Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 21
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 09:30:18.485966 lava-dispatcher, installed at version: 2024.03
2 09:30:18.486156 start: 0 validate
3 09:30:18.486287 Start time: 2024-06-18 09:30:18.486280+00:00 (UTC)
4 09:30:18.486404 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:30:18.486534 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:30:18.778379 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:30:18.779096 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:30:19.039665 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:30:19.040349 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:30:19.308787 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:30:19.309499 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:30:19.577228 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:30:19.577925 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:30:19.845488 validate duration: 1.36
16 09:30:19.846654 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:30:19.847145 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:30:19.847582 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:30:19.848131 Not decompressing ramdisk as can be used compressed.
20 09:30:19.848603 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 09:30:19.848950 saving as /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/ramdisk/initrd.cpio.gz
22 09:30:19.849285 total size: 5628169 (5 MB)
23 09:30:19.856093 progress 0 % (0 MB)
24 09:30:19.864681 progress 5 % (0 MB)
25 09:30:19.871088 progress 10 % (0 MB)
26 09:30:19.875213 progress 15 % (0 MB)
27 09:30:19.879044 progress 20 % (1 MB)
28 09:30:19.882064 progress 25 % (1 MB)
29 09:30:19.884945 progress 30 % (1 MB)
30 09:30:19.887699 progress 35 % (1 MB)
31 09:30:19.889836 progress 40 % (2 MB)
32 09:30:19.892204 progress 45 % (2 MB)
33 09:30:19.894146 progress 50 % (2 MB)
34 09:30:19.896228 progress 55 % (2 MB)
35 09:30:19.898263 progress 60 % (3 MB)
36 09:30:19.899929 progress 65 % (3 MB)
37 09:30:19.901795 progress 70 % (3 MB)
38 09:30:19.903391 progress 75 % (4 MB)
39 09:30:19.905073 progress 80 % (4 MB)
40 09:30:19.906570 progress 85 % (4 MB)
41 09:30:19.908207 progress 90 % (4 MB)
42 09:30:19.909743 progress 95 % (5 MB)
43 09:30:19.911133 progress 100 % (5 MB)
44 09:30:19.911342 5 MB downloaded in 0.06 s (86.47 MB/s)
45 09:30:19.911496 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:30:19.911740 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:30:19.911827 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:30:19.911912 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:30:19.912045 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:30:19.912118 saving as /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/kernel/Image
52 09:30:19.912179 total size: 54813184 (52 MB)
53 09:30:19.912241 No compression specified
54 09:30:19.913375 progress 0 % (0 MB)
55 09:30:19.927025 progress 5 % (2 MB)
56 09:30:19.940610 progress 10 % (5 MB)
57 09:30:19.954021 progress 15 % (7 MB)
58 09:30:19.967746 progress 20 % (10 MB)
59 09:30:19.981497 progress 25 % (13 MB)
60 09:30:19.995001 progress 30 % (15 MB)
61 09:30:20.008632 progress 35 % (18 MB)
62 09:30:20.022197 progress 40 % (20 MB)
63 09:30:20.035603 progress 45 % (23 MB)
64 09:30:20.049231 progress 50 % (26 MB)
65 09:30:20.062641 progress 55 % (28 MB)
66 09:30:20.075914 progress 60 % (31 MB)
67 09:30:20.089522 progress 65 % (34 MB)
68 09:30:20.102899 progress 70 % (36 MB)
69 09:30:20.116441 progress 75 % (39 MB)
70 09:30:20.129858 progress 80 % (41 MB)
71 09:30:20.142989 progress 85 % (44 MB)
72 09:30:20.156433 progress 90 % (47 MB)
73 09:30:20.169801 progress 95 % (49 MB)
74 09:30:20.182864 progress 100 % (52 MB)
75 09:30:20.183082 52 MB downloaded in 0.27 s (192.97 MB/s)
76 09:30:20.183225 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:30:20.183452 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:30:20.183537 start: 1.3 download-retry (timeout 00:10:00) [common]
80 09:30:20.183620 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 09:30:20.183747 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:30:20.183814 saving as /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/dtb/mt8192-asurada-spherion-r0.dtb
83 09:30:20.183874 total size: 47258 (0 MB)
84 09:30:20.183936 No compression specified
85 09:30:20.185227 progress 69 % (0 MB)
86 09:30:20.185536 progress 100 % (0 MB)
87 09:30:20.185691 0 MB downloaded in 0.00 s (24.85 MB/s)
88 09:30:20.185810 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:30:20.186029 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:30:20.186113 start: 1.4 download-retry (timeout 00:10:00) [common]
92 09:30:20.186194 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 09:30:20.186330 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 09:30:20.186396 saving as /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/nfsrootfs/full.rootfs.tar
95 09:30:20.186456 total size: 120894716 (115 MB)
96 09:30:20.186517 Using unxz to decompress xz
97 09:30:20.190041 progress 0 % (0 MB)
98 09:30:20.531773 progress 5 % (5 MB)
99 09:30:20.889990 progress 10 % (11 MB)
100 09:30:21.239139 progress 15 % (17 MB)
101 09:30:21.562183 progress 20 % (23 MB)
102 09:30:21.852723 progress 25 % (28 MB)
103 09:30:22.207410 progress 30 % (34 MB)
104 09:30:22.540252 progress 35 % (40 MB)
105 09:30:22.703455 progress 40 % (46 MB)
106 09:30:22.878941 progress 45 % (51 MB)
107 09:30:23.185095 progress 50 % (57 MB)
108 09:30:23.554891 progress 55 % (63 MB)
109 09:30:23.893273 progress 60 % (69 MB)
110 09:30:24.230916 progress 65 % (74 MB)
111 09:30:24.570950 progress 70 % (80 MB)
112 09:30:24.923304 progress 75 % (86 MB)
113 09:30:25.262337 progress 80 % (92 MB)
114 09:30:25.598238 progress 85 % (98 MB)
115 09:30:25.951215 progress 90 % (103 MB)
116 09:30:26.278554 progress 95 % (109 MB)
117 09:30:26.632965 progress 100 % (115 MB)
118 09:30:26.638444 115 MB downloaded in 6.45 s (17.87 MB/s)
119 09:30:26.638696 end: 1.4.1 http-download (duration 00:00:06) [common]
121 09:30:26.638974 end: 1.4 download-retry (duration 00:00:06) [common]
122 09:30:26.639070 start: 1.5 download-retry (timeout 00:09:53) [common]
123 09:30:26.639157 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 09:30:26.639301 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:30:26.639373 saving as /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/modules/modules.tar
126 09:30:26.639435 total size: 8619356 (8 MB)
127 09:30:26.639499 Using unxz to decompress xz
128 09:30:26.643412 progress 0 % (0 MB)
129 09:30:26.662867 progress 5 % (0 MB)
130 09:30:26.687205 progress 10 % (0 MB)
131 09:30:26.712383 progress 15 % (1 MB)
132 09:30:26.737766 progress 20 % (1 MB)
133 09:30:26.763229 progress 25 % (2 MB)
134 09:30:26.788282 progress 30 % (2 MB)
135 09:30:26.812944 progress 35 % (2 MB)
136 09:30:26.836959 progress 40 % (3 MB)
137 09:30:26.861212 progress 45 % (3 MB)
138 09:30:26.884917 progress 50 % (4 MB)
139 09:30:26.909421 progress 55 % (4 MB)
140 09:30:26.933337 progress 60 % (4 MB)
141 09:30:26.956703 progress 65 % (5 MB)
142 09:30:26.984377 progress 70 % (5 MB)
143 09:30:27.009252 progress 75 % (6 MB)
144 09:30:27.032212 progress 80 % (6 MB)
145 09:30:27.055315 progress 85 % (7 MB)
146 09:30:27.078411 progress 90 % (7 MB)
147 09:30:27.106244 progress 95 % (7 MB)
148 09:30:27.139729 progress 100 % (8 MB)
149 09:30:27.144485 8 MB downloaded in 0.51 s (16.28 MB/s)
150 09:30:27.144767 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:30:27.145031 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:30:27.145126 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 09:30:27.145217 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 09:30:30.354079 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14407671/extract-nfsrootfs-tqnv2l7u
156 09:30:30.354282 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 09:30:30.354385 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 09:30:30.354551 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t
159 09:30:30.354673 makedir: /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin
160 09:30:30.354770 makedir: /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/tests
161 09:30:30.354864 makedir: /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/results
162 09:30:30.354961 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-add-keys
163 09:30:30.355093 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-add-sources
164 09:30:30.355213 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-background-process-start
165 09:30:30.355331 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-background-process-stop
166 09:30:30.355447 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-common-functions
167 09:30:30.355562 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-echo-ipv4
168 09:30:30.355681 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-install-packages
169 09:30:30.355795 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-installed-packages
170 09:30:30.355908 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-os-build
171 09:30:30.356021 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-probe-channel
172 09:30:30.356136 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-probe-ip
173 09:30:30.356249 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-target-ip
174 09:30:30.356361 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-target-mac
175 09:30:30.356473 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-target-storage
176 09:30:30.356621 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-test-case
177 09:30:30.356749 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-test-event
178 09:30:30.356862 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-test-feedback
179 09:30:30.356975 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-test-raise
180 09:30:30.357087 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-test-reference
181 09:30:30.357210 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-test-runner
182 09:30:30.357325 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-test-set
183 09:30:30.357438 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-test-shell
184 09:30:30.357552 Updating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-add-keys (debian)
185 09:30:30.357694 Updating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-add-sources (debian)
186 09:30:30.357832 Updating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-install-packages (debian)
187 09:30:30.357960 Updating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-installed-packages (debian)
188 09:30:30.358094 Updating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/bin/lava-os-build (debian)
189 09:30:30.358211 Creating /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/environment
190 09:30:30.358305 LAVA metadata
191 09:30:30.358368 - LAVA_JOB_ID=14407671
192 09:30:30.358429 - LAVA_DISPATCHER_IP=192.168.201.1
193 09:30:30.358524 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 09:30:30.358587 skipped lava-vland-overlay
195 09:30:30.358656 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 09:30:30.358731 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 09:30:30.358789 skipped lava-multinode-overlay
198 09:30:30.358857 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 09:30:30.358931 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 09:30:30.359000 Loading test definitions
201 09:30:30.359084 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 09:30:30.359152 Using /lava-14407671 at stage 0
203 09:30:30.359411 uuid=14407671_1.6.2.3.1 testdef=None
204 09:30:30.359496 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 09:30:30.359576 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 09:30:30.360002 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 09:30:30.360218 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 09:30:30.360910 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 09:30:30.361136 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 09:30:30.361647 runner path: /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/0/tests/0_timesync-off test_uuid 14407671_1.6.2.3.1
213 09:30:30.361797 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 09:30:30.362015 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 09:30:30.362085 Using /lava-14407671 at stage 0
217 09:30:30.362177 Fetching tests from https://github.com/kernelci/test-definitions.git
218 09:30:30.362261 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/0/tests/1_kselftest-rtc'
219 09:30:32.300278 Running '/usr/bin/git checkout kernelci.org
220 09:30:32.445104 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 09:30:32.445814 uuid=14407671_1.6.2.3.5 testdef=None
222 09:30:32.445970 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 09:30:32.446218 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 09:30:32.446946 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 09:30:32.447170 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 09:30:32.448127 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 09:30:32.448364 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 09:30:32.449312 runner path: /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/0/tests/1_kselftest-rtc test_uuid 14407671_1.6.2.3.5
232 09:30:32.449402 BOARD='mt8192-asurada-spherion-r0'
233 09:30:32.449467 BRANCH='cip'
234 09:30:32.449528 SKIPFILE='/dev/null'
235 09:30:32.449587 SKIP_INSTALL='True'
236 09:30:32.449643 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 09:30:32.449700 TST_CASENAME=''
238 09:30:32.449754 TST_CMDFILES='rtc'
239 09:30:32.449893 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 09:30:32.450094 Creating lava-test-runner.conf files
242 09:30:32.450157 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407671/lava-overlay-0ln6lx3t/lava-14407671/0 for stage 0
243 09:30:32.450246 - 0_timesync-off
244 09:30:32.450313 - 1_kselftest-rtc
245 09:30:32.450404 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 09:30:32.450491 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 09:30:39.960035 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 09:30:39.960192 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:40) [common]
249 09:30:39.960288 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 09:30:39.960389 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 09:30:39.960476 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:40) [common]
252 09:30:40.117362 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 09:30:40.117737 start: 1.6.4 extract-modules (timeout 00:09:40) [common]
254 09:30:40.117851 extracting modules file /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407671/extract-nfsrootfs-tqnv2l7u
255 09:30:40.317166 extracting modules file /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407671/extract-overlay-ramdisk-iq6wuknk/ramdisk
256 09:30:40.521744 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 09:30:40.521918 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 09:30:40.522021 [common] Applying overlay to NFS
259 09:30:40.522095 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407671/compress-overlay-vqk2_as9/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407671/extract-nfsrootfs-tqnv2l7u
260 09:30:41.417521 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 09:30:41.417700 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 09:30:41.417795 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 09:30:41.417885 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 09:30:41.417965 Building ramdisk /var/lib/lava/dispatcher/tmp/14407671/extract-overlay-ramdisk-iq6wuknk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407671/extract-overlay-ramdisk-iq6wuknk/ramdisk
265 09:30:41.738296 >> 130466 blocks
266 09:30:43.754918 rename /var/lib/lava/dispatcher/tmp/14407671/extract-overlay-ramdisk-iq6wuknk/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/ramdisk/ramdisk.cpio.gz
267 09:30:43.755367 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 09:30:43.755489 start: 1.6.8 prepare-kernel (timeout 00:09:36) [common]
269 09:30:43.755593 start: 1.6.8.1 prepare-fit (timeout 00:09:36) [common]
270 09:30:43.755752 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/kernel/Image']
271 09:30:56.875994 Returned 0 in 13 seconds
272 09:30:56.976985 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/kernel/image.itb
273 09:30:57.328582 output: FIT description: Kernel Image image with one or more FDT blobs
274 09:30:57.328963 output: Created: Tue Jun 18 10:30:57 2024
275 09:30:57.329054 output: Image 0 (kernel-1)
276 09:30:57.329149 output: Description:
277 09:30:57.329247 output: Created: Tue Jun 18 10:30:57 2024
278 09:30:57.329313 output: Type: Kernel Image
279 09:30:57.329375 output: Compression: lzma compressed
280 09:30:57.329442 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
281 09:30:57.329501 output: Architecture: AArch64
282 09:30:57.329558 output: OS: Linux
283 09:30:57.329615 output: Load Address: 0x00000000
284 09:30:57.329688 output: Entry Point: 0x00000000
285 09:30:57.329748 output: Hash algo: crc32
286 09:30:57.329811 output: Hash value: 4137a6e7
287 09:30:57.329866 output: Image 1 (fdt-1)
288 09:30:57.329931 output: Description: mt8192-asurada-spherion-r0
289 09:30:57.329987 output: Created: Tue Jun 18 10:30:57 2024
290 09:30:57.330041 output: Type: Flat Device Tree
291 09:30:57.330094 output: Compression: uncompressed
292 09:30:57.330153 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 09:30:57.330207 output: Architecture: AArch64
294 09:30:57.330260 output: Hash algo: crc32
295 09:30:57.330312 output: Hash value: 0f8e4d2e
296 09:30:57.330365 output: Image 2 (ramdisk-1)
297 09:30:57.330424 output: Description: unavailable
298 09:30:57.330477 output: Created: Tue Jun 18 10:30:57 2024
299 09:30:57.330530 output: Type: RAMDisk Image
300 09:30:57.330583 output: Compression: Unknown Compression
301 09:30:57.330642 output: Data Size: 18749230 Bytes = 18309.79 KiB = 17.88 MiB
302 09:30:57.330697 output: Architecture: AArch64
303 09:30:57.330749 output: OS: Linux
304 09:30:57.330802 output: Load Address: unavailable
305 09:30:57.330854 output: Entry Point: unavailable
306 09:30:57.330914 output: Hash algo: crc32
307 09:30:57.330967 output: Hash value: 51af1195
308 09:30:57.331019 output: Default Configuration: 'conf-1'
309 09:30:57.331072 output: Configuration 0 (conf-1)
310 09:30:57.331124 output: Description: mt8192-asurada-spherion-r0
311 09:30:57.331183 output: Kernel: kernel-1
312 09:30:57.331236 output: Init Ramdisk: ramdisk-1
313 09:30:57.331288 output: FDT: fdt-1
314 09:30:57.331340 output: Loadables: kernel-1
315 09:30:57.331398 output:
316 09:30:57.331594 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 09:30:57.331695 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 09:30:57.331799 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 09:30:57.331899 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:23) [common]
320 09:30:57.331979 No LXC device requested
321 09:30:57.332056 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 09:30:57.332149 start: 1.8 deploy-device-env (timeout 00:09:23) [common]
323 09:30:57.332229 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 09:30:57.332300 Checking files for TFTP limit of 4294967296 bytes.
325 09:30:57.332840 end: 1 tftp-deploy (duration 00:00:37) [common]
326 09:30:57.332957 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 09:30:57.333051 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 09:30:57.333180 substitutions:
329 09:30:57.333250 - {DTB}: 14407671/tftp-deploy-gyn3kd_t/dtb/mt8192-asurada-spherion-r0.dtb
330 09:30:57.333315 - {INITRD}: 14407671/tftp-deploy-gyn3kd_t/ramdisk/ramdisk.cpio.gz
331 09:30:57.333382 - {KERNEL}: 14407671/tftp-deploy-gyn3kd_t/kernel/Image
332 09:30:57.333441 - {LAVA_MAC}: None
333 09:30:57.333498 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14407671/extract-nfsrootfs-tqnv2l7u
334 09:30:57.333554 - {NFS_SERVER_IP}: 192.168.201.1
335 09:30:57.333616 - {PRESEED_CONFIG}: None
336 09:30:57.333671 - {PRESEED_LOCAL}: None
337 09:30:57.333726 - {RAMDISK}: 14407671/tftp-deploy-gyn3kd_t/ramdisk/ramdisk.cpio.gz
338 09:30:57.333780 - {ROOT_PART}: None
339 09:30:57.333834 - {ROOT}: None
340 09:30:57.333895 - {SERVER_IP}: 192.168.201.1
341 09:30:57.333948 - {TEE}: None
342 09:30:57.334002 Parsed boot commands:
343 09:30:57.334055 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 09:30:57.334237 Parsed boot commands: tftpboot 192.168.201.1 14407671/tftp-deploy-gyn3kd_t/kernel/image.itb 14407671/tftp-deploy-gyn3kd_t/kernel/cmdline
345 09:30:57.334325 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 09:30:57.334419 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 09:30:57.334512 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 09:30:57.334601 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 09:30:57.334676 Not connected, no need to disconnect.
350 09:30:57.334750 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 09:30:57.334837 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 09:30:57.334908 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-1'
353 09:30:57.338083 Setting prompt string to ['lava-test: # ']
354 09:30:57.338466 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 09:30:57.338576 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 09:30:57.338683 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 09:30:57.338778 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 09:30:57.338958 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-1']
359 09:31:11.002402 Returned 0 in 13 seconds
360 09:31:11.103475 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 09:31:11.105008 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 09:31:11.105576 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 09:31:11.106073 Setting prompt string to 'Starting depthcharge on Spherion...'
365 09:31:11.106496 Changing prompt to 'Starting depthcharge on Spherion...'
366 09:31:11.106936 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 09:31:11.108191 [Enter `^Ec?' for help]
368 09:31:11.108279
369 09:31:11.108384
370 09:31:11.108489 F0: 102B 0000
371 09:31:11.108619
372 09:31:11.108701 F3: 1001 0000 [0200]
373 09:31:11.108781
374 09:31:11.108880 F3: 1001 0000
375 09:31:11.108978
376 09:31:11.109073 F7: 102D 0000
377 09:31:11.109169
378 09:31:11.109263 F1: 0000 0000
379 09:31:11.109359
380 09:31:11.109454 V0: 0000 0000 [0001]
381 09:31:11.109548
382 09:31:11.109641 00: 0007 8000
383 09:31:11.109740
384 09:31:11.109834 01: 0000 0000
385 09:31:11.109929
386 09:31:11.110023 BP: 0C00 0209 [0000]
387 09:31:11.110117
388 09:31:11.110210 G0: 1182 0000
389 09:31:11.110303
390 09:31:11.110395 EC: 0000 0021 [4000]
391 09:31:11.110488
392 09:31:11.110592 S7: 0000 0000 [0000]
393 09:31:11.110710
394 09:31:11.110811 CC: 0000 0000 [0001]
395 09:31:11.110908
396 09:31:11.111003 T0: 0000 0040 [010F]
397 09:31:11.111098
398 09:31:11.111191 Jump to BL
399 09:31:11.111285
400 09:31:11.111379
401 09:31:11.111471
402 09:31:11.111566 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 09:31:11.111664 ARM64: Exception handlers installed.
404 09:31:11.111759 ARM64: Testing exception
405 09:31:11.111852 ARM64: Done test exception
406 09:31:11.111947 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 09:31:11.112043 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 09:31:11.112138 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 09:31:11.112234 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 09:31:11.112329 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 09:31:11.112424 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 09:31:11.112519 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 09:31:11.112657 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 09:31:11.112753 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 09:31:11.112847 WDT: Last reset was cold boot
416 09:31:11.112941 SPI1(PAD0) initialized at 2873684 Hz
417 09:31:11.113034 SPI5(PAD0) initialized at 992727 Hz
418 09:31:11.113127 VBOOT: Loading verstage.
419 09:31:11.113221 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 09:31:11.113315 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 09:31:11.113409 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 09:31:11.113504 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 09:31:11.113599 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 09:31:11.113694 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 09:31:11.113788 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
426 09:31:11.113881
427 09:31:11.113998
428 09:31:11.114106 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 09:31:11.114200 ARM64: Exception handlers installed.
430 09:31:11.114293 ARM64: Testing exception
431 09:31:11.114386 ARM64: Done test exception
432 09:31:11.114480 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 09:31:11.114574 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 09:31:11.114668 Probing TPM: . done!
435 09:31:11.114760 TPM ready after 0 ms
436 09:31:11.114854 Connected to device vid:did:rid of 1ae0:0028:00
437 09:31:11.114949 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
438 09:31:11.115044 Initialized TPM device CR50 revision 0
439 09:31:11.115137 tlcl_send_startup: Startup return code is 0
440 09:31:11.115230 TPM: setup succeeded
441 09:31:11.115324 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 09:31:11.115418 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 09:31:11.115513 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 09:31:11.115607 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 09:31:11.115701 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 09:31:11.115795 in-header: 03 07 00 00 08 00 00 00
447 09:31:11.115888 in-data: aa e4 47 04 13 02 00 00
448 09:31:11.115980 Chrome EC: UHEPI supported
449 09:31:11.116074 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 09:31:11.116168 in-header: 03 a9 00 00 08 00 00 00
451 09:31:11.116261 in-data: 84 60 60 08 00 00 00 00
452 09:31:11.116354 Phase 1
453 09:31:11.116448 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 09:31:11.116542 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 09:31:11.116673 VB2:vb2_check_recovery() Recovery was requested manually
456 09:31:11.116767 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 09:31:11.116861 Recovery requested (1009000e)
458 09:31:11.116954 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 09:31:11.117047 tlcl_extend: response is 0
460 09:31:11.117142 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 09:31:11.117235 tlcl_extend: response is 0
462 09:31:11.117362 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 09:31:11.117456 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 09:31:11.117551 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 09:31:11.117644
466 09:31:11.117736
467 09:31:11.117830 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 09:31:11.117924 ARM64: Exception handlers installed.
469 09:31:11.118017 ARM64: Testing exception
470 09:31:11.118110 ARM64: Done test exception
471 09:31:11.118203 pmic_efuse_setting: Set efuses in 11 msecs
472 09:31:11.118296 pmwrap_interface_init: Select PMIF_VLD_RDY
473 09:31:11.118390 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 09:31:11.118484 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 09:31:11.118770 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 09:31:11.118871 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 09:31:11.118969 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 09:31:11.119050 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 09:31:11.119126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 09:31:11.119216 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 09:31:11.119303 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 09:31:11.119376 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 09:31:11.119470 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 09:31:11.119563 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 09:31:11.119656 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 09:31:11.119749 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 09:31:11.119842 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 09:31:11.119936 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 09:31:11.120029 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 09:31:11.120121 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 09:31:11.120213 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 09:31:11.120306 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 09:31:11.120398 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 09:31:11.120491 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 09:31:11.120622 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 09:31:11.120716 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 09:31:11.120810 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 09:31:11.120902 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 09:31:11.120995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 09:31:11.121088 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 09:31:11.121181 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 09:31:11.121274 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 09:31:11.121367 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 09:31:11.121460 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 09:31:11.121553 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 09:31:11.121646 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 09:31:11.121738 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 09:31:11.121830 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 09:31:11.121923 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 09:31:11.122015 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 09:31:11.122108 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 09:31:11.122200 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 09:31:11.122292 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 09:31:11.122385 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 09:31:11.122478 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 09:31:11.122570 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 09:31:11.122661 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 09:31:11.122753 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 09:31:11.122844 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 09:31:11.122937 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 09:31:11.123029 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 09:31:11.123121 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 09:31:11.123213 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 09:31:11.123305 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 09:31:11.123399 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 09:31:11.123492 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 09:31:11.123585 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 09:31:11.123678 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 09:31:11.123771 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 09:31:11.123864 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 09:31:11.123956 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 09:31:11.124048 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x2d
533 09:31:11.124141 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 09:31:11.124233 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 09:31:11.124325 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 09:31:11.124417 [RTC]rtc_get_frequency_meter,154: input=15, output=772
537 09:31:11.124510 [RTC]rtc_get_frequency_meter,154: input=23, output=957
538 09:31:11.124638 [RTC]rtc_get_frequency_meter,154: input=19, output=865
539 09:31:11.124731 [RTC]rtc_get_frequency_meter,154: input=17, output=816
540 09:31:11.124823 [RTC]rtc_get_frequency_meter,154: input=16, output=794
541 09:31:11.124915 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
542 09:31:11.125007 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
543 09:31:11.125099 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
544 09:31:11.125191 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
545 09:31:11.125475 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
546 09:31:11.125570 ADC[4]: Raw value=901770 ID=7
547 09:31:11.125666 ADC[3]: Raw value=213179 ID=1
548 09:31:11.125760 RAM Code: 0x71
549 09:31:11.125855 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
550 09:31:11.125949 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
551 09:31:11.126044 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
552 09:31:11.126138 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
553 09:31:11.126231 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
554 09:31:11.126325 in-header: 03 07 00 00 08 00 00 00
555 09:31:11.126418 in-data: aa e4 47 04 13 02 00 00
556 09:31:11.126511 Chrome EC: UHEPI supported
557 09:31:11.126603 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
558 09:31:11.126696 in-header: 03 a9 00 00 08 00 00 00
559 09:31:11.126789 in-data: 84 60 60 08 00 00 00 00
560 09:31:11.126880 MRC: failed to locate region type 0.
561 09:31:11.126973 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
562 09:31:11.127066 DRAM-K: Running full calibration
563 09:31:11.127159 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
564 09:31:11.127251 header.status = 0x0
565 09:31:11.127343 header.version = 0x6 (expected: 0x6)
566 09:31:11.127435 header.size = 0xd00 (expected: 0xd00)
567 09:31:11.127528 header.flags = 0x0
568 09:31:11.127620 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
569 09:31:11.127713 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
570 09:31:11.127806 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
571 09:31:11.127898 dram_init: ddr_geometry: 2
572 09:31:11.127990 [EMI] MDL number = 2
573 09:31:11.128083 [EMI] Get MDL freq = 0
574 09:31:11.128175 dram_init: ddr_type: 0
575 09:31:11.128267 is_discrete_lpddr4: 1
576 09:31:11.128359 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
577 09:31:11.128450
578 09:31:11.128543
579 09:31:11.128708 [Bian_co] ETT version 0.0.0.1
580 09:31:11.128802 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
581 09:31:11.128895
582 09:31:11.128987 dramc_set_vcore_voltage set vcore to 650000
583 09:31:11.129081 Read voltage for 800, 4
584 09:31:11.129173 Vio18 = 0
585 09:31:11.129265 Vcore = 650000
586 09:31:11.129358 Vdram = 0
587 09:31:11.129450 Vddq = 0
588 09:31:11.129542 Vmddr = 0
589 09:31:11.129638 dram_init: config_dvfs: 1
590 09:31:11.129731 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
591 09:31:11.129824 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
592 09:31:11.129923 [SwImpedanceCal] DRVP=10, DRVN=17, ODTN=9
593 09:31:11.130016 freq_region=0, Reg: DRVP=10, DRVN=17, ODTN=9
594 09:31:11.130112 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
595 09:31:11.130207 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
596 09:31:11.130305 MEM_TYPE=3, freq_sel=18
597 09:31:11.130398 sv_algorithm_assistance_LP4_1600
598 09:31:11.130490 ============ PULL DRAM RESETB DOWN ============
599 09:31:11.130585 ========== PULL DRAM RESETB DOWN end =========
600 09:31:11.130678 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
601 09:31:11.130771 ===================================
602 09:31:11.130864 LPDDR4 DRAM CONFIGURATION
603 09:31:11.130956 ===================================
604 09:31:11.131048 EX_ROW_EN[0] = 0x0
605 09:31:11.131140 EX_ROW_EN[1] = 0x0
606 09:31:11.131261 LP4Y_EN = 0x0
607 09:31:11.131353 WORK_FSP = 0x0
608 09:31:11.131454 WL = 0x2
609 09:31:11.131546 RL = 0x2
610 09:31:11.131638 BL = 0x2
611 09:31:11.131729 RPST = 0x0
612 09:31:11.131821 RD_PRE = 0x0
613 09:31:11.131913 WR_PRE = 0x1
614 09:31:11.132005 WR_PST = 0x0
615 09:31:11.132096 DBI_WR = 0x0
616 09:31:11.132187 DBI_RD = 0x0
617 09:31:11.132279 OTF = 0x1
618 09:31:11.132371 ===================================
619 09:31:11.132465 ===================================
620 09:31:11.132580 ANA top config
621 09:31:11.132687 ===================================
622 09:31:11.132780 DLL_ASYNC_EN = 0
623 09:31:11.132876 ALL_SLAVE_EN = 1
624 09:31:11.132948 NEW_RANK_MODE = 1
625 09:31:11.133021 DLL_IDLE_MODE = 1
626 09:31:11.133093 LP45_APHY_COMB_EN = 1
627 09:31:11.133165 TX_ODT_DIS = 1
628 09:31:11.133258 NEW_8X_MODE = 1
629 09:31:11.133352 ===================================
630 09:31:11.133445 ===================================
631 09:31:11.133538 data_rate = 1600
632 09:31:11.133631 CKR = 1
633 09:31:11.133722 DQ_P2S_RATIO = 8
634 09:31:11.133815 ===================================
635 09:31:11.133907 CA_P2S_RATIO = 8
636 09:31:11.133998 DQ_CA_OPEN = 0
637 09:31:11.134090 DQ_SEMI_OPEN = 0
638 09:31:11.134182 CA_SEMI_OPEN = 0
639 09:31:11.134273 CA_FULL_RATE = 0
640 09:31:11.134364 DQ_CKDIV4_EN = 1
641 09:31:11.134456 CA_CKDIV4_EN = 1
642 09:31:11.134547 CA_PREDIV_EN = 0
643 09:31:11.134674 PH8_DLY = 0
644 09:31:11.134766 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
645 09:31:11.134857 DQ_AAMCK_DIV = 4
646 09:31:11.134948 CA_AAMCK_DIV = 4
647 09:31:11.135043 CA_ADMCK_DIV = 4
648 09:31:11.135164 DQ_TRACK_CA_EN = 0
649 09:31:11.135257 CA_PICK = 800
650 09:31:11.135349 CA_MCKIO = 800
651 09:31:11.135444 MCKIO_SEMI = 0
652 09:31:11.135540 PLL_FREQ = 3068
653 09:31:11.135635 DQ_UI_PI_RATIO = 32
654 09:31:11.135727 CA_UI_PI_RATIO = 0
655 09:31:11.135819 ===================================
656 09:31:11.135911 ===================================
657 09:31:11.136003 memory_type:LPDDR4
658 09:31:11.136095 GP_NUM : 10
659 09:31:11.136186 SRAM_EN : 1
660 09:31:11.136278 MD32_EN : 0
661 09:31:11.136370 ===================================
662 09:31:11.136462 [ANA_INIT] >>>>>>>>>>>>>>
663 09:31:11.136559 <<<<<< [CONFIGURE PHASE]: ANA_TX
664 09:31:11.136655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
665 09:31:11.136748 ===================================
666 09:31:11.137055 data_rate = 1600,PCW = 0X7600
667 09:31:11.137152 ===================================
668 09:31:11.137228 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
669 09:31:11.137303 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
670 09:31:11.137378 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
671 09:31:11.137473 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
672 09:31:11.137567 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
673 09:31:11.137661 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
674 09:31:11.137754 [ANA_INIT] flow start
675 09:31:11.137847 [ANA_INIT] PLL >>>>>>>>
676 09:31:11.137939 [ANA_INIT] PLL <<<<<<<<
677 09:31:11.138032 [ANA_INIT] MIDPI >>>>>>>>
678 09:31:11.138125 [ANA_INIT] MIDPI <<<<<<<<
679 09:31:11.138217 [ANA_INIT] DLL >>>>>>>>
680 09:31:11.138309 [ANA_INIT] flow end
681 09:31:11.138400 ============ LP4 DIFF to SE enter ============
682 09:31:11.138494 ============ LP4 DIFF to SE exit ============
683 09:31:11.138587 [ANA_INIT] <<<<<<<<<<<<<
684 09:31:11.138679 [Flow] Enable top DCM control >>>>>
685 09:31:11.138771 [Flow] Enable top DCM control <<<<<
686 09:31:11.138864 Enable DLL master slave shuffle
687 09:31:11.138956 ==============================================================
688 09:31:11.139049 Gating Mode config
689 09:31:11.139168 ==============================================================
690 09:31:11.139277 Config description:
691 09:31:11.139387 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
692 09:31:11.139483 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
693 09:31:11.139578 SELPH_MODE 0: By rank 1: By Phase
694 09:31:11.139678 ==============================================================
695 09:31:11.139791 GAT_TRACK_EN = 1
696 09:31:11.139890 RX_GATING_MODE = 2
697 09:31:11.139984 RX_GATING_TRACK_MODE = 2
698 09:31:11.140077 SELPH_MODE = 1
699 09:31:11.140170 PICG_EARLY_EN = 1
700 09:31:11.140262 VALID_LAT_VALUE = 1
701 09:31:11.140354 ==============================================================
702 09:31:11.140447 Enter into Gating configuration >>>>
703 09:31:11.140540 Exit from Gating configuration <<<<
704 09:31:11.140673 Enter into DVFS_PRE_config >>>>>
705 09:31:11.140768 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
706 09:31:11.140867 Exit from DVFS_PRE_config <<<<<
707 09:31:11.140961 Enter into PICG configuration >>>>
708 09:31:11.141071 Exit from PICG configuration <<<<
709 09:31:11.141169 [RX_INPUT] configuration >>>>>
710 09:31:11.141319 [RX_INPUT] configuration <<<<<
711 09:31:11.141414 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
712 09:31:11.141509 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
713 09:31:11.141608 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
714 09:31:11.141706 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
715 09:31:11.141809 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
716 09:31:11.141902 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
717 09:31:11.142008 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
718 09:31:11.142102 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
719 09:31:11.142196 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
720 09:31:11.142289 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
721 09:31:11.142381 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
722 09:31:11.142474 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
723 09:31:11.142567 ===================================
724 09:31:11.142660 LPDDR4 DRAM CONFIGURATION
725 09:31:11.142753 ===================================
726 09:31:11.142846 EX_ROW_EN[0] = 0x0
727 09:31:11.142938 EX_ROW_EN[1] = 0x0
728 09:31:11.143030 LP4Y_EN = 0x0
729 09:31:11.143123 WORK_FSP = 0x0
730 09:31:11.143216 WL = 0x2
731 09:31:11.143338 RL = 0x2
732 09:31:11.143430 BL = 0x2
733 09:31:11.143523 RPST = 0x0
734 09:31:11.143614 RD_PRE = 0x0
735 09:31:11.143706 WR_PRE = 0x1
736 09:31:11.143798 WR_PST = 0x0
737 09:31:11.143890 DBI_WR = 0x0
738 09:31:11.143982 DBI_RD = 0x0
739 09:31:11.144074 OTF = 0x1
740 09:31:11.144166 ===================================
741 09:31:11.144278 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
742 09:31:11.144386 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
743 09:31:11.144509 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
744 09:31:11.144627 ===================================
745 09:31:11.144722 LPDDR4 DRAM CONFIGURATION
746 09:31:11.144816 ===================================
747 09:31:11.144909 EX_ROW_EN[0] = 0x10
748 09:31:11.145002 EX_ROW_EN[1] = 0x0
749 09:31:11.145131 LP4Y_EN = 0x0
750 09:31:11.145236 WORK_FSP = 0x0
751 09:31:11.145341 WL = 0x2
752 09:31:11.145448 RL = 0x2
753 09:31:11.145560 BL = 0x2
754 09:31:11.145656 RPST = 0x0
755 09:31:11.145750 RD_PRE = 0x0
756 09:31:11.145848 WR_PRE = 0x1
757 09:31:11.145941 WR_PST = 0x0
758 09:31:11.146034 DBI_WR = 0x0
759 09:31:11.146131 DBI_RD = 0x0
760 09:31:11.146224 OTF = 0x1
761 09:31:11.146321 ===================================
762 09:31:11.146474 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
763 09:31:11.146570 nWR fixed to 40
764 09:31:11.146679 [ModeRegInit_LP4] CH0 RK0
765 09:31:11.146773 [ModeRegInit_LP4] CH0 RK1
766 09:31:11.146869 [ModeRegInit_LP4] CH1 RK0
767 09:31:11.146962 [ModeRegInit_LP4] CH1 RK1
768 09:31:11.147074 match AC timing 13
769 09:31:11.147196 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
770 09:31:11.147289 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
771 09:31:11.147396 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
772 09:31:11.147533 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
773 09:31:11.147852 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
774 09:31:11.147962 [EMI DOE] emi_dcm 0
775 09:31:11.148059 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
776 09:31:11.148171 ==
777 09:31:11.148299 Dram Type= 6, Freq= 0, CH_0, rank 0
778 09:31:11.148399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 09:31:11.148500 ==
780 09:31:11.148612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
781 09:31:11.148715 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
782 09:31:11.148867 [CA 0] Center 38 (7~69) winsize 63
783 09:31:11.148990 [CA 1] Center 38 (7~69) winsize 63
784 09:31:11.149086 [CA 2] Center 35 (5~66) winsize 62
785 09:31:11.149181 [CA 3] Center 35 (5~66) winsize 62
786 09:31:11.149276 [CA 4] Center 35 (4~66) winsize 63
787 09:31:11.149370 [CA 5] Center 33 (3~64) winsize 62
788 09:31:11.149477
789 09:31:11.149569 [CmdBusTrainingLP45] Vref(ca) range 1: 32
790 09:31:11.149663
791 09:31:11.149756 [CATrainingPosCal] consider 1 rank data
792 09:31:11.149850 u2DelayCellTimex100 = 270/100 ps
793 09:31:11.149942 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
794 09:31:11.150036 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
795 09:31:11.150128 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
796 09:31:11.150221 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
797 09:31:11.150313 CA4 delay=35 (4~66),Diff = 2 PI (14 cell)
798 09:31:11.150405 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
799 09:31:11.150497
800 09:31:11.150589 CA PerBit enable=1, Macro0, CA PI delay=33
801 09:31:11.150682
802 09:31:11.150774 [CBTSetCACLKResult] CA Dly = 33
803 09:31:11.150866 CS Dly: 5 (0~36)
804 09:31:11.150986 ==
805 09:31:11.151079 Dram Type= 6, Freq= 0, CH_0, rank 1
806 09:31:11.151172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
807 09:31:11.151264 ==
808 09:31:11.151395 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
809 09:31:11.151489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
810 09:31:11.151581 [CA 0] Center 38 (7~69) winsize 63
811 09:31:11.151674 [CA 1] Center 38 (8~69) winsize 62
812 09:31:11.151766 [CA 2] Center 36 (6~67) winsize 62
813 09:31:11.151858 [CA 3] Center 35 (5~66) winsize 62
814 09:31:11.151950 [CA 4] Center 35 (4~66) winsize 63
815 09:31:11.152042 [CA 5] Center 34 (4~65) winsize 62
816 09:31:11.152133
817 09:31:11.152243 [CmdBusTrainingLP45] Vref(ca) range 1: 34
818 09:31:11.152339
819 09:31:11.152445 [CATrainingPosCal] consider 2 rank data
820 09:31:11.152540 u2DelayCellTimex100 = 270/100 ps
821 09:31:11.152677 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
822 09:31:11.152772 CA1 delay=38 (8~69),Diff = 4 PI (28 cell)
823 09:31:11.152866 CA2 delay=36 (6~66),Diff = 2 PI (14 cell)
824 09:31:11.152976 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
825 09:31:11.153091 CA4 delay=35 (4~66),Diff = 1 PI (7 cell)
826 09:31:11.153206 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
827 09:31:11.153305
828 09:31:11.153402 CA PerBit enable=1, Macro0, CA PI delay=34
829 09:31:11.153503
830 09:31:11.153611 [CBTSetCACLKResult] CA Dly = 34
831 09:31:11.153706 CS Dly: 6 (0~38)
832 09:31:11.153803
833 09:31:11.153901 ----->DramcWriteLeveling(PI) begin...
834 09:31:11.154017 ==
835 09:31:11.154122 Dram Type= 6, Freq= 0, CH_0, rank 0
836 09:31:11.154230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
837 09:31:11.154325 ==
838 09:31:11.154419 Write leveling (Byte 0): 31 => 31
839 09:31:11.154513 Write leveling (Byte 1): 30 => 30
840 09:31:11.154613 DramcWriteLeveling(PI) end<-----
841 09:31:11.154720
842 09:31:11.154815 ==
843 09:31:11.154909 Dram Type= 6, Freq= 0, CH_0, rank 0
844 09:31:11.155003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
845 09:31:11.155097 ==
846 09:31:11.155194 [Gating] SW mode calibration
847 09:31:11.155291 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
848 09:31:11.155385 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
849 09:31:11.155495 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
850 09:31:11.155596 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
851 09:31:11.155706 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
852 09:31:11.155815 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 09:31:11.155915 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 09:31:11.156012 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 09:31:11.156134 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 09:31:11.156255 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 09:31:11.156354 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 09:31:11.156452 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 09:31:11.156554 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 09:31:11.156666 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 09:31:11.156791 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 09:31:11.156908 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 09:31:11.157028 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 09:31:11.157122 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 09:31:11.157217 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
866 09:31:11.157310 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
867 09:31:11.157411 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
868 09:31:11.157517 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 09:31:11.157619 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 09:31:11.157724 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 09:31:11.157818 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 09:31:11.157911 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 09:31:11.158036 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 09:31:11.158129 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
875 09:31:11.158222 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
876 09:31:11.158314 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
877 09:31:11.158407 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 09:31:11.158499 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 09:31:11.158591 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 09:31:11.158683 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 09:31:11.158976 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
882 09:31:11.159073 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
883 09:31:11.159170 0 10 8 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
884 09:31:11.159266 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
885 09:31:11.159360 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 09:31:11.159455 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 09:31:11.159548 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 09:31:11.159641 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 09:31:11.159735 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 09:31:11.159827 0 11 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
891 09:31:11.159920 0 11 8 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
892 09:31:11.160013 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
893 09:31:11.160106 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 09:31:11.160198 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 09:31:11.160290 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 09:31:11.160382 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 09:31:11.160474 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 09:31:11.160574 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
899 09:31:11.160667 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 09:31:11.160760 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 09:31:11.160852 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 09:31:11.160944 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 09:31:11.161036 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 09:31:11.161127 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 09:31:11.161220 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 09:31:11.161315 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 09:31:11.161410 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 09:31:11.161504 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 09:31:11.161597 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 09:31:11.161689 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 09:31:11.161785 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 09:31:11.161885 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 09:31:11.161978 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 09:31:11.162071 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
915 09:31:11.162166 Total UI for P1: 0, mck2ui 16
916 09:31:11.162301 best dqsien dly found for B0: ( 0, 14, 2)
917 09:31:11.162394 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
918 09:31:11.162487 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
919 09:31:11.162580 Total UI for P1: 0, mck2ui 16
920 09:31:11.162672 best dqsien dly found for B1: ( 0, 14, 6)
921 09:31:11.162765 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
922 09:31:11.162858 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
923 09:31:11.162950
924 09:31:11.163042 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
925 09:31:11.163135 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
926 09:31:11.163227 [Gating] SW calibration Done
927 09:31:11.163319 ==
928 09:31:11.163412 Dram Type= 6, Freq= 0, CH_0, rank 0
929 09:31:11.163504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
930 09:31:11.163597 ==
931 09:31:11.163689 RX Vref Scan: 0
932 09:31:11.163781
933 09:31:11.163872 RX Vref 0 -> 0, step: 1
934 09:31:11.163964
935 09:31:11.164056 RX Delay -130 -> 252, step: 16
936 09:31:11.164148 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
937 09:31:11.164240 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
938 09:31:11.164333 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
939 09:31:11.164426 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
940 09:31:11.164518 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
941 09:31:11.164652 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
942 09:31:11.164778 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
943 09:31:11.164871 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
944 09:31:11.164999 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
945 09:31:11.165092 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
946 09:31:11.165185 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
947 09:31:11.165278 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
948 09:31:11.165370 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
949 09:31:11.165493 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
950 09:31:11.165585 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
951 09:31:11.165676 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
952 09:31:11.165768 ==
953 09:31:11.165863 Dram Type= 6, Freq= 0, CH_0, rank 0
954 09:31:11.165956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
955 09:31:11.166052 ==
956 09:31:11.166144 DQS Delay:
957 09:31:11.166235 DQS0 = 0, DQS1 = 0
958 09:31:11.166328 DQM Delay:
959 09:31:11.166425 DQM0 = 89, DQM1 = 78
960 09:31:11.166521 DQ Delay:
961 09:31:11.166615 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
962 09:31:11.166707 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
963 09:31:11.166800 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
964 09:31:11.166891 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =85
965 09:31:11.166982
966 09:31:11.167074
967 09:31:11.167165 ==
968 09:31:11.167257 Dram Type= 6, Freq= 0, CH_0, rank 0
969 09:31:11.167348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
970 09:31:11.167441 ==
971 09:31:11.167534
972 09:31:11.167625
973 09:31:11.167716 TX Vref Scan disable
974 09:31:11.167808 == TX Byte 0 ==
975 09:31:11.167900 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
976 09:31:11.167991 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
977 09:31:11.168083 == TX Byte 1 ==
978 09:31:11.168174 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
979 09:31:11.168266 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
980 09:31:11.168358 ==
981 09:31:11.168450 Dram Type= 6, Freq= 0, CH_0, rank 0
982 09:31:11.168542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 09:31:11.168677 ==
984 09:31:11.168769 TX Vref=22, minBit 6, minWin=27, winSum=444
985 09:31:11.168862 TX Vref=24, minBit 8, minWin=27, winSum=444
986 09:31:11.168959 TX Vref=26, minBit 8, minWin=27, winSum=450
987 09:31:11.169052 TX Vref=28, minBit 8, minWin=27, winSum=453
988 09:31:11.169144 TX Vref=30, minBit 8, minWin=28, winSum=457
989 09:31:11.169436 TX Vref=32, minBit 10, minWin=27, winSum=455
990 09:31:11.169531 [TxChooseVref] Worse bit 8, Min win 28, Win sum 457, Final Vref 30
991 09:31:11.169627
992 09:31:11.169760 Final TX Range 1 Vref 30
993 09:31:11.169855
994 09:31:11.169948 ==
995 09:31:11.170041 Dram Type= 6, Freq= 0, CH_0, rank 0
996 09:31:11.170134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
997 09:31:11.170228 ==
998 09:31:11.170350
999 09:31:11.170441
1000 09:31:11.170533 TX Vref Scan disable
1001 09:31:11.170625 == TX Byte 0 ==
1002 09:31:11.170717 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1003 09:31:11.170810 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1004 09:31:11.170903 == TX Byte 1 ==
1005 09:31:11.170995 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1006 09:31:11.171087 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1007 09:31:11.171178
1008 09:31:11.171270 [DATLAT]
1009 09:31:11.171361 Freq=800, CH0 RK0
1010 09:31:11.171454
1011 09:31:11.171545 DATLAT Default: 0xa
1012 09:31:11.171639 0, 0xFFFF, sum = 0
1013 09:31:11.171734 1, 0xFFFF, sum = 0
1014 09:31:11.171829 2, 0xFFFF, sum = 0
1015 09:31:11.171923 3, 0xFFFF, sum = 0
1016 09:31:11.172017 4, 0xFFFF, sum = 0
1017 09:31:11.172111 5, 0xFFFF, sum = 0
1018 09:31:11.172204 6, 0xFFFF, sum = 0
1019 09:31:11.172298 7, 0xFFFF, sum = 0
1020 09:31:11.172391 8, 0xFFFF, sum = 0
1021 09:31:11.172485 9, 0x0, sum = 1
1022 09:31:11.172619 10, 0x0, sum = 2
1023 09:31:11.172716 11, 0x0, sum = 3
1024 09:31:11.172811 12, 0x0, sum = 4
1025 09:31:11.172912 best_step = 10
1026 09:31:11.173007
1027 09:31:11.173101 ==
1028 09:31:11.173195 Dram Type= 6, Freq= 0, CH_0, rank 0
1029 09:31:11.173289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1030 09:31:11.173383 ==
1031 09:31:11.173476 RX Vref Scan: 1
1032 09:31:11.173569
1033 09:31:11.173661 Set Vref Range= 32 -> 127
1034 09:31:11.173753
1035 09:31:11.173844 RX Vref 32 -> 127, step: 1
1036 09:31:11.173936
1037 09:31:11.174026 RX Delay -95 -> 252, step: 8
1038 09:31:11.174118
1039 09:31:11.174209 Set Vref, RX VrefLevel [Byte0]: 32
1040 09:31:11.174301 [Byte1]: 32
1041 09:31:11.174392
1042 09:31:11.174515 Set Vref, RX VrefLevel [Byte0]: 33
1043 09:31:11.174607 [Byte1]: 33
1044 09:31:11.174697
1045 09:31:11.174788 Set Vref, RX VrefLevel [Byte0]: 34
1046 09:31:11.174879 [Byte1]: 34
1047 09:31:11.174970
1048 09:31:11.175060 Set Vref, RX VrefLevel [Byte0]: 35
1049 09:31:11.175151 [Byte1]: 35
1050 09:31:11.175241
1051 09:31:11.175331 Set Vref, RX VrefLevel [Byte0]: 36
1052 09:31:11.175422 [Byte1]: 36
1053 09:31:11.175513
1054 09:31:11.175603 Set Vref, RX VrefLevel [Byte0]: 37
1055 09:31:11.175694 [Byte1]: 37
1056 09:31:11.175786
1057 09:31:11.175876 Set Vref, RX VrefLevel [Byte0]: 38
1058 09:31:11.175967 [Byte1]: 38
1059 09:31:11.176057
1060 09:31:11.176148 Set Vref, RX VrefLevel [Byte0]: 39
1061 09:31:11.176238 [Byte1]: 39
1062 09:31:11.176328
1063 09:31:11.176418 Set Vref, RX VrefLevel [Byte0]: 40
1064 09:31:11.176509 [Byte1]: 40
1065 09:31:11.176645
1066 09:31:11.176737 Set Vref, RX VrefLevel [Byte0]: 41
1067 09:31:11.176828 [Byte1]: 41
1068 09:31:11.176919
1069 09:31:11.177010 Set Vref, RX VrefLevel [Byte0]: 42
1070 09:31:11.177106 [Byte1]: 42
1071 09:31:11.177197
1072 09:31:11.177287 Set Vref, RX VrefLevel [Byte0]: 43
1073 09:31:11.177378 [Byte1]: 43
1074 09:31:11.177469
1075 09:31:11.177559 Set Vref, RX VrefLevel [Byte0]: 44
1076 09:31:11.177650 [Byte1]: 44
1077 09:31:11.177741
1078 09:31:11.177831 Set Vref, RX VrefLevel [Byte0]: 45
1079 09:31:11.177921 [Byte1]: 45
1080 09:31:11.178012
1081 09:31:11.178103 Set Vref, RX VrefLevel [Byte0]: 46
1082 09:31:11.178193 [Byte1]: 46
1083 09:31:11.178283
1084 09:31:11.178373 Set Vref, RX VrefLevel [Byte0]: 47
1085 09:31:11.178464 [Byte1]: 47
1086 09:31:11.178554
1087 09:31:11.178644 Set Vref, RX VrefLevel [Byte0]: 48
1088 09:31:11.178734 [Byte1]: 48
1089 09:31:11.178824
1090 09:31:11.178914 Set Vref, RX VrefLevel [Byte0]: 49
1091 09:31:11.179005 [Byte1]: 49
1092 09:31:11.179095
1093 09:31:11.179186 Set Vref, RX VrefLevel [Byte0]: 50
1094 09:31:11.179277 [Byte1]: 50
1095 09:31:11.179367
1096 09:31:11.179457 Set Vref, RX VrefLevel [Byte0]: 51
1097 09:31:11.179547 [Byte1]: 51
1098 09:31:11.179637
1099 09:31:11.179727 Set Vref, RX VrefLevel [Byte0]: 52
1100 09:31:11.179818 [Byte1]: 52
1101 09:31:11.179908
1102 09:31:11.179998 Set Vref, RX VrefLevel [Byte0]: 53
1103 09:31:11.180088 [Byte1]: 53
1104 09:31:11.180178
1105 09:31:11.180269 Set Vref, RX VrefLevel [Byte0]: 54
1106 09:31:11.180359 [Byte1]: 54
1107 09:31:11.180449
1108 09:31:11.180539 Set Vref, RX VrefLevel [Byte0]: 55
1109 09:31:11.180666 [Byte1]: 55
1110 09:31:11.180756
1111 09:31:11.180846 Set Vref, RX VrefLevel [Byte0]: 56
1112 09:31:11.180937 [Byte1]: 56
1113 09:31:11.181027
1114 09:31:11.181118 Set Vref, RX VrefLevel [Byte0]: 57
1115 09:31:11.181208 [Byte1]: 57
1116 09:31:11.181298
1117 09:31:11.181388 Set Vref, RX VrefLevel [Byte0]: 58
1118 09:31:11.181478 [Byte1]: 58
1119 09:31:11.181569
1120 09:31:11.181659 Set Vref, RX VrefLevel [Byte0]: 59
1121 09:31:11.181749 [Byte1]: 59
1122 09:31:11.181840
1123 09:31:11.181930 Set Vref, RX VrefLevel [Byte0]: 60
1124 09:31:11.182020 [Byte1]: 60
1125 09:31:11.182110
1126 09:31:11.182201 Set Vref, RX VrefLevel [Byte0]: 61
1127 09:31:11.182291 [Byte1]: 61
1128 09:31:11.182382
1129 09:31:11.182471 Set Vref, RX VrefLevel [Byte0]: 62
1130 09:31:11.182562 [Byte1]: 62
1131 09:31:11.182653
1132 09:31:11.182744 Set Vref, RX VrefLevel [Byte0]: 63
1133 09:31:11.182835 [Byte1]: 63
1134 09:31:11.182925
1135 09:31:11.183015 Set Vref, RX VrefLevel [Byte0]: 64
1136 09:31:11.183105 [Byte1]: 64
1137 09:31:11.183195
1138 09:31:11.183285 Set Vref, RX VrefLevel [Byte0]: 65
1139 09:31:11.183376 [Byte1]: 65
1140 09:31:11.183467
1141 09:31:11.183557 Set Vref, RX VrefLevel [Byte0]: 66
1142 09:31:11.183647 [Byte1]: 66
1143 09:31:11.183737
1144 09:31:11.183827 Set Vref, RX VrefLevel [Byte0]: 67
1145 09:31:11.183918 [Byte1]: 67
1146 09:31:11.184008
1147 09:31:11.184098 Set Vref, RX VrefLevel [Byte0]: 68
1148 09:31:11.184188 [Byte1]: 68
1149 09:31:11.184283
1150 09:31:11.184373 Set Vref, RX VrefLevel [Byte0]: 69
1151 09:31:11.184487 [Byte1]: 69
1152 09:31:11.184599
1153 09:31:11.184752 Set Vref, RX VrefLevel [Byte0]: 70
1154 09:31:11.184887 [Byte1]: 70
1155 09:31:11.184977
1156 09:31:11.185068 Set Vref, RX VrefLevel [Byte0]: 71
1157 09:31:11.185160 [Byte1]: 71
1158 09:31:11.185250
1159 09:31:11.185340 Set Vref, RX VrefLevel [Byte0]: 72
1160 09:31:11.185628 [Byte1]: 72
1161 09:31:11.185720
1162 09:31:11.185814 Set Vref, RX VrefLevel [Byte0]: 73
1163 09:31:11.185908 [Byte1]: 73
1164 09:31:11.186000
1165 09:31:11.186091 Set Vref, RX VrefLevel [Byte0]: 74
1166 09:31:11.186183 [Byte1]: 74
1167 09:31:11.186273
1168 09:31:11.186364 Set Vref, RX VrefLevel [Byte0]: 75
1169 09:31:11.186455 [Byte1]: 75
1170 09:31:11.186546
1171 09:31:11.186636 Set Vref, RX VrefLevel [Byte0]: 76
1172 09:31:11.186727 [Byte1]: 76
1173 09:31:11.186818
1174 09:31:11.186908 Set Vref, RX VrefLevel [Byte0]: 77
1175 09:31:11.186999 [Byte1]: 77
1176 09:31:11.187120
1177 09:31:11.187210 Final RX Vref Byte 0 = 65 to rank0
1178 09:31:11.187301 Final RX Vref Byte 1 = 61 to rank0
1179 09:31:11.187392 Final RX Vref Byte 0 = 65 to rank1
1180 09:31:11.187484 Final RX Vref Byte 1 = 61 to rank1==
1181 09:31:11.187575 Dram Type= 6, Freq= 0, CH_0, rank 0
1182 09:31:11.187682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1183 09:31:11.187787 ==
1184 09:31:11.187878 DQS Delay:
1185 09:31:11.187969 DQS0 = 0, DQS1 = 0
1186 09:31:11.188059 DQM Delay:
1187 09:31:11.188150 DQM0 = 93, DQM1 = 81
1188 09:31:11.188240 DQ Delay:
1189 09:31:11.188330 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1190 09:31:11.188421 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1191 09:31:11.188512 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =80
1192 09:31:11.188643 DQ12 =84, DQ13 =80, DQ14 =92, DQ15 =92
1193 09:31:11.188735
1194 09:31:11.188826
1195 09:31:11.188918 [DQSOSCAuto] RK0, (LSB)MR18= 0x423d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
1196 09:31:11.189011 CH0 RK0: MR19=606, MR18=423D
1197 09:31:11.189102 CH0_RK0: MR19=0x606, MR18=0x423D, DQSOSC=393, MR23=63, INC=95, DEC=63
1198 09:31:11.189194
1199 09:31:11.189285 ----->DramcWriteLeveling(PI) begin...
1200 09:31:11.189378 ==
1201 09:31:11.189469 Dram Type= 6, Freq= 0, CH_0, rank 1
1202 09:31:11.189561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1203 09:31:11.189653 ==
1204 09:31:11.189744 Write leveling (Byte 0): 31 => 31
1205 09:31:11.189835 Write leveling (Byte 1): 29 => 29
1206 09:31:11.189926 DramcWriteLeveling(PI) end<-----
1207 09:31:11.190017
1208 09:31:11.190107 ==
1209 09:31:11.190198 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 09:31:11.190288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 09:31:11.190380 ==
1212 09:31:11.190471 [Gating] SW mode calibration
1213 09:31:11.190561 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1214 09:31:11.190655 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1215 09:31:11.190746 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1216 09:31:11.190838 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1217 09:31:11.190930 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1218 09:31:11.191021 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 09:31:11.191111 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 09:31:11.191202 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 09:31:11.191293 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 09:31:11.191384 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 09:31:11.191476 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 09:31:11.191566 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 09:31:11.191657 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 09:31:11.191748 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 09:31:11.191838 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 09:31:11.191928 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 09:31:11.192019 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 09:31:11.192109 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 09:31:11.192199 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 09:31:11.192289 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1233 09:31:11.192383 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1234 09:31:11.192474 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 09:31:11.192586 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 09:31:11.192691 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 09:31:11.192782 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 09:31:11.192873 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 09:31:11.192963 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 09:31:11.193053 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1241 09:31:11.193144 0 9 8 | B1->B0 | 2d2d 3333 | 1 1 | (1 1) (1 1)
1242 09:31:11.193234 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 09:31:11.193329 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 09:31:11.193430 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 09:31:11.193520 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 09:31:11.193606 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 09:31:11.193691 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 09:31:11.193775 0 10 4 | B1->B0 | 3131 3030 | 0 0 | (0 0) (0 1)
1249 09:31:11.193859 0 10 8 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)
1250 09:31:11.193942 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 09:31:11.194026 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 09:31:11.194110 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 09:31:11.194193 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 09:31:11.194276 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 09:31:11.194360 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 09:31:11.194443 0 11 4 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
1257 09:31:11.194526 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1258 09:31:11.194610 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 09:31:11.194693 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 09:31:11.194776 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 09:31:11.194860 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 09:31:11.194943 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 09:31:11.195026 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 09:31:11.195305 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1265 09:31:11.195396 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 09:31:11.195511 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 09:31:11.195595 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 09:31:11.195679 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 09:31:11.195762 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 09:31:11.195845 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 09:31:11.195928 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 09:31:11.196012 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 09:31:11.196095 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 09:31:11.196178 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 09:31:11.196262 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 09:31:11.196345 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 09:31:11.196429 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 09:31:11.196512 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 09:31:11.196635 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 09:31:11.196719 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1281 09:31:11.196806 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1282 09:31:11.196889 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 09:31:11.196972 Total UI for P1: 0, mck2ui 16
1284 09:31:11.197056 best dqsien dly found for B0: ( 0, 14, 6)
1285 09:31:11.197140 Total UI for P1: 0, mck2ui 16
1286 09:31:11.197224 best dqsien dly found for B1: ( 0, 14, 8)
1287 09:31:11.197307 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1288 09:31:11.197390 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1289 09:31:11.197474
1290 09:31:11.197564 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1291 09:31:11.197656 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1292 09:31:11.197747 [Gating] SW calibration Done
1293 09:31:11.197838 ==
1294 09:31:11.197930 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 09:31:11.198021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 09:31:11.198113 ==
1297 09:31:11.198204 RX Vref Scan: 0
1298 09:31:11.198294
1299 09:31:11.198384 RX Vref 0 -> 0, step: 1
1300 09:31:11.198475
1301 09:31:11.198565 RX Delay -130 -> 252, step: 16
1302 09:31:11.198656 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1303 09:31:11.198747 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1304 09:31:11.198837 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1305 09:31:11.198928 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1306 09:31:11.199018 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1307 09:31:11.199108 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1308 09:31:11.199199 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1309 09:31:11.199289 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1310 09:31:11.199380 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1311 09:31:11.199470 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1312 09:31:11.199561 iDelay=206, Bit 10, Center 85 (-18 ~ 189) 208
1313 09:31:11.199652 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1314 09:31:11.199742 iDelay=206, Bit 12, Center 85 (-18 ~ 189) 208
1315 09:31:11.199837 iDelay=206, Bit 13, Center 85 (-18 ~ 189) 208
1316 09:31:11.199928 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1317 09:31:11.200019 iDelay=206, Bit 15, Center 85 (-18 ~ 189) 208
1318 09:31:11.200109 ==
1319 09:31:11.200200 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 09:31:11.200290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 09:31:11.200381 ==
1322 09:31:11.200472 DQS Delay:
1323 09:31:11.200568 DQS0 = 0, DQS1 = 0
1324 09:31:11.200718 DQM Delay:
1325 09:31:11.200809 DQM0 = 88, DQM1 = 80
1326 09:31:11.200900 DQ Delay:
1327 09:31:11.200991 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
1328 09:31:11.201082 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1329 09:31:11.201173 DQ8 =69, DQ9 =61, DQ10 =85, DQ11 =77
1330 09:31:11.201264 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1331 09:31:11.201354
1332 09:31:11.201445
1333 09:31:11.201535 ==
1334 09:31:11.201625 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 09:31:11.201716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 09:31:11.201807 ==
1337 09:31:11.201897
1338 09:31:11.201987
1339 09:31:11.202077 TX Vref Scan disable
1340 09:31:11.202168 == TX Byte 0 ==
1341 09:31:11.202258 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1342 09:31:11.202349 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1343 09:31:11.202440 == TX Byte 1 ==
1344 09:31:11.202530 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1345 09:31:11.202621 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1346 09:31:11.202712 ==
1347 09:31:11.202802 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 09:31:11.202893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 09:31:11.202984 ==
1350 09:31:11.203074 TX Vref=22, minBit 1, minWin=27, winSum=446
1351 09:31:11.203166 TX Vref=24, minBit 8, minWin=27, winSum=447
1352 09:31:11.203258 TX Vref=26, minBit 8, minWin=27, winSum=451
1353 09:31:11.203350 TX Vref=28, minBit 8, minWin=27, winSum=456
1354 09:31:11.203441 TX Vref=30, minBit 4, minWin=28, winSum=458
1355 09:31:11.203532 TX Vref=32, minBit 8, minWin=27, winSum=458
1356 09:31:11.203623 [TxChooseVref] Worse bit 4, Min win 28, Win sum 458, Final Vref 30
1357 09:31:11.203713
1358 09:31:11.203803 Final TX Range 1 Vref 30
1359 09:31:11.203894
1360 09:31:11.203984 ==
1361 09:31:11.204081 Dram Type= 6, Freq= 0, CH_0, rank 1
1362 09:31:11.204170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1363 09:31:11.204260 ==
1364 09:31:11.204351
1365 09:31:11.204443
1366 09:31:11.204532 TX Vref Scan disable
1367 09:31:11.204655 == TX Byte 0 ==
1368 09:31:11.204742 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1369 09:31:11.204827 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1370 09:31:11.204911 == TX Byte 1 ==
1371 09:31:11.204993 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1372 09:31:11.205075 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1373 09:31:11.205161
1374 09:31:11.205244 [DATLAT]
1375 09:31:11.205326 Freq=800, CH0 RK1
1376 09:31:11.205409
1377 09:31:11.205490 DATLAT Default: 0xa
1378 09:31:11.205572 0, 0xFFFF, sum = 0
1379 09:31:11.205656 1, 0xFFFF, sum = 0
1380 09:31:11.205741 2, 0xFFFF, sum = 0
1381 09:31:11.205824 3, 0xFFFF, sum = 0
1382 09:31:11.205906 4, 0xFFFF, sum = 0
1383 09:31:11.205989 5, 0xFFFF, sum = 0
1384 09:31:11.206071 6, 0xFFFF, sum = 0
1385 09:31:11.206152 7, 0xFFFF, sum = 0
1386 09:31:11.206235 8, 0xFFFF, sum = 0
1387 09:31:11.206318 9, 0x0, sum = 1
1388 09:31:11.206400 10, 0x0, sum = 2
1389 09:31:11.206483 11, 0x0, sum = 3
1390 09:31:11.206566 12, 0x0, sum = 4
1391 09:31:11.206650 best_step = 10
1392 09:31:11.206733
1393 09:31:11.206814 ==
1394 09:31:11.206895 Dram Type= 6, Freq= 0, CH_0, rank 1
1395 09:31:11.207184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 09:31:11.207278 ==
1397 09:31:11.207365 RX Vref Scan: 0
1398 09:31:11.207448
1399 09:31:11.207531 RX Vref 0 -> 0, step: 1
1400 09:31:11.207615
1401 09:31:11.207696 RX Delay -95 -> 252, step: 8
1402 09:31:11.207778 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1403 09:31:11.207859 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1404 09:31:11.207942 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1405 09:31:11.208025 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1406 09:31:11.208108 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1407 09:31:11.208190 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1408 09:31:11.208272 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1409 09:31:11.208353 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1410 09:31:11.208434 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1411 09:31:11.208515 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1412 09:31:11.208638 iDelay=209, Bit 10, Center 80 (-23 ~ 184) 208
1413 09:31:11.208721 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1414 09:31:11.208803 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1415 09:31:11.208884 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1416 09:31:11.208966 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1417 09:31:11.209047 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1418 09:31:11.209128 ==
1419 09:31:11.209209 Dram Type= 6, Freq= 0, CH_0, rank 1
1420 09:31:11.209290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1421 09:31:11.209371 ==
1422 09:31:11.209452 DQS Delay:
1423 09:31:11.209533 DQS0 = 0, DQS1 = 0
1424 09:31:11.209613 DQM Delay:
1425 09:31:11.209693 DQM0 = 91, DQM1 = 80
1426 09:31:11.209795 DQ Delay:
1427 09:31:11.209901 DQ0 =88, DQ1 =92, DQ2 =88, DQ3 =88
1428 09:31:11.210008 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1429 09:31:11.210096 DQ8 =72, DQ9 =68, DQ10 =80, DQ11 =76
1430 09:31:11.210178 DQ12 =84, DQ13 =84, DQ14 =92, DQ15 =88
1431 09:31:11.210259
1432 09:31:11.210340
1433 09:31:11.210421 [DQSOSCAuto] RK1, (LSB)MR18= 0x421c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1434 09:31:11.210504 CH0 RK1: MR19=606, MR18=421C
1435 09:31:11.210585 CH0_RK1: MR19=0x606, MR18=0x421C, DQSOSC=393, MR23=63, INC=95, DEC=63
1436 09:31:11.210667 [RxdqsGatingPostProcess] freq 800
1437 09:31:11.210754 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1438 09:31:11.210836 Pre-setting of DQS Precalculation
1439 09:31:11.210918 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1440 09:31:11.211000 ==
1441 09:31:11.211078 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 09:31:11.211156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 09:31:11.211234 ==
1444 09:31:11.211310 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1445 09:31:11.211388 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1446 09:31:11.211466 [CA 0] Center 36 (6~67) winsize 62
1447 09:31:11.211545 [CA 1] Center 36 (6~67) winsize 62
1448 09:31:11.211623 [CA 2] Center 34 (4~65) winsize 62
1449 09:31:11.211701 [CA 3] Center 34 (3~65) winsize 63
1450 09:31:11.211779 [CA 4] Center 34 (4~65) winsize 62
1451 09:31:11.211857 [CA 5] Center 33 (3~64) winsize 62
1452 09:31:11.211935
1453 09:31:11.212012 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1454 09:31:11.212092
1455 09:31:11.212192 [CATrainingPosCal] consider 1 rank data
1456 09:31:11.212274 u2DelayCellTimex100 = 270/100 ps
1457 09:31:11.212360 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1458 09:31:11.212452 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1459 09:31:11.212550 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1460 09:31:11.212678 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1461 09:31:11.212773 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1462 09:31:11.212867 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1463 09:31:11.212966
1464 09:31:11.213064 CA PerBit enable=1, Macro0, CA PI delay=33
1465 09:31:11.213151
1466 09:31:11.213236 [CBTSetCACLKResult] CA Dly = 33
1467 09:31:11.213320 CS Dly: 5 (0~36)
1468 09:31:11.213402 ==
1469 09:31:11.213485 Dram Type= 6, Freq= 0, CH_1, rank 1
1470 09:31:11.213567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1471 09:31:11.213649 ==
1472 09:31:11.213732 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1473 09:31:11.213814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1474 09:31:11.213896 [CA 0] Center 36 (6~67) winsize 62
1475 09:31:11.213977 [CA 1] Center 37 (6~68) winsize 63
1476 09:31:11.214058 [CA 2] Center 35 (4~66) winsize 63
1477 09:31:11.214139 [CA 3] Center 34 (4~65) winsize 62
1478 09:31:11.214220 [CA 4] Center 34 (4~65) winsize 62
1479 09:31:11.214301 [CA 5] Center 34 (3~65) winsize 63
1480 09:31:11.214382
1481 09:31:11.214462 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1482 09:31:11.214544
1483 09:31:11.214625 [CATrainingPosCal] consider 2 rank data
1484 09:31:11.214706 u2DelayCellTimex100 = 270/100 ps
1485 09:31:11.214787 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1486 09:31:11.214869 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1487 09:31:11.214951 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1488 09:31:11.215031 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1489 09:31:11.215112 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1490 09:31:11.215193 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1491 09:31:11.215274
1492 09:31:11.215355 CA PerBit enable=1, Macro0, CA PI delay=33
1493 09:31:11.215435
1494 09:31:11.215515 [CBTSetCACLKResult] CA Dly = 33
1495 09:31:11.215596 CS Dly: 6 (0~38)
1496 09:31:11.215676
1497 09:31:11.215757 ----->DramcWriteLeveling(PI) begin...
1498 09:31:11.215839 ==
1499 09:31:11.215921 Dram Type= 6, Freq= 0, CH_1, rank 0
1500 09:31:11.216002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1501 09:31:11.216083 ==
1502 09:31:11.216165 Write leveling (Byte 0): 28 => 28
1503 09:31:11.216246 Write leveling (Byte 1): 29 => 29
1504 09:31:11.216327 DramcWriteLeveling(PI) end<-----
1505 09:31:11.216407
1506 09:31:11.216488 ==
1507 09:31:11.216608 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 09:31:11.216690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 09:31:11.216771 ==
1510 09:31:11.216852 [Gating] SW mode calibration
1511 09:31:11.216934 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1512 09:31:11.217017 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1513 09:31:11.217099 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1514 09:31:11.217181 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1515 09:31:11.217262 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1516 09:31:11.217344 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 09:31:11.217621 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 09:31:11.217707 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 09:31:11.217806 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 09:31:11.217903 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 09:31:11.218015 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 09:31:11.218098 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 09:31:11.218179 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 09:31:11.218261 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 09:31:11.218342 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 09:31:11.218455 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 09:31:11.218536 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 09:31:11.218618 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 09:31:11.218699 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1530 09:31:11.218781 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1531 09:31:11.218863 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1532 09:31:11.218944 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 09:31:11.219026 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 09:31:11.219107 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 09:31:11.219189 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 09:31:11.219270 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 09:31:11.219351 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 09:31:11.219433 0 9 4 | B1->B0 | 2424 2c2c | 0 0 | (0 0) (0 0)
1539 09:31:11.219514 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 09:31:11.219596 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 09:31:11.219677 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 09:31:11.219758 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 09:31:11.219840 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 09:31:11.219921 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 09:31:11.220002 0 10 0 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)
1546 09:31:11.220084 0 10 4 | B1->B0 | 3030 2a2a | 1 1 | (1 1) (1 0)
1547 09:31:11.220165 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 09:31:11.220247 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 09:31:11.220328 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 09:31:11.220409 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 09:31:11.220491 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 09:31:11.220597 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 09:31:11.220693 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 09:31:11.220775 0 11 4 | B1->B0 | 3333 3939 | 0 0 | (0 0) (0 0)
1555 09:31:11.220856 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 09:31:11.220938 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 09:31:11.221019 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 09:31:11.221100 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 09:31:11.221181 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 09:31:11.221263 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 09:31:11.221344 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 09:31:11.221425 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1563 09:31:11.221507 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1564 09:31:11.221593 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 09:31:11.221648 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 09:31:11.221701 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 09:31:11.221752 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 09:31:11.221803 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 09:31:11.221855 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 09:31:11.221906 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 09:31:11.221957 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 09:31:11.222008 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 09:31:11.222060 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 09:31:11.222111 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 09:31:11.222162 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 09:31:11.222213 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 09:31:11.222264 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 09:31:11.222315 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1579 09:31:11.222366 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 09:31:11.222417 Total UI for P1: 0, mck2ui 16
1581 09:31:11.222469 best dqsien dly found for B0: ( 0, 14, 4)
1582 09:31:11.222521 Total UI for P1: 0, mck2ui 16
1583 09:31:11.222572 best dqsien dly found for B1: ( 0, 14, 4)
1584 09:31:11.222623 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1585 09:31:11.222674 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1586 09:31:11.222726
1587 09:31:11.222777 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1588 09:31:11.222829 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1589 09:31:11.222879 [Gating] SW calibration Done
1590 09:31:11.222931 ==
1591 09:31:11.222982 Dram Type= 6, Freq= 0, CH_1, rank 0
1592 09:31:11.223034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1593 09:31:11.223086 ==
1594 09:31:11.223136 RX Vref Scan: 0
1595 09:31:11.223187
1596 09:31:11.223238 RX Vref 0 -> 0, step: 1
1597 09:31:11.223288
1598 09:31:11.223339 RX Delay -130 -> 252, step: 16
1599 09:31:11.223391 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1600 09:31:11.223442 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1601 09:31:11.223494 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1602 09:31:11.223546 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1603 09:31:11.223597 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1604 09:31:11.223648 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1605 09:31:11.223699 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1606 09:31:11.223948 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1607 09:31:11.224006 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1608 09:31:11.224059 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1609 09:31:11.224111 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1610 09:31:11.224162 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1611 09:31:11.224213 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1612 09:31:11.224265 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1613 09:31:11.224317 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1614 09:31:11.224367 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1615 09:31:11.224419 ==
1616 09:31:11.224484 Dram Type= 6, Freq= 0, CH_1, rank 0
1617 09:31:11.224537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1618 09:31:11.224613 ==
1619 09:31:11.224664 DQS Delay:
1620 09:31:11.224716 DQS0 = 0, DQS1 = 0
1621 09:31:11.224767 DQM Delay:
1622 09:31:11.224818 DQM0 = 87, DQM1 = 82
1623 09:31:11.224869 DQ Delay:
1624 09:31:11.224919 DQ0 =93, DQ1 =77, DQ2 =77, DQ3 =85
1625 09:31:11.224971 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1626 09:31:11.225022 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1627 09:31:11.225073 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1628 09:31:11.225124
1629 09:31:11.225175
1630 09:31:11.225226 ==
1631 09:31:11.225276 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 09:31:11.225327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 09:31:11.225378 ==
1634 09:31:11.225429
1635 09:31:11.225479
1636 09:31:11.225530 TX Vref Scan disable
1637 09:31:11.225581 == TX Byte 0 ==
1638 09:31:11.225632 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1639 09:31:11.225683 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1640 09:31:11.225735 == TX Byte 1 ==
1641 09:31:11.225786 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1642 09:31:11.225837 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1643 09:31:11.225888 ==
1644 09:31:11.225938 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 09:31:11.225989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 09:31:11.226041 ==
1647 09:31:11.226092 TX Vref=22, minBit 8, minWin=27, winSum=446
1648 09:31:11.226144 TX Vref=24, minBit 8, minWin=27, winSum=452
1649 09:31:11.226195 TX Vref=26, minBit 15, minWin=27, winSum=456
1650 09:31:11.226247 TX Vref=28, minBit 15, minWin=27, winSum=458
1651 09:31:11.226298 TX Vref=30, minBit 1, minWin=28, winSum=457
1652 09:31:11.226350 TX Vref=32, minBit 8, minWin=28, winSum=458
1653 09:31:11.226401 [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 32
1654 09:31:11.226453
1655 09:31:11.226504 Final TX Range 1 Vref 32
1656 09:31:11.226555
1657 09:31:11.226605 ==
1658 09:31:11.226656 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 09:31:11.226707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 09:31:11.226759 ==
1661 09:31:11.226810
1662 09:31:11.226861
1663 09:31:11.226911 TX Vref Scan disable
1664 09:31:11.226963 == TX Byte 0 ==
1665 09:31:11.227014 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1666 09:31:11.227066 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1667 09:31:11.227117 == TX Byte 1 ==
1668 09:31:11.227167 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1669 09:31:11.227219 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1670 09:31:11.227270
1671 09:31:11.227321 [DATLAT]
1672 09:31:11.227372 Freq=800, CH1 RK0
1673 09:31:11.227423
1674 09:31:11.227474 DATLAT Default: 0xa
1675 09:31:11.227524 0, 0xFFFF, sum = 0
1676 09:31:11.227577 1, 0xFFFF, sum = 0
1677 09:31:11.227629 2, 0xFFFF, sum = 0
1678 09:31:11.227680 3, 0xFFFF, sum = 0
1679 09:31:11.227731 4, 0xFFFF, sum = 0
1680 09:31:11.227783 5, 0xFFFF, sum = 0
1681 09:31:11.227834 6, 0xFFFF, sum = 0
1682 09:31:11.227886 7, 0xFFFF, sum = 0
1683 09:31:11.227937 8, 0xFFFF, sum = 0
1684 09:31:11.227989 9, 0x0, sum = 1
1685 09:31:11.228041 10, 0x0, sum = 2
1686 09:31:11.228094 11, 0x0, sum = 3
1687 09:31:11.228146 12, 0x0, sum = 4
1688 09:31:11.228198 best_step = 10
1689 09:31:11.228249
1690 09:31:11.228300 ==
1691 09:31:11.228351 Dram Type= 6, Freq= 0, CH_1, rank 0
1692 09:31:11.228402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1693 09:31:11.228453 ==
1694 09:31:11.228505 RX Vref Scan: 1
1695 09:31:11.228563
1696 09:31:11.228683 Set Vref Range= 32 -> 127
1697 09:31:11.228763
1698 09:31:11.228843 RX Vref 32 -> 127, step: 1
1699 09:31:11.228924
1700 09:31:11.229004 RX Delay -79 -> 252, step: 8
1701 09:31:11.229085
1702 09:31:11.229165 Set Vref, RX VrefLevel [Byte0]: 32
1703 09:31:11.229247 [Byte1]: 32
1704 09:31:11.229327
1705 09:31:11.229408 Set Vref, RX VrefLevel [Byte0]: 33
1706 09:31:11.229489 [Byte1]: 33
1707 09:31:11.229569
1708 09:31:11.229650 Set Vref, RX VrefLevel [Byte0]: 34
1709 09:31:11.229730 [Byte1]: 34
1710 09:31:11.229810
1711 09:31:11.229891 Set Vref, RX VrefLevel [Byte0]: 35
1712 09:31:11.229972 [Byte1]: 35
1713 09:31:11.230052
1714 09:31:11.230134 Set Vref, RX VrefLevel [Byte0]: 36
1715 09:31:11.230221 [Byte1]: 36
1716 09:31:11.230282
1717 09:31:11.230334 Set Vref, RX VrefLevel [Byte0]: 37
1718 09:31:11.230386 [Byte1]: 37
1719 09:31:11.230437
1720 09:31:11.230488 Set Vref, RX VrefLevel [Byte0]: 38
1721 09:31:11.230539 [Byte1]: 38
1722 09:31:11.230591
1723 09:31:11.230642 Set Vref, RX VrefLevel [Byte0]: 39
1724 09:31:11.230693 [Byte1]: 39
1725 09:31:11.230745
1726 09:31:11.230795 Set Vref, RX VrefLevel [Byte0]: 40
1727 09:31:11.230846 [Byte1]: 40
1728 09:31:11.230897
1729 09:31:11.230948 Set Vref, RX VrefLevel [Byte0]: 41
1730 09:31:11.230999 [Byte1]: 41
1731 09:31:11.231050
1732 09:31:11.231101 Set Vref, RX VrefLevel [Byte0]: 42
1733 09:31:11.231152 [Byte1]: 42
1734 09:31:11.231203
1735 09:31:11.231253 Set Vref, RX VrefLevel [Byte0]: 43
1736 09:31:11.231304 [Byte1]: 43
1737 09:31:11.231355
1738 09:31:11.231405 Set Vref, RX VrefLevel [Byte0]: 44
1739 09:31:11.231456 [Byte1]: 44
1740 09:31:11.231508
1741 09:31:11.231558 Set Vref, RX VrefLevel [Byte0]: 45
1742 09:31:11.231609 [Byte1]: 45
1743 09:31:11.231661
1744 09:31:11.231711 Set Vref, RX VrefLevel [Byte0]: 46
1745 09:31:11.231762 [Byte1]: 46
1746 09:31:11.231813
1747 09:31:11.231864 Set Vref, RX VrefLevel [Byte0]: 47
1748 09:31:11.231915 [Byte1]: 47
1749 09:31:11.231966
1750 09:31:11.232017 Set Vref, RX VrefLevel [Byte0]: 48
1751 09:31:11.232068 [Byte1]: 48
1752 09:31:11.232119
1753 09:31:11.232169 Set Vref, RX VrefLevel [Byte0]: 49
1754 09:31:11.232220 [Byte1]: 49
1755 09:31:11.232271
1756 09:31:11.232321 Set Vref, RX VrefLevel [Byte0]: 50
1757 09:31:11.232373 [Byte1]: 50
1758 09:31:11.232424
1759 09:31:11.232474 Set Vref, RX VrefLevel [Byte0]: 51
1760 09:31:11.232525 [Byte1]: 51
1761 09:31:11.232620
1762 09:31:11.232672 Set Vref, RX VrefLevel [Byte0]: 52
1763 09:31:11.232723 [Byte1]: 52
1764 09:31:11.232774
1765 09:31:11.232824 Set Vref, RX VrefLevel [Byte0]: 53
1766 09:31:11.232875 [Byte1]: 53
1767 09:31:11.232927
1768 09:31:11.233167 Set Vref, RX VrefLevel [Byte0]: 54
1769 09:31:11.233225 [Byte1]: 54
1770 09:31:11.233278
1771 09:31:11.233330 Set Vref, RX VrefLevel [Byte0]: 55
1772 09:31:11.233382 [Byte1]: 55
1773 09:31:11.233434
1774 09:31:11.233485 Set Vref, RX VrefLevel [Byte0]: 56
1775 09:31:11.233537 [Byte1]: 56
1776 09:31:11.233589
1777 09:31:11.233640 Set Vref, RX VrefLevel [Byte0]: 57
1778 09:31:11.233691 [Byte1]: 57
1779 09:31:11.233742
1780 09:31:11.233793 Set Vref, RX VrefLevel [Byte0]: 58
1781 09:31:11.233844 [Byte1]: 58
1782 09:31:11.233894
1783 09:31:11.233945 Set Vref, RX VrefLevel [Byte0]: 59
1784 09:31:11.233996 [Byte1]: 59
1785 09:31:11.234047
1786 09:31:11.234098 Set Vref, RX VrefLevel [Byte0]: 60
1787 09:31:11.234149 [Byte1]: 60
1788 09:31:11.234200
1789 09:31:11.234251 Set Vref, RX VrefLevel [Byte0]: 61
1790 09:31:11.234302 [Byte1]: 61
1791 09:31:11.234353
1792 09:31:11.234404 Set Vref, RX VrefLevel [Byte0]: 62
1793 09:31:11.234455 [Byte1]: 62
1794 09:31:11.234506
1795 09:31:11.234557 Set Vref, RX VrefLevel [Byte0]: 63
1796 09:31:11.234608 [Byte1]: 63
1797 09:31:11.234660
1798 09:31:11.234711 Set Vref, RX VrefLevel [Byte0]: 64
1799 09:31:11.234763 [Byte1]: 64
1800 09:31:11.234814
1801 09:31:11.234865 Set Vref, RX VrefLevel [Byte0]: 65
1802 09:31:11.234916 [Byte1]: 65
1803 09:31:11.234967
1804 09:31:11.235017 Set Vref, RX VrefLevel [Byte0]: 66
1805 09:31:11.235068 [Byte1]: 66
1806 09:31:11.235120
1807 09:31:11.235170 Set Vref, RX VrefLevel [Byte0]: 67
1808 09:31:11.235221 [Byte1]: 67
1809 09:31:11.235272
1810 09:31:11.235323 Set Vref, RX VrefLevel [Byte0]: 68
1811 09:31:11.235374 [Byte1]: 68
1812 09:31:11.235425
1813 09:31:11.235476 Set Vref, RX VrefLevel [Byte0]: 69
1814 09:31:11.235527 [Byte1]: 69
1815 09:31:11.235578
1816 09:31:11.235630 Set Vref, RX VrefLevel [Byte0]: 70
1817 09:31:11.235681 [Byte1]: 70
1818 09:31:11.235731
1819 09:31:11.235781 Set Vref, RX VrefLevel [Byte0]: 71
1820 09:31:11.235833 [Byte1]: 71
1821 09:31:11.235884
1822 09:31:11.235934 Set Vref, RX VrefLevel [Byte0]: 72
1823 09:31:11.235986 [Byte1]: 72
1824 09:31:11.236037
1825 09:31:11.236087 Set Vref, RX VrefLevel [Byte0]: 73
1826 09:31:11.236138 [Byte1]: 73
1827 09:31:11.236189
1828 09:31:11.236240 Set Vref, RX VrefLevel [Byte0]: 74
1829 09:31:11.236290 [Byte1]: 74
1830 09:31:11.236341
1831 09:31:11.236392 Set Vref, RX VrefLevel [Byte0]: 75
1832 09:31:11.236443 [Byte1]: 75
1833 09:31:11.236494
1834 09:31:11.236544 Set Vref, RX VrefLevel [Byte0]: 76
1835 09:31:11.236640 [Byte1]: 76
1836 09:31:11.236691
1837 09:31:11.236742 Set Vref, RX VrefLevel [Byte0]: 77
1838 09:31:11.236793 [Byte1]: 77
1839 09:31:11.236843
1840 09:31:11.236894 Set Vref, RX VrefLevel [Byte0]: 78
1841 09:31:11.236945 [Byte1]: 78
1842 09:31:11.236997
1843 09:31:11.237048 Final RX Vref Byte 0 = 51 to rank0
1844 09:31:11.237100 Final RX Vref Byte 1 = 59 to rank0
1845 09:31:11.237152 Final RX Vref Byte 0 = 51 to rank1
1846 09:31:11.237204 Final RX Vref Byte 1 = 59 to rank1==
1847 09:31:11.237255 Dram Type= 6, Freq= 0, CH_1, rank 0
1848 09:31:11.237307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 09:31:11.237358 ==
1850 09:31:11.237409 DQS Delay:
1851 09:31:11.237460 DQS0 = 0, DQS1 = 0
1852 09:31:11.237511 DQM Delay:
1853 09:31:11.237562 DQM0 = 92, DQM1 = 81
1854 09:31:11.237613 DQ Delay:
1855 09:31:11.237665 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1856 09:31:11.237716 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =88
1857 09:31:11.237768 DQ8 =72, DQ9 =68, DQ10 =84, DQ11 =76
1858 09:31:11.237819 DQ12 =92, DQ13 =88, DQ14 =84, DQ15 =88
1859 09:31:11.237870
1860 09:31:11.237921
1861 09:31:11.237972 [DQSOSCAuto] RK0, (LSB)MR18= 0x3250, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 397 ps
1862 09:31:11.238024 CH1 RK0: MR19=606, MR18=3250
1863 09:31:11.238075 CH1_RK0: MR19=0x606, MR18=0x3250, DQSOSC=389, MR23=63, INC=97, DEC=65
1864 09:31:11.238127
1865 09:31:11.238178 ----->DramcWriteLeveling(PI) begin...
1866 09:31:11.238230 ==
1867 09:31:11.238281 Dram Type= 6, Freq= 0, CH_1, rank 1
1868 09:31:11.238333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1869 09:31:11.238385 ==
1870 09:31:11.238436 Write leveling (Byte 0): 26 => 26
1871 09:31:11.238487 Write leveling (Byte 1): 28 => 28
1872 09:31:11.238539 DramcWriteLeveling(PI) end<-----
1873 09:31:11.238590
1874 09:31:11.238641 ==
1875 09:31:11.238720 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 09:31:11.238776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 09:31:11.238829 ==
1878 09:31:11.238881 [Gating] SW mode calibration
1879 09:31:11.238933 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1880 09:31:11.239026 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1881 09:31:11.239079 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1882 09:31:11.239131 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1883 09:31:11.239183 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 09:31:11.239234 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 09:31:11.239286 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 09:31:11.239338 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 09:31:11.239389 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 09:31:11.239440 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 09:31:11.239521 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 09:31:11.239572 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 09:31:11.239623 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 09:31:11.239675 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 09:31:11.239726 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 09:31:11.239778 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 09:31:11.239829 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 09:31:11.239880 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 09:31:11.239931 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1898 09:31:11.239982 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1899 09:31:11.240033 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 09:31:11.240084 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 09:31:11.240326 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 09:31:11.240383 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 09:31:11.240435 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 09:31:11.240487 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 09:31:11.240600 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 09:31:11.240707 0 9 4 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
1907 09:31:11.240804 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1908 09:31:11.240886 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 09:31:11.240969 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 09:31:11.241051 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 09:31:11.241133 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 09:31:11.241215 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 09:31:11.241304 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 09:31:11.241388 0 10 4 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
1915 09:31:11.241470 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 09:31:11.241553 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 09:31:11.241635 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 09:31:11.241717 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 09:31:11.241799 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 09:31:11.241881 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 09:31:11.241963 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 09:31:11.242045 0 11 4 | B1->B0 | 3535 3030 | 1 0 | (0 0) (0 0)
1923 09:31:11.242127 0 11 8 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
1924 09:31:11.242209 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 09:31:11.242291 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 09:31:11.242373 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 09:31:11.242455 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 09:31:11.242536 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 09:31:11.242618 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 09:31:11.242700 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1931 09:31:11.242782 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1932 09:31:11.242864 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 09:31:11.242946 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 09:31:11.243027 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 09:31:11.243109 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 09:31:11.243191 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 09:31:11.243273 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 09:31:11.243354 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 09:31:11.243436 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 09:31:11.243518 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 09:31:11.243600 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 09:31:11.243682 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 09:31:11.243764 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 09:31:11.243845 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 09:31:11.243927 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 09:31:11.244009 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1947 09:31:11.244092 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1948 09:31:11.244174 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1949 09:31:11.244255 Total UI for P1: 0, mck2ui 16
1950 09:31:11.244337 best dqsien dly found for B0: ( 0, 14, 6)
1951 09:31:11.244419 Total UI for P1: 0, mck2ui 16
1952 09:31:11.244501 best dqsien dly found for B1: ( 0, 14, 6)
1953 09:31:11.244621 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1954 09:31:11.244704 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1955 09:31:11.244784
1956 09:31:11.244866 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1957 09:31:11.244947 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1958 09:31:11.245029 [Gating] SW calibration Done
1959 09:31:11.245109 ==
1960 09:31:11.245191 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 09:31:11.245273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 09:31:11.245355 ==
1963 09:31:11.245436 RX Vref Scan: 0
1964 09:31:11.245517
1965 09:31:11.245598 RX Vref 0 -> 0, step: 1
1966 09:31:11.245678
1967 09:31:11.245759 RX Delay -130 -> 252, step: 16
1968 09:31:11.245840 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1969 09:31:11.245922 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1970 09:31:11.246003 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1971 09:31:11.246085 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1972 09:31:11.246166 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1973 09:31:11.246248 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1974 09:31:11.246329 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1975 09:31:11.246411 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1976 09:31:11.246492 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1977 09:31:11.246573 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1978 09:31:11.246655 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1979 09:31:11.246736 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1980 09:31:11.246818 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1981 09:31:11.246899 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1982 09:31:11.246981 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1983 09:31:11.247062 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1984 09:31:11.247143 ==
1985 09:31:11.474083 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 09:31:11.474788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 09:31:11.475341 ==
1988 09:31:11.475859 DQS Delay:
1989 09:31:11.476372 DQS0 = 0, DQS1 = 0
1990 09:31:11.476904 DQM Delay:
1991 09:31:11.477405 DQM0 = 90, DQM1 = 86
1992 09:31:11.477906 DQ Delay:
1993 09:31:11.478398 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1994 09:31:11.478890 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1995 09:31:11.479381 DQ8 =69, DQ9 =77, DQ10 =93, DQ11 =77
1996 09:31:11.479873 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1997 09:31:11.480364
1998 09:31:11.480889
1999 09:31:11.481378 ==
2000 09:31:11.481868 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 09:31:11.482845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 09:31:11.483393 ==
2003 09:31:11.483905
2004 09:31:11.484403
2005 09:31:11.484931 TX Vref Scan disable
2006 09:31:11.485431 == TX Byte 0 ==
2007 09:31:11.485918 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2008 09:31:11.486412 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2009 09:31:11.486903 == TX Byte 1 ==
2010 09:31:11.487387 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2011 09:31:11.487876 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2012 09:31:11.488360 ==
2013 09:31:11.488868 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 09:31:11.489361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 09:31:11.489852 ==
2016 09:31:11.490336 TX Vref=22, minBit 13, minWin=27, winSum=454
2017 09:31:11.490815 TX Vref=24, minBit 13, minWin=27, winSum=455
2018 09:31:11.491298 TX Vref=26, minBit 9, minWin=28, winSum=459
2019 09:31:11.491804 TX Vref=28, minBit 8, minWin=28, winSum=459
2020 09:31:11.492297 TX Vref=30, minBit 8, minWin=28, winSum=459
2021 09:31:11.492819 TX Vref=32, minBit 9, minWin=27, winSum=458
2022 09:31:11.493317 [TxChooseVref] Worse bit 9, Min win 28, Win sum 459, Final Vref 26
2023 09:31:11.493829
2024 09:31:11.494316 Final TX Range 1 Vref 26
2025 09:31:11.494807
2026 09:31:11.495288 ==
2027 09:31:11.495777 Dram Type= 6, Freq= 0, CH_1, rank 1
2028 09:31:11.496255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2029 09:31:11.496761 ==
2030 09:31:11.497244
2031 09:31:11.497718
2032 09:31:11.498199 TX Vref Scan disable
2033 09:31:11.498682 == TX Byte 0 ==
2034 09:31:11.499159 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2035 09:31:11.499646 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2036 09:31:11.500131 == TX Byte 1 ==
2037 09:31:11.500664 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2038 09:31:11.501104 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2039 09:31:11.501445
2040 09:31:11.501785 [DATLAT]
2041 09:31:11.502124 Freq=800, CH1 RK1
2042 09:31:11.502470
2043 09:31:11.502807 DATLAT Default: 0xa
2044 09:31:11.503149 0, 0xFFFF, sum = 0
2045 09:31:11.503499 1, 0xFFFF, sum = 0
2046 09:31:11.503848 2, 0xFFFF, sum = 0
2047 09:31:11.504194 3, 0xFFFF, sum = 0
2048 09:31:11.504540 4, 0xFFFF, sum = 0
2049 09:31:11.504910 5, 0xFFFF, sum = 0
2050 09:31:11.505261 6, 0xFFFF, sum = 0
2051 09:31:11.505609 7, 0xFFFF, sum = 0
2052 09:31:11.505956 8, 0xFFFF, sum = 0
2053 09:31:11.506217 9, 0x0, sum = 1
2054 09:31:11.506481 10, 0x0, sum = 2
2055 09:31:11.506745 11, 0x0, sum = 3
2056 09:31:11.507007 12, 0x0, sum = 4
2057 09:31:11.507270 best_step = 10
2058 09:31:11.507528
2059 09:31:11.507784 ==
2060 09:31:11.508042 Dram Type= 6, Freq= 0, CH_1, rank 1
2061 09:31:11.508297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2062 09:31:11.508569 ==
2063 09:31:11.508829 RX Vref Scan: 0
2064 09:31:11.509088
2065 09:31:11.509344 RX Vref 0 -> 0, step: 1
2066 09:31:11.509602
2067 09:31:11.509856 RX Delay -95 -> 252, step: 8
2068 09:31:11.510110 iDelay=209, Bit 0, Center 92 (-7 ~ 192) 200
2069 09:31:11.510370 iDelay=209, Bit 1, Center 88 (-15 ~ 192) 208
2070 09:31:11.510629 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
2071 09:31:11.510888 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
2072 09:31:11.511114 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
2073 09:31:11.511321 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2074 09:31:11.511526 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
2075 09:31:11.511730 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2076 09:31:11.511935 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2077 09:31:11.512142 iDelay=209, Bit 9, Center 76 (-31 ~ 184) 216
2078 09:31:11.512349 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
2079 09:31:11.512566 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2080 09:31:11.512775 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2081 09:31:11.512982 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2082 09:31:11.513191 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2083 09:31:11.513398 iDelay=209, Bit 15, Center 92 (-23 ~ 208) 232
2084 09:31:11.513605 ==
2085 09:31:11.513812 Dram Type= 6, Freq= 0, CH_1, rank 1
2086 09:31:11.514019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2087 09:31:11.514224 ==
2088 09:31:11.514429 DQS Delay:
2089 09:31:11.514646 DQS0 = 0, DQS1 = 0
2090 09:31:11.514853 DQM Delay:
2091 09:31:11.515060 DQM0 = 91, DQM1 = 83
2092 09:31:11.515265 DQ Delay:
2093 09:31:11.515470 DQ0 =92, DQ1 =88, DQ2 =80, DQ3 =88
2094 09:31:11.515674 DQ4 =92, DQ5 =108, DQ6 =96, DQ7 =88
2095 09:31:11.515881 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =80
2096 09:31:11.516072 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =92
2097 09:31:11.516243
2098 09:31:11.516413
2099 09:31:11.516594 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2100 09:31:11.516773 CH1 RK1: MR19=606, MR18=3C12
2101 09:31:11.516948 CH1_RK1: MR19=0x606, MR18=0x3C12, DQSOSC=394, MR23=63, INC=95, DEC=63
2102 09:31:11.517092 [RxdqsGatingPostProcess] freq 800
2103 09:31:11.517229 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2104 09:31:11.517366 Pre-setting of DQS Precalculation
2105 09:31:11.517501 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2106 09:31:11.517642 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2107 09:31:11.517778 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2108 09:31:11.517952
2109 09:31:11.518122
2110 09:31:11.518293 [Calibration Summary] 1600 Mbps
2111 09:31:11.518463 CH 0, Rank 0
2112 09:31:11.518634 SW Impedance : PASS
2113 09:31:11.518803 DUTY Scan : NO K
2114 09:31:11.518972 ZQ Calibration : PASS
2115 09:31:11.519105 Jitter Meter : NO K
2116 09:31:11.519275 CBT Training : PASS
2117 09:31:11.519444 Write leveling : PASS
2118 09:31:11.519612 RX DQS gating : PASS
2119 09:31:11.519744 RX DQ/DQS(RDDQC) : PASS
2120 09:31:11.519877 TX DQ/DQS : PASS
2121 09:31:11.520046 RX DATLAT : PASS
2122 09:31:11.520215 RX DQ/DQS(Engine): PASS
2123 09:31:11.520384 TX OE : NO K
2124 09:31:11.520560 All Pass.
2125 09:31:11.520717
2126 09:31:11.520854 CH 0, Rank 1
2127 09:31:11.520992 SW Impedance : PASS
2128 09:31:11.521108 DUTY Scan : NO K
2129 09:31:11.521224 ZQ Calibration : PASS
2130 09:31:11.521370 Jitter Meter : NO K
2131 09:31:11.521516 CBT Training : PASS
2132 09:31:11.521662 Write leveling : PASS
2133 09:31:11.521807 RX DQS gating : PASS
2134 09:31:11.521920 RX DQ/DQS(RDDQC) : PASS
2135 09:31:11.522033 TX DQ/DQS : PASS
2136 09:31:11.522147 RX DATLAT : PASS
2137 09:31:11.522260 RX DQ/DQS(Engine): PASS
2138 09:31:11.522373 TX OE : NO K
2139 09:31:11.522518 All Pass.
2140 09:31:11.522631
2141 09:31:11.522776 CH 1, Rank 0
2142 09:31:11.522921 SW Impedance : PASS
2143 09:31:11.523034 DUTY Scan : NO K
2144 09:31:11.523147 ZQ Calibration : PASS
2145 09:31:11.523264 Jitter Meter : NO K
2146 09:31:11.523377 CBT Training : PASS
2147 09:31:11.523520 Write leveling : PASS
2148 09:31:11.523664 RX DQS gating : PASS
2149 09:31:11.524034 RX DQ/DQS(RDDQC) : PASS
2150 09:31:11.524182 TX DQ/DQS : PASS
2151 09:31:11.524332 RX DATLAT : PASS
2152 09:31:11.524480 RX DQ/DQS(Engine): PASS
2153 09:31:11.524632 TX OE : NO K
2154 09:31:11.524750 All Pass.
2155 09:31:11.524866
2156 09:31:11.524981 CH 1, Rank 1
2157 09:31:11.525097 SW Impedance : PASS
2158 09:31:11.525243 DUTY Scan : NO K
2159 09:31:11.525389 ZQ Calibration : PASS
2160 09:31:11.525503 Jitter Meter : NO K
2161 09:31:11.525650 CBT Training : PASS
2162 09:31:11.525795 Write leveling : PASS
2163 09:31:11.525908 RX DQS gating : PASS
2164 09:31:11.526024 RX DQ/DQS(RDDQC) : PASS
2165 09:31:11.526124 TX DQ/DQS : PASS
2166 09:31:11.526224 RX DATLAT : PASS
2167 09:31:11.526323 RX DQ/DQS(Engine): PASS
2168 09:31:11.526451 TX OE : NO K
2169 09:31:11.526579 All Pass.
2170 09:31:11.526706
2171 09:31:11.526833 DramC Write-DBI off
2172 09:31:11.526932 PER_BANK_REFRESH: Hybrid Mode
2173 09:31:11.527032 TX_TRACKING: ON
2174 09:31:11.527132 [GetDramInforAfterCalByMRR] Vendor 6.
2175 09:31:11.527232 [GetDramInforAfterCalByMRR] Revision 606.
2176 09:31:11.527332 [GetDramInforAfterCalByMRR] Revision 2 0.
2177 09:31:11.527459 MR0 0x3b3b
2178 09:31:11.527587 MR8 0x5151
2179 09:31:11.527713 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2180 09:31:11.527840
2181 09:31:11.527966 MR0 0x3b3b
2182 09:31:11.528065 MR8 0x5151
2183 09:31:11.528164 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2184 09:31:11.528292
2185 09:31:11.528419 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2186 09:31:11.528553 [FAST_K] Save calibration result to emmc
2187 09:31:11.528684 [FAST_K] Save calibration result to emmc
2188 09:31:11.528811 dram_init: config_dvfs: 1
2189 09:31:11.528938 dramc_set_vcore_voltage set vcore to 662500
2190 09:31:11.529066 Read voltage for 1200, 2
2191 09:31:11.529193 Vio18 = 0
2192 09:31:11.529319 Vcore = 662500
2193 09:31:11.529447 Vdram = 0
2194 09:31:11.529574 Vddq = 0
2195 09:31:11.529700 Vmddr = 0
2196 09:31:11.529827 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2197 09:31:11.529955 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2198 09:31:11.530082 MEM_TYPE=3, freq_sel=15
2199 09:31:11.530209 sv_algorithm_assistance_LP4_1600
2200 09:31:11.530336 ============ PULL DRAM RESETB DOWN ============
2201 09:31:11.530464 ========== PULL DRAM RESETB DOWN end =========
2202 09:31:11.530593 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2203 09:31:11.530720 ===================================
2204 09:31:11.530847 LPDDR4 DRAM CONFIGURATION
2205 09:31:11.530980 ===================================
2206 09:31:11.531094 EX_ROW_EN[0] = 0x0
2207 09:31:11.531206 EX_ROW_EN[1] = 0x0
2208 09:31:11.531319 LP4Y_EN = 0x0
2209 09:31:11.531432 WORK_FSP = 0x0
2210 09:31:11.531545 WL = 0x4
2211 09:31:11.531657 RL = 0x4
2212 09:31:11.531770 BL = 0x2
2213 09:31:11.531881 RPST = 0x0
2214 09:31:11.531993 RD_PRE = 0x0
2215 09:31:11.532105 WR_PRE = 0x1
2216 09:31:11.532217 WR_PST = 0x0
2217 09:31:11.532329 DBI_WR = 0x0
2218 09:31:11.532441 DBI_RD = 0x0
2219 09:31:11.532561 OTF = 0x1
2220 09:31:11.532673 ===================================
2221 09:31:11.532778 ===================================
2222 09:31:11.532882 ANA top config
2223 09:31:11.532985 ===================================
2224 09:31:11.533089 DLL_ASYNC_EN = 0
2225 09:31:11.533192 ALL_SLAVE_EN = 0
2226 09:31:11.533295 NEW_RANK_MODE = 1
2227 09:31:11.533399 DLL_IDLE_MODE = 1
2228 09:31:11.533501 LP45_APHY_COMB_EN = 1
2229 09:31:11.533603 TX_ODT_DIS = 1
2230 09:31:11.533706 NEW_8X_MODE = 1
2231 09:31:11.533810 ===================================
2232 09:31:11.533913 ===================================
2233 09:31:11.534017 data_rate = 2400
2234 09:31:11.534120 CKR = 1
2235 09:31:11.534222 DQ_P2S_RATIO = 8
2236 09:31:11.534325 ===================================
2237 09:31:11.534428 CA_P2S_RATIO = 8
2238 09:31:11.534531 DQ_CA_OPEN = 0
2239 09:31:11.534633 DQ_SEMI_OPEN = 0
2240 09:31:11.534736 CA_SEMI_OPEN = 0
2241 09:31:11.534838 CA_FULL_RATE = 0
2242 09:31:11.534940 DQ_CKDIV4_EN = 0
2243 09:31:11.535043 CA_CKDIV4_EN = 0
2244 09:31:11.535146 CA_PREDIV_EN = 0
2245 09:31:11.535248 PH8_DLY = 17
2246 09:31:11.535351 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2247 09:31:11.535453 DQ_AAMCK_DIV = 4
2248 09:31:11.535555 CA_AAMCK_DIV = 4
2249 09:31:11.535658 CA_ADMCK_DIV = 4
2250 09:31:11.535760 DQ_TRACK_CA_EN = 0
2251 09:31:11.535862 CA_PICK = 1200
2252 09:31:11.535970 CA_MCKIO = 1200
2253 09:31:11.536063 MCKIO_SEMI = 0
2254 09:31:11.536155 PLL_FREQ = 2366
2255 09:31:11.536248 DQ_UI_PI_RATIO = 32
2256 09:31:11.536341 CA_UI_PI_RATIO = 0
2257 09:31:11.536433 ===================================
2258 09:31:11.536527 ===================================
2259 09:31:11.536627 memory_type:LPDDR4
2260 09:31:11.536719 GP_NUM : 10
2261 09:31:11.536812 SRAM_EN : 1
2262 09:31:11.536904 MD32_EN : 0
2263 09:31:11.536997 ===================================
2264 09:31:11.537090 [ANA_INIT] >>>>>>>>>>>>>>
2265 09:31:11.537183 <<<<<< [CONFIGURE PHASE]: ANA_TX
2266 09:31:11.537277 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2267 09:31:11.537369 ===================================
2268 09:31:11.537462 data_rate = 2400,PCW = 0X5b00
2269 09:31:11.537555 ===================================
2270 09:31:11.537648 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2271 09:31:11.537742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2272 09:31:11.537836 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2273 09:31:11.537930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2274 09:31:11.538024 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2275 09:31:11.538116 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2276 09:31:11.538210 [ANA_INIT] flow start
2277 09:31:11.538302 [ANA_INIT] PLL >>>>>>>>
2278 09:31:11.538394 [ANA_INIT] PLL <<<<<<<<
2279 09:31:11.538486 [ANA_INIT] MIDPI >>>>>>>>
2280 09:31:11.538579 [ANA_INIT] MIDPI <<<<<<<<
2281 09:31:11.538671 [ANA_INIT] DLL >>>>>>>>
2282 09:31:11.538763 [ANA_INIT] DLL <<<<<<<<
2283 09:31:11.538855 [ANA_INIT] flow end
2284 09:31:11.538947 ============ LP4 DIFF to SE enter ============
2285 09:31:11.539041 ============ LP4 DIFF to SE exit ============
2286 09:31:11.539334 [ANA_INIT] <<<<<<<<<<<<<
2287 09:31:11.539433 [Flow] Enable top DCM control >>>>>
2288 09:31:11.539527 [Flow] Enable top DCM control <<<<<
2289 09:31:11.539620 Enable DLL master slave shuffle
2290 09:31:11.539714 ==============================================================
2291 09:31:11.539808 Gating Mode config
2292 09:31:11.539902 ==============================================================
2293 09:31:11.539995 Config description:
2294 09:31:11.540089 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2295 09:31:11.540185 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2296 09:31:11.540280 SELPH_MODE 0: By rank 1: By Phase
2297 09:31:11.540374 ==============================================================
2298 09:31:11.540468 GAT_TRACK_EN = 1
2299 09:31:11.540569 RX_GATING_MODE = 2
2300 09:31:11.540664 RX_GATING_TRACK_MODE = 2
2301 09:31:11.540757 SELPH_MODE = 1
2302 09:31:11.540850 PICG_EARLY_EN = 1
2303 09:31:11.540954 VALID_LAT_VALUE = 1
2304 09:31:11.541040 ==============================================================
2305 09:31:11.541125 Enter into Gating configuration >>>>
2306 09:31:11.541210 Exit from Gating configuration <<<<
2307 09:31:11.541295 Enter into DVFS_PRE_config >>>>>
2308 09:31:11.541382 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2309 09:31:11.541468 Exit from DVFS_PRE_config <<<<<
2310 09:31:11.541553 Enter into PICG configuration >>>>
2311 09:31:11.541638 Exit from PICG configuration <<<<
2312 09:31:11.541723 [RX_INPUT] configuration >>>>>
2313 09:31:11.541807 [RX_INPUT] configuration <<<<<
2314 09:31:11.541892 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2315 09:31:11.541978 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2316 09:31:11.542064 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2317 09:31:11.542149 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2318 09:31:11.542235 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2319 09:31:11.542321 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2320 09:31:11.542406 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2321 09:31:11.542491 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2322 09:31:11.542577 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2323 09:31:11.542662 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2324 09:31:11.542747 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2325 09:31:11.542832 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2326 09:31:11.542917 ===================================
2327 09:31:11.543004 LPDDR4 DRAM CONFIGURATION
2328 09:31:11.543080 ===================================
2329 09:31:11.543155 EX_ROW_EN[0] = 0x0
2330 09:31:11.543228 EX_ROW_EN[1] = 0x0
2331 09:31:11.543301 LP4Y_EN = 0x0
2332 09:31:11.543374 WORK_FSP = 0x0
2333 09:31:11.543446 WL = 0x4
2334 09:31:11.543539 RL = 0x4
2335 09:31:11.543632 BL = 0x2
2336 09:31:11.543725 RPST = 0x0
2337 09:31:11.543817 RD_PRE = 0x0
2338 09:31:11.543909 WR_PRE = 0x1
2339 09:31:11.544002 WR_PST = 0x0
2340 09:31:11.544094 DBI_WR = 0x0
2341 09:31:11.544187 DBI_RD = 0x0
2342 09:31:11.544279 OTF = 0x1
2343 09:31:11.544372 ===================================
2344 09:31:11.544465 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2345 09:31:11.544563 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2346 09:31:11.544658 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2347 09:31:11.544752 ===================================
2348 09:31:11.544845 LPDDR4 DRAM CONFIGURATION
2349 09:31:11.544938 ===================================
2350 09:31:11.545032 EX_ROW_EN[0] = 0x10
2351 09:31:11.545124 EX_ROW_EN[1] = 0x0
2352 09:31:11.545217 LP4Y_EN = 0x0
2353 09:31:11.545309 WORK_FSP = 0x0
2354 09:31:11.545402 WL = 0x4
2355 09:31:11.545494 RL = 0x4
2356 09:31:11.545586 BL = 0x2
2357 09:31:11.545678 RPST = 0x0
2358 09:31:11.545771 RD_PRE = 0x0
2359 09:31:11.545863 WR_PRE = 0x1
2360 09:31:11.545968 WR_PST = 0x0
2361 09:31:11.546058 DBI_WR = 0x0
2362 09:31:11.546149 DBI_RD = 0x0
2363 09:31:11.546239 OTF = 0x1
2364 09:31:11.546334 ===================================
2365 09:31:11.546423 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2366 09:31:11.546507 ==
2367 09:31:11.546589 Dram Type= 6, Freq= 0, CH_0, rank 0
2368 09:31:11.546671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2369 09:31:11.546752 ==
2370 09:31:11.546832 [Duty_Offset_Calibration]
2371 09:31:11.546912 B0:2 B1:0 CA:1
2372 09:31:11.546991
2373 09:31:11.547070 [DutyScan_Calibration_Flow] k_type=0
2374 09:31:11.547149
2375 09:31:11.547227 ==CLK 0==
2376 09:31:11.547306 Final CLK duty delay cell = -4
2377 09:31:11.547386 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2378 09:31:11.547465 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2379 09:31:11.547544 [-4] AVG Duty = 4953%(X100)
2380 09:31:11.547623
2381 09:31:11.547702 CH0 CLK Duty spec in!! Max-Min= 156%
2382 09:31:11.547781 [DutyScan_Calibration_Flow] ====Done====
2383 09:31:11.547860
2384 09:31:11.547939 [DutyScan_Calibration_Flow] k_type=1
2385 09:31:11.548017
2386 09:31:11.548095 ==DQS 0 ==
2387 09:31:11.548173 Final DQS duty delay cell = 0
2388 09:31:11.548251 [0] MAX Duty = 5187%(X100), DQS PI = 30
2389 09:31:11.548330 [0] MIN Duty = 4938%(X100), DQS PI = 0
2390 09:31:11.548409 [0] AVG Duty = 5062%(X100)
2391 09:31:11.548486
2392 09:31:11.548605 ==DQS 1 ==
2393 09:31:11.548686 Final DQS duty delay cell = -4
2394 09:31:11.548766 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2395 09:31:11.548845 [-4] MIN Duty = 4907%(X100), DQS PI = 8
2396 09:31:11.548924 [-4] AVG Duty = 5015%(X100)
2397 09:31:11.549002
2398 09:31:11.549080 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2399 09:31:11.549159
2400 09:31:11.549237 CH0 DQS 1 Duty spec in!! Max-Min= 217%
2401 09:31:11.549315 [DutyScan_Calibration_Flow] ====Done====
2402 09:31:11.549394
2403 09:31:11.549473 [DutyScan_Calibration_Flow] k_type=3
2404 09:31:11.549552
2405 09:31:11.549629 ==DQM 0 ==
2406 09:31:11.549708 Final DQM duty delay cell = 0
2407 09:31:11.549787 [0] MAX Duty = 5062%(X100), DQS PI = 24
2408 09:31:11.550079 [0] MIN Duty = 4813%(X100), DQS PI = 0
2409 09:31:11.550171 [0] AVG Duty = 4937%(X100)
2410 09:31:11.550254
2411 09:31:11.550335 ==DQM 1 ==
2412 09:31:11.550416 Final DQM duty delay cell = 0
2413 09:31:11.550496 [0] MAX Duty = 5187%(X100), DQS PI = 48
2414 09:31:11.550576 [0] MIN Duty = 5000%(X100), DQS PI = 10
2415 09:31:11.550657 [0] AVG Duty = 5093%(X100)
2416 09:31:11.550736
2417 09:31:11.550849 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2418 09:31:11.550928
2419 09:31:11.551006 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2420 09:31:11.551086 [DutyScan_Calibration_Flow] ====Done====
2421 09:31:11.551165
2422 09:31:11.551243 [DutyScan_Calibration_Flow] k_type=2
2423 09:31:11.551325
2424 09:31:11.551405 ==DQ 0 ==
2425 09:31:11.551486 Final DQ duty delay cell = -4
2426 09:31:11.551568 [-4] MAX Duty = 5031%(X100), DQS PI = 34
2427 09:31:11.551650 [-4] MIN Duty = 4844%(X100), DQS PI = 14
2428 09:31:11.551732 [-4] AVG Duty = 4937%(X100)
2429 09:31:11.551813
2430 09:31:11.551894 ==DQ 1 ==
2431 09:31:11.551977 Final DQ duty delay cell = 4
2432 09:31:11.552058 [4] MAX Duty = 5093%(X100), DQS PI = 4
2433 09:31:11.552135 [4] MIN Duty = 5000%(X100), DQS PI = 18
2434 09:31:11.552212 [4] AVG Duty = 5046%(X100)
2435 09:31:11.552288
2436 09:31:11.552363 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2437 09:31:11.552445
2438 09:31:11.552526 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2439 09:31:11.552644 [DutyScan_Calibration_Flow] ====Done====
2440 09:31:11.552727 ==
2441 09:31:11.552809 Dram Type= 6, Freq= 0, CH_1, rank 0
2442 09:31:11.552892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2443 09:31:11.552975 ==
2444 09:31:11.553058 [Duty_Offset_Calibration]
2445 09:31:11.553139 B0:0 B1:-1 CA:2
2446 09:31:11.553220
2447 09:31:11.553298 [DutyScan_Calibration_Flow] k_type=0
2448 09:31:11.553387
2449 09:31:11.553482 ==CLK 0==
2450 09:31:11.553577 Final CLK duty delay cell = 0
2451 09:31:11.553673 [0] MAX Duty = 5156%(X100), DQS PI = 16
2452 09:31:11.553769 [0] MIN Duty = 4938%(X100), DQS PI = 44
2453 09:31:11.553866 [0] AVG Duty = 5047%(X100)
2454 09:31:11.553972
2455 09:31:11.554066 CH1 CLK Duty spec in!! Max-Min= 218%
2456 09:31:11.554155 [DutyScan_Calibration_Flow] ====Done====
2457 09:31:11.554240
2458 09:31:11.554324 [DutyScan_Calibration_Flow] k_type=1
2459 09:31:11.554407
2460 09:31:11.554489 ==DQS 0 ==
2461 09:31:11.554573 Final DQS duty delay cell = 0
2462 09:31:11.554656 [0] MAX Duty = 5093%(X100), DQS PI = 26
2463 09:31:11.554738 [0] MIN Duty = 4969%(X100), DQS PI = 0
2464 09:31:11.554820 [0] AVG Duty = 5031%(X100)
2465 09:31:11.554901
2466 09:31:11.554982 ==DQS 1 ==
2467 09:31:11.555064 Final DQS duty delay cell = 0
2468 09:31:11.555147 [0] MAX Duty = 5156%(X100), DQS PI = 0
2469 09:31:11.555229 [0] MIN Duty = 4844%(X100), DQS PI = 36
2470 09:31:11.555310 [0] AVG Duty = 5000%(X100)
2471 09:31:11.555391
2472 09:31:11.555472 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2473 09:31:11.555553
2474 09:31:11.555634 CH1 DQS 1 Duty spec in!! Max-Min= 312%
2475 09:31:11.555715 [DutyScan_Calibration_Flow] ====Done====
2476 09:31:11.555796
2477 09:31:11.555877 [DutyScan_Calibration_Flow] k_type=3
2478 09:31:11.555958
2479 09:31:11.556039 ==DQM 0 ==
2480 09:31:11.556120 Final DQM duty delay cell = 4
2481 09:31:11.556202 [4] MAX Duty = 5093%(X100), DQS PI = 22
2482 09:31:11.556284 [4] MIN Duty = 4938%(X100), DQS PI = 32
2483 09:31:11.556365 [4] AVG Duty = 5015%(X100)
2484 09:31:11.556446
2485 09:31:11.556527 ==DQM 1 ==
2486 09:31:11.556652 Final DQM duty delay cell = 0
2487 09:31:11.556735 [0] MAX Duty = 5249%(X100), DQS PI = 0
2488 09:31:11.556817 [0] MIN Duty = 4875%(X100), DQS PI = 36
2489 09:31:11.556899 [0] AVG Duty = 5062%(X100)
2490 09:31:11.556980
2491 09:31:11.557061 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2492 09:31:11.557142
2493 09:31:11.557223 CH1 DQM 1 Duty spec in!! Max-Min= 374%
2494 09:31:11.557305 [DutyScan_Calibration_Flow] ====Done====
2495 09:31:11.557385
2496 09:31:11.557467 [DutyScan_Calibration_Flow] k_type=2
2497 09:31:11.557548
2498 09:31:11.557628 ==DQ 0 ==
2499 09:31:11.557709 Final DQ duty delay cell = 0
2500 09:31:11.557792 [0] MAX Duty = 5031%(X100), DQS PI = 18
2501 09:31:11.557873 [0] MIN Duty = 4938%(X100), DQS PI = 0
2502 09:31:11.557954 [0] AVG Duty = 4984%(X100)
2503 09:31:11.558035
2504 09:31:11.558115 ==DQ 1 ==
2505 09:31:11.558197 Final DQ duty delay cell = 0
2506 09:31:11.558279 [0] MAX Duty = 5031%(X100), DQS PI = 2
2507 09:31:11.558361 [0] MIN Duty = 4813%(X100), DQS PI = 34
2508 09:31:11.558442 [0] AVG Duty = 4922%(X100)
2509 09:31:11.558523
2510 09:31:11.558604 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2511 09:31:11.558685
2512 09:31:11.558766 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2513 09:31:11.558848 [DutyScan_Calibration_Flow] ====Done====
2514 09:31:11.558929 nWR fixed to 30
2515 09:31:11.559011 [ModeRegInit_LP4] CH0 RK0
2516 09:31:11.559092 [ModeRegInit_LP4] CH0 RK1
2517 09:31:11.559173 [ModeRegInit_LP4] CH1 RK0
2518 09:31:11.559254 [ModeRegInit_LP4] CH1 RK1
2519 09:31:11.559334 match AC timing 7
2520 09:31:11.559416 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2521 09:31:11.559498 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2522 09:31:11.559580 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2523 09:31:11.559662 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2524 09:31:11.559744 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2525 09:31:11.559825 ==
2526 09:31:11.559907 Dram Type= 6, Freq= 0, CH_0, rank 0
2527 09:31:11.559989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2528 09:31:11.560070 ==
2529 09:31:11.560152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2530 09:31:11.560236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2531 09:31:11.560318 [CA 0] Center 38 (8~69) winsize 62
2532 09:31:11.560400 [CA 1] Center 38 (7~69) winsize 63
2533 09:31:11.560481 [CA 2] Center 35 (5~66) winsize 62
2534 09:31:11.560598 [CA 3] Center 35 (4~66) winsize 63
2535 09:31:11.560681 [CA 4] Center 34 (4~65) winsize 62
2536 09:31:11.560762 [CA 5] Center 33 (3~63) winsize 61
2537 09:31:11.560843
2538 09:31:11.560924 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2539 09:31:11.561005
2540 09:31:11.561087 [CATrainingPosCal] consider 1 rank data
2541 09:31:11.561173 u2DelayCellTimex100 = 270/100 ps
2542 09:31:11.561255 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2543 09:31:11.561337 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2544 09:31:11.561418 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2545 09:31:11.561500 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2546 09:31:11.561581 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2547 09:31:11.561662 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2548 09:31:11.561742
2549 09:31:11.561824 CA PerBit enable=1, Macro0, CA PI delay=33
2550 09:31:11.561905
2551 09:31:11.561986 [CBTSetCACLKResult] CA Dly = 33
2552 09:31:11.562067 CS Dly: 6 (0~37)
2553 09:31:11.562148 ==
2554 09:31:11.562229 Dram Type= 6, Freq= 0, CH_0, rank 1
2555 09:31:11.562311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2556 09:31:11.562392 ==
2557 09:31:11.562670 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2558 09:31:11.562758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2559 09:31:11.562828 [CA 0] Center 39 (8~70) winsize 63
2560 09:31:11.562883 [CA 1] Center 38 (8~69) winsize 62
2561 09:31:11.562936 [CA 2] Center 35 (5~66) winsize 62
2562 09:31:11.562988 [CA 3] Center 35 (5~66) winsize 62
2563 09:31:11.563041 [CA 4] Center 34 (4~65) winsize 62
2564 09:31:11.563093 [CA 5] Center 34 (4~64) winsize 61
2565 09:31:11.563144
2566 09:31:11.563195 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2567 09:31:11.563247
2568 09:31:11.563297 [CATrainingPosCal] consider 2 rank data
2569 09:31:11.563350 u2DelayCellTimex100 = 270/100 ps
2570 09:31:11.563402 CA0 delay=38 (8~69),Diff = 5 PI (24 cell)
2571 09:31:11.563454 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2572 09:31:11.563506 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2573 09:31:11.563557 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2574 09:31:11.563608 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2575 09:31:11.563659 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2576 09:31:11.563710
2577 09:31:11.563761 CA PerBit enable=1, Macro0, CA PI delay=33
2578 09:31:11.563813
2579 09:31:11.563863 [CBTSetCACLKResult] CA Dly = 33
2580 09:31:11.563915 CS Dly: 7 (0~39)
2581 09:31:11.563966
2582 09:31:11.564018 ----->DramcWriteLeveling(PI) begin...
2583 09:31:11.564070 ==
2584 09:31:11.564122 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 09:31:11.564173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 09:31:11.564225 ==
2587 09:31:11.564277 Write leveling (Byte 0): 33 => 33
2588 09:31:11.564328 Write leveling (Byte 1): 31 => 31
2589 09:31:11.564380 DramcWriteLeveling(PI) end<-----
2590 09:31:11.564431
2591 09:31:11.564482 ==
2592 09:31:11.564533 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 09:31:11.564645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 09:31:11.564699 ==
2595 09:31:11.564750 [Gating] SW mode calibration
2596 09:31:11.564802 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2597 09:31:11.564854 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2598 09:31:11.564906 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2599 09:31:11.564959 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2600 09:31:11.565010 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 09:31:11.565062 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 09:31:11.565113 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 09:31:11.565165 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 09:31:11.565216 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2605 09:31:11.565268 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 0)
2606 09:31:11.565319 1 0 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
2607 09:31:11.565372 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 09:31:11.565424 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 09:31:11.565475 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 09:31:11.565527 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 09:31:11.565578 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 09:31:11.565634 1 0 24 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2613 09:31:11.565691 1 0 28 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2614 09:31:11.565742 1 1 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
2615 09:31:11.565794 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 09:31:11.565846 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 09:31:11.565897 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 09:31:11.565948 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 09:31:11.565999 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 09:31:11.566051 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 09:31:11.566103 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2622 09:31:11.566154 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2623 09:31:11.566205 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 09:31:11.566257 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 09:31:11.566308 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 09:31:11.566360 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 09:31:11.566411 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 09:31:11.566462 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 09:31:11.566513 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 09:31:11.566564 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 09:31:11.566615 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 09:31:11.566667 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 09:31:11.566718 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 09:31:11.566769 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 09:31:11.566820 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 09:31:11.566871 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 09:31:11.566923 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2638 09:31:11.566974 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2639 09:31:11.567026 Total UI for P1: 0, mck2ui 16
2640 09:31:11.567078 best dqsien dly found for B0: ( 1, 3, 28)
2641 09:31:11.567131 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2642 09:31:11.567182 Total UI for P1: 0, mck2ui 16
2643 09:31:11.567234 best dqsien dly found for B1: ( 1, 4, 0)
2644 09:31:11.567286 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2645 09:31:11.567338 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2646 09:31:11.567390
2647 09:31:11.567441 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2648 09:31:11.567492 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2649 09:31:11.567544 [Gating] SW calibration Done
2650 09:31:11.567595 ==
2651 09:31:11.567646 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 09:31:11.567697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 09:31:11.567749 ==
2654 09:31:11.567800 RX Vref Scan: 0
2655 09:31:11.567851
2656 09:31:11.567902 RX Vref 0 -> 0, step: 1
2657 09:31:11.567954
2658 09:31:11.568005 RX Delay -40 -> 252, step: 8
2659 09:31:11.568056 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2660 09:31:11.568108 iDelay=200, Bit 1, Center 127 (56 ~ 199) 144
2661 09:31:11.568160 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2662 09:31:11.568405 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2663 09:31:11.568463 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2664 09:31:11.568516 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2665 09:31:11.568593 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2666 09:31:11.568659 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2667 09:31:11.568710 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2668 09:31:11.568762 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2669 09:31:11.568813 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2670 09:31:11.568865 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2671 09:31:11.568916 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2672 09:31:11.568968 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2673 09:31:11.569019 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2674 09:31:11.569071 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2675 09:31:11.569122 ==
2676 09:31:11.569173 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 09:31:11.569226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 09:31:11.569278 ==
2679 09:31:11.569331 DQS Delay:
2680 09:31:11.569382 DQS0 = 0, DQS1 = 0
2681 09:31:11.569434 DQM Delay:
2682 09:31:11.569486 DQM0 = 122, DQM1 = 110
2683 09:31:11.569538 DQ Delay:
2684 09:31:11.569589 DQ0 =119, DQ1 =127, DQ2 =119, DQ3 =119
2685 09:31:11.569641 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2686 09:31:11.569693 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2687 09:31:11.569745 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2688 09:31:11.569797
2689 09:31:11.569847
2690 09:31:11.569899 ==
2691 09:31:11.569950 Dram Type= 6, Freq= 0, CH_0, rank 0
2692 09:31:11.570002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2693 09:31:11.570054 ==
2694 09:31:11.570105
2695 09:31:11.570156
2696 09:31:11.570207 TX Vref Scan disable
2697 09:31:11.570258 == TX Byte 0 ==
2698 09:31:11.570310 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2699 09:31:11.570361 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2700 09:31:11.570412 == TX Byte 1 ==
2701 09:31:11.570463 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2702 09:31:11.570514 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2703 09:31:11.570565 ==
2704 09:31:11.570617 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 09:31:11.570668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 09:31:11.570721 ==
2707 09:31:11.570772 TX Vref=22, minBit 4, minWin=24, winSum=409
2708 09:31:11.570824 TX Vref=24, minBit 0, minWin=25, winSum=416
2709 09:31:11.570876 TX Vref=26, minBit 0, minWin=25, winSum=414
2710 09:31:11.570928 TX Vref=28, minBit 1, minWin=25, winSum=422
2711 09:31:11.570979 TX Vref=30, minBit 1, minWin=25, winSum=423
2712 09:31:11.571031 TX Vref=32, minBit 3, minWin=25, winSum=422
2713 09:31:11.571083 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 30
2714 09:31:11.571135
2715 09:31:11.571185 Final TX Range 1 Vref 30
2716 09:31:11.571237
2717 09:31:11.571288 ==
2718 09:31:11.571339 Dram Type= 6, Freq= 0, CH_0, rank 0
2719 09:31:11.571391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2720 09:31:11.571443 ==
2721 09:31:11.571495
2722 09:31:11.571547
2723 09:31:11.571597 TX Vref Scan disable
2724 09:31:11.571649 == TX Byte 0 ==
2725 09:31:11.571701 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2726 09:31:11.571752 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2727 09:31:11.571804 == TX Byte 1 ==
2728 09:31:11.571855 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2729 09:31:11.571906 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2730 09:31:11.571958
2731 09:31:11.572008 [DATLAT]
2732 09:31:11.572060 Freq=1200, CH0 RK0
2733 09:31:11.572112
2734 09:31:11.572163 DATLAT Default: 0xd
2735 09:31:11.572215 0, 0xFFFF, sum = 0
2736 09:31:11.572268 1, 0xFFFF, sum = 0
2737 09:31:11.572321 2, 0xFFFF, sum = 0
2738 09:31:11.572372 3, 0xFFFF, sum = 0
2739 09:31:11.572424 4, 0xFFFF, sum = 0
2740 09:31:11.572477 5, 0xFFFF, sum = 0
2741 09:31:11.572528 6, 0xFFFF, sum = 0
2742 09:31:11.572627 7, 0xFFFF, sum = 0
2743 09:31:11.572679 8, 0xFFFF, sum = 0
2744 09:31:11.572732 9, 0xFFFF, sum = 0
2745 09:31:11.572784 10, 0xFFFF, sum = 0
2746 09:31:11.572836 11, 0xFFFF, sum = 0
2747 09:31:11.572888 12, 0x0, sum = 1
2748 09:31:11.572940 13, 0x0, sum = 2
2749 09:31:11.572993 14, 0x0, sum = 3
2750 09:31:11.573045 15, 0x0, sum = 4
2751 09:31:11.573097 best_step = 13
2752 09:31:11.573148
2753 09:31:11.573199 ==
2754 09:31:11.573251 Dram Type= 6, Freq= 0, CH_0, rank 0
2755 09:31:11.573303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2756 09:31:11.573355 ==
2757 09:31:11.573406 RX Vref Scan: 1
2758 09:31:11.573457
2759 09:31:11.573508 Set Vref Range= 32 -> 127
2760 09:31:11.573559
2761 09:31:11.573611 RX Vref 32 -> 127, step: 1
2762 09:31:11.573662
2763 09:31:11.573713 RX Delay -13 -> 252, step: 4
2764 09:31:11.573765
2765 09:31:11.573816 Set Vref, RX VrefLevel [Byte0]: 32
2766 09:31:11.573868 [Byte1]: 32
2767 09:31:11.573919
2768 09:31:11.573970 Set Vref, RX VrefLevel [Byte0]: 33
2769 09:31:11.574022 [Byte1]: 33
2770 09:31:11.574073
2771 09:31:11.574123 Set Vref, RX VrefLevel [Byte0]: 34
2772 09:31:11.574175 [Byte1]: 34
2773 09:31:11.574226
2774 09:31:11.574278 Set Vref, RX VrefLevel [Byte0]: 35
2775 09:31:11.574329 [Byte1]: 35
2776 09:31:11.574380
2777 09:31:11.574430 Set Vref, RX VrefLevel [Byte0]: 36
2778 09:31:11.574482 [Byte1]: 36
2779 09:31:11.574533
2780 09:31:11.574584 Set Vref, RX VrefLevel [Byte0]: 37
2781 09:31:11.574635 [Byte1]: 37
2782 09:31:11.574687
2783 09:31:11.574738 Set Vref, RX VrefLevel [Byte0]: 38
2784 09:31:11.574789 [Byte1]: 38
2785 09:31:11.574840
2786 09:31:11.574891 Set Vref, RX VrefLevel [Byte0]: 39
2787 09:31:11.574942 [Byte1]: 39
2788 09:31:11.574993
2789 09:31:11.575044 Set Vref, RX VrefLevel [Byte0]: 40
2790 09:31:11.575096 [Byte1]: 40
2791 09:31:11.575147
2792 09:31:11.575198 Set Vref, RX VrefLevel [Byte0]: 41
2793 09:31:11.575249 [Byte1]: 41
2794 09:31:11.575300
2795 09:31:11.575351 Set Vref, RX VrefLevel [Byte0]: 42
2796 09:31:11.575403 [Byte1]: 42
2797 09:31:11.575454
2798 09:31:11.575505 Set Vref, RX VrefLevel [Byte0]: 43
2799 09:31:11.575555 [Byte1]: 43
2800 09:31:11.575607
2801 09:31:11.575657 Set Vref, RX VrefLevel [Byte0]: 44
2802 09:31:11.575708 [Byte1]: 44
2803 09:31:11.575759
2804 09:31:11.575811 Set Vref, RX VrefLevel [Byte0]: 45
2805 09:31:11.575862 [Byte1]: 45
2806 09:31:11.575913
2807 09:31:11.575964 Set Vref, RX VrefLevel [Byte0]: 46
2808 09:31:11.576016 [Byte1]: 46
2809 09:31:11.576067
2810 09:31:11.576118 Set Vref, RX VrefLevel [Byte0]: 47
2811 09:31:11.576169 [Byte1]: 47
2812 09:31:11.576220
2813 09:31:11.576271 Set Vref, RX VrefLevel [Byte0]: 48
2814 09:31:11.576322 [Byte1]: 48
2815 09:31:11.576373
2816 09:31:11.576424 Set Vref, RX VrefLevel [Byte0]: 49
2817 09:31:11.576475 [Byte1]: 49
2818 09:31:11.576527
2819 09:31:11.576616 Set Vref, RX VrefLevel [Byte0]: 50
2820 09:31:11.576859 [Byte1]: 50
2821 09:31:11.576917
2822 09:31:11.576969 Set Vref, RX VrefLevel [Byte0]: 51
2823 09:31:11.577021 [Byte1]: 51
2824 09:31:11.577073
2825 09:31:11.577125 Set Vref, RX VrefLevel [Byte0]: 52
2826 09:31:11.577176 [Byte1]: 52
2827 09:31:11.577227
2828 09:31:11.577278 Set Vref, RX VrefLevel [Byte0]: 53
2829 09:31:11.577329 [Byte1]: 53
2830 09:31:11.577381
2831 09:31:11.577431 Set Vref, RX VrefLevel [Byte0]: 54
2832 09:31:11.577483 [Byte1]: 54
2833 09:31:11.577534
2834 09:31:11.577585 Set Vref, RX VrefLevel [Byte0]: 55
2835 09:31:11.577636 [Byte1]: 55
2836 09:31:11.577687
2837 09:31:11.577738 Set Vref, RX VrefLevel [Byte0]: 56
2838 09:31:11.577789 [Byte1]: 56
2839 09:31:11.577840
2840 09:31:11.577891 Set Vref, RX VrefLevel [Byte0]: 57
2841 09:31:11.577942 [Byte1]: 57
2842 09:31:11.577994
2843 09:31:11.578044 Set Vref, RX VrefLevel [Byte0]: 58
2844 09:31:11.578095 [Byte1]: 58
2845 09:31:11.578146
2846 09:31:11.578197 Set Vref, RX VrefLevel [Byte0]: 59
2847 09:31:11.578248 [Byte1]: 59
2848 09:31:11.578299
2849 09:31:11.578350 Set Vref, RX VrefLevel [Byte0]: 60
2850 09:31:11.578402 [Byte1]: 60
2851 09:31:11.578453
2852 09:31:11.578504 Set Vref, RX VrefLevel [Byte0]: 61
2853 09:31:11.578556 [Byte1]: 61
2854 09:31:11.578607
2855 09:31:11.578658 Set Vref, RX VrefLevel [Byte0]: 62
2856 09:31:11.578709 [Byte1]: 62
2857 09:31:11.578760
2858 09:31:11.578810 Set Vref, RX VrefLevel [Byte0]: 63
2859 09:31:11.578861 [Byte1]: 63
2860 09:31:11.578912
2861 09:31:11.578963 Set Vref, RX VrefLevel [Byte0]: 64
2862 09:31:11.579014 [Byte1]: 64
2863 09:31:11.579065
2864 09:31:11.579116 Set Vref, RX VrefLevel [Byte0]: 65
2865 09:31:11.579167 [Byte1]: 65
2866 09:31:11.579218
2867 09:31:11.579269 Set Vref, RX VrefLevel [Byte0]: 66
2868 09:31:11.579319 [Byte1]: 66
2869 09:31:11.579370
2870 09:31:11.579420 Set Vref, RX VrefLevel [Byte0]: 67
2871 09:31:11.579471 [Byte1]: 67
2872 09:31:11.579522
2873 09:31:11.579573 Set Vref, RX VrefLevel [Byte0]: 68
2874 09:31:11.579625 [Byte1]: 68
2875 09:31:11.579676
2876 09:31:11.579727 Set Vref, RX VrefLevel [Byte0]: 69
2877 09:31:11.579778 [Byte1]: 69
2878 09:31:11.579829
2879 09:31:11.579880 Set Vref, RX VrefLevel [Byte0]: 70
2880 09:31:11.579931 [Byte1]: 70
2881 09:31:11.579982
2882 09:31:11.580032 Final RX Vref Byte 0 = 59 to rank0
2883 09:31:11.580085 Final RX Vref Byte 1 = 49 to rank0
2884 09:31:11.580136 Final RX Vref Byte 0 = 59 to rank1
2885 09:31:11.580188 Final RX Vref Byte 1 = 49 to rank1==
2886 09:31:11.580240 Dram Type= 6, Freq= 0, CH_0, rank 0
2887 09:31:11.580292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 09:31:11.580344 ==
2889 09:31:11.580395 DQS Delay:
2890 09:31:11.580447 DQS0 = 0, DQS1 = 0
2891 09:31:11.580498 DQM Delay:
2892 09:31:11.580555 DQM0 = 123, DQM1 = 109
2893 09:31:11.580640 DQ Delay:
2894 09:31:11.580692 DQ0 =122, DQ1 =124, DQ2 =118, DQ3 =120
2895 09:31:11.580743 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2896 09:31:11.580795 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2897 09:31:11.580846 DQ12 =114, DQ13 =110, DQ14 =122, DQ15 =116
2898 09:31:11.580897
2899 09:31:11.580949
2900 09:31:11.581000 [DQSOSCAuto] RK0, (LSB)MR18= 0xb08, (MSB)MR19= 0x404, tDQSOscB0 = 406 ps tDQSOscB1 = 405 ps
2901 09:31:11.581053 CH0 RK0: MR19=404, MR18=B08
2902 09:31:11.581104 CH0_RK0: MR19=0x404, MR18=0xB08, DQSOSC=405, MR23=63, INC=39, DEC=26
2903 09:31:11.581156
2904 09:31:11.581207 ----->DramcWriteLeveling(PI) begin...
2905 09:31:11.581260 ==
2906 09:31:11.581312 Dram Type= 6, Freq= 0, CH_0, rank 1
2907 09:31:11.581363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2908 09:31:11.581415 ==
2909 09:31:11.581467 Write leveling (Byte 0): 35 => 35
2910 09:31:11.581518 Write leveling (Byte 1): 30 => 30
2911 09:31:11.581570 DramcWriteLeveling(PI) end<-----
2912 09:31:11.581621
2913 09:31:11.581672 ==
2914 09:31:11.581723 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 09:31:11.581775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 09:31:11.581827 ==
2917 09:31:11.581878 [Gating] SW mode calibration
2918 09:31:11.581929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2919 09:31:11.581981 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2920 09:31:11.582032 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2921 09:31:11.582084 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 09:31:11.582136 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 09:31:11.582187 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 09:31:11.582238 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 09:31:11.582290 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 09:31:11.582366 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 09:31:11.582432 0 15 28 | B1->B0 | 3333 2d2d | 1 1 | (1 1) (1 0)
2928 09:31:11.582483 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 09:31:11.582535 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 09:31:11.582587 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 09:31:11.582639 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 09:31:11.582691 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 09:31:11.582742 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 09:31:11.582793 1 0 24 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
2935 09:31:11.582845 1 0 28 | B1->B0 | 3838 4343 | 0 1 | (0 0) (0 0)
2936 09:31:11.582896 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 09:31:11.582947 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 09:31:11.582998 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 09:31:11.583050 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 09:31:11.583101 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 09:31:11.583152 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 09:31:11.583203 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 09:31:11.583254 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2944 09:31:11.583306 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2945 09:31:11.583357 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 09:31:11.583599 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 09:31:11.583657 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 09:31:11.583710 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 09:31:11.583761 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 09:31:11.583813 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 09:31:11.583864 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 09:31:11.583916 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 09:31:11.583968 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 09:31:11.584019 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 09:31:11.584071 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 09:31:11.584122 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 09:31:11.584173 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 09:31:11.584224 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 09:31:11.584276 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2960 09:31:11.584327 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2961 09:31:11.584379 Total UI for P1: 0, mck2ui 16
2962 09:31:11.584431 best dqsien dly found for B1: ( 1, 3, 28)
2963 09:31:11.584483 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 09:31:11.584535 Total UI for P1: 0, mck2ui 16
2965 09:31:11.584626 best dqsien dly found for B0: ( 1, 3, 30)
2966 09:31:11.584678 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2967 09:31:11.584729 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2968 09:31:11.584781
2969 09:31:11.584831 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2970 09:31:11.584883 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2971 09:31:11.584934 [Gating] SW calibration Done
2972 09:31:11.584986 ==
2973 09:31:11.585038 Dram Type= 6, Freq= 0, CH_0, rank 1
2974 09:31:11.585089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2975 09:31:11.585142 ==
2976 09:31:11.585194 RX Vref Scan: 0
2977 09:31:11.585245
2978 09:31:11.585296 RX Vref 0 -> 0, step: 1
2979 09:31:11.585348
2980 09:31:11.585399 RX Delay -40 -> 252, step: 8
2981 09:31:11.585450 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2982 09:31:11.585502 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2983 09:31:11.585554 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2984 09:31:11.585605 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2985 09:31:11.585656 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2986 09:31:11.585708 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2987 09:31:11.585759 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2988 09:31:11.585810 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2989 09:31:11.585861 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2990 09:31:11.585913 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2991 09:31:11.585964 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2992 09:31:11.586016 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2993 09:31:11.586067 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2994 09:31:11.586119 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2995 09:31:11.586170 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2996 09:31:11.586221 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2997 09:31:11.586272 ==
2998 09:31:11.586324 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 09:31:11.586375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 09:31:11.586427 ==
3001 09:31:11.586479 DQS Delay:
3002 09:31:11.586530 DQS0 = 0, DQS1 = 0
3003 09:31:11.719472 DQM Delay:
3004 09:31:11.720242 DQM0 = 120, DQM1 = 108
3005 09:31:11.720897 DQ Delay:
3006 09:31:11.721482 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
3007 09:31:11.722062 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
3008 09:31:11.722623 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3009 09:31:11.723178 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
3010 09:31:11.723755
3011 09:31:11.724303
3012 09:31:11.724881 ==
3013 09:31:11.725432 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 09:31:11.725975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 09:31:11.726517 ==
3016 09:31:11.727056
3017 09:31:11.727587
3018 09:31:11.728119 TX Vref Scan disable
3019 09:31:11.728685 == TX Byte 0 ==
3020 09:31:11.729233 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3021 09:31:11.729771 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3022 09:31:11.730304 == TX Byte 1 ==
3023 09:31:11.730841 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3024 09:31:11.731379 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3025 09:31:11.731918 ==
3026 09:31:11.732455 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 09:31:11.733077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 09:31:11.733687 ==
3029 09:31:11.734287 TX Vref=22, minBit 3, minWin=23, winSum=408
3030 09:31:11.734869 TX Vref=24, minBit 1, minWin=25, winSum=418
3031 09:31:11.735430 TX Vref=26, minBit 7, minWin=24, winSum=416
3032 09:31:11.735991 TX Vref=28, minBit 4, minWin=25, winSum=425
3033 09:31:11.736544 TX Vref=30, minBit 5, minWin=25, winSum=426
3034 09:31:11.737127 TX Vref=32, minBit 3, minWin=25, winSum=425
3035 09:31:11.737677 [TxChooseVref] Worse bit 5, Min win 25, Win sum 426, Final Vref 30
3036 09:31:11.738222
3037 09:31:11.738756 Final TX Range 1 Vref 30
3038 09:31:11.739295
3039 09:31:11.739823 ==
3040 09:31:11.740360 Dram Type= 6, Freq= 0, CH_0, rank 1
3041 09:31:11.740928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3042 09:31:11.741473 ==
3043 09:31:11.742005
3044 09:31:11.742534
3045 09:31:11.743066 TX Vref Scan disable
3046 09:31:11.743606 == TX Byte 0 ==
3047 09:31:11.744142 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
3048 09:31:11.744703 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
3049 09:31:11.745243 == TX Byte 1 ==
3050 09:31:11.745776 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3051 09:31:11.746205 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3052 09:31:11.746579
3053 09:31:11.746949 [DATLAT]
3054 09:31:11.747321 Freq=1200, CH0 RK1
3055 09:31:11.747699
3056 09:31:11.748073 DATLAT Default: 0xd
3057 09:31:11.748444 0, 0xFFFF, sum = 0
3058 09:31:11.748845 1, 0xFFFF, sum = 0
3059 09:31:11.749231 2, 0xFFFF, sum = 0
3060 09:31:11.749611 3, 0xFFFF, sum = 0
3061 09:31:11.749993 4, 0xFFFF, sum = 0
3062 09:31:11.750374 5, 0xFFFF, sum = 0
3063 09:31:11.750755 6, 0xFFFF, sum = 0
3064 09:31:11.751084 7, 0xFFFF, sum = 0
3065 09:31:11.751359 8, 0xFFFF, sum = 0
3066 09:31:11.751632 9, 0xFFFF, sum = 0
3067 09:31:11.751907 10, 0xFFFF, sum = 0
3068 09:31:11.752184 11, 0xFFFF, sum = 0
3069 09:31:11.752461 12, 0x0, sum = 1
3070 09:31:11.752754 13, 0x0, sum = 2
3071 09:31:11.753032 14, 0x0, sum = 3
3072 09:31:11.753307 15, 0x0, sum = 4
3073 09:31:11.753586 best_step = 13
3074 09:31:11.753859
3075 09:31:11.754130 ==
3076 09:31:11.754407 Dram Type= 6, Freq= 0, CH_0, rank 1
3077 09:31:11.754677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 09:31:11.754954 ==
3079 09:31:11.755228 RX Vref Scan: 0
3080 09:31:11.755501
3081 09:31:11.755772 RX Vref 0 -> 0, step: 1
3082 09:31:11.756037
3083 09:31:11.756570 RX Delay -21 -> 252, step: 4
3084 09:31:11.756818 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3085 09:31:11.757052 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3086 09:31:11.757280 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3087 09:31:11.757505 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3088 09:31:11.757727 iDelay=195, Bit 4, Center 120 (55 ~ 186) 132
3089 09:31:11.757949 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3090 09:31:11.758169 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3091 09:31:11.758390 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3092 09:31:11.758610 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3093 09:31:11.758832 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3094 09:31:11.759052 iDelay=195, Bit 10, Center 108 (47 ~ 170) 124
3095 09:31:11.759271 iDelay=195, Bit 11, Center 104 (43 ~ 166) 124
3096 09:31:11.759488 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3097 09:31:11.759708 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3098 09:31:11.759926 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3099 09:31:11.760144 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3100 09:31:11.760361 ==
3101 09:31:11.760587 Dram Type= 6, Freq= 0, CH_0, rank 1
3102 09:31:11.760811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 09:31:11.761030 ==
3104 09:31:11.761210 DQS Delay:
3105 09:31:11.761391 DQS0 = 0, DQS1 = 0
3106 09:31:11.761572 DQM Delay:
3107 09:31:11.761753 DQM0 = 119, DQM1 = 107
3108 09:31:11.761933 DQ Delay:
3109 09:31:11.762113 DQ0 =118, DQ1 =122, DQ2 =116, DQ3 =112
3110 09:31:11.762294 DQ4 =120, DQ5 =114, DQ6 =126, DQ7 =126
3111 09:31:11.762474 DQ8 =98, DQ9 =94, DQ10 =108, DQ11 =104
3112 09:31:11.762656 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
3113 09:31:11.762835
3114 09:31:11.763013
3115 09:31:11.763195 [DQSOSCAuto] RK1, (LSB)MR18= 0xdf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 405 ps
3116 09:31:11.763382 CH0 RK1: MR19=403, MR18=DF4
3117 09:31:11.763564 CH0_RK1: MR19=0x403, MR18=0xDF4, DQSOSC=405, MR23=63, INC=39, DEC=26
3118 09:31:11.763747 [RxdqsGatingPostProcess] freq 1200
3119 09:31:11.763927 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3120 09:31:11.764110 best DQS0 dly(2T, 0.5T) = (0, 11)
3121 09:31:11.764297 best DQS1 dly(2T, 0.5T) = (0, 12)
3122 09:31:11.764438 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3123 09:31:11.764623 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3124 09:31:11.764782 best DQS0 dly(2T, 0.5T) = (0, 11)
3125 09:31:11.764924 best DQS1 dly(2T, 0.5T) = (0, 11)
3126 09:31:11.765104 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3127 09:31:11.765284 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3128 09:31:11.765462 Pre-setting of DQS Precalculation
3129 09:31:11.765601 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3130 09:31:11.765779 ==
3131 09:31:11.765966 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 09:31:11.766067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 09:31:11.766160 ==
3134 09:31:11.766251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3135 09:31:11.766341 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3136 09:31:11.766432 [CA 0] Center 37 (7~68) winsize 62
3137 09:31:11.766522 [CA 1] Center 37 (7~68) winsize 62
3138 09:31:11.766612 [CA 2] Center 35 (5~65) winsize 61
3139 09:31:11.766701 [CA 3] Center 34 (4~65) winsize 62
3140 09:31:11.766789 [CA 4] Center 34 (3~65) winsize 63
3141 09:31:11.766877 [CA 5] Center 33 (3~64) winsize 62
3142 09:31:11.766965
3143 09:31:11.767052 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3144 09:31:11.767139
3145 09:31:11.767226 [CATrainingPosCal] consider 1 rank data
3146 09:31:11.767314 u2DelayCellTimex100 = 270/100 ps
3147 09:31:11.767401 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3148 09:31:11.767488 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3149 09:31:11.767575 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3150 09:31:11.767663 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3151 09:31:11.767751 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
3152 09:31:11.767838 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3153 09:31:11.767925
3154 09:31:11.768012 CA PerBit enable=1, Macro0, CA PI delay=33
3155 09:31:11.768100
3156 09:31:11.768187 [CBTSetCACLKResult] CA Dly = 33
3157 09:31:11.768275 CS Dly: 5 (0~36)
3158 09:31:11.768362 ==
3159 09:31:11.768450 Dram Type= 6, Freq= 0, CH_1, rank 1
3160 09:31:11.768537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3161 09:31:11.768637 ==
3162 09:31:11.768726 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3163 09:31:11.768816 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3164 09:31:11.768905 [CA 0] Center 38 (8~68) winsize 61
3165 09:31:11.768993 [CA 1] Center 38 (7~69) winsize 63
3166 09:31:11.769081 [CA 2] Center 35 (5~66) winsize 62
3167 09:31:11.769168 [CA 3] Center 35 (5~65) winsize 61
3168 09:31:11.769256 [CA 4] Center 35 (5~65) winsize 61
3169 09:31:11.769344 [CA 5] Center 34 (4~64) winsize 61
3170 09:31:11.769431
3171 09:31:11.769518 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3172 09:31:11.769606
3173 09:31:11.769693 [CATrainingPosCal] consider 2 rank data
3174 09:31:11.769781 u2DelayCellTimex100 = 270/100 ps
3175 09:31:11.769869 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3176 09:31:11.769957 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3177 09:31:11.770045 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3178 09:31:11.770132 CA3 delay=35 (5~65),Diff = 1 PI (4 cell)
3179 09:31:11.770221 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
3180 09:31:11.770308 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3181 09:31:11.770395
3182 09:31:11.770482 CA PerBit enable=1, Macro0, CA PI delay=34
3183 09:31:11.770570
3184 09:31:11.770657 [CBTSetCACLKResult] CA Dly = 34
3185 09:31:11.770745 CS Dly: 6 (0~39)
3186 09:31:11.770832
3187 09:31:11.770931 ----->DramcWriteLeveling(PI) begin...
3188 09:31:11.771009 ==
3189 09:31:11.771086 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 09:31:11.771163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 09:31:11.771239 ==
3192 09:31:11.771316 Write leveling (Byte 0): 25 => 25
3193 09:31:11.771393 Write leveling (Byte 1): 28 => 28
3194 09:31:11.771470 DramcWriteLeveling(PI) end<-----
3195 09:31:11.771546
3196 09:31:11.771622 ==
3197 09:31:11.771699 Dram Type= 6, Freq= 0, CH_1, rank 0
3198 09:31:11.771776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3199 09:31:11.771853 ==
3200 09:31:11.771929 [Gating] SW mode calibration
3201 09:31:11.772006 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3202 09:31:11.772296 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3203 09:31:11.772382 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 09:31:11.772462 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 09:31:11.772540 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 09:31:11.772631 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 09:31:11.772709 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 09:31:11.772786 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3209 09:31:11.772863 0 15 24 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (1 0)
3210 09:31:11.772940 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 09:31:11.773016 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 09:31:11.773093 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 09:31:11.773170 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 09:31:11.773246 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 09:31:11.773322 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 09:31:11.773398 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 09:31:11.773475 1 0 24 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
3218 09:31:11.773551 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 09:31:11.773628 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 09:31:11.773704 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 09:31:11.773781 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 09:31:11.773857 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 09:31:11.773934 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 09:31:11.774010 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 09:31:11.774087 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3226 09:31:11.774163 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3227 09:31:11.774240 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 09:31:11.774316 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 09:31:11.774392 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 09:31:11.774468 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 09:31:11.774545 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 09:31:11.774621 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 09:31:11.774698 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 09:31:11.774775 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 09:31:11.774851 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 09:31:11.774927 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 09:31:11.775003 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 09:31:11.775079 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 09:31:11.775155 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 09:31:11.775231 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3241 09:31:11.775307 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3242 09:31:11.775384 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3243 09:31:11.775460 Total UI for P1: 0, mck2ui 16
3244 09:31:11.775542 best dqsien dly found for B0: ( 1, 3, 22)
3245 09:31:11.775651 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 09:31:11.775756 Total UI for P1: 0, mck2ui 16
3247 09:31:11.775874 best dqsien dly found for B1: ( 1, 3, 24)
3248 09:31:11.776018 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3249 09:31:11.776127 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3250 09:31:11.776234
3251 09:31:11.776341 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3252 09:31:11.776449 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3253 09:31:11.776561 [Gating] SW calibration Done
3254 09:31:11.776635 ==
3255 09:31:11.776704 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 09:31:11.776774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 09:31:11.776843 ==
3258 09:31:11.776912 RX Vref Scan: 0
3259 09:31:11.776980
3260 09:31:11.777048 RX Vref 0 -> 0, step: 1
3261 09:31:11.777115
3262 09:31:11.777184 RX Delay -40 -> 252, step: 8
3263 09:31:11.777252 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3264 09:31:11.777320 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3265 09:31:11.777388 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3266 09:31:11.777457 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3267 09:31:11.777525 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3268 09:31:11.777593 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3269 09:31:11.777660 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3270 09:31:11.777728 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3271 09:31:11.777795 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3272 09:31:11.777864 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3273 09:31:11.777932 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3274 09:31:11.778000 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3275 09:31:11.778068 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3276 09:31:11.778136 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3277 09:31:11.778204 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3278 09:31:11.778271 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3279 09:31:11.778339 ==
3280 09:31:11.778407 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 09:31:11.778475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 09:31:11.778544 ==
3283 09:31:11.778612 DQS Delay:
3284 09:31:11.778679 DQS0 = 0, DQS1 = 0
3285 09:31:11.778747 DQM Delay:
3286 09:31:11.778814 DQM0 = 119, DQM1 = 113
3287 09:31:11.778881 DQ Delay:
3288 09:31:11.778949 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3289 09:31:11.779017 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =119
3290 09:31:11.779085 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3291 09:31:11.779153 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3292 09:31:11.779220
3293 09:31:11.779288
3294 09:31:11.779355 ==
3295 09:31:11.779423 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 09:31:11.779491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 09:31:11.779560 ==
3298 09:31:11.779628
3299 09:31:11.779695
3300 09:31:11.779762 TX Vref Scan disable
3301 09:31:11.779830 == TX Byte 0 ==
3302 09:31:11.779898 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3303 09:31:11.779967 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3304 09:31:11.780034 == TX Byte 1 ==
3305 09:31:11.780102 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3306 09:31:11.780170 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3307 09:31:11.780238 ==
3308 09:31:11.780509 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 09:31:11.780593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 09:31:11.780664 ==
3311 09:31:11.780732 TX Vref=22, minBit 10, minWin=23, winSum=402
3312 09:31:11.780801 TX Vref=24, minBit 1, minWin=24, winSum=409
3313 09:31:11.780870 TX Vref=26, minBit 8, minWin=25, winSum=415
3314 09:31:11.780946 TX Vref=28, minBit 10, minWin=25, winSum=423
3315 09:31:11.781008 TX Vref=30, minBit 10, minWin=25, winSum=421
3316 09:31:11.781070 TX Vref=32, minBit 10, minWin=25, winSum=420
3317 09:31:11.781133 [TxChooseVref] Worse bit 10, Min win 25, Win sum 423, Final Vref 28
3318 09:31:11.781194
3319 09:31:11.781254 Final TX Range 1 Vref 28
3320 09:31:11.781315
3321 09:31:11.781376 ==
3322 09:31:11.781437 Dram Type= 6, Freq= 0, CH_1, rank 0
3323 09:31:11.781498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3324 09:31:11.781560 ==
3325 09:31:11.781621
3326 09:31:11.781681
3327 09:31:11.781742 TX Vref Scan disable
3328 09:31:11.781802 == TX Byte 0 ==
3329 09:31:11.781863 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3330 09:31:11.781925 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3331 09:31:11.781985 == TX Byte 1 ==
3332 09:31:11.782046 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3333 09:31:11.782108 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3334 09:31:11.782169
3335 09:31:11.782229 [DATLAT]
3336 09:31:11.782290 Freq=1200, CH1 RK0
3337 09:31:11.782351
3338 09:31:11.782412 DATLAT Default: 0xd
3339 09:31:11.782474 0, 0xFFFF, sum = 0
3340 09:31:11.782537 1, 0xFFFF, sum = 0
3341 09:31:11.782600 2, 0xFFFF, sum = 0
3342 09:31:11.782662 3, 0xFFFF, sum = 0
3343 09:31:11.782724 4, 0xFFFF, sum = 0
3344 09:31:11.782787 5, 0xFFFF, sum = 0
3345 09:31:11.782849 6, 0xFFFF, sum = 0
3346 09:31:11.782910 7, 0xFFFF, sum = 0
3347 09:31:11.782972 8, 0xFFFF, sum = 0
3348 09:31:11.783034 9, 0xFFFF, sum = 0
3349 09:31:11.783096 10, 0xFFFF, sum = 0
3350 09:31:11.783158 11, 0xFFFF, sum = 0
3351 09:31:11.783220 12, 0x0, sum = 1
3352 09:31:11.783282 13, 0x0, sum = 2
3353 09:31:11.783344 14, 0x0, sum = 3
3354 09:31:11.783406 15, 0x0, sum = 4
3355 09:31:11.783468 best_step = 13
3356 09:31:11.783529
3357 09:31:11.783589 ==
3358 09:31:11.783650 Dram Type= 6, Freq= 0, CH_1, rank 0
3359 09:31:11.783711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3360 09:31:11.783773 ==
3361 09:31:11.783833 RX Vref Scan: 1
3362 09:31:11.783892
3363 09:31:11.783951 Set Vref Range= 32 -> 127
3364 09:31:11.784011
3365 09:31:11.784069 RX Vref 32 -> 127, step: 1
3366 09:31:11.784128
3367 09:31:11.784186 RX Delay -13 -> 252, step: 4
3368 09:31:11.784245
3369 09:31:11.784303 Set Vref, RX VrefLevel [Byte0]: 32
3370 09:31:11.784362 [Byte1]: 32
3371 09:31:11.784421
3372 09:31:11.784479 Set Vref, RX VrefLevel [Byte0]: 33
3373 09:31:11.784538 [Byte1]: 33
3374 09:31:11.784601
3375 09:31:11.784660 Set Vref, RX VrefLevel [Byte0]: 34
3376 09:31:11.784718 [Byte1]: 34
3377 09:31:11.784777
3378 09:31:11.784835 Set Vref, RX VrefLevel [Byte0]: 35
3379 09:31:11.784893 [Byte1]: 35
3380 09:31:11.784953
3381 09:31:11.785011 Set Vref, RX VrefLevel [Byte0]: 36
3382 09:31:11.785070 [Byte1]: 36
3383 09:31:11.785129
3384 09:31:11.785187 Set Vref, RX VrefLevel [Byte0]: 37
3385 09:31:11.785245 [Byte1]: 37
3386 09:31:11.785303
3387 09:31:11.785361 Set Vref, RX VrefLevel [Byte0]: 38
3388 09:31:11.785419 [Byte1]: 38
3389 09:31:11.785478
3390 09:31:11.785537 Set Vref, RX VrefLevel [Byte0]: 39
3391 09:31:11.785596 [Byte1]: 39
3392 09:31:11.785655
3393 09:31:11.785714 Set Vref, RX VrefLevel [Byte0]: 40
3394 09:31:11.785772 [Byte1]: 40
3395 09:31:11.785831
3396 09:31:11.785889 Set Vref, RX VrefLevel [Byte0]: 41
3397 09:31:11.785961 [Byte1]: 41
3398 09:31:11.786013
3399 09:31:11.786067 Set Vref, RX VrefLevel [Byte0]: 42
3400 09:31:11.786120 [Byte1]: 42
3401 09:31:11.786172
3402 09:31:11.786225 Set Vref, RX VrefLevel [Byte0]: 43
3403 09:31:11.786278 [Byte1]: 43
3404 09:31:11.786333
3405 09:31:11.786385 Set Vref, RX VrefLevel [Byte0]: 44
3406 09:31:11.786439 [Byte1]: 44
3407 09:31:11.786491
3408 09:31:11.786544 Set Vref, RX VrefLevel [Byte0]: 45
3409 09:31:11.786597 [Byte1]: 45
3410 09:31:11.786650
3411 09:31:11.786703 Set Vref, RX VrefLevel [Byte0]: 46
3412 09:31:11.786756 [Byte1]: 46
3413 09:31:11.786809
3414 09:31:11.786862 Set Vref, RX VrefLevel [Byte0]: 47
3415 09:31:11.786915 [Byte1]: 47
3416 09:31:11.786968
3417 09:31:11.787021 Set Vref, RX VrefLevel [Byte0]: 48
3418 09:31:11.787075 [Byte1]: 48
3419 09:31:11.787128
3420 09:31:11.787181 Set Vref, RX VrefLevel [Byte0]: 49
3421 09:31:11.787235 [Byte1]: 49
3422 09:31:11.787288
3423 09:31:11.787340 Set Vref, RX VrefLevel [Byte0]: 50
3424 09:31:11.787393 [Byte1]: 50
3425 09:31:11.787447
3426 09:31:11.787500 Set Vref, RX VrefLevel [Byte0]: 51
3427 09:31:11.787553 [Byte1]: 51
3428 09:31:11.787605
3429 09:31:11.787659 Set Vref, RX VrefLevel [Byte0]: 52
3430 09:31:11.787712 [Byte1]: 52
3431 09:31:11.787765
3432 09:31:11.787818 Set Vref, RX VrefLevel [Byte0]: 53
3433 09:31:11.787871 [Byte1]: 53
3434 09:31:11.787924
3435 09:31:11.787978 Set Vref, RX VrefLevel [Byte0]: 54
3436 09:31:11.788031 [Byte1]: 54
3437 09:31:11.788085
3438 09:31:11.788137 Set Vref, RX VrefLevel [Byte0]: 55
3439 09:31:11.788190 [Byte1]: 55
3440 09:31:11.788244
3441 09:31:11.788296 Set Vref, RX VrefLevel [Byte0]: 56
3442 09:31:11.788351 [Byte1]: 56
3443 09:31:11.788404
3444 09:31:11.788457 Set Vref, RX VrefLevel [Byte0]: 57
3445 09:31:11.788510 [Byte1]: 57
3446 09:31:11.788569
3447 09:31:11.788623 Set Vref, RX VrefLevel [Byte0]: 58
3448 09:31:11.788676 [Byte1]: 58
3449 09:31:11.788730
3450 09:31:11.788783 Set Vref, RX VrefLevel [Byte0]: 59
3451 09:31:11.788836 [Byte1]: 59
3452 09:31:11.788889
3453 09:31:11.788942 Set Vref, RX VrefLevel [Byte0]: 60
3454 09:31:11.788995 [Byte1]: 60
3455 09:31:11.789049
3456 09:31:11.789102 Set Vref, RX VrefLevel [Byte0]: 61
3457 09:31:11.789155 [Byte1]: 61
3458 09:31:11.789209
3459 09:31:11.789262 Set Vref, RX VrefLevel [Byte0]: 62
3460 09:31:11.789315 [Byte1]: 62
3461 09:31:11.789368
3462 09:31:11.789422 Set Vref, RX VrefLevel [Byte0]: 63
3463 09:31:11.789475 [Byte1]: 63
3464 09:31:11.789528
3465 09:31:11.789581 Set Vref, RX VrefLevel [Byte0]: 64
3466 09:31:11.789634 [Byte1]: 64
3467 09:31:11.789687
3468 09:31:11.789740 Set Vref, RX VrefLevel [Byte0]: 65
3469 09:31:11.789793 [Byte1]: 65
3470 09:31:11.789847
3471 09:31:11.789900 Set Vref, RX VrefLevel [Byte0]: 66
3472 09:31:11.789954 [Byte1]: 66
3473 09:31:11.790007
3474 09:31:11.790060 Set Vref, RX VrefLevel [Byte0]: 67
3475 09:31:11.790307 [Byte1]: 67
3476 09:31:11.790366
3477 09:31:11.790420 Final RX Vref Byte 0 = 51 to rank0
3478 09:31:11.790475 Final RX Vref Byte 1 = 53 to rank0
3479 09:31:11.790529 Final RX Vref Byte 0 = 51 to rank1
3480 09:31:11.790584 Final RX Vref Byte 1 = 53 to rank1==
3481 09:31:11.790637 Dram Type= 6, Freq= 0, CH_1, rank 0
3482 09:31:11.790692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3483 09:31:11.790746 ==
3484 09:31:11.790799 DQS Delay:
3485 09:31:11.790852 DQS0 = 0, DQS1 = 0
3486 09:31:11.790906 DQM Delay:
3487 09:31:11.790970 DQM0 = 119, DQM1 = 112
3488 09:31:11.791021 DQ Delay:
3489 09:31:11.791072 DQ0 =120, DQ1 =112, DQ2 =112, DQ3 =116
3490 09:31:11.791123 DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =116
3491 09:31:11.791173 DQ8 =102, DQ9 =98, DQ10 =114, DQ11 =106
3492 09:31:11.791224 DQ12 =122, DQ13 =118, DQ14 =120, DQ15 =118
3493 09:31:11.791275
3494 09:31:11.791325
3495 09:31:11.791392 [DQSOSCAuto] RK0, (LSB)MR18= 0x114, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3496 09:31:11.791458 CH1 RK0: MR19=404, MR18=114
3497 09:31:11.791508 CH1_RK0: MR19=0x404, MR18=0x114, DQSOSC=402, MR23=63, INC=40, DEC=27
3498 09:31:11.791559
3499 09:31:11.791609 ----->DramcWriteLeveling(PI) begin...
3500 09:31:11.791662 ==
3501 09:31:11.791712 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 09:31:11.791762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 09:31:11.791813 ==
3504 09:31:11.791863 Write leveling (Byte 0): 24 => 24
3505 09:31:11.791914 Write leveling (Byte 1): 29 => 29
3506 09:31:11.791964 DramcWriteLeveling(PI) end<-----
3507 09:31:11.792015
3508 09:31:11.792064 ==
3509 09:31:11.792115 Dram Type= 6, Freq= 0, CH_1, rank 1
3510 09:31:11.792165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3511 09:31:11.792216 ==
3512 09:31:11.792266 [Gating] SW mode calibration
3513 09:31:11.792317 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3514 09:31:11.792367 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3515 09:31:11.792434 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3516 09:31:11.792501 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 09:31:11.792560 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 09:31:11.792626 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 09:31:11.792677 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 09:31:11.792729 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 09:31:11.792794 0 15 24 | B1->B0 | 2c2c 3434 | 0 0 | (1 0) (0 1)
3522 09:31:11.792860 0 15 28 | B1->B0 | 2323 2b2b | 0 0 | (1 0) (1 0)
3523 09:31:11.792912 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3524 09:31:11.792976 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 09:31:11.793027 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 09:31:11.793078 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 09:31:11.793128 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 09:31:11.793179 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 09:31:11.793229 1 0 24 | B1->B0 | 3f3f 2929 | 0 1 | (0 0) (0 0)
3530 09:31:11.793280 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3531 09:31:11.793330 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 09:31:11.793380 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 09:31:11.793446 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 09:31:11.793533 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 09:31:11.793605 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 09:31:11.793671 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 09:31:11.793755 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3538 09:31:11.793857 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3539 09:31:11.793959 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 09:31:11.794062 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 09:31:11.794112 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 09:31:11.794163 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 09:31:11.794214 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 09:31:11.794264 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 09:31:11.794314 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 09:31:11.794364 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 09:31:11.794414 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 09:31:11.794469 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 09:31:11.794536 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 09:31:11.794587 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 09:31:11.794651 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 09:31:11.794701 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 09:31:11.794804 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3554 09:31:11.794856 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3555 09:31:11.794907 Total UI for P1: 0, mck2ui 16
3556 09:31:11.794974 best dqsien dly found for B1: ( 1, 3, 24)
3557 09:31:11.795040 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 09:31:11.795121 Total UI for P1: 0, mck2ui 16
3559 09:31:11.795174 best dqsien dly found for B0: ( 1, 3, 26)
3560 09:31:11.795226 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3561 09:31:11.795295 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3562 09:31:11.795378
3563 09:31:11.795458 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3564 09:31:11.795535 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3565 09:31:11.795618 [Gating] SW calibration Done
3566 09:31:11.795670 ==
3567 09:31:11.795722 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 09:31:11.795773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 09:31:11.795824 ==
3570 09:31:11.795876 RX Vref Scan: 0
3571 09:31:11.795927
3572 09:31:11.795978 RX Vref 0 -> 0, step: 1
3573 09:31:11.796029
3574 09:31:11.796079 RX Delay -40 -> 252, step: 8
3575 09:31:11.796143 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3576 09:31:11.796193 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3577 09:31:11.796243 iDelay=200, Bit 2, Center 107 (48 ~ 167) 120
3578 09:31:11.796320 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3579 09:31:11.796370 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3580 09:31:11.796420 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3581 09:31:11.796669 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3582 09:31:11.796727 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3583 09:31:11.796780 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3584 09:31:11.796831 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3585 09:31:11.796881 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3586 09:31:11.796932 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3587 09:31:11.796982 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3588 09:31:11.797032 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3589 09:31:11.797083 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3590 09:31:11.797134 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3591 09:31:11.797184 ==
3592 09:31:11.797235 Dram Type= 6, Freq= 0, CH_1, rank 1
3593 09:31:11.797285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3594 09:31:11.797336 ==
3595 09:31:11.797386 DQS Delay:
3596 09:31:11.797436 DQS0 = 0, DQS1 = 0
3597 09:31:11.797486 DQM Delay:
3598 09:31:11.797537 DQM0 = 119, DQM1 = 112
3599 09:31:11.797588 DQ Delay:
3600 09:31:11.797666 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =119
3601 09:31:11.797754 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3602 09:31:11.797804 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3603 09:31:11.797855 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3604 09:31:11.797905
3605 09:31:11.797955
3606 09:31:11.798005 ==
3607 09:31:11.798056 Dram Type= 6, Freq= 0, CH_1, rank 1
3608 09:31:11.798106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3609 09:31:11.798157 ==
3610 09:31:11.798208
3611 09:31:11.798257
3612 09:31:11.798307 TX Vref Scan disable
3613 09:31:11.798357 == TX Byte 0 ==
3614 09:31:11.798407 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3615 09:31:11.798465 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3616 09:31:11.798519 == TX Byte 1 ==
3617 09:31:11.798570 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3618 09:31:11.798621 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3619 09:31:11.798671 ==
3620 09:31:11.798722 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 09:31:11.798772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 09:31:11.798823 ==
3623 09:31:11.798874 TX Vref=22, minBit 1, minWin=25, winSum=416
3624 09:31:11.798925 TX Vref=24, minBit 9, minWin=25, winSum=420
3625 09:31:11.798976 TX Vref=26, minBit 9, minWin=25, winSum=423
3626 09:31:11.799027 TX Vref=28, minBit 1, minWin=26, winSum=428
3627 09:31:11.799078 TX Vref=30, minBit 9, minWin=25, winSum=428
3628 09:31:11.799129 TX Vref=32, minBit 1, minWin=26, winSum=429
3629 09:31:11.799180 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 32
3630 09:31:11.799245
3631 09:31:11.799323 Final TX Range 1 Vref 32
3632 09:31:11.799413
3633 09:31:11.799463 ==
3634 09:31:11.799513 Dram Type= 6, Freq= 0, CH_1, rank 1
3635 09:31:11.799563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3636 09:31:11.799613 ==
3637 09:31:11.799663
3638 09:31:11.799713
3639 09:31:11.799762 TX Vref Scan disable
3640 09:31:11.799813 == TX Byte 0 ==
3641 09:31:11.799863 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3642 09:31:11.799914 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3643 09:31:11.799964 == TX Byte 1 ==
3644 09:31:11.800015 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3645 09:31:11.800065 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3646 09:31:11.800115
3647 09:31:11.800165 [DATLAT]
3648 09:31:11.800215 Freq=1200, CH1 RK1
3649 09:31:11.800266
3650 09:31:11.800316 DATLAT Default: 0xd
3651 09:31:11.800366 0, 0xFFFF, sum = 0
3652 09:31:11.800418 1, 0xFFFF, sum = 0
3653 09:31:11.800469 2, 0xFFFF, sum = 0
3654 09:31:11.800520 3, 0xFFFF, sum = 0
3655 09:31:11.800596 4, 0xFFFF, sum = 0
3656 09:31:11.800675 5, 0xFFFF, sum = 0
3657 09:31:11.800726 6, 0xFFFF, sum = 0
3658 09:31:11.800776 7, 0xFFFF, sum = 0
3659 09:31:11.800827 8, 0xFFFF, sum = 0
3660 09:31:11.800878 9, 0xFFFF, sum = 0
3661 09:31:11.800929 10, 0xFFFF, sum = 0
3662 09:31:11.800981 11, 0xFFFF, sum = 0
3663 09:31:11.801032 12, 0x0, sum = 1
3664 09:31:11.801083 13, 0x0, sum = 2
3665 09:31:11.801134 14, 0x0, sum = 3
3666 09:31:11.801186 15, 0x0, sum = 4
3667 09:31:11.801237 best_step = 13
3668 09:31:11.801287
3669 09:31:11.801337 ==
3670 09:31:11.801387 Dram Type= 6, Freq= 0, CH_1, rank 1
3671 09:31:11.801438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3672 09:31:11.801489 ==
3673 09:31:11.801540 RX Vref Scan: 0
3674 09:31:11.801589
3675 09:31:11.801639 RX Vref 0 -> 0, step: 1
3676 09:31:11.801689
3677 09:31:11.801739 RX Delay -13 -> 252, step: 4
3678 09:31:11.801789 iDelay=191, Bit 0, Center 122 (63 ~ 182) 120
3679 09:31:11.801839 iDelay=191, Bit 1, Center 114 (55 ~ 174) 120
3680 09:31:11.801889 iDelay=191, Bit 2, Center 108 (51 ~ 166) 116
3681 09:31:11.801939 iDelay=191, Bit 3, Center 118 (59 ~ 178) 120
3682 09:31:11.801990 iDelay=191, Bit 4, Center 122 (63 ~ 182) 120
3683 09:31:11.802040 iDelay=191, Bit 5, Center 128 (67 ~ 190) 124
3684 09:31:11.802095 iDelay=191, Bit 6, Center 126 (67 ~ 186) 120
3685 09:31:11.802145 iDelay=191, Bit 7, Center 116 (55 ~ 178) 124
3686 09:31:11.802196 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3687 09:31:11.802246 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3688 09:31:11.802296 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3689 09:31:11.802405 iDelay=191, Bit 11, Center 108 (47 ~ 170) 124
3690 09:31:11.802483 iDelay=191, Bit 12, Center 122 (59 ~ 186) 128
3691 09:31:11.802533 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3692 09:31:11.802583 iDelay=191, Bit 14, Center 122 (59 ~ 186) 128
3693 09:31:11.802633 iDelay=191, Bit 15, Center 124 (59 ~ 190) 132
3694 09:31:11.802684 ==
3695 09:31:11.802734 Dram Type= 6, Freq= 0, CH_1, rank 1
3696 09:31:11.802784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3697 09:31:11.802835 ==
3698 09:31:11.802885 DQS Delay:
3699 09:31:11.802935 DQS0 = 0, DQS1 = 0
3700 09:31:11.802985 DQM Delay:
3701 09:31:11.803035 DQM0 = 119, DQM1 = 113
3702 09:31:11.803085 DQ Delay:
3703 09:31:11.803135 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =118
3704 09:31:11.803185 DQ4 =122, DQ5 =128, DQ6 =126, DQ7 =116
3705 09:31:11.803235 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3706 09:31:11.803285 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3707 09:31:11.803335
3708 09:31:11.803384
3709 09:31:11.803434 [DQSOSCAuto] RK1, (LSB)MR18= 0x7eb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 407 ps
3710 09:31:11.803485 CH1 RK1: MR19=403, MR18=7EB
3711 09:31:11.803536 CH1_RK1: MR19=0x403, MR18=0x7EB, DQSOSC=407, MR23=63, INC=39, DEC=26
3712 09:31:11.803587 [RxdqsGatingPostProcess] freq 1200
3713 09:31:11.803636 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3714 09:31:11.803686 best DQS0 dly(2T, 0.5T) = (0, 11)
3715 09:31:11.803736 best DQS1 dly(2T, 0.5T) = (0, 11)
3716 09:31:11.803787 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3717 09:31:11.803836 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3718 09:31:11.803886 best DQS0 dly(2T, 0.5T) = (0, 11)
3719 09:31:11.804124 best DQS1 dly(2T, 0.5T) = (0, 11)
3720 09:31:11.804181 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3721 09:31:11.804232 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3722 09:31:11.804284 Pre-setting of DQS Precalculation
3723 09:31:11.804335 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3724 09:31:11.804386 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3725 09:31:11.804437 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3726 09:31:11.804488
3727 09:31:11.804539
3728 09:31:11.804642 [Calibration Summary] 2400 Mbps
3729 09:31:11.804693 CH 0, Rank 0
3730 09:31:11.804743 SW Impedance : PASS
3731 09:31:11.804794 DUTY Scan : NO K
3732 09:31:11.804844 ZQ Calibration : PASS
3733 09:31:11.804895 Jitter Meter : NO K
3734 09:31:11.804946 CBT Training : PASS
3735 09:31:11.804996 Write leveling : PASS
3736 09:31:11.805046 RX DQS gating : PASS
3737 09:31:11.805097 RX DQ/DQS(RDDQC) : PASS
3738 09:31:11.805146 TX DQ/DQS : PASS
3739 09:31:11.805197 RX DATLAT : PASS
3740 09:31:11.805247 RX DQ/DQS(Engine): PASS
3741 09:31:11.805298 TX OE : NO K
3742 09:31:11.805363 All Pass.
3743 09:31:11.805431
3744 09:31:11.805481 CH 0, Rank 1
3745 09:31:11.805531 SW Impedance : PASS
3746 09:31:11.805581 DUTY Scan : NO K
3747 09:31:11.805631 ZQ Calibration : PASS
3748 09:31:11.805681 Jitter Meter : NO K
3749 09:31:11.805731 CBT Training : PASS
3750 09:31:11.805782 Write leveling : PASS
3751 09:31:11.805831 RX DQS gating : PASS
3752 09:31:11.805881 RX DQ/DQS(RDDQC) : PASS
3753 09:31:11.805932 TX DQ/DQS : PASS
3754 09:31:11.805982 RX DATLAT : PASS
3755 09:31:11.806032 RX DQ/DQS(Engine): PASS
3756 09:31:11.806082 TX OE : NO K
3757 09:31:11.806132 All Pass.
3758 09:31:11.806182
3759 09:31:11.806232 CH 1, Rank 0
3760 09:31:11.806281 SW Impedance : PASS
3761 09:31:11.806331 DUTY Scan : NO K
3762 09:31:11.806381 ZQ Calibration : PASS
3763 09:31:11.806431 Jitter Meter : NO K
3764 09:31:11.806482 CBT Training : PASS
3765 09:31:11.806532 Write leveling : PASS
3766 09:31:11.806583 RX DQS gating : PASS
3767 09:31:11.806633 RX DQ/DQS(RDDQC) : PASS
3768 09:31:11.806683 TX DQ/DQS : PASS
3769 09:31:11.806733 RX DATLAT : PASS
3770 09:31:11.806783 RX DQ/DQS(Engine): PASS
3771 09:31:11.806833 TX OE : NO K
3772 09:31:11.806884 All Pass.
3773 09:31:11.806934
3774 09:31:11.806984 CH 1, Rank 1
3775 09:31:11.807034 SW Impedance : PASS
3776 09:31:11.807084 DUTY Scan : NO K
3777 09:31:11.807135 ZQ Calibration : PASS
3778 09:31:11.807185 Jitter Meter : NO K
3779 09:31:11.807235 CBT Training : PASS
3780 09:31:11.807285 Write leveling : PASS
3781 09:31:11.807336 RX DQS gating : PASS
3782 09:31:11.807385 RX DQ/DQS(RDDQC) : PASS
3783 09:31:11.807464 TX DQ/DQS : PASS
3784 09:31:11.807514 RX DATLAT : PASS
3785 09:31:11.807564 RX DQ/DQS(Engine): PASS
3786 09:31:11.807614 TX OE : NO K
3787 09:31:11.807664 All Pass.
3788 09:31:11.807715
3789 09:31:11.807765 DramC Write-DBI off
3790 09:31:11.807814 PER_BANK_REFRESH: Hybrid Mode
3791 09:31:11.807864 TX_TRACKING: ON
3792 09:31:11.807915 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3793 09:31:11.807967 [FAST_K] Save calibration result to emmc
3794 09:31:11.808018 dramc_set_vcore_voltage set vcore to 650000
3795 09:31:11.808068 Read voltage for 600, 5
3796 09:31:11.808118 Vio18 = 0
3797 09:31:11.808168 Vcore = 650000
3798 09:31:11.808218 Vdram = 0
3799 09:31:11.808268 Vddq = 0
3800 09:31:11.808318 Vmddr = 0
3801 09:31:11.808368 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3802 09:31:11.808419 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3803 09:31:11.808469 MEM_TYPE=3, freq_sel=19
3804 09:31:11.808519 sv_algorithm_assistance_LP4_1600
3805 09:31:11.808601 ============ PULL DRAM RESETB DOWN ============
3806 09:31:11.808680 ========== PULL DRAM RESETB DOWN end =========
3807 09:31:11.808731 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3808 09:31:11.808781 ===================================
3809 09:31:11.808831 LPDDR4 DRAM CONFIGURATION
3810 09:31:11.808882 ===================================
3811 09:31:11.808961 EX_ROW_EN[0] = 0x0
3812 09:31:11.809040 EX_ROW_EN[1] = 0x0
3813 09:31:11.809119 LP4Y_EN = 0x0
3814 09:31:11.809169 WORK_FSP = 0x0
3815 09:31:11.809219 WL = 0x2
3816 09:31:11.809270 RL = 0x2
3817 09:31:11.809319 BL = 0x2
3818 09:31:11.809369 RPST = 0x0
3819 09:31:11.809418 RD_PRE = 0x0
3820 09:31:11.809469 WR_PRE = 0x1
3821 09:31:11.809519 WR_PST = 0x0
3822 09:31:11.809569 DBI_WR = 0x0
3823 09:31:11.809619 DBI_RD = 0x0
3824 09:31:11.809669 OTF = 0x1
3825 09:31:11.809719 ===================================
3826 09:31:11.809800 ===================================
3827 09:31:11.809851 ANA top config
3828 09:31:11.809900 ===================================
3829 09:31:11.809951 DLL_ASYNC_EN = 0
3830 09:31:11.810001 ALL_SLAVE_EN = 1
3831 09:31:11.810051 NEW_RANK_MODE = 1
3832 09:31:11.810103 DLL_IDLE_MODE = 1
3833 09:31:11.810154 LP45_APHY_COMB_EN = 1
3834 09:31:11.810204 TX_ODT_DIS = 1
3835 09:31:11.810254 NEW_8X_MODE = 1
3836 09:31:11.810305 ===================================
3837 09:31:11.810356 ===================================
3838 09:31:11.810407 data_rate = 1200
3839 09:31:11.810457 CKR = 1
3840 09:31:11.810507 DQ_P2S_RATIO = 8
3841 09:31:11.810557 ===================================
3842 09:31:11.810607 CA_P2S_RATIO = 8
3843 09:31:11.810657 DQ_CA_OPEN = 0
3844 09:31:11.810707 DQ_SEMI_OPEN = 0
3845 09:31:11.810757 CA_SEMI_OPEN = 0
3846 09:31:11.810807 CA_FULL_RATE = 0
3847 09:31:11.810858 DQ_CKDIV4_EN = 1
3848 09:31:11.810908 CA_CKDIV4_EN = 1
3849 09:31:11.810958 CA_PREDIV_EN = 0
3850 09:31:11.811008 PH8_DLY = 0
3851 09:31:11.811058 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3852 09:31:11.811108 DQ_AAMCK_DIV = 4
3853 09:31:11.811159 CA_AAMCK_DIV = 4
3854 09:31:11.811209 CA_ADMCK_DIV = 4
3855 09:31:11.811259 DQ_TRACK_CA_EN = 0
3856 09:31:11.811309 CA_PICK = 600
3857 09:31:11.811359 CA_MCKIO = 600
3858 09:31:11.811409 MCKIO_SEMI = 0
3859 09:31:11.811459 PLL_FREQ = 2288
3860 09:31:11.811509 DQ_UI_PI_RATIO = 32
3861 09:31:11.811560 CA_UI_PI_RATIO = 0
3862 09:31:11.811610 ===================================
3863 09:31:11.811661 ===================================
3864 09:31:11.811712 memory_type:LPDDR4
3865 09:31:11.811948 GP_NUM : 10
3866 09:31:11.812004 SRAM_EN : 1
3867 09:31:11.812055 MD32_EN : 0
3868 09:31:11.812105 ===================================
3869 09:31:11.812155 [ANA_INIT] >>>>>>>>>>>>>>
3870 09:31:11.812206 <<<<<< [CONFIGURE PHASE]: ANA_TX
3871 09:31:11.812257 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3872 09:31:11.812307 ===================================
3873 09:31:11.812358 data_rate = 1200,PCW = 0X5800
3874 09:31:11.812408 ===================================
3875 09:31:11.812459 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3876 09:31:11.812527 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3877 09:31:11.812608 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3878 09:31:11.812659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3879 09:31:11.812710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3880 09:31:11.812760 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3881 09:31:11.812810 [ANA_INIT] flow start
3882 09:31:11.812860 [ANA_INIT] PLL >>>>>>>>
3883 09:31:11.812911 [ANA_INIT] PLL <<<<<<<<
3884 09:31:11.812961 [ANA_INIT] MIDPI >>>>>>>>
3885 09:31:11.813011 [ANA_INIT] MIDPI <<<<<<<<
3886 09:31:11.813062 [ANA_INIT] DLL >>>>>>>>
3887 09:31:11.813111 [ANA_INIT] flow end
3888 09:31:11.813161 ============ LP4 DIFF to SE enter ============
3889 09:31:11.813212 ============ LP4 DIFF to SE exit ============
3890 09:31:11.813262 [ANA_INIT] <<<<<<<<<<<<<
3891 09:31:11.813313 [Flow] Enable top DCM control >>>>>
3892 09:31:11.813363 [Flow] Enable top DCM control <<<<<
3893 09:31:11.813414 Enable DLL master slave shuffle
3894 09:31:11.813464 ==============================================================
3895 09:31:11.813514 Gating Mode config
3896 09:31:11.813564 ==============================================================
3897 09:31:11.813615 Config description:
3898 09:31:11.813664 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3899 09:31:11.813716 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3900 09:31:11.813767 SELPH_MODE 0: By rank 1: By Phase
3901 09:31:11.813818 ==============================================================
3902 09:31:11.813868 GAT_TRACK_EN = 1
3903 09:31:11.813919 RX_GATING_MODE = 2
3904 09:31:11.813969 RX_GATING_TRACK_MODE = 2
3905 09:31:11.814019 SELPH_MODE = 1
3906 09:31:11.814069 PICG_EARLY_EN = 1
3907 09:31:11.814119 VALID_LAT_VALUE = 1
3908 09:31:11.814169 ==============================================================
3909 09:31:11.814220 Enter into Gating configuration >>>>
3910 09:31:11.814270 Exit from Gating configuration <<<<
3911 09:31:11.814320 Enter into DVFS_PRE_config >>>>>
3912 09:31:11.814370 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3913 09:31:11.814422 Exit from DVFS_PRE_config <<<<<
3914 09:31:11.814472 Enter into PICG configuration >>>>
3915 09:31:11.814522 Exit from PICG configuration <<<<
3916 09:31:11.814572 [RX_INPUT] configuration >>>>>
3917 09:31:11.814623 [RX_INPUT] configuration <<<<<
3918 09:31:11.814673 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3919 09:31:11.814723 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3920 09:31:11.814774 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3921 09:31:11.814825 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3922 09:31:11.814876 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3923 09:31:11.814926 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3924 09:31:11.814976 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3925 09:31:11.815026 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3926 09:31:11.815076 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3927 09:31:11.815138 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3928 09:31:11.815692 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3929 09:31:11.822496 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3930 09:31:11.825545 ===================================
3931 09:31:11.829077 LPDDR4 DRAM CONFIGURATION
3932 09:31:11.832376 ===================================
3933 09:31:11.832538 EX_ROW_EN[0] = 0x0
3934 09:31:11.835957 EX_ROW_EN[1] = 0x0
3935 09:31:11.836117 LP4Y_EN = 0x0
3936 09:31:11.839357 WORK_FSP = 0x0
3937 09:31:11.839487 WL = 0x2
3938 09:31:11.842298 RL = 0x2
3939 09:31:11.842460 BL = 0x2
3940 09:31:11.845800 RPST = 0x0
3941 09:31:11.845969 RD_PRE = 0x0
3942 09:31:11.849109 WR_PRE = 0x1
3943 09:31:11.849273 WR_PST = 0x0
3944 09:31:11.852074 DBI_WR = 0x0
3945 09:31:11.852234 DBI_RD = 0x0
3946 09:31:11.855657 OTF = 0x1
3947 09:31:11.858772 ===================================
3948 09:31:11.861894 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3949 09:31:11.865577 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3950 09:31:11.871922 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3951 09:31:11.875799 ===================================
3952 09:31:11.876011 LPDDR4 DRAM CONFIGURATION
3953 09:31:11.878580 ===================================
3954 09:31:11.882209 EX_ROW_EN[0] = 0x10
3955 09:31:11.885153 EX_ROW_EN[1] = 0x0
3956 09:31:11.885369 LP4Y_EN = 0x0
3957 09:31:11.888946 WORK_FSP = 0x0
3958 09:31:11.889180 WL = 0x2
3959 09:31:11.892006 RL = 0x2
3960 09:31:11.892262 BL = 0x2
3961 09:31:11.895339 RPST = 0x0
3962 09:31:11.895517 RD_PRE = 0x0
3963 09:31:11.898318 WR_PRE = 0x1
3964 09:31:11.898583 WR_PST = 0x0
3965 09:31:11.901955 DBI_WR = 0x0
3966 09:31:11.902189 DBI_RD = 0x0
3967 09:31:11.905207 OTF = 0x1
3968 09:31:11.908791 ===================================
3969 09:31:11.915591 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3970 09:31:11.919092 nWR fixed to 30
3971 09:31:11.922046 [ModeRegInit_LP4] CH0 RK0
3972 09:31:11.922502 [ModeRegInit_LP4] CH0 RK1
3973 09:31:11.925568 [ModeRegInit_LP4] CH1 RK0
3974 09:31:11.928658 [ModeRegInit_LP4] CH1 RK1
3975 09:31:11.929288 match AC timing 17
3976 09:31:11.934860 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3977 09:31:11.938637 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3978 09:31:11.941463 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3979 09:31:11.948682 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3980 09:31:11.951503 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3981 09:31:11.951610 ==
3982 09:31:11.954706 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 09:31:11.958683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 09:31:11.958873 ==
3985 09:31:11.965169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3986 09:31:11.972024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3987 09:31:11.975075 [CA 0] Center 36 (5~67) winsize 63
3988 09:31:11.978628 [CA 1] Center 36 (6~67) winsize 62
3989 09:31:11.981917 [CA 2] Center 34 (4~65) winsize 62
3990 09:31:11.985052 [CA 3] Center 34 (3~65) winsize 63
3991 09:31:11.988600 [CA 4] Center 34 (3~65) winsize 63
3992 09:31:11.991945 [CA 5] Center 33 (2~64) winsize 63
3993 09:31:11.992352
3994 09:31:11.995376 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3995 09:31:11.995804
3996 09:31:11.998411 [CATrainingPosCal] consider 1 rank data
3997 09:31:12.001956 u2DelayCellTimex100 = 270/100 ps
3998 09:31:12.005059 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
3999 09:31:12.026140 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4000 09:31:12.026660 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4001 09:31:12.027028 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4002 09:31:12.027370 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4003 09:31:12.027762 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4004 09:31:12.028153
4005 09:31:12.028577 CA PerBit enable=1, Macro0, CA PI delay=33
4006 09:31:12.028921
4007 09:31:12.031590 [CBTSetCACLKResult] CA Dly = 33
4008 09:31:12.031960 CS Dly: 5 (0~36)
4009 09:31:12.032298 ==
4010 09:31:12.034753 Dram Type= 6, Freq= 0, CH_0, rank 1
4011 09:31:12.038347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4012 09:31:12.038814 ==
4013 09:31:12.044855 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4014 09:31:12.051625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4015 09:31:12.054823 [CA 0] Center 36 (6~67) winsize 62
4016 09:31:12.058131 [CA 1] Center 36 (6~67) winsize 62
4017 09:31:12.061778 [CA 2] Center 35 (4~66) winsize 63
4018 09:31:12.064640 [CA 3] Center 34 (4~65) winsize 62
4019 09:31:12.068441 [CA 4] Center 34 (3~65) winsize 63
4020 09:31:12.071890 [CA 5] Center 33 (3~64) winsize 62
4021 09:31:12.072232
4022 09:31:12.074995 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4023 09:31:12.075334
4024 09:31:12.078358 [CATrainingPosCal] consider 2 rank data
4025 09:31:12.081905 u2DelayCellTimex100 = 270/100 ps
4026 09:31:12.085140 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4027 09:31:12.088422 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4028 09:31:12.091799 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4029 09:31:12.094613 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4030 09:31:12.098213 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4031 09:31:12.104878 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4032 09:31:12.105350
4033 09:31:12.107918 CA PerBit enable=1, Macro0, CA PI delay=33
4034 09:31:12.108390
4035 09:31:12.111733 [CBTSetCACLKResult] CA Dly = 33
4036 09:31:12.112305 CS Dly: 6 (0~38)
4037 09:31:12.112739
4038 09:31:12.115000 ----->DramcWriteLeveling(PI) begin...
4039 09:31:12.115580 ==
4040 09:31:12.117939 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 09:31:12.124906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 09:31:12.125483 ==
4043 09:31:12.127979 Write leveling (Byte 0): 32 => 32
4044 09:31:12.128584 Write leveling (Byte 1): 31 => 31
4045 09:31:12.131702 DramcWriteLeveling(PI) end<-----
4046 09:31:12.132277
4047 09:31:12.132725 ==
4048 09:31:12.134537 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 09:31:12.141530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 09:31:12.142101 ==
4051 09:31:12.145170 [Gating] SW mode calibration
4052 09:31:12.151806 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4053 09:31:12.154614 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4054 09:31:12.161239 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4055 09:31:12.164722 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4056 09:31:12.168370 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 09:31:12.174232 0 9 12 | B1->B0 | 3333 2828 | 1 0 | (1 1) (0 0)
4058 09:31:12.177777 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4059 09:31:12.181393 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 09:31:12.184707 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 09:31:12.191236 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 09:31:12.194334 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 09:31:12.197843 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 09:31:12.204249 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4065 09:31:12.207952 0 10 12 | B1->B0 | 2b2b 4242 | 0 0 | (0 0) (0 0)
4066 09:31:12.211145 0 10 16 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
4067 09:31:12.217839 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 09:31:12.220778 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 09:31:12.224256 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 09:31:12.231221 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 09:31:12.235080 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 09:31:12.237823 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 09:31:12.244602 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 09:31:12.248390 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4075 09:31:12.251225 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 09:31:12.258073 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 09:31:12.261435 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 09:31:12.264324 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 09:31:12.271187 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 09:31:12.274413 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 09:31:12.277334 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 09:31:12.284126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 09:31:12.287875 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 09:31:12.290794 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 09:31:12.297602 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 09:31:12.301189 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 09:31:12.304190 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 09:31:12.310496 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 09:31:12.314003 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4090 09:31:12.317148 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 09:31:12.320692 Total UI for P1: 0, mck2ui 16
4092 09:31:12.323686 best dqsien dly found for B0: ( 0, 13, 12)
4093 09:31:12.327315 Total UI for P1: 0, mck2ui 16
4094 09:31:12.330420 best dqsien dly found for B1: ( 0, 13, 14)
4095 09:31:12.334044 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4096 09:31:12.337161 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4097 09:31:12.337592
4098 09:31:12.340647 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4099 09:31:12.347403 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4100 09:31:12.347836 [Gating] SW calibration Done
4101 09:31:12.348180 ==
4102 09:31:12.350561 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 09:31:12.357069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 09:31:12.357503 ==
4105 09:31:12.357846 RX Vref Scan: 0
4106 09:31:12.358164
4107 09:31:12.360176 RX Vref 0 -> 0, step: 1
4108 09:31:12.360646
4109 09:31:12.363681 RX Delay -230 -> 252, step: 16
4110 09:31:12.367103 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4111 09:31:12.370018 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4112 09:31:12.376994 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4113 09:31:12.379959 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4114 09:31:12.383476 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4115 09:31:12.386640 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4116 09:31:12.390261 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4117 09:31:12.396998 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4118 09:31:12.400156 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4119 09:31:12.403234 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4120 09:31:12.406724 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4121 09:31:12.413189 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4122 09:31:12.416132 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4123 09:31:12.419748 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4124 09:31:12.422792 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4125 09:31:12.429365 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4126 09:31:12.429448 ==
4127 09:31:12.432943 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 09:31:12.435979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 09:31:12.436063 ==
4130 09:31:12.436129 DQS Delay:
4131 09:31:12.439115 DQS0 = 0, DQS1 = 0
4132 09:31:12.439197 DQM Delay:
4133 09:31:12.442776 DQM0 = 50, DQM1 = 40
4134 09:31:12.442859 DQ Delay:
4135 09:31:12.445874 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4136 09:31:12.449501 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4137 09:31:12.452521 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4138 09:31:12.455641 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41
4139 09:31:12.455724
4140 09:31:12.455790
4141 09:31:12.455851 ==
4142 09:31:12.459308 Dram Type= 6, Freq= 0, CH_0, rank 0
4143 09:31:12.462380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4144 09:31:12.465909 ==
4145 09:31:12.465993
4146 09:31:12.466058
4147 09:31:12.466120 TX Vref Scan disable
4148 09:31:12.469039 == TX Byte 0 ==
4149 09:31:12.472137 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4150 09:31:12.475583 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4151 09:31:12.479123 == TX Byte 1 ==
4152 09:31:12.482599 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4153 09:31:12.485625 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4154 09:31:12.489285 ==
4155 09:31:12.489368 Dram Type= 6, Freq= 0, CH_0, rank 0
4156 09:31:12.495798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 09:31:12.495882 ==
4158 09:31:12.495948
4159 09:31:12.496008
4160 09:31:12.496067 TX Vref Scan disable
4161 09:31:12.500446 == TX Byte 0 ==
4162 09:31:12.504105 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4163 09:31:12.510243 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4164 09:31:12.510327 == TX Byte 1 ==
4165 09:31:12.513715 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4166 09:31:12.520465 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4167 09:31:12.520611
4168 09:31:12.520679 [DATLAT]
4169 09:31:12.520741 Freq=600, CH0 RK0
4170 09:31:12.520801
4171 09:31:12.523657 DATLAT Default: 0x9
4172 09:31:12.523740 0, 0xFFFF, sum = 0
4173 09:31:12.527301 1, 0xFFFF, sum = 0
4174 09:31:12.527386 2, 0xFFFF, sum = 0
4175 09:31:12.530273 3, 0xFFFF, sum = 0
4176 09:31:12.533872 4, 0xFFFF, sum = 0
4177 09:31:12.533956 5, 0xFFFF, sum = 0
4178 09:31:12.536945 6, 0xFFFF, sum = 0
4179 09:31:12.537030 7, 0xFFFF, sum = 0
4180 09:31:12.537097 8, 0x0, sum = 1
4181 09:31:12.540501 9, 0x0, sum = 2
4182 09:31:12.540606 10, 0x0, sum = 3
4183 09:31:12.543747 11, 0x0, sum = 4
4184 09:31:12.543841 best_step = 9
4185 09:31:12.543910
4186 09:31:12.543974 ==
4187 09:31:12.546823 Dram Type= 6, Freq= 0, CH_0, rank 0
4188 09:31:12.553584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4189 09:31:12.553669 ==
4190 09:31:12.553735 RX Vref Scan: 1
4191 09:31:12.553796
4192 09:31:12.557130 RX Vref 0 -> 0, step: 1
4193 09:31:12.557214
4194 09:31:12.560204 RX Delay -163 -> 252, step: 8
4195 09:31:12.560287
4196 09:31:12.563894 Set Vref, RX VrefLevel [Byte0]: 59
4197 09:31:12.566944 [Byte1]: 49
4198 09:31:12.567033
4199 09:31:12.570664 Final RX Vref Byte 0 = 59 to rank0
4200 09:31:12.573491 Final RX Vref Byte 1 = 49 to rank0
4201 09:31:12.576876 Final RX Vref Byte 0 = 59 to rank1
4202 09:31:12.580449 Final RX Vref Byte 1 = 49 to rank1==
4203 09:31:12.583348 Dram Type= 6, Freq= 0, CH_0, rank 0
4204 09:31:12.587114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 09:31:12.587199 ==
4206 09:31:12.590072 DQS Delay:
4207 09:31:12.590156 DQS0 = 0, DQS1 = 0
4208 09:31:12.590223 DQM Delay:
4209 09:31:12.593589 DQM0 = 50, DQM1 = 36
4210 09:31:12.593673 DQ Delay:
4211 09:31:12.597384 DQ0 =48, DQ1 =48, DQ2 =48, DQ3 =48
4212 09:31:12.600344 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4213 09:31:12.603532 DQ8 =32, DQ9 =20, DQ10 =36, DQ11 =32
4214 09:31:12.607310 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =44
4215 09:31:12.607400
4216 09:31:12.607470
4217 09:31:12.617209 [DQSOSCAuto] RK0, (LSB)MR18= 0x5852, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4218 09:31:12.617397 CH0 RK0: MR19=808, MR18=5852
4219 09:31:12.623672 CH0_RK0: MR19=0x808, MR18=0x5852, DQSOSC=393, MR23=63, INC=169, DEC=113
4220 09:31:12.623863
4221 09:31:12.627441 ----->DramcWriteLeveling(PI) begin...
4222 09:31:12.630199 ==
4223 09:31:12.630378 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 09:31:12.637196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 09:31:12.637642 ==
4226 09:31:12.640645 Write leveling (Byte 0): 34 => 34
4227 09:31:12.643689 Write leveling (Byte 1): 29 => 29
4228 09:31:12.647188 DramcWriteLeveling(PI) end<-----
4229 09:31:12.647614
4230 09:31:12.647950 ==
4231 09:31:12.650989 Dram Type= 6, Freq= 0, CH_0, rank 1
4232 09:31:12.653812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4233 09:31:12.654287 ==
4234 09:31:12.657655 [Gating] SW mode calibration
4235 09:31:12.663793 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4236 09:31:12.667486 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4237 09:31:12.673946 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4238 09:31:12.677513 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4239 09:31:12.680697 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4240 09:31:12.687267 0 9 12 | B1->B0 | 3131 3131 | 1 0 | (1 0) (0 1)
4241 09:31:12.690704 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4242 09:31:12.693977 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4243 09:31:12.700127 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 09:31:12.703835 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 09:31:12.706928 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 09:31:12.713657 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 09:31:12.717231 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 09:31:12.720340 0 10 12 | B1->B0 | 2828 3030 | 0 0 | (0 0) (0 0)
4249 09:31:12.727219 0 10 16 | B1->B0 | 4444 4444 | 0 0 | (0 0) (0 0)
4250 09:31:12.730585 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4251 09:31:12.733917 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 09:31:12.740010 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 09:31:12.743762 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 09:31:12.746942 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 09:31:12.753717 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 09:31:12.756707 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4257 09:31:12.760514 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 09:31:12.766863 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 09:31:12.770741 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 09:31:12.773566 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 09:31:12.780113 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 09:31:12.783109 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 09:31:12.786882 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 09:31:12.793423 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 09:31:12.796841 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 09:31:12.799998 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 09:31:12.806809 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 09:31:12.809837 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 09:31:12.813585 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 09:31:12.816852 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 09:31:12.823330 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 09:31:12.826703 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4273 09:31:12.829821 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 09:31:12.833098 Total UI for P1: 0, mck2ui 16
4275 09:31:12.836803 best dqsien dly found for B0: ( 0, 13, 12)
4276 09:31:12.840443 Total UI for P1: 0, mck2ui 16
4277 09:31:12.843261 best dqsien dly found for B1: ( 0, 13, 12)
4278 09:31:12.846442 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4279 09:31:12.852914 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4280 09:31:12.853771
4281 09:31:12.856380 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4282 09:31:12.859679 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4283 09:31:12.862843 [Gating] SW calibration Done
4284 09:31:12.863327 ==
4285 09:31:12.866206 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 09:31:12.869806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 09:31:12.870292 ==
4288 09:31:12.872999 RX Vref Scan: 0
4289 09:31:12.873577
4290 09:31:12.874064 RX Vref 0 -> 0, step: 1
4291 09:31:12.874519
4292 09:31:12.876590 RX Delay -230 -> 252, step: 16
4293 09:31:12.879545 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4294 09:31:12.886305 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4295 09:31:12.889354 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4296 09:31:12.892822 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4297 09:31:12.896366 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4298 09:31:12.899573 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4299 09:31:12.906627 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4300 09:31:12.909834 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4301 09:31:12.912978 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4302 09:31:12.916292 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4303 09:31:12.922837 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4304 09:31:12.926337 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4305 09:31:12.929470 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4306 09:31:12.933260 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4307 09:31:12.939354 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4308 09:31:12.942893 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4309 09:31:12.943365 ==
4310 09:31:12.945961 Dram Type= 6, Freq= 0, CH_0, rank 1
4311 09:31:12.949595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4312 09:31:12.950172 ==
4313 09:31:12.950548 DQS Delay:
4314 09:31:12.953190 DQS0 = 0, DQS1 = 0
4315 09:31:12.953768 DQM Delay:
4316 09:31:12.956314 DQM0 = 47, DQM1 = 41
4317 09:31:12.956942 DQ Delay:
4318 09:31:12.959858 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4319 09:31:12.962848 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4320 09:31:12.966179 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4321 09:31:12.969161 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4322 09:31:12.969643
4323 09:31:12.970011
4324 09:31:12.970351 ==
4325 09:31:12.972779 Dram Type= 6, Freq= 0, CH_0, rank 1
4326 09:31:12.976084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4327 09:31:12.979390 ==
4328 09:31:12.979911
4329 09:31:12.980283
4330 09:31:12.980688 TX Vref Scan disable
4331 09:31:12.983106 == TX Byte 0 ==
4332 09:31:12.986252 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4333 09:31:12.989204 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4334 09:31:12.992800 == TX Byte 1 ==
4335 09:31:12.995752 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4336 09:31:12.999307 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4337 09:31:13.002449 ==
4338 09:31:13.005913 Dram Type= 6, Freq= 0, CH_0, rank 1
4339 09:31:13.009212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4340 09:31:13.009678 ==
4341 09:31:13.010046
4342 09:31:13.010411
4343 09:31:13.012513 TX Vref Scan disable
4344 09:31:13.013156 == TX Byte 0 ==
4345 09:31:13.019645 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4346 09:31:13.022770 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4347 09:31:13.023334 == TX Byte 1 ==
4348 09:31:13.029741 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4349 09:31:13.032743 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4350 09:31:13.033313
4351 09:31:13.033683 [DATLAT]
4352 09:31:13.036446 Freq=600, CH0 RK1
4353 09:31:13.037051
4354 09:31:13.037424 DATLAT Default: 0x9
4355 09:31:13.039383 0, 0xFFFF, sum = 0
4356 09:31:13.039853 1, 0xFFFF, sum = 0
4357 09:31:13.042730 2, 0xFFFF, sum = 0
4358 09:31:13.043199 3, 0xFFFF, sum = 0
4359 09:31:13.046412 4, 0xFFFF, sum = 0
4360 09:31:13.049288 5, 0xFFFF, sum = 0
4361 09:31:13.049752 6, 0xFFFF, sum = 0
4362 09:31:13.052334 7, 0xFFFF, sum = 0
4363 09:31:13.052817 8, 0x0, sum = 1
4364 09:31:13.053185 9, 0x0, sum = 2
4365 09:31:13.055921 10, 0x0, sum = 3
4366 09:31:13.056381 11, 0x0, sum = 4
4367 09:31:13.059460 best_step = 9
4368 09:31:13.059910
4369 09:31:13.060265 ==
4370 09:31:13.062569 Dram Type= 6, Freq= 0, CH_0, rank 1
4371 09:31:13.065652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 09:31:13.066110 ==
4373 09:31:13.069231 RX Vref Scan: 0
4374 09:31:13.069686
4375 09:31:13.070045 RX Vref 0 -> 0, step: 1
4376 09:31:13.070380
4377 09:31:13.072421 RX Delay -179 -> 252, step: 8
4378 09:31:13.079958 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4379 09:31:13.083061 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4380 09:31:13.086831 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4381 09:31:13.089603 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4382 09:31:13.093160 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4383 09:31:13.099856 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4384 09:31:13.103232 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4385 09:31:13.106366 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4386 09:31:13.110052 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4387 09:31:13.112894 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4388 09:31:13.119425 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4389 09:31:13.123173 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4390 09:31:13.126175 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4391 09:31:13.130294 iDelay=205, Bit 13, Center 48 (-91 ~ 188) 280
4392 09:31:13.136497 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4393 09:31:13.139859 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4394 09:31:13.140269 ==
4395 09:31:13.142880 Dram Type= 6, Freq= 0, CH_0, rank 1
4396 09:31:13.146854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 09:31:13.147399 ==
4398 09:31:13.149865 DQS Delay:
4399 09:31:13.150274 DQS0 = 0, DQS1 = 0
4400 09:31:13.150600 DQM Delay:
4401 09:31:13.153182 DQM0 = 48, DQM1 = 41
4402 09:31:13.153599 DQ Delay:
4403 09:31:13.156339 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4404 09:31:13.160132 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4405 09:31:13.162952 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4406 09:31:13.166406 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =52
4407 09:31:13.166815
4408 09:31:13.167137
4409 09:31:13.176929 [DQSOSCAuto] RK1, (LSB)MR18= 0x6734, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4410 09:31:13.177454 CH0 RK1: MR19=808, MR18=6734
4411 09:31:13.183401 CH0_RK1: MR19=0x808, MR18=0x6734, DQSOSC=390, MR23=63, INC=172, DEC=114
4412 09:31:13.186181 [RxdqsGatingPostProcess] freq 600
4413 09:31:13.192877 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4414 09:31:13.196430 Pre-setting of DQS Precalculation
4415 09:31:13.199712 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4416 09:31:13.200228 ==
4417 09:31:13.203001 Dram Type= 6, Freq= 0, CH_1, rank 0
4418 09:31:13.206818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4419 09:31:13.209463 ==
4420 09:31:13.213105 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4421 09:31:13.219867 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4422 09:31:13.223032 [CA 0] Center 35 (5~65) winsize 61
4423 09:31:13.226402 [CA 1] Center 35 (5~66) winsize 62
4424 09:31:13.229786 [CA 2] Center 34 (4~65) winsize 62
4425 09:31:13.232987 [CA 3] Center 33 (3~64) winsize 62
4426 09:31:13.236166 [CA 4] Center 34 (3~65) winsize 63
4427 09:31:13.239509 [CA 5] Center 33 (3~64) winsize 62
4428 09:31:13.239934
4429 09:31:13.243044 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4430 09:31:13.243529
4431 09:31:13.246158 [CATrainingPosCal] consider 1 rank data
4432 09:31:13.249596 u2DelayCellTimex100 = 270/100 ps
4433 09:31:13.252647 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4434 09:31:13.256286 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4435 09:31:13.259765 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4436 09:31:13.262687 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4437 09:31:13.269507 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4438 09:31:13.272971 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4439 09:31:13.273509
4440 09:31:13.276518 CA PerBit enable=1, Macro0, CA PI delay=33
4441 09:31:13.277086
4442 09:31:13.279251 [CBTSetCACLKResult] CA Dly = 33
4443 09:31:13.279934 CS Dly: 5 (0~36)
4444 09:31:13.280522 ==
4445 09:31:13.282930 Dram Type= 6, Freq= 0, CH_1, rank 1
4446 09:31:13.289831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4447 09:31:13.290262 ==
4448 09:31:13.293030 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4449 09:31:13.299473 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4450 09:31:13.302981 [CA 0] Center 35 (5~66) winsize 62
4451 09:31:13.306041 [CA 1] Center 35 (5~66) winsize 62
4452 09:31:13.309233 [CA 2] Center 34 (4~65) winsize 62
4453 09:31:13.313147 [CA 3] Center 34 (4~64) winsize 61
4454 09:31:13.316009 [CA 4] Center 34 (4~65) winsize 62
4455 09:31:13.319736 [CA 5] Center 33 (3~64) winsize 62
4456 09:31:13.320270
4457 09:31:13.322707 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4458 09:31:13.323237
4459 09:31:13.326279 [CATrainingPosCal] consider 2 rank data
4460 09:31:13.329346 u2DelayCellTimex100 = 270/100 ps
4461 09:31:13.332701 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4462 09:31:13.336074 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4463 09:31:13.342575 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4464 09:31:13.346034 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4465 09:31:13.349092 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4466 09:31:13.352531 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4467 09:31:13.353021
4468 09:31:13.355986 CA PerBit enable=1, Macro0, CA PI delay=33
4469 09:31:13.356413
4470 09:31:13.359468 [CBTSetCACLKResult] CA Dly = 33
4471 09:31:13.360074 CS Dly: 5 (0~36)
4472 09:31:13.360427
4473 09:31:13.362749 ----->DramcWriteLeveling(PI) begin...
4474 09:31:13.365989 ==
4475 09:31:13.366416 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 09:31:13.372499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 09:31:13.373077 ==
4478 09:31:13.376078 Write leveling (Byte 0): 29 => 29
4479 09:31:13.379216 Write leveling (Byte 1): 30 => 30
4480 09:31:13.382557 DramcWriteLeveling(PI) end<-----
4481 09:31:13.382984
4482 09:31:13.383316 ==
4483 09:31:13.385573 Dram Type= 6, Freq= 0, CH_1, rank 0
4484 09:31:13.389138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4485 09:31:13.389702 ==
4486 09:31:13.392599 [Gating] SW mode calibration
4487 09:31:13.398851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4488 09:31:13.402348 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4489 09:31:13.409031 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4490 09:31:13.412771 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4491 09:31:13.416007 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4492 09:31:13.422377 0 9 12 | B1->B0 | 2d2d 2d2d | 0 0 | (0 0) (1 1)
4493 09:31:13.425737 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 09:31:13.429309 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 09:31:13.436015 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 09:31:13.439250 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 09:31:13.442620 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 09:31:13.449085 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 09:31:13.452666 0 10 8 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
4500 09:31:13.455353 0 10 12 | B1->B0 | 3636 3b3b | 0 0 | (1 1) (0 0)
4501 09:31:13.462198 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 09:31:13.466008 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 09:31:13.469041 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 09:31:13.475293 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 09:31:13.478824 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 09:31:13.481869 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 09:31:13.489032 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4508 09:31:13.491999 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4509 09:31:13.495513 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 09:31:13.502315 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 09:31:13.505399 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 09:31:13.508543 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 09:31:13.515790 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 09:31:13.519018 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 09:31:13.521907 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 09:31:13.525464 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 09:31:13.532863 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 09:31:13.535870 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 09:31:13.538811 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 09:31:13.545336 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 09:31:13.548922 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 09:31:13.551737 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 09:31:13.559064 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4524 09:31:13.561846 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4525 09:31:13.565415 Total UI for P1: 0, mck2ui 16
4526 09:31:13.568912 best dqsien dly found for B0: ( 0, 13, 8)
4527 09:31:13.572103 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 09:31:13.575488 Total UI for P1: 0, mck2ui 16
4529 09:31:13.579047 best dqsien dly found for B1: ( 0, 13, 14)
4530 09:31:13.581832 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4531 09:31:13.585517 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4532 09:31:13.586120
4533 09:31:13.592172 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4534 09:31:13.595117 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4535 09:31:13.598924 [Gating] SW calibration Done
4536 09:31:13.599492 ==
4537 09:31:13.601873 Dram Type= 6, Freq= 0, CH_1, rank 0
4538 09:31:13.605241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4539 09:31:13.605732 ==
4540 09:31:13.606100 RX Vref Scan: 0
4541 09:31:13.606439
4542 09:31:13.608344 RX Vref 0 -> 0, step: 1
4543 09:31:13.608841
4544 09:31:13.611871 RX Delay -230 -> 252, step: 16
4545 09:31:13.614863 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4546 09:31:13.618896 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4547 09:31:13.625177 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4548 09:31:13.628668 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4549 09:31:13.631820 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4550 09:31:13.635167 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4551 09:31:13.638788 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4552 09:31:13.645250 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4553 09:31:13.648499 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4554 09:31:13.652182 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4555 09:31:13.655233 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4556 09:31:13.661975 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4557 09:31:13.665499 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4558 09:31:13.668694 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4559 09:31:13.671970 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4560 09:31:13.678584 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4561 09:31:13.679167 ==
4562 09:31:13.681701 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 09:31:13.685495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 09:31:13.686080 ==
4565 09:31:13.686453 DQS Delay:
4566 09:31:13.688585 DQS0 = 0, DQS1 = 0
4567 09:31:13.689154 DQM Delay:
4568 09:31:13.692057 DQM0 = 50, DQM1 = 43
4569 09:31:13.692658 DQ Delay:
4570 09:31:13.694970 DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49
4571 09:31:13.698328 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4572 09:31:13.701588 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =33
4573 09:31:13.705137 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4574 09:31:13.705601
4575 09:31:13.705966
4576 09:31:13.706307 ==
4577 09:31:13.708308 Dram Type= 6, Freq= 0, CH_1, rank 0
4578 09:31:13.711990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 09:31:13.712605 ==
4580 09:31:13.712994
4581 09:31:13.713340
4582 09:31:13.714710 TX Vref Scan disable
4583 09:31:13.718201 == TX Byte 0 ==
4584 09:31:13.721415 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4585 09:31:13.724843 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4586 09:31:13.728044 == TX Byte 1 ==
4587 09:31:13.731494 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4588 09:31:13.735117 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4589 09:31:13.735735 ==
4590 09:31:13.738120 Dram Type= 6, Freq= 0, CH_1, rank 0
4591 09:31:13.744900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 09:31:13.745470 ==
4593 09:31:13.745842
4594 09:31:13.746179
4595 09:31:13.746504 TX Vref Scan disable
4596 09:31:13.749179 == TX Byte 0 ==
4597 09:31:13.752933 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4598 09:31:13.759031 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4599 09:31:13.759500 == TX Byte 1 ==
4600 09:31:13.762353 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4601 09:31:13.769193 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4602 09:31:13.769767
4603 09:31:13.770137 [DATLAT]
4604 09:31:13.770477 Freq=600, CH1 RK0
4605 09:31:13.770809
4606 09:31:13.772873 DATLAT Default: 0x9
4607 09:31:13.773443 0, 0xFFFF, sum = 0
4608 09:31:13.775838 1, 0xFFFF, sum = 0
4609 09:31:13.776406 2, 0xFFFF, sum = 0
4610 09:31:13.778984 3, 0xFFFF, sum = 0
4611 09:31:13.781864 4, 0xFFFF, sum = 0
4612 09:31:13.782513 5, 0xFFFF, sum = 0
4613 09:31:13.785440 6, 0xFFFF, sum = 0
4614 09:31:13.785914 7, 0xFFFF, sum = 0
4615 09:31:13.788931 8, 0x0, sum = 1
4616 09:31:13.789402 9, 0x0, sum = 2
4617 09:31:13.789775 10, 0x0, sum = 3
4618 09:31:13.792086 11, 0x0, sum = 4
4619 09:31:13.792614 best_step = 9
4620 09:31:13.792996
4621 09:31:13.793340 ==
4622 09:31:13.795652 Dram Type= 6, Freq= 0, CH_1, rank 0
4623 09:31:13.802278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4624 09:31:13.802744 ==
4625 09:31:13.803110 RX Vref Scan: 1
4626 09:31:13.803453
4627 09:31:13.805357 RX Vref 0 -> 0, step: 1
4628 09:31:13.805830
4629 09:31:13.808527 RX Delay -163 -> 252, step: 8
4630 09:31:13.809038
4631 09:31:13.812201 Set Vref, RX VrefLevel [Byte0]: 51
4632 09:31:13.815562 [Byte1]: 53
4633 09:31:13.816174
4634 09:31:13.819182 Final RX Vref Byte 0 = 51 to rank0
4635 09:31:13.822436 Final RX Vref Byte 1 = 53 to rank0
4636 09:31:13.825276 Final RX Vref Byte 0 = 51 to rank1
4637 09:31:13.829070 Final RX Vref Byte 1 = 53 to rank1==
4638 09:31:13.832078 Dram Type= 6, Freq= 0, CH_1, rank 0
4639 09:31:13.835335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 09:31:13.835917 ==
4641 09:31:13.839020 DQS Delay:
4642 09:31:13.839593 DQS0 = 0, DQS1 = 0
4643 09:31:13.841911 DQM Delay:
4644 09:31:13.842396 DQM0 = 48, DQM1 = 40
4645 09:31:13.842770 DQ Delay:
4646 09:31:13.845785 DQ0 =56, DQ1 =40, DQ2 =36, DQ3 =44
4647 09:31:13.848671 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4648 09:31:13.852122 DQ8 =28, DQ9 =28, DQ10 =44, DQ11 =32
4649 09:31:13.855222 DQ12 =52, DQ13 =48, DQ14 =44, DQ15 =48
4650 09:31:13.855694
4651 09:31:13.856062
4652 09:31:13.865115 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e75, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 395 ps
4653 09:31:13.868633 CH1 RK0: MR19=808, MR18=4E75
4654 09:31:13.872162 CH1_RK0: MR19=0x808, MR18=0x4E75, DQSOSC=387, MR23=63, INC=175, DEC=116
4655 09:31:13.875238
4656 09:31:13.878550 ----->DramcWriteLeveling(PI) begin...
4657 09:31:13.879026 ==
4658 09:31:13.881917 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 09:31:13.885246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 09:31:13.886017 ==
4661 09:31:13.888709 Write leveling (Byte 0): 28 => 28
4662 09:31:13.892217 Write leveling (Byte 1): 28 => 28
4663 09:31:13.895492 DramcWriteLeveling(PI) end<-----
4664 09:31:13.896095
4665 09:31:13.896469 ==
4666 09:31:13.898585 Dram Type= 6, Freq= 0, CH_1, rank 1
4667 09:31:13.901644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4668 09:31:13.902128 ==
4669 09:31:13.905120 [Gating] SW mode calibration
4670 09:31:13.911854 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4671 09:31:13.918581 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4672 09:31:13.921831 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4673 09:31:13.925008 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4674 09:31:13.931983 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4675 09:31:13.935127 0 9 12 | B1->B0 | 2b2b 2f2f | 0 0 | (1 1) (1 1)
4676 09:31:13.938759 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4677 09:31:13.941607 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 09:31:13.948576 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 09:31:13.951416 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 09:31:13.955047 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 09:31:13.961775 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 09:31:13.965412 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4683 09:31:13.968211 0 10 12 | B1->B0 | 3b3b 3333 | 1 0 | (0 0) (0 0)
4684 09:31:13.974989 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 09:31:13.978049 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 09:31:13.981682 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 09:31:13.988641 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 09:31:13.992007 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 09:31:13.995339 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 09:31:14.001539 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 09:31:14.004909 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4692 09:31:14.008333 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 09:31:14.015208 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 09:31:14.018249 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 09:31:14.021522 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 09:31:14.028026 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 09:31:14.031972 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 09:31:14.034974 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 09:31:14.041416 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 09:31:14.044991 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 09:31:14.048165 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 09:31:14.055005 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 09:31:14.057790 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 09:31:14.061486 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 09:31:14.068155 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 09:31:14.071114 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 09:31:14.074576 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4708 09:31:14.078296 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4709 09:31:14.081461 Total UI for P1: 0, mck2ui 16
4710 09:31:14.084385 best dqsien dly found for B0: ( 0, 13, 12)
4711 09:31:14.088262 Total UI for P1: 0, mck2ui 16
4712 09:31:14.091461 best dqsien dly found for B1: ( 0, 13, 12)
4713 09:31:14.094714 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4714 09:31:14.101057 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4715 09:31:14.101636
4716 09:31:14.104297 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4717 09:31:14.107711 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4718 09:31:14.111087 [Gating] SW calibration Done
4719 09:31:14.111734 ==
4720 09:31:14.114309 Dram Type= 6, Freq= 0, CH_1, rank 1
4721 09:31:14.117921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4722 09:31:14.118391 ==
4723 09:31:14.121032 RX Vref Scan: 0
4724 09:31:14.121493
4725 09:31:14.121860 RX Vref 0 -> 0, step: 1
4726 09:31:14.122202
4727 09:31:14.124448 RX Delay -230 -> 252, step: 16
4728 09:31:14.127679 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4729 09:31:14.134312 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4730 09:31:14.137530 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4731 09:31:14.141134 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4732 09:31:14.144392 iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288
4733 09:31:14.147382 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4734 09:31:14.154778 iDelay=218, Bit 6, Center 57 (-86 ~ 201) 288
4735 09:31:14.157518 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4736 09:31:14.160810 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4737 09:31:14.164327 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4738 09:31:14.170643 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4739 09:31:14.174256 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4740 09:31:14.177795 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4741 09:31:14.181068 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4742 09:31:14.187194 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4743 09:31:14.190650 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4744 09:31:14.191111 ==
4745 09:31:14.194222 Dram Type= 6, Freq= 0, CH_1, rank 1
4746 09:31:14.197805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4747 09:31:14.198273 ==
4748 09:31:14.198641 DQS Delay:
4749 09:31:14.200629 DQS0 = 0, DQS1 = 0
4750 09:31:14.201092 DQM Delay:
4751 09:31:14.203997 DQM0 = 52, DQM1 = 46
4752 09:31:14.204459 DQ Delay:
4753 09:31:14.207610 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4754 09:31:14.210461 DQ4 =57, DQ5 =65, DQ6 =57, DQ7 =49
4755 09:31:14.213992 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4756 09:31:14.217579 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4757 09:31:14.218069
4758 09:31:14.218437
4759 09:31:14.218776 ==
4760 09:31:14.220578 Dram Type= 6, Freq= 0, CH_1, rank 1
4761 09:31:14.224209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4762 09:31:14.227083 ==
4763 09:31:14.227551
4764 09:31:14.227917
4765 09:31:14.228259 TX Vref Scan disable
4766 09:31:14.230820 == TX Byte 0 ==
4767 09:31:14.233714 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4768 09:31:14.237517 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4769 09:31:14.240506 == TX Byte 1 ==
4770 09:31:14.244213 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4771 09:31:14.247300 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4772 09:31:14.250894 ==
4773 09:31:14.253979 Dram Type= 6, Freq= 0, CH_1, rank 1
4774 09:31:14.257485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4775 09:31:14.258058 ==
4776 09:31:14.258426
4777 09:31:14.258767
4778 09:31:14.260383 TX Vref Scan disable
4779 09:31:14.260884 == TX Byte 0 ==
4780 09:31:14.267168 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4781 09:31:14.270560 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4782 09:31:14.271168 == TX Byte 1 ==
4783 09:31:14.277138 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4784 09:31:14.280519 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4785 09:31:14.281075
4786 09:31:14.281529 [DATLAT]
4787 09:31:14.283634 Freq=600, CH1 RK1
4788 09:31:14.284105
4789 09:31:14.284482 DATLAT Default: 0x9
4790 09:31:14.287088 0, 0xFFFF, sum = 0
4791 09:31:14.287638 1, 0xFFFF, sum = 0
4792 09:31:14.290130 2, 0xFFFF, sum = 0
4793 09:31:14.290606 3, 0xFFFF, sum = 0
4794 09:31:14.293634 4, 0xFFFF, sum = 0
4795 09:31:14.297222 5, 0xFFFF, sum = 0
4796 09:31:14.297970 6, 0xFFFF, sum = 0
4797 09:31:14.300243 7, 0xFFFF, sum = 0
4798 09:31:14.301066 8, 0x0, sum = 1
4799 09:31:14.301546 9, 0x0, sum = 2
4800 09:31:14.303620 10, 0x0, sum = 3
4801 09:31:14.304092 11, 0x0, sum = 4
4802 09:31:14.307355 best_step = 9
4803 09:31:14.308041
4804 09:31:14.308438 ==
4805 09:31:14.310541 Dram Type= 6, Freq= 0, CH_1, rank 1
4806 09:31:14.313628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4807 09:31:14.314151 ==
4808 09:31:14.316832 RX Vref Scan: 0
4809 09:31:14.317302
4810 09:31:14.317675 RX Vref 0 -> 0, step: 1
4811 09:31:14.318024
4812 09:31:14.320349 RX Delay -163 -> 252, step: 8
4813 09:31:14.327616 iDelay=205, Bit 0, Center 52 (-83 ~ 188) 272
4814 09:31:14.330850 iDelay=205, Bit 1, Center 44 (-91 ~ 180) 272
4815 09:31:14.334381 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4816 09:31:14.337228 iDelay=205, Bit 3, Center 48 (-91 ~ 188) 280
4817 09:31:14.341255 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4818 09:31:14.347934 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4819 09:31:14.350917 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4820 09:31:14.354506 iDelay=205, Bit 7, Center 48 (-91 ~ 188) 280
4821 09:31:14.357307 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4822 09:31:14.361011 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4823 09:31:14.367522 iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288
4824 09:31:14.370734 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4825 09:31:14.374323 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4826 09:31:14.377603 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4827 09:31:14.384134 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4828 09:31:14.387779 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4829 09:31:14.388359 ==
4830 09:31:14.390846 Dram Type= 6, Freq= 0, CH_1, rank 1
4831 09:31:14.394209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4832 09:31:14.394785 ==
4833 09:31:14.397556 DQS Delay:
4834 09:31:14.398027 DQS0 = 0, DQS1 = 0
4835 09:31:14.398404 DQM Delay:
4836 09:31:14.400531 DQM0 = 49, DQM1 = 44
4837 09:31:14.401047 DQ Delay:
4838 09:31:14.404143 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =48
4839 09:31:14.407182 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4840 09:31:14.410834 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =40
4841 09:31:14.413938 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =56
4842 09:31:14.414414
4843 09:31:14.414789
4844 09:31:14.423860 [DQSOSCAuto] RK1, (LSB)MR18= 0x581e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
4845 09:31:14.424441 CH1 RK1: MR19=808, MR18=581E
4846 09:31:14.430531 CH1_RK1: MR19=0x808, MR18=0x581E, DQSOSC=393, MR23=63, INC=169, DEC=113
4847 09:31:14.434152 [RxdqsGatingPostProcess] freq 600
4848 09:31:14.441048 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4849 09:31:14.444151 Pre-setting of DQS Precalculation
4850 09:31:14.447582 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4851 09:31:14.453865 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4852 09:31:14.464208 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4853 09:31:14.464834
4854 09:31:14.465218
4855 09:31:14.465566 [Calibration Summary] 1200 Mbps
4856 09:31:14.467319 CH 0, Rank 0
4857 09:31:14.467895 SW Impedance : PASS
4858 09:31:14.470891 DUTY Scan : NO K
4859 09:31:14.473710 ZQ Calibration : PASS
4860 09:31:14.474185 Jitter Meter : NO K
4861 09:31:14.477193 CBT Training : PASS
4862 09:31:14.480601 Write leveling : PASS
4863 09:31:14.481177 RX DQS gating : PASS
4864 09:31:14.483800 RX DQ/DQS(RDDQC) : PASS
4865 09:31:14.487473 TX DQ/DQS : PASS
4866 09:31:14.488044 RX DATLAT : PASS
4867 09:31:14.490472 RX DQ/DQS(Engine): PASS
4868 09:31:14.494021 TX OE : NO K
4869 09:31:14.494610 All Pass.
4870 09:31:14.495004
4871 09:31:14.495358 CH 0, Rank 1
4872 09:31:14.496879 SW Impedance : PASS
4873 09:31:14.500591 DUTY Scan : NO K
4874 09:31:14.501186 ZQ Calibration : PASS
4875 09:31:14.503965 Jitter Meter : NO K
4876 09:31:14.506890 CBT Training : PASS
4877 09:31:14.507378 Write leveling : PASS
4878 09:31:14.510589 RX DQS gating : PASS
4879 09:31:14.513429 RX DQ/DQS(RDDQC) : PASS
4880 09:31:14.513917 TX DQ/DQS : PASS
4881 09:31:14.517779 RX DATLAT : PASS
4882 09:31:14.519923 RX DQ/DQS(Engine): PASS
4883 09:31:14.520414 TX OE : NO K
4884 09:31:14.520943 All Pass.
4885 09:31:14.521403
4886 09:31:14.523124 CH 1, Rank 0
4887 09:31:14.523751 SW Impedance : PASS
4888 09:31:14.526682 DUTY Scan : NO K
4889 09:31:14.530189 ZQ Calibration : PASS
4890 09:31:14.530750 Jitter Meter : NO K
4891 09:31:14.533583 CBT Training : PASS
4892 09:31:14.536626 Write leveling : PASS
4893 09:31:14.537067 RX DQS gating : PASS
4894 09:31:14.540196 RX DQ/DQS(RDDQC) : PASS
4895 09:31:14.543476 TX DQ/DQS : PASS
4896 09:31:14.543951 RX DATLAT : PASS
4897 09:31:14.546504 RX DQ/DQS(Engine): PASS
4898 09:31:14.550167 TX OE : NO K
4899 09:31:14.550641 All Pass.
4900 09:31:14.551015
4901 09:31:14.551368 CH 1, Rank 1
4902 09:31:14.553146 SW Impedance : PASS
4903 09:31:14.556154 DUTY Scan : NO K
4904 09:31:14.556682 ZQ Calibration : PASS
4905 09:31:14.559757 Jitter Meter : NO K
4906 09:31:14.562792 CBT Training : PASS
4907 09:31:14.563432 Write leveling : PASS
4908 09:31:14.566624 RX DQS gating : PASS
4909 09:31:14.569453 RX DQ/DQS(RDDQC) : PASS
4910 09:31:14.569940 TX DQ/DQS : PASS
4911 09:31:14.573044 RX DATLAT : PASS
4912 09:31:14.576072 RX DQ/DQS(Engine): PASS
4913 09:31:14.576712 TX OE : NO K
4914 09:31:14.577105 All Pass.
4915 09:31:14.579633
4916 09:31:14.580096 DramC Write-DBI off
4917 09:31:14.582859 PER_BANK_REFRESH: Hybrid Mode
4918 09:31:14.583347 TX_TRACKING: ON
4919 09:31:14.592633 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4920 09:31:14.596292 [FAST_K] Save calibration result to emmc
4921 09:31:14.599214 dramc_set_vcore_voltage set vcore to 662500
4922 09:31:14.602819 Read voltage for 933, 3
4923 09:31:14.603380 Vio18 = 0
4924 09:31:14.605986 Vcore = 662500
4925 09:31:14.606411 Vdram = 0
4926 09:31:14.606810 Vddq = 0
4927 09:31:14.607141 Vmddr = 0
4928 09:31:14.612965 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4929 09:31:14.619027 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4930 09:31:14.619587 MEM_TYPE=3, freq_sel=17
4931 09:31:14.622544 sv_algorithm_assistance_LP4_1600
4932 09:31:14.625958 ============ PULL DRAM RESETB DOWN ============
4933 09:31:14.632595 ========== PULL DRAM RESETB DOWN end =========
4934 09:31:14.635910 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4935 09:31:14.639577 ===================================
4936 09:31:14.642908 LPDDR4 DRAM CONFIGURATION
4937 09:31:14.646040 ===================================
4938 09:31:14.646537 EX_ROW_EN[0] = 0x0
4939 09:31:14.649770 EX_ROW_EN[1] = 0x0
4940 09:31:14.650338 LP4Y_EN = 0x0
4941 09:31:14.652695 WORK_FSP = 0x0
4942 09:31:14.653245 WL = 0x3
4943 09:31:14.656602 RL = 0x3
4944 09:31:14.657173 BL = 0x2
4945 09:31:14.659538 RPST = 0x0
4946 09:31:14.663096 RD_PRE = 0x0
4947 09:31:14.663660 WR_PRE = 0x1
4948 09:31:14.666142 WR_PST = 0x0
4949 09:31:14.666604 DBI_WR = 0x0
4950 09:31:14.669620 DBI_RD = 0x0
4951 09:31:14.670085 OTF = 0x1
4952 09:31:14.672744 ===================================
4953 09:31:14.676010 ===================================
4954 09:31:14.676613 ANA top config
4955 09:31:14.679570 ===================================
4956 09:31:14.682888 DLL_ASYNC_EN = 0
4957 09:31:14.685941 ALL_SLAVE_EN = 1
4958 09:31:14.689232 NEW_RANK_MODE = 1
4959 09:31:14.692658 DLL_IDLE_MODE = 1
4960 09:31:14.693123 LP45_APHY_COMB_EN = 1
4961 09:31:14.695928 TX_ODT_DIS = 1
4962 09:31:14.699334 NEW_8X_MODE = 1
4963 09:31:14.702725 ===================================
4964 09:31:14.706165 ===================================
4965 09:31:14.709068 data_rate = 1866
4966 09:31:14.712473 CKR = 1
4967 09:31:14.712969 DQ_P2S_RATIO = 8
4968 09:31:14.716147 ===================================
4969 09:31:14.719202 CA_P2S_RATIO = 8
4970 09:31:14.722536 DQ_CA_OPEN = 0
4971 09:31:14.725693 DQ_SEMI_OPEN = 0
4972 09:31:14.729431 CA_SEMI_OPEN = 0
4973 09:31:14.732292 CA_FULL_RATE = 0
4974 09:31:14.732900 DQ_CKDIV4_EN = 1
4975 09:31:14.735687 CA_CKDIV4_EN = 1
4976 09:31:14.739087 CA_PREDIV_EN = 0
4977 09:31:14.742523 PH8_DLY = 0
4978 09:31:14.745530 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4979 09:31:14.749034 DQ_AAMCK_DIV = 4
4980 09:31:14.749506 CA_AAMCK_DIV = 4
4981 09:31:14.752205 CA_ADMCK_DIV = 4
4982 09:31:14.755975 DQ_TRACK_CA_EN = 0
4983 09:31:14.759035 CA_PICK = 933
4984 09:31:14.762459 CA_MCKIO = 933
4985 09:31:14.765689 MCKIO_SEMI = 0
4986 09:31:14.769146 PLL_FREQ = 3732
4987 09:31:14.769615 DQ_UI_PI_RATIO = 32
4988 09:31:14.772407 CA_UI_PI_RATIO = 0
4989 09:31:14.775919 ===================================
4990 09:31:14.778724 ===================================
4991 09:31:14.782331 memory_type:LPDDR4
4992 09:31:14.785757 GP_NUM : 10
4993 09:31:14.786228 SRAM_EN : 1
4994 09:31:14.788834 MD32_EN : 0
4995 09:31:14.792315 ===================================
4996 09:31:14.795441 [ANA_INIT] >>>>>>>>>>>>>>
4997 09:31:14.795911 <<<<<< [CONFIGURE PHASE]: ANA_TX
4998 09:31:14.799054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4999 09:31:14.802143 ===================================
5000 09:31:14.805794 data_rate = 1866,PCW = 0X8f00
5001 09:31:14.808736 ===================================
5002 09:31:14.812353 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5003 09:31:14.818979 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5004 09:31:14.825374 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5005 09:31:14.829064 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5006 09:31:14.831992 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5007 09:31:14.835701 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5008 09:31:14.839153 [ANA_INIT] flow start
5009 09:31:14.839712 [ANA_INIT] PLL >>>>>>>>
5010 09:31:14.842309 [ANA_INIT] PLL <<<<<<<<
5011 09:31:14.845204 [ANA_INIT] MIDPI >>>>>>>>
5012 09:31:14.845670 [ANA_INIT] MIDPI <<<<<<<<
5013 09:31:14.848798 [ANA_INIT] DLL >>>>>>>>
5014 09:31:14.851980 [ANA_INIT] flow end
5015 09:31:14.855437 ============ LP4 DIFF to SE enter ============
5016 09:31:14.858636 ============ LP4 DIFF to SE exit ============
5017 09:31:14.862019 [ANA_INIT] <<<<<<<<<<<<<
5018 09:31:14.865544 [Flow] Enable top DCM control >>>>>
5019 09:31:14.868882 [Flow] Enable top DCM control <<<<<
5020 09:31:14.872440 Enable DLL master slave shuffle
5021 09:31:14.875269 ==============================================================
5022 09:31:14.878723 Gating Mode config
5023 09:31:14.885348 ==============================================================
5024 09:31:14.885894 Config description:
5025 09:31:14.895476 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5026 09:31:14.901560 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5027 09:31:14.908930 SELPH_MODE 0: By rank 1: By Phase
5028 09:31:14.911808 ==============================================================
5029 09:31:14.915271 GAT_TRACK_EN = 1
5030 09:31:14.918760 RX_GATING_MODE = 2
5031 09:31:14.921775 RX_GATING_TRACK_MODE = 2
5032 09:31:14.924894 SELPH_MODE = 1
5033 09:31:14.928700 PICG_EARLY_EN = 1
5034 09:31:14.931581 VALID_LAT_VALUE = 1
5035 09:31:14.935309 ==============================================================
5036 09:31:14.938583 Enter into Gating configuration >>>>
5037 09:31:14.941825 Exit from Gating configuration <<<<
5038 09:31:14.945159 Enter into DVFS_PRE_config >>>>>
5039 09:31:14.958390 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5040 09:31:14.958949 Exit from DVFS_PRE_config <<<<<
5041 09:31:14.961355 Enter into PICG configuration >>>>
5042 09:31:14.965325 Exit from PICG configuration <<<<
5043 09:31:14.968381 [RX_INPUT] configuration >>>>>
5044 09:31:14.971582 [RX_INPUT] configuration <<<<<
5045 09:31:14.978586 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5046 09:31:14.981888 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5047 09:31:14.988543 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5048 09:31:14.995047 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5049 09:31:15.001208 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5050 09:31:15.008072 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5051 09:31:15.011426 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5052 09:31:15.014679 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5053 09:31:15.018441 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5054 09:31:15.025015 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5055 09:31:15.028484 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5056 09:31:15.031431 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5057 09:31:15.035182 ===================================
5058 09:31:15.038197 LPDDR4 DRAM CONFIGURATION
5059 09:31:15.041645 ===================================
5060 09:31:15.042114 EX_ROW_EN[0] = 0x0
5061 09:31:15.044762 EX_ROW_EN[1] = 0x0
5062 09:31:15.045230 LP4Y_EN = 0x0
5063 09:31:15.048475 WORK_FSP = 0x0
5064 09:31:15.051664 WL = 0x3
5065 09:31:15.052238 RL = 0x3
5066 09:31:15.054782 BL = 0x2
5067 09:31:15.055250 RPST = 0x0
5068 09:31:15.058274 RD_PRE = 0x0
5069 09:31:15.058739 WR_PRE = 0x1
5070 09:31:15.061952 WR_PST = 0x0
5071 09:31:15.062418 DBI_WR = 0x0
5072 09:31:15.065304 DBI_RD = 0x0
5073 09:31:15.065881 OTF = 0x1
5074 09:31:15.068114 ===================================
5075 09:31:15.072121 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5076 09:31:15.078168 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5077 09:31:15.081818 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5078 09:31:15.084880 ===================================
5079 09:31:15.088477 LPDDR4 DRAM CONFIGURATION
5080 09:31:15.092156 ===================================
5081 09:31:15.092784 EX_ROW_EN[0] = 0x10
5082 09:31:15.094905 EX_ROW_EN[1] = 0x0
5083 09:31:15.095426 LP4Y_EN = 0x0
5084 09:31:15.098491 WORK_FSP = 0x0
5085 09:31:15.098959 WL = 0x3
5086 09:31:15.101722 RL = 0x3
5087 09:31:15.102424 BL = 0x2
5088 09:31:15.105129 RPST = 0x0
5089 09:31:15.105599 RD_PRE = 0x0
5090 09:31:15.108074 WR_PRE = 0x1
5091 09:31:15.111545 WR_PST = 0x0
5092 09:31:15.112032 DBI_WR = 0x0
5093 09:31:15.114655 DBI_RD = 0x0
5094 09:31:15.115128 OTF = 0x1
5095 09:31:15.118524 ===================================
5096 09:31:15.124746 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5097 09:31:15.128298 nWR fixed to 30
5098 09:31:15.131852 [ModeRegInit_LP4] CH0 RK0
5099 09:31:15.132419 [ModeRegInit_LP4] CH0 RK1
5100 09:31:15.135390 [ModeRegInit_LP4] CH1 RK0
5101 09:31:15.138785 [ModeRegInit_LP4] CH1 RK1
5102 09:31:15.139346 match AC timing 9
5103 09:31:15.144999 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5104 09:31:15.148330 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5105 09:31:15.151821 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5106 09:31:15.158563 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5107 09:31:15.161633 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5108 09:31:15.162200 ==
5109 09:31:15.165222 Dram Type= 6, Freq= 0, CH_0, rank 0
5110 09:31:15.168379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 09:31:15.168986 ==
5112 09:31:15.175112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5113 09:31:15.181835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5114 09:31:15.184732 [CA 0] Center 37 (7~68) winsize 62
5115 09:31:15.188280 [CA 1] Center 38 (7~69) winsize 63
5116 09:31:15.191439 [CA 2] Center 35 (5~65) winsize 61
5117 09:31:15.194990 [CA 3] Center 35 (5~65) winsize 61
5118 09:31:15.198026 [CA 4] Center 34 (4~65) winsize 62
5119 09:31:15.201823 [CA 5] Center 33 (3~64) winsize 62
5120 09:31:15.202397
5121 09:31:15.205062 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5122 09:31:15.205549
5123 09:31:15.208052 [CATrainingPosCal] consider 1 rank data
5124 09:31:15.211141 u2DelayCellTimex100 = 270/100 ps
5125 09:31:15.214670 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5126 09:31:15.217784 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5127 09:31:15.221493 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5128 09:31:15.224821 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5129 09:31:15.228041 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5130 09:31:15.231849 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5131 09:31:15.234995
5132 09:31:15.238263 CA PerBit enable=1, Macro0, CA PI delay=33
5133 09:31:15.238753
5134 09:31:15.241108 [CBTSetCACLKResult] CA Dly = 33
5135 09:31:15.241579 CS Dly: 6 (0~37)
5136 09:31:15.241952 ==
5137 09:31:15.244740 Dram Type= 6, Freq= 0, CH_0, rank 1
5138 09:31:15.248076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5139 09:31:15.251239 ==
5140 09:31:15.254928 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5141 09:31:15.261509 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5142 09:31:15.264957 [CA 0] Center 38 (8~69) winsize 62
5143 09:31:15.267939 [CA 1] Center 38 (8~69) winsize 62
5144 09:31:15.271317 [CA 2] Center 35 (5~66) winsize 62
5145 09:31:15.274959 [CA 3] Center 35 (5~66) winsize 62
5146 09:31:15.277940 [CA 4] Center 34 (4~65) winsize 62
5147 09:31:15.281445 [CA 5] Center 34 (4~64) winsize 61
5148 09:31:15.282094
5149 09:31:15.284319 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5150 09:31:15.284886
5151 09:31:15.287965 [CATrainingPosCal] consider 2 rank data
5152 09:31:15.291377 u2DelayCellTimex100 = 270/100 ps
5153 09:31:15.294787 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5154 09:31:15.297784 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5155 09:31:15.301479 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5156 09:31:15.304683 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5157 09:31:15.308029 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5158 09:31:15.314497 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5159 09:31:15.314963
5160 09:31:15.318308 CA PerBit enable=1, Macro0, CA PI delay=34
5161 09:31:15.319057
5162 09:31:15.321185 [CBTSetCACLKResult] CA Dly = 34
5163 09:31:15.321856 CS Dly: 7 (0~39)
5164 09:31:15.322238
5165 09:31:15.324526 ----->DramcWriteLeveling(PI) begin...
5166 09:31:15.325047 ==
5167 09:31:15.327753 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 09:31:15.331203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 09:31:15.334321 ==
5170 09:31:15.335088 Write leveling (Byte 0): 34 => 34
5171 09:31:15.337847 Write leveling (Byte 1): 28 => 28
5172 09:31:15.340981 DramcWriteLeveling(PI) end<-----
5173 09:31:15.341458
5174 09:31:15.341825 ==
5175 09:31:15.344270 Dram Type= 6, Freq= 0, CH_0, rank 0
5176 09:31:15.351314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5177 09:31:15.351975 ==
5178 09:31:15.354282 [Gating] SW mode calibration
5179 09:31:15.360913 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5180 09:31:15.364350 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5181 09:31:15.371114 0 14 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5182 09:31:15.374582 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 09:31:15.377586 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 09:31:15.384479 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 09:31:15.387837 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 09:31:15.390852 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5187 09:31:15.394341 0 14 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
5188 09:31:15.401097 0 14 28 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
5189 09:31:15.404168 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5190 09:31:15.407911 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 09:31:15.414248 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 09:31:15.417295 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 09:31:15.420834 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 09:31:15.427192 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 09:31:15.430881 0 15 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5196 09:31:15.433705 0 15 28 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
5197 09:31:15.440701 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 09:31:15.444191 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 09:31:15.447036 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 09:31:15.453923 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 09:31:15.457053 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 09:31:15.460846 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 09:31:15.467404 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 09:31:15.470753 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5205 09:31:15.473746 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5206 09:31:15.480392 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 09:31:15.484004 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 09:31:15.486965 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 09:31:15.493733 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 09:31:15.497339 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 09:31:15.500301 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 09:31:15.506750 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 09:31:15.510149 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 09:31:15.513596 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 09:31:15.520621 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 09:31:15.523728 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 09:31:15.526833 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 09:31:15.533232 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 09:31:15.536869 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5220 09:31:15.540349 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5221 09:31:15.546460 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5222 09:31:15.546957 Total UI for P1: 0, mck2ui 16
5223 09:31:15.553520 best dqsien dly found for B0: ( 1, 2, 26)
5224 09:31:15.556851 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 09:31:15.560122 Total UI for P1: 0, mck2ui 16
5226 09:31:15.563708 best dqsien dly found for B1: ( 1, 3, 0)
5227 09:31:15.566470 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5228 09:31:15.570050 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5229 09:31:15.570529
5230 09:31:15.573175 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5231 09:31:15.576604 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5232 09:31:15.580033 [Gating] SW calibration Done
5233 09:31:15.580509 ==
5234 09:31:15.583894 Dram Type= 6, Freq= 0, CH_0, rank 0
5235 09:31:15.586659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5236 09:31:15.587142 ==
5237 09:31:15.590138 RX Vref Scan: 0
5238 09:31:15.590612
5239 09:31:15.591082 RX Vref 0 -> 0, step: 1
5240 09:31:15.593264
5241 09:31:15.593737 RX Delay -80 -> 252, step: 8
5242 09:31:15.600036 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5243 09:31:15.603384 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5244 09:31:15.606345 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5245 09:31:15.610059 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5246 09:31:15.613458 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5247 09:31:15.616522 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5248 09:31:15.623133 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5249 09:31:15.626543 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5250 09:31:15.630225 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5251 09:31:15.633010 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5252 09:31:15.636717 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5253 09:31:15.640205 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5254 09:31:15.646365 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5255 09:31:15.649926 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5256 09:31:15.652863 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5257 09:31:15.656377 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5258 09:31:15.656901 ==
5259 09:31:15.660005 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 09:31:15.662895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 09:31:15.666571 ==
5262 09:31:15.667149 DQS Delay:
5263 09:31:15.667528 DQS0 = 0, DQS1 = 0
5264 09:31:15.669835 DQM Delay:
5265 09:31:15.670301 DQM0 = 105, DQM1 = 90
5266 09:31:15.672928 DQ Delay:
5267 09:31:15.676753 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5268 09:31:15.679675 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5269 09:31:15.682922 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5270 09:31:15.686396 DQ12 =91, DQ13 =91, DQ14 =99, DQ15 =99
5271 09:31:15.686866
5272 09:31:15.687231
5273 09:31:15.687568 ==
5274 09:31:15.689949 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 09:31:15.692971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 09:31:15.693548 ==
5277 09:31:15.693978
5278 09:31:15.694329
5279 09:31:15.696491 TX Vref Scan disable
5280 09:31:15.697092 == TX Byte 0 ==
5281 09:31:15.703192 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5282 09:31:15.706062 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5283 09:31:15.706530 == TX Byte 1 ==
5284 09:31:15.713317 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5285 09:31:15.716128 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5286 09:31:15.716639 ==
5287 09:31:15.719959 Dram Type= 6, Freq= 0, CH_0, rank 0
5288 09:31:15.723034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 09:31:15.723615 ==
5290 09:31:15.723990
5291 09:31:15.726317
5292 09:31:15.726785 TX Vref Scan disable
5293 09:31:15.729420 == TX Byte 0 ==
5294 09:31:15.732583 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5295 09:31:15.736307 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5296 09:31:15.739119 == TX Byte 1 ==
5297 09:31:15.742757 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5298 09:31:15.745960 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5299 09:31:15.749586
5300 09:31:15.750161 [DATLAT]
5301 09:31:15.750536 Freq=933, CH0 RK0
5302 09:31:15.750887
5303 09:31:15.752835 DATLAT Default: 0xd
5304 09:31:15.753415 0, 0xFFFF, sum = 0
5305 09:31:15.756353 1, 0xFFFF, sum = 0
5306 09:31:15.756995 2, 0xFFFF, sum = 0
5307 09:31:15.759335 3, 0xFFFF, sum = 0
5308 09:31:15.759919 4, 0xFFFF, sum = 0
5309 09:31:15.762634 5, 0xFFFF, sum = 0
5310 09:31:15.765856 6, 0xFFFF, sum = 0
5311 09:31:15.766435 7, 0xFFFF, sum = 0
5312 09:31:15.769085 8, 0xFFFF, sum = 0
5313 09:31:15.769564 9, 0xFFFF, sum = 0
5314 09:31:15.772613 10, 0x0, sum = 1
5315 09:31:15.773303 11, 0x0, sum = 2
5316 09:31:15.773844 12, 0x0, sum = 3
5317 09:31:15.776116 13, 0x0, sum = 4
5318 09:31:15.776743 best_step = 11
5319 09:31:15.777126
5320 09:31:15.779025 ==
5321 09:31:15.779545 Dram Type= 6, Freq= 0, CH_0, rank 0
5322 09:31:15.785511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5323 09:31:15.786001 ==
5324 09:31:15.786378 RX Vref Scan: 1
5325 09:31:15.786728
5326 09:31:15.788970 RX Vref 0 -> 0, step: 1
5327 09:31:15.789552
5328 09:31:15.792671 RX Delay -53 -> 252, step: 4
5329 09:31:15.793163
5330 09:31:15.795449 Set Vref, RX VrefLevel [Byte0]: 59
5331 09:31:15.798895 [Byte1]: 49
5332 09:31:15.799367
5333 09:31:15.802704 Final RX Vref Byte 0 = 59 to rank0
5334 09:31:15.805640 Final RX Vref Byte 1 = 49 to rank0
5335 09:31:15.809235 Final RX Vref Byte 0 = 59 to rank1
5336 09:31:15.812127 Final RX Vref Byte 1 = 49 to rank1==
5337 09:31:15.815721 Dram Type= 6, Freq= 0, CH_0, rank 0
5338 09:31:15.818969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5339 09:31:15.819549 ==
5340 09:31:15.822561 DQS Delay:
5341 09:31:15.823193 DQS0 = 0, DQS1 = 0
5342 09:31:15.825357 DQM Delay:
5343 09:31:15.825827 DQM0 = 106, DQM1 = 91
5344 09:31:15.826202 DQ Delay:
5345 09:31:15.832349 DQ0 =106, DQ1 =106, DQ2 =102, DQ3 =106
5346 09:31:15.835972 DQ4 =106, DQ5 =98, DQ6 =114, DQ7 =114
5347 09:31:15.839000 DQ8 =84, DQ9 =76, DQ10 =92, DQ11 =90
5348 09:31:15.842626 DQ12 =94, DQ13 =92, DQ14 =104, DQ15 =98
5349 09:31:15.843209
5350 09:31:15.843585
5351 09:31:15.849227 [DQSOSCAuto] RK0, (LSB)MR18= 0x221e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
5352 09:31:15.852141 CH0 RK0: MR19=505, MR18=221E
5353 09:31:15.858856 CH0_RK0: MR19=0x505, MR18=0x221E, DQSOSC=411, MR23=63, INC=64, DEC=42
5354 09:31:15.859331
5355 09:31:15.862403 ----->DramcWriteLeveling(PI) begin...
5356 09:31:15.862884 ==
5357 09:31:15.865720 Dram Type= 6, Freq= 0, CH_0, rank 1
5358 09:31:15.868741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 09:31:15.869306 ==
5360 09:31:15.872052 Write leveling (Byte 0): 31 => 31
5361 09:31:15.875442 Write leveling (Byte 1): 29 => 29
5362 09:31:15.879119 DramcWriteLeveling(PI) end<-----
5363 09:31:15.879581
5364 09:31:15.879970 ==
5365 09:31:15.882057 Dram Type= 6, Freq= 0, CH_0, rank 1
5366 09:31:15.885664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5367 09:31:15.886126 ==
5368 09:31:15.888724 [Gating] SW mode calibration
5369 09:31:15.895288 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5370 09:31:15.901679 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5371 09:31:15.905078 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 09:31:15.908736 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5373 09:31:15.915501 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 09:31:15.918736 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 09:31:15.921911 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 09:31:15.928325 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 09:31:15.932027 0 14 24 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
5378 09:31:15.935798 0 14 28 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (1 0)
5379 09:31:15.941712 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5380 09:31:15.945260 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5381 09:31:15.949121 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 09:31:15.955462 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 09:31:15.958595 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 09:31:15.962282 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 09:31:15.968769 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5386 09:31:15.972087 0 15 28 | B1->B0 | 3535 4040 | 0 0 | (0 0) (1 1)
5387 09:31:15.975319 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 09:31:15.982219 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 09:31:15.985491 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 09:31:15.988860 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 09:31:15.995547 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 09:31:15.998620 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 09:31:16.001932 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 09:31:16.008733 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5395 09:31:16.011978 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 09:31:16.015282 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 09:31:16.021778 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 09:31:16.025004 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 09:31:16.028616 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 09:31:16.031700 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 09:31:16.038475 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 09:31:16.041985 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 09:31:16.045168 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 09:31:16.051621 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 09:31:16.054937 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 09:31:16.058660 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 09:31:16.065274 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 09:31:16.068920 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 09:31:16.071936 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5410 09:31:16.078680 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5411 09:31:16.081549 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5412 09:31:16.085090 Total UI for P1: 0, mck2ui 16
5413 09:31:16.088513 best dqsien dly found for B0: ( 1, 2, 28)
5414 09:31:16.091757 Total UI for P1: 0, mck2ui 16
5415 09:31:16.095366 best dqsien dly found for B1: ( 1, 2, 26)
5416 09:31:16.098455 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5417 09:31:16.101810 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5418 09:31:16.102274
5419 09:31:16.105068 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5420 09:31:16.108618 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5421 09:31:16.111399 [Gating] SW calibration Done
5422 09:31:16.111858 ==
5423 09:31:16.114675 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 09:31:16.118324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 09:31:16.121602 ==
5426 09:31:16.122067 RX Vref Scan: 0
5427 09:31:16.122426
5428 09:31:16.124720 RX Vref 0 -> 0, step: 1
5429 09:31:16.125182
5430 09:31:16.128144 RX Delay -80 -> 252, step: 8
5431 09:31:16.131811 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5432 09:31:16.135107 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5433 09:31:16.138443 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5434 09:31:16.141732 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5435 09:31:16.145459 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5436 09:31:16.151406 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5437 09:31:16.155241 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5438 09:31:16.158282 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5439 09:31:16.161904 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5440 09:31:16.164938 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5441 09:31:16.168259 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5442 09:31:16.175109 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5443 09:31:16.178105 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5444 09:31:16.181430 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5445 09:31:16.184866 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5446 09:31:16.188309 iDelay=208, Bit 15, Center 95 (8 ~ 183) 176
5447 09:31:16.188821 ==
5448 09:31:16.191299 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 09:31:16.197958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 09:31:16.198530 ==
5451 09:31:16.198903 DQS Delay:
5452 09:31:16.201321 DQS0 = 0, DQS1 = 0
5453 09:31:16.201789 DQM Delay:
5454 09:31:16.204592 DQM0 = 104, DQM1 = 89
5455 09:31:16.205160 DQ Delay:
5456 09:31:16.207772 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5457 09:31:16.211143 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5458 09:31:16.214180 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5459 09:31:16.217591 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =95
5460 09:31:16.218066
5461 09:31:16.218429
5462 09:31:16.218769 ==
5463 09:31:16.221018 Dram Type= 6, Freq= 0, CH_0, rank 1
5464 09:31:16.224523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5465 09:31:16.225037 ==
5466 09:31:16.225400
5467 09:31:16.225738
5468 09:31:16.227873 TX Vref Scan disable
5469 09:31:16.231028 == TX Byte 0 ==
5470 09:31:16.234307 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5471 09:31:16.237409 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5472 09:31:16.241242 == TX Byte 1 ==
5473 09:31:16.243872 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5474 09:31:16.247693 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5475 09:31:16.248276 ==
5476 09:31:16.250648 Dram Type= 6, Freq= 0, CH_0, rank 1
5477 09:31:16.257259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5478 09:31:16.257864 ==
5479 09:31:16.258236
5480 09:31:16.258573
5481 09:31:16.258900 TX Vref Scan disable
5482 09:31:16.261036 == TX Byte 0 ==
5483 09:31:16.264765 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5484 09:31:16.268360 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5485 09:31:16.271180 == TX Byte 1 ==
5486 09:31:16.274957 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5487 09:31:16.281319 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5488 09:31:16.281937
5489 09:31:16.282311 [DATLAT]
5490 09:31:16.282658 Freq=933, CH0 RK1
5491 09:31:16.282992
5492 09:31:16.284303 DATLAT Default: 0xb
5493 09:31:16.284997 0, 0xFFFF, sum = 0
5494 09:31:16.287881 1, 0xFFFF, sum = 0
5495 09:31:16.288355 2, 0xFFFF, sum = 0
5496 09:31:16.290976 3, 0xFFFF, sum = 0
5497 09:31:16.294646 4, 0xFFFF, sum = 0
5498 09:31:16.295118 5, 0xFFFF, sum = 0
5499 09:31:16.297682 6, 0xFFFF, sum = 0
5500 09:31:16.298157 7, 0xFFFF, sum = 0
5501 09:31:16.301306 8, 0xFFFF, sum = 0
5502 09:31:16.301888 9, 0xFFFF, sum = 0
5503 09:31:16.304293 10, 0x0, sum = 1
5504 09:31:16.304800 11, 0x0, sum = 2
5505 09:31:16.308093 12, 0x0, sum = 3
5506 09:31:16.308724 13, 0x0, sum = 4
5507 09:31:16.309111 best_step = 11
5508 09:31:16.309459
5509 09:31:16.311047 ==
5510 09:31:16.314153 Dram Type= 6, Freq= 0, CH_0, rank 1
5511 09:31:16.317700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 09:31:16.318221 ==
5513 09:31:16.318601 RX Vref Scan: 0
5514 09:31:16.318948
5515 09:31:16.320753 RX Vref 0 -> 0, step: 1
5516 09:31:16.321220
5517 09:31:16.324346 RX Delay -53 -> 252, step: 4
5518 09:31:16.327966 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5519 09:31:16.334310 iDelay=199, Bit 1, Center 104 (15 ~ 194) 180
5520 09:31:16.337958 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5521 09:31:16.341183 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5522 09:31:16.344334 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5523 09:31:16.348075 iDelay=199, Bit 5, Center 96 (11 ~ 182) 172
5524 09:31:16.354700 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5525 09:31:16.357712 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5526 09:31:16.360799 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5527 09:31:16.364427 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5528 09:31:16.367479 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5529 09:31:16.374105 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5530 09:31:16.377271 iDelay=199, Bit 12, Center 98 (15 ~ 182) 168
5531 09:31:16.380969 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5532 09:31:16.383868 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5533 09:31:16.387429 iDelay=199, Bit 15, Center 100 (19 ~ 182) 164
5534 09:31:16.387932 ==
5535 09:31:16.390606 Dram Type= 6, Freq= 0, CH_0, rank 1
5536 09:31:16.397289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 09:31:16.397767 ==
5538 09:31:16.398436 DQS Delay:
5539 09:31:16.400467 DQS0 = 0, DQS1 = 0
5540 09:31:16.400998 DQM Delay:
5541 09:31:16.401499 DQM0 = 103, DQM1 = 92
5542 09:31:16.403819 DQ Delay:
5543 09:31:16.407070 DQ0 =102, DQ1 =104, DQ2 =102, DQ3 =98
5544 09:31:16.410751 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =112
5545 09:31:16.413954 DQ8 =84, DQ9 =80, DQ10 =94, DQ11 =92
5546 09:31:16.417318 DQ12 =98, DQ13 =94, DQ14 =100, DQ15 =100
5547 09:31:16.417842
5548 09:31:16.418430
5549 09:31:16.423731 [DQSOSCAuto] RK1, (LSB)MR18= 0x2708, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 409 ps
5550 09:31:16.427466 CH0 RK1: MR19=505, MR18=2708
5551 09:31:16.434305 CH0_RK1: MR19=0x505, MR18=0x2708, DQSOSC=409, MR23=63, INC=64, DEC=43
5552 09:31:16.437445 [RxdqsGatingPostProcess] freq 933
5553 09:31:16.443767 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5554 09:31:16.447343 best DQS0 dly(2T, 0.5T) = (0, 10)
5555 09:31:16.447831 best DQS1 dly(2T, 0.5T) = (0, 11)
5556 09:31:16.450630 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5557 09:31:16.453964 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5558 09:31:16.457087 best DQS0 dly(2T, 0.5T) = (0, 10)
5559 09:31:16.460809 best DQS1 dly(2T, 0.5T) = (0, 10)
5560 09:31:16.463932 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5561 09:31:16.467269 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5562 09:31:16.470593 Pre-setting of DQS Precalculation
5563 09:31:16.477334 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5564 09:31:16.477922 ==
5565 09:31:16.480633 Dram Type= 6, Freq= 0, CH_1, rank 0
5566 09:31:16.484001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5567 09:31:16.484632 ==
5568 09:31:16.490754 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5569 09:31:16.494048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5570 09:31:16.497899 [CA 0] Center 37 (7~68) winsize 62
5571 09:31:16.501152 [CA 1] Center 37 (7~68) winsize 62
5572 09:31:16.504813 [CA 2] Center 35 (5~65) winsize 61
5573 09:31:16.507661 [CA 3] Center 35 (5~65) winsize 61
5574 09:31:16.511112 [CA 4] Center 35 (5~66) winsize 62
5575 09:31:16.514677 [CA 5] Center 34 (4~65) winsize 62
5576 09:31:16.515244
5577 09:31:16.517584 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5578 09:31:16.518077
5579 09:31:16.520680 [CATrainingPosCal] consider 1 rank data
5580 09:31:16.524053 u2DelayCellTimex100 = 270/100 ps
5581 09:31:16.527815 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5582 09:31:16.530957 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5583 09:31:16.537993 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5584 09:31:16.540689 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5585 09:31:16.544318 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5586 09:31:16.547595 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5587 09:31:16.548118
5588 09:31:16.551001 CA PerBit enable=1, Macro0, CA PI delay=34
5589 09:31:16.551502
5590 09:31:16.553934 [CBTSetCACLKResult] CA Dly = 34
5591 09:31:16.554400 CS Dly: 6 (0~37)
5592 09:31:16.557516 ==
5593 09:31:16.558022 Dram Type= 6, Freq= 0, CH_1, rank 1
5594 09:31:16.564027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5595 09:31:16.564535 ==
5596 09:31:16.568107 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5597 09:31:16.574179 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5598 09:31:16.577866 [CA 0] Center 38 (8~69) winsize 62
5599 09:31:16.581071 [CA 1] Center 38 (7~69) winsize 63
5600 09:31:16.584102 [CA 2] Center 36 (6~66) winsize 61
5601 09:31:16.587697 [CA 3] Center 35 (6~65) winsize 60
5602 09:31:16.590992 [CA 4] Center 35 (5~65) winsize 61
5603 09:31:16.594719 [CA 5] Center 35 (5~65) winsize 61
5604 09:31:16.595289
5605 09:31:16.597515 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5606 09:31:16.597982
5607 09:31:16.601273 [CATrainingPosCal] consider 2 rank data
5608 09:31:16.604127 u2DelayCellTimex100 = 270/100 ps
5609 09:31:16.607915 CA0 delay=38 (8~68),Diff = 3 PI (18 cell)
5610 09:31:16.610866 CA1 delay=37 (7~68),Diff = 2 PI (12 cell)
5611 09:31:16.617654 CA2 delay=35 (6~65),Diff = 0 PI (0 cell)
5612 09:31:16.620719 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
5613 09:31:16.624388 CA4 delay=35 (5~65),Diff = 0 PI (0 cell)
5614 09:31:16.628179 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
5615 09:31:16.628799
5616 09:31:16.630975 CA PerBit enable=1, Macro0, CA PI delay=35
5617 09:31:16.631445
5618 09:31:16.634028 [CBTSetCACLKResult] CA Dly = 35
5619 09:31:16.634497 CS Dly: 7 (0~39)
5620 09:31:16.634863
5621 09:31:16.637579 ----->DramcWriteLeveling(PI) begin...
5622 09:31:16.641114 ==
5623 09:31:16.644373 Dram Type= 6, Freq= 0, CH_1, rank 0
5624 09:31:16.647995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5625 09:31:16.648624 ==
5626 09:31:16.651064 Write leveling (Byte 0): 26 => 26
5627 09:31:16.654547 Write leveling (Byte 1): 27 => 27
5628 09:31:16.657692 DramcWriteLeveling(PI) end<-----
5629 09:31:16.658160
5630 09:31:16.658588 ==
5631 09:31:16.660655 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 09:31:16.664188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 09:31:16.664895 ==
5634 09:31:16.667745 [Gating] SW mode calibration
5635 09:31:16.674218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5636 09:31:16.681130 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5637 09:31:16.684126 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5638 09:31:16.687465 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 09:31:16.690779 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 09:31:16.697765 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 09:31:16.700892 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 09:31:16.704101 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 09:31:16.710644 0 14 24 | B1->B0 | 3232 3131 | 1 1 | (0 1) (0 0)
5644 09:31:16.714357 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 09:31:16.717588 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 09:31:16.724062 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 09:31:16.727304 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 09:31:16.730582 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 09:31:16.737209 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 09:31:16.740822 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 09:31:16.743813 0 15 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5652 09:31:16.751076 0 15 28 | B1->B0 | 4040 4343 | 0 0 | (0 0) (1 1)
5653 09:31:16.753913 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 09:31:16.757142 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 09:31:16.763380 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 09:31:16.766766 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 09:31:16.770121 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 09:31:16.776823 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 09:31:16.780278 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5660 09:31:16.783292 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 09:31:16.790033 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 09:31:16.793619 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 09:31:16.796553 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 09:31:16.800273 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 09:31:16.806876 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 09:31:16.810158 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 09:31:16.813180 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 09:31:16.819951 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 09:31:16.823614 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 09:31:16.826978 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 09:31:16.833747 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 09:31:16.836960 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 09:31:16.840433 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 09:31:16.846859 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5675 09:31:16.850128 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5676 09:31:16.853539 Total UI for P1: 0, mck2ui 16
5677 09:31:16.856514 best dqsien dly found for B0: ( 1, 2, 20)
5678 09:31:16.860396 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 09:31:16.863359 Total UI for P1: 0, mck2ui 16
5680 09:31:16.867034 best dqsien dly found for B1: ( 1, 2, 24)
5681 09:31:16.870381 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5682 09:31:16.873820 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5683 09:31:16.874309
5684 09:31:16.880399 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5685 09:31:16.883740 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5686 09:31:16.884210 [Gating] SW calibration Done
5687 09:31:16.887449 ==
5688 09:31:16.890493 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 09:31:16.893963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 09:31:16.894436 ==
5691 09:31:16.894801 RX Vref Scan: 0
5692 09:31:16.895228
5693 09:31:16.896844 RX Vref 0 -> 0, step: 1
5694 09:31:16.897309
5695 09:31:16.900696 RX Delay -80 -> 252, step: 8
5696 09:31:16.903733 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5697 09:31:16.907036 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5698 09:31:16.910088 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5699 09:31:16.916724 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5700 09:31:16.919902 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5701 09:31:16.923644 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5702 09:31:16.926690 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5703 09:31:16.930128 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5704 09:31:16.933509 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5705 09:31:16.940256 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5706 09:31:16.943838 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5707 09:31:16.947028 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5708 09:31:16.950243 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5709 09:31:16.953355 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5710 09:31:16.957038 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5711 09:31:16.963780 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5712 09:31:16.964354 ==
5713 09:31:16.966684 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 09:31:16.970207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 09:31:16.970777 ==
5716 09:31:16.971153 DQS Delay:
5717 09:31:16.973035 DQS0 = 0, DQS1 = 0
5718 09:31:16.973499 DQM Delay:
5719 09:31:16.976743 DQM0 = 101, DQM1 = 95
5720 09:31:16.977208 DQ Delay:
5721 09:31:16.980062 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5722 09:31:16.983309 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5723 09:31:16.986317 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5724 09:31:16.990205 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =103
5725 09:31:16.990774
5726 09:31:16.991170
5727 09:31:16.991518 ==
5728 09:31:16.993460 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 09:31:17.000066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 09:31:17.000649 ==
5731 09:31:17.001029
5732 09:31:17.001374
5733 09:31:17.001705 TX Vref Scan disable
5734 09:31:17.003131 == TX Byte 0 ==
5735 09:31:17.006342 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5736 09:31:17.010093 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5737 09:31:17.013091 == TX Byte 1 ==
5738 09:31:17.016921 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5739 09:31:17.020152 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5740 09:31:17.023134 ==
5741 09:31:17.026991 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 09:31:17.029878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 09:31:17.030357 ==
5744 09:31:17.030732
5745 09:31:17.031077
5746 09:31:17.033037 TX Vref Scan disable
5747 09:31:17.033508 == TX Byte 0 ==
5748 09:31:17.040139 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5749 09:31:17.043571 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5750 09:31:17.044142 == TX Byte 1 ==
5751 09:31:17.050163 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5752 09:31:17.052970 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5753 09:31:17.053446
5754 09:31:17.053817 [DATLAT]
5755 09:31:17.056681 Freq=933, CH1 RK0
5756 09:31:17.057251
5757 09:31:17.057623 DATLAT Default: 0xd
5758 09:31:17.059896 0, 0xFFFF, sum = 0
5759 09:31:17.060473 1, 0xFFFF, sum = 0
5760 09:31:17.063185 2, 0xFFFF, sum = 0
5761 09:31:17.063663 3, 0xFFFF, sum = 0
5762 09:31:17.066377 4, 0xFFFF, sum = 0
5763 09:31:17.066966 5, 0xFFFF, sum = 0
5764 09:31:17.069899 6, 0xFFFF, sum = 0
5765 09:31:17.070374 7, 0xFFFF, sum = 0
5766 09:31:17.072943 8, 0xFFFF, sum = 0
5767 09:31:17.073417 9, 0xFFFF, sum = 0
5768 09:31:17.076538 10, 0x0, sum = 1
5769 09:31:17.077042 11, 0x0, sum = 2
5770 09:31:17.080010 12, 0x0, sum = 3
5771 09:31:17.080625 13, 0x0, sum = 4
5772 09:31:17.083011 best_step = 11
5773 09:31:17.083475
5774 09:31:17.083859 ==
5775 09:31:17.086495 Dram Type= 6, Freq= 0, CH_1, rank 0
5776 09:31:17.089872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 09:31:17.090339 ==
5778 09:31:17.093007 RX Vref Scan: 1
5779 09:31:17.093399
5780 09:31:17.093756 RX Vref 0 -> 0, step: 1
5781 09:31:17.094085
5782 09:31:17.096666 RX Delay -53 -> 252, step: 4
5783 09:31:17.097131
5784 09:31:17.099623 Set Vref, RX VrefLevel [Byte0]: 51
5785 09:31:17.103123 [Byte1]: 53
5786 09:31:17.107020
5787 09:31:17.107583 Final RX Vref Byte 0 = 51 to rank0
5788 09:31:17.110652 Final RX Vref Byte 1 = 53 to rank0
5789 09:31:17.113562 Final RX Vref Byte 0 = 51 to rank1
5790 09:31:17.117146 Final RX Vref Byte 1 = 53 to rank1==
5791 09:31:17.120387 Dram Type= 6, Freq= 0, CH_1, rank 0
5792 09:31:17.127180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 09:31:17.127763 ==
5794 09:31:17.128139 DQS Delay:
5795 09:31:17.128482 DQS0 = 0, DQS1 = 0
5796 09:31:17.130520 DQM Delay:
5797 09:31:17.130981 DQM0 = 104, DQM1 = 97
5798 09:31:17.133607 DQ Delay:
5799 09:31:17.137212 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5800 09:31:17.140522 DQ4 =104, DQ5 =112, DQ6 =114, DQ7 =100
5801 09:31:17.143708 DQ8 =86, DQ9 =84, DQ10 =100, DQ11 =94
5802 09:31:17.147009 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =100
5803 09:31:17.147494
5804 09:31:17.147859
5805 09:31:17.153558 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5806 09:31:17.156667 CH1 RK0: MR19=505, MR18=1830
5807 09:31:17.163526 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5808 09:31:17.164095
5809 09:31:17.167195 ----->DramcWriteLeveling(PI) begin...
5810 09:31:17.167769 ==
5811 09:31:17.170045 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 09:31:17.173737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 09:31:17.174312 ==
5814 09:31:17.176808 Write leveling (Byte 0): 26 => 26
5815 09:31:17.180326 Write leveling (Byte 1): 28 => 28
5816 09:31:17.183499 DramcWriteLeveling(PI) end<-----
5817 09:31:17.183964
5818 09:31:17.184328 ==
5819 09:31:17.186632 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 09:31:17.193420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 09:31:17.193890 ==
5822 09:31:17.194259 [Gating] SW mode calibration
5823 09:31:17.203481 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5824 09:31:17.206627 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5825 09:31:17.210513 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 09:31:17.217035 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 09:31:17.220025 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 09:31:17.223877 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 09:31:17.230457 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 09:31:17.233426 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 09:31:17.236492 0 14 24 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 0)
5832 09:31:17.243862 0 14 28 | B1->B0 | 2626 2d2d | 0 0 | (1 0) (1 1)
5833 09:31:17.246950 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 09:31:17.250093 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 09:31:17.257161 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 09:31:17.259955 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 09:31:17.263780 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 09:31:17.270181 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 09:31:17.273159 0 15 24 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
5840 09:31:17.276781 0 15 28 | B1->B0 | 3a3a 3939 | 0 0 | (0 0) (0 0)
5841 09:31:17.280333 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5842 09:31:17.286836 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 09:31:17.290413 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 09:31:17.293803 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 09:31:17.300302 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 09:31:17.303772 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 09:31:17.306780 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5848 09:31:17.313511 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5849 09:31:17.317375 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 09:31:17.320337 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 09:31:17.327069 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 09:31:17.330279 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 09:31:17.333195 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 09:31:17.340293 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 09:31:17.343807 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 09:31:17.347401 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 09:31:17.353609 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 09:31:17.356653 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 09:31:17.360167 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 09:31:17.366775 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 09:31:17.370373 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 09:31:17.373492 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5863 09:31:17.377118 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5864 09:31:17.383674 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5865 09:31:17.386772 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5866 09:31:17.390129 Total UI for P1: 0, mck2ui 16
5867 09:31:17.393039 best dqsien dly found for B0: ( 1, 2, 28)
5868 09:31:17.396531 Total UI for P1: 0, mck2ui 16
5869 09:31:17.400224 best dqsien dly found for B1: ( 1, 2, 26)
5870 09:31:17.403551 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5871 09:31:17.406989 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5872 09:31:17.407519
5873 09:31:17.409955 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5874 09:31:17.416724 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5875 09:31:17.417354 [Gating] SW calibration Done
5876 09:31:17.417893 ==
5877 09:31:17.419752 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 09:31:17.426462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 09:31:17.426946 ==
5880 09:31:17.427324 RX Vref Scan: 0
5881 09:31:17.427674
5882 09:31:17.429405 RX Vref 0 -> 0, step: 1
5883 09:31:17.429875
5884 09:31:17.433151 RX Delay -80 -> 252, step: 8
5885 09:31:17.435995 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5886 09:31:17.439817 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5887 09:31:17.443251 iDelay=200, Bit 2, Center 91 (8 ~ 175) 168
5888 09:31:17.449409 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5889 09:31:17.453066 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5890 09:31:17.456260 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5891 09:31:17.459466 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5892 09:31:17.462921 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5893 09:31:17.466461 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5894 09:31:17.473190 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5895 09:31:17.476381 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5896 09:31:17.479811 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5897 09:31:17.483111 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5898 09:31:17.486120 iDelay=200, Bit 13, Center 107 (16 ~ 199) 184
5899 09:31:17.493297 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5900 09:31:17.496393 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5901 09:31:17.497045 ==
5902 09:31:17.499650 Dram Type= 6, Freq= 0, CH_1, rank 1
5903 09:31:17.502794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 09:31:17.503408 ==
5905 09:31:17.503784 DQS Delay:
5906 09:31:17.506083 DQS0 = 0, DQS1 = 0
5907 09:31:17.506545 DQM Delay:
5908 09:31:17.509609 DQM0 = 103, DQM1 = 98
5909 09:31:17.510075 DQ Delay:
5910 09:31:17.512514 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =103
5911 09:31:17.516195 DQ4 =103, DQ5 =111, DQ6 =107, DQ7 =103
5912 09:31:17.519750 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5913 09:31:17.522614 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5914 09:31:17.523209
5915 09:31:17.523785
5916 09:31:17.526503 ==
5917 09:31:17.527066 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 09:31:17.533114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 09:31:17.533685 ==
5920 09:31:17.534061
5921 09:31:17.534399
5922 09:31:17.536271 TX Vref Scan disable
5923 09:31:17.536904 == TX Byte 0 ==
5924 09:31:17.539349 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5925 09:31:17.546148 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5926 09:31:17.546717 == TX Byte 1 ==
5927 09:31:17.549605 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5928 09:31:17.555961 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5929 09:31:17.556579 ==
5930 09:31:17.559390 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 09:31:17.562531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 09:31:17.563002 ==
5933 09:31:17.563369
5934 09:31:17.563710
5935 09:31:17.565963 TX Vref Scan disable
5936 09:31:17.569260 == TX Byte 0 ==
5937 09:31:17.572508 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5938 09:31:17.575857 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5939 09:31:17.579582 == TX Byte 1 ==
5940 09:31:17.582690 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5941 09:31:17.585591 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5942 09:31:17.586058
5943 09:31:17.589274 [DATLAT]
5944 09:31:17.589836 Freq=933, CH1 RK1
5945 09:31:17.590211
5946 09:31:17.592567 DATLAT Default: 0xb
5947 09:31:17.593036 0, 0xFFFF, sum = 0
5948 09:31:17.595849 1, 0xFFFF, sum = 0
5949 09:31:17.596418 2, 0xFFFF, sum = 0
5950 09:31:17.599324 3, 0xFFFF, sum = 0
5951 09:31:17.599889 4, 0xFFFF, sum = 0
5952 09:31:17.602318 5, 0xFFFF, sum = 0
5953 09:31:17.602788 6, 0xFFFF, sum = 0
5954 09:31:17.605549 7, 0xFFFF, sum = 0
5955 09:31:17.606021 8, 0xFFFF, sum = 0
5956 09:31:17.609229 9, 0xFFFF, sum = 0
5957 09:31:17.609739 10, 0x0, sum = 1
5958 09:31:17.612302 11, 0x0, sum = 2
5959 09:31:17.612874 12, 0x0, sum = 3
5960 09:31:17.615998 13, 0x0, sum = 4
5961 09:31:17.616726 best_step = 11
5962 09:31:17.617122
5963 09:31:17.617497 ==
5964 09:31:17.619092 Dram Type= 6, Freq= 0, CH_1, rank 1
5965 09:31:17.622151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5966 09:31:17.625758 ==
5967 09:31:17.626222 RX Vref Scan: 0
5968 09:31:17.626594
5969 09:31:17.628889 RX Vref 0 -> 0, step: 1
5970 09:31:17.629356
5971 09:31:17.632040 RX Delay -53 -> 252, step: 4
5972 09:31:17.635571 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5973 09:31:17.638699 iDelay=199, Bit 1, Center 100 (23 ~ 178) 156
5974 09:31:17.645340 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5975 09:31:17.649185 iDelay=199, Bit 3, Center 102 (19 ~ 186) 168
5976 09:31:17.652186 iDelay=199, Bit 4, Center 108 (27 ~ 190) 164
5977 09:31:17.655770 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5978 09:31:17.658835 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5979 09:31:17.662319 iDelay=199, Bit 7, Center 102 (23 ~ 182) 160
5980 09:31:17.668534 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5981 09:31:17.672204 iDelay=199, Bit 9, Center 90 (7 ~ 174) 168
5982 09:31:17.675416 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5983 09:31:17.678576 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5984 09:31:17.682214 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5985 09:31:17.689141 iDelay=199, Bit 13, Center 102 (15 ~ 190) 176
5986 09:31:17.692007 iDelay=199, Bit 14, Center 104 (15 ~ 194) 180
5987 09:31:17.695729 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5988 09:31:17.696294 ==
5989 09:31:17.698863 Dram Type= 6, Freq= 0, CH_1, rank 1
5990 09:31:17.702380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5991 09:31:17.702951 ==
5992 09:31:17.705151 DQS Delay:
5993 09:31:17.705618 DQS0 = 0, DQS1 = 0
5994 09:31:17.708910 DQM Delay:
5995 09:31:17.709495 DQM0 = 105, DQM1 = 97
5996 09:31:17.709870 DQ Delay:
5997 09:31:17.711820 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =102
5998 09:31:17.715248 DQ4 =108, DQ5 =114, DQ6 =112, DQ7 =102
5999 09:31:17.718610 DQ8 =84, DQ9 =90, DQ10 =98, DQ11 =92
6000 09:31:17.725167 DQ12 =106, DQ13 =102, DQ14 =104, DQ15 =106
6001 09:31:17.725722
6002 09:31:17.726090
6003 09:31:17.732075 [DQSOSCAuto] RK1, (LSB)MR18= 0x2401, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 410 ps
6004 09:31:17.735347 CH1 RK1: MR19=505, MR18=2401
6005 09:31:17.741695 CH1_RK1: MR19=0x505, MR18=0x2401, DQSOSC=410, MR23=63, INC=64, DEC=42
6006 09:31:17.745239 [RxdqsGatingPostProcess] freq 933
6007 09:31:17.748747 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6008 09:31:17.751804 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 09:31:17.755474 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 09:31:17.758635 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 09:31:17.761803 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 09:31:17.765465 best DQS0 dly(2T, 0.5T) = (0, 10)
6013 09:31:17.768446 best DQS1 dly(2T, 0.5T) = (0, 10)
6014 09:31:17.771805 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6015 09:31:17.775134 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6016 09:31:17.778185 Pre-setting of DQS Precalculation
6017 09:31:17.781844 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6018 09:31:17.791779 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6019 09:31:17.798070 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6020 09:31:17.798540
6021 09:31:17.798904
6022 09:31:17.801743 [Calibration Summary] 1866 Mbps
6023 09:31:17.802207 CH 0, Rank 0
6024 09:31:17.804837 SW Impedance : PASS
6025 09:31:17.805304 DUTY Scan : NO K
6026 09:31:17.808587 ZQ Calibration : PASS
6027 09:31:17.811445 Jitter Meter : NO K
6028 09:31:17.811909 CBT Training : PASS
6029 09:31:17.815021 Write leveling : PASS
6030 09:31:17.818508 RX DQS gating : PASS
6031 09:31:17.818970 RX DQ/DQS(RDDQC) : PASS
6032 09:31:17.821593 TX DQ/DQS : PASS
6033 09:31:17.822060 RX DATLAT : PASS
6034 09:31:17.824806 RX DQ/DQS(Engine): PASS
6035 09:31:17.828090 TX OE : NO K
6036 09:31:17.828601 All Pass.
6037 09:31:17.828985
6038 09:31:17.829336 CH 0, Rank 1
6039 09:31:17.831490 SW Impedance : PASS
6040 09:31:17.835105 DUTY Scan : NO K
6041 09:31:17.835800 ZQ Calibration : PASS
6042 09:31:17.838357 Jitter Meter : NO K
6043 09:31:17.841177 CBT Training : PASS
6044 09:31:17.841650 Write leveling : PASS
6045 09:31:17.845131 RX DQS gating : PASS
6046 09:31:17.848176 RX DQ/DQS(RDDQC) : PASS
6047 09:31:17.848793 TX DQ/DQS : PASS
6048 09:31:17.851510 RX DATLAT : PASS
6049 09:31:17.854472 RX DQ/DQS(Engine): PASS
6050 09:31:17.854945 TX OE : NO K
6051 09:31:17.858148 All Pass.
6052 09:31:17.858619
6053 09:31:17.858986 CH 1, Rank 0
6054 09:31:17.861398 SW Impedance : PASS
6055 09:31:17.861967 DUTY Scan : NO K
6056 09:31:17.864892 ZQ Calibration : PASS
6057 09:31:17.868021 Jitter Meter : NO K
6058 09:31:17.868636 CBT Training : PASS
6059 09:31:17.871640 Write leveling : PASS
6060 09:31:17.872227 RX DQS gating : PASS
6061 09:31:17.874552 RX DQ/DQS(RDDQC) : PASS
6062 09:31:17.878220 TX DQ/DQS : PASS
6063 09:31:17.878794 RX DATLAT : PASS
6064 09:31:17.881863 RX DQ/DQS(Engine): PASS
6065 09:31:17.884722 TX OE : NO K
6066 09:31:17.885287 All Pass.
6067 09:31:17.885663
6068 09:31:17.886009 CH 1, Rank 1
6069 09:31:17.888114 SW Impedance : PASS
6070 09:31:17.891164 DUTY Scan : NO K
6071 09:31:17.891686 ZQ Calibration : PASS
6072 09:31:17.895026 Jitter Meter : NO K
6073 09:31:17.897891 CBT Training : PASS
6074 09:31:17.898357 Write leveling : PASS
6075 09:31:17.901679 RX DQS gating : PASS
6076 09:31:17.904497 RX DQ/DQS(RDDQC) : PASS
6077 09:31:17.905015 TX DQ/DQS : PASS
6078 09:31:17.908085 RX DATLAT : PASS
6079 09:31:17.911561 RX DQ/DQS(Engine): PASS
6080 09:31:17.912142 TX OE : NO K
6081 09:31:17.912524 All Pass.
6082 09:31:17.914765
6083 09:31:17.915231 DramC Write-DBI off
6084 09:31:17.917980 PER_BANK_REFRESH: Hybrid Mode
6085 09:31:17.918614 TX_TRACKING: ON
6086 09:31:17.928082 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6087 09:31:17.931402 [FAST_K] Save calibration result to emmc
6088 09:31:17.934778 dramc_set_vcore_voltage set vcore to 650000
6089 09:31:17.938330 Read voltage for 400, 6
6090 09:31:17.938898 Vio18 = 0
6091 09:31:17.941256 Vcore = 650000
6092 09:31:17.941717 Vdram = 0
6093 09:31:17.942085 Vddq = 0
6094 09:31:17.942424 Vmddr = 0
6095 09:31:17.948153 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6096 09:31:17.954717 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6097 09:31:17.955290 MEM_TYPE=3, freq_sel=20
6098 09:31:17.958375 sv_algorithm_assistance_LP4_800
6099 09:31:17.961131 ============ PULL DRAM RESETB DOWN ============
6100 09:31:17.968060 ========== PULL DRAM RESETB DOWN end =========
6101 09:31:17.971476 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6102 09:31:17.974467 ===================================
6103 09:31:17.978206 LPDDR4 DRAM CONFIGURATION
6104 09:31:17.981103 ===================================
6105 09:31:17.981579 EX_ROW_EN[0] = 0x0
6106 09:31:17.984925 EX_ROW_EN[1] = 0x0
6107 09:31:17.985499 LP4Y_EN = 0x0
6108 09:31:17.987852 WORK_FSP = 0x0
6109 09:31:17.988414 WL = 0x2
6110 09:31:17.990958 RL = 0x2
6111 09:31:17.991420 BL = 0x2
6112 09:31:17.994400 RPST = 0x0
6113 09:31:17.997710 RD_PRE = 0x0
6114 09:31:17.998280 WR_PRE = 0x1
6115 09:31:18.001116 WR_PST = 0x0
6116 09:31:18.001684 DBI_WR = 0x0
6117 09:31:18.004536 DBI_RD = 0x0
6118 09:31:18.005026 OTF = 0x1
6119 09:31:18.007838 ===================================
6120 09:31:18.011097 ===================================
6121 09:31:18.011667 ANA top config
6122 09:31:18.014631 ===================================
6123 09:31:18.017803 DLL_ASYNC_EN = 0
6124 09:31:18.021365 ALL_SLAVE_EN = 1
6125 09:31:18.024639 NEW_RANK_MODE = 1
6126 09:31:18.027683 DLL_IDLE_MODE = 1
6127 09:31:18.028148 LP45_APHY_COMB_EN = 1
6128 09:31:18.031219 TX_ODT_DIS = 1
6129 09:31:18.034294 NEW_8X_MODE = 1
6130 09:31:18.038041 ===================================
6131 09:31:18.041237 ===================================
6132 09:31:18.044667 data_rate = 800
6133 09:31:18.048234 CKR = 1
6134 09:31:18.048842 DQ_P2S_RATIO = 4
6135 09:31:18.051016 ===================================
6136 09:31:18.054587 CA_P2S_RATIO = 4
6137 09:31:18.057660 DQ_CA_OPEN = 0
6138 09:31:18.060956 DQ_SEMI_OPEN = 1
6139 09:31:18.064465 CA_SEMI_OPEN = 1
6140 09:31:18.067782 CA_FULL_RATE = 0
6141 09:31:18.068348 DQ_CKDIV4_EN = 0
6142 09:31:18.071402 CA_CKDIV4_EN = 1
6143 09:31:18.074159 CA_PREDIV_EN = 0
6144 09:31:18.077629 PH8_DLY = 0
6145 09:31:18.081343 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6146 09:31:18.084682 DQ_AAMCK_DIV = 0
6147 09:31:18.085264 CA_AAMCK_DIV = 0
6148 09:31:18.087777 CA_ADMCK_DIV = 4
6149 09:31:18.091100 DQ_TRACK_CA_EN = 0
6150 09:31:18.094542 CA_PICK = 800
6151 09:31:18.097696 CA_MCKIO = 400
6152 09:31:18.101182 MCKIO_SEMI = 400
6153 09:31:18.104838 PLL_FREQ = 3016
6154 09:31:18.105424 DQ_UI_PI_RATIO = 32
6155 09:31:18.107818 CA_UI_PI_RATIO = 32
6156 09:31:18.110683 ===================================
6157 09:31:18.114244 ===================================
6158 09:31:18.117886 memory_type:LPDDR4
6159 09:31:18.121130 GP_NUM : 10
6160 09:31:18.121700 SRAM_EN : 1
6161 09:31:18.124461 MD32_EN : 0
6162 09:31:18.127519 ===================================
6163 09:31:18.127989 [ANA_INIT] >>>>>>>>>>>>>>
6164 09:31:18.131093 <<<<<< [CONFIGURE PHASE]: ANA_TX
6165 09:31:18.134429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6166 09:31:18.137491 ===================================
6167 09:31:18.140979 data_rate = 800,PCW = 0X7400
6168 09:31:18.144446 ===================================
6169 09:31:18.147915 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6170 09:31:18.153955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6171 09:31:18.164356 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6172 09:31:18.171184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6173 09:31:18.174343 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6174 09:31:18.177681 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6175 09:31:18.178155 [ANA_INIT] flow start
6176 09:31:18.180774 [ANA_INIT] PLL >>>>>>>>
6177 09:31:18.184395 [ANA_INIT] PLL <<<<<<<<
6178 09:31:18.185116 [ANA_INIT] MIDPI >>>>>>>>
6179 09:31:18.187361 [ANA_INIT] MIDPI <<<<<<<<
6180 09:31:18.190961 [ANA_INIT] DLL >>>>>>>>
6181 09:31:18.191428 [ANA_INIT] flow end
6182 09:31:18.197195 ============ LP4 DIFF to SE enter ============
6183 09:31:18.200728 ============ LP4 DIFF to SE exit ============
6184 09:31:18.204245 [ANA_INIT] <<<<<<<<<<<<<
6185 09:31:18.207620 [Flow] Enable top DCM control >>>>>
6186 09:31:18.210798 [Flow] Enable top DCM control <<<<<
6187 09:31:18.211375 Enable DLL master slave shuffle
6188 09:31:18.217110 ==============================================================
6189 09:31:18.220693 Gating Mode config
6190 09:31:18.223853 ==============================================================
6191 09:31:18.227413 Config description:
6192 09:31:18.237175 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6193 09:31:18.244045 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6194 09:31:18.247279 SELPH_MODE 0: By rank 1: By Phase
6195 09:31:18.253815 ==============================================================
6196 09:31:18.256989 GAT_TRACK_EN = 0
6197 09:31:18.260640 RX_GATING_MODE = 2
6198 09:31:18.264060 RX_GATING_TRACK_MODE = 2
6199 09:31:18.267058 SELPH_MODE = 1
6200 09:31:18.267531 PICG_EARLY_EN = 1
6201 09:31:18.270849 VALID_LAT_VALUE = 1
6202 09:31:18.277437 ==============================================================
6203 09:31:18.280274 Enter into Gating configuration >>>>
6204 09:31:18.283748 Exit from Gating configuration <<<<
6205 09:31:18.287168 Enter into DVFS_PRE_config >>>>>
6206 09:31:18.297047 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6207 09:31:18.300543 Exit from DVFS_PRE_config <<<<<
6208 09:31:18.303936 Enter into PICG configuration >>>>
6209 09:31:18.307081 Exit from PICG configuration <<<<
6210 09:31:18.310502 [RX_INPUT] configuration >>>>>
6211 09:31:18.313871 [RX_INPUT] configuration <<<<<
6212 09:31:18.316945 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6213 09:31:18.323449 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6214 09:31:18.330190 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6215 09:31:18.336793 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6216 09:31:18.343992 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6217 09:31:18.347071 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6218 09:31:18.353391 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6219 09:31:18.356712 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6220 09:31:18.360179 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6221 09:31:18.363422 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6222 09:31:18.366466 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6223 09:31:18.373538 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6224 09:31:18.376610 ===================================
6225 09:31:18.379868 LPDDR4 DRAM CONFIGURATION
6226 09:31:18.379976 ===================================
6227 09:31:18.383345 EX_ROW_EN[0] = 0x0
6228 09:31:18.386939 EX_ROW_EN[1] = 0x0
6229 09:31:18.387036 LP4Y_EN = 0x0
6230 09:31:18.389922 WORK_FSP = 0x0
6231 09:31:18.390011 WL = 0x2
6232 09:31:18.393530 RL = 0x2
6233 09:31:18.393620 BL = 0x2
6234 09:31:18.396514 RPST = 0x0
6235 09:31:18.396637 RD_PRE = 0x0
6236 09:31:18.400022 WR_PRE = 0x1
6237 09:31:18.400105 WR_PST = 0x0
6238 09:31:18.403093 DBI_WR = 0x0
6239 09:31:18.403179 DBI_RD = 0x0
6240 09:31:18.406676 OTF = 0x1
6241 09:31:18.409734 ===================================
6242 09:31:18.413297 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6243 09:31:18.416219 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6244 09:31:18.423160 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6245 09:31:18.426173 ===================================
6246 09:31:18.426270 LPDDR4 DRAM CONFIGURATION
6247 09:31:18.429882 ===================================
6248 09:31:18.432930 EX_ROW_EN[0] = 0x10
6249 09:31:18.436519 EX_ROW_EN[1] = 0x0
6250 09:31:18.436635 LP4Y_EN = 0x0
6251 09:31:18.439666 WORK_FSP = 0x0
6252 09:31:18.439750 WL = 0x2
6253 09:31:18.442808 RL = 0x2
6254 09:31:18.442894 BL = 0x2
6255 09:31:18.446337 RPST = 0x0
6256 09:31:18.446429 RD_PRE = 0x0
6257 09:31:18.449255 WR_PRE = 0x1
6258 09:31:18.449339 WR_PST = 0x0
6259 09:31:18.452857 DBI_WR = 0x0
6260 09:31:18.452944 DBI_RD = 0x0
6261 09:31:18.456489 OTF = 0x1
6262 09:31:18.459369 ===================================
6263 09:31:18.465937 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6264 09:31:18.469586 nWR fixed to 30
6265 09:31:18.472734 [ModeRegInit_LP4] CH0 RK0
6266 09:31:18.472848 [ModeRegInit_LP4] CH0 RK1
6267 09:31:18.476061 [ModeRegInit_LP4] CH1 RK0
6268 09:31:18.479239 [ModeRegInit_LP4] CH1 RK1
6269 09:31:18.479354 match AC timing 19
6270 09:31:18.486311 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6271 09:31:18.489230 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6272 09:31:18.492725 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6273 09:31:18.499352 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6274 09:31:18.502885 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6275 09:31:18.503030 ==
6276 09:31:18.505922 Dram Type= 6, Freq= 0, CH_0, rank 0
6277 09:31:18.509530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6278 09:31:18.509655 ==
6279 09:31:18.516121 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6280 09:31:18.522691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6281 09:31:18.525794 [CA 0] Center 36 (8~64) winsize 57
6282 09:31:18.529416 [CA 1] Center 36 (8~64) winsize 57
6283 09:31:18.529562 [CA 2] Center 36 (8~64) winsize 57
6284 09:31:18.532373 [CA 3] Center 36 (8~64) winsize 57
6285 09:31:18.536068 [CA 4] Center 36 (8~64) winsize 57
6286 09:31:18.539133 [CA 5] Center 36 (8~64) winsize 57
6287 09:31:18.539225
6288 09:31:18.542619 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6289 09:31:18.542704
6290 09:31:18.549425 [CATrainingPosCal] consider 1 rank data
6291 09:31:18.549526 u2DelayCellTimex100 = 270/100 ps
6292 09:31:18.552391 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 09:31:18.558999 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 09:31:18.562658 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 09:31:18.565934 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 09:31:18.569559 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 09:31:18.572721 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 09:31:18.572806
6299 09:31:18.576262 CA PerBit enable=1, Macro0, CA PI delay=36
6300 09:31:18.576373
6301 09:31:18.579344 [CBTSetCACLKResult] CA Dly = 36
6302 09:31:18.579430 CS Dly: 1 (0~32)
6303 09:31:18.582479 ==
6304 09:31:18.586000 Dram Type= 6, Freq= 0, CH_0, rank 1
6305 09:31:18.589609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6306 09:31:18.589702 ==
6307 09:31:18.592575 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6308 09:31:18.599310 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6309 09:31:18.602829 [CA 0] Center 36 (8~64) winsize 57
6310 09:31:18.605965 [CA 1] Center 36 (8~64) winsize 57
6311 09:31:18.609472 [CA 2] Center 36 (8~64) winsize 57
6312 09:31:18.613029 [CA 3] Center 36 (8~64) winsize 57
6313 09:31:18.616166 [CA 4] Center 36 (8~64) winsize 57
6314 09:31:18.619186 [CA 5] Center 36 (8~64) winsize 57
6315 09:31:18.619270
6316 09:31:18.622713 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6317 09:31:18.622802
6318 09:31:18.626149 [CATrainingPosCal] consider 2 rank data
6319 09:31:18.628969 u2DelayCellTimex100 = 270/100 ps
6320 09:31:18.632580 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 09:31:18.635677 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 09:31:18.638866 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 09:31:18.642300 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 09:31:18.648827 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 09:31:18.652419 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 09:31:18.652529
6327 09:31:18.655559 CA PerBit enable=1, Macro0, CA PI delay=36
6328 09:31:18.655644
6329 09:31:18.659202 [CBTSetCACLKResult] CA Dly = 36
6330 09:31:18.659312 CS Dly: 1 (0~32)
6331 09:31:18.659391
6332 09:31:18.662189 ----->DramcWriteLeveling(PI) begin...
6333 09:31:18.662273 ==
6334 09:31:18.665705 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 09:31:18.672433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 09:31:18.672613 ==
6337 09:31:18.675989 Write leveling (Byte 0): 40 => 8
6338 09:31:18.676154 Write leveling (Byte 1): 32 => 0
6339 09:31:18.679169 DramcWriteLeveling(PI) end<-----
6340 09:31:18.679332
6341 09:31:18.679404 ==
6342 09:31:18.682730 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 09:31:18.689484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 09:31:18.689646 ==
6345 09:31:18.689719 [Gating] SW mode calibration
6346 09:31:18.699073 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6347 09:31:18.702641 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6348 09:31:18.705918 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6349 09:31:18.712868 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6350 09:31:18.716015 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6351 09:31:18.719333 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 09:31:18.726147 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6353 09:31:18.729056 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 09:31:18.732470 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 09:31:18.738910 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 09:31:18.742535 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 09:31:18.746103 Total UI for P1: 0, mck2ui 16
6358 09:31:18.749215 best dqsien dly found for B0: ( 0, 14, 24)
6359 09:31:18.752980 Total UI for P1: 0, mck2ui 16
6360 09:31:18.756050 best dqsien dly found for B1: ( 0, 14, 24)
6361 09:31:18.759198 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6362 09:31:18.762789 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6363 09:31:18.763242
6364 09:31:18.765856 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6365 09:31:18.769324 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6366 09:31:18.772833 [Gating] SW calibration Done
6367 09:31:18.773284 ==
6368 09:31:18.775745 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 09:31:18.782429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 09:31:18.782887 ==
6371 09:31:18.783242 RX Vref Scan: 0
6372 09:31:18.783574
6373 09:31:18.786136 RX Vref 0 -> 0, step: 1
6374 09:31:18.786871
6375 09:31:18.789054 RX Delay -410 -> 252, step: 16
6376 09:31:18.792658 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6377 09:31:18.795707 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6378 09:31:18.799232 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6379 09:31:18.805929 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6380 09:31:18.809346 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6381 09:31:18.812480 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6382 09:31:18.816137 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6383 09:31:18.822711 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6384 09:31:18.825708 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6385 09:31:18.829321 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6386 09:31:18.832727 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6387 09:31:18.838871 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6388 09:31:18.842640 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6389 09:31:18.845976 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6390 09:31:18.849015 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6391 09:31:18.856133 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6392 09:31:18.856793 ==
6393 09:31:18.859026 Dram Type= 6, Freq= 0, CH_0, rank 0
6394 09:31:18.862750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6395 09:31:18.863304 ==
6396 09:31:18.863668 DQS Delay:
6397 09:31:18.865702 DQS0 = 27, DQS1 = 43
6398 09:31:18.866158 DQM Delay:
6399 09:31:18.869353 DQM0 = 12, DQM1 = 11
6400 09:31:18.869817 DQ Delay:
6401 09:31:18.872762 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6402 09:31:18.875915 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6403 09:31:18.879551 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6404 09:31:18.882987 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6405 09:31:18.883549
6406 09:31:18.883908
6407 09:31:18.884239 ==
6408 09:31:18.886033 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 09:31:18.888928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 09:31:18.889387 ==
6411 09:31:18.889742
6412 09:31:18.892832
6413 09:31:18.893384 TX Vref Scan disable
6414 09:31:18.895874 == TX Byte 0 ==
6415 09:31:18.899020 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 09:31:18.902433 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 09:31:18.905925 == TX Byte 1 ==
6418 09:31:18.909028 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6419 09:31:18.912501 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6420 09:31:18.913006 ==
6421 09:31:18.915675 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 09:31:18.918725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 09:31:18.922391 ==
6424 09:31:18.922851
6425 09:31:18.923212
6426 09:31:18.923548 TX Vref Scan disable
6427 09:31:18.925930 == TX Byte 0 ==
6428 09:31:18.928996 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6429 09:31:18.932607 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6430 09:31:18.935666 == TX Byte 1 ==
6431 09:31:18.939344 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6432 09:31:18.942355 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6433 09:31:18.942925
6434 09:31:18.945600 [DATLAT]
6435 09:31:18.946060 Freq=400, CH0 RK0
6436 09:31:18.946424
6437 09:31:18.948927 DATLAT Default: 0xf
6438 09:31:18.949503 0, 0xFFFF, sum = 0
6439 09:31:18.952268 1, 0xFFFF, sum = 0
6440 09:31:18.952857 2, 0xFFFF, sum = 0
6441 09:31:18.955542 3, 0xFFFF, sum = 0
6442 09:31:18.956113 4, 0xFFFF, sum = 0
6443 09:31:18.958898 5, 0xFFFF, sum = 0
6444 09:31:18.959362 6, 0xFFFF, sum = 0
6445 09:31:18.961992 7, 0xFFFF, sum = 0
6446 09:31:18.962504 8, 0xFFFF, sum = 0
6447 09:31:18.965622 9, 0xFFFF, sum = 0
6448 09:31:18.966087 10, 0xFFFF, sum = 0
6449 09:31:18.968623 11, 0xFFFF, sum = 0
6450 09:31:18.969160 12, 0xFFFF, sum = 0
6451 09:31:18.972141 13, 0x0, sum = 1
6452 09:31:18.972659 14, 0x0, sum = 2
6453 09:31:18.975495 15, 0x0, sum = 3
6454 09:31:18.976131 16, 0x0, sum = 4
6455 09:31:18.978912 best_step = 14
6456 09:31:18.979452
6457 09:31:18.979828 ==
6458 09:31:18.981950 Dram Type= 6, Freq= 0, CH_0, rank 0
6459 09:31:18.985352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 09:31:18.985831 ==
6461 09:31:18.988851 RX Vref Scan: 1
6462 09:31:18.989427
6463 09:31:18.989803 RX Vref 0 -> 0, step: 1
6464 09:31:18.990150
6465 09:31:18.991688 RX Delay -327 -> 252, step: 8
6466 09:31:18.992183
6467 09:31:18.995111 Set Vref, RX VrefLevel [Byte0]: 59
6468 09:31:18.998149 [Byte1]: 49
6469 09:31:19.003340
6470 09:31:19.003909 Final RX Vref Byte 0 = 59 to rank0
6471 09:31:19.007032 Final RX Vref Byte 1 = 49 to rank0
6472 09:31:19.009802 Final RX Vref Byte 0 = 59 to rank1
6473 09:31:19.013167 Final RX Vref Byte 1 = 49 to rank1==
6474 09:31:19.016941 Dram Type= 6, Freq= 0, CH_0, rank 0
6475 09:31:19.023503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 09:31:19.024087 ==
6477 09:31:19.024466 DQS Delay:
6478 09:31:19.026917 DQS0 = 28, DQS1 = 48
6479 09:31:19.027428 DQM Delay:
6480 09:31:19.027808 DQM0 = 11, DQM1 = 15
6481 09:31:19.029805 DQ Delay:
6482 09:31:19.033018 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6483 09:31:19.033492 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =20
6484 09:31:19.036708 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6485 09:31:19.040213 DQ12 =20, DQ13 =16, DQ14 =28, DQ15 =24
6486 09:31:19.040843
6487 09:31:19.041222
6488 09:31:19.050020 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 387 ps
6489 09:31:19.053433 CH0 RK0: MR19=C0C, MR18=B0A7
6490 09:31:19.059959 CH0_RK0: MR19=0xC0C, MR18=0xB0A7, DQSOSC=387, MR23=63, INC=394, DEC=262
6491 09:31:19.060528 ==
6492 09:31:19.062998 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 09:31:19.066824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 09:31:19.067396 ==
6495 09:31:19.069652 [Gating] SW mode calibration
6496 09:31:19.076294 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6497 09:31:19.083284 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6498 09:31:19.086209 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6499 09:31:19.089909 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 09:31:19.092940 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6501 09:31:19.099800 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 09:31:19.102827 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6503 09:31:19.106421 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 09:31:19.113149 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 09:31:19.116230 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 09:31:19.119739 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 09:31:19.122767 Total UI for P1: 0, mck2ui 16
6508 09:31:19.126592 best dqsien dly found for B0: ( 0, 14, 24)
6509 09:31:19.129885 Total UI for P1: 0, mck2ui 16
6510 09:31:19.132961 best dqsien dly found for B1: ( 0, 14, 24)
6511 09:31:19.136683 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6512 09:31:19.139877 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6513 09:31:19.142906
6514 09:31:19.146181 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6515 09:31:19.150076 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6516 09:31:19.152952 [Gating] SW calibration Done
6517 09:31:19.153448 ==
6518 09:31:19.156334 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 09:31:19.159868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 09:31:19.160441 ==
6521 09:31:19.160895 RX Vref Scan: 0
6522 09:31:19.161251
6523 09:31:19.162623 RX Vref 0 -> 0, step: 1
6524 09:31:19.163097
6525 09:31:19.166226 RX Delay -410 -> 252, step: 16
6526 09:31:19.169490 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6527 09:31:19.176145 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6528 09:31:19.179164 iDelay=230, Bit 2, Center -11 (-234 ~ 213) 448
6529 09:31:19.182702 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6530 09:31:19.185989 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6531 09:31:19.192720 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6532 09:31:19.196191 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6533 09:31:19.199326 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6534 09:31:19.202756 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6535 09:31:19.206287 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6536 09:31:19.212991 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6537 09:31:19.216361 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6538 09:31:19.219351 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6539 09:31:19.226322 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6540 09:31:19.229711 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6541 09:31:19.232695 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6542 09:31:19.233161 ==
6543 09:31:19.236225 Dram Type= 6, Freq= 0, CH_0, rank 1
6544 09:31:19.239594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 09:31:19.243077 ==
6546 09:31:19.243656 DQS Delay:
6547 09:31:19.244035 DQS0 = 27, DQS1 = 43
6548 09:31:19.245761 DQM Delay:
6549 09:31:19.246232 DQM0 = 15, DQM1 = 14
6550 09:31:19.249496 DQ Delay:
6551 09:31:19.250072 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =8
6552 09:31:19.252580 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6553 09:31:19.255786 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6554 09:31:19.259509 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6555 09:31:19.260091
6556 09:31:19.260467
6557 09:31:19.262488 ==
6558 09:31:19.265860 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 09:31:19.269180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 09:31:19.269768 ==
6561 09:31:19.270255
6562 09:31:19.270708
6563 09:31:19.272187 TX Vref Scan disable
6564 09:31:19.272706 == TX Byte 0 ==
6565 09:31:19.275873 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6566 09:31:19.282779 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6567 09:31:19.283365 == TX Byte 1 ==
6568 09:31:19.285610 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6569 09:31:19.288903 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6570 09:31:19.292529 ==
6571 09:31:19.295489 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 09:31:19.298945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 09:31:19.299436 ==
6574 09:31:19.299921
6575 09:31:19.300463
6576 09:31:19.302370 TX Vref Scan disable
6577 09:31:19.302853 == TX Byte 0 ==
6578 09:31:19.305636 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6579 09:31:19.312300 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6580 09:31:19.312827 == TX Byte 1 ==
6581 09:31:19.315925 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6582 09:31:19.319084 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6583 09:31:19.322221
6584 09:31:19.322688 [DATLAT]
6585 09:31:19.323059 Freq=400, CH0 RK1
6586 09:31:19.323406
6587 09:31:19.325962 DATLAT Default: 0xe
6588 09:31:19.326523 0, 0xFFFF, sum = 0
6589 09:31:19.329092 1, 0xFFFF, sum = 0
6590 09:31:19.329662 2, 0xFFFF, sum = 0
6591 09:31:19.332056 3, 0xFFFF, sum = 0
6592 09:31:19.332805 4, 0xFFFF, sum = 0
6593 09:31:19.335796 5, 0xFFFF, sum = 0
6594 09:31:19.338536 6, 0xFFFF, sum = 0
6595 09:31:19.339009 7, 0xFFFF, sum = 0
6596 09:31:19.342302 8, 0xFFFF, sum = 0
6597 09:31:19.342867 9, 0xFFFF, sum = 0
6598 09:31:19.345676 10, 0xFFFF, sum = 0
6599 09:31:19.346215 11, 0xFFFF, sum = 0
6600 09:31:19.348494 12, 0xFFFF, sum = 0
6601 09:31:19.349040 13, 0x0, sum = 1
6602 09:31:19.352051 14, 0x0, sum = 2
6603 09:31:19.352524 15, 0x0, sum = 3
6604 09:31:19.355095 16, 0x0, sum = 4
6605 09:31:19.355568 best_step = 14
6606 09:31:19.355938
6607 09:31:19.356281 ==
6608 09:31:19.358685 Dram Type= 6, Freq= 0, CH_0, rank 1
6609 09:31:19.362178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 09:31:19.365189 ==
6611 09:31:19.365714 RX Vref Scan: 0
6612 09:31:19.366101
6613 09:31:19.368489 RX Vref 0 -> 0, step: 1
6614 09:31:19.369024
6615 09:31:19.371782 RX Delay -327 -> 252, step: 8
6616 09:31:19.374989 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6617 09:31:19.381836 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6618 09:31:19.385381 iDelay=217, Bit 2, Center -24 (-247 ~ 200) 448
6619 09:31:19.388318 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6620 09:31:19.392244 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6621 09:31:19.398507 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6622 09:31:19.401514 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6623 09:31:19.405089 iDelay=217, Bit 7, Center -12 (-239 ~ 216) 456
6624 09:31:19.408594 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6625 09:31:19.415053 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6626 09:31:19.418016 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6627 09:31:19.421605 iDelay=217, Bit 11, Center -36 (-263 ~ 192) 456
6628 09:31:19.428189 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6629 09:31:19.431284 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6630 09:31:19.435177 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6631 09:31:19.438073 iDelay=217, Bit 15, Center -24 (-247 ~ 200) 448
6632 09:31:19.438551 ==
6633 09:31:19.441797 Dram Type= 6, Freq= 0, CH_0, rank 1
6634 09:31:19.448056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6635 09:31:19.448669 ==
6636 09:31:19.449051 DQS Delay:
6637 09:31:19.451626 DQS0 = 28, DQS1 = 44
6638 09:31:19.452200 DQM Delay:
6639 09:31:19.454455 DQM0 = 9, DQM1 = 14
6640 09:31:19.454926 DQ Delay:
6641 09:31:19.458303 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6642 09:31:19.461096 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6643 09:31:19.461568 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6644 09:31:19.468389 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6645 09:31:19.469030
6646 09:31:19.469410
6647 09:31:19.474530 [DQSOSCAuto] RK1, (LSB)MR18= 0xc073, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6648 09:31:19.477894 CH0 RK1: MR19=C0C, MR18=C073
6649 09:31:19.484762 CH0_RK1: MR19=0xC0C, MR18=0xC073, DQSOSC=386, MR23=63, INC=396, DEC=264
6650 09:31:19.488018 [RxdqsGatingPostProcess] freq 400
6651 09:31:19.491188 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6652 09:31:19.494792 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 09:31:19.498191 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 09:31:19.501158 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 09:31:19.504892 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 09:31:19.508076 best DQS0 dly(2T, 0.5T) = (0, 10)
6657 09:31:19.510836 best DQS1 dly(2T, 0.5T) = (0, 10)
6658 09:31:19.514482 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6659 09:31:19.517744 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6660 09:31:19.520845 Pre-setting of DQS Precalculation
6661 09:31:19.524447 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6662 09:31:19.524942 ==
6663 09:31:19.527505 Dram Type= 6, Freq= 0, CH_1, rank 0
6664 09:31:19.534179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6665 09:31:19.534912 ==
6666 09:31:19.537795 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6667 09:31:19.544504 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6668 09:31:19.547520 [CA 0] Center 36 (8~64) winsize 57
6669 09:31:19.551169 [CA 1] Center 36 (8~64) winsize 57
6670 09:31:19.554200 [CA 2] Center 36 (8~64) winsize 57
6671 09:31:19.557310 [CA 3] Center 36 (8~64) winsize 57
6672 09:31:19.560941 [CA 4] Center 36 (8~64) winsize 57
6673 09:31:19.564187 [CA 5] Center 36 (8~64) winsize 57
6674 09:31:19.564798
6675 09:31:19.567707 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6676 09:31:19.568277
6677 09:31:19.571266 [CATrainingPosCal] consider 1 rank data
6678 09:31:19.574108 u2DelayCellTimex100 = 270/100 ps
6679 09:31:19.577571 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 09:31:19.580671 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 09:31:19.584351 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 09:31:19.587546 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 09:31:19.590918 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 09:31:19.593994 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 09:31:19.597468
6686 09:31:19.601024 CA PerBit enable=1, Macro0, CA PI delay=36
6687 09:31:19.601594
6688 09:31:19.604450 [CBTSetCACLKResult] CA Dly = 36
6689 09:31:19.605144 CS Dly: 1 (0~32)
6690 09:31:19.605542 ==
6691 09:31:19.607448 Dram Type= 6, Freq= 0, CH_1, rank 1
6692 09:31:19.610435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6693 09:31:19.610913 ==
6694 09:31:19.617570 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6695 09:31:19.623961 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6696 09:31:19.627150 [CA 0] Center 36 (8~64) winsize 57
6697 09:31:19.630687 [CA 1] Center 36 (8~64) winsize 57
6698 09:31:19.633699 [CA 2] Center 36 (8~64) winsize 57
6699 09:31:19.637366 [CA 3] Center 36 (8~64) winsize 57
6700 09:31:19.637860 [CA 4] Center 36 (8~64) winsize 57
6701 09:31:19.640393 [CA 5] Center 36 (8~64) winsize 57
6702 09:31:19.640965
6703 09:31:19.647047 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6704 09:31:19.647544
6705 09:31:19.650530 [CATrainingPosCal] consider 2 rank data
6706 09:31:19.653948 u2DelayCellTimex100 = 270/100 ps
6707 09:31:19.657075 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 09:31:19.660699 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 09:31:19.663710 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 09:31:19.666910 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 09:31:19.670402 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 09:31:19.673876 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 09:31:19.674431
6714 09:31:19.677020 CA PerBit enable=1, Macro0, CA PI delay=36
6715 09:31:19.677546
6716 09:31:19.680517 [CBTSetCACLKResult] CA Dly = 36
6717 09:31:19.683754 CS Dly: 1 (0~32)
6718 09:31:19.684319
6719 09:31:19.687154 ----->DramcWriteLeveling(PI) begin...
6720 09:31:19.687709 ==
6721 09:31:19.690377 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 09:31:19.693838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 09:31:19.694308 ==
6724 09:31:19.697025 Write leveling (Byte 0): 40 => 8
6725 09:31:19.700441 Write leveling (Byte 1): 32 => 0
6726 09:31:19.703524 DramcWriteLeveling(PI) end<-----
6727 09:31:19.703865
6728 09:31:19.704058 ==
6729 09:31:19.706933 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 09:31:19.709844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 09:31:19.710041 ==
6732 09:31:19.713487 [Gating] SW mode calibration
6733 09:31:19.719912 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6734 09:31:19.726878 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6735 09:31:19.730288 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6736 09:31:19.733196 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6737 09:31:19.739871 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6738 09:31:19.743482 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 09:31:19.746476 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6740 09:31:19.753084 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 09:31:19.756607 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 09:31:19.760212 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 09:31:19.766798 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 09:31:19.766884 Total UI for P1: 0, mck2ui 16
6745 09:31:19.773553 best dqsien dly found for B0: ( 0, 14, 24)
6746 09:31:19.773638 Total UI for P1: 0, mck2ui 16
6747 09:31:19.780200 best dqsien dly found for B1: ( 0, 14, 24)
6748 09:31:19.783208 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6749 09:31:19.786389 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6750 09:31:19.786475
6751 09:31:19.789885 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6752 09:31:19.792954 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6753 09:31:19.796684 [Gating] SW calibration Done
6754 09:31:19.796772 ==
6755 09:31:19.799820 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 09:31:19.803419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 09:31:19.803505 ==
6758 09:31:19.806567 RX Vref Scan: 0
6759 09:31:19.806651
6760 09:31:19.806736 RX Vref 0 -> 0, step: 1
6761 09:31:19.806815
6762 09:31:19.809619 RX Delay -410 -> 252, step: 16
6763 09:31:19.816314 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6764 09:31:19.819868 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6765 09:31:19.823229 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6766 09:31:19.826383 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6767 09:31:19.832864 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6768 09:31:19.836062 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6769 09:31:19.839633 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6770 09:31:19.843192 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6771 09:31:19.849790 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6772 09:31:19.852948 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6773 09:31:19.856040 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6774 09:31:19.859554 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6775 09:31:19.866112 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6776 09:31:19.869245 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6777 09:31:19.872838 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6778 09:31:19.875858 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6779 09:31:19.879430 ==
6780 09:31:19.882505 Dram Type= 6, Freq= 0, CH_1, rank 0
6781 09:31:19.886019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6782 09:31:19.886119 ==
6783 09:31:19.886206 DQS Delay:
6784 09:31:19.889171 DQS0 = 27, DQS1 = 43
6785 09:31:19.889272 DQM Delay:
6786 09:31:19.892770 DQM0 = 9, DQM1 = 17
6787 09:31:19.892859 DQ Delay:
6788 09:31:19.895723 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6789 09:31:19.899281 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =0
6790 09:31:19.902239 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6791 09:31:19.905822 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6792 09:31:19.905923
6793 09:31:19.905991
6794 09:31:19.906051 ==
6795 09:31:19.908834 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 09:31:19.912419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 09:31:19.912508 ==
6798 09:31:19.912610
6799 09:31:19.912671
6800 09:31:19.915588 TX Vref Scan disable
6801 09:31:19.915672 == TX Byte 0 ==
6802 09:31:19.922350 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 09:31:19.925381 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 09:31:19.925469 == TX Byte 1 ==
6805 09:31:19.932439 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6806 09:31:19.935498 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6807 09:31:19.935593 ==
6808 09:31:19.938897 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 09:31:19.941856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 09:31:19.941942 ==
6811 09:31:19.942008
6812 09:31:19.942068
6813 09:31:19.945437 TX Vref Scan disable
6814 09:31:19.945521 == TX Byte 0 ==
6815 09:31:19.952209 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6816 09:31:19.955337 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6817 09:31:19.955422 == TX Byte 1 ==
6818 09:31:19.962026 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6819 09:31:19.965185 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6820 09:31:19.965272
6821 09:31:19.965337 [DATLAT]
6822 09:31:19.968778 Freq=400, CH1 RK0
6823 09:31:19.968863
6824 09:31:19.968928 DATLAT Default: 0xf
6825 09:31:19.971838 0, 0xFFFF, sum = 0
6826 09:31:19.971923 1, 0xFFFF, sum = 0
6827 09:31:19.975585 2, 0xFFFF, sum = 0
6828 09:31:19.975670 3, 0xFFFF, sum = 0
6829 09:31:19.978569 4, 0xFFFF, sum = 0
6830 09:31:19.981582 5, 0xFFFF, sum = 0
6831 09:31:19.981667 6, 0xFFFF, sum = 0
6832 09:31:19.985118 7, 0xFFFF, sum = 0
6833 09:31:19.985203 8, 0xFFFF, sum = 0
6834 09:31:19.988671 9, 0xFFFF, sum = 0
6835 09:31:19.988757 10, 0xFFFF, sum = 0
6836 09:31:19.991874 11, 0xFFFF, sum = 0
6837 09:31:19.991958 12, 0xFFFF, sum = 0
6838 09:31:19.995460 13, 0x0, sum = 1
6839 09:31:19.995546 14, 0x0, sum = 2
6840 09:31:19.998479 15, 0x0, sum = 3
6841 09:31:19.998565 16, 0x0, sum = 4
6842 09:31:20.001973 best_step = 14
6843 09:31:20.002058
6844 09:31:20.002136 ==
6845 09:31:20.005143 Dram Type= 6, Freq= 0, CH_1, rank 0
6846 09:31:20.008387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 09:31:20.008496 ==
6848 09:31:20.008640 RX Vref Scan: 1
6849 09:31:20.008731
6850 09:31:20.011845 RX Vref 0 -> 0, step: 1
6851 09:31:20.011927
6852 09:31:20.015145 RX Delay -327 -> 252, step: 8
6853 09:31:20.015229
6854 09:31:20.018155 Set Vref, RX VrefLevel [Byte0]: 51
6855 09:31:20.021741 [Byte1]: 53
6856 09:31:20.025363
6857 09:31:20.025446 Final RX Vref Byte 0 = 51 to rank0
6858 09:31:20.028878 Final RX Vref Byte 1 = 53 to rank0
6859 09:31:20.032449 Final RX Vref Byte 0 = 51 to rank1
6860 09:31:20.035306 Final RX Vref Byte 1 = 53 to rank1==
6861 09:31:20.038838 Dram Type= 6, Freq= 0, CH_1, rank 0
6862 09:31:20.045358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 09:31:20.045450 ==
6864 09:31:20.045516 DQS Delay:
6865 09:31:20.048699 DQS0 = 32, DQS1 = 40
6866 09:31:20.048782 DQM Delay:
6867 09:31:20.048848 DQM0 = 11, DQM1 = 13
6868 09:31:20.052328 DQ Delay:
6869 09:31:20.055320 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6870 09:31:20.055405 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6871 09:31:20.058901 DQ8 =0, DQ9 =0, DQ10 =20, DQ11 =4
6872 09:31:20.061963 DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20
6873 09:31:20.062047
6874 09:31:20.065486
6875 09:31:20.072112 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0da, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 389 ps
6876 09:31:20.075221 CH1 RK0: MR19=C0C, MR18=A0DA
6877 09:31:20.081703 CH1_RK0: MR19=0xC0C, MR18=0xA0DA, DQSOSC=382, MR23=63, INC=404, DEC=269
6878 09:31:20.081793 ==
6879 09:31:20.085284 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 09:31:20.088796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 09:31:20.088881 ==
6882 09:31:20.091932 [Gating] SW mode calibration
6883 09:31:20.098582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6884 09:31:20.102117 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6885 09:31:20.108584 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6886 09:31:20.111733 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6887 09:31:20.115353 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6888 09:31:20.122027 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 09:31:20.125258 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6890 09:31:20.128817 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 09:31:20.134947 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 09:31:20.138524 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 09:31:20.141683 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 09:31:20.145334 Total UI for P1: 0, mck2ui 16
6895 09:31:20.148460 best dqsien dly found for B0: ( 0, 14, 24)
6896 09:31:20.151807 Total UI for P1: 0, mck2ui 16
6897 09:31:20.155383 best dqsien dly found for B1: ( 0, 14, 24)
6898 09:31:20.158464 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6899 09:31:20.162057 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6900 09:31:20.162140
6901 09:31:20.168675 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6902 09:31:20.171720 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6903 09:31:20.175331 [Gating] SW calibration Done
6904 09:31:20.175415 ==
6905 09:31:20.178481 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 09:31:20.182015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 09:31:20.182132 ==
6908 09:31:20.182202 RX Vref Scan: 0
6909 09:31:20.182265
6910 09:31:20.185030 RX Vref 0 -> 0, step: 1
6911 09:31:20.185122
6912 09:31:20.188113 RX Delay -410 -> 252, step: 16
6913 09:31:20.191732 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6914 09:31:20.198505 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6915 09:31:20.201592 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6916 09:31:20.205106 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6917 09:31:20.208125 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6918 09:31:20.215264 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6919 09:31:20.218445 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6920 09:31:20.221561 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6921 09:31:20.225223 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6922 09:31:20.228356 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6923 09:31:20.235082 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6924 09:31:20.238580 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6925 09:31:20.241595 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6926 09:31:20.248478 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6927 09:31:20.251606 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6928 09:31:20.255069 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6929 09:31:20.255175 ==
6930 09:31:20.258542 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 09:31:20.261546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 09:31:20.265079 ==
6933 09:31:20.265185 DQS Delay:
6934 09:31:20.265250 DQS0 = 35, DQS1 = 43
6935 09:31:20.268201 DQM Delay:
6936 09:31:20.268282 DQM0 = 16, DQM1 = 18
6937 09:31:20.271667 DQ Delay:
6938 09:31:20.271750 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6939 09:31:20.274799 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6940 09:31:20.278443 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6941 09:31:20.281430 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =32
6942 09:31:20.281514
6943 09:31:20.281579
6944 09:31:20.285000 ==
6945 09:31:20.288010 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 09:31:20.291618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 09:31:20.291738 ==
6948 09:31:20.291829
6949 09:31:20.291899
6950 09:31:20.294707 TX Vref Scan disable
6951 09:31:20.294791 == TX Byte 0 ==
6952 09:31:20.298439 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6953 09:31:20.305028 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6954 09:31:20.305116 == TX Byte 1 ==
6955 09:31:20.308243 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6956 09:31:20.311658 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6957 09:31:20.315114 ==
6958 09:31:20.318246 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 09:31:20.321862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 09:31:20.321949 ==
6961 09:31:20.322015
6962 09:31:20.322076
6963 09:31:20.324844 TX Vref Scan disable
6964 09:31:20.324941 == TX Byte 0 ==
6965 09:31:20.328327 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6966 09:31:20.335030 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6967 09:31:20.335132 == TX Byte 1 ==
6968 09:31:20.338142 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6969 09:31:20.341731 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6970 09:31:20.344755
6971 09:31:20.344839 [DATLAT]
6972 09:31:20.344904 Freq=400, CH1 RK1
6973 09:31:20.344967
6974 09:31:20.348285 DATLAT Default: 0xe
6975 09:31:20.348375 0, 0xFFFF, sum = 0
6976 09:31:20.351852 1, 0xFFFF, sum = 0
6977 09:31:20.351936 2, 0xFFFF, sum = 0
6978 09:31:20.354816 3, 0xFFFF, sum = 0
6979 09:31:20.354901 4, 0xFFFF, sum = 0
6980 09:31:20.358286 5, 0xFFFF, sum = 0
6981 09:31:20.358372 6, 0xFFFF, sum = 0
6982 09:31:20.361675 7, 0xFFFF, sum = 0
6983 09:31:20.364679 8, 0xFFFF, sum = 0
6984 09:31:20.364764 9, 0xFFFF, sum = 0
6985 09:31:20.368243 10, 0xFFFF, sum = 0
6986 09:31:20.368330 11, 0xFFFF, sum = 0
6987 09:31:20.371344 12, 0xFFFF, sum = 0
6988 09:31:20.371457 13, 0x0, sum = 1
6989 09:31:20.374908 14, 0x0, sum = 2
6990 09:31:20.375020 15, 0x0, sum = 3
6991 09:31:20.377847 16, 0x0, sum = 4
6992 09:31:20.377967 best_step = 14
6993 09:31:20.378090
6994 09:31:20.378180 ==
6995 09:31:20.381673 Dram Type= 6, Freq= 0, CH_1, rank 1
6996 09:31:20.384504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6997 09:31:20.384613 ==
6998 09:31:20.388147 RX Vref Scan: 0
6999 09:31:20.388231
7000 09:31:20.391260 RX Vref 0 -> 0, step: 1
7001 09:31:20.391364
7002 09:31:20.391431 RX Delay -327 -> 252, step: 8
7003 09:31:20.399943 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
7004 09:31:20.403501 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
7005 09:31:20.406713 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
7006 09:31:20.410257 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
7007 09:31:20.416469 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
7008 09:31:20.419984 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
7009 09:31:20.423007 iDelay=217, Bit 6, Center -16 (-239 ~ 208) 448
7010 09:31:20.426588 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
7011 09:31:20.433188 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7012 09:31:20.436347 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
7013 09:31:20.439918 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
7014 09:31:20.443454 iDelay=217, Bit 11, Center -32 (-263 ~ 200) 464
7015 09:31:20.450066 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
7016 09:31:20.453035 iDelay=217, Bit 13, Center -20 (-247 ~ 208) 456
7017 09:31:20.456204 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
7018 09:31:20.463214 iDelay=217, Bit 15, Center -16 (-247 ~ 216) 464
7019 09:31:20.463320 ==
7020 09:31:20.466445 Dram Type= 6, Freq= 0, CH_1, rank 1
7021 09:31:20.469839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7022 09:31:20.469928 ==
7023 09:31:20.469996 DQS Delay:
7024 09:31:20.473460 DQS0 = 32, DQS1 = 36
7025 09:31:20.473546 DQM Delay:
7026 09:31:20.476516 DQM0 = 11, DQM1 = 10
7027 09:31:20.476616 DQ Delay:
7028 09:31:20.479741 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7029 09:31:20.483379 DQ4 =16, DQ5 =24, DQ6 =16, DQ7 =8
7030 09:31:20.486378 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7031 09:31:20.489757 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
7032 09:31:20.489843
7033 09:31:20.489909
7034 09:31:20.496420 [DQSOSCAuto] RK1, (LSB)MR18= 0xab54, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 388 ps
7035 09:31:20.499508 CH1 RK1: MR19=C0C, MR18=AB54
7036 09:31:20.506262 CH1_RK1: MR19=0xC0C, MR18=0xAB54, DQSOSC=388, MR23=63, INC=392, DEC=261
7037 09:31:20.509205 [RxdqsGatingPostProcess] freq 400
7038 09:31:20.516121 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7039 09:31:20.516219 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 09:31:20.519225 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 09:31:20.523054 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 09:31:20.525942 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 09:31:20.529485 best DQS0 dly(2T, 0.5T) = (0, 10)
7044 09:31:20.532801 best DQS1 dly(2T, 0.5T) = (0, 10)
7045 09:31:20.535957 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7046 09:31:20.539698 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7047 09:31:20.542777 Pre-setting of DQS Precalculation
7048 09:31:20.546415 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7049 09:31:20.556173 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7050 09:31:20.562693 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7051 09:31:20.562797
7052 09:31:20.562866
7053 09:31:20.566260 [Calibration Summary] 800 Mbps
7054 09:31:20.566348 CH 0, Rank 0
7055 09:31:20.569676 SW Impedance : PASS
7056 09:31:20.569763 DUTY Scan : NO K
7057 09:31:20.572959 ZQ Calibration : PASS
7058 09:31:20.575931 Jitter Meter : NO K
7059 09:31:20.576021 CBT Training : PASS
7060 09:31:20.579444 Write leveling : PASS
7061 09:31:20.582521 RX DQS gating : PASS
7062 09:31:20.582611 RX DQ/DQS(RDDQC) : PASS
7063 09:31:20.586172 TX DQ/DQS : PASS
7064 09:31:20.589581 RX DATLAT : PASS
7065 09:31:20.589669 RX DQ/DQS(Engine): PASS
7066 09:31:20.592657 TX OE : NO K
7067 09:31:20.592744 All Pass.
7068 09:31:20.592813
7069 09:31:20.596155 CH 0, Rank 1
7070 09:31:20.596245 SW Impedance : PASS
7071 09:31:20.599325 DUTY Scan : NO K
7072 09:31:20.602894 ZQ Calibration : PASS
7073 09:31:20.602983 Jitter Meter : NO K
7074 09:31:20.605882 CBT Training : PASS
7075 09:31:20.609630 Write leveling : NO K
7076 09:31:20.609718 RX DQS gating : PASS
7077 09:31:20.612746 RX DQ/DQS(RDDQC) : PASS
7078 09:31:20.612833 TX DQ/DQS : PASS
7079 09:31:20.615894 RX DATLAT : PASS
7080 09:31:20.619370 RX DQ/DQS(Engine): PASS
7081 09:31:20.619458 TX OE : NO K
7082 09:31:20.622527 All Pass.
7083 09:31:20.622614
7084 09:31:20.622682 CH 1, Rank 0
7085 09:31:20.626099 SW Impedance : PASS
7086 09:31:20.626186 DUTY Scan : NO K
7087 09:31:20.629567 ZQ Calibration : PASS
7088 09:31:20.632468 Jitter Meter : NO K
7089 09:31:20.632585 CBT Training : PASS
7090 09:31:20.636105 Write leveling : PASS
7091 09:31:20.639247 RX DQS gating : PASS
7092 09:31:20.639335 RX DQ/DQS(RDDQC) : PASS
7093 09:31:20.642710 TX DQ/DQS : PASS
7094 09:31:20.646148 RX DATLAT : PASS
7095 09:31:20.646235 RX DQ/DQS(Engine): PASS
7096 09:31:20.649259 TX OE : NO K
7097 09:31:20.649347 All Pass.
7098 09:31:20.649415
7099 09:31:20.652714 CH 1, Rank 1
7100 09:31:20.652799 SW Impedance : PASS
7101 09:31:20.655903 DUTY Scan : NO K
7102 09:31:20.659552 ZQ Calibration : PASS
7103 09:31:20.659638 Jitter Meter : NO K
7104 09:31:20.662589 CBT Training : PASS
7105 09:31:20.662673 Write leveling : NO K
7106 09:31:20.665974 RX DQS gating : PASS
7107 09:31:20.669082 RX DQ/DQS(RDDQC) : PASS
7108 09:31:20.669167 TX DQ/DQS : PASS
7109 09:31:20.672497 RX DATLAT : PASS
7110 09:31:20.675855 RX DQ/DQS(Engine): PASS
7111 09:31:20.675939 TX OE : NO K
7112 09:31:20.678863 All Pass.
7113 09:31:20.678947
7114 09:31:20.679013 DramC Write-DBI off
7115 09:31:20.682295 PER_BANK_REFRESH: Hybrid Mode
7116 09:31:20.685466 TX_TRACKING: ON
7117 09:31:20.692609 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7118 09:31:20.695686 [FAST_K] Save calibration result to emmc
7119 09:31:20.699124 dramc_set_vcore_voltage set vcore to 725000
7120 09:31:20.702395 Read voltage for 1600, 0
7121 09:31:20.702498 Vio18 = 0
7122 09:31:20.705333 Vcore = 725000
7123 09:31:20.705416 Vdram = 0
7124 09:31:20.705500 Vddq = 0
7125 09:31:20.709010 Vmddr = 0
7126 09:31:20.712127 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7127 09:31:20.718649 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7128 09:31:20.718765 MEM_TYPE=3, freq_sel=13
7129 09:31:20.722260 sv_algorithm_assistance_LP4_3733
7130 09:31:20.728819 ============ PULL DRAM RESETB DOWN ============
7131 09:31:20.731880 ========== PULL DRAM RESETB DOWN end =========
7132 09:31:20.735326 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7133 09:31:20.738833 ===================================
7134 09:31:20.742051 LPDDR4 DRAM CONFIGURATION
7135 09:31:20.745427 ===================================
7136 09:31:20.748957 EX_ROW_EN[0] = 0x0
7137 09:31:20.749068 EX_ROW_EN[1] = 0x0
7138 09:31:20.752007 LP4Y_EN = 0x0
7139 09:31:20.752136 WORK_FSP = 0x1
7140 09:31:20.755115 WL = 0x5
7141 09:31:20.755221 RL = 0x5
7142 09:31:20.758895 BL = 0x2
7143 09:31:20.759000 RPST = 0x0
7144 09:31:20.762096 RD_PRE = 0x0
7145 09:31:20.762261 WR_PRE = 0x1
7146 09:31:20.765033 WR_PST = 0x1
7147 09:31:20.765137 DBI_WR = 0x0
7148 09:31:20.768666 DBI_RD = 0x0
7149 09:31:20.768773 OTF = 0x1
7150 09:31:20.772207 ===================================
7151 09:31:20.775103 ===================================
7152 09:31:20.778642 ANA top config
7153 09:31:20.782073 ===================================
7154 09:31:20.785337 DLL_ASYNC_EN = 0
7155 09:31:20.785449 ALL_SLAVE_EN = 0
7156 09:31:20.788641 NEW_RANK_MODE = 1
7157 09:31:20.791679 DLL_IDLE_MODE = 1
7158 09:31:20.795421 LP45_APHY_COMB_EN = 1
7159 09:31:20.795503 TX_ODT_DIS = 0
7160 09:31:20.798377 NEW_8X_MODE = 1
7161 09:31:20.802062 ===================================
7162 09:31:20.805063 ===================================
7163 09:31:20.808798 data_rate = 3200
7164 09:31:20.811801 CKR = 1
7165 09:31:20.815402 DQ_P2S_RATIO = 8
7166 09:31:20.818585 ===================================
7167 09:31:20.821638 CA_P2S_RATIO = 8
7168 09:31:20.821724 DQ_CA_OPEN = 0
7169 09:31:20.825256 DQ_SEMI_OPEN = 0
7170 09:31:20.828383 CA_SEMI_OPEN = 0
7171 09:31:20.831996 CA_FULL_RATE = 0
7172 09:31:20.835072 DQ_CKDIV4_EN = 0
7173 09:31:20.835162 CA_CKDIV4_EN = 0
7174 09:31:20.838388 CA_PREDIV_EN = 0
7175 09:31:20.841921 PH8_DLY = 12
7176 09:31:20.845040 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7177 09:31:20.848503 DQ_AAMCK_DIV = 4
7178 09:31:20.851524 CA_AAMCK_DIV = 4
7179 09:31:20.855127 CA_ADMCK_DIV = 4
7180 09:31:20.855256 DQ_TRACK_CA_EN = 0
7181 09:31:20.858183 CA_PICK = 1600
7182 09:31:20.861752 CA_MCKIO = 1600
7183 09:31:20.864942 MCKIO_SEMI = 0
7184 09:31:20.868453 PLL_FREQ = 3068
7185 09:31:20.871550 DQ_UI_PI_RATIO = 32
7186 09:31:20.875038 CA_UI_PI_RATIO = 0
7187 09:31:20.878050 ===================================
7188 09:31:20.881390 ===================================
7189 09:31:20.881479 memory_type:LPDDR4
7190 09:31:20.884823 GP_NUM : 10
7191 09:31:20.888265 SRAM_EN : 1
7192 09:31:20.888354 MD32_EN : 0
7193 09:31:20.891714 ===================================
7194 09:31:20.894730 [ANA_INIT] >>>>>>>>>>>>>>
7195 09:31:20.898306 <<<<<< [CONFIGURE PHASE]: ANA_TX
7196 09:31:20.901322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7197 09:31:20.904435 ===================================
7198 09:31:20.908190 data_rate = 3200,PCW = 0X7600
7199 09:31:20.911316 ===================================
7200 09:31:20.914839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7201 09:31:20.917961 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7202 09:31:20.924710 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7203 09:31:20.928330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7204 09:31:20.931318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7205 09:31:20.934881 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7206 09:31:20.937994 [ANA_INIT] flow start
7207 09:31:20.941506 [ANA_INIT] PLL >>>>>>>>
7208 09:31:20.941609 [ANA_INIT] PLL <<<<<<<<
7209 09:31:20.944843 [ANA_INIT] MIDPI >>>>>>>>
7210 09:31:20.947979 [ANA_INIT] MIDPI <<<<<<<<
7211 09:31:20.948087 [ANA_INIT] DLL >>>>>>>>
7212 09:31:20.951156 [ANA_INIT] DLL <<<<<<<<
7213 09:31:20.954734 [ANA_INIT] flow end
7214 09:31:20.957925 ============ LP4 DIFF to SE enter ============
7215 09:31:20.961539 ============ LP4 DIFF to SE exit ============
7216 09:31:20.964544 [ANA_INIT] <<<<<<<<<<<<<
7217 09:31:20.968259 [Flow] Enable top DCM control >>>>>
7218 09:31:20.971365 [Flow] Enable top DCM control <<<<<
7219 09:31:20.974467 Enable DLL master slave shuffle
7220 09:31:20.978057 ==============================================================
7221 09:31:20.981437 Gating Mode config
7222 09:31:20.988076 ==============================================================
7223 09:31:20.988265 Config description:
7224 09:31:20.998145 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7225 09:31:21.004818 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7226 09:31:21.007834 SELPH_MODE 0: By rank 1: By Phase
7227 09:31:21.014633 ==============================================================
7228 09:31:21.017621 GAT_TRACK_EN = 1
7229 09:31:21.021238 RX_GATING_MODE = 2
7230 09:31:21.024322 RX_GATING_TRACK_MODE = 2
7231 09:31:21.027892 SELPH_MODE = 1
7232 09:31:21.031064 PICG_EARLY_EN = 1
7233 09:31:21.034463 VALID_LAT_VALUE = 1
7234 09:31:21.037739 ==============================================================
7235 09:31:21.040903 Enter into Gating configuration >>>>
7236 09:31:21.044399 Exit from Gating configuration <<<<
7237 09:31:21.047755 Enter into DVFS_PRE_config >>>>>
7238 09:31:21.061174 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7239 09:31:21.061326 Exit from DVFS_PRE_config <<<<<
7240 09:31:21.064257 Enter into PICG configuration >>>>
7241 09:31:21.067774 Exit from PICG configuration <<<<
7242 09:31:21.070939 [RX_INPUT] configuration >>>>>
7243 09:31:21.074474 [RX_INPUT] configuration <<<<<
7244 09:31:21.081188 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7245 09:31:21.084128 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7246 09:31:21.091089 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7247 09:31:21.097780 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7248 09:31:21.104107 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7249 09:31:21.110657 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7250 09:31:21.114268 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7251 09:31:21.117378 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7252 09:31:21.121029 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7253 09:31:21.127232 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7254 09:31:21.130877 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7255 09:31:21.134091 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7256 09:31:21.137502 ===================================
7257 09:31:21.140615 LPDDR4 DRAM CONFIGURATION
7258 09:31:21.143813 ===================================
7259 09:31:21.143906 EX_ROW_EN[0] = 0x0
7260 09:31:21.147495 EX_ROW_EN[1] = 0x0
7261 09:31:21.150536 LP4Y_EN = 0x0
7262 09:31:21.150623 WORK_FSP = 0x1
7263 09:31:21.153986 WL = 0x5
7264 09:31:21.154071 RL = 0x5
7265 09:31:21.156966 BL = 0x2
7266 09:31:21.157051 RPST = 0x0
7267 09:31:21.160620 RD_PRE = 0x0
7268 09:31:21.160707 WR_PRE = 0x1
7269 09:31:21.163687 WR_PST = 0x1
7270 09:31:21.163773 DBI_WR = 0x0
7271 09:31:21.167266 DBI_RD = 0x0
7272 09:31:21.167352 OTF = 0x1
7273 09:31:21.170317 ===================================
7274 09:31:21.173917 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7275 09:31:21.180169 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7276 09:31:21.183808 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7277 09:31:21.186896 ===================================
7278 09:31:21.190454 LPDDR4 DRAM CONFIGURATION
7279 09:31:21.193339 ===================================
7280 09:31:21.193425 EX_ROW_EN[0] = 0x10
7281 09:31:21.197122 EX_ROW_EN[1] = 0x0
7282 09:31:21.200310 LP4Y_EN = 0x0
7283 09:31:21.200395 WORK_FSP = 0x1
7284 09:31:21.203715 WL = 0x5
7285 09:31:21.203800 RL = 0x5
7286 09:31:21.207163 BL = 0x2
7287 09:31:21.207248 RPST = 0x0
7288 09:31:21.210159 RD_PRE = 0x0
7289 09:31:21.210249 WR_PRE = 0x1
7290 09:31:21.213758 WR_PST = 0x1
7291 09:31:21.213870 DBI_WR = 0x0
7292 09:31:21.216828 DBI_RD = 0x0
7293 09:31:21.216909 OTF = 0x1
7294 09:31:21.219936 ===================================
7295 09:31:21.226654 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7296 09:31:21.226738 ==
7297 09:31:21.230293 Dram Type= 6, Freq= 0, CH_0, rank 0
7298 09:31:21.233467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7299 09:31:21.236486 ==
7300 09:31:21.236616 [Duty_Offset_Calibration]
7301 09:31:21.240120 B0:2 B1:0 CA:1
7302 09:31:21.240200
7303 09:31:21.243193 [DutyScan_Calibration_Flow] k_type=0
7304 09:31:21.251401
7305 09:31:21.251485 ==CLK 0==
7306 09:31:21.254822 Final CLK duty delay cell = -4
7307 09:31:21.258064 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7308 09:31:21.261540 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7309 09:31:21.264681 [-4] AVG Duty = 4906%(X100)
7310 09:31:21.264765
7311 09:31:21.268269 CH0 CLK Duty spec in!! Max-Min= 187%
7312 09:31:21.271326 [DutyScan_Calibration_Flow] ====Done====
7313 09:31:21.271409
7314 09:31:21.274345 [DutyScan_Calibration_Flow] k_type=1
7315 09:31:21.290676
7316 09:31:21.290817 ==DQS 0 ==
7317 09:31:21.294308 Final DQS duty delay cell = 0
7318 09:31:21.297837 [0] MAX Duty = 5218%(X100), DQS PI = 28
7319 09:31:21.300505 [0] MIN Duty = 4938%(X100), DQS PI = 60
7320 09:31:21.304121 [0] AVG Duty = 5078%(X100)
7321 09:31:21.304233
7322 09:31:21.304361 ==DQS 1 ==
7323 09:31:21.307138 Final DQS duty delay cell = -4
7324 09:31:21.310716 [-4] MAX Duty = 5094%(X100), DQS PI = 28
7325 09:31:21.313959 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7326 09:31:21.316943 [-4] AVG Duty = 4969%(X100)
7327 09:31:21.317047
7328 09:31:21.320484 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7329 09:31:21.320618
7330 09:31:21.324230 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7331 09:31:21.327302 [DutyScan_Calibration_Flow] ====Done====
7332 09:31:21.327404
7333 09:31:21.330404 [DutyScan_Calibration_Flow] k_type=3
7334 09:31:21.348467
7335 09:31:21.348635 ==DQM 0 ==
7336 09:31:21.351594 Final DQM duty delay cell = 0
7337 09:31:21.354659 [0] MAX Duty = 5062%(X100), DQS PI = 24
7338 09:31:21.358231 [0] MIN Duty = 4813%(X100), DQS PI = 50
7339 09:31:21.361752 [0] AVG Duty = 4937%(X100)
7340 09:31:21.361838
7341 09:31:21.361938 ==DQM 1 ==
7342 09:31:21.364691 Final DQM duty delay cell = 0
7343 09:31:21.368079 [0] MAX Duty = 5249%(X100), DQS PI = 30
7344 09:31:21.371221 [0] MIN Duty = 5000%(X100), DQS PI = 20
7345 09:31:21.374800 [0] AVG Duty = 5124%(X100)
7346 09:31:21.374886
7347 09:31:21.378567 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7348 09:31:21.378652
7349 09:31:21.381393 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7350 09:31:21.384501 [DutyScan_Calibration_Flow] ====Done====
7351 09:31:21.384631
7352 09:31:21.388092 [DutyScan_Calibration_Flow] k_type=2
7353 09:31:21.405485
7354 09:31:21.405620 ==DQ 0 ==
7355 09:31:21.408966 Final DQ duty delay cell = 0
7356 09:31:21.412191 [0] MAX Duty = 5124%(X100), DQS PI = 34
7357 09:31:21.415483 [0] MIN Duty = 4969%(X100), DQS PI = 16
7358 09:31:21.415570 [0] AVG Duty = 5046%(X100)
7359 09:31:21.418599
7360 09:31:21.418683 ==DQ 1 ==
7361 09:31:21.422099 Final DQ duty delay cell = 0
7362 09:31:21.425235 [0] MAX Duty = 4969%(X100), DQS PI = 44
7363 09:31:21.428903 [0] MIN Duty = 4875%(X100), DQS PI = 0
7364 09:31:21.428992 [0] AVG Duty = 4922%(X100)
7365 09:31:21.429057
7366 09:31:21.432080 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7367 09:31:21.435502
7368 09:31:21.438472 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7369 09:31:21.442125 [DutyScan_Calibration_Flow] ====Done====
7370 09:31:21.442216 ==
7371 09:31:21.445169 Dram Type= 6, Freq= 0, CH_1, rank 0
7372 09:31:21.448614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7373 09:31:21.448699 ==
7374 09:31:21.451760 [Duty_Offset_Calibration]
7375 09:31:21.451840 B0:0 B1:-1 CA:2
7376 09:31:21.451904
7377 09:31:21.455366 [DutyScan_Calibration_Flow] k_type=0
7378 09:31:21.465617
7379 09:31:21.465734 ==CLK 0==
7380 09:31:21.468973 Final CLK duty delay cell = 0
7381 09:31:21.472294 [0] MAX Duty = 5156%(X100), DQS PI = 10
7382 09:31:21.475438 [0] MIN Duty = 4906%(X100), DQS PI = 44
7383 09:31:21.475527 [0] AVG Duty = 5031%(X100)
7384 09:31:21.479099
7385 09:31:21.482179 CH1 CLK Duty spec in!! Max-Min= 250%
7386 09:31:21.485614 [DutyScan_Calibration_Flow] ====Done====
7387 09:31:21.485699
7388 09:31:21.488609 [DutyScan_Calibration_Flow] k_type=1
7389 09:31:21.505518
7390 09:31:21.505661 ==DQS 0 ==
7391 09:31:21.508497 Final DQS duty delay cell = 0
7392 09:31:21.512022 [0] MAX Duty = 5093%(X100), DQS PI = 26
7393 09:31:21.515426 [0] MIN Duty = 4969%(X100), DQS PI = 18
7394 09:31:21.518706 [0] AVG Duty = 5031%(X100)
7395 09:31:21.518791
7396 09:31:21.518856 ==DQS 1 ==
7397 09:31:21.521995 Final DQS duty delay cell = 0
7398 09:31:21.525395 [0] MAX Duty = 5156%(X100), DQS PI = 0
7399 09:31:21.528891 [0] MIN Duty = 4844%(X100), DQS PI = 32
7400 09:31:21.531811 [0] AVG Duty = 5000%(X100)
7401 09:31:21.531921
7402 09:31:21.535084 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7403 09:31:21.535197
7404 09:31:21.538583 CH1 DQS 1 Duty spec in!! Max-Min= 312%
7405 09:31:21.541838 [DutyScan_Calibration_Flow] ====Done====
7406 09:31:21.541928
7407 09:31:21.545460 [DutyScan_Calibration_Flow] k_type=3
7408 09:31:21.562982
7409 09:31:21.563119 ==DQM 0 ==
7410 09:31:21.566552 Final DQM duty delay cell = 4
7411 09:31:21.569528 [4] MAX Duty = 5125%(X100), DQS PI = 8
7412 09:31:21.573124 [4] MIN Duty = 4969%(X100), DQS PI = 32
7413 09:31:21.573199 [4] AVG Duty = 5047%(X100)
7414 09:31:21.576473
7415 09:31:21.576552 ==DQM 1 ==
7416 09:31:21.579542 Final DQM duty delay cell = 0
7417 09:31:21.582661 [0] MAX Duty = 5281%(X100), DQS PI = 60
7418 09:31:21.586313 [0] MIN Duty = 4876%(X100), DQS PI = 34
7419 09:31:21.589495 [0] AVG Duty = 5078%(X100)
7420 09:31:21.589574
7421 09:31:21.592510 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7422 09:31:21.592624
7423 09:31:21.596041 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7424 09:31:21.599669 [DutyScan_Calibration_Flow] ====Done====
7425 09:31:21.599754
7426 09:31:21.602607 [DutyScan_Calibration_Flow] k_type=2
7427 09:31:21.620175
7428 09:31:21.620326 ==DQ 0 ==
7429 09:31:21.623078 Final DQ duty delay cell = 0
7430 09:31:21.626655 [0] MAX Duty = 5062%(X100), DQS PI = 18
7431 09:31:21.630116 [0] MIN Duty = 4969%(X100), DQS PI = 0
7432 09:31:21.630206 [0] AVG Duty = 5015%(X100)
7433 09:31:21.630273
7434 09:31:21.633015 ==DQ 1 ==
7435 09:31:21.636367 Final DQ duty delay cell = 0
7436 09:31:21.639923 [0] MAX Duty = 5062%(X100), DQS PI = 2
7437 09:31:21.643156 [0] MIN Duty = 4844%(X100), DQS PI = 32
7438 09:31:21.643286 [0] AVG Duty = 4953%(X100)
7439 09:31:21.643382
7440 09:31:21.646711 CH1 DQ 0 Duty spec in!! Max-Min= 93%
7441 09:31:21.646799
7442 09:31:21.649647 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7443 09:31:21.656318 [DutyScan_Calibration_Flow] ====Done====
7444 09:31:21.660118 nWR fixed to 30
7445 09:31:21.660234 [ModeRegInit_LP4] CH0 RK0
7446 09:31:21.663024 [ModeRegInit_LP4] CH0 RK1
7447 09:31:21.666613 [ModeRegInit_LP4] CH1 RK0
7448 09:31:21.666700 [ModeRegInit_LP4] CH1 RK1
7449 09:31:21.669796 match AC timing 5
7450 09:31:21.673286 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7451 09:31:21.676522 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7452 09:31:21.683380 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7453 09:31:21.686513 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7454 09:31:21.693216 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7455 09:31:21.693357 [MiockJmeterHQA]
7456 09:31:21.693519
7457 09:31:21.696379 [DramcMiockJmeter] u1RxGatingPI = 0
7458 09:31:21.699875 0 : 4252, 4027
7459 09:31:21.699976 4 : 4252, 4027
7460 09:31:21.700076 8 : 4252, 4027
7461 09:31:21.702903 12 : 4253, 4027
7462 09:31:21.703035 16 : 4252, 4027
7463 09:31:21.706537 20 : 4363, 4137
7464 09:31:21.706616 24 : 4252, 4027
7465 09:31:21.709629 28 : 4252, 4027
7466 09:31:21.709714 32 : 4253, 4026
7467 09:31:21.709838 36 : 4255, 4030
7468 09:31:21.713245 40 : 4252, 4027
7469 09:31:21.713330 44 : 4361, 4137
7470 09:31:21.716305 48 : 4363, 4138
7471 09:31:21.716390 52 : 4250, 4026
7472 09:31:21.719937 56 : 4252, 4027
7473 09:31:21.720084 60 : 4252, 4030
7474 09:31:21.722811 64 : 4250, 4026
7475 09:31:21.722923 68 : 4252, 4030
7476 09:31:21.723050 72 : 4361, 4137
7477 09:31:21.726445 76 : 4250, 4027
7478 09:31:21.726547 80 : 4250, 4027
7479 09:31:21.729614 84 : 4252, 4029
7480 09:31:21.729687 88 : 4252, 3821
7481 09:31:21.733135 92 : 4250, 0
7482 09:31:21.733211 96 : 4250, 0
7483 09:31:21.733272 100 : 4250, 0
7484 09:31:21.736229 104 : 4250, 0
7485 09:31:21.736320 108 : 4360, 0
7486 09:31:21.736394 112 : 4249, 0
7487 09:31:21.739777 116 : 4360, 0
7488 09:31:21.739868 120 : 4361, 0
7489 09:31:21.742808 124 : 4363, 0
7490 09:31:21.742895 128 : 4253, 0
7491 09:31:21.742964 132 : 4252, 0
7492 09:31:21.746424 136 : 4250, 0
7493 09:31:21.746511 140 : 4252, 0
7494 09:31:21.749419 144 : 4252, 0
7495 09:31:21.749507 148 : 4249, 0
7496 09:31:21.749576 152 : 4252, 0
7497 09:31:21.753197 156 : 4252, 0
7498 09:31:21.753284 160 : 4250, 0
7499 09:31:21.753353 164 : 4253, 0
7500 09:31:21.756219 168 : 4363, 0
7501 09:31:21.756306 172 : 4361, 0
7502 09:31:21.759853 176 : 4362, 0
7503 09:31:21.759940 180 : 4252, 0
7504 09:31:21.760009 184 : 4252, 0
7505 09:31:21.762971 188 : 4250, 0
7506 09:31:21.763058 192 : 4250, 0
7507 09:31:21.766115 196 : 4250, 0
7508 09:31:21.766202 200 : 4249, 6
7509 09:31:21.766271 204 : 4252, 2974
7510 09:31:21.769736 208 : 4250, 4027
7511 09:31:21.769823 212 : 4250, 4027
7512 09:31:21.772844 216 : 4361, 4137
7513 09:31:21.772931 220 : 4250, 4027
7514 09:31:21.776456 224 : 4250, 4027
7515 09:31:21.776577 228 : 4361, 4137
7516 09:31:21.779424 232 : 4250, 4026
7517 09:31:21.779511 236 : 4250, 4027
7518 09:31:21.782811 240 : 4363, 4140
7519 09:31:21.782926 244 : 4250, 4027
7520 09:31:21.786204 248 : 4250, 4026
7521 09:31:21.786326 252 : 4250, 4027
7522 09:31:21.789655 256 : 4252, 4030
7523 09:31:21.789769 260 : 4249, 4027
7524 09:31:21.789879 264 : 4250, 4026
7525 09:31:21.792753 268 : 4363, 4140
7526 09:31:21.792872 272 : 4250, 4027
7527 09:31:21.796464 276 : 4249, 4027
7528 09:31:21.796560 280 : 4361, 4137
7529 09:31:21.799531 284 : 4250, 4026
7530 09:31:21.799618 288 : 4250, 4027
7531 09:31:21.802999 292 : 4363, 4140
7532 09:31:21.803123 296 : 4249, 4027
7533 09:31:21.806043 300 : 4250, 4026
7534 09:31:21.806129 304 : 4250, 4027
7535 09:31:21.809536 308 : 4252, 4029
7536 09:31:21.809623 312 : 4249, 3915
7537 09:31:21.812789 316 : 4250, 2068
7538 09:31:21.812874
7539 09:31:21.812941 MIOCK jitter meter ch=0
7540 09:31:21.813003
7541 09:31:21.816409 1T = (316-92) = 224 dly cells
7542 09:31:21.822901 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7543 09:31:21.822991 ==
7544 09:31:21.825897 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 09:31:21.829603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 09:31:21.829689 ==
7547 09:31:21.836196 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7548 09:31:21.839251 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7549 09:31:21.842868 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7550 09:31:21.849383 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7551 09:31:21.858598 [CA 0] Center 43 (13~73) winsize 61
7552 09:31:21.862128 [CA 1] Center 43 (13~73) winsize 61
7553 09:31:21.865401 [CA 2] Center 38 (8~68) winsize 61
7554 09:31:21.868793 [CA 3] Center 37 (8~67) winsize 60
7555 09:31:21.871913 [CA 4] Center 36 (6~66) winsize 61
7556 09:31:21.875076 [CA 5] Center 35 (5~66) winsize 62
7557 09:31:21.875160
7558 09:31:21.878621 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7559 09:31:21.878704
7560 09:31:21.881625 [CATrainingPosCal] consider 1 rank data
7561 09:31:21.885438 u2DelayCellTimex100 = 290/100 ps
7562 09:31:21.888419 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7563 09:31:21.895172 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7564 09:31:21.898209 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7565 09:31:21.901802 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7566 09:31:21.905342 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7567 09:31:21.908351 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7568 09:31:21.908434
7569 09:31:21.911954 CA PerBit enable=1, Macro0, CA PI delay=35
7570 09:31:21.912038
7571 09:31:21.915111 [CBTSetCACLKResult] CA Dly = 35
7572 09:31:21.918642 CS Dly: 9 (0~40)
7573 09:31:21.921691 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7574 09:31:21.925206 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7575 09:31:21.925294 ==
7576 09:31:21.928231 Dram Type= 6, Freq= 0, CH_0, rank 1
7577 09:31:21.931841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 09:31:21.931927 ==
7579 09:31:21.938034 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7580 09:31:21.941473 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7581 09:31:21.948287 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7582 09:31:21.951666 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7583 09:31:21.961887 [CA 0] Center 43 (13~73) winsize 61
7584 09:31:21.964994 [CA 1] Center 43 (13~73) winsize 61
7585 09:31:21.968537 [CA 2] Center 37 (8~67) winsize 60
7586 09:31:21.971594 [CA 3] Center 38 (8~68) winsize 61
7587 09:31:21.975250 [CA 4] Center 36 (6~66) winsize 61
7588 09:31:21.978394 [CA 5] Center 36 (6~66) winsize 61
7589 09:31:21.978472
7590 09:31:21.981517 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7591 09:31:21.981617
7592 09:31:21.985161 [CATrainingPosCal] consider 2 rank data
7593 09:31:21.988459 u2DelayCellTimex100 = 290/100 ps
7594 09:31:21.991459 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7595 09:31:21.998312 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7596 09:31:22.001348 CA2 delay=37 (8~67),Diff = 1 PI (3 cell)
7597 09:31:22.004830 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
7598 09:31:22.008013 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7599 09:31:22.011564 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7600 09:31:22.011652
7601 09:31:22.014685 CA PerBit enable=1, Macro0, CA PI delay=36
7602 09:31:22.014772
7603 09:31:22.018282 [CBTSetCACLKResult] CA Dly = 36
7604 09:31:22.021340 CS Dly: 10 (0~43)
7605 09:31:22.024682 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7606 09:31:22.028282 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7607 09:31:22.028369
7608 09:31:22.031437 ----->DramcWriteLeveling(PI) begin...
7609 09:31:22.031525 ==
7610 09:31:22.034980 Dram Type= 6, Freq= 0, CH_0, rank 0
7611 09:31:22.038063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7612 09:31:22.041765 ==
7613 09:31:22.041897 Write leveling (Byte 0): 36 => 36
7614 09:31:22.045217 Write leveling (Byte 1): 28 => 28
7615 09:31:22.048199 DramcWriteLeveling(PI) end<-----
7616 09:31:22.048283
7617 09:31:22.048349 ==
7618 09:31:22.051685 Dram Type= 6, Freq= 0, CH_0, rank 0
7619 09:31:22.058207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7620 09:31:22.058290 ==
7621 09:31:22.058356 [Gating] SW mode calibration
7622 09:31:22.068406 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7623 09:31:22.071563 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7624 09:31:22.078278 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7625 09:31:22.081362 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7626 09:31:22.085027 1 4 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7627 09:31:22.091517 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7628 09:31:22.094522 1 4 16 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
7629 09:31:22.097926 1 4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7630 09:31:22.101402 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7631 09:31:22.108110 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7632 09:31:22.111149 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7633 09:31:22.117825 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7634 09:31:22.120918 1 5 8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
7635 09:31:22.124442 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7636 09:31:22.127538 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7637 09:31:22.134741 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
7638 09:31:22.137760 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 09:31:22.140845 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 09:31:22.147557 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 09:31:22.151122 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7642 09:31:22.154164 1 6 8 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7643 09:31:22.161089 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7644 09:31:22.164202 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7645 09:31:22.167726 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7646 09:31:22.174254 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 09:31:22.177596 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 09:31:22.180602 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 09:31:22.187451 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 09:31:22.190532 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7651 09:31:22.194065 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7652 09:31:22.200979 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7653 09:31:22.203824 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7654 09:31:22.207277 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7655 09:31:22.214177 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 09:31:22.217299 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 09:31:22.220879 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 09:31:22.227373 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 09:31:22.230321 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 09:31:22.233949 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 09:31:22.240223 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 09:31:22.243829 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 09:31:22.246955 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 09:31:22.253515 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 09:31:22.257118 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 09:31:22.260127 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 09:31:22.266798 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7668 09:31:22.270387 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7669 09:31:22.273429 Total UI for P1: 0, mck2ui 16
7670 09:31:22.276950 best dqsien dly found for B0: ( 1, 9, 12)
7671 09:31:22.280111 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7672 09:31:22.283739 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7673 09:31:22.286792 Total UI for P1: 0, mck2ui 16
7674 09:31:22.290458 best dqsien dly found for B1: ( 1, 9, 20)
7675 09:31:22.293687 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7676 09:31:22.300194 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7677 09:31:22.300319
7678 09:31:22.303680 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7679 09:31:22.307179 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7680 09:31:22.310078 [Gating] SW calibration Done
7681 09:31:22.310192 ==
7682 09:31:22.313368 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 09:31:22.316716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 09:31:22.316829 ==
7685 09:31:22.320255 RX Vref Scan: 0
7686 09:31:22.320366
7687 09:31:22.320463 RX Vref 0 -> 0, step: 1
7688 09:31:22.320594
7689 09:31:22.323468 RX Delay 0 -> 252, step: 8
7690 09:31:22.327082 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
7691 09:31:22.330133 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7692 09:31:22.336989 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7693 09:31:22.340419 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7694 09:31:22.343582 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7695 09:31:22.347091 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7696 09:31:22.350239 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7697 09:31:22.356972 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7698 09:31:22.360056 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7699 09:31:22.363672 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7700 09:31:22.366757 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7701 09:31:22.369853 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7702 09:31:22.376514 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7703 09:31:22.380308 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7704 09:31:22.383353 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7705 09:31:22.386523 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7706 09:31:22.386635 ==
7707 09:31:22.390178 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 09:31:22.393256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 09:31:22.396889 ==
7710 09:31:22.396998 DQS Delay:
7711 09:31:22.397093 DQS0 = 0, DQS1 = 0
7712 09:31:22.400027 DQM Delay:
7713 09:31:22.400135 DQM0 = 138, DQM1 = 126
7714 09:31:22.403124 DQ Delay:
7715 09:31:22.406510 DQ0 =139, DQ1 =139, DQ2 =135, DQ3 =135
7716 09:31:22.409933 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7717 09:31:22.413392 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7718 09:31:22.416449 DQ12 =131, DQ13 =127, DQ14 =139, DQ15 =135
7719 09:31:22.416582
7720 09:31:22.416697
7721 09:31:22.416795 ==
7722 09:31:22.419899 Dram Type= 6, Freq= 0, CH_0, rank 0
7723 09:31:22.423341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7724 09:31:22.423453 ==
7725 09:31:22.423549
7726 09:31:22.426524
7727 09:31:22.426629 TX Vref Scan disable
7728 09:31:22.430072 == TX Byte 0 ==
7729 09:31:22.433180 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7730 09:31:22.436658 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7731 09:31:22.440177 == TX Byte 1 ==
7732 09:31:22.443201 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7733 09:31:22.446698 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7734 09:31:22.446810 ==
7735 09:31:22.449976 Dram Type= 6, Freq= 0, CH_0, rank 0
7736 09:31:22.456644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7737 09:31:22.456757 ==
7738 09:31:22.468739
7739 09:31:22.472107 TX Vref early break, caculate TX vref
7740 09:31:22.475473 TX Vref=16, minBit 12, minWin=22, winSum=375
7741 09:31:22.479187 TX Vref=18, minBit 12, minWin=22, winSum=387
7742 09:31:22.482176 TX Vref=20, minBit 7, minWin=23, winSum=397
7743 09:31:22.485826 TX Vref=22, minBit 12, minWin=24, winSum=407
7744 09:31:22.488906 TX Vref=24, minBit 4, minWin=24, winSum=410
7745 09:31:22.495710 TX Vref=26, minBit 0, minWin=26, winSum=424
7746 09:31:22.498821 TX Vref=28, minBit 0, minWin=26, winSum=430
7747 09:31:22.502324 TX Vref=30, minBit 0, minWin=25, winSum=426
7748 09:31:22.505464 TX Vref=32, minBit 0, minWin=25, winSum=409
7749 09:31:22.508946 TX Vref=34, minBit 1, minWin=24, winSum=400
7750 09:31:22.515742 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
7751 09:31:22.515859
7752 09:31:22.518641 Final TX Range 0 Vref 28
7753 09:31:22.518751
7754 09:31:22.518850 ==
7755 09:31:22.522105 Dram Type= 6, Freq= 0, CH_0, rank 0
7756 09:31:22.525420 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7757 09:31:22.525532 ==
7758 09:31:22.525632
7759 09:31:22.525729
7760 09:31:22.529051 TX Vref Scan disable
7761 09:31:22.535295 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7762 09:31:22.535412 == TX Byte 0 ==
7763 09:31:22.538771 u2DelayCellOfst[0]=13 cells (4 PI)
7764 09:31:22.541961 u2DelayCellOfst[1]=20 cells (6 PI)
7765 09:31:22.545481 u2DelayCellOfst[2]=13 cells (4 PI)
7766 09:31:22.548637 u2DelayCellOfst[3]=13 cells (4 PI)
7767 09:31:22.552276 u2DelayCellOfst[4]=13 cells (4 PI)
7768 09:31:22.555387 u2DelayCellOfst[5]=0 cells (0 PI)
7769 09:31:22.559057 u2DelayCellOfst[6]=20 cells (6 PI)
7770 09:31:22.562152 u2DelayCellOfst[7]=16 cells (5 PI)
7771 09:31:22.565698 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7772 09:31:22.568563 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7773 09:31:22.572131 == TX Byte 1 ==
7774 09:31:22.572240 u2DelayCellOfst[8]=0 cells (0 PI)
7775 09:31:22.575540 u2DelayCellOfst[9]=0 cells (0 PI)
7776 09:31:22.579003 u2DelayCellOfst[10]=6 cells (2 PI)
7777 09:31:22.582088 u2DelayCellOfst[11]=3 cells (1 PI)
7778 09:31:22.585686 u2DelayCellOfst[12]=10 cells (3 PI)
7779 09:31:22.588785 u2DelayCellOfst[13]=10 cells (3 PI)
7780 09:31:22.591927 u2DelayCellOfst[14]=13 cells (4 PI)
7781 09:31:22.595601 u2DelayCellOfst[15]=10 cells (3 PI)
7782 09:31:22.598633 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7783 09:31:22.605747 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7784 09:31:22.605857 DramC Write-DBI on
7785 09:31:22.605963 ==
7786 09:31:22.608742 Dram Type= 6, Freq= 0, CH_0, rank 0
7787 09:31:22.611918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7788 09:31:22.615315 ==
7789 09:31:22.615420
7790 09:31:22.615515
7791 09:31:22.615605 TX Vref Scan disable
7792 09:31:22.618722 == TX Byte 0 ==
7793 09:31:22.622347 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7794 09:31:22.625310 == TX Byte 1 ==
7795 09:31:22.628823 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7796 09:31:22.632069 DramC Write-DBI off
7797 09:31:22.632188
7798 09:31:22.632313 [DATLAT]
7799 09:31:22.632439 Freq=1600, CH0 RK0
7800 09:31:22.632543
7801 09:31:22.635442 DATLAT Default: 0xf
7802 09:31:22.635550 0, 0xFFFF, sum = 0
7803 09:31:22.638440 1, 0xFFFF, sum = 0
7804 09:31:22.638549 2, 0xFFFF, sum = 0
7805 09:31:22.642083 3, 0xFFFF, sum = 0
7806 09:31:22.642191 4, 0xFFFF, sum = 0
7807 09:31:22.645827 5, 0xFFFF, sum = 0
7808 09:31:22.648717 6, 0xFFFF, sum = 0
7809 09:31:22.648828 7, 0xFFFF, sum = 0
7810 09:31:22.651866 8, 0xFFFF, sum = 0
7811 09:31:22.651977 9, 0xFFFF, sum = 0
7812 09:31:22.655471 10, 0xFFFF, sum = 0
7813 09:31:22.655584 11, 0xFFFF, sum = 0
7814 09:31:22.659130 12, 0xFFFF, sum = 0
7815 09:31:22.659260 13, 0xFFFF, sum = 0
7816 09:31:22.662125 14, 0x0, sum = 1
7817 09:31:22.662238 15, 0x0, sum = 2
7818 09:31:22.665741 16, 0x0, sum = 3
7819 09:31:22.665908 17, 0x0, sum = 4
7820 09:31:22.666037 best_step = 15
7821 09:31:22.668765
7822 09:31:22.668872 ==
7823 09:31:22.672309 Dram Type= 6, Freq= 0, CH_0, rank 0
7824 09:31:22.675600 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7825 09:31:22.675708 ==
7826 09:31:22.675801 RX Vref Scan: 1
7827 09:31:22.675891
7828 09:31:22.678752 Set Vref Range= 24 -> 127
7829 09:31:22.678948
7830 09:31:22.682216 RX Vref 24 -> 127, step: 1
7831 09:31:22.682321
7832 09:31:22.685912 RX Delay 19 -> 252, step: 4
7833 09:31:22.685995
7834 09:31:22.689090 Set Vref, RX VrefLevel [Byte0]: 24
7835 09:31:22.692096 [Byte1]: 24
7836 09:31:22.692204
7837 09:31:22.695546 Set Vref, RX VrefLevel [Byte0]: 25
7838 09:31:22.698817 [Byte1]: 25
7839 09:31:22.698899
7840 09:31:22.702333 Set Vref, RX VrefLevel [Byte0]: 26
7841 09:31:22.705482 [Byte1]: 26
7842 09:31:22.708964
7843 09:31:22.709046 Set Vref, RX VrefLevel [Byte0]: 27
7844 09:31:22.712653 [Byte1]: 27
7845 09:31:22.716746
7846 09:31:22.716829 Set Vref, RX VrefLevel [Byte0]: 28
7847 09:31:22.719630 [Byte1]: 28
7848 09:31:22.724166
7849 09:31:22.724249 Set Vref, RX VrefLevel [Byte0]: 29
7850 09:31:22.727611 [Byte1]: 29
7851 09:31:22.731525
7852 09:31:22.731621 Set Vref, RX VrefLevel [Byte0]: 30
7853 09:31:22.735092 [Byte1]: 30
7854 09:31:22.739018
7855 09:31:22.739142 Set Vref, RX VrefLevel [Byte0]: 31
7856 09:31:22.742595 [Byte1]: 31
7857 09:31:22.746810
7858 09:31:22.746894 Set Vref, RX VrefLevel [Byte0]: 32
7859 09:31:22.750474 [Byte1]: 32
7860 09:31:22.754606
7861 09:31:22.754688 Set Vref, RX VrefLevel [Byte0]: 33
7862 09:31:22.757736 [Byte1]: 33
7863 09:31:22.761836
7864 09:31:22.761918 Set Vref, RX VrefLevel [Byte0]: 34
7865 09:31:22.765460 [Byte1]: 34
7866 09:31:22.769524
7867 09:31:22.769609 Set Vref, RX VrefLevel [Byte0]: 35
7868 09:31:22.773072 [Byte1]: 35
7869 09:31:22.777019
7870 09:31:22.777103 Set Vref, RX VrefLevel [Byte0]: 36
7871 09:31:22.780458 [Byte1]: 36
7872 09:31:22.784658
7873 09:31:22.784744 Set Vref, RX VrefLevel [Byte0]: 37
7874 09:31:22.788065 [Byte1]: 37
7875 09:31:22.791946
7876 09:31:22.792050 Set Vref, RX VrefLevel [Byte0]: 38
7877 09:31:22.795518 [Byte1]: 38
7878 09:31:22.799714
7879 09:31:22.799798 Set Vref, RX VrefLevel [Byte0]: 39
7880 09:31:22.803390 [Byte1]: 39
7881 09:31:22.807486
7882 09:31:22.807568 Set Vref, RX VrefLevel [Byte0]: 40
7883 09:31:22.810552 [Byte1]: 40
7884 09:31:22.814795
7885 09:31:22.814878 Set Vref, RX VrefLevel [Byte0]: 41
7886 09:31:22.818331 [Byte1]: 41
7887 09:31:22.822372
7888 09:31:22.822454 Set Vref, RX VrefLevel [Byte0]: 42
7889 09:31:22.825784 [Byte1]: 42
7890 09:31:22.830139
7891 09:31:22.830221 Set Vref, RX VrefLevel [Byte0]: 43
7892 09:31:22.833508 [Byte1]: 43
7893 09:31:22.837930
7894 09:31:22.838038 Set Vref, RX VrefLevel [Byte0]: 44
7895 09:31:22.840847 [Byte1]: 44
7896 09:31:22.845081
7897 09:31:22.845164 Set Vref, RX VrefLevel [Byte0]: 45
7898 09:31:22.848690 [Byte1]: 45
7899 09:31:22.852735
7900 09:31:22.852845 Set Vref, RX VrefLevel [Byte0]: 46
7901 09:31:22.855851 [Byte1]: 46
7902 09:31:22.860570
7903 09:31:22.860666 Set Vref, RX VrefLevel [Byte0]: 47
7904 09:31:22.863816 [Byte1]: 47
7905 09:31:22.867887
7906 09:31:22.867996 Set Vref, RX VrefLevel [Byte0]: 48
7907 09:31:22.874773 [Byte1]: 48
7908 09:31:22.874854
7909 09:31:22.877750 Set Vref, RX VrefLevel [Byte0]: 49
7910 09:31:22.881224 [Byte1]: 49
7911 09:31:22.881300
7912 09:31:22.884311 Set Vref, RX VrefLevel [Byte0]: 50
7913 09:31:22.887781 [Byte1]: 50
7914 09:31:22.887860
7915 09:31:22.890797 Set Vref, RX VrefLevel [Byte0]: 51
7916 09:31:22.894202 [Byte1]: 51
7917 09:31:22.898414
7918 09:31:22.898493 Set Vref, RX VrefLevel [Byte0]: 52
7919 09:31:22.901530 [Byte1]: 52
7920 09:31:22.906091
7921 09:31:22.906175 Set Vref, RX VrefLevel [Byte0]: 53
7922 09:31:22.909123 [Byte1]: 53
7923 09:31:22.913342
7924 09:31:22.913427 Set Vref, RX VrefLevel [Byte0]: 54
7925 09:31:22.916866 [Byte1]: 54
7926 09:31:22.921030
7927 09:31:22.921117 Set Vref, RX VrefLevel [Byte0]: 55
7928 09:31:22.924038 [Byte1]: 55
7929 09:31:22.928487
7930 09:31:22.928622 Set Vref, RX VrefLevel [Byte0]: 56
7931 09:31:22.932040 [Byte1]: 56
7932 09:31:22.936262
7933 09:31:22.936344 Set Vref, RX VrefLevel [Byte0]: 57
7934 09:31:22.939209 [Byte1]: 57
7935 09:31:22.943720
7936 09:31:22.943832 Set Vref, RX VrefLevel [Byte0]: 58
7937 09:31:22.947024 [Byte1]: 58
7938 09:31:22.951199
7939 09:31:22.951281 Set Vref, RX VrefLevel [Byte0]: 59
7940 09:31:22.954720 [Byte1]: 59
7941 09:31:22.958741
7942 09:31:22.958837 Set Vref, RX VrefLevel [Byte0]: 60
7943 09:31:22.962365 [Byte1]: 60
7944 09:31:22.966495
7945 09:31:22.966577 Set Vref, RX VrefLevel [Byte0]: 61
7946 09:31:22.969596 [Byte1]: 61
7947 09:31:22.974139
7948 09:31:22.974221 Set Vref, RX VrefLevel [Byte0]: 62
7949 09:31:22.977202 [Byte1]: 62
7950 09:31:22.981744
7951 09:31:22.981823 Set Vref, RX VrefLevel [Byte0]: 63
7952 09:31:22.984821 [Byte1]: 63
7953 09:31:22.988890
7954 09:31:22.988965 Set Vref, RX VrefLevel [Byte0]: 64
7955 09:31:22.992401 [Byte1]: 64
7956 09:31:22.996838
7957 09:31:22.996913 Set Vref, RX VrefLevel [Byte0]: 65
7958 09:31:22.999802 [Byte1]: 65
7959 09:31:23.004324
7960 09:31:23.004399 Set Vref, RX VrefLevel [Byte0]: 66
7961 09:31:23.007481 [Byte1]: 66
7962 09:31:23.012026
7963 09:31:23.012104 Set Vref, RX VrefLevel [Byte0]: 67
7964 09:31:23.015062 [Byte1]: 67
7965 09:31:23.019667
7966 09:31:23.019738 Set Vref, RX VrefLevel [Byte0]: 68
7967 09:31:23.022852 [Byte1]: 68
7968 09:31:23.026953
7969 09:31:23.027038 Set Vref, RX VrefLevel [Byte0]: 69
7970 09:31:23.030118 [Byte1]: 69
7971 09:31:23.035011
7972 09:31:23.035097 Set Vref, RX VrefLevel [Byte0]: 70
7973 09:31:23.037868 [Byte1]: 70
7974 09:31:23.042191
7975 09:31:23.042280 Set Vref, RX VrefLevel [Byte0]: 71
7976 09:31:23.045500 [Byte1]: 71
7977 09:31:23.049621
7978 09:31:23.049707 Set Vref, RX VrefLevel [Byte0]: 72
7979 09:31:23.052985 [Byte1]: 72
7980 09:31:23.057200
7981 09:31:23.057286 Set Vref, RX VrefLevel [Byte0]: 73
7982 09:31:23.060833 [Byte1]: 73
7983 09:31:23.064886
7984 09:31:23.064971 Set Vref, RX VrefLevel [Byte0]: 74
7985 09:31:23.067992 [Byte1]: 74
7986 09:31:23.072645
7987 09:31:23.072731 Set Vref, RX VrefLevel [Byte0]: 75
7988 09:31:23.075721 [Byte1]: 75
7989 09:31:23.079827
7990 09:31:23.079913 Set Vref, RX VrefLevel [Byte0]: 76
7991 09:31:23.083284 [Byte1]: 76
7992 09:31:23.087828
7993 09:31:23.087915 Set Vref, RX VrefLevel [Byte0]: 77
7994 09:31:23.091006 [Byte1]: 77
7995 09:31:23.095091
7996 09:31:23.095177 Set Vref, RX VrefLevel [Byte0]: 78
7997 09:31:23.098561 [Byte1]: 78
7998 09:31:23.102870
7999 09:31:23.102956 Set Vref, RX VrefLevel [Byte0]: 79
8000 09:31:23.105784 [Byte1]: 79
8001 09:31:23.110464
8002 09:31:23.110556 Set Vref, RX VrefLevel [Byte0]: 80
8003 09:31:23.113516 [Byte1]: 80
8004 09:31:23.118235
8005 09:31:23.118346 Set Vref, RX VrefLevel [Byte0]: 81
8006 09:31:23.121233 [Byte1]: 81
8007 09:31:23.125291
8008 09:31:23.125376 Final RX Vref Byte 0 = 63 to rank0
8009 09:31:23.128920 Final RX Vref Byte 1 = 63 to rank0
8010 09:31:23.132048 Final RX Vref Byte 0 = 63 to rank1
8011 09:31:23.135516 Final RX Vref Byte 1 = 63 to rank1==
8012 09:31:23.138842 Dram Type= 6, Freq= 0, CH_0, rank 0
8013 09:31:23.145673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 09:31:23.145773 ==
8015 09:31:23.145842 DQS Delay:
8016 09:31:23.145904 DQS0 = 0, DQS1 = 0
8017 09:31:23.149369 DQM Delay:
8018 09:31:23.149452 DQM0 = 136, DQM1 = 124
8019 09:31:23.152032 DQ Delay:
8020 09:31:23.155354 DQ0 =136, DQ1 =136, DQ2 =132, DQ3 =134
8021 09:31:23.158755 DQ4 =138, DQ5 =124, DQ6 =144, DQ7 =144
8022 09:31:23.161893 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
8023 09:31:23.165549 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =132
8024 09:31:23.165633
8025 09:31:23.165699
8026 09:31:23.165760
8027 09:31:23.168678 [DramC_TX_OE_Calibration] TA2
8028 09:31:23.171695 Original DQ_B0 (3 6) =30, OEN = 27
8029 09:31:23.175360 Original DQ_B1 (3 6) =30, OEN = 27
8030 09:31:23.178616 24, 0x0, End_B0=24 End_B1=24
8031 09:31:23.178695 25, 0x0, End_B0=25 End_B1=25
8032 09:31:23.181678 26, 0x0, End_B0=26 End_B1=26
8033 09:31:23.185149 27, 0x0, End_B0=27 End_B1=27
8034 09:31:23.188695 28, 0x0, End_B0=28 End_B1=28
8035 09:31:23.188776 29, 0x0, End_B0=29 End_B1=29
8036 09:31:23.191852 30, 0x0, End_B0=30 End_B1=30
8037 09:31:23.195035 31, 0x4141, End_B0=30 End_B1=30
8038 09:31:23.198568 Byte0 end_step=30 best_step=27
8039 09:31:23.201664 Byte1 end_step=30 best_step=27
8040 09:31:23.205276 Byte0 TX OE(2T, 0.5T) = (3, 3)
8041 09:31:23.208263 Byte1 TX OE(2T, 0.5T) = (3, 3)
8042 09:31:23.208337
8043 09:31:23.208412
8044 09:31:23.215180 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
8045 09:31:23.218294 CH0 RK0: MR19=303, MR18=1D1B
8046 09:31:23.224856 CH0_RK0: MR19=0x303, MR18=0x1D1B, DQSOSC=395, MR23=63, INC=23, DEC=15
8047 09:31:23.224942
8048 09:31:23.228484 ----->DramcWriteLeveling(PI) begin...
8049 09:31:23.228611 ==
8050 09:31:23.231973 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 09:31:23.235133 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 09:31:23.235223 ==
8053 09:31:23.238165 Write leveling (Byte 0): 38 => 38
8054 09:31:23.241631 Write leveling (Byte 1): 28 => 28
8055 09:31:23.245128 DramcWriteLeveling(PI) end<-----
8056 09:31:23.245213
8057 09:31:23.245277 ==
8058 09:31:23.248455 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 09:31:23.251925 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 09:31:23.252008 ==
8061 09:31:23.255094 [Gating] SW mode calibration
8062 09:31:23.261475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8063 09:31:23.268140 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8064 09:31:23.271742 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 09:31:23.274711 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 09:31:23.281424 1 4 8 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8067 09:31:23.285022 1 4 12 | B1->B0 | 2828 3232 | 0 1 | (0 0) (1 1)
8068 09:31:23.288000 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8069 09:31:23.294971 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8070 09:31:23.298120 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 09:31:23.301704 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 09:31:23.307986 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 09:31:23.311557 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 09:31:23.314607 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8075 09:31:23.321420 1 5 12 | B1->B0 | 3434 2c2c | 0 0 | (0 1) (1 0)
8076 09:31:23.324910 1 5 16 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)
8077 09:31:23.327865 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8078 09:31:23.334585 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 09:31:23.337974 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 09:31:23.341213 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 09:31:23.347734 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 09:31:23.351046 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8083 09:31:23.354476 1 6 12 | B1->B0 | 2e2e 4545 | 1 0 | (0 0) (0 0)
8084 09:31:23.360999 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8085 09:31:23.364201 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8086 09:31:23.367683 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 09:31:23.374333 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 09:31:23.377923 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 09:31:23.381143 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 09:31:23.387788 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8091 09:31:23.390824 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8092 09:31:23.394539 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8093 09:31:23.400888 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8094 09:31:23.404413 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 09:31:23.407484 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 09:31:23.411125 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 09:31:23.417854 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 09:31:23.420849 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 09:31:23.424416 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 09:31:23.430919 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 09:31:23.434467 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 09:31:23.437579 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 09:31:23.444204 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 09:31:23.447357 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 09:31:23.450816 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 09:31:23.457663 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 09:31:23.460799 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8108 09:31:23.464134 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 09:31:23.467257 Total UI for P1: 0, mck2ui 16
8110 09:31:23.470844 best dqsien dly found for B0: ( 1, 9, 12)
8111 09:31:23.473929 Total UI for P1: 0, mck2ui 16
8112 09:31:23.477589 best dqsien dly found for B1: ( 1, 9, 12)
8113 09:31:23.480494 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8114 09:31:23.483681 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8115 09:31:23.483758
8116 09:31:23.490833 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8117 09:31:23.493996 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8118 09:31:23.497193 [Gating] SW calibration Done
8119 09:31:23.497277 ==
8120 09:31:23.500766 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 09:31:23.503776 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 09:31:23.503867 ==
8123 09:31:23.503935 RX Vref Scan: 0
8124 09:31:23.503995
8125 09:31:23.507483 RX Vref 0 -> 0, step: 1
8126 09:31:23.507570
8127 09:31:23.510533 RX Delay 0 -> 252, step: 8
8128 09:31:23.513591 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8129 09:31:23.517231 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8130 09:31:23.523949 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8131 09:31:23.527218 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8132 09:31:23.530299 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8133 09:31:23.534070 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
8134 09:31:23.536863 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8135 09:31:23.540565 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8136 09:31:23.547289 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8137 09:31:23.550582 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8138 09:31:23.553514 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8139 09:31:23.556901 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8140 09:31:23.563788 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8141 09:31:23.566768 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8142 09:31:23.570213 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8143 09:31:23.573681 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8144 09:31:23.573764 ==
8145 09:31:23.576765 Dram Type= 6, Freq= 0, CH_0, rank 1
8146 09:31:23.583619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8147 09:31:23.583704 ==
8148 09:31:23.583770 DQS Delay:
8149 09:31:23.583830 DQS0 = 0, DQS1 = 0
8150 09:31:23.586723 DQM Delay:
8151 09:31:23.586805 DQM0 = 136, DQM1 = 124
8152 09:31:23.590326 DQ Delay:
8153 09:31:23.593371 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8154 09:31:23.596921 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
8155 09:31:23.600098 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =123
8156 09:31:23.603559 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8157 09:31:23.603643
8158 09:31:23.603718
8159 09:31:23.603779 ==
8160 09:31:23.607204 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 09:31:23.610138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 09:31:23.610222 ==
8163 09:31:23.610287
8164 09:31:23.613578
8165 09:31:23.613660 TX Vref Scan disable
8166 09:31:23.616726 == TX Byte 0 ==
8167 09:31:23.620279 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8168 09:31:23.623416 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8169 09:31:23.626970 == TX Byte 1 ==
8170 09:31:23.630188 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8171 09:31:23.633784 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8172 09:31:23.633873 ==
8173 09:31:23.636863 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 09:31:23.643283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 09:31:23.643392 ==
8176 09:31:23.657620
8177 09:31:23.660797 TX Vref early break, caculate TX vref
8178 09:31:23.664256 TX Vref=16, minBit 0, minWin=23, winSum=389
8179 09:31:23.667581 TX Vref=18, minBit 0, minWin=24, winSum=396
8180 09:31:23.671035 TX Vref=20, minBit 8, minWin=24, winSum=404
8181 09:31:23.674017 TX Vref=22, minBit 8, minWin=24, winSum=409
8182 09:31:23.677464 TX Vref=24, minBit 0, minWin=25, winSum=421
8183 09:31:23.684149 TX Vref=26, minBit 1, minWin=25, winSum=428
8184 09:31:23.687365 TX Vref=28, minBit 0, minWin=26, winSum=430
8185 09:31:23.690966 TX Vref=30, minBit 0, minWin=25, winSum=426
8186 09:31:23.694034 TX Vref=32, minBit 0, minWin=26, winSum=420
8187 09:31:23.697413 TX Vref=34, minBit 0, minWin=25, winSum=409
8188 09:31:23.700986 TX Vref=36, minBit 2, minWin=24, winSum=402
8189 09:31:23.707639 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8190 09:31:23.707728
8191 09:31:23.710535 Final TX Range 0 Vref 28
8192 09:31:23.710637
8193 09:31:23.710737 ==
8194 09:31:23.714318 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 09:31:23.717258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 09:31:23.717388 ==
8197 09:31:23.717483
8198 09:31:23.717574
8199 09:31:23.720968 TX Vref Scan disable
8200 09:31:23.727567 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8201 09:31:23.727659 == TX Byte 0 ==
8202 09:31:23.730659 u2DelayCellOfst[0]=13 cells (4 PI)
8203 09:31:23.734177 u2DelayCellOfst[1]=20 cells (6 PI)
8204 09:31:23.737069 u2DelayCellOfst[2]=13 cells (4 PI)
8205 09:31:23.740761 u2DelayCellOfst[3]=13 cells (4 PI)
8206 09:31:23.743855 u2DelayCellOfst[4]=10 cells (3 PI)
8207 09:31:23.747361 u2DelayCellOfst[5]=0 cells (0 PI)
8208 09:31:23.750683 u2DelayCellOfst[6]=20 cells (6 PI)
8209 09:31:23.754122 u2DelayCellOfst[7]=20 cells (6 PI)
8210 09:31:23.757170 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8211 09:31:23.760728 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8212 09:31:23.763871 == TX Byte 1 ==
8213 09:31:23.767361 u2DelayCellOfst[8]=0 cells (0 PI)
8214 09:31:23.767445 u2DelayCellOfst[9]=3 cells (1 PI)
8215 09:31:23.770565 u2DelayCellOfst[10]=6 cells (2 PI)
8216 09:31:23.774087 u2DelayCellOfst[11]=3 cells (1 PI)
8217 09:31:23.777502 u2DelayCellOfst[12]=13 cells (4 PI)
8218 09:31:23.780907 u2DelayCellOfst[13]=13 cells (4 PI)
8219 09:31:23.783964 u2DelayCellOfst[14]=13 cells (4 PI)
8220 09:31:23.787093 u2DelayCellOfst[15]=10 cells (3 PI)
8221 09:31:23.790730 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8222 09:31:23.797341 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8223 09:31:23.797458 DramC Write-DBI on
8224 09:31:23.797540 ==
8225 09:31:23.800282 Dram Type= 6, Freq= 0, CH_0, rank 1
8226 09:31:23.807122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8227 09:31:23.807216 ==
8228 09:31:23.807303
8229 09:31:23.807383
8230 09:31:23.807463 TX Vref Scan disable
8231 09:31:23.811147 == TX Byte 0 ==
8232 09:31:23.814195 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8233 09:31:23.817758 == TX Byte 1 ==
8234 09:31:23.820882 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8235 09:31:23.824374 DramC Write-DBI off
8236 09:31:23.824462
8237 09:31:23.824592 [DATLAT]
8238 09:31:23.824688 Freq=1600, CH0 RK1
8239 09:31:23.824768
8240 09:31:23.827489 DATLAT Default: 0xf
8241 09:31:23.827590 0, 0xFFFF, sum = 0
8242 09:31:23.831020 1, 0xFFFF, sum = 0
8243 09:31:23.834033 2, 0xFFFF, sum = 0
8244 09:31:23.834121 3, 0xFFFF, sum = 0
8245 09:31:23.837765 4, 0xFFFF, sum = 0
8246 09:31:23.837853 5, 0xFFFF, sum = 0
8247 09:31:23.840520 6, 0xFFFF, sum = 0
8248 09:31:23.840675 7, 0xFFFF, sum = 0
8249 09:31:23.844207 8, 0xFFFF, sum = 0
8250 09:31:23.844293 9, 0xFFFF, sum = 0
8251 09:31:23.847296 10, 0xFFFF, sum = 0
8252 09:31:23.847373 11, 0xFFFF, sum = 0
8253 09:31:23.850798 12, 0xFFFF, sum = 0
8254 09:31:23.850873 13, 0xFFFF, sum = 0
8255 09:31:23.854044 14, 0x0, sum = 1
8256 09:31:23.854157 15, 0x0, sum = 2
8257 09:31:23.857369 16, 0x0, sum = 3
8258 09:31:23.857453 17, 0x0, sum = 4
8259 09:31:23.860309 best_step = 15
8260 09:31:23.860399
8261 09:31:23.860497 ==
8262 09:31:23.863818 Dram Type= 6, Freq= 0, CH_0, rank 1
8263 09:31:23.867424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 09:31:23.867508 ==
8265 09:31:23.870517 RX Vref Scan: 0
8266 09:31:23.870601
8267 09:31:23.870666 RX Vref 0 -> 0, step: 1
8268 09:31:23.870727
8269 09:31:23.874035 RX Delay 11 -> 252, step: 4
8270 09:31:23.880314 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8271 09:31:23.883941 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8272 09:31:23.887143 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8273 09:31:23.890216 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8274 09:31:23.893876 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8275 09:31:23.897126 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8276 09:31:23.903735 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8277 09:31:23.906764 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8278 09:31:23.910447 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8279 09:31:23.913944 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8280 09:31:23.917096 iDelay=191, Bit 10, Center 126 (79 ~ 174) 96
8281 09:31:23.923888 iDelay=191, Bit 11, Center 118 (71 ~ 166) 96
8282 09:31:23.927039 iDelay=191, Bit 12, Center 128 (79 ~ 178) 100
8283 09:31:23.930123 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8284 09:31:23.933659 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8285 09:31:23.936816 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8286 09:31:23.940449 ==
8287 09:31:23.943465 Dram Type= 6, Freq= 0, CH_0, rank 1
8288 09:31:23.947065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8289 09:31:23.947180 ==
8290 09:31:23.947282 DQS Delay:
8291 09:31:23.950127 DQS0 = 0, DQS1 = 0
8292 09:31:23.950210 DQM Delay:
8293 09:31:23.953687 DQM0 = 133, DQM1 = 123
8294 09:31:23.953771 DQ Delay:
8295 09:31:23.956739 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8296 09:31:23.960301 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =138
8297 09:31:23.963192 DQ8 =116, DQ9 =110, DQ10 =126, DQ11 =118
8298 09:31:23.966766 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =128
8299 09:31:23.966851
8300 09:31:23.966956
8301 09:31:23.967020
8302 09:31:23.970002 [DramC_TX_OE_Calibration] TA2
8303 09:31:23.973415 Original DQ_B0 (3 6) =30, OEN = 27
8304 09:31:23.976581 Original DQ_B1 (3 6) =30, OEN = 27
8305 09:31:23.979848 24, 0x0, End_B0=24 End_B1=24
8306 09:31:23.983349 25, 0x0, End_B0=25 End_B1=25
8307 09:31:23.983435 26, 0x0, End_B0=26 End_B1=26
8308 09:31:23.986726 27, 0x0, End_B0=27 End_B1=27
8309 09:31:23.989828 28, 0x0, End_B0=28 End_B1=28
8310 09:31:23.993842 29, 0x0, End_B0=29 End_B1=29
8311 09:31:23.993956 30, 0x0, End_B0=30 End_B1=30
8312 09:31:23.996991 31, 0x4545, End_B0=30 End_B1=30
8313 09:31:23.999963 Byte0 end_step=30 best_step=27
8314 09:31:24.003506 Byte1 end_step=30 best_step=27
8315 09:31:24.006549 Byte0 TX OE(2T, 0.5T) = (3, 3)
8316 09:31:24.010153 Byte1 TX OE(2T, 0.5T) = (3, 3)
8317 09:31:24.010240
8318 09:31:24.010307
8319 09:31:24.016740 [DQSOSCAuto] RK1, (LSB)MR18= 0x230f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8320 09:31:24.019943 CH0 RK1: MR19=303, MR18=230F
8321 09:31:24.026766 CH0_RK1: MR19=0x303, MR18=0x230F, DQSOSC=392, MR23=63, INC=24, DEC=16
8322 09:31:24.029840 [RxdqsGatingPostProcess] freq 1600
8323 09:31:24.036460 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8324 09:31:24.036594 best DQS0 dly(2T, 0.5T) = (1, 1)
8325 09:31:24.040139 best DQS1 dly(2T, 0.5T) = (1, 1)
8326 09:31:24.043265 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8327 09:31:24.046447 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8328 09:31:24.049868 best DQS0 dly(2T, 0.5T) = (1, 1)
8329 09:31:24.052965 best DQS1 dly(2T, 0.5T) = (1, 1)
8330 09:31:24.056696 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8331 09:31:24.059556 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8332 09:31:24.063099 Pre-setting of DQS Precalculation
8333 09:31:24.066467 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8334 09:31:24.066594 ==
8335 09:31:24.069495 Dram Type= 6, Freq= 0, CH_1, rank 0
8336 09:31:24.076378 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8337 09:31:24.076465 ==
8338 09:31:24.079411 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8339 09:31:24.086135 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8340 09:31:24.089456 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8341 09:31:24.095872 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8342 09:31:24.104063 [CA 0] Center 42 (12~72) winsize 61
8343 09:31:24.107112 [CA 1] Center 42 (12~72) winsize 61
8344 09:31:24.110698 [CA 2] Center 38 (9~68) winsize 60
8345 09:31:24.113768 [CA 3] Center 37 (8~67) winsize 60
8346 09:31:24.117363 [CA 4] Center 37 (8~67) winsize 60
8347 09:31:24.120430 [CA 5] Center 37 (7~67) winsize 61
8348 09:31:24.120513
8349 09:31:24.123567 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8350 09:31:24.123650
8351 09:31:24.127245 [CATrainingPosCal] consider 1 rank data
8352 09:31:24.130240 u2DelayCellTimex100 = 290/100 ps
8353 09:31:24.133851 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8354 09:31:24.140443 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8355 09:31:24.143656 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8356 09:31:24.147218 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8357 09:31:24.150349 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8358 09:31:24.153510 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8359 09:31:24.153593
8360 09:31:24.156819 CA PerBit enable=1, Macro0, CA PI delay=37
8361 09:31:24.156902
8362 09:31:24.160464 [CBTSetCACLKResult] CA Dly = 37
8363 09:31:24.163616 CS Dly: 8 (0~39)
8364 09:31:24.166679 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8365 09:31:24.170054 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8366 09:31:24.170137 ==
8367 09:31:24.173623 Dram Type= 6, Freq= 0, CH_1, rank 1
8368 09:31:24.176689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 09:31:24.180307 ==
8370 09:31:24.183358 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8371 09:31:24.186437 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8372 09:31:24.193192 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8373 09:31:24.196909 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8374 09:31:24.206855 [CA 0] Center 41 (12~71) winsize 60
8375 09:31:24.210454 [CA 1] Center 41 (12~71) winsize 60
8376 09:31:24.213555 [CA 2] Center 38 (8~68) winsize 61
8377 09:31:24.217158 [CA 3] Center 37 (8~67) winsize 60
8378 09:31:24.220168 [CA 4] Center 37 (8~67) winsize 60
8379 09:31:24.223774 [CA 5] Center 37 (7~67) winsize 61
8380 09:31:24.223855
8381 09:31:24.226945 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8382 09:31:24.227025
8383 09:31:24.230084 [CATrainingPosCal] consider 2 rank data
8384 09:31:24.233754 u2DelayCellTimex100 = 290/100 ps
8385 09:31:24.236870 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8386 09:31:24.243568 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8387 09:31:24.247085 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8388 09:31:24.250251 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8389 09:31:24.253808 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8390 09:31:24.256942 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8391 09:31:24.257023
8392 09:31:24.260318 CA PerBit enable=1, Macro0, CA PI delay=37
8393 09:31:24.260424
8394 09:31:24.263643 [CBTSetCACLKResult] CA Dly = 37
8395 09:31:24.263719 CS Dly: 9 (0~42)
8396 09:31:24.270336 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8397 09:31:24.273429 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8398 09:31:24.273514
8399 09:31:24.277099 ----->DramcWriteLeveling(PI) begin...
8400 09:31:24.277183 ==
8401 09:31:24.280055 Dram Type= 6, Freq= 0, CH_1, rank 0
8402 09:31:24.283563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8403 09:31:24.286636 ==
8404 09:31:24.286717 Write leveling (Byte 0): 24 => 24
8405 09:31:24.290126 Write leveling (Byte 1): 28 => 28
8406 09:31:24.293029 DramcWriteLeveling(PI) end<-----
8407 09:31:24.293132
8408 09:31:24.293197 ==
8409 09:31:24.296621 Dram Type= 6, Freq= 0, CH_1, rank 0
8410 09:31:24.303299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8411 09:31:24.303389 ==
8412 09:31:24.303453 [Gating] SW mode calibration
8413 09:31:24.313187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8414 09:31:24.316304 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8415 09:31:24.323353 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 09:31:24.326632 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 09:31:24.329558 1 4 8 | B1->B0 | 2828 2c2c | 1 1 | (1 1) (1 1)
8418 09:31:24.336170 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8419 09:31:24.339713 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8420 09:31:24.343304 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8421 09:31:24.346407 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8422 09:31:24.353134 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8423 09:31:24.356612 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 09:31:24.359612 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8425 09:31:24.366480 1 5 8 | B1->B0 | 3131 2e2e | 0 0 | (0 1) (0 1)
8426 09:31:24.369792 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8427 09:31:24.373356 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8428 09:31:24.380016 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8429 09:31:24.383046 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8430 09:31:24.386490 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 09:31:24.393076 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 09:31:24.396033 1 6 4 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
8433 09:31:24.399561 1 6 8 | B1->B0 | 3c3c 4343 | 0 0 | (0 0) (0 0)
8434 09:31:24.406055 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8435 09:31:24.409677 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8436 09:31:24.413048 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8437 09:31:24.419474 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8438 09:31:24.422719 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 09:31:24.426351 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 09:31:24.433010 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8441 09:31:24.436156 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8442 09:31:24.439219 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8443 09:31:24.446302 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 09:31:24.449351 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 09:31:24.453009 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 09:31:24.459195 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 09:31:24.462739 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 09:31:24.465821 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 09:31:24.472735 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 09:31:24.475709 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 09:31:24.479376 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 09:31:24.482463 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 09:31:24.489410 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 09:31:24.492433 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 09:31:24.496093 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 09:31:24.502543 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8457 09:31:24.506031 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8458 09:31:24.509120 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8459 09:31:24.515542 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 09:31:24.518933 Total UI for P1: 0, mck2ui 16
8461 09:31:24.522508 best dqsien dly found for B0: ( 1, 9, 8)
8462 09:31:24.522621 Total UI for P1: 0, mck2ui 16
8463 09:31:24.529180 best dqsien dly found for B1: ( 1, 9, 10)
8464 09:31:24.532247 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8465 09:31:24.535821 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8466 09:31:24.535901
8467 09:31:24.538883 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8468 09:31:24.542063 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8469 09:31:24.545510 [Gating] SW calibration Done
8470 09:31:24.545597 ==
8471 09:31:24.548720 Dram Type= 6, Freq= 0, CH_1, rank 0
8472 09:31:24.552334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8473 09:31:24.552422 ==
8474 09:31:24.555409 RX Vref Scan: 0
8475 09:31:24.555494
8476 09:31:24.558539 RX Vref 0 -> 0, step: 1
8477 09:31:24.558623
8478 09:31:24.558722 RX Delay 0 -> 252, step: 8
8479 09:31:24.562039 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8480 09:31:24.568774 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8481 09:31:24.571798 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8482 09:31:24.575555 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8483 09:31:24.578838 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8484 09:31:24.581796 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8485 09:31:24.588762 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8486 09:31:24.592084 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8487 09:31:24.595088 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8488 09:31:24.598680 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8489 09:31:24.601839 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8490 09:31:24.609009 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8491 09:31:24.611986 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8492 09:31:24.615475 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8493 09:31:24.618455 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8494 09:31:24.621989 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8495 09:31:24.622070 ==
8496 09:31:24.625097 Dram Type= 6, Freq= 0, CH_1, rank 0
8497 09:31:24.632147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8498 09:31:24.632231 ==
8499 09:31:24.632298 DQS Delay:
8500 09:31:24.635249 DQS0 = 0, DQS1 = 0
8501 09:31:24.635326 DQM Delay:
8502 09:31:24.638972 DQM0 = 137, DQM1 = 131
8503 09:31:24.639048 DQ Delay:
8504 09:31:24.642102 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8505 09:31:24.645203 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8506 09:31:24.648749 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8507 09:31:24.652333 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8508 09:31:24.652439
8509 09:31:24.652525
8510 09:31:24.652643 ==
8511 09:31:24.655382 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 09:31:24.658533 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 09:31:24.662271 ==
8514 09:31:24.662350
8515 09:31:24.662414
8516 09:31:24.662472 TX Vref Scan disable
8517 09:31:24.665412 == TX Byte 0 ==
8518 09:31:24.668457 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8519 09:31:24.672097 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8520 09:31:24.675218 == TX Byte 1 ==
8521 09:31:24.678735 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8522 09:31:24.682347 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8523 09:31:24.685306 ==
8524 09:31:24.685382 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 09:31:24.691912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 09:31:24.691994 ==
8527 09:31:24.703823
8528 09:31:24.707389 TX Vref early break, caculate TX vref
8529 09:31:24.710543 TX Vref=16, minBit 10, minWin=21, winSum=369
8530 09:31:24.714000 TX Vref=18, minBit 15, minWin=22, winSum=380
8531 09:31:24.717022 TX Vref=20, minBit 10, minWin=23, winSum=392
8532 09:31:24.720528 TX Vref=22, minBit 15, minWin=23, winSum=395
8533 09:31:24.726973 TX Vref=24, minBit 10, minWin=24, winSum=408
8534 09:31:24.730603 TX Vref=26, minBit 10, minWin=24, winSum=414
8535 09:31:24.734287 TX Vref=28, minBit 10, minWin=25, winSum=419
8536 09:31:24.737274 TX Vref=30, minBit 9, minWin=24, winSum=417
8537 09:31:24.740330 TX Vref=32, minBit 9, minWin=24, winSum=404
8538 09:31:24.744087 TX Vref=34, minBit 9, minWin=23, winSum=394
8539 09:31:24.750562 [TxChooseVref] Worse bit 10, Min win 25, Win sum 419, Final Vref 28
8540 09:31:24.750649
8541 09:31:24.753660 Final TX Range 0 Vref 28
8542 09:31:24.753766
8543 09:31:24.753830 ==
8544 09:31:24.757343 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 09:31:24.760271 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 09:31:24.760389 ==
8547 09:31:24.760482
8548 09:31:24.760576
8549 09:31:24.763771 TX Vref Scan disable
8550 09:31:24.770538 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8551 09:31:24.770626 == TX Byte 0 ==
8552 09:31:24.773571 u2DelayCellOfst[0]=16 cells (5 PI)
8553 09:31:24.777146 u2DelayCellOfst[1]=10 cells (3 PI)
8554 09:31:24.780219 u2DelayCellOfst[2]=0 cells (0 PI)
8555 09:31:24.783945 u2DelayCellOfst[3]=3 cells (1 PI)
8556 09:31:24.786664 u2DelayCellOfst[4]=6 cells (2 PI)
8557 09:31:24.790348 u2DelayCellOfst[5]=16 cells (5 PI)
8558 09:31:24.793447 u2DelayCellOfst[6]=16 cells (5 PI)
8559 09:31:24.796973 u2DelayCellOfst[7]=3 cells (1 PI)
8560 09:31:24.800053 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8561 09:31:24.803533 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8562 09:31:24.806703 == TX Byte 1 ==
8563 09:31:24.810200 u2DelayCellOfst[8]=0 cells (0 PI)
8564 09:31:24.810288 u2DelayCellOfst[9]=3 cells (1 PI)
8565 09:31:24.813736 u2DelayCellOfst[10]=10 cells (3 PI)
8566 09:31:24.816780 u2DelayCellOfst[11]=3 cells (1 PI)
8567 09:31:24.820394 u2DelayCellOfst[12]=16 cells (5 PI)
8568 09:31:24.823496 u2DelayCellOfst[13]=16 cells (5 PI)
8569 09:31:24.826940 u2DelayCellOfst[14]=20 cells (6 PI)
8570 09:31:24.829814 u2DelayCellOfst[15]=20 cells (6 PI)
8571 09:31:24.833358 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8572 09:31:24.840038 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8573 09:31:24.840128 DramC Write-DBI on
8574 09:31:24.840215 ==
8575 09:31:24.843600 Dram Type= 6, Freq= 0, CH_1, rank 0
8576 09:31:24.849811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8577 09:31:24.849902 ==
8578 09:31:24.849988
8579 09:31:24.850069
8580 09:31:24.850149 TX Vref Scan disable
8581 09:31:24.853867 == TX Byte 0 ==
8582 09:31:24.856983 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8583 09:31:24.860567 == TX Byte 1 ==
8584 09:31:24.863757 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8585 09:31:24.863846 DramC Write-DBI off
8586 09:31:24.867391
8587 09:31:24.867478 [DATLAT]
8588 09:31:24.867564 Freq=1600, CH1 RK0
8589 09:31:24.867646
8590 09:31:24.870489 DATLAT Default: 0xf
8591 09:31:24.870577 0, 0xFFFF, sum = 0
8592 09:31:24.874239 1, 0xFFFF, sum = 0
8593 09:31:24.874329 2, 0xFFFF, sum = 0
8594 09:31:24.877135 3, 0xFFFF, sum = 0
8595 09:31:24.880718 4, 0xFFFF, sum = 0
8596 09:31:24.880835 5, 0xFFFF, sum = 0
8597 09:31:24.883772 6, 0xFFFF, sum = 0
8598 09:31:24.883862 7, 0xFFFF, sum = 0
8599 09:31:24.887337 8, 0xFFFF, sum = 0
8600 09:31:24.887427 9, 0xFFFF, sum = 0
8601 09:31:24.890316 10, 0xFFFF, sum = 0
8602 09:31:24.890405 11, 0xFFFF, sum = 0
8603 09:31:24.893730 12, 0xFFFF, sum = 0
8604 09:31:24.893819 13, 0xFFFF, sum = 0
8605 09:31:24.897361 14, 0x0, sum = 1
8606 09:31:24.897447 15, 0x0, sum = 2
8607 09:31:24.900475 16, 0x0, sum = 3
8608 09:31:24.900571 17, 0x0, sum = 4
8609 09:31:24.903908 best_step = 15
8610 09:31:24.903992
8611 09:31:24.904060 ==
8612 09:31:24.906901 Dram Type= 6, Freq= 0, CH_1, rank 0
8613 09:31:24.910309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8614 09:31:24.910394 ==
8615 09:31:24.910461 RX Vref Scan: 1
8616 09:31:24.913870
8617 09:31:24.913954 Set Vref Range= 24 -> 127
8618 09:31:24.914020
8619 09:31:24.917357 RX Vref 24 -> 127, step: 1
8620 09:31:24.917441
8621 09:31:24.920369 RX Delay 19 -> 252, step: 4
8622 09:31:24.920492
8623 09:31:24.923528 Set Vref, RX VrefLevel [Byte0]: 24
8624 09:31:24.927133 [Byte1]: 24
8625 09:31:24.927218
8626 09:31:24.930472 Set Vref, RX VrefLevel [Byte0]: 25
8627 09:31:24.933431 [Byte1]: 25
8628 09:31:24.933516
8629 09:31:24.936648 Set Vref, RX VrefLevel [Byte0]: 26
8630 09:31:24.940338 [Byte1]: 26
8631 09:31:24.943931
8632 09:31:24.944014 Set Vref, RX VrefLevel [Byte0]: 27
8633 09:31:24.947651 [Byte1]: 27
8634 09:31:24.951776
8635 09:31:24.951858 Set Vref, RX VrefLevel [Byte0]: 28
8636 09:31:24.954762 [Byte1]: 28
8637 09:31:24.959433
8638 09:31:24.959516 Set Vref, RX VrefLevel [Byte0]: 29
8639 09:31:24.962540 [Byte1]: 29
8640 09:31:24.966685
8641 09:31:24.966768 Set Vref, RX VrefLevel [Byte0]: 30
8642 09:31:24.970316 [Byte1]: 30
8643 09:31:24.974388
8644 09:31:24.974471 Set Vref, RX VrefLevel [Byte0]: 31
8645 09:31:24.977476 [Byte1]: 31
8646 09:31:24.982013
8647 09:31:24.982096 Set Vref, RX VrefLevel [Byte0]: 32
8648 09:31:24.985019 [Byte1]: 32
8649 09:31:24.989581
8650 09:31:24.989664 Set Vref, RX VrefLevel [Byte0]: 33
8651 09:31:24.992685 [Byte1]: 33
8652 09:31:24.997101
8653 09:31:24.997184 Set Vref, RX VrefLevel [Byte0]: 34
8654 09:31:25.000166 [Byte1]: 34
8655 09:31:25.004817
8656 09:31:25.004901 Set Vref, RX VrefLevel [Byte0]: 35
8657 09:31:25.007936 [Byte1]: 35
8658 09:31:25.012494
8659 09:31:25.012630 Set Vref, RX VrefLevel [Byte0]: 36
8660 09:31:25.015477 [Byte1]: 36
8661 09:31:25.020128
8662 09:31:25.020210 Set Vref, RX VrefLevel [Byte0]: 37
8663 09:31:25.023232 [Byte1]: 37
8664 09:31:25.027469
8665 09:31:25.027552 Set Vref, RX VrefLevel [Byte0]: 38
8666 09:31:25.030538 [Byte1]: 38
8667 09:31:25.035033
8668 09:31:25.035116 Set Vref, RX VrefLevel [Byte0]: 39
8669 09:31:25.038304 [Byte1]: 39
8670 09:31:25.042777
8671 09:31:25.042861 Set Vref, RX VrefLevel [Byte0]: 40
8672 09:31:25.045824 [Byte1]: 40
8673 09:31:25.050041
8674 09:31:25.050124 Set Vref, RX VrefLevel [Byte0]: 41
8675 09:31:25.053602 [Byte1]: 41
8676 09:31:25.057643
8677 09:31:25.057726 Set Vref, RX VrefLevel [Byte0]: 42
8678 09:31:25.060745 [Byte1]: 42
8679 09:31:25.065435
8680 09:31:25.065518 Set Vref, RX VrefLevel [Byte0]: 43
8681 09:31:25.068672 [Byte1]: 43
8682 09:31:25.072578
8683 09:31:25.072661 Set Vref, RX VrefLevel [Byte0]: 44
8684 09:31:25.076052 [Byte1]: 44
8685 09:31:25.080600
8686 09:31:25.080683 Set Vref, RX VrefLevel [Byte0]: 45
8687 09:31:25.086756 [Byte1]: 45
8688 09:31:25.086842
8689 09:31:25.090259 Set Vref, RX VrefLevel [Byte0]: 46
8690 09:31:25.093440 [Byte1]: 46
8691 09:31:25.093523
8692 09:31:25.097029 Set Vref, RX VrefLevel [Byte0]: 47
8693 09:31:25.100431 [Byte1]: 47
8694 09:31:25.100515
8695 09:31:25.103585 Set Vref, RX VrefLevel [Byte0]: 48
8696 09:31:25.106803 [Byte1]: 48
8697 09:31:25.111006
8698 09:31:25.111092 Set Vref, RX VrefLevel [Byte0]: 49
8699 09:31:25.114026 [Byte1]: 49
8700 09:31:25.118312
8701 09:31:25.118398 Set Vref, RX VrefLevel [Byte0]: 50
8702 09:31:25.121813 [Byte1]: 50
8703 09:31:25.125838
8704 09:31:25.125923 Set Vref, RX VrefLevel [Byte0]: 51
8705 09:31:25.128890 [Byte1]: 51
8706 09:31:25.133503
8707 09:31:25.133589 Set Vref, RX VrefLevel [Byte0]: 52
8708 09:31:25.136603 [Byte1]: 52
8709 09:31:25.141042
8710 09:31:25.141178 Set Vref, RX VrefLevel [Byte0]: 53
8711 09:31:25.144272 [Byte1]: 53
8712 09:31:25.148376
8713 09:31:25.148461 Set Vref, RX VrefLevel [Byte0]: 54
8714 09:31:25.151998 [Byte1]: 54
8715 09:31:25.156107
8716 09:31:25.156190 Set Vref, RX VrefLevel [Byte0]: 55
8717 09:31:25.159643 [Byte1]: 55
8718 09:31:25.163882
8719 09:31:25.163966 Set Vref, RX VrefLevel [Byte0]: 56
8720 09:31:25.166947 [Byte1]: 56
8721 09:31:25.171095
8722 09:31:25.171178 Set Vref, RX VrefLevel [Byte0]: 57
8723 09:31:25.174777 [Byte1]: 57
8724 09:31:25.178840
8725 09:31:25.178923 Set Vref, RX VrefLevel [Byte0]: 58
8726 09:31:25.182443 [Byte1]: 58
8727 09:31:25.186454
8728 09:31:25.186539 Set Vref, RX VrefLevel [Byte0]: 59
8729 09:31:25.190045 [Byte1]: 59
8730 09:31:25.194270
8731 09:31:25.194354 Set Vref, RX VrefLevel [Byte0]: 60
8732 09:31:25.197304 [Byte1]: 60
8733 09:31:25.201779
8734 09:31:25.201864 Set Vref, RX VrefLevel [Byte0]: 61
8735 09:31:25.204983 [Byte1]: 61
8736 09:31:25.208928
8737 09:31:25.209013 Set Vref, RX VrefLevel [Byte0]: 62
8738 09:31:25.212539 [Byte1]: 62
8739 09:31:25.216615
8740 09:31:25.216701 Set Vref, RX VrefLevel [Byte0]: 63
8741 09:31:25.220186 [Byte1]: 63
8742 09:31:25.224185
8743 09:31:25.224269 Set Vref, RX VrefLevel [Byte0]: 64
8744 09:31:25.227761 [Byte1]: 64
8745 09:31:25.231936
8746 09:31:25.232020 Set Vref, RX VrefLevel [Byte0]: 65
8747 09:31:25.235061 [Byte1]: 65
8748 09:31:25.239595
8749 09:31:25.239681 Set Vref, RX VrefLevel [Byte0]: 66
8750 09:31:25.242573 [Byte1]: 66
8751 09:31:25.246877
8752 09:31:25.246961 Set Vref, RX VrefLevel [Byte0]: 67
8753 09:31:25.250313 [Byte1]: 67
8754 09:31:25.254335
8755 09:31:25.254418 Set Vref, RX VrefLevel [Byte0]: 68
8756 09:31:25.258039 [Byte1]: 68
8757 09:31:25.262158
8758 09:31:25.262242 Set Vref, RX VrefLevel [Byte0]: 69
8759 09:31:25.265199 [Byte1]: 69
8760 09:31:25.269812
8761 09:31:25.269899 Set Vref, RX VrefLevel [Byte0]: 70
8762 09:31:25.272801 [Byte1]: 70
8763 09:31:25.277412
8764 09:31:25.277495 Set Vref, RX VrefLevel [Byte0]: 71
8765 09:31:25.280420 [Byte1]: 71
8766 09:31:25.284846
8767 09:31:25.284930 Set Vref, RX VrefLevel [Byte0]: 72
8768 09:31:25.288245 [Byte1]: 72
8769 09:31:25.292195
8770 09:31:25.292342 Final RX Vref Byte 0 = 62 to rank0
8771 09:31:25.295584 Final RX Vref Byte 1 = 61 to rank0
8772 09:31:25.299209 Final RX Vref Byte 0 = 62 to rank1
8773 09:31:25.302262 Final RX Vref Byte 1 = 61 to rank1==
8774 09:31:25.305666 Dram Type= 6, Freq= 0, CH_1, rank 0
8775 09:31:25.312428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8776 09:31:25.312541 ==
8777 09:31:25.312629 DQS Delay:
8778 09:31:25.312729 DQS0 = 0, DQS1 = 0
8779 09:31:25.315672 DQM Delay:
8780 09:31:25.315754 DQM0 = 134, DQM1 = 129
8781 09:31:25.319154 DQ Delay:
8782 09:31:25.322022 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =134
8783 09:31:25.325441 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8784 09:31:25.328817 DQ8 =116, DQ9 =118, DQ10 =134, DQ11 =122
8785 09:31:25.332427 DQ12 =140, DQ13 =134, DQ14 =138, DQ15 =136
8786 09:31:25.332511
8787 09:31:25.332616
8788 09:31:25.332678
8789 09:31:25.335522 [DramC_TX_OE_Calibration] TA2
8790 09:31:25.339021 Original DQ_B0 (3 6) =30, OEN = 27
8791 09:31:25.342004 Original DQ_B1 (3 6) =30, OEN = 27
8792 09:31:25.345557 24, 0x0, End_B0=24 End_B1=24
8793 09:31:25.345644 25, 0x0, End_B0=25 End_B1=25
8794 09:31:25.348997 26, 0x0, End_B0=26 End_B1=26
8795 09:31:25.352365 27, 0x0, End_B0=27 End_B1=27
8796 09:31:25.355714 28, 0x0, End_B0=28 End_B1=28
8797 09:31:25.358905 29, 0x0, End_B0=29 End_B1=29
8798 09:31:25.358990 30, 0x0, End_B0=30 End_B1=30
8799 09:31:25.361890 31, 0x4141, End_B0=30 End_B1=30
8800 09:31:25.365469 Byte0 end_step=30 best_step=27
8801 09:31:25.369136 Byte1 end_step=30 best_step=27
8802 09:31:25.372010 Byte0 TX OE(2T, 0.5T) = (3, 3)
8803 09:31:25.375563 Byte1 TX OE(2T, 0.5T) = (3, 3)
8804 09:31:25.375648
8805 09:31:25.375716
8806 09:31:25.382037 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8807 09:31:25.385525 CH1 RK0: MR19=303, MR18=1624
8808 09:31:25.392035 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8809 09:31:25.392135
8810 09:31:25.395321 ----->DramcWriteLeveling(PI) begin...
8811 09:31:25.395435 ==
8812 09:31:25.398922 Dram Type= 6, Freq= 0, CH_1, rank 1
8813 09:31:25.402036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8814 09:31:25.402122 ==
8815 09:31:25.405129 Write leveling (Byte 0): 26 => 26
8816 09:31:25.408499 Write leveling (Byte 1): 28 => 28
8817 09:31:25.411670 DramcWriteLeveling(PI) end<-----
8818 09:31:25.411753
8819 09:31:25.411818 ==
8820 09:31:25.415175 Dram Type= 6, Freq= 0, CH_1, rank 1
8821 09:31:25.418584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8822 09:31:25.418681 ==
8823 09:31:25.421802 [Gating] SW mode calibration
8824 09:31:25.428384 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8825 09:31:25.435283 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8826 09:31:25.438365 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 09:31:25.441839 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 09:31:25.448317 1 4 8 | B1->B0 | 3131 2323 | 1 0 | (1 1) (0 0)
8829 09:31:25.451839 1 4 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 1)
8830 09:31:25.455319 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 09:31:25.461563 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 09:31:25.464912 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 09:31:25.468518 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 09:31:25.475101 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 09:31:25.478155 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 09:31:25.481669 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (1 0) (1 0)
8837 09:31:25.488125 1 5 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 0)
8838 09:31:25.491646 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 09:31:25.494768 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 09:31:25.501595 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 09:31:25.505069 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 09:31:25.508026 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 09:31:25.515118 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 09:31:25.518582 1 6 8 | B1->B0 | 4343 2423 | 0 1 | (0 0) (0 0)
8845 09:31:25.521953 1 6 12 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
8846 09:31:25.528531 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8847 09:31:25.531623 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 09:31:25.535016 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 09:31:25.541535 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 09:31:25.544992 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 09:31:25.547952 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 09:31:25.554997 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8853 09:31:25.557974 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8854 09:31:25.561364 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8855 09:31:25.564944 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 09:31:25.571398 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 09:31:25.574494 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 09:31:25.577949 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 09:31:25.584423 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 09:31:25.587945 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 09:31:25.590976 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 09:31:25.597804 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 09:31:25.601380 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 09:31:25.604430 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 09:31:25.611369 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 09:31:25.614355 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 09:31:25.617988 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 09:31:25.624963 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8869 09:31:25.627895 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8870 09:31:25.631235 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 09:31:25.634588 Total UI for P1: 0, mck2ui 16
8872 09:31:25.637685 best dqsien dly found for B0: ( 1, 9, 10)
8873 09:31:25.641293 Total UI for P1: 0, mck2ui 16
8874 09:31:25.644137 best dqsien dly found for B1: ( 1, 9, 10)
8875 09:31:25.647473 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8876 09:31:25.650986 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8877 09:31:25.651112
8878 09:31:25.657452 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8879 09:31:25.660972 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8880 09:31:25.664434 [Gating] SW calibration Done
8881 09:31:25.664559 ==
8882 09:31:25.667380 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 09:31:25.670855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 09:31:25.670975 ==
8885 09:31:25.671076 RX Vref Scan: 0
8886 09:31:25.671178
8887 09:31:25.674300 RX Vref 0 -> 0, step: 1
8888 09:31:25.674413
8889 09:31:25.677322 RX Delay 0 -> 252, step: 8
8890 09:31:25.680895 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8891 09:31:25.683941 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8892 09:31:25.687457 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8893 09:31:25.693948 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8894 09:31:25.697303 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8895 09:31:25.700778 iDelay=200, Bit 5, Center 143 (96 ~ 191) 96
8896 09:31:25.704236 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8897 09:31:25.707230 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8898 09:31:25.713848 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8899 09:31:25.717341 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8900 09:31:25.720420 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8901 09:31:25.723928 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8902 09:31:25.727360 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8903 09:31:25.733813 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8904 09:31:25.737129 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8905 09:31:25.740553 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8906 09:31:25.740646 ==
8907 09:31:25.743612 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 09:31:25.747085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 09:31:25.750293 ==
8910 09:31:25.750389 DQS Delay:
8911 09:31:25.750467 DQS0 = 0, DQS1 = 0
8912 09:31:25.753705 DQM Delay:
8913 09:31:25.753793 DQM0 = 136, DQM1 = 132
8914 09:31:25.756919 DQ Delay:
8915 09:31:25.760424 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8916 09:31:25.763599 DQ4 =139, DQ5 =143, DQ6 =143, DQ7 =135
8917 09:31:25.767074 DQ8 =115, DQ9 =123, DQ10 =135, DQ11 =127
8918 09:31:25.769939 DQ12 =143, DQ13 =139, DQ14 =135, DQ15 =139
8919 09:31:25.770036
8920 09:31:25.770105
8921 09:31:25.770167 ==
8922 09:31:25.773418 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 09:31:25.777159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 09:31:25.780034 ==
8925 09:31:25.780153
8926 09:31:25.780251
8927 09:31:25.780345 TX Vref Scan disable
8928 09:31:25.783650 == TX Byte 0 ==
8929 09:31:25.786664 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8930 09:31:25.790109 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8931 09:31:25.793502 == TX Byte 1 ==
8932 09:31:25.796571 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8933 09:31:25.800064 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8934 09:31:25.800160 ==
8935 09:31:25.803057 Dram Type= 6, Freq= 0, CH_1, rank 1
8936 09:31:25.810118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8937 09:31:25.810219 ==
8938 09:31:25.822614
8939 09:31:25.826026 TX Vref early break, caculate TX vref
8940 09:31:25.829505 TX Vref=16, minBit 9, minWin=22, winSum=381
8941 09:31:25.832492 TX Vref=18, minBit 8, minWin=23, winSum=393
8942 09:31:25.835920 TX Vref=20, minBit 9, minWin=23, winSum=398
8943 09:31:25.839292 TX Vref=22, minBit 9, minWin=23, winSum=405
8944 09:31:25.842619 TX Vref=24, minBit 12, minWin=24, winSum=420
8945 09:31:25.849117 TX Vref=26, minBit 12, minWin=24, winSum=419
8946 09:31:25.852470 TX Vref=28, minBit 10, minWin=25, winSum=420
8947 09:31:25.856364 TX Vref=30, minBit 5, minWin=25, winSum=413
8948 09:31:25.859320 TX Vref=32, minBit 0, minWin=24, winSum=405
8949 09:31:25.862731 TX Vref=34, minBit 9, minWin=23, winSum=399
8950 09:31:25.866347 TX Vref=36, minBit 9, minWin=23, winSum=391
8951 09:31:25.872825 [TxChooseVref] Worse bit 10, Min win 25, Win sum 420, Final Vref 28
8952 09:31:25.872929
8953 09:31:25.876117 Final TX Range 0 Vref 28
8954 09:31:25.876207
8955 09:31:25.876274 ==
8956 09:31:25.879588 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 09:31:25.883033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 09:31:25.883122 ==
8959 09:31:25.883189
8960 09:31:25.886119
8961 09:31:25.886203 TX Vref Scan disable
8962 09:31:25.892629 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8963 09:31:25.892721 == TX Byte 0 ==
8964 09:31:25.896013 u2DelayCellOfst[0]=16 cells (5 PI)
8965 09:31:25.899532 u2DelayCellOfst[1]=10 cells (3 PI)
8966 09:31:25.902521 u2DelayCellOfst[2]=0 cells (0 PI)
8967 09:31:25.906090 u2DelayCellOfst[3]=6 cells (2 PI)
8968 09:31:25.909401 u2DelayCellOfst[4]=10 cells (3 PI)
8969 09:31:25.912499 u2DelayCellOfst[5]=20 cells (6 PI)
8970 09:31:25.916078 u2DelayCellOfst[6]=16 cells (5 PI)
8971 09:31:25.919546 u2DelayCellOfst[7]=6 cells (2 PI)
8972 09:31:25.922928 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8973 09:31:25.925841 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8974 09:31:25.929438 == TX Byte 1 ==
8975 09:31:25.932466 u2DelayCellOfst[8]=0 cells (0 PI)
8976 09:31:25.932564 u2DelayCellOfst[9]=3 cells (1 PI)
8977 09:31:25.935981 u2DelayCellOfst[10]=13 cells (4 PI)
8978 09:31:25.939387 u2DelayCellOfst[11]=3 cells (1 PI)
8979 09:31:25.942631 u2DelayCellOfst[12]=13 cells (4 PI)
8980 09:31:25.945787 u2DelayCellOfst[13]=16 cells (5 PI)
8981 09:31:25.949105 u2DelayCellOfst[14]=20 cells (6 PI)
8982 09:31:25.952464 u2DelayCellOfst[15]=16 cells (5 PI)
8983 09:31:25.956023 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8984 09:31:25.962340 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8985 09:31:25.962498 DramC Write-DBI on
8986 09:31:25.962573 ==
8987 09:31:25.965950 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 09:31:25.972568 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 09:31:25.972724 ==
8990 09:31:25.972798
8991 09:31:25.972860
8992 09:31:25.972919 TX Vref Scan disable
8993 09:31:25.976169 == TX Byte 0 ==
8994 09:31:25.979493 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8995 09:31:25.983153 == TX Byte 1 ==
8996 09:31:25.986145 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8997 09:31:25.989697 DramC Write-DBI off
8998 09:31:25.989805
8999 09:31:25.989874 [DATLAT]
9000 09:31:25.989935 Freq=1600, CH1 RK1
9001 09:31:25.989994
9002 09:31:25.992858 DATLAT Default: 0xf
9003 09:31:25.992941 0, 0xFFFF, sum = 0
9004 09:31:25.996209 1, 0xFFFF, sum = 0
9005 09:31:25.999696 2, 0xFFFF, sum = 0
9006 09:31:25.999782 3, 0xFFFF, sum = 0
9007 09:31:26.002618 4, 0xFFFF, sum = 0
9008 09:31:26.002703 5, 0xFFFF, sum = 0
9009 09:31:26.005993 6, 0xFFFF, sum = 0
9010 09:31:26.006078 7, 0xFFFF, sum = 0
9011 09:31:26.009520 8, 0xFFFF, sum = 0
9012 09:31:26.009617 9, 0xFFFF, sum = 0
9013 09:31:26.012472 10, 0xFFFF, sum = 0
9014 09:31:26.012620 11, 0xFFFF, sum = 0
9015 09:31:26.016039 12, 0xFFFF, sum = 0
9016 09:31:26.016124 13, 0xFFFF, sum = 0
9017 09:31:26.019689 14, 0x0, sum = 1
9018 09:31:26.019773 15, 0x0, sum = 2
9019 09:31:26.022639 16, 0x0, sum = 3
9020 09:31:26.022729 17, 0x0, sum = 4
9021 09:31:26.026086 best_step = 15
9022 09:31:26.026197
9023 09:31:26.026310 ==
9024 09:31:26.028991 Dram Type= 6, Freq= 0, CH_1, rank 1
9025 09:31:26.032501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9026 09:31:26.032640 ==
9027 09:31:26.036144 RX Vref Scan: 0
9028 09:31:26.036282
9029 09:31:26.036365 RX Vref 0 -> 0, step: 1
9030 09:31:26.036428
9031 09:31:26.039143 RX Delay 19 -> 252, step: 4
9032 09:31:26.042564 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9033 09:31:26.049440 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9034 09:31:26.052965 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
9035 09:31:26.055927 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
9036 09:31:26.059491 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
9037 09:31:26.062835 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
9038 09:31:26.066072 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9039 09:31:26.072919 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
9040 09:31:26.075868 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
9041 09:31:26.079414 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
9042 09:31:26.082557 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9043 09:31:26.086055 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
9044 09:31:26.092495 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9045 09:31:26.096053 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9046 09:31:26.099111 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
9047 09:31:26.102490 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
9048 09:31:26.102577 ==
9049 09:31:26.106032 Dram Type= 6, Freq= 0, CH_1, rank 1
9050 09:31:26.112512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9051 09:31:26.112612 ==
9052 09:31:26.112680 DQS Delay:
9053 09:31:26.116046 DQS0 = 0, DQS1 = 0
9054 09:31:26.116130 DQM Delay:
9055 09:31:26.116195 DQM0 = 134, DQM1 = 130
9056 09:31:26.119133 DQ Delay:
9057 09:31:26.122570 DQ0 =138, DQ1 =130, DQ2 =120, DQ3 =132
9058 09:31:26.126076 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
9059 09:31:26.129534 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
9060 09:31:26.132397 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
9061 09:31:26.132481
9062 09:31:26.132551
9063 09:31:26.132644
9064 09:31:26.135902 [DramC_TX_OE_Calibration] TA2
9065 09:31:26.139069 Original DQ_B0 (3 6) =30, OEN = 27
9066 09:31:26.142594 Original DQ_B1 (3 6) =30, OEN = 27
9067 09:31:26.146030 24, 0x0, End_B0=24 End_B1=24
9068 09:31:26.146126 25, 0x0, End_B0=25 End_B1=25
9069 09:31:26.149119 26, 0x0, End_B0=26 End_B1=26
9070 09:31:26.152457 27, 0x0, End_B0=27 End_B1=27
9071 09:31:26.155664 28, 0x0, End_B0=28 End_B1=28
9072 09:31:26.159129 29, 0x0, End_B0=29 End_B1=29
9073 09:31:26.159214 30, 0x0, End_B0=30 End_B1=30
9074 09:31:26.162531 31, 0x4545, End_B0=30 End_B1=30
9075 09:31:26.165527 Byte0 end_step=30 best_step=27
9076 09:31:26.168908 Byte1 end_step=30 best_step=27
9077 09:31:26.172406 Byte0 TX OE(2T, 0.5T) = (3, 3)
9078 09:31:26.175553 Byte1 TX OE(2T, 0.5T) = (3, 3)
9079 09:31:26.175637
9080 09:31:26.175701
9081 09:31:26.182499 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps
9082 09:31:26.185543 CH1 RK1: MR19=303, MR18=1C07
9083 09:31:26.192321 CH1_RK1: MR19=0x303, MR18=0x1C07, DQSOSC=395, MR23=63, INC=23, DEC=15
9084 09:31:26.195337 [RxdqsGatingPostProcess] freq 1600
9085 09:31:26.199013 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9086 09:31:26.201937 best DQS0 dly(2T, 0.5T) = (1, 1)
9087 09:31:26.205436 best DQS1 dly(2T, 0.5T) = (1, 1)
9088 09:31:26.208853 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9089 09:31:26.212430 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9090 09:31:26.215394 best DQS0 dly(2T, 0.5T) = (1, 1)
9091 09:31:26.219058 best DQS1 dly(2T, 0.5T) = (1, 1)
9092 09:31:26.222048 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9093 09:31:26.225581 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9094 09:31:26.229161 Pre-setting of DQS Precalculation
9095 09:31:26.232471 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9096 09:31:26.239073 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9097 09:31:26.245584 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9098 09:31:26.249190
9099 09:31:26.249285
9100 09:31:26.249350 [Calibration Summary] 3200 Mbps
9101 09:31:26.252085 CH 0, Rank 0
9102 09:31:26.252168 SW Impedance : PASS
9103 09:31:26.255607 DUTY Scan : NO K
9104 09:31:26.258850 ZQ Calibration : PASS
9105 09:31:26.258973 Jitter Meter : NO K
9106 09:31:26.262413 CBT Training : PASS
9107 09:31:26.265368 Write leveling : PASS
9108 09:31:26.265500 RX DQS gating : PASS
9109 09:31:26.268808 RX DQ/DQS(RDDQC) : PASS
9110 09:31:26.271911 TX DQ/DQS : PASS
9111 09:31:26.271995 RX DATLAT : PASS
9112 09:31:26.275338 RX DQ/DQS(Engine): PASS
9113 09:31:26.278895 TX OE : PASS
9114 09:31:26.278998 All Pass.
9115 09:31:26.279097
9116 09:31:26.279174 CH 0, Rank 1
9117 09:31:26.282065 SW Impedance : PASS
9118 09:31:26.285489 DUTY Scan : NO K
9119 09:31:26.285573 ZQ Calibration : PASS
9120 09:31:26.288563 Jitter Meter : NO K
9121 09:31:26.288660 CBT Training : PASS
9122 09:31:26.292113 Write leveling : PASS
9123 09:31:26.295370 RX DQS gating : PASS
9124 09:31:26.295456 RX DQ/DQS(RDDQC) : PASS
9125 09:31:26.298551 TX DQ/DQS : PASS
9126 09:31:26.302067 RX DATLAT : PASS
9127 09:31:26.302168 RX DQ/DQS(Engine): PASS
9128 09:31:26.305466 TX OE : PASS
9129 09:31:26.305551 All Pass.
9130 09:31:26.305617
9131 09:31:26.309125 CH 1, Rank 0
9132 09:31:26.309209 SW Impedance : PASS
9133 09:31:26.312054 DUTY Scan : NO K
9134 09:31:26.315509 ZQ Calibration : PASS
9135 09:31:26.315593 Jitter Meter : NO K
9136 09:31:26.319115 CBT Training : PASS
9137 09:31:26.322194 Write leveling : PASS
9138 09:31:26.322309 RX DQS gating : PASS
9139 09:31:26.325621 RX DQ/DQS(RDDQC) : PASS
9140 09:31:26.329089 TX DQ/DQS : PASS
9141 09:31:26.329173 RX DATLAT : PASS
9142 09:31:26.332150 RX DQ/DQS(Engine): PASS
9143 09:31:26.332233 TX OE : PASS
9144 09:31:26.335554 All Pass.
9145 09:31:26.335663
9146 09:31:26.335754 CH 1, Rank 1
9147 09:31:26.338936 SW Impedance : PASS
9148 09:31:26.339020 DUTY Scan : NO K
9149 09:31:26.341929 ZQ Calibration : PASS
9150 09:31:26.345477 Jitter Meter : NO K
9151 09:31:26.345562 CBT Training : PASS
9152 09:31:26.348495 Write leveling : PASS
9153 09:31:26.351884 RX DQS gating : PASS
9154 09:31:26.351970 RX DQ/DQS(RDDQC) : PASS
9155 09:31:26.355526 TX DQ/DQS : PASS
9156 09:31:26.358691 RX DATLAT : PASS
9157 09:31:26.358775 RX DQ/DQS(Engine): PASS
9158 09:31:26.362092 TX OE : PASS
9159 09:31:26.362176 All Pass.
9160 09:31:26.362245
9161 09:31:26.365198 DramC Write-DBI on
9162 09:31:26.368473 PER_BANK_REFRESH: Hybrid Mode
9163 09:31:26.368613 TX_TRACKING: ON
9164 09:31:26.378471 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9165 09:31:26.385317 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9166 09:31:26.391797 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9167 09:31:26.395315 [FAST_K] Save calibration result to emmc
9168 09:31:26.398479 sync common calibartion params.
9169 09:31:26.401951 sync cbt_mode0:1, 1:1
9170 09:31:26.405067 dram_init: ddr_geometry: 2
9171 09:31:26.405152 dram_init: ddr_geometry: 2
9172 09:31:26.408468 dram_init: ddr_geometry: 2
9173 09:31:26.411956 0:dram_rank_size:100000000
9174 09:31:26.414922 1:dram_rank_size:100000000
9175 09:31:26.418451 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9176 09:31:26.422041 DFS_SHUFFLE_HW_MODE: ON
9177 09:31:26.425026 dramc_set_vcore_voltage set vcore to 725000
9178 09:31:26.428536 Read voltage for 1600, 0
9179 09:31:26.428667 Vio18 = 0
9180 09:31:26.428734 Vcore = 725000
9181 09:31:26.432134 Vdram = 0
9182 09:31:26.432221 Vddq = 0
9183 09:31:26.432289 Vmddr = 0
9184 09:31:26.435131 switch to 3200 Mbps bootup
9185 09:31:26.435239 [DramcRunTimeConfig]
9186 09:31:26.438678 PHYPLL
9187 09:31:26.438762 DPM_CONTROL_AFTERK: ON
9188 09:31:26.441741 PER_BANK_REFRESH: ON
9189 09:31:26.445379 REFRESH_OVERHEAD_REDUCTION: ON
9190 09:31:26.445463 CMD_PICG_NEW_MODE: OFF
9191 09:31:26.448354 XRTWTW_NEW_MODE: ON
9192 09:31:26.448439 XRTRTR_NEW_MODE: ON
9193 09:31:26.451867 TX_TRACKING: ON
9194 09:31:26.451951 RDSEL_TRACKING: OFF
9195 09:31:26.455461 DQS Precalculation for DVFS: ON
9196 09:31:26.458481 RX_TRACKING: OFF
9197 09:31:26.458564 HW_GATING DBG: ON
9198 09:31:26.462048 ZQCS_ENABLE_LP4: ON
9199 09:31:26.462132 RX_PICG_NEW_MODE: ON
9200 09:31:26.465116 TX_PICG_NEW_MODE: ON
9201 09:31:26.468337 ENABLE_RX_DCM_DPHY: ON
9202 09:31:26.468422 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9203 09:31:26.472118 DUMMY_READ_FOR_TRACKING: OFF
9204 09:31:26.475402 !!! SPM_CONTROL_AFTERK: OFF
9205 09:31:26.478498 !!! SPM could not control APHY
9206 09:31:26.478583 IMPEDANCE_TRACKING: ON
9207 09:31:26.481995 TEMP_SENSOR: ON
9208 09:31:26.482080 HW_SAVE_FOR_SR: OFF
9209 09:31:26.485453 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9210 09:31:26.488796 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9211 09:31:26.491819 Read ODT Tracking: ON
9212 09:31:26.495205 Refresh Rate DeBounce: ON
9213 09:31:26.495289 DFS_NO_QUEUE_FLUSH: ON
9214 09:31:26.498317 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9215 09:31:26.501825 ENABLE_DFS_RUNTIME_MRW: OFF
9216 09:31:26.505255 DDR_RESERVE_NEW_MODE: ON
9217 09:31:26.505339 MR_CBT_SWITCH_FREQ: ON
9218 09:31:26.508289 =========================
9219 09:31:26.527643 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9220 09:31:26.530553 dram_init: ddr_geometry: 2
9221 09:31:26.548904 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9222 09:31:26.552482 dram_init: dram init end (result: 0)
9223 09:31:26.559075 DRAM-K: Full calibration passed in 24523 msecs
9224 09:31:26.562161 MRC: failed to locate region type 0.
9225 09:31:26.562245 DRAM rank0 size:0x100000000,
9226 09:31:26.565291 DRAM rank1 size=0x100000000
9227 09:31:26.575541 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9228 09:31:26.582352 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9229 09:31:26.588798 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9230 09:31:26.595314 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9231 09:31:26.598830 DRAM rank0 size:0x100000000,
9232 09:31:26.601792 DRAM rank1 size=0x100000000
9233 09:31:26.601874 CBMEM:
9234 09:31:26.605363 IMD: root @ 0xfffff000 254 entries.
9235 09:31:26.608863 IMD: root @ 0xffffec00 62 entries.
9236 09:31:26.611842 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9237 09:31:26.615316 WARNING: RO_VPD is uninitialized or empty.
9238 09:31:26.621873 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9239 09:31:26.629123 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9240 09:31:26.642000 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9241 09:31:26.653197 BS: romstage times (exec / console): total (unknown) / 24021 ms
9242 09:31:26.653310
9243 09:31:26.653402
9244 09:31:26.663205 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9245 09:31:26.666328 ARM64: Exception handlers installed.
9246 09:31:26.669829 ARM64: Testing exception
9247 09:31:26.672915 ARM64: Done test exception
9248 09:31:26.673002 Enumerating buses...
9249 09:31:26.676420 Show all devs... Before device enumeration.
9250 09:31:26.679717 Root Device: enabled 1
9251 09:31:26.683033 CPU_CLUSTER: 0: enabled 1
9252 09:31:26.683119 CPU: 00: enabled 1
9253 09:31:26.686492 Compare with tree...
9254 09:31:26.686577 Root Device: enabled 1
9255 09:31:26.689447 CPU_CLUSTER: 0: enabled 1
9256 09:31:26.693000 CPU: 00: enabled 1
9257 09:31:26.693086 Root Device scanning...
9258 09:31:26.696301 scan_static_bus for Root Device
9259 09:31:26.699840 CPU_CLUSTER: 0 enabled
9260 09:31:26.702863 scan_static_bus for Root Device done
9261 09:31:26.706440 scan_bus: bus Root Device finished in 8 msecs
9262 09:31:26.706525 done
9263 09:31:26.712740 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9264 09:31:26.716171 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9265 09:31:26.723074 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9266 09:31:26.726041 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9267 09:31:26.729577 Allocating resources...
9268 09:31:26.733159 Reading resources...
9269 09:31:26.736011 Root Device read_resources bus 0 link: 0
9270 09:31:26.736108 DRAM rank0 size:0x100000000,
9271 09:31:26.739594 DRAM rank1 size=0x100000000
9272 09:31:26.743020 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9273 09:31:26.746017 CPU: 00 missing read_resources
9274 09:31:26.749408 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9275 09:31:26.755999 Root Device read_resources bus 0 link: 0 done
9276 09:31:26.756083 Done reading resources.
9277 09:31:26.763031 Show resources in subtree (Root Device)...After reading.
9278 09:31:26.766134 Root Device child on link 0 CPU_CLUSTER: 0
9279 09:31:26.769189 CPU_CLUSTER: 0 child on link 0 CPU: 00
9280 09:31:26.779247 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9281 09:31:26.779369 CPU: 00
9282 09:31:26.782534 Root Device assign_resources, bus 0 link: 0
9283 09:31:26.786303 CPU_CLUSTER: 0 missing set_resources
9284 09:31:26.789468 Root Device assign_resources, bus 0 link: 0 done
9285 09:31:26.793073 Done setting resources.
9286 09:31:26.799358 Show resources in subtree (Root Device)...After assigning values.
9287 09:31:26.802813 Root Device child on link 0 CPU_CLUSTER: 0
9288 09:31:26.806469 CPU_CLUSTER: 0 child on link 0 CPU: 00
9289 09:31:26.815997 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9290 09:31:26.816094 CPU: 00
9291 09:31:26.819454 Done allocating resources.
9292 09:31:26.822791 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9293 09:31:26.826279 Enabling resources...
9294 09:31:26.826362 done.
9295 09:31:26.833036 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9296 09:31:26.833123 Initializing devices...
9297 09:31:26.835947 Root Device init
9298 09:31:26.836029 init hardware done!
9299 09:31:26.839392 0x00000018: ctrlr->caps
9300 09:31:26.842912 52.000 MHz: ctrlr->f_max
9301 09:31:26.842996 0.400 MHz: ctrlr->f_min
9302 09:31:26.845907 0x40ff8080: ctrlr->voltages
9303 09:31:26.845991 sclk: 390625
9304 09:31:26.849445 Bus Width = 1
9305 09:31:26.849528 sclk: 390625
9306 09:31:26.849593 Bus Width = 1
9307 09:31:26.852451 Early init status = 3
9308 09:31:26.859531 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9309 09:31:26.863031 in-header: 03 fc 00 00 01 00 00 00
9310 09:31:26.863119 in-data: 00
9311 09:31:26.869516 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9312 09:31:26.872517 in-header: 03 fd 00 00 00 00 00 00
9313 09:31:26.876052 in-data:
9314 09:31:26.879551 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9315 09:31:26.883061 in-header: 03 fc 00 00 01 00 00 00
9316 09:31:26.886009 in-data: 00
9317 09:31:26.889454 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9318 09:31:26.895247 in-header: 03 fd 00 00 00 00 00 00
9319 09:31:26.898769 in-data:
9320 09:31:26.901807 [SSUSB] Setting up USB HOST controller...
9321 09:31:26.905082 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9322 09:31:26.908495 [SSUSB] phy power-on done.
9323 09:31:26.912112 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9324 09:31:26.918602 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9325 09:31:26.921762 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9326 09:31:26.928581 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9327 09:31:26.935166 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9328 09:31:26.941565 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9329 09:31:26.948094 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9330 09:31:26.955097 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9331 09:31:26.958074 SPM: binary array size = 0x9dc
9332 09:31:26.961622 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9333 09:31:26.968083 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9334 09:31:26.975082 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9335 09:31:26.978068 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9336 09:31:26.984525 configure_display: Starting display init
9337 09:31:27.018470 anx7625_power_on_init: Init interface.
9338 09:31:27.021850 anx7625_disable_pd_protocol: Disabled PD feature.
9339 09:31:27.024946 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9340 09:31:27.053168 anx7625_start_dp_work: Secure OCM version=00
9341 09:31:27.056110 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9342 09:31:27.071030 sp_tx_get_edid_block: EDID Block = 1
9343 09:31:27.173716 Extracted contents:
9344 09:31:27.176755 header: 00 ff ff ff ff ff ff 00
9345 09:31:27.180186 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9346 09:31:27.183663 version: 01 04
9347 09:31:27.187183 basic params: 95 1f 11 78 0a
9348 09:31:27.190081 chroma info: 76 90 94 55 54 90 27 21 50 54
9349 09:31:27.193606 established: 00 00 00
9350 09:31:27.200166 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9351 09:31:27.203709 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9352 09:31:27.210286 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9353 09:31:27.216730 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9354 09:31:27.223652 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9355 09:31:27.226627 extensions: 00
9356 09:31:27.226712 checksum: fb
9357 09:31:27.226780
9358 09:31:27.230119 Manufacturer: IVO Model 57d Serial Number 0
9359 09:31:27.233564 Made week 0 of 2020
9360 09:31:27.233648 EDID version: 1.4
9361 09:31:27.237166 Digital display
9362 09:31:27.240139 6 bits per primary color channel
9363 09:31:27.240227 DisplayPort interface
9364 09:31:27.243493 Maximum image size: 31 cm x 17 cm
9365 09:31:27.246427 Gamma: 220%
9366 09:31:27.246545 Check DPMS levels
9367 09:31:27.250007 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9368 09:31:27.253553 First detailed timing is preferred timing
9369 09:31:27.256500 Established timings supported:
9370 09:31:27.259895 Standard timings supported:
9371 09:31:27.260015 Detailed timings
9372 09:31:27.266562 Hex of detail: 383680a07038204018303c0035ae10000019
9373 09:31:27.269718 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9374 09:31:27.276665 0780 0798 07c8 0820 hborder 0
9375 09:31:27.279776 0438 043b 0447 0458 vborder 0
9376 09:31:27.283272 -hsync -vsync
9377 09:31:27.283391 Did detailed timing
9378 09:31:27.286789 Hex of detail: 000000000000000000000000000000000000
9379 09:31:27.290262 Manufacturer-specified data, tag 0
9380 09:31:27.296590 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9381 09:31:27.296725 ASCII string: InfoVision
9382 09:31:27.303192 Hex of detail: 000000fe00523134304e574635205248200a
9383 09:31:27.306315 ASCII string: R140NWF5 RH
9384 09:31:27.306441 Checksum
9385 09:31:27.306542 Checksum: 0xfb (valid)
9386 09:31:27.313090 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9387 09:31:27.316563 DSI data_rate: 832800000 bps
9388 09:31:27.319654 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9389 09:31:27.326536 anx7625_parse_edid: pixelclock(138800).
9390 09:31:27.330067 hactive(1920), hsync(48), hfp(24), hbp(88)
9391 09:31:27.333098 vactive(1080), vsync(12), vfp(3), vbp(17)
9392 09:31:27.336523 anx7625_dsi_config: config dsi.
9393 09:31:27.343008 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9394 09:31:27.355618 anx7625_dsi_config: success to config DSI
9395 09:31:27.359057 anx7625_dp_start: MIPI phy setup OK.
9396 09:31:27.362082 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9397 09:31:27.365674 mtk_ddp_mode_set invalid vrefresh 60
9398 09:31:27.368665 main_disp_path_setup
9399 09:31:27.368750 ovl_layer_smi_id_en
9400 09:31:27.372086 ovl_layer_smi_id_en
9401 09:31:27.372170 ccorr_config
9402 09:31:27.372234 aal_config
9403 09:31:27.375669 gamma_config
9404 09:31:27.375752 postmask_config
9405 09:31:27.378619 dither_config
9406 09:31:27.382145 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9407 09:31:27.388745 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9408 09:31:27.392306 Root Device init finished in 553 msecs
9409 09:31:27.392392 CPU_CLUSTER: 0 init
9410 09:31:27.402306 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9411 09:31:27.405310 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9412 09:31:27.408945 APU_MBOX 0x190000b0 = 0x10001
9413 09:31:27.411831 APU_MBOX 0x190001b0 = 0x10001
9414 09:31:27.415263 APU_MBOX 0x190005b0 = 0x10001
9415 09:31:27.418612 APU_MBOX 0x190006b0 = 0x10001
9416 09:31:27.422082 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9417 09:31:27.434617 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9418 09:31:27.447326 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9419 09:31:27.453743 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9420 09:31:27.465071 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9421 09:31:27.474415 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9422 09:31:27.477452 CPU_CLUSTER: 0 init finished in 81 msecs
9423 09:31:27.481017 Devices initialized
9424 09:31:27.484611 Show all devs... After init.
9425 09:31:27.484715 Root Device: enabled 1
9426 09:31:27.487497 CPU_CLUSTER: 0: enabled 1
9427 09:31:27.491082 CPU: 00: enabled 1
9428 09:31:27.494119 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9429 09:31:27.497509 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9430 09:31:27.500932 ELOG: NV offset 0x57f000 size 0x1000
9431 09:31:27.507465 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9432 09:31:27.514023 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9433 09:31:27.517607 ELOG: Event(17) added with size 13 at 2024-06-18 09:30:02 UTC
9434 09:31:27.520921 out: cmd=0x121: 03 db 21 01 00 00 00 00
9435 09:31:27.524810 in-header: 03 3e 00 00 2c 00 00 00
9436 09:31:27.538261 in-data: 00 71 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9437 09:31:27.544715 ELOG: Event(A1) added with size 10 at 2024-06-18 09:30:02 UTC
9438 09:31:27.551411 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9439 09:31:27.558116 ELOG: Event(A0) added with size 9 at 2024-06-18 09:30:02 UTC
9440 09:31:27.561452 elog_add_boot_reason: Logged dev mode boot
9441 09:31:27.564511 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9442 09:31:27.568032 Finalize devices...
9443 09:31:27.568127 Devices finalized
9444 09:31:27.574655 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9445 09:31:27.578094 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9446 09:31:27.581617 in-header: 03 07 00 00 08 00 00 00
9447 09:31:27.584541 in-data: aa e4 47 04 13 02 00 00
9448 09:31:27.588051 Chrome EC: UHEPI supported
9449 09:31:27.594651 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9450 09:31:27.597636 in-header: 03 a9 00 00 08 00 00 00
9451 09:31:27.601048 in-data: 84 60 60 08 00 00 00 00
9452 09:31:27.607538 ELOG: Event(91) added with size 10 at 2024-06-18 09:30:02 UTC
9453 09:31:27.611035 Chrome EC: clear events_b mask to 0x0000000020004000
9454 09:31:27.617516 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9455 09:31:27.621605 in-header: 03 fd 00 00 00 00 00 00
9456 09:31:27.625142 in-data:
9457 09:31:27.628425 BS: BS_WRITE_TABLES entry times (exec / console): 4 / 46 ms
9458 09:31:27.631572 Writing coreboot table at 0xffe64000
9459 09:31:27.638239 0. 000000000010a000-0000000000113fff: RAMSTAGE
9460 09:31:27.641270 1. 0000000040000000-00000000400fffff: RAM
9461 09:31:27.644792 2. 0000000040100000-000000004032afff: RAMSTAGE
9462 09:31:27.647954 3. 000000004032b000-00000000545fffff: RAM
9463 09:31:27.651478 4. 0000000054600000-000000005465ffff: BL31
9464 09:31:27.654813 5. 0000000054660000-00000000ffe63fff: RAM
9465 09:31:27.661622 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9466 09:31:27.664918 7. 0000000100000000-000000023fffffff: RAM
9467 09:31:27.667919 Passing 5 GPIOs to payload:
9468 09:31:27.671463 NAME | PORT | POLARITY | VALUE
9469 09:31:27.677918 EC in RW | 0x000000aa | low | undefined
9470 09:31:27.681580 EC interrupt | 0x00000005 | low | undefined
9471 09:31:27.684459 TPM interrupt | 0x000000ab | high | undefined
9472 09:31:27.691479 SD card detect | 0x00000011 | high | undefined
9473 09:31:27.694613 speaker enable | 0x00000093 | high | undefined
9474 09:31:27.698047 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9475 09:31:27.701036 in-header: 03 f9 00 00 02 00 00 00
9476 09:31:27.704494 in-data: 02 00
9477 09:31:27.708031 ADC[4]: Raw value=901401 ID=7
9478 09:31:27.708126 ADC[3]: Raw value=213179 ID=1
9479 09:31:27.711017 RAM Code: 0x71
9480 09:31:27.714620 ADC[6]: Raw value=74502 ID=0
9481 09:31:27.718070 ADC[5]: Raw value=211703 ID=1
9482 09:31:27.718164 SKU Code: 0x1
9483 09:31:27.724525 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum c1b2
9484 09:31:27.724674 coreboot table: 964 bytes.
9485 09:31:27.727583 IMD ROOT 0. 0xfffff000 0x00001000
9486 09:31:27.731007 IMD SMALL 1. 0xffffe000 0x00001000
9487 09:31:27.734284 RO MCACHE 2. 0xffffc000 0x00001104
9488 09:31:27.737793 CONSOLE 3. 0xfff7c000 0x00080000
9489 09:31:27.741330 FMAP 4. 0xfff7b000 0x00000452
9490 09:31:27.744147 TIME STAMP 5. 0xfff7a000 0x00000910
9491 09:31:27.747772 VBOOT WORK 6. 0xfff66000 0x00014000
9492 09:31:27.751257 RAMOOPS 7. 0xffe66000 0x00100000
9493 09:31:27.754160 COREBOOT 8. 0xffe64000 0x00002000
9494 09:31:27.757621 IMD small region:
9495 09:31:27.761093 IMD ROOT 0. 0xffffec00 0x00000400
9496 09:31:27.764085 VPD 1. 0xffffeb80 0x0000006c
9497 09:31:27.767653 MMC STATUS 2. 0xffffeb60 0x00000004
9498 09:31:27.770943 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9499 09:31:27.777389 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9500 09:31:27.818448 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9501 09:31:27.822019 Checking segment from ROM address 0x40100000
9502 09:31:27.825094 Checking segment from ROM address 0x4010001c
9503 09:31:27.832011 Loading segment from ROM address 0x40100000
9504 09:31:27.832112 code (compression=0)
9505 09:31:27.842192 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9506 09:31:27.848588 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9507 09:31:27.848688 it's not compressed!
9508 09:31:27.855565 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9509 09:31:27.858522 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9510 09:31:27.879217 Loading segment from ROM address 0x4010001c
9511 09:31:27.879327 Entry Point 0x80000000
9512 09:31:27.882631 Loaded segments
9513 09:31:27.885662 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9514 09:31:27.892261 Jumping to boot code at 0x80000000(0xffe64000)
9515 09:31:27.899267 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9516 09:31:27.905761 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9517 09:31:27.913575 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9518 09:31:27.917109 Checking segment from ROM address 0x40100000
9519 09:31:27.920072 Checking segment from ROM address 0x4010001c
9520 09:31:27.927065 Loading segment from ROM address 0x40100000
9521 09:31:27.927155 code (compression=1)
9522 09:31:27.933523 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9523 09:31:27.943380 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9524 09:31:27.943472 using LZMA
9525 09:31:27.951739 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9526 09:31:27.958600 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9527 09:31:27.962081 Loading segment from ROM address 0x4010001c
9528 09:31:27.962174 Entry Point 0x54601000
9529 09:31:27.965556 Loaded segments
9530 09:31:27.968518 NOTICE: MT8192 bl31_setup
9531 09:31:27.975524 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9532 09:31:27.978696 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9533 09:31:27.982155 WARNING: region 0:
9534 09:31:27.985365 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9535 09:31:27.985493 WARNING: region 1:
9536 09:31:27.991980 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9537 09:31:27.995566 WARNING: region 2:
9538 09:31:27.998637 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9539 09:31:28.002081 WARNING: region 3:
9540 09:31:28.005511 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9541 09:31:28.008498 WARNING: region 4:
9542 09:31:28.015673 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9543 09:31:28.015766 WARNING: region 5:
9544 09:31:28.018833 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 09:31:28.021612 WARNING: region 6:
9546 09:31:28.025242 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 09:31:28.028256 WARNING: region 7:
9548 09:31:28.031606 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9549 09:31:28.038769 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9550 09:31:28.041758 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9551 09:31:28.045109 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9552 09:31:28.051822 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9553 09:31:28.055118 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9554 09:31:28.058512 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9555 09:31:28.065028 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9556 09:31:28.068450 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9557 09:31:28.075161 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9558 09:31:28.078398 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9559 09:31:28.081880 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9560 09:31:28.088668 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9561 09:31:28.091788 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9562 09:31:28.095271 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9563 09:31:28.101808 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9564 09:31:28.105379 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9565 09:31:28.111783 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9566 09:31:28.115416 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9567 09:31:28.118454 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9568 09:31:28.125064 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9569 09:31:28.128415 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9570 09:31:28.132004 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9571 09:31:28.138549 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9572 09:31:28.141563 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9573 09:31:28.148403 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9574 09:31:28.151896 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9575 09:31:28.158200 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9576 09:31:28.161667 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9577 09:31:28.165003 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9578 09:31:28.171569 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9579 09:31:28.174680 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9580 09:31:28.178160 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9581 09:31:28.184759 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9582 09:31:28.188168 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9583 09:31:28.191235 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9584 09:31:28.194661 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9585 09:31:28.201320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9586 09:31:28.204798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9587 09:31:28.207919 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9588 09:31:28.211468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9589 09:31:28.217921 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9590 09:31:28.221480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9591 09:31:28.224969 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9592 09:31:28.227927 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9593 09:31:28.234875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9594 09:31:28.237870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9595 09:31:28.241468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9596 09:31:28.248040 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9597 09:31:28.251548 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9598 09:31:28.254805 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9599 09:31:28.261068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9600 09:31:28.264490 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9601 09:31:28.271119 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9602 09:31:28.274569 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9603 09:31:28.278111 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9604 09:31:28.284820 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9605 09:31:28.287733 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9606 09:31:28.294680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9607 09:31:28.298001 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9608 09:31:28.304578 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9609 09:31:28.307587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9610 09:31:28.314571 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9611 09:31:28.317988 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9612 09:31:28.321076 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9613 09:31:28.327607 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9614 09:31:28.331091 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9615 09:31:28.338067 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9616 09:31:28.341050 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9617 09:31:28.347608 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9618 09:31:28.351097 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9619 09:31:28.354579 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9620 09:31:28.361224 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9621 09:31:28.364283 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9622 09:31:28.371330 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9623 09:31:28.374459 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9624 09:31:28.381054 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9625 09:31:28.384513 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9626 09:31:28.387977 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9627 09:31:28.394867 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9628 09:31:28.398001 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9629 09:31:28.404524 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9630 09:31:28.408055 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9631 09:31:28.414508 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9632 09:31:28.417994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9633 09:31:28.424443 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9634 09:31:28.427908 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9635 09:31:28.430924 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9636 09:31:28.437814 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9637 09:31:28.440896 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9638 09:31:28.447905 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9639 09:31:28.451035 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9640 09:31:28.481866 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9641 09:31:28.482026 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9642 09:31:28.482102 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9643 09:31:28.482167 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9644 09:31:28.482230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9645 09:31:28.482304 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9646 09:31:28.484303 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9647 09:31:28.487807 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9648 09:31:28.490900 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9649 09:31:28.497714 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9650 09:31:28.500958 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9651 09:31:28.504296 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9652 09:31:28.510901 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9653 09:31:28.514478 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9654 09:31:28.520854 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9655 09:31:28.523854 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9656 09:31:28.527418 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9657 09:31:28.534311 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9658 09:31:28.537329 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9659 09:31:28.544315 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9660 09:31:28.547385 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9661 09:31:28.550887 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9662 09:31:28.557519 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9663 09:31:28.561018 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9664 09:31:28.567417 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9665 09:31:28.570891 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9666 09:31:28.574120 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9667 09:31:28.577570 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9668 09:31:28.584227 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9669 09:31:28.587273 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9670 09:31:28.590757 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9671 09:31:28.594307 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9672 09:31:28.600811 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9673 09:31:28.603727 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9674 09:31:28.607151 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9675 09:31:28.614024 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9676 09:31:28.616988 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9677 09:31:28.624006 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9678 09:31:28.627085 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9679 09:31:28.630602 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9680 09:31:28.637028 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9681 09:31:28.640466 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9682 09:31:28.646998 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9683 09:31:28.650544 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9684 09:31:28.653605 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9685 09:31:28.660135 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9686 09:31:28.663602 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9687 09:31:28.670011 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9688 09:31:28.673418 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9689 09:31:28.677329 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9690 09:31:28.683524 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9691 09:31:28.686836 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9692 09:31:28.693340 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9693 09:31:28.696917 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9694 09:31:28.700362 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9695 09:31:28.706969 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9696 09:31:28.710052 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9697 09:31:28.716828 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9698 09:31:28.719875 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9699 09:31:28.723254 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9700 09:31:28.729850 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9701 09:31:28.733362 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9702 09:31:28.736270 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9703 09:31:28.743390 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9704 09:31:28.746371 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9705 09:31:28.753475 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9706 09:31:28.756499 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9707 09:31:28.760138 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9708 09:31:28.766526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9709 09:31:28.769983 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9710 09:31:28.776533 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9711 09:31:28.779643 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9712 09:31:28.783090 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9713 09:31:28.789936 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9714 09:31:28.792922 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9715 09:31:28.796482 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9716 09:31:28.803051 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9717 09:31:28.806501 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9718 09:31:28.813053 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9719 09:31:28.816472 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9720 09:31:28.822989 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9721 09:31:28.826443 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9722 09:31:28.829487 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9723 09:31:28.836658 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9724 09:31:28.839540 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9725 09:31:28.843006 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9726 09:31:28.849992 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9727 09:31:28.853003 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9728 09:31:28.856445 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9729 09:31:28.863058 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9730 09:31:28.866442 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9731 09:31:28.872993 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9732 09:31:28.876478 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9733 09:31:28.879921 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9734 09:31:28.886251 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9735 09:31:28.889990 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9736 09:31:28.896538 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9737 09:31:28.899671 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9738 09:31:28.903219 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9739 09:31:28.909819 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9740 09:31:28.912882 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9741 09:31:28.919550 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9742 09:31:28.922960 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9743 09:31:28.926467 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9744 09:31:28.932968 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9745 09:31:28.936498 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9746 09:31:28.943015 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9747 09:31:28.946561 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9748 09:31:28.953032 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9749 09:31:28.956507 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9750 09:31:28.959401 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9751 09:31:28.966538 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9752 09:31:28.969504 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9753 09:31:28.976452 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9754 09:31:28.979468 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9755 09:31:28.986414 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9756 09:31:28.989358 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9757 09:31:28.992811 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9758 09:31:28.999542 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9759 09:31:29.002781 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9760 09:31:29.009122 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9761 09:31:29.012563 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9762 09:31:29.016169 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9763 09:31:29.022506 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9764 09:31:29.025955 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9765 09:31:29.032458 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9766 09:31:29.036048 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9767 09:31:29.042590 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9768 09:31:29.045520 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9769 09:31:29.049084 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9770 09:31:29.055972 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9771 09:31:29.058924 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9772 09:31:29.065535 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9773 09:31:29.069281 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9774 09:31:29.072270 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9775 09:31:29.079029 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9776 09:31:29.082533 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9777 09:31:29.088922 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9778 09:31:29.092401 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9779 09:31:29.095841 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9780 09:31:29.099050 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9781 09:31:29.105743 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9782 09:31:29.109014 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9783 09:31:29.112025 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9784 09:31:29.118855 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9785 09:31:29.121961 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9786 09:31:29.125559 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9787 09:31:29.131889 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9788 09:31:29.135559 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9789 09:31:29.138545 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9790 09:31:29.145088 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9791 09:31:29.148455 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9792 09:31:29.152077 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9793 09:31:29.158552 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9794 09:31:29.162100 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9795 09:31:29.168723 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9796 09:31:29.171913 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9797 09:31:29.175384 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9798 09:31:29.181942 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9799 09:31:29.185305 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9800 09:31:29.188794 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9801 09:31:29.195280 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9802 09:31:29.198636 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9803 09:31:29.202063 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9804 09:31:29.208732 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9805 09:31:29.211617 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9806 09:31:29.218680 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9807 09:31:29.221619 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9808 09:31:29.225088 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9809 09:31:29.232355 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9810 09:31:29.235502 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9811 09:31:29.238433 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9812 09:31:29.244885 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9813 09:31:29.248390 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9814 09:31:29.252018 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9815 09:31:29.258468 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9816 09:31:29.261610 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9817 09:31:29.268174 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9818 09:31:29.271452 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9819 09:31:29.274731 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9820 09:31:29.278209 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9821 09:31:29.281339 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9822 09:31:29.288399 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9823 09:31:29.291429 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9824 09:31:29.295050 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9825 09:31:29.297904 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9826 09:31:29.304822 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9827 09:31:29.308269 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9828 09:31:29.311306 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9829 09:31:29.314760 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9830 09:31:29.321517 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9831 09:31:29.324889 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9832 09:31:29.331524 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9833 09:31:29.334976 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9834 09:31:29.337800 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9835 09:31:29.344876 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9836 09:31:29.348165 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9837 09:31:29.354782 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9838 09:31:29.358150 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9839 09:31:29.361272 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9840 09:31:29.367762 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9841 09:31:29.371356 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9842 09:31:29.377918 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9843 09:31:29.381539 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9844 09:31:29.388055 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9845 09:31:29.391155 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9846 09:31:29.394542 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9847 09:31:29.400975 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9848 09:31:29.404582 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9849 09:31:29.411265 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9850 09:31:29.414329 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9851 09:31:29.417816 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9852 09:31:29.424239 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9853 09:31:29.427564 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9854 09:31:29.431116 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9855 09:31:29.437520 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9856 09:31:29.441024 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9857 09:31:29.447852 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9858 09:31:29.450821 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9859 09:31:29.457691 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9860 09:31:29.461110 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9861 09:31:29.464232 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9862 09:31:29.470732 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9863 09:31:29.474277 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9864 09:31:29.480788 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9865 09:31:29.484110 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9866 09:31:29.487602 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9867 09:31:29.494096 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9868 09:31:29.497485 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9869 09:31:29.503904 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9870 09:31:29.507490 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9871 09:31:29.510620 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9872 09:31:29.517311 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9873 09:31:29.520927 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9874 09:31:29.527304 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9875 09:31:29.530722 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9876 09:31:29.537129 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9877 09:31:29.540603 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9878 09:31:29.544016 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9879 09:31:29.550436 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9880 09:31:29.554114 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9881 09:31:29.560176 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9882 09:31:29.563778 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9883 09:31:29.567307 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9884 09:31:29.573797 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9885 09:31:29.577426 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9886 09:31:29.583791 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9887 09:31:29.587494 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9888 09:31:29.590510 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9889 09:31:29.597050 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9890 09:31:29.600486 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9891 09:31:29.607063 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9892 09:31:29.610533 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9893 09:31:29.616994 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9894 09:31:29.620272 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9895 09:31:29.623665 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9896 09:31:29.630417 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9897 09:31:29.633968 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9898 09:31:29.640371 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9899 09:31:29.643452 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9900 09:31:29.646564 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9901 09:31:29.653880 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9902 09:31:29.656859 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9903 09:31:29.663269 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9904 09:31:29.666495 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9905 09:31:29.670060 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9906 09:31:29.676614 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9907 09:31:29.680343 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9908 09:31:29.686790 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9909 09:31:29.690270 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9910 09:31:29.696872 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9911 09:31:29.699954 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9912 09:31:29.703335 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9913 09:31:29.709973 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9914 09:31:29.713003 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9915 09:31:29.720111 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9916 09:31:29.723377 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9917 09:31:29.729878 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9918 09:31:29.733073 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9919 09:31:29.736341 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9920 09:31:29.743164 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9921 09:31:29.746386 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9922 09:31:29.752984 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9923 09:31:29.756466 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9924 09:31:29.762837 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9925 09:31:29.766490 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9926 09:31:29.772511 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9927 09:31:29.776245 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9928 09:31:29.779262 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9929 09:31:29.785827 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9930 09:31:29.789395 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9931 09:31:29.795916 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9932 09:31:29.799494 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9933 09:31:29.806060 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9934 09:31:29.808961 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9935 09:31:29.815543 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9936 09:31:29.819007 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9937 09:31:29.822538 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9938 09:31:29.828934 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9939 09:31:29.831957 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9940 09:31:29.838970 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9941 09:31:29.842380 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9942 09:31:29.848540 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9943 09:31:29.851901 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9944 09:31:29.858849 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9945 09:31:29.861993 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9946 09:31:29.865507 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9947 09:31:29.871610 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9948 09:31:29.875070 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9949 09:31:29.881756 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9950 09:31:29.885411 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9951 09:31:29.888323 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9952 09:31:29.894856 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9953 09:31:29.898428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9954 09:31:29.904995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9955 09:31:29.908435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9956 09:31:29.914887 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9957 09:31:29.918507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9958 09:31:29.925000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9959 09:31:29.927986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9960 09:31:29.934811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9961 09:31:29.938247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9962 09:31:29.944407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9963 09:31:29.947854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9964 09:31:29.954687 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9965 09:31:29.957735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9966 09:31:29.964298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9967 09:31:29.967818 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9968 09:31:29.974519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9969 09:31:29.977957 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9970 09:31:29.984500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9971 09:31:29.987555 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9972 09:31:29.994380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9973 09:31:29.997500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9974 09:31:30.004012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9975 09:31:30.007518 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9976 09:31:30.013966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9977 09:31:30.017474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9978 09:31:30.023996 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9979 09:31:30.027643 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9980 09:31:30.034198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9981 09:31:30.037186 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9982 09:31:30.043977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9983 09:31:30.047244 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9984 09:31:30.050344 INFO: [APUAPC] vio 0
9985 09:31:30.053676 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9986 09:31:30.060452 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9987 09:31:30.063547 INFO: [APUAPC] D0_APC_0: 0x400510
9988 09:31:30.063661 INFO: [APUAPC] D0_APC_1: 0x0
9989 09:31:30.067090 INFO: [APUAPC] D0_APC_2: 0x1540
9990 09:31:30.070143 INFO: [APUAPC] D0_APC_3: 0x0
9991 09:31:30.073516 INFO: [APUAPC] D1_APC_0: 0xffffffff
9992 09:31:30.076972 INFO: [APUAPC] D1_APC_1: 0xffffffff
9993 09:31:30.080361 INFO: [APUAPC] D1_APC_2: 0x3fffff
9994 09:31:30.083445 INFO: [APUAPC] D1_APC_3: 0x0
9995 09:31:30.087102 INFO: [APUAPC] D2_APC_0: 0xffffffff
9996 09:31:30.090045 INFO: [APUAPC] D2_APC_1: 0xffffffff
9997 09:31:30.093507 INFO: [APUAPC] D2_APC_2: 0x3fffff
9998 09:31:30.096870 INFO: [APUAPC] D2_APC_3: 0x0
9999 09:31:30.100375 INFO: [APUAPC] D3_APC_0: 0xffffffff
10000 09:31:30.103307 INFO: [APUAPC] D3_APC_1: 0xffffffff
10001 09:31:30.106846 INFO: [APUAPC] D3_APC_2: 0x3fffff
10002 09:31:30.109920 INFO: [APUAPC] D3_APC_3: 0x0
10003 09:31:30.113518 INFO: [APUAPC] D4_APC_0: 0xffffffff
10004 09:31:30.116383 INFO: [APUAPC] D4_APC_1: 0xffffffff
10005 09:31:30.120065 INFO: [APUAPC] D4_APC_2: 0x3fffff
10006 09:31:30.123078 INFO: [APUAPC] D4_APC_3: 0x0
10007 09:31:30.126613 INFO: [APUAPC] D5_APC_0: 0xffffffff
10008 09:31:30.129612 INFO: [APUAPC] D5_APC_1: 0xffffffff
10009 09:31:30.133112 INFO: [APUAPC] D5_APC_2: 0x3fffff
10010 09:31:30.136708 INFO: [APUAPC] D5_APC_3: 0x0
10011 09:31:30.139750 INFO: [APUAPC] D6_APC_0: 0xffffffff
10012 09:31:30.142988 INFO: [APUAPC] D6_APC_1: 0xffffffff
10013 09:31:30.146425 INFO: [APUAPC] D6_APC_2: 0x3fffff
10014 09:31:30.149942 INFO: [APUAPC] D6_APC_3: 0x0
10015 09:31:30.153285 INFO: [APUAPC] D7_APC_0: 0xffffffff
10016 09:31:30.156115 INFO: [APUAPC] D7_APC_1: 0xffffffff
10017 09:31:30.159601 INFO: [APUAPC] D7_APC_2: 0x3fffff
10018 09:31:30.162908 INFO: [APUAPC] D7_APC_3: 0x0
10019 09:31:30.166374 INFO: [APUAPC] D8_APC_0: 0xffffffff
10020 09:31:30.169854 INFO: [APUAPC] D8_APC_1: 0xffffffff
10021 09:31:30.172913 INFO: [APUAPC] D8_APC_2: 0x3fffff
10022 09:31:30.176368 INFO: [APUAPC] D8_APC_3: 0x0
10023 09:31:30.179918 INFO: [APUAPC] D9_APC_0: 0xffffffff
10024 09:31:30.182939 INFO: [APUAPC] D9_APC_1: 0xffffffff
10025 09:31:30.186341 INFO: [APUAPC] D9_APC_2: 0x3fffff
10026 09:31:30.189943 INFO: [APUAPC] D9_APC_3: 0x0
10027 09:31:30.192996 INFO: [APUAPC] D10_APC_0: 0xffffffff
10028 09:31:30.196450 INFO: [APUAPC] D10_APC_1: 0xffffffff
10029 09:31:30.199420 INFO: [APUAPC] D10_APC_2: 0x3fffff
10030 09:31:30.202972 INFO: [APUAPC] D10_APC_3: 0x0
10031 09:31:30.206426 INFO: [APUAPC] D11_APC_0: 0xffffffff
10032 09:31:30.209428 INFO: [APUAPC] D11_APC_1: 0xffffffff
10033 09:31:30.212989 INFO: [APUAPC] D11_APC_2: 0x3fffff
10034 09:31:30.216007 INFO: [APUAPC] D11_APC_3: 0x0
10035 09:31:30.219453 INFO: [APUAPC] D12_APC_0: 0xffffffff
10036 09:31:30.222973 INFO: [APUAPC] D12_APC_1: 0xffffffff
10037 09:31:30.226121 INFO: [APUAPC] D12_APC_2: 0x3fffff
10038 09:31:30.229407 INFO: [APUAPC] D12_APC_3: 0x0
10039 09:31:30.232446 INFO: [APUAPC] D13_APC_0: 0xffffffff
10040 09:31:30.235964 INFO: [APUAPC] D13_APC_1: 0xffffffff
10041 09:31:30.239458 INFO: [APUAPC] D13_APC_2: 0x3fffff
10042 09:31:30.242926 INFO: [APUAPC] D13_APC_3: 0x0
10043 09:31:30.246185 INFO: [APUAPC] D14_APC_0: 0xffffffff
10044 09:31:30.249473 INFO: [APUAPC] D14_APC_1: 0xffffffff
10045 09:31:30.252982 INFO: [APUAPC] D14_APC_2: 0x3fffff
10046 09:31:30.255968 INFO: [APUAPC] D14_APC_3: 0x0
10047 09:31:30.259449 INFO: [APUAPC] D15_APC_0: 0xffffffff
10048 09:31:30.262791 INFO: [APUAPC] D15_APC_1: 0xffffffff
10049 09:31:30.265917 INFO: [APUAPC] D15_APC_2: 0x3fffff
10050 09:31:30.269235 INFO: [APUAPC] D15_APC_3: 0x0
10051 09:31:30.272740 INFO: [APUAPC] APC_CON: 0x4
10052 09:31:30.272827 INFO: [NOCDAPC] D0_APC_0: 0x0
10053 09:31:30.275688 INFO: [NOCDAPC] D0_APC_1: 0x0
10054 09:31:30.279225 INFO: [NOCDAPC] D1_APC_0: 0x0
10055 09:31:30.282825 INFO: [NOCDAPC] D1_APC_1: 0xfff
10056 09:31:30.286293 INFO: [NOCDAPC] D2_APC_0: 0x0
10057 09:31:30.289087 INFO: [NOCDAPC] D2_APC_1: 0xfff
10058 09:31:30.292746 INFO: [NOCDAPC] D3_APC_0: 0x0
10059 09:31:30.295734 INFO: [NOCDAPC] D3_APC_1: 0xfff
10060 09:31:30.299207 INFO: [NOCDAPC] D4_APC_0: 0x0
10061 09:31:30.302610 INFO: [NOCDAPC] D4_APC_1: 0xfff
10062 09:31:30.302704 INFO: [NOCDAPC] D5_APC_0: 0x0
10063 09:31:30.305782 INFO: [NOCDAPC] D5_APC_1: 0xfff
10064 09:31:30.309406 INFO: [NOCDAPC] D6_APC_0: 0x0
10065 09:31:30.312349 INFO: [NOCDAPC] D6_APC_1: 0xfff
10066 09:31:30.315816 INFO: [NOCDAPC] D7_APC_0: 0x0
10067 09:31:30.319368 INFO: [NOCDAPC] D7_APC_1: 0xfff
10068 09:31:30.322363 INFO: [NOCDAPC] D8_APC_0: 0x0
10069 09:31:30.325833 INFO: [NOCDAPC] D8_APC_1: 0xfff
10070 09:31:30.328892 INFO: [NOCDAPC] D9_APC_0: 0x0
10071 09:31:30.332427 INFO: [NOCDAPC] D9_APC_1: 0xfff
10072 09:31:30.332585 INFO: [NOCDAPC] D10_APC_0: 0x0
10073 09:31:30.335912 INFO: [NOCDAPC] D10_APC_1: 0xfff
10074 09:31:30.338924 INFO: [NOCDAPC] D11_APC_0: 0x0
10075 09:31:30.342525 INFO: [NOCDAPC] D11_APC_1: 0xfff
10076 09:31:30.346049 INFO: [NOCDAPC] D12_APC_0: 0x0
10077 09:31:30.348971 INFO: [NOCDAPC] D12_APC_1: 0xfff
10078 09:31:30.352277 INFO: [NOCDAPC] D13_APC_0: 0x0
10079 09:31:30.356054 INFO: [NOCDAPC] D13_APC_1: 0xfff
10080 09:31:30.359330 INFO: [NOCDAPC] D14_APC_0: 0x0
10081 09:31:30.362210 INFO: [NOCDAPC] D14_APC_1: 0xfff
10082 09:31:30.365668 INFO: [NOCDAPC] D15_APC_0: 0x0
10083 09:31:30.369011 INFO: [NOCDAPC] D15_APC_1: 0xfff
10084 09:31:30.372238 INFO: [NOCDAPC] APC_CON: 0x4
10085 09:31:30.375486 INFO: [APUAPC] set_apusys_apc done
10086 09:31:30.378896 INFO: [DEVAPC] devapc_init done
10087 09:31:30.382269 INFO: GICv3 without legacy support detected.
10088 09:31:30.385858 INFO: ARM GICv3 driver initialized in EL3
10089 09:31:30.388967 INFO: Maximum SPI INTID supported: 639
10090 09:31:30.392391 INFO: BL31: Initializing runtime services
10091 09:31:30.398889 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10092 09:31:30.402480 INFO: SPM: enable CPC mode
10093 09:31:30.405493 INFO: mcdi ready for mcusys-off-idle and system suspend
10094 09:31:30.412055 INFO: BL31: Preparing for EL3 exit to normal world
10095 09:31:30.415572 INFO: Entry point address = 0x80000000
10096 09:31:30.418958 INFO: SPSR = 0x8
10097 09:31:30.423486
10098 09:31:30.423580
10099 09:31:30.423648
10100 09:31:30.426649 Starting depthcharge on Spherion...
10101 09:31:30.426738
10102 09:31:30.426805 Wipe memory regions:
10103 09:31:30.426867
10104 09:31:30.427474 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10105 09:31:30.427576 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10106 09:31:30.427665 Setting prompt string to ['asurada:']
10107 09:31:30.427748 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10108 09:31:30.430155 [0x00000040000000, 0x00000054600000)
10109 09:31:30.551831
10110 09:31:30.552031 [0x00000054660000, 0x00000080000000)
10111 09:31:30.812623
10112 09:31:30.812806 [0x000000821a7280, 0x000000ffe64000)
10113 09:31:31.557550
10114 09:31:31.557774 [0x00000100000000, 0x00000240000000)
10115 09:31:33.447560
10116 09:31:33.450978 Initializing XHCI USB controller at 0x11200000.
10117 09:31:34.488949
10118 09:31:34.492243 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10119 09:31:34.492358
10120 09:31:34.492426
10121 09:31:34.492715 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10123 09:31:34.593092 asurada: tftpboot 192.168.201.1 14407671/tftp-deploy-gyn3kd_t/kernel/image.itb 14407671/tftp-deploy-gyn3kd_t/kernel/cmdline
10124 09:31:34.593277 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10125 09:31:34.593389 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10126 09:31:34.597708 tftpboot 192.168.201.1 14407671/tftp-deploy-gyn3kd_t/kernel/image.itp-deploy-gyn3kd_t/kernel/cmdline
10127 09:31:34.597793
10128 09:31:34.597858 Waiting for link
10129 09:31:34.755957
10130 09:31:34.756107 R8152: Initializing
10131 09:31:34.756194
10132 09:31:34.759029 Version 9 (ocp_data = 6010)
10133 09:31:34.759126
10134 09:31:34.762041 R8152: Done initializing
10135 09:31:34.762127
10136 09:31:34.762192 Adding net device
10137 09:31:36.637067
10138 09:31:36.637217 done.
10139 09:31:36.637287
10140 09:31:36.637347 MAC: 00:e0:4c:72:2d:d6
10141 09:31:36.637406
10142 09:31:36.640484 Sending DHCP discover... done.
10143 09:31:36.640592
10144 09:31:36.643983 Waiting for reply... done.
10145 09:31:36.644122
10146 09:31:36.647059 Sending DHCP request... done.
10147 09:31:36.647141
10148 09:31:36.647205 Waiting for reply... done.
10149 09:31:36.647264
10150 09:31:36.650629 My ip is 192.168.201.21
10151 09:31:36.650711
10152 09:31:36.653983 The DHCP server ip is 192.168.201.1
10153 09:31:36.654065
10154 09:31:36.656925 TFTP server IP predefined by user: 192.168.201.1
10155 09:31:36.657008
10156 09:31:36.663552 Bootfile predefined by user: 14407671/tftp-deploy-gyn3kd_t/kernel/image.itb
10157 09:31:36.663635
10158 09:31:36.667071 Sending tftp read request... done.
10159 09:31:36.667153
10160 09:31:36.670457 Waiting for the transfer...
10161 09:31:36.670540
10162 09:31:36.962435 00000000 ################################################################
10163 09:31:36.962656
10164 09:31:37.248888 00080000 ################################################################
10165 09:31:37.249032
10166 09:31:37.526069 00100000 ################################################################
10167 09:31:37.526219
10168 09:31:37.807814 00180000 ################################################################
10169 09:31:37.807992
10170 09:31:38.092115 00200000 ################################################################
10171 09:31:38.092258
10172 09:31:38.374897 00280000 ################################################################
10173 09:31:38.375046
10174 09:31:38.668819 00300000 ################################################################
10175 09:31:38.668970
10176 09:31:38.938575 00380000 ################################################################
10177 09:31:38.938721
10178 09:31:39.232275 00400000 ################################################################
10179 09:31:39.232424
10180 09:31:39.511935 00480000 ################################################################
10181 09:31:39.512115
10182 09:31:39.791762 00500000 ################################################################
10183 09:31:39.791913
10184 09:31:40.064604 00580000 ################################################################
10185 09:31:40.064775
10186 09:31:40.348333 00600000 ################################################################
10187 09:31:40.348516
10188 09:31:40.619859 00680000 ################################################################
10189 09:31:40.620012
10190 09:31:40.875705 00700000 ################################################################
10191 09:31:40.875881
10192 09:31:41.130612 00780000 ################################################################
10193 09:31:41.130833
10194 09:31:41.385288 00800000 ################################################################
10195 09:31:41.385432
10196 09:31:41.639232 00880000 ################################################################
10197 09:31:41.639417
10198 09:31:41.903964 00900000 ################################################################
10199 09:31:41.904112
10200 09:31:42.183652 00980000 ################################################################
10201 09:31:42.183801
10202 09:31:42.429551 00a00000 ################################################################
10203 09:31:42.429741
10204 09:31:42.707597 00a80000 ################################################################
10205 09:31:42.707754
10206 09:31:42.964485 00b00000 ################################################################
10207 09:31:42.964640
10208 09:31:43.243918 00b80000 ################################################################
10209 09:31:43.244068
10210 09:31:43.500699 00c00000 ################################################################
10211 09:31:43.500854
10212 09:31:43.756769 00c80000 ################################################################
10213 09:31:43.756913
10214 09:31:44.037053 00d00000 ################################################################
10215 09:31:44.037202
10216 09:31:44.331567 00d80000 ################################################################
10217 09:31:44.331707
10218 09:31:44.597190 00e00000 ################################################################
10219 09:31:44.597389
10220 09:31:44.851061 00e80000 ################################################################
10221 09:31:44.851212
10222 09:31:45.125069 00f00000 ################################################################
10223 09:31:45.125223
10224 09:31:45.394725 00f80000 ################################################################
10225 09:31:45.394884
10226 09:31:45.665877 01000000 ################################################################
10227 09:31:45.666044
10228 09:31:45.926006 01080000 ################################################################
10229 09:31:45.926163
10230 09:31:46.169547 01100000 ################################################################
10231 09:31:46.169706
10232 09:31:46.444858 01180000 ################################################################
10233 09:31:46.445042
10234 09:31:46.732586 01200000 ################################################################
10235 09:31:46.732742
10236 09:31:47.004866 01280000 ################################################################
10237 09:31:47.005048
10238 09:31:47.304428 01300000 ################################################################
10239 09:31:47.304658
10240 09:31:47.605192 01380000 ################################################################
10241 09:31:47.605346
10242 09:31:47.866546 01400000 ################################################################
10243 09:31:47.866698
10244 09:31:48.123016 01480000 ################################################################
10245 09:31:48.123203
10246 09:31:48.410929 01500000 ################################################################
10247 09:31:48.411162
10248 09:31:48.680028 01580000 ################################################################
10249 09:31:48.680185
10250 09:31:48.941144 01600000 ################################################################
10251 09:31:48.941303
10252 09:31:49.227520 01680000 ################################################################
10253 09:31:49.227703
10254 09:31:49.505817 01700000 ################################################################
10255 09:31:49.505977
10256 09:31:49.763436 01780000 ################################################################
10257 09:31:49.763573
10258 09:31:50.038920 01800000 ################################################################
10259 09:31:50.039058
10260 09:31:50.296941 01880000 ################################################################
10261 09:31:50.297097
10262 09:31:50.556405 01900000 ################################################################
10263 09:31:50.556584
10264 09:31:50.807611 01980000 ################################################################
10265 09:31:50.807773
10266 09:31:51.056483 01a00000 ################################################################
10267 09:31:51.056679
10268 09:31:51.310444 01a80000 ################################################################
10269 09:31:51.310596
10270 09:31:51.559296 01b00000 ################################################################
10271 09:31:51.559448
10272 09:31:51.814116 01b80000 ################################################################
10273 09:31:51.814268
10274 09:31:52.093496 01c00000 ################################################################
10275 09:31:52.093656
10276 09:31:52.344399 01c80000 ################################################################
10277 09:31:52.344601
10278 09:31:52.594447 01d00000 ################################################################
10279 09:31:52.594629
10280 09:31:52.842756 01d80000 ################################################################
10281 09:31:52.842940
10282 09:31:53.063983 01e00000 ########################################################## done.
10283 09:31:53.064167
10284 09:31:53.067152 The bootfile was 31925250 bytes long.
10285 09:31:53.067234
10286 09:31:53.070631 Sending tftp read request... done.
10287 09:31:53.070726
10288 09:31:53.073864 Waiting for the transfer...
10289 09:31:53.073973
10290 09:31:53.074065 00000000 # done.
10291 09:31:53.074167
10292 09:31:53.083851 Command line loaded dynamically from TFTP file: 14407671/tftp-deploy-gyn3kd_t/kernel/cmdline
10293 09:31:53.083970
10294 09:31:53.103648 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407671/extract-nfsrootfs-tqnv2l7u,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10295 09:31:53.103785
10296 09:31:53.106627 Loading FIT.
10297 09:31:53.106731
10298 09:31:53.110256 Image ramdisk-1 has 18749230 bytes.
10299 09:31:53.110374
10300 09:31:53.110481 Image fdt-1 has 47258 bytes.
10301 09:31:53.110584
10302 09:31:53.113385 Image kernel-1 has 13126726 bytes.
10303 09:31:53.113467
10304 09:31:53.123331 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10305 09:31:53.123445
10306 09:31:53.140181 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10307 09:31:53.140277
10308 09:31:53.146307 Choosing best match conf-1 for compat google,spherion-rev2.
10309 09:31:53.150357
10310 09:31:53.154934 Connected to device vid:did:rid of 1ae0:0028:00
10311 09:31:53.161892
10312 09:31:53.165429 tpm_get_response: command 0x17b, return code 0x0
10313 09:31:53.165535
10314 09:31:53.168636 ec_init: CrosEC protocol v3 supported (256, 248)
10315 09:31:53.173311
10316 09:31:53.176358 tpm_cleanup: add release locality here.
10317 09:31:53.176460
10318 09:31:53.176580 Shutting down all USB controllers.
10319 09:31:53.179916
10320 09:31:53.179994 Removing current net device
10321 09:31:53.180058
10322 09:31:53.186407 Exiting depthcharge with code 4 at timestamp: 52092870
10323 09:31:53.186567
10324 09:31:53.189823 LZMA decompressing kernel-1 to 0x821a6718
10325 09:31:53.189935
10326 09:31:53.193233 LZMA decompressing kernel-1 to 0x40000000
10327 09:31:54.810795
10328 09:31:54.810976 jumping to kernel
10329 09:31:54.811785 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10330 09:31:54.811887 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10331 09:31:54.811967 Setting prompt string to ['Linux version [0-9]']
10332 09:31:54.812036 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10333 09:31:54.812103 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10334 09:31:54.892615
10335 09:31:54.896191 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10336 09:31:54.899474 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10337 09:31:54.899647 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10338 09:31:54.899752 Setting prompt string to []
10339 09:31:54.899862 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10340 09:31:54.899972 Using line separator: #'\n'#
10341 09:31:54.900062 No login prompt set.
10342 09:31:54.900157 Parsing kernel messages
10343 09:31:54.900244 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10344 09:31:54.900411 [login-action] Waiting for messages, (timeout 00:04:02)
10345 09:31:54.900510 Waiting using forced prompt support (timeout 00:02:01)
10346 09:31:54.919214 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
10347 09:31:54.922790 [ 0.000000] random: crng init done
10348 09:31:54.929411 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10349 09:31:54.932451 [ 0.000000] efi: UEFI not found.
10350 09:31:54.939044 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10351 09:31:54.945931 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10352 09:31:54.955716 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10353 09:31:54.965737 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10354 09:31:54.972653 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10355 09:31:54.979252 [ 0.000000] printk: bootconsole [mtk8250] enabled
10356 09:31:54.985968 [ 0.000000] NUMA: No NUMA configuration found
10357 09:31:54.991923 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10358 09:31:54.995605 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10359 09:31:54.998772 [ 0.000000] Zone ranges:
10360 09:31:55.005396 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10361 09:31:55.009003 [ 0.000000] DMA32 empty
10362 09:31:55.015307 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10363 09:31:55.018670 [ 0.000000] Movable zone start for each node
10364 09:31:55.022259 [ 0.000000] Early memory node ranges
10365 09:31:55.028661 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10366 09:31:55.035427 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10367 09:31:55.042006 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10368 09:31:55.048726 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10369 09:31:55.051737 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10370 09:31:55.058494 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10371 09:31:55.117413 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10372 09:31:55.123849 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10373 09:31:55.130820 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10374 09:31:55.133966 [ 0.000000] psci: probing for conduit method from DT.
10375 09:31:55.140501 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10376 09:31:55.143765 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10377 09:31:55.150392 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10378 09:31:55.153874 [ 0.000000] psci: SMC Calling Convention v1.2
10379 09:31:55.160520 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10380 09:31:55.163583 [ 0.000000] Detected VIPT I-cache on CPU0
10381 09:31:55.170184 [ 0.000000] CPU features: detected: GIC system register CPU interface
10382 09:31:55.176655 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10383 09:31:55.183362 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10384 09:31:55.189903 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10385 09:31:55.200178 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10386 09:31:55.206636 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10387 09:31:55.210143 [ 0.000000] alternatives: applying boot alternatives
10388 09:31:55.216427 [ 0.000000] Fallback order for Node 0: 0
10389 09:31:55.222969 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10390 09:31:55.226443 [ 0.000000] Policy zone: Normal
10391 09:31:55.249880 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407671/extract-nfsrootfs-tqnv2l7u,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10392 09:31:55.259415 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10393 09:31:55.270832 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10394 09:31:55.280803 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10395 09:31:55.287451 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10396 09:31:55.290869 <6>[ 0.000000] software IO TLB: area num 8.
10397 09:31:55.346907 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10398 09:31:55.496926 <6>[ 0.000000] Memory: 7945752K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407016K reserved, 32768K cma-reserved)
10399 09:31:55.503571 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10400 09:31:55.510114 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10401 09:31:55.513167 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10402 09:31:55.519791 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10403 09:31:55.526890 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10404 09:31:55.529887 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10405 09:31:55.539917 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10406 09:31:55.546894 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10407 09:31:55.549819 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10408 09:31:55.558087 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10409 09:31:55.561178 <6>[ 0.000000] GICv3: 608 SPIs implemented
10410 09:31:55.567744 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10411 09:31:55.570878 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10412 09:31:55.574385 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10413 09:31:55.584151 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10414 09:31:55.594219 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10415 09:31:55.607931 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10416 09:31:55.614448 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10417 09:31:55.623124 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10418 09:31:55.636411 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10419 09:31:55.643040 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10420 09:31:55.649867 <6>[ 0.009185] Console: colour dummy device 80x25
10421 09:31:55.660012 <6>[ 0.013945] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10422 09:31:55.666664 <6>[ 0.024387] pid_max: default: 32768 minimum: 301
10423 09:31:55.669890 <6>[ 0.029258] LSM: Security Framework initializing
10424 09:31:55.676494 <6>[ 0.034196] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10425 09:31:55.686356 <6>[ 0.042009] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10426 09:31:55.693019 <6>[ 0.051450] cblist_init_generic: Setting adjustable number of callback queues.
10427 09:31:55.699914 <6>[ 0.058891] cblist_init_generic: Setting shift to 3 and lim to 1.
10428 09:31:55.709944 <6>[ 0.065233] cblist_init_generic: Setting adjustable number of callback queues.
10429 09:31:55.712873 <6>[ 0.072659] cblist_init_generic: Setting shift to 3 and lim to 1.
10430 09:31:55.719508 <6>[ 0.079060] rcu: Hierarchical SRCU implementation.
10431 09:31:55.726124 <6>[ 0.084107] rcu: Max phase no-delay instances is 1000.
10432 09:31:55.733230 <6>[ 0.091141] EFI services will not be available.
10433 09:31:55.736322 <6>[ 0.096128] smp: Bringing up secondary CPUs ...
10434 09:31:55.744127 <6>[ 0.101177] Detected VIPT I-cache on CPU1
10435 09:31:55.750834 <6>[ 0.101248] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10436 09:31:55.757699 <6>[ 0.101279] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10437 09:31:55.760890 <6>[ 0.101620] Detected VIPT I-cache on CPU2
10438 09:31:55.767373 <6>[ 0.101672] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10439 09:31:55.774075 <6>[ 0.101691] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10440 09:31:55.780849 <6>[ 0.101951] Detected VIPT I-cache on CPU3
10441 09:31:55.787455 <6>[ 0.101997] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10442 09:31:55.794183 <6>[ 0.102011] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10443 09:31:55.797353 <6>[ 0.102313] CPU features: detected: Spectre-v4
10444 09:31:55.804342 <6>[ 0.102319] CPU features: detected: Spectre-BHB
10445 09:31:55.807551 <6>[ 0.102324] Detected PIPT I-cache on CPU4
10446 09:31:55.814033 <6>[ 0.102382] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10447 09:31:55.820432 <6>[ 0.102398] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10448 09:31:55.827063 <6>[ 0.102693] Detected PIPT I-cache on CPU5
10449 09:31:55.834211 <6>[ 0.102758] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10450 09:31:55.840401 <6>[ 0.102775] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10451 09:31:55.843950 <6>[ 0.103056] Detected PIPT I-cache on CPU6
10452 09:31:55.850629 <6>[ 0.103122] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10453 09:31:55.857069 <6>[ 0.103138] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10454 09:31:55.863922 <6>[ 0.103436] Detected PIPT I-cache on CPU7
10455 09:31:55.870526 <6>[ 0.103503] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10456 09:31:55.877253 <6>[ 0.103519] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10457 09:31:55.880347 <6>[ 0.103566] smp: Brought up 1 node, 8 CPUs
10458 09:31:55.887101 <6>[ 0.244891] SMP: Total of 8 processors activated.
10459 09:31:55.890295 <6>[ 0.249812] CPU features: detected: 32-bit EL0 Support
10460 09:31:55.900639 <6>[ 0.255175] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10461 09:31:55.906950 <6>[ 0.263975] CPU features: detected: Common not Private translations
10462 09:31:55.910356 <6>[ 0.270451] CPU features: detected: CRC32 instructions
10463 09:31:55.916954 <6>[ 0.275802] CPU features: detected: RCpc load-acquire (LDAPR)
10464 09:31:55.923454 <6>[ 0.281762] CPU features: detected: LSE atomic instructions
10465 09:31:55.929974 <6>[ 0.287543] CPU features: detected: Privileged Access Never
10466 09:31:55.933412 <6>[ 0.293359] CPU features: detected: RAS Extension Support
10467 09:31:55.940092 <6>[ 0.298967] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10468 09:31:55.946864 <6>[ 0.306186] CPU: All CPU(s) started at EL2
10469 09:31:55.953476 <6>[ 0.310530] alternatives: applying system-wide alternatives
10470 09:31:55.961666 <6>[ 0.321326] devtmpfs: initialized
10471 09:31:55.977499 <6>[ 0.330251] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10472 09:31:55.984151 <6>[ 0.340213] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10473 09:31:55.990443 <6>[ 0.348222] pinctrl core: initialized pinctrl subsystem
10474 09:31:55.993667 <6>[ 0.355040] DMI not present or invalid.
10475 09:31:56.000416 <6>[ 0.359452] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10476 09:31:56.010616 <6>[ 0.366316] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10477 09:31:56.017250 <6>[ 0.373905] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10478 09:31:56.027011 <6>[ 0.382125] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10479 09:31:56.030538 <6>[ 0.390366] audit: initializing netlink subsys (disabled)
10480 09:31:56.040707 <5>[ 0.396061] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10481 09:31:56.046922 <6>[ 0.396822] thermal_sys: Registered thermal governor 'step_wise'
10482 09:31:56.053593 <6>[ 0.404028] thermal_sys: Registered thermal governor 'power_allocator'
10483 09:31:56.057170 <6>[ 0.410285] cpuidle: using governor menu
10484 09:31:56.063446 <6>[ 0.421246] NET: Registered PF_QIPCRTR protocol family
10485 09:31:56.070305 <6>[ 0.426736] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10486 09:31:56.073322 <6>[ 0.433839] ASID allocator initialised with 32768 entries
10487 09:31:56.081096 <6>[ 0.440472] Serial: AMBA PL011 UART driver
10488 09:31:56.090351 <4>[ 0.449696] Trying to register duplicate clock ID: 134
10489 09:31:56.150604 <6>[ 0.513489] KASLR enabled
10490 09:31:56.165404 <6>[ 0.521205] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10491 09:31:56.171681 <6>[ 0.528217] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10492 09:31:56.178254 <6>[ 0.534705] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10493 09:31:56.184989 <6>[ 0.541710] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10494 09:31:56.191290 <6>[ 0.548199] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10495 09:31:56.197981 <6>[ 0.555204] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10496 09:31:56.204651 <6>[ 0.561692] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10497 09:31:56.211338 <6>[ 0.568700] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10498 09:31:56.214455 <6>[ 0.576176] ACPI: Interpreter disabled.
10499 09:31:56.223409 <6>[ 0.582678] iommu: Default domain type: Translated
10500 09:31:56.229872 <6>[ 0.587827] iommu: DMA domain TLB invalidation policy: strict mode
10501 09:31:56.232923 <5>[ 0.594487] SCSI subsystem initialized
10502 09:31:56.239945 <6>[ 0.598734] usbcore: registered new interface driver usbfs
10503 09:31:56.246475 <6>[ 0.604465] usbcore: registered new interface driver hub
10504 09:31:56.249562 <6>[ 0.610015] usbcore: registered new device driver usb
10505 09:31:56.256825 <6>[ 0.616180] pps_core: LinuxPPS API ver. 1 registered
10506 09:31:56.266372 <6>[ 0.621376] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10507 09:31:56.269935 <6>[ 0.630719] PTP clock support registered
10508 09:31:56.272932 <6>[ 0.634964] EDAC MC: Ver: 3.0.0
10509 09:31:56.280703 <6>[ 0.640191] FPGA manager framework
10510 09:31:56.287183 <6>[ 0.643868] Advanced Linux Sound Architecture Driver Initialized.
10511 09:31:56.290295 <6>[ 0.650649] vgaarb: loaded
10512 09:31:56.297411 <6>[ 0.653802] clocksource: Switched to clocksource arch_sys_counter
10513 09:31:56.300517 <5>[ 0.660247] VFS: Disk quotas dquot_6.6.0
10514 09:31:56.307239 <6>[ 0.664435] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10515 09:31:56.310367 <6>[ 0.671627] pnp: PnP ACPI: disabled
10516 09:31:56.319114 <6>[ 0.678358] NET: Registered PF_INET protocol family
10517 09:31:56.328443 <6>[ 0.683951] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10518 09:31:56.340060 <6>[ 0.696288] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10519 09:31:56.349982 <6>[ 0.705104] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10520 09:31:56.356681 <6>[ 0.713071] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10521 09:31:56.363482 <6>[ 0.721771] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10522 09:31:56.375683 <6>[ 0.731522] TCP: Hash tables configured (established 65536 bind 65536)
10523 09:31:56.382188 <6>[ 0.738392] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10524 09:31:56.388329 <6>[ 0.745590] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10525 09:31:56.394954 <6>[ 0.753298] NET: Registered PF_UNIX/PF_LOCAL protocol family
10526 09:31:56.401966 <6>[ 0.759445] RPC: Registered named UNIX socket transport module.
10527 09:31:56.405066 <6>[ 0.765598] RPC: Registered udp transport module.
10528 09:31:56.411707 <6>[ 0.770530] RPC: Registered tcp transport module.
10529 09:31:56.418299 <6>[ 0.775462] RPC: Registered tcp NFSv4.1 backchannel transport module.
10530 09:31:56.421279 <6>[ 0.782128] PCI: CLS 0 bytes, default 64
10531 09:31:56.424834 <6>[ 0.786506] Unpacking initramfs...
10532 09:31:56.434958 <6>[ 0.790246] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10533 09:31:56.441269 <6>[ 0.798875] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10534 09:31:56.448296 <6>[ 0.807700] kvm [1]: IPA Size Limit: 40 bits
10535 09:31:56.451411 <6>[ 0.812228] kvm [1]: GICv3: no GICV resource entry
10536 09:31:56.458061 <6>[ 0.817249] kvm [1]: disabling GICv2 emulation
10537 09:31:56.464822 <6>[ 0.821934] kvm [1]: GIC system register CPU interface enabled
10538 09:31:56.468335 <6>[ 0.828099] kvm [1]: vgic interrupt IRQ18
10539 09:31:56.474976 <6>[ 0.833866] kvm [1]: VHE mode initialized successfully
10540 09:31:56.481384 <5>[ 0.840242] Initialise system trusted keyrings
10541 09:31:56.488063 <6>[ 0.845041] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10542 09:31:56.495544 <6>[ 0.855019] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10543 09:31:56.502287 <5>[ 0.861391] NFS: Registering the id_resolver key type
10544 09:31:56.505406 <5>[ 0.866688] Key type id_resolver registered
10545 09:31:56.512146 <5>[ 0.871105] Key type id_legacy registered
10546 09:31:56.518681 <6>[ 0.875388] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10547 09:31:56.525455 <6>[ 0.882308] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10548 09:31:56.531924 <6>[ 0.890009] 9p: Installing v9fs 9p2000 file system support
10549 09:31:56.568414 <5>[ 0.927944] Key type asymmetric registered
10550 09:31:56.571967 <5>[ 0.932274] Asymmetric key parser 'x509' registered
10551 09:31:56.581842 <6>[ 0.937409] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10552 09:31:56.584940 <6>[ 0.945024] io scheduler mq-deadline registered
10553 09:31:56.588395 <6>[ 0.949787] io scheduler kyber registered
10554 09:31:56.607928 <6>[ 0.967368] EINJ: ACPI disabled.
10555 09:31:56.641000 <4>[ 0.994034] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10556 09:31:56.651223 <4>[ 1.004646] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10557 09:31:56.666499 <6>[ 1.025808] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10558 09:31:56.674435 <6>[ 1.033856] printk: console [ttyS0] disabled
10559 09:31:56.702401 <6>[ 1.058487] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10560 09:31:56.709073 <6>[ 1.067958] printk: console [ttyS0] enabled
10561 09:31:56.712159 <6>[ 1.067958] printk: console [ttyS0] enabled
10562 09:31:56.718822 <6>[ 1.076852] printk: bootconsole [mtk8250] disabled
10563 09:31:56.722259 <6>[ 1.076852] printk: bootconsole [mtk8250] disabled
10564 09:31:56.729109 <6>[ 1.087979] SuperH (H)SCI(F) driver initialized
10565 09:31:56.732063 <6>[ 1.093274] msm_serial: driver initialized
10566 09:31:56.746472 <6>[ 1.102349] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10567 09:31:56.756165 <6>[ 1.110894] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10568 09:31:56.762782 <6>[ 1.119436] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10569 09:31:56.772654 <6>[ 1.128064] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10570 09:31:56.779326 <6>[ 1.136771] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10571 09:31:56.789130 <6>[ 1.145486] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10572 09:31:56.799391 <6>[ 1.154027] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10573 09:31:56.805767 <6>[ 1.162831] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10574 09:31:56.815963 <6>[ 1.171376] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10575 09:31:56.827868 <6>[ 1.187394] loop: module loaded
10576 09:31:56.834420 <6>[ 1.193399] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10577 09:31:56.857242 <4>[ 1.216833] mtk-pmic-keys: Failed to locate of_node [id: -1]
10578 09:31:56.863779 <6>[ 1.223527] megasas: 07.719.03.00-rc1
10579 09:31:56.873567 <6>[ 1.233223] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10580 09:31:56.881831 <6>[ 1.241181] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10581 09:31:56.898100 <6>[ 1.257521] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10582 09:31:56.953626 <6>[ 1.306844] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10583 09:31:57.213749 <6>[ 1.573196] Freeing initrd memory: 18304K
10584 09:31:57.225716 <6>[ 1.584991] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10585 09:31:57.236396 <6>[ 1.595830] tun: Universal TUN/TAP device driver, 1.6
10586 09:31:57.239491 <6>[ 1.601927] thunder_xcv, ver 1.0
10587 09:31:57.243171 <6>[ 1.605420] thunder_bgx, ver 1.0
10588 09:31:57.246276 <6>[ 1.608919] nicpf, ver 1.0
10589 09:31:57.256952 <6>[ 1.612962] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10590 09:31:57.259942 <6>[ 1.620439] hns3: Copyright (c) 2017 Huawei Corporation.
10591 09:31:57.263516 <6>[ 1.626026] hclge is initializing
10592 09:31:57.270187 <6>[ 1.629602] e1000: Intel(R) PRO/1000 Network Driver
10593 09:31:57.276716 <6>[ 1.634732] e1000: Copyright (c) 1999-2006 Intel Corporation.
10594 09:31:57.279788 <6>[ 1.640747] e1000e: Intel(R) PRO/1000 Network Driver
10595 09:31:57.286381 <6>[ 1.645963] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10596 09:31:57.293538 <6>[ 1.652151] igb: Intel(R) Gigabit Ethernet Network Driver
10597 09:31:57.300240 <6>[ 1.657801] igb: Copyright (c) 2007-2014 Intel Corporation.
10598 09:31:57.306868 <6>[ 1.663638] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10599 09:31:57.313195 <6>[ 1.670158] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10600 09:31:57.316886 <6>[ 1.676619] sky2: driver version 1.30
10601 09:31:57.323348 <6>[ 1.681589] usbcore: registered new device driver r8152-cfgselector
10602 09:31:57.330256 <6>[ 1.688126] usbcore: registered new interface driver r8152
10603 09:31:57.333242 <6>[ 1.693941] VFIO - User Level meta-driver version: 0.3
10604 09:31:57.343043 <6>[ 1.702295] usbcore: registered new interface driver usb-storage
10605 09:31:57.349289 <6>[ 1.708736] usbcore: registered new device driver onboard-usb-hub
10606 09:31:57.358422 <6>[ 1.717960] mt6397-rtc mt6359-rtc: registered as rtc0
10607 09:31:57.368445 <6>[ 1.723424] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-18T09:30:32 UTC (1718703032)
10608 09:31:57.371574 <6>[ 1.733012] i2c_dev: i2c /dev entries driver
10609 09:31:57.385852 <4>[ 1.745159] cpu cpu0: supply cpu not found, using dummy regulator
10610 09:31:57.392433 <4>[ 1.751585] cpu cpu1: supply cpu not found, using dummy regulator
10611 09:31:57.398969 <4>[ 1.758004] cpu cpu2: supply cpu not found, using dummy regulator
10612 09:31:57.405628 <4>[ 1.764409] cpu cpu3: supply cpu not found, using dummy regulator
10613 09:31:57.412319 <4>[ 1.770803] cpu cpu4: supply cpu not found, using dummy regulator
10614 09:31:57.419067 <4>[ 1.777206] cpu cpu5: supply cpu not found, using dummy regulator
10615 09:31:57.425502 <4>[ 1.783604] cpu cpu6: supply cpu not found, using dummy regulator
10616 09:31:57.431979 <4>[ 1.790017] cpu cpu7: supply cpu not found, using dummy regulator
10617 09:31:57.452011 <6>[ 1.811668] cpu cpu0: EM: created perf domain
10618 09:31:57.455546 <6>[ 1.816607] cpu cpu4: EM: created perf domain
10619 09:31:57.462657 <6>[ 1.822184] sdhci: Secure Digital Host Controller Interface driver
10620 09:31:57.469130 <6>[ 1.828614] sdhci: Copyright(c) Pierre Ossman
10621 09:31:57.475814 <6>[ 1.833576] Synopsys Designware Multimedia Card Interface Driver
10622 09:31:57.482809 <6>[ 1.840223] sdhci-pltfm: SDHCI platform and OF driver helper
10623 09:31:57.485791 <6>[ 1.840319] mmc0: CQHCI version 5.10
10624 09:31:57.492890 <6>[ 1.850152] ledtrig-cpu: registered to indicate activity on CPUs
10625 09:31:57.499268 <6>[ 1.857112] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10626 09:31:57.505856 <6>[ 1.864172] usbcore: registered new interface driver usbhid
10627 09:31:57.509348 <6>[ 1.870007] usbhid: USB HID core driver
10628 09:31:57.515938 <6>[ 1.874185] spi_master spi0: will run message pump with realtime priority
10629 09:31:57.564705 <6>[ 1.917504] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10630 09:31:57.583500 <6>[ 1.932637] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10631 09:31:57.586570 <6>[ 1.943865] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15c14
10632 09:31:57.593496 <6>[ 1.948777] cros-ec-spi spi0.0: Chrome EC device registered
10633 09:31:57.597098 <6>[ 1.958045] mmc0: Command Queue Engine enabled
10634 09:31:57.603825 <6>[ 1.962764] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10635 09:31:57.610433 <6>[ 1.970005] mmcblk0: mmc0:0001 DA4128 116 GiB
10636 09:31:57.620285 <6>[ 1.972216] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10637 09:31:57.623760 <6>[ 1.979087] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10638 09:31:57.630439 <6>[ 1.985086] NET: Registered PF_PACKET protocol family
10639 09:31:57.636945 <6>[ 1.991306] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10640 09:31:57.640457 <6>[ 1.995306] 9pnet: Installing 9P2000 support
10641 09:31:57.646888 <6>[ 2.001103] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10642 09:31:57.650465 <5>[ 2.005011] Key type dns_resolver registered
10643 09:31:57.656928 <6>[ 2.010833] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10644 09:31:57.660506 <6>[ 2.015159] registered taskstats version 1
10645 09:31:57.667040 <5>[ 2.025619] Loading compiled-in X.509 certificates
10646 09:31:57.694653 <4>[ 2.047671] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10647 09:31:57.704810 <4>[ 2.058403] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10648 09:31:57.719152 <6>[ 2.078669] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10649 09:31:57.725785 <6>[ 2.085453] xhci-mtk 11200000.usb: xHCI Host Controller
10650 09:31:57.732411 <6>[ 2.090959] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10651 09:31:57.742550 <6>[ 2.098816] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10652 09:31:57.749153 <6>[ 2.108252] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10653 09:31:57.755714 <6>[ 2.114432] xhci-mtk 11200000.usb: xHCI Host Controller
10654 09:31:57.762418 <6>[ 2.119926] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10655 09:31:57.769018 <6>[ 2.127586] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10656 09:31:57.776060 <6>[ 2.135422] hub 1-0:1.0: USB hub found
10657 09:31:57.779140 <6>[ 2.139447] hub 1-0:1.0: 1 port detected
10658 09:31:57.785811 <6>[ 2.143728] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10659 09:31:57.792892 <6>[ 2.152531] hub 2-0:1.0: USB hub found
10660 09:31:57.796309 <6>[ 2.156553] hub 2-0:1.0: 1 port detected
10661 09:31:57.804426 <6>[ 2.163835] mtk-msdc 11f70000.mmc: Got CD GPIO
10662 09:31:57.816396 <6>[ 2.172759] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10663 09:31:57.826296 <6>[ 2.181141] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10664 09:31:57.833145 <6>[ 2.189482] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10665 09:31:57.843107 <6>[ 2.197823] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10666 09:31:57.849430 <6>[ 2.206161] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10667 09:31:57.859445 <6>[ 2.214499] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10668 09:31:57.866584 <6>[ 2.222838] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10669 09:31:57.876275 <6>[ 2.231177] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10670 09:31:57.883010 <6>[ 2.239518] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10671 09:31:57.892861 <6>[ 2.247856] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10672 09:31:57.899343 <6>[ 2.256194] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10673 09:31:57.909401 <6>[ 2.264536] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10674 09:31:57.916264 <6>[ 2.272874] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10675 09:31:57.926203 <6>[ 2.281211] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10676 09:31:57.932457 <6>[ 2.289550] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10677 09:31:57.939083 <6>[ 2.298245] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10678 09:31:57.945803 <6>[ 2.305432] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10679 09:31:57.952488 <6>[ 2.312190] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10680 09:31:57.962438 <6>[ 2.318980] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10681 09:31:57.969082 <6>[ 2.325931] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10682 09:31:57.975840 <6>[ 2.332791] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10683 09:31:57.985919 <6>[ 2.341921] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10684 09:31:57.995749 <6>[ 2.351043] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10685 09:31:58.005540 <6>[ 2.360337] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10686 09:31:58.015500 <6>[ 2.369803] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10687 09:31:58.022464 <6>[ 2.379270] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10688 09:31:58.032455 <6>[ 2.388390] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10689 09:31:58.041896 <6>[ 2.397857] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10690 09:31:58.052075 <6>[ 2.406976] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10691 09:31:58.062194 <6>[ 2.416270] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10692 09:31:58.071916 <6>[ 2.426430] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10693 09:31:58.081982 <6>[ 2.437670] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10694 09:31:58.088789 <6>[ 2.448239] Trying to probe devices needed for running init ...
10695 09:31:58.099146 <3>[ 2.455498] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10696 09:31:58.209494 <6>[ 2.566087] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10697 09:31:58.362889 <6>[ 2.722529] hub 1-1:1.0: USB hub found
10698 09:31:58.365992 <6>[ 2.726924] hub 1-1:1.0: 4 ports detected
10699 09:31:58.376356 <6>[ 2.736245] hub 1-1:1.0: USB hub found
10700 09:31:58.379871 <6>[ 2.740559] hub 1-1:1.0: 4 ports detected
10701 09:31:58.493802 <6>[ 2.850295] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10702 09:31:58.519507 <6>[ 2.879198] hub 2-1:1.0: USB hub found
10703 09:31:58.522567 <6>[ 2.883657] hub 2-1:1.0: 3 ports detected
10704 09:31:58.534564 <6>[ 2.894159] hub 2-1:1.0: USB hub found
10705 09:31:58.537636 <6>[ 2.898588] hub 2-1:1.0: 3 ports detected
10706 09:31:58.709405 <6>[ 3.066124] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10707 09:31:58.842557 <6>[ 3.202090] hub 1-1.4:1.0: USB hub found
10708 09:31:58.845621 <6>[ 3.206761] hub 1-1.4:1.0: 2 ports detected
10709 09:31:58.857906 <6>[ 3.217736] hub 1-1.4:1.0: USB hub found
10710 09:31:58.861494 <6>[ 3.222266] hub 1-1.4:1.0: 2 ports detected
10711 09:31:58.921937 <6>[ 3.278249] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10712 09:31:59.030058 <6>[ 3.386764] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10713 09:31:59.066248 <4>[ 3.422748] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10714 09:31:59.076307 <4>[ 3.431839] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10715 09:31:59.115711 <6>[ 3.475645] r8152 2-1.3:1.0 eth0: v1.12.13
10716 09:31:59.157540 <6>[ 3.513907] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10717 09:31:59.345237 <6>[ 3.701952] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10718 09:32:00.787572 <6>[ 5.147764] r8152 2-1.3:1.0 eth0: carrier on
10719 09:32:02.977897 <5>[ 5.169905] Sending DHCP requests .., OK
10720 09:32:02.984304 <6>[ 7.342245] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10721 09:32:02.987467 <6>[ 7.350539] IP-Config: Complete:
10722 09:32:03.000878 <6>[ 7.354033] device=eth0, hwaddr=00:e0:4c:72:2d:d6, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10723 09:32:03.007507 <6>[ 7.364740] host=mt8192-asurada-spherion-r0-cbg-1, domain=lava-rack, nis-domain=(none)
10724 09:32:03.014250 <6>[ 7.373358] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10725 09:32:03.020821 <6>[ 7.373367] nameserver0=192.168.201.1
10726 09:32:03.023944 <6>[ 7.385482] clk: Disabling unused clocks
10727 09:32:03.027669 <6>[ 7.391016] ALSA device list:
10728 09:32:03.034129 <6>[ 7.394279] No soundcards found.
10729 09:32:03.041433 <6>[ 7.401548] Freeing unused kernel memory: 8512K
10730 09:32:03.044496 <6>[ 7.406520] Run /init as init process
10731 09:32:03.054635 Loading, please wait...
10732 09:32:03.082448 Starting systemd-udevd version 252.22-1~deb12u1
10733 09:32:03.365909 <6>[ 7.722880] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10734 09:32:03.372879 <6>[ 7.726320] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10735 09:32:03.382918 <6>[ 7.730573] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10736 09:32:03.389147 <6>[ 7.730581] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10737 09:32:03.399280 <6>[ 7.750314] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10738 09:32:03.410667 <6>[ 7.767660] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10739 09:32:03.414209 <6>[ 7.769360] remoteproc remoteproc0: scp is available
10740 09:32:03.424215 <6>[ 7.775750] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10741 09:32:03.427359 <6>[ 7.782249] remoteproc remoteproc0: powering up scp
10742 09:32:03.437147 <4>[ 7.789174] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10743 09:32:03.447312 <6>[ 7.793917] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10744 09:32:03.453970 <3>[ 7.798399] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10745 09:32:03.463507 <3>[ 7.798429] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 09:32:03.470404 <3>[ 7.798437] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10747 09:32:03.480105 <3>[ 7.798619] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10748 09:32:03.487069 <3>[ 7.798625] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10749 09:32:03.493687 <3>[ 7.798639] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 09:32:03.503213 <3>[ 7.798664] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 09:32:03.510067 <3>[ 7.798671] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 09:32:03.519824 <3>[ 7.798747] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 09:32:03.526653 <3>[ 7.798777] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10754 09:32:03.536456 <3>[ 7.798780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 09:32:03.543210 <3>[ 7.798799] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10756 09:32:03.553415 <3>[ 7.798842] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10757 09:32:03.559815 <3>[ 7.798846] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10758 09:32:03.569920 <3>[ 7.798853] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 09:32:03.576256 <3>[ 7.798857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 09:32:03.583044 <3>[ 7.798861] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 09:32:03.592833 <4>[ 7.799028] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10762 09:32:03.599421 <3>[ 7.803301] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10763 09:32:03.605824 <4>[ 7.803339] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10764 09:32:03.615908 <6>[ 7.803762] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10765 09:32:03.622495 <6>[ 7.803770] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10766 09:32:03.632325 <6>[ 7.810552] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10767 09:32:03.638830 <6>[ 7.810564] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10768 09:32:03.645612 <6>[ 7.810567] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10769 09:32:03.655628 <6>[ 7.810570] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10770 09:32:03.662168 <6>[ 7.811519] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10771 09:32:03.668870 <6>[ 7.859913] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10772 09:32:03.671995 <6>[ 7.863110] mc: Linux media interface: v0.10
10773 09:32:03.682066 <6>[ 7.875556] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10774 09:32:03.688805 <4>[ 7.887069] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10775 09:32:03.695093 <4>[ 7.887069] Fallback method does not support PEC.
10776 09:32:03.698783 <6>[ 7.892814] pci_bus 0000:00: root bus resource [bus 00-ff]
10777 09:32:03.708339 <6>[ 7.892832] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10778 09:32:03.718385 <6>[ 7.892834] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10779 09:32:03.722046 <6>[ 7.892898] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10780 09:32:03.731505 <6>[ 7.929879] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10781 09:32:03.738453 <6>[ 7.933423] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10782 09:32:03.751749 <6>[ 8.088536] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10783 09:32:03.758451 <6>[ 8.097817] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10784 09:32:03.764699 <6>[ 8.097878] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10785 09:32:03.771503 <6>[ 8.097893] remoteproc remoteproc0: remote processor scp is now up
10786 09:32:03.777937 <6>[ 8.098012] pci 0000:00:00.0: supports D1 D2
10787 09:32:03.784756 <6>[ 8.098017] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10788 09:32:03.791448 <6>[ 8.099090] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10789 09:32:03.797793 <6>[ 8.099171] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10790 09:32:03.804705 <6>[ 8.099196] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10791 09:32:03.814454 <6>[ 8.099211] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10792 09:32:03.821304 <6>[ 8.099227] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10793 09:32:03.824453 <6>[ 8.099335] pci 0000:01:00.0: supports D1 D2
10794 09:32:03.831118 <6>[ 8.099337] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10795 09:32:03.841063 <6>[ 8.105835] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10796 09:32:03.847476 <6>[ 8.114054] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10797 09:32:03.857282 <6>[ 8.114076] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10798 09:32:03.864047 <6>[ 8.114079] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10799 09:32:03.870537 <6>[ 8.114087] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10800 09:32:03.880560 <6>[ 8.114100] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10801 09:32:03.887492 <6>[ 8.114112] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10802 09:32:03.893895 <6>[ 8.114124] pci 0000:00:00.0: PCI bridge to [bus 01]
10803 09:32:03.900796 <6>[ 8.114129] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10804 09:32:03.907150 <6>[ 8.114257] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10805 09:32:03.913884 <6>[ 8.114729] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10806 09:32:03.920463 <6>[ 8.115381] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10807 09:32:03.927331 <6>[ 8.127154] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10808 09:32:03.933696 <6>[ 8.137788] videodev: Linux video capture interface: v2.00
10809 09:32:03.940363 <6>[ 8.164812] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10810 09:32:03.943896 <6>[ 8.164827] Bluetooth: Core ver 2.22
10811 09:32:03.950381 <6>[ 8.164896] NET: Registered PF_BLUETOOTH protocol family
10812 09:32:03.957226 <6>[ 8.164898] Bluetooth: HCI device and connection manager initialized
10813 09:32:03.963617 <6>[ 8.164915] Bluetooth: HCI socket layer initialized
10814 09:32:03.966973 <6>[ 8.164919] Bluetooth: L2CAP socket layer initialized
10815 09:32:03.973826 <6>[ 8.164925] Bluetooth: SCO socket layer initialized
10816 09:32:03.980113 <5>[ 8.167249] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10817 09:32:03.987004 <5>[ 8.180528] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10818 09:32:03.993507 <6>[ 8.207801] usbcore: registered new interface driver btusb
10819 09:32:04.000135 <6>[ 8.207830] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10820 09:32:04.010207 <4>[ 8.208574] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10821 09:32:04.016662 <3>[ 8.208580] Bluetooth: hci0: Failed to load firmware file (-2)
10822 09:32:04.023457 <3>[ 8.208582] Bluetooth: hci0: Failed to set up firmware (-2)
10823 09:32:04.033236 <4>[ 8.208584] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10824 09:32:04.046296 <6>[ 8.208983] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10825 09:32:04.052832 <6>[ 8.209089] usbcore: registered new interface driver uvcvideo
10826 09:32:04.059388 <5>[ 8.213759] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10827 09:32:04.066268 <6>[ 8.245681] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10828 09:32:04.076346 <4>[ 8.253311] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10829 09:32:04.082830 <6>[ 8.373131] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10830 09:32:04.089200 <6>[ 8.376585] cfg80211: failed to load regulatory.db
10831 09:32:04.096175 <6>[ 8.382752] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10832 09:32:04.117619 <6>[ 8.478005] mt7921e 0000:01:00.0: ASIC revision: 79610010
10833 09:32:04.221014 <6>[ 8.578119] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10834 09:32:04.224662 <6>[ 8.578119]
10835 09:32:04.227842 Begin: Loading essential drivers ... done.
10836 09:32:04.230956 Begin: Running /scripts/init-premount ... done.
10837 09:32:04.237595 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10838 09:32:04.247517 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10839 09:32:04.251262 Device /sys/class/net/eth0 found
10840 09:32:04.251367 done.
10841 09:32:04.257490 Begin: Waiting up to 180 secs for any network device to become available ... done.
10842 09:32:04.317772 IP-Config: eth0 hardware address 00:e0:4c:72:2d:d6 mtu 1500 DHCP
10843 09:32:04.324192 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10844 09:32:04.330867 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10845 09:32:04.337747 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10846 09:32:04.344345 host : mt8192-asurada-spherion-r0-cbg-1
10847 09:32:04.351071 domain : lava-rack
10848 09:32:04.354260 rootserver: 192.168.201.1 rootpath:
10849 09:32:04.354361 filename :
10850 09:32:04.489395 <6>[ 8.846733] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10851 09:32:04.489562 done.
10852 09:32:04.499474 Begin: Running /scripts/nfs-bottom ... done.
10853 09:32:04.515160 Begin: Running /scripts/init-bottom ... done.
10854 09:32:05.805596 <6>[ 10.165878] NET: Registered PF_INET6 protocol family
10855 09:32:05.812801 <6>[ 10.173414] Segment Routing with IPv6
10856 09:32:05.815886 <6>[ 10.177406] In-situ OAM (IOAM) with IPv6
10857 09:32:05.977814 <30>[ 10.311975] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10858 09:32:05.984669 <30>[ 10.345104] systemd[1]: Detected architecture arm64.
10859 09:32:05.992011
10860 09:32:05.995198 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10861 09:32:05.995281
10862 09:32:06.018310 <30>[ 10.378927] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10863 09:32:06.937558 <30>[ 11.294691] systemd[1]: Queued start job for default target graphical.target.
10864 09:32:06.977490 <30>[ 11.334967] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10865 09:32:06.984217 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10866 09:32:07.006503 <30>[ 11.363918] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10867 09:32:07.016920 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10868 09:32:07.034483 <30>[ 11.391809] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10869 09:32:07.044423 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10870 09:32:07.062524 <30>[ 11.419544] systemd[1]: Created slice user.slice - User and Session Slice.
10871 09:32:07.068544 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10872 09:32:07.092245 <30>[ 11.446394] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10873 09:32:07.102307 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10874 09:32:07.120239 <30>[ 11.474321] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10875 09:32:07.126888 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10876 09:32:07.155154 <30>[ 11.502765] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10877 09:32:07.165622 <30>[ 11.522672] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10878 09:32:07.172182 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10879 09:32:07.189101 <30>[ 11.546091] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10880 09:32:07.195700 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10881 09:32:07.213379 <30>[ 11.570158] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10882 09:32:07.222806 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10883 09:32:07.238336 <30>[ 11.598389] systemd[1]: Reached target paths.target - Path Units.
10884 09:32:07.248079 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10885 09:32:07.265446 <30>[ 11.622539] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10886 09:32:07.272329 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10887 09:32:07.285948 <30>[ 11.646080] systemd[1]: Reached target slices.target - Slice Units.
10888 09:32:07.296043 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10889 09:32:07.310194 <30>[ 11.670591] systemd[1]: Reached target swap.target - Swaps.
10890 09:32:07.317147 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10891 09:32:07.337692 <30>[ 11.694154] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10892 09:32:07.347163 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10893 09:32:07.366409 <30>[ 11.723065] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10894 09:32:07.376160 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10895 09:32:07.396173 <30>[ 11.753305] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10896 09:32:07.406764 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10897 09:32:07.422883 <30>[ 11.779643] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10898 09:32:07.433066 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10899 09:32:07.449907 <30>[ 11.806857] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10900 09:32:07.456912 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10901 09:32:07.475140 <30>[ 11.831841] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10902 09:32:07.485035 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10903 09:32:07.505265 <30>[ 11.862326] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10904 09:32:07.515428 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10905 09:32:07.534575 <30>[ 11.891592] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10906 09:32:07.544265 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10907 09:32:07.593806 <30>[ 11.950526] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10908 09:32:07.600248 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10909 09:32:07.619175 <30>[ 11.976549] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10910 09:32:07.625931 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10911 09:32:07.648732 <30>[ 12.005910] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10912 09:32:07.655392 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10913 09:32:07.680458 <30>[ 12.030742] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10914 09:32:07.695728 <30>[ 12.052937] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10915 09:32:07.705867 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10916 09:32:07.726644 <30>[ 12.083699] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10917 09:32:07.733522 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10918 09:32:07.756463 <30>[ 12.113271] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10919 09:32:07.762950 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10920 09:32:07.786668 <30>[ 12.143690] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10921 09:32:07.800054 Starting [0;1;39mmodprobe@drm.service[0m - Load Kerne<6>[ 12.156655] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10922 09:32:07.802957 l Module drm...
10923 09:32:07.861974 <30>[ 12.218928] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10924 09:32:07.871955 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10925 09:32:07.894431 <30>[ 12.251594] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10926 09:32:07.901220 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10927 09:32:07.926761 <30>[ 12.283748] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10928 09:32:07.933488 Startin<6>[ 12.292700] fuse: init (API version 7.37)
10929 09:32:07.939772 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10930 09:32:07.970417 <30>[ 12.327348] systemd[1]: Starting systemd-journald.service - Journal Service...
10931 09:32:07.976806 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10932 09:32:08.011837 <30>[ 12.369004] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10933 09:32:08.018897 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10934 09:32:08.047177 <30>[ 12.400845] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10935 09:32:08.053877 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10936 09:32:08.084180 <30>[ 12.441482] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10937 09:32:08.094100 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10938 09:32:08.154227 <30>[ 12.511122] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10939 09:32:08.160877 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10940 09:32:08.189994 <30>[ 12.547147] systemd[1]: Started systemd-journald.service - Journal Service.
10941 09:32:08.196811 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10942 09:32:08.216135 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10943 09:32:08.237830 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10944 09:32:08.257479 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10945 09:32:08.278465 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10946 09:32:08.299309 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10947 09:32:08.319876 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10948 09:32:08.342712 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10949 09:32:08.362085 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10950 09:32:08.383631 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10951 09:32:08.403791 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10952 09:32:08.423843 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10953 09:32:08.443335 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10954 09:32:08.462774 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10955 09:32:08.484669 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10956 09:32:08.542237 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10957 09:32:08.563973 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10958 09:32:08.589494 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10959 09:32:08.619368 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10960 09:32:08.647259 <46>[ 13.004303] systemd-journald[301]: Received client request to flush runtime journal.
10961 09:32:08.653747 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10962 09:32:08.702711 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10963 09:32:08.971816 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10964 09:32:08.990574 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10965 09:32:09.009636 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10966 09:32:09.029998 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10967 09:32:09.746752 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10968 09:32:10.053123 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10969 09:32:10.074107 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10970 09:32:10.134291 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10971 09:32:10.222714 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10972 09:32:10.245375 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10973 09:32:10.265197 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10974 09:32:10.307173 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10975 09:32:10.335641 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10976 09:32:10.560467 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10977 09:32:10.578265 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10978 09:32:10.699921 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10979 09:32:10.763207 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10980 09:32:10.878784 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10981 09:32:10.912332 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10982 09:32:10.929580 <6>[ 15.290503] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10983 09:32:11.011076 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10984 09:32:11.084454 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10985 09:32:11.123055 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10986 09:32:11.171791 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10987 09:32:11.247592 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10988 09:32:11.265221 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10989 09:32:11.289112 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10990 09:32:11.311903 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10991 09:32:11.327901 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10992 09:32:11.349129 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10993 09:32:11.365198 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10994 09:32:11.380785 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10995 09:32:11.406828 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10996 09:32:11.428328 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10997 09:32:11.444886 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10998 09:32:11.463821 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10999 09:32:11.483711 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11000 09:32:11.500612 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11001 09:32:11.519155 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11002 09:32:11.536952 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11003 09:32:11.552950 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11004 09:32:11.598352 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11005 09:32:11.655636 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11006 09:32:11.710171 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11007 09:32:11.736431 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11008 09:32:11.758104 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11009 09:32:11.843908 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11010 09:32:11.901119 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11011 09:32:11.921769 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11012 09:32:11.941061 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11013 09:32:11.961785 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11014 09:32:11.980719 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11015 09:32:12.018955 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11016 09:32:12.250454 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11017 09:32:12.275896 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11018 09:32:12.295532 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11019 09:32:12.337100 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11020 09:32:12.392852 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11021 09:32:12.468874
11022 09:32:12.472306 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11023 09:32:12.472817
11024 09:32:12.475483 debian-bookworm-arm64 login: root (automatic login)
11025 09:32:12.475954
11026 09:32:12.774932 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
11027 09:32:12.775145
11028 09:32:12.781692 The programs included with the Debian GNU/Linux system are free software;
11029 09:32:12.788722 the exact distribution terms for each program are described in the
11030 09:32:12.791851 individual files in /usr/share/doc/*/copyright.
11031 09:32:12.792282
11032 09:32:12.798263 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11033 09:32:12.801937 permitted by applicable law.
11034 09:32:13.896827 Matched prompt #10: / #
11036 09:32:13.898172 Setting prompt string to ['/ #']
11037 09:32:13.898617 end: 2.2.5.1 login-action (duration 00:00:19) [common]
11039 09:32:13.900019 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
11040 09:32:13.900796 start: 2.2.6 expect-shell-connection (timeout 00:03:43) [common]
11041 09:32:13.901164 Setting prompt string to ['/ #']
11042 09:32:13.901258 Forcing a shell prompt, looking for ['/ #']
11044 09:32:13.951905 / #
11045 09:32:13.952617 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11046 09:32:13.953108 Waiting using forced prompt support (timeout 00:02:30)
11047 09:32:13.958008
11048 09:32:13.958956 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11049 09:32:13.959502 start: 2.2.7 export-device-env (timeout 00:03:43) [common]
11051 09:32:14.060665 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407671/extract-nfsrootfs-tqnv2l7u'
11052 09:32:14.067487 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407671/extract-nfsrootfs-tqnv2l7u'
11054 09:32:14.169268 / # export NFS_SERVER_IP='192.168.201.1'
11055 09:32:14.175635 export NFS_SERVER_IP='192.168.201.1'
11056 09:32:14.176618 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11057 09:32:14.177159 end: 2.2 depthcharge-retry (duration 00:01:17) [common]
11058 09:32:14.177675 end: 2 depthcharge-action (duration 00:01:17) [common]
11059 09:32:14.178287 start: 3 lava-test-retry (timeout 00:08:06) [common]
11060 09:32:14.178789 start: 3.1 lava-test-shell (timeout 00:08:06) [common]
11061 09:32:14.179204 Using namespace: common
11063 09:32:14.280654 / # #
11064 09:32:14.281310 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11065 09:32:14.286959 #
11066 09:32:14.287870 Using /lava-14407671
11068 09:32:14.389149 / # export SHELL=/bin/bash
11069 09:32:14.395874 export SHELL=/bin/bash
11071 09:32:14.498066 / # . /lava-14407671/environment
11072 09:32:14.504659 . /lava-14407671/environment
11074 09:32:14.612284 / # /lava-14407671/bin/lava-test-runner /lava-14407671/0
11075 09:32:14.612956 Test shell timeout: 10s (minimum of the action and connection timeout)
11076 09:32:14.619155 /lava-14407671/bin/lava-test-runner /lava-14407671/0
11077 09:32:14.888465 + export TESTRUN_ID=0_timesync-off
11078 09:32:14.891665 + TESTRUN_ID=0_timesync-off
11079 09:32:14.894835 + cd /lava-14407671/0/tests/0_timesync-off
11080 09:32:14.898042 ++ cat uuid
11081 09:32:14.901846 + UUID=14407671_1.6.2.3.1
11082 09:32:14.902276 + set +x
11083 09:32:14.908071 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14407671_1.6.2.3.1>
11084 09:32:14.908911 Received signal: <STARTRUN> 0_timesync-off 14407671_1.6.2.3.1
11085 09:32:14.909306 Starting test lava.0_timesync-off (14407671_1.6.2.3.1)
11086 09:32:14.909743 Skipping test definition patterns.
11087 09:32:14.911243 + systemctl stop systemd-timesyncd
11088 09:32:15.009014 + set +x
11089 09:32:15.012185 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14407671_1.6.2.3.1>
11090 09:32:15.012527 Received signal: <ENDRUN> 0_timesync-off 14407671_1.6.2.3.1
11091 09:32:15.012686 Ending use of test pattern.
11092 09:32:15.012784 Ending test lava.0_timesync-off (14407671_1.6.2.3.1), duration 0.10
11094 09:32:15.075872 + export TESTRUN_ID=1_kselftest-rtc
11095 09:32:15.079128 + TESTRUN_ID=1_kselftest-rtc
11096 09:32:15.082389 + cd /lava-14407671/0/tests/1_kselftest-rtc
11097 09:32:15.086184 ++ cat uuid
11098 09:32:15.089337 + UUID=14407671_1.6.2.3.5
11099 09:32:15.089420 + set +x
11100 09:32:15.092377 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 14407671_1.6.2.3.5>
11101 09:32:15.092633 Received signal: <STARTRUN> 1_kselftest-rtc 14407671_1.6.2.3.5
11102 09:32:15.092702 Starting test lava.1_kselftest-rtc (14407671_1.6.2.3.5)
11103 09:32:15.092782 Skipping test definition patterns.
11104 09:32:15.095793 + cd ./automated/linux/kselftest/
11105 09:32:15.122462 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11106 09:32:15.157711 INFO: install_deps skipped
11107 09:32:15.667279 --2024-06-18 09:30:50-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11108 09:32:15.680694 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11109 09:32:15.809446 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11110 09:32:15.938185 HTTP request sent, awaiting response... 200 OK
11111 09:32:15.941664 Length: 1642672 (1.6M) [application/octet-stream]
11112 09:32:15.944808 Saving to: 'kselftest_armhf.tar.gz'
11113 09:32:15.945446
11114 09:32:15.945815
11115 09:32:16.195909 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11116 09:32:16.453424 kselftest_armhf.tar 2%[ ] 47.81K 186KB/s
11117 09:32:16.757407 kselftest_armhf.tar 13%[=> ] 217.50K 422KB/s
11118 09:32:16.888621 kselftest_armhf.tar 52%[=========> ] 836.85K 1022KB/s
11119 09:32:16.895397 kselftest_armhf.tar 100%[===================>] 1.57M 1.65MB/s in 1.0s
11120 09:32:16.895493
11121 09:32:17.041342 2024-06-18 09:30:52 (1.65 MB/s) - 'kselftest_armhf.tar.gz' saved [1642672/1642672]
11122 09:32:17.041477
11123 09:32:20.371857 skiplist:
11124 09:32:20.375513 ========================================
11125 09:32:20.378717 ========================================
11126 09:32:20.419880 rtc:rtctest
11127 09:32:20.438559 ============== Tests to run ===============
11128 09:32:20.438870 rtc:rtctest
11129 09:32:20.442289 ===========End Tests to run ===============
11130 09:32:20.445391 shardfile-rtc pass
11131 09:32:20.542284 <12>[ 24.904550] kselftest: Running tests in rtc
11132 09:32:20.551808 TAP version 13
11133 09:32:20.565836 1..1
11134 09:32:20.594028 # selftests: rtc: rtctest
11135 09:32:21.047076 # TAP version 13
11136 09:32:21.047233 # 1..8
11137 09:32:21.050702 # # Starting 8 tests from 2 test cases.
11138 09:32:21.053609 # # RUN rtc.date_read ...
11139 09:32:21.060285 # # rtctest.c:49:date_read:Current RTC date/time is 18/06/2024 09:30:55.
11140 09:32:21.063397 # # OK rtc.date_read
11141 09:32:21.067135 # ok 1 rtc.date_read
11142 09:32:21.070271 # # RUN rtc.date_read_loop ...
11143 09:32:21.080256 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11144 09:32:33.599361 <6>[ 37.966217] vpu: disabling
11145 09:32:33.602307 <6>[ 37.969324] vproc2: disabling
11146 09:32:33.605869 <6>[ 37.972682] vproc1: disabling
11147 09:32:33.608872 <6>[ 37.976058] vaud18: disabling
11148 09:32:33.616173 <6>[ 37.979962] vsram_others: disabling
11149 09:32:33.619653 <6>[ 37.983931] va09: disabling
11150 09:32:33.622625 <6>[ 37.987098] vsram_md: disabling
11151 09:32:33.626226 <6>[ 37.990665] Vgpu: disabling
11152 09:32:51.051733 # # rtctest.c:115:date_read_loop:Performed 2625 RTC time reads.
11153 09:32:51.055309 # # OK rtc.date_read_loop
11154 09:32:51.058809 # ok 2 rtc.date_read_loop
11155 09:32:51.061894 # # RUN rtc.uie_read ...
11156 09:32:54.035513 # # OK rtc.uie_read
11157 09:32:54.038727 # ok 3 rtc.uie_read
11158 09:32:54.042111 # # RUN rtc.uie_select ...
11159 09:32:57.035165 # # OK rtc.uie_select
11160 09:32:57.038264 # ok 4 rtc.uie_select
11161 09:32:57.041770 # # RUN rtc.alarm_alm_set ...
11162 09:32:57.048171 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 09:31:35.
11163 09:32:57.051196 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11164 09:32:57.058292 # # alarm_alm_set: Test terminated by assertion
11165 09:32:57.061640 # # FAIL rtc.alarm_alm_set
11166 09:32:57.062119 # not ok 5 rtc.alarm_alm_set
11167 09:32:57.068388 # # RUN rtc.alarm_wkalm_set ...
11168 09:32:57.074716 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 18/06/2024 09:31:35.
11169 09:33:00.037683 # # OK rtc.alarm_wkalm_set
11170 09:33:00.038238 # ok 6 rtc.alarm_wkalm_set
11171 09:33:00.044365 # # RUN rtc.alarm_alm_set_minute ...
11172 09:33:00.047474 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 09:32:00.
11173 09:33:00.054333 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11174 09:33:00.060852 # # alarm_alm_set_minute: Test terminated by assertion
11175 09:33:00.064282 # # FAIL rtc.alarm_alm_set_minute
11176 09:33:00.067671 # not ok 7 rtc.alarm_alm_set_minute
11177 09:33:00.071405 # # RUN rtc.alarm_wkalm_set_minute ...
11178 09:33:00.077466 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 18/06/2024 09:32:00.
11179 09:33:25.034712 # # OK rtc.alarm_wkalm_set_minute
11180 09:33:25.037943 # ok 8 rtc.alarm_wkalm_set_minute
11181 09:33:25.041331 # # FAILED: 6 / 8 tests passed.
11182 09:33:25.044663 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11183 09:33:25.047633 not ok 1 selftests: rtc: rtctest # exit=1
11184 09:33:26.470231 rtc_rtctest_rtc_date_read pass
11185 09:33:26.473492 rtc_rtctest_rtc_date_read_loop pass
11186 09:33:26.476440 rtc_rtctest_rtc_uie_read pass
11187 09:33:26.479793 rtc_rtctest_rtc_uie_select pass
11188 09:33:26.483363 rtc_rtctest_rtc_alarm_alm_set fail
11189 09:33:26.486466 rtc_rtctest_rtc_alarm_wkalm_set pass
11190 09:33:26.489911 rtc_rtctest_rtc_alarm_alm_set_minute fail
11191 09:33:26.493369 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11192 09:33:26.496307 rtc_rtctest fail
11193 09:33:26.547376 + ../../utils/send-to-lava.sh ./output/result.txt
11194 09:33:26.602675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11195 09:33:26.603062 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11197 09:33:26.643788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11198 09:33:26.644057 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11200 09:33:26.692587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11201 09:33:26.692866 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11203 09:33:26.735017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11204 09:33:26.735287 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11206 09:33:26.782254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11207 09:33:26.782510 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11209 09:33:26.826991 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11211 09:33:26.830115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11212 09:33:26.870134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11213 09:33:26.870399 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11215 09:33:26.911024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11216 09:33:26.911297 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11218 09:33:26.952475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11219 09:33:26.952819 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11221 09:33:26.988374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11222 09:33:26.988460 + set +x
11223 09:33:26.988696 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11225 09:33:26.995013 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 14407671_1.6.2.3.5>
11226 09:33:26.995268 Received signal: <ENDRUN> 1_kselftest-rtc 14407671_1.6.2.3.5
11227 09:33:26.995342 Ending use of test pattern.
11228 09:33:26.995405 Ending test lava.1_kselftest-rtc (14407671_1.6.2.3.5), duration 71.90
11230 09:33:26.995625 ok: lava_test_shell seems to have completed
11231 09:33:26.995758 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11232 09:33:26.995850 end: 3.1 lava-test-shell (duration 00:01:13) [common]
11233 09:33:26.995937 end: 3 lava-test-retry (duration 00:01:13) [common]
11234 09:33:26.996027 start: 4 finalize (timeout 00:06:53) [common]
11235 09:33:26.996122 start: 4.1 power-off (timeout 00:00:30) [common]
11236 09:33:26.996275 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-1', '--port=1', '--command=off']
11237 09:33:27.193875 >> Command sent successfully.
11238 09:33:27.196130 Returned 0 in 0 seconds
11239 09:33:27.296503 end: 4.1 power-off (duration 00:00:00) [common]
11241 09:33:27.296849 start: 4.2 read-feedback (timeout 00:06:53) [common]
11243 09:33:27.297407 Listened to connection for namespace 'common' for up to 1s
11244 09:33:28.298065 Finalising connection for namespace 'common'
11245 09:33:28.298235 Disconnecting from shell: Finalise
11246 09:33:28.298317 / #
11247 09:33:28.398588 end: 4.2 read-feedback (duration 00:00:01) [common]
11248 09:33:28.398800 end: 4 finalize (duration 00:00:01) [common]
11249 09:33:28.398965 Cleaning after the job
11250 09:33:28.399135 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/ramdisk
11251 09:33:28.401554 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/kernel
11252 09:33:28.412095 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/dtb
11253 09:33:28.412276 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/nfsrootfs
11254 09:33:28.472365 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407671/tftp-deploy-gyn3kd_t/modules
11255 09:33:28.477678 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407671
11256 09:33:28.996309 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407671
11257 09:33:28.996494 Job finished correctly