Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 09:27:26.416537 lava-dispatcher, installed at version: 2024.03
2 09:27:26.416752 start: 0 validate
3 09:27:26.416890 Start time: 2024-06-18 09:27:26.416883+00:00 (UTC)
4 09:27:26.417018 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:27:26.417158 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:27:26.670348 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:27:26.670663 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:27:26.936798 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:27:26.937765 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:27:27.205841 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:27:27.206549 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:27:27.467845 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:27:27.468609 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:27:27.738266 validate duration: 1.32
16 09:27:27.738550 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:27:27.738654 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:27:27.738773 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:27:27.738943 Not decompressing ramdisk as can be used compressed.
20 09:27:27.739029 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 09:27:27.739093 saving as /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/ramdisk/initrd.cpio.gz
22 09:27:27.739158 total size: 5628169 (5 MB)
23 09:27:27.740203 progress 0 % (0 MB)
24 09:27:27.742066 progress 5 % (0 MB)
25 09:27:27.743707 progress 10 % (0 MB)
26 09:27:27.745126 progress 15 % (0 MB)
27 09:27:27.746760 progress 20 % (1 MB)
28 09:27:27.748193 progress 25 % (1 MB)
29 09:27:27.749777 progress 30 % (1 MB)
30 09:27:27.751381 progress 35 % (1 MB)
31 09:27:27.752815 progress 40 % (2 MB)
32 09:27:27.754472 progress 45 % (2 MB)
33 09:27:27.755840 progress 50 % (2 MB)
34 09:27:27.757356 progress 55 % (2 MB)
35 09:27:27.758932 progress 60 % (3 MB)
36 09:27:27.760331 progress 65 % (3 MB)
37 09:27:27.761930 progress 70 % (3 MB)
38 09:27:27.763320 progress 75 % (4 MB)
39 09:27:27.764830 progress 80 % (4 MB)
40 09:27:27.766203 progress 85 % (4 MB)
41 09:27:27.767745 progress 90 % (4 MB)
42 09:27:27.769256 progress 95 % (5 MB)
43 09:27:27.770675 progress 100 % (5 MB)
44 09:27:27.770881 5 MB downloaded in 0.03 s (169.19 MB/s)
45 09:27:27.771032 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:27:27.771269 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:27:27.771353 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:27:27.771434 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:27:27.771569 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:27:27.771640 saving as /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/kernel/Image
52 09:27:27.771705 total size: 54813184 (52 MB)
53 09:27:27.771766 No compression specified
54 09:27:27.772860 progress 0 % (0 MB)
55 09:27:27.786768 progress 5 % (2 MB)
56 09:27:27.800689 progress 10 % (5 MB)
57 09:27:27.814484 progress 15 % (7 MB)
58 09:27:27.828436 progress 20 % (10 MB)
59 09:27:27.842416 progress 25 % (13 MB)
60 09:27:27.856257 progress 30 % (15 MB)
61 09:27:27.870248 progress 35 % (18 MB)
62 09:27:27.884161 progress 40 % (20 MB)
63 09:27:27.897922 progress 45 % (23 MB)
64 09:27:27.911940 progress 50 % (26 MB)
65 09:27:27.925928 progress 55 % (28 MB)
66 09:27:27.939940 progress 60 % (31 MB)
67 09:27:27.953794 progress 65 % (34 MB)
68 09:27:27.967700 progress 70 % (36 MB)
69 09:27:27.981833 progress 75 % (39 MB)
70 09:27:27.995861 progress 80 % (41 MB)
71 09:27:28.009731 progress 85 % (44 MB)
72 09:27:28.023648 progress 90 % (47 MB)
73 09:27:28.037387 progress 95 % (49 MB)
74 09:27:28.051279 progress 100 % (52 MB)
75 09:27:28.051535 52 MB downloaded in 0.28 s (186.81 MB/s)
76 09:27:28.051689 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:27:28.051937 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:27:28.052041 start: 1.3 download-retry (timeout 00:10:00) [common]
80 09:27:28.052124 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 09:27:28.052261 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 09:27:28.052329 saving as /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/dtb/mt8192-asurada-spherion-r0.dtb
83 09:27:28.052389 total size: 47258 (0 MB)
84 09:27:28.052449 No compression specified
85 09:27:28.053593 progress 69 % (0 MB)
86 09:27:28.053865 progress 100 % (0 MB)
87 09:27:28.054020 0 MB downloaded in 0.00 s (27.67 MB/s)
88 09:27:28.054141 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:27:28.054407 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:27:28.054491 start: 1.4 download-retry (timeout 00:10:00) [common]
92 09:27:28.054572 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 09:27:28.054683 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 09:27:28.054750 saving as /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/nfsrootfs/full.rootfs.tar
95 09:27:28.054808 total size: 120894716 (115 MB)
96 09:27:28.054868 Using unxz to decompress xz
97 09:27:28.058970 progress 0 % (0 MB)
98 09:27:28.419150 progress 5 % (5 MB)
99 09:27:28.796411 progress 10 % (11 MB)
100 09:27:29.145906 progress 15 % (17 MB)
101 09:27:29.473351 progress 20 % (23 MB)
102 09:27:29.764862 progress 25 % (28 MB)
103 09:27:30.123857 progress 30 % (34 MB)
104 09:27:30.459907 progress 35 % (40 MB)
105 09:27:30.626034 progress 40 % (46 MB)
106 09:27:30.803154 progress 45 % (51 MB)
107 09:27:31.115133 progress 50 % (57 MB)
108 09:27:31.489584 progress 55 % (63 MB)
109 09:27:31.835626 progress 60 % (69 MB)
110 09:27:32.180850 progress 65 % (74 MB)
111 09:27:32.526472 progress 70 % (80 MB)
112 09:27:32.886134 progress 75 % (86 MB)
113 09:27:33.230915 progress 80 % (92 MB)
114 09:27:33.571990 progress 85 % (98 MB)
115 09:27:33.930012 progress 90 % (103 MB)
116 09:27:34.263675 progress 95 % (109 MB)
117 09:27:34.621792 progress 100 % (115 MB)
118 09:27:34.627244 115 MB downloaded in 6.57 s (17.54 MB/s)
119 09:27:34.627539 end: 1.4.1 http-download (duration 00:00:07) [common]
121 09:27:34.627813 end: 1.4 download-retry (duration 00:00:07) [common]
122 09:27:34.627906 start: 1.5 download-retry (timeout 00:09:53) [common]
123 09:27:34.627991 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 09:27:34.628142 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:27:34.628215 saving as /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/modules/modules.tar
126 09:27:34.628276 total size: 8619356 (8 MB)
127 09:27:34.628338 Using unxz to decompress xz
128 09:27:34.632492 progress 0 % (0 MB)
129 09:27:34.652454 progress 5 % (0 MB)
130 09:27:34.677225 progress 10 % (0 MB)
131 09:27:34.702944 progress 15 % (1 MB)
132 09:27:34.728352 progress 20 % (1 MB)
133 09:27:34.754324 progress 25 % (2 MB)
134 09:27:34.779601 progress 30 % (2 MB)
135 09:27:34.805065 progress 35 % (2 MB)
136 09:27:34.829828 progress 40 % (3 MB)
137 09:27:34.854829 progress 45 % (3 MB)
138 09:27:34.879307 progress 50 % (4 MB)
139 09:27:34.904397 progress 55 % (4 MB)
140 09:27:34.929356 progress 60 % (4 MB)
141 09:27:34.953743 progress 65 % (5 MB)
142 09:27:34.982362 progress 70 % (5 MB)
143 09:27:35.007747 progress 75 % (6 MB)
144 09:27:35.031736 progress 80 % (6 MB)
145 09:27:35.055721 progress 85 % (7 MB)
146 09:27:35.079773 progress 90 % (7 MB)
147 09:27:35.109005 progress 95 % (7 MB)
148 09:27:35.139923 progress 100 % (8 MB)
149 09:27:35.144564 8 MB downloaded in 0.52 s (15.92 MB/s)
150 09:27:35.144844 end: 1.5.1 http-download (duration 00:00:01) [common]
152 09:27:35.145117 end: 1.5 download-retry (duration 00:00:01) [common]
153 09:27:35.145213 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 09:27:35.145305 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 09:27:38.577571 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14407642/extract-nfsrootfs-ibllctfm
156 09:27:38.577788 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 09:27:38.577887 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 09:27:38.578063 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43
159 09:27:38.578208 makedir: /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin
160 09:27:38.578319 makedir: /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/tests
161 09:27:38.578415 makedir: /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/results
162 09:27:38.578516 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-add-keys
163 09:27:38.578656 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-add-sources
164 09:27:38.578784 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-background-process-start
165 09:27:38.578907 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-background-process-stop
166 09:27:38.579028 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-common-functions
167 09:27:38.579148 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-echo-ipv4
168 09:27:38.579267 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-install-packages
169 09:27:38.579388 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-installed-packages
170 09:27:38.579508 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-os-build
171 09:27:38.579629 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-probe-channel
172 09:27:38.579750 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-probe-ip
173 09:27:38.579870 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-target-ip
174 09:27:38.579990 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-target-mac
175 09:27:38.580108 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-target-storage
176 09:27:38.580229 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-test-case
177 09:27:38.580350 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-test-event
178 09:27:38.580469 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-test-feedback
179 09:27:38.580588 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-test-raise
180 09:27:38.580706 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-test-reference
181 09:27:38.580825 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-test-runner
182 09:27:38.580944 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-test-set
183 09:27:38.581063 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-test-shell
184 09:27:38.581184 Updating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-add-keys (debian)
185 09:27:38.581330 Updating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-add-sources (debian)
186 09:27:38.581469 Updating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-install-packages (debian)
187 09:27:38.581609 Updating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-installed-packages (debian)
188 09:27:38.581740 Updating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/bin/lava-os-build (debian)
189 09:27:38.581859 Creating /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/environment
190 09:27:38.581954 LAVA metadata
191 09:27:38.582018 - LAVA_JOB_ID=14407642
192 09:27:38.582078 - LAVA_DISPATCHER_IP=192.168.201.1
193 09:27:38.582448 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 09:27:38.582519 skipped lava-vland-overlay
195 09:27:38.582596 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 09:27:38.582674 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 09:27:38.582735 skipped lava-multinode-overlay
198 09:27:38.582806 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 09:27:38.582884 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 09:27:38.582958 Loading test definitions
201 09:27:38.583043 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 09:27:38.583114 Using /lava-14407642 at stage 0
203 09:27:38.583387 uuid=14407642_1.6.2.3.1 testdef=None
204 09:27:38.583473 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 09:27:38.583557 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 09:27:38.584004 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 09:27:38.584219 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 09:27:38.584760 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 09:27:38.584984 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 09:27:38.585502 runner path: /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/0/tests/0_timesync-off test_uuid 14407642_1.6.2.3.1
213 09:27:38.585656 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 09:27:38.585879 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 09:27:38.585950 Using /lava-14407642 at stage 0
217 09:27:38.586043 Fetching tests from https://github.com/kernelci/test-definitions.git
218 09:27:38.586127 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/0/tests/1_kselftest-tpm2'
219 09:27:41.192463 Running '/usr/bin/git checkout kernelci.org
220 09:27:41.322920 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 09:27:41.323663 uuid=14407642_1.6.2.3.5 testdef=None
222 09:27:41.323830 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 09:27:41.324121 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 09:27:41.324866 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 09:27:41.325098 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 09:27:41.326075 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 09:27:41.326359 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 09:27:41.327282 runner path: /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/0/tests/1_kselftest-tpm2 test_uuid 14407642_1.6.2.3.5
232 09:27:41.327376 BOARD='mt8192-asurada-spherion-r0'
233 09:27:41.327440 BRANCH='cip'
234 09:27:41.327499 SKIPFILE='/dev/null'
235 09:27:41.327557 SKIP_INSTALL='True'
236 09:27:41.327612 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 09:27:41.327668 TST_CASENAME=''
238 09:27:41.327722 TST_CMDFILES='tpm2'
239 09:27:41.327860 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 09:27:41.328060 Creating lava-test-runner.conf files
242 09:27:41.328123 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407642/lava-overlay-twsylh43/lava-14407642/0 for stage 0
243 09:27:41.328216 - 0_timesync-off
244 09:27:41.328281 - 1_kselftest-tpm2
245 09:27:41.328375 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 09:27:41.328485 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 09:27:48.934030 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 09:27:48.934193 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 09:27:48.934287 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 09:27:48.934383 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 09:27:48.934472 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 09:27:49.100919 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 09:27:49.101314 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 09:27:49.101424 extracting modules file /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407642/extract-nfsrootfs-ibllctfm
255 09:27:49.329022 extracting modules file /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407642/extract-overlay-ramdisk-r4shgg6k/ramdisk
256 09:27:49.543814 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 09:27:49.543988 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 09:27:49.544085 [common] Applying overlay to NFS
259 09:27:49.544156 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407642/compress-overlay-5x5klg64/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407642/extract-nfsrootfs-ibllctfm
260 09:27:50.459428 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 09:27:50.459597 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 09:27:50.459692 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 09:27:50.459780 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 09:27:50.459860 Building ramdisk /var/lib/lava/dispatcher/tmp/14407642/extract-overlay-ramdisk-r4shgg6k/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407642/extract-overlay-ramdisk-r4shgg6k/ramdisk
265 09:27:50.786272 >> 130466 blocks
266 09:27:52.786111 rename /var/lib/lava/dispatcher/tmp/14407642/extract-overlay-ramdisk-r4shgg6k/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/ramdisk/ramdisk.cpio.gz
267 09:27:52.786597 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 09:27:52.786725 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 09:27:52.786827 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 09:27:52.786929 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/kernel/Image']
271 09:28:05.965261 Returned 0 in 13 seconds
272 09:28:06.065940 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/kernel/image.itb
273 09:28:06.415020 output: FIT description: Kernel Image image with one or more FDT blobs
274 09:28:06.415401 output: Created: Tue Jun 18 10:28:06 2024
275 09:28:06.415476 output: Image 0 (kernel-1)
276 09:28:06.415538 output: Description:
277 09:28:06.415603 output: Created: Tue Jun 18 10:28:06 2024
278 09:28:06.415668 output: Type: Kernel Image
279 09:28:06.415729 output: Compression: lzma compressed
280 09:28:06.415804 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
281 09:28:06.415865 output: Architecture: AArch64
282 09:28:06.415923 output: OS: Linux
283 09:28:06.415980 output: Load Address: 0x00000000
284 09:28:06.416035 output: Entry Point: 0x00000000
285 09:28:06.416089 output: Hash algo: crc32
286 09:28:06.416144 output: Hash value: 4137a6e7
287 09:28:06.416197 output: Image 1 (fdt-1)
288 09:28:06.416252 output: Description: mt8192-asurada-spherion-r0
289 09:28:06.416307 output: Created: Tue Jun 18 10:28:06 2024
290 09:28:06.416362 output: Type: Flat Device Tree
291 09:28:06.416416 output: Compression: uncompressed
292 09:28:06.416469 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 09:28:06.416521 output: Architecture: AArch64
294 09:28:06.416574 output: Hash algo: crc32
295 09:28:06.416626 output: Hash value: 0f8e4d2e
296 09:28:06.416679 output: Image 2 (ramdisk-1)
297 09:28:06.416731 output: Description: unavailable
298 09:28:06.416782 output: Created: Tue Jun 18 10:28:06 2024
299 09:28:06.416835 output: Type: RAMDisk Image
300 09:28:06.416887 output: Compression: Unknown Compression
301 09:28:06.416939 output: Data Size: 18746599 Bytes = 18307.23 KiB = 17.88 MiB
302 09:28:06.416992 output: Architecture: AArch64
303 09:28:06.417044 output: OS: Linux
304 09:28:06.417096 output: Load Address: unavailable
305 09:28:06.417148 output: Entry Point: unavailable
306 09:28:06.417199 output: Hash algo: crc32
307 09:28:06.417251 output: Hash value: 40680b04
308 09:28:06.417302 output: Default Configuration: 'conf-1'
309 09:28:06.417354 output: Configuration 0 (conf-1)
310 09:28:06.417406 output: Description: mt8192-asurada-spherion-r0
311 09:28:06.417458 output: Kernel: kernel-1
312 09:28:06.417510 output: Init Ramdisk: ramdisk-1
313 09:28:06.417562 output: FDT: fdt-1
314 09:28:06.417614 output: Loadables: kernel-1
315 09:28:06.417665 output:
316 09:28:06.417866 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 09:28:06.417965 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 09:28:06.418071 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 09:28:06.418168 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 09:28:06.418282 No LXC device requested
321 09:28:06.418361 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 09:28:06.418445 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 09:28:06.418524 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 09:28:06.418590 Checking files for TFTP limit of 4294967296 bytes.
325 09:28:06.419150 end: 1 tftp-deploy (duration 00:00:39) [common]
326 09:28:06.419263 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 09:28:06.419358 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 09:28:06.419485 substitutions:
329 09:28:06.419554 - {DTB}: 14407642/tftp-deploy-loscb235/dtb/mt8192-asurada-spherion-r0.dtb
330 09:28:06.419618 - {INITRD}: 14407642/tftp-deploy-loscb235/ramdisk/ramdisk.cpio.gz
331 09:28:06.419677 - {KERNEL}: 14407642/tftp-deploy-loscb235/kernel/Image
332 09:28:06.419734 - {LAVA_MAC}: None
333 09:28:06.419790 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14407642/extract-nfsrootfs-ibllctfm
334 09:28:06.419845 - {NFS_SERVER_IP}: 192.168.201.1
335 09:28:06.419900 - {PRESEED_CONFIG}: None
336 09:28:06.419954 - {PRESEED_LOCAL}: None
337 09:28:06.420008 - {RAMDISK}: 14407642/tftp-deploy-loscb235/ramdisk/ramdisk.cpio.gz
338 09:28:06.420062 - {ROOT_PART}: None
339 09:28:06.420115 - {ROOT}: None
340 09:28:06.420169 - {SERVER_IP}: 192.168.201.1
341 09:28:06.420221 - {TEE}: None
342 09:28:06.420275 Parsed boot commands:
343 09:28:06.420327 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 09:28:06.420506 Parsed boot commands: tftpboot 192.168.201.1 14407642/tftp-deploy-loscb235/kernel/image.itb 14407642/tftp-deploy-loscb235/kernel/cmdline
345 09:28:06.420594 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 09:28:06.420678 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 09:28:06.420771 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 09:28:06.420856 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 09:28:06.420928 Not connected, no need to disconnect.
350 09:28:06.421000 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 09:28:06.421080 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 09:28:06.421147 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
353 09:28:06.424904 Setting prompt string to ['lava-test: # ']
354 09:28:06.425272 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 09:28:06.425381 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 09:28:06.425480 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 09:28:06.425573 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 09:28:06.425745 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
359 09:28:20.509263 Returned 0 in 14 seconds
360 09:28:20.609883 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 09:28:20.610271 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 09:28:20.610368 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 09:28:20.610455 Setting prompt string to 'Starting depthcharge on Spherion...'
365 09:28:20.610525 Changing prompt to 'Starting depthcharge on Spherion...'
366 09:28:20.610594 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 09:28:20.611003 [Enter `^Ec?' for help]
368 09:28:20.611084
369 09:28:20.611154 F0: 102B 0000
370 09:28:20.611220
371 09:28:20.611283 F3: 1001 0000 [0200]
372 09:28:20.611342
373 09:28:20.611399 F3: 1001 0000
374 09:28:20.611458
375 09:28:20.611514 F7: 102D 0000
376 09:28:20.611567
377 09:28:20.611621 F1: 0000 0000
378 09:28:20.611674
379 09:28:20.611726 V0: 0000 0000 [0001]
380 09:28:20.611779
381 09:28:20.611831 00: 0007 8000
382 09:28:20.611888
383 09:28:20.611941 01: 0000 0000
384 09:28:20.611995
385 09:28:20.612048 BP: 0C00 0209 [0000]
386 09:28:20.612101
387 09:28:20.612153 G0: 1182 0000
388 09:28:20.612206
389 09:28:20.612259 EC: 0000 0021 [4000]
390 09:28:20.612311
391 09:28:20.612363 S7: 0000 0000 [0000]
392 09:28:20.612415
393 09:28:20.612468 CC: 0000 0000 [0001]
394 09:28:20.612522
395 09:28:20.612594 T0: 0000 0040 [010F]
396 09:28:20.612648
397 09:28:20.612701 Jump to BL
398 09:28:20.612753
399 09:28:20.612805
400 09:28:20.612857
401 09:28:20.612910 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
402 09:28:20.612967 ARM64: Exception handlers installed.
403 09:28:20.613021 ARM64: Testing exception
404 09:28:20.613073 ARM64: Done test exception
405 09:28:20.613126 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
406 09:28:20.613179 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
407 09:28:20.613233 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
408 09:28:20.613287 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
409 09:28:20.613341 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
410 09:28:20.613394 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
411 09:28:20.613462 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
412 09:28:20.613546 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
413 09:28:20.613629 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
414 09:28:20.613697 WDT: Last reset was cold boot
415 09:28:20.613749 SPI1(PAD0) initialized at 2873684 Hz
416 09:28:20.613802 SPI5(PAD0) initialized at 992727 Hz
417 09:28:20.613855 VBOOT: Loading verstage.
418 09:28:20.613908 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
419 09:28:20.613961 FMAP: Found "FLASH" version 1.1 at 0x20000.
420 09:28:20.614015 FMAP: base = 0x0 size = 0x800000 #areas = 25
421 09:28:20.614069 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
422 09:28:20.614122 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
423 09:28:20.614202 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
424 09:28:20.614270 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
425 09:28:20.614323
426 09:28:20.614375
427 09:28:20.614428 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
428 09:28:20.614481 ARM64: Exception handlers installed.
429 09:28:20.614534 ARM64: Testing exception
430 09:28:20.614586 ARM64: Done test exception
431 09:28:20.614639 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
432 09:28:20.614692 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
433 09:28:20.614746 Probing TPM: . done!
434 09:28:20.614799 TPM ready after 0 ms
435 09:28:20.614851 Connected to device vid:did:rid of 1ae0:0028:00
436 09:28:20.614904 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
437 09:28:20.614958 Initialized TPM device CR50 revision 0
438 09:28:20.615010 tlcl_send_startup: Startup return code is 0
439 09:28:20.615063 TPM: setup succeeded
440 09:28:20.615133 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
441 09:28:20.615200 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
442 09:28:20.615253 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
443 09:28:20.615306 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 09:28:20.615362 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
445 09:28:20.615415 in-header: 03 07 00 00 08 00 00 00
446 09:28:20.615478 in-data: aa e4 47 04 13 02 00 00
447 09:28:20.615533 Chrome EC: UHEPI supported
448 09:28:20.615587 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
449 09:28:20.615640 in-header: 03 a9 00 00 08 00 00 00
450 09:28:20.615693 in-data: 84 60 60 08 00 00 00 00
451 09:28:20.615746 Phase 1
452 09:28:20.615799 FMAP: area GBB found @ 3f5000 (12032 bytes)
453 09:28:20.615852 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
454 09:28:20.615906 VB2:vb2_check_recovery() Recovery was requested manually
455 09:28:20.615959 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
456 09:28:20.616012 Recovery requested (1009000e)
457 09:28:20.616065 TPM: Extending digest for VBOOT: boot mode into PCR 0
458 09:28:20.616119 tlcl_extend: response is 0
459 09:28:20.616172 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
460 09:28:20.616225 tlcl_extend: response is 0
461 09:28:20.616277 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
462 09:28:20.616331 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
463 09:28:20.616384 BS: bootblock times (exec / console): total (unknown) / 148 ms
464 09:28:20.616437
465 09:28:20.616489
466 09:28:20.616542 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
467 09:28:20.616615 ARM64: Exception handlers installed.
468 09:28:20.616670 ARM64: Testing exception
469 09:28:20.616724 ARM64: Done test exception
470 09:28:20.616776 pmic_efuse_setting: Set efuses in 11 msecs
471 09:28:20.616829 pmwrap_interface_init: Select PMIF_VLD_RDY
472 09:28:20.616882 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
473 09:28:20.617123 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
474 09:28:20.617183 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
475 09:28:20.617238 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
476 09:28:20.617291 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
477 09:28:20.617345 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
478 09:28:20.617397 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
479 09:28:20.617451 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
480 09:28:20.617504 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
481 09:28:20.617557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
482 09:28:20.617609 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
483 09:28:20.617662 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
484 09:28:20.617715 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
485 09:28:20.617768 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
486 09:28:20.617821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
487 09:28:20.617874 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
488 09:28:20.617928 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
489 09:28:20.617981 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
490 09:28:20.618034 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
491 09:28:20.618087 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
492 09:28:20.618140 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
493 09:28:20.618238 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
494 09:28:20.618293 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
495 09:28:20.618345 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
496 09:28:20.618399 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
497 09:28:20.618451 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
498 09:28:20.618505 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
499 09:28:20.618559 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
500 09:28:20.618612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
501 09:28:20.618665 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
502 09:28:20.618718 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
503 09:28:20.618771 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
504 09:28:20.618824 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
505 09:28:20.618876 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
506 09:28:20.618929 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
507 09:28:20.618982 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
508 09:28:20.619034 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
509 09:28:20.619087 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
510 09:28:20.619140 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
511 09:28:20.619193 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
512 09:28:20.619245 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
513 09:28:20.619298 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
514 09:28:20.619351 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
515 09:28:20.619404 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
516 09:28:20.619456 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
517 09:28:20.619509 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
518 09:28:20.619562 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
519 09:28:20.619615 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
520 09:28:20.619667 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
521 09:28:20.619720 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
522 09:28:20.619773 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
523 09:28:20.619825 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
524 09:28:20.619879 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
525 09:28:20.619932 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
526 09:28:20.619985 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
527 09:28:20.620038 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
528 09:28:20.620091 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
529 09:28:20.620145 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
530 09:28:20.620198 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 09:28:20.620271 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x32
532 09:28:20.620328 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
533 09:28:20.620381 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
534 09:28:20.620435 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
535 09:28:20.620488 [RTC]rtc_get_frequency_meter,154: input=15, output=835
536 09:28:20.620541 [RTC]rtc_get_frequency_meter,154: input=7, output=709
537 09:28:20.620594 [RTC]rtc_get_frequency_meter,154: input=11, output=772
538 09:28:20.620647 [RTC]rtc_get_frequency_meter,154: input=13, output=804
539 09:28:20.620699 [RTC]rtc_get_frequency_meter,154: input=12, output=788
540 09:28:20.620752 [RTC]rtc_get_frequency_meter,154: input=12, output=787
541 09:28:20.620804 [RTC]rtc_get_frequency_meter,154: input=13, output=804
542 09:28:20.620857 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
543 09:28:20.621097 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
544 09:28:20.621157 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
545 09:28:20.621210 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
546 09:28:20.621264 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
547 09:28:20.621340 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
548 09:28:20.621425 ADC[4]: Raw value=903400 ID=7
549 09:28:20.621491 ADC[3]: Raw value=213282 ID=1
550 09:28:20.621544 RAM Code: 0x71
551 09:28:20.621598 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
552 09:28:20.621652 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
553 09:28:20.621705 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
554 09:28:20.621759 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
555 09:28:20.621813 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
556 09:28:20.621866 in-header: 03 07 00 00 08 00 00 00
557 09:28:20.621918 in-data: aa e4 47 04 13 02 00 00
558 09:28:20.621971 Chrome EC: UHEPI supported
559 09:28:20.622024 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
560 09:28:20.622077 in-header: 03 a9 00 00 08 00 00 00
561 09:28:20.622130 in-data: 84 60 60 08 00 00 00 00
562 09:28:20.622231 MRC: failed to locate region type 0.
563 09:28:20.622287 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
564 09:28:20.622340 DRAM-K: Running full calibration
565 09:28:20.622393 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
566 09:28:20.622446 header.status = 0x0
567 09:28:20.622499 header.version = 0x6 (expected: 0x6)
568 09:28:20.622552 header.size = 0xd00 (expected: 0xd00)
569 09:28:20.622605 header.flags = 0x0
570 09:28:20.622657 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
571 09:28:20.622711 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
572 09:28:20.622764 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
573 09:28:20.622818 dram_init: ddr_geometry: 2
574 09:28:20.622870 [EMI] MDL number = 2
575 09:28:20.622922 [EMI] Get MDL freq = 0
576 09:28:20.622975 dram_init: ddr_type: 0
577 09:28:20.623026 is_discrete_lpddr4: 1
578 09:28:20.623079 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
579 09:28:20.623130
580 09:28:20.623183
581 09:28:20.623235 [Bian_co] ETT version 0.0.0.1
582 09:28:20.623287 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
583 09:28:20.623342
584 09:28:20.623395 dramc_set_vcore_voltage set vcore to 650000
585 09:28:20.623447 Read voltage for 800, 4
586 09:28:20.623500 Vio18 = 0
587 09:28:20.623552 Vcore = 650000
588 09:28:20.623604 Vdram = 0
589 09:28:20.623657 Vddq = 0
590 09:28:20.623709 Vmddr = 0
591 09:28:20.623761 dram_init: config_dvfs: 1
592 09:28:20.623814 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
593 09:28:20.623867 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
594 09:28:20.623920 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
595 09:28:20.623972 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
596 09:28:20.624025 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
597 09:28:20.624078 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
598 09:28:20.624130 MEM_TYPE=3, freq_sel=18
599 09:28:20.624182 sv_algorithm_assistance_LP4_1600
600 09:28:20.624234 ============ PULL DRAM RESETB DOWN ============
601 09:28:20.624287 ========== PULL DRAM RESETB DOWN end =========
602 09:28:20.624340 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
603 09:28:20.624408 ===================================
604 09:28:20.624465 LPDDR4 DRAM CONFIGURATION
605 09:28:20.624518 ===================================
606 09:28:20.624571 EX_ROW_EN[0] = 0x0
607 09:28:20.624624 EX_ROW_EN[1] = 0x0
608 09:28:20.624677 LP4Y_EN = 0x0
609 09:28:20.624729 WORK_FSP = 0x0
610 09:28:20.624781 WL = 0x2
611 09:28:20.624834 RL = 0x2
612 09:28:20.624887 BL = 0x2
613 09:28:20.624939 RPST = 0x0
614 09:28:20.624992 RD_PRE = 0x0
615 09:28:20.625053 WR_PRE = 0x1
616 09:28:20.625113 WR_PST = 0x0
617 09:28:20.625166 DBI_WR = 0x0
618 09:28:20.625218 DBI_RD = 0x0
619 09:28:20.625271 OTF = 0x1
620 09:28:20.625323 ===================================
621 09:28:20.625376 ===================================
622 09:28:20.625428 ANA top config
623 09:28:20.625481 ===================================
624 09:28:20.625534 DLL_ASYNC_EN = 0
625 09:28:20.625586 ALL_SLAVE_EN = 1
626 09:28:20.625639 NEW_RANK_MODE = 1
627 09:28:20.625694 DLL_IDLE_MODE = 1
628 09:28:20.625747 LP45_APHY_COMB_EN = 1
629 09:28:20.625819 TX_ODT_DIS = 1
630 09:28:20.625873 NEW_8X_MODE = 1
631 09:28:20.625927 ===================================
632 09:28:20.625980 ===================================
633 09:28:20.626033 data_rate = 1600
634 09:28:20.626085 CKR = 1
635 09:28:20.626137 DQ_P2S_RATIO = 8
636 09:28:20.626233 ===================================
637 09:28:20.626286 CA_P2S_RATIO = 8
638 09:28:20.626339 DQ_CA_OPEN = 0
639 09:28:20.626392 DQ_SEMI_OPEN = 0
640 09:28:20.626444 CA_SEMI_OPEN = 0
641 09:28:20.626497 CA_FULL_RATE = 0
642 09:28:20.626549 DQ_CKDIV4_EN = 1
643 09:28:20.626602 CA_CKDIV4_EN = 1
644 09:28:20.626654 CA_PREDIV_EN = 0
645 09:28:20.626707 PH8_DLY = 0
646 09:28:20.626758 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
647 09:28:20.626810 DQ_AAMCK_DIV = 4
648 09:28:20.626863 CA_AAMCK_DIV = 4
649 09:28:20.626914 CA_ADMCK_DIV = 4
650 09:28:20.626966 DQ_TRACK_CA_EN = 0
651 09:28:20.627019 CA_PICK = 800
652 09:28:20.627071 CA_MCKIO = 800
653 09:28:20.627123 MCKIO_SEMI = 0
654 09:28:20.627176 PLL_FREQ = 3068
655 09:28:20.627228 DQ_UI_PI_RATIO = 32
656 09:28:20.627280 CA_UI_PI_RATIO = 0
657 09:28:20.627332 ===================================
658 09:28:20.627384 ===================================
659 09:28:20.627437 memory_type:LPDDR4
660 09:28:20.627508 GP_NUM : 10
661 09:28:20.627562 SRAM_EN : 1
662 09:28:20.627614 MD32_EN : 0
663 09:28:20.627874 ===================================
664 09:28:20.627937 [ANA_INIT] >>>>>>>>>>>>>>
665 09:28:20.627992 <<<<<< [CONFIGURE PHASE]: ANA_TX
666 09:28:20.628048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
667 09:28:20.628101 ===================================
668 09:28:20.628155 data_rate = 1600,PCW = 0X7600
669 09:28:20.628208 ===================================
670 09:28:20.628262 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
671 09:28:20.628315 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
672 09:28:20.628369 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 09:28:20.628422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
674 09:28:20.628475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
675 09:28:20.628528 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
676 09:28:20.628580 [ANA_INIT] flow start
677 09:28:20.628633 [ANA_INIT] PLL >>>>>>>>
678 09:28:20.628686 [ANA_INIT] PLL <<<<<<<<
679 09:28:20.628739 [ANA_INIT] MIDPI >>>>>>>>
680 09:28:20.628791 [ANA_INIT] MIDPI <<<<<<<<
681 09:28:20.628844 [ANA_INIT] DLL >>>>>>>>
682 09:28:20.628896 [ANA_INIT] flow end
683 09:28:20.628948 ============ LP4 DIFF to SE enter ============
684 09:28:20.629002 ============ LP4 DIFF to SE exit ============
685 09:28:20.629055 [ANA_INIT] <<<<<<<<<<<<<
686 09:28:20.629108 [Flow] Enable top DCM control >>>>>
687 09:28:20.629160 [Flow] Enable top DCM control <<<<<
688 09:28:20.629213 Enable DLL master slave shuffle
689 09:28:20.629265 ==============================================================
690 09:28:20.629318 Gating Mode config
691 09:28:20.629370 ==============================================================
692 09:28:20.629423 Config description:
693 09:28:20.629476 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
694 09:28:20.629530 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
695 09:28:20.629620 SELPH_MODE 0: By rank 1: By Phase
696 09:28:20.629685 ==============================================================
697 09:28:20.629740 GAT_TRACK_EN = 1
698 09:28:20.629823 RX_GATING_MODE = 2
699 09:28:20.629876 RX_GATING_TRACK_MODE = 2
700 09:28:20.629929 SELPH_MODE = 1
701 09:28:20.629981 PICG_EARLY_EN = 1
702 09:28:20.630033 VALID_LAT_VALUE = 1
703 09:28:20.630086 ==============================================================
704 09:28:20.630140 Enter into Gating configuration >>>>
705 09:28:20.630235 Exit from Gating configuration <<<<
706 09:28:20.630288 Enter into DVFS_PRE_config >>>>>
707 09:28:20.630341 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
708 09:28:20.630399 Exit from DVFS_PRE_config <<<<<
709 09:28:20.630452 Enter into PICG configuration >>>>
710 09:28:20.630504 Exit from PICG configuration <<<<
711 09:28:20.630557 [RX_INPUT] configuration >>>>>
712 09:28:20.630610 [RX_INPUT] configuration <<<<<
713 09:28:20.630663 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
714 09:28:20.630716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
715 09:28:20.630769 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
716 09:28:20.630823 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
717 09:28:20.630875 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
718 09:28:20.630928 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
719 09:28:20.630981 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
720 09:28:20.631034 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
721 09:28:20.631087 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
722 09:28:20.631140 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
723 09:28:20.631192 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
724 09:28:20.631245 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
725 09:28:20.631297 ===================================
726 09:28:20.631350 LPDDR4 DRAM CONFIGURATION
727 09:28:20.631402 ===================================
728 09:28:20.631455 EX_ROW_EN[0] = 0x0
729 09:28:20.631508 EX_ROW_EN[1] = 0x0
730 09:28:20.631560 LP4Y_EN = 0x0
731 09:28:20.631612 WORK_FSP = 0x0
732 09:28:20.631664 WL = 0x2
733 09:28:20.631716 RL = 0x2
734 09:28:20.631768 BL = 0x2
735 09:28:20.631821 RPST = 0x0
736 09:28:20.631872 RD_PRE = 0x0
737 09:28:20.631924 WR_PRE = 0x1
738 09:28:20.631977 WR_PST = 0x0
739 09:28:20.632028 DBI_WR = 0x0
740 09:28:20.632080 DBI_RD = 0x0
741 09:28:20.632132 OTF = 0x1
742 09:28:20.632184 ===================================
743 09:28:20.632237 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
744 09:28:20.632290 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
745 09:28:20.632342 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
746 09:28:20.632395 ===================================
747 09:28:20.632448 LPDDR4 DRAM CONFIGURATION
748 09:28:20.632500 ===================================
749 09:28:20.632552 EX_ROW_EN[0] = 0x10
750 09:28:20.632604 EX_ROW_EN[1] = 0x0
751 09:28:20.632656 LP4Y_EN = 0x0
752 09:28:20.632708 WORK_FSP = 0x0
753 09:28:20.632759 WL = 0x2
754 09:28:20.632812 RL = 0x2
755 09:28:20.632864 BL = 0x2
756 09:28:20.632916 RPST = 0x0
757 09:28:20.632968 RD_PRE = 0x0
758 09:28:20.633020 WR_PRE = 0x1
759 09:28:20.633072 WR_PST = 0x0
760 09:28:20.633124 DBI_WR = 0x0
761 09:28:20.633176 DBI_RD = 0x0
762 09:28:20.633228 OTF = 0x1
763 09:28:20.633280 ===================================
764 09:28:20.633333 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
765 09:28:20.633386 nWR fixed to 40
766 09:28:20.633439 [ModeRegInit_LP4] CH0 RK0
767 09:28:20.633491 [ModeRegInit_LP4] CH0 RK1
768 09:28:20.633543 [ModeRegInit_LP4] CH1 RK0
769 09:28:20.633595 [ModeRegInit_LP4] CH1 RK1
770 09:28:20.633648 match AC timing 13
771 09:28:20.633889 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
772 09:28:20.633949 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
773 09:28:20.634003 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
774 09:28:20.634057 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
775 09:28:20.634109 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
776 09:28:20.634167 [EMI DOE] emi_dcm 0
777 09:28:20.634289 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
778 09:28:20.634347 ==
779 09:28:20.634400 Dram Type= 6, Freq= 0, CH_0, rank 0
780 09:28:20.634453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 09:28:20.634507 ==
782 09:28:20.634560 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
783 09:28:20.634613 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
784 09:28:20.634666 [CA 0] Center 37 (6~68) winsize 63
785 09:28:20.634720 [CA 1] Center 36 (6~67) winsize 62
786 09:28:20.634773 [CA 2] Center 34 (4~65) winsize 62
787 09:28:20.634825 [CA 3] Center 34 (4~65) winsize 62
788 09:28:20.634878 [CA 4] Center 33 (3~64) winsize 62
789 09:28:20.634930 [CA 5] Center 33 (3~64) winsize 62
790 09:28:20.634982
791 09:28:20.635035 [CmdBusTrainingLP45] Vref(ca) range 1: 32
792 09:28:20.635088
793 09:28:20.635140 [CATrainingPosCal] consider 1 rank data
794 09:28:20.635193 u2DelayCellTimex100 = 270/100 ps
795 09:28:20.635245 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
796 09:28:20.635298 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
797 09:28:20.635351 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
798 09:28:20.635422 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
799 09:28:20.635489 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
800 09:28:20.635541 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
801 09:28:20.635593
802 09:28:20.635645 CA PerBit enable=1, Macro0, CA PI delay=33
803 09:28:20.635697
804 09:28:20.635749 [CBTSetCACLKResult] CA Dly = 33
805 09:28:20.635802 CS Dly: 6 (0~37)
806 09:28:20.635854 ==
807 09:28:20.635907 Dram Type= 6, Freq= 0, CH_0, rank 1
808 09:28:20.635960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
809 09:28:20.636013 ==
810 09:28:20.636066 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
811 09:28:20.636118 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
812 09:28:20.636171 [CA 0] Center 37 (6~68) winsize 63
813 09:28:20.636224 [CA 1] Center 37 (7~68) winsize 62
814 09:28:20.636276 [CA 2] Center 34 (4~65) winsize 62
815 09:28:20.636328 [CA 3] Center 34 (4~65) winsize 62
816 09:28:20.636397 [CA 4] Center 33 (3~64) winsize 62
817 09:28:20.636463 [CA 5] Center 33 (3~64) winsize 62
818 09:28:20.636516
819 09:28:20.636568 [CmdBusTrainingLP45] Vref(ca) range 1: 32
820 09:28:20.636620
821 09:28:20.636672 [CATrainingPosCal] consider 2 rank data
822 09:28:20.636725 u2DelayCellTimex100 = 270/100 ps
823 09:28:20.636777 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
824 09:28:20.636830 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
825 09:28:20.636883 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
826 09:28:20.636935 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
827 09:28:20.636987 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
828 09:28:20.637040 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
829 09:28:20.637092
830 09:28:20.637174 CA PerBit enable=1, Macro0, CA PI delay=33
831 09:28:20.637226
832 09:28:20.637278 [CBTSetCACLKResult] CA Dly = 33
833 09:28:20.637330 CS Dly: 6 (0~38)
834 09:28:20.637382
835 09:28:20.637434 ----->DramcWriteLeveling(PI) begin...
836 09:28:20.637487 ==
837 09:28:20.637540 Dram Type= 6, Freq= 0, CH_0, rank 0
838 09:28:20.637592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
839 09:28:20.637645 ==
840 09:28:20.637714 Write leveling (Byte 0): 33 => 33
841 09:28:20.637780 Write leveling (Byte 1): 30 => 30
842 09:28:20.637833 DramcWriteLeveling(PI) end<-----
843 09:28:20.637885
844 09:28:20.637937 ==
845 09:28:20.637989 Dram Type= 6, Freq= 0, CH_0, rank 0
846 09:28:20.638042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
847 09:28:20.638094 ==
848 09:28:20.638147 [Gating] SW mode calibration
849 09:28:20.638239 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
850 09:28:20.638294 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
851 09:28:20.638347 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
852 09:28:20.638401 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
853 09:28:20.638454 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 09:28:20.638508 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
855 09:28:20.638590 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 09:28:20.638645 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 09:28:20.638699 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 09:28:20.638752 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 09:28:20.638805 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 09:28:20.638857 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 09:28:20.638910 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 09:28:20.638963 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 09:28:20.639016 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 09:28:20.639069 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 09:28:20.639121 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 09:28:20.639174 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 09:28:20.639226 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 09:28:20.639283 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
869 09:28:20.639350 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
870 09:28:20.639402 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
871 09:28:20.639455 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 09:28:20.639507 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 09:28:20.639560 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 09:28:20.639612 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 09:28:20.639665 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 09:28:20.639741 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 09:28:20.639807 0 9 8 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
878 09:28:20.639859 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
879 09:28:20.640104 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 09:28:20.640166 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 09:28:20.640222 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 09:28:20.640276 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 09:28:20.640330 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 09:28:20.640383 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 09:28:20.640436 0 10 8 | B1->B0 | 3434 2929 | 0 1 | (0 0) (1 0)
886 09:28:20.640489 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
887 09:28:20.640541 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 09:28:20.640594 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 09:28:20.640646 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 09:28:20.640699 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 09:28:20.640751 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 09:28:20.640804 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 09:28:20.640856 0 11 8 | B1->B0 | 2323 3939 | 0 1 | (0 0) (0 0)
894 09:28:20.640909 0 11 12 | B1->B0 | 3a3a 4646 | 1 0 | (1 1) (0 0)
895 09:28:20.640961 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 09:28:20.641014 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 09:28:20.641066 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 09:28:20.641119 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 09:28:20.641171 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 09:28:20.641224 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
901 09:28:20.641277 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 09:28:20.641349 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 09:28:20.641439 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 09:28:20.641493 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 09:28:20.641546 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 09:28:20.641598 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 09:28:20.641651 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 09:28:20.641704 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 09:28:20.641757 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 09:28:20.641809 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 09:28:20.641862 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 09:28:20.641918 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 09:28:20.641972 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 09:28:20.642024 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 09:28:20.642081 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 09:28:20.642199 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
917 09:28:20.642271 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 09:28:20.642325 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
919 09:28:20.642378 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 09:28:20.642431 Total UI for P1: 0, mck2ui 16
921 09:28:20.642484 best dqsien dly found for B0: ( 0, 14, 8)
922 09:28:20.642537 Total UI for P1: 0, mck2ui 16
923 09:28:20.642589 best dqsien dly found for B1: ( 0, 14, 12)
924 09:28:20.642642 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
925 09:28:20.642694 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
926 09:28:20.642747
927 09:28:20.642799 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
928 09:28:20.642852 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
929 09:28:20.642905 [Gating] SW calibration Done
930 09:28:20.642957 ==
931 09:28:20.643010 Dram Type= 6, Freq= 0, CH_0, rank 0
932 09:28:20.643063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 09:28:20.643116 ==
934 09:28:20.643168 RX Vref Scan: 0
935 09:28:20.643220
936 09:28:20.643273 RX Vref 0 -> 0, step: 1
937 09:28:20.643325
938 09:28:20.643394 RX Delay -130 -> 252, step: 16
939 09:28:20.643449 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
940 09:28:20.643501 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
941 09:28:20.643554 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
942 09:28:20.643606 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
943 09:28:20.643659 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
944 09:28:20.643712 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
945 09:28:20.643764 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
946 09:28:20.643816 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
947 09:28:20.643868 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
948 09:28:20.643920 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
949 09:28:20.643973 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
950 09:28:20.644026 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
951 09:28:20.644078 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
952 09:28:20.644131 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
953 09:28:20.644183 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
954 09:28:20.644235 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
955 09:28:20.644288 ==
956 09:28:20.644341 Dram Type= 6, Freq= 0, CH_0, rank 0
957 09:28:20.644394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 09:28:20.644446 ==
959 09:28:20.644499 DQS Delay:
960 09:28:20.644551 DQS0 = 0, DQS1 = 0
961 09:28:20.644603 DQM Delay:
962 09:28:20.644655 DQM0 = 86, DQM1 = 70
963 09:28:20.644707 DQ Delay:
964 09:28:20.644759 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
965 09:28:20.644812 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
966 09:28:20.644864 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
967 09:28:20.644917 DQ12 =69, DQ13 =77, DQ14 =85, DQ15 =77
968 09:28:20.644969
969 09:28:20.645021
970 09:28:20.645072 ==
971 09:28:20.645125 Dram Type= 6, Freq= 0, CH_0, rank 0
972 09:28:20.645177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 09:28:20.645230 ==
974 09:28:20.645282
975 09:28:20.645334
976 09:28:20.645385 TX Vref Scan disable
977 09:28:20.645437 == TX Byte 0 ==
978 09:28:20.645488 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
979 09:28:20.645542 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
980 09:28:20.645594 == TX Byte 1 ==
981 09:28:20.645646 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
982 09:28:20.645698 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
983 09:28:20.645750 ==
984 09:28:20.645802 Dram Type= 6, Freq= 0, CH_0, rank 0
985 09:28:20.645855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 09:28:20.645907 ==
987 09:28:20.646185 TX Vref=22, minBit 2, minWin=27, winSum=440
988 09:28:20.646265 TX Vref=24, minBit 3, minWin=27, winSum=448
989 09:28:20.646321 TX Vref=26, minBit 8, minWin=27, winSum=448
990 09:28:20.646375 TX Vref=28, minBit 10, minWin=27, winSum=449
991 09:28:20.646429 TX Vref=30, minBit 10, minWin=27, winSum=451
992 09:28:20.646482 TX Vref=32, minBit 8, minWin=27, winSum=447
993 09:28:20.646535 [TxChooseVref] Worse bit 10, Min win 27, Win sum 451, Final Vref 30
994 09:28:20.646589
995 09:28:20.646641 Final TX Range 1 Vref 30
996 09:28:20.646694
997 09:28:20.646746 ==
998 09:28:20.646798 Dram Type= 6, Freq= 0, CH_0, rank 0
999 09:28:20.646851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 09:28:20.646904 ==
1001 09:28:20.646956
1002 09:28:20.647008
1003 09:28:20.647059 TX Vref Scan disable
1004 09:28:20.647112 == TX Byte 0 ==
1005 09:28:20.647164 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1006 09:28:20.647217 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1007 09:28:20.647270 == TX Byte 1 ==
1008 09:28:20.647322 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1009 09:28:20.647374 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1010 09:28:20.647426
1011 09:28:20.647480 [DATLAT]
1012 09:28:20.647533 Freq=800, CH0 RK0
1013 09:28:20.647585
1014 09:28:20.647637 DATLAT Default: 0xa
1015 09:28:20.647689 0, 0xFFFF, sum = 0
1016 09:28:20.647742 1, 0xFFFF, sum = 0
1017 09:28:20.647795 2, 0xFFFF, sum = 0
1018 09:28:20.647848 3, 0xFFFF, sum = 0
1019 09:28:20.647901 4, 0xFFFF, sum = 0
1020 09:28:20.647954 5, 0xFFFF, sum = 0
1021 09:28:20.648007 6, 0xFFFF, sum = 0
1022 09:28:20.648059 7, 0xFFFF, sum = 0
1023 09:28:20.648112 8, 0xFFFF, sum = 0
1024 09:28:20.648165 9, 0x0, sum = 1
1025 09:28:20.648224 10, 0x0, sum = 2
1026 09:28:20.648280 11, 0x0, sum = 3
1027 09:28:20.648333 12, 0x0, sum = 4
1028 09:28:20.648388 best_step = 10
1029 09:28:20.648440
1030 09:28:20.648492 ==
1031 09:28:20.648543 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 09:28:20.648596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 09:28:20.648647 ==
1034 09:28:20.648698 RX Vref Scan: 1
1035 09:28:20.648750
1036 09:28:20.648801 Set Vref Range= 32 -> 127
1037 09:28:20.648852
1038 09:28:20.648904 RX Vref 32 -> 127, step: 1
1039 09:28:20.648955
1040 09:28:20.649007 RX Delay -111 -> 252, step: 8
1041 09:28:20.649058
1042 09:28:20.649109 Set Vref, RX VrefLevel [Byte0]: 32
1043 09:28:20.649161 [Byte1]: 32
1044 09:28:20.649213
1045 09:28:20.649264 Set Vref, RX VrefLevel [Byte0]: 33
1046 09:28:20.649316 [Byte1]: 33
1047 09:28:20.649367
1048 09:28:20.649418 Set Vref, RX VrefLevel [Byte0]: 34
1049 09:28:20.649470 [Byte1]: 34
1050 09:28:20.649522
1051 09:28:20.649572 Set Vref, RX VrefLevel [Byte0]: 35
1052 09:28:20.649624 [Byte1]: 35
1053 09:28:20.649675
1054 09:28:20.649726 Set Vref, RX VrefLevel [Byte0]: 36
1055 09:28:20.649777 [Byte1]: 36
1056 09:28:20.649829
1057 09:28:20.649880 Set Vref, RX VrefLevel [Byte0]: 37
1058 09:28:20.649931 [Byte1]: 37
1059 09:28:20.649982
1060 09:28:20.650033 Set Vref, RX VrefLevel [Byte0]: 38
1061 09:28:20.650084 [Byte1]: 38
1062 09:28:20.650136
1063 09:28:20.650198 Set Vref, RX VrefLevel [Byte0]: 39
1064 09:28:20.650249 [Byte1]: 39
1065 09:28:20.650301
1066 09:28:20.650352 Set Vref, RX VrefLevel [Byte0]: 40
1067 09:28:20.650403 [Byte1]: 40
1068 09:28:20.650455
1069 09:28:20.650506 Set Vref, RX VrefLevel [Byte0]: 41
1070 09:28:20.650558 [Byte1]: 41
1071 09:28:20.650609
1072 09:28:20.650663 Set Vref, RX VrefLevel [Byte0]: 42
1073 09:28:20.650740 [Byte1]: 42
1074 09:28:20.650794
1075 09:28:20.650846 Set Vref, RX VrefLevel [Byte0]: 43
1076 09:28:20.650897 [Byte1]: 43
1077 09:28:20.650947
1078 09:28:20.650999 Set Vref, RX VrefLevel [Byte0]: 44
1079 09:28:20.651050 [Byte1]: 44
1080 09:28:20.651101
1081 09:28:20.651163 Set Vref, RX VrefLevel [Byte0]: 45
1082 09:28:20.651216 [Byte1]: 45
1083 09:28:20.651268
1084 09:28:20.651349 Set Vref, RX VrefLevel [Byte0]: 46
1085 09:28:20.651431 [Byte1]: 46
1086 09:28:20.651485
1087 09:28:20.651537 Set Vref, RX VrefLevel [Byte0]: 47
1088 09:28:20.651590 [Byte1]: 47
1089 09:28:20.651642
1090 09:28:20.651693 Set Vref, RX VrefLevel [Byte0]: 48
1091 09:28:20.651745 [Byte1]: 48
1092 09:28:20.651796
1093 09:28:20.651847 Set Vref, RX VrefLevel [Byte0]: 49
1094 09:28:20.651898 [Byte1]: 49
1095 09:28:20.651950
1096 09:28:20.652001 Set Vref, RX VrefLevel [Byte0]: 50
1097 09:28:20.652052 [Byte1]: 50
1098 09:28:20.652104
1099 09:28:20.652155 Set Vref, RX VrefLevel [Byte0]: 51
1100 09:28:20.652207 [Byte1]: 51
1101 09:28:20.652258
1102 09:28:20.652309 Set Vref, RX VrefLevel [Byte0]: 52
1103 09:28:20.652360 [Byte1]: 52
1104 09:28:20.652411
1105 09:28:20.652461 Set Vref, RX VrefLevel [Byte0]: 53
1106 09:28:20.652512 [Byte1]: 53
1107 09:28:20.652563
1108 09:28:20.652615 Set Vref, RX VrefLevel [Byte0]: 54
1109 09:28:20.652666 [Byte1]: 54
1110 09:28:20.652717
1111 09:28:20.652768 Set Vref, RX VrefLevel [Byte0]: 55
1112 09:28:20.652819 [Byte1]: 55
1113 09:28:20.652870
1114 09:28:20.652921 Set Vref, RX VrefLevel [Byte0]: 56
1115 09:28:20.652971 [Byte1]: 56
1116 09:28:20.653023
1117 09:28:20.653073 Set Vref, RX VrefLevel [Byte0]: 57
1118 09:28:20.653125 [Byte1]: 57
1119 09:28:20.653176
1120 09:28:20.653227 Set Vref, RX VrefLevel [Byte0]: 58
1121 09:28:20.653278 [Byte1]: 58
1122 09:28:20.653394
1123 09:28:20.653459 Set Vref, RX VrefLevel [Byte0]: 59
1124 09:28:20.653511 [Byte1]: 59
1125 09:28:20.653562
1126 09:28:20.653613 Set Vref, RX VrefLevel [Byte0]: 60
1127 09:28:20.653665 [Byte1]: 60
1128 09:28:20.653716
1129 09:28:20.653767 Set Vref, RX VrefLevel [Byte0]: 61
1130 09:28:20.653818 [Byte1]: 61
1131 09:28:20.653870
1132 09:28:20.653925 Set Vref, RX VrefLevel [Byte0]: 62
1133 09:28:20.654004 [Byte1]: 62
1134 09:28:20.654060
1135 09:28:20.654112 Set Vref, RX VrefLevel [Byte0]: 63
1136 09:28:20.654183 [Byte1]: 63
1137 09:28:20.654250
1138 09:28:20.654302 Set Vref, RX VrefLevel [Byte0]: 64
1139 09:28:20.654354 [Byte1]: 64
1140 09:28:20.654404
1141 09:28:20.654455 Set Vref, RX VrefLevel [Byte0]: 65
1142 09:28:20.654506 [Byte1]: 65
1143 09:28:20.654558
1144 09:28:20.654608 Set Vref, RX VrefLevel [Byte0]: 66
1145 09:28:20.654660 [Byte1]: 66
1146 09:28:20.654711
1147 09:28:20.654761 Set Vref, RX VrefLevel [Byte0]: 67
1148 09:28:20.654813 [Byte1]: 67
1149 09:28:20.654864
1150 09:28:20.654915 Set Vref, RX VrefLevel [Byte0]: 68
1151 09:28:20.654967 [Byte1]: 68
1152 09:28:20.655018
1153 09:28:20.655069 Set Vref, RX VrefLevel [Byte0]: 69
1154 09:28:20.655319 [Byte1]: 69
1155 09:28:20.655381
1156 09:28:20.655434 Set Vref, RX VrefLevel [Byte0]: 70
1157 09:28:20.655487 [Byte1]: 70
1158 09:28:20.655539
1159 09:28:20.655591 Set Vref, RX VrefLevel [Byte0]: 71
1160 09:28:20.655643 [Byte1]: 71
1161 09:28:20.655694
1162 09:28:20.655746 Set Vref, RX VrefLevel [Byte0]: 72
1163 09:28:20.655798 [Byte1]: 72
1164 09:28:20.655866
1165 09:28:20.655932 Set Vref, RX VrefLevel [Byte0]: 73
1166 09:28:20.655983 [Byte1]: 73
1167 09:28:20.656035
1168 09:28:20.656086 Set Vref, RX VrefLevel [Byte0]: 74
1169 09:28:20.656138 [Byte1]: 74
1170 09:28:20.656189
1171 09:28:20.656240 Set Vref, RX VrefLevel [Byte0]: 75
1172 09:28:20.656292 [Byte1]: 75
1173 09:28:20.656344
1174 09:28:20.656395 Set Vref, RX VrefLevel [Byte0]: 76
1175 09:28:20.656446 [Byte1]: 76
1176 09:28:20.656498
1177 09:28:20.656548 Set Vref, RX VrefLevel [Byte0]: 77
1178 09:28:20.656600 [Byte1]: 77
1179 09:28:20.656652
1180 09:28:20.656702 Set Vref, RX VrefLevel [Byte0]: 78
1181 09:28:20.656754 [Byte1]: 78
1182 09:28:20.656805
1183 09:28:20.656856 Set Vref, RX VrefLevel [Byte0]: 79
1184 09:28:20.656907 [Byte1]: 79
1185 09:28:20.656975
1186 09:28:20.657057 Set Vref, RX VrefLevel [Byte0]: 80
1187 09:28:20.657151 [Byte1]: 80
1188 09:28:20.657225
1189 09:28:20.657306 Final RX Vref Byte 0 = 62 to rank0
1190 09:28:20.657371 Final RX Vref Byte 1 = 51 to rank0
1191 09:28:20.657424 Final RX Vref Byte 0 = 62 to rank1
1192 09:28:20.657476 Final RX Vref Byte 1 = 51 to rank1==
1193 09:28:20.657542 Dram Type= 6, Freq= 0, CH_0, rank 0
1194 09:28:20.657610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1195 09:28:20.657662 ==
1196 09:28:20.657714 DQS Delay:
1197 09:28:20.657765 DQS0 = 0, DQS1 = 0
1198 09:28:20.657818 DQM Delay:
1199 09:28:20.657869 DQM0 = 86, DQM1 = 75
1200 09:28:20.657921 DQ Delay:
1201 09:28:20.657973 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1202 09:28:20.658024 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =100
1203 09:28:20.658076 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1204 09:28:20.658127 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1205 09:28:20.658219
1206 09:28:20.658273
1207 09:28:20.658324 [DQSOSCAuto] RK0, (LSB)MR18= 0x4627, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
1208 09:28:20.658377 CH0 RK0: MR19=606, MR18=4627
1209 09:28:20.658429 CH0_RK0: MR19=0x606, MR18=0x4627, DQSOSC=392, MR23=63, INC=96, DEC=64
1210 09:28:20.658482
1211 09:28:20.658533 ----->DramcWriteLeveling(PI) begin...
1212 09:28:20.658587 ==
1213 09:28:20.658639 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 09:28:20.658691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 09:28:20.658744 ==
1216 09:28:20.658795 Write leveling (Byte 0): 31 => 31
1217 09:28:20.658846 Write leveling (Byte 1): 30 => 30
1218 09:28:20.658898 DramcWriteLeveling(PI) end<-----
1219 09:28:20.658950
1220 09:28:20.659027 ==
1221 09:28:20.659084 Dram Type= 6, Freq= 0, CH_0, rank 1
1222 09:28:20.659136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1223 09:28:20.659189 ==
1224 09:28:20.659241 [Gating] SW mode calibration
1225 09:28:20.659292 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1226 09:28:20.659347 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1227 09:28:20.659400 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1228 09:28:20.659452 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1229 09:28:20.659504 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1230 09:28:20.659556 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1231 09:28:20.659608 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 09:28:20.659660 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 09:28:20.659711 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 09:28:20.659762 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 09:28:20.659814 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 09:28:20.659866 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 09:28:20.659918 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 09:28:20.659969 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 09:28:20.660020 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 09:28:20.660071 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 09:28:20.660123 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 09:28:20.660174 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 09:28:20.660226 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 09:28:20.660277 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1245 09:28:20.660329 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1246 09:28:20.660380 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 09:28:20.660431 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 09:28:20.660483 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 09:28:20.660534 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 09:28:20.660592 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 09:28:20.660659 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 09:28:20.660712 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 09:28:20.660765 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1254 09:28:20.660816 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 09:28:20.660868 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 09:28:20.660919 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1257 09:28:20.660971 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1258 09:28:20.661022 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1259 09:28:20.661074 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1260 09:28:20.661125 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
1261 09:28:20.661177 0 10 8 | B1->B0 | 3030 2929 | 1 0 | (1 0) (0 0)
1262 09:28:20.661228 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 09:28:20.661297 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 09:28:20.661387 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 09:28:20.661471 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 09:28:20.661527 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 09:28:20.661772 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1268 09:28:20.661832 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
1269 09:28:20.661886 0 11 8 | B1->B0 | 3030 3939 | 0 0 | (1 1) (0 0)
1270 09:28:20.661938 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1271 09:28:20.661991 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 09:28:20.662043 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 09:28:20.662095 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1274 09:28:20.662147 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1275 09:28:20.662240 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1276 09:28:20.662293 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1277 09:28:20.662345 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1278 09:28:20.662397 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 09:28:20.662449 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 09:28:20.662501 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 09:28:20.662552 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 09:28:20.662603 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 09:28:20.662655 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 09:28:20.662706 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 09:28:20.662757 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 09:28:20.662809 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 09:28:20.662860 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 09:28:20.662918 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 09:28:20.662991 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 09:28:20.663045 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 09:28:20.663097 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 09:28:20.663149 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1293 09:28:20.663201 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1294 09:28:20.663253 Total UI for P1: 0, mck2ui 16
1295 09:28:20.663306 best dqsien dly found for B0: ( 0, 14, 4)
1296 09:28:20.663358 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1297 09:28:20.663409 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1298 09:28:20.663462 Total UI for P1: 0, mck2ui 16
1299 09:28:20.663514 best dqsien dly found for B1: ( 0, 14, 8)
1300 09:28:20.663565 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1301 09:28:20.663616 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1302 09:28:20.663668
1303 09:28:20.663719 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1304 09:28:20.663771 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1305 09:28:20.663822 [Gating] SW calibration Done
1306 09:28:20.663873 ==
1307 09:28:20.663925 Dram Type= 6, Freq= 0, CH_0, rank 1
1308 09:28:20.663977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1309 09:28:20.664030 ==
1310 09:28:20.664087 RX Vref Scan: 0
1311 09:28:20.664161
1312 09:28:20.664215 RX Vref 0 -> 0, step: 1
1313 09:28:20.664267
1314 09:28:20.664320 RX Delay -130 -> 252, step: 16
1315 09:28:20.664372 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1316 09:28:20.664424 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1317 09:28:20.664476 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1318 09:28:20.664528 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1319 09:28:20.664580 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1320 09:28:20.664631 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1321 09:28:20.664683 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1322 09:28:20.664734 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1323 09:28:20.664786 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1324 09:28:20.664837 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1325 09:28:20.664889 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1326 09:28:20.664940 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1327 09:28:20.664991 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1328 09:28:20.665043 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1329 09:28:20.665095 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1330 09:28:20.665146 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1331 09:28:20.665198 ==
1332 09:28:20.665249 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 09:28:20.665301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 09:28:20.665353 ==
1335 09:28:20.665404 DQS Delay:
1336 09:28:20.665455 DQS0 = 0, DQS1 = 0
1337 09:28:20.665506 DQM Delay:
1338 09:28:20.665558 DQM0 = 84, DQM1 = 78
1339 09:28:20.665609 DQ Delay:
1340 09:28:20.665661 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1341 09:28:20.665713 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1342 09:28:20.665764 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1343 09:28:20.665815 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1344 09:28:20.665866
1345 09:28:20.665917
1346 09:28:20.665968 ==
1347 09:28:20.666020 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 09:28:20.666072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 09:28:20.666124 ==
1350 09:28:20.666186
1351 09:28:20.666239
1352 09:28:20.666290 TX Vref Scan disable
1353 09:28:20.666342 == TX Byte 0 ==
1354 09:28:20.666394 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1355 09:28:20.666446 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1356 09:28:20.666498 == TX Byte 1 ==
1357 09:28:20.666549 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1358 09:28:20.666601 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1359 09:28:20.666653 ==
1360 09:28:20.666705 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 09:28:20.666757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 09:28:20.666808 ==
1363 09:28:20.666875 TX Vref=22, minBit 8, minWin=26, winSum=443
1364 09:28:20.666938 TX Vref=24, minBit 3, minWin=27, winSum=448
1365 09:28:20.666990 TX Vref=26, minBit 8, minWin=27, winSum=448
1366 09:28:20.667042 TX Vref=28, minBit 8, minWin=27, winSum=445
1367 09:28:20.667093 TX Vref=30, minBit 9, minWin=27, winSum=450
1368 09:28:20.667145 TX Vref=32, minBit 8, minWin=27, winSum=445
1369 09:28:20.667197 [TxChooseVref] Worse bit 9, Min win 27, Win sum 450, Final Vref 30
1370 09:28:20.667248
1371 09:28:20.667331 Final TX Range 1 Vref 30
1372 09:28:20.667410
1373 09:28:20.667461 ==
1374 09:28:20.667512 Dram Type= 6, Freq= 0, CH_0, rank 1
1375 09:28:20.667563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 09:28:20.667615 ==
1377 09:28:20.667665
1378 09:28:20.667716
1379 09:28:20.667767 TX Vref Scan disable
1380 09:28:20.667818 == TX Byte 0 ==
1381 09:28:20.667869 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1382 09:28:20.668115 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1383 09:28:20.668213 == TX Byte 1 ==
1384 09:28:20.668297 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1385 09:28:20.668353 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1386 09:28:20.668420
1387 09:28:20.668472 [DATLAT]
1388 09:28:20.668524 Freq=800, CH0 RK1
1389 09:28:20.668577
1390 09:28:20.668628 DATLAT Default: 0xa
1391 09:28:20.668679 0, 0xFFFF, sum = 0
1392 09:28:20.668732 1, 0xFFFF, sum = 0
1393 09:28:20.668784 2, 0xFFFF, sum = 0
1394 09:28:20.668836 3, 0xFFFF, sum = 0
1395 09:28:20.668888 4, 0xFFFF, sum = 0
1396 09:28:20.668939 5, 0xFFFF, sum = 0
1397 09:28:20.668991 6, 0xFFFF, sum = 0
1398 09:28:20.669043 7, 0xFFFF, sum = 0
1399 09:28:20.669095 8, 0xFFFF, sum = 0
1400 09:28:20.669147 9, 0x0, sum = 1
1401 09:28:20.669198 10, 0x0, sum = 2
1402 09:28:20.669250 11, 0x0, sum = 3
1403 09:28:20.669302 12, 0x0, sum = 4
1404 09:28:20.669355 best_step = 10
1405 09:28:20.669406
1406 09:28:20.669456 ==
1407 09:28:20.669507 Dram Type= 6, Freq= 0, CH_0, rank 1
1408 09:28:20.669560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 09:28:20.669612 ==
1410 09:28:20.669663 RX Vref Scan: 0
1411 09:28:20.669713
1412 09:28:20.669764 RX Vref 0 -> 0, step: 1
1413 09:28:20.669815
1414 09:28:20.669865 RX Delay -95 -> 252, step: 8
1415 09:28:20.669917 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1416 09:28:20.669968 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1417 09:28:20.670019 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1418 09:28:20.670070 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1419 09:28:20.670122 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1420 09:28:20.670214 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1421 09:28:20.670267 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1422 09:28:20.670318 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1423 09:28:20.670370 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1424 09:28:20.670420 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1425 09:28:20.670471 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1426 09:28:20.670523 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1427 09:28:20.670574 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1428 09:28:20.670625 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1429 09:28:20.670676 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1430 09:28:20.670727 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1431 09:28:20.670778 ==
1432 09:28:20.670829 Dram Type= 6, Freq= 0, CH_0, rank 1
1433 09:28:20.670880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 09:28:20.670932 ==
1435 09:28:20.670982 DQS Delay:
1436 09:28:20.671033 DQS0 = 0, DQS1 = 0
1437 09:28:20.671083 DQM Delay:
1438 09:28:20.671159 DQM0 = 85, DQM1 = 76
1439 09:28:20.671216 DQ Delay:
1440 09:28:20.671268 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =80
1441 09:28:20.671319 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =92
1442 09:28:20.671371 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
1443 09:28:20.671423 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1444 09:28:20.671475
1445 09:28:20.671526
1446 09:28:20.671577 [DQSOSCAuto] RK1, (LSB)MR18= 0x4209, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
1447 09:28:20.671629 CH0 RK1: MR19=606, MR18=4209
1448 09:28:20.671721 CH0_RK1: MR19=0x606, MR18=0x4209, DQSOSC=393, MR23=63, INC=95, DEC=63
1449 09:28:20.671773 [RxdqsGatingPostProcess] freq 800
1450 09:28:20.671824 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1451 09:28:20.671876 Pre-setting of DQS Precalculation
1452 09:28:20.671949 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1453 09:28:20.672002 ==
1454 09:28:20.672053 Dram Type= 6, Freq= 0, CH_1, rank 0
1455 09:28:20.672105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 09:28:20.672156 ==
1457 09:28:20.672208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1458 09:28:20.672259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1459 09:28:20.672311 [CA 0] Center 36 (6~67) winsize 62
1460 09:28:20.672363 [CA 1] Center 36 (6~67) winsize 62
1461 09:28:20.672414 [CA 2] Center 34 (4~65) winsize 62
1462 09:28:20.672465 [CA 3] Center 34 (3~65) winsize 63
1463 09:28:20.672516 [CA 4] Center 34 (4~65) winsize 62
1464 09:28:20.672567 [CA 5] Center 34 (3~65) winsize 63
1465 09:28:20.672618
1466 09:28:20.672669 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1467 09:28:20.672720
1468 09:28:20.672771 [CATrainingPosCal] consider 1 rank data
1469 09:28:20.672823 u2DelayCellTimex100 = 270/100 ps
1470 09:28:20.672874 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1471 09:28:20.672925 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1472 09:28:20.672976 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1473 09:28:20.673028 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1474 09:28:20.673078 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1475 09:28:20.673129 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1476 09:28:20.673179
1477 09:28:20.673230 CA PerBit enable=1, Macro0, CA PI delay=34
1478 09:28:20.673281
1479 09:28:20.673345 [CBTSetCACLKResult] CA Dly = 34
1480 09:28:20.673398 CS Dly: 5 (0~36)
1481 09:28:20.673450 ==
1482 09:28:20.673502 Dram Type= 6, Freq= 0, CH_1, rank 1
1483 09:28:20.673554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1484 09:28:20.673605 ==
1485 09:28:20.673656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1486 09:28:20.673707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1487 09:28:20.673759 [CA 0] Center 36 (6~67) winsize 62
1488 09:28:20.673811 [CA 1] Center 36 (6~67) winsize 62
1489 09:28:20.673861 [CA 2] Center 34 (4~65) winsize 62
1490 09:28:20.673912 [CA 3] Center 34 (3~65) winsize 63
1491 09:28:20.673962 [CA 4] Center 34 (4~65) winsize 62
1492 09:28:20.674014 [CA 5] Center 34 (3~65) winsize 63
1493 09:28:20.674064
1494 09:28:20.674115 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1495 09:28:20.674175
1496 09:28:20.674227 [CATrainingPosCal] consider 2 rank data
1497 09:28:20.674279 u2DelayCellTimex100 = 270/100 ps
1498 09:28:20.674330 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1499 09:28:20.674381 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1500 09:28:20.674433 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1501 09:28:20.674484 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1502 09:28:20.674535 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1503 09:28:20.674586 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1504 09:28:20.674637
1505 09:28:20.674688 CA PerBit enable=1, Macro0, CA PI delay=34
1506 09:28:20.674739
1507 09:28:20.674790 [CBTSetCACLKResult] CA Dly = 34
1508 09:28:20.674842 CS Dly: 6 (0~38)
1509 09:28:20.674892
1510 09:28:20.674943 ----->DramcWriteLeveling(PI) begin...
1511 09:28:20.674995 ==
1512 09:28:20.675046 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 09:28:20.675097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1514 09:28:20.675149 ==
1515 09:28:20.675227 Write leveling (Byte 0): 26 => 26
1516 09:28:20.675486 Write leveling (Byte 1): 26 => 26
1517 09:28:20.675550 DramcWriteLeveling(PI) end<-----
1518 09:28:20.675605
1519 09:28:20.675657 ==
1520 09:28:20.675709 Dram Type= 6, Freq= 0, CH_1, rank 0
1521 09:28:20.675761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1522 09:28:20.675815 ==
1523 09:28:20.675866 [Gating] SW mode calibration
1524 09:28:20.675919 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1525 09:28:20.675983 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1526 09:28:20.676037 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1527 09:28:20.676089 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1528 09:28:20.676142 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 09:28:20.676192 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 09:28:20.676243 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 09:28:20.676294 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 09:28:20.676345 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 09:28:20.676396 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 09:28:20.676447 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 09:28:20.676498 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 09:28:20.676549 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 09:28:20.676601 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 09:28:20.676652 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 09:28:20.676704 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 09:28:20.676755 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 09:28:20.676806 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 09:28:20.676857 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1543 09:28:20.676908 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1544 09:28:20.676959 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 09:28:20.677010 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 09:28:20.677061 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 09:28:20.677112 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 09:28:20.677163 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 09:28:20.677214 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 09:28:20.677265 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 09:28:20.677316 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 09:28:20.677367 0 9 8 | B1->B0 | 2b2b 3030 | 0 1 | (0 0) (1 1)
1553 09:28:20.677418 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 09:28:20.677468 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1555 09:28:20.677519 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1556 09:28:20.677571 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1557 09:28:20.677622 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1558 09:28:20.677674 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1559 09:28:20.677725 0 10 4 | B1->B0 | 3434 3232 | 0 0 | (0 1) (0 1)
1560 09:28:20.677776 0 10 8 | B1->B0 | 2d2d 2a2a | 0 0 | (0 0) (0 0)
1561 09:28:20.677826 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 09:28:20.677878 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 09:28:20.677929 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 09:28:20.677979 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1565 09:28:20.678030 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1566 09:28:20.678082 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 09:28:20.678133 0 11 4 | B1->B0 | 2727 2727 | 0 0 | (0 0) (0 0)
1568 09:28:20.678195 0 11 8 | B1->B0 | 3d3d 4242 | 1 0 | (0 0) (0 0)
1569 09:28:20.678247 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 09:28:20.678298 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1571 09:28:20.678349 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1572 09:28:20.678399 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1573 09:28:20.678451 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1574 09:28:20.678502 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1575 09:28:20.678553 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1576 09:28:20.678604 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1577 09:28:20.678672 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 09:28:20.678726 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 09:28:20.678777 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 09:28:20.678827 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 09:28:20.678878 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 09:28:20.678929 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 09:28:20.678980 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 09:28:20.679031 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 09:28:20.679101 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 09:28:20.679159 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 09:28:20.679211 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 09:28:20.679262 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 09:28:20.679315 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 09:28:20.679366 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 09:28:20.679417 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1592 09:28:20.679468 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1593 09:28:20.679519 Total UI for P1: 0, mck2ui 16
1594 09:28:20.679571 best dqsien dly found for B0: ( 0, 14, 4)
1595 09:28:20.679622 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1596 09:28:20.679673 Total UI for P1: 0, mck2ui 16
1597 09:28:20.679725 best dqsien dly found for B1: ( 0, 14, 8)
1598 09:28:20.679776 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1599 09:28:20.679828 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1600 09:28:20.679878
1601 09:28:20.679929 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1602 09:28:20.680173 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1603 09:28:20.680231 [Gating] SW calibration Done
1604 09:28:20.680283 ==
1605 09:28:20.680336 Dram Type= 6, Freq= 0, CH_1, rank 0
1606 09:28:20.680387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1607 09:28:20.680439 ==
1608 09:28:20.680491 RX Vref Scan: 0
1609 09:28:20.680542
1610 09:28:20.680593 RX Vref 0 -> 0, step: 1
1611 09:28:20.680644
1612 09:28:20.680694 RX Delay -130 -> 252, step: 16
1613 09:28:20.680745 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1614 09:28:20.680795 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1615 09:28:20.680847 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1616 09:28:20.680898 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1617 09:28:20.680948 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1618 09:28:20.681000 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1619 09:28:20.681051 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1620 09:28:20.681102 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1621 09:28:20.681154 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1622 09:28:20.681205 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1623 09:28:20.681256 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1624 09:28:20.681307 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1625 09:28:20.681358 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1626 09:28:20.681409 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1627 09:28:20.681461 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1628 09:28:20.681512 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1629 09:28:20.681564 ==
1630 09:28:20.681614 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 09:28:20.681665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 09:28:20.681716 ==
1633 09:28:20.681767 DQS Delay:
1634 09:28:20.681818 DQS0 = 0, DQS1 = 0
1635 09:28:20.681868 DQM Delay:
1636 09:28:20.681919 DQM0 = 89, DQM1 = 78
1637 09:28:20.681969 DQ Delay:
1638 09:28:20.682021 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1639 09:28:20.682071 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1640 09:28:20.682122 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1641 09:28:20.682185 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1642 09:28:20.682239
1643 09:28:20.682289
1644 09:28:20.682339 ==
1645 09:28:20.682391 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 09:28:20.682441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 09:28:20.682493 ==
1648 09:28:20.682543
1649 09:28:20.682593
1650 09:28:20.682644 TX Vref Scan disable
1651 09:28:20.682696 == TX Byte 0 ==
1652 09:28:20.682747 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1653 09:28:20.682798 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1654 09:28:20.682849 == TX Byte 1 ==
1655 09:28:20.682899 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1656 09:28:20.682951 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1657 09:28:20.683001 ==
1658 09:28:20.683052 Dram Type= 6, Freq= 0, CH_1, rank 0
1659 09:28:20.683103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1660 09:28:20.683154 ==
1661 09:28:20.683205 TX Vref=22, minBit 10, minWin=26, winSum=443
1662 09:28:20.683256 TX Vref=24, minBit 9, minWin=27, winSum=446
1663 09:28:20.683307 TX Vref=26, minBit 9, minWin=27, winSum=451
1664 09:28:20.683360 TX Vref=28, minBit 15, minWin=27, winSum=452
1665 09:28:20.683439 TX Vref=30, minBit 9, minWin=27, winSum=451
1666 09:28:20.683492 TX Vref=32, minBit 8, minWin=27, winSum=446
1667 09:28:20.683544 [TxChooseVref] Worse bit 15, Min win 27, Win sum 452, Final Vref 28
1668 09:28:20.683596
1669 09:28:20.683647 Final TX Range 1 Vref 28
1670 09:28:20.683698
1671 09:28:20.683749 ==
1672 09:28:20.683800 Dram Type= 6, Freq= 0, CH_1, rank 0
1673 09:28:20.683851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1674 09:28:20.683902 ==
1675 09:28:20.683953
1676 09:28:20.684003
1677 09:28:20.684053 TX Vref Scan disable
1678 09:28:20.684104 == TX Byte 0 ==
1679 09:28:20.684155 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1680 09:28:20.684207 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1681 09:28:20.684258 == TX Byte 1 ==
1682 09:28:20.684309 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1683 09:28:20.684360 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1684 09:28:20.684411
1685 09:28:20.684461 [DATLAT]
1686 09:28:20.684512 Freq=800, CH1 RK0
1687 09:28:20.684563
1688 09:28:20.684613 DATLAT Default: 0xa
1689 09:28:20.684664 0, 0xFFFF, sum = 0
1690 09:28:20.684716 1, 0xFFFF, sum = 0
1691 09:28:20.684768 2, 0xFFFF, sum = 0
1692 09:28:20.684820 3, 0xFFFF, sum = 0
1693 09:28:20.684871 4, 0xFFFF, sum = 0
1694 09:28:20.684922 5, 0xFFFF, sum = 0
1695 09:28:20.684974 6, 0xFFFF, sum = 0
1696 09:28:20.685025 7, 0xFFFF, sum = 0
1697 09:28:20.685077 8, 0xFFFF, sum = 0
1698 09:28:20.685129 9, 0x0, sum = 1
1699 09:28:20.685180 10, 0x0, sum = 2
1700 09:28:20.685231 11, 0x0, sum = 3
1701 09:28:20.685283 12, 0x0, sum = 4
1702 09:28:20.685335 best_step = 10
1703 09:28:20.685385
1704 09:28:20.685435 ==
1705 09:28:20.685486 Dram Type= 6, Freq= 0, CH_1, rank 0
1706 09:28:20.685537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1707 09:28:20.685588 ==
1708 09:28:20.685639 RX Vref Scan: 1
1709 09:28:20.685690
1710 09:28:20.685740 Set Vref Range= 32 -> 127
1711 09:28:20.685791
1712 09:28:20.685842 RX Vref 32 -> 127, step: 1
1713 09:28:20.685894
1714 09:28:20.685945 RX Delay -95 -> 252, step: 8
1715 09:28:20.685995
1716 09:28:20.686046 Set Vref, RX VrefLevel [Byte0]: 32
1717 09:28:20.686096 [Byte1]: 32
1718 09:28:20.686147
1719 09:28:20.686247 Set Vref, RX VrefLevel [Byte0]: 33
1720 09:28:20.686300 [Byte1]: 33
1721 09:28:20.686351
1722 09:28:20.686402 Set Vref, RX VrefLevel [Byte0]: 34
1723 09:28:20.686454 [Byte1]: 34
1724 09:28:20.686505
1725 09:28:20.686556 Set Vref, RX VrefLevel [Byte0]: 35
1726 09:28:20.686607 [Byte1]: 35
1727 09:28:20.686658
1728 09:28:20.686713 Set Vref, RX VrefLevel [Byte0]: 36
1729 09:28:20.686778 [Byte1]: 36
1730 09:28:20.686830
1731 09:28:20.686881 Set Vref, RX VrefLevel [Byte0]: 37
1732 09:28:20.686932 [Byte1]: 37
1733 09:28:20.686983
1734 09:28:20.687034 Set Vref, RX VrefLevel [Byte0]: 38
1735 09:28:20.687084 [Byte1]: 38
1736 09:28:20.687135
1737 09:28:20.687185 Set Vref, RX VrefLevel [Byte0]: 39
1738 09:28:20.687236 [Byte1]: 39
1739 09:28:20.687287
1740 09:28:20.687337 Set Vref, RX VrefLevel [Byte0]: 40
1741 09:28:20.687388 [Byte1]: 40
1742 09:28:20.687439
1743 09:28:20.687490 Set Vref, RX VrefLevel [Byte0]: 41
1744 09:28:20.687540 [Byte1]: 41
1745 09:28:20.687592
1746 09:28:20.687642 Set Vref, RX VrefLevel [Byte0]: 42
1747 09:28:20.687692 [Byte1]: 42
1748 09:28:20.687743
1749 09:28:20.687824 Set Vref, RX VrefLevel [Byte0]: 43
1750 09:28:20.687877 [Byte1]: 43
1751 09:28:20.687929
1752 09:28:20.687980 Set Vref, RX VrefLevel [Byte0]: 44
1753 09:28:20.688031 [Byte1]: 44
1754 09:28:20.688082
1755 09:28:20.688133 Set Vref, RX VrefLevel [Byte0]: 45
1756 09:28:20.688185 [Byte1]: 45
1757 09:28:20.688236
1758 09:28:20.688287 Set Vref, RX VrefLevel [Byte0]: 46
1759 09:28:20.688532 [Byte1]: 46
1760 09:28:20.688600
1761 09:28:20.688653 Set Vref, RX VrefLevel [Byte0]: 47
1762 09:28:20.688706 [Byte1]: 47
1763 09:28:20.688758
1764 09:28:20.688808 Set Vref, RX VrefLevel [Byte0]: 48
1765 09:28:20.688860 [Byte1]: 48
1766 09:28:20.688911
1767 09:28:20.688962 Set Vref, RX VrefLevel [Byte0]: 49
1768 09:28:20.689014 [Byte1]: 49
1769 09:28:20.689065
1770 09:28:20.689116 Set Vref, RX VrefLevel [Byte0]: 50
1771 09:28:20.689167 [Byte1]: 50
1772 09:28:20.689219
1773 09:28:20.689269 Set Vref, RX VrefLevel [Byte0]: 51
1774 09:28:20.689320 [Byte1]: 51
1775 09:28:20.689372
1776 09:28:20.689422 Set Vref, RX VrefLevel [Byte0]: 52
1777 09:28:20.689473 [Byte1]: 52
1778 09:28:20.689526
1779 09:28:20.689577 Set Vref, RX VrefLevel [Byte0]: 53
1780 09:28:20.689628 [Byte1]: 53
1781 09:28:20.689679
1782 09:28:20.689730 Set Vref, RX VrefLevel [Byte0]: 54
1783 09:28:20.689781 [Byte1]: 54
1784 09:28:20.689845
1785 09:28:20.689900 Set Vref, RX VrefLevel [Byte0]: 55
1786 09:28:20.689951 [Byte1]: 55
1787 09:28:20.690002
1788 09:28:20.690053 Set Vref, RX VrefLevel [Byte0]: 56
1789 09:28:20.690105 [Byte1]: 56
1790 09:28:20.690156
1791 09:28:20.690252 Set Vref, RX VrefLevel [Byte0]: 57
1792 09:28:20.690304 [Byte1]: 57
1793 09:28:20.690355
1794 09:28:20.690406 Set Vref, RX VrefLevel [Byte0]: 58
1795 09:28:20.690457 [Byte1]: 58
1796 09:28:20.690508
1797 09:28:20.690559 Set Vref, RX VrefLevel [Byte0]: 59
1798 09:28:20.690616 [Byte1]: 59
1799 09:28:20.690668
1800 09:28:20.690718 Set Vref, RX VrefLevel [Byte0]: 60
1801 09:28:20.690769 [Byte1]: 60
1802 09:28:20.690820
1803 09:28:20.690871 Set Vref, RX VrefLevel [Byte0]: 61
1804 09:28:20.690922 [Byte1]: 61
1805 09:28:20.690972
1806 09:28:20.691023 Set Vref, RX VrefLevel [Byte0]: 62
1807 09:28:20.691074 [Byte1]: 62
1808 09:28:20.691125
1809 09:28:20.691175 Set Vref, RX VrefLevel [Byte0]: 63
1810 09:28:20.691226 [Byte1]: 63
1811 09:28:20.691277
1812 09:28:20.691328 Set Vref, RX VrefLevel [Byte0]: 64
1813 09:28:20.691379 [Byte1]: 64
1814 09:28:20.691429
1815 09:28:20.691480 Set Vref, RX VrefLevel [Byte0]: 65
1816 09:28:20.691530 [Byte1]: 65
1817 09:28:20.691581
1818 09:28:20.691632 Set Vref, RX VrefLevel [Byte0]: 66
1819 09:28:20.691682 [Byte1]: 66
1820 09:28:20.691733
1821 09:28:20.691783 Set Vref, RX VrefLevel [Byte0]: 67
1822 09:28:20.691834 [Byte1]: 67
1823 09:28:20.691886
1824 09:28:20.691936 Set Vref, RX VrefLevel [Byte0]: 68
1825 09:28:20.691988 [Byte1]: 68
1826 09:28:20.692038
1827 09:28:20.692089 Set Vref, RX VrefLevel [Byte0]: 69
1828 09:28:20.692140 [Byte1]: 69
1829 09:28:20.692191
1830 09:28:20.692242 Set Vref, RX VrefLevel [Byte0]: 70
1831 09:28:20.692292 [Byte1]: 70
1832 09:28:20.692346
1833 09:28:20.692397 Set Vref, RX VrefLevel [Byte0]: 71
1834 09:28:20.692447 [Byte1]: 71
1835 09:28:20.692513
1836 09:28:20.692574 Set Vref, RX VrefLevel [Byte0]: 72
1837 09:28:20.692626 [Byte1]: 72
1838 09:28:20.692678
1839 09:28:20.692729 Set Vref, RX VrefLevel [Byte0]: 73
1840 09:28:20.692781 [Byte1]: 73
1841 09:28:20.692833
1842 09:28:20.692884 Set Vref, RX VrefLevel [Byte0]: 74
1843 09:28:20.692935 [Byte1]: 74
1844 09:28:20.692985
1845 09:28:20.693036 Final RX Vref Byte 0 = 60 to rank0
1846 09:28:20.693088 Final RX Vref Byte 1 = 63 to rank0
1847 09:28:20.693140 Final RX Vref Byte 0 = 60 to rank1
1848 09:28:20.693191 Final RX Vref Byte 1 = 63 to rank1==
1849 09:28:20.693242 Dram Type= 6, Freq= 0, CH_1, rank 0
1850 09:28:20.693294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1851 09:28:20.693345 ==
1852 09:28:20.693412 DQS Delay:
1853 09:28:20.693466 DQS0 = 0, DQS1 = 0
1854 09:28:20.693517 DQM Delay:
1855 09:28:20.693568 DQM0 = 86, DQM1 = 79
1856 09:28:20.693619 DQ Delay:
1857 09:28:20.693670 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1858 09:28:20.693722 DQ4 =80, DQ5 =100, DQ6 =96, DQ7 =80
1859 09:28:20.693773 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1860 09:28:20.693824 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1861 09:28:20.693875
1862 09:28:20.693926
1863 09:28:20.693978 [DQSOSCAuto] RK0, (LSB)MR18= 0x331f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
1864 09:28:20.694030 CH1 RK0: MR19=606, MR18=331F
1865 09:28:20.694082 CH1_RK0: MR19=0x606, MR18=0x331F, DQSOSC=396, MR23=63, INC=94, DEC=62
1866 09:28:20.694133
1867 09:28:20.694210 ----->DramcWriteLeveling(PI) begin...
1868 09:28:20.694279 ==
1869 09:28:20.694331 Dram Type= 6, Freq= 0, CH_1, rank 1
1870 09:28:20.694382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1871 09:28:20.694434 ==
1872 09:28:20.694485 Write leveling (Byte 0): 25 => 25
1873 09:28:20.694536 Write leveling (Byte 1): 26 => 26
1874 09:28:20.694587 DramcWriteLeveling(PI) end<-----
1875 09:28:20.694638
1876 09:28:20.694689 ==
1877 09:28:20.694739 Dram Type= 6, Freq= 0, CH_1, rank 1
1878 09:28:20.694791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1879 09:28:20.694842 ==
1880 09:28:20.694893 [Gating] SW mode calibration
1881 09:28:20.694946 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1882 09:28:20.694998 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1883 09:28:20.695050 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1884 09:28:20.695101 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1885 09:28:20.695153 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 09:28:20.695204 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 09:28:20.695255 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 09:28:20.695306 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 09:28:20.695357 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 09:28:20.695412 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 09:28:20.695478 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 09:28:20.695531 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 09:28:20.695582 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 09:28:20.695633 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 09:28:20.695684 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 09:28:20.695735 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 09:28:20.695786 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 09:28:20.696027 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 09:28:20.696085 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1900 09:28:20.696137 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1901 09:28:20.696188 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1902 09:28:20.696240 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 09:28:20.696291 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 09:28:20.696342 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 09:28:20.696394 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 09:28:20.696445 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 09:28:20.696495 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 09:28:20.696547 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 09:28:20.696598 0 9 8 | B1->B0 | 3232 2b2b | 1 1 | (1 1) (1 1)
1910 09:28:20.696650 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 1)
1911 09:28:20.696700 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 09:28:20.696751 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1913 09:28:20.696803 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1914 09:28:20.696854 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 09:28:20.696906 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 09:28:20.696957 0 10 4 | B1->B0 | 3030 3434 | 1 1 | (1 0) (1 0)
1917 09:28:20.697008 0 10 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
1918 09:28:20.697059 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 09:28:20.697111 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 09:28:20.697161 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 09:28:20.697212 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 09:28:20.697293 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 09:28:20.697348 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 09:28:20.697399 0 11 4 | B1->B0 | 2c2c 2525 | 1 0 | (1 1) (0 0)
1925 09:28:20.697458 0 11 8 | B1->B0 | 4040 3636 | 1 1 | (0 0) (0 0)
1926 09:28:20.697547 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 09:28:20.697608 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 09:28:20.697661 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 09:28:20.697713 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 09:28:20.697765 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 09:28:20.697817 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 09:28:20.697869 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1933 09:28:20.697920 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1934 09:28:20.697972 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 09:28:20.698023 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 09:28:20.698075 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 09:28:20.698127 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 09:28:20.698223 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 09:28:20.698276 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 09:28:20.698327 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 09:28:20.698379 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 09:28:20.698430 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 09:28:20.698481 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 09:28:20.698535 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 09:28:20.698638 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 09:28:20.698695 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 09:28:20.698748 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 09:28:20.698800 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 09:28:20.698869 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1950 09:28:20.698923 Total UI for P1: 0, mck2ui 16
1951 09:28:20.698976 best dqsien dly found for B1: ( 0, 14, 6)
1952 09:28:20.699029 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1953 09:28:20.699093 Total UI for P1: 0, mck2ui 16
1954 09:28:20.699148 best dqsien dly found for B0: ( 0, 14, 8)
1955 09:28:20.699201 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1956 09:28:20.699253 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1957 09:28:20.699304
1958 09:28:20.699372 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1959 09:28:20.699425 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1960 09:28:20.699476 [Gating] SW calibration Done
1961 09:28:20.699527 ==
1962 09:28:20.699593 Dram Type= 6, Freq= 0, CH_1, rank 1
1963 09:28:20.699647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1964 09:28:20.699699 ==
1965 09:28:20.699751 RX Vref Scan: 0
1966 09:28:20.699802
1967 09:28:20.699853 RX Vref 0 -> 0, step: 1
1968 09:28:20.699905
1969 09:28:20.699967 RX Delay -130 -> 252, step: 16
1970 09:28:20.700021 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1971 09:28:20.700073 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1972 09:28:20.700124 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1973 09:28:20.700176 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1974 09:28:20.700231 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1975 09:28:20.700293 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1976 09:28:20.700345 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1977 09:28:20.700395 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1978 09:28:20.700447 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1979 09:28:20.700499 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1980 09:28:20.700550 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1981 09:28:20.700600 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1982 09:28:20.700657 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1983 09:28:20.700717 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1984 09:28:20.700768 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1985 09:28:20.837072 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1986 09:28:20.837199 ==
1987 09:28:20.837280 Dram Type= 6, Freq= 0, CH_1, rank 1
1988 09:28:20.837371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1989 09:28:20.837458 ==
1990 09:28:20.837551 DQS Delay:
1991 09:28:20.837634 DQS0 = 0, DQS1 = 0
1992 09:28:20.837717 DQM Delay:
1993 09:28:20.838020 DQM0 = 87, DQM1 = 78
1994 09:28:20.838118 DQ Delay:
1995 09:28:20.838235 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1996 09:28:20.838308 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1997 09:28:20.838364 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1998 09:28:20.838418 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1999 09:28:20.838471
2000 09:28:20.838541
2001 09:28:20.838595 ==
2002 09:28:20.838648 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 09:28:20.838701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 09:28:20.838763 ==
2005 09:28:20.838820
2006 09:28:20.838871
2007 09:28:20.838923 TX Vref Scan disable
2008 09:28:20.838975 == TX Byte 0 ==
2009 09:28:20.839043 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2010 09:28:20.839097 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2011 09:28:20.839149 == TX Byte 1 ==
2012 09:28:20.839200 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2013 09:28:20.839261 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2014 09:28:20.839318 ==
2015 09:28:20.839370 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 09:28:20.839421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 09:28:20.839473 ==
2018 09:28:20.839551 TX Vref=22, minBit 9, minWin=26, winSum=439
2019 09:28:20.839634 TX Vref=24, minBit 1, minWin=27, winSum=447
2020 09:28:20.839716 TX Vref=26, minBit 1, minWin=27, winSum=448
2021 09:28:20.839793 TX Vref=28, minBit 8, minWin=27, winSum=448
2022 09:28:20.839847 TX Vref=30, minBit 1, minWin=27, winSum=449
2023 09:28:20.839900 TX Vref=32, minBit 0, minWin=28, winSum=449
2024 09:28:20.839951 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 32
2025 09:28:20.840013
2026 09:28:20.840068 Final TX Range 1 Vref 32
2027 09:28:20.840120
2028 09:28:20.840171 ==
2029 09:28:20.840223 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 09:28:20.840303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 09:28:20.840385 ==
2032 09:28:20.840465
2033 09:28:20.840553
2034 09:28:20.840635 TX Vref Scan disable
2035 09:28:20.840715 == TX Byte 0 ==
2036 09:28:20.840805 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2037 09:28:20.840887 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2038 09:28:20.840968 == TX Byte 1 ==
2039 09:28:20.841057 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2040 09:28:20.841139 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2041 09:28:20.841219
2042 09:28:20.841307 [DATLAT]
2043 09:28:20.841388 Freq=800, CH1 RK1
2044 09:28:20.841468
2045 09:28:20.841556 DATLAT Default: 0xa
2046 09:28:20.841637 0, 0xFFFF, sum = 0
2047 09:28:20.841720 1, 0xFFFF, sum = 0
2048 09:28:20.841810 2, 0xFFFF, sum = 0
2049 09:28:20.841893 3, 0xFFFF, sum = 0
2050 09:28:20.841975 4, 0xFFFF, sum = 0
2051 09:28:20.842067 5, 0xFFFF, sum = 0
2052 09:28:20.842149 6, 0xFFFF, sum = 0
2053 09:28:20.842243 7, 0xFFFF, sum = 0
2054 09:28:20.842306 8, 0xFFFF, sum = 0
2055 09:28:20.842359 9, 0x0, sum = 1
2056 09:28:20.842412 10, 0x0, sum = 2
2057 09:28:20.842465 11, 0x0, sum = 3
2058 09:28:20.842560 12, 0x0, sum = 4
2059 09:28:20.842618 best_step = 10
2060 09:28:20.842670
2061 09:28:20.842722 ==
2062 09:28:20.842791 Dram Type= 6, Freq= 0, CH_1, rank 1
2063 09:28:20.842844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2064 09:28:20.842897 ==
2065 09:28:20.842949 RX Vref Scan: 0
2066 09:28:20.843014
2067 09:28:20.843069 RX Vref 0 -> 0, step: 1
2068 09:28:20.843121
2069 09:28:20.843173 RX Delay -95 -> 252, step: 8
2070 09:28:20.843225 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2071 09:28:20.843291 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2072 09:28:20.843343 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2073 09:28:20.843396 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2074 09:28:20.843448 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2075 09:28:20.843514 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2076 09:28:20.843568 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2077 09:28:20.843620 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2078 09:28:20.843673 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2079 09:28:20.843726 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2080 09:28:20.843790 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2081 09:28:20.843843 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2082 09:28:20.843895 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2083 09:28:20.843947 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2084 09:28:20.844013 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2085 09:28:20.844066 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2086 09:28:20.844118 ==
2087 09:28:20.844170 Dram Type= 6, Freq= 0, CH_1, rank 1
2088 09:28:20.844222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2089 09:28:20.844288 ==
2090 09:28:20.844340 DQS Delay:
2091 09:28:20.844391 DQS0 = 0, DQS1 = 0
2092 09:28:20.844442 DQM Delay:
2093 09:28:20.844510 DQM0 = 87, DQM1 = 78
2094 09:28:20.844592 DQ Delay:
2095 09:28:20.844673 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2096 09:28:20.844762 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2097 09:28:20.844845 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
2098 09:28:20.844926 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2099 09:28:20.845014
2100 09:28:20.845095
2101 09:28:20.845178 [DQSOSCAuto] RK1, (LSB)MR18= 0x1910, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2102 09:28:20.845269 CH1 RK1: MR19=606, MR18=1910
2103 09:28:20.845352 CH1_RK1: MR19=0x606, MR18=0x1910, DQSOSC=403, MR23=63, INC=90, DEC=60
2104 09:28:20.845434 [RxdqsGatingPostProcess] freq 800
2105 09:28:20.845524 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2106 09:28:20.845607 Pre-setting of DQS Precalculation
2107 09:28:20.845688 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2108 09:28:20.845780 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2109 09:28:20.845864 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2110 09:28:20.845944
2111 09:28:20.846032
2112 09:28:20.846114 [Calibration Summary] 1600 Mbps
2113 09:28:20.846245 CH 0, Rank 0
2114 09:28:20.846304 SW Impedance : PASS
2115 09:28:20.846357 DUTY Scan : NO K
2116 09:28:20.846410 ZQ Calibration : PASS
2117 09:28:20.846461 Jitter Meter : NO K
2118 09:28:20.846514 CBT Training : PASS
2119 09:28:20.846566 Write leveling : PASS
2120 09:28:20.846618 RX DQS gating : PASS
2121 09:28:20.846670 RX DQ/DQS(RDDQC) : PASS
2122 09:28:20.846722 TX DQ/DQS : PASS
2123 09:28:20.846775 RX DATLAT : PASS
2124 09:28:20.846826 RX DQ/DQS(Engine): PASS
2125 09:28:20.846877 TX OE : NO K
2126 09:28:20.846929 All Pass.
2127 09:28:20.846981
2128 09:28:20.847033 CH 0, Rank 1
2129 09:28:20.847085 SW Impedance : PASS
2130 09:28:20.847136 DUTY Scan : NO K
2131 09:28:20.847187 ZQ Calibration : PASS
2132 09:28:20.847238 Jitter Meter : NO K
2133 09:28:20.847290 CBT Training : PASS
2134 09:28:20.847340 Write leveling : PASS
2135 09:28:20.847391 RX DQS gating : PASS
2136 09:28:20.847442 RX DQ/DQS(RDDQC) : PASS
2137 09:28:20.847494 TX DQ/DQS : PASS
2138 09:28:20.847546 RX DATLAT : PASS
2139 09:28:20.847789 RX DQ/DQS(Engine): PASS
2140 09:28:20.847847 TX OE : NO K
2141 09:28:20.847916 All Pass.
2142 09:28:20.848007
2143 09:28:20.848102 CH 1, Rank 0
2144 09:28:20.848154 SW Impedance : PASS
2145 09:28:20.848205 DUTY Scan : NO K
2146 09:28:20.848256 ZQ Calibration : PASS
2147 09:28:20.848307 Jitter Meter : NO K
2148 09:28:20.848359 CBT Training : PASS
2149 09:28:20.848410 Write leveling : PASS
2150 09:28:20.848461 RX DQS gating : PASS
2151 09:28:20.848513 RX DQ/DQS(RDDQC) : PASS
2152 09:28:20.848564 TX DQ/DQS : PASS
2153 09:28:20.848616 RX DATLAT : PASS
2154 09:28:20.848667 RX DQ/DQS(Engine): PASS
2155 09:28:20.848718 TX OE : NO K
2156 09:28:20.848770 All Pass.
2157 09:28:20.848822
2158 09:28:20.848873 CH 1, Rank 1
2159 09:28:20.848925 SW Impedance : PASS
2160 09:28:20.848977 DUTY Scan : NO K
2161 09:28:20.849029 ZQ Calibration : PASS
2162 09:28:20.849080 Jitter Meter : NO K
2163 09:28:20.849131 CBT Training : PASS
2164 09:28:20.849183 Write leveling : PASS
2165 09:28:20.849233 RX DQS gating : PASS
2166 09:28:20.849284 RX DQ/DQS(RDDQC) : PASS
2167 09:28:20.849335 TX DQ/DQS : PASS
2168 09:28:20.849387 RX DATLAT : PASS
2169 09:28:20.849438 RX DQ/DQS(Engine): PASS
2170 09:28:20.849489 TX OE : NO K
2171 09:28:20.849541 All Pass.
2172 09:28:20.849593
2173 09:28:20.849644 DramC Write-DBI off
2174 09:28:20.849694 PER_BANK_REFRESH: Hybrid Mode
2175 09:28:20.849746 TX_TRACKING: ON
2176 09:28:20.849797 [GetDramInforAfterCalByMRR] Vendor 6.
2177 09:28:20.849849 [GetDramInforAfterCalByMRR] Revision 606.
2178 09:28:20.849901 [GetDramInforAfterCalByMRR] Revision 2 0.
2179 09:28:20.849952 MR0 0x3b3b
2180 09:28:20.850004 MR8 0x5151
2181 09:28:20.850055 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 09:28:20.850107
2183 09:28:20.850157 MR0 0x3b3b
2184 09:28:20.850249 MR8 0x5151
2185 09:28:20.850301 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2186 09:28:20.850353
2187 09:28:20.850404 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2188 09:28:20.850476 [FAST_K] Save calibration result to emmc
2189 09:28:20.850536 [FAST_K] Save calibration result to emmc
2190 09:28:20.850588 dram_init: config_dvfs: 1
2191 09:28:20.850640 dramc_set_vcore_voltage set vcore to 662500
2192 09:28:20.850692 Read voltage for 1200, 2
2193 09:28:20.850744 Vio18 = 0
2194 09:28:20.850795 Vcore = 662500
2195 09:28:20.850846 Vdram = 0
2196 09:28:20.850897 Vddq = 0
2197 09:28:20.850948 Vmddr = 0
2198 09:28:20.850999 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2199 09:28:20.851051 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2200 09:28:20.851102 MEM_TYPE=3, freq_sel=15
2201 09:28:20.851202 sv_algorithm_assistance_LP4_1600
2202 09:28:20.851268 ============ PULL DRAM RESETB DOWN ============
2203 09:28:20.851320 ========== PULL DRAM RESETB DOWN end =========
2204 09:28:20.851388 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2205 09:28:20.851455 ===================================
2206 09:28:20.851525 LPDDR4 DRAM CONFIGURATION
2207 09:28:20.851577 ===================================
2208 09:28:20.851629 EX_ROW_EN[0] = 0x0
2209 09:28:20.851681 EX_ROW_EN[1] = 0x0
2210 09:28:20.851732 LP4Y_EN = 0x0
2211 09:28:20.851784 WORK_FSP = 0x0
2212 09:28:20.851835 WL = 0x4
2213 09:28:20.851887 RL = 0x4
2214 09:28:20.851939 BL = 0x2
2215 09:28:20.851990 RPST = 0x0
2216 09:28:20.852042 RD_PRE = 0x0
2217 09:28:20.852093 WR_PRE = 0x1
2218 09:28:20.852144 WR_PST = 0x0
2219 09:28:20.852196 DBI_WR = 0x0
2220 09:28:20.852246 DBI_RD = 0x0
2221 09:28:20.852297 OTF = 0x1
2222 09:28:20.852349 ===================================
2223 09:28:20.852401 ===================================
2224 09:28:20.852453 ANA top config
2225 09:28:20.852504 ===================================
2226 09:28:20.852556 DLL_ASYNC_EN = 0
2227 09:28:20.852607 ALL_SLAVE_EN = 0
2228 09:28:20.852658 NEW_RANK_MODE = 1
2229 09:28:20.852711 DLL_IDLE_MODE = 1
2230 09:28:20.852762 LP45_APHY_COMB_EN = 1
2231 09:28:20.852813 TX_ODT_DIS = 1
2232 09:28:20.852895 NEW_8X_MODE = 1
2233 09:28:20.852947 ===================================
2234 09:28:20.852999 ===================================
2235 09:28:20.853050 data_rate = 2400
2236 09:28:20.853101 CKR = 1
2237 09:28:20.853153 DQ_P2S_RATIO = 8
2238 09:28:20.853204 ===================================
2239 09:28:20.853256 CA_P2S_RATIO = 8
2240 09:28:20.853308 DQ_CA_OPEN = 0
2241 09:28:20.853359 DQ_SEMI_OPEN = 0
2242 09:28:20.853411 CA_SEMI_OPEN = 0
2243 09:28:20.853462 CA_FULL_RATE = 0
2244 09:28:20.853514 DQ_CKDIV4_EN = 0
2245 09:28:20.853565 CA_CKDIV4_EN = 0
2246 09:28:20.853616 CA_PREDIV_EN = 0
2247 09:28:20.853667 PH8_DLY = 17
2248 09:28:20.853750 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2249 09:28:20.853801 DQ_AAMCK_DIV = 4
2250 09:28:20.853853 CA_AAMCK_DIV = 4
2251 09:28:20.853904 CA_ADMCK_DIV = 4
2252 09:28:20.853955 DQ_TRACK_CA_EN = 0
2253 09:28:20.854007 CA_PICK = 1200
2254 09:28:20.854058 CA_MCKIO = 1200
2255 09:28:20.854127 MCKIO_SEMI = 0
2256 09:28:20.854201 PLL_FREQ = 2366
2257 09:28:20.854260 DQ_UI_PI_RATIO = 32
2258 09:28:20.854334 CA_UI_PI_RATIO = 0
2259 09:28:20.854388 ===================================
2260 09:28:20.854440 ===================================
2261 09:28:20.854492 memory_type:LPDDR4
2262 09:28:20.854544 GP_NUM : 10
2263 09:28:20.854595 SRAM_EN : 1
2264 09:28:20.854647 MD32_EN : 0
2265 09:28:20.854699 ===================================
2266 09:28:20.854751 [ANA_INIT] >>>>>>>>>>>>>>
2267 09:28:20.854818 <<<<<< [CONFIGURE PHASE]: ANA_TX
2268 09:28:20.854885 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2269 09:28:20.854937 ===================================
2270 09:28:20.855010 data_rate = 2400,PCW = 0X5b00
2271 09:28:20.855065 ===================================
2272 09:28:20.855118 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2273 09:28:20.855170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2274 09:28:20.855223 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2275 09:28:20.855275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2276 09:28:20.855327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2277 09:28:20.855379 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2278 09:28:20.855431 [ANA_INIT] flow start
2279 09:28:20.855484 [ANA_INIT] PLL >>>>>>>>
2280 09:28:20.855726 [ANA_INIT] PLL <<<<<<<<
2281 09:28:20.855784 [ANA_INIT] MIDPI >>>>>>>>
2282 09:28:20.855852 [ANA_INIT] MIDPI <<<<<<<<
2283 09:28:20.855919 [ANA_INIT] DLL >>>>>>>>
2284 09:28:20.855970 [ANA_INIT] DLL <<<<<<<<
2285 09:28:20.856021 [ANA_INIT] flow end
2286 09:28:20.856073 ============ LP4 DIFF to SE enter ============
2287 09:28:20.856125 ============ LP4 DIFF to SE exit ============
2288 09:28:20.856177 [ANA_INIT] <<<<<<<<<<<<<
2289 09:28:20.856229 [Flow] Enable top DCM control >>>>>
2290 09:28:20.856281 [Flow] Enable top DCM control <<<<<
2291 09:28:20.856332 Enable DLL master slave shuffle
2292 09:28:20.856385 ==============================================================
2293 09:28:20.856437 Gating Mode config
2294 09:28:20.856489 ==============================================================
2295 09:28:20.856541 Config description:
2296 09:28:20.856592 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2297 09:28:20.856645 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2298 09:28:20.856697 SELPH_MODE 0: By rank 1: By Phase
2299 09:28:20.856750 ==============================================================
2300 09:28:20.856803 GAT_TRACK_EN = 1
2301 09:28:20.856854 RX_GATING_MODE = 2
2302 09:28:20.856906 RX_GATING_TRACK_MODE = 2
2303 09:28:20.856958 SELPH_MODE = 1
2304 09:28:20.857010 PICG_EARLY_EN = 1
2305 09:28:20.857062 VALID_LAT_VALUE = 1
2306 09:28:20.857113 ==============================================================
2307 09:28:20.857165 Enter into Gating configuration >>>>
2308 09:28:20.857217 Exit from Gating configuration <<<<
2309 09:28:20.857269 Enter into DVFS_PRE_config >>>>>
2310 09:28:20.857320 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2311 09:28:20.857374 Exit from DVFS_PRE_config <<<<<
2312 09:28:20.857426 Enter into PICG configuration >>>>
2313 09:28:20.857477 Exit from PICG configuration <<<<
2314 09:28:20.857531 [RX_INPUT] configuration >>>>>
2315 09:28:20.857584 [RX_INPUT] configuration <<<<<
2316 09:28:20.857635 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2317 09:28:20.857687 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2318 09:28:20.857740 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2319 09:28:20.857792 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2320 09:28:20.857844 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 09:28:20.857896 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 09:28:20.857947 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2323 09:28:20.858026 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2324 09:28:20.858111 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2325 09:28:20.858226 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2326 09:28:20.858281 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2327 09:28:20.858333 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2328 09:28:20.858386 ===================================
2329 09:28:20.858438 LPDDR4 DRAM CONFIGURATION
2330 09:28:20.858489 ===================================
2331 09:28:20.858541 EX_ROW_EN[0] = 0x0
2332 09:28:20.858593 EX_ROW_EN[1] = 0x0
2333 09:28:20.858644 LP4Y_EN = 0x0
2334 09:28:20.858696 WORK_FSP = 0x0
2335 09:28:20.858747 WL = 0x4
2336 09:28:20.858799 RL = 0x4
2337 09:28:20.858850 BL = 0x2
2338 09:28:20.858901 RPST = 0x0
2339 09:28:20.858952 RD_PRE = 0x0
2340 09:28:20.859003 WR_PRE = 0x1
2341 09:28:20.859054 WR_PST = 0x0
2342 09:28:20.859105 DBI_WR = 0x0
2343 09:28:20.859156 DBI_RD = 0x0
2344 09:28:20.859207 OTF = 0x1
2345 09:28:20.859258 ===================================
2346 09:28:20.859310 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2347 09:28:20.859361 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2348 09:28:20.859413 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2349 09:28:20.859465 ===================================
2350 09:28:20.859517 LPDDR4 DRAM CONFIGURATION
2351 09:28:20.859568 ===================================
2352 09:28:20.859619 EX_ROW_EN[0] = 0x10
2353 09:28:20.859671 EX_ROW_EN[1] = 0x0
2354 09:28:20.859722 LP4Y_EN = 0x0
2355 09:28:20.859773 WORK_FSP = 0x0
2356 09:28:20.859824 WL = 0x4
2357 09:28:20.859876 RL = 0x4
2358 09:28:20.859927 BL = 0x2
2359 09:28:20.859979 RPST = 0x0
2360 09:28:20.860030 RD_PRE = 0x0
2361 09:28:20.860081 WR_PRE = 0x1
2362 09:28:20.860132 WR_PST = 0x0
2363 09:28:20.860186 DBI_WR = 0x0
2364 09:28:20.860251 DBI_RD = 0x0
2365 09:28:20.860303 OTF = 0x1
2366 09:28:20.860355 ===================================
2367 09:28:20.860407 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2368 09:28:20.860476 ==
2369 09:28:20.860529 Dram Type= 6, Freq= 0, CH_0, rank 0
2370 09:28:20.860581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2371 09:28:20.860633 ==
2372 09:28:20.860688 [Duty_Offset_Calibration]
2373 09:28:20.860750 B0:1 B1:-1 CA:0
2374 09:28:20.860802
2375 09:28:20.860853 [DutyScan_Calibration_Flow] k_type=0
2376 09:28:20.860905
2377 09:28:20.860972 ==CLK 0==
2378 09:28:20.861026 Final CLK duty delay cell = 0
2379 09:28:20.861078 [0] MAX Duty = 5094%(X100), DQS PI = 16
2380 09:28:20.861130 [0] MIN Duty = 4875%(X100), DQS PI = 10
2381 09:28:20.861186 [0] AVG Duty = 4984%(X100)
2382 09:28:20.861246
2383 09:28:20.861297 CH0 CLK Duty spec in!! Max-Min= 219%
2384 09:28:20.861349 [DutyScan_Calibration_Flow] ====Done====
2385 09:28:20.861400
2386 09:28:20.861464 [DutyScan_Calibration_Flow] k_type=1
2387 09:28:20.861518
2388 09:28:20.861569 ==DQS 0 ==
2389 09:28:20.861621 Final DQS duty delay cell = -4
2390 09:28:20.861672 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2391 09:28:20.861761 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2392 09:28:20.861843 [-4] AVG Duty = 4953%(X100)
2393 09:28:20.861922
2394 09:28:20.862012 ==DQS 1 ==
2395 09:28:20.862093 Final DQS duty delay cell = -4
2396 09:28:20.862219 [-4] MAX Duty = 5000%(X100), DQS PI = 8
2397 09:28:20.862277 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2398 09:28:20.862521 [-4] AVG Duty = 4938%(X100)
2399 09:28:20.862581
2400 09:28:20.862634 CH0 DQS 0 Duty spec in!! Max-Min= 156%
2401 09:28:20.862687
2402 09:28:20.862753 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2403 09:28:20.862807 [DutyScan_Calibration_Flow] ====Done====
2404 09:28:20.862858
2405 09:28:20.862909 [DutyScan_Calibration_Flow] k_type=3
2406 09:28:20.862975
2407 09:28:20.863029 ==DQM 0 ==
2408 09:28:20.863081 Final DQM duty delay cell = 0
2409 09:28:20.863133 [0] MAX Duty = 5062%(X100), DQS PI = 24
2410 09:28:20.863185 [0] MIN Duty = 4875%(X100), DQS PI = 8
2411 09:28:20.863251 [0] AVG Duty = 4968%(X100)
2412 09:28:20.863304
2413 09:28:20.863355 ==DQM 1 ==
2414 09:28:20.863406 Final DQM duty delay cell = 4
2415 09:28:20.863474 [4] MAX Duty = 5187%(X100), DQS PI = 14
2416 09:28:20.863528 [4] MIN Duty = 4969%(X100), DQS PI = 26
2417 09:28:20.863579 [4] AVG Duty = 5078%(X100)
2418 09:28:20.863631
2419 09:28:20.863691 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2420 09:28:20.863748
2421 09:28:20.863799 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2422 09:28:20.863850 [DutyScan_Calibration_Flow] ====Done====
2423 09:28:20.863901
2424 09:28:20.863968 [DutyScan_Calibration_Flow] k_type=2
2425 09:28:20.864022
2426 09:28:20.864073 ==DQ 0 ==
2427 09:28:20.864124 Final DQ duty delay cell = -4
2428 09:28:20.864181 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2429 09:28:20.864269 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2430 09:28:20.864350 [-4] AVG Duty = 4953%(X100)
2431 09:28:20.864437
2432 09:28:20.864519 ==DQ 1 ==
2433 09:28:20.864600 Final DQ duty delay cell = -4
2434 09:28:20.864688 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2435 09:28:20.864771 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2436 09:28:20.864851 [-4] AVG Duty = 4922%(X100)
2437 09:28:20.864938
2438 09:28:20.865021 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2439 09:28:20.865101
2440 09:28:20.865189 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2441 09:28:20.865272 [DutyScan_Calibration_Flow] ====Done====
2442 09:28:20.865352 ==
2443 09:28:20.865441 Dram Type= 6, Freq= 0, CH_1, rank 0
2444 09:28:20.865524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2445 09:28:20.865605 ==
2446 09:28:20.865693 [Duty_Offset_Calibration]
2447 09:28:20.865775 B0:-1 B1:1 CA:1
2448 09:28:20.865855
2449 09:28:20.865943 [DutyScan_Calibration_Flow] k_type=0
2450 09:28:20.866025
2451 09:28:20.866104 ==CLK 0==
2452 09:28:20.866222 Final CLK duty delay cell = 0
2453 09:28:20.866319 [0] MAX Duty = 5156%(X100), DQS PI = 6
2454 09:28:20.866401 [0] MIN Duty = 5000%(X100), DQS PI = 28
2455 09:28:20.866489 [0] AVG Duty = 5078%(X100)
2456 09:28:20.866569
2457 09:28:20.866650 CH1 CLK Duty spec in!! Max-Min= 156%
2458 09:28:20.866739 [DutyScan_Calibration_Flow] ====Done====
2459 09:28:20.866820
2460 09:28:20.866900 [DutyScan_Calibration_Flow] k_type=1
2461 09:28:20.866988
2462 09:28:20.867068 ==DQS 0 ==
2463 09:28:20.867149 Final DQS duty delay cell = 0
2464 09:28:20.867238 [0] MAX Duty = 5125%(X100), DQS PI = 16
2465 09:28:20.867320 [0] MIN Duty = 4907%(X100), DQS PI = 38
2466 09:28:20.867400 [0] AVG Duty = 5016%(X100)
2467 09:28:20.867489
2468 09:28:20.867569 ==DQS 1 ==
2469 09:28:20.867650 Final DQS duty delay cell = 0
2470 09:28:20.867740 [0] MAX Duty = 5094%(X100), DQS PI = 44
2471 09:28:20.867821 [0] MIN Duty = 4969%(X100), DQS PI = 26
2472 09:28:20.867902 [0] AVG Duty = 5031%(X100)
2473 09:28:20.867991
2474 09:28:20.868072 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2475 09:28:20.868151
2476 09:28:20.868240 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2477 09:28:20.868321 [DutyScan_Calibration_Flow] ====Done====
2478 09:28:20.868401
2479 09:28:20.868490 [DutyScan_Calibration_Flow] k_type=3
2480 09:28:20.868570
2481 09:28:20.868650 ==DQM 0 ==
2482 09:28:20.868739 Final DQM duty delay cell = -4
2483 09:28:20.868821 [-4] MAX Duty = 5031%(X100), DQS PI = 2
2484 09:28:20.868902 [-4] MIN Duty = 4844%(X100), DQS PI = 38
2485 09:28:20.868991 [-4] AVG Duty = 4937%(X100)
2486 09:28:20.869072
2487 09:28:20.869151 ==DQM 1 ==
2488 09:28:20.869258 Final DQM duty delay cell = 0
2489 09:28:20.869415 [0] MAX Duty = 5187%(X100), DQS PI = 36
2490 09:28:20.869503 [0] MIN Duty = 4969%(X100), DQS PI = 0
2491 09:28:20.869584 [0] AVG Duty = 5078%(X100)
2492 09:28:20.869667
2493 09:28:20.869753 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2494 09:28:20.869833
2495 09:28:20.869917 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2496 09:28:20.870003 [DutyScan_Calibration_Flow] ====Done====
2497 09:28:20.870083
2498 09:28:20.870186 [DutyScan_Calibration_Flow] k_type=2
2499 09:28:20.870286
2500 09:28:20.870366 ==DQ 0 ==
2501 09:28:20.870446 Final DQ duty delay cell = 0
2502 09:28:20.870537 [0] MAX Duty = 5156%(X100), DQS PI = 60
2503 09:28:20.870618 [0] MIN Duty = 4875%(X100), DQS PI = 38
2504 09:28:20.870700 [0] AVG Duty = 5015%(X100)
2505 09:28:20.870787
2506 09:28:20.870867 ==DQ 1 ==
2507 09:28:20.870948 Final DQ duty delay cell = 0
2508 09:28:20.871037 [0] MAX Duty = 5124%(X100), DQS PI = 42
2509 09:28:20.871118 [0] MIN Duty = 4969%(X100), DQS PI = 0
2510 09:28:20.871201 [0] AVG Duty = 5046%(X100)
2511 09:28:20.871287
2512 09:28:20.871367 CH1 DQ 0 Duty spec in!! Max-Min= 281%
2513 09:28:20.871451
2514 09:28:20.871537 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2515 09:28:20.871618 [DutyScan_Calibration_Flow] ====Done====
2516 09:28:20.871701 nWR fixed to 30
2517 09:28:20.871788 [ModeRegInit_LP4] CH0 RK0
2518 09:28:20.871869 [ModeRegInit_LP4] CH0 RK1
2519 09:28:20.871949 [ModeRegInit_LP4] CH1 RK0
2520 09:28:20.872038 [ModeRegInit_LP4] CH1 RK1
2521 09:28:20.872118 match AC timing 7
2522 09:28:20.872199 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2523 09:28:20.872280 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2524 09:28:20.872361 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2525 09:28:20.872458 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2526 09:28:20.872598 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2527 09:28:20.872692 ==
2528 09:28:20.872812 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 09:28:20.872895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 09:28:20.872976 ==
2531 09:28:20.873057 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2532 09:28:20.873139 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2533 09:28:20.873224 [CA 0] Center 39 (9~70) winsize 62
2534 09:28:20.873309 [CA 1] Center 39 (9~70) winsize 62
2535 09:28:20.873390 [CA 2] Center 35 (5~66) winsize 62
2536 09:28:20.873471 [CA 3] Center 35 (5~65) winsize 61
2537 09:28:20.873551 [CA 4] Center 33 (3~64) winsize 62
2538 09:28:20.873633 [CA 5] Center 33 (4~63) winsize 60
2539 09:28:20.873696
2540 09:28:20.873748 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2541 09:28:20.873799
2542 09:28:20.873850 [CATrainingPosCal] consider 1 rank data
2543 09:28:20.873915 u2DelayCellTimex100 = 270/100 ps
2544 09:28:20.873969 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2545 09:28:20.874021 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2546 09:28:20.874072 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2547 09:28:20.874122 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2548 09:28:20.874431 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2549 09:28:20.874520 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2550 09:28:20.874573
2551 09:28:20.874625 CA PerBit enable=1, Macro0, CA PI delay=33
2552 09:28:20.874691
2553 09:28:20.874743 [CBTSetCACLKResult] CA Dly = 33
2554 09:28:20.874794 CS Dly: 8 (0~39)
2555 09:28:20.874845 ==
2556 09:28:20.874941 Dram Type= 6, Freq= 0, CH_0, rank 1
2557 09:28:20.874995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 09:28:20.875047 ==
2559 09:28:20.875098 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2560 09:28:20.875165 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2561 09:28:20.875248 [CA 0] Center 39 (8~70) winsize 63
2562 09:28:20.875329 [CA 1] Center 39 (9~70) winsize 62
2563 09:28:20.875418 [CA 2] Center 35 (5~66) winsize 62
2564 09:28:20.875500 [CA 3] Center 34 (4~65) winsize 62
2565 09:28:20.875580 [CA 4] Center 33 (3~64) winsize 62
2566 09:28:20.875669 [CA 5] Center 33 (3~63) winsize 61
2567 09:28:20.875750
2568 09:28:20.875832 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2569 09:28:20.875920
2570 09:28:20.876001 [CATrainingPosCal] consider 2 rank data
2571 09:28:20.876082 u2DelayCellTimex100 = 270/100 ps
2572 09:28:20.876171 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2573 09:28:20.876253 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2574 09:28:20.876334 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2575 09:28:20.876423 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2576 09:28:20.876504 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2577 09:28:20.876585 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2578 09:28:20.876674
2579 09:28:20.876755 CA PerBit enable=1, Macro0, CA PI delay=33
2580 09:28:20.876836
2581 09:28:20.876924 [CBTSetCACLKResult] CA Dly = 33
2582 09:28:20.877005 CS Dly: 9 (0~41)
2583 09:28:20.877085
2584 09:28:20.877174 ----->DramcWriteLeveling(PI) begin...
2585 09:28:20.877256 ==
2586 09:28:20.877337 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 09:28:20.877427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 09:28:20.877508 ==
2589 09:28:20.877589 Write leveling (Byte 0): 33 => 33
2590 09:28:20.877678 Write leveling (Byte 1): 29 => 29
2591 09:28:20.877759 DramcWriteLeveling(PI) end<-----
2592 09:28:20.877839
2593 09:28:20.877927 ==
2594 09:28:20.878008 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 09:28:20.878089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 09:28:20.878221 ==
2597 09:28:20.878276 [Gating] SW mode calibration
2598 09:28:20.878329 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2599 09:28:20.878398 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2600 09:28:20.878481 0 15 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2601 09:28:20.878562 0 15 4 | B1->B0 | 2929 3434 | 1 1 | (0 0) (1 1)
2602 09:28:20.878651 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 09:28:20.878734 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 09:28:20.878815 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 09:28:20.878897 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 09:28:20.878952 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2607 09:28:20.879005 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
2608 09:28:20.879057 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2609 09:28:20.879109 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2610 09:28:20.879161 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 09:28:20.879212 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 09:28:20.879263 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 09:28:20.879314 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 09:28:20.879365 1 0 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2615 09:28:20.879416 1 0 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
2616 09:28:20.879467 1 1 0 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
2617 09:28:20.879518 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2618 09:28:20.879569 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 09:28:20.879620 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 09:28:20.879671 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 09:28:20.879722 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 09:28:20.879773 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 09:28:20.879824 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2624 09:28:20.879875 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2625 09:28:20.879926 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 09:28:20.879977 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 09:28:20.880028 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 09:28:20.880080 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 09:28:20.880131 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 09:28:20.880182 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 09:28:20.880234 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 09:28:20.880285 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 09:28:20.880336 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 09:28:20.880387 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 09:28:20.880437 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 09:28:20.880488 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 09:28:20.880539 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 09:28:20.880590 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 09:28:20.880641 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2640 09:28:20.880693 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2641 09:28:20.880745 Total UI for P1: 0, mck2ui 16
2642 09:28:20.880796 best dqsien dly found for B0: ( 1, 3, 28)
2643 09:28:20.880847 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2644 09:28:20.880899 Total UI for P1: 0, mck2ui 16
2645 09:28:20.880950 best dqsien dly found for B1: ( 1, 4, 0)
2646 09:28:20.881001 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2647 09:28:20.881052 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2648 09:28:20.881104
2649 09:28:20.881154 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2650 09:28:20.881205 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2651 09:28:20.881255 [Gating] SW calibration Done
2652 09:28:20.881306 ==
2653 09:28:20.881550 Dram Type= 6, Freq= 0, CH_0, rank 0
2654 09:28:20.881647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2655 09:28:20.881700 ==
2656 09:28:20.881751 RX Vref Scan: 0
2657 09:28:20.881803
2658 09:28:20.881854 RX Vref 0 -> 0, step: 1
2659 09:28:20.881905
2660 09:28:20.881987 RX Delay -40 -> 252, step: 8
2661 09:28:20.882038 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2662 09:28:20.882090 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2663 09:28:20.882141 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2664 09:28:20.882230 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2665 09:28:20.882282 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2666 09:28:20.882334 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2667 09:28:20.882400 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2668 09:28:20.882466 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2669 09:28:20.882517 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2670 09:28:20.882568 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2671 09:28:20.882620 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2672 09:28:20.882671 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2673 09:28:20.882723 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2674 09:28:20.882774 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2675 09:28:20.882826 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2676 09:28:20.882876 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2677 09:28:20.882927 ==
2678 09:28:20.882980 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 09:28:20.883032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 09:28:20.883082 ==
2681 09:28:20.883133 DQS Delay:
2682 09:28:20.883184 DQS0 = 0, DQS1 = 0
2683 09:28:20.883235 DQM Delay:
2684 09:28:20.883286 DQM0 = 119, DQM1 = 106
2685 09:28:20.883337 DQ Delay:
2686 09:28:20.883389 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2687 09:28:20.883440 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2688 09:28:20.883491 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2689 09:28:20.883542 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2690 09:28:20.883619
2691 09:28:20.883716
2692 09:28:20.883766 ==
2693 09:28:20.883817 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 09:28:20.883868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 09:28:20.883920 ==
2696 09:28:20.883971
2697 09:28:20.884021
2698 09:28:20.884071 TX Vref Scan disable
2699 09:28:20.884122 == TX Byte 0 ==
2700 09:28:20.884173 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2701 09:28:20.884225 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2702 09:28:20.884276 == TX Byte 1 ==
2703 09:28:20.884327 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2704 09:28:20.884378 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2705 09:28:20.884429 ==
2706 09:28:20.884479 Dram Type= 6, Freq= 0, CH_0, rank 0
2707 09:28:20.884530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2708 09:28:20.884582 ==
2709 09:28:20.884633 TX Vref=22, minBit 1, minWin=25, winSum=413
2710 09:28:20.884684 TX Vref=24, minBit 5, minWin=25, winSum=421
2711 09:28:20.884734 TX Vref=26, minBit 13, minWin=25, winSum=425
2712 09:28:20.884786 TX Vref=28, minBit 13, minWin=26, winSum=435
2713 09:28:20.884837 TX Vref=30, minBit 4, minWin=26, winSum=434
2714 09:28:20.884888 TX Vref=32, minBit 4, minWin=26, winSum=433
2715 09:28:20.884939 [TxChooseVref] Worse bit 13, Min win 26, Win sum 435, Final Vref 28
2716 09:28:20.884991
2717 09:28:20.885041 Final TX Range 1 Vref 28
2718 09:28:20.885093
2719 09:28:20.885145 ==
2720 09:28:20.885196 Dram Type= 6, Freq= 0, CH_0, rank 0
2721 09:28:20.885247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2722 09:28:20.885299 ==
2723 09:28:20.885350
2724 09:28:20.885400
2725 09:28:20.885451 TX Vref Scan disable
2726 09:28:20.885502 == TX Byte 0 ==
2727 09:28:20.885570 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2728 09:28:20.885622 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2729 09:28:20.885673 == TX Byte 1 ==
2730 09:28:20.885724 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2731 09:28:20.885775 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2732 09:28:20.885827
2733 09:28:20.885877 [DATLAT]
2734 09:28:20.885928 Freq=1200, CH0 RK0
2735 09:28:20.885979
2736 09:28:20.886030 DATLAT Default: 0xd
2737 09:28:20.886082 0, 0xFFFF, sum = 0
2738 09:28:20.886134 1, 0xFFFF, sum = 0
2739 09:28:20.886228 2, 0xFFFF, sum = 0
2740 09:28:20.886280 3, 0xFFFF, sum = 0
2741 09:28:20.886332 4, 0xFFFF, sum = 0
2742 09:28:20.886384 5, 0xFFFF, sum = 0
2743 09:28:20.886435 6, 0xFFFF, sum = 0
2744 09:28:20.886487 7, 0xFFFF, sum = 0
2745 09:28:20.886538 8, 0xFFFF, sum = 0
2746 09:28:20.886590 9, 0xFFFF, sum = 0
2747 09:28:20.886642 10, 0xFFFF, sum = 0
2748 09:28:20.886694 11, 0xFFFF, sum = 0
2749 09:28:20.886746 12, 0x0, sum = 1
2750 09:28:20.886797 13, 0x0, sum = 2
2751 09:28:20.886849 14, 0x0, sum = 3
2752 09:28:20.886901 15, 0x0, sum = 4
2753 09:28:20.886953 best_step = 13
2754 09:28:20.887003
2755 09:28:20.887054 ==
2756 09:28:20.887105 Dram Type= 6, Freq= 0, CH_0, rank 0
2757 09:28:20.887157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2758 09:28:20.887208 ==
2759 09:28:20.887260 RX Vref Scan: 1
2760 09:28:20.887311
2761 09:28:20.887361 Set Vref Range= 32 -> 127
2762 09:28:20.887412
2763 09:28:20.887463 RX Vref 32 -> 127, step: 1
2764 09:28:20.887515
2765 09:28:20.887566 RX Delay -21 -> 252, step: 4
2766 09:28:20.887617
2767 09:28:20.887667 Set Vref, RX VrefLevel [Byte0]: 32
2768 09:28:20.887718 [Byte1]: 32
2769 09:28:20.887769
2770 09:28:20.887820 Set Vref, RX VrefLevel [Byte0]: 33
2771 09:28:20.887871 [Byte1]: 33
2772 09:28:20.887922
2773 09:28:20.887973 Set Vref, RX VrefLevel [Byte0]: 34
2774 09:28:20.888024 [Byte1]: 34
2775 09:28:20.888075
2776 09:28:20.888125 Set Vref, RX VrefLevel [Byte0]: 35
2777 09:28:20.888176 [Byte1]: 35
2778 09:28:20.888227
2779 09:28:20.888277 Set Vref, RX VrefLevel [Byte0]: 36
2780 09:28:20.888328 [Byte1]: 36
2781 09:28:20.888379
2782 09:28:20.888429 Set Vref, RX VrefLevel [Byte0]: 37
2783 09:28:20.888480 [Byte1]: 37
2784 09:28:20.888531
2785 09:28:20.888581 Set Vref, RX VrefLevel [Byte0]: 38
2786 09:28:20.888632 [Byte1]: 38
2787 09:28:20.888683
2788 09:28:20.888734 Set Vref, RX VrefLevel [Byte0]: 39
2789 09:28:20.888799 [Byte1]: 39
2790 09:28:20.888854
2791 09:28:20.888904 Set Vref, RX VrefLevel [Byte0]: 40
2792 09:28:20.888955 [Byte1]: 40
2793 09:28:20.889007
2794 09:28:20.889057 Set Vref, RX VrefLevel [Byte0]: 41
2795 09:28:20.889108 [Byte1]: 41
2796 09:28:20.889158
2797 09:28:20.889209 Set Vref, RX VrefLevel [Byte0]: 42
2798 09:28:20.889260 [Byte1]: 42
2799 09:28:20.889311
2800 09:28:20.889361 Set Vref, RX VrefLevel [Byte0]: 43
2801 09:28:20.889412 [Byte1]: 43
2802 09:28:20.889463
2803 09:28:20.889558 Set Vref, RX VrefLevel [Byte0]: 44
2804 09:28:20.889624 [Byte1]: 44
2805 09:28:20.889675
2806 09:28:20.889725 Set Vref, RX VrefLevel [Byte0]: 45
2807 09:28:20.889777 [Byte1]: 45
2808 09:28:20.889828
2809 09:28:20.889879 Set Vref, RX VrefLevel [Byte0]: 46
2810 09:28:20.890127 [Byte1]: 46
2811 09:28:20.890227
2812 09:28:20.890281 Set Vref, RX VrefLevel [Byte0]: 47
2813 09:28:20.890333 [Byte1]: 47
2814 09:28:20.890384
2815 09:28:20.890435 Set Vref, RX VrefLevel [Byte0]: 48
2816 09:28:20.890486 [Byte1]: 48
2817 09:28:20.890537
2818 09:28:20.890588 Set Vref, RX VrefLevel [Byte0]: 49
2819 09:28:20.890639 [Byte1]: 49
2820 09:28:20.890690
2821 09:28:20.890741 Set Vref, RX VrefLevel [Byte0]: 50
2822 09:28:20.890792 [Byte1]: 50
2823 09:28:20.890843
2824 09:28:20.890893 Set Vref, RX VrefLevel [Byte0]: 51
2825 09:28:20.890943 [Byte1]: 51
2826 09:28:20.890994
2827 09:28:20.891044 Set Vref, RX VrefLevel [Byte0]: 52
2828 09:28:20.891095 [Byte1]: 52
2829 09:28:20.891146
2830 09:28:20.891197 Set Vref, RX VrefLevel [Byte0]: 53
2831 09:28:20.891247 [Byte1]: 53
2832 09:28:20.891298
2833 09:28:20.891347 Set Vref, RX VrefLevel [Byte0]: 54
2834 09:28:20.891398 [Byte1]: 54
2835 09:28:20.891448
2836 09:28:20.891499 Set Vref, RX VrefLevel [Byte0]: 55
2837 09:28:20.891550 [Byte1]: 55
2838 09:28:20.891601
2839 09:28:20.891660 Set Vref, RX VrefLevel [Byte0]: 56
2840 09:28:20.891729 [Byte1]: 56
2841 09:28:20.891817
2842 09:28:20.891873 Set Vref, RX VrefLevel [Byte0]: 57
2843 09:28:20.891925 [Byte1]: 57
2844 09:28:20.891976
2845 09:28:20.892027 Set Vref, RX VrefLevel [Byte0]: 58
2846 09:28:20.892078 [Byte1]: 58
2847 09:28:20.892129
2848 09:28:20.892180 Set Vref, RX VrefLevel [Byte0]: 59
2849 09:28:20.892231 [Byte1]: 59
2850 09:28:20.892283
2851 09:28:20.892333 Set Vref, RX VrefLevel [Byte0]: 60
2852 09:28:20.892383 [Byte1]: 60
2853 09:28:20.892434
2854 09:28:20.892484 Set Vref, RX VrefLevel [Byte0]: 61
2855 09:28:20.892535 [Byte1]: 61
2856 09:28:20.892586
2857 09:28:20.892637 Set Vref, RX VrefLevel [Byte0]: 62
2858 09:28:20.892688 [Byte1]: 62
2859 09:28:20.892738
2860 09:28:20.892789 Set Vref, RX VrefLevel [Byte0]: 63
2861 09:28:20.892839 [Byte1]: 63
2862 09:28:20.892890
2863 09:28:20.892940 Set Vref, RX VrefLevel [Byte0]: 64
2864 09:28:20.892990 [Byte1]: 64
2865 09:28:20.893040
2866 09:28:20.893091 Set Vref, RX VrefLevel [Byte0]: 65
2867 09:28:20.893141 [Byte1]: 65
2868 09:28:20.893193
2869 09:28:20.893243 Set Vref, RX VrefLevel [Byte0]: 66
2870 09:28:20.893294 [Byte1]: 66
2871 09:28:20.893345
2872 09:28:20.893395 Set Vref, RX VrefLevel [Byte0]: 67
2873 09:28:20.893446 [Byte1]: 67
2874 09:28:20.893497
2875 09:28:20.893547 Set Vref, RX VrefLevel [Byte0]: 68
2876 09:28:20.893597 [Byte1]: 68
2877 09:28:20.893648
2878 09:28:20.893698 Set Vref, RX VrefLevel [Byte0]: 69
2879 09:28:20.893749 [Byte1]: 69
2880 09:28:20.893800
2881 09:28:20.893850 Set Vref, RX VrefLevel [Byte0]: 70
2882 09:28:20.893901 [Byte1]: 70
2883 09:28:20.893951
2884 09:28:20.894002 Set Vref, RX VrefLevel [Byte0]: 71
2885 09:28:20.894052 [Byte1]: 71
2886 09:28:20.894102
2887 09:28:20.894153 Set Vref, RX VrefLevel [Byte0]: 72
2888 09:28:20.894246 [Byte1]: 72
2889 09:28:20.894297
2890 09:28:20.894347 Set Vref, RX VrefLevel [Byte0]: 73
2891 09:28:20.894399 [Byte1]: 73
2892 09:28:20.894451
2893 09:28:20.894501 Set Vref, RX VrefLevel [Byte0]: 74
2894 09:28:20.894552 [Byte1]: 74
2895 09:28:20.894603
2896 09:28:20.894653 Set Vref, RX VrefLevel [Byte0]: 75
2897 09:28:20.894704 [Byte1]: 75
2898 09:28:20.894755
2899 09:28:20.894806 Set Vref, RX VrefLevel [Byte0]: 76
2900 09:28:20.894857 [Byte1]: 76
2901 09:28:20.894908
2902 09:28:20.894959 Set Vref, RX VrefLevel [Byte0]: 77
2903 09:28:20.895010 [Byte1]: 77
2904 09:28:20.895060
2905 09:28:20.895110 Final RX Vref Byte 0 = 60 to rank0
2906 09:28:20.895162 Final RX Vref Byte 1 = 58 to rank0
2907 09:28:20.895213 Final RX Vref Byte 0 = 60 to rank1
2908 09:28:20.895264 Final RX Vref Byte 1 = 58 to rank1==
2909 09:28:20.895315 Dram Type= 6, Freq= 0, CH_0, rank 0
2910 09:28:20.895367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 09:28:20.895418 ==
2912 09:28:20.895469 DQS Delay:
2913 09:28:20.895520 DQS0 = 0, DQS1 = 0
2914 09:28:20.895571 DQM Delay:
2915 09:28:20.895623 DQM0 = 118, DQM1 = 107
2916 09:28:20.895722 DQ Delay:
2917 09:28:20.895774 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2918 09:28:20.895826 DQ4 =120, DQ5 =114, DQ6 =124, DQ7 =124
2919 09:28:20.895877 DQ8 =96, DQ9 =94, DQ10 =112, DQ11 =100
2920 09:28:20.895928 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2921 09:28:20.895979
2922 09:28:20.896030
2923 09:28:20.896080 [DQSOSCAuto] RK0, (LSB)MR18= 0x10fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 403 ps
2924 09:28:20.896132 CH0 RK0: MR19=403, MR18=10FC
2925 09:28:20.896183 CH0_RK0: MR19=0x403, MR18=0x10FC, DQSOSC=403, MR23=63, INC=40, DEC=26
2926 09:28:20.896235
2927 09:28:20.896285 ----->DramcWriteLeveling(PI) begin...
2928 09:28:20.896338 ==
2929 09:28:20.896389 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 09:28:20.896440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 09:28:20.896491 ==
2932 09:28:20.896543 Write leveling (Byte 0): 31 => 31
2933 09:28:20.896594 Write leveling (Byte 1): 28 => 28
2934 09:28:20.896645 DramcWriteLeveling(PI) end<-----
2935 09:28:20.896696
2936 09:28:20.896746 ==
2937 09:28:20.896797 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 09:28:20.896848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 09:28:20.896899 ==
2940 09:28:20.896950 [Gating] SW mode calibration
2941 09:28:20.897001 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2942 09:28:20.897053 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2943 09:28:20.897104 0 15 0 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
2944 09:28:20.897155 0 15 4 | B1->B0 | 3433 3434 | 1 1 | (1 1) (1 1)
2945 09:28:20.897206 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2946 09:28:20.897257 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2947 09:28:20.897308 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2948 09:28:20.897359 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2949 09:28:20.897410 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2950 09:28:20.897461 0 15 28 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2951 09:28:20.897512 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
2952 09:28:20.897563 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2953 09:28:20.897806 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2954 09:28:20.897870 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2955 09:28:20.897925 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2956 09:28:20.897976 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2957 09:28:20.898029 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2958 09:28:20.898081 1 0 28 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
2959 09:28:20.898133 1 1 0 | B1->B0 | 3636 4545 | 0 0 | (0 0) (1 1)
2960 09:28:20.898220 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2961 09:28:20.898272 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2962 09:28:20.898323 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 09:28:20.898375 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2964 09:28:20.898426 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2965 09:28:20.898477 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2966 09:28:20.898529 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2967 09:28:20.898581 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2968 09:28:20.898634 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2969 09:28:20.898684 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2970 09:28:20.898736 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2971 09:28:20.898787 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2972 09:28:20.898856 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2973 09:28:20.898946 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2974 09:28:20.899002 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2975 09:28:20.899055 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2976 09:28:20.899106 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 09:28:20.899158 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 09:28:20.899209 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 09:28:20.899260 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 09:28:20.899311 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 09:28:20.899362 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2982 09:28:20.899414 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2983 09:28:20.899465 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2984 09:28:20.899516 Total UI for P1: 0, mck2ui 16
2985 09:28:20.899568 best dqsien dly found for B0: ( 1, 3, 26)
2986 09:28:20.899619 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2987 09:28:20.899689 Total UI for P1: 0, mck2ui 16
2988 09:28:20.899757 best dqsien dly found for B1: ( 1, 4, 0)
2989 09:28:20.899809 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2990 09:28:20.899860 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2991 09:28:20.899911
2992 09:28:20.899962 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2993 09:28:20.900013 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2994 09:28:20.900064 [Gating] SW calibration Done
2995 09:28:20.900128 ==
2996 09:28:20.900180 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 09:28:20.900231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 09:28:20.900284 ==
2999 09:28:20.900335 RX Vref Scan: 0
3000 09:28:20.900387
3001 09:28:20.900438 RX Vref 0 -> 0, step: 1
3002 09:28:20.900489
3003 09:28:20.900540 RX Delay -40 -> 252, step: 8
3004 09:28:21.023178 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3005 09:28:21.023315 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3006 09:28:21.023378 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3007 09:28:21.023436 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3008 09:28:21.023492 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3009 09:28:21.023547 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3010 09:28:21.023601 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3011 09:28:21.023653 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3012 09:28:21.023706 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3013 09:28:21.023759 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3014 09:28:21.023812 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3015 09:28:21.023864 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3016 09:28:21.023916 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3017 09:28:21.023968 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3018 09:28:21.024020 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3019 09:28:21.024071 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3020 09:28:21.024122 ==
3021 09:28:21.024174 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 09:28:21.024224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 09:28:21.024276 ==
3024 09:28:21.024327 DQS Delay:
3025 09:28:21.024378 DQS0 = 0, DQS1 = 0
3026 09:28:21.024439 DQM Delay:
3027 09:28:21.024491 DQM0 = 116, DQM1 = 108
3028 09:28:21.024543 DQ Delay:
3029 09:28:21.024594 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3030 09:28:21.024645 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3031 09:28:21.024696 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3032 09:28:21.024760 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3033 09:28:21.024917
3034 09:28:21.025020
3035 09:28:21.025082 ==
3036 09:28:21.025136 Dram Type= 6, Freq= 0, CH_0, rank 1
3037 09:28:21.025212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3038 09:28:21.025374 ==
3039 09:28:21.025474
3040 09:28:21.025538
3041 09:28:21.025592 TX Vref Scan disable
3042 09:28:21.025645 == TX Byte 0 ==
3043 09:28:21.025698 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3044 09:28:21.025751 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3045 09:28:21.025803 == TX Byte 1 ==
3046 09:28:21.025944 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3047 09:28:21.026031 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3048 09:28:21.026115 ==
3049 09:28:21.026212 Dram Type= 6, Freq= 0, CH_0, rank 1
3050 09:28:21.026267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3051 09:28:21.026320 ==
3052 09:28:21.026371 TX Vref=22, minBit 1, minWin=25, winSum=412
3053 09:28:21.026424 TX Vref=24, minBit 4, minWin=25, winSum=414
3054 09:28:21.026475 TX Vref=26, minBit 13, minWin=25, winSum=424
3055 09:28:21.026527 TX Vref=28, minBit 13, minWin=24, winSum=423
3056 09:28:21.026578 TX Vref=30, minBit 13, minWin=25, winSum=429
3057 09:28:21.026630 TX Vref=32, minBit 13, minWin=25, winSum=429
3058 09:28:21.026682 [TxChooseVref] Worse bit 13, Min win 25, Win sum 429, Final Vref 30
3059 09:28:21.026734
3060 09:28:21.026785 Final TX Range 1 Vref 30
3061 09:28:21.026836
3062 09:28:21.026887 ==
3063 09:28:21.026938 Dram Type= 6, Freq= 0, CH_0, rank 1
3064 09:28:21.027191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 09:28:21.027281 ==
3066 09:28:21.027363
3067 09:28:21.027414
3068 09:28:21.027465 TX Vref Scan disable
3069 09:28:21.027517 == TX Byte 0 ==
3070 09:28:21.027568 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
3071 09:28:21.027620 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
3072 09:28:21.027672 == TX Byte 1 ==
3073 09:28:21.027723 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3074 09:28:21.027775 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3075 09:28:21.027825
3076 09:28:21.027876 [DATLAT]
3077 09:28:21.027927 Freq=1200, CH0 RK1
3078 09:28:21.027979
3079 09:28:21.028030 DATLAT Default: 0xd
3080 09:28:21.028081 0, 0xFFFF, sum = 0
3081 09:28:21.028134 1, 0xFFFF, sum = 0
3082 09:28:21.028186 2, 0xFFFF, sum = 0
3083 09:28:21.028238 3, 0xFFFF, sum = 0
3084 09:28:21.028291 4, 0xFFFF, sum = 0
3085 09:28:21.028343 5, 0xFFFF, sum = 0
3086 09:28:21.028405 6, 0xFFFF, sum = 0
3087 09:28:21.028458 7, 0xFFFF, sum = 0
3088 09:28:21.028511 8, 0xFFFF, sum = 0
3089 09:28:21.028570 9, 0xFFFF, sum = 0
3090 09:28:21.028623 10, 0xFFFF, sum = 0
3091 09:28:21.028675 11, 0xFFFF, sum = 0
3092 09:28:21.028776 12, 0x0, sum = 1
3093 09:28:21.028847 13, 0x0, sum = 2
3094 09:28:21.028900 14, 0x0, sum = 3
3095 09:28:21.028951 15, 0x0, sum = 4
3096 09:28:21.029004 best_step = 13
3097 09:28:21.029055
3098 09:28:21.029110 ==
3099 09:28:21.029189 Dram Type= 6, Freq= 0, CH_0, rank 1
3100 09:28:21.029271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 09:28:21.029351 ==
3102 09:28:21.029431 RX Vref Scan: 0
3103 09:28:21.029511
3104 09:28:21.029581 RX Vref 0 -> 0, step: 1
3105 09:28:21.029645
3106 09:28:21.029726 RX Delay -21 -> 252, step: 4
3107 09:28:21.029807 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3108 09:28:21.029900 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
3109 09:28:21.029983 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3110 09:28:21.030078 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3111 09:28:21.030187 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3112 09:28:21.030263 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3113 09:28:21.030316 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
3114 09:28:21.030405 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
3115 09:28:21.030467 iDelay=195, Bit 8, Center 98 (31 ~ 166) 136
3116 09:28:21.030552 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3117 09:28:21.030640 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3118 09:28:21.030727 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3119 09:28:21.030808 iDelay=195, Bit 12, Center 114 (47 ~ 182) 136
3120 09:28:21.030889 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
3121 09:28:21.030970 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3122 09:28:21.031052 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3123 09:28:21.031132 ==
3124 09:28:21.031216 Dram Type= 6, Freq= 0, CH_0, rank 1
3125 09:28:21.031301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3126 09:28:21.031382 ==
3127 09:28:21.031465 DQS Delay:
3128 09:28:21.031550 DQS0 = 0, DQS1 = 0
3129 09:28:21.031630 DQM Delay:
3130 09:28:21.031711 DQM0 = 116, DQM1 = 109
3131 09:28:21.031831 DQ Delay:
3132 09:28:21.031973 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3133 09:28:21.032056 DQ4 =116, DQ5 =110, DQ6 =124, DQ7 =124
3134 09:28:21.032118 DQ8 =98, DQ9 =94, DQ10 =112, DQ11 =104
3135 09:28:21.032175 DQ12 =114, DQ13 =114, DQ14 =120, DQ15 =116
3136 09:28:21.032231
3137 09:28:21.032315
3138 09:28:21.032398 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3139 09:28:21.032483 CH0 RK1: MR19=403, MR18=BE6
3140 09:28:21.032569 CH0_RK1: MR19=0x403, MR18=0xBE6, DQSOSC=405, MR23=63, INC=39, DEC=26
3141 09:28:21.032651 [RxdqsGatingPostProcess] freq 1200
3142 09:28:21.032733 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3143 09:28:21.032815 best DQS0 dly(2T, 0.5T) = (0, 11)
3144 09:28:21.032896 best DQS1 dly(2T, 0.5T) = (0, 12)
3145 09:28:21.032979 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3146 09:28:21.033067 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3147 09:28:21.033236 best DQS0 dly(2T, 0.5T) = (0, 11)
3148 09:28:21.033342 best DQS1 dly(2T, 0.5T) = (0, 12)
3149 09:28:21.033435 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3150 09:28:21.033540 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3151 09:28:21.033637 Pre-setting of DQS Precalculation
3152 09:28:21.033720 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3153 09:28:21.033812 ==
3154 09:28:21.033912 Dram Type= 6, Freq= 0, CH_1, rank 0
3155 09:28:21.034007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 09:28:21.034120 ==
3157 09:28:21.034231 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3158 09:28:21.034319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3159 09:28:21.034402 [CA 0] Center 38 (8~68) winsize 61
3160 09:28:21.034478 [CA 1] Center 38 (8~68) winsize 61
3161 09:28:21.034534 [CA 2] Center 34 (4~64) winsize 61
3162 09:28:21.034587 [CA 3] Center 33 (3~64) winsize 62
3163 09:28:21.034639 [CA 4] Center 34 (4~64) winsize 61
3164 09:28:21.034691 [CA 5] Center 33 (3~64) winsize 62
3165 09:28:21.034766
3166 09:28:21.034848 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3167 09:28:21.034929
3168 09:28:21.035016 [CATrainingPosCal] consider 1 rank data
3169 09:28:21.035100 u2DelayCellTimex100 = 270/100 ps
3170 09:28:21.035186 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3171 09:28:21.035274 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3172 09:28:21.035356 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3173 09:28:21.035438 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3174 09:28:21.035525 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3175 09:28:21.035607 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3176 09:28:21.035687
3177 09:28:21.035782 CA PerBit enable=1, Macro0, CA PI delay=33
3178 09:28:21.035884
3179 09:28:21.035979 [CBTSetCACLKResult] CA Dly = 33
3180 09:28:21.036060 CS Dly: 6 (0~37)
3181 09:28:21.036140 ==
3182 09:28:21.036222 Dram Type= 6, Freq= 0, CH_1, rank 1
3183 09:28:21.036304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 09:28:21.036385 ==
3185 09:28:21.036466 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3186 09:28:21.036549 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3187 09:28:21.036630 [CA 0] Center 37 (7~68) winsize 62
3188 09:28:21.036712 [CA 1] Center 38 (8~68) winsize 61
3189 09:28:21.036793 [CA 2] Center 34 (4~65) winsize 62
3190 09:28:21.036874 [CA 3] Center 33 (3~64) winsize 62
3191 09:28:21.036956 [CA 4] Center 34 (4~65) winsize 62
3192 09:28:21.037053 [CA 5] Center 33 (3~64) winsize 62
3193 09:28:21.037135
3194 09:28:21.037213 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3195 09:28:21.037268
3196 09:28:21.037320 [CATrainingPosCal] consider 2 rank data
3197 09:28:21.037372 u2DelayCellTimex100 = 270/100 ps
3198 09:28:21.037628 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3199 09:28:21.037688 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3200 09:28:21.037761 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3201 09:28:21.037846 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3202 09:28:21.037928 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3203 09:28:21.038016 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3204 09:28:21.038097
3205 09:28:21.038204 CA PerBit enable=1, Macro0, CA PI delay=33
3206 09:28:21.038278
3207 09:28:21.038331 [CBTSetCACLKResult] CA Dly = 33
3208 09:28:21.038384 CS Dly: 7 (0~40)
3209 09:28:21.038439
3210 09:28:21.038498 ----->DramcWriteLeveling(PI) begin...
3211 09:28:21.038552 ==
3212 09:28:21.038630 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 09:28:21.038717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 09:28:21.038800 ==
3215 09:28:21.038881 Write leveling (Byte 0): 23 => 23
3216 09:28:21.038966 Write leveling (Byte 1): 28 => 28
3217 09:28:21.039050 DramcWriteLeveling(PI) end<-----
3218 09:28:21.039136
3219 09:28:21.039220 ==
3220 09:28:21.039303 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 09:28:21.039390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 09:28:21.039472 ==
3223 09:28:21.039553 [Gating] SW mode calibration
3224 09:28:21.039640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3225 09:28:21.039758 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3226 09:28:21.039872 0 15 0 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
3227 09:28:21.039962 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3228 09:28:21.040078 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3229 09:28:21.040165 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3230 09:28:21.040254 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3231 09:28:21.040380 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3232 09:28:21.040464 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
3233 09:28:21.040546 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
3234 09:28:21.040628 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3235 09:28:21.040726 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3236 09:28:21.040855 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3237 09:28:21.040937 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3238 09:28:21.041018 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3239 09:28:21.041100 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3240 09:28:21.041181 1 0 24 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
3241 09:28:21.041263 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3242 09:28:21.041344 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3243 09:28:21.041425 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3244 09:28:21.041506 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3245 09:28:21.041588 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 09:28:21.041669 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3247 09:28:21.041750 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3248 09:28:21.041835 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3249 09:28:21.041920 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3250 09:28:21.042003 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3251 09:28:21.042088 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3252 09:28:21.042206 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3253 09:28:21.042311 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3254 09:28:21.042397 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3255 09:28:21.042514 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3256 09:28:21.042599 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3257 09:28:21.042683 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3258 09:28:21.042770 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3259 09:28:21.042852 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 09:28:21.042936 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 09:28:21.043020 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 09:28:21.043105 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 09:28:21.043189 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 09:28:21.043270 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 09:28:21.043355 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3266 09:28:21.043439 Total UI for P1: 0, mck2ui 16
3267 09:28:21.043526 best dqsien dly found for B0: ( 1, 3, 26)
3268 09:28:21.043609 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3269 09:28:21.043692 Total UI for P1: 0, mck2ui 16
3270 09:28:21.043780 best dqsien dly found for B1: ( 1, 3, 28)
3271 09:28:21.043863 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3272 09:28:21.043944 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3273 09:28:21.044034
3274 09:28:21.044131 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3275 09:28:21.044241 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3276 09:28:21.044323 [Gating] SW calibration Done
3277 09:28:21.044404 ==
3278 09:28:21.044488 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 09:28:21.044576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 09:28:21.044660 ==
3281 09:28:21.044741 RX Vref Scan: 0
3282 09:28:21.044823
3283 09:28:21.044907 RX Vref 0 -> 0, step: 1
3284 09:28:21.044992
3285 09:28:21.045074 RX Delay -40 -> 252, step: 8
3286 09:28:21.045161 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3287 09:28:21.045248 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3288 09:28:21.045331 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3289 09:28:21.045412 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3290 09:28:21.045505 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3291 09:28:21.045629 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3292 09:28:21.045715 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3293 09:28:21.045806 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3294 09:28:21.045894 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3295 09:28:21.045976 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3296 09:28:21.046069 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3297 09:28:21.046154 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3298 09:28:21.046285 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3299 09:28:21.046579 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3300 09:28:21.046681 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3301 09:28:21.046764 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3302 09:28:21.046846 ==
3303 09:28:21.046927 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 09:28:21.047019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 09:28:21.047101 ==
3306 09:28:21.047181 DQS Delay:
3307 09:28:21.047262 DQS0 = 0, DQS1 = 0
3308 09:28:21.047350 DQM Delay:
3309 09:28:21.047434 DQM0 = 118, DQM1 = 110
3310 09:28:21.047515 DQ Delay:
3311 09:28:21.047596 DQ0 =119, DQ1 =115, DQ2 =111, DQ3 =119
3312 09:28:21.047677 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3313 09:28:21.047758 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =99
3314 09:28:21.047848 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3315 09:28:21.047931
3316 09:28:21.048011
3317 09:28:21.048091 ==
3318 09:28:21.048172 Dram Type= 6, Freq= 0, CH_1, rank 0
3319 09:28:21.048310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3320 09:28:21.048412 ==
3321 09:28:21.048501
3322 09:28:21.048582
3323 09:28:21.048663 TX Vref Scan disable
3324 09:28:21.048756 == TX Byte 0 ==
3325 09:28:21.048842 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3326 09:28:21.048933 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3327 09:28:21.049021 == TX Byte 1 ==
3328 09:28:21.049104 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3329 09:28:21.049198 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3330 09:28:21.049282 ==
3331 09:28:21.049427 Dram Type= 6, Freq= 0, CH_1, rank 0
3332 09:28:21.049531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3333 09:28:21.049613 ==
3334 09:28:21.049697 TX Vref=22, minBit 10, minWin=25, winSum=417
3335 09:28:21.049783 TX Vref=24, minBit 9, minWin=25, winSum=420
3336 09:28:21.049870 TX Vref=26, minBit 10, minWin=25, winSum=425
3337 09:28:21.049953 TX Vref=28, minBit 10, minWin=25, winSum=426
3338 09:28:21.050036 TX Vref=30, minBit 1, minWin=26, winSum=426
3339 09:28:21.050122 TX Vref=32, minBit 9, minWin=25, winSum=422
3340 09:28:21.050249 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 30
3341 09:28:21.050335
3342 09:28:21.050416 Final TX Range 1 Vref 30
3343 09:28:21.050504
3344 09:28:21.050587 ==
3345 09:28:21.050671 Dram Type= 6, Freq= 0, CH_1, rank 0
3346 09:28:21.050758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3347 09:28:21.050840 ==
3348 09:28:21.050921
3349 09:28:21.051007
3350 09:28:21.051089 TX Vref Scan disable
3351 09:28:21.051170 == TX Byte 0 ==
3352 09:28:21.051257 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3353 09:28:21.051342 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3354 09:28:21.051426 == TX Byte 1 ==
3355 09:28:21.051512 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3356 09:28:21.051595 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3357 09:28:21.051675
3358 09:28:21.051786 [DATLAT]
3359 09:28:21.051897 Freq=1200, CH1 RK0
3360 09:28:21.051978
3361 09:28:21.052057 DATLAT Default: 0xd
3362 09:28:21.052174 0, 0xFFFF, sum = 0
3363 09:28:21.052272 1, 0xFFFF, sum = 0
3364 09:28:21.052355 2, 0xFFFF, sum = 0
3365 09:28:21.052479 3, 0xFFFF, sum = 0
3366 09:28:21.052563 4, 0xFFFF, sum = 0
3367 09:28:21.052645 5, 0xFFFF, sum = 0
3368 09:28:21.052727 6, 0xFFFF, sum = 0
3369 09:28:21.052809 7, 0xFFFF, sum = 0
3370 09:28:21.052892 8, 0xFFFF, sum = 0
3371 09:28:21.052974 9, 0xFFFF, sum = 0
3372 09:28:21.053057 10, 0xFFFF, sum = 0
3373 09:28:21.053139 11, 0xFFFF, sum = 0
3374 09:28:21.053221 12, 0x0, sum = 1
3375 09:28:21.053304 13, 0x0, sum = 2
3376 09:28:21.053386 14, 0x0, sum = 3
3377 09:28:21.053468 15, 0x0, sum = 4
3378 09:28:21.053594 best_step = 13
3379 09:28:21.053675
3380 09:28:21.053755 ==
3381 09:28:21.053836 Dram Type= 6, Freq= 0, CH_1, rank 0
3382 09:28:21.053917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3383 09:28:21.054004 ==
3384 09:28:21.054089 RX Vref Scan: 1
3385 09:28:21.054196
3386 09:28:21.054265 Set Vref Range= 32 -> 127
3387 09:28:21.054317
3388 09:28:21.054379 RX Vref 32 -> 127, step: 1
3389 09:28:21.054444
3390 09:28:21.054527 RX Delay -21 -> 252, step: 4
3391 09:28:21.054610
3392 09:28:21.054694 Set Vref, RX VrefLevel [Byte0]: 32
3393 09:28:21.054869 [Byte1]: 32
3394 09:28:21.054999
3395 09:28:21.055114 Set Vref, RX VrefLevel [Byte0]: 33
3396 09:28:21.055222 [Byte1]: 33
3397 09:28:21.055304
3398 09:28:21.055391 Set Vref, RX VrefLevel [Byte0]: 34
3399 09:28:21.055472 [Byte1]: 34
3400 09:28:21.055553
3401 09:28:21.055639 Set Vref, RX VrefLevel [Byte0]: 35
3402 09:28:21.055724 [Byte1]: 35
3403 09:28:21.055808
3404 09:28:21.055892 Set Vref, RX VrefLevel [Byte0]: 36
3405 09:28:21.055976 [Byte1]: 36
3406 09:28:21.056060
3407 09:28:21.056146 Set Vref, RX VrefLevel [Byte0]: 37
3408 09:28:21.056228 [Byte1]: 37
3409 09:28:21.056309
3410 09:28:21.056393 Set Vref, RX VrefLevel [Byte0]: 38
3411 09:28:21.056478 [Byte1]: 38
3412 09:28:21.056562
3413 09:28:21.056645 Set Vref, RX VrefLevel [Byte0]: 39
3414 09:28:21.056726 [Byte1]: 39
3415 09:28:21.056806
3416 09:28:21.056893 Set Vref, RX VrefLevel [Byte0]: 40
3417 09:28:21.056975 [Byte1]: 40
3418 09:28:21.057055
3419 09:28:21.057135 Set Vref, RX VrefLevel [Byte0]: 41
3420 09:28:21.057250 [Byte1]: 41
3421 09:28:21.057342
3422 09:28:21.057424 Set Vref, RX VrefLevel [Byte0]: 42
3423 09:28:21.057504 [Byte1]: 42
3424 09:28:21.057584
3425 09:28:21.057664 Set Vref, RX VrefLevel [Byte0]: 43
3426 09:28:21.057745 [Byte1]: 43
3427 09:28:21.057824
3428 09:28:21.057905 Set Vref, RX VrefLevel [Byte0]: 44
3429 09:28:21.057985 [Byte1]: 44
3430 09:28:21.058065
3431 09:28:21.058145 Set Vref, RX VrefLevel [Byte0]: 45
3432 09:28:21.058248 [Byte1]: 45
3433 09:28:21.058301
3434 09:28:21.058357 Set Vref, RX VrefLevel [Byte0]: 46
3435 09:28:21.058419 [Byte1]: 46
3436 09:28:21.058502
3437 09:28:21.058585 Set Vref, RX VrefLevel [Byte0]: 47
3438 09:28:21.058717 [Byte1]: 47
3439 09:28:21.058811
3440 09:28:21.058895 Set Vref, RX VrefLevel [Byte0]: 48
3441 09:28:21.058982 [Byte1]: 48
3442 09:28:21.059063
3443 09:28:21.059144 Set Vref, RX VrefLevel [Byte0]: 49
3444 09:28:21.059228 [Byte1]: 49
3445 09:28:21.059313
3446 09:28:21.059394 Set Vref, RX VrefLevel [Byte0]: 50
3447 09:28:21.059478 [Byte1]: 50
3448 09:28:21.059561
3449 09:28:21.059648 Set Vref, RX VrefLevel [Byte0]: 51
3450 09:28:21.059729 [Byte1]: 51
3451 09:28:21.059809
3452 09:28:21.059894 Set Vref, RX VrefLevel [Byte0]: 52
3453 09:28:21.059978 [Byte1]: 52
3454 09:28:21.060058
3455 09:28:21.060143 Set Vref, RX VrefLevel [Byte0]: 53
3456 09:28:21.060229 [Byte1]: 53
3457 09:28:21.060309
3458 09:28:21.060390 Set Vref, RX VrefLevel [Byte0]: 54
3459 09:28:21.060474 [Byte1]: 54
3460 09:28:21.060556
3461 09:28:21.060651 Set Vref, RX VrefLevel [Byte0]: 55
3462 09:28:21.060737 [Byte1]: 55
3463 09:28:21.060820
3464 09:28:21.060908 Set Vref, RX VrefLevel [Byte0]: 56
3465 09:28:21.061194 [Byte1]: 56
3466 09:28:21.061281
3467 09:28:21.061375 Set Vref, RX VrefLevel [Byte0]: 57
3468 09:28:21.061458 [Byte1]: 57
3469 09:28:21.061577
3470 09:28:21.061667 Set Vref, RX VrefLevel [Byte0]: 58
3471 09:28:21.061749 [Byte1]: 58
3472 09:28:21.061829
3473 09:28:21.061917 Set Vref, RX VrefLevel [Byte0]: 59
3474 09:28:21.062008 [Byte1]: 59
3475 09:28:21.062089
3476 09:28:21.062183 Set Vref, RX VrefLevel [Byte0]: 60
3477 09:28:21.062271 [Byte1]: 60
3478 09:28:21.062353
3479 09:28:21.062442 Set Vref, RX VrefLevel [Byte0]: 61
3480 09:28:21.062513 [Byte1]: 61
3481 09:28:21.062569
3482 09:28:21.062649 Set Vref, RX VrefLevel [Byte0]: 62
3483 09:28:21.062743 [Byte1]: 62
3484 09:28:21.062837
3485 09:28:21.062924 Set Vref, RX VrefLevel [Byte0]: 63
3486 09:28:21.063006 [Byte1]: 63
3487 09:28:21.063092
3488 09:28:21.063148 Set Vref, RX VrefLevel [Byte0]: 64
3489 09:28:21.063201 [Byte1]: 64
3490 09:28:21.063253
3491 09:28:21.063305 Set Vref, RX VrefLevel [Byte0]: 65
3492 09:28:21.063374 [Byte1]: 65
3493 09:28:21.063428
3494 09:28:21.063479 Set Vref, RX VrefLevel [Byte0]: 66
3495 09:28:21.063530 [Byte1]: 66
3496 09:28:21.063581
3497 09:28:21.063650 Set Vref, RX VrefLevel [Byte0]: 67
3498 09:28:21.063704 [Byte1]: 67
3499 09:28:21.063755
3500 09:28:21.063806 Final RX Vref Byte 0 = 48 to rank0
3501 09:28:21.063858 Final RX Vref Byte 1 = 54 to rank0
3502 09:28:21.063927 Final RX Vref Byte 0 = 48 to rank1
3503 09:28:21.063981 Final RX Vref Byte 1 = 54 to rank1==
3504 09:28:21.064033 Dram Type= 6, Freq= 0, CH_1, rank 0
3505 09:28:21.064084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 09:28:21.064146 ==
3507 09:28:21.064201 DQS Delay:
3508 09:28:21.064253 DQS0 = 0, DQS1 = 0
3509 09:28:21.064305 DQM Delay:
3510 09:28:21.064357 DQM0 = 117, DQM1 = 111
3511 09:28:21.064424 DQ Delay:
3512 09:28:21.064478 DQ0 =118, DQ1 =114, DQ2 =108, DQ3 =114
3513 09:28:21.064530 DQ4 =116, DQ5 =128, DQ6 =126, DQ7 =114
3514 09:28:21.064581 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =100
3515 09:28:21.064644 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =120
3516 09:28:21.064699
3517 09:28:21.064750
3518 09:28:21.064802 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3519 09:28:21.064856 CH1 RK0: MR19=403, MR18=3F7
3520 09:28:21.064940 CH1_RK0: MR19=0x403, MR18=0x3F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3521 09:28:21.065014
3522 09:28:21.065068 ----->DramcWriteLeveling(PI) begin...
3523 09:28:21.065121 ==
3524 09:28:21.065185 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 09:28:21.065249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 09:28:21.065305 ==
3527 09:28:21.065357 Write leveling (Byte 0): 24 => 24
3528 09:28:21.065423 Write leveling (Byte 1): 29 => 29
3529 09:28:21.065511 DramcWriteLeveling(PI) end<-----
3530 09:28:21.065592
3531 09:28:21.065682 ==
3532 09:28:21.065770 Dram Type= 6, Freq= 0, CH_1, rank 1
3533 09:28:21.065855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3534 09:28:21.065947 ==
3535 09:28:21.066029 [Gating] SW mode calibration
3536 09:28:21.066116 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3537 09:28:21.066233 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3538 09:28:21.066289 0 15 0 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
3539 09:28:21.066342 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3540 09:28:21.066403 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3541 09:28:21.066480 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3542 09:28:21.066558 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3543 09:28:21.066634 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3544 09:28:21.066722 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
3545 09:28:21.066807 0 15 28 | B1->B0 | 2626 2a2a | 0 1 | (0 1) (1 0)
3546 09:28:21.066900 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3547 09:28:21.066995 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3548 09:28:21.067080 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3549 09:28:21.067162 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3550 09:28:21.067255 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3551 09:28:21.067340 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3552 09:28:21.067425 1 0 24 | B1->B0 | 3131 2323 | 1 0 | (0 0) (0 0)
3553 09:28:21.067519 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3554 09:28:21.067601 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3555 09:28:21.067684 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3556 09:28:21.067776 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3557 09:28:21.067863 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 09:28:21.067947 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 09:28:21.068040 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3560 09:28:21.068123 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3561 09:28:21.068204 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3562 09:28:21.068293 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 09:28:21.068375 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 09:28:21.068456 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 09:28:21.068545 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 09:28:21.068628 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3567 09:28:21.068710 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3568 09:28:21.068799 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3569 09:28:21.068882 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3570 09:28:21.068963 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3571 09:28:21.069051 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3572 09:28:21.069134 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3573 09:28:21.069215 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 09:28:21.069298 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 09:28:21.069361 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 09:28:21.069413 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3577 09:28:21.069465 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3578 09:28:21.069719 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3579 09:28:21.069779 Total UI for P1: 0, mck2ui 16
3580 09:28:21.069839 best dqsien dly found for B0: ( 1, 3, 26)
3581 09:28:21.069900 Total UI for P1: 0, mck2ui 16
3582 09:28:21.069954 best dqsien dly found for B1: ( 1, 3, 26)
3583 09:28:21.070006 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3584 09:28:21.070057 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3585 09:28:21.070143
3586 09:28:21.070254 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3587 09:28:21.070312 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3588 09:28:21.070381 [Gating] SW calibration Done
3589 09:28:21.070435 ==
3590 09:28:21.070487 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 09:28:21.070539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 09:28:21.070614 ==
3593 09:28:21.070669 RX Vref Scan: 0
3594 09:28:21.070721
3595 09:28:21.070772 RX Vref 0 -> 0, step: 1
3596 09:28:21.070826
3597 09:28:21.070883 RX Delay -40 -> 252, step: 8
3598 09:28:21.070966 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3599 09:28:21.071049 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3600 09:28:21.071123 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3601 09:28:21.071204 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3602 09:28:21.071291 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3603 09:28:21.071359 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3604 09:28:21.071443 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3605 09:28:21.071529 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3606 09:28:21.071620 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3607 09:28:21.071702 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3608 09:28:21.071821 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3609 09:28:21.071913 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3610 09:28:21.071994 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3611 09:28:21.072084 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3612 09:28:21.072200 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3613 09:28:21.072285 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3614 09:28:21.072382 ==
3615 09:28:21.072470 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 09:28:21.072553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 09:28:21.072634 ==
3618 09:28:21.072719 DQS Delay:
3619 09:28:21.072802 DQS0 = 0, DQS1 = 0
3620 09:28:21.072887 DQM Delay:
3621 09:28:21.072971 DQM0 = 118, DQM1 = 110
3622 09:28:21.073054 DQ Delay:
3623 09:28:21.073140 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3624 09:28:21.073225 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3625 09:28:21.073308 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3626 09:28:21.073389 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3627 09:28:21.073472
3628 09:28:21.073554
3629 09:28:21.073639 ==
3630 09:28:21.073723 Dram Type= 6, Freq= 0, CH_1, rank 1
3631 09:28:21.073807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3632 09:28:21.073888 ==
3633 09:28:21.073971
3634 09:28:21.074053
3635 09:28:21.074137 TX Vref Scan disable
3636 09:28:21.074264 == TX Byte 0 ==
3637 09:28:21.074346 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3638 09:28:21.074408 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3639 09:28:21.074461 == TX Byte 1 ==
3640 09:28:21.074513 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3641 09:28:21.074565 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3642 09:28:21.074624 ==
3643 09:28:21.074681 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 09:28:21.074733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 09:28:21.074785 ==
3646 09:28:21.074842 TX Vref=22, minBit 11, minWin=25, winSum=420
3647 09:28:21.074899 TX Vref=24, minBit 0, minWin=26, winSum=428
3648 09:28:21.074952 TX Vref=26, minBit 0, minWin=26, winSum=431
3649 09:28:21.075004 TX Vref=28, minBit 5, minWin=26, winSum=430
3650 09:28:21.075056 TX Vref=30, minBit 6, minWin=26, winSum=430
3651 09:28:21.075107 TX Vref=32, minBit 1, minWin=26, winSum=432
3652 09:28:21.075210 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 32
3653 09:28:21.075278
3654 09:28:21.075330 Final TX Range 1 Vref 32
3655 09:28:21.075382
3656 09:28:21.075450 ==
3657 09:28:21.075540 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 09:28:21.075623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 09:28:21.075707 ==
3660 09:28:21.075793
3661 09:28:21.075873
3662 09:28:21.075956 TX Vref Scan disable
3663 09:28:21.076042 == TX Byte 0 ==
3664 09:28:21.076123 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3665 09:28:21.076212 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3666 09:28:21.076295 == TX Byte 1 ==
3667 09:28:21.076376 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3668 09:28:21.076465 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3669 09:28:21.076547
3670 09:28:21.076627 [DATLAT]
3671 09:28:21.076715 Freq=1200, CH1 RK1
3672 09:28:21.076797
3673 09:28:21.076884 DATLAT Default: 0xd
3674 09:28:21.076975 0, 0xFFFF, sum = 0
3675 09:28:21.077062 1, 0xFFFF, sum = 0
3676 09:28:21.077150 2, 0xFFFF, sum = 0
3677 09:28:21.077245 3, 0xFFFF, sum = 0
3678 09:28:21.077332 4, 0xFFFF, sum = 0
3679 09:28:21.077417 5, 0xFFFF, sum = 0
3680 09:28:21.077508 6, 0xFFFF, sum = 0
3681 09:28:21.077593 7, 0xFFFF, sum = 0
3682 09:28:21.077680 8, 0xFFFF, sum = 0
3683 09:28:21.077773 9, 0xFFFF, sum = 0
3684 09:28:21.077856 10, 0xFFFF, sum = 0
3685 09:28:21.077947 11, 0xFFFF, sum = 0
3686 09:28:21.078036 12, 0x0, sum = 1
3687 09:28:21.078119 13, 0x0, sum = 2
3688 09:28:21.078248 14, 0x0, sum = 3
3689 09:28:21.078335 15, 0x0, sum = 4
3690 09:28:21.078421 best_step = 13
3691 09:28:21.078534
3692 09:28:21.078638 ==
3693 09:28:21.078720 Dram Type= 6, Freq= 0, CH_1, rank 1
3694 09:28:21.078810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3695 09:28:21.078905 ==
3696 09:28:21.078992 RX Vref Scan: 0
3697 09:28:21.079075
3698 09:28:21.079163 RX Vref 0 -> 0, step: 1
3699 09:28:21.079251
3700 09:28:21.079341 RX Delay -21 -> 252, step: 4
3701 09:28:21.079423 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3702 09:28:21.079516 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3703 09:28:21.079613 iDelay=199, Bit 2, Center 108 (47 ~ 170) 124
3704 09:28:21.079695 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3705 09:28:21.079766 iDelay=199, Bit 4, Center 116 (51 ~ 182) 132
3706 09:28:21.079835 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3707 09:28:21.079888 iDelay=199, Bit 6, Center 132 (67 ~ 198) 132
3708 09:28:21.079941 iDelay=199, Bit 7, Center 114 (51 ~ 178) 128
3709 09:28:21.080033 iDelay=199, Bit 8, Center 98 (35 ~ 162) 128
3710 09:28:21.080124 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3711 09:28:21.080206 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3712 09:28:21.080295 iDelay=199, Bit 11, Center 102 (39 ~ 166) 128
3713 09:28:21.080383 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3714 09:28:21.080467 iDelay=199, Bit 13, Center 120 (55 ~ 186) 132
3715 09:28:21.080559 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3716 09:28:21.080641 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3717 09:28:21.080922 ==
3718 09:28:21.081022 Dram Type= 6, Freq= 0, CH_1, rank 1
3719 09:28:21.081107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3720 09:28:21.081189 ==
3721 09:28:21.081275 DQS Delay:
3722 09:28:21.081356 DQS0 = 0, DQS1 = 0
3723 09:28:21.081437 DQM Delay:
3724 09:28:21.081526 DQM0 = 117, DQM1 = 111
3725 09:28:21.081606 DQ Delay:
3726 09:28:21.081688 DQ0 =120, DQ1 =112, DQ2 =108, DQ3 =112
3727 09:28:21.081769 DQ4 =116, DQ5 =128, DQ6 =132, DQ7 =114
3728 09:28:21.081859 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =102
3729 09:28:21.081942 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =118
3730 09:28:21.082022
3731 09:28:21.082109
3732 09:28:21.082226 [DQSOSCAuto] RK1, (LSB)MR18= 0xf8f2, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
3733 09:28:21.082281 CH1 RK1: MR19=303, MR18=F8F2
3734 09:28:21.082345 CH1_RK1: MR19=0x303, MR18=0xF8F2, DQSOSC=413, MR23=63, INC=38, DEC=25
3735 09:28:21.082401 [RxdqsGatingPostProcess] freq 1200
3736 09:28:21.082453 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3737 09:28:21.082505 best DQS0 dly(2T, 0.5T) = (0, 11)
3738 09:28:21.082557 best DQS1 dly(2T, 0.5T) = (0, 11)
3739 09:28:21.082625 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3740 09:28:21.082677 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3741 09:28:21.082728 best DQS0 dly(2T, 0.5T) = (0, 11)
3742 09:28:21.082780 best DQS1 dly(2T, 0.5T) = (0, 11)
3743 09:28:21.082830 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3744 09:28:21.082900 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3745 09:28:21.082953 Pre-setting of DQS Precalculation
3746 09:28:21.083005 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3747 09:28:21.083056 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3748 09:28:21.083109 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3749 09:28:21.083178
3750 09:28:21.083231
3751 09:28:21.083282 [Calibration Summary] 2400 Mbps
3752 09:28:21.083334 CH 0, Rank 0
3753 09:28:21.083393 SW Impedance : PASS
3754 09:28:21.083451 DUTY Scan : NO K
3755 09:28:21.083512 ZQ Calibration : PASS
3756 09:28:21.083567 Jitter Meter : NO K
3757 09:28:21.083619 CBT Training : PASS
3758 09:28:21.083693 Write leveling : PASS
3759 09:28:21.083755 RX DQS gating : PASS
3760 09:28:21.083825 RX DQ/DQS(RDDQC) : PASS
3761 09:28:21.083929 TX DQ/DQS : PASS
3762 09:28:21.084039 RX DATLAT : PASS
3763 09:28:21.084125 RX DQ/DQS(Engine): PASS
3764 09:28:21.084215 TX OE : NO K
3765 09:28:21.084311 All Pass.
3766 09:28:21.084398
3767 09:28:21.084487 CH 0, Rank 1
3768 09:28:21.084586 SW Impedance : PASS
3769 09:28:21.084671 DUTY Scan : NO K
3770 09:28:21.084752 ZQ Calibration : PASS
3771 09:28:21.084845 Jitter Meter : NO K
3772 09:28:21.084933 CBT Training : PASS
3773 09:28:21.085026 Write leveling : PASS
3774 09:28:21.085113 RX DQS gating : PASS
3775 09:28:21.085195 RX DQ/DQS(RDDQC) : PASS
3776 09:28:21.085286 TX DQ/DQS : PASS
3777 09:28:21.085374 RX DATLAT : PASS
3778 09:28:21.085456 RX DQ/DQS(Engine): PASS
3779 09:28:21.085544 TX OE : NO K
3780 09:28:21.085632 All Pass.
3781 09:28:21.085722
3782 09:28:21.085808 CH 1, Rank 0
3783 09:28:21.085894 SW Impedance : PASS
3784 09:28:21.085985 DUTY Scan : NO K
3785 09:28:21.086072 ZQ Calibration : PASS
3786 09:28:21.086155 Jitter Meter : NO K
3787 09:28:21.086287 CBT Training : PASS
3788 09:28:21.086374 Write leveling : PASS
3789 09:28:21.086462 RX DQS gating : PASS
3790 09:28:21.086548 RX DQ/DQS(RDDQC) : PASS
3791 09:28:21.086634 TX DQ/DQS : PASS
3792 09:28:21.086725 RX DATLAT : PASS
3793 09:28:21.086808 RX DQ/DQS(Engine): PASS
3794 09:28:21.086894 TX OE : NO K
3795 09:28:21.086987 All Pass.
3796 09:28:21.087069
3797 09:28:21.087155 CH 1, Rank 1
3798 09:28:21.087248 SW Impedance : PASS
3799 09:28:21.087333 DUTY Scan : NO K
3800 09:28:21.087419 ZQ Calibration : PASS
3801 09:28:21.087509 Jitter Meter : NO K
3802 09:28:21.087595 CBT Training : PASS
3803 09:28:21.087682 Write leveling : PASS
3804 09:28:21.087765 RX DQS gating : PASS
3805 09:28:21.087845 RX DQ/DQS(RDDQC) : PASS
3806 09:28:21.087932 TX DQ/DQS : PASS
3807 09:28:21.088015 RX DATLAT : PASS
3808 09:28:21.088096 RX DQ/DQS(Engine): PASS
3809 09:28:21.088187 TX OE : NO K
3810 09:28:21.088323 All Pass.
3811 09:28:21.088416
3812 09:28:21.088505 DramC Write-DBI off
3813 09:28:21.088587 PER_BANK_REFRESH: Hybrid Mode
3814 09:28:21.088676 TX_TRACKING: ON
3815 09:28:21.088762 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3816 09:28:21.088847 [FAST_K] Save calibration result to emmc
3817 09:28:21.088942 dramc_set_vcore_voltage set vcore to 650000
3818 09:28:21.089028 Read voltage for 600, 5
3819 09:28:21.089116 Vio18 = 0
3820 09:28:21.089207 Vcore = 650000
3821 09:28:21.089289 Vdram = 0
3822 09:28:21.089369 Vddq = 0
3823 09:28:21.089462 Vmddr = 0
3824 09:28:21.089547 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3825 09:28:21.089619 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3826 09:28:21.089695 MEM_TYPE=3, freq_sel=19
3827 09:28:21.089752 sv_algorithm_assistance_LP4_1600
3828 09:28:21.089805 ============ PULL DRAM RESETB DOWN ============
3829 09:28:21.089858 ========== PULL DRAM RESETB DOWN end =========
3830 09:28:21.089944 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3831 09:28:21.090033 ===================================
3832 09:28:21.090128 LPDDR4 DRAM CONFIGURATION
3833 09:28:21.090249 ===================================
3834 09:28:21.090331 EX_ROW_EN[0] = 0x0
3835 09:28:21.090421 EX_ROW_EN[1] = 0x0
3836 09:28:21.090489 LP4Y_EN = 0x0
3837 09:28:21.090544 WORK_FSP = 0x0
3838 09:28:21.090615 WL = 0x2
3839 09:28:21.090697 RL = 0x2
3840 09:28:21.090783 BL = 0x2
3841 09:28:21.090873 RPST = 0x0
3842 09:28:21.090954 RD_PRE = 0x0
3843 09:28:21.091034 WR_PRE = 0x1
3844 09:28:21.091127 WR_PST = 0x0
3845 09:28:21.091211 DBI_WR = 0x0
3846 09:28:21.091301 DBI_RD = 0x0
3847 09:28:21.091388 OTF = 0x1
3848 09:28:21.091474 ===================================
3849 09:28:21.091566 ===================================
3850 09:28:21.091655 ANA top config
3851 09:28:21.091743 ===================================
3852 09:28:21.091830 DLL_ASYNC_EN = 0
3853 09:28:21.091918 ALL_SLAVE_EN = 1
3854 09:28:21.092008 NEW_RANK_MODE = 1
3855 09:28:21.092093 DLL_IDLE_MODE = 1
3856 09:28:21.092174 LP45_APHY_COMB_EN = 1
3857 09:28:21.092262 TX_ODT_DIS = 1
3858 09:28:21.092349 NEW_8X_MODE = 1
3859 09:28:21.092470 ===================================
3860 09:28:21.092559 ===================================
3861 09:28:21.092646 data_rate = 1200
3862 09:28:21.092739 CKR = 1
3863 09:28:21.093015 DQ_P2S_RATIO = 8
3864 09:28:21.094457 ===================================
3865 09:28:21.098088 CA_P2S_RATIO = 8
3866 09:28:21.101526 DQ_CA_OPEN = 0
3867 09:28:21.104458 DQ_SEMI_OPEN = 0
3868 09:28:21.108039 CA_SEMI_OPEN = 0
3869 09:28:21.108145 CA_FULL_RATE = 0
3870 09:28:21.111262 DQ_CKDIV4_EN = 1
3871 09:28:21.114770 CA_CKDIV4_EN = 1
3872 09:28:21.117753 CA_PREDIV_EN = 0
3873 09:28:21.121345 PH8_DLY = 0
3874 09:28:21.124333 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3875 09:28:21.124440 DQ_AAMCK_DIV = 4
3876 09:28:21.127344 CA_AAMCK_DIV = 4
3877 09:28:21.130884 CA_ADMCK_DIV = 4
3878 09:28:21.134436 DQ_TRACK_CA_EN = 0
3879 09:28:21.137400 CA_PICK = 600
3880 09:28:21.141265 CA_MCKIO = 600
3881 09:28:21.144079 MCKIO_SEMI = 0
3882 09:28:21.144193 PLL_FREQ = 2288
3883 09:28:21.147293 DQ_UI_PI_RATIO = 32
3884 09:28:21.150872 CA_UI_PI_RATIO = 0
3885 09:28:21.153836 ===================================
3886 09:28:21.157234 ===================================
3887 09:28:21.160860 memory_type:LPDDR4
3888 09:28:21.160969 GP_NUM : 10
3889 09:28:21.163940 SRAM_EN : 1
3890 09:28:21.167535 MD32_EN : 0
3891 09:28:21.170652 ===================================
3892 09:28:21.170739 [ANA_INIT] >>>>>>>>>>>>>>
3893 09:28:21.173671 <<<<<< [CONFIGURE PHASE]: ANA_TX
3894 09:28:21.177221 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3895 09:28:21.180256 ===================================
3896 09:28:21.184272 data_rate = 1200,PCW = 0X5800
3897 09:28:21.187001 ===================================
3898 09:28:21.190129 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3899 09:28:21.196766 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3900 09:28:21.203542 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3901 09:28:21.207073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3902 09:28:21.210138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3903 09:28:21.213705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3904 09:28:21.216801 [ANA_INIT] flow start
3905 09:28:21.216924 [ANA_INIT] PLL >>>>>>>>
3906 09:28:21.220392 [ANA_INIT] PLL <<<<<<<<
3907 09:28:21.223295 [ANA_INIT] MIDPI >>>>>>>>
3908 09:28:21.223405 [ANA_INIT] MIDPI <<<<<<<<
3909 09:28:21.226868 [ANA_INIT] DLL >>>>>>>>
3910 09:28:21.230335 [ANA_INIT] flow end
3911 09:28:21.233377 ============ LP4 DIFF to SE enter ============
3912 09:28:21.236868 ============ LP4 DIFF to SE exit ============
3913 09:28:21.239976 [ANA_INIT] <<<<<<<<<<<<<
3914 09:28:21.243500 [Flow] Enable top DCM control >>>>>
3915 09:28:21.246927 [Flow] Enable top DCM control <<<<<
3916 09:28:21.249844 Enable DLL master slave shuffle
3917 09:28:21.253078 ==============================================================
3918 09:28:21.256607 Gating Mode config
3919 09:28:21.263102 ==============================================================
3920 09:28:21.263183 Config description:
3921 09:28:21.272999 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3922 09:28:21.279713 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3923 09:28:21.286275 SELPH_MODE 0: By rank 1: By Phase
3924 09:28:21.289367 ==============================================================
3925 09:28:21.292596 GAT_TRACK_EN = 1
3926 09:28:21.296334 RX_GATING_MODE = 2
3927 09:28:21.299176 RX_GATING_TRACK_MODE = 2
3928 09:28:21.302159 SELPH_MODE = 1
3929 09:28:21.305841 PICG_EARLY_EN = 1
3930 09:28:21.308962 VALID_LAT_VALUE = 1
3931 09:28:21.315440 ==============================================================
3932 09:28:21.318963 Enter into Gating configuration >>>>
3933 09:28:21.322424 Exit from Gating configuration <<<<
3934 09:28:21.325201 Enter into DVFS_PRE_config >>>>>
3935 09:28:21.335476 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3936 09:28:21.338389 Exit from DVFS_PRE_config <<<<<
3937 09:28:21.342105 Enter into PICG configuration >>>>
3938 09:28:21.345252 Exit from PICG configuration <<<<
3939 09:28:21.348676 [RX_INPUT] configuration >>>>>
3940 09:28:21.348757 [RX_INPUT] configuration <<<<<
3941 09:28:21.355449 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3942 09:28:21.361821 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3943 09:28:21.364922 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3944 09:28:21.371435 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3945 09:28:21.378467 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3946 09:28:21.385111 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3947 09:28:21.388216 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3948 09:28:21.391307 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3949 09:28:21.398099 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3950 09:28:21.401093 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3951 09:28:21.404674 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3952 09:28:21.411573 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3953 09:28:21.414525 ===================================
3954 09:28:21.414606 LPDDR4 DRAM CONFIGURATION
3955 09:28:21.418321 ===================================
3956 09:28:21.421090 EX_ROW_EN[0] = 0x0
3957 09:28:21.421196 EX_ROW_EN[1] = 0x0
3958 09:28:21.424512 LP4Y_EN = 0x0
3959 09:28:21.428138 WORK_FSP = 0x0
3960 09:28:21.428237 WL = 0x2
3961 09:28:21.431143 RL = 0x2
3962 09:28:21.431215 BL = 0x2
3963 09:28:21.434822 RPST = 0x0
3964 09:28:21.434902 RD_PRE = 0x0
3965 09:28:21.437464 WR_PRE = 0x1
3966 09:28:21.437544 WR_PST = 0x0
3967 09:28:21.441057 DBI_WR = 0x0
3968 09:28:21.441137 DBI_RD = 0x0
3969 09:28:21.444545 OTF = 0x1
3970 09:28:21.447644 ===================================
3971 09:28:21.450768 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3972 09:28:21.454143 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3973 09:28:21.460811 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3974 09:28:21.464282 ===================================
3975 09:28:21.464362 LPDDR4 DRAM CONFIGURATION
3976 09:28:21.467340 ===================================
3977 09:28:21.470388 EX_ROW_EN[0] = 0x10
3978 09:28:21.474146 EX_ROW_EN[1] = 0x0
3979 09:28:21.474264 LP4Y_EN = 0x0
3980 09:28:21.477235 WORK_FSP = 0x0
3981 09:28:21.477315 WL = 0x2
3982 09:28:21.480564 RL = 0x2
3983 09:28:21.480644 BL = 0x2
3984 09:28:21.483934 RPST = 0x0
3985 09:28:21.484014 RD_PRE = 0x0
3986 09:28:21.486927 WR_PRE = 0x1
3987 09:28:21.487007 WR_PST = 0x0
3988 09:28:21.490464 DBI_WR = 0x0
3989 09:28:21.490544 DBI_RD = 0x0
3990 09:28:21.493445 OTF = 0x1
3991 09:28:21.497229 ===================================
3992 09:28:21.503231 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3993 09:28:21.506969 nWR fixed to 30
3994 09:28:21.509789 [ModeRegInit_LP4] CH0 RK0
3995 09:28:21.509888 [ModeRegInit_LP4] CH0 RK1
3996 09:28:21.513107 [ModeRegInit_LP4] CH1 RK0
3997 09:28:21.516611 [ModeRegInit_LP4] CH1 RK1
3998 09:28:21.516719 match AC timing 17
3999 09:28:21.523326 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4000 09:28:21.526477 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4001 09:28:21.529750 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4002 09:28:21.536536 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4003 09:28:21.539921 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4004 09:28:21.540005 ==
4005 09:28:21.543179 Dram Type= 6, Freq= 0, CH_0, rank 0
4006 09:28:21.546140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4007 09:28:21.546260 ==
4008 09:28:21.552611 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4009 09:28:21.559241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4010 09:28:21.562893 [CA 0] Center 36 (6~66) winsize 61
4011 09:28:21.565927 [CA 1] Center 36 (6~66) winsize 61
4012 09:28:21.569557 [CA 2] Center 34 (3~65) winsize 63
4013 09:28:21.572657 [CA 3] Center 34 (4~65) winsize 62
4014 09:28:21.576335 [CA 4] Center 33 (3~64) winsize 62
4015 09:28:21.579394 [CA 5] Center 33 (3~64) winsize 62
4016 09:28:21.579501
4017 09:28:21.582456 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4018 09:28:21.582561
4019 09:28:21.586068 [CATrainingPosCal] consider 1 rank data
4020 09:28:21.589514 u2DelayCellTimex100 = 270/100 ps
4021 09:28:21.592944 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4022 09:28:21.595657 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4023 09:28:21.599184 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4024 09:28:21.602350 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4025 09:28:21.605925 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4026 09:28:21.612578 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4027 09:28:21.612675
4028 09:28:21.615572 CA PerBit enable=1, Macro0, CA PI delay=33
4029 09:28:21.615653
4030 09:28:21.619228 [CBTSetCACLKResult] CA Dly = 33
4031 09:28:21.619334 CS Dly: 6 (0~37)
4032 09:28:21.619428 ==
4033 09:28:21.622247 Dram Type= 6, Freq= 0, CH_0, rank 1
4034 09:28:21.625240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4035 09:28:21.628983 ==
4036 09:28:21.631988 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4037 09:28:21.638621 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4038 09:28:21.642047 [CA 0] Center 36 (6~66) winsize 61
4039 09:28:21.645081 [CA 1] Center 36 (6~66) winsize 61
4040 09:28:21.648454 [CA 2] Center 33 (3~64) winsize 62
4041 09:28:21.651707 [CA 3] Center 33 (3~64) winsize 62
4042 09:28:21.654933 [CA 4] Center 33 (3~64) winsize 62
4043 09:28:21.658440 [CA 5] Center 33 (2~64) winsize 63
4044 09:28:21.658542
4045 09:28:21.662018 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4046 09:28:21.662132
4047 09:28:21.665025 [CATrainingPosCal] consider 2 rank data
4048 09:28:21.668110 u2DelayCellTimex100 = 270/100 ps
4049 09:28:21.671710 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4050 09:28:21.678307 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4051 09:28:21.681386 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4052 09:28:21.684521 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4053 09:28:21.688343 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4054 09:28:21.691348 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4055 09:28:21.691444
4056 09:28:21.694275 CA PerBit enable=1, Macro0, CA PI delay=33
4057 09:28:21.694350
4058 09:28:21.697675 [CBTSetCACLKResult] CA Dly = 33
4059 09:28:21.701068 CS Dly: 6 (0~37)
4060 09:28:21.701168
4061 09:28:21.704234 ----->DramcWriteLeveling(PI) begin...
4062 09:28:21.704357 ==
4063 09:28:21.707582 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 09:28:21.711216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 09:28:21.711312 ==
4066 09:28:21.714118 Write leveling (Byte 0): 33 => 33
4067 09:28:21.717671 Write leveling (Byte 1): 32 => 32
4068 09:28:21.721380 DramcWriteLeveling(PI) end<-----
4069 09:28:21.721487
4070 09:28:21.721576 ==
4071 09:28:21.724476 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 09:28:21.727554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 09:28:21.727671 ==
4074 09:28:21.730601 [Gating] SW mode calibration
4075 09:28:21.737364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4076 09:28:21.744197 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4077 09:28:21.747558 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4078 09:28:21.750529 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4079 09:28:21.757300 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4080 09:28:21.760614 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4081 09:28:21.763730 0 9 16 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
4082 09:28:21.770332 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4083 09:28:21.773623 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4084 09:28:21.777261 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4085 09:28:21.783855 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4086 09:28:21.786884 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4087 09:28:21.790030 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4088 09:28:21.796675 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4089 09:28:21.800389 0 10 16 | B1->B0 | 3434 4141 | 0 0 | (0 0) (0 0)
4090 09:28:21.803544 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4091 09:28:21.809952 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 09:28:21.813211 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 09:28:21.816442 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 09:28:21.823144 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4095 09:28:21.826552 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4096 09:28:21.829586 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4097 09:28:21.836344 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4098 09:28:21.839328 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 09:28:21.843011 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 09:28:21.849707 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 09:28:21.852725 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4102 09:28:21.855764 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4103 09:28:21.862548 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4104 09:28:21.865991 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4105 09:28:21.869021 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4106 09:28:21.875911 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4107 09:28:21.878873 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4108 09:28:21.882301 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4109 09:28:21.889144 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 09:28:21.892082 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 09:28:21.895741 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 09:28:21.902297 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 09:28:21.905226 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4114 09:28:21.908894 Total UI for P1: 0, mck2ui 16
4115 09:28:21.912136 best dqsien dly found for B0: ( 0, 13, 14)
4116 09:28:21.915104 Total UI for P1: 0, mck2ui 16
4117 09:28:21.918550 best dqsien dly found for B1: ( 0, 13, 14)
4118 09:28:21.921812 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4119 09:28:21.925112 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4120 09:28:21.925209
4121 09:28:21.928792 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4122 09:28:21.935283 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4123 09:28:21.935364 [Gating] SW calibration Done
4124 09:28:21.935427 ==
4125 09:28:21.938394 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 09:28:21.945138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 09:28:21.945219 ==
4128 09:28:21.945287 RX Vref Scan: 0
4129 09:28:21.945346
4130 09:28:21.948092 RX Vref 0 -> 0, step: 1
4131 09:28:21.948172
4132 09:28:21.951538 RX Delay -230 -> 252, step: 16
4133 09:28:21.954720 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4134 09:28:21.958399 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4135 09:28:21.964947 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4136 09:28:21.968130 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4137 09:28:21.971205 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4138 09:28:21.974978 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4139 09:28:21.978044 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4140 09:28:21.984758 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4141 09:28:21.988110 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4142 09:28:21.991579 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4143 09:28:21.994920 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4144 09:28:22.001119 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4145 09:28:22.004231 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4146 09:28:22.007647 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4147 09:28:22.011230 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4148 09:28:22.017407 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4149 09:28:22.017505 ==
4150 09:28:22.021276 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 09:28:22.024110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 09:28:22.024191 ==
4153 09:28:22.024254 DQS Delay:
4154 09:28:22.027748 DQS0 = 0, DQS1 = 0
4155 09:28:22.027828 DQM Delay:
4156 09:28:22.031200 DQM0 = 43, DQM1 = 33
4157 09:28:22.031279 DQ Delay:
4158 09:28:22.034208 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4159 09:28:22.037657 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4160 09:28:22.040832 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4161 09:28:22.044331 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4162 09:28:22.044435
4163 09:28:22.044524
4164 09:28:22.044620 ==
4165 09:28:22.047351 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 09:28:22.050997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 09:28:22.051077 ==
4168 09:28:22.053785
4169 09:28:22.053896
4170 09:28:22.053987 TX Vref Scan disable
4171 09:28:22.057238 == TX Byte 0 ==
4172 09:28:22.060726 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4173 09:28:22.063793 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4174 09:28:22.067469 == TX Byte 1 ==
4175 09:28:22.070431 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4176 09:28:22.074193 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4177 09:28:22.077215 ==
4178 09:28:22.080310 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 09:28:22.084035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 09:28:22.084107 ==
4181 09:28:22.084167
4182 09:28:22.084223
4183 09:28:22.087014 TX Vref Scan disable
4184 09:28:22.087088 == TX Byte 0 ==
4185 09:28:22.093802 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4186 09:28:22.096786 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4187 09:28:22.096883 == TX Byte 1 ==
4188 09:28:22.104052 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4189 09:28:22.106824 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4190 09:28:22.106904
4191 09:28:22.106967 [DATLAT]
4192 09:28:22.110239 Freq=600, CH0 RK0
4193 09:28:22.110319
4194 09:28:22.110381 DATLAT Default: 0x9
4195 09:28:22.113640 0, 0xFFFF, sum = 0
4196 09:28:22.113721 1, 0xFFFF, sum = 0
4197 09:28:22.117169 2, 0xFFFF, sum = 0
4198 09:28:22.120069 3, 0xFFFF, sum = 0
4199 09:28:22.120150 4, 0xFFFF, sum = 0
4200 09:28:22.123735 5, 0xFFFF, sum = 0
4201 09:28:22.123817 6, 0xFFFF, sum = 0
4202 09:28:22.126808 7, 0xFFFF, sum = 0
4203 09:28:22.126902 8, 0x0, sum = 1
4204 09:28:22.126966 9, 0x0, sum = 2
4205 09:28:22.129799 10, 0x0, sum = 3
4206 09:28:22.129880 11, 0x0, sum = 4
4207 09:28:22.133516 best_step = 9
4208 09:28:22.133595
4209 09:28:22.133657 ==
4210 09:28:22.136433 Dram Type= 6, Freq= 0, CH_0, rank 0
4211 09:28:22.140156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4212 09:28:22.140237 ==
4213 09:28:22.143750 RX Vref Scan: 1
4214 09:28:22.143829
4215 09:28:22.143892 RX Vref 0 -> 0, step: 1
4216 09:28:22.143949
4217 09:28:22.146473 RX Delay -195 -> 252, step: 8
4218 09:28:22.146553
4219 09:28:22.149702 Set Vref, RX VrefLevel [Byte0]: 60
4220 09:28:22.152911 [Byte1]: 58
4221 09:28:22.157366
4222 09:28:22.157459 Final RX Vref Byte 0 = 60 to rank0
4223 09:28:22.161072 Final RX Vref Byte 1 = 58 to rank0
4224 09:28:22.164253 Final RX Vref Byte 0 = 60 to rank1
4225 09:28:22.167185 Final RX Vref Byte 1 = 58 to rank1==
4226 09:28:22.170772 Dram Type= 6, Freq= 0, CH_0, rank 0
4227 09:28:22.177587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 09:28:22.177668 ==
4229 09:28:22.177730 DQS Delay:
4230 09:28:22.180538 DQS0 = 0, DQS1 = 0
4231 09:28:22.180618 DQM Delay:
4232 09:28:22.180680 DQM0 = 43, DQM1 = 32
4233 09:28:22.184252 DQ Delay:
4234 09:28:22.187484 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4235 09:28:22.190350 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4236 09:28:22.193949 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4237 09:28:22.197005 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4238 09:28:22.197084
4239 09:28:22.197147
4240 09:28:22.203815 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a42, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 389 ps
4241 09:28:22.207121 CH0 RK0: MR19=808, MR18=6A42
4242 09:28:22.213561 CH0_RK0: MR19=0x808, MR18=0x6A42, DQSOSC=389, MR23=63, INC=173, DEC=115
4243 09:28:22.213641
4244 09:28:22.216577 ----->DramcWriteLeveling(PI) begin...
4245 09:28:22.216684 ==
4246 09:28:22.219927 Dram Type= 6, Freq= 0, CH_0, rank 1
4247 09:28:22.223300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4248 09:28:22.223380 ==
4249 09:28:22.226619 Write leveling (Byte 0): 34 => 34
4250 09:28:22.230000 Write leveling (Byte 1): 31 => 31
4251 09:28:22.233438 DramcWriteLeveling(PI) end<-----
4252 09:28:22.233519
4253 09:28:22.233581 ==
4254 09:28:22.236559 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 09:28:22.243174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 09:28:22.243257 ==
4257 09:28:22.243321 [Gating] SW mode calibration
4258 09:28:22.252946 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4259 09:28:22.256271 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4260 09:28:22.259543 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4261 09:28:22.265910 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4262 09:28:22.269674 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4263 09:28:22.272585 0 9 12 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
4264 09:28:22.279305 0 9 16 | B1->B0 | 2e2e 2828 | 1 1 | (1 0) (1 0)
4265 09:28:22.282411 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4266 09:28:22.286079 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4267 09:28:22.292249 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4268 09:28:22.295824 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4269 09:28:22.298804 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4270 09:28:22.305544 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4271 09:28:22.308738 0 10 12 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
4272 09:28:22.312222 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
4273 09:28:22.318477 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4274 09:28:22.322281 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 09:28:22.328497 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4276 09:28:22.332194 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4277 09:28:22.334969 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 09:28:22.341941 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4279 09:28:22.345137 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4280 09:28:22.348587 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 09:28:22.351673 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 09:28:22.358487 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 09:28:22.361415 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 09:28:22.364699 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 09:28:22.371264 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4286 09:28:22.374819 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4287 09:28:22.377854 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4288 09:28:22.384716 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4289 09:28:22.388182 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4290 09:28:22.391500 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4291 09:28:22.398128 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4292 09:28:22.401145 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4293 09:28:22.404927 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 09:28:22.411042 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 09:28:22.414269 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4296 09:28:22.420704 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4297 09:28:22.420785 Total UI for P1: 0, mck2ui 16
4298 09:28:22.423972 best dqsien dly found for B0: ( 0, 13, 12)
4299 09:28:22.431158 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4300 09:28:22.434201 Total UI for P1: 0, mck2ui 16
4301 09:28:22.437324 best dqsien dly found for B1: ( 0, 13, 16)
4302 09:28:22.441124 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4303 09:28:22.443964 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4304 09:28:22.444045
4305 09:28:22.447302 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4306 09:28:22.450774 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4307 09:28:22.453575 [Gating] SW calibration Done
4308 09:28:22.453656 ==
4309 09:28:22.456911 Dram Type= 6, Freq= 0, CH_0, rank 1
4310 09:28:22.460277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4311 09:28:22.463926 ==
4312 09:28:22.464007 RX Vref Scan: 0
4313 09:28:22.464070
4314 09:28:22.466827 RX Vref 0 -> 0, step: 1
4315 09:28:22.466908
4316 09:28:22.469844 RX Delay -230 -> 252, step: 16
4317 09:28:22.473393 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4318 09:28:22.476398 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4319 09:28:22.480161 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4320 09:28:22.486494 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4321 09:28:22.489938 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4322 09:28:22.493410 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4323 09:28:22.496159 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4324 09:28:22.503211 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4325 09:28:22.506111 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4326 09:28:22.509802 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4327 09:28:22.512798 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4328 09:28:22.516583 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4329 09:28:22.522753 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4330 09:28:22.526287 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4331 09:28:22.529229 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4332 09:28:22.536152 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4333 09:28:22.536255 ==
4334 09:28:22.539021 Dram Type= 6, Freq= 0, CH_0, rank 1
4335 09:28:22.542781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 09:28:22.542861 ==
4337 09:28:22.542924 DQS Delay:
4338 09:28:22.545753 DQS0 = 0, DQS1 = 0
4339 09:28:22.545832 DQM Delay:
4340 09:28:22.548830 DQM0 = 44, DQM1 = 39
4341 09:28:22.548909 DQ Delay:
4342 09:28:22.552208 DQ0 =41, DQ1 =57, DQ2 =33, DQ3 =33
4343 09:28:22.555897 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4344 09:28:22.558871 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4345 09:28:22.562539 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4346 09:28:22.562619
4347 09:28:22.562681
4348 09:28:22.562739 ==
4349 09:28:22.565276 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 09:28:22.568918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 09:28:22.568998 ==
4352 09:28:22.572138
4353 09:28:22.572232
4354 09:28:22.572293 TX Vref Scan disable
4355 09:28:22.575305 == TX Byte 0 ==
4356 09:28:22.578640 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4357 09:28:22.581860 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4358 09:28:22.585720 == TX Byte 1 ==
4359 09:28:22.588577 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4360 09:28:22.591867 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4361 09:28:22.594880 ==
4362 09:28:22.598536 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 09:28:22.601682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 09:28:22.601762 ==
4365 09:28:22.601824
4366 09:28:22.601880
4367 09:28:22.604580 TX Vref Scan disable
4368 09:28:22.604659 == TX Byte 0 ==
4369 09:28:22.611416 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4370 09:28:22.614622 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4371 09:28:22.617897 == TX Byte 1 ==
4372 09:28:22.621582 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4373 09:28:22.624764 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4374 09:28:22.624844
4375 09:28:22.624905 [DATLAT]
4376 09:28:22.627769 Freq=600, CH0 RK1
4377 09:28:22.627849
4378 09:28:22.631538 DATLAT Default: 0x9
4379 09:28:22.631616 0, 0xFFFF, sum = 0
4380 09:28:22.634494 1, 0xFFFF, sum = 0
4381 09:28:22.634574 2, 0xFFFF, sum = 0
4382 09:28:22.637550 3, 0xFFFF, sum = 0
4383 09:28:22.637633 4, 0xFFFF, sum = 0
4384 09:28:22.640933 5, 0xFFFF, sum = 0
4385 09:28:22.641042 6, 0xFFFF, sum = 0
4386 09:28:22.644279 7, 0xFFFF, sum = 0
4387 09:28:22.644415 8, 0x0, sum = 1
4388 09:28:22.647871 9, 0x0, sum = 2
4389 09:28:22.647969 10, 0x0, sum = 3
4390 09:28:22.651229 11, 0x0, sum = 4
4391 09:28:22.651324 best_step = 9
4392 09:28:22.651408
4393 09:28:22.651490 ==
4394 09:28:22.654074 Dram Type= 6, Freq= 0, CH_0, rank 1
4395 09:28:22.657580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 09:28:22.657673 ==
4397 09:28:22.660630 RX Vref Scan: 0
4398 09:28:22.660720
4399 09:28:22.663740 RX Vref 0 -> 0, step: 1
4400 09:28:22.663838
4401 09:28:22.663928 RX Delay -195 -> 252, step: 8
4402 09:28:22.672307 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4403 09:28:22.675205 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4404 09:28:22.678527 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4405 09:28:22.681744 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4406 09:28:22.688560 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4407 09:28:22.691739 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4408 09:28:22.694665 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4409 09:28:22.698082 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4410 09:28:22.704851 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4411 09:28:22.707904 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4412 09:28:22.711494 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4413 09:28:22.714549 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4414 09:28:22.721518 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4415 09:28:22.724688 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4416 09:28:22.727703 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4417 09:28:22.730998 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4418 09:28:22.731093 ==
4419 09:28:22.734615 Dram Type= 6, Freq= 0, CH_0, rank 1
4420 09:28:22.741317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4421 09:28:22.741437 ==
4422 09:28:22.741557 DQS Delay:
4423 09:28:22.744430 DQS0 = 0, DQS1 = 0
4424 09:28:22.744543 DQM Delay:
4425 09:28:22.744662 DQM0 = 41, DQM1 = 35
4426 09:28:22.747911 DQ Delay:
4427 09:28:22.751304 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4428 09:28:22.754251 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =52
4429 09:28:22.757761 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4430 09:28:22.761367 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4431 09:28:22.761460
4432 09:28:22.761546
4433 09:28:22.767570 [DQSOSCAuto] RK1, (LSB)MR18= 0x6518, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 390 ps
4434 09:28:22.770668 CH0 RK1: MR19=808, MR18=6518
4435 09:28:22.777457 CH0_RK1: MR19=0x808, MR18=0x6518, DQSOSC=390, MR23=63, INC=172, DEC=114
4436 09:28:22.780549 [RxdqsGatingPostProcess] freq 600
4437 09:28:22.784297 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4438 09:28:22.787182 Pre-setting of DQS Precalculation
4439 09:28:22.793915 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4440 09:28:22.794013 ==
4441 09:28:22.797155 Dram Type= 6, Freq= 0, CH_1, rank 0
4442 09:28:22.800744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4443 09:28:22.800847 ==
4444 09:28:22.807700 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4445 09:28:22.813849 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4446 09:28:22.817219 [CA 0] Center 35 (5~66) winsize 62
4447 09:28:22.820435 [CA 1] Center 36 (6~66) winsize 61
4448 09:28:22.824063 [CA 2] Center 34 (4~65) winsize 62
4449 09:28:22.827232 [CA 3] Center 33 (3~64) winsize 62
4450 09:28:22.830043 [CA 4] Center 34 (4~65) winsize 62
4451 09:28:22.833502 [CA 5] Center 33 (3~64) winsize 62
4452 09:28:22.833584
4453 09:28:22.837181 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4454 09:28:22.837262
4455 09:28:22.840462 [CATrainingPosCal] consider 1 rank data
4456 09:28:22.843595 u2DelayCellTimex100 = 270/100 ps
4457 09:28:22.846655 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4458 09:28:22.850373 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4459 09:28:22.853470 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4460 09:28:22.856985 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4461 09:28:22.860197 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4462 09:28:22.863269 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4463 09:28:22.866882
4464 09:28:22.870079 CA PerBit enable=1, Macro0, CA PI delay=33
4465 09:28:22.870203
4466 09:28:22.873083 [CBTSetCACLKResult] CA Dly = 33
4467 09:28:22.873180 CS Dly: 4 (0~35)
4468 09:28:22.873245 ==
4469 09:28:22.876532 Dram Type= 6, Freq= 0, CH_1, rank 1
4470 09:28:22.879708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 09:28:22.879813 ==
4472 09:28:22.886394 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4473 09:28:22.893142 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4474 09:28:22.896405 [CA 0] Center 35 (5~66) winsize 62
4475 09:28:22.899357 [CA 1] Center 36 (6~66) winsize 61
4476 09:28:22.902956 [CA 2] Center 34 (4~65) winsize 62
4477 09:28:22.906029 [CA 3] Center 34 (4~65) winsize 62
4478 09:28:22.909565 [CA 4] Center 34 (3~65) winsize 63
4479 09:28:22.913058 [CA 5] Center 34 (3~65) winsize 63
4480 09:28:22.913137
4481 09:28:22.916056 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4482 09:28:22.916136
4483 09:28:22.919288 [CATrainingPosCal] consider 2 rank data
4484 09:28:22.922530 u2DelayCellTimex100 = 270/100 ps
4485 09:28:22.925917 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4486 09:28:22.928923 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4487 09:28:22.935657 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4488 09:28:22.938735 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4489 09:28:22.942376 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4490 09:28:22.945659 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4491 09:28:22.945736
4492 09:28:22.948689 CA PerBit enable=1, Macro0, CA PI delay=33
4493 09:28:22.948760
4494 09:28:22.951960 [CBTSetCACLKResult] CA Dly = 33
4495 09:28:22.952035 CS Dly: 5 (0~37)
4496 09:28:22.952095
4497 09:28:22.955600 ----->DramcWriteLeveling(PI) begin...
4498 09:28:22.958733 ==
4499 09:28:22.961726 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 09:28:22.965258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 09:28:22.965339 ==
4502 09:28:22.968821 Write leveling (Byte 0): 30 => 30
4503 09:28:22.971977 Write leveling (Byte 1): 29 => 29
4504 09:28:22.975524 DramcWriteLeveling(PI) end<-----
4505 09:28:22.975604
4506 09:28:22.975666 ==
4507 09:28:22.978502 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 09:28:22.981526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 09:28:22.981614 ==
4510 09:28:22.984786 [Gating] SW mode calibration
4511 09:28:22.991421 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4512 09:28:22.998178 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4513 09:28:23.001850 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4514 09:28:23.004774 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4515 09:28:23.011131 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4516 09:28:23.014845 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4517 09:28:23.017916 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4518 09:28:23.024549 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4519 09:28:23.027574 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4520 09:28:23.030612 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4521 09:28:23.037802 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4522 09:28:23.040631 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4523 09:28:23.044194 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4524 09:28:23.050582 0 10 12 | B1->B0 | 3030 3737 | 0 0 | (0 0) (0 0)
4525 09:28:23.054307 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4526 09:28:23.057554 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 09:28:23.064045 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4528 09:28:23.067416 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4529 09:28:23.070671 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 09:28:23.077223 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4531 09:28:23.080539 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4532 09:28:23.083891 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4533 09:28:23.090403 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 09:28:23.093406 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 09:28:23.097067 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 09:28:23.103619 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4537 09:28:23.106612 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4538 09:28:23.110052 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4539 09:28:23.116890 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4540 09:28:23.120110 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4541 09:28:23.123203 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4542 09:28:23.129850 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4543 09:28:23.132998 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4544 09:28:23.136666 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4545 09:28:23.143243 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 09:28:23.146362 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 09:28:23.149903 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 09:28:23.156511 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4549 09:28:23.159544 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4550 09:28:23.163126 Total UI for P1: 0, mck2ui 16
4551 09:28:23.165954 best dqsien dly found for B0: ( 0, 13, 12)
4552 09:28:23.169171 Total UI for P1: 0, mck2ui 16
4553 09:28:23.172626 best dqsien dly found for B1: ( 0, 13, 12)
4554 09:28:23.175905 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4555 09:28:23.179182 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4556 09:28:23.179263
4557 09:28:23.182350 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4558 09:28:23.189157 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4559 09:28:23.189237 [Gating] SW calibration Done
4560 09:28:23.189300 ==
4561 09:28:23.192327 Dram Type= 6, Freq= 0, CH_1, rank 0
4562 09:28:23.199278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4563 09:28:23.199359 ==
4564 09:28:23.199421 RX Vref Scan: 0
4565 09:28:23.199480
4566 09:28:23.202270 RX Vref 0 -> 0, step: 1
4567 09:28:23.202379
4568 09:28:23.205919 RX Delay -230 -> 252, step: 16
4569 09:28:23.208883 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4570 09:28:23.212560 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4571 09:28:23.218724 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4572 09:28:23.222457 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4573 09:28:23.225495 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4574 09:28:23.228515 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4575 09:28:23.232181 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4576 09:28:23.239003 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4577 09:28:23.242006 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4578 09:28:23.244973 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4579 09:28:23.248251 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4580 09:28:23.255317 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4581 09:28:23.258435 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4582 09:28:23.261498 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4583 09:28:23.265224 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4584 09:28:23.271576 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4585 09:28:23.271657 ==
4586 09:28:23.274864 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 09:28:23.278373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 09:28:23.278454 ==
4589 09:28:23.278517 DQS Delay:
4590 09:28:23.281565 DQS0 = 0, DQS1 = 0
4591 09:28:23.281646 DQM Delay:
4592 09:28:23.284571 DQM0 = 47, DQM1 = 40
4593 09:28:23.284650 DQ Delay:
4594 09:28:23.288156 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4595 09:28:23.291392 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4596 09:28:23.294464 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =25
4597 09:28:23.298024 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4598 09:28:23.298129
4599 09:28:23.298267
4600 09:28:23.298354 ==
4601 09:28:23.301024 Dram Type= 6, Freq= 0, CH_1, rank 0
4602 09:28:23.304339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 09:28:23.308138 ==
4604 09:28:23.308239
4605 09:28:23.308336
4606 09:28:23.308422 TX Vref Scan disable
4607 09:28:23.311121 == TX Byte 0 ==
4608 09:28:23.314412 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4609 09:28:23.317694 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4610 09:28:23.321378 == TX Byte 1 ==
4611 09:28:23.324486 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4612 09:28:23.327513 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4613 09:28:23.331190 ==
4614 09:28:23.334390 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 09:28:23.338049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 09:28:23.338147 ==
4617 09:28:23.338251
4618 09:28:23.338319
4619 09:28:23.341004 TX Vref Scan disable
4620 09:28:23.341097 == TX Byte 0 ==
4621 09:28:23.347862 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4622 09:28:23.350958 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4623 09:28:23.351032 == TX Byte 1 ==
4624 09:28:23.357419 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4625 09:28:23.360586 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4626 09:28:23.360667
4627 09:28:23.360729 [DATLAT]
4628 09:28:23.364079 Freq=600, CH1 RK0
4629 09:28:23.364159
4630 09:28:23.364221 DATLAT Default: 0x9
4631 09:28:23.367112 0, 0xFFFF, sum = 0
4632 09:28:23.367193 1, 0xFFFF, sum = 0
4633 09:28:23.370801 2, 0xFFFF, sum = 0
4634 09:28:23.373784 3, 0xFFFF, sum = 0
4635 09:28:23.373865 4, 0xFFFF, sum = 0
4636 09:28:23.377306 5, 0xFFFF, sum = 0
4637 09:28:23.377387 6, 0xFFFF, sum = 0
4638 09:28:23.380666 7, 0xFFFF, sum = 0
4639 09:28:23.380748 8, 0x0, sum = 1
4640 09:28:23.383772 9, 0x0, sum = 2
4641 09:28:23.383855 10, 0x0, sum = 3
4642 09:28:23.383920 11, 0x0, sum = 4
4643 09:28:23.387294 best_step = 9
4644 09:28:23.387375
4645 09:28:23.387438 ==
4646 09:28:23.390361 Dram Type= 6, Freq= 0, CH_1, rank 0
4647 09:28:23.393827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 09:28:23.393912 ==
4649 09:28:23.396967 RX Vref Scan: 1
4650 09:28:23.397066
4651 09:28:23.400474 RX Vref 0 -> 0, step: 1
4652 09:28:23.400554
4653 09:28:23.400617 RX Delay -179 -> 252, step: 8
4654 09:28:23.400677
4655 09:28:23.403698 Set Vref, RX VrefLevel [Byte0]: 48
4656 09:28:23.406889 [Byte1]: 54
4657 09:28:23.411548
4658 09:28:23.411630 Final RX Vref Byte 0 = 48 to rank0
4659 09:28:23.414495 Final RX Vref Byte 1 = 54 to rank0
4660 09:28:23.418117 Final RX Vref Byte 0 = 48 to rank1
4661 09:28:23.421282 Final RX Vref Byte 1 = 54 to rank1==
4662 09:28:23.424238 Dram Type= 6, Freq= 0, CH_1, rank 0
4663 09:28:23.431087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 09:28:23.431183 ==
4665 09:28:23.431267 DQS Delay:
4666 09:28:23.434484 DQS0 = 0, DQS1 = 0
4667 09:28:23.434574 DQM Delay:
4668 09:28:23.434639 DQM0 = 46, DQM1 = 38
4669 09:28:23.438067 DQ Delay:
4670 09:28:23.440956 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4671 09:28:23.444208 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4672 09:28:23.447802 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4673 09:28:23.450796 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4674 09:28:23.450876
4675 09:28:23.450938
4676 09:28:23.457668 [DQSOSCAuto] RK0, (LSB)MR18= 0x5236, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 394 ps
4677 09:28:23.460510 CH1 RK0: MR19=808, MR18=5236
4678 09:28:23.467317 CH1_RK0: MR19=0x808, MR18=0x5236, DQSOSC=394, MR23=63, INC=168, DEC=112
4679 09:28:23.467398
4680 09:28:23.470963 ----->DramcWriteLeveling(PI) begin...
4681 09:28:23.471049 ==
4682 09:28:23.474057 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 09:28:23.477329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 09:28:23.477409 ==
4685 09:28:23.480282 Write leveling (Byte 0): 29 => 29
4686 09:28:23.483725 Write leveling (Byte 1): 29 => 29
4687 09:28:23.487102 DramcWriteLeveling(PI) end<-----
4688 09:28:23.487211
4689 09:28:23.487277 ==
4690 09:28:23.491050 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 09:28:23.493704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 09:28:23.497124 ==
4693 09:28:23.497206 [Gating] SW mode calibration
4694 09:28:23.507132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4695 09:28:23.510063 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4696 09:28:23.513783 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4697 09:28:23.519938 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4698 09:28:23.523444 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4699 09:28:23.527190 0 9 12 | B1->B0 | 2e2e 3333 | 0 0 | (1 1) (0 1)
4700 09:28:23.533416 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4701 09:28:23.536848 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4702 09:28:23.540279 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4703 09:28:23.546675 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4704 09:28:23.549819 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4705 09:28:23.552885 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4706 09:28:23.559769 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4707 09:28:23.563087 0 10 12 | B1->B0 | 3232 2a2a | 0 0 | (0 0) (0 0)
4708 09:28:23.566141 0 10 16 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
4709 09:28:23.573032 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 09:28:23.576018 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4711 09:28:23.579782 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4712 09:28:23.586011 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 09:28:23.589608 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4714 09:28:23.592385 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 09:28:23.599364 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4716 09:28:23.602723 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 09:28:23.605575 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 09:28:23.612260 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 09:28:23.615370 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4720 09:28:23.619030 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4721 09:28:23.625399 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4722 09:28:23.628604 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4723 09:28:23.632252 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4724 09:28:23.638787 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4725 09:28:23.642386 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4726 09:28:23.645133 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4727 09:28:23.652022 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4728 09:28:23.655077 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 09:28:23.658489 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 09:28:23.665111 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 09:28:23.668198 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4732 09:28:23.671868 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4733 09:28:23.675047 Total UI for P1: 0, mck2ui 16
4734 09:28:23.678596 best dqsien dly found for B0: ( 0, 13, 12)
4735 09:28:23.681741 Total UI for P1: 0, mck2ui 16
4736 09:28:23.684819 best dqsien dly found for B1: ( 0, 13, 12)
4737 09:28:23.688468 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4738 09:28:23.691544 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4739 09:28:23.691639
4740 09:28:23.698218 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4741 09:28:23.701586 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4742 09:28:23.704958 [Gating] SW calibration Done
4743 09:28:23.705056 ==
4744 09:28:23.708052 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 09:28:23.711441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 09:28:23.711536 ==
4747 09:28:23.711620 RX Vref Scan: 0
4748 09:28:23.711705
4749 09:28:23.714672 RX Vref 0 -> 0, step: 1
4750 09:28:23.714791
4751 09:28:23.717860 RX Delay -230 -> 252, step: 16
4752 09:28:23.721499 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4753 09:28:23.728163 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4754 09:28:23.731281 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4755 09:28:23.734529 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4756 09:28:23.737750 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4757 09:28:23.741079 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4758 09:28:23.747556 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4759 09:28:23.750801 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4760 09:28:23.754573 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4761 09:28:23.758033 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4762 09:28:23.764431 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4763 09:28:23.767291 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4764 09:28:23.770785 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4765 09:28:23.774373 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4766 09:28:23.780977 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4767 09:28:23.784116 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4768 09:28:23.784198 ==
4769 09:28:23.787147 Dram Type= 6, Freq= 0, CH_1, rank 1
4770 09:28:23.791027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4771 09:28:23.791108 ==
4772 09:28:23.794030 DQS Delay:
4773 09:28:23.794135 DQS0 = 0, DQS1 = 0
4774 09:28:23.794258 DQM Delay:
4775 09:28:23.797022 DQM0 = 42, DQM1 = 40
4776 09:28:23.797094 DQ Delay:
4777 09:28:23.800694 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4778 09:28:23.803733 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4779 09:28:23.807423 DQ8 =25, DQ9 =33, DQ10 =33, DQ11 =33
4780 09:28:23.810589 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4781 09:28:23.810664
4782 09:28:23.810726
4783 09:28:23.810790 ==
4784 09:28:23.813739 Dram Type= 6, Freq= 0, CH_1, rank 1
4785 09:28:23.820173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4786 09:28:23.820251 ==
4787 09:28:23.820320
4788 09:28:23.820384
4789 09:28:23.820441 TX Vref Scan disable
4790 09:28:23.824029 == TX Byte 0 ==
4791 09:28:23.827834 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4792 09:28:23.834405 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4793 09:28:23.834487 == TX Byte 1 ==
4794 09:28:23.837315 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4795 09:28:23.844036 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4796 09:28:23.844117 ==
4797 09:28:23.847497 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 09:28:23.850693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 09:28:23.850775 ==
4800 09:28:23.850838
4801 09:28:23.850896
4802 09:28:23.853546 TX Vref Scan disable
4803 09:28:23.857038 == TX Byte 0 ==
4804 09:28:23.860370 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4805 09:28:23.863714 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4806 09:28:23.867024 == TX Byte 1 ==
4807 09:28:23.870145 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4808 09:28:23.873431 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4809 09:28:23.873503
4810 09:28:23.873569 [DATLAT]
4811 09:28:23.876648 Freq=600, CH1 RK1
4812 09:28:23.876719
4813 09:28:23.880051 DATLAT Default: 0x9
4814 09:28:23.880127 0, 0xFFFF, sum = 0
4815 09:28:23.883639 1, 0xFFFF, sum = 0
4816 09:28:23.883716 2, 0xFFFF, sum = 0
4817 09:28:23.886775 3, 0xFFFF, sum = 0
4818 09:28:23.886849 4, 0xFFFF, sum = 0
4819 09:28:23.890426 5, 0xFFFF, sum = 0
4820 09:28:23.890497 6, 0xFFFF, sum = 0
4821 09:28:23.893565 7, 0xFFFF, sum = 0
4822 09:28:23.893722 8, 0x0, sum = 1
4823 09:28:23.896578 9, 0x0, sum = 2
4824 09:28:23.896682 10, 0x0, sum = 3
4825 09:28:23.900382 11, 0x0, sum = 4
4826 09:28:23.900464 best_step = 9
4827 09:28:23.900527
4828 09:28:23.900585 ==
4829 09:28:23.903452 Dram Type= 6, Freq= 0, CH_1, rank 1
4830 09:28:23.906574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4831 09:28:23.906656 ==
4832 09:28:23.910308 RX Vref Scan: 0
4833 09:28:23.910389
4834 09:28:23.913399 RX Vref 0 -> 0, step: 1
4835 09:28:23.913479
4836 09:28:23.913541 RX Delay -179 -> 252, step: 8
4837 09:28:23.921201 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4838 09:28:23.924824 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4839 09:28:23.927764 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4840 09:28:23.931291 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4841 09:28:23.937530 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4842 09:28:23.941108 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4843 09:28:23.944654 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4844 09:28:23.947704 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4845 09:28:23.950749 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4846 09:28:23.957505 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4847 09:28:23.961130 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4848 09:28:23.964125 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4849 09:28:23.967279 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4850 09:28:23.974042 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4851 09:28:23.977151 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4852 09:28:23.980835 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4853 09:28:23.980957 ==
4854 09:28:23.983999 Dram Type= 6, Freq= 0, CH_1, rank 1
4855 09:28:23.990447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4856 09:28:23.990528 ==
4857 09:28:23.990591 DQS Delay:
4858 09:28:23.990649 DQS0 = 0, DQS1 = 0
4859 09:28:23.993799 DQM Delay:
4860 09:28:23.993879 DQM0 = 45, DQM1 = 36
4861 09:28:23.997504 DQ Delay:
4862 09:28:24.000769 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4863 09:28:24.000850 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4864 09:28:24.003775 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4865 09:28:24.010531 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4866 09:28:24.010639
4867 09:28:24.010732
4868 09:28:24.017385 [DQSOSCAuto] RK1, (LSB)MR18= 0x3227, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4869 09:28:24.020342 CH1 RK1: MR19=808, MR18=3227
4870 09:28:24.027062 CH1_RK1: MR19=0x808, MR18=0x3227, DQSOSC=400, MR23=63, INC=163, DEC=109
4871 09:28:24.030212 [RxdqsGatingPostProcess] freq 600
4872 09:28:24.033854 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4873 09:28:24.036723 Pre-setting of DQS Precalculation
4874 09:28:24.043321 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4875 09:28:24.050082 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4876 09:28:24.056883 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4877 09:28:24.056966
4878 09:28:24.057029
4879 09:28:24.060351 [Calibration Summary] 1200 Mbps
4880 09:28:24.060433 CH 0, Rank 0
4881 09:28:24.063118 SW Impedance : PASS
4882 09:28:24.066726 DUTY Scan : NO K
4883 09:28:24.066806 ZQ Calibration : PASS
4884 09:28:24.070311 Jitter Meter : NO K
4885 09:28:24.073421 CBT Training : PASS
4886 09:28:24.073527 Write leveling : PASS
4887 09:28:24.076954 RX DQS gating : PASS
4888 09:28:24.079724 RX DQ/DQS(RDDQC) : PASS
4889 09:28:24.079806 TX DQ/DQS : PASS
4890 09:28:24.083389 RX DATLAT : PASS
4891 09:28:24.086365 RX DQ/DQS(Engine): PASS
4892 09:28:24.086437 TX OE : NO K
4893 09:28:24.086508 All Pass.
4894 09:28:24.090117
4895 09:28:24.090257 CH 0, Rank 1
4896 09:28:24.092883 SW Impedance : PASS
4897 09:28:24.092952 DUTY Scan : NO K
4898 09:28:24.096331 ZQ Calibration : PASS
4899 09:28:24.099603 Jitter Meter : NO K
4900 09:28:24.099702 CBT Training : PASS
4901 09:28:24.102812 Write leveling : PASS
4902 09:28:24.102895 RX DQS gating : PASS
4903 09:28:24.106763 RX DQ/DQS(RDDQC) : PASS
4904 09:28:24.109808 TX DQ/DQS : PASS
4905 09:28:24.109888 RX DATLAT : PASS
4906 09:28:24.112883 RX DQ/DQS(Engine): PASS
4907 09:28:24.116598 TX OE : NO K
4908 09:28:24.116676 All Pass.
4909 09:28:24.116737
4910 09:28:24.116795 CH 1, Rank 0
4911 09:28:24.119627 SW Impedance : PASS
4912 09:28:24.123207 DUTY Scan : NO K
4913 09:28:24.123285 ZQ Calibration : PASS
4914 09:28:24.126248 Jitter Meter : NO K
4915 09:28:24.129176 CBT Training : PASS
4916 09:28:24.129264 Write leveling : PASS
4917 09:28:24.132840 RX DQS gating : PASS
4918 09:28:24.135840 RX DQ/DQS(RDDQC) : PASS
4919 09:28:24.135921 TX DQ/DQS : PASS
4920 09:28:24.139469 RX DATLAT : PASS
4921 09:28:24.142566 RX DQ/DQS(Engine): PASS
4922 09:28:24.142646 TX OE : NO K
4923 09:28:24.145965 All Pass.
4924 09:28:24.146045
4925 09:28:24.146107 CH 1, Rank 1
4926 09:28:24.148946 SW Impedance : PASS
4927 09:28:24.149052 DUTY Scan : NO K
4928 09:28:24.152578 ZQ Calibration : PASS
4929 09:28:24.155826 Jitter Meter : NO K
4930 09:28:24.155961 CBT Training : PASS
4931 09:28:24.158721 Write leveling : PASS
4932 09:28:24.162072 RX DQS gating : PASS
4933 09:28:24.162153 RX DQ/DQS(RDDQC) : PASS
4934 09:28:24.165607 TX DQ/DQS : PASS
4935 09:28:24.168975 RX DATLAT : PASS
4936 09:28:24.169056 RX DQ/DQS(Engine): PASS
4937 09:28:24.172114 TX OE : NO K
4938 09:28:24.172195 All Pass.
4939 09:28:24.172258
4940 09:28:24.175767 DramC Write-DBI off
4941 09:28:24.178834 PER_BANK_REFRESH: Hybrid Mode
4942 09:28:24.178941 TX_TRACKING: ON
4943 09:28:24.189040 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4944 09:28:24.192189 [FAST_K] Save calibration result to emmc
4945 09:28:24.195276 dramc_set_vcore_voltage set vcore to 662500
4946 09:28:24.198371 Read voltage for 933, 3
4947 09:28:24.198481 Vio18 = 0
4948 09:28:24.198571 Vcore = 662500
4949 09:28:24.202045 Vdram = 0
4950 09:28:24.202125 Vddq = 0
4951 09:28:24.202228 Vmddr = 0
4952 09:28:24.208705 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4953 09:28:24.211851 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4954 09:28:24.215192 MEM_TYPE=3, freq_sel=17
4955 09:28:24.218098 sv_algorithm_assistance_LP4_1600
4956 09:28:24.221806 ============ PULL DRAM RESETB DOWN ============
4957 09:28:24.224850 ========== PULL DRAM RESETB DOWN end =========
4958 09:28:24.231254 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4959 09:28:24.234806 ===================================
4960 09:28:24.238415 LPDDR4 DRAM CONFIGURATION
4961 09:28:24.238496 ===================================
4962 09:28:24.241384 EX_ROW_EN[0] = 0x0
4963 09:28:24.244603 EX_ROW_EN[1] = 0x0
4964 09:28:24.244683 LP4Y_EN = 0x0
4965 09:28:24.248102 WORK_FSP = 0x0
4966 09:28:24.248182 WL = 0x3
4967 09:28:24.251397 RL = 0x3
4968 09:28:24.251506 BL = 0x2
4969 09:28:24.254725 RPST = 0x0
4970 09:28:24.254805 RD_PRE = 0x0
4971 09:28:24.257818 WR_PRE = 0x1
4972 09:28:24.257898 WR_PST = 0x0
4973 09:28:24.261031 DBI_WR = 0x0
4974 09:28:24.261111 DBI_RD = 0x0
4975 09:28:24.264307 OTF = 0x1
4976 09:28:24.267634 ===================================
4977 09:28:24.270988 ===================================
4978 09:28:24.271069 ANA top config
4979 09:28:24.274327 ===================================
4980 09:28:24.277946 DLL_ASYNC_EN = 0
4981 09:28:24.281015 ALL_SLAVE_EN = 1
4982 09:28:24.284056 NEW_RANK_MODE = 1
4983 09:28:24.284163 DLL_IDLE_MODE = 1
4984 09:28:24.287699 LP45_APHY_COMB_EN = 1
4985 09:28:24.290659 TX_ODT_DIS = 1
4986 09:28:24.294055 NEW_8X_MODE = 1
4987 09:28:24.297477 ===================================
4988 09:28:24.300517 ===================================
4989 09:28:24.304192 data_rate = 1866
4990 09:28:24.307325 CKR = 1
4991 09:28:24.307416 DQ_P2S_RATIO = 8
4992 09:28:24.310471 ===================================
4993 09:28:24.314091 CA_P2S_RATIO = 8
4994 09:28:24.316931 DQ_CA_OPEN = 0
4995 09:28:24.320720 DQ_SEMI_OPEN = 0
4996 09:28:24.323477 CA_SEMI_OPEN = 0
4997 09:28:24.327149 CA_FULL_RATE = 0
4998 09:28:24.327259 DQ_CKDIV4_EN = 1
4999 09:28:24.330228 CA_CKDIV4_EN = 1
5000 09:28:24.333842 CA_PREDIV_EN = 0
5001 09:28:24.337241 PH8_DLY = 0
5002 09:28:24.340288 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5003 09:28:24.343825 DQ_AAMCK_DIV = 4
5004 09:28:24.343905 CA_AAMCK_DIV = 4
5005 09:28:24.346816 CA_ADMCK_DIV = 4
5006 09:28:24.350461 DQ_TRACK_CA_EN = 0
5007 09:28:24.353617 CA_PICK = 933
5008 09:28:24.356922 CA_MCKIO = 933
5009 09:28:24.360490 MCKIO_SEMI = 0
5010 09:28:24.363539 PLL_FREQ = 3732
5011 09:28:24.366560 DQ_UI_PI_RATIO = 32
5012 09:28:24.366641 CA_UI_PI_RATIO = 0
5013 09:28:24.370183 ===================================
5014 09:28:24.373074 ===================================
5015 09:28:24.376299 memory_type:LPDDR4
5016 09:28:24.379758 GP_NUM : 10
5017 09:28:24.379839 SRAM_EN : 1
5018 09:28:24.383385 MD32_EN : 0
5019 09:28:24.386398 ===================================
5020 09:28:24.390052 [ANA_INIT] >>>>>>>>>>>>>>
5021 09:28:24.393111 <<<<<< [CONFIGURE PHASE]: ANA_TX
5022 09:28:24.396209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5023 09:28:24.399840 ===================================
5024 09:28:24.399921 data_rate = 1866,PCW = 0X8f00
5025 09:28:24.403187 ===================================
5026 09:28:24.406084 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5027 09:28:24.413380 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5028 09:28:24.419347 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5029 09:28:24.422570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5030 09:28:24.425874 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5031 09:28:24.429312 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5032 09:28:24.432446 [ANA_INIT] flow start
5033 09:28:24.436063 [ANA_INIT] PLL >>>>>>>>
5034 09:28:24.436144 [ANA_INIT] PLL <<<<<<<<
5035 09:28:24.438987 [ANA_INIT] MIDPI >>>>>>>>
5036 09:28:24.442284 [ANA_INIT] MIDPI <<<<<<<<
5037 09:28:24.442365 [ANA_INIT] DLL >>>>>>>>
5038 09:28:24.445866 [ANA_INIT] flow end
5039 09:28:24.448931 ============ LP4 DIFF to SE enter ============
5040 09:28:24.452433 ============ LP4 DIFF to SE exit ============
5041 09:28:24.455565 [ANA_INIT] <<<<<<<<<<<<<
5042 09:28:24.459066 [Flow] Enable top DCM control >>>>>
5043 09:28:24.461935 [Flow] Enable top DCM control <<<<<
5044 09:28:24.465514 Enable DLL master slave shuffle
5045 09:28:24.472178 ==============================================================
5046 09:28:24.472262 Gating Mode config
5047 09:28:24.478730 ==============================================================
5048 09:28:24.482133 Config description:
5049 09:28:24.488814 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5050 09:28:24.495283 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5051 09:28:24.501503 SELPH_MODE 0: By rank 1: By Phase
5052 09:28:24.508137 ==============================================================
5053 09:28:24.511455 GAT_TRACK_EN = 1
5054 09:28:24.511536 RX_GATING_MODE = 2
5055 09:28:24.514771 RX_GATING_TRACK_MODE = 2
5056 09:28:24.517899 SELPH_MODE = 1
5057 09:28:24.521594 PICG_EARLY_EN = 1
5058 09:28:24.524606 VALID_LAT_VALUE = 1
5059 09:28:24.531495 ==============================================================
5060 09:28:24.534751 Enter into Gating configuration >>>>
5061 09:28:24.537978 Exit from Gating configuration <<<<
5062 09:28:24.541262 Enter into DVFS_PRE_config >>>>>
5063 09:28:24.550917 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5064 09:28:24.554470 Exit from DVFS_PRE_config <<<<<
5065 09:28:24.557619 Enter into PICG configuration >>>>
5066 09:28:24.561324 Exit from PICG configuration <<<<
5067 09:28:24.564320 [RX_INPUT] configuration >>>>>
5068 09:28:24.567697 [RX_INPUT] configuration <<<<<
5069 09:28:24.571315 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5070 09:28:24.577226 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5071 09:28:24.583945 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5072 09:28:24.590600 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5073 09:28:24.597330 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5074 09:28:24.600601 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5075 09:28:24.607102 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5076 09:28:24.610695 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5077 09:28:24.613838 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5078 09:28:24.617165 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5079 09:28:24.623285 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5080 09:28:24.627124 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5081 09:28:24.630194 ===================================
5082 09:28:24.633208 LPDDR4 DRAM CONFIGURATION
5083 09:28:24.636847 ===================================
5084 09:28:24.636931 EX_ROW_EN[0] = 0x0
5085 09:28:24.640054 EX_ROW_EN[1] = 0x0
5086 09:28:24.640142 LP4Y_EN = 0x0
5087 09:28:24.643577 WORK_FSP = 0x0
5088 09:28:24.643655 WL = 0x3
5089 09:28:24.646597 RL = 0x3
5090 09:28:24.646673 BL = 0x2
5091 09:28:24.650134 RPST = 0x0
5092 09:28:24.653010 RD_PRE = 0x0
5093 09:28:24.653086 WR_PRE = 0x1
5094 09:28:24.656540 WR_PST = 0x0
5095 09:28:24.656620 DBI_WR = 0x0
5096 09:28:24.659851 DBI_RD = 0x0
5097 09:28:24.659932 OTF = 0x1
5098 09:28:24.662989 ===================================
5099 09:28:24.666330 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5100 09:28:24.673271 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5101 09:28:24.676452 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5102 09:28:24.679553 ===================================
5103 09:28:24.683260 LPDDR4 DRAM CONFIGURATION
5104 09:28:24.686114 ===================================
5105 09:28:24.686239 EX_ROW_EN[0] = 0x10
5106 09:28:24.689815 EX_ROW_EN[1] = 0x0
5107 09:28:24.689893 LP4Y_EN = 0x0
5108 09:28:24.692745 WORK_FSP = 0x0
5109 09:28:24.692825 WL = 0x3
5110 09:28:24.696414 RL = 0x3
5111 09:28:24.696489 BL = 0x2
5112 09:28:24.699460 RPST = 0x0
5113 09:28:24.699537 RD_PRE = 0x0
5114 09:28:24.703085 WR_PRE = 0x1
5115 09:28:24.706460 WR_PST = 0x0
5116 09:28:24.706554 DBI_WR = 0x0
5117 09:28:24.709249 DBI_RD = 0x0
5118 09:28:24.709330 OTF = 0x1
5119 09:28:24.712999 ===================================
5120 09:28:24.719183 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5121 09:28:24.722830 nWR fixed to 30
5122 09:28:24.726261 [ModeRegInit_LP4] CH0 RK0
5123 09:28:24.726346 [ModeRegInit_LP4] CH0 RK1
5124 09:28:24.729762 [ModeRegInit_LP4] CH1 RK0
5125 09:28:24.733231 [ModeRegInit_LP4] CH1 RK1
5126 09:28:24.733303 match AC timing 9
5127 09:28:24.739380 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5128 09:28:24.742630 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5129 09:28:24.746079 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5130 09:28:24.752608 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5131 09:28:24.755569 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5132 09:28:24.755660 ==
5133 09:28:24.759138 Dram Type= 6, Freq= 0, CH_0, rank 0
5134 09:28:24.762332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5135 09:28:24.765950 ==
5136 09:28:24.768826 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5137 09:28:24.775341 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5138 09:28:24.778909 [CA 0] Center 37 (7~68) winsize 62
5139 09:28:24.782068 [CA 1] Center 38 (7~69) winsize 63
5140 09:28:24.785497 [CA 2] Center 34 (4~65) winsize 62
5141 09:28:24.788519 [CA 3] Center 34 (4~65) winsize 62
5142 09:28:24.791894 [CA 4] Center 34 (4~64) winsize 61
5143 09:28:24.795044 [CA 5] Center 33 (4~63) winsize 60
5144 09:28:24.795140
5145 09:28:24.798661 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5146 09:28:24.798741
5147 09:28:24.801720 [CATrainingPosCal] consider 1 rank data
5148 09:28:24.805568 u2DelayCellTimex100 = 270/100 ps
5149 09:28:24.808575 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5150 09:28:24.811528 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5151 09:28:24.815049 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5152 09:28:24.821790 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5153 09:28:24.824867 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5154 09:28:24.828557 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5155 09:28:24.828640
5156 09:28:24.831552 CA PerBit enable=1, Macro0, CA PI delay=33
5157 09:28:24.831634
5158 09:28:24.834940 [CBTSetCACLKResult] CA Dly = 33
5159 09:28:24.835045 CS Dly: 7 (0~38)
5160 09:28:24.835140 ==
5161 09:28:24.838262 Dram Type= 6, Freq= 0, CH_0, rank 1
5162 09:28:24.845009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 09:28:24.845090 ==
5164 09:28:24.848096 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5165 09:28:24.854922 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5166 09:28:24.857810 [CA 0] Center 37 (7~68) winsize 62
5167 09:28:24.861496 [CA 1] Center 37 (7~68) winsize 62
5168 09:28:24.864329 [CA 2] Center 34 (4~65) winsize 62
5169 09:28:24.868063 [CA 3] Center 34 (4~65) winsize 62
5170 09:28:24.871089 [CA 4] Center 33 (3~64) winsize 62
5171 09:28:24.874309 [CA 5] Center 33 (3~63) winsize 61
5172 09:28:24.874413
5173 09:28:24.877940 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5174 09:28:24.878060
5175 09:28:24.881115 [CATrainingPosCal] consider 2 rank data
5176 09:28:24.884549 u2DelayCellTimex100 = 270/100 ps
5177 09:28:24.887502 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5178 09:28:24.894058 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5179 09:28:24.897268 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5180 09:28:24.900578 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5181 09:28:24.904117 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5182 09:28:24.907380 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5183 09:28:24.907493
5184 09:28:24.910566 CA PerBit enable=1, Macro0, CA PI delay=33
5185 09:28:24.910649
5186 09:28:24.914182 [CBTSetCACLKResult] CA Dly = 33
5187 09:28:24.917258 CS Dly: 7 (0~39)
5188 09:28:24.917339
5189 09:28:24.920244 ----->DramcWriteLeveling(PI) begin...
5190 09:28:24.920320 ==
5191 09:28:24.924201 Dram Type= 6, Freq= 0, CH_0, rank 0
5192 09:28:24.926841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5193 09:28:24.926923 ==
5194 09:28:24.930132 Write leveling (Byte 0): 32 => 32
5195 09:28:24.933874 Write leveling (Byte 1): 30 => 30
5196 09:28:24.936997 DramcWriteLeveling(PI) end<-----
5197 09:28:24.937079
5198 09:28:24.937144 ==
5199 09:28:24.940020 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 09:28:24.943550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 09:28:24.943632 ==
5202 09:28:24.946770 [Gating] SW mode calibration
5203 09:28:24.953684 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5204 09:28:24.960257 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5205 09:28:24.963315 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5206 09:28:24.966838 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
5207 09:28:24.973512 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5208 09:28:24.976520 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5209 09:28:24.980196 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5210 09:28:24.986891 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5211 09:28:24.989936 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5212 09:28:24.993631 0 14 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
5213 09:28:24.999767 0 15 0 | B1->B0 | 3131 2727 | 0 0 | (0 1) (0 0)
5214 09:28:25.003238 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5215 09:28:25.006596 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5216 09:28:25.013132 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5217 09:28:25.015953 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5218 09:28:25.019569 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5219 09:28:25.026197 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5220 09:28:25.029564 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (1 1)
5221 09:28:25.033014 1 0 0 | B1->B0 | 3131 4444 | 0 0 | (0 0) (0 0)
5222 09:28:25.039287 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5223 09:28:25.042531 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5224 09:28:25.049073 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5225 09:28:25.052578 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 09:28:25.055793 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 09:28:25.058823 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 09:28:25.065671 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5229 09:28:25.068690 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5230 09:28:25.072170 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 09:28:25.078887 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 09:28:25.081995 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 09:28:25.088729 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5234 09:28:25.091611 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5235 09:28:25.095479 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5236 09:28:25.098479 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5237 09:28:25.105203 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5238 09:28:25.108353 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5239 09:28:25.111923 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5240 09:28:25.118132 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5241 09:28:25.121670 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5242 09:28:25.124702 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 09:28:25.131487 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 09:28:25.134830 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5245 09:28:25.138516 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5246 09:28:25.145588 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5247 09:28:25.147897 Total UI for P1: 0, mck2ui 16
5248 09:28:25.151547 best dqsien dly found for B0: ( 1, 2, 30)
5249 09:28:25.154881 Total UI for P1: 0, mck2ui 16
5250 09:28:25.157732 best dqsien dly found for B1: ( 1, 2, 30)
5251 09:28:25.161272 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5252 09:28:25.164649 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5253 09:28:25.164730
5254 09:28:25.168309 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5255 09:28:25.171174 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5256 09:28:25.174950 [Gating] SW calibration Done
5257 09:28:25.175035 ==
5258 09:28:25.177741 Dram Type= 6, Freq= 0, CH_0, rank 0
5259 09:28:25.181228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5260 09:28:25.181313 ==
5261 09:28:25.184332 RX Vref Scan: 0
5262 09:28:25.184417
5263 09:28:25.187415 RX Vref 0 -> 0, step: 1
5264 09:28:25.187499
5265 09:28:25.187583 RX Delay -80 -> 252, step: 8
5266 09:28:25.194194 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5267 09:28:25.197893 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5268 09:28:25.201022 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5269 09:28:25.203963 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5270 09:28:25.207645 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5271 09:28:25.214149 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5272 09:28:25.217245 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5273 09:28:25.220370 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5274 09:28:25.224038 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5275 09:28:25.227093 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5276 09:28:25.230693 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5277 09:28:25.237270 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5278 09:28:25.240300 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5279 09:28:25.243828 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5280 09:28:25.247537 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5281 09:28:25.253634 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5282 09:28:25.253722 ==
5283 09:28:25.256752 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 09:28:25.260143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 09:28:25.260228 ==
5286 09:28:25.260313 DQS Delay:
5287 09:28:25.263267 DQS0 = 0, DQS1 = 0
5288 09:28:25.263351 DQM Delay:
5289 09:28:25.266879 DQM0 = 96, DQM1 = 86
5290 09:28:25.267028 DQ Delay:
5291 09:28:25.270090 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5292 09:28:25.273204 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5293 09:28:25.276836 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5294 09:28:25.280100 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5295 09:28:25.280182
5296 09:28:25.280245
5297 09:28:25.280304 ==
5298 09:28:25.283084 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 09:28:25.286727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 09:28:25.286809 ==
5301 09:28:25.286872
5302 09:28:25.290130
5303 09:28:25.290250 TX Vref Scan disable
5304 09:28:25.293229 == TX Byte 0 ==
5305 09:28:25.297023 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5306 09:28:25.299985 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5307 09:28:25.303226 == TX Byte 1 ==
5308 09:28:25.306146 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5309 09:28:25.309980 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5310 09:28:25.310062 ==
5311 09:28:25.312959 Dram Type= 6, Freq= 0, CH_0, rank 0
5312 09:28:25.319644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 09:28:25.319729 ==
5314 09:28:25.319814
5315 09:28:25.319892
5316 09:28:25.319970 TX Vref Scan disable
5317 09:28:25.323931 == TX Byte 0 ==
5318 09:28:25.326931 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5319 09:28:25.333810 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5320 09:28:25.333895 == TX Byte 1 ==
5321 09:28:25.337306 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5322 09:28:25.343358 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5323 09:28:25.343446
5324 09:28:25.343531 [DATLAT]
5325 09:28:25.343610 Freq=933, CH0 RK0
5326 09:28:25.343688
5327 09:28:25.347105 DATLAT Default: 0xd
5328 09:28:25.349950 0, 0xFFFF, sum = 0
5329 09:28:25.350036 1, 0xFFFF, sum = 0
5330 09:28:25.353620 2, 0xFFFF, sum = 0
5331 09:28:25.353706 3, 0xFFFF, sum = 0
5332 09:28:25.356723 4, 0xFFFF, sum = 0
5333 09:28:25.356808 5, 0xFFFF, sum = 0
5334 09:28:25.360384 6, 0xFFFF, sum = 0
5335 09:28:25.360468 7, 0xFFFF, sum = 0
5336 09:28:25.363248 8, 0xFFFF, sum = 0
5337 09:28:25.363333 9, 0xFFFF, sum = 0
5338 09:28:25.366807 10, 0x0, sum = 1
5339 09:28:25.366892 11, 0x0, sum = 2
5340 09:28:25.370058 12, 0x0, sum = 3
5341 09:28:25.370143 13, 0x0, sum = 4
5342 09:28:25.372955 best_step = 11
5343 09:28:25.373039
5344 09:28:25.373122 ==
5345 09:28:25.376283 Dram Type= 6, Freq= 0, CH_0, rank 0
5346 09:28:25.379964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5347 09:28:25.380048 ==
5348 09:28:25.380133 RX Vref Scan: 1
5349 09:28:25.382859
5350 09:28:25.382942 RX Vref 0 -> 0, step: 1
5351 09:28:25.383026
5352 09:28:25.386585 RX Delay -61 -> 252, step: 4
5353 09:28:25.386668
5354 09:28:25.389390 Set Vref, RX VrefLevel [Byte0]: 60
5355 09:28:25.392641 [Byte1]: 58
5356 09:28:25.396738
5357 09:28:25.396818 Final RX Vref Byte 0 = 60 to rank0
5358 09:28:25.399979 Final RX Vref Byte 1 = 58 to rank0
5359 09:28:25.403128 Final RX Vref Byte 0 = 60 to rank1
5360 09:28:25.406117 Final RX Vref Byte 1 = 58 to rank1==
5361 09:28:25.409308 Dram Type= 6, Freq= 0, CH_0, rank 0
5362 09:28:25.416195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 09:28:25.416278 ==
5364 09:28:25.416341 DQS Delay:
5365 09:28:25.419729 DQS0 = 0, DQS1 = 0
5366 09:28:25.419808 DQM Delay:
5367 09:28:25.419870 DQM0 = 96, DQM1 = 86
5368 09:28:25.422549 DQ Delay:
5369 09:28:25.426193 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5370 09:28:25.429127 DQ4 =96, DQ5 =88, DQ6 =108, DQ7 =106
5371 09:28:25.432801 DQ8 =80, DQ9 =78, DQ10 =86, DQ11 =82
5372 09:28:25.435786 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =90
5373 09:28:25.435865
5374 09:28:25.435926
5375 09:28:25.442555 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5376 09:28:25.445780 CH0 RK0: MR19=505, MR18=2F15
5377 09:28:25.452448 CH0_RK0: MR19=0x505, MR18=0x2F15, DQSOSC=407, MR23=63, INC=65, DEC=43
5378 09:28:25.452529
5379 09:28:25.455795 ----->DramcWriteLeveling(PI) begin...
5380 09:28:25.455876 ==
5381 09:28:25.458871 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 09:28:25.462507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 09:28:25.462588 ==
5384 09:28:25.465593 Write leveling (Byte 0): 34 => 34
5385 09:28:25.468589 Write leveling (Byte 1): 29 => 29
5386 09:28:25.471953 DramcWriteLeveling(PI) end<-----
5387 09:28:25.472033
5388 09:28:25.472096 ==
5389 09:28:25.475522 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 09:28:25.482123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 09:28:25.482245 ==
5392 09:28:25.482313 [Gating] SW mode calibration
5393 09:28:25.492172 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5394 09:28:25.495207 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5395 09:28:25.498282 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5396 09:28:25.504825 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5397 09:28:25.508266 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5398 09:28:25.514772 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5399 09:28:25.518311 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5400 09:28:25.521188 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5401 09:28:25.527872 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5402 09:28:25.531423 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
5403 09:28:25.534498 0 15 0 | B1->B0 | 2d2d 2727 | 0 0 | (0 0) (0 0)
5404 09:28:25.541157 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5405 09:28:25.544228 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5406 09:28:25.547847 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5407 09:28:25.554676 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5408 09:28:25.557473 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5409 09:28:25.561211 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5410 09:28:25.567468 0 15 28 | B1->B0 | 2929 3939 | 0 0 | (0 0) (0 0)
5411 09:28:25.570527 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5412 09:28:25.574247 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 09:28:25.580516 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5414 09:28:25.583975 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5415 09:28:25.587546 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5416 09:28:25.593877 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5417 09:28:25.596904 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5418 09:28:25.600574 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5419 09:28:25.607312 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5420 09:28:25.610462 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 09:28:25.613505 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 09:28:25.620146 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 09:28:25.623736 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 09:28:25.626622 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 09:28:25.633401 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 09:28:25.636837 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5427 09:28:25.639935 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5428 09:28:25.646124 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5429 09:28:25.649745 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5430 09:28:25.652810 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5431 09:28:25.659431 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 09:28:25.662848 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 09:28:25.666013 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 09:28:25.672264 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5435 09:28:25.676048 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5436 09:28:25.678956 Total UI for P1: 0, mck2ui 16
5437 09:28:25.682623 best dqsien dly found for B0: ( 1, 2, 28)
5438 09:28:25.685776 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5439 09:28:25.689024 Total UI for P1: 0, mck2ui 16
5440 09:28:25.692437 best dqsien dly found for B1: ( 1, 2, 30)
5441 09:28:25.695615 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5442 09:28:25.699293 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5443 09:28:25.699377
5444 09:28:25.705124 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5445 09:28:25.708324 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5446 09:28:25.711745 [Gating] SW calibration Done
5447 09:28:25.711830 ==
5448 09:28:25.714942 Dram Type= 6, Freq= 0, CH_0, rank 1
5449 09:28:25.718308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5450 09:28:25.718393 ==
5451 09:28:25.718477 RX Vref Scan: 0
5452 09:28:25.721981
5453 09:28:25.722065 RX Vref 0 -> 0, step: 1
5454 09:28:25.722187
5455 09:28:25.725063 RX Delay -80 -> 252, step: 8
5456 09:28:25.728202 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5457 09:28:25.731301 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5458 09:28:25.737922 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5459 09:28:25.741551 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5460 09:28:25.744789 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5461 09:28:25.747886 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5462 09:28:25.751524 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5463 09:28:25.754594 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5464 09:28:25.761203 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5465 09:28:25.764544 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5466 09:28:25.767572 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5467 09:28:25.770634 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5468 09:28:25.774361 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5469 09:28:25.781028 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5470 09:28:25.784264 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5471 09:28:25.787886 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5472 09:28:25.787967 ==
5473 09:28:25.790712 Dram Type= 6, Freq= 0, CH_0, rank 1
5474 09:28:25.794289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5475 09:28:25.794370 ==
5476 09:28:25.797262 DQS Delay:
5477 09:28:25.797342 DQS0 = 0, DQS1 = 0
5478 09:28:25.800903 DQM Delay:
5479 09:28:25.800983 DQM0 = 96, DQM1 = 90
5480 09:28:25.801045 DQ Delay:
5481 09:28:25.803903 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5482 09:28:25.807487 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5483 09:28:25.810399 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5484 09:28:25.813894 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5485 09:28:25.813973
5486 09:28:25.817357
5487 09:28:25.817438 ==
5488 09:28:25.820251 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 09:28:25.824095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 09:28:25.824176 ==
5491 09:28:25.824242
5492 09:28:25.824301
5493 09:28:25.827085 TX Vref Scan disable
5494 09:28:25.827164 == TX Byte 0 ==
5495 09:28:25.833915 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5496 09:28:25.837032 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5497 09:28:25.837112 == TX Byte 1 ==
5498 09:28:25.843829 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5499 09:28:25.847054 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5500 09:28:25.847134 ==
5501 09:28:25.850143 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 09:28:25.853201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 09:28:25.853281 ==
5504 09:28:25.853350
5505 09:28:25.853407
5506 09:28:25.856811 TX Vref Scan disable
5507 09:28:25.860399 == TX Byte 0 ==
5508 09:28:25.863000 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5509 09:28:25.866804 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5510 09:28:25.869946 == TX Byte 1 ==
5511 09:28:25.873033 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5512 09:28:25.876279 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5513 09:28:25.876358
5514 09:28:25.879804 [DATLAT]
5515 09:28:25.879883 Freq=933, CH0 RK1
5516 09:28:25.879945
5517 09:28:25.882581 DATLAT Default: 0xb
5518 09:28:25.882718 0, 0xFFFF, sum = 0
5519 09:28:25.886139 1, 0xFFFF, sum = 0
5520 09:28:25.886275 2, 0xFFFF, sum = 0
5521 09:28:25.889860 3, 0xFFFF, sum = 0
5522 09:28:25.889946 4, 0xFFFF, sum = 0
5523 09:28:25.892923 5, 0xFFFF, sum = 0
5524 09:28:25.895995 6, 0xFFFF, sum = 0
5525 09:28:25.896076 7, 0xFFFF, sum = 0
5526 09:28:25.899487 8, 0xFFFF, sum = 0
5527 09:28:25.899570 9, 0xFFFF, sum = 0
5528 09:28:25.902463 10, 0x0, sum = 1
5529 09:28:25.902543 11, 0x0, sum = 2
5530 09:28:25.906277 12, 0x0, sum = 3
5531 09:28:25.906363 13, 0x0, sum = 4
5532 09:28:25.906483 best_step = 11
5533 09:28:25.906562
5534 09:28:25.909114 ==
5535 09:28:25.912661 Dram Type= 6, Freq= 0, CH_0, rank 1
5536 09:28:25.916288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5537 09:28:25.916373 ==
5538 09:28:25.916457 RX Vref Scan: 0
5539 09:28:25.916537
5540 09:28:25.919202 RX Vref 0 -> 0, step: 1
5541 09:28:25.919286
5542 09:28:25.922436 RX Delay -61 -> 252, step: 4
5543 09:28:25.925938 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5544 09:28:25.932200 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5545 09:28:25.935962 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5546 09:28:25.939067 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5547 09:28:25.942699 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5548 09:28:25.945641 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5549 09:28:25.949214 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5550 09:28:25.955804 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5551 09:28:25.958889 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5552 09:28:25.962613 iDelay=203, Bit 9, Center 76 (-13 ~ 166) 180
5553 09:28:25.965656 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5554 09:28:25.968780 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5555 09:28:25.975380 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5556 09:28:25.979170 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5557 09:28:25.982138 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5558 09:28:25.985212 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5559 09:28:25.985296 ==
5560 09:28:25.988727 Dram Type= 6, Freq= 0, CH_0, rank 1
5561 09:28:25.995387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 09:28:25.995472 ==
5563 09:28:25.995556 DQS Delay:
5564 09:28:25.998302 DQS0 = 0, DQS1 = 0
5565 09:28:25.998387 DQM Delay:
5566 09:28:25.998471 DQM0 = 95, DQM1 = 87
5567 09:28:26.001977 DQ Delay:
5568 09:28:26.005012 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5569 09:28:26.008272 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5570 09:28:26.011607 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =82
5571 09:28:26.015024 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =92
5572 09:28:26.015104
5573 09:28:26.015166
5574 09:28:26.022011 [DQSOSCAuto] RK1, (LSB)MR18= 0x25f5, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 410 ps
5575 09:28:26.025249 CH0 RK1: MR19=504, MR18=25F5
5576 09:28:26.031915 CH0_RK1: MR19=0x504, MR18=0x25F5, DQSOSC=410, MR23=63, INC=64, DEC=42
5577 09:28:26.035375 [RxdqsGatingPostProcess] freq 933
5578 09:28:26.038631 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5579 09:28:26.041905 best DQS0 dly(2T, 0.5T) = (0, 10)
5580 09:28:26.045393 best DQS1 dly(2T, 0.5T) = (0, 10)
5581 09:28:26.048536 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5582 09:28:26.051625 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5583 09:28:26.054728 best DQS0 dly(2T, 0.5T) = (0, 10)
5584 09:28:26.058345 best DQS1 dly(2T, 0.5T) = (0, 10)
5585 09:28:26.061940 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5586 09:28:26.064959 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5587 09:28:26.068212 Pre-setting of DQS Precalculation
5588 09:28:26.071668 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5589 09:28:26.075083 ==
5590 09:28:26.075169 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 09:28:26.081416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5592 09:28:26.081498 ==
5593 09:28:26.084549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5594 09:28:26.091345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5595 09:28:26.094438 [CA 0] Center 37 (7~67) winsize 61
5596 09:28:26.098115 [CA 1] Center 37 (7~68) winsize 62
5597 09:28:26.101128 [CA 2] Center 34 (4~65) winsize 62
5598 09:28:26.104535 [CA 3] Center 33 (3~64) winsize 62
5599 09:28:26.107638 [CA 4] Center 34 (4~64) winsize 61
5600 09:28:26.111112 [CA 5] Center 33 (3~64) winsize 62
5601 09:28:26.111192
5602 09:28:26.114527 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5603 09:28:26.114607
5604 09:28:26.118122 [CATrainingPosCal] consider 1 rank data
5605 09:28:26.120849 u2DelayCellTimex100 = 270/100 ps
5606 09:28:26.124245 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5607 09:28:26.130860 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5608 09:28:26.134431 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5609 09:28:26.137761 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5610 09:28:26.140679 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5611 09:28:26.144268 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5612 09:28:26.144349
5613 09:28:26.147695 CA PerBit enable=1, Macro0, CA PI delay=33
5614 09:28:26.147777
5615 09:28:26.151058 [CBTSetCACLKResult] CA Dly = 33
5616 09:28:26.154378 CS Dly: 6 (0~37)
5617 09:28:26.154459 ==
5618 09:28:26.157476 Dram Type= 6, Freq= 0, CH_1, rank 1
5619 09:28:26.161075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 09:28:26.161157 ==
5621 09:28:26.167246 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5622 09:28:26.171021 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5623 09:28:26.174786 [CA 0] Center 36 (6~67) winsize 62
5624 09:28:26.177720 [CA 1] Center 37 (7~67) winsize 61
5625 09:28:26.181011 [CA 2] Center 34 (4~65) winsize 62
5626 09:28:26.184422 [CA 3] Center 34 (4~65) winsize 62
5627 09:28:26.188101 [CA 4] Center 34 (4~65) winsize 62
5628 09:28:26.191124 [CA 5] Center 33 (3~64) winsize 62
5629 09:28:26.191205
5630 09:28:26.194322 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5631 09:28:26.194428
5632 09:28:26.197366 [CATrainingPosCal] consider 2 rank data
5633 09:28:26.200908 u2DelayCellTimex100 = 270/100 ps
5634 09:28:26.204719 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5635 09:28:26.210758 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5636 09:28:26.214011 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5637 09:28:26.217823 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5638 09:28:26.220667 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5639 09:28:26.224198 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5640 09:28:26.224280
5641 09:28:26.227341 CA PerBit enable=1, Macro0, CA PI delay=33
5642 09:28:26.227424
5643 09:28:26.230769 [CBTSetCACLKResult] CA Dly = 33
5644 09:28:26.234518 CS Dly: 7 (0~39)
5645 09:28:26.234599
5646 09:28:26.237507 ----->DramcWriteLeveling(PI) begin...
5647 09:28:26.237590 ==
5648 09:28:26.240814 Dram Type= 6, Freq= 0, CH_1, rank 0
5649 09:28:26.243990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5650 09:28:26.244073 ==
5651 09:28:26.247031 Write leveling (Byte 0): 24 => 24
5652 09:28:26.250464 Write leveling (Byte 1): 26 => 26
5653 09:28:26.253744 DramcWriteLeveling(PI) end<-----
5654 09:28:26.253824
5655 09:28:26.253888 ==
5656 09:28:26.257205 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 09:28:26.260655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 09:28:26.260738 ==
5659 09:28:26.263780 [Gating] SW mode calibration
5660 09:28:26.270443 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5661 09:28:26.277167 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5662 09:28:26.280238 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5663 09:28:26.283482 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 09:28:26.289938 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 09:28:26.293682 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 09:28:26.296704 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5667 09:28:26.303534 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5668 09:28:26.306574 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
5669 09:28:26.309826 0 14 28 | B1->B0 | 2d2d 2c2c | 0 0 | (0 1) (1 1)
5670 09:28:26.317079 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5671 09:28:26.320036 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 09:28:26.323611 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 09:28:26.330521 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 09:28:26.333278 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5675 09:28:26.336616 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5676 09:28:26.343286 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5677 09:28:26.346445 0 15 28 | B1->B0 | 3737 3838 | 0 1 | (0 0) (0 0)
5678 09:28:26.349636 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 09:28:26.356393 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 09:28:26.359380 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 09:28:26.362830 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 09:28:26.369649 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 09:28:26.372699 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 09:28:26.376113 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5685 09:28:26.382521 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5686 09:28:26.385764 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 09:28:26.389012 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 09:28:26.395701 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 09:28:26.398824 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 09:28:26.402354 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 09:28:26.408952 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 09:28:26.412161 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 09:28:26.415649 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 09:28:26.422016 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 09:28:26.425666 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 09:28:26.428696 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 09:28:26.435338 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 09:28:26.438409 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 09:28:26.441688 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 09:28:26.448617 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5701 09:28:26.451798 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5702 09:28:26.455282 Total UI for P1: 0, mck2ui 16
5703 09:28:26.458454 best dqsien dly found for B0: ( 1, 2, 24)
5704 09:28:26.461512 Total UI for P1: 0, mck2ui 16
5705 09:28:26.465237 best dqsien dly found for B1: ( 1, 2, 24)
5706 09:28:26.468387 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5707 09:28:26.471418 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5708 09:28:26.471499
5709 09:28:26.474935 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5710 09:28:26.477916 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5711 09:28:26.481669 [Gating] SW calibration Done
5712 09:28:26.481750 ==
5713 09:28:26.485169 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 09:28:26.491531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 09:28:26.491613 ==
5716 09:28:26.491676 RX Vref Scan: 0
5717 09:28:26.491736
5718 09:28:26.494705 RX Vref 0 -> 0, step: 1
5719 09:28:26.494786
5720 09:28:26.498145 RX Delay -80 -> 252, step: 8
5721 09:28:26.501010 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5722 09:28:26.504488 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5723 09:28:26.507778 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5724 09:28:26.511375 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5725 09:28:26.517972 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5726 09:28:26.521124 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5727 09:28:26.524651 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5728 09:28:26.527540 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5729 09:28:26.530920 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5730 09:28:26.537706 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5731 09:28:26.540676 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5732 09:28:26.543818 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5733 09:28:26.547475 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5734 09:28:26.550607 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5735 09:28:26.553873 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5736 09:28:26.560879 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5737 09:28:26.560980 ==
5738 09:28:26.563808 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 09:28:26.567550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 09:28:26.567632 ==
5741 09:28:26.567695 DQS Delay:
5742 09:28:26.570695 DQS0 = 0, DQS1 = 0
5743 09:28:26.570776 DQM Delay:
5744 09:28:26.573973 DQM0 = 102, DQM1 = 91
5745 09:28:26.574054 DQ Delay:
5746 09:28:26.577150 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =99
5747 09:28:26.580515 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5748 09:28:26.583478 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5749 09:28:26.587252 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5750 09:28:26.587333
5751 09:28:26.587397
5752 09:28:26.587456 ==
5753 09:28:26.590589 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 09:28:26.596830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 09:28:26.596912 ==
5756 09:28:26.596976
5757 09:28:26.597034
5758 09:28:26.597091 TX Vref Scan disable
5759 09:28:26.600371 == TX Byte 0 ==
5760 09:28:26.603760 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5761 09:28:26.607184 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5762 09:28:26.610321 == TX Byte 1 ==
5763 09:28:26.613443 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5764 09:28:26.620320 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5765 09:28:26.620402 ==
5766 09:28:26.623324 Dram Type= 6, Freq= 0, CH_1, rank 0
5767 09:28:26.627103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 09:28:26.627185 ==
5769 09:28:26.627248
5770 09:28:26.627307
5771 09:28:26.630125 TX Vref Scan disable
5772 09:28:26.630245 == TX Byte 0 ==
5773 09:28:26.636420 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5774 09:28:26.639755 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5775 09:28:26.639837 == TX Byte 1 ==
5776 09:28:26.646602 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5777 09:28:26.649669 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5778 09:28:26.649768
5779 09:28:26.649845 [DATLAT]
5780 09:28:26.653270 Freq=933, CH1 RK0
5781 09:28:26.653351
5782 09:28:26.653414 DATLAT Default: 0xd
5783 09:28:26.656143 0, 0xFFFF, sum = 0
5784 09:28:26.659607 1, 0xFFFF, sum = 0
5785 09:28:26.659689 2, 0xFFFF, sum = 0
5786 09:28:26.662791 3, 0xFFFF, sum = 0
5787 09:28:26.662874 4, 0xFFFF, sum = 0
5788 09:28:26.665892 5, 0xFFFF, sum = 0
5789 09:28:26.665974 6, 0xFFFF, sum = 0
5790 09:28:26.669706 7, 0xFFFF, sum = 0
5791 09:28:26.669788 8, 0xFFFF, sum = 0
5792 09:28:26.672726 9, 0xFFFF, sum = 0
5793 09:28:26.672809 10, 0x0, sum = 1
5794 09:28:26.676228 11, 0x0, sum = 2
5795 09:28:26.676310 12, 0x0, sum = 3
5796 09:28:26.679505 13, 0x0, sum = 4
5797 09:28:26.679587 best_step = 11
5798 09:28:26.679650
5799 09:28:26.679709 ==
5800 09:28:26.682447 Dram Type= 6, Freq= 0, CH_1, rank 0
5801 09:28:26.685839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5802 09:28:26.688887 ==
5803 09:28:26.688968 RX Vref Scan: 1
5804 09:28:26.689032
5805 09:28:26.692263 RX Vref 0 -> 0, step: 1
5806 09:28:26.692344
5807 09:28:26.695898 RX Delay -69 -> 252, step: 4
5808 09:28:26.695979
5809 09:28:26.699041 Set Vref, RX VrefLevel [Byte0]: 48
5810 09:28:26.702033 [Byte1]: 54
5811 09:28:26.702114
5812 09:28:26.705752 Final RX Vref Byte 0 = 48 to rank0
5813 09:28:26.708746 Final RX Vref Byte 1 = 54 to rank0
5814 09:28:26.712048 Final RX Vref Byte 0 = 48 to rank1
5815 09:28:26.715788 Final RX Vref Byte 1 = 54 to rank1==
5816 09:28:26.718809 Dram Type= 6, Freq= 0, CH_1, rank 0
5817 09:28:26.722473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5818 09:28:26.722556 ==
5819 09:28:26.725444 DQS Delay:
5820 09:28:26.725525 DQS0 = 0, DQS1 = 0
5821 09:28:26.725589 DQM Delay:
5822 09:28:26.728681 DQM0 = 101, DQM1 = 94
5823 09:28:26.728763 DQ Delay:
5824 09:28:26.732171 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5825 09:28:26.735424 DQ4 =100, DQ5 =112, DQ6 =110, DQ7 =98
5826 09:28:26.738905 DQ8 =80, DQ9 =86, DQ10 =92, DQ11 =86
5827 09:28:26.742358 DQ12 =102, DQ13 =98, DQ14 =104, DQ15 =104
5828 09:28:26.742440
5829 09:28:26.742503
5830 09:28:26.751778 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 413 ps
5831 09:28:26.755245 CH1 RK0: MR19=505, MR18=1B0B
5832 09:28:26.761725 CH1_RK0: MR19=0x505, MR18=0x1B0B, DQSOSC=413, MR23=63, INC=63, DEC=42
5833 09:28:26.761808
5834 09:28:26.765323 ----->DramcWriteLeveling(PI) begin...
5835 09:28:26.765406 ==
5836 09:28:26.768295 Dram Type= 6, Freq= 0, CH_1, rank 1
5837 09:28:26.771414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5838 09:28:26.771496 ==
5839 09:28:26.775110 Write leveling (Byte 0): 26 => 26
5840 09:28:26.778036 Write leveling (Byte 1): 27 => 27
5841 09:28:26.781987 DramcWriteLeveling(PI) end<-----
5842 09:28:26.782068
5843 09:28:26.782132 ==
5844 09:28:26.784906 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 09:28:26.788394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 09:28:26.788476 ==
5847 09:28:26.791539 [Gating] SW mode calibration
5848 09:28:26.798027 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5849 09:28:26.804757 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5850 09:28:26.808461 0 14 0 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
5851 09:28:26.811585 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5852 09:28:26.818073 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5853 09:28:26.821232 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 09:28:26.824536 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 09:28:26.831489 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 09:28:26.834534 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
5857 09:28:26.837722 0 14 28 | B1->B0 | 2525 2f2f | 1 1 | (1 0) (1 1)
5858 09:28:26.844719 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
5859 09:28:26.847580 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5860 09:28:26.851197 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5861 09:28:26.857437 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5862 09:28:26.860814 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 09:28:26.864169 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 09:28:26.870531 0 15 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5865 09:28:26.873921 0 15 28 | B1->B0 | 4444 2f2f | 0 1 | (0 0) (0 0)
5866 09:28:26.877626 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 09:28:26.883565 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5868 09:28:26.887277 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5869 09:28:26.890318 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 09:28:26.896869 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 09:28:26.900452 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5872 09:28:26.903473 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5873 09:28:26.910306 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 09:28:26.913447 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 09:28:26.916944 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 09:28:26.923781 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 09:28:26.926611 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 09:28:26.930048 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 09:28:26.936643 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5880 09:28:26.939835 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 09:28:26.943453 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 09:28:26.949591 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 09:28:26.952970 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 09:28:26.956310 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 09:28:26.963206 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 09:28:26.966224 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 09:28:26.969815 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 09:28:26.976367 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5889 09:28:26.979396 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5890 09:28:26.982584 Total UI for P1: 0, mck2ui 16
5891 09:28:26.986112 best dqsien dly found for B0: ( 1, 2, 26)
5892 09:28:26.989287 Total UI for P1: 0, mck2ui 16
5893 09:28:26.992853 best dqsien dly found for B1: ( 1, 2, 24)
5894 09:28:26.995893 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5895 09:28:26.999475 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5896 09:28:26.999557
5897 09:28:27.002664 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5898 09:28:27.006149 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5899 09:28:27.009288 [Gating] SW calibration Done
5900 09:28:27.009370 ==
5901 09:28:27.012361 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 09:28:27.019104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 09:28:27.019186 ==
5904 09:28:27.019250 RX Vref Scan: 0
5905 09:28:27.019309
5906 09:28:27.022101 RX Vref 0 -> 0, step: 1
5907 09:28:27.022222
5908 09:28:27.025909 RX Delay -80 -> 252, step: 8
5909 09:28:27.028937 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5910 09:28:27.032733 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5911 09:28:27.035636 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5912 09:28:27.038910 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5913 09:28:27.045468 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5914 09:28:27.048323 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5915 09:28:27.052085 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5916 09:28:27.055189 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5917 09:28:27.058326 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5918 09:28:27.065118 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5919 09:28:27.068379 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5920 09:28:27.071807 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5921 09:28:27.074702 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5922 09:28:27.078432 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5923 09:28:27.084573 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5924 09:28:27.087904 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5925 09:28:27.087985 ==
5926 09:28:27.091437 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 09:28:27.094717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 09:28:27.094798 ==
5929 09:28:27.094861 DQS Delay:
5930 09:28:27.098064 DQS0 = 0, DQS1 = 0
5931 09:28:27.098145 DQM Delay:
5932 09:28:27.101402 DQM0 = 99, DQM1 = 93
5933 09:28:27.101486 DQ Delay:
5934 09:28:27.104279 DQ0 =103, DQ1 =91, DQ2 =91, DQ3 =99
5935 09:28:27.107842 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5936 09:28:27.111489 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =87
5937 09:28:27.114629 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5938 09:28:27.114711
5939 09:28:27.114795
5940 09:28:27.114875 ==
5941 09:28:27.117691 Dram Type= 6, Freq= 0, CH_1, rank 1
5942 09:28:27.124460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5943 09:28:27.124543 ==
5944 09:28:27.124607
5945 09:28:27.124666
5946 09:28:27.127803 TX Vref Scan disable
5947 09:28:27.127884 == TX Byte 0 ==
5948 09:28:27.130760 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5949 09:28:27.137437 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5950 09:28:27.137518 == TX Byte 1 ==
5951 09:28:27.140556 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5952 09:28:27.147438 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5953 09:28:27.147519 ==
5954 09:28:27.150537 Dram Type= 6, Freq= 0, CH_1, rank 1
5955 09:28:27.153661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5956 09:28:27.153743 ==
5957 09:28:27.153806
5958 09:28:27.153864
5959 09:28:27.157208 TX Vref Scan disable
5960 09:28:27.160543 == TX Byte 0 ==
5961 09:28:27.163662 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5962 09:28:27.167258 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5963 09:28:27.170311 == TX Byte 1 ==
5964 09:28:27.173854 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5965 09:28:27.176631 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5966 09:28:27.176712
5967 09:28:27.180246 [DATLAT]
5968 09:28:27.180326 Freq=933, CH1 RK1
5969 09:28:27.180390
5970 09:28:27.183164 DATLAT Default: 0xb
5971 09:28:27.183245 0, 0xFFFF, sum = 0
5972 09:28:27.186716 1, 0xFFFF, sum = 0
5973 09:28:27.186798 2, 0xFFFF, sum = 0
5974 09:28:27.189907 3, 0xFFFF, sum = 0
5975 09:28:27.189990 4, 0xFFFF, sum = 0
5976 09:28:27.193491 5, 0xFFFF, sum = 0
5977 09:28:27.193573 6, 0xFFFF, sum = 0
5978 09:28:27.196607 7, 0xFFFF, sum = 0
5979 09:28:27.196690 8, 0xFFFF, sum = 0
5980 09:28:27.200066 9, 0xFFFF, sum = 0
5981 09:28:27.200147 10, 0x0, sum = 1
5982 09:28:27.203002 11, 0x0, sum = 2
5983 09:28:27.203084 12, 0x0, sum = 3
5984 09:28:27.206637 13, 0x0, sum = 4
5985 09:28:27.206719 best_step = 11
5986 09:28:27.206782
5987 09:28:27.206841 ==
5988 09:28:27.210047 Dram Type= 6, Freq= 0, CH_1, rank 1
5989 09:28:27.216465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5990 09:28:27.216547 ==
5991 09:28:27.216611 RX Vref Scan: 0
5992 09:28:27.216670
5993 09:28:27.219805 RX Vref 0 -> 0, step: 1
5994 09:28:27.219886
5995 09:28:27.222881 RX Delay -61 -> 252, step: 4
5996 09:28:27.226606 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5997 09:28:27.232899 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
5998 09:28:27.236041 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5999 09:28:27.239645 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6000 09:28:27.242768 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6001 09:28:27.246524 iDelay=207, Bit 5, Center 112 (27 ~ 198) 172
6002 09:28:27.249391 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
6003 09:28:27.255941 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6004 09:28:27.259514 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6005 09:28:27.262429 iDelay=207, Bit 9, Center 86 (-1 ~ 174) 176
6006 09:28:27.265587 iDelay=207, Bit 10, Center 90 (-1 ~ 182) 184
6007 09:28:27.269206 iDelay=207, Bit 11, Center 86 (-1 ~ 174) 176
6008 09:28:27.276074 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6009 09:28:27.279223 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
6010 09:28:27.282107 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
6011 09:28:27.285676 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6012 09:28:27.285757 ==
6013 09:28:27.289100 Dram Type= 6, Freq= 0, CH_1, rank 1
6014 09:28:27.295476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6015 09:28:27.295628 ==
6016 09:28:27.295697 DQS Delay:
6017 09:28:27.298478 DQS0 = 0, DQS1 = 0
6018 09:28:27.298550 DQM Delay:
6019 09:28:27.302180 DQM0 = 102, DQM1 = 93
6020 09:28:27.302264 DQ Delay:
6021 09:28:27.305191 DQ0 =106, DQ1 =96, DQ2 =90, DQ3 =98
6022 09:28:27.308295 DQ4 =100, DQ5 =112, DQ6 =116, DQ7 =98
6023 09:28:27.311753 DQ8 =82, DQ9 =86, DQ10 =90, DQ11 =86
6024 09:28:27.315358 DQ12 =102, DQ13 =100, DQ14 =100, DQ15 =102
6025 09:28:27.315465
6026 09:28:27.315549
6027 09:28:27.321514 [DQSOSCAuto] RK1, (LSB)MR18= 0x701, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6028 09:28:27.325000 CH1 RK1: MR19=505, MR18=701
6029 09:28:27.331561 CH1_RK1: MR19=0x505, MR18=0x701, DQSOSC=419, MR23=63, INC=61, DEC=41
6030 09:28:27.334992 [RxdqsGatingPostProcess] freq 933
6031 09:28:27.341155 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6032 09:28:27.344569 best DQS0 dly(2T, 0.5T) = (0, 10)
6033 09:28:27.347705 best DQS1 dly(2T, 0.5T) = (0, 10)
6034 09:28:27.351308 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6035 09:28:27.354546 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6036 09:28:27.354630 best DQS0 dly(2T, 0.5T) = (0, 10)
6037 09:28:27.358167 best DQS1 dly(2T, 0.5T) = (0, 10)
6038 09:28:27.361202 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6039 09:28:27.364177 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6040 09:28:27.367902 Pre-setting of DQS Precalculation
6041 09:28:27.374003 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6042 09:28:27.380783 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6043 09:28:27.387625 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6044 09:28:27.387709
6045 09:28:27.387792
6046 09:28:27.390663 [Calibration Summary] 1866 Mbps
6047 09:28:27.393597 CH 0, Rank 0
6048 09:28:27.393686 SW Impedance : PASS
6049 09:28:27.397131 DUTY Scan : NO K
6050 09:28:27.400358 ZQ Calibration : PASS
6051 09:28:27.400441 Jitter Meter : NO K
6052 09:28:27.403636 CBT Training : PASS
6053 09:28:27.403719 Write leveling : PASS
6054 09:28:27.407004 RX DQS gating : PASS
6055 09:28:27.410362 RX DQ/DQS(RDDQC) : PASS
6056 09:28:27.410444 TX DQ/DQS : PASS
6057 09:28:27.413290 RX DATLAT : PASS
6058 09:28:27.417115 RX DQ/DQS(Engine): PASS
6059 09:28:27.417196 TX OE : NO K
6060 09:28:27.420370 All Pass.
6061 09:28:27.420451
6062 09:28:27.420515 CH 0, Rank 1
6063 09:28:27.423631 SW Impedance : PASS
6064 09:28:27.423712 DUTY Scan : NO K
6065 09:28:27.426526 ZQ Calibration : PASS
6066 09:28:27.430094 Jitter Meter : NO K
6067 09:28:27.430236 CBT Training : PASS
6068 09:28:27.433523 Write leveling : PASS
6069 09:28:27.437096 RX DQS gating : PASS
6070 09:28:27.437178 RX DQ/DQS(RDDQC) : PASS
6071 09:28:27.440098 TX DQ/DQS : PASS
6072 09:28:27.443073 RX DATLAT : PASS
6073 09:28:27.443154 RX DQ/DQS(Engine): PASS
6074 09:28:27.446912 TX OE : NO K
6075 09:28:27.446994 All Pass.
6076 09:28:27.447057
6077 09:28:27.450331 CH 1, Rank 0
6078 09:28:27.450411 SW Impedance : PASS
6079 09:28:27.453469 DUTY Scan : NO K
6080 09:28:27.456511 ZQ Calibration : PASS
6081 09:28:27.456593 Jitter Meter : NO K
6082 09:28:27.460192 CBT Training : PASS
6083 09:28:27.463019 Write leveling : PASS
6084 09:28:27.463099 RX DQS gating : PASS
6085 09:28:27.466606 RX DQ/DQS(RDDQC) : PASS
6086 09:28:27.466687 TX DQ/DQS : PASS
6087 09:28:27.470355 RX DATLAT : PASS
6088 09:28:27.473371 RX DQ/DQS(Engine): PASS
6089 09:28:27.473452 TX OE : NO K
6090 09:28:27.476512 All Pass.
6091 09:28:27.476592
6092 09:28:27.476656 CH 1, Rank 1
6093 09:28:27.479890 SW Impedance : PASS
6094 09:28:27.479971 DUTY Scan : NO K
6095 09:28:27.483145 ZQ Calibration : PASS
6096 09:28:27.486137 Jitter Meter : NO K
6097 09:28:27.486257 CBT Training : PASS
6098 09:28:27.489904 Write leveling : PASS
6099 09:28:27.492856 RX DQS gating : PASS
6100 09:28:27.492937 RX DQ/DQS(RDDQC) : PASS
6101 09:28:27.496061 TX DQ/DQS : PASS
6102 09:28:27.499660 RX DATLAT : PASS
6103 09:28:27.499741 RX DQ/DQS(Engine): PASS
6104 09:28:27.502643 TX OE : NO K
6105 09:28:27.502724 All Pass.
6106 09:28:27.502786
6107 09:28:27.506353 DramC Write-DBI off
6108 09:28:27.509317 PER_BANK_REFRESH: Hybrid Mode
6109 09:28:27.509398 TX_TRACKING: ON
6110 09:28:27.519391 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6111 09:28:27.522350 [FAST_K] Save calibration result to emmc
6112 09:28:27.525873 dramc_set_vcore_voltage set vcore to 650000
6113 09:28:27.529171 Read voltage for 400, 6
6114 09:28:27.529252 Vio18 = 0
6115 09:28:27.529316 Vcore = 650000
6116 09:28:27.532426 Vdram = 0
6117 09:28:27.532506 Vddq = 0
6118 09:28:27.532569 Vmddr = 0
6119 09:28:27.539051 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6120 09:28:27.542745 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6121 09:28:27.545807 MEM_TYPE=3, freq_sel=20
6122 09:28:27.549385 sv_algorithm_assistance_LP4_800
6123 09:28:27.552373 ============ PULL DRAM RESETB DOWN ============
6124 09:28:27.555712 ========== PULL DRAM RESETB DOWN end =========
6125 09:28:27.562118 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6126 09:28:27.565792 ===================================
6127 09:28:27.568708 LPDDR4 DRAM CONFIGURATION
6128 09:28:27.572219 ===================================
6129 09:28:27.572301 EX_ROW_EN[0] = 0x0
6130 09:28:27.575623 EX_ROW_EN[1] = 0x0
6131 09:28:27.575704 LP4Y_EN = 0x0
6132 09:28:27.579052 WORK_FSP = 0x0
6133 09:28:27.579133 WL = 0x2
6134 09:28:27.582337 RL = 0x2
6135 09:28:27.582418 BL = 0x2
6136 09:28:27.585253 RPST = 0x0
6137 09:28:27.585334 RD_PRE = 0x0
6138 09:28:27.588452 WR_PRE = 0x1
6139 09:28:27.588533 WR_PST = 0x0
6140 09:28:27.591964 DBI_WR = 0x0
6141 09:28:27.592045 DBI_RD = 0x0
6142 09:28:27.595063 OTF = 0x1
6143 09:28:27.598640 ===================================
6144 09:28:27.601736 ===================================
6145 09:28:27.601817 ANA top config
6146 09:28:27.605461 ===================================
6147 09:28:27.608560 DLL_ASYNC_EN = 0
6148 09:28:27.611690 ALL_SLAVE_EN = 1
6149 09:28:27.614733 NEW_RANK_MODE = 1
6150 09:28:27.618506 DLL_IDLE_MODE = 1
6151 09:28:27.618587 LP45_APHY_COMB_EN = 1
6152 09:28:27.621498 TX_ODT_DIS = 1
6153 09:28:27.625182 NEW_8X_MODE = 1
6154 09:28:27.628137 ===================================
6155 09:28:27.631414 ===================================
6156 09:28:27.634694 data_rate = 800
6157 09:28:27.638119 CKR = 1
6158 09:28:27.640949 DQ_P2S_RATIO = 4
6159 09:28:27.644723 ===================================
6160 09:28:27.644805 CA_P2S_RATIO = 4
6161 09:28:27.648057 DQ_CA_OPEN = 0
6162 09:28:27.650901 DQ_SEMI_OPEN = 1
6163 09:28:27.654719 CA_SEMI_OPEN = 1
6164 09:28:27.657566 CA_FULL_RATE = 0
6165 09:28:27.660843 DQ_CKDIV4_EN = 0
6166 09:28:27.660924 CA_CKDIV4_EN = 1
6167 09:28:27.664383 CA_PREDIV_EN = 0
6168 09:28:27.667580 PH8_DLY = 0
6169 09:28:27.670830 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6170 09:28:27.673930 DQ_AAMCK_DIV = 0
6171 09:28:27.677529 CA_AAMCK_DIV = 0
6172 09:28:27.677610 CA_ADMCK_DIV = 4
6173 09:28:27.680506 DQ_TRACK_CA_EN = 0
6174 09:28:27.684291 CA_PICK = 800
6175 09:28:27.687344 CA_MCKIO = 400
6176 09:28:27.690399 MCKIO_SEMI = 400
6177 09:28:27.694056 PLL_FREQ = 3016
6178 09:28:27.697005 DQ_UI_PI_RATIO = 32
6179 09:28:27.700697 CA_UI_PI_RATIO = 32
6180 09:28:27.703713 ===================================
6181 09:28:27.706737 ===================================
6182 09:28:27.706819 memory_type:LPDDR4
6183 09:28:27.710395 GP_NUM : 10
6184 09:28:27.713588 SRAM_EN : 1
6185 09:28:27.713695 MD32_EN : 0
6186 09:28:27.716779 ===================================
6187 09:28:27.720582 [ANA_INIT] >>>>>>>>>>>>>>
6188 09:28:27.723426 <<<<<< [CONFIGURE PHASE]: ANA_TX
6189 09:28:27.726652 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6190 09:28:27.730182 ===================================
6191 09:28:27.733240 data_rate = 800,PCW = 0X7400
6192 09:28:27.736723 ===================================
6193 09:28:27.740079 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6194 09:28:27.743494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6195 09:28:27.756388 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6196 09:28:27.759869 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6197 09:28:27.762755 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6198 09:28:27.766094 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6199 09:28:27.769295 [ANA_INIT] flow start
6200 09:28:27.772858 [ANA_INIT] PLL >>>>>>>>
6201 09:28:27.772932 [ANA_INIT] PLL <<<<<<<<
6202 09:28:27.776338 [ANA_INIT] MIDPI >>>>>>>>
6203 09:28:27.779195 [ANA_INIT] MIDPI <<<<<<<<
6204 09:28:27.779287 [ANA_INIT] DLL >>>>>>>>
6205 09:28:27.782748 [ANA_INIT] flow end
6206 09:28:27.786681 ============ LP4 DIFF to SE enter ============
6207 09:28:27.789542 ============ LP4 DIFF to SE exit ============
6208 09:28:27.792703 [ANA_INIT] <<<<<<<<<<<<<
6209 09:28:27.795890 [Flow] Enable top DCM control >>>>>
6210 09:28:27.799694 [Flow] Enable top DCM control <<<<<
6211 09:28:27.802663 Enable DLL master slave shuffle
6212 09:28:27.809403 ==============================================================
6213 09:28:27.809566 Gating Mode config
6214 09:28:27.816212 ==============================================================
6215 09:28:27.819103 Config description:
6216 09:28:27.825913 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6217 09:28:27.835336 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6218 09:28:27.839064 SELPH_MODE 0: By rank 1: By Phase
6219 09:28:27.845581 ==============================================================
6220 09:28:27.848481 GAT_TRACK_EN = 0
6221 09:28:27.848604 RX_GATING_MODE = 2
6222 09:28:27.852066 RX_GATING_TRACK_MODE = 2
6223 09:28:27.855005 SELPH_MODE = 1
6224 09:28:27.858781 PICG_EARLY_EN = 1
6225 09:28:27.862106 VALID_LAT_VALUE = 1
6226 09:28:27.868698 ==============================================================
6227 09:28:27.871937 Enter into Gating configuration >>>>
6228 09:28:27.875517 Exit from Gating configuration <<<<
6229 09:28:27.878743 Enter into DVFS_PRE_config >>>>>
6230 09:28:27.888347 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6231 09:28:27.891676 Exit from DVFS_PRE_config <<<<<
6232 09:28:27.895306 Enter into PICG configuration >>>>
6233 09:28:27.898269 Exit from PICG configuration <<<<
6234 09:28:27.901342 [RX_INPUT] configuration >>>>>
6235 09:28:27.905327 [RX_INPUT] configuration <<<<<
6236 09:28:27.908590 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6237 09:28:27.914892 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6238 09:28:27.921491 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6239 09:28:27.928506 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6240 09:28:27.934880 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6241 09:28:27.938036 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6242 09:28:27.944824 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6243 09:28:27.947754 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6244 09:28:27.951144 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6245 09:28:27.954708 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6246 09:28:27.960872 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6247 09:28:27.964242 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6248 09:28:27.967744 ===================================
6249 09:28:27.970951 LPDDR4 DRAM CONFIGURATION
6250 09:28:27.974575 ===================================
6251 09:28:27.974996 EX_ROW_EN[0] = 0x0
6252 09:28:27.977472 EX_ROW_EN[1] = 0x0
6253 09:28:27.977895 LP4Y_EN = 0x0
6254 09:28:27.980559 WORK_FSP = 0x0
6255 09:28:27.980973 WL = 0x2
6256 09:28:27.984225 RL = 0x2
6257 09:28:27.984640 BL = 0x2
6258 09:28:27.987339 RPST = 0x0
6259 09:28:27.990998 RD_PRE = 0x0
6260 09:28:27.991417 WR_PRE = 0x1
6261 09:28:27.994001 WR_PST = 0x0
6262 09:28:27.994439 DBI_WR = 0x0
6263 09:28:27.997679 DBI_RD = 0x0
6264 09:28:27.998096 OTF = 0x1
6265 09:28:28.000342 ===================================
6266 09:28:28.004116 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6267 09:28:28.010438 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6268 09:28:28.013699 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6269 09:28:28.017327 ===================================
6270 09:28:28.020184 LPDDR4 DRAM CONFIGURATION
6271 09:28:28.024006 ===================================
6272 09:28:28.024428 EX_ROW_EN[0] = 0x10
6273 09:28:28.026733 EX_ROW_EN[1] = 0x0
6274 09:28:28.027311 LP4Y_EN = 0x0
6275 09:28:28.030027 WORK_FSP = 0x0
6276 09:28:28.030489 WL = 0x2
6277 09:28:28.033468 RL = 0x2
6278 09:28:28.036583 BL = 0x2
6279 09:28:28.037102 RPST = 0x0
6280 09:28:28.040257 RD_PRE = 0x0
6281 09:28:28.040677 WR_PRE = 0x1
6282 09:28:28.043312 WR_PST = 0x0
6283 09:28:28.043730 DBI_WR = 0x0
6284 09:28:28.046812 DBI_RD = 0x0
6285 09:28:28.047365 OTF = 0x1
6286 09:28:28.049925 ===================================
6287 09:28:28.056721 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6288 09:28:28.060807 nWR fixed to 30
6289 09:28:28.064209 [ModeRegInit_LP4] CH0 RK0
6290 09:28:28.064627 [ModeRegInit_LP4] CH0 RK1
6291 09:28:28.067304 [ModeRegInit_LP4] CH1 RK0
6292 09:28:28.070756 [ModeRegInit_LP4] CH1 RK1
6293 09:28:28.071372 match AC timing 19
6294 09:28:28.077107 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6295 09:28:28.080553 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6296 09:28:28.083493 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6297 09:28:28.090356 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6298 09:28:28.093928 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6299 09:28:28.094393 ==
6300 09:28:28.096960 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 09:28:28.099979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 09:28:28.100420 ==
6303 09:28:28.106797 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6304 09:28:28.113066 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6305 09:28:28.116457 [CA 0] Center 36 (8~64) winsize 57
6306 09:28:28.119884 [CA 1] Center 36 (8~64) winsize 57
6307 09:28:28.123024 [CA 2] Center 36 (8~64) winsize 57
6308 09:28:28.126592 [CA 3] Center 36 (8~64) winsize 57
6309 09:28:28.129624 [CA 4] Center 36 (8~64) winsize 57
6310 09:28:28.133149 [CA 5] Center 36 (8~64) winsize 57
6311 09:28:28.133567
6312 09:28:28.136039 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6313 09:28:28.136455
6314 09:28:28.139886 [CATrainingPosCal] consider 1 rank data
6315 09:28:28.142854 u2DelayCellTimex100 = 270/100 ps
6316 09:28:28.146537 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 09:28:28.149622 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 09:28:28.152611 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 09:28:28.156074 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 09:28:28.159066 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 09:28:28.162654 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 09:28:28.163072
6323 09:28:28.169038 CA PerBit enable=1, Macro0, CA PI delay=36
6324 09:28:28.169460
6325 09:28:28.169789 [CBTSetCACLKResult] CA Dly = 36
6326 09:28:28.172498 CS Dly: 1 (0~32)
6327 09:28:28.173228 ==
6328 09:28:28.175998 Dram Type= 6, Freq= 0, CH_0, rank 1
6329 09:28:28.178918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 09:28:28.179442 ==
6331 09:28:28.185949 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6332 09:28:28.192394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6333 09:28:28.196208 [CA 0] Center 36 (8~64) winsize 57
6334 09:28:28.199225 [CA 1] Center 36 (8~64) winsize 57
6335 09:28:28.202193 [CA 2] Center 36 (8~64) winsize 57
6336 09:28:28.205728 [CA 3] Center 36 (8~64) winsize 57
6337 09:28:28.206148 [CA 4] Center 36 (8~64) winsize 57
6338 09:28:28.208873 [CA 5] Center 36 (8~64) winsize 57
6339 09:28:28.209423
6340 09:28:28.215539 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6341 09:28:28.215962
6342 09:28:28.219293 [CATrainingPosCal] consider 2 rank data
6343 09:28:28.222263 u2DelayCellTimex100 = 270/100 ps
6344 09:28:28.225809 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6345 09:28:28.229141 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 09:28:28.232361 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 09:28:28.235540 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 09:28:28.238496 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 09:28:28.242483 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 09:28:28.242910
6351 09:28:28.245191 CA PerBit enable=1, Macro0, CA PI delay=36
6352 09:28:28.245619
6353 09:28:28.248520 [CBTSetCACLKResult] CA Dly = 36
6354 09:28:28.252058 CS Dly: 1 (0~32)
6355 09:28:28.252566
6356 09:28:28.255469 ----->DramcWriteLeveling(PI) begin...
6357 09:28:28.255917 ==
6358 09:28:28.258463 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 09:28:28.261989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 09:28:28.262470 ==
6361 09:28:28.265134 Write leveling (Byte 0): 40 => 8
6362 09:28:28.268351 Write leveling (Byte 1): 32 => 0
6363 09:28:28.271911 DramcWriteLeveling(PI) end<-----
6364 09:28:28.272321
6365 09:28:28.272640 ==
6366 09:28:28.275159 Dram Type= 6, Freq= 0, CH_0, rank 0
6367 09:28:28.278559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6368 09:28:28.279060 ==
6369 09:28:28.281378 [Gating] SW mode calibration
6370 09:28:28.288286 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6371 09:28:28.294824 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6372 09:28:28.298241 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6373 09:28:28.301982 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6374 09:28:28.308299 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6375 09:28:28.311759 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6376 09:28:28.314832 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6377 09:28:28.321625 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6378 09:28:28.325002 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6379 09:28:28.327842 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6380 09:28:28.334459 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6381 09:28:28.338210 Total UI for P1: 0, mck2ui 16
6382 09:28:28.341272 best dqsien dly found for B0: ( 0, 14, 24)
6383 09:28:28.344479 Total UI for P1: 0, mck2ui 16
6384 09:28:28.347784 best dqsien dly found for B1: ( 0, 14, 24)
6385 09:28:28.351281 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6386 09:28:28.354737 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6387 09:28:28.355230
6388 09:28:28.358265 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6389 09:28:28.361312 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6390 09:28:28.364616 [Gating] SW calibration Done
6391 09:28:28.365140 ==
6392 09:28:28.367641 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 09:28:28.371240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 09:28:28.371657 ==
6395 09:28:28.375154 RX Vref Scan: 0
6396 09:28:28.375661
6397 09:28:28.377643 RX Vref 0 -> 0, step: 1
6398 09:28:28.378054
6399 09:28:28.378412 RX Delay -410 -> 252, step: 16
6400 09:28:28.384379 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6401 09:28:28.387987 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6402 09:28:28.391309 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6403 09:28:28.398092 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6404 09:28:28.401528 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6405 09:28:28.404160 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6406 09:28:28.407683 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6407 09:28:28.414278 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6408 09:28:28.417267 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6409 09:28:28.421006 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6410 09:28:28.424102 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6411 09:28:28.430802 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6412 09:28:28.433895 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6413 09:28:28.437058 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6414 09:28:28.440863 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6415 09:28:28.447464 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6416 09:28:28.447885 ==
6417 09:28:28.450424 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 09:28:28.453561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 09:28:28.453977 ==
6420 09:28:28.454425 DQS Delay:
6421 09:28:28.457420 DQS0 = 43, DQS1 = 59
6422 09:28:28.457934 DQM Delay:
6423 09:28:28.460408 DQM0 = 9, DQM1 = 12
6424 09:28:28.460820 DQ Delay:
6425 09:28:28.463769 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6426 09:28:28.466895 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6427 09:28:28.470626 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6428 09:28:28.474061 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6429 09:28:28.474653
6430 09:28:28.474985
6431 09:28:28.475289 ==
6432 09:28:28.477151 Dram Type= 6, Freq= 0, CH_0, rank 0
6433 09:28:28.480234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6434 09:28:28.480655 ==
6435 09:28:28.480987
6436 09:28:28.483255
6437 09:28:28.483739 TX Vref Scan disable
6438 09:28:28.486728 == TX Byte 0 ==
6439 09:28:28.490055 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6440 09:28:28.493448 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6441 09:28:28.496572 == TX Byte 1 ==
6442 09:28:28.500511 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6443 09:28:28.503155 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6444 09:28:28.503614 ==
6445 09:28:28.506742 Dram Type= 6, Freq= 0, CH_0, rank 0
6446 09:28:28.509937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 09:28:28.513377 ==
6448 09:28:28.513875
6449 09:28:28.514272
6450 09:28:28.514603 TX Vref Scan disable
6451 09:28:28.516368 == TX Byte 0 ==
6452 09:28:28.520067 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6453 09:28:28.523130 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6454 09:28:28.526140 == TX Byte 1 ==
6455 09:28:28.529855 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6456 09:28:28.532787 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6457 09:28:28.533274
6458 09:28:28.536645 [DATLAT]
6459 09:28:28.537155 Freq=400, CH0 RK0
6460 09:28:28.537485
6461 09:28:28.539499 DATLAT Default: 0xf
6462 09:28:28.539909 0, 0xFFFF, sum = 0
6463 09:28:28.543091 1, 0xFFFF, sum = 0
6464 09:28:28.543610 2, 0xFFFF, sum = 0
6465 09:28:28.546011 3, 0xFFFF, sum = 0
6466 09:28:28.546489 4, 0xFFFF, sum = 0
6467 09:28:28.549184 5, 0xFFFF, sum = 0
6468 09:28:28.549598 6, 0xFFFF, sum = 0
6469 09:28:28.552770 7, 0xFFFF, sum = 0
6470 09:28:28.553185 8, 0xFFFF, sum = 0
6471 09:28:28.555719 9, 0xFFFF, sum = 0
6472 09:28:28.559367 10, 0xFFFF, sum = 0
6473 09:28:28.559784 11, 0xFFFF, sum = 0
6474 09:28:28.562555 12, 0xFFFF, sum = 0
6475 09:28:28.562971 13, 0x0, sum = 1
6476 09:28:28.565605 14, 0x0, sum = 2
6477 09:28:28.566020 15, 0x0, sum = 3
6478 09:28:28.569257 16, 0x0, sum = 4
6479 09:28:28.569669 best_step = 14
6480 09:28:28.569988
6481 09:28:28.570338 ==
6482 09:28:28.572568 Dram Type= 6, Freq= 0, CH_0, rank 0
6483 09:28:28.575624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 09:28:28.576041 ==
6485 09:28:28.579246 RX Vref Scan: 1
6486 09:28:28.579656
6487 09:28:28.582257 RX Vref 0 -> 0, step: 1
6488 09:28:28.582666
6489 09:28:28.582986 RX Delay -359 -> 252, step: 8
6490 09:28:28.585467
6491 09:28:28.585914 Set Vref, RX VrefLevel [Byte0]: 60
6492 09:28:28.588618 [Byte1]: 58
6493 09:28:28.594499
6494 09:28:28.595087 Final RX Vref Byte 0 = 60 to rank0
6495 09:28:28.597794 Final RX Vref Byte 1 = 58 to rank0
6496 09:28:28.601213 Final RX Vref Byte 0 = 60 to rank1
6497 09:28:28.604258 Final RX Vref Byte 1 = 58 to rank1==
6498 09:28:28.607706 Dram Type= 6, Freq= 0, CH_0, rank 0
6499 09:28:28.614056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 09:28:28.614652 ==
6501 09:28:28.615131 DQS Delay:
6502 09:28:28.617538 DQS0 = 48, DQS1 = 64
6503 09:28:28.617946 DQM Delay:
6504 09:28:28.618307 DQM0 = 11, DQM1 = 14
6505 09:28:28.621096 DQ Delay:
6506 09:28:28.624500 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6507 09:28:28.627727 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6508 09:28:28.628186 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6509 09:28:28.630767 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6510 09:28:28.634003
6511 09:28:28.634523
6512 09:28:28.640565 [DQSOSCAuto] RK0, (LSB)MR18= 0xc284, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 385 ps
6513 09:28:28.644152 CH0 RK0: MR19=C0C, MR18=C284
6514 09:28:28.650864 CH0_RK0: MR19=0xC0C, MR18=0xC284, DQSOSC=385, MR23=63, INC=398, DEC=265
6515 09:28:28.651275 ==
6516 09:28:28.654343 Dram Type= 6, Freq= 0, CH_0, rank 1
6517 09:28:28.657176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 09:28:28.657592 ==
6519 09:28:28.660810 [Gating] SW mode calibration
6520 09:28:28.667553 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6521 09:28:28.673613 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6522 09:28:28.677339 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6523 09:28:28.680554 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6524 09:28:28.686633 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6525 09:28:28.690234 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6526 09:28:28.693136 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6527 09:28:28.699793 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6528 09:28:28.703304 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6529 09:28:28.707110 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 09:28:28.713117 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6531 09:28:28.716611 Total UI for P1: 0, mck2ui 16
6532 09:28:28.720253 best dqsien dly found for B0: ( 0, 14, 24)
6533 09:28:28.720684 Total UI for P1: 0, mck2ui 16
6534 09:28:28.726473 best dqsien dly found for B1: ( 0, 14, 24)
6535 09:28:28.729605 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6536 09:28:28.732843 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6537 09:28:28.733282
6538 09:28:28.736535 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6539 09:28:28.739667 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6540 09:28:28.743089 [Gating] SW calibration Done
6541 09:28:28.743529 ==
6542 09:28:28.746130 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 09:28:28.749711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 09:28:28.750299 ==
6545 09:28:28.752696 RX Vref Scan: 0
6546 09:28:28.753235
6547 09:28:28.753697 RX Vref 0 -> 0, step: 1
6548 09:28:28.756397
6549 09:28:28.756882 RX Delay -410 -> 252, step: 16
6550 09:28:28.762776 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6551 09:28:28.766288 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6552 09:28:28.769608 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6553 09:28:28.773122 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6554 09:28:28.779329 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6555 09:28:28.782501 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6556 09:28:28.786190 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6557 09:28:28.789308 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6558 09:28:28.796088 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6559 09:28:28.799434 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6560 09:28:28.802711 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6561 09:28:28.809289 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6562 09:28:28.812286 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6563 09:28:28.815648 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6564 09:28:28.819019 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6565 09:28:28.825670 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6566 09:28:28.826084 ==
6567 09:28:28.828746 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 09:28:28.832466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 09:28:28.832884 ==
6570 09:28:28.833206 DQS Delay:
6571 09:28:28.835273 DQS0 = 43, DQS1 = 59
6572 09:28:28.835685 DQM Delay:
6573 09:28:28.838702 DQM0 = 9, DQM1 = 13
6574 09:28:28.839236 DQ Delay:
6575 09:28:28.842303 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6576 09:28:28.845150 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6577 09:28:28.848696 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6578 09:28:28.852109 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =16
6579 09:28:28.852637
6580 09:28:28.852964
6581 09:28:28.853260 ==
6582 09:28:28.855585 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 09:28:28.858585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 09:28:28.859093 ==
6585 09:28:28.859416
6586 09:28:28.859713
6587 09:28:28.861560 TX Vref Scan disable
6588 09:28:28.865483 == TX Byte 0 ==
6589 09:28:28.868446 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6590 09:28:28.871900 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6591 09:28:28.875060 == TX Byte 1 ==
6592 09:28:28.878090 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6593 09:28:28.881779 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6594 09:28:28.882226 ==
6595 09:28:28.884705 Dram Type= 6, Freq= 0, CH_0, rank 1
6596 09:28:28.887817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 09:28:28.891367 ==
6598 09:28:28.891783
6599 09:28:28.892106
6600 09:28:28.892405 TX Vref Scan disable
6601 09:28:28.894576 == TX Byte 0 ==
6602 09:28:28.897996 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6603 09:28:28.900861 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6604 09:28:28.904341 == TX Byte 1 ==
6605 09:28:28.907795 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6606 09:28:28.911567 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6607 09:28:28.911982
6608 09:28:28.914210 [DATLAT]
6609 09:28:28.914782 Freq=400, CH0 RK1
6610 09:28:28.915215
6611 09:28:28.917652 DATLAT Default: 0xe
6612 09:28:28.918082 0, 0xFFFF, sum = 0
6613 09:28:28.920999 1, 0xFFFF, sum = 0
6614 09:28:28.921450 2, 0xFFFF, sum = 0
6615 09:28:28.924188 3, 0xFFFF, sum = 0
6616 09:28:28.924621 4, 0xFFFF, sum = 0
6617 09:28:28.927633 5, 0xFFFF, sum = 0
6618 09:28:28.928066 6, 0xFFFF, sum = 0
6619 09:28:28.931175 7, 0xFFFF, sum = 0
6620 09:28:28.931608 8, 0xFFFF, sum = 0
6621 09:28:28.934115 9, 0xFFFF, sum = 0
6622 09:28:28.934587 10, 0xFFFF, sum = 0
6623 09:28:28.937247 11, 0xFFFF, sum = 0
6624 09:28:28.940755 12, 0xFFFF, sum = 0
6625 09:28:28.941189 13, 0x0, sum = 1
6626 09:28:28.941621 14, 0x0, sum = 2
6627 09:28:28.944020 15, 0x0, sum = 3
6628 09:28:28.944453 16, 0x0, sum = 4
6629 09:28:28.947009 best_step = 14
6630 09:28:28.947438
6631 09:28:28.947869 ==
6632 09:28:28.950254 Dram Type= 6, Freq= 0, CH_0, rank 1
6633 09:28:28.953732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 09:28:28.954209 ==
6635 09:28:28.957300 RX Vref Scan: 0
6636 09:28:28.957726
6637 09:28:28.958154 RX Vref 0 -> 0, step: 1
6638 09:28:28.958607
6639 09:28:28.960624 RX Delay -359 -> 252, step: 8
6640 09:28:28.968529 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6641 09:28:28.972182 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6642 09:28:28.975750 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6643 09:28:28.981912 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6644 09:28:28.984989 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6645 09:28:28.988658 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6646 09:28:28.991684 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6647 09:28:28.998469 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6648 09:28:29.001566 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6649 09:28:29.005181 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6650 09:28:29.008601 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6651 09:28:29.014668 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6652 09:28:29.018100 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6653 09:28:29.021597 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6654 09:28:29.024532 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6655 09:28:29.031426 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6656 09:28:29.031846 ==
6657 09:28:29.034905 Dram Type= 6, Freq= 0, CH_0, rank 1
6658 09:28:29.037592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 09:28:29.038031 ==
6660 09:28:29.041185 DQS Delay:
6661 09:28:29.041624 DQS0 = 44, DQS1 = 60
6662 09:28:29.041947 DQM Delay:
6663 09:28:29.044342 DQM0 = 7, DQM1 = 14
6664 09:28:29.044751 DQ Delay:
6665 09:28:29.047925 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6666 09:28:29.050886 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6667 09:28:29.054488 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =4
6668 09:28:29.057786 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6669 09:28:29.058277
6670 09:28:29.058607
6671 09:28:29.064310 [DQSOSCAuto] RK1, (LSB)MR18= 0xb03e, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 387 ps
6672 09:28:29.067442 CH0 RK1: MR19=C0C, MR18=B03E
6673 09:28:29.074122 CH0_RK1: MR19=0xC0C, MR18=0xB03E, DQSOSC=387, MR23=63, INC=394, DEC=262
6674 09:28:29.077336 [RxdqsGatingPostProcess] freq 400
6675 09:28:29.084514 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6676 09:28:29.087429 best DQS0 dly(2T, 0.5T) = (0, 10)
6677 09:28:29.090544 best DQS1 dly(2T, 0.5T) = (0, 10)
6678 09:28:29.094264 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6679 09:28:29.097375 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6680 09:28:29.097895 best DQS0 dly(2T, 0.5T) = (0, 10)
6681 09:28:29.101163 best DQS1 dly(2T, 0.5T) = (0, 10)
6682 09:28:29.104115 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6683 09:28:29.107884 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6684 09:28:29.110557 Pre-setting of DQS Precalculation
6685 09:28:29.117052 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6686 09:28:29.117474 ==
6687 09:28:29.120680 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 09:28:29.123942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 09:28:29.124394 ==
6690 09:28:29.130829 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6691 09:28:29.137761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6692 09:28:29.140574 [CA 0] Center 36 (8~64) winsize 57
6693 09:28:29.141137 [CA 1] Center 36 (8~64) winsize 57
6694 09:28:29.143709 [CA 2] Center 36 (8~64) winsize 57
6695 09:28:29.146989 [CA 3] Center 36 (8~64) winsize 57
6696 09:28:29.150813 [CA 4] Center 36 (8~64) winsize 57
6697 09:28:29.153511 [CA 5] Center 36 (8~64) winsize 57
6698 09:28:29.153959
6699 09:28:29.156603 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6700 09:28:29.157012
6701 09:28:29.163264 [CATrainingPosCal] consider 1 rank data
6702 09:28:29.163681 u2DelayCellTimex100 = 270/100 ps
6703 09:28:29.170004 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 09:28:29.173803 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 09:28:29.176419 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 09:28:29.180220 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 09:28:29.183518 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 09:28:29.186740 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 09:28:29.187359
6710 09:28:29.189807 CA PerBit enable=1, Macro0, CA PI delay=36
6711 09:28:29.190295
6712 09:28:29.193265 [CBTSetCACLKResult] CA Dly = 36
6713 09:28:29.196803 CS Dly: 1 (0~32)
6714 09:28:29.197365 ==
6715 09:28:29.199787 Dram Type= 6, Freq= 0, CH_1, rank 1
6716 09:28:29.203272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 09:28:29.203742 ==
6718 09:28:29.209516 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6719 09:28:29.212968 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6720 09:28:29.216347 [CA 0] Center 36 (8~64) winsize 57
6721 09:28:29.219249 [CA 1] Center 36 (8~64) winsize 57
6722 09:28:29.222905 [CA 2] Center 36 (8~64) winsize 57
6723 09:28:29.225925 [CA 3] Center 36 (8~64) winsize 57
6724 09:28:29.229666 [CA 4] Center 36 (8~64) winsize 57
6725 09:28:29.232412 [CA 5] Center 36 (8~64) winsize 57
6726 09:28:29.232865
6727 09:28:29.235583 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6728 09:28:29.236061
6729 09:28:29.239045 [CATrainingPosCal] consider 2 rank data
6730 09:28:29.242920 u2DelayCellTimex100 = 270/100 ps
6731 09:28:29.246063 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 09:28:29.252433 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 09:28:29.255597 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 09:28:29.258893 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 09:28:29.262567 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 09:28:29.265635 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 09:28:29.266240
6738 09:28:29.269143 CA PerBit enable=1, Macro0, CA PI delay=36
6739 09:28:29.269566
6740 09:28:29.272109 [CBTSetCACLKResult] CA Dly = 36
6741 09:28:29.272498 CS Dly: 1 (0~32)
6742 09:28:29.275267
6743 09:28:29.279092 ----->DramcWriteLeveling(PI) begin...
6744 09:28:29.279809 ==
6745 09:28:29.282489 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 09:28:29.285735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 09:28:29.286204 ==
6748 09:28:29.288859 Write leveling (Byte 0): 40 => 8
6749 09:28:29.292344 Write leveling (Byte 1): 32 => 0
6750 09:28:29.295714 DramcWriteLeveling(PI) end<-----
6751 09:28:29.296170
6752 09:28:29.296492 ==
6753 09:28:29.298502 Dram Type= 6, Freq= 0, CH_1, rank 0
6754 09:28:29.301852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6755 09:28:29.302349 ==
6756 09:28:29.305521 [Gating] SW mode calibration
6757 09:28:29.311710 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6758 09:28:29.318586 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6759 09:28:29.321588 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6760 09:28:29.325194 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6761 09:28:29.331795 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6762 09:28:29.334968 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6763 09:28:29.338264 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6764 09:28:29.344891 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6765 09:28:29.348015 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6766 09:28:29.351632 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6767 09:28:29.358384 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6768 09:28:29.358794 Total UI for P1: 0, mck2ui 16
6769 09:28:29.365015 best dqsien dly found for B0: ( 0, 14, 24)
6770 09:28:29.365616 Total UI for P1: 0, mck2ui 16
6771 09:28:29.371325 best dqsien dly found for B1: ( 0, 14, 24)
6772 09:28:29.374666 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6773 09:28:29.377705 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6774 09:28:29.378139
6775 09:28:29.381298 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6776 09:28:29.384393 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6777 09:28:29.387836 [Gating] SW calibration Done
6778 09:28:29.388333 ==
6779 09:28:29.391003 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 09:28:29.394030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 09:28:29.394628 ==
6782 09:28:29.397573 RX Vref Scan: 0
6783 09:28:29.397939
6784 09:28:29.398371 RX Vref 0 -> 0, step: 1
6785 09:28:29.400537
6786 09:28:29.400941 RX Delay -410 -> 252, step: 16
6787 09:28:29.407519 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6788 09:28:29.410796 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6789 09:28:29.414385 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6790 09:28:29.417220 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6791 09:28:29.423807 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6792 09:28:29.427327 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6793 09:28:29.430842 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6794 09:28:29.434077 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6795 09:28:29.440441 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6796 09:28:29.444089 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6797 09:28:29.446991 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6798 09:28:29.453770 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6799 09:28:29.457387 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6800 09:28:29.460642 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6801 09:28:29.463521 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6802 09:28:29.470609 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6803 09:28:29.471137 ==
6804 09:28:29.473806 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 09:28:29.477182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 09:28:29.477694 ==
6807 09:28:29.478016 DQS Delay:
6808 09:28:29.480189 DQS0 = 43, DQS1 = 51
6809 09:28:29.480696 DQM Delay:
6810 09:28:29.483851 DQM0 = 12, DQM1 = 14
6811 09:28:29.484402 DQ Delay:
6812 09:28:29.486341 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6813 09:28:29.489942 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6814 09:28:29.493377 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6815 09:28:29.496625 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6816 09:28:29.497035
6817 09:28:29.497355
6818 09:28:29.497651 ==
6819 09:28:29.499919 Dram Type= 6, Freq= 0, CH_1, rank 0
6820 09:28:29.502820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6821 09:28:29.503233 ==
6822 09:28:29.503553
6823 09:28:29.503848
6824 09:28:29.506422 TX Vref Scan disable
6825 09:28:29.509983 == TX Byte 0 ==
6826 09:28:29.513255 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6827 09:28:29.516017 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6828 09:28:29.519770 == TX Byte 1 ==
6829 09:28:29.522624 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6830 09:28:29.526091 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6831 09:28:29.526687 ==
6832 09:28:29.529449 Dram Type= 6, Freq= 0, CH_1, rank 0
6833 09:28:29.533140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 09:28:29.536363 ==
6835 09:28:29.536772
6836 09:28:29.537090
6837 09:28:29.537385 TX Vref Scan disable
6838 09:28:29.539427 == TX Byte 0 ==
6839 09:28:29.542578 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6840 09:28:29.546150 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6841 09:28:29.549100 == TX Byte 1 ==
6842 09:28:29.552590 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6843 09:28:29.555784 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6844 09:28:29.556220
6845 09:28:29.559174 [DATLAT]
6846 09:28:29.559579 Freq=400, CH1 RK0
6847 09:28:29.559899
6848 09:28:29.562796 DATLAT Default: 0xf
6849 09:28:29.563232 0, 0xFFFF, sum = 0
6850 09:28:29.565748 1, 0xFFFF, sum = 0
6851 09:28:29.566206 2, 0xFFFF, sum = 0
6852 09:28:29.568935 3, 0xFFFF, sum = 0
6853 09:28:29.569351 4, 0xFFFF, sum = 0
6854 09:28:29.572605 5, 0xFFFF, sum = 0
6855 09:28:29.573136 6, 0xFFFF, sum = 0
6856 09:28:29.575904 7, 0xFFFF, sum = 0
6857 09:28:29.576446 8, 0xFFFF, sum = 0
6858 09:28:29.579424 9, 0xFFFF, sum = 0
6859 09:28:29.582263 10, 0xFFFF, sum = 0
6860 09:28:29.582729 11, 0xFFFF, sum = 0
6861 09:28:29.585618 12, 0xFFFF, sum = 0
6862 09:28:29.586092 13, 0x0, sum = 1
6863 09:28:29.588613 14, 0x0, sum = 2
6864 09:28:29.589072 15, 0x0, sum = 3
6865 09:28:29.592121 16, 0x0, sum = 4
6866 09:28:29.592579 best_step = 14
6867 09:28:29.592930
6868 09:28:29.593258 ==
6869 09:28:29.595090 Dram Type= 6, Freq= 0, CH_1, rank 0
6870 09:28:29.598710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 09:28:29.599124 ==
6872 09:28:29.601664 RX Vref Scan: 1
6873 09:28:29.602072
6874 09:28:29.605381 RX Vref 0 -> 0, step: 1
6875 09:28:29.605787
6876 09:28:29.606108 RX Delay -343 -> 252, step: 8
6877 09:28:29.608604
6878 09:28:29.609007 Set Vref, RX VrefLevel [Byte0]: 48
6879 09:28:29.611963 [Byte1]: 54
6880 09:28:29.616924
6881 09:28:29.617332 Final RX Vref Byte 0 = 48 to rank0
6882 09:28:29.620521 Final RX Vref Byte 1 = 54 to rank0
6883 09:28:29.623843 Final RX Vref Byte 0 = 48 to rank1
6884 09:28:29.627491 Final RX Vref Byte 1 = 54 to rank1==
6885 09:28:29.630241 Dram Type= 6, Freq= 0, CH_1, rank 0
6886 09:28:29.637430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 09:28:29.637944 ==
6888 09:28:29.638316 DQS Delay:
6889 09:28:29.640545 DQS0 = 44, DQS1 = 56
6890 09:28:29.641287 DQM Delay:
6891 09:28:29.641843 DQM0 = 8, DQM1 = 11
6892 09:28:29.643902 DQ Delay:
6893 09:28:29.646836 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6894 09:28:29.647289 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =4
6895 09:28:29.650030 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6896 09:28:29.653946 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6897 09:28:29.654567
6898 09:28:29.656757
6899 09:28:29.663680 [DQSOSCAuto] RK0, (LSB)MR18= 0x986e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6900 09:28:29.666719 CH1 RK0: MR19=C0C, MR18=986E
6901 09:28:29.673336 CH1_RK0: MR19=0xC0C, MR18=0x986E, DQSOSC=390, MR23=63, INC=388, DEC=258
6902 09:28:29.673908 ==
6903 09:28:29.676698 Dram Type= 6, Freq= 0, CH_1, rank 1
6904 09:28:29.680664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 09:28:29.681239 ==
6906 09:28:29.683426 [Gating] SW mode calibration
6907 09:28:29.689731 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6908 09:28:29.696530 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6909 09:28:29.700041 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6910 09:28:29.702968 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6911 09:28:29.710255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6912 09:28:29.713059 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6913 09:28:29.716584 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6914 09:28:29.722559 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6915 09:28:29.726210 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6916 09:28:29.729811 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6917 09:28:29.736345 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6918 09:28:29.736817 Total UI for P1: 0, mck2ui 16
6919 09:28:29.743012 best dqsien dly found for B0: ( 0, 14, 24)
6920 09:28:29.743469 Total UI for P1: 0, mck2ui 16
6921 09:28:29.749242 best dqsien dly found for B1: ( 0, 14, 24)
6922 09:28:29.752863 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6923 09:28:29.755875 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6924 09:28:29.756437
6925 09:28:29.758933 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6926 09:28:29.762542 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6927 09:28:29.765369 [Gating] SW calibration Done
6928 09:28:29.765819 ==
6929 09:28:29.769094 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 09:28:29.772635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 09:28:29.773187 ==
6932 09:28:29.775681 RX Vref Scan: 0
6933 09:28:29.776183
6934 09:28:29.776535 RX Vref 0 -> 0, step: 1
6935 09:28:29.779055
6936 09:28:29.779535 RX Delay -410 -> 252, step: 16
6937 09:28:29.785177 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6938 09:28:29.788806 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6939 09:28:29.791861 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6940 09:28:29.795407 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6941 09:28:29.801866 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6942 09:28:29.805350 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6943 09:28:29.808197 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6944 09:28:29.811561 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6945 09:28:29.818281 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6946 09:28:29.821512 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6947 09:28:29.824935 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6948 09:28:29.831903 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6949 09:28:29.834670 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6950 09:28:29.838130 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6951 09:28:29.841031 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6952 09:28:29.848033 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6953 09:28:29.848599 ==
6954 09:28:29.851418 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 09:28:29.854600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 09:28:29.855014 ==
6957 09:28:29.855333 DQS Delay:
6958 09:28:29.857964 DQS0 = 51, DQS1 = 51
6959 09:28:29.858461 DQM Delay:
6960 09:28:29.861178 DQM0 = 19, DQM1 = 14
6961 09:28:29.861732 DQ Delay:
6962 09:28:29.864472 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6963 09:28:29.867412 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6964 09:28:29.870769 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6965 09:28:29.873941 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6966 09:28:29.874529
6967 09:28:29.874987
6968 09:28:29.875422 ==
6969 09:28:29.877295 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 09:28:29.880873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 09:28:29.884154 ==
6972 09:28:29.884620
6973 09:28:29.884943
6974 09:28:29.885239 TX Vref Scan disable
6975 09:28:29.887240 == TX Byte 0 ==
6976 09:28:29.890921 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6977 09:28:29.893936 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6978 09:28:29.897470 == TX Byte 1 ==
6979 09:28:29.900322 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6980 09:28:29.904172 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6981 09:28:29.904616 ==
6982 09:28:29.906972 Dram Type= 6, Freq= 0, CH_1, rank 1
6983 09:28:29.913821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6984 09:28:29.914379 ==
6985 09:28:29.914713
6986 09:28:29.915061
6987 09:28:29.915354 TX Vref Scan disable
6988 09:28:29.916997 == TX Byte 0 ==
6989 09:28:29.920190 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6990 09:28:29.923752 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6991 09:28:29.926761 == TX Byte 1 ==
6992 09:28:29.930390 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6993 09:28:29.933765 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6994 09:28:29.934212
6995 09:28:29.936869 [DATLAT]
6996 09:28:29.937384 Freq=400, CH1 RK1
6997 09:28:29.937712
6998 09:28:29.940302 DATLAT Default: 0xe
6999 09:28:29.940812 0, 0xFFFF, sum = 0
7000 09:28:29.943288 1, 0xFFFF, sum = 0
7001 09:28:29.943703 2, 0xFFFF, sum = 0
7002 09:28:29.946903 3, 0xFFFF, sum = 0
7003 09:28:29.947319 4, 0xFFFF, sum = 0
7004 09:28:29.950125 5, 0xFFFF, sum = 0
7005 09:28:29.950565 6, 0xFFFF, sum = 0
7006 09:28:29.953985 7, 0xFFFF, sum = 0
7007 09:28:29.954546 8, 0xFFFF, sum = 0
7008 09:28:29.956846 9, 0xFFFF, sum = 0
7009 09:28:29.957375 10, 0xFFFF, sum = 0
7010 09:28:29.960099 11, 0xFFFF, sum = 0
7011 09:28:29.963582 12, 0xFFFF, sum = 0
7012 09:28:29.964003 13, 0x0, sum = 1
7013 09:28:29.966771 14, 0x0, sum = 2
7014 09:28:29.967184 15, 0x0, sum = 3
7015 09:28:29.967512 16, 0x0, sum = 4
7016 09:28:29.969866 best_step = 14
7017 09:28:29.970332
7018 09:28:29.970688 ==
7019 09:28:29.973306 Dram Type= 6, Freq= 0, CH_1, rank 1
7020 09:28:29.976709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7021 09:28:29.977237 ==
7022 09:28:29.979948 RX Vref Scan: 0
7023 09:28:29.980455
7024 09:28:29.983104 RX Vref 0 -> 0, step: 1
7025 09:28:29.983613
7026 09:28:29.983935 RX Delay -343 -> 252, step: 8
7027 09:28:29.991696 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7028 09:28:29.994865 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7029 09:28:29.998515 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7030 09:28:30.004744 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7031 09:28:30.008377 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7032 09:28:30.011330 iDelay=225, Bit 5, Center -28 (-271 ~ 216) 488
7033 09:28:30.014873 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7034 09:28:30.021221 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7035 09:28:30.024630 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7036 09:28:30.027517 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7037 09:28:30.031103 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7038 09:28:30.037791 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7039 09:28:30.041136 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7040 09:28:30.043852 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7041 09:28:30.047617 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7042 09:28:30.054336 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7043 09:28:30.054889 ==
7044 09:28:30.057659 Dram Type= 6, Freq= 0, CH_1, rank 1
7045 09:28:30.060771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7046 09:28:30.061229 ==
7047 09:28:30.063622 DQS Delay:
7048 09:28:30.064077 DQS0 = 48, DQS1 = 56
7049 09:28:30.064471 DQM Delay:
7050 09:28:30.067356 DQM0 = 12, DQM1 = 11
7051 09:28:30.067834 DQ Delay:
7052 09:28:30.070908 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7053 09:28:30.073571 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
7054 09:28:30.077353 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7055 09:28:30.080301 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7056 09:28:30.080763
7057 09:28:30.081218
7058 09:28:30.090053 [DQSOSCAuto] RK1, (LSB)MR18= 0x6758, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7059 09:28:30.090683 CH1 RK1: MR19=C0C, MR18=6758
7060 09:28:30.096571 CH1_RK1: MR19=0xC0C, MR18=0x6758, DQSOSC=396, MR23=63, INC=376, DEC=251
7061 09:28:30.099743 [RxdqsGatingPostProcess] freq 400
7062 09:28:30.106399 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7063 09:28:30.110050 best DQS0 dly(2T, 0.5T) = (0, 10)
7064 09:28:30.113354 best DQS1 dly(2T, 0.5T) = (0, 10)
7065 09:28:30.116618 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7066 09:28:30.119679 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7067 09:28:30.123252 best DQS0 dly(2T, 0.5T) = (0, 10)
7068 09:28:30.126240 best DQS1 dly(2T, 0.5T) = (0, 10)
7069 09:28:30.129716 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7070 09:28:30.132852 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7071 09:28:30.133271 Pre-setting of DQS Precalculation
7072 09:28:30.139396 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7073 09:28:30.146227 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7074 09:28:30.152740 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7075 09:28:30.153161
7076 09:28:30.153485
7077 09:28:30.155994 [Calibration Summary] 800 Mbps
7078 09:28:30.159793 CH 0, Rank 0
7079 09:28:30.160210 SW Impedance : PASS
7080 09:28:30.162857 DUTY Scan : NO K
7081 09:28:30.166296 ZQ Calibration : PASS
7082 09:28:30.166716 Jitter Meter : NO K
7083 09:28:30.169493 CBT Training : PASS
7084 09:28:30.172635 Write leveling : PASS
7085 09:28:30.173058 RX DQS gating : PASS
7086 09:28:30.175694 RX DQ/DQS(RDDQC) : PASS
7087 09:28:30.176110 TX DQ/DQS : PASS
7088 09:28:30.179251 RX DATLAT : PASS
7089 09:28:30.182397 RX DQ/DQS(Engine): PASS
7090 09:28:30.182816 TX OE : NO K
7091 09:28:30.185844 All Pass.
7092 09:28:30.186434
7093 09:28:30.186958 CH 0, Rank 1
7094 09:28:30.189110 SW Impedance : PASS
7095 09:28:30.189820 DUTY Scan : NO K
7096 09:28:30.192205 ZQ Calibration : PASS
7097 09:28:30.195743 Jitter Meter : NO K
7098 09:28:30.196382 CBT Training : PASS
7099 09:28:30.198809 Write leveling : NO K
7100 09:28:30.202050 RX DQS gating : PASS
7101 09:28:30.202584 RX DQ/DQS(RDDQC) : PASS
7102 09:28:30.205515 TX DQ/DQS : PASS
7103 09:28:30.209223 RX DATLAT : PASS
7104 09:28:30.209742 RX DQ/DQS(Engine): PASS
7105 09:28:30.212071 TX OE : NO K
7106 09:28:30.212667 All Pass.
7107 09:28:30.213157
7108 09:28:30.215151 CH 1, Rank 0
7109 09:28:30.215580 SW Impedance : PASS
7110 09:28:30.218827 DUTY Scan : NO K
7111 09:28:30.221990 ZQ Calibration : PASS
7112 09:28:30.222630 Jitter Meter : NO K
7113 09:28:30.225113 CBT Training : PASS
7114 09:28:30.228584 Write leveling : PASS
7115 09:28:30.229115 RX DQS gating : PASS
7116 09:28:30.231750 RX DQ/DQS(RDDQC) : PASS
7117 09:28:30.234993 TX DQ/DQS : PASS
7118 09:28:30.235513 RX DATLAT : PASS
7119 09:28:30.238359 RX DQ/DQS(Engine): PASS
7120 09:28:30.241306 TX OE : NO K
7121 09:28:30.241620 All Pass.
7122 09:28:30.241862
7123 09:28:30.242246 CH 1, Rank 1
7124 09:28:30.244610 SW Impedance : PASS
7125 09:28:30.248101 DUTY Scan : NO K
7126 09:28:30.248403 ZQ Calibration : PASS
7127 09:28:30.251322 Jitter Meter : NO K
7128 09:28:30.255007 CBT Training : PASS
7129 09:28:30.255234 Write leveling : NO K
7130 09:28:30.258076 RX DQS gating : PASS
7131 09:28:30.258359 RX DQ/DQS(RDDQC) : PASS
7132 09:28:30.261233 TX DQ/DQS : PASS
7133 09:28:30.264428 RX DATLAT : PASS
7134 09:28:30.264624 RX DQ/DQS(Engine): PASS
7135 09:28:30.268239 TX OE : NO K
7136 09:28:30.268432 All Pass.
7137 09:28:30.268595
7138 09:28:30.271554 DramC Write-DBI off
7139 09:28:30.274640 PER_BANK_REFRESH: Hybrid Mode
7140 09:28:30.274868 TX_TRACKING: ON
7141 09:28:30.284626 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7142 09:28:30.287886 [FAST_K] Save calibration result to emmc
7143 09:28:30.291183 dramc_set_vcore_voltage set vcore to 725000
7144 09:28:30.294200 Read voltage for 1600, 0
7145 09:28:30.294426 Vio18 = 0
7146 09:28:30.297255 Vcore = 725000
7147 09:28:30.297479 Vdram = 0
7148 09:28:30.297653 Vddq = 0
7149 09:28:30.297814 Vmddr = 0
7150 09:28:30.303971 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7151 09:28:30.310729 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7152 09:28:30.310983 MEM_TYPE=3, freq_sel=13
7153 09:28:30.313862 sv_algorithm_assistance_LP4_3733
7154 09:28:30.320297 ============ PULL DRAM RESETB DOWN ============
7155 09:28:30.323924 ========== PULL DRAM RESETB DOWN end =========
7156 09:28:30.327270 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7157 09:28:30.330400 ===================================
7158 09:28:30.333645 LPDDR4 DRAM CONFIGURATION
7159 09:28:30.336707 ===================================
7160 09:28:30.337177 EX_ROW_EN[0] = 0x0
7161 09:28:30.340632 EX_ROW_EN[1] = 0x0
7162 09:28:30.343437 LP4Y_EN = 0x0
7163 09:28:30.343786 WORK_FSP = 0x1
7164 09:28:30.347049 WL = 0x5
7165 09:28:30.347451 RL = 0x5
7166 09:28:30.350337 BL = 0x2
7167 09:28:30.350818 RPST = 0x0
7168 09:28:30.353735 RD_PRE = 0x0
7169 09:28:30.354288 WR_PRE = 0x1
7170 09:28:30.356999 WR_PST = 0x1
7171 09:28:30.357378 DBI_WR = 0x0
7172 09:28:30.360369 DBI_RD = 0x0
7173 09:28:30.360912 OTF = 0x1
7174 09:28:30.363461 ===================================
7175 09:28:30.366675 ===================================
7176 09:28:30.370370 ANA top config
7177 09:28:30.373441 ===================================
7178 09:28:30.376539 DLL_ASYNC_EN = 0
7179 09:28:30.376893 ALL_SLAVE_EN = 0
7180 09:28:30.379714 NEW_RANK_MODE = 1
7181 09:28:30.383354 DLL_IDLE_MODE = 1
7182 09:28:30.386660 LP45_APHY_COMB_EN = 1
7183 09:28:30.387006 TX_ODT_DIS = 0
7184 09:28:30.389636 NEW_8X_MODE = 1
7185 09:28:30.393153 ===================================
7186 09:28:30.396680 ===================================
7187 09:28:30.399845 data_rate = 3200
7188 09:28:30.402666 CKR = 1
7189 09:28:30.406204 DQ_P2S_RATIO = 8
7190 09:28:30.409361 ===================================
7191 09:28:30.412989 CA_P2S_RATIO = 8
7192 09:28:30.413441 DQ_CA_OPEN = 0
7193 09:28:30.415935 DQ_SEMI_OPEN = 0
7194 09:28:30.419743 CA_SEMI_OPEN = 0
7195 09:28:30.422802 CA_FULL_RATE = 0
7196 09:28:30.425992 DQ_CKDIV4_EN = 0
7197 09:28:30.429180 CA_CKDIV4_EN = 0
7198 09:28:30.432582 CA_PREDIV_EN = 0
7199 09:28:30.432940 PH8_DLY = 12
7200 09:28:30.435768 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7201 09:28:30.438827 DQ_AAMCK_DIV = 4
7202 09:28:30.442391 CA_AAMCK_DIV = 4
7203 09:28:30.445290 CA_ADMCK_DIV = 4
7204 09:28:30.448792 DQ_TRACK_CA_EN = 0
7205 09:28:30.451990 CA_PICK = 1600
7206 09:28:30.452100 CA_MCKIO = 1600
7207 09:28:30.455301 MCKIO_SEMI = 0
7208 09:28:30.458818 PLL_FREQ = 3068
7209 09:28:30.461813 DQ_UI_PI_RATIO = 32
7210 09:28:30.465098 CA_UI_PI_RATIO = 0
7211 09:28:30.468474 ===================================
7212 09:28:30.471612 ===================================
7213 09:28:30.475462 memory_type:LPDDR4
7214 09:28:30.475551 GP_NUM : 10
7215 09:28:30.478528 SRAM_EN : 1
7216 09:28:30.478615 MD32_EN : 0
7217 09:28:30.481620 ===================================
7218 09:28:30.484708 [ANA_INIT] >>>>>>>>>>>>>>
7219 09:28:30.488183 <<<<<< [CONFIGURE PHASE]: ANA_TX
7220 09:28:30.491281 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7221 09:28:30.494907 ===================================
7222 09:28:30.498144 data_rate = 3200,PCW = 0X7600
7223 09:28:30.502003 ===================================
7224 09:28:30.504898 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7225 09:28:30.511790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7226 09:28:30.514793 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7227 09:28:30.521254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7228 09:28:30.524480 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7229 09:28:30.528296 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7230 09:28:30.528916 [ANA_INIT] flow start
7231 09:28:30.531587 [ANA_INIT] PLL >>>>>>>>
7232 09:28:30.534987 [ANA_INIT] PLL <<<<<<<<
7233 09:28:30.538133 [ANA_INIT] MIDPI >>>>>>>>
7234 09:28:30.538613 [ANA_INIT] MIDPI <<<<<<<<
7235 09:28:30.541178 [ANA_INIT] DLL >>>>>>>>
7236 09:28:30.544737 [ANA_INIT] DLL <<<<<<<<
7237 09:28:30.545310 [ANA_INIT] flow end
7238 09:28:30.547502 ============ LP4 DIFF to SE enter ============
7239 09:28:30.554360 ============ LP4 DIFF to SE exit ============
7240 09:28:30.554947 [ANA_INIT] <<<<<<<<<<<<<
7241 09:28:30.557974 [Flow] Enable top DCM control >>>>>
7242 09:28:30.560994 [Flow] Enable top DCM control <<<<<
7243 09:28:30.564193 Enable DLL master slave shuffle
7244 09:28:30.570933 ==============================================================
7245 09:28:30.571541 Gating Mode config
7246 09:28:30.577397 ==============================================================
7247 09:28:30.580525 Config description:
7248 09:28:30.590598 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7249 09:28:30.597455 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7250 09:28:30.600982 SELPH_MODE 0: By rank 1: By Phase
7251 09:28:30.606872 ==============================================================
7252 09:28:30.610719 GAT_TRACK_EN = 1
7253 09:28:30.613957 RX_GATING_MODE = 2
7254 09:28:30.617810 RX_GATING_TRACK_MODE = 2
7255 09:28:30.618414 SELPH_MODE = 1
7256 09:28:30.620755 PICG_EARLY_EN = 1
7257 09:28:30.624223 VALID_LAT_VALUE = 1
7258 09:28:30.630273 ==============================================================
7259 09:28:30.633671 Enter into Gating configuration >>>>
7260 09:28:30.637035 Exit from Gating configuration <<<<
7261 09:28:30.640735 Enter into DVFS_PRE_config >>>>>
7262 09:28:30.650441 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7263 09:28:30.653542 Exit from DVFS_PRE_config <<<<<
7264 09:28:30.656511 Enter into PICG configuration >>>>
7265 09:28:30.660259 Exit from PICG configuration <<<<
7266 09:28:30.663105 [RX_INPUT] configuration >>>>>
7267 09:28:30.666602 [RX_INPUT] configuration <<<<<
7268 09:28:30.669736 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7269 09:28:30.676277 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7270 09:28:30.683046 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7271 09:28:30.689374 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7272 09:28:30.696578 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7273 09:28:30.702696 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7274 09:28:30.706327 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7275 09:28:30.709266 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7276 09:28:30.713195 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7277 09:28:30.719236 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7278 09:28:30.722426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7279 09:28:30.725772 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7280 09:28:30.729357 ===================================
7281 09:28:30.732570 LPDDR4 DRAM CONFIGURATION
7282 09:28:30.735693 ===================================
7283 09:28:30.736002 EX_ROW_EN[0] = 0x0
7284 09:28:30.739377 EX_ROW_EN[1] = 0x0
7285 09:28:30.741962 LP4Y_EN = 0x0
7286 09:28:30.742344 WORK_FSP = 0x1
7287 09:28:30.745504 WL = 0x5
7288 09:28:30.745864 RL = 0x5
7289 09:28:30.748636 BL = 0x2
7290 09:28:30.749044 RPST = 0x0
7291 09:28:30.752422 RD_PRE = 0x0
7292 09:28:30.752859 WR_PRE = 0x1
7293 09:28:30.755435 WR_PST = 0x1
7294 09:28:30.755820 DBI_WR = 0x0
7295 09:28:30.758596 DBI_RD = 0x0
7296 09:28:30.758903 OTF = 0x1
7297 09:28:30.762255 ===================================
7298 09:28:30.765416 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7299 09:28:30.772244 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7300 09:28:30.775394 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7301 09:28:30.779024 ===================================
7302 09:28:30.782044 LPDDR4 DRAM CONFIGURATION
7303 09:28:30.785524 ===================================
7304 09:28:30.785826 EX_ROW_EN[0] = 0x10
7305 09:28:30.788568 EX_ROW_EN[1] = 0x0
7306 09:28:30.788866 LP4Y_EN = 0x0
7307 09:28:30.792009 WORK_FSP = 0x1
7308 09:28:30.795296 WL = 0x5
7309 09:28:30.795594 RL = 0x5
7310 09:28:30.798402 BL = 0x2
7311 09:28:30.798701 RPST = 0x0
7312 09:28:30.802036 RD_PRE = 0x0
7313 09:28:30.802417 WR_PRE = 0x1
7314 09:28:30.804980 WR_PST = 0x1
7315 09:28:30.805293 DBI_WR = 0x0
7316 09:28:30.808282 DBI_RD = 0x0
7317 09:28:30.808600 OTF = 0x1
7318 09:28:30.811680 ===================================
7319 09:28:30.818103 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7320 09:28:30.818477 ==
7321 09:28:30.821601 Dram Type= 6, Freq= 0, CH_0, rank 0
7322 09:28:30.824710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7323 09:28:30.828432 ==
7324 09:28:30.828739 [Duty_Offset_Calibration]
7325 09:28:30.831629 B0:1 B1:-1 CA:0
7326 09:28:30.832007
7327 09:28:30.834822 [DutyScan_Calibration_Flow] k_type=0
7328 09:28:30.843427
7329 09:28:30.843812 ==CLK 0==
7330 09:28:30.847256 Final CLK duty delay cell = 0
7331 09:28:30.850151 [0] MAX Duty = 5125%(X100), DQS PI = 20
7332 09:28:30.853605 [0] MIN Duty = 4907%(X100), DQS PI = 6
7333 09:28:30.853904 [0] AVG Duty = 5016%(X100)
7334 09:28:30.857005
7335 09:28:30.860160 CH0 CLK Duty spec in!! Max-Min= 218%
7336 09:28:30.863384 [DutyScan_Calibration_Flow] ====Done====
7337 09:28:30.863721
7338 09:28:30.867084 [DutyScan_Calibration_Flow] k_type=1
7339 09:28:30.883089
7340 09:28:30.883402 ==DQS 0 ==
7341 09:28:30.885982 Final DQS duty delay cell = -4
7342 09:28:30.889165 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7343 09:28:30.892777 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7344 09:28:30.895850 [-4] AVG Duty = 4906%(X100)
7345 09:28:30.895931
7346 09:28:30.895995 ==DQS 1 ==
7347 09:28:30.899009 Final DQS duty delay cell = 0
7348 09:28:30.902073 [0] MAX Duty = 5156%(X100), DQS PI = 2
7349 09:28:30.905506 [0] MIN Duty = 5000%(X100), DQS PI = 18
7350 09:28:30.909034 [0] AVG Duty = 5078%(X100)
7351 09:28:30.909108
7352 09:28:30.911863 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7353 09:28:30.911936
7354 09:28:30.915208 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7355 09:28:30.918535 [DutyScan_Calibration_Flow] ====Done====
7356 09:28:30.918608
7357 09:28:30.921905 [DutyScan_Calibration_Flow] k_type=3
7358 09:28:30.940090
7359 09:28:30.940239 ==DQM 0 ==
7360 09:28:30.943314 Final DQM duty delay cell = 0
7361 09:28:30.947133 [0] MAX Duty = 5093%(X100), DQS PI = 18
7362 09:28:30.950124 [0] MIN Duty = 4875%(X100), DQS PI = 8
7363 09:28:30.953289 [0] AVG Duty = 4984%(X100)
7364 09:28:30.953413
7365 09:28:30.953526 ==DQM 1 ==
7366 09:28:30.956883 Final DQM duty delay cell = 0
7367 09:28:30.959775 [0] MAX Duty = 5000%(X100), DQS PI = 2
7368 09:28:30.963339 [0] MIN Duty = 4782%(X100), DQS PI = 22
7369 09:28:30.966358 [0] AVG Duty = 4891%(X100)
7370 09:28:30.966479
7371 09:28:30.970149 CH0 DQM 0 Duty spec in!! Max-Min= 218%
7372 09:28:30.970297
7373 09:28:30.973235 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7374 09:28:30.976444 [DutyScan_Calibration_Flow] ====Done====
7375 09:28:30.976593
7376 09:28:30.979501 [DutyScan_Calibration_Flow] k_type=2
7377 09:28:30.996101
7378 09:28:30.996356 ==DQ 0 ==
7379 09:28:30.999914 Final DQ duty delay cell = -4
7380 09:28:31.003316 [-4] MAX Duty = 5031%(X100), DQS PI = 26
7381 09:28:31.006487 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7382 09:28:31.009710 [-4] AVG Duty = 4953%(X100)
7383 09:28:31.010000
7384 09:28:31.010222 ==DQ 1 ==
7385 09:28:31.012884 Final DQ duty delay cell = 0
7386 09:28:31.016391 [0] MAX Duty = 5125%(X100), DQS PI = 48
7387 09:28:31.019747 [0] MIN Duty = 4969%(X100), DQS PI = 40
7388 09:28:31.022757 [0] AVG Duty = 5047%(X100)
7389 09:28:31.022996
7390 09:28:31.025926 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7391 09:28:31.026193
7392 09:28:31.029366 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7393 09:28:31.032479 [DutyScan_Calibration_Flow] ====Done====
7394 09:28:31.032718 ==
7395 09:28:31.035894 Dram Type= 6, Freq= 0, CH_1, rank 0
7396 09:28:31.039039 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7397 09:28:31.039279 ==
7398 09:28:31.042499 [Duty_Offset_Calibration]
7399 09:28:31.042814 B0:-1 B1:1 CA:2
7400 09:28:31.045952
7401 09:28:31.048964 [DutyScan_Calibration_Flow] k_type=0
7402 09:28:31.057434
7403 09:28:31.057757 ==CLK 0==
7404 09:28:31.060381 Final CLK duty delay cell = 0
7405 09:28:31.064270 [0] MAX Duty = 5187%(X100), DQS PI = 22
7406 09:28:31.067007 [0] MIN Duty = 4969%(X100), DQS PI = 0
7407 09:28:31.067385 [0] AVG Duty = 5078%(X100)
7408 09:28:31.070444
7409 09:28:31.073961 CH1 CLK Duty spec in!! Max-Min= 218%
7410 09:28:31.077117 [DutyScan_Calibration_Flow] ====Done====
7411 09:28:31.077364
7412 09:28:31.080152 [DutyScan_Calibration_Flow] k_type=1
7413 09:28:31.096885
7414 09:28:31.097125 ==DQS 0 ==
7415 09:28:31.100055 Final DQS duty delay cell = 0
7416 09:28:31.103068 [0] MAX Duty = 5125%(X100), DQS PI = 20
7417 09:28:31.106596 [0] MIN Duty = 4907%(X100), DQS PI = 8
7418 09:28:31.109897 [0] AVG Duty = 5016%(X100)
7419 09:28:31.110134
7420 09:28:31.110345 ==DQS 1 ==
7421 09:28:31.113074 Final DQS duty delay cell = 0
7422 09:28:31.116820 [0] MAX Duty = 5093%(X100), DQS PI = 26
7423 09:28:31.120000 [0] MIN Duty = 4938%(X100), DQS PI = 56
7424 09:28:31.123160 [0] AVG Duty = 5015%(X100)
7425 09:28:31.123420
7426 09:28:31.126402 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7427 09:28:31.126642
7428 09:28:31.129355 CH1 DQS 1 Duty spec in!! Max-Min= 155%
7429 09:28:31.133032 [DutyScan_Calibration_Flow] ====Done====
7430 09:28:31.133271
7431 09:28:31.136213 [DutyScan_Calibration_Flow] k_type=3
7432 09:28:31.153530
7433 09:28:31.153768 ==DQM 0 ==
7434 09:28:31.157059 Final DQM duty delay cell = 0
7435 09:28:31.160307 [0] MAX Duty = 5218%(X100), DQS PI = 34
7436 09:28:31.163312 [0] MIN Duty = 5031%(X100), DQS PI = 6
7437 09:28:31.166827 [0] AVG Duty = 5124%(X100)
7438 09:28:31.167064
7439 09:28:31.167250 ==DQM 1 ==
7440 09:28:31.170046 Final DQM duty delay cell = 0
7441 09:28:31.173759 [0] MAX Duty = 5125%(X100), DQS PI = 2
7442 09:28:31.176530 [0] MIN Duty = 4938%(X100), DQS PI = 36
7443 09:28:31.180377 [0] AVG Duty = 5031%(X100)
7444 09:28:31.180614
7445 09:28:31.183164 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7446 09:28:31.183405
7447 09:28:31.187026 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7448 09:28:31.189832 [DutyScan_Calibration_Flow] ====Done====
7449 09:28:31.190078
7450 09:28:31.193234 [DutyScan_Calibration_Flow] k_type=2
7451 09:28:31.210110
7452 09:28:31.210273 ==DQ 0 ==
7453 09:28:31.213679 Final DQ duty delay cell = 0
7454 09:28:31.216982 [0] MAX Duty = 5156%(X100), DQS PI = 30
7455 09:28:31.220193 [0] MIN Duty = 4906%(X100), DQS PI = 8
7456 09:28:31.220328 [0] AVG Duty = 5031%(X100)
7457 09:28:31.220433
7458 09:28:31.223270 ==DQ 1 ==
7459 09:28:31.227068 Final DQ duty delay cell = 0
7460 09:28:31.230141 [0] MAX Duty = 5156%(X100), DQS PI = 10
7461 09:28:31.233345 [0] MIN Duty = 4969%(X100), DQS PI = 34
7462 09:28:31.233481 [0] AVG Duty = 5062%(X100)
7463 09:28:31.233587
7464 09:28:31.236846 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7465 09:28:31.240412
7466 09:28:31.243481 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7467 09:28:31.246517 [DutyScan_Calibration_Flow] ====Done====
7468 09:28:31.250422 nWR fixed to 30
7469 09:28:31.250504 [ModeRegInit_LP4] CH0 RK0
7470 09:28:31.253522 [ModeRegInit_LP4] CH0 RK1
7471 09:28:31.256599 [ModeRegInit_LP4] CH1 RK0
7472 09:28:31.259770 [ModeRegInit_LP4] CH1 RK1
7473 09:28:31.259851 match AC timing 5
7474 09:28:31.266422 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7475 09:28:31.269543 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7476 09:28:31.273261 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7477 09:28:31.279495 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7478 09:28:31.283127 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7479 09:28:31.283227 [MiockJmeterHQA]
7480 09:28:31.283317
7481 09:28:31.286102 [DramcMiockJmeter] u1RxGatingPI = 0
7482 09:28:31.289859 0 : 4253, 4027
7483 09:28:31.289984 4 : 4252, 4027
7484 09:28:31.293147 8 : 4363, 4138
7485 09:28:31.293237 12 : 4363, 4137
7486 09:28:31.293332 16 : 4363, 4137
7487 09:28:31.296443 20 : 4252, 4027
7488 09:28:31.296516 24 : 4252, 4027
7489 09:28:31.299676 28 : 4253, 4027
7490 09:28:31.299747 32 : 4363, 4137
7491 09:28:31.302715 36 : 4252, 4027
7492 09:28:31.302823 40 : 4363, 4137
7493 09:28:31.306350 44 : 4252, 4027
7494 09:28:31.306461 48 : 4253, 4027
7495 09:28:31.306561 52 : 4252, 4027
7496 09:28:31.309563 56 : 4255, 4029
7497 09:28:31.309705 60 : 4361, 4138
7498 09:28:31.312874 64 : 4252, 4029
7499 09:28:31.312958 68 : 4361, 4137
7500 09:28:31.315881 72 : 4253, 4029
7501 09:28:31.315964 76 : 4250, 4027
7502 09:28:31.319638 80 : 4250, 4027
7503 09:28:31.319721 84 : 4361, 4138
7504 09:28:31.319786 88 : 4250, 4027
7505 09:28:31.322776 92 : 4361, 380
7506 09:28:31.322874 96 : 4253, 0
7507 09:28:31.325937 100 : 4250, 0
7508 09:28:31.326020 104 : 4250, 0
7509 09:28:31.326105 108 : 4250, 0
7510 09:28:31.329094 112 : 4252, 0
7511 09:28:31.329203 116 : 4250, 0
7512 09:28:31.332237 120 : 4250, 0
7513 09:28:31.332346 124 : 4252, 0
7514 09:28:31.332440 128 : 4361, 0
7515 09:28:31.335934 132 : 4250, 0
7516 09:28:31.336023 136 : 4250, 0
7517 09:28:31.338981 140 : 4250, 0
7518 09:28:31.339063 144 : 4361, 0
7519 09:28:31.339128 148 : 4360, 0
7520 09:28:31.342636 152 : 4250, 0
7521 09:28:31.342721 156 : 4250, 0
7522 09:28:31.345824 160 : 4250, 0
7523 09:28:31.345905 164 : 4250, 0
7524 09:28:31.346040 168 : 4250, 0
7525 09:28:31.348773 172 : 4250, 0
7526 09:28:31.348855 176 : 4252, 0
7527 09:28:31.348920 180 : 4361, 0
7528 09:28:31.351983 184 : 4250, 0
7529 09:28:31.352065 188 : 4250, 0
7530 09:28:31.355192 192 : 4250, 0
7531 09:28:31.355277 196 : 4361, 0
7532 09:28:31.355343 200 : 4250, 0
7533 09:28:31.358978 204 : 4250, 0
7534 09:28:31.359061 208 : 4250, 0
7535 09:28:31.362040 212 : 4363, 0
7536 09:28:31.362123 216 : 4250, 0
7537 09:28:31.362223 220 : 4250, 0
7538 09:28:31.365202 224 : 4250, 52
7539 09:28:31.365284 228 : 4250, 2936
7540 09:28:31.368654 232 : 4250, 4027
7541 09:28:31.368736 236 : 4250, 4026
7542 09:28:31.371875 240 : 4250, 4027
7543 09:28:31.371957 244 : 4250, 4027
7544 09:28:31.375163 248 : 4252, 4029
7545 09:28:31.375246 252 : 4250, 4027
7546 09:28:31.378800 256 : 4361, 4137
7547 09:28:31.378882 260 : 4361, 4138
7548 09:28:31.381731 264 : 4250, 4027
7549 09:28:31.381813 268 : 4363, 4140
7550 09:28:31.381878 272 : 4250, 4027
7551 09:28:31.385205 276 : 4250, 4027
7552 09:28:31.385287 280 : 4252, 4027
7553 09:28:31.388618 284 : 4252, 4029
7554 09:28:31.388701 288 : 4250, 4027
7555 09:28:31.391672 292 : 4250, 4027
7556 09:28:31.391782 296 : 4250, 4027
7557 09:28:31.394745 300 : 4252, 4029
7558 09:28:31.394828 304 : 4250, 4027
7559 09:28:31.398485 308 : 4361, 4137
7560 09:28:31.398601 312 : 4361, 4137
7561 09:28:31.401845 316 : 4250, 4027
7562 09:28:31.401927 320 : 4363, 4140
7563 09:28:31.404874 324 : 4360, 4138
7564 09:28:31.404956 328 : 4250, 4027
7565 09:28:31.408157 332 : 4250, 4027
7566 09:28:31.408240 336 : 4252, 3931
7567 09:28:31.408305 340 : 4250, 2459
7568 09:28:31.411870 344 : 4250, 61
7569 09:28:31.411953
7570 09:28:31.414874 MIOCK jitter meter ch=0
7571 09:28:31.414955
7572 09:28:31.415018 1T = (344-92) = 252 dly cells
7573 09:28:31.421187 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7574 09:28:31.421269 ==
7575 09:28:31.424847 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 09:28:31.428093 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 09:28:31.431627 ==
7578 09:28:31.434874 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7579 09:28:31.437693 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7580 09:28:31.444448 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7581 09:28:31.451230 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7582 09:28:31.459085 [CA 0] Center 43 (13~74) winsize 62
7583 09:28:31.461913 [CA 1] Center 43 (13~74) winsize 62
7584 09:28:31.465903 [CA 2] Center 39 (10~69) winsize 60
7585 09:28:31.468948 [CA 3] Center 38 (9~68) winsize 60
7586 09:28:31.472351 [CA 4] Center 37 (8~66) winsize 59
7587 09:28:31.475588 [CA 5] Center 36 (7~66) winsize 60
7588 09:28:31.476007
7589 09:28:31.478953 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7590 09:28:31.479376
7591 09:28:31.482435 [CATrainingPosCal] consider 1 rank data
7592 09:28:31.485493 u2DelayCellTimex100 = 258/100 ps
7593 09:28:31.492420 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7594 09:28:31.495201 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7595 09:28:31.498438 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7596 09:28:31.501944 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7597 09:28:31.504975 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7598 09:28:31.508774 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7599 09:28:31.509195
7600 09:28:31.511998 CA PerBit enable=1, Macro0, CA PI delay=36
7601 09:28:31.512417
7602 09:28:31.515166 [CBTSetCACLKResult] CA Dly = 36
7603 09:28:31.518795 CS Dly: 12 (0~43)
7604 09:28:31.521880 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7605 09:28:31.525273 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7606 09:28:31.525692 ==
7607 09:28:31.528362 Dram Type= 6, Freq= 0, CH_0, rank 1
7608 09:28:31.535017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 09:28:31.535578 ==
7610 09:28:31.538220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7611 09:28:31.544742 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7612 09:28:31.547993 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7613 09:28:31.554204 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7614 09:28:31.562496 [CA 0] Center 42 (12~73) winsize 62
7615 09:28:31.566105 [CA 1] Center 43 (13~73) winsize 61
7616 09:28:31.569123 [CA 2] Center 37 (8~67) winsize 60
7617 09:28:31.572249 [CA 3] Center 37 (7~67) winsize 61
7618 09:28:31.575921 [CA 4] Center 36 (6~66) winsize 61
7619 09:28:31.579034 [CA 5] Center 35 (5~65) winsize 61
7620 09:28:31.579527
7621 09:28:31.582669 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7622 09:28:31.583089
7623 09:28:31.589449 [CATrainingPosCal] consider 2 rank data
7624 09:28:31.589866 u2DelayCellTimex100 = 258/100 ps
7625 09:28:31.595836 CA0 delay=43 (13~73),Diff = 7 PI (26 cell)
7626 09:28:31.598765 CA1 delay=43 (13~73),Diff = 7 PI (26 cell)
7627 09:28:31.602337 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7628 09:28:31.605685 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7629 09:28:31.608795 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
7630 09:28:31.612031 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7631 09:28:31.612472
7632 09:28:31.615240 CA PerBit enable=1, Macro0, CA PI delay=36
7633 09:28:31.615663
7634 09:28:31.618829 [CBTSetCACLKResult] CA Dly = 36
7635 09:28:31.621907 CS Dly: 12 (0~43)
7636 09:28:31.625720 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7637 09:28:31.628731 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7638 09:28:31.629151
7639 09:28:31.631742 ----->DramcWriteLeveling(PI) begin...
7640 09:28:31.632333 ==
7641 09:28:31.634994 Dram Type= 6, Freq= 0, CH_0, rank 0
7642 09:28:31.641534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7643 09:28:31.642098 ==
7644 09:28:31.644929 Write leveling (Byte 0): 36 => 36
7645 09:28:31.648534 Write leveling (Byte 1): 25 => 25
7646 09:28:31.648953 DramcWriteLeveling(PI) end<-----
7647 09:28:31.651544
7648 09:28:31.651974 ==
7649 09:28:31.655292 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 09:28:31.658536 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 09:28:31.659106 ==
7652 09:28:31.661673 [Gating] SW mode calibration
7653 09:28:31.668057 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7654 09:28:31.674682 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7655 09:28:31.677793 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 09:28:31.681356 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7657 09:28:31.688035 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 09:28:31.690838 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7659 09:28:31.694688 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7660 09:28:31.700796 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7661 09:28:31.704410 1 4 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7662 09:28:31.707425 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7663 09:28:31.714378 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7664 09:28:31.717093 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7665 09:28:31.720598 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7666 09:28:31.727284 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
7667 09:28:31.730365 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7668 09:28:31.733616 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7669 09:28:31.740586 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7670 09:28:31.743512 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 09:28:31.746542 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7672 09:28:31.753991 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7673 09:28:31.756840 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7674 09:28:31.760235 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7675 09:28:31.766483 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7676 09:28:31.770158 1 6 20 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
7677 09:28:31.773030 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7678 09:28:31.779478 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7679 09:28:31.782830 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7680 09:28:31.786336 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7681 09:28:31.792633 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7682 09:28:31.796423 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7683 09:28:31.799401 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7684 09:28:31.806288 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7685 09:28:31.809514 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7686 09:28:31.813064 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 09:28:31.820245 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 09:28:31.822686 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 09:28:31.826074 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 09:28:31.832613 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 09:28:31.835602 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 09:28:31.839331 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 09:28:31.845116 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 09:28:31.848597 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7695 09:28:31.851733 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7696 09:28:31.858528 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7697 09:28:31.862141 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7698 09:28:31.865227 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7699 09:28:31.872154 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7700 09:28:31.874945 Total UI for P1: 0, mck2ui 16
7701 09:28:31.878902 best dqsien dly found for B0: ( 1, 9, 12)
7702 09:28:31.882000 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7703 09:28:31.884777 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7704 09:28:31.892057 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7705 09:28:31.892494 Total UI for P1: 0, mck2ui 16
7706 09:28:31.898262 best dqsien dly found for B1: ( 1, 9, 20)
7707 09:28:31.901899 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7708 09:28:31.904693 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7709 09:28:31.905113
7710 09:28:31.908357 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7711 09:28:31.911286 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7712 09:28:31.914616 [Gating] SW calibration Done
7713 09:28:31.915064 ==
7714 09:28:31.918008 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 09:28:31.921486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 09:28:31.922007 ==
7717 09:28:31.924800 RX Vref Scan: 0
7718 09:28:31.925273
7719 09:28:31.927740 RX Vref 0 -> 0, step: 1
7720 09:28:31.928222
7721 09:28:31.928672 RX Delay 0 -> 252, step: 8
7722 09:28:31.934422 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7723 09:28:31.938238 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7724 09:28:31.941354 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7725 09:28:31.944379 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7726 09:28:31.947442 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7727 09:28:31.954556 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7728 09:28:31.957439 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7729 09:28:31.960793 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7730 09:28:31.964326 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7731 09:28:31.967626 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7732 09:28:31.974253 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7733 09:28:31.977495 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7734 09:28:31.981201 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7735 09:28:31.984095 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7736 09:28:31.987731 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7737 09:28:31.993700 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7738 09:28:31.994280 ==
7739 09:28:31.997305 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 09:28:32.000689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 09:28:32.001270 ==
7742 09:28:32.001639 DQS Delay:
7743 09:28:32.003857 DQS0 = 0, DQS1 = 0
7744 09:28:32.004317 DQM Delay:
7745 09:28:32.006883 DQM0 = 136, DQM1 = 125
7746 09:28:32.007409 DQ Delay:
7747 09:28:32.010527 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =135
7748 09:28:32.014150 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =147
7749 09:28:32.017543 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7750 09:28:32.023514 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7751 09:28:32.024076
7752 09:28:32.024442
7753 09:28:32.024792 ==
7754 09:28:32.026736 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 09:28:32.030345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 09:28:32.030808 ==
7757 09:28:32.031188
7758 09:28:32.031523
7759 09:28:32.033347 TX Vref Scan disable
7760 09:28:32.033843 == TX Byte 0 ==
7761 09:28:32.039988 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7762 09:28:32.043290 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7763 09:28:32.043849 == TX Byte 1 ==
7764 09:28:32.050228 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7765 09:28:32.053608 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7766 09:28:32.054098 ==
7767 09:28:32.056792 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 09:28:32.059952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 09:28:32.060371 ==
7770 09:28:32.074672
7771 09:28:32.078222 TX Vref early break, caculate TX vref
7772 09:28:32.081226 TX Vref=16, minBit 4, minWin=22, winSum=369
7773 09:28:32.084656 TX Vref=18, minBit 0, minWin=23, winSum=377
7774 09:28:32.087956 TX Vref=20, minBit 1, minWin=23, winSum=385
7775 09:28:32.091185 TX Vref=22, minBit 3, minWin=24, winSum=402
7776 09:28:32.094404 TX Vref=24, minBit 3, minWin=24, winSum=407
7777 09:28:32.100775 TX Vref=26, minBit 4, minWin=24, winSum=413
7778 09:28:32.104554 TX Vref=28, minBit 0, minWin=24, winSum=417
7779 09:28:32.107453 TX Vref=30, minBit 4, minWin=24, winSum=408
7780 09:28:32.111112 TX Vref=32, minBit 0, minWin=24, winSum=398
7781 09:28:32.114561 TX Vref=34, minBit 4, minWin=23, winSum=389
7782 09:28:32.120532 [TxChooseVref] Worse bit 0, Min win 24, Win sum 417, Final Vref 28
7783 09:28:32.121078
7784 09:28:32.124362 Final TX Range 0 Vref 28
7785 09:28:32.125008
7786 09:28:32.125431 ==
7787 09:28:32.127153 Dram Type= 6, Freq= 0, CH_0, rank 0
7788 09:28:32.131097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7789 09:28:32.131563 ==
7790 09:28:32.131927
7791 09:28:32.132261
7792 09:28:32.133845 TX Vref Scan disable
7793 09:28:32.140676 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7794 09:28:32.141295 == TX Byte 0 ==
7795 09:28:32.144034 u2DelayCellOfst[0]=15 cells (4 PI)
7796 09:28:32.147415 u2DelayCellOfst[1]=15 cells (4 PI)
7797 09:28:32.150082 u2DelayCellOfst[2]=11 cells (3 PI)
7798 09:28:32.153499 u2DelayCellOfst[3]=11 cells (3 PI)
7799 09:28:32.156759 u2DelayCellOfst[4]=7 cells (2 PI)
7800 09:28:32.160123 u2DelayCellOfst[5]=0 cells (0 PI)
7801 09:28:32.163339 u2DelayCellOfst[6]=15 cells (4 PI)
7802 09:28:32.166739 u2DelayCellOfst[7]=18 cells (5 PI)
7803 09:28:32.170426 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7804 09:28:32.173608 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7805 09:28:32.176870 == TX Byte 1 ==
7806 09:28:32.179814 u2DelayCellOfst[8]=0 cells (0 PI)
7807 09:28:32.183874 u2DelayCellOfst[9]=0 cells (0 PI)
7808 09:28:32.186477 u2DelayCellOfst[10]=3 cells (1 PI)
7809 09:28:32.186900 u2DelayCellOfst[11]=0 cells (0 PI)
7810 09:28:32.189702 u2DelayCellOfst[12]=7 cells (2 PI)
7811 09:28:32.193247 u2DelayCellOfst[13]=11 cells (3 PI)
7812 09:28:32.196361 u2DelayCellOfst[14]=11 cells (3 PI)
7813 09:28:32.199459 u2DelayCellOfst[15]=7 cells (2 PI)
7814 09:28:32.206356 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7815 09:28:32.209774 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7816 09:28:32.209904 DramC Write-DBI on
7817 09:28:32.210006 ==
7818 09:28:32.212740 Dram Type= 6, Freq= 0, CH_0, rank 0
7819 09:28:32.219534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7820 09:28:32.219643 ==
7821 09:28:32.219734
7822 09:28:32.219809
7823 09:28:32.222716 TX Vref Scan disable
7824 09:28:32.222797 == TX Byte 0 ==
7825 09:28:32.229549 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7826 09:28:32.229665 == TX Byte 1 ==
7827 09:28:32.232436 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7828 09:28:32.235614 DramC Write-DBI off
7829 09:28:32.235685
7830 09:28:32.235744 [DATLAT]
7831 09:28:32.239375 Freq=1600, CH0 RK0
7832 09:28:32.239511
7833 09:28:32.239648 DATLAT Default: 0xf
7834 09:28:32.242504 0, 0xFFFF, sum = 0
7835 09:28:32.242612 1, 0xFFFF, sum = 0
7836 09:28:32.245501 2, 0xFFFF, sum = 0
7837 09:28:32.245582 3, 0xFFFF, sum = 0
7838 09:28:32.249149 4, 0xFFFF, sum = 0
7839 09:28:32.249231 5, 0xFFFF, sum = 0
7840 09:28:32.252122 6, 0xFFFF, sum = 0
7841 09:28:32.252216 7, 0xFFFF, sum = 0
7842 09:28:32.255683 8, 0xFFFF, sum = 0
7843 09:28:32.258794 9, 0xFFFF, sum = 0
7844 09:28:32.258902 10, 0xFFFF, sum = 0
7845 09:28:32.262716 11, 0xFFFF, sum = 0
7846 09:28:32.262798 12, 0xFFFF, sum = 0
7847 09:28:32.265640 13, 0xFFFF, sum = 0
7848 09:28:32.265756 14, 0x0, sum = 1
7849 09:28:32.269254 15, 0x0, sum = 2
7850 09:28:32.269337 16, 0x0, sum = 3
7851 09:28:32.272345 17, 0x0, sum = 4
7852 09:28:32.272428 best_step = 15
7853 09:28:32.272492
7854 09:28:32.272551 ==
7855 09:28:32.275431 Dram Type= 6, Freq= 0, CH_0, rank 0
7856 09:28:32.278944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7857 09:28:32.279026 ==
7858 09:28:32.282086 RX Vref Scan: 1
7859 09:28:32.282178
7860 09:28:32.285741 Set Vref Range= 24 -> 127
7861 09:28:32.285822
7862 09:28:32.285886 RX Vref 24 -> 127, step: 1
7863 09:28:32.288744
7864 09:28:32.288824 RX Delay 11 -> 252, step: 4
7865 09:28:32.288888
7866 09:28:32.292040 Set Vref, RX VrefLevel [Byte0]: 24
7867 09:28:32.295423 [Byte1]: 24
7868 09:28:32.298597
7869 09:28:32.298675 Set Vref, RX VrefLevel [Byte0]: 25
7870 09:28:32.302379 [Byte1]: 25
7871 09:28:32.306814
7872 09:28:32.306895 Set Vref, RX VrefLevel [Byte0]: 26
7873 09:28:32.309875 [Byte1]: 26
7874 09:28:32.313827
7875 09:28:32.313920 Set Vref, RX VrefLevel [Byte0]: 27
7876 09:28:32.317545 [Byte1]: 27
7877 09:28:32.321608
7878 09:28:32.321715 Set Vref, RX VrefLevel [Byte0]: 28
7879 09:28:32.325245 [Byte1]: 28
7880 09:28:32.329723
7881 09:28:32.329898 Set Vref, RX VrefLevel [Byte0]: 29
7882 09:28:32.332799 [Byte1]: 29
7883 09:28:32.336909
7884 09:28:32.337050 Set Vref, RX VrefLevel [Byte0]: 30
7885 09:28:32.340619 [Byte1]: 30
7886 09:28:32.344983
7887 09:28:32.345154 Set Vref, RX VrefLevel [Byte0]: 31
7888 09:28:32.347969 [Byte1]: 31
7889 09:28:32.352315
7890 09:28:32.352566 Set Vref, RX VrefLevel [Byte0]: 32
7891 09:28:32.356085 [Byte1]: 32
7892 09:28:32.360159
7893 09:28:32.360638 Set Vref, RX VrefLevel [Byte0]: 33
7894 09:28:32.366744 [Byte1]: 33
7895 09:28:32.367146
7896 09:28:32.369822 Set Vref, RX VrefLevel [Byte0]: 34
7897 09:28:32.373282 [Byte1]: 34
7898 09:28:32.373696
7899 09:28:32.376461 Set Vref, RX VrefLevel [Byte0]: 35
7900 09:28:32.379947 [Byte1]: 35
7901 09:28:32.382967
7902 09:28:32.383387 Set Vref, RX VrefLevel [Byte0]: 36
7903 09:28:32.386005 [Byte1]: 36
7904 09:28:32.390988
7905 09:28:32.391408 Set Vref, RX VrefLevel [Byte0]: 37
7906 09:28:32.393910 [Byte1]: 37
7907 09:28:32.398526
7908 09:28:32.398942 Set Vref, RX VrefLevel [Byte0]: 38
7909 09:28:32.401798 [Byte1]: 38
7910 09:28:32.405491
7911 09:28:32.405905 Set Vref, RX VrefLevel [Byte0]: 39
7912 09:28:32.408770 [Byte1]: 39
7913 09:28:32.413084
7914 09:28:32.413499 Set Vref, RX VrefLevel [Byte0]: 40
7915 09:28:32.416835 [Byte1]: 40
7916 09:28:32.420884
7917 09:28:32.421463 Set Vref, RX VrefLevel [Byte0]: 41
7918 09:28:32.424118 [Byte1]: 41
7919 09:28:32.428680
7920 09:28:32.429186 Set Vref, RX VrefLevel [Byte0]: 42
7921 09:28:32.431760 [Byte1]: 42
7922 09:28:32.436133
7923 09:28:32.436647 Set Vref, RX VrefLevel [Byte0]: 43
7924 09:28:32.439767 [Byte1]: 43
7925 09:28:32.444087
7926 09:28:32.444500 Set Vref, RX VrefLevel [Byte0]: 44
7927 09:28:32.447169 [Byte1]: 44
7928 09:28:32.451404
7929 09:28:32.451859 Set Vref, RX VrefLevel [Byte0]: 45
7930 09:28:32.454693 [Byte1]: 45
7931 09:28:32.458988
7932 09:28:32.459404 Set Vref, RX VrefLevel [Byte0]: 46
7933 09:28:32.462592 [Byte1]: 46
7934 09:28:32.466596
7935 09:28:32.467149 Set Vref, RX VrefLevel [Byte0]: 47
7936 09:28:32.470001 [Byte1]: 47
7937 09:28:32.474329
7938 09:28:32.474551 Set Vref, RX VrefLevel [Byte0]: 48
7939 09:28:32.477367 [Byte1]: 48
7940 09:28:32.481420
7941 09:28:32.481526 Set Vref, RX VrefLevel [Byte0]: 49
7942 09:28:32.484699 [Byte1]: 49
7943 09:28:32.489313
7944 09:28:32.489393 Set Vref, RX VrefLevel [Byte0]: 50
7945 09:28:32.492225 [Byte1]: 50
7946 09:28:32.496701
7947 09:28:32.496782 Set Vref, RX VrefLevel [Byte0]: 51
7948 09:28:32.500409 [Byte1]: 51
7949 09:28:32.504213
7950 09:28:32.504324 Set Vref, RX VrefLevel [Byte0]: 52
7951 09:28:32.507410 [Byte1]: 52
7952 09:28:32.512287
7953 09:28:32.512371 Set Vref, RX VrefLevel [Byte0]: 53
7954 09:28:32.515406 [Byte1]: 53
7955 09:28:32.519505
7956 09:28:32.519603 Set Vref, RX VrefLevel [Byte0]: 54
7957 09:28:32.523039 [Byte1]: 54
7958 09:28:32.527665
7959 09:28:32.527763 Set Vref, RX VrefLevel [Byte0]: 55
7960 09:28:32.530385 [Byte1]: 55
7961 09:28:32.534698
7962 09:28:32.534790 Set Vref, RX VrefLevel [Byte0]: 56
7963 09:28:32.537931 [Byte1]: 56
7964 09:28:32.542467
7965 09:28:32.542577 Set Vref, RX VrefLevel [Byte0]: 57
7966 09:28:32.545866 [Byte1]: 57
7967 09:28:32.550091
7968 09:28:32.550586 Set Vref, RX VrefLevel [Byte0]: 58
7969 09:28:32.553932 [Byte1]: 58
7970 09:28:32.558039
7971 09:28:32.558521 Set Vref, RX VrefLevel [Byte0]: 59
7972 09:28:32.561414 [Byte1]: 59
7973 09:28:32.565482
7974 09:28:32.565938 Set Vref, RX VrefLevel [Byte0]: 60
7975 09:28:32.569223 [Byte1]: 60
7976 09:28:32.573391
7977 09:28:32.574000 Set Vref, RX VrefLevel [Byte0]: 61
7978 09:28:32.576851 [Byte1]: 61
7979 09:28:32.581127
7980 09:28:32.581680 Set Vref, RX VrefLevel [Byte0]: 62
7981 09:28:32.584287 [Byte1]: 62
7982 09:28:32.588337
7983 09:28:32.588752 Set Vref, RX VrefLevel [Byte0]: 63
7984 09:28:32.591636 [Byte1]: 63
7985 09:28:32.595994
7986 09:28:32.596408 Set Vref, RX VrefLevel [Byte0]: 64
7987 09:28:32.599707 [Byte1]: 64
7988 09:28:32.603956
7989 09:28:32.604371 Set Vref, RX VrefLevel [Byte0]: 65
7990 09:28:32.606873 [Byte1]: 65
7991 09:28:32.611322
7992 09:28:32.611744 Set Vref, RX VrefLevel [Byte0]: 66
7993 09:28:32.614408 [Byte1]: 66
7994 09:28:32.618843
7995 09:28:32.619258 Set Vref, RX VrefLevel [Byte0]: 67
7996 09:28:32.622202 [Byte1]: 67
7997 09:28:32.626616
7998 09:28:32.627041 Set Vref, RX VrefLevel [Byte0]: 68
7999 09:28:32.630157 [Byte1]: 68
8000 09:28:32.634618
8001 09:28:32.635035 Set Vref, RX VrefLevel [Byte0]: 69
8002 09:28:32.637386 [Byte1]: 69
8003 09:28:32.641777
8004 09:28:32.642241 Set Vref, RX VrefLevel [Byte0]: 70
8005 09:28:32.645206 [Byte1]: 70
8006 09:28:32.649351
8007 09:28:32.649770 Set Vref, RX VrefLevel [Byte0]: 71
8008 09:28:32.653016 [Byte1]: 71
8009 09:28:32.657110
8010 09:28:32.657558 Set Vref, RX VrefLevel [Byte0]: 72
8011 09:28:32.660127 [Byte1]: 72
8012 09:28:32.664854
8013 09:28:32.665305 Set Vref, RX VrefLevel [Byte0]: 73
8014 09:28:32.668006 [Byte1]: 73
8015 09:28:32.672190
8016 09:28:32.672608 Set Vref, RX VrefLevel [Byte0]: 74
8017 09:28:32.675723 [Byte1]: 74
8018 09:28:32.680115
8019 09:28:32.680625 Set Vref, RX VrefLevel [Byte0]: 75
8020 09:28:32.683222 [Byte1]: 75
8021 09:28:32.687728
8022 09:28:32.688242 Set Vref, RX VrefLevel [Byte0]: 76
8023 09:28:32.691159 [Byte1]: 76
8024 09:28:32.695631
8025 09:28:32.696043 Set Vref, RX VrefLevel [Byte0]: 77
8026 09:28:32.698309 [Byte1]: 77
8027 09:28:32.702421
8028 09:28:32.702837 Set Vref, RX VrefLevel [Byte0]: 78
8029 09:28:32.705737 [Byte1]: 78
8030 09:28:32.710620
8031 09:28:32.711036 Set Vref, RX VrefLevel [Byte0]: 79
8032 09:28:32.713781 [Byte1]: 79
8033 09:28:32.718074
8034 09:28:32.718537 Final RX Vref Byte 0 = 64 to rank0
8035 09:28:32.721722 Final RX Vref Byte 1 = 60 to rank0
8036 09:28:32.724388 Final RX Vref Byte 0 = 64 to rank1
8037 09:28:32.728008 Final RX Vref Byte 1 = 60 to rank1==
8038 09:28:32.731111 Dram Type= 6, Freq= 0, CH_0, rank 0
8039 09:28:32.737774 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 09:28:32.738402 ==
8041 09:28:32.738744 DQS Delay:
8042 09:28:32.739054 DQS0 = 0, DQS1 = 0
8043 09:28:32.740815 DQM Delay:
8044 09:28:32.741226 DQM0 = 133, DQM1 = 123
8045 09:28:32.744549 DQ Delay:
8046 09:28:32.747978 DQ0 =130, DQ1 =134, DQ2 =132, DQ3 =132
8047 09:28:32.751211 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8048 09:28:32.754123 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =118
8049 09:28:32.757755 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =128
8050 09:28:32.758202
8051 09:28:32.758540
8052 09:28:32.758840
8053 09:28:32.761276 [DramC_TX_OE_Calibration] TA2
8054 09:28:32.764662 Original DQ_B0 (3 6) =30, OEN = 27
8055 09:28:32.767402 Original DQ_B1 (3 6) =30, OEN = 27
8056 09:28:32.770972 24, 0x0, End_B0=24 End_B1=24
8057 09:28:32.771396 25, 0x0, End_B0=25 End_B1=25
8058 09:28:32.774377 26, 0x0, End_B0=26 End_B1=26
8059 09:28:32.777305 27, 0x0, End_B0=27 End_B1=27
8060 09:28:32.780926 28, 0x0, End_B0=28 End_B1=28
8061 09:28:32.783937 29, 0x0, End_B0=29 End_B1=29
8062 09:28:32.784605 30, 0x0, End_B0=30 End_B1=30
8063 09:28:32.787260 31, 0x4141, End_B0=30 End_B1=30
8064 09:28:32.790819 Byte0 end_step=30 best_step=27
8065 09:28:32.793635 Byte1 end_step=30 best_step=27
8066 09:28:32.797533 Byte0 TX OE(2T, 0.5T) = (3, 3)
8067 09:28:32.800360 Byte1 TX OE(2T, 0.5T) = (3, 3)
8068 09:28:32.800774
8069 09:28:32.801097
8070 09:28:32.807048 [DQSOSCAuto] RK0, (LSB)MR18= 0x2415, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 391 ps
8071 09:28:32.810701 CH0 RK0: MR19=303, MR18=2415
8072 09:28:32.817154 CH0_RK0: MR19=0x303, MR18=0x2415, DQSOSC=391, MR23=63, INC=24, DEC=16
8073 09:28:32.817673
8074 09:28:32.820710 ----->DramcWriteLeveling(PI) begin...
8075 09:28:32.821137 ==
8076 09:28:32.823689 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 09:28:32.826834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 09:28:32.827252 ==
8079 09:28:32.830334 Write leveling (Byte 0): 35 => 35
8080 09:28:32.833917 Write leveling (Byte 1): 26 => 26
8081 09:28:32.836756 DramcWriteLeveling(PI) end<-----
8082 09:28:32.837170
8083 09:28:32.837495 ==
8084 09:28:32.840521 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 09:28:32.843432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 09:28:32.843849 ==
8087 09:28:32.847199 [Gating] SW mode calibration
8088 09:28:32.853606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8089 09:28:32.860023 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8090 09:28:32.863724 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 09:28:32.870096 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 09:28:32.873202 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8093 09:28:32.876493 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8094 09:28:32.883236 1 4 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8095 09:28:32.886398 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8096 09:28:32.889594 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8097 09:28:32.896389 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8098 09:28:32.900098 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8099 09:28:32.902960 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8100 09:28:32.909684 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8101 09:28:32.912970 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
8102 09:28:32.916405 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
8103 09:28:32.922511 1 5 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
8104 09:28:32.925998 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8105 09:28:32.929182 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8106 09:28:32.936424 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8107 09:28:32.939388 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8108 09:28:32.942345 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8109 09:28:32.949088 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8110 09:28:32.952541 1 6 16 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
8111 09:28:32.956100 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8112 09:28:32.962555 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8113 09:28:32.965823 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8114 09:28:32.968857 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 09:28:32.975483 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8116 09:28:32.979091 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8117 09:28:32.982221 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8118 09:28:32.988610 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8119 09:28:32.992295 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8120 09:28:32.995408 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 09:28:33.002073 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 09:28:33.005573 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 09:28:33.008518 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 09:28:33.015361 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8125 09:28:33.018132 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8126 09:28:33.021574 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8127 09:28:33.028146 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8128 09:28:33.031573 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8129 09:28:33.034774 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8130 09:28:33.041130 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8131 09:28:33.044499 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 09:28:33.048121 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8133 09:28:33.054286 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8134 09:28:33.057965 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8135 09:28:33.061059 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8136 09:28:33.064153 Total UI for P1: 0, mck2ui 16
8137 09:28:33.067820 best dqsien dly found for B0: ( 1, 9, 12)
8138 09:28:33.074067 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8139 09:28:33.074536 Total UI for P1: 0, mck2ui 16
8140 09:28:33.080651 best dqsien dly found for B1: ( 1, 9, 18)
8141 09:28:33.084038 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8142 09:28:33.087342 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8143 09:28:33.087766
8144 09:28:33.090546 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8145 09:28:33.093534 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8146 09:28:33.096885 [Gating] SW calibration Done
8147 09:28:33.097306 ==
8148 09:28:33.100626 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 09:28:33.103489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 09:28:33.103595 ==
8151 09:28:33.106507 RX Vref Scan: 0
8152 09:28:33.106589
8153 09:28:33.110183 RX Vref 0 -> 0, step: 1
8154 09:28:33.110285
8155 09:28:33.110369 RX Delay 0 -> 252, step: 8
8156 09:28:33.116571 iDelay=208, Bit 0, Center 131 (80 ~ 183) 104
8157 09:28:33.119768 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8158 09:28:33.123147 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8159 09:28:33.126701 iDelay=208, Bit 3, Center 127 (72 ~ 183) 112
8160 09:28:33.129922 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8161 09:28:33.136551 iDelay=208, Bit 5, Center 123 (64 ~ 183) 120
8162 09:28:33.139470 iDelay=208, Bit 6, Center 139 (80 ~ 199) 120
8163 09:28:33.142766 iDelay=208, Bit 7, Center 147 (88 ~ 207) 120
8164 09:28:33.146449 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8165 09:28:33.149335 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8166 09:28:33.156240 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8167 09:28:33.159301 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8168 09:28:33.162917 iDelay=208, Bit 12, Center 131 (72 ~ 191) 120
8169 09:28:33.165966 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8170 09:28:33.169595 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8171 09:28:33.175842 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8172 09:28:33.175949 ==
8173 09:28:33.179000 Dram Type= 6, Freq= 0, CH_0, rank 1
8174 09:28:33.182626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8175 09:28:33.182696 ==
8176 09:28:33.182761 DQS Delay:
8177 09:28:33.186172 DQS0 = 0, DQS1 = 0
8178 09:28:33.186253 DQM Delay:
8179 09:28:33.189510 DQM0 = 133, DQM1 = 128
8180 09:28:33.189608 DQ Delay:
8181 09:28:33.192677 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8182 09:28:33.195597 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =147
8183 09:28:33.199238 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
8184 09:28:33.206053 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8185 09:28:33.206137
8186 09:28:33.206224
8187 09:28:33.206283 ==
8188 09:28:33.209073 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 09:28:33.212147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 09:28:33.212246 ==
8191 09:28:33.212333
8192 09:28:33.212419
8193 09:28:33.215742 TX Vref Scan disable
8194 09:28:33.215832 == TX Byte 0 ==
8195 09:28:33.222035 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8196 09:28:33.225206 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8197 09:28:33.225305 == TX Byte 1 ==
8198 09:28:33.231812 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8199 09:28:33.235690 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8200 09:28:33.235814 ==
8201 09:28:33.239022 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 09:28:33.241801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 09:28:33.241913 ==
8204 09:28:33.256811
8205 09:28:33.260312 TX Vref early break, caculate TX vref
8206 09:28:33.263451 TX Vref=16, minBit 1, minWin=22, winSum=373
8207 09:28:33.266550 TX Vref=18, minBit 0, minWin=23, winSum=385
8208 09:28:33.270073 TX Vref=20, minBit 1, minWin=23, winSum=393
8209 09:28:33.273246 TX Vref=22, minBit 7, minWin=23, winSum=400
8210 09:28:33.276857 TX Vref=24, minBit 3, minWin=24, winSum=408
8211 09:28:33.283552 TX Vref=26, minBit 1, minWin=24, winSum=408
8212 09:28:33.286861 TX Vref=28, minBit 0, minWin=24, winSum=408
8213 09:28:33.289956 TX Vref=30, minBit 2, minWin=23, winSum=398
8214 09:28:33.293011 TX Vref=32, minBit 5, minWin=23, winSum=389
8215 09:28:33.296507 TX Vref=34, minBit 1, minWin=23, winSum=383
8216 09:28:33.302955 [TxChooseVref] Worse bit 3, Min win 24, Win sum 408, Final Vref 24
8217 09:28:33.303077
8218 09:28:33.306095 Final TX Range 0 Vref 24
8219 09:28:33.306214
8220 09:28:33.306314 ==
8221 09:28:33.309858 Dram Type= 6, Freq= 0, CH_0, rank 1
8222 09:28:33.312608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8223 09:28:33.312693 ==
8224 09:28:33.312758
8225 09:28:33.312818
8226 09:28:33.316069 TX Vref Scan disable
8227 09:28:33.322901 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8228 09:28:33.323010 == TX Byte 0 ==
8229 09:28:33.326043 u2DelayCellOfst[0]=15 cells (4 PI)
8230 09:28:33.329125 u2DelayCellOfst[1]=18 cells (5 PI)
8231 09:28:33.332813 u2DelayCellOfst[2]=15 cells (4 PI)
8232 09:28:33.335896 u2DelayCellOfst[3]=15 cells (4 PI)
8233 09:28:33.339105 u2DelayCellOfst[4]=11 cells (3 PI)
8234 09:28:33.342320 u2DelayCellOfst[5]=0 cells (0 PI)
8235 09:28:33.346266 u2DelayCellOfst[6]=18 cells (5 PI)
8236 09:28:33.349591 u2DelayCellOfst[7]=22 cells (6 PI)
8237 09:28:33.352432 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8238 09:28:33.355568 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8239 09:28:33.359142 == TX Byte 1 ==
8240 09:28:33.362056 u2DelayCellOfst[8]=0 cells (0 PI)
8241 09:28:33.365990 u2DelayCellOfst[9]=0 cells (0 PI)
8242 09:28:33.368859 u2DelayCellOfst[10]=3 cells (1 PI)
8243 09:28:33.368941 u2DelayCellOfst[11]=0 cells (0 PI)
8244 09:28:33.372228 u2DelayCellOfst[12]=11 cells (3 PI)
8245 09:28:33.375628 u2DelayCellOfst[13]=11 cells (3 PI)
8246 09:28:33.378933 u2DelayCellOfst[14]=15 cells (4 PI)
8247 09:28:33.382387 u2DelayCellOfst[15]=7 cells (2 PI)
8248 09:28:33.388615 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8249 09:28:33.392163 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8250 09:28:33.392246 DramC Write-DBI on
8251 09:28:33.395815 ==
8252 09:28:33.395897 Dram Type= 6, Freq= 0, CH_0, rank 1
8253 09:28:33.402151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 09:28:33.402247 ==
8255 09:28:33.402316
8256 09:28:33.402403
8257 09:28:33.405275 TX Vref Scan disable
8258 09:28:33.405368 == TX Byte 0 ==
8259 09:28:33.411961 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8260 09:28:33.412062 == TX Byte 1 ==
8261 09:28:33.414919 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8262 09:28:33.418321 DramC Write-DBI off
8263 09:28:33.418441
8264 09:28:33.418535 [DATLAT]
8265 09:28:33.421460 Freq=1600, CH0 RK1
8266 09:28:33.421580
8267 09:28:33.421672 DATLAT Default: 0xf
8268 09:28:33.424974 0, 0xFFFF, sum = 0
8269 09:28:33.425109 1, 0xFFFF, sum = 0
8270 09:28:33.428066 2, 0xFFFF, sum = 0
8271 09:28:33.428217 3, 0xFFFF, sum = 0
8272 09:28:33.431699 4, 0xFFFF, sum = 0
8273 09:28:33.434698 5, 0xFFFF, sum = 0
8274 09:28:33.434871 6, 0xFFFF, sum = 0
8275 09:28:33.438243 7, 0xFFFF, sum = 0
8276 09:28:33.438447 8, 0xFFFF, sum = 0
8277 09:28:33.441364 9, 0xFFFF, sum = 0
8278 09:28:33.441565 10, 0xFFFF, sum = 0
8279 09:28:33.444988 11, 0xFFFF, sum = 0
8280 09:28:33.445230 12, 0xFFFF, sum = 0
8281 09:28:33.447955 13, 0xFFFF, sum = 0
8282 09:28:33.448403 14, 0x0, sum = 1
8283 09:28:33.451587 15, 0x0, sum = 2
8284 09:28:33.451976 16, 0x0, sum = 3
8285 09:28:33.454513 17, 0x0, sum = 4
8286 09:28:33.454902 best_step = 15
8287 09:28:33.455202
8288 09:28:33.455479 ==
8289 09:28:33.458366 Dram Type= 6, Freq= 0, CH_0, rank 1
8290 09:28:33.464818 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8291 09:28:33.465320 ==
8292 09:28:33.465650 RX Vref Scan: 0
8293 09:28:33.465954
8294 09:28:33.468666 RX Vref 0 -> 0, step: 1
8295 09:28:33.469185
8296 09:28:33.471736 RX Delay 11 -> 252, step: 4
8297 09:28:33.474484 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8298 09:28:33.477652 iDelay=191, Bit 1, Center 134 (79 ~ 190) 112
8299 09:28:33.481080 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8300 09:28:33.487415 iDelay=191, Bit 3, Center 128 (75 ~ 182) 108
8301 09:28:33.491164 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8302 09:28:33.494096 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8303 09:28:33.497636 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8304 09:28:33.500492 iDelay=191, Bit 7, Center 138 (87 ~ 190) 104
8305 09:28:33.506975 iDelay=191, Bit 8, Center 116 (63 ~ 170) 108
8306 09:28:33.510644 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8307 09:28:33.514142 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8308 09:28:33.517166 iDelay=191, Bit 11, Center 120 (67 ~ 174) 108
8309 09:28:33.524310 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8310 09:28:33.526884 iDelay=191, Bit 13, Center 132 (79 ~ 186) 108
8311 09:28:33.530035 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8312 09:28:33.533683 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8313 09:28:33.533916 ==
8314 09:28:33.536855 Dram Type= 6, Freq= 0, CH_0, rank 1
8315 09:28:33.543725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 09:28:33.543929 ==
8317 09:28:33.544104 DQS Delay:
8318 09:28:33.544264 DQS0 = 0, DQS1 = 0
8319 09:28:33.546778 DQM Delay:
8320 09:28:33.546951 DQM0 = 129, DQM1 = 125
8321 09:28:33.550357 DQ Delay:
8322 09:28:33.553500 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8323 09:28:33.556597 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =138
8324 09:28:33.559830 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8325 09:28:33.563621 DQ12 =128, DQ13 =132, DQ14 =136, DQ15 =132
8326 09:28:33.563769
8327 09:28:33.563885
8328 09:28:33.564005
8329 09:28:33.566842 [DramC_TX_OE_Calibration] TA2
8330 09:28:33.569597 Original DQ_B0 (3 6) =30, OEN = 27
8331 09:28:33.573302 Original DQ_B1 (3 6) =30, OEN = 27
8332 09:28:33.576430 24, 0x0, End_B0=24 End_B1=24
8333 09:28:33.576632 25, 0x0, End_B0=25 End_B1=25
8334 09:28:33.579508 26, 0x0, End_B0=26 End_B1=26
8335 09:28:33.583385 27, 0x0, End_B0=27 End_B1=27
8336 09:28:33.586281 28, 0x0, End_B0=28 End_B1=28
8337 09:28:33.589805 29, 0x0, End_B0=29 End_B1=29
8338 09:28:33.589905 30, 0x0, End_B0=30 End_B1=30
8339 09:28:33.592768 31, 0x4141, End_B0=30 End_B1=30
8340 09:28:33.596179 Byte0 end_step=30 best_step=27
8341 09:28:33.599759 Byte1 end_step=30 best_step=27
8342 09:28:33.602943 Byte0 TX OE(2T, 0.5T) = (3, 3)
8343 09:28:33.606095 Byte1 TX OE(2T, 0.5T) = (3, 3)
8344 09:28:33.606185
8345 09:28:33.606265
8346 09:28:33.612933 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8347 09:28:33.616243 CH0 RK1: MR19=303, MR18=1E01
8348 09:28:33.622486 CH0_RK1: MR19=0x303, MR18=0x1E01, DQSOSC=394, MR23=63, INC=23, DEC=15
8349 09:28:33.625944 [RxdqsGatingPostProcess] freq 1600
8350 09:28:33.629351 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8351 09:28:33.632479 best DQS0 dly(2T, 0.5T) = (1, 1)
8352 09:28:33.635617 best DQS1 dly(2T, 0.5T) = (1, 1)
8353 09:28:33.638967 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8354 09:28:33.642532 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8355 09:28:33.645423 best DQS0 dly(2T, 0.5T) = (1, 1)
8356 09:28:33.648723 best DQS1 dly(2T, 0.5T) = (1, 1)
8357 09:28:33.652222 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8358 09:28:33.655499 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8359 09:28:33.658662 Pre-setting of DQS Precalculation
8360 09:28:33.662136 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8361 09:28:33.662255 ==
8362 09:28:33.665374 Dram Type= 6, Freq= 0, CH_1, rank 0
8363 09:28:33.671804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 09:28:33.671891 ==
8365 09:28:33.675374 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8366 09:28:33.682082 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8367 09:28:33.685414 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8368 09:28:33.691986 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8369 09:28:33.699595 [CA 0] Center 41 (12~70) winsize 59
8370 09:28:33.702867 [CA 1] Center 41 (12~71) winsize 60
8371 09:28:33.706319 [CA 2] Center 37 (8~66) winsize 59
8372 09:28:33.709452 [CA 3] Center 36 (7~65) winsize 59
8373 09:28:33.713076 [CA 4] Center 37 (7~67) winsize 61
8374 09:28:33.716210 [CA 5] Center 36 (7~65) winsize 59
8375 09:28:33.716367
8376 09:28:33.719307 [CmdBusTrainingLP45] Vref(ca) range 0: 28
8377 09:28:33.719488
8378 09:28:33.725964 [CATrainingPosCal] consider 1 rank data
8379 09:28:33.726189 u2DelayCellTimex100 = 258/100 ps
8380 09:28:33.732632 CA0 delay=41 (12~70),Diff = 5 PI (18 cell)
8381 09:28:33.736093 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8382 09:28:33.739481 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8383 09:28:33.742397 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8384 09:28:33.745754 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8385 09:28:33.748939 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8386 09:28:33.749363
8387 09:28:33.752225 CA PerBit enable=1, Macro0, CA PI delay=36
8388 09:28:33.752702
8389 09:28:33.755473 [CBTSetCACLKResult] CA Dly = 36
8390 09:28:33.759423 CS Dly: 8 (0~39)
8391 09:28:33.762486 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8392 09:28:33.765537 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8393 09:28:33.765968 ==
8394 09:28:33.769004 Dram Type= 6, Freq= 0, CH_1, rank 1
8395 09:28:33.775421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8396 09:28:33.775828 ==
8397 09:28:33.779245 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8398 09:28:33.785120 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8399 09:28:33.788893 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8400 09:28:33.795124 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8401 09:28:33.803006 [CA 0] Center 43 (14~72) winsize 59
8402 09:28:33.806695 [CA 1] Center 43 (13~73) winsize 61
8403 09:28:33.810187 [CA 2] Center 37 (8~67) winsize 60
8404 09:28:33.813521 [CA 3] Center 37 (8~67) winsize 60
8405 09:28:33.816245 [CA 4] Center 37 (8~67) winsize 60
8406 09:28:33.819985 [CA 5] Center 37 (8~67) winsize 60
8407 09:28:33.820400
8408 09:28:33.822740 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8409 09:28:33.823156
8410 09:28:33.826491 [CATrainingPosCal] consider 2 rank data
8411 09:28:33.829618 u2DelayCellTimex100 = 258/100 ps
8412 09:28:33.833154 CA0 delay=42 (14~70),Diff = 6 PI (22 cell)
8413 09:28:33.839593 CA1 delay=42 (13~71),Diff = 6 PI (22 cell)
8414 09:28:33.842729 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8415 09:28:33.846726 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8416 09:28:33.849484 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8417 09:28:33.852503 CA5 delay=36 (8~65),Diff = 0 PI (0 cell)
8418 09:28:33.853014
8419 09:28:33.855838 CA PerBit enable=1, Macro0, CA PI delay=36
8420 09:28:33.856377
8421 09:28:33.859433 [CBTSetCACLKResult] CA Dly = 36
8422 09:28:33.862704 CS Dly: 10 (0~43)
8423 09:28:33.865629 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8424 09:28:33.869267 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8425 09:28:33.869786
8426 09:28:33.872366 ----->DramcWriteLeveling(PI) begin...
8427 09:28:33.872780 ==
8428 09:28:33.875656 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 09:28:33.882865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 09:28:33.883377 ==
8431 09:28:33.885844 Write leveling (Byte 0): 23 => 23
8432 09:28:33.889303 Write leveling (Byte 1): 26 => 26
8433 09:28:33.889898 DramcWriteLeveling(PI) end<-----
8434 09:28:33.892066
8435 09:28:33.892472 ==
8436 09:28:33.895457 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 09:28:33.898614 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 09:28:33.899025 ==
8439 09:28:33.901744 [Gating] SW mode calibration
8440 09:28:33.908606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8441 09:28:33.912310 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8442 09:28:33.918392 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8443 09:28:33.921636 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8444 09:28:33.925059 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8445 09:28:33.931732 1 4 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8446 09:28:33.935199 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8447 09:28:33.938111 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8448 09:28:33.944982 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8449 09:28:33.948088 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8450 09:28:33.951873 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8451 09:28:33.958606 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8452 09:28:33.961426 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8453 09:28:33.964961 1 5 12 | B1->B0 | 3030 2525 | 0 0 | (0 0) (1 0)
8454 09:28:33.971430 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8455 09:28:33.974815 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8456 09:28:33.977725 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8457 09:28:33.984543 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8458 09:28:33.987632 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8459 09:28:33.991370 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8460 09:28:33.998071 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8461 09:28:34.000898 1 6 12 | B1->B0 | 3838 4444 | 1 0 | (1 1) (0 0)
8462 09:28:34.004268 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8463 09:28:34.010755 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8464 09:28:34.014127 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8465 09:28:34.016962 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8466 09:28:34.023884 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8467 09:28:34.027579 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8468 09:28:34.030232 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8469 09:28:34.037214 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8470 09:28:34.040581 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8471 09:28:34.043486 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 09:28:34.050014 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 09:28:34.053724 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 09:28:34.059791 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 09:28:34.063487 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 09:28:34.066505 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 09:28:34.073250 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8478 09:28:34.076728 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8479 09:28:34.080070 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8480 09:28:34.083225 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8481 09:28:34.089996 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 09:28:34.093042 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 09:28:34.099898 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 09:28:34.102913 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8485 09:28:34.106248 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8486 09:28:34.112679 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8487 09:28:34.113121 Total UI for P1: 0, mck2ui 16
8488 09:28:34.116382 best dqsien dly found for B0: ( 1, 9, 10)
8489 09:28:34.119799 Total UI for P1: 0, mck2ui 16
8490 09:28:34.122981 best dqsien dly found for B1: ( 1, 9, 10)
8491 09:28:34.126444 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8492 09:28:34.132551 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8493 09:28:34.132967
8494 09:28:34.135631 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8495 09:28:34.139144 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8496 09:28:34.142525 [Gating] SW calibration Done
8497 09:28:34.142944 ==
8498 09:28:34.145988 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 09:28:34.148863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 09:28:34.149419 ==
8501 09:28:34.152421 RX Vref Scan: 0
8502 09:28:34.152838
8503 09:28:34.153162 RX Vref 0 -> 0, step: 1
8504 09:28:34.153464
8505 09:28:34.155742 RX Delay 0 -> 252, step: 8
8506 09:28:34.159029 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8507 09:28:34.165787 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8508 09:28:34.168596 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8509 09:28:34.171993 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8510 09:28:34.175524 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8511 09:28:34.178627 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8512 09:28:34.185464 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8513 09:28:34.188427 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8514 09:28:34.192112 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8515 09:28:34.195183 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8516 09:28:34.198192 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8517 09:28:34.205041 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8518 09:28:34.208545 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8519 09:28:34.211589 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8520 09:28:34.214656 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8521 09:28:34.221657 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8522 09:28:34.222073 ==
8523 09:28:34.224749 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 09:28:34.227978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 09:28:34.228398 ==
8526 09:28:34.228724 DQS Delay:
8527 09:28:34.231163 DQS0 = 0, DQS1 = 0
8528 09:28:34.231670 DQM Delay:
8529 09:28:34.234892 DQM0 = 137, DQM1 = 128
8530 09:28:34.235463 DQ Delay:
8531 09:28:34.238085 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =131
8532 09:28:34.241272 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8533 09:28:34.244810 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8534 09:28:34.247600 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8535 09:28:34.248036
8536 09:28:34.251082
8537 09:28:34.251492 ==
8538 09:28:34.254133 Dram Type= 6, Freq= 0, CH_1, rank 0
8539 09:28:34.257672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8540 09:28:34.258366 ==
8541 09:28:34.258869
8542 09:28:34.259409
8543 09:28:34.261060 TX Vref Scan disable
8544 09:28:34.261561 == TX Byte 0 ==
8545 09:28:34.267283 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8546 09:28:34.271248 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8547 09:28:34.271682 == TX Byte 1 ==
8548 09:28:34.277438 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8549 09:28:34.280930 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8550 09:28:34.281367 ==
8551 09:28:34.283913 Dram Type= 6, Freq= 0, CH_1, rank 0
8552 09:28:34.286955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8553 09:28:34.287392 ==
8554 09:28:34.300933
8555 09:28:34.303994 TX Vref early break, caculate TX vref
8556 09:28:34.307578 TX Vref=16, minBit 0, minWin=21, winSum=372
8557 09:28:34.310609 TX Vref=18, minBit 5, minWin=22, winSum=384
8558 09:28:34.314007 TX Vref=20, minBit 0, minWin=23, winSum=394
8559 09:28:34.317122 TX Vref=22, minBit 5, minWin=23, winSum=404
8560 09:28:34.321108 TX Vref=24, minBit 0, minWin=25, winSum=415
8561 09:28:34.327032 TX Vref=26, minBit 0, minWin=24, winSum=418
8562 09:28:34.330894 TX Vref=28, minBit 0, minWin=24, winSum=418
8563 09:28:34.333864 TX Vref=30, minBit 0, minWin=24, winSum=409
8564 09:28:34.337223 TX Vref=32, minBit 5, minWin=23, winSum=401
8565 09:28:34.340371 TX Vref=34, minBit 0, minWin=23, winSum=396
8566 09:28:34.346989 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 24
8567 09:28:34.347170
8568 09:28:34.350454 Final TX Range 0 Vref 24
8569 09:28:34.350663
8570 09:28:34.350914 ==
8571 09:28:34.353381 Dram Type= 6, Freq= 0, CH_1, rank 0
8572 09:28:34.356863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8573 09:28:34.357115 ==
8574 09:28:34.357409
8575 09:28:34.357704
8576 09:28:34.360450 TX Vref Scan disable
8577 09:28:34.366771 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8578 09:28:34.367439 == TX Byte 0 ==
8579 09:28:34.370102 u2DelayCellOfst[0]=18 cells (5 PI)
8580 09:28:34.373386 u2DelayCellOfst[1]=15 cells (4 PI)
8581 09:28:34.376970 u2DelayCellOfst[2]=0 cells (0 PI)
8582 09:28:34.379833 u2DelayCellOfst[3]=7 cells (2 PI)
8583 09:28:34.383844 u2DelayCellOfst[4]=11 cells (3 PI)
8584 09:28:34.386688 u2DelayCellOfst[5]=22 cells (6 PI)
8585 09:28:34.390445 u2DelayCellOfst[6]=22 cells (6 PI)
8586 09:28:34.393437 u2DelayCellOfst[7]=7 cells (2 PI)
8587 09:28:34.396598 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8588 09:28:34.399795 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8589 09:28:34.402958 == TX Byte 1 ==
8590 09:28:34.406487 u2DelayCellOfst[8]=0 cells (0 PI)
8591 09:28:34.409946 u2DelayCellOfst[9]=3 cells (1 PI)
8592 09:28:34.413612 u2DelayCellOfst[10]=11 cells (3 PI)
8593 09:28:34.414124 u2DelayCellOfst[11]=3 cells (1 PI)
8594 09:28:34.416507 u2DelayCellOfst[12]=15 cells (4 PI)
8595 09:28:34.420103 u2DelayCellOfst[13]=15 cells (4 PI)
8596 09:28:34.423007 u2DelayCellOfst[14]=18 cells (5 PI)
8597 09:28:34.426662 u2DelayCellOfst[15]=18 cells (5 PI)
8598 09:28:34.432842 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8599 09:28:34.436520 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8600 09:28:34.436941 DramC Write-DBI on
8601 09:28:34.437272 ==
8602 09:28:34.439828 Dram Type= 6, Freq= 0, CH_1, rank 0
8603 09:28:34.445991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8604 09:28:34.446554 ==
8605 09:28:34.446894
8606 09:28:34.447327
8607 09:28:34.449173 TX Vref Scan disable
8608 09:28:34.449609 == TX Byte 0 ==
8609 09:28:34.456093 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8610 09:28:34.456515 == TX Byte 1 ==
8611 09:28:34.459131 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8612 09:28:34.462497 DramC Write-DBI off
8613 09:28:34.462916
8614 09:28:34.463241 [DATLAT]
8615 09:28:34.465555 Freq=1600, CH1 RK0
8616 09:28:34.466002
8617 09:28:34.466395 DATLAT Default: 0xf
8618 09:28:34.468954 0, 0xFFFF, sum = 0
8619 09:28:34.469377 1, 0xFFFF, sum = 0
8620 09:28:34.472526 2, 0xFFFF, sum = 0
8621 09:28:34.472949 3, 0xFFFF, sum = 0
8622 09:28:34.475851 4, 0xFFFF, sum = 0
8623 09:28:34.476432 5, 0xFFFF, sum = 0
8624 09:28:34.478709 6, 0xFFFF, sum = 0
8625 09:28:34.479135 7, 0xFFFF, sum = 0
8626 09:28:34.482798 8, 0xFFFF, sum = 0
8627 09:28:34.483329 9, 0xFFFF, sum = 0
8628 09:28:34.485507 10, 0xFFFF, sum = 0
8629 09:28:34.489078 11, 0xFFFF, sum = 0
8630 09:28:34.489507 12, 0xFFFF, sum = 0
8631 09:28:34.492200 13, 0xFFFF, sum = 0
8632 09:28:34.492717 14, 0x0, sum = 1
8633 09:28:34.495563 15, 0x0, sum = 2
8634 09:28:34.495988 16, 0x0, sum = 3
8635 09:28:34.498581 17, 0x0, sum = 4
8636 09:28:34.499036 best_step = 15
8637 09:28:34.499366
8638 09:28:34.499674 ==
8639 09:28:34.502262 Dram Type= 6, Freq= 0, CH_1, rank 0
8640 09:28:34.505397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8641 09:28:34.505914 ==
8642 09:28:34.508658 RX Vref Scan: 1
8643 09:28:34.509078
8644 09:28:34.511940 Set Vref Range= 24 -> 127
8645 09:28:34.512483
8646 09:28:34.512878 RX Vref 24 -> 127, step: 1
8647 09:28:34.514971
8648 09:28:34.515408 RX Delay 11 -> 252, step: 4
8649 09:28:34.515531
8650 09:28:34.518247 Set Vref, RX VrefLevel [Byte0]: 24
8651 09:28:34.521066 [Byte1]: 24
8652 09:28:34.525460
8653 09:28:34.525541 Set Vref, RX VrefLevel [Byte0]: 25
8654 09:28:34.528487 [Byte1]: 25
8655 09:28:34.532807
8656 09:28:34.532887 Set Vref, RX VrefLevel [Byte0]: 26
8657 09:28:34.535931 [Byte1]: 26
8658 09:28:34.540190
8659 09:28:34.543199 Set Vref, RX VrefLevel [Byte0]: 27
8660 09:28:34.546956 [Byte1]: 27
8661 09:28:34.547039
8662 09:28:34.550053 Set Vref, RX VrefLevel [Byte0]: 28
8663 09:28:34.553113 [Byte1]: 28
8664 09:28:34.553194
8665 09:28:34.557013 Set Vref, RX VrefLevel [Byte0]: 29
8666 09:28:34.559863 [Byte1]: 29
8667 09:28:34.563389
8668 09:28:34.563470 Set Vref, RX VrefLevel [Byte0]: 30
8669 09:28:34.566118 [Byte1]: 30
8670 09:28:34.570862
8671 09:28:34.570944 Set Vref, RX VrefLevel [Byte0]: 31
8672 09:28:34.574059 [Byte1]: 31
8673 09:28:34.578273
8674 09:28:34.578448 Set Vref, RX VrefLevel [Byte0]: 32
8675 09:28:34.581783 [Byte1]: 32
8676 09:28:34.585823
8677 09:28:34.585905 Set Vref, RX VrefLevel [Byte0]: 33
8678 09:28:34.589355 [Byte1]: 33
8679 09:28:34.593895
8680 09:28:34.593976 Set Vref, RX VrefLevel [Byte0]: 34
8681 09:28:34.596656 [Byte1]: 34
8682 09:28:34.600908
8683 09:28:34.600989 Set Vref, RX VrefLevel [Byte0]: 35
8684 09:28:34.604358 [Byte1]: 35
8685 09:28:34.608469
8686 09:28:34.608551 Set Vref, RX VrefLevel [Byte0]: 36
8687 09:28:34.611983 [Byte1]: 36
8688 09:28:34.616367
8689 09:28:34.616448 Set Vref, RX VrefLevel [Byte0]: 37
8690 09:28:34.619449 [Byte1]: 37
8691 09:28:34.623612
8692 09:28:34.623693 Set Vref, RX VrefLevel [Byte0]: 38
8693 09:28:34.627293 [Byte1]: 38
8694 09:28:34.631535
8695 09:28:34.631616 Set Vref, RX VrefLevel [Byte0]: 39
8696 09:28:34.634558 [Byte1]: 39
8697 09:28:34.638995
8698 09:28:34.639077 Set Vref, RX VrefLevel [Byte0]: 40
8699 09:28:34.642553 [Byte1]: 40
8700 09:28:34.646935
8701 09:28:34.647016 Set Vref, RX VrefLevel [Byte0]: 41
8702 09:28:34.650464 [Byte1]: 41
8703 09:28:34.654119
8704 09:28:34.654237 Set Vref, RX VrefLevel [Byte0]: 42
8705 09:28:34.657884 [Byte1]: 42
8706 09:28:34.662098
8707 09:28:34.662203 Set Vref, RX VrefLevel [Byte0]: 43
8708 09:28:34.665103 [Byte1]: 43
8709 09:28:34.669395
8710 09:28:34.669479 Set Vref, RX VrefLevel [Byte0]: 44
8711 09:28:34.672998 [Byte1]: 44
8712 09:28:34.677261
8713 09:28:34.677345 Set Vref, RX VrefLevel [Byte0]: 45
8714 09:28:34.680379 [Byte1]: 45
8715 09:28:34.684930
8716 09:28:34.685014 Set Vref, RX VrefLevel [Byte0]: 46
8717 09:28:34.688441 [Byte1]: 46
8718 09:28:34.692487
8719 09:28:34.692577 Set Vref, RX VrefLevel [Byte0]: 47
8720 09:28:34.695521 [Byte1]: 47
8721 09:28:34.700453
8722 09:28:34.700550 Set Vref, RX VrefLevel [Byte0]: 48
8723 09:28:34.703372 [Byte1]: 48
8724 09:28:34.707641
8725 09:28:34.707755 Set Vref, RX VrefLevel [Byte0]: 49
8726 09:28:34.711309 [Byte1]: 49
8727 09:28:34.715480
8728 09:28:34.715605 Set Vref, RX VrefLevel [Byte0]: 50
8729 09:28:34.718763 [Byte1]: 50
8730 09:28:34.722857
8731 09:28:34.723004 Set Vref, RX VrefLevel [Byte0]: 51
8732 09:28:34.726037 [Byte1]: 51
8733 09:28:34.730849
8734 09:28:34.731027 Set Vref, RX VrefLevel [Byte0]: 52
8735 09:28:34.734133 [Byte1]: 52
8736 09:28:34.738331
8737 09:28:34.738578 Set Vref, RX VrefLevel [Byte0]: 53
8738 09:28:34.741544 [Byte1]: 53
8739 09:28:34.745920
8740 09:28:34.746247 Set Vref, RX VrefLevel [Byte0]: 54
8741 09:28:34.749643 [Byte1]: 54
8742 09:28:34.754350
8743 09:28:34.754923 Set Vref, RX VrefLevel [Byte0]: 55
8744 09:28:34.757166 [Byte1]: 55
8745 09:28:34.761464
8746 09:28:34.761895 Set Vref, RX VrefLevel [Byte0]: 56
8747 09:28:34.764689 [Byte1]: 56
8748 09:28:34.769333
8749 09:28:34.769743 Set Vref, RX VrefLevel [Byte0]: 57
8750 09:28:34.772326 [Byte1]: 57
8751 09:28:34.776584
8752 09:28:34.777097 Set Vref, RX VrefLevel [Byte0]: 58
8753 09:28:34.780191 [Byte1]: 58
8754 09:28:34.784302
8755 09:28:34.784713 Set Vref, RX VrefLevel [Byte0]: 59
8756 09:28:34.787377 [Byte1]: 59
8757 09:28:34.791533
8758 09:28:34.791944 Set Vref, RX VrefLevel [Byte0]: 60
8759 09:28:34.795195 [Byte1]: 60
8760 09:28:34.799259
8761 09:28:34.799801 Set Vref, RX VrefLevel [Byte0]: 61
8762 09:28:34.802841 [Byte1]: 61
8763 09:28:34.807118
8764 09:28:34.807530 Set Vref, RX VrefLevel [Byte0]: 62
8765 09:28:34.810275 [Byte1]: 62
8766 09:28:34.814494
8767 09:28:34.814925 Set Vref, RX VrefLevel [Byte0]: 63
8768 09:28:34.817897 [Byte1]: 63
8769 09:28:34.822023
8770 09:28:34.822527 Set Vref, RX VrefLevel [Byte0]: 64
8771 09:28:34.825371 [Byte1]: 64
8772 09:28:34.829648
8773 09:28:34.830228 Set Vref, RX VrefLevel [Byte0]: 65
8774 09:28:34.832919 [Byte1]: 65
8775 09:28:34.837181
8776 09:28:34.837767 Set Vref, RX VrefLevel [Byte0]: 66
8777 09:28:34.840695 [Byte1]: 66
8778 09:28:34.844851
8779 09:28:34.845404 Set Vref, RX VrefLevel [Byte0]: 67
8780 09:28:34.848421 [Byte1]: 67
8781 09:28:34.852582
8782 09:28:34.853003 Set Vref, RX VrefLevel [Byte0]: 68
8783 09:28:34.855939 [Byte1]: 68
8784 09:28:34.860316
8785 09:28:34.860732 Set Vref, RX VrefLevel [Byte0]: 69
8786 09:28:34.863675 [Byte1]: 69
8787 09:28:34.868352
8788 09:28:34.868774 Set Vref, RX VrefLevel [Byte0]: 70
8789 09:28:34.871126 [Byte1]: 70
8790 09:28:34.875526
8791 09:28:34.876248 Set Vref, RX VrefLevel [Byte0]: 71
8792 09:28:34.878981 [Byte1]: 71
8793 09:28:34.883126
8794 09:28:34.883542 Set Vref, RX VrefLevel [Byte0]: 72
8795 09:28:34.886239 [Byte1]: 72
8796 09:28:34.890641
8797 09:28:34.891058 Set Vref, RX VrefLevel [Byte0]: 73
8798 09:28:34.894649 [Byte1]: 73
8799 09:28:34.898615
8800 09:28:34.899034 Final RX Vref Byte 0 = 54 to rank0
8801 09:28:34.901787 Final RX Vref Byte 1 = 58 to rank0
8802 09:28:34.905068 Final RX Vref Byte 0 = 54 to rank1
8803 09:28:34.908156 Final RX Vref Byte 1 = 58 to rank1==
8804 09:28:34.911146 Dram Type= 6, Freq= 0, CH_1, rank 0
8805 09:28:34.918484 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 09:28:34.918909 ==
8807 09:28:34.919238 DQS Delay:
8808 09:28:34.921325 DQS0 = 0, DQS1 = 0
8809 09:28:34.921742 DQM Delay:
8810 09:28:34.922076 DQM0 = 133, DQM1 = 127
8811 09:28:34.924956 DQ Delay:
8812 09:28:34.927876 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8813 09:28:34.931453 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8814 09:28:34.934436 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8815 09:28:34.938009 DQ12 =136, DQ13 =136, DQ14 =136, DQ15 =138
8816 09:28:34.938595
8817 09:28:34.939047
8818 09:28:34.939481
8819 09:28:34.940929 [DramC_TX_OE_Calibration] TA2
8820 09:28:34.944381 Original DQ_B0 (3 6) =30, OEN = 27
8821 09:28:34.947596 Original DQ_B1 (3 6) =30, OEN = 27
8822 09:28:34.951063 24, 0x0, End_B0=24 End_B1=24
8823 09:28:34.954035 25, 0x0, End_B0=25 End_B1=25
8824 09:28:34.954518 26, 0x0, End_B0=26 End_B1=26
8825 09:28:34.957553 27, 0x0, End_B0=27 End_B1=27
8826 09:28:34.960735 28, 0x0, End_B0=28 End_B1=28
8827 09:28:34.964258 29, 0x0, End_B0=29 End_B1=29
8828 09:28:34.964701 30, 0x0, End_B0=30 End_B1=30
8829 09:28:34.967543 31, 0x4141, End_B0=30 End_B1=30
8830 09:28:34.970485 Byte0 end_step=30 best_step=27
8831 09:28:34.974196 Byte1 end_step=30 best_step=27
8832 09:28:34.977331 Byte0 TX OE(2T, 0.5T) = (3, 3)
8833 09:28:34.980444 Byte1 TX OE(2T, 0.5T) = (3, 3)
8834 09:28:34.980861
8835 09:28:34.981187
8836 09:28:34.987035 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8837 09:28:34.990304 CH1 RK0: MR19=303, MR18=1A0F
8838 09:28:34.996928 CH1_RK0: MR19=0x303, MR18=0x1A0F, DQSOSC=396, MR23=63, INC=23, DEC=15
8839 09:28:34.997483
8840 09:28:35.000621 ----->DramcWriteLeveling(PI) begin...
8841 09:28:35.001043 ==
8842 09:28:35.003671 Dram Type= 6, Freq= 0, CH_1, rank 1
8843 09:28:35.006743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8844 09:28:35.007256 ==
8845 09:28:35.010057 Write leveling (Byte 0): 25 => 25
8846 09:28:35.013474 Write leveling (Byte 1): 27 => 27
8847 09:28:35.016998 DramcWriteLeveling(PI) end<-----
8848 09:28:35.017540
8849 09:28:35.018008 ==
8850 09:28:35.019972 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 09:28:35.026578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 09:28:35.027142 ==
8853 09:28:35.027623 [Gating] SW mode calibration
8854 09:28:35.036140 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8855 09:28:35.039560 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8856 09:28:35.046046 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 09:28:35.049389 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 09:28:35.053064 1 4 8 | B1->B0 | 2626 2323 | 1 0 | (0 0) (0 0)
8859 09:28:35.059724 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8860 09:28:35.062690 1 4 16 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 1)
8861 09:28:35.066379 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8862 09:28:35.073305 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8863 09:28:35.076028 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8864 09:28:35.079251 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8865 09:28:35.085928 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8866 09:28:35.089035 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8867 09:28:35.092721 1 5 12 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 0)
8868 09:28:35.099236 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
8869 09:28:35.102327 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8870 09:28:35.105525 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8871 09:28:35.112208 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8872 09:28:35.115931 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8873 09:28:35.118742 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8874 09:28:35.125429 1 6 8 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
8875 09:28:35.128812 1 6 12 | B1->B0 | 4545 2626 | 0 0 | (0 0) (0 0)
8876 09:28:35.132414 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8877 09:28:35.138830 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8878 09:28:35.141881 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8879 09:28:35.145563 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8880 09:28:35.151644 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8881 09:28:35.154914 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8882 09:28:35.158544 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8883 09:28:35.165262 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8884 09:28:35.168371 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 09:28:35.171432 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 09:28:35.178274 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8887 09:28:35.181415 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8888 09:28:35.185116 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8889 09:28:35.191224 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8890 09:28:35.194411 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8891 09:28:35.197978 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8892 09:28:35.204588 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8893 09:28:35.207829 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8894 09:28:35.210980 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8895 09:28:35.217406 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 09:28:35.220935 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 09:28:35.224104 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 09:28:35.231286 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8899 09:28:35.234432 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8900 09:28:35.237286 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8901 09:28:35.240806 Total UI for P1: 0, mck2ui 16
8902 09:28:35.243798 best dqsien dly found for B0: ( 1, 9, 10)
8903 09:28:35.247621 Total UI for P1: 0, mck2ui 16
8904 09:28:35.250635 best dqsien dly found for B1: ( 1, 9, 10)
8905 09:28:35.254251 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8906 09:28:35.257325 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8907 09:28:35.257621
8908 09:28:35.260798 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8909 09:28:35.267332 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8910 09:28:35.267745 [Gating] SW calibration Done
8911 09:28:35.268218 ==
8912 09:28:35.270990 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 09:28:35.277396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 09:28:35.277897 ==
8915 09:28:35.278270 RX Vref Scan: 0
8916 09:28:35.278505
8917 09:28:35.280677 RX Vref 0 -> 0, step: 1
8918 09:28:35.280971
8919 09:28:35.284189 RX Delay 0 -> 252, step: 8
8920 09:28:35.287789 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8921 09:28:35.290943 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8922 09:28:35.293762 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8923 09:28:35.300323 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8924 09:28:35.303842 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8925 09:28:35.307200 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8926 09:28:35.309967 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8927 09:28:35.313508 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8928 09:28:35.320607 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8929 09:28:35.323958 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8930 09:28:35.327220 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8931 09:28:35.330232 iDelay=208, Bit 11, Center 123 (64 ~ 183) 120
8932 09:28:35.333775 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8933 09:28:35.339976 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8934 09:28:35.343596 iDelay=208, Bit 14, Center 131 (72 ~ 191) 120
8935 09:28:35.346785 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8936 09:28:35.347206 ==
8937 09:28:35.350346 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 09:28:35.353258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 09:28:35.356853 ==
8940 09:28:35.357270 DQS Delay:
8941 09:28:35.357597 DQS0 = 0, DQS1 = 0
8942 09:28:35.360054 DQM Delay:
8943 09:28:35.360756 DQM0 = 136, DQM1 = 129
8944 09:28:35.363418 DQ Delay:
8945 09:28:35.367144 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8946 09:28:35.369821 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8947 09:28:35.373581 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8948 09:28:35.376239 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8949 09:28:35.376657
8950 09:28:35.376992
8951 09:28:35.377318 ==
8952 09:28:35.379965 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 09:28:35.383322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 09:28:35.383751 ==
8955 09:28:35.386263
8956 09:28:35.386675
8957 09:28:35.387001 TX Vref Scan disable
8958 09:28:35.389800 == TX Byte 0 ==
8959 09:28:35.392822 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8960 09:28:35.395939 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8961 09:28:35.399836 == TX Byte 1 ==
8962 09:28:35.402953 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8963 09:28:35.406064 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8964 09:28:35.406524 ==
8965 09:28:35.409677 Dram Type= 6, Freq= 0, CH_1, rank 1
8966 09:28:35.415834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8967 09:28:35.416262 ==
8968 09:28:35.428598
8969 09:28:35.431466 TX Vref early break, caculate TX vref
8970 09:28:35.434961 TX Vref=16, minBit 5, minWin=23, winSum=389
8971 09:28:35.437753 TX Vref=18, minBit 0, minWin=24, winSum=398
8972 09:28:35.440933 TX Vref=20, minBit 0, minWin=24, winSum=404
8973 09:28:35.444336 TX Vref=22, minBit 1, minWin=25, winSum=413
8974 09:28:35.448069 TX Vref=24, minBit 1, minWin=25, winSum=424
8975 09:28:35.454448 TX Vref=26, minBit 0, minWin=25, winSum=427
8976 09:28:35.457510 TX Vref=28, minBit 0, minWin=25, winSum=424
8977 09:28:35.461012 TX Vref=30, minBit 0, minWin=25, winSum=422
8978 09:28:35.463841 TX Vref=32, minBit 1, minWin=24, winSum=409
8979 09:28:35.467446 TX Vref=34, minBit 0, minWin=24, winSum=401
8980 09:28:35.473963 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 26
8981 09:28:35.474435
8982 09:28:35.477041 Final TX Range 0 Vref 26
8983 09:28:35.477457
8984 09:28:35.477780 ==
8985 09:28:35.480578 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 09:28:35.484381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 09:28:35.484928 ==
8988 09:28:35.485383
8989 09:28:35.485700
8990 09:28:35.487228 TX Vref Scan disable
8991 09:28:35.493874 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8992 09:28:35.494322 == TX Byte 0 ==
8993 09:28:35.497310 u2DelayCellOfst[0]=22 cells (6 PI)
8994 09:28:35.500515 u2DelayCellOfst[1]=15 cells (4 PI)
8995 09:28:35.503940 u2DelayCellOfst[2]=0 cells (0 PI)
8996 09:28:35.506879 u2DelayCellOfst[3]=7 cells (2 PI)
8997 09:28:35.510735 u2DelayCellOfst[4]=11 cells (3 PI)
8998 09:28:35.513599 u2DelayCellOfst[5]=22 cells (6 PI)
8999 09:28:35.516806 u2DelayCellOfst[6]=22 cells (6 PI)
9000 09:28:35.520718 u2DelayCellOfst[7]=7 cells (2 PI)
9001 09:28:35.523344 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9002 09:28:35.527082 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9003 09:28:35.530107 == TX Byte 1 ==
9004 09:28:35.533412 u2DelayCellOfst[8]=0 cells (0 PI)
9005 09:28:35.536827 u2DelayCellOfst[9]=7 cells (2 PI)
9006 09:28:35.539901 u2DelayCellOfst[10]=15 cells (4 PI)
9007 09:28:35.543347 u2DelayCellOfst[11]=7 cells (2 PI)
9008 09:28:35.543806 u2DelayCellOfst[12]=18 cells (5 PI)
9009 09:28:35.546312 u2DelayCellOfst[13]=18 cells (5 PI)
9010 09:28:35.549712 u2DelayCellOfst[14]=18 cells (5 PI)
9011 09:28:35.553280 u2DelayCellOfst[15]=18 cells (5 PI)
9012 09:28:35.559914 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9013 09:28:35.562874 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9014 09:28:35.565826 DramC Write-DBI on
9015 09:28:35.566263 ==
9016 09:28:35.569729 Dram Type= 6, Freq= 0, CH_1, rank 1
9017 09:28:35.572509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9018 09:28:35.572966 ==
9019 09:28:35.573292
9020 09:28:35.573592
9021 09:28:35.576176 TX Vref Scan disable
9022 09:28:35.576696 == TX Byte 0 ==
9023 09:28:35.582680 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9024 09:28:35.583127 == TX Byte 1 ==
9025 09:28:35.586105 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9026 09:28:35.589489 DramC Write-DBI off
9027 09:28:35.589902
9028 09:28:35.590268 [DATLAT]
9029 09:28:35.592563 Freq=1600, CH1 RK1
9030 09:28:35.592978
9031 09:28:35.593300 DATLAT Default: 0xf
9032 09:28:35.596339 0, 0xFFFF, sum = 0
9033 09:28:35.596762 1, 0xFFFF, sum = 0
9034 09:28:35.599375 2, 0xFFFF, sum = 0
9035 09:28:35.599799 3, 0xFFFF, sum = 0
9036 09:28:35.602421 4, 0xFFFF, sum = 0
9037 09:28:35.602936 5, 0xFFFF, sum = 0
9038 09:28:35.606093 6, 0xFFFF, sum = 0
9039 09:28:35.609193 7, 0xFFFF, sum = 0
9040 09:28:35.609711 8, 0xFFFF, sum = 0
9041 09:28:35.612770 9, 0xFFFF, sum = 0
9042 09:28:35.613194 10, 0xFFFF, sum = 0
9043 09:28:35.615956 11, 0xFFFF, sum = 0
9044 09:28:35.616473 12, 0xFFFF, sum = 0
9045 09:28:35.619116 13, 0xFFFF, sum = 0
9046 09:28:35.619583 14, 0x0, sum = 1
9047 09:28:35.622125 15, 0x0, sum = 2
9048 09:28:35.622580 16, 0x0, sum = 3
9049 09:28:35.625797 17, 0x0, sum = 4
9050 09:28:35.626314 best_step = 15
9051 09:28:35.626644
9052 09:28:35.626949 ==
9053 09:28:35.628734 Dram Type= 6, Freq= 0, CH_1, rank 1
9054 09:28:35.632471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9055 09:28:35.635587 ==
9056 09:28:35.636002 RX Vref Scan: 0
9057 09:28:35.636329
9058 09:28:35.638964 RX Vref 0 -> 0, step: 1
9059 09:28:35.639377
9060 09:28:35.639707 RX Delay 11 -> 252, step: 4
9061 09:28:35.646500 iDelay=199, Bit 0, Center 138 (87 ~ 190) 104
9062 09:28:35.649679 iDelay=199, Bit 1, Center 128 (75 ~ 182) 108
9063 09:28:35.652669 iDelay=199, Bit 2, Center 122 (67 ~ 178) 112
9064 09:28:35.656226 iDelay=199, Bit 3, Center 130 (79 ~ 182) 104
9065 09:28:35.663093 iDelay=199, Bit 4, Center 132 (75 ~ 190) 116
9066 09:28:35.666318 iDelay=199, Bit 5, Center 144 (91 ~ 198) 108
9067 09:28:35.669365 iDelay=199, Bit 6, Center 144 (91 ~ 198) 108
9068 09:28:35.672456 iDelay=199, Bit 7, Center 130 (79 ~ 182) 104
9069 09:28:35.676111 iDelay=199, Bit 8, Center 112 (55 ~ 170) 116
9070 09:28:35.683129 iDelay=199, Bit 9, Center 116 (63 ~ 170) 108
9071 09:28:35.685785 iDelay=199, Bit 10, Center 128 (75 ~ 182) 108
9072 09:28:35.689234 iDelay=199, Bit 11, Center 116 (63 ~ 170) 108
9073 09:28:35.692896 iDelay=199, Bit 12, Center 138 (83 ~ 194) 112
9074 09:28:35.695545 iDelay=199, Bit 13, Center 136 (83 ~ 190) 108
9075 09:28:35.702224 iDelay=199, Bit 14, Center 132 (75 ~ 190) 116
9076 09:28:35.705620 iDelay=199, Bit 15, Center 138 (83 ~ 194) 112
9077 09:28:35.706216 ==
9078 09:28:35.709203 Dram Type= 6, Freq= 0, CH_1, rank 1
9079 09:28:35.712147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9080 09:28:35.712624 ==
9081 09:28:35.715982 DQS Delay:
9082 09:28:35.716537 DQS0 = 0, DQS1 = 0
9083 09:28:35.716897 DQM Delay:
9084 09:28:35.718919 DQM0 = 133, DQM1 = 127
9085 09:28:35.719377 DQ Delay:
9086 09:28:35.721830 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9087 09:28:35.728517 DQ4 =132, DQ5 =144, DQ6 =144, DQ7 =130
9088 09:28:35.731633 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =116
9089 09:28:35.735626 DQ12 =138, DQ13 =136, DQ14 =132, DQ15 =138
9090 09:28:35.736173
9091 09:28:35.736503
9092 09:28:35.736807
9093 09:28:35.738630 [DramC_TX_OE_Calibration] TA2
9094 09:28:35.742037 Original DQ_B0 (3 6) =30, OEN = 27
9095 09:28:35.745010 Original DQ_B1 (3 6) =30, OEN = 27
9096 09:28:35.745481 24, 0x0, End_B0=24 End_B1=24
9097 09:28:35.748027 25, 0x0, End_B0=25 End_B1=25
9098 09:28:35.751518 26, 0x0, End_B0=26 End_B1=26
9099 09:28:35.755067 27, 0x0, End_B0=27 End_B1=27
9100 09:28:35.758202 28, 0x0, End_B0=28 End_B1=28
9101 09:28:35.758626 29, 0x0, End_B0=29 End_B1=29
9102 09:28:35.761399 30, 0x0, End_B0=30 End_B1=30
9103 09:28:35.764907 31, 0x4141, End_B0=30 End_B1=30
9104 09:28:35.767758 Byte0 end_step=30 best_step=27
9105 09:28:35.771178 Byte1 end_step=30 best_step=27
9106 09:28:35.774508 Byte0 TX OE(2T, 0.5T) = (3, 3)
9107 09:28:35.775033 Byte1 TX OE(2T, 0.5T) = (3, 3)
9108 09:28:35.775363
9109 09:28:35.778004
9110 09:28:35.784836 [DQSOSCAuto] RK1, (LSB)MR18= 0xd0a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 403 ps
9111 09:28:35.787866 CH1 RK1: MR19=303, MR18=D0A
9112 09:28:35.794607 CH1_RK1: MR19=0x303, MR18=0xD0A, DQSOSC=403, MR23=63, INC=22, DEC=15
9113 09:28:35.795120 [RxdqsGatingPostProcess] freq 1600
9114 09:28:35.801046 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9115 09:28:35.804247 best DQS0 dly(2T, 0.5T) = (1, 1)
9116 09:28:35.807570 best DQS1 dly(2T, 0.5T) = (1, 1)
9117 09:28:35.810803 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9118 09:28:35.814339 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9119 09:28:35.817462 best DQS0 dly(2T, 0.5T) = (1, 1)
9120 09:28:35.821016 best DQS1 dly(2T, 0.5T) = (1, 1)
9121 09:28:35.824162 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9122 09:28:35.827342 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9123 09:28:35.827758 Pre-setting of DQS Precalculation
9124 09:28:35.833699 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9125 09:28:35.840437 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9126 09:28:35.847181 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9127 09:28:35.847736
9128 09:28:35.848219
9129 09:28:35.850922 [Calibration Summary] 3200 Mbps
9130 09:28:35.853953 CH 0, Rank 0
9131 09:28:35.854487 SW Impedance : PASS
9132 09:28:35.857476 DUTY Scan : NO K
9133 09:28:35.860173 ZQ Calibration : PASS
9134 09:28:35.860590 Jitter Meter : NO K
9135 09:28:35.863680 CBT Training : PASS
9136 09:28:35.867140 Write leveling : PASS
9137 09:28:35.867555 RX DQS gating : PASS
9138 09:28:35.870210 RX DQ/DQS(RDDQC) : PASS
9139 09:28:35.873415 TX DQ/DQS : PASS
9140 09:28:35.873832 RX DATLAT : PASS
9141 09:28:35.876783 RX DQ/DQS(Engine): PASS
9142 09:28:35.880386 TX OE : PASS
9143 09:28:35.880849 All Pass.
9144 09:28:35.881176
9145 09:28:35.881480 CH 0, Rank 1
9146 09:28:35.883882 SW Impedance : PASS
9147 09:28:35.886716 DUTY Scan : NO K
9148 09:28:35.887127 ZQ Calibration : PASS
9149 09:28:35.889788 Jitter Meter : NO K
9150 09:28:35.893587 CBT Training : PASS
9151 09:28:35.894001 Write leveling : PASS
9152 09:28:35.896551 RX DQS gating : PASS
9153 09:28:35.899790 RX DQ/DQS(RDDQC) : PASS
9154 09:28:35.900350 TX DQ/DQS : PASS
9155 09:28:35.903503 RX DATLAT : PASS
9156 09:28:35.904005 RX DQ/DQS(Engine): PASS
9157 09:28:35.906475 TX OE : PASS
9158 09:28:35.906891 All Pass.
9159 09:28:35.907217
9160 09:28:35.909504 CH 1, Rank 0
9161 09:28:35.909918 SW Impedance : PASS
9162 09:28:35.913129 DUTY Scan : NO K
9163 09:28:35.916216 ZQ Calibration : PASS
9164 09:28:35.916631 Jitter Meter : NO K
9165 09:28:35.919436 CBT Training : PASS
9166 09:28:35.922837 Write leveling : PASS
9167 09:28:35.923270 RX DQS gating : PASS
9168 09:28:35.926562 RX DQ/DQS(RDDQC) : PASS
9169 09:28:35.929241 TX DQ/DQS : PASS
9170 09:28:35.929695 RX DATLAT : PASS
9171 09:28:35.932817 RX DQ/DQS(Engine): PASS
9172 09:28:35.936747 TX OE : PASS
9173 09:28:35.937281 All Pass.
9174 09:28:35.937606
9175 09:28:35.937944 CH 1, Rank 1
9176 09:28:35.939365 SW Impedance : PASS
9177 09:28:35.942786 DUTY Scan : NO K
9178 09:28:35.943201 ZQ Calibration : PASS
9179 09:28:35.945717 Jitter Meter : NO K
9180 09:28:35.949542 CBT Training : PASS
9181 09:28:35.949952 Write leveling : PASS
9182 09:28:35.952572 RX DQS gating : PASS
9183 09:28:35.956292 RX DQ/DQS(RDDQC) : PASS
9184 09:28:35.956703 TX DQ/DQS : PASS
9185 09:28:35.959166 RX DATLAT : PASS
9186 09:28:35.962245 RX DQ/DQS(Engine): PASS
9187 09:28:35.962702 TX OE : PASS
9188 09:28:35.963067 All Pass.
9189 09:28:35.965872
9190 09:28:35.966342 DramC Write-DBI on
9191 09:28:35.969083 PER_BANK_REFRESH: Hybrid Mode
9192 09:28:35.969601 TX_TRACKING: ON
9193 09:28:35.978961 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9194 09:28:35.985478 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9195 09:28:35.995914 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9196 09:28:35.998621 [FAST_K] Save calibration result to emmc
9197 09:28:36.002266 sync common calibartion params.
9198 09:28:36.002702 sync cbt_mode0:1, 1:1
9199 09:28:36.005807 dram_init: ddr_geometry: 2
9200 09:28:36.008464 dram_init: ddr_geometry: 2
9201 09:28:36.008876 dram_init: ddr_geometry: 2
9202 09:28:36.012079 0:dram_rank_size:100000000
9203 09:28:36.015198 1:dram_rank_size:100000000
9204 09:28:36.022148 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9205 09:28:36.022709 DFS_SHUFFLE_HW_MODE: ON
9206 09:28:36.025184 dramc_set_vcore_voltage set vcore to 725000
9207 09:28:36.028652 Read voltage for 1600, 0
9208 09:28:36.029065 Vio18 = 0
9209 09:28:36.031758 Vcore = 725000
9210 09:28:36.032175 Vdram = 0
9211 09:28:36.032499 Vddq = 0
9212 09:28:36.034901 Vmddr = 0
9213 09:28:36.035444 switch to 3200 Mbps bootup
9214 09:28:36.038057 [DramcRunTimeConfig]
9215 09:28:36.038512 PHYPLL
9216 09:28:36.041383 DPM_CONTROL_AFTERK: ON
9217 09:28:36.041983 PER_BANK_REFRESH: ON
9218 09:28:36.045148 REFRESH_OVERHEAD_REDUCTION: ON
9219 09:28:36.048315 CMD_PICG_NEW_MODE: OFF
9220 09:28:36.048730 XRTWTW_NEW_MODE: ON
9221 09:28:36.051489 XRTRTR_NEW_MODE: ON
9222 09:28:36.051906 TX_TRACKING: ON
9223 09:28:36.054646 RDSEL_TRACKING: OFF
9224 09:28:36.058279 DQS Precalculation for DVFS: ON
9225 09:28:36.058698 RX_TRACKING: OFF
9226 09:28:36.061304 HW_GATING DBG: ON
9227 09:28:36.061716 ZQCS_ENABLE_LP4: ON
9228 09:28:36.064458 RX_PICG_NEW_MODE: ON
9229 09:28:36.064870 TX_PICG_NEW_MODE: ON
9230 09:28:36.068139 ENABLE_RX_DCM_DPHY: ON
9231 09:28:36.071163 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9232 09:28:36.074912 DUMMY_READ_FOR_TRACKING: OFF
9233 09:28:36.077889 !!! SPM_CONTROL_AFTERK: OFF
9234 09:28:36.078361 !!! SPM could not control APHY
9235 09:28:36.081299 IMPEDANCE_TRACKING: ON
9236 09:28:36.081710 TEMP_SENSOR: ON
9237 09:28:36.084514 HW_SAVE_FOR_SR: OFF
9238 09:28:36.087570 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9239 09:28:36.091034 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9240 09:28:36.094396 Read ODT Tracking: ON
9241 09:28:36.094915 Refresh Rate DeBounce: ON
9242 09:28:36.097733 DFS_NO_QUEUE_FLUSH: ON
9243 09:28:36.101074 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9244 09:28:36.104158 ENABLE_DFS_RUNTIME_MRW: OFF
9245 09:28:36.104573 DDR_RESERVE_NEW_MODE: ON
9246 09:28:36.107506 MR_CBT_SWITCH_FREQ: ON
9247 09:28:36.110888 =========================
9248 09:28:36.128963 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9249 09:28:36.131768 dram_init: ddr_geometry: 2
9250 09:28:36.149927 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9251 09:28:36.153230 dram_init: dram init end (result: 0)
9252 09:28:36.159866 DRAM-K: Full calibration passed in 24603 msecs
9253 09:28:36.163047 MRC: failed to locate region type 0.
9254 09:28:36.163580 DRAM rank0 size:0x100000000,
9255 09:28:36.166567 DRAM rank1 size=0x100000000
9256 09:28:36.176095 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9257 09:28:36.183107 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9258 09:28:36.192631 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9259 09:28:36.199608 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9260 09:28:36.200078 DRAM rank0 size:0x100000000,
9261 09:28:36.202710 DRAM rank1 size=0x100000000
9262 09:28:36.203123 CBMEM:
9263 09:28:36.206198 IMD: root @ 0xfffff000 254 entries.
9264 09:28:36.209087 IMD: root @ 0xffffec00 62 entries.
9265 09:28:36.212655 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9266 09:28:36.219149 WARNING: RO_VPD is uninitialized or empty.
9267 09:28:36.222278 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9268 09:28:36.230204 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9269 09:28:36.242793 read SPI 0x42894 0xe01e: 6223 us, 9219 KB/s, 73.752 Mbps
9270 09:28:36.254630 BS: romstage times (exec / console): total (unknown) / 24098 ms
9271 09:28:36.255050
9272 09:28:36.255374
9273 09:28:36.264182 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9274 09:28:36.268061 ARM64: Exception handlers installed.
9275 09:28:36.271020 ARM64: Testing exception
9276 09:28:36.274396 ARM64: Done test exception
9277 09:28:36.274834 Enumerating buses...
9278 09:28:36.277782 Show all devs... Before device enumeration.
9279 09:28:36.280776 Root Device: enabled 1
9280 09:28:36.284502 CPU_CLUSTER: 0: enabled 1
9281 09:28:36.285040 CPU: 00: enabled 1
9282 09:28:36.287629 Compare with tree...
9283 09:28:36.288152 Root Device: enabled 1
9284 09:28:36.291183 CPU_CLUSTER: 0: enabled 1
9285 09:28:36.294100 CPU: 00: enabled 1
9286 09:28:36.294549 Root Device scanning...
9287 09:28:36.297380 scan_static_bus for Root Device
9288 09:28:36.300861 CPU_CLUSTER: 0 enabled
9289 09:28:36.303576 scan_static_bus for Root Device done
9290 09:28:36.307775 scan_bus: bus Root Device finished in 8 msecs
9291 09:28:36.308356 done
9292 09:28:36.313964 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9293 09:28:36.317173 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9294 09:28:36.323796 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9295 09:28:36.326988 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9296 09:28:36.330013 Allocating resources...
9297 09:28:36.333796 Reading resources...
9298 09:28:36.336907 Root Device read_resources bus 0 link: 0
9299 09:28:36.340666 DRAM rank0 size:0x100000000,
9300 09:28:36.341201 DRAM rank1 size=0x100000000
9301 09:28:36.347049 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9302 09:28:36.347485 CPU: 00 missing read_resources
9303 09:28:36.353154 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9304 09:28:36.356831 Root Device read_resources bus 0 link: 0 done
9305 09:28:36.360016 Done reading resources.
9306 09:28:36.363040 Show resources in subtree (Root Device)...After reading.
9307 09:28:36.366852 Root Device child on link 0 CPU_CLUSTER: 0
9308 09:28:36.369974 CPU_CLUSTER: 0 child on link 0 CPU: 00
9309 09:28:36.379852 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9310 09:28:36.380379 CPU: 00
9311 09:28:36.386434 Root Device assign_resources, bus 0 link: 0
9312 09:28:36.386944 CPU_CLUSTER: 0 missing set_resources
9313 09:28:36.392906 Root Device assign_resources, bus 0 link: 0 done
9314 09:28:36.393448 Done setting resources.
9315 09:28:36.399306 Show resources in subtree (Root Device)...After assigning values.
9316 09:28:36.402890 Root Device child on link 0 CPU_CLUSTER: 0
9317 09:28:36.405920 CPU_CLUSTER: 0 child on link 0 CPU: 00
9318 09:28:36.415641 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9319 09:28:36.416061 CPU: 00
9320 09:28:36.419227 Done allocating resources.
9321 09:28:36.425946 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9322 09:28:36.426391 Enabling resources...
9323 09:28:36.428931 done.
9324 09:28:36.432687 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9325 09:28:36.435717 Initializing devices...
9326 09:28:36.436127 Root Device init
9327 09:28:36.439178 init hardware done!
9328 09:28:36.439586 0x00000018: ctrlr->caps
9329 09:28:36.442250 52.000 MHz: ctrlr->f_max
9330 09:28:36.445702 0.400 MHz: ctrlr->f_min
9331 09:28:36.446123 0x40ff8080: ctrlr->voltages
9332 09:28:36.449001 sclk: 390625
9333 09:28:36.449526 Bus Width = 1
9334 09:28:36.452454 sclk: 390625
9335 09:28:36.452902 Bus Width = 1
9336 09:28:36.456024 Early init status = 3
9337 09:28:36.459038 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9338 09:28:36.462608 in-header: 03 fc 00 00 01 00 00 00
9339 09:28:36.465760 in-data: 00
9340 09:28:36.469444 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9341 09:28:36.475142 in-header: 03 fd 00 00 00 00 00 00
9342 09:28:36.478225 in-data:
9343 09:28:36.481961 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9344 09:28:36.486241 in-header: 03 fc 00 00 01 00 00 00
9345 09:28:36.489124 in-data: 00
9346 09:28:36.492562 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9347 09:28:36.498548 in-header: 03 fd 00 00 00 00 00 00
9348 09:28:36.501329 in-data:
9349 09:28:36.504511 [SSUSB] Setting up USB HOST controller...
9350 09:28:36.508289 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9351 09:28:36.511305 [SSUSB] phy power-on done.
9352 09:28:36.514448 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9353 09:28:36.521385 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9354 09:28:36.524280 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9355 09:28:36.530684 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9356 09:28:36.537117 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9357 09:28:36.543561 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9358 09:28:36.550447 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9359 09:28:36.557257 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9360 09:28:36.560027 SPM: binary array size = 0x9dc
9361 09:28:36.566784 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9362 09:28:36.570029 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9363 09:28:36.579890 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9364 09:28:36.583808 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9365 09:28:36.586652 configure_display: Starting display init
9366 09:28:36.621729 anx7625_power_on_init: Init interface.
9367 09:28:36.624812 anx7625_disable_pd_protocol: Disabled PD feature.
9368 09:28:36.628349 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9369 09:28:36.655944 anx7625_start_dp_work: Secure OCM version=00
9370 09:28:36.658840 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9371 09:28:36.673984 sp_tx_get_edid_block: EDID Block = 1
9372 09:28:36.776222 Extracted contents:
9373 09:28:36.779300 header: 00 ff ff ff ff ff ff 00
9374 09:28:36.783185 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9375 09:28:36.786055 version: 01 04
9376 09:28:36.789539 basic params: 95 1f 11 78 0a
9377 09:28:36.792800 chroma info: 76 90 94 55 54 90 27 21 50 54
9378 09:28:36.796418 established: 00 00 00
9379 09:28:36.803113 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9380 09:28:36.806195 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9381 09:28:36.812587 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9382 09:28:36.819377 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9383 09:28:36.826090 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9384 09:28:36.829345 extensions: 00
9385 09:28:36.829727 checksum: fb
9386 09:28:36.830026
9387 09:28:36.836021 Manufacturer: IVO Model 57d Serial Number 0
9388 09:28:36.836524 Made week 0 of 2020
9389 09:28:36.839145 EDID version: 1.4
9390 09:28:36.839566 Digital display
9391 09:28:36.842150 6 bits per primary color channel
9392 09:28:36.842607 DisplayPort interface
9393 09:28:36.845722 Maximum image size: 31 cm x 17 cm
9394 09:28:36.848749 Gamma: 220%
9395 09:28:36.849175 Check DPMS levels
9396 09:28:36.855925 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9397 09:28:36.858610 First detailed timing is preferred timing
9398 09:28:36.859136 Established timings supported:
9399 09:28:36.862339 Standard timings supported:
9400 09:28:36.865619 Detailed timings
9401 09:28:36.868770 Hex of detail: 383680a07038204018303c0035ae10000019
9402 09:28:36.875404 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9403 09:28:36.878479 0780 0798 07c8 0820 hborder 0
9404 09:28:36.881826 0438 043b 0447 0458 vborder 0
9405 09:28:36.885791 -hsync -vsync
9406 09:28:36.886374 Did detailed timing
9407 09:28:36.892213 Hex of detail: 000000000000000000000000000000000000
9408 09:28:36.895237 Manufacturer-specified data, tag 0
9409 09:28:36.898682 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9410 09:28:36.901737 ASCII string: InfoVision
9411 09:28:36.905381 Hex of detail: 000000fe00523134304e574635205248200a
9412 09:28:36.908448 ASCII string: R140NWF5 RH
9413 09:28:36.908883 Checksum
9414 09:28:36.911531 Checksum: 0xfb (valid)
9415 09:28:36.915181 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9416 09:28:36.917953 DSI data_rate: 832800000 bps
9417 09:28:36.924663 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9418 09:28:36.927889 anx7625_parse_edid: pixelclock(138800).
9419 09:28:36.931648 hactive(1920), hsync(48), hfp(24), hbp(88)
9420 09:28:36.934581 vactive(1080), vsync(12), vfp(3), vbp(17)
9421 09:28:36.937662 anx7625_dsi_config: config dsi.
9422 09:28:36.944350 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9423 09:28:36.958253 anx7625_dsi_config: success to config DSI
9424 09:28:36.961455 anx7625_dp_start: MIPI phy setup OK.
9425 09:28:36.965280 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9426 09:28:36.968647 mtk_ddp_mode_set invalid vrefresh 60
9427 09:28:36.971734 main_disp_path_setup
9428 09:28:36.972172 ovl_layer_smi_id_en
9429 09:28:36.974642 ovl_layer_smi_id_en
9430 09:28:36.975091 ccorr_config
9431 09:28:36.975511 aal_config
9432 09:28:36.977991 gamma_config
9433 09:28:36.978620 postmask_config
9434 09:28:36.981274 dither_config
9435 09:28:36.984882 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9436 09:28:36.991181 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9437 09:28:36.994649 Root Device init finished in 555 msecs
9438 09:28:36.997812 CPU_CLUSTER: 0 init
9439 09:28:37.004156 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9440 09:28:37.011142 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9441 09:28:37.011701 APU_MBOX 0x190000b0 = 0x10001
9442 09:28:37.014339 APU_MBOX 0x190001b0 = 0x10001
9443 09:28:37.017992 APU_MBOX 0x190005b0 = 0x10001
9444 09:28:37.020901 APU_MBOX 0x190006b0 = 0x10001
9445 09:28:37.027491 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9446 09:28:37.036995 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9447 09:28:37.049979 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9448 09:28:37.056074 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9449 09:28:37.068155 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9450 09:28:37.077230 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9451 09:28:37.081024 CPU_CLUSTER: 0 init finished in 81 msecs
9452 09:28:37.084027 Devices initialized
9453 09:28:37.087075 Show all devs... After init.
9454 09:28:37.087487 Root Device: enabled 1
9455 09:28:37.090608 CPU_CLUSTER: 0: enabled 1
9456 09:28:37.093505 CPU: 00: enabled 1
9457 09:28:37.096658 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9458 09:28:37.100213 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9459 09:28:37.103398 ELOG: NV offset 0x57f000 size 0x1000
9460 09:28:37.110378 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9461 09:28:37.116589 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9462 09:28:37.119773 ELOG: Event(17) added with size 13 at 2024-06-18 09:28:36 UTC
9463 09:28:37.126725 out: cmd=0x121: 03 db 21 01 00 00 00 00
9464 09:28:37.129514 in-header: 03 4c 00 00 2c 00 00 00
9465 09:28:37.143194 in-data: f1 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9466 09:28:37.146130 ELOG: Event(A1) added with size 10 at 2024-06-18 09:28:36 UTC
9467 09:28:37.156484 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9468 09:28:37.159543 ELOG: Event(A0) added with size 9 at 2024-06-18 09:28:36 UTC
9469 09:28:37.162736 elog_add_boot_reason: Logged dev mode boot
9470 09:28:37.169170 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9471 09:28:37.172580 Finalize devices...
9472 09:28:37.173150 Devices finalized
9473 09:28:37.179434 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9474 09:28:37.182528 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9475 09:28:37.186266 in-header: 03 07 00 00 08 00 00 00
9476 09:28:37.189241 in-data: aa e4 47 04 13 02 00 00
9477 09:28:37.189786 Chrome EC: UHEPI supported
9478 09:28:37.195448 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9479 09:28:37.199005 in-header: 03 a9 00 00 08 00 00 00
9480 09:28:37.202459 in-data: 84 60 60 08 00 00 00 00
9481 09:28:37.209198 ELOG: Event(91) added with size 10 at 2024-06-18 09:28:36 UTC
9482 09:28:37.212304 Chrome EC: clear events_b mask to 0x0000000020004000
9483 09:28:37.218903 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9484 09:28:37.223065 in-header: 03 fd 00 00 00 00 00 00
9485 09:28:37.225956 in-data:
9486 09:28:37.229658 BS: BS_WRITE_TABLES entry times (exec / console): 2 / 46 ms
9487 09:28:37.232733 Writing coreboot table at 0xffe64000
9488 09:28:37.239221 0. 000000000010a000-0000000000113fff: RAMSTAGE
9489 09:28:37.243069 1. 0000000040000000-00000000400fffff: RAM
9490 09:28:37.246047 2. 0000000040100000-000000004032afff: RAMSTAGE
9491 09:28:37.249161 3. 000000004032b000-00000000545fffff: RAM
9492 09:28:37.252883 4. 0000000054600000-000000005465ffff: BL31
9493 09:28:37.259097 5. 0000000054660000-00000000ffe63fff: RAM
9494 09:28:37.262552 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9495 09:28:37.265739 7. 0000000100000000-000000023fffffff: RAM
9496 09:28:37.269553 Passing 5 GPIOs to payload:
9497 09:28:37.272588 NAME | PORT | POLARITY | VALUE
9498 09:28:37.278935 EC in RW | 0x000000aa | low | undefined
9499 09:28:37.282015 EC interrupt | 0x00000005 | low | undefined
9500 09:28:37.288930 TPM interrupt | 0x000000ab | high | undefined
9501 09:28:37.292598 SD card detect | 0x00000011 | high | undefined
9502 09:28:37.295592 speaker enable | 0x00000093 | high | undefined
9503 09:28:37.301807 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9504 09:28:37.305485 in-header: 03 f9 00 00 02 00 00 00
9505 09:28:37.306041 in-data: 02 00
9506 09:28:37.308684 ADC[4]: Raw value=904509 ID=7
9507 09:28:37.312021 ADC[3]: Raw value=212912 ID=1
9508 09:28:37.312578 RAM Code: 0x71
9509 09:28:37.315027 ADC[6]: Raw value=75036 ID=0
9510 09:28:37.318511 ADC[5]: Raw value=212912 ID=1
9511 09:28:37.319062 SKU Code: 0x1
9512 09:28:37.325174 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9899
9513 09:28:37.328154 coreboot table: 964 bytes.
9514 09:28:37.331833 IMD ROOT 0. 0xfffff000 0x00001000
9515 09:28:37.335137 IMD SMALL 1. 0xffffe000 0x00001000
9516 09:28:37.338379 RO MCACHE 2. 0xffffc000 0x00001104
9517 09:28:37.341580 CONSOLE 3. 0xfff7c000 0x00080000
9518 09:28:37.344749 FMAP 4. 0xfff7b000 0x00000452
9519 09:28:37.348071 TIME STAMP 5. 0xfff7a000 0x00000910
9520 09:28:37.351720 VBOOT WORK 6. 0xfff66000 0x00014000
9521 09:28:37.354396 RAMOOPS 7. 0xffe66000 0x00100000
9522 09:28:37.357791 COREBOOT 8. 0xffe64000 0x00002000
9523 09:28:37.358264 IMD small region:
9524 09:28:37.360840 IMD ROOT 0. 0xffffec00 0x00000400
9525 09:28:37.364452 VPD 1. 0xffffeb80 0x0000006c
9526 09:28:37.367527 MMC STATUS 2. 0xffffeb60 0x00000004
9527 09:28:37.374103 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9528 09:28:37.380679 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9529 09:28:37.421175 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9530 09:28:37.423917 Checking segment from ROM address 0x40100000
9531 09:28:37.427505 Checking segment from ROM address 0x4010001c
9532 09:28:37.434120 Loading segment from ROM address 0x40100000
9533 09:28:37.434592 code (compression=0)
9534 09:28:37.444230 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9535 09:28:37.450973 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9536 09:28:37.451407 it's not compressed!
9537 09:28:37.457423 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9538 09:28:37.464237 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9539 09:28:37.481844 Loading segment from ROM address 0x4010001c
9540 09:28:37.482423 Entry Point 0x80000000
9541 09:28:37.484737 Loaded segments
9542 09:28:37.488067 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9543 09:28:37.495072 Jumping to boot code at 0x80000000(0xffe64000)
9544 09:28:37.501078 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9545 09:28:37.507961 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9546 09:28:37.515886 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9547 09:28:37.519377 Checking segment from ROM address 0x40100000
9548 09:28:37.522432 Checking segment from ROM address 0x4010001c
9549 09:28:37.528968 Loading segment from ROM address 0x40100000
9550 09:28:37.529426 code (compression=1)
9551 09:28:37.535531 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9552 09:28:37.545303 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9553 09:28:37.545754 using LZMA
9554 09:28:37.553952 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9555 09:28:37.560505 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9556 09:28:37.564042 Loading segment from ROM address 0x4010001c
9557 09:28:37.567569 Entry Point 0x54601000
9558 09:28:37.568035 Loaded segments
9559 09:28:37.570231 NOTICE: MT8192 bl31_setup
9560 09:28:37.577664 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9561 09:28:37.581299 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9562 09:28:37.584266 WARNING: region 0:
9563 09:28:37.587907 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9564 09:28:37.588320 WARNING: region 1:
9565 09:28:37.594296 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9566 09:28:37.597567 WARNING: region 2:
9567 09:28:37.601130 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9568 09:28:37.603981 WARNING: region 3:
9569 09:28:37.607303 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9570 09:28:37.610904 WARNING: region 4:
9571 09:28:37.617540 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9572 09:28:37.618086 WARNING: region 5:
9573 09:28:37.620603 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9574 09:28:37.624164 WARNING: region 6:
9575 09:28:37.627797 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9576 09:28:37.630839 WARNING: region 7:
9577 09:28:37.633743 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9578 09:28:37.640671 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9579 09:28:37.644228 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9580 09:28:37.650461 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9581 09:28:37.654124 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9582 09:28:37.657045 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9583 09:28:37.663930 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9584 09:28:37.666896 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9585 09:28:37.670642 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9586 09:28:37.676935 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9587 09:28:37.680360 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9588 09:28:37.686760 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9589 09:28:37.690343 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9590 09:28:37.693303 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9591 09:28:37.699711 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9592 09:28:37.703515 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9593 09:28:37.706542 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9594 09:28:37.712904 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9595 09:28:37.716152 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9596 09:28:37.722851 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9597 09:28:37.726155 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9598 09:28:37.729852 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9599 09:28:37.736007 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9600 09:28:37.739508 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9601 09:28:37.745867 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9602 09:28:37.749670 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9603 09:28:37.752671 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9604 09:28:37.759399 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9605 09:28:37.762478 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9606 09:28:37.769386 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9607 09:28:37.772470 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9608 09:28:37.779329 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9609 09:28:37.782662 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9610 09:28:37.786054 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9611 09:28:37.789001 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9612 09:28:37.795405 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9613 09:28:37.799039 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9614 09:28:37.802446 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9615 09:28:37.805527 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9616 09:28:37.812066 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9617 09:28:37.815215 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9618 09:28:37.818548 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9619 09:28:37.822057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9620 09:28:37.828783 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9621 09:28:37.832104 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9622 09:28:37.835042 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9623 09:28:37.841646 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9624 09:28:37.845358 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9625 09:28:37.848675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9626 09:28:37.855163 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9627 09:28:37.858155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9628 09:28:37.861337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9629 09:28:37.868492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9630 09:28:37.871629 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9631 09:28:37.877734 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9632 09:28:37.881544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9633 09:28:37.888139 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9634 09:28:37.891301 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9635 09:28:37.894964 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9636 09:28:37.901204 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9637 09:28:37.904538 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9638 09:28:37.910978 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9639 09:28:37.914654 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9640 09:28:37.921264 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9641 09:28:37.924811 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9642 09:28:37.930809 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9643 09:28:37.934424 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9644 09:28:37.940660 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9645 09:28:37.944072 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9646 09:28:37.947788 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9647 09:28:37.953821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9648 09:28:37.957166 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9649 09:28:37.963884 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9650 09:28:37.967505 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9651 09:28:37.973715 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9652 09:28:37.977258 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9653 09:28:37.980481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9654 09:28:37.987108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9655 09:28:37.990744 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9656 09:28:37.997634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9657 09:28:38.000372 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9658 09:28:38.006958 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9659 09:28:38.009920 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9660 09:28:38.017282 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9661 09:28:38.020165 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9662 09:28:38.023671 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9663 09:28:38.030745 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9664 09:28:38.033233 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9665 09:28:38.040452 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9666 09:28:38.043207 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9667 09:28:38.049509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9668 09:28:38.053326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9669 09:28:38.059805 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9670 09:28:38.063220 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9671 09:28:38.069637 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9672 09:28:38.073302 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9673 09:28:38.076544 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9674 09:28:38.082952 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9675 09:28:38.086474 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9676 09:28:38.089687 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9677 09:28:38.092869 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9678 09:28:38.099452 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9679 09:28:38.103319 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9680 09:28:38.109594 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9681 09:28:38.112750 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9682 09:28:38.115819 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9683 09:28:38.122815 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9684 09:28:38.125954 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9685 09:28:38.132560 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9686 09:28:38.135851 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9687 09:28:38.138889 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9688 09:28:38.146003 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9689 09:28:38.148906 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9690 09:28:38.156014 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9691 09:28:38.158832 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9692 09:28:38.165571 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9693 09:28:38.168739 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9694 09:28:38.172649 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9695 09:28:38.175344 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9696 09:28:38.182239 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9697 09:28:38.185971 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9698 09:28:38.189178 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9699 09:28:38.192537 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9700 09:28:38.198615 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9701 09:28:38.201694 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9702 09:28:38.205553 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9703 09:28:38.211556 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9704 09:28:38.215349 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9705 09:28:38.221997 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9706 09:28:38.224918 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9707 09:28:38.228455 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9708 09:28:38.234865 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9709 09:28:38.238220 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9710 09:28:38.244821 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9711 09:28:38.248514 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9712 09:28:38.251970 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9713 09:28:38.258296 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9714 09:28:38.261739 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9715 09:28:38.268202 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9716 09:28:38.271240 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9717 09:28:38.274358 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9718 09:28:38.281437 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9719 09:28:38.284888 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9720 09:28:38.291274 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9721 09:28:38.294694 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9722 09:28:38.297748 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9723 09:28:38.303952 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9724 09:28:38.307335 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9725 09:28:38.314417 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9726 09:28:38.317676 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9727 09:28:38.320695 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9728 09:28:38.327243 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9729 09:28:38.330579 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9730 09:28:38.337162 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9731 09:28:38.340570 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9732 09:28:38.344024 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9733 09:28:38.350611 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9734 09:28:38.353586 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9735 09:28:38.360274 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9736 09:28:38.363479 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9737 09:28:38.366693 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9738 09:28:38.374058 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9739 09:28:38.377067 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9740 09:28:38.383700 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9741 09:28:38.386748 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9742 09:28:38.389831 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9743 09:28:38.396849 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9744 09:28:38.399854 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9745 09:28:38.406311 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9746 09:28:38.410001 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9747 09:28:38.412916 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9748 09:28:38.419684 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9749 09:28:38.423436 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9750 09:28:38.429374 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9751 09:28:38.433049 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9752 09:28:38.436437 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9753 09:28:38.443401 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9754 09:28:38.446349 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9755 09:28:38.452983 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9756 09:28:38.456171 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9757 09:28:38.459677 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9758 09:28:38.466277 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9759 09:28:38.469627 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9760 09:28:38.475928 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9761 09:28:38.479411 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9762 09:28:38.482387 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9763 09:28:38.489505 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9764 09:28:38.492476 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9765 09:28:38.499137 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9766 09:28:38.502022 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9767 09:28:38.505681 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9768 09:28:38.512274 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9769 09:28:38.515236 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9770 09:28:38.522022 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9771 09:28:38.525421 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9772 09:28:38.531701 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9773 09:28:38.535582 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9774 09:28:38.538369 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9775 09:28:38.544963 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9776 09:28:38.548547 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9777 09:28:38.554814 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9778 09:28:38.558384 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9779 09:28:38.562129 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9780 09:28:38.568272 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9781 09:28:38.571839 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9782 09:28:38.578346 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9783 09:28:38.581719 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9784 09:28:38.588300 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9785 09:28:38.591982 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9786 09:28:38.594989 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9787 09:28:38.601869 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9788 09:28:38.604728 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9789 09:28:38.611870 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9790 09:28:38.614716 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9791 09:28:38.621460 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9792 09:28:38.624736 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9793 09:28:38.627738 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9794 09:28:38.634653 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9795 09:28:38.637664 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9796 09:28:38.644632 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9797 09:28:38.647391 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9798 09:28:38.654357 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9799 09:28:38.657237 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9800 09:28:38.660458 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9801 09:28:38.667542 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9802 09:28:38.670540 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9803 09:28:38.677345 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9804 09:28:38.680553 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9805 09:28:38.686938 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9806 09:28:38.690431 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9807 09:28:38.693692 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9808 09:28:38.697226 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9809 09:28:38.703582 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9810 09:28:38.707084 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9811 09:28:38.710612 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9812 09:28:38.713632 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9813 09:28:38.720456 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9814 09:28:38.723367 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9815 09:28:38.730460 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9816 09:28:38.733661 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9817 09:28:38.736941 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9818 09:28:38.743468 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9819 09:28:38.747111 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9820 09:28:38.750225 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9821 09:28:38.757094 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9822 09:28:38.760055 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9823 09:28:38.766673 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9824 09:28:38.769642 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9825 09:28:38.773415 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9826 09:28:38.780058 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9827 09:28:38.783044 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9828 09:28:38.786774 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9829 09:28:38.793271 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9830 09:28:38.796696 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9831 09:28:38.799676 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9832 09:28:38.806428 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9833 09:28:38.809635 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9834 09:28:38.816370 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9835 09:28:38.819398 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9836 09:28:38.822680 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9837 09:28:38.829372 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9838 09:28:38.832476 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9839 09:28:38.839246 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9840 09:28:38.842706 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9841 09:28:38.846225 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9842 09:28:38.852848 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9843 09:28:38.855729 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9844 09:28:38.859428 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9845 09:28:38.866083 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9846 09:28:38.869225 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9847 09:28:38.872251 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9848 09:28:38.875852 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9849 09:28:38.882080 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9850 09:28:38.885565 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9851 09:28:38.888707 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9852 09:28:38.892285 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9853 09:28:38.898612 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9854 09:28:38.902096 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9855 09:28:38.905479 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9856 09:28:38.911580 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9857 09:28:38.915274 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9858 09:28:38.918417 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9859 09:28:38.921705 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9860 09:28:38.928501 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9861 09:28:38.931603 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9862 09:28:38.938123 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9863 09:28:38.941549 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9864 09:28:38.948692 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9865 09:28:38.951230 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9866 09:28:38.954755 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9867 09:28:38.960949 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9868 09:28:38.964645 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9869 09:28:38.970817 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9870 09:28:38.974648 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9871 09:28:38.981296 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9872 09:28:38.984510 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9873 09:28:38.988257 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9874 09:28:38.994618 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9875 09:28:38.997545 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9876 09:28:39.004039 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9877 09:28:39.007726 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9878 09:28:39.010440 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9879 09:28:39.017744 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9880 09:28:39.020567 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9881 09:28:39.027120 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9882 09:28:39.030796 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9883 09:28:39.033965 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9884 09:28:39.040229 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9885 09:28:39.043485 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9886 09:28:39.050243 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9887 09:28:39.053659 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9888 09:28:39.059900 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9889 09:28:39.063129 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9890 09:28:39.070039 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9891 09:28:39.073598 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9892 09:28:39.076345 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9893 09:28:39.083417 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9894 09:28:39.086359 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9895 09:28:39.092931 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9896 09:28:39.096082 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9897 09:28:39.099669 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9898 09:28:39.105824 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9899 09:28:39.109418 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9900 09:28:39.115486 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9901 09:28:39.118623 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9902 09:28:39.122368 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9903 09:28:39.129063 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9904 09:28:39.132210 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9905 09:28:39.139006 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9906 09:28:39.142064 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9907 09:28:39.145634 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9908 09:28:39.151658 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9909 09:28:39.155331 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9910 09:28:39.161830 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9911 09:28:39.164907 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9912 09:28:39.172000 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9913 09:28:39.175309 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9914 09:28:39.181754 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9915 09:28:39.185255 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9916 09:28:39.188448 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9917 09:28:39.195031 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9918 09:28:39.198157 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9919 09:28:39.204793 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9920 09:28:39.208891 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9921 09:28:39.211642 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9922 09:28:39.217781 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9923 09:28:39.221581 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9924 09:28:39.227810 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9925 09:28:39.231431 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9926 09:28:39.234864 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9927 09:28:39.241394 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9928 09:28:39.244370 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9929 09:28:39.250970 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9930 09:28:39.254565 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9931 09:28:39.257584 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9932 09:28:39.264353 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9933 09:28:39.267449 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9934 09:28:39.274758 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9935 09:28:39.277536 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9936 09:28:39.284584 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9937 09:28:39.287695 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9938 09:28:39.294126 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9939 09:28:39.297401 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9940 09:28:39.301045 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9941 09:28:39.307592 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9942 09:28:39.310554 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9943 09:28:39.317381 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9944 09:28:39.320839 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9945 09:28:39.327060 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9946 09:28:39.330654 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9947 09:28:39.336749 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9948 09:28:39.340512 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9949 09:28:39.344163 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9950 09:28:39.350606 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9951 09:28:39.353792 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9952 09:28:39.360646 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9953 09:28:39.363575 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9954 09:28:39.370021 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9955 09:28:39.373937 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9956 09:28:39.376961 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9957 09:28:39.383817 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9958 09:28:39.387073 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9959 09:28:39.393549 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9960 09:28:39.397288 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9961 09:28:39.403971 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9962 09:28:39.406578 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9963 09:28:39.413493 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9964 09:28:39.416530 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9965 09:28:39.419829 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9966 09:28:39.426505 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9967 09:28:39.430049 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9968 09:28:39.436319 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9969 09:28:39.439497 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9970 09:28:39.446280 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9971 09:28:39.449302 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9972 09:28:39.456046 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9973 09:28:39.459578 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9974 09:28:39.465784 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9975 09:28:39.468772 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9976 09:28:39.472533 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9977 09:28:39.479327 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9978 09:28:39.482243 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9979 09:28:39.489027 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9980 09:28:39.492224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9981 09:28:39.496035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9982 09:28:39.502696 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9983 09:28:39.505433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9984 09:28:39.512133 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9985 09:28:39.515843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9986 09:28:39.522143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9987 09:28:39.525944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9988 09:28:39.531827 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9989 09:28:39.535148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9990 09:28:39.541775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9991 09:28:39.544953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9992 09:28:39.551592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9993 09:28:39.554889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9994 09:28:39.561624 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9995 09:28:39.565153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9996 09:28:39.571387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9997 09:28:39.575006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9998 09:28:39.581989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9999 09:28:39.584736 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10000 09:28:39.591543 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10001 09:28:39.594653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10002 09:28:39.601184 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10003 09:28:39.604404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10004 09:28:39.611447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10005 09:28:39.614551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10006 09:28:39.620991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10007 09:28:39.623995 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10008 09:28:39.631158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10009 09:28:39.634505 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10010 09:28:39.641195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10011 09:28:39.644066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10012 09:28:39.651155 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10013 09:28:39.651668 INFO: [APUAPC] vio 0
10014 09:28:39.657959 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10015 09:28:39.660894 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10016 09:28:39.664366 INFO: [APUAPC] D0_APC_0: 0x400510
10017 09:28:39.667551 INFO: [APUAPC] D0_APC_1: 0x0
10018 09:28:39.671013 INFO: [APUAPC] D0_APC_2: 0x1540
10019 09:28:39.674041 INFO: [APUAPC] D0_APC_3: 0x0
10020 09:28:39.677686 INFO: [APUAPC] D1_APC_0: 0xffffffff
10021 09:28:39.680946 INFO: [APUAPC] D1_APC_1: 0xffffffff
10022 09:28:39.684316 INFO: [APUAPC] D1_APC_2: 0x3fffff
10023 09:28:39.687711 INFO: [APUAPC] D1_APC_3: 0x0
10024 09:28:39.690710 INFO: [APUAPC] D2_APC_0: 0xffffffff
10025 09:28:39.694091 INFO: [APUAPC] D2_APC_1: 0xffffffff
10026 09:28:39.697257 INFO: [APUAPC] D2_APC_2: 0x3fffff
10027 09:28:39.700678 INFO: [APUAPC] D2_APC_3: 0x0
10028 09:28:39.703588 INFO: [APUAPC] D3_APC_0: 0xffffffff
10029 09:28:39.707455 INFO: [APUAPC] D3_APC_1: 0xffffffff
10030 09:28:39.710441 INFO: [APUAPC] D3_APC_2: 0x3fffff
10031 09:28:39.713576 INFO: [APUAPC] D3_APC_3: 0x0
10032 09:28:39.716839 INFO: [APUAPC] D4_APC_0: 0xffffffff
10033 09:28:39.720129 INFO: [APUAPC] D4_APC_1: 0xffffffff
10034 09:28:39.723650 INFO: [APUAPC] D4_APC_2: 0x3fffff
10035 09:28:39.727031 INFO: [APUAPC] D4_APC_3: 0x0
10036 09:28:39.730403 INFO: [APUAPC] D5_APC_0: 0xffffffff
10037 09:28:39.733770 INFO: [APUAPC] D5_APC_1: 0xffffffff
10038 09:28:39.737058 INFO: [APUAPC] D5_APC_2: 0x3fffff
10039 09:28:39.737620 INFO: [APUAPC] D5_APC_3: 0x0
10040 09:28:39.743560 INFO: [APUAPC] D6_APC_0: 0xffffffff
10041 09:28:39.746566 INFO: [APUAPC] D6_APC_1: 0xffffffff
10042 09:28:39.750033 INFO: [APUAPC] D6_APC_2: 0x3fffff
10043 09:28:39.750611 INFO: [APUAPC] D6_APC_3: 0x0
10044 09:28:39.753237 INFO: [APUAPC] D7_APC_0: 0xffffffff
10045 09:28:39.756964 INFO: [APUAPC] D7_APC_1: 0xffffffff
10046 09:28:39.759809 INFO: [APUAPC] D7_APC_2: 0x3fffff
10047 09:28:39.763040 INFO: [APUAPC] D7_APC_3: 0x0
10048 09:28:39.766545 INFO: [APUAPC] D8_APC_0: 0xffffffff
10049 09:28:39.769734 INFO: [APUAPC] D8_APC_1: 0xffffffff
10050 09:28:39.773311 INFO: [APUAPC] D8_APC_2: 0x3fffff
10051 09:28:39.776385 INFO: [APUAPC] D8_APC_3: 0x0
10052 09:28:39.779534 INFO: [APUAPC] D9_APC_0: 0xffffffff
10053 09:28:39.782882 INFO: [APUAPC] D9_APC_1: 0xffffffff
10054 09:28:39.786297 INFO: [APUAPC] D9_APC_2: 0x3fffff
10055 09:28:39.789473 INFO: [APUAPC] D9_APC_3: 0x0
10056 09:28:39.793211 INFO: [APUAPC] D10_APC_0: 0xffffffff
10057 09:28:39.796265 INFO: [APUAPC] D10_APC_1: 0xffffffff
10058 09:28:39.799374 INFO: [APUAPC] D10_APC_2: 0x3fffff
10059 09:28:39.803066 INFO: [APUAPC] D10_APC_3: 0x0
10060 09:28:39.806135 INFO: [APUAPC] D11_APC_0: 0xffffffff
10061 09:28:39.809299 INFO: [APUAPC] D11_APC_1: 0xffffffff
10062 09:28:39.813028 INFO: [APUAPC] D11_APC_2: 0x3fffff
10063 09:28:39.816050 INFO: [APUAPC] D11_APC_3: 0x0
10064 09:28:39.819115 INFO: [APUAPC] D12_APC_0: 0xffffffff
10065 09:28:39.822706 INFO: [APUAPC] D12_APC_1: 0xffffffff
10066 09:28:39.825512 INFO: [APUAPC] D12_APC_2: 0x3fffff
10067 09:28:39.829353 INFO: [APUAPC] D12_APC_3: 0x0
10068 09:28:39.832369 INFO: [APUAPC] D13_APC_0: 0xffffffff
10069 09:28:39.839152 INFO: [APUAPC] D13_APC_1: 0xffffffff
10070 09:28:39.842071 INFO: [APUAPC] D13_APC_2: 0x3fffff
10071 09:28:39.842176 INFO: [APUAPC] D13_APC_3: 0x0
10072 09:28:39.845192 INFO: [APUAPC] D14_APC_0: 0xffffffff
10073 09:28:39.851995 INFO: [APUAPC] D14_APC_1: 0xffffffff
10074 09:28:39.855528 INFO: [APUAPC] D14_APC_2: 0x3fffff
10075 09:28:39.855610 INFO: [APUAPC] D14_APC_3: 0x0
10076 09:28:39.861772 INFO: [APUAPC] D15_APC_0: 0xffffffff
10077 09:28:39.865287 INFO: [APUAPC] D15_APC_1: 0xffffffff
10078 09:28:39.868814 INFO: [APUAPC] D15_APC_2: 0x3fffff
10079 09:28:39.868925 INFO: [APUAPC] D15_APC_3: 0x0
10080 09:28:39.871895 INFO: [APUAPC] APC_CON: 0x4
10081 09:28:39.874974 INFO: [NOCDAPC] D0_APC_0: 0x0
10082 09:28:39.878351 INFO: [NOCDAPC] D0_APC_1: 0x0
10083 09:28:39.881883 INFO: [NOCDAPC] D1_APC_0: 0x0
10084 09:28:39.884851 INFO: [NOCDAPC] D1_APC_1: 0xfff
10085 09:28:39.888263 INFO: [NOCDAPC] D2_APC_0: 0x0
10086 09:28:39.891658 INFO: [NOCDAPC] D2_APC_1: 0xfff
10087 09:28:39.895008 INFO: [NOCDAPC] D3_APC_0: 0x0
10088 09:28:39.898133 INFO: [NOCDAPC] D3_APC_1: 0xfff
10089 09:28:39.898252 INFO: [NOCDAPC] D4_APC_0: 0x0
10090 09:28:39.901757 INFO: [NOCDAPC] D4_APC_1: 0xfff
10091 09:28:39.904790 INFO: [NOCDAPC] D5_APC_0: 0x0
10092 09:28:39.908513 INFO: [NOCDAPC] D5_APC_1: 0xfff
10093 09:28:39.911443 INFO: [NOCDAPC] D6_APC_0: 0x0
10094 09:28:39.915149 INFO: [NOCDAPC] D6_APC_1: 0xfff
10095 09:28:39.918332 INFO: [NOCDAPC] D7_APC_0: 0x0
10096 09:28:39.921382 INFO: [NOCDAPC] D7_APC_1: 0xfff
10097 09:28:39.925233 INFO: [NOCDAPC] D8_APC_0: 0x0
10098 09:28:39.928182 INFO: [NOCDAPC] D8_APC_1: 0xfff
10099 09:28:39.931297 INFO: [NOCDAPC] D9_APC_0: 0x0
10100 09:28:39.935384 INFO: [NOCDAPC] D9_APC_1: 0xfff
10101 09:28:39.935493 INFO: [NOCDAPC] D10_APC_0: 0x0
10102 09:28:39.938058 INFO: [NOCDAPC] D10_APC_1: 0xfff
10103 09:28:39.940940 INFO: [NOCDAPC] D11_APC_0: 0x0
10104 09:28:39.944732 INFO: [NOCDAPC] D11_APC_1: 0xfff
10105 09:28:39.947854 INFO: [NOCDAPC] D12_APC_0: 0x0
10106 09:28:39.951462 INFO: [NOCDAPC] D12_APC_1: 0xfff
10107 09:28:39.954661 INFO: [NOCDAPC] D13_APC_0: 0x0
10108 09:28:39.957784 INFO: [NOCDAPC] D13_APC_1: 0xfff
10109 09:28:39.960926 INFO: [NOCDAPC] D14_APC_0: 0x0
10110 09:28:39.964179 INFO: [NOCDAPC] D14_APC_1: 0xfff
10111 09:28:39.967730 INFO: [NOCDAPC] D15_APC_0: 0x0
10112 09:28:39.970684 INFO: [NOCDAPC] D15_APC_1: 0xfff
10113 09:28:39.974444 INFO: [NOCDAPC] APC_CON: 0x4
10114 09:28:39.977346 INFO: [APUAPC] set_apusys_apc done
10115 09:28:39.980890 INFO: [DEVAPC] devapc_init done
10116 09:28:39.984530 INFO: GICv3 without legacy support detected.
10117 09:28:39.987402 INFO: ARM GICv3 driver initialized in EL3
10118 09:28:39.991520 INFO: Maximum SPI INTID supported: 639
10119 09:28:39.994176 INFO: BL31: Initializing runtime services
10120 09:28:40.000929 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10121 09:28:40.004233 INFO: SPM: enable CPC mode
10122 09:28:40.010657 INFO: mcdi ready for mcusys-off-idle and system suspend
10123 09:28:40.014156 INFO: BL31: Preparing for EL3 exit to normal world
10124 09:28:40.017311 INFO: Entry point address = 0x80000000
10125 09:28:40.020396 INFO: SPSR = 0x8
10126 09:28:40.025276
10127 09:28:40.025448
10128 09:28:40.025583
10129 09:28:40.028935 Starting depthcharge on Spherion...
10130 09:28:40.029135
10131 09:28:40.029292 Wipe memory regions:
10132 09:28:40.029438
10133 09:28:40.030647 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10134 09:28:40.030884 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10135 09:28:40.031074 Setting prompt string to ['asurada:']
10136 09:28:40.031285 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10137 09:28:40.032055 [0x00000040000000, 0x00000054600000)
10138 09:28:40.154567
10139 09:28:40.155070 [0x00000054660000, 0x00000080000000)
10140 09:28:40.415242
10141 09:28:40.417974 [0x000000821a7280, 0x000000ffe64000)
10142 09:28:41.160355
10143 09:28:41.160863 [0x00000100000000, 0x00000240000000)
10144 09:28:43.050147
10145 09:28:43.053066 Initializing XHCI USB controller at 0x11200000.
10146 09:28:44.091805
10147 09:28:44.095492 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10148 09:28:44.095911
10149 09:28:44.096239
10150 09:28:44.097000 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10152 09:28:44.198219 asurada: tftpboot 192.168.201.1 14407642/tftp-deploy-loscb235/kernel/image.itb 14407642/tftp-deploy-loscb235/kernel/cmdline
10153 09:28:44.198862 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10154 09:28:44.199406 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10155 09:28:44.203651 tftpboot 192.168.201.1 14407642/tftp-deploy-loscb235/kernel/image.itp-deploy-loscb235/kernel/cmdline
10156 09:28:44.204116
10157 09:28:44.204474 Waiting for link
10158 09:28:44.361386
10159 09:28:44.362098 R8152: Initializing
10160 09:28:44.362731
10161 09:28:44.364756 Version 6 (ocp_data = 5c30)
10162 09:28:44.365331
10163 09:28:44.368093 R8152: Done initializing
10164 09:28:44.368676
10165 09:28:44.369213 Adding net device
10166 09:28:46.270923
10167 09:28:46.271464 done.
10168 09:28:46.271877
10169 09:28:46.272217 MAC: 00:e0:4c:68:02:81
10170 09:28:46.272542
10171 09:28:46.274097 Sending DHCP discover... done.
10172 09:28:46.274601
10173 09:28:49.972470 Waiting for reply... done.
10174 09:28:49.973132
10175 09:28:49.973502 Sending DHCP request... done.
10176 09:28:49.975357
10177 09:28:49.981928 Waiting for reply... done.
10178 09:28:49.982529
10179 09:28:49.982894 My ip is 192.168.201.14
10180 09:28:49.983227
10181 09:28:49.985291 The DHCP server ip is 192.168.201.1
10182 09:28:49.985747
10183 09:28:49.991359 TFTP server IP predefined by user: 192.168.201.1
10184 09:28:49.992067
10185 09:28:49.998261 Bootfile predefined by user: 14407642/tftp-deploy-loscb235/kernel/image.itb
10186 09:28:49.998718
10187 09:28:50.001498 Sending tftp read request... done.
10188 09:28:50.001947
10189 09:28:50.008331 Waiting for the transfer...
10190 09:28:50.008892
10191 09:28:50.706465 00000000 ################################################################
10192 09:28:50.707104
10193 09:28:51.389814 00080000 ################################################################
10194 09:28:51.390435
10195 09:28:52.082573 00100000 ################################################################
10196 09:28:52.083108
10197 09:28:52.761929 00180000 ################################################################
10198 09:28:52.762543
10199 09:28:53.447447 00200000 ################################################################
10200 09:28:53.447974
10201 09:28:54.136764 00280000 ################################################################
10202 09:28:54.137276
10203 09:28:54.821199 00300000 ################################################################
10204 09:28:54.821715
10205 09:28:55.480116 00380000 ################################################################
10206 09:28:55.480634
10207 09:28:56.168138 00400000 ################################################################
10208 09:28:56.168655
10209 09:28:56.791158 00480000 ################################################################
10210 09:28:56.791315
10211 09:28:57.436513 00500000 ################################################################
10212 09:28:57.437029
10213 09:28:58.128323 00580000 ################################################################
10214 09:28:58.128502
10215 09:28:58.781537 00600000 ################################################################
10216 09:28:58.782055
10217 09:28:59.491661 00680000 ################################################################
10218 09:28:59.492187
10219 09:29:00.210435 00700000 ################################################################
10220 09:29:00.210936
10221 09:29:00.899059 00780000 ################################################################
10222 09:29:00.899581
10223 09:29:01.544037 00800000 ################################################################
10224 09:29:01.544586
10225 09:29:02.244294 00880000 ################################################################
10226 09:29:02.244889
10227 09:29:02.947007 00900000 ################################################################
10228 09:29:02.947519
10229 09:29:03.650798 00980000 ################################################################
10230 09:29:03.651365
10231 09:29:04.335912 00a00000 ################################################################
10232 09:29:04.336446
10233 09:29:05.049460 00a80000 ################################################################
10234 09:29:05.050148
10235 09:29:05.699394 00b00000 ################################################################
10236 09:29:05.699903
10237 09:29:06.351496 00b80000 ################################################################
10238 09:29:06.351627
10239 09:29:07.030916 00c00000 ################################################################
10240 09:29:07.031308
10241 09:29:07.699964 00c80000 ################################################################
10242 09:29:07.700504
10243 09:29:08.340111 00d00000 ################################################################
10244 09:29:08.340773
10245 09:29:08.927054 00d80000 ################################################################
10246 09:29:08.927238
10247 09:29:09.588606 00e00000 ################################################################
10248 09:29:09.589174
10249 09:29:10.243682 00e80000 ################################################################
10250 09:29:10.244222
10251 09:29:10.868926 00f00000 ################################################################
10252 09:29:10.869443
10253 09:29:11.517352 00f80000 ################################################################
10254 09:29:11.517858
10255 09:29:12.214062 01000000 ################################################################
10256 09:29:12.214624
10257 09:29:12.911242 01080000 ################################################################
10258 09:29:12.911781
10259 09:29:13.621896 01100000 ################################################################
10260 09:29:13.622531
10261 09:29:14.317504 01180000 ################################################################
10262 09:29:14.318019
10263 09:29:15.002264 01200000 ################################################################
10264 09:29:15.002782
10265 09:29:15.697413 01280000 ################################################################
10266 09:29:15.697986
10267 09:29:16.411930 01300000 ################################################################
10268 09:29:16.412477
10269 09:29:17.080710 01380000 ################################################################
10270 09:29:17.081418
10271 09:29:17.679593 01400000 ################################################################
10272 09:29:17.679775
10273 09:29:18.254637 01480000 ################################################################
10274 09:29:18.255150
10275 09:29:18.915060 01500000 ################################################################
10276 09:29:18.915706
10277 09:29:19.573532 01580000 ################################################################
10278 09:29:19.574245
10279 09:29:20.270152 01600000 ################################################################
10280 09:29:20.270717
10281 09:29:20.944848 01680000 ################################################################
10282 09:29:20.945349
10283 09:29:21.640822 01700000 ################################################################
10284 09:29:21.641328
10285 09:29:22.322951 01780000 ################################################################
10286 09:29:22.323459
10287 09:29:23.019020 01800000 ################################################################
10288 09:29:23.019612
10289 09:29:23.706943 01880000 ################################################################
10290 09:29:23.707458
10291 09:29:24.416251 01900000 ################################################################
10292 09:29:24.416772
10293 09:29:25.109024 01980000 ################################################################
10294 09:29:25.109540
10295 09:29:25.772435 01a00000 ################################################################
10296 09:29:25.772604
10297 09:29:26.443883 01a80000 ################################################################
10298 09:29:26.444032
10299 09:29:27.089414 01b00000 ################################################################
10300 09:29:27.089913
10301 09:29:27.769621 01b80000 ################################################################
10302 09:29:27.770105
10303 09:29:28.348965 01c00000 ################################################################
10304 09:29:28.349096
10305 09:29:28.914525 01c80000 ################################################################
10306 09:29:28.914736
10307 09:29:29.484176 01d00000 ################################################################
10308 09:29:29.484327
10309 09:29:30.052935 01d80000 ################################################################
10310 09:29:30.053085
10311 09:29:30.549162 01e00000 ######################################################### done.
10312 09:29:30.549312
10313 09:29:30.552699 The bootfile was 31922618 bytes long.
10314 09:29:30.552790
10315 09:29:30.555639 Sending tftp read request... done.
10316 09:29:30.555723
10317 09:29:30.555789 Waiting for the transfer...
10318 09:29:30.555849
10319 09:29:30.559044 00000000 # done.
10320 09:29:30.559131
10321 09:29:30.565599 Command line loaded dynamically from TFTP file: 14407642/tftp-deploy-loscb235/kernel/cmdline
10322 09:29:30.565699
10323 09:29:30.588768 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407642/extract-nfsrootfs-ibllctfm,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10324 09:29:30.588945
10325 09:29:30.589046 Loading FIT.
10326 09:29:30.589134
10327 09:29:30.592094 Image ramdisk-1 has 18746599 bytes.
10328 09:29:30.592195
10329 09:29:30.595159 Image fdt-1 has 47258 bytes.
10330 09:29:30.595243
10331 09:29:30.599091 Image kernel-1 has 13126726 bytes.
10332 09:29:30.599173
10333 09:29:30.608435 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10334 09:29:30.608549
10335 09:29:30.625126 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10336 09:29:30.625272
10337 09:29:30.631735 Choosing best match conf-1 for compat google,spherion-rev2.
10338 09:29:30.634710
10339 09:29:30.638961 Connected to device vid:did:rid of 1ae0:0028:00
10340 09:29:30.646239
10341 09:29:30.649548 tpm_get_response: command 0x17b, return code 0x0
10342 09:29:30.649642
10343 09:29:30.656072 ec_init: CrosEC protocol v3 supported (256, 248)
10344 09:29:30.656172
10345 09:29:30.659406 tpm_cleanup: add release locality here.
10346 09:29:30.659492
10347 09:29:30.662660 Shutting down all USB controllers.
10348 09:29:30.662769
10349 09:29:30.665925 Removing current net device
10350 09:29:30.666008
10351 09:29:30.669470 Exiting depthcharge with code 4 at timestamp: 80068595
10352 09:29:30.669552
10353 09:29:30.676231 LZMA decompressing kernel-1 to 0x821a6718
10354 09:29:30.676320
10355 09:29:30.679365 LZMA decompressing kernel-1 to 0x40000000
10356 09:29:32.296239
10357 09:29:32.296409 jumping to kernel
10358 09:29:32.297253 end: 2.2.4 bootloader-commands (duration 00:00:52) [common]
10359 09:29:32.297381 start: 2.2.5 auto-login-action (timeout 00:03:34) [common]
10360 09:29:32.297485 Setting prompt string to ['Linux version [0-9]']
10361 09:29:32.297580 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10362 09:29:32.297674 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10363 09:29:32.377927
10364 09:29:32.381340 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10365 09:29:32.385133 start: 2.2.5.1 login-action (timeout 00:03:34) [common]
10366 09:29:32.385235 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10367 09:29:32.385305 Setting prompt string to []
10368 09:29:32.385380 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10369 09:29:32.385451 Using line separator: #'\n'#
10370 09:29:32.385509 No login prompt set.
10371 09:29:32.385570 Parsing kernel messages
10372 09:29:32.385623 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10373 09:29:32.385723 [login-action] Waiting for messages, (timeout 00:03:34)
10374 09:29:32.385788 Waiting using forced prompt support (timeout 00:01:47)
10375 09:29:32.404744 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
10376 09:29:32.407605 [ 0.000000] random: crng init done
10377 09:29:32.414585 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10378 09:29:32.417591 [ 0.000000] efi: UEFI not found.
10379 09:29:32.424217 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10380 09:29:32.430684 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10381 09:29:32.440925 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10382 09:29:32.450327 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10383 09:29:32.457326 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10384 09:29:32.463536 [ 0.000000] printk: bootconsole [mtk8250] enabled
10385 09:29:32.470670 [ 0.000000] NUMA: No NUMA configuration found
10386 09:29:32.477340 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10387 09:29:32.480181 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10388 09:29:32.484089 [ 0.000000] Zone ranges:
10389 09:29:32.490092 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10390 09:29:32.493386 [ 0.000000] DMA32 empty
10391 09:29:32.500084 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10392 09:29:32.503550 [ 0.000000] Movable zone start for each node
10393 09:29:32.506837 [ 0.000000] Early memory node ranges
10394 09:29:32.513341 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10395 09:29:32.519771 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10396 09:29:32.526573 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10397 09:29:32.533222 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10398 09:29:32.539326 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10399 09:29:32.546033 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10400 09:29:32.602460 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10401 09:29:32.609491 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10402 09:29:32.615864 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10403 09:29:32.619095 [ 0.000000] psci: probing for conduit method from DT.
10404 09:29:32.625491 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10405 09:29:32.628577 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10406 09:29:32.635378 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10407 09:29:32.638607 [ 0.000000] psci: SMC Calling Convention v1.2
10408 09:29:32.645199 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10409 09:29:32.648603 [ 0.000000] Detected VIPT I-cache on CPU0
10410 09:29:32.655075 [ 0.000000] CPU features: detected: GIC system register CPU interface
10411 09:29:32.661579 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10412 09:29:32.668404 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10413 09:29:32.674909 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10414 09:29:32.684651 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10415 09:29:32.691326 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10416 09:29:32.694876 [ 0.000000] alternatives: applying boot alternatives
10417 09:29:32.701373 [ 0.000000] Fallback order for Node 0: 0
10418 09:29:32.708659 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10419 09:29:32.711544 [ 0.000000] Policy zone: Normal
10420 09:29:32.734149 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407642/extract-nfsrootfs-ibllctfm,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10421 09:29:32.744124 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10422 09:29:32.755621 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10423 09:29:32.765436 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10424 09:29:32.772161 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10425 09:29:32.775560 <6>[ 0.000000] software IO TLB: area num 8.
10426 09:29:32.832095 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10427 09:29:32.982032 <6>[ 0.000000] Memory: 7945752K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 407016K reserved, 32768K cma-reserved)
10428 09:29:32.988733 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10429 09:29:32.995181 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10430 09:29:32.998410 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10431 09:29:33.005164 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10432 09:29:33.011891 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10433 09:29:33.014699 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10434 09:29:33.024571 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10435 09:29:33.031263 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10436 09:29:33.037697 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10437 09:29:33.044587 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10438 09:29:33.047735 <6>[ 0.000000] GICv3: 608 SPIs implemented
10439 09:29:33.050884 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10440 09:29:33.057535 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10441 09:29:33.060927 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10442 09:29:33.067487 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10443 09:29:33.080867 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10444 09:29:33.093875 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10445 09:29:33.100202 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10446 09:29:33.108978 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10447 09:29:33.122122 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10448 09:29:33.128509 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10449 09:29:33.134882 <6>[ 0.009180] Console: colour dummy device 80x25
10450 09:29:33.144729 <6>[ 0.013911] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10451 09:29:33.151664 <6>[ 0.024417] pid_max: default: 32768 minimum: 301
10452 09:29:33.154807 <6>[ 0.029289] LSM: Security Framework initializing
10453 09:29:33.161715 <6>[ 0.034228] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10454 09:29:33.171440 <6>[ 0.042043] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10455 09:29:33.181232 <6>[ 0.051346] cblist_init_generic: Setting adjustable number of callback queues.
10456 09:29:33.187710 <6>[ 0.058836] cblist_init_generic: Setting shift to 3 and lim to 1.
10457 09:29:33.194101 <6>[ 0.065175] cblist_init_generic: Setting adjustable number of callback queues.
10458 09:29:33.201005 <6>[ 0.072648] cblist_init_generic: Setting shift to 3 and lim to 1.
10459 09:29:33.204117 <6>[ 0.079049] rcu: Hierarchical SRCU implementation.
10460 09:29:33.210574 <6>[ 0.084094] rcu: Max phase no-delay instances is 1000.
10461 09:29:33.217496 <6>[ 0.091130] EFI services will not be available.
10462 09:29:33.220861 <6>[ 0.096116] smp: Bringing up secondary CPUs ...
10463 09:29:33.229359 <6>[ 0.101179] Detected VIPT I-cache on CPU1
10464 09:29:33.236084 <6>[ 0.101251] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10465 09:29:33.243000 <6>[ 0.101282] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10466 09:29:33.246031 <6>[ 0.101621] Detected VIPT I-cache on CPU2
10467 09:29:33.255619 <6>[ 0.101673] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10468 09:29:33.262515 <6>[ 0.101690] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10469 09:29:33.265820 <6>[ 0.101950] Detected VIPT I-cache on CPU3
10470 09:29:33.272475 <6>[ 0.101997] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10471 09:29:33.278908 <6>[ 0.102011] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10472 09:29:33.282559 <6>[ 0.102314] CPU features: detected: Spectre-v4
10473 09:29:33.289219 <6>[ 0.102320] CPU features: detected: Spectre-BHB
10474 09:29:33.292474 <6>[ 0.102325] Detected PIPT I-cache on CPU4
10475 09:29:33.298823 <6>[ 0.102383] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10476 09:29:33.305345 <6>[ 0.102400] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10477 09:29:33.312512 <6>[ 0.102693] Detected PIPT I-cache on CPU5
10478 09:29:33.318937 <6>[ 0.102755] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10479 09:29:33.325053 <6>[ 0.102771] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10480 09:29:33.328509 <6>[ 0.103053] Detected PIPT I-cache on CPU6
10481 09:29:33.335218 <6>[ 0.103116] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10482 09:29:33.341741 <6>[ 0.103132] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10483 09:29:33.348333 <6>[ 0.103433] Detected PIPT I-cache on CPU7
10484 09:29:33.354544 <6>[ 0.103498] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10485 09:29:33.361427 <6>[ 0.103513] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10486 09:29:33.364584 <6>[ 0.103560] smp: Brought up 1 node, 8 CPUs
10487 09:29:33.371109 <6>[ 0.244857] SMP: Total of 8 processors activated.
10488 09:29:33.374410 <6>[ 0.249809] CPU features: detected: 32-bit EL0 Support
10489 09:29:33.384730 <6>[ 0.255172] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10490 09:29:33.391074 <6>[ 0.264027] CPU features: detected: Common not Private translations
10491 09:29:33.397667 <6>[ 0.270503] CPU features: detected: CRC32 instructions
10492 09:29:33.404183 <6>[ 0.275887] CPU features: detected: RCpc load-acquire (LDAPR)
10493 09:29:33.407288 <6>[ 0.281847] CPU features: detected: LSE atomic instructions
10494 09:29:33.414470 <6>[ 0.287629] CPU features: detected: Privileged Access Never
10495 09:29:33.420609 <6>[ 0.293408] CPU features: detected: RAS Extension Support
10496 09:29:33.427333 <6>[ 0.299017] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10497 09:29:33.430802 <6>[ 0.306280] CPU: All CPU(s) started at EL2
10498 09:29:33.437181 <6>[ 0.310623] alternatives: applying system-wide alternatives
10499 09:29:33.447161 <6>[ 0.321397] devtmpfs: initialized
10500 09:29:33.459436 <6>[ 0.330339] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10501 09:29:33.469387 <6>[ 0.340299] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10502 09:29:33.476155 <6>[ 0.348328] pinctrl core: initialized pinctrl subsystem
10503 09:29:33.479495 <6>[ 0.355018] DMI not present or invalid.
10504 09:29:33.485867 <6>[ 0.359433] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10505 09:29:33.495842 <6>[ 0.366309] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10506 09:29:33.502445 <6>[ 0.373902] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10507 09:29:33.512409 <6>[ 0.382123] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10508 09:29:33.515480 <6>[ 0.390367] audit: initializing netlink subsys (disabled)
10509 09:29:33.525611 <5>[ 0.396061] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10510 09:29:33.532210 <6>[ 0.396776] thermal_sys: Registered thermal governor 'step_wise'
10511 09:29:33.538519 <6>[ 0.404028] thermal_sys: Registered thermal governor 'power_allocator'
10512 09:29:33.541615 <6>[ 0.410284] cpuidle: using governor menu
10513 09:29:33.548611 <6>[ 0.421248] NET: Registered PF_QIPCRTR protocol family
10514 09:29:33.554887 <6>[ 0.426736] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10515 09:29:33.561667 <6>[ 0.433838] ASID allocator initialised with 32768 entries
10516 09:29:33.564831 <6>[ 0.440424] Serial: AMBA PL011 UART driver
10517 09:29:33.575020 <4>[ 0.449249] Trying to register duplicate clock ID: 134
10518 09:29:33.633455 <6>[ 0.510895] KASLR enabled
10519 09:29:33.647717 <6>[ 0.518653] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10520 09:29:33.654390 <6>[ 0.525667] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10521 09:29:33.661388 <6>[ 0.532158] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10522 09:29:33.667523 <6>[ 0.539164] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10523 09:29:33.674449 <6>[ 0.545652] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10524 09:29:33.680865 <6>[ 0.552657] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10525 09:29:33.687488 <6>[ 0.559145] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10526 09:29:33.693854 <6>[ 0.566152] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10527 09:29:33.697552 <6>[ 0.573670] ACPI: Interpreter disabled.
10528 09:29:33.705872 <6>[ 0.580115] iommu: Default domain type: Translated
10529 09:29:33.712313 <6>[ 0.585226] iommu: DMA domain TLB invalidation policy: strict mode
10530 09:29:33.716086 <5>[ 0.591888] SCSI subsystem initialized
10531 09:29:33.722502 <6>[ 0.596055] usbcore: registered new interface driver usbfs
10532 09:29:33.728970 <6>[ 0.601787] usbcore: registered new interface driver hub
10533 09:29:33.732266 <6>[ 0.607340] usbcore: registered new device driver usb
10534 09:29:33.739364 <6>[ 0.613442] pps_core: LinuxPPS API ver. 1 registered
10535 09:29:33.748936 <6>[ 0.618634] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10536 09:29:33.752777 <6>[ 0.627982] PTP clock support registered
10537 09:29:33.756049 <6>[ 0.632228] EDAC MC: Ver: 3.0.0
10538 09:29:33.763370 <6>[ 0.637361] FPGA manager framework
10539 09:29:33.769658 <6>[ 0.641045] Advanced Linux Sound Architecture Driver Initialized.
10540 09:29:33.772994 <6>[ 0.647822] vgaarb: loaded
10541 09:29:33.779622 <6>[ 0.650980] clocksource: Switched to clocksource arch_sys_counter
10542 09:29:33.782615 <5>[ 0.657418] VFS: Disk quotas dquot_6.6.0
10543 09:29:33.789335 <6>[ 0.661606] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10544 09:29:33.792782 <6>[ 0.668800] pnp: PnP ACPI: disabled
10545 09:29:33.801469 <6>[ 0.675554] NET: Registered PF_INET protocol family
10546 09:29:33.811183 <6>[ 0.681147] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10547 09:29:33.822905 <6>[ 0.693484] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10548 09:29:33.832418 <6>[ 0.702296] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10549 09:29:33.839201 <6>[ 0.710268] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10550 09:29:33.849039 <6>[ 0.718976] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10551 09:29:33.855548 <6>[ 0.728732] TCP: Hash tables configured (established 65536 bind 65536)
10552 09:29:33.861987 <6>[ 0.735599] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10553 09:29:33.871822 <6>[ 0.742797] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10554 09:29:33.878739 <6>[ 0.750500] NET: Registered PF_UNIX/PF_LOCAL protocol family
10555 09:29:33.885250 <6>[ 0.756649] RPC: Registered named UNIX socket transport module.
10556 09:29:33.888588 <6>[ 0.762804] RPC: Registered udp transport module.
10557 09:29:33.894918 <6>[ 0.767737] RPC: Registered tcp transport module.
10558 09:29:33.901727 <6>[ 0.772669] RPC: Registered tcp NFSv4.1 backchannel transport module.
10559 09:29:33.904711 <6>[ 0.779334] PCI: CLS 0 bytes, default 64
10560 09:29:33.907929 <6>[ 0.783653] Unpacking initramfs...
10561 09:29:33.924676 <6>[ 0.795509] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10562 09:29:33.934415 <6>[ 0.804162] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10563 09:29:33.937672 <6>[ 0.812987] kvm [1]: IPA Size Limit: 40 bits
10564 09:29:33.944435 <6>[ 0.817517] kvm [1]: GICv3: no GICV resource entry
10565 09:29:33.947802 <6>[ 0.822540] kvm [1]: disabling GICv2 emulation
10566 09:29:33.954484 <6>[ 0.827228] kvm [1]: GIC system register CPU interface enabled
10567 09:29:33.958097 <6>[ 0.833388] kvm [1]: vgic interrupt IRQ18
10568 09:29:33.964630 <6>[ 0.837748] kvm [1]: VHE mode initialized successfully
10569 09:29:33.971125 <5>[ 0.844234] Initialise system trusted keyrings
10570 09:29:33.977553 <6>[ 0.849038] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10571 09:29:33.984944 <6>[ 0.859046] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10572 09:29:33.991371 <5>[ 0.865433] NFS: Registering the id_resolver key type
10573 09:29:33.994516 <5>[ 0.870732] Key type id_resolver registered
10574 09:29:34.001200 <5>[ 0.875148] Key type id_legacy registered
10575 09:29:34.008110 <6>[ 0.879438] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10576 09:29:34.014427 <6>[ 0.886360] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10577 09:29:34.020932 <6>[ 0.894072] 9p: Installing v9fs 9p2000 file system support
10578 09:29:34.057224 <5>[ 0.931570] Key type asymmetric registered
10579 09:29:34.060578 <5>[ 0.935901] Asymmetric key parser 'x509' registered
10580 09:29:34.070688 <6>[ 0.941058] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10581 09:29:34.074015 <6>[ 0.948675] io scheduler mq-deadline registered
10582 09:29:34.076780 <6>[ 0.953437] io scheduler kyber registered
10583 09:29:34.096436 <6>[ 0.970494] EINJ: ACPI disabled.
10584 09:29:34.129017 <4>[ 0.996586] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 09:29:34.138655 <4>[ 1.007221] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10586 09:29:34.154472 <6>[ 1.028642] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10587 09:29:34.162509 <6>[ 1.036743] printk: console [ttyS0] disabled
10588 09:29:34.190567 <6>[ 1.061391] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10589 09:29:34.197045 <6>[ 1.070863] printk: console [ttyS0] enabled
10590 09:29:34.200228 <6>[ 1.070863] printk: console [ttyS0] enabled
10591 09:29:34.206863 <6>[ 1.079758] printk: bootconsole [mtk8250] disabled
10592 09:29:34.210733 <6>[ 1.079758] printk: bootconsole [mtk8250] disabled
10593 09:29:34.216722 <6>[ 1.090804] SuperH (H)SCI(F) driver initialized
10594 09:29:34.219994 <6>[ 1.096086] msm_serial: driver initialized
10595 09:29:34.233859 <6>[ 1.104999] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10596 09:29:34.243965 <6>[ 1.113548] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10597 09:29:34.250727 <6>[ 1.122090] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10598 09:29:34.260556 <6>[ 1.130717] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10599 09:29:34.270312 <6>[ 1.139429] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10600 09:29:34.277209 <6>[ 1.148142] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10601 09:29:34.286967 <6>[ 1.156681] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10602 09:29:34.293424 <6>[ 1.165480] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10603 09:29:34.303421 <6>[ 1.174024] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10604 09:29:34.315363 <6>[ 1.189489] loop: module loaded
10605 09:29:34.321522 <6>[ 1.195480] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10606 09:29:34.344625 <4>[ 1.218737] mtk-pmic-keys: Failed to locate of_node [id: -1]
10607 09:29:34.351557 <6>[ 1.225526] megasas: 07.719.03.00-rc1
10608 09:29:34.360609 <6>[ 1.235055] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10609 09:29:34.372595 <6>[ 1.246334] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10610 09:29:34.388525 <6>[ 1.262669] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10611 09:29:34.448493 <6>[ 1.316161] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10612 09:29:34.697140 <6>[ 1.571071] Freeing initrd memory: 18304K
10613 09:29:34.708525 <6>[ 1.582692] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10614 09:29:34.719059 <6>[ 1.593373] tun: Universal TUN/TAP device driver, 1.6
10615 09:29:34.722849 <6>[ 1.599435] thunder_xcv, ver 1.0
10616 09:29:34.725650 <6>[ 1.602930] thunder_bgx, ver 1.0
10617 09:29:34.729408 <6>[ 1.606429] nicpf, ver 1.0
10618 09:29:34.739577 <6>[ 1.610431] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10619 09:29:34.742890 <6>[ 1.617907] hns3: Copyright (c) 2017 Huawei Corporation.
10620 09:29:34.749331 <6>[ 1.623495] hclge is initializing
10621 09:29:34.752675 <6>[ 1.627074] e1000: Intel(R) PRO/1000 Network Driver
10622 09:29:34.759192 <6>[ 1.632204] e1000: Copyright (c) 1999-2006 Intel Corporation.
10623 09:29:34.762703 <6>[ 1.638217] e1000e: Intel(R) PRO/1000 Network Driver
10624 09:29:34.769282 <6>[ 1.643433] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10625 09:29:34.775991 <6>[ 1.649617] igb: Intel(R) Gigabit Ethernet Network Driver
10626 09:29:34.782605 <6>[ 1.655267] igb: Copyright (c) 2007-2014 Intel Corporation.
10627 09:29:34.789348 <6>[ 1.661102] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10628 09:29:34.796232 <6>[ 1.667620] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10629 09:29:34.799423 <6>[ 1.674080] sky2: driver version 1.30
10630 09:29:34.805782 <6>[ 1.679008] usbcore: registered new device driver r8152-cfgselector
10631 09:29:34.812282 <6>[ 1.685565] usbcore: registered new interface driver r8152
10632 09:29:34.818696 <6>[ 1.691375] VFIO - User Level meta-driver version: 0.3
10633 09:29:34.825387 <6>[ 1.699604] usbcore: registered new interface driver usb-storage
10634 09:29:34.831966 <6>[ 1.706049] usbcore: registered new device driver onboard-usb-hub
10635 09:29:34.841105 <6>[ 1.715167] mt6397-rtc mt6359-rtc: registered as rtc0
10636 09:29:34.850632 <6>[ 1.720630] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-18T09:29:34 UTC (1718702974)
10637 09:29:34.854050 <6>[ 1.730193] i2c_dev: i2c /dev entries driver
10638 09:29:34.867994 <4>[ 1.742243] cpu cpu0: supply cpu not found, using dummy regulator
10639 09:29:34.874341 <4>[ 1.748668] cpu cpu1: supply cpu not found, using dummy regulator
10640 09:29:34.881369 <4>[ 1.755074] cpu cpu2: supply cpu not found, using dummy regulator
10641 09:29:34.887787 <4>[ 1.761493] cpu cpu3: supply cpu not found, using dummy regulator
10642 09:29:34.894436 <4>[ 1.767892] cpu cpu4: supply cpu not found, using dummy regulator
10643 09:29:34.901164 <4>[ 1.774291] cpu cpu5: supply cpu not found, using dummy regulator
10644 09:29:34.907560 <4>[ 1.780686] cpu cpu6: supply cpu not found, using dummy regulator
10645 09:29:34.914438 <4>[ 1.787083] cpu cpu7: supply cpu not found, using dummy regulator
10646 09:29:34.933269 <6>[ 1.807713] cpu cpu0: EM: created perf domain
10647 09:29:34.936995 <6>[ 1.812626] cpu cpu4: EM: created perf domain
10648 09:29:34.943799 <6>[ 1.818210] sdhci: Secure Digital Host Controller Interface driver
10649 09:29:34.950469 <6>[ 1.824642] sdhci: Copyright(c) Pierre Ossman
10650 09:29:34.957411 <6>[ 1.829607] Synopsys Designware Multimedia Card Interface Driver
10651 09:29:34.963853 <6>[ 1.836238] sdhci-pltfm: SDHCI platform and OF driver helper
10652 09:29:34.967370 <6>[ 1.836376] mmc0: CQHCI version 5.10
10653 09:29:34.973692 <6>[ 1.846237] ledtrig-cpu: registered to indicate activity on CPUs
10654 09:29:34.980148 <6>[ 1.853113] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10655 09:29:34.987058 <6>[ 1.860160] usbcore: registered new interface driver usbhid
10656 09:29:34.990279 <6>[ 1.865981] usbhid: USB HID core driver
10657 09:29:34.996699 <6>[ 1.870179] spi_master spi0: will run message pump with realtime priority
10658 09:29:35.040061 <6>[ 1.907902] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10659 09:29:35.059093 <6>[ 1.923082] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10660 09:29:35.061993 <6>[ 1.936576] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10661 09:29:35.069444 <6>[ 1.943780] cros-ec-spi spi0.0: Chrome EC device registered
10662 09:29:35.076218 <6>[ 1.949774] mmc0: Command Queue Engine enabled
10663 09:29:35.082837 <6>[ 1.954507] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10664 09:29:35.086120 <6>[ 1.961985] mmcblk0: mmc0:0001 DA4128 116 GiB
10665 09:29:35.096409 <6>[ 1.970936] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10666 09:29:35.104415 <6>[ 1.978317] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10667 09:29:35.114239 <6>[ 1.982551] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10668 09:29:35.117085 <6>[ 1.984255] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10669 09:29:35.123705 <6>[ 1.994095] NET: Registered PF_PACKET protocol family
10670 09:29:35.130452 <6>[ 1.998658] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10671 09:29:35.133913 <6>[ 2.003484] 9pnet: Installing 9P2000 support
10672 09:29:35.140714 <5>[ 2.014458] Key type dns_resolver registered
10673 09:29:35.143989 <6>[ 2.019418] registered taskstats version 1
10674 09:29:35.150113 <5>[ 2.023797] Loading compiled-in X.509 certificates
10675 09:29:35.178528 <4>[ 2.046064] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10676 09:29:35.188520 <4>[ 2.056821] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10677 09:29:35.203062 <6>[ 2.077362] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10678 09:29:35.210203 <6>[ 2.084419] xhci-mtk 11200000.usb: xHCI Host Controller
10679 09:29:35.216755 <6>[ 2.089932] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10680 09:29:35.226721 <6>[ 2.097793] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10681 09:29:35.233666 <6>[ 2.107327] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10682 09:29:35.239945 <6>[ 2.113438] xhci-mtk 11200000.usb: xHCI Host Controller
10683 09:29:35.246536 <6>[ 2.118918] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10684 09:29:35.253062 <6>[ 2.126572] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10685 09:29:35.260293 <6>[ 2.134362] hub 1-0:1.0: USB hub found
10686 09:29:35.263553 <6>[ 2.138394] hub 1-0:1.0: 1 port detected
10687 09:29:35.270419 <6>[ 2.142681] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10688 09:29:35.277438 <6>[ 2.151442] hub 2-0:1.0: USB hub found
10689 09:29:35.280463 <6>[ 2.155464] hub 2-0:1.0: 1 port detected
10690 09:29:35.287751 <6>[ 2.162301] mtk-msdc 11f70000.mmc: Got CD GPIO
10691 09:29:35.301372 <6>[ 2.172394] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10692 09:29:35.311456 <6>[ 2.180780] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10693 09:29:35.318153 <6>[ 2.189122] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10694 09:29:35.328080 <6>[ 2.197461] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10695 09:29:35.334477 <6>[ 2.205799] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10696 09:29:35.344803 <6>[ 2.214136] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10697 09:29:35.351052 <6>[ 2.222475] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10698 09:29:35.361278 <6>[ 2.230813] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10699 09:29:35.367601 <6>[ 2.239150] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10700 09:29:35.377559 <6>[ 2.247488] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10701 09:29:35.384437 <6>[ 2.255826] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10702 09:29:35.394499 <6>[ 2.264174] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10703 09:29:35.401022 <6>[ 2.272513] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10704 09:29:35.410782 <6>[ 2.280851] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10705 09:29:35.417537 <6>[ 2.289189] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10706 09:29:35.424029 <6>[ 2.297912] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10707 09:29:35.430518 <6>[ 2.305065] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10708 09:29:35.437410 <6>[ 2.311858] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10709 09:29:35.447519 <6>[ 2.318629] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10710 09:29:35.454240 <6>[ 2.325556] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10711 09:29:35.460707 <6>[ 2.332446] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10712 09:29:35.470628 <6>[ 2.341580] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10713 09:29:35.480826 <6>[ 2.350702] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10714 09:29:35.490369 <6>[ 2.359996] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10715 09:29:35.500403 <6>[ 2.369465] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10716 09:29:35.510057 <6>[ 2.378934] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10717 09:29:35.517093 <6>[ 2.388054] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10718 09:29:35.526920 <6>[ 2.397520] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10719 09:29:35.536794 <6>[ 2.406639] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10720 09:29:35.546696 <6>[ 2.415937] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10721 09:29:35.556219 <6>[ 2.426097] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10722 09:29:35.566502 <6>[ 2.437620] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10723 09:29:35.573679 <6>[ 2.448272] Trying to probe devices needed for running init ...
10724 09:29:35.584418 <3>[ 2.455524] mt8192-audio 11210000.syscon:mt8192-afe-pcm: could not get audiosys reset:-517
10725 09:29:35.692211 <6>[ 2.563257] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10726 09:29:35.846960 <6>[ 2.721260] hub 1-1:1.0: USB hub found
10727 09:29:35.850113 <6>[ 2.725790] hub 1-1:1.0: 4 ports detected
10728 09:29:35.862142 <6>[ 2.736678] hub 1-1:1.0: USB hub found
10729 09:29:35.865627 <6>[ 2.740975] hub 1-1:1.0: 4 ports detected
10730 09:29:35.972133 <6>[ 2.843457] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10731 09:29:35.998833 <6>[ 2.873389] hub 2-1:1.0: USB hub found
10732 09:29:36.002091 <6>[ 2.877911] hub 2-1:1.0: 3 ports detected
10733 09:29:36.014970 <6>[ 2.889069] hub 2-1:1.0: USB hub found
10734 09:29:36.018097 <6>[ 2.893523] hub 2-1:1.0: 3 ports detected
10735 09:29:36.188041 <6>[ 3.059298] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10736 09:29:36.320502 <6>[ 3.194993] hub 1-1.4:1.0: USB hub found
10737 09:29:36.323667 <6>[ 3.199641] hub 1-1.4:1.0: 2 ports detected
10738 09:29:36.336159 <6>[ 3.210810] hub 1-1.4:1.0: USB hub found
10739 09:29:36.339747 <6>[ 3.215375] hub 1-1.4:1.0: 2 ports detected
10740 09:29:36.400120 <6>[ 3.271422] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10741 09:29:36.508563 <6>[ 3.379932] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10742 09:29:36.545332 <4>[ 3.416478] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10743 09:29:36.555373 <4>[ 3.425602] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10744 09:29:36.590448 <6>[ 3.464855] r8152 2-1.3:1.0 eth0: v1.12.13
10745 09:29:36.635999 <6>[ 3.507151] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10746 09:29:36.831823 <6>[ 3.703303] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10747 09:29:38.222053 <6>[ 5.096690] r8152 2-1.3:1.0 eth0: carrier on
10748 09:29:40.916232 <5>[ 5.119097] Sending DHCP requests .., OK
10749 09:29:40.922717 <6>[ 7.795374] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10750 09:29:40.926099 <6>[ 7.803664] IP-Config: Complete:
10751 09:29:40.939542 <6>[ 7.807163] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10752 09:29:40.946604 <6>[ 7.817872] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10753 09:29:40.952447 <6>[ 7.826488] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10754 09:29:40.959297 <6>[ 7.826497] nameserver0=192.168.201.1
10755 09:29:40.962321 <6>[ 7.838645] clk: Disabling unused clocks
10756 09:29:40.965825 <6>[ 7.844098] ALSA device list:
10757 09:29:40.972295 <6>[ 7.847391] No soundcards found.
10758 09:29:40.979384 <6>[ 7.854125] Freeing unused kernel memory: 8512K
10759 09:29:40.982658 <6>[ 7.859111] Run /init as init process
10760 09:29:40.992016 Loading, please wait...
10761 09:29:41.017467 Starting systemd-udevd version 252.22-1~deb12u1
10762 09:29:41.218006 <6>[ 8.089696] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10763 09:29:41.224782 <6>[ 8.098602] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10764 09:29:41.234459 <6>[ 8.100091] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10765 09:29:41.238196 <6>[ 8.106695] remoteproc remoteproc0: scp is available
10766 09:29:41.248306 <6>[ 8.113919] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10767 09:29:41.251128 <6>[ 8.119175] remoteproc remoteproc0: powering up scp
10768 09:29:41.261168 <3>[ 8.121064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10769 09:29:41.267666 <3>[ 8.121080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10770 09:29:41.277625 <3>[ 8.121087] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 09:29:41.284179 <3>[ 8.122193] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10772 09:29:41.294052 <3>[ 8.122204] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10773 09:29:41.301001 <3>[ 8.122211] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10774 09:29:41.307122 <3>[ 8.122220] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10775 09:29:41.317552 <3>[ 8.122227] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10776 09:29:41.324144 <3>[ 8.122276] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10777 09:29:41.334003 <3>[ 8.123237] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 09:29:41.340976 <3>[ 8.123249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 09:29:41.351119 <3>[ 8.123256] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 09:29:41.357996 <3>[ 8.123317] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 09:29:41.364445 <3>[ 8.123325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 09:29:41.374480 <3>[ 8.123331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 09:29:41.381292 <3>[ 8.123339] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 09:29:41.391010 <3>[ 8.123345] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 09:29:41.397839 <3>[ 8.123384] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10786 09:29:41.404252 <6>[ 8.124131] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10787 09:29:41.414158 <6>[ 8.124411] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10788 09:29:41.424456 <6>[ 8.124421] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10789 09:29:41.431170 <4>[ 8.127170] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10790 09:29:41.440589 <4>[ 8.127386] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10791 09:29:41.447171 <4>[ 8.128783] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10792 09:29:41.453916 <6>[ 8.130176] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10793 09:29:41.463580 <6>[ 8.132112] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10794 09:29:41.467361 <6>[ 8.132120] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10795 09:29:41.476984 <4>[ 8.160625] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10796 09:29:41.483431 <4>[ 8.160625] Fallback method does not support PEC.
10797 09:29:41.490021 <6>[ 8.164968] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10798 09:29:41.493681 <6>[ 8.179313] mc: Linux media interface: v0.10
10799 09:29:41.503353 <6>[ 8.180637] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10800 09:29:41.509835 <3>[ 8.207351] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10801 09:29:41.519490 <6>[ 8.213112] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10802 09:29:41.529824 <3>[ 8.242363] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10803 09:29:41.536459 <6>[ 8.243148] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10804 09:29:41.546187 <6>[ 8.245329] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10805 09:29:41.552489 <6>[ 8.248284] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10806 09:29:41.559386 <6>[ 8.248291] pci_bus 0000:00: root bus resource [bus 00-ff]
10807 09:29:41.565749 <6>[ 8.248297] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10808 09:29:41.575896 <6>[ 8.248303] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10809 09:29:41.582580 <6>[ 8.248333] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10810 09:29:41.589182 <6>[ 8.248353] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10811 09:29:41.592078 <6>[ 8.248429] pci 0000:00:00.0: supports D1 D2
10812 09:29:41.598721 <6>[ 8.248433] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10813 09:29:41.608662 <6>[ 8.250158] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10814 09:29:41.615388 <6>[ 8.250284] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10815 09:29:41.621857 <6>[ 8.250317] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10816 09:29:41.628964 <6>[ 8.250338] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10817 09:29:41.638664 <6>[ 8.250357] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10818 09:29:41.641720 <6>[ 8.250476] pci 0000:01:00.0: supports D1 D2
10819 09:29:41.648532 <6>[ 8.250480] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10820 09:29:41.655269 <6>[ 8.257827] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10821 09:29:41.664720 <6>[ 8.257865] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10822 09:29:41.671800 <6>[ 8.257869] remoteproc remoteproc0: remote processor scp is now up
10823 09:29:41.678120 <6>[ 8.259279] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10824 09:29:41.684719 <6>[ 8.259306] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10825 09:29:41.694688 <6>[ 8.259313] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10826 09:29:41.701225 <6>[ 8.259327] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10827 09:29:41.708026 <6>[ 8.259345] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10828 09:29:41.717872 <6>[ 8.259362] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10829 09:29:41.721077 <6>[ 8.259379] pci 0000:00:00.0: PCI bridge to [bus 01]
10830 09:29:41.731210 <6>[ 8.259387] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10831 09:29:41.737820 <6>[ 8.259504] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10832 09:29:41.744285 <6>[ 8.260497] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10833 09:29:41.747387 <6>[ 8.260878] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10834 09:29:41.757603 <6>[ 8.261432] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10835 09:29:41.767198 <6>[ 8.261435] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10836 09:29:41.777102 <6>[ 8.445070] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10837 09:29:41.787354 <6>[ 8.656635] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10838 09:29:41.793721 <6>[ 8.667469] videodev: Linux video capture interface: v2.00
10839 09:29:41.796950 <6>[ 8.673811] Bluetooth: Core ver 2.22
10840 09:29:41.803784 <6>[ 8.677681] NET: Registered PF_BLUETOOTH protocol family
10841 09:29:41.810272 <6>[ 8.683244] Bluetooth: HCI device and connection manager initialized
10842 09:29:41.813958 <6>[ 8.689851] Bluetooth: HCI socket layer initialized
10843 09:29:41.823663 <6>[ 8.690767] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10844 09:29:41.830602 <5>[ 8.691807] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10845 09:29:41.836596 <6>[ 8.694980] Bluetooth: L2CAP socket layer initialized
10846 09:29:41.839807 <6>[ 8.694986] Bluetooth: SCO socket layer initialized
10847 09:29:41.849755 <5>[ 8.700148] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10848 09:29:41.856495 <6>[ 8.705903] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10849 09:29:41.866877 <5>[ 8.711487] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10850 09:29:41.873105 <6>[ 8.717132] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10851 09:29:41.879708 <4>[ 8.721732] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10852 09:29:41.886117 <6>[ 8.721736] cfg80211: failed to load regulatory.db
10853 09:29:41.899309 <6>[ 8.729668] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10854 09:29:41.903158 <6>[ 8.752474] usbcore: registered new interface driver btusb
10855 09:29:41.909370 <6>[ 8.752520] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10856 09:29:41.922830 <4>[ 8.753177] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10857 09:29:41.926074 <3>[ 8.753187] Bluetooth: hci0: Failed to load firmware file (-2)
10858 09:29:41.933066 <3>[ 8.753192] Bluetooth: hci0: Failed to set up firmware (-2)
10859 09:29:41.942323 <4>[ 8.753196] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10860 09:29:41.949449 <6>[ 8.761130] usbcore: registered new interface driver uvcvideo
10861 09:29:41.955564 <6>[ 8.815306] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10862 09:29:41.961882 <6>[ 8.837005] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10863 09:29:41.988068 <6>[ 8.863147] mt7921e 0000:01:00.0: ASIC revision: 79610010
10864 09:29:42.081693 <6>[ 8.953489] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10865 09:29:42.085256 <6>[ 8.953489]
10866 09:29:42.088493 Begin: Loading essential drivers ... done.
10867 09:29:42.091429 Begin: Running /scripts/init-premount ... done.
10868 09:29:42.097980 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10869 09:29:42.107888 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10870 09:29:42.111225 Device /sys/class/net/eth0 found
10871 09:29:42.111331 done.
10872 09:29:42.117916 Begin: Waiting up to 180 secs for any network device to become available ... done.
10873 09:29:42.160343 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10874 09:29:42.166922 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10875 09:29:42.173652 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10876 09:29:42.179844 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10877 09:29:42.186333 host : mt8192-asurada-spherion-r0-cbg-9
10878 09:29:42.193229 domain : lava-rack
10879 09:29:42.196372 rootserver: 192.168.201.1 rootpath:
10880 09:29:42.199301 filename :
10881 09:29:42.307641 done.
10882 09:29:42.315726 Begin: Running /scripts/nfs-bottom ... done.
10883 09:29:42.324639 Begin: Running /scripts/init-bottom ... done.
10884 09:29:42.347834 <6>[ 9.219612] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10885 09:29:43.689123 <6>[ 10.564368] NET: Registered PF_INET6 protocol family
10886 09:29:43.696760 <6>[ 10.571763] Segment Routing with IPv6
10887 09:29:43.699777 <6>[ 10.575749] In-situ OAM (IOAM) with IPv6
10888 09:29:43.873513 <30>[ 10.722469] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10889 09:29:43.880225 <30>[ 10.755578] systemd[1]: Detected architecture arm64.
10890 09:29:43.889062
10891 09:29:43.892374 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10892 09:29:43.892460
10893 09:29:43.917276 <30>[ 10.792825] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10894 09:29:44.953923 <30>[ 11.825899] systemd[1]: Queued start job for default target graphical.target.
10895 09:29:45.000138 <30>[ 11.872442] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10896 09:29:45.006674 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10897 09:29:45.029179 <30>[ 11.900981] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10898 09:29:45.038545 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10899 09:29:45.056866 <30>[ 11.928996] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10900 09:29:45.066942 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10901 09:29:45.084453 <30>[ 11.956665] systemd[1]: Created slice user.slice - User and Session Slice.
10902 09:29:45.091446 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10903 09:29:45.115615 <30>[ 11.984040] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10904 09:29:45.125396 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10905 09:29:45.142615 <30>[ 12.011503] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10906 09:29:45.149302 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10907 09:29:45.177565 <30>[ 12.039829] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10908 09:29:45.187306 <30>[ 12.059692] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10909 09:29:45.194487 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10910 09:29:45.211074 <30>[ 12.083267] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10911 09:29:45.217966 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10912 09:29:45.235236 <30>[ 12.107312] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10913 09:29:45.245049 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10914 09:29:45.259765 <30>[ 12.135388] systemd[1]: Reached target paths.target - Path Units.
10915 09:29:45.269952 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10916 09:29:45.287045 <30>[ 12.159286] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10917 09:29:45.293773 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10918 09:29:45.307808 <30>[ 12.183262] systemd[1]: Reached target slices.target - Slice Units.
10919 09:29:45.318091 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10920 09:29:45.331978 <30>[ 12.207297] systemd[1]: Reached target swap.target - Swaps.
10921 09:29:45.338429 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10922 09:29:45.359780 <30>[ 12.231706] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10923 09:29:45.369451 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10924 09:29:45.387943 <30>[ 12.260124] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10925 09:29:45.397981 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10926 09:29:45.418472 <30>[ 12.290397] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10927 09:29:45.428048 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10928 09:29:45.444580 <30>[ 12.316813] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10929 09:29:45.454643 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10930 09:29:45.472491 <30>[ 12.343911] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10931 09:29:45.478123 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10932 09:29:45.496637 <30>[ 12.368841] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10933 09:29:45.506461 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10934 09:29:45.526908 <30>[ 12.398393] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10935 09:29:45.535763 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10936 09:29:45.551820 <30>[ 12.423748] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10937 09:29:45.561242 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10938 09:29:45.615585 <30>[ 12.487477] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10939 09:29:45.621654 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10940 09:29:45.643495 <30>[ 12.515673] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10941 09:29:45.650133 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10942 09:29:45.711604 <30>[ 12.583573] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10943 09:29:45.718089 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10944 09:29:45.741623 <30>[ 12.607446] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10945 09:29:45.757069 <30>[ 12.629076] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10946 09:29:45.766731 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10947 09:29:45.788162 <30>[ 12.660254] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10948 09:29:45.794772 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10949 09:29:45.859483 <30>[ 12.731836] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10950 09:29:45.866194 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10951 09:29:45.890333 <30>[ 12.762756] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10952 09:29:45.900641 Starting [0;1;39mmodpr<6>[ 12.772895] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10953 09:29:45.907430 obe@drm.service[0m - Load Kernel Module drm...
10954 09:29:45.959571 <30>[ 12.831798] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10955 09:29:45.969427 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10956 09:29:45.992876 <30>[ 12.864874] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10957 09:29:45.999379 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10958 09:29:46.022853 <30>[ 12.895228] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10959 09:29:46.033023 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 12.908912] fuse: init (API version 7.37)
10960 09:29:46.033166 el Module loop...
10961 09:29:46.058137 <30>[ 12.930389] systemd[1]: Starting systemd-journald.service - Journal Service...
10962 09:29:46.064446 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10963 09:29:46.090840 <30>[ 12.962955] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10964 09:29:46.096968 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10965 09:29:46.122866 <30>[ 12.991950] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10966 09:29:46.130054 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10967 09:29:46.151018 <30>[ 13.023430] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10968 09:29:46.160829 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10969 09:29:46.184213 <30>[ 13.056162] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10970 09:29:46.190646 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10971 09:29:46.218701 <30>[ 13.090665] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10972 09:29:46.225101 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10973 09:29:46.235387 <3>[ 13.107234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 09:29:46.244873 <30>[ 13.116768] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10975 09:29:46.251485 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10976 09:29:46.272212 <30>[ 13.144255] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10977 09:29:46.281641 [[0;32m OK [<3>[ 13.152381] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 09:29:46.288841 0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10979 09:29:46.312148 <30>[ 13.184153] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10980 09:29:46.321659 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10981 09:29:46.340576 <30>[ 13.212686] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10982 09:29:46.347505 <30>[ 13.220861] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10983 09:29:46.360788 [[0;32m OK [<3>[ 13.230959] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10984 09:29:46.367470 0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10985 09:29:46.387672 <3>[ 13.259826] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 09:29:46.394142 <30>[ 13.260995] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10987 09:29:46.404363 <30>[ 13.276725] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10988 09:29:46.414006 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10989 09:29:46.431863 <3>[ 13.303787] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 09:29:46.437845 <30>[ 13.303973] systemd[1]: modprobe@drm.service: Deactivated successfully.
10991 09:29:46.448197 <30>[ 13.320316] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10992 09:29:46.461479 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Mod<3>[ 13.333764] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10993 09:29:46.465181 ule drm.
10994 09:29:46.484999 <30>[ 13.356816] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10995 09:29:46.495033 <30>[ 13.365125] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10996 09:29:46.501461 <3>[ 13.367503] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10997 09:29:46.511327 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10998 09:29:46.529267 <30>[ 13.401018] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10999 09:29:46.535825 <3>[ 13.405604] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11000 09:29:46.545874 <30>[ 13.408564] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11001 09:29:46.552407 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11002 09:29:46.572844 <30>[ 13.445069] systemd[1]: modprobe@loop.service: Deactivated successfully.
11003 09:29:46.579678 <3>[ 13.445320] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11004 09:29:46.589764 <3>[ 13.446137] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
11005 09:29:46.603599 <4>[ 13.446148] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11006 09:29:46.613411 <3>[ 13.446151] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
11007 09:29:46.619689 <30>[ 13.452851] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11008 09:29:46.630497 <3>[ 13.482547] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11009 09:29:46.636116 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11010 09:29:46.659983 <30>[ 13.532129] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
11011 09:29:46.669717 [[0;32m OK [<3>[ 13.540874] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11012 09:29:46.676132 0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11013 09:29:46.703790 <30>[ 13.572650] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
11014 09:29:46.710429 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11015 09:29:46.732797 <30>[ 13.604431] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
11016 09:29:46.742177 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11017 09:29:46.759275 <30>[ 13.631671] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
11018 09:29:46.766657 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11019 09:29:46.787303 <30>[ 13.659696] systemd[1]: Started systemd-journald.service - Journal Service.
11020 09:29:46.793990 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11021 09:29:46.816990 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11022 09:29:46.855577 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11023 09:29:46.875939 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11024 09:29:46.899794 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11025 09:29:46.924614 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11026 09:29:46.956118 Starting [0;1;39msyste<46>[ 13.827089] systemd-journald[313]: Received client request to flush runtime journal.
11027 09:29:46.959570 md-sysctl.se…ce[0m - Apply Kernel Variables...
11028 09:29:47.027644 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11029 09:29:47.276578 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11030 09:29:47.295466 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11031 09:29:47.316166 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11032 09:29:47.363435 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11033 09:29:48.389099 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11034 09:29:48.411968 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11035 09:29:48.463562 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11036 09:29:48.561492 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11037 09:29:48.579568 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11038 09:29:48.603125 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11039 09:29:48.643368 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11040 09:29:48.669178 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11041 09:29:48.950549 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11042 09:29:49.003249 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11043 09:29:49.071420 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11044 09:29:49.225438 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11045 09:29:49.270775 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11046 09:29:49.287741 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11047 09:29:49.355846 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11048 09:29:49.375420 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11049 09:29:49.391882 <6>[ 16.267277] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11050 09:29:49.447981 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11051 09:29:49.472277 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11052 09:29:49.492811 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11053 09:29:49.509105 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11054 09:29:49.619919 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11055 09:29:49.650426 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11056 09:29:49.669250 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11057 09:29:49.688048 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11058 09:29:49.812982 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11059 09:29:49.836003 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11060 09:29:49.851269 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11061 09:29:49.866949 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11062 09:29:49.892091 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11063 09:29:49.913940 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11064 09:29:49.931005 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11065 09:29:49.950606 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11066 09:29:49.970955 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11067 09:29:49.986579 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11068 09:29:50.005070 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11069 09:29:50.022421 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11070 09:29:50.038998 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11071 09:29:50.080521 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11072 09:29:50.118023 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11073 09:29:50.229193 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11074 09:29:50.256513 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11075 09:29:50.306862 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11076 09:29:50.355417 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11077 09:29:50.376884 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11078 09:29:50.400555 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11079 09:29:50.415760 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11080 09:29:50.458866 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11081 09:29:50.608743 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11082 09:29:50.633457 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11083 09:29:50.651312 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11084 09:29:50.707872 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11085 09:29:50.798506 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11086 09:29:50.880689
11087 09:29:50.884234 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11088 09:29:50.884333
11089 09:29:50.887007 debian-bookworm-arm64 login: root (automatic login)
11090 09:29:50.887084
11091 09:29:51.192494 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
11092 09:29:51.192639
11093 09:29:51.199275 The programs included with the Debian GNU/Linux system are free software;
11094 09:29:51.206072 the exact distribution terms for each program are described in the
11095 09:29:51.208795 individual files in /usr/share/doc/*/copyright.
11096 09:29:51.208871
11097 09:29:51.215554 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11098 09:29:51.218723 permitted by applicable law.
11099 09:29:52.275319 Matched prompt #10: / #
11101 09:29:52.275699 Setting prompt string to ['/ #']
11102 09:29:52.275808 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11104 09:29:52.276118 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11105 09:29:52.276223 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
11106 09:29:52.276299 Setting prompt string to ['/ #']
11107 09:29:52.276394 Forcing a shell prompt, looking for ['/ #']
11109 09:29:52.326689 / #
11110 09:29:52.326860 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11111 09:29:52.326955 Waiting using forced prompt support (timeout 00:02:30)
11112 09:29:52.331538
11113 09:29:52.331819 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11114 09:29:52.331921 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11116 09:29:52.432352 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407642/extract-nfsrootfs-ibllctfm'
11117 09:29:52.437252 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407642/extract-nfsrootfs-ibllctfm'
11119 09:29:52.537828 / # export NFS_SERVER_IP='192.168.201.1'
11120 09:29:52.542607 export NFS_SERVER_IP='192.168.201.1'
11121 09:29:52.542907 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11122 09:29:52.543017 end: 2.2 depthcharge-retry (duration 00:01:46) [common]
11123 09:29:52.543122 end: 2 depthcharge-action (duration 00:01:46) [common]
11124 09:29:52.543223 start: 3 lava-test-retry (timeout 00:07:35) [common]
11125 09:29:52.543322 start: 3.1 lava-test-shell (timeout 00:07:35) [common]
11126 09:29:52.543430 Using namespace: common
11128 09:29:52.643817 / # #
11129 09:29:52.644012 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11130 09:29:52.648778 #
11131 09:29:52.649046 Using /lava-14407642
11133 09:29:52.749358 / # export SHELL=/bin/bash
11134 09:29:52.754146 export SHELL=/bin/bash
11136 09:29:52.854734 / # . /lava-14407642/environment
11137 09:29:52.860361 . /lava-14407642/environment
11139 09:29:52.967046 / # /lava-14407642/bin/lava-test-runner /lava-14407642/0
11140 09:29:52.967247 Test shell timeout: 10s (minimum of the action and connection timeout)
11141 09:29:52.972410 /lava-14407642/bin/lava-test-runner /lava-14407642/0
11142 09:29:53.251732 + export TESTRUN_ID=0_timesync-off
11143 09:29:53.254944 + TESTRUN_ID=0_timesync-off
11144 09:29:53.258146 + cd /lava-14407642/0/tests/0_timesync-off
11145 09:29:53.261488 ++ cat uuid
11146 09:29:53.266801 + UUID=14407642_1.6.2.3.1
11147 09:29:53.266913 + set +x
11148 09:29:53.273091 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14407642_1.6.2.3.1>
11149 09:29:53.273393 Received signal: <STARTRUN> 0_timesync-off 14407642_1.6.2.3.1
11150 09:29:53.273544 Starting test lava.0_timesync-off (14407642_1.6.2.3.1)
11151 09:29:53.273670 Skipping test definition patterns.
11152 09:29:53.276074 + systemctl stop systemd-timesyncd
11153 09:29:53.350037 + set +x
11154 09:29:53.353065 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14407642_1.6.2.3.1>
11155 09:29:53.353372 Received signal: <ENDRUN> 0_timesync-off 14407642_1.6.2.3.1
11156 09:29:53.353496 Ending use of test pattern.
11157 09:29:53.353595 Ending test lava.0_timesync-off (14407642_1.6.2.3.1), duration 0.08
11159 09:29:53.428157 + export TESTRUN_ID=1_kselftest-tpm2
11160 09:29:53.431576 + TESTRUN_ID=1_kselftest-tpm2
11161 09:29:53.437866 + cd /lava-14407642/0/tests/1_kselftest-tpm2
11162 09:29:53.437982 ++ cat uuid
11163 09:29:53.442462 + UUID=14407642_1.6.2.3.5
11164 09:29:53.442569 + set +x
11165 09:29:53.449143 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 14407642_1.6.2.3.5>
11166 09:29:53.449430 Received signal: <STARTRUN> 1_kselftest-tpm2 14407642_1.6.2.3.5
11167 09:29:53.449538 Starting test lava.1_kselftest-tpm2 (14407642_1.6.2.3.5)
11168 09:29:53.449656 Skipping test definition patterns.
11169 09:29:53.452779 + cd ./automated/linux/kselftest/
11170 09:29:53.478902 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11171 09:29:53.522093 INFO: install_deps skipped
11172 09:29:54.033288 --2024-06-18 09:29:53-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11173 09:29:54.050120 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11174 09:29:54.175095 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11175 09:29:54.300406 HTTP request sent, awaiting response... 200 OK
11176 09:29:54.303566 Length: 1642672 (1.6M) [application/octet-stream]
11177 09:29:54.306905 Saving to: 'kselftest_armhf.tar.gz'
11178 09:29:54.306987
11179 09:29:54.307072
11180 09:29:54.550037 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11181 09:29:54.802920 kselftest_armhf.tar 2%[ ] 44.98K 180KB/s
11182 09:29:55.053578 kselftest_armhf.tar 13%[=> ] 217.50K 433KB/s
11183 09:29:55.299641 kselftest_armhf.tar 54%[=========> ] 870.79K 1.13MB/s
11184 09:29:55.550009 kselftest_armhf.tar 79%[==============> ] 1.24M 1.25MB/s
11185 09:29:55.802049 kselftest_armhf.tar 79%[==============> ] 1.25M 1.00MB/s
11186 09:29:56.051799 kselftest_armhf.tar 80%[===============> ] 1.26M 862KB/s
11187 09:29:56.302873 kselftest_armhf.tar 85%[================> ] 1.33M 780KB/s
11188 09:29:56.309361 kselftest_armhf.tar 98%[==================> ] 1.54M 787KB/s
11189 09:29:56.315789 kselftest_armhf.tar 100%[===================>] 1.57M 800KB/s in 2.0s
11190 09:29:56.315883
11191 09:29:56.456934 2024-06-18 09:29:55 (800 KB/s) - 'kselftest_armhf.tar.gz' saved [1642672/1642672]
11192 09:29:56.457082
11193 09:30:01.111020 skiplist:
11194 09:30:01.114342 ========================================
11195 09:30:01.117554 ========================================
11196 09:30:01.168095 tpm2:test_smoke.sh
11197 09:30:01.171143 tpm2:test_space.sh
11198 09:30:01.190137 ============== Tests to run ===============
11199 09:30:01.193492 tpm2:test_smoke.sh
11200 09:30:01.193592 tpm2:test_space.sh
11201 09:30:01.196810 ===========End Tests to run ===============
11202 09:30:01.200017 shardfile-tpm2 pass
11203 09:30:01.307290 <12>[ 28.184442] kselftest: Running tests in tpm2
11204 09:30:01.316863 TAP version 13
11205 09:30:01.331460 1..2
11206 09:30:01.362191 # selftests: tpm2: test_smoke.sh
11207 09:30:03.210892 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
11208 09:30:03.217510 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
11209 09:30:03.223981 # Exception ignored in: <function Client.__del__ at 0xffff93e2ccc0>
11210 09:30:03.227426 # Traceback (most recent call last):
11211 09:30:03.237368 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11212 09:30:03.237504 # if self.tpm:
11213 09:30:03.240535 # ^^^^^^^^
11214 09:30:03.243777 # AttributeError: 'Client' object has no attribute 'tpm'
11215 09:30:03.250731 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
11216 09:30:03.257163 # Exception ignored in: <function Client.__del__ at 0xffff93e2ccc0>
11217 09:30:03.260701 # Traceback (most recent call last):
11218 09:30:03.270503 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11219 09:30:03.270628 # if self.tpm:
11220 09:30:03.273732 # ^^^^^^^^
11221 09:30:03.277289 # AttributeError: 'Client' object has no attribute 'tpm'
11222 09:30:03.286867 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
11223 09:30:03.290745 # Exception ignored in: <function Client.__del__ at 0xffff93e2ccc0>
11224 09:30:03.293726 # Traceback (most recent call last):
11225 09:30:03.303798 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11226 09:30:03.307123 # if self.tpm:
11227 09:30:03.307222 # ^^^^^^^^
11228 09:30:03.313659 # AttributeError: 'Client' object has no attribute 'tpm'
11229 09:30:03.320039 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
11230 09:30:03.326762 # Exception ignored in: <function Client.__del__ at 0xffff93e2ccc0>
11231 09:30:03.330344 # Traceback (most recent call last):
11232 09:30:03.340110 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11233 09:30:03.343222 # if self.tpm:
11234 09:30:03.343317 # ^^^^^^^^
11235 09:30:03.349918 # AttributeError: 'Client' object has no attribute 'tpm'
11236 09:30:03.356647 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
11237 09:30:03.359912 # Exception ignored in: <function Client.__del__ at 0xffff93e2ccc0>
11238 09:30:03.363304 # Traceback (most recent call last):
11239 09:30:03.373063 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11240 09:30:03.376151 # if self.tpm:
11241 09:30:03.376254 # ^^^^^^^^
11242 09:30:03.382910 # AttributeError: 'Client' object has no attribute 'tpm'
11243 09:30:03.389778 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
11244 09:30:03.396127 # Exception ignored in: <function Client.__del__ at 0xffff93e2ccc0>
11245 09:30:03.399825 # Traceback (most recent call last):
11246 09:30:03.409396 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11247 09:30:03.409522 # if self.tpm:
11248 09:30:03.412917 # ^^^^^^^^
11249 09:30:03.415820 # AttributeError: 'Client' object has no attribute 'tpm'
11250 09:30:03.425959 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
11251 09:30:03.429249 # Exception ignored in: <function Client.__del__ at 0xffff93e2ccc0>
11252 09:30:03.432518 # Traceback (most recent call last):
11253 09:30:03.442762 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11254 09:30:03.445768 # if self.tpm:
11255 09:30:03.445862 # ^^^^^^^^
11256 09:30:03.452581 # AttributeError: 'Client' object has no attribute 'tpm'
11257 09:30:03.459158 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
11258 09:30:03.465864 # Exception ignored in: <function Client.__del__ at 0xffff93e2ccc0>
11259 09:30:03.469165 # Traceback (most recent call last):
11260 09:30:03.478910 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11261 09:30:03.482092 # if self.tpm:
11262 09:30:03.482229 # ^^^^^^^^
11263 09:30:03.488686 # AttributeError: 'Client' object has no attribute 'tpm'
11264 09:30:03.488790 #
11265 09:30:03.495582 # ======================================================================
11266 09:30:03.501908 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
11267 09:30:03.508501 # ----------------------------------------------------------------------
11268 09:30:03.511909 # Traceback (most recent call last):
11269 09:30:03.522058 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11270 09:30:03.525016 # self.root_key = self.client.create_root_key()
11271 09:30:03.531560 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11272 09:30:03.541660 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11273 09:30:03.548089 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11274 09:30:03.551331 # ^^^^^^^^^^^^^^^^^^
11275 09:30:03.561098 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11276 09:30:03.564763 # raise ProtocolError(cc, rc)
11277 09:30:03.572767 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11278 09:30:03.572896 #
11279 09:30:03.576792 # ======================================================================
11280 09:30:03.583851 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
11281 09:30:03.590690 # ----------------------------------------------------------------------
11282 09:30:03.593862 # Traceback (most recent call last):
11283 09:30:03.603991 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11284 09:30:03.607142 # self.client = tpm2.Client()
11285 09:30:03.610482 # ^^^^^^^^^^^^^
11286 09:30:03.620825 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11287 09:30:03.623582 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11288 09:30:03.630630 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11289 09:30:03.633573 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11290 09:30:03.637018 #
11291 09:30:03.640461 # ======================================================================
11292 09:30:03.647038 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
11293 09:30:03.653466 # ----------------------------------------------------------------------
11294 09:30:03.656750 # Traceback (most recent call last):
11295 09:30:03.666862 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11296 09:30:03.670214 # self.client = tpm2.Client()
11297 09:30:03.673455 # ^^^^^^^^^^^^^
11298 09:30:03.683388 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11299 09:30:03.689929 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11300 09:30:03.693286 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11301 09:30:03.699982 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11302 09:30:03.700091 #
11303 09:30:03.706682 # ======================================================================
11304 09:30:03.713384 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
11305 09:30:03.719698 # ----------------------------------------------------------------------
11306 09:30:03.722851 # Traceback (most recent call last):
11307 09:30:03.733144 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11308 09:30:03.736396 # self.client = tpm2.Client()
11309 09:30:03.739732 # ^^^^^^^^^^^^^
11310 09:30:03.749324 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11311 09:30:03.752793 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11312 09:30:03.759560 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11313 09:30:03.762563 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11314 09:30:03.762666 #
11315 09:30:03.769138 # ======================================================================
11316 09:30:03.779379 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
11317 09:30:03.785717 # ----------------------------------------------------------------------
11318 09:30:03.788913 # Traceback (most recent call last):
11319 09:30:03.799201 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11320 09:30:03.799341 # self.client = tpm2.Client()
11321 09:30:03.802221 # ^^^^^^^^^^^^^
11322 09:30:03.812195 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11323 09:30:03.818976 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11324 09:30:03.822411 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11325 09:30:03.828601 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11326 09:30:03.828715 #
11327 09:30:03.835272 # ======================================================================
11328 09:30:03.842085 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11329 09:30:03.848782 # ----------------------------------------------------------------------
11330 09:30:03.851591 # Traceback (most recent call last):
11331 09:30:03.861848 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11332 09:30:03.865117 # self.client = tpm2.Client()
11333 09:30:03.868378 # ^^^^^^^^^^^^^
11334 09:30:03.878464 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11335 09:30:03.881472 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11336 09:30:03.888225 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11337 09:30:03.891783 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11338 09:30:03.891883 #
11339 09:30:03.898028 # ======================================================================
11340 09:30:03.904550 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11341 09:30:03.911315 # ----------------------------------------------------------------------
11342 09:30:03.914480 # Traceback (most recent call last):
11343 09:30:03.924636 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11344 09:30:03.927755 # self.client = tpm2.Client()
11345 09:30:03.931464 # ^^^^^^^^^^^^^
11346 09:30:03.942100 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11347 09:30:03.945683 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11348 09:30:03.949524 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11349 09:30:03.955817 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11350 09:30:03.955931 #
11351 09:30:03.962513 # ======================================================================
11352 09:30:03.969973 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11353 09:30:03.977070 # ----------------------------------------------------------------------
11354 09:30:03.980759 # Traceback (most recent call last):
11355 09:30:03.989267 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11356 09:30:03.993115 # self.client = tpm2.Client()
11357 09:30:03.996314 # ^^^^^^^^^^^^^
11358 09:30:04.005981 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11359 09:30:04.009212 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11360 09:30:04.015795 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11361 09:30:04.019174 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11362 09:30:04.022478 #
11363 09:30:04.026045 # ======================================================================
11364 09:30:04.035897 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11365 09:30:04.042450 # ----------------------------------------------------------------------
11366 09:30:04.045731 # Traceback (most recent call last):
11367 09:30:04.055902 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11368 09:30:04.059384 # self.client = tpm2.Client()
11369 09:30:04.062449 # ^^^^^^^^^^^^^
11370 09:30:04.072502 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11371 09:30:04.075542 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11372 09:30:04.082112 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11373 09:30:04.085556 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11374 09:30:04.085648 #
11375 09:30:04.092362 # ----------------------------------------------------------------------
11376 09:30:04.095249 # Ran 9 tests in 0.061s
11377 09:30:04.095337 #
11378 09:30:04.098593 # FAILED (errors=9)
11379 09:30:04.102009 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11380 09:30:04.108551 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11381 09:30:04.108653 #
11382 09:30:04.114994 # ----------------------------------------------------------------------
11383 09:30:04.118346 # Ran 2 tests in 0.029s
11384 09:30:04.118440 #
11385 09:30:04.118503 # OK
11386 09:30:04.122441 ok 1 selftests: tpm2: test_smoke.sh
11387 09:30:04.125407 # selftests: tpm2: test_space.sh
11388 09:30:04.131408 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11389 09:30:04.138443 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11390 09:30:04.144850 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11391 09:30:04.151547 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11392 09:30:04.151662 #
11393 09:30:04.158292 # ======================================================================
11394 09:30:04.164857 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11395 09:30:04.171771 # ----------------------------------------------------------------------
11396 09:30:04.174536 # Traceback (most recent call last):
11397 09:30:04.184689 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11398 09:30:04.187823 # root1 = space1.create_root_key()
11399 09:30:04.191170 # ^^^^^^^^^^^^^^^^^^^^^^^^
11400 09:30:04.201607 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11401 09:30:04.207762 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11402 09:30:04.211164 # ^^^^^^^^^^^^^^^^^^
11403 09:30:04.221655 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11404 09:30:04.224527 # raise ProtocolError(cc, rc)
11405 09:30:04.231038 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11406 09:30:04.231164 #
11407 09:30:04.237465 # ======================================================================
11408 09:30:04.244197 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11409 09:30:04.250842 # ----------------------------------------------------------------------
11410 09:30:04.254235 # Traceback (most recent call last):
11411 09:30:04.263938 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11412 09:30:04.267446 # space1.create_root_key()
11413 09:30:04.277317 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11414 09:30:04.283858 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11415 09:30:04.287125 # ^^^^^^^^^^^^^^^^^^
11416 09:30:04.296858 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11417 09:30:04.300253 # raise ProtocolError(cc, rc)
11418 09:30:04.306858 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11419 09:30:04.306968 #
11420 09:30:04.313579 # ======================================================================
11421 09:30:04.320336 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11422 09:30:04.327013 # ----------------------------------------------------------------------
11423 09:30:04.329826 # Traceback (most recent call last):
11424 09:30:04.339977 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11425 09:30:04.343891 # root1 = space1.create_root_key()
11426 09:30:04.346952 # ^^^^^^^^^^^^^^^^^^^^^^^^
11427 09:30:04.356443 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11428 09:30:04.363218 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11429 09:30:04.366360 # ^^^^^^^^^^^^^^^^^^
11430 09:30:04.376186 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11431 09:30:04.379949 # raise ProtocolError(cc, rc)
11432 09:30:04.386311 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11433 09:30:04.386438 #
11434 09:30:04.392753 # ======================================================================
11435 09:30:04.399630 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11436 09:30:04.405864 # ----------------------------------------------------------------------
11437 09:30:04.409516 # Traceback (most recent call last):
11438 09:30:04.422448 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11439 09:30:04.425751 # root1 = space1.create_root_key()
11440 09:30:04.429211 # ^^^^^^^^^^^^^^^^^^^^^^^^
11441 09:30:04.439009 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11442 09:30:04.442655 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11443 09:30:04.449319 # ^^^^^^^^^^^^^^^^^^
11444 09:30:04.459321 # File "/lava-14407642/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11445 09:30:04.462475 # raise ProtocolError(cc, rc)
11446 09:30:04.468936 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11447 09:30:04.469046 #
11448 09:30:04.475791 # ----------------------------------------------------------------------
11449 09:30:04.475894 # Ran 4 tests in 0.089s
11450 09:30:04.475959 #
11451 09:30:04.479032 # FAILED (errors=4)
11452 09:30:04.481942 not ok 2 selftests: tpm2: test_space.sh # exit=1
11453 09:30:05.013922 tpm2_test_smoke_sh pass
11454 09:30:05.017212 tpm2_test_space_sh fail
11455 09:30:05.076516 + ../../utils/send-to-lava.sh ./output/result.txt
11456 09:30:05.154798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11457 09:30:05.155137 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11459 09:30:05.205578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11460 09:30:05.205896 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11462 09:30:05.258468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11463 09:30:05.258785 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11465 09:30:05.261744 + set +x
11466 09:30:05.265249 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 14407642_1.6.2.3.5>
11467 09:30:05.265506 Received signal: <ENDRUN> 1_kselftest-tpm2 14407642_1.6.2.3.5
11468 09:30:05.265582 Ending use of test pattern.
11469 09:30:05.265643 Ending test lava.1_kselftest-tpm2 (14407642_1.6.2.3.5), duration 11.82
11471 09:30:05.268051 <LAVA_TEST_RUNNER EXIT>
11472 09:30:05.268303 ok: lava_test_shell seems to have completed
11473 09:30:05.268406 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11474 09:30:05.268494 end: 3.1 lava-test-shell (duration 00:00:13) [common]
11475 09:30:05.268577 end: 3 lava-test-retry (duration 00:00:13) [common]
11476 09:30:05.268661 start: 4 finalize (timeout 00:07:22) [common]
11477 09:30:05.268746 start: 4.1 power-off (timeout 00:00:30) [common]
11478 09:30:05.268888 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11479 09:30:05.472371 >> Command sent successfully.
11480 09:30:05.474830 Returned 0 in 0 seconds
11481 09:30:05.575258 end: 4.1 power-off (duration 00:00:00) [common]
11483 09:30:05.575672 start: 4.2 read-feedback (timeout 00:07:22) [common]
11484 09:30:05.575975 Listened to connection for namespace 'common' for up to 1s
11485 09:30:06.576943 Finalising connection for namespace 'common'
11486 09:30:06.577139 Disconnecting from shell: Finalise
11487 09:30:06.577217 / #
11488 09:30:06.677573 end: 4.2 read-feedback (duration 00:00:01) [common]
11489 09:30:06.677759 end: 4 finalize (duration 00:00:01) [common]
11490 09:30:06.677879 Cleaning after the job
11491 09:30:06.677978 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/ramdisk
11492 09:30:06.680014 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/kernel
11493 09:30:06.690520 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/dtb
11494 09:30:06.690721 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/nfsrootfs
11495 09:30:06.753529 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407642/tftp-deploy-loscb235/modules
11496 09:30:06.758992 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407642
11497 09:30:07.304932 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407642
11498 09:30:07.305112 Job finished correctly