Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 50
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 90
1 09:53:55.465289 lava-dispatcher, installed at version: 2024.03
2 09:53:55.465497 start: 0 validate
3 09:53:55.465610 Start time: 2024-06-18 09:53:55.465605+00:00 (UTC)
4 09:53:55.465732 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:53:55.465867 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 09:53:55.731250 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:53:55.731988 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:53:55.987061 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:53:55.987951 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 09:53:56.251772 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:53:56.252388 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-libcamera%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 09:53:56.758137 Using caching service: 'http://localhost/cache/?uri=%s'
13 09:53:56.758777 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 09:53:57.024855 validate duration: 1.56
16 09:53:57.025967 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 09:53:57.026532 start: 1.1 download-retry (timeout 00:10:00) [common]
18 09:53:57.027008 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 09:53:57.027741 Not decompressing ramdisk as can be used compressed.
20 09:53:57.028215 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/initrd.cpio.gz
21 09:53:57.028590 saving as /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/ramdisk/initrd.cpio.gz
22 09:53:57.028915 total size: 5628151 (5 MB)
23 09:53:57.037074 progress 0 % (0 MB)
24 09:53:57.045285 progress 5 % (0 MB)
25 09:53:57.052968 progress 10 % (0 MB)
26 09:53:57.057784 progress 15 % (0 MB)
27 09:53:57.062113 progress 20 % (1 MB)
28 09:53:57.065121 progress 25 % (1 MB)
29 09:53:57.068247 progress 30 % (1 MB)
30 09:53:57.071017 progress 35 % (1 MB)
31 09:53:57.073350 progress 40 % (2 MB)
32 09:53:57.075720 progress 45 % (2 MB)
33 09:53:57.077835 progress 50 % (2 MB)
34 09:53:57.079913 progress 55 % (2 MB)
35 09:53:57.081976 progress 60 % (3 MB)
36 09:53:57.083692 progress 65 % (3 MB)
37 09:53:57.085549 progress 70 % (3 MB)
38 09:53:57.087211 progress 75 % (4 MB)
39 09:53:57.088900 progress 80 % (4 MB)
40 09:53:57.090412 progress 85 % (4 MB)
41 09:53:57.092096 progress 90 % (4 MB)
42 09:53:57.093652 progress 95 % (5 MB)
43 09:53:57.095040 progress 100 % (5 MB)
44 09:53:57.095257 5 MB downloaded in 0.07 s (80.91 MB/s)
45 09:53:57.095417 end: 1.1.1 http-download (duration 00:00:00) [common]
47 09:53:57.095647 end: 1.1 download-retry (duration 00:00:00) [common]
48 09:53:57.095737 start: 1.2 download-retry (timeout 00:10:00) [common]
49 09:53:57.095814 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 09:53:57.095946 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 09:53:57.096007 saving as /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/kernel/Image
52 09:53:57.096062 total size: 54813184 (52 MB)
53 09:53:57.096117 No compression specified
54 09:53:57.097127 progress 0 % (0 MB)
55 09:53:57.110759 progress 5 % (2 MB)
56 09:53:57.124475 progress 10 % (5 MB)
57 09:53:57.138160 progress 15 % (7 MB)
58 09:53:57.151810 progress 20 % (10 MB)
59 09:53:57.165497 progress 25 % (13 MB)
60 09:53:57.179018 progress 30 % (15 MB)
61 09:53:57.192629 progress 35 % (18 MB)
62 09:53:57.206166 progress 40 % (20 MB)
63 09:53:57.219801 progress 45 % (23 MB)
64 09:53:57.233532 progress 50 % (26 MB)
65 09:53:57.247528 progress 55 % (28 MB)
66 09:53:57.260998 progress 60 % (31 MB)
67 09:53:57.274810 progress 65 % (34 MB)
68 09:53:57.288359 progress 70 % (36 MB)
69 09:53:57.302185 progress 75 % (39 MB)
70 09:53:57.315829 progress 80 % (41 MB)
71 09:53:57.329412 progress 85 % (44 MB)
72 09:53:57.343155 progress 90 % (47 MB)
73 09:53:57.356884 progress 95 % (49 MB)
74 09:53:57.370437 progress 100 % (52 MB)
75 09:53:57.370657 52 MB downloaded in 0.27 s (190.37 MB/s)
76 09:53:57.370808 end: 1.2.1 http-download (duration 00:00:00) [common]
78 09:53:57.371014 end: 1.2 download-retry (duration 00:00:00) [common]
79 09:53:57.371094 start: 1.3 download-retry (timeout 00:10:00) [common]
80 09:53:57.371170 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 09:53:57.371295 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 09:53:57.371360 saving as /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 09:53:57.371413 total size: 57695 (0 MB)
84 09:53:57.371466 No compression specified
85 09:53:57.372627 progress 56 % (0 MB)
86 09:53:57.372888 progress 100 % (0 MB)
87 09:53:57.373080 0 MB downloaded in 0.00 s (33.05 MB/s)
88 09:53:57.373202 end: 1.3.1 http-download (duration 00:00:00) [common]
90 09:53:57.373404 end: 1.3 download-retry (duration 00:00:00) [common]
91 09:53:57.373480 start: 1.4 download-retry (timeout 00:10:00) [common]
92 09:53:57.373554 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 09:53:57.373656 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-libcamera/20240313.0/arm64/full.rootfs.tar.xz
94 09:53:57.373715 saving as /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/nfsrootfs/full.rootfs.tar
95 09:53:57.373765 total size: 69067788 (65 MB)
96 09:53:57.373818 Using unxz to decompress xz
97 09:53:57.379073 progress 0 % (0 MB)
98 09:53:57.563219 progress 5 % (3 MB)
99 09:53:57.753835 progress 10 % (6 MB)
100 09:53:57.944570 progress 15 % (9 MB)
101 09:53:58.104937 progress 20 % (13 MB)
102 09:53:58.283490 progress 25 % (16 MB)
103 09:53:58.470334 progress 30 % (19 MB)
104 09:53:58.589682 progress 35 % (23 MB)
105 09:53:58.687023 progress 40 % (26 MB)
106 09:53:58.880630 progress 45 % (29 MB)
107 09:53:59.076050 progress 50 % (32 MB)
108 09:53:59.268993 progress 55 % (36 MB)
109 09:53:59.475288 progress 60 % (39 MB)
110 09:53:59.659050 progress 65 % (42 MB)
111 09:53:59.849732 progress 70 % (46 MB)
112 09:54:00.035809 progress 75 % (49 MB)
113 09:54:00.233029 progress 80 % (52 MB)
114 09:54:00.400485 progress 85 % (56 MB)
115 09:54:00.584441 progress 90 % (59 MB)
116 09:54:00.781823 progress 95 % (62 MB)
117 09:54:00.978563 progress 100 % (65 MB)
118 09:54:00.984488 65 MB downloaded in 3.61 s (18.24 MB/s)
119 09:54:00.984646 end: 1.4.1 http-download (duration 00:00:04) [common]
121 09:54:00.984895 end: 1.4 download-retry (duration 00:00:04) [common]
122 09:54:00.984976 start: 1.5 download-retry (timeout 00:09:56) [common]
123 09:54:00.985051 start: 1.5.1 http-download (timeout 00:09:56) [common]
124 09:54:00.985176 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 09:54:00.985236 saving as /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/modules/modules.tar
126 09:54:00.985288 total size: 8619356 (8 MB)
127 09:54:00.985342 Using unxz to decompress xz
128 09:54:00.986608 progress 0 % (0 MB)
129 09:54:01.005601 progress 5 % (0 MB)
130 09:54:01.029029 progress 10 % (0 MB)
131 09:54:01.053117 progress 15 % (1 MB)
132 09:54:01.076792 progress 20 % (1 MB)
133 09:54:01.100919 progress 25 % (2 MB)
134 09:54:01.124571 progress 30 % (2 MB)
135 09:54:01.148808 progress 35 % (2 MB)
136 09:54:01.172664 progress 40 % (3 MB)
137 09:54:01.196355 progress 45 % (3 MB)
138 09:54:01.219289 progress 50 % (4 MB)
139 09:54:01.242997 progress 55 % (4 MB)
140 09:54:01.266561 progress 60 % (4 MB)
141 09:54:01.289456 progress 65 % (5 MB)
142 09:54:01.316260 progress 70 % (5 MB)
143 09:54:01.340012 progress 75 % (6 MB)
144 09:54:01.363180 progress 80 % (6 MB)
145 09:54:01.386064 progress 85 % (7 MB)
146 09:54:01.408709 progress 90 % (7 MB)
147 09:54:01.434669 progress 95 % (7 MB)
148 09:54:01.462835 progress 100 % (8 MB)
149 09:54:01.467225 8 MB downloaded in 0.48 s (17.06 MB/s)
150 09:54:01.467391 end: 1.5.1 http-download (duration 00:00:00) [common]
152 09:54:01.467602 end: 1.5 download-retry (duration 00:00:00) [common]
153 09:54:01.467680 start: 1.6 prepare-tftp-overlay (timeout 00:09:56) [common]
154 09:54:01.467757 start: 1.6.1 extract-nfsrootfs (timeout 00:09:56) [common]
155 09:54:03.004261 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14407606/extract-nfsrootfs-d7meu2he
156 09:54:03.004429 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 09:54:03.004521 start: 1.6.2 lava-overlay (timeout 00:09:54) [common]
158 09:54:03.004674 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t
159 09:54:03.004790 makedir: /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin
160 09:54:03.004882 makedir: /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/tests
161 09:54:03.004970 makedir: /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/results
162 09:54:03.005053 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-add-keys
163 09:54:03.005177 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-add-sources
164 09:54:03.005295 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-background-process-start
165 09:54:03.005411 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-background-process-stop
166 09:54:03.005534 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-common-functions
167 09:54:03.005649 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-echo-ipv4
168 09:54:03.005763 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-install-packages
169 09:54:03.005875 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-installed-packages
170 09:54:03.005995 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-os-build
171 09:54:03.006108 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-probe-channel
172 09:54:03.006220 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-probe-ip
173 09:54:03.006334 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-target-ip
174 09:54:03.006445 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-target-mac
175 09:54:03.006589 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-target-storage
176 09:54:03.006705 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-test-case
177 09:54:03.006819 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-test-event
178 09:54:03.006931 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-test-feedback
179 09:54:03.007043 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-test-raise
180 09:54:03.007154 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-test-reference
181 09:54:03.007266 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-test-runner
182 09:54:03.007379 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-test-set
183 09:54:03.007490 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-test-shell
184 09:54:03.007605 Updating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-install-packages (oe)
185 09:54:03.007744 Updating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/bin/lava-installed-packages (oe)
186 09:54:03.007855 Creating /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/environment
187 09:54:03.007941 LAVA metadata
188 09:54:03.008006 - LAVA_JOB_ID=14407606
189 09:54:03.008062 - LAVA_DISPATCHER_IP=192.168.201.1
190 09:54:03.008153 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:54) [common]
191 09:54:03.008209 skipped lava-vland-overlay
192 09:54:03.008274 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 09:54:03.008344 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:54) [common]
194 09:54:03.008398 skipped lava-multinode-overlay
195 09:54:03.008464 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 09:54:03.008534 start: 1.6.2.3 test-definition (timeout 00:09:54) [common]
197 09:54:03.008595 Loading test definitions
198 09:54:03.008667 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:54) [common]
199 09:54:03.008725 Using /lava-14407606 at stage 0
200 09:54:03.009014 uuid=14407606_1.6.2.3.1 testdef=None
201 09:54:03.009095 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 09:54:03.009170 start: 1.6.2.3.2 test-overlay (timeout 00:09:54) [common]
203 09:54:03.009591 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 09:54:03.009790 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:54) [common]
206 09:54:03.010378 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 09:54:03.010589 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:54) [common]
209 09:54:03.011122 runner path: /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/0/tests/0_lc-compliance test_uuid 14407606_1.6.2.3.1
210 09:54:03.011268 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 09:54:03.011488 Creating lava-test-runner.conf files
213 09:54:03.011543 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407606/lava-overlay-9qay746t/lava-14407606/0 for stage 0
214 09:54:03.011623 - 0_lc-compliance
215 09:54:03.011712 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 09:54:03.011787 start: 1.6.2.4 compress-overlay (timeout 00:09:54) [common]
217 09:54:03.017344 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 09:54:03.017437 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:54) [common]
219 09:54:03.017515 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 09:54:03.017591 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 09:54:03.017668 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:54) [common]
222 09:54:03.174315 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 09:54:03.174466 start: 1.6.4 extract-modules (timeout 00:09:54) [common]
224 09:54:03.174545 extracting modules file /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407606/extract-nfsrootfs-d7meu2he
225 09:54:03.389401 extracting modules file /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407606/extract-overlay-ramdisk-yj6tut36/ramdisk
226 09:54:03.622629 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 09:54:03.622773 start: 1.6.5 apply-overlay-tftp (timeout 00:09:53) [common]
228 09:54:03.622850 [common] Applying overlay to NFS
229 09:54:03.622909 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407606/compress-overlay-kpztv_wh/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407606/extract-nfsrootfs-d7meu2he
230 09:54:03.629614 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 09:54:03.629736 start: 1.6.6 configure-preseed-file (timeout 00:09:53) [common]
232 09:54:03.629842 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 09:54:03.629946 start: 1.6.7 compress-ramdisk (timeout 00:09:53) [common]
234 09:54:03.630096 Building ramdisk /var/lib/lava/dispatcher/tmp/14407606/extract-overlay-ramdisk-yj6tut36/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407606/extract-overlay-ramdisk-yj6tut36/ramdisk
235 09:54:03.948042 >> 130466 blocks
236 09:54:06.059241 rename /var/lib/lava/dispatcher/tmp/14407606/extract-overlay-ramdisk-yj6tut36/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/ramdisk/ramdisk.cpio.gz
237 09:54:06.059413 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 09:54:06.059503 start: 1.6.8 prepare-kernel (timeout 00:09:51) [common]
239 09:54:06.059582 start: 1.6.8.1 prepare-fit (timeout 00:09:51) [common]
240 09:54:06.059659 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/kernel/Image']
241 09:54:19.234921 Returned 0 in 13 seconds
242 09:54:19.335778 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/kernel/image.itb
243 09:54:19.783600 output: FIT description: Kernel Image image with one or more FDT blobs
244 09:54:19.783739 output: Created: Tue Jun 18 10:54:19 2024
245 09:54:19.783803 output: Image 0 (kernel-1)
246 09:54:19.783857 output: Description:
247 09:54:19.783911 output: Created: Tue Jun 18 10:54:19 2024
248 09:54:19.783964 output: Type: Kernel Image
249 09:54:19.784017 output: Compression: lzma compressed
250 09:54:19.784074 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
251 09:54:19.784128 output: Architecture: AArch64
252 09:54:19.784181 output: OS: Linux
253 09:54:19.784236 output: Load Address: 0x00000000
254 09:54:19.784291 output: Entry Point: 0x00000000
255 09:54:19.784346 output: Hash algo: crc32
256 09:54:19.784404 output: Hash value: 4137a6e7
257 09:54:19.784461 output: Image 1 (fdt-1)
258 09:54:19.784514 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
259 09:54:19.784569 output: Created: Tue Jun 18 10:54:19 2024
260 09:54:19.784621 output: Type: Flat Device Tree
261 09:54:19.784672 output: Compression: uncompressed
262 09:54:19.784721 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
263 09:54:19.784771 output: Architecture: AArch64
264 09:54:19.784820 output: Hash algo: crc32
265 09:54:19.784868 output: Hash value: a9713552
266 09:54:19.784915 output: Image 2 (ramdisk-1)
267 09:54:19.784962 output: Description: unavailable
268 09:54:19.785010 output: Created: Tue Jun 18 10:54:19 2024
269 09:54:19.785057 output: Type: RAMDisk Image
270 09:54:19.785105 output: Compression: uncompressed
271 09:54:19.785152 output: Data Size: 18744998 Bytes = 18305.66 KiB = 17.88 MiB
272 09:54:19.785200 output: Architecture: AArch64
273 09:54:19.785247 output: OS: Linux
274 09:54:19.785295 output: Load Address: unavailable
275 09:54:19.785342 output: Entry Point: unavailable
276 09:54:19.785389 output: Hash algo: crc32
277 09:54:19.785435 output: Hash value: e2fe3243
278 09:54:19.785482 output: Default Configuration: 'conf-1'
279 09:54:19.785530 output: Configuration 0 (conf-1)
280 09:54:19.785577 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
281 09:54:19.785625 output: Kernel: kernel-1
282 09:54:19.785672 output: Init Ramdisk: ramdisk-1
283 09:54:19.785719 output: FDT: fdt-1
284 09:54:19.785766 output: Loadables: kernel-1
285 09:54:19.785813 output:
286 09:54:19.785948 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 09:54:19.786084 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 09:54:19.786173 end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
289 09:54:19.786260 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:37) [common]
290 09:54:19.786328 No LXC device requested
291 09:54:19.786409 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 09:54:19.786487 start: 1.8 deploy-device-env (timeout 00:09:37) [common]
293 09:54:19.786558 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 09:54:19.786619 Checking files for TFTP limit of 4294967296 bytes.
295 09:54:19.787072 end: 1 tftp-deploy (duration 00:00:23) [common]
296 09:54:19.787175 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 09:54:19.787264 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 09:54:19.787374 substitutions:
299 09:54:19.787436 - {DTB}: 14407606/tftp-deploy-js1wnew3/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
300 09:54:19.787494 - {INITRD}: 14407606/tftp-deploy-js1wnew3/ramdisk/ramdisk.cpio.gz
301 09:54:19.787547 - {KERNEL}: 14407606/tftp-deploy-js1wnew3/kernel/Image
302 09:54:19.787598 - {LAVA_MAC}: None
303 09:54:19.787649 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14407606/extract-nfsrootfs-d7meu2he
304 09:54:19.787699 - {NFS_SERVER_IP}: 192.168.201.1
305 09:54:19.787749 - {PRESEED_CONFIG}: None
306 09:54:19.787808 - {PRESEED_LOCAL}: None
307 09:54:19.787859 - {RAMDISK}: 14407606/tftp-deploy-js1wnew3/ramdisk/ramdisk.cpio.gz
308 09:54:19.787908 - {ROOT_PART}: None
309 09:54:19.787956 - {ROOT}: None
310 09:54:19.788005 - {SERVER_IP}: 192.168.201.1
311 09:54:19.788053 - {TEE}: None
312 09:54:19.788102 Parsed boot commands:
313 09:54:19.788150 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 09:54:19.788341 Parsed boot commands: tftpboot 192.168.201.1 14407606/tftp-deploy-js1wnew3/kernel/image.itb 14407606/tftp-deploy-js1wnew3/kernel/cmdline
315 09:54:19.788425 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 09:54:19.788501 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 09:54:19.788581 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 09:54:19.788666 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 09:54:19.788734 Not connected, no need to disconnect.
320 09:54:19.788801 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 09:54:19.788876 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 09:54:19.788936 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-1'
323 09:54:19.792370 Setting prompt string to ['lava-test: # ']
324 09:54:19.792691 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 09:54:19.792785 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 09:54:19.792876 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 09:54:19.792959 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 09:54:19.793133 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-1']
329 09:54:42.308299 Returned 0 in 22 seconds
330 09:54:42.409378 end: 2.2.2.1 pdu-reboot (duration 00:00:23) [common]
332 09:54:42.410809 end: 2.2.2 reset-device (duration 00:00:23) [common]
333 09:54:42.411345 start: 2.2.3 depthcharge-start (timeout 00:04:37) [common]
334 09:54:42.411848 Setting prompt string to 'Starting depthcharge on Juniper...'
335 09:54:42.412193 Changing prompt to 'Starting depthcharge on Juniper...'
336 09:54:42.412570 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
337 09:54:42.414438 [Enter `^Ec?' for help]
338 09:54:42.414867 [DL] 00000000 00000000 010701
339 09:54:42.415225
340 09:54:42.415576
341 09:54:42.415863 F0: 102B 0000
342 09:54:42.416161
343 09:54:42.416436 F3: 1006 0033 [0200]
344 09:54:42.416721
345 09:54:42.417001 F3: 4001 00E0 [0200]
346 09:54:42.417261
347 09:54:42.417513 F3: 0000 0000
348 09:54:42.417767
349 09:54:42.418171 V0: 0000 0000 [0001]
350 09:54:42.418440
351 09:54:42.418692 00: 1027 0002
352 09:54:42.418954
353 09:54:42.419207 01: 0000 0000
354 09:54:42.419477
355 09:54:42.419725 BP: 0C00 0251 [0000]
356 09:54:42.420062
357 09:54:42.420390 G0: 1182 0000
358 09:54:42.420786
359 09:54:42.421054 EC: 0004 0000 [0001]
360 09:54:42.421326
361 09:54:42.421631 S7: 0000 0000 [0000]
362 09:54:42.421890
363 09:54:42.422186 CC: 0000 0000 [0001]
364 09:54:42.422441
365 09:54:42.422686 T0: 0000 00DB [000F]
366 09:54:42.422936
367 09:54:42.423182 Jump to BL
368 09:54:42.423431
369 09:54:42.423678
370 09:54:42.423927
371 09:54:42.424173 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
372 09:54:42.424439 ARM64: Exception handlers installed.
373 09:54:42.424690 ARM64: Testing exception
374 09:54:42.424939 ARM64: Done test exception
375 09:54:42.425192 WDT: Last reset was cold boot
376 09:54:42.425442 SPI0(PAD0) initialized at 992727 Hz
377 09:54:42.425692 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
378 09:54:42.425944 Manufacturer: ef
379 09:54:42.426212 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
380 09:54:42.426461 Probing TPM: . done!
381 09:54:42.426708 TPM ready after 0 ms
382 09:54:42.426958 Connected to device vid:did:rid of 1ae0:0028:00
383 09:54:42.427211 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
384 09:54:42.427469 Initialized TPM device CR50 revision 0
385 09:54:42.427720 tlcl_send_startup: Startup return code is 0
386 09:54:42.428031 TPM: setup succeeded
387 09:54:42.428447 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
388 09:54:42.428716 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
389 09:54:42.428976 in-header: 03 19 00 00 08 00 00 00
390 09:54:42.429229 in-data: a2 e0 47 00 13 00 00 00
391 09:54:42.429481 Chrome EC: UHEPI supported
392 09:54:42.429733 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
393 09:54:42.430104 in-header: 03 a1 00 00 08 00 00 00
394 09:54:42.430500 in-data: 84 60 60 10 00 00 00 00
395 09:54:42.430764 Phase 1
396 09:54:42.431017 FMAP: area GBB found @ 3f5000 (12032 bytes)
397 09:54:42.431276 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
398 09:54:42.431533 VB2:vb2_check_recovery() Recovery was requested manually
399 09:54:42.431786 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
400 09:54:42.432171 Recovery requested (1009000e)
401 09:54:42.432557 tlcl_extend: response is 0
402 09:54:42.432828 tlcl_extend: response is 0
403 09:54:42.433087
404 09:54:42.433336
405 09:54:42.433586 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
406 09:54:42.433847 ARM64: Exception handlers installed.
407 09:54:42.434156 ARM64: Testing exception
408 09:54:42.434413 ARM64: Done test exception
409 09:54:42.434662 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0x826a, sec=0x2014
410 09:54:42.434914 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
411 09:54:42.435167 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
412 09:54:42.435422 [RTC]rtc_get_frequency_meter,134: input=0xf, output=875
413 09:54:42.435672 [RTC]rtc_get_frequency_meter,134: input=0x7, output=743
414 09:54:42.435922 [RTC]rtc_get_frequency_meter,134: input=0xb, output=810
415 09:54:42.436170 [RTC]rtc_get_frequency_meter,134: input=0x9, output=776
416 09:54:42.436424 [RTC]rtc_get_frequency_meter,134: input=0xa, output=791
417 09:54:42.436680 [RTC]rtc_get_frequency_meter,134: input=0xa, output=792
418 09:54:42.436931 [RTC]rtc_get_frequency_meter,134: input=0xb, output=808
419 09:54:42.437179 [RTC]rtc_osc_init,208: EOSC32 cali val = 0x826a
420 09:54:42.437431 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
421 09:54:42.437682 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
422 09:54:42.437930 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
423 09:54:42.438224 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
424 09:54:42.438482 in-header: 03 19 00 00 08 00 00 00
425 09:54:42.438733 in-data: a2 e0 47 00 13 00 00 00
426 09:54:42.438984 Chrome EC: UHEPI supported
427 09:54:42.439233 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
428 09:54:42.439487 in-header: 03 a1 00 00 08 00 00 00
429 09:54:42.439735 in-data: 84 60 60 10 00 00 00 00
430 09:54:42.439981 Skip loading cached calibration data
431 09:54:42.440269 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
432 09:54:42.440538 in-header: 03 a1 00 00 08 00 00 00
433 09:54:42.440785 in-data: 84 60 60 10 00 00 00 00
434 09:54:42.441045 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
435 09:54:42.441301 in-header: 03 a1 00 00 08 00 00 00
436 09:54:42.441550 in-data: 84 60 60 10 00 00 00 00
437 09:54:42.441796 ADC[3]: Raw value=216425 ID=1
438 09:54:42.442059 Manufacturer: ef
439 09:54:42.442310 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
440 09:54:42.442539 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
441 09:54:42.442720 CBFS @ 21000 size 3d4000
442 09:54:42.442898 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
443 09:54:42.443076 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
444 09:54:42.443253 CBFS: Found @ offset 3c700 size 44
445 09:54:42.443430 DRAM-K: Full Calibration
446 09:54:42.443604 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
447 09:54:42.443781 CBFS @ 21000 size 3d4000
448 09:54:42.443956 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
449 09:54:42.444133 CBFS: Locating 'fallback/dram'
450 09:54:42.444305 CBFS: Found @ offset 24b00 size 12268
451 09:54:42.444480 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
452 09:54:42.444657 ddr_geometry: 1, config: 0x0
453 09:54:42.444833 header.status = 0x0
454 09:54:42.445010 header.magic = 0x44524d4b (expected: 0x44524d4b)
455 09:54:42.445185 header.version = 0x5 (expected: 0x5)
456 09:54:42.445651 header.size = 0x8f0 (expected: 0x8f0)
457 09:54:42.445868 header.config = 0x0
458 09:54:42.446075 header.flags = 0x0
459 09:54:42.446261 header.checksum = 0x0
460 09:54:42.446441 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
461 09:54:42.446624 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
462 09:54:42.446803 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
463 09:54:42.446984 ddr_geometry:1
464 09:54:42.447161 [EMI] new MDL number = 1
465 09:54:42.447349 dram_cbt_mode_extern: 0
466 09:54:42.447511 dram_cbt_mode [RK0]: 0, [RK1]: 0
467 09:54:42.447647 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
468 09:54:42.447784
469 09:54:42.447918
470 09:54:42.448052 [Bianco] ETT version 0.0.0.1
471 09:54:42.448186 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
472 09:54:42.448320
473 09:54:42.448456 vSetVcoreByFreq with vcore:762500, freq=1600
474 09:54:42.448590
475 09:54:42.448724 [DramcInit]
476 09:54:42.448857 AutoRefreshCKEOff AutoREF OFF
477 09:54:42.448991 DDRPhyPLLSetting-CKEOFF
478 09:54:42.449124 DDRPhyPLLSetting-CKEON
479 09:54:42.449256
480 09:54:42.449387 Enable WDQS
481 09:54:42.449517 [ModeRegInit_LP4] CH0 RK0
482 09:54:42.449648 Write Rank0 MR13 =0x18
483 09:54:42.449779 Write Rank0 MR12 =0x5d
484 09:54:42.449910 Write Rank0 MR1 =0x56
485 09:54:42.450067 Write Rank0 MR2 =0x1a
486 09:54:42.450202 Write Rank0 MR11 =0x0
487 09:54:42.450334 Write Rank0 MR22 =0x38
488 09:54:42.450465 Write Rank0 MR14 =0x5d
489 09:54:42.450596 Write Rank0 MR3 =0x30
490 09:54:42.450728 Write Rank0 MR13 =0x58
491 09:54:42.450858 Write Rank0 MR12 =0x5d
492 09:54:42.450989 Write Rank0 MR1 =0x56
493 09:54:42.451118 Write Rank0 MR2 =0x2d
494 09:54:42.451249 Write Rank0 MR11 =0x23
495 09:54:42.451380 Write Rank0 MR22 =0x34
496 09:54:42.451512 Write Rank0 MR14 =0x10
497 09:54:42.451644 Write Rank0 MR3 =0x30
498 09:54:42.451775 Write Rank0 MR13 =0xd8
499 09:54:42.451905 [ModeRegInit_LP4] CH0 RK1
500 09:54:42.452037 Write Rank1 MR13 =0x18
501 09:54:42.452171 Write Rank1 MR12 =0x5d
502 09:54:42.452303 Write Rank1 MR1 =0x56
503 09:54:42.452445 Write Rank1 MR2 =0x1a
504 09:54:42.452552 Write Rank1 MR11 =0x0
505 09:54:42.452661 Write Rank1 MR22 =0x38
506 09:54:42.452767 Write Rank1 MR14 =0x5d
507 09:54:42.452874 Write Rank1 MR3 =0x30
508 09:54:42.452980 Write Rank1 MR13 =0x58
509 09:54:42.453086 Write Rank1 MR12 =0x5d
510 09:54:42.453193 Write Rank1 MR1 =0x56
511 09:54:42.453304 Write Rank1 MR2 =0x2d
512 09:54:42.453409 Write Rank1 MR11 =0x23
513 09:54:42.453516 Write Rank1 MR22 =0x34
514 09:54:42.453621 Write Rank1 MR14 =0x10
515 09:54:42.453729 Write Rank1 MR3 =0x30
516 09:54:42.453835 Write Rank1 MR13 =0xd8
517 09:54:42.453940 [ModeRegInit_LP4] CH1 RK0
518 09:54:42.454055 Write Rank0 MR13 =0x18
519 09:54:42.454161 Write Rank0 MR12 =0x5d
520 09:54:42.454269 Write Rank0 MR1 =0x56
521 09:54:42.454373 Write Rank0 MR2 =0x1a
522 09:54:42.454478 Write Rank0 MR11 =0x0
523 09:54:42.454584 Write Rank0 MR22 =0x38
524 09:54:42.454692 Write Rank0 MR14 =0x5d
525 09:54:42.454798 Write Rank0 MR3 =0x30
526 09:54:42.454903 Write Rank0 MR13 =0x58
527 09:54:42.455009 Write Rank0 MR12 =0x5d
528 09:54:42.455116 Write Rank0 MR1 =0x56
529 09:54:42.455222 Write Rank0 MR2 =0x2d
530 09:54:42.455327 Write Rank0 MR11 =0x23
531 09:54:42.455433 Write Rank0 MR22 =0x34
532 09:54:42.455538 Write Rank0 MR14 =0x10
533 09:54:42.455643 Write Rank0 MR3 =0x30
534 09:54:42.455748 Write Rank0 MR13 =0xd8
535 09:54:42.455854 [ModeRegInit_LP4] CH1 RK1
536 09:54:42.455960 Write Rank1 MR13 =0x18
537 09:54:42.456065 Write Rank1 MR12 =0x5d
538 09:54:42.456172 Write Rank1 MR1 =0x56
539 09:54:42.456277 Write Rank1 MR2 =0x1a
540 09:54:42.456383 Write Rank1 MR11 =0x0
541 09:54:42.456488 Write Rank1 MR22 =0x38
542 09:54:42.456592 Write Rank1 MR14 =0x5d
543 09:54:42.456699 Write Rank1 MR3 =0x30
544 09:54:42.456805 Write Rank1 MR13 =0x58
545 09:54:42.456910 Write Rank1 MR12 =0x5d
546 09:54:42.457016 Write Rank1 MR1 =0x56
547 09:54:42.457121 Write Rank1 MR2 =0x2d
548 09:54:42.457227 Write Rank1 MR11 =0x23
549 09:54:42.457333 Write Rank1 MR22 =0x34
550 09:54:42.457443 Write Rank1 MR14 =0x10
551 09:54:42.457531 Write Rank1 MR3 =0x30
552 09:54:42.457618 Write Rank1 MR13 =0xd8
553 09:54:42.457706 match AC timing 3
554 09:54:42.457794 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
555 09:54:42.457886 [MiockJmeterHQA]
556 09:54:42.457974 vSetVcoreByFreq with vcore:762500, freq=1600
557 09:54:42.458072
558 09:54:42.458161 MIOCK jitter meter ch=0
559 09:54:42.458251
560 09:54:42.458338 1T = (89-15) = 74 dly cells
561 09:54:42.458430 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 844/100 ps
562 09:54:42.458521 vSetVcoreByFreq with vcore:725000, freq=1200
563 09:54:42.458611
564 09:54:42.458700 MIOCK jitter meter ch=0
565 09:54:42.458788
566 09:54:42.458876 1T = (84-14) = 70 dly cells
567 09:54:42.458968 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 892/100 ps
568 09:54:42.459058 vSetVcoreByFreq with vcore:725000, freq=800
569 09:54:42.459146
570 09:54:42.459233 MIOCK jitter meter ch=0
571 09:54:42.459323
572 09:54:42.459411 1T = (84-14) = 70 dly cells
573 09:54:42.459503 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 892/100 ps
574 09:54:42.459594 vSetVcoreByFreq with vcore:762500, freq=1600
575 09:54:42.459683 vSetVcoreByFreq with vcore:762500, freq=1600
576 09:54:42.459771
577 09:54:42.459859 K DRVP
578 09:54:42.459947 1. OCD DRVP=0 CALOUT=0
579 09:54:42.460038 1. OCD DRVP=1 CALOUT=0
580 09:54:42.460129 1. OCD DRVP=2 CALOUT=0
581 09:54:42.460222 1. OCD DRVP=3 CALOUT=0
582 09:54:42.460312 1. OCD DRVP=4 CALOUT=0
583 09:54:42.460402 1. OCD DRVP=5 CALOUT=0
584 09:54:42.460492 1. OCD DRVP=6 CALOUT=0
585 09:54:42.460584 1. OCD DRVP=7 CALOUT=0
586 09:54:42.460675 1. OCD DRVP=8 CALOUT=0
587 09:54:42.460765 1. OCD DRVP=9 CALOUT=1
588 09:54:42.460856
589 09:54:42.460946 1. OCD DRVP calibration OK! DRVP=9
590 09:54:42.461037
591 09:54:42.461126
592 09:54:42.461214
593 09:54:42.461302 K ODTN
594 09:54:42.461391 3. OCD ODTN=0 ,CALOUT=1
595 09:54:42.461488 3. OCD ODTN=1 ,CALOUT=1
596 09:54:42.461579 3. OCD ODTN=2 ,CALOUT=1
597 09:54:42.461671 3. OCD ODTN=3 ,CALOUT=1
598 09:54:42.461762 3. OCD ODTN=4 ,CALOUT=1
599 09:54:42.461854 3. OCD ODTN=5 ,CALOUT=1
600 09:54:42.461945 3. OCD ODTN=6 ,CALOUT=1
601 09:54:42.462049 3. OCD ODTN=7 ,CALOUT=1
602 09:54:42.462141 3. OCD ODTN=8 ,CALOUT=0
603 09:54:42.462233
604 09:54:42.462322 3. OCD ODTN calibration OK! ODTN=8
605 09:54:42.462422
606 09:54:42.462499 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=8
607 09:54:42.462577 term_option=0, Reg: DRVP=9, DRVN=8, ODTN=15
608 09:54:42.462655 term_option=0, Reg: DRVP=9, DRVN=8, ODTN=15 (After Adjust)
609 09:54:42.462732
610 09:54:42.462809 K DRVP
611 09:54:42.462885 1. OCD DRVP=0 CALOUT=0
612 09:54:42.462964 1. OCD DRVP=1 CALOUT=0
613 09:54:42.463043 1. OCD DRVP=2 CALOUT=0
614 09:54:42.463121 1. OCD DRVP=3 CALOUT=0
615 09:54:42.463200 1. OCD DRVP=4 CALOUT=0
616 09:54:42.463278 1. OCD DRVP=5 CALOUT=0
617 09:54:42.463355 1. OCD DRVP=6 CALOUT=0
618 09:54:42.463432 1. OCD DRVP=7 CALOUT=0
619 09:54:42.463510 1. OCD DRVP=8 CALOUT=0
620 09:54:42.463794 1. OCD DRVP=9 CALOUT=0
621 09:54:42.463888 1. OCD DRVP=10 CALOUT=1
622 09:54:42.463970
623 09:54:42.464047 1. OCD DRVP calibration OK! DRVP=10
624 09:54:42.464127
625 09:54:42.464204
626 09:54:42.464281
627 09:54:42.464358 K ODTN
628 09:54:42.464434 3. OCD ODTN=0 ,CALOUT=1
629 09:54:42.464513 3. OCD ODTN=1 ,CALOUT=1
630 09:54:42.464591 3. OCD ODTN=2 ,CALOUT=1
631 09:54:42.464668 3. OCD ODTN=3 ,CALOUT=1
632 09:54:42.464745 3. OCD ODTN=4 ,CALOUT=1
633 09:54:42.464824 3. OCD ODTN=5 ,CALOUT=1
634 09:54:42.464904 3. OCD ODTN=6 ,CALOUT=1
635 09:54:42.464982 3. OCD ODTN=7 ,CALOUT=1
636 09:54:42.465060 3. OCD ODTN=8 ,CALOUT=1
637 09:54:42.465138 3. OCD ODTN=9 ,CALOUT=1
638 09:54:42.465216 3. OCD ODTN=10 ,CALOUT=1
639 09:54:42.465294 3. OCD ODTN=11 ,CALOUT=1
640 09:54:42.465372 3. OCD ODTN=12 ,CALOUT=1
641 09:54:42.465452 3. OCD ODTN=13 ,CALOUT=1
642 09:54:42.465530 3. OCD ODTN=14 ,CALOUT=1
643 09:54:42.465608 3. OCD ODTN=15 ,CALOUT=0
644 09:54:42.465685
645 09:54:42.465761 3. OCD ODTN calibration OK! ODTN=15
646 09:54:42.465839
647 09:54:42.465915 [SwImpedanceCal] DRVP=10, DRVN=9, ODTN=15
648 09:54:42.466001 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15
649 09:54:42.466081 term_option=1, Reg: DRVP=10, DRVN=9, ODTN=15 (After Adjust)
650 09:54:42.466159
651 09:54:42.466234 [DramcInit]
652 09:54:42.466310 AutoRefreshCKEOff AutoREF OFF
653 09:54:42.466386 DDRPhyPLLSetting-CKEOFF
654 09:54:42.466461 DDRPhyPLLSetting-CKEON
655 09:54:42.466536
656 09:54:42.466612 Enable WDQS
657 09:54:42.466688 ==
658 09:54:42.466768 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
659 09:54:42.466846 fsp= 1, odt_onoff= 1, Byte mode= 0
660 09:54:42.466924 ==
661 09:54:42.467000 [Duty_Offset_Calibration]
662 09:54:42.467076
663 09:54:42.467152 ===========================
664 09:54:42.467227 B0:0 B1:0 CA:2
665 09:54:42.467302 ==
666 09:54:42.467379 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
667 09:54:42.467460 fsp= 1, odt_onoff= 1, Byte mode= 0
668 09:54:42.467526 ==
669 09:54:42.467593 [Duty_Offset_Calibration]
670 09:54:42.467660
671 09:54:42.467726 ===========================
672 09:54:42.467793 B0:0 B1:1 CA:1
673 09:54:42.467860 [ModeRegInit_LP4] CH0 RK0
674 09:54:42.467926 Write Rank0 MR13 =0x18
675 09:54:42.467993 Write Rank0 MR12 =0x5d
676 09:54:42.468059 Write Rank0 MR1 =0x56
677 09:54:42.468126 Write Rank0 MR2 =0x1a
678 09:54:42.468193 Write Rank0 MR11 =0x0
679 09:54:42.468260 Write Rank0 MR22 =0x38
680 09:54:42.468325 Write Rank0 MR14 =0x5d
681 09:54:42.468391 Write Rank0 MR3 =0x30
682 09:54:42.468458 Write Rank0 MR13 =0x58
683 09:54:42.468524 Write Rank0 MR12 =0x5d
684 09:54:42.468591 Write Rank0 MR1 =0x56
685 09:54:42.468657 Write Rank0 MR2 =0x2d
686 09:54:42.468724 Write Rank0 MR11 =0x23
687 09:54:42.468791 Write Rank0 MR22 =0x34
688 09:54:42.468858 Write Rank0 MR14 =0x10
689 09:54:42.468924 Write Rank0 MR3 =0x30
690 09:54:42.468991 Write Rank0 MR13 =0xd8
691 09:54:42.469058 [ModeRegInit_LP4] CH0 RK1
692 09:54:42.469125 Write Rank1 MR13 =0x18
693 09:54:42.469191 Write Rank1 MR12 =0x5d
694 09:54:42.469256 Write Rank1 MR1 =0x56
695 09:54:42.469322 Write Rank1 MR2 =0x1a
696 09:54:42.469389 Write Rank1 MR11 =0x0
697 09:54:42.469455 Write Rank1 MR22 =0x38
698 09:54:42.469522 Write Rank1 MR14 =0x5d
699 09:54:42.469588 Write Rank1 MR3 =0x30
700 09:54:42.469654 Write Rank1 MR13 =0x58
701 09:54:42.469721 Write Rank1 MR12 =0x5d
702 09:54:42.469788 Write Rank1 MR1 =0x56
703 09:54:42.469853 Write Rank1 MR2 =0x2d
704 09:54:42.469919 Write Rank1 MR11 =0x23
705 09:54:42.469994 Write Rank1 MR22 =0x34
706 09:54:42.470063 Write Rank1 MR14 =0x10
707 09:54:42.470130 Write Rank1 MR3 =0x30
708 09:54:42.470196 Write Rank1 MR13 =0xd8
709 09:54:42.470263 [ModeRegInit_LP4] CH1 RK0
710 09:54:42.470330 Write Rank0 MR13 =0x18
711 09:54:42.470397 Write Rank0 MR12 =0x5d
712 09:54:42.470464 Write Rank0 MR1 =0x56
713 09:54:42.470530 Write Rank0 MR2 =0x1a
714 09:54:42.470596 Write Rank0 MR11 =0x0
715 09:54:42.470662 Write Rank0 MR22 =0x38
716 09:54:42.470728 Write Rank0 MR14 =0x5d
717 09:54:42.470794 Write Rank0 MR3 =0x30
718 09:54:42.470861 Write Rank0 MR13 =0x58
719 09:54:42.470928 Write Rank0 MR12 =0x5d
720 09:54:42.470995 Write Rank0 MR1 =0x56
721 09:54:42.471061 Write Rank0 MR2 =0x2d
722 09:54:42.471128 Write Rank0 MR11 =0x23
723 09:54:42.471194 Write Rank0 MR22 =0x34
724 09:54:42.471260 Write Rank0 MR14 =0x10
725 09:54:42.471327 Write Rank0 MR3 =0x30
726 09:54:42.471394 Write Rank0 MR13 =0xd8
727 09:54:42.471461 [ModeRegInit_LP4] CH1 RK1
728 09:54:42.471527 Write Rank1 MR13 =0x18
729 09:54:42.471594 Write Rank1 MR12 =0x5d
730 09:54:42.471660 Write Rank1 MR1 =0x56
731 09:54:42.471726 Write Rank1 MR2 =0x1a
732 09:54:42.471793 Write Rank1 MR11 =0x0
733 09:54:42.471859 Write Rank1 MR22 =0x38
734 09:54:42.471924 Write Rank1 MR14 =0x5d
735 09:54:42.471990 Write Rank1 MR3 =0x30
736 09:54:42.472056 Write Rank1 MR13 =0x58
737 09:54:42.472122 Write Rank1 MR12 =0x5d
738 09:54:42.472189 Write Rank1 MR1 =0x56
739 09:54:42.472255 Write Rank1 MR2 =0x2d
740 09:54:42.472321 Write Rank1 MR11 =0x23
741 09:54:42.472397 Write Rank1 MR22 =0x34
742 09:54:42.472456 Write Rank1 MR14 =0x10
743 09:54:42.472515 Write Rank1 MR3 =0x30
744 09:54:42.472573 Write Rank1 MR13 =0xd8
745 09:54:42.472631 match AC timing 3
746 09:54:42.472689 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
747 09:54:42.472750 DramC Write-DBI off
748 09:54:42.472810 DramC Read-DBI off
749 09:54:42.472869 Write Rank0 MR13 =0x59
750 09:54:42.472928 ==
751 09:54:42.472988 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
752 09:54:42.473049 fsp= 1, odt_onoff= 1, Byte mode= 0
753 09:54:42.473109 ==
754 09:54:42.473169 === u2Vref_new: 0x56 --> 0x2d
755 09:54:42.473228 === u2Vref_new: 0x58 --> 0x38
756 09:54:42.473287 === u2Vref_new: 0x5a --> 0x39
757 09:54:42.473348 === u2Vref_new: 0x5c --> 0x3c
758 09:54:42.473408 === u2Vref_new: 0x5e --> 0x3d
759 09:54:42.473467 === u2Vref_new: 0x60 --> 0xa0
760 09:54:42.473527 [CA 0] Center 35 (8~63) winsize 56
761 09:54:42.473586 [CA 1] Center 36 (10~63) winsize 54
762 09:54:42.473645 [CA 2] Center 31 (2~60) winsize 59
763 09:54:42.473704 [CA 3] Center 26 (-2~55) winsize 58
764 09:54:42.473764 [CA 4] Center 27 (-1~55) winsize 57
765 09:54:42.473824 [CA 5] Center 32 (2~62) winsize 61
766 09:54:42.473883
767 09:54:42.473943 [CATrainingPosCal] consider 1 rank data
768 09:54:42.474008 u2DelayCellTimex100 = 844/100 ps
769 09:54:42.474069 CA0 delay=35 (8~63),Diff = 9 PI (10 cell)
770 09:54:42.474128 CA1 delay=36 (10~63),Diff = 10 PI (11 cell)
771 09:54:42.474188 CA2 delay=31 (2~60),Diff = 5 PI (5 cell)
772 09:54:42.474248 CA3 delay=26 (-2~55),Diff = 0 PI (0 cell)
773 09:54:42.474308 CA4 delay=27 (-1~55),Diff = 1 PI (1 cell)
774 09:54:42.474367 CA5 delay=32 (2~62),Diff = 6 PI (6 cell)
775 09:54:42.474427
776 09:54:42.474487 CA PerBit enable=1, Macro0, CA PI delay=26
777 09:54:42.474548 === u2Vref_new: 0x5e --> 0x3d
778 09:54:42.474609
779 09:54:42.474667 Vref(ca) range 1: 30
780 09:54:42.474725
781 09:54:42.474784 CS Dly= 10 (41-0-32)
782 09:54:42.474843 Write Rank0 MR13 =0xd8
783 09:54:42.474903 Write Rank0 MR13 =0xd8
784 09:54:42.474963 Write Rank0 MR12 =0x5e
785 09:54:42.475237 Write Rank1 MR13 =0x59
786 09:54:42.475308 ==
787 09:54:42.475369 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
788 09:54:42.475429 fsp= 1, odt_onoff= 1, Byte mode= 0
789 09:54:42.475490 ==
790 09:54:42.475551 === u2Vref_new: 0x56 --> 0x2d
791 09:54:42.475612 === u2Vref_new: 0x58 --> 0x38
792 09:54:42.475672 === u2Vref_new: 0x5a --> 0x39
793 09:54:42.475733 === u2Vref_new: 0x5c --> 0x3c
794 09:54:42.475793 === u2Vref_new: 0x5e --> 0x3d
795 09:54:42.475854 === u2Vref_new: 0x60 --> 0xa0
796 09:54:42.475914 [CA 0] Center 36 (10~63) winsize 54
797 09:54:42.475973 [CA 1] Center 37 (11~63) winsize 53
798 09:54:42.476033 [CA 2] Center 32 (3~61) winsize 59
799 09:54:42.476092 [CA 3] Center 26 (-2~55) winsize 58
800 09:54:42.476151 [CA 4] Center 26 (-2~54) winsize 57
801 09:54:42.476211 [CA 5] Center 31 (2~61) winsize 60
802 09:54:42.476270
803 09:54:42.476329 [CATrainingPosCal] consider 2 rank data
804 09:54:42.476389 u2DelayCellTimex100 = 844/100 ps
805 09:54:42.476448 CA0 delay=36 (10~63),Diff = 10 PI (11 cell)
806 09:54:42.476507 CA1 delay=37 (11~63),Diff = 11 PI (12 cell)
807 09:54:42.476567 CA2 delay=31 (3~60),Diff = 5 PI (5 cell)
808 09:54:42.476627 CA3 delay=26 (-2~55),Diff = 0 PI (0 cell)
809 09:54:42.476688 CA4 delay=26 (-1~54),Diff = 0 PI (0 cell)
810 09:54:42.476748 CA5 delay=31 (2~61),Diff = 5 PI (5 cell)
811 09:54:42.476807
812 09:54:42.476866 CA PerBit enable=1, Macro0, CA PI delay=26
813 09:54:42.476927 === u2Vref_new: 0x5c --> 0x3c
814 09:54:42.476986
815 09:54:42.477044 Vref(ca) range 1: 28
816 09:54:42.477104
817 09:54:42.477163 CS Dly= 7 (38-0-32)
818 09:54:42.477223 Write Rank1 MR13 =0xd8
819 09:54:42.477281 Write Rank1 MR13 =0xd8
820 09:54:42.477340 Write Rank1 MR12 =0x5c
821 09:54:42.477399 [RankSwap] Rank num 2, (Multi 1), Rank 0
822 09:54:42.477466 Write Rank0 MR2 =0xad
823 09:54:42.477520 [Write Leveling]
824 09:54:42.477573 delay byte0 byte1 byte2 byte3
825 09:54:42.477626
826 09:54:42.477679 10 0 0
827 09:54:42.477734 11 0 0
828 09:54:42.477789 12 0 0
829 09:54:42.477843 13 0 0
830 09:54:42.477897 14 0 0
831 09:54:42.477951 15 0 0
832 09:54:42.478012 16 0 0
833 09:54:42.478067 17 0 0
834 09:54:42.478121 18 0 0
835 09:54:42.478174 19 0 0
836 09:54:42.478228 20 0 0
837 09:54:42.478282 21 0 0
838 09:54:42.478336 22 0 0
839 09:54:42.478390 23 0 ff
840 09:54:42.478444 24 0 ff
841 09:54:42.478498 25 0 ff
842 09:54:42.478552 26 0 ff
843 09:54:42.478607 27 0 ff
844 09:54:42.478660 28 0 ff
845 09:54:42.478715 29 0 ff
846 09:54:42.478769 30 0 ff
847 09:54:42.478822 31 0 ff
848 09:54:42.478876 32 0 ff
849 09:54:42.478930 33 ff ff
850 09:54:42.478984 34 ff ff
851 09:54:42.479040 35 ff ff
852 09:54:42.479094 36 ff ff
853 09:54:42.479148 37 ff ff
854 09:54:42.479203 38 ff ff
855 09:54:42.479257 39 ff ff
856 09:54:42.479311 pass bytecount = 0xff (0xff: all bytes pass)
857 09:54:42.479365
858 09:54:42.479418 DQS0 dly: 33
859 09:54:42.479471 DQS1 dly: 23
860 09:54:42.479525 Write Rank0 MR2 =0x2d
861 09:54:42.479578 [RankSwap] Rank num 2, (Multi 1), Rank 0
862 09:54:42.479632 Write Rank0 MR1 =0xd6
863 09:54:42.479685 [Gating]
864 09:54:42.479737 ==
865 09:54:42.479793 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
866 09:54:42.479848 fsp= 1, odt_onoff= 1, Byte mode= 0
867 09:54:42.479903 ==
868 09:54:42.479957 3 1 0 |3534 3635 |(11 11)(11 11) |(0 0)(1 1)| 0
869 09:54:42.480012 3 1 4 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
870 09:54:42.480068 3 1 8 |3534 2322 |(11 11)(11 11) |(1 1)(0 0)| 0
871 09:54:42.480123 3 1 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
872 09:54:42.480177 3 1 16 |3534 3636 |(11 11)(0 0) |(1 1)(1 1)| 0
873 09:54:42.480232 3 1 20 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
874 09:54:42.480287 [Byte 1] Lead/lag Transition tap number (1)
875 09:54:42.480341 3 1 24 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
876 09:54:42.480395 3 1 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
877 09:54:42.480450 3 2 0 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
878 09:54:42.480504 3 2 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
879 09:54:42.480559 3 2 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
880 09:54:42.480614 3 2 12 |504 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
881 09:54:42.480669 3 2 16 |201 807 |(11 11)(11 11) |(1 1)(1 1)| 0
882 09:54:42.480724 3 2 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
883 09:54:42.480778 3 2 24 |3d3d 3939 |(11 11)(11 11) |(1 1)(1 1)| 0
884 09:54:42.480832 3 2 28 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
885 09:54:42.480887 3 3 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
886 09:54:42.480941 [Byte 1] Lead/lag Transition tap number (1)
887 09:54:42.480995 3 3 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(0 0)| 0
888 09:54:42.481049 3 3 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
889 09:54:42.481103 3 3 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
890 09:54:42.481157 3 3 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
891 09:54:42.481212 3 3 20 |2c2b 3c3b |(11 11)(11 11) |(1 1)(1 1)| 0
892 09:54:42.481266 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
893 09:54:42.481321 [Byte 0] Lead/lag Transition tap number (1)
894 09:54:42.481374 [Byte 1] Lead/lag Transition tap number (1)
895 09:54:42.481428 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
896 09:54:42.481482 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
897 09:54:42.481537 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
898 09:54:42.481592 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
899 09:54:42.481647 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
900 09:54:42.481701 3 4 16 |707 201 |(11 11)(11 11) |(1 1)(1 1)| 0
901 09:54:42.481756 3 4 20 |3d3d 1616 |(11 11)(11 11) |(1 1)(1 1)| 0
902 09:54:42.481810 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
903 09:54:42.481865 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
904 09:54:42.481920 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
905 09:54:42.481973 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
906 09:54:42.482032 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
907 09:54:42.482087 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
908 09:54:42.482142 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
909 09:54:42.482196 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
910 09:54:42.482441 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
911 09:54:42.482499 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
912 09:54:42.482551 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
913 09:54:42.482601 [Byte 0] Lead/lag falling Transition (3, 6, 0)
914 09:54:42.482651 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
915 09:54:42.482701 [Byte 1] Lead/lag falling Transition (3, 6, 4)
916 09:54:42.482750 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
917 09:54:42.482800 [Byte 0] Lead/lag Transition tap number (3)
918 09:54:42.482849 3 6 12 |2525 3e3d |(11 11)(11 11) |(0 0)(1 0)| 0
919 09:54:42.482899 [Byte 1] Lead/lag Transition tap number (3)
920 09:54:42.482948 3 6 16 |202 202 |(11 11)(11 11) |(0 0)(0 0)| 0
921 09:54:42.482998 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
922 09:54:42.483048 [Byte 0]First pass (3, 6, 20)
923 09:54:42.483097 [Byte 1]First pass (3, 6, 20)
924 09:54:42.483145 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
925 09:54:42.483194 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
926 09:54:42.483244 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
927 09:54:42.483294 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
928 09:54:42.483344 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
929 09:54:42.483394 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
930 09:54:42.483444 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
931 09:54:42.483492 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
932 09:54:42.483541 All bytes gating window > 1UI, Early break!
933 09:54:42.483590
934 09:54:42.483640 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
935 09:54:42.483690
936 09:54:42.483739 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 10)
937 09:54:42.483787
938 09:54:42.483836
939 09:54:42.483884
940 09:54:42.483932 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
941 09:54:42.483981
942 09:54:42.484030 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
943 09:54:42.484080
944 09:54:42.484129
945 09:54:42.484177 Write Rank0 MR1 =0x56
946 09:54:42.484226
947 09:54:42.484274 best RODT dly(2T, 0.5T) = (2, 3)
948 09:54:42.484323
949 09:54:42.484372 best RODT dly(2T, 0.5T) = (2, 3)
950 09:54:42.484421 ==
951 09:54:42.484469 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
952 09:54:42.484519 fsp= 1, odt_onoff= 1, Byte mode= 0
953 09:54:42.484568 ==
954 09:54:42.484617 Start DQ dly to find pass range UseTestEngine =0
955 09:54:42.484666 x-axis: bit #, y-axis: DQ dly (-127~63)
956 09:54:42.484715 RX Vref Scan = 0
957 09:54:42.484764 -26, [0] xxxxxxxx xxxxxxxx [MSB]
958 09:54:42.484815 -25, [0] xxxxxxxx xxxxxxxx [MSB]
959 09:54:42.484865 -24, [0] xxxxxxxx xxxxxxxx [MSB]
960 09:54:42.484915 -23, [0] xxxxxxxx xxxxxxxx [MSB]
961 09:54:42.484965 -22, [0] xxxxxxxx xxxxxxxx [MSB]
962 09:54:42.485015 -21, [0] xxxxxxxx xxxxxxxx [MSB]
963 09:54:42.485065 -20, [0] xxxxxxxx xxxxxxxx [MSB]
964 09:54:42.485115 -19, [0] xxxxxxxx xxxxxxxx [MSB]
965 09:54:42.485165 -18, [0] xxxxxxxx xxxxxxxx [MSB]
966 09:54:42.485215 -17, [0] xxxxxxxx xxxxxxxx [MSB]
967 09:54:42.485264 -16, [0] xxxxxxxx xxxxxxxx [MSB]
968 09:54:42.485314 -15, [0] xxxxxxxx xxxxxxxx [MSB]
969 09:54:42.485364 -14, [0] xxxxxxxx xxxxxxxx [MSB]
970 09:54:42.485413 -13, [0] xxxxxxxx xxxxxxxx [MSB]
971 09:54:42.485463 -12, [0] xxxxxxxx xxxxxxxx [MSB]
972 09:54:42.485512 -11, [0] xxxxxxxx xxxxxxxx [MSB]
973 09:54:42.485562 -10, [0] xxxxxxxx xxxxxxxx [MSB]
974 09:54:42.485611 -9, [0] xxxxxxxx xxxxxxxx [MSB]
975 09:54:42.485661 -8, [0] xxxxxxxx xxxxxxxx [MSB]
976 09:54:42.485712 -7, [0] xxxxxxxx xxxxxxxx [MSB]
977 09:54:42.485763 -6, [0] xxxxxxxx xxxxxxxx [MSB]
978 09:54:42.485812 -5, [0] xxxxxxxx xxxxxxxx [MSB]
979 09:54:42.485861 -4, [0] xxxxxxxx xxxxxxxx [MSB]
980 09:54:42.485911 -3, [0] xxxxxxxx xxxxxxxx [MSB]
981 09:54:42.485960 -2, [0] xxxxxxxx xxxxxxxx [MSB]
982 09:54:42.486016 -1, [0] xxxxxxxx xxxxxxxx [MSB]
983 09:54:42.486067 0, [0] xxxxxxxx xxxxxxxx [MSB]
984 09:54:42.486117 1, [0] xxxxxxxx xxxxxxxx [MSB]
985 09:54:42.486167 2, [0] xxxoxxxx oxxxxxxx [MSB]
986 09:54:42.486216 3, [0] xxxoxoxx oxxoxxxx [MSB]
987 09:54:42.486266 4, [0] xxxoxoxx ooxoxxxx [MSB]
988 09:54:42.486315 5, [0] xxxoxoxx ooxoxoox [MSB]
989 09:54:42.486364 6, [0] xxxoxooo ooxoooox [MSB]
990 09:54:42.486413 7, [0] xoxoxooo ooxoooox [MSB]
991 09:54:42.486464 8, [0] ooxoxooo ooxooooo [MSB]
992 09:54:42.486513 9, [0] ooxooooo ooxooooo [MSB]
993 09:54:42.486562 10, [0] oooooooo ooxooooo [MSB]
994 09:54:42.486612 31, [0] oooooooo oooooooo [MSB]
995 09:54:42.486662 32, [0] oooxoooo oooooooo [MSB]
996 09:54:42.486712 33, [0] oooxoooo xooooooo [MSB]
997 09:54:42.486761 34, [0] oooxoooo xooooooo [MSB]
998 09:54:42.486811 35, [0] oooxoxoo xooxoooo [MSB]
999 09:54:42.486860 36, [0] oooxoxxo xxoxxooo [MSB]
1000 09:54:42.486910 37, [0] oooxoxxo xxoxxoxo [MSB]
1001 09:54:42.486960 38, [0] oxoxoxxo xxoxxxxo [MSB]
1002 09:54:42.487009 39, [0] oxoxoxxx xxoxxxxo [MSB]
1003 09:54:42.487058 40, [0] xxoxxxxx xxoxxxxo [MSB]
1004 09:54:42.487108 41, [0] xxoxxxxx xxoxxxxx [MSB]
1005 09:54:42.487158 42, [0] xxxxxxxx xxxxxxxx [MSB]
1006 09:54:42.487207 iDelay=42, Bit 0, Center 23 (8 ~ 39) 32
1007 09:54:42.487256 iDelay=42, Bit 1, Center 22 (7 ~ 37) 31
1008 09:54:42.487305 iDelay=42, Bit 2, Center 25 (10 ~ 41) 32
1009 09:54:42.487354 iDelay=42, Bit 3, Center 16 (2 ~ 31) 30
1010 09:54:42.487416 iDelay=42, Bit 4, Center 24 (9 ~ 39) 31
1011 09:54:42.487464 iDelay=42, Bit 5, Center 18 (3 ~ 34) 32
1012 09:54:42.487511 iDelay=42, Bit 6, Center 20 (6 ~ 35) 30
1013 09:54:42.487559 iDelay=42, Bit 7, Center 22 (6 ~ 38) 33
1014 09:54:42.487606 iDelay=42, Bit 8, Center 17 (2 ~ 32) 31
1015 09:54:42.487654 iDelay=42, Bit 9, Center 19 (4 ~ 35) 32
1016 09:54:42.487702 iDelay=42, Bit 10, Center 26 (11 ~ 41) 31
1017 09:54:42.487750 iDelay=42, Bit 11, Center 18 (3 ~ 34) 32
1018 09:54:42.487797 iDelay=42, Bit 12, Center 20 (6 ~ 35) 30
1019 09:54:42.487846 iDelay=42, Bit 13, Center 21 (5 ~ 37) 33
1020 09:54:42.487893 iDelay=42, Bit 14, Center 20 (5 ~ 36) 32
1021 09:54:42.487941 iDelay=42, Bit 15, Center 24 (8 ~ 40) 33
1022 09:54:42.487991 ==
1023 09:54:42.488039 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1024 09:54:42.488088 fsp= 1, odt_onoff= 1, Byte mode= 0
1025 09:54:42.488136 ==
1026 09:54:42.488183 DQS Delay:
1027 09:54:42.488230 DQS0 = 0, DQS1 = 0
1028 09:54:42.488277 DQM Delay:
1029 09:54:42.488325 DQM0 = 21, DQM1 = 20
1030 09:54:42.488372 DQ Delay:
1031 09:54:42.488420 DQ0 =23, DQ1 =22, DQ2 =25, DQ3 =16
1032 09:54:42.488467 DQ4 =24, DQ5 =18, DQ6 =20, DQ7 =22
1033 09:54:42.488729 DQ8 =17, DQ9 =19, DQ10 =26, DQ11 =18
1034 09:54:42.488823 DQ12 =20, DQ13 =21, DQ14 =20, DQ15 =24
1035 09:54:42.488874
1036 09:54:42.488923
1037 09:54:42.488972 DramC Write-DBI off
1038 09:54:42.489020 ==
1039 09:54:42.489068 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1040 09:54:42.489117 fsp= 1, odt_onoff= 1, Byte mode= 0
1041 09:54:42.489165 ==
1042 09:54:42.489214 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1043 09:54:42.489262
1044 09:54:42.489309 Begin, DQ Scan Range 919~1175
1045 09:54:42.489357
1046 09:54:42.489404
1047 09:54:42.489452 TX Vref Scan disable
1048 09:54:42.489501 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB]
1049 09:54:42.489551 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1050 09:54:42.489600 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1051 09:54:42.489649 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1052 09:54:42.489698 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1053 09:54:42.489748 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1054 09:54:42.489797 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1055 09:54:42.489846 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1056 09:54:42.489895 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1057 09:54:42.489944 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1058 09:54:42.490004 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1059 09:54:42.490099 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1060 09:54:42.490148 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1061 09:54:42.490198 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1062 09:54:42.490248 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1063 09:54:42.490297 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1064 09:54:42.490345 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1065 09:54:42.490394 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1066 09:54:42.490443 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1067 09:54:42.490492 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1068 09:54:42.490540 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1069 09:54:42.490590 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1070 09:54:42.490639 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1071 09:54:42.490687 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1072 09:54:42.490736 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1073 09:54:42.490785 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1074 09:54:42.490834 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1075 09:54:42.490883 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1076 09:54:42.490931 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1077 09:54:42.490979 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1078 09:54:42.491028 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1079 09:54:42.491077 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1080 09:54:42.491126 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1081 09:54:42.491175 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1082 09:54:42.491223 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1083 09:54:42.491272 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1084 09:54:42.491321 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1085 09:54:42.491370 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1086 09:54:42.491419 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1087 09:54:42.491468 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1088 09:54:42.491517 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1089 09:54:42.491567 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1090 09:54:42.491615 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1091 09:54:42.491665 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1092 09:54:42.491714 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1093 09:54:42.491763 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1094 09:54:42.491813 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1095 09:54:42.491861 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1096 09:54:42.491910 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1097 09:54:42.491959 968 |3 6 8|[0] xxxxxxxx ooxoxxxx [MSB]
1098 09:54:42.492008 969 |3 6 9|[0] xxxxxxxx ooxoooxx [MSB]
1099 09:54:42.492057 970 |3 6 10|[0] xxxxxxxx ooxoooxx [MSB]
1100 09:54:42.492106 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1101 09:54:42.492155 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1102 09:54:42.492204 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1103 09:54:42.492252 974 |3 6 14|[0] xxxxxxxx ooooooox [MSB]
1104 09:54:42.492301 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1105 09:54:42.492350 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1106 09:54:42.492398 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1107 09:54:42.492447 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
1108 09:54:42.492496 979 |3 6 19|[0] xxxoxxxx oooooooo [MSB]
1109 09:54:42.492544 980 |3 6 20|[0] xxxooooo oooooooo [MSB]
1110 09:54:42.492593 981 |3 6 21|[0] xxxooooo oooooooo [MSB]
1111 09:54:42.492642 982 |3 6 22|[0] xoxooooo oooooooo [MSB]
1112 09:54:42.492691 987 |3 6 27|[0] oooooooo xooooooo [MSB]
1113 09:54:42.492778 988 |3 6 28|[0] oooooooo xooxoooo [MSB]
1114 09:54:42.492850 989 |3 6 29|[0] oooooooo xooxoooo [MSB]
1115 09:54:42.492900 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1116 09:54:42.492949 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1117 09:54:42.492998 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1118 09:54:42.493047 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1119 09:54:42.493097 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
1120 09:54:42.493145 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1121 09:54:42.493194 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
1122 09:54:42.493243 997 |3 6 37|[0] oooxoxoo xxxxxxxx [MSB]
1123 09:54:42.493293 998 |3 6 38|[0] oooxoxoo xxxxxxxx [MSB]
1124 09:54:42.493341 999 |3 6 39|[0] oooxoxxo xxxxxxxx [MSB]
1125 09:54:42.493391 1000 |3 6 40|[0] oooxxxxx xxxxxxxx [MSB]
1126 09:54:42.493440 1001 |3 6 41|[0] oooxxxxx xxxxxxxx [MSB]
1127 09:54:42.493490 1002 |3 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
1128 09:54:42.493539 Byte0, DQ PI dly=989, DQM PI dly= 989
1129 09:54:42.493588 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
1130 09:54:42.493636
1131 09:54:42.493684 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
1132 09:54:42.493732
1133 09:54:42.493779 Byte1, DQ PI dly=979, DQM PI dly= 979
1134 09:54:42.493827 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1135 09:54:42.493876
1136 09:54:42.493924 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1137 09:54:42.493972
1138 09:54:42.494063 ==
1139 09:54:42.494111 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1140 09:54:42.494160 fsp= 1, odt_onoff= 1, Byte mode= 0
1141 09:54:42.494209 ==
1142 09:54:42.494256 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1143 09:54:42.494304
1144 09:54:42.494352 Begin, DQ Scan Range 955~1019
1145 09:54:42.494400 Write Rank0 MR14 =0x0
1146 09:54:42.494448
1147 09:54:42.494496 CH=0, VrefRange= 0, VrefLevel = 0
1148 09:54:42.494734 TX Bit0 (986~995) 10 990, Bit8 (970~982) 13 976,
1149 09:54:42.494789 TX Bit1 (984~996) 13 990, Bit9 (972~984) 13 978,
1150 09:54:42.494860 TX Bit2 (985~995) 11 990, Bit10 (978~987) 10 982,
1151 09:54:42.494911 TX Bit3 (979~991) 13 985, Bit11 (972~983) 12 977,
1152 09:54:42.494975 TX Bit4 (983~994) 12 988, Bit12 (973~984) 12 978,
1153 09:54:42.495024 TX Bit5 (984~992) 9 988, Bit13 (973~983) 11 978,
1154 09:54:42.495073 TX Bit6 (982~994) 13 988, Bit14 (974~986) 13 980,
1155 09:54:42.495122 TX Bit7 (983~994) 12 988, Bit15 (979~989) 11 984,
1156 09:54:42.495169
1157 09:54:42.495217 Write Rank0 MR14 =0x2
1158 09:54:42.495265
1159 09:54:42.495312 CH=0, VrefRange= 0, VrefLevel = 2
1160 09:54:42.495361 TX Bit0 (986~996) 11 991, Bit8 (970~983) 14 976,
1161 09:54:42.495409 TX Bit1 (985~996) 12 990, Bit9 (972~985) 14 978,
1162 09:54:42.495458 TX Bit2 (985~995) 11 990, Bit10 (976~988) 13 982,
1163 09:54:42.495507 TX Bit3 (979~992) 14 985, Bit11 (971~983) 13 977,
1164 09:54:42.495555 TX Bit4 (984~994) 11 989, Bit12 (972~985) 14 978,
1165 09:54:42.495603 TX Bit5 (983~993) 11 988, Bit13 (972~984) 13 978,
1166 09:54:42.495652 TX Bit6 (981~994) 14 987, Bit14 (973~988) 16 980,
1167 09:54:42.495700 TX Bit7 (983~995) 13 989, Bit15 (978~989) 12 983,
1168 09:54:42.495749
1169 09:54:42.495796 Write Rank0 MR14 =0x4
1170 09:54:42.495845
1171 09:54:42.495892 CH=0, VrefRange= 0, VrefLevel = 4
1172 09:54:42.495940 TX Bit0 (985~997) 13 991, Bit8 (969~983) 15 976,
1173 09:54:42.495990 TX Bit1 (983~997) 15 990, Bit9 (972~986) 15 979,
1174 09:54:42.496038 TX Bit2 (985~996) 12 990, Bit10 (976~989) 14 982,
1175 09:54:42.496086 TX Bit3 (979~992) 14 985, Bit11 (971~984) 14 977,
1176 09:54:42.496134 TX Bit4 (983~995) 13 989, Bit12 (971~985) 15 978,
1177 09:54:42.496184 TX Bit5 (982~993) 12 987, Bit13 (972~984) 13 978,
1178 09:54:42.496232 TX Bit6 (981~994) 14 987, Bit14 (973~988) 16 980,
1179 09:54:42.496281 TX Bit7 (983~995) 13 989, Bit15 (977~989) 13 983,
1180 09:54:42.496329
1181 09:54:42.496377 Write Rank0 MR14 =0x6
1182 09:54:42.496425
1183 09:54:42.496472 CH=0, VrefRange= 0, VrefLevel = 6
1184 09:54:42.496520 TX Bit0 (985~998) 14 991, Bit8 (968~983) 16 975,
1185 09:54:42.496568 TX Bit1 (984~998) 15 991, Bit9 (971~986) 16 978,
1186 09:54:42.496617 TX Bit2 (985~997) 13 991, Bit10 (975~989) 15 982,
1187 09:54:42.496666 TX Bit3 (979~993) 15 986, Bit11 (970~984) 15 977,
1188 09:54:42.496715 TX Bit4 (982~996) 15 989, Bit12 (971~986) 16 978,
1189 09:54:42.496763 TX Bit5 (982~993) 12 987, Bit13 (972~985) 14 978,
1190 09:54:42.496812 TX Bit6 (981~995) 15 988, Bit14 (973~988) 16 980,
1191 09:54:42.496860 TX Bit7 (982~996) 15 989, Bit15 (976~990) 15 983,
1192 09:54:42.496908
1193 09:54:42.496955 Write Rank0 MR14 =0x8
1194 09:54:42.497002
1195 09:54:42.497050 CH=0, VrefRange= 0, VrefLevel = 8
1196 09:54:42.497099 TX Bit0 (984~999) 16 991, Bit8 (968~984) 17 976,
1197 09:54:42.497148 TX Bit1 (983~998) 16 990, Bit9 (971~987) 17 979,
1198 09:54:42.497196 TX Bit2 (985~998) 14 991, Bit10 (975~989) 15 982,
1199 09:54:42.497245 TX Bit3 (979~993) 15 986, Bit11 (970~984) 15 977,
1200 09:54:42.497293 TX Bit4 (982~996) 15 989, Bit12 (971~987) 17 979,
1201 09:54:42.497342 TX Bit5 (981~994) 14 987, Bit13 (971~986) 16 978,
1202 09:54:42.497391 TX Bit6 (980~995) 16 987, Bit14 (972~989) 18 980,
1203 09:54:42.497439 TX Bit7 (982~997) 16 989, Bit15 (976~990) 15 983,
1204 09:54:42.497488
1205 09:54:42.497536 Write Rank0 MR14 =0xa
1206 09:54:42.497583
1207 09:54:42.497631 CH=0, VrefRange= 0, VrefLevel = 10
1208 09:54:42.497680 TX Bit0 (985~1000) 16 992, Bit8 (968~984) 17 976,
1209 09:54:42.497728 TX Bit1 (982~999) 18 990, Bit9 (971~987) 17 979,
1210 09:54:42.497776 TX Bit2 (984~999) 16 991, Bit10 (975~990) 16 982,
1211 09:54:42.497824 TX Bit3 (979~993) 15 986, Bit11 (969~985) 17 977,
1212 09:54:42.497873 TX Bit4 (982~997) 16 989, Bit12 (970~988) 19 979,
1213 09:54:42.497921 TX Bit5 (981~995) 15 988, Bit13 (970~986) 17 978,
1214 09:54:42.497969 TX Bit6 (981~996) 16 988, Bit14 (972~989) 18 980,
1215 09:54:42.498052 TX Bit7 (981~997) 17 989, Bit15 (976~991) 16 983,
1216 09:54:42.498114
1217 09:54:42.498161 Write Rank0 MR14 =0xc
1218 09:54:42.498209
1219 09:54:42.498257 CH=0, VrefRange= 0, VrefLevel = 12
1220 09:54:42.498305 TX Bit0 (984~1000) 17 992, Bit8 (968~985) 18 976,
1221 09:54:42.498354 TX Bit1 (982~999) 18 990, Bit9 (970~988) 19 979,
1222 09:54:42.498403 TX Bit2 (984~999) 16 991, Bit10 (975~991) 17 983,
1223 09:54:42.498452 TX Bit3 (978~994) 17 986, Bit11 (969~986) 18 977,
1224 09:54:42.498501 TX Bit4 (981~998) 18 989, Bit12 (970~988) 19 979,
1225 09:54:42.498549 TX Bit5 (980~995) 16 987, Bit13 (970~986) 17 978,
1226 09:54:42.498597 TX Bit6 (980~996) 17 988, Bit14 (971~989) 19 980,
1227 09:54:42.498645 TX Bit7 (981~998) 18 989, Bit15 (976~991) 16 983,
1228 09:54:42.498698
1229 09:54:42.498806 Write Rank0 MR14 =0xe
1230 09:54:42.498871
1231 09:54:42.498921 CH=0, VrefRange= 0, VrefLevel = 14
1232 09:54:42.498970 TX Bit0 (984~1001) 18 992, Bit8 (968~986) 19 977,
1233 09:54:42.499019 TX Bit1 (982~1000) 19 991, Bit9 (969~989) 21 979,
1234 09:54:42.499067 TX Bit2 (984~1000) 17 992, Bit10 (974~991) 18 982,
1235 09:54:42.499116 TX Bit3 (978~994) 17 986, Bit11 (968~986) 19 977,
1236 09:54:42.499165 TX Bit4 (981~998) 18 989, Bit12 (969~989) 21 979,
1237 09:54:42.499214 TX Bit5 (980~996) 17 988, Bit13 (970~988) 19 979,
1238 09:54:42.499263 TX Bit6 (980~997) 18 988, Bit14 (970~990) 21 980,
1239 09:54:42.499312 TX Bit7 (981~999) 19 990, Bit15 (975~992) 18 983,
1240 09:54:42.499360
1241 09:54:42.499407 Write Rank0 MR14 =0x10
1242 09:54:42.499455
1243 09:54:42.499503 CH=0, VrefRange= 0, VrefLevel = 16
1244 09:54:42.499552 TX Bit0 (983~1002) 20 992, Bit8 (968~986) 19 977,
1245 09:54:42.499601 TX Bit1 (982~1001) 20 991, Bit9 (969~989) 21 979,
1246 09:54:42.499650 TX Bit2 (983~1001) 19 992, Bit10 (974~992) 19 983,
1247 09:54:42.499886 TX Bit3 (978~994) 17 986, Bit11 (968~988) 21 978,
1248 09:54:42.499942 TX Bit4 (981~999) 19 990, Bit12 (969~989) 21 979,
1249 09:54:42.499992 TX Bit5 (980~996) 17 988, Bit13 (969~988) 20 978,
1250 09:54:42.500041 TX Bit6 (980~998) 19 989, Bit14 (970~990) 21 980,
1251 09:54:42.500090 TX Bit7 (980~999) 20 989, Bit15 (975~993) 19 984,
1252 09:54:42.500139
1253 09:54:42.500196 Write Rank0 MR14 =0x12
1254 09:54:42.500288
1255 09:54:42.500374 CH=0, VrefRange= 0, VrefLevel = 18
1256 09:54:42.500425 TX Bit0 (983~1002) 20 992, Bit8 (967~987) 21 977,
1257 09:54:42.500475 TX Bit1 (981~1001) 21 991, Bit9 (969~990) 22 979,
1258 09:54:42.500525 TX Bit2 (983~1001) 19 992, Bit10 (974~991) 18 982,
1259 09:54:42.500574 TX Bit3 (978~994) 17 986, Bit11 (968~988) 21 978,
1260 09:54:42.500622 TX Bit4 (980~1000) 21 990, Bit12 (968~989) 22 978,
1261 09:54:42.500672 TX Bit5 (979~997) 19 988, Bit13 (968~989) 22 978,
1262 09:54:42.500721 TX Bit6 (980~998) 19 989, Bit14 (969~990) 22 979,
1263 09:54:42.500770 TX Bit7 (980~1000) 21 990, Bit15 (974~993) 20 983,
1264 09:54:42.500818
1265 09:54:42.500866 Write Rank0 MR14 =0x14
1266 09:54:42.500915
1267 09:54:42.500963 CH=0, VrefRange= 0, VrefLevel = 20
1268 09:54:42.501012 TX Bit0 (983~1002) 20 992, Bit8 (967~988) 22 977,
1269 09:54:42.501061 TX Bit1 (981~1002) 22 991, Bit9 (968~989) 22 978,
1270 09:54:42.501110 TX Bit2 (983~1002) 20 992, Bit10 (974~993) 20 983,
1271 09:54:42.501159 TX Bit3 (977~995) 19 986, Bit11 (968~988) 21 978,
1272 09:54:42.501207 TX Bit4 (980~1001) 22 990, Bit12 (968~989) 22 978,
1273 09:54:42.501256 TX Bit5 (980~998) 19 989, Bit13 (968~989) 22 978,
1274 09:54:42.501304 TX Bit6 (979~999) 21 989, Bit14 (970~990) 21 980,
1275 09:54:42.501352 TX Bit7 (980~1001) 22 990, Bit15 (974~993) 20 983,
1276 09:54:42.501401
1277 09:54:42.501449 Write Rank0 MR14 =0x16
1278 09:54:42.501497
1279 09:54:42.501544 CH=0, VrefRange= 0, VrefLevel = 22
1280 09:54:42.501593 TX Bit0 (983~1002) 20 992, Bit8 (967~988) 22 977,
1281 09:54:42.501641 TX Bit1 (981~1002) 22 991, Bit9 (968~989) 22 978,
1282 09:54:42.501689 TX Bit2 (983~1002) 20 992, Bit10 (974~993) 20 983,
1283 09:54:42.501737 TX Bit3 (977~995) 19 986, Bit11 (968~988) 21 978,
1284 09:54:42.501786 TX Bit4 (980~1001) 22 990, Bit12 (968~989) 22 978,
1285 09:54:42.501834 TX Bit5 (980~998) 19 989, Bit13 (968~989) 22 978,
1286 09:54:42.501882 TX Bit6 (979~999) 21 989, Bit14 (970~990) 21 980,
1287 09:54:42.501931 TX Bit7 (980~1001) 22 990, Bit15 (974~993) 20 983,
1288 09:54:42.501979
1289 09:54:42.502069 Write Rank0 MR14 =0x18
1290 09:54:42.502117
1291 09:54:42.502165 CH=0, VrefRange= 0, VrefLevel = 24
1292 09:54:42.502213 TX Bit0 (983~1004) 22 993, Bit8 (967~989) 23 978,
1293 09:54:42.502262 TX Bit1 (980~1003) 24 991, Bit9 (968~990) 23 979,
1294 09:54:42.502312 TX Bit2 (982~1003) 22 992, Bit10 (973~994) 22 983,
1295 09:54:42.502360 TX Bit3 (978~996) 19 987, Bit11 (967~989) 23 978,
1296 09:54:42.502409 TX Bit4 (980~1002) 23 991, Bit12 (968~991) 24 979,
1297 09:54:42.502458 TX Bit5 (979~998) 20 988, Bit13 (968~990) 23 979,
1298 09:54:42.502506 TX Bit6 (979~1000) 22 989, Bit14 (969~992) 24 980,
1299 09:54:42.502554 TX Bit7 (980~1002) 23 991, Bit15 (973~994) 22 983,
1300 09:54:42.502602
1301 09:54:42.502651 Write Rank0 MR14 =0x1a
1302 09:54:42.502699
1303 09:54:42.502762 CH=0, VrefRange= 0, VrefLevel = 26
1304 09:54:42.502844 TX Bit0 (982~1004) 23 993, Bit8 (967~989) 23 978,
1305 09:54:42.502908 TX Bit1 (980~1003) 24 991, Bit9 (967~989) 23 978,
1306 09:54:42.502957 TX Bit2 (981~1003) 23 992, Bit10 (973~994) 22 983,
1307 09:54:42.503005 TX Bit3 (977~996) 20 986, Bit11 (967~989) 23 978,
1308 09:54:42.503054 TX Bit4 (980~1002) 23 991, Bit12 (968~990) 23 979,
1309 09:54:42.503102 TX Bit5 (979~999) 21 989, Bit13 (968~990) 23 979,
1310 09:54:42.503151 TX Bit6 (979~1001) 23 990, Bit14 (968~992) 25 980,
1311 09:54:42.503200 TX Bit7 (980~1002) 23 991, Bit15 (973~994) 22 983,
1312 09:54:42.503249
1313 09:54:42.503297 Write Rank0 MR14 =0x1c
1314 09:54:42.503345
1315 09:54:42.503392 CH=0, VrefRange= 0, VrefLevel = 28
1316 09:54:42.503439 TX Bit0 (981~1005) 25 993, Bit8 (966~989) 24 977,
1317 09:54:42.503487 TX Bit1 (980~1003) 24 991, Bit9 (968~990) 23 979,
1318 09:54:42.503536 TX Bit2 (981~1004) 24 992, Bit10 (972~995) 24 983,
1319 09:54:42.503585 TX Bit3 (977~997) 21 987, Bit11 (967~990) 24 978,
1320 09:54:42.503633 TX Bit4 (980~1003) 24 991, Bit12 (968~991) 24 979,
1321 09:54:42.503681 TX Bit5 (979~999) 21 989, Bit13 (967~990) 24 978,
1322 09:54:42.503730 TX Bit6 (979~1001) 23 990, Bit14 (968~992) 25 980,
1323 09:54:42.503778 TX Bit7 (980~1003) 24 991, Bit15 (973~995) 23 984,
1324 09:54:42.503826
1325 09:54:42.503873 Write Rank0 MR14 =0x1e
1326 09:54:42.503920
1327 09:54:42.503968 CH=0, VrefRange= 0, VrefLevel = 30
1328 09:54:42.504017 TX Bit0 (981~1005) 25 993, Bit8 (966~989) 24 977,
1329 09:54:42.504065 TX Bit1 (980~1003) 24 991, Bit9 (967~990) 24 978,
1330 09:54:42.504113 TX Bit2 (982~1004) 23 993, Bit10 (972~996) 25 984,
1331 09:54:42.504162 TX Bit3 (977~997) 21 987, Bit11 (967~989) 23 978,
1332 09:54:42.504209 TX Bit4 (980~1003) 24 991, Bit12 (968~990) 23 979,
1333 09:54:42.504257 TX Bit5 (979~1000) 22 989, Bit13 (968~990) 23 979,
1334 09:54:42.504304 TX Bit6 (979~1002) 24 990, Bit14 (968~991) 24 979,
1335 09:54:42.504352 TX Bit7 (980~1003) 24 991, Bit15 (972~996) 25 984,
1336 09:54:42.504400
1337 09:54:42.504446 Write Rank0 MR14 =0x20
1338 09:54:42.504493
1339 09:54:42.504539 CH=0, VrefRange= 0, VrefLevel = 32
1340 09:54:42.504587 TX Bit0 (981~1005) 25 993, Bit8 (966~989) 24 977,
1341 09:54:42.504636 TX Bit1 (980~1003) 24 991, Bit9 (967~990) 24 978,
1342 09:54:42.504683 TX Bit2 (982~1004) 23 993, Bit10 (972~996) 25 984,
1343 09:54:42.504731 TX Bit3 (977~997) 21 987, Bit11 (967~989) 23 978,
1344 09:54:42.504781 TX Bit4 (980~1003) 24 991, Bit12 (968~990) 23 979,
1345 09:54:42.504830 TX Bit5 (979~1000) 22 989, Bit13 (968~990) 23 979,
1346 09:54:42.505069 TX Bit6 (979~1002) 24 990, Bit14 (968~991) 24 979,
1347 09:54:42.505164 TX Bit7 (980~1003) 24 991, Bit15 (972~996) 25 984,
1348 09:54:42.505213
1349 09:54:42.505261 Write Rank0 MR14 =0x22
1350 09:54:42.505308
1351 09:54:42.505375 CH=0, VrefRange= 0, VrefLevel = 34
1352 09:54:42.505437 TX Bit0 (981~1005) 25 993, Bit8 (966~989) 24 977,
1353 09:54:42.505485 TX Bit1 (980~1003) 24 991, Bit9 (967~990) 24 978,
1354 09:54:42.505533 TX Bit2 (982~1004) 23 993, Bit10 (972~996) 25 984,
1355 09:54:42.505582 TX Bit3 (977~997) 21 987, Bit11 (967~989) 23 978,
1356 09:54:42.505630 TX Bit4 (980~1003) 24 991, Bit12 (968~990) 23 979,
1357 09:54:42.505678 TX Bit5 (979~1000) 22 989, Bit13 (968~990) 23 979,
1358 09:54:42.505726 TX Bit6 (979~1002) 24 990, Bit14 (968~991) 24 979,
1359 09:54:42.505775 TX Bit7 (980~1003) 24 991, Bit15 (972~996) 25 984,
1360 09:54:42.505823
1361 09:54:42.505870 Write Rank0 MR14 =0x24
1362 09:54:42.505933
1363 09:54:42.505987 CH=0, VrefRange= 0, VrefLevel = 36
1364 09:54:42.506051 TX Bit0 (981~1005) 25 993, Bit8 (966~989) 24 977,
1365 09:54:42.506100 TX Bit1 (980~1003) 24 991, Bit9 (967~990) 24 978,
1366 09:54:42.506147 TX Bit2 (982~1004) 23 993, Bit10 (972~996) 25 984,
1367 09:54:42.506197 TX Bit3 (977~997) 21 987, Bit11 (967~989) 23 978,
1368 09:54:42.506245 TX Bit4 (980~1003) 24 991, Bit12 (968~990) 23 979,
1369 09:54:42.506294 TX Bit5 (979~1000) 22 989, Bit13 (968~990) 23 979,
1370 09:54:42.506342 TX Bit6 (979~1002) 24 990, Bit14 (968~991) 24 979,
1371 09:54:42.506390 TX Bit7 (980~1003) 24 991, Bit15 (972~996) 25 984,
1372 09:54:42.506438
1373 09:54:42.506485
1374 09:54:42.506532 TX Vref found, early break! 358< 359
1375 09:54:42.506580 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =844/100 ps
1376 09:54:42.506628 u1DelayCellOfst[0]=6 cells (6 PI)
1377 09:54:42.506675 u1DelayCellOfst[1]=4 cells (4 PI)
1378 09:54:42.506723 u1DelayCellOfst[2]=6 cells (6 PI)
1379 09:54:42.506771 u1DelayCellOfst[3]=0 cells (0 PI)
1380 09:54:42.506818 u1DelayCellOfst[4]=4 cells (4 PI)
1381 09:54:42.506865 u1DelayCellOfst[5]=2 cells (2 PI)
1382 09:54:42.506913 u1DelayCellOfst[6]=3 cells (3 PI)
1383 09:54:42.506960 u1DelayCellOfst[7]=4 cells (4 PI)
1384 09:54:42.507007 Byte0, DQ PI dly=987, DQM PI dly= 990
1385 09:54:42.507055 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
1386 09:54:42.507103
1387 09:54:42.507151 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
1388 09:54:42.507199
1389 09:54:42.507247 u1DelayCellOfst[8]=0 cells (0 PI)
1390 09:54:42.507294 u1DelayCellOfst[9]=1 cells (1 PI)
1391 09:54:42.507341 u1DelayCellOfst[10]=8 cells (7 PI)
1392 09:54:42.507388 u1DelayCellOfst[11]=1 cells (1 PI)
1393 09:54:42.507435 u1DelayCellOfst[12]=2 cells (2 PI)
1394 09:54:42.507482 u1DelayCellOfst[13]=2 cells (2 PI)
1395 09:54:42.507530 u1DelayCellOfst[14]=2 cells (2 PI)
1396 09:54:42.507577 u1DelayCellOfst[15]=8 cells (7 PI)
1397 09:54:42.507625 Byte1, DQ PI dly=977, DQM PI dly= 980
1398 09:54:42.507673 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
1399 09:54:42.507721
1400 09:54:42.507767 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
1401 09:54:42.507815
1402 09:54:42.507862 Write Rank0 MR14 =0x1e
1403 09:54:42.507909
1404 09:54:42.507956 Final TX Range 0 Vref 30
1405 09:54:42.508004
1406 09:54:42.508052 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1407 09:54:42.508101
1408 09:54:42.508148 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1409 09:54:42.508196 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1410 09:54:42.508244 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1411 09:54:42.508292 Write Rank0 MR3 =0xb0
1412 09:54:42.508339 DramC Write-DBI on
1413 09:54:42.508386 ==
1414 09:54:42.508433 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1415 09:54:42.508481 fsp= 1, odt_onoff= 1, Byte mode= 0
1416 09:54:42.508529 ==
1417 09:54:42.508576 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1418 09:54:42.508623
1419 09:54:42.508670 Begin, DQ Scan Range 700~764
1420 09:54:42.508717
1421 09:54:42.508764
1422 09:54:42.508810 TX Vref Scan disable
1423 09:54:42.508856 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1424 09:54:42.508905 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1425 09:54:42.508954 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1426 09:54:42.509002 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1427 09:54:42.509050 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1428 09:54:42.509099 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1429 09:54:42.509148 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1430 09:54:42.509196 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1431 09:54:42.509245 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1432 09:54:42.509294 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1433 09:54:42.509342 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1434 09:54:42.509391 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1435 09:54:42.509438 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1436 09:54:42.509486 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1437 09:54:42.509535 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1438 09:54:42.509583 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1439 09:54:42.509631 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1440 09:54:42.509679 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1441 09:54:42.509728 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1442 09:54:42.509776 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1443 09:54:42.509824 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
1444 09:54:42.509875 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
1445 09:54:42.509923 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
1446 09:54:42.509972 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
1447 09:54:42.510065 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1448 09:54:42.510113 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1449 09:54:42.510161 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1450 09:54:42.510209 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1451 09:54:42.510257 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1452 09:54:42.510305 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1453 09:54:42.510355 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1454 09:54:42.510403 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1455 09:54:42.510451 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1456 09:54:42.510499 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1457 09:54:42.510548 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
1458 09:54:42.510820 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
1459 09:54:42.510874 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
1460 09:54:42.510924 749 |2 6 45|[0] xxxxxxxx xxxxxxxx [MSB]
1461 09:54:42.510973 Byte0, DQ PI dly=736, DQM PI dly= 736
1462 09:54:42.511021 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 32)
1463 09:54:42.511069
1464 09:54:42.511117 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 32)
1465 09:54:42.511166
1466 09:54:42.511213 Byte1, DQ PI dly=723, DQM PI dly= 723
1467 09:54:42.511261 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
1468 09:54:42.511309
1469 09:54:42.511356 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
1470 09:54:42.511404
1471 09:54:42.511451 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1472 09:54:42.511500 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1473 09:54:42.511548 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1474 09:54:42.511597 Write Rank0 MR3 =0x30
1475 09:54:42.511643 DramC Write-DBI off
1476 09:54:42.511690
1477 09:54:42.511737 [DATLAT]
1478 09:54:42.511784 Freq=1600, CH0 RK0, use_rxtx_scan=0
1479 09:54:42.511832
1480 09:54:42.511878 DATLAT Default: 0xf
1481 09:54:42.511927 7, 0xFFFF, sum=0
1482 09:54:42.511976 8, 0xFFFF, sum=0
1483 09:54:42.512024 9, 0xFFFF, sum=0
1484 09:54:42.512072 10, 0xFFFF, sum=0
1485 09:54:42.512120 11, 0xFFFF, sum=0
1486 09:54:42.512169 12, 0xFFFF, sum=0
1487 09:54:42.512217 13, 0xFFFF, sum=0
1488 09:54:42.512265 14, 0x0, sum=1
1489 09:54:42.512313 15, 0x0, sum=2
1490 09:54:42.512360 16, 0x0, sum=3
1491 09:54:42.512409 17, 0x0, sum=4
1492 09:54:42.512456 pattern=2 first_step=14 total pass=5 best_step=16
1493 09:54:42.512503 ==
1494 09:54:42.512551 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1495 09:54:42.512598 fsp= 1, odt_onoff= 1, Byte mode= 0
1496 09:54:42.512646 ==
1497 09:54:42.512694 Start DQ dly to find pass range UseTestEngine =1
1498 09:54:42.512742 x-axis: bit #, y-axis: DQ dly (-127~63)
1499 09:54:42.512790 RX Vref Scan = 1
1500 09:54:42.512837
1501 09:54:42.512883 RX Vref found, early break!
1502 09:54:42.512930
1503 09:54:42.512977 Final RX Vref 12, apply to both rank0 and 1
1504 09:54:42.513025 ==
1505 09:54:42.513072 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1506 09:54:42.513120 fsp= 1, odt_onoff= 1, Byte mode= 0
1507 09:54:42.513167 ==
1508 09:54:42.513214 DQS Delay:
1509 09:54:42.513262 DQS0 = 0, DQS1 = 0
1510 09:54:42.513309 DQM Delay:
1511 09:54:42.513355 DQM0 = 21, DQM1 = 20
1512 09:54:42.513401 DQ Delay:
1513 09:54:42.513449 DQ0 =23, DQ1 =22, DQ2 =24, DQ3 =17
1514 09:54:42.513496 DQ4 =23, DQ5 =18, DQ6 =20, DQ7 =23
1515 09:54:42.513544 DQ8 =17, DQ9 =19, DQ10 =25, DQ11 =18
1516 09:54:42.513592 DQ12 =20, DQ13 =20, DQ14 =21, DQ15 =23
1517 09:54:42.513639
1518 09:54:42.513686
1519 09:54:42.513733
1520 09:54:42.513780 [DramC_TX_OE_Calibration] TA2
1521 09:54:42.513828 Original DQ_B0 (3 6) =30, OEN = 27
1522 09:54:42.513875 Original DQ_B1 (3 6) =30, OEN = 27
1523 09:54:42.513923 23, 0x0, End_B0=23 End_B1=23
1524 09:54:42.513971 24, 0x0, End_B0=24 End_B1=24
1525 09:54:42.514060 25, 0x0, End_B0=25 End_B1=25
1526 09:54:42.514109 26, 0x0, End_B0=26 End_B1=26
1527 09:54:42.514157 27, 0x0, End_B0=27 End_B1=27
1528 09:54:42.514206 28, 0x0, End_B0=28 End_B1=28
1529 09:54:42.514253 29, 0x0, End_B0=29 End_B1=29
1530 09:54:42.514300 30, 0x0, End_B0=30 End_B1=30
1531 09:54:42.514349 31, 0xFFFF, End_B0=30 End_B1=30
1532 09:54:42.514398 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1533 09:54:42.514446 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1534 09:54:42.514493
1535 09:54:42.514540
1536 09:54:42.514586 Write Rank0 MR23 =0x3f
1537 09:54:42.514634 [DQSOSC]
1538 09:54:42.514681 [DQSOSCAuto] RK0, (LSB)MR18= 0xcdcd, (MSB)MR19= 0x202, tDQSOscB0 = 439 ps tDQSOscB1 = 439 ps
1539 09:54:42.514732 CH0_RK0: MR19=0x202, MR18=0xCDCD, DQSOSC=439, MR23=63, INC=12, DEC=19
1540 09:54:42.514780 Write Rank0 MR23 =0x3f
1541 09:54:42.514827 [DQSOSC]
1542 09:54:42.514875 [DQSOSCAuto] RK0, (LSB)MR18= 0xcaca, (MSB)MR19= 0x202, tDQSOscB0 = 441 ps tDQSOscB1 = 441 ps
1543 09:54:42.514923 CH0 RK0: MR19=202, MR18=CACA
1544 09:54:42.514970 [RankSwap] Rank num 2, (Multi 1), Rank 1
1545 09:54:42.515018 Write Rank0 MR2 =0xad
1546 09:54:42.515065 [Write Leveling]
1547 09:54:42.515113 delay byte0 byte1 byte2 byte3
1548 09:54:42.515160
1549 09:54:42.515208 10 0 0
1550 09:54:42.515257 11 0 0
1551 09:54:42.515306 12 0 0
1552 09:54:42.515354 13 0 0
1553 09:54:42.515401 14 0 0
1554 09:54:42.515449 15 0 0
1555 09:54:42.515497 16 0 0
1556 09:54:42.515544 17 0 0
1557 09:54:42.515593 18 0 0
1558 09:54:42.515641 19 0 0
1559 09:54:42.515689 20 0 0
1560 09:54:42.515736 21 0 0
1561 09:54:42.515784 22 0 0
1562 09:54:42.515831 23 0 0
1563 09:54:42.515879 24 0 ff
1564 09:54:42.515927 25 0 ff
1565 09:54:42.515977 26 0 ff
1566 09:54:42.516025 27 0 ff
1567 09:54:42.516074 28 0 ff
1568 09:54:42.516122 29 0 ff
1569 09:54:42.516170 30 0 ff
1570 09:54:42.516218 31 0 ff
1571 09:54:42.516265 32 0 ff
1572 09:54:42.516312 33 ff ff
1573 09:54:42.516360 34 ff ff
1574 09:54:42.516408 35 ff ff
1575 09:54:42.516456 36 ff ff
1576 09:54:42.516503 37 ff ff
1577 09:54:42.516551 38 ff ff
1578 09:54:42.516598 39 ff ff
1579 09:54:42.516646 pass bytecount = 0xff (0xff: all bytes pass)
1580 09:54:42.516693
1581 09:54:42.516740 DQS0 dly: 33
1582 09:54:42.516788 DQS1 dly: 24
1583 09:54:42.516835 Write Rank0 MR2 =0x2d
1584 09:54:42.516882 [RankSwap] Rank num 2, (Multi 1), Rank 0
1585 09:54:42.516929 Write Rank1 MR1 =0xd6
1586 09:54:42.516975 [Gating]
1587 09:54:42.517021 ==
1588 09:54:42.517069 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1589 09:54:42.517117 fsp= 1, odt_onoff= 1, Byte mode= 0
1590 09:54:42.517165 ==
1591 09:54:42.517212 3 1 0 |3534 3535 |(11 11)(0 0) |(0 0)(1 1)| 0
1592 09:54:42.517261 3 1 4 |3534 3635 |(11 11)(11 11) |(0 0)(1 1)| 0
1593 09:54:42.517310 3 1 8 |3534 3535 |(11 11)(0 0) |(0 0)(0 0)| 0
1594 09:54:42.517358 3 1 12 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1595 09:54:42.517406 3 1 16 |3534 3635 |(11 11)(11 11) |(1 1)(1 1)| 0
1596 09:54:42.517454 3 1 20 |3534 3535 |(11 11)(0 0) |(0 0)(1 1)| 0
1597 09:54:42.517503 3 1 24 |3534 3635 |(11 11)(11 11) |(0 0)(0 0)| 0
1598 09:54:42.517551 3 1 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1599 09:54:42.517599 3 2 0 |3534 3434 |(11 11)(11 11) |(0 0)(0 0)| 0
1600 09:54:42.517647 3 2 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1601 09:54:42.517695 3 2 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1602 09:54:42.517743 3 2 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1603 09:54:42.517791 3 2 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1604 09:54:42.517839 3 2 20 |201 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1605 09:54:42.518089 3 2 24 |3d3d 3130 |(11 11)(11 11) |(1 1)(1 1)| 0
1606 09:54:42.518145 3 2 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1607 09:54:42.518197 3 3 0 |3d3d 3d3d |(11 11)(0 0) |(1 1)(1 1)| 0
1608 09:54:42.518247 3 3 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1609 09:54:42.518296 3 3 8 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
1610 09:54:42.518344 3 3 12 |3d3d 1918 |(11 11)(11 11) |(1 1)(1 1)| 0
1611 09:54:42.518393 3 3 16 |3d3d 3c3b |(11 11)(11 11) |(1 1)(1 1)| 0
1612 09:54:42.518442 3 3 20 |1615 3b3b |(11 11)(11 11) |(1 1)(1 1)| 0
1613 09:54:42.518490 3 3 24 |807 1413 |(11 11)(11 11) |(1 1)(1 1)| 0
1614 09:54:42.518538 [Byte 0] Lead/lag Transition tap number (1)
1615 09:54:42.518587 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1616 09:54:42.518636 [Byte 1] Lead/lag Transition tap number (1)
1617 09:54:42.518683 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1618 09:54:42.518732 3 4 4 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1619 09:54:42.518781 3 4 8 |3534 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1620 09:54:42.518829 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
1621 09:54:42.518877 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1622 09:54:42.518926 3 4 20 |e0d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1623 09:54:42.518975 3 4 24 |3d3d c6be |(11 11)(11 11) |(1 1)(1 1)| 0
1624 09:54:42.519024 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1625 09:54:42.519072 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1626 09:54:42.519120 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1627 09:54:42.519168 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1628 09:54:42.519216 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1629 09:54:42.519264 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1630 09:54:42.519313 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1631 09:54:42.519361 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1632 09:54:42.519409 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1633 09:54:42.519458 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1634 09:54:42.519507 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1635 09:54:42.519556 [Byte 0] Lead/lag falling Transition (3, 6, 4)
1636 09:54:42.519604 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1637 09:54:42.519653 [Byte 1] Lead/lag falling Transition (3, 6, 8)
1638 09:54:42.519700 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 0)| 0
1639 09:54:42.519749 [Byte 0] Lead/lag Transition tap number (3)
1640 09:54:42.519796 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1641 09:54:42.519846 [Byte 1] Lead/lag Transition tap number (3)
1642 09:54:42.519894 3 6 20 |4646 403 |(0 0)(11 11) |(0 0)(0 0)| 0
1643 09:54:42.519944 [Byte 0]First pass (3, 6, 20)
1644 09:54:42.519991 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1645 09:54:42.520040 [Byte 1]First pass (3, 6, 24)
1646 09:54:42.520087 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1647 09:54:42.520135 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1648 09:54:42.520184 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1649 09:54:42.520234 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1650 09:54:42.520282 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1651 09:54:42.520330 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1652 09:54:42.520378 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1653 09:54:42.520427 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1654 09:54:42.520475 All bytes gating window > 1UI, Early break!
1655 09:54:42.520522
1656 09:54:42.520570 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 10)
1657 09:54:42.520619
1658 09:54:42.520666 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 14)
1659 09:54:42.520713
1660 09:54:42.520760
1661 09:54:42.520807
1662 09:54:42.520854 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 10)
1663 09:54:42.520901
1664 09:54:42.520948 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 14)
1665 09:54:42.520995
1666 09:54:42.521042
1667 09:54:42.521090 Write Rank1 MR1 =0x56
1668 09:54:42.521136
1669 09:54:42.521183 best RODT dly(2T, 0.5T) = (2, 3)
1670 09:54:42.521230
1671 09:54:42.521278 best RODT dly(2T, 0.5T) = (2, 3)
1672 09:54:42.521325 ==
1673 09:54:42.521373 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1674 09:54:42.521420 fsp= 1, odt_onoff= 1, Byte mode= 0
1675 09:54:42.521467 ==
1676 09:54:42.521532 Start DQ dly to find pass range UseTestEngine =0
1677 09:54:42.521584 x-axis: bit #, y-axis: DQ dly (-127~63)
1678 09:54:42.521632 RX Vref Scan = 0
1679 09:54:42.521680 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1680 09:54:42.521729 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1681 09:54:42.521780 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1682 09:54:42.521829 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1683 09:54:42.521877 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1684 09:54:42.521926 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1685 09:54:42.521975 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1686 09:54:42.522033 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1687 09:54:42.522082 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1688 09:54:42.522131 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1689 09:54:42.522179 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1690 09:54:42.522228 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1691 09:54:42.522277 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1692 09:54:42.522326 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1693 09:54:42.522375 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1694 09:54:42.522422 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1695 09:54:42.522471 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1696 09:54:42.522519 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1697 09:54:42.522568 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1698 09:54:42.522616 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1699 09:54:42.522664 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1700 09:54:42.522712 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1701 09:54:42.522761 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1702 09:54:42.522809 -3, [0] xxxxxxxx xxxxxxxx [MSB]
1703 09:54:42.522857 -2, [0] xxxxxxxx xxxxxxxx [MSB]
1704 09:54:42.522905 -1, [0] xxxxxxxx xxxxxxxx [MSB]
1705 09:54:42.522953 0, [0] xxxxxxxx xxxxxxxx [MSB]
1706 09:54:42.523002 1, [0] xxxxxxxx xxxxxxxx [MSB]
1707 09:54:42.523051 2, [0] xxxxxxxx xxxxxxxx [MSB]
1708 09:54:42.523099 3, [0] xxxoxxxx oxxxxxxx [MSB]
1709 09:54:42.523147 4, [0] xxxoxoxx oxxoxxxx [MSB]
1710 09:54:42.523195 5, [0] xxxoxoox ooxoxxxx [MSB]
1711 09:54:42.523243 6, [0] xxxoxooo ooxoxxxx [MSB]
1712 09:54:42.523292 7, [0] xxxoxooo ooxooxxx [MSB]
1713 09:54:42.523340 8, [0] xooooooo ooxoooox [MSB]
1714 09:54:42.523388 9, [0] oooooooo ooxooooo [MSB]
1715 09:54:42.523622 10, [0] oooooooo ooxooooo [MSB]
1716 09:54:42.523676 11, [0] oooooooo ooxooooo [MSB]
1717 09:54:42.523726 32, [0] oooooooo oooooooo [MSB]
1718 09:54:42.523776 33, [0] oooxoooo xooooooo [MSB]
1719 09:54:42.523825 34, [0] oooxoooo xooooooo [MSB]
1720 09:54:42.523875 35, [0] oooxoooo xooxoooo [MSB]
1721 09:54:42.523924 36, [0] oooxooxo xxoxxooo [MSB]
1722 09:54:42.523973 37, [0] oooxoxxo xxoxxxoo [MSB]
1723 09:54:42.524022 38, [0] oooxoxxo xxoxxxxo [MSB]
1724 09:54:42.524070 39, [0] oooxoxxx xxoxxxxo [MSB]
1725 09:54:42.524120 40, [0] oxoxxxxx xxoxxxxo [MSB]
1726 09:54:42.524169 41, [0] xxxxxxxx xxoxxxxx [MSB]
1727 09:54:42.524217 42, [0] xxxxxxxx xxoxxxxx [MSB]
1728 09:54:42.524266 43, [0] xxxxxxxx xxoxxxxx [MSB]
1729 09:54:42.524314 44, [0] xxxxxxxx xxxxxxxx [MSB]
1730 09:54:42.524374 iDelay=44, Bit 0, Center 24 (9 ~ 40) 32
1731 09:54:42.524424 iDelay=44, Bit 1, Center 23 (8 ~ 39) 32
1732 09:54:42.524472 iDelay=44, Bit 2, Center 24 (8 ~ 40) 33
1733 09:54:42.524520 iDelay=44, Bit 3, Center 17 (3 ~ 32) 30
1734 09:54:42.524567 iDelay=44, Bit 4, Center 23 (8 ~ 39) 32
1735 09:54:42.524614 iDelay=44, Bit 5, Center 20 (4 ~ 36) 33
1736 09:54:42.524662 iDelay=44, Bit 6, Center 20 (5 ~ 35) 31
1737 09:54:42.524709 iDelay=44, Bit 7, Center 22 (6 ~ 38) 33
1738 09:54:42.524756 iDelay=44, Bit 8, Center 17 (3 ~ 32) 30
1739 09:54:42.524803 iDelay=44, Bit 9, Center 20 (5 ~ 35) 31
1740 09:54:42.524850 iDelay=44, Bit 10, Center 27 (12 ~ 43) 32
1741 09:54:42.524898 iDelay=44, Bit 11, Center 19 (4 ~ 34) 31
1742 09:54:42.524945 iDelay=44, Bit 12, Center 21 (7 ~ 35) 29
1743 09:54:42.524993 iDelay=44, Bit 13, Center 22 (8 ~ 36) 29
1744 09:54:42.525040 iDelay=44, Bit 14, Center 22 (8 ~ 37) 30
1745 09:54:42.525087 iDelay=44, Bit 15, Center 24 (9 ~ 40) 32
1746 09:54:42.525133 ==
1747 09:54:42.525180 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1748 09:54:42.525228 fsp= 1, odt_onoff= 1, Byte mode= 0
1749 09:54:42.525276 ==
1750 09:54:42.525323 DQS Delay:
1751 09:54:42.525370 DQS0 = 0, DQS1 = 0
1752 09:54:42.525417 DQM Delay:
1753 09:54:42.525464 DQM0 = 21, DQM1 = 21
1754 09:54:42.525511 DQ Delay:
1755 09:54:42.525558 DQ0 =24, DQ1 =23, DQ2 =24, DQ3 =17
1756 09:54:42.525605 DQ4 =23, DQ5 =20, DQ6 =20, DQ7 =22
1757 09:54:42.525653 DQ8 =17, DQ9 =20, DQ10 =27, DQ11 =19
1758 09:54:42.525701 DQ12 =21, DQ13 =22, DQ14 =22, DQ15 =24
1759 09:54:42.525754
1760 09:54:42.525801
1761 09:54:42.525849 DramC Write-DBI off
1762 09:54:42.525896 ==
1763 09:54:42.525943 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1764 09:54:42.525998 fsp= 1, odt_onoff= 1, Byte mode= 0
1765 09:54:42.526087 ==
1766 09:54:42.526134 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1767 09:54:42.526182
1768 09:54:42.526229 Begin, DQ Scan Range 920~1176
1769 09:54:42.526277
1770 09:54:42.526324
1771 09:54:42.526391 TX Vref Scan disable
1772 09:54:42.526476 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1773 09:54:42.526531 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1774 09:54:42.526581 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1775 09:54:42.526632 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1776 09:54:42.526682 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1777 09:54:42.526731 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1778 09:54:42.526780 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1779 09:54:42.526830 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1780 09:54:42.526878 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1781 09:54:42.526927 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1782 09:54:42.526977 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1783 09:54:42.527025 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1784 09:54:42.527074 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1785 09:54:42.527123 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1786 09:54:42.527171 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1787 09:54:42.527220 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1788 09:54:42.527269 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1789 09:54:42.527319 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1790 09:54:42.527368 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1791 09:54:42.527417 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1792 09:54:42.527465 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1793 09:54:42.527514 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1794 09:54:42.527563 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1795 09:54:42.527612 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1796 09:54:42.527660 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1797 09:54:42.527710 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1798 09:54:42.527759 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1799 09:54:42.527808 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1800 09:54:42.527857 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1801 09:54:42.527906 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1802 09:54:42.527954 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1803 09:54:42.528003 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1804 09:54:42.528051 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1805 09:54:42.528099 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1806 09:54:42.528148 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1807 09:54:42.528197 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1808 09:54:42.528259 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1809 09:54:42.528310 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1810 09:54:42.528359 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1811 09:54:42.528407 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1812 09:54:42.528457 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1813 09:54:42.528506 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1814 09:54:42.528555 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1815 09:54:42.528603 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1816 09:54:42.528652 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1817 09:54:42.528701 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1818 09:54:42.528749 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1819 09:54:42.528797 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1820 09:54:42.528846 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
1821 09:54:42.528894 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
1822 09:54:42.528942 970 |3 6 10|[0] xxxxxxxx oxxoxxxx [MSB]
1823 09:54:42.528990 971 |3 6 11|[0] xxxxxxxx oxxoxxxx [MSB]
1824 09:54:42.529038 972 |3 6 12|[0] xxxxxxxx ooxooxxx [MSB]
1825 09:54:42.529087 973 |3 6 13|[0] xxxxxxxx ooxoooxx [MSB]
1826 09:54:42.529136 974 |3 6 14|[0] xxxxxxxx ooxoooox [MSB]
1827 09:54:42.529184 975 |3 6 15|[0] xxxxxxxx ooxoooox [MSB]
1828 09:54:42.529233 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
1829 09:54:42.529280 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
1830 09:54:42.529516 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
1831 09:54:42.529574 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
1832 09:54:42.529624 980 |3 6 20|[0] xxxoxoox oooooooo [MSB]
1833 09:54:42.529673 981 |3 6 21|[0] xxxoooox oooooooo [MSB]
1834 09:54:42.529723 982 |3 6 22|[0] xoxooooo oooooooo [MSB]
1835 09:54:42.529772 990 |3 6 30|[0] oooooooo xooxoooo [MSB]
1836 09:54:42.529821 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1837 09:54:42.529869 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1838 09:54:42.529918 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
1839 09:54:42.529968 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
1840 09:54:42.530092 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1841 09:54:42.530171 996 |3 6 36|[0] oooxoooo xxxxxxxx [MSB]
1842 09:54:42.530249 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
1843 09:54:42.530327 998 |3 6 38|[0] oooxoxoo xxxxxxxx [MSB]
1844 09:54:42.530378 999 |3 6 39|[0] oooxoxoo xxxxxxxx [MSB]
1845 09:54:42.530429 1000 |3 6 40|[0] oooxoxxx xxxxxxxx [MSB]
1846 09:54:42.530478 1001 |3 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
1847 09:54:42.530527 Byte0, DQ PI dly=989, DQM PI dly= 989
1848 09:54:42.530575 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
1849 09:54:42.530624
1850 09:54:42.530672 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
1851 09:54:42.530720
1852 09:54:42.530768 Byte1, DQ PI dly=981, DQM PI dly= 981
1853 09:54:42.530816 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 21)
1854 09:54:42.530864
1855 09:54:42.530911 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 21)
1856 09:54:42.530959
1857 09:54:42.531006 ==
1858 09:54:42.531054 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1859 09:54:42.531102 fsp= 1, odt_onoff= 1, Byte mode= 0
1860 09:54:42.531150 ==
1861 09:54:42.531198 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1862 09:54:42.531245
1863 09:54:42.531291 Begin, DQ Scan Range 957~1021
1864 09:54:42.531338 Write Rank1 MR14 =0x0
1865 09:54:42.531385
1866 09:54:42.531433 CH=0, VrefRange= 0, VrefLevel = 0
1867 09:54:42.531481 TX Bit0 (985~998) 14 991, Bit8 (972~984) 13 978,
1868 09:54:42.531529 TX Bit1 (985~995) 11 990, Bit9 (973~988) 16 980,
1869 09:54:42.531577 TX Bit2 (985~996) 12 990, Bit10 (979~992) 14 985,
1870 09:54:42.531625 TX Bit3 (979~988) 10 983, Bit11 (973~983) 11 978,
1871 09:54:42.531674 TX Bit4 (984~996) 13 990, Bit12 (975~987) 13 981,
1872 09:54:42.531722 TX Bit5 (982~993) 12 987, Bit13 (975~988) 14 981,
1873 09:54:42.531770 TX Bit6 (982~994) 13 988, Bit14 (976~989) 14 982,
1874 09:54:42.531818 TX Bit7 (985~994) 10 989, Bit15 (980~991) 12 985,
1875 09:54:42.531866
1876 09:54:42.531914 Write Rank1 MR14 =0x2
1877 09:54:42.531961
1878 09:54:42.532009 CH=0, VrefRange= 0, VrefLevel = 2
1879 09:54:42.532057 TX Bit0 (985~999) 15 992, Bit8 (971~984) 14 977,
1880 09:54:42.532105 TX Bit1 (985~996) 12 990, Bit9 (974~988) 15 981,
1881 09:54:42.532152 TX Bit2 (985~997) 13 991, Bit10 (979~992) 14 985,
1882 09:54:42.532200 TX Bit3 (979~989) 11 984, Bit11 (973~984) 12 978,
1883 09:54:42.532248 TX Bit4 (983~997) 15 990, Bit12 (975~988) 14 981,
1884 09:54:42.532296 TX Bit5 (981~993) 13 987, Bit13 (975~988) 14 981,
1885 09:54:42.532358 TX Bit6 (980~994) 15 987, Bit14 (975~989) 15 982,
1886 09:54:42.532409 TX Bit7 (984~994) 11 989, Bit15 (979~991) 13 985,
1887 09:54:42.532458
1888 09:54:42.532505 Write Rank1 MR14 =0x4
1889 09:54:42.532552
1890 09:54:42.532599 CH=0, VrefRange= 0, VrefLevel = 4
1891 09:54:42.532647 TX Bit0 (985~999) 15 992, Bit8 (971~985) 15 978,
1892 09:54:42.532695 TX Bit1 (984~997) 14 990, Bit9 (973~989) 17 981,
1893 09:54:42.532744 TX Bit2 (985~998) 14 991, Bit10 (978~993) 16 985,
1894 09:54:42.532791 TX Bit3 (979~990) 12 984, Bit11 (973~985) 13 979,
1895 09:54:42.532839 TX Bit4 (983~997) 15 990, Bit12 (974~988) 15 981,
1896 09:54:42.532887 TX Bit5 (981~994) 14 987, Bit13 (975~988) 14 981,
1897 09:54:42.532935 TX Bit6 (980~995) 16 987, Bit14 (975~990) 16 982,
1898 09:54:42.532982 TX Bit7 (984~995) 12 989, Bit15 (978~992) 15 985,
1899 09:54:42.533030
1900 09:54:42.533077 Write Rank1 MR14 =0x6
1901 09:54:42.533125
1902 09:54:42.533172 CH=0, VrefRange= 0, VrefLevel = 6
1903 09:54:42.533220 TX Bit0 (985~1000) 16 992, Bit8 (971~986) 16 978,
1904 09:54:42.533268 TX Bit1 (983~997) 15 990, Bit9 (973~989) 17 981,
1905 09:54:42.533316 TX Bit2 (984~999) 16 991, Bit10 (978~994) 17 986,
1906 09:54:42.533363 TX Bit3 (979~992) 14 985, Bit11 (972~986) 15 979,
1907 09:54:42.533411 TX Bit4 (982~998) 17 990, Bit12 (974~988) 15 981,
1908 09:54:42.533461 TX Bit5 (980~994) 15 987, Bit13 (974~989) 16 981,
1909 09:54:42.533509 TX Bit6 (980~995) 16 987, Bit14 (975~990) 16 982,
1910 09:54:42.533556 TX Bit7 (984~995) 12 989, Bit15 (978~992) 15 985,
1911 09:54:42.533604
1912 09:54:42.533650 Write Rank1 MR14 =0x8
1913 09:54:42.533697
1914 09:54:42.533744 CH=0, VrefRange= 0, VrefLevel = 8
1915 09:54:42.533791 TX Bit0 (984~1001) 18 992, Bit8 (971~986) 16 978,
1916 09:54:42.533839 TX Bit1 (983~998) 16 990, Bit9 (973~989) 17 981,
1917 09:54:42.533887 TX Bit2 (985~999) 15 992, Bit10 (977~994) 18 985,
1918 09:54:42.533935 TX Bit3 (979~992) 14 985, Bit11 (972~986) 15 979,
1919 09:54:42.533989 TX Bit4 (983~999) 17 991, Bit12 (974~989) 16 981,
1920 09:54:42.534080 TX Bit5 (980~994) 15 987, Bit13 (974~989) 16 981,
1921 09:54:42.534128 TX Bit6 (980~996) 17 988, Bit14 (975~991) 17 983,
1922 09:54:42.534176 TX Bit7 (983~996) 14 989, Bit15 (978~993) 16 985,
1923 09:54:42.534223
1924 09:54:42.534271 Write Rank1 MR14 =0xa
1925 09:54:42.534318
1926 09:54:42.534365 CH=0, VrefRange= 0, VrefLevel = 10
1927 09:54:42.534413 TX Bit0 (984~1001) 18 992, Bit8 (970~988) 19 979,
1928 09:54:42.534461 TX Bit1 (983~999) 17 991, Bit9 (972~990) 19 981,
1929 09:54:42.534510 TX Bit2 (984~1000) 17 992, Bit10 (977~995) 19 986,
1930 09:54:42.534558 TX Bit3 (979~993) 15 986, Bit11 (971~987) 17 979,
1931 09:54:42.534606 TX Bit4 (982~999) 18 990, Bit12 (973~989) 17 981,
1932 09:54:42.534654 TX Bit5 (980~995) 16 987, Bit13 (973~990) 18 981,
1933 09:54:42.534703 TX Bit6 (980~997) 18 988, Bit14 (974~992) 19 983,
1934 09:54:42.534751 TX Bit7 (983~997) 15 990, Bit15 (977~995) 19 986,
1935 09:54:42.534800
1936 09:54:42.534847 Write Rank1 MR14 =0xc
1937 09:54:42.534895
1938 09:54:42.535127 CH=0, VrefRange= 0, VrefLevel = 12
1939 09:54:42.535183 TX Bit0 (984~1002) 19 993, Bit8 (970~988) 19 979,
1940 09:54:42.535233 TX Bit1 (983~1000) 18 991, Bit9 (972~990) 19 981,
1941 09:54:42.535282 TX Bit2 (984~1001) 18 992, Bit10 (977~995) 19 986,
1942 09:54:42.535331 TX Bit3 (978~993) 16 985, Bit11 (971~988) 18 979,
1943 09:54:42.535380 TX Bit4 (981~1000) 20 990, Bit12 (973~990) 18 981,
1944 09:54:42.761181 TX Bit5 (980~995) 16 987, Bit13 (973~990) 18 981,
1945 09:54:42.761706 TX Bit6 (980~997) 18 988, Bit14 (974~992) 19 983,
1946 09:54:42.762073 TX Bit7 (982~997) 16 989, Bit15 (977~994) 18 985,
1947 09:54:42.762390
1948 09:54:42.762682 Write Rank1 MR14 =0xe
1949 09:54:42.762968
1950 09:54:42.763247 CH=0, VrefRange= 0, VrefLevel = 14
1951 09:54:42.763650 TX Bit0 (984~1002) 19 993, Bit8 (970~988) 19 979,
1952 09:54:42.764075 TX Bit1 (983~1000) 18 991, Bit9 (972~990) 19 981,
1953 09:54:42.764372 TX Bit2 (984~1001) 18 992, Bit10 (977~995) 19 986,
1954 09:54:42.764660 TX Bit3 (978~993) 16 985, Bit11 (971~988) 18 979,
1955 09:54:42.764940 TX Bit4 (981~1000) 20 990, Bit12 (973~990) 18 981,
1956 09:54:42.765216 TX Bit5 (980~995) 16 987, Bit13 (973~990) 18 981,
1957 09:54:42.765497 TX Bit6 (980~997) 18 988, Bit14 (974~992) 19 983,
1958 09:54:42.765779 TX Bit7 (982~997) 16 989, Bit15 (977~994) 18 985,
1959 09:54:42.766099
1960 09:54:42.766380 Write Rank1 MR14 =0x10
1961 09:54:42.766654
1962 09:54:42.766924 CH=0, VrefRange= 0, VrefLevel = 16
1963 09:54:42.767199 TX Bit0 (982~1003) 22 992, Bit8 (969~989) 21 979,
1964 09:54:42.767473 TX Bit1 (982~1001) 20 991, Bit9 (972~991) 20 981,
1965 09:54:42.767745 TX Bit2 (983~1002) 20 992, Bit10 (976~996) 21 986,
1966 09:54:42.768019 TX Bit3 (978~994) 17 986, Bit11 (970~989) 20 979,
1967 09:54:42.768293 TX Bit4 (981~1001) 21 991, Bit12 (973~991) 19 982,
1968 09:54:42.768564 TX Bit5 (979~997) 19 988, Bit13 (973~991) 19 982,
1969 09:54:42.768839 TX Bit6 (980~999) 20 989, Bit14 (973~993) 21 983,
1970 09:54:42.769110 TX Bit7 (982~999) 18 990, Bit15 (976~996) 21 986,
1971 09:54:42.769385
1972 09:54:42.769653 Write Rank1 MR14 =0x12
1973 09:54:42.769919
1974 09:54:42.770228 CH=0, VrefRange= 0, VrefLevel = 18
1975 09:54:42.770504 TX Bit0 (984~1004) 21 994, Bit8 (968~989) 22 978,
1976 09:54:42.770782 TX Bit1 (981~1001) 21 991, Bit9 (971~992) 22 981,
1977 09:54:42.771062 TX Bit2 (983~1002) 20 992, Bit10 (976~996) 21 986,
1978 09:54:42.771337 TX Bit3 (978~994) 17 986, Bit11 (970~989) 20 979,
1979 09:54:42.771611 TX Bit4 (981~1001) 21 991, Bit12 (972~991) 20 981,
1980 09:54:42.771891 TX Bit5 (979~997) 19 988, Bit13 (973~991) 19 982,
1981 09:54:42.772166 TX Bit6 (980~999) 20 989, Bit14 (973~994) 22 983,
1982 09:54:42.772437 TX Bit7 (981~1000) 20 990, Bit15 (976~996) 21 986,
1983 09:54:42.772707
1984 09:54:42.772979 Write Rank1 MR14 =0x14
1985 09:54:42.773255
1986 09:54:42.773523 CH=0, VrefRange= 0, VrefLevel = 20
1987 09:54:42.773798 TX Bit0 (983~1004) 22 993, Bit8 (968~990) 23 979,
1988 09:54:42.774095 TX Bit1 (981~1002) 22 991, Bit9 (970~992) 23 981,
1989 09:54:42.774367 TX Bit2 (982~1003) 22 992, Bit10 (975~997) 23 986,
1990 09:54:42.774638 TX Bit3 (978~994) 17 986, Bit11 (970~989) 20 979,
1991 09:54:42.774909 TX Bit4 (980~1002) 23 991, Bit12 (972~991) 20 981,
1992 09:54:42.775179 TX Bit5 (979~998) 20 988, Bit13 (972~992) 21 982,
1993 09:54:42.775452 TX Bit6 (979~1000) 22 989, Bit14 (973~994) 22 983,
1994 09:54:42.775726 TX Bit7 (981~1001) 21 991, Bit15 (975~996) 22 985,
1995 09:54:42.775997
1996 09:54:42.776264 Write Rank1 MR14 =0x16
1997 09:54:42.776530
1998 09:54:42.776796 CH=0, VrefRange= 0, VrefLevel = 22
1999 09:54:42.777067 TX Bit0 (982~1005) 24 993, Bit8 (968~990) 23 979,
2000 09:54:42.777339 TX Bit1 (981~1002) 22 991, Bit9 (970~993) 24 981,
2001 09:54:42.777610 TX Bit2 (982~1003) 22 992, Bit10 (975~997) 23 986,
2002 09:54:42.777885 TX Bit3 (978~995) 18 986, Bit11 (969~990) 22 979,
2003 09:54:42.778177 TX Bit4 (980~1002) 23 991, Bit12 (971~993) 23 982,
2004 09:54:42.778453 TX Bit5 (979~998) 20 988, Bit13 (972~993) 22 982,
2005 09:54:42.778726 TX Bit6 (979~1000) 22 989, Bit14 (972~995) 24 983,
2006 09:54:42.779003 TX Bit7 (981~1001) 21 991, Bit15 (976~996) 21 986,
2007 09:54:42.779278
2008 09:54:42.779544 Write Rank1 MR14 =0x18
2009 09:54:42.779812
2010 09:54:42.780080 CH=0, VrefRange= 0, VrefLevel = 24
2011 09:54:42.780353 TX Bit0 (981~1005) 25 993, Bit8 (968~991) 24 979,
2012 09:54:42.780625 TX Bit1 (981~1003) 23 992, Bit9 (969~993) 25 981,
2013 09:54:42.780902 TX Bit2 (982~1004) 23 993, Bit10 (975~997) 23 986,
2014 09:54:42.781176 TX Bit3 (978~995) 18 986, Bit11 (969~990) 22 979,
2015 09:54:42.781450 TX Bit4 (980~1003) 24 991, Bit12 (971~992) 22 981,
2016 09:54:42.781792 TX Bit5 (979~999) 21 989, Bit13 (972~993) 22 982,
2017 09:54:42.782098 TX Bit6 (979~1001) 23 990, Bit14 (972~995) 24 983,
2018 09:54:42.782380 TX Bit7 (981~1002) 22 991, Bit15 (976~997) 22 986,
2019 09:54:42.782659
2020 09:54:42.782929 Write Rank1 MR14 =0x1a
2021 09:54:42.783200
2022 09:54:42.783468 CH=0, VrefRange= 0, VrefLevel = 26
2023 09:54:42.783763 TX Bit0 (982~1006) 25 994, Bit8 (968~991) 24 979,
2024 09:54:42.784049 TX Bit1 (980~1004) 25 992, Bit9 (969~993) 25 981,
2025 09:54:42.784323 TX Bit2 (981~1005) 25 993, Bit10 (975~998) 24 986,
2026 09:54:42.784595 TX Bit3 (977~996) 20 986, Bit11 (969~991) 23 980,
2027 09:54:42.784869 TX Bit4 (980~1004) 25 992, Bit12 (971~994) 24 982,
2028 09:54:42.785145 TX Bit5 (978~999) 22 988, Bit13 (971~993) 23 982,
2029 09:54:42.785416 TX Bit6 (979~1001) 23 990, Bit14 (971~996) 26 983,
2030 09:54:42.785687 TX Bit7 (981~1002) 22 991, Bit15 (975~997) 23 986,
2031 09:54:42.786058
2032 09:54:42.786338 Write Rank1 MR14 =0x1c
2033 09:54:42.786603
2034 09:54:42.786848 CH=0, VrefRange= 0, VrefLevel = 28
2035 09:54:42.787097 TX Bit0 (981~1006) 26 993, Bit8 (968~991) 24 979,
2036 09:54:42.787350 TX Bit1 (980~1004) 25 992, Bit9 (970~993) 24 981,
2037 09:54:42.787964 TX Bit2 (981~1005) 25 993, Bit10 (974~998) 25 986,
2038 09:54:42.788253 TX Bit3 (977~996) 20 986, Bit11 (968~991) 24 979,
2039 09:54:42.788513 TX Bit4 (980~1004) 25 992, Bit12 (970~994) 25 982,
2040 09:54:42.788766 TX Bit5 (979~1000) 22 989, Bit13 (970~994) 25 982,
2041 09:54:42.789019 TX Bit6 (979~1002) 24 990, Bit14 (971~996) 26 983,
2042 09:54:42.789270 TX Bit7 (980~1003) 24 991, Bit15 (975~997) 23 986,
2043 09:54:42.789520
2044 09:54:42.789766 Write Rank1 MR14 =0x1e
2045 09:54:42.790066
2046 09:54:42.790328 CH=0, VrefRange= 0, VrefLevel = 30
2047 09:54:42.790580 TX Bit0 (981~1006) 26 993, Bit8 (968~991) 24 979,
2048 09:54:42.790833 TX Bit1 (980~1004) 25 992, Bit9 (971~993) 23 982,
2049 09:54:42.791081 TX Bit2 (981~1005) 25 993, Bit10 (975~997) 23 986,
2050 09:54:42.791335 TX Bit3 (977~997) 21 987, Bit11 (969~992) 24 980,
2051 09:54:42.791587 TX Bit4 (980~1004) 25 992, Bit12 (971~994) 24 982,
2052 09:54:42.791890 TX Bit5 (978~1001) 24 989, Bit13 (970~993) 24 981,
2053 09:54:42.792150 TX Bit6 (979~1001) 23 990, Bit14 (971~995) 25 983,
2054 09:54:42.792417 TX Bit7 (980~1003) 24 991, Bit15 (974~997) 24 985,
2055 09:54:42.792598
2056 09:54:42.792774 Write Rank1 MR14 =0x20
2057 09:54:42.792949
2058 09:54:42.793126 CH=0, VrefRange= 0, VrefLevel = 32
2059 09:54:42.793305 TX Bit0 (981~1006) 26 993, Bit8 (968~991) 24 979,
2060 09:54:42.793489 TX Bit1 (980~1004) 25 992, Bit9 (971~993) 23 982,
2061 09:54:42.793671 TX Bit2 (981~1005) 25 993, Bit10 (975~997) 23 986,
2062 09:54:42.793850 TX Bit3 (977~997) 21 987, Bit11 (969~992) 24 980,
2063 09:54:42.794058 TX Bit4 (980~1004) 25 992, Bit12 (971~994) 24 982,
2064 09:54:42.794243 TX Bit5 (978~1001) 24 989, Bit13 (970~993) 24 981,
2065 09:54:42.794421 TX Bit6 (979~1001) 23 990, Bit14 (971~995) 25 983,
2066 09:54:42.794603 TX Bit7 (980~1003) 24 991, Bit15 (974~997) 24 985,
2067 09:54:42.794783
2068 09:54:42.794960 Write Rank1 MR14 =0x22
2069 09:54:42.795140
2070 09:54:42.795314 CH=0, VrefRange= 0, VrefLevel = 34
2071 09:54:42.795492 TX Bit0 (981~1006) 26 993, Bit8 (968~991) 24 979,
2072 09:54:42.795670 TX Bit1 (980~1004) 25 992, Bit9 (971~993) 23 982,
2073 09:54:42.795848 TX Bit2 (981~1005) 25 993, Bit10 (975~997) 23 986,
2074 09:54:42.796027 TX Bit3 (977~997) 21 987, Bit11 (969~992) 24 980,
2075 09:54:42.796205 TX Bit4 (980~1004) 25 992, Bit12 (971~994) 24 982,
2076 09:54:42.796384 TX Bit5 (978~1001) 24 989, Bit13 (970~993) 24 981,
2077 09:54:42.796565 TX Bit6 (979~1001) 23 990, Bit14 (971~995) 25 983,
2078 09:54:42.796747 TX Bit7 (980~1003) 24 991, Bit15 (974~997) 24 985,
2079 09:54:42.796924
2080 09:54:42.797099 Write Rank1 MR14 =0x24
2081 09:54:42.797273
2082 09:54:42.797445 CH=0, VrefRange= 0, VrefLevel = 36
2083 09:54:42.797580 TX Bit0 (981~1006) 26 993, Bit8 (968~991) 24 979,
2084 09:54:42.797725 TX Bit1 (980~1004) 25 992, Bit9 (971~993) 23 982,
2085 09:54:42.797965 TX Bit2 (981~1005) 25 993, Bit10 (975~997) 23 986,
2086 09:54:42.798153 TX Bit3 (977~997) 21 987, Bit11 (969~992) 24 980,
2087 09:54:42.798290 TX Bit4 (980~1004) 25 992, Bit12 (971~994) 24 982,
2088 09:54:42.798428 TX Bit5 (978~1001) 24 989, Bit13 (970~993) 24 981,
2089 09:54:42.798562 TX Bit6 (979~1001) 23 990, Bit14 (971~995) 25 983,
2090 09:54:42.798698 TX Bit7 (980~1003) 24 991, Bit15 (974~997) 24 985,
2091 09:54:42.798832
2092 09:54:42.798965
2093 09:54:42.799096 TX Vref found, early break! 354< 364
2094 09:54:42.799232 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =844/100 ps
2095 09:54:42.799365 u1DelayCellOfst[0]=6 cells (6 PI)
2096 09:54:42.799499 u1DelayCellOfst[1]=5 cells (5 PI)
2097 09:54:42.799635 u1DelayCellOfst[2]=6 cells (6 PI)
2098 09:54:42.799769 u1DelayCellOfst[3]=0 cells (0 PI)
2099 09:54:42.799902 u1DelayCellOfst[4]=5 cells (5 PI)
2100 09:54:42.800035 u1DelayCellOfst[5]=2 cells (2 PI)
2101 09:54:42.800171 u1DelayCellOfst[6]=3 cells (3 PI)
2102 09:54:42.800303 u1DelayCellOfst[7]=4 cells (4 PI)
2103 09:54:42.800437 Byte0, DQ PI dly=987, DQM PI dly= 990
2104 09:54:42.800571 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
2105 09:54:42.800727
2106 09:54:42.800869 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
2107 09:54:42.801006
2108 09:54:42.801138 u1DelayCellOfst[8]=0 cells (0 PI)
2109 09:54:42.801272 u1DelayCellOfst[9]=3 cells (3 PI)
2110 09:54:42.801405 u1DelayCellOfst[10]=8 cells (7 PI)
2111 09:54:42.801539 u1DelayCellOfst[11]=1 cells (1 PI)
2112 09:54:42.801672 u1DelayCellOfst[12]=3 cells (3 PI)
2113 09:54:42.801805 u1DelayCellOfst[13]=2 cells (2 PI)
2114 09:54:42.801938 u1DelayCellOfst[14]=4 cells (4 PI)
2115 09:54:42.802086 u1DelayCellOfst[15]=6 cells (6 PI)
2116 09:54:42.802221 Byte1, DQ PI dly=979, DQM PI dly= 982
2117 09:54:42.802355 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2118 09:54:42.802484
2119 09:54:42.802591 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2120 09:54:42.802700
2121 09:54:42.802806 Write Rank1 MR14 =0x1e
2122 09:54:42.802913
2123 09:54:42.803019 Final TX Range 0 Vref 30
2124 09:54:42.803125
2125 09:54:42.803233 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2126 09:54:42.803343
2127 09:54:42.803450 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2128 09:54:42.803559 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2129 09:54:42.803669 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2130 09:54:42.803777 Write Rank1 MR3 =0xb0
2131 09:54:42.803882 DramC Write-DBI on
2132 09:54:42.803986 ==
2133 09:54:42.804092 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2134 09:54:42.804201 fsp= 1, odt_onoff= 1, Byte mode= 0
2135 09:54:42.804308 ==
2136 09:54:42.804414 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2137 09:54:42.804521
2138 09:54:42.804627 Begin, DQ Scan Range 702~766
2139 09:54:42.804735
2140 09:54:42.804840
2141 09:54:42.804944 TX Vref Scan disable
2142 09:54:42.805051 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2143 09:54:42.805161 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2144 09:54:42.805272 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2145 09:54:42.805382 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2146 09:54:42.805492 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2147 09:54:42.805600 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2148 09:54:42.805950 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2149 09:54:42.806087 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2150 09:54:42.806202 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2151 09:54:42.806313 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2152 09:54:42.806424 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2153 09:54:42.806536 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2154 09:54:42.806648 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2155 09:54:42.806760 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2156 09:54:42.806869 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2157 09:54:42.806979 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2158 09:54:42.807089 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2159 09:54:42.807199 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2160 09:54:42.807307 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2161 09:54:42.807424 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
2162 09:54:42.807514 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
2163 09:54:42.807606 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
2164 09:54:42.807698 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2165 09:54:42.807789 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2166 09:54:42.807880 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2167 09:54:42.807971 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2168 09:54:42.808062 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2169 09:54:42.808153 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2170 09:54:42.808245 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
2171 09:54:42.808335 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
2172 09:54:42.808427 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
2173 09:54:42.808518 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
2174 09:54:42.808609 750 |2 6 46|[0] xxxxxxxx xxxxxxxx [MSB]
2175 09:54:42.808700 Byte0, DQ PI dly=736, DQM PI dly= 736
2176 09:54:42.808790 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 32)
2177 09:54:42.808880
2178 09:54:42.808969 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 32)
2179 09:54:42.809058
2180 09:54:42.809145 Byte1, DQ PI dly=727, DQM PI dly= 727
2181 09:54:42.809235 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 23)
2182 09:54:42.809326
2183 09:54:42.809414 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 23)
2184 09:54:42.809505
2185 09:54:42.809595 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2186 09:54:42.809687 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2187 09:54:42.809779 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2188 09:54:42.809870 Write Rank1 MR3 =0x30
2189 09:54:42.809960 DramC Write-DBI off
2190 09:54:42.810059
2191 09:54:42.810149 [DATLAT]
2192 09:54:42.810237 Freq=1600, CH0 RK1, use_rxtx_scan=0
2193 09:54:42.810328
2194 09:54:42.810417 DATLAT Default: 0x10
2195 09:54:42.810508 7, 0xFFFF, sum=0
2196 09:54:42.810599 8, 0xFFFF, sum=0
2197 09:54:42.810690 9, 0xFFFF, sum=0
2198 09:54:42.810782 10, 0xFFFF, sum=0
2199 09:54:42.810871 11, 0xFFFF, sum=0
2200 09:54:42.810961 12, 0xFFFF, sum=0
2201 09:54:42.811051 13, 0xFFFF, sum=0
2202 09:54:42.811141 14, 0x0, sum=1
2203 09:54:42.811231 15, 0x0, sum=2
2204 09:54:42.811321 16, 0x0, sum=3
2205 09:54:42.811411 17, 0x0, sum=4
2206 09:54:42.811501 pattern=2 first_step=14 total pass=5 best_step=16
2207 09:54:42.811590 ==
2208 09:54:42.811681 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2209 09:54:42.811771 fsp= 1, odt_onoff= 1, Byte mode= 0
2210 09:54:42.811862 ==
2211 09:54:42.811951 Start DQ dly to find pass range UseTestEngine =1
2212 09:54:42.812040 x-axis: bit #, y-axis: DQ dly (-127~63)
2213 09:54:42.812130 RX Vref Scan = 0
2214 09:54:42.812217 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2215 09:54:42.812308 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2216 09:54:42.812412 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2217 09:54:42.812490 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2218 09:54:42.812569 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2219 09:54:42.812648 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2220 09:54:42.812725 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2221 09:54:42.812803 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2222 09:54:42.812880 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2223 09:54:42.812958 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2224 09:54:42.813037 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2225 09:54:42.813115 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2226 09:54:42.813194 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2227 09:54:42.813272 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2228 09:54:42.813349 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2229 09:54:42.813426 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2230 09:54:42.813504 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2231 09:54:42.813581 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2232 09:54:42.813660 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2233 09:54:42.813737 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2234 09:54:42.813814 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2235 09:54:42.813892 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2236 09:54:42.813970 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2237 09:54:42.814056 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2238 09:54:42.814134 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2239 09:54:42.814213 -1, [0] xxxxxxxx xxxxxxxx [MSB]
2240 09:54:42.814292 0, [0] xxxxxxxx xxxxxxxx [MSB]
2241 09:54:42.814370 1, [0] xxxoxxxx xxxxxxxx [MSB]
2242 09:54:42.814449 2, [0] xxxoxxxx xxxxxxxx [MSB]
2243 09:54:42.814538 3, [0] xxxoxxxx oxxxxxxx [MSB]
2244 09:54:42.814619 4, [0] xxxoxoxx oxxoxxxx [MSB]
2245 09:54:42.814699 5, [0] xxxoxoox oxxoxxxx [MSB]
2246 09:54:42.814778 6, [0] xxxoxoox ooxooxxx [MSB]
2247 09:54:42.814856 7, [0] xxxoxooo ooxooxxx [MSB]
2248 09:54:42.814933 8, [0] xoxoxooo ooxoooox [MSB]
2249 09:54:42.815010 9, [0] xoxoxooo ooxoooox [MSB]
2250 09:54:42.815087 10, [0] oooooooo ooxooooo [MSB]
2251 09:54:42.815166 11, [0] oooooooo ooxooooo [MSB]
2252 09:54:42.815245 33, [0] oooxoooo xooxoooo [MSB]
2253 09:54:42.815323 34, [0] oooxoooo xooxoooo [MSB]
2254 09:54:42.815401 35, [0] oooxoxoo xxoxoxoo [MSB]
2255 09:54:42.815479 36, [0] oooxoxxo xxoxoxoo [MSB]
2256 09:54:42.815557 37, [0] oooxoxxo xxoxxxoo [MSB]
2257 09:54:42.815635 38, [0] oooxoxxx xxoxxxxo [MSB]
2258 09:54:42.815711 39, [0] oooxxxxx xxoxxxxx [MSB]
2259 09:54:42.815790 40, [0] xxxxxxxx xxoxxxxx [MSB]
2260 09:54:42.815867 41, [0] xxxxxxxx xxoxxxxx [MSB]
2261 09:54:42.815946 42, [0] xxxxxxxx xxxxxxxx [MSB]
2262 09:54:42.816023 iDelay=42, Bit 0, Center 24 (10 ~ 39) 30
2263 09:54:42.816100 iDelay=42, Bit 1, Center 23 (8 ~ 39) 32
2264 09:54:42.816176 iDelay=42, Bit 2, Center 24 (10 ~ 39) 30
2265 09:54:42.816254 iDelay=42, Bit 3, Center 16 (1 ~ 32) 32
2266 09:54:42.816331 iDelay=42, Bit 4, Center 24 (10 ~ 38) 29
2267 09:54:42.816408 iDelay=42, Bit 5, Center 19 (4 ~ 34) 31
2268 09:54:42.816485 iDelay=42, Bit 6, Center 20 (5 ~ 35) 31
2269 09:54:42.816808 iDelay=42, Bit 7, Center 22 (7 ~ 37) 31
2270 09:54:42.816906 iDelay=42, Bit 8, Center 17 (3 ~ 32) 30
2271 09:54:42.816989 iDelay=42, Bit 9, Center 20 (6 ~ 34) 29
2272 09:54:42.817067 iDelay=42, Bit 10, Center 26 (12 ~ 41) 30
2273 09:54:42.817145 iDelay=42, Bit 11, Center 18 (4 ~ 32) 29
2274 09:54:42.817225 iDelay=42, Bit 12, Center 21 (6 ~ 36) 31
2275 09:54:42.817303 iDelay=42, Bit 13, Center 21 (8 ~ 34) 27
2276 09:54:42.817380 iDelay=42, Bit 14, Center 22 (8 ~ 37) 30
2277 09:54:42.817464 iDelay=42, Bit 15, Center 24 (10 ~ 38) 29
2278 09:54:42.817533 ==
2279 09:54:42.817601 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2280 09:54:42.817670 fsp= 1, odt_onoff= 1, Byte mode= 0
2281 09:54:42.817738 ==
2282 09:54:42.817805 DQS Delay:
2283 09:54:42.817873 DQS0 = 0, DQS1 = 0
2284 09:54:42.817940 DQM Delay:
2285 09:54:42.818019 DQM0 = 21, DQM1 = 21
2286 09:54:42.818089 DQ Delay:
2287 09:54:42.818157 DQ0 =24, DQ1 =23, DQ2 =24, DQ3 =16
2288 09:54:42.818225 DQ4 =24, DQ5 =19, DQ6 =20, DQ7 =22
2289 09:54:42.818293 DQ8 =17, DQ9 =20, DQ10 =26, DQ11 =18
2290 09:54:42.818362 DQ12 =21, DQ13 =21, DQ14 =22, DQ15 =24
2291 09:54:42.818429
2292 09:54:42.818496
2293 09:54:42.818563
2294 09:54:42.818630 [DramC_TX_OE_Calibration] TA2
2295 09:54:42.818698 Original DQ_B0 (3 6) =30, OEN = 27
2296 09:54:42.818765 Original DQ_B1 (3 6) =30, OEN = 27
2297 09:54:42.818832 23, 0x0, End_B0=23 End_B1=23
2298 09:54:42.818902 24, 0x0, End_B0=24 End_B1=24
2299 09:54:42.818970 25, 0x0, End_B0=25 End_B1=25
2300 09:54:42.819038 26, 0x0, End_B0=26 End_B1=26
2301 09:54:42.819107 27, 0x0, End_B0=27 End_B1=27
2302 09:54:42.819176 28, 0x0, End_B0=28 End_B1=28
2303 09:54:42.819243 29, 0x0, End_B0=29 End_B1=29
2304 09:54:42.819311 30, 0x0, End_B0=30 End_B1=30
2305 09:54:42.819381 31, 0xFFFF, End_B0=30 End_B1=30
2306 09:54:42.819449 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2307 09:54:42.819518 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2308 09:54:42.819586
2309 09:54:42.819653
2310 09:54:42.819719 Write Rank1 MR23 =0x3f
2311 09:54:42.819785 [DQSOSC]
2312 09:54:42.819852 [DQSOSCAuto] RK1, (LSB)MR18= 0xb6b6, (MSB)MR19= 0x202, tDQSOscB0 = 453 ps tDQSOscB1 = 453 ps
2313 09:54:42.819922 CH0_RK1: MR19=0x202, MR18=0xB6B6, DQSOSC=453, MR23=63, INC=11, DEC=17
2314 09:54:42.819990 Write Rank1 MR23 =0x3f
2315 09:54:42.820057 [DQSOSC]
2316 09:54:42.820127 [DQSOSCAuto] RK1, (LSB)MR18= 0xb6b6, (MSB)MR19= 0x202, tDQSOscB0 = 453 ps tDQSOscB1 = 453 ps
2317 09:54:42.820196 CH0 RK1: MR19=202, MR18=B6B6
2318 09:54:42.820266 [RxdqsGatingPostProcess] freq 1600
2319 09:54:42.820333 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2320 09:54:42.820402 Rank: 0
2321 09:54:42.820470 best DQS0 dly(2T, 0.5T) = (2, 6)
2322 09:54:42.820537 best DQS1 dly(2T, 0.5T) = (2, 6)
2323 09:54:42.820606 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2324 09:54:42.820673 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2325 09:54:42.820740 Rank: 1
2326 09:54:42.820806 best DQS0 dly(2T, 0.5T) = (2, 6)
2327 09:54:42.820873 best DQS1 dly(2T, 0.5T) = (2, 6)
2328 09:54:42.820940 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2329 09:54:42.821006 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2330 09:54:42.821073 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2331 09:54:42.821141 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2332 09:54:42.821208 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2333 09:54:42.821276 Write Rank0 MR13 =0x59
2334 09:54:42.821343 ==
2335 09:54:42.821410 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2336 09:54:42.821477 fsp= 1, odt_onoff= 1, Byte mode= 0
2337 09:54:42.821546 ==
2338 09:54:42.821612 === u2Vref_new: 0x56 --> 0x3a
2339 09:54:42.821679 === u2Vref_new: 0x58 --> 0x58
2340 09:54:42.821746 === u2Vref_new: 0x5a --> 0x5a
2341 09:54:42.821813 === u2Vref_new: 0x5c --> 0x78
2342 09:54:42.821879 === u2Vref_new: 0x5e --> 0x7a
2343 09:54:42.821945 === u2Vref_new: 0x60 --> 0x90
2344 09:54:42.822037 [CA 0] Center 38 (14~63) winsize 50
2345 09:54:42.822144 [CA 1] Center 37 (12~63) winsize 52
2346 09:54:42.822252 [CA 2] Center 35 (7~63) winsize 57
2347 09:54:42.822335 [CA 3] Center 35 (7~63) winsize 57
2348 09:54:42.822415 [CA 4] Center 34 (5~63) winsize 59
2349 09:54:42.822476 [CA 5] Center 28 (-1~57) winsize 59
2350 09:54:42.822536
2351 09:54:42.822595 [CATrainingPosCal] consider 1 rank data
2352 09:54:42.822654 u2DelayCellTimex100 = 844/100 ps
2353 09:54:42.822714 CA0 delay=38 (14~63),Diff = 10 PI (11 cell)
2354 09:54:42.822775 CA1 delay=37 (12~63),Diff = 9 PI (10 cell)
2355 09:54:42.822835 CA2 delay=35 (7~63),Diff = 7 PI (8 cell)
2356 09:54:42.822894 CA3 delay=35 (7~63),Diff = 7 PI (8 cell)
2357 09:54:42.822954 CA4 delay=34 (5~63),Diff = 6 PI (6 cell)
2358 09:54:42.823014 CA5 delay=28 (-1~57),Diff = 0 PI (0 cell)
2359 09:54:42.823074
2360 09:54:42.823133 CA PerBit enable=1, Macro0, CA PI delay=28
2361 09:54:42.823192 === u2Vref_new: 0x5c --> 0x78
2362 09:54:42.823252
2363 09:54:42.823311 Vref(ca) range 1: 28
2364 09:54:42.823370
2365 09:54:42.823428 CS Dly= 10 (41-0-32)
2366 09:54:42.823488 Write Rank0 MR13 =0xd8
2367 09:54:42.823547 Write Rank0 MR13 =0xd8
2368 09:54:42.823607 Write Rank0 MR12 =0x5c
2369 09:54:42.823665 Write Rank1 MR13 =0x59
2370 09:54:42.823723 ==
2371 09:54:42.823784 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2372 09:54:42.823844 fsp= 1, odt_onoff= 1, Byte mode= 0
2373 09:54:42.823904 ==
2374 09:54:42.823962 === u2Vref_new: 0x56 --> 0x3a
2375 09:54:42.824021 === u2Vref_new: 0x58 --> 0x58
2376 09:54:42.824081 === u2Vref_new: 0x5a --> 0x5a
2377 09:54:42.824141 === u2Vref_new: 0x5c --> 0x78
2378 09:54:42.824200 === u2Vref_new: 0x5e --> 0x7a
2379 09:54:42.824260 === u2Vref_new: 0x60 --> 0x90
2380 09:54:42.824320 [CA 0] Center 37 (11~63) winsize 53
2381 09:54:42.824379 [CA 1] Center 37 (11~63) winsize 53
2382 09:54:42.824438 [CA 2] Center 34 (6~63) winsize 58
2383 09:54:42.824497 [CA 3] Center 35 (7~63) winsize 57
2384 09:54:42.824556 [CA 4] Center 34 (5~63) winsize 59
2385 09:54:42.824615 [CA 5] Center 28 (-1~57) winsize 59
2386 09:54:42.824675
2387 09:54:42.824734 [CATrainingPosCal] consider 2 rank data
2388 09:54:42.824795 u2DelayCellTimex100 = 844/100 ps
2389 09:54:42.824855 CA0 delay=38 (14~63),Diff = 10 PI (11 cell)
2390 09:54:42.824915 CA1 delay=37 (12~63),Diff = 9 PI (10 cell)
2391 09:54:42.824976 CA2 delay=35 (7~63),Diff = 7 PI (8 cell)
2392 09:54:42.825036 CA3 delay=35 (7~63),Diff = 7 PI (8 cell)
2393 09:54:42.825095 CA4 delay=34 (5~63),Diff = 6 PI (6 cell)
2394 09:54:42.825154 CA5 delay=28 (-1~57),Diff = 0 PI (0 cell)
2395 09:54:42.825214
2396 09:54:42.825272 CA PerBit enable=1, Macro0, CA PI delay=28
2397 09:54:42.825529 === u2Vref_new: 0x5c --> 0x78
2398 09:54:42.825599
2399 09:54:42.825660 Vref(ca) range 1: 28
2400 09:54:42.825719
2401 09:54:42.825778 CS Dly= 10 (41-0-32)
2402 09:54:42.825838 Write Rank1 MR13 =0xd8
2403 09:54:42.825898 Write Rank1 MR13 =0xd8
2404 09:54:42.825959 Write Rank1 MR12 =0x5c
2405 09:54:42.826030 [RankSwap] Rank num 2, (Multi 1), Rank 0
2406 09:54:42.826091 Write Rank0 MR2 =0xad
2407 09:54:42.826151 [Write Leveling]
2408 09:54:42.826211 delay byte0 byte1 byte2 byte3
2409 09:54:42.826271
2410 09:54:42.826329 10 0 0
2411 09:54:42.826389 11 0 0
2412 09:54:42.826451 12 0 0
2413 09:54:42.826512 13 0 0
2414 09:54:42.826572 14 0 0
2415 09:54:42.826632 15 0 0
2416 09:54:42.826691 16 0 0
2417 09:54:42.826750 17 0 0
2418 09:54:42.826810 18 0 0
2419 09:54:42.826870 19 0 0
2420 09:54:42.826930 20 0 0
2421 09:54:42.826991 21 0 0
2422 09:54:42.827051 22 0 0
2423 09:54:42.827110 23 0 0
2424 09:54:42.827170 24 0 0
2425 09:54:42.827230 25 0 0
2426 09:54:42.827290 26 0 0
2427 09:54:42.827349 27 0 0
2428 09:54:42.827421 28 0 0
2429 09:54:42.827475 29 0 0
2430 09:54:42.827528 30 0 0
2431 09:54:42.827580 31 0 ff
2432 09:54:42.827634 32 0 ff
2433 09:54:42.827687 33 0 ff
2434 09:54:42.827741 34 ff ff
2435 09:54:42.827795 35 ff ff
2436 09:54:42.827849 36 ff ff
2437 09:54:42.827904 37 ff ff
2438 09:54:42.827957 38 ff ff
2439 09:54:42.828011 39 ff ff
2440 09:54:42.828065 40 ff ff
2441 09:54:42.828118 pass bytecount = 0xff (0xff: all bytes pass)
2442 09:54:42.828172
2443 09:54:42.828225 DQS0 dly: 34
2444 09:54:42.828277 DQS1 dly: 31
2445 09:54:42.828330 Write Rank0 MR2 =0x2d
2446 09:54:42.828383 [RankSwap] Rank num 2, (Multi 1), Rank 0
2447 09:54:42.828436 Write Rank0 MR1 =0xd6
2448 09:54:42.828489 [Gating]
2449 09:54:42.828541 ==
2450 09:54:42.828593 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2451 09:54:42.828647 fsp= 1, odt_onoff= 1, Byte mode= 0
2452 09:54:42.828700 ==
2453 09:54:42.828754 3 1 0 |3534 605 |(11 11)(11 11) |(0 0)(0 0)| 0
2454 09:54:42.828810 3 1 4 |3534 2424 |(11 11)(11 11) |(0 0)(1 1)| 0
2455 09:54:42.828865 3 1 8 |3534 2f2e |(11 11)(11 11) |(0 0)(0 0)| 0
2456 09:54:42.828920 3 1 12 |3534 2f2e |(11 11)(11 11) |(0 0)(0 0)| 0
2457 09:54:42.828975 3 1 16 |3534 302f |(11 11)(11 11) |(1 1)(0 0)| 0
2458 09:54:42.829030 3 1 20 |3534 2d2c |(11 11)(11 11) |(1 1)(0 0)| 0
2459 09:54:42.829084 3 1 24 |3534 2020 |(11 11)(11 11) |(1 1)(1 1)| 0
2460 09:54:42.829138 3 1 28 |3534 2e2d |(11 11)(11 11) |(0 1)(1 1)| 0
2461 09:54:42.829193 3 2 0 |3534 2c2c |(11 11)(0 0) |(0 1)(1 0)| 0
2462 09:54:42.829248 3 2 4 |3534 2d2c |(11 11)(11 11) |(0 1)(1 0)| 0
2463 09:54:42.829303 3 2 8 |3534 2d2c |(11 11)(11 11) |(0 1)(1 0)| 0
2464 09:54:42.829357 3 2 12 |3534 2423 |(11 11)(11 11) |(0 1)(0 0)| 0
2465 09:54:42.829411 3 2 16 |3534 1b1b |(11 11)(11 11) |(0 1)(1 0)| 0
2466 09:54:42.829466 3 2 20 |504 2e2e |(11 11)(10 10) |(1 1)(1 0)| 0
2467 09:54:42.829520 3 2 24 |201 2121 |(11 11)(11 11) |(1 1)(1 0)| 0
2468 09:54:42.829575 3 2 28 |3d3d 302 |(11 11)(11 11) |(1 1)(0 0)| 0
2469 09:54:42.829629 3 3 0 |3d3d 1110 |(11 11)(11 11) |(1 1)(1 1)| 0
2470 09:54:42.829684 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2471 09:54:42.829739 3 3 8 |3d3d 3635 |(11 11)(11 11) |(1 1)(0 0)| 0
2472 09:54:42.829793 3 3 12 |3d3d 3535 |(11 11)(11 11) |(1 1)(1 1)| 0
2473 09:54:42.829848 3 3 16 |3d3d 3635 |(11 11)(11 11) |(1 1)(1 1)| 0
2474 09:54:42.829902 3 3 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2475 09:54:42.829970 [Byte 1] Lead/lag Transition tap number (1)
2476 09:54:42.831738 3 3 24 |707 3535 |(11 11)(11 11) |(1 1)(0 0)| 0
2477 09:54:42.838342 3 3 28 |3534 3231 |(11 11)(11 11) |(1 1)(1 1)| 0
2478 09:54:42.841821 [Byte 0] Lead/lag falling Transition (3, 3, 28)
2479 09:54:42.845233 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2480 09:54:42.852030 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2481 09:54:42.854806 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2482 09:54:42.858518 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2483 09:54:42.864601 3 4 16 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
2484 09:54:42.868245 3 4 20 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2485 09:54:42.871946 3 4 24 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2486 09:54:42.878363 3 4 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2487 09:54:42.881827 3 5 0 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
2488 09:54:42.885083 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2489 09:54:42.888463 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2490 09:54:42.894979 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2491 09:54:42.898115 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2492 09:54:42.902374 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2493 09:54:42.909025 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2494 09:54:42.911804 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2495 09:54:42.915000 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2496 09:54:42.921672 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2497 09:54:42.925549 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2498 09:54:42.928649 [Byte 0] Lead/lag falling Transition (3, 6, 8)
2499 09:54:42.931569 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2500 09:54:42.938715 3 6 16 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2501 09:54:42.942021 [Byte 0] Lead/lag Transition tap number (3)
2502 09:54:42.945236 3 6 20 |202 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2503 09:54:42.952126 [Byte 1] Lead/lag falling Transition (3, 6, 20)
2504 09:54:42.954659 3 6 24 |808 3d3d |(1 1)(11 11) |(0 0)(1 0)| 0
2505 09:54:42.958584 [Byte 1] Lead/lag Transition tap number (2)
2506 09:54:42.961474 3 6 28 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
2507 09:54:42.964817 [Byte 0]First pass (3, 6, 28)
2508 09:54:42.968274 3 7 0 |4646 606 |(0 0)(11 11) |(0 0)(0 0)| 0
2509 09:54:42.971318 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2510 09:54:42.974804 [Byte 1]First pass (3, 7, 4)
2511 09:54:42.978204 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2512 09:54:42.984702 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2513 09:54:42.988379 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2514 09:54:42.991581 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2515 09:54:42.994325 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2516 09:54:43.001389 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2517 09:54:43.004755 4 0 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2518 09:54:43.007958 4 0 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2519 09:54:43.011454 All bytes gating window > 1UI, Early break!
2520 09:54:43.011964
2521 09:54:43.014221 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 14)
2522 09:54:43.014650
2523 09:54:43.017694 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 24)
2524 09:54:43.018260
2525 09:54:43.018598
2526 09:54:43.021065
2527 09:54:43.024365 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 14)
2528 09:54:43.024875
2529 09:54:43.027673 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 24)
2530 09:54:43.028099
2531 09:54:43.028445
2532 09:54:43.030814 Write Rank0 MR1 =0x56
2533 09:54:43.031374
2534 09:54:43.034057 best RODT dly(2T, 0.5T) = (2, 3)
2535 09:54:43.034585
2536 09:54:43.034931 best RODT dly(2T, 0.5T) = (2, 3)
2537 09:54:43.037942 ==
2538 09:54:43.040996 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2539 09:54:43.044613 fsp= 1, odt_onoff= 1, Byte mode= 0
2540 09:54:43.045123 ==
2541 09:54:43.047744 Start DQ dly to find pass range UseTestEngine =0
2542 09:54:43.050991 x-axis: bit #, y-axis: DQ dly (-127~63)
2543 09:54:43.053948 RX Vref Scan = 0
2544 09:54:43.057755 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2545 09:54:43.061310 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2546 09:54:43.064510 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2547 09:54:43.064911 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2548 09:54:43.068548 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2549 09:54:43.071545 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2550 09:54:43.074593 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2551 09:54:43.077423 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2552 09:54:43.080912 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2553 09:54:43.084126 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2554 09:54:43.087139 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2555 09:54:43.090796 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2556 09:54:43.091186 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2557 09:54:43.094477 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2558 09:54:43.097307 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2559 09:54:43.100881 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2560 09:54:43.104150 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2561 09:54:43.107033 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2562 09:54:43.110938 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2563 09:54:43.114358 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2564 09:54:43.114873 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2565 09:54:43.118013 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2566 09:54:43.120468 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2567 09:54:43.124593 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2568 09:54:43.127102 -2, [0] xxxxxxxx xxxxxxxx [MSB]
2569 09:54:43.130691 -1, [0] xxxxxxxx xxxxxxxo [MSB]
2570 09:54:43.131203 0, [0] xxxxxxxx xxxxxxxo [MSB]
2571 09:54:43.133890 1, [0] xxxxxxxx xxxxxxxo [MSB]
2572 09:54:43.137482 2, [0] xxxxxxxx xoxxxxxo [MSB]
2573 09:54:43.141245 3, [0] xxxoxxxx ooxxxxxo [MSB]
2574 09:54:43.144005 4, [0] xxxoxxxx ooxxxxxo [MSB]
2575 09:54:43.147803 5, [0] xxxoxxxx ooxxxxxo [MSB]
2576 09:54:43.148355 6, [0] xoooxxxo ooxxxxxo [MSB]
2577 09:54:43.150582 7, [0] oooooxoo oooooooo [MSB]
2578 09:54:43.154154 8, [0] oooooxoo oooooooo [MSB]
2579 09:54:43.157436 31, [0] oooooooo ooooooox [MSB]
2580 09:54:43.160381 32, [0] oooooooo ooooooox [MSB]
2581 09:54:43.163796 33, [0] oooooooo ooooooox [MSB]
2582 09:54:43.167040 34, [0] oooooooo oxooooox [MSB]
2583 09:54:43.167477 35, [0] ooxxoooo xxooooox [MSB]
2584 09:54:43.170329 36, [0] ooxxoooo xxooooox [MSB]
2585 09:54:43.173944 37, [0] ooxxxooo xxxoooox [MSB]
2586 09:54:43.177224 38, [0] ooxxxooo xxxxoxxx [MSB]
2587 09:54:43.180741 39, [0] oxxxxxox xxxxxxxx [MSB]
2588 09:54:43.183722 40, [0] oxxxxxox xxxxxxxx [MSB]
2589 09:54:43.184161 41, [0] xxxxxxxx xxxxxxxx [MSB]
2590 09:54:43.190528 iDelay=41, Bit 0, Center 23 (7 ~ 40) 34
2591 09:54:43.193823 iDelay=41, Bit 1, Center 22 (6 ~ 38) 33
2592 09:54:43.197474 iDelay=41, Bit 2, Center 20 (6 ~ 34) 29
2593 09:54:43.200481 iDelay=41, Bit 3, Center 18 (3 ~ 34) 32
2594 09:54:43.203756 iDelay=41, Bit 4, Center 21 (7 ~ 36) 30
2595 09:54:43.207101 iDelay=41, Bit 5, Center 23 (9 ~ 38) 30
2596 09:54:43.210534 iDelay=41, Bit 6, Center 23 (7 ~ 40) 34
2597 09:54:43.214243 iDelay=41, Bit 7, Center 22 (6 ~ 38) 33
2598 09:54:43.217754 iDelay=41, Bit 8, Center 18 (3 ~ 34) 32
2599 09:54:43.221269 iDelay=41, Bit 9, Center 17 (2 ~ 33) 32
2600 09:54:43.223963 iDelay=41, Bit 10, Center 21 (7 ~ 36) 30
2601 09:54:43.227221 iDelay=41, Bit 11, Center 22 (7 ~ 37) 31
2602 09:54:43.230517 iDelay=41, Bit 12, Center 22 (7 ~ 38) 32
2603 09:54:43.233827 iDelay=41, Bit 13, Center 22 (7 ~ 37) 31
2604 09:54:43.240564 iDelay=41, Bit 14, Center 22 (7 ~ 37) 31
2605 09:54:43.243988 iDelay=41, Bit 15, Center 14 (-1 ~ 30) 32
2606 09:54:43.244498 ==
2607 09:54:43.247273 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2608 09:54:43.250799 fsp= 1, odt_onoff= 1, Byte mode= 0
2609 09:54:43.251310 ==
2610 09:54:43.253751 DQS Delay:
2611 09:54:43.254207 DQS0 = 0, DQS1 = 0
2612 09:54:43.254545 DQM Delay:
2613 09:54:43.257324 DQM0 = 21, DQM1 = 19
2614 09:54:43.257832 DQ Delay:
2615 09:54:43.260376 DQ0 =23, DQ1 =22, DQ2 =20, DQ3 =18
2616 09:54:43.263775 DQ4 =21, DQ5 =23, DQ6 =23, DQ7 =22
2617 09:54:43.268014 DQ8 =18, DQ9 =17, DQ10 =21, DQ11 =22
2618 09:54:43.270768 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =14
2619 09:54:43.271282
2620 09:54:43.271613
2621 09:54:43.273492 DramC Write-DBI off
2622 09:54:43.274030 ==
2623 09:54:43.277171 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2624 09:54:43.280690 fsp= 1, odt_onoff= 1, Byte mode= 0
2625 09:54:43.281208 ==
2626 09:54:43.286778 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2627 09:54:43.287353
2628 09:54:43.290379 Begin, DQ Scan Range 927~1183
2629 09:54:43.290896
2630 09:54:43.291227
2631 09:54:43.291538 TX Vref Scan disable
2632 09:54:43.293764 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2633 09:54:43.297408 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2634 09:54:43.300306 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2635 09:54:43.306978 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2636 09:54:43.310161 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2637 09:54:43.313841 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2638 09:54:43.317516 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2639 09:54:43.320178 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2640 09:54:43.323616 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2641 09:54:43.326870 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2642 09:54:43.330283 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2643 09:54:43.333549 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2644 09:54:43.337292 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2645 09:54:43.340495 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2646 09:54:43.343472 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2647 09:54:43.346885 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2648 09:54:43.350465 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2649 09:54:43.353777 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2650 09:54:43.356402 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2651 09:54:43.363986 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2652 09:54:43.366463 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2653 09:54:43.370373 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2654 09:54:43.373138 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2655 09:54:43.377021 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2656 09:54:43.380484 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2657 09:54:43.383438 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2658 09:54:43.387498 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2659 09:54:43.389525 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2660 09:54:43.393511 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2661 09:54:43.396297 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2662 09:54:43.399579 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2663 09:54:43.404031 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2664 09:54:43.406303 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2665 09:54:43.409768 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2666 09:54:43.412986 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2667 09:54:43.420137 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2668 09:54:43.422802 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2669 09:54:43.426231 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2670 09:54:43.429715 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2671 09:54:43.432884 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2672 09:54:43.436344 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2673 09:54:43.439699 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
2674 09:54:43.442557 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
2675 09:54:43.446356 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
2676 09:54:43.449341 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
2677 09:54:43.453318 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
2678 09:54:43.456177 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
2679 09:54:43.459208 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
2680 09:54:43.463040 975 |3 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
2681 09:54:43.466122 976 |3 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
2682 09:54:43.469854 977 |3 6 17|[0] xxxxxxxx ooxxxxxo [MSB]
2683 09:54:43.472711 978 |3 6 18|[0] xxxxxxxx ooxxxxxo [MSB]
2684 09:54:43.479405 979 |3 6 19|[0] xxxxxxxx ooxxxxoo [MSB]
2685 09:54:43.482562 980 |3 6 20|[0] xxxxxxxx ooooxxoo [MSB]
2686 09:54:43.485664 981 |3 6 21|[0] xxxxxxxx oooooxoo [MSB]
2687 09:54:43.489164 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
2688 09:54:43.492655 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
2689 09:54:43.495933 984 |3 6 24|[0] xooooxoo oooooooo [MSB]
2690 09:54:43.499140 994 |3 6 34|[0] oooooooo ooooooox [MSB]
2691 09:54:43.502306 995 |3 6 35|[0] oooooooo ooooooox [MSB]
2692 09:54:43.505693 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
2693 09:54:43.512012 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
2694 09:54:43.515578 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2695 09:54:43.518940 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
2696 09:54:43.522929 1000 |3 6 40|[0] oooooooo xxxxxxxx [MSB]
2697 09:54:43.525681 1001 |3 6 41|[0] oooxoooo xxxxxxxx [MSB]
2698 09:54:43.528458 1002 |3 6 42|[0] oooxoooo xxxxxxxx [MSB]
2699 09:54:43.531812 1003 |3 6 43|[0] oooxoooo xxxxxxxx [MSB]
2700 09:54:43.535164 1004 |3 6 44|[0] oooxoooo xxxxxxxx [MSB]
2701 09:54:43.538761 1005 |3 6 45|[0] oxxxooox xxxxxxxx [MSB]
2702 09:54:43.541915 1006 |3 6 46|[0] oxxxooox xxxxxxxx [MSB]
2703 09:54:43.545624 1007 |3 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
2704 09:54:43.548658 Byte0, DQ PI dly=993, DQM PI dly= 993
2705 09:54:43.555248 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 33)
2706 09:54:43.555638
2707 09:54:43.559019 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 33)
2708 09:54:43.559497
2709 09:54:43.561798 Byte1, DQ PI dly=986, DQM PI dly= 986
2710 09:54:43.565363 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
2711 09:54:43.568538
2712 09:54:43.572096 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
2713 09:54:43.572511
2714 09:54:43.572915 ==
2715 09:54:43.575186 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2716 09:54:43.578683 fsp= 1, odt_onoff= 1, Byte mode= 0
2717 09:54:43.579120 ==
2718 09:54:43.585502 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2719 09:54:43.586048
2720 09:54:43.588638 Begin, DQ Scan Range 962~1026
2721 09:54:43.589356 Write Rank0 MR14 =0x0
2722 09:54:43.596905
2723 09:54:43.597312 CH=1, VrefRange= 0, VrefLevel = 0
2724 09:54:43.603747 TX Bit0 (987~1001) 15 994, Bit8 (980~992) 13 986,
2725 09:54:43.606991 TX Bit1 (985~999) 15 992, Bit9 (980~991) 12 985,
2726 09:54:43.613898 TX Bit2 (983~999) 17 991, Bit10 (983~993) 11 988,
2727 09:54:43.616822 TX Bit3 (982~994) 13 988, Bit11 (984~995) 12 989,
2728 09:54:43.620302 TX Bit4 (985~1000) 16 992, Bit12 (984~994) 11 989,
2729 09:54:43.627077 TX Bit5 (987~1000) 14 993, Bit13 (984~993) 10 988,
2730 09:54:43.629948 TX Bit6 (985~1000) 16 992, Bit14 (983~994) 12 988,
2731 09:54:43.636901 TX Bit7 (985~1000) 16 992, Bit15 (976~987) 12 981,
2732 09:54:43.637398
2733 09:54:43.637713 Write Rank0 MR14 =0x2
2734 09:54:43.645752
2735 09:54:43.646316 CH=1, VrefRange= 0, VrefLevel = 2
2736 09:54:43.652265 TX Bit0 (986~1002) 17 994, Bit8 (980~992) 13 986,
2737 09:54:43.656385 TX Bit1 (985~1000) 16 992, Bit9 (979~992) 14 985,
2738 09:54:43.662394 TX Bit2 (983~1000) 18 991, Bit10 (983~994) 12 988,
2739 09:54:43.665303 TX Bit3 (982~994) 13 988, Bit11 (983~996) 14 989,
2740 09:54:43.668866 TX Bit4 (985~1001) 17 993, Bit12 (983~994) 12 988,
2741 09:54:43.675670 TX Bit5 (987~1001) 15 994, Bit13 (984~993) 10 988,
2742 09:54:43.678771 TX Bit6 (985~1001) 17 993, Bit14 (982~995) 14 988,
2743 09:54:43.685930 TX Bit7 (985~1000) 16 992, Bit15 (977~988) 12 982,
2744 09:54:43.686490
2745 09:54:43.688778 wait MRW command Rank0 MR14 =0x4 fired (1)
2746 09:54:43.689285 Write Rank0 MR14 =0x4
2747 09:54:43.698632
2748 09:54:43.699344 CH=1, VrefRange= 0, VrefLevel = 4
2749 09:54:43.705309 TX Bit0 (986~1003) 18 994, Bit8 (979~993) 15 986,
2750 09:54:43.708748 TX Bit1 (984~1000) 17 992, Bit9 (979~992) 14 985,
2751 09:54:43.715301 TX Bit2 (983~1000) 18 991, Bit10 (983~995) 13 989,
2752 09:54:43.718794 TX Bit3 (981~996) 16 988, Bit11 (983~997) 15 990,
2753 09:54:43.721786 TX Bit4 (984~1001) 18 992, Bit12 (983~995) 13 989,
2754 09:54:43.728467 TX Bit5 (986~1002) 17 994, Bit13 (984~994) 11 989,
2755 09:54:43.732033 TX Bit6 (984~1002) 19 993, Bit14 (982~995) 14 988,
2756 09:54:43.738557 TX Bit7 (985~1001) 17 993, Bit15 (976~990) 15 983,
2757 09:54:43.738951
2758 09:54:43.739257 Write Rank0 MR14 =0x6
2759 09:54:43.747847
2760 09:54:43.748315 CH=1, VrefRange= 0, VrefLevel = 6
2761 09:54:43.754462 TX Bit0 (986~1003) 18 994, Bit8 (978~993) 16 985,
2762 09:54:43.758076 TX Bit1 (985~1001) 17 993, Bit9 (978~993) 16 985,
2763 09:54:43.764963 TX Bit2 (982~1001) 20 991, Bit10 (982~996) 15 989,
2764 09:54:43.767207 TX Bit3 (981~996) 16 988, Bit11 (983~998) 16 990,
2765 09:54:43.770825 TX Bit4 (984~1002) 19 993, Bit12 (983~997) 15 990,
2766 09:54:43.777240 TX Bit5 (986~1002) 17 994, Bit13 (983~995) 13 989,
2767 09:54:43.780830 TX Bit6 (984~1002) 19 993, Bit14 (982~996) 15 989,
2768 09:54:43.787477 TX Bit7 (985~1001) 17 993, Bit15 (976~990) 15 983,
2769 09:54:43.787995
2770 09:54:43.788330 Write Rank0 MR14 =0x8
2771 09:54:43.797482
2772 09:54:43.798022 CH=1, VrefRange= 0, VrefLevel = 8
2773 09:54:43.803351 TX Bit0 (986~1004) 19 995, Bit8 (977~993) 17 985,
2774 09:54:43.806654 TX Bit1 (984~1002) 19 993, Bit9 (978~993) 16 985,
2775 09:54:43.813656 TX Bit2 (982~1001) 20 991, Bit10 (982~996) 15 989,
2776 09:54:43.817104 TX Bit3 (980~997) 18 988, Bit11 (983~998) 16 990,
2777 09:54:43.819971 TX Bit4 (984~1003) 20 993, Bit12 (982~997) 16 989,
2778 09:54:43.826916 TX Bit5 (986~1003) 18 994, Bit13 (983~996) 14 989,
2779 09:54:43.830251 TX Bit6 (984~1003) 20 993, Bit14 (981~997) 17 989,
2780 09:54:43.836819 TX Bit7 (984~1002) 19 993, Bit15 (976~991) 16 983,
2781 09:54:43.837337
2782 09:54:43.837669 Write Rank0 MR14 =0xa
2783 09:54:43.846743
2784 09:54:43.849851 CH=1, VrefRange= 0, VrefLevel = 10
2785 09:54:43.853186 TX Bit0 (986~1005) 20 995, Bit8 (977~994) 18 985,
2786 09:54:43.856443 TX Bit1 (984~1002) 19 993, Bit9 (977~994) 18 985,
2787 09:54:43.863052 TX Bit2 (981~1002) 22 991, Bit10 (981~997) 17 989,
2788 09:54:43.866074 TX Bit3 (979~998) 20 988, Bit11 (982~998) 17 990,
2789 09:54:43.869219 TX Bit4 (984~1003) 20 993, Bit12 (982~997) 16 989,
2790 09:54:43.875759 TX Bit5 (986~1004) 19 995, Bit13 (983~997) 15 990,
2791 09:54:43.879357 TX Bit6 (984~1003) 20 993, Bit14 (982~998) 17 990,
2792 09:54:43.886130 TX Bit7 (984~1002) 19 993, Bit15 (974~991) 18 982,
2793 09:54:43.886645
2794 09:54:43.886976 Write Rank0 MR14 =0xc
2795 09:54:43.895666
2796 09:54:43.899114 CH=1, VrefRange= 0, VrefLevel = 12
2797 09:54:43.902595 TX Bit0 (985~1005) 21 995, Bit8 (977~995) 19 986,
2798 09:54:43.905598 TX Bit1 (984~1003) 20 993, Bit9 (977~994) 18 985,
2799 09:54:43.911994 TX Bit2 (981~1002) 22 991, Bit10 (981~998) 18 989,
2800 09:54:43.915388 TX Bit3 (979~999) 21 989, Bit11 (982~999) 18 990,
2801 09:54:43.918566 TX Bit4 (983~1004) 22 993, Bit12 (982~998) 17 990,
2802 09:54:43.925350 TX Bit5 (985~1005) 21 995, Bit13 (983~998) 16 990,
2803 09:54:43.928514 TX Bit6 (984~1004) 21 994, Bit14 (981~998) 18 989,
2804 09:54:43.935659 TX Bit7 (984~1003) 20 993, Bit15 (975~991) 17 983,
2805 09:54:43.936153
2806 09:54:43.938561 wait MRW command Rank0 MR14 =0xe fired (1)
2807 09:54:43.939103 Write Rank0 MR14 =0xe
2808 09:54:43.949326
2809 09:54:43.952328 CH=1, VrefRange= 0, VrefLevel = 14
2810 09:54:43.955962 TX Bit0 (985~1006) 22 995, Bit8 (977~995) 19 986,
2811 09:54:43.959137 TX Bit1 (983~1004) 22 993, Bit9 (977~995) 19 986,
2812 09:54:43.965782 TX Bit2 (981~1003) 23 992, Bit10 (980~998) 19 989,
2813 09:54:43.969671 TX Bit3 (979~1000) 22 989, Bit11 (981~999) 19 990,
2814 09:54:43.972271 TX Bit4 (983~1004) 22 993, Bit12 (981~999) 19 990,
2815 09:54:43.978554 TX Bit5 (985~1005) 21 995, Bit13 (982~998) 17 990,
2816 09:54:43.981652 TX Bit6 (983~1004) 22 993, Bit14 (981~999) 19 990,
2817 09:54:43.988709 TX Bit7 (984~1003) 20 993, Bit15 (974~992) 19 983,
2818 09:54:43.989228
2819 09:54:43.989569 Write Rank0 MR14 =0x10
2820 09:54:43.998856
2821 09:54:44.002076 CH=1, VrefRange= 0, VrefLevel = 16
2822 09:54:44.005263 TX Bit0 (985~1006) 22 995, Bit8 (976~996) 21 986,
2823 09:54:44.008385 TX Bit1 (983~1004) 22 993, Bit9 (976~995) 20 985,
2824 09:54:44.015800 TX Bit2 (980~1004) 25 992, Bit10 (980~999) 20 989,
2825 09:54:44.019391 TX Bit3 (979~1000) 22 989, Bit11 (981~999) 19 990,
2826 09:54:44.021764 TX Bit4 (983~1005) 23 994, Bit12 (980~999) 20 989,
2827 09:54:44.028740 TX Bit5 (985~1006) 22 995, Bit13 (982~999) 18 990,
2828 09:54:44.031899 TX Bit6 (983~1006) 24 994, Bit14 (979~999) 21 989,
2829 09:54:44.038645 TX Bit7 (984~1004) 21 994, Bit15 (972~992) 21 982,
2830 09:54:44.039157
2831 09:54:44.039495 Write Rank0 MR14 =0x12
2832 09:54:44.048710
2833 09:54:44.051586 CH=1, VrefRange= 0, VrefLevel = 18
2834 09:54:44.055125 TX Bit0 (985~1007) 23 996, Bit8 (976~997) 22 986,
2835 09:54:44.058399 TX Bit1 (983~1005) 23 994, Bit9 (975~996) 22 985,
2836 09:54:44.065064 TX Bit2 (981~1004) 24 992, Bit10 (979~999) 21 989,
2837 09:54:44.068911 TX Bit3 (979~1001) 23 990, Bit11 (980~1000) 21 990,
2838 09:54:44.074680 TX Bit4 (982~1005) 24 993, Bit12 (980~999) 20 989,
2839 09:54:44.078562 TX Bit5 (985~1006) 22 995, Bit13 (982~999) 18 990,
2840 09:54:44.081508 TX Bit6 (983~1006) 24 994, Bit14 (979~999) 21 989,
2841 09:54:44.088098 TX Bit7 (983~1005) 23 994, Bit15 (973~993) 21 983,
2842 09:54:44.088529
2843 09:54:44.088865 Write Rank0 MR14 =0x14
2844 09:54:44.099023
2845 09:54:44.102240 CH=1, VrefRange= 0, VrefLevel = 20
2846 09:54:44.104964 TX Bit0 (984~1007) 24 995, Bit8 (976~998) 23 987,
2847 09:54:44.108756 TX Bit1 (983~1006) 24 994, Bit9 (975~997) 23 986,
2848 09:54:44.114924 TX Bit2 (980~1005) 26 992, Bit10 (979~999) 21 989,
2849 09:54:44.118437 TX Bit3 (978~1001) 24 989, Bit11 (979~1000) 22 989,
2850 09:54:44.125116 TX Bit4 (982~1006) 25 994, Bit12 (980~1000) 21 990,
2851 09:54:44.128739 TX Bit5 (985~1006) 22 995, Bit13 (981~999) 19 990,
2852 09:54:44.132077 TX Bit6 (982~1007) 26 994, Bit14 (979~999) 21 989,
2853 09:54:44.138609 TX Bit7 (983~1006) 24 994, Bit15 (972~993) 22 982,
2854 09:54:44.139114
2855 09:54:44.139455 Write Rank0 MR14 =0x16
2856 09:54:44.148871
2857 09:54:44.152096 CH=1, VrefRange= 0, VrefLevel = 22
2858 09:54:44.155119 TX Bit0 (984~1007) 24 995, Bit8 (975~998) 24 986,
2859 09:54:44.158741 TX Bit1 (983~1006) 24 994, Bit9 (975~997) 23 986,
2860 09:54:44.165343 TX Bit2 (979~1005) 27 992, Bit10 (978~1000) 23 989,
2861 09:54:44.168306 TX Bit3 (978~1002) 25 990, Bit11 (979~1000) 22 989,
2862 09:54:44.174966 TX Bit4 (982~1007) 26 994, Bit12 (979~1000) 22 989,
2863 09:54:44.178224 TX Bit5 (984~1007) 24 995, Bit13 (981~1000) 20 990,
2864 09:54:44.181770 TX Bit6 (982~1007) 26 994, Bit14 (979~1000) 22 989,
2865 09:54:44.188279 TX Bit7 (982~1006) 25 994, Bit15 (971~994) 24 982,
2866 09:54:44.188793
2867 09:54:44.191406 Write Rank0 MR14 =0x18
2868 09:54:44.198963
2869 09:54:44.202292 CH=1, VrefRange= 0, VrefLevel = 24
2870 09:54:44.205448 TX Bit0 (985~1007) 23 996, Bit8 (975~998) 24 986,
2871 09:54:44.209207 TX Bit1 (982~1006) 25 994, Bit9 (975~997) 23 986,
2872 09:54:44.215516 TX Bit2 (979~1006) 28 992, Bit10 (978~1000) 23 989,
2873 09:54:44.218851 TX Bit3 (978~1002) 25 990, Bit11 (979~1001) 23 990,
2874 09:54:44.225597 TX Bit4 (981~1007) 27 994, Bit12 (979~1000) 22 989,
2875 09:54:44.229454 TX Bit5 (984~1007) 24 995, Bit13 (981~1000) 20 990,
2876 09:54:44.231853 TX Bit6 (982~1007) 26 994, Bit14 (978~1000) 23 989,
2877 09:54:44.238742 TX Bit7 (982~1006) 25 994, Bit15 (971~994) 24 982,
2878 09:54:44.239248
2879 09:54:44.241705 Write Rank0 MR14 =0x1a
2880 09:54:44.249803
2881 09:54:44.252549 CH=1, VrefRange= 0, VrefLevel = 26
2882 09:54:44.256181 TX Bit0 (984~1007) 24 995, Bit8 (974~998) 25 986,
2883 09:54:44.259295 TX Bit1 (982~1007) 26 994, Bit9 (974~998) 25 986,
2884 09:54:44.266058 TX Bit2 (979~1006) 28 992, Bit10 (977~1000) 24 988,
2885 09:54:44.269430 TX Bit3 (978~1002) 25 990, Bit11 (978~1001) 24 989,
2886 09:54:44.276407 TX Bit4 (981~1007) 27 994, Bit12 (978~1001) 24 989,
2887 09:54:44.278929 TX Bit5 (984~1007) 24 995, Bit13 (980~1000) 21 990,
2888 09:54:44.282945 TX Bit6 (981~1007) 27 994, Bit14 (978~1000) 23 989,
2889 09:54:44.289276 TX Bit7 (981~1007) 27 994, Bit15 (971~995) 25 983,
2890 09:54:44.289785
2891 09:54:44.290173 Write Rank0 MR14 =0x1c
2892 09:54:44.299851
2893 09:54:44.303044 CH=1, VrefRange= 0, VrefLevel = 28
2894 09:54:44.306275 TX Bit0 (983~1008) 26 995, Bit8 (974~999) 26 986,
2895 09:54:44.309467 TX Bit1 (981~1007) 27 994, Bit9 (974~998) 25 986,
2896 09:54:44.316795 TX Bit2 (979~1005) 27 992, Bit10 (977~1000) 24 988,
2897 09:54:44.319652 TX Bit3 (978~1003) 26 990, Bit11 (978~1001) 24 989,
2898 09:54:44.326321 TX Bit4 (981~1007) 27 994, Bit12 (978~1001) 24 989,
2899 09:54:44.329760 TX Bit5 (984~1007) 24 995, Bit13 (980~1000) 21 990,
2900 09:54:44.333665 TX Bit6 (981~1007) 27 994, Bit14 (977~1001) 25 989,
2901 09:54:44.339925 TX Bit7 (981~1007) 27 994, Bit15 (970~995) 26 982,
2902 09:54:44.340433
2903 09:54:44.340774 Write Rank0 MR14 =0x1e
2904 09:54:44.350802
2905 09:54:44.353765 CH=1, VrefRange= 0, VrefLevel = 30
2906 09:54:44.356744 TX Bit0 (983~1008) 26 995, Bit8 (974~999) 26 986,
2907 09:54:44.360146 TX Bit1 (981~1007) 27 994, Bit9 (974~998) 25 986,
2908 09:54:44.366837 TX Bit2 (979~1005) 27 992, Bit10 (977~1000) 24 988,
2909 09:54:44.370305 TX Bit3 (978~1003) 26 990, Bit11 (978~1001) 24 989,
2910 09:54:44.376449 TX Bit4 (982~1007) 26 994, Bit12 (978~1000) 23 989,
2911 09:54:44.380164 TX Bit5 (983~1008) 26 995, Bit13 (979~1001) 23 990,
2912 09:54:44.383413 TX Bit6 (981~1007) 27 994, Bit14 (977~1000) 24 988,
2913 09:54:44.390109 TX Bit7 (980~1007) 28 993, Bit15 (970~995) 26 982,
2914 09:54:44.390618
2915 09:54:44.393288 Write Rank0 MR14 =0x20
2916 09:54:44.400998
2917 09:54:44.403769 CH=1, VrefRange= 0, VrefLevel = 32
2918 09:54:44.407163 TX Bit0 (983~1008) 26 995, Bit8 (974~999) 26 986,
2919 09:54:44.410443 TX Bit1 (981~1007) 27 994, Bit9 (974~998) 25 986,
2920 09:54:44.418154 TX Bit2 (979~1005) 27 992, Bit10 (977~1000) 24 988,
2921 09:54:44.421462 TX Bit3 (978~1003) 26 990, Bit11 (978~1001) 24 989,
2922 09:54:44.427215 TX Bit4 (982~1007) 26 994, Bit12 (978~1000) 23 989,
2923 09:54:44.430385 TX Bit5 (983~1008) 26 995, Bit13 (979~1001) 23 990,
2924 09:54:44.433642 TX Bit6 (981~1007) 27 994, Bit14 (977~1000) 24 988,
2925 09:54:44.440546 TX Bit7 (980~1007) 28 993, Bit15 (970~995) 26 982,
2926 09:54:44.441060
2927 09:54:44.443791 Write Rank0 MR14 =0x22
2928 09:54:44.451596
2929 09:54:44.454758 CH=1, VrefRange= 0, VrefLevel = 34
2930 09:54:44.458424 TX Bit0 (983~1008) 26 995, Bit8 (974~999) 26 986,
2931 09:54:44.461375 TX Bit1 (981~1007) 27 994, Bit9 (974~998) 25 986,
2932 09:54:44.467824 TX Bit2 (979~1005) 27 992, Bit10 (977~1000) 24 988,
2933 09:54:44.471496 TX Bit3 (978~1003) 26 990, Bit11 (978~1001) 24 989,
2934 09:54:44.478183 TX Bit4 (982~1007) 26 994, Bit12 (978~1000) 23 989,
2935 09:54:44.481242 TX Bit5 (983~1008) 26 995, Bit13 (979~1001) 23 990,
2936 09:54:44.484810 TX Bit6 (981~1007) 27 994, Bit14 (977~1000) 24 988,
2937 09:54:44.491158 TX Bit7 (980~1007) 28 993, Bit15 (970~995) 26 982,
2938 09:54:44.491690
2939 09:54:44.494498 Write Rank0 MR14 =0x24
2940 09:54:44.501670
2941 09:54:44.502215 CH=1, VrefRange= 0, VrefLevel = 36
2942 09:54:44.508607 TX Bit0 (983~1008) 26 995, Bit8 (974~999) 26 986,
2943 09:54:44.511388 TX Bit1 (981~1007) 27 994, Bit9 (974~998) 25 986,
2944 09:54:44.518021 TX Bit2 (979~1005) 27 992, Bit10 (977~1000) 24 988,
2945 09:54:44.521419 TX Bit3 (978~1003) 26 990, Bit11 (978~1001) 24 989,
2946 09:54:44.528702 TX Bit4 (982~1007) 26 994, Bit12 (978~1000) 23 989,
2947 09:54:44.531472 TX Bit5 (983~1008) 26 995, Bit13 (979~1001) 23 990,
2948 09:54:44.534210 TX Bit6 (981~1007) 27 994, Bit14 (977~1000) 24 988,
2949 09:54:44.541038 TX Bit7 (980~1007) 28 993, Bit15 (970~995) 26 982,
2950 09:54:44.541560
2951 09:54:44.541897
2952 09:54:44.544429 TX Vref found, early break! 383< 387
2953 09:54:44.547735 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =844/100 ps
2954 09:54:44.550966 u1DelayCellOfst[0]=5 cells (5 PI)
2955 09:54:44.554579 u1DelayCellOfst[1]=4 cells (4 PI)
2956 09:54:44.558023 u1DelayCellOfst[2]=2 cells (2 PI)
2957 09:54:44.561932 u1DelayCellOfst[3]=0 cells (0 PI)
2958 09:54:44.564422 u1DelayCellOfst[4]=4 cells (4 PI)
2959 09:54:44.567569 u1DelayCellOfst[5]=5 cells (5 PI)
2960 09:54:44.570944 u1DelayCellOfst[6]=4 cells (4 PI)
2961 09:54:44.574883 u1DelayCellOfst[7]=3 cells (3 PI)
2962 09:54:44.578057 Byte0, DQ PI dly=990, DQM PI dly= 992
2963 09:54:44.581463 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 30)
2964 09:54:44.582025
2965 09:54:44.584631 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 30)
2966 09:54:44.585072
2967 09:54:44.588096 u1DelayCellOfst[8]=4 cells (4 PI)
2968 09:54:44.591000 u1DelayCellOfst[9]=4 cells (4 PI)
2969 09:54:44.594675 u1DelayCellOfst[10]=6 cells (6 PI)
2970 09:54:44.598039 u1DelayCellOfst[11]=8 cells (7 PI)
2971 09:54:44.601125 u1DelayCellOfst[12]=8 cells (7 PI)
2972 09:54:44.604171 u1DelayCellOfst[13]=9 cells (8 PI)
2973 09:54:44.607348 u1DelayCellOfst[14]=6 cells (6 PI)
2974 09:54:44.610626 u1DelayCellOfst[15]=0 cells (0 PI)
2975 09:54:44.614048 Byte1, DQ PI dly=982, DQM PI dly= 986
2976 09:54:44.617120 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
2977 09:54:44.617629
2978 09:54:44.621784 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
2979 09:54:44.624273
2980 09:54:44.624777 Write Rank0 MR14 =0x1e
2981 09:54:44.625108
2982 09:54:44.628106 Final TX Range 0 Vref 30
2983 09:54:44.628615
2984 09:54:44.633947 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2985 09:54:44.634410
2986 09:54:44.640805 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2987 09:54:44.647894 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2988 09:54:44.653839 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2989 09:54:44.657093 Write Rank0 MR3 =0xb0
2990 09:54:44.657618 DramC Write-DBI on
2991 09:54:44.657959 ==
2992 09:54:44.663847 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2993 09:54:44.667401 fsp= 1, odt_onoff= 1, Byte mode= 0
2994 09:54:44.667909 ==
2995 09:54:44.670327 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2996 09:54:44.670755
2997 09:54:44.673749 Begin, DQ Scan Range 706~770
2998 09:54:44.674291
2999 09:54:44.674626
3000 09:54:44.677269 TX Vref Scan disable
3001 09:54:44.680360 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3002 09:54:44.684285 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3003 09:54:44.686923 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3004 09:54:44.690560 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3005 09:54:44.693506 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3006 09:54:44.696989 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3007 09:54:44.700776 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3008 09:54:44.704237 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3009 09:54:44.706898 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3010 09:54:44.709822 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3011 09:54:44.713192 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3012 09:54:44.716919 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3013 09:54:44.720618 718 |2 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
3014 09:54:44.723918 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3015 09:54:44.726788 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3016 09:54:44.733647 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3017 09:54:44.736757 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3018 09:54:44.740314 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3019 09:54:44.743609 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3020 09:54:44.747336 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3021 09:54:44.750055 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB]
3022 09:54:44.757790 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3023 09:54:44.760297 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3024 09:54:44.763841 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3025 09:54:44.766925 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3026 09:54:44.770215 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3027 09:54:44.774329 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3028 09:54:44.776827 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3029 09:54:44.780063 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3030 09:54:44.783258 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB]
3031 09:54:44.787342 753 |2 6 49|[0] xxxxxxxx xxxxxxxx [MSB]
3032 09:54:44.790281 Byte0, DQ PI dly=739, DQM PI dly= 739
3033 09:54:44.793385 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 35)
3034 09:54:44.796819
3035 09:54:44.800448 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 35)
3036 09:54:44.800931
3037 09:54:44.803502 Byte1, DQ PI dly=731, DQM PI dly= 731
3038 09:54:44.806401 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 27)
3039 09:54:44.806811
3040 09:54:44.813092 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 27)
3041 09:54:44.813573
3042 09:54:44.819984 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3043 09:54:44.826531 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3044 09:54:44.832950 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3045 09:54:44.833375 Write Rank0 MR3 =0x30
3046 09:54:44.836172 DramC Write-DBI off
3047 09:54:44.836574
3048 09:54:44.836870 [DATLAT]
3049 09:54:44.840283 Freq=1600, CH1 RK0, use_rxtx_scan=0
3050 09:54:44.840756
3051 09:54:44.842715 DATLAT Default: 0xf
3052 09:54:44.843096 7, 0xFFFF, sum=0
3053 09:54:44.846360 8, 0xFFFF, sum=0
3054 09:54:44.846759 9, 0xFFFF, sum=0
3055 09:54:44.849889 10, 0xFFFF, sum=0
3056 09:54:44.850392 11, 0xFFFF, sum=0
3057 09:54:44.852849 12, 0xFFFF, sum=0
3058 09:54:44.853246 13, 0xFFFF, sum=0
3059 09:54:44.856249 14, 0x0, sum=1
3060 09:54:44.856646 15, 0x0, sum=2
3061 09:54:44.856957 16, 0x0, sum=3
3062 09:54:44.860057 17, 0x0, sum=4
3063 09:54:44.862859 pattern=2 first_step=14 total pass=5 best_step=16
3064 09:54:44.863250 ==
3065 09:54:44.869930 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3066 09:54:44.872662 fsp= 1, odt_onoff= 1, Byte mode= 0
3067 09:54:44.873046 ==
3068 09:54:44.876594 Start DQ dly to find pass range UseTestEngine =1
3069 09:54:44.880096 x-axis: bit #, y-axis: DQ dly (-127~63)
3070 09:54:44.883019 RX Vref Scan = 1
3071 09:54:44.996803
3072 09:54:44.997311 RX Vref found, early break!
3073 09:54:44.997647
3074 09:54:45.003168 Final RX Vref 12, apply to both rank0 and 1
3075 09:54:45.003714 ==
3076 09:54:45.006613 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3077 09:54:45.009855 fsp= 1, odt_onoff= 1, Byte mode= 0
3078 09:54:45.010325 ==
3079 09:54:45.010658 DQS Delay:
3080 09:54:45.013081 DQS0 = 0, DQS1 = 0
3081 09:54:45.013506 DQM Delay:
3082 09:54:45.016928 DQM0 = 21, DQM1 = 19
3083 09:54:45.017385 DQ Delay:
3084 09:54:45.020029 DQ0 =23, DQ1 =21, DQ2 =20, DQ3 =19
3085 09:54:45.023260 DQ4 =21, DQ5 =23, DQ6 =24, DQ7 =22
3086 09:54:45.025977 DQ8 =18, DQ9 =16, DQ10 =21, DQ11 =21
3087 09:54:45.029403 DQ12 =22, DQ13 =22, DQ14 =21, DQ15 =15
3088 09:54:45.029783
3089 09:54:45.030125
3090 09:54:45.030408
3091 09:54:45.032807 [DramC_TX_OE_Calibration] TA2
3092 09:54:45.036442 Original DQ_B0 (3 6) =30, OEN = 27
3093 09:54:45.039502 Original DQ_B1 (3 6) =30, OEN = 27
3094 09:54:45.042886 23, 0x0, End_B0=23 End_B1=23
3095 09:54:45.043281 24, 0x0, End_B0=24 End_B1=24
3096 09:54:45.046164 25, 0x0, End_B0=25 End_B1=25
3097 09:54:45.049598 26, 0x0, End_B0=26 End_B1=26
3098 09:54:45.053326 27, 0x0, End_B0=27 End_B1=27
3099 09:54:45.056223 28, 0x0, End_B0=28 End_B1=28
3100 09:54:45.056700 29, 0x0, End_B0=29 End_B1=29
3101 09:54:45.060145 30, 0x0, End_B0=30 End_B1=30
3102 09:54:45.062792 31, 0xFFFF, End_B0=30 End_B1=30
3103 09:54:45.069886 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3104 09:54:45.073168 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3105 09:54:45.073640
3106 09:54:45.073941
3107 09:54:45.076610 Write Rank0 MR23 =0x3f
3108 09:54:45.077077 [DQSOSC]
3109 09:54:45.086451 [DQSOSCAuto] RK0, (LSB)MR18= 0xbfbf, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
3110 09:54:45.093061 CH1_RK0: MR19=0x202, MR18=0xBFBF, DQSOSC=448, MR23=63, INC=12, DEC=18
3111 09:54:45.093580 Write Rank0 MR23 =0x3f
3112 09:54:45.096274 [DQSOSC]
3113 09:54:45.102952 [DQSOSCAuto] RK0, (LSB)MR18= 0xbcbc, (MSB)MR19= 0x202, tDQSOscB0 = 450 ps tDQSOscB1 = 450 ps
3114 09:54:45.105945 CH1 RK0: MR19=202, MR18=BCBC
3115 09:54:45.109276 [RankSwap] Rank num 2, (Multi 1), Rank 1
3116 09:54:45.109882 Write Rank0 MR2 =0xad
3117 09:54:45.112165 [Write Leveling]
3118 09:54:45.115673 delay byte0 byte1 byte2 byte3
3119 09:54:45.116105
3120 09:54:45.116438 10 0 0
3121 09:54:45.119266 11 0 0
3122 09:54:45.119661 12 0 0
3123 09:54:45.122617 13 0 0
3124 09:54:45.123025 14 0 0
3125 09:54:45.123338 15 0 0
3126 09:54:45.125718 16 0 0
3127 09:54:45.126142 17 0 0
3128 09:54:45.129336 18 0 0
3129 09:54:45.129731 19 0 0
3130 09:54:45.130086 20 0 0
3131 09:54:45.132496 21 0 0
3132 09:54:45.132891 22 0 0
3133 09:54:45.135914 23 0 0
3134 09:54:45.136341 24 0 0
3135 09:54:45.136645 25 0 0
3136 09:54:45.139658 26 0 0
3137 09:54:45.140049 27 0 0
3138 09:54:45.142417 28 0 0
3139 09:54:45.142807 29 0 0
3140 09:54:45.145813 30 0 0
3141 09:54:45.146375 31 0 0
3142 09:54:45.146687 32 0 ff
3143 09:54:45.149565 33 0 ff
3144 09:54:45.150065 34 0 ff
3145 09:54:45.152676 35 0 ff
3146 09:54:45.153158 36 0 ff
3147 09:54:45.155511 37 ff ff
3148 09:54:45.155900 38 ff ff
3149 09:54:45.158738 39 0 ff
3150 09:54:45.159126 40 ff ff
3151 09:54:45.159433 41 ff ff
3152 09:54:45.162350 42 ff ff
3153 09:54:45.162739 43 ff ff
3154 09:54:45.165501 44 ff ff
3155 09:54:45.165890 45 ff ff
3156 09:54:45.168816 46 ff ff
3157 09:54:45.172784 pass bytecount = 0xff (0xff: all bytes pass)
3158 09:54:45.173252
3159 09:54:45.173554 DQS0 dly: 40
3160 09:54:45.175969 DQS1 dly: 32
3161 09:54:45.176437 Write Rank0 MR2 =0x2d
3162 09:54:45.182528 [RankSwap] Rank num 2, (Multi 1), Rank 0
3163 09:54:45.182994 Write Rank1 MR1 =0xd6
3164 09:54:45.183292 [Gating]
3165 09:54:45.185862 ==
3166 09:54:45.188686 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3167 09:54:45.192004 fsp= 1, odt_onoff= 1, Byte mode= 0
3168 09:54:45.192497 ==
3169 09:54:45.196014 3 1 0 |3534 2c2c |(11 11)(11 11) |(0 0)(1 1)| 0
3170 09:54:45.202305 3 1 4 |3534 2c2c |(11 11)(11 11) |(1 1)(0 0)| 0
3171 09:54:45.205691 3 1 8 |3534 2d2d |(11 11)(10 10) |(1 1)(0 0)| 0
3172 09:54:45.208382 3 1 12 |3534 2c2c |(11 11)(11 11) |(1 1)(1 0)| 0
3173 09:54:45.215154 3 1 16 |3534 2e2d |(11 11)(11 11) |(1 1)(1 1)| 0
3174 09:54:45.218478 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 1)(1 1)| 0
3175 09:54:45.221934 3 1 24 |3534 2c2c |(11 11)(11 11) |(0 1)(1 0)| 0
3176 09:54:45.228743 3 1 28 |3534 2c2c |(11 11)(0 0) |(0 1)(0 1)| 0
3177 09:54:45.231866 3 2 0 |3534 2d2d |(11 11)(11 11) |(0 1)(1 0)| 0
3178 09:54:45.234878 3 2 4 |3534 2c2c |(11 11)(0 0) |(0 1)(1 1)| 0
3179 09:54:45.238479 3 2 8 |3534 2f2f |(11 11)(0 0) |(0 1)(1 0)| 0
3180 09:54:45.245083 3 2 12 |807 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3181 09:54:45.248979 3 2 16 |3d3d 2c2c |(11 11)(11 11) |(1 1)(0 0)| 0
3182 09:54:45.251620 3 2 20 |3d3d e0e |(11 11)(11 11) |(1 1)(0 0)| 0
3183 09:54:45.258414 3 2 24 |3d3d 807 |(11 11)(11 11) |(1 1)(0 0)| 0
3184 09:54:45.261746 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3185 09:54:45.265106 3 3 0 |3d3d 3635 |(11 11)(11 11) |(1 1)(0 0)| 0
3186 09:54:45.268316 3 3 4 |3d3d 3635 |(11 11)(11 11) |(1 1)(1 1)| 0
3187 09:54:45.275184 3 3 8 |3d3d 3535 |(11 11)(10 10) |(1 1)(1 1)| 0
3188 09:54:45.278069 [Byte 1] Lead/lag Transition tap number (1)
3189 09:54:45.281868 3 3 12 |3d3d a09 |(11 11)(11 11) |(1 1)(0 0)| 0
3190 09:54:45.288529 3 3 16 |202 1a1a |(11 11)(11 11) |(1 1)(1 1)| 0
3191 09:54:45.291515 3 3 20 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3192 09:54:45.294968 [Byte 0] Lead/lag falling Transition (3, 3, 20)
3193 09:54:45.298259 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3194 09:54:45.305630 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3195 09:54:45.308164 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3196 09:54:45.311105 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3197 09:54:45.317888 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
3198 09:54:45.321642 3 4 12 |303 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3199 09:54:45.325084 3 4 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3200 09:54:45.331307 3 4 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3201 09:54:45.334525 3 4 24 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
3202 09:54:45.338060 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3203 09:54:45.345097 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3204 09:54:45.347918 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3205 09:54:45.351532 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3206 09:54:45.354472 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3207 09:54:45.361161 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3208 09:54:45.364444 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3209 09:54:45.367913 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3210 09:54:45.374662 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3211 09:54:45.377880 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3212 09:54:45.381638 [Byte 0] Lead/lag falling Transition (3, 6, 0)
3213 09:54:45.387733 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3214 09:54:45.391058 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3215 09:54:45.394845 [Byte 0] Lead/lag Transition tap number (3)
3216 09:54:45.398309 [Byte 1] Lead/lag falling Transition (3, 6, 8)
3217 09:54:45.404299 3 6 12 |201f 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3218 09:54:45.407393 [Byte 1] Lead/lag Transition tap number (2)
3219 09:54:45.411680 3 6 16 |606 3d3d |(1 1)(11 11) |(0 0)(0 0)| 0
3220 09:54:45.414485 3 6 20 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
3221 09:54:45.418467 [Byte 0]First pass (3, 6, 20)
3222 09:54:45.421048 3 6 24 |4646 202 |(0 0)(1 1) |(0 0)(0 0)| 0
3223 09:54:45.427849 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3224 09:54:45.428289 [Byte 1]First pass (3, 6, 28)
3225 09:54:45.434096 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3226 09:54:45.437708 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3227 09:54:45.441597 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3228 09:54:45.444326 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3229 09:54:45.447124 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3230 09:54:45.454151 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3231 09:54:45.457473 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3232 09:54:45.460605 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3233 09:54:45.464073 All bytes gating window > 1UI, Early break!
3234 09:54:45.464588
3235 09:54:45.467537 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 6)
3236 09:54:45.468053
3237 09:54:45.473881 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 12)
3238 09:54:45.474729
3239 09:54:45.475294
3240 09:54:45.475761
3241 09:54:45.477105 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 6)
3242 09:54:45.477604
3243 09:54:45.481352 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
3244 09:54:45.481864
3245 09:54:45.482249
3246 09:54:45.483651 Write Rank1 MR1 =0x56
3247 09:54:45.484080
3248 09:54:45.487073 best RODT dly(2T, 0.5T) = (2, 3)
3249 09:54:45.487504
3250 09:54:45.490504 best RODT dly(2T, 0.5T) = (2, 3)
3251 09:54:45.490934 ==
3252 09:54:45.493507 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3253 09:54:45.497205 fsp= 1, odt_onoff= 1, Byte mode= 0
3254 09:54:45.497683 ==
3255 09:54:45.504080 Start DQ dly to find pass range UseTestEngine =0
3256 09:54:45.507174 x-axis: bit #, y-axis: DQ dly (-127~63)
3257 09:54:45.507649 RX Vref Scan = 0
3258 09:54:45.510378 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3259 09:54:45.513850 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3260 09:54:45.517125 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3261 09:54:45.520375 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3262 09:54:45.520772 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3263 09:54:45.523954 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3264 09:54:45.527721 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3265 09:54:45.530513 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3266 09:54:45.534260 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3267 09:54:45.536972 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3268 09:54:45.541168 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3269 09:54:45.543363 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3270 09:54:45.543793 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3271 09:54:45.547343 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3272 09:54:45.550067 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3273 09:54:45.554639 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3274 09:54:45.557731 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3275 09:54:45.560463 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3276 09:54:45.563833 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3277 09:54:45.567612 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3278 09:54:45.568125 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3279 09:54:45.570538 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3280 09:54:45.574019 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3281 09:54:45.577278 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3282 09:54:45.580465 -2, [0] xxxxxxxx xxxxxxxx [MSB]
3283 09:54:45.584281 -1, [0] xxxxxxxx xxxxxxxx [MSB]
3284 09:54:45.587441 0, [0] xxxxxxxx xxxxxxxo [MSB]
3285 09:54:45.587971 1, [0] xxxxxxxx xxxxxxxo [MSB]
3286 09:54:45.590614 2, [0] xxxoxxxx ooxxxxxo [MSB]
3287 09:54:45.593276 3, [0] xxxoxxxx ooxxxxxo [MSB]
3288 09:54:45.597221 4, [0] xxooxxxx ooxxxxxo [MSB]
3289 09:54:45.601096 5, [0] xxoooxxx oooxoxoo [MSB]
3290 09:54:45.601607 6, [0] xxoooxxo oooooooo [MSB]
3291 09:54:45.603917 7, [0] xooooxxo oooooooo [MSB]
3292 09:54:45.607229 31, [0] oooooooo ooooooox [MSB]
3293 09:54:45.610484 32, [0] oooooooo ooooooox [MSB]
3294 09:54:45.613515 33, [0] oooooooo ooooooox [MSB]
3295 09:54:45.617596 34, [0] oooooooo oxooooox [MSB]
3296 09:54:45.620128 35, [0] oooxoooo xxooooox [MSB]
3297 09:54:45.623266 36, [0] ooxxoooo xxooooox [MSB]
3298 09:54:45.623700 37, [0] ooxxoooo xxooooox [MSB]
3299 09:54:45.626847 38, [0] ooxxxooo xxxoooox [MSB]
3300 09:54:45.629853 39, [0] ooxxxoox xxxxxxxx [MSB]
3301 09:54:45.633167 40, [0] oxxxxoox xxxxxxxx [MSB]
3302 09:54:45.636649 41, [0] xxxxxxox xxxxxxxx [MSB]
3303 09:54:45.640133 42, [0] xxxxxxxx xxxxxxxx [MSB]
3304 09:54:45.643490 iDelay=42, Bit 0, Center 24 (8 ~ 40) 33
3305 09:54:45.646642 iDelay=42, Bit 1, Center 23 (7 ~ 39) 33
3306 09:54:45.650510 iDelay=42, Bit 2, Center 19 (4 ~ 35) 32
3307 09:54:45.653776 iDelay=42, Bit 3, Center 18 (2 ~ 34) 33
3308 09:54:45.656560 iDelay=42, Bit 4, Center 21 (5 ~ 37) 33
3309 09:54:45.659770 iDelay=42, Bit 5, Center 24 (8 ~ 40) 33
3310 09:54:45.662748 iDelay=42, Bit 6, Center 24 (8 ~ 41) 34
3311 09:54:45.667127 iDelay=42, Bit 7, Center 22 (6 ~ 38) 33
3312 09:54:45.670054 iDelay=42, Bit 8, Center 18 (2 ~ 34) 33
3313 09:54:45.673226 iDelay=42, Bit 9, Center 17 (2 ~ 33) 32
3314 09:54:45.676799 iDelay=42, Bit 10, Center 21 (5 ~ 37) 33
3315 09:54:45.682969 iDelay=42, Bit 11, Center 22 (6 ~ 38) 33
3316 09:54:45.686761 iDelay=42, Bit 12, Center 21 (5 ~ 38) 34
3317 09:54:45.689446 iDelay=42, Bit 13, Center 22 (6 ~ 38) 33
3318 09:54:45.692885 iDelay=42, Bit 14, Center 21 (5 ~ 38) 34
3319 09:54:45.696488 iDelay=42, Bit 15, Center 15 (0 ~ 30) 31
3320 09:54:45.697008 ==
3321 09:54:45.699825 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3322 09:54:45.703228 fsp= 1, odt_onoff= 1, Byte mode= 0
3323 09:54:45.706204 ==
3324 09:54:45.706754 DQS Delay:
3325 09:54:45.707101 DQS0 = 0, DQS1 = 0
3326 09:54:45.709631 DQM Delay:
3327 09:54:45.710105 DQM0 = 21, DQM1 = 19
3328 09:54:45.712701 DQ Delay:
3329 09:54:45.713149 DQ0 =24, DQ1 =23, DQ2 =19, DQ3 =18
3330 09:54:45.716040 DQ4 =21, DQ5 =24, DQ6 =24, DQ7 =22
3331 09:54:45.719329 DQ8 =18, DQ9 =17, DQ10 =21, DQ11 =22
3332 09:54:45.722947 DQ12 =21, DQ13 =22, DQ14 =21, DQ15 =15
3333 09:54:45.723332
3334 09:54:45.726625
3335 09:54:45.727158 DramC Write-DBI off
3336 09:54:45.727470 ==
3337 09:54:45.732827 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3338 09:54:45.736551 fsp= 1, odt_onoff= 1, Byte mode= 0
3339 09:54:45.736942 ==
3340 09:54:45.739710 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3341 09:54:45.740100
3342 09:54:45.742559 Begin, DQ Scan Range 928~1184
3343 09:54:45.742946
3344 09:54:45.743245
3345 09:54:45.745785 TX Vref Scan disable
3346 09:54:45.749539 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3347 09:54:45.752867 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3348 09:54:45.756036 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3349 09:54:45.759556 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3350 09:54:45.762685 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3351 09:54:45.766177 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3352 09:54:45.770161 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3353 09:54:45.773270 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3354 09:54:45.776160 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3355 09:54:45.779889 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3356 09:54:45.782726 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3357 09:54:45.785833 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3358 09:54:45.788940 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3359 09:54:45.792477 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3360 09:54:45.796542 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3361 09:54:45.802607 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3362 09:54:45.806333 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3363 09:54:45.809605 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3364 09:54:45.812034 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3365 09:54:45.815468 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3366 09:54:45.818848 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3367 09:54:45.822540 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3368 09:54:45.825572 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3369 09:54:45.829466 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3370 09:54:45.832880 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3371 09:54:45.835151 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3372 09:54:45.838738 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3373 09:54:45.841740 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3374 09:54:45.845552 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3375 09:54:45.848979 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3376 09:54:45.855282 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3377 09:54:45.859163 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3378 09:54:45.862025 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3379 09:54:45.865327 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3380 09:54:45.869173 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3381 09:54:45.872471 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3382 09:54:45.875787 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3383 09:54:45.878916 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3384 09:54:45.882154 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3385 09:54:45.885450 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3386 09:54:45.888815 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3387 09:54:45.892472 969 |3 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3388 09:54:45.895519 970 |3 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3389 09:54:45.899469 971 |3 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3390 09:54:45.902187 972 |3 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3391 09:54:45.905302 973 |3 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3392 09:54:45.909411 974 |3 6 14|[0] xxxxxxxx xxxxxxxx [MSB]
3393 09:54:45.912253 975 |3 6 15|[0] xxxxxxxx xxxxxxxx [MSB]
3394 09:54:45.915215 976 |3 6 16|[0] xxxxxxxx xxxxxxxx [MSB]
3395 09:54:45.919556 977 |3 6 17|[0] xxxxxxxx ooxxxxxo [MSB]
3396 09:54:45.924927 978 |3 6 18|[0] xxxxxxxx ooxxxxxo [MSB]
3397 09:54:45.928649 979 |3 6 19|[0] xxxxxxxx oooxxxxo [MSB]
3398 09:54:45.931557 980 |3 6 20|[0] xxxxxxxx ooooxxoo [MSB]
3399 09:54:45.934967 981 |3 6 21|[0] xxxxxxxx oooooxoo [MSB]
3400 09:54:45.938431 982 |3 6 22|[0] xxxxxxxx oooooooo [MSB]
3401 09:54:45.942192 983 |3 6 23|[0] xxxxxxxx oooooooo [MSB]
3402 09:54:45.945408 984 |3 6 24|[0] xxxxxxxx oooooooo [MSB]
3403 09:54:45.949103 985 |3 6 25|[0] xxoooxox oooooooo [MSB]
3404 09:54:45.951447 986 |3 6 26|[0] xooooooo oooooooo [MSB]
3405 09:54:45.958149 994 |3 6 34|[0] oooooooo ooooooox [MSB]
3406 09:54:45.961785 995 |3 6 35|[0] oooooooo oxooooox [MSB]
3407 09:54:45.965025 996 |3 6 36|[0] oooooooo xxooooox [MSB]
3408 09:54:45.968608 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3409 09:54:45.971413 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
3410 09:54:45.974947 999 |3 6 39|[0] oooooooo xxxxxxxx [MSB]
3411 09:54:45.977939 1000 |3 6 40|[0] oooooooo xxxxxxxx [MSB]
3412 09:54:45.981355 1001 |3 6 41|[0] oooooooo xxxxxxxx [MSB]
3413 09:54:45.984966 1002 |3 6 42|[0] oooooooo xxxxxxxx [MSB]
3414 09:54:45.988389 1003 |3 6 43|[0] oooooooo xxxxxxxx [MSB]
3415 09:54:45.991423 1004 |3 6 44|[0] oooxoooo xxxxxxxx [MSB]
3416 09:54:45.995208 1005 |3 6 45|[0] oooxoooo xxxxxxxx [MSB]
3417 09:54:45.998257 1006 |3 6 46|[0] oooxoooo xxxxxxxx [MSB]
3418 09:54:46.004517 1007 |3 6 47|[0] ooxxooxo xxxxxxxx [MSB]
3419 09:54:46.007704 1008 |3 6 48|[0] xxxxxxxx xxxxxxxx [MSB]
3420 09:54:46.011108 Byte0, DQ PI dly=995, DQM PI dly= 995
3421 09:54:46.014641 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 35)
3422 09:54:46.015205
3423 09:54:46.018017 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 35)
3424 09:54:46.018418
3425 09:54:46.021046 Byte1, DQ PI dly=987, DQM PI dly= 987
3426 09:54:46.028018 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
3427 09:54:46.028414
3428 09:54:46.031828 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
3429 09:54:46.032310
3430 09:54:46.032615 ==
3431 09:54:46.038091 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3432 09:54:46.041232 fsp= 1, odt_onoff= 1, Byte mode= 0
3433 09:54:46.041708 ==
3434 09:54:46.044432 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3435 09:54:46.044869
3436 09:54:46.047470 Begin, DQ Scan Range 963~1027
3437 09:54:46.047879 Write Rank1 MR14 =0x0
3438 09:54:46.057448
3439 09:54:46.057838 CH=1, VrefRange= 0, VrefLevel = 0
3440 09:54:46.064507 TX Bit0 (990~1002) 13 996, Bit8 (980~991) 12 985,
3441 09:54:46.068221 TX Bit1 (988~1001) 14 994, Bit9 (981~990) 10 985,
3442 09:54:46.073970 TX Bit2 (985~1000) 16 992, Bit10 (983~993) 11 988,
3443 09:54:46.077224 TX Bit3 (984~998) 15 991, Bit11 (983~995) 13 989,
3444 09:54:46.080740 TX Bit4 (986~1003) 18 994, Bit12 (984~994) 11 989,
3445 09:54:46.087534 TX Bit5 (990~1002) 13 996, Bit13 (984~993) 10 988,
3446 09:54:46.090691 TX Bit6 (987~1001) 15 994, Bit14 (983~994) 12 988,
3447 09:54:46.097349 TX Bit7 (988~1002) 15 995, Bit15 (976~987) 12 981,
3448 09:54:46.097870
3449 09:54:46.098274 Write Rank1 MR14 =0x2
3450 09:54:46.106915
3451 09:54:46.107463 CH=1, VrefRange= 0, VrefLevel = 2
3452 09:54:46.114074 TX Bit0 (990~1004) 15 997, Bit8 (980~992) 13 986,
3453 09:54:46.116061 TX Bit1 (988~1002) 15 995, Bit9 (979~991) 13 985,
3454 09:54:46.123141 TX Bit2 (986~1001) 16 993, Bit10 (983~994) 12 988,
3455 09:54:46.126209 TX Bit3 (984~998) 15 991, Bit11 (983~996) 14 989,
3456 09:54:46.129450 TX Bit4 (986~1003) 18 994, Bit12 (983~994) 12 988,
3457 09:54:46.136922 TX Bit5 (989~1002) 14 995, Bit13 (984~994) 11 989,
3458 09:54:46.139519 TX Bit6 (987~1002) 16 994, Bit14 (983~994) 12 988,
3459 09:54:46.146230 TX Bit7 (987~1003) 17 995, Bit15 (976~988) 13 982,
3460 09:54:46.146724
3461 09:54:46.147040 Write Rank1 MR14 =0x4
3462 09:54:46.155697
3463 09:54:46.156090 CH=1, VrefRange= 0, VrefLevel = 4
3464 09:54:46.162771 TX Bit0 (990~1005) 16 997, Bit8 (979~992) 14 985,
3465 09:54:46.165586 TX Bit1 (987~1003) 17 995, Bit9 (979~991) 13 985,
3466 09:54:46.172411 TX Bit2 (985~1002) 18 993, Bit10 (983~994) 12 988,
3467 09:54:46.175966 TX Bit3 (984~999) 16 991, Bit11 (983~996) 14 989,
3468 09:54:46.179951 TX Bit4 (986~1004) 19 995, Bit12 (983~995) 13 989,
3469 09:54:46.186209 TX Bit5 (989~1003) 15 996, Bit13 (984~995) 12 989,
3470 09:54:46.189303 TX Bit6 (987~1003) 17 995, Bit14 (983~995) 13 989,
3471 09:54:46.195943 TX Bit7 (987~1003) 17 995, Bit15 (975~989) 15 982,
3472 09:54:46.196423
3473 09:54:46.196733 Write Rank1 MR14 =0x6
3474 09:54:46.205020
3475 09:54:46.205564 CH=1, VrefRange= 0, VrefLevel = 6
3476 09:54:46.211609 TX Bit0 (989~1006) 18 997, Bit8 (978~992) 15 985,
3477 09:54:46.215097 TX Bit1 (987~1004) 18 995, Bit9 (978~992) 15 985,
3478 09:54:46.221368 TX Bit2 (985~1002) 18 993, Bit10 (982~995) 14 988,
3479 09:54:46.224595 TX Bit3 (983~1000) 18 991, Bit11 (982~998) 17 990,
3480 09:54:46.228294 TX Bit4 (986~1006) 21 996, Bit12 (983~996) 14 989,
3481 09:54:46.235130 TX Bit5 (988~1004) 17 996, Bit13 (983~995) 13 989,
3482 09:54:46.238257 TX Bit6 (986~1004) 19 995, Bit14 (982~996) 15 989,
3483 09:54:46.244885 TX Bit7 (987~1004) 18 995, Bit15 (975~991) 17 983,
3484 09:54:46.245361
3485 09:54:46.245670 Write Rank1 MR14 =0x8
3486 09:54:46.254319
3487 09:54:46.254708 CH=1, VrefRange= 0, VrefLevel = 8
3488 09:54:46.261142 TX Bit0 (988~1006) 19 997, Bit8 (977~993) 17 985,
3489 09:54:46.264889 TX Bit1 (986~1005) 20 995, Bit9 (978~992) 15 985,
3490 09:54:46.270968 TX Bit2 (985~1003) 19 994, Bit10 (982~997) 16 989,
3491 09:54:46.274355 TX Bit3 (983~1001) 19 992, Bit11 (982~999) 18 990,
3492 09:54:46.277613 TX Bit4 (986~1006) 21 996, Bit12 (983~997) 15 990,
3493 09:54:46.284676 TX Bit5 (987~1006) 20 996, Bit13 (983~996) 14 989,
3494 09:54:46.287566 TX Bit6 (986~1005) 20 995, Bit14 (982~997) 16 989,
3495 09:54:46.294071 TX Bit7 (987~1005) 19 996, Bit15 (975~991) 17 983,
3496 09:54:46.294537
3497 09:54:46.294858 Write Rank1 MR14 =0xa
3498 09:54:46.304516
3499 09:54:46.307489 CH=1, VrefRange= 0, VrefLevel = 10
3500 09:54:46.310469 TX Bit0 (988~1006) 19 997, Bit8 (977~993) 17 985,
3501 09:54:46.313906 TX Bit1 (986~1005) 20 995, Bit9 (978~993) 16 985,
3502 09:54:46.320476 TX Bit2 (984~1004) 21 994, Bit10 (981~997) 17 989,
3503 09:54:46.323649 TX Bit3 (983~1001) 19 992, Bit11 (982~999) 18 990,
3504 09:54:46.327243 TX Bit4 (985~1006) 22 995, Bit12 (982~998) 17 990,
3505 09:54:46.334074 TX Bit5 (987~1006) 20 996, Bit13 (983~997) 15 990,
3506 09:54:46.337238 TX Bit6 (986~1005) 20 995, Bit14 (981~997) 17 989,
3507 09:54:46.344247 TX Bit7 (986~1006) 21 996, Bit15 (974~992) 19 983,
3508 09:54:46.344640
3509 09:54:46.344958 Write Rank1 MR14 =0xc
3510 09:54:46.354138
3511 09:54:46.357372 CH=1, VrefRange= 0, VrefLevel = 12
3512 09:54:46.360734 TX Bit0 (987~1007) 21 997, Bit8 (977~994) 18 985,
3513 09:54:46.364256 TX Bit1 (986~1006) 21 996, Bit9 (978~993) 16 985,
3514 09:54:46.370064 TX Bit2 (984~1004) 21 994, Bit10 (980~997) 18 988,
3515 09:54:46.373651 TX Bit3 (982~1002) 21 992, Bit11 (981~999) 19 990,
3516 09:54:46.376731 TX Bit4 (985~1006) 22 995, Bit12 (982~998) 17 990,
3517 09:54:46.384252 TX Bit5 (986~1006) 21 996, Bit13 (983~998) 16 990,
3518 09:54:46.386861 TX Bit6 (986~1006) 21 996, Bit14 (981~998) 18 989,
3519 09:54:46.393362 TX Bit7 (986~1006) 21 996, Bit15 (974~992) 19 983,
3520 09:54:46.393859
3521 09:54:46.394298 Write Rank1 MR14 =0xe
3522 09:54:46.403572
3523 09:54:46.406960 CH=1, VrefRange= 0, VrefLevel = 14
3524 09:54:46.410160 TX Bit0 (987~1007) 21 997, Bit8 (977~994) 18 985,
3525 09:54:46.414026 TX Bit1 (986~1006) 21 996, Bit9 (977~993) 17 985,
3526 09:54:46.419737 TX Bit2 (984~1005) 22 994, Bit10 (979~998) 20 988,
3527 09:54:46.423372 TX Bit3 (982~1002) 21 992, Bit11 (981~999) 19 990,
3528 09:54:46.426588 TX Bit4 (985~1007) 23 996, Bit12 (982~999) 18 990,
3529 09:54:46.433456 TX Bit5 (986~1007) 22 996, Bit13 (982~999) 18 990,
3530 09:54:46.436761 TX Bit6 (986~1006) 21 996, Bit14 (981~998) 18 989,
3531 09:54:46.442938 TX Bit7 (986~1006) 21 996, Bit15 (973~992) 20 982,
3532 09:54:46.443447
3533 09:54:46.443784 Write Rank1 MR14 =0x10
3534 09:54:46.453701
3535 09:54:46.456795 CH=1, VrefRange= 0, VrefLevel = 16
3536 09:54:46.459784 TX Bit0 (987~1007) 21 997, Bit8 (976~995) 20 985,
3537 09:54:46.463109 TX Bit1 (986~1007) 22 996, Bit9 (977~994) 18 985,
3538 09:54:46.470831 TX Bit2 (984~1006) 23 995, Bit10 (979~999) 21 989,
3539 09:54:46.473172 TX Bit3 (982~1003) 22 992, Bit11 (981~1000) 20 990,
3540 09:54:46.477304 TX Bit4 (985~1007) 23 996, Bit12 (981~999) 19 990,
3541 09:54:46.483484 TX Bit5 (986~1007) 22 996, Bit13 (982~999) 18 990,
3542 09:54:46.486660 TX Bit6 (985~1007) 23 996, Bit14 (981~999) 19 990,
3543 09:54:46.493625 TX Bit7 (985~1007) 23 996, Bit15 (972~993) 22 982,
3544 09:54:46.494173
3545 09:54:46.494518 Write Rank1 MR14 =0x12
3546 09:54:46.503659
3547 09:54:46.506299 CH=1, VrefRange= 0, VrefLevel = 18
3548 09:54:46.509903 TX Bit0 (987~1007) 21 997, Bit8 (976~995) 20 985,
3549 09:54:46.513180 TX Bit1 (985~1007) 23 996, Bit9 (976~994) 19 985,
3550 09:54:46.520122 TX Bit2 (983~1006) 24 994, Bit10 (980~999) 20 989,
3551 09:54:46.523587 TX Bit3 (981~1003) 23 992, Bit11 (980~1000) 21 990,
3552 09:54:46.526668 TX Bit4 (985~1007) 23 996, Bit12 (981~999) 19 990,
3553 09:54:46.533116 TX Bit5 (986~1007) 22 996, Bit13 (982~1000) 19 991,
3554 09:54:46.536410 TX Bit6 (985~1007) 23 996, Bit14 (980~999) 20 989,
3555 09:54:46.543074 TX Bit7 (985~1007) 23 996, Bit15 (972~993) 22 982,
3556 09:54:46.543584
3557 09:54:46.543920 Write Rank1 MR14 =0x14
3558 09:54:46.553308
3559 09:54:46.556984 CH=1, VrefRange= 0, VrefLevel = 20
3560 09:54:46.559796 TX Bit0 (986~1008) 23 997, Bit8 (975~996) 22 985,
3561 09:54:46.563701 TX Bit1 (985~1007) 23 996, Bit9 (976~995) 20 985,
3562 09:54:46.570471 TX Bit2 (983~1006) 24 994, Bit10 (978~999) 22 988,
3563 09:54:46.573610 TX Bit3 (981~1004) 24 992, Bit11 (980~1000) 21 990,
3564 09:54:46.576908 TX Bit4 (984~1007) 24 995, Bit12 (981~999) 19 990,
3565 09:54:46.583600 TX Bit5 (986~1007) 22 996, Bit13 (982~1000) 19 991,
3566 09:54:46.586362 TX Bit6 (985~1007) 23 996, Bit14 (979~999) 21 989,
3567 09:54:46.593125 TX Bit7 (985~1007) 23 996, Bit15 (972~994) 23 983,
3568 09:54:46.593621
3569 09:54:46.593960 Write Rank1 MR14 =0x16
3570 09:54:46.603186
3571 09:54:46.606747 CH=1, VrefRange= 0, VrefLevel = 22
3572 09:54:46.610250 TX Bit0 (986~1008) 23 997, Bit8 (975~997) 23 986,
3573 09:54:46.614213 TX Bit1 (985~1007) 23 996, Bit9 (976~995) 20 985,
3574 09:54:46.619805 TX Bit2 (983~1007) 25 995, Bit10 (978~1000) 23 989,
3575 09:54:46.623436 TX Bit3 (981~1005) 25 993, Bit11 (979~1001) 23 990,
3576 09:54:46.629791 TX Bit4 (984~1007) 24 995, Bit12 (980~1000) 21 990,
3577 09:54:46.633345 TX Bit5 (985~1008) 24 996, Bit13 (981~1000) 20 990,
3578 09:54:46.636795 TX Bit6 (985~1007) 23 996, Bit14 (979~1000) 22 989,
3579 09:54:46.643595 TX Bit7 (985~1007) 23 996, Bit15 (971~994) 24 982,
3580 09:54:46.644109
3581 09:54:46.646348 Write Rank1 MR14 =0x18
3582 09:54:46.654214
3583 09:54:46.657730 CH=1, VrefRange= 0, VrefLevel = 24
3584 09:54:46.660659 TX Bit0 (986~1008) 23 997, Bit8 (975~998) 24 986,
3585 09:54:46.663777 TX Bit1 (985~1007) 23 996, Bit9 (975~997) 23 986,
3586 09:54:46.670505 TX Bit2 (984~1007) 24 995, Bit10 (978~1000) 23 989,
3587 09:54:46.674300 TX Bit3 (980~1005) 26 992, Bit11 (979~1001) 23 990,
3588 09:54:46.680372 TX Bit4 (984~1008) 25 996, Bit12 (980~1000) 21 990,
3589 09:54:46.684373 TX Bit5 (985~1008) 24 996, Bit13 (981~1001) 21 991,
3590 09:54:46.686758 TX Bit6 (985~1007) 23 996, Bit14 (979~1000) 22 989,
3591 09:54:46.693602 TX Bit7 (985~1007) 23 996, Bit15 (971~995) 25 983,
3592 09:54:46.694168
3593 09:54:46.697084 Write Rank1 MR14 =0x1a
3594 09:54:46.704158
3595 09:54:46.707523 CH=1, VrefRange= 0, VrefLevel = 26
3596 09:54:46.711147 TX Bit0 (986~1008) 23 997, Bit8 (974~998) 25 986,
3597 09:54:46.714324 TX Bit1 (985~1008) 24 996, Bit9 (975~997) 23 986,
3598 09:54:46.721747 TX Bit2 (983~1007) 25 995, Bit10 (977~1000) 24 988,
3599 09:54:46.724870 TX Bit3 (980~1006) 27 993, Bit11 (978~1001) 24 989,
3600 09:54:46.730815 TX Bit4 (984~1008) 25 996, Bit12 (979~1000) 22 989,
3601 09:54:46.733886 TX Bit5 (985~1008) 24 996, Bit13 (980~1001) 22 990,
3602 09:54:46.737230 TX Bit6 (985~1008) 24 996, Bit14 (979~1000) 22 989,
3603 09:54:46.743812 TX Bit7 (984~1008) 25 996, Bit15 (970~995) 26 982,
3604 09:54:46.744358
3605 09:54:46.746843 Write Rank1 MR14 =0x1c
3606 09:54:46.755218
3607 09:54:46.758083 CH=1, VrefRange= 0, VrefLevel = 28
3608 09:54:46.761740 TX Bit0 (986~1009) 24 997, Bit8 (974~999) 26 986,
3609 09:54:46.764348 TX Bit1 (985~1008) 24 996, Bit9 (975~998) 24 986,
3610 09:54:46.771138 TX Bit2 (983~1007) 25 995, Bit10 (977~1000) 24 988,
3611 09:54:46.774085 TX Bit3 (979~1006) 28 992, Bit11 (978~1001) 24 989,
3612 09:54:46.781499 TX Bit4 (985~1008) 24 996, Bit12 (979~1001) 23 990,
3613 09:54:46.784511 TX Bit5 (985~1008) 24 996, Bit13 (980~1001) 22 990,
3614 09:54:46.787685 TX Bit6 (985~1008) 24 996, Bit14 (978~1000) 23 989,
3615 09:54:46.794734 TX Bit7 (984~1008) 25 996, Bit15 (971~995) 25 983,
3616 09:54:46.795256
3617 09:54:46.797583 Write Rank1 MR14 =0x1e
3618 09:54:46.805650
3619 09:54:46.808861 CH=1, VrefRange= 0, VrefLevel = 30
3620 09:54:46.813023 TX Bit0 (985~1009) 25 997, Bit8 (975~999) 25 987,
3621 09:54:46.815480 TX Bit1 (984~1008) 25 996, Bit9 (974~998) 25 986,
3622 09:54:46.822449 TX Bit2 (982~1007) 26 994, Bit10 (977~1001) 25 989,
3623 09:54:46.825228 TX Bit3 (980~1006) 27 993, Bit11 (978~1000) 23 989,
3624 09:54:46.832271 TX Bit4 (985~1008) 24 996, Bit12 (979~1001) 23 990,
3625 09:54:46.835071 TX Bit5 (985~1009) 25 997, Bit13 (979~1001) 23 990,
3626 09:54:46.838420 TX Bit6 (984~1008) 25 996, Bit14 (978~1000) 23 989,
3627 09:54:46.844992 TX Bit7 (984~1008) 25 996, Bit15 (971~995) 25 983,
3628 09:54:46.845424
3629 09:54:46.845759 Write Rank1 MR14 =0x20
3630 09:54:46.855760
3631 09:54:46.858948 CH=1, VrefRange= 0, VrefLevel = 32
3632 09:54:46.862720 TX Bit0 (985~1009) 25 997, Bit8 (975~999) 25 987,
3633 09:54:46.866226 TX Bit1 (984~1008) 25 996, Bit9 (974~998) 25 986,
3634 09:54:46.872588 TX Bit2 (982~1007) 26 994, Bit10 (977~1001) 25 989,
3635 09:54:46.875791 TX Bit3 (980~1006) 27 993, Bit11 (978~1000) 23 989,
3636 09:54:46.882362 TX Bit4 (985~1008) 24 996, Bit12 (979~1001) 23 990,
3637 09:54:46.885590 TX Bit5 (985~1009) 25 997, Bit13 (979~1001) 23 990,
3638 09:54:46.888959 TX Bit6 (984~1008) 25 996, Bit14 (978~1000) 23 989,
3639 09:54:46.895779 TX Bit7 (984~1008) 25 996, Bit15 (971~995) 25 983,
3640 09:54:46.896214
3641 09:54:46.896667 Write Rank1 MR14 =0x22
3642 09:54:46.906119
3643 09:54:46.909727 CH=1, VrefRange= 0, VrefLevel = 34
3644 09:54:46.912940 TX Bit0 (985~1009) 25 997, Bit8 (975~999) 25 987,
3645 09:54:46.916587 TX Bit1 (984~1008) 25 996, Bit9 (974~998) 25 986,
3646 09:54:46.922695 TX Bit2 (982~1007) 26 994, Bit10 (977~1001) 25 989,
3647 09:54:46.926535 TX Bit3 (980~1006) 27 993, Bit11 (978~1000) 23 989,
3648 09:54:46.932959 TX Bit4 (985~1008) 24 996, Bit12 (979~1001) 23 990,
3649 09:54:46.936240 TX Bit5 (985~1009) 25 997, Bit13 (979~1001) 23 990,
3650 09:54:46.939015 TX Bit6 (984~1008) 25 996, Bit14 (978~1000) 23 989,
3651 09:54:46.946446 TX Bit7 (984~1008) 25 996, Bit15 (971~995) 25 983,
3652 09:54:46.946961
3653 09:54:46.950138 Write Rank1 MR14 =0x24
3654 09:54:46.956817
3655 09:54:46.960077 CH=1, VrefRange= 0, VrefLevel = 36
3656 09:54:46.963599 TX Bit0 (985~1009) 25 997, Bit8 (975~999) 25 987,
3657 09:54:46.967270 TX Bit1 (984~1008) 25 996, Bit9 (974~998) 25 986,
3658 09:54:46.974145 TX Bit2 (982~1007) 26 994, Bit10 (977~1001) 25 989,
3659 09:54:46.976883 TX Bit3 (980~1006) 27 993, Bit11 (978~1000) 23 989,
3660 09:54:46.984036 TX Bit4 (985~1008) 24 996, Bit12 (979~1001) 23 990,
3661 09:54:46.986623 TX Bit5 (985~1009) 25 997, Bit13 (979~1001) 23 990,
3662 09:54:46.990338 TX Bit6 (984~1008) 25 996, Bit14 (978~1000) 23 989,
3663 09:54:46.996889 TX Bit7 (984~1008) 25 996, Bit15 (971~995) 25 983,
3664 09:54:46.997406
3665 09:54:47.000678 Write Rank1 MR14 =0x26
3666 09:54:47.007440
3667 09:54:47.010669 CH=1, VrefRange= 0, VrefLevel = 38
3668 09:54:47.014145 TX Bit0 (985~1009) 25 997, Bit8 (975~999) 25 987,
3669 09:54:47.017545 TX Bit1 (984~1008) 25 996, Bit9 (974~998) 25 986,
3670 09:54:47.024366 TX Bit2 (982~1007) 26 994, Bit10 (977~1001) 25 989,
3671 09:54:47.027069 TX Bit3 (980~1006) 27 993, Bit11 (978~1000) 23 989,
3672 09:54:47.033822 TX Bit4 (985~1008) 24 996, Bit12 (979~1001) 23 990,
3673 09:54:47.037866 TX Bit5 (985~1009) 25 997, Bit13 (979~1001) 23 990,
3674 09:54:47.040957 TX Bit6 (984~1008) 25 996, Bit14 (978~1000) 23 989,
3675 09:54:47.047543 TX Bit7 (984~1008) 25 996, Bit15 (971~995) 25 983,
3676 09:54:47.048053
3677 09:54:47.048389
3678 09:54:47.050725 TX Vref found, early break! 368< 374
3679 09:54:47.053739 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =844/100 ps
3680 09:54:47.057318 u1DelayCellOfst[0]=4 cells (4 PI)
3681 09:54:47.060506 u1DelayCellOfst[1]=3 cells (3 PI)
3682 09:54:47.063867 u1DelayCellOfst[2]=1 cells (1 PI)
3683 09:54:47.067139 u1DelayCellOfst[3]=0 cells (0 PI)
3684 09:54:47.070580 u1DelayCellOfst[4]=3 cells (3 PI)
3685 09:54:47.074725 u1DelayCellOfst[5]=4 cells (4 PI)
3686 09:54:47.077564 u1DelayCellOfst[6]=3 cells (3 PI)
3687 09:54:47.080678 u1DelayCellOfst[7]=3 cells (3 PI)
3688 09:54:47.084046 Byte0, DQ PI dly=993, DQM PI dly= 995
3689 09:54:47.086954 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 33)
3690 09:54:47.087344
3691 09:54:47.090396 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 33)
3692 09:54:47.090874
3693 09:54:47.094066 u1DelayCellOfst[8]=4 cells (4 PI)
3694 09:54:47.097063 u1DelayCellOfst[9]=3 cells (3 PI)
3695 09:54:47.100248 u1DelayCellOfst[10]=6 cells (6 PI)
3696 09:54:47.103654 u1DelayCellOfst[11]=6 cells (6 PI)
3697 09:54:47.106903 u1DelayCellOfst[12]=8 cells (7 PI)
3698 09:54:47.110109 u1DelayCellOfst[13]=8 cells (7 PI)
3699 09:54:47.113532 u1DelayCellOfst[14]=6 cells (6 PI)
3700 09:54:47.116624 u1DelayCellOfst[15]=0 cells (0 PI)
3701 09:54:47.120119 Byte1, DQ PI dly=983, DQM PI dly= 986
3702 09:54:47.123889 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
3703 09:54:47.124368
3704 09:54:47.126815 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
3705 09:54:47.127210
3706 09:54:47.130153 Write Rank1 MR14 =0x1e
3707 09:54:47.130544
3708 09:54:47.133088 Final TX Range 0 Vref 30
3709 09:54:47.133481
3710 09:54:47.140381 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3711 09:54:47.140845
3712 09:54:47.146819 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3713 09:54:47.153634 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3714 09:54:47.159748 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3715 09:54:47.163020 Write Rank1 MR3 =0xb0
3716 09:54:47.163492 DramC Write-DBI on
3717 09:54:47.163799 ==
3718 09:54:47.170105 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3719 09:54:47.173263 fsp= 1, odt_onoff= 1, Byte mode= 0
3720 09:54:47.173771 ==
3721 09:54:47.176303 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3722 09:54:47.176731
3723 09:54:47.180026 Begin, DQ Scan Range 706~770
3724 09:54:47.180536
3725 09:54:47.180931
3726 09:54:47.182934 TX Vref Scan disable
3727 09:54:47.186598 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3728 09:54:47.189949 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3729 09:54:47.193010 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3730 09:54:47.196060 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3731 09:54:47.199731 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3732 09:54:47.202674 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3733 09:54:47.206735 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3734 09:54:47.210071 713 |2 6 9|[0] xxxxxxxx xxxxxxxx [MSB]
3735 09:54:47.212619 714 |2 6 10|[0] xxxxxxxx xxxxxxxx [MSB]
3736 09:54:47.216069 715 |2 6 11|[0] xxxxxxxx xxxxxxxx [MSB]
3737 09:54:47.219282 716 |2 6 12|[0] xxxxxxxx xxxxxxxx [MSB]
3738 09:54:47.222856 717 |2 6 13|[0] xxxxxxxx xxxxxxxx [MSB]
3739 09:54:47.226349 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3740 09:54:47.229576 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3741 09:54:47.232996 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3742 09:54:47.235761 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3743 09:54:47.242869 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3744 09:54:47.246361 723 |2 6 19|[0] xxxxxxxx oooooooo [MSB]
3745 09:54:47.250060 724 |2 6 20|[0] xxxxxxxx oooooooo [MSB]
3746 09:54:47.252440 725 |2 6 21|[0] xxxxxxxx oooooooo [MSB]
3747 09:54:47.256589 726 |2 6 22|[0] xxxxxxxx oooooooo [MSB]
3748 09:54:47.259565 727 |2 6 23|[0] xxxxxxxx oooooooo [MSB]
3749 09:54:47.262766 728 |2 6 24|[0] xxxxxxxx oooooooo [MSB]
3750 09:54:47.269648 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3751 09:54:47.273471 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3752 09:54:47.276144 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3753 09:54:47.280135 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3754 09:54:47.283221 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3755 09:54:47.286631 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3756 09:54:47.289795 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3757 09:54:47.292987 751 |2 6 47|[0] oooooooo xxxxxxxx [MSB]
3758 09:54:47.296533 752 |2 6 48|[0] oooooooo xxxxxxxx [MSB]
3759 09:54:47.299504 753 |2 6 49|[0] oooooooo xxxxxxxx [MSB]
3760 09:54:47.303449 754 |2 6 50|[0] oooooooo xxxxxxxx [MSB]
3761 09:54:47.306023 755 |2 6 51|[0] oooooooo xxxxxxxx [MSB]
3762 09:54:47.309627 756 |2 6 52|[0] xxxxxxxx xxxxxxxx [MSB]
3763 09:54:47.312680 Byte0, DQ PI dly=742, DQM PI dly= 742
3764 09:54:47.319465 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 38)
3765 09:54:47.319917
3766 09:54:47.322586 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 38)
3767 09:54:47.323135
3768 09:54:47.326648 Byte1, DQ PI dly=730, DQM PI dly= 730
3769 09:54:47.329533 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 26)
3770 09:54:47.330087
3771 09:54:47.336026 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 26)
3772 09:54:47.336544
3773 09:54:47.342688 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3774 09:54:47.349395 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3775 09:54:47.356031 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3776 09:54:47.358959 Write Rank1 MR3 =0x30
3777 09:54:47.359396 DramC Write-DBI off
3778 09:54:47.359734
3779 09:54:47.360048 [DATLAT]
3780 09:54:47.363139 Freq=1600, CH1 RK1, use_rxtx_scan=0
3781 09:54:47.363589
3782 09:54:47.365921 DATLAT Default: 0x10
3783 09:54:47.368900 7, 0xFFFF, sum=0
3784 09:54:47.369340 8, 0xFFFF, sum=0
3785 09:54:47.369693 9, 0xFFFF, sum=0
3786 09:54:47.372470 10, 0xFFFF, sum=0
3787 09:54:47.372989 11, 0xFFFF, sum=0
3788 09:54:47.375835 12, 0xFFFF, sum=0
3789 09:54:47.376232 13, 0xFFFF, sum=0
3790 09:54:47.379434 14, 0x0, sum=1
3791 09:54:47.379832 15, 0x0, sum=2
3792 09:54:47.382447 16, 0x0, sum=3
3793 09:54:47.382846 17, 0x0, sum=4
3794 09:54:47.385632 pattern=2 first_step=14 total pass=5 best_step=16
3795 09:54:47.389415 ==
3796 09:54:47.392614 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3797 09:54:47.395290 fsp= 1, odt_onoff= 1, Byte mode= 0
3798 09:54:47.395723 ==
3799 09:54:47.399453 Start DQ dly to find pass range UseTestEngine =1
3800 09:54:47.402619 x-axis: bit #, y-axis: DQ dly (-127~63)
3801 09:54:47.405271 RX Vref Scan = 0
3802 09:54:47.408592 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3803 09:54:47.412587 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3804 09:54:47.415524 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3805 09:54:47.415999 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3806 09:54:47.419287 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3807 09:54:47.422672 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3808 09:54:47.425578 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3809 09:54:47.428778 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3810 09:54:47.432383 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3811 09:54:47.435449 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3812 09:54:47.439007 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3813 09:54:47.439408 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3814 09:54:47.441929 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3815 09:54:47.445290 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3816 09:54:47.449058 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3817 09:54:47.451915 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3818 09:54:47.455045 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3819 09:54:47.458620 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3820 09:54:47.462246 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3821 09:54:47.462646 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3822 09:54:47.465233 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3823 09:54:47.468468 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3824 09:54:47.472038 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3825 09:54:47.474892 -3, [0] xxxxxxxx xxxxxxxx [MSB]
3826 09:54:47.478347 -2, [0] xxxxxxxx xxxxxxxx [MSB]
3827 09:54:47.481605 -1, [0] xxxxxxxx xxxxxxxx [MSB]
3828 09:54:47.482040 0, [0] xxxxxxxx xxxxxxxo [MSB]
3829 09:54:47.484824 1, [0] xxxxxxxx xoxxxxxo [MSB]
3830 09:54:47.488675 2, [0] xxxxxxxx xoxxxxxo [MSB]
3831 09:54:47.492389 3, [0] xxxoxxxx ooxxxxxo [MSB]
3832 09:54:47.495190 4, [0] xxooxxxx ooxxxxxo [MSB]
3833 09:54:47.498664 5, [0] xxooxxxx ooxxxxxo [MSB]
3834 09:54:47.499059 6, [0] xooooxxx ooxxoxxo [MSB]
3835 09:54:47.502184 7, [0] oooooxxx oooooooo [MSB]
3836 09:54:47.504871 8, [0] ooooooxo oooooooo [MSB]
3837 09:54:47.508573 31, [0] oooooooo ooooooox [MSB]
3838 09:54:47.511818 32, [0] oooooooo ooooooox [MSB]
3839 09:54:47.515356 33, [0] oooooooo oxooooox [MSB]
3840 09:54:47.518820 34, [0] oooooooo xxooooox [MSB]
3841 09:54:47.522988 35, [0] oooxoooo xxooooox [MSB]
3842 09:54:47.525328 36, [0] ooxxoooo xxooooox [MSB]
3843 09:54:47.525725 37, [0] ooxxooox xxxoxoxx [MSB]
3844 09:54:47.529029 38, [0] ooxxxoox xxxxxxxx [MSB]
3845 09:54:47.532204 39, [0] oxxxxoox xxxxxxxx [MSB]
3846 09:54:47.535480 40, [0] xxxxxxox xxxxxxxx [MSB]
3847 09:54:47.538570 41, [0] xxxxxxxx xxxxxxxx [MSB]
3848 09:54:47.542110 iDelay=41, Bit 0, Center 23 (7 ~ 39) 33
3849 09:54:47.545572 iDelay=41, Bit 1, Center 22 (6 ~ 38) 33
3850 09:54:47.549078 iDelay=41, Bit 2, Center 19 (4 ~ 35) 32
3851 09:54:47.552054 iDelay=41, Bit 3, Center 18 (3 ~ 34) 32
3852 09:54:47.555527 iDelay=41, Bit 4, Center 21 (6 ~ 37) 32
3853 09:54:47.558546 iDelay=41, Bit 5, Center 23 (8 ~ 39) 32
3854 09:54:47.562596 iDelay=41, Bit 6, Center 24 (9 ~ 40) 32
3855 09:54:47.565451 iDelay=41, Bit 7, Center 22 (8 ~ 36) 29
3856 09:54:47.569353 iDelay=41, Bit 8, Center 18 (3 ~ 33) 31
3857 09:54:47.572229 iDelay=41, Bit 9, Center 16 (1 ~ 32) 32
3858 09:54:47.578875 iDelay=41, Bit 10, Center 21 (7 ~ 36) 30
3859 09:54:47.582259 iDelay=41, Bit 11, Center 22 (7 ~ 37) 31
3860 09:54:47.585533 iDelay=41, Bit 12, Center 21 (6 ~ 36) 31
3861 09:54:47.588760 iDelay=41, Bit 13, Center 22 (7 ~ 37) 31
3862 09:54:47.592155 iDelay=41, Bit 14, Center 21 (7 ~ 36) 30
3863 09:54:47.595672 iDelay=41, Bit 15, Center 15 (0 ~ 30) 31
3864 09:54:47.596163 ==
3865 09:54:47.602355 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3866 09:54:47.605948 fsp= 1, odt_onoff= 1, Byte mode= 0
3867 09:54:47.606456 ==
3868 09:54:47.606766 DQS Delay:
3869 09:54:47.607048 DQS0 = 0, DQS1 = 0
3870 09:54:47.608726 DQM Delay:
3871 09:54:47.609114 DQM0 = 21, DQM1 = 19
3872 09:54:47.611534 DQ Delay:
3873 09:54:47.615497 DQ0 =23, DQ1 =22, DQ2 =19, DQ3 =18
3874 09:54:47.618659 DQ4 =21, DQ5 =23, DQ6 =24, DQ7 =22
3875 09:54:47.621733 DQ8 =18, DQ9 =16, DQ10 =21, DQ11 =22
3876 09:54:47.625535 DQ12 =21, DQ13 =22, DQ14 =21, DQ15 =15
3877 09:54:47.626037
3878 09:54:47.626359
3879 09:54:47.626646
3880 09:54:47.626915 [DramC_TX_OE_Calibration] TA2
3881 09:54:47.628851 Original DQ_B0 (3 6) =30, OEN = 27
3882 09:54:47.631559 Original DQ_B1 (3 6) =30, OEN = 27
3883 09:54:47.635012 23, 0x0, End_B0=23 End_B1=23
3884 09:54:47.638238 24, 0x0, End_B0=24 End_B1=24
3885 09:54:47.641873 25, 0x0, End_B0=25 End_B1=25
3886 09:54:47.645746 26, 0x0, End_B0=26 End_B1=26
3887 09:54:47.646318 27, 0x0, End_B0=27 End_B1=27
3888 09:54:47.648571 28, 0x0, End_B0=28 End_B1=28
3889 09:54:47.651473 29, 0x0, End_B0=29 End_B1=29
3890 09:54:47.654708 30, 0x0, End_B0=30 End_B1=30
3891 09:54:47.658230 31, 0xFFFF, End_B0=30 End_B1=30
3892 09:54:47.661686 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3893 09:54:47.668299 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3894 09:54:47.668817
3895 09:54:47.669150
3896 09:54:47.671768 Write Rank1 MR23 =0x3f
3897 09:54:47.672286 [DQSOSC]
3898 09:54:47.678051 [DQSOSCAuto] RK1, (LSB)MR18= 0xd2d2, (MSB)MR19= 0x202, tDQSOscB0 = 436 ps tDQSOscB1 = 436 ps
3899 09:54:47.685488 CH1_RK1: MR19=0x202, MR18=0xD2D2, DQSOSC=436, MR23=63, INC=12, DEC=19
3900 09:54:47.688900 Write Rank1 MR23 =0x3f
3901 09:54:47.689333 [DQSOSC]
3902 09:54:47.695813 [DQSOSCAuto] RK1, (LSB)MR18= 0xd7d7, (MSB)MR19= 0x202, tDQSOscB0 = 433 ps tDQSOscB1 = 433 ps
3903 09:54:47.698184 CH1 RK1: MR19=202, MR18=D7D7
3904 09:54:47.702550 [RxdqsGatingPostProcess] freq 1600
3905 09:54:47.708569 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3906 09:54:47.709088 Rank: 0
3907 09:54:47.711712 best DQS0 dly(2T, 0.5T) = (2, 6)
3908 09:54:47.714837 best DQS1 dly(2T, 0.5T) = (2, 6)
3909 09:54:47.717836 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3910 09:54:47.721702 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3911 09:54:47.722203 Rank: 1
3912 09:54:47.725000 best DQS0 dly(2T, 0.5T) = (2, 6)
3913 09:54:47.728356 best DQS1 dly(2T, 0.5T) = (2, 6)
3914 09:54:47.731797 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3915 09:54:47.734924 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3916 09:54:47.738336 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3917 09:54:47.741685 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3918 09:54:47.745100 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3919 09:54:47.748275
3920 09:54:47.748789
3921 09:54:47.751240 [Calibration Summary] Freqency 1600
3922 09:54:47.751670 CH 0, Rank 0
3923 09:54:47.752073 All Pass.
3924 09:54:47.752388
3925 09:54:47.754593 CH 0, Rank 1
3926 09:54:47.755023 All Pass.
3927 09:54:47.755370
3928 09:54:47.755676 CH 1, Rank 0
3929 09:54:47.758327 All Pass.
3930 09:54:47.758833
3931 09:54:47.759171 CH 1, Rank 1
3932 09:54:47.759481 All Pass.
3933 09:54:47.759775
3934 09:54:47.764891 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3935 09:54:47.771151 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3936 09:54:47.781541 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3937 09:54:47.782273 Write Rank0 MR3 =0xb0
3938 09:54:47.788325 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3939 09:54:47.794601 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3940 09:54:47.801356 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3941 09:54:47.804910 Write Rank1 MR3 =0xb0
3942 09:54:47.811042 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3943 09:54:47.818316 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3944 09:54:47.824326 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3945 09:54:47.827706 Write Rank0 MR3 =0xb0
3946 09:54:47.834408 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3947 09:54:47.840982 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3948 09:54:47.847519 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3949 09:54:47.847961 Write Rank1 MR3 =0xb0
3950 09:54:47.850952 DramC Write-DBI on
3951 09:54:47.854211 [GetDramInforAfterCalByMRR] Vendor 6.
3952 09:54:47.857453 [GetDramInforAfterCalByMRR] Revision 505.
3953 09:54:47.857889 MR8 1111
3954 09:54:47.863970 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3955 09:54:47.864478 MR8 1111
3956 09:54:47.871186 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3957 09:54:47.871707 MR8 1111
3958 09:54:47.874160 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3959 09:54:47.877901 MR8 1111
3960 09:54:47.880976 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3961 09:54:47.890608 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3962 09:54:47.891132 Write Rank0 MR13 =0xd0
3963 09:54:47.893755 Write Rank1 MR13 =0xd0
3964 09:54:47.897238 Write Rank0 MR13 =0xd0
3965 09:54:47.897756 Write Rank1 MR13 =0xd0
3966 09:54:47.900635 Save calibration result to emmc
3967 09:54:47.901066
3968 09:54:47.901396
3969 09:54:47.903893 [DramcModeReg_Check] Freq_1600, FSP_1
3970 09:54:47.907327 FSP_1, CH_0, RK0
3971 09:54:47.907841 Write Rank0 MR13 =0xd8
3972 09:54:47.910546 MR12 = 0x5e (global = 0x5e) match
3973 09:54:47.914447 MR14 = 0x1e (global = 0x1e) match
3974 09:54:47.916814 FSP_1, CH_0, RK1
3975 09:54:47.917248 Write Rank1 MR13 =0xd8
3976 09:54:47.920261 MR12 = 0x5c (global = 0x5c) match
3977 09:54:47.923899 MR14 = 0x1e (global = 0x1e) match
3978 09:54:47.926915 FSP_1, CH_1, RK0
3979 09:54:47.927385 Write Rank0 MR13 =0xd8
3980 09:54:47.930224 MR12 = 0x5c (global = 0x5c) match
3981 09:54:47.933576 MR14 = 0x1e (global = 0x1e) match
3982 09:54:47.936996 FSP_1, CH_1, RK1
3983 09:54:47.937518 Write Rank1 MR13 =0xd8
3984 09:54:47.940600 MR12 = 0x5c (global = 0x5c) match
3985 09:54:47.943793 MR14 = 0x1e (global = 0x1e) match
3986 09:54:47.944225
3987 09:54:47.950263 [MEM_TEST] 02: After DFS, before run time config
3988 09:54:47.956826 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3989 09:54:47.960220
3990 09:54:47.960730 [TA2_TEST]
3991 09:54:47.961065 === TA2 HW
3992 09:54:47.963601 TA2 PAT: XTALK
3993 09:54:47.966972 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3994 09:54:47.973732 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3995 09:54:47.976700 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3996 09:54:47.980626 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3997 09:54:47.981143
3998 09:54:47.983632
3999 09:54:47.984144 Settings after calibration
4000 09:54:47.984483
4001 09:54:47.986581 [DramcRunTimeConfig]
4002 09:54:47.990010 TransferPLLToSPMControl - MODE SW PHYPLL
4003 09:54:47.990532 TX_TRACKING: ON
4004 09:54:47.993448 RX_TRACKING: ON
4005 09:54:47.994197 HW_GATING: ON
4006 09:54:47.996823 HW_GATING DBG: OFF
4007 09:54:47.997333 ddr_geometry:1
4008 09:54:47.999601 ddr_geometry:1
4009 09:54:48.000032 ddr_geometry:1
4010 09:54:48.000363 ddr_geometry:1
4011 09:54:48.003546 ddr_geometry:1
4012 09:54:48.004055 ddr_geometry:1
4013 09:54:48.006613 ddr_geometry:1
4014 09:54:48.007040 ddr_geometry:1
4015 09:54:48.009616 High Freq DUMMY_READ_FOR_TRACKING: ON
4016 09:54:48.013435 ZQCS_ENABLE_LP4: OFF
4017 09:54:48.016549 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
4018 09:54:48.019417 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
4019 09:54:48.019849 SPM_CONTROL_AFTERK: ON
4020 09:54:48.022842 IMPEDANCE_TRACKING: ON
4021 09:54:48.023230 TEMP_SENSOR: ON
4022 09:54:48.026358 PER_BANK_REFRESH: ON
4023 09:54:48.026750 HW_SAVE_FOR_SR: ON
4024 09:54:48.029695 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4025 09:54:48.032952 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
4026 09:54:48.036667 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
4027 09:54:48.039591 Read ODT Tracking: ON
4028 09:54:48.043105 =========================
4029 09:54:48.043502
4030 09:54:48.043801 [TA2_TEST]
4031 09:54:48.044083 === TA2 HW
4032 09:54:48.049593 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
4033 09:54:48.053224 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
4034 09:54:48.060522 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
4035 09:54:48.062788 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
4036 09:54:48.063194
4037 09:54:48.066475 [MEM_TEST] 03: After run time config
4038 09:54:48.077833 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
4039 09:54:48.080720 [complex_mem_test] start addr:0x40024000, len:131072
4040 09:54:48.285555 1st complex R/W mem test pass
4041 09:54:48.291758 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
4042 09:54:48.295565 sync preloader write leveling
4043 09:54:48.298994 sync preloader cbt_mr12
4044 09:54:48.302067 sync preloader cbt_clk_dly
4045 09:54:48.302586 sync preloader cbt_cmd_dly
4046 09:54:48.305724 sync preloader cbt_cs
4047 09:54:48.309158 sync preloader cbt_ca_perbit_delay
4048 09:54:48.309673 sync preloader clk_delay
4049 09:54:48.311847 sync preloader dqs_delay
4050 09:54:48.315452 sync preloader u1Gating2T_Save
4051 09:54:48.318513 sync preloader u1Gating05T_Save
4052 09:54:48.321952 sync preloader u1Gatingfine_tune_Save
4053 09:54:48.324931 sync preloader u1Gatingucpass_count_Save
4054 09:54:48.328473 sync preloader u1TxWindowPerbitVref_Save
4055 09:54:48.332202 sync preloader u1TxCenter_min_Save
4056 09:54:48.334865 sync preloader u1TxCenter_max_Save
4057 09:54:48.338569 sync preloader u1Txwin_center_Save
4058 09:54:48.342049 sync preloader u1Txfirst_pass_Save
4059 09:54:48.344714 sync preloader u1Txlast_pass_Save
4060 09:54:48.348088 sync preloader u1RxDatlat_Save
4061 09:54:48.351578 sync preloader u1RxWinPerbitVref_Save
4062 09:54:48.354993 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4063 09:54:48.358260 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4064 09:54:48.361863 sync preloader delay_cell_unit
4065 09:54:48.368823 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4066 09:54:48.371564 sync preloader write leveling
4067 09:54:48.371999 sync preloader cbt_mr12
4068 09:54:48.376078 sync preloader cbt_clk_dly
4069 09:54:48.377885 sync preloader cbt_cmd_dly
4070 09:54:48.378352 sync preloader cbt_cs
4071 09:54:48.381392 sync preloader cbt_ca_perbit_delay
4072 09:54:48.384987 sync preloader clk_delay
4073 09:54:48.388056 sync preloader dqs_delay
4074 09:54:48.391943 sync preloader u1Gating2T_Save
4075 09:54:48.392421 sync preloader u1Gating05T_Save
4076 09:54:48.394997 sync preloader u1Gatingfine_tune_Save
4077 09:54:48.401187 sync preloader u1Gatingucpass_count_Save
4078 09:54:48.404315 sync preloader u1TxWindowPerbitVref_Save
4079 09:54:48.408104 sync preloader u1TxCenter_min_Save
4080 09:54:48.408579 sync preloader u1TxCenter_max_Save
4081 09:54:48.411381 sync preloader u1Txwin_center_Save
4082 09:54:48.414251 sync preloader u1Txfirst_pass_Save
4083 09:54:48.417804 sync preloader u1Txlast_pass_Save
4084 09:54:48.421352 sync preloader u1RxDatlat_Save
4085 09:54:48.424296 sync preloader u1RxWinPerbitVref_Save
4086 09:54:48.428039 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4087 09:54:48.434266 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4088 09:54:48.434729 sync preloader delay_cell_unit
4089 09:54:48.440814 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4090 09:54:48.445007 sync preloader write leveling
4091 09:54:48.447767 sync preloader cbt_mr12
4092 09:54:48.450752 sync preloader cbt_clk_dly
4093 09:54:48.451181 sync preloader cbt_cmd_dly
4094 09:54:48.454473 sync preloader cbt_cs
4095 09:54:48.457844 sync preloader cbt_ca_perbit_delay
4096 09:54:48.461049 sync preloader clk_delay
4097 09:54:48.461562 sync preloader dqs_delay
4098 09:54:48.464631 sync preloader u1Gating2T_Save
4099 09:54:48.467595 sync preloader u1Gating05T_Save
4100 09:54:48.471018 sync preloader u1Gatingfine_tune_Save
4101 09:54:48.474091 sync preloader u1Gatingucpass_count_Save
4102 09:54:48.477616 sync preloader u1TxWindowPerbitVref_Save
4103 09:54:48.481192 sync preloader u1TxCenter_min_Save
4104 09:54:48.483829 sync preloader u1TxCenter_max_Save
4105 09:54:48.487372 sync preloader u1Txwin_center_Save
4106 09:54:48.491244 sync preloader u1Txfirst_pass_Save
4107 09:54:48.494823 sync preloader u1Txlast_pass_Save
4108 09:54:48.497401 sync preloader u1RxDatlat_Save
4109 09:54:48.501180 sync preloader u1RxWinPerbitVref_Save
4110 09:54:48.504211 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4111 09:54:48.507650 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4112 09:54:48.510949 sync preloader delay_cell_unit
4113 09:54:48.513893 just_for_test_dump_coreboot_params dump all params
4114 09:54:48.517702 dump source = 0x0
4115 09:54:48.520774 dump params frequency:1600
4116 09:54:48.521331 dump params rank number:2
4117 09:54:48.521681
4118 09:54:48.524017 dump params write leveling
4119 09:54:48.527182 write leveling[0][0][0] = 0x21
4120 09:54:48.530573 write leveling[0][0][1] = 0x17
4121 09:54:48.534037 write leveling[0][1][0] = 0x21
4122 09:54:48.534650 write leveling[0][1][1] = 0x18
4123 09:54:48.537332 write leveling[1][0][0] = 0x22
4124 09:54:48.540702 write leveling[1][0][1] = 0x1f
4125 09:54:48.544060 write leveling[1][1][0] = 0x28
4126 09:54:48.547149 write leveling[1][1][1] = 0x20
4127 09:54:48.547664 dump params cbt_cs
4128 09:54:48.550536 cbt_cs[0][0] = 0x8
4129 09:54:48.551053 cbt_cs[0][1] = 0x8
4130 09:54:48.553886 cbt_cs[1][0] = 0xa
4131 09:54:48.554454 cbt_cs[1][1] = 0xa
4132 09:54:48.556847 dump params cbt_mr12
4133 09:54:48.557278 cbt_mr12[0][0] = 0x1e
4134 09:54:48.560386 cbt_mr12[0][1] = 0x1c
4135 09:54:48.563743 cbt_mr12[1][0] = 0x1c
4136 09:54:48.564255 cbt_mr12[1][1] = 0x1c
4137 09:54:48.567239 dump params tx window
4138 09:54:48.570855 tx_center_min[0][0][0] = 987
4139 09:54:48.571373 tx_center_max[0][0][0] = 993
4140 09:54:48.573599 tx_center_min[0][0][1] = 977
4141 09:54:48.576706 tx_center_max[0][0][1] = 984
4142 09:54:48.580394 tx_center_min[0][1][0] = 987
4143 09:54:48.584238 tx_center_max[0][1][0] = 993
4144 09:54:48.584755 tx_center_min[0][1][1] = 979
4145 09:54:48.587326 tx_center_max[0][1][1] = 986
4146 09:54:48.590384 tx_center_min[1][0][0] = 990
4147 09:54:48.593736 tx_center_max[1][0][0] = 995
4148 09:54:48.596779 tx_center_min[1][0][1] = 982
4149 09:54:48.597176 tx_center_max[1][0][1] = 990
4150 09:54:48.600385 tx_center_min[1][1][0] = 993
4151 09:54:48.603551 tx_center_max[1][1][0] = 997
4152 09:54:48.606863 tx_center_min[1][1][1] = 983
4153 09:54:48.610998 tx_center_max[1][1][1] = 990
4154 09:54:48.611430 dump params tx window
4155 09:54:48.613268 tx_win_center[0][0][0] = 993
4156 09:54:48.616747 tx_first_pass[0][0][0] = 981
4157 09:54:48.617139 tx_last_pass[0][0][0] = 1005
4158 09:54:48.620125 tx_win_center[0][0][1] = 991
4159 09:54:48.623417 tx_first_pass[0][0][1] = 980
4160 09:54:48.626717 tx_last_pass[0][0][1] = 1003
4161 09:54:48.630359 tx_win_center[0][0][2] = 993
4162 09:54:48.630753 tx_first_pass[0][0][2] = 982
4163 09:54:48.633477 tx_last_pass[0][0][2] = 1004
4164 09:54:48.636826 tx_win_center[0][0][3] = 987
4165 09:54:48.640671 tx_first_pass[0][0][3] = 977
4166 09:54:48.643440 tx_last_pass[0][0][3] = 997
4167 09:54:48.643884 tx_win_center[0][0][4] = 991
4168 09:54:48.647266 tx_first_pass[0][0][4] = 980
4169 09:54:48.649927 tx_last_pass[0][0][4] = 1003
4170 09:54:48.653637 tx_win_center[0][0][5] = 989
4171 09:54:48.654088 tx_first_pass[0][0][5] = 979
4172 09:54:48.656472 tx_last_pass[0][0][5] = 1000
4173 09:54:48.659875 tx_win_center[0][0][6] = 990
4174 09:54:48.663288 tx_first_pass[0][0][6] = 979
4175 09:54:48.666861 tx_last_pass[0][0][6] = 1002
4176 09:54:48.667255 tx_win_center[0][0][7] = 991
4177 09:54:48.670108 tx_first_pass[0][0][7] = 980
4178 09:54:48.673343 tx_last_pass[0][0][7] = 1003
4179 09:54:48.676504 tx_win_center[0][0][8] = 977
4180 09:54:48.679808 tx_first_pass[0][0][8] = 966
4181 09:54:48.680201 tx_last_pass[0][0][8] = 989
4182 09:54:48.683412 tx_win_center[0][0][9] = 978
4183 09:54:48.686355 tx_first_pass[0][0][9] = 967
4184 09:54:48.690034 tx_last_pass[0][0][9] = 990
4185 09:54:48.693068 tx_win_center[0][0][10] = 984
4186 09:54:48.693461 tx_first_pass[0][0][10] = 972
4187 09:54:48.696723 tx_last_pass[0][0][10] = 996
4188 09:54:48.699651 tx_win_center[0][0][11] = 978
4189 09:54:48.702750 tx_first_pass[0][0][11] = 967
4190 09:54:48.706156 tx_last_pass[0][0][11] = 989
4191 09:54:48.706549 tx_win_center[0][0][12] = 979
4192 09:54:48.709112 tx_first_pass[0][0][12] = 968
4193 09:54:48.713277 tx_last_pass[0][0][12] = 990
4194 09:54:48.715979 tx_win_center[0][0][13] = 979
4195 09:54:48.719461 tx_first_pass[0][0][13] = 968
4196 09:54:48.720088 tx_last_pass[0][0][13] = 990
4197 09:54:48.722603 tx_win_center[0][0][14] = 979
4198 09:54:48.725643 tx_first_pass[0][0][14] = 968
4199 09:54:48.729333 tx_last_pass[0][0][14] = 991
4200 09:54:48.732669 tx_win_center[0][0][15] = 984
4201 09:54:48.733068 tx_first_pass[0][0][15] = 972
4202 09:54:48.736151 tx_last_pass[0][0][15] = 996
4203 09:54:48.739189 tx_win_center[0][1][0] = 993
4204 09:54:48.742257 tx_first_pass[0][1][0] = 981
4205 09:54:48.746234 tx_last_pass[0][1][0] = 1006
4206 09:54:48.746627 tx_win_center[0][1][1] = 992
4207 09:54:48.749166 tx_first_pass[0][1][1] = 980
4208 09:54:48.752539 tx_last_pass[0][1][1] = 1004
4209 09:54:48.755448 tx_win_center[0][1][2] = 993
4210 09:54:48.759149 tx_first_pass[0][1][2] = 981
4211 09:54:48.759561 tx_last_pass[0][1][2] = 1005
4212 09:54:48.762478 tx_win_center[0][1][3] = 987
4213 09:54:48.765622 tx_first_pass[0][1][3] = 977
4214 09:54:48.769512 tx_last_pass[0][1][3] = 997
4215 09:54:48.770033 tx_win_center[0][1][4] = 992
4216 09:54:48.772384 tx_first_pass[0][1][4] = 980
4217 09:54:48.775735 tx_last_pass[0][1][4] = 1004
4218 09:54:48.780438 tx_win_center[0][1][5] = 989
4219 09:54:48.782351 tx_first_pass[0][1][5] = 978
4220 09:54:48.782745 tx_last_pass[0][1][5] = 1001
4221 09:54:48.785650 tx_win_center[0][1][6] = 990
4222 09:54:48.788861 tx_first_pass[0][1][6] = 979
4223 09:54:48.792347 tx_last_pass[0][1][6] = 1001
4224 09:54:48.795475 tx_win_center[0][1][7] = 991
4225 09:54:48.795871 tx_first_pass[0][1][7] = 980
4226 09:54:48.799228 tx_last_pass[0][1][7] = 1003
4227 09:54:48.802349 tx_win_center[0][1][8] = 979
4228 09:54:48.805834 tx_first_pass[0][1][8] = 968
4229 09:54:48.806268 tx_last_pass[0][1][8] = 991
4230 09:54:48.809235 tx_win_center[0][1][9] = 982
4231 09:54:48.812612 tx_first_pass[0][1][9] = 971
4232 09:54:48.815730 tx_last_pass[0][1][9] = 993
4233 09:54:48.819026 tx_win_center[0][1][10] = 986
4234 09:54:48.819520 tx_first_pass[0][1][10] = 975
4235 09:54:48.822539 tx_last_pass[0][1][10] = 997
4236 09:54:48.825446 tx_win_center[0][1][11] = 980
4237 09:54:48.829222 tx_first_pass[0][1][11] = 969
4238 09:54:48.832258 tx_last_pass[0][1][11] = 992
4239 09:54:48.832744 tx_win_center[0][1][12] = 982
4240 09:54:48.835855 tx_first_pass[0][1][12] = 971
4241 09:54:48.838699 tx_last_pass[0][1][12] = 994
4242 09:54:48.842273 tx_win_center[0][1][13] = 981
4243 09:54:48.845329 tx_first_pass[0][1][13] = 970
4244 09:54:48.845719 tx_last_pass[0][1][13] = 993
4245 09:54:48.848966 tx_win_center[0][1][14] = 983
4246 09:54:48.852824 tx_first_pass[0][1][14] = 971
4247 09:54:48.855316 tx_last_pass[0][1][14] = 995
4248 09:54:48.858855 tx_win_center[0][1][15] = 985
4249 09:54:48.862251 tx_first_pass[0][1][15] = 974
4250 09:54:48.862728 tx_last_pass[0][1][15] = 997
4251 09:54:48.865329 tx_win_center[1][0][0] = 995
4252 09:54:48.869097 tx_first_pass[1][0][0] = 983
4253 09:54:48.873032 tx_last_pass[1][0][0] = 1008
4254 09:54:48.873508 tx_win_center[1][0][1] = 994
4255 09:54:48.875408 tx_first_pass[1][0][1] = 981
4256 09:54:48.878842 tx_last_pass[1][0][1] = 1007
4257 09:54:48.881948 tx_win_center[1][0][2] = 992
4258 09:54:48.885362 tx_first_pass[1][0][2] = 979
4259 09:54:48.885838 tx_last_pass[1][0][2] = 1005
4260 09:54:48.889045 tx_win_center[1][0][3] = 990
4261 09:54:48.891880 tx_first_pass[1][0][3] = 978
4262 09:54:48.895172 tx_last_pass[1][0][3] = 1003
4263 09:54:48.898570 tx_win_center[1][0][4] = 994
4264 09:54:48.899043 tx_first_pass[1][0][4] = 982
4265 09:54:48.902053 tx_last_pass[1][0][4] = 1007
4266 09:54:48.905059 tx_win_center[1][0][5] = 995
4267 09:54:48.908382 tx_first_pass[1][0][5] = 983
4268 09:54:48.911954 tx_last_pass[1][0][5] = 1008
4269 09:54:48.912430 tx_win_center[1][0][6] = 994
4270 09:54:48.914791 tx_first_pass[1][0][6] = 981
4271 09:54:48.918057 tx_last_pass[1][0][6] = 1007
4272 09:54:48.921491 tx_win_center[1][0][7] = 993
4273 09:54:48.921883 tx_first_pass[1][0][7] = 980
4274 09:54:48.925064 tx_last_pass[1][0][7] = 1007
4275 09:54:48.928285 tx_win_center[1][0][8] = 986
4276 09:54:48.931440 tx_first_pass[1][0][8] = 974
4277 09:54:48.935579 tx_last_pass[1][0][8] = 999
4278 09:54:48.936050 tx_win_center[1][0][9] = 986
4279 09:54:48.938040 tx_first_pass[1][0][9] = 974
4280 09:54:48.941489 tx_last_pass[1][0][9] = 998
4281 09:54:48.945256 tx_win_center[1][0][10] = 988
4282 09:54:48.948544 tx_first_pass[1][0][10] = 977
4283 09:54:48.949024 tx_last_pass[1][0][10] = 1000
4284 09:54:48.952159 tx_win_center[1][0][11] = 989
4285 09:54:48.954950 tx_first_pass[1][0][11] = 978
4286 09:54:48.958917 tx_last_pass[1][0][11] = 1001
4287 09:54:48.962118 tx_win_center[1][0][12] = 989
4288 09:54:48.962592 tx_first_pass[1][0][12] = 978
4289 09:54:48.964807 tx_last_pass[1][0][12] = 1000
4290 09:54:48.968335 tx_win_center[1][0][13] = 990
4291 09:54:48.971376 tx_first_pass[1][0][13] = 979
4292 09:54:48.975154 tx_last_pass[1][0][13] = 1001
4293 09:54:48.975655 tx_win_center[1][0][14] = 988
4294 09:54:48.978366 tx_first_pass[1][0][14] = 977
4295 09:54:48.981393 tx_last_pass[1][0][14] = 1000
4296 09:54:48.985460 tx_win_center[1][0][15] = 982
4297 09:54:48.987854 tx_first_pass[1][0][15] = 970
4298 09:54:48.988244 tx_last_pass[1][0][15] = 995
4299 09:54:48.992277 tx_win_center[1][1][0] = 997
4300 09:54:48.995377 tx_first_pass[1][1][0] = 985
4301 09:54:48.998129 tx_last_pass[1][1][0] = 1009
4302 09:54:49.001645 tx_win_center[1][1][1] = 996
4303 09:54:49.002242 tx_first_pass[1][1][1] = 984
4304 09:54:49.004849 tx_last_pass[1][1][1] = 1008
4305 09:54:49.008360 tx_win_center[1][1][2] = 994
4306 09:54:49.012489 tx_first_pass[1][1][2] = 982
4307 09:54:49.015026 tx_last_pass[1][1][2] = 1007
4308 09:54:49.015519 tx_win_center[1][1][3] = 993
4309 09:54:49.018040 tx_first_pass[1][1][3] = 980
4310 09:54:49.021670 tx_last_pass[1][1][3] = 1006
4311 09:54:49.024510 tx_win_center[1][1][4] = 996
4312 09:54:49.027760 tx_first_pass[1][1][4] = 985
4313 09:54:49.028154 tx_last_pass[1][1][4] = 1008
4314 09:54:49.032246 tx_win_center[1][1][5] = 997
4315 09:54:49.034553 tx_first_pass[1][1][5] = 985
4316 09:54:49.038133 tx_last_pass[1][1][5] = 1009
4317 09:54:49.038631 tx_win_center[1][1][6] = 996
4318 09:54:49.041187 tx_first_pass[1][1][6] = 984
4319 09:54:49.044747 tx_last_pass[1][1][6] = 1008
4320 09:54:49.047893 tx_win_center[1][1][7] = 996
4321 09:54:49.051291 tx_first_pass[1][1][7] = 984
4322 09:54:49.051778 tx_last_pass[1][1][7] = 1008
4323 09:54:49.054299 tx_win_center[1][1][8] = 987
4324 09:54:49.057718 tx_first_pass[1][1][8] = 975
4325 09:54:49.061097 tx_last_pass[1][1][8] = 999
4326 09:54:49.064313 tx_win_center[1][1][9] = 986
4327 09:54:49.064785 tx_first_pass[1][1][9] = 974
4328 09:54:49.067668 tx_last_pass[1][1][9] = 998
4329 09:54:49.070971 tx_win_center[1][1][10] = 989
4330 09:54:49.074279 tx_first_pass[1][1][10] = 977
4331 09:54:49.077541 tx_last_pass[1][1][10] = 1001
4332 09:54:49.077930 tx_win_center[1][1][11] = 989
4333 09:54:49.081606 tx_first_pass[1][1][11] = 978
4334 09:54:49.084719 tx_last_pass[1][1][11] = 1000
4335 09:54:49.087520 tx_win_center[1][1][12] = 990
4336 09:54:49.090548 tx_first_pass[1][1][12] = 979
4337 09:54:49.090940 tx_last_pass[1][1][12] = 1001
4338 09:54:49.094300 tx_win_center[1][1][13] = 990
4339 09:54:49.097751 tx_first_pass[1][1][13] = 979
4340 09:54:49.101612 tx_last_pass[1][1][13] = 1001
4341 09:54:49.104609 tx_win_center[1][1][14] = 989
4342 09:54:49.107401 tx_first_pass[1][1][14] = 978
4343 09:54:49.107872 tx_last_pass[1][1][14] = 1000
4344 09:54:49.110922 tx_win_center[1][1][15] = 983
4345 09:54:49.113850 tx_first_pass[1][1][15] = 971
4346 09:54:49.117293 tx_last_pass[1][1][15] = 995
4347 09:54:49.117685 dump params rx window
4348 09:54:49.120529 rx_firspass[0][0][0] = 9
4349 09:54:49.123774 rx_lastpass[0][0][0] = 37
4350 09:54:49.124159 rx_firspass[0][0][1] = 8
4351 09:54:49.127275 rx_lastpass[0][0][1] = 36
4352 09:54:49.130450 rx_firspass[0][0][2] = 11
4353 09:54:49.134005 rx_lastpass[0][0][2] = 37
4354 09:54:49.134399 rx_firspass[0][0][3] = 3
4355 09:54:49.137518 rx_lastpass[0][0][3] = 32
4356 09:54:49.140235 rx_firspass[0][0][4] = 9
4357 09:54:49.140622 rx_lastpass[0][0][4] = 36
4358 09:54:49.143271 rx_firspass[0][0][5] = 5
4359 09:54:49.147002 rx_lastpass[0][0][5] = 32
4360 09:54:49.150225 rx_firspass[0][0][6] = 6
4361 09:54:49.150613 rx_lastpass[0][0][6] = 35
4362 09:54:49.153602 rx_firspass[0][0][7] = 10
4363 09:54:49.157087 rx_lastpass[0][0][7] = 35
4364 09:54:49.157556 rx_firspass[0][0][8] = 4
4365 09:54:49.160165 rx_lastpass[0][0][8] = 31
4366 09:54:49.164602 rx_firspass[0][0][9] = 6
4367 09:54:49.165082 rx_lastpass[0][0][9] = 32
4368 09:54:49.166746 rx_firspass[0][0][10] = 12
4369 09:54:49.170380 rx_lastpass[0][0][10] = 39
4370 09:54:49.173918 rx_firspass[0][0][11] = 5
4371 09:54:49.174435 rx_lastpass[0][0][11] = 31
4372 09:54:49.176938 rx_firspass[0][0][12] = 6
4373 09:54:49.180812 rx_lastpass[0][0][12] = 34
4374 09:54:49.184081 rx_firspass[0][0][13] = 7
4375 09:54:49.184558 rx_lastpass[0][0][13] = 32
4376 09:54:49.187489 rx_firspass[0][0][14] = 8
4377 09:54:49.190531 rx_lastpass[0][0][14] = 35
4378 09:54:49.194080 rx_firspass[0][0][15] = 10
4379 09:54:49.194470 rx_lastpass[0][0][15] = 36
4380 09:54:49.196894 rx_firspass[0][1][0] = 10
4381 09:54:49.200148 rx_lastpass[0][1][0] = 39
4382 09:54:49.200614 rx_firspass[0][1][1] = 8
4383 09:54:49.203764 rx_lastpass[0][1][1] = 39
4384 09:54:49.206958 rx_firspass[0][1][2] = 10
4385 09:54:49.209883 rx_lastpass[0][1][2] = 39
4386 09:54:49.210298 rx_firspass[0][1][3] = 1
4387 09:54:49.213690 rx_lastpass[0][1][3] = 32
4388 09:54:49.216925 rx_firspass[0][1][4] = 10
4389 09:54:49.217395 rx_lastpass[0][1][4] = 38
4390 09:54:49.219626 rx_firspass[0][1][5] = 4
4391 09:54:49.223145 rx_lastpass[0][1][5] = 34
4392 09:54:49.223530 rx_firspass[0][1][6] = 5
4393 09:54:49.226676 rx_lastpass[0][1][6] = 35
4394 09:54:49.229751 rx_firspass[0][1][7] = 7
4395 09:54:49.233892 rx_lastpass[0][1][7] = 37
4396 09:54:49.234407 rx_firspass[0][1][8] = 3
4397 09:54:49.236632 rx_lastpass[0][1][8] = 32
4398 09:54:49.240139 rx_firspass[0][1][9] = 6
4399 09:54:49.240529 rx_lastpass[0][1][9] = 34
4400 09:54:49.243792 rx_firspass[0][1][10] = 12
4401 09:54:49.246480 rx_lastpass[0][1][10] = 41
4402 09:54:49.249589 rx_firspass[0][1][11] = 4
4403 09:54:49.249979 rx_lastpass[0][1][11] = 32
4404 09:54:49.253260 rx_firspass[0][1][12] = 6
4405 09:54:49.256625 rx_lastpass[0][1][12] = 36
4406 09:54:49.257103 rx_firspass[0][1][13] = 8
4407 09:54:49.259854 rx_lastpass[0][1][13] = 34
4408 09:54:49.263104 rx_firspass[0][1][14] = 8
4409 09:54:49.266731 rx_lastpass[0][1][14] = 37
4410 09:54:49.267223 rx_firspass[0][1][15] = 10
4411 09:54:49.270589 rx_lastpass[0][1][15] = 38
4412 09:54:49.273307 rx_firspass[1][0][0] = 7
4413 09:54:49.277128 rx_lastpass[1][0][0] = 37
4414 09:54:49.277521 rx_firspass[1][0][1] = 7
4415 09:54:49.279721 rx_lastpass[1][0][1] = 35
4416 09:54:49.282769 rx_firspass[1][0][2] = 5
4417 09:54:49.283163 rx_lastpass[1][0][2] = 35
4418 09:54:49.285966 rx_firspass[1][0][3] = 5
4419 09:54:49.289649 rx_lastpass[1][0][3] = 32
4420 09:54:49.290238 rx_firspass[1][0][4] = 7
4421 09:54:49.292990 rx_lastpass[1][0][4] = 36
4422 09:54:49.296067 rx_firspass[1][0][5] = 9
4423 09:54:49.300317 rx_lastpass[1][0][5] = 37
4424 09:54:49.300791 rx_firspass[1][0][6] = 11
4425 09:54:49.302774 rx_lastpass[1][0][6] = 37
4426 09:54:49.306993 rx_firspass[1][0][7] = 9
4427 09:54:49.307469 rx_lastpass[1][0][7] = 35
4428 09:54:49.309599 rx_firspass[1][0][8] = 5
4429 09:54:49.313321 rx_lastpass[1][0][8] = 32
4430 09:54:49.313797 rx_firspass[1][0][9] = 3
4431 09:54:49.316537 rx_lastpass[1][0][9] = 31
4432 09:54:49.319624 rx_firspass[1][0][10] = 6
4433 09:54:49.323257 rx_lastpass[1][0][10] = 36
4434 09:54:49.323733 rx_firspass[1][0][11] = 7
4435 09:54:49.326359 rx_lastpass[1][0][11] = 35
4436 09:54:49.331002 rx_firspass[1][0][12] = 8
4437 09:54:49.333324 rx_lastpass[1][0][12] = 35
4438 09:54:49.333796 rx_firspass[1][0][13] = 8
4439 09:54:49.336313 rx_lastpass[1][0][13] = 36
4440 09:54:49.339764 rx_firspass[1][0][14] = 9
4441 09:54:49.340156 rx_lastpass[1][0][14] = 34
4442 09:54:49.342922 rx_firspass[1][0][15] = 2
4443 09:54:49.346524 rx_lastpass[1][0][15] = 28
4444 09:54:49.349822 rx_firspass[1][1][0] = 7
4445 09:54:49.350339 rx_lastpass[1][1][0] = 39
4446 09:54:49.352713 rx_firspass[1][1][1] = 6
4447 09:54:49.356499 rx_lastpass[1][1][1] = 38
4448 09:54:49.356890 rx_firspass[1][1][2] = 4
4449 09:54:49.359587 rx_lastpass[1][1][2] = 35
4450 09:54:49.363473 rx_firspass[1][1][3] = 3
4451 09:54:49.366377 rx_lastpass[1][1][3] = 34
4452 09:54:49.366851 rx_firspass[1][1][4] = 6
4453 09:54:49.369890 rx_lastpass[1][1][4] = 37
4454 09:54:49.373082 rx_firspass[1][1][5] = 8
4455 09:54:49.373479 rx_lastpass[1][1][5] = 39
4456 09:54:49.375908 rx_firspass[1][1][6] = 9
4457 09:54:49.379643 rx_lastpass[1][1][6] = 40
4458 09:54:49.380119 rx_firspass[1][1][7] = 8
4459 09:54:49.382690 rx_lastpass[1][1][7] = 36
4460 09:54:49.386374 rx_firspass[1][1][8] = 3
4461 09:54:49.389222 rx_lastpass[1][1][8] = 33
4462 09:54:49.389612 rx_firspass[1][1][9] = 1
4463 09:54:49.392598 rx_lastpass[1][1][9] = 32
4464 09:54:49.396266 rx_firspass[1][1][10] = 7
4465 09:54:49.396792 rx_lastpass[1][1][10] = 36
4466 09:54:49.398877 rx_firspass[1][1][11] = 7
4467 09:54:49.402628 rx_lastpass[1][1][11] = 37
4468 09:54:49.406062 rx_firspass[1][1][12] = 6
4469 09:54:49.406540 rx_lastpass[1][1][12] = 36
4470 09:54:49.409176 rx_firspass[1][1][13] = 7
4471 09:54:49.412371 rx_lastpass[1][1][13] = 37
4472 09:54:49.412840 rx_firspass[1][1][14] = 7
4473 09:54:49.415414 rx_lastpass[1][1][14] = 36
4474 09:54:49.418692 rx_firspass[1][1][15] = 0
4475 09:54:49.422346 rx_lastpass[1][1][15] = 30
4476 09:54:49.422824 dump params clk_delay
4477 09:54:49.425870 clk_delay[0] = 1
4478 09:54:49.426372 clk_delay[1] = 0
4479 09:54:49.429285 dump params dqs_delay
4480 09:54:49.429759 dqs_delay[0][0] = 0
4481 09:54:49.432266 dqs_delay[0][1] = -1
4482 09:54:49.432664 dqs_delay[1][0] = 0
4483 09:54:49.435719 dqs_delay[1][1] = 0
4484 09:54:49.438611 dump params delay_cell_unit = 844
4485 09:54:49.439001 dump source = 0x0
4486 09:54:49.442481 dump params frequency:1200
4487 09:54:49.445602 dump params rank number:2
4488 09:54:49.446106
4489 09:54:49.448854 dump params write leveling
4490 09:54:49.452360 write leveling[0][0][0] = 0x0
4491 09:54:49.452872 write leveling[0][0][1] = 0x0
4492 09:54:49.455760 write leveling[0][1][0] = 0x0
4493 09:54:49.458601 write leveling[0][1][1] = 0x0
4494 09:54:49.461763 write leveling[1][0][0] = 0x0
4495 09:54:49.465575 write leveling[1][0][1] = 0x0
4496 09:54:49.466110 write leveling[1][1][0] = 0x0
4497 09:54:49.469146 write leveling[1][1][1] = 0x0
4498 09:54:49.471948 dump params cbt_cs
4499 09:54:49.472372 cbt_cs[0][0] = 0x0
4500 09:54:49.475636 cbt_cs[0][1] = 0x0
4501 09:54:49.476149 cbt_cs[1][0] = 0x0
4502 09:54:49.478144 cbt_cs[1][1] = 0x0
4503 09:54:49.478576 dump params cbt_mr12
4504 09:54:49.481692 cbt_mr12[0][0] = 0x0
4505 09:54:49.485041 cbt_mr12[0][1] = 0x0
4506 09:54:49.485703 cbt_mr12[1][0] = 0x0
4507 09:54:49.488070 cbt_mr12[1][1] = 0x0
4508 09:54:49.488501 dump params tx window
4509 09:54:49.491873 tx_center_min[0][0][0] = 0
4510 09:54:49.494589 tx_center_max[0][0][0] = 0
4511 09:54:49.495020 tx_center_min[0][0][1] = 0
4512 09:54:49.498349 tx_center_max[0][0][1] = 0
4513 09:54:49.501738 tx_center_min[0][1][0] = 0
4514 09:54:49.505062 tx_center_max[0][1][0] = 0
4515 09:54:49.505495 tx_center_min[0][1][1] = 0
4516 09:54:49.508578 tx_center_max[0][1][1] = 0
4517 09:54:49.511487 tx_center_min[1][0][0] = 0
4518 09:54:49.514591 tx_center_max[1][0][0] = 0
4519 09:54:49.515105 tx_center_min[1][0][1] = 0
4520 09:54:49.518047 tx_center_max[1][0][1] = 0
4521 09:54:49.520941 tx_center_min[1][1][0] = 0
4522 09:54:49.524687 tx_center_max[1][1][0] = 0
4523 09:54:49.525078 tx_center_min[1][1][1] = 0
4524 09:54:49.528212 tx_center_max[1][1][1] = 0
4525 09:54:49.531339 dump params tx window
4526 09:54:49.531946 tx_win_center[0][0][0] = 0
4527 09:54:49.535185 tx_first_pass[0][0][0] = 0
4528 09:54:49.538169 tx_last_pass[0][0][0] = 0
4529 09:54:49.541330 tx_win_center[0][0][1] = 0
4530 09:54:49.541755 tx_first_pass[0][0][1] = 0
4531 09:54:49.544795 tx_last_pass[0][0][1] = 0
4532 09:54:49.548051 tx_win_center[0][0][2] = 0
4533 09:54:49.550942 tx_first_pass[0][0][2] = 0
4534 09:54:49.551334 tx_last_pass[0][0][2] = 0
4535 09:54:49.554915 tx_win_center[0][0][3] = 0
4536 09:54:49.558421 tx_first_pass[0][0][3] = 0
4537 09:54:49.558943 tx_last_pass[0][0][3] = 0
4538 09:54:49.561688 tx_win_center[0][0][4] = 0
4539 09:54:49.564770 tx_first_pass[0][0][4] = 0
4540 09:54:49.567918 tx_last_pass[0][0][4] = 0
4541 09:54:49.568350 tx_win_center[0][0][5] = 0
4542 09:54:49.571363 tx_first_pass[0][0][5] = 0
4543 09:54:49.574681 tx_last_pass[0][0][5] = 0
4544 09:54:49.577978 tx_win_center[0][0][6] = 0
4545 09:54:49.578552 tx_first_pass[0][0][6] = 0
4546 09:54:49.581438 tx_last_pass[0][0][6] = 0
4547 09:54:49.584389 tx_win_center[0][0][7] = 0
4548 09:54:49.584900 tx_first_pass[0][0][7] = 0
4549 09:54:49.588035 tx_last_pass[0][0][7] = 0
4550 09:54:49.590968 tx_win_center[0][0][8] = 0
4551 09:54:49.594750 tx_first_pass[0][0][8] = 0
4552 09:54:49.595180 tx_last_pass[0][0][8] = 0
4553 09:54:49.597836 tx_win_center[0][0][9] = 0
4554 09:54:49.601366 tx_first_pass[0][0][9] = 0
4555 09:54:49.604658 tx_last_pass[0][0][9] = 0
4556 09:54:49.605176 tx_win_center[0][0][10] = 0
4557 09:54:49.607839 tx_first_pass[0][0][10] = 0
4558 09:54:49.611006 tx_last_pass[0][0][10] = 0
4559 09:54:49.614973 tx_win_center[0][0][11] = 0
4560 09:54:49.615491 tx_first_pass[0][0][11] = 0
4561 09:54:49.617782 tx_last_pass[0][0][11] = 0
4562 09:54:49.621197 tx_win_center[0][0][12] = 0
4563 09:54:49.624485 tx_first_pass[0][0][12] = 0
4564 09:54:49.624919 tx_last_pass[0][0][12] = 0
4565 09:54:49.627872 tx_win_center[0][0][13] = 0
4566 09:54:49.630739 tx_first_pass[0][0][13] = 0
4567 09:54:49.634441 tx_last_pass[0][0][13] = 0
4568 09:54:49.634873 tx_win_center[0][0][14] = 0
4569 09:54:49.637780 tx_first_pass[0][0][14] = 0
4570 09:54:49.640597 tx_last_pass[0][0][14] = 0
4571 09:54:49.643894 tx_win_center[0][0][15] = 0
4572 09:54:49.644324 tx_first_pass[0][0][15] = 0
4573 09:54:49.647183 tx_last_pass[0][0][15] = 0
4574 09:54:49.650876 tx_win_center[0][1][0] = 0
4575 09:54:49.653914 tx_first_pass[0][1][0] = 0
4576 09:54:49.654342 tx_last_pass[0][1][0] = 0
4577 09:54:49.657495 tx_win_center[0][1][1] = 0
4578 09:54:49.660564 tx_first_pass[0][1][1] = 0
4579 09:54:49.661082 tx_last_pass[0][1][1] = 0
4580 09:54:49.664477 tx_win_center[0][1][2] = 0
4581 09:54:49.667201 tx_first_pass[0][1][2] = 0
4582 09:54:49.671007 tx_last_pass[0][1][2] = 0
4583 09:54:49.671483 tx_win_center[0][1][3] = 0
4584 09:54:49.673956 tx_first_pass[0][1][3] = 0
4585 09:54:49.677391 tx_last_pass[0][1][3] = 0
4586 09:54:49.680407 tx_win_center[0][1][4] = 0
4587 09:54:49.680801 tx_first_pass[0][1][4] = 0
4588 09:54:49.684244 tx_last_pass[0][1][4] = 0
4589 09:54:49.687502 tx_win_center[0][1][5] = 0
4590 09:54:49.687977 tx_first_pass[0][1][5] = 0
4591 09:54:49.690964 tx_last_pass[0][1][5] = 0
4592 09:54:49.694653 tx_win_center[0][1][6] = 0
4593 09:54:49.697977 tx_first_pass[0][1][6] = 0
4594 09:54:49.698490 tx_last_pass[0][1][6] = 0
4595 09:54:49.700566 tx_win_center[0][1][7] = 0
4596 09:54:49.704071 tx_first_pass[0][1][7] = 0
4597 09:54:49.707108 tx_last_pass[0][1][7] = 0
4598 09:54:49.707501 tx_win_center[0][1][8] = 0
4599 09:54:49.710348 tx_first_pass[0][1][8] = 0
4600 09:54:49.714393 tx_last_pass[0][1][8] = 0
4601 09:54:49.714924 tx_win_center[0][1][9] = 0
4602 09:54:49.717047 tx_first_pass[0][1][9] = 0
4603 09:54:49.720568 tx_last_pass[0][1][9] = 0
4604 09:54:49.723664 tx_win_center[0][1][10] = 0
4605 09:54:49.724069 tx_first_pass[0][1][10] = 0
4606 09:54:49.726750 tx_last_pass[0][1][10] = 0
4607 09:54:49.731107 tx_win_center[0][1][11] = 0
4608 09:54:49.733646 tx_first_pass[0][1][11] = 0
4609 09:54:49.734086 tx_last_pass[0][1][11] = 0
4610 09:54:49.737695 tx_win_center[0][1][12] = 0
4611 09:54:49.740237 tx_first_pass[0][1][12] = 0
4612 09:54:49.744323 tx_last_pass[0][1][12] = 0
4613 09:54:49.744790 tx_win_center[0][1][13] = 0
4614 09:54:49.747582 tx_first_pass[0][1][13] = 0
4615 09:54:49.750595 tx_last_pass[0][1][13] = 0
4616 09:54:49.753628 tx_win_center[0][1][14] = 0
4617 09:54:49.754172 tx_first_pass[0][1][14] = 0
4618 09:54:49.757048 tx_last_pass[0][1][14] = 0
4619 09:54:49.760330 tx_win_center[0][1][15] = 0
4620 09:54:49.764040 tx_first_pass[0][1][15] = 0
4621 09:54:49.764554 tx_last_pass[0][1][15] = 0
4622 09:54:49.766938 tx_win_center[1][0][0] = 0
4623 09:54:49.769952 tx_first_pass[1][0][0] = 0
4624 09:54:49.773712 tx_last_pass[1][0][0] = 0
4625 09:54:49.774254 tx_win_center[1][0][1] = 0
4626 09:54:49.777608 tx_first_pass[1][0][1] = 0
4627 09:54:49.780626 tx_last_pass[1][0][1] = 0
4628 09:54:49.783930 tx_win_center[1][0][2] = 0
4629 09:54:49.784375 tx_first_pass[1][0][2] = 0
4630 09:54:49.786461 tx_last_pass[1][0][2] = 0
4631 09:54:49.789967 tx_win_center[1][0][3] = 0
4632 09:54:49.790518 tx_first_pass[1][0][3] = 0
4633 09:54:49.793517 tx_last_pass[1][0][3] = 0
4634 09:54:49.797041 tx_win_center[1][0][4] = 0
4635 09:54:49.799936 tx_first_pass[1][0][4] = 0
4636 09:54:49.800369 tx_last_pass[1][0][4] = 0
4637 09:54:49.803409 tx_win_center[1][0][5] = 0
4638 09:54:49.807380 tx_first_pass[1][0][5] = 0
4639 09:54:49.810029 tx_last_pass[1][0][5] = 0
4640 09:54:49.810465 tx_win_center[1][0][6] = 0
4641 09:54:49.813197 tx_first_pass[1][0][6] = 0
4642 09:54:49.816480 tx_last_pass[1][0][6] = 0
4643 09:54:49.816910 tx_win_center[1][0][7] = 0
4644 09:54:49.820599 tx_first_pass[1][0][7] = 0
4645 09:54:49.823774 tx_last_pass[1][0][7] = 0
4646 09:54:49.826551 tx_win_center[1][0][8] = 0
4647 09:54:49.826945 tx_first_pass[1][0][8] = 0
4648 09:54:49.830161 tx_last_pass[1][0][8] = 0
4649 09:54:49.833194 tx_win_center[1][0][9] = 0
4650 09:54:49.836499 tx_first_pass[1][0][9] = 0
4651 09:54:49.836932 tx_last_pass[1][0][9] = 0
4652 09:54:49.840117 tx_win_center[1][0][10] = 0
4653 09:54:49.843060 tx_first_pass[1][0][10] = 0
4654 09:54:49.846280 tx_last_pass[1][0][10] = 0
4655 09:54:49.846744 tx_win_center[1][0][11] = 0
4656 09:54:49.849773 tx_first_pass[1][0][11] = 0
4657 09:54:49.853850 tx_last_pass[1][0][11] = 0
4658 09:54:49.856692 tx_win_center[1][0][12] = 0
4659 09:54:49.857168 tx_first_pass[1][0][12] = 0
4660 09:54:49.859568 tx_last_pass[1][0][12] = 0
4661 09:54:49.863230 tx_win_center[1][0][13] = 0
4662 09:54:49.866751 tx_first_pass[1][0][13] = 0
4663 09:54:49.867190 tx_last_pass[1][0][13] = 0
4664 09:54:49.869594 tx_win_center[1][0][14] = 0
4665 09:54:49.873269 tx_first_pass[1][0][14] = 0
4666 09:54:49.876292 tx_last_pass[1][0][14] = 0
4667 09:54:49.876683 tx_win_center[1][0][15] = 0
4668 09:54:49.879527 tx_first_pass[1][0][15] = 0
4669 09:54:49.882629 tx_last_pass[1][0][15] = 0
4670 09:54:49.886495 tx_win_center[1][1][0] = 0
4671 09:54:49.886886 tx_first_pass[1][1][0] = 0
4672 09:54:49.889691 tx_last_pass[1][1][0] = 0
4673 09:54:49.893839 tx_win_center[1][1][1] = 0
4674 09:54:49.897176 tx_first_pass[1][1][1] = 0
4675 09:54:49.897567 tx_last_pass[1][1][1] = 0
4676 09:54:49.899359 tx_win_center[1][1][2] = 0
4677 09:54:49.902934 tx_first_pass[1][1][2] = 0
4678 09:54:49.903323 tx_last_pass[1][1][2] = 0
4679 09:54:49.906661 tx_win_center[1][1][3] = 0
4680 09:54:49.909267 tx_first_pass[1][1][3] = 0
4681 09:54:49.912704 tx_last_pass[1][1][3] = 0
4682 09:54:49.913181 tx_win_center[1][1][4] = 0
4683 09:54:49.916260 tx_first_pass[1][1][4] = 0
4684 09:54:49.919276 tx_last_pass[1][1][4] = 0
4685 09:54:49.923306 tx_win_center[1][1][5] = 0
4686 09:54:49.923696 tx_first_pass[1][1][5] = 0
4687 09:54:49.926639 tx_last_pass[1][1][5] = 0
4688 09:54:49.929132 tx_win_center[1][1][6] = 0
4689 09:54:49.929520 tx_first_pass[1][1][6] = 0
4690 09:54:49.932796 tx_last_pass[1][1][6] = 0
4691 09:54:49.936747 tx_win_center[1][1][7] = 0
4692 09:54:49.939376 tx_first_pass[1][1][7] = 0
4693 09:54:49.939768 tx_last_pass[1][1][7] = 0
4694 09:54:49.942516 tx_win_center[1][1][8] = 0
4695 09:54:49.946090 tx_first_pass[1][1][8] = 0
4696 09:54:49.948821 tx_last_pass[1][1][8] = 0
4697 09:54:49.949331 tx_win_center[1][1][9] = 0
4698 09:54:49.953351 tx_first_pass[1][1][9] = 0
4699 09:54:49.956622 tx_last_pass[1][1][9] = 0
4700 09:54:49.957184 tx_win_center[1][1][10] = 0
4701 09:54:49.959449 tx_first_pass[1][1][10] = 0
4702 09:54:49.962668 tx_last_pass[1][1][10] = 0
4703 09:54:49.966595 tx_win_center[1][1][11] = 0
4704 09:54:49.967057 tx_first_pass[1][1][11] = 0
4705 09:54:49.969841 tx_last_pass[1][1][11] = 0
4706 09:54:49.973083 tx_win_center[1][1][12] = 0
4707 09:54:49.976039 tx_first_pass[1][1][12] = 0
4708 09:54:49.976542 tx_last_pass[1][1][12] = 0
4709 09:54:49.979414 tx_win_center[1][1][13] = 0
4710 09:54:49.982732 tx_first_pass[1][1][13] = 0
4711 09:54:49.985918 tx_last_pass[1][1][13] = 0
4712 09:54:49.986451 tx_win_center[1][1][14] = 0
4713 09:54:49.989316 tx_first_pass[1][1][14] = 0
4714 09:54:49.992608 tx_last_pass[1][1][14] = 0
4715 09:54:49.995848 tx_win_center[1][1][15] = 0
4716 09:54:49.996353 tx_first_pass[1][1][15] = 0
4717 09:54:49.999298 tx_last_pass[1][1][15] = 0
4718 09:54:50.002717 dump params rx window
4719 09:54:50.003243 rx_firspass[0][0][0] = 0
4720 09:54:50.005829 rx_lastpass[0][0][0] = 0
4721 09:54:50.009058 rx_firspass[0][0][1] = 0
4722 09:54:50.014633 rx_lastpass[0][0][1] = 0
4723 09:54:50.015143 rx_firspass[0][0][2] = 0
4724 09:54:50.015802 rx_lastpass[0][0][2] = 0
4725 09:54:50.019781 rx_firspass[0][0][3] = 0
4726 09:54:50.020325 rx_lastpass[0][0][3] = 0
4727 09:54:50.022562 rx_firspass[0][0][4] = 0
4728 09:54:50.025774 rx_lastpass[0][0][4] = 0
4729 09:54:50.026251 rx_firspass[0][0][5] = 0
4730 09:54:50.028884 rx_lastpass[0][0][5] = 0
4731 09:54:50.032381 rx_firspass[0][0][6] = 0
4732 09:54:50.032809 rx_lastpass[0][0][6] = 0
4733 09:54:50.035436 rx_firspass[0][0][7] = 0
4734 09:54:50.039021 rx_lastpass[0][0][7] = 0
4735 09:54:50.039495 rx_firspass[0][0][8] = 0
4736 09:54:50.042894 rx_lastpass[0][0][8] = 0
4737 09:54:50.045378 rx_firspass[0][0][9] = 0
4738 09:54:50.049384 rx_lastpass[0][0][9] = 0
4739 09:54:50.049810 rx_firspass[0][0][10] = 0
4740 09:54:50.051911 rx_lastpass[0][0][10] = 0
4741 09:54:50.055473 rx_firspass[0][0][11] = 0
4742 09:54:50.055856 rx_lastpass[0][0][11] = 0
4743 09:54:50.059259 rx_firspass[0][0][12] = 0
4744 09:54:50.062457 rx_lastpass[0][0][12] = 0
4745 09:54:50.065658 rx_firspass[0][0][13] = 0
4746 09:54:50.066155 rx_lastpass[0][0][13] = 0
4747 09:54:50.068991 rx_firspass[0][0][14] = 0
4748 09:54:50.072723 rx_lastpass[0][0][14] = 0
4749 09:54:50.073205 rx_firspass[0][0][15] = 0
4750 09:54:50.075561 rx_lastpass[0][0][15] = 0
4751 09:54:50.079242 rx_firspass[0][1][0] = 0
4752 09:54:50.082152 rx_lastpass[0][1][0] = 0
4753 09:54:50.082657 rx_firspass[0][1][1] = 0
4754 09:54:50.085748 rx_lastpass[0][1][1] = 0
4755 09:54:50.089309 rx_firspass[0][1][2] = 0
4756 09:54:50.089810 rx_lastpass[0][1][2] = 0
4757 09:54:50.092456 rx_firspass[0][1][3] = 0
4758 09:54:50.095353 rx_lastpass[0][1][3] = 0
4759 09:54:50.095897 rx_firspass[0][1][4] = 0
4760 09:54:50.098864 rx_lastpass[0][1][4] = 0
4761 09:54:50.101923 rx_firspass[0][1][5] = 0
4762 09:54:50.102466 rx_lastpass[0][1][5] = 0
4763 09:54:50.105174 rx_firspass[0][1][6] = 0
4764 09:54:50.108266 rx_lastpass[0][1][6] = 0
4765 09:54:50.111385 rx_firspass[0][1][7] = 0
4766 09:54:50.111854 rx_lastpass[0][1][7] = 0
4767 09:54:50.114885 rx_firspass[0][1][8] = 0
4768 09:54:50.118357 rx_lastpass[0][1][8] = 0
4769 09:54:50.118783 rx_firspass[0][1][9] = 0
4770 09:54:50.121578 rx_lastpass[0][1][9] = 0
4771 09:54:50.125187 rx_firspass[0][1][10] = 0
4772 09:54:50.125615 rx_lastpass[0][1][10] = 0
4773 09:54:50.129157 rx_firspass[0][1][11] = 0
4774 09:54:50.131455 rx_lastpass[0][1][11] = 0
4775 09:54:50.135086 rx_firspass[0][1][12] = 0
4776 09:54:50.135528 rx_lastpass[0][1][12] = 0
4777 09:54:50.138169 rx_firspass[0][1][13] = 0
4778 09:54:50.141797 rx_lastpass[0][1][13] = 0
4779 09:54:50.142377 rx_firspass[0][1][14] = 0
4780 09:54:50.145052 rx_lastpass[0][1][14] = 0
4781 09:54:50.147659 rx_firspass[0][1][15] = 0
4782 09:54:50.151188 rx_lastpass[0][1][15] = 0
4783 09:54:50.151618 rx_firspass[1][0][0] = 0
4784 09:54:50.154459 rx_lastpass[1][0][0] = 0
4785 09:54:50.158043 rx_firspass[1][0][1] = 0
4786 09:54:50.158434 rx_lastpass[1][0][1] = 0
4787 09:54:50.161497 rx_firspass[1][0][2] = 0
4788 09:54:50.165359 rx_lastpass[1][0][2] = 0
4789 09:54:50.165887 rx_firspass[1][0][3] = 0
4790 09:54:50.168179 rx_lastpass[1][0][3] = 0
4791 09:54:50.171959 rx_firspass[1][0][4] = 0
4792 09:54:50.172475 rx_lastpass[1][0][4] = 0
4793 09:54:50.174693 rx_firspass[1][0][5] = 0
4794 09:54:50.178640 rx_lastpass[1][0][5] = 0
4795 09:54:50.181519 rx_firspass[1][0][6] = 0
4796 09:54:50.182047 rx_lastpass[1][0][6] = 0
4797 09:54:50.184512 rx_firspass[1][0][7] = 0
4798 09:54:50.188734 rx_lastpass[1][0][7] = 0
4799 09:54:50.189246 rx_firspass[1][0][8] = 0
4800 09:54:50.191243 rx_lastpass[1][0][8] = 0
4801 09:54:50.194460 rx_firspass[1][0][9] = 0
4802 09:54:50.194888 rx_lastpass[1][0][9] = 0
4803 09:54:50.198312 rx_firspass[1][0][10] = 0
4804 09:54:50.201102 rx_lastpass[1][0][10] = 0
4805 09:54:50.204234 rx_firspass[1][0][11] = 0
4806 09:54:50.204705 rx_lastpass[1][0][11] = 0
4807 09:54:50.207769 rx_firspass[1][0][12] = 0
4808 09:54:50.210894 rx_lastpass[1][0][12] = 0
4809 09:54:50.211333 rx_firspass[1][0][13] = 0
4810 09:54:50.214253 rx_lastpass[1][0][13] = 0
4811 09:54:50.217135 rx_firspass[1][0][14] = 0
4812 09:54:50.220784 rx_lastpass[1][0][14] = 0
4813 09:54:50.221317 rx_firspass[1][0][15] = 0
4814 09:54:50.224189 rx_lastpass[1][0][15] = 0
4815 09:54:50.227651 rx_firspass[1][1][0] = 0
4816 09:54:50.228083 rx_lastpass[1][1][0] = 0
4817 09:54:50.231167 rx_firspass[1][1][1] = 0
4818 09:54:50.234145 rx_lastpass[1][1][1] = 0
4819 09:54:50.234666 rx_firspass[1][1][2] = 0
4820 09:54:50.238595 rx_lastpass[1][1][2] = 0
4821 09:54:50.240830 rx_firspass[1][1][3] = 0
4822 09:54:50.244059 rx_lastpass[1][1][3] = 0
4823 09:54:50.244666 rx_firspass[1][1][4] = 0
4824 09:54:50.247234 rx_lastpass[1][1][4] = 0
4825 09:54:50.250301 rx_firspass[1][1][5] = 0
4826 09:54:50.250731 rx_lastpass[1][1][5] = 0
4827 09:54:50.253772 rx_firspass[1][1][6] = 0
4828 09:54:50.257520 rx_lastpass[1][1][6] = 0
4829 09:54:50.258099 rx_firspass[1][1][7] = 0
4830 09:54:50.261231 rx_lastpass[1][1][7] = 0
4831 09:54:50.264101 rx_firspass[1][1][8] = 0
4832 09:54:50.264618 rx_lastpass[1][1][8] = 0
4833 09:54:50.266943 rx_firspass[1][1][9] = 0
4834 09:54:50.270656 rx_lastpass[1][1][9] = 0
4835 09:54:50.273655 rx_firspass[1][1][10] = 0
4836 09:54:50.274125 rx_lastpass[1][1][10] = 0
4837 09:54:50.276886 rx_firspass[1][1][11] = 0
4838 09:54:50.280413 rx_lastpass[1][1][11] = 0
4839 09:54:50.280930 rx_firspass[1][1][12] = 0
4840 09:54:50.283528 rx_lastpass[1][1][12] = 0
4841 09:54:50.286920 rx_firspass[1][1][13] = 0
4842 09:54:50.290552 rx_lastpass[1][1][13] = 0
4843 09:54:50.291067 rx_firspass[1][1][14] = 0
4844 09:54:50.293492 rx_lastpass[1][1][14] = 0
4845 09:54:50.296863 rx_firspass[1][1][15] = 0
4846 09:54:50.297384 rx_lastpass[1][1][15] = 0
4847 09:54:50.300170 dump params clk_delay
4848 09:54:50.300680 clk_delay[0] = 0
4849 09:54:50.303379 clk_delay[1] = 0
4850 09:54:50.306728 dump params dqs_delay
4851 09:54:50.307250 dqs_delay[0][0] = 0
4852 09:54:50.309887 dqs_delay[0][1] = 0
4853 09:54:50.310381 dqs_delay[1][0] = 0
4854 09:54:50.313674 dqs_delay[1][1] = 0
4855 09:54:50.317046 dump params delay_cell_unit = 844
4856 09:54:50.317478 dump source = 0x0
4857 09:54:50.320413 dump params frequency:800
4858 09:54:50.323681 dump params rank number:2
4859 09:54:50.324111
4860 09:54:50.324442 dump params write leveling
4861 09:54:50.326868 write leveling[0][0][0] = 0x0
4862 09:54:50.330076 write leveling[0][0][1] = 0x0
4863 09:54:50.333462 write leveling[0][1][0] = 0x0
4864 09:54:50.336721 write leveling[0][1][1] = 0x0
4865 09:54:50.337153 write leveling[1][0][0] = 0x0
4866 09:54:50.339716 write leveling[1][0][1] = 0x0
4867 09:54:50.343588 write leveling[1][1][0] = 0x0
4868 09:54:50.346900 write leveling[1][1][1] = 0x0
4869 09:54:50.347294 dump params cbt_cs
4870 09:54:50.349567 cbt_cs[0][0] = 0x0
4871 09:54:50.349954 cbt_cs[0][1] = 0x0
4872 09:54:50.353561 cbt_cs[1][0] = 0x0
4873 09:54:50.354139 cbt_cs[1][1] = 0x0
4874 09:54:50.356989 dump params cbt_mr12
4875 09:54:50.359942 cbt_mr12[0][0] = 0x0
4876 09:54:50.360332 cbt_mr12[0][1] = 0x0
4877 09:54:50.363617 cbt_mr12[1][0] = 0x0
4878 09:54:50.364007 cbt_mr12[1][1] = 0x0
4879 09:54:50.366261 dump params tx window
4880 09:54:50.369589 tx_center_min[0][0][0] = 0
4881 09:54:50.370101 tx_center_max[0][0][0] = 0
4882 09:54:50.373559 tx_center_min[0][0][1] = 0
4883 09:54:50.376116 tx_center_max[0][0][1] = 0
4884 09:54:50.379745 tx_center_min[0][1][0] = 0
4885 09:54:50.380223 tx_center_max[0][1][0] = 0
4886 09:54:50.382923 tx_center_min[0][1][1] = 0
4887 09:54:50.386374 tx_center_max[0][1][1] = 0
4888 09:54:50.386845 tx_center_min[1][0][0] = 0
4889 09:54:50.389785 tx_center_max[1][0][0] = 0
4890 09:54:50.393014 tx_center_min[1][0][1] = 0
4891 09:54:50.396509 tx_center_max[1][0][1] = 0
4892 09:54:50.396985 tx_center_min[1][1][0] = 0
4893 09:54:50.399879 tx_center_max[1][1][0] = 0
4894 09:54:50.402998 tx_center_min[1][1][1] = 0
4895 09:54:50.406788 tx_center_max[1][1][1] = 0
4896 09:54:50.407188 dump params tx window
4897 09:54:50.409584 tx_win_center[0][0][0] = 0
4898 09:54:50.413268 tx_first_pass[0][0][0] = 0
4899 09:54:50.413660 tx_last_pass[0][0][0] = 0
4900 09:54:50.416570 tx_win_center[0][0][1] = 0
4901 09:54:50.419749 tx_first_pass[0][0][1] = 0
4902 09:54:50.422624 tx_last_pass[0][0][1] = 0
4903 09:54:50.423017 tx_win_center[0][0][2] = 0
4904 09:54:50.425935 tx_first_pass[0][0][2] = 0
4905 09:54:50.429524 tx_last_pass[0][0][2] = 0
4906 09:54:50.433131 tx_win_center[0][0][3] = 0
4907 09:54:50.433525 tx_first_pass[0][0][3] = 0
4908 09:54:50.435930 tx_last_pass[0][0][3] = 0
4909 09:54:50.439733 tx_win_center[0][0][4] = 0
4910 09:54:50.440165 tx_first_pass[0][0][4] = 0
4911 09:54:50.442615 tx_last_pass[0][0][4] = 0
4912 09:54:50.446027 tx_win_center[0][0][5] = 0
4913 09:54:50.449429 tx_first_pass[0][0][5] = 0
4914 09:54:50.449821 tx_last_pass[0][0][5] = 0
4915 09:54:50.453316 tx_win_center[0][0][6] = 0
4916 09:54:50.456562 tx_first_pass[0][0][6] = 0
4917 09:54:50.459111 tx_last_pass[0][0][6] = 0
4918 09:54:50.459505 tx_win_center[0][0][7] = 0
4919 09:54:50.463059 tx_first_pass[0][0][7] = 0
4920 09:54:50.466148 tx_last_pass[0][0][7] = 0
4921 09:54:50.466627 tx_win_center[0][0][8] = 0
4922 09:54:50.469468 tx_first_pass[0][0][8] = 0
4923 09:54:50.472786 tx_last_pass[0][0][8] = 0
4924 09:54:50.476305 tx_win_center[0][0][9] = 0
4925 09:54:50.476788 tx_first_pass[0][0][9] = 0
4926 09:54:50.479616 tx_last_pass[0][0][9] = 0
4927 09:54:50.482686 tx_win_center[0][0][10] = 0
4928 09:54:50.485802 tx_first_pass[0][0][10] = 0
4929 09:54:50.486331 tx_last_pass[0][0][10] = 0
4930 09:54:50.489173 tx_win_center[0][0][11] = 0
4931 09:54:50.492437 tx_first_pass[0][0][11] = 0
4932 09:54:50.496568 tx_last_pass[0][0][11] = 0
4933 09:54:50.497099 tx_win_center[0][0][12] = 0
4934 09:54:50.499253 tx_first_pass[0][0][12] = 0
4935 09:54:50.502451 tx_last_pass[0][0][12] = 0
4936 09:54:50.506588 tx_win_center[0][0][13] = 0
4937 09:54:50.507072 tx_first_pass[0][0][13] = 0
4938 09:54:50.508917 tx_last_pass[0][0][13] = 0
4939 09:54:50.512411 tx_win_center[0][0][14] = 0
4940 09:54:50.515883 tx_first_pass[0][0][14] = 0
4941 09:54:50.516397 tx_last_pass[0][0][14] = 0
4942 09:54:50.518939 tx_win_center[0][0][15] = 0
4943 09:54:50.522612 tx_first_pass[0][0][15] = 0
4944 09:54:50.525282 tx_last_pass[0][0][15] = 0
4945 09:54:50.525674 tx_win_center[0][1][0] = 0
4946 09:54:50.529235 tx_first_pass[0][1][0] = 0
4947 09:54:50.532333 tx_last_pass[0][1][0] = 0
4948 09:54:50.536082 tx_win_center[0][1][1] = 0
4949 09:54:50.536478 tx_first_pass[0][1][1] = 0
4950 09:54:50.538948 tx_last_pass[0][1][1] = 0
4951 09:54:50.542683 tx_win_center[0][1][2] = 0
4952 09:54:50.543158 tx_first_pass[0][1][2] = 0
4953 09:54:50.545466 tx_last_pass[0][1][2] = 0
4954 09:54:50.548649 tx_win_center[0][1][3] = 0
4955 09:54:50.552569 tx_first_pass[0][1][3] = 0
4956 09:54:50.553045 tx_last_pass[0][1][3] = 0
4957 09:54:50.555395 tx_win_center[0][1][4] = 0
4958 09:54:50.559176 tx_first_pass[0][1][4] = 0
4959 09:54:50.561976 tx_last_pass[0][1][4] = 0
4960 09:54:50.562404 tx_win_center[0][1][5] = 0
4961 09:54:50.565502 tx_first_pass[0][1][5] = 0
4962 09:54:50.568582 tx_last_pass[0][1][5] = 0
4963 09:54:50.572465 tx_win_center[0][1][6] = 0
4964 09:54:50.572943 tx_first_pass[0][1][6] = 0
4965 09:54:50.575675 tx_last_pass[0][1][6] = 0
4966 09:54:50.578848 tx_win_center[0][1][7] = 0
4967 09:54:50.579324 tx_first_pass[0][1][7] = 0
4968 09:54:50.582363 tx_last_pass[0][1][7] = 0
4969 09:54:50.585417 tx_win_center[0][1][8] = 0
4970 09:54:50.588680 tx_first_pass[0][1][8] = 0
4971 09:54:50.589072 tx_last_pass[0][1][8] = 0
4972 09:54:50.592615 tx_win_center[0][1][9] = 0
4973 09:54:50.596087 tx_first_pass[0][1][9] = 0
4974 09:54:50.596566 tx_last_pass[0][1][9] = 0
4975 09:54:50.598831 tx_win_center[0][1][10] = 0
4976 09:54:50.602188 tx_first_pass[0][1][10] = 0
4977 09:54:50.605589 tx_last_pass[0][1][10] = 0
4978 09:54:50.606120 tx_win_center[0][1][11] = 0
4979 09:54:50.609172 tx_first_pass[0][1][11] = 0
4980 09:54:50.611725 tx_last_pass[0][1][11] = 0
4981 09:54:50.615428 tx_win_center[0][1][12] = 0
4982 09:54:50.615941 tx_first_pass[0][1][12] = 0
4983 09:54:50.618783 tx_last_pass[0][1][12] = 0
4984 09:54:50.621768 tx_win_center[0][1][13] = 0
4985 09:54:50.625835 tx_first_pass[0][1][13] = 0
4986 09:54:50.626385 tx_last_pass[0][1][13] = 0
4987 09:54:50.628698 tx_win_center[0][1][14] = 0
4988 09:54:50.632464 tx_first_pass[0][1][14] = 0
4989 09:54:50.635607 tx_last_pass[0][1][14] = 0
4990 09:54:50.635999 tx_win_center[0][1][15] = 0
4991 09:54:50.638695 tx_first_pass[0][1][15] = 0
4992 09:54:50.641929 tx_last_pass[0][1][15] = 0
4993 09:54:50.645708 tx_win_center[1][0][0] = 0
4994 09:54:50.646228 tx_first_pass[1][0][0] = 0
4995 09:54:50.648502 tx_last_pass[1][0][0] = 0
4996 09:54:50.652054 tx_win_center[1][0][1] = 0
4997 09:54:50.655546 tx_first_pass[1][0][1] = 0
4998 09:54:50.656026 tx_last_pass[1][0][1] = 0
4999 09:54:50.658984 tx_win_center[1][0][2] = 0
5000 09:54:50.661570 tx_first_pass[1][0][2] = 0
5001 09:54:50.665285 tx_last_pass[1][0][2] = 0
5002 09:54:50.665772 tx_win_center[1][0][3] = 0
5003 09:54:50.668359 tx_first_pass[1][0][3] = 0
5004 09:54:50.672572 tx_last_pass[1][0][3] = 0
5005 09:54:50.673049 tx_win_center[1][0][4] = 0
5006 09:54:50.674964 tx_first_pass[1][0][4] = 0
5007 09:54:50.678508 tx_last_pass[1][0][4] = 0
5008 09:54:50.681791 tx_win_center[1][0][5] = 0
5009 09:54:50.682295 tx_first_pass[1][0][5] = 0
5010 09:54:50.684880 tx_last_pass[1][0][5] = 0
5011 09:54:50.688815 tx_win_center[1][0][6] = 0
5012 09:54:50.691876 tx_first_pass[1][0][6] = 0
5013 09:54:50.692352 tx_last_pass[1][0][6] = 0
5014 09:54:50.695799 tx_win_center[1][0][7] = 0
5015 09:54:50.699196 tx_first_pass[1][0][7] = 0
5016 09:54:50.699670 tx_last_pass[1][0][7] = 0
5017 09:54:50.701933 tx_win_center[1][0][8] = 0
5018 09:54:50.704971 tx_first_pass[1][0][8] = 0
5019 09:54:50.708574 tx_last_pass[1][0][8] = 0
5020 09:54:50.709050 tx_win_center[1][0][9] = 0
5021 09:54:50.711604 tx_first_pass[1][0][9] = 0
5022 09:54:50.715395 tx_last_pass[1][0][9] = 0
5023 09:54:50.718475 tx_win_center[1][0][10] = 0
5024 09:54:50.718947 tx_first_pass[1][0][10] = 0
5025 09:54:50.721486 tx_last_pass[1][0][10] = 0
5026 09:54:50.724810 tx_win_center[1][0][11] = 0
5027 09:54:50.728777 tx_first_pass[1][0][11] = 0
5028 09:54:50.729249 tx_last_pass[1][0][11] = 0
5029 09:54:50.731859 tx_win_center[1][0][12] = 0
5030 09:54:50.734673 tx_first_pass[1][0][12] = 0
5031 09:54:50.738123 tx_last_pass[1][0][12] = 0
5032 09:54:50.738704 tx_win_center[1][0][13] = 0
5033 09:54:50.741978 tx_first_pass[1][0][13] = 0
5034 09:54:50.745077 tx_last_pass[1][0][13] = 0
5035 09:54:50.747959 tx_win_center[1][0][14] = 0
5036 09:54:50.748354 tx_first_pass[1][0][14] = 0
5037 09:54:50.751355 tx_last_pass[1][0][14] = 0
5038 09:54:50.754929 tx_win_center[1][0][15] = 0
5039 09:54:50.757659 tx_first_pass[1][0][15] = 0
5040 09:54:50.758124 tx_last_pass[1][0][15] = 0
5041 09:54:50.761204 tx_win_center[1][1][0] = 0
5042 09:54:50.764519 tx_first_pass[1][1][0] = 0
5043 09:54:50.768146 tx_last_pass[1][1][0] = 0
5044 09:54:50.768654 tx_win_center[1][1][1] = 0
5045 09:54:50.771731 tx_first_pass[1][1][1] = 0
5046 09:54:50.774558 tx_last_pass[1][1][1] = 0
5047 09:54:50.774989 tx_win_center[1][1][2] = 0
5048 09:54:50.777861 tx_first_pass[1][1][2] = 0
5049 09:54:50.781725 tx_last_pass[1][1][2] = 0
5050 09:54:50.784621 tx_win_center[1][1][3] = 0
5051 09:54:50.785101 tx_first_pass[1][1][3] = 0
5052 09:54:50.787830 tx_last_pass[1][1][3] = 0
5053 09:54:50.791452 tx_win_center[1][1][4] = 0
5054 09:54:50.795300 tx_first_pass[1][1][4] = 0
5055 09:54:50.795837 tx_last_pass[1][1][4] = 0
5056 09:54:50.798331 tx_win_center[1][1][5] = 0
5057 09:54:50.801354 tx_first_pass[1][1][5] = 0
5058 09:54:50.801785 tx_last_pass[1][1][5] = 0
5059 09:54:50.805712 tx_win_center[1][1][6] = 0
5060 09:54:50.808113 tx_first_pass[1][1][6] = 0
5061 09:54:50.811022 tx_last_pass[1][1][6] = 0
5062 09:54:50.811492 tx_win_center[1][1][7] = 0
5063 09:54:50.815155 tx_first_pass[1][1][7] = 0
5064 09:54:50.817688 tx_last_pass[1][1][7] = 0
5065 09:54:50.821514 tx_win_center[1][1][8] = 0
5066 09:54:50.822061 tx_first_pass[1][1][8] = 0
5067 09:54:50.824337 tx_last_pass[1][1][8] = 0
5068 09:54:50.827716 tx_win_center[1][1][9] = 0
5069 09:54:50.830667 tx_first_pass[1][1][9] = 0
5070 09:54:50.831100 tx_last_pass[1][1][9] = 0
5071 09:54:50.834632 tx_win_center[1][1][10] = 0
5072 09:54:50.837168 tx_first_pass[1][1][10] = 0
5073 09:54:50.837603 tx_last_pass[1][1][10] = 0
5074 09:54:50.840776 tx_win_center[1][1][11] = 0
5075 09:54:50.843775 tx_first_pass[1][1][11] = 0
5076 09:54:50.847094 tx_last_pass[1][1][11] = 0
5077 09:54:50.850709 tx_win_center[1][1][12] = 0
5078 09:54:50.851155 tx_first_pass[1][1][12] = 0
5079 09:54:50.853925 tx_last_pass[1][1][12] = 0
5080 09:54:50.857267 tx_win_center[1][1][13] = 0
5081 09:54:50.861019 tx_first_pass[1][1][13] = 0
5082 09:54:50.861569 tx_last_pass[1][1][13] = 0
5083 09:54:50.863959 tx_win_center[1][1][14] = 0
5084 09:54:50.868088 tx_first_pass[1][1][14] = 0
5085 09:54:50.871016 tx_last_pass[1][1][14] = 0
5086 09:54:50.871453 tx_win_center[1][1][15] = 0
5087 09:54:50.874101 tx_first_pass[1][1][15] = 0
5088 09:54:50.877412 tx_last_pass[1][1][15] = 0
5089 09:54:50.877842 dump params rx window
5090 09:54:50.880412 rx_firspass[0][0][0] = 0
5091 09:54:50.883756 rx_lastpass[0][0][0] = 0
5092 09:54:50.884188 rx_firspass[0][0][1] = 0
5093 09:54:50.887199 rx_lastpass[0][0][1] = 0
5094 09:54:50.890683 rx_firspass[0][0][2] = 0
5095 09:54:50.893968 rx_lastpass[0][0][2] = 0
5096 09:54:50.894514 rx_firspass[0][0][3] = 0
5097 09:54:50.896838 rx_lastpass[0][0][3] = 0
5098 09:54:50.900204 rx_firspass[0][0][4] = 0
5099 09:54:50.900715 rx_lastpass[0][0][4] = 0
5100 09:54:50.903581 rx_firspass[0][0][5] = 0
5101 09:54:50.906827 rx_lastpass[0][0][5] = 0
5102 09:54:50.907337 rx_firspass[0][0][6] = 0
5103 09:54:50.910803 rx_lastpass[0][0][6] = 0
5104 09:54:50.913764 rx_firspass[0][0][7] = 0
5105 09:54:50.914309 rx_lastpass[0][0][7] = 0
5106 09:54:50.916909 rx_firspass[0][0][8] = 0
5107 09:54:50.920574 rx_lastpass[0][0][8] = 0
5108 09:54:50.923411 rx_firspass[0][0][9] = 0
5109 09:54:50.923844 rx_lastpass[0][0][9] = 0
5110 09:54:50.927458 rx_firspass[0][0][10] = 0
5111 09:54:50.929666 rx_lastpass[0][0][10] = 0
5112 09:54:50.930126 rx_firspass[0][0][11] = 0
5113 09:54:50.932937 rx_lastpass[0][0][11] = 0
5114 09:54:50.936863 rx_firspass[0][0][12] = 0
5115 09:54:50.940107 rx_lastpass[0][0][12] = 0
5116 09:54:50.940536 rx_firspass[0][0][13] = 0
5117 09:54:50.943803 rx_lastpass[0][0][13] = 0
5118 09:54:50.946597 rx_firspass[0][0][14] = 0
5119 09:54:50.947027 rx_lastpass[0][0][14] = 0
5120 09:54:50.949905 rx_firspass[0][0][15] = 0
5121 09:54:50.953384 rx_lastpass[0][0][15] = 0
5122 09:54:50.953907 rx_firspass[0][1][0] = 0
5123 09:54:50.956474 rx_lastpass[0][1][0] = 0
5124 09:54:50.960471 rx_firspass[0][1][1] = 0
5125 09:54:50.962948 rx_lastpass[0][1][1] = 0
5126 09:54:50.963381 rx_firspass[0][1][2] = 0
5127 09:54:50.966580 rx_lastpass[0][1][2] = 0
5128 09:54:50.969966 rx_firspass[0][1][3] = 0
5129 09:54:50.970424 rx_lastpass[0][1][3] = 0
5130 09:54:50.972900 rx_firspass[0][1][4] = 0
5131 09:54:50.976165 rx_lastpass[0][1][4] = 0
5132 09:54:50.976595 rx_firspass[0][1][5] = 0
5133 09:54:50.979761 rx_lastpass[0][1][5] = 0
5134 09:54:50.983017 rx_firspass[0][1][6] = 0
5135 09:54:50.983450 rx_lastpass[0][1][6] = 0
5136 09:54:50.986544 rx_firspass[0][1][7] = 0
5137 09:54:50.989768 rx_lastpass[0][1][7] = 0
5138 09:54:50.990183 rx_firspass[0][1][8] = 0
5139 09:54:50.993301 rx_lastpass[0][1][8] = 0
5140 09:54:50.996225 rx_firspass[0][1][9] = 0
5141 09:54:50.999474 rx_lastpass[0][1][9] = 0
5142 09:54:50.999870 rx_firspass[0][1][10] = 0
5143 09:54:51.003910 rx_lastpass[0][1][10] = 0
5144 09:54:51.006872 rx_firspass[0][1][11] = 0
5145 09:54:51.007296 rx_lastpass[0][1][11] = 0
5146 09:54:51.009666 rx_firspass[0][1][12] = 0
5147 09:54:51.013454 rx_lastpass[0][1][12] = 0
5148 09:54:51.016785 rx_firspass[0][1][13] = 0
5149 09:54:51.017178 rx_lastpass[0][1][13] = 0
5150 09:54:51.020395 rx_firspass[0][1][14] = 0
5151 09:54:51.023127 rx_lastpass[0][1][14] = 0
5152 09:54:51.023564 rx_firspass[0][1][15] = 0
5153 09:54:51.025936 rx_lastpass[0][1][15] = 0
5154 09:54:51.029809 rx_firspass[1][0][0] = 0
5155 09:54:51.032768 rx_lastpass[1][0][0] = 0
5156 09:54:51.033161 rx_firspass[1][0][1] = 0
5157 09:54:51.036636 rx_lastpass[1][0][1] = 0
5158 09:54:51.039532 rx_firspass[1][0][2] = 0
5159 09:54:51.040094 rx_lastpass[1][0][2] = 0
5160 09:54:51.042770 rx_firspass[1][0][3] = 0
5161 09:54:51.046371 rx_lastpass[1][0][3] = 0
5162 09:54:51.046761 rx_firspass[1][0][4] = 0
5163 09:54:51.049675 rx_lastpass[1][0][4] = 0
5164 09:54:51.052865 rx_firspass[1][0][5] = 0
5165 09:54:51.053347 rx_lastpass[1][0][5] = 0
5166 09:54:51.055774 rx_firspass[1][0][6] = 0
5167 09:54:51.058991 rx_lastpass[1][0][6] = 0
5168 09:54:51.059401 rx_firspass[1][0][7] = 0
5169 09:54:51.062820 rx_lastpass[1][0][7] = 0
5170 09:54:51.065859 rx_firspass[1][0][8] = 0
5171 09:54:51.069459 rx_lastpass[1][0][8] = 0
5172 09:54:51.069847 rx_firspass[1][0][9] = 0
5173 09:54:51.072693 rx_lastpass[1][0][9] = 0
5174 09:54:51.076498 rx_firspass[1][0][10] = 0
5175 09:54:51.076970 rx_lastpass[1][0][10] = 0
5176 09:54:51.079162 rx_firspass[1][0][11] = 0
5177 09:54:51.082536 rx_lastpass[1][0][11] = 0
5178 09:54:51.082928 rx_firspass[1][0][12] = 0
5179 09:54:51.085735 rx_lastpass[1][0][12] = 0
5180 09:54:51.089710 rx_firspass[1][0][13] = 0
5181 09:54:51.092600 rx_lastpass[1][0][13] = 0
5182 09:54:51.093034 rx_firspass[1][0][14] = 0
5183 09:54:51.096294 rx_lastpass[1][0][14] = 0
5184 09:54:51.098979 rx_firspass[1][0][15] = 0
5185 09:54:51.099412 rx_lastpass[1][0][15] = 0
5186 09:54:51.102351 rx_firspass[1][1][0] = 0
5187 09:54:51.105972 rx_lastpass[1][1][0] = 0
5188 09:54:51.109281 rx_firspass[1][1][1] = 0
5189 09:54:51.109740 rx_lastpass[1][1][1] = 0
5190 09:54:51.112554 rx_firspass[1][1][2] = 0
5191 09:54:51.115667 rx_lastpass[1][1][2] = 0
5192 09:54:51.116093 rx_firspass[1][1][3] = 0
5193 09:54:51.118946 rx_lastpass[1][1][3] = 0
5194 09:54:51.122318 rx_firspass[1][1][4] = 0
5195 09:54:51.122818 rx_lastpass[1][1][4] = 0
5196 09:54:51.125442 rx_firspass[1][1][5] = 0
5197 09:54:51.129057 rx_lastpass[1][1][5] = 0
5198 09:54:51.129565 rx_firspass[1][1][6] = 0
5199 09:54:51.132189 rx_lastpass[1][1][6] = 0
5200 09:54:51.135551 rx_firspass[1][1][7] = 0
5201 09:54:51.138770 rx_lastpass[1][1][7] = 0
5202 09:54:51.139246 rx_firspass[1][1][8] = 0
5203 09:54:51.142222 rx_lastpass[1][1][8] = 0
5204 09:54:51.145673 rx_firspass[1][1][9] = 0
5205 09:54:51.146063 rx_lastpass[1][1][9] = 0
5206 09:54:51.149060 rx_firspass[1][1][10] = 0
5207 09:54:51.152103 rx_lastpass[1][1][10] = 0
5208 09:54:51.152493 rx_firspass[1][1][11] = 0
5209 09:54:51.155322 rx_lastpass[1][1][11] = 0
5210 09:54:51.158952 rx_firspass[1][1][12] = 0
5211 09:54:51.162040 rx_lastpass[1][1][12] = 0
5212 09:54:51.162494 rx_firspass[1][1][13] = 0
5213 09:54:51.166232 rx_lastpass[1][1][13] = 0
5214 09:54:51.168921 rx_firspass[1][1][14] = 0
5215 09:54:51.169308 rx_lastpass[1][1][14] = 0
5216 09:54:51.172044 rx_firspass[1][1][15] = 0
5217 09:54:51.175246 rx_lastpass[1][1][15] = 0
5218 09:54:51.175716 dump params clk_delay
5219 09:54:51.178796 clk_delay[0] = 0
5220 09:54:51.179182 clk_delay[1] = 0
5221 09:54:51.182139 dump params dqs_delay
5222 09:54:51.185378 dqs_delay[0][0] = 0
5223 09:54:51.185827 dqs_delay[0][1] = 0
5224 09:54:51.188622 dqs_delay[1][0] = 0
5225 09:54:51.189172 dqs_delay[1][1] = 0
5226 09:54:51.191953 dump params delay_cell_unit = 844
5227 09:54:51.195774 mt_set_emi_preloader end
5228 09:54:51.198372 [mt_mem_init] dram size: 0x100000000, rank number: 2
5229 09:54:51.205380 [complex_mem_test] start addr:0x40000000, len:20480
5230 09:54:51.240171 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5231 09:54:51.246950 [complex_mem_test] start addr:0x80000000, len:20480
5232 09:54:51.283084 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5233 09:54:51.289547 [complex_mem_test] start addr:0xc0000000, len:20480
5234 09:54:51.325196 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5235 09:54:51.331785 [complex_mem_test] start addr:0x56000000, len:8192
5236 09:54:51.348402 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5237 09:54:51.348930 ddr_geometry:1
5238 09:54:51.355004 [complex_mem_test] start addr:0x80000000, len:8192
5239 09:54:51.372549 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5240 09:54:51.375417 dram_init: dram init end (result: 0)
5241 09:54:51.382158 Successfully loaded DRAM blobs and ran DRAM calibration
5242 09:54:51.392494 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5243 09:54:51.392998 CBMEM:
5244 09:54:51.395422 IMD: root @ 00000000fffff000 254 entries.
5245 09:54:51.399243 IMD: root @ 00000000ffffec00 62 entries.
5246 09:54:51.405011 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5247 09:54:51.411627 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5248 09:54:51.415381 in-header: 03 a1 00 00 08 00 00 00
5249 09:54:51.418830 in-data: 84 60 60 10 00 00 00 00
5250 09:54:51.421554 Chrome EC: clear events_b mask to 0x0000000020004000
5251 09:54:51.427552 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5252 09:54:51.432445 in-header: 03 fd 00 00 00 00 00 00
5253 09:54:51.435367 in-data:
5254 09:54:51.438819 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5255 09:54:51.441949 CBFS @ 21000 size 3d4000
5256 09:54:51.445147 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5257 09:54:51.449192 CBFS: Locating 'fallback/ramstage'
5258 09:54:51.451743 CBFS: Found @ offset 10d40 size d563
5259 09:54:51.474375 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5260 09:54:51.486132 Accumulated console time in romstage 13744 ms
5261 09:54:51.486697
5262 09:54:51.487032
5263 09:54:51.495937 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5264 09:54:51.499353 ARM64: Exception handlers installed.
5265 09:54:51.499860 ARM64: Testing exception
5266 09:54:51.502575 ARM64: Done test exception
5267 09:54:51.506467 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5268 09:54:51.509636 Manufacturer: ef
5269 09:54:51.512406 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5270 09:54:51.519136 WARNING: RO_VPD is uninitialized or empty.
5271 09:54:51.523501 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5272 09:54:51.525835 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5273 09:54:51.535909 read SPI 0x550600 0x3a00: 4533 us, 3275 KB/s, 26.200 Mbps
5274 09:54:51.540054 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5275 09:54:51.546163 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5276 09:54:51.546667 Enumerating buses...
5277 09:54:51.552631 Show all devs... Before device enumeration.
5278 09:54:51.553141 Root Device: enabled 1
5279 09:54:51.556119 CPU_CLUSTER: 0: enabled 1
5280 09:54:51.556546 CPU: 00: enabled 1
5281 09:54:51.559580 Compare with tree...
5282 09:54:51.562539 Root Device: enabled 1
5283 09:54:51.562966 CPU_CLUSTER: 0: enabled 1
5284 09:54:51.566076 CPU: 00: enabled 1
5285 09:54:51.569357 Root Device scanning...
5286 09:54:51.572397 root_dev_scan_bus for Root Device
5287 09:54:51.572828 CPU_CLUSTER: 0 enabled
5288 09:54:51.575731 root_dev_scan_bus for Root Device done
5289 09:54:51.582116 scan_bus: scanning of bus Root Device took 10690 usecs
5290 09:54:51.582547 done
5291 09:54:51.585473 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5292 09:54:51.588885 Allocating resources...
5293 09:54:51.589389 Reading resources...
5294 09:54:51.595536 Root Device read_resources bus 0 link: 0
5295 09:54:51.598924 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5296 09:54:51.602629 CPU: 00 missing read_resources
5297 09:54:51.605413 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5298 09:54:51.608619 Root Device read_resources bus 0 link: 0 done
5299 09:54:51.612421 Done reading resources.
5300 09:54:51.616078 Show resources in subtree (Root Device)...After reading.
5301 09:54:51.618766 Root Device child on link 0 CPU_CLUSTER: 0
5302 09:54:51.622228 CPU_CLUSTER: 0 child on link 0 CPU: 00
5303 09:54:51.632398 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5304 09:54:51.632906 CPU: 00
5305 09:54:51.635156 Setting resources...
5306 09:54:51.638953 Root Device assign_resources, bus 0 link: 0
5307 09:54:51.642065 CPU_CLUSTER: 0 missing set_resources
5308 09:54:51.645910 Root Device assign_resources, bus 0 link: 0
5309 09:54:51.648601 Done setting resources.
5310 09:54:51.656208 Show resources in subtree (Root Device)...After assigning values.
5311 09:54:51.658721 Root Device child on link 0 CPU_CLUSTER: 0
5312 09:54:51.662522 CPU_CLUSTER: 0 child on link 0 CPU: 00
5313 09:54:51.672236 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5314 09:54:51.672754 CPU: 00
5315 09:54:51.675276 Done allocating resources.
5316 09:54:51.678780 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5317 09:54:51.682392 Enabling resources...
5318 09:54:51.682898 done.
5319 09:54:51.685024 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5320 09:54:51.688281 Initializing devices...
5321 09:54:51.688714 Root Device init ...
5322 09:54:51.694818 mainboard_init: Starting display init.
5323 09:54:51.695318 ADC[4]: Raw value=76301 ID=0
5324 09:54:51.719301 anx7625_power_on_init: Init interface.
5325 09:54:51.721948 anx7625_disable_pd_protocol: Disabled PD feature.
5326 09:54:51.728687 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5327 09:54:51.785787 anx7625_start_dp_work: Secure OCM version=00
5328 09:54:51.788653 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5329 09:54:51.806048 sp_tx_get_edid_block: EDID Block = 1
5330 09:54:51.923349 Extracted contents:
5331 09:54:51.926472 header: 00 ff ff ff ff ff ff 00
5332 09:54:51.930257 serial number: 06 af 5c 14 00 00 00 00 00 1a
5333 09:54:51.933200 version: 01 04
5334 09:54:51.936643 basic params: 95 1a 0e 78 02
5335 09:54:51.940064 chroma info: 99 85 95 55 56 92 28 22 50 54
5336 09:54:51.943652 established: 00 00 00
5337 09:54:51.950316 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5338 09:54:51.952954 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5339 09:54:51.960380 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5340 09:54:51.966692 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5341 09:54:51.973414 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5342 09:54:51.976417 extensions: 00
5343 09:54:51.977018 checksum: ae
5344 09:54:51.977361
5345 09:54:51.979454 Manufacturer: AUO Model 145c Serial Number 0
5346 09:54:51.983135 Made week 0 of 2016
5347 09:54:51.983644 EDID version: 1.4
5348 09:54:51.986334 Digital display
5349 09:54:51.990158 6 bits per primary color channel
5350 09:54:51.990594 DisplayPort interface
5351 09:54:51.992791 Maximum image size: 26 cm x 14 cm
5352 09:54:51.996102 Gamma: 220%
5353 09:54:51.996524 Check DPMS levels
5354 09:54:51.999723 Supported color formats: RGB 4:4:4
5355 09:54:52.002816 First detailed timing is preferred timing
5356 09:54:52.006641 Established timings supported:
5357 09:54:52.009701 Standard timings supported:
5358 09:54:52.010260 Detailed timings
5359 09:54:52.016209 Hex of detail: ce1d56ea50001a3030204600009010000018
5360 09:54:52.019394 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5361 09:54:52.022874 0556 0586 05a6 0640 hborder 0
5362 09:54:52.029013 0300 0304 030a 031a vborder 0
5363 09:54:52.029440 -hsync -vsync
5364 09:54:52.032666 Did detailed timing
5365 09:54:52.035658 Hex of detail: 0000000f0000000000000000000000000020
5366 09:54:52.038862 Manufacturer-specified data, tag 15
5367 09:54:52.045666 Hex of detail: 000000fe0041554f0a202020202020202020
5368 09:54:52.046193 ASCII string: AUO
5369 09:54:52.053092 Hex of detail: 000000fe004231313658414230312e34200a
5370 09:54:52.053708 ASCII string: B116XAB01.4
5371 09:54:52.055872 Checksum
5372 09:54:52.056374 Checksum: 0xae (valid)
5373 09:54:52.062716 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5374 09:54:52.066026 DSI data_rate: 457800000 bps
5375 09:54:52.069709 anx7625_parse_edid: set default k value to 0x3d for panel
5376 09:54:52.072406 anx7625_parse_edid: pixelclock(76300).
5377 09:54:52.079853 hactive(1366), hsync(32), hfp(48), hbp(154)
5378 09:54:52.082702 vactive(768), vsync(6), vfp(4), vbp(16)
5379 09:54:52.085856 anx7625_dsi_config: config dsi.
5380 09:54:52.092299 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5381 09:54:52.112764 anx7625_dsi_config: success to config DSI
5382 09:54:52.116229 anx7625_dp_start: MIPI phy setup OK.
5383 09:54:52.119692 [SSUSB] Setting up USB HOST controller...
5384 09:54:52.122460 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5385 09:54:52.126043 [SSUSB] phy power-on done.
5386 09:54:52.129469 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5387 09:54:52.132597 in-header: 03 fc 01 00 00 00 00 00
5388 09:54:52.133024 in-data:
5389 09:54:52.139341 handle_proto3_response: EC response with error code: 1
5390 09:54:52.139953 SPM: pcm index = 1
5391 09:54:52.145664 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5392 09:54:52.146128 CBFS @ 21000 size 3d4000
5393 09:54:52.152644 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5394 09:54:52.155825 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5395 09:54:52.159383 CBFS: Found @ offset 1e7c0 size 1026
5396 09:54:52.166225 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5397 09:54:52.169826 SPM: binary array size = 2988
5398 09:54:52.173276 SPM: version = pcm_allinone_v1.17.2_20180829
5399 09:54:52.175875 SPM binary loaded in 32 msecs
5400 09:54:52.183761 spm_kick_im_to_fetch: ptr = 000000004021eec2
5401 09:54:52.187134 spm_kick_im_to_fetch: len = 2988
5402 09:54:52.187766 SPM: spm_kick_pcm_to_run
5403 09:54:52.190489 SPM: spm_kick_pcm_to_run done
5404 09:54:52.194147 SPM: spm_init done in 52 msecs
5405 09:54:52.197602 Root Device init finished in 505567 usecs
5406 09:54:52.200979 CPU_CLUSTER: 0 init ...
5407 09:54:52.210613 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5408 09:54:52.213851 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5409 09:54:52.217291 CBFS @ 21000 size 3d4000
5410 09:54:52.220640 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5411 09:54:52.223950 CBFS: Locating 'sspm.bin'
5412 09:54:52.227036 CBFS: Found @ offset 208c0 size 41cb
5413 09:54:52.237348 read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps
5414 09:54:52.244810 CPU_CLUSTER: 0 init finished in 42800 usecs
5415 09:54:52.245329 Devices initialized
5416 09:54:52.248231 Show all devs... After init.
5417 09:54:52.251637 Root Device: enabled 1
5418 09:54:52.252104 CPU_CLUSTER: 0: enabled 1
5419 09:54:52.254914 CPU: 00: enabled 1
5420 09:54:52.258241 BS: BS_DEV_INIT times (ms): entry 0 run 234 exit 0
5421 09:54:52.261974 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5422 09:54:52.264839 ELOG: NV offset 0x558000 size 0x1000
5423 09:54:52.272660 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5424 09:54:52.278848 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5425 09:54:52.282448 ELOG: Event(17) added with size 13 at 2024-06-18 09:54:52 UTC
5426 09:54:52.289151 out: cmd=0x121: 03 db 21 01 00 00 00 00
5427 09:54:52.292468 in-header: 03 57 00 00 2c 00 00 00
5428 09:54:52.302339 in-data: a9 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 c1 c3 00 00 06 80 00 00 2b 9d 01 00 06 80 00 00 46 d5 00 00 06 80 00 00 43 b0 01 00
5429 09:54:52.305479 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5430 09:54:52.309117 in-header: 03 19 00 00 08 00 00 00
5431 09:54:52.312471 in-data: a2 e0 47 00 13 00 00 00
5432 09:54:52.315510 Chrome EC: UHEPI supported
5433 09:54:52.322123 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5434 09:54:52.325566 in-header: 03 e1 00 00 08 00 00 00
5435 09:54:52.328884 in-data: 84 20 60 10 00 00 00 00
5436 09:54:52.331937 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5437 09:54:52.338707 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5438 09:54:52.342588 in-header: 03 e1 00 00 08 00 00 00
5439 09:54:52.345279 in-data: 84 20 60 10 00 00 00 00
5440 09:54:52.352116 ELOG: Event(A1) added with size 10 at 2024-06-18 09:54:52 UTC
5441 09:54:52.358278 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5442 09:54:52.365931 ELOG: Event(A0) added with size 9 at 2024-06-18 09:54:52 UTC
5443 09:54:52.368777 elog_add_boot_reason: Logged dev mode boot
5444 09:54:52.369287 Finalize devices...
5445 09:54:52.371823 Devices finalized
5446 09:54:52.375003 BS: BS_POST_DEVICE times (ms): entry 2 run 0 exit 0
5447 09:54:52.381777 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5448 09:54:52.385373 ELOG: Event(91) added with size 10 at 2024-06-18 09:54:52 UTC
5449 09:54:52.388321 Writing coreboot table at 0xffeda000
5450 09:54:52.394751 0. 0000000000114000-000000000011efff: RAMSTAGE
5451 09:54:52.398293 1. 0000000040000000-000000004023cfff: RAMSTAGE
5452 09:54:52.401422 2. 000000004023d000-00000000545fffff: RAM
5453 09:54:52.404836 3. 0000000054600000-000000005465ffff: BL31
5454 09:54:52.408250 4. 0000000054660000-00000000ffed9fff: RAM
5455 09:54:52.414948 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5456 09:54:52.418477 6. 0000000100000000-000000013fffffff: RAM
5457 09:54:52.421759 Passing 5 GPIOs to payload:
5458 09:54:52.424616 NAME | PORT | POLARITY | VALUE
5459 09:54:52.431222 write protect | 0x00000096 | low | low
5460 09:54:52.434455 EC in RW | 0x000000b1 | high | undefined
5461 09:54:52.438209 EC interrupt | 0x00000097 | low | undefined
5462 09:54:52.444981 TPM interrupt | 0x00000099 | high | undefined
5463 09:54:52.448029 speaker enable | 0x000000af | high | undefined
5464 09:54:52.451787 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5465 09:54:52.454649 in-header: 03 f7 00 00 02 00 00 00
5466 09:54:52.457926 in-data: 04 00
5467 09:54:52.458366 Board ID: 4
5468 09:54:52.461571 ADC[3]: Raw value=216068 ID=1
5469 09:54:52.461978 RAM code: 1
5470 09:54:52.464362 SKU ID: 16
5471 09:54:52.468063 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5472 09:54:52.471268 CBFS @ 21000 size 3d4000
5473 09:54:52.474304 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5474 09:54:52.481434 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum cf92
5475 09:54:52.484698 coreboot table: 940 bytes.
5476 09:54:52.488324 IMD ROOT 0. 00000000fffff000 00001000
5477 09:54:52.491149 IMD SMALL 1. 00000000ffffe000 00001000
5478 09:54:52.494475 CONSOLE 2. 00000000fffde000 00020000
5479 09:54:52.497488 FMAP 3. 00000000fffdd000 0000047c
5480 09:54:52.501292 TIME STAMP 4. 00000000fffdc000 00000910
5481 09:54:52.504580 RAMOOPS 5. 00000000ffedc000 00100000
5482 09:54:52.507863 COREBOOT 6. 00000000ffeda000 00002000
5483 09:54:52.511197 IMD small region:
5484 09:54:52.514630 IMD ROOT 0. 00000000ffffec00 00000400
5485 09:54:52.517604 VBOOT WORK 1. 00000000ffffeb00 00000100
5486 09:54:52.520935 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5487 09:54:52.524329 VPD 3. 00000000ffffea60 0000006c
5488 09:54:52.530753 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5489 09:54:52.537842 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5490 09:54:52.541110 in-header: 03 e1 00 00 08 00 00 00
5491 09:54:52.544634 in-data: 84 20 60 10 00 00 00 00
5492 09:54:52.547452 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5493 09:54:52.551163 CBFS @ 21000 size 3d4000
5494 09:54:52.554261 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5495 09:54:52.557730 CBFS: Locating 'fallback/payload'
5496 09:54:52.566612 CBFS: Found @ offset dc040 size 439a0
5497 09:54:52.654295 read SPI 0xfd078 0x439a0: 84380 us, 3281 KB/s, 26.248 Mbps
5498 09:54:52.657627 Checking segment from ROM address 0x0000000040003a00
5499 09:54:52.665002 Checking segment from ROM address 0x0000000040003a1c
5500 09:54:52.667894 Loading segment from ROM address 0x0000000040003a00
5501 09:54:52.671635 code (compression=0)
5502 09:54:52.681595 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5503 09:54:52.688383 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5504 09:54:52.691336 it's not compressed!
5505 09:54:52.694356 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5506 09:54:52.700839 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5507 09:54:52.709257 Loading segment from ROM address 0x0000000040003a1c
5508 09:54:52.712160 Entry Point 0x0000000080000000
5509 09:54:52.712672 Loaded segments
5510 09:54:52.718968 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5511 09:54:52.722707 Jumping to boot code at 0000000080000000(00000000ffeda000)
5512 09:54:52.732305 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5513 09:54:52.735541 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5514 09:54:52.738543 CBFS @ 21000 size 3d4000
5515 09:54:52.745598 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5516 09:54:52.748249 CBFS: Locating 'fallback/bl31'
5517 09:54:52.751596 CBFS: Found @ offset 36dc0 size 5820
5518 09:54:52.762752 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5519 09:54:52.766366 Checking segment from ROM address 0x0000000040003a00
5520 09:54:52.772630 Checking segment from ROM address 0x0000000040003a1c
5521 09:54:52.776151 Loading segment from ROM address 0x0000000040003a00
5522 09:54:52.779266 code (compression=1)
5523 09:54:52.786171 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5524 09:54:52.795967 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5525 09:54:52.796485 using LZMA
5526 09:54:52.804875 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5527 09:54:52.811156 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5528 09:54:52.814976 Loading segment from ROM address 0x0000000040003a1c
5529 09:54:52.818189 Entry Point 0x0000000054601000
5530 09:54:52.818621 Loaded segments
5531 09:54:52.821341 NOTICE: MT8183 bl31_setup
5532 09:54:52.828200 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5533 09:54:52.832152 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5534 09:54:52.835390 INFO: [DEVAPC] dump DEVAPC registers:
5535 09:54:52.845053 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5536 09:54:52.852056 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5537 09:54:52.861566 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5538 09:54:52.867946 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5539 09:54:52.878956 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5540 09:54:52.885163 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5541 09:54:52.894738 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5542 09:54:52.902260 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5543 09:54:52.908355 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5544 09:54:52.918879 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5545 09:54:52.925456 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5546 09:54:52.934844 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5547 09:54:52.941330 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5548 09:54:52.950986 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5549 09:54:52.957580 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5550 09:54:52.964631 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5551 09:54:52.971222 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5552 09:54:52.977354 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5553 09:54:52.988058 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5554 09:54:52.993889 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5555 09:54:53.000870 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5556 09:54:53.007653 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5557 09:54:53.010261 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5558 09:54:53.013607 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5559 09:54:53.016982 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5560 09:54:53.021108 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5561 09:54:53.024113 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5562 09:54:53.030396 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5563 09:54:53.037107 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5564 09:54:53.037628 WARNING: region 0:
5565 09:54:53.039952 WARNING: apc:0x168, sa:0x0, ea:0xfff
5566 09:54:53.043510 WARNING: region 1:
5567 09:54:53.047201 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5568 09:54:53.047723 WARNING: region 2:
5569 09:54:53.053399 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5570 09:54:53.053831 WARNING: region 3:
5571 09:54:53.056954 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5572 09:54:53.060352 WARNING: region 4:
5573 09:54:53.063016 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5574 09:54:53.063477 WARNING: region 5:
5575 09:54:53.066385 WARNING: apc:0x0, sa:0x0, ea:0x0
5576 09:54:53.069540 WARNING: region 6:
5577 09:54:53.073530 WARNING: apc:0x0, sa:0x0, ea:0x0
5578 09:54:53.074092 WARNING: region 7:
5579 09:54:53.076767 WARNING: apc:0x0, sa:0x0, ea:0x0
5580 09:54:53.083551 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5581 09:54:53.086686 INFO: SPM: enable SPMC mode
5582 09:54:53.089739 NOTICE: spm_boot_init() start
5583 09:54:53.093811 NOTICE: spm_boot_init() end
5584 09:54:53.096515 INFO: BL31: Initializing runtime services
5585 09:54:53.103396 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5586 09:54:53.106540 INFO: BL31: Preparing for EL3 exit to normal world
5587 09:54:53.109714 INFO: Entry point address = 0x80000000
5588 09:54:53.112990 INFO: SPSR = 0x8
5589 09:54:53.135036
5590 09:54:53.135659
5591 09:54:53.136116
5592 09:54:53.137685 end: 2.2.3 depthcharge-start (duration 00:00:11) [common]
5593 09:54:53.138259 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
5594 09:54:53.138667 Setting prompt string to ['jacuzzi:']
5595 09:54:53.139072 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:27)
5596 09:54:53.139722 Starting depthcharge on Juniper...
5597 09:54:53.140076
5598 09:54:53.141349 vboot_handoff: creating legacy vboot_handoff structure
5599 09:54:53.141782
5600 09:54:53.144943 ec_init(0): CrosEC protocol v3 supported (544, 544)
5601 09:54:53.145461
5602 09:54:53.148091 Wipe memory regions:
5603 09:54:53.148519
5604 09:54:53.151610 [0x00000040000000, 0x00000054600000)
5605 09:54:53.194635
5606 09:54:53.195147 [0x00000054660000, 0x00000080000000)
5607 09:54:53.285768
5608 09:54:53.286327 [0x000000811994a0, 0x000000ffeda000)
5609 09:54:53.545262
5610 09:54:53.545779 [0x00000100000000, 0x00000140000000)
5611 09:54:53.678139
5612 09:54:53.681403 Initializing XHCI USB controller at 0x11200000.
5613 09:54:53.704192
5614 09:54:53.707511 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5615 09:54:53.707945
5616 09:54:53.708277
5617 09:54:53.709047 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5619 09:54:53.810331 jacuzzi: tftpboot 192.168.201.1 14407606/tftp-deploy-js1wnew3/kernel/image.itb 14407606/tftp-deploy-js1wnew3/kernel/cmdline
5620 09:54:53.811017 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5621 09:54:53.811436 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:26)
5622 09:54:53.816041 tftpboot 192.168.201.1 14407606/tftp-deploy-js1wnew3/kernel/image.itbtp-deploy-js1wnew3/kernel/cmdline
5623 09:54:53.816558
5624 09:54:53.816893 Waiting for link
5625 09:54:54.218357
5626 09:54:54.218871 R8152: Initializing
5627 09:54:54.219209
5628 09:54:54.221506 Version 9 (ocp_data = 6010)
5629 09:54:54.222050
5630 09:54:54.224880 R8152: Done initializing
5631 09:54:54.225311
5632 09:54:54.225639 Adding net device
5633 09:54:54.610499
5634 09:54:54.611015 done.
5635 09:54:54.611352
5636 09:54:54.611678 MAC: 00:e0:4c:72:3d:67
5637 09:54:54.611979
5638 09:54:54.614148 Sending DHCP discover... done.
5639 09:54:54.614579
5640 09:54:54.617059 Waiting for reply... done.
5641 09:54:54.617561
5642 09:54:54.620173 Sending DHCP request... done.
5643 09:54:54.620733
5644 09:54:54.625750 Waiting for reply... done.
5645 09:54:54.626326
5646 09:54:54.626669 My ip is 192.168.201.13
5647 09:54:54.626977
5648 09:54:54.629219 The DHCP server ip is 192.168.201.1
5649 09:54:54.629649
5650 09:54:54.635339 TFTP server IP predefined by user: 192.168.201.1
5651 09:54:54.635777
5652 09:54:54.643048 Bootfile predefined by user: 14407606/tftp-deploy-js1wnew3/kernel/image.itb
5653 09:54:54.643572
5654 09:54:54.645119 Sending tftp read request... done.
5655 09:54:54.645553
5656 09:54:54.652864 Waiting for the transfer...
5657 09:54:54.653297
5658 09:54:55.052396 00000000 ################################################################
5659 09:54:55.052863
5660 09:54:55.446199 00080000 ################################################################
5661 09:54:55.446662
5662 09:54:55.756030 00100000 ################################################################
5663 09:54:55.756154
5664 09:54:56.052521 00180000 ################################################################
5665 09:54:56.052643
5666 09:54:56.336929 00200000 ################################################################
5667 09:54:56.337071
5668 09:54:56.631357 00280000 ################################################################
5669 09:54:56.631503
5670 09:54:56.931925 00300000 ################################################################
5671 09:54:56.932045
5672 09:54:57.220041 00380000 ################################################################
5673 09:54:57.220164
5674 09:54:57.501692 00400000 ################################################################
5675 09:54:57.501815
5676 09:54:57.764884 00480000 ################################################################
5677 09:54:57.765006
5678 09:54:58.061867 00500000 ################################################################
5679 09:54:58.062029
5680 09:54:58.345698 00580000 ################################################################
5681 09:54:58.345836
5682 09:54:58.626289 00600000 ################################################################
5683 09:54:58.626433
5684 09:54:58.878902 00680000 ################################################################
5685 09:54:58.879023
5686 09:54:59.132931 00700000 ################################################################
5687 09:54:59.133054
5688 09:54:59.403369 00780000 ################################################################
5689 09:54:59.403482
5690 09:54:59.690857 00800000 ################################################################
5691 09:54:59.690979
5692 09:54:59.968004 00880000 ################################################################
5693 09:54:59.968127
5694 09:55:00.241809 00900000 ################################################################
5695 09:55:00.241931
5696 09:55:00.502027 00980000 ################################################################
5697 09:55:00.502165
5698 09:55:00.754460 00a00000 ################################################################
5699 09:55:00.754571
5700 09:55:01.020111 00a80000 ################################################################
5701 09:55:01.020251
5702 09:55:01.289443 00b00000 ################################################################
5703 09:55:01.289567
5704 09:55:01.556590 00b80000 ################################################################
5705 09:55:01.556711
5706 09:55:01.835576 00c00000 ################################################################
5707 09:55:01.835698
5708 09:55:02.101939 00c80000 ################################################################
5709 09:55:02.102091
5710 09:55:02.368028 00d00000 ################################################################
5711 09:55:02.368154
5712 09:55:02.655726 00d80000 ################################################################
5713 09:55:02.655852
5714 09:55:02.956410 00e00000 ################################################################
5715 09:55:02.956533
5716 09:55:03.246691 00e80000 ################################################################
5717 09:55:03.246813
5718 09:55:03.541662 00f00000 ################################################################
5719 09:55:03.541784
5720 09:55:03.828772 00f80000 ################################################################
5721 09:55:03.828900
5722 09:55:04.127522 01000000 ################################################################
5723 09:55:04.127648
5724 09:55:04.426581 01080000 ################################################################
5725 09:55:04.426699
5726 09:55:04.713416 01100000 ################################################################
5727 09:55:04.713538
5728 09:55:04.981440 01180000 ################################################################
5729 09:55:04.981585
5730 09:55:05.283740 01200000 ################################################################
5731 09:55:05.283857
5732 09:55:05.577782 01280000 ################################################################
5733 09:55:05.577905
5734 09:55:05.873706 01300000 ################################################################
5735 09:55:05.873850
5736 09:55:06.151673 01380000 ################################################################
5737 09:55:06.151798
5738 09:55:06.434545 01400000 ################################################################
5739 09:55:06.434672
5740 09:55:06.721952 01480000 ################################################################
5741 09:55:06.722115
5742 09:55:07.025556 01500000 ################################################################
5743 09:55:07.025675
5744 09:55:07.410404 01580000 ################################################################
5745 09:55:07.411071
5746 09:55:07.753872 01600000 ################################################################
5747 09:55:07.754025
5748 09:55:08.053944 01680000 ################################################################
5749 09:55:08.054090
5750 09:55:08.338098 01700000 ################################################################
5751 09:55:08.338236
5752 09:55:08.620669 01780000 ################################################################
5753 09:55:08.620790
5754 09:55:08.928557 01800000 ################################################################
5755 09:55:08.928686
5756 09:55:09.221145 01880000 ################################################################
5757 09:55:09.221270
5758 09:55:09.581643 01900000 ################################################################
5759 09:55:09.582138
5760 09:55:09.962750 01980000 ################################################################
5761 09:55:09.963213
5762 09:55:10.248090 01a00000 ################################################################
5763 09:55:10.248210
5764 09:55:10.513414 01a80000 ################################################################
5765 09:55:10.513558
5766 09:55:10.768726 01b00000 ################################################################
5767 09:55:10.768842
5768 09:55:11.034843 01b80000 ################################################################
5769 09:55:11.034966
5770 09:55:11.291956 01c00000 ################################################################
5771 09:55:11.292079
5772 09:55:11.560868 01c80000 ################################################################
5773 09:55:11.560987
5774 09:55:11.833138 01d00000 ################################################################
5775 09:55:11.833277
5776 09:55:12.113509 01d80000 ################################################################
5777 09:55:12.113647
5778 09:55:12.343692 01e00000 ########################################################## done.
5779 09:55:12.343812
5780 09:55:12.346444 The bootfile was 31931462 bytes long.
5781 09:55:12.346526
5782 09:55:12.349905 Sending tftp read request... done.
5783 09:55:12.350015
5784 09:55:12.350081 Waiting for the transfer...
5785 09:55:12.350140
5786 09:55:12.353061 00000000 # done.
5787 09:55:12.353168
5788 09:55:12.359577 Command line loaded dynamically from TFTP file: 14407606/tftp-deploy-js1wnew3/kernel/cmdline
5789 09:55:12.359673
5790 09:55:12.386638 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407606/extract-nfsrootfs-d7meu2he,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5791 09:55:12.386836
5792 09:55:12.386980 Loading FIT.
5793 09:55:12.387115
5794 09:55:12.390818 Image ramdisk-1 has 18744998 bytes.
5795 09:55:12.391145
5796 09:55:12.393052 Image fdt-1 has 57695 bytes.
5797 09:55:12.393280
5798 09:55:12.396399 Image kernel-1 has 13126726 bytes.
5799 09:55:12.396674
5800 09:55:12.407131 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5801 09:55:12.407519
5802 09:55:12.416673 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5803 09:55:12.417207
5804 09:55:12.423575 Choosing best match conf-1 for compat google,juniper-sku16.
5805 09:55:12.427515
5806 09:55:12.432136 Connected to device vid:did:rid of 1ae0:0028:00
5807 09:55:12.438940
5808 09:55:12.442153 tpm_get_response: command 0x17b, return code 0x0
5809 09:55:12.442539
5810 09:55:12.445362 tpm_cleanup: add release locality here.
5811 09:55:12.445756
5812 09:55:12.448986 Shutting down all USB controllers.
5813 09:55:12.449450
5814 09:55:12.451936 Removing current net device
5815 09:55:12.452317
5816 09:55:12.455292 Exiting depthcharge with code 4 at timestamp: 36673664
5817 09:55:12.455742
5818 09:55:12.458821 LZMA decompressing kernel-1 to 0x80193568
5819 09:55:12.459203
5820 09:55:12.462720 LZMA decompressing kernel-1 to 0x40000000
5821 09:55:14.331208
5822 09:55:14.331714 jumping to kernel
5823 09:55:14.333427 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
5824 09:55:14.333933 start: 2.2.5 auto-login-action (timeout 00:04:05) [common]
5825 09:55:14.334334 Setting prompt string to ['Linux version [0-9]']
5826 09:55:14.334677 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5827 09:55:14.335023 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5828 09:55:14.406664
5829 09:55:14.409899 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5830 09:55:14.414109 start: 2.2.5.1 login-action (timeout 00:04:05) [common]
5831 09:55:14.414693 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5832 09:55:14.415079 Setting prompt string to []
5833 09:55:14.415478 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5834 09:55:14.415834 Using line separator: #'\n'#
5835 09:55:14.416139 No login prompt set.
5836 09:55:14.416467 Parsing kernel messages
5837 09:55:14.416753 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5838 09:55:14.417526 [login-action] Waiting for messages, (timeout 00:04:05)
5839 09:55:14.417937 Waiting using forced prompt support (timeout 00:02:03)
5840 09:55:14.432996 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
5841 09:55:14.436920 [ 0.000000] random: crng init done
5842 09:55:14.442999 [ 0.000000] Machine model: Google juniper sku16 board
5843 09:55:14.446372 [ 0.000000] efi: UEFI not found.
5844 09:55:14.453230 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5845 09:55:14.463041 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5846 09:55:14.469911 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5847 09:55:14.472639 [ 0.000000] printk: bootconsole [mtk8250] enabled
5848 09:55:14.482067 [ 0.000000] NUMA: No NUMA configuration found
5849 09:55:14.487934 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5850 09:55:14.495078 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5851 09:55:14.495595 [ 0.000000] Zone ranges:
5852 09:55:14.501649 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5853 09:55:14.505224 [ 0.000000] DMA32 empty
5854 09:55:14.511828 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5855 09:55:14.514675 [ 0.000000] Movable zone start for each node
5856 09:55:14.518193 [ 0.000000] Early memory node ranges
5857 09:55:14.524522 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5858 09:55:14.531564 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5859 09:55:14.537929 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5860 09:55:14.544987 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5861 09:55:14.551018 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5862 09:55:14.558030 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5863 09:55:14.574065 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5864 09:55:14.581178 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5865 09:55:14.587504 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5866 09:55:14.590794 [ 0.000000] psci: probing for conduit method from DT.
5867 09:55:14.597527 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5868 09:55:14.601146 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5869 09:55:14.607145 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5870 09:55:14.610351 [ 0.000000] psci: SMC Calling Convention v1.1
5871 09:55:14.617653 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5872 09:55:14.620961 [ 0.000000] Detected VIPT I-cache on CPU0
5873 09:55:14.626937 [ 0.000000] CPU features: detected: GIC system register CPU interface
5874 09:55:14.633959 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5875 09:55:14.640472 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5876 09:55:14.646913 [ 0.000000] CPU features: detected: ARM erratum 845719
5877 09:55:14.650469 [ 0.000000] alternatives: applying boot alternatives
5878 09:55:14.653703 [ 0.000000] Fallback order for Node 0: 0
5879 09:55:14.660238 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5880 09:55:14.663270 [ 0.000000] Policy zone: Normal
5881 09:55:14.690512 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14407606/extract-nfsrootfs-d7meu2he,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5882 09:55:14.703253 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5883 09:55:14.713434 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5884 09:55:14.720225 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5885 09:55:14.726413 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5886 09:55:14.733583 <6>[ 0.000000] software IO TLB: area num 8.
5887 09:55:14.757306 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5888 09:55:14.815117 <6>[ 0.000000] Memory: 3896768K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 261696K reserved, 32768K cma-reserved)
5889 09:55:14.822070 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5890 09:55:14.829351 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5891 09:55:14.831633 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5892 09:55:14.838941 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5893 09:55:14.844923 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5894 09:55:14.848689 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5895 09:55:14.859228 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5896 09:55:14.865338 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5897 09:55:14.871805 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5898 09:55:14.881611 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5899 09:55:14.885231 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5900 09:55:14.888117 <6>[ 0.000000] GICv3: 640 SPIs implemented
5901 09:55:14.895151 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5902 09:55:14.898285 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5903 09:55:14.904465 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5904 09:55:14.911156 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5905 09:55:14.921213 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5906 09:55:14.934482 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5907 09:55:14.941172 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5908 09:55:14.952233 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5909 09:55:14.965845 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5910 09:55:14.972581 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5911 09:55:14.979107 <6>[ 0.009471] Console: colour dummy device 80x25
5912 09:55:14.982539 <6>[ 0.014513] printk: console [tty1] enabled
5913 09:55:14.995423 <6>[ 0.018901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5914 09:55:14.998556 <6>[ 0.029366] pid_max: default: 32768 minimum: 301
5915 09:55:15.002201 <6>[ 0.034247] LSM: Security Framework initializing
5916 09:55:15.013543 <6>[ 0.039164] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5917 09:55:15.018906 <6>[ 0.046788] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5918 09:55:15.025242 <4>[ 0.055662] cacheinfo: Unable to detect cache hierarchy for CPU 0
5919 09:55:15.035322 <6>[ 0.062286] cblist_init_generic: Setting adjustable number of callback queues.
5920 09:55:15.042560 <6>[ 0.069732] cblist_init_generic: Setting shift to 3 and lim to 1.
5921 09:55:15.048767 <6>[ 0.076085] cblist_init_generic: Setting adjustable number of callback queues.
5922 09:55:15.055367 <6>[ 0.083530] cblist_init_generic: Setting shift to 3 and lim to 1.
5923 09:55:15.058727 <6>[ 0.089929] rcu: Hierarchical SRCU implementation.
5924 09:55:15.064834 <6>[ 0.094955] rcu: Max phase no-delay instances is 1000.
5925 09:55:15.072454 <6>[ 0.102880] EFI services will not be available.
5926 09:55:15.075643 <6>[ 0.107830] smp: Bringing up secondary CPUs ...
5927 09:55:15.086698 <6>[ 0.113064] Detected VIPT I-cache on CPU1
5928 09:55:15.093270 <4>[ 0.113113] cacheinfo: Unable to detect cache hierarchy for CPU 1
5929 09:55:15.099645 <6>[ 0.113122] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5930 09:55:15.106274 <6>[ 0.113153] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5931 09:55:15.109587 <6>[ 0.113634] Detected VIPT I-cache on CPU2
5932 09:55:15.116110 <4>[ 0.113668] cacheinfo: Unable to detect cache hierarchy for CPU 2
5933 09:55:15.122785 <6>[ 0.113673] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5934 09:55:15.130375 <6>[ 0.113685] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5935 09:55:15.135585 <6>[ 0.114129] Detected VIPT I-cache on CPU3
5936 09:55:15.139321 <4>[ 0.114159] cacheinfo: Unable to detect cache hierarchy for CPU 3
5937 09:55:15.149459 <6>[ 0.114164] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5938 09:55:15.156135 <6>[ 0.114175] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5939 09:55:15.159438 <6>[ 0.114749] CPU features: detected: Spectre-v2
5940 09:55:15.162381 <6>[ 0.114759] CPU features: detected: Spectre-BHB
5941 09:55:15.169523 <6>[ 0.114763] CPU features: detected: ARM erratum 858921
5942 09:55:15.172491 <6>[ 0.114768] Detected VIPT I-cache on CPU4
5943 09:55:15.178987 <4>[ 0.114817] cacheinfo: Unable to detect cache hierarchy for CPU 4
5944 09:55:15.186114 <6>[ 0.114825] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5945 09:55:15.195525 <6>[ 0.114833] arch_timer: Enabling local workaround for ARM erratum 858921
5946 09:55:15.198869 <6>[ 0.114843] arch_timer: CPU4: Trapping CNTVCT access
5947 09:55:15.205659 <6>[ 0.114851] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5948 09:55:15.208847 <6>[ 0.115336] Detected VIPT I-cache on CPU5
5949 09:55:15.215571 <4>[ 0.115377] cacheinfo: Unable to detect cache hierarchy for CPU 5
5950 09:55:15.222459 <6>[ 0.115382] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5951 09:55:15.232162 <6>[ 0.115389] arch_timer: Enabling local workaround for ARM erratum 858921
5952 09:55:15.235385 <6>[ 0.115395] arch_timer: CPU5: Trapping CNTVCT access
5953 09:55:15.242396 <6>[ 0.115400] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5954 09:55:15.245506 <6>[ 0.115836] Detected VIPT I-cache on CPU6
5955 09:55:15.252590 <4>[ 0.115881] cacheinfo: Unable to detect cache hierarchy for CPU 6
5956 09:55:15.262245 <6>[ 0.115887] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5957 09:55:15.268666 <6>[ 0.115894] arch_timer: Enabling local workaround for ARM erratum 858921
5958 09:55:15.271542 <6>[ 0.115900] arch_timer: CPU6: Trapping CNTVCT access
5959 09:55:15.278244 <6>[ 0.115905] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5960 09:55:15.285347 <6>[ 0.116436] Detected VIPT I-cache on CPU7
5961 09:55:15.288761 <4>[ 0.116478] cacheinfo: Unable to detect cache hierarchy for CPU 7
5962 09:55:15.298342 <6>[ 0.116484] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5963 09:55:15.305123 <6>[ 0.116491] arch_timer: Enabling local workaround for ARM erratum 858921
5964 09:55:15.308323 <6>[ 0.116497] arch_timer: CPU7: Trapping CNTVCT access
5965 09:55:15.314961 <6>[ 0.116503] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5966 09:55:15.321545 <6>[ 0.116551] smp: Brought up 1 node, 8 CPUs
5967 09:55:15.325070 <6>[ 0.355451] SMP: Total of 8 processors activated.
5968 09:55:15.331407 <6>[ 0.360385] CPU features: detected: 32-bit EL0 Support
5969 09:55:15.334688 <6>[ 0.365764] CPU features: detected: 32-bit EL1 Support
5970 09:55:15.341458 <6>[ 0.371131] CPU features: detected: CRC32 instructions
5971 09:55:15.344895 <6>[ 0.376557] CPU: All CPU(s) started at EL2
5972 09:55:15.350971 <6>[ 0.380895] alternatives: applying system-wide alternatives
5973 09:55:15.358878 <6>[ 0.389064] devtmpfs: initialized
5974 09:55:15.370869 <6>[ 0.398019] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5975 09:55:15.381033 <6>[ 0.407967] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5976 09:55:15.385036 <6>[ 0.415698] pinctrl core: initialized pinctrl subsystem
5977 09:55:15.392320 <6>[ 0.422806] DMI not present or invalid.
5978 09:55:15.399318 <6>[ 0.427174] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5979 09:55:15.406230 <6>[ 0.434075] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5980 09:55:15.416831 <6>[ 0.441586] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5981 09:55:15.422481 <6>[ 0.449758] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5982 09:55:15.429082 <6>[ 0.457903] audit: initializing netlink subsys (disabled)
5983 09:55:15.436195 <5>[ 0.463584] audit: type=2000 audit(0.328:1): state=initialized audit_enabled=0 res=1
5984 09:55:15.443026 <6>[ 0.464546] thermal_sys: Registered thermal governor 'step_wise'
5985 09:55:15.448850 <6>[ 0.471536] thermal_sys: Registered thermal governor 'power_allocator'
5986 09:55:15.452479 <6>[ 0.477783] cpuidle: using governor menu
5987 09:55:15.458792 <6>[ 0.488728] NET: Registered PF_QIPCRTR protocol family
5988 09:55:15.465494 <6>[ 0.494213] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5989 09:55:15.472482 <6>[ 0.501303] ASID allocator initialised with 32768 entries
5990 09:55:15.475933 <6>[ 0.508078] Serial: AMBA PL011 UART driver
5991 09:55:15.487718 <4>[ 0.518472] Trying to register duplicate clock ID: 113
5992 09:55:15.547556 <6>[ 0.574379] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5993 09:55:15.562343 <6>[ 0.588736] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5994 09:55:15.565628 <6>[ 0.598491] KASLR enabled
5995 09:55:15.581008 <6>[ 0.606495] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5996 09:55:15.586094 <6>[ 0.613500] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5997 09:55:15.593613 <6>[ 0.619978] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5998 09:55:15.599538 <6>[ 0.626969] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5999 09:55:15.606118 <6>[ 0.633443] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
6000 09:55:15.612661 <6>[ 0.640432] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
6001 09:55:15.619521 <6>[ 0.646905] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
6002 09:55:15.626264 <6>[ 0.653895] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
6003 09:55:15.629335 <6>[ 0.661464] ACPI: Interpreter disabled.
6004 09:55:15.639514 <6>[ 0.669440] iommu: Default domain type: Translated
6005 09:55:15.646055 <6>[ 0.674546] iommu: DMA domain TLB invalidation policy: strict mode
6006 09:55:15.649448 <5>[ 0.681178] SCSI subsystem initialized
6007 09:55:15.656232 <6>[ 0.685604] usbcore: registered new interface driver usbfs
6008 09:55:15.662533 <6>[ 0.691332] usbcore: registered new interface driver hub
6009 09:55:15.665508 <6>[ 0.696872] usbcore: registered new device driver usb
6010 09:55:15.673281 <6>[ 0.703169] pps_core: LinuxPPS API ver. 1 registered
6011 09:55:15.682774 <6>[ 0.708354] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
6012 09:55:15.686137 <6>[ 0.717678] PTP clock support registered
6013 09:55:15.689834 <6>[ 0.721931] EDAC MC: Ver: 3.0.0
6014 09:55:15.698204 <6>[ 0.727567] FPGA manager framework
6015 09:55:15.704143 <6>[ 0.731249] Advanced Linux Sound Architecture Driver Initialized.
6016 09:55:15.707264 <6>[ 0.737999] vgaarb: loaded
6017 09:55:15.713720 <6>[ 0.741126] clocksource: Switched to clocksource arch_sys_counter
6018 09:55:15.717230 <5>[ 0.747558] VFS: Disk quotas dquot_6.6.0
6019 09:55:15.723940 <6>[ 0.751731] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
6020 09:55:15.726849 <6>[ 0.758908] pnp: PnP ACPI: disabled
6021 09:55:15.736460 <6>[ 0.765793] NET: Registered PF_INET protocol family
6022 09:55:15.742701 <6>[ 0.771020] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
6023 09:55:15.754552 <6>[ 0.780926] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
6024 09:55:15.763756 <6>[ 0.789680] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
6025 09:55:15.770426 <6>[ 0.797631] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
6026 09:55:15.777385 <6>[ 0.805865] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
6027 09:55:15.784338 <6>[ 0.813959] TCP: Hash tables configured (established 32768 bind 32768)
6028 09:55:15.793605 <6>[ 0.820788] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
6029 09:55:15.801137 <6>[ 0.827760] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
6030 09:55:15.806989 <6>[ 0.835241] NET: Registered PF_UNIX/PF_LOCAL protocol family
6031 09:55:15.813650 <6>[ 0.841373] RPC: Registered named UNIX socket transport module.
6032 09:55:15.816678 <6>[ 0.847517] RPC: Registered udp transport module.
6033 09:55:15.824346 <6>[ 0.852442] RPC: Registered tcp transport module.
6034 09:55:15.830463 <6>[ 0.857365] RPC: Registered tcp NFSv4.1 backchannel transport module.
6035 09:55:15.833462 <6>[ 0.864020] PCI: CLS 0 bytes, default 64
6036 09:55:15.836882 <6>[ 0.868304] Unpacking initramfs...
6037 09:55:15.846625 <6>[ 0.872081] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6038 09:55:15.853506 <6>[ 0.880707] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6039 09:55:15.859774 <6>[ 0.889560] kvm [1]: IPA Size Limit: 40 bits
6040 09:55:15.864598 <6>[ 0.895883] kvm [1]: vgic-v2@c420000
6041 09:55:15.869499 <6>[ 0.899698] kvm [1]: GIC system register CPU interface enabled
6042 09:55:15.876324 <6>[ 0.905870] kvm [1]: vgic interrupt IRQ18
6043 09:55:15.879593 <6>[ 0.910229] kvm [1]: Hyp mode initialized successfully
6044 09:55:15.886601 <5>[ 0.916492] Initialise system trusted keyrings
6045 09:55:15.892903 <6>[ 0.921318] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6046 09:55:15.900817 <6>[ 0.931195] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6047 09:55:15.908205 <5>[ 0.937686] NFS: Registering the id_resolver key type
6048 09:55:15.910898 <5>[ 0.942992] Key type id_resolver registered
6049 09:55:15.918287 <5>[ 0.947404] Key type id_legacy registered
6050 09:55:15.924472 <6>[ 0.951711] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6051 09:55:15.930716 <6>[ 0.958632] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6052 09:55:15.937414 <6>[ 0.966407] 9p: Installing v9fs 9p2000 file system support
6053 09:55:15.965089 <5>[ 0.995179] Key type asymmetric registered
6054 09:55:15.968237 <5>[ 0.999525] Asymmetric key parser 'x509' registered
6055 09:55:15.977913 <6>[ 1.004677] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6056 09:55:15.981455 <6>[ 1.012284] io scheduler mq-deadline registered
6057 09:55:15.984800 <6>[ 1.017044] io scheduler kyber registered
6058 09:55:16.007477 <6>[ 1.037829] EINJ: ACPI disabled.
6059 09:55:16.014013 <4>[ 1.041593] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6060 09:55:16.051566 <6>[ 1.082311] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6061 09:55:16.060495 <6>[ 1.090838] printk: console [ttyS0] disabled
6062 09:55:16.088750 <6>[ 1.115486] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6063 09:55:16.095077 <6>[ 1.124962] printk: console [ttyS0] enabled
6064 09:55:16.098424 <6>[ 1.124962] printk: console [ttyS0] enabled
6065 09:55:16.104672 <6>[ 1.133877] printk: bootconsole [mtk8250] disabled
6066 09:55:16.108225 <6>[ 1.133877] printk: bootconsole [mtk8250] disabled
6067 09:55:16.118775 <3>[ 1.144420] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6068 09:55:16.125426 <3>[ 1.152805] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6069 09:55:16.154112 <6>[ 1.181225] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6070 09:55:16.161088 <6>[ 1.190877] serial serial0: tty port ttyS1 registered
6071 09:55:16.167742 <6>[ 1.197465] SuperH (H)SCI(F) driver initialized
6072 09:55:16.170706 <6>[ 1.202922] msm_serial: driver initialized
6073 09:55:16.185793 <6>[ 1.213244] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6074 09:55:16.196436 <6>[ 1.221839] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6075 09:55:16.202590 <6>[ 1.230415] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6076 09:55:16.212393 <6>[ 1.238984] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6077 09:55:16.222391 <6>[ 1.247642] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6078 09:55:16.229158 <6>[ 1.256306] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6079 09:55:16.238636 <6>[ 1.265046] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6080 09:55:16.245252 <6>[ 1.273786] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6081 09:55:16.255605 <6>[ 1.282354] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6082 09:55:16.264986 <6>[ 1.291153] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6083 09:55:16.273543 <4>[ 1.303536] cacheinfo: Unable to detect cache hierarchy for CPU 0
6084 09:55:16.279269 <6>[ 1.312877] loop: module loaded
6085 09:55:16.294280 <6>[ 1.324859] vsim1: Bringing 1800000uV into 2700000-2700000uV
6086 09:55:16.312611 <6>[ 1.342831] megasas: 07.719.03.00-rc1
6087 09:55:16.321426 <6>[ 1.351551] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6088 09:55:16.334470 <6>[ 1.364521] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6089 09:55:16.351231 <6>[ 1.381287] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6090 09:55:16.407598 <6>[ 1.431459] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1d
6091 09:55:16.448034 <6>[ 1.477945] Freeing initrd memory: 18300K
6092 09:55:16.463485 <4>[ 1.489761] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6093 09:55:16.469586 <4>[ 1.498992] CPU: 5 PID: 1 Comm: swapper/0 Not tainted 6.1.92-cip22 #1
6094 09:55:16.476187 <4>[ 1.505690] Hardware name: Google juniper sku16 board (DT)
6095 09:55:16.480152 <4>[ 1.511429] Call trace:
6096 09:55:16.482775 <4>[ 1.514129] dump_backtrace.part.0+0xe0/0xf0
6097 09:55:16.485908 <4>[ 1.518667] show_stack+0x18/0x30
6098 09:55:16.489855 <4>[ 1.522239] dump_stack_lvl+0x68/0x84
6099 09:55:16.492856 <4>[ 1.526160] dump_stack+0x18/0x34
6100 09:55:16.499333 <4>[ 1.529730] sysfs_warn_dup+0x64/0x80
6101 09:55:16.502980 <4>[ 1.533652] sysfs_do_create_link_sd+0xf0/0x100
6102 09:55:16.506550 <4>[ 1.538439] sysfs_create_link+0x20/0x40
6103 09:55:16.513128 <4>[ 1.542618] bus_add_device+0x68/0x10c
6104 09:55:16.516251 <4>[ 1.546625] device_add+0x340/0x7ac
6105 09:55:16.519538 <4>[ 1.550368] of_device_add+0x44/0x60
6106 09:55:16.526124 <4>[ 1.554202] of_platform_device_create_pdata+0x90/0x120
6107 09:55:16.529022 <4>[ 1.559683] of_platform_bus_create+0x170/0x370
6108 09:55:16.532481 <4>[ 1.564469] of_platform_populate+0x50/0xfc
6109 09:55:16.539253 <4>[ 1.568909] parse_mtd_partitions+0x1dc/0x510
6110 09:55:16.542428 <4>[ 1.573522] mtd_device_parse_register+0xf8/0x2e0
6111 09:55:16.545889 <4>[ 1.578480] spi_nor_probe+0x21c/0x2f0
6112 09:55:16.552307 <4>[ 1.582486] spi_mem_probe+0x6c/0xb0
6113 09:55:16.555984 <4>[ 1.586319] spi_probe+0x84/0xe4
6114 09:55:16.559197 <4>[ 1.589801] really_probe+0xbc/0x2e0
6115 09:55:16.562542 <4>[ 1.593631] __driver_probe_device+0x78/0x11c
6116 09:55:16.569197 <4>[ 1.598243] driver_probe_device+0xd8/0x160
6117 09:55:16.572091 <4>[ 1.602681] __device_attach_driver+0xb8/0x134
6118 09:55:16.575484 <4>[ 1.607380] bus_for_each_drv+0x78/0xd0
6119 09:55:16.579721 <4>[ 1.611470] __device_attach+0xa8/0x1c0
6120 09:55:16.585626 <4>[ 1.615561] device_initial_probe+0x14/0x20
6121 09:55:16.589039 <4>[ 1.619999] bus_probe_device+0x9c/0xa4
6122 09:55:16.592276 <4>[ 1.624089] device_add+0x3ac/0x7ac
6123 09:55:16.595451 <4>[ 1.627831] __spi_add_device+0x78/0x120
6124 09:55:16.602312 <4>[ 1.632010] spi_add_device+0x40/0x7c
6125 09:55:16.605191 <4>[ 1.635927] spi_register_controller+0x610/0xad0
6126 09:55:16.612452 <4>[ 1.640800] devm_spi_register_controller+0x4c/0xa4
6127 09:55:16.615179 <4>[ 1.645933] mtk_spi_probe+0x3f8/0x650
6128 09:55:16.618981 <4>[ 1.649937] platform_probe+0x68/0xe0
6129 09:55:16.622699 <4>[ 1.653855] really_probe+0xbc/0x2e0
6130 09:55:16.625108 <4>[ 1.657686] __driver_probe_device+0x78/0x11c
6131 09:55:16.631725 <4>[ 1.662297] driver_probe_device+0xd8/0x160
6132 09:55:16.635270 <4>[ 1.666735] __driver_attach+0x94/0x19c
6133 09:55:16.639224 <4>[ 1.670826] bus_for_each_dev+0x70/0xd0
6134 09:55:16.641802 <4>[ 1.674916] driver_attach+0x24/0x30
6135 09:55:16.648870 <4>[ 1.678745] bus_add_driver+0x154/0x20c
6136 09:55:16.652275 <4>[ 1.682836] driver_register+0x78/0x130
6137 09:55:16.655610 <4>[ 1.686927] __platform_driver_register+0x28/0x34
6138 09:55:16.662381 <4>[ 1.691887] mtk_spi_driver_init+0x1c/0x28
6139 09:55:16.665409 <4>[ 1.696240] do_one_initcall+0x50/0x1d0
6140 09:55:16.668661 <4>[ 1.700330] kernel_init_freeable+0x21c/0x288
6141 09:55:16.671769 <4>[ 1.704944] kernel_init+0x24/0x12c
6142 09:55:16.678540 <4>[ 1.708689] ret_from_fork+0x10/0x20
6143 09:55:16.688163 <6>[ 1.717611] tun: Universal TUN/TAP device driver, 1.6
6144 09:55:16.691048 <6>[ 1.723892] thunder_xcv, ver 1.0
6145 09:55:16.694022 <6>[ 1.727407] thunder_bgx, ver 1.0
6146 09:55:16.697242 <6>[ 1.730911] nicpf, ver 1.0
6147 09:55:16.708276 <6>[ 1.735281] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6148 09:55:16.712465 <6>[ 1.742765] hns3: Copyright (c) 2017 Huawei Corporation.
6149 09:55:16.718499 <6>[ 1.748375] hclge is initializing
6150 09:55:16.721818 <6>[ 1.751959] e1000: Intel(R) PRO/1000 Network Driver
6151 09:55:16.728289 <6>[ 1.757094] e1000: Copyright (c) 1999-2006 Intel Corporation.
6152 09:55:16.731612 <6>[ 1.763115] e1000e: Intel(R) PRO/1000 Network Driver
6153 09:55:16.739055 <6>[ 1.768336] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6154 09:55:16.745594 <6>[ 1.774528] igb: Intel(R) Gigabit Ethernet Network Driver
6155 09:55:16.749081 <6>[ 1.780183] igb: Copyright (c) 2007-2014 Intel Corporation.
6156 09:55:16.755834 <6>[ 1.786026] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6157 09:55:16.762718 <6>[ 1.792548] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6158 09:55:16.769859 <6>[ 1.799100] sky2: driver version 1.30
6159 09:55:16.776125 <6>[ 1.804347] usbcore: registered new device driver r8152-cfgselector
6160 09:55:16.782998 <6>[ 1.810889] usbcore: registered new interface driver r8152
6161 09:55:16.786290 <6>[ 1.816718] VFIO - User Level meta-driver version: 0.3
6162 09:55:16.794473 <6>[ 1.824485] mtu3 11201000.usb: uwk - reg:0x420, version:101
6163 09:55:16.801081 <4>[ 1.830357] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6164 09:55:16.807859 <6>[ 1.837634] mtu3 11201000.usb: dr_mode: 1, drd: auto
6165 09:55:16.814350 <6>[ 1.842859] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6166 09:55:16.817209 <6>[ 1.849045] mtu3 11201000.usb: usb3-drd: 0
6167 09:55:16.827889 <6>[ 1.854605] mtu3 11201000.usb: xHCI platform device register success...
6168 09:55:16.834553 <4>[ 1.863224] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6169 09:55:16.841041 <6>[ 1.871166] xhci-mtk 11200000.usb: xHCI Host Controller
6170 09:55:16.847516 <6>[ 1.876676] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6171 09:55:16.854566 <6>[ 1.884395] xhci-mtk 11200000.usb: USB3 root hub has no ports
6172 09:55:16.864473 <6>[ 1.890402] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6173 09:55:16.870836 <6>[ 1.899846] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6174 09:55:16.877439 <6>[ 1.905925] xhci-mtk 11200000.usb: xHCI Host Controller
6175 09:55:16.884948 <6>[ 1.911413] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6176 09:55:16.890471 <6>[ 1.919072] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6177 09:55:16.894140 <6>[ 1.925887] hub 1-0:1.0: USB hub found
6178 09:55:16.898159 <6>[ 1.929915] hub 1-0:1.0: 1 port detected
6179 09:55:16.909335 <6>[ 1.935268] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6180 09:55:16.911396 <6>[ 1.943880] hub 2-0:1.0: USB hub found
6181 09:55:16.921636 <3>[ 1.947908] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6182 09:55:16.928750 <6>[ 1.955789] usbcore: registered new interface driver usb-storage
6183 09:55:16.934851 <6>[ 1.962386] usbcore: registered new device driver onboard-usb-hub
6184 09:55:16.950952 <4>[ 1.977221] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6185 09:55:16.959461 <6>[ 1.989538] mt6397-rtc mt6358-rtc: registered as rtc0
6186 09:55:16.969144 <6>[ 1.995015] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-18T09:55:16 UTC (1718704516)
6187 09:55:16.972906 <6>[ 2.004899] i2c_dev: i2c /dev entries driver
6188 09:55:16.984470 <6>[ 2.011366] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6189 09:55:16.994369 <6>[ 2.019686] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6190 09:55:16.997450 <6>[ 2.028590] i2c 4-0058: Fixed dependency cycle(s) with /panel
6191 09:55:17.007337 <6>[ 2.034622] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6192 09:55:17.013898 <3>[ 2.042100] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
6193 09:55:17.031852 <6>[ 2.062031] cpu cpu0: EM: created perf domain
6194 09:55:17.041894 <6>[ 2.067528] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6195 09:55:17.048709 <6>[ 2.078814] cpu cpu4: EM: created perf domain
6196 09:55:17.055703 <6>[ 2.085856] sdhci: Secure Digital Host Controller Interface driver
6197 09:55:17.062610 <6>[ 2.092310] sdhci: Copyright(c) Pierre Ossman
6198 09:55:17.068931 <6>[ 2.097707] Synopsys Designware Multimedia Card Interface Driver
6199 09:55:17.075667 <6>[ 2.098203] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6200 09:55:17.079016 <6>[ 2.104777] sdhci-pltfm: SDHCI platform and OF driver helper
6201 09:55:17.087504 <6>[ 2.117663] ledtrig-cpu: registered to indicate activity on CPUs
6202 09:55:17.095057 <6>[ 2.125364] usbcore: registered new interface driver usbhid
6203 09:55:17.098370 <6>[ 2.131202] usbhid: USB HID core driver
6204 09:55:17.109004 <6>[ 2.135463] spi_master spi2: will run message pump with realtime priority
6205 09:55:17.112847 <4>[ 2.135474] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6206 09:55:17.120086 <4>[ 2.149725] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6207 09:55:17.133221 <6>[ 2.154207] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6208 09:55:17.151932 <6>[ 2.172447] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6209 09:55:17.158523 <4>[ 2.182420] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6210 09:55:17.161941 <6>[ 2.187482] cros-ec-spi spi2.0: Chrome EC device registered
6211 09:55:17.173589 <4>[ 2.200793] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6212 09:55:17.184526 <4>[ 2.211698] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6213 09:55:17.191414 <6>[ 2.217635] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x12c14
6214 09:55:17.198132 <4>[ 2.220443] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6215 09:55:17.201275 <6>[ 2.227933] mmc0: new HS400 MMC card at address 0001
6216 09:55:17.208331 <6>[ 2.237816] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6217 09:55:17.214790 <6>[ 2.238505] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6218 09:55:17.221405 <6>[ 2.248560] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6219 09:55:17.228041 <6>[ 2.257161] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6220 09:55:17.234578 <6>[ 2.263862] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6221 09:55:17.241603 <6>[ 2.270059] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6222 09:55:17.253279 <6>[ 2.271115] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6223 09:55:17.266111 <6>[ 2.289881] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6224 09:55:17.272591 <6>[ 2.303052] NET: Registered PF_PACKET protocol family
6225 09:55:17.286111 <6>[ 2.305355] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6226 09:55:17.289550 <6>[ 2.308468] 9pnet: Installing 9P2000 support
6227 09:55:17.299168 <6>[ 2.320799] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6228 09:55:17.302502 <5>[ 2.325021] Key type dns_resolver registered
6229 09:55:17.309580 <6>[ 2.339864] registered taskstats version 1
6230 09:55:17.312816 <5>[ 2.344230] Loading compiled-in X.509 certificates
6231 09:55:17.326734 <6>[ 2.353144] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6232 09:55:17.356693 <3>[ 2.383502] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6233 09:55:17.386345 <6>[ 2.409681] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6234 09:55:17.396769 <6>[ 2.423396] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6235 09:55:17.406253 <6>[ 2.431971] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6236 09:55:17.413581 <6>[ 2.440498] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6237 09:55:17.423200 <6>[ 2.449021] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6238 09:55:17.429726 <6>[ 2.457541] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6239 09:55:17.439258 <6>[ 2.466061] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6240 09:55:17.449570 <6>[ 2.474579] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6241 09:55:17.455786 <6>[ 2.483809] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6242 09:55:17.462346 <6>[ 2.491345] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6243 09:55:17.469088 <6>[ 2.498697] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6244 09:55:17.478920 <6>[ 2.506036] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6245 09:55:17.482333 <6>[ 2.508136] hub 1-1:1.0: USB hub found
6246 09:55:17.489344 <6>[ 2.513540] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6247 09:55:17.492053 <6>[ 2.517206] hub 1-1:1.0: 3 ports detected
6248 09:55:17.498654 <6>[ 2.525084] panfrost 13040000.gpu: clock rate = 511999970
6249 09:55:17.508876 <6>[ 2.533390] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6250 09:55:17.515379 <6>[ 2.543483] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6251 09:55:17.525221 <6>[ 2.551490] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6252 09:55:17.534737 <6>[ 2.559923] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6253 09:55:17.541964 <6>[ 2.572000] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6254 09:55:17.555130 <6>[ 2.581976] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6255 09:55:17.564732 <6>[ 2.591326] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6256 09:55:17.574801 <6>[ 2.600478] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6257 09:55:17.584719 <6>[ 2.609610] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6258 09:55:17.591159 <6>[ 2.618738] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6259 09:55:17.601610 <6>[ 2.628039] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6260 09:55:17.611560 <6>[ 2.637340] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6261 09:55:17.620971 <6>[ 2.646813] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6262 09:55:17.630952 <6>[ 2.656286] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6263 09:55:17.641636 <6>[ 2.665414] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6264 09:55:17.711222 <6>[ 2.738173] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6265 09:55:17.721465 <6>[ 2.747118] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6266 09:55:17.731954 <6>[ 2.759037] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6267 09:55:17.810369 <6>[ 2.837161] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6268 09:55:18.420897 <6>[ 3.029422] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6269 09:55:18.430466 <4>[ 3.146735] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6270 09:55:18.437299 <4>[ 3.146768] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6271 09:55:18.443563 <6>[ 3.199700] r8152 1-1.2:1.0 eth0: v1.12.13
6272 09:55:18.450535 <6>[ 3.281157] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6273 09:55:18.456827 <6>[ 3.430731] Console: switching to colour frame buffer device 170x48
6274 09:55:18.463154 <6>[ 3.491416] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6275 09:55:18.484687 <6>[ 3.507539] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6276 09:55:18.501138 <6>[ 3.524931] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6277 09:55:18.507817 <6>[ 3.537184] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6278 09:55:18.519068 <6>[ 3.545723] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6279 09:55:18.529311 <6>[ 3.552986] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6280 09:55:18.548496 <6>[ 3.571777] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6281 09:55:19.781777 <6>[ 4.811711] r8152 1-1.2:1.0 eth0: carrier on
6282 09:55:22.319757 <5>[ 4.837260] Sending DHCP requests .., OK
6283 09:55:22.325469 <6>[ 7.353541] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.13
6284 09:55:22.329216 <6>[ 7.361987] IP-Config: Complete:
6285 09:55:22.342719 <6>[ 7.365559] device=eth0, hwaddr=00:e0:4c:72:3d:67, ipaddr=192.168.201.13, mask=255.255.255.0, gw=192.168.201.1
6286 09:55:22.351916 <6>[ 7.376459] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-1, domain=lava-rack, nis-domain=(none)
6287 09:55:22.364150 <6>[ 7.390737] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6288 09:55:22.372438 <6>[ 7.390748] nameserver0=192.168.201.1
6289 09:55:22.380383 <6>[ 7.410521] clk: Disabling unused clocks
6290 09:55:22.385105 <6>[ 7.418443] ALSA device list:
6291 09:55:22.394400 <6>[ 7.424487] No soundcards found.
6292 09:55:22.403747 <6>[ 7.433577] Freeing unused kernel memory: 8512K
6293 09:55:22.410669 <6>[ 7.440715] Run /init as init process
6294 09:55:22.422584 Loading, please wait...
6295 09:55:22.456953 Starting systemd-udevd version 252.22-1~deb12u1
6296 09:55:22.788382 <3>[ 7.818207] thermal_sys: Failed to find 'trips' node
6297 09:55:22.797968 <3>[ 7.824172] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6298 09:55:22.804331 <3>[ 7.832208] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6299 09:55:22.814940 <4>[ 7.841592] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6300 09:55:22.824693 <3>[ 7.841901] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6301 09:55:22.831715 <6>[ 7.846874] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6302 09:55:22.838326 <3>[ 7.851325] thermal_sys: Failed to find 'trips' node
6303 09:55:22.844719 <3>[ 7.859278] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6304 09:55:22.851021 <4>[ 7.859559] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6305 09:55:22.857524 <4>[ 7.860094] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6306 09:55:22.864714 <3>[ 7.861062] mtk-scp 10500000.scp: invalid resource
6307 09:55:22.871005 <6>[ 7.861112] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6308 09:55:22.878384 <3>[ 7.867699] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6309 09:55:22.890706 <3>[ 7.872463] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6310 09:55:22.897547 <3>[ 7.872480] elan_i2c 2-0015: Error applying setting, reverse things back
6311 09:55:22.900625 <6>[ 7.875785] remoteproc remoteproc0: scp is available
6312 09:55:22.911151 <3>[ 7.879641] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6313 09:55:22.921029 <3>[ 7.886734] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6314 09:55:22.928344 <4>[ 7.886763] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6315 09:55:22.935091 <6>[ 7.886770] remoteproc remoteproc0: powering up scp
6316 09:55:22.941902 <4>[ 7.886785] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6317 09:55:22.948131 <3>[ 7.886788] remoteproc remoteproc0: request_firmware failed: -2
6318 09:55:22.955039 <4>[ 7.894134] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6319 09:55:22.964167 <3>[ 7.899308] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6320 09:55:22.971501 <6>[ 7.906918] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6321 09:55:22.981192 <3>[ 7.914044] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6322 09:55:22.990728 <4>[ 7.914356] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6323 09:55:23.005700 <6>[ 7.916055] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6324 09:55:23.016412 <6>[ 7.919914] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6325 09:55:23.023385 <6>[ 7.922149] mc: Linux media interface: v0.10
6326 09:55:23.030070 <6>[ 7.927664] cs_system_cfg: CoreSight Configuration manager initialised
6327 09:55:23.042699 <3>[ 7.932805] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6328 09:55:23.055272 <3>[ 7.933066] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6329 09:55:23.065585 <5>[ 7.935702] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6330 09:55:23.075692 <5>[ 7.951631] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6331 09:55:23.085975 <3>[ 7.954824] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6332 09:55:23.096682 <5>[ 7.963796] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6333 09:55:23.105270 <3>[ 7.968415] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6334 09:55:23.115231 <4>[ 7.976960] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6335 09:55:23.125297 <3>[ 7.983052] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6336 09:55:23.136255 <3>[ 7.983066] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6337 09:55:23.146031 <3>[ 7.983291] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6338 09:55:23.152716 <6>[ 7.990723] cfg80211: failed to load regulatory.db
6339 09:55:23.162730 <6>[ 8.002909] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6340 09:55:23.217815 <3>[ 8.240888] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6341 09:55:23.227732 <6>[ 8.254537] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6342 09:55:23.234565 <6>[ 8.254579] videodev: Linux video capture interface: v2.00
6343 09:55:23.241202 <3>[ 8.254952] debugfs: File 'Playback' in directory 'dapm' already present!
6344 09:55:23.247508 <3>[ 8.254957] debugfs: File 'Capture' in directory 'dapm' already present!
6345 09:55:23.261082 <6>[ 8.256616] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6346 09:55:23.267360 <6>[ 8.262973] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6347 09:55:23.277938 <4>[ 8.295760] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6348 09:55:23.280451 <4>[ 8.295760] Fallback method does not support PEC.
6349 09:55:23.291371 <6>[ 8.303981] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6350 09:55:23.295739 <6>[ 8.318313] Bluetooth: Core ver 2.22
6351 09:55:23.302483 <6>[ 8.318585] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6352 09:55:23.309291 <6>[ 8.319763] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video0
6353 09:55:23.315665 <6>[ 8.325581] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6354 09:55:23.322200 <6>[ 8.329223] NET: Registered PF_BLUETOOTH protocol family
6355 09:55:23.329328 <6>[ 8.330048] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6356 09:55:23.335870 <6>[ 8.330383] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video1 (81,1)
6357 09:55:23.342073 <6>[ 8.330630] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6358 09:55:23.351872 <3>[ 8.331076] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6359 09:55:23.358588 <6>[ 8.336071] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6360 09:55:23.368885 <3>[ 8.337210] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6361 09:55:23.376098 <6>[ 8.343519] Bluetooth: HCI device and connection manager initialized
6362 09:55:23.388913 <6>[ 8.348776] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6363 09:55:23.396010 <6>[ 8.348884] usbcore: registered new interface driver uvcvideo
6364 09:55:23.405417 <6>[ 8.349776] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6365 09:55:23.415638 <6>[ 8.349784] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6366 09:55:23.428867 <6>[ 8.350113] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6367 09:55:23.435102 <6>[ 8.351561] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6368 09:55:23.442338 <6>[ 8.357130] Bluetooth: HCI socket layer initialized
6369 09:55:23.452008 <6>[ 8.363472] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6370 09:55:23.455923 <6>[ 8.371884] Bluetooth: L2CAP socket layer initialized
6371 09:55:23.465855 <6>[ 8.386571] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6372 09:55:23.469097 <6>[ 8.387345] Bluetooth: SCO socket layer initialized
6373 09:55:23.484242 <6>[ 8.500045] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6374 09:55:23.498164 <6>[ 8.523740] Bluetooth: HCI UART driver ver 2.3
6375 09:55:23.514519 <6>[ 8.544396] Bluetooth: HCI UART protocol H4 registered
6376 09:55:23.521622 <6>[ 8.550550] Bluetooth: HCI UART protocol LL registered
6377 09:55:23.527477 <6>[ 8.556662] Bluetooth: HCI UART protocol Three-wire (H5) registered
6378 09:55:23.534255 <6>[ 8.564237] Bluetooth: HCI UART protocol Broadcom registered
6379 09:55:23.541293 <6>[ 8.570881] Bluetooth: HCI UART protocol QCA registered
6380 09:55:23.547572 <6>[ 8.572032] Bluetooth: hci0: setting up ROME/QCA6390
6381 09:55:23.550803 <6>[ 8.576380] Bluetooth: HCI UART protocol Marvell registered
6382 09:55:23.561840 Begin: Loading essential drivers ... done.
6383 09:55:23.565025 Begin: Running /scripts/init-premount ... done.
6384 09:55:23.571194 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
6385 09:55:23.581377 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
6386 09:55:23.584894 Device /sys/class/net/eth0 found
6387 09:55:23.585280 done.
6388 09:55:23.592214 Begin: Waiting up to 180 secs for any network device to become available ... done.
6389 09:55:23.651996 IP-Config: eth0 hardware address 00:e0:4c:72:3d:67 mtu 1500 DHCP
6390 09:55:23.658450 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6391 09:55:23.665310 address: 192.168.201.13 broadcast: 192.168.201.255 netmask: 255.255.255.0
6392 09:55:23.671162 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6393 09:55:23.678049 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-1
6394 09:55:23.685036 domain : lava-rack
6395 09:55:23.687932 rootserver: 192.168.201.1 rootpath:
6396 09:55:23.690619 filename :
6397 09:55:23.709572 done.
6398 09:55:23.717116 Begin: Running /scripts/nfs-bottom ... done.
6399 09:55:23.731282 Begin: Running /scripts/init-bottom ... done.
6400 09:55:23.766708 <3>[ 8.796219] Bluetooth: hci0: Frame reassembly failed (-84)
6401 09:55:23.849271 <6>[ 8.875963] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6402 09:55:23.929790 <4>[ 8.957043] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6403 09:55:23.949861 <4>[ 8.976843] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6404 09:55:23.965738 <4>[ 8.992701] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6405 09:55:23.975851 <4>[ 9.006265] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6406 09:55:24.031719 <6>[ 9.062205] Bluetooth: hci0: QCA Product ID :0x00000008
6407 09:55:24.042105 <6>[ 9.072257] Bluetooth: hci0: QCA SOC Version :0x00000044
6408 09:55:24.052079 <6>[ 9.082110] Bluetooth: hci0: QCA ROM Version :0x00000302
6409 09:55:24.061545 <6>[ 9.091863] Bluetooth: hci0: QCA Patch Version:0x00000111
6410 09:55:24.072123 <6>[ 9.101618] Bluetooth: hci0: QCA controller version 0x00440302
6411 09:55:24.083989 <6>[ 9.110849] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6412 09:55:24.094478 <4>[ 9.121063] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6413 09:55:24.106496 <3>[ 9.133245] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6414 09:55:24.113595 <3>[ 9.143765] Bluetooth: hci0: QCA Failed to download patch (-2)
6415 09:55:25.228905 <6>[ 10.258615] NET: Registered PF_INET6 protocol family
6416 09:55:25.240384 <6>[ 10.270517] Segment Routing with IPv6
6417 09:55:25.248381 <6>[ 10.278486] In-situ OAM (IOAM) with IPv6
6418 09:55:25.436988 <30>[ 10.440439] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6419 09:55:25.456145 <30>[ 10.486367] systemd[1]: Detected architecture arm64.
6420 09:55:25.471209
6421 09:55:25.474098 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6422 09:55:25.474574
6423 09:55:25.502048 <30>[ 10.531332] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6424 09:55:26.623757 <30>[ 11.650347] systemd[1]: Queued start job for default target graphical.target.
6425 09:55:26.660209 <30>[ 11.686719] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6426 09:55:26.672656 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6427 09:55:26.693765 <30>[ 11.720604] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6428 09:55:26.707202 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6429 09:55:26.724786 <30>[ 11.751572] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6430 09:55:26.738453 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6431 09:55:26.755930 <30>[ 11.782698] systemd[1]: Created slice user.slice - User and Session Slice.
6432 09:55:26.767566 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6433 09:55:26.790867 <30>[ 11.813729] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6434 09:55:26.802726 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6435 09:55:26.822731 <30>[ 11.845543] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6436 09:55:26.833918 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6437 09:55:26.860536 <30>[ 11.877548] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6438 09:55:26.878913 <30>[ 11.905548] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6439 09:55:26.886054 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6440 09:55:26.906443 <30>[ 11.933333] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6441 09:55:26.918817 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6442 09:55:26.934869 <30>[ 11.961403] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6443 09:55:26.947953 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6444 09:55:26.963495 <30>[ 11.993427] systemd[1]: Reached target paths.target - Path Units.
6445 09:55:26.977577 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6446 09:55:26.994295 <30>[ 12.021325] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6447 09:55:27.006492 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6448 09:55:27.019165 <30>[ 12.049276] systemd[1]: Reached target slices.target - Slice Units.
6449 09:55:27.033729 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6450 09:55:27.047351 <30>[ 12.077380] systemd[1]: Reached target swap.target - Swaps.
6451 09:55:27.057500 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6452 09:55:27.078568 <30>[ 12.105376] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6453 09:55:27.091938 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6454 09:55:27.111141 <30>[ 12.137761] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6455 09:55:27.124431 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6456 09:55:27.145943 <30>[ 12.172769] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6457 09:55:27.159661 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6458 09:55:27.181232 <30>[ 12.207518] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6459 09:55:27.194924 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6460 09:55:27.212239 <30>[ 12.238058] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6461 09:55:27.223274 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6462 09:55:27.244663 <30>[ 12.271120] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6463 09:55:27.257703 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6464 09:55:27.278281 <30>[ 12.304810] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6465 09:55:27.290870 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6466 09:55:27.306830 <30>[ 12.333928] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6467 09:55:27.320135 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6468 09:55:27.371097 <30>[ 12.397693] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6469 09:55:27.383492 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6470 09:55:27.404140 <30>[ 12.431192] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6471 09:55:27.416753 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6472 09:55:27.438790 <30>[ 12.465577] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6473 09:55:27.450526 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6474 09:55:27.473964 <30>[ 12.494254] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6475 09:55:27.523706 <30>[ 12.550644] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6476 09:55:27.538128 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6477 09:55:27.561372 <30>[ 12.587860] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6478 09:55:27.574916 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6479 09:55:27.594990 <30>[ 12.621788] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6480 09:55:27.608385 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6481 09:55:27.631759 <30>[ 12.658647] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6482 09:55:27.643586 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6483 09:55:27.655302 <6>[ 12.682446] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6484 09:55:27.669098 <30>[ 12.695843] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6485 09:55:27.680999 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6486 09:55:27.702896 <30>[ 12.729081] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6487 09:55:27.714504 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6488 09:55:27.734871 <30>[ 12.761897] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6489 09:55:27.746709 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6490 09:55:27.766274 <6>[ 12.796558] fuse: init (API version 7.37)
6491 09:55:27.787412 <30>[ 12.814296] systemd[1]: Starting systemd-journald.service - Journal Service...
6492 09:55:27.797626 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6493 09:55:27.825627 <30>[ 12.852417] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6494 09:55:27.835089 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6495 09:55:27.857950 <30>[ 12.881414] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6496 09:55:27.868214 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6497 09:55:27.911899 <30>[ 12.937875] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6498 09:55:27.924936 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6499 09:55:27.947972 <30>[ 12.974631] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6500 09:55:27.959755 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6501 09:55:27.983309 <30>[ 13.010203] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6502 09:55:27.993216 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6503 09:55:28.015921 <30>[ 13.041898] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6504 09:55:28.022676 <3>[ 13.044275] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6505 09:55:28.041207 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue <3>[ 13.065879] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6506 09:55:28.041658 File System.
6507 09:55:28.061971 <3>[ 13.088093] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6508 09:55:28.069551 <30>[ 13.097699] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6509 09:55:28.078871 <3>[ 13.104877] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6510 09:55:28.098656 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug <3>[ 13.124319] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6511 09:55:28.099088 File System.
6512 09:55:28.114953 <3>[ 13.141047] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6513 09:55:28.125482 <30>[ 13.150571] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
6514 09:55:28.131850 <3>[ 13.157599] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6515 09:55:28.146275 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6516 09:55:28.153175 <3>[ 13.179807] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6517 09:55:28.162974 <30>[ 13.192253] systemd[1]: modprobe@configfs.service: Deactivated successfully.
6518 09:55:28.175973 <30>[ 13.201876] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
6519 09:55:28.185713 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6520 09:55:28.203477 <30>[ 13.230338] systemd[1]: Started systemd-journald.service - Journal Service.
6521 09:55:28.215059 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6522 09:55:28.237432 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6523 09:55:28.258588 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6524 09:55:28.277776 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6525 09:55:28.295449 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6526 09:55:28.320089 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6527 09:55:28.343893 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6528 09:55:28.363479 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6529 09:55:28.387292 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6530 09:55:28.412392 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6531 09:55:28.451579 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6532 09:55:28.458394 <4>[ 13.486650] power_supply_show_property: 2 callbacks suppressed
6533 09:55:28.466151 <3>[ 13.486659] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6534 09:55:28.476111 <3>[ 13.499645] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6535 09:55:28.494339 <4>[ 13.501718] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6536 09:55:28.508136 <3>[ 13.501724] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6537 09:55:28.524850 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6538 09:55:28.536349 <3>[ 13.562805] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6539 09:55:28.555125 Starting [0;1;39msyste<3>[ 13.579709] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6540 09:55:28.558365 md-journal-f…h Journal to Persistent Storage...
6541 09:55:28.570080 <3>[ 13.596907] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6542 09:55:28.586777 <3>[ 13.613460] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6543 09:55:28.593557 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6544 09:55:28.605887 <3>[ 13.632399] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6545 09:55:28.622501 <3>[ 13.649037] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6546 09:55:28.640159 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables..<3>[ 13.664135] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6547 09:55:28.640565 .
6548 09:55:28.654606 <3>[ 13.680969] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6549 09:55:28.677666 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users..<46>[ 13.702840] systemd-journald[316]: Received client request to flush runtime journal.
6550 09:55:28.678256 .
6551 09:55:28.708555 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6552 09:55:28.727506 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6553 09:55:28.748133 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6554 09:55:28.768085 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6555 09:55:28.788466 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6556 09:55:29.768271 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6557 09:55:29.815453 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6558 09:55:30.118700 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6559 09:55:30.241902 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6560 09:55:30.263206 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6561 09:55:30.286520 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6562 09:55:30.335695 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6563 09:55:30.363303 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6564 09:55:30.656729 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6565 09:55:30.698761 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6566 09:55:30.716381 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6567 09:55:30.763999 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6568 09:55:30.960750 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6569 09:55:30.981492 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6570 09:55:31.211033 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6571 09:55:31.243420 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6572 09:55:31.262507 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6573 09:55:31.275854 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6574 09:55:31.295558 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6575 09:55:31.353763 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6576 09:55:31.375658 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6577 09:55:31.400323 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6578 09:55:31.425965 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6579 09:55:31.446191 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6580 09:55:31.467285 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6581 09:55:31.487049 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6582 09:55:31.502522 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6583 09:55:31.524645 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6584 09:55:31.577079 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6585 09:55:31.595410 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6586 09:55:31.614028 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6587 09:55:31.634267 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6588 09:55:31.651085 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6589 09:55:31.669477 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6590 09:55:31.687049 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6591 09:55:31.703212 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6592 09:55:31.755097 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6593 09:55:31.795947 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6594 09:55:31.889600 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6595 09:55:31.913158 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6596 09:55:31.936721 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6597 09:55:32.080048 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6598 09:55:32.123542 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6599 09:55:32.143969 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6600 09:55:32.166664 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6601 09:55:32.177064 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6602 09:55:32.197132 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6603 09:55:32.216945 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6604 09:55:32.260760 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6605 09:55:32.285571 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6606 09:55:32.304024 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6607 09:55:32.348108 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6608 09:55:32.402754 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6609 09:55:32.498159
6610 09:55:32.501673 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6611 09:55:32.502147
6612 09:55:32.505103 debian-bookworm-arm64 login: root (automatic login)
6613 09:55:32.505558
6614 09:55:32.791104 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
6615 09:55:32.791565
6616 09:55:32.797127 The programs included with the Debian GNU/Linux system are free software;
6617 09:55:32.803942 the exact distribution terms for each program are described in the
6618 09:55:32.807281 individual files in /usr/share/doc/*/copyright.
6619 09:55:32.807789
6620 09:55:32.814597 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6621 09:55:32.817828 permitted by applicable law.
6622 09:55:32.897167 Matched prompt #10: / #
6624 09:55:32.898179 Setting prompt string to ['/ #']
6625 09:55:32.898646 end: 2.2.5.1 login-action (duration 00:00:18) [common]
6627 09:55:32.899551 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
6628 09:55:32.899946 start: 2.2.6 expect-shell-connection (timeout 00:03:47) [common]
6629 09:55:32.900286 Setting prompt string to ['/ #']
6630 09:55:32.900602 Forcing a shell prompt, looking for ['/ #']
6632 09:55:32.951339 / #
6633 09:55:32.952075 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6634 09:55:32.952567 Waiting using forced prompt support (timeout 00:02:30)
6635 09:55:32.957884
6636 09:55:32.958827 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6637 09:55:32.959410 start: 2.2.7 export-device-env (timeout 00:03:47) [common]
6639 09:55:33.060779 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407606/extract-nfsrootfs-d7meu2he'
6640 09:55:33.067708 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14407606/extract-nfsrootfs-d7meu2he'
6642 09:55:33.169288 / # export NFS_SERVER_IP='192.168.201.1'
6643 09:55:33.175878 export NFS_SERVER_IP='192.168.201.1'
6644 09:55:33.176764 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6645 09:55:33.177305 end: 2.2 depthcharge-retry (duration 00:01:13) [common]
6646 09:55:33.177856 end: 2 depthcharge-action (duration 00:01:13) [common]
6647 09:55:33.178485 start: 3 lava-test-retry (timeout 00:30:00) [common]
6648 09:55:33.179031 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
6649 09:55:33.179458 Using namespace: common
6651 09:55:33.280853 / # #
6652 09:55:33.281566 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
6653 09:55:33.287104 #
6654 09:55:33.287908 Using /lava-14407606
6656 09:55:33.389113 / # export SHELL=/bin/sh
6657 09:55:33.395452 export SHELL=/bin/sh
6659 09:55:33.497264 / # . /lava-14407606/environment
6660 09:55:33.503801 . /lava-14407606/environment
6662 09:55:33.611802 / # /lava-14407606/bin/lava-test-runner /lava-14407606/0
6663 09:55:33.612453 Test shell timeout: 10s (minimum of the action and connection timeout)
6664 09:55:33.618319 /lava-14407606/bin/lava-test-runner /lava-14407606/0
6665 09:55:33.844326 + export TESTRUN_ID=0_lc-compliance
6666 09:55:33.850571 + cd /lava-14407606/0/tests/0_lc-compliance
6667 09:55:33.850983 + cat uuid
6668 09:55:33.856769 + UUID=14407606_1.6.2.3.1
6669 09:55:33.857162 + set +x
6670 09:55:33.863139 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 14407606_1.6.2.3.1>
6671 09:55:33.863803 Received signal: <STARTRUN> 0_lc-compliance 14407606_1.6.2.3.1
6672 09:55:33.864197 Starting test lava.0_lc-compliance (14407606_1.6.2.3.1)
6673 09:55:33.864574 Skipping test definition patterns.
6674 09:55:33.866386 + /usr/bin/lc-compliance-parser.sh
6675 09:55:35.540803 [0:00:20.426678923] [428] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:284 [0mlibcamera v0.0.0+1-01935edb
6676 09:55:35.547337 Using camera /base/soc/usb@11201000/usb@11200000/hub@1-1.3:1.0-04f2:b567
6677 09:55:35.595814 [0:00:20.482106846] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6678 09:55:35.627605 [==========] Running 120 tests from 1 test suite.
6679 09:55:35.666618 [0:00:20.552836692] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6680 09:55:35.707833 [----------] Global test environment set-up.
6681 09:55:35.731287 [0:00:20.617460000] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6682 09:55:35.784368 [----------] 120 tests from CaptureTests/SingleStream
6683 09:55:35.794754 [0:00:20.682608231] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6684 09:55:35.866791 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
6685 09:55:35.934444 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
6686 09:55:35.935157 Received signal: <TESTSET> START CaptureTests/SingleStream
6687 09:55:35.935510 Starting test_set CaptureTests/SingleStream
6688 09:55:35.937829 Camera needs 4 requests, can't test only 1
6689 09:55:36.008154 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6690 09:55:36.086927
6691 09:55:36.167688 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (70 ms)
6692 09:55:36.256300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
6693 09:55:36.256976 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
6695 09:55:36.270126 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
6696 09:55:36.317334 Camera needs 4 requests, can't test only 2
6697 09:55:36.400245 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6698 09:55:36.481095
6699 09:55:36.528088 [0:00:21.414427692] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6700 09:55:36.560630 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (63 ms)
6701 09:55:36.650834 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
6702 09:55:36.651680 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
6704 09:55:36.665743 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
6705 09:55:36.714044 Camera needs 4 requests, can't test only 3
6706 09:55:36.802381 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6707 09:55:36.878346
6708 09:55:36.968345 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (65 ms)
6709 09:55:37.060422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
6710 09:55:37.061111 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
6712 09:55:37.082208 [0:00:21.968389154] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6713 09:55:37.085685 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
6714 09:55:37.131772 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (732 ms)
6715 09:55:37.220048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
6716 09:55:37.220741 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
6718 09:55:37.234585 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
6719 09:55:37.283470 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (554 ms)
6720 09:55:37.367170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
6721 09:55:37.367877 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
6723 09:55:37.383566 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
6724 09:55:38.518159 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (1480 ms)
6725 09:55:38.563212 [0:00:23.448857693] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6726 09:55:38.608195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
6727 09:55:38.608837 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
6729 09:55:38.624225 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
6730 09:55:41.034878 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (2515 ms)
6731 09:55:41.078793 [0:00:25.964915462] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6732 09:55:41.121522 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
6733 09:55:41.122151 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
6735 09:55:41.141069 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
6736 09:55:44.845865 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (3811 ms)
6737 09:55:44.890639 [0:00:29.776922154] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6738 09:55:44.938668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
6739 09:55:44.939305 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
6741 09:55:44.953935 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
6742 09:55:50.750526 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (5904 ms)
6743 09:55:50.795163 [0:00:35.680996463] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6744 09:55:50.841393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
6745 09:55:50.842069 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
6747 09:55:50.859618 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
6748 09:55:52.957373 <6>[ 37.989823] vaux18: disabling
6749 09:55:52.961700 <6>[ 37.994368] vio28: disabling
6750 09:56:00.046778 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (9296 ms)
6751 09:56:00.093646 [0:00:44.978891540] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6752 09:56:00.136720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
6753 09:56:00.137351 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
6755 09:56:00.155180 [0:00:45.040910078] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6756 09:56:00.158887 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
6757 09:56:00.206068 Camera needs 4 requests, can't test only 1
6758 09:56:00.219813 [0:00:45.105606002] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6759 09:56:00.282117 [0:00:45.167723694] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6760 09:56:00.285238 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6761 09:56:00.355156
6762 09:56:00.437915 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (63 ms)
6763 09:56:00.531050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
6764 09:56:00.531749 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
6766 09:56:00.546452 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
6767 09:56:00.603671 Camera needs 4 requests, can't test only 2
6768 09:56:00.693908 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6769 09:56:00.770873
6770 09:56:00.855768 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (63 ms)
6771 09:56:00.939521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
6772 09:56:00.940212 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
6774 09:56:00.956358 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
6775 09:56:01.012137 Camera needs 4 requests, can't test only 3
6776 09:56:01.102219 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6777 09:56:01.179594
6778 09:56:01.267228 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (63 ms)
6779 09:56:01.371280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
6780 09:56:01.372269 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
6782 09:56:01.386242 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
6783 09:56:01.564831 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (1327 ms)
6784 09:56:01.609445 [0:00:46.495052155] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6785 09:56:01.660443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
6786 09:56:01.661173 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
6788 09:56:01.674899 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
6789 09:56:02.787652 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (1222 ms)
6790 09:56:02.831166 [0:00:47.717276771] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6791 09:56:02.873181 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
6792 09:56:02.873875 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
6794 09:56:02.888813 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
6795 09:56:04.511056 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (1720 ms)
6796 09:56:04.552895 [0:00:49.438457540] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6797 09:56:04.603153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
6798 09:56:04.603872 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
6800 09:56:04.618757 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
6801 09:56:07.025946 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (2518 ms)
6802 09:56:07.070883 [0:00:51.956785310] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6803 09:56:07.123440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
6804 09:56:07.124131 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
6806 09:56:07.139967 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
6807 09:56:10.840414 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (3813 ms)
6808 09:56:10.885818 [0:00:55.770488925] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6809 09:56:10.938813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
6810 09:56:10.939506 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
6812 09:56:10.955657 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
6813 09:56:16.746477 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (5905 ms)
6814 09:56:16.790615 [0:01:01.675928541] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6815 09:56:16.840436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
6816 09:56:16.841103 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
6818 09:56:16.855198 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
6819 09:56:26.046956 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (9297 ms)
6820 09:56:26.088655 [0:01:10.974022695] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6821 09:56:26.132525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
6822 09:56:26.133169 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
6824 09:56:26.151693 [0:01:11.036523080] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6825 09:56:26.155085 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
6826 09:56:26.205054 Camera needs 4 requests, can't test only 1
6827 09:56:26.214808 [0:01:11.100801618] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6828 09:56:26.280826 [0:01:11.165896695] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6829 09:56:26.284317 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6830 09:56:26.362587
6831 09:56:26.441695 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (61 ms)
6832 09:56:26.537570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
6833 09:56:26.538286 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
6835 09:56:26.552147 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
6836 09:56:26.608519 Camera needs 4 requests, can't test only 2
6837 09:56:26.696244 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6838 09:56:26.776248
6839 09:56:26.859722 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (64 ms)
6840 09:56:26.957537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
6841 09:56:26.958269 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
6843 09:56:26.975326 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
6844 09:56:27.030816 Camera needs 4 requests, can't test only 3
6845 09:56:27.113276 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6846 09:56:27.188043
6847 09:56:27.274499 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (63 ms)
6848 09:56:27.360935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
6849 09:56:27.361583 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
6851 09:56:27.376357 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
6852 09:56:27.563383 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (1329 ms)
6853 09:56:27.607183 [0:01:12.492344772] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6854 09:56:27.656803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
6855 09:56:27.657577 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
6857 09:56:27.673860 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
6858 09:56:28.783799 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (1220 ms)
6859 09:56:28.828239 [0:01:13.713214542] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6860 09:56:28.876084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
6861 09:56:28.877346 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
6863 09:56:28.890566 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
6864 09:56:30.509466 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (1722 ms)
6865 09:56:30.550565 [0:01:15.435291388] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6866 09:56:30.596766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
6867 09:56:30.597137 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
6869 09:56:30.610414 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
6870 09:56:33.022746 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (2516 ms)
6871 09:56:33.067292 [0:01:17.952633465] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6872 09:56:33.102984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
6873 09:56:33.103237 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
6875 09:56:33.116747 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
6876 09:56:36.835659 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (3812 ms)
6877 09:56:36.881592 [0:01:21.766257388] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6878 09:56:36.921934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
6879 09:56:36.922403 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
6881 09:56:36.934414 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
6882 09:56:42.741778 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (5906 ms)
6883 09:56:42.787455 [0:01:27.671811081] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6884 09:56:42.834412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
6885 09:56:42.835045 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
6887 09:56:42.847995 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
6888 09:56:52.039878 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (9297 ms)
6889 09:56:52.084566 [0:01:36.969423774] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6890 09:56:52.133298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
6891 09:56:52.133622 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
6893 09:56:52.149778 [0:01:37.034136389] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6894 09:56:52.152813 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
6895 09:56:52.198839 Camera needs 4 requests, can't test only 1
6896 09:56:52.216982 [0:01:37.101364851] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6897 09:56:52.271557 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6898 09:56:52.287653 [0:01:37.172287466] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6899 09:56:52.346569
6900 09:56:52.424329 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (63 ms)
6901 09:56:52.516125 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
6902 09:56:52.516807 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
6904 09:56:52.533238 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
6905 09:56:52.585463 Camera needs 4 requests, can't test only 2
6906 09:56:52.660185 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6907 09:56:52.728976
6908 09:56:52.807168 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (66 ms)
6909 09:56:52.892412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
6910 09:56:52.893283 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
6912 09:56:52.908885 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
6913 09:56:52.954936 Camera needs 4 requests, can't test only 3
6914 09:56:53.034436 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6915 09:56:53.108778
6916 09:56:53.192227 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (68 ms)
6917 09:56:53.283113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
6918 09:56:53.283761 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
6920 09:56:53.298980 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
6921 09:56:53.563838 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (1324 ms)
6922 09:56:53.608880 [0:01:38.493454466] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6923 09:56:53.653725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
6924 09:56:53.654408 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
6926 09:56:53.668609 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
6927 09:56:54.786536 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (1222 ms)
6928 09:56:54.831004 [0:01:39.715533928] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6929 09:56:54.873822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
6930 09:56:54.874622 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
6932 09:56:54.890782 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
6933 09:56:56.506059 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (1720 ms)
6934 09:56:56.550674 [0:01:41.435427236] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6935 09:56:56.602959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
6936 09:56:56.603877 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
6938 09:56:56.618164 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
6939 09:56:59.023401 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (2516 ms)
6940 09:56:59.069102 [0:01:43.953358928] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6941 09:56:59.122998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
6942 09:56:59.123697 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
6944 09:56:59.138878 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
6945 09:57:02.838136 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (3814 ms)
6946 09:57:02.883380 [0:01:47.767569467] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6947 09:57:02.935587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
6948 09:57:02.936229 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
6950 09:57:02.951305 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
6951 09:57:08.743575 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (5905 ms)
6952 09:57:08.789619 [0:01:53.673416390] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6953 09:57:08.849197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
6954 09:57:08.849841 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
6956 09:57:08.866587 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
6957 09:57:18.042590 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (9298 ms)
6958 09:57:18.093061 [0:02:02.976875929] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6959 09:57:18.128815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
6960 09:57:18.129452 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
6962 09:57:18.143444 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
6963 09:57:18.158749 [0:02:03.042838006] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6964 09:57:18.192443 Camera needs 4 requests, can't test only 1
6965 09:57:18.228456 [0:02:03.112043698] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6966 09:57:18.270348 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6967 09:57:18.295454 [0:02:03.179233237] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6968 09:57:18.351247
6969 09:57:18.432822 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (67 ms)
6970 09:57:18.534427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
6971 09:57:18.535088 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
6973 09:57:18.550602 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
6974 09:57:18.607034 Camera needs 4 requests, can't test only 2
6975 09:57:18.694591 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6976 09:57:18.775548
6977 09:57:18.860555 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (68 ms)
6978 09:57:18.954916 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
6979 09:57:18.955607 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
6981 09:57:18.971338 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
6982 09:57:19.023503 Camera needs 4 requests, can't test only 3
6983 09:57:19.112253 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
6984 09:57:19.190368
6985 09:57:19.271384 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (68 ms)
6986 09:57:19.356228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
6987 09:57:19.356928 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
6989 09:57:19.373751 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
6990 09:57:21.320708 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (3070 ms)
6991 09:57:21.365502 [0:02:06.249499699] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6992 09:57:21.412474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
6993 09:57:21.413171 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
6995 09:57:21.428175 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
6996 09:57:24.888165 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (3567 ms)
6997 09:57:24.933263 [0:02:09.817162007] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
6998 09:57:24.976831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
6999 09:57:24.977470 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
7001 09:57:24.992430 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
7002 09:57:29.954879 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (5066 ms)
7003 09:57:29.999442 [0:02:14.882867468] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7004 09:57:30.043032 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
7005 09:57:30.043738 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
7007 09:57:30.059960 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
7008 09:57:37.409798 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (7455 ms)
7009 09:57:37.455126 [0:02:22.338947777] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7010 09:57:37.486107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
7011 09:57:37.486389 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
7013 09:57:37.497773 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
7014 09:57:48.753807 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (11342 ms)
7015 09:57:48.798050 [0:02:33.681451623] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7016 09:57:48.844369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
7017 09:57:48.845100 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
7019 09:57:48.859900 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
7020 09:58:06.370056 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (17616 ms)
7021 09:58:06.414370 [0:02:51.297459701] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7022 09:58:06.460772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
7023 09:58:06.461682 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
7025 09:58:06.475094 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
7026 09:58:34.161281 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (27790 ms)
7027 09:58:34.206774 [0:03:19.088719472] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7028 09:58:34.260118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
7029 09:58:34.260832 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
7031 09:58:34.272654 [0:03:19.151490780] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7032 09:58:34.279334 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
7033 09:58:34.328814 Camera needs 4 requests, can't test only 1
7034 09:58:34.338755 [0:03:19.218012165] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7035 09:58:34.400367 [0:03:19.282060703] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7036 09:58:34.403112 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7037 09:58:34.464397
7038 09:58:34.546702 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (62 ms)
7039 09:58:34.635992 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
7040 09:58:34.636262 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
7042 09:58:34.646100 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
7043 09:58:34.693302 Camera needs 4 requests, can't test only 2
7044 09:58:34.758771 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7045 09:58:34.834630
7046 09:58:34.911034 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (66 ms)
7047 09:58:34.991306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
7048 09:58:34.991581 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
7050 09:58:35.000002 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
7051 09:58:35.042071 Camera needs 4 requests, can't test only 3
7052 09:58:35.118515 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7053 09:58:35.187350
7054 09:58:35.256654 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (63 ms)
7055 09:58:35.340364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
7056 09:58:35.340768 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
7058 09:58:35.349826 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
7059 09:58:37.418760 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (3062 ms)
7060 09:58:37.460099 [0:03:22.342396934] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7061 09:58:37.500850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
7062 09:58:37.501493 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
7064 09:58:37.513838 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
7065 09:58:40.981706 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (3562 ms)
7066 09:58:41.022804 [0:03:25.904739011] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7067 09:58:41.071279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
7068 09:58:41.071960 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
7070 09:58:41.082618 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
7071 09:58:46.043014 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (5061 ms)
7072 09:58:46.084374 [0:03:30.966327319] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7073 09:58:46.129031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
7074 09:58:46.129725 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
7076 09:58:46.141242 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
7077 09:58:53.491928 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (7449 ms)
7078 09:58:53.534399 [0:03:38.416207627] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7079 09:58:53.585090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
7080 09:58:53.585733 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
7082 09:58:53.597514 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
7083 09:59:04.831917 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (11339 ms)
7084 09:59:04.873911 [0:03:49.755316474] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7085 09:59:04.919913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
7086 09:59:04.920191 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
7088 09:59:04.929839 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
7089 09:59:22.445593 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (17613 ms)
7090 09:59:22.489314 [0:04:07.370016475] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7091 09:59:22.545358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
7092 09:59:22.546042 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
7094 09:59:22.559806 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
7095 09:59:50.235222 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (27789 ms)
7096 09:59:50.277111 [0:04:35.157498169] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7097 09:59:50.308282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
7098 09:59:50.308578 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
7100 09:59:50.317889 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
7101 09:59:50.341824 [0:04:35.222922784] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7102 09:59:50.361232 Camera needs 4 requests, can't test only 1
7103 09:59:50.409806 [0:04:35.290521477] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7104 09:59:50.417377 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7105 09:59:50.478626 [0:04:35.359673861] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7106 09:59:50.478727
7107 09:59:50.553226 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (64 ms)
7108 09:59:50.624258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
7109 09:59:50.624551 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
7111 09:59:50.633130 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
7112 09:59:50.672859 Camera needs 4 requests, can't test only 2
7113 09:59:50.736027 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7114 09:59:50.795295
7115 09:59:50.863590 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (67 ms)
7116 09:59:50.938113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
7117 09:59:50.938405 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
7119 09:59:50.948994 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
7120 09:59:50.996115 Camera needs 4 requests, can't test only 3
7121 09:59:51.065915 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7122 09:59:51.132457
7123 09:59:51.212025 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (70 ms)
7124 09:59:51.286456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
7125 09:59:51.286720 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
7127 09:59:51.298154 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
7128 09:59:53.492817 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (3054 ms)
7129 09:59:53.534829 [0:04:38.415115323] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7130 09:59:53.567090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
7131 09:59:53.567427 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
7133 09:59:53.578590 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
7134 09:59:57.053475 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (3560 ms)
7135 09:59:57.097055 [0:04:41.977614016] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7136 09:59:57.129831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
7137 09:59:57.130123 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
7139 09:59:57.140822 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
7140 10:00:02.118850 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (5064 ms)
7141 10:00:02.162693 [0:04:47.043100554] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7142 10:00:02.210219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
7143 10:00:02.210915 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
7145 10:00:02.226257 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
7146 10:00:09.569383 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (7450 ms)
7147 10:00:09.615495 [0:04:54.495633863] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7148 10:00:09.666809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
7149 10:00:09.667509 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
7151 10:00:09.682298 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
7152 10:00:20.913668 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (11344 ms)
7153 10:00:20.957883 [0:05:05.837226094] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7154 10:00:21.004418 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
7155 10:00:21.005262 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
7157 10:00:21.014927 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
7158 10:00:38.528532 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (17614 ms)
7159 10:00:38.569699 [0:05:23.449100787] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7160 10:00:38.621372 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
7161 10:00:38.622199 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
7163 10:00:38.634354 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
7164 10:01:06.313072 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (27783 ms)
7165 10:01:06.354963 [0:05:51.233834097] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7166 10:01:06.409470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
7167 10:01:06.410161 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
7169 10:01:06.420145 [0:05:51.299590635] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7170 10:01:06.426363 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
7171 10:01:06.473488 Camera needs 4 requests, can't test only 1
7172 10:01:06.487167 [0:05:51.365740404] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7173 10:01:06.552463 [0:05:51.431224327] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7174 10:01:06.556452 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7175 10:01:06.630826
7176 10:01:06.716332 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (64 ms)
7177 10:01:06.804758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
7178 10:01:06.805532 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
7180 10:01:06.818934 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
7181 10:01:06.872853 Camera needs 4 requests, can't test only 2
7182 10:01:06.953205 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7183 10:01:07.029397
7184 10:01:07.114694 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (67 ms)
7185 10:01:07.203837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
7186 10:01:07.204614 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
7188 10:01:07.216808 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
7189 10:01:07.273451 Camera needs 4 requests, can't test only 3
7190 10:01:07.352931 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
7191 10:01:07.425021
7192 10:01:07.512185 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (64 ms)
7193 10:01:07.607365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
7194 10:01:07.608061 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
7196 10:01:07.623071 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
7197 10:01:09.569294 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (3059 ms)
7198 10:01:09.612285 [0:05:54.490977866] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7199 10:01:09.666497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
7200 10:01:09.667200 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
7202 10:01:09.678834 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
7203 10:01:13.132837 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (3563 ms)
7204 10:01:13.175448 [0:05:58.054554636] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7205 10:01:13.206870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
7206 10:01:13.207150 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
7208 10:01:13.215152 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
7209 10:01:18.195713 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (5062 ms)
7210 10:01:18.241070 [0:06:03.119195405] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7211 10:01:18.290266 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
7212 10:01:18.290917 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
7214 10:01:18.302558 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
7215 10:01:25.648712 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (7452 ms)
7216 10:01:25.691942 [0:06:10.570408329] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7217 10:01:25.741003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
7218 10:01:25.741690 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
7220 10:01:25.751923 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
7221 10:01:36.987021 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (11337 ms)
7222 10:01:37.028493 [0:06:21.906606945] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7223 10:01:37.073550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
7224 10:01:37.074195 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
7226 10:01:37.084432 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
7227 10:01:54.599118 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (17611 ms)
7228 10:01:54.641050 [0:06:39.518494715] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7229 10:01:54.702931 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
7230 10:01:54.703671 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
7232 10:01:54.717067 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
7233 10:02:22.394379 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (27794 ms)
7234 10:02:22.436232 [0:07:07.313150101] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7235 10:02:22.503111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
7236 10:02:22.503813 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
7238 10:02:22.518900 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
7239 10:02:22.919371 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (528 ms)
7240 10:02:22.964792 [0:07:07.841878486] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7241 10:02:23.017589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
7242 10:02:23.018296 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
7244 10:02:23.034109 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
7245 10:02:23.546394 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (626 ms)
7246 10:02:23.592941 [0:07:08.469929563] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7247 10:02:23.646220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
7248 10:02:23.646914 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
7250 10:02:23.662389 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
7251 10:02:24.274445 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (727 ms)
7252 10:02:24.318696 [0:07:09.195425332] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7253 10:02:24.367361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
7254 10:02:24.368077 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
7256 10:02:24.384251 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
7257 10:02:25.196669 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (922 ms)
7258 10:02:25.240522 [0:07:10.117637486] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7259 10:02:25.297017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
7260 10:02:25.297657 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
7262 10:02:25.315613 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
7263 10:02:26.418113 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (1221 ms)
7264 10:02:26.462560 [0:07:11.339615255] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7265 10:02:26.514881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
7266 10:02:26.515277 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
7268 10:02:26.531414 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
7269 10:02:28.138133 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (1720 ms)
7270 10:02:28.182755 [0:07:13.059577640] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7271 10:02:28.233019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
7272 10:02:28.233698 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
7274 10:02:28.249414 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
7275 10:02:30.655899 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (2517 ms)
7276 10:02:30.700866 [0:07:15.577979717] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7277 10:02:30.759538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
7278 10:02:30.760231 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
7280 10:02:30.776729 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
7281 10:02:34.472365 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (3816 ms)
7282 10:02:34.517633 [0:07:19.394085948] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7283 10:02:34.566034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
7284 10:02:34.566694 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
7286 10:02:34.581188 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
7287 10:02:40.377044 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (5904 ms)
7288 10:02:40.421732 [0:07:25.298341948] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7289 10:02:40.461757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
7290 10:02:40.462432 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
7292 10:02:40.477684 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
7293 10:02:49.671183 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (9294 ms)
7294 10:02:49.715910 [0:07:34.592371180] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7295 10:02:49.761595 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
7296 10:02:49.762270 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
7298 10:02:49.776920 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
7299 10:02:50.199025 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (524 ms)
7300 10:02:50.240772 [0:07:35.117029641] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7301 10:02:50.284536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
7302 10:02:50.285186 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
7304 10:02:50.295810 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
7305 10:02:50.823523 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (624 ms)
7306 10:02:50.865168 [0:07:35.741975488] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7307 10:02:50.907896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
7308 10:02:50.908546 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
7310 10:02:50.921596 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
7311 10:02:51.545131 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (721 ms)
7312 10:02:51.587112 [0:07:36.463455180] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7313 10:02:51.632645 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
7314 10:02:51.633316 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
7316 10:02:51.646039 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
7317 10:02:52.464721 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (920 ms)
7318 10:02:52.506080 [0:07:37.382713026] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7319 10:02:52.545797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
7320 10:02:52.546502 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
7322 10:02:52.559571 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
7323 10:02:53.687502 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (1222 ms)
7324 10:02:53.729344 [0:07:38.605445180] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7325 10:02:53.774950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
7326 10:02:53.775604 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
7328 10:02:53.788855 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
7329 10:02:55.410543 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (1722 ms)
7330 10:02:55.452614 [0:07:40.328930334] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7331 10:02:55.506722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
7332 10:02:55.507364 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
7334 10:02:55.517302 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
7335 10:02:57.930367 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (2519 ms)
7336 10:02:57.971599 [0:07:42.847908180] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7337 10:02:58.019764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
7338 10:02:58.020473 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
7340 10:02:58.031839 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
7341 10:03:01.741827 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (3811 ms)
7342 10:03:01.783307 [0:07:46.659415104] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7343 10:03:01.828598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
7344 10:03:01.829250 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
7346 10:03:01.839894 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
7347 10:03:07.646157 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (5904 ms)
7348 10:03:07.686963 [0:07:52.563290950] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7349 10:03:07.736096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
7350 10:03:07.736758 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
7352 10:03:07.748768 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
7353 10:03:16.942771 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (9296 ms)
7354 10:03:16.983956 [0:08:01.859922412] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7355 10:03:17.026667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
7356 10:03:17.027306 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
7358 10:03:17.038389 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
7359 10:03:17.466814 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (524 ms)
7360 10:03:17.509053 [0:08:02.385218797] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7361 10:03:17.547170 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
7362 10:03:17.547843 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
7364 10:03:17.559708 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
7365 10:03:18.093304 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (625 ms)
7366 10:03:18.133632 [0:08:03.009355335] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7367 10:03:18.191203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
7368 10:03:18.191888 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
7370 10:03:18.202063 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
7371 10:03:18.814300 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (721 ms)
7372 10:03:18.856990 [0:08:03.732041028] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7373 10:03:18.903679 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
7374 10:03:18.904339 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
7376 10:03:18.914879 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
7377 10:03:19.736127 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (921 ms)
7378 10:03:19.777494 [0:08:04.653579259] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7379 10:03:19.829156 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
7380 10:03:19.829821 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
7382 10:03:19.839833 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
7383 10:03:20.957177 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (1220 ms)
7384 10:03:20.998590 [0:08:05.874388797] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7385 10:03:21.053186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
7386 10:03:21.053877 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
7388 10:03:21.065062 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
7389 10:03:22.677344 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (1719 ms)
7390 10:03:22.718799 [0:08:07.594571259] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7391 10:03:22.786026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
7392 10:03:22.786721 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
7394 10:03:22.798677 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
7395 10:03:25.195654 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (2517 ms)
7396 10:03:25.238332 [0:08:10.113739874] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7397 10:03:25.292394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
7398 10:03:25.293089 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
7400 10:03:25.305747 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
7401 10:03:29.009425 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (3813 ms)
7402 10:03:29.053032 [0:08:13.928482798] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7403 10:03:29.107219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
7404 10:03:29.107948 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
7406 10:03:29.122345 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
7407 10:03:34.915388 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (5905 ms)
7408 10:03:34.957474 [0:08:19.833014567] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7409 10:03:35.004842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
7410 10:03:35.005485 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
7412 10:03:35.017054 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
7413 10:03:44.212720 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (9297 ms)
7414 10:03:44.255165 [0:08:29.130567798] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7415 10:03:44.297453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
7416 10:03:44.298088 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
7418 10:03:44.309078 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
7419 10:03:44.738409 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (526 ms)
7420 10:03:44.780276 [0:08:29.655489952] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7421 10:03:44.828815 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
7423 10:03:44.831762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
7424 10:03:44.843146 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
7425 10:03:45.364331 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (625 ms)
7426 10:03:45.407686 [0:08:30.283142568] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7427 10:03:45.449620 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
7429 10:03:45.453172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
7430 10:03:45.462637 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
7431 10:03:46.090889 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (725 ms)
7432 10:03:46.133688 [0:08:31.008373875] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7433 10:03:46.178034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
7434 10:03:46.178780 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
7436 10:03:46.190476 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
7437 10:03:47.012194 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (921 ms)
7438 10:03:47.053571 [0:08:31.928612799] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7439 10:03:47.100080 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
7441 10:03:47.102898 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
7442 10:03:47.116630 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
7443 10:03:48.233455 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (1221 ms)
7444 10:03:48.274899 [0:08:33.150095414] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7445 10:03:48.319952 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
7447 10:03:48.322517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
7448 10:03:48.336584 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
7449 10:03:49.953763 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (1720 ms)
7450 10:03:49.996950 [0:08:34.871261491] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7451 10:03:50.044717 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
7452 10:03:50.045361 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
7454 10:03:50.059494 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
7455 10:03:52.472726 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (2517 ms)
7456 10:03:52.514446 [0:08:37.389799184] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7457 10:03:52.560807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
7458 10:03:52.561514 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
7460 10:03:52.574144 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
7461 10:03:56.286566 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (3814 ms)
7462 10:03:56.328734 [0:08:41.203069953] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7463 10:03:56.376198 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
7465 10:03:56.380073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
7466 10:03:56.393479 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
7467 10:04:02.192141 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (5905 ms)
7468 10:04:02.233465 [0:08:47.108198184] [428] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1183 [0mconfiguring streams: (0) 1280x720-MJPEG
7469 10:04:02.282576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
7470 10:04:02.283342 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
7472 10:04:02.293907 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
7473 10:04:11.488619 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (9296 ms)
7474 10:04:11.557269 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
7476 10:04:11.560230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
7477 10:04:11.568947 [----------] 120 tests from CaptureTests/SingleStream (515923 ms total)
7478 10:04:11.625310
7479 10:04:11.691181 [----------] Global test environment tear-down
7480 10:04:11.767581 [==========] 120 tests from 1 test suite ran. (515923 ms total)
7481 10:04:11.847805 <LAVA_SIGNAL_TESTSET STOP>
7482 10:04:11.848082 Received signal: <TESTSET> STOP
7483 10:04:11.848172 Closing test_set CaptureTests/SingleStream
7484 10:04:11.851069 + set +x
7485 10:04:11.854550 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 14407606_1.6.2.3.1>
7486 10:04:11.854778 Received signal: <ENDRUN> 0_lc-compliance 14407606_1.6.2.3.1
7487 10:04:11.854850 Ending use of test pattern.
7488 10:04:11.854904 Ending test lava.0_lc-compliance (14407606_1.6.2.3.1), duration 517.99
7490 10:04:11.857338 <LAVA_TEST_RUNNER EXIT>
7491 10:04:11.857569 ok: lava_test_shell seems to have completed
7492 10:04:11.859798 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
7493 10:04:11.860010 end: 3.1 lava-test-shell (duration 00:08:39) [common]
7494 10:04:11.860109 end: 3 lava-test-retry (duration 00:08:39) [common]
7495 10:04:11.860193 start: 4 finalize (timeout 00:10:00) [common]
7496 10:04:11.860276 start: 4.1 power-off (timeout 00:00:30) [common]
7497 10:04:11.860412 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-1', '--port=1', '--command=off']
7498 10:04:12.752350 >> Command sent successfully.
7499 10:04:12.766770 Returned 0 in 0 seconds
7500 10:04:12.868002 end: 4.1 power-off (duration 00:00:01) [common]
7502 10:04:12.869573 start: 4.2 read-feedback (timeout 00:09:59) [common]
7503 10:04:12.870962 Listened to connection for namespace 'common' for up to 1s
7504 10:04:13.871641 Finalising connection for namespace 'common'
7505 10:04:13.872287 Disconnecting from shell: Finalise
7506 10:04:13.872757 / #
7507 10:04:13.973761 end: 4.2 read-feedback (duration 00:00:01) [common]
7508 10:04:13.974566 end: 4 finalize (duration 00:00:02) [common]
7509 10:04:13.975281 Cleaning after the job
7510 10:04:13.975857 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/ramdisk
7511 10:04:13.986542 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/kernel
7512 10:04:14.018381 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/dtb
7513 10:04:14.018739 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/nfsrootfs
7514 10:04:14.064433 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407606/tftp-deploy-js1wnew3/modules
7515 10:04:14.070158 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407606
7516 10:04:14.321052 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407606
7517 10:04:14.321216 Job finished correctly