Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 1
- Kernel Errors: 46
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 87
1 09:53:52.031385 lava-dispatcher, installed at version: 2024.03
2 09:53:52.031626 start: 0 validate
3 09:53:52.031777 Start time: 2024-06-18 09:53:52.031769+00:00 (UTC)
4 09:53:52.031914 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:53:52.032059 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 09:53:52.321700 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:53:52.322440 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:53:52.575319 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:53:52.576152 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 09:53:52.829193 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:53:52.829889 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:53:53.338377 validate duration: 1.31
14 09:53:53.339645 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:53:53.340243 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:53:53.340758 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:53:53.341324 Not decompressing ramdisk as can be used compressed.
18 09:53:53.341756 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 09:53:53.342090 saving as /var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/ramdisk/rootfs.cpio.gz
20 09:53:53.342404 total size: 28105535 (26 MB)
21 09:53:53.347060 progress 0 % (0 MB)
22 09:53:53.375940 progress 5 % (1 MB)
23 09:53:53.388911 progress 10 % (2 MB)
24 09:53:53.398466 progress 15 % (4 MB)
25 09:53:53.406505 progress 20 % (5 MB)
26 09:53:53.414488 progress 25 % (6 MB)
27 09:53:53.422500 progress 30 % (8 MB)
28 09:53:53.430525 progress 35 % (9 MB)
29 09:53:53.438544 progress 40 % (10 MB)
30 09:53:53.446312 progress 45 % (12 MB)
31 09:53:53.454281 progress 50 % (13 MB)
32 09:53:53.462343 progress 55 % (14 MB)
33 09:53:53.470430 progress 60 % (16 MB)
34 09:53:53.478418 progress 65 % (17 MB)
35 09:53:53.486383 progress 70 % (18 MB)
36 09:53:53.494481 progress 75 % (20 MB)
37 09:53:53.502457 progress 80 % (21 MB)
38 09:53:53.510486 progress 85 % (22 MB)
39 09:53:53.518225 progress 90 % (24 MB)
40 09:53:53.526050 progress 95 % (25 MB)
41 09:53:53.533869 progress 100 % (26 MB)
42 09:53:53.534097 26 MB downloaded in 0.19 s (139.81 MB/s)
43 09:53:53.534266 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:53:53.534656 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:53:53.534751 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:53:53.534845 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:53:53.534991 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:53:53.535072 saving as /var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/kernel/Image
50 09:53:53.535139 total size: 54813184 (52 MB)
51 09:53:53.535207 No compression specified
52 09:53:53.536447 progress 0 % (0 MB)
53 09:53:53.551852 progress 5 % (2 MB)
54 09:53:53.567295 progress 10 % (5 MB)
55 09:53:53.582573 progress 15 % (7 MB)
56 09:53:53.598004 progress 20 % (10 MB)
57 09:53:53.613425 progress 25 % (13 MB)
58 09:53:53.629002 progress 30 % (15 MB)
59 09:53:53.644727 progress 35 % (18 MB)
60 09:53:53.660467 progress 40 % (20 MB)
61 09:53:53.675934 progress 45 % (23 MB)
62 09:53:53.691385 progress 50 % (26 MB)
63 09:53:53.706832 progress 55 % (28 MB)
64 09:53:53.722609 progress 60 % (31 MB)
65 09:53:53.738721 progress 65 % (34 MB)
66 09:53:53.754716 progress 70 % (36 MB)
67 09:53:53.771204 progress 75 % (39 MB)
68 09:53:53.787086 progress 80 % (41 MB)
69 09:53:53.802382 progress 85 % (44 MB)
70 09:53:53.817897 progress 90 % (47 MB)
71 09:53:53.833256 progress 95 % (49 MB)
72 09:53:53.848263 progress 100 % (52 MB)
73 09:53:53.848524 52 MB downloaded in 0.31 s (166.81 MB/s)
74 09:53:53.848736 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:53:53.849002 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:53:53.849095 start: 1.3 download-retry (timeout 00:09:59) [common]
78 09:53:53.849186 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 09:53:53.849328 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
80 09:53:53.849409 saving as /var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
81 09:53:53.849475 total size: 57695 (0 MB)
82 09:53:53.849541 No compression specified
83 09:53:53.850787 progress 56 % (0 MB)
84 09:53:53.851090 progress 100 % (0 MB)
85 09:53:53.851312 0 MB downloaded in 0.00 s (30.00 MB/s)
86 09:53:53.851456 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:53:53.851702 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:53:53.851798 start: 1.4 download-retry (timeout 00:09:59) [common]
90 09:53:53.851890 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 09:53:53.852016 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:53:53.852089 saving as /var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/modules/modules.tar
93 09:53:53.852155 total size: 8619356 (8 MB)
94 09:53:53.852220 Using unxz to decompress xz
95 09:53:53.856597 progress 0 % (0 MB)
96 09:53:53.878460 progress 5 % (0 MB)
97 09:53:53.905930 progress 10 % (0 MB)
98 09:53:53.933942 progress 15 % (1 MB)
99 09:53:53.961136 progress 20 % (1 MB)
100 09:53:53.989830 progress 25 % (2 MB)
101 09:53:54.017718 progress 30 % (2 MB)
102 09:53:54.045338 progress 35 % (2 MB)
103 09:53:54.072423 progress 40 % (3 MB)
104 09:53:54.099769 progress 45 % (3 MB)
105 09:53:54.126766 progress 50 % (4 MB)
106 09:53:54.155169 progress 55 % (4 MB)
107 09:53:54.182904 progress 60 % (4 MB)
108 09:53:54.209226 progress 65 % (5 MB)
109 09:53:54.240894 progress 70 % (5 MB)
110 09:53:54.268888 progress 75 % (6 MB)
111 09:53:54.294878 progress 80 % (6 MB)
112 09:53:54.320956 progress 85 % (7 MB)
113 09:53:54.347391 progress 90 % (7 MB)
114 09:53:54.378700 progress 95 % (7 MB)
115 09:53:54.412387 progress 100 % (8 MB)
116 09:53:54.417547 8 MB downloaded in 0.57 s (14.54 MB/s)
117 09:53:54.417863 end: 1.4.1 http-download (duration 00:00:01) [common]
119 09:53:54.418298 end: 1.4 download-retry (duration 00:00:01) [common]
120 09:53:54.418436 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 09:53:54.418573 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 09:53:54.418696 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:53:54.418826 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 09:53:54.419120 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0
125 09:53:54.419309 makedir: /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin
126 09:53:54.419467 makedir: /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/tests
127 09:53:54.419611 makedir: /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/results
128 09:53:54.419773 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-add-keys
129 09:53:54.419969 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-add-sources
130 09:53:54.420148 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-background-process-start
131 09:53:54.420328 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-background-process-stop
132 09:53:54.420502 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-common-functions
133 09:53:54.420675 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-echo-ipv4
134 09:53:54.420851 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-install-packages
135 09:53:54.421025 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-installed-packages
136 09:53:54.421197 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-os-build
137 09:53:54.421370 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-probe-channel
138 09:53:54.421543 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-probe-ip
139 09:53:54.421716 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-target-ip
140 09:53:54.421887 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-target-mac
141 09:53:54.422058 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-target-storage
142 09:53:54.422237 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-test-case
143 09:53:54.422412 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-test-event
144 09:53:54.422584 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-test-feedback
145 09:53:54.422755 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-test-raise
146 09:53:54.422927 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-test-reference
147 09:53:54.423066 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-test-runner
148 09:53:54.423256 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-test-set
149 09:53:54.423435 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-test-shell
150 09:53:54.423579 Updating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-install-packages (oe)
151 09:53:54.423748 Updating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/bin/lava-installed-packages (oe)
152 09:53:54.423882 Creating /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/environment
153 09:53:54.423993 LAVA metadata
154 09:53:54.424074 - LAVA_JOB_ID=14407602
155 09:53:54.424145 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:53:54.424256 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 09:53:54.424332 skipped lava-vland-overlay
158 09:53:54.424413 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:53:54.424505 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 09:53:54.424584 skipped lava-multinode-overlay
161 09:53:54.424664 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:53:54.424754 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 09:53:54.424855 Loading test definitions
164 09:53:54.424958 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 09:53:54.425040 Using /lava-14407602 at stage 0
166 09:53:54.425432 uuid=14407602_1.5.2.3.1 testdef=None
167 09:53:54.425534 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:53:54.425632 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 09:53:54.426196 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:53:54.426445 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 09:53:54.427219 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:53:54.427550 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 09:53:54.428234 runner path: /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/0/tests/0_v4l2-compliance-uvc test_uuid 14407602_1.5.2.3.1
176 09:53:54.428414 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:53:54.428641 Creating lava-test-runner.conf files
179 09:53:54.428712 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407602/lava-overlay-z7bhk3v0/lava-14407602/0 for stage 0
180 09:53:54.428811 - 0_v4l2-compliance-uvc
181 09:53:54.428919 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 09:53:54.429016 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 09:53:54.437027 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 09:53:54.437144 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 09:53:54.437240 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 09:53:54.437335 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 09:53:54.437433 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 09:53:55.413512 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 09:53:55.413928 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 09:53:55.414055 extracting modules file /var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407602/extract-overlay-ramdisk-fl05wyhl/ramdisk
191 09:53:55.659317 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 09:53:55.659510 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 09:53:55.659617 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407602/compress-overlay-ritja_gd/overlay-1.5.2.4.tar.gz to ramdisk
194 09:53:55.659697 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407602/compress-overlay-ritja_gd/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407602/extract-overlay-ramdisk-fl05wyhl/ramdisk
195 09:53:55.667056 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 09:53:55.667187 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 09:53:55.667282 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 09:53:55.667383 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 09:53:55.667483 Building ramdisk /var/lib/lava/dispatcher/tmp/14407602/extract-overlay-ramdisk-fl05wyhl/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407602/extract-overlay-ramdisk-fl05wyhl/ramdisk
200 09:53:56.408450 >> 276012 blocks
201 09:54:00.963219 rename /var/lib/lava/dispatcher/tmp/14407602/extract-overlay-ramdisk-fl05wyhl/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/ramdisk/ramdisk.cpio.gz
202 09:54:00.963725 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 09:54:00.963870 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 09:54:00.963980 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 09:54:00.964105 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/kernel/Image']
206 09:54:15.063544 Returned 0 in 14 seconds
207 09:54:15.164552 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/kernel/image.itb
208 09:54:15.873605 output: FIT description: Kernel Image image with one or more FDT blobs
209 09:54:15.874058 output: Created: Tue Jun 18 10:54:15 2024
210 09:54:15.874150 output: Image 0 (kernel-1)
211 09:54:15.874224 output: Description:
212 09:54:15.874294 output: Created: Tue Jun 18 10:54:15 2024
213 09:54:15.874366 output: Type: Kernel Image
214 09:54:15.874429 output: Compression: lzma compressed
215 09:54:15.874493 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
216 09:54:15.874558 output: Architecture: AArch64
217 09:54:15.874618 output: OS: Linux
218 09:54:15.874678 output: Load Address: 0x00000000
219 09:54:15.874737 output: Entry Point: 0x00000000
220 09:54:15.874798 output: Hash algo: crc32
221 09:54:15.874857 output: Hash value: 4137a6e7
222 09:54:15.874918 output: Image 1 (fdt-1)
223 09:54:15.874978 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
224 09:54:15.875041 output: Created: Tue Jun 18 10:54:15 2024
225 09:54:15.875104 output: Type: Flat Device Tree
226 09:54:15.875162 output: Compression: uncompressed
227 09:54:15.875220 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
228 09:54:15.875277 output: Architecture: AArch64
229 09:54:15.875335 output: Hash algo: crc32
230 09:54:15.875392 output: Hash value: a9713552
231 09:54:15.875463 output: Image 2 (ramdisk-1)
232 09:54:15.875521 output: Description: unavailable
233 09:54:15.875579 output: Created: Tue Jun 18 10:54:15 2024
234 09:54:15.875637 output: Type: RAMDisk Image
235 09:54:15.875694 output: Compression: Unknown Compression
236 09:54:15.875752 output: Data Size: 41219809 Bytes = 40253.72 KiB = 39.31 MiB
237 09:54:15.875810 output: Architecture: AArch64
238 09:54:15.875867 output: OS: Linux
239 09:54:15.875930 output: Load Address: unavailable
240 09:54:15.876002 output: Entry Point: unavailable
241 09:54:15.876061 output: Hash algo: crc32
242 09:54:15.876118 output: Hash value: 30a7ad9d
243 09:54:15.876175 output: Default Configuration: 'conf-1'
244 09:54:15.876233 output: Configuration 0 (conf-1)
245 09:54:15.876290 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
246 09:54:15.876348 output: Kernel: kernel-1
247 09:54:15.876405 output: Init Ramdisk: ramdisk-1
248 09:54:15.876463 output: FDT: fdt-1
249 09:54:15.876520 output: Loadables: kernel-1
250 09:54:15.876576 output:
251 09:54:15.876800 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 09:54:15.876902 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 09:54:15.877015 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 09:54:15.877116 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
255 09:54:15.877203 No LXC device requested
256 09:54:15.877292 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 09:54:15.877383 start: 1.7 deploy-device-env (timeout 00:09:37) [common]
258 09:54:15.877472 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 09:54:15.877545 Checking files for TFTP limit of 4294967296 bytes.
260 09:54:15.878163 end: 1 tftp-deploy (duration 00:00:23) [common]
261 09:54:15.878277 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 09:54:15.878379 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 09:54:15.878513 substitutions:
264 09:54:15.878588 - {DTB}: 14407602/tftp-deploy-bxltqb1m/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
265 09:54:15.878659 - {INITRD}: 14407602/tftp-deploy-bxltqb1m/ramdisk/ramdisk.cpio.gz
266 09:54:15.878725 - {KERNEL}: 14407602/tftp-deploy-bxltqb1m/kernel/Image
267 09:54:15.878788 - {LAVA_MAC}: None
268 09:54:15.878850 - {PRESEED_CONFIG}: None
269 09:54:15.878911 - {PRESEED_LOCAL}: None
270 09:54:15.878971 - {RAMDISK}: 14407602/tftp-deploy-bxltqb1m/ramdisk/ramdisk.cpio.gz
271 09:54:15.879031 - {ROOT_PART}: None
272 09:54:15.879091 - {ROOT}: None
273 09:54:15.879150 - {SERVER_IP}: 192.168.201.1
274 09:54:15.879209 - {TEE}: None
275 09:54:15.879268 Parsed boot commands:
276 09:54:15.879328 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 09:54:15.879530 Parsed boot commands: tftpboot 192.168.201.1 14407602/tftp-deploy-bxltqb1m/kernel/image.itb 14407602/tftp-deploy-bxltqb1m/kernel/cmdline
278 09:54:15.879630 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 09:54:15.879727 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 09:54:15.879837 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 09:54:15.879939 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 09:54:15.880016 Not connected, no need to disconnect.
283 09:54:15.880097 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 09:54:15.880185 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 09:54:15.880258 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-0'
286 09:54:15.884247 Setting prompt string to ['lava-test: # ']
287 09:54:15.884644 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 09:54:15.884760 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 09:54:15.884867 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 09:54:15.884963 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 09:54:15.885166 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-0']
292 09:54:40.470578 Returned 0 in 24 seconds
293 09:54:40.572033 end: 2.2.2.1 pdu-reboot (duration 00:00:25) [common]
295 09:54:40.574104 end: 2.2.2 reset-device (duration 00:00:25) [common]
296 09:54:40.574787 start: 2.2.3 depthcharge-start (timeout 00:04:35) [common]
297 09:54:40.575452 Setting prompt string to 'Starting depthcharge on Juniper...'
298 09:54:40.575843 Changing prompt to 'Starting depthcharge on Juniper...'
299 09:54:40.576211 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
300 09:54:40.578359 [Enter `^Ec?' for help]
301 09:54:40.578823 [DL] 00000000 00000000 010701
302 09:54:40.579192
303 09:54:40.579578
304 09:54:40.579919 F0: 102B 0000
305 09:54:40.580286
306 09:54:40.580610 F3: 1006 0033 [0200]
307 09:54:40.580973
308 09:54:40.581303 F3: 4001 00E0 [0200]
309 09:54:40.581624
310 09:54:40.581926 F3: 0000 0000
311 09:54:40.582282
312 09:54:40.582583 V0: 0000 0000 [0001]
313 09:54:40.582881
314 09:54:40.583177 00: 1027 0002
315 09:54:40.583544
316 09:54:40.583891 01: 0000 0000
317 09:54:40.584224
318 09:54:40.584567 BP: 0C00 0251 [0000]
319 09:54:40.585029
320 09:54:40.585312 G0: 1182 0000
321 09:54:40.585586
322 09:54:40.585855 EC: 0004 0000 [0001]
323 09:54:40.586145
324 09:54:40.586413 S7: 0000 0000 [0000]
325 09:54:40.586681
326 09:54:40.586945 CC: 0000 0000 [0001]
327 09:54:40.587209
328 09:54:40.587537 T0: 0000 00DB [000F]
329 09:54:40.587820
330 09:54:40.588133 Jump to BL
331 09:54:40.588486
332 09:54:40.588763
333 09:54:40.589031
334 09:54:40.589298 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
335 09:54:40.589582 ARM64: Exception handlers installed.
336 09:54:40.589853 ARM64: Testing exception
337 09:54:40.590121 ARM64: Done test exception
338 09:54:40.590411 WDT: Last reset was cold boot
339 09:54:40.590677 SPI0(PAD0) initialized at 992727 Hz
340 09:54:40.590985 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
341 09:54:40.591256 Manufacturer: ef
342 09:54:40.591628 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
343 09:54:40.591905 Probing TPM: . done!
344 09:54:40.592192 TPM ready after 0 ms
345 09:54:40.592462 Connected to device vid:did:rid of 1ae0:0028:00
346 09:54:40.592730 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
347 09:54:40.592998 Initialized TPM device CR50 revision 0
348 09:54:40.593266 tlcl_send_startup: Startup return code is 0
349 09:54:40.593536 TPM: setup succeeded
350 09:54:40.593803 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
351 09:54:40.594071 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
352 09:54:40.594497 in-header: 03 19 00 00 08 00 00 00
353 09:54:40.594780 in-data: a2 e0 47 00 13 00 00 00
354 09:54:40.595049 Chrome EC: UHEPI supported
355 09:54:40.595317 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
356 09:54:40.595618 in-header: 03 a1 00 00 08 00 00 00
357 09:54:40.595889 in-data: 84 60 60 10 00 00 00 00
358 09:54:40.596155 Phase 1
359 09:54:40.596446 FMAP: area GBB found @ 3f5000 (12032 bytes)
360 09:54:40.596719 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
361 09:54:40.597023 VB2:vb2_check_recovery() Recovery was requested manually
362 09:54:40.597297 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
363 09:54:40.597566 Recovery requested (1009000e)
364 09:54:40.597832 tlcl_extend: response is 0
365 09:54:40.598101 tlcl_extend: response is 0
366 09:54:40.598385
367 09:54:40.598652
368 09:54:40.598944 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
369 09:54:40.599219 ARM64: Exception handlers installed.
370 09:54:40.599536 ARM64: Testing exception
371 09:54:40.599809 ARM64: Done test exception
372 09:54:40.600078 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xc268, sec=0x2014
373 09:54:40.600443 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
374 09:54:40.600930 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
375 09:54:40.601222 [RTC]rtc_get_frequency_meter,134: input=0xf, output=915
376 09:54:40.601492 [RTC]rtc_get_frequency_meter,134: input=0x7, output=778
377 09:54:40.601764 [RTC]rtc_get_frequency_meter,134: input=0xb, output=846
378 09:54:40.602032 [RTC]rtc_get_frequency_meter,134: input=0x9, output=812
379 09:54:40.602300 [RTC]rtc_get_frequency_meter,134: input=0x8, output=794
380 09:54:40.602564 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xc268
381 09:54:40.602801 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
382 09:54:40.602990 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
383 09:54:40.603180 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
384 09:54:40.603372 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
385 09:54:40.603590 in-header: 03 19 00 00 08 00 00 00
386 09:54:40.603781 in-data: a2 e0 47 00 13 00 00 00
387 09:54:40.604005 Chrome EC: UHEPI supported
388 09:54:40.604197 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
389 09:54:40.604391 in-header: 03 a1 00 00 08 00 00 00
390 09:54:40.604580 in-data: 84 60 60 10 00 00 00 00
391 09:54:40.604779 Skip loading cached calibration data
392 09:54:40.604971 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
393 09:54:40.605162 in-header: 03 a1 00 00 08 00 00 00
394 09:54:40.605350 in-data: 84 60 60 10 00 00 00 00
395 09:54:40.605540 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
396 09:54:40.605733 in-header: 03 a1 00 00 08 00 00 00
397 09:54:40.605922 in-data: 84 60 60 10 00 00 00 00
398 09:54:40.606112 ADC[3]: Raw value=216216 ID=1
399 09:54:40.606301 Manufacturer: ef
400 09:54:40.606490 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
401 09:54:40.606679 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
402 09:54:40.606871 CBFS @ 21000 size 3d4000
403 09:54:40.607060 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
404 09:54:40.607282 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
405 09:54:40.607489 CBFS: Found @ offset 3c700 size 44
406 09:54:40.607686 DRAM-K: Full Calibration
407 09:54:40.607830 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
408 09:54:40.607975 CBFS @ 21000 size 3d4000
409 09:54:40.608118 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
410 09:54:40.608261 CBFS: Locating 'fallback/dram'
411 09:54:40.608403 CBFS: Found @ offset 24b00 size 12268
412 09:54:40.608546 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
413 09:54:40.608691 ddr_geometry: 1, config: 0x0
414 09:54:40.608832 header.status = 0x0
415 09:54:40.608973 header.magic = 0x44524d4b (expected: 0x44524d4b)
416 09:54:40.609116 header.version = 0x5 (expected: 0x5)
417 09:54:40.609258 header.size = 0x8f0 (expected: 0x8f0)
418 09:54:40.609400 header.config = 0x0
419 09:54:40.609543 header.flags = 0x0
420 09:54:40.609684 header.checksum = 0x0
421 09:54:40.610109 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
422 09:54:40.610274 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
423 09:54:40.610424 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
424 09:54:40.610571 ddr_geometry:1
425 09:54:40.610714 [EMI] new MDL number = 1
426 09:54:40.610886 dram_cbt_mode_extern: 0
427 09:54:40.611033 dram_cbt_mode [RK0]: 0, [RK1]: 0
428 09:54:40.611177 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
429 09:54:40.611320
430 09:54:40.611481
431 09:54:40.611624 [Bianco] ETT version 0.0.0.1
432 09:54:40.611768 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
433 09:54:40.611925
434 09:54:40.612067 vSetVcoreByFreq with vcore:762500, freq=1600
435 09:54:40.612216
436 09:54:40.612358 [DramcInit]
437 09:54:40.612499 AutoRefreshCKEOff AutoREF OFF
438 09:54:40.612640 DDRPhyPLLSetting-CKEOFF
439 09:54:40.612775 DDRPhyPLLSetting-CKEON
440 09:54:40.612889
441 09:54:40.613002 Enable WDQS
442 09:54:40.613115 [ModeRegInit_LP4] CH0 RK0
443 09:54:40.613230 Write Rank0 MR13 =0x18
444 09:54:40.613345 Write Rank0 MR12 =0x5d
445 09:54:40.613459 Write Rank0 MR1 =0x56
446 09:54:40.613574 Write Rank0 MR2 =0x1a
447 09:54:40.613687 Write Rank0 MR11 =0x0
448 09:54:40.613821 Write Rank0 MR22 =0x38
449 09:54:40.613941 Write Rank0 MR14 =0x5d
450 09:54:40.614080 Write Rank0 MR3 =0x30
451 09:54:40.614195 Write Rank0 MR13 =0x58
452 09:54:40.614310 Write Rank0 MR12 =0x5d
453 09:54:40.614423 Write Rank0 MR1 =0x56
454 09:54:40.614536 Write Rank0 MR2 =0x2d
455 09:54:40.614651 Write Rank0 MR11 =0x23
456 09:54:40.614765 Write Rank0 MR22 =0x34
457 09:54:40.614877 Write Rank0 MR14 =0x10
458 09:54:40.614990 Write Rank0 MR3 =0x30
459 09:54:40.615103 Write Rank0 MR13 =0xd8
460 09:54:40.615215 [ModeRegInit_LP4] CH0 RK1
461 09:54:40.615328 Write Rank1 MR13 =0x18
462 09:54:40.615449 Write Rank1 MR12 =0x5d
463 09:54:40.615563 Write Rank1 MR1 =0x56
464 09:54:40.615676 Write Rank1 MR2 =0x1a
465 09:54:40.615788 Write Rank1 MR11 =0x0
466 09:54:40.615901 Write Rank1 MR22 =0x38
467 09:54:40.616015 Write Rank1 MR14 =0x5d
468 09:54:40.616128 Write Rank1 MR3 =0x30
469 09:54:40.616241 Write Rank1 MR13 =0x58
470 09:54:40.616354 Write Rank1 MR12 =0x5d
471 09:54:40.616467 Write Rank1 MR1 =0x56
472 09:54:40.616580 Write Rank1 MR2 =0x2d
473 09:54:40.616694 Write Rank1 MR11 =0x23
474 09:54:40.616807 Write Rank1 MR22 =0x34
475 09:54:40.616921 Write Rank1 MR14 =0x10
476 09:54:40.617034 Write Rank1 MR3 =0x30
477 09:54:40.617165 Write Rank1 MR13 =0xd8
478 09:54:40.617279 [ModeRegInit_LP4] CH1 RK0
479 09:54:40.617393 Write Rank0 MR13 =0x18
480 09:54:40.617507 Write Rank0 MR12 =0x5d
481 09:54:40.617620 Write Rank0 MR1 =0x56
482 09:54:40.617740 Write Rank0 MR2 =0x1a
483 09:54:40.617835 Write Rank0 MR11 =0x0
484 09:54:40.617929 Write Rank0 MR22 =0x38
485 09:54:40.618024 Write Rank0 MR14 =0x5d
486 09:54:40.618118 Write Rank0 MR3 =0x30
487 09:54:40.618213 Write Rank0 MR13 =0x58
488 09:54:40.618308 Write Rank0 MR12 =0x5d
489 09:54:40.618403 Write Rank0 MR1 =0x56
490 09:54:40.618498 Write Rank0 MR2 =0x2d
491 09:54:40.618593 Write Rank0 MR11 =0x23
492 09:54:40.618687 Write Rank0 MR22 =0x34
493 09:54:40.618782 Write Rank0 MR14 =0x10
494 09:54:40.618876 Write Rank0 MR3 =0x30
495 09:54:40.618971 Write Rank0 MR13 =0xd8
496 09:54:40.619065 [ModeRegInit_LP4] CH1 RK1
497 09:54:40.619160 Write Rank1 MR13 =0x18
498 09:54:40.619254 Write Rank1 MR12 =0x5d
499 09:54:40.619349 Write Rank1 MR1 =0x56
500 09:54:40.619487 Write Rank1 MR2 =0x1a
501 09:54:40.619586 Write Rank1 MR11 =0x0
502 09:54:40.619682 Write Rank1 MR22 =0x38
503 09:54:40.619779 Write Rank1 MR14 =0x5d
504 09:54:40.619873 Write Rank1 MR3 =0x30
505 09:54:40.619968 Write Rank1 MR13 =0x58
506 09:54:40.620062 Write Rank1 MR12 =0x5d
507 09:54:40.620156 Write Rank1 MR1 =0x56
508 09:54:40.620251 Write Rank1 MR2 =0x2d
509 09:54:40.620358 Write Rank1 MR11 =0x23
510 09:54:40.620482 Write Rank1 MR22 =0x34
511 09:54:40.620580 Write Rank1 MR14 =0x10
512 09:54:40.620676 Write Rank1 MR3 =0x30
513 09:54:40.620785 Write Rank1 MR13 =0xd8
514 09:54:40.620883 match AC timing 3
515 09:54:40.620980 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
516 09:54:40.621078 [MiockJmeterHQA]
517 09:54:40.621175 vSetVcoreByFreq with vcore:762500, freq=1600
518 09:54:40.621271
519 09:54:40.621367 MIOCK jitter meter ch=0
520 09:54:40.621464
521 09:54:40.621558 1T = (102-17) = 85 dly cells
522 09:54:40.621657 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 735/100 ps
523 09:54:40.621754 vSetVcoreByFreq with vcore:725000, freq=1200
524 09:54:40.621851
525 09:54:40.621946 MIOCK jitter meter ch=0
526 09:54:40.622041
527 09:54:40.622136 1T = (96-16) = 80 dly cells
528 09:54:40.622235 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
529 09:54:40.622332 vSetVcoreByFreq with vcore:725000, freq=800
530 09:54:40.622432
531 09:54:40.622550 MIOCK jitter meter ch=0
532 09:54:40.622700
533 09:54:40.622833 1T = (96-16) = 80 dly cells
534 09:54:40.622948 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
535 09:54:40.623036 vSetVcoreByFreq with vcore:762500, freq=1600
536 09:54:40.623121 vSetVcoreByFreq with vcore:762500, freq=1600
537 09:54:40.623205
538 09:54:40.623287 K DRVP
539 09:54:40.623369 1. OCD DRVP=0 CALOUT=0
540 09:54:40.623467 1. OCD DRVP=1 CALOUT=0
541 09:54:40.623553 1. OCD DRVP=2 CALOUT=0
542 09:54:40.623639 1. OCD DRVP=3 CALOUT=0
543 09:54:40.623723 1. OCD DRVP=4 CALOUT=0
544 09:54:40.623807 1. OCD DRVP=5 CALOUT=0
545 09:54:40.623891 1. OCD DRVP=6 CALOUT=0
546 09:54:40.623991 1. OCD DRVP=7 CALOUT=0
547 09:54:40.624076 1. OCD DRVP=8 CALOUT=0
548 09:54:40.624160 1. OCD DRVP=9 CALOUT=1
549 09:54:40.624243
550 09:54:40.624325 1. OCD DRVP calibration OK! DRVP=9
551 09:54:40.624410
552 09:54:40.624492
553 09:54:40.624573
554 09:54:40.624654 K ODTN
555 09:54:40.624735 3. OCD ODTN=0 ,CALOUT=1
556 09:54:40.624823 3. OCD ODTN=1 ,CALOUT=1
557 09:54:40.624908 3. OCD ODTN=2 ,CALOUT=1
558 09:54:40.624992 3. OCD ODTN=3 ,CALOUT=1
559 09:54:40.625075 3. OCD ODTN=4 ,CALOUT=1
560 09:54:40.625159 3. OCD ODTN=5 ,CALOUT=1
561 09:54:40.625242 3. OCD ODTN=6 ,CALOUT=1
562 09:54:40.625326 3. OCD ODTN=7 ,CALOUT=0
563 09:54:40.625410
564 09:54:40.625491 3. OCD ODTN calibration OK! ODTN=7
565 09:54:40.625575
566 09:54:40.625657 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=7
567 09:54:40.625740 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15
568 09:54:40.625822 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15 (After Adjust)
569 09:54:40.625906
570 09:54:40.625988 K DRVP
571 09:54:40.626070 1. OCD DRVP=0 CALOUT=0
572 09:54:40.626153 1. OCD DRVP=1 CALOUT=0
573 09:54:40.626237 1. OCD DRVP=2 CALOUT=0
574 09:54:40.626319 1. OCD DRVP=3 CALOUT=0
575 09:54:40.626403 1. OCD DRVP=4 CALOUT=0
576 09:54:40.626487 1. OCD DRVP=5 CALOUT=0
577 09:54:40.626570 1. OCD DRVP=6 CALOUT=0
578 09:54:40.626653 1. OCD DRVP=7 CALOUT=0
579 09:54:40.626736 1. OCD DRVP=8 CALOUT=0
580 09:54:40.626819 1. OCD DRVP=9 CALOUT=0
581 09:54:40.626901 1. OCD DRVP=10 CALOUT=0
582 09:54:40.626986 1. OCD DRVP=11 CALOUT=1
583 09:54:40.627070
584 09:54:40.627151 1. OCD DRVP calibration OK! DRVP=11
585 09:54:40.627247
586 09:54:40.627330
587 09:54:40.627421
588 09:54:40.627504 K ODTN
589 09:54:40.627587 3. OCD ODTN=0 ,CALOUT=1
590 09:54:40.627883 3. OCD ODTN=1 ,CALOUT=1
591 09:54:40.627973 3. OCD ODTN=2 ,CALOUT=1
592 09:54:40.628050 3. OCD ODTN=3 ,CALOUT=1
593 09:54:40.628124 3. OCD ODTN=4 ,CALOUT=1
594 09:54:40.628199 3. OCD ODTN=5 ,CALOUT=1
595 09:54:40.628271 3. OCD ODTN=6 ,CALOUT=1
596 09:54:40.628345 3. OCD ODTN=7 ,CALOUT=1
597 09:54:40.628418 3. OCD ODTN=8 ,CALOUT=1
598 09:54:40.628492 3. OCD ODTN=9 ,CALOUT=1
599 09:54:40.628565 3. OCD ODTN=10 ,CALOUT=1
600 09:54:40.628638 3. OCD ODTN=11 ,CALOUT=1
601 09:54:40.628712 3. OCD ODTN=12 ,CALOUT=1
602 09:54:40.628785 3. OCD ODTN=13 ,CALOUT=1
603 09:54:40.628859 3. OCD ODTN=14 ,CALOUT=1
604 09:54:40.628931 3. OCD ODTN=15 ,CALOUT=0
605 09:54:40.629005
606 09:54:40.629077 3. OCD ODTN calibration OK! ODTN=15
607 09:54:40.629151
608 09:54:40.629223 [SwImpedanceCal] DRVP=11, DRVN=9, ODTN=15
609 09:54:40.629296 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15
610 09:54:40.629370 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15 (After Adjust)
611 09:54:40.629442
612 09:54:40.629515 [DramcInit]
613 09:54:40.629587 AutoRefreshCKEOff AutoREF OFF
614 09:54:40.629660 DDRPhyPLLSetting-CKEOFF
615 09:54:40.629731 DDRPhyPLLSetting-CKEON
616 09:54:40.629803
617 09:54:40.629874 Enable WDQS
618 09:54:40.629946 ==
619 09:54:40.630017 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
620 09:54:40.630090 fsp= 1, odt_onoff= 1, Byte mode= 0
621 09:54:40.630163 ==
622 09:54:40.630236 [Duty_Offset_Calibration]
623 09:54:40.630307
624 09:54:40.630379 ===========================
625 09:54:40.630451 B0:1 B1:1 CA:1
626 09:54:40.630523 ==
627 09:54:40.630595 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
628 09:54:40.630677 fsp= 1, odt_onoff= 1, Byte mode= 0
629 09:54:40.630752 ==
630 09:54:40.630825 [Duty_Offset_Calibration]
631 09:54:40.630896
632 09:54:40.630968 ===========================
633 09:54:40.631040 B0:1 B1:0 CA:2
634 09:54:40.631113 [ModeRegInit_LP4] CH0 RK0
635 09:54:40.631185 Write Rank0 MR13 =0x18
636 09:54:40.631257 Write Rank0 MR12 =0x5d
637 09:54:40.631329 Write Rank0 MR1 =0x56
638 09:54:40.631401 Write Rank0 MR2 =0x1a
639 09:54:40.631482 Write Rank0 MR11 =0x0
640 09:54:40.631554 Write Rank0 MR22 =0x38
641 09:54:40.631627 Write Rank0 MR14 =0x5d
642 09:54:40.631698 Write Rank0 MR3 =0x30
643 09:54:40.631770 Write Rank0 MR13 =0x58
644 09:54:40.631841 Write Rank0 MR12 =0x5d
645 09:54:40.631912 Write Rank0 MR1 =0x56
646 09:54:40.631984 Write Rank0 MR2 =0x2d
647 09:54:40.632055 Write Rank0 MR11 =0x23
648 09:54:40.632126 Write Rank0 MR22 =0x34
649 09:54:40.632198 Write Rank0 MR14 =0x10
650 09:54:40.632269 Write Rank0 MR3 =0x30
651 09:54:40.632340 Write Rank0 MR13 =0xd8
652 09:54:40.632411 [ModeRegInit_LP4] CH0 RK1
653 09:54:40.632483 Write Rank1 MR13 =0x18
654 09:54:40.632556 Write Rank1 MR12 =0x5d
655 09:54:40.632627 Write Rank1 MR1 =0x56
656 09:54:40.632706 Write Rank1 MR2 =0x1a
657 09:54:40.632770 Write Rank1 MR11 =0x0
658 09:54:40.632834 Write Rank1 MR22 =0x38
659 09:54:40.632897 Write Rank1 MR14 =0x5d
660 09:54:40.632961 Write Rank1 MR3 =0x30
661 09:54:40.633025 Write Rank1 MR13 =0x58
662 09:54:40.633088 Write Rank1 MR12 =0x5d
663 09:54:40.633151 Write Rank1 MR1 =0x56
664 09:54:40.633215 Write Rank1 MR2 =0x2d
665 09:54:40.633280 Write Rank1 MR11 =0x23
666 09:54:40.633343 Write Rank1 MR22 =0x34
667 09:54:40.633407 Write Rank1 MR14 =0x10
668 09:54:40.633470 Write Rank1 MR3 =0x30
669 09:54:40.633534 Write Rank1 MR13 =0xd8
670 09:54:40.633598 [ModeRegInit_LP4] CH1 RK0
671 09:54:40.633661 Write Rank0 MR13 =0x18
672 09:54:40.633725 Write Rank0 MR12 =0x5d
673 09:54:40.633789 Write Rank0 MR1 =0x56
674 09:54:40.633853 Write Rank0 MR2 =0x1a
675 09:54:40.633924 Write Rank0 MR11 =0x0
676 09:54:40.633999 Write Rank0 MR22 =0x38
677 09:54:40.634063 Write Rank0 MR14 =0x5d
678 09:54:40.634128 Write Rank0 MR3 =0x30
679 09:54:40.634192 Write Rank0 MR13 =0x58
680 09:54:40.634256 Write Rank0 MR12 =0x5d
681 09:54:40.634319 Write Rank0 MR1 =0x56
682 09:54:40.634383 Write Rank0 MR2 =0x2d
683 09:54:40.634446 Write Rank0 MR11 =0x23
684 09:54:40.634509 Write Rank0 MR22 =0x34
685 09:54:40.634573 Write Rank0 MR14 =0x10
686 09:54:40.634637 Write Rank0 MR3 =0x30
687 09:54:40.634701 Write Rank0 MR13 =0xd8
688 09:54:40.634764 [ModeRegInit_LP4] CH1 RK1
689 09:54:40.634828 Write Rank1 MR13 =0x18
690 09:54:40.634891 Write Rank1 MR12 =0x5d
691 09:54:40.634954 Write Rank1 MR1 =0x56
692 09:54:40.635017 Write Rank1 MR2 =0x1a
693 09:54:40.635081 Write Rank1 MR11 =0x0
694 09:54:40.635145 Write Rank1 MR22 =0x38
695 09:54:40.635209 Write Rank1 MR14 =0x5d
696 09:54:40.635273 Write Rank1 MR3 =0x30
697 09:54:40.635337 Write Rank1 MR13 =0x58
698 09:54:40.635400 Write Rank1 MR12 =0x5d
699 09:54:40.635491 Write Rank1 MR1 =0x56
700 09:54:40.635556 Write Rank1 MR2 =0x2d
701 09:54:40.635620 Write Rank1 MR11 =0x23
702 09:54:40.635683 Write Rank1 MR22 =0x34
703 09:54:40.635748 Write Rank1 MR14 =0x10
704 09:54:40.635811 Write Rank1 MR3 =0x30
705 09:54:40.635875 Write Rank1 MR13 =0xd8
706 09:54:40.635939 match AC timing 3
707 09:54:40.636004 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
708 09:54:40.636069 DramC Write-DBI off
709 09:54:40.636134 DramC Read-DBI off
710 09:54:40.636197 Write Rank0 MR13 =0x59
711 09:54:40.636261 ==
712 09:54:40.636325 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
713 09:54:40.636389 fsp= 1, odt_onoff= 1, Byte mode= 0
714 09:54:40.636454 ==
715 09:54:40.636518 === u2Vref_new: 0x56 --> 0x2d
716 09:54:40.636583 === u2Vref_new: 0x58 --> 0x38
717 09:54:40.636647 === u2Vref_new: 0x5a --> 0x39
718 09:54:40.636711 === u2Vref_new: 0x5c --> 0x3c
719 09:54:40.636775 === u2Vref_new: 0x5e --> 0x3d
720 09:54:40.636839 === u2Vref_new: 0x60 --> 0xa0
721 09:54:40.636903 [CA 0] Center 34 (6~63) winsize 58
722 09:54:40.636968 [CA 1] Center 36 (9~63) winsize 55
723 09:54:40.637033 [CA 2] Center 29 (0~58) winsize 59
724 09:54:40.637097 [CA 3] Center 24 (-3~52) winsize 56
725 09:54:40.637161 [CA 4] Center 25 (-3~53) winsize 57
726 09:54:40.637237 [CA 5] Center 30 (0~60) winsize 61
727 09:54:40.637308
728 09:54:40.637372 [CATrainingPosCal] consider 1 rank data
729 09:54:40.637437 u2DelayCellTimex100 = 735/100 ps
730 09:54:40.637502 CA0 delay=34 (6~63),Diff = 10 PI (13 cell)
731 09:54:40.637567 CA1 delay=36 (9~63),Diff = 12 PI (15 cell)
732 09:54:40.637632 CA2 delay=29 (0~58),Diff = 5 PI (6 cell)
733 09:54:40.637709 CA3 delay=24 (-3~52),Diff = 0 PI (0 cell)
734 09:54:40.637780 CA4 delay=25 (-3~53),Diff = 1 PI (1 cell)
735 09:54:40.637844 CA5 delay=30 (0~60),Diff = 6 PI (7 cell)
736 09:54:40.637902
737 09:54:40.637960 CA PerBit enable=1, Macro0, CA PI delay=24
738 09:54:40.638018 === u2Vref_new: 0x5e --> 0x3d
739 09:54:40.638076
740 09:54:40.638134 Vref(ca) range 1: 30
741 09:54:40.638192
742 09:54:40.638249 CS Dly= 9 (40-0-32)
743 09:54:40.638307 Write Rank0 MR13 =0xd8
744 09:54:40.638365 Write Rank0 MR13 =0xd8
745 09:54:40.638423 Write Rank0 MR12 =0x5e
746 09:54:40.638480 Write Rank1 MR13 =0x59
747 09:54:40.638538 ==
748 09:54:40.638596 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
749 09:54:40.638861 fsp= 1, odt_onoff= 1, Byte mode= 0
750 09:54:40.638926 ==
751 09:54:40.638986 === u2Vref_new: 0x56 --> 0x2d
752 09:54:40.639045 === u2Vref_new: 0x58 --> 0x38
753 09:54:40.639103 === u2Vref_new: 0x5a --> 0x39
754 09:54:40.639161 === u2Vref_new: 0x5c --> 0x3c
755 09:54:40.639220 === u2Vref_new: 0x5e --> 0x3d
756 09:54:40.639278 === u2Vref_new: 0x60 --> 0xa0
757 09:54:40.639336 [CA 0] Center 36 (10~63) winsize 54
758 09:54:40.639395 [CA 1] Center 36 (9~63) winsize 55
759 09:54:40.639463 [CA 2] Center 31 (2~60) winsize 59
760 09:54:40.639522 [CA 3] Center 25 (-3~53) winsize 57
761 09:54:40.639580 [CA 4] Center 25 (-3~54) winsize 58
762 09:54:40.639638 [CA 5] Center 31 (2~61) winsize 60
763 09:54:40.639696
764 09:54:40.639754 [CATrainingPosCal] consider 2 rank data
765 09:54:40.639812 u2DelayCellTimex100 = 735/100 ps
766 09:54:40.639870 CA0 delay=36 (10~63),Diff = 12 PI (15 cell)
767 09:54:40.639929 CA1 delay=36 (9~63),Diff = 12 PI (15 cell)
768 09:54:40.639987 CA2 delay=30 (2~58),Diff = 6 PI (7 cell)
769 09:54:40.640045 CA3 delay=24 (-3~52),Diff = 0 PI (0 cell)
770 09:54:40.640119 CA4 delay=25 (-3~53),Diff = 1 PI (1 cell)
771 09:54:40.640180 CA5 delay=31 (2~60),Diff = 7 PI (9 cell)
772 09:54:40.640238
773 09:54:40.640297 CA PerBit enable=1, Macro0, CA PI delay=24
774 09:54:40.640355 === u2Vref_new: 0x5a --> 0x39
775 09:54:40.640413
776 09:54:40.640471 Vref(ca) range 1: 26
777 09:54:40.640529
778 09:54:40.640597 CS Dly= 7 (38-0-32)
779 09:54:40.640655 Write Rank1 MR13 =0xd8
780 09:54:40.640714 Write Rank1 MR13 =0xd8
781 09:54:40.640772 Write Rank1 MR12 =0x5a
782 09:54:40.640830 [RankSwap] Rank num 2, (Multi 1), Rank 0
783 09:54:40.640888 Write Rank0 MR2 =0xad
784 09:54:40.640946 [Write Leveling]
785 09:54:40.641004 delay byte0 byte1 byte2 byte3
786 09:54:40.641061
787 09:54:40.641119 10 0 0
788 09:54:40.641178 11 0 0
789 09:54:40.641237 12 0 0
790 09:54:40.641296 13 0 0
791 09:54:40.641354 14 0 0
792 09:54:40.641412 15 0 0
793 09:54:40.641471 16 0 0
794 09:54:40.641529 17 0 0
795 09:54:40.641588 18 0 0
796 09:54:40.641648 19 0 0
797 09:54:40.641706 20 0 0
798 09:54:40.641765 21 0 0
799 09:54:40.641824 22 0 0
800 09:54:40.641882 23 0 0
801 09:54:40.641940 24 0 ff
802 09:54:40.641999 25 0 ff
803 09:54:40.642058 26 0 ff
804 09:54:40.642116 27 0 ff
805 09:54:40.642174 28 0 ff
806 09:54:40.642232 29 0 ff
807 09:54:40.642291 30 0 ff
808 09:54:40.642349 31 0 ff
809 09:54:40.642407 32 0 ff
810 09:54:40.642465 33 ff ff
811 09:54:40.642523 34 ff ff
812 09:54:40.642582 35 ff ff
813 09:54:40.642640 36 ff ff
814 09:54:40.642698 37 ff ff
815 09:54:40.642757 38 ff ff
816 09:54:40.642816 39 ff ff
817 09:54:40.642875 pass bytecount = 0xff (0xff: all bytes pass)
818 09:54:40.642932
819 09:54:40.642990 DQS0 dly: 33
820 09:54:40.643047 DQS1 dly: 24
821 09:54:40.643105 Write Rank0 MR2 =0x2d
822 09:54:40.643162 [RankSwap] Rank num 2, (Multi 1), Rank 0
823 09:54:40.643220 Write Rank0 MR1 =0xd6
824 09:54:40.643277 [Gating]
825 09:54:40.643335 ==
826 09:54:40.643392 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
827 09:54:40.643456 fsp= 1, odt_onoff= 1, Byte mode= 0
828 09:54:40.643515 ==
829 09:54:40.643572 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
830 09:54:40.643632 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
831 09:54:40.643691 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
832 09:54:40.643750 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
833 09:54:40.643810 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
834 09:54:40.643879 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
835 09:54:40.643939 3 1 24 |2c2b 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
836 09:54:40.643998 3 1 28 |504 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
837 09:54:40.644057 3 2 0 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
838 09:54:40.644116 3 2 4 |3534 c0c |(11 11)(11 11) |(0 0)(1 1)| 0
839 09:54:40.644175 3 2 8 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
840 09:54:40.644233 3 2 12 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
841 09:54:40.644292 3 2 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
842 09:54:40.644350 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
843 09:54:40.644409 3 2 24 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
844 09:54:40.644468 3 2 28 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
845 09:54:40.644528 3 3 0 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
846 09:54:40.644586 3 3 4 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
847 09:54:40.644645 3 3 8 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
848 09:54:40.644704 [Byte 1] Lead/lag falling Transition (3, 3, 8)
849 09:54:40.644771 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
850 09:54:40.644843 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
851 09:54:40.644904 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
852 09:54:40.644963 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
853 09:54:40.645022 3 3 28 |403 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
854 09:54:40.645081 3 4 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
855 09:54:40.645140 3 4 4 |3d3d 706 |(11 11)(11 11) |(1 1)(1 1)| 0
856 09:54:40.645199 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
857 09:54:40.645273 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
858 09:54:40.645334 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
859 09:54:40.645394 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
860 09:54:40.645453 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
861 09:54:40.645512 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
862 09:54:40.645571 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
863 09:54:40.645630 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
864 09:54:40.645689 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
865 09:54:40.645749 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
866 09:54:40.645808 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
867 09:54:40.645866 [Byte 0] Lead/lag falling Transition (3, 5, 16)
868 09:54:40.645925 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
869 09:54:40.645984 [Byte 0] Lead/lag Transition tap number (2)
870 09:54:40.646041 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
871 09:54:40.646100 [Byte 1] Lead/lag falling Transition (3, 5, 24)
872 09:54:40.646158 3 5 28 |2424 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
873 09:54:40.646413 3 6 0 |4646 3d3d |(0 0)(11 11) |(0 0)(1 0)| 0
874 09:54:40.646479 [Byte 0]First pass (3, 6, 0)
875 09:54:40.646539 [Byte 1] Lead/lag Transition tap number (3)
876 09:54:40.646597 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
877 09:54:40.646657 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
878 09:54:40.646716 [Byte 1]First pass (3, 6, 8)
879 09:54:40.646774 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
880 09:54:40.646833 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
881 09:54:40.646892 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
882 09:54:40.646951 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
883 09:54:40.647011 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
884 09:54:40.647070 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
885 09:54:40.647129 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
886 09:54:40.647188 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
887 09:54:40.647258 All bytes gating window > 1UI, Early break!
888 09:54:40.647316
889 09:54:40.647373 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 20)
890 09:54:40.647454
891 09:54:40.647513 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 30)
892 09:54:40.647571
893 09:54:40.647629
894 09:54:40.647686
895 09:54:40.647743 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 20)
896 09:54:40.647801
897 09:54:40.647859 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
898 09:54:40.647917
899 09:54:40.647973
900 09:54:40.648031 Write Rank0 MR1 =0x56
901 09:54:40.648088
902 09:54:40.648146 best RODT dly(2T, 0.5T) = (2, 2)
903 09:54:40.648204
904 09:54:40.648261 best RODT dly(2T, 0.5T) = (2, 2)
905 09:54:40.648318 ==
906 09:54:40.648376 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
907 09:54:40.648435 fsp= 1, odt_onoff= 1, Byte mode= 0
908 09:54:40.648493 ==
909 09:54:40.648551 Start DQ dly to find pass range UseTestEngine =0
910 09:54:40.648609 x-axis: bit #, y-axis: DQ dly (-127~63)
911 09:54:40.648667 RX Vref Scan = 0
912 09:54:40.648724 -26, [0] xxxxxxxx xxxxxxxx [MSB]
913 09:54:40.648784 -25, [0] xxxxxxxx xxxxxxxx [MSB]
914 09:54:40.648843 -24, [0] xxxxxxxx xxxxxxxx [MSB]
915 09:54:40.648902 -23, [0] xxxxxxxx xxxxxxxx [MSB]
916 09:54:40.648961 -22, [0] xxxxxxxx xxxxxxxx [MSB]
917 09:54:40.649020 -21, [0] xxxxxxxx xxxxxxxx [MSB]
918 09:54:40.649079 -20, [0] xxxxxxxx xxxxxxxx [MSB]
919 09:54:40.649138 -19, [0] xxxxxxxx xxxxxxxx [MSB]
920 09:54:40.649196 -18, [0] xxxxxxxx xxxxxxxx [MSB]
921 09:54:40.649255 -17, [0] xxxxxxxx xxxxxxxx [MSB]
922 09:54:40.649314 -16, [0] xxxxxxxx xxxxxxxx [MSB]
923 09:54:40.649373 -15, [0] xxxxxxxx xxxxxxxx [MSB]
924 09:54:40.649432 -14, [0] xxxxxxxx xxxxxxxx [MSB]
925 09:54:40.649491 -13, [0] xxxxxxxx xxxxxxxx [MSB]
926 09:54:40.649550 -12, [0] xxxxxxxx xxxxxxxx [MSB]
927 09:54:40.649609 -11, [0] xxxxxxxx xxxxxxxx [MSB]
928 09:54:40.649667 -10, [0] xxxxxxxx xxxxxxxx [MSB]
929 09:54:40.649725 -9, [0] xxxxxxxx xxxxxxxx [MSB]
930 09:54:40.649784 -8, [0] xxxxxxxx xxxxxxxx [MSB]
931 09:54:40.649843 -7, [0] xxxxxxxx xxxxxxxx [MSB]
932 09:54:40.649901 -6, [0] xxxxxxxx xxxxxxxx [MSB]
933 09:54:40.649960 -5, [0] xxxxxxxx xxxxxxxx [MSB]
934 09:54:40.650018 -4, [0] xxxxxxxx xxxxxxxx [MSB]
935 09:54:40.650077 -3, [0] xxxxxxxx xxxxxxxx [MSB]
936 09:54:40.650135 -2, [0] xxxoxxxx oxxxxxxx [MSB]
937 09:54:40.650194 -1, [0] xxxoxxxx ooxoxxxx [MSB]
938 09:54:40.650252 0, [0] xxxoxoxx ooxoxxxx [MSB]
939 09:54:40.650311 1, [0] xxxoxoox ooxoxoxx [MSB]
940 09:54:40.650370 2, [0] xxxoxoox ooxoooxx [MSB]
941 09:54:40.650429 3, [0] xxxoxoox ooxoooxx [MSB]
942 09:54:40.650487 4, [0] xxxoxooo ooxoooox [MSB]
943 09:54:40.650560 5, [0] xooooooo ooxooooo [MSB]
944 09:54:40.650620 6, [0] xooooooo ooxooooo [MSB]
945 09:54:40.650678 7, [0] oooooooo ooxooooo [MSB]
946 09:54:40.650737 32, [0] oooxoooo oooooooo [MSB]
947 09:54:40.650796 33, [0] oooxoooo xooooooo [MSB]
948 09:54:40.650855 34, [0] oooxoooo xooooooo [MSB]
949 09:54:40.650913 35, [0] oooxoooo xooooooo [MSB]
950 09:54:40.650973 36, [0] oooxoxox xooxoooo [MSB]
951 09:54:40.651031 37, [0] oooxoxxx xxoxoooo [MSB]
952 09:54:40.651089 38, [0] oooxoxxx xxoxxoxo [MSB]
953 09:54:40.651147 39, [0] oooxxxxx xxoxxxxo [MSB]
954 09:54:40.651205 40, [0] xooxxxxx xxoxxxxo [MSB]
955 09:54:40.651263 41, [0] xxoxxxxx xxoxxxxo [MSB]
956 09:54:40.651321 42, [0] xxxxxxxx xxoxxxxx [MSB]
957 09:54:40.651380 43, [0] xxxxxxxx xxoxxxxx [MSB]
958 09:54:40.651446 44, [0] xxxxxxxx xxxxxxxx [MSB]
959 09:54:40.651505 iDelay=44, Bit 0, Center 23 (7 ~ 39) 33
960 09:54:40.651563 iDelay=44, Bit 1, Center 22 (5 ~ 40) 36
961 09:54:40.651620 iDelay=44, Bit 2, Center 23 (5 ~ 41) 37
962 09:54:40.651678 iDelay=44, Bit 3, Center 14 (-2 ~ 31) 34
963 09:54:40.651735 iDelay=44, Bit 4, Center 21 (5 ~ 38) 34
964 09:54:40.651792 iDelay=44, Bit 5, Center 17 (0 ~ 35) 36
965 09:54:40.651849 iDelay=44, Bit 6, Center 18 (1 ~ 36) 36
966 09:54:40.651906 iDelay=44, Bit 7, Center 19 (4 ~ 35) 32
967 09:54:40.651964 iDelay=44, Bit 8, Center 15 (-2 ~ 32) 35
968 09:54:40.652022 iDelay=44, Bit 9, Center 17 (-1 ~ 36) 38
969 09:54:40.652080 iDelay=44, Bit 10, Center 25 (8 ~ 43) 36
970 09:54:40.652137 iDelay=44, Bit 11, Center 17 (-1 ~ 35) 37
971 09:54:40.652195 iDelay=44, Bit 12, Center 19 (2 ~ 37) 36
972 09:54:40.652253 iDelay=44, Bit 13, Center 19 (1 ~ 38) 38
973 09:54:40.652310 iDelay=44, Bit 14, Center 20 (4 ~ 37) 34
974 09:54:40.652368 iDelay=44, Bit 15, Center 23 (5 ~ 41) 37
975 09:54:40.652425 ==
976 09:54:40.652483 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
977 09:54:40.652541 fsp= 1, odt_onoff= 1, Byte mode= 0
978 09:54:40.652598 ==
979 09:54:40.652656 DQS Delay:
980 09:54:40.652713 DQS0 = 0, DQS1 = 0
981 09:54:40.652771 DQM Delay:
982 09:54:40.652828 DQM0 = 19, DQM1 = 19
983 09:54:40.652885 DQ Delay:
984 09:54:40.652943 DQ0 =23, DQ1 =22, DQ2 =23, DQ3 =14
985 09:54:40.653001 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =19
986 09:54:40.653058 DQ8 =15, DQ9 =17, DQ10 =25, DQ11 =17
987 09:54:40.653116 DQ12 =19, DQ13 =19, DQ14 =20, DQ15 =23
988 09:54:40.653174
989 09:54:40.653231
990 09:54:40.653287 DramC Write-DBI off
991 09:54:40.653345 ==
992 09:54:40.653402 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
993 09:54:40.653461 fsp= 1, odt_onoff= 1, Byte mode= 0
994 09:54:40.653519 ==
995 09:54:40.653576 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
996 09:54:40.653634
997 09:54:40.653691 Begin, DQ Scan Range 920~1176
998 09:54:40.653749
999 09:54:40.653806
1000 09:54:40.653862 TX Vref Scan disable
1001 09:54:40.653920 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1002 09:54:40.653989 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1003 09:54:40.654049 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1004 09:54:40.654108 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1005 09:54:40.654365 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1006 09:54:40.654434 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1007 09:54:40.654494 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1008 09:54:40.654553 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1009 09:54:40.654613 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1010 09:54:40.654672 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1011 09:54:40.654731 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1012 09:54:40.654789 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1013 09:54:40.654849 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1014 09:54:40.654908 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1015 09:54:40.654966 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1016 09:54:40.655025 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1017 09:54:40.655085 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1018 09:54:40.655146 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1019 09:54:40.655205 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1020 09:54:40.655265 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1021 09:54:40.655323 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1022 09:54:40.655382 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1023 09:54:40.655451 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1024 09:54:40.655511 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1025 09:54:40.655578 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1026 09:54:40.655640 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1027 09:54:40.655701 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1028 09:54:40.655761 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1029 09:54:40.655820 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1030 09:54:40.655879 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1031 09:54:40.655938 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1032 09:54:40.655997 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1033 09:54:40.656056 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1034 09:54:40.656115 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1035 09:54:40.656173 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1036 09:54:40.656231 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1037 09:54:40.656290 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1038 09:54:40.656349 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1039 09:54:40.656407 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1040 09:54:40.656466 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1041 09:54:40.656524 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1042 09:54:40.656583 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1043 09:54:40.656642 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1044 09:54:40.656700 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1045 09:54:40.656758 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1046 09:54:40.656817 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1047 09:54:40.656876 966 |3 6 6|[0] xxxxxxxx oxxxxxxx [MSB]
1048 09:54:40.656935 967 |3 6 7|[0] xxxxxxxx oxxoxxxx [MSB]
1049 09:54:40.656993 968 |3 6 8|[0] xxxxxxxx ooxoooox [MSB]
1050 09:54:40.657052 969 |3 6 9|[0] xxxxxxxx ooxoooox [MSB]
1051 09:54:40.657110 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1052 09:54:40.657171 971 |3 6 11|[0] xxxxxxxx ooxooooo [MSB]
1053 09:54:40.657241 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
1054 09:54:40.657299 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
1055 09:54:40.657358 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
1056 09:54:40.657417 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
1057 09:54:40.657476 976 |3 6 16|[0] xxxoxoox oooooooo [MSB]
1058 09:54:40.657534 977 |3 6 17|[0] xooooooo oooooooo [MSB]
1059 09:54:40.657592 985 |3 6 25|[0] oooooooo xooooooo [MSB]
1060 09:54:40.657670 986 |3 6 26|[0] oooooooo xooxoooo [MSB]
1061 09:54:40.657730 987 |3 6 27|[0] oooooooo xooxoooo [MSB]
1062 09:54:40.657790 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1063 09:54:40.657849 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1064 09:54:40.657907 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1065 09:54:40.657965 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
1066 09:54:40.658024 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
1067 09:54:40.658083 993 |3 6 33|[0] oooxoooo xxxxxxxx [MSB]
1068 09:54:40.658141 994 |3 6 34|[0] oooxoooo xxxxxxxx [MSB]
1069 09:54:40.658200 995 |3 6 35|[0] oooxoooo xxxxxxxx [MSB]
1070 09:54:40.658258 996 |3 6 36|[0] oooxoxoo xxxxxxxx [MSB]
1071 09:54:40.658316 997 |3 6 37|[0] oooxoxxo xxxxxxxx [MSB]
1072 09:54:40.658375 998 |3 6 38|[0] oxoxxxxx xxxxxxxx [MSB]
1073 09:54:40.658433 999 |3 6 39|[0] oxoxxxxx xxxxxxxx [MSB]
1074 09:54:40.658492 1000 |3 6 40|[0] xxxxxxxx xxxxxxxx [MSB]
1075 09:54:40.658550 Byte0, DQ PI dly=986, DQM PI dly= 986
1076 09:54:40.658609 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 26)
1077 09:54:40.658667
1078 09:54:40.658724 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 26)
1079 09:54:40.658782
1080 09:54:40.658840 Byte1, DQ PI dly=977, DQM PI dly= 977
1081 09:54:40.658897 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
1082 09:54:40.658956
1083 09:54:40.659013 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
1084 09:54:40.659071
1085 09:54:40.659128 ==
1086 09:54:40.659184 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1087 09:54:40.659242 fsp= 1, odt_onoff= 1, Byte mode= 0
1088 09:54:40.659300 ==
1089 09:54:40.659357 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1090 09:54:40.659424
1091 09:54:40.659484 Begin, DQ Scan Range 953~1017
1092 09:54:40.659541 Write Rank0 MR14 =0x0
1093 09:54:40.659598
1094 09:54:40.659654 CH=0, VrefRange= 0, VrefLevel = 0
1095 09:54:40.659713 TX Bit0 (980~994) 15 987, Bit8 (967~978) 12 972,
1096 09:54:40.659771 TX Bit1 (978~993) 16 985, Bit9 (969~983) 15 976,
1097 09:54:40.659830 TX Bit2 (980~994) 15 987, Bit10 (975~987) 13 981,
1098 09:54:40.659888 TX Bit3 (976~987) 12 981, Bit11 (968~982) 15 975,
1099 09:54:40.659945 TX Bit4 (979~992) 14 985, Bit12 (971~983) 13 977,
1100 09:54:40.660002 TX Bit5 (977~991) 15 984, Bit13 (970~984) 15 977,
1101 09:54:40.660061 TX Bit6 (978~991) 14 984, Bit14 (969~984) 16 976,
1102 09:54:40.660119 TX Bit7 (979~992) 14 985, Bit15 (974~986) 13 980,
1103 09:54:40.660176
1104 09:54:40.660233 Write Rank0 MR14 =0x2
1105 09:54:40.660290
1106 09:54:40.660347 CH=0, VrefRange= 0, VrefLevel = 2
1107 09:54:40.660405 TX Bit0 (980~995) 16 987, Bit8 (967~979) 13 973,
1108 09:54:40.660463 TX Bit1 (978~993) 16 985, Bit9 (969~984) 16 976,
1109 09:54:40.660531 TX Bit2 (980~995) 16 987, Bit10 (975~988) 14 981,
1110 09:54:40.660591 TX Bit3 (976~988) 13 982, Bit11 (968~982) 15 975,
1111 09:54:40.660845 TX Bit4 (978~993) 16 985, Bit12 (970~984) 15 977,
1112 09:54:40.660911 TX Bit5 (977~992) 16 984, Bit13 (969~984) 16 976,
1113 09:54:40.660972 TX Bit6 (977~992) 16 984, Bit14 (969~985) 17 977,
1114 09:54:40.661030 TX Bit7 (979~993) 15 986, Bit15 (974~987) 14 980,
1115 09:54:40.661088
1116 09:54:40.661145 Write Rank0 MR14 =0x4
1117 09:54:40.661203
1118 09:54:40.661259 CH=0, VrefRange= 0, VrefLevel = 4
1119 09:54:40.661317 TX Bit0 (979~995) 17 987, Bit8 (967~981) 15 974,
1120 09:54:40.661375 TX Bit1 (978~994) 17 986, Bit9 (968~984) 17 976,
1121 09:54:40.661433 TX Bit2 (979~995) 17 987, Bit10 (974~989) 16 981,
1122 09:54:40.661491 TX Bit3 (975~989) 15 982, Bit11 (968~983) 16 975,
1123 09:54:40.661549 TX Bit4 (978~993) 16 985, Bit12 (969~984) 16 976,
1124 09:54:40.661607 TX Bit5 (976~992) 17 984, Bit13 (969~985) 17 977,
1125 09:54:40.661665 TX Bit6 (977~992) 16 984, Bit14 (969~985) 17 977,
1126 09:54:40.661722 TX Bit7 (979~993) 15 986, Bit15 (974~987) 14 980,
1127 09:54:40.661780
1128 09:54:40.661837 Write Rank0 MR14 =0x6
1129 09:54:40.661894
1130 09:54:40.661951 CH=0, VrefRange= 0, VrefLevel = 6
1131 09:54:40.662009 TX Bit0 (979~997) 19 988, Bit8 (967~981) 15 974,
1132 09:54:40.662067 TX Bit1 (978~995) 18 986, Bit9 (968~985) 18 976,
1133 09:54:40.662125 TX Bit2 (979~996) 18 987, Bit10 (974~990) 17 982,
1134 09:54:40.662182 TX Bit3 (974~990) 17 982, Bit11 (968~983) 16 975,
1135 09:54:40.662240 TX Bit4 (978~994) 17 986, Bit12 (969~985) 17 977,
1136 09:54:40.662298 TX Bit5 (976~993) 18 984, Bit13 (969~985) 17 977,
1137 09:54:40.662359 TX Bit6 (977~993) 17 985, Bit14 (969~986) 18 977,
1138 09:54:40.662421 TX Bit7 (978~994) 17 986, Bit15 (974~989) 16 981,
1139 09:54:40.662482
1140 09:54:40.662540 Write Rank0 MR14 =0x8
1141 09:54:40.662597
1142 09:54:40.662653 CH=0, VrefRange= 0, VrefLevel = 8
1143 09:54:40.662711 TX Bit0 (979~998) 20 988, Bit8 (967~982) 16 974,
1144 09:54:40.662769 TX Bit1 (978~995) 18 986, Bit9 (968~985) 18 976,
1145 09:54:40.662830 TX Bit2 (979~998) 20 988, Bit10 (973~990) 18 981,
1146 09:54:40.662891 TX Bit3 (974~991) 18 982, Bit11 (967~984) 18 975,
1147 09:54:40.662950 TX Bit4 (978~994) 17 986, Bit12 (969~985) 17 977,
1148 09:54:40.663008 TX Bit5 (976~993) 18 984, Bit13 (969~985) 17 977,
1149 09:54:40.663065 TX Bit6 (977~993) 17 985, Bit14 (968~987) 20 977,
1150 09:54:40.663123 TX Bit7 (978~994) 17 986, Bit15 (973~990) 18 981,
1151 09:54:40.663181
1152 09:54:40.663238 Write Rank0 MR14 =0xa
1153 09:54:40.663296
1154 09:54:40.663353 CH=0, VrefRange= 0, VrefLevel = 10
1155 09:54:40.663419 TX Bit0 (978~998) 21 988, Bit8 (966~982) 17 974,
1156 09:54:40.663480 TX Bit1 (977~996) 20 986, Bit9 (968~986) 19 977,
1157 09:54:40.663538 TX Bit2 (978~998) 21 988, Bit10 (972~990) 19 981,
1158 09:54:40.663596 TX Bit3 (974~991) 18 982, Bit11 (967~984) 18 975,
1159 09:54:40.663654 TX Bit4 (977~995) 19 986, Bit12 (969~986) 18 977,
1160 09:54:40.663711 TX Bit5 (976~994) 19 985, Bit13 (969~986) 18 977,
1161 09:54:40.663769 TX Bit6 (977~994) 18 985, Bit14 (968~987) 20 977,
1162 09:54:40.663826 TX Bit7 (978~994) 17 986, Bit15 (973~990) 18 981,
1163 09:54:40.663883
1164 09:54:40.663940 Write Rank0 MR14 =0xc
1165 09:54:40.663998
1166 09:54:40.664054 CH=0, VrefRange= 0, VrefLevel = 12
1167 09:54:40.664112 TX Bit0 (978~999) 22 988, Bit8 (966~983) 18 974,
1168 09:54:40.664170 TX Bit1 (977~997) 21 987, Bit9 (968~986) 19 977,
1169 09:54:40.664228 TX Bit2 (978~999) 22 988, Bit10 (973~991) 19 982,
1170 09:54:40.664286 TX Bit3 (973~991) 19 982, Bit11 (967~985) 19 976,
1171 09:54:40.664343 TX Bit4 (977~996) 20 986, Bit12 (969~986) 18 977,
1172 09:54:40.664401 TX Bit5 (975~994) 20 984, Bit13 (968~986) 19 977,
1173 09:54:40.664470 TX Bit6 (976~994) 19 985, Bit14 (968~988) 21 978,
1174 09:54:40.664529 TX Bit7 (978~996) 19 987, Bit15 (972~990) 19 981,
1175 09:54:40.664586
1176 09:54:40.664643 Write Rank0 MR14 =0xe
1177 09:54:40.664700
1178 09:54:40.664757 CH=0, VrefRange= 0, VrefLevel = 14
1179 09:54:40.664814 TX Bit0 (978~999) 22 988, Bit8 (966~984) 19 975,
1180 09:54:40.664872 TX Bit1 (977~998) 22 987, Bit9 (968~987) 20 977,
1181 09:54:40.664930 TX Bit2 (978~998) 21 988, Bit10 (971~991) 21 981,
1182 09:54:40.664989 TX Bit3 (973~992) 20 982, Bit11 (967~985) 19 976,
1183 09:54:40.665046 TX Bit4 (977~997) 21 987, Bit12 (968~987) 20 977,
1184 09:54:40.665104 TX Bit5 (975~994) 20 984, Bit13 (968~987) 20 977,
1185 09:54:40.665162 TX Bit6 (976~995) 20 985, Bit14 (968~989) 22 978,
1186 09:54:40.665220 TX Bit7 (977~996) 20 986, Bit15 (971~990) 20 980,
1187 09:54:40.665278
1188 09:54:40.665335 Write Rank0 MR14 =0x10
1189 09:54:40.665391
1190 09:54:40.665449 CH=0, VrefRange= 0, VrefLevel = 16
1191 09:54:40.665506 TX Bit0 (978~999) 22 988, Bit8 (965~984) 20 974,
1192 09:54:40.665564 TX Bit1 (977~998) 22 987, Bit9 (967~988) 22 977,
1193 09:54:40.665622 TX Bit2 (977~999) 23 988, Bit10 (972~992) 21 982,
1194 09:54:40.665685 TX Bit3 (973~992) 20 982, Bit11 (967~986) 20 976,
1195 09:54:40.665750 TX Bit4 (977~997) 21 987, Bit12 (968~988) 21 978,
1196 09:54:40.665808 TX Bit5 (975~994) 20 984, Bit13 (968~988) 21 978,
1197 09:54:40.665866 TX Bit6 (976~995) 20 985, Bit14 (968~989) 22 978,
1198 09:54:40.665927 TX Bit7 (977~997) 21 987, Bit15 (971~991) 21 981,
1199 09:54:40.665984
1200 09:54:40.666041 Write Rank0 MR14 =0x12
1201 09:54:40.666098
1202 09:54:40.666155 CH=0, VrefRange= 0, VrefLevel = 18
1203 09:54:40.666212 TX Bit0 (977~999) 23 988, Bit8 (965~985) 21 975,
1204 09:54:40.666270 TX Bit1 (977~999) 23 988, Bit9 (967~988) 22 977,
1205 09:54:40.666328 TX Bit2 (977~999) 23 988, Bit10 (971~992) 22 981,
1206 09:54:40.666386 TX Bit3 (972~993) 22 982, Bit11 (966~986) 21 976,
1207 09:54:40.666443 TX Bit4 (977~998) 22 987, Bit12 (968~989) 22 978,
1208 09:54:40.666500 TX Bit5 (975~996) 22 985, Bit13 (968~989) 22 978,
1209 09:54:40.666558 TX Bit6 (976~996) 21 986, Bit14 (968~990) 23 979,
1210 09:54:40.666615 TX Bit7 (977~997) 21 987, Bit15 (971~991) 21 981,
1211 09:54:40.666673
1212 09:54:40.666925 Write Rank0 MR14 =0x14
1213 09:54:40.666989
1214 09:54:40.667048 CH=0, VrefRange= 0, VrefLevel = 20
1215 09:54:40.667105 TX Bit0 (977~1000) 24 988, Bit8 (965~985) 21 975,
1216 09:54:40.667163 TX Bit1 (977~999) 23 988, Bit9 (967~989) 23 978,
1217 09:54:40.667222 TX Bit2 (977~1000) 24 988, Bit10 (971~992) 22 981,
1218 09:54:40.667280 TX Bit3 (972~993) 22 982, Bit11 (966~987) 22 976,
1219 09:54:40.667338 TX Bit4 (977~998) 22 987, Bit12 (968~989) 22 978,
1220 09:54:40.667395 TX Bit5 (975~996) 22 985, Bit13 (968~989) 22 978,
1221 09:54:40.667465 TX Bit6 (976~997) 22 986, Bit14 (967~990) 24 978,
1222 09:54:40.667524 TX Bit7 (977~998) 22 987, Bit15 (971~992) 22 981,
1223 09:54:40.667593
1224 09:54:40.667650 Write Rank0 MR14 =0x16
1225 09:54:40.667724
1226 09:54:40.667789 CH=0, VrefRange= 0, VrefLevel = 22
1227 09:54:40.667855 TX Bit0 (977~1000) 24 988, Bit8 (964~985) 22 974,
1228 09:54:40.667917 TX Bit1 (977~999) 23 988, Bit9 (967~989) 23 978,
1229 09:54:40.667976 TX Bit2 (977~1000) 24 988, Bit10 (970~992) 23 981,
1230 09:54:40.668034 TX Bit3 (972~993) 22 982, Bit11 (966~988) 23 977,
1231 09:54:40.668093 TX Bit4 (976~999) 24 987, Bit12 (968~990) 23 979,
1232 09:54:40.668150 TX Bit5 (974~996) 23 985, Bit13 (967~990) 24 978,
1233 09:54:40.668209 TX Bit6 (976~997) 22 986, Bit14 (967~990) 24 978,
1234 09:54:40.668266 TX Bit7 (977~999) 23 988, Bit15 (970~992) 23 981,
1235 09:54:40.668324
1236 09:54:40.668381 Write Rank0 MR14 =0x18
1237 09:54:40.668438
1238 09:54:40.668494 CH=0, VrefRange= 0, VrefLevel = 24
1239 09:54:40.668552 TX Bit0 (977~1000) 24 988, Bit8 (964~986) 23 975,
1240 09:54:40.668609 TX Bit1 (976~999) 24 987, Bit9 (966~990) 25 978,
1241 09:54:40.668667 TX Bit2 (977~1000) 24 988, Bit10 (970~993) 24 981,
1242 09:54:40.668725 TX Bit3 (971~994) 24 982, Bit11 (965~989) 25 977,
1243 09:54:40.668783 TX Bit4 (976~999) 24 987, Bit12 (967~990) 24 978,
1244 09:54:40.668840 TX Bit5 (974~997) 24 985, Bit13 (967~990) 24 978,
1245 09:54:40.668898 TX Bit6 (975~998) 24 986, Bit14 (967~991) 25 979,
1246 09:54:40.668956 TX Bit7 (977~999) 23 988, Bit15 (969~992) 24 980,
1247 09:54:40.669013
1248 09:54:40.669069 Write Rank0 MR14 =0x1a
1249 09:54:40.669126
1250 09:54:40.669183 CH=0, VrefRange= 0, VrefLevel = 26
1251 09:54:40.669241 TX Bit0 (977~1001) 25 989, Bit8 (963~987) 25 975,
1252 09:54:40.669299 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1253 09:54:40.669357 TX Bit2 (977~1001) 25 989, Bit10 (970~994) 25 982,
1254 09:54:40.669415 TX Bit3 (971~994) 24 982, Bit11 (965~989) 25 977,
1255 09:54:40.669472 TX Bit4 (976~999) 24 987, Bit12 (967~990) 24 978,
1256 09:54:40.669530 TX Bit5 (973~998) 26 985, Bit13 (967~990) 24 978,
1257 09:54:40.669587 TX Bit6 (975~999) 25 987, Bit14 (967~991) 25 979,
1258 09:54:40.669644 TX Bit7 (976~999) 24 987, Bit15 (969~993) 25 981,
1259 09:54:40.669715
1260 09:54:40.669773 Write Rank0 MR14 =0x1c
1261 09:54:40.669831
1262 09:54:40.669888 CH=0, VrefRange= 0, VrefLevel = 28
1263 09:54:40.669946 TX Bit0 (977~1001) 25 989, Bit8 (963~988) 26 975,
1264 09:54:40.670005 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1265 09:54:40.670062 TX Bit2 (977~1001) 25 989, Bit10 (969~994) 26 981,
1266 09:54:40.670120 TX Bit3 (970~995) 26 982, Bit11 (965~989) 25 977,
1267 09:54:40.670177 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1268 09:54:40.670235 TX Bit5 (974~998) 25 986, Bit13 (967~990) 24 978,
1269 09:54:40.670293 TX Bit6 (974~999) 26 986, Bit14 (967~991) 25 979,
1270 09:54:40.670350 TX Bit7 (976~1000) 25 988, Bit15 (969~993) 25 981,
1271 09:54:40.670408
1272 09:54:40.670465 Write Rank0 MR14 =0x1e
1273 09:54:40.670522
1274 09:54:40.670580 CH=0, VrefRange= 0, VrefLevel = 30
1275 09:54:40.670647 TX Bit0 (977~1001) 25 989, Bit8 (963~988) 26 975,
1276 09:54:40.670706 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1277 09:54:40.670763 TX Bit2 (977~1001) 25 989, Bit10 (969~994) 26 981,
1278 09:54:40.670821 TX Bit3 (970~995) 26 982, Bit11 (965~989) 25 977,
1279 09:54:40.670879 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1280 09:54:40.670936 TX Bit5 (974~998) 25 986, Bit13 (967~990) 24 978,
1281 09:54:40.670994 TX Bit6 (974~999) 26 986, Bit14 (967~991) 25 979,
1282 09:54:40.671052 TX Bit7 (976~1000) 25 988, Bit15 (969~993) 25 981,
1283 09:54:40.671110
1284 09:54:40.671167 Write Rank0 MR14 =0x20
1285 09:54:40.671224
1286 09:54:40.671280 CH=0, VrefRange= 0, VrefLevel = 32
1287 09:54:40.671337 TX Bit0 (977~1001) 25 989, Bit8 (963~988) 26 975,
1288 09:54:40.671395 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1289 09:54:40.671462 TX Bit2 (977~1001) 25 989, Bit10 (969~994) 26 981,
1290 09:54:40.671520 TX Bit3 (970~995) 26 982, Bit11 (965~989) 25 977,
1291 09:54:40.671578 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1292 09:54:40.671636 TX Bit5 (974~998) 25 986, Bit13 (967~990) 24 978,
1293 09:54:40.671703 TX Bit6 (974~999) 26 986, Bit14 (967~991) 25 979,
1294 09:54:40.671761 TX Bit7 (976~1000) 25 988, Bit15 (969~993) 25 981,
1295 09:54:40.671818
1296 09:54:40.671875 Write Rank0 MR14 =0x22
1297 09:54:40.671931
1298 09:54:40.671987 CH=0, VrefRange= 0, VrefLevel = 34
1299 09:54:40.672044 TX Bit0 (977~1001) 25 989, Bit8 (963~988) 26 975,
1300 09:54:40.672101 TX Bit1 (976~1000) 25 988, Bit9 (967~990) 24 978,
1301 09:54:40.672158 TX Bit2 (977~1001) 25 989, Bit10 (969~994) 26 981,
1302 09:54:40.672215 TX Bit3 (970~995) 26 982, Bit11 (965~989) 25 977,
1303 09:54:40.672272 TX Bit4 (976~1000) 25 988, Bit12 (967~991) 25 979,
1304 09:54:40.672329 TX Bit5 (974~998) 25 986, Bit13 (967~990) 24 978,
1305 09:54:40.672386 TX Bit6 (974~999) 26 986, Bit14 (967~991) 25 979,
1306 09:54:40.672443 TX Bit7 (976~1000) 25 988, Bit15 (969~993) 25 981,
1307 09:54:40.672500
1308 09:54:40.672556
1309 09:54:40.672612 TX Vref found, early break! 380< 381
1310 09:54:40.672669 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
1311 09:54:40.672726 u1DelayCellOfst[0]=9 cells (7 PI)
1312 09:54:40.672783 u1DelayCellOfst[1]=7 cells (6 PI)
1313 09:54:40.673037 u1DelayCellOfst[2]=9 cells (7 PI)
1314 09:54:40.673104 u1DelayCellOfst[3]=0 cells (0 PI)
1315 09:54:40.673161 u1DelayCellOfst[4]=7 cells (6 PI)
1316 09:54:40.673219 u1DelayCellOfst[5]=5 cells (4 PI)
1317 09:54:40.673275 u1DelayCellOfst[6]=5 cells (4 PI)
1318 09:54:40.673332 u1DelayCellOfst[7]=7 cells (6 PI)
1319 09:54:40.673388 Byte0, DQ PI dly=982, DQM PI dly= 985
1320 09:54:40.673445 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
1321 09:54:40.673503
1322 09:54:40.673559 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
1323 09:54:40.673616
1324 09:54:40.673677 u1DelayCellOfst[8]=0 cells (0 PI)
1325 09:54:40.673746 u1DelayCellOfst[9]=3 cells (3 PI)
1326 09:54:40.673814 u1DelayCellOfst[10]=7 cells (6 PI)
1327 09:54:40.673873 u1DelayCellOfst[11]=2 cells (2 PI)
1328 09:54:40.673930 u1DelayCellOfst[12]=5 cells (4 PI)
1329 09:54:40.673987 u1DelayCellOfst[13]=3 cells (3 PI)
1330 09:54:40.674044 u1DelayCellOfst[14]=5 cells (4 PI)
1331 09:54:40.674112 u1DelayCellOfst[15]=7 cells (6 PI)
1332 09:54:40.674170 Byte1, DQ PI dly=975, DQM PI dly= 978
1333 09:54:40.674228 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15)
1334 09:54:40.674285
1335 09:54:40.674341 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15)
1336 09:54:40.674398
1337 09:54:40.674455 Write Rank0 MR14 =0x1c
1338 09:54:40.674511
1339 09:54:40.674566 Final TX Range 0 Vref 28
1340 09:54:40.674623
1341 09:54:40.674680 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1342 09:54:40.674738
1343 09:54:40.674794 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1344 09:54:40.674852 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1345 09:54:40.674908 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1346 09:54:40.674965 Write Rank0 MR3 =0xb0
1347 09:54:40.675022 DramC Write-DBI on
1348 09:54:40.675078 ==
1349 09:54:40.675134 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1350 09:54:40.675191 fsp= 1, odt_onoff= 1, Byte mode= 0
1351 09:54:40.675248 ==
1352 09:54:40.675304 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1353 09:54:40.675361
1354 09:54:40.675429 Begin, DQ Scan Range 698~762
1355 09:54:40.675489
1356 09:54:40.675545
1357 09:54:40.675602 TX Vref Scan disable
1358 09:54:40.675663 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1359 09:54:40.675729 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1360 09:54:40.675788 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1361 09:54:40.675847 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1362 09:54:40.675904 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1363 09:54:40.675962 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1364 09:54:40.676020 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1365 09:54:40.676078 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1366 09:54:40.676136 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1367 09:54:40.676194 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1368 09:54:40.676252 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1369 09:54:40.676309 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1370 09:54:40.676367 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1371 09:54:40.676425 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1372 09:54:40.676483 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1373 09:54:40.676540 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1374 09:54:40.676598 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1375 09:54:40.676657 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1376 09:54:40.676714 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1377 09:54:40.676772 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
1378 09:54:40.676829 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
1379 09:54:40.676887 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
1380 09:54:40.676944 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1381 09:54:40.677003 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1382 09:54:40.677060 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1383 09:54:40.677117 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1384 09:54:40.677175 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1385 09:54:40.677233 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1386 09:54:40.677291 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1387 09:54:40.677358 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1388 09:54:40.677417 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
1389 09:54:40.677474 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
1390 09:54:40.677532 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
1391 09:54:40.677589 746 |2 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
1392 09:54:40.677648 Byte0, DQ PI dly=732, DQM PI dly= 732
1393 09:54:40.677720 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 28)
1394 09:54:40.677778
1395 09:54:40.677835 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 28)
1396 09:54:40.677892
1397 09:54:40.677949 Byte1, DQ PI dly=722, DQM PI dly= 722
1398 09:54:40.678005 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 18)
1399 09:54:40.678062
1400 09:54:40.678119 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 18)
1401 09:54:40.678176
1402 09:54:40.678233 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1403 09:54:40.678290 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1404 09:54:40.678348 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1405 09:54:40.678404 Write Rank0 MR3 =0x30
1406 09:54:40.678462 DramC Write-DBI off
1407 09:54:40.678517
1408 09:54:40.678574 [DATLAT]
1409 09:54:40.678631 Freq=1600, CH0 RK0, use_rxtx_scan=0
1410 09:54:40.678688
1411 09:54:40.678744 DATLAT Default: 0xf
1412 09:54:40.678800 7, 0xFFFF, sum=0
1413 09:54:40.678857 8, 0xFFFF, sum=0
1414 09:54:40.678915 9, 0xFFFF, sum=0
1415 09:54:40.678973 10, 0xFFFF, sum=0
1416 09:54:40.679031 11, 0xFFFF, sum=0
1417 09:54:40.679088 12, 0xFFFF, sum=0
1418 09:54:40.679145 13, 0xFFFF, sum=0
1419 09:54:40.679203 14, 0x0, sum=1
1420 09:54:40.679260 15, 0x0, sum=2
1421 09:54:40.679318 16, 0x0, sum=3
1422 09:54:40.679375 17, 0x0, sum=4
1423 09:54:40.679458 pattern=2 first_step=14 total pass=5 best_step=16
1424 09:54:40.679517 ==
1425 09:54:40.679574 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1426 09:54:40.679631 fsp= 1, odt_onoff= 1, Byte mode= 0
1427 09:54:40.679693 ==
1428 09:54:40.679762 Start DQ dly to find pass range UseTestEngine =1
1429 09:54:40.679820 x-axis: bit #, y-axis: DQ dly (-127~63)
1430 09:54:40.679878 RX Vref Scan = 1
1431 09:54:40.679934
1432 09:54:40.679990 RX Vref found, early break!
1433 09:54:40.680047
1434 09:54:40.680103 Final RX Vref 12, apply to both rank0 and 1
1435 09:54:40.680160 ==
1436 09:54:40.680216 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1437 09:54:40.680273 fsp= 1, odt_onoff= 1, Byte mode= 0
1438 09:54:40.680330 ==
1439 09:54:40.680386 DQS Delay:
1440 09:54:40.680442 DQS0 = 0, DQS1 = 0
1441 09:54:40.680498 DQM Delay:
1442 09:54:40.680762 DQM0 = 19, DQM1 = 18
1443 09:54:40.680826 DQ Delay:
1444 09:54:40.680885 DQ0 =22, DQ1 =21, DQ2 =21, DQ3 =15
1445 09:54:40.680943 DQ4 =21, DQ5 =17, DQ6 =19, DQ7 =20
1446 09:54:40.681000 DQ8 =14, DQ9 =16, DQ10 =25, DQ11 =16
1447 09:54:40.681057 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
1448 09:54:40.681113
1449 09:54:40.681169
1450 09:54:40.681225
1451 09:54:40.681282 [DramC_TX_OE_Calibration] TA2
1452 09:54:40.681339 Original DQ_B0 (3 6) =30, OEN = 27
1453 09:54:40.681397 Original DQ_B1 (3 6) =30, OEN = 27
1454 09:54:40.681454 23, 0x0, End_B0=23 End_B1=23
1455 09:54:40.681512 24, 0x0, End_B0=24 End_B1=24
1456 09:54:40.681570 25, 0x0, End_B0=25 End_B1=25
1457 09:54:40.681628 26, 0x0, End_B0=26 End_B1=26
1458 09:54:40.681690 27, 0x0, End_B0=27 End_B1=27
1459 09:54:40.681758 28, 0x0, End_B0=28 End_B1=28
1460 09:54:40.681815 29, 0x0, End_B0=29 End_B1=29
1461 09:54:40.681873 30, 0x0, End_B0=30 End_B1=30
1462 09:54:40.681931 31, 0xFFFF, End_B0=30 End_B1=30
1463 09:54:40.681989 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1464 09:54:40.682045 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1465 09:54:40.682103
1466 09:54:40.682159
1467 09:54:40.682215 Write Rank0 MR23 =0x3f
1468 09:54:40.682272 [DQSOSC]
1469 09:54:40.682328 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 402 ps
1470 09:54:40.682387 CH0_RK0: MR19=0x303, MR18=0xF0F, DQSOSC=402, MR23=63, INC=15, DEC=22
1471 09:54:40.682444 Write Rank0 MR23 =0x3f
1472 09:54:40.682501 [DQSOSC]
1473 09:54:40.682558 [DQSOSCAuto] RK0, (LSB)MR18= 0x1010, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1474 09:54:40.682615 CH0 RK0: MR19=303, MR18=1010
1475 09:54:40.682672 [RankSwap] Rank num 2, (Multi 1), Rank 1
1476 09:54:40.682729 Write Rank0 MR2 =0xad
1477 09:54:40.682785 [Write Leveling]
1478 09:54:40.682842 delay byte0 byte1 byte2 byte3
1479 09:54:40.682898
1480 09:54:40.682954 10 0 0
1481 09:54:40.683013 11 0 0
1482 09:54:40.683070 12 0 0
1483 09:54:40.683127 13 0 0
1484 09:54:40.683184 14 0 0
1485 09:54:40.683241 15 0 0
1486 09:54:40.683298 16 0 0
1487 09:54:40.683355 17 0 0
1488 09:54:40.683422 18 0 0
1489 09:54:40.683482 19 0 0
1490 09:54:40.683539 20 0 0
1491 09:54:40.683596 21 0 0
1492 09:54:40.683653 22 0 0
1493 09:54:40.683724 23 0 ff
1494 09:54:40.683783 24 0 ff
1495 09:54:40.683840 25 0 ff
1496 09:54:40.683897 26 ff ff
1497 09:54:40.683954 27 ff ff
1498 09:54:40.684011 28 ff ff
1499 09:54:40.684068 29 ff ff
1500 09:54:40.684125 30 ff ff
1501 09:54:40.684183 31 ff ff
1502 09:54:40.684251 32 ff ff
1503 09:54:40.684310 pass bytecount = 0xff (0xff: all bytes pass)
1504 09:54:40.684366
1505 09:54:40.684423 DQS0 dly: 26
1506 09:54:40.684479 DQS1 dly: 23
1507 09:54:40.684535 Write Rank0 MR2 =0x2d
1508 09:54:40.684592 [RankSwap] Rank num 2, (Multi 1), Rank 0
1509 09:54:40.684648 Write Rank1 MR1 =0xd6
1510 09:54:40.684736 [Gating]
1511 09:54:40.684826 ==
1512 09:54:40.684916 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1513 09:54:40.685000 fsp= 1, odt_onoff= 1, Byte mode= 0
1514 09:54:40.685060 ==
1515 09:54:40.685118 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
1516 09:54:40.685177 3 1 4 |2c2b 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1517 09:54:40.685235 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1518 09:54:40.685293 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1519 09:54:40.685351 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1520 09:54:40.685409 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1521 09:54:40.685467 3 1 24 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1522 09:54:40.685524 3 1 28 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1523 09:54:40.685582 3 2 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1524 09:54:40.685639 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1525 09:54:40.685710 3 2 8 |201 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1526 09:54:40.685787 3 2 12 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1527 09:54:40.685885 3 2 16 |3534 2323 |(11 11)(11 11) |(0 0)(1 1)| 0
1528 09:54:40.685953 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1529 09:54:40.686013 3 2 24 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1530 09:54:40.686072 3 2 28 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1531 09:54:40.686131 3 3 0 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1532 09:54:40.686190 3 3 4 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1533 09:54:40.686247 3 3 8 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1534 09:54:40.686305 3 3 12 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1535 09:54:40.686363 [Byte 0] Lead/lag Transition tap number (1)
1536 09:54:40.686421 3 3 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1537 09:54:40.686478 3 3 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1538 09:54:40.686535 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1539 09:54:40.686593 [Byte 1] Lead/lag falling Transition (3, 3, 24)
1540 09:54:40.686649 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1541 09:54:40.686707 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1542 09:54:40.686765 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1543 09:54:40.686823 3 4 8 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1544 09:54:40.686880 3 4 12 |403 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1545 09:54:40.686938 3 4 16 |3d3d 403 |(11 11)(11 11) |(1 1)(1 1)| 0
1546 09:54:40.686996 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1547 09:54:40.687053 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1548 09:54:40.687111 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1549 09:54:40.687168 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1550 09:54:40.687225 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1551 09:54:40.687283 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1552 09:54:40.687340 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1553 09:54:40.687398 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1554 09:54:40.687470 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1555 09:54:40.687529 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1556 09:54:40.687586 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1557 09:54:40.687657 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1558 09:54:40.687725 [Byte 0] Lead/lag falling Transition (3, 6, 0)
1559 09:54:40.687990 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1560 09:54:40.688091 [Byte 0] Lead/lag Transition tap number (2)
1561 09:54:40.688183 [Byte 1] Lead/lag falling Transition (3, 6, 4)
1562 09:54:40.688273 3 6 8 |403 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1563 09:54:40.688366 [Byte 1] Lead/lag Transition tap number (2)
1564 09:54:40.688456 3 6 12 |4646 3d3d |(0 0)(11 11) |(0 0)(0 0)| 0
1565 09:54:40.688548 [Byte 0]First pass (3, 6, 12)
1566 09:54:40.688639 3 6 16 |4646 4646 |(0 0)(10 10) |(0 0)(0 0)| 0
1567 09:54:40.688731 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1568 09:54:40.688823 [Byte 1]First pass (3, 6, 20)
1569 09:54:40.688913 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1570 09:54:40.689004 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1571 09:54:40.689096 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1572 09:54:40.689188 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1573 09:54:40.689279 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1574 09:54:40.689371 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1575 09:54:40.689462 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1576 09:54:40.689554 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1577 09:54:40.689646 All bytes gating window > 1UI, Early break!
1578 09:54:40.689734
1579 09:54:40.689823 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 4)
1580 09:54:40.689912
1581 09:54:40.690001 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
1582 09:54:40.690089
1583 09:54:40.690177
1584 09:54:40.690264
1585 09:54:40.690353 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1586 09:54:40.690453
1587 09:54:40.690543 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
1588 09:54:40.690631
1589 09:54:40.690719
1590 09:54:40.690807 Write Rank1 MR1 =0x56
1591 09:54:40.690896
1592 09:54:40.690994 best RODT dly(2T, 0.5T) = (2, 3)
1593 09:54:40.691082
1594 09:54:40.691171 best RODT dly(2T, 0.5T) = (2, 3)
1595 09:54:40.691259 ==
1596 09:54:40.691349 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1597 09:54:40.691451 fsp= 1, odt_onoff= 1, Byte mode= 0
1598 09:54:40.691512 ==
1599 09:54:40.691569 Start DQ dly to find pass range UseTestEngine =0
1600 09:54:40.691626 x-axis: bit #, y-axis: DQ dly (-127~63)
1601 09:54:40.691683 RX Vref Scan = 0
1602 09:54:40.691740 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1603 09:54:40.691798 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1604 09:54:40.691857 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1605 09:54:40.691915 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1606 09:54:40.691972 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1607 09:54:40.692031 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1608 09:54:40.692089 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1609 09:54:40.692146 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1610 09:54:40.692204 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1611 09:54:40.692262 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1612 09:54:40.692319 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1613 09:54:40.692376 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1614 09:54:40.692439 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1615 09:54:40.692514 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1616 09:54:40.692573 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1617 09:54:40.692630 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1618 09:54:40.692688 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1619 09:54:40.692745 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1620 09:54:40.692803 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1621 09:54:40.692861 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1622 09:54:40.692918 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1623 09:54:40.692975 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1624 09:54:40.693033 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1625 09:54:40.693090 -3, [0] xxxxxxxx oxxxxxxx [MSB]
1626 09:54:40.693147 -2, [0] xxxoxxxx oxxoxxxx [MSB]
1627 09:54:40.693204 -1, [0] xxxoxxxx oxxoxxxx [MSB]
1628 09:54:40.693261 0, [0] xxxoxoxx ooxooxxx [MSB]
1629 09:54:40.693319 1, [0] xxxoxoox ooxoooxx [MSB]
1630 09:54:40.693376 2, [0] xxxoxoox ooxoooxx [MSB]
1631 09:54:40.693433 3, [0] xxxooooo ooxoooox [MSB]
1632 09:54:40.693491 4, [0] xoxooooo ooxoooox [MSB]
1633 09:54:40.693548 5, [0] oooooooo ooxooooo [MSB]
1634 09:54:40.693606 6, [0] oooooooo ooxooooo [MSB]
1635 09:54:40.693663 33, [0] oooooooo xooooooo [MSB]
1636 09:54:40.693721 34, [0] oooxoooo xooooooo [MSB]
1637 09:54:40.693778 35, [0] oooxoooo xooooooo [MSB]
1638 09:54:40.693836 36, [0] oooxoooo xooxoooo [MSB]
1639 09:54:40.693894 37, [0] oooxoxoo xxoxoxoo [MSB]
1640 09:54:40.693952 38, [0] oooxoxoo xxoxxxxo [MSB]
1641 09:54:40.694010 39, [0] oooxoxox xxoxxxxo [MSB]
1642 09:54:40.694067 40, [0] oooxoxxx xxoxxxxo [MSB]
1643 09:54:40.694124 41, [0] oxxxxxxx xxoxxxxx [MSB]
1644 09:54:40.694182 42, [0] oxxxxxxx xxoxxxxx [MSB]
1645 09:54:40.694239 43, [0] xxxxxxxx xxoxxxxx [MSB]
1646 09:54:40.694298 44, [0] xxxxxxxx xxoxxxxx [MSB]
1647 09:54:40.694356 45, [0] xxxxxxxx xxxxxxxx [MSB]
1648 09:54:40.694417 iDelay=45, Bit 0, Center 23 (5 ~ 42) 38
1649 09:54:40.694481 iDelay=45, Bit 1, Center 22 (4 ~ 40) 37
1650 09:54:40.694538 iDelay=45, Bit 2, Center 22 (5 ~ 40) 36
1651 09:54:40.694595 iDelay=45, Bit 3, Center 15 (-2 ~ 33) 36
1652 09:54:40.694652 iDelay=45, Bit 4, Center 21 (3 ~ 40) 38
1653 09:54:40.694708 iDelay=45, Bit 5, Center 18 (0 ~ 36) 37
1654 09:54:40.694775 iDelay=45, Bit 6, Center 20 (1 ~ 39) 39
1655 09:54:40.694832 iDelay=45, Bit 7, Center 20 (3 ~ 38) 36
1656 09:54:40.694889 iDelay=45, Bit 8, Center 14 (-3 ~ 32) 36
1657 09:54:40.694945 iDelay=45, Bit 9, Center 18 (0 ~ 36) 37
1658 09:54:40.695009 iDelay=45, Bit 10, Center 25 (7 ~ 44) 38
1659 09:54:40.695098 iDelay=45, Bit 11, Center 16 (-2 ~ 35) 38
1660 09:54:40.695175 iDelay=45, Bit 12, Center 18 (0 ~ 37) 38
1661 09:54:40.695233 iDelay=45, Bit 13, Center 18 (1 ~ 36) 36
1662 09:54:40.695290 iDelay=45, Bit 14, Center 20 (3 ~ 37) 35
1663 09:54:40.695347 iDelay=45, Bit 15, Center 22 (5 ~ 40) 36
1664 09:54:40.695411 ==
1665 09:54:40.695471 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1666 09:54:40.695528 fsp= 1, odt_onoff= 1, Byte mode= 0
1667 09:54:40.695585 ==
1668 09:54:40.695642 DQS Delay:
1669 09:54:40.695698 DQS0 = 0, DQS1 = 0
1670 09:54:40.695755 DQM Delay:
1671 09:54:40.695811 DQM0 = 20, DQM1 = 18
1672 09:54:40.695868 DQ Delay:
1673 09:54:40.695924 DQ0 =23, DQ1 =22, DQ2 =22, DQ3 =15
1674 09:54:40.695981 DQ4 =21, DQ5 =18, DQ6 =20, DQ7 =20
1675 09:54:40.696037 DQ8 =14, DQ9 =18, DQ10 =25, DQ11 =16
1676 09:54:40.696094 DQ12 =18, DQ13 =18, DQ14 =20, DQ15 =22
1677 09:54:40.696150
1678 09:54:40.696205
1679 09:54:40.696261 DramC Write-DBI off
1680 09:54:40.696317 ==
1681 09:54:40.696373 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1682 09:54:40.696434 fsp= 1, odt_onoff= 1, Byte mode= 0
1683 09:54:40.696507 ==
1684 09:54:40.696565 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1685 09:54:40.696622
1686 09:54:40.696679 Begin, DQ Scan Range 919~1175
1687 09:54:40.696736
1688 09:54:40.696792
1689 09:54:40.696848 TX Vref Scan disable
1690 09:54:40.697102 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB]
1691 09:54:40.697168 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1692 09:54:40.697229 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1693 09:54:40.697287 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1694 09:54:40.697346 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1695 09:54:40.697405 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1696 09:54:40.697462 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1697 09:54:40.697520 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1698 09:54:40.697577 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1699 09:54:40.697634 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1700 09:54:40.697692 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1701 09:54:40.697760 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1702 09:54:40.697819 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1703 09:54:40.697877 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1704 09:54:40.697934 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1705 09:54:40.698008 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1706 09:54:40.698085 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1707 09:54:40.698156 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1708 09:54:40.698225 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1709 09:54:40.698286 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1710 09:54:40.698345 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1711 09:54:40.698408 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1712 09:54:40.698467 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1713 09:54:40.698526 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1714 09:54:40.698616 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1715 09:54:40.698711 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1716 09:54:40.698803 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1717 09:54:40.698895 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1718 09:54:40.698987 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1719 09:54:40.699079 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1720 09:54:40.699172 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1721 09:54:40.699264 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1722 09:54:40.699356 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1723 09:54:40.699445 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1724 09:54:40.699506 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1725 09:54:40.699565 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1726 09:54:40.699624 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1727 09:54:40.699682 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1728 09:54:40.699739 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1729 09:54:40.699797 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1730 09:54:40.699854 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1731 09:54:40.699912 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1732 09:54:40.699970 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1733 09:54:40.700028 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1734 09:54:40.700085 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1735 09:54:40.700143 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1736 09:54:40.700201 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1737 09:54:40.700258 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1738 09:54:40.700316 967 |3 6 7|[0] xxxxxxxx oxxoxxxx [MSB]
1739 09:54:40.700373 968 |3 6 8|[0] xxxxxxxx ooxoxxxx [MSB]
1740 09:54:40.700430 969 |3 6 9|[0] xxxxxxxx ooxoooox [MSB]
1741 09:54:40.700487 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1742 09:54:40.700545 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1743 09:54:40.700603 972 |3 6 12|[0] xxxxxxxx ooxooooo [MSB]
1744 09:54:40.700660 973 |3 6 13|[0] xxxooooo oooooooo [MSB]
1745 09:54:40.700739 974 |3 6 14|[0] xoxooooo oooooooo [MSB]
1746 09:54:40.700798 975 |3 6 15|[0] ooxooooo oooooooo [MSB]
1747 09:54:40.700855 986 |3 6 26|[0] oooooooo xxxxxxxx [MSB]
1748 09:54:40.700913 987 |3 6 27|[0] oooooooo xxxxxxxx [MSB]
1749 09:54:40.700971 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1750 09:54:40.701028 989 |3 6 29|[0] oooxoooo xxxxxxxx [MSB]
1751 09:54:40.701086 990 |3 6 30|[0] oooxoooo xxxxxxxx [MSB]
1752 09:54:40.701143 991 |3 6 31|[0] oooxoxoo xxxxxxxx [MSB]
1753 09:54:40.701201 992 |3 6 32|[0] xxoxxxxx xxxxxxxx [MSB]
1754 09:54:40.701268 993 |3 6 33|[0] xxxxxxxx xxxxxxxx [MSB]
1755 09:54:40.701327 Byte0, DQ PI dly=982, DQM PI dly= 982
1756 09:54:40.701384 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 22)
1757 09:54:40.701442
1758 09:54:40.701499 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 22)
1759 09:54:40.701557
1760 09:54:40.701614 Byte1, DQ PI dly=977, DQM PI dly= 977
1761 09:54:40.701671 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
1762 09:54:40.701729
1763 09:54:40.701785 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
1764 09:54:40.701842
1765 09:54:40.701897 ==
1766 09:54:40.701964 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1767 09:54:40.702022 fsp= 1, odt_onoff= 1, Byte mode= 0
1768 09:54:40.702079 ==
1769 09:54:40.702135 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1770 09:54:40.702191
1771 09:54:40.702247 Begin, DQ Scan Range 953~1017
1772 09:54:40.702303 Write Rank1 MR14 =0x0
1773 09:54:40.702359
1774 09:54:40.702415 CH=0, VrefRange= 0, VrefLevel = 0
1775 09:54:40.702471 TX Bit0 (977~991) 15 984, Bit8 (968~981) 14 974,
1776 09:54:40.702529 TX Bit1 (977~988) 12 982, Bit9 (970~983) 14 976,
1777 09:54:40.702585 TX Bit2 (977~989) 13 983, Bit10 (976~987) 12 981,
1778 09:54:40.702642 TX Bit3 (971~982) 12 976, Bit11 (969~982) 14 975,
1779 09:54:40.702699 TX Bit4 (976~988) 13 982, Bit12 (972~984) 13 978,
1780 09:54:40.702755 TX Bit5 (974~985) 12 979, Bit13 (973~981) 9 977,
1781 09:54:40.702812 TX Bit6 (975~987) 13 981, Bit14 (972~983) 12 977,
1782 09:54:40.702868 TX Bit7 (976~989) 14 982, Bit15 (975~987) 13 981,
1783 09:54:40.702925
1784 09:54:40.702981 Write Rank1 MR14 =0x2
1785 09:54:40.703036
1786 09:54:40.703093 CH=0, VrefRange= 0, VrefLevel = 2
1787 09:54:40.703149 TX Bit0 (977~991) 15 984, Bit8 (968~982) 15 975,
1788 09:54:40.703206 TX Bit1 (976~989) 14 982, Bit9 (969~984) 16 976,
1789 09:54:40.703262 TX Bit2 (977~990) 14 983, Bit10 (976~989) 14 982,
1790 09:54:40.703318 TX Bit3 (970~983) 14 976, Bit11 (968~982) 15 975,
1791 09:54:40.703375 TX Bit4 (976~989) 14 982, Bit12 (971~984) 14 977,
1792 09:54:40.703443 TX Bit5 (972~985) 14 978, Bit13 (973~982) 10 977,
1793 09:54:40.703501 TX Bit6 (974~988) 15 981, Bit14 (972~984) 13 978,
1794 09:54:40.703558 TX Bit7 (975~990) 16 982, Bit15 (975~988) 14 981,
1795 09:54:40.703614
1796 09:54:40.703670 Write Rank1 MR14 =0x4
1797 09:54:40.703726
1798 09:54:40.703986 CH=0, VrefRange= 0, VrefLevel = 4
1799 09:54:40.704050 TX Bit0 (977~992) 16 984, Bit8 (968~982) 15 975,
1800 09:54:40.704110 TX Bit1 (976~990) 15 983, Bit9 (969~984) 16 976,
1801 09:54:40.704168 TX Bit2 (977~991) 15 984, Bit10 (975~990) 16 982,
1802 09:54:40.704225 TX Bit3 (970~984) 15 977, Bit11 (968~983) 16 975,
1803 09:54:40.704282 TX Bit4 (976~990) 15 983, Bit12 (970~985) 16 977,
1804 09:54:40.704338 TX Bit5 (973~987) 15 980, Bit13 (972~983) 12 977,
1805 09:54:40.704395 TX Bit6 (974~988) 15 981, Bit14 (971~984) 14 977,
1806 09:54:40.704463 TX Bit7 (975~990) 16 982, Bit15 (974~989) 16 981,
1807 09:54:40.704520
1808 09:54:40.704576 Write Rank1 MR14 =0x6
1809 09:54:40.704632
1810 09:54:40.704689 CH=0, VrefRange= 0, VrefLevel = 6
1811 09:54:40.704745 TX Bit0 (977~992) 16 984, Bit8 (968~983) 16 975,
1812 09:54:40.704802 TX Bit1 (976~990) 15 983, Bit9 (969~985) 17 977,
1813 09:54:40.704859 TX Bit2 (977~991) 15 984, Bit10 (975~990) 16 982,
1814 09:54:40.704916 TX Bit3 (970~985) 16 977, Bit11 (968~983) 16 975,
1815 09:54:40.704973 TX Bit4 (975~991) 17 983, Bit12 (970~985) 16 977,
1816 09:54:40.705029 TX Bit5 (972~988) 17 980, Bit13 (971~983) 13 977,
1817 09:54:40.705086 TX Bit6 (973~989) 17 981, Bit14 (971~985) 15 978,
1818 09:54:40.705143 TX Bit7 (975~991) 17 983, Bit15 (973~990) 18 981,
1819 09:54:40.705199
1820 09:54:40.705254 Write Rank1 MR14 =0x8
1821 09:54:40.705310
1822 09:54:40.705366 CH=0, VrefRange= 0, VrefLevel = 8
1823 09:54:40.705423 TX Bit0 (976~993) 18 984, Bit8 (968~983) 16 975,
1824 09:54:40.705480 TX Bit1 (976~991) 16 983, Bit9 (969~985) 17 977,
1825 09:54:40.705536 TX Bit2 (977~991) 15 984, Bit10 (975~990) 16 982,
1826 09:54:40.705593 TX Bit3 (969~985) 17 977, Bit11 (968~983) 16 975,
1827 09:54:40.705649 TX Bit4 (975~991) 17 983, Bit12 (969~986) 18 977,
1828 09:54:40.705705 TX Bit5 (971~988) 18 979, Bit13 (971~984) 14 977,
1829 09:54:40.705762 TX Bit6 (973~990) 18 981, Bit14 (970~986) 17 978,
1830 09:54:40.705819 TX Bit7 (974~991) 18 982, Bit15 (974~990) 17 982,
1831 09:54:40.705875
1832 09:54:40.705935 Write Rank1 MR14 =0xa
1833 09:54:40.705998
1834 09:54:40.706054 CH=0, VrefRange= 0, VrefLevel = 10
1835 09:54:40.706111 TX Bit0 (976~993) 18 984, Bit8 (967~983) 17 975,
1836 09:54:40.706169 TX Bit1 (975~991) 17 983, Bit9 (968~986) 19 977,
1837 09:54:40.706225 TX Bit2 (976~992) 17 984, Bit10 (975~991) 17 983,
1838 09:54:40.706281 TX Bit3 (969~986) 18 977, Bit11 (968~984) 17 976,
1839 09:54:40.706338 TX Bit4 (974~991) 18 982, Bit12 (969~986) 18 977,
1840 09:54:40.706395 TX Bit5 (971~989) 19 980, Bit13 (970~984) 15 977,
1841 09:54:40.706451 TX Bit6 (972~991) 20 981, Bit14 (970~987) 18 978,
1842 09:54:40.706507 TX Bit7 (974~991) 18 982, Bit15 (974~991) 18 982,
1843 09:54:40.706563
1844 09:54:40.706619 Write Rank1 MR14 =0xc
1845 09:54:40.706675
1846 09:54:40.706730 CH=0, VrefRange= 0, VrefLevel = 12
1847 09:54:40.706787 TX Bit0 (976~994) 19 985, Bit8 (967~984) 18 975,
1848 09:54:40.706843 TX Bit1 (975~992) 18 983, Bit9 (967~986) 20 976,
1849 09:54:40.706900 TX Bit2 (976~992) 17 984, Bit10 (974~991) 18 982,
1850 09:54:40.706956 TX Bit3 (969~987) 19 978, Bit11 (967~984) 18 975,
1851 09:54:40.707013 TX Bit4 (974~992) 19 983, Bit12 (969~987) 19 978,
1852 09:54:40.707069 TX Bit5 (971~990) 20 980, Bit13 (970~984) 15 977,
1853 09:54:40.707126 TX Bit6 (972~991) 20 981, Bit14 (969~988) 20 978,
1854 09:54:40.707182 TX Bit7 (974~992) 19 983, Bit15 (974~991) 18 982,
1855 09:54:40.707239
1856 09:54:40.707294 Write Rank1 MR14 =0xe
1857 09:54:40.707350
1858 09:54:40.707413 CH=0, VrefRange= 0, VrefLevel = 14
1859 09:54:40.707473 TX Bit0 (976~994) 19 985, Bit8 (967~984) 18 975,
1860 09:54:40.707530 TX Bit1 (975~992) 18 983, Bit9 (968~987) 20 977,
1861 09:54:40.707587 TX Bit2 (976~993) 18 984, Bit10 (974~991) 18 982,
1862 09:54:40.707644 TX Bit3 (969~987) 19 978, Bit11 (967~985) 19 976,
1863 09:54:40.707701 TX Bit4 (974~992) 19 983, Bit12 (969~988) 20 978,
1864 09:54:40.707758 TX Bit5 (970~990) 21 980, Bit13 (969~985) 17 977,
1865 09:54:40.707814 TX Bit6 (971~991) 21 981, Bit14 (969~989) 21 979,
1866 09:54:40.707871 TX Bit7 (973~992) 20 982, Bit15 (973~991) 19 982,
1867 09:54:40.707932
1868 09:54:40.708039 Write Rank1 MR14 =0x10
1869 09:54:40.708111
1870 09:54:40.708169 CH=0, VrefRange= 0, VrefLevel = 16
1871 09:54:40.708226 TX Bit0 (976~995) 20 985, Bit8 (967~985) 19 976,
1872 09:54:40.708289 TX Bit1 (974~992) 19 983, Bit9 (968~988) 21 978,
1873 09:54:40.708385 TX Bit2 (976~994) 19 985, Bit10 (974~992) 19 983,
1874 09:54:40.708495 TX Bit3 (968~988) 21 978, Bit11 (967~985) 19 976,
1875 09:54:40.708607 TX Bit4 (973~993) 21 983, Bit12 (968~989) 22 978,
1876 09:54:40.708707 TX Bit5 (970~990) 21 980, Bit13 (969~985) 17 977,
1877 09:54:40.708799 TX Bit6 (971~991) 21 981, Bit14 (969~989) 21 979,
1878 09:54:40.708894 TX Bit7 (972~993) 22 982, Bit15 (972~992) 21 982,
1879 09:54:40.708991
1880 09:54:40.709090 Write Rank1 MR14 =0x12
1881 09:54:40.709191
1882 09:54:40.709287 CH=0, VrefRange= 0, VrefLevel = 18
1883 09:54:40.709387 TX Bit0 (976~995) 20 985, Bit8 (966~985) 20 975,
1884 09:54:40.709486 TX Bit1 (974~993) 20 983, Bit9 (968~989) 22 978,
1885 09:54:40.709584 TX Bit2 (976~994) 19 985, Bit10 (973~992) 20 982,
1886 09:54:40.709681 TX Bit3 (968~988) 21 978, Bit11 (967~986) 20 976,
1887 09:54:40.709772 TX Bit4 (972~993) 22 982, Bit12 (968~990) 23 979,
1888 09:54:40.709863 TX Bit5 (970~991) 22 980, Bit13 (969~987) 19 978,
1889 09:54:40.709964 TX Bit6 (971~992) 22 981, Bit14 (969~990) 22 979,
1890 09:54:40.710054 TX Bit7 (972~993) 22 982, Bit15 (971~992) 22 981,
1891 09:54:40.710143
1892 09:54:40.710232 Write Rank1 MR14 =0x14
1893 09:54:40.710320
1894 09:54:40.710408 CH=0, VrefRange= 0, VrefLevel = 20
1895 09:54:40.710498 TX Bit0 (975~996) 22 985, Bit8 (966~986) 21 976,
1896 09:54:40.710588 TX Bit1 (974~993) 20 983, Bit9 (968~989) 22 978,
1897 09:54:40.710679 TX Bit2 (976~994) 19 985, Bit10 (972~993) 22 982,
1898 09:54:40.710968 TX Bit3 (968~989) 22 978, Bit11 (967~987) 21 977,
1899 09:54:40.711074 TX Bit4 (972~993) 22 982, Bit12 (968~990) 23 979,
1900 09:54:40.711165 TX Bit5 (970~991) 22 980, Bit13 (969~988) 20 978,
1901 09:54:40.711256 TX Bit6 (971~992) 22 981, Bit14 (968~990) 23 979,
1902 09:54:40.711347 TX Bit7 (972~994) 23 983, Bit15 (971~993) 23 982,
1903 09:54:40.711449
1904 09:54:40.711539 Write Rank1 MR14 =0x16
1905 09:54:40.711628
1906 09:54:40.711717 CH=0, VrefRange= 0, VrefLevel = 22
1907 09:54:40.711806 TX Bit0 (975~995) 21 985, Bit8 (965~986) 22 975,
1908 09:54:40.951006 TX Bit1 (973~994) 22 983, Bit9 (967~990) 24 978,
1909 09:54:40.951559 TX Bit2 (976~995) 20 985, Bit10 (972~993) 22 982,
1910 09:54:40.952057 TX Bit3 (968~990) 23 979, Bit11 (967~987) 21 977,
1911 09:54:40.952384 TX Bit4 (972~994) 23 983, Bit12 (968~990) 23 979,
1912 09:54:40.952680 TX Bit5 (970~992) 23 981, Bit13 (969~988) 20 978,
1913 09:54:40.952967 TX Bit6 (970~993) 24 981, Bit14 (968~990) 23 979,
1914 09:54:40.953248 TX Bit7 (971~994) 24 982, Bit15 (971~993) 23 982,
1915 09:54:40.953569
1916 09:54:40.953848 Write Rank1 MR14 =0x18
1917 09:54:40.954119
1918 09:54:40.954389 CH=0, VrefRange= 0, VrefLevel = 24
1919 09:54:40.954658 TX Bit0 (974~997) 24 985, Bit8 (965~987) 23 976,
1920 09:54:40.955078 TX Bit1 (973~995) 23 984, Bit9 (967~990) 24 978,
1921 09:54:40.955379 TX Bit2 (975~995) 21 985, Bit10 (971~993) 23 982,
1922 09:54:40.955705 TX Bit3 (968~990) 23 979, Bit11 (966~989) 24 977,
1923 09:54:40.955977 TX Bit4 (971~995) 25 983, Bit12 (968~990) 23 979,
1924 09:54:40.956247 TX Bit5 (969~992) 24 980, Bit13 (968~989) 22 978,
1925 09:54:40.956516 TX Bit6 (970~993) 24 981, Bit14 (968~990) 23 979,
1926 09:54:40.956781 TX Bit7 (971~995) 25 983, Bit15 (970~993) 24 981,
1927 09:54:40.957043
1928 09:54:40.957304 Write Rank1 MR14 =0x1a
1929 09:54:40.957565
1930 09:54:40.957825 CH=0, VrefRange= 0, VrefLevel = 26
1931 09:54:40.958088 TX Bit0 (974~998) 25 986, Bit8 (965~989) 25 977,
1932 09:54:40.958477 TX Bit1 (972~995) 24 983, Bit9 (967~990) 24 978,
1933 09:54:40.958752 TX Bit2 (975~996) 22 985, Bit10 (971~993) 23 982,
1934 09:54:40.959020 TX Bit3 (967~991) 25 979, Bit11 (966~989) 24 977,
1935 09:54:40.959283 TX Bit4 (971~995) 25 983, Bit12 (968~991) 24 979,
1936 09:54:40.959575 TX Bit5 (969~992) 24 980, Bit13 (968~989) 22 978,
1937 09:54:40.959841 TX Bit6 (970~994) 25 982, Bit14 (968~991) 24 979,
1938 09:54:40.960103 TX Bit7 (971~995) 25 983, Bit15 (970~993) 24 981,
1939 09:54:40.960365
1940 09:54:40.960627 Write Rank1 MR14 =0x1c
1941 09:54:40.960889
1942 09:54:40.961149 CH=0, VrefRange= 0, VrefLevel = 28
1943 09:54:40.961408 TX Bit0 (974~998) 25 986, Bit8 (965~988) 24 976,
1944 09:54:40.961719 TX Bit1 (972~995) 24 983, Bit9 (967~990) 24 978,
1945 09:54:40.961983 TX Bit2 (974~996) 23 985, Bit10 (970~995) 26 982,
1946 09:54:40.962247 TX Bit3 (967~991) 25 979, Bit11 (966~989) 24 977,
1947 09:54:40.962507 TX Bit4 (971~995) 25 983, Bit12 (967~991) 25 979,
1948 09:54:40.962772 TX Bit5 (969~993) 25 981, Bit13 (968~990) 23 979,
1949 09:54:40.963033 TX Bit6 (970~994) 25 982, Bit14 (968~991) 24 979,
1950 09:54:40.963294 TX Bit7 (970~996) 27 983, Bit15 (970~994) 25 982,
1951 09:54:40.963580
1952 09:54:40.963843 Write Rank1 MR14 =0x1e
1953 09:54:40.964106
1954 09:54:40.964368 CH=0, VrefRange= 0, VrefLevel = 30
1955 09:54:40.964633 TX Bit0 (974~998) 25 986, Bit8 (965~989) 25 977,
1956 09:54:40.964900 TX Bit1 (972~996) 25 984, Bit9 (967~990) 24 978,
1957 09:54:40.965164 TX Bit2 (974~998) 25 986, Bit10 (970~995) 26 982,
1958 09:54:40.965463 TX Bit3 (967~991) 25 979, Bit11 (966~989) 24 977,
1959 09:54:40.965734 TX Bit4 (970~995) 26 982, Bit12 (967~991) 25 979,
1960 09:54:40.965995 TX Bit5 (968~993) 26 980, Bit13 (968~990) 23 979,
1961 09:54:40.966256 TX Bit6 (969~994) 26 981, Bit14 (968~991) 24 979,
1962 09:54:40.966519 TX Bit7 (970~995) 26 982, Bit15 (970~994) 25 982,
1963 09:54:40.966781
1964 09:54:40.967042 Write Rank1 MR14 =0x20
1965 09:54:40.967301
1966 09:54:40.967580 CH=0, VrefRange= 0, VrefLevel = 32
1967 09:54:40.967844 TX Bit0 (974~998) 25 986, Bit8 (965~989) 25 977,
1968 09:54:40.968105 TX Bit1 (972~996) 25 984, Bit9 (967~990) 24 978,
1969 09:54:40.968406 TX Bit2 (974~998) 25 986, Bit10 (970~995) 26 982,
1970 09:54:40.968671 TX Bit3 (967~991) 25 979, Bit11 (966~989) 24 977,
1971 09:54:40.968935 TX Bit4 (970~995) 26 982, Bit12 (967~991) 25 979,
1972 09:54:40.969196 TX Bit5 (968~993) 26 980, Bit13 (968~990) 23 979,
1973 09:54:40.969456 TX Bit6 (969~994) 26 981, Bit14 (968~991) 24 979,
1974 09:54:40.969720 TX Bit7 (970~995) 26 982, Bit15 (970~994) 25 982,
1975 09:54:40.969982
1976 09:54:40.970239 Write Rank1 MR14 =0x22
1977 09:54:40.970497
1978 09:54:40.970757 CH=0, VrefRange= 0, VrefLevel = 34
1979 09:54:40.971018 TX Bit0 (974~998) 25 986, Bit8 (965~989) 25 977,
1980 09:54:40.971285 TX Bit1 (972~996) 25 984, Bit9 (967~990) 24 978,
1981 09:54:40.971572 TX Bit2 (974~998) 25 986, Bit10 (970~995) 26 982,
1982 09:54:40.971840 TX Bit3 (967~991) 25 979, Bit11 (966~989) 24 977,
1983 09:54:40.972142 TX Bit4 (970~995) 26 982, Bit12 (967~991) 25 979,
1984 09:54:40.972409 TX Bit5 (968~993) 26 980, Bit13 (968~990) 23 979,
1985 09:54:40.972671 TX Bit6 (969~994) 26 981, Bit14 (968~991) 24 979,
1986 09:54:40.972935 TX Bit7 (970~995) 26 982, Bit15 (970~994) 25 982,
1987 09:54:40.973197
1988 09:54:40.973458 Write Rank1 MR14 =0x24
1989 09:54:40.973715
1990 09:54:40.973972 CH=0, VrefRange= 0, VrefLevel = 36
1991 09:54:40.974234 TX Bit0 (974~998) 25 986, Bit8 (965~989) 25 977,
1992 09:54:40.974497 TX Bit1 (972~996) 25 984, Bit9 (967~990) 24 978,
1993 09:54:40.974758 TX Bit2 (974~998) 25 986, Bit10 (970~995) 26 982,
1994 09:54:40.975020 TX Bit3 (967~991) 25 979, Bit11 (966~989) 24 977,
1995 09:54:40.975282 TX Bit4 (970~995) 26 982, Bit12 (967~991) 25 979,
1996 09:54:40.975614 TX Bit5 (968~993) 26 980, Bit13 (968~990) 23 979,
1997 09:54:40.976269 TX Bit6 (969~994) 26 981, Bit14 (968~991) 24 979,
1998 09:54:40.976581 TX Bit7 (970~995) 26 982, Bit15 (970~994) 25 982,
1999 09:54:40.976853
2000 09:54:40.977116 Write Rank1 MR14 =0x26
2001 09:54:40.977381
2002 09:54:40.977656 CH=0, VrefRange= 0, VrefLevel = 38
2003 09:54:40.977841 TX Bit0 (974~998) 25 986, Bit8 (965~989) 25 977,
2004 09:54:40.978031 TX Bit1 (972~996) 25 984, Bit9 (967~990) 24 978,
2005 09:54:40.978252 TX Bit2 (974~998) 25 986, Bit10 (970~995) 26 982,
2006 09:54:40.978444 TX Bit3 (967~991) 25 979, Bit11 (966~989) 24 977,
2007 09:54:40.978631 TX Bit4 (970~995) 26 982, Bit12 (967~991) 25 979,
2008 09:54:40.978820 TX Bit5 (968~993) 26 980, Bit13 (968~990) 23 979,
2009 09:54:40.979007 TX Bit6 (969~994) 26 981, Bit14 (968~991) 24 979,
2010 09:54:40.979193 TX Bit7 (970~995) 26 982, Bit15 (970~994) 25 982,
2011 09:54:40.979379
2012 09:54:40.979589
2013 09:54:40.979774 TX Vref found, early break! 375< 380
2014 09:54:40.979964 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2015 09:54:40.980154 u1DelayCellOfst[0]=9 cells (7 PI)
2016 09:54:40.980342 u1DelayCellOfst[1]=6 cells (5 PI)
2017 09:54:40.980527 u1DelayCellOfst[2]=9 cells (7 PI)
2018 09:54:40.980713 u1DelayCellOfst[3]=0 cells (0 PI)
2019 09:54:40.980899 u1DelayCellOfst[4]=3 cells (3 PI)
2020 09:54:40.981085 u1DelayCellOfst[5]=1 cells (1 PI)
2021 09:54:40.981272 u1DelayCellOfst[6]=2 cells (2 PI)
2022 09:54:40.981458 u1DelayCellOfst[7]=3 cells (3 PI)
2023 09:54:40.981643 Byte0, DQ PI dly=979, DQM PI dly= 982
2024 09:54:40.981830 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
2025 09:54:40.982019
2026 09:54:40.982236 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
2027 09:54:40.982427
2028 09:54:40.982611 u1DelayCellOfst[8]=0 cells (0 PI)
2029 09:54:40.982784 u1DelayCellOfst[9]=1 cells (1 PI)
2030 09:54:40.982923 u1DelayCellOfst[10]=6 cells (5 PI)
2031 09:54:40.983064 u1DelayCellOfst[11]=0 cells (0 PI)
2032 09:54:40.983206 u1DelayCellOfst[12]=2 cells (2 PI)
2033 09:54:40.983347 u1DelayCellOfst[13]=2 cells (2 PI)
2034 09:54:40.983501 u1DelayCellOfst[14]=2 cells (2 PI)
2035 09:54:40.983643 u1DelayCellOfst[15]=6 cells (5 PI)
2036 09:54:40.983789 Byte1, DQ PI dly=977, DQM PI dly= 979
2037 09:54:40.983932 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
2038 09:54:40.984075
2039 09:54:40.984216 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
2040 09:54:40.984357
2041 09:54:40.984497 Write Rank1 MR14 =0x1e
2042 09:54:40.984637
2043 09:54:40.984777 Final TX Range 0 Vref 30
2044 09:54:40.984919
2045 09:54:40.985059 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2046 09:54:40.985202
2047 09:54:40.985412 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2048 09:54:40.985566 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2049 09:54:40.985710 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2050 09:54:40.985854 wait MRW command Rank1 MR3 =0xb0 fired (1)
2051 09:54:40.985996 Write Rank1 MR3 =0xb0
2052 09:54:40.986138 DramC Write-DBI on
2053 09:54:40.986278 ==
2054 09:54:40.986419 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2055 09:54:40.986559 fsp= 1, odt_onoff= 1, Byte mode= 0
2056 09:54:40.986700 ==
2057 09:54:40.986840 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2058 09:54:40.986981
2059 09:54:40.987120 Begin, DQ Scan Range 699~763
2060 09:54:40.987260
2061 09:54:40.987399
2062 09:54:40.987551 TX Vref Scan disable
2063 09:54:40.987699 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2064 09:54:40.987815 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2065 09:54:40.987930 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2066 09:54:40.988044 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2067 09:54:40.988173 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2068 09:54:40.988290 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2069 09:54:40.988406 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2070 09:54:40.988521 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2071 09:54:40.988636 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2072 09:54:40.988752 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2073 09:54:40.988866 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2074 09:54:40.988982 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2075 09:54:40.989097 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2076 09:54:40.989213 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2077 09:54:40.989328 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2078 09:54:40.989441 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2079 09:54:40.989557 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
2080 09:54:40.989672 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2081 09:54:40.989788 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2082 09:54:40.989903 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2083 09:54:40.990018 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2084 09:54:40.990133 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2085 09:54:40.990247 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2086 09:54:40.990362 742 |2 6 38|[0] xxxxxxxx xxxxxxxx [MSB]
2087 09:54:40.990477 Byte0, DQ PI dly=728, DQM PI dly= 728
2088 09:54:40.990590 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
2089 09:54:40.990705
2090 09:54:40.990819 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
2091 09:54:40.990933
2092 09:54:40.991047 Byte1, DQ PI dly=722, DQM PI dly= 722
2093 09:54:40.991160 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 18)
2094 09:54:40.991274
2095 09:54:40.991386 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 18)
2096 09:54:40.991515
2097 09:54:40.991627 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2098 09:54:40.991741 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2099 09:54:40.991870 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2100 09:54:40.991988 Write Rank1 MR3 =0x30
2101 09:54:40.992101 DramC Write-DBI off
2102 09:54:40.992214
2103 09:54:40.992327 [DATLAT]
2104 09:54:40.992440 Freq=1600, CH0 RK1, use_rxtx_scan=0
2105 09:54:40.992555
2106 09:54:40.992676 DATLAT Default: 0x10
2107 09:54:40.992772 7, 0xFFFF, sum=0
2108 09:54:40.992868 8, 0xFFFF, sum=0
2109 09:54:40.992964 9, 0xFFFF, sum=0
2110 09:54:40.993060 10, 0xFFFF, sum=0
2111 09:54:40.993158 11, 0xFFFF, sum=0
2112 09:54:40.993254 12, 0xFFFF, sum=0
2113 09:54:40.993351 13, 0xFFFF, sum=0
2114 09:54:40.993447 14, 0x0, sum=1
2115 09:54:40.993544 15, 0x0, sum=2
2116 09:54:40.993640 16, 0x0, sum=3
2117 09:54:40.993735 17, 0x0, sum=4
2118 09:54:40.993830 pattern=2 first_step=14 total pass=5 best_step=16
2119 09:54:40.993925 ==
2120 09:54:40.994019 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2121 09:54:40.994344 fsp= 1, odt_onoff= 1, Byte mode= 0
2122 09:54:40.994451 ==
2123 09:54:40.994549 Start DQ dly to find pass range UseTestEngine =1
2124 09:54:40.994645 x-axis: bit #, y-axis: DQ dly (-127~63)
2125 09:54:40.994741 RX Vref Scan = 0
2126 09:54:40.994838 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2127 09:54:40.994936 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2128 09:54:40.995033 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2129 09:54:40.995130 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2130 09:54:40.995243 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2131 09:54:40.995341 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2132 09:54:40.995453 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2133 09:54:40.995551 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2134 09:54:40.995648 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2135 09:54:40.995744 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2136 09:54:40.995840 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2137 09:54:40.995937 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2138 09:54:40.996033 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2139 09:54:40.996129 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2140 09:54:40.996225 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2141 09:54:40.996322 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2142 09:54:40.996418 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2143 09:54:40.996515 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2144 09:54:40.996612 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2145 09:54:40.996709 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2146 09:54:40.996807 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2147 09:54:40.996903 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2148 09:54:40.997000 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2149 09:54:40.997096 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2150 09:54:40.997193 -2, [0] xxxoxxxx oxxoxxxx [MSB]
2151 09:54:40.997289 -1, [0] xxxoxxxx oxxoxxxx [MSB]
2152 09:54:40.997385 0, [0] xxxoxxxx oxxoxxxx [MSB]
2153 09:54:40.997482 1, [0] xxxoxoxx ooxooxxx [MSB]
2154 09:54:40.997578 2, [0] xxxoxoxx ooxoooox [MSB]
2155 09:54:40.997685 3, [0] xxxoxooo ooxoooox [MSB]
2156 09:54:40.997767 4, [0] xxxoxooo ooxoooox [MSB]
2157 09:54:40.997871 5, [0] ooxooooo ooxoooox [MSB]
2158 09:54:40.997955 6, [0] oooooooo ooxooooo [MSB]
2159 09:54:40.998038 33, [0] oooooooo xooooooo [MSB]
2160 09:54:40.998121 34, [0] oooxoooo xooooooo [MSB]
2161 09:54:40.998205 35, [0] oooxoxoo xooxoooo [MSB]
2162 09:54:40.998286 36, [0] oooxoxoo xooxoxoo [MSB]
2163 09:54:40.998382 37, [0] oooxoxoo xxoxoxoo [MSB]
2164 09:54:40.998466 38, [0] oooxoxxo xxoxxxoo [MSB]
2165 09:54:40.998549 39, [0] oxxxoxxx xxoxxxxo [MSB]
2166 09:54:40.998631 40, [0] oxxxxxxx xxoxxxxx [MSB]
2167 09:54:40.998713 41, [0] xxxxxxxx xxoxxxxx [MSB]
2168 09:54:40.998796 42, [0] xxxxxxxx xxoxxxxx [MSB]
2169 09:54:40.998879 43, [0] xxxxxxxx xxoxxxxx [MSB]
2170 09:54:40.998961 44, [0] xxxxxxxx xxxxxxxx [MSB]
2171 09:54:40.999045 iDelay=44, Bit 0, Center 22 (5 ~ 40) 36
2172 09:54:40.999127 iDelay=44, Bit 1, Center 21 (5 ~ 38) 34
2173 09:54:40.999209 iDelay=44, Bit 2, Center 22 (6 ~ 38) 33
2174 09:54:40.999290 iDelay=44, Bit 3, Center 15 (-2 ~ 33) 36
2175 09:54:40.999372 iDelay=44, Bit 4, Center 22 (5 ~ 39) 35
2176 09:54:40.999461 iDelay=44, Bit 5, Center 17 (1 ~ 34) 34
2177 09:54:40.999543 iDelay=44, Bit 6, Center 20 (3 ~ 37) 35
2178 09:54:40.999623 iDelay=44, Bit 7, Center 20 (3 ~ 38) 36
2179 09:54:40.999705 iDelay=44, Bit 8, Center 15 (-2 ~ 32) 35
2180 09:54:40.999790 iDelay=44, Bit 9, Center 18 (1 ~ 36) 36
2181 09:54:40.999880 iDelay=44, Bit 10, Center 25 (7 ~ 43) 37
2182 09:54:40.999961 iDelay=44, Bit 11, Center 16 (-2 ~ 34) 37
2183 09:54:41.000043 iDelay=44, Bit 12, Center 19 (1 ~ 37) 37
2184 09:54:41.000124 iDelay=44, Bit 13, Center 18 (2 ~ 35) 34
2185 09:54:41.000205 iDelay=44, Bit 14, Center 20 (2 ~ 38) 37
2186 09:54:41.000286 iDelay=44, Bit 15, Center 22 (6 ~ 39) 34
2187 09:54:41.000367 ==
2188 09:54:41.000448 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2189 09:54:41.000530 fsp= 1, odt_onoff= 1, Byte mode= 0
2190 09:54:41.000612 ==
2191 09:54:41.000693 DQS Delay:
2192 09:54:41.000774 DQS0 = 0, DQS1 = 0
2193 09:54:41.000855 DQM Delay:
2194 09:54:41.000937 DQM0 = 19, DQM1 = 19
2195 09:54:41.001018 DQ Delay:
2196 09:54:41.001099 DQ0 =22, DQ1 =21, DQ2 =22, DQ3 =15
2197 09:54:41.001181 DQ4 =22, DQ5 =17, DQ6 =20, DQ7 =20
2198 09:54:41.001262 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =16
2199 09:54:41.001343 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
2200 09:54:41.001424
2201 09:54:41.001504
2202 09:54:41.001584
2203 09:54:41.001664 [DramC_TX_OE_Calibration] TA2
2204 09:54:41.001745 Original DQ_B0 (3 6) =30, OEN = 27
2205 09:54:41.001842 Original DQ_B1 (3 6) =30, OEN = 27
2206 09:54:41.001933 23, 0x0, End_B0=23 End_B1=23
2207 09:54:41.002029 24, 0x0, End_B0=24 End_B1=24
2208 09:54:41.002112 25, 0x0, End_B0=25 End_B1=25
2209 09:54:41.002194 26, 0x0, End_B0=26 End_B1=26
2210 09:54:41.002277 27, 0x0, End_B0=27 End_B1=27
2211 09:54:41.002360 28, 0x0, End_B0=28 End_B1=28
2212 09:54:41.002442 29, 0x0, End_B0=29 End_B1=29
2213 09:54:41.002525 30, 0x0, End_B0=30 End_B1=30
2214 09:54:41.002607 31, 0xFFFF, End_B0=30 End_B1=30
2215 09:54:41.002702 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2216 09:54:41.002775 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2217 09:54:41.002846
2218 09:54:41.002916
2219 09:54:41.002986 Write Rank1 MR23 =0x3f
2220 09:54:41.003057 [DQSOSC]
2221 09:54:41.003129 [DQSOSCAuto] RK1, (LSB)MR18= 0xd8d8, (MSB)MR19= 0x202, tDQSOscB0 = 432 ps tDQSOscB1 = 432 ps
2222 09:54:41.003202 CH0_RK1: MR19=0x202, MR18=0xD8D8, DQSOSC=432, MR23=63, INC=13, DEC=19
2223 09:54:41.003274 Write Rank1 MR23 =0x3f
2224 09:54:41.003345 [DQSOSC]
2225 09:54:41.003425 [DQSOSCAuto] RK1, (LSB)MR18= 0xd8d8, (MSB)MR19= 0x202, tDQSOscB0 = 432 ps tDQSOscB1 = 432 ps
2226 09:54:41.003498 CH0 RK1: MR19=202, MR18=D8D8
2227 09:54:41.003569 [RxdqsGatingPostProcess] freq 1600
2228 09:54:41.003641 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2229 09:54:41.003713 Rank: 0
2230 09:54:41.003784 best DQS0 dly(2T, 0.5T) = (2, 5)
2231 09:54:41.003855 best DQS1 dly(2T, 0.5T) = (2, 5)
2232 09:54:41.003931 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2233 09:54:41.004018 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2234 09:54:41.004091 Rank: 1
2235 09:54:41.004162 best DQS0 dly(2T, 0.5T) = (2, 6)
2236 09:54:41.004233 best DQS1 dly(2T, 0.5T) = (2, 6)
2237 09:54:41.004304 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2238 09:54:41.004376 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2239 09:54:41.004447 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2240 09:54:41.004520 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2241 09:54:41.004591 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2242 09:54:41.004664 Write Rank0 MR13 =0x59
2243 09:54:41.004735 ==
2244 09:54:41.005008 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2245 09:54:41.005088 fsp= 1, odt_onoff= 1, Byte mode= 0
2246 09:54:41.005175 ==
2247 09:54:41.005248 === u2Vref_new: 0x56 --> 0x3a
2248 09:54:41.005320 === u2Vref_new: 0x58 --> 0x58
2249 09:54:41.005407 === u2Vref_new: 0x5a --> 0x5a
2250 09:54:41.008522 === u2Vref_new: 0x5c --> 0x78
2251 09:54:41.008622 === u2Vref_new: 0x5e --> 0x7a
2252 09:54:41.012569 === u2Vref_new: 0x60 --> 0x90
2253 09:54:41.015551 [CA 0] Center 38 (13~63) winsize 51
2254 09:54:41.019131 [CA 1] Center 37 (11~63) winsize 53
2255 09:54:41.022369 [CA 2] Center 35 (7~63) winsize 57
2256 09:54:41.025587 [CA 3] Center 34 (6~63) winsize 58
2257 09:54:41.029461 [CA 4] Center 34 (6~63) winsize 58
2258 09:54:41.032548 [CA 5] Center 28 (-2~58) winsize 61
2259 09:54:41.032713
2260 09:54:41.035976 [CATrainingPosCal] consider 1 rank data
2261 09:54:41.039323 u2DelayCellTimex100 = 735/100 ps
2262 09:54:41.042490 CA0 delay=38 (13~63),Diff = 10 PI (13 cell)
2263 09:54:41.045532 CA1 delay=37 (11~63),Diff = 9 PI (11 cell)
2264 09:54:41.048845 CA2 delay=35 (7~63),Diff = 7 PI (9 cell)
2265 09:54:41.055690 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2266 09:54:41.059200 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2267 09:54:41.062764 CA5 delay=28 (-2~58),Diff = 0 PI (0 cell)
2268 09:54:41.062968
2269 09:54:41.065819 CA PerBit enable=1, Macro0, CA PI delay=28
2270 09:54:41.069178 === u2Vref_new: 0x5e --> 0x7a
2271 09:54:41.069407
2272 09:54:41.069533 Vref(ca) range 1: 30
2273 09:54:41.069643
2274 09:54:41.072576 CS Dly= 11 (42-0-32)
2275 09:54:41.076092 Write Rank0 MR13 =0xd8
2276 09:54:41.076336 Write Rank0 MR13 =0xd8
2277 09:54:41.079529 Write Rank0 MR12 =0x5e
2278 09:54:41.079800 Write Rank1 MR13 =0x59
2279 09:54:41.082925 ==
2280 09:54:41.086111 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2281 09:54:41.089603 fsp= 1, odt_onoff= 1, Byte mode= 0
2282 09:54:41.089963 ==
2283 09:54:41.092750 === u2Vref_new: 0x56 --> 0x3a
2284 09:54:41.096218 === u2Vref_new: 0x58 --> 0x58
2285 09:54:41.099636 === u2Vref_new: 0x5a --> 0x5a
2286 09:54:41.102934 === u2Vref_new: 0x5c --> 0x78
2287 09:54:41.106126 === u2Vref_new: 0x5e --> 0x7a
2288 09:54:41.109788 === u2Vref_new: 0x60 --> 0x90
2289 09:54:41.112494 [CA 0] Center 37 (12~63) winsize 52
2290 09:54:41.116124 [CA 1] Center 38 (13~63) winsize 51
2291 09:54:41.116674 [CA 2] Center 35 (7~63) winsize 57
2292 09:54:41.119199 [CA 3] Center 35 (7~63) winsize 57
2293 09:54:41.122833 [CA 4] Center 35 (7~63) winsize 57
2294 09:54:41.125947 [CA 5] Center 27 (-2~57) winsize 60
2295 09:54:41.126357
2296 09:54:41.129515 [CATrainingPosCal] consider 2 rank data
2297 09:54:41.132536 u2DelayCellTimex100 = 735/100 ps
2298 09:54:41.135884 CA0 delay=38 (13~63),Diff = 11 PI (14 cell)
2299 09:54:41.142491 CA1 delay=38 (13~63),Diff = 11 PI (14 cell)
2300 09:54:41.146024 CA2 delay=35 (7~63),Diff = 8 PI (10 cell)
2301 09:54:41.149614 CA3 delay=35 (7~63),Diff = 8 PI (10 cell)
2302 09:54:41.152663 CA4 delay=35 (7~63),Diff = 8 PI (10 cell)
2303 09:54:41.155949 CA5 delay=27 (-2~57),Diff = 0 PI (0 cell)
2304 09:54:41.156355
2305 09:54:41.159599 CA PerBit enable=1, Macro0, CA PI delay=27
2306 09:54:41.163025 === u2Vref_new: 0x60 --> 0x90
2307 09:54:41.163591
2308 09:54:41.166208 Vref(ca) range 1: 32
2309 09:54:41.166775
2310 09:54:41.167303 CS Dly= 11 (42-0-32)
2311 09:54:41.169717 Write Rank1 MR13 =0xd8
2312 09:54:41.172428 Write Rank1 MR13 =0xd8
2313 09:54:41.172886 Write Rank1 MR12 =0x60
2314 09:54:41.176144 [RankSwap] Rank num 2, (Multi 1), Rank 0
2315 09:54:41.179240 Write Rank0 MR2 =0xad
2316 09:54:41.179687 [Write Leveling]
2317 09:54:41.182942 delay byte0 byte1 byte2 byte3
2318 09:54:41.183518
2319 09:54:41.185872 10 0 0
2320 09:54:41.186288 11 0 0
2321 09:54:41.189147 12 0 0
2322 09:54:41.189559 13 0 0
2323 09:54:41.189885 14 0 0
2324 09:54:41.192787 15 0 0
2325 09:54:41.193303 16 0 0
2326 09:54:41.195968 17 0 0
2327 09:54:41.196381 18 0 0
2328 09:54:41.196708 19 0 0
2329 09:54:41.199698 20 0 0
2330 09:54:41.200208 21 0 0
2331 09:54:41.202911 22 0 0
2332 09:54:41.203462 23 0 ff
2333 09:54:41.203925 24 0 ff
2334 09:54:41.206141 25 0 ff
2335 09:54:41.206553 26 0 ff
2336 09:54:41.209620 27 0 ff
2337 09:54:41.210141 28 0 ff
2338 09:54:41.212774 29 0 ff
2339 09:54:41.213197 30 0 ff
2340 09:54:41.216501 31 0 ff
2341 09:54:41.217013 32 ff ff
2342 09:54:41.217342 33 ff ff
2343 09:54:41.219877 34 ff ff
2344 09:54:41.220409 35 ff ff
2345 09:54:41.223286 36 ff ff
2346 09:54:41.223854 37 ff ff
2347 09:54:41.226903 38 ff ff
2348 09:54:41.229964 pass bytecount = 0xff (0xff: all bytes pass)
2349 09:54:41.230478
2350 09:54:41.230810 DQS0 dly: 32
2351 09:54:41.233496 DQS1 dly: 23
2352 09:54:41.234065 Write Rank0 MR2 =0x2d
2353 09:54:41.237084 [RankSwap] Rank num 2, (Multi 1), Rank 0
2354 09:54:41.239896 Write Rank0 MR1 =0xd6
2355 09:54:41.240456 [Gating]
2356 09:54:41.240817 ==
2357 09:54:41.246687 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2358 09:54:41.250369 fsp= 1, odt_onoff= 1, Byte mode= 0
2359 09:54:41.250926 ==
2360 09:54:41.253041 3 1 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2361 09:54:41.256855 3 1 4 |1313 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2362 09:54:41.263085 3 1 8 |d0c 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2363 09:54:41.267024 3 1 12 |3534 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2364 09:54:41.270115 3 1 16 |3535 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2365 09:54:41.276969 [Byte 1] Lead/lag falling Transition (3, 1, 16)
2366 09:54:41.280140 3 1 20 |3434 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2367 09:54:41.283731 3 1 24 |3535 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2368 09:54:41.290169 3 1 28 |3534 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2369 09:54:41.293144 [Byte 0] Lead/lag falling Transition (3, 1, 28)
2370 09:54:41.296625 3 2 0 |3434 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2371 09:54:41.299895 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2372 09:54:41.306976 3 2 8 |504 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2373 09:54:41.310309 3 2 12 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2374 09:54:41.313630 3 2 16 |3434 2c2b |(0 11)(11 11) |(1 1)(1 0)| 0
2375 09:54:41.320302 3 2 20 |3d3d 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2376 09:54:41.323973 [Byte 1] Lead/lag Transition tap number (10)
2377 09:54:41.327056 3 2 24 |707 2625 |(11 11)(11 11) |(1 1)(0 0)| 0
2378 09:54:41.330123 3 2 28 |3b3b 606 |(11 11)(11 11) |(1 1)(0 0)| 0
2379 09:54:41.336952 3 3 0 |3d3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2380 09:54:41.340411 3 3 4 |3c3c 3534 |(10 10)(11 11) |(1 1)(0 0)| 0
2381 09:54:41.343859 3 3 8 |2c2b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2382 09:54:41.346992 [Byte 0] Lead/lag Transition tap number (1)
2383 09:54:41.353316 3 3 12 |3c3b 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
2384 09:54:41.356604 3 3 16 |c0c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2385 09:54:41.360445 3 3 20 |201 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2386 09:54:41.366790 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2387 09:54:41.370526 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2388 09:54:41.373568 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2389 09:54:41.376960 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2390 09:54:41.383936 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2391 09:54:41.386911 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2392 09:54:41.390572 3 4 16 |2322 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2393 09:54:41.396592 3 4 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2394 09:54:41.400035 3 4 24 |3d3d 1716 |(11 11)(11 11) |(1 1)(0 1)| 0
2395 09:54:41.403506 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2396 09:54:41.410656 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2397 09:54:41.413774 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2398 09:54:41.417047 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2399 09:54:41.420231 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2400 09:54:41.427771 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2401 09:54:41.431046 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2402 09:54:41.434240 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2403 09:54:41.440685 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2404 09:54:41.443976 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2405 09:54:41.447526 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2406 09:54:41.454219 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2407 09:54:41.456974 [Byte 0] Lead/lag falling Transition (3, 6, 8)
2408 09:54:41.460703 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2409 09:54:41.464075 [Byte 0] Lead/lag Transition tap number (2)
2410 09:54:41.470784 3 6 16 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2411 09:54:41.473821 [Byte 1] Lead/lag falling Transition (3, 6, 16)
2412 09:54:41.477157 3 6 20 |606 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2413 09:54:41.480236 [Byte 1] Lead/lag Transition tap number (2)
2414 09:54:41.486938 3 6 24 |4646 3d3d |(0 0)(11 11) |(0 0)(0 0)| 0
2415 09:54:41.487364 [Byte 0]First pass (3, 6, 24)
2416 09:54:41.493739 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2417 09:54:41.494164 [Byte 1]First pass (3, 6, 28)
2418 09:54:41.500297 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2419 09:54:41.503678 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2420 09:54:41.506791 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2421 09:54:41.510161 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2422 09:54:41.513279 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2423 09:54:41.520137 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2424 09:54:41.523247 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2425 09:54:41.526797 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2426 09:54:41.530165 All bytes gating window > 1UI, Early break!
2427 09:54:41.530699
2428 09:54:41.533570 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
2429 09:54:41.537016
2430 09:54:41.540085 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 20)
2431 09:54:41.540502
2432 09:54:41.540826
2433 09:54:41.541130
2434 09:54:41.543546 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
2435 09:54:41.544064
2436 09:54:41.546580 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 20)
2437 09:54:41.547162
2438 09:54:41.547542
2439 09:54:41.549984 Write Rank0 MR1 =0x56
2440 09:54:41.550565
2441 09:54:41.553695 best RODT dly(2T, 0.5T) = (2, 3)
2442 09:54:41.554212
2443 09:54:41.556343 best RODT dly(2T, 0.5T) = (2, 3)
2444 09:54:41.556757 ==
2445 09:54:41.560097 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2446 09:54:41.563322 fsp= 1, odt_onoff= 1, Byte mode= 0
2447 09:54:41.563919 ==
2448 09:54:41.569539 Start DQ dly to find pass range UseTestEngine =0
2449 09:54:41.573272 x-axis: bit #, y-axis: DQ dly (-127~63)
2450 09:54:41.573812 RX Vref Scan = 0
2451 09:54:41.576375 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2452 09:54:41.579806 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2453 09:54:41.583199 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2454 09:54:41.586792 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2455 09:54:41.590344 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2456 09:54:41.590905 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2457 09:54:41.593214 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2458 09:54:41.596316 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2459 09:54:41.599875 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2460 09:54:41.603896 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2461 09:54:41.606954 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2462 09:54:41.610219 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2463 09:54:41.613513 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2464 09:54:41.616856 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2465 09:54:41.617452 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2466 09:54:41.619589 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2467 09:54:41.623085 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2468 09:54:41.626609 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2469 09:54:41.629644 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2470 09:54:41.632639 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2471 09:54:41.636421 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2472 09:54:41.639890 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2473 09:54:41.640559 -4, [0] xxxxxxxx xxxxxxxo [MSB]
2474 09:54:41.642926 -3, [0] xxxxxxxx xoxxxxxo [MSB]
2475 09:54:41.646177 -2, [0] xxxxxxxx xoxxxxxo [MSB]
2476 09:54:41.649461 -1, [0] xxxoxxxx xoxxxxxo [MSB]
2477 09:54:41.653040 0, [0] xxxoxxxx ooxxxxxo [MSB]
2478 09:54:41.656354 1, [0] xxooxxxx oooxxxxo [MSB]
2479 09:54:41.656968 2, [0] xxooxxxx oooxxxxo [MSB]
2480 09:54:41.659927 3, [0] xxooxxxx oooxxxxo [MSB]
2481 09:54:41.662906 4, [0] oxooxxxo ooooooxo [MSB]
2482 09:54:41.665812 5, [0] oooooxoo oooooooo [MSB]
2483 09:54:41.669733 32, [0] oooooooo ooooooox [MSB]
2484 09:54:41.672827 33, [0] oooooooo ooooooox [MSB]
2485 09:54:41.675771 34, [0] oooooooo ooooooox [MSB]
2486 09:54:41.676213 35, [0] oooxoooo xxooooox [MSB]
2487 09:54:41.679498 36, [0] oooxoooo xxooooox [MSB]
2488 09:54:41.682600 37, [0] ooxxoooo xxooooox [MSB]
2489 09:54:41.685846 38, [0] ooxxoooo xxooooox [MSB]
2490 09:54:41.688969 39, [0] ooxxooox xxooooox [MSB]
2491 09:54:41.692852 40, [0] oxxxxoox xxxoooox [MSB]
2492 09:54:41.696105 41, [0] xxxxxoox xxxxxxxx [MSB]
2493 09:54:41.696550 42, [0] xxxxxxxx xxxxxxxx [MSB]
2494 09:54:41.699124 iDelay=42, Bit 0, Center 22 (4 ~ 40) 37
2495 09:54:41.706088 iDelay=42, Bit 1, Center 22 (5 ~ 39) 35
2496 09:54:41.709600 iDelay=42, Bit 2, Center 18 (1 ~ 36) 36
2497 09:54:41.712968 iDelay=42, Bit 3, Center 16 (-1 ~ 34) 36
2498 09:54:41.716148 iDelay=42, Bit 4, Center 22 (5 ~ 39) 35
2499 09:54:41.719580 iDelay=42, Bit 5, Center 23 (6 ~ 41) 36
2500 09:54:41.722617 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
2501 09:54:41.726266 iDelay=42, Bit 7, Center 21 (4 ~ 38) 35
2502 09:54:41.729579 iDelay=42, Bit 8, Center 17 (0 ~ 34) 35
2503 09:54:41.732720 iDelay=42, Bit 9, Center 15 (-3 ~ 34) 38
2504 09:54:41.736142 iDelay=42, Bit 10, Center 20 (1 ~ 39) 39
2505 09:54:41.739203 iDelay=42, Bit 11, Center 22 (4 ~ 40) 37
2506 09:54:41.742787 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
2507 09:54:41.745651 iDelay=42, Bit 13, Center 22 (4 ~ 40) 37
2508 09:54:41.752836 iDelay=42, Bit 14, Center 22 (5 ~ 40) 36
2509 09:54:41.755607 iDelay=42, Bit 15, Center 13 (-4 ~ 31) 36
2510 09:54:41.756150 ==
2511 09:54:41.759186 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2512 09:54:41.762468 fsp= 1, odt_onoff= 1, Byte mode= 0
2513 09:54:41.763086 ==
2514 09:54:41.766031 DQS Delay:
2515 09:54:41.766611 DQS0 = 0, DQS1 = 0
2516 09:54:41.767101 DQM Delay:
2517 09:54:41.769455 DQM0 = 20, DQM1 = 19
2518 09:54:41.770019 DQ Delay:
2519 09:54:41.772377 DQ0 =22, DQ1 =22, DQ2 =18, DQ3 =16
2520 09:54:41.775883 DQ4 =22, DQ5 =23, DQ6 =23, DQ7 =21
2521 09:54:41.779087 DQ8 =17, DQ9 =15, DQ10 =20, DQ11 =22
2522 09:54:41.782817 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =13
2523 09:54:41.783367
2524 09:54:41.783782
2525 09:54:41.785524 DramC Write-DBI off
2526 09:54:41.785985 ==
2527 09:54:41.788859 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2528 09:54:41.792131 fsp= 1, odt_onoff= 1, Byte mode= 0
2529 09:54:41.792555 ==
2530 09:54:41.799209 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2531 09:54:41.799819
2532 09:54:41.800163 Begin, DQ Scan Range 919~1175
2533 09:54:41.802507
2534 09:54:41.803011
2535 09:54:41.803344 TX Vref Scan disable
2536 09:54:41.805895 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB]
2537 09:54:41.809201 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
2538 09:54:41.812639 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
2539 09:54:41.816067 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
2540 09:54:41.822877 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
2541 09:54:41.826253 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
2542 09:54:41.829656 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
2543 09:54:41.832743 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
2544 09:54:41.835922 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2545 09:54:41.839457 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2546 09:54:41.842337 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2547 09:54:41.846168 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2548 09:54:41.849327 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2549 09:54:41.852561 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2550 09:54:41.856169 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2551 09:54:41.859115 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2552 09:54:41.862469 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2553 09:54:41.865853 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2554 09:54:41.869053 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2555 09:54:41.872462 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2556 09:54:41.875801 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2557 09:54:41.882518 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2558 09:54:41.885972 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2559 09:54:41.889014 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2560 09:54:41.892471 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2561 09:54:41.895558 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2562 09:54:41.898777 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2563 09:54:41.902752 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2564 09:54:41.905796 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2565 09:54:41.909013 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2566 09:54:41.912315 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2567 09:54:41.915772 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2568 09:54:41.919184 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2569 09:54:41.922450 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2570 09:54:41.925847 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2571 09:54:41.928654 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2572 09:54:41.932608 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2573 09:54:41.939018 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2574 09:54:41.942306 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2575 09:54:41.945614 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2576 09:54:41.948553 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2577 09:54:41.952354 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2578 09:54:41.955329 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2579 09:54:41.958432 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2580 09:54:41.961964 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2581 09:54:41.965423 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2582 09:54:41.968407 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2583 09:54:41.971801 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2584 09:54:41.974892 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2585 09:54:41.978594 968 |3 6 8|[0] xxxxxxxx xxxxxxxo [MSB]
2586 09:54:41.981649 969 |3 6 9|[0] xxxxxxxx ooxxxxxo [MSB]
2587 09:54:41.985040 970 |3 6 10|[0] xxxxxxxx oooxxxoo [MSB]
2588 09:54:41.988036 971 |3 6 11|[0] xxxxxxxx oooooxoo [MSB]
2589 09:54:41.991559 972 |3 6 12|[0] xxxxxxxx oooooxoo [MSB]
2590 09:54:41.995138 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
2591 09:54:42.001793 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
2592 09:54:42.004641 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
2593 09:54:42.007967 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
2594 09:54:42.011556 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
2595 09:54:42.014727 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
2596 09:54:42.018179 979 |3 6 19|[0] xooooxoo oooooooo [MSB]
2597 09:54:42.021373 980 |3 6 20|[0] oooooxoo oooooooo [MSB]
2598 09:54:42.024885 985 |3 6 25|[0] oooooooo ooooooox [MSB]
2599 09:54:42.028001 986 |3 6 26|[0] oooooooo oxooooox [MSB]
2600 09:54:42.031550 987 |3 6 27|[0] oooooooo oxooooox [MSB]
2601 09:54:42.034545 988 |3 6 28|[0] oooooooo xxooooox [MSB]
2602 09:54:42.038149 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
2603 09:54:42.044795 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
2604 09:54:42.048012 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
2605 09:54:42.051322 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2606 09:54:42.054989 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2607 09:54:42.057923 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2608 09:54:42.061202 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
2609 09:54:42.064654 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
2610 09:54:42.068287 997 |3 6 37|[0] oooxoooo xxxxxxxx [MSB]
2611 09:54:42.071586 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
2612 09:54:42.074998 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
2613 09:54:42.077685 1000 |3 6 40|[0] ooxxooox xxxxxxxx [MSB]
2614 09:54:42.081509 1001 |3 6 41|[0] xxxxxxxx xxxxxxxx [MSB]
2615 09:54:42.084523 Byte0, DQ PI dly=988, DQM PI dly= 988
2616 09:54:42.090841 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 28)
2617 09:54:42.091309
2618 09:54:42.094489 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 28)
2619 09:54:42.095058
2620 09:54:42.097530 Byte1, DQ PI dly=978, DQM PI dly= 978
2621 09:54:42.100943 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
2622 09:54:42.101656
2623 09:54:42.107463 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
2624 09:54:42.107932
2625 09:54:42.108306 ==
2626 09:54:42.111138 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2627 09:54:42.114239 fsp= 1, odt_onoff= 1, Byte mode= 0
2628 09:54:42.114790 ==
2629 09:54:42.121320 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2630 09:54:42.121864
2631 09:54:42.122411 Begin, DQ Scan Range 954~1018
2632 09:54:42.124222 Write Rank0 MR14 =0x0
2633 09:54:42.133421
2634 09:54:42.133975 CH=1, VrefRange= 0, VrefLevel = 0
2635 09:54:42.140428 TX Bit0 (983~998) 16 990, Bit8 (971~983) 13 977,
2636 09:54:42.143057 TX Bit1 (982~994) 13 988, Bit9 (971~982) 12 976,
2637 09:54:42.149744 TX Bit2 (980~993) 14 986, Bit10 (974~985) 12 979,
2638 09:54:42.153170 TX Bit3 (978~991) 14 984, Bit11 (975~986) 12 980,
2639 09:54:42.156578 TX Bit4 (982~995) 14 988, Bit12 (973~986) 14 979,
2640 09:54:42.163163 TX Bit5 (984~996) 13 990, Bit13 (975~986) 12 980,
2641 09:54:42.166368 TX Bit6 (983~995) 13 989, Bit14 (973~985) 13 979,
2642 09:54:42.172947 TX Bit7 (982~994) 13 988, Bit15 (968~978) 11 973,
2643 09:54:42.173512
2644 09:54:42.173874 Write Rank0 MR14 =0x2
2645 09:54:42.182621
2646 09:54:42.183167 CH=1, VrefRange= 0, VrefLevel = 2
2647 09:54:42.188896 TX Bit0 (983~999) 17 991, Bit8 (970~983) 14 976,
2648 09:54:42.192556 TX Bit1 (982~994) 13 988, Bit9 (971~983) 13 977,
2649 09:54:42.198559 TX Bit2 (979~994) 16 986, Bit10 (973~986) 14 979,
2650 09:54:42.201778 TX Bit3 (978~992) 15 985, Bit11 (975~987) 13 981,
2651 09:54:42.205894 TX Bit4 (982~996) 15 989, Bit12 (974~987) 14 980,
2652 09:54:42.211885 TX Bit5 (984~996) 13 990, Bit13 (975~987) 13 981,
2653 09:54:42.215453 TX Bit6 (982~995) 14 988, Bit14 (972~985) 14 978,
2654 09:54:42.218799 TX Bit7 (982~995) 14 988, Bit15 (968~979) 12 973,
2655 09:54:42.219325
2656 09:54:42.222060 Write Rank0 MR14 =0x4
2657 09:54:42.231479
2658 09:54:42.232034 CH=1, VrefRange= 0, VrefLevel = 4
2659 09:54:42.238290 TX Bit0 (983~999) 17 991, Bit8 (970~984) 15 977,
2660 09:54:42.241281 TX Bit1 (981~995) 15 988, Bit9 (970~983) 14 976,
2661 09:54:42.247890 TX Bit2 (979~994) 16 986, Bit10 (972~986) 15 979,
2662 09:54:42.251588 TX Bit3 (977~992) 16 984, Bit11 (974~987) 14 980,
2663 09:54:42.254296 TX Bit4 (981~997) 17 989, Bit12 (973~988) 16 980,
2664 09:54:42.260930 TX Bit5 (983~998) 16 990, Bit13 (975~988) 14 981,
2665 09:54:42.264443 TX Bit6 (982~997) 16 989, Bit14 (972~986) 15 979,
2666 09:54:42.268004 TX Bit7 (981~996) 16 988, Bit15 (968~979) 12 973,
2667 09:54:42.271531
2668 09:54:42.272086 Write Rank0 MR14 =0x6
2669 09:54:42.280612
2670 09:54:42.281160 CH=1, VrefRange= 0, VrefLevel = 6
2671 09:54:42.287268 TX Bit0 (983~999) 17 991, Bit8 (970~984) 15 977,
2672 09:54:42.290454 TX Bit1 (981~997) 17 989, Bit9 (970~984) 15 977,
2673 09:54:42.297073 TX Bit2 (979~996) 18 987, Bit10 (972~987) 16 979,
2674 09:54:42.300686 TX Bit3 (977~993) 17 985, Bit11 (973~988) 16 980,
2675 09:54:42.303382 TX Bit4 (980~998) 19 989, Bit12 (973~988) 16 980,
2676 09:54:42.310549 TX Bit5 (983~999) 17 991, Bit13 (975~988) 14 981,
2677 09:54:42.313898 TX Bit6 (981~998) 18 989, Bit14 (971~987) 17 979,
2678 09:54:42.316825 TX Bit7 (981~997) 17 989, Bit15 (967~981) 15 974,
2679 09:54:42.317288
2680 09:54:42.320588 Write Rank0 MR14 =0x8
2681 09:54:42.329461
2682 09:54:42.330006 CH=1, VrefRange= 0, VrefLevel = 8
2683 09:54:42.336078 TX Bit0 (982~1000) 19 991, Bit8 (970~985) 16 977,
2684 09:54:42.340068 TX Bit1 (980~998) 19 989, Bit9 (970~984) 15 977,
2685 09:54:42.346082 TX Bit2 (978~996) 19 987, Bit10 (971~988) 18 979,
2686 09:54:42.349814 TX Bit3 (977~994) 18 985, Bit11 (972~989) 18 980,
2687 09:54:42.353073 TX Bit4 (980~999) 20 989, Bit12 (971~989) 19 980,
2688 09:54:42.359309 TX Bit5 (983~999) 17 991, Bit13 (974~990) 17 982,
2689 09:54:42.362753 TX Bit6 (981~998) 18 989, Bit14 (971~987) 17 979,
2690 09:54:42.366374 TX Bit7 (980~998) 19 989, Bit15 (967~982) 16 974,
2691 09:54:42.369259
2692 09:54:42.369716 Write Rank0 MR14 =0xa
2693 09:54:42.378934
2694 09:54:42.382176 CH=1, VrefRange= 0, VrefLevel = 10
2695 09:54:42.385425 TX Bit0 (982~1000) 19 991, Bit8 (970~985) 16 977,
2696 09:54:42.389026 TX Bit1 (979~998) 20 988, Bit9 (970~984) 15 977,
2697 09:54:42.395558 TX Bit2 (978~997) 20 987, Bit10 (971~989) 19 980,
2698 09:54:42.398845 TX Bit3 (977~994) 18 985, Bit11 (972~990) 19 981,
2699 09:54:42.402117 TX Bit4 (979~999) 21 989, Bit12 (971~990) 20 980,
2700 09:54:42.408667 TX Bit5 (982~999) 18 990, Bit13 (973~990) 18 981,
2701 09:54:42.411811 TX Bit6 (980~999) 20 989, Bit14 (971~989) 19 980,
2702 09:54:42.418229 TX Bit7 (980~998) 19 989, Bit15 (966~983) 18 974,
2703 09:54:42.418665
2704 09:54:42.419103 Write Rank0 MR14 =0xc
2705 09:54:42.427996
2706 09:54:42.431576 CH=1, VrefRange= 0, VrefLevel = 12
2707 09:54:42.434815 TX Bit0 (982~1000) 19 991, Bit8 (969~986) 18 977,
2708 09:54:42.438382 TX Bit1 (979~999) 21 989, Bit9 (969~985) 17 977,
2709 09:54:42.444657 TX Bit2 (978~998) 21 988, Bit10 (970~990) 21 980,
2710 09:54:42.448144 TX Bit3 (977~995) 19 986, Bit11 (971~990) 20 980,
2711 09:54:42.451443 TX Bit4 (979~1000) 22 989, Bit12 (971~991) 21 981,
2712 09:54:42.458147 TX Bit5 (982~999) 18 990, Bit13 (973~990) 18 981,
2713 09:54:42.461222 TX Bit6 (979~999) 21 989, Bit14 (971~990) 20 980,
2714 09:54:42.464678 TX Bit7 (980~998) 19 989, Bit15 (966~983) 18 974,
2715 09:54:42.467713
2716 09:54:42.468143 Write Rank0 MR14 =0xe
2717 09:54:42.477273
2718 09:54:42.480871 CH=1, VrefRange= 0, VrefLevel = 14
2719 09:54:42.484178 TX Bit0 (980~1000) 21 990, Bit8 (969~986) 18 977,
2720 09:54:42.487740 TX Bit1 (979~999) 21 989, Bit9 (969~985) 17 977,
2721 09:54:42.494243 TX Bit2 (977~999) 23 988, Bit10 (970~990) 21 980,
2722 09:54:42.497557 TX Bit3 (976~995) 20 985, Bit11 (971~991) 21 981,
2723 09:54:42.501001 TX Bit4 (979~1000) 22 989, Bit12 (971~991) 21 981,
2724 09:54:42.507845 TX Bit5 (982~1000) 19 991, Bit13 (973~991) 19 982,
2725 09:54:42.510346 TX Bit6 (979~999) 21 989, Bit14 (970~990) 21 980,
2726 09:54:42.517732 TX Bit7 (980~999) 20 989, Bit15 (966~984) 19 975,
2727 09:54:42.518272
2728 09:54:42.518719 Write Rank0 MR14 =0x10
2729 09:54:42.527528
2730 09:54:42.530561 CH=1, VrefRange= 0, VrefLevel = 16
2731 09:54:42.533780 TX Bit0 (980~1001) 22 990, Bit8 (969~987) 19 978,
2732 09:54:42.537336 TX Bit1 (978~999) 22 988, Bit9 (969~985) 17 977,
2733 09:54:42.543859 TX Bit2 (977~999) 23 988, Bit10 (970~991) 22 980,
2734 09:54:42.546996 TX Bit3 (976~996) 21 986, Bit11 (971~991) 21 981,
2735 09:54:42.550847 TX Bit4 (978~1000) 23 989, Bit12 (970~992) 23 981,
2736 09:54:42.557366 TX Bit5 (981~1000) 20 990, Bit13 (973~991) 19 982,
2737 09:54:42.560569 TX Bit6 (979~1000) 22 989, Bit14 (970~991) 22 980,
2738 09:54:42.564111 TX Bit7 (979~999) 21 989, Bit15 (966~984) 19 975,
2739 09:54:42.567179
2740 09:54:42.567713 Write Rank0 MR14 =0x12
2741 09:54:42.577285
2742 09:54:42.580631 CH=1, VrefRange= 0, VrefLevel = 18
2743 09:54:42.583770 TX Bit0 (980~1001) 22 990, Bit8 (969~988) 20 978,
2744 09:54:42.587509 TX Bit1 (978~1000) 23 989, Bit9 (969~986) 18 977,
2745 09:54:42.593852 TX Bit2 (977~999) 23 988, Bit10 (970~991) 22 980,
2746 09:54:42.597036 TX Bit3 (976~996) 21 986, Bit11 (970~992) 23 981,
2747 09:54:42.600787 TX Bit4 (978~1000) 23 989, Bit12 (970~992) 23 981,
2748 09:54:42.607060 TX Bit5 (981~1000) 20 990, Bit13 (972~991) 20 981,
2749 09:54:42.610209 TX Bit6 (978~1000) 23 989, Bit14 (970~991) 22 980,
2750 09:54:42.616660 TX Bit7 (979~1000) 22 989, Bit15 (965~984) 20 974,
2751 09:54:42.617201
2752 09:54:42.617643 Write Rank0 MR14 =0x14
2753 09:54:42.627287
2754 09:54:42.630697 CH=1, VrefRange= 0, VrefLevel = 20
2755 09:54:42.633814 TX Bit0 (979~1001) 23 990, Bit8 (968~989) 22 978,
2756 09:54:42.637739 TX Bit1 (978~1000) 23 989, Bit9 (969~987) 19 978,
2757 09:54:42.644105 TX Bit2 (977~1000) 24 988, Bit10 (970~991) 22 980,
2758 09:54:42.647195 TX Bit3 (976~997) 22 986, Bit11 (970~992) 23 981,
2759 09:54:42.650357 TX Bit4 (978~1001) 24 989, Bit12 (970~992) 23 981,
2760 09:54:42.657080 TX Bit5 (980~1001) 22 990, Bit13 (971~992) 22 981,
2761 09:54:42.660852 TX Bit6 (978~1000) 23 989, Bit14 (970~992) 23 981,
2762 09:54:42.667104 TX Bit7 (978~1000) 23 989, Bit15 (965~985) 21 975,
2763 09:54:42.667562
2764 09:54:42.667898 Write Rank0 MR14 =0x16
2765 09:54:42.677799
2766 09:54:42.680845 CH=1, VrefRange= 0, VrefLevel = 22
2767 09:54:42.684322 TX Bit0 (979~1002) 24 990, Bit8 (968~989) 22 978,
2768 09:54:42.687674 TX Bit1 (978~1001) 24 989, Bit9 (969~987) 19 978,
2769 09:54:42.694700 TX Bit2 (977~1000) 24 988, Bit10 (970~992) 23 981,
2770 09:54:42.698008 TX Bit3 (976~998) 23 987, Bit11 (970~992) 23 981,
2771 09:54:42.700694 TX Bit4 (977~1001) 25 989, Bit12 (970~992) 23 981,
2772 09:54:42.707940 TX Bit5 (980~1001) 22 990, Bit13 (971~992) 22 981,
2773 09:54:42.710583 TX Bit6 (978~1001) 24 989, Bit14 (969~992) 24 980,
2774 09:54:42.717146 TX Bit7 (978~1000) 23 989, Bit15 (964~985) 22 974,
2775 09:54:42.717568
2776 09:54:42.717897 Write Rank0 MR14 =0x18
2777 09:54:42.727852
2778 09:54:42.731455 CH=1, VrefRange= 0, VrefLevel = 24
2779 09:54:42.734867 TX Bit0 (979~1003) 25 991, Bit8 (968~990) 23 979,
2780 09:54:42.738348 TX Bit1 (977~1001) 25 989, Bit9 (968~988) 21 978,
2781 09:54:42.744735 TX Bit2 (977~1000) 24 988, Bit10 (969~992) 24 980,
2782 09:54:42.748020 TX Bit3 (976~999) 24 987, Bit11 (970~992) 23 981,
2783 09:54:42.751230 TX Bit4 (977~1001) 25 989, Bit12 (970~993) 24 981,
2784 09:54:42.757761 TX Bit5 (979~1001) 23 990, Bit13 (970~993) 24 981,
2785 09:54:42.760846 TX Bit6 (978~1001) 24 989, Bit14 (969~992) 24 980,
2786 09:54:42.767379 TX Bit7 (978~1001) 24 989, Bit15 (964~986) 23 975,
2787 09:54:42.767987
2788 09:54:42.768352 Write Rank0 MR14 =0x1a
2789 09:54:42.778503
2790 09:54:42.781705 CH=1, VrefRange= 0, VrefLevel = 26
2791 09:54:42.785489 TX Bit0 (978~1003) 26 990, Bit8 (967~990) 24 978,
2792 09:54:42.788467 TX Bit1 (977~1001) 25 989, Bit9 (968~989) 22 978,
2793 09:54:42.795667 TX Bit2 (977~1000) 24 988, Bit10 (969~992) 24 980,
2794 09:54:42.798440 TX Bit3 (975~999) 25 987, Bit11 (970~993) 24 981,
2795 09:54:42.801707 TX Bit4 (977~1002) 26 989, Bit12 (969~993) 25 981,
2796 09:54:42.808355 TX Bit5 (979~1002) 24 990, Bit13 (971~993) 23 982,
2797 09:54:42.811501 TX Bit6 (978~1001) 24 989, Bit14 (969~992) 24 980,
2798 09:54:42.818456 TX Bit7 (978~1001) 24 989, Bit15 (963~986) 24 974,
2799 09:54:42.819007
2800 09:54:42.819373 Write Rank0 MR14 =0x1c
2801 09:54:42.829121
2802 09:54:42.832261 CH=1, VrefRange= 0, VrefLevel = 28
2803 09:54:42.835886 TX Bit0 (978~1004) 27 991, Bit8 (967~990) 24 978,
2804 09:54:42.839092 TX Bit1 (977~1001) 25 989, Bit9 (968~990) 23 979,
2805 09:54:42.846242 TX Bit2 (976~1001) 26 988, Bit10 (969~992) 24 980,
2806 09:54:42.849463 TX Bit3 (975~999) 25 987, Bit11 (970~993) 24 981,
2807 09:54:42.852649 TX Bit4 (977~1002) 26 989, Bit12 (970~993) 24 981,
2808 09:54:42.858750 TX Bit5 (979~1003) 25 991, Bit13 (971~993) 23 982,
2809 09:54:42.862703 TX Bit6 (978~1002) 25 990, Bit14 (969~993) 25 981,
2810 09:54:42.869007 TX Bit7 (978~1001) 24 989, Bit15 (963~987) 25 975,
2811 09:54:42.869477
2812 09:54:42.869905 Write Rank0 MR14 =0x1e
2813 09:54:42.880107
2814 09:54:42.883332 CH=1, VrefRange= 0, VrefLevel = 30
2815 09:54:42.886732 TX Bit0 (978~1005) 28 991, Bit8 (967~991) 25 979,
2816 09:54:42.889937 TX Bit1 (977~1002) 26 989, Bit9 (967~990) 24 978,
2817 09:54:42.896345 TX Bit2 (976~1000) 25 988, Bit10 (969~992) 24 980,
2818 09:54:42.899712 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
2819 09:54:42.902879 TX Bit4 (978~1002) 25 990, Bit12 (969~993) 25 981,
2820 09:54:42.909549 TX Bit5 (978~1003) 26 990, Bit13 (970~993) 24 981,
2821 09:54:42.912805 TX Bit6 (977~1002) 26 989, Bit14 (969~993) 25 981,
2822 09:54:42.919896 TX Bit7 (978~1002) 25 990, Bit15 (963~986) 24 974,
2823 09:54:42.920451
2824 09:54:42.920815 Write Rank0 MR14 =0x20
2825 09:54:42.930549
2826 09:54:42.933777 CH=1, VrefRange= 0, VrefLevel = 32
2827 09:54:42.937273 TX Bit0 (978~1005) 28 991, Bit8 (967~991) 25 979,
2828 09:54:42.940506 TX Bit1 (977~1002) 26 989, Bit9 (967~990) 24 978,
2829 09:54:42.947307 TX Bit2 (976~1000) 25 988, Bit10 (969~992) 24 980,
2830 09:54:42.950391 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
2831 09:54:42.953990 TX Bit4 (978~1002) 25 990, Bit12 (969~993) 25 981,
2832 09:54:42.960453 TX Bit5 (978~1003) 26 990, Bit13 (970~993) 24 981,
2833 09:54:42.963581 TX Bit6 (977~1002) 26 989, Bit14 (969~993) 25 981,
2834 09:54:42.970564 TX Bit7 (978~1002) 25 990, Bit15 (963~986) 24 974,
2835 09:54:42.971132
2836 09:54:42.971541 Write Rank0 MR14 =0x22
2837 09:54:42.980743
2838 09:54:42.984154 CH=1, VrefRange= 0, VrefLevel = 34
2839 09:54:42.987809 TX Bit0 (978~1005) 28 991, Bit8 (967~991) 25 979,
2840 09:54:42.990729 TX Bit1 (977~1002) 26 989, Bit9 (967~990) 24 978,
2841 09:54:42.997172 TX Bit2 (976~1000) 25 988, Bit10 (969~992) 24 980,
2842 09:54:43.001087 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
2843 09:54:43.003893 TX Bit4 (978~1002) 25 990, Bit12 (969~993) 25 981,
2844 09:54:43.010972 TX Bit5 (978~1003) 26 990, Bit13 (970~993) 24 981,
2845 09:54:43.013957 TX Bit6 (977~1002) 26 989, Bit14 (969~993) 25 981,
2846 09:54:43.021095 TX Bit7 (978~1002) 25 990, Bit15 (963~986) 24 974,
2847 09:54:43.021615
2848 09:54:43.021949 Write Rank0 MR14 =0x24
2849 09:54:43.031379
2850 09:54:43.031952 CH=1, VrefRange= 0, VrefLevel = 36
2851 09:54:43.038325 TX Bit0 (978~1005) 28 991, Bit8 (967~991) 25 979,
2852 09:54:43.041578 TX Bit1 (977~1002) 26 989, Bit9 (967~990) 24 978,
2853 09:54:43.047838 TX Bit2 (976~1000) 25 988, Bit10 (969~992) 24 980,
2854 09:54:43.051205 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
2855 09:54:43.054626 TX Bit4 (978~1002) 25 990, Bit12 (969~993) 25 981,
2856 09:54:43.061360 TX Bit5 (978~1003) 26 990, Bit13 (970~993) 24 981,
2857 09:54:43.064334 TX Bit6 (977~1002) 26 989, Bit14 (969~993) 25 981,
2858 09:54:43.071441 TX Bit7 (978~1002) 25 990, Bit15 (963~986) 24 974,
2859 09:54:43.072039
2860 09:54:43.072406 Write Rank0 MR14 =0x26
2861 09:54:43.082044
2862 09:54:43.084599 CH=1, VrefRange= 0, VrefLevel = 38
2863 09:54:43.088474 TX Bit0 (978~1005) 28 991, Bit8 (967~991) 25 979,
2864 09:54:43.091498 TX Bit1 (977~1002) 26 989, Bit9 (967~990) 24 978,
2865 09:54:43.098126 TX Bit2 (976~1000) 25 988, Bit10 (969~992) 24 980,
2866 09:54:43.101573 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
2867 09:54:43.105017 TX Bit4 (978~1002) 25 990, Bit12 (969~993) 25 981,
2868 09:54:43.111561 TX Bit5 (978~1003) 26 990, Bit13 (970~993) 24 981,
2869 09:54:43.115011 TX Bit6 (977~1002) 26 989, Bit14 (969~993) 25 981,
2870 09:54:43.121538 TX Bit7 (978~1002) 25 990, Bit15 (963~986) 24 974,
2871 09:54:43.122057
2872 09:54:43.122390
2873 09:54:43.124809 TX Vref found, early break! 373< 381
2874 09:54:43.128098 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2875 09:54:43.131916 u1DelayCellOfst[0]=5 cells (4 PI)
2876 09:54:43.135079 u1DelayCellOfst[1]=2 cells (2 PI)
2877 09:54:43.138134 u1DelayCellOfst[2]=1 cells (1 PI)
2878 09:54:43.141404 u1DelayCellOfst[3]=0 cells (0 PI)
2879 09:54:43.144817 u1DelayCellOfst[4]=3 cells (3 PI)
2880 09:54:43.148048 u1DelayCellOfst[5]=3 cells (3 PI)
2881 09:54:43.151433 u1DelayCellOfst[6]=2 cells (2 PI)
2882 09:54:43.151962 u1DelayCellOfst[7]=3 cells (3 PI)
2883 09:54:43.154404 Byte0, DQ PI dly=987, DQM PI dly= 989
2884 09:54:43.161376 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
2885 09:54:43.161901
2886 09:54:43.164326 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
2887 09:54:43.164748
2888 09:54:43.168435 u1DelayCellOfst[8]=6 cells (5 PI)
2889 09:54:43.171013 u1DelayCellOfst[9]=5 cells (4 PI)
2890 09:54:43.174916 u1DelayCellOfst[10]=7 cells (6 PI)
2891 09:54:43.177733 u1DelayCellOfst[11]=9 cells (7 PI)
2892 09:54:43.181306 u1DelayCellOfst[12]=9 cells (7 PI)
2893 09:54:43.184518 u1DelayCellOfst[13]=9 cells (7 PI)
2894 09:54:43.187593 u1DelayCellOfst[14]=9 cells (7 PI)
2895 09:54:43.190880 u1DelayCellOfst[15]=0 cells (0 PI)
2896 09:54:43.194223 Byte1, DQ PI dly=974, DQM PI dly= 977
2897 09:54:43.198026 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 14)
2898 09:54:43.198542
2899 09:54:43.201385 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 14)
2900 09:54:43.201910
2901 09:54:43.204753 Write Rank0 MR14 =0x1e
2902 09:54:43.205270
2903 09:54:43.207615 Final TX Range 0 Vref 30
2904 09:54:43.208035
2905 09:54:43.215083 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2906 09:54:43.215646
2907 09:54:43.220935 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2908 09:54:43.228145 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2909 09:54:43.234673 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2910 09:54:43.235234 Write Rank0 MR3 =0xb0
2911 09:54:43.237790 DramC Write-DBI on
2912 09:54:43.238325 ==
2913 09:54:43.244338 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2914 09:54:43.244889 fsp= 1, odt_onoff= 1, Byte mode= 0
2915 09:54:43.247591 ==
2916 09:54:43.251527 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2917 09:54:43.252114
2918 09:54:43.254546 Begin, DQ Scan Range 697~761
2919 09:54:43.255003
2920 09:54:43.255366
2921 09:54:43.255762 TX Vref Scan disable
2922 09:54:43.257818 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2923 09:54:43.261222 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2924 09:54:43.267842 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2925 09:54:43.270911 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2926 09:54:43.274339 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2927 09:54:43.277386 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2928 09:54:43.280873 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2929 09:54:43.284301 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2930 09:54:43.287557 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2931 09:54:43.290683 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2932 09:54:43.294201 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2933 09:54:43.297606 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2934 09:54:43.300573 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2935 09:54:43.304517 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2936 09:54:43.307658 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2937 09:54:43.310634 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2938 09:54:43.313914 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2939 09:54:43.317465 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2940 09:54:43.321139 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
2941 09:54:43.324005 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
2942 09:54:43.327245 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
2943 09:54:43.334239 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
2944 09:54:43.337525 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
2945 09:54:43.340767 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
2946 09:54:43.344174 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
2947 09:54:43.347106 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2948 09:54:43.353855 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2949 09:54:43.357065 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2950 09:54:43.360554 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2951 09:54:43.363958 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2952 09:54:43.367509 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2953 09:54:43.370176 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2954 09:54:43.374120 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
2955 09:54:43.377074 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
2956 09:54:43.380347 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
2957 09:54:43.383628 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
2958 09:54:43.387019 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
2959 09:54:43.390386 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
2960 09:54:43.393376 749 |2 6 45|[0] xxxxxxxx xxxxxxxx [MSB]
2961 09:54:43.397161 Byte0, DQ PI dly=735, DQM PI dly= 735
2962 09:54:43.403697 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 31)
2963 09:54:43.404272
2964 09:54:43.407148 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 31)
2965 09:54:43.407686
2966 09:54:43.410542 Byte1, DQ PI dly=723, DQM PI dly= 723
2967 09:54:43.413442 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
2968 09:54:43.413884
2969 09:54:43.420228 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
2970 09:54:43.420654
2971 09:54:43.426889 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2972 09:54:43.433573 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2973 09:54:43.439937 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2974 09:54:43.443485 Write Rank0 MR3 =0x30
2975 09:54:43.443904 DramC Write-DBI off
2976 09:54:43.444235
2977 09:54:43.444542 [DATLAT]
2978 09:54:43.446714 Freq=1600, CH1 RK0, use_rxtx_scan=0
2979 09:54:43.447133
2980 09:54:43.449979 DATLAT Default: 0xf
2981 09:54:43.450276 7, 0xFFFF, sum=0
2982 09:54:43.453146 8, 0xFFFF, sum=0
2983 09:54:43.453375 9, 0xFFFF, sum=0
2984 09:54:43.456727 10, 0xFFFF, sum=0
2985 09:54:43.457008 11, 0xFFFF, sum=0
2986 09:54:43.459746 12, 0xFFFF, sum=0
2987 09:54:43.459929 13, 0xFFFF, sum=0
2988 09:54:43.463353 14, 0x0, sum=1
2989 09:54:43.463641 15, 0x0, sum=2
2990 09:54:43.466495 16, 0x0, sum=3
2991 09:54:43.466764 17, 0x0, sum=4
2992 09:54:43.469669 pattern=2 first_step=14 total pass=5 best_step=16
2993 09:54:43.469940 ==
2994 09:54:43.476361 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2995 09:54:43.479943 fsp= 1, odt_onoff= 1, Byte mode= 0
2996 09:54:43.480202 ==
2997 09:54:43.483109 Start DQ dly to find pass range UseTestEngine =1
2998 09:54:43.486519 x-axis: bit #, y-axis: DQ dly (-127~63)
2999 09:54:43.489763 RX Vref Scan = 1
3000 09:54:43.596376
3001 09:54:43.596959 RX Vref found, early break!
3002 09:54:43.597299
3003 09:54:43.602529 Final RX Vref 11, apply to both rank0 and 1
3004 09:54:43.602953 ==
3005 09:54:43.605901 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3006 09:54:43.609415 fsp= 1, odt_onoff= 1, Byte mode= 0
3007 09:54:43.609836 ==
3008 09:54:43.610168 DQS Delay:
3009 09:54:43.612641 DQS0 = 0, DQS1 = 0
3010 09:54:43.613058 DQM Delay:
3011 09:54:43.616088 DQM0 = 20, DQM1 = 18
3012 09:54:43.616502 DQ Delay:
3013 09:54:43.619700 DQ0 =22, DQ1 =21, DQ2 =19, DQ3 =17
3014 09:54:43.622608 DQ4 =22, DQ5 =22, DQ6 =24, DQ7 =20
3015 09:54:43.626076 DQ8 =16, DQ9 =15, DQ10 =19, DQ11 =22
3016 09:54:43.629423 DQ12 =22, DQ13 =21, DQ14 =23, DQ15 =13
3017 09:54:43.629839
3018 09:54:43.630166
3019 09:54:43.630471
3020 09:54:43.633305 [DramC_TX_OE_Calibration] TA2
3021 09:54:43.636243 Original DQ_B0 (3 6) =30, OEN = 27
3022 09:54:43.639895 Original DQ_B1 (3 6) =30, OEN = 27
3023 09:54:43.642836 23, 0x0, End_B0=23 End_B1=23
3024 09:54:43.643288 24, 0x0, End_B0=24 End_B1=24
3025 09:54:43.645988 25, 0x0, End_B0=25 End_B1=25
3026 09:54:43.649575 26, 0x0, End_B0=26 End_B1=26
3027 09:54:43.652878 27, 0x0, End_B0=27 End_B1=27
3028 09:54:43.653408 28, 0x0, End_B0=28 End_B1=28
3029 09:54:43.655977 29, 0x0, End_B0=29 End_B1=29
3030 09:54:43.659527 30, 0x0, End_B0=30 End_B1=30
3031 09:54:43.662748 31, 0xFFFF, End_B0=30 End_B1=30
3032 09:54:43.669533 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3033 09:54:43.672603 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3034 09:54:43.673022
3035 09:54:43.673449
3036 09:54:43.676045 Write Rank0 MR23 =0x3f
3037 09:54:43.676553 [DQSOSC]
3038 09:54:43.686119 [DQSOSCAuto] RK0, (LSB)MR18= 0xbcbc, (MSB)MR19= 0x202, tDQSOscB0 = 450 ps tDQSOscB1 = 450 ps
3039 09:54:43.689308 CH1_RK0: MR19=0x202, MR18=0xBCBC, DQSOSC=450, MR23=63, INC=12, DEC=18
3040 09:54:43.692590 Write Rank0 MR23 =0x3f
3041 09:54:43.693135 [DQSOSC]
3042 09:54:43.703255 [DQSOSCAuto] RK0, (LSB)MR18= 0xbebe, (MSB)MR19= 0x202, tDQSOscB0 = 448 ps tDQSOscB1 = 448 ps
3043 09:54:43.706433 CH1 RK0: MR19=202, MR18=BEBE
3044 09:54:43.709490 [RankSwap] Rank num 2, (Multi 1), Rank 1
3045 09:54:43.710001 Write Rank0 MR2 =0xad
3046 09:54:43.712717 [Write Leveling]
3047 09:54:43.715997 delay byte0 byte1 byte2 byte3
3048 09:54:43.716416
3049 09:54:43.716743 10 0 0
3050 09:54:43.719362 11 0 0
3051 09:54:43.719815 12 0 0
3052 09:54:43.720150 13 0 0
3053 09:54:43.722762 14 0 0
3054 09:54:43.723185 15 0 0
3055 09:54:43.725954 16 0 0
3056 09:54:43.726469 17 0 0
3057 09:54:43.726845 18 0 0
3058 09:54:43.729597 19 0 0
3059 09:54:43.730116 20 0 0
3060 09:54:43.732902 21 0 0
3061 09:54:43.733418 22 0 0
3062 09:54:43.736173 23 0 0
3063 09:54:43.736686 24 0 ff
3064 09:54:43.737039 25 0 ff
3065 09:54:43.739480 26 0 ff
3066 09:54:43.739999 27 0 ff
3067 09:54:43.742488 28 0 ff
3068 09:54:43.742911 29 0 ff
3069 09:54:43.746008 30 0 ff
3070 09:54:43.746524 31 0 ff
3071 09:54:43.749116 32 0 ff
3072 09:54:43.749630 33 0 ff
3073 09:54:43.749970 34 0 ff
3074 09:54:43.752227 35 ff ff
3075 09:54:43.752654 36 ff ff
3076 09:54:43.755805 37 ff ff
3077 09:54:43.756324 38 ff ff
3078 09:54:43.758748 39 ff ff
3079 09:54:43.759172 40 ff ff
3080 09:54:43.762336 41 ff ff
3081 09:54:43.765818 pass bytecount = 0xff (0xff: all bytes pass)
3082 09:54:43.766237
3083 09:54:43.766567 DQS0 dly: 35
3084 09:54:43.769083 DQS1 dly: 24
3085 09:54:43.769589 Write Rank0 MR2 =0x2d
3086 09:54:43.772103 [RankSwap] Rank num 2, (Multi 1), Rank 0
3087 09:54:43.775271 Write Rank1 MR1 =0xd6
3088 09:54:43.775812 [Gating]
3089 09:54:43.776145 ==
3090 09:54:43.782355 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3091 09:54:43.785389 fsp= 1, odt_onoff= 1, Byte mode= 0
3092 09:54:43.785860 ==
3093 09:54:43.788761 3 1 0 |3635 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
3094 09:54:43.795454 3 1 4 |3736 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
3095 09:54:43.798376 3 1 8 |3433 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3096 09:54:43.801942 3 1 12 |3433 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3097 09:54:43.804938 3 1 16 |b0a 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3098 09:54:43.811588 3 1 20 |2f2e 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3099 09:54:43.815225 3 1 24 |2020 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3100 09:54:43.818731 3 1 28 |3333 2c2b |(11 11)(11 11) |(1 0)(1 0)| 0
3101 09:54:43.825452 3 2 0 |3232 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3102 09:54:43.828841 3 2 4 |1c1b 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3103 09:54:43.832178 3 2 8 |505 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3104 09:54:43.838792 3 2 12 |3b3b 2c2c |(11 11)(11 0) |(1 1)(0 0)| 0
3105 09:54:43.842049 3 2 16 |2928 1515 |(11 11)(11 11) |(1 1)(0 0)| 0
3106 09:54:43.845358 [Byte 0] Lead/lag Transition tap number (1)
3107 09:54:43.848719 3 2 20 |3a39 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3108 09:54:43.854977 3 2 24 |3a3a 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3109 09:54:43.858326 3 2 28 |1b1a 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
3110 09:54:43.861442 3 3 0 |3a3a 3534 |(0 0)(11 11) |(1 1)(0 0)| 0
3111 09:54:43.868576 3 3 4 |1414 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3112 09:54:43.871672 3 3 8 |b0a 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3113 09:54:43.875030 3 3 12 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3114 09:54:43.881604 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3115 09:54:43.884716 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3116 09:54:43.888129 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3117 09:54:43.894802 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3118 09:54:43.898085 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3119 09:54:43.901807 3 4 4 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3120 09:54:43.904400 3 4 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3121 09:54:43.911277 3 4 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3122 09:54:43.914290 3 4 16 |3d3d 3d3c |(11 11)(11 11) |(1 1)(1 1)| 0
3123 09:54:43.917608 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3124 09:54:43.924110 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3125 09:54:43.927682 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3126 09:54:43.930781 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3127 09:54:43.937491 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3128 09:54:43.940599 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3129 09:54:43.944185 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3130 09:54:43.951487 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3131 09:54:43.954750 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3132 09:54:43.958057 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3133 09:54:43.964358 [Byte 0] Lead/lag falling Transition (3, 5, 24)
3134 09:54:43.967618 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3135 09:54:43.970997 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3136 09:54:43.974290 [Byte 0] Lead/lag Transition tap number (3)
3137 09:54:43.980874 3 6 4 |1010 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3138 09:54:43.984077 [Byte 1] Lead/lag falling Transition (3, 6, 4)
3139 09:54:43.987447 3 6 8 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3140 09:54:43.990606 [Byte 1] Lead/lag Transition tap number (2)
3141 09:54:43.997309 3 6 12 |4646 1e1e |(0 0)(11 11) |(0 0)(0 0)| 0
3142 09:54:43.997876 [Byte 0]First pass (3, 6, 12)
3143 09:54:44.004220 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3144 09:54:44.004643 [Byte 1]First pass (3, 6, 16)
3145 09:54:44.011150 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3146 09:54:44.014747 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3147 09:54:44.017666 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3148 09:54:44.021359 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3149 09:54:44.024649 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3150 09:54:44.030544 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3151 09:54:44.034275 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3152 09:54:44.037081 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3153 09:54:44.040910 All bytes gating window > 1UI, Early break!
3154 09:54:44.041331
3155 09:54:44.044115 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 30)
3156 09:54:44.044532
3157 09:54:44.047531 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
3158 09:54:44.047949
3159 09:54:44.051176
3160 09:54:44.051788
3161 09:54:44.054436 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 30)
3162 09:54:44.054856
3163 09:54:44.057687 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
3164 09:54:44.058105
3165 09:54:44.058431
3166 09:54:44.061166 Write Rank1 MR1 =0x56
3167 09:54:44.061582
3168 09:54:44.063897 best RODT dly(2T, 0.5T) = (2, 2)
3169 09:54:44.064317
3170 09:54:44.064646 best RODT dly(2T, 0.5T) = (2, 3)
3171 09:54:44.067770 ==
3172 09:54:44.070893 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3173 09:54:44.074519 fsp= 1, odt_onoff= 1, Byte mode= 0
3174 09:54:44.074962 ==
3175 09:54:44.077776 Start DQ dly to find pass range UseTestEngine =0
3176 09:54:44.080682 x-axis: bit #, y-axis: DQ dly (-127~63)
3177 09:54:44.083982 RX Vref Scan = 0
3178 09:54:44.087167 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3179 09:54:44.090559 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3180 09:54:44.094144 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3181 09:54:44.094697 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3182 09:54:44.096951 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3183 09:54:44.100346 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3184 09:54:44.104120 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3185 09:54:44.107168 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3186 09:54:44.110538 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3187 09:54:44.114021 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3188 09:54:44.117210 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3189 09:54:44.120244 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3190 09:54:44.120663 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3191 09:54:44.123882 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3192 09:54:44.126783 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3193 09:54:44.130589 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3194 09:54:44.134032 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3195 09:54:44.137266 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3196 09:54:44.139962 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3197 09:54:44.143327 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3198 09:54:44.143451 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3199 09:54:44.146976 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3200 09:54:44.149753 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3201 09:54:44.153437 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3202 09:54:44.156889 -2, [0] xxxoxxxx xoxxxxxo [MSB]
3203 09:54:44.160383 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3204 09:54:44.160798 0, [0] xxooxxxx ooxxxxxo [MSB]
3205 09:54:44.163556 1, [0] xxooxxxx ooxxxxxo [MSB]
3206 09:54:44.166980 2, [0] xxooxxxx ooxxxxxo [MSB]
3207 09:54:44.170664 3, [0] xxooxxxo oooxxxxo [MSB]
3208 09:54:44.173988 4, [0] oxoooxxo oooxxxxo [MSB]
3209 09:54:44.177007 5, [0] oooooxoo ooooooxo [MSB]
3210 09:54:44.180103 31, [0] oooooooo ooooooox [MSB]
3211 09:54:44.180521 32, [0] oooooooo ooooooox [MSB]
3212 09:54:44.183973 33, [0] oooooooo ooooooox [MSB]
3213 09:54:44.186760 34, [0] oooooooo ooooooox [MSB]
3214 09:54:44.190181 35, [0] oooxoooo xxooooox [MSB]
3215 09:54:44.193858 36, [0] oooxoooo xxooooox [MSB]
3216 09:54:44.197468 37, [0] ooxxoooo xxooooox [MSB]
3217 09:54:44.198000 38, [0] ooxxoooo xxooooox [MSB]
3218 09:54:44.200818 39, [0] oxxxooox xxooooox [MSB]
3219 09:54:44.203855 40, [0] oxxxxoox xxxoooox [MSB]
3220 09:54:44.207516 41, [0] oxxxxoox xxxxxxox [MSB]
3221 09:54:44.210514 42, [0] xxxxxxxx xxxxxxxx [MSB]
3222 09:54:44.213966 iDelay=42, Bit 0, Center 22 (4 ~ 41) 38
3223 09:54:44.217017 iDelay=42, Bit 1, Center 21 (5 ~ 38) 34
3224 09:54:44.220534 iDelay=42, Bit 2, Center 18 (0 ~ 36) 37
3225 09:54:44.223581 iDelay=42, Bit 3, Center 16 (-2 ~ 34) 37
3226 09:54:44.227299 iDelay=42, Bit 4, Center 21 (4 ~ 39) 36
3227 09:54:44.230884 iDelay=42, Bit 5, Center 23 (6 ~ 41) 36
3228 09:54:44.233816 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
3229 09:54:44.237657 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
3230 09:54:44.240510 iDelay=42, Bit 8, Center 17 (0 ~ 34) 35
3231 09:54:44.247186 iDelay=42, Bit 9, Center 16 (-2 ~ 34) 37
3232 09:54:44.250622 iDelay=42, Bit 10, Center 21 (3 ~ 39) 37
3233 09:54:44.253729 iDelay=42, Bit 11, Center 22 (5 ~ 40) 36
3234 09:54:44.257267 iDelay=42, Bit 12, Center 22 (5 ~ 40) 36
3235 09:54:44.260261 iDelay=42, Bit 13, Center 22 (5 ~ 40) 36
3236 09:54:44.264035 iDelay=42, Bit 14, Center 23 (6 ~ 41) 36
3237 09:54:44.267160 iDelay=42, Bit 15, Center 13 (-3 ~ 30) 34
3238 09:54:44.267648 ==
3239 09:54:44.274098 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3240 09:54:44.277163 fsp= 1, odt_onoff= 1, Byte mode= 0
3241 09:54:44.277618 ==
3242 09:54:44.277975 DQS Delay:
3243 09:54:44.280453 DQS0 = 0, DQS1 = 0
3244 09:54:44.280904 DQM Delay:
3245 09:54:44.281258 DQM0 = 20, DQM1 = 19
3246 09:54:44.283726 DQ Delay:
3247 09:54:44.286977 DQ0 =22, DQ1 =21, DQ2 =18, DQ3 =16
3248 09:54:44.290373 DQ4 =21, DQ5 =23, DQ6 =23, DQ7 =20
3249 09:54:44.293179 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
3250 09:54:44.296981 DQ12 =22, DQ13 =22, DQ14 =23, DQ15 =13
3251 09:54:44.297502
3252 09:54:44.297940
3253 09:54:44.298347 DramC Write-DBI off
3254 09:54:44.298795 ==
3255 09:54:44.303795 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3256 09:54:44.306963 fsp= 1, odt_onoff= 1, Byte mode= 0
3257 09:54:44.307501 ==
3258 09:54:44.310375 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3259 09:54:44.310882
3260 09:54:44.313578 Begin, DQ Scan Range 920~1176
3261 09:54:44.314105
3262 09:54:44.314542
3263 09:54:44.317239 TX Vref Scan disable
3264 09:54:44.320086 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
3265 09:54:44.323589 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
3266 09:54:44.327086 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
3267 09:54:44.330473 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
3268 09:54:44.333556 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
3269 09:54:44.336974 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3270 09:54:44.340156 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3271 09:54:44.343117 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3272 09:54:44.346799 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3273 09:54:44.350644 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3274 09:54:44.353501 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3275 09:54:44.356695 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3276 09:54:44.363366 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3277 09:54:44.366680 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3278 09:54:44.369916 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3279 09:54:44.373201 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3280 09:54:44.376660 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3281 09:54:44.379922 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3282 09:54:44.383485 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3283 09:54:44.386807 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3284 09:54:44.390222 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3285 09:54:44.393154 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3286 09:54:44.396865 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3287 09:54:44.399830 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3288 09:54:44.403121 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3289 09:54:44.406975 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3290 09:54:44.410428 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3291 09:54:44.413489 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3292 09:54:44.419743 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3293 09:54:44.423071 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3294 09:54:44.426646 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3295 09:54:44.429682 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3296 09:54:44.433057 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3297 09:54:44.436332 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3298 09:54:44.439860 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3299 09:54:44.443386 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3300 09:54:44.446522 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3301 09:54:44.449665 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3302 09:54:44.453187 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3303 09:54:44.456764 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3304 09:54:44.459810 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3305 09:54:44.463107 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3306 09:54:44.466342 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3307 09:54:44.469757 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3308 09:54:44.473152 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3309 09:54:44.475875 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3310 09:54:44.479629 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3311 09:54:44.486187 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3312 09:54:44.489991 968 |3 6 8|[0] xxxxxxxx xxxxxxxo [MSB]
3313 09:54:44.493192 969 |3 6 9|[0] xxxxxxxx ooxxxxxo [MSB]
3314 09:54:44.496457 970 |3 6 10|[0] xxxxxxxx ooxxxxxo [MSB]
3315 09:54:44.500110 971 |3 6 11|[0] xxxxxxxx oooooxoo [MSB]
3316 09:54:44.503069 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
3317 09:54:44.506704 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
3318 09:54:44.510152 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
3319 09:54:44.513426 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
3320 09:54:44.516761 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
3321 09:54:44.519990 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
3322 09:54:44.523188 978 |3 6 18|[0] xxooxxxx oooooooo [MSB]
3323 09:54:44.526294 979 |3 6 19|[0] xooooxxx oooooooo [MSB]
3324 09:54:44.529614 980 |3 6 20|[0] xooooxoo oooooooo [MSB]
3325 09:54:44.536188 985 |3 6 25|[0] oooooooo ooooooox [MSB]
3326 09:54:44.539982 986 |3 6 26|[0] oooooooo ooooooox [MSB]
3327 09:54:44.542900 987 |3 6 27|[0] oooooooo ooooooox [MSB]
3328 09:54:44.546305 988 |3 6 28|[0] oooooooo xxooooox [MSB]
3329 09:54:44.549461 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
3330 09:54:44.553060 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
3331 09:54:44.556454 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3332 09:54:44.559677 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3333 09:54:44.563006 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3334 09:54:44.566242 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3335 09:54:44.569591 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3336 09:54:44.572728 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3337 09:54:44.576094 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3338 09:54:44.579559 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
3339 09:54:44.585612 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
3340 09:54:44.589084 1000 |3 6 40|[0] ooxxoooo xxxxxxxx [MSB]
3341 09:54:44.592502 1001 |3 6 41|[0] ooxxxoox xxxxxxxx [MSB]
3342 09:54:44.595856 1002 |3 6 42|[0] oxxxxoxx xxxxxxxx [MSB]
3343 09:54:44.599345 1003 |3 6 43|[0] xxxxxxxx xxxxxxxx [MSB]
3344 09:54:44.602347 Byte0, DQ PI dly=989, DQM PI dly= 989
3345 09:54:44.605690 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
3346 09:54:44.606102
3347 09:54:44.612552 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
3348 09:54:44.613065
3349 09:54:44.615924 Byte1, DQ PI dly=978, DQM PI dly= 978
3350 09:54:44.619288 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
3351 09:54:44.619880
3352 09:54:44.622664 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
3353 09:54:44.623218
3354 09:54:44.623648 ==
3355 09:54:44.628987 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3356 09:54:44.632250 fsp= 1, odt_onoff= 1, Byte mode= 0
3357 09:54:44.632657 ==
3358 09:54:44.635617 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3359 09:54:44.636229
3360 09:54:44.638779 Begin, DQ Scan Range 954~1018
3361 09:54:44.641838 Write Rank1 MR14 =0x0
3362 09:54:44.649720
3363 09:54:44.650372 CH=1, VrefRange= 0, VrefLevel = 0
3364 09:54:44.656549 TX Bit0 (983~998) 16 990, Bit8 (970~984) 15 977,
3365 09:54:44.659689 TX Bit1 (982~997) 16 989, Bit9 (970~984) 15 977,
3366 09:54:44.666419 TX Bit2 (980~994) 15 987, Bit10 (974~985) 12 979,
3367 09:54:44.669742 TX Bit3 (978~991) 14 984, Bit11 (975~986) 12 980,
3368 09:54:44.673115 TX Bit4 (982~997) 16 989, Bit12 (975~985) 11 980,
3369 09:54:44.679760 TX Bit5 (983~998) 16 990, Bit13 (975~987) 13 981,
3370 09:54:44.683148 TX Bit6 (983~997) 15 990, Bit14 (975~984) 10 979,
3371 09:54:44.686424 TX Bit7 (984~995) 12 989, Bit15 (968~978) 11 973,
3372 09:54:44.686845
3373 09:54:44.689675 Write Rank1 MR14 =0x2
3374 09:54:44.698755
3375 09:54:44.699274 CH=1, VrefRange= 0, VrefLevel = 2
3376 09:54:44.705620 TX Bit0 (983~999) 17 991, Bit8 (970~984) 15 977,
3377 09:54:44.708790 TX Bit1 (982~998) 17 990, Bit9 (970~984) 15 977,
3378 09:54:44.715577 TX Bit2 (980~995) 16 987, Bit10 (974~985) 12 979,
3379 09:54:44.719010 TX Bit3 (978~992) 15 985, Bit11 (974~986) 13 980,
3380 09:54:44.722327 TX Bit4 (982~997) 16 989, Bit12 (974~985) 12 979,
3381 09:54:44.728983 TX Bit5 (983~999) 17 991, Bit13 (974~988) 15 981,
3382 09:54:44.732736 TX Bit6 (982~998) 17 990, Bit14 (975~985) 11 980,
3383 09:54:44.735859 TX Bit7 (984~997) 14 990, Bit15 (968~979) 12 973,
3384 09:54:44.736420
3385 09:54:44.739198 Write Rank1 MR14 =0x4
3386 09:54:44.748453
3387 09:54:44.749006 CH=1, VrefRange= 0, VrefLevel = 4
3388 09:54:44.755209 TX Bit0 (983~999) 17 991, Bit8 (970~984) 15 977,
3389 09:54:44.757955 TX Bit1 (982~998) 17 990, Bit9 (970~984) 15 977,
3390 09:54:44.764704 TX Bit2 (980~996) 17 988, Bit10 (974~986) 13 980,
3391 09:54:44.768313 TX Bit3 (978~992) 15 985, Bit11 (974~987) 14 980,
3392 09:54:44.771625 TX Bit4 (981~998) 18 989, Bit12 (974~986) 13 980,
3393 09:54:44.777990 TX Bit5 (983~999) 17 991, Bit13 (975~989) 15 982,
3394 09:54:44.781289 TX Bit6 (982~998) 17 990, Bit14 (974~986) 13 980,
3395 09:54:44.784709 TX Bit7 (984~997) 14 990, Bit15 (967~980) 14 973,
3396 09:54:44.785178
3397 09:54:44.787853 Write Rank1 MR14 =0x6
3398 09:54:44.797461
3399 09:54:44.798000 CH=1, VrefRange= 0, VrefLevel = 6
3400 09:54:44.804183 TX Bit0 (983~1000) 18 991, Bit8 (970~985) 16 977,
3401 09:54:44.806878 TX Bit1 (981~998) 18 989, Bit9 (970~984) 15 977,
3402 09:54:44.813885 TX Bit2 (979~997) 19 988, Bit10 (973~987) 15 980,
3403 09:54:44.817100 TX Bit3 (978~993) 16 985, Bit11 (974~988) 15 981,
3404 09:54:44.820302 TX Bit4 (981~998) 18 989, Bit12 (974~987) 14 980,
3405 09:54:44.827274 TX Bit5 (983~1000) 18 991, Bit13 (974~989) 16 981,
3406 09:54:44.830624 TX Bit6 (981~998) 18 989, Bit14 (973~987) 15 980,
3407 09:54:44.834073 TX Bit7 (983~998) 16 990, Bit15 (968~981) 14 974,
3408 09:54:44.837439
3409 09:54:44.837990 Write Rank1 MR14 =0x8
3410 09:54:44.846973
3411 09:54:44.847558 CH=1, VrefRange= 0, VrefLevel = 8
3412 09:54:44.853623 TX Bit0 (982~1000) 19 991, Bit8 (969~985) 17 977,
3413 09:54:44.856808 TX Bit1 (981~999) 19 990, Bit9 (969~985) 17 977,
3414 09:54:44.863247 TX Bit2 (979~998) 20 988, Bit10 (972~987) 16 979,
3415 09:54:44.866744 TX Bit3 (978~994) 17 986, Bit11 (973~990) 18 981,
3416 09:54:44.870083 TX Bit4 (980~999) 20 989, Bit12 (974~988) 15 981,
3417 09:54:44.876341 TX Bit5 (982~1000) 19 991, Bit13 (974~990) 17 982,
3418 09:54:44.880220 TX Bit6 (981~999) 19 990, Bit14 (973~987) 15 980,
3419 09:54:44.886677 TX Bit7 (983~998) 16 990, Bit15 (967~982) 16 974,
3420 09:54:44.887193
3421 09:54:44.887557 Write Rank1 MR14 =0xa
3422 09:54:44.896349
3423 09:54:44.900065 CH=1, VrefRange= 0, VrefLevel = 10
3424 09:54:44.903065 TX Bit0 (982~1001) 20 991, Bit8 (969~985) 17 977,
3425 09:54:44.905937 TX Bit1 (980~999) 20 989, Bit9 (970~985) 16 977,
3426 09:54:44.912870 TX Bit2 (979~998) 20 988, Bit10 (972~988) 17 980,
3427 09:54:44.915907 TX Bit3 (978~995) 18 986, Bit11 (972~990) 19 981,
3428 09:54:44.919952 TX Bit4 (980~999) 20 989, Bit12 (973~989) 17 981,
3429 09:54:44.926470 TX Bit5 (982~1000) 19 991, Bit13 (973~991) 19 982,
3430 09:54:44.929485 TX Bit6 (980~1000) 21 990, Bit14 (972~988) 17 980,
3431 09:54:44.935728 TX Bit7 (982~999) 18 990, Bit15 (968~983) 16 975,
3432 09:54:44.936141
3433 09:54:44.936461 Write Rank1 MR14 =0xc
3434 09:54:44.946300
3435 09:54:44.949501 CH=1, VrefRange= 0, VrefLevel = 12
3436 09:54:44.953021 TX Bit0 (982~1001) 20 991, Bit8 (969~986) 18 977,
3437 09:54:44.956465 TX Bit1 (979~1000) 22 989, Bit9 (969~986) 18 977,
3438 09:54:44.963296 TX Bit2 (978~998) 21 988, Bit10 (971~989) 19 980,
3439 09:54:44.966049 TX Bit3 (978~996) 19 987, Bit11 (973~990) 18 981,
3440 09:54:44.969305 TX Bit4 (979~999) 21 989, Bit12 (972~989) 18 980,
3441 09:54:44.975856 TX Bit5 (981~1001) 21 991, Bit13 (972~991) 20 981,
3442 09:54:44.979339 TX Bit6 (980~1000) 21 990, Bit14 (971~989) 19 980,
3443 09:54:44.985906 TX Bit7 (982~999) 18 990, Bit15 (967~983) 17 975,
3444 09:54:44.986425
3445 09:54:44.986755 Write Rank1 MR14 =0xe
3446 09:54:44.995982
3447 09:54:44.999885 CH=1, VrefRange= 0, VrefLevel = 14
3448 09:54:45.002944 TX Bit0 (981~1002) 22 991, Bit8 (969~986) 18 977,
3449 09:54:45.006200 TX Bit1 (979~1000) 22 989, Bit9 (969~986) 18 977,
3450 09:54:45.012955 TX Bit2 (978~998) 21 988, Bit10 (971~990) 20 980,
3451 09:54:45.016076 TX Bit3 (977~997) 21 987, Bit11 (972~991) 20 981,
3452 09:54:45.019467 TX Bit4 (979~1000) 22 989, Bit12 (972~990) 19 981,
3453 09:54:45.025825 TX Bit5 (981~1001) 21 991, Bit13 (972~991) 20 981,
3454 09:54:45.028943 TX Bit6 (980~1000) 21 990, Bit14 (970~990) 21 980,
3455 09:54:45.035953 TX Bit7 (981~999) 19 990, Bit15 (967~984) 18 975,
3456 09:54:45.036469
3457 09:54:45.036794 Write Rank1 MR14 =0x10
3458 09:54:45.046293
3459 09:54:45.049986 CH=1, VrefRange= 0, VrefLevel = 16
3460 09:54:45.053177 TX Bit0 (981~1002) 22 991, Bit8 (968~987) 20 977,
3461 09:54:45.056464 TX Bit1 (979~1001) 23 990, Bit9 (969~987) 19 978,
3462 09:54:45.063130 TX Bit2 (978~999) 22 988, Bit10 (970~990) 21 980,
3463 09:54:45.066039 TX Bit3 (977~997) 21 987, Bit11 (972~991) 20 981,
3464 09:54:45.069155 TX Bit4 (979~1000) 22 989, Bit12 (971~991) 21 981,
3465 09:54:45.075942 TX Bit5 (980~1002) 23 991, Bit13 (972~992) 21 982,
3466 09:54:45.079672 TX Bit6 (979~1001) 23 990, Bit14 (971~990) 20 980,
3467 09:54:45.086122 TX Bit7 (981~1000) 20 990, Bit15 (966~984) 19 975,
3468 09:54:45.086643
3469 09:54:45.086968 Write Rank1 MR14 =0x12
3470 09:54:45.096918
3471 09:54:45.097426 CH=1, VrefRange= 0, VrefLevel = 18
3472 09:54:45.103558 TX Bit0 (980~1003) 24 991, Bit8 (968~988) 21 978,
3473 09:54:45.106862 TX Bit1 (979~1001) 23 990, Bit9 (969~988) 20 978,
3474 09:54:45.113718 TX Bit2 (978~999) 22 988, Bit10 (970~991) 22 980,
3475 09:54:45.116743 TX Bit3 (977~998) 22 987, Bit11 (971~991) 21 981,
3476 09:54:45.119943 TX Bit4 (979~1001) 23 990, Bit12 (971~991) 21 981,
3477 09:54:45.127012 TX Bit5 (980~1003) 24 991, Bit13 (971~992) 22 981,
3478 09:54:45.129929 TX Bit6 (979~1001) 23 990, Bit14 (971~991) 21 981,
3479 09:54:45.136669 TX Bit7 (980~1000) 21 990, Bit15 (966~985) 20 975,
3480 09:54:45.137177
3481 09:54:45.137501 Write Rank1 MR14 =0x14
3482 09:54:45.147306
3483 09:54:45.150809 CH=1, VrefRange= 0, VrefLevel = 20
3484 09:54:45.154075 TX Bit0 (980~1003) 24 991, Bit8 (968~989) 22 978,
3485 09:54:45.156952 TX Bit1 (979~1002) 24 990, Bit9 (969~988) 20 978,
3486 09:54:45.163904 TX Bit2 (978~1000) 23 989, Bit10 (970~991) 22 980,
3487 09:54:45.166772 TX Bit3 (976~998) 23 987, Bit11 (971~992) 22 981,
3488 09:54:45.170436 TX Bit4 (978~1001) 24 989, Bit12 (971~991) 21 981,
3489 09:54:45.177314 TX Bit5 (980~1003) 24 991, Bit13 (971~992) 22 981,
3490 09:54:45.180548 TX Bit6 (979~1002) 24 990, Bit14 (970~991) 22 980,
3491 09:54:45.186934 TX Bit7 (980~1001) 22 990, Bit15 (966~985) 20 975,
3492 09:54:45.187493
3493 09:54:45.187832 Write Rank1 MR14 =0x16
3494 09:54:45.198217
3495 09:54:45.201451 CH=1, VrefRange= 0, VrefLevel = 22
3496 09:54:45.204550 TX Bit0 (979~1005) 27 992, Bit8 (968~990) 23 979,
3497 09:54:45.208255 TX Bit1 (979~1002) 24 990, Bit9 (969~989) 21 979,
3498 09:54:45.214746 TX Bit2 (977~1000) 24 988, Bit10 (970~991) 22 980,
3499 09:54:45.218073 TX Bit3 (976~998) 23 987, Bit11 (970~992) 23 981,
3500 09:54:45.221148 TX Bit4 (978~1002) 25 990, Bit12 (970~992) 23 981,
3501 09:54:45.227837 TX Bit5 (979~1004) 26 991, Bit13 (971~992) 22 981,
3502 09:54:45.231431 TX Bit6 (979~1003) 25 991, Bit14 (970~991) 22 980,
3503 09:54:45.237674 TX Bit7 (980~1001) 22 990, Bit15 (966~985) 20 975,
3504 09:54:45.238188
3505 09:54:45.238512 Write Rank1 MR14 =0x18
3506 09:54:45.249272
3507 09:54:45.252089 CH=1, VrefRange= 0, VrefLevel = 24
3508 09:54:45.255669 TX Bit0 (980~1005) 26 992, Bit8 (968~990) 23 979,
3509 09:54:45.259109 TX Bit1 (978~1003) 26 990, Bit9 (968~990) 23 979,
3510 09:54:45.265313 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3511 09:54:45.269043 TX Bit3 (976~998) 23 987, Bit11 (970~992) 23 981,
3512 09:54:45.272167 TX Bit4 (978~1002) 25 990, Bit12 (970~992) 23 981,
3513 09:54:45.278685 TX Bit5 (979~1004) 26 991, Bit13 (971~993) 23 982,
3514 09:54:45.282075 TX Bit6 (979~1003) 25 991, Bit14 (970~992) 23 981,
3515 09:54:45.288549 TX Bit7 (980~1002) 23 991, Bit15 (965~986) 22 975,
3516 09:54:45.289101
3517 09:54:45.289670 Write Rank1 MR14 =0x1a
3518 09:54:45.300333
3519 09:54:45.300878 CH=1, VrefRange= 0, VrefLevel = 26
3520 09:54:45.306025 TX Bit0 (979~1005) 27 992, Bit8 (968~991) 24 979,
3521 09:54:45.309755 TX Bit1 (978~1003) 26 990, Bit9 (968~990) 23 979,
3522 09:54:45.316199 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3523 09:54:45.319980 TX Bit3 (976~999) 24 987, Bit11 (970~993) 24 981,
3524 09:54:45.323135 TX Bit4 (978~1003) 26 990, Bit12 (970~992) 23 981,
3525 09:54:45.329898 TX Bit5 (979~1005) 27 992, Bit13 (970~993) 24 981,
3526 09:54:45.332893 TX Bit6 (978~1003) 26 990, Bit14 (970~992) 23 981,
3527 09:54:45.339837 TX Bit7 (979~1002) 24 990, Bit15 (965~986) 22 975,
3528 09:54:45.340574
3529 09:54:45.341064 Write Rank1 MR14 =0x1c
3530 09:54:45.350718
3531 09:54:45.351291 CH=1, VrefRange= 0, VrefLevel = 28
3532 09:54:45.357378 TX Bit0 (979~1006) 28 992, Bit8 (967~991) 25 979,
3533 09:54:45.360790 TX Bit1 (978~1004) 27 991, Bit9 (967~991) 25 979,
3534 09:54:45.367573 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
3535 09:54:45.370887 TX Bit3 (975~999) 25 987, Bit11 (970~993) 24 981,
3536 09:54:45.373972 TX Bit4 (978~1004) 27 991, Bit12 (970~992) 23 981,
3537 09:54:45.380380 TX Bit5 (979~1006) 28 992, Bit13 (970~993) 24 981,
3538 09:54:45.383728 TX Bit6 (978~1004) 27 991, Bit14 (970~992) 23 981,
3539 09:54:45.390586 TX Bit7 (978~1002) 25 990, Bit15 (964~987) 24 975,
3540 09:54:45.391119
3541 09:54:45.391637 Write Rank1 MR14 =0x1e
3542 09:54:45.402041
3543 09:54:45.405112 CH=1, VrefRange= 0, VrefLevel = 30
3544 09:54:45.408569 TX Bit0 (979~1006) 28 992, Bit8 (967~991) 25 979,
3545 09:54:45.412074 TX Bit1 (978~1004) 27 991, Bit9 (967~990) 24 978,
3546 09:54:45.418300 TX Bit2 (977~1002) 26 989, Bit10 (969~993) 25 981,
3547 09:54:45.421180 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
3548 09:54:45.425227 TX Bit4 (978~1004) 27 991, Bit12 (970~993) 24 981,
3549 09:54:45.431255 TX Bit5 (979~1005) 27 992, Bit13 (970~993) 24 981,
3550 09:54:45.434674 TX Bit6 (978~1005) 28 991, Bit14 (969~993) 25 981,
3551 09:54:45.441285 TX Bit7 (978~1003) 26 990, Bit15 (964~987) 24 975,
3552 09:54:45.441730
3553 09:54:45.442163 Write Rank1 MR14 =0x20
3554 09:54:45.452867
3555 09:54:45.456064 CH=1, VrefRange= 0, VrefLevel = 32
3556 09:54:45.459104 TX Bit0 (979~1006) 28 992, Bit8 (967~991) 25 979,
3557 09:54:45.462533 TX Bit1 (978~1004) 27 991, Bit9 (967~990) 24 978,
3558 09:54:45.469439 TX Bit2 (977~1002) 26 989, Bit10 (969~993) 25 981,
3559 09:54:45.472807 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
3560 09:54:45.475778 TX Bit4 (978~1004) 27 991, Bit12 (970~993) 24 981,
3561 09:54:45.482407 TX Bit5 (979~1005) 27 992, Bit13 (970~993) 24 981,
3562 09:54:45.485812 TX Bit6 (978~1005) 28 991, Bit14 (969~993) 25 981,
3563 09:54:45.492163 TX Bit7 (978~1003) 26 990, Bit15 (964~987) 24 975,
3564 09:54:45.492665
3565 09:54:45.492994 Write Rank1 MR14 =0x22
3566 09:54:45.503624
3567 09:54:45.506740 CH=1, VrefRange= 0, VrefLevel = 34
3568 09:54:45.510453 TX Bit0 (979~1006) 28 992, Bit8 (967~991) 25 979,
3569 09:54:45.513770 TX Bit1 (978~1004) 27 991, Bit9 (967~990) 24 978,
3570 09:54:45.520343 TX Bit2 (977~1002) 26 989, Bit10 (969~993) 25 981,
3571 09:54:45.523546 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
3572 09:54:45.526787 TX Bit4 (978~1004) 27 991, Bit12 (970~993) 24 981,
3573 09:54:45.533816 TX Bit5 (979~1005) 27 992, Bit13 (970~993) 24 981,
3574 09:54:45.537092 TX Bit6 (978~1005) 28 991, Bit14 (969~993) 25 981,
3575 09:54:45.543733 TX Bit7 (978~1003) 26 990, Bit15 (964~987) 24 975,
3576 09:54:45.544237
3577 09:54:45.544563 Write Rank1 MR14 =0x24
3578 09:54:45.554353
3579 09:54:45.557996 CH=1, VrefRange= 0, VrefLevel = 36
3580 09:54:45.560891 TX Bit0 (979~1006) 28 992, Bit8 (967~991) 25 979,
3581 09:54:45.564394 TX Bit1 (978~1004) 27 991, Bit9 (967~990) 24 978,
3582 09:54:45.571140 TX Bit2 (977~1002) 26 989, Bit10 (969~993) 25 981,
3583 09:54:45.574916 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
3584 09:54:45.577892 TX Bit4 (978~1004) 27 991, Bit12 (970~993) 24 981,
3585 09:54:45.584298 TX Bit5 (979~1005) 27 992, Bit13 (970~993) 24 981,
3586 09:54:45.587851 TX Bit6 (978~1005) 28 991, Bit14 (969~993) 25 981,
3587 09:54:45.594435 TX Bit7 (978~1003) 26 990, Bit15 (964~987) 24 975,
3588 09:54:45.594929
3589 09:54:45.595251 Write Rank1 MR14 =0x26
3590 09:54:45.605545
3591 09:54:45.608860 CH=1, VrefRange= 0, VrefLevel = 38
3592 09:54:45.611775 TX Bit0 (979~1006) 28 992, Bit8 (967~991) 25 979,
3593 09:54:45.615434 TX Bit1 (978~1004) 27 991, Bit9 (967~990) 24 978,
3594 09:54:45.622414 TX Bit2 (977~1002) 26 989, Bit10 (969~993) 25 981,
3595 09:54:45.625637 TX Bit3 (975~999) 25 987, Bit11 (969~993) 25 981,
3596 09:54:45.629080 TX Bit4 (978~1004) 27 991, Bit12 (970~993) 24 981,
3597 09:54:45.634908 TX Bit5 (979~1005) 27 992, Bit13 (970~993) 24 981,
3598 09:54:45.638058 TX Bit6 (978~1005) 28 991, Bit14 (969~993) 25 981,
3599 09:54:45.644764 TX Bit7 (978~1003) 26 990, Bit15 (964~987) 24 975,
3600 09:54:45.645178
3601 09:54:45.645499
3602 09:54:45.648208 TX Vref found, early break! 382< 389
3603 09:54:45.651891 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
3604 09:54:45.655065 u1DelayCellOfst[0]=6 cells (5 PI)
3605 09:54:45.658937 u1DelayCellOfst[1]=5 cells (4 PI)
3606 09:54:45.661955 u1DelayCellOfst[2]=2 cells (2 PI)
3607 09:54:45.665038 u1DelayCellOfst[3]=0 cells (0 PI)
3608 09:54:45.668501 u1DelayCellOfst[4]=5 cells (4 PI)
3609 09:54:45.672116 u1DelayCellOfst[5]=6 cells (5 PI)
3610 09:54:45.672538 u1DelayCellOfst[6]=5 cells (4 PI)
3611 09:54:45.675149 u1DelayCellOfst[7]=3 cells (3 PI)
3612 09:54:45.678399 Byte0, DQ PI dly=987, DQM PI dly= 989
3613 09:54:45.685492 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
3614 09:54:45.685946
3615 09:54:45.688513 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
3616 09:54:45.688931
3617 09:54:45.691789 u1DelayCellOfst[8]=5 cells (4 PI)
3618 09:54:45.695230 u1DelayCellOfst[9]=3 cells (3 PI)
3619 09:54:45.698569 u1DelayCellOfst[10]=7 cells (6 PI)
3620 09:54:45.702113 u1DelayCellOfst[11]=7 cells (6 PI)
3621 09:54:45.705269 u1DelayCellOfst[12]=7 cells (6 PI)
3622 09:54:45.708399 u1DelayCellOfst[13]=7 cells (6 PI)
3623 09:54:45.709040 u1DelayCellOfst[14]=7 cells (6 PI)
3624 09:54:45.712054 u1DelayCellOfst[15]=0 cells (0 PI)
3625 09:54:45.715194 Byte1, DQ PI dly=975, DQM PI dly= 978
3626 09:54:45.721732 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15)
3627 09:54:45.722151
3628 09:54:45.725573 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15)
3629 09:54:45.725990
3630 09:54:45.728409 Write Rank1 MR14 =0x1e
3631 09:54:45.728824
3632 09:54:45.729149 Final TX Range 0 Vref 30
3633 09:54:45.731704
3634 09:54:45.735142 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3635 09:54:45.738749
3636 09:54:45.741811 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3637 09:54:45.751904 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3638 09:54:45.758527 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3639 09:54:45.759072 Write Rank1 MR3 =0xb0
3640 09:54:45.762055 DramC Write-DBI on
3641 09:54:45.762469 ==
3642 09:54:45.765184 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3643 09:54:45.768295 fsp= 1, odt_onoff= 1, Byte mode= 0
3644 09:54:45.768713 ==
3645 09:54:45.775309 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3646 09:54:45.775892
3647 09:54:45.778274 Begin, DQ Scan Range 698~762
3648 09:54:45.778788
3649 09:54:45.779117
3650 09:54:45.779457 TX Vref Scan disable
3651 09:54:45.782205 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3652 09:54:45.785075 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3653 09:54:45.788424 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3654 09:54:45.791828 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3655 09:54:45.798577 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3656 09:54:45.801772 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3657 09:54:45.805529 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3658 09:54:45.808091 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3659 09:54:45.811948 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3660 09:54:45.815486 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3661 09:54:45.818449 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3662 09:54:45.821647 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3663 09:54:45.825452 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3664 09:54:45.828164 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3665 09:54:45.831681 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3666 09:54:45.834831 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3667 09:54:45.838386 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3668 09:54:45.841683 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3669 09:54:45.845221 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3670 09:54:45.848312 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3671 09:54:45.852007 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3672 09:54:45.854932 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3673 09:54:45.858654 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3674 09:54:45.861812 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3675 09:54:45.870416 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
3676 09:54:45.874041 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3677 09:54:45.877060 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3678 09:54:45.880371 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3679 09:54:45.883904 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3680 09:54:45.887023 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3681 09:54:45.890406 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3682 09:54:45.893696 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3683 09:54:45.897044 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3684 09:54:45.900827 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3685 09:54:45.903595 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3686 09:54:45.907095 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3687 09:54:45.910097 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3688 09:54:45.913488 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3689 09:54:45.916796 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3690 09:54:45.923439 751 |2 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
3691 09:54:45.926662 Byte0, DQ PI dly=736, DQM PI dly= 736
3692 09:54:45.929973 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 32)
3693 09:54:45.930391
3694 09:54:45.933754 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 32)
3695 09:54:45.934306
3696 09:54:45.937264 Byte1, DQ PI dly=723, DQM PI dly= 723
3697 09:54:45.943239 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
3698 09:54:45.943707
3699 09:54:45.946833 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
3700 09:54:45.947250
3701 09:54:45.953120 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3702 09:54:45.960013 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3703 09:54:45.966362 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3704 09:54:45.969585 Write Rank1 MR3 =0x30
3705 09:54:45.969881 DramC Write-DBI off
3706 09:54:45.970113
3707 09:54:45.973052 [DATLAT]
3708 09:54:45.976130 Freq=1600, CH1 RK1, use_rxtx_scan=0
3709 09:54:45.976435
3710 09:54:45.976613 DATLAT Default: 0x10
3711 09:54:45.979758 7, 0xFFFF, sum=0
3712 09:54:45.980020 8, 0xFFFF, sum=0
3713 09:54:45.982855 9, 0xFFFF, sum=0
3714 09:54:45.983116 10, 0xFFFF, sum=0
3715 09:54:45.986294 11, 0xFFFF, sum=0
3716 09:54:45.986531 12, 0xFFFF, sum=0
3717 09:54:45.989668 13, 0xFFFF, sum=0
3718 09:54:45.989850 14, 0x0, sum=1
3719 09:54:45.989994 15, 0x0, sum=2
3720 09:54:45.993051 16, 0x0, sum=3
3721 09:54:45.993233 17, 0x0, sum=4
3722 09:54:45.996436 pattern=2 first_step=14 total pass=5 best_step=16
3723 09:54:45.999842 ==
3724 09:54:46.003111 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3725 09:54:46.006312 fsp= 1, odt_onoff= 1, Byte mode= 0
3726 09:54:46.006546 ==
3727 09:54:46.009564 Start DQ dly to find pass range UseTestEngine =1
3728 09:54:46.012906 x-axis: bit #, y-axis: DQ dly (-127~63)
3729 09:54:46.016299 RX Vref Scan = 0
3730 09:54:46.019640 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3731 09:54:46.023002 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3732 09:54:46.026588 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3733 09:54:46.027106 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3734 09:54:46.029881 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3735 09:54:46.033252 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3736 09:54:46.036560 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3737 09:54:46.039952 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3738 09:54:46.043057 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3739 09:54:46.046915 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3740 09:54:46.049900 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3741 09:54:46.050471 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3742 09:54:46.053403 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3743 09:54:46.056615 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3744 09:54:46.060082 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3745 09:54:46.062817 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3746 09:54:46.066742 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3747 09:54:46.070111 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3748 09:54:46.073260 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3749 09:54:46.073726 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3750 09:54:46.076488 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3751 09:54:46.079988 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3752 09:54:46.083218 -4, [0] xxxxxxxx xxxxxxxo [MSB]
3753 09:54:46.086559 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3754 09:54:46.089364 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3755 09:54:46.092899 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3756 09:54:46.093322 0, [0] xxooxxxx ooxxxxxo [MSB]
3757 09:54:46.096415 1, [0] xxooxxxx ooxxxxxo [MSB]
3758 09:54:46.099802 2, [0] xxooxxxx ooxxxxxo [MSB]
3759 09:54:46.103143 3, [0] oxooxxxo oooxxxxo [MSB]
3760 09:54:46.106505 4, [0] oooooxxo ooooooxo [MSB]
3761 09:54:46.109301 32, [0] oooooooo ooooooox [MSB]
3762 09:54:46.112978 33, [0] oooooooo ooooooox [MSB]
3763 09:54:46.116012 34, [0] oooooooo ooooooox [MSB]
3764 09:54:46.119462 35, [0] oooxoooo oxooooox [MSB]
3765 09:54:46.123567 36, [0] oooxoooo xxooooox [MSB]
3766 09:54:46.126114 37, [0] ooxxoooo xxooooox [MSB]
3767 09:54:46.126627 38, [0] ooxxoooo xxooooox [MSB]
3768 09:54:46.129458 39, [0] ooxxooox xxxoooox [MSB]
3769 09:54:46.133336 40, [0] oxxxxoox xxxoooox [MSB]
3770 09:54:46.136676 41, [0] xxxxxxox xxxxxxxx [MSB]
3771 09:54:46.140056 42, [0] xxxxxxxx xxxxxxxx [MSB]
3772 09:54:46.142481 iDelay=42, Bit 0, Center 21 (3 ~ 40) 38
3773 09:54:46.146236 iDelay=42, Bit 1, Center 21 (4 ~ 39) 36
3774 09:54:46.149412 iDelay=42, Bit 2, Center 18 (0 ~ 36) 37
3775 09:54:46.153328 iDelay=42, Bit 3, Center 16 (-2 ~ 34) 37
3776 09:54:46.156483 iDelay=42, Bit 4, Center 21 (4 ~ 39) 36
3777 09:54:46.159835 iDelay=42, Bit 5, Center 22 (5 ~ 40) 36
3778 09:54:46.162964 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
3779 09:54:46.165913 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
3780 09:54:46.169651 iDelay=42, Bit 8, Center 17 (0 ~ 35) 36
3781 09:54:46.176259 iDelay=42, Bit 9, Center 16 (-1 ~ 34) 36
3782 09:54:46.179556 iDelay=42, Bit 10, Center 20 (3 ~ 38) 36
3783 09:54:46.182724 iDelay=42, Bit 11, Center 22 (4 ~ 40) 37
3784 09:54:46.185715 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
3785 09:54:46.189027 iDelay=42, Bit 13, Center 22 (4 ~ 40) 37
3786 09:54:46.192327 iDelay=42, Bit 14, Center 22 (5 ~ 40) 36
3787 09:54:46.195622 iDelay=42, Bit 15, Center 13 (-4 ~ 31) 36
3788 09:54:46.196037 ==
3789 09:54:46.202921 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3790 09:54:46.205985 fsp= 1, odt_onoff= 1, Byte mode= 0
3791 09:54:46.206583 ==
3792 09:54:46.206972 DQS Delay:
3793 09:54:46.209208 DQS0 = 0, DQS1 = 0
3794 09:54:46.209671 DQM Delay:
3795 09:54:46.210088 DQM0 = 20, DQM1 = 19
3796 09:54:46.212715 DQ Delay:
3797 09:54:46.216017 DQ0 =21, DQ1 =21, DQ2 =18, DQ3 =16
3798 09:54:46.219012 DQ4 =21, DQ5 =22, DQ6 =23, DQ7 =20
3799 09:54:46.222271 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =22
3800 09:54:46.226007 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =13
3801 09:54:46.226518
3802 09:54:46.226843
3803 09:54:46.227144
3804 09:54:46.229252 [DramC_TX_OE_Calibration] TA2
3805 09:54:46.232549 Original DQ_B0 (3 6) =30, OEN = 27
3806 09:54:46.232970 Original DQ_B1 (3 6) =30, OEN = 27
3807 09:54:46.235816 23, 0x0, End_B0=23 End_B1=23
3808 09:54:46.239283 24, 0x0, End_B0=24 End_B1=24
3809 09:54:46.242571 25, 0x0, End_B0=25 End_B1=25
3810 09:54:46.245763 26, 0x0, End_B0=26 End_B1=26
3811 09:54:46.246276 27, 0x0, End_B0=27 End_B1=27
3812 09:54:46.249121 28, 0x0, End_B0=28 End_B1=28
3813 09:54:46.252320 29, 0x0, End_B0=29 End_B1=29
3814 09:54:46.255648 30, 0x0, End_B0=30 End_B1=30
3815 09:54:46.258619 31, 0xFFFF, End_B0=30 End_B1=30
3816 09:54:46.261879 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3817 09:54:46.268630 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3818 09:54:46.269142
3819 09:54:46.269468
3820 09:54:46.272178 Write Rank1 MR23 =0x3f
3821 09:54:46.272593 [DQSOSC]
3822 09:54:46.278306 [DQSOSCAuto] RK1, (LSB)MR18= 0xcece, (MSB)MR19= 0x202, tDQSOscB0 = 438 ps tDQSOscB1 = 438 ps
3823 09:54:46.285277 CH1_RK1: MR19=0x202, MR18=0xCECE, DQSOSC=438, MR23=63, INC=12, DEC=19
3824 09:54:46.288583 Write Rank1 MR23 =0x3f
3825 09:54:46.289000 [DQSOSC]
3826 09:54:46.298810 [DQSOSCAuto] RK1, (LSB)MR18= 0xcdcd, (MSB)MR19= 0x202, tDQSOscB0 = 439 ps tDQSOscB1 = 439 ps
3827 09:54:46.299329 CH1 RK1: MR19=202, MR18=CDCD
3828 09:54:46.302382 [RxdqsGatingPostProcess] freq 1600
3829 09:54:46.308644 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3830 09:54:46.309163 Rank: 0
3831 09:54:46.312027 best DQS0 dly(2T, 0.5T) = (2, 6)
3832 09:54:46.315462 best DQS1 dly(2T, 0.5T) = (2, 6)
3833 09:54:46.318616 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3834 09:54:46.322282 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3835 09:54:46.322838 Rank: 1
3836 09:54:46.325284 best DQS0 dly(2T, 0.5T) = (2, 5)
3837 09:54:46.328842 best DQS1 dly(2T, 0.5T) = (2, 6)
3838 09:54:46.331670 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3839 09:54:46.335047 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3840 09:54:46.338570 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3841 09:54:46.341855 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3842 09:54:46.348715 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3843 09:54:46.349276
3844 09:54:46.349612
3845 09:54:46.351319 [Calibration Summary] Freqency 1600
3846 09:54:46.351781 CH 0, Rank 0
3847 09:54:46.352189 All Pass.
3848 09:54:46.352497
3849 09:54:46.355279 CH 0, Rank 1
3850 09:54:46.355795 All Pass.
3851 09:54:46.356127
3852 09:54:46.356429 CH 1, Rank 0
3853 09:54:46.357971 All Pass.
3854 09:54:46.358388
3855 09:54:46.358748 CH 1, Rank 1
3856 09:54:46.359131 All Pass.
3857 09:54:46.359468
3858 09:54:46.364835 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3859 09:54:46.375180 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3860 09:54:46.381798 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3861 09:54:46.382321 Write Rank0 MR3 =0xb0
3862 09:54:46.388332 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3863 09:54:46.394785 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3864 09:54:46.401568 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3865 09:54:46.404880 Write Rank1 MR3 =0xb0
3866 09:54:46.411453 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3867 09:54:46.418102 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3868 09:54:46.424890 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3869 09:54:46.428565 Write Rank0 MR3 =0xb0
3870 09:54:46.435073 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3871 09:54:46.441549 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3872 09:54:46.448408 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3873 09:54:46.451637 Write Rank1 MR3 =0xb0
3874 09:54:46.452119 DramC Write-DBI on
3875 09:54:46.454691 [GetDramInforAfterCalByMRR] Vendor 6.
3876 09:54:46.458421 [GetDramInforAfterCalByMRR] Revision 505.
3877 09:54:46.459008 MR8 1111
3878 09:54:46.464632 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3879 09:54:46.465050 MR8 1111
3880 09:54:46.471571 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3881 09:54:46.472107 MR8 1111
3882 09:54:46.475153 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3883 09:54:46.478382 MR8 1111
3884 09:54:46.481460 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3885 09:54:46.491429 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3886 09:54:46.491959 Write Rank0 MR13 =0xd0
3887 09:54:46.494654 Write Rank1 MR13 =0xd0
3888 09:54:46.497889 Write Rank0 MR13 =0xd0
3889 09:54:46.498339 Write Rank1 MR13 =0xd0
3890 09:54:46.501343 Save calibration result to emmc
3891 09:54:46.501852
3892 09:54:46.502181
3893 09:54:46.504520 [DramcModeReg_Check] Freq_1600, FSP_1
3894 09:54:46.508428 FSP_1, CH_0, RK0
3895 09:54:46.508941 Write Rank0 MR13 =0xd8
3896 09:54:46.511506 MR12 = 0x5e (global = 0x5e) match
3897 09:54:46.514836 MR14 = 0x1c (global = 0x1c) match
3898 09:54:46.518424 FSP_1, CH_0, RK1
3899 09:54:46.518943 Write Rank1 MR13 =0xd8
3900 09:54:46.521443 MR12 = 0x5a (global = 0x5a) match
3901 09:54:46.524740 MR14 = 0x1e (global = 0x1e) match
3902 09:54:46.528278 FSP_1, CH_1, RK0
3903 09:54:46.528795 Write Rank0 MR13 =0xd8
3904 09:54:46.531556 MR12 = 0x5e (global = 0x5e) match
3905 09:54:46.535071 MR14 = 0x1e (global = 0x1e) match
3906 09:54:46.538080 FSP_1, CH_1, RK1
3907 09:54:46.538596 Write Rank1 MR13 =0xd8
3908 09:54:46.541416 MR12 = 0x60 (global = 0x60) match
3909 09:54:46.544547 MR14 = 0x1e (global = 0x1e) match
3910 09:54:46.544969
3911 09:54:46.551350 [MEM_TEST] 02: After DFS, before run time config
3912 09:54:46.557982 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3913 09:54:46.558502
3914 09:54:46.561107 [TA2_TEST]
3915 09:54:46.561615 === TA2 HW
3916 09:54:46.561940 TA2 PAT: XTALK
3917 09:54:46.567928 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3918 09:54:46.570826 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3919 09:54:46.578173 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3920 09:54:46.581070 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3921 09:54:46.581627
3922 09:54:46.581984
3923 09:54:46.584320 Settings after calibration
3924 09:54:46.584774
3925 09:54:46.587772 [DramcRunTimeConfig]
3926 09:54:46.591373 TransferPLLToSPMControl - MODE SW PHYPLL
3927 09:54:46.591976 TX_TRACKING: ON
3928 09:54:46.594730 RX_TRACKING: ON
3929 09:54:46.595545 HW_GATING: ON
3930 09:54:46.597543 HW_GATING DBG: OFF
3931 09:54:46.597996 ddr_geometry:1
3932 09:54:46.598444 ddr_geometry:1
3933 09:54:46.601191 ddr_geometry:1
3934 09:54:46.601745 ddr_geometry:1
3935 09:54:46.604164 ddr_geometry:1
3936 09:54:46.604613 ddr_geometry:1
3937 09:54:46.607548 ddr_geometry:1
3938 09:54:46.607986 ddr_geometry:1
3939 09:54:46.610989 High Freq DUMMY_READ_FOR_TRACKING: ON
3940 09:54:46.614448 ZQCS_ENABLE_LP4: OFF
3941 09:54:46.614951 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
3942 09:54:46.617750 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
3943 09:54:46.620810 SPM_CONTROL_AFTERK: ON
3944 09:54:46.624282 IMPEDANCE_TRACKING: ON
3945 09:54:46.624740 TEMP_SENSOR: ON
3946 09:54:46.627633 PER_BANK_REFRESH: ON
3947 09:54:46.628047 HW_SAVE_FOR_SR: ON
3948 09:54:46.631288 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3949 09:54:46.634472 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
3950 09:54:46.637948 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
3951 09:54:46.641378 Read ODT Tracking: ON
3952 09:54:46.641921 =========================
3953 09:54:46.644631
3954 09:54:46.645086 [TA2_TEST]
3955 09:54:46.645444 === TA2 HW
3956 09:54:46.651050 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
3957 09:54:46.654240 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
3958 09:54:46.660797 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
3959 09:54:46.663956 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
3960 09:54:46.664416
3961 09:54:46.667677 [MEM_TEST] 03: After run time config
3962 09:54:46.678799 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3963 09:54:46.681831 [complex_mem_test] start addr:0x40024000, len:131072
3964 09:54:46.886219 1st complex R/W mem test pass
3965 09:54:46.892840 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
3966 09:54:46.896338 sync preloader write leveling
3967 09:54:46.899701 sync preloader cbt_mr12
3968 09:54:46.900215 sync preloader cbt_clk_dly
3969 09:54:46.902860 sync preloader cbt_cmd_dly
3970 09:54:46.906606 sync preloader cbt_cs
3971 09:54:46.909707 sync preloader cbt_ca_perbit_delay
3972 09:54:46.910181 sync preloader clk_delay
3973 09:54:46.912912 sync preloader dqs_delay
3974 09:54:46.916107 sync preloader u1Gating2T_Save
3975 09:54:46.919361 sync preloader u1Gating05T_Save
3976 09:54:46.922940 sync preloader u1Gatingfine_tune_Save
3977 09:54:46.926519 sync preloader u1Gatingucpass_count_Save
3978 09:54:46.929821 sync preloader u1TxWindowPerbitVref_Save
3979 09:54:46.932973 sync preloader u1TxCenter_min_Save
3980 09:54:46.936103 sync preloader u1TxCenter_max_Save
3981 09:54:46.939007 sync preloader u1Txwin_center_Save
3982 09:54:46.942732 sync preloader u1Txfirst_pass_Save
3983 09:54:46.945658 sync preloader u1Txlast_pass_Save
3984 09:54:46.946120 sync preloader u1RxDatlat_Save
3985 09:54:46.949456 sync preloader u1RxWinPerbitVref_Save
3986 09:54:46.955786 sync preloader u1RxWinPerbitDQ_firsbypass_Save
3987 09:54:46.959371 sync preloader u1RxWinPerbitDQ_lastbypass_Save
3988 09:54:46.962984 sync preloader delay_cell_unit
3989 09:54:46.969215 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
3990 09:54:46.972441 sync preloader write leveling
3991 09:54:46.972995 sync preloader cbt_mr12
3992 09:54:46.975623 sync preloader cbt_clk_dly
3993 09:54:46.979228 sync preloader cbt_cmd_dly
3994 09:54:46.979734 sync preloader cbt_cs
3995 09:54:46.982599 sync preloader cbt_ca_perbit_delay
3996 09:54:46.985970 sync preloader clk_delay
3997 09:54:46.989465 sync preloader dqs_delay
3998 09:54:46.989971 sync preloader u1Gating2T_Save
3999 09:54:46.992827 sync preloader u1Gating05T_Save
4000 09:54:46.995948 sync preloader u1Gatingfine_tune_Save
4001 09:54:46.999565 sync preloader u1Gatingucpass_count_Save
4002 09:54:47.002630 sync preloader u1TxWindowPerbitVref_Save
4003 09:54:47.006291 sync preloader u1TxCenter_min_Save
4004 09:54:47.009153 sync preloader u1TxCenter_max_Save
4005 09:54:47.013118 sync preloader u1Txwin_center_Save
4006 09:54:47.015975 sync preloader u1Txfirst_pass_Save
4007 09:54:47.019380 sync preloader u1Txlast_pass_Save
4008 09:54:47.022381 sync preloader u1RxDatlat_Save
4009 09:54:47.026074 sync preloader u1RxWinPerbitVref_Save
4010 09:54:47.029481 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4011 09:54:47.032770 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4012 09:54:47.036001 sync preloader delay_cell_unit
4013 09:54:47.042486 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4014 09:54:47.046004 sync preloader write leveling
4015 09:54:47.049792 sync preloader cbt_mr12
4016 09:54:47.050338 sync preloader cbt_clk_dly
4017 09:54:47.052678 sync preloader cbt_cmd_dly
4018 09:54:47.055896 sync preloader cbt_cs
4019 09:54:47.059248 sync preloader cbt_ca_perbit_delay
4020 09:54:47.059909 sync preloader clk_delay
4021 09:54:47.062700 sync preloader dqs_delay
4022 09:54:47.065486 sync preloader u1Gating2T_Save
4023 09:54:47.069227 sync preloader u1Gating05T_Save
4024 09:54:47.072328 sync preloader u1Gatingfine_tune_Save
4025 09:54:47.075748 sync preloader u1Gatingucpass_count_Save
4026 09:54:47.079225 sync preloader u1TxWindowPerbitVref_Save
4027 09:54:47.082646 sync preloader u1TxCenter_min_Save
4028 09:54:47.085542 sync preloader u1TxCenter_max_Save
4029 09:54:47.089411 sync preloader u1Txwin_center_Save
4030 09:54:47.092600 sync preloader u1Txfirst_pass_Save
4031 09:54:47.095797 sync preloader u1Txlast_pass_Save
4032 09:54:47.096305 sync preloader u1RxDatlat_Save
4033 09:54:47.099167 sync preloader u1RxWinPerbitVref_Save
4034 09:54:47.105941 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4035 09:54:47.109548 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4036 09:54:47.112871 sync preloader delay_cell_unit
4037 09:54:47.115759 just_for_test_dump_coreboot_params dump all params
4038 09:54:47.116220 dump source = 0x0
4039 09:54:47.119505 dump params frequency:1600
4040 09:54:47.122468 dump params rank number:2
4041 09:54:47.122970
4042 09:54:47.125565 dump params write leveling
4043 09:54:47.128929 write leveling[0][0][0] = 0x21
4044 09:54:47.129384 write leveling[0][0][1] = 0x18
4045 09:54:47.132250 write leveling[0][1][0] = 0x1a
4046 09:54:47.135723 write leveling[0][1][1] = 0x17
4047 09:54:47.139066 write leveling[1][0][0] = 0x20
4048 09:54:47.142604 write leveling[1][0][1] = 0x17
4049 09:54:47.143114 write leveling[1][1][0] = 0x23
4050 09:54:47.145964 write leveling[1][1][1] = 0x18
4051 09:54:47.149341 dump params cbt_cs
4052 09:54:47.149895 cbt_cs[0][0] = 0x8
4053 09:54:47.152266 cbt_cs[0][1] = 0x8
4054 09:54:47.152724 cbt_cs[1][0] = 0xb
4055 09:54:47.156044 cbt_cs[1][1] = 0xb
4056 09:54:47.156608 dump params cbt_mr12
4057 09:54:47.159467 cbt_mr12[0][0] = 0x1e
4058 09:54:47.162342 cbt_mr12[0][1] = 0x1a
4059 09:54:47.162802 cbt_mr12[1][0] = 0x1e
4060 09:54:47.165977 cbt_mr12[1][1] = 0x20
4061 09:54:47.166497 dump params tx window
4062 09:54:47.168766 tx_center_min[0][0][0] = 982
4063 09:54:47.172561 tx_center_max[0][0][0] = 989
4064 09:54:47.175512 tx_center_min[0][0][1] = 975
4065 09:54:47.178984 tx_center_max[0][0][1] = 981
4066 09:54:47.179394 tx_center_min[0][1][0] = 979
4067 09:54:47.182465 tx_center_max[0][1][0] = 986
4068 09:54:47.185427 tx_center_min[0][1][1] = 977
4069 09:54:47.189016 tx_center_max[0][1][1] = 982
4070 09:54:47.192319 tx_center_min[1][0][0] = 987
4071 09:54:47.192748 tx_center_max[1][0][0] = 991
4072 09:54:47.195561 tx_center_min[1][0][1] = 974
4073 09:54:47.198950 tx_center_max[1][0][1] = 981
4074 09:54:47.202392 tx_center_min[1][1][0] = 987
4075 09:54:47.206238 tx_center_max[1][1][0] = 992
4076 09:54:47.206759 tx_center_min[1][1][1] = 975
4077 09:54:47.209147 tx_center_max[1][1][1] = 981
4078 09:54:47.212278 dump params tx window
4079 09:54:47.212691 tx_win_center[0][0][0] = 989
4080 09:54:47.215630 tx_first_pass[0][0][0] = 977
4081 09:54:47.219261 tx_last_pass[0][0][0] = 1001
4082 09:54:47.222505 tx_win_center[0][0][1] = 988
4083 09:54:47.225425 tx_first_pass[0][0][1] = 976
4084 09:54:47.225837 tx_last_pass[0][0][1] = 1000
4085 09:54:47.229024 tx_win_center[0][0][2] = 989
4086 09:54:47.232237 tx_first_pass[0][0][2] = 977
4087 09:54:47.235867 tx_last_pass[0][0][2] = 1001
4088 09:54:47.239125 tx_win_center[0][0][3] = 982
4089 09:54:47.239683 tx_first_pass[0][0][3] = 970
4090 09:54:47.242187 tx_last_pass[0][0][3] = 995
4091 09:54:47.246043 tx_win_center[0][0][4] = 988
4092 09:54:47.249406 tx_first_pass[0][0][4] = 976
4093 09:54:47.249915 tx_last_pass[0][0][4] = 1000
4094 09:54:47.252647 tx_win_center[0][0][5] = 986
4095 09:54:47.255571 tx_first_pass[0][0][5] = 974
4096 09:54:47.259321 tx_last_pass[0][0][5] = 998
4097 09:54:47.262480 tx_win_center[0][0][6] = 986
4098 09:54:47.263033 tx_first_pass[0][0][6] = 974
4099 09:54:47.265538 tx_last_pass[0][0][6] = 999
4100 09:54:47.268874 tx_win_center[0][0][7] = 988
4101 09:54:47.272093 tx_first_pass[0][0][7] = 976
4102 09:54:47.272507 tx_last_pass[0][0][7] = 1000
4103 09:54:47.275622 tx_win_center[0][0][8] = 975
4104 09:54:47.278813 tx_first_pass[0][0][8] = 963
4105 09:54:47.282567 tx_last_pass[0][0][8] = 988
4106 09:54:47.285582 tx_win_center[0][0][9] = 978
4107 09:54:47.286123 tx_first_pass[0][0][9] = 967
4108 09:54:47.288963 tx_last_pass[0][0][9] = 990
4109 09:54:47.292122 tx_win_center[0][0][10] = 981
4110 09:54:47.295261 tx_first_pass[0][0][10] = 969
4111 09:54:47.298635 tx_last_pass[0][0][10] = 994
4112 09:54:47.299063 tx_win_center[0][0][11] = 977
4113 09:54:47.301979 tx_first_pass[0][0][11] = 965
4114 09:54:47.305636 tx_last_pass[0][0][11] = 989
4115 09:54:47.308926 tx_win_center[0][0][12] = 979
4116 09:54:47.312396 tx_first_pass[0][0][12] = 967
4117 09:54:47.312939 tx_last_pass[0][0][12] = 991
4118 09:54:47.315263 tx_win_center[0][0][13] = 978
4119 09:54:47.318970 tx_first_pass[0][0][13] = 967
4120 09:54:47.322023 tx_last_pass[0][0][13] = 990
4121 09:54:47.325388 tx_win_center[0][0][14] = 979
4122 09:54:47.325937 tx_first_pass[0][0][14] = 967
4123 09:54:47.328511 tx_last_pass[0][0][14] = 991
4124 09:54:47.331822 tx_win_center[0][0][15] = 981
4125 09:54:47.335186 tx_first_pass[0][0][15] = 969
4126 09:54:47.338639 tx_last_pass[0][0][15] = 993
4127 09:54:47.339185 tx_win_center[0][1][0] = 986
4128 09:54:47.341960 tx_first_pass[0][1][0] = 974
4129 09:54:47.345052 tx_last_pass[0][1][0] = 998
4130 09:54:47.348482 tx_win_center[0][1][1] = 984
4131 09:54:47.351954 tx_first_pass[0][1][1] = 972
4132 09:54:47.352458 tx_last_pass[0][1][1] = 996
4133 09:54:47.355054 tx_win_center[0][1][2] = 986
4134 09:54:47.358304 tx_first_pass[0][1][2] = 974
4135 09:54:47.361662 tx_last_pass[0][1][2] = 998
4136 09:54:47.362074 tx_win_center[0][1][3] = 979
4137 09:54:47.364963 tx_first_pass[0][1][3] = 967
4138 09:54:47.368236 tx_last_pass[0][1][3] = 991
4139 09:54:47.371508 tx_win_center[0][1][4] = 982
4140 09:54:47.374648 tx_first_pass[0][1][4] = 970
4141 09:54:47.375066 tx_last_pass[0][1][4] = 995
4142 09:54:47.378242 tx_win_center[0][1][5] = 980
4143 09:54:47.381440 tx_first_pass[0][1][5] = 968
4144 09:54:47.385297 tx_last_pass[0][1][5] = 993
4145 09:54:47.385819 tx_win_center[0][1][6] = 981
4146 09:54:47.388294 tx_first_pass[0][1][6] = 969
4147 09:54:47.391609 tx_last_pass[0][1][6] = 994
4148 09:54:47.395131 tx_win_center[0][1][7] = 982
4149 09:54:47.398105 tx_first_pass[0][1][7] = 970
4150 09:54:47.398566 tx_last_pass[0][1][7] = 995
4151 09:54:47.401328 tx_win_center[0][1][8] = 977
4152 09:54:47.405109 tx_first_pass[0][1][8] = 965
4153 09:54:47.408196 tx_last_pass[0][1][8] = 989
4154 09:54:47.408744 tx_win_center[0][1][9] = 978
4155 09:54:47.411675 tx_first_pass[0][1][9] = 967
4156 09:54:47.414745 tx_last_pass[0][1][9] = 990
4157 09:54:47.417921 tx_win_center[0][1][10] = 982
4158 09:54:47.421310 tx_first_pass[0][1][10] = 970
4159 09:54:47.421728 tx_last_pass[0][1][10] = 995
4160 09:54:47.424610 tx_win_center[0][1][11] = 977
4161 09:54:47.427854 tx_first_pass[0][1][11] = 966
4162 09:54:47.431519 tx_last_pass[0][1][11] = 989
4163 09:54:47.434314 tx_win_center[0][1][12] = 979
4164 09:54:47.438046 tx_first_pass[0][1][12] = 967
4165 09:54:47.438712 tx_last_pass[0][1][12] = 991
4166 09:54:47.441209 tx_win_center[0][1][13] = 979
4167 09:54:47.444376 tx_first_pass[0][1][13] = 968
4168 09:54:47.447843 tx_last_pass[0][1][13] = 990
4169 09:54:47.451330 tx_win_center[0][1][14] = 979
4170 09:54:47.451923 tx_first_pass[0][1][14] = 968
4171 09:54:47.454403 tx_last_pass[0][1][14] = 991
4172 09:54:47.457911 tx_win_center[0][1][15] = 982
4173 09:54:47.461050 tx_first_pass[0][1][15] = 970
4174 09:54:47.464477 tx_last_pass[0][1][15] = 994
4175 09:54:47.465032 tx_win_center[1][0][0] = 991
4176 09:54:47.468141 tx_first_pass[1][0][0] = 978
4177 09:54:47.471397 tx_last_pass[1][0][0] = 1005
4178 09:54:47.474245 tx_win_center[1][0][1] = 989
4179 09:54:47.477507 tx_first_pass[1][0][1] = 977
4180 09:54:47.478074 tx_last_pass[1][0][1] = 1002
4181 09:54:47.480803 tx_win_center[1][0][2] = 988
4182 09:54:47.484523 tx_first_pass[1][0][2] = 976
4183 09:54:47.488047 tx_last_pass[1][0][2] = 1000
4184 09:54:47.488603 tx_win_center[1][0][3] = 987
4185 09:54:47.491227 tx_first_pass[1][0][3] = 975
4186 09:54:47.494537 tx_last_pass[1][0][3] = 999
4187 09:54:47.497551 tx_win_center[1][0][4] = 990
4188 09:54:47.500914 tx_first_pass[1][0][4] = 978
4189 09:54:47.501368 tx_last_pass[1][0][4] = 1002
4190 09:54:47.504184 tx_win_center[1][0][5] = 990
4191 09:54:47.507588 tx_first_pass[1][0][5] = 978
4192 09:54:47.510655 tx_last_pass[1][0][5] = 1003
4193 09:54:47.514003 tx_win_center[1][0][6] = 989
4194 09:54:47.514550 tx_first_pass[1][0][6] = 977
4195 09:54:47.517422 tx_last_pass[1][0][6] = 1002
4196 09:54:47.520764 tx_win_center[1][0][7] = 990
4197 09:54:47.523955 tx_first_pass[1][0][7] = 978
4198 09:54:47.527495 tx_last_pass[1][0][7] = 1002
4199 09:54:47.527998 tx_win_center[1][0][8] = 979
4200 09:54:47.530869 tx_first_pass[1][0][8] = 967
4201 09:54:47.534240 tx_last_pass[1][0][8] = 991
4202 09:54:47.537186 tx_win_center[1][0][9] = 978
4203 09:54:47.537646 tx_first_pass[1][0][9] = 967
4204 09:54:47.540448 tx_last_pass[1][0][9] = 990
4205 09:54:47.543601 tx_win_center[1][0][10] = 980
4206 09:54:47.546939 tx_first_pass[1][0][10] = 969
4207 09:54:47.550163 tx_last_pass[1][0][10] = 992
4208 09:54:47.550612 tx_win_center[1][0][11] = 981
4209 09:54:47.553760 tx_first_pass[1][0][11] = 969
4210 09:54:47.557114 tx_last_pass[1][0][11] = 993
4211 09:54:47.560436 tx_win_center[1][0][12] = 981
4212 09:54:47.563606 tx_first_pass[1][0][12] = 969
4213 09:54:47.563904 tx_last_pass[1][0][12] = 993
4214 09:54:47.566647 tx_win_center[1][0][13] = 981
4215 09:54:47.570130 tx_first_pass[1][0][13] = 970
4216 09:54:47.573218 tx_last_pass[1][0][13] = 993
4217 09:54:47.576995 tx_win_center[1][0][14] = 981
4218 09:54:47.577177 tx_first_pass[1][0][14] = 969
4219 09:54:47.580334 tx_last_pass[1][0][14] = 993
4220 09:54:47.583704 tx_win_center[1][0][15] = 974
4221 09:54:47.586886 tx_first_pass[1][0][15] = 963
4222 09:54:47.589778 tx_last_pass[1][0][15] = 986
4223 09:54:47.589907 tx_win_center[1][1][0] = 992
4224 09:54:47.593374 tx_first_pass[1][1][0] = 979
4225 09:54:47.596517 tx_last_pass[1][1][0] = 1006
4226 09:54:47.600260 tx_win_center[1][1][1] = 991
4227 09:54:47.603158 tx_first_pass[1][1][1] = 978
4228 09:54:47.603287 tx_last_pass[1][1][1] = 1004
4229 09:54:47.607276 tx_win_center[1][1][2] = 989
4230 09:54:47.610527 tx_first_pass[1][1][2] = 977
4231 09:54:47.613556 tx_last_pass[1][1][2] = 1002
4232 09:54:47.613784 tx_win_center[1][1][3] = 987
4233 09:54:47.616635 tx_first_pass[1][1][3] = 975
4234 09:54:47.619941 tx_last_pass[1][1][3] = 999
4235 09:54:47.623461 tx_win_center[1][1][4] = 991
4236 09:54:47.627003 tx_first_pass[1][1][4] = 978
4237 09:54:47.627280 tx_last_pass[1][1][4] = 1004
4238 09:54:47.630568 tx_win_center[1][1][5] = 992
4239 09:54:47.633702 tx_first_pass[1][1][5] = 979
4240 09:54:47.636767 tx_last_pass[1][1][5] = 1005
4241 09:54:47.640325 tx_win_center[1][1][6] = 991
4242 09:54:47.640781 tx_first_pass[1][1][6] = 978
4243 09:54:47.643640 tx_last_pass[1][1][6] = 1005
4244 09:54:47.646875 tx_win_center[1][1][7] = 990
4245 09:54:47.650664 tx_first_pass[1][1][7] = 978
4246 09:54:47.651225 tx_last_pass[1][1][7] = 1003
4247 09:54:47.653920 tx_win_center[1][1][8] = 979
4248 09:54:47.657290 tx_first_pass[1][1][8] = 967
4249 09:54:47.660420 tx_last_pass[1][1][8] = 991
4250 09:54:47.663469 tx_win_center[1][1][9] = 978
4251 09:54:47.664093 tx_first_pass[1][1][9] = 967
4252 09:54:47.666686 tx_last_pass[1][1][9] = 990
4253 09:54:47.670286 tx_win_center[1][1][10] = 981
4254 09:54:47.673970 tx_first_pass[1][1][10] = 969
4255 09:54:47.677165 tx_last_pass[1][1][10] = 993
4256 09:54:47.677626 tx_win_center[1][1][11] = 981
4257 09:54:47.680209 tx_first_pass[1][1][11] = 969
4258 09:54:47.683477 tx_last_pass[1][1][11] = 993
4259 09:54:47.686979 tx_win_center[1][1][12] = 981
4260 09:54:47.690554 tx_first_pass[1][1][12] = 970
4261 09:54:47.691073 tx_last_pass[1][1][12] = 993
4262 09:54:47.693301 tx_win_center[1][1][13] = 981
4263 09:54:47.696680 tx_first_pass[1][1][13] = 970
4264 09:54:47.699922 tx_last_pass[1][1][13] = 993
4265 09:54:47.703451 tx_win_center[1][1][14] = 981
4266 09:54:47.703867 tx_first_pass[1][1][14] = 969
4267 09:54:47.706628 tx_last_pass[1][1][14] = 993
4268 09:54:47.709833 tx_win_center[1][1][15] = 975
4269 09:54:47.713191 tx_first_pass[1][1][15] = 964
4270 09:54:47.716992 tx_last_pass[1][1][15] = 987
4271 09:54:47.717423 dump params rx window
4272 09:54:47.720003 rx_firspass[0][0][0] = 5
4273 09:54:47.723583 rx_lastpass[0][0][0] = 38
4274 09:54:47.724087 rx_firspass[0][0][1] = 5
4275 09:54:47.726982 rx_lastpass[0][0][1] = 36
4276 09:54:47.730333 rx_firspass[0][0][2] = 6
4277 09:54:47.730852 rx_lastpass[0][0][2] = 36
4278 09:54:47.733505 rx_firspass[0][0][3] = -2
4279 09:54:47.736780 rx_lastpass[0][0][3] = 31
4280 09:54:47.737286 rx_firspass[0][0][4] = 5
4281 09:54:47.740136 rx_lastpass[0][0][4] = 36
4282 09:54:47.743746 rx_firspass[0][0][5] = 2
4283 09:54:47.747062 rx_lastpass[0][0][5] = 32
4284 09:54:47.747633 rx_firspass[0][0][6] = 3
4285 09:54:47.750233 rx_lastpass[0][0][6] = 33
4286 09:54:47.753390 rx_firspass[0][0][7] = 5
4287 09:54:47.753932 rx_lastpass[0][0][7] = 36
4288 09:54:47.756854 rx_firspass[0][0][8] = -3
4289 09:54:47.760355 rx_lastpass[0][0][8] = 32
4290 09:54:47.763165 rx_firspass[0][0][9] = 1
4291 09:54:47.763669 rx_lastpass[0][0][9] = 32
4292 09:54:47.766328 rx_firspass[0][0][10] = 8
4293 09:54:47.770086 rx_lastpass[0][0][10] = 41
4294 09:54:47.770536 rx_firspass[0][0][11] = 1
4295 09:54:47.773411 rx_lastpass[0][0][11] = 32
4296 09:54:47.776834 rx_firspass[0][0][12] = 2
4297 09:54:47.780103 rx_lastpass[0][0][12] = 36
4298 09:54:47.780514 rx_firspass[0][0][13] = 3
4299 09:54:47.783384 rx_lastpass[0][0][13] = 33
4300 09:54:47.786590 rx_firspass[0][0][14] = 2
4301 09:54:47.786996 rx_lastpass[0][0][14] = 37
4302 09:54:47.789830 rx_firspass[0][0][15] = 5
4303 09:54:47.793160 rx_lastpass[0][0][15] = 37
4304 09:54:47.796783 rx_firspass[0][1][0] = 5
4305 09:54:47.797190 rx_lastpass[0][1][0] = 40
4306 09:54:47.799998 rx_firspass[0][1][1] = 5
4307 09:54:47.803346 rx_lastpass[0][1][1] = 38
4308 09:54:47.803797 rx_firspass[0][1][2] = 6
4309 09:54:47.806765 rx_lastpass[0][1][2] = 38
4310 09:54:47.810063 rx_firspass[0][1][3] = -2
4311 09:54:47.813568 rx_lastpass[0][1][3] = 33
4312 09:54:47.814069 rx_firspass[0][1][4] = 5
4313 09:54:47.816468 rx_lastpass[0][1][4] = 39
4314 09:54:47.819790 rx_firspass[0][1][5] = 1
4315 09:54:47.820258 rx_lastpass[0][1][5] = 34
4316 09:54:47.822916 rx_firspass[0][1][6] = 3
4317 09:54:47.826178 rx_lastpass[0][1][6] = 37
4318 09:54:47.826589 rx_firspass[0][1][7] = 3
4319 09:54:47.829783 rx_lastpass[0][1][7] = 38
4320 09:54:47.832873 rx_firspass[0][1][8] = -2
4321 09:54:47.836387 rx_lastpass[0][1][8] = 32
4322 09:54:47.836799 rx_firspass[0][1][9] = 1
4323 09:54:47.839201 rx_lastpass[0][1][9] = 36
4324 09:54:47.842735 rx_firspass[0][1][10] = 7
4325 09:54:47.843144 rx_lastpass[0][1][10] = 43
4326 09:54:47.846108 rx_firspass[0][1][11] = -2
4327 09:54:47.849629 rx_lastpass[0][1][11] = 34
4328 09:54:47.852825 rx_firspass[0][1][12] = 1
4329 09:54:47.853235 rx_lastpass[0][1][12] = 37
4330 09:54:47.856112 rx_firspass[0][1][13] = 2
4331 09:54:47.859223 rx_lastpass[0][1][13] = 35
4332 09:54:47.862694 rx_firspass[0][1][14] = 2
4333 09:54:47.863186 rx_lastpass[0][1][14] = 38
4334 09:54:47.865815 rx_firspass[0][1][15] = 6
4335 09:54:47.869338 rx_lastpass[0][1][15] = 39
4336 09:54:47.870094 rx_firspass[1][0][0] = 4
4337 09:54:47.873040 rx_lastpass[1][0][0] = 39
4338 09:54:47.876075 rx_firspass[1][0][1] = 3
4339 09:54:47.879839 rx_lastpass[1][0][1] = 38
4340 09:54:47.880248 rx_firspass[1][0][2] = 3
4341 09:54:47.882395 rx_lastpass[1][0][2] = 36
4342 09:54:47.885695 rx_firspass[1][0][3] = -1
4343 09:54:47.886143 rx_lastpass[1][0][3] = 33
4344 09:54:47.889000 rx_firspass[1][0][4] = 4
4345 09:54:47.892835 rx_lastpass[1][0][4] = 38
4346 09:54:47.893247 rx_firspass[1][0][5] = 5
4347 09:54:47.895778 rx_lastpass[1][0][5] = 39
4348 09:54:47.899270 rx_firspass[1][0][6] = 7
4349 09:54:47.902898 rx_lastpass[1][0][6] = 40
4350 09:54:47.903309 rx_firspass[1][0][7] = 5
4351 09:54:47.906505 rx_lastpass[1][0][7] = 38
4352 09:54:47.909832 rx_firspass[1][0][8] = 0
4353 09:54:47.910350 rx_lastpass[1][0][8] = 33
4354 09:54:47.912489 rx_firspass[1][0][9] = 0
4355 09:54:47.916108 rx_lastpass[1][0][9] = 32
4356 09:54:47.919295 rx_firspass[1][0][10] = 4
4357 09:54:47.919837 rx_lastpass[1][0][10] = 35
4358 09:54:47.922304 rx_firspass[1][0][11] = 5
4359 09:54:47.925802 rx_lastpass[1][0][11] = 38
4360 09:54:47.926211 rx_firspass[1][0][12] = 5
4361 09:54:47.929668 rx_lastpass[1][0][12] = 38
4362 09:54:47.932653 rx_firspass[1][0][13] = 5
4363 09:54:47.935816 rx_lastpass[1][0][13] = 37
4364 09:54:47.936223 rx_firspass[1][0][14] = 7
4365 09:54:47.939517 rx_lastpass[1][0][14] = 38
4366 09:54:47.942521 rx_firspass[1][0][15] = -4
4367 09:54:47.945922 rx_lastpass[1][0][15] = 30
4368 09:54:47.946429 rx_firspass[1][1][0] = 3
4369 09:54:47.949156 rx_lastpass[1][1][0] = 40
4370 09:54:47.952552 rx_firspass[1][1][1] = 4
4371 09:54:47.953164 rx_lastpass[1][1][1] = 39
4372 09:54:47.955632 rx_firspass[1][1][2] = 0
4373 09:54:47.959115 rx_lastpass[1][1][2] = 36
4374 09:54:47.959726 rx_firspass[1][1][3] = -2
4375 09:54:47.962573 rx_lastpass[1][1][3] = 34
4376 09:54:47.965891 rx_firspass[1][1][4] = 4
4377 09:54:47.968849 rx_lastpass[1][1][4] = 39
4378 09:54:47.969302 rx_firspass[1][1][5] = 5
4379 09:54:47.972204 rx_lastpass[1][1][5] = 40
4380 09:54:47.975874 rx_firspass[1][1][6] = 5
4381 09:54:47.976280 rx_lastpass[1][1][6] = 41
4382 09:54:47.979160 rx_firspass[1][1][7] = 3
4383 09:54:47.982607 rx_lastpass[1][1][7] = 38
4384 09:54:47.983116 rx_firspass[1][1][8] = 0
4385 09:54:47.985973 rx_lastpass[1][1][8] = 35
4386 09:54:47.988950 rx_firspass[1][1][9] = -1
4387 09:54:47.992372 rx_lastpass[1][1][9] = 34
4388 09:54:47.992881 rx_firspass[1][1][10] = 3
4389 09:54:47.996247 rx_lastpass[1][1][10] = 38
4390 09:54:47.999281 rx_firspass[1][1][11] = 4
4391 09:54:47.999793 rx_lastpass[1][1][11] = 40
4392 09:54:48.002391 rx_firspass[1][1][12] = 4
4393 09:54:48.005913 rx_lastpass[1][1][12] = 40
4394 09:54:48.009496 rx_firspass[1][1][13] = 4
4395 09:54:48.010017 rx_lastpass[1][1][13] = 40
4396 09:54:48.012598 rx_firspass[1][1][14] = 5
4397 09:54:48.016039 rx_lastpass[1][1][14] = 40
4398 09:54:48.019279 rx_firspass[1][1][15] = -4
4399 09:54:48.020027 rx_lastpass[1][1][15] = 31
4400 09:54:48.022653 dump params clk_delay
4401 09:54:48.023189 clk_delay[0] = 1
4402 09:54:48.025821 clk_delay[1] = 0
4403 09:54:48.026329 dump params dqs_delay
4404 09:54:48.029494 dqs_delay[0][0] = -2
4405 09:54:48.032786 dqs_delay[0][1] = 0
4406 09:54:48.033292 dqs_delay[1][0] = 0
4407 09:54:48.035913 dqs_delay[1][1] = 0
4408 09:54:48.039640 dump params delay_cell_unit = 735
4409 09:54:48.040141 dump source = 0x0
4410 09:54:48.042775 dump params frequency:1200
4411 09:54:48.043281 dump params rank number:2
4412 09:54:48.043649
4413 09:54:48.046263 dump params write leveling
4414 09:54:48.049012 write leveling[0][0][0] = 0x0
4415 09:54:48.052785 write leveling[0][0][1] = 0x0
4416 09:54:48.055974 write leveling[0][1][0] = 0x0
4417 09:54:48.056482 write leveling[0][1][1] = 0x0
4418 09:54:48.059085 write leveling[1][0][0] = 0x0
4419 09:54:48.062386 write leveling[1][0][1] = 0x0
4420 09:54:48.065703 write leveling[1][1][0] = 0x0
4421 09:54:48.068933 write leveling[1][1][1] = 0x0
4422 09:54:48.069387 dump params cbt_cs
4423 09:54:48.072042 cbt_cs[0][0] = 0x0
4424 09:54:48.072450 cbt_cs[0][1] = 0x0
4425 09:54:48.075949 cbt_cs[1][0] = 0x0
4426 09:54:48.076459 cbt_cs[1][1] = 0x0
4427 09:54:48.079149 dump params cbt_mr12
4428 09:54:48.079619 cbt_mr12[0][0] = 0x0
4429 09:54:48.082085 cbt_mr12[0][1] = 0x0
4430 09:54:48.085803 cbt_mr12[1][0] = 0x0
4431 09:54:48.086325 cbt_mr12[1][1] = 0x0
4432 09:54:48.088764 dump params tx window
4433 09:54:48.089173 tx_center_min[0][0][0] = 0
4434 09:54:48.092396 tx_center_max[0][0][0] = 0
4435 09:54:48.095965 tx_center_min[0][0][1] = 0
4436 09:54:48.098925 tx_center_max[0][0][1] = 0
4437 09:54:48.099349 tx_center_min[0][1][0] = 0
4438 09:54:48.101982 tx_center_max[0][1][0] = 0
4439 09:54:48.105775 tx_center_min[0][1][1] = 0
4440 09:54:48.109139 tx_center_max[0][1][1] = 0
4441 09:54:48.109688 tx_center_min[1][0][0] = 0
4442 09:54:48.112811 tx_center_max[1][0][0] = 0
4443 09:54:48.116045 tx_center_min[1][0][1] = 0
4444 09:54:48.119399 tx_center_max[1][0][1] = 0
4445 09:54:48.120026 tx_center_min[1][1][0] = 0
4446 09:54:48.122684 tx_center_max[1][1][0] = 0
4447 09:54:48.125925 tx_center_min[1][1][1] = 0
4448 09:54:48.126472 tx_center_max[1][1][1] = 0
4449 09:54:48.129350 dump params tx window
4450 09:54:48.132495 tx_win_center[0][0][0] = 0
4451 09:54:48.135930 tx_first_pass[0][0][0] = 0
4452 09:54:48.136477 tx_last_pass[0][0][0] = 0
4453 09:54:48.139320 tx_win_center[0][0][1] = 0
4454 09:54:48.142542 tx_first_pass[0][0][1] = 0
4455 09:54:48.143093 tx_last_pass[0][0][1] = 0
4456 09:54:48.145552 tx_win_center[0][0][2] = 0
4457 09:54:48.149207 tx_first_pass[0][0][2] = 0
4458 09:54:48.152597 tx_last_pass[0][0][2] = 0
4459 09:54:48.153142 tx_win_center[0][0][3] = 0
4460 09:54:48.156120 tx_first_pass[0][0][3] = 0
4461 09:54:48.159558 tx_last_pass[0][0][3] = 0
4462 09:54:48.160104 tx_win_center[0][0][4] = 0
4463 09:54:48.162698 tx_first_pass[0][0][4] = 0
4464 09:54:48.165728 tx_last_pass[0][0][4] = 0
4465 09:54:48.168949 tx_win_center[0][0][5] = 0
4466 09:54:48.169498 tx_first_pass[0][0][5] = 0
4467 09:54:48.171955 tx_last_pass[0][0][5] = 0
4468 09:54:48.175666 tx_win_center[0][0][6] = 0
4469 09:54:48.178920 tx_first_pass[0][0][6] = 0
4470 09:54:48.179507 tx_last_pass[0][0][6] = 0
4471 09:54:48.182201 tx_win_center[0][0][7] = 0
4472 09:54:48.185849 tx_first_pass[0][0][7] = 0
4473 09:54:48.186411 tx_last_pass[0][0][7] = 0
4474 09:54:48.188845 tx_win_center[0][0][8] = 0
4475 09:54:48.192013 tx_first_pass[0][0][8] = 0
4476 09:54:48.195260 tx_last_pass[0][0][8] = 0
4477 09:54:48.195745 tx_win_center[0][0][9] = 0
4478 09:54:48.198893 tx_first_pass[0][0][9] = 0
4479 09:54:48.201951 tx_last_pass[0][0][9] = 0
4480 09:54:48.205476 tx_win_center[0][0][10] = 0
4481 09:54:48.206033 tx_first_pass[0][0][10] = 0
4482 09:54:48.209026 tx_last_pass[0][0][10] = 0
4483 09:54:48.212040 tx_win_center[0][0][11] = 0
4484 09:54:48.215110 tx_first_pass[0][0][11] = 0
4485 09:54:48.215658 tx_last_pass[0][0][11] = 0
4486 09:54:48.218877 tx_win_center[0][0][12] = 0
4487 09:54:48.222241 tx_first_pass[0][0][12] = 0
4488 09:54:48.225308 tx_last_pass[0][0][12] = 0
4489 09:54:48.225770 tx_win_center[0][0][13] = 0
4490 09:54:48.228551 tx_first_pass[0][0][13] = 0
4491 09:54:48.232067 tx_last_pass[0][0][13] = 0
4492 09:54:48.235268 tx_win_center[0][0][14] = 0
4493 09:54:48.238099 tx_first_pass[0][0][14] = 0
4494 09:54:48.238519 tx_last_pass[0][0][14] = 0
4495 09:54:48.241742 tx_win_center[0][0][15] = 0
4496 09:54:48.245007 tx_first_pass[0][0][15] = 0
4497 09:54:48.245525 tx_last_pass[0][0][15] = 0
4498 09:54:48.248091 tx_win_center[0][1][0] = 0
4499 09:54:48.251790 tx_first_pass[0][1][0] = 0
4500 09:54:48.255000 tx_last_pass[0][1][0] = 0
4501 09:54:48.255565 tx_win_center[0][1][1] = 0
4502 09:54:48.258302 tx_first_pass[0][1][1] = 0
4503 09:54:48.261604 tx_last_pass[0][1][1] = 0
4504 09:54:48.264628 tx_win_center[0][1][2] = 0
4505 09:54:48.265043 tx_first_pass[0][1][2] = 0
4506 09:54:48.268356 tx_last_pass[0][1][2] = 0
4507 09:54:48.271865 tx_win_center[0][1][3] = 0
4508 09:54:48.275015 tx_first_pass[0][1][3] = 0
4509 09:54:48.275586 tx_last_pass[0][1][3] = 0
4510 09:54:48.277872 tx_win_center[0][1][4] = 0
4511 09:54:48.290945 tx_first_pass[0][1][4] = 0
4512 09:54:48.291584 tx_last_pass[0][1][4] = 0
4513 09:54:48.291932 tx_win_center[0][1][5] = 0
4514 09:54:48.292240 tx_first_pass[0][1][5] = 0
4515 09:54:48.292889 tx_last_pass[0][1][5] = 0
4516 09:54:48.293209 tx_win_center[0][1][6] = 0
4517 09:54:48.294501 tx_first_pass[0][1][6] = 0
4518 09:54:48.297734 tx_last_pass[0][1][6] = 0
4519 09:54:48.298148 tx_win_center[0][1][7] = 0
4520 09:54:48.301479 tx_first_pass[0][1][7] = 0
4521 09:54:48.304735 tx_last_pass[0][1][7] = 0
4522 09:54:48.308155 tx_win_center[0][1][8] = 0
4523 09:54:48.308572 tx_first_pass[0][1][8] = 0
4524 09:54:48.311524 tx_last_pass[0][1][8] = 0
4525 09:54:48.315046 tx_win_center[0][1][9] = 0
4526 09:54:48.318145 tx_first_pass[0][1][9] = 0
4527 09:54:48.318654 tx_last_pass[0][1][9] = 0
4528 09:54:48.321337 tx_win_center[0][1][10] = 0
4529 09:54:48.324795 tx_first_pass[0][1][10] = 0
4530 09:54:48.327874 tx_last_pass[0][1][10] = 0
4531 09:54:48.328281 tx_win_center[0][1][11] = 0
4532 09:54:48.331559 tx_first_pass[0][1][11] = 0
4533 09:54:48.334859 tx_last_pass[0][1][11] = 0
4534 09:54:48.338046 tx_win_center[0][1][12] = 0
4535 09:54:48.338461 tx_first_pass[0][1][12] = 0
4536 09:54:48.341454 tx_last_pass[0][1][12] = 0
4537 09:54:48.344869 tx_win_center[0][1][13] = 0
4538 09:54:48.347650 tx_first_pass[0][1][13] = 0
4539 09:54:48.348065 tx_last_pass[0][1][13] = 0
4540 09:54:48.351211 tx_win_center[0][1][14] = 0
4541 09:54:48.354285 tx_first_pass[0][1][14] = 0
4542 09:54:48.357673 tx_last_pass[0][1][14] = 0
4543 09:54:48.358081 tx_win_center[0][1][15] = 0
4544 09:54:48.361212 tx_first_pass[0][1][15] = 0
4545 09:54:48.364648 tx_last_pass[0][1][15] = 0
4546 09:54:48.367892 tx_win_center[1][0][0] = 0
4547 09:54:48.368405 tx_first_pass[1][0][0] = 0
4548 09:54:48.370935 tx_last_pass[1][0][0] = 0
4549 09:54:48.374242 tx_win_center[1][0][1] = 0
4550 09:54:48.378055 tx_first_pass[1][0][1] = 0
4551 09:54:48.378560 tx_last_pass[1][0][1] = 0
4552 09:54:48.381022 tx_win_center[1][0][2] = 0
4553 09:54:48.384677 tx_first_pass[1][0][2] = 0
4554 09:54:48.385185 tx_last_pass[1][0][2] = 0
4555 09:54:48.387576 tx_win_center[1][0][3] = 0
4556 09:54:48.391022 tx_first_pass[1][0][3] = 0
4557 09:54:48.394367 tx_last_pass[1][0][3] = 0
4558 09:54:48.394884 tx_win_center[1][0][4] = 0
4559 09:54:48.397425 tx_first_pass[1][0][4] = 0
4560 09:54:48.400989 tx_last_pass[1][0][4] = 0
4561 09:54:48.401494 tx_win_center[1][0][5] = 0
4562 09:54:48.404520 tx_first_pass[1][0][5] = 0
4563 09:54:48.408162 tx_last_pass[1][0][5] = 0
4564 09:54:48.411202 tx_win_center[1][0][6] = 0
4565 09:54:48.411817 tx_first_pass[1][0][6] = 0
4566 09:54:48.414179 tx_last_pass[1][0][6] = 0
4567 09:54:48.417263 tx_win_center[1][0][7] = 0
4568 09:54:48.420737 tx_first_pass[1][0][7] = 0
4569 09:54:48.421165 tx_last_pass[1][0][7] = 0
4570 09:54:48.423996 tx_win_center[1][0][8] = 0
4571 09:54:48.427679 tx_first_pass[1][0][8] = 0
4572 09:54:48.428177 tx_last_pass[1][0][8] = 0
4573 09:54:48.430744 tx_win_center[1][0][9] = 0
4574 09:54:48.434605 tx_first_pass[1][0][9] = 0
4575 09:54:48.437636 tx_last_pass[1][0][9] = 0
4576 09:54:48.438086 tx_win_center[1][0][10] = 0
4577 09:54:48.440737 tx_first_pass[1][0][10] = 0
4578 09:54:48.443922 tx_last_pass[1][0][10] = 0
4579 09:54:48.447513 tx_win_center[1][0][11] = 0
4580 09:54:48.447922 tx_first_pass[1][0][11] = 0
4581 09:54:48.450907 tx_last_pass[1][0][11] = 0
4582 09:54:48.454516 tx_win_center[1][0][12] = 0
4583 09:54:48.457807 tx_first_pass[1][0][12] = 0
4584 09:54:48.458310 tx_last_pass[1][0][12] = 0
4585 09:54:48.461128 tx_win_center[1][0][13] = 0
4586 09:54:48.464077 tx_first_pass[1][0][13] = 0
4587 09:54:48.467464 tx_last_pass[1][0][13] = 0
4588 09:54:48.467885 tx_win_center[1][0][14] = 0
4589 09:54:48.470771 tx_first_pass[1][0][14] = 0
4590 09:54:48.474131 tx_last_pass[1][0][14] = 0
4591 09:54:48.477323 tx_win_center[1][0][15] = 0
4592 09:54:48.477731 tx_first_pass[1][0][15] = 0
4593 09:54:48.480556 tx_last_pass[1][0][15] = 0
4594 09:54:48.484412 tx_win_center[1][1][0] = 0
4595 09:54:48.487386 tx_first_pass[1][1][0] = 0
4596 09:54:48.487847 tx_last_pass[1][1][0] = 0
4597 09:54:48.490838 tx_win_center[1][1][1] = 0
4598 09:54:48.494167 tx_first_pass[1][1][1] = 0
4599 09:54:48.494677 tx_last_pass[1][1][1] = 0
4600 09:54:48.497766 tx_win_center[1][1][2] = 0
4601 09:54:48.500697 tx_first_pass[1][1][2] = 0
4602 09:54:48.504303 tx_last_pass[1][1][2] = 0
4603 09:54:48.504942 tx_win_center[1][1][3] = 0
4604 09:54:48.507591 tx_first_pass[1][1][3] = 0
4605 09:54:48.511211 tx_last_pass[1][1][3] = 0
4606 09:54:48.514505 tx_win_center[1][1][4] = 0
4607 09:54:48.515023 tx_first_pass[1][1][4] = 0
4608 09:54:48.517774 tx_last_pass[1][1][4] = 0
4609 09:54:48.521067 tx_win_center[1][1][5] = 0
4610 09:54:48.521569 tx_first_pass[1][1][5] = 0
4611 09:54:48.524039 tx_last_pass[1][1][5] = 0
4612 09:54:48.527572 tx_win_center[1][1][6] = 0
4613 09:54:48.530627 tx_first_pass[1][1][6] = 0
4614 09:54:48.531032 tx_last_pass[1][1][6] = 0
4615 09:54:48.534107 tx_win_center[1][1][7] = 0
4616 09:54:48.537210 tx_first_pass[1][1][7] = 0
4617 09:54:48.540506 tx_last_pass[1][1][7] = 0
4618 09:54:48.540914 tx_win_center[1][1][8] = 0
4619 09:54:48.544533 tx_first_pass[1][1][8] = 0
4620 09:54:48.547644 tx_last_pass[1][1][8] = 0
4621 09:54:48.548150 tx_win_center[1][1][9] = 0
4622 09:54:48.550916 tx_first_pass[1][1][9] = 0
4623 09:54:48.554364 tx_last_pass[1][1][9] = 0
4624 09:54:48.557624 tx_win_center[1][1][10] = 0
4625 09:54:48.558128 tx_first_pass[1][1][10] = 0
4626 09:54:48.560736 tx_last_pass[1][1][10] = 0
4627 09:54:48.564110 tx_win_center[1][1][11] = 0
4628 09:54:48.567273 tx_first_pass[1][1][11] = 0
4629 09:54:48.567824 tx_last_pass[1][1][11] = 0
4630 09:54:48.570562 tx_win_center[1][1][12] = 0
4631 09:54:48.573928 tx_first_pass[1][1][12] = 0
4632 09:54:48.577125 tx_last_pass[1][1][12] = 0
4633 09:54:48.577544 tx_win_center[1][1][13] = 0
4634 09:54:48.580976 tx_first_pass[1][1][13] = 0
4635 09:54:48.584255 tx_last_pass[1][1][13] = 0
4636 09:54:48.587131 tx_win_center[1][1][14] = 0
4637 09:54:48.587730 tx_first_pass[1][1][14] = 0
4638 09:54:48.590721 tx_last_pass[1][1][14] = 0
4639 09:54:48.593794 tx_win_center[1][1][15] = 0
4640 09:54:48.597182 tx_first_pass[1][1][15] = 0
4641 09:54:48.597746 tx_last_pass[1][1][15] = 0
4642 09:54:48.600436 dump params rx window
4643 09:54:48.603677 rx_firspass[0][0][0] = 0
4644 09:54:48.604126 rx_lastpass[0][0][0] = 0
4645 09:54:48.607526 rx_firspass[0][0][1] = 0
4646 09:54:48.611341 rx_lastpass[0][0][1] = 0
4647 09:54:48.611937 rx_firspass[0][0][2] = 0
4648 09:54:48.614181 rx_lastpass[0][0][2] = 0
4649 09:54:48.617281 rx_firspass[0][0][3] = 0
4650 09:54:48.617730 rx_lastpass[0][0][3] = 0
4651 09:54:48.621071 rx_firspass[0][0][4] = 0
4652 09:54:48.624120 rx_lastpass[0][0][4] = 0
4653 09:54:48.627925 rx_firspass[0][0][5] = 0
4654 09:54:48.628469 rx_lastpass[0][0][5] = 0
4655 09:54:48.631064 rx_firspass[0][0][6] = 0
4656 09:54:48.634160 rx_lastpass[0][0][6] = 0
4657 09:54:48.634728 rx_firspass[0][0][7] = 0
4658 09:54:48.637305 rx_lastpass[0][0][7] = 0
4659 09:54:48.641021 rx_firspass[0][0][8] = 0
4660 09:54:48.641589 rx_lastpass[0][0][8] = 0
4661 09:54:48.644081 rx_firspass[0][0][9] = 0
4662 09:54:48.647661 rx_lastpass[0][0][9] = 0
4663 09:54:48.648220 rx_firspass[0][0][10] = 0
4664 09:54:48.650555 rx_lastpass[0][0][10] = 0
4665 09:54:48.654152 rx_firspass[0][0][11] = 0
4666 09:54:48.657590 rx_lastpass[0][0][11] = 0
4667 09:54:48.658152 rx_firspass[0][0][12] = 0
4668 09:54:48.660826 rx_lastpass[0][0][12] = 0
4669 09:54:48.663934 rx_firspass[0][0][13] = 0
4670 09:54:48.664452 rx_lastpass[0][0][13] = 0
4671 09:54:48.666909 rx_firspass[0][0][14] = 0
4672 09:54:48.670436 rx_lastpass[0][0][14] = 0
4673 09:54:48.674321 rx_firspass[0][0][15] = 0
4674 09:54:48.674875 rx_lastpass[0][0][15] = 0
4675 09:54:48.677546 rx_firspass[0][1][0] = 0
4676 09:54:48.680653 rx_lastpass[0][1][0] = 0
4677 09:54:48.681110 rx_firspass[0][1][1] = 0
4678 09:54:48.684211 rx_lastpass[0][1][1] = 0
4679 09:54:48.687401 rx_firspass[0][1][2] = 0
4680 09:54:48.687998 rx_lastpass[0][1][2] = 0
4681 09:54:48.690739 rx_firspass[0][1][3] = 0
4682 09:54:48.693858 rx_lastpass[0][1][3] = 0
4683 09:54:48.694414 rx_firspass[0][1][4] = 0
4684 09:54:48.696849 rx_lastpass[0][1][4] = 0
4685 09:54:48.700311 rx_firspass[0][1][5] = 0
4686 09:54:48.703705 rx_lastpass[0][1][5] = 0
4687 09:54:48.704265 rx_firspass[0][1][6] = 0
4688 09:54:48.706843 rx_lastpass[0][1][6] = 0
4689 09:54:48.710294 rx_firspass[0][1][7] = 0
4690 09:54:48.710843 rx_lastpass[0][1][7] = 0
4691 09:54:48.713998 rx_firspass[0][1][8] = 0
4692 09:54:48.717062 rx_lastpass[0][1][8] = 0
4693 09:54:48.717773 rx_firspass[0][1][9] = 0
4694 09:54:48.720239 rx_lastpass[0][1][9] = 0
4695 09:54:48.723639 rx_firspass[0][1][10] = 0
4696 09:54:48.724099 rx_lastpass[0][1][10] = 0
4697 09:54:48.727114 rx_firspass[0][1][11] = 0
4698 09:54:48.730602 rx_lastpass[0][1][11] = 0
4699 09:54:48.733904 rx_firspass[0][1][12] = 0
4700 09:54:48.734422 rx_lastpass[0][1][12] = 0
4701 09:54:48.737043 rx_firspass[0][1][13] = 0
4702 09:54:48.740508 rx_lastpass[0][1][13] = 0
4703 09:54:48.741025 rx_firspass[0][1][14] = 0
4704 09:54:48.743579 rx_lastpass[0][1][14] = 0
4705 09:54:48.746751 rx_firspass[0][1][15] = 0
4706 09:54:48.750147 rx_lastpass[0][1][15] = 0
4707 09:54:48.750564 rx_firspass[1][0][0] = 0
4708 09:54:48.753850 rx_lastpass[1][0][0] = 0
4709 09:54:48.756979 rx_firspass[1][0][1] = 0
4710 09:54:48.757495 rx_lastpass[1][0][1] = 0
4711 09:54:48.760305 rx_firspass[1][0][2] = 0
4712 09:54:48.763709 rx_lastpass[1][0][2] = 0
4713 09:54:48.764227 rx_firspass[1][0][3] = 0
4714 09:54:48.766783 rx_lastpass[1][0][3] = 0
4715 09:54:48.770174 rx_firspass[1][0][4] = 0
4716 09:54:48.770694 rx_lastpass[1][0][4] = 0
4717 09:54:48.773511 rx_firspass[1][0][5] = 0
4718 09:54:48.776667 rx_lastpass[1][0][5] = 0
4719 09:54:48.780066 rx_firspass[1][0][6] = 0
4720 09:54:48.780584 rx_lastpass[1][0][6] = 0
4721 09:54:48.783323 rx_firspass[1][0][7] = 0
4722 09:54:48.786731 rx_lastpass[1][0][7] = 0
4723 09:54:48.787247 rx_firspass[1][0][8] = 0
4724 09:54:48.789847 rx_lastpass[1][0][8] = 0
4725 09:54:48.793167 rx_firspass[1][0][9] = 0
4726 09:54:48.793683 rx_lastpass[1][0][9] = 0
4727 09:54:48.796967 rx_firspass[1][0][10] = 0
4728 09:54:48.800021 rx_lastpass[1][0][10] = 0
4729 09:54:48.803023 rx_firspass[1][0][11] = 0
4730 09:54:48.803589 rx_lastpass[1][0][11] = 0
4731 09:54:48.806170 rx_firspass[1][0][12] = 0
4732 09:54:48.810113 rx_lastpass[1][0][12] = 0
4733 09:54:48.810632 rx_firspass[1][0][13] = 0
4734 09:54:48.813401 rx_lastpass[1][0][13] = 0
4735 09:54:48.816655 rx_firspass[1][0][14] = 0
4736 09:54:48.820226 rx_lastpass[1][0][14] = 0
4737 09:54:48.820744 rx_firspass[1][0][15] = 0
4738 09:54:48.823255 rx_lastpass[1][0][15] = 0
4739 09:54:48.826084 rx_firspass[1][1][0] = 0
4740 09:54:48.826498 rx_lastpass[1][1][0] = 0
4741 09:54:48.829408 rx_firspass[1][1][1] = 0
4742 09:54:48.832989 rx_lastpass[1][1][1] = 0
4743 09:54:48.833502 rx_firspass[1][1][2] = 0
4744 09:54:48.836112 rx_lastpass[1][1][2] = 0
4745 09:54:48.839401 rx_firspass[1][1][3] = 0
4746 09:54:48.842913 rx_lastpass[1][1][3] = 0
4747 09:54:48.843475 rx_firspass[1][1][4] = 0
4748 09:54:48.846435 rx_lastpass[1][1][4] = 0
4749 09:54:48.849626 rx_firspass[1][1][5] = 0
4750 09:54:48.850045 rx_lastpass[1][1][5] = 0
4751 09:54:48.852937 rx_firspass[1][1][6] = 0
4752 09:54:48.856205 rx_lastpass[1][1][6] = 0
4753 09:54:48.856766 rx_firspass[1][1][7] = 0
4754 09:54:48.859997 rx_lastpass[1][1][7] = 0
4755 09:54:48.863067 rx_firspass[1][1][8] = 0
4756 09:54:48.863653 rx_lastpass[1][1][8] = 0
4757 09:54:48.866301 rx_firspass[1][1][9] = 0
4758 09:54:48.869424 rx_lastpass[1][1][9] = 0
4759 09:54:48.869882 rx_firspass[1][1][10] = 0
4760 09:54:48.872982 rx_lastpass[1][1][10] = 0
4761 09:54:48.875856 rx_firspass[1][1][11] = 0
4762 09:54:48.879385 rx_lastpass[1][1][11] = 0
4763 09:54:48.879929 rx_firspass[1][1][12] = 0
4764 09:54:48.882604 rx_lastpass[1][1][12] = 0
4765 09:54:48.885991 rx_firspass[1][1][13] = 0
4766 09:54:48.886500 rx_lastpass[1][1][13] = 0
4767 09:54:48.889364 rx_firspass[1][1][14] = 0
4768 09:54:48.892400 rx_lastpass[1][1][14] = 0
4769 09:54:48.895574 rx_firspass[1][1][15] = 0
4770 09:54:48.896025 rx_lastpass[1][1][15] = 0
4771 09:54:48.899311 dump params clk_delay
4772 09:54:48.899839 clk_delay[0] = 0
4773 09:54:48.902593 clk_delay[1] = 0
4774 09:54:48.903026 dump params dqs_delay
4775 09:54:48.905825 dqs_delay[0][0] = 0
4776 09:54:48.909057 dqs_delay[0][1] = 0
4777 09:54:48.909723 dqs_delay[1][0] = 0
4778 09:54:48.912495 dqs_delay[1][1] = 0
4779 09:54:48.915691 dump params delay_cell_unit = 735
4780 09:54:48.916153 dump source = 0x0
4781 09:54:48.918969 dump params frequency:800
4782 09:54:48.919536 dump params rank number:2
4783 09:54:48.919860
4784 09:54:48.922211 dump params write leveling
4785 09:54:48.925463 write leveling[0][0][0] = 0x0
4786 09:54:48.928862 write leveling[0][0][1] = 0x0
4787 09:54:48.932318 write leveling[0][1][0] = 0x0
4788 09:54:48.932857 write leveling[0][1][1] = 0x0
4789 09:54:48.935651 write leveling[1][0][0] = 0x0
4790 09:54:48.939038 write leveling[1][0][1] = 0x0
4791 09:54:48.942283 write leveling[1][1][0] = 0x0
4792 09:54:48.945851 write leveling[1][1][1] = 0x0
4793 09:54:48.946256 dump params cbt_cs
4794 09:54:48.949054 cbt_cs[0][0] = 0x0
4795 09:54:48.949460 cbt_cs[0][1] = 0x0
4796 09:54:48.952919 cbt_cs[1][0] = 0x0
4797 09:54:48.953425 cbt_cs[1][1] = 0x0
4798 09:54:48.956036 dump params cbt_mr12
4799 09:54:48.956444 cbt_mr12[0][0] = 0x0
4800 09:54:48.959254 cbt_mr12[0][1] = 0x0
4801 09:54:48.959710 cbt_mr12[1][0] = 0x0
4802 09:54:48.962277 cbt_mr12[1][1] = 0x0
4803 09:54:48.965553 dump params tx window
4804 09:54:48.965957 tx_center_min[0][0][0] = 0
4805 09:54:48.968871 tx_center_max[0][0][0] = 0
4806 09:54:48.972751 tx_center_min[0][0][1] = 0
4807 09:54:48.975812 tx_center_max[0][0][1] = 0
4808 09:54:48.976233 tx_center_min[0][1][0] = 0
4809 09:54:48.979252 tx_center_max[0][1][0] = 0
4810 09:54:48.982224 tx_center_min[0][1][1] = 0
4811 09:54:48.985915 tx_center_max[0][1][1] = 0
4812 09:54:48.986436 tx_center_min[1][0][0] = 0
4813 09:54:48.988982 tx_center_max[1][0][0] = 0
4814 09:54:48.992299 tx_center_min[1][0][1] = 0
4815 09:54:48.995786 tx_center_max[1][0][1] = 0
4816 09:54:48.996299 tx_center_min[1][1][0] = 0
4817 09:54:48.998849 tx_center_max[1][1][0] = 0
4818 09:54:49.002435 tx_center_min[1][1][1] = 0
4819 09:54:49.005773 tx_center_max[1][1][1] = 0
4820 09:54:49.006281 dump params tx window
4821 09:54:49.008858 tx_win_center[0][0][0] = 0
4822 09:54:49.012293 tx_first_pass[0][0][0] = 0
4823 09:54:49.012700 tx_last_pass[0][0][0] = 0
4824 09:54:49.015941 tx_win_center[0][0][1] = 0
4825 09:54:49.019267 tx_first_pass[0][0][1] = 0
4826 09:54:49.019817 tx_last_pass[0][0][1] = 0
4827 09:54:49.022760 tx_win_center[0][0][2] = 0
4828 09:54:49.025687 tx_first_pass[0][0][2] = 0
4829 09:54:49.029403 tx_last_pass[0][0][2] = 0
4830 09:54:49.029913 tx_win_center[0][0][3] = 0
4831 09:54:49.032607 tx_first_pass[0][0][3] = 0
4832 09:54:49.035804 tx_last_pass[0][0][3] = 0
4833 09:54:49.038989 tx_win_center[0][0][4] = 0
4834 09:54:49.039397 tx_first_pass[0][0][4] = 0
4835 09:54:49.042649 tx_last_pass[0][0][4] = 0
4836 09:54:49.045989 tx_win_center[0][0][5] = 0
4837 09:54:49.046495 tx_first_pass[0][0][5] = 0
4838 09:54:49.048706 tx_last_pass[0][0][5] = 0
4839 09:54:49.052700 tx_win_center[0][0][6] = 0
4840 09:54:49.055182 tx_first_pass[0][0][6] = 0
4841 09:54:49.055629 tx_last_pass[0][0][6] = 0
4842 09:54:49.059002 tx_win_center[0][0][7] = 0
4843 09:54:49.061926 tx_first_pass[0][0][7] = 0
4844 09:54:49.065458 tx_last_pass[0][0][7] = 0
4845 09:54:49.065969 tx_win_center[0][0][8] = 0
4846 09:54:49.068989 tx_first_pass[0][0][8] = 0
4847 09:54:49.072081 tx_last_pass[0][0][8] = 0
4848 09:54:49.072590 tx_win_center[0][0][9] = 0
4849 09:54:49.075696 tx_first_pass[0][0][9] = 0
4850 09:54:49.078649 tx_last_pass[0][0][9] = 0
4851 09:54:49.082357 tx_win_center[0][0][10] = 0
4852 09:54:49.082862 tx_first_pass[0][0][10] = 0
4853 09:54:49.085675 tx_last_pass[0][0][10] = 0
4854 09:54:49.088804 tx_win_center[0][0][11] = 0
4855 09:54:49.092130 tx_first_pass[0][0][11] = 0
4856 09:54:49.092653 tx_last_pass[0][0][11] = 0
4857 09:54:49.095385 tx_win_center[0][0][12] = 0
4858 09:54:49.098779 tx_first_pass[0][0][12] = 0
4859 09:54:49.101665 tx_last_pass[0][0][12] = 0
4860 09:54:49.102125 tx_win_center[0][0][13] = 0
4861 09:54:49.104964 tx_first_pass[0][0][13] = 0
4862 09:54:49.108623 tx_last_pass[0][0][13] = 0
4863 09:54:49.111662 tx_win_center[0][0][14] = 0
4864 09:54:49.112123 tx_first_pass[0][0][14] = 0
4865 09:54:49.115526 tx_last_pass[0][0][14] = 0
4866 09:54:49.118670 tx_win_center[0][0][15] = 0
4867 09:54:49.122380 tx_first_pass[0][0][15] = 0
4868 09:54:49.122927 tx_last_pass[0][0][15] = 0
4869 09:54:49.125314 tx_win_center[0][1][0] = 0
4870 09:54:49.128949 tx_first_pass[0][1][0] = 0
4871 09:54:49.131721 tx_last_pass[0][1][0] = 0
4872 09:54:49.132135 tx_win_center[0][1][1] = 0
4873 09:54:49.135481 tx_first_pass[0][1][1] = 0
4874 09:54:49.138302 tx_last_pass[0][1][1] = 0
4875 09:54:49.142077 tx_win_center[0][1][2] = 0
4876 09:54:49.142586 tx_first_pass[0][1][2] = 0
4877 09:54:49.145266 tx_last_pass[0][1][2] = 0
4878 09:54:49.148550 tx_win_center[0][1][3] = 0
4879 09:54:49.149059 tx_first_pass[0][1][3] = 0
4880 09:54:49.152020 tx_last_pass[0][1][3] = 0
4881 09:54:49.155295 tx_win_center[0][1][4] = 0
4882 09:54:49.158661 tx_first_pass[0][1][4] = 0
4883 09:54:49.159166 tx_last_pass[0][1][4] = 0
4884 09:54:49.162076 tx_win_center[0][1][5] = 0
4885 09:54:49.165127 tx_first_pass[0][1][5] = 0
4886 09:54:49.168612 tx_last_pass[0][1][5] = 0
4887 09:54:49.169121 tx_win_center[0][1][6] = 0
4888 09:54:49.171854 tx_first_pass[0][1][6] = 0
4889 09:54:49.175113 tx_last_pass[0][1][6] = 0
4890 09:54:49.175658 tx_win_center[0][1][7] = 0
4891 09:54:49.178277 tx_first_pass[0][1][7] = 0
4892 09:54:49.182051 tx_last_pass[0][1][7] = 0
4893 09:54:49.184866 tx_win_center[0][1][8] = 0
4894 09:54:49.185286 tx_first_pass[0][1][8] = 0
4895 09:54:49.188167 tx_last_pass[0][1][8] = 0
4896 09:54:49.191884 tx_win_center[0][1][9] = 0
4897 09:54:49.195181 tx_first_pass[0][1][9] = 0
4898 09:54:49.195757 tx_last_pass[0][1][9] = 0
4899 09:54:49.198503 tx_win_center[0][1][10] = 0
4900 09:54:49.201306 tx_first_pass[0][1][10] = 0
4901 09:54:49.204776 tx_last_pass[0][1][10] = 0
4902 09:54:49.205262 tx_win_center[0][1][11] = 0
4903 09:54:49.208075 tx_first_pass[0][1][11] = 0
4904 09:54:49.211349 tx_last_pass[0][1][11] = 0
4905 09:54:49.214643 tx_win_center[0][1][12] = 0
4906 09:54:49.215058 tx_first_pass[0][1][12] = 0
4907 09:54:49.218254 tx_last_pass[0][1][12] = 0
4908 09:54:49.221643 tx_win_center[0][1][13] = 0
4909 09:54:49.224759 tx_first_pass[0][1][13] = 0
4910 09:54:49.225267 tx_last_pass[0][1][13] = 0
4911 09:54:49.227988 tx_win_center[0][1][14] = 0
4912 09:54:49.231072 tx_first_pass[0][1][14] = 0
4913 09:54:49.234693 tx_last_pass[0][1][14] = 0
4914 09:54:49.235203 tx_win_center[0][1][15] = 0
4915 09:54:49.237540 tx_first_pass[0][1][15] = 0
4916 09:54:49.241473 tx_last_pass[0][1][15] = 0
4917 09:54:49.244705 tx_win_center[1][0][0] = 0
4918 09:54:49.245212 tx_first_pass[1][0][0] = 0
4919 09:54:49.247773 tx_last_pass[1][0][0] = 0
4920 09:54:49.251229 tx_win_center[1][0][1] = 0
4921 09:54:49.251794 tx_first_pass[1][0][1] = 0
4922 09:54:49.254645 tx_last_pass[1][0][1] = 0
4923 09:54:49.257931 tx_win_center[1][0][2] = 0
4924 09:54:49.261225 tx_first_pass[1][0][2] = 0
4925 09:54:49.261730 tx_last_pass[1][0][2] = 0
4926 09:54:49.264747 tx_win_center[1][0][3] = 0
4927 09:54:49.267953 tx_first_pass[1][0][3] = 0
4928 09:54:49.271159 tx_last_pass[1][0][3] = 0
4929 09:54:49.271650 tx_win_center[1][0][4] = 0
4930 09:54:49.274814 tx_first_pass[1][0][4] = 0
4931 09:54:49.278021 tx_last_pass[1][0][4] = 0
4932 09:54:49.278535 tx_win_center[1][0][5] = 0
4933 09:54:49.281197 tx_first_pass[1][0][5] = 0
4934 09:54:49.284421 tx_last_pass[1][0][5] = 0
4935 09:54:49.287832 tx_win_center[1][0][6] = 0
4936 09:54:49.288285 tx_first_pass[1][0][6] = 0
4937 09:54:49.290953 tx_last_pass[1][0][6] = 0
4938 09:54:49.294002 tx_win_center[1][0][7] = 0
4939 09:54:49.297272 tx_first_pass[1][0][7] = 0
4940 09:54:49.297717 tx_last_pass[1][0][7] = 0
4941 09:54:49.300792 tx_win_center[1][0][8] = 0
4942 09:54:49.304417 tx_first_pass[1][0][8] = 0
4943 09:54:49.304836 tx_last_pass[1][0][8] = 0
4944 09:54:49.307624 tx_win_center[1][0][9] = 0
4945 09:54:49.310839 tx_first_pass[1][0][9] = 0
4946 09:54:49.314344 tx_last_pass[1][0][9] = 0
4947 09:54:49.314795 tx_win_center[1][0][10] = 0
4948 09:54:49.317727 tx_first_pass[1][0][10] = 0
4949 09:54:49.321060 tx_last_pass[1][0][10] = 0
4950 09:54:49.324321 tx_win_center[1][0][11] = 0
4951 09:54:49.324740 tx_first_pass[1][0][11] = 0
4952 09:54:49.327686 tx_last_pass[1][0][11] = 0
4953 09:54:49.330534 tx_win_center[1][0][12] = 0
4954 09:54:49.333836 tx_first_pass[1][0][12] = 0
4955 09:54:49.334251 tx_last_pass[1][0][12] = 0
4956 09:54:49.337261 tx_win_center[1][0][13] = 0
4957 09:54:49.340928 tx_first_pass[1][0][13] = 0
4958 09:54:49.344129 tx_last_pass[1][0][13] = 0
4959 09:54:49.344543 tx_win_center[1][0][14] = 0
4960 09:54:49.347443 tx_first_pass[1][0][14] = 0
4961 09:54:49.350803 tx_last_pass[1][0][14] = 0
4962 09:54:49.354096 tx_win_center[1][0][15] = 0
4963 09:54:49.354513 tx_first_pass[1][0][15] = 0
4964 09:54:49.357627 tx_last_pass[1][0][15] = 0
4965 09:54:49.360656 tx_win_center[1][1][0] = 0
4966 09:54:49.363857 tx_first_pass[1][1][0] = 0
4967 09:54:49.364274 tx_last_pass[1][1][0] = 0
4968 09:54:49.367347 tx_win_center[1][1][1] = 0
4969 09:54:49.370583 tx_first_pass[1][1][1] = 0
4970 09:54:49.374758 tx_last_pass[1][1][1] = 0
4971 09:54:49.375177 tx_win_center[1][1][2] = 0
4972 09:54:49.377221 tx_first_pass[1][1][2] = 0
4973 09:54:49.380658 tx_last_pass[1][1][2] = 0
4974 09:54:49.381077 tx_win_center[1][1][3] = 0
4975 09:54:49.384225 tx_first_pass[1][1][3] = 0
4976 09:54:49.387556 tx_last_pass[1][1][3] = 0
4977 09:54:49.390857 tx_win_center[1][1][4] = 0
4978 09:54:49.391275 tx_first_pass[1][1][4] = 0
4979 09:54:49.393955 tx_last_pass[1][1][4] = 0
4980 09:54:49.397140 tx_win_center[1][1][5] = 0
4981 09:54:49.400856 tx_first_pass[1][1][5] = 0
4982 09:54:49.401337 tx_last_pass[1][1][5] = 0
4983 09:54:49.403913 tx_win_center[1][1][6] = 0
4984 09:54:49.407257 tx_first_pass[1][1][6] = 0
4985 09:54:49.407752 tx_last_pass[1][1][6] = 0
4986 09:54:49.410565 tx_win_center[1][1][7] = 0
4987 09:54:49.413788 tx_first_pass[1][1][7] = 0
4988 09:54:49.416966 tx_last_pass[1][1][7] = 0
4989 09:54:49.417385 tx_win_center[1][1][8] = 0
4990 09:54:49.420554 tx_first_pass[1][1][8] = 0
4991 09:54:49.423990 tx_last_pass[1][1][8] = 0
4992 09:54:49.426724 tx_win_center[1][1][9] = 0
4993 09:54:49.427162 tx_first_pass[1][1][9] = 0
4994 09:54:49.430602 tx_last_pass[1][1][9] = 0
4995 09:54:49.433763 tx_win_center[1][1][10] = 0
4996 09:54:49.437040 tx_first_pass[1][1][10] = 0
4997 09:54:49.437632 tx_last_pass[1][1][10] = 0
4998 09:54:49.440033 tx_win_center[1][1][11] = 0
4999 09:54:49.443826 tx_first_pass[1][1][11] = 0
5000 09:54:49.444244 tx_last_pass[1][1][11] = 0
5001 09:54:49.446905 tx_win_center[1][1][12] = 0
5002 09:54:49.449908 tx_first_pass[1][1][12] = 0
5003 09:54:49.453313 tx_last_pass[1][1][12] = 0
5004 09:54:49.456734 tx_win_center[1][1][13] = 0
5005 09:54:49.457152 tx_first_pass[1][1][13] = 0
5006 09:54:49.460103 tx_last_pass[1][1][13] = 0
5007 09:54:49.463107 tx_win_center[1][1][14] = 0
5008 09:54:49.467076 tx_first_pass[1][1][14] = 0
5009 09:54:49.467530 tx_last_pass[1][1][14] = 0
5010 09:54:49.470234 tx_win_center[1][1][15] = 0
5011 09:54:49.473518 tx_first_pass[1][1][15] = 0
5012 09:54:49.476718 tx_last_pass[1][1][15] = 0
5013 09:54:49.477168 dump params rx window
5014 09:54:49.480135 rx_firspass[0][0][0] = 0
5015 09:54:49.483235 rx_lastpass[0][0][0] = 0
5016 09:54:49.483687 rx_firspass[0][0][1] = 0
5017 09:54:49.486389 rx_lastpass[0][0][1] = 0
5018 09:54:49.490260 rx_firspass[0][0][2] = 0
5019 09:54:49.490687 rx_lastpass[0][0][2] = 0
5020 09:54:49.493372 rx_firspass[0][0][3] = 0
5021 09:54:49.496560 rx_lastpass[0][0][3] = 0
5022 09:54:49.496974 rx_firspass[0][0][4] = 0
5023 09:54:49.500285 rx_lastpass[0][0][4] = 0
5024 09:54:49.503025 rx_firspass[0][0][5] = 0
5025 09:54:49.503479 rx_lastpass[0][0][5] = 0
5026 09:54:49.506620 rx_firspass[0][0][6] = 0
5027 09:54:49.509624 rx_lastpass[0][0][6] = 0
5028 09:54:49.510040 rx_firspass[0][0][7] = 0
5029 09:54:49.513643 rx_lastpass[0][0][7] = 0
5030 09:54:49.516456 rx_firspass[0][0][8] = 0
5031 09:54:49.520082 rx_lastpass[0][0][8] = 0
5032 09:54:49.520456 rx_firspass[0][0][9] = 0
5033 09:54:49.523393 rx_lastpass[0][0][9] = 0
5034 09:54:49.526510 rx_firspass[0][0][10] = 0
5035 09:54:49.526946 rx_lastpass[0][0][10] = 0
5036 09:54:49.529762 rx_firspass[0][0][11] = 0
5037 09:54:49.533086 rx_lastpass[0][0][11] = 0
5038 09:54:49.533502 rx_firspass[0][0][12] = 0
5039 09:54:49.536403 rx_lastpass[0][0][12] = 0
5040 09:54:49.539849 rx_firspass[0][0][13] = 0
5041 09:54:49.543611 rx_lastpass[0][0][13] = 0
5042 09:54:49.544118 rx_firspass[0][0][14] = 0
5043 09:54:49.546872 rx_lastpass[0][0][14] = 0
5044 09:54:49.550035 rx_firspass[0][0][15] = 0
5045 09:54:49.550554 rx_lastpass[0][0][15] = 0
5046 09:54:49.553143 rx_firspass[0][1][0] = 0
5047 09:54:49.556797 rx_lastpass[0][1][0] = 0
5048 09:54:49.559961 rx_firspass[0][1][1] = 0
5049 09:54:49.560368 rx_lastpass[0][1][1] = 0
5050 09:54:49.563201 rx_firspass[0][1][2] = 0
5051 09:54:49.566276 rx_lastpass[0][1][2] = 0
5052 09:54:49.566735 rx_firspass[0][1][3] = 0
5053 09:54:49.570072 rx_lastpass[0][1][3] = 0
5054 09:54:49.573277 rx_firspass[0][1][4] = 0
5055 09:54:49.573691 rx_lastpass[0][1][4] = 0
5056 09:54:49.576749 rx_firspass[0][1][5] = 0
5057 09:54:49.579802 rx_lastpass[0][1][5] = 0
5058 09:54:49.580222 rx_firspass[0][1][6] = 0
5059 09:54:49.583512 rx_lastpass[0][1][6] = 0
5060 09:54:49.586743 rx_firspass[0][1][7] = 0
5061 09:54:49.587261 rx_lastpass[0][1][7] = 0
5062 09:54:49.590113 rx_firspass[0][1][8] = 0
5063 09:54:49.593061 rx_lastpass[0][1][8] = 0
5064 09:54:49.596308 rx_firspass[0][1][9] = 0
5065 09:54:49.596726 rx_lastpass[0][1][9] = 0
5066 09:54:49.599353 rx_firspass[0][1][10] = 0
5067 09:54:49.602771 rx_lastpass[0][1][10] = 0
5068 09:54:49.603183 rx_firspass[0][1][11] = 0
5069 09:54:49.606532 rx_lastpass[0][1][11] = 0
5070 09:54:49.610152 rx_firspass[0][1][12] = 0
5071 09:54:49.610779 rx_lastpass[0][1][12] = 0
5072 09:54:49.612981 rx_firspass[0][1][13] = 0
5073 09:54:49.616174 rx_lastpass[0][1][13] = 0
5074 09:54:49.619315 rx_firspass[0][1][14] = 0
5075 09:54:49.619761 rx_lastpass[0][1][14] = 0
5076 09:54:49.622957 rx_firspass[0][1][15] = 0
5077 09:54:49.626376 rx_lastpass[0][1][15] = 0
5078 09:54:49.627139 rx_firspass[1][0][0] = 0
5079 09:54:49.629185 rx_lastpass[1][0][0] = 0
5080 09:54:49.632464 rx_firspass[1][0][1] = 0
5081 09:54:49.635932 rx_lastpass[1][0][1] = 0
5082 09:54:49.636348 rx_firspass[1][0][2] = 0
5083 09:54:49.639484 rx_lastpass[1][0][2] = 0
5084 09:54:49.642454 rx_firspass[1][0][3] = 0
5085 09:54:49.642953 rx_lastpass[1][0][3] = 0
5086 09:54:49.646166 rx_firspass[1][0][4] = 0
5087 09:54:49.649282 rx_lastpass[1][0][4] = 0
5088 09:54:49.649786 rx_firspass[1][0][5] = 0
5089 09:54:49.652845 rx_lastpass[1][0][5] = 0
5090 09:54:49.656045 rx_firspass[1][0][6] = 0
5091 09:54:49.656497 rx_lastpass[1][0][6] = 0
5092 09:54:49.659174 rx_firspass[1][0][7] = 0
5093 09:54:49.662885 rx_lastpass[1][0][7] = 0
5094 09:54:49.663492 rx_firspass[1][0][8] = 0
5095 09:54:49.665794 rx_lastpass[1][0][8] = 0
5096 09:54:49.669026 rx_firspass[1][0][9] = 0
5097 09:54:49.672708 rx_lastpass[1][0][9] = 0
5098 09:54:49.673112 rx_firspass[1][0][10] = 0
5099 09:54:49.675982 rx_lastpass[1][0][10] = 0
5100 09:54:49.679056 rx_firspass[1][0][11] = 0
5101 09:54:49.679542 rx_lastpass[1][0][11] = 0
5102 09:54:49.682841 rx_firspass[1][0][12] = 0
5103 09:54:49.686047 rx_lastpass[1][0][12] = 0
5104 09:54:49.689293 rx_firspass[1][0][13] = 0
5105 09:54:49.689695 rx_lastpass[1][0][13] = 0
5106 09:54:49.692614 rx_firspass[1][0][14] = 0
5107 09:54:49.695960 rx_lastpass[1][0][14] = 0
5108 09:54:49.696366 rx_firspass[1][0][15] = 0
5109 09:54:49.699266 rx_lastpass[1][0][15] = 0
5110 09:54:49.702425 rx_firspass[1][1][0] = 0
5111 09:54:49.702827 rx_lastpass[1][1][0] = 0
5112 09:54:49.705946 rx_firspass[1][1][1] = 0
5113 09:54:49.709234 rx_lastpass[1][1][1] = 0
5114 09:54:49.712542 rx_firspass[1][1][2] = 0
5115 09:54:49.712952 rx_lastpass[1][1][2] = 0
5116 09:54:49.715597 rx_firspass[1][1][3] = 0
5117 09:54:49.718823 rx_lastpass[1][1][3] = 0
5118 09:54:49.719258 rx_firspass[1][1][4] = 0
5119 09:54:49.722449 rx_lastpass[1][1][4] = 0
5120 09:54:49.725749 rx_firspass[1][1][5] = 0
5121 09:54:49.726255 rx_lastpass[1][1][5] = 0
5122 09:54:49.729344 rx_firspass[1][1][6] = 0
5123 09:54:49.733020 rx_lastpass[1][1][6] = 0
5124 09:54:49.733529 rx_firspass[1][1][7] = 0
5125 09:54:49.735975 rx_lastpass[1][1][7] = 0
5126 09:54:49.739057 rx_firspass[1][1][8] = 0
5127 09:54:49.739503 rx_lastpass[1][1][8] = 0
5128 09:54:49.742203 rx_firspass[1][1][9] = 0
5129 09:54:49.745486 rx_lastpass[1][1][9] = 0
5130 09:54:49.749222 rx_firspass[1][1][10] = 0
5131 09:54:49.749629 rx_lastpass[1][1][10] = 0
5132 09:54:49.752194 rx_firspass[1][1][11] = 0
5133 09:54:49.755727 rx_lastpass[1][1][11] = 0
5134 09:54:49.756178 rx_firspass[1][1][12] = 0
5135 09:54:49.759088 rx_lastpass[1][1][12] = 0
5136 09:54:49.762438 rx_firspass[1][1][13] = 0
5137 09:54:49.765536 rx_lastpass[1][1][13] = 0
5138 09:54:49.765942 rx_firspass[1][1][14] = 0
5139 09:54:49.768769 rx_lastpass[1][1][14] = 0
5140 09:54:49.772224 rx_firspass[1][1][15] = 0
5141 09:54:49.772648 rx_lastpass[1][1][15] = 0
5142 09:54:49.775572 dump params clk_delay
5143 09:54:49.776085 clk_delay[0] = 0
5144 09:54:49.779165 clk_delay[1] = 0
5145 09:54:49.782620 dump params dqs_delay
5146 09:54:49.783123 dqs_delay[0][0] = 0
5147 09:54:49.785579 dqs_delay[0][1] = 0
5148 09:54:49.785993 dqs_delay[1][0] = 0
5149 09:54:49.789199 dqs_delay[1][1] = 0
5150 09:54:49.792357 dump params delay_cell_unit = 735
5151 09:54:49.792775 mt_set_emi_preloader end
5152 09:54:49.799111 [mt_mem_init] dram size: 0x100000000, rank number: 2
5153 09:54:49.802295 [complex_mem_test] start addr:0x40000000, len:20480
5154 09:54:49.839019 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5155 09:54:49.845962 [complex_mem_test] start addr:0x80000000, len:20480
5156 09:54:49.881340 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5157 09:54:49.887801 [complex_mem_test] start addr:0xc0000000, len:20480
5158 09:54:49.923924 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5159 09:54:49.930222 [complex_mem_test] start addr:0x56000000, len:8192
5160 09:54:49.946934 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5161 09:54:49.950226 ddr_geometry:1
5162 09:54:49.953399 [complex_mem_test] start addr:0x80000000, len:8192
5163 09:54:49.970437 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5164 09:54:49.973978 dram_init: dram init end (result: 0)
5165 09:54:49.980691 Successfully loaded DRAM blobs and ran DRAM calibration
5166 09:54:49.990544 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5167 09:54:49.991214 CBMEM:
5168 09:54:49.994208 IMD: root @ 00000000fffff000 254 entries.
5169 09:54:49.997324 IMD: root @ 00000000ffffec00 62 entries.
5170 09:54:50.004255 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5171 09:54:50.010777 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5172 09:54:50.014356 in-header: 03 a1 00 00 08 00 00 00
5173 09:54:50.017590 in-data: 84 60 60 10 00 00 00 00
5174 09:54:50.020767 Chrome EC: clear events_b mask to 0x0000000020004000
5175 09:54:50.028436 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5176 09:54:50.031535 in-header: 03 fd 00 00 00 00 00 00
5177 09:54:50.031958 in-data:
5178 09:54:50.038200 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5179 09:54:50.038819 CBFS @ 21000 size 3d4000
5180 09:54:50.045081 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5181 09:54:50.047938 CBFS: Locating 'fallback/ramstage'
5182 09:54:50.051390 CBFS: Found @ offset 10d40 size d563
5183 09:54:50.072879 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5184 09:54:50.084656 Accumulated console time in romstage 13614 ms
5185 09:54:50.085389
5186 09:54:50.085917
5187 09:54:50.095090 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5188 09:54:50.098249 ARM64: Exception handlers installed.
5189 09:54:50.098662 ARM64: Testing exception
5190 09:54:50.101250 ARM64: Done test exception
5191 09:54:50.104527 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5192 09:54:50.107799 Manufacturer: ef
5193 09:54:50.110969 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5194 09:54:50.117599 WARNING: RO_VPD is uninitialized or empty.
5195 09:54:50.121137 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5196 09:54:50.124547 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5197 09:54:50.134722 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5198 09:54:50.137935 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5199 09:54:50.144617 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5200 09:54:50.145124 Enumerating buses...
5201 09:54:50.151043 Show all devs... Before device enumeration.
5202 09:54:50.151602 Root Device: enabled 1
5203 09:54:50.154660 CPU_CLUSTER: 0: enabled 1
5204 09:54:50.155075 CPU: 00: enabled 1
5205 09:54:50.158108 Compare with tree...
5206 09:54:50.161390 Root Device: enabled 1
5207 09:54:50.161899 CPU_CLUSTER: 0: enabled 1
5208 09:54:50.164681 CPU: 00: enabled 1
5209 09:54:50.167923 Root Device scanning...
5210 09:54:50.168672 root_dev_scan_bus for Root Device
5211 09:54:50.170975 CPU_CLUSTER: 0 enabled
5212 09:54:50.174466 root_dev_scan_bus for Root Device done
5213 09:54:50.180963 scan_bus: scanning of bus Root Device took 10690 usecs
5214 09:54:50.181463 done
5215 09:54:50.184127 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5216 09:54:50.187508 Allocating resources...
5217 09:54:50.187954 Reading resources...
5218 09:54:50.190746 Root Device read_resources bus 0 link: 0
5219 09:54:50.197508 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5220 09:54:50.198017 CPU: 00 missing read_resources
5221 09:54:50.204184 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5222 09:54:50.207459 Root Device read_resources bus 0 link: 0 done
5223 09:54:50.211170 Done reading resources.
5224 09:54:50.214131 Show resources in subtree (Root Device)...After reading.
5225 09:54:50.217387 Root Device child on link 0 CPU_CLUSTER: 0
5226 09:54:50.220983 CPU_CLUSTER: 0 child on link 0 CPU: 00
5227 09:54:50.230768 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5228 09:54:50.231368 CPU: 00
5229 09:54:50.233905 Setting resources...
5230 09:54:50.237416 Root Device assign_resources, bus 0 link: 0
5231 09:54:50.240748 CPU_CLUSTER: 0 missing set_resources
5232 09:54:50.243866 Root Device assign_resources, bus 0 link: 0
5233 09:54:50.246912 Done setting resources.
5234 09:54:50.253644 Show resources in subtree (Root Device)...After assigning values.
5235 09:54:50.257384 Root Device child on link 0 CPU_CLUSTER: 0
5236 09:54:50.260583 CPU_CLUSTER: 0 child on link 0 CPU: 00
5237 09:54:50.270815 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5238 09:54:50.271321 CPU: 00
5239 09:54:50.273854 Done allocating resources.
5240 09:54:50.277590 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5241 09:54:50.280078 Enabling resources...
5242 09:54:50.280492 done.
5243 09:54:50.284044 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5244 09:54:50.287463 Initializing devices...
5245 09:54:50.287995 Root Device init ...
5246 09:54:50.290807 mainboard_init: Starting display init.
5247 09:54:50.293754 ADC[4]: Raw value=76102 ID=0
5248 09:54:50.317387 anx7625_power_on_init: Init interface.
5249 09:54:50.320386 anx7625_disable_pd_protocol: Disabled PD feature.
5250 09:54:50.327034 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5251 09:54:50.374284 anx7625_start_dp_work: Secure OCM version=00
5252 09:54:50.377250 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5253 09:54:50.394487 sp_tx_get_edid_block: EDID Block = 1
5254 09:54:50.511835 Extracted contents:
5255 09:54:50.514908 header: 00 ff ff ff ff ff ff 00
5256 09:54:50.518535 serial number: 06 af 5c 14 00 00 00 00 00 1a
5257 09:54:50.521851 version: 01 04
5258 09:54:50.525068 basic params: 95 1a 0e 78 02
5259 09:54:50.528212 chroma info: 99 85 95 55 56 92 28 22 50 54
5260 09:54:50.531617 established: 00 00 00
5261 09:54:50.538507 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5262 09:54:50.541516 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5263 09:54:50.548702 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5264 09:54:50.555269 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5265 09:54:50.561908 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5266 09:54:50.564772 extensions: 00
5267 09:54:50.565238 checksum: ae
5268 09:54:50.565709
5269 09:54:50.568145 Manufacturer: AUO Model 145c Serial Number 0
5270 09:54:50.571229 Made week 0 of 2016
5271 09:54:50.571861 EDID version: 1.4
5272 09:54:50.574623 Digital display
5273 09:54:50.578083 6 bits per primary color channel
5274 09:54:50.578655 DisplayPort interface
5275 09:54:50.581931 Maximum image size: 26 cm x 14 cm
5276 09:54:50.585050 Gamma: 220%
5277 09:54:50.585519 Check DPMS levels
5278 09:54:50.588072 Supported color formats: RGB 4:4:4
5279 09:54:50.591644 First detailed timing is preferred timing
5280 09:54:50.594900 Established timings supported:
5281 09:54:50.598227 Standard timings supported:
5282 09:54:50.598785 Detailed timings
5283 09:54:50.605019 Hex of detail: ce1d56ea50001a3030204600009010000018
5284 09:54:50.608208 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5285 09:54:50.611161 0556 0586 05a6 0640 hborder 0
5286 09:54:50.614451 0300 0304 030a 031a vborder 0
5287 09:54:50.617834 -hsync -vsync
5288 09:54:50.621637 Did detailed timing
5289 09:54:50.624676 Hex of detail: 0000000f0000000000000000000000000020
5290 09:54:50.628401 Manufacturer-specified data, tag 15
5291 09:54:50.634306 Hex of detail: 000000fe0041554f0a202020202020202020
5292 09:54:50.634843 ASCII string: AUO
5293 09:54:50.637600 Hex of detail: 000000fe004231313658414230312e34200a
5294 09:54:50.640784 ASCII string: B116XAB01.4
5295 09:54:50.641239 Checksum
5296 09:54:50.644107 Checksum: 0xae (valid)
5297 09:54:50.650696 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5298 09:54:50.651109 DSI data_rate: 457800000 bps
5299 09:54:50.658332 anx7625_parse_edid: set default k value to 0x3d for panel
5300 09:54:50.661942 anx7625_parse_edid: pixelclock(76300).
5301 09:54:50.665054 hactive(1366), hsync(32), hfp(48), hbp(154)
5302 09:54:50.668112 vactive(768), vsync(6), vfp(4), vbp(16)
5303 09:54:50.671500 anx7625_dsi_config: config dsi.
5304 09:54:50.679981 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5305 09:54:50.701062 anx7625_dsi_config: success to config DSI
5306 09:54:50.703887 anx7625_dp_start: MIPI phy setup OK.
5307 09:54:50.707279 [SSUSB] Setting up USB HOST controller...
5308 09:54:50.710666 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5309 09:54:50.714080 [SSUSB] phy power-on done.
5310 09:54:50.717835 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5311 09:54:50.721678 in-header: 03 fc 01 00 00 00 00 00
5312 09:54:50.722220 in-data:
5313 09:54:50.727692 handle_proto3_response: EC response with error code: 1
5314 09:54:50.728106 SPM: pcm index = 1
5315 09:54:50.731222 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5316 09:54:50.734333 CBFS @ 21000 size 3d4000
5317 09:54:50.740976 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5318 09:54:50.744117 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5319 09:54:50.747582 CBFS: Found @ offset 1e7c0 size 1026
5320 09:54:50.754124 read SPI 0x3f808 0x1026: 1271 us, 3252 KB/s, 26.016 Mbps
5321 09:54:50.757812 SPM: binary array size = 2988
5322 09:54:50.761182 SPM: version = pcm_allinone_v1.17.2_20180829
5323 09:54:50.764224 SPM binary loaded in 32 msecs
5324 09:54:50.772069 spm_kick_im_to_fetch: ptr = 000000004021eec2
5325 09:54:50.775743 spm_kick_im_to_fetch: len = 2988
5326 09:54:50.776157 SPM: spm_kick_pcm_to_run
5327 09:54:50.778893 SPM: spm_kick_pcm_to_run done
5328 09:54:50.782688 SPM: spm_init done in 52 msecs
5329 09:54:50.785208 Root Device init finished in 494985 usecs
5330 09:54:50.789188 CPU_CLUSTER: 0 init ...
5331 09:54:50.795470 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5332 09:54:50.802320 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5333 09:54:50.802867 CBFS @ 21000 size 3d4000
5334 09:54:50.808696 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5335 09:54:50.812445 CBFS: Locating 'sspm.bin'
5336 09:54:50.815563 CBFS: Found @ offset 208c0 size 41cb
5337 09:54:50.825461 read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps
5338 09:54:50.832890 CPU_CLUSTER: 0 init finished in 42802 usecs
5339 09:54:50.833416 Devices initialized
5340 09:54:50.836165 Show all devs... After init.
5341 09:54:50.839709 Root Device: enabled 1
5342 09:54:50.840253 CPU_CLUSTER: 0: enabled 1
5343 09:54:50.842807 CPU: 00: enabled 1
5344 09:54:50.846498 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5345 09:54:50.849642 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5346 09:54:50.852635 ELOG: NV offset 0x558000 size 0x1000
5347 09:54:50.860543 read SPI 0x558000 0x1000: 1259 us, 3253 KB/s, 26.024 Mbps
5348 09:54:50.867094 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5349 09:54:50.870749 ELOG: Event(17) added with size 13 at 2024-06-18 09:53:52 UTC
5350 09:54:50.877208 out: cmd=0x121: 03 db 21 01 00 00 00 00
5351 09:54:50.880264 in-header: 03 c0 00 00 2c 00 00 00
5352 09:54:50.890890 in-data: 64 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 e0 0b 12 00 06 80 00 00 e8 86 13 00 06 80 00 00 35 04 01 00 06 80 00 00 7e 00 02 00
5353 09:54:50.893615 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5354 09:54:50.897201 in-header: 03 19 00 00 08 00 00 00
5355 09:54:50.900492 in-data: a2 e0 47 00 13 00 00 00
5356 09:54:50.903749 Chrome EC: UHEPI supported
5357 09:54:50.910138 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5358 09:54:50.913790 in-header: 03 e1 00 00 08 00 00 00
5359 09:54:50.916805 in-data: 84 20 60 10 00 00 00 00
5360 09:54:50.920251 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5361 09:54:50.926871 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5362 09:54:50.930313 in-header: 03 e1 00 00 08 00 00 00
5363 09:54:50.933228 in-data: 84 20 60 10 00 00 00 00
5364 09:54:50.940211 ELOG: Event(A1) added with size 10 at 2024-06-18 09:53:52 UTC
5365 09:54:50.946634 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5366 09:54:50.953811 ELOG: Event(A0) added with size 9 at 2024-06-18 09:53:52 UTC
5367 09:54:50.957089 elog_add_boot_reason: Logged dev mode boot
5368 09:54:50.957598 Finalize devices...
5369 09:54:50.960170 Devices finalized
5370 09:54:50.963932 BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0
5371 09:54:50.969657 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5372 09:54:50.973650 ELOG: Event(91) added with size 10 at 2024-06-18 09:53:53 UTC
5373 09:54:50.976351 Writing coreboot table at 0xffeda000
5374 09:54:50.983233 0. 0000000000114000-000000000011efff: RAMSTAGE
5375 09:54:50.986461 1. 0000000040000000-000000004023cfff: RAMSTAGE
5376 09:54:50.989901 2. 000000004023d000-00000000545fffff: RAM
5377 09:54:50.993131 3. 0000000054600000-000000005465ffff: BL31
5378 09:54:50.996580 4. 0000000054660000-00000000ffed9fff: RAM
5379 09:54:51.003369 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5380 09:54:51.006657 6. 0000000100000000-000000013fffffff: RAM
5381 09:54:51.009767 Passing 5 GPIOs to payload:
5382 09:54:51.012917 NAME | PORT | POLARITY | VALUE
5383 09:54:51.019588 write protect | 0x00000096 | low | low
5384 09:54:51.022867 EC in RW | 0x000000b1 | high | undefined
5385 09:54:51.026104 EC interrupt | 0x00000097 | low | undefined
5386 09:54:51.032704 TPM interrupt | 0x00000099 | high | undefined
5387 09:54:51.036260 speaker enable | 0x000000af | high | undefined
5388 09:54:51.039338 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5389 09:54:51.042747 in-header: 03 f7 00 00 02 00 00 00
5390 09:54:51.045914 in-data: 04 00
5391 09:54:51.046463 Board ID: 4
5392 09:54:51.049301 ADC[3]: Raw value=215860 ID=1
5393 09:54:51.049847 RAM code: 1
5394 09:54:51.050263 SKU ID: 16
5395 09:54:51.055934 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5396 09:54:51.059313 CBFS @ 21000 size 3d4000
5397 09:54:51.062513 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5398 09:54:51.069519 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 77ff
5399 09:54:51.072832 coreboot table: 940 bytes.
5400 09:54:51.075884 IMD ROOT 0. 00000000fffff000 00001000
5401 09:54:51.079292 IMD SMALL 1. 00000000ffffe000 00001000
5402 09:54:51.082407 CONSOLE 2. 00000000fffde000 00020000
5403 09:54:51.085753 FMAP 3. 00000000fffdd000 0000047c
5404 09:54:51.089700 TIME STAMP 4. 00000000fffdc000 00000910
5405 09:54:51.092659 RAMOOPS 5. 00000000ffedc000 00100000
5406 09:54:51.095638 COREBOOT 6. 00000000ffeda000 00002000
5407 09:54:51.098938 IMD small region:
5408 09:54:51.102606 IMD ROOT 0. 00000000ffffec00 00000400
5409 09:54:51.106014 VBOOT WORK 1. 00000000ffffeb00 00000100
5410 09:54:51.109043 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5411 09:54:51.112515 VPD 3. 00000000ffffea60 0000006c
5412 09:54:51.119027 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5413 09:54:51.125912 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5414 09:54:51.128949 in-header: 03 e1 00 00 08 00 00 00
5415 09:54:51.132246 in-data: 84 20 60 10 00 00 00 00
5416 09:54:51.135814 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5417 09:54:51.139229 CBFS @ 21000 size 3d4000
5418 09:54:51.142468 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5419 09:54:51.145573 CBFS: Locating 'fallback/payload'
5420 09:54:51.155122 CBFS: Found @ offset dc040 size 439a0
5421 09:54:51.242951 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5422 09:54:51.246239 Checking segment from ROM address 0x0000000040003a00
5423 09:54:51.252659 Checking segment from ROM address 0x0000000040003a1c
5424 09:54:51.256418 Loading segment from ROM address 0x0000000040003a00
5425 09:54:51.259889 code (compression=0)
5426 09:54:51.269197 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5427 09:54:51.276029 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5428 09:54:51.279610 it's not compressed!
5429 09:54:51.282410 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5430 09:54:51.289034 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5431 09:54:51.297411 Loading segment from ROM address 0x0000000040003a1c
5432 09:54:51.300905 Entry Point 0x0000000080000000
5433 09:54:51.301457 Loaded segments
5434 09:54:51.307271 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5435 09:54:51.310843 Jumping to boot code at 0000000080000000(00000000ffeda000)
5436 09:54:51.320877 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5437 09:54:51.324007 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5438 09:54:51.327519 CBFS @ 21000 size 3d4000
5439 09:54:51.334325 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5440 09:54:51.334876 CBFS: Locating 'fallback/bl31'
5441 09:54:51.337316 CBFS: Found @ offset 36dc0 size 5820
5442 09:54:51.351055 read SPI 0x57de8 0x5820: 6881 us, 3278 KB/s, 26.224 Mbps
5443 09:54:51.353981 Checking segment from ROM address 0x0000000040003a00
5444 09:54:51.360994 Checking segment from ROM address 0x0000000040003a1c
5445 09:54:51.364462 Loading segment from ROM address 0x0000000040003a00
5446 09:54:51.367641 code (compression=1)
5447 09:54:51.374599 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5448 09:54:51.384136 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5449 09:54:51.384592 using LZMA
5450 09:54:51.392781 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5451 09:54:51.399847 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5452 09:54:51.403199 Loading segment from ROM address 0x0000000040003a1c
5453 09:54:51.406050 Entry Point 0x0000000054601000
5454 09:54:51.406513 Loaded segments
5455 09:54:51.409623 NOTICE: MT8183 bl31_setup
5456 09:54:51.416480 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5457 09:54:51.419783 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5458 09:54:51.423180 INFO: [DEVAPC] dump DEVAPC registers:
5459 09:54:51.433401 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5460 09:54:51.439845 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5461 09:54:51.447075 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5462 09:54:51.456717 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5463 09:54:51.466647 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5464 09:54:51.473569 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5465 09:54:51.483714 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5466 09:54:51.490288 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5467 09:54:51.496536 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5468 09:54:51.506710 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5469 09:54:51.513277 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5470 09:54:51.522920 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5471 09:54:51.529787 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5472 09:54:51.536390 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5473 09:54:51.546781 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5474 09:54:51.553359 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5475 09:54:51.560156 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5476 09:54:51.566613 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5477 09:54:51.576407 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5478 09:54:51.582909 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5479 09:54:51.589871 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5480 09:54:51.596440 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5481 09:54:51.599730 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5482 09:54:51.603005 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5483 09:54:51.606007 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5484 09:54:51.609273 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5485 09:54:51.612890 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5486 09:54:51.619590 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5487 09:54:51.623072 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5488 09:54:51.626285 WARNING: region 0:
5489 09:54:51.629351 WARNING: apc:0x168, sa:0x0, ea:0xfff
5490 09:54:51.632337 WARNING: region 1:
5491 09:54:51.635857 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5492 09:54:51.636271 WARNING: region 2:
5493 09:54:51.639178 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5494 09:54:51.642663 WARNING: region 3:
5495 09:54:51.645774 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5496 09:54:51.646192 WARNING: region 4:
5497 09:54:51.652104 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5498 09:54:51.652598 WARNING: region 5:
5499 09:54:51.655981 WARNING: apc:0x0, sa:0x0, ea:0x0
5500 09:54:51.659049 WARNING: region 6:
5501 09:54:51.662189 WARNING: apc:0x0, sa:0x0, ea:0x0
5502 09:54:51.662742 WARNING: region 7:
5503 09:54:51.665366 WARNING: apc:0x0, sa:0x0, ea:0x0
5504 09:54:51.672343 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5505 09:54:51.675670 INFO: SPM: enable SPMC mode
5506 09:54:51.678843 NOTICE: spm_boot_init() start
5507 09:54:51.682236 NOTICE: spm_boot_init() end
5508 09:54:51.685366 INFO: BL31: Initializing runtime services
5509 09:54:51.692410 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5510 09:54:51.695450 INFO: BL31: Preparing for EL3 exit to normal world
5511 09:54:51.698860 INFO: Entry point address = 0x80000000
5512 09:54:51.701740 INFO: SPSR = 0x8
5513 09:54:51.723179
5514 09:54:51.723791
5515 09:54:51.724157
5516 09:54:51.725891 end: 2.2.3 depthcharge-start (duration 00:00:11) [common]
5517 09:54:51.726421 start: 2.2.4 bootloader-commands (timeout 00:04:24) [common]
5518 09:54:51.726862 Setting prompt string to ['jacuzzi:']
5519 09:54:51.727278 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:24)
5520 09:54:51.728032 Starting depthcharge on Juniper...
5521 09:54:51.728416
5522 09:54:51.729477 vboot_handoff: creating legacy vboot_handoff structure
5523 09:54:51.729940
5524 09:54:51.732808 ec_init(0): CrosEC protocol v3 supported (544, 544)
5525 09:54:51.733268
5526 09:54:51.736171 Wipe memory regions:
5527 09:54:51.736584
5528 09:54:51.739141 [0x00000040000000, 0x00000054600000)
5529 09:54:51.782479
5530 09:54:51.783026 [0x00000054660000, 0x00000080000000)
5531 09:54:51.874150
5532 09:54:51.874695 [0x000000811994a0, 0x000000ffeda000)
5533 09:54:52.133949
5534 09:54:52.134458 [0x00000100000000, 0x00000140000000)
5535 09:54:52.266281
5536 09:54:52.269818 Initializing XHCI USB controller at 0x11200000.
5537 09:54:52.292919
5538 09:54:52.295905 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5539 09:54:52.296368
5540 09:54:52.296733
5541 09:54:52.297550 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5543 09:54:52.398872 jacuzzi: tftpboot 192.168.201.1 14407602/tftp-deploy-bxltqb1m/kernel/image.itb 14407602/tftp-deploy-bxltqb1m/kernel/cmdline
5544 09:54:52.399602 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5545 09:54:52.400111 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
5546 09:54:52.404752 tftpboot 192.168.201.1 14407602/tftp-deploy-bxltqb1m/kernel/image.ittp-deploy-bxltqb1m/kernel/cmdline
5547 09:54:52.405222
5548 09:54:52.405583 Waiting for link
5549 09:54:52.806890
5550 09:54:52.807477 R8152: Initializing
5551 09:54:52.807915
5552 09:54:52.810214 Version 9 (ocp_data = 6010)
5553 09:54:52.810765
5554 09:54:52.813297 R8152: Done initializing
5555 09:54:52.813774
5556 09:54:52.814132 Adding net device
5557 09:54:53.199204
5558 09:54:53.199821 done.
5559 09:54:53.200287
5560 09:54:53.200689 MAC: 00:e0:4c:68:0b:b9
5561 09:54:53.201088
5562 09:54:53.202293 Sending DHCP discover... done.
5563 09:54:53.202717
5564 09:54:53.205676 Waiting for reply... done.
5565 09:54:53.206213
5566 09:54:53.208780 Sending DHCP request... done.
5567 09:54:53.209205
5568 09:54:53.212347 Waiting for reply... done.
5569 09:54:53.212775
5570 09:54:53.213200 My ip is 192.168.201.13
5571 09:54:53.213605
5572 09:54:53.215607 The DHCP server ip is 192.168.201.1
5573 09:54:53.216036
5574 09:54:53.222172 TFTP server IP predefined by user: 192.168.201.1
5575 09:54:53.222692
5576 09:54:53.228844 Bootfile predefined by user: 14407602/tftp-deploy-bxltqb1m/kernel/image.itb
5577 09:54:53.229367
5578 09:54:53.231995 Sending tftp read request... done.
5579 09:54:53.232424
5580 09:54:53.237715 Waiting for the transfer...
5581 09:54:53.238184
5582 09:54:53.566512 00000000 ################################################################
5583 09:54:53.566658
5584 09:54:53.866112 00080000 ################################################################
5585 09:54:53.866264
5586 09:54:54.169011 00100000 ################################################################
5587 09:54:54.169163
5588 09:54:54.467728 00180000 ################################################################
5589 09:54:54.467870
5590 09:54:54.774989 00200000 ################################################################
5591 09:54:54.775136
5592 09:54:55.101618 00280000 ################################################################
5593 09:54:55.102129
5594 09:54:55.489185 00300000 ################################################################
5595 09:54:55.489709
5596 09:54:55.884583 00380000 ################################################################
5597 09:54:55.885089
5598 09:54:56.264920 00400000 ################################################################
5599 09:54:56.265469
5600 09:54:56.617526 00480000 ################################################################
5601 09:54:56.618073
5602 09:54:57.000312 00500000 ################################################################
5603 09:54:57.000847
5604 09:54:57.308788 00580000 ################################################################
5605 09:54:57.308938
5606 09:54:57.584915 00600000 ################################################################
5607 09:54:57.585064
5608 09:54:57.929561 00680000 ################################################################
5609 09:54:57.930249
5610 09:54:58.236612 00700000 ################################################################
5611 09:54:58.236794
5612 09:54:58.532097 00780000 ################################################################
5613 09:54:58.532248
5614 09:54:58.837516 00800000 ################################################################
5615 09:54:58.837693
5616 09:54:59.141160 00880000 ################################################################
5617 09:54:59.141310
5618 09:54:59.508297 00900000 ################################################################
5619 09:54:59.508436
5620 09:54:59.805105 00980000 ################################################################
5621 09:54:59.805254
5622 09:55:00.209962 00a00000 ################################################################
5623 09:55:00.210482
5624 09:55:00.628872 00a80000 ################################################################
5625 09:55:00.629416
5626 09:55:01.056959 00b00000 ################################################################
5627 09:55:01.057483
5628 09:55:01.454370 00b80000 ################################################################
5629 09:55:01.455012
5630 09:55:01.830808 00c00000 ################################################################
5631 09:55:01.831331
5632 09:55:02.226846 00c80000 ################################################################
5633 09:55:02.227445
5634 09:55:02.590903 00d00000 ################################################################
5635 09:55:02.591085
5636 09:55:02.876079 00d80000 ################################################################
5637 09:55:02.876235
5638 09:55:03.254105 00e00000 ################################################################
5639 09:55:03.254610
5640 09:55:03.639126 00e80000 ################################################################
5641 09:55:03.639815
5642 09:55:04.016952 00f00000 ################################################################
5643 09:55:04.017459
5644 09:55:04.403849 00f80000 ################################################################
5645 09:55:04.404417
5646 09:55:04.806303 01000000 ################################################################
5647 09:55:04.806878
5648 09:55:05.199452 01080000 ################################################################
5649 09:55:05.199949
5650 09:55:05.575757 01100000 ################################################################
5651 09:55:05.576259
5652 09:55:05.954166 01180000 ################################################################
5653 09:55:05.954667
5654 09:55:06.274575 01200000 ################################################################
5655 09:55:06.274728
5656 09:55:06.568740 01280000 ################################################################
5657 09:55:06.568897
5658 09:55:06.868963 01300000 ################################################################
5659 09:55:06.869116
5660 09:55:07.157591 01380000 ################################################################
5661 09:55:07.157747
5662 09:55:07.444756 01400000 ################################################################
5663 09:55:07.444906
5664 09:55:07.816973 01480000 ################################################################
5665 09:55:07.817481
5666 09:55:08.112566 01500000 ################################################################
5667 09:55:08.112720
5668 09:55:08.418029 01580000 ################################################################
5669 09:55:08.418185
5670 09:55:08.751731 01600000 ################################################################
5671 09:55:08.752228
5672 09:55:09.128045 01680000 ################################################################
5673 09:55:09.128547
5674 09:55:09.528030 01700000 ################################################################
5675 09:55:09.528719
5676 09:55:09.936198 01780000 ################################################################
5677 09:55:09.936746
5678 09:55:10.227974 01800000 ################################################################
5679 09:55:10.228126
5680 09:55:10.517522 01880000 ################################################################
5681 09:55:10.517670
5682 09:55:10.884981 01900000 ################################################################
5683 09:55:10.885538
5684 09:55:11.263763 01980000 ################################################################
5685 09:55:11.264275
5686 09:55:11.646513 01a00000 ################################################################
5687 09:55:11.647022
5688 09:55:12.023109 01a80000 ################################################################
5689 09:55:12.023692
5690 09:55:12.425740 01b00000 ################################################################
5691 09:55:12.426229
5692 09:55:12.829095 01b80000 ################################################################
5693 09:55:12.829787
5694 09:55:13.150576 01c00000 ################################################################
5695 09:55:13.150734
5696 09:55:13.425650 01c80000 ################################################################
5697 09:55:13.425802
5698 09:55:13.706599 01d00000 ################################################################
5699 09:55:13.706747
5700 09:55:13.991379 01d80000 ################################################################
5701 09:55:13.991537
5702 09:55:14.344351 01e00000 ################################################################
5703 09:55:14.344500
5704 09:55:14.644215 01e80000 ################################################################
5705 09:55:14.644367
5706 09:55:14.944001 01f00000 ################################################################
5707 09:55:14.944154
5708 09:55:15.279835 01f80000 ################################################################
5709 09:55:15.280471
5710 09:55:15.669100 02000000 ################################################################
5711 09:55:15.669600
5712 09:55:16.054018 02080000 ################################################################
5713 09:55:16.054658
5714 09:55:16.444472 02100000 ################################################################
5715 09:55:16.445003
5716 09:55:16.780584 02180000 ################################################################
5717 09:55:16.780735
5718 09:55:17.117507 02200000 ################################################################
5719 09:55:17.117663
5720 09:55:17.377495 02280000 ################################################################
5721 09:55:17.377675
5722 09:55:17.643155 02300000 ################################################################
5723 09:55:17.643326
5724 09:55:17.941870 02380000 ################################################################
5725 09:55:17.942052
5726 09:55:18.228475 02400000 ################################################################
5727 09:55:18.228649
5728 09:55:18.501249 02480000 ################################################################
5729 09:55:18.501398
5730 09:55:18.886001 02500000 ################################################################
5731 09:55:18.886512
5732 09:55:19.257694 02580000 ################################################################
5733 09:55:19.257873
5734 09:55:19.542589 02600000 ################################################################
5735 09:55:19.542771
5736 09:55:19.827714 02680000 ################################################################
5737 09:55:19.827894
5738 09:55:20.116695 02700000 ################################################################
5739 09:55:20.116842
5740 09:55:20.412106 02780000 ################################################################
5741 09:55:20.412253
5742 09:55:20.737986 02800000 ################################################################
5743 09:55:20.738611
5744 09:55:21.141669 02880000 ################################################################
5745 09:55:21.142176
5746 09:55:21.564944 02900000 ################################################################
5747 09:55:21.565465
5748 09:55:21.876954 02980000 ################################################################
5749 09:55:21.877110
5750 09:55:22.135678 02a00000 ################################################################
5751 09:55:22.135832
5752 09:55:22.430188 02a80000 ################################################################
5753 09:55:22.430336
5754 09:55:22.779969 02b00000 ################################################################
5755 09:55:22.780458
5756 09:55:23.171849 02b80000 ################################################################
5757 09:55:23.172342
5758 09:55:23.560440 02c00000 ################################################################
5759 09:55:23.560673
5760 09:55:23.953937 02c80000 ################################################################
5761 09:55:23.954438
5762 09:55:24.263998 02d00000 ################################################################
5763 09:55:24.264146
5764 09:55:24.577046 02d80000 ################################################################
5765 09:55:24.577560
5766 09:55:24.920859 02e00000 ################################################################
5767 09:55:24.921003
5768 09:55:25.206075 02e80000 ################################################################
5769 09:55:25.206226
5770 09:55:25.485066 02f00000 ################################################################
5771 09:55:25.485209
5772 09:55:25.751143 02f80000 ################################################################
5773 09:55:25.751299
5774 09:55:26.040900 03000000 ################################################################
5775 09:55:26.041049
5776 09:55:26.319268 03080000 ################################################################
5777 09:55:26.319417
5778 09:55:26.599023 03100000 ################################################################
5779 09:55:26.599172
5780 09:55:26.888282 03180000 ################################################################
5781 09:55:26.888436
5782 09:55:27.184395 03200000 ################################################################
5783 09:55:27.184545
5784 09:55:27.486927 03280000 ################################################################
5785 09:55:27.487076
5786 09:55:27.771546 03300000 ################################################################
5787 09:55:27.771696
5788 09:55:27.994470 03380000 ################################################## done.
5789 09:55:27.994620
5790 09:55:27.997676 The bootfile was 54406282 bytes long.
5791 09:55:27.997774
5792 09:55:28.000803 Sending tftp read request... done.
5793 09:55:28.000901
5794 09:55:28.004535 Waiting for the transfer...
5795 09:55:28.004717
5796 09:55:28.004810 00000000 # done.
5797 09:55:28.004896
5798 09:55:28.014658 Command line loaded dynamically from TFTP file: 14407602/tftp-deploy-bxltqb1m/kernel/cmdline
5799 09:55:28.015158
5800 09:55:28.031635 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
5801 09:55:28.032175
5802 09:55:28.032501 Loading FIT.
5803 09:55:28.032811
5804 09:55:28.034632 Image ramdisk-1 has 41219809 bytes.
5805 09:55:28.035037
5806 09:55:28.038326 Image fdt-1 has 57695 bytes.
5807 09:55:28.038833
5808 09:55:28.040824 Image kernel-1 has 13126726 bytes.
5809 09:55:28.041228
5810 09:55:28.050993 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5811 09:55:28.051459
5812 09:55:28.061428 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5813 09:55:28.061948
5814 09:55:28.068092 Choosing best match conf-1 for compat google,juniper-sku16.
5815 09:55:28.071466
5816 09:55:28.076402 Connected to device vid:did:rid of 1ae0:0028:00
5817 09:55:28.084330
5818 09:55:28.087384 tpm_get_response: command 0x17b, return code 0x0
5819 09:55:28.087865
5820 09:55:28.090689 tpm_cleanup: add release locality here.
5821 09:55:28.091194
5822 09:55:28.094022 Shutting down all USB controllers.
5823 09:55:28.094432
5824 09:55:28.097243 Removing current net device
5825 09:55:28.097647
5826 09:55:28.100722 Exiting depthcharge with code 4 at timestamp: 53632682
5827 09:55:28.101129
5828 09:55:28.104273 LZMA decompressing kernel-1 to 0x80193568
5829 09:55:28.104675
5830 09:55:28.107797 LZMA decompressing kernel-1 to 0x40000000
5831 09:55:29.975791
5832 09:55:29.976321 jumping to kernel
5833 09:55:29.978357 end: 2.2.4 bootloader-commands (duration 00:00:38) [common]
5834 09:55:29.978932 start: 2.2.5 auto-login-action (timeout 00:03:46) [common]
5835 09:55:29.979337 Setting prompt string to ['Linux version [0-9]']
5836 09:55:29.979771 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5837 09:55:29.980146 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5838 09:55:30.051607
5839 09:55:30.054650 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5840 09:55:30.058557 start: 2.2.5.1 login-action (timeout 00:03:46) [common]
5841 09:55:30.059156 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5842 09:55:30.059627 Setting prompt string to []
5843 09:55:30.060051 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5844 09:55:30.060443 Using line separator: #'\n'#
5845 09:55:30.061001 No login prompt set.
5846 09:55:30.061359 Parsing kernel messages
5847 09:55:30.061668 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5848 09:55:30.062234 [login-action] Waiting for messages, (timeout 00:03:46)
5849 09:55:30.062596 Waiting using forced prompt support (timeout 00:01:53)
5850 09:55:30.077821 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
5851 09:55:30.081423 [ 0.000000] random: crng init done
5852 09:55:30.087840 [ 0.000000] Machine model: Google juniper sku16 board
5853 09:55:30.090901 [ 0.000000] efi: UEFI not found.
5854 09:55:30.097613 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5855 09:55:30.108018 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5856 09:55:30.114845 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5857 09:55:30.117778 [ 0.000000] printk: bootconsole [mtk8250] enabled
5858 09:55:30.126385 [ 0.000000] NUMA: No NUMA configuration found
5859 09:55:30.133312 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5860 09:55:30.139296 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bda00-0x13f7bffff]
5861 09:55:30.139848 [ 0.000000] Zone ranges:
5862 09:55:30.146164 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5863 09:55:30.149540 [ 0.000000] DMA32 empty
5864 09:55:30.156564 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5865 09:55:30.159750 [ 0.000000] Movable zone start for each node
5866 09:55:30.162930 [ 0.000000] Early memory node ranges
5867 09:55:30.169688 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5868 09:55:30.176222 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5869 09:55:30.183127 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5870 09:55:30.188984 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5871 09:55:30.196010 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5872 09:55:30.202281 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5873 09:55:30.218400 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5874 09:55:30.226066 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5875 09:55:30.232112 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5876 09:55:30.235157 [ 0.000000] psci: probing for conduit method from DT.
5877 09:55:30.242016 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5878 09:55:30.245196 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5879 09:55:30.252122 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5880 09:55:30.255261 [ 0.000000] psci: SMC Calling Convention v1.1
5881 09:55:30.262085 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5882 09:55:30.265269 [ 0.000000] Detected VIPT I-cache on CPU0
5883 09:55:30.272057 [ 0.000000] CPU features: detected: GIC system register CPU interface
5884 09:55:30.278471 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5885 09:55:30.285315 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5886 09:55:30.288763 [ 0.000000] CPU features: detected: ARM erratum 845719
5887 09:55:30.295619 [ 0.000000] alternatives: applying boot alternatives
5888 09:55:30.298927 [ 0.000000] Fallback order for Node 0: 0
5889 09:55:30.305285 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5890 09:55:30.308521 [ 0.000000] Policy zone: Normal
5891 09:55:30.328413 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
5892 09:55:30.342059 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5893 09:55:30.348226 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5894 09:55:30.358172 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5895 09:55:30.364742 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5896 09:55:30.368106 <6>[ 0.000000] software IO TLB: area num 8.
5897 09:55:30.393362 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5898 09:55:30.451437 <6>[ 0.000000] Memory: 3874820K/4191232K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 283644K reserved, 32768K cma-reserved)
5899 09:55:30.457947 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5900 09:55:30.464718 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5901 09:55:30.467645 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5902 09:55:30.474742 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5903 09:55:30.481375 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5904 09:55:30.484439 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5905 09:55:30.494597 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5906 09:55:30.501591 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5907 09:55:30.504921 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5908 09:55:30.516371 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5909 09:55:30.523248 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5910 09:55:30.526458 <6>[ 0.000000] GICv3: 640 SPIs implemented
5911 09:55:30.529602 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5912 09:55:30.536528 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5913 09:55:30.540109 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5914 09:55:30.546552 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5915 09:55:30.556196 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5916 09:55:30.569534 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5917 09:55:30.576070 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5918 09:55:30.588384 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5919 09:55:30.601526 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5920 09:55:30.608343 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5921 09:55:30.615277 <6>[ 0.009483] Console: colour dummy device 80x25
5922 09:55:30.618534 <6>[ 0.014521] printk: console [tty1] enabled
5923 09:55:30.628446 <6>[ 0.018907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5924 09:55:30.635123 <6>[ 0.029371] pid_max: default: 32768 minimum: 301
5925 09:55:30.638293 <6>[ 0.034253] LSM: Security Framework initializing
5926 09:55:30.648159 <6>[ 0.039168] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5927 09:55:30.654930 <6>[ 0.046792] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5928 09:55:30.661518 <4>[ 0.055666] cacheinfo: Unable to detect cache hierarchy for CPU 0
5929 09:55:30.671494 <6>[ 0.062293] cblist_init_generic: Setting adjustable number of callback queues.
5930 09:55:30.678073 <6>[ 0.069739] cblist_init_generic: Setting shift to 3 and lim to 1.
5931 09:55:30.684791 <6>[ 0.076093] cblist_init_generic: Setting adjustable number of callback queues.
5932 09:55:30.691348 <6>[ 0.083538] cblist_init_generic: Setting shift to 3 and lim to 1.
5933 09:55:30.694549 <6>[ 0.089937] rcu: Hierarchical SRCU implementation.
5934 09:55:30.700962 <6>[ 0.094963] rcu: Max phase no-delay instances is 1000.
5935 09:55:30.708147 <6>[ 0.102894] EFI services will not be available.
5936 09:55:30.711591 <6>[ 0.107839] smp: Bringing up secondary CPUs ...
5937 09:55:30.722308 <6>[ 0.113103] Detected VIPT I-cache on CPU1
5938 09:55:30.728984 <4>[ 0.113150] cacheinfo: Unable to detect cache hierarchy for CPU 1
5939 09:55:30.735571 <6>[ 0.113160] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5940 09:55:30.742195 <6>[ 0.113193] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5941 09:55:30.745272 <6>[ 0.113673] Detected VIPT I-cache on CPU2
5942 09:55:30.752168 <4>[ 0.113705] cacheinfo: Unable to detect cache hierarchy for CPU 2
5943 09:55:30.758990 <6>[ 0.113710] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5944 09:55:30.764905 <6>[ 0.113722] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5945 09:55:30.768285 <6>[ 0.114167] Detected VIPT I-cache on CPU3
5946 09:55:30.775351 <4>[ 0.114197] cacheinfo: Unable to detect cache hierarchy for CPU 3
5947 09:55:30.784922 <6>[ 0.114202] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5948 09:55:30.791364 <6>[ 0.114213] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5949 09:55:30.794705 <6>[ 0.114788] CPU features: detected: Spectre-v2
5950 09:55:30.798274 <6>[ 0.114798] CPU features: detected: Spectre-BHB
5951 09:55:30.804753 <6>[ 0.114802] CPU features: detected: ARM erratum 858921
5952 09:55:30.807847 <6>[ 0.114807] Detected VIPT I-cache on CPU4
5953 09:55:30.814470 <4>[ 0.114855] cacheinfo: Unable to detect cache hierarchy for CPU 4
5954 09:55:30.821249 <6>[ 0.114863] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5955 09:55:30.831104 <6>[ 0.114871] arch_timer: Enabling local workaround for ARM erratum 858921
5956 09:55:30.834349 <6>[ 0.114881] arch_timer: CPU4: Trapping CNTVCT access
5957 09:55:30.841144 <6>[ 0.114889] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5958 09:55:30.847796 <6>[ 0.115375] Detected VIPT I-cache on CPU5
5959 09:55:30.850991 <4>[ 0.115416] cacheinfo: Unable to detect cache hierarchy for CPU 5
5960 09:55:30.860547 <6>[ 0.115421] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5961 09:55:30.867135 <6>[ 0.115428] arch_timer: Enabling local workaround for ARM erratum 858921
5962 09:55:30.870583 <6>[ 0.115435] arch_timer: CPU5: Trapping CNTVCT access
5963 09:55:30.877320 <6>[ 0.115440] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5964 09:55:30.883858 <6>[ 0.115875] Detected VIPT I-cache on CPU6
5965 09:55:30.887648 <4>[ 0.115920] cacheinfo: Unable to detect cache hierarchy for CPU 6
5966 09:55:30.897182 <6>[ 0.115926] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5967 09:55:30.903526 <6>[ 0.115933] arch_timer: Enabling local workaround for ARM erratum 858921
5968 09:55:30.906756 <6>[ 0.115939] arch_timer: CPU6: Trapping CNTVCT access
5969 09:55:30.913750 <6>[ 0.115944] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5970 09:55:30.920059 <6>[ 0.116475] Detected VIPT I-cache on CPU7
5971 09:55:30.926544 <4>[ 0.116519] cacheinfo: Unable to detect cache hierarchy for CPU 7
5972 09:55:30.933558 <6>[ 0.116525] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5973 09:55:30.939864 <6>[ 0.116532] arch_timer: Enabling local workaround for ARM erratum 858921
5974 09:55:30.943306 <6>[ 0.116538] arch_timer: CPU7: Trapping CNTVCT access
5975 09:55:30.949852 <6>[ 0.116544] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5976 09:55:30.956494 <6>[ 0.116592] smp: Brought up 1 node, 8 CPUs
5977 09:55:30.959860 <6>[ 0.355493] SMP: Total of 8 processors activated.
5978 09:55:30.966337 <6>[ 0.360427] CPU features: detected: 32-bit EL0 Support
5979 09:55:30.970324 <6>[ 0.365805] CPU features: detected: 32-bit EL1 Support
5980 09:55:30.976753 <6>[ 0.371173] CPU features: detected: CRC32 instructions
5981 09:55:30.980080 <6>[ 0.376599] CPU: All CPU(s) started at EL2
5982 09:55:30.987016 <6>[ 0.380937] alternatives: applying system-wide alternatives
5983 09:55:30.994836 <6>[ 0.388960] devtmpfs: initialized
5984 09:55:31.006772 <6>[ 0.397889] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5985 09:55:31.016446 <6>[ 0.407839] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5986 09:55:31.020319 <6>[ 0.415567] pinctrl core: initialized pinctrl subsystem
5987 09:55:31.028386 <6>[ 0.422693] DMI not present or invalid.
5988 09:55:31.034725 <6>[ 0.427060] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5989 09:55:31.041685 <6>[ 0.433959] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5990 09:55:31.051710 <6>[ 0.441486] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5991 09:55:31.058376 <6>[ 0.449737] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5992 09:55:31.064281 <6>[ 0.457914] audit: initializing netlink subsys (disabled)
5993 09:55:31.071123 <5>[ 0.463618] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5994 09:55:31.077931 <6>[ 0.464595] thermal_sys: Registered thermal governor 'step_wise'
5995 09:55:31.084234 <6>[ 0.471585] thermal_sys: Registered thermal governor 'power_allocator'
5996 09:55:31.087601 <6>[ 0.477883] cpuidle: using governor menu
5997 09:55:31.094882 <6>[ 0.488848] NET: Registered PF_QIPCRTR protocol family
5998 09:55:31.101214 <6>[ 0.494333] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5999 09:55:31.107903 <6>[ 0.501430] ASID allocator initialised with 32768 entries
6000 09:55:31.111684 <6>[ 0.508195] Serial: AMBA PL011 UART driver
6001 09:55:31.124037 <4>[ 0.518616] Trying to register duplicate clock ID: 113
6002 09:55:31.183561 <6>[ 0.574931] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6003 09:55:31.198280 <6>[ 0.589281] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6004 09:55:31.201807 <6>[ 0.599039] KASLR enabled
6005 09:55:31.216017 <6>[ 0.607038] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
6006 09:55:31.219709 <6>[ 0.614039] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
6007 09:55:31.229739 <6>[ 0.620516] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
6008 09:55:31.236054 <6>[ 0.627506] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
6009 09:55:31.242577 <6>[ 0.633980] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
6010 09:55:31.249328 <6>[ 0.640970] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
6011 09:55:31.256037 <6>[ 0.647445] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
6012 09:55:31.262509 <6>[ 0.654434] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
6013 09:55:31.265542 <6>[ 0.662003] ACPI: Interpreter disabled.
6014 09:55:31.275660 <6>[ 0.670006] iommu: Default domain type: Translated
6015 09:55:31.282262 <6>[ 0.675113] iommu: DMA domain TLB invalidation policy: strict mode
6016 09:55:31.285393 <5>[ 0.681743] SCSI subsystem initialized
6017 09:55:31.292306 <6>[ 0.686159] usbcore: registered new interface driver usbfs
6018 09:55:31.298605 <6>[ 0.691887] usbcore: registered new interface driver hub
6019 09:55:31.301700 <6>[ 0.697428] usbcore: registered new device driver usb
6020 09:55:31.309520 <6>[ 0.703739] pps_core: LinuxPPS API ver. 1 registered
6021 09:55:31.319234 <6>[ 0.708923] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
6022 09:55:31.322657 <6>[ 0.718247] PTP clock support registered
6023 09:55:31.326015 <6>[ 0.722500] EDAC MC: Ver: 3.0.0
6024 09:55:31.333815 <6>[ 0.728146] FPGA manager framework
6025 09:55:31.340319 <6>[ 0.731829] Advanced Linux Sound Architecture Driver Initialized.
6026 09:55:31.343971 <6>[ 0.738583] vgaarb: loaded
6027 09:55:31.347355 <6>[ 0.741701] clocksource: Switched to clocksource arch_sys_counter
6028 09:55:31.353557 <5>[ 0.748132] VFS: Disk quotas dquot_6.6.0
6029 09:55:31.360360 <6>[ 0.752308] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
6030 09:55:31.364024 <6>[ 0.759482] pnp: PnP ACPI: disabled
6031 09:55:31.371945 <6>[ 0.766368] NET: Registered PF_INET protocol family
6032 09:55:31.378677 <6>[ 0.771596] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
6033 09:55:31.390649 <6>[ 0.781504] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
6034 09:55:31.396980 <6>[ 0.790260] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
6035 09:55:31.407373 <6>[ 0.798211] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
6036 09:55:31.413814 <6>[ 0.806443] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
6037 09:55:31.419735 <6>[ 0.814536] TCP: Hash tables configured (established 32768 bind 32768)
6038 09:55:31.430613 <6>[ 0.821363] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
6039 09:55:31.436481 <6>[ 0.828335] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
6040 09:55:31.443529 <6>[ 0.835815] NET: Registered PF_UNIX/PF_LOCAL protocol family
6041 09:55:31.450152 <6>[ 0.841911] RPC: Registered named UNIX socket transport module.
6042 09:55:31.453286 <6>[ 0.848055] RPC: Registered udp transport module.
6043 09:55:31.460375 <6>[ 0.852979] RPC: Registered tcp transport module.
6044 09:55:31.466496 <6>[ 0.857903] RPC: Registered tcp NFSv4.1 backchannel transport module.
6045 09:55:31.469808 <6>[ 0.864554] PCI: CLS 0 bytes, default 64
6046 09:55:31.472998 <6>[ 0.868838] Unpacking initramfs...
6047 09:55:31.487364 <6>[ 0.878249] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6048 09:55:31.497126 <6>[ 0.886871] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6049 09:55:31.500075 <6>[ 0.895727] kvm [1]: IPA Size Limit: 40 bits
6050 09:55:31.507820 <6>[ 0.902061] kvm [1]: vgic-v2@c420000
6051 09:55:31.511190 <6>[ 0.905877] kvm [1]: GIC system register CPU interface enabled
6052 09:55:31.518900 <6>[ 0.913774] kvm [1]: vgic interrupt IRQ18
6053 09:55:31.522392 <6>[ 0.918162] kvm [1]: Hyp mode initialized successfully
6054 09:55:31.530289 <5>[ 0.924547] Initialise system trusted keyrings
6055 09:55:31.536376 <6>[ 0.929406] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6056 09:55:31.544621 <6>[ 0.939398] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6057 09:55:31.551800 <5>[ 0.945848] NFS: Registering the id_resolver key type
6058 09:55:31.555159 <5>[ 0.951153] Key type id_resolver registered
6059 09:55:31.561699 <5>[ 0.955565] Key type id_legacy registered
6060 09:55:31.567947 <6>[ 0.959872] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6061 09:55:31.575142 <6>[ 0.966795] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6062 09:55:31.581358 <6>[ 0.974536] 9p: Installing v9fs 9p2000 file system support
6063 09:55:31.608984 <5>[ 1.003521] Key type asymmetric registered
6064 09:55:31.612561 <5>[ 1.007870] Asymmetric key parser 'x509' registered
6065 09:55:31.622694 <6>[ 1.013033] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6066 09:55:31.626014 <6>[ 1.020645] io scheduler mq-deadline registered
6067 09:55:31.629313 <6>[ 1.025404] io scheduler kyber registered
6068 09:55:31.651744 <6>[ 1.046251] EINJ: ACPI disabled.
6069 09:55:31.658609 <4>[ 1.049998] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6070 09:55:31.696258 <6>[ 1.090673] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6071 09:55:31.704834 <6>[ 1.099177] printk: console [ttyS0] disabled
6072 09:55:31.733167 <6>[ 1.123820] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6073 09:55:31.739307 <6>[ 1.133293] printk: console [ttyS0] enabled
6074 09:55:31.742649 <6>[ 1.133293] printk: console [ttyS0] enabled
6075 09:55:31.749364 <6>[ 1.142210] printk: bootconsole [mtk8250] disabled
6076 09:55:31.752672 <6>[ 1.142210] printk: bootconsole [mtk8250] disabled
6077 09:55:31.762383 <3>[ 1.152754] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6078 09:55:31.768842 <3>[ 1.161136] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6079 09:55:31.798312 <6>[ 1.189547] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6080 09:55:31.805403 <6>[ 1.199201] serial serial0: tty port ttyS1 registered
6081 09:55:31.811789 <6>[ 1.205796] SuperH (H)SCI(F) driver initialized
6082 09:55:31.815314 <6>[ 1.211251] msm_serial: driver initialized
6083 09:55:31.830699 <6>[ 1.221576] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6084 09:55:31.840590 <6>[ 1.230177] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6085 09:55:31.846999 <6>[ 1.238750] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6086 09:55:31.856828 <6>[ 1.247318] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6087 09:55:31.863780 <6>[ 1.255972] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6088 09:55:31.873525 <6>[ 1.264635] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6089 09:55:31.883489 <6>[ 1.273374] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6090 09:55:31.890471 <6>[ 1.282112] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6091 09:55:31.900205 <6>[ 1.290681] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6092 09:55:31.909927 <6>[ 1.299481] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6093 09:55:31.917118 <4>[ 1.311928] cacheinfo: Unable to detect cache hierarchy for CPU 0
6094 09:55:31.926749 <6>[ 1.321273] loop: module loaded
6095 09:55:31.938878 <6>[ 1.333222] vsim1: Bringing 1800000uV into 2700000-2700000uV
6096 09:55:31.956727 <6>[ 1.351310] megasas: 07.719.03.00-rc1
6097 09:55:31.965645 <6>[ 1.360222] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6098 09:55:31.974632 <6>[ 1.369089] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6099 09:55:31.991556 <6>[ 1.386007] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6100 09:55:32.048244 <6>[ 1.436276] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1d
6101 09:55:32.782308 <6>[ 2.176815] Freeing initrd memory: 40248K
6102 09:55:32.797835 <4>[ 2.188778] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6103 09:55:32.804379 <4>[ 2.198011] CPU: 7 PID: 1 Comm: swapper/0 Not tainted 6.1.92-cip22 #1
6104 09:55:32.811557 <4>[ 2.204709] Hardware name: Google juniper sku16 board (DT)
6105 09:55:32.814626 <4>[ 2.210448] Call trace:
6106 09:55:32.817831 <4>[ 2.213148] dump_backtrace.part.0+0xe0/0xf0
6107 09:55:32.821263 <4>[ 2.217685] show_stack+0x18/0x30
6108 09:55:32.824203 <4>[ 2.221257] dump_stack_lvl+0x68/0x84
6109 09:55:32.830653 <4>[ 2.225177] dump_stack+0x18/0x34
6110 09:55:32.834352 <4>[ 2.228747] sysfs_warn_dup+0x64/0x80
6111 09:55:32.837480 <4>[ 2.232669] sysfs_do_create_link_sd+0xf0/0x100
6112 09:55:32.840775 <4>[ 2.237456] sysfs_create_link+0x20/0x40
6113 09:55:32.848096 <4>[ 2.241635] bus_add_device+0x68/0x10c
6114 09:55:32.851315 <4>[ 2.245641] device_add+0x340/0x7ac
6115 09:55:32.854485 <4>[ 2.249385] of_device_add+0x44/0x60
6116 09:55:32.860624 <4>[ 2.253219] of_platform_device_create_pdata+0x90/0x120
6117 09:55:32.864505 <4>[ 2.258700] of_platform_bus_create+0x170/0x370
6118 09:55:32.867503 <4>[ 2.263487] of_platform_populate+0x50/0xfc
6119 09:55:32.874452 <4>[ 2.267927] parse_mtd_partitions+0x1dc/0x510
6120 09:55:32.877404 <4>[ 2.272540] mtd_device_parse_register+0xf8/0x2e0
6121 09:55:32.880692 <4>[ 2.277498] spi_nor_probe+0x21c/0x2f0
6122 09:55:32.884001 <4>[ 2.281504] spi_mem_probe+0x6c/0xb0
6123 09:55:32.890966 <4>[ 2.285338] spi_probe+0x84/0xe4
6124 09:55:32.894074 <4>[ 2.288819] really_probe+0xbc/0x2e0
6125 09:55:32.897447 <4>[ 2.292650] __driver_probe_device+0x78/0x11c
6126 09:55:32.900735 <4>[ 2.297262] driver_probe_device+0xd8/0x160
6127 09:55:32.907591 <4>[ 2.301700] __device_attach_driver+0xb8/0x134
6128 09:55:32.911077 <4>[ 2.306399] bus_for_each_drv+0x78/0xd0
6129 09:55:32.914343 <4>[ 2.310489] __device_attach+0xa8/0x1c0
6130 09:55:32.920499 <4>[ 2.314580] device_initial_probe+0x14/0x20
6131 09:55:32.923806 <4>[ 2.319017] bus_probe_device+0x9c/0xa4
6132 09:55:32.927468 <4>[ 2.323108] device_add+0x3ac/0x7ac
6133 09:55:32.930923 <4>[ 2.326850] __spi_add_device+0x78/0x120
6134 09:55:32.934290 <4>[ 2.331028] spi_add_device+0x40/0x7c
6135 09:55:32.940814 <4>[ 2.334946] spi_register_controller+0x610/0xad0
6136 09:55:32.943926 <4>[ 2.339818] devm_spi_register_controller+0x4c/0xa4
6137 09:55:32.951020 <4>[ 2.344951] mtk_spi_probe+0x3f8/0x650
6138 09:55:32.953927 <4>[ 2.348955] platform_probe+0x68/0xe0
6139 09:55:32.957414 <4>[ 2.352874] really_probe+0xbc/0x2e0
6140 09:55:32.960648 <4>[ 2.356704] __driver_probe_device+0x78/0x11c
6141 09:55:32.967334 <4>[ 2.361315] driver_probe_device+0xd8/0x160
6142 09:55:32.970819 <4>[ 2.365753] __driver_attach+0x94/0x19c
6143 09:55:32.974091 <4>[ 2.369843] bus_for_each_dev+0x70/0xd0
6144 09:55:32.977491 <4>[ 2.373933] driver_attach+0x24/0x30
6145 09:55:32.980971 <4>[ 2.377763] bus_add_driver+0x154/0x20c
6146 09:55:32.987552 <4>[ 2.381853] driver_register+0x78/0x130
6147 09:55:32.990679 <4>[ 2.385944] __platform_driver_register+0x28/0x34
6148 09:55:32.997523 <4>[ 2.390904] mtk_spi_driver_init+0x1c/0x28
6149 09:55:33.000461 <4>[ 2.395258] do_one_initcall+0x50/0x1d0
6150 09:55:33.003687 <4>[ 2.399348] kernel_init_freeable+0x21c/0x288
6151 09:55:33.007169 <4>[ 2.403962] kernel_init+0x24/0x12c
6152 09:55:33.010503 <4>[ 2.407707] ret_from_fork+0x10/0x20
6153 09:55:33.022244 <6>[ 2.416651] tun: Universal TUN/TAP device driver, 1.6
6154 09:55:33.025178 <6>[ 2.422943] thunder_xcv, ver 1.0
6155 09:55:33.028720 <6>[ 2.426462] thunder_bgx, ver 1.0
6156 09:55:33.031757 <6>[ 2.429967] nicpf, ver 1.0
6157 09:55:33.042798 <6>[ 2.434352] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6158 09:55:33.046147 <6>[ 2.441837] hns3: Copyright (c) 2017 Huawei Corporation.
6159 09:55:33.053310 <6>[ 2.447435] hclge is initializing
6160 09:55:33.056097 <6>[ 2.451025] e1000: Intel(R) PRO/1000 Network Driver
6161 09:55:33.062696 <6>[ 2.456160] e1000: Copyright (c) 1999-2006 Intel Corporation.
6162 09:55:33.066109 <6>[ 2.462184] e1000e: Intel(R) PRO/1000 Network Driver
6163 09:55:33.073078 <6>[ 2.467404] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6164 09:55:33.079811 <6>[ 2.473597] igb: Intel(R) Gigabit Ethernet Network Driver
6165 09:55:33.086426 <6>[ 2.479252] igb: Copyright (c) 2007-2014 Intel Corporation.
6166 09:55:33.093358 <6>[ 2.485095] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6167 09:55:33.100093 <6>[ 2.491618] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6168 09:55:33.103266 <6>[ 2.498169] sky2: driver version 1.30
6169 09:55:33.109539 <6>[ 2.503424] usbcore: registered new device driver r8152-cfgselector
6170 09:55:33.116009 <6>[ 2.509968] usbcore: registered new interface driver r8152
6171 09:55:33.122770 <6>[ 2.515797] VFIO - User Level meta-driver version: 0.3
6172 09:55:33.129419 <6>[ 2.523588] mtu3 11201000.usb: uwk - reg:0x420, version:101
6173 09:55:33.136010 <4>[ 2.529462] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6174 09:55:33.142830 <6>[ 2.536744] mtu3 11201000.usb: dr_mode: 1, drd: auto
6175 09:55:33.149811 <6>[ 2.541970] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6176 09:55:33.152982 <6>[ 2.548159] mtu3 11201000.usb: usb3-drd: 0
6177 09:55:33.159022 <6>[ 2.553728] mtu3 11201000.usb: xHCI platform device register success...
6178 09:55:33.171308 <4>[ 2.562435] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6179 09:55:33.178023 <6>[ 2.570368] xhci-mtk 11200000.usb: xHCI Host Controller
6180 09:55:33.184539 <6>[ 2.575881] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6181 09:55:33.191051 <6>[ 2.583601] xhci-mtk 11200000.usb: USB3 root hub has no ports
6182 09:55:33.201304 <6>[ 2.589609] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6183 09:55:33.204423 <6>[ 2.599032] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6184 09:55:33.211296 <6>[ 2.605103] xhci-mtk 11200000.usb: xHCI Host Controller
6185 09:55:33.217733 <6>[ 2.610591] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6186 09:55:33.224393 <6>[ 2.618248] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6187 09:55:33.231349 <6>[ 2.625064] hub 1-0:1.0: USB hub found
6188 09:55:33.234794 <6>[ 2.629092] hub 1-0:1.0: 1 port detected
6189 09:55:33.244052 <6>[ 2.634437] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6190 09:55:33.247292 <6>[ 2.643053] hub 2-0:1.0: USB hub found
6191 09:55:33.253983 <3>[ 2.647079] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6192 09:55:33.260833 <6>[ 2.654971] usbcore: registered new interface driver usb-storage
6193 09:55:33.267440 <6>[ 2.661561] usbcore: registered new device driver onboard-usb-hub
6194 09:55:33.278603 <4>[ 2.669808] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6195 09:55:33.287492 <6>[ 2.682139] mt6397-rtc mt6358-rtc: registered as rtc0
6196 09:55:33.297962 <6>[ 2.687619] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-18T09:54:35 UTC (1718704475)
6197 09:55:33.304153 <6>[ 2.697516] i2c_dev: i2c /dev entries driver
6198 09:55:33.314233 <6>[ 2.703932] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6199 09:55:33.320523 <6>[ 2.712252] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6200 09:55:33.327840 <6>[ 2.721156] i2c 4-0058: Fixed dependency cycle(s) with /panel
6201 09:55:33.334505 <6>[ 2.727188] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6202 09:55:33.343907 <3>[ 2.734653] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
6203 09:55:33.360001 <6>[ 2.754598] cpu cpu0: EM: created perf domain
6204 09:55:33.372912 <6>[ 2.760077] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6205 09:55:33.376104 <6>[ 2.771351] cpu cpu4: EM: created perf domain
6206 09:55:33.383369 <6>[ 2.778042] sdhci: Secure Digital Host Controller Interface driver
6207 09:55:33.389874 <6>[ 2.784497] sdhci: Copyright(c) Pierre Ossman
6208 09:55:33.396721 <6>[ 2.789892] Synopsys Designware Multimedia Card Interface Driver
6209 09:55:33.403271 <6>[ 2.790367] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6210 09:55:33.406507 <6>[ 2.796985] sdhci-pltfm: SDHCI platform and OF driver helper
6211 09:55:33.414825 <6>[ 2.809628] ledtrig-cpu: registered to indicate activity on CPUs
6212 09:55:33.423204 <6>[ 2.817415] usbcore: registered new interface driver usbhid
6213 09:55:33.426743 <6>[ 2.823257] usbhid: USB HID core driver
6214 09:55:33.437190 <6>[ 2.827565] spi_master spi2: will run message pump with realtime priority
6215 09:55:33.440742 <4>[ 2.827825] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6216 09:55:33.448240 <4>[ 2.841931] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6217 09:55:33.461416 <6>[ 2.847292] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6218 09:55:33.480875 <6>[ 2.865382] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6219 09:55:33.487312 <4>[ 2.874380] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6220 09:55:33.490409 <6>[ 2.880544] cros-ec-spi spi2.0: Chrome EC device registered
6221 09:55:33.505196 <4>[ 2.896404] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6222 09:55:33.517877 <4>[ 2.908764] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6223 09:55:33.524279 <6>[ 2.917419] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x13014
6224 09:55:33.531150 <4>[ 2.917783] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6225 09:55:33.534381 <6>[ 2.925471] mmc0: new HS400 MMC card at address 0001
6226 09:55:33.541352 <6>[ 2.935739] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6227 09:55:33.547895 <6>[ 2.940234] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6228 09:55:33.558483 <6>[ 2.952798] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6229 09:55:33.568720 <6>[ 2.959955] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6230 09:55:33.575354 <6>[ 2.960047] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6231 09:55:33.585230 <6>[ 2.973093] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6232 09:55:33.588439 <6>[ 2.975138] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6233 09:55:33.595759 <6>[ 2.986457] NET: Registered PF_PACKET protocol family
6234 09:55:33.602212 <6>[ 2.991089] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6235 09:55:33.615198 <6>[ 2.993978] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6236 09:55:33.625345 <6>[ 2.994168] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6237 09:55:33.628626 <6>[ 2.995420] 9pnet: Installing 9P2000 support
6238 09:55:33.631631 <5>[ 3.028587] Key type dns_resolver registered
6239 09:55:33.639250 <6>[ 3.033667] registered taskstats version 1
6240 09:55:33.642633 <5>[ 3.038036] Loading compiled-in X.509 certificates
6241 09:55:33.659184 <6>[ 3.053721] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6242 09:55:33.681196 <3>[ 3.071944] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6243 09:55:33.711874 <6>[ 3.099886] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6244 09:55:33.723575 <6>[ 3.114741] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6245 09:55:33.733567 <6>[ 3.123310] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6246 09:55:33.740546 <6>[ 3.131860] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6247 09:55:33.750457 <6>[ 3.140419] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6248 09:55:33.757131 <6>[ 3.149063] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6249 09:55:33.767367 <6>[ 3.157659] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6250 09:55:33.776635 <6>[ 3.166201] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6251 09:55:33.783586 <6>[ 3.175468] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6252 09:55:33.790165 <6>[ 3.182791] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6253 09:55:33.796474 <6>[ 3.189966] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6254 09:55:33.803362 <6>[ 3.197054] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6255 09:55:33.813190 <6>[ 3.204312] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6256 09:55:33.819732 <6>[ 3.212470] panfrost 13040000.gpu: clock rate = 511999970
6257 09:55:33.829957 <6>[ 3.218163] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6258 09:55:33.836590 <6>[ 3.228526] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6259 09:55:33.840148 <6>[ 3.228964] hub 1-1:1.0: USB hub found
6260 09:55:33.849569 <6>[ 3.236533] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6261 09:55:33.852708 <6>[ 3.240973] hub 1-1:1.0: 3 ports detected
6262 09:55:33.865985 <6>[ 3.248949] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6263 09:55:33.872586 <6>[ 3.265295] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6264 09:55:33.885648 <6>[ 3.276501] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6265 09:55:33.895355 <6>[ 3.285616] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6266 09:55:33.905334 <6>[ 3.294794] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6267 09:55:33.915263 <6>[ 3.303922] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6268 09:55:33.921828 <6>[ 3.313051] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6269 09:55:33.931848 <6>[ 3.322352] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6270 09:55:33.941496 <6>[ 3.331653] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6271 09:55:33.951212 <6>[ 3.341129] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6272 09:55:33.961547 <6>[ 3.350601] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6273 09:55:33.968232 <6>[ 3.359727] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6274 09:55:34.042542 <6>[ 3.433508] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6275 09:55:34.052494 <6>[ 3.442378] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6276 09:55:34.063946 <6>[ 3.454650] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6277 09:55:34.150608 <6>[ 3.541745] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6278 09:55:34.756876 <6>[ 3.734033] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6279 09:55:34.766404 <4>[ 3.851315] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6280 09:55:34.772978 <4>[ 3.851334] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6281 09:55:34.779608 <6>[ 3.903907] r8152 1-1.2:1.0 eth0: v1.12.13
6282 09:55:34.786425 <6>[ 3.985756] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6283 09:55:34.792353 <6>[ 4.129389] Console: switching to colour frame buffer device 170x48
6284 09:55:34.799506 <6>[ 4.191448] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6285 09:55:34.820887 <6>[ 4.208836] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6286 09:55:34.839838 <6>[ 4.227525] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6287 09:55:34.846400 <6>[ 4.239851] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input4
6288 09:55:34.857222 <6>[ 4.248239] input: volume-buttons as /devices/platform/volume-buttons/input/input5
6289 09:55:34.867559 <6>[ 4.255103] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6290 09:55:34.887815 <6>[ 4.275363] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6291 09:55:36.148210 <6>[ 5.542900] r8152 1-1.2:1.0 eth0: carrier on
6292 09:55:38.655757 <5>[ 5.569736] Sending DHCP requests .., OK
6293 09:55:38.662200 <6>[ 8.054260] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.13
6294 09:55:38.665161 <6>[ 8.062696] IP-Config: Complete:
6295 09:55:38.678614 <6>[ 8.066268] device=eth0, hwaddr=00:e0:4c:68:0b:b9, ipaddr=192.168.201.13, mask=255.255.255.0, gw=192.168.201.1
6296 09:55:38.688035 <6>[ 8.077167] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0, domain=lava-rack, nis-domain=(none)
6297 09:55:38.700234 <6>[ 8.091443] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6298 09:55:38.708830 <6>[ 8.091454] nameserver0=192.168.201.1
6299 09:55:38.716899 <6>[ 8.111212] clk: Disabling unused clocks
6300 09:55:38.721905 <6>[ 8.119152] ALSA device list:
6301 09:55:38.730792 <6>[ 8.125194] No soundcards found.
6302 09:55:38.740493 <6>[ 8.134464] Freeing unused kernel memory: 8512K
6303 09:55:38.747474 <6>[ 8.141628] Run /init as init process
6304 09:55:38.777776 <6>[ 8.172256] NET: Registered PF_INET6 protocol family
6305 09:55:38.785549 <6>[ 8.179878] Segment Routing with IPv6
6306 09:55:38.788859 <6>[ 8.184542] In-situ OAM (IOAM) with IPv6
6307 09:55:38.830670 <30>[ 8.198444] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6308 09:55:38.843367 <30>[ 8.237196] systemd[1]: Detected architecture arm64.
6309 09:55:38.850531
6310 09:55:38.853355 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6311 09:55:38.853817
6312 09:55:38.867624 <30>[ 8.261818] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6313 09:55:39.032512 <30>[ 8.423565] systemd[1]: Queued start job for default target graphical.target.
6314 09:55:39.056673 <30>[ 8.447479] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6315 09:55:39.066060 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6316 09:55:39.084080 <30>[ 8.474914] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6317 09:55:39.093637 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6318 09:55:39.116202 <30>[ 8.507265] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6319 09:55:39.126856 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6320 09:55:39.143522 <30>[ 8.534529] systemd[1]: Created slice user.slice - User and Session Slice.
6321 09:55:39.154298 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6322 09:55:39.174849 <30>[ 8.562172] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6323 09:55:39.185740 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6324 09:55:39.206876 <30>[ 8.594085] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6325 09:55:39.218126 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6326 09:55:39.244779 <30>[ 8.626019] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6327 09:55:39.263268 <30>[ 8.654132] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6328 09:55:39.270218 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6329 09:55:39.292003 <30>[ 8.682643] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6330 09:55:39.304124 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6331 09:55:39.322951 <30>[ 8.714018] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6332 09:55:39.336839 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6333 09:55:39.351626 <30>[ 8.746163] systemd[1]: Reached target paths.target - Path Units.
6334 09:55:39.366078 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6335 09:55:39.382555 <30>[ 8.773912] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6336 09:55:39.395478 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6337 09:55:39.407286 <30>[ 8.801881] systemd[1]: Reached target slices.target - Slice Units.
6338 09:55:39.422001 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6339 09:55:39.435382 <30>[ 8.829927] systemd[1]: Reached target swap.target - Swaps.
6340 09:55:39.446309 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6341 09:55:39.466657 <30>[ 8.857956] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6342 09:55:39.480359 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6343 09:55:39.499590 <30>[ 8.890436] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6344 09:55:39.512910 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6345 09:55:39.532835 <30>[ 8.923597] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6346 09:55:39.546298 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6347 09:55:39.563219 <30>[ 8.954593] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6348 09:55:39.577740 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6349 09:55:39.595886 <30>[ 8.986670] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6350 09:55:39.607908 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6351 09:55:39.627528 <30>[ 9.018697] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6352 09:55:39.641405 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6353 09:55:39.659845 <30>[ 9.050598] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6354 09:55:39.673001 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6355 09:55:39.691583 <30>[ 9.082362] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6356 09:55:39.704095 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6357 09:55:39.751824 <30>[ 9.142764] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6358 09:55:39.764227 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6359 09:55:39.787883 <30>[ 9.178884] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6360 09:55:39.801493 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6361 09:55:39.823698 <30>[ 9.214629] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6362 09:55:39.836358 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6363 09:55:39.862681 <30>[ 9.246873] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6364 09:55:39.911871 <30>[ 9.302961] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6365 09:55:39.925286 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6366 09:55:39.949246 <30>[ 9.339744] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6367 09:55:39.962375 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6368 09:55:39.984371 <30>[ 9.375363] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6369 09:55:40.001023 Startin<6>[ 9.389222] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6370 09:55:40.004553 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6371 09:55:40.043929 <30>[ 9.434684] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6372 09:55:40.054235 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6373 09:55:40.075990 <30>[ 9.467305] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6374 09:55:40.088474 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6375 09:55:40.112146 <30>[ 9.503448] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6376 09:55:40.123541 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6377 09:55:40.179784 <30>[ 9.570460] systemd[1]: Starting systemd-journald.service - Journal Service...
6378 09:55:40.190221 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6379 09:55:40.211563 <30>[ 9.602162] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6380 09:55:40.222141 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6381 09:55:40.248507 <30>[ 9.636088] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6382 09:55:40.255110 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6383 09:55:40.278662 <30>[ 9.669817] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6384 09:55:40.291569 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6385 09:55:40.310898 <30>[ 9.701453] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6386 09:55:40.322775 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
6387 09:55:40.342554 <30>[ 9.733410] systemd[1]: Started systemd-journald.service - Journal Service.
6388 09:55:40.352313 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6389 09:55:40.373000 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
6390 09:55:40.392258 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
6391 09:55:40.412295 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6392 09:55:40.428666 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6393 09:55:40.449171 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6394 09:55:40.468990 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6395 09:55:40.493218 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6396 09:55:40.517860 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6397 09:55:40.537885 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6398 09:55:40.560867 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6399 09:55:40.584527 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6400 09:55:40.610034 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
6401 09:55:40.628235 See 'systemctl status systemd-remount-fs.service' for details.
6402 09:55:40.640414 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6403 09:55:40.667558 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6404 09:55:40.719706 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6405 09:55:40.741455 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6406 09:55:40.755156 <46>[ 10.146077] systemd-journald[201]: Received client request to flush runtime journal.
6407 09:55:40.769256 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6408 09:55:40.793298 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
6409 09:55:40.814745 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6410 09:55:40.842530 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6411 09:55:40.862569 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6412 09:55:40.881556 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6413 09:55:40.900250 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6414 09:55:40.920771 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6415 09:55:40.963774 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6416 09:55:41.002087 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6417 09:55:41.020091 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6418 09:55:41.039322 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6419 09:55:41.095664 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6420 09:55:41.120807 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6421 09:55:41.146971 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6422 09:55:41.195985 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6423 09:55:41.218413 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
6424 09:55:41.236083 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6425 09:55:41.269554 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6426 09:55:41.288770 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6427 09:55:41.315920 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6428 09:55:41.441847 <3>[ 10.835923] mtk-scp 10500000.scp: invalid resource
6429 09:55:41.451836 <6>[ 10.840574] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6430 09:55:41.461725 <6>[ 10.851821] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6431 09:55:41.468334 <6>[ 10.852006] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6432 09:55:41.478306 <3>[ 10.863084] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6433 09:55:41.485003 <3>[ 10.863596] thermal_sys: Failed to find 'trips' node
6434 09:55:41.491332 <3>[ 10.863601] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6435 09:55:41.501285 <3>[ 10.863607] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6436 09:55:41.507919 <4>[ 10.863610] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6437 09:55:41.517509 <4>[ 10.869939] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6438 09:55:41.528768 <3>[ 10.877740] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6439 09:55:41.532446 <6>[ 10.880696] remoteproc remoteproc0: scp is available
6440 09:55:41.543237 <4>[ 10.880825] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6441 09:55:41.550233 <6>[ 10.880833] remoteproc remoteproc0: powering up scp
6442 09:55:41.560448 <4>[ 10.880853] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6443 09:55:41.567955 <3>[ 10.880857] remoteproc remoteproc0: request_firmware failed: -2
6444 09:55:41.582491 <6>[ 10.890803] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6445 09:55:41.592158 <3>[ 10.892274] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6446 09:55:41.603964 <3>[ 10.901942] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6447 09:55:41.614764 <4>[ 10.902079] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6448 09:55:41.620888 <4>[ 10.902200] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6449 09:55:41.630878 <6>[ 10.905624] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6450 09:55:41.637713 <3>[ 10.908292] elan_i2c 2-0015: Error applying setting, reverse things back
6451 09:55:41.644372 <6>[ 10.918759] mc: Linux media interface: v0.10
6452 09:55:41.650926 <3>[ 10.920210] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6453 09:55:41.664333 <3>[ 11.011308] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6454 09:55:41.673668 <3>[ 11.012862] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6455 09:55:41.677252 <6>[ 11.014602] videodev: Linux video capture interface: v2.00
6456 09:55:41.683821 <6>[ 11.020350] cs_system_cfg: CoreSight Configuration manager initialised
6457 09:55:41.695004 <5>[ 11.021410] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6458 09:55:41.701185 <3>[ 11.032432] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6459 09:55:41.711818 <5>[ 11.037260] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6460 09:55:41.718283 <5>[ 11.037763] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6461 09:55:41.728142 <6>[ 11.040165] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6462 09:55:41.735008 <3>[ 11.042299] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6463 09:55:41.744336 <6>[ 11.042934] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6464 09:55:41.754050 <4>[ 11.051146] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6465 09:55:41.762391 <3>[ 11.063264] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6466 09:55:41.771916 <6>[ 11.066389] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6467 09:55:41.778615 <6>[ 11.066515] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6468 09:55:41.785661 <6>[ 11.066593] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6469 09:55:41.791924 <6>[ 11.071884] cfg80211: failed to load regulatory.db
6470 09:55:41.798780 <6>[ 11.072265] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6471 09:55:41.808930 <6>[ 11.072420] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6472 09:55:41.815298 <3>[ 11.077754] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6473 09:55:41.826360 <6>[ 11.078680] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6474 09:55:41.832617 <6>[ 11.078840] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6475 09:55:41.842995 <6>[ 11.078901] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6476 09:55:41.846312 <6>[ 11.109776] Bluetooth: Core ver 2.22
6477 09:55:41.853344 <3>[ 11.110021] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6478 09:55:41.859953 <6>[ 11.118402] NET: Registered PF_BLUETOOTH protocol family
6479 09:55:41.869730 <3>[ 11.142041] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6480 09:55:41.873227 <6>[ 11.144705] Bluetooth: HCI device and connection manager initialized
6481 09:55:41.879762 <6>[ 11.153721] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6482 09:55:41.886593 <6>[ 11.162114] Bluetooth: HCI socket layer initialized
6483 09:55:41.892899 <6>[ 11.171029] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6484 09:55:41.899631 <6>[ 11.178122] Bluetooth: L2CAP socket layer initialized
6485 09:55:41.906794 <6>[ 11.186171] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6486 09:55:41.913100 <6>[ 11.187277] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video0
6487 09:55:41.919975 <6>[ 11.191031] Bluetooth: SCO socket layer initialized
6488 09:55:41.932950 <3>[ 11.191335] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6489 09:55:41.939974 <3>[ 11.192204] debugfs: File 'Playback' in directory 'dapm' already present!
6490 09:55:41.946388 <3>[ 11.192212] debugfs: File 'Capture' in directory 'dapm' already present!
6491 09:55:41.959772 <6>[ 11.193608] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input6
6492 09:55:41.963295 <3>[ 11.199602] thermal_sys: Failed to find 'trips' node
6493 09:55:41.973912 <6>[ 11.199770] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video1 (81,1)
6494 09:55:41.987792 <6>[ 11.200549] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6495 09:55:41.994138 <6>[ 11.200694] usbcore: registered new interface driver uvcvideo
6496 09:55:42.004294 <6>[ 11.218758] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6497 09:55:42.010815 <3>[ 11.225583] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6498 09:55:42.020692 <6>[ 11.233126] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6499 09:55:42.031122 <3>[ 11.240967] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6500 09:55:42.034491 <6>[ 11.245034] Bluetooth: HCI UART driver ver 2.3
6501 09:55:42.047909 <6>[ 11.245138] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6502 09:55:42.054702 <4>[ 11.253310] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6503 09:55:42.058604 <3>[ 11.255914] thermal_sys: Failed to find 'trips' node
6504 09:55:42.064658 <6>[ 11.258876] Bluetooth: HCI UART protocol H4 registered
6505 09:55:42.073078 <3>[ 11.267409] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6506 09:55:42.077035 <6>[ 11.274037] Bluetooth: HCI UART protocol LL registered
6507 09:55:42.087135 <3>[ 11.280421] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6508 09:55:42.094113 <4>[ 11.280424] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6509 09:55:42.101814 <6>[ 11.285580] Bluetooth: HCI UART protocol Three-wire (H5) registered
6510 09:55:42.111601 <6>[ 11.393432] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6511 09:55:42.120118 <6>[ 11.394006] Bluetooth: HCI UART protocol Broadcom registered
6512 09:55:42.134899 <4>[ 11.433722] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6513 09:55:42.140972 <4>[ 11.433722] Fallback method does not support PEC.
6514 09:55:42.149140 <6>[ 11.434755] Bluetooth: HCI UART protocol QCA registered
6515 09:55:42.158899 <6>[ 11.435525] Bluetooth: hci0: setting up ROME/QCA6390
6516 09:55:42.170589 <3>[ 11.448403] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6517 09:55:42.178681 <6>[ 11.453575] Bluetooth: HCI UART protocol Marvell registered
6518 09:55:42.190530 <3>[ 11.469500] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6519 09:55:42.200236 <3>[ 11.469933] power_supply sbs-12-000b: driver failed to report `technology' property: -6
6520 09:55:42.211077 <3>[ 11.475666] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6521 09:55:42.221154 <3>[ 11.495362] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6522 09:55:42.265628 <3>[ 11.657644] Bluetooth: hci0: Frame reassembly failed (-84)
6523 09:55:42.273007 <3>[ 11.659496] power_supply sbs-12-000b: driver failed to report `capacity_level' property: -6
6524 09:55:42.283030 <3>[ 11.666760] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6525 09:55:42.356171 <6>[ 11.744046] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6526 09:55:42.363075 <3>[ 11.749835] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6527 09:55:42.373879 <3>[ 11.755056] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6528 09:55:42.383322 <3>[ 11.773991] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6529 09:55:42.397859 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6530 09:55:42.414717 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6531 09:55:42.443843 <4>[ 11.834897] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6532 09:55:42.463503 <4>[ 11.854866] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6533 09:55:42.484431 Starting [0;1;39msystemd-backlight…ess of backlight:<4>[ 11.873325] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6534 09:55:42.484938 backlight_lcd0...
6535 09:55:42.510708 Startin<4>[ 11.902253] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6536 09:55:42.519288 g [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6537 09:55:42.532856 <6>[ 11.927068] Bluetooth: hci0: QCA Product ID :0x00000008
6538 09:55:42.540055 <6>[ 11.934599] Bluetooth: hci0: QCA SOC Version :0x00000044
6539 09:55:42.546551 <6>[ 11.934606] Bluetooth: hci0: QCA ROM Version :0x00000302
6540 09:55:42.553739 <6>[ 11.934608] Bluetooth: hci0: QCA Patch Version:0x00000111
6541 09:55:42.559904 <6>[ 11.934613] Bluetooth: hci0: QCA controller version 0x00440302
6542 09:55:42.566518 <6>[ 11.934617] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6543 09:55:42.577189 <4>[ 11.934687] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6544 09:55:42.587075 <3>[ 11.934696] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6545 09:55:42.593613 <3>[ 11.934700] Bluetooth: hci0: QCA Failed to download patch (-2)
6546 09:55:42.603243 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6547 09:55:42.635162 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6548 09:55:42.657543 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6549 09:55:42.671138 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6550 09:55:42.694852 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6551 09:55:42.711630 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6552 09:55:42.737686 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6553 09:55:42.756398 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6554 09:55:42.772326 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6555 09:55:42.789596 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6556 09:55:42.805285 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6557 09:55:42.821719 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6558 09:55:42.838199 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6559 09:55:42.888067 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6560 09:55:42.917056 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6561 09:55:42.941130 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6562 09:55:42.961929 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6563 09:55:42.990293 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6564 09:55:43.042825 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6565 09:55:43.062476 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6566 09:55:43.080316 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6567 09:55:43.100262 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6568 09:55:43.121587 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6569 09:55:43.142075 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6570 09:55:43.163440 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6571 09:55:43.181096 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6572 09:55:43.222498 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6573 09:55:43.255865 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6574 09:55:43.298753
6575 09:55:43.302131 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6576 09:55:43.302713
6577 09:55:43.305036 debian-bookworm-arm64 login: root (automatic login)
6578 09:55:43.305499
6579 09:55:43.322998 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
6580 09:55:43.323600
6581 09:55:43.329286 The programs included with the Debian GNU/Linux system are free software;
6582 09:55:43.336116 the exact distribution terms for each program are described in the
6583 09:55:43.339138 individual files in /usr/share/doc/*/copyright.
6584 09:55:43.339732
6585 09:55:43.346235 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6586 09:55:43.349245 permitted by applicable law.
6587 09:55:43.350787 Matched prompt #10: / #
6589 09:55:43.352067 Setting prompt string to ['/ #']
6590 09:55:43.352658 end: 2.2.5.1 login-action (duration 00:00:13) [common]
6592 09:55:43.353910 end: 2.2.5 auto-login-action (duration 00:00:13) [common]
6593 09:55:43.354501 start: 2.2.6 expect-shell-connection (timeout 00:03:33) [common]
6594 09:55:43.354934 Setting prompt string to ['/ #']
6595 09:55:43.355361 Forcing a shell prompt, looking for ['/ #']
6597 09:55:43.406686 / #
6598 09:55:43.407359 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6599 09:55:43.407935 Waiting using forced prompt support (timeout 00:02:30)
6600 09:55:43.413545
6601 09:55:43.414515 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6602 09:55:43.415128 start: 2.2.7 export-device-env (timeout 00:03:32) [common]
6603 09:55:43.415962 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6604 09:55:43.416525 end: 2.2 depthcharge-retry (duration 00:01:28) [common]
6605 09:55:43.417103 end: 2 depthcharge-action (duration 00:01:28) [common]
6606 09:55:43.417685 start: 3 lava-test-retry (timeout 00:08:10) [common]
6607 09:55:43.418243 start: 3.1 lava-test-shell (timeout 00:08:10) [common]
6608 09:55:43.418719 Using namespace: common
6610 09:55:43.520365 / # #
6611 09:55:43.521036 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6612 09:55:43.527531 #
6613 09:55:43.528439 Using /lava-14407602
6615 09:55:43.629847 / # export SHELL=/bin/sh
6616 09:55:43.636027 export SHELL=/bin/sh
6618 09:55:43.737311 / # . /lava-14407602/environment
6619 09:55:43.744094 . /lava-14407602/environment
6621 09:55:43.846160 / # /lava-14407602/bin/lava-test-runner /lava-14407602/0
6622 09:55:43.847012 Test shell timeout: 10s (minimum of the action and connection timeout)
6623 09:55:43.852467 /lava-14407602/bin/lava-test-runner /lava-14407602/0
6624 09:55:43.878766 + export TESTRUN_ID=0_v4l2-compliance-uvc
6625 09:55:43.882244 + cd /lava-14407602/0/tests/0_v4l2-compliance-uvc
6626 09:55:43.882825 + cat uuid
6627 09:55:43.884668 + UUID=14407602_1.5.2.3.1
6628 09:55:43.885096 + set +x
6629 09:55:43.892350 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14407602_1.5.2.3.1>
6630 09:55:43.893460 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14407602_1.5.2.3.1
6631 09:55:43.894093 Starting test lava.0_v4l2-compliance-uvc (14407602_1.5.2.3.1)
6632 09:55:43.894792 Skipping test definition patterns.
6633 09:55:43.895677 + /usr/bin/v4l2-parser.sh -d uvcvideo
6634 09:55:43.901725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
6635 09:55:43.902184 device: /dev/video2
6636 09:55:43.902808 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
6638 09:55:50.851251 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
6639 09:55:50.864280 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
6640 09:55:50.875756
6641 09:55:50.892680 Compliance test for uvcvideo device /dev/video2:
6642 09:55:50.905289
6643 09:55:50.919159 Driver Info:
6644 09:55:50.934734 Driver name : uvcvideo
6645 09:55:50.953222 Card type : HD WebCam: HD WebCam
6646 09:55:50.967318 Bus info : usb-11200000.usb-1.3
6647 09:55:50.978751 Driver version : 6.1.92
6648 09:55:50.992930 Capabilities : 0x84a00001
6649 09:55:51.010740 Metadata Capture
6650 09:55:51.024355 Streaming
6651 09:55:51.040124 Extended Pix Format
6652 09:55:51.053131 Device Capabilities
6653 09:55:51.069984 Device Caps : 0x04200001
6654 09:55:51.088370 Streaming
6655 09:55:51.103849 Extended Pix Format
6656 09:55:51.119975 Media Driver Info:
6657 09:55:51.135544 Driver name : uvcvideo
6658 09:55:51.152664 Model : HD WebCam: HD WebCam
6659 09:55:51.165139 Serial :
6660 09:55:51.184415 Bus info : usb-11200000.usb-1.3
6661 09:55:51.195076 Media version : 6.1.92
6662 09:55:51.211670 Hardware revision: 0x00003269 (12905)
6663 09:55:51.222222 Driver version : 6.1.92
6664 09:55:51.235715 Interface Info:
6665 09:55:51.253062 <LAVA_SIGNAL_TESTSET START Interface-Info>
6666 09:55:51.253636 ID : 0x03000002
6667 09:55:51.254290 Received signal: <TESTSET> START Interface-Info
6668 09:55:51.254677 Starting test_set Interface-Info
6669 09:55:51.268229 Type : V4L Video
6670 09:55:51.281202 Entity Info:
6671 09:55:51.289430 <LAVA_SIGNAL_TESTSET STOP>
6672 09:55:51.290157 Received signal: <TESTSET> STOP
6673 09:55:51.290562 Closing test_set Interface-Info
6674 09:55:51.299695 <LAVA_SIGNAL_TESTSET START Entity-Info>
6675 09:55:51.300498 Received signal: <TESTSET> START Entity-Info
6676 09:55:51.300893 Starting test_set Entity-Info
6677 09:55:51.302621 ID : 0x00000001 (1)
6678 09:55:51.320549 Name : HD WebCam: HD WebCam
6679 09:55:51.329923 Function : V4L2 I/O
6680 09:55:51.345682 Flags : default
6681 09:55:51.360716 Pad 0x01000007 : 0: Sink
6682 09:55:51.384343 Link 0x02000013: from remote pad 0x100000a of entity 'Extension 4' (Video Pixel Formatter): Data, Enabled, Immutable
6683 09:55:51.389779
6684 09:55:51.406119 Required ioctls:
6685 09:55:51.414420 <LAVA_SIGNAL_TESTSET STOP>
6686 09:55:51.415467 Received signal: <TESTSET> STOP
6687 09:55:51.416055 Closing test_set Entity-Info
6688 09:55:51.425316 <LAVA_SIGNAL_TESTSET START Required-ioctls>
6689 09:55:51.425990 Received signal: <TESTSET> START Required-ioctls
6690 09:55:51.426355 Starting test_set Required-ioctls
6691 09:55:51.428117 test MC information (see 'Media Driver Info' above): OK
6692 09:55:51.459635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
6693 09:55:51.460476 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
6695 09:55:51.462706 test VIDIOC_QUERYCAP: OK
6696 09:55:51.487713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
6697 09:55:51.488542 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
6699 09:55:51.490762 test invalid ioctls: OK
6700 09:55:51.518709 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
6701 09:55:51.519265
6702 09:55:51.519937 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
6704 09:55:51.533301 Allow for multiple opens:
6705 09:55:51.544203 <LAVA_SIGNAL_TESTSET STOP>
6706 09:55:51.545017 Received signal: <TESTSET> STOP
6707 09:55:51.545398 Closing test_set Required-ioctls
6708 09:55:51.553425 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
6709 09:55:51.554241 Received signal: <TESTSET> START Allow-for-multiple-opens
6710 09:55:51.554631 Starting test_set Allow-for-multiple-opens
6711 09:55:51.556416 test second /dev/video2 open: OK
6712 09:55:51.583456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
6713 09:55:51.584291 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
6715 09:55:51.586892 test VIDIOC_QUERYCAP: OK
6716 09:55:51.614075 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
6717 09:55:51.614800 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
6719 09:55:51.617532 test VIDIOC_G/S_PRIORITY: OK
6720 09:55:51.645622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
6721 09:55:51.646393 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
6723 09:55:51.648810 test for unlimited opens: OK
6724 09:55:51.675655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
6725 09:55:51.676150
6726 09:55:51.676729 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
6728 09:55:51.689114 Debug ioctls:
6729 09:55:51.697518 <LAVA_SIGNAL_TESTSET STOP>
6730 09:55:51.698356 Received signal: <TESTSET> STOP
6731 09:55:51.698705 Closing test_set Allow-for-multiple-opens
6732 09:55:51.708615 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
6733 09:55:51.709507 Received signal: <TESTSET> START Debug-ioctls
6734 09:55:51.709861 Starting test_set Debug-ioctls
6735 09:55:51.712081 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
6736 09:55:51.740158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
6737 09:55:51.741034 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
6739 09:55:51.746346 test VIDIOC_LOG_STATUS: OK (Not Supported)
6740 09:55:51.771338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
6741 09:55:51.771876
6742 09:55:51.772461 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
6744 09:55:51.789158 Input ioctls:
6745 09:55:51.799588 <LAVA_SIGNAL_TESTSET STOP>
6746 09:55:51.800556 Received signal: <TESTSET> STOP
6747 09:55:51.800992 Closing test_set Debug-ioctls
6748 09:55:51.810371 <LAVA_SIGNAL_TESTSET START Input-ioctls>
6749 09:55:51.811043 Received signal: <TESTSET> START Input-ioctls
6750 09:55:51.811393 Starting test_set Input-ioctls
6751 09:55:51.814193 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
6752 09:55:51.850403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
6753 09:55:51.851236 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
6755 09:55:51.853515 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
6756 09:55:51.876194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
6757 09:55:51.877019 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
6759 09:55:51.882942 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
6760 09:55:51.900927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
6761 09:55:51.901740 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
6763 09:55:51.907531 test VIDIOC_ENUMAUDIO: OK (Not Supported)
6764 09:55:51.929311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
6765 09:55:51.930143 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
6767 09:55:51.932165 test VIDIOC_G/S/ENUMINPUT: OK
6768 09:55:51.960195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
6769 09:55:51.961009 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
6771 09:55:51.963546 test VIDIOC_G/S_AUDIO: OK (Not Supported)
6772 09:55:51.989675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
6773 09:55:51.990444 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
6775 09:55:51.992831 Inputs: 1 Audio Inputs: 0 Tuners: 0
6776 09:55:52.003753
6777 09:55:52.024328 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
6778 09:55:52.050482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
6779 09:55:52.051156 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
6781 09:55:52.056778 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
6782 09:55:52.082291 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
6783 09:55:52.083053 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
6785 09:55:52.089110 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
6786 09:55:52.110774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
6787 09:55:52.111481 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
6789 09:55:52.117103 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
6790 09:55:52.139110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
6791 09:55:52.140185 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
6793 09:55:52.145460 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
6794 09:55:52.170364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
6795 09:55:52.170633 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
6797 09:55:52.175133
6798 09:55:52.198240 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
6799 09:55:52.225141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
6800 09:55:52.225635 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
6802 09:55:52.231362 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
6803 09:55:52.263232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
6804 09:55:52.263948 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
6806 09:55:52.266162 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
6807 09:55:52.293557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
6808 09:55:52.294372 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
6810 09:55:52.296728 test VIDIOC_G/S_EDID: OK (Not Supported)
6811 09:55:52.324174 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
6812 09:55:52.324730
6813 09:55:52.325392 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
6815 09:55:52.339334 Control ioctls (Input 0):
6816 09:55:52.349759 <LAVA_SIGNAL_TESTSET STOP>
6817 09:55:52.350516 Received signal: <TESTSET> STOP
6818 09:55:52.350962 Closing test_set Input-ioctls
6819 09:55:52.360832 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
6820 09:55:52.361556 Received signal: <TESTSET> START Control-ioctls-Input-0
6821 09:55:52.361941 Starting test_set Control-ioctls-Input-0
6822 09:55:52.364152 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
6823 09:55:52.392022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
6824 09:55:52.392476 test VIDIOC_QUERYCTRL: OK
6825 09:55:52.393059 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
6827 09:55:52.417567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
6828 09:55:52.418242 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
6830 09:55:52.421317 test VIDIOC_G/S_CTRL: OK
6831 09:55:52.446451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
6832 09:55:52.447214 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
6834 09:55:52.449872 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
6835 09:55:52.476135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
6836 09:55:52.476891 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
6838 09:55:52.482486 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
6839 09:55:52.509638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
6840 09:55:52.510411 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
6842 09:55:52.512792 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
6843 09:55:52.537148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
6844 09:55:52.537958 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
6846 09:55:52.543283 Standard Controls: 15 Private Controls: 0
6847 09:55:52.551714
6848 09:55:52.568041 Format ioctls (Input 0):
6849 09:55:52.576298 <LAVA_SIGNAL_TESTSET STOP>
6850 09:55:52.576976 Received signal: <TESTSET> STOP
6851 09:55:52.577336 Closing test_set Control-ioctls-Input-0
6852 09:55:52.586799 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
6853 09:55:52.587497 Received signal: <TESTSET> START Format-ioctls-Input-0
6854 09:55:52.587851 Starting test_set Format-ioctls-Input-0
6855 09:55:52.590438 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
6856 09:55:52.621019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
6857 09:55:52.621692 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
6859 09:55:52.624021 test VIDIOC_G/S_PARM: OK
6860 09:55:52.650008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
6861 09:55:52.650676 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
6863 09:55:52.653439 test VIDIOC_G_FBUF: OK (Not Supported)
6864 09:55:52.678738 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
6865 09:55:52.679433 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
6867 09:55:52.682060 test VIDIOC_G_FMT: OK
6868 09:55:52.707989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
6869 09:55:52.708659 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
6871 09:55:52.711198 test VIDIOC_TRY_FMT: OK
6872 09:55:52.741204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
6873 09:55:52.741957 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
6875 09:55:52.747825 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
6876 09:55:52.754203 test VIDIOC_S_FMT: OK
6877 09:55:52.786532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
6878 09:55:52.787292 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
6880 09:55:52.789704 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
6881 09:55:52.824537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
6882 09:55:52.825294 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
6884 09:55:52.827771 test Cropping: OK (Not Supported)
6885 09:55:52.853711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
6886 09:55:52.854470 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
6888 09:55:52.857030 test Composing: OK (Not Supported)
6889 09:55:52.886245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
6890 09:55:52.886977 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
6892 09:55:52.889043 test Scaling: OK (Not Supported)
6893 09:55:52.918214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
6894 09:55:52.918714
6895 09:55:52.919299 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
6897 09:55:52.932652 Codec ioctls (Input 0):
6898 09:55:52.941618 <LAVA_SIGNAL_TESTSET STOP>
6899 09:55:52.942280 Received signal: <TESTSET> STOP
6900 09:55:52.942623 Closing test_set Format-ioctls-Input-0
6901 09:55:52.952277 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
6902 09:55:52.952949 Received signal: <TESTSET> START Codec-ioctls-Input-0
6903 09:55:52.953311 Starting test_set Codec-ioctls-Input-0
6904 09:55:52.955210 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
6905 09:55:52.982467 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
6906 09:55:52.983151 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
6908 09:55:52.988250 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
6909 09:55:53.010822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
6910 09:55:53.011539 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
6912 09:55:53.017339 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
6913 09:55:53.042811 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
6914 09:55:53.043225
6915 09:55:53.043835 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
6917 09:55:53.058283 Buffer ioctls (Input 0):
6918 09:55:53.066307 <LAVA_SIGNAL_TESTSET STOP>
6919 09:55:53.066980 Received signal: <TESTSET> STOP
6920 09:55:53.067320 Closing test_set Codec-ioctls-Input-0
6921 09:55:53.077995 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
6922 09:55:53.078663 Received signal: <TESTSET> START Buffer-ioctls-Input-0
6923 09:55:53.079011 Starting test_set Buffer-ioctls-Input-0
6924 09:55:53.081472 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
6925 09:55:53.113459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
6926 09:55:53.114141 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
6928 09:55:53.116828 test CREATE_BUFS maximum buffers: OK
6929 09:55:53.140986 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
6931 09:55:53.143983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
6932 09:55:53.144463 test VIDIOC_EXPBUF: OK
6933 09:55:53.169853 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
6934 09:55:53.170740 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
6936 09:55:53.173224 test Requests: OK (Not Supported)
6937 09:55:53.203140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
6938 09:55:53.203730
6939 09:55:53.204611 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
6941 09:55:53.219366 Test input 0:
6942 09:55:53.231680
6943 09:55:53.245182 Streaming ioctls:
6944 09:55:53.256021 <LAVA_SIGNAL_TESTSET STOP>
6945 09:55:53.256688 Received signal: <TESTSET> STOP
6946 09:55:53.257029 Closing test_set Buffer-ioctls-Input-0
6947 09:55:53.268110 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
6948 09:55:53.268781 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
6949 09:55:53.269133 Starting test_set Streaming-ioctls_Test-input-0
6950 09:55:53.271364 test read/write: OK (Not Supported)
6951 09:55:53.297404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
6952 09:55:53.298070 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
6954 09:55:53.300413 test blocking wait: OK
6955 09:55:53.330791 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
6956 09:55:53.331534 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
6958 09:55:53.337648 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
6959 09:55:53.344316 test MMAP (no poll): FAIL
6960 09:55:53.374157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
6961 09:55:53.374921 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
6963 09:55:53.380316 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
6964 09:55:53.389066 test MMAP (select): FAIL
6965 09:55:53.420349 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
6966 09:55:53.421042 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
6968 09:55:53.426996 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
6969 09:55:53.435673 test MMAP (epoll): FAIL
6970 09:55:53.464080 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
6971 09:55:53.464582
6972 09:55:53.465165 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
6974 09:55:53.696299
6975 09:55:53.707512 test USERPTR (no poll): OK
6976 09:55:53.736071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
6977 09:55:53.736489
6978 09:55:53.737076 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
6980 09:55:53.967233
6981 09:55:53.978615 test USERPTR (select): OK
6982 09:55:54.008859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
6983 09:55:54.009543 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
6985 09:55:54.015182 test DMABUF: Cannot test, specify --expbuf-device
6986 09:55:54.023288
6987 09:55:54.043607 Total for uvcvideo device /dev/video2: 54, Succeeded: 51, Failed: 3, Warnings: 1
6988 09:55:54.049434 <LAVA_TEST_RUNNER EXIT>
6989 09:55:54.050110 ok: lava_test_shell seems to have completed
6990 09:55:54.050474 Marking unfinished test run as failed
6992 09:55:54.055215 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
6993 09:55:54.055886 end: 3.1 lava-test-shell (duration 00:00:11) [common]
6994 09:55:54.056322 end: 3 lava-test-retry (duration 00:00:11) [common]
6995 09:55:54.056757 start: 4 finalize (timeout 00:07:59) [common]
6996 09:55:54.057199 start: 4.1 power-off (timeout 00:00:30) [common]
6997 09:55:54.057970 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0', '--port=1', '--command=off']
6998 09:55:55.587137 >> Command sent successfully.
6999 09:55:55.598427 Returned 0 in 1 seconds
7000 09:55:55.699698 end: 4.1 power-off (duration 00:00:02) [common]
7002 09:55:55.701076 start: 4.2 read-feedback (timeout 00:07:58) [common]
7003 09:55:55.702278 Listened to connection for namespace 'common' for up to 1s
7004 09:55:56.702268 Finalising connection for namespace 'common'
7005 09:55:56.702953 Disconnecting from shell: Finalise
7006 09:55:56.703363 / #
7007 09:55:56.804429 end: 4.2 read-feedback (duration 00:00:01) [common]
7008 09:55:56.805166 end: 4 finalize (duration 00:00:03) [common]
7009 09:55:56.805789 Cleaning after the job
7010 09:55:56.806330 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/ramdisk
7011 09:55:56.826191 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/kernel
7012 09:55:56.856707 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/dtb
7013 09:55:56.857006 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407602/tftp-deploy-bxltqb1m/modules
7014 09:55:56.864363 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407602
7015 09:55:56.932252 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407602
7016 09:55:56.932443 Job finished correctly