Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 09:28:34.438250 lava-dispatcher, installed at version: 2024.03
2 09:28:34.438501 start: 0 validate
3 09:28:34.438635 Start time: 2024-06-18 09:28:34.438628+00:00 (UTC)
4 09:28:34.438811 Using caching service: 'http://localhost/cache/?uri=%s'
5 09:28:34.439016 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-v4l2%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 09:28:34.706617 Using caching service: 'http://localhost/cache/?uri=%s'
7 09:28:34.706779 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 09:28:34.970282 Using caching service: 'http://localhost/cache/?uri=%s'
9 09:28:34.970493 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 09:28:35.229265 Using caching service: 'http://localhost/cache/?uri=%s'
11 09:28:35.229407 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22-32-g866364c7d80d0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 09:28:35.488359 validate duration: 1.05
14 09:28:35.488611 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 09:28:35.488713 start: 1.1 download-retry (timeout 00:10:00) [common]
16 09:28:35.488797 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 09:28:35.488956 Not decompressing ramdisk as can be used compressed.
18 09:28:35.489047 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-v4l2/20240313.0/arm64/rootfs.cpio.gz
19 09:28:35.489119 saving as /var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/ramdisk/rootfs.cpio.gz
20 09:28:35.489192 total size: 28105535 (26 MB)
21 09:28:35.490204 progress 0 % (0 MB)
22 09:28:35.497359 progress 5 % (1 MB)
23 09:28:35.504457 progress 10 % (2 MB)
24 09:28:35.511678 progress 15 % (4 MB)
25 09:28:35.518717 progress 20 % (5 MB)
26 09:28:35.525716 progress 25 % (6 MB)
27 09:28:35.532761 progress 30 % (8 MB)
28 09:28:35.539839 progress 35 % (9 MB)
29 09:28:35.546905 progress 40 % (10 MB)
30 09:28:35.553804 progress 45 % (12 MB)
31 09:28:35.560853 progress 50 % (13 MB)
32 09:28:35.567806 progress 55 % (14 MB)
33 09:28:35.574804 progress 60 % (16 MB)
34 09:28:35.581783 progress 65 % (17 MB)
35 09:28:35.588746 progress 70 % (18 MB)
36 09:28:35.595805 progress 75 % (20 MB)
37 09:28:35.603133 progress 80 % (21 MB)
38 09:28:35.610142 progress 85 % (22 MB)
39 09:28:35.616890 progress 90 % (24 MB)
40 09:28:35.623869 progress 95 % (25 MB)
41 09:28:35.630835 progress 100 % (26 MB)
42 09:28:35.631058 26 MB downloaded in 0.14 s (188.95 MB/s)
43 09:28:35.631215 end: 1.1.1 http-download (duration 00:00:00) [common]
45 09:28:35.631438 end: 1.1 download-retry (duration 00:00:00) [common]
46 09:28:35.631518 start: 1.2 download-retry (timeout 00:10:00) [common]
47 09:28:35.631630 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 09:28:35.631841 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 09:28:35.631908 saving as /var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/kernel/Image
50 09:28:35.631981 total size: 54813184 (52 MB)
51 09:28:35.632052 No compression specified
52 09:28:35.633307 progress 0 % (0 MB)
53 09:28:35.646901 progress 5 % (2 MB)
54 09:28:35.660747 progress 10 % (5 MB)
55 09:28:35.674138 progress 15 % (7 MB)
56 09:28:35.688088 progress 20 % (10 MB)
57 09:28:35.702037 progress 25 % (13 MB)
58 09:28:35.715623 progress 30 % (15 MB)
59 09:28:35.729328 progress 35 % (18 MB)
60 09:28:35.743131 progress 40 % (20 MB)
61 09:28:35.756713 progress 45 % (23 MB)
62 09:28:35.770290 progress 50 % (26 MB)
63 09:28:35.784290 progress 55 % (28 MB)
64 09:28:35.798177 progress 60 % (31 MB)
65 09:28:35.811893 progress 65 % (34 MB)
66 09:28:35.825630 progress 70 % (36 MB)
67 09:28:35.839234 progress 75 % (39 MB)
68 09:28:35.853030 progress 80 % (41 MB)
69 09:28:35.866531 progress 85 % (44 MB)
70 09:28:35.880278 progress 90 % (47 MB)
71 09:28:35.893926 progress 95 % (49 MB)
72 09:28:35.907349 progress 100 % (52 MB)
73 09:28:35.907646 52 MB downloaded in 0.28 s (189.63 MB/s)
74 09:28:35.907820 end: 1.2.1 http-download (duration 00:00:00) [common]
76 09:28:35.908056 end: 1.2 download-retry (duration 00:00:00) [common]
77 09:28:35.908153 start: 1.3 download-retry (timeout 00:10:00) [common]
78 09:28:35.908244 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 09:28:35.908389 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 09:28:35.908456 saving as /var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/dtb/mt8192-asurada-spherion-r0.dtb
81 09:28:35.908545 total size: 47258 (0 MB)
82 09:28:35.908635 No compression specified
83 09:28:35.910167 progress 69 % (0 MB)
84 09:28:35.910452 progress 100 % (0 MB)
85 09:28:35.910630 0 MB downloaded in 0.00 s (21.65 MB/s)
86 09:28:35.910758 end: 1.3.1 http-download (duration 00:00:00) [common]
88 09:28:35.910986 end: 1.3 download-retry (duration 00:00:00) [common]
89 09:28:35.911076 start: 1.4 download-retry (timeout 00:10:00) [common]
90 09:28:35.911165 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 09:28:35.911285 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22-32-g866364c7d80d0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 09:28:35.911375 saving as /var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/modules/modules.tar
93 09:28:35.911463 total size: 8619356 (8 MB)
94 09:28:35.911552 Using unxz to decompress xz
95 09:28:35.913293 progress 0 % (0 MB)
96 09:28:35.932234 progress 5 % (0 MB)
97 09:28:35.955749 progress 10 % (0 MB)
98 09:28:35.979801 progress 15 % (1 MB)
99 09:28:36.004508 progress 20 % (1 MB)
100 09:28:36.028921 progress 25 % (2 MB)
101 09:28:36.052734 progress 30 % (2 MB)
102 09:28:36.077283 progress 35 % (2 MB)
103 09:28:36.101743 progress 40 % (3 MB)
104 09:28:36.126884 progress 45 % (3 MB)
105 09:28:36.150308 progress 50 % (4 MB)
106 09:28:36.174067 progress 55 % (4 MB)
107 09:28:36.197701 progress 60 % (4 MB)
108 09:28:36.220672 progress 65 % (5 MB)
109 09:28:36.247809 progress 70 % (5 MB)
110 09:28:36.272133 progress 75 % (6 MB)
111 09:28:36.295264 progress 80 % (6 MB)
112 09:28:36.317931 progress 85 % (7 MB)
113 09:28:36.340673 progress 90 % (7 MB)
114 09:28:36.366868 progress 95 % (7 MB)
115 09:28:36.394893 progress 100 % (8 MB)
116 09:28:36.399400 8 MB downloaded in 0.49 s (16.85 MB/s)
117 09:28:36.399565 end: 1.4.1 http-download (duration 00:00:00) [common]
119 09:28:36.399779 end: 1.4 download-retry (duration 00:00:00) [common]
120 09:28:36.399863 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 09:28:36.399941 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 09:28:36.400010 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 09:28:36.400081 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 09:28:36.400244 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b
125 09:28:36.400371 makedir: /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin
126 09:28:36.400469 makedir: /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/tests
127 09:28:36.400559 makedir: /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/results
128 09:28:36.400643 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-add-keys
129 09:28:36.400772 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-add-sources
130 09:28:36.400890 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-background-process-start
131 09:28:36.401006 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-background-process-stop
132 09:28:36.401128 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-common-functions
133 09:28:36.401242 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-echo-ipv4
134 09:28:36.401356 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-install-packages
135 09:28:36.401467 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-installed-packages
136 09:28:36.401579 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-os-build
137 09:28:36.401689 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-probe-channel
138 09:28:36.401799 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-probe-ip
139 09:28:36.401910 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-target-ip
140 09:28:36.402065 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-target-mac
141 09:28:36.402175 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-target-storage
142 09:28:36.402289 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-test-case
143 09:28:36.402404 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-test-event
144 09:28:36.402514 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-test-feedback
145 09:28:36.402624 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-test-raise
146 09:28:36.402738 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-test-reference
147 09:28:36.402847 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-test-runner
148 09:28:36.402958 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-test-set
149 09:28:36.403069 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-test-shell
150 09:28:36.403181 Updating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-install-packages (oe)
151 09:28:36.403316 Updating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/bin/lava-installed-packages (oe)
152 09:28:36.403431 Creating /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/environment
153 09:28:36.403520 LAVA metadata
154 09:28:36.403586 - LAVA_JOB_ID=14407667
155 09:28:36.403642 - LAVA_DISPATCHER_IP=192.168.201.1
156 09:28:36.403731 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 09:28:36.403788 skipped lava-vland-overlay
158 09:28:36.403854 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 09:28:36.403925 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 09:28:36.403982 skipped lava-multinode-overlay
161 09:28:36.404048 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 09:28:36.404118 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 09:28:36.404180 Loading test definitions
164 09:28:36.404254 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 09:28:36.404314 Using /lava-14407667 at stage 0
166 09:28:36.404617 uuid=14407667_1.5.2.3.1 testdef=None
167 09:28:36.404699 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 09:28:36.404775 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 09:28:36.405213 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 09:28:36.405412 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 09:28:36.405967 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 09:28:36.406220 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 09:28:36.406757 runner path: /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/0/tests/0_v4l2-compliance-uvc test_uuid 14407667_1.5.2.3.1
176 09:28:36.406902 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 09:28:36.407100 Creating lava-test-runner.conf files
179 09:28:36.407156 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14407667/lava-overlay-58i5q69b/lava-14407667/0 for stage 0
180 09:28:36.407236 - 0_v4l2-compliance-uvc
181 09:28:36.407326 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 09:28:36.407406 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 09:28:36.413357 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 09:28:36.413455 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 09:28:36.413535 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 09:28:36.413611 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 09:28:36.413687 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 09:28:37.276125 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 09:28:37.276277 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 09:28:37.276357 extracting modules file /var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14407667/extract-overlay-ramdisk-8vxsg204/ramdisk
191 09:28:37.499168 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 09:28:37.499313 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 09:28:37.499398 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407667/compress-overlay-cobkdnbl/overlay-1.5.2.4.tar.gz to ramdisk
194 09:28:37.499459 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14407667/compress-overlay-cobkdnbl/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14407667/extract-overlay-ramdisk-8vxsg204/ramdisk
195 09:28:37.505729 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 09:28:37.505824 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 09:28:37.505904 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 09:28:37.506032 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 09:28:37.506122 Building ramdisk /var/lib/lava/dispatcher/tmp/14407667/extract-overlay-ramdisk-8vxsg204/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14407667/extract-overlay-ramdisk-8vxsg204/ramdisk
200 09:28:38.232078 >> 276012 blocks
201 09:28:42.407015 rename /var/lib/lava/dispatcher/tmp/14407667/extract-overlay-ramdisk-8vxsg204/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/ramdisk/ramdisk.cpio.gz
202 09:28:42.407172 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 09:28:42.407260 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 09:28:42.407340 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 09:28:42.407418 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/kernel/Image']
206 09:28:55.789995 Returned 0 in 13 seconds
207 09:28:55.890556 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/kernel/image.itb
208 09:28:56.700391 output: FIT description: Kernel Image image with one or more FDT blobs
209 09:28:56.700531 output: Created: Tue Jun 18 10:28:56 2024
210 09:28:56.700595 output: Image 0 (kernel-1)
211 09:28:56.700651 output: Description:
212 09:28:56.700707 output: Created: Tue Jun 18 10:28:56 2024
213 09:28:56.700761 output: Type: Kernel Image
214 09:28:56.700814 output: Compression: lzma compressed
215 09:28:56.700867 output: Data Size: 13126726 Bytes = 12819.07 KiB = 12.52 MiB
216 09:28:56.700918 output: Architecture: AArch64
217 09:28:56.700986 output: OS: Linux
218 09:28:56.701038 output: Load Address: 0x00000000
219 09:28:56.701087 output: Entry Point: 0x00000000
220 09:28:56.701139 output: Hash algo: crc32
221 09:28:56.701190 output: Hash value: 4137a6e7
222 09:28:56.701237 output: Image 1 (fdt-1)
223 09:28:56.701288 output: Description: mt8192-asurada-spherion-r0
224 09:28:56.701340 output: Created: Tue Jun 18 10:28:56 2024
225 09:28:56.701393 output: Type: Flat Device Tree
226 09:28:56.701451 output: Compression: uncompressed
227 09:28:56.701516 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 09:28:56.701570 output: Architecture: AArch64
229 09:28:56.701625 output: Hash algo: crc32
230 09:28:56.701678 output: Hash value: 0f8e4d2e
231 09:28:56.701733 output: Image 2 (ramdisk-1)
232 09:28:56.701785 output: Description: unavailable
233 09:28:56.701834 output: Created: Tue Jun 18 10:28:56 2024
234 09:28:56.701882 output: Type: RAMDisk Image
235 09:28:56.701929 output: Compression: uncompressed
236 09:28:56.701991 output: Data Size: 41214930 Bytes = 40248.96 KiB = 39.31 MiB
237 09:28:56.702082 output: Architecture: AArch64
238 09:28:56.702133 output: OS: Linux
239 09:28:56.702188 output: Load Address: unavailable
240 09:28:56.702236 output: Entry Point: unavailable
241 09:28:56.702284 output: Hash algo: crc32
242 09:28:56.702331 output: Hash value: 61dca841
243 09:28:56.702379 output: Default Configuration: 'conf-1'
244 09:28:56.702426 output: Configuration 0 (conf-1)
245 09:28:56.702476 output: Description: mt8192-asurada-spherion-r0
246 09:28:56.702535 output: Kernel: kernel-1
247 09:28:56.702584 output: Init Ramdisk: ramdisk-1
248 09:28:56.702632 output: FDT: fdt-1
249 09:28:56.702680 output: Loadables: kernel-1
250 09:28:56.702727 output:
251 09:28:56.702859 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 09:28:56.702942 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 09:28:56.703040 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 09:28:56.703127 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 09:28:56.703194 No LXC device requested
256 09:28:56.703265 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 09:28:56.703341 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 09:28:56.703409 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 09:28:56.703467 Checking files for TFTP limit of 4294967296 bytes.
260 09:28:56.703930 end: 1 tftp-deploy (duration 00:00:21) [common]
261 09:28:56.704040 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 09:28:56.704134 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 09:28:56.704341 substitutions:
264 09:28:56.704401 - {DTB}: 14407667/tftp-deploy-x7pvf940/dtb/mt8192-asurada-spherion-r0.dtb
265 09:28:56.704465 - {INITRD}: 14407667/tftp-deploy-x7pvf940/ramdisk/ramdisk.cpio.gz
266 09:28:56.704540 - {KERNEL}: 14407667/tftp-deploy-x7pvf940/kernel/Image
267 09:28:56.704597 - {LAVA_MAC}: None
268 09:28:56.704651 - {PRESEED_CONFIG}: None
269 09:28:56.704705 - {PRESEED_LOCAL}: None
270 09:28:56.704759 - {RAMDISK}: 14407667/tftp-deploy-x7pvf940/ramdisk/ramdisk.cpio.gz
271 09:28:56.704817 - {ROOT_PART}: None
272 09:28:56.704870 - {ROOT}: None
273 09:28:56.704922 - {SERVER_IP}: 192.168.201.1
274 09:28:56.704972 - {TEE}: None
275 09:28:56.705033 Parsed boot commands:
276 09:28:56.705084 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 09:28:56.705228 Parsed boot commands: tftpboot 192.168.201.1 14407667/tftp-deploy-x7pvf940/kernel/image.itb 14407667/tftp-deploy-x7pvf940/kernel/cmdline
278 09:28:56.705319 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 09:28:56.705398 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 09:28:56.705476 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 09:28:56.705565 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 09:28:56.705627 Not connected, no need to disconnect.
283 09:28:56.705695 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 09:28:56.705765 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 09:28:56.705822 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 09:28:56.709012 Setting prompt string to ['lava-test: # ']
287 09:28:56.709336 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 09:28:56.709438 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 09:28:56.709531 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 09:28:56.709614 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 09:28:56.709827 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 09:29:03.348555 >> Command sent successfully.
293 09:29:03.352324 Returned 0 in 6 seconds
294 09:29:03.452637 end: 2.2.2.1 pdu-reboot (duration 00:00:07) [common]
296 09:29:03.452919 end: 2.2.2 reset-device (duration 00:00:07) [common]
297 09:29:03.453017 start: 2.2.3 depthcharge-start (timeout 00:04:53) [common]
298 09:29:03.453102 Setting prompt string to 'Starting depthcharge on Spherion...'
299 09:29:03.453162 Changing prompt to 'Starting depthcharge on Spherion...'
300 09:29:03.453226 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 09:29:03.453583 [Enter `^Ec?' for help]
302 09:29:03.453655
303 09:29:03.453716
304 09:29:03.453774 F0: 102B 0000
305 09:29:03.453831
306 09:29:03.453888 F3: 1001 0000 [0200]
307 09:29:03.453945
308 09:29:03.454017 F3: 1001 0000
309 09:29:03.454078
310 09:29:03.454136 F7: 102D 0000
311 09:29:03.454193
312 09:29:03.454249 F1: 0000 0000
313 09:29:03.454303
314 09:29:03.454362 V0: 0000 0000 [0001]
315 09:29:03.454417
316 09:29:03.454471 00: 0007 8000
317 09:29:03.454523
318 09:29:03.454576 01: 0000 0000
319 09:29:03.454627
320 09:29:03.454678 BP: 0C00 0209 [0000]
321 09:29:03.454733
322 09:29:03.454783 G0: 1182 0000
323 09:29:03.454832
324 09:29:03.454881 EC: 0000 0021 [4000]
325 09:29:03.454931
326 09:29:03.454981 S7: 0000 0000 [0000]
327 09:29:03.455030
328 09:29:03.455079 CC: 0000 0000 [0001]
329 09:29:03.455128
330 09:29:03.455177 T0: 0000 0040 [010F]
331 09:29:03.455226
332 09:29:03.455275 Jump to BL
333 09:29:03.455323
334 09:29:03.462320
335 09:29:03.462410
336 09:29:03.469095 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 09:29:03.473053 ARM64: Exception handlers installed.
338 09:29:03.476495 ARM64: Testing exception
339 09:29:03.479593 ARM64: Done test exception
340 09:29:03.486162 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 09:29:03.496343 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 09:29:03.502904 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 09:29:03.512917 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 09:29:03.519639 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 09:29:03.526388 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 09:29:03.538498 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 09:29:03.544579 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 09:29:03.564573 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 09:29:03.568112 WDT: Last reset was cold boot
350 09:29:03.571174 SPI1(PAD0) initialized at 2873684 Hz
351 09:29:03.574411 SPI5(PAD0) initialized at 992727 Hz
352 09:29:03.577883 VBOOT: Loading verstage.
353 09:29:03.584685 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 09:29:03.587771 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 09:29:03.591373 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 09:29:03.594468 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 09:29:03.602329 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 09:29:03.608733 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 09:29:03.619554 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
360 09:29:03.619658
361 09:29:03.619747
362 09:29:03.629994 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 09:29:03.633251 ARM64: Exception handlers installed.
364 09:29:03.636524 ARM64: Testing exception
365 09:29:03.636624 ARM64: Done test exception
366 09:29:03.643040 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 09:29:03.646592 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 09:29:03.660762 Probing TPM: . done!
369 09:29:03.660866 TPM ready after 0 ms
370 09:29:03.667502 Connected to device vid:did:rid of 1ae0:0028:00
371 09:29:03.674450 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 09:29:03.715100 Initialized TPM device CR50 revision 0
373 09:29:03.726800 tlcl_send_startup: Startup return code is 0
374 09:29:03.726896 TPM: setup succeeded
375 09:29:03.738909 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 09:29:03.747358 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 09:29:03.757453 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 09:29:03.766071 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 09:29:03.770017 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 09:29:03.773766 in-header: 03 07 00 00 08 00 00 00
381 09:29:03.776853 in-data: aa e4 47 04 13 02 00 00
382 09:29:03.779843 Chrome EC: UHEPI supported
383 09:29:03.786721 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 09:29:03.789879 in-header: 03 c9 00 00 08 00 00 00
385 09:29:03.793575 in-data: 04 00 20 08 00 00 00 00
386 09:29:03.793644 Phase 1
387 09:29:03.796746 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 09:29:03.803611 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 09:29:03.810556 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 09:29:03.813575 Recovery requested (1009000e)
391 09:29:03.820244 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 09:29:03.826175 tlcl_extend: response is 0
393 09:29:03.835900 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 09:29:03.839289 tlcl_extend: response is 0
395 09:29:03.845966 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 09:29:03.866906 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 09:29:03.873168 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 09:29:03.873247
399 09:29:03.873307
400 09:29:03.883800 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 09:29:03.886828 ARM64: Exception handlers installed.
402 09:29:03.889883 ARM64: Testing exception
403 09:29:03.889955 ARM64: Done test exception
404 09:29:03.912071 pmic_efuse_setting: Set efuses in 11 msecs
405 09:29:03.915426 pmwrap_interface_init: Select PMIF_VLD_RDY
406 09:29:03.922221 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 09:29:03.925699 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 09:29:03.932480 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 09:29:03.935402 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 09:29:03.938708 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 09:29:03.945840 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 09:29:03.949382 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 09:29:03.956049 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 09:29:03.958957 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 09:29:03.965873 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 09:29:03.969468 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 09:29:03.972375 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 09:29:03.979797 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 09:29:03.985637 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 09:29:03.989450 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 09:29:03.996129 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 09:29:04.002364 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 09:29:04.006198 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 09:29:04.012906 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 09:29:04.019155 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 09:29:04.022797 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 09:29:04.029286 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 09:29:04.036285 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 09:29:04.039283 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 09:29:04.045854 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 09:29:04.052798 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 09:29:04.056216 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 09:29:04.062847 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 09:29:04.066069 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 09:29:04.069778 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 09:29:04.076091 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 09:29:04.079797 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 09:29:04.086233 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 09:29:04.089499 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 09:29:04.096576 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 09:29:04.099418 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 09:29:04.106255 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 09:29:04.109978 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 09:29:04.116115 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 09:29:04.119940 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 09:29:04.123826 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 09:29:04.127000 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 09:29:04.134016 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 09:29:04.137340 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 09:29:04.140723 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 09:29:04.147337 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 09:29:04.150808 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 09:29:04.154258 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 09:29:04.157579 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 09:29:04.163932 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 09:29:04.167318 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 09:29:04.174007 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
458 09:29:04.184447 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 09:29:04.187585 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 09:29:04.197810 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 09:29:04.204138 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 09:29:04.207466 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 09:29:04.214462 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 09:29:04.217533 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 09:29:04.224816 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x12
466 09:29:04.231559 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 09:29:04.234738 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 09:29:04.238358 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 09:29:04.249334 [RTC]rtc_get_frequency_meter,154: input=15, output=790
470 09:29:04.258729 [RTC]rtc_get_frequency_meter,154: input=23, output=979
471 09:29:04.268538 [RTC]rtc_get_frequency_meter,154: input=19, output=884
472 09:29:04.278122 [RTC]rtc_get_frequency_meter,154: input=17, output=836
473 09:29:04.287713 [RTC]rtc_get_frequency_meter,154: input=16, output=814
474 09:29:04.296990 [RTC]rtc_get_frequency_meter,154: input=15, output=789
475 09:29:04.306630 [RTC]rtc_get_frequency_meter,154: input=16, output=814
476 09:29:04.309697 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 09:29:04.317187 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 09:29:04.320506 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 09:29:04.324132 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 09:29:04.330352 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 09:29:04.334070 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 09:29:04.337117 ADC[4]: Raw value=902066 ID=7
483 09:29:04.337199 ADC[3]: Raw value=213336 ID=1
484 09:29:04.340296 RAM Code: 0x71
485 09:29:04.343913 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 09:29:04.350404 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 09:29:04.357473 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 09:29:04.364285 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 09:29:04.367203 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 09:29:04.370612 in-header: 03 07 00 00 08 00 00 00
491 09:29:04.373805 in-data: aa e4 47 04 13 02 00 00
492 09:29:04.377195 Chrome EC: UHEPI supported
493 09:29:04.384352 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 09:29:04.387198 in-header: 03 c9 00 00 08 00 00 00
495 09:29:04.390785 in-data: 04 00 20 08 00 00 00 00
496 09:29:04.393976 MRC: failed to locate region type 0.
497 09:29:04.400738 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 09:29:04.404449 DRAM-K: Running full calibration
499 09:29:04.407530 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 09:29:04.411317 header.status = 0x0
501 09:29:04.414360 header.version = 0x6 (expected: 0x6)
502 09:29:04.417483 header.size = 0xd00 (expected: 0xd00)
503 09:29:04.417558 header.flags = 0x0
504 09:29:04.424544 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 09:29:04.443527 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 09:29:04.450282 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 09:29:04.453331 dram_init: ddr_geometry: 2
508 09:29:04.453404 [EMI] MDL number = 2
509 09:29:04.456891 [EMI] Get MDL freq = 0
510 09:29:04.460026 dram_init: ddr_type: 0
511 09:29:04.460099 is_discrete_lpddr4: 1
512 09:29:04.463500 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 09:29:04.463576
514 09:29:04.463637
515 09:29:04.466626 [Bian_co] ETT version 0.0.0.1
516 09:29:04.470377 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 09:29:04.473498
518 09:29:04.477102 dramc_set_vcore_voltage set vcore to 650000
519 09:29:04.477174 Read voltage for 800, 4
520 09:29:04.480060 Vio18 = 0
521 09:29:04.480168 Vcore = 650000
522 09:29:04.480261 Vdram = 0
523 09:29:04.483464 Vddq = 0
524 09:29:04.483560 Vmddr = 0
525 09:29:04.487127 dram_init: config_dvfs: 1
526 09:29:04.490425 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 09:29:04.496823 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 09:29:04.500534 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 09:29:04.503577 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 09:29:04.507175 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 09:29:04.510816 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 09:29:04.513918 MEM_TYPE=3, freq_sel=18
533 09:29:04.517102 sv_algorithm_assistance_LP4_1600
534 09:29:04.520877 ============ PULL DRAM RESETB DOWN ============
535 09:29:04.523897 ========== PULL DRAM RESETB DOWN end =========
536 09:29:04.530707 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 09:29:04.534328 ===================================
538 09:29:04.534399 LPDDR4 DRAM CONFIGURATION
539 09:29:04.537201 ===================================
540 09:29:04.540757 EX_ROW_EN[0] = 0x0
541 09:29:04.540829 EX_ROW_EN[1] = 0x0
542 09:29:04.544223 LP4Y_EN = 0x0
543 09:29:04.544294 WORK_FSP = 0x0
544 09:29:04.547470 WL = 0x2
545 09:29:04.547569 RL = 0x2
546 09:29:04.551269 BL = 0x2
547 09:29:04.551347 RPST = 0x0
548 09:29:04.554323 RD_PRE = 0x0
549 09:29:04.557944 WR_PRE = 0x1
550 09:29:04.558030 WR_PST = 0x0
551 09:29:04.560893 DBI_WR = 0x0
552 09:29:04.560967 DBI_RD = 0x0
553 09:29:04.564610 OTF = 0x1
554 09:29:04.567596 ===================================
555 09:29:04.570901 ===================================
556 09:29:04.570983 ANA top config
557 09:29:04.574152 ===================================
558 09:29:04.577846 DLL_ASYNC_EN = 0
559 09:29:04.577925 ALL_SLAVE_EN = 1
560 09:29:04.580877 NEW_RANK_MODE = 1
561 09:29:04.584746 DLL_IDLE_MODE = 1
562 09:29:04.587903 LP45_APHY_COMB_EN = 1
563 09:29:04.591302 TX_ODT_DIS = 1
564 09:29:04.591418 NEW_8X_MODE = 1
565 09:29:04.594717 ===================================
566 09:29:04.597953 ===================================
567 09:29:04.600912 data_rate = 1600
568 09:29:04.604448 CKR = 1
569 09:29:04.607933 DQ_P2S_RATIO = 8
570 09:29:04.611373 ===================================
571 09:29:04.614801 CA_P2S_RATIO = 8
572 09:29:04.614899 DQ_CA_OPEN = 0
573 09:29:04.617785 DQ_SEMI_OPEN = 0
574 09:29:04.621570 CA_SEMI_OPEN = 0
575 09:29:04.624683 CA_FULL_RATE = 0
576 09:29:04.627701 DQ_CKDIV4_EN = 1
577 09:29:04.631400 CA_CKDIV4_EN = 1
578 09:29:04.631509 CA_PREDIV_EN = 0
579 09:29:04.634560 PH8_DLY = 0
580 09:29:04.638216 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 09:29:04.641316 DQ_AAMCK_DIV = 4
582 09:29:04.645161 CA_AAMCK_DIV = 4
583 09:29:04.645247 CA_ADMCK_DIV = 4
584 09:29:04.648071 DQ_TRACK_CA_EN = 0
585 09:29:04.651749 CA_PICK = 800
586 09:29:04.654555 CA_MCKIO = 800
587 09:29:04.658445 MCKIO_SEMI = 0
588 09:29:04.661695 PLL_FREQ = 3068
589 09:29:04.665084 DQ_UI_PI_RATIO = 32
590 09:29:04.665182 CA_UI_PI_RATIO = 0
591 09:29:04.668561 ===================================
592 09:29:04.671710 ===================================
593 09:29:04.674705 memory_type:LPDDR4
594 09:29:04.678244 GP_NUM : 10
595 09:29:04.678333 SRAM_EN : 1
596 09:29:04.681997 MD32_EN : 0
597 09:29:04.685101 ===================================
598 09:29:04.688699 [ANA_INIT] >>>>>>>>>>>>>>
599 09:29:04.688769 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 09:29:04.695035 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 09:29:04.695159 ===================================
602 09:29:04.698697 data_rate = 1600,PCW = 0X7600
603 09:29:04.701969 ===================================
604 09:29:04.705463 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 09:29:04.712051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 09:29:04.718343 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 09:29:04.721873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 09:29:04.725326 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 09:29:04.728863 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 09:29:04.732023 [ANA_INIT] flow start
611 09:29:04.732117 [ANA_INIT] PLL >>>>>>>>
612 09:29:04.735041 [ANA_INIT] PLL <<<<<<<<
613 09:29:04.738847 [ANA_INIT] MIDPI >>>>>>>>
614 09:29:04.738942 [ANA_INIT] MIDPI <<<<<<<<
615 09:29:04.741933 [ANA_INIT] DLL >>>>>>>>
616 09:29:04.744913 [ANA_INIT] flow end
617 09:29:04.748699 ============ LP4 DIFF to SE enter ============
618 09:29:04.751809 ============ LP4 DIFF to SE exit ============
619 09:29:04.754981 [ANA_INIT] <<<<<<<<<<<<<
620 09:29:04.758635 [Flow] Enable top DCM control >>>>>
621 09:29:04.762028 [Flow] Enable top DCM control <<<<<
622 09:29:04.765402 Enable DLL master slave shuffle
623 09:29:04.768875 ==============================================================
624 09:29:04.772216 Gating Mode config
625 09:29:04.778933 ==============================================================
626 09:29:04.779015 Config description:
627 09:29:04.788665 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 09:29:04.795404 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 09:29:04.799039 SELPH_MODE 0: By rank 1: By Phase
630 09:29:04.805349 ==============================================================
631 09:29:04.809185 GAT_TRACK_EN = 1
632 09:29:04.812316 RX_GATING_MODE = 2
633 09:29:04.815735 RX_GATING_TRACK_MODE = 2
634 09:29:04.818696 SELPH_MODE = 1
635 09:29:04.822274 PICG_EARLY_EN = 1
636 09:29:04.822348 VALID_LAT_VALUE = 1
637 09:29:04.829053 ==============================================================
638 09:29:04.832296 Enter into Gating configuration >>>>
639 09:29:04.835698 Exit from Gating configuration <<<<
640 09:29:04.839028 Enter into DVFS_PRE_config >>>>>
641 09:29:04.849063 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 09:29:04.852285 Exit from DVFS_PRE_config <<<<<
643 09:29:04.855948 Enter into PICG configuration >>>>
644 09:29:04.859126 Exit from PICG configuration <<<<
645 09:29:04.862797 [RX_INPUT] configuration >>>>>
646 09:29:04.865934 [RX_INPUT] configuration <<<<<
647 09:29:04.868839 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 09:29:04.875554 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 09:29:04.882442 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 09:29:04.889072 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 09:29:04.892532 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 09:29:04.899188 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 09:29:04.902274 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 09:29:04.909046 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 09:29:04.912224 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 09:29:04.916050 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 09:29:04.918980 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 09:29:04.925593 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 09:29:04.929273 ===================================
660 09:29:04.932393 LPDDR4 DRAM CONFIGURATION
661 09:29:04.935931 ===================================
662 09:29:04.936006 EX_ROW_EN[0] = 0x0
663 09:29:04.939203 EX_ROW_EN[1] = 0x0
664 09:29:04.939282 LP4Y_EN = 0x0
665 09:29:04.942520 WORK_FSP = 0x0
666 09:29:04.942594 WL = 0x2
667 09:29:04.945863 RL = 0x2
668 09:29:04.945972 BL = 0x2
669 09:29:04.949159 RPST = 0x0
670 09:29:04.949257 RD_PRE = 0x0
671 09:29:04.952060 WR_PRE = 0x1
672 09:29:04.952157 WR_PST = 0x0
673 09:29:04.955706 DBI_WR = 0x0
674 09:29:04.955789 DBI_RD = 0x0
675 09:29:04.958730 OTF = 0x1
676 09:29:04.962617 ===================================
677 09:29:04.965559 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 09:29:04.969326 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 09:29:04.976120 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 09:29:04.979257 ===================================
681 09:29:04.979340 LPDDR4 DRAM CONFIGURATION
682 09:29:04.982303 ===================================
683 09:29:04.985889 EX_ROW_EN[0] = 0x10
684 09:29:04.989242 EX_ROW_EN[1] = 0x0
685 09:29:04.989336 LP4Y_EN = 0x0
686 09:29:04.992750 WORK_FSP = 0x0
687 09:29:04.992823 WL = 0x2
688 09:29:04.995626 RL = 0x2
689 09:29:04.995707 BL = 0x2
690 09:29:04.998984 RPST = 0x0
691 09:29:04.999053 RD_PRE = 0x0
692 09:29:05.002761 WR_PRE = 0x1
693 09:29:05.002861 WR_PST = 0x0
694 09:29:05.005661 DBI_WR = 0x0
695 09:29:05.005758 DBI_RD = 0x0
696 09:29:05.009350 OTF = 0x1
697 09:29:05.012491 ===================================
698 09:29:05.019330 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 09:29:05.022330 nWR fixed to 40
700 09:29:05.022403 [ModeRegInit_LP4] CH0 RK0
701 09:29:05.026017 [ModeRegInit_LP4] CH0 RK1
702 09:29:05.029097 [ModeRegInit_LP4] CH1 RK0
703 09:29:05.029167 [ModeRegInit_LP4] CH1 RK1
704 09:29:05.032594 match AC timing 13
705 09:29:05.035748 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 09:29:05.039418 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 09:29:05.046053 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 09:29:05.049463 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 09:29:05.055981 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 09:29:05.056082 [EMI DOE] emi_dcm 0
711 09:29:05.059338 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 09:29:05.062868 ==
713 09:29:05.065861 Dram Type= 6, Freq= 0, CH_0, rank 0
714 09:29:05.068958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 09:29:05.069053 ==
716 09:29:05.075610 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 09:29:05.079161 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 09:29:05.089192 [CA 0] Center 37 (6~68) winsize 63
719 09:29:05.092206 [CA 1] Center 37 (6~68) winsize 63
720 09:29:05.095955 [CA 2] Center 35 (4~66) winsize 63
721 09:29:05.099460 [CA 3] Center 35 (4~66) winsize 63
722 09:29:05.102475 [CA 4] Center 34 (3~65) winsize 63
723 09:29:05.105495 [CA 5] Center 33 (3~64) winsize 62
724 09:29:05.105587
725 09:29:05.108897 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 09:29:05.108990
727 09:29:05.112458 [CATrainingPosCal] consider 1 rank data
728 09:29:05.115916 u2DelayCellTimex100 = 270/100 ps
729 09:29:05.118851 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
730 09:29:05.123313 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 09:29:05.126373 CA2 delay=35 (4~66),Diff = 2 PI (14 cell)
732 09:29:05.130062 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
733 09:29:05.133108 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
734 09:29:05.139855 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 09:29:05.139928
736 09:29:05.143107 CA PerBit enable=1, Macro0, CA PI delay=33
737 09:29:05.143183
738 09:29:05.146743 [CBTSetCACLKResult] CA Dly = 33
739 09:29:05.146818 CS Dly: 5 (0~36)
740 09:29:05.146891 ==
741 09:29:05.149729 Dram Type= 6, Freq= 0, CH_0, rank 1
742 09:29:05.153371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 09:29:05.156325 ==
744 09:29:05.159656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 09:29:05.166574 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 09:29:05.175633 [CA 0] Center 37 (6~68) winsize 63
747 09:29:05.178633 [CA 1] Center 37 (6~68) winsize 63
748 09:29:05.181872 [CA 2] Center 35 (5~66) winsize 62
749 09:29:05.185557 [CA 3] Center 35 (4~66) winsize 63
750 09:29:05.188665 [CA 4] Center 34 (4~65) winsize 62
751 09:29:05.192383 [CA 5] Center 33 (3~64) winsize 62
752 09:29:05.192481
753 09:29:05.195632 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 09:29:05.195702
755 09:29:05.198832 [CATrainingPosCal] consider 2 rank data
756 09:29:05.201783 u2DelayCellTimex100 = 270/100 ps
757 09:29:05.205219 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
758 09:29:05.208891 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
759 09:29:05.215104 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 09:29:05.218590 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
761 09:29:05.221869 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
762 09:29:05.225333 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 09:29:05.225433
764 09:29:05.228583 CA PerBit enable=1, Macro0, CA PI delay=33
765 09:29:05.228682
766 09:29:05.232186 [CBTSetCACLKResult] CA Dly = 33
767 09:29:05.232259 CS Dly: 5 (0~37)
768 09:29:05.235184
769 09:29:05.238882 ----->DramcWriteLeveling(PI) begin...
770 09:29:05.238955 ==
771 09:29:05.241622 Dram Type= 6, Freq= 0, CH_0, rank 0
772 09:29:05.245413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 09:29:05.245504 ==
774 09:29:05.248605 Write leveling (Byte 0): 28 => 28
775 09:29:05.251598 Write leveling (Byte 1): 28 => 28
776 09:29:05.255396 DramcWriteLeveling(PI) end<-----
777 09:29:05.255488
778 09:29:05.255579 ==
779 09:29:05.258545 Dram Type= 6, Freq= 0, CH_0, rank 0
780 09:29:05.262245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 09:29:05.262346 ==
782 09:29:05.265052 [Gating] SW mode calibration
783 09:29:05.272146 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 09:29:05.278876 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 09:29:05.281848 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 09:29:05.285275 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 09:29:05.288934 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 09:29:05.295202 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 09:29:05.298856 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 09:29:05.301997 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 09:29:05.308795 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 09:29:05.311777 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 09:29:05.315304 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 09:29:05.322192 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 09:29:05.325253 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 09:29:05.328917 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 09:29:05.335558 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 09:29:05.338520 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 09:29:05.341968 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 09:29:05.348516 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 09:29:05.352232 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 09:29:05.355355 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
803 09:29:05.362268 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
804 09:29:05.365353 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 09:29:05.368598 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 09:29:05.372140 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 09:29:05.378808 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 09:29:05.382379 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 09:29:05.385098 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 09:29:05.391909 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 09:29:05.395168 0 9 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
812 09:29:05.398603 0 9 12 | B1->B0 | 2929 3232 | 1 0 | (1 1) (0 0)
813 09:29:05.405539 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 09:29:05.408712 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 09:29:05.412435 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 09:29:05.418932 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 09:29:05.421874 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 09:29:05.425383 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 09:29:05.432282 0 10 8 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
820 09:29:05.435692 0 10 12 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
821 09:29:05.438574 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 09:29:05.445749 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 09:29:05.448818 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 09:29:05.452227 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 09:29:05.455474 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 09:29:05.462320 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 09:29:05.465595 0 11 8 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
828 09:29:05.469235 0 11 12 | B1->B0 | 3b3b 3f3f | 0 0 | (0 0) (0 0)
829 09:29:05.475744 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 09:29:05.478791 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 09:29:05.482498 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 09:29:05.489178 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 09:29:05.492095 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 09:29:05.495510 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 09:29:05.502309 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 09:29:05.505602 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 09:29:05.508659 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 09:29:05.515553 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 09:29:05.519269 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 09:29:05.522426 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 09:29:05.528985 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 09:29:05.532699 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 09:29:05.535782 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 09:29:05.538973 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 09:29:05.545577 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 09:29:05.548911 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 09:29:05.552404 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 09:29:05.559160 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 09:29:05.562329 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 09:29:05.565578 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 09:29:05.572754 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 09:29:05.575832 Total UI for P1: 0, mck2ui 16
853 09:29:05.579305 best dqsien dly found for B0: ( 0, 14, 6)
854 09:29:05.582268 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
855 09:29:05.585885 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 09:29:05.589149 Total UI for P1: 0, mck2ui 16
857 09:29:05.592157 best dqsien dly found for B1: ( 0, 14, 10)
858 09:29:05.595888 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 09:29:05.599137 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 09:29:05.599229
861 09:29:05.605639 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 09:29:05.609050 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 09:29:05.609147 [Gating] SW calibration Done
864 09:29:05.612051 ==
865 09:29:05.615796 Dram Type= 6, Freq= 0, CH_0, rank 0
866 09:29:05.618801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 09:29:05.618872 ==
868 09:29:05.618932 RX Vref Scan: 0
869 09:29:05.618988
870 09:29:05.621998 RX Vref 0 -> 0, step: 1
871 09:29:05.622109
872 09:29:05.625777 RX Delay -130 -> 252, step: 16
873 09:29:05.628870 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 09:29:05.632405 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 09:29:05.639056 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 09:29:05.642112 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 09:29:05.645913 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 09:29:05.649042 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
879 09:29:05.652110 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
880 09:29:05.655632 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
881 09:29:05.662069 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
882 09:29:05.665773 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 09:29:05.668781 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 09:29:05.672187 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 09:29:05.678591 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
886 09:29:05.682237 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 09:29:05.685262 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 09:29:05.688887 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 09:29:05.688974 ==
890 09:29:05.692466 Dram Type= 6, Freq= 0, CH_0, rank 0
891 09:29:05.695454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 09:29:05.698707 ==
893 09:29:05.698777 DQS Delay:
894 09:29:05.698835 DQS0 = 0, DQS1 = 0
895 09:29:05.702255 DQM Delay:
896 09:29:05.702318 DQM0 = 84, DQM1 = 75
897 09:29:05.705270 DQ Delay:
898 09:29:05.705345 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 09:29:05.708766 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
900 09:29:05.712113 DQ8 =53, DQ9 =69, DQ10 =77, DQ11 =69
901 09:29:05.715651 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
902 09:29:05.715744
903 09:29:05.718549
904 09:29:05.718644 ==
905 09:29:05.722379 Dram Type= 6, Freq= 0, CH_0, rank 0
906 09:29:05.725509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 09:29:05.725616 ==
908 09:29:05.725705
909 09:29:05.725793
910 09:29:05.728666 TX Vref Scan disable
911 09:29:05.728758 == TX Byte 0 ==
912 09:29:05.735522 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
913 09:29:05.738539 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
914 09:29:05.738633 == TX Byte 1 ==
915 09:29:05.745276 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 09:29:05.748805 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 09:29:05.748904 ==
918 09:29:05.751909 Dram Type= 6, Freq= 0, CH_0, rank 0
919 09:29:05.755513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 09:29:05.755591 ==
921 09:29:05.769153 TX Vref=22, minBit 3, minWin=27, winSum=443
922 09:29:05.772252 TX Vref=24, minBit 3, minWin=27, winSum=442
923 09:29:05.775829 TX Vref=26, minBit 0, minWin=27, winSum=443
924 09:29:05.779173 TX Vref=28, minBit 12, minWin=27, winSum=450
925 09:29:05.782191 TX Vref=30, minBit 2, minWin=28, winSum=453
926 09:29:05.785731 TX Vref=32, minBit 12, minWin=27, winSum=451
927 09:29:05.792485 [TxChooseVref] Worse bit 2, Min win 28, Win sum 453, Final Vref 30
928 09:29:05.792581
929 09:29:05.795774 Final TX Range 1 Vref 30
930 09:29:05.795867
931 09:29:05.795951 ==
932 09:29:05.798985 Dram Type= 6, Freq= 0, CH_0, rank 0
933 09:29:05.802202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 09:29:05.802278 ==
935 09:29:05.802336
936 09:29:05.805873
937 09:29:05.805963 TX Vref Scan disable
938 09:29:05.808914 == TX Byte 0 ==
939 09:29:05.812511 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 09:29:05.815709 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 09:29:05.819328 == TX Byte 1 ==
942 09:29:05.822616 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 09:29:05.826163 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 09:29:05.826237
945 09:29:05.829295 [DATLAT]
946 09:29:05.829368 Freq=800, CH0 RK0
947 09:29:05.829444
948 09:29:05.832491 DATLAT Default: 0xa
949 09:29:05.832564 0, 0xFFFF, sum = 0
950 09:29:05.836184 1, 0xFFFF, sum = 0
951 09:29:05.836258 2, 0xFFFF, sum = 0
952 09:29:05.839367 3, 0xFFFF, sum = 0
953 09:29:05.839440 4, 0xFFFF, sum = 0
954 09:29:05.842511 5, 0xFFFF, sum = 0
955 09:29:05.842583 6, 0xFFFF, sum = 0
956 09:29:05.846104 7, 0xFFFF, sum = 0
957 09:29:05.846178 8, 0xFFFF, sum = 0
958 09:29:05.849228 9, 0x0, sum = 1
959 09:29:05.849325 10, 0x0, sum = 2
960 09:29:05.852928 11, 0x0, sum = 3
961 09:29:05.853001 12, 0x0, sum = 4
962 09:29:05.856240 best_step = 10
963 09:29:05.856312
964 09:29:05.856385 ==
965 09:29:05.859232 Dram Type= 6, Freq= 0, CH_0, rank 0
966 09:29:05.862845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 09:29:05.862921 ==
968 09:29:05.865908 RX Vref Scan: 1
969 09:29:05.866019
970 09:29:05.866107 Set Vref Range= 32 -> 127
971 09:29:05.866196
972 09:29:05.869002 RX Vref 32 -> 127, step: 1
973 09:29:05.869090
974 09:29:05.872642 RX Delay -111 -> 252, step: 8
975 09:29:05.872709
976 09:29:05.875859 Set Vref, RX VrefLevel [Byte0]: 32
977 09:29:05.879372 [Byte1]: 32
978 09:29:05.879445
979 09:29:05.882436 Set Vref, RX VrefLevel [Byte0]: 33
980 09:29:05.886069 [Byte1]: 33
981 09:29:05.889613
982 09:29:05.889682 Set Vref, RX VrefLevel [Byte0]: 34
983 09:29:05.892558 [Byte1]: 34
984 09:29:05.896828
985 09:29:05.896899 Set Vref, RX VrefLevel [Byte0]: 35
986 09:29:05.900227 [Byte1]: 35
987 09:29:05.904957
988 09:29:05.905025 Set Vref, RX VrefLevel [Byte0]: 36
989 09:29:05.908021 [Byte1]: 36
990 09:29:05.912294
991 09:29:05.912361 Set Vref, RX VrefLevel [Byte0]: 37
992 09:29:05.915353 [Byte1]: 37
993 09:29:05.920090
994 09:29:05.920158 Set Vref, RX VrefLevel [Byte0]: 38
995 09:29:05.922965 [Byte1]: 38
996 09:29:05.927810
997 09:29:05.927884 Set Vref, RX VrefLevel [Byte0]: 39
998 09:29:05.930845 [Byte1]: 39
999 09:29:05.934971
1000 09:29:05.935039 Set Vref, RX VrefLevel [Byte0]: 40
1001 09:29:05.938800 [Byte1]: 40
1002 09:29:05.943200
1003 09:29:05.943266 Set Vref, RX VrefLevel [Byte0]: 41
1004 09:29:05.946407 [Byte1]: 41
1005 09:29:05.950592
1006 09:29:05.950659 Set Vref, RX VrefLevel [Byte0]: 42
1007 09:29:05.953675 [Byte1]: 42
1008 09:29:05.957960
1009 09:29:05.958059 Set Vref, RX VrefLevel [Byte0]: 43
1010 09:29:05.961427 [Byte1]: 43
1011 09:29:05.966162
1012 09:29:05.966234 Set Vref, RX VrefLevel [Byte0]: 44
1013 09:29:05.969245 [Byte1]: 44
1014 09:29:05.973711
1015 09:29:05.973803 Set Vref, RX VrefLevel [Byte0]: 45
1016 09:29:05.976541 [Byte1]: 45
1017 09:29:05.981283
1018 09:29:05.981392 Set Vref, RX VrefLevel [Byte0]: 46
1019 09:29:05.984552 [Byte1]: 46
1020 09:29:05.989034
1021 09:29:05.989119 Set Vref, RX VrefLevel [Byte0]: 47
1022 09:29:05.991955 [Byte1]: 47
1023 09:29:05.996222
1024 09:29:05.996293 Set Vref, RX VrefLevel [Byte0]: 48
1025 09:29:06.003258 [Byte1]: 48
1026 09:29:06.003334
1027 09:29:06.006054 Set Vref, RX VrefLevel [Byte0]: 49
1028 09:29:06.009656 [Byte1]: 49
1029 09:29:06.009750
1030 09:29:06.012740 Set Vref, RX VrefLevel [Byte0]: 50
1031 09:29:06.016228 [Byte1]: 50
1032 09:29:06.016321
1033 09:29:06.019381 Set Vref, RX VrefLevel [Byte0]: 51
1034 09:29:06.023216 [Byte1]: 51
1035 09:29:06.026784
1036 09:29:06.026875 Set Vref, RX VrefLevel [Byte0]: 52
1037 09:29:06.030302 [Byte1]: 52
1038 09:29:06.034473
1039 09:29:06.034547 Set Vref, RX VrefLevel [Byte0]: 53
1040 09:29:06.037773 [Byte1]: 53
1041 09:29:06.042030
1042 09:29:06.042102 Set Vref, RX VrefLevel [Byte0]: 54
1043 09:29:06.045869 [Byte1]: 54
1044 09:29:06.050262
1045 09:29:06.050331 Set Vref, RX VrefLevel [Byte0]: 55
1046 09:29:06.053266 [Byte1]: 55
1047 09:29:06.057766
1048 09:29:06.057835 Set Vref, RX VrefLevel [Byte0]: 56
1049 09:29:06.060755 [Byte1]: 56
1050 09:29:06.065126
1051 09:29:06.065218 Set Vref, RX VrefLevel [Byte0]: 57
1052 09:29:06.068978 [Byte1]: 57
1053 09:29:06.072927
1054 09:29:06.072997 Set Vref, RX VrefLevel [Byte0]: 58
1055 09:29:06.075945 [Byte1]: 58
1056 09:29:06.080248
1057 09:29:06.080319 Set Vref, RX VrefLevel [Byte0]: 59
1058 09:29:06.083936 [Byte1]: 59
1059 09:29:06.088280
1060 09:29:06.088353 Set Vref, RX VrefLevel [Byte0]: 60
1061 09:29:06.091699 [Byte1]: 60
1062 09:29:06.096085
1063 09:29:06.096154 Set Vref, RX VrefLevel [Byte0]: 61
1064 09:29:06.099280 [Byte1]: 61
1065 09:29:06.103644
1066 09:29:06.103716 Set Vref, RX VrefLevel [Byte0]: 62
1067 09:29:06.106755 [Byte1]: 62
1068 09:29:06.110988
1069 09:29:06.111056 Set Vref, RX VrefLevel [Byte0]: 63
1070 09:29:06.114288 [Byte1]: 63
1071 09:29:06.118785
1072 09:29:06.118857 Set Vref, RX VrefLevel [Byte0]: 64
1073 09:29:06.121970 [Byte1]: 64
1074 09:29:06.126156
1075 09:29:06.126231 Set Vref, RX VrefLevel [Byte0]: 65
1076 09:29:06.129871 [Byte1]: 65
1077 09:29:06.134060
1078 09:29:06.134130 Set Vref, RX VrefLevel [Byte0]: 66
1079 09:29:06.137647 [Byte1]: 66
1080 09:29:06.141686
1081 09:29:06.141755 Set Vref, RX VrefLevel [Byte0]: 67
1082 09:29:06.144666 [Byte1]: 67
1083 09:29:06.149594
1084 09:29:06.149665 Set Vref, RX VrefLevel [Byte0]: 68
1085 09:29:06.152502 [Byte1]: 68
1086 09:29:06.156957
1087 09:29:06.157030 Set Vref, RX VrefLevel [Byte0]: 69
1088 09:29:06.160055 [Byte1]: 69
1089 09:29:06.164414
1090 09:29:06.164511 Set Vref, RX VrefLevel [Byte0]: 70
1091 09:29:06.168026 [Byte1]: 70
1092 09:29:06.172313
1093 09:29:06.172381 Set Vref, RX VrefLevel [Byte0]: 71
1094 09:29:06.175359 [Byte1]: 71
1095 09:29:06.180243
1096 09:29:06.180336 Set Vref, RX VrefLevel [Byte0]: 72
1097 09:29:06.183146 [Byte1]: 72
1098 09:29:06.187436
1099 09:29:06.187523 Set Vref, RX VrefLevel [Byte0]: 73
1100 09:29:06.190656 [Byte1]: 73
1101 09:29:06.195078
1102 09:29:06.195167 Set Vref, RX VrefLevel [Byte0]: 74
1103 09:29:06.198589 [Byte1]: 74
1104 09:29:06.202871
1105 09:29:06.202933 Set Vref, RX VrefLevel [Byte0]: 75
1106 09:29:06.205975 [Byte1]: 75
1107 09:29:06.210345
1108 09:29:06.210431 Set Vref, RX VrefLevel [Byte0]: 76
1109 09:29:06.213782 [Byte1]: 76
1110 09:29:06.218039
1111 09:29:06.218106 Final RX Vref Byte 0 = 60 to rank0
1112 09:29:06.221481 Final RX Vref Byte 1 = 56 to rank0
1113 09:29:06.224806 Final RX Vref Byte 0 = 60 to rank1
1114 09:29:06.227970 Final RX Vref Byte 1 = 56 to rank1==
1115 09:29:06.231152 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 09:29:06.238024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 09:29:06.238115 ==
1118 09:29:06.238198 DQS Delay:
1119 09:29:06.238277 DQS0 = 0, DQS1 = 0
1120 09:29:06.241573 DQM Delay:
1121 09:29:06.241661 DQM0 = 86, DQM1 = 78
1122 09:29:06.244615 DQ Delay:
1123 09:29:06.248179 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1124 09:29:06.251192 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1125 09:29:06.251277 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =72
1126 09:29:06.254794 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1127 09:29:06.257963
1128 09:29:06.258064
1129 09:29:06.264899 [DQSOSCAuto] RK0, (LSB)MR18= 0x260d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1130 09:29:06.267985 CH0 RK0: MR19=606, MR18=260D
1131 09:29:06.275006 CH0_RK0: MR19=0x606, MR18=0x260D, DQSOSC=400, MR23=63, INC=92, DEC=61
1132 09:29:06.275071
1133 09:29:06.278154 ----->DramcWriteLeveling(PI) begin...
1134 09:29:06.278218 ==
1135 09:29:06.281796 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 09:29:06.284774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 09:29:06.284840 ==
1138 09:29:06.288184 Write leveling (Byte 0): 28 => 28
1139 09:29:06.291738 Write leveling (Byte 1): 28 => 28
1140 09:29:06.294871 DramcWriteLeveling(PI) end<-----
1141 09:29:06.294935
1142 09:29:06.294992 ==
1143 09:29:06.297965 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 09:29:06.301723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 09:29:06.301784 ==
1146 09:29:06.304882 [Gating] SW mode calibration
1147 09:29:06.311498 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 09:29:06.318535 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 09:29:06.321626 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 09:29:06.324910 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 09:29:06.331373 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1152 09:29:06.334999 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 09:29:06.338445 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 09:29:06.385870 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 09:29:06.385987 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 09:29:06.386327 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 09:29:06.386419 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 09:29:06.386511 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 09:29:06.386600 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 09:29:06.386689 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 09:29:06.386791 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 09:29:06.386876 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 09:29:06.386963 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 09:29:06.387051 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 09:29:06.390271 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 09:29:06.396770 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1167 09:29:06.400230 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1168 09:29:06.403349 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 09:29:06.410202 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 09:29:06.413432 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 09:29:06.417129 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 09:29:06.423403 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 09:29:06.427154 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 09:29:06.430556 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 09:29:06.437121 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
1176 09:29:06.440282 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
1177 09:29:06.443460 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 09:29:06.450608 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 09:29:06.453653 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 09:29:06.457056 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 09:29:06.460256 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 09:29:06.466878 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
1183 09:29:06.470407 0 10 8 | B1->B0 | 3131 2525 | 0 0 | (0 1) (0 0)
1184 09:29:06.473855 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 09:29:06.480576 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 09:29:06.483612 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 09:29:06.487256 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 09:29:06.493481 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 09:29:06.497230 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 09:29:06.500260 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1191 09:29:06.507314 0 11 8 | B1->B0 | 2828 3c3c | 0 0 | (0 0) (0 0)
1192 09:29:06.510461 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1193 09:29:06.513497 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 09:29:06.520172 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 09:29:06.524002 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 09:29:06.527132 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 09:29:06.533998 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 09:29:06.537123 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1199 09:29:06.540471 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1200 09:29:06.547363 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 09:29:06.550507 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 09:29:06.553637 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 09:29:06.556925 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 09:29:06.563970 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 09:29:06.567124 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 09:29:06.570447 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 09:29:06.577382 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 09:29:06.580546 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 09:29:06.583905 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 09:29:06.590837 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 09:29:06.594111 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 09:29:06.597119 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 09:29:06.603823 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 09:29:06.606877 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1215 09:29:06.610496 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1216 09:29:06.614164 Total UI for P1: 0, mck2ui 16
1217 09:29:06.616851 best dqsien dly found for B0: ( 0, 14, 4)
1218 09:29:06.623854 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 09:29:06.623957 Total UI for P1: 0, mck2ui 16
1220 09:29:06.626953 best dqsien dly found for B1: ( 0, 14, 6)
1221 09:29:06.633805 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1222 09:29:06.636927 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1223 09:29:06.637003
1224 09:29:06.640684 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1225 09:29:06.643665 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1226 09:29:06.647290 [Gating] SW calibration Done
1227 09:29:06.647366 ==
1228 09:29:06.650391 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 09:29:06.653925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 09:29:06.654057 ==
1231 09:29:06.656860 RX Vref Scan: 0
1232 09:29:06.656951
1233 09:29:06.657043 RX Vref 0 -> 0, step: 1
1234 09:29:06.657114
1235 09:29:06.660252 RX Delay -130 -> 252, step: 16
1236 09:29:06.663874 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1237 09:29:06.670661 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1238 09:29:06.673547 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1239 09:29:06.677182 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1240 09:29:06.680178 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1241 09:29:06.683774 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1242 09:29:06.687138 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1243 09:29:06.693536 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1244 09:29:06.696931 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1245 09:29:06.700047 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1246 09:29:06.703597 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1247 09:29:06.707278 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1248 09:29:06.713512 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1249 09:29:06.717077 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1250 09:29:06.720591 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1251 09:29:06.724159 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1252 09:29:06.724255 ==
1253 09:29:06.727162 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 09:29:06.734052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 09:29:06.734122 ==
1256 09:29:06.734190 DQS Delay:
1257 09:29:06.737199 DQS0 = 0, DQS1 = 0
1258 09:29:06.737261 DQM Delay:
1259 09:29:06.737315 DQM0 = 90, DQM1 = 80
1260 09:29:06.740959 DQ Delay:
1261 09:29:06.744114 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1262 09:29:06.747120 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
1263 09:29:06.750758 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1264 09:29:06.753796 DQ12 =77, DQ13 =93, DQ14 =93, DQ15 =93
1265 09:29:06.753886
1266 09:29:06.753972
1267 09:29:06.754116 ==
1268 09:29:06.757480 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 09:29:06.760655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 09:29:06.760741 ==
1271 09:29:06.760822
1272 09:29:06.760900
1273 09:29:06.763851 TX Vref Scan disable
1274 09:29:06.763934 == TX Byte 0 ==
1275 09:29:06.770619 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1276 09:29:06.774183 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1277 09:29:06.774247 == TX Byte 1 ==
1278 09:29:06.780469 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1279 09:29:06.783984 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1280 09:29:06.784050 ==
1281 09:29:06.787106 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 09:29:06.790201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 09:29:06.790272 ==
1284 09:29:06.804301 TX Vref=22, minBit 2, minWin=27, winSum=442
1285 09:29:06.807745 TX Vref=24, minBit 3, minWin=27, winSum=447
1286 09:29:06.811183 TX Vref=26, minBit 7, minWin=27, winSum=450
1287 09:29:06.814194 TX Vref=28, minBit 9, minWin=27, winSum=452
1288 09:29:06.817427 TX Vref=30, minBit 0, minWin=28, winSum=454
1289 09:29:06.821192 TX Vref=32, minBit 0, minWin=28, winSum=453
1290 09:29:06.827745 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
1291 09:29:06.827837
1292 09:29:06.831252 Final TX Range 1 Vref 30
1293 09:29:06.831339
1294 09:29:06.831429 ==
1295 09:29:06.834263 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 09:29:06.838043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 09:29:06.838106 ==
1298 09:29:06.838160
1299 09:29:06.841249
1300 09:29:06.841346 TX Vref Scan disable
1301 09:29:06.844363 == TX Byte 0 ==
1302 09:29:06.847407 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1303 09:29:06.854131 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1304 09:29:06.854202 == TX Byte 1 ==
1305 09:29:06.857771 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1306 09:29:06.860932 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1307 09:29:06.864526
1308 09:29:06.864613 [DATLAT]
1309 09:29:06.864695 Freq=800, CH0 RK1
1310 09:29:06.864774
1311 09:29:06.867725 DATLAT Default: 0xa
1312 09:29:06.867809 0, 0xFFFF, sum = 0
1313 09:29:06.870741 1, 0xFFFF, sum = 0
1314 09:29:06.870804 2, 0xFFFF, sum = 0
1315 09:29:06.874370 3, 0xFFFF, sum = 0
1316 09:29:06.874433 4, 0xFFFF, sum = 0
1317 09:29:06.877375 5, 0xFFFF, sum = 0
1318 09:29:06.877444 6, 0xFFFF, sum = 0
1319 09:29:06.881234 7, 0xFFFF, sum = 0
1320 09:29:06.884635 8, 0xFFFF, sum = 0
1321 09:29:06.884722 9, 0x0, sum = 1
1322 09:29:06.884804 10, 0x0, sum = 2
1323 09:29:06.887600 11, 0x0, sum = 3
1324 09:29:06.887662 12, 0x0, sum = 4
1325 09:29:06.891051 best_step = 10
1326 09:29:06.891112
1327 09:29:06.891162 ==
1328 09:29:06.894323 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 09:29:06.897855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 09:29:06.897941 ==
1331 09:29:06.900745 RX Vref Scan: 0
1332 09:29:06.900807
1333 09:29:06.900859 RX Vref 0 -> 0, step: 1
1334 09:29:06.900909
1335 09:29:06.904264 RX Delay -95 -> 252, step: 8
1336 09:29:06.911047 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1337 09:29:06.914570 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1338 09:29:06.917515 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1339 09:29:06.920969 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1340 09:29:06.924327 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1341 09:29:06.930804 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1342 09:29:06.934387 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1343 09:29:06.938092 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1344 09:29:06.940960 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1345 09:29:06.944692 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1346 09:29:06.950909 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1347 09:29:06.954558 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1348 09:29:06.957598 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1349 09:29:06.961244 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1350 09:29:06.964381 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1351 09:29:06.971414 iDelay=209, Bit 15, Center 84 (-23 ~ 192) 216
1352 09:29:06.971478 ==
1353 09:29:06.974446 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 09:29:06.978194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 09:29:06.978280 ==
1356 09:29:06.978362 DQS Delay:
1357 09:29:06.981098 DQS0 = 0, DQS1 = 0
1358 09:29:06.981180 DQM Delay:
1359 09:29:06.984791 DQM0 = 87, DQM1 = 77
1360 09:29:06.984874 DQ Delay:
1361 09:29:06.987751 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1362 09:29:06.991483 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1363 09:29:06.994304 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1364 09:29:06.997867 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1365 09:29:06.997954
1366 09:29:06.998038
1367 09:29:07.004503 [DQSOSCAuto] RK1, (LSB)MR18= 0x321c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1368 09:29:07.008057 CH0 RK1: MR19=606, MR18=321C
1369 09:29:07.014871 CH0_RK1: MR19=0x606, MR18=0x321C, DQSOSC=397, MR23=63, INC=93, DEC=62
1370 09:29:07.018036 [RxdqsGatingPostProcess] freq 800
1371 09:29:07.024882 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 09:29:07.024956 Pre-setting of DQS Precalculation
1373 09:29:07.031451 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 09:29:07.031520 ==
1375 09:29:07.034779 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 09:29:07.038121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 09:29:07.038192 ==
1378 09:29:07.044582 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 09:29:07.051154 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 09:29:07.059271 [CA 0] Center 36 (6~66) winsize 61
1381 09:29:07.062959 [CA 1] Center 36 (6~66) winsize 61
1382 09:29:07.065931 [CA 2] Center 34 (4~64) winsize 61
1383 09:29:07.068925 [CA 3] Center 34 (3~65) winsize 63
1384 09:29:07.072716 [CA 4] Center 34 (4~65) winsize 62
1385 09:29:07.075920 [CA 5] Center 33 (3~64) winsize 62
1386 09:29:07.076015
1387 09:29:07.078993 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1388 09:29:07.079063
1389 09:29:07.082643 [CATrainingPosCal] consider 1 rank data
1390 09:29:07.086279 u2DelayCellTimex100 = 270/100 ps
1391 09:29:07.089345 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1392 09:29:07.092924 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1393 09:29:07.096109 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1394 09:29:07.102960 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1395 09:29:07.105909 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1396 09:29:07.109281 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 09:29:07.109369
1398 09:29:07.112930 CA PerBit enable=1, Macro0, CA PI delay=33
1399 09:29:07.113020
1400 09:29:07.116133 [CBTSetCACLKResult] CA Dly = 33
1401 09:29:07.116221 CS Dly: 4 (0~35)
1402 09:29:07.116311 ==
1403 09:29:07.119127 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 09:29:07.126235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 09:29:07.126304 ==
1406 09:29:07.129432 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 09:29:07.136207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 09:29:07.145045 [CA 0] Center 36 (6~66) winsize 61
1409 09:29:07.148724 [CA 1] Center 36 (6~66) winsize 61
1410 09:29:07.151729 [CA 2] Center 34 (4~65) winsize 62
1411 09:29:07.155059 [CA 3] Center 33 (3~64) winsize 62
1412 09:29:07.158528 [CA 4] Center 34 (4~65) winsize 62
1413 09:29:07.161728 [CA 5] Center 33 (3~64) winsize 62
1414 09:29:07.161831
1415 09:29:07.165380 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1416 09:29:07.165447
1417 09:29:07.168491 [CATrainingPosCal] consider 2 rank data
1418 09:29:07.171648 u2DelayCellTimex100 = 270/100 ps
1419 09:29:07.175436 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1420 09:29:07.178509 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1421 09:29:07.182158 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1422 09:29:07.188813 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1423 09:29:07.191880 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1424 09:29:07.195402 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 09:29:07.195490
1426 09:29:07.199048 CA PerBit enable=1, Macro0, CA PI delay=33
1427 09:29:07.199112
1428 09:29:07.202096 [CBTSetCACLKResult] CA Dly = 33
1429 09:29:07.202158 CS Dly: 4 (0~36)
1430 09:29:07.202216
1431 09:29:07.205200 ----->DramcWriteLeveling(PI) begin...
1432 09:29:07.205289 ==
1433 09:29:07.208445 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 09:29:07.214884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 09:29:07.214953 ==
1436 09:29:07.218391 Write leveling (Byte 0): 27 => 27
1437 09:29:07.221504 Write leveling (Byte 1): 28 => 28
1438 09:29:07.225392 DramcWriteLeveling(PI) end<-----
1439 09:29:07.225463
1440 09:29:07.225548 ==
1441 09:29:07.228376 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 09:29:07.232119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 09:29:07.232214 ==
1444 09:29:07.235084 [Gating] SW mode calibration
1445 09:29:07.242071 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 09:29:07.245191 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 09:29:07.251899 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 09:29:07.255058 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (1 0)
1449 09:29:07.258518 0 6 8 | B1->B0 | 2322 2323 | 1 0 | (1 0) (0 0)
1450 09:29:07.265202 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 09:29:07.268341 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 09:29:07.272021 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 09:29:07.278448 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 09:29:07.281583 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 09:29:07.285214 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 09:29:07.291856 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 09:29:07.294956 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 09:29:07.298564 0 7 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1459 09:29:07.305163 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 09:29:07.308351 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 09:29:07.311987 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 09:29:07.318647 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 09:29:07.321593 0 8 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1464 09:29:07.325016 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1465 09:29:07.331766 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1466 09:29:07.334985 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 09:29:07.338681 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 09:29:07.341756 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 09:29:07.348239 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 09:29:07.351578 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 09:29:07.355233 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 09:29:07.361629 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 09:29:07.364876 0 9 8 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
1474 09:29:07.368426 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1475 09:29:07.374752 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 09:29:07.378398 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1477 09:29:07.382046 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 09:29:07.388517 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 09:29:07.392080 0 10 0 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1480 09:29:07.395086 0 10 4 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
1481 09:29:07.402095 0 10 8 | B1->B0 | 2f2f 2e2e | 1 1 | (1 0) (1 0)
1482 09:29:07.405313 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 09:29:07.408542 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 09:29:07.412123 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 09:29:07.418503 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 09:29:07.422131 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 09:29:07.425175 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1488 09:29:07.432023 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 09:29:07.435150 0 11 8 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
1490 09:29:07.438740 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 09:29:07.445747 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 09:29:07.448754 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 09:29:07.451887 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 09:29:07.458492 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 09:29:07.462030 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 09:29:07.465234 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 09:29:07.472066 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 09:29:07.475175 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 09:29:07.479065 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 09:29:07.485179 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 09:29:07.489052 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 09:29:07.491953 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 09:29:07.495607 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 09:29:07.501967 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 09:29:07.505410 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 09:29:07.508451 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 09:29:07.515632 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 09:29:07.519015 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 09:29:07.522019 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 09:29:07.528744 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 09:29:07.532355 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 09:29:07.535329 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 09:29:07.542140 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1514 09:29:07.542235 Total UI for P1: 0, mck2ui 16
1515 09:29:07.548540 best dqsien dly found for B1: ( 0, 14, 6)
1516 09:29:07.552117 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 09:29:07.555753 Total UI for P1: 0, mck2ui 16
1518 09:29:07.558899 best dqsien dly found for B0: ( 0, 14, 8)
1519 09:29:07.562129 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1520 09:29:07.565143 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1521 09:29:07.565219
1522 09:29:07.568922 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1523 09:29:07.572283 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1524 09:29:07.575609 [Gating] SW calibration Done
1525 09:29:07.575674 ==
1526 09:29:07.578774 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 09:29:07.582057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 09:29:07.582130 ==
1529 09:29:07.585735 RX Vref Scan: 0
1530 09:29:07.585827
1531 09:29:07.588866 RX Vref 0 -> 0, step: 1
1532 09:29:07.588949
1533 09:29:07.589003 RX Delay -130 -> 252, step: 16
1534 09:29:07.595679 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1535 09:29:07.598821 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1536 09:29:07.602524 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1537 09:29:07.605515 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1538 09:29:07.609153 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1539 09:29:07.615329 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1540 09:29:07.619051 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1541 09:29:07.622172 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1542 09:29:07.625753 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1543 09:29:07.628764 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1544 09:29:07.635540 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1545 09:29:07.638567 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1546 09:29:07.642132 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1547 09:29:07.645273 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1548 09:29:07.648568 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1549 09:29:07.655412 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1550 09:29:07.655506 ==
1551 09:29:07.658536 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 09:29:07.661989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 09:29:07.662074 ==
1554 09:29:07.662133 DQS Delay:
1555 09:29:07.665907 DQS0 = 0, DQS1 = 0
1556 09:29:07.666000 DQM Delay:
1557 09:29:07.668842 DQM0 = 83, DQM1 = 75
1558 09:29:07.668925 DQ Delay:
1559 09:29:07.672028 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1560 09:29:07.675678 DQ4 =85, DQ5 =85, DQ6 =93, DQ7 =77
1561 09:29:07.678801 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
1562 09:29:07.682244 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1563 09:29:07.682307
1564 09:29:07.682378
1565 09:29:07.682433 ==
1566 09:29:07.685285 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 09:29:07.688913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 09:29:07.688989 ==
1569 09:29:07.689045
1570 09:29:07.689124
1571 09:29:07.692110 TX Vref Scan disable
1572 09:29:07.695788 == TX Byte 0 ==
1573 09:29:07.698906 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1574 09:29:07.701922 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1575 09:29:07.705743 == TX Byte 1 ==
1576 09:29:07.708794 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1577 09:29:07.712445 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1578 09:29:07.712524 ==
1579 09:29:07.715595 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 09:29:07.722382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 09:29:07.722458 ==
1582 09:29:07.733630 TX Vref=22, minBit 0, minWin=27, winSum=440
1583 09:29:07.737505 TX Vref=24, minBit 0, minWin=27, winSum=442
1584 09:29:07.740535 TX Vref=26, minBit 7, minWin=27, winSum=449
1585 09:29:07.743669 TX Vref=28, minBit 1, minWin=28, winSum=453
1586 09:29:07.747049 TX Vref=30, minBit 2, minWin=28, winSum=456
1587 09:29:07.750601 TX Vref=32, minBit 0, minWin=28, winSum=456
1588 09:29:07.757384 [TxChooseVref] Worse bit 2, Min win 28, Win sum 456, Final Vref 30
1589 09:29:07.757461
1590 09:29:07.760453 Final TX Range 1 Vref 30
1591 09:29:07.760530
1592 09:29:07.760589 ==
1593 09:29:07.764224 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 09:29:07.767557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 09:29:07.767634 ==
1596 09:29:07.767693
1597 09:29:07.767747
1598 09:29:07.770842 TX Vref Scan disable
1599 09:29:07.774170 == TX Byte 0 ==
1600 09:29:07.777439 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1601 09:29:07.780545 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1602 09:29:07.784169 == TX Byte 1 ==
1603 09:29:07.787382 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1604 09:29:07.790535 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1605 09:29:07.790612
1606 09:29:07.794398 [DATLAT]
1607 09:29:07.794474 Freq=800, CH1 RK0
1608 09:29:07.794546
1609 09:29:07.797251 DATLAT Default: 0xa
1610 09:29:07.797328 0, 0xFFFF, sum = 0
1611 09:29:07.800913 1, 0xFFFF, sum = 0
1612 09:29:07.800990 2, 0xFFFF, sum = 0
1613 09:29:07.804096 3, 0xFFFF, sum = 0
1614 09:29:07.804174 4, 0xFFFF, sum = 0
1615 09:29:07.807612 5, 0xFFFF, sum = 0
1616 09:29:07.807690 6, 0xFFFF, sum = 0
1617 09:29:07.810858 7, 0xFFFF, sum = 0
1618 09:29:07.810953 8, 0xFFFF, sum = 0
1619 09:29:07.813873 9, 0x0, sum = 1
1620 09:29:07.813974 10, 0x0, sum = 2
1621 09:29:07.817428 11, 0x0, sum = 3
1622 09:29:07.817505 12, 0x0, sum = 4
1623 09:29:07.820686 best_step = 10
1624 09:29:07.820762
1625 09:29:07.820821 ==
1626 09:29:07.824427 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 09:29:07.827508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 09:29:07.827585 ==
1629 09:29:07.830578 RX Vref Scan: 1
1630 09:29:07.830654
1631 09:29:07.830713 Set Vref Range= 32 -> 127
1632 09:29:07.830768
1633 09:29:07.833851 RX Vref 32 -> 127, step: 1
1634 09:29:07.833949
1635 09:29:07.837601 RX Delay -111 -> 252, step: 8
1636 09:29:07.837677
1637 09:29:07.840641 Set Vref, RX VrefLevel [Byte0]: 32
1638 09:29:07.843866 [Byte1]: 32
1639 09:29:07.843943
1640 09:29:07.847526 Set Vref, RX VrefLevel [Byte0]: 33
1641 09:29:07.850342 [Byte1]: 33
1642 09:29:07.854349
1643 09:29:07.854442 Set Vref, RX VrefLevel [Byte0]: 34
1644 09:29:07.857445 [Byte1]: 34
1645 09:29:07.861607
1646 09:29:07.861702 Set Vref, RX VrefLevel [Byte0]: 35
1647 09:29:07.865421 [Byte1]: 35
1648 09:29:07.869875
1649 09:29:07.869972 Set Vref, RX VrefLevel [Byte0]: 36
1650 09:29:07.872761 [Byte1]: 36
1651 09:29:07.877120
1652 09:29:07.877188 Set Vref, RX VrefLevel [Byte0]: 37
1653 09:29:07.880230 [Byte1]: 37
1654 09:29:07.884420
1655 09:29:07.884525 Set Vref, RX VrefLevel [Byte0]: 38
1656 09:29:07.887784 [Byte1]: 38
1657 09:29:07.892438
1658 09:29:07.892510 Set Vref, RX VrefLevel [Byte0]: 39
1659 09:29:07.895779 [Byte1]: 39
1660 09:29:07.900210
1661 09:29:07.900279 Set Vref, RX VrefLevel [Byte0]: 40
1662 09:29:07.903174 [Byte1]: 40
1663 09:29:07.907777
1664 09:29:07.907870 Set Vref, RX VrefLevel [Byte0]: 41
1665 09:29:07.910755 [Byte1]: 41
1666 09:29:07.915164
1667 09:29:07.915234 Set Vref, RX VrefLevel [Byte0]: 42
1668 09:29:07.918487 [Byte1]: 42
1669 09:29:07.923140
1670 09:29:07.923208 Set Vref, RX VrefLevel [Byte0]: 43
1671 09:29:07.926140 [Byte1]: 43
1672 09:29:07.930772
1673 09:29:07.930845 Set Vref, RX VrefLevel [Byte0]: 44
1674 09:29:07.933887 [Byte1]: 44
1675 09:29:07.938260
1676 09:29:07.938331 Set Vref, RX VrefLevel [Byte0]: 45
1677 09:29:07.941457 [Byte1]: 45
1678 09:29:07.945693
1679 09:29:07.945782 Set Vref, RX VrefLevel [Byte0]: 46
1680 09:29:07.949429 [Byte1]: 46
1681 09:29:07.953200
1682 09:29:07.953278 Set Vref, RX VrefLevel [Byte0]: 47
1683 09:29:07.956908 [Byte1]: 47
1684 09:29:07.960950
1685 09:29:07.961052 Set Vref, RX VrefLevel [Byte0]: 48
1686 09:29:07.964377 [Byte1]: 48
1687 09:29:07.968665
1688 09:29:07.968771 Set Vref, RX VrefLevel [Byte0]: 49
1689 09:29:07.972464 [Byte1]: 49
1690 09:29:07.976696
1691 09:29:07.976785 Set Vref, RX VrefLevel [Byte0]: 50
1692 09:29:07.979644 [Byte1]: 50
1693 09:29:07.984083
1694 09:29:07.984171 Set Vref, RX VrefLevel [Byte0]: 51
1695 09:29:07.987162 [Byte1]: 51
1696 09:29:07.991943
1697 09:29:07.992030 Set Vref, RX VrefLevel [Byte0]: 52
1698 09:29:07.994885 [Byte1]: 52
1699 09:29:07.999473
1700 09:29:07.999540 Set Vref, RX VrefLevel [Byte0]: 53
1701 09:29:08.002717 [Byte1]: 53
1702 09:29:08.006939
1703 09:29:08.007028 Set Vref, RX VrefLevel [Byte0]: 54
1704 09:29:08.010456 [Byte1]: 54
1705 09:29:08.014981
1706 09:29:08.015075 Set Vref, RX VrefLevel [Byte0]: 55
1707 09:29:08.017830 [Byte1]: 55
1708 09:29:08.022176
1709 09:29:08.022258 Set Vref, RX VrefLevel [Byte0]: 56
1710 09:29:08.025757 [Byte1]: 56
1711 09:29:08.030140
1712 09:29:08.030215 Set Vref, RX VrefLevel [Byte0]: 57
1713 09:29:08.033288 [Byte1]: 57
1714 09:29:08.037569
1715 09:29:08.037664 Set Vref, RX VrefLevel [Byte0]: 58
1716 09:29:08.040721 [Byte1]: 58
1717 09:29:08.045228
1718 09:29:08.045321 Set Vref, RX VrefLevel [Byte0]: 59
1719 09:29:08.048565 [Byte1]: 59
1720 09:29:08.052998
1721 09:29:08.053097 Set Vref, RX VrefLevel [Byte0]: 60
1722 09:29:08.056092 [Byte1]: 60
1723 09:29:08.060366
1724 09:29:08.060456 Set Vref, RX VrefLevel [Byte0]: 61
1725 09:29:08.063639 [Byte1]: 61
1726 09:29:08.068205
1727 09:29:08.068304 Set Vref, RX VrefLevel [Byte0]: 62
1728 09:29:08.071529 [Byte1]: 62
1729 09:29:08.075913
1730 09:29:08.076007 Set Vref, RX VrefLevel [Byte0]: 63
1731 09:29:08.079159 [Byte1]: 63
1732 09:29:08.083551
1733 09:29:08.083640 Set Vref, RX VrefLevel [Byte0]: 64
1734 09:29:08.086534 [Byte1]: 64
1735 09:29:08.090830
1736 09:29:08.090920 Set Vref, RX VrefLevel [Byte0]: 65
1737 09:29:08.094616 [Byte1]: 65
1738 09:29:08.098985
1739 09:29:08.099074 Set Vref, RX VrefLevel [Byte0]: 66
1740 09:29:08.102349 [Byte1]: 66
1741 09:29:08.106405
1742 09:29:08.106480 Set Vref, RX VrefLevel [Byte0]: 67
1743 09:29:08.109992 [Byte1]: 67
1744 09:29:08.114324
1745 09:29:08.114391 Set Vref, RX VrefLevel [Byte0]: 68
1746 09:29:08.117268 [Byte1]: 68
1747 09:29:08.121957
1748 09:29:08.122065 Set Vref, RX VrefLevel [Byte0]: 69
1749 09:29:08.125053 [Byte1]: 69
1750 09:29:08.129241
1751 09:29:08.129328 Set Vref, RX VrefLevel [Byte0]: 70
1752 09:29:08.132751 [Byte1]: 70
1753 09:29:08.137245
1754 09:29:08.137332 Set Vref, RX VrefLevel [Byte0]: 71
1755 09:29:08.140287 [Byte1]: 71
1756 09:29:08.144831
1757 09:29:08.144899 Set Vref, RX VrefLevel [Byte0]: 72
1758 09:29:08.147967 [Byte1]: 72
1759 09:29:08.152190
1760 09:29:08.152275 Set Vref, RX VrefLevel [Byte0]: 73
1761 09:29:08.155415 [Byte1]: 73
1762 09:29:08.159961
1763 09:29:08.160088 Set Vref, RX VrefLevel [Byte0]: 74
1764 09:29:08.163251 [Byte1]: 74
1765 09:29:08.167515
1766 09:29:08.167605 Set Vref, RX VrefLevel [Byte0]: 75
1767 09:29:08.170990 [Byte1]: 75
1768 09:29:08.175115
1769 09:29:08.178420 Set Vref, RX VrefLevel [Byte0]: 76
1770 09:29:08.178491 [Byte1]: 76
1771 09:29:08.182706
1772 09:29:08.182791 Set Vref, RX VrefLevel [Byte0]: 77
1773 09:29:08.186430 [Byte1]: 77
1774 09:29:08.190870
1775 09:29:08.190962 Set Vref, RX VrefLevel [Byte0]: 78
1776 09:29:08.194125 [Byte1]: 78
1777 09:29:08.198462
1778 09:29:08.198537 Set Vref, RX VrefLevel [Byte0]: 79
1779 09:29:08.201571 [Byte1]: 79
1780 09:29:08.205929
1781 09:29:08.206037 Final RX Vref Byte 0 = 58 to rank0
1782 09:29:08.209371 Final RX Vref Byte 1 = 60 to rank0
1783 09:29:08.212670 Final RX Vref Byte 0 = 58 to rank1
1784 09:29:08.215713 Final RX Vref Byte 1 = 60 to rank1==
1785 09:29:08.219450 Dram Type= 6, Freq= 0, CH_1, rank 0
1786 09:29:08.225560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1787 09:29:08.225660 ==
1788 09:29:08.225757 DQS Delay:
1789 09:29:08.225848 DQS0 = 0, DQS1 = 0
1790 09:29:08.229235 DQM Delay:
1791 09:29:08.229326 DQM0 = 83, DQM1 = 73
1792 09:29:08.232327 DQ Delay:
1793 09:29:08.236028 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1794 09:29:08.236121 DQ4 =84, DQ5 =92, DQ6 =92, DQ7 =76
1795 09:29:08.239212 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =72
1796 09:29:08.245673 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1797 09:29:08.245768
1798 09:29:08.245867
1799 09:29:08.252502 [DQSOSCAuto] RK0, (LSB)MR18= 0x2afe, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1800 09:29:08.255864 CH1 RK0: MR19=605, MR18=2AFE
1801 09:29:08.262528 CH1_RK0: MR19=0x605, MR18=0x2AFE, DQSOSC=399, MR23=63, INC=92, DEC=61
1802 09:29:08.262634
1803 09:29:08.265777 ----->DramcWriteLeveling(PI) begin...
1804 09:29:08.265871 ==
1805 09:29:08.269381 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 09:29:08.272766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 09:29:08.272860 ==
1808 09:29:08.276255 Write leveling (Byte 0): 28 => 28
1809 09:29:08.279069 Write leveling (Byte 1): 28 => 28
1810 09:29:08.282758 DramcWriteLeveling(PI) end<-----
1811 09:29:08.282829
1812 09:29:08.282903 ==
1813 09:29:08.286210 Dram Type= 6, Freq= 0, CH_1, rank 1
1814 09:29:08.289372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1815 09:29:08.289441 ==
1816 09:29:08.292824 [Gating] SW mode calibration
1817 09:29:08.299156 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1818 09:29:08.305798 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1819 09:29:08.309673 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1820 09:29:08.312704 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1821 09:29:08.319274 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 09:29:08.322817 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 09:29:08.326239 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 09:29:08.329304 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 09:29:08.336154 0 6 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1826 09:29:08.339808 0 6 28 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1827 09:29:08.342830 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 09:29:08.349664 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 09:29:08.352674 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 09:29:08.356431 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1831 09:29:08.362601 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 09:29:08.366395 0 7 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1833 09:29:08.369706 0 7 24 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
1834 09:29:08.375873 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1835 09:29:08.379522 0 8 0 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1836 09:29:08.382742 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1837 09:29:08.389540 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 09:29:08.393124 0 8 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1839 09:29:08.396096 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1840 09:29:08.402658 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 09:29:08.406353 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 09:29:08.409376 0 8 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1843 09:29:08.416059 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 09:29:08.419586 0 9 4 | B1->B0 | 2423 2b2b | 1 1 | (0 0) (1 1)
1845 09:29:08.422905 0 9 8 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
1846 09:29:08.426455 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1847 09:29:08.432711 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1848 09:29:08.436478 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 09:29:08.439571 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1850 09:29:08.446420 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1851 09:29:08.449517 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 09:29:08.453268 0 10 4 | B1->B0 | 3232 2e2e | 1 0 | (0 0) (0 0)
1853 09:29:08.460151 0 10 8 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
1854 09:29:08.463087 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 09:29:08.466156 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 09:29:08.472766 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 09:29:08.476315 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 09:29:08.479748 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 09:29:08.486200 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1860 09:29:08.489797 0 11 4 | B1->B0 | 2a2a 3939 | 0 0 | (0 0) (1 1)
1861 09:29:08.492900 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
1862 09:29:08.499593 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 09:29:08.503153 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1864 09:29:08.506206 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 09:29:08.513106 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 09:29:08.516258 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 09:29:08.519784 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 09:29:08.522761 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1869 09:29:08.529780 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1870 09:29:08.532814 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 09:29:08.536442 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 09:29:08.542757 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 09:29:08.546739 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 09:29:08.549312 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 09:29:08.555969 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 09:29:08.559822 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 09:29:08.562984 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 09:29:08.569748 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 09:29:08.572886 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 09:29:08.575959 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 09:29:08.582701 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 09:29:08.586361 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 09:29:08.589830 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 09:29:08.596604 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1885 09:29:08.599768 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 09:29:08.603022 Total UI for P1: 0, mck2ui 16
1887 09:29:08.606690 best dqsien dly found for B0: ( 0, 14, 4)
1888 09:29:08.609714 Total UI for P1: 0, mck2ui 16
1889 09:29:08.612927 best dqsien dly found for B1: ( 0, 14, 4)
1890 09:29:08.616565 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1891 09:29:08.619684 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1892 09:29:08.619760
1893 09:29:08.623213 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1894 09:29:08.626421 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1895 09:29:08.629680 [Gating] SW calibration Done
1896 09:29:08.629757 ==
1897 09:29:08.633321 Dram Type= 6, Freq= 0, CH_1, rank 1
1898 09:29:08.636561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1899 09:29:08.636638 ==
1900 09:29:08.639417 RX Vref Scan: 0
1901 09:29:08.639493
1902 09:29:08.639552 RX Vref 0 -> 0, step: 1
1903 09:29:08.642817
1904 09:29:08.642892 RX Delay -130 -> 252, step: 16
1905 09:29:08.649788 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1906 09:29:08.652760 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1907 09:29:08.656199 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1908 09:29:08.659621 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1909 09:29:08.662815 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1910 09:29:08.669785 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1911 09:29:08.673046 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1912 09:29:08.676434 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1913 09:29:08.679298 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1914 09:29:08.682948 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1915 09:29:08.689795 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1916 09:29:08.692968 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1917 09:29:08.696559 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1918 09:29:08.699471 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1919 09:29:08.702862 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1920 09:29:08.709872 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1921 09:29:08.709951 ==
1922 09:29:08.713001 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 09:29:08.716169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 09:29:08.716246 ==
1925 09:29:08.716306 DQS Delay:
1926 09:29:08.719826 DQS0 = 0, DQS1 = 0
1927 09:29:08.719902 DQM Delay:
1928 09:29:08.723108 DQM0 = 81, DQM1 = 78
1929 09:29:08.723184 DQ Delay:
1930 09:29:08.726258 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1931 09:29:08.729889 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1932 09:29:08.733064 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1933 09:29:08.736231 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1934 09:29:08.736307
1935 09:29:08.736367
1936 09:29:08.736421 ==
1937 09:29:08.740063 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 09:29:08.743112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 09:29:08.743188 ==
1940 09:29:08.743248
1941 09:29:08.743302
1942 09:29:08.746538 TX Vref Scan disable
1943 09:29:08.749773 == TX Byte 0 ==
1944 09:29:08.752899 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1945 09:29:08.756086 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1946 09:29:08.759810 == TX Byte 1 ==
1947 09:29:08.762993 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1948 09:29:08.766542 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1949 09:29:08.766618 ==
1950 09:29:08.769766 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 09:29:08.772844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 09:29:08.776360 ==
1953 09:29:08.787740 TX Vref=22, minBit 1, minWin=27, winSum=443
1954 09:29:08.790712 TX Vref=24, minBit 1, minWin=27, winSum=444
1955 09:29:08.794000 TX Vref=26, minBit 10, minWin=27, winSum=447
1956 09:29:08.797774 TX Vref=28, minBit 0, minWin=28, winSum=449
1957 09:29:08.800729 TX Vref=30, minBit 0, minWin=28, winSum=451
1958 09:29:08.807517 TX Vref=32, minBit 0, minWin=28, winSum=454
1959 09:29:08.810698 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1960 09:29:08.810795
1961 09:29:08.814366 Final TX Range 1 Vref 32
1962 09:29:08.814441
1963 09:29:08.814516 ==
1964 09:29:08.817694 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 09:29:08.820895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 09:29:08.821001 ==
1967 09:29:08.821093
1968 09:29:08.824142
1969 09:29:08.824235 TX Vref Scan disable
1970 09:29:08.827374 == TX Byte 0 ==
1971 09:29:08.831191 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1972 09:29:08.837332 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1973 09:29:08.837400 == TX Byte 1 ==
1974 09:29:08.840519 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1975 09:29:08.847281 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1976 09:29:08.847374
1977 09:29:08.847465 [DATLAT]
1978 09:29:08.847553 Freq=800, CH1 RK1
1979 09:29:08.847641
1980 09:29:08.851029 DATLAT Default: 0xa
1981 09:29:08.851096 0, 0xFFFF, sum = 0
1982 09:29:08.854121 1, 0xFFFF, sum = 0
1983 09:29:08.854219 2, 0xFFFF, sum = 0
1984 09:29:08.857420 3, 0xFFFF, sum = 0
1985 09:29:08.857513 4, 0xFFFF, sum = 0
1986 09:29:08.860626 5, 0xFFFF, sum = 0
1987 09:29:08.864277 6, 0xFFFF, sum = 0
1988 09:29:08.864364 7, 0xFFFF, sum = 0
1989 09:29:08.867507 8, 0xFFFF, sum = 0
1990 09:29:08.867572 9, 0x0, sum = 1
1991 09:29:08.867651 10, 0x0, sum = 2
1992 09:29:08.871075 11, 0x0, sum = 3
1993 09:29:08.871140 12, 0x0, sum = 4
1994 09:29:08.874346 best_step = 10
1995 09:29:08.874408
1996 09:29:08.874478 ==
1997 09:29:08.877474 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 09:29:08.881003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 09:29:08.881088 ==
2000 09:29:08.884017 RX Vref Scan: 0
2001 09:29:08.884105
2002 09:29:08.884185 RX Vref 0 -> 0, step: 1
2003 09:29:08.884263
2004 09:29:08.887285 RX Delay -95 -> 252, step: 8
2005 09:29:08.894260 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2006 09:29:08.897283 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2007 09:29:08.901097 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2008 09:29:08.904096 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2009 09:29:08.907684 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
2010 09:29:08.914218 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
2011 09:29:08.917547 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2012 09:29:08.920987 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2013 09:29:08.924032 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2014 09:29:08.927766 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2015 09:29:08.934299 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2016 09:29:08.937478 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2017 09:29:08.940786 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2018 09:29:08.944487 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2019 09:29:08.947513 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2020 09:29:08.954346 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2021 09:29:08.954419 ==
2022 09:29:08.957480 Dram Type= 6, Freq= 0, CH_1, rank 1
2023 09:29:08.961188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2024 09:29:08.961258 ==
2025 09:29:08.961320 DQS Delay:
2026 09:29:08.964590 DQS0 = 0, DQS1 = 0
2027 09:29:08.964677 DQM Delay:
2028 09:29:08.968046 DQM0 = 80, DQM1 = 76
2029 09:29:08.968146 DQ Delay:
2030 09:29:08.971206 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2031 09:29:08.974268 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
2032 09:29:08.978090 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2033 09:29:08.981135 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2034 09:29:08.981222
2035 09:29:08.981313
2036 09:29:08.988004 [DQSOSCAuto] RK1, (LSB)MR18= 0x222d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2037 09:29:08.991096 CH1 RK1: MR19=606, MR18=222D
2038 09:29:08.997902 CH1_RK1: MR19=0x606, MR18=0x222D, DQSOSC=398, MR23=63, INC=93, DEC=62
2039 09:29:09.001237 [RxdqsGatingPostProcess] freq 800
2040 09:29:09.008059 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2041 09:29:09.008159 Pre-setting of DQS Precalculation
2042 09:29:09.014813 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2043 09:29:09.021319 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2044 09:29:09.027740 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2045 09:29:09.027849
2046 09:29:09.027937
2047 09:29:09.031448 [Calibration Summary] 1600 Mbps
2048 09:29:09.034248 CH 0, Rank 0
2049 09:29:09.034323 SW Impedance : PASS
2050 09:29:09.037670 DUTY Scan : NO K
2051 09:29:09.041162 ZQ Calibration : PASS
2052 09:29:09.041238 Jitter Meter : NO K
2053 09:29:09.044919 CBT Training : PASS
2054 09:29:09.045015 Write leveling : PASS
2055 09:29:09.047779 RX DQS gating : PASS
2056 09:29:09.051143 RX DQ/DQS(RDDQC) : PASS
2057 09:29:09.051239 TX DQ/DQS : PASS
2058 09:29:09.055002 RX DATLAT : PASS
2059 09:29:09.057793 RX DQ/DQS(Engine): PASS
2060 09:29:09.057942 TX OE : NO K
2061 09:29:09.061396 All Pass.
2062 09:29:09.061514
2063 09:29:09.061575 CH 0, Rank 1
2064 09:29:09.064447 SW Impedance : PASS
2065 09:29:09.064530 DUTY Scan : NO K
2066 09:29:09.068162 ZQ Calibration : PASS
2067 09:29:09.071588 Jitter Meter : NO K
2068 09:29:09.071670 CBT Training : PASS
2069 09:29:09.074269 Write leveling : PASS
2070 09:29:09.078137 RX DQS gating : PASS
2071 09:29:09.078214 RX DQ/DQS(RDDQC) : PASS
2072 09:29:09.081211 TX DQ/DQS : PASS
2073 09:29:09.081289 RX DATLAT : PASS
2074 09:29:09.084820 RX DQ/DQS(Engine): PASS
2075 09:29:09.087964 TX OE : NO K
2076 09:29:09.088042 All Pass.
2077 09:29:09.088101
2078 09:29:09.088157 CH 1, Rank 0
2079 09:29:09.091042 SW Impedance : PASS
2080 09:29:09.094739 DUTY Scan : NO K
2081 09:29:09.094816 ZQ Calibration : PASS
2082 09:29:09.097839 Jitter Meter : NO K
2083 09:29:09.101535 CBT Training : PASS
2084 09:29:09.101613 Write leveling : PASS
2085 09:29:09.104495 RX DQS gating : PASS
2086 09:29:09.107989 RX DQ/DQS(RDDQC) : PASS
2087 09:29:09.108067 TX DQ/DQS : PASS
2088 09:29:09.111239 RX DATLAT : PASS
2089 09:29:09.115039 RX DQ/DQS(Engine): PASS
2090 09:29:09.115116 TX OE : NO K
2091 09:29:09.115177 All Pass.
2092 09:29:09.115233
2093 09:29:09.117986 CH 1, Rank 1
2094 09:29:09.121664 SW Impedance : PASS
2095 09:29:09.121740 DUTY Scan : NO K
2096 09:29:09.124599 ZQ Calibration : PASS
2097 09:29:09.124695 Jitter Meter : NO K
2098 09:29:09.128118 CBT Training : PASS
2099 09:29:09.131561 Write leveling : PASS
2100 09:29:09.131639 RX DQS gating : PASS
2101 09:29:09.135194 RX DQ/DQS(RDDQC) : PASS
2102 09:29:09.138309 TX DQ/DQS : PASS
2103 09:29:09.138386 RX DATLAT : PASS
2104 09:29:09.141228 RX DQ/DQS(Engine): PASS
2105 09:29:09.144646 TX OE : NO K
2106 09:29:09.144724 All Pass.
2107 09:29:09.144783
2108 09:29:09.144838 DramC Write-DBI off
2109 09:29:09.148366 PER_BANK_REFRESH: Hybrid Mode
2110 09:29:09.151522 TX_TRACKING: ON
2111 09:29:09.154556 [GetDramInforAfterCalByMRR] Vendor 6.
2112 09:29:09.158313 [GetDramInforAfterCalByMRR] Revision 606.
2113 09:29:09.161695 [GetDramInforAfterCalByMRR] Revision 2 0.
2114 09:29:09.161787 MR0 0x3b3b
2115 09:29:09.164595 MR8 0x5151
2116 09:29:09.168397 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2117 09:29:09.168489
2118 09:29:09.168572 MR0 0x3b3b
2119 09:29:09.168651 MR8 0x5151
2120 09:29:09.171779 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2121 09:29:09.171874
2122 09:29:09.181615 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2123 09:29:09.184820 [FAST_K] Save calibration result to emmc
2124 09:29:09.188499 [FAST_K] Save calibration result to emmc
2125 09:29:09.191699 dram_init: config_dvfs: 1
2126 09:29:09.195170 dramc_set_vcore_voltage set vcore to 662500
2127 09:29:09.198317 Read voltage for 1200, 2
2128 09:29:09.198408 Vio18 = 0
2129 09:29:09.201400 Vcore = 662500
2130 09:29:09.201497 Vdram = 0
2131 09:29:09.201587 Vddq = 0
2132 09:29:09.201667 Vmddr = 0
2133 09:29:09.208266 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2134 09:29:09.212029 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2135 09:29:09.214921 MEM_TYPE=3, freq_sel=15
2136 09:29:09.218550 sv_algorithm_assistance_LP4_1600
2137 09:29:09.221752 ============ PULL DRAM RESETB DOWN ============
2138 09:29:09.228078 ========== PULL DRAM RESETB DOWN end =========
2139 09:29:09.231852 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2140 09:29:09.234748 ===================================
2141 09:29:09.238134 LPDDR4 DRAM CONFIGURATION
2142 09:29:09.241478 ===================================
2143 09:29:09.241557 EX_ROW_EN[0] = 0x0
2144 09:29:09.245100 EX_ROW_EN[1] = 0x0
2145 09:29:09.245178 LP4Y_EN = 0x0
2146 09:29:09.248037 WORK_FSP = 0x0
2147 09:29:09.248114 WL = 0x4
2148 09:29:09.251603 RL = 0x4
2149 09:29:09.251680 BL = 0x2
2150 09:29:09.254773 RPST = 0x0
2151 09:29:09.254850 RD_PRE = 0x0
2152 09:29:09.258456 WR_PRE = 0x1
2153 09:29:09.258576 WR_PST = 0x0
2154 09:29:09.261460 DBI_WR = 0x0
2155 09:29:09.261553 DBI_RD = 0x0
2156 09:29:09.265226 OTF = 0x1
2157 09:29:09.268138 ===================================
2158 09:29:09.271938 ===================================
2159 09:29:09.272016 ANA top config
2160 09:29:09.274910 ===================================
2161 09:29:09.278390 DLL_ASYNC_EN = 0
2162 09:29:09.281446 ALL_SLAVE_EN = 0
2163 09:29:09.284873 NEW_RANK_MODE = 1
2164 09:29:09.284951 DLL_IDLE_MODE = 1
2165 09:29:09.288236 LP45_APHY_COMB_EN = 1
2166 09:29:09.291571 TX_ODT_DIS = 1
2167 09:29:09.295423 NEW_8X_MODE = 1
2168 09:29:09.298476 ===================================
2169 09:29:09.301675 ===================================
2170 09:29:09.305376 data_rate = 2400
2171 09:29:09.305454 CKR = 1
2172 09:29:09.308526 DQ_P2S_RATIO = 8
2173 09:29:09.311648 ===================================
2174 09:29:09.315199 CA_P2S_RATIO = 8
2175 09:29:09.318426 DQ_CA_OPEN = 0
2176 09:29:09.321505 DQ_SEMI_OPEN = 0
2177 09:29:09.325201 CA_SEMI_OPEN = 0
2178 09:29:09.325279 CA_FULL_RATE = 0
2179 09:29:09.328534 DQ_CKDIV4_EN = 0
2180 09:29:09.331439 CA_CKDIV4_EN = 0
2181 09:29:09.335285 CA_PREDIV_EN = 0
2182 09:29:09.338231 PH8_DLY = 17
2183 09:29:09.341582 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2184 09:29:09.341690 DQ_AAMCK_DIV = 4
2185 09:29:09.345081 CA_AAMCK_DIV = 4
2186 09:29:09.348452 CA_ADMCK_DIV = 4
2187 09:29:09.351933 DQ_TRACK_CA_EN = 0
2188 09:29:09.354784 CA_PICK = 1200
2189 09:29:09.358393 CA_MCKIO = 1200
2190 09:29:09.358472 MCKIO_SEMI = 0
2191 09:29:09.361426 PLL_FREQ = 2366
2192 09:29:09.365099 DQ_UI_PI_RATIO = 32
2193 09:29:09.368339 CA_UI_PI_RATIO = 0
2194 09:29:09.372027 ===================================
2195 09:29:09.375296 ===================================
2196 09:29:09.378494 memory_type:LPDDR4
2197 09:29:09.378572 GP_NUM : 10
2198 09:29:09.381607 SRAM_EN : 1
2199 09:29:09.385360 MD32_EN : 0
2200 09:29:09.388227 ===================================
2201 09:29:09.388304 [ANA_INIT] >>>>>>>>>>>>>>
2202 09:29:09.391788 <<<<<< [CONFIGURE PHASE]: ANA_TX
2203 09:29:09.395193 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2204 09:29:09.398490 ===================================
2205 09:29:09.401617 data_rate = 2400,PCW = 0X5b00
2206 09:29:09.405227 ===================================
2207 09:29:09.408151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2208 09:29:09.415201 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2209 09:29:09.418218 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2210 09:29:09.424910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2211 09:29:09.428695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2212 09:29:09.431725 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2213 09:29:09.431803 [ANA_INIT] flow start
2214 09:29:09.434918 [ANA_INIT] PLL >>>>>>>>
2215 09:29:09.438496 [ANA_INIT] PLL <<<<<<<<
2216 09:29:09.438574 [ANA_INIT] MIDPI >>>>>>>>
2217 09:29:09.441560 [ANA_INIT] MIDPI <<<<<<<<
2218 09:29:09.444953 [ANA_INIT] DLL >>>>>>>>
2219 09:29:09.445057 [ANA_INIT] DLL <<<<<<<<
2220 09:29:09.448281 [ANA_INIT] flow end
2221 09:29:09.451939 ============ LP4 DIFF to SE enter ============
2222 09:29:09.458580 ============ LP4 DIFF to SE exit ============
2223 09:29:09.458660 [ANA_INIT] <<<<<<<<<<<<<
2224 09:29:09.461719 [Flow] Enable top DCM control >>>>>
2225 09:29:09.465385 [Flow] Enable top DCM control <<<<<
2226 09:29:09.468363 Enable DLL master slave shuffle
2227 09:29:09.475334 ==============================================================
2228 09:29:09.475413 Gating Mode config
2229 09:29:09.481975 ==============================================================
2230 09:29:09.482076 Config description:
2231 09:29:09.491754 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2232 09:29:09.498369 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2233 09:29:09.505194 SELPH_MODE 0: By rank 1: By Phase
2234 09:29:09.508617 ==============================================================
2235 09:29:09.511946 GAT_TRACK_EN = 1
2236 09:29:09.515178 RX_GATING_MODE = 2
2237 09:29:09.518803 RX_GATING_TRACK_MODE = 2
2238 09:29:09.521827 SELPH_MODE = 1
2239 09:29:09.525557 PICG_EARLY_EN = 1
2240 09:29:09.528671 VALID_LAT_VALUE = 1
2241 09:29:09.535413 ==============================================================
2242 09:29:09.538687 Enter into Gating configuration >>>>
2243 09:29:09.541564 Exit from Gating configuration <<<<
2244 09:29:09.545377 Enter into DVFS_PRE_config >>>>>
2245 09:29:09.555333 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2246 09:29:09.558361 Exit from DVFS_PRE_config <<<<<
2247 09:29:09.561693 Enter into PICG configuration >>>>
2248 09:29:09.565209 Exit from PICG configuration <<<<
2249 09:29:09.565286 [RX_INPUT] configuration >>>>>
2250 09:29:09.568549 [RX_INPUT] configuration <<<<<
2251 09:29:09.574975 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2252 09:29:09.578151 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2253 09:29:09.584739 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2254 09:29:09.591890 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2255 09:29:09.598567 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 09:29:09.605124 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 09:29:09.608342 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2258 09:29:09.612030 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2259 09:29:09.618602 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2260 09:29:09.621492 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2261 09:29:09.625387 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2262 09:29:09.628210 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2263 09:29:09.631709 ===================================
2264 09:29:09.634849 LPDDR4 DRAM CONFIGURATION
2265 09:29:09.638587 ===================================
2266 09:29:09.641842 EX_ROW_EN[0] = 0x0
2267 09:29:09.641918 EX_ROW_EN[1] = 0x0
2268 09:29:09.644844 LP4Y_EN = 0x0
2269 09:29:09.644921 WORK_FSP = 0x0
2270 09:29:09.648649 WL = 0x4
2271 09:29:09.648725 RL = 0x4
2272 09:29:09.651698 BL = 0x2
2273 09:29:09.651774 RPST = 0x0
2274 09:29:09.655423 RD_PRE = 0x0
2275 09:29:09.655500 WR_PRE = 0x1
2276 09:29:09.658820 WR_PST = 0x0
2277 09:29:09.658897 DBI_WR = 0x0
2278 09:29:09.661868 DBI_RD = 0x0
2279 09:29:09.662028 OTF = 0x1
2280 09:29:09.665336 ===================================
2281 09:29:09.671509 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2282 09:29:09.675128 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2283 09:29:09.678407 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2284 09:29:09.681947 ===================================
2285 09:29:09.685718 LPDDR4 DRAM CONFIGURATION
2286 09:29:09.688678 ===================================
2287 09:29:09.688755 EX_ROW_EN[0] = 0x10
2288 09:29:09.692292 EX_ROW_EN[1] = 0x0
2289 09:29:09.695372 LP4Y_EN = 0x0
2290 09:29:09.695449 WORK_FSP = 0x0
2291 09:29:09.698435 WL = 0x4
2292 09:29:09.698511 RL = 0x4
2293 09:29:09.701570 BL = 0x2
2294 09:29:09.701675 RPST = 0x0
2295 09:29:09.705128 RD_PRE = 0x0
2296 09:29:09.705205 WR_PRE = 0x1
2297 09:29:09.708476 WR_PST = 0x0
2298 09:29:09.708553 DBI_WR = 0x0
2299 09:29:09.711927 DBI_RD = 0x0
2300 09:29:09.712004 OTF = 0x1
2301 09:29:09.715423 ===================================
2302 09:29:09.722196 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2303 09:29:09.722273 ==
2304 09:29:09.725164 Dram Type= 6, Freq= 0, CH_0, rank 0
2305 09:29:09.728722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2306 09:29:09.728800 ==
2307 09:29:09.732054 [Duty_Offset_Calibration]
2308 09:29:09.735388 B0:2 B1:-1 CA:1
2309 09:29:09.735466
2310 09:29:09.738190 [DutyScan_Calibration_Flow] k_type=0
2311 09:29:09.746196
2312 09:29:09.746275 ==CLK 0==
2313 09:29:09.749291 Final CLK duty delay cell = -4
2314 09:29:09.752395 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2315 09:29:09.756228 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2316 09:29:09.759211 [-4] AVG Duty = 4953%(X100)
2317 09:29:09.759280
2318 09:29:09.762867 CH0 CLK Duty spec in!! Max-Min= 156%
2319 09:29:09.766061 [DutyScan_Calibration_Flow] ====Done====
2320 09:29:09.766128
2321 09:29:09.769595 [DutyScan_Calibration_Flow] k_type=1
2322 09:29:09.784708
2323 09:29:09.784791 ==DQS 0 ==
2324 09:29:09.788182 Final DQS duty delay cell = 0
2325 09:29:09.791346 [0] MAX Duty = 5156%(X100), DQS PI = 46
2326 09:29:09.794990 [0] MIN Duty = 5000%(X100), DQS PI = 12
2327 09:29:09.798136 [0] AVG Duty = 5078%(X100)
2328 09:29:09.798210
2329 09:29:09.798268 ==DQS 1 ==
2330 09:29:09.801924 Final DQS duty delay cell = -4
2331 09:29:09.804944 [-4] MAX Duty = 5093%(X100), DQS PI = 18
2332 09:29:09.808351 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2333 09:29:09.811591 [-4] AVG Duty = 5046%(X100)
2334 09:29:09.811666
2335 09:29:09.814727 CH0 DQS 0 Duty spec in!! Max-Min= 156%
2336 09:29:09.814800
2337 09:29:09.818074 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2338 09:29:09.821594 [DutyScan_Calibration_Flow] ====Done====
2339 09:29:09.821666
2340 09:29:09.824954 [DutyScan_Calibration_Flow] k_type=3
2341 09:29:09.841917
2342 09:29:09.842016 ==DQM 0 ==
2343 09:29:09.845308 Final DQM duty delay cell = 0
2344 09:29:09.848258 [0] MAX Duty = 4969%(X100), DQS PI = 28
2345 09:29:09.851827 [0] MIN Duty = 4907%(X100), DQS PI = 2
2346 09:29:09.851898 [0] AVG Duty = 4938%(X100)
2347 09:29:09.854902
2348 09:29:09.854970 ==DQM 1 ==
2349 09:29:09.858658 Final DQM duty delay cell = 0
2350 09:29:09.861739 [0] MAX Duty = 5124%(X100), DQS PI = 32
2351 09:29:09.864940 [0] MIN Duty = 4969%(X100), DQS PI = 10
2352 09:29:09.865008 [0] AVG Duty = 5046%(X100)
2353 09:29:09.868579
2354 09:29:09.871647 CH0 DQM 0 Duty spec in!! Max-Min= 62%
2355 09:29:09.871715
2356 09:29:09.875287 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2357 09:29:09.878446 [DutyScan_Calibration_Flow] ====Done====
2358 09:29:09.878526
2359 09:29:09.881531 [DutyScan_Calibration_Flow] k_type=2
2360 09:29:09.897091
2361 09:29:09.897163 ==DQ 0 ==
2362 09:29:09.901024 Final DQ duty delay cell = -4
2363 09:29:09.903967 [-4] MAX Duty = 5031%(X100), DQS PI = 40
2364 09:29:09.907535 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2365 09:29:09.910863 [-4] AVG Duty = 4937%(X100)
2366 09:29:09.910930
2367 09:29:09.910988 ==DQ 1 ==
2368 09:29:09.914524 Final DQ duty delay cell = 0
2369 09:29:09.917437 [0] MAX Duty = 5031%(X100), DQS PI = 18
2370 09:29:09.920914 [0] MIN Duty = 4907%(X100), DQS PI = 46
2371 09:29:09.920984 [0] AVG Duty = 4969%(X100)
2372 09:29:09.924474
2373 09:29:09.927317 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2374 09:29:09.927386
2375 09:29:09.931110 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2376 09:29:09.933937 [DutyScan_Calibration_Flow] ====Done====
2377 09:29:09.934069 ==
2378 09:29:09.937550 Dram Type= 6, Freq= 0, CH_1, rank 0
2379 09:29:09.940821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2380 09:29:09.940895 ==
2381 09:29:09.944373 [Duty_Offset_Calibration]
2382 09:29:09.944465 B0:1 B1:1 CA:2
2383 09:29:09.944559
2384 09:29:09.947514 [DutyScan_Calibration_Flow] k_type=0
2385 09:29:09.957570
2386 09:29:09.957645 ==CLK 0==
2387 09:29:09.961143 Final CLK duty delay cell = 0
2388 09:29:09.964167 [0] MAX Duty = 5156%(X100), DQS PI = 24
2389 09:29:09.967934 [0] MIN Duty = 4938%(X100), DQS PI = 42
2390 09:29:09.968005 [0] AVG Duty = 5047%(X100)
2391 09:29:09.971093
2392 09:29:09.974593 CH1 CLK Duty spec in!! Max-Min= 218%
2393 09:29:09.977563 [DutyScan_Calibration_Flow] ====Done====
2394 09:29:09.977643
2395 09:29:09.980669 [DutyScan_Calibration_Flow] k_type=1
2396 09:29:09.997098
2397 09:29:09.997173 ==DQS 0 ==
2398 09:29:10.000477 Final DQS duty delay cell = 0
2399 09:29:10.003548 [0] MAX Duty = 5031%(X100), DQS PI = 18
2400 09:29:10.007228 [0] MIN Duty = 4844%(X100), DQS PI = 42
2401 09:29:10.010336 [0] AVG Duty = 4937%(X100)
2402 09:29:10.010409
2403 09:29:10.010469 ==DQS 1 ==
2404 09:29:10.013905 Final DQS duty delay cell = 0
2405 09:29:10.017191 [0] MAX Duty = 5062%(X100), DQS PI = 36
2406 09:29:10.020243 [0] MIN Duty = 4907%(X100), DQS PI = 14
2407 09:29:10.023946 [0] AVG Duty = 4984%(X100)
2408 09:29:10.024014
2409 09:29:10.026969 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2410 09:29:10.027037
2411 09:29:10.030488 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2412 09:29:10.033757 [DutyScan_Calibration_Flow] ====Done====
2413 09:29:10.033822
2414 09:29:10.036829 [DutyScan_Calibration_Flow] k_type=3
2415 09:29:10.053411
2416 09:29:10.053494 ==DQM 0 ==
2417 09:29:10.057115 Final DQM duty delay cell = 0
2418 09:29:10.060104 [0] MAX Duty = 5093%(X100), DQS PI = 16
2419 09:29:10.063868 [0] MIN Duty = 4875%(X100), DQS PI = 48
2420 09:29:10.066814 [0] AVG Duty = 4984%(X100)
2421 09:29:10.066891
2422 09:29:10.066951 ==DQM 1 ==
2423 09:29:10.070265 Final DQM duty delay cell = 0
2424 09:29:10.073871 [0] MAX Duty = 5125%(X100), DQS PI = 0
2425 09:29:10.077055 [0] MIN Duty = 4969%(X100), DQS PI = 4
2426 09:29:10.077133 [0] AVG Duty = 5047%(X100)
2427 09:29:10.080224
2428 09:29:10.083806 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2429 09:29:10.083897
2430 09:29:10.086980 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2431 09:29:10.090242 [DutyScan_Calibration_Flow] ====Done====
2432 09:29:10.090320
2433 09:29:10.093709 [DutyScan_Calibration_Flow] k_type=2
2434 09:29:10.109821
2435 09:29:10.109940 ==DQ 0 ==
2436 09:29:10.113404 Final DQ duty delay cell = 0
2437 09:29:10.116846 [0] MAX Duty = 5124%(X100), DQS PI = 18
2438 09:29:10.119938 [0] MIN Duty = 4907%(X100), DQS PI = 50
2439 09:29:10.120046 [0] AVG Duty = 5015%(X100)
2440 09:29:10.123117
2441 09:29:10.123195 ==DQ 1 ==
2442 09:29:10.126611 Final DQ duty delay cell = 0
2443 09:29:10.129861 [0] MAX Duty = 5093%(X100), DQS PI = 10
2444 09:29:10.133439 [0] MIN Duty = 5000%(X100), DQS PI = 50
2445 09:29:10.133517 [0] AVG Duty = 5046%(X100)
2446 09:29:10.133577
2447 09:29:10.137030 CH1 DQ 0 Duty spec in!! Max-Min= 217%
2448 09:29:10.137108
2449 09:29:10.139801 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2450 09:29:10.147020 [DutyScan_Calibration_Flow] ====Done====
2451 09:29:10.150172 nWR fixed to 30
2452 09:29:10.150250 [ModeRegInit_LP4] CH0 RK0
2453 09:29:10.153167 [ModeRegInit_LP4] CH0 RK1
2454 09:29:10.156870 [ModeRegInit_LP4] CH1 RK0
2455 09:29:10.156949 [ModeRegInit_LP4] CH1 RK1
2456 09:29:10.160291 match AC timing 7
2457 09:29:10.163627 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2458 09:29:10.166666 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2459 09:29:10.173526 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2460 09:29:10.176884 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2461 09:29:10.183440 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2462 09:29:10.183517 ==
2463 09:29:10.187057 Dram Type= 6, Freq= 0, CH_0, rank 0
2464 09:29:10.190114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2465 09:29:10.190192 ==
2466 09:29:10.196970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2467 09:29:10.200065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2468 09:29:10.209725 [CA 0] Center 40 (10~71) winsize 62
2469 09:29:10.213136 [CA 1] Center 39 (9~70) winsize 62
2470 09:29:10.216937 [CA 2] Center 36 (6~67) winsize 62
2471 09:29:10.219895 [CA 3] Center 35 (5~66) winsize 62
2472 09:29:10.223103 [CA 4] Center 34 (4~65) winsize 62
2473 09:29:10.226772 [CA 5] Center 34 (4~64) winsize 61
2474 09:29:10.226850
2475 09:29:10.229784 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2476 09:29:10.229862
2477 09:29:10.233377 [CATrainingPosCal] consider 1 rank data
2478 09:29:10.237166 u2DelayCellTimex100 = 270/100 ps
2479 09:29:10.240151 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2480 09:29:10.243940 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2481 09:29:10.250022 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2482 09:29:10.253722 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2483 09:29:10.256798 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2484 09:29:10.260427 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2485 09:29:10.260528
2486 09:29:10.263472 CA PerBit enable=1, Macro0, CA PI delay=34
2487 09:29:10.263550
2488 09:29:10.267044 [CBTSetCACLKResult] CA Dly = 34
2489 09:29:10.267122 CS Dly: 7 (0~38)
2490 09:29:10.267215 ==
2491 09:29:10.270162 Dram Type= 6, Freq= 0, CH_0, rank 1
2492 09:29:10.277352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2493 09:29:10.277431 ==
2494 09:29:10.280312 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2495 09:29:10.286812 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2496 09:29:10.296037 [CA 0] Center 39 (9~70) winsize 62
2497 09:29:10.299740 [CA 1] Center 39 (9~70) winsize 62
2498 09:29:10.302780 [CA 2] Center 36 (6~67) winsize 62
2499 09:29:10.305918 [CA 3] Center 36 (5~67) winsize 63
2500 09:29:10.309815 [CA 4] Center 34 (4~65) winsize 62
2501 09:29:10.312784 [CA 5] Center 34 (4~64) winsize 61
2502 09:29:10.312884
2503 09:29:10.316280 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2504 09:29:10.316357
2505 09:29:10.319641 [CATrainingPosCal] consider 2 rank data
2506 09:29:10.322729 u2DelayCellTimex100 = 270/100 ps
2507 09:29:10.326392 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2508 09:29:10.329489 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2509 09:29:10.336123 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2510 09:29:10.339163 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2511 09:29:10.342976 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2512 09:29:10.346085 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2513 09:29:10.346208
2514 09:29:10.349217 CA PerBit enable=1, Macro0, CA PI delay=34
2515 09:29:10.349295
2516 09:29:10.352770 [CBTSetCACLKResult] CA Dly = 34
2517 09:29:10.352849 CS Dly: 8 (0~41)
2518 09:29:10.352911
2519 09:29:10.356026 ----->DramcWriteLeveling(PI) begin...
2520 09:29:10.359694 ==
2521 09:29:10.359773 Dram Type= 6, Freq= 0, CH_0, rank 0
2522 09:29:10.366342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2523 09:29:10.366421 ==
2524 09:29:10.369587 Write leveling (Byte 0): 32 => 32
2525 09:29:10.372719 Write leveling (Byte 1): 29 => 29
2526 09:29:10.372821 DramcWriteLeveling(PI) end<-----
2527 09:29:10.376137
2528 09:29:10.376238 ==
2529 09:29:10.379656 Dram Type= 6, Freq= 0, CH_0, rank 0
2530 09:29:10.382944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 09:29:10.383076 ==
2532 09:29:10.386036 [Gating] SW mode calibration
2533 09:29:10.392967 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2534 09:29:10.396415 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2535 09:29:10.402870 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 09:29:10.406202 0 15 4 | B1->B0 | 2525 3333 | 0 0 | (0 0) (0 0)
2537 09:29:10.409334 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2538 09:29:10.416183 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2539 09:29:10.419284 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2540 09:29:10.422792 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 09:29:10.429571 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 09:29:10.432754 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 09:29:10.435813 1 0 0 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
2544 09:29:10.442971 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
2545 09:29:10.446096 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2546 09:29:10.449794 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2547 09:29:10.455965 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 09:29:10.459516 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 09:29:10.463004 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 09:29:10.466556 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 09:29:10.472762 1 1 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2552 09:29:10.476483 1 1 4 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2553 09:29:10.479623 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2554 09:29:10.486492 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2555 09:29:10.490027 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 09:29:10.492724 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 09:29:10.499720 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 09:29:10.503167 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 09:29:10.505962 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2560 09:29:10.513142 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2561 09:29:10.516438 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 09:29:10.519704 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 09:29:10.526384 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 09:29:10.530127 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 09:29:10.532970 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 09:29:10.539987 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 09:29:10.543074 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 09:29:10.546807 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 09:29:10.549821 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 09:29:10.556646 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 09:29:10.559802 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 09:29:10.563353 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 09:29:10.569878 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 09:29:10.573226 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 09:29:10.576941 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2576 09:29:10.583203 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2577 09:29:10.586282 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2578 09:29:10.589979 Total UI for P1: 0, mck2ui 16
2579 09:29:10.593047 best dqsien dly found for B0: ( 1, 4, 2)
2580 09:29:10.596510 Total UI for P1: 0, mck2ui 16
2581 09:29:10.599992 best dqsien dly found for B1: ( 1, 4, 2)
2582 09:29:10.603439 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2583 09:29:10.606900 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2584 09:29:10.606978
2585 09:29:10.610163 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2586 09:29:10.613386 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2587 09:29:10.616657 [Gating] SW calibration Done
2588 09:29:10.616733 ==
2589 09:29:10.619760 Dram Type= 6, Freq= 0, CH_0, rank 0
2590 09:29:10.623159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2591 09:29:10.623225 ==
2592 09:29:10.626609 RX Vref Scan: 0
2593 09:29:10.626678
2594 09:29:10.626735 RX Vref 0 -> 0, step: 1
2595 09:29:10.629772
2596 09:29:10.629836 RX Delay -40 -> 252, step: 8
2597 09:29:10.636351 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2598 09:29:10.639890 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2599 09:29:10.643289 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2600 09:29:10.646761 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2601 09:29:10.650341 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2602 09:29:10.653331 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2603 09:29:10.660174 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2604 09:29:10.663370 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2605 09:29:10.666369 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2606 09:29:10.670129 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2607 09:29:10.673214 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2608 09:29:10.679706 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2609 09:29:10.683151 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2610 09:29:10.686891 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2611 09:29:10.690086 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2612 09:29:10.696840 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2613 09:29:10.696921 ==
2614 09:29:10.699936 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 09:29:10.703033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 09:29:10.703111 ==
2617 09:29:10.703174 DQS Delay:
2618 09:29:10.706558 DQS0 = 0, DQS1 = 0
2619 09:29:10.706636 DQM Delay:
2620 09:29:10.710160 DQM0 = 115, DQM1 = 107
2621 09:29:10.710238 DQ Delay:
2622 09:29:10.713562 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2623 09:29:10.716530 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2624 09:29:10.720011 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2625 09:29:10.723364 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2626 09:29:10.723475
2627 09:29:10.723539
2628 09:29:10.723597 ==
2629 09:29:10.726539 Dram Type= 6, Freq= 0, CH_0, rank 0
2630 09:29:10.733456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2631 09:29:10.733550 ==
2632 09:29:10.733653
2633 09:29:10.733759
2634 09:29:10.733819 TX Vref Scan disable
2635 09:29:10.736900 == TX Byte 0 ==
2636 09:29:10.740367 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2637 09:29:10.743500 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2638 09:29:10.747105 == TX Byte 1 ==
2639 09:29:10.750322 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2640 09:29:10.753562 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2641 09:29:10.757022 ==
2642 09:29:10.760154 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 09:29:10.763739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 09:29:10.763816 ==
2645 09:29:10.774859 TX Vref=22, minBit 1, minWin=25, winSum=421
2646 09:29:10.777975 TX Vref=24, minBit 7, minWin=25, winSum=425
2647 09:29:10.781717 TX Vref=26, minBit 7, minWin=25, winSum=427
2648 09:29:10.784777 TX Vref=28, minBit 1, minWin=26, winSum=435
2649 09:29:10.788087 TX Vref=30, minBit 1, minWin=26, winSum=435
2650 09:29:10.791584 TX Vref=32, minBit 1, minWin=26, winSum=435
2651 09:29:10.797968 [TxChooseVref] Worse bit 1, Min win 26, Win sum 435, Final Vref 28
2652 09:29:10.798077
2653 09:29:10.801547 Final TX Range 1 Vref 28
2654 09:29:10.801643
2655 09:29:10.801750 ==
2656 09:29:10.804774 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 09:29:10.807980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 09:29:10.808048 ==
2659 09:29:10.808103
2660 09:29:10.811549
2661 09:29:10.811643 TX Vref Scan disable
2662 09:29:10.814959 == TX Byte 0 ==
2663 09:29:10.818192 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2664 09:29:10.821661 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2665 09:29:10.824595 == TX Byte 1 ==
2666 09:29:10.828357 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2667 09:29:10.831258 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2668 09:29:10.831328
2669 09:29:10.834633 [DATLAT]
2670 09:29:10.834697 Freq=1200, CH0 RK0
2671 09:29:10.834752
2672 09:29:10.838431 DATLAT Default: 0xd
2673 09:29:10.838492 0, 0xFFFF, sum = 0
2674 09:29:10.841788 1, 0xFFFF, sum = 0
2675 09:29:10.841857 2, 0xFFFF, sum = 0
2676 09:29:10.844778 3, 0xFFFF, sum = 0
2677 09:29:10.844842 4, 0xFFFF, sum = 0
2678 09:29:10.847983 5, 0xFFFF, sum = 0
2679 09:29:10.848050 6, 0xFFFF, sum = 0
2680 09:29:10.851605 7, 0xFFFF, sum = 0
2681 09:29:10.854519 8, 0xFFFF, sum = 0
2682 09:29:10.854590 9, 0xFFFF, sum = 0
2683 09:29:10.858154 10, 0xFFFF, sum = 0
2684 09:29:10.858232 11, 0xFFFF, sum = 0
2685 09:29:10.861412 12, 0x0, sum = 1
2686 09:29:10.861491 13, 0x0, sum = 2
2687 09:29:10.864522 14, 0x0, sum = 3
2688 09:29:10.864588 15, 0x0, sum = 4
2689 09:29:10.864651 best_step = 13
2690 09:29:10.864703
2691 09:29:10.868299 ==
2692 09:29:10.868364 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 09:29:10.874618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 09:29:10.874684 ==
2695 09:29:10.874744 RX Vref Scan: 1
2696 09:29:10.874797
2697 09:29:10.878396 Set Vref Range= 32 -> 127
2698 09:29:10.878464
2699 09:29:10.881448 RX Vref 32 -> 127, step: 1
2700 09:29:10.881509
2701 09:29:10.884623 RX Delay -21 -> 252, step: 4
2702 09:29:10.884692
2703 09:29:10.888323 Set Vref, RX VrefLevel [Byte0]: 32
2704 09:29:10.891270 [Byte1]: 32
2705 09:29:10.891332
2706 09:29:10.894759 Set Vref, RX VrefLevel [Byte0]: 33
2707 09:29:10.898148 [Byte1]: 33
2708 09:29:10.898240
2709 09:29:10.901162 Set Vref, RX VrefLevel [Byte0]: 34
2710 09:29:10.904361 [Byte1]: 34
2711 09:29:10.908718
2712 09:29:10.908785 Set Vref, RX VrefLevel [Byte0]: 35
2713 09:29:10.912487 [Byte1]: 35
2714 09:29:10.916647
2715 09:29:10.916712 Set Vref, RX VrefLevel [Byte0]: 36
2716 09:29:10.920123 [Byte1]: 36
2717 09:29:10.925211
2718 09:29:10.925290 Set Vref, RX VrefLevel [Byte0]: 37
2719 09:29:10.928171 [Byte1]: 37
2720 09:29:10.932978
2721 09:29:10.933056 Set Vref, RX VrefLevel [Byte0]: 38
2722 09:29:10.936061 [Byte1]: 38
2723 09:29:10.940768
2724 09:29:10.940845 Set Vref, RX VrefLevel [Byte0]: 39
2725 09:29:10.943725 [Byte1]: 39
2726 09:29:10.948673
2727 09:29:10.948751 Set Vref, RX VrefLevel [Byte0]: 40
2728 09:29:10.951589 [Byte1]: 40
2729 09:29:10.956912
2730 09:29:10.957016 Set Vref, RX VrefLevel [Byte0]: 41
2731 09:29:10.959801 [Byte1]: 41
2732 09:29:10.964480
2733 09:29:10.964556 Set Vref, RX VrefLevel [Byte0]: 42
2734 09:29:10.967464 [Byte1]: 42
2735 09:29:10.972113
2736 09:29:10.972190 Set Vref, RX VrefLevel [Byte0]: 43
2737 09:29:10.976018 [Byte1]: 43
2738 09:29:10.980191
2739 09:29:10.980268 Set Vref, RX VrefLevel [Byte0]: 44
2740 09:29:10.983890 [Byte1]: 44
2741 09:29:10.988274
2742 09:29:10.988351 Set Vref, RX VrefLevel [Byte0]: 45
2743 09:29:10.991321 [Byte1]: 45
2744 09:29:10.996185
2745 09:29:10.996263 Set Vref, RX VrefLevel [Byte0]: 46
2746 09:29:10.999370 [Byte1]: 46
2747 09:29:11.004013
2748 09:29:11.004091 Set Vref, RX VrefLevel [Byte0]: 47
2749 09:29:11.007529 [Byte1]: 47
2750 09:29:11.011911
2751 09:29:11.011988 Set Vref, RX VrefLevel [Byte0]: 48
2752 09:29:11.015135 [Byte1]: 48
2753 09:29:11.019853
2754 09:29:11.019930 Set Vref, RX VrefLevel [Byte0]: 49
2755 09:29:11.023508 [Byte1]: 49
2756 09:29:11.027583
2757 09:29:11.027659 Set Vref, RX VrefLevel [Byte0]: 50
2758 09:29:11.031256 [Byte1]: 50
2759 09:29:11.036037
2760 09:29:11.036114 Set Vref, RX VrefLevel [Byte0]: 51
2761 09:29:11.039250 [Byte1]: 51
2762 09:29:11.043514
2763 09:29:11.043591 Set Vref, RX VrefLevel [Byte0]: 52
2764 09:29:11.047254 [Byte1]: 52
2765 09:29:11.051846
2766 09:29:11.051923 Set Vref, RX VrefLevel [Byte0]: 53
2767 09:29:11.058381 [Byte1]: 53
2768 09:29:11.058488
2769 09:29:11.061291 Set Vref, RX VrefLevel [Byte0]: 54
2770 09:29:11.064664 [Byte1]: 54
2771 09:29:11.064742
2772 09:29:11.068182 Set Vref, RX VrefLevel [Byte0]: 55
2773 09:29:11.071188 [Byte1]: 55
2774 09:29:11.075453
2775 09:29:11.075530 Set Vref, RX VrefLevel [Byte0]: 56
2776 09:29:11.078738 [Byte1]: 56
2777 09:29:11.083415
2778 09:29:11.083492 Set Vref, RX VrefLevel [Byte0]: 57
2779 09:29:11.086689 [Byte1]: 57
2780 09:29:11.091357
2781 09:29:11.091434 Set Vref, RX VrefLevel [Byte0]: 58
2782 09:29:11.094431 [Byte1]: 58
2783 09:29:11.099488
2784 09:29:11.099565 Set Vref, RX VrefLevel [Byte0]: 59
2785 09:29:11.102528 [Byte1]: 59
2786 09:29:11.107008
2787 09:29:11.107085 Set Vref, RX VrefLevel [Byte0]: 60
2788 09:29:11.110664 [Byte1]: 60
2789 09:29:11.115250
2790 09:29:11.115327 Set Vref, RX VrefLevel [Byte0]: 61
2791 09:29:11.118233 [Byte1]: 61
2792 09:29:11.122605
2793 09:29:11.122682 Set Vref, RX VrefLevel [Byte0]: 62
2794 09:29:11.126386 [Byte1]: 62
2795 09:29:11.130578
2796 09:29:11.130653 Set Vref, RX VrefLevel [Byte0]: 63
2797 09:29:11.134200 [Byte1]: 63
2798 09:29:11.139040
2799 09:29:11.139110 Set Vref, RX VrefLevel [Byte0]: 64
2800 09:29:11.141860 [Byte1]: 64
2801 09:29:11.146855
2802 09:29:11.146932 Set Vref, RX VrefLevel [Byte0]: 65
2803 09:29:11.150133 [Byte1]: 65
2804 09:29:11.154878
2805 09:29:11.154954 Set Vref, RX VrefLevel [Byte0]: 66
2806 09:29:11.157940 [Byte1]: 66
2807 09:29:11.162559
2808 09:29:11.162636 Set Vref, RX VrefLevel [Byte0]: 67
2809 09:29:11.165963 [Byte1]: 67
2810 09:29:11.170732
2811 09:29:11.170809 Set Vref, RX VrefLevel [Byte0]: 68
2812 09:29:11.173657 [Byte1]: 68
2813 09:29:11.178339
2814 09:29:11.178433 Final RX Vref Byte 0 = 52 to rank0
2815 09:29:11.181377 Final RX Vref Byte 1 = 50 to rank0
2816 09:29:11.185151 Final RX Vref Byte 0 = 52 to rank1
2817 09:29:11.188166 Final RX Vref Byte 1 = 50 to rank1==
2818 09:29:11.191298 Dram Type= 6, Freq= 0, CH_0, rank 0
2819 09:29:11.198270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 09:29:11.198349 ==
2821 09:29:11.198409 DQS Delay:
2822 09:29:11.198464 DQS0 = 0, DQS1 = 0
2823 09:29:11.201818 DQM Delay:
2824 09:29:11.201895 DQM0 = 114, DQM1 = 104
2825 09:29:11.205203 DQ Delay:
2826 09:29:11.208535 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
2827 09:29:11.211560 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2828 09:29:11.215203 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2829 09:29:11.218266 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
2830 09:29:11.218338
2831 09:29:11.218394
2832 09:29:11.225211 [DQSOSCAuto] RK0, (LSB)MR18= 0xfeee, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2833 09:29:11.228390 CH0 RK0: MR19=303, MR18=FEEE
2834 09:29:11.235045 CH0_RK0: MR19=0x303, MR18=0xFEEE, DQSOSC=410, MR23=63, INC=39, DEC=26
2835 09:29:11.235124
2836 09:29:11.238441 ----->DramcWriteLeveling(PI) begin...
2837 09:29:11.238544 ==
2838 09:29:11.242048 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 09:29:11.245127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 09:29:11.245196 ==
2841 09:29:11.248225 Write leveling (Byte 0): 33 => 33
2842 09:29:11.252045 Write leveling (Byte 1): 30 => 30
2843 09:29:11.255068 DramcWriteLeveling(PI) end<-----
2844 09:29:11.255136
2845 09:29:11.255199 ==
2846 09:29:11.258529 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 09:29:11.264789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 09:29:11.264862 ==
2849 09:29:11.264927 [Gating] SW mode calibration
2850 09:29:11.275268 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2851 09:29:11.278244 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2852 09:29:11.281798 0 15 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2853 09:29:11.288901 0 15 4 | B1->B0 | 2928 3434 | 1 1 | (0 0) (1 1)
2854 09:29:11.292109 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 09:29:11.295236 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 09:29:11.302057 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 09:29:11.305039 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 09:29:11.308475 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 09:29:11.315293 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
2860 09:29:11.318391 1 0 0 | B1->B0 | 3030 2828 | 0 0 | (1 0) (0 0)
2861 09:29:11.321629 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 09:29:11.328627 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 09:29:11.332332 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 09:29:11.335458 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 09:29:11.338600 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 09:29:11.345471 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2867 09:29:11.348635 1 0 28 | B1->B0 | 2323 4141 | 0 1 | (0 0) (0 0)
2868 09:29:11.352283 1 1 0 | B1->B0 | 3232 3d3d | 1 0 | (0 0) (0 0)
2869 09:29:11.358899 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2870 09:29:11.362018 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 09:29:11.365657 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 09:29:11.371906 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 09:29:11.375551 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 09:29:11.379184 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 09:29:11.385496 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2876 09:29:11.388986 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2877 09:29:11.391805 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 09:29:11.398533 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 09:29:11.402233 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 09:29:11.405411 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 09:29:11.412152 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 09:29:11.415261 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 09:29:11.418690 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 09:29:11.425256 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 09:29:11.428676 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 09:29:11.431611 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 09:29:11.438520 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 09:29:11.441639 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 09:29:11.445446 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 09:29:11.448457 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2891 09:29:11.455325 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2892 09:29:11.458502 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2893 09:29:11.462023 Total UI for P1: 0, mck2ui 16
2894 09:29:11.465051 best dqsien dly found for B0: ( 1, 3, 26)
2895 09:29:11.468549 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 09:29:11.471865 Total UI for P1: 0, mck2ui 16
2897 09:29:11.474854 best dqsien dly found for B1: ( 1, 4, 0)
2898 09:29:11.478595 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2899 09:29:11.481619 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2900 09:29:11.481700
2901 09:29:11.488544 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2902 09:29:11.492030 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2903 09:29:11.492108 [Gating] SW calibration Done
2904 09:29:11.494959 ==
2905 09:29:11.498406 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 09:29:11.501924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 09:29:11.502042 ==
2908 09:29:11.502104 RX Vref Scan: 0
2909 09:29:11.502160
2910 09:29:11.504986 RX Vref 0 -> 0, step: 1
2911 09:29:11.505063
2912 09:29:11.508730 RX Delay -40 -> 252, step: 8
2913 09:29:11.511808 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2914 09:29:11.515055 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2915 09:29:11.518828 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2916 09:29:11.525547 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2917 09:29:11.528497 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2918 09:29:11.532023 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2919 09:29:11.535141 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2920 09:29:11.538332 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2921 09:29:11.545052 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2922 09:29:11.548624 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2923 09:29:11.551913 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2924 09:29:11.555482 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2925 09:29:11.558930 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2926 09:29:11.565556 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2927 09:29:11.568781 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2928 09:29:11.571771 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2929 09:29:11.571842 ==
2930 09:29:11.575422 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 09:29:11.578739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 09:29:11.578812 ==
2933 09:29:11.581742 DQS Delay:
2934 09:29:11.581805 DQS0 = 0, DQS1 = 0
2935 09:29:11.581860 DQM Delay:
2936 09:29:11.585557 DQM0 = 115, DQM1 = 106
2937 09:29:11.585619 DQ Delay:
2938 09:29:11.588657 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2939 09:29:11.592219 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2940 09:29:11.595603 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2941 09:29:11.602101 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2942 09:29:11.602179
2943 09:29:11.602239
2944 09:29:11.602295 ==
2945 09:29:11.605355 Dram Type= 6, Freq= 0, CH_0, rank 1
2946 09:29:11.608917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2947 09:29:11.609006 ==
2948 09:29:11.609069
2949 09:29:11.609125
2950 09:29:11.611915 TX Vref Scan disable
2951 09:29:11.611993 == TX Byte 0 ==
2952 09:29:11.618795 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2953 09:29:11.621910 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2954 09:29:11.622049 == TX Byte 1 ==
2955 09:29:11.628763 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2956 09:29:11.632449 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2957 09:29:11.632527 ==
2958 09:29:11.635725 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 09:29:11.638761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 09:29:11.638839 ==
2961 09:29:11.651425 TX Vref=22, minBit 0, minWin=25, winSum=416
2962 09:29:11.654827 TX Vref=24, minBit 3, minWin=25, winSum=422
2963 09:29:11.658559 TX Vref=26, minBit 0, minWin=26, winSum=428
2964 09:29:11.661763 TX Vref=28, minBit 0, minWin=26, winSum=433
2965 09:29:11.665062 TX Vref=30, minBit 3, minWin=26, winSum=433
2966 09:29:11.668448 TX Vref=32, minBit 3, minWin=26, winSum=434
2967 09:29:11.675060 [TxChooseVref] Worse bit 3, Min win 26, Win sum 434, Final Vref 32
2968 09:29:11.675157
2969 09:29:11.678171 Final TX Range 1 Vref 32
2970 09:29:11.678250
2971 09:29:11.678311 ==
2972 09:29:11.681858 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 09:29:11.684952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 09:29:11.685031 ==
2975 09:29:11.685092
2976 09:29:11.685148
2977 09:29:11.688110 TX Vref Scan disable
2978 09:29:11.691837 == TX Byte 0 ==
2979 09:29:11.695150 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2980 09:29:11.698069 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2981 09:29:11.701609 == TX Byte 1 ==
2982 09:29:11.704955 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2983 09:29:11.708563 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2984 09:29:11.708643
2985 09:29:11.711477 [DATLAT]
2986 09:29:11.711546 Freq=1200, CH0 RK1
2987 09:29:11.711610
2988 09:29:11.714911 DATLAT Default: 0xd
2989 09:29:11.714983 0, 0xFFFF, sum = 0
2990 09:29:11.718225 1, 0xFFFF, sum = 0
2991 09:29:11.718317 2, 0xFFFF, sum = 0
2992 09:29:11.721865 3, 0xFFFF, sum = 0
2993 09:29:11.721954 4, 0xFFFF, sum = 0
2994 09:29:11.725020 5, 0xFFFF, sum = 0
2995 09:29:11.725083 6, 0xFFFF, sum = 0
2996 09:29:11.728796 7, 0xFFFF, sum = 0
2997 09:29:11.728861 8, 0xFFFF, sum = 0
2998 09:29:11.731684 9, 0xFFFF, sum = 0
2999 09:29:11.731749 10, 0xFFFF, sum = 0
3000 09:29:11.735608 11, 0xFFFF, sum = 0
3001 09:29:11.735671 12, 0x0, sum = 1
3002 09:29:11.738524 13, 0x0, sum = 2
3003 09:29:11.738593 14, 0x0, sum = 3
3004 09:29:11.741598 15, 0x0, sum = 4
3005 09:29:11.741659 best_step = 13
3006 09:29:11.741712
3007 09:29:11.741762 ==
3008 09:29:11.745316 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 09:29:11.752070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 09:29:11.752136 ==
3011 09:29:11.752191 RX Vref Scan: 0
3012 09:29:11.752242
3013 09:29:11.755193 RX Vref 0 -> 0, step: 1
3014 09:29:11.755256
3015 09:29:11.758705 RX Delay -21 -> 252, step: 4
3016 09:29:11.761592 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3017 09:29:11.764991 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3018 09:29:11.772016 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3019 09:29:11.775200 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3020 09:29:11.778421 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3021 09:29:11.781678 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3022 09:29:11.785092 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3023 09:29:11.792039 iDelay=195, Bit 7, Center 120 (51 ~ 190) 140
3024 09:29:11.795119 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3025 09:29:11.798302 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3026 09:29:11.801919 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3027 09:29:11.805111 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3028 09:29:11.808188 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3029 09:29:11.815289 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3030 09:29:11.818282 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3031 09:29:11.821890 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3032 09:29:11.821986 ==
3033 09:29:11.825239 Dram Type= 6, Freq= 0, CH_0, rank 1
3034 09:29:11.828699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3035 09:29:11.831736 ==
3036 09:29:11.831805 DQS Delay:
3037 09:29:11.831863 DQS0 = 0, DQS1 = 0
3038 09:29:11.834903 DQM Delay:
3039 09:29:11.834967 DQM0 = 113, DQM1 = 104
3040 09:29:11.838604 DQ Delay:
3041 09:29:11.841691 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3042 09:29:11.845417 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =120
3043 09:29:11.848589 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3044 09:29:11.851772 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3045 09:29:11.851837
3046 09:29:11.851892
3047 09:29:11.858405 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
3048 09:29:11.862106 CH0 RK1: MR19=403, MR18=3F4
3049 09:29:11.868455 CH0_RK1: MR19=0x403, MR18=0x3F4, DQSOSC=408, MR23=63, INC=39, DEC=26
3050 09:29:11.872124 [RxdqsGatingPostProcess] freq 1200
3051 09:29:11.875052 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3052 09:29:11.878653 best DQS0 dly(2T, 0.5T) = (0, 12)
3053 09:29:11.881603 best DQS1 dly(2T, 0.5T) = (0, 12)
3054 09:29:11.885173 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3055 09:29:11.888803 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3056 09:29:11.891944 best DQS0 dly(2T, 0.5T) = (0, 11)
3057 09:29:11.895139 best DQS1 dly(2T, 0.5T) = (0, 12)
3058 09:29:11.898453 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3059 09:29:11.902103 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3060 09:29:11.905555 Pre-setting of DQS Precalculation
3061 09:29:11.908803 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3062 09:29:11.908881 ==
3063 09:29:11.911870 Dram Type= 6, Freq= 0, CH_1, rank 0
3064 09:29:11.918506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 09:29:11.918624 ==
3066 09:29:11.921790 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3067 09:29:11.928567 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3068 09:29:11.937245 [CA 0] Center 38 (8~68) winsize 61
3069 09:29:11.940622 [CA 1] Center 38 (8~68) winsize 61
3070 09:29:11.943906 [CA 2] Center 35 (5~65) winsize 61
3071 09:29:11.946859 [CA 3] Center 34 (4~64) winsize 61
3072 09:29:11.950522 [CA 4] Center 34 (4~65) winsize 62
3073 09:29:11.953692 [CA 5] Center 33 (3~64) winsize 62
3074 09:29:11.953770
3075 09:29:11.957453 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3076 09:29:11.957530
3077 09:29:11.960665 [CATrainingPosCal] consider 1 rank data
3078 09:29:11.963683 u2DelayCellTimex100 = 270/100 ps
3079 09:29:11.967175 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3080 09:29:11.970260 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3081 09:29:11.977264 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3082 09:29:11.980228 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3083 09:29:11.983596 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3084 09:29:11.987180 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3085 09:29:11.987257
3086 09:29:11.990313 CA PerBit enable=1, Macro0, CA PI delay=33
3087 09:29:11.990391
3088 09:29:11.993861 [CBTSetCACLKResult] CA Dly = 33
3089 09:29:11.993939 CS Dly: 6 (0~37)
3090 09:29:11.994038 ==
3091 09:29:11.997448 Dram Type= 6, Freq= 0, CH_1, rank 1
3092 09:29:12.003853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 09:29:12.003932 ==
3094 09:29:12.007091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3095 09:29:12.013835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3096 09:29:12.022683 [CA 0] Center 38 (8~68) winsize 61
3097 09:29:12.041441 [CA 1] Center 38 (9~68) winsize 60
3098 09:29:12.041766 [CA 2] Center 34 (4~65) winsize 62
3099 09:29:12.041836 [CA 3] Center 34 (4~65) winsize 62
3100 09:29:12.041893 [CA 4] Center 34 (4~65) winsize 62
3101 09:29:12.041954 [CA 5] Center 33 (3~64) winsize 62
3102 09:29:12.042034
3103 09:29:12.043096 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3104 09:29:12.043162
3105 09:29:12.045897 [CATrainingPosCal] consider 2 rank data
3106 09:29:12.049483 u2DelayCellTimex100 = 270/100 ps
3107 09:29:12.053118 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3108 09:29:12.056159 CA1 delay=38 (9~68),Diff = 5 PI (24 cell)
3109 09:29:12.062466 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3110 09:29:12.066225 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3111 09:29:12.069697 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3112 09:29:12.072500 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3113 09:29:12.072597
3114 09:29:12.076349 CA PerBit enable=1, Macro0, CA PI delay=33
3115 09:29:12.076413
3116 09:29:12.079465 [CBTSetCACLKResult] CA Dly = 33
3117 09:29:12.079529 CS Dly: 7 (0~39)
3118 09:29:12.079591
3119 09:29:12.082695 ----->DramcWriteLeveling(PI) begin...
3120 09:29:12.082787 ==
3121 09:29:12.086251 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 09:29:12.092689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 09:29:12.092782 ==
3124 09:29:12.096452 Write leveling (Byte 0): 27 => 27
3125 09:29:12.099491 Write leveling (Byte 1): 29 => 29
3126 09:29:12.099570 DramcWriteLeveling(PI) end<-----
3127 09:29:12.102937
3128 09:29:12.103014 ==
3129 09:29:12.105968 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 09:29:12.109891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 09:29:12.109970 ==
3132 09:29:12.112801 [Gating] SW mode calibration
3133 09:29:12.119554 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3134 09:29:12.122921 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3135 09:29:12.129387 0 15 0 | B1->B0 | 2c2c 2727 | 0 0 | (0 0) (0 0)
3136 09:29:12.132985 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 09:29:12.136323 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 09:29:12.143010 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 09:29:12.145966 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 09:29:12.149814 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 09:29:12.156366 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 09:29:12.159859 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3143 09:29:12.162926 1 0 0 | B1->B0 | 2525 2c2c | 0 0 | (1 1) (1 0)
3144 09:29:12.169807 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 09:29:12.172966 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 09:29:12.176502 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 09:29:12.182721 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 09:29:12.186570 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 09:29:12.189659 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 09:29:12.192633 1 0 28 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
3151 09:29:12.199747 1 1 0 | B1->B0 | 4141 3232 | 0 1 | (0 0) (0 0)
3152 09:29:12.202869 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 09:29:12.205891 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 09:29:12.212723 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 09:29:12.215905 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 09:29:12.219554 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 09:29:12.225991 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 09:29:12.229403 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3159 09:29:12.232846 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3160 09:29:12.239427 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 09:29:12.242963 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 09:29:12.246300 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 09:29:12.253140 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 09:29:12.256050 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 09:29:12.259442 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 09:29:12.266482 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 09:29:12.269527 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 09:29:12.272620 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 09:29:12.279371 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 09:29:12.283147 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 09:29:12.286363 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 09:29:12.289355 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 09:29:12.296106 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 09:29:12.299628 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3175 09:29:12.303050 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 09:29:12.305958 Total UI for P1: 0, mck2ui 16
3177 09:29:12.309597 best dqsien dly found for B0: ( 1, 3, 28)
3178 09:29:12.312763 Total UI for P1: 0, mck2ui 16
3179 09:29:12.316405 best dqsien dly found for B1: ( 1, 3, 30)
3180 09:29:12.319594 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3181 09:29:12.322691 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3182 09:29:12.322769
3183 09:29:12.329474 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3184 09:29:12.333101 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3185 09:29:12.336216 [Gating] SW calibration Done
3186 09:29:12.336324 ==
3187 09:29:12.339653 Dram Type= 6, Freq= 0, CH_1, rank 0
3188 09:29:12.343019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3189 09:29:12.343097 ==
3190 09:29:12.343158 RX Vref Scan: 0
3191 09:29:12.343213
3192 09:29:12.346467 RX Vref 0 -> 0, step: 1
3193 09:29:12.346545
3194 09:29:12.349887 RX Delay -40 -> 252, step: 8
3195 09:29:12.352733 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3196 09:29:12.356795 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3197 09:29:12.359824 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3198 09:29:12.366416 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3199 09:29:12.370005 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3200 09:29:12.372825 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3201 09:29:12.376606 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3202 09:29:12.379516 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3203 09:29:12.386167 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3204 09:29:12.390031 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3205 09:29:12.393210 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3206 09:29:12.396307 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3207 09:29:12.400026 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3208 09:29:12.406480 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3209 09:29:12.410055 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3210 09:29:12.413386 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3211 09:29:12.413463 ==
3212 09:29:12.416425 Dram Type= 6, Freq= 0, CH_1, rank 0
3213 09:29:12.419637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 09:29:12.419715 ==
3215 09:29:12.423287 DQS Delay:
3216 09:29:12.423365 DQS0 = 0, DQS1 = 0
3217 09:29:12.426398 DQM Delay:
3218 09:29:12.426475 DQM0 = 116, DQM1 = 109
3219 09:29:12.426536 DQ Delay:
3220 09:29:12.429568 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3221 09:29:12.436947 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3222 09:29:12.439932 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3223 09:29:12.443048 DQ12 =119, DQ13 =115, DQ14 =115, DQ15 =115
3224 09:29:12.443125
3225 09:29:12.443185
3226 09:29:12.443239 ==
3227 09:29:12.446789 Dram Type= 6, Freq= 0, CH_1, rank 0
3228 09:29:12.449446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3229 09:29:12.449524 ==
3230 09:29:12.449585
3231 09:29:12.449649
3232 09:29:12.452957 TX Vref Scan disable
3233 09:29:12.456230 == TX Byte 0 ==
3234 09:29:12.459715 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3235 09:29:12.462961 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3236 09:29:12.466390 == TX Byte 1 ==
3237 09:29:12.469878 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3238 09:29:12.472884 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3239 09:29:12.472962 ==
3240 09:29:12.476458 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 09:29:12.480016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 09:29:12.480094 ==
3243 09:29:12.492722 TX Vref=22, minBit 1, minWin=25, winSum=413
3244 09:29:12.496394 TX Vref=24, minBit 1, minWin=25, winSum=418
3245 09:29:12.499459 TX Vref=26, minBit 1, minWin=26, winSum=421
3246 09:29:12.502535 TX Vref=28, minBit 2, minWin=26, winSum=427
3247 09:29:12.506285 TX Vref=30, minBit 3, minWin=26, winSum=429
3248 09:29:12.509308 TX Vref=32, minBit 1, minWin=26, winSum=428
3249 09:29:12.516357 [TxChooseVref] Worse bit 3, Min win 26, Win sum 429, Final Vref 30
3250 09:29:12.516435
3251 09:29:12.519316 Final TX Range 1 Vref 30
3252 09:29:12.519393
3253 09:29:12.519452 ==
3254 09:29:12.523120 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 09:29:12.526282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 09:29:12.526360 ==
3257 09:29:12.526420
3258 09:29:12.526475
3259 09:29:12.529886 TX Vref Scan disable
3260 09:29:12.533179 == TX Byte 0 ==
3261 09:29:12.536231 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3262 09:29:12.539791 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3263 09:29:12.542844 == TX Byte 1 ==
3264 09:29:12.545941 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3265 09:29:12.549647 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3266 09:29:12.549723
3267 09:29:12.552631 [DATLAT]
3268 09:29:12.552708 Freq=1200, CH1 RK0
3269 09:29:12.552768
3270 09:29:12.556266 DATLAT Default: 0xd
3271 09:29:12.556342 0, 0xFFFF, sum = 0
3272 09:29:12.559987 1, 0xFFFF, sum = 0
3273 09:29:12.560065 2, 0xFFFF, sum = 0
3274 09:29:12.562802 3, 0xFFFF, sum = 0
3275 09:29:12.562885 4, 0xFFFF, sum = 0
3276 09:29:12.566530 5, 0xFFFF, sum = 0
3277 09:29:12.566628 6, 0xFFFF, sum = 0
3278 09:29:12.569594 7, 0xFFFF, sum = 0
3279 09:29:12.569671 8, 0xFFFF, sum = 0
3280 09:29:12.573058 9, 0xFFFF, sum = 0
3281 09:29:12.573135 10, 0xFFFF, sum = 0
3282 09:29:12.576503 11, 0xFFFF, sum = 0
3283 09:29:12.576581 12, 0x0, sum = 1
3284 09:29:12.579751 13, 0x0, sum = 2
3285 09:29:12.579850 14, 0x0, sum = 3
3286 09:29:12.583173 15, 0x0, sum = 4
3287 09:29:12.583250 best_step = 13
3288 09:29:12.583309
3289 09:29:12.583364 ==
3290 09:29:12.586242 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 09:29:12.593021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 09:29:12.593099 ==
3293 09:29:12.593159 RX Vref Scan: 1
3294 09:29:12.593215
3295 09:29:12.596271 Set Vref Range= 32 -> 127
3296 09:29:12.596361
3297 09:29:12.600026 RX Vref 32 -> 127, step: 1
3298 09:29:12.600102
3299 09:29:12.600162 RX Delay -21 -> 252, step: 4
3300 09:29:12.603033
3301 09:29:12.603109 Set Vref, RX VrefLevel [Byte0]: 32
3302 09:29:12.606192 [Byte1]: 32
3303 09:29:12.611206
3304 09:29:12.611281 Set Vref, RX VrefLevel [Byte0]: 33
3305 09:29:12.614325 [Byte1]: 33
3306 09:29:12.618881
3307 09:29:12.618957 Set Vref, RX VrefLevel [Byte0]: 34
3308 09:29:12.622364 [Byte1]: 34
3309 09:29:12.626781
3310 09:29:12.626858 Set Vref, RX VrefLevel [Byte0]: 35
3311 09:29:12.629925 [Byte1]: 35
3312 09:29:12.635034
3313 09:29:12.635111 Set Vref, RX VrefLevel [Byte0]: 36
3314 09:29:12.637966 [Byte1]: 36
3315 09:29:12.642747
3316 09:29:12.642822 Set Vref, RX VrefLevel [Byte0]: 37
3317 09:29:12.645862 [Byte1]: 37
3318 09:29:12.650943
3319 09:29:12.651010 Set Vref, RX VrefLevel [Byte0]: 38
3320 09:29:12.653984 [Byte1]: 38
3321 09:29:12.658408
3322 09:29:12.658470 Set Vref, RX VrefLevel [Byte0]: 39
3323 09:29:12.662069 [Byte1]: 39
3324 09:29:12.666302
3325 09:29:12.666371 Set Vref, RX VrefLevel [Byte0]: 40
3326 09:29:12.669421 [Byte1]: 40
3327 09:29:12.674368
3328 09:29:12.674438 Set Vref, RX VrefLevel [Byte0]: 41
3329 09:29:12.677533 [Byte1]: 41
3330 09:29:12.682519
3331 09:29:12.682622 Set Vref, RX VrefLevel [Byte0]: 42
3332 09:29:12.685319 [Byte1]: 42
3333 09:29:12.690003
3334 09:29:12.690094 Set Vref, RX VrefLevel [Byte0]: 43
3335 09:29:12.693582 [Byte1]: 43
3336 09:29:12.698199
3337 09:29:12.698275 Set Vref, RX VrefLevel [Byte0]: 44
3338 09:29:12.701429 [Byte1]: 44
3339 09:29:12.705900
3340 09:29:12.705985 Set Vref, RX VrefLevel [Byte0]: 45
3341 09:29:12.709475 [Byte1]: 45
3342 09:29:12.713772
3343 09:29:12.713848 Set Vref, RX VrefLevel [Byte0]: 46
3344 09:29:12.717358 [Byte1]: 46
3345 09:29:12.721715
3346 09:29:12.721792 Set Vref, RX VrefLevel [Byte0]: 47
3347 09:29:12.725158 [Byte1]: 47
3348 09:29:12.729534
3349 09:29:12.729610 Set Vref, RX VrefLevel [Byte0]: 48
3350 09:29:12.733466 [Byte1]: 48
3351 09:29:12.737598
3352 09:29:12.737674 Set Vref, RX VrefLevel [Byte0]: 49
3353 09:29:12.740806 [Byte1]: 49
3354 09:29:12.745785
3355 09:29:12.745860 Set Vref, RX VrefLevel [Byte0]: 50
3356 09:29:12.749180 [Byte1]: 50
3357 09:29:12.753611
3358 09:29:12.753688 Set Vref, RX VrefLevel [Byte0]: 51
3359 09:29:12.756681 [Byte1]: 51
3360 09:29:12.761673
3361 09:29:12.761750 Set Vref, RX VrefLevel [Byte0]: 52
3362 09:29:12.764677 [Byte1]: 52
3363 09:29:12.769090
3364 09:29:12.769167 Set Vref, RX VrefLevel [Byte0]: 53
3365 09:29:12.772655 [Byte1]: 53
3366 09:29:12.777648
3367 09:29:12.777724 Set Vref, RX VrefLevel [Byte0]: 54
3368 09:29:12.780701 [Byte1]: 54
3369 09:29:12.785113
3370 09:29:12.785192 Set Vref, RX VrefLevel [Byte0]: 55
3371 09:29:12.788829 [Byte1]: 55
3372 09:29:12.793158
3373 09:29:12.793244 Set Vref, RX VrefLevel [Byte0]: 56
3374 09:29:12.796502 [Byte1]: 56
3375 09:29:12.800898
3376 09:29:12.800974 Set Vref, RX VrefLevel [Byte0]: 57
3377 09:29:12.803980 [Byte1]: 57
3378 09:29:12.808831
3379 09:29:12.808907 Set Vref, RX VrefLevel [Byte0]: 58
3380 09:29:12.812421 [Byte1]: 58
3381 09:29:12.817075
3382 09:29:12.817155 Set Vref, RX VrefLevel [Byte0]: 59
3383 09:29:12.820359 [Byte1]: 59
3384 09:29:12.824524
3385 09:29:12.824605 Set Vref, RX VrefLevel [Byte0]: 60
3386 09:29:12.827943 [Byte1]: 60
3387 09:29:12.832656
3388 09:29:12.832757 Set Vref, RX VrefLevel [Byte0]: 61
3389 09:29:12.835640 [Byte1]: 61
3390 09:29:12.840252
3391 09:29:12.840321 Set Vref, RX VrefLevel [Byte0]: 62
3392 09:29:12.843920 [Byte1]: 62
3393 09:29:12.848889
3394 09:29:12.848994 Set Vref, RX VrefLevel [Byte0]: 63
3395 09:29:12.851730 [Byte1]: 63
3396 09:29:12.856491
3397 09:29:12.856583 Set Vref, RX VrefLevel [Byte0]: 64
3398 09:29:12.859586 [Byte1]: 64
3399 09:29:12.864001
3400 09:29:12.864072 Set Vref, RX VrefLevel [Byte0]: 65
3401 09:29:12.867614 [Byte1]: 65
3402 09:29:12.872433
3403 09:29:12.872510 Set Vref, RX VrefLevel [Byte0]: 66
3404 09:29:12.875658 [Byte1]: 66
3405 09:29:12.879952
3406 09:29:12.880027 Set Vref, RX VrefLevel [Byte0]: 67
3407 09:29:12.883720 [Byte1]: 67
3408 09:29:12.888113
3409 09:29:12.888188 Set Vref, RX VrefLevel [Byte0]: 68
3410 09:29:12.891203 [Byte1]: 68
3411 09:29:12.896194
3412 09:29:12.896308 Set Vref, RX VrefLevel [Byte0]: 69
3413 09:29:12.899119 [Byte1]: 69
3414 09:29:12.904246
3415 09:29:12.904342 Set Vref, RX VrefLevel [Byte0]: 70
3416 09:29:12.907067 [Byte1]: 70
3417 09:29:12.911900
3418 09:29:12.911992 Final RX Vref Byte 0 = 57 to rank0
3419 09:29:12.915058 Final RX Vref Byte 1 = 51 to rank0
3420 09:29:12.918696 Final RX Vref Byte 0 = 57 to rank1
3421 09:29:12.921823 Final RX Vref Byte 1 = 51 to rank1==
3422 09:29:12.925530 Dram Type= 6, Freq= 0, CH_1, rank 0
3423 09:29:12.932058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 09:29:12.932132 ==
3425 09:29:12.932221 DQS Delay:
3426 09:29:12.932340 DQS0 = 0, DQS1 = 0
3427 09:29:12.934858 DQM Delay:
3428 09:29:12.934930 DQM0 = 115, DQM1 = 109
3429 09:29:12.938223 DQ Delay:
3430 09:29:12.942106 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =112
3431 09:29:12.945117 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =112
3432 09:29:12.948339 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =106
3433 09:29:12.951938 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3434 09:29:12.952012
3435 09:29:12.952070
3436 09:29:12.958528 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce0, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
3437 09:29:12.962091 CH1 RK0: MR19=303, MR18=FCE0
3438 09:29:12.968445 CH1_RK0: MR19=0x303, MR18=0xFCE0, DQSOSC=411, MR23=63, INC=38, DEC=25
3439 09:29:12.968519
3440 09:29:12.971996 ----->DramcWriteLeveling(PI) begin...
3441 09:29:12.972074 ==
3442 09:29:12.975099 Dram Type= 6, Freq= 0, CH_1, rank 1
3443 09:29:12.978726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3444 09:29:12.978801 ==
3445 09:29:12.981798 Write leveling (Byte 0): 28 => 28
3446 09:29:12.985641 Write leveling (Byte 1): 28 => 28
3447 09:29:12.988757 DramcWriteLeveling(PI) end<-----
3448 09:29:12.988830
3449 09:29:12.988925 ==
3450 09:29:12.991844 Dram Type= 6, Freq= 0, CH_1, rank 1
3451 09:29:12.995052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3452 09:29:12.998770 ==
3453 09:29:12.998839 [Gating] SW mode calibration
3454 09:29:13.008467 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3455 09:29:13.011808 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3456 09:29:13.015391 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3457 09:29:13.021912 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3458 09:29:13.025513 0 15 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3459 09:29:13.028673 0 15 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3460 09:29:13.035355 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3461 09:29:13.038532 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3462 09:29:13.042295 0 15 24 | B1->B0 | 3333 2828 | 1 0 | (1 1) (0 0)
3463 09:29:13.048990 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3464 09:29:13.052118 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3465 09:29:13.055853 1 0 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3466 09:29:13.062003 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3467 09:29:13.065551 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3468 09:29:13.068973 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 09:29:13.072340 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3470 09:29:13.078959 1 0 24 | B1->B0 | 2828 4545 | 0 0 | (1 1) (0 0)
3471 09:29:13.082332 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3472 09:29:13.085252 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3473 09:29:13.092103 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 09:29:13.095181 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3475 09:29:13.098961 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 09:29:13.105705 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 09:29:13.108904 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3478 09:29:13.112068 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3479 09:29:13.118750 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3480 09:29:13.122092 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 09:29:13.125460 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 09:29:13.132067 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 09:29:13.135168 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 09:29:13.138891 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 09:29:13.145146 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 09:29:13.148927 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 09:29:13.151998 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 09:29:13.158517 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 09:29:13.162305 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 09:29:13.165466 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 09:29:13.171823 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 09:29:13.175376 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 09:29:13.178987 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 09:29:13.181766 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3495 09:29:13.188685 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3496 09:29:13.191772 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3497 09:29:13.195283 Total UI for P1: 0, mck2ui 16
3498 09:29:13.198823 best dqsien dly found for B0: ( 1, 3, 26)
3499 09:29:13.201995 Total UI for P1: 0, mck2ui 16
3500 09:29:13.205159 best dqsien dly found for B1: ( 1, 3, 28)
3501 09:29:13.208831 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3502 09:29:13.212112 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3503 09:29:13.212183
3504 09:29:13.215042 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3505 09:29:13.218776 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3506 09:29:13.221747 [Gating] SW calibration Done
3507 09:29:13.221844 ==
3508 09:29:13.225565 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 09:29:13.228981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 09:29:13.231797 ==
3511 09:29:13.231868 RX Vref Scan: 0
3512 09:29:13.231933
3513 09:29:13.235528 RX Vref 0 -> 0, step: 1
3514 09:29:13.235629
3515 09:29:13.238950 RX Delay -40 -> 252, step: 8
3516 09:29:13.241905 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3517 09:29:13.245565 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3518 09:29:13.248521 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3519 09:29:13.252183 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3520 09:29:13.258803 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3521 09:29:13.262062 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3522 09:29:13.265654 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3523 09:29:13.268830 iDelay=200, Bit 7, Center 107 (40 ~ 175) 136
3524 09:29:13.271787 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3525 09:29:13.275466 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3526 09:29:13.281874 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3527 09:29:13.285479 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3528 09:29:13.288432 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3529 09:29:13.292117 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3530 09:29:13.298695 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3531 09:29:13.302511 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3532 09:29:13.302586 ==
3533 09:29:13.305174 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 09:29:13.308600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 09:29:13.308673 ==
3536 09:29:13.308752 DQS Delay:
3537 09:29:13.312150 DQS0 = 0, DQS1 = 0
3538 09:29:13.312222 DQM Delay:
3539 09:29:13.315640 DQM0 = 113, DQM1 = 110
3540 09:29:13.315716 DQ Delay:
3541 09:29:13.318832 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3542 09:29:13.322466 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =107
3543 09:29:13.325657 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3544 09:29:13.328681 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3545 09:29:13.328753
3546 09:29:13.332489
3547 09:29:13.332556 ==
3548 09:29:13.335564 Dram Type= 6, Freq= 0, CH_1, rank 1
3549 09:29:13.339080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3550 09:29:13.339151 ==
3551 09:29:13.339214
3552 09:29:13.339267
3553 09:29:13.341941 TX Vref Scan disable
3554 09:29:13.342060 == TX Byte 0 ==
3555 09:29:13.345639 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3556 09:29:13.352075 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3557 09:29:13.352156 == TX Byte 1 ==
3558 09:29:13.355250 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3559 09:29:13.362235 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3560 09:29:13.362341 ==
3561 09:29:13.365227 Dram Type= 6, Freq= 0, CH_1, rank 1
3562 09:29:13.368960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3563 09:29:13.369029 ==
3564 09:29:13.380822 TX Vref=22, minBit 7, minWin=25, winSum=420
3565 09:29:13.383854 TX Vref=24, minBit 0, minWin=26, winSum=425
3566 09:29:13.387130 TX Vref=26, minBit 2, minWin=26, winSum=431
3567 09:29:13.390572 TX Vref=28, minBit 2, minWin=26, winSum=432
3568 09:29:13.394186 TX Vref=30, minBit 2, minWin=26, winSum=432
3569 09:29:13.397355 TX Vref=32, minBit 2, minWin=26, winSum=434
3570 09:29:13.403792 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 32
3571 09:29:13.403887
3572 09:29:13.407521 Final TX Range 1 Vref 32
3573 09:29:13.407592
3574 09:29:13.407657 ==
3575 09:29:13.410626 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 09:29:13.413657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 09:29:13.413753 ==
3578 09:29:13.413835
3579 09:29:13.417228
3580 09:29:13.417317 TX Vref Scan disable
3581 09:29:13.420716 == TX Byte 0 ==
3582 09:29:13.424034 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3583 09:29:13.427448 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3584 09:29:13.430693 == TX Byte 1 ==
3585 09:29:13.433881 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3586 09:29:13.437699 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3587 09:29:13.437792
3588 09:29:13.440703 [DATLAT]
3589 09:29:13.440770 Freq=1200, CH1 RK1
3590 09:29:13.440832
3591 09:29:13.443775 DATLAT Default: 0xd
3592 09:29:13.443841 0, 0xFFFF, sum = 0
3593 09:29:13.447665 1, 0xFFFF, sum = 0
3594 09:29:13.447732 2, 0xFFFF, sum = 0
3595 09:29:13.450749 3, 0xFFFF, sum = 0
3596 09:29:13.450830 4, 0xFFFF, sum = 0
3597 09:29:13.454328 5, 0xFFFF, sum = 0
3598 09:29:13.454400 6, 0xFFFF, sum = 0
3599 09:29:13.457325 7, 0xFFFF, sum = 0
3600 09:29:13.457424 8, 0xFFFF, sum = 0
3601 09:29:13.460695 9, 0xFFFF, sum = 0
3602 09:29:13.464042 10, 0xFFFF, sum = 0
3603 09:29:13.464114 11, 0xFFFF, sum = 0
3604 09:29:13.467469 12, 0x0, sum = 1
3605 09:29:13.467543 13, 0x0, sum = 2
3606 09:29:13.467600 14, 0x0, sum = 3
3607 09:29:13.471051 15, 0x0, sum = 4
3608 09:29:13.471117 best_step = 13
3609 09:29:13.471176
3610 09:29:13.471229 ==
3611 09:29:13.474133 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 09:29:13.480434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 09:29:13.480506 ==
3614 09:29:13.480564 RX Vref Scan: 0
3615 09:29:13.480618
3616 09:29:13.484162 RX Vref 0 -> 0, step: 1
3617 09:29:13.484226
3618 09:29:13.487276 RX Delay -21 -> 252, step: 4
3619 09:29:13.490422 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3620 09:29:13.494158 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3621 09:29:13.500892 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3622 09:29:13.503920 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3623 09:29:13.507552 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3624 09:29:13.510691 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3625 09:29:13.513577 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3626 09:29:13.520491 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3627 09:29:13.524174 iDelay=191, Bit 8, Center 94 (27 ~ 162) 136
3628 09:29:13.527250 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3629 09:29:13.530352 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3630 09:29:13.533722 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3631 09:29:13.540640 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3632 09:29:13.543966 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3633 09:29:13.547182 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3634 09:29:13.550383 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3635 09:29:13.550451 ==
3636 09:29:13.554130 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 09:29:13.557100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 09:29:13.560688 ==
3639 09:29:13.560777 DQS Delay:
3640 09:29:13.560858 DQS0 = 0, DQS1 = 0
3641 09:29:13.564326 DQM Delay:
3642 09:29:13.564395 DQM0 = 113, DQM1 = 108
3643 09:29:13.567477 DQ Delay:
3644 09:29:13.570513 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3645 09:29:13.574205 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =110
3646 09:29:13.577086 DQ8 =94, DQ9 =98, DQ10 =110, DQ11 =100
3647 09:29:13.580358 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =116
3648 09:29:13.580425
3649 09:29:13.580480
3650 09:29:13.587303 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3651 09:29:13.590909 CH1 RK1: MR19=304, MR18=FB02
3652 09:29:13.597076 CH1_RK1: MR19=0x304, MR18=0xFB02, DQSOSC=409, MR23=63, INC=39, DEC=26
3653 09:29:13.600778 [RxdqsGatingPostProcess] freq 1200
3654 09:29:13.607706 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3655 09:29:13.610706 best DQS0 dly(2T, 0.5T) = (0, 11)
3656 09:29:13.610779 best DQS1 dly(2T, 0.5T) = (0, 11)
3657 09:29:13.614180 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3658 09:29:13.617600 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3659 09:29:13.620668 best DQS0 dly(2T, 0.5T) = (0, 11)
3660 09:29:13.623770 best DQS1 dly(2T, 0.5T) = (0, 11)
3661 09:29:13.627476 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3662 09:29:13.630599 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3663 09:29:13.634254 Pre-setting of DQS Precalculation
3664 09:29:13.640614 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3665 09:29:13.647254 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3666 09:29:13.654080 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3667 09:29:13.654151
3668 09:29:13.654209
3669 09:29:13.657419 [Calibration Summary] 2400 Mbps
3670 09:29:13.657517 CH 0, Rank 0
3671 09:29:13.660801 SW Impedance : PASS
3672 09:29:13.663748 DUTY Scan : NO K
3673 09:29:13.663817 ZQ Calibration : PASS
3674 09:29:13.667221 Jitter Meter : NO K
3675 09:29:13.667295 CBT Training : PASS
3676 09:29:13.670555 Write leveling : PASS
3677 09:29:13.673818 RX DQS gating : PASS
3678 09:29:13.673915 RX DQ/DQS(RDDQC) : PASS
3679 09:29:13.677513 TX DQ/DQS : PASS
3680 09:29:13.680425 RX DATLAT : PASS
3681 09:29:13.680493 RX DQ/DQS(Engine): PASS
3682 09:29:13.684083 TX OE : NO K
3683 09:29:13.684150 All Pass.
3684 09:29:13.684212
3685 09:29:13.687061 CH 0, Rank 1
3686 09:29:13.687157 SW Impedance : PASS
3687 09:29:13.690554 DUTY Scan : NO K
3688 09:29:13.694133 ZQ Calibration : PASS
3689 09:29:13.694217 Jitter Meter : NO K
3690 09:29:13.697451 CBT Training : PASS
3691 09:29:13.700487 Write leveling : PASS
3692 09:29:13.700558 RX DQS gating : PASS
3693 09:29:13.704138 RX DQ/DQS(RDDQC) : PASS
3694 09:29:13.707281 TX DQ/DQS : PASS
3695 09:29:13.707349 RX DATLAT : PASS
3696 09:29:13.710422 RX DQ/DQS(Engine): PASS
3697 09:29:13.710494 TX OE : NO K
3698 09:29:13.714131 All Pass.
3699 09:29:13.714195
3700 09:29:13.714256 CH 1, Rank 0
3701 09:29:13.717208 SW Impedance : PASS
3702 09:29:13.717273 DUTY Scan : NO K
3703 09:29:13.721063 ZQ Calibration : PASS
3704 09:29:13.723905 Jitter Meter : NO K
3705 09:29:13.723970 CBT Training : PASS
3706 09:29:13.727550 Write leveling : PASS
3707 09:29:13.730680 RX DQS gating : PASS
3708 09:29:13.730749 RX DQ/DQS(RDDQC) : PASS
3709 09:29:13.733672 TX DQ/DQS : PASS
3710 09:29:13.737096 RX DATLAT : PASS
3711 09:29:13.737171 RX DQ/DQS(Engine): PASS
3712 09:29:13.740429 TX OE : NO K
3713 09:29:13.740498 All Pass.
3714 09:29:13.740561
3715 09:29:13.744155 CH 1, Rank 1
3716 09:29:13.744218 SW Impedance : PASS
3717 09:29:13.747285 DUTY Scan : NO K
3718 09:29:13.750278 ZQ Calibration : PASS
3719 09:29:13.750345 Jitter Meter : NO K
3720 09:29:13.753956 CBT Training : PASS
3721 09:29:13.757099 Write leveling : PASS
3722 09:29:13.757164 RX DQS gating : PASS
3723 09:29:13.760867 RX DQ/DQS(RDDQC) : PASS
3724 09:29:13.760931 TX DQ/DQS : PASS
3725 09:29:13.763705 RX DATLAT : PASS
3726 09:29:13.766927 RX DQ/DQS(Engine): PASS
3727 09:29:13.766993 TX OE : NO K
3728 09:29:13.770257 All Pass.
3729 09:29:13.770323
3730 09:29:13.770384 DramC Write-DBI off
3731 09:29:13.774264 PER_BANK_REFRESH: Hybrid Mode
3732 09:29:13.777299 TX_TRACKING: ON
3733 09:29:13.783699 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3734 09:29:13.787306 [FAST_K] Save calibration result to emmc
3735 09:29:13.790416 dramc_set_vcore_voltage set vcore to 650000
3736 09:29:13.793640 Read voltage for 600, 5
3737 09:29:13.793716 Vio18 = 0
3738 09:29:13.797312 Vcore = 650000
3739 09:29:13.797388 Vdram = 0
3740 09:29:13.797447 Vddq = 0
3741 09:29:13.800318 Vmddr = 0
3742 09:29:13.803804 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3743 09:29:13.810469 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3744 09:29:13.810550 MEM_TYPE=3, freq_sel=19
3745 09:29:13.813462 sv_algorithm_assistance_LP4_1600
3746 09:29:13.820587 ============ PULL DRAM RESETB DOWN ============
3747 09:29:13.823676 ========== PULL DRAM RESETB DOWN end =========
3748 09:29:13.827412 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3749 09:29:13.830269 ===================================
3750 09:29:13.833801 LPDDR4 DRAM CONFIGURATION
3751 09:29:13.837388 ===================================
3752 09:29:13.837464 EX_ROW_EN[0] = 0x0
3753 09:29:13.840544 EX_ROW_EN[1] = 0x0
3754 09:29:13.844095 LP4Y_EN = 0x0
3755 09:29:13.844172 WORK_FSP = 0x0
3756 09:29:13.847115 WL = 0x2
3757 09:29:13.847191 RL = 0x2
3758 09:29:13.850312 BL = 0x2
3759 09:29:13.850408 RPST = 0x0
3760 09:29:13.853934 RD_PRE = 0x0
3761 09:29:13.854057 WR_PRE = 0x1
3762 09:29:13.857197 WR_PST = 0x0
3763 09:29:13.857274 DBI_WR = 0x0
3764 09:29:13.860815 DBI_RD = 0x0
3765 09:29:13.860892 OTF = 0x1
3766 09:29:13.863897 ===================================
3767 09:29:13.867197 ===================================
3768 09:29:13.871041 ANA top config
3769 09:29:13.873887 ===================================
3770 09:29:13.874010 DLL_ASYNC_EN = 0
3771 09:29:13.877423 ALL_SLAVE_EN = 1
3772 09:29:13.880744 NEW_RANK_MODE = 1
3773 09:29:13.884109 DLL_IDLE_MODE = 1
3774 09:29:13.884186 LP45_APHY_COMB_EN = 1
3775 09:29:13.887424 TX_ODT_DIS = 1
3776 09:29:13.890661 NEW_8X_MODE = 1
3777 09:29:13.893775 ===================================
3778 09:29:13.897037 ===================================
3779 09:29:13.900681 data_rate = 1200
3780 09:29:13.903775 CKR = 1
3781 09:29:13.907520 DQ_P2S_RATIO = 8
3782 09:29:13.910537 ===================================
3783 09:29:13.910608 CA_P2S_RATIO = 8
3784 09:29:13.913655 DQ_CA_OPEN = 0
3785 09:29:13.917387 DQ_SEMI_OPEN = 0
3786 09:29:13.920677 CA_SEMI_OPEN = 0
3787 09:29:13.924038 CA_FULL_RATE = 0
3788 09:29:13.927016 DQ_CKDIV4_EN = 1
3789 09:29:13.927086 CA_CKDIV4_EN = 1
3790 09:29:13.930207 CA_PREDIV_EN = 0
3791 09:29:13.933304 PH8_DLY = 0
3792 09:29:13.936882 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3793 09:29:13.940351 DQ_AAMCK_DIV = 4
3794 09:29:13.943820 CA_AAMCK_DIV = 4
3795 09:29:13.943886 CA_ADMCK_DIV = 4
3796 09:29:13.946776 DQ_TRACK_CA_EN = 0
3797 09:29:13.950517 CA_PICK = 600
3798 09:29:13.953519 CA_MCKIO = 600
3799 09:29:13.957176 MCKIO_SEMI = 0
3800 09:29:13.960132 PLL_FREQ = 2288
3801 09:29:13.963900 DQ_UI_PI_RATIO = 32
3802 09:29:13.963971 CA_UI_PI_RATIO = 0
3803 09:29:13.967140 ===================================
3804 09:29:13.970155 ===================================
3805 09:29:13.973780 memory_type:LPDDR4
3806 09:29:13.976852 GP_NUM : 10
3807 09:29:13.976918 SRAM_EN : 1
3808 09:29:13.980091 MD32_EN : 0
3809 09:29:13.983836 ===================================
3810 09:29:13.987284 [ANA_INIT] >>>>>>>>>>>>>>
3811 09:29:13.987351 <<<<<< [CONFIGURE PHASE]: ANA_TX
3812 09:29:13.990643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3813 09:29:13.993788 ===================================
3814 09:29:13.996839 data_rate = 1200,PCW = 0X5800
3815 09:29:14.000239 ===================================
3816 09:29:14.003597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3817 09:29:14.010574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3818 09:29:14.017188 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3819 09:29:14.020393 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3820 09:29:14.023572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3821 09:29:14.027068 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3822 09:29:14.030640 [ANA_INIT] flow start
3823 09:29:14.030707 [ANA_INIT] PLL >>>>>>>>
3824 09:29:14.033854 [ANA_INIT] PLL <<<<<<<<
3825 09:29:14.036982 [ANA_INIT] MIDPI >>>>>>>>
3826 09:29:14.037046 [ANA_INIT] MIDPI <<<<<<<<
3827 09:29:14.040608 [ANA_INIT] DLL >>>>>>>>
3828 09:29:14.043877 [ANA_INIT] flow end
3829 09:29:14.047486 ============ LP4 DIFF to SE enter ============
3830 09:29:14.050201 ============ LP4 DIFF to SE exit ============
3831 09:29:14.054106 [ANA_INIT] <<<<<<<<<<<<<
3832 09:29:14.057159 [Flow] Enable top DCM control >>>>>
3833 09:29:14.060258 [Flow] Enable top DCM control <<<<<
3834 09:29:14.063876 Enable DLL master slave shuffle
3835 09:29:14.067033 ==============================================================
3836 09:29:14.070259 Gating Mode config
3837 09:29:14.077070 ==============================================================
3838 09:29:14.077142 Config description:
3839 09:29:14.087213 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3840 09:29:14.093985 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3841 09:29:14.097006 SELPH_MODE 0: By rank 1: By Phase
3842 09:29:14.103817 ==============================================================
3843 09:29:14.107040 GAT_TRACK_EN = 1
3844 09:29:14.110657 RX_GATING_MODE = 2
3845 09:29:14.114241 RX_GATING_TRACK_MODE = 2
3846 09:29:14.117045 SELPH_MODE = 1
3847 09:29:14.120811 PICG_EARLY_EN = 1
3848 09:29:14.120881 VALID_LAT_VALUE = 1
3849 09:29:14.127322 ==============================================================
3850 09:29:14.130457 Enter into Gating configuration >>>>
3851 09:29:14.134354 Exit from Gating configuration <<<<
3852 09:29:14.137406 Enter into DVFS_PRE_config >>>>>
3853 09:29:14.147178 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3854 09:29:14.150473 Exit from DVFS_PRE_config <<<<<
3855 09:29:14.153733 Enter into PICG configuration >>>>
3856 09:29:14.157357 Exit from PICG configuration <<<<
3857 09:29:14.160323 [RX_INPUT] configuration >>>>>
3858 09:29:14.164158 [RX_INPUT] configuration <<<<<
3859 09:29:14.167469 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3860 09:29:14.173864 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3861 09:29:14.180863 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3862 09:29:14.187083 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3863 09:29:14.194199 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3864 09:29:14.197223 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3865 09:29:14.204102 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3866 09:29:14.207119 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3867 09:29:14.210908 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3868 09:29:14.213947 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3869 09:29:14.220862 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3870 09:29:14.223857 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3871 09:29:14.227330 ===================================
3872 09:29:14.230843 LPDDR4 DRAM CONFIGURATION
3873 09:29:14.234169 ===================================
3874 09:29:14.234247 EX_ROW_EN[0] = 0x0
3875 09:29:14.237218 EX_ROW_EN[1] = 0x0
3876 09:29:14.237295 LP4Y_EN = 0x0
3877 09:29:14.240844 WORK_FSP = 0x0
3878 09:29:14.240921 WL = 0x2
3879 09:29:14.244457 RL = 0x2
3880 09:29:14.244552 BL = 0x2
3881 09:29:14.247685 RPST = 0x0
3882 09:29:14.247762 RD_PRE = 0x0
3883 09:29:14.250682 WR_PRE = 0x1
3884 09:29:14.250759 WR_PST = 0x0
3885 09:29:14.254417 DBI_WR = 0x0
3886 09:29:14.254496 DBI_RD = 0x0
3887 09:29:14.257862 OTF = 0x1
3888 09:29:14.261260 ===================================
3889 09:29:14.264487 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3890 09:29:14.267482 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3891 09:29:14.274557 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3892 09:29:14.277632 ===================================
3893 09:29:14.277709 LPDDR4 DRAM CONFIGURATION
3894 09:29:14.280699 ===================================
3895 09:29:14.284218 EX_ROW_EN[0] = 0x10
3896 09:29:14.287892 EX_ROW_EN[1] = 0x0
3897 09:29:14.287969 LP4Y_EN = 0x0
3898 09:29:14.291036 WORK_FSP = 0x0
3899 09:29:14.291112 WL = 0x2
3900 09:29:14.294037 RL = 0x2
3901 09:29:14.294130 BL = 0x2
3902 09:29:14.297778 RPST = 0x0
3903 09:29:14.297854 RD_PRE = 0x0
3904 09:29:14.300866 WR_PRE = 0x1
3905 09:29:14.300942 WR_PST = 0x0
3906 09:29:14.304446 DBI_WR = 0x0
3907 09:29:14.304522 DBI_RD = 0x0
3908 09:29:14.307634 OTF = 0x1
3909 09:29:14.310688 ===================================
3910 09:29:14.317541 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3911 09:29:14.320569 nWR fixed to 30
3912 09:29:14.320649 [ModeRegInit_LP4] CH0 RK0
3913 09:29:14.324300 [ModeRegInit_LP4] CH0 RK1
3914 09:29:14.327418 [ModeRegInit_LP4] CH1 RK0
3915 09:29:14.330478 [ModeRegInit_LP4] CH1 RK1
3916 09:29:14.330566 match AC timing 17
3917 09:29:14.333969 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3918 09:29:14.340696 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3919 09:29:14.343988 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3920 09:29:14.347333 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3921 09:29:14.353848 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3922 09:29:14.353946 ==
3923 09:29:14.357172 Dram Type= 6, Freq= 0, CH_0, rank 0
3924 09:29:14.360932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3925 09:29:14.361004 ==
3926 09:29:14.367595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3927 09:29:14.370804 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3928 09:29:14.375221 [CA 0] Center 36 (6~66) winsize 61
3929 09:29:14.379026 [CA 1] Center 36 (6~66) winsize 61
3930 09:29:14.382022 [CA 2] Center 34 (4~65) winsize 62
3931 09:29:14.385447 [CA 3] Center 34 (4~65) winsize 62
3932 09:29:14.388420 [CA 4] Center 33 (3~64) winsize 62
3933 09:29:14.391998 [CA 5] Center 33 (3~64) winsize 62
3934 09:29:14.392067
3935 09:29:14.395128 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3936 09:29:14.395200
3937 09:29:14.398530 [CATrainingPosCal] consider 1 rank data
3938 09:29:14.402418 u2DelayCellTimex100 = 270/100 ps
3939 09:29:14.405400 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3940 09:29:14.408460 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3941 09:29:14.415444 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3942 09:29:14.418478 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3943 09:29:14.422061 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3944 09:29:14.425074 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3945 09:29:14.425144
3946 09:29:14.428877 CA PerBit enable=1, Macro0, CA PI delay=33
3947 09:29:14.428948
3948 09:29:14.432029 [CBTSetCACLKResult] CA Dly = 33
3949 09:29:14.432103 CS Dly: 5 (0~36)
3950 09:29:14.434981 ==
3951 09:29:14.435051 Dram Type= 6, Freq= 0, CH_0, rank 1
3952 09:29:14.442101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3953 09:29:14.442176 ==
3954 09:29:14.445304 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3955 09:29:14.452023 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3956 09:29:14.455570 [CA 0] Center 36 (6~66) winsize 61
3957 09:29:14.458972 [CA 1] Center 36 (6~66) winsize 61
3958 09:29:14.461885 [CA 2] Center 34 (4~65) winsize 62
3959 09:29:14.465252 [CA 3] Center 34 (4~65) winsize 62
3960 09:29:14.469172 [CA 4] Center 33 (3~64) winsize 62
3961 09:29:14.472122 [CA 5] Center 33 (3~64) winsize 62
3962 09:29:14.472193
3963 09:29:14.475432 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3964 09:29:14.475530
3965 09:29:14.478473 [CATrainingPosCal] consider 2 rank data
3966 09:29:14.481992 u2DelayCellTimex100 = 270/100 ps
3967 09:29:14.485283 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3968 09:29:14.489070 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3969 09:29:14.495686 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3970 09:29:14.498696 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3971 09:29:14.502174 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 09:29:14.505471 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3973 09:29:14.505539
3974 09:29:14.508922 CA PerBit enable=1, Macro0, CA PI delay=33
3975 09:29:14.508992
3976 09:29:14.511810 [CBTSetCACLKResult] CA Dly = 33
3977 09:29:14.511882 CS Dly: 5 (0~36)
3978 09:29:14.511940
3979 09:29:14.515535 ----->DramcWriteLeveling(PI) begin...
3980 09:29:14.518694 ==
3981 09:29:14.518779 Dram Type= 6, Freq= 0, CH_0, rank 0
3982 09:29:14.525829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3983 09:29:14.525929 ==
3984 09:29:14.528983 Write leveling (Byte 0): 31 => 31
3985 09:29:14.532394 Write leveling (Byte 1): 29 => 29
3986 09:29:14.532472 DramcWriteLeveling(PI) end<-----
3987 09:29:14.535441
3988 09:29:14.535518 ==
3989 09:29:14.538781 Dram Type= 6, Freq= 0, CH_0, rank 0
3990 09:29:14.542479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3991 09:29:14.542557 ==
3992 09:29:14.545595 [Gating] SW mode calibration
3993 09:29:14.552046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3994 09:29:14.555136 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3995 09:29:14.562230 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3996 09:29:14.565850 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3997 09:29:14.568850 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3998 09:29:14.575677 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
3999 09:29:14.579224 0 9 16 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (1 0)
4000 09:29:14.582110 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4001 09:29:14.588798 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4002 09:29:14.592226 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4003 09:29:14.595383 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 09:29:14.602101 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 09:29:14.605819 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 09:29:14.608997 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4007 09:29:14.615526 0 10 16 | B1->B0 | 3232 3a3a | 0 0 | (0 0) (0 0)
4008 09:29:14.618814 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4009 09:29:14.622305 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 09:29:14.625898 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 09:29:14.632521 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 09:29:14.635824 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 09:29:14.638948 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 09:29:14.645969 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 09:29:14.649341 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4016 09:29:14.652487 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 09:29:14.659231 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 09:29:14.662322 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 09:29:14.665921 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 09:29:14.672575 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 09:29:14.676065 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 09:29:14.678856 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 09:29:14.685614 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 09:29:14.689058 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 09:29:14.692189 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 09:29:14.698979 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 09:29:14.702730 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 09:29:14.706451 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 09:29:14.712824 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 09:29:14.715811 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 09:29:14.719380 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4032 09:29:14.722485 Total UI for P1: 0, mck2ui 16
4033 09:29:14.726111 best dqsien dly found for B0: ( 0, 13, 14)
4034 09:29:14.729147 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4035 09:29:14.736213 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 09:29:14.739203 Total UI for P1: 0, mck2ui 16
4037 09:29:14.742403 best dqsien dly found for B1: ( 0, 13, 18)
4038 09:29:14.746190 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4039 09:29:14.749528 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4040 09:29:14.750041
4041 09:29:14.752529 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4042 09:29:14.756261 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4043 09:29:14.759297 [Gating] SW calibration Done
4044 09:29:14.759693 ==
4045 09:29:14.762355 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 09:29:14.765794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 09:29:14.766281 ==
4048 09:29:14.769117 RX Vref Scan: 0
4049 09:29:14.769565
4050 09:29:14.772731 RX Vref 0 -> 0, step: 1
4051 09:29:14.773175
4052 09:29:14.773479 RX Delay -230 -> 252, step: 16
4053 09:29:14.779165 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4054 09:29:14.782458 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4055 09:29:14.785493 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4056 09:29:14.789148 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4057 09:29:14.795765 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4058 09:29:14.799126 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4059 09:29:14.802421 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4060 09:29:14.805672 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4061 09:29:14.809381 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4062 09:29:14.816003 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4063 09:29:14.819130 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4064 09:29:14.822407 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4065 09:29:14.825925 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4066 09:29:14.832594 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4067 09:29:14.835806 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4068 09:29:14.839418 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4069 09:29:14.839816 ==
4070 09:29:14.842411 Dram Type= 6, Freq= 0, CH_0, rank 0
4071 09:29:14.845792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4072 09:29:14.846328 ==
4073 09:29:14.849406 DQS Delay:
4074 09:29:14.849879 DQS0 = 0, DQS1 = 0
4075 09:29:14.852663 DQM Delay:
4076 09:29:14.853100 DQM0 = 42, DQM1 = 34
4077 09:29:14.853408 DQ Delay:
4078 09:29:14.855641 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4079 09:29:14.858988 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4080 09:29:14.862749 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4081 09:29:14.865886 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4082 09:29:14.866480
4083 09:29:14.867052
4084 09:29:14.869570 ==
4085 09:29:14.869967 Dram Type= 6, Freq= 0, CH_0, rank 0
4086 09:29:14.875671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4087 09:29:14.876117 ==
4088 09:29:14.876457
4089 09:29:14.876753
4090 09:29:14.879278 TX Vref Scan disable
4091 09:29:14.879677 == TX Byte 0 ==
4092 09:29:14.882463 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4093 09:29:14.888963 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4094 09:29:14.889428 == TX Byte 1 ==
4095 09:29:14.892740 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4096 09:29:14.899264 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4097 09:29:14.899667 ==
4098 09:29:14.902446 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 09:29:14.906105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 09:29:14.906580 ==
4101 09:29:14.906889
4102 09:29:14.907172
4103 09:29:14.909148 TX Vref Scan disable
4104 09:29:14.912368 == TX Byte 0 ==
4105 09:29:14.916120 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4106 09:29:14.919197 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4107 09:29:14.922458 == TX Byte 1 ==
4108 09:29:14.926018 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4109 09:29:14.929233 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4110 09:29:14.929701
4111 09:29:14.932430 [DATLAT]
4112 09:29:14.932825 Freq=600, CH0 RK0
4113 09:29:14.933137
4114 09:29:14.935853 DATLAT Default: 0x9
4115 09:29:14.936251 0, 0xFFFF, sum = 0
4116 09:29:14.939339 1, 0xFFFF, sum = 0
4117 09:29:14.939745 2, 0xFFFF, sum = 0
4118 09:29:14.942261 3, 0xFFFF, sum = 0
4119 09:29:14.942668 4, 0xFFFF, sum = 0
4120 09:29:14.946043 5, 0xFFFF, sum = 0
4121 09:29:14.946529 6, 0xFFFF, sum = 0
4122 09:29:14.949024 7, 0xFFFF, sum = 0
4123 09:29:14.949429 8, 0x0, sum = 1
4124 09:29:14.952893 9, 0x0, sum = 2
4125 09:29:14.953351 10, 0x0, sum = 3
4126 09:29:14.955804 11, 0x0, sum = 4
4127 09:29:14.956207 best_step = 9
4128 09:29:14.956530
4129 09:29:14.956814 ==
4130 09:29:14.959637 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 09:29:14.962936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 09:29:14.963427 ==
4133 09:29:14.966088 RX Vref Scan: 1
4134 09:29:14.966489
4135 09:29:14.969163 RX Vref 0 -> 0, step: 1
4136 09:29:14.969558
4137 09:29:14.969865 RX Delay -195 -> 252, step: 8
4138 09:29:14.970208
4139 09:29:14.972220 Set Vref, RX VrefLevel [Byte0]: 52
4140 09:29:14.975774 [Byte1]: 50
4141 09:29:14.980130
4142 09:29:14.980524 Final RX Vref Byte 0 = 52 to rank0
4143 09:29:14.983775 Final RX Vref Byte 1 = 50 to rank0
4144 09:29:14.987022 Final RX Vref Byte 0 = 52 to rank1
4145 09:29:14.990611 Final RX Vref Byte 1 = 50 to rank1==
4146 09:29:14.993594 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 09:29:15.000492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 09:29:15.000969 ==
4149 09:29:15.001288 DQS Delay:
4150 09:29:15.001578 DQS0 = 0, DQS1 = 0
4151 09:29:15.004084 DQM Delay:
4152 09:29:15.004523 DQM0 = 42, DQM1 = 33
4153 09:29:15.006748 DQ Delay:
4154 09:29:15.010686 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4155 09:29:15.011087 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4156 09:29:15.013699 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4157 09:29:15.017806 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4158 09:29:15.020795
4159 09:29:15.021284
4160 09:29:15.027396 [DQSOSCAuto] RK0, (LSB)MR18= 0x4120, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
4161 09:29:15.030543 CH0 RK0: MR19=808, MR18=4120
4162 09:29:15.037563 CH0_RK0: MR19=0x808, MR18=0x4120, DQSOSC=397, MR23=63, INC=166, DEC=110
4163 09:29:15.038091
4164 09:29:15.040847 ----->DramcWriteLeveling(PI) begin...
4165 09:29:15.041338 ==
4166 09:29:15.043674 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 09:29:15.047700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 09:29:15.048226 ==
4169 09:29:15.050570 Write leveling (Byte 0): 32 => 32
4170 09:29:15.053676 Write leveling (Byte 1): 32 => 32
4171 09:29:15.057437 DramcWriteLeveling(PI) end<-----
4172 09:29:15.057977
4173 09:29:15.058377 ==
4174 09:29:15.060708 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 09:29:15.063618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 09:29:15.064060 ==
4177 09:29:15.067267 [Gating] SW mode calibration
4178 09:29:15.074017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4179 09:29:15.080320 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4180 09:29:15.083688 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4181 09:29:15.086935 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4182 09:29:15.093526 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 09:29:15.097124 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
4184 09:29:15.100949 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
4185 09:29:15.107173 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 09:29:15.110749 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4187 09:29:15.113607 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 09:29:15.120152 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 09:29:15.124070 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 09:29:15.127133 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 09:29:15.134042 0 10 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4192 09:29:15.137438 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
4193 09:29:15.140424 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 09:29:15.144218 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 09:29:15.150471 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 09:29:15.153785 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 09:29:15.157567 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 09:29:15.163994 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 09:29:15.167240 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4200 09:29:15.170321 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4201 09:29:15.177232 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4202 09:29:15.180583 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 09:29:15.184384 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 09:29:15.190470 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 09:29:15.194036 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 09:29:15.197740 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 09:29:15.203964 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 09:29:15.207074 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 09:29:15.210783 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 09:29:15.217210 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 09:29:15.220671 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 09:29:15.223582 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 09:29:15.230412 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 09:29:15.234309 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4215 09:29:15.237422 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4216 09:29:15.240530 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4217 09:29:15.244295 Total UI for P1: 0, mck2ui 16
4218 09:29:15.247254 best dqsien dly found for B0: ( 0, 13, 10)
4219 09:29:15.254319 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4220 09:29:15.257312 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 09:29:15.260377 Total UI for P1: 0, mck2ui 16
4222 09:29:15.264216 best dqsien dly found for B1: ( 0, 13, 18)
4223 09:29:15.267122 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4224 09:29:15.270954 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4225 09:29:15.271364
4226 09:29:15.274168 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4227 09:29:15.277390 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4228 09:29:15.280745 [Gating] SW calibration Done
4229 09:29:15.281155 ==
4230 09:29:15.283537 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 09:29:15.290678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 09:29:15.291078 ==
4233 09:29:15.291384 RX Vref Scan: 0
4234 09:29:15.291667
4235 09:29:15.293661 RX Vref 0 -> 0, step: 1
4236 09:29:15.294106
4237 09:29:15.297096 RX Delay -230 -> 252, step: 16
4238 09:29:15.300426 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4239 09:29:15.303898 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4240 09:29:15.307123 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4241 09:29:15.313632 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4242 09:29:15.317366 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4243 09:29:15.320415 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4244 09:29:15.323872 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4245 09:29:15.327107 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4246 09:29:15.334278 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4247 09:29:15.337381 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4248 09:29:15.340569 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4249 09:29:15.344125 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4250 09:29:15.350859 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4251 09:29:15.354103 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4252 09:29:15.357047 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4253 09:29:15.360735 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4254 09:29:15.361128 ==
4255 09:29:15.363889 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 09:29:15.370506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 09:29:15.370789 ==
4258 09:29:15.371006 DQS Delay:
4259 09:29:15.373615 DQS0 = 0, DQS1 = 0
4260 09:29:15.373889 DQM Delay:
4261 09:29:15.374132 DQM0 = 38, DQM1 = 29
4262 09:29:15.377372 DQ Delay:
4263 09:29:15.380581 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4264 09:29:15.383802 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4265 09:29:15.387707 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4266 09:29:15.390519 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4267 09:29:15.390802
4268 09:29:15.391011
4269 09:29:15.391209 ==
4270 09:29:15.393641 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 09:29:15.397121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 09:29:15.397400 ==
4273 09:29:15.397612
4274 09:29:15.397808
4275 09:29:15.400771 TX Vref Scan disable
4276 09:29:15.401049 == TX Byte 0 ==
4277 09:29:15.407441 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4278 09:29:15.411052 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4279 09:29:15.411509 == TX Byte 1 ==
4280 09:29:15.417031 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4281 09:29:15.420618 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4282 09:29:15.420899 ==
4283 09:29:15.424190 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 09:29:15.427531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 09:29:15.427982 ==
4286 09:29:15.428428
4287 09:29:15.428711
4288 09:29:15.430442 TX Vref Scan disable
4289 09:29:15.433951 == TX Byte 0 ==
4290 09:29:15.437212 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4291 09:29:15.440851 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4292 09:29:15.443955 == TX Byte 1 ==
4293 09:29:15.447026 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4294 09:29:15.450897 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4295 09:29:15.451294
4296 09:29:15.454374 [DATLAT]
4297 09:29:15.454767 Freq=600, CH0 RK1
4298 09:29:15.455075
4299 09:29:15.457554 DATLAT Default: 0x9
4300 09:29:15.457947 0, 0xFFFF, sum = 0
4301 09:29:15.460688 1, 0xFFFF, sum = 0
4302 09:29:15.461087 2, 0xFFFF, sum = 0
4303 09:29:15.464266 3, 0xFFFF, sum = 0
4304 09:29:15.464666 4, 0xFFFF, sum = 0
4305 09:29:15.467415 5, 0xFFFF, sum = 0
4306 09:29:15.467816 6, 0xFFFF, sum = 0
4307 09:29:15.471451 7, 0xFFFF, sum = 0
4308 09:29:15.471930 8, 0x0, sum = 1
4309 09:29:15.474584 9, 0x0, sum = 2
4310 09:29:15.475062 10, 0x0, sum = 3
4311 09:29:15.478111 11, 0x0, sum = 4
4312 09:29:15.478597 best_step = 9
4313 09:29:15.478907
4314 09:29:15.479186 ==
4315 09:29:15.480889 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 09:29:15.484131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 09:29:15.488162 ==
4318 09:29:15.488640 RX Vref Scan: 0
4319 09:29:15.488944
4320 09:29:15.491254 RX Vref 0 -> 0, step: 1
4321 09:29:15.491735
4322 09:29:15.494094 RX Delay -195 -> 252, step: 8
4323 09:29:15.497295 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4324 09:29:15.500731 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4325 09:29:15.508111 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4326 09:29:15.510847 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4327 09:29:15.514928 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4328 09:29:15.517673 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4329 09:29:15.521108 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4330 09:29:15.528025 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4331 09:29:15.530950 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4332 09:29:15.533912 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4333 09:29:15.537464 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4334 09:29:15.544396 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4335 09:29:15.547349 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4336 09:29:15.550884 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4337 09:29:15.554163 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4338 09:29:15.560813 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4339 09:29:15.561206 ==
4340 09:29:15.564194 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 09:29:15.567738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 09:29:15.568268 ==
4343 09:29:15.568591 DQS Delay:
4344 09:29:15.570849 DQS0 = 0, DQS1 = 0
4345 09:29:15.571241 DQM Delay:
4346 09:29:15.574619 DQM0 = 40, DQM1 = 33
4347 09:29:15.575011 DQ Delay:
4348 09:29:15.577702 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4349 09:29:15.580976 DQ4 =36, DQ5 =28, DQ6 =52, DQ7 =48
4350 09:29:15.584614 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4351 09:29:15.587798 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4352 09:29:15.588191
4353 09:29:15.588491
4354 09:29:15.594758 [DQSOSCAuto] RK1, (LSB)MR18= 0x4e31, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4355 09:29:15.597861 CH0 RK1: MR19=808, MR18=4E31
4356 09:29:15.604810 CH0_RK1: MR19=0x808, MR18=0x4E31, DQSOSC=395, MR23=63, INC=168, DEC=112
4357 09:29:15.607750 [RxdqsGatingPostProcess] freq 600
4358 09:29:15.614353 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4359 09:29:15.614764 Pre-setting of DQS Precalculation
4360 09:29:15.621464 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4361 09:29:15.621914 ==
4362 09:29:15.624550 Dram Type= 6, Freq= 0, CH_1, rank 0
4363 09:29:15.627602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 09:29:15.628013 ==
4365 09:29:15.634854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 09:29:15.641115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4367 09:29:15.644506 [CA 0] Center 35 (5~66) winsize 62
4368 09:29:15.647762 [CA 1] Center 35 (5~66) winsize 62
4369 09:29:15.651111 [CA 2] Center 34 (4~65) winsize 62
4370 09:29:15.654627 [CA 3] Center 33 (3~64) winsize 62
4371 09:29:15.657898 [CA 4] Center 33 (3~64) winsize 62
4372 09:29:15.661276 [CA 5] Center 33 (3~64) winsize 62
4373 09:29:15.661767
4374 09:29:15.664944 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4375 09:29:15.665432
4376 09:29:15.667611 [CATrainingPosCal] consider 1 rank data
4377 09:29:15.671121 u2DelayCellTimex100 = 270/100 ps
4378 09:29:15.674495 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4379 09:29:15.677919 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4380 09:29:15.681347 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4381 09:29:15.684323 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4382 09:29:15.687479 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4383 09:29:15.691092 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4384 09:29:15.691488
4385 09:29:15.694668 CA PerBit enable=1, Macro0, CA PI delay=33
4386 09:29:15.695067
4387 09:29:15.698062 [CBTSetCACLKResult] CA Dly = 33
4388 09:29:15.701350 CS Dly: 5 (0~36)
4389 09:29:15.701793 ==
4390 09:29:15.704589 Dram Type= 6, Freq= 0, CH_1, rank 1
4391 09:29:15.708337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 09:29:15.708824 ==
4393 09:29:15.714623 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 09:29:15.721470 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4395 09:29:15.724921 [CA 0] Center 35 (5~66) winsize 62
4396 09:29:15.727867 [CA 1] Center 36 (6~66) winsize 61
4397 09:29:15.731677 [CA 2] Center 34 (3~65) winsize 63
4398 09:29:15.734663 [CA 3] Center 34 (3~65) winsize 63
4399 09:29:15.737759 [CA 4] Center 34 (3~65) winsize 63
4400 09:29:15.741593 [CA 5] Center 33 (3~64) winsize 62
4401 09:29:15.742087
4402 09:29:15.745211 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4403 09:29:15.745608
4404 09:29:15.748002 [CATrainingPosCal] consider 2 rank data
4405 09:29:15.751381 u2DelayCellTimex100 = 270/100 ps
4406 09:29:15.754452 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4407 09:29:15.758156 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4408 09:29:15.761718 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 09:29:15.764468 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4410 09:29:15.768127 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4411 09:29:15.771123 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 09:29:15.771523
4413 09:29:15.775167 CA PerBit enable=1, Macro0, CA PI delay=33
4414 09:29:15.775648
4415 09:29:15.777964 [CBTSetCACLKResult] CA Dly = 33
4416 09:29:15.781577 CS Dly: 5 (0~36)
4417 09:29:15.781971
4418 09:29:15.784731 ----->DramcWriteLeveling(PI) begin...
4419 09:29:15.785130 ==
4420 09:29:15.788204 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 09:29:15.791538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 09:29:15.791994 ==
4423 09:29:15.794532 Write leveling (Byte 0): 30 => 30
4424 09:29:15.797769 Write leveling (Byte 1): 32 => 32
4425 09:29:15.801501 DramcWriteLeveling(PI) end<-----
4426 09:29:15.802066
4427 09:29:15.802470 ==
4428 09:29:15.804455 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 09:29:15.807956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 09:29:15.808366 ==
4431 09:29:15.811433 [Gating] SW mode calibration
4432 09:29:15.817775 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4433 09:29:15.824491 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4434 09:29:15.828160 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 09:29:15.831746 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 09:29:15.838024 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 09:29:15.841557 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
4438 09:29:15.844497 0 9 16 | B1->B0 | 2929 2828 | 0 0 | (1 1) (1 1)
4439 09:29:15.851551 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4440 09:29:15.855226 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 09:29:15.857968 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 09:29:15.864945 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 09:29:15.867997 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 09:29:15.871691 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 09:29:15.878150 0 10 12 | B1->B0 | 2727 2b2b | 0 1 | (0 0) (0 0)
4446 09:29:15.882111 0 10 16 | B1->B0 | 3e3e 3f3f | 0 0 | (0 0) (0 0)
4447 09:29:15.885228 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 09:29:15.892493 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 09:29:15.895235 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 09:29:15.898534 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 09:29:15.901638 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 09:29:15.908209 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 09:29:15.911683 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 09:29:15.915008 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4455 09:29:15.921967 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 09:29:15.925750 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 09:29:15.928248 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 09:29:15.935027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 09:29:15.938188 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 09:29:15.941543 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 09:29:15.948413 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 09:29:15.951519 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 09:29:15.955333 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 09:29:15.961763 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 09:29:15.965295 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 09:29:15.968101 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 09:29:15.974962 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 09:29:15.978252 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 09:29:15.981619 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4470 09:29:15.988012 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 09:29:15.988476 Total UI for P1: 0, mck2ui 16
4472 09:29:15.995238 best dqsien dly found for B0: ( 0, 13, 14)
4473 09:29:15.995719 Total UI for P1: 0, mck2ui 16
4474 09:29:15.998237 best dqsien dly found for B1: ( 0, 13, 12)
4475 09:29:16.005054 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4476 09:29:16.008040 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4477 09:29:16.008439
4478 09:29:16.012041 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4479 09:29:16.014690 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4480 09:29:16.018634 [Gating] SW calibration Done
4481 09:29:16.019109 ==
4482 09:29:16.021556 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 09:29:16.025297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 09:29:16.025780 ==
4485 09:29:16.028455 RX Vref Scan: 0
4486 09:29:16.029088
4487 09:29:16.029528 RX Vref 0 -> 0, step: 1
4488 09:29:16.029873
4489 09:29:16.031379 RX Delay -230 -> 252, step: 16
4490 09:29:16.034869 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4491 09:29:16.041668 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4492 09:29:16.045042 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4493 09:29:16.048566 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4494 09:29:16.051786 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4495 09:29:16.054917 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4496 09:29:16.062085 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4497 09:29:16.065673 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4498 09:29:16.068458 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4499 09:29:16.071388 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4500 09:29:16.078266 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4501 09:29:16.081333 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4502 09:29:16.085108 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4503 09:29:16.088046 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4504 09:29:16.094799 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4505 09:29:16.098646 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4506 09:29:16.099127 ==
4507 09:29:16.101615 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 09:29:16.104711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 09:29:16.105192 ==
4510 09:29:16.105496 DQS Delay:
4511 09:29:16.108530 DQS0 = 0, DQS1 = 0
4512 09:29:16.108937 DQM Delay:
4513 09:29:16.111488 DQM0 = 43, DQM1 = 34
4514 09:29:16.111881 DQ Delay:
4515 09:29:16.115564 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4516 09:29:16.118983 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4517 09:29:16.121789 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4518 09:29:16.125810 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4519 09:29:16.126330
4520 09:29:16.126642
4521 09:29:16.126923 ==
4522 09:29:16.128677 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 09:29:16.131914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 09:29:16.135071 ==
4525 09:29:16.135469
4526 09:29:16.135783
4527 09:29:16.136154 TX Vref Scan disable
4528 09:29:16.138177 == TX Byte 0 ==
4529 09:29:16.141773 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4530 09:29:16.145490 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4531 09:29:16.148130 == TX Byte 1 ==
4532 09:29:16.151909 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4533 09:29:16.155142 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4534 09:29:16.158077 ==
4535 09:29:16.158474 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 09:29:16.165520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 09:29:16.166058 ==
4538 09:29:16.166407
4539 09:29:16.166696
4540 09:29:16.168057 TX Vref Scan disable
4541 09:29:16.168455 == TX Byte 0 ==
4542 09:29:16.174573 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4543 09:29:16.178428 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4544 09:29:16.178959 == TX Byte 1 ==
4545 09:29:16.184920 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4546 09:29:16.188203 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4547 09:29:16.188743
4548 09:29:16.189183 [DATLAT]
4549 09:29:16.191381 Freq=600, CH1 RK0
4550 09:29:16.191907
4551 09:29:16.192353 DATLAT Default: 0x9
4552 09:29:16.195112 0, 0xFFFF, sum = 0
4553 09:29:16.195611 1, 0xFFFF, sum = 0
4554 09:29:16.198115 2, 0xFFFF, sum = 0
4555 09:29:16.198518 3, 0xFFFF, sum = 0
4556 09:29:16.201662 4, 0xFFFF, sum = 0
4557 09:29:16.202169 5, 0xFFFF, sum = 0
4558 09:29:16.205187 6, 0xFFFF, sum = 0
4559 09:29:16.205594 7, 0xFFFF, sum = 0
4560 09:29:16.208121 8, 0x0, sum = 1
4561 09:29:16.208524 9, 0x0, sum = 2
4562 09:29:16.211204 10, 0x0, sum = 3
4563 09:29:16.211608 11, 0x0, sum = 4
4564 09:29:16.215234 best_step = 9
4565 09:29:16.215707
4566 09:29:16.216018 ==
4567 09:29:16.218578 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 09:29:16.221627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 09:29:16.222146 ==
4570 09:29:16.224812 RX Vref Scan: 1
4571 09:29:16.225310
4572 09:29:16.225632 RX Vref 0 -> 0, step: 1
4573 09:29:16.225918
4574 09:29:16.228109 RX Delay -195 -> 252, step: 8
4575 09:29:16.228507
4576 09:29:16.231251 Set Vref, RX VrefLevel [Byte0]: 57
4577 09:29:16.235001 [Byte1]: 51
4578 09:29:16.238601
4579 09:29:16.238995 Final RX Vref Byte 0 = 57 to rank0
4580 09:29:16.242190 Final RX Vref Byte 1 = 51 to rank0
4581 09:29:16.245552 Final RX Vref Byte 0 = 57 to rank1
4582 09:29:16.248683 Final RX Vref Byte 1 = 51 to rank1==
4583 09:29:16.252259 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 09:29:16.258592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 09:29:16.258990 ==
4586 09:29:16.259312 DQS Delay:
4587 09:29:16.259596 DQS0 = 0, DQS1 = 0
4588 09:29:16.261849 DQM Delay:
4589 09:29:16.262282 DQM0 = 41, DQM1 = 32
4590 09:29:16.265435 DQ Delay:
4591 09:29:16.269066 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4592 09:29:16.269542 DQ4 =40, DQ5 =52, DQ6 =52, DQ7 =36
4593 09:29:16.272043 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4594 09:29:16.275957 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4595 09:29:16.276440
4596 09:29:16.278615
4597 09:29:16.285319 [DQSOSCAuto] RK0, (LSB)MR18= 0x4308, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4598 09:29:16.289066 CH1 RK0: MR19=808, MR18=4308
4599 09:29:16.295863 CH1_RK0: MR19=0x808, MR18=0x4308, DQSOSC=397, MR23=63, INC=166, DEC=110
4600 09:29:16.296297
4601 09:29:16.298689 ----->DramcWriteLeveling(PI) begin...
4602 09:29:16.299092 ==
4603 09:29:16.301962 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 09:29:16.305746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 09:29:16.306275 ==
4606 09:29:16.309054 Write leveling (Byte 0): 28 => 28
4607 09:29:16.312274 Write leveling (Byte 1): 32 => 32
4608 09:29:16.315655 DramcWriteLeveling(PI) end<-----
4609 09:29:16.316154
4610 09:29:16.316467 ==
4611 09:29:16.319130 Dram Type= 6, Freq= 0, CH_1, rank 1
4612 09:29:16.322085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 09:29:16.322570 ==
4614 09:29:16.325227 [Gating] SW mode calibration
4615 09:29:16.332261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4616 09:29:16.338915 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4617 09:29:16.342027 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4618 09:29:16.345087 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4619 09:29:16.352703 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4620 09:29:16.355627 0 9 12 | B1->B0 | 3333 2d2d | 1 0 | (0 0) (1 0)
4621 09:29:16.358540 0 9 16 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
4622 09:29:16.365313 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 09:29:16.368575 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 09:29:16.372232 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 09:29:16.379035 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 09:29:16.382002 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 09:29:16.385630 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4628 09:29:16.392199 0 10 12 | B1->B0 | 3030 3a3a | 1 1 | (0 0) (0 0)
4629 09:29:16.395511 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4630 09:29:16.398230 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 09:29:16.405660 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 09:29:16.408864 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 09:29:16.412196 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 09:29:16.415348 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 09:29:16.422214 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 09:29:16.425145 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4637 09:29:16.428664 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 09:29:16.435021 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 09:29:16.438327 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 09:29:16.442132 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 09:29:16.448527 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 09:29:16.451837 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 09:29:16.454926 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 09:29:16.462130 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 09:29:16.465188 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 09:29:16.468523 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 09:29:16.474944 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 09:29:16.478224 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 09:29:16.481708 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 09:29:16.488571 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 09:29:16.491802 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4652 09:29:16.495483 Total UI for P1: 0, mck2ui 16
4653 09:29:16.498647 best dqsien dly found for B0: ( 0, 13, 6)
4654 09:29:16.501920 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4655 09:29:16.504982 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 09:29:16.508334 Total UI for P1: 0, mck2ui 16
4657 09:29:16.511707 best dqsien dly found for B1: ( 0, 13, 12)
4658 09:29:16.514869 best DQS0 dly(MCK, UI, PI) = (0, 13, 6)
4659 09:29:16.521705 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4660 09:29:16.522138
4661 09:29:16.525056 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 6)
4662 09:29:16.528374 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4663 09:29:16.531963 [Gating] SW calibration Done
4664 09:29:16.532356 ==
4665 09:29:16.535271 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 09:29:16.538412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 09:29:16.538888 ==
4668 09:29:16.539195 RX Vref Scan: 0
4669 09:29:16.541958
4670 09:29:16.542396 RX Vref 0 -> 0, step: 1
4671 09:29:16.542705
4672 09:29:16.545220 RX Delay -230 -> 252, step: 16
4673 09:29:16.548425 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4674 09:29:16.555240 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4675 09:29:16.558281 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4676 09:29:16.561695 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4677 09:29:16.565371 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4678 09:29:16.568124 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4679 09:29:16.575381 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4680 09:29:16.578370 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4681 09:29:16.581899 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4682 09:29:16.585329 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4683 09:29:16.588915 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4684 09:29:16.595316 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4685 09:29:16.598457 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4686 09:29:16.602368 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4687 09:29:16.605431 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4688 09:29:16.612310 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4689 09:29:16.612786 ==
4690 09:29:16.615579 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 09:29:16.618931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 09:29:16.619401 ==
4693 09:29:16.619710 DQS Delay:
4694 09:29:16.621921 DQS0 = 0, DQS1 = 0
4695 09:29:16.622349 DQM Delay:
4696 09:29:16.625211 DQM0 = 43, DQM1 = 36
4697 09:29:16.625676 DQ Delay:
4698 09:29:16.628625 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4699 09:29:16.632424 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4700 09:29:16.635290 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4701 09:29:16.638914 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4702 09:29:16.639333
4703 09:29:16.639722
4704 09:29:16.640030 ==
4705 09:29:16.642222 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 09:29:16.645262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 09:29:16.645773 ==
4708 09:29:16.646258
4709 09:29:16.648418
4710 09:29:16.648831 TX Vref Scan disable
4711 09:29:16.652257 == TX Byte 0 ==
4712 09:29:16.655337 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4713 09:29:16.658609 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4714 09:29:16.662357 == TX Byte 1 ==
4715 09:29:16.665808 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4716 09:29:16.668613 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4717 09:29:16.669013 ==
4718 09:29:16.672299 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 09:29:16.678745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 09:29:16.679138 ==
4721 09:29:16.679535
4722 09:29:16.679983
4723 09:29:16.680279 TX Vref Scan disable
4724 09:29:16.682897 == TX Byte 0 ==
4725 09:29:16.686416 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4726 09:29:16.690313 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4727 09:29:16.693378 == TX Byte 1 ==
4728 09:29:16.696896 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4729 09:29:16.703111 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4730 09:29:16.703561
4731 09:29:16.703871 [DATLAT]
4732 09:29:16.704153 Freq=600, CH1 RK1
4733 09:29:16.704425
4734 09:29:16.707090 DATLAT Default: 0x9
4735 09:29:16.707565 0, 0xFFFF, sum = 0
4736 09:29:16.710081 1, 0xFFFF, sum = 0
4737 09:29:16.710476 2, 0xFFFF, sum = 0
4738 09:29:16.713260 3, 0xFFFF, sum = 0
4739 09:29:16.713656 4, 0xFFFF, sum = 0
4740 09:29:16.716462 5, 0xFFFF, sum = 0
4741 09:29:16.720185 6, 0xFFFF, sum = 0
4742 09:29:16.720581 7, 0xFFFF, sum = 0
4743 09:29:16.720893 8, 0x0, sum = 1
4744 09:29:16.723241 9, 0x0, sum = 2
4745 09:29:16.723638 10, 0x0, sum = 3
4746 09:29:16.726623 11, 0x0, sum = 4
4747 09:29:16.727113 best_step = 9
4748 09:29:16.727423
4749 09:29:16.727705 ==
4750 09:29:16.730090 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 09:29:16.737193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 09:29:16.737680 ==
4753 09:29:16.738033 RX Vref Scan: 0
4754 09:29:16.738341
4755 09:29:16.740077 RX Vref 0 -> 0, step: 1
4756 09:29:16.740467
4757 09:29:16.743808 RX Delay -179 -> 252, step: 8
4758 09:29:16.746720 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4759 09:29:16.753561 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4760 09:29:16.756599 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4761 09:29:16.760092 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4762 09:29:16.763031 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4763 09:29:16.766447 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4764 09:29:16.772925 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4765 09:29:16.776570 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4766 09:29:16.779803 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4767 09:29:16.783167 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4768 09:29:16.789856 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4769 09:29:16.793255 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4770 09:29:16.796646 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4771 09:29:16.799725 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4772 09:29:16.803067 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4773 09:29:16.810062 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4774 09:29:16.810541 ==
4775 09:29:16.813308 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 09:29:16.816391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 09:29:16.816783 ==
4778 09:29:16.817087 DQS Delay:
4779 09:29:16.820013 DQS0 = 0, DQS1 = 0
4780 09:29:16.820403 DQM Delay:
4781 09:29:16.823194 DQM0 = 38, DQM1 = 34
4782 09:29:16.823588 DQ Delay:
4783 09:29:16.827050 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4784 09:29:16.830304 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4785 09:29:16.833899 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4786 09:29:16.836507 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4787 09:29:16.837006
4788 09:29:16.837315
4789 09:29:16.843504 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c4a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
4790 09:29:16.846527 CH1 RK1: MR19=808, MR18=3C4A
4791 09:29:16.853671 CH1_RK1: MR19=0x808, MR18=0x3C4A, DQSOSC=395, MR23=63, INC=168, DEC=112
4792 09:29:16.857037 [RxdqsGatingPostProcess] freq 600
4793 09:29:16.863635 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4794 09:29:16.866684 Pre-setting of DQS Precalculation
4795 09:29:16.869916 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4796 09:29:16.876928 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4797 09:29:16.883349 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4798 09:29:16.883744
4799 09:29:16.884045
4800 09:29:16.886219 [Calibration Summary] 1200 Mbps
4801 09:29:16.889814 CH 0, Rank 0
4802 09:29:16.890311 SW Impedance : PASS
4803 09:29:16.893205 DUTY Scan : NO K
4804 09:29:16.896176 ZQ Calibration : PASS
4805 09:29:16.896566 Jitter Meter : NO K
4806 09:29:16.899816 CBT Training : PASS
4807 09:29:16.903498 Write leveling : PASS
4808 09:29:16.903912 RX DQS gating : PASS
4809 09:29:16.906321 RX DQ/DQS(RDDQC) : PASS
4810 09:29:16.906727 TX DQ/DQS : PASS
4811 09:29:16.909538 RX DATLAT : PASS
4812 09:29:16.913128 RX DQ/DQS(Engine): PASS
4813 09:29:16.913555 TX OE : NO K
4814 09:29:16.916660 All Pass.
4815 09:29:16.917163
4816 09:29:16.917597 CH 0, Rank 1
4817 09:29:16.919728 SW Impedance : PASS
4818 09:29:16.920273 DUTY Scan : NO K
4819 09:29:16.923086 ZQ Calibration : PASS
4820 09:29:16.926527 Jitter Meter : NO K
4821 09:29:16.926939 CBT Training : PASS
4822 09:29:16.930167 Write leveling : PASS
4823 09:29:16.933317 RX DQS gating : PASS
4824 09:29:16.933713 RX DQ/DQS(RDDQC) : PASS
4825 09:29:16.936422 TX DQ/DQS : PASS
4826 09:29:16.939579 RX DATLAT : PASS
4827 09:29:16.939971 RX DQ/DQS(Engine): PASS
4828 09:29:16.942952 TX OE : NO K
4829 09:29:16.943391 All Pass.
4830 09:29:16.943697
4831 09:29:16.946265 CH 1, Rank 0
4832 09:29:16.946656 SW Impedance : PASS
4833 09:29:16.950211 DUTY Scan : NO K
4834 09:29:16.953293 ZQ Calibration : PASS
4835 09:29:16.953681 Jitter Meter : NO K
4836 09:29:16.956219 CBT Training : PASS
4837 09:29:16.956612 Write leveling : PASS
4838 09:29:16.959819 RX DQS gating : PASS
4839 09:29:16.962892 RX DQ/DQS(RDDQC) : PASS
4840 09:29:16.963283 TX DQ/DQS : PASS
4841 09:29:16.966033 RX DATLAT : PASS
4842 09:29:16.969745 RX DQ/DQS(Engine): PASS
4843 09:29:16.970176 TX OE : NO K
4844 09:29:16.972921 All Pass.
4845 09:29:16.973310
4846 09:29:16.973623 CH 1, Rank 1
4847 09:29:16.976097 SW Impedance : PASS
4848 09:29:16.976642 DUTY Scan : NO K
4849 09:29:16.979933 ZQ Calibration : PASS
4850 09:29:16.983103 Jitter Meter : NO K
4851 09:29:16.983503 CBT Training : PASS
4852 09:29:16.986269 Write leveling : PASS
4853 09:29:16.989529 RX DQS gating : PASS
4854 09:29:16.990133 RX DQ/DQS(RDDQC) : PASS
4855 09:29:16.992889 TX DQ/DQS : PASS
4856 09:29:16.993331 RX DATLAT : PASS
4857 09:29:16.996722 RX DQ/DQS(Engine): PASS
4858 09:29:16.999843 TX OE : NO K
4859 09:29:17.000261 All Pass.
4860 09:29:17.000567
4861 09:29:17.003490 DramC Write-DBI off
4862 09:29:17.003927 PER_BANK_REFRESH: Hybrid Mode
4863 09:29:17.006264 TX_TRACKING: ON
4864 09:29:17.016418 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4865 09:29:17.020156 [FAST_K] Save calibration result to emmc
4866 09:29:17.023259 dramc_set_vcore_voltage set vcore to 662500
4867 09:29:17.023672 Read voltage for 933, 3
4868 09:29:17.026617 Vio18 = 0
4869 09:29:17.027112 Vcore = 662500
4870 09:29:17.027568 Vdram = 0
4871 09:29:17.029912 Vddq = 0
4872 09:29:17.030468 Vmddr = 0
4873 09:29:17.032962 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4874 09:29:17.039835 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4875 09:29:17.042924 MEM_TYPE=3, freq_sel=17
4876 09:29:17.046870 sv_algorithm_assistance_LP4_1600
4877 09:29:17.049787 ============ PULL DRAM RESETB DOWN ============
4878 09:29:17.053478 ========== PULL DRAM RESETB DOWN end =========
4879 09:29:17.056809 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4880 09:29:17.059965 ===================================
4881 09:29:17.063437 LPDDR4 DRAM CONFIGURATION
4882 09:29:17.066375 ===================================
4883 09:29:17.069736 EX_ROW_EN[0] = 0x0
4884 09:29:17.070115 EX_ROW_EN[1] = 0x0
4885 09:29:17.073664 LP4Y_EN = 0x0
4886 09:29:17.073942 WORK_FSP = 0x0
4887 09:29:17.076832 WL = 0x3
4888 09:29:17.077220 RL = 0x3
4889 09:29:17.080000 BL = 0x2
4890 09:29:17.080368 RPST = 0x0
4891 09:29:17.083281 RD_PRE = 0x0
4892 09:29:17.083645 WR_PRE = 0x1
4893 09:29:17.086402 WR_PST = 0x0
4894 09:29:17.086767 DBI_WR = 0x0
4895 09:29:17.089714 DBI_RD = 0x0
4896 09:29:17.093335 OTF = 0x1
4897 09:29:17.096604 ===================================
4898 09:29:17.097006 ===================================
4899 09:29:17.099729 ANA top config
4900 09:29:17.103070 ===================================
4901 09:29:17.106711 DLL_ASYNC_EN = 0
4902 09:29:17.107036 ALL_SLAVE_EN = 1
4903 09:29:17.110076 NEW_RANK_MODE = 1
4904 09:29:17.113063 DLL_IDLE_MODE = 1
4905 09:29:17.116560 LP45_APHY_COMB_EN = 1
4906 09:29:17.119669 TX_ODT_DIS = 1
4907 09:29:17.120044 NEW_8X_MODE = 1
4908 09:29:17.123034 ===================================
4909 09:29:17.126845 ===================================
4910 09:29:17.129928 data_rate = 1866
4911 09:29:17.133137 CKR = 1
4912 09:29:17.136656 DQ_P2S_RATIO = 8
4913 09:29:17.139997 ===================================
4914 09:29:17.143054 CA_P2S_RATIO = 8
4915 09:29:17.143131 DQ_CA_OPEN = 0
4916 09:29:17.146070 DQ_SEMI_OPEN = 0
4917 09:29:17.149595 CA_SEMI_OPEN = 0
4918 09:29:17.152933 CA_FULL_RATE = 0
4919 09:29:17.156537 DQ_CKDIV4_EN = 1
4920 09:29:17.159413 CA_CKDIV4_EN = 1
4921 09:29:17.159517 CA_PREDIV_EN = 0
4922 09:29:17.163377 PH8_DLY = 0
4923 09:29:17.166765 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4924 09:29:17.170542 DQ_AAMCK_DIV = 4
4925 09:29:17.173476 CA_AAMCK_DIV = 4
4926 09:29:17.176650 CA_ADMCK_DIV = 4
4927 09:29:17.177041 DQ_TRACK_CA_EN = 0
4928 09:29:17.180744 CA_PICK = 933
4929 09:29:17.183486 CA_MCKIO = 933
4930 09:29:17.186547 MCKIO_SEMI = 0
4931 09:29:17.190439 PLL_FREQ = 3732
4932 09:29:17.193627 DQ_UI_PI_RATIO = 32
4933 09:29:17.196648 CA_UI_PI_RATIO = 0
4934 09:29:17.200297 ===================================
4935 09:29:17.203223 ===================================
4936 09:29:17.203613 memory_type:LPDDR4
4937 09:29:17.206781 GP_NUM : 10
4938 09:29:17.207171 SRAM_EN : 1
4939 09:29:17.210316 MD32_EN : 0
4940 09:29:17.214113 ===================================
4941 09:29:17.216673 [ANA_INIT] >>>>>>>>>>>>>>
4942 09:29:17.220781 <<<<<< [CONFIGURE PHASE]: ANA_TX
4943 09:29:17.223485 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4944 09:29:17.227222 ===================================
4945 09:29:17.227693 data_rate = 1866,PCW = 0X8f00
4946 09:29:17.230022 ===================================
4947 09:29:17.236955 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4948 09:29:17.239851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4949 09:29:17.246350 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 09:29:17.250245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4951 09:29:17.253109 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4952 09:29:17.256775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4953 09:29:17.260226 [ANA_INIT] flow start
4954 09:29:17.263597 [ANA_INIT] PLL >>>>>>>>
4955 09:29:17.264000 [ANA_INIT] PLL <<<<<<<<
4956 09:29:17.266901 [ANA_INIT] MIDPI >>>>>>>>
4957 09:29:17.270101 [ANA_INIT] MIDPI <<<<<<<<
4958 09:29:17.270511 [ANA_INIT] DLL >>>>>>>>
4959 09:29:17.273302 [ANA_INIT] flow end
4960 09:29:17.276821 ============ LP4 DIFF to SE enter ============
4961 09:29:17.280573 ============ LP4 DIFF to SE exit ============
4962 09:29:17.283744 [ANA_INIT] <<<<<<<<<<<<<
4963 09:29:17.286949 [Flow] Enable top DCM control >>>>>
4964 09:29:17.290017 [Flow] Enable top DCM control <<<<<
4965 09:29:17.293135 Enable DLL master slave shuffle
4966 09:29:17.300399 ==============================================================
4967 09:29:17.300940 Gating Mode config
4968 09:29:17.306688 ==============================================================
4969 09:29:17.307109 Config description:
4970 09:29:17.316861 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4971 09:29:17.323199 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4972 09:29:17.329937 SELPH_MODE 0: By rank 1: By Phase
4973 09:29:17.333749 ==============================================================
4974 09:29:17.336716 GAT_TRACK_EN = 1
4975 09:29:17.340424 RX_GATING_MODE = 2
4976 09:29:17.342950 RX_GATING_TRACK_MODE = 2
4977 09:29:17.346502 SELPH_MODE = 1
4978 09:29:17.349960 PICG_EARLY_EN = 1
4979 09:29:17.353348 VALID_LAT_VALUE = 1
4980 09:29:17.356578 ==============================================================
4981 09:29:17.359773 Enter into Gating configuration >>>>
4982 09:29:17.363450 Exit from Gating configuration <<<<
4983 09:29:17.366447 Enter into DVFS_PRE_config >>>>>
4984 09:29:17.379945 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4985 09:29:17.383426 Exit from DVFS_PRE_config <<<<<
4986 09:29:17.386467 Enter into PICG configuration >>>>
4987 09:29:17.386761 Exit from PICG configuration <<<<
4988 09:29:17.389560 [RX_INPUT] configuration >>>>>
4989 09:29:17.393455 [RX_INPUT] configuration <<<<<
4990 09:29:17.399709 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4991 09:29:17.403553 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4992 09:29:17.410185 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4993 09:29:17.416254 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4994 09:29:17.423309 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4995 09:29:17.429746 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4996 09:29:17.433064 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4997 09:29:17.436202 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4998 09:29:17.439529 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4999 09:29:17.446394 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5000 09:29:17.449451 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5001 09:29:17.453225 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5002 09:29:17.456378 ===================================
5003 09:29:17.459935 LPDDR4 DRAM CONFIGURATION
5004 09:29:17.463224 ===================================
5005 09:29:17.466383 EX_ROW_EN[0] = 0x0
5006 09:29:17.466877 EX_ROW_EN[1] = 0x0
5007 09:29:17.469425 LP4Y_EN = 0x0
5008 09:29:17.469826 WORK_FSP = 0x0
5009 09:29:17.473181 WL = 0x3
5010 09:29:17.473582 RL = 0x3
5011 09:29:17.476078 BL = 0x2
5012 09:29:17.476486 RPST = 0x0
5013 09:29:17.479727 RD_PRE = 0x0
5014 09:29:17.480126 WR_PRE = 0x1
5015 09:29:17.482962 WR_PST = 0x0
5016 09:29:17.483363 DBI_WR = 0x0
5017 09:29:17.486415 DBI_RD = 0x0
5018 09:29:17.486816 OTF = 0x1
5019 09:29:17.489620 ===================================
5020 09:29:17.496441 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5021 09:29:17.499458 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5022 09:29:17.502575 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5023 09:29:17.506374 ===================================
5024 09:29:17.509533 LPDDR4 DRAM CONFIGURATION
5025 09:29:17.512789 ===================================
5026 09:29:17.512932 EX_ROW_EN[0] = 0x10
5027 09:29:17.516023 EX_ROW_EN[1] = 0x0
5028 09:29:17.519825 LP4Y_EN = 0x0
5029 09:29:17.519969 WORK_FSP = 0x0
5030 09:29:17.523159 WL = 0x3
5031 09:29:17.523303 RL = 0x3
5032 09:29:17.526286 BL = 0x2
5033 09:29:17.526430 RPST = 0x0
5034 09:29:17.529306 RD_PRE = 0x0
5035 09:29:17.529450 WR_PRE = 0x1
5036 09:29:17.532985 WR_PST = 0x0
5037 09:29:17.533128 DBI_WR = 0x0
5038 09:29:17.536195 DBI_RD = 0x0
5039 09:29:17.536339 OTF = 0x1
5040 09:29:17.539440 ===================================
5041 09:29:17.546252 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5042 09:29:17.550537 nWR fixed to 30
5043 09:29:17.553835 [ModeRegInit_LP4] CH0 RK0
5044 09:29:17.553992 [ModeRegInit_LP4] CH0 RK1
5045 09:29:17.557289 [ModeRegInit_LP4] CH1 RK0
5046 09:29:17.560349 [ModeRegInit_LP4] CH1 RK1
5047 09:29:17.560493 match AC timing 9
5048 09:29:17.566785 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5049 09:29:17.569849 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5050 09:29:17.573414 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5051 09:29:17.580130 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5052 09:29:17.583687 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5053 09:29:17.583852 ==
5054 09:29:17.586981 Dram Type= 6, Freq= 0, CH_0, rank 0
5055 09:29:17.590366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5056 09:29:17.590533 ==
5057 09:29:17.596652 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5058 09:29:17.603539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5059 09:29:17.606772 [CA 0] Center 38 (7~69) winsize 63
5060 09:29:17.610063 [CA 1] Center 38 (7~69) winsize 63
5061 09:29:17.613648 [CA 2] Center 35 (5~66) winsize 62
5062 09:29:17.616852 [CA 3] Center 35 (5~66) winsize 62
5063 09:29:17.620022 [CA 4] Center 33 (3~64) winsize 62
5064 09:29:17.624005 [CA 5] Center 33 (3~64) winsize 62
5065 09:29:17.624168
5066 09:29:17.627474 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5067 09:29:17.627856
5068 09:29:17.630620 [CATrainingPosCal] consider 1 rank data
5069 09:29:17.633713 u2DelayCellTimex100 = 270/100 ps
5070 09:29:17.637260 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5071 09:29:17.640727 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5072 09:29:17.643995 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5073 09:29:17.647169 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5074 09:29:17.650455 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5075 09:29:17.653918 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5076 09:29:17.654381
5077 09:29:17.660329 CA PerBit enable=1, Macro0, CA PI delay=33
5078 09:29:17.660865
5079 09:29:17.661308 [CBTSetCACLKResult] CA Dly = 33
5080 09:29:17.664141 CS Dly: 6 (0~37)
5081 09:29:17.664680 ==
5082 09:29:17.667224 Dram Type= 6, Freq= 0, CH_0, rank 1
5083 09:29:17.670622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 09:29:17.671093 ==
5085 09:29:17.676705 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5086 09:29:17.683498 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5087 09:29:17.686986 [CA 0] Center 38 (8~69) winsize 62
5088 09:29:17.689935 [CA 1] Center 38 (7~69) winsize 63
5089 09:29:17.693458 [CA 2] Center 35 (5~66) winsize 62
5090 09:29:17.696913 [CA 3] Center 35 (5~66) winsize 62
5091 09:29:17.699751 [CA 4] Center 34 (3~65) winsize 63
5092 09:29:17.703551 [CA 5] Center 33 (3~64) winsize 62
5093 09:29:17.703825
5094 09:29:17.706649 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5095 09:29:17.706895
5096 09:29:17.710161 [CATrainingPosCal] consider 2 rank data
5097 09:29:17.713371 u2DelayCellTimex100 = 270/100 ps
5098 09:29:17.716892 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5099 09:29:17.719773 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5100 09:29:17.723541 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5101 09:29:17.726705 CA3 delay=35 (5~66),Diff = 2 PI (12 cell)
5102 09:29:17.729878 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5103 09:29:17.733254 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5104 09:29:17.736371
5105 09:29:17.740367 CA PerBit enable=1, Macro0, CA PI delay=33
5106 09:29:17.740506
5107 09:29:17.743366 [CBTSetCACLKResult] CA Dly = 33
5108 09:29:17.743472 CS Dly: 7 (0~39)
5109 09:29:17.743555
5110 09:29:17.746299 ----->DramcWriteLeveling(PI) begin...
5111 09:29:17.746408 ==
5112 09:29:17.749957 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 09:29:17.753295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 09:29:17.756403 ==
5115 09:29:17.756510 Write leveling (Byte 0): 32 => 32
5116 09:29:17.760037 Write leveling (Byte 1): 25 => 25
5117 09:29:17.763145 DramcWriteLeveling(PI) end<-----
5118 09:29:17.763252
5119 09:29:17.763335 ==
5120 09:29:17.767050 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 09:29:17.773127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 09:29:17.773285 ==
5123 09:29:17.773431 [Gating] SW mode calibration
5124 09:29:17.783423 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5125 09:29:17.786170 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5126 09:29:17.789969 0 14 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
5127 09:29:17.796652 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5128 09:29:17.799672 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 09:29:17.803408 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 09:29:17.809883 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 09:29:17.813000 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 09:29:17.816549 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 09:29:17.822998 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5134 09:29:17.826721 0 15 0 | B1->B0 | 3232 2626 | 0 0 | (0 0) (0 0)
5135 09:29:17.829672 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5136 09:29:17.836386 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 09:29:17.839569 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 09:29:17.843408 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 09:29:17.850329 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 09:29:17.853175 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 09:29:17.856593 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5142 09:29:17.863403 1 0 0 | B1->B0 | 3232 3b3b | 1 0 | (0 0) (0 0)
5143 09:29:17.866567 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 09:29:17.869730 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 09:29:17.876841 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 09:29:17.879985 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 09:29:17.883184 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 09:29:17.886338 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 09:29:17.893172 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5150 09:29:17.896755 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5151 09:29:17.899683 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5152 09:29:17.906509 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 09:29:17.910163 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 09:29:17.913400 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 09:29:17.919839 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 09:29:17.923530 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 09:29:17.926731 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 09:29:17.933612 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 09:29:17.936904 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 09:29:17.940440 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 09:29:17.946809 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 09:29:17.949802 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 09:29:17.953631 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 09:29:17.956881 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 09:29:17.963254 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5166 09:29:17.966575 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5167 09:29:17.970214 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5168 09:29:17.976705 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 09:29:17.979835 Total UI for P1: 0, mck2ui 16
5170 09:29:17.983669 best dqsien dly found for B0: ( 1, 3, 0)
5171 09:29:17.983747 Total UI for P1: 0, mck2ui 16
5172 09:29:17.990277 best dqsien dly found for B1: ( 1, 3, 0)
5173 09:29:17.993508 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5174 09:29:17.997092 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5175 09:29:17.997170
5176 09:29:18.000073 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5177 09:29:18.003152 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5178 09:29:18.006725 [Gating] SW calibration Done
5179 09:29:18.006803 ==
5180 09:29:18.010310 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 09:29:18.013470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 09:29:18.013548 ==
5183 09:29:18.016530 RX Vref Scan: 0
5184 09:29:18.016608
5185 09:29:18.016668 RX Vref 0 -> 0, step: 1
5186 09:29:18.016724
5187 09:29:18.020216 RX Delay -80 -> 252, step: 8
5188 09:29:18.023573 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5189 09:29:18.029988 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5190 09:29:18.033845 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5191 09:29:18.036865 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5192 09:29:18.040127 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5193 09:29:18.043172 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5194 09:29:18.046993 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5195 09:29:18.050214 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5196 09:29:18.056645 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5197 09:29:18.059806 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5198 09:29:18.063621 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5199 09:29:18.066761 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5200 09:29:18.069813 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5201 09:29:18.076805 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5202 09:29:18.079808 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5203 09:29:18.083470 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5204 09:29:18.083547 ==
5205 09:29:18.086650 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 09:29:18.089864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 09:29:18.089942 ==
5208 09:29:18.093709 DQS Delay:
5209 09:29:18.093787 DQS0 = 0, DQS1 = 0
5210 09:29:18.093847 DQM Delay:
5211 09:29:18.097020 DQM0 = 98, DQM1 = 86
5212 09:29:18.097097 DQ Delay:
5213 09:29:18.099910 DQ0 =99, DQ1 =103, DQ2 =91, DQ3 =91
5214 09:29:18.103466 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5215 09:29:18.107183 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5216 09:29:18.110218 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5217 09:29:18.110295
5218 09:29:18.110365
5219 09:29:18.113183 ==
5220 09:29:18.113260 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 09:29:18.120312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 09:29:18.120389 ==
5223 09:29:18.120450
5224 09:29:18.120504
5225 09:29:18.123398 TX Vref Scan disable
5226 09:29:18.123481 == TX Byte 0 ==
5227 09:29:18.126833 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5228 09:29:18.133507 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5229 09:29:18.133603 == TX Byte 1 ==
5230 09:29:18.137201 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5231 09:29:18.143814 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5232 09:29:18.143909 ==
5233 09:29:18.147123 Dram Type= 6, Freq= 0, CH_0, rank 0
5234 09:29:18.150230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5235 09:29:18.150326 ==
5236 09:29:18.150401
5237 09:29:18.150470
5238 09:29:18.153840 TX Vref Scan disable
5239 09:29:18.157142 == TX Byte 0 ==
5240 09:29:18.160270 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5241 09:29:18.163806 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5242 09:29:18.167271 == TX Byte 1 ==
5243 09:29:18.170106 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5244 09:29:18.173437 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5245 09:29:18.173514
5246 09:29:18.173573 [DATLAT]
5247 09:29:18.176642 Freq=933, CH0 RK0
5248 09:29:18.176751
5249 09:29:18.180552 DATLAT Default: 0xd
5250 09:29:18.180648 0, 0xFFFF, sum = 0
5251 09:29:18.183509 1, 0xFFFF, sum = 0
5252 09:29:18.183621 2, 0xFFFF, sum = 0
5253 09:29:18.186651 3, 0xFFFF, sum = 0
5254 09:29:18.186768 4, 0xFFFF, sum = 0
5255 09:29:18.190325 5, 0xFFFF, sum = 0
5256 09:29:18.190435 6, 0xFFFF, sum = 0
5257 09:29:18.193745 7, 0xFFFF, sum = 0
5258 09:29:18.193876 8, 0xFFFF, sum = 0
5259 09:29:18.197255 9, 0xFFFF, sum = 0
5260 09:29:18.197379 10, 0x0, sum = 1
5261 09:29:18.200427 11, 0x0, sum = 2
5262 09:29:18.200536 12, 0x0, sum = 3
5263 09:29:18.203738 13, 0x0, sum = 4
5264 09:29:18.203892 best_step = 11
5265 09:29:18.204019
5266 09:29:18.204137 ==
5267 09:29:18.206842 Dram Type= 6, Freq= 0, CH_0, rank 0
5268 09:29:18.210426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5269 09:29:18.210542 ==
5270 09:29:18.213699 RX Vref Scan: 1
5271 09:29:18.213812
5272 09:29:18.216808 RX Vref 0 -> 0, step: 1
5273 09:29:18.216922
5274 09:29:18.217009 RX Delay -61 -> 252, step: 4
5275 09:29:18.217092
5276 09:29:18.220576 Set Vref, RX VrefLevel [Byte0]: 52
5277 09:29:18.224118 [Byte1]: 50
5278 09:29:18.228336
5279 09:29:18.228572 Final RX Vref Byte 0 = 52 to rank0
5280 09:29:18.231890 Final RX Vref Byte 1 = 50 to rank0
5281 09:29:18.235238 Final RX Vref Byte 0 = 52 to rank1
5282 09:29:18.238385 Final RX Vref Byte 1 = 50 to rank1==
5283 09:29:18.241542 Dram Type= 6, Freq= 0, CH_0, rank 0
5284 09:29:18.248747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 09:29:18.249068 ==
5286 09:29:18.249289 DQS Delay:
5287 09:29:18.249512 DQS0 = 0, DQS1 = 0
5288 09:29:18.251886 DQM Delay:
5289 09:29:18.252247 DQM0 = 97, DQM1 = 87
5290 09:29:18.255263 DQ Delay:
5291 09:29:18.258475 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5292 09:29:18.261830 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =104
5293 09:29:18.265120 DQ8 =78, DQ9 =76, DQ10 =86, DQ11 =80
5294 09:29:18.268338 DQ12 =94, DQ13 =88, DQ14 =100, DQ15 =98
5295 09:29:18.268811
5296 09:29:18.269230
5297 09:29:18.275049 [DQSOSCAuto] RK0, (LSB)MR18= 0x1601, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5298 09:29:18.278109 CH0 RK0: MR19=505, MR18=1601
5299 09:29:18.284776 CH0_RK0: MR19=0x505, MR18=0x1601, DQSOSC=414, MR23=63, INC=63, DEC=42
5300 09:29:18.285135
5301 09:29:18.288015 ----->DramcWriteLeveling(PI) begin...
5302 09:29:18.288379 ==
5303 09:29:18.291861 Dram Type= 6, Freq= 0, CH_0, rank 1
5304 09:29:18.295127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5305 09:29:18.295485 ==
5306 09:29:18.298420 Write leveling (Byte 0): 30 => 30
5307 09:29:18.301544 Write leveling (Byte 1): 30 => 30
5308 09:29:18.305295 DramcWriteLeveling(PI) end<-----
5309 09:29:18.305653
5310 09:29:18.305931 ==
5311 09:29:18.308469 Dram Type= 6, Freq= 0, CH_0, rank 1
5312 09:29:18.311616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5313 09:29:18.312079 ==
5314 09:29:18.315275 [Gating] SW mode calibration
5315 09:29:18.321797 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5316 09:29:18.328449 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5317 09:29:18.332027 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
5318 09:29:18.334981 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
5319 09:29:18.341849 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 09:29:18.345324 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 09:29:18.348382 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 09:29:18.355051 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 09:29:18.358034 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 09:29:18.361915 0 14 28 | B1->B0 | 3333 2e2e | 1 0 | (1 0) (1 1)
5325 09:29:18.368435 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (1 0) (0 0)
5326 09:29:18.371628 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 09:29:18.375269 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 09:29:18.382010 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 09:29:18.384954 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 09:29:18.388506 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 09:29:18.394988 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 09:29:18.398726 0 15 28 | B1->B0 | 2424 2c2c | 0 1 | (0 0) (0 0)
5333 09:29:18.401937 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5334 09:29:18.408758 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 09:29:18.411929 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 09:29:18.415314 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 09:29:18.418566 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 09:29:18.425143 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 09:29:18.428723 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 09:29:18.432009 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5341 09:29:18.438593 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5342 09:29:18.442305 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 09:29:18.445147 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 09:29:18.452277 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 09:29:18.455301 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 09:29:18.459012 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 09:29:18.464917 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 09:29:18.468740 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 09:29:18.471960 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 09:29:18.477908 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 09:29:18.481864 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 09:29:18.485122 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 09:29:18.491605 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 09:29:18.495202 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 09:29:18.498356 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5356 09:29:18.505292 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5357 09:29:18.508426 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5358 09:29:18.512678 Total UI for P1: 0, mck2ui 16
5359 09:29:18.515378 best dqsien dly found for B0: ( 1, 2, 26)
5360 09:29:18.518513 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 09:29:18.522351 Total UI for P1: 0, mck2ui 16
5362 09:29:18.524968 best dqsien dly found for B1: ( 1, 2, 30)
5363 09:29:18.528530 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5364 09:29:18.532115 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5365 09:29:18.532510
5366 09:29:18.535567 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5367 09:29:18.538670 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5368 09:29:18.541713 [Gating] SW calibration Done
5369 09:29:18.542144 ==
5370 09:29:18.545590 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 09:29:18.552153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 09:29:18.552656 ==
5373 09:29:18.552971 RX Vref Scan: 0
5374 09:29:18.553290
5375 09:29:18.555156 RX Vref 0 -> 0, step: 1
5376 09:29:18.555656
5377 09:29:18.558457 RX Delay -80 -> 252, step: 8
5378 09:29:18.562305 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5379 09:29:18.565223 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5380 09:29:18.568884 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5381 09:29:18.571642 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5382 09:29:18.575440 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5383 09:29:18.582184 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5384 09:29:18.585265 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5385 09:29:18.588101 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5386 09:29:18.591860 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5387 09:29:18.595151 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5388 09:29:18.598772 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5389 09:29:18.605543 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5390 09:29:18.608794 iDelay=200, Bit 12, Center 87 (-8 ~ 183) 192
5391 09:29:18.612208 iDelay=200, Bit 13, Center 87 (-8 ~ 183) 192
5392 09:29:18.615526 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5393 09:29:18.618560 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5394 09:29:18.622127 ==
5395 09:29:18.622543 Dram Type= 6, Freq= 0, CH_0, rank 1
5396 09:29:18.628783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5397 09:29:18.629293 ==
5398 09:29:18.629613 DQS Delay:
5399 09:29:18.632155 DQS0 = 0, DQS1 = 0
5400 09:29:18.632553 DQM Delay:
5401 09:29:18.635322 DQM0 = 96, DQM1 = 86
5402 09:29:18.635811 DQ Delay:
5403 09:29:18.638410 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5404 09:29:18.641906 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =103
5405 09:29:18.645250 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5406 09:29:18.648480 DQ12 =87, DQ13 =87, DQ14 =95, DQ15 =95
5407 09:29:18.648963
5408 09:29:18.649517
5409 09:29:18.649848 ==
5410 09:29:18.652084 Dram Type= 6, Freq= 0, CH_0, rank 1
5411 09:29:18.655032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5412 09:29:18.655435 ==
5413 09:29:18.655747
5414 09:29:18.656085
5415 09:29:18.658435 TX Vref Scan disable
5416 09:29:18.661953 == TX Byte 0 ==
5417 09:29:18.665176 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5418 09:29:18.668403 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5419 09:29:18.672019 == TX Byte 1 ==
5420 09:29:18.674855 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5421 09:29:18.678592 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5422 09:29:18.679118 ==
5423 09:29:18.681574 Dram Type= 6, Freq= 0, CH_0, rank 1
5424 09:29:18.685354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 09:29:18.685752 ==
5426 09:29:18.688400
5427 09:29:18.688796
5428 09:29:18.689101 TX Vref Scan disable
5429 09:29:18.692246 == TX Byte 0 ==
5430 09:29:18.695353 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5431 09:29:18.698997 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5432 09:29:18.701972 == TX Byte 1 ==
5433 09:29:18.705046 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5434 09:29:18.708454 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5435 09:29:18.712165
5436 09:29:18.712562 [DATLAT]
5437 09:29:18.712866 Freq=933, CH0 RK1
5438 09:29:18.713157
5439 09:29:18.715324 DATLAT Default: 0xb
5440 09:29:18.715721 0, 0xFFFF, sum = 0
5441 09:29:18.718368 1, 0xFFFF, sum = 0
5442 09:29:18.718771 2, 0xFFFF, sum = 0
5443 09:29:18.722236 3, 0xFFFF, sum = 0
5444 09:29:18.722633 4, 0xFFFF, sum = 0
5445 09:29:18.725258 5, 0xFFFF, sum = 0
5446 09:29:18.728975 6, 0xFFFF, sum = 0
5447 09:29:18.729469 7, 0xFFFF, sum = 0
5448 09:29:18.731593 8, 0xFFFF, sum = 0
5449 09:29:18.732056 9, 0xFFFF, sum = 0
5450 09:29:18.735611 10, 0x0, sum = 1
5451 09:29:18.736255 11, 0x0, sum = 2
5452 09:29:18.736658 12, 0x0, sum = 3
5453 09:29:18.738398 13, 0x0, sum = 4
5454 09:29:18.738927 best_step = 11
5455 09:29:18.739411
5456 09:29:18.739831 ==
5457 09:29:18.741598 Dram Type= 6, Freq= 0, CH_0, rank 1
5458 09:29:18.748528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5459 09:29:18.749031 ==
5460 09:29:18.749522 RX Vref Scan: 0
5461 09:29:18.750018
5462 09:29:18.752023 RX Vref 0 -> 0, step: 1
5463 09:29:18.752510
5464 09:29:18.754769 RX Delay -61 -> 252, step: 4
5465 09:29:18.758367 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5466 09:29:18.761649 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5467 09:29:18.768367 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5468 09:29:18.771955 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5469 09:29:18.775195 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5470 09:29:18.778532 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5471 09:29:18.781574 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5472 09:29:18.784878 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5473 09:29:18.791304 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5474 09:29:18.795125 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5475 09:29:18.798405 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5476 09:29:18.801467 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5477 09:29:18.804811 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5478 09:29:18.811747 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5479 09:29:18.814685 iDelay=199, Bit 14, Center 96 (11 ~ 182) 172
5480 09:29:18.817929 iDelay=199, Bit 15, Center 92 (3 ~ 182) 180
5481 09:29:18.818066 ==
5482 09:29:18.821849 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 09:29:18.824810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 09:29:18.824935 ==
5485 09:29:18.827989 DQS Delay:
5486 09:29:18.828091 DQS0 = 0, DQS1 = 0
5487 09:29:18.828180 DQM Delay:
5488 09:29:18.831131 DQM0 = 95, DQM1 = 86
5489 09:29:18.831210 DQ Delay:
5490 09:29:18.835142 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5491 09:29:18.838283 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5492 09:29:18.841549 DQ8 =80, DQ9 =80, DQ10 =86, DQ11 =78
5493 09:29:18.844736 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5494 09:29:18.844844
5495 09:29:18.844971
5496 09:29:18.854433 [DQSOSCAuto] RK1, (LSB)MR18= 0x1805, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5497 09:29:18.858235 CH0 RK1: MR19=505, MR18=1805
5498 09:29:18.861449 CH0_RK1: MR19=0x505, MR18=0x1805, DQSOSC=414, MR23=63, INC=63, DEC=42
5499 09:29:18.865177 [RxdqsGatingPostProcess] freq 933
5500 09:29:18.871712 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5501 09:29:18.874885 best DQS0 dly(2T, 0.5T) = (0, 11)
5502 09:29:18.878122 best DQS1 dly(2T, 0.5T) = (0, 11)
5503 09:29:18.881653 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5504 09:29:18.885032 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5505 09:29:18.887926 best DQS0 dly(2T, 0.5T) = (0, 10)
5506 09:29:18.891802 best DQS1 dly(2T, 0.5T) = (0, 10)
5507 09:29:18.891952 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5508 09:29:18.895224 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5509 09:29:18.898081 Pre-setting of DQS Precalculation
5510 09:29:18.904624 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5511 09:29:18.904825 ==
5512 09:29:18.908606 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 09:29:18.911904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5514 09:29:18.912085 ==
5515 09:29:18.918226 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5516 09:29:18.924968 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5517 09:29:18.928160 [CA 0] Center 36 (6~67) winsize 62
5518 09:29:18.931763 [CA 1] Center 36 (6~67) winsize 62
5519 09:29:18.935012 [CA 2] Center 33 (3~64) winsize 62
5520 09:29:18.938357 [CA 3] Center 34 (4~64) winsize 61
5521 09:29:18.941380 [CA 4] Center 34 (4~64) winsize 61
5522 09:29:18.945290 [CA 5] Center 33 (2~64) winsize 63
5523 09:29:18.945439
5524 09:29:18.948408 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5525 09:29:18.948558
5526 09:29:18.951925 [CATrainingPosCal] consider 1 rank data
5527 09:29:18.955044 u2DelayCellTimex100 = 270/100 ps
5528 09:29:18.958289 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5529 09:29:18.961951 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 09:29:18.965122 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
5531 09:29:18.968678 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5532 09:29:18.971815 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5533 09:29:18.975036 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5534 09:29:18.975459
5535 09:29:18.978737 CA PerBit enable=1, Macro0, CA PI delay=33
5536 09:29:18.981934
5537 09:29:18.982440 [CBTSetCACLKResult] CA Dly = 33
5538 09:29:18.985235 CS Dly: 4 (0~35)
5539 09:29:18.985629 ==
5540 09:29:18.988673 Dram Type= 6, Freq= 0, CH_1, rank 1
5541 09:29:18.991826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5542 09:29:18.992229 ==
5543 09:29:18.998409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5544 09:29:19.004795 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5545 09:29:19.008104 [CA 0] Center 36 (6~67) winsize 62
5546 09:29:19.011586 [CA 1] Center 37 (7~67) winsize 61
5547 09:29:19.015031 [CA 2] Center 33 (3~64) winsize 62
5548 09:29:19.018516 [CA 3] Center 33 (3~64) winsize 62
5549 09:29:19.021664 [CA 4] Center 34 (4~65) winsize 62
5550 09:29:19.024610 [CA 5] Center 33 (2~64) winsize 63
5551 09:29:19.025015
5552 09:29:19.028144 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5553 09:29:19.028543
5554 09:29:19.031218 [CATrainingPosCal] consider 2 rank data
5555 09:29:19.035083 u2DelayCellTimex100 = 270/100 ps
5556 09:29:19.037750 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5557 09:29:19.041758 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5558 09:29:19.044951 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
5559 09:29:19.048153 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5560 09:29:19.051275 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5561 09:29:19.055113 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
5562 09:29:19.055515
5563 09:29:19.061142 CA PerBit enable=1, Macro0, CA PI delay=33
5564 09:29:19.061550
5565 09:29:19.061859 [CBTSetCACLKResult] CA Dly = 33
5566 09:29:19.064994 CS Dly: 5 (0~38)
5567 09:29:19.065275
5568 09:29:19.068019 ----->DramcWriteLeveling(PI) begin...
5569 09:29:19.068343 ==
5570 09:29:19.071307 Dram Type= 6, Freq= 0, CH_1, rank 0
5571 09:29:19.074617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5572 09:29:19.074841 ==
5573 09:29:19.078212 Write leveling (Byte 0): 27 => 27
5574 09:29:19.081009 Write leveling (Byte 1): 30 => 30
5575 09:29:19.084757 DramcWriteLeveling(PI) end<-----
5576 09:29:19.084928
5577 09:29:19.085059 ==
5578 09:29:19.087906 Dram Type= 6, Freq= 0, CH_1, rank 0
5579 09:29:19.091210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5580 09:29:19.094439 ==
5581 09:29:19.094610 [Gating] SW mode calibration
5582 09:29:19.101509 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5583 09:29:19.107823 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5584 09:29:19.111250 0 14 0 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
5585 09:29:19.117771 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 09:29:19.121164 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 09:29:19.124525 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 09:29:19.131522 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 09:29:19.134646 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 09:29:19.138174 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 09:29:19.144586 0 14 28 | B1->B0 | 2f2f 3030 | 1 1 | (1 0) (1 0)
5592 09:29:19.147829 0 15 0 | B1->B0 | 2929 2929 | 1 1 | (0 0) (0 0)
5593 09:29:19.151014 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 09:29:19.154390 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 09:29:19.161208 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 09:29:19.165000 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 09:29:19.168141 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 09:29:19.174885 0 15 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5599 09:29:19.178323 0 15 28 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
5600 09:29:19.181958 1 0 0 | B1->B0 | 4444 4444 | 0 0 | (1 1) (0 0)
5601 09:29:19.188179 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 09:29:19.191314 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 09:29:19.195236 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 09:29:19.201490 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 09:29:19.205238 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 09:29:19.208407 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 09:29:19.214854 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5608 09:29:19.218331 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5609 09:29:19.221715 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 09:29:19.228020 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 09:29:19.231772 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 09:29:19.234735 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 09:29:19.241766 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 09:29:19.245266 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 09:29:19.248351 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 09:29:19.251512 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 09:29:19.257885 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 09:29:19.261130 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 09:29:19.264877 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 09:29:19.271434 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 09:29:19.274577 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 09:29:19.277689 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 09:29:19.284459 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5624 09:29:19.288248 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5625 09:29:19.291271 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 09:29:19.294484 Total UI for P1: 0, mck2ui 16
5627 09:29:19.297651 best dqsien dly found for B0: ( 1, 2, 30)
5628 09:29:19.301576 Total UI for P1: 0, mck2ui 16
5629 09:29:19.304848 best dqsien dly found for B1: ( 1, 2, 30)
5630 09:29:19.307919 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5631 09:29:19.311052 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5632 09:29:19.311139
5633 09:29:19.318157 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5634 09:29:19.321173 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5635 09:29:19.321245 [Gating] SW calibration Done
5636 09:29:19.324729 ==
5637 09:29:19.324824 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 09:29:19.331010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 09:29:19.331108 ==
5640 09:29:19.331202 RX Vref Scan: 0
5641 09:29:19.331285
5642 09:29:19.334738 RX Vref 0 -> 0, step: 1
5643 09:29:19.334829
5644 09:29:19.337958 RX Delay -80 -> 252, step: 8
5645 09:29:19.341196 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5646 09:29:19.344644 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5647 09:29:19.347826 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5648 09:29:19.350993 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5649 09:29:19.358024 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5650 09:29:19.361397 iDelay=200, Bit 5, Center 107 (16 ~ 199) 184
5651 09:29:19.364968 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5652 09:29:19.368295 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5653 09:29:19.371471 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5654 09:29:19.374506 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5655 09:29:19.381668 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5656 09:29:19.384736 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5657 09:29:19.388577 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5658 09:29:19.391395 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5659 09:29:19.395162 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5660 09:29:19.401587 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5661 09:29:19.401786 ==
5662 09:29:19.405431 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 09:29:19.408411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 09:29:19.408598 ==
5665 09:29:19.408769 DQS Delay:
5666 09:29:19.411669 DQS0 = 0, DQS1 = 0
5667 09:29:19.411909 DQM Delay:
5668 09:29:19.415300 DQM0 = 96, DQM1 = 88
5669 09:29:19.415616 DQ Delay:
5670 09:29:19.418596 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5671 09:29:19.422499 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5672 09:29:19.425250 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5673 09:29:19.428899 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5674 09:29:19.429419
5675 09:29:19.429756
5676 09:29:19.430092 ==
5677 09:29:19.431887 Dram Type= 6, Freq= 0, CH_1, rank 0
5678 09:29:19.435389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5679 09:29:19.435784 ==
5680 09:29:19.436085
5681 09:29:19.436359
5682 09:29:19.438818 TX Vref Scan disable
5683 09:29:19.442347 == TX Byte 0 ==
5684 09:29:19.445502 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5685 09:29:19.448994 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5686 09:29:19.452637 == TX Byte 1 ==
5687 09:29:19.456136 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5688 09:29:19.459028 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5689 09:29:19.459420 ==
5690 09:29:19.462183 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 09:29:19.465357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 09:29:19.468731 ==
5693 09:29:19.469201
5694 09:29:19.469624
5695 09:29:19.470067 TX Vref Scan disable
5696 09:29:19.472103 == TX Byte 0 ==
5697 09:29:19.475751 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5698 09:29:19.478687 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5699 09:29:19.482297 == TX Byte 1 ==
5700 09:29:19.485444 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5701 09:29:19.489362 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5702 09:29:19.492059
5703 09:29:19.492450 [DATLAT]
5704 09:29:19.492754 Freq=933, CH1 RK0
5705 09:29:19.493055
5706 09:29:19.496144 DATLAT Default: 0xd
5707 09:29:19.496618 0, 0xFFFF, sum = 0
5708 09:29:19.498836 1, 0xFFFF, sum = 0
5709 09:29:19.499279 2, 0xFFFF, sum = 0
5710 09:29:19.502284 3, 0xFFFF, sum = 0
5711 09:29:19.502679 4, 0xFFFF, sum = 0
5712 09:29:19.505878 5, 0xFFFF, sum = 0
5713 09:29:19.506321 6, 0xFFFF, sum = 0
5714 09:29:19.508938 7, 0xFFFF, sum = 0
5715 09:29:19.512445 8, 0xFFFF, sum = 0
5716 09:29:19.512927 9, 0xFFFF, sum = 0
5717 09:29:19.515858 10, 0x0, sum = 1
5718 09:29:19.516254 11, 0x0, sum = 2
5719 09:29:19.516562 12, 0x0, sum = 3
5720 09:29:19.518945 13, 0x0, sum = 4
5721 09:29:19.519450 best_step = 11
5722 09:29:19.519918
5723 09:29:19.520222 ==
5724 09:29:19.522585 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 09:29:19.528964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 09:29:19.529443 ==
5727 09:29:19.529751 RX Vref Scan: 1
5728 09:29:19.530097
5729 09:29:19.532634 RX Vref 0 -> 0, step: 1
5730 09:29:19.533025
5731 09:29:19.535715 RX Delay -61 -> 252, step: 4
5732 09:29:19.536105
5733 09:29:19.538756 Set Vref, RX VrefLevel [Byte0]: 57
5734 09:29:19.542153 [Byte1]: 51
5735 09:29:19.542543
5736 09:29:19.546034 Final RX Vref Byte 0 = 57 to rank0
5737 09:29:19.549001 Final RX Vref Byte 1 = 51 to rank0
5738 09:29:19.552221 Final RX Vref Byte 0 = 57 to rank1
5739 09:29:19.555218 Final RX Vref Byte 1 = 51 to rank1==
5740 09:29:19.559076 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 09:29:19.562008 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 09:29:19.562366 ==
5743 09:29:19.565973 DQS Delay:
5744 09:29:19.566404 DQS0 = 0, DQS1 = 0
5745 09:29:19.568953 DQM Delay:
5746 09:29:19.569472 DQM0 = 97, DQM1 = 90
5747 09:29:19.569778 DQ Delay:
5748 09:29:19.572286 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =96
5749 09:29:19.575555 DQ4 =96, DQ5 =108, DQ6 =106, DQ7 =96
5750 09:29:19.579323 DQ8 =80, DQ9 =78, DQ10 =94, DQ11 =84
5751 09:29:19.582191 DQ12 =100, DQ13 =98, DQ14 =96, DQ15 =96
5752 09:29:19.582583
5753 09:29:19.582901
5754 09:29:19.592318 [DQSOSCAuto] RK0, (LSB)MR18= 0x14f0, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5755 09:29:19.596037 CH1 RK0: MR19=504, MR18=14F0
5756 09:29:19.598975 CH1_RK0: MR19=0x504, MR18=0x14F0, DQSOSC=415, MR23=63, INC=62, DEC=41
5757 09:29:19.602225
5758 09:29:19.605711 ----->DramcWriteLeveling(PI) begin...
5759 09:29:19.606483 ==
5760 09:29:19.608807 Dram Type= 6, Freq= 0, CH_1, rank 1
5761 09:29:19.612221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 09:29:19.612746 ==
5763 09:29:19.615390 Write leveling (Byte 0): 28 => 28
5764 09:29:19.619252 Write leveling (Byte 1): 27 => 27
5765 09:29:19.622243 DramcWriteLeveling(PI) end<-----
5766 09:29:19.622770
5767 09:29:19.623207 ==
5768 09:29:19.625342 Dram Type= 6, Freq= 0, CH_1, rank 1
5769 09:29:19.629235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 09:29:19.629626 ==
5771 09:29:19.632334 [Gating] SW mode calibration
5772 09:29:19.639011 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5773 09:29:19.646080 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5774 09:29:19.649041 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 09:29:19.652858 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 09:29:19.659137 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5777 09:29:19.662564 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 09:29:19.665689 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 09:29:19.669258 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 09:29:19.675519 0 14 24 | B1->B0 | 3333 2e2e | 1 1 | (1 1) (1 0)
5781 09:29:19.678962 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
5782 09:29:19.682436 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5783 09:29:19.689122 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 09:29:19.692544 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 09:29:19.695685 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 09:29:19.702160 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 09:29:19.705569 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5788 09:29:19.708528 0 15 24 | B1->B0 | 2e2e 3737 | 0 0 | (0 0) (0 0)
5789 09:29:19.715735 0 15 28 | B1->B0 | 3939 4545 | 0 0 | (0 0) (0 0)
5790 09:29:19.718709 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 09:29:19.722314 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 09:29:19.728904 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 09:29:19.732286 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 09:29:19.735393 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 09:29:19.738728 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5796 09:29:19.745554 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5797 09:29:19.748744 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 09:29:19.752519 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 09:29:19.758828 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 09:29:19.761973 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 09:29:19.765298 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 09:29:19.772300 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 09:29:19.775608 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 09:29:19.779354 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 09:29:19.785657 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 09:29:19.789192 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 09:29:19.792754 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 09:29:19.798977 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 09:29:19.802825 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 09:29:19.805943 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 09:29:19.809175 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 09:29:19.816254 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5813 09:29:19.819538 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5814 09:29:19.822555 Total UI for P1: 0, mck2ui 16
5815 09:29:19.825533 best dqsien dly found for B0: ( 1, 2, 24)
5816 09:29:19.829180 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 09:29:19.832981 Total UI for P1: 0, mck2ui 16
5818 09:29:19.835991 best dqsien dly found for B1: ( 1, 2, 28)
5819 09:29:19.839314 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5820 09:29:19.842499 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5821 09:29:19.842614
5822 09:29:19.849008 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5823 09:29:19.852386 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5824 09:29:19.855952 [Gating] SW calibration Done
5825 09:29:19.856178 ==
5826 09:29:19.859341 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 09:29:19.862459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 09:29:19.862622 ==
5829 09:29:19.862749 RX Vref Scan: 0
5830 09:29:19.862867
5831 09:29:19.866172 RX Vref 0 -> 0, step: 1
5832 09:29:19.866349
5833 09:29:19.869444 RX Delay -80 -> 252, step: 8
5834 09:29:19.872675 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5835 09:29:19.875762 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5836 09:29:19.879528 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5837 09:29:19.885803 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5838 09:29:19.889737 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5839 09:29:19.892800 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5840 09:29:19.895837 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5841 09:29:19.899300 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5842 09:29:19.902530 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5843 09:29:19.905761 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5844 09:29:19.912644 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5845 09:29:19.915881 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5846 09:29:19.919567 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5847 09:29:19.922916 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5848 09:29:19.925832 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5849 09:29:19.929114 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5850 09:29:19.932731 ==
5851 09:29:19.935913 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 09:29:19.939036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 09:29:19.939116 ==
5854 09:29:19.939177 DQS Delay:
5855 09:29:19.942735 DQS0 = 0, DQS1 = 0
5856 09:29:19.942814 DQM Delay:
5857 09:29:19.946199 DQM0 = 95, DQM1 = 89
5858 09:29:19.946303 DQ Delay:
5859 09:29:19.949053 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5860 09:29:19.952263 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5861 09:29:19.955773 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5862 09:29:19.958973 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5863 09:29:19.959053
5864 09:29:19.959122
5865 09:29:19.959179 ==
5866 09:29:19.962798 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 09:29:19.965968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 09:29:19.966056 ==
5869 09:29:19.966120
5870 09:29:19.966182
5871 09:29:19.969296 TX Vref Scan disable
5872 09:29:19.972923 == TX Byte 0 ==
5873 09:29:19.975849 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5874 09:29:19.979566 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5875 09:29:19.982652 == TX Byte 1 ==
5876 09:29:19.986267 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5877 09:29:19.989278 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5878 09:29:19.989347 ==
5879 09:29:19.992746 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 09:29:19.995842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 09:29:19.999383 ==
5882 09:29:19.999464
5883 09:29:19.999528
5884 09:29:19.999594 TX Vref Scan disable
5885 09:29:20.003094 == TX Byte 0 ==
5886 09:29:20.006070 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5887 09:29:20.009871 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5888 09:29:20.013047 == TX Byte 1 ==
5889 09:29:20.016041 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5890 09:29:20.019944 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5891 09:29:20.023059
5892 09:29:20.023138 [DATLAT]
5893 09:29:20.023207 Freq=933, CH1 RK1
5894 09:29:20.023283
5895 09:29:20.026422 DATLAT Default: 0xb
5896 09:29:20.026526 0, 0xFFFF, sum = 0
5897 09:29:20.029516 1, 0xFFFF, sum = 0
5898 09:29:20.029671 2, 0xFFFF, sum = 0
5899 09:29:20.032826 3, 0xFFFF, sum = 0
5900 09:29:20.032928 4, 0xFFFF, sum = 0
5901 09:29:20.035969 5, 0xFFFF, sum = 0
5902 09:29:20.036064 6, 0xFFFF, sum = 0
5903 09:29:20.039865 7, 0xFFFF, sum = 0
5904 09:29:20.042928 8, 0xFFFF, sum = 0
5905 09:29:20.043026 9, 0xFFFF, sum = 0
5906 09:29:20.046141 10, 0x0, sum = 1
5907 09:29:20.046217 11, 0x0, sum = 2
5908 09:29:20.046279 12, 0x0, sum = 3
5909 09:29:20.049406 13, 0x0, sum = 4
5910 09:29:20.049503 best_step = 11
5911 09:29:20.049586
5912 09:29:20.049668 ==
5913 09:29:20.052650 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 09:29:20.059530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 09:29:20.059631 ==
5916 09:29:20.059723 RX Vref Scan: 0
5917 09:29:20.059805
5918 09:29:20.062627 RX Vref 0 -> 0, step: 1
5919 09:29:20.062719
5920 09:29:20.066056 RX Delay -61 -> 252, step: 4
5921 09:29:20.069593 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5922 09:29:20.076335 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5923 09:29:20.079157 iDelay=195, Bit 2, Center 84 (-9 ~ 178) 188
5924 09:29:20.082933 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5925 09:29:20.086150 iDelay=195, Bit 4, Center 96 (3 ~ 190) 188
5926 09:29:20.089685 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5927 09:29:20.093066 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5928 09:29:20.096172 iDelay=195, Bit 7, Center 92 (3 ~ 182) 180
5929 09:29:20.102549 iDelay=195, Bit 8, Center 80 (-13 ~ 174) 188
5930 09:29:20.106413 iDelay=195, Bit 9, Center 78 (-13 ~ 170) 184
5931 09:29:20.109873 iDelay=195, Bit 10, Center 92 (-1 ~ 186) 188
5932 09:29:20.112613 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5933 09:29:20.116332 iDelay=195, Bit 12, Center 100 (15 ~ 186) 172
5934 09:29:20.122670 iDelay=195, Bit 13, Center 96 (3 ~ 190) 188
5935 09:29:20.125898 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5936 09:29:20.129770 iDelay=195, Bit 15, Center 96 (3 ~ 190) 188
5937 09:29:20.129854 ==
5938 09:29:20.133124 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 09:29:20.136259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 09:29:20.136343 ==
5941 09:29:20.139546 DQS Delay:
5942 09:29:20.139625 DQS0 = 0, DQS1 = 0
5943 09:29:20.139687 DQM Delay:
5944 09:29:20.142665 DQM0 = 95, DQM1 = 90
5945 09:29:20.142734 DQ Delay:
5946 09:29:20.145945 DQ0 =98, DQ1 =90, DQ2 =84, DQ3 =94
5947 09:29:20.149819 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =92
5948 09:29:20.152921 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5949 09:29:20.156065 DQ12 =100, DQ13 =96, DQ14 =98, DQ15 =96
5950 09:29:20.156132
5951 09:29:20.156189
5952 09:29:20.166322 [DQSOSCAuto] RK1, (LSB)MR18= 0xe18, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5953 09:29:20.169255 CH1 RK1: MR19=505, MR18=E18
5954 09:29:20.172855 CH1_RK1: MR19=0x505, MR18=0xE18, DQSOSC=414, MR23=63, INC=63, DEC=42
5955 09:29:20.176278 [RxdqsGatingPostProcess] freq 933
5956 09:29:20.182625 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5957 09:29:20.186370 best DQS0 dly(2T, 0.5T) = (0, 10)
5958 09:29:20.190058 best DQS1 dly(2T, 0.5T) = (0, 10)
5959 09:29:20.193201 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5960 09:29:20.196388 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5961 09:29:20.199930 best DQS0 dly(2T, 0.5T) = (0, 10)
5962 09:29:20.200000 best DQS1 dly(2T, 0.5T) = (0, 10)
5963 09:29:20.202821 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5964 09:29:20.206061 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5965 09:29:20.209988 Pre-setting of DQS Precalculation
5966 09:29:20.216122 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5967 09:29:20.222690 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5968 09:29:20.229239 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5969 09:29:20.229314
5970 09:29:20.229380
5971 09:29:20.233144 [Calibration Summary] 1866 Mbps
5972 09:29:20.233217 CH 0, Rank 0
5973 09:29:20.236287 SW Impedance : PASS
5974 09:29:20.239331 DUTY Scan : NO K
5975 09:29:20.239419 ZQ Calibration : PASS
5976 09:29:20.243170 Jitter Meter : NO K
5977 09:29:20.246365 CBT Training : PASS
5978 09:29:20.246438 Write leveling : PASS
5979 09:29:20.249506 RX DQS gating : PASS
5980 09:29:20.252687 RX DQ/DQS(RDDQC) : PASS
5981 09:29:20.252757 TX DQ/DQS : PASS
5982 09:29:20.255854 RX DATLAT : PASS
5983 09:29:20.259530 RX DQ/DQS(Engine): PASS
5984 09:29:20.259607 TX OE : NO K
5985 09:29:20.262598 All Pass.
5986 09:29:20.262672
5987 09:29:20.262729 CH 0, Rank 1
5988 09:29:20.266311 SW Impedance : PASS
5989 09:29:20.266377 DUTY Scan : NO K
5990 09:29:20.269538 ZQ Calibration : PASS
5991 09:29:20.272617 Jitter Meter : NO K
5992 09:29:20.272683 CBT Training : PASS
5993 09:29:20.276321 Write leveling : PASS
5994 09:29:20.276387 RX DQS gating : PASS
5995 09:29:20.279412 RX DQ/DQS(RDDQC) : PASS
5996 09:29:20.282815 TX DQ/DQS : PASS
5997 09:29:20.282882 RX DATLAT : PASS
5998 09:29:20.285891 RX DQ/DQS(Engine): PASS
5999 09:29:20.289611 TX OE : NO K
6000 09:29:20.289691 All Pass.
6001 09:29:20.289751
6002 09:29:20.289807 CH 1, Rank 0
6003 09:29:20.292665 SW Impedance : PASS
6004 09:29:20.296234 DUTY Scan : NO K
6005 09:29:20.296312 ZQ Calibration : PASS
6006 09:29:20.299308 Jitter Meter : NO K
6007 09:29:20.302931 CBT Training : PASS
6008 09:29:20.303010 Write leveling : PASS
6009 09:29:20.306151 RX DQS gating : PASS
6010 09:29:20.309623 RX DQ/DQS(RDDQC) : PASS
6011 09:29:20.309701 TX DQ/DQS : PASS
6012 09:29:20.313238 RX DATLAT : PASS
6013 09:29:20.313317 RX DQ/DQS(Engine): PASS
6014 09:29:20.316338 TX OE : NO K
6015 09:29:20.316434 All Pass.
6016 09:29:20.316506
6017 09:29:20.319340 CH 1, Rank 1
6018 09:29:20.319417 SW Impedance : PASS
6019 09:29:20.322980 DUTY Scan : NO K
6020 09:29:20.326214 ZQ Calibration : PASS
6021 09:29:20.326291 Jitter Meter : NO K
6022 09:29:20.329962 CBT Training : PASS
6023 09:29:20.332830 Write leveling : PASS
6024 09:29:20.332907 RX DQS gating : PASS
6025 09:29:20.336606 RX DQ/DQS(RDDQC) : PASS
6026 09:29:20.339876 TX DQ/DQS : PASS
6027 09:29:20.339953 RX DATLAT : PASS
6028 09:29:20.342895 RX DQ/DQS(Engine): PASS
6029 09:29:20.346796 TX OE : NO K
6030 09:29:20.346873 All Pass.
6031 09:29:20.346932
6032 09:29:20.346987 DramC Write-DBI off
6033 09:29:20.350194 PER_BANK_REFRESH: Hybrid Mode
6034 09:29:20.353400 TX_TRACKING: ON
6035 09:29:20.359624 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6036 09:29:20.363200 [FAST_K] Save calibration result to emmc
6037 09:29:20.369979 dramc_set_vcore_voltage set vcore to 650000
6038 09:29:20.370107 Read voltage for 400, 6
6039 09:29:20.370166 Vio18 = 0
6040 09:29:20.373025 Vcore = 650000
6041 09:29:20.373093 Vdram = 0
6042 09:29:20.373148 Vddq = 0
6043 09:29:20.376745 Vmddr = 0
6044 09:29:20.379799 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6045 09:29:20.386640 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6046 09:29:20.386744 MEM_TYPE=3, freq_sel=20
6047 09:29:20.389644 sv_algorithm_assistance_LP4_800
6048 09:29:20.396306 ============ PULL DRAM RESETB DOWN ============
6049 09:29:20.399573 ========== PULL DRAM RESETB DOWN end =========
6050 09:29:20.403155 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6051 09:29:20.406749 ===================================
6052 09:29:20.409822 LPDDR4 DRAM CONFIGURATION
6053 09:29:20.413326 ===================================
6054 09:29:20.416306 EX_ROW_EN[0] = 0x0
6055 09:29:20.416384 EX_ROW_EN[1] = 0x0
6056 09:29:20.419893 LP4Y_EN = 0x0
6057 09:29:20.419970 WORK_FSP = 0x0
6058 09:29:20.423527 WL = 0x2
6059 09:29:20.423604 RL = 0x2
6060 09:29:20.426753 BL = 0x2
6061 09:29:20.426830 RPST = 0x0
6062 09:29:20.429669 RD_PRE = 0x0
6063 09:29:20.429748 WR_PRE = 0x1
6064 09:29:20.433379 WR_PST = 0x0
6065 09:29:20.433466 DBI_WR = 0x0
6066 09:29:20.436416 DBI_RD = 0x0
6067 09:29:20.436493 OTF = 0x1
6068 09:29:20.439908 ===================================
6069 09:29:20.443525 ===================================
6070 09:29:20.446365 ANA top config
6071 09:29:20.449754 ===================================
6072 09:29:20.449854 DLL_ASYNC_EN = 0
6073 09:29:20.453095 ALL_SLAVE_EN = 1
6074 09:29:20.456738 NEW_RANK_MODE = 1
6075 09:29:20.459899 DLL_IDLE_MODE = 1
6076 09:29:20.463168 LP45_APHY_COMB_EN = 1
6077 09:29:20.463246 TX_ODT_DIS = 1
6078 09:29:20.466803 NEW_8X_MODE = 1
6079 09:29:20.469984 ===================================
6080 09:29:20.473564 ===================================
6081 09:29:20.476658 data_rate = 800
6082 09:29:20.480359 CKR = 1
6083 09:29:20.483399 DQ_P2S_RATIO = 4
6084 09:29:20.486513 ===================================
6085 09:29:20.486592 CA_P2S_RATIO = 4
6086 09:29:20.490257 DQ_CA_OPEN = 0
6087 09:29:20.493372 DQ_SEMI_OPEN = 1
6088 09:29:20.497119 CA_SEMI_OPEN = 1
6089 09:29:20.500004 CA_FULL_RATE = 0
6090 09:29:20.500082 DQ_CKDIV4_EN = 0
6091 09:29:20.503431 CA_CKDIV4_EN = 1
6092 09:29:20.506634 CA_PREDIV_EN = 0
6093 09:29:20.509975 PH8_DLY = 0
6094 09:29:20.513312 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6095 09:29:20.517106 DQ_AAMCK_DIV = 0
6096 09:29:20.517183 CA_AAMCK_DIV = 0
6097 09:29:20.520072 CA_ADMCK_DIV = 4
6098 09:29:20.523730 DQ_TRACK_CA_EN = 0
6099 09:29:20.526641 CA_PICK = 800
6100 09:29:20.530535 CA_MCKIO = 400
6101 09:29:20.533776 MCKIO_SEMI = 400
6102 09:29:20.537039 PLL_FREQ = 3016
6103 09:29:20.537116 DQ_UI_PI_RATIO = 32
6104 09:29:20.540141 CA_UI_PI_RATIO = 32
6105 09:29:20.543782 ===================================
6106 09:29:20.546876 ===================================
6107 09:29:20.550404 memory_type:LPDDR4
6108 09:29:20.553689 GP_NUM : 10
6109 09:29:20.553788 SRAM_EN : 1
6110 09:29:20.556627 MD32_EN : 0
6111 09:29:20.560137 ===================================
6112 09:29:20.563517 [ANA_INIT] >>>>>>>>>>>>>>
6113 09:29:20.563598 <<<<<< [CONFIGURE PHASE]: ANA_TX
6114 09:29:20.566982 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6115 09:29:20.570156 ===================================
6116 09:29:20.573494 data_rate = 800,PCW = 0X7400
6117 09:29:20.577145 ===================================
6118 09:29:20.580142 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6119 09:29:20.587094 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6120 09:29:20.597119 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6121 09:29:20.603688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6122 09:29:20.606825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6123 09:29:20.610417 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6124 09:29:20.610494 [ANA_INIT] flow start
6125 09:29:20.613447 [ANA_INIT] PLL >>>>>>>>
6126 09:29:20.616716 [ANA_INIT] PLL <<<<<<<<
6127 09:29:20.616792 [ANA_INIT] MIDPI >>>>>>>>
6128 09:29:20.620687 [ANA_INIT] MIDPI <<<<<<<<
6129 09:29:20.623615 [ANA_INIT] DLL >>>>>>>>
6130 09:29:20.623692 [ANA_INIT] flow end
6131 09:29:20.630431 ============ LP4 DIFF to SE enter ============
6132 09:29:20.633961 ============ LP4 DIFF to SE exit ============
6133 09:29:20.636983 [ANA_INIT] <<<<<<<<<<<<<
6134 09:29:20.640699 [Flow] Enable top DCM control >>>>>
6135 09:29:20.640776 [Flow] Enable top DCM control <<<<<
6136 09:29:20.643756 Enable DLL master slave shuffle
6137 09:29:20.650517 ==============================================================
6138 09:29:20.653696 Gating Mode config
6139 09:29:20.657241 ==============================================================
6140 09:29:20.660939 Config description:
6141 09:29:20.670901 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6142 09:29:20.677468 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6143 09:29:20.680651 SELPH_MODE 0: By rank 1: By Phase
6144 09:29:20.687077 ==============================================================
6145 09:29:20.690922 GAT_TRACK_EN = 0
6146 09:29:20.693904 RX_GATING_MODE = 2
6147 09:29:20.694004 RX_GATING_TRACK_MODE = 2
6148 09:29:20.697552 SELPH_MODE = 1
6149 09:29:20.700629 PICG_EARLY_EN = 1
6150 09:29:20.703635 VALID_LAT_VALUE = 1
6151 09:29:20.710284 ==============================================================
6152 09:29:20.713832 Enter into Gating configuration >>>>
6153 09:29:20.716998 Exit from Gating configuration <<<<
6154 09:29:20.720634 Enter into DVFS_PRE_config >>>>>
6155 09:29:20.730935 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6156 09:29:20.733845 Exit from DVFS_PRE_config <<<<<
6157 09:29:20.737601 Enter into PICG configuration >>>>
6158 09:29:20.740476 Exit from PICG configuration <<<<
6159 09:29:20.744018 [RX_INPUT] configuration >>>>>
6160 09:29:20.747224 [RX_INPUT] configuration <<<<<
6161 09:29:20.750943 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6162 09:29:20.757463 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6163 09:29:20.763970 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6164 09:29:20.767471 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6165 09:29:20.774164 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6166 09:29:20.780509 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6167 09:29:20.784234 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6168 09:29:20.787095 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6169 09:29:20.794255 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6170 09:29:20.797261 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6171 09:29:20.800927 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6172 09:29:20.807271 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6173 09:29:20.810826 ===================================
6174 09:29:20.811016 LPDDR4 DRAM CONFIGURATION
6175 09:29:20.813943 ===================================
6176 09:29:20.817554 EX_ROW_EN[0] = 0x0
6177 09:29:20.817684 EX_ROW_EN[1] = 0x0
6178 09:29:20.820684 LP4Y_EN = 0x0
6179 09:29:20.820777 WORK_FSP = 0x0
6180 09:29:20.823721 WL = 0x2
6181 09:29:20.827541 RL = 0x2
6182 09:29:20.827692 BL = 0x2
6183 09:29:20.830568 RPST = 0x0
6184 09:29:20.830709 RD_PRE = 0x0
6185 09:29:20.834020 WR_PRE = 0x1
6186 09:29:20.834178 WR_PST = 0x0
6187 09:29:20.837388 DBI_WR = 0x0
6188 09:29:20.837507 DBI_RD = 0x0
6189 09:29:20.840839 OTF = 0x1
6190 09:29:20.843936 ===================================
6191 09:29:20.847516 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6192 09:29:20.895502 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6193 09:29:20.896225 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 09:29:20.896821 ===================================
6195 09:29:20.897384 LPDDR4 DRAM CONFIGURATION
6196 09:29:20.897951 ===================================
6197 09:29:20.898562 EX_ROW_EN[0] = 0x10
6198 09:29:20.899111 EX_ROW_EN[1] = 0x0
6199 09:29:20.899650 LP4Y_EN = 0x0
6200 09:29:20.900194 WORK_FSP = 0x0
6201 09:29:20.900715 WL = 0x2
6202 09:29:20.901252 RL = 0x2
6203 09:29:20.901778 BL = 0x2
6204 09:29:20.902336 RPST = 0x0
6205 09:29:20.902873 RD_PRE = 0x0
6206 09:29:20.903411 WR_PRE = 0x1
6207 09:29:20.903938 WR_PST = 0x0
6208 09:29:20.904473 DBI_WR = 0x0
6209 09:29:20.905034 DBI_RD = 0x0
6210 09:29:20.905579 OTF = 0x1
6211 09:29:20.906152 ===================================
6212 09:29:20.907022 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6213 09:29:20.907501 nWR fixed to 30
6214 09:29:20.907856 [ModeRegInit_LP4] CH0 RK0
6215 09:29:20.908148 [ModeRegInit_LP4] CH0 RK1
6216 09:29:20.909724 [ModeRegInit_LP4] CH1 RK0
6217 09:29:20.912718 [ModeRegInit_LP4] CH1 RK1
6218 09:29:20.913386 match AC timing 19
6219 09:29:20.919381 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6220 09:29:20.922415 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6221 09:29:20.926217 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6222 09:29:20.932726 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6223 09:29:20.935684 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6224 09:29:20.936232 ==
6225 09:29:20.939268 Dram Type= 6, Freq= 0, CH_0, rank 0
6226 09:29:20.942830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6227 09:29:20.943387 ==
6228 09:29:20.948974 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6229 09:29:20.955329 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6230 09:29:20.958900 [CA 0] Center 36 (8~64) winsize 57
6231 09:29:20.962448 [CA 1] Center 36 (8~64) winsize 57
6232 09:29:20.965695 [CA 2] Center 36 (8~64) winsize 57
6233 09:29:20.965993 [CA 3] Center 36 (8~64) winsize 57
6234 09:29:20.968692 [CA 4] Center 36 (8~64) winsize 57
6235 09:29:20.972170 [CA 5] Center 36 (8~64) winsize 57
6236 09:29:20.972524
6237 09:29:20.975402 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6238 09:29:20.979168
6239 09:29:20.982126 [CATrainingPosCal] consider 1 rank data
6240 09:29:20.982289 u2DelayCellTimex100 = 270/100 ps
6241 09:29:20.989217 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 09:29:20.992476 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 09:29:20.995631 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 09:29:20.998758 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 09:29:21.002357 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 09:29:21.005973 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 09:29:21.006069
6248 09:29:21.008956 CA PerBit enable=1, Macro0, CA PI delay=36
6249 09:29:21.009069
6250 09:29:21.012157 [CBTSetCACLKResult] CA Dly = 36
6251 09:29:21.015526 CS Dly: 1 (0~32)
6252 09:29:21.015618 ==
6253 09:29:21.019255 Dram Type= 6, Freq= 0, CH_0, rank 1
6254 09:29:21.022286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 09:29:21.022408 ==
6256 09:29:21.028951 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6257 09:29:21.032597 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6258 09:29:21.035794 [CA 0] Center 36 (8~64) winsize 57
6259 09:29:21.038862 [CA 1] Center 36 (8~64) winsize 57
6260 09:29:21.042303 [CA 2] Center 36 (8~64) winsize 57
6261 09:29:21.045470 [CA 3] Center 36 (8~64) winsize 57
6262 09:29:21.049157 [CA 4] Center 36 (8~64) winsize 57
6263 09:29:21.052045 [CA 5] Center 36 (8~64) winsize 57
6264 09:29:21.052183
6265 09:29:21.055469 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6266 09:29:21.055616
6267 09:29:21.059213 [CATrainingPosCal] consider 2 rank data
6268 09:29:21.062223 u2DelayCellTimex100 = 270/100 ps
6269 09:29:21.065885 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 09:29:21.068971 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 09:29:21.072046 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 09:29:21.075620 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 09:29:21.082309 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 09:29:21.085537 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 09:29:21.085692
6276 09:29:21.088704 CA PerBit enable=1, Macro0, CA PI delay=36
6277 09:29:21.088801
6278 09:29:21.092323 [CBTSetCACLKResult] CA Dly = 36
6279 09:29:21.092391 CS Dly: 1 (0~32)
6280 09:29:21.092450
6281 09:29:21.095499 ----->DramcWriteLeveling(PI) begin...
6282 09:29:21.095582 ==
6283 09:29:21.098949 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 09:29:21.105619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 09:29:21.105701 ==
6286 09:29:21.109226 Write leveling (Byte 0): 40 => 8
6287 09:29:21.109315 Write leveling (Byte 1): 32 => 0
6288 09:29:21.112335 DramcWriteLeveling(PI) end<-----
6289 09:29:21.112430
6290 09:29:21.112504 ==
6291 09:29:21.116008 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 09:29:21.122271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 09:29:21.122430 ==
6294 09:29:21.122520 [Gating] SW mode calibration
6295 09:29:21.132477 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6296 09:29:21.135832 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6297 09:29:21.138977 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6298 09:29:21.145654 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6299 09:29:21.149540 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6300 09:29:21.152702 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 09:29:21.159399 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 09:29:21.162890 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 09:29:21.166456 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 09:29:21.172849 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 09:29:21.176494 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 09:29:21.179807 Total UI for P1: 0, mck2ui 16
6307 09:29:21.183025 best dqsien dly found for B0: ( 0, 14, 24)
6308 09:29:21.186149 Total UI for P1: 0, mck2ui 16
6309 09:29:21.189028 best dqsien dly found for B1: ( 0, 14, 24)
6310 09:29:21.192978 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6311 09:29:21.196070 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6312 09:29:21.196513
6313 09:29:21.199066 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6314 09:29:21.202677 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6315 09:29:21.206319 [Gating] SW calibration Done
6316 09:29:21.206722 ==
6317 09:29:21.209072 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 09:29:21.212863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 09:29:21.215855 ==
6320 09:29:21.216066 RX Vref Scan: 0
6321 09:29:21.216227
6322 09:29:21.218918 RX Vref 0 -> 0, step: 1
6323 09:29:21.219086
6324 09:29:21.222492 RX Delay -410 -> 252, step: 16
6325 09:29:21.226001 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6326 09:29:21.228904 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6327 09:29:21.232463 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6328 09:29:21.239193 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6329 09:29:21.242733 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6330 09:29:21.245952 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6331 09:29:21.249636 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6332 09:29:21.256398 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6333 09:29:21.259599 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6334 09:29:21.263290 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6335 09:29:21.266417 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6336 09:29:21.273112 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6337 09:29:21.276463 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6338 09:29:21.279505 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6339 09:29:21.282560 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6340 09:29:21.289523 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6341 09:29:21.289921 ==
6342 09:29:21.292875 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 09:29:21.295787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 09:29:21.296363 ==
6345 09:29:21.296696 DQS Delay:
6346 09:29:21.299563 DQS0 = 35, DQS1 = 51
6347 09:29:21.299963 DQM Delay:
6348 09:29:21.302724 DQM0 = 7, DQM1 = 10
6349 09:29:21.303121 DQ Delay:
6350 09:29:21.306129 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6351 09:29:21.309568 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6352 09:29:21.313085 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6353 09:29:21.316415 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6354 09:29:21.316931
6355 09:29:21.317323
6356 09:29:21.317612 ==
6357 09:29:21.319279 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 09:29:21.322887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 09:29:21.323382 ==
6360 09:29:21.323699
6361 09:29:21.323983
6362 09:29:21.326048 TX Vref Scan disable
6363 09:29:21.329256 == TX Byte 0 ==
6364 09:29:21.333104 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 09:29:21.335996 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 09:29:21.336400 == TX Byte 1 ==
6367 09:29:21.342589 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6368 09:29:21.346210 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6369 09:29:21.346609 ==
6370 09:29:21.349099 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 09:29:21.352668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 09:29:21.353068 ==
6373 09:29:21.353487
6374 09:29:21.355599
6375 09:29:21.355995 TX Vref Scan disable
6376 09:29:21.359200 == TX Byte 0 ==
6377 09:29:21.362385 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6378 09:29:21.365687 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6379 09:29:21.369350 == TX Byte 1 ==
6380 09:29:21.372548 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6381 09:29:21.376106 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6382 09:29:21.376642
6383 09:29:21.377094 [DATLAT]
6384 09:29:21.379060 Freq=400, CH0 RK0
6385 09:29:21.379645
6386 09:29:21.380002 DATLAT Default: 0xf
6387 09:29:21.382574 0, 0xFFFF, sum = 0
6388 09:29:21.385568 1, 0xFFFF, sum = 0
6389 09:29:21.386340 2, 0xFFFF, sum = 0
6390 09:29:21.389115 3, 0xFFFF, sum = 0
6391 09:29:21.389667 4, 0xFFFF, sum = 0
6392 09:29:21.392672 5, 0xFFFF, sum = 0
6393 09:29:21.393188 6, 0xFFFF, sum = 0
6394 09:29:21.396010 7, 0xFFFF, sum = 0
6395 09:29:21.396534 8, 0xFFFF, sum = 0
6396 09:29:21.399085 9, 0xFFFF, sum = 0
6397 09:29:21.399618 10, 0xFFFF, sum = 0
6398 09:29:21.402895 11, 0xFFFF, sum = 0
6399 09:29:21.403375 12, 0xFFFF, sum = 0
6400 09:29:21.406036 13, 0x0, sum = 1
6401 09:29:21.406542 14, 0x0, sum = 2
6402 09:29:21.409119 15, 0x0, sum = 3
6403 09:29:21.409628 16, 0x0, sum = 4
6404 09:29:21.412717 best_step = 14
6405 09:29:21.413267
6406 09:29:21.413765 ==
6407 09:29:21.415688 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 09:29:21.419203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 09:29:21.419602 ==
6410 09:29:21.419909 RX Vref Scan: 1
6411 09:29:21.420195
6412 09:29:21.422760 RX Vref 0 -> 0, step: 1
6413 09:29:21.423156
6414 09:29:21.425951 RX Delay -343 -> 252, step: 8
6415 09:29:21.426393
6416 09:29:21.428961 Set Vref, RX VrefLevel [Byte0]: 52
6417 09:29:21.432656 [Byte1]: 50
6418 09:29:21.436382
6419 09:29:21.436778 Final RX Vref Byte 0 = 52 to rank0
6420 09:29:21.440073 Final RX Vref Byte 1 = 50 to rank0
6421 09:29:21.442993 Final RX Vref Byte 0 = 52 to rank1
6422 09:29:21.446620 Final RX Vref Byte 1 = 50 to rank1==
6423 09:29:21.450174 Dram Type= 6, Freq= 0, CH_0, rank 0
6424 09:29:21.456374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 09:29:21.456825 ==
6426 09:29:21.457265 DQS Delay:
6427 09:29:21.459970 DQS0 = 44, DQS1 = 60
6428 09:29:21.460396 DQM Delay:
6429 09:29:21.460775 DQM0 = 11, DQM1 = 15
6430 09:29:21.462893 DQ Delay:
6431 09:29:21.466416 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6432 09:29:21.466888 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6433 09:29:21.469713 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6434 09:29:21.473347 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6435 09:29:21.473825
6436 09:29:21.476363
6437 09:29:21.483027 [DQSOSCAuto] RK0, (LSB)MR18= 0x8f5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
6438 09:29:21.486585 CH0 RK0: MR19=C0C, MR18=8F5D
6439 09:29:21.492781 CH0_RK0: MR19=0xC0C, MR18=0x8F5D, DQSOSC=391, MR23=63, INC=386, DEC=257
6440 09:29:21.493187 ==
6441 09:29:21.496406 Dram Type= 6, Freq= 0, CH_0, rank 1
6442 09:29:21.499449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 09:29:21.499850 ==
6444 09:29:21.502912 [Gating] SW mode calibration
6445 09:29:21.510202 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6446 09:29:21.513142 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6447 09:29:21.519833 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6448 09:29:21.523094 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6449 09:29:21.526690 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 09:29:21.533062 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 09:29:21.536263 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 09:29:21.539354 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 09:29:21.546236 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 09:29:21.549898 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 09:29:21.552848 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 09:29:21.556216 Total UI for P1: 0, mck2ui 16
6457 09:29:21.559676 best dqsien dly found for B0: ( 0, 14, 24)
6458 09:29:21.562998 Total UI for P1: 0, mck2ui 16
6459 09:29:21.566435 best dqsien dly found for B1: ( 0, 14, 24)
6460 09:29:21.569408 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6461 09:29:21.572912 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6462 09:29:21.573018
6463 09:29:21.579987 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6464 09:29:21.583138 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6465 09:29:21.583215 [Gating] SW calibration Done
6466 09:29:21.586174 ==
6467 09:29:21.589864 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 09:29:21.592793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 09:29:21.592872 ==
6470 09:29:21.592932 RX Vref Scan: 0
6471 09:29:21.592989
6472 09:29:21.596214 RX Vref 0 -> 0, step: 1
6473 09:29:21.596291
6474 09:29:21.599412 RX Delay -410 -> 252, step: 16
6475 09:29:21.603252 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6476 09:29:21.606310 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6477 09:29:21.612767 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6478 09:29:21.616384 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6479 09:29:21.619352 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6480 09:29:21.623019 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6481 09:29:21.629840 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6482 09:29:21.632660 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6483 09:29:21.636465 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6484 09:29:21.639588 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6485 09:29:21.646487 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6486 09:29:21.649747 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6487 09:29:21.652830 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6488 09:29:21.656501 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6489 09:29:21.662898 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6490 09:29:21.666450 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6491 09:29:21.666527 ==
6492 09:29:21.669887 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 09:29:21.673150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 09:29:21.673229 ==
6495 09:29:21.676679 DQS Delay:
6496 09:29:21.676757 DQS0 = 43, DQS1 = 51
6497 09:29:21.680112 DQM Delay:
6498 09:29:21.680190 DQM0 = 11, DQM1 = 10
6499 09:29:21.680251 DQ Delay:
6500 09:29:21.683041 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6501 09:29:21.686560 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6502 09:29:21.689722 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6503 09:29:21.693506 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6504 09:29:21.693583
6505 09:29:21.693643
6506 09:29:21.693699 ==
6507 09:29:21.696466 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 09:29:21.699899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 09:29:21.699976 ==
6510 09:29:21.703168
6511 09:29:21.703245
6512 09:29:21.703304 TX Vref Scan disable
6513 09:29:21.706723 == TX Byte 0 ==
6514 09:29:21.710082 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6515 09:29:21.713030 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6516 09:29:21.716094 == TX Byte 1 ==
6517 09:29:21.719474 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6518 09:29:21.722820 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6519 09:29:21.722897 ==
6520 09:29:21.726219 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 09:29:21.729970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 09:29:21.733202 ==
6523 09:29:21.733278
6524 09:29:21.733337
6525 09:29:21.733393 TX Vref Scan disable
6526 09:29:21.736081 == TX Byte 0 ==
6527 09:29:21.739564 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6528 09:29:21.743164 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6529 09:29:21.746458 == TX Byte 1 ==
6530 09:29:21.749467 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6531 09:29:21.752719 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6532 09:29:21.752797
6533 09:29:21.752856 [DATLAT]
6534 09:29:21.756419 Freq=400, CH0 RK1
6535 09:29:21.756496
6536 09:29:21.759547 DATLAT Default: 0xe
6537 09:29:21.759624 0, 0xFFFF, sum = 0
6538 09:29:21.762612 1, 0xFFFF, sum = 0
6539 09:29:21.762691 2, 0xFFFF, sum = 0
6540 09:29:21.766353 3, 0xFFFF, sum = 0
6541 09:29:21.766431 4, 0xFFFF, sum = 0
6542 09:29:21.769797 5, 0xFFFF, sum = 0
6543 09:29:21.769900 6, 0xFFFF, sum = 0
6544 09:29:21.772809 7, 0xFFFF, sum = 0
6545 09:29:21.772887 8, 0xFFFF, sum = 0
6546 09:29:21.776212 9, 0xFFFF, sum = 0
6547 09:29:21.776290 10, 0xFFFF, sum = 0
6548 09:29:21.779537 11, 0xFFFF, sum = 0
6549 09:29:21.779615 12, 0xFFFF, sum = 0
6550 09:29:21.782872 13, 0x0, sum = 1
6551 09:29:21.782946 14, 0x0, sum = 2
6552 09:29:21.786228 15, 0x0, sum = 3
6553 09:29:21.786311 16, 0x0, sum = 4
6554 09:29:21.789584 best_step = 14
6555 09:29:21.789661
6556 09:29:21.789734 ==
6557 09:29:21.793271 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 09:29:21.796491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 09:29:21.796570 ==
6560 09:29:21.799487 RX Vref Scan: 0
6561 09:29:21.799565
6562 09:29:21.799625 RX Vref 0 -> 0, step: 1
6563 09:29:21.799680
6564 09:29:21.802619 RX Delay -343 -> 252, step: 8
6565 09:29:21.810475 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6566 09:29:21.813874 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6567 09:29:21.817381 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6568 09:29:21.820749 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6569 09:29:21.826976 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6570 09:29:21.830281 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6571 09:29:21.833488 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6572 09:29:21.837232 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6573 09:29:21.843773 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6574 09:29:21.847476 iDelay=217, Bit 9, Center -56 (-295 ~ 184) 480
6575 09:29:21.850494 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6576 09:29:21.853666 iDelay=217, Bit 11, Center -52 (-287 ~ 184) 472
6577 09:29:21.861145 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6578 09:29:21.864039 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6579 09:29:21.867116 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6580 09:29:21.870690 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6581 09:29:21.874381 ==
6582 09:29:21.877424 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 09:29:21.880919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 09:29:21.880998 ==
6585 09:29:21.881059 DQS Delay:
6586 09:29:21.883892 DQS0 = 48, DQS1 = 56
6587 09:29:21.883970 DQM Delay:
6588 09:29:21.887449 DQM0 = 12, DQM1 = 10
6589 09:29:21.887526 DQ Delay:
6590 09:29:21.890556 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6591 09:29:21.893885 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6592 09:29:21.897281 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6593 09:29:21.900511 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6594 09:29:21.900605
6595 09:29:21.900668
6596 09:29:21.907413 [DQSOSCAuto] RK1, (LSB)MR18= 0x986b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6597 09:29:21.910398 CH0 RK1: MR19=C0C, MR18=986B
6598 09:29:21.917405 CH0_RK1: MR19=0xC0C, MR18=0x986B, DQSOSC=390, MR23=63, INC=388, DEC=258
6599 09:29:21.920843 [RxdqsGatingPostProcess] freq 400
6600 09:29:21.923786 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6601 09:29:21.927274 best DQS0 dly(2T, 0.5T) = (0, 10)
6602 09:29:21.930743 best DQS1 dly(2T, 0.5T) = (0, 10)
6603 09:29:21.934329 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6604 09:29:21.937883 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6605 09:29:21.940575 best DQS0 dly(2T, 0.5T) = (0, 10)
6606 09:29:21.944176 best DQS1 dly(2T, 0.5T) = (0, 10)
6607 09:29:21.947272 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6608 09:29:21.950854 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6609 09:29:21.953856 Pre-setting of DQS Precalculation
6610 09:29:21.957081 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6611 09:29:21.957154 ==
6612 09:29:21.960931 Dram Type= 6, Freq= 0, CH_1, rank 0
6613 09:29:21.967752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 09:29:21.967832 ==
6615 09:29:21.970792 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6616 09:29:21.977352 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6617 09:29:21.981312 [CA 0] Center 36 (8~64) winsize 57
6618 09:29:21.984492 [CA 1] Center 36 (8~64) winsize 57
6619 09:29:21.988067 [CA 2] Center 36 (8~64) winsize 57
6620 09:29:21.991030 [CA 3] Center 36 (8~64) winsize 57
6621 09:29:21.994809 [CA 4] Center 36 (8~64) winsize 57
6622 09:29:21.997729 [CA 5] Center 36 (8~64) winsize 57
6623 09:29:21.997806
6624 09:29:22.001178 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6625 09:29:22.001255
6626 09:29:22.004389 [CATrainingPosCal] consider 1 rank data
6627 09:29:22.007882 u2DelayCellTimex100 = 270/100 ps
6628 09:29:22.011304 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 09:29:22.014270 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 09:29:22.017999 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 09:29:22.021135 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 09:29:22.024782 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 09:29:22.027747 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 09:29:22.027836
6635 09:29:22.031540 CA PerBit enable=1, Macro0, CA PI delay=36
6636 09:29:22.031636
6637 09:29:22.034511 [CBTSetCACLKResult] CA Dly = 36
6638 09:29:22.038142 CS Dly: 1 (0~32)
6639 09:29:22.038247 ==
6640 09:29:22.041326 Dram Type= 6, Freq= 0, CH_1, rank 1
6641 09:29:22.044779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 09:29:22.044908 ==
6643 09:29:22.051205 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6644 09:29:22.057936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6645 09:29:22.061570 [CA 0] Center 36 (8~64) winsize 57
6646 09:29:22.061890 [CA 1] Center 36 (8~64) winsize 57
6647 09:29:22.064478 [CA 2] Center 36 (8~64) winsize 57
6648 09:29:22.067803 [CA 3] Center 36 (8~64) winsize 57
6649 09:29:22.071476 [CA 4] Center 36 (8~64) winsize 57
6650 09:29:22.074581 [CA 5] Center 36 (8~64) winsize 57
6651 09:29:22.074949
6652 09:29:22.078471 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6653 09:29:22.078914
6654 09:29:22.081829 [CATrainingPosCal] consider 2 rank data
6655 09:29:22.085268 u2DelayCellTimex100 = 270/100 ps
6656 09:29:22.088193 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 09:29:22.094686 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 09:29:22.098483 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 09:29:22.101511 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 09:29:22.105185 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 09:29:22.107983 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 09:29:22.108384
6663 09:29:22.111419 CA PerBit enable=1, Macro0, CA PI delay=36
6664 09:29:22.111818
6665 09:29:22.114985 [CBTSetCACLKResult] CA Dly = 36
6666 09:29:22.115379 CS Dly: 1 (0~32)
6667 09:29:22.115684
6668 09:29:22.118292 ----->DramcWriteLeveling(PI) begin...
6669 09:29:22.121590 ==
6670 09:29:22.125105 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 09:29:22.128189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 09:29:22.128402 ==
6673 09:29:22.131350 Write leveling (Byte 0): 40 => 8
6674 09:29:22.134970 Write leveling (Byte 1): 40 => 8
6675 09:29:22.138123 DramcWriteLeveling(PI) end<-----
6676 09:29:22.138297
6677 09:29:22.138469 ==
6678 09:29:22.141479 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 09:29:22.144762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 09:29:22.144938 ==
6681 09:29:22.147896 [Gating] SW mode calibration
6682 09:29:22.154932 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6683 09:29:22.158403 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6684 09:29:22.164570 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6685 09:29:22.168195 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6686 09:29:22.171643 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6687 09:29:22.178484 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 09:29:22.181651 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 09:29:22.185195 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 09:29:22.191443 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 09:29:22.195241 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 09:29:22.198251 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 09:29:22.202058 Total UI for P1: 0, mck2ui 16
6694 09:29:22.205378 best dqsien dly found for B0: ( 0, 14, 24)
6695 09:29:22.208198 Total UI for P1: 0, mck2ui 16
6696 09:29:22.211991 best dqsien dly found for B1: ( 0, 14, 24)
6697 09:29:22.214727 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6698 09:29:22.218132 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6699 09:29:22.218545
6700 09:29:22.224701 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6701 09:29:22.228250 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6702 09:29:22.228644 [Gating] SW calibration Done
6703 09:29:22.231615 ==
6704 09:29:22.235379 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 09:29:22.238575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 09:29:22.239058 ==
6707 09:29:22.239367 RX Vref Scan: 0
6708 09:29:22.239648
6709 09:29:22.241641 RX Vref 0 -> 0, step: 1
6710 09:29:22.242161
6711 09:29:22.244711 RX Delay -410 -> 252, step: 16
6712 09:29:22.248583 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6713 09:29:22.251519 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6714 09:29:22.258335 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6715 09:29:22.262028 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6716 09:29:22.264807 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6717 09:29:22.268018 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6718 09:29:22.274822 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6719 09:29:22.278415 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6720 09:29:22.281358 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6721 09:29:22.285071 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6722 09:29:22.291711 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6723 09:29:22.294912 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6724 09:29:22.298334 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6725 09:29:22.301344 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6726 09:29:22.308338 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6727 09:29:22.311511 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6728 09:29:22.311911 ==
6729 09:29:22.314682 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 09:29:22.318162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 09:29:22.318563 ==
6732 09:29:22.321596 DQS Delay:
6733 09:29:22.322251 DQS0 = 51, DQS1 = 59
6734 09:29:22.325030 DQM Delay:
6735 09:29:22.325390 DQM0 = 19, DQM1 = 16
6736 09:29:22.325686 DQ Delay:
6737 09:29:22.328291 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6738 09:29:22.331322 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6739 09:29:22.334953 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6740 09:29:22.338023 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6741 09:29:22.338299
6742 09:29:22.338513
6743 09:29:22.338722 ==
6744 09:29:22.341439 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 09:29:22.347752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 09:29:22.348031 ==
6747 09:29:22.348259
6748 09:29:22.348466
6749 09:29:22.348657 TX Vref Scan disable
6750 09:29:22.351504 == TX Byte 0 ==
6751 09:29:22.354661 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 09:29:22.357751 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 09:29:22.361097 == TX Byte 1 ==
6754 09:29:22.365006 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 09:29:22.368098 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 09:29:22.371456 ==
6757 09:29:22.371742 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 09:29:22.378083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 09:29:22.378450 ==
6760 09:29:22.378674
6761 09:29:22.378935
6762 09:29:22.379183 TX Vref Scan disable
6763 09:29:22.381755 == TX Byte 0 ==
6764 09:29:22.385381 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 09:29:22.388178 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 09:29:22.391699 == TX Byte 1 ==
6767 09:29:22.394630 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 09:29:22.398464 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 09:29:22.398987
6770 09:29:22.401930 [DATLAT]
6771 09:29:22.402399 Freq=400, CH1 RK0
6772 09:29:22.402741
6773 09:29:22.404901 DATLAT Default: 0xf
6774 09:29:22.405353 0, 0xFFFF, sum = 0
6775 09:29:22.408549 1, 0xFFFF, sum = 0
6776 09:29:22.408952 2, 0xFFFF, sum = 0
6777 09:29:22.411657 3, 0xFFFF, sum = 0
6778 09:29:22.412062 4, 0xFFFF, sum = 0
6779 09:29:22.414903 5, 0xFFFF, sum = 0
6780 09:29:22.415310 6, 0xFFFF, sum = 0
6781 09:29:22.418503 7, 0xFFFF, sum = 0
6782 09:29:22.418905 8, 0xFFFF, sum = 0
6783 09:29:22.421537 9, 0xFFFF, sum = 0
6784 09:29:22.421951 10, 0xFFFF, sum = 0
6785 09:29:22.424842 11, 0xFFFF, sum = 0
6786 09:29:22.428267 12, 0xFFFF, sum = 0
6787 09:29:22.428673 13, 0x0, sum = 1
6788 09:29:22.428990 14, 0x0, sum = 2
6789 09:29:22.432020 15, 0x0, sum = 3
6790 09:29:22.432511 16, 0x0, sum = 4
6791 09:29:22.435123 best_step = 14
6792 09:29:22.435548
6793 09:29:22.435853 ==
6794 09:29:22.438210 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 09:29:22.441470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 09:29:22.441947 ==
6797 09:29:22.445207 RX Vref Scan: 1
6798 09:29:22.445683
6799 09:29:22.446035 RX Vref 0 -> 0, step: 1
6800 09:29:22.447962
6801 09:29:22.448359 RX Delay -359 -> 252, step: 8
6802 09:29:22.448669
6803 09:29:22.451868 Set Vref, RX VrefLevel [Byte0]: 57
6804 09:29:22.454967 [Byte1]: 51
6805 09:29:22.460569
6806 09:29:22.461093 Final RX Vref Byte 0 = 57 to rank0
6807 09:29:22.463638 Final RX Vref Byte 1 = 51 to rank0
6808 09:29:22.466604 Final RX Vref Byte 0 = 57 to rank1
6809 09:29:22.470103 Final RX Vref Byte 1 = 51 to rank1==
6810 09:29:22.473244 Dram Type= 6, Freq= 0, CH_1, rank 0
6811 09:29:22.479923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 09:29:22.480367 ==
6813 09:29:22.480686 DQS Delay:
6814 09:29:22.482918 DQS0 = 48, DQS1 = 64
6815 09:29:22.483317 DQM Delay:
6816 09:29:22.483625 DQM0 = 10, DQM1 = 16
6817 09:29:22.486650 DQ Delay:
6818 09:29:22.490070 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6819 09:29:22.490474 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6820 09:29:22.493407 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6821 09:29:22.496943 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6822 09:29:22.497347
6823 09:29:22.497655
6824 09:29:22.506969 [DQSOSCAuto] RK0, (LSB)MR18= 0x8c33, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6825 09:29:22.509826 CH1 RK0: MR19=C0C, MR18=8C33
6826 09:29:22.516763 CH1_RK0: MR19=0xC0C, MR18=0x8C33, DQSOSC=392, MR23=63, INC=384, DEC=256
6827 09:29:22.517244 ==
6828 09:29:22.520322 Dram Type= 6, Freq= 0, CH_1, rank 1
6829 09:29:22.523561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 09:29:22.523963 ==
6831 09:29:22.526477 [Gating] SW mode calibration
6832 09:29:22.533304 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6833 09:29:22.537337 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6834 09:29:22.543569 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6835 09:29:22.546585 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6836 09:29:22.550397 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6837 09:29:22.557017 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 09:29:22.560029 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 09:29:22.563507 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 09:29:22.570269 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 09:29:22.573701 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 09:29:22.577286 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 09:29:22.580486 Total UI for P1: 0, mck2ui 16
6844 09:29:22.583663 best dqsien dly found for B0: ( 0, 14, 24)
6845 09:29:22.586671 Total UI for P1: 0, mck2ui 16
6846 09:29:22.590583 best dqsien dly found for B1: ( 0, 14, 24)
6847 09:29:22.593719 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6848 09:29:22.597524 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6849 09:29:22.598059
6850 09:29:22.600817 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6851 09:29:22.606995 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6852 09:29:22.607392 [Gating] SW calibration Done
6853 09:29:22.607700 ==
6854 09:29:22.610251 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 09:29:22.617204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 09:29:22.617687 ==
6857 09:29:22.618050 RX Vref Scan: 0
6858 09:29:22.618360
6859 09:29:22.620270 RX Vref 0 -> 0, step: 1
6860 09:29:22.620665
6861 09:29:22.623501 RX Delay -410 -> 252, step: 16
6862 09:29:22.627183 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6863 09:29:22.630145 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6864 09:29:22.636964 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6865 09:29:22.640396 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6866 09:29:22.643855 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6867 09:29:22.647334 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6868 09:29:22.650862 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6869 09:29:22.657650 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6870 09:29:22.660984 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6871 09:29:22.663762 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6872 09:29:22.667650 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6873 09:29:22.674056 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6874 09:29:22.676949 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6875 09:29:22.680466 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6876 09:29:22.687188 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6877 09:29:22.690396 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6878 09:29:22.690794 ==
6879 09:29:22.694095 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 09:29:22.697469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 09:29:22.697948 ==
6882 09:29:22.700859 DQS Delay:
6883 09:29:22.701247 DQS0 = 43, DQS1 = 59
6884 09:29:22.701551 DQM Delay:
6885 09:29:22.703780 DQM0 = 9, DQM1 = 17
6886 09:29:22.704175 DQ Delay:
6887 09:29:22.707534 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6888 09:29:22.710341 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6889 09:29:22.713763 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6890 09:29:22.717491 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6891 09:29:22.717889
6892 09:29:22.718230
6893 09:29:22.718514 ==
6894 09:29:22.720893 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 09:29:22.723886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 09:29:22.724365 ==
6897 09:29:22.724675
6898 09:29:22.724956
6899 09:29:22.726975 TX Vref Scan disable
6900 09:29:22.730691 == TX Byte 0 ==
6901 09:29:22.733741 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6902 09:29:22.736957 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6903 09:29:22.737354 == TX Byte 1 ==
6904 09:29:22.743685 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6905 09:29:22.747430 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6906 09:29:22.747826 ==
6907 09:29:22.750447 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 09:29:22.754466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 09:29:22.754947 ==
6910 09:29:22.755257
6911 09:29:22.755538
6912 09:29:22.757114 TX Vref Scan disable
6913 09:29:22.760964 == TX Byte 0 ==
6914 09:29:22.764073 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6915 09:29:22.767148 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6916 09:29:22.767557 == TX Byte 1 ==
6917 09:29:22.774482 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6918 09:29:22.777149 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6919 09:29:22.777545
6920 09:29:22.777851 [DATLAT]
6921 09:29:22.780561 Freq=400, CH1 RK1
6922 09:29:22.780957
6923 09:29:22.781261 DATLAT Default: 0xe
6924 09:29:22.783959 0, 0xFFFF, sum = 0
6925 09:29:22.784359 1, 0xFFFF, sum = 0
6926 09:29:22.787325 2, 0xFFFF, sum = 0
6927 09:29:22.787768 3, 0xFFFF, sum = 0
6928 09:29:22.790712 4, 0xFFFF, sum = 0
6929 09:29:22.791112 5, 0xFFFF, sum = 0
6930 09:29:22.793964 6, 0xFFFF, sum = 0
6931 09:29:22.794394 7, 0xFFFF, sum = 0
6932 09:29:22.797206 8, 0xFFFF, sum = 0
6933 09:29:22.797606 9, 0xFFFF, sum = 0
6934 09:29:22.800930 10, 0xFFFF, sum = 0
6935 09:29:22.804301 11, 0xFFFF, sum = 0
6936 09:29:22.804779 12, 0xFFFF, sum = 0
6937 09:29:22.807280 13, 0x0, sum = 1
6938 09:29:22.807683 14, 0x0, sum = 2
6939 09:29:22.810870 15, 0x0, sum = 3
6940 09:29:22.811268 16, 0x0, sum = 4
6941 09:29:22.811577 best_step = 14
6942 09:29:22.811952
6943 09:29:22.813913 ==
6944 09:29:22.816963 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 09:29:22.820497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 09:29:22.820893 ==
6947 09:29:22.821197 RX Vref Scan: 0
6948 09:29:22.821480
6949 09:29:22.823959 RX Vref 0 -> 0, step: 1
6950 09:29:22.824493
6951 09:29:22.827349 RX Delay -359 -> 252, step: 8
6952 09:29:22.834488 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6953 09:29:22.837704 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6954 09:29:22.841099 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6955 09:29:22.844534 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6956 09:29:22.850913 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6957 09:29:22.854433 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6958 09:29:22.857298 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6959 09:29:22.860948 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6960 09:29:22.867304 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6961 09:29:22.870522 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6962 09:29:22.874525 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6963 09:29:22.877845 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6964 09:29:22.884313 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6965 09:29:22.887805 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6966 09:29:22.891294 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6967 09:29:22.898041 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6968 09:29:22.898546 ==
6969 09:29:22.901141 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 09:29:22.904412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 09:29:22.904904 ==
6972 09:29:22.905312 DQS Delay:
6973 09:29:22.907513 DQS0 = 52, DQS1 = 60
6974 09:29:22.907950 DQM Delay:
6975 09:29:22.910862 DQM0 = 12, DQM1 = 12
6976 09:29:22.911256 DQ Delay:
6977 09:29:22.914879 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6978 09:29:22.917957 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6979 09:29:22.921247 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6980 09:29:22.924973 DQ12 =16, DQ13 =20, DQ14 =20, DQ15 =20
6981 09:29:22.925453
6982 09:29:22.925780
6983 09:29:22.931247 [DQSOSCAuto] RK1, (LSB)MR18= 0x7e92, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 393 ps
6984 09:29:22.934734 CH1 RK1: MR19=C0C, MR18=7E92
6985 09:29:22.941336 CH1_RK1: MR19=0xC0C, MR18=0x7E92, DQSOSC=391, MR23=63, INC=386, DEC=257
6986 09:29:22.944863 [RxdqsGatingPostProcess] freq 400
6987 09:29:22.947760 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6988 09:29:22.951193 best DQS0 dly(2T, 0.5T) = (0, 10)
6989 09:29:22.954557 best DQS1 dly(2T, 0.5T) = (0, 10)
6990 09:29:22.957497 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6991 09:29:22.961542 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6992 09:29:22.964366 best DQS0 dly(2T, 0.5T) = (0, 10)
6993 09:29:22.967723 best DQS1 dly(2T, 0.5T) = (0, 10)
6994 09:29:22.971010 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6995 09:29:22.974691 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6996 09:29:22.978173 Pre-setting of DQS Precalculation
6997 09:29:22.981404 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6998 09:29:22.987918 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6999 09:29:22.997849 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7000 09:29:22.998416
7001 09:29:22.998861
7002 09:29:23.001933 [Calibration Summary] 800 Mbps
7003 09:29:23.002524 CH 0, Rank 0
7004 09:29:23.004600 SW Impedance : PASS
7005 09:29:23.005035 DUTY Scan : NO K
7006 09:29:23.007787 ZQ Calibration : PASS
7007 09:29:23.008221 Jitter Meter : NO K
7008 09:29:23.011419 CBT Training : PASS
7009 09:29:23.014360 Write leveling : PASS
7010 09:29:23.014791 RX DQS gating : PASS
7011 09:29:23.017775 RX DQ/DQS(RDDQC) : PASS
7012 09:29:23.021433 TX DQ/DQS : PASS
7013 09:29:23.021905 RX DATLAT : PASS
7014 09:29:23.024374 RX DQ/DQS(Engine): PASS
7015 09:29:23.028083 TX OE : NO K
7016 09:29:23.028481 All Pass.
7017 09:29:23.028801
7018 09:29:23.029086 CH 0, Rank 1
7019 09:29:23.031104 SW Impedance : PASS
7020 09:29:23.034461 DUTY Scan : NO K
7021 09:29:23.034872 ZQ Calibration : PASS
7022 09:29:23.038045 Jitter Meter : NO K
7023 09:29:23.041446 CBT Training : PASS
7024 09:29:23.041929 Write leveling : NO K
7025 09:29:23.044581 RX DQS gating : PASS
7026 09:29:23.048114 RX DQ/DQS(RDDQC) : PASS
7027 09:29:23.048508 TX DQ/DQS : PASS
7028 09:29:23.051182 RX DATLAT : PASS
7029 09:29:23.051660 RX DQ/DQS(Engine): PASS
7030 09:29:23.054458 TX OE : NO K
7031 09:29:23.054939 All Pass.
7032 09:29:23.055248
7033 09:29:23.057886 CH 1, Rank 0
7034 09:29:23.058411 SW Impedance : PASS
7035 09:29:23.061052 DUTY Scan : NO K
7036 09:29:23.064223 ZQ Calibration : PASS
7037 09:29:23.064618 Jitter Meter : NO K
7038 09:29:23.067814 CBT Training : PASS
7039 09:29:23.070737 Write leveling : PASS
7040 09:29:23.071130 RX DQS gating : PASS
7041 09:29:23.075008 RX DQ/DQS(RDDQC) : PASS
7042 09:29:23.077743 TX DQ/DQS : PASS
7043 09:29:23.078175 RX DATLAT : PASS
7044 09:29:23.081503 RX DQ/DQS(Engine): PASS
7045 09:29:23.084824 TX OE : NO K
7046 09:29:23.085332 All Pass.
7047 09:29:23.085640
7048 09:29:23.085919 CH 1, Rank 1
7049 09:29:23.088144 SW Impedance : PASS
7050 09:29:23.090668 DUTY Scan : NO K
7051 09:29:23.091065 ZQ Calibration : PASS
7052 09:29:23.094927 Jitter Meter : NO K
7053 09:29:23.097587 CBT Training : PASS
7054 09:29:23.098010 Write leveling : NO K
7055 09:29:23.101496 RX DQS gating : PASS
7056 09:29:23.101971 RX DQ/DQS(RDDQC) : PASS
7057 09:29:23.104550 TX DQ/DQS : PASS
7058 09:29:23.107351 RX DATLAT : PASS
7059 09:29:23.107749 RX DQ/DQS(Engine): PASS
7060 09:29:23.111121 TX OE : NO K
7061 09:29:23.111517 All Pass.
7062 09:29:23.111820
7063 09:29:23.114283 DramC Write-DBI off
7064 09:29:23.117318 PER_BANK_REFRESH: Hybrid Mode
7065 09:29:23.117725 TX_TRACKING: ON
7066 09:29:23.127326 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7067 09:29:23.130705 [FAST_K] Save calibration result to emmc
7068 09:29:23.134653 dramc_set_vcore_voltage set vcore to 725000
7069 09:29:23.137812 Read voltage for 1600, 0
7070 09:29:23.138237 Vio18 = 0
7071 09:29:23.138545 Vcore = 725000
7072 09:29:23.141188 Vdram = 0
7073 09:29:23.141668 Vddq = 0
7074 09:29:23.142015 Vmddr = 0
7075 09:29:23.147756 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7076 09:29:23.151448 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7077 09:29:23.154494 MEM_TYPE=3, freq_sel=13
7078 09:29:23.157521 sv_algorithm_assistance_LP4_3733
7079 09:29:23.161252 ============ PULL DRAM RESETB DOWN ============
7080 09:29:23.164714 ========== PULL DRAM RESETB DOWN end =========
7081 09:29:23.170849 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7082 09:29:23.174282 ===================================
7083 09:29:23.178038 LPDDR4 DRAM CONFIGURATION
7084 09:29:23.181361 ===================================
7085 09:29:23.181844 EX_ROW_EN[0] = 0x0
7086 09:29:23.184468 EX_ROW_EN[1] = 0x0
7087 09:29:23.184954 LP4Y_EN = 0x0
7088 09:29:23.187899 WORK_FSP = 0x1
7089 09:29:23.188296 WL = 0x5
7090 09:29:23.191044 RL = 0x5
7091 09:29:23.191437 BL = 0x2
7092 09:29:23.194618 RPST = 0x0
7093 09:29:23.195015 RD_PRE = 0x0
7094 09:29:23.197785 WR_PRE = 0x1
7095 09:29:23.198235 WR_PST = 0x1
7096 09:29:23.201411 DBI_WR = 0x0
7097 09:29:23.201893 DBI_RD = 0x0
7098 09:29:23.204593 OTF = 0x1
7099 09:29:23.207480 ===================================
7100 09:29:23.211042 ===================================
7101 09:29:23.211456 ANA top config
7102 09:29:23.214194 ===================================
7103 09:29:23.217926 DLL_ASYNC_EN = 0
7104 09:29:23.221252 ALL_SLAVE_EN = 0
7105 09:29:23.224469 NEW_RANK_MODE = 1
7106 09:29:23.224955 DLL_IDLE_MODE = 1
7107 09:29:23.227829 LP45_APHY_COMB_EN = 1
7108 09:29:23.231065 TX_ODT_DIS = 0
7109 09:29:23.234784 NEW_8X_MODE = 1
7110 09:29:23.237874 ===================================
7111 09:29:23.241265 ===================================
7112 09:29:23.244353 data_rate = 3200
7113 09:29:23.244865 CKR = 1
7114 09:29:23.247621 DQ_P2S_RATIO = 8
7115 09:29:23.251584 ===================================
7116 09:29:23.254747 CA_P2S_RATIO = 8
7117 09:29:23.257704 DQ_CA_OPEN = 0
7118 09:29:23.260959 DQ_SEMI_OPEN = 0
7119 09:29:23.261357 CA_SEMI_OPEN = 0
7120 09:29:23.264481 CA_FULL_RATE = 0
7121 09:29:23.268147 DQ_CKDIV4_EN = 0
7122 09:29:23.271230 CA_CKDIV4_EN = 0
7123 09:29:23.274707 CA_PREDIV_EN = 0
7124 09:29:23.278144 PH8_DLY = 12
7125 09:29:23.278543 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7126 09:29:23.281271 DQ_AAMCK_DIV = 4
7127 09:29:23.284672 CA_AAMCK_DIV = 4
7128 09:29:23.288185 CA_ADMCK_DIV = 4
7129 09:29:23.291236 DQ_TRACK_CA_EN = 0
7130 09:29:23.295168 CA_PICK = 1600
7131 09:29:23.297941 CA_MCKIO = 1600
7132 09:29:23.298371 MCKIO_SEMI = 0
7133 09:29:23.301377 PLL_FREQ = 3068
7134 09:29:23.304965 DQ_UI_PI_RATIO = 32
7135 09:29:23.308176 CA_UI_PI_RATIO = 0
7136 09:29:23.311241 ===================================
7137 09:29:23.314889 ===================================
7138 09:29:23.318396 memory_type:LPDDR4
7139 09:29:23.318978 GP_NUM : 10
7140 09:29:23.321492 SRAM_EN : 1
7141 09:29:23.322004 MD32_EN : 0
7142 09:29:23.325258 ===================================
7143 09:29:23.328126 [ANA_INIT] >>>>>>>>>>>>>>
7144 09:29:23.331684 <<<<<< [CONFIGURE PHASE]: ANA_TX
7145 09:29:23.334994 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7146 09:29:23.337964 ===================================
7147 09:29:23.342105 data_rate = 3200,PCW = 0X7600
7148 09:29:23.345155 ===================================
7149 09:29:23.348161 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7150 09:29:23.354967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7151 09:29:23.358294 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7152 09:29:23.364613 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7153 09:29:23.368026 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7154 09:29:23.371429 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7155 09:29:23.371914 [ANA_INIT] flow start
7156 09:29:23.374810 [ANA_INIT] PLL >>>>>>>>
7157 09:29:23.377877 [ANA_INIT] PLL <<<<<<<<
7158 09:29:23.378415 [ANA_INIT] MIDPI >>>>>>>>
7159 09:29:23.381466 [ANA_INIT] MIDPI <<<<<<<<
7160 09:29:23.385120 [ANA_INIT] DLL >>>>>>>>
7161 09:29:23.385518 [ANA_INIT] DLL <<<<<<<<
7162 09:29:23.388101 [ANA_INIT] flow end
7163 09:29:23.391446 ============ LP4 DIFF to SE enter ============
7164 09:29:23.394982 ============ LP4 DIFF to SE exit ============
7165 09:29:23.397910 [ANA_INIT] <<<<<<<<<<<<<
7166 09:29:23.402052 [Flow] Enable top DCM control >>>>>
7167 09:29:23.405256 [Flow] Enable top DCM control <<<<<
7168 09:29:23.407845 Enable DLL master slave shuffle
7169 09:29:23.414604 ==============================================================
7170 09:29:23.415012 Gating Mode config
7171 09:29:23.421915 ==============================================================
7172 09:29:23.422452 Config description:
7173 09:29:23.431240 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7174 09:29:23.438348 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7175 09:29:23.444701 SELPH_MODE 0: By rank 1: By Phase
7176 09:29:23.448272 ==============================================================
7177 09:29:23.451399 GAT_TRACK_EN = 1
7178 09:29:23.454382 RX_GATING_MODE = 2
7179 09:29:23.458283 RX_GATING_TRACK_MODE = 2
7180 09:29:23.461234 SELPH_MODE = 1
7181 09:29:23.464881 PICG_EARLY_EN = 1
7182 09:29:23.468019 VALID_LAT_VALUE = 1
7183 09:29:23.471156 ==============================================================
7184 09:29:23.474738 Enter into Gating configuration >>>>
7185 09:29:23.477736 Exit from Gating configuration <<<<
7186 09:29:23.481247 Enter into DVFS_PRE_config >>>>>
7187 09:29:23.494357 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7188 09:29:23.497756 Exit from DVFS_PRE_config <<<<<
7189 09:29:23.501264 Enter into PICG configuration >>>>
7190 09:29:23.501706 Exit from PICG configuration <<<<
7191 09:29:23.504333 [RX_INPUT] configuration >>>>>
7192 09:29:23.508016 [RX_INPUT] configuration <<<<<
7193 09:29:23.514830 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7194 09:29:23.517869 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7195 09:29:23.524488 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7196 09:29:23.531476 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7197 09:29:23.537681 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7198 09:29:23.544125 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7199 09:29:23.547254 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7200 09:29:23.551049 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7201 09:29:23.554083 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7202 09:29:23.560790 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7203 09:29:23.564446 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7204 09:29:23.567649 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7205 09:29:23.570743 ===================================
7206 09:29:23.574360 LPDDR4 DRAM CONFIGURATION
7207 09:29:23.577860 ===================================
7208 09:29:23.577936 EX_ROW_EN[0] = 0x0
7209 09:29:23.581136 EX_ROW_EN[1] = 0x0
7210 09:29:23.584422 LP4Y_EN = 0x0
7211 09:29:23.584501 WORK_FSP = 0x1
7212 09:29:23.587505 WL = 0x5
7213 09:29:23.587571 RL = 0x5
7214 09:29:23.590682 BL = 0x2
7215 09:29:23.590780 RPST = 0x0
7216 09:29:23.594644 RD_PRE = 0x0
7217 09:29:23.594723 WR_PRE = 0x1
7218 09:29:23.597725 WR_PST = 0x1
7219 09:29:23.597835 DBI_WR = 0x0
7220 09:29:23.600963 DBI_RD = 0x0
7221 09:29:23.601037 OTF = 0x1
7222 09:29:23.604213 ===================================
7223 09:29:23.607454 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7224 09:29:23.614709 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7225 09:29:23.617749 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 09:29:23.620947 ===================================
7227 09:29:23.624224 LPDDR4 DRAM CONFIGURATION
7228 09:29:23.627724 ===================================
7229 09:29:23.627793 EX_ROW_EN[0] = 0x10
7230 09:29:23.631073 EX_ROW_EN[1] = 0x0
7231 09:29:23.631174 LP4Y_EN = 0x0
7232 09:29:23.634462 WORK_FSP = 0x1
7233 09:29:23.634541 WL = 0x5
7234 09:29:23.637806 RL = 0x5
7235 09:29:23.637910 BL = 0x2
7236 09:29:23.641130 RPST = 0x0
7237 09:29:23.641205 RD_PRE = 0x0
7238 09:29:23.644201 WR_PRE = 0x1
7239 09:29:23.648204 WR_PST = 0x1
7240 09:29:23.648297 DBI_WR = 0x0
7241 09:29:23.651249 DBI_RD = 0x0
7242 09:29:23.651329 OTF = 0x1
7243 09:29:23.654251 ===================================
7244 09:29:23.660994 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7245 09:29:23.661067 ==
7246 09:29:23.664713 Dram Type= 6, Freq= 0, CH_0, rank 0
7247 09:29:23.667728 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7248 09:29:23.667795 ==
7249 09:29:23.671511 [Duty_Offset_Calibration]
7250 09:29:23.671592 B0:2 B1:-1 CA:1
7251 09:29:23.671653
7252 09:29:23.674626 [DutyScan_Calibration_Flow] k_type=0
7253 09:29:23.685100
7254 09:29:23.685191 ==CLK 0==
7255 09:29:23.688629 Final CLK duty delay cell = -4
7256 09:29:23.692026 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7257 09:29:23.695383 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7258 09:29:23.698526 [-4] AVG Duty = 4922%(X100)
7259 09:29:23.698635
7260 09:29:23.701997 CH0 CLK Duty spec in!! Max-Min= 156%
7261 09:29:23.705367 [DutyScan_Calibration_Flow] ====Done====
7262 09:29:23.705492
7263 09:29:23.708558 [DutyScan_Calibration_Flow] k_type=1
7264 09:29:23.725178
7265 09:29:23.725406 ==DQS 0 ==
7266 09:29:23.728239 Final DQS duty delay cell = 0
7267 09:29:23.731368 [0] MAX Duty = 5125%(X100), DQS PI = 56
7268 09:29:23.735182 [0] MIN Duty = 5000%(X100), DQS PI = 16
7269 09:29:23.738245 [0] AVG Duty = 5062%(X100)
7270 09:29:23.738639
7271 09:29:23.738942 ==DQS 1 ==
7272 09:29:23.741421 Final DQS duty delay cell = -4
7273 09:29:23.744997 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7274 09:29:23.748446 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7275 09:29:23.751292 [-4] AVG Duty = 5046%(X100)
7276 09:29:23.751924
7277 09:29:23.755048 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7278 09:29:23.755445
7279 09:29:23.757973 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7280 09:29:23.761799 [DutyScan_Calibration_Flow] ====Done====
7281 09:29:23.762383
7282 09:29:23.764792 [DutyScan_Calibration_Flow] k_type=3
7283 09:29:23.782198
7284 09:29:23.782834 ==DQM 0 ==
7285 09:29:23.785811 Final DQM duty delay cell = 0
7286 09:29:23.788814 [0] MAX Duty = 5000%(X100), DQS PI = 18
7287 09:29:23.792180 [0] MIN Duty = 4875%(X100), DQS PI = 4
7288 09:29:23.792791 [0] AVG Duty = 4937%(X100)
7289 09:29:23.795775
7290 09:29:23.796344 ==DQM 1 ==
7291 09:29:23.799147 Final DQM duty delay cell = 0
7292 09:29:23.802589 [0] MAX Duty = 5218%(X100), DQS PI = 58
7293 09:29:23.805783 [0] MIN Duty = 4969%(X100), DQS PI = 18
7294 09:29:23.808890 [0] AVG Duty = 5093%(X100)
7295 09:29:23.809432
7296 09:29:23.812284 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7297 09:29:23.812655
7298 09:29:23.815398 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7299 09:29:23.818970 [DutyScan_Calibration_Flow] ====Done====
7300 09:29:23.819484
7301 09:29:23.822382 [DutyScan_Calibration_Flow] k_type=2
7302 09:29:23.839382
7303 09:29:23.839838 ==DQ 0 ==
7304 09:29:23.843044 Final DQ duty delay cell = 0
7305 09:29:23.846265 [0] MAX Duty = 5156%(X100), DQS PI = 0
7306 09:29:23.849409 [0] MIN Duty = 5031%(X100), DQS PI = 6
7307 09:29:23.849792 [0] AVG Duty = 5093%(X100)
7308 09:29:23.850305
7309 09:29:23.852815 ==DQ 1 ==
7310 09:29:23.855852 Final DQ duty delay cell = 0
7311 09:29:23.859325 [0] MAX Duty = 5031%(X100), DQS PI = 14
7312 09:29:23.862953 [0] MIN Duty = 4907%(X100), DQS PI = 18
7313 09:29:23.863131 [0] AVG Duty = 4969%(X100)
7314 09:29:23.863270
7315 09:29:23.865848 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7316 09:29:23.866076
7317 09:29:23.869454 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7318 09:29:23.876293 [DutyScan_Calibration_Flow] ====Done====
7319 09:29:23.876433 ==
7320 09:29:23.879274 Dram Type= 6, Freq= 0, CH_1, rank 0
7321 09:29:23.883105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7322 09:29:23.883203 ==
7323 09:29:23.886061 [Duty_Offset_Calibration]
7324 09:29:23.886158 B0:1 B1:1 CA:2
7325 09:29:23.886238
7326 09:29:23.889156 [DutyScan_Calibration_Flow] k_type=0
7327 09:29:23.899307
7328 09:29:23.899398 ==CLK 0==
7329 09:29:23.902792 Final CLK duty delay cell = 0
7330 09:29:23.905791 [0] MAX Duty = 5187%(X100), DQS PI = 26
7331 09:29:23.909404 [0] MIN Duty = 4938%(X100), DQS PI = 50
7332 09:29:23.909493 [0] AVG Duty = 5062%(X100)
7333 09:29:23.912872
7334 09:29:23.916125 CH1 CLK Duty spec in!! Max-Min= 249%
7335 09:29:23.919439 [DutyScan_Calibration_Flow] ====Done====
7336 09:29:23.919526
7337 09:29:23.922424 [DutyScan_Calibration_Flow] k_type=1
7338 09:29:23.939568
7339 09:29:23.940129 ==DQS 0 ==
7340 09:29:23.942726 Final DQS duty delay cell = 0
7341 09:29:23.946415 [0] MAX Duty = 5031%(X100), DQS PI = 20
7342 09:29:23.949534 [0] MIN Duty = 4813%(X100), DQS PI = 52
7343 09:29:23.952513 [0] AVG Duty = 4922%(X100)
7344 09:29:23.952923
7345 09:29:23.953234 ==DQS 1 ==
7346 09:29:23.956321 Final DQS duty delay cell = 0
7347 09:29:23.959252 [0] MAX Duty = 5031%(X100), DQS PI = 34
7348 09:29:23.962670 [0] MIN Duty = 4938%(X100), DQS PI = 0
7349 09:29:23.965842 [0] AVG Duty = 4984%(X100)
7350 09:29:23.966273
7351 09:29:23.969733 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7352 09:29:23.970276
7353 09:29:23.973064 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7354 09:29:23.976416 [DutyScan_Calibration_Flow] ====Done====
7355 09:29:23.976904
7356 09:29:23.979160 [DutyScan_Calibration_Flow] k_type=3
7357 09:29:23.996507
7358 09:29:23.997002 ==DQM 0 ==
7359 09:29:23.999515 Final DQM duty delay cell = 0
7360 09:29:24.003222 [0] MAX Duty = 5156%(X100), DQS PI = 20
7361 09:29:24.006407 [0] MIN Duty = 4844%(X100), DQS PI = 50
7362 09:29:24.006812 [0] AVG Duty = 5000%(X100)
7363 09:29:24.009870
7364 09:29:24.010311 ==DQM 1 ==
7365 09:29:24.013133 Final DQM duty delay cell = 0
7366 09:29:24.016199 [0] MAX Duty = 5125%(X100), DQS PI = 8
7367 09:29:24.019736 [0] MIN Duty = 4875%(X100), DQS PI = 20
7368 09:29:24.020136 [0] AVG Duty = 5000%(X100)
7369 09:29:24.020441
7370 09:29:24.026585 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7371 09:29:24.027070
7372 09:29:24.029714 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7373 09:29:24.033247 [DutyScan_Calibration_Flow] ====Done====
7374 09:29:24.033751
7375 09:29:24.036266 [DutyScan_Calibration_Flow] k_type=2
7376 09:29:24.053212
7377 09:29:24.053628 ==DQ 0 ==
7378 09:29:24.056514 Final DQ duty delay cell = 0
7379 09:29:24.059730 [0] MAX Duty = 5125%(X100), DQS PI = 20
7380 09:29:24.063415 [0] MIN Duty = 4907%(X100), DQS PI = 52
7381 09:29:24.063811 [0] AVG Duty = 5016%(X100)
7382 09:29:24.064202
7383 09:29:24.066811 ==DQ 1 ==
7384 09:29:24.069676 Final DQ duty delay cell = 0
7385 09:29:24.073196 [0] MAX Duty = 5093%(X100), DQS PI = 6
7386 09:29:24.076734 [0] MIN Duty = 5031%(X100), DQS PI = 0
7387 09:29:24.077135 [0] AVG Duty = 5062%(X100)
7388 09:29:24.077447
7389 09:29:24.079978 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7390 09:29:24.080423
7391 09:29:24.083000 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7392 09:29:24.089785 [DutyScan_Calibration_Flow] ====Done====
7393 09:29:24.093133 nWR fixed to 30
7394 09:29:24.093524 [ModeRegInit_LP4] CH0 RK0
7395 09:29:24.096062 [ModeRegInit_LP4] CH0 RK1
7396 09:29:24.099627 [ModeRegInit_LP4] CH1 RK0
7397 09:29:24.100030 [ModeRegInit_LP4] CH1 RK1
7398 09:29:24.102924 match AC timing 5
7399 09:29:24.106526 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7400 09:29:24.109703 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7401 09:29:24.116535 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7402 09:29:24.120027 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7403 09:29:24.126820 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7404 09:29:24.127274 [MiockJmeterHQA]
7405 09:29:24.127602
7406 09:29:24.129681 [DramcMiockJmeter] u1RxGatingPI = 0
7407 09:29:24.130191 0 : 4259, 4029
7408 09:29:24.133349 4 : 4252, 4027
7409 09:29:24.133746 8 : 4252, 4027
7410 09:29:24.136703 12 : 4255, 4029
7411 09:29:24.137304 16 : 4363, 4138
7412 09:29:24.139630 20 : 4253, 4027
7413 09:29:24.140192 24 : 4252, 4027
7414 09:29:24.140732 28 : 4252, 4027
7415 09:29:24.143042 32 : 4255, 4030
7416 09:29:24.143378 36 : 4362, 4137
7417 09:29:24.146355 40 : 4360, 4137
7418 09:29:24.146567 44 : 4365, 4140
7419 09:29:24.149419 48 : 4253, 4026
7420 09:29:24.149633 52 : 4255, 4030
7421 09:29:24.153139 56 : 4252, 4027
7422 09:29:24.153311 60 : 4360, 4137
7423 09:29:24.153443 64 : 4252, 4027
7424 09:29:24.156154 68 : 4363, 4140
7425 09:29:24.156292 72 : 4250, 4026
7426 09:29:24.159161 76 : 4250, 4027
7427 09:29:24.159374 80 : 4250, 4027
7428 09:29:24.162868 84 : 4253, 4029
7429 09:29:24.163052 88 : 4360, 4137
7430 09:29:24.163225 92 : 4250, 4026
7431 09:29:24.166357 96 : 4361, 3409
7432 09:29:24.166466 100 : 4250, 0
7433 09:29:24.169691 104 : 4250, 0
7434 09:29:24.169834 108 : 4254, 0
7435 09:29:24.169957 112 : 4252, 0
7436 09:29:24.172886 116 : 4250, 0
7437 09:29:24.173013 120 : 4252, 0
7438 09:29:24.176083 124 : 4360, 0
7439 09:29:24.176206 128 : 4250, 0
7440 09:29:24.176305 132 : 4250, 0
7441 09:29:24.179262 136 : 4361, 0
7442 09:29:24.179350 140 : 4360, 0
7443 09:29:24.182721 144 : 4363, 0
7444 09:29:24.182804 148 : 4250, 0
7445 09:29:24.182866 152 : 4360, 0
7446 09:29:24.186300 156 : 4361, 0
7447 09:29:24.186379 160 : 4247, 0
7448 09:29:24.186444 164 : 4250, 0
7449 09:29:24.189613 168 : 4250, 0
7450 09:29:24.189714 172 : 4252, 0
7451 09:29:24.192715 176 : 4360, 0
7452 09:29:24.192818 180 : 4250, 0
7453 09:29:24.192905 184 : 4250, 0
7454 09:29:24.196467 188 : 4250, 0
7455 09:29:24.196544 192 : 4360, 0
7456 09:29:24.199527 196 : 4361, 0
7457 09:29:24.199605 200 : 4250, 0
7458 09:29:24.199665 204 : 4360, 0
7459 09:29:24.202542 208 : 4250, 0
7460 09:29:24.202678 212 : 4250, 98
7461 09:29:24.206527 216 : 4363, 3830
7462 09:29:24.206605 220 : 4360, 4137
7463 09:29:24.209529 224 : 4250, 4027
7464 09:29:24.209605 228 : 4361, 4137
7465 09:29:24.212877 232 : 4360, 4137
7466 09:29:24.212972 236 : 4252, 4027
7467 09:29:24.213036 240 : 4250, 4026
7468 09:29:24.216485 244 : 4253, 4029
7469 09:29:24.216564 248 : 4250, 4027
7470 09:29:24.219691 252 : 4250, 4027
7471 09:29:24.219770 256 : 4250, 4026
7472 09:29:24.223160 260 : 4253, 4029
7473 09:29:24.223251 264 : 4250, 4027
7474 09:29:24.226384 268 : 4361, 4138
7475 09:29:24.226463 272 : 4360, 4137
7476 09:29:24.229870 276 : 4250, 4027
7477 09:29:24.229997 280 : 4363, 4140
7478 09:29:24.232832 284 : 4250, 4027
7479 09:29:24.232961 288 : 4250, 4027
7480 09:29:24.233058 292 : 4250, 4027
7481 09:29:24.236507 296 : 4253, 4029
7482 09:29:24.236598 300 : 4250, 4027
7483 09:29:24.240180 304 : 4250, 4027
7484 09:29:24.240277 308 : 4250, 4026
7485 09:29:24.243374 312 : 4253, 4029
7486 09:29:24.243473 316 : 4250, 4026
7487 09:29:24.246568 320 : 4361, 4138
7488 09:29:24.246677 324 : 4360, 4137
7489 09:29:24.249616 328 : 4250, 4027
7490 09:29:24.249723 332 : 4362, 2941
7491 09:29:24.249819 336 : 4250, 70
7492 09:29:24.253042
7493 09:29:24.253140 MIOCK jitter meter ch=0
7494 09:29:24.253225
7495 09:29:24.256138 1T = (336-100) = 236 dly cells
7496 09:29:24.262834 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7497 09:29:24.262912 ==
7498 09:29:24.266878 Dram Type= 6, Freq= 0, CH_0, rank 0
7499 09:29:24.269926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7500 09:29:24.270377 ==
7501 09:29:24.276911 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7502 09:29:24.280133 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7503 09:29:24.283583 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7504 09:29:24.290205 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7505 09:29:24.299458 [CA 0] Center 44 (14~75) winsize 62
7506 09:29:24.303257 [CA 1] Center 44 (14~74) winsize 61
7507 09:29:24.306272 [CA 2] Center 39 (10~68) winsize 59
7508 09:29:24.309586 [CA 3] Center 39 (10~68) winsize 59
7509 09:29:24.312873 [CA 4] Center 37 (7~67) winsize 61
7510 09:29:24.316509 [CA 5] Center 37 (7~67) winsize 61
7511 09:29:24.317070
7512 09:29:24.319401 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7513 09:29:24.319841
7514 09:29:24.322881 [CATrainingPosCal] consider 1 rank data
7515 09:29:24.325973 u2DelayCellTimex100 = 275/100 ps
7516 09:29:24.329682 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7517 09:29:24.336394 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7518 09:29:24.339336 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7519 09:29:24.343104 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7520 09:29:24.346091 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7521 09:29:24.349517 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7522 09:29:24.350137
7523 09:29:24.352759 CA PerBit enable=1, Macro0, CA PI delay=37
7524 09:29:24.353160
7525 09:29:24.356228 [CBTSetCACLKResult] CA Dly = 37
7526 09:29:24.359531 CS Dly: 10 (0~41)
7527 09:29:24.362656 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7528 09:29:24.366228 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7529 09:29:24.366649 ==
7530 09:29:24.369223 Dram Type= 6, Freq= 0, CH_0, rank 1
7531 09:29:24.372503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 09:29:24.376023 ==
7533 09:29:24.378992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7534 09:29:24.382571 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7535 09:29:24.389394 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7536 09:29:24.393030 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7537 09:29:24.403333 [CA 0] Center 44 (14~75) winsize 62
7538 09:29:24.406437 [CA 1] Center 44 (14~75) winsize 62
7539 09:29:24.409803 [CA 2] Center 40 (11~70) winsize 60
7540 09:29:24.413031 [CA 3] Center 39 (10~69) winsize 60
7541 09:29:24.416528 [CA 4] Center 38 (8~68) winsize 61
7542 09:29:24.420208 [CA 5] Center 37 (7~67) winsize 61
7543 09:29:24.420613
7544 09:29:24.423711 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7545 09:29:24.424198
7546 09:29:24.426414 [CATrainingPosCal] consider 2 rank data
7547 09:29:24.430444 u2DelayCellTimex100 = 275/100 ps
7548 09:29:24.433124 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7549 09:29:24.439685 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7550 09:29:24.443816 CA2 delay=39 (11~68),Diff = 2 PI (7 cell)
7551 09:29:24.446602 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7552 09:29:24.450665 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7553 09:29:24.453248 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7554 09:29:24.453675
7555 09:29:24.456750 CA PerBit enable=1, Macro0, CA PI delay=37
7556 09:29:24.457138
7557 09:29:24.460166 [CBTSetCACLKResult] CA Dly = 37
7558 09:29:24.463862 CS Dly: 11 (0~44)
7559 09:29:24.466475 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7560 09:29:24.469885 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7561 09:29:24.470426
7562 09:29:24.473912 ----->DramcWriteLeveling(PI) begin...
7563 09:29:24.474432 ==
7564 09:29:24.476658 Dram Type= 6, Freq= 0, CH_0, rank 0
7565 09:29:24.483229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7566 09:29:24.483622 ==
7567 09:29:24.486306 Write leveling (Byte 0): 30 => 30
7568 09:29:24.486697 Write leveling (Byte 1): 27 => 27
7569 09:29:24.489514 DramcWriteLeveling(PI) end<-----
7570 09:29:24.489904
7571 09:29:24.490295 ==
7572 09:29:24.493135 Dram Type= 6, Freq= 0, CH_0, rank 0
7573 09:29:24.500211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7574 09:29:24.500702 ==
7575 09:29:24.503307 [Gating] SW mode calibration
7576 09:29:24.509485 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7577 09:29:24.513124 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7578 09:29:24.519709 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 09:29:24.523335 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 09:29:24.526526 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 09:29:24.532939 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 09:29:24.536482 1 4 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7583 09:29:24.539618 1 4 20 | B1->B0 | 2323 3232 | 1 0 | (1 1) (0 0)
7584 09:29:24.546311 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7585 09:29:24.549551 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 09:29:24.553493 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 09:29:24.556764 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 09:29:24.563331 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 09:29:24.566613 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7590 09:29:24.569532 1 5 16 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7591 09:29:24.576622 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
7592 09:29:24.579941 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7593 09:29:24.583253 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 09:29:24.589936 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 09:29:24.592950 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 09:29:24.596453 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 09:29:24.603091 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 09:29:24.606324 1 6 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7599 09:29:24.609187 1 6 20 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7600 09:29:24.616118 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7601 09:29:24.619474 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 09:29:24.622884 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 09:29:24.629523 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 09:29:24.632879 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 09:29:24.636375 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 09:29:24.639652 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7607 09:29:24.646493 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7608 09:29:24.649724 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7609 09:29:24.653343 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 09:29:24.659689 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 09:29:24.663553 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 09:29:24.666405 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 09:29:24.673074 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 09:29:24.676816 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 09:29:24.679927 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 09:29:24.686881 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 09:29:24.690183 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 09:29:24.694074 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 09:29:24.700150 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 09:29:24.703261 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 09:29:24.706783 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 09:29:24.713138 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 09:29:24.716780 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7624 09:29:24.719856 Total UI for P1: 0, mck2ui 16
7625 09:29:24.723928 best dqsien dly found for B0: ( 1, 9, 18)
7626 09:29:24.726565 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 09:29:24.730253 Total UI for P1: 0, mck2ui 16
7628 09:29:24.733638 best dqsien dly found for B1: ( 1, 9, 20)
7629 09:29:24.736913 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7630 09:29:24.740765 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7631 09:29:24.741248
7632 09:29:24.743847 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7633 09:29:24.746470 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7634 09:29:24.750046 [Gating] SW calibration Done
7635 09:29:24.750440 ==
7636 09:29:24.753468 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 09:29:24.760213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 09:29:24.760609 ==
7639 09:29:24.760936 RX Vref Scan: 0
7640 09:29:24.761219
7641 09:29:24.764148 RX Vref 0 -> 0, step: 1
7642 09:29:24.764629
7643 09:29:24.766908 RX Delay 0 -> 252, step: 8
7644 09:29:24.770625 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7645 09:29:24.773551 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7646 09:29:24.777411 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7647 09:29:24.780133 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7648 09:29:24.784229 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7649 09:29:24.790639 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7650 09:29:24.793960 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7651 09:29:24.796738 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7652 09:29:24.799903 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7653 09:29:24.804022 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7654 09:29:24.810028 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7655 09:29:24.813816 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7656 09:29:24.816743 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7657 09:29:24.820520 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7658 09:29:24.823906 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7659 09:29:24.830517 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7660 09:29:24.830915 ==
7661 09:29:24.834163 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 09:29:24.837143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 09:29:24.837537 ==
7664 09:29:24.837840 DQS Delay:
7665 09:29:24.840771 DQS0 = 0, DQS1 = 0
7666 09:29:24.841389 DQM Delay:
7667 09:29:24.844121 DQM0 = 132, DQM1 = 124
7668 09:29:24.844598 DQ Delay:
7669 09:29:24.847454 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7670 09:29:24.850554 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7671 09:29:24.853693 DQ8 =111, DQ9 =115, DQ10 =119, DQ11 =119
7672 09:29:24.857126 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7673 09:29:24.857532
7674 09:29:24.857830
7675 09:29:24.860906 ==
7676 09:29:24.863906 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 09:29:24.867082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 09:29:24.867496 ==
7679 09:29:24.867804
7680 09:29:24.868087
7681 09:29:24.870405 TX Vref Scan disable
7682 09:29:24.870747 == TX Byte 0 ==
7683 09:29:24.874200 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7684 09:29:24.880634 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7685 09:29:24.881035 == TX Byte 1 ==
7686 09:29:24.884224 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7687 09:29:24.890906 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7688 09:29:24.891364 ==
7689 09:29:24.894141 Dram Type= 6, Freq= 0, CH_0, rank 0
7690 09:29:24.897086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7691 09:29:24.897556 ==
7692 09:29:24.911918
7693 09:29:24.914906 TX Vref early break, caculate TX vref
7694 09:29:24.918322 TX Vref=16, minBit 1, minWin=21, winSum=355
7695 09:29:24.921341 TX Vref=18, minBit 1, minWin=22, winSum=370
7696 09:29:24.925142 TX Vref=20, minBit 1, minWin=23, winSum=379
7697 09:29:24.928215 TX Vref=22, minBit 8, minWin=23, winSum=393
7698 09:29:24.931926 TX Vref=24, minBit 1, minWin=24, winSum=404
7699 09:29:24.938323 TX Vref=26, minBit 0, minWin=25, winSum=410
7700 09:29:24.941356 TX Vref=28, minBit 0, minWin=25, winSum=415
7701 09:29:24.945087 TX Vref=30, minBit 0, minWin=25, winSum=418
7702 09:29:24.948465 TX Vref=32, minBit 0, minWin=25, winSum=410
7703 09:29:24.951912 TX Vref=34, minBit 2, minWin=24, winSum=397
7704 09:29:24.955453 TX Vref=36, minBit 0, minWin=23, winSum=392
7705 09:29:24.961481 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 30
7706 09:29:24.962174
7707 09:29:24.964606 Final TX Range 0 Vref 30
7708 09:29:24.965026
7709 09:29:24.965329 ==
7710 09:29:24.968337 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 09:29:24.972019 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 09:29:24.972412 ==
7713 09:29:24.972768
7714 09:29:24.973175
7715 09:29:24.974909 TX Vref Scan disable
7716 09:29:24.981434 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7717 09:29:24.982013 == TX Byte 0 ==
7718 09:29:24.985171 u2DelayCellOfst[0]=14 cells (4 PI)
7719 09:29:24.988058 u2DelayCellOfst[1]=21 cells (6 PI)
7720 09:29:24.991780 u2DelayCellOfst[2]=10 cells (3 PI)
7721 09:29:24.995005 u2DelayCellOfst[3]=14 cells (4 PI)
7722 09:29:24.998614 u2DelayCellOfst[4]=10 cells (3 PI)
7723 09:29:25.001746 u2DelayCellOfst[5]=0 cells (0 PI)
7724 09:29:25.005241 u2DelayCellOfst[6]=17 cells (5 PI)
7725 09:29:25.008331 u2DelayCellOfst[7]=17 cells (5 PI)
7726 09:29:25.011673 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7727 09:29:25.014743 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7728 09:29:25.018302 == TX Byte 1 ==
7729 09:29:25.018703 u2DelayCellOfst[8]=0 cells (0 PI)
7730 09:29:25.021658 u2DelayCellOfst[9]=0 cells (0 PI)
7731 09:29:25.025307 u2DelayCellOfst[10]=7 cells (2 PI)
7732 09:29:25.028344 u2DelayCellOfst[11]=0 cells (0 PI)
7733 09:29:25.031495 u2DelayCellOfst[12]=10 cells (3 PI)
7734 09:29:25.035109 u2DelayCellOfst[13]=10 cells (3 PI)
7735 09:29:25.038289 u2DelayCellOfst[14]=17 cells (5 PI)
7736 09:29:25.041647 u2DelayCellOfst[15]=10 cells (3 PI)
7737 09:29:25.044848 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7738 09:29:25.051838 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7739 09:29:25.052229 DramC Write-DBI on
7740 09:29:25.052534 ==
7741 09:29:25.054997 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 09:29:25.058024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 09:29:25.061594 ==
7744 09:29:25.062017
7745 09:29:25.062346
7746 09:29:25.062633 TX Vref Scan disable
7747 09:29:25.065313 == TX Byte 0 ==
7748 09:29:25.068097 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7749 09:29:25.071486 == TX Byte 1 ==
7750 09:29:25.075370 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7751 09:29:25.078507 DramC Write-DBI off
7752 09:29:25.078896
7753 09:29:25.079197 [DATLAT]
7754 09:29:25.079574 Freq=1600, CH0 RK0
7755 09:29:25.079954
7756 09:29:25.081606 DATLAT Default: 0xf
7757 09:29:25.082059 0, 0xFFFF, sum = 0
7758 09:29:25.085459 1, 0xFFFF, sum = 0
7759 09:29:25.085852 2, 0xFFFF, sum = 0
7760 09:29:25.088526 3, 0xFFFF, sum = 0
7761 09:29:25.091848 4, 0xFFFF, sum = 0
7762 09:29:25.092248 5, 0xFFFF, sum = 0
7763 09:29:25.094957 6, 0xFFFF, sum = 0
7764 09:29:25.095357 7, 0xFFFF, sum = 0
7765 09:29:25.098075 8, 0xFFFF, sum = 0
7766 09:29:25.098475 9, 0xFFFF, sum = 0
7767 09:29:25.101458 10, 0xFFFF, sum = 0
7768 09:29:25.101856 11, 0xFFFF, sum = 0
7769 09:29:25.105234 12, 0xFFFF, sum = 0
7770 09:29:25.105633 13, 0xFFFF, sum = 0
7771 09:29:25.108357 14, 0x0, sum = 1
7772 09:29:25.108756 15, 0x0, sum = 2
7773 09:29:25.111417 16, 0x0, sum = 3
7774 09:29:25.111816 17, 0x0, sum = 4
7775 09:29:25.115045 best_step = 15
7776 09:29:25.115439
7777 09:29:25.115741 ==
7778 09:29:25.118306 Dram Type= 6, Freq= 0, CH_0, rank 0
7779 09:29:25.121785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7780 09:29:25.122233 ==
7781 09:29:25.122544 RX Vref Scan: 1
7782 09:29:25.124808
7783 09:29:25.125198 Set Vref Range= 24 -> 127
7784 09:29:25.125504
7785 09:29:25.128177 RX Vref 24 -> 127, step: 1
7786 09:29:25.128569
7787 09:29:25.131789 RX Delay 11 -> 252, step: 4
7788 09:29:25.132222
7789 09:29:25.134777 Set Vref, RX VrefLevel [Byte0]: 24
7790 09:29:25.138515 [Byte1]: 24
7791 09:29:25.138907
7792 09:29:25.141443 Set Vref, RX VrefLevel [Byte0]: 25
7793 09:29:25.144944 [Byte1]: 25
7794 09:29:25.145359
7795 09:29:25.148076 Set Vref, RX VrefLevel [Byte0]: 26
7796 09:29:25.151655 [Byte1]: 26
7797 09:29:25.155433
7798 09:29:25.155825 Set Vref, RX VrefLevel [Byte0]: 27
7799 09:29:25.159112 [Byte1]: 27
7800 09:29:25.163311
7801 09:29:25.163701 Set Vref, RX VrefLevel [Byte0]: 28
7802 09:29:25.166469 [Byte1]: 28
7803 09:29:25.170790
7804 09:29:25.171183 Set Vref, RX VrefLevel [Byte0]: 29
7805 09:29:25.173944 [Byte1]: 29
7806 09:29:25.178079
7807 09:29:25.178473 Set Vref, RX VrefLevel [Byte0]: 30
7808 09:29:25.181749 [Byte1]: 30
7809 09:29:25.186229
7810 09:29:25.186620 Set Vref, RX VrefLevel [Byte0]: 31
7811 09:29:25.189345 [Byte1]: 31
7812 09:29:25.193667
7813 09:29:25.194108 Set Vref, RX VrefLevel [Byte0]: 32
7814 09:29:25.197018 [Byte1]: 32
7815 09:29:25.201375
7816 09:29:25.201768 Set Vref, RX VrefLevel [Byte0]: 33
7817 09:29:25.204356 [Byte1]: 33
7818 09:29:25.208335
7819 09:29:25.208735 Set Vref, RX VrefLevel [Byte0]: 34
7820 09:29:25.212034 [Byte1]: 34
7821 09:29:25.216003
7822 09:29:25.216397 Set Vref, RX VrefLevel [Byte0]: 35
7823 09:29:25.219589 [Byte1]: 35
7824 09:29:25.223752
7825 09:29:25.224142 Set Vref, RX VrefLevel [Byte0]: 36
7826 09:29:25.227277 [Byte1]: 36
7827 09:29:25.231467
7828 09:29:25.231854 Set Vref, RX VrefLevel [Byte0]: 37
7829 09:29:25.235141 [Byte1]: 37
7830 09:29:25.239245
7831 09:29:25.239636 Set Vref, RX VrefLevel [Byte0]: 38
7832 09:29:25.242417 [Byte1]: 38
7833 09:29:25.246754
7834 09:29:25.247143 Set Vref, RX VrefLevel [Byte0]: 39
7835 09:29:25.250290 [Byte1]: 39
7836 09:29:25.254520
7837 09:29:25.257624 Set Vref, RX VrefLevel [Byte0]: 40
7838 09:29:25.258099 [Byte1]: 40
7839 09:29:25.261918
7840 09:29:25.262348 Set Vref, RX VrefLevel [Byte0]: 41
7841 09:29:25.265612 [Byte1]: 41
7842 09:29:25.269897
7843 09:29:25.270340 Set Vref, RX VrefLevel [Byte0]: 42
7844 09:29:25.273065 [Byte1]: 42
7845 09:29:25.277947
7846 09:29:25.278368 Set Vref, RX VrefLevel [Byte0]: 43
7847 09:29:25.280429 [Byte1]: 43
7848 09:29:25.284825
7849 09:29:25.285216 Set Vref, RX VrefLevel [Byte0]: 44
7850 09:29:25.288821 [Byte1]: 44
7851 09:29:25.292649
7852 09:29:25.293045 Set Vref, RX VrefLevel [Byte0]: 45
7853 09:29:25.295625 [Byte1]: 45
7854 09:29:25.300067
7855 09:29:25.300545 Set Vref, RX VrefLevel [Byte0]: 46
7856 09:29:25.303494 [Byte1]: 46
7857 09:29:25.307688
7858 09:29:25.308098 Set Vref, RX VrefLevel [Byte0]: 47
7859 09:29:25.311380 [Byte1]: 47
7860 09:29:25.315545
7861 09:29:25.315933 Set Vref, RX VrefLevel [Byte0]: 48
7862 09:29:25.318460 [Byte1]: 48
7863 09:29:25.323332
7864 09:29:25.323835 Set Vref, RX VrefLevel [Byte0]: 49
7865 09:29:25.325965 [Byte1]: 49
7866 09:29:25.330584
7867 09:29:25.330973 Set Vref, RX VrefLevel [Byte0]: 50
7868 09:29:25.333789 [Byte1]: 50
7869 09:29:25.337969
7870 09:29:25.338399 Set Vref, RX VrefLevel [Byte0]: 51
7871 09:29:25.341237 [Byte1]: 51
7872 09:29:25.345804
7873 09:29:25.346240 Set Vref, RX VrefLevel [Byte0]: 52
7874 09:29:25.349218 [Byte1]: 52
7875 09:29:25.353581
7876 09:29:25.354032 Set Vref, RX VrefLevel [Byte0]: 53
7877 09:29:25.356948 [Byte1]: 53
7878 09:29:25.360896
7879 09:29:25.361289 Set Vref, RX VrefLevel [Byte0]: 54
7880 09:29:25.364607 [Byte1]: 54
7881 09:29:25.368814
7882 09:29:25.369225 Set Vref, RX VrefLevel [Byte0]: 55
7883 09:29:25.371938 [Byte1]: 55
7884 09:29:25.376140
7885 09:29:25.376531 Set Vref, RX VrefLevel [Byte0]: 56
7886 09:29:25.379387 [Byte1]: 56
7887 09:29:25.383726
7888 09:29:25.384119 Set Vref, RX VrefLevel [Byte0]: 57
7889 09:29:25.387375 [Byte1]: 57
7890 09:29:25.391722
7891 09:29:25.392114 Set Vref, RX VrefLevel [Byte0]: 58
7892 09:29:25.394755 [Byte1]: 58
7893 09:29:25.399324
7894 09:29:25.399718 Set Vref, RX VrefLevel [Byte0]: 59
7895 09:29:25.402367 [Byte1]: 59
7896 09:29:25.406467
7897 09:29:25.406866 Set Vref, RX VrefLevel [Byte0]: 60
7898 09:29:25.410097 [Byte1]: 60
7899 09:29:25.414311
7900 09:29:25.414702 Set Vref, RX VrefLevel [Byte0]: 61
7901 09:29:25.417360 [Byte1]: 61
7902 09:29:25.421971
7903 09:29:25.422405 Set Vref, RX VrefLevel [Byte0]: 62
7904 09:29:25.425608 [Byte1]: 62
7905 09:29:25.429931
7906 09:29:25.430467 Set Vref, RX VrefLevel [Byte0]: 63
7907 09:29:25.432671 [Byte1]: 63
7908 09:29:25.437300
7909 09:29:25.437691 Set Vref, RX VrefLevel [Byte0]: 64
7910 09:29:25.440684 [Byte1]: 64
7911 09:29:25.445129
7912 09:29:25.445609 Set Vref, RX VrefLevel [Byte0]: 65
7913 09:29:25.448489 [Byte1]: 65
7914 09:29:25.452294
7915 09:29:25.452848 Set Vref, RX VrefLevel [Byte0]: 66
7916 09:29:25.455794 [Byte1]: 66
7917 09:29:25.460178
7918 09:29:25.460594 Set Vref, RX VrefLevel [Byte0]: 67
7919 09:29:25.463231 [Byte1]: 67
7920 09:29:25.467464
7921 09:29:25.467941 Set Vref, RX VrefLevel [Byte0]: 68
7922 09:29:25.470650 [Byte1]: 68
7923 09:29:25.475296
7924 09:29:25.475779 Set Vref, RX VrefLevel [Byte0]: 69
7925 09:29:25.478636 [Byte1]: 69
7926 09:29:25.482738
7927 09:29:25.483134 Set Vref, RX VrefLevel [Byte0]: 70
7928 09:29:25.486431 [Byte1]: 70
7929 09:29:25.490694
7930 09:29:25.491089 Set Vref, RX VrefLevel [Byte0]: 71
7931 09:29:25.493906 [Byte1]: 71
7932 09:29:25.498240
7933 09:29:25.498634 Set Vref, RX VrefLevel [Byte0]: 72
7934 09:29:25.501302 [Byte1]: 72
7935 09:29:25.505566
7936 09:29:25.505971 Set Vref, RX VrefLevel [Byte0]: 73
7937 09:29:25.509205 [Byte1]: 73
7938 09:29:25.513421
7939 09:29:25.513816 Set Vref, RX VrefLevel [Byte0]: 74
7940 09:29:25.516385 [Byte1]: 74
7941 09:29:25.520751
7942 09:29:25.521148 Set Vref, RX VrefLevel [Byte0]: 75
7943 09:29:25.524434 [Byte1]: 75
7944 09:29:25.528666
7945 09:29:25.529062 Final RX Vref Byte 0 = 56 to rank0
7946 09:29:25.531991 Final RX Vref Byte 1 = 62 to rank0
7947 09:29:25.535447 Final RX Vref Byte 0 = 56 to rank1
7948 09:29:25.538469 Final RX Vref Byte 1 = 62 to rank1==
7949 09:29:25.541575 Dram Type= 6, Freq= 0, CH_0, rank 0
7950 09:29:25.548226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7951 09:29:25.548638 ==
7952 09:29:25.548945 DQS Delay:
7953 09:29:25.549232 DQS0 = 0, DQS1 = 0
7954 09:29:25.551784 DQM Delay:
7955 09:29:25.552173 DQM0 = 129, DQM1 = 122
7956 09:29:25.554850 DQ Delay:
7957 09:29:25.558332 DQ0 =128, DQ1 =132, DQ2 =122, DQ3 =126
7958 09:29:25.561732 DQ4 =132, DQ5 =120, DQ6 =136, DQ7 =136
7959 09:29:25.565259 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
7960 09:29:25.568191 DQ12 =128, DQ13 =128, DQ14 =132, DQ15 =132
7961 09:29:25.568470
7962 09:29:25.568687
7963 09:29:25.568883
7964 09:29:25.571680 [DramC_TX_OE_Calibration] TA2
7965 09:29:25.575043 Original DQ_B0 (3 6) =30, OEN = 27
7966 09:29:25.578280 Original DQ_B1 (3 6) =30, OEN = 27
7967 09:29:25.581480 24, 0x0, End_B0=24 End_B1=24
7968 09:29:25.581651 25, 0x0, End_B0=25 End_B1=25
7969 09:29:25.584784 26, 0x0, End_B0=26 End_B1=26
7970 09:29:25.588145 27, 0x0, End_B0=27 End_B1=27
7971 09:29:25.591623 28, 0x0, End_B0=28 End_B1=28
7972 09:29:25.591746 29, 0x0, End_B0=29 End_B1=29
7973 09:29:25.594774 30, 0x0, End_B0=30 End_B1=30
7974 09:29:25.598087 31, 0x4141, End_B0=30 End_B1=30
7975 09:29:25.601915 Byte0 end_step=30 best_step=27
7976 09:29:25.604913 Byte1 end_step=30 best_step=27
7977 09:29:25.608664 Byte0 TX OE(2T, 0.5T) = (3, 3)
7978 09:29:25.608831 Byte1 TX OE(2T, 0.5T) = (3, 3)
7979 09:29:25.608921
7980 09:29:25.609003
7981 09:29:25.618335 [DQSOSCAuto] RK0, (LSB)MR18= 0x1408, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7982 09:29:25.621650 CH0 RK0: MR19=303, MR18=1408
7983 09:29:25.628407 CH0_RK0: MR19=0x303, MR18=0x1408, DQSOSC=399, MR23=63, INC=23, DEC=15
7984 09:29:25.628614
7985 09:29:25.631222 ----->DramcWriteLeveling(PI) begin...
7986 09:29:25.631414 ==
7987 09:29:25.635033 Dram Type= 6, Freq= 0, CH_0, rank 1
7988 09:29:25.638150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7989 09:29:25.638329 ==
7990 09:29:25.641683 Write leveling (Byte 0): 35 => 35
7991 09:29:25.644875 Write leveling (Byte 1): 28 => 28
7992 09:29:25.647961 DramcWriteLeveling(PI) end<-----
7993 09:29:25.648191
7994 09:29:25.648371 ==
7995 09:29:25.651441 Dram Type= 6, Freq= 0, CH_0, rank 1
7996 09:29:25.655328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7997 09:29:25.655746 ==
7998 09:29:25.658505 [Gating] SW mode calibration
7999 09:29:25.665073 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8000 09:29:25.671499 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8001 09:29:25.675102 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8002 09:29:25.678306 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 09:29:25.685080 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 09:29:25.688184 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
8005 09:29:25.691743 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8006 09:29:25.697694 1 4 20 | B1->B0 | 2828 3434 | 0 1 | (1 1) (1 1)
8007 09:29:25.701514 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8008 09:29:25.704676 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8009 09:29:25.711258 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8010 09:29:25.714863 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8011 09:29:25.717869 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
8012 09:29:25.724577 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8013 09:29:25.727640 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8014 09:29:25.731229 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
8015 09:29:25.737875 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 09:29:25.741042 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 09:29:25.744134 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8018 09:29:25.750812 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8019 09:29:25.754537 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8020 09:29:25.757621 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8021 09:29:25.764072 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8022 09:29:25.767710 1 6 20 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
8023 09:29:25.770714 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8024 09:29:25.777336 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 09:29:25.781004 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8026 09:29:25.784229 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8027 09:29:25.787908 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8028 09:29:25.794349 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8029 09:29:25.797463 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8030 09:29:25.801174 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8031 09:29:25.807538 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8032 09:29:25.811007 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 09:29:25.814577 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 09:29:25.821370 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 09:29:25.824525 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 09:29:25.828173 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 09:29:25.834576 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 09:29:25.838082 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 09:29:25.841224 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 09:29:25.847989 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 09:29:25.851014 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 09:29:25.854881 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 09:29:25.861393 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8044 09:29:25.864924 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8045 09:29:25.867917 Total UI for P1: 0, mck2ui 16
8046 09:29:25.871015 best dqsien dly found for B0: ( 1, 9, 8)
8047 09:29:25.874537 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8048 09:29:25.878157 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8049 09:29:25.884628 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 09:29:25.887728 Total UI for P1: 0, mck2ui 16
8051 09:29:25.891392 best dqsien dly found for B1: ( 1, 9, 20)
8052 09:29:25.894461 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8053 09:29:25.897521 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8054 09:29:25.897910
8055 09:29:25.901162 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8056 09:29:25.904438 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8057 09:29:25.908158 [Gating] SW calibration Done
8058 09:29:25.908733 ==
8059 09:29:25.911586 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 09:29:25.914564 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 09:29:25.914980 ==
8062 09:29:25.918191 RX Vref Scan: 0
8063 09:29:25.918600
8064 09:29:25.918900 RX Vref 0 -> 0, step: 1
8065 09:29:25.919202
8066 09:29:25.921286 RX Delay 0 -> 252, step: 8
8067 09:29:25.925038 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8068 09:29:25.931444 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8069 09:29:25.935003 iDelay=200, Bit 2, Center 127 (64 ~ 191) 128
8070 09:29:25.938057 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8071 09:29:25.941070 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8072 09:29:25.944835 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8073 09:29:25.948462 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8074 09:29:25.954913 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8075 09:29:25.958139 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8076 09:29:25.961202 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8077 09:29:25.964665 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8078 09:29:25.968443 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8079 09:29:25.974890 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8080 09:29:25.978016 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8081 09:29:25.981416 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8082 09:29:25.984406 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8083 09:29:25.984811 ==
8084 09:29:25.988395 Dram Type= 6, Freq= 0, CH_0, rank 1
8085 09:29:25.994657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8086 09:29:25.995050 ==
8087 09:29:25.995355 DQS Delay:
8088 09:29:25.998032 DQS0 = 0, DQS1 = 0
8089 09:29:25.998426 DQM Delay:
8090 09:29:25.998733 DQM0 = 130, DQM1 = 124
8091 09:29:26.001548 DQ Delay:
8092 09:29:26.004655 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8093 09:29:26.008335 DQ4 =131, DQ5 =115, DQ6 =139, DQ7 =139
8094 09:29:26.011462 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8095 09:29:26.014977 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8096 09:29:26.015369
8097 09:29:26.015672
8098 09:29:26.015969 ==
8099 09:29:26.018035 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 09:29:26.021228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 09:29:26.025012 ==
8102 09:29:26.025543
8103 09:29:26.025855
8104 09:29:26.026206 TX Vref Scan disable
8105 09:29:26.028110 == TX Byte 0 ==
8106 09:29:26.031754 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8107 09:29:26.035013 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8108 09:29:26.038042 == TX Byte 1 ==
8109 09:29:26.041637 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8110 09:29:26.044580 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8111 09:29:26.044982 ==
8112 09:29:26.048044 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 09:29:26.054830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 09:29:26.055359 ==
8115 09:29:26.068814
8116 09:29:26.071764 TX Vref early break, caculate TX vref
8117 09:29:26.075319 TX Vref=16, minBit 3, minWin=23, winSum=379
8118 09:29:26.078767 TX Vref=18, minBit 2, minWin=24, winSum=393
8119 09:29:26.082513 TX Vref=20, minBit 5, minWin=24, winSum=398
8120 09:29:26.085525 TX Vref=22, minBit 11, minWin=24, winSum=411
8121 09:29:26.089224 TX Vref=24, minBit 12, minWin=24, winSum=416
8122 09:29:26.095751 TX Vref=26, minBit 1, minWin=25, winSum=426
8123 09:29:26.099215 TX Vref=28, minBit 2, minWin=26, winSum=429
8124 09:29:26.102217 TX Vref=30, minBit 0, minWin=26, winSum=431
8125 09:29:26.105339 TX Vref=32, minBit 5, minWin=25, winSum=423
8126 09:29:26.109119 TX Vref=34, minBit 0, minWin=25, winSum=409
8127 09:29:26.112371 TX Vref=36, minBit 8, minWin=24, winSum=403
8128 09:29:26.118937 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 30
8129 09:29:26.119389
8130 09:29:26.121969 Final TX Range 0 Vref 30
8131 09:29:26.122469
8132 09:29:26.122779 ==
8133 09:29:26.125535 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 09:29:26.128803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 09:29:26.129424 ==
8136 09:29:26.129892
8137 09:29:26.130363
8138 09:29:26.131991 TX Vref Scan disable
8139 09:29:26.138893 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8140 09:29:26.139288 == TX Byte 0 ==
8141 09:29:26.141922 u2DelayCellOfst[0]=14 cells (4 PI)
8142 09:29:26.145788 u2DelayCellOfst[1]=21 cells (6 PI)
8143 09:29:26.148909 u2DelayCellOfst[2]=10 cells (3 PI)
8144 09:29:26.152331 u2DelayCellOfst[3]=14 cells (4 PI)
8145 09:29:26.155304 u2DelayCellOfst[4]=10 cells (3 PI)
8146 09:29:26.158568 u2DelayCellOfst[5]=0 cells (0 PI)
8147 09:29:26.162399 u2DelayCellOfst[6]=17 cells (5 PI)
8148 09:29:26.165376 u2DelayCellOfst[7]=21 cells (6 PI)
8149 09:29:26.168952 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8150 09:29:26.171891 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8151 09:29:26.175138 == TX Byte 1 ==
8152 09:29:26.178746 u2DelayCellOfst[8]=0 cells (0 PI)
8153 09:29:26.179255 u2DelayCellOfst[9]=0 cells (0 PI)
8154 09:29:26.181945 u2DelayCellOfst[10]=7 cells (2 PI)
8155 09:29:26.185086 u2DelayCellOfst[11]=0 cells (0 PI)
8156 09:29:26.188554 u2DelayCellOfst[12]=14 cells (4 PI)
8157 09:29:26.191918 u2DelayCellOfst[13]=10 cells (3 PI)
8158 09:29:26.194964 u2DelayCellOfst[14]=14 cells (4 PI)
8159 09:29:26.198650 u2DelayCellOfst[15]=10 cells (3 PI)
8160 09:29:26.201502 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8161 09:29:26.208708 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8162 09:29:26.208852 DramC Write-DBI on
8163 09:29:26.209014 ==
8164 09:29:26.211677 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 09:29:26.218499 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 09:29:26.218643 ==
8167 09:29:26.218753
8168 09:29:26.218854
8169 09:29:26.218950 TX Vref Scan disable
8170 09:29:26.222019 == TX Byte 0 ==
8171 09:29:26.226067 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8172 09:29:26.229044 == TX Byte 1 ==
8173 09:29:26.232360 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8174 09:29:26.235835 DramC Write-DBI off
8175 09:29:26.236230
8176 09:29:26.236555 [DATLAT]
8177 09:29:26.236850 Freq=1600, CH0 RK1
8178 09:29:26.237128
8179 09:29:26.238954 DATLAT Default: 0xf
8180 09:29:26.239367 0, 0xFFFF, sum = 0
8181 09:29:26.242133 1, 0xFFFF, sum = 0
8182 09:29:26.242536 2, 0xFFFF, sum = 0
8183 09:29:26.245908 3, 0xFFFF, sum = 0
8184 09:29:26.249052 4, 0xFFFF, sum = 0
8185 09:29:26.249452 5, 0xFFFF, sum = 0
8186 09:29:26.252853 6, 0xFFFF, sum = 0
8187 09:29:26.253281 7, 0xFFFF, sum = 0
8188 09:29:26.255893 8, 0xFFFF, sum = 0
8189 09:29:26.256323 9, 0xFFFF, sum = 0
8190 09:29:26.259423 10, 0xFFFF, sum = 0
8191 09:29:26.260012 11, 0xFFFF, sum = 0
8192 09:29:26.262581 12, 0xFFFF, sum = 0
8193 09:29:26.263001 13, 0xFFFF, sum = 0
8194 09:29:26.265688 14, 0x0, sum = 1
8195 09:29:26.266135 15, 0x0, sum = 2
8196 09:29:26.269399 16, 0x0, sum = 3
8197 09:29:26.269806 17, 0x0, sum = 4
8198 09:29:26.272535 best_step = 15
8199 09:29:26.272933
8200 09:29:26.273235 ==
8201 09:29:26.275585 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 09:29:26.279147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 09:29:26.279548 ==
8204 09:29:26.279855 RX Vref Scan: 0
8205 09:29:26.280139
8206 09:29:26.282439 RX Vref 0 -> 0, step: 1
8207 09:29:26.282836
8208 09:29:26.286052 RX Delay 11 -> 252, step: 4
8209 09:29:26.289131 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8210 09:29:26.295759 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8211 09:29:26.299307 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8212 09:29:26.302241 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8213 09:29:26.305635 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8214 09:29:26.309192 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8215 09:29:26.312511 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8216 09:29:26.319235 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8217 09:29:26.322635 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8218 09:29:26.325798 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8219 09:29:26.328875 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8220 09:29:26.332614 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8221 09:29:26.339438 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8222 09:29:26.342714 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8223 09:29:26.345713 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8224 09:29:26.349419 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8225 09:29:26.349915 ==
8226 09:29:26.352378 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 09:29:26.359574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 09:29:26.359994 ==
8229 09:29:26.360324 DQS Delay:
8230 09:29:26.362329 DQS0 = 0, DQS1 = 0
8231 09:29:26.362783 DQM Delay:
8232 09:29:26.363261 DQM0 = 126, DQM1 = 122
8233 09:29:26.366296 DQ Delay:
8234 09:29:26.369253 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8235 09:29:26.372808 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =136
8236 09:29:26.375972 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8237 09:29:26.379098 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8238 09:29:26.379525
8239 09:29:26.379992
8240 09:29:26.380437
8241 09:29:26.382836 [DramC_TX_OE_Calibration] TA2
8242 09:29:26.385873 Original DQ_B0 (3 6) =30, OEN = 27
8243 09:29:26.389108 Original DQ_B1 (3 6) =30, OEN = 27
8244 09:29:26.392669 24, 0x0, End_B0=24 End_B1=24
8245 09:29:26.393072 25, 0x0, End_B0=25 End_B1=25
8246 09:29:26.396192 26, 0x0, End_B0=26 End_B1=26
8247 09:29:26.399261 27, 0x0, End_B0=27 End_B1=27
8248 09:29:26.402433 28, 0x0, End_B0=28 End_B1=28
8249 09:29:26.402835 29, 0x0, End_B0=29 End_B1=29
8250 09:29:26.406228 30, 0x0, End_B0=30 End_B1=30
8251 09:29:26.409279 31, 0x4545, End_B0=30 End_B1=30
8252 09:29:26.412853 Byte0 end_step=30 best_step=27
8253 09:29:26.416108 Byte1 end_step=30 best_step=27
8254 09:29:26.418963 Byte0 TX OE(2T, 0.5T) = (3, 3)
8255 09:29:26.419358 Byte1 TX OE(2T, 0.5T) = (3, 3)
8256 09:29:26.422631
8257 09:29:26.423021
8258 09:29:26.429239 [DQSOSCAuto] RK1, (LSB)MR18= 0x150a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8259 09:29:26.432465 CH0 RK1: MR19=303, MR18=150A
8260 09:29:26.439144 CH0_RK1: MR19=0x303, MR18=0x150A, DQSOSC=399, MR23=63, INC=23, DEC=15
8261 09:29:26.442641 [RxdqsGatingPostProcess] freq 1600
8262 09:29:26.445721 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8263 09:29:26.449567 best DQS0 dly(2T, 0.5T) = (1, 1)
8264 09:29:26.452606 best DQS1 dly(2T, 0.5T) = (1, 1)
8265 09:29:26.456228 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8266 09:29:26.459302 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8267 09:29:26.462432 best DQS0 dly(2T, 0.5T) = (1, 1)
8268 09:29:26.465847 best DQS1 dly(2T, 0.5T) = (1, 1)
8269 09:29:26.469030 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8270 09:29:26.469109 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8271 09:29:26.472278 Pre-setting of DQS Precalculation
8272 09:29:26.479471 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8273 09:29:26.479577 ==
8274 09:29:26.482714 Dram Type= 6, Freq= 0, CH_1, rank 0
8275 09:29:26.485837 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 09:29:26.485941 ==
8277 09:29:26.492863 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8278 09:29:26.496072 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8279 09:29:26.499271 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8280 09:29:26.505999 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8281 09:29:26.515354 [CA 0] Center 42 (13~71) winsize 59
8282 09:29:26.518560 [CA 1] Center 42 (13~71) winsize 59
8283 09:29:26.521568 [CA 2] Center 37 (8~66) winsize 59
8284 09:29:26.525318 [CA 3] Center 35 (6~65) winsize 60
8285 09:29:26.528440 [CA 4] Center 37 (8~67) winsize 60
8286 09:29:26.531802 [CA 5] Center 36 (6~66) winsize 61
8287 09:29:26.531880
8288 09:29:26.535410 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8289 09:29:26.535490
8290 09:29:26.538235 [CATrainingPosCal] consider 1 rank data
8291 09:29:26.541888 u2DelayCellTimex100 = 275/100 ps
8292 09:29:26.545378 CA0 delay=42 (13~71),Diff = 7 PI (24 cell)
8293 09:29:26.551768 CA1 delay=42 (13~71),Diff = 7 PI (24 cell)
8294 09:29:26.555417 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8295 09:29:26.558818 CA3 delay=35 (6~65),Diff = 0 PI (0 cell)
8296 09:29:26.561976 CA4 delay=37 (8~67),Diff = 2 PI (7 cell)
8297 09:29:26.565633 CA5 delay=36 (6~66),Diff = 1 PI (3 cell)
8298 09:29:26.565733
8299 09:29:26.568389 CA PerBit enable=1, Macro0, CA PI delay=35
8300 09:29:26.568467
8301 09:29:26.571687 [CBTSetCACLKResult] CA Dly = 35
8302 09:29:26.571766 CS Dly: 8 (0~39)
8303 09:29:26.578326 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8304 09:29:26.581725 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8305 09:29:26.581803 ==
8306 09:29:26.585040 Dram Type= 6, Freq= 0, CH_1, rank 1
8307 09:29:26.588660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 09:29:26.588740 ==
8309 09:29:26.595043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8310 09:29:26.598766 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8311 09:29:26.601840 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8312 09:29:26.608625 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8313 09:29:26.617904 [CA 0] Center 43 (14~72) winsize 59
8314 09:29:26.621687 [CA 1] Center 43 (14~72) winsize 59
8315 09:29:26.624736 [CA 2] Center 38 (9~67) winsize 59
8316 09:29:26.628446 [CA 3] Center 37 (8~67) winsize 60
8317 09:29:26.631514 [CA 4] Center 38 (9~68) winsize 60
8318 09:29:26.635173 [CA 5] Center 37 (8~66) winsize 59
8319 09:29:26.635250
8320 09:29:26.638398 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8321 09:29:26.638475
8322 09:29:26.641814 [CATrainingPosCal] consider 2 rank data
8323 09:29:26.644907 u2DelayCellTimex100 = 275/100 ps
8324 09:29:26.648480 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8325 09:29:26.655222 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8326 09:29:26.658270 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8327 09:29:26.661382 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8328 09:29:26.665200 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8329 09:29:26.668182 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8330 09:29:26.668260
8331 09:29:26.671900 CA PerBit enable=1, Macro0, CA PI delay=36
8332 09:29:26.671978
8333 09:29:26.675023 [CBTSetCACLKResult] CA Dly = 36
8334 09:29:26.675100 CS Dly: 10 (0~44)
8335 09:29:26.681731 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8336 09:29:26.684663 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8337 09:29:26.684740
8338 09:29:26.688125 ----->DramcWriteLeveling(PI) begin...
8339 09:29:26.688228 ==
8340 09:29:26.691842 Dram Type= 6, Freq= 0, CH_1, rank 0
8341 09:29:26.695242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8342 09:29:26.695319 ==
8343 09:29:26.698268 Write leveling (Byte 0): 27 => 27
8344 09:29:26.701486 Write leveling (Byte 1): 29 => 29
8345 09:29:26.704785 DramcWriteLeveling(PI) end<-----
8346 09:29:26.704863
8347 09:29:26.704923 ==
8348 09:29:26.708512 Dram Type= 6, Freq= 0, CH_1, rank 0
8349 09:29:26.715001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 09:29:26.715081 ==
8351 09:29:26.715142 [Gating] SW mode calibration
8352 09:29:26.724836 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8353 09:29:26.728482 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8354 09:29:26.731557 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 09:29:26.738453 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 09:29:26.741481 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 09:29:26.745166 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 09:29:26.751209 1 4 16 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
8359 09:29:26.754663 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8360 09:29:26.758366 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8361 09:29:26.765039 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8362 09:29:26.768480 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8363 09:29:26.771333 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8364 09:29:26.778286 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 09:29:26.781269 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 09:29:26.784915 1 5 16 | B1->B0 | 2d2d 3333 | 0 0 | (0 1) (0 1)
8367 09:29:26.791631 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 09:29:26.794788 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 09:29:26.798388 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 09:29:26.804875 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 09:29:26.808231 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8372 09:29:26.811407 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 09:29:26.814940 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 09:29:26.821266 1 6 16 | B1->B0 | 3636 2e2e | 0 0 | (0 0) (0 0)
8375 09:29:26.824750 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 09:29:26.828257 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8377 09:29:26.834662 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8378 09:29:26.838245 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8379 09:29:26.841349 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 09:29:26.848079 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 09:29:26.851739 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8382 09:29:26.854941 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8383 09:29:26.861954 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 09:29:26.865174 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 09:29:26.868290 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 09:29:26.874665 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 09:29:26.878339 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 09:29:26.881385 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 09:29:26.888065 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 09:29:26.891837 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 09:29:26.895082 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 09:29:26.898194 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 09:29:26.904708 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 09:29:26.908469 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 09:29:26.911471 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 09:29:26.918005 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 09:29:26.921890 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8398 09:29:26.924779 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8399 09:29:26.931405 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 09:29:26.934958 Total UI for P1: 0, mck2ui 16
8401 09:29:26.938399 best dqsien dly found for B0: ( 1, 9, 14)
8402 09:29:26.938476 Total UI for P1: 0, mck2ui 16
8403 09:29:26.945064 best dqsien dly found for B1: ( 1, 9, 14)
8404 09:29:26.948097 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8405 09:29:26.951498 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8406 09:29:26.951595
8407 09:29:26.955177 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8408 09:29:26.958372 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8409 09:29:26.961503 [Gating] SW calibration Done
8410 09:29:26.961603 ==
8411 09:29:26.965198 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 09:29:26.968414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 09:29:26.968493 ==
8414 09:29:26.971584 RX Vref Scan: 0
8415 09:29:26.971685
8416 09:29:26.971776 RX Vref 0 -> 0, step: 1
8417 09:29:26.971859
8418 09:29:26.974633 RX Delay 0 -> 252, step: 8
8419 09:29:26.978315 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8420 09:29:26.985124 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8421 09:29:26.988104 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8422 09:29:26.991684 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8423 09:29:26.994780 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8424 09:29:26.998591 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8425 09:29:27.001816 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8426 09:29:27.008626 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8427 09:29:27.011863 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8428 09:29:27.015039 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8429 09:29:27.018628 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8430 09:29:27.021835 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8431 09:29:27.028652 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8432 09:29:27.031626 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8433 09:29:27.035615 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8434 09:29:27.038713 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8435 09:29:27.038821 ==
8436 09:29:27.041852 Dram Type= 6, Freq= 0, CH_1, rank 0
8437 09:29:27.048828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8438 09:29:27.048907 ==
8439 09:29:27.048973 DQS Delay:
8440 09:29:27.049030 DQS0 = 0, DQS1 = 0
8441 09:29:27.051791 DQM Delay:
8442 09:29:27.051869 DQM0 = 134, DQM1 = 126
8443 09:29:27.055460 DQ Delay:
8444 09:29:27.058719 DQ0 =139, DQ1 =131, DQ2 =119, DQ3 =135
8445 09:29:27.062005 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8446 09:29:27.065238 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8447 09:29:27.068765 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8448 09:29:27.068843
8449 09:29:27.068928
8450 09:29:27.069000 ==
8451 09:29:27.071851 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 09:29:27.075143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 09:29:27.078665 ==
8454 09:29:27.078742
8455 09:29:27.078801
8456 09:29:27.078855 TX Vref Scan disable
8457 09:29:27.081750 == TX Byte 0 ==
8458 09:29:27.084887 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8459 09:29:27.088466 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8460 09:29:27.092019 == TX Byte 1 ==
8461 09:29:27.094885 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8462 09:29:27.098449 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8463 09:29:27.098556 ==
8464 09:29:27.101672 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 09:29:27.108578 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 09:29:27.108658 ==
8467 09:29:27.119881
8468 09:29:27.123483 TX Vref early break, caculate TX vref
8469 09:29:27.126940 TX Vref=16, minBit 8, minWin=20, winSum=361
8470 09:29:27.130121 TX Vref=18, minBit 8, minWin=21, winSum=367
8471 09:29:27.133256 TX Vref=20, minBit 5, minWin=22, winSum=378
8472 09:29:27.136723 TX Vref=22, minBit 8, minWin=22, winSum=389
8473 09:29:27.139873 TX Vref=24, minBit 8, minWin=22, winSum=396
8474 09:29:27.146871 TX Vref=26, minBit 5, minWin=24, winSum=409
8475 09:29:27.149954 TX Vref=28, minBit 0, minWin=25, winSum=414
8476 09:29:27.153655 TX Vref=30, minBit 0, minWin=25, winSum=411
8477 09:29:27.156812 TX Vref=32, minBit 0, minWin=24, winSum=404
8478 09:29:27.160099 TX Vref=34, minBit 8, minWin=23, winSum=392
8479 09:29:27.166864 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
8480 09:29:27.166942
8481 09:29:27.170413 Final TX Range 0 Vref 28
8482 09:29:27.170491
8483 09:29:27.170550 ==
8484 09:29:27.173444 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 09:29:27.176982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 09:29:27.177100 ==
8487 09:29:27.177160
8488 09:29:27.177214
8489 09:29:27.179910 TX Vref Scan disable
8490 09:29:27.186947 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8491 09:29:27.187042 == TX Byte 0 ==
8492 09:29:27.190185 u2DelayCellOfst[0]=14 cells (4 PI)
8493 09:29:27.193377 u2DelayCellOfst[1]=14 cells (4 PI)
8494 09:29:27.197030 u2DelayCellOfst[2]=0 cells (0 PI)
8495 09:29:27.199993 u2DelayCellOfst[3]=7 cells (2 PI)
8496 09:29:27.203458 u2DelayCellOfst[4]=10 cells (3 PI)
8497 09:29:27.206685 u2DelayCellOfst[5]=17 cells (5 PI)
8498 09:29:27.206770 u2DelayCellOfst[6]=17 cells (5 PI)
8499 09:29:27.210302 u2DelayCellOfst[7]=7 cells (2 PI)
8500 09:29:27.216450 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8501 09:29:27.220412 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8502 09:29:27.220519 == TX Byte 1 ==
8503 09:29:27.223597 u2DelayCellOfst[8]=0 cells (0 PI)
8504 09:29:27.226637 u2DelayCellOfst[9]=3 cells (1 PI)
8505 09:29:27.230274 u2DelayCellOfst[10]=7 cells (2 PI)
8506 09:29:27.233190 u2DelayCellOfst[11]=3 cells (1 PI)
8507 09:29:27.236985 u2DelayCellOfst[12]=10 cells (3 PI)
8508 09:29:27.239971 u2DelayCellOfst[13]=14 cells (4 PI)
8509 09:29:27.243190 u2DelayCellOfst[14]=14 cells (4 PI)
8510 09:29:27.246549 u2DelayCellOfst[15]=14 cells (4 PI)
8511 09:29:27.249712 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8512 09:29:27.253385 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8513 09:29:27.256735 DramC Write-DBI on
8514 09:29:27.256830 ==
8515 09:29:27.259907 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 09:29:27.263264 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 09:29:27.263395 ==
8518 09:29:27.263531
8519 09:29:27.263587
8520 09:29:27.266365 TX Vref Scan disable
8521 09:29:27.270183 == TX Byte 0 ==
8522 09:29:27.273186 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8523 09:29:27.276361 == TX Byte 1 ==
8524 09:29:27.279961 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8525 09:29:27.280035 DramC Write-DBI off
8526 09:29:27.280095
8527 09:29:27.283190 [DATLAT]
8528 09:29:27.283258 Freq=1600, CH1 RK0
8529 09:29:27.283315
8530 09:29:27.286269 DATLAT Default: 0xf
8531 09:29:27.286334 0, 0xFFFF, sum = 0
8532 09:29:27.289445 1, 0xFFFF, sum = 0
8533 09:29:27.289515 2, 0xFFFF, sum = 0
8534 09:29:27.293123 3, 0xFFFF, sum = 0
8535 09:29:27.293212 4, 0xFFFF, sum = 0
8536 09:29:27.296549 5, 0xFFFF, sum = 0
8537 09:29:27.296623 6, 0xFFFF, sum = 0
8538 09:29:27.299987 7, 0xFFFF, sum = 0
8539 09:29:27.300056 8, 0xFFFF, sum = 0
8540 09:29:27.302925 9, 0xFFFF, sum = 0
8541 09:29:27.306435 10, 0xFFFF, sum = 0
8542 09:29:27.306539 11, 0xFFFF, sum = 0
8543 09:29:27.309562 12, 0xFFFF, sum = 0
8544 09:29:27.309630 13, 0xFFFF, sum = 0
8545 09:29:27.313064 14, 0x0, sum = 1
8546 09:29:27.313137 15, 0x0, sum = 2
8547 09:29:27.316276 16, 0x0, sum = 3
8548 09:29:27.316370 17, 0x0, sum = 4
8549 09:29:27.316455 best_step = 15
8550 09:29:27.319603
8551 09:29:27.319675 ==
8552 09:29:27.323213 Dram Type= 6, Freq= 0, CH_1, rank 0
8553 09:29:27.326370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8554 09:29:27.326440 ==
8555 09:29:27.326498 RX Vref Scan: 1
8556 09:29:27.326553
8557 09:29:27.329599 Set Vref Range= 24 -> 127
8558 09:29:27.329688
8559 09:29:27.332776 RX Vref 24 -> 127, step: 1
8560 09:29:27.332868
8561 09:29:27.336226 RX Delay 11 -> 252, step: 4
8562 09:29:27.336292
8563 09:29:27.339753 Set Vref, RX VrefLevel [Byte0]: 24
8564 09:29:27.342744 [Byte1]: 24
8565 09:29:27.342824
8566 09:29:27.346060 Set Vref, RX VrefLevel [Byte0]: 25
8567 09:29:27.349822 [Byte1]: 25
8568 09:29:27.349900
8569 09:29:27.352761 Set Vref, RX VrefLevel [Byte0]: 26
8570 09:29:27.356583 [Byte1]: 26
8571 09:29:27.359549
8572 09:29:27.359627 Set Vref, RX VrefLevel [Byte0]: 27
8573 09:29:27.363188 [Byte1]: 27
8574 09:29:27.367716
8575 09:29:27.367795 Set Vref, RX VrefLevel [Byte0]: 28
8576 09:29:27.370839 [Byte1]: 28
8577 09:29:27.375186
8578 09:29:27.375265 Set Vref, RX VrefLevel [Byte0]: 29
8579 09:29:27.378247 [Byte1]: 29
8580 09:29:27.382855
8581 09:29:27.382933 Set Vref, RX VrefLevel [Byte0]: 30
8582 09:29:27.385936 [Byte1]: 30
8583 09:29:27.390298
8584 09:29:27.390376 Set Vref, RX VrefLevel [Byte0]: 31
8585 09:29:27.393321 [Byte1]: 31
8586 09:29:27.397685
8587 09:29:27.397763 Set Vref, RX VrefLevel [Byte0]: 32
8588 09:29:27.401483 [Byte1]: 32
8589 09:29:27.405001
8590 09:29:27.408556 Set Vref, RX VrefLevel [Byte0]: 33
8591 09:29:27.411821 [Byte1]: 33
8592 09:29:27.411900
8593 09:29:27.415067 Set Vref, RX VrefLevel [Byte0]: 34
8594 09:29:27.418443 [Byte1]: 34
8595 09:29:27.418523
8596 09:29:27.421921 Set Vref, RX VrefLevel [Byte0]: 35
8597 09:29:27.425484 [Byte1]: 35
8598 09:29:27.425562
8599 09:29:27.428798 Set Vref, RX VrefLevel [Byte0]: 36
8600 09:29:27.432037 [Byte1]: 36
8601 09:29:27.435889
8602 09:29:27.435967 Set Vref, RX VrefLevel [Byte0]: 37
8603 09:29:27.438989 [Byte1]: 37
8604 09:29:27.443505
8605 09:29:27.443582 Set Vref, RX VrefLevel [Byte0]: 38
8606 09:29:27.446964 [Byte1]: 38
8607 09:29:27.451286
8608 09:29:27.451364 Set Vref, RX VrefLevel [Byte0]: 39
8609 09:29:27.454267 [Byte1]: 39
8610 09:29:27.458644
8611 09:29:27.458721 Set Vref, RX VrefLevel [Byte0]: 40
8612 09:29:27.462287 [Byte1]: 40
8613 09:29:27.466607
8614 09:29:27.466684 Set Vref, RX VrefLevel [Byte0]: 41
8615 09:29:27.469633 [Byte1]: 41
8616 09:29:27.473851
8617 09:29:27.473952 Set Vref, RX VrefLevel [Byte0]: 42
8618 09:29:27.477036 [Byte1]: 42
8619 09:29:27.481903
8620 09:29:27.482042 Set Vref, RX VrefLevel [Byte0]: 43
8621 09:29:27.484905 [Byte1]: 43
8622 09:29:27.489218
8623 09:29:27.489318 Set Vref, RX VrefLevel [Byte0]: 44
8624 09:29:27.492298 [Byte1]: 44
8625 09:29:27.496658
8626 09:29:27.496735 Set Vref, RX VrefLevel [Byte0]: 45
8627 09:29:27.500418 [Byte1]: 45
8628 09:29:27.504591
8629 09:29:27.504671 Set Vref, RX VrefLevel [Byte0]: 46
8630 09:29:27.507611 [Byte1]: 46
8631 09:29:27.511883
8632 09:29:27.511984 Set Vref, RX VrefLevel [Byte0]: 47
8633 09:29:27.515683 [Byte1]: 47
8634 09:29:27.519836
8635 09:29:27.519913 Set Vref, RX VrefLevel [Byte0]: 48
8636 09:29:27.522662 [Byte1]: 48
8637 09:29:27.527416
8638 09:29:27.527526 Set Vref, RX VrefLevel [Byte0]: 49
8639 09:29:27.530443 [Byte1]: 49
8640 09:29:27.535097
8641 09:29:27.535173 Set Vref, RX VrefLevel [Byte0]: 50
8642 09:29:27.538103 [Byte1]: 50
8643 09:29:27.542364
8644 09:29:27.542440 Set Vref, RX VrefLevel [Byte0]: 51
8645 09:29:27.545570 [Byte1]: 51
8646 09:29:27.549855
8647 09:29:27.549955 Set Vref, RX VrefLevel [Byte0]: 52
8648 09:29:27.553246 [Byte1]: 52
8649 09:29:27.557754
8650 09:29:27.557871 Set Vref, RX VrefLevel [Byte0]: 53
8651 09:29:27.560892 [Byte1]: 53
8652 09:29:27.565138
8653 09:29:27.565221 Set Vref, RX VrefLevel [Byte0]: 54
8654 09:29:27.569292 [Byte1]: 54
8655 09:29:27.573457
8656 09:29:27.573969 Set Vref, RX VrefLevel [Byte0]: 55
8657 09:29:27.576760 [Byte1]: 55
8658 09:29:27.580858
8659 09:29:27.581377 Set Vref, RX VrefLevel [Byte0]: 56
8660 09:29:27.584093 [Byte1]: 56
8661 09:29:27.588393
8662 09:29:27.588469 Set Vref, RX VrefLevel [Byte0]: 57
8663 09:29:27.591395 [Byte1]: 57
8664 09:29:27.595684
8665 09:29:27.595761 Set Vref, RX VrefLevel [Byte0]: 58
8666 09:29:27.599369 [Byte1]: 58
8667 09:29:27.603290
8668 09:29:27.603367 Set Vref, RX VrefLevel [Byte0]: 59
8669 09:29:27.606809 [Byte1]: 59
8670 09:29:27.610946
8671 09:29:27.611047 Set Vref, RX VrefLevel [Byte0]: 60
8672 09:29:27.614165 [Byte1]: 60
8673 09:29:27.618419
8674 09:29:27.618496 Set Vref, RX VrefLevel [Byte0]: 61
8675 09:29:27.622138 [Byte1]: 61
8676 09:29:27.626404
8677 09:29:27.626480 Set Vref, RX VrefLevel [Byte0]: 62
8678 09:29:27.629703 [Byte1]: 62
8679 09:29:27.633843
8680 09:29:27.633959 Set Vref, RX VrefLevel [Byte0]: 63
8681 09:29:27.640399 [Byte1]: 63
8682 09:29:27.640494
8683 09:29:27.643502 Set Vref, RX VrefLevel [Byte0]: 64
8684 09:29:27.647080 [Byte1]: 64
8685 09:29:27.647157
8686 09:29:27.650687 Set Vref, RX VrefLevel [Byte0]: 65
8687 09:29:27.653713 [Byte1]: 65
8688 09:29:27.653796
8689 09:29:27.657361 Set Vref, RX VrefLevel [Byte0]: 66
8690 09:29:27.660407 [Byte1]: 66
8691 09:29:27.664435
8692 09:29:27.664531 Set Vref, RX VrefLevel [Byte0]: 67
8693 09:29:27.667674 [Byte1]: 67
8694 09:29:27.671891
8695 09:29:27.672006 Set Vref, RX VrefLevel [Byte0]: 68
8696 09:29:27.675370 [Byte1]: 68
8697 09:29:27.679754
8698 09:29:27.679896 Set Vref, RX VrefLevel [Byte0]: 69
8699 09:29:27.682663 [Byte1]: 69
8700 09:29:27.687154
8701 09:29:27.687317 Set Vref, RX VrefLevel [Byte0]: 70
8702 09:29:27.690865 [Byte1]: 70
8703 09:29:27.695125
8704 09:29:27.695350 Set Vref, RX VrefLevel [Byte0]: 71
8705 09:29:27.698151 [Byte1]: 71
8706 09:29:27.702446
8707 09:29:27.702727 Set Vref, RX VrefLevel [Byte0]: 72
8708 09:29:27.706244 [Byte1]: 72
8709 09:29:27.710739
8710 09:29:27.711179 Set Vref, RX VrefLevel [Byte0]: 73
8711 09:29:27.713620 [Byte1]: 73
8712 09:29:27.718435
8713 09:29:27.718911 Set Vref, RX VrefLevel [Byte0]: 74
8714 09:29:27.721379 [Byte1]: 74
8715 09:29:27.725787
8716 09:29:27.726312 Set Vref, RX VrefLevel [Byte0]: 75
8717 09:29:27.728803 [Byte1]: 75
8718 09:29:27.733553
8719 09:29:27.734054 Set Vref, RX VrefLevel [Byte0]: 76
8720 09:29:27.736911 [Byte1]: 76
8721 09:29:27.741033
8722 09:29:27.741482 Final RX Vref Byte 0 = 60 to rank0
8723 09:29:27.744242 Final RX Vref Byte 1 = 55 to rank0
8724 09:29:27.747323 Final RX Vref Byte 0 = 60 to rank1
8725 09:29:27.751155 Final RX Vref Byte 1 = 55 to rank1==
8726 09:29:27.754059 Dram Type= 6, Freq= 0, CH_1, rank 0
8727 09:29:27.760938 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8728 09:29:27.761337 ==
8729 09:29:27.761724 DQS Delay:
8730 09:29:27.762063 DQS0 = 0, DQS1 = 0
8731 09:29:27.764266 DQM Delay:
8732 09:29:27.764659 DQM0 = 131, DQM1 = 124
8733 09:29:27.767530 DQ Delay:
8734 09:29:27.770989 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =128
8735 09:29:27.774215 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8736 09:29:27.777839 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8737 09:29:27.781123 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8738 09:29:27.781520
8739 09:29:27.781826
8740 09:29:27.782164
8741 09:29:27.783926 [DramC_TX_OE_Calibration] TA2
8742 09:29:27.787760 Original DQ_B0 (3 6) =30, OEN = 27
8743 09:29:27.790799 Original DQ_B1 (3 6) =30, OEN = 27
8744 09:29:27.794496 24, 0x0, End_B0=24 End_B1=24
8745 09:29:27.795072 25, 0x0, End_B0=25 End_B1=25
8746 09:29:27.797350 26, 0x0, End_B0=26 End_B1=26
8747 09:29:27.800877 27, 0x0, End_B0=27 End_B1=27
8748 09:29:27.804769 28, 0x0, End_B0=28 End_B1=28
8749 09:29:27.805262 29, 0x0, End_B0=29 End_B1=29
8750 09:29:27.807632 30, 0x0, End_B0=30 End_B1=30
8751 09:29:27.810743 31, 0x4141, End_B0=30 End_B1=30
8752 09:29:27.814232 Byte0 end_step=30 best_step=27
8753 09:29:27.817136 Byte1 end_step=30 best_step=27
8754 09:29:27.821019 Byte0 TX OE(2T, 0.5T) = (3, 3)
8755 09:29:27.821418 Byte1 TX OE(2T, 0.5T) = (3, 3)
8756 09:29:27.821728
8757 09:29:27.824174
8758 09:29:27.831288 [DQSOSCAuto] RK0, (LSB)MR18= 0x14fe, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 399 ps
8759 09:29:27.834326 CH1 RK0: MR19=302, MR18=14FE
8760 09:29:27.841035 CH1_RK0: MR19=0x302, MR18=0x14FE, DQSOSC=399, MR23=63, INC=23, DEC=15
8761 09:29:27.841719
8762 09:29:27.844003 ----->DramcWriteLeveling(PI) begin...
8763 09:29:27.844402 ==
8764 09:29:27.848070 Dram Type= 6, Freq= 0, CH_1, rank 1
8765 09:29:27.850652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8766 09:29:27.851059 ==
8767 09:29:27.854485 Write leveling (Byte 0): 26 => 26
8768 09:29:27.857502 Write leveling (Byte 1): 29 => 29
8769 09:29:27.860703 DramcWriteLeveling(PI) end<-----
8770 09:29:27.861100
8771 09:29:27.861504 ==
8772 09:29:27.864238 Dram Type= 6, Freq= 0, CH_1, rank 1
8773 09:29:27.867643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8774 09:29:27.868077 ==
8775 09:29:27.870961 [Gating] SW mode calibration
8776 09:29:27.877731 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8777 09:29:27.884333 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8778 09:29:27.888293 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 09:29:27.890701 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8780 09:29:27.897618 1 4 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
8781 09:29:27.901074 1 4 12 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
8782 09:29:27.904579 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 09:29:27.911024 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 09:29:27.914569 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 09:29:27.917567 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 09:29:27.920653 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 09:29:27.927557 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8788 09:29:27.931299 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8789 09:29:27.934476 1 5 12 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
8790 09:29:27.941381 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8791 09:29:27.944559 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 09:29:27.947258 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 09:29:27.954018 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 09:29:27.957698 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 09:29:27.960888 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8796 09:29:27.967930 1 6 8 | B1->B0 | 2929 4242 | 0 0 | (0 0) (0 0)
8797 09:29:27.970983 1 6 12 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8798 09:29:27.974038 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 09:29:27.980866 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 09:29:27.984178 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 09:29:27.987332 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 09:29:27.994112 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 09:29:27.997845 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8804 09:29:28.000714 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8805 09:29:28.007253 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8806 09:29:28.011110 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8807 09:29:28.014085 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 09:29:28.017493 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 09:29:28.023917 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 09:29:28.027668 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 09:29:28.031185 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 09:29:28.037644 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 09:29:28.041310 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 09:29:28.044930 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 09:29:28.051281 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 09:29:28.054511 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 09:29:28.057573 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 09:29:28.064430 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 09:29:28.067660 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 09:29:28.071526 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8821 09:29:28.078643 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8822 09:29:28.079162 Total UI for P1: 0, mck2ui 16
8823 09:29:28.081502 best dqsien dly found for B0: ( 1, 9, 8)
8824 09:29:28.088307 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 09:29:28.091161 Total UI for P1: 0, mck2ui 16
8826 09:29:28.094197 best dqsien dly found for B1: ( 1, 9, 12)
8827 09:29:28.098011 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8828 09:29:28.100746 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8829 09:29:28.101273
8830 09:29:28.104130 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8831 09:29:28.107347 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8832 09:29:28.111059 [Gating] SW calibration Done
8833 09:29:28.111600 ==
8834 09:29:28.114436 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 09:29:28.117485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 09:29:28.117895 ==
8837 09:29:28.121335 RX Vref Scan: 0
8838 09:29:28.121724
8839 09:29:28.124370 RX Vref 0 -> 0, step: 1
8840 09:29:28.124779
8841 09:29:28.125080 RX Delay 0 -> 252, step: 8
8842 09:29:28.131210 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8843 09:29:28.134046 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8844 09:29:28.137646 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8845 09:29:28.141271 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8846 09:29:28.144079 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8847 09:29:28.150911 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8848 09:29:28.153972 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8849 09:29:28.157873 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8850 09:29:28.161089 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8851 09:29:28.163965 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8852 09:29:28.167657 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8853 09:29:28.174032 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8854 09:29:28.177855 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8855 09:29:28.181011 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8856 09:29:28.184878 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8857 09:29:28.191365 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8858 09:29:28.191840 ==
8859 09:29:28.194613 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 09:29:28.198057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 09:29:28.198458 ==
8862 09:29:28.198764 DQS Delay:
8863 09:29:28.200839 DQS0 = 0, DQS1 = 0
8864 09:29:28.201231 DQM Delay:
8865 09:29:28.204330 DQM0 = 132, DQM1 = 127
8866 09:29:28.204723 DQ Delay:
8867 09:29:28.207634 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8868 09:29:28.210729 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8869 09:29:28.214507 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8870 09:29:28.217765 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8871 09:29:28.218206
8872 09:29:28.218512
8873 09:29:28.220657 ==
8874 09:29:28.221050 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 09:29:28.228015 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 09:29:28.228497 ==
8877 09:29:28.228809
8878 09:29:28.229087
8879 09:29:28.229354 TX Vref Scan disable
8880 09:29:28.231570 == TX Byte 0 ==
8881 09:29:28.234801 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8882 09:29:28.237959 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8883 09:29:28.241501 == TX Byte 1 ==
8884 09:29:28.245149 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8885 09:29:28.251929 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8886 09:29:28.252405 ==
8887 09:29:28.254519 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 09:29:28.258295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 09:29:28.258688 ==
8890 09:29:28.271755
8891 09:29:28.274729 TX Vref early break, caculate TX vref
8892 09:29:28.277676 TX Vref=16, minBit 8, minWin=21, winSum=373
8893 09:29:28.281661 TX Vref=18, minBit 8, minWin=22, winSum=381
8894 09:29:28.284948 TX Vref=20, minBit 8, minWin=23, winSum=393
8895 09:29:28.288191 TX Vref=22, minBit 1, minWin=24, winSum=396
8896 09:29:28.291254 TX Vref=24, minBit 6, minWin=25, winSum=410
8897 09:29:28.298184 TX Vref=26, minBit 0, minWin=25, winSum=414
8898 09:29:28.301048 TX Vref=28, minBit 0, minWin=25, winSum=419
8899 09:29:28.304864 TX Vref=30, minBit 0, minWin=25, winSum=415
8900 09:29:28.307883 TX Vref=32, minBit 0, minWin=25, winSum=412
8901 09:29:28.311324 TX Vref=34, minBit 8, minWin=24, winSum=400
8902 09:29:28.314568 TX Vref=36, minBit 5, minWin=23, winSum=395
8903 09:29:28.321421 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
8904 09:29:28.321819
8905 09:29:28.325060 Final TX Range 0 Vref 28
8906 09:29:28.325453
8907 09:29:28.325757 ==
8908 09:29:28.328226 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 09:29:28.331765 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 09:29:28.332162 ==
8911 09:29:28.332470
8912 09:29:28.332754
8913 09:29:28.334484 TX Vref Scan disable
8914 09:29:28.341779 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8915 09:29:28.342449 == TX Byte 0 ==
8916 09:29:28.344732 u2DelayCellOfst[0]=17 cells (5 PI)
8917 09:29:28.348068 u2DelayCellOfst[1]=10 cells (3 PI)
8918 09:29:28.352054 u2DelayCellOfst[2]=0 cells (0 PI)
8919 09:29:28.354867 u2DelayCellOfst[3]=7 cells (2 PI)
8920 09:29:28.358324 u2DelayCellOfst[4]=10 cells (3 PI)
8921 09:29:28.361814 u2DelayCellOfst[5]=17 cells (5 PI)
8922 09:29:28.364828 u2DelayCellOfst[6]=17 cells (5 PI)
8923 09:29:28.367808 u2DelayCellOfst[7]=7 cells (2 PI)
8924 09:29:28.371995 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8925 09:29:28.374692 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8926 09:29:28.378427 == TX Byte 1 ==
8927 09:29:28.378906 u2DelayCellOfst[8]=0 cells (0 PI)
8928 09:29:28.381502 u2DelayCellOfst[9]=7 cells (2 PI)
8929 09:29:28.384960 u2DelayCellOfst[10]=10 cells (3 PI)
8930 09:29:28.388070 u2DelayCellOfst[11]=7 cells (2 PI)
8931 09:29:28.391268 u2DelayCellOfst[12]=14 cells (4 PI)
8932 09:29:28.394955 u2DelayCellOfst[13]=17 cells (5 PI)
8933 09:29:28.398329 u2DelayCellOfst[14]=17 cells (5 PI)
8934 09:29:28.401221 u2DelayCellOfst[15]=17 cells (5 PI)
8935 09:29:28.404888 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8936 09:29:28.408128 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8937 09:29:28.411808 DramC Write-DBI on
8938 09:29:28.412209 ==
8939 09:29:28.414921 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 09:29:28.418087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 09:29:28.418523 ==
8942 09:29:28.418838
8943 09:29:28.421579
8944 09:29:28.422106 TX Vref Scan disable
8945 09:29:28.424796 == TX Byte 0 ==
8946 09:29:28.428646 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8947 09:29:28.431831 == TX Byte 1 ==
8948 09:29:28.435085 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8949 09:29:28.435479 DramC Write-DBI off
8950 09:29:28.435783
8951 09:29:28.438096 [DATLAT]
8952 09:29:28.438502 Freq=1600, CH1 RK1
8953 09:29:28.438962
8954 09:29:28.441950 DATLAT Default: 0xf
8955 09:29:28.442514 0, 0xFFFF, sum = 0
8956 09:29:28.445322 1, 0xFFFF, sum = 0
8957 09:29:28.445799 2, 0xFFFF, sum = 0
8958 09:29:28.448063 3, 0xFFFF, sum = 0
8959 09:29:28.448461 4, 0xFFFF, sum = 0
8960 09:29:28.451492 5, 0xFFFF, sum = 0
8961 09:29:28.451969 6, 0xFFFF, sum = 0
8962 09:29:28.454710 7, 0xFFFF, sum = 0
8963 09:29:28.455107 8, 0xFFFF, sum = 0
8964 09:29:28.458523 9, 0xFFFF, sum = 0
8965 09:29:28.461764 10, 0xFFFF, sum = 0
8966 09:29:28.462217 11, 0xFFFF, sum = 0
8967 09:29:28.465537 12, 0xFFFF, sum = 0
8968 09:29:28.465935 13, 0xFFFF, sum = 0
8969 09:29:28.468225 14, 0x0, sum = 1
8970 09:29:28.468624 15, 0x0, sum = 2
8971 09:29:28.472290 16, 0x0, sum = 3
8972 09:29:28.472768 17, 0x0, sum = 4
8973 09:29:28.473084 best_step = 15
8974 09:29:28.475139
8975 09:29:28.475531 ==
8976 09:29:28.478332 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 09:29:28.481809 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 09:29:28.482396 ==
8979 09:29:28.482886 RX Vref Scan: 0
8980 09:29:28.483365
8981 09:29:28.484888 RX Vref 0 -> 0, step: 1
8982 09:29:28.485224
8983 09:29:28.488241 RX Delay 11 -> 252, step: 4
8984 09:29:28.491946 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8985 09:29:28.494990 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8986 09:29:28.501692 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8987 09:29:28.505160 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8988 09:29:28.508229 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8989 09:29:28.511723 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8990 09:29:28.514824 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8991 09:29:28.521504 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
8992 09:29:28.525209 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8993 09:29:28.528438 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8994 09:29:28.531799 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8995 09:29:28.535135 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8996 09:29:28.541787 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8997 09:29:28.544838 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
8998 09:29:28.548698 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8999 09:29:28.551782 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
9000 09:29:28.552182 ==
9001 09:29:28.554672 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 09:29:28.562303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 09:29:28.562783 ==
9004 09:29:28.563104 DQS Delay:
9005 09:29:28.563393 DQS0 = 0, DQS1 = 0
9006 09:29:28.564926 DQM Delay:
9007 09:29:28.565317 DQM0 = 129, DQM1 = 126
9008 09:29:28.568334 DQ Delay:
9009 09:29:28.572167 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9010 09:29:28.574941 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9011 09:29:28.578410 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9012 09:29:28.581574 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9013 09:29:28.581965
9014 09:29:28.582302
9015 09:29:28.582583
9016 09:29:28.585189 [DramC_TX_OE_Calibration] TA2
9017 09:29:28.588481 Original DQ_B0 (3 6) =30, OEN = 27
9018 09:29:28.591840 Original DQ_B1 (3 6) =30, OEN = 27
9019 09:29:28.595257 24, 0x0, End_B0=24 End_B1=24
9020 09:29:28.595669 25, 0x0, End_B0=25 End_B1=25
9021 09:29:28.598390 26, 0x0, End_B0=26 End_B1=26
9022 09:29:28.601697 27, 0x0, End_B0=27 End_B1=27
9023 09:29:28.605248 28, 0x0, End_B0=28 End_B1=28
9024 09:29:28.605647 29, 0x0, End_B0=29 End_B1=29
9025 09:29:28.608475 30, 0x0, End_B0=30 End_B1=30
9026 09:29:28.611790 31, 0x4141, End_B0=30 End_B1=30
9027 09:29:28.614837 Byte0 end_step=30 best_step=27
9028 09:29:28.618080 Byte1 end_step=30 best_step=27
9029 09:29:28.621801 Byte0 TX OE(2T, 0.5T) = (3, 3)
9030 09:29:28.622278 Byte1 TX OE(2T, 0.5T) = (3, 3)
9031 09:29:28.622590
9032 09:29:28.622918
9033 09:29:28.631657 [DQSOSCAuto] RK1, (LSB)MR18= 0x1218, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
9034 09:29:28.635297 CH1 RK1: MR19=303, MR18=1218
9035 09:29:28.641722 CH1_RK1: MR19=0x303, MR18=0x1218, DQSOSC=397, MR23=63, INC=23, DEC=15
9036 09:29:28.642294 [RxdqsGatingPostProcess] freq 1600
9037 09:29:28.648372 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9038 09:29:28.651658 best DQS0 dly(2T, 0.5T) = (1, 1)
9039 09:29:28.655436 best DQS1 dly(2T, 0.5T) = (1, 1)
9040 09:29:28.658496 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9041 09:29:28.661618 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9042 09:29:28.665167 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 09:29:28.668539 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 09:29:28.668930 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 09:29:28.671984 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 09:29:28.675142 Pre-setting of DQS Precalculation
9047 09:29:28.681538 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9048 09:29:28.688702 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9049 09:29:28.695451 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9050 09:29:28.695847
9051 09:29:28.696151
9052 09:29:28.698679 [Calibration Summary] 3200 Mbps
9053 09:29:28.699100 CH 0, Rank 0
9054 09:29:28.701857 SW Impedance : PASS
9055 09:29:28.705202 DUTY Scan : NO K
9056 09:29:28.705590 ZQ Calibration : PASS
9057 09:29:28.708664 Jitter Meter : NO K
9058 09:29:28.711936 CBT Training : PASS
9059 09:29:28.712334 Write leveling : PASS
9060 09:29:28.715018 RX DQS gating : PASS
9061 09:29:28.718508 RX DQ/DQS(RDDQC) : PASS
9062 09:29:28.718922 TX DQ/DQS : PASS
9063 09:29:28.721597 RX DATLAT : PASS
9064 09:29:28.725329 RX DQ/DQS(Engine): PASS
9065 09:29:28.725879 TX OE : PASS
9066 09:29:28.729022 All Pass.
9067 09:29:28.729550
9068 09:29:28.730055 CH 0, Rank 1
9069 09:29:28.731946 SW Impedance : PASS
9070 09:29:28.732336 DUTY Scan : NO K
9071 09:29:28.735442 ZQ Calibration : PASS
9072 09:29:28.738119 Jitter Meter : NO K
9073 09:29:28.738517 CBT Training : PASS
9074 09:29:28.742335 Write leveling : PASS
9075 09:29:28.742884 RX DQS gating : PASS
9076 09:29:28.745160 RX DQ/DQS(RDDQC) : PASS
9077 09:29:28.748679 TX DQ/DQS : PASS
9078 09:29:28.749164 RX DATLAT : PASS
9079 09:29:28.752272 RX DQ/DQS(Engine): PASS
9080 09:29:28.755357 TX OE : PASS
9081 09:29:28.755748 All Pass.
9082 09:29:28.756052
9083 09:29:28.756376 CH 1, Rank 0
9084 09:29:28.758557 SW Impedance : PASS
9085 09:29:28.761749 DUTY Scan : NO K
9086 09:29:28.762176 ZQ Calibration : PASS
9087 09:29:28.765333 Jitter Meter : NO K
9088 09:29:28.768325 CBT Training : PASS
9089 09:29:28.768715 Write leveling : PASS
9090 09:29:28.771794 RX DQS gating : PASS
9091 09:29:28.775387 RX DQ/DQS(RDDQC) : PASS
9092 09:29:28.775922 TX DQ/DQS : PASS
9093 09:29:28.778674 RX DATLAT : PASS
9094 09:29:28.779199 RX DQ/DQS(Engine): PASS
9095 09:29:28.781462 TX OE : PASS
9096 09:29:28.781879 All Pass.
9097 09:29:28.782233
9098 09:29:28.785249 CH 1, Rank 1
9099 09:29:28.785640 SW Impedance : PASS
9100 09:29:28.788751 DUTY Scan : NO K
9101 09:29:28.791608 ZQ Calibration : PASS
9102 09:29:28.792061 Jitter Meter : NO K
9103 09:29:28.795209 CBT Training : PASS
9104 09:29:28.798362 Write leveling : PASS
9105 09:29:28.798904 RX DQS gating : PASS
9106 09:29:28.801628 RX DQ/DQS(RDDQC) : PASS
9107 09:29:28.805343 TX DQ/DQS : PASS
9108 09:29:28.805860 RX DATLAT : PASS
9109 09:29:28.808305 RX DQ/DQS(Engine): PASS
9110 09:29:28.812069 TX OE : PASS
9111 09:29:28.812532 All Pass.
9112 09:29:28.812948
9113 09:29:28.813351 DramC Write-DBI on
9114 09:29:28.815336 PER_BANK_REFRESH: Hybrid Mode
9115 09:29:28.818253 TX_TRACKING: ON
9116 09:29:28.825265 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9117 09:29:28.835589 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9118 09:29:28.841802 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9119 09:29:28.845003 [FAST_K] Save calibration result to emmc
9120 09:29:28.848720 sync common calibartion params.
9121 09:29:28.849113 sync cbt_mode0:1, 1:1
9122 09:29:28.852436 dram_init: ddr_geometry: 2
9123 09:29:28.855514 dram_init: ddr_geometry: 2
9124 09:29:28.858686 dram_init: ddr_geometry: 2
9125 09:29:28.859077 0:dram_rank_size:100000000
9126 09:29:28.862088 1:dram_rank_size:100000000
9127 09:29:28.868765 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9128 09:29:28.869229 DFS_SHUFFLE_HW_MODE: ON
9129 09:29:28.875209 dramc_set_vcore_voltage set vcore to 725000
9130 09:29:28.875646 Read voltage for 1600, 0
9131 09:29:28.878509 Vio18 = 0
9132 09:29:28.878942 Vcore = 725000
9133 09:29:28.879311 Vdram = 0
9134 09:29:28.882165 Vddq = 0
9135 09:29:28.882558 Vmddr = 0
9136 09:29:28.885626 switch to 3200 Mbps bootup
9137 09:29:28.886250 [DramcRunTimeConfig]
9138 09:29:28.886575 PHYPLL
9139 09:29:28.888442 DPM_CONTROL_AFTERK: ON
9140 09:29:28.888833 PER_BANK_REFRESH: ON
9141 09:29:28.891885 REFRESH_OVERHEAD_REDUCTION: ON
9142 09:29:28.895030 CMD_PICG_NEW_MODE: OFF
9143 09:29:28.895424 XRTWTW_NEW_MODE: ON
9144 09:29:28.898480 XRTRTR_NEW_MODE: ON
9145 09:29:28.898889 TX_TRACKING: ON
9146 09:29:28.901964 RDSEL_TRACKING: OFF
9147 09:29:28.905031 DQS Precalculation for DVFS: ON
9148 09:29:28.905424 RX_TRACKING: OFF
9149 09:29:28.908850 HW_GATING DBG: ON
9150 09:29:28.909406 ZQCS_ENABLE_LP4: ON
9151 09:29:28.911641 RX_PICG_NEW_MODE: ON
9152 09:29:28.915524 TX_PICG_NEW_MODE: ON
9153 09:29:28.915919 ENABLE_RX_DCM_DPHY: ON
9154 09:29:28.918399 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9155 09:29:28.922365 DUMMY_READ_FOR_TRACKING: OFF
9156 09:29:28.925538 !!! SPM_CONTROL_AFTERK: OFF
9157 09:29:28.926095 !!! SPM could not control APHY
9158 09:29:28.928646 IMPEDANCE_TRACKING: ON
9159 09:29:28.929055 TEMP_SENSOR: ON
9160 09:29:28.931719 HW_SAVE_FOR_SR: OFF
9161 09:29:28.935360 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9162 09:29:28.938431 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9163 09:29:28.942414 Read ODT Tracking: ON
9164 09:29:28.942949 Refresh Rate DeBounce: ON
9165 09:29:28.945465 DFS_NO_QUEUE_FLUSH: ON
9166 09:29:28.948368 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9167 09:29:28.952506 ENABLE_DFS_RUNTIME_MRW: OFF
9168 09:29:28.952981 DDR_RESERVE_NEW_MODE: ON
9169 09:29:28.955537 MR_CBT_SWITCH_FREQ: ON
9170 09:29:28.958385 =========================
9171 09:29:28.976403 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9172 09:29:28.979133 dram_init: ddr_geometry: 2
9173 09:29:28.997397 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9174 09:29:29.001186 dram_init: dram init end (result: 0)
9175 09:29:29.007565 DRAM-K: Full calibration passed in 24592 msecs
9176 09:29:29.010653 MRC: failed to locate region type 0.
9177 09:29:29.011270 DRAM rank0 size:0x100000000,
9178 09:29:29.014115 DRAM rank1 size=0x100000000
9179 09:29:29.024076 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9180 09:29:29.030797 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9181 09:29:29.037726 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9182 09:29:29.043706 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9183 09:29:29.047389 DRAM rank0 size:0x100000000,
9184 09:29:29.050508 DRAM rank1 size=0x100000000
9185 09:29:29.050902 CBMEM:
9186 09:29:29.054399 IMD: root @ 0xfffff000 254 entries.
9187 09:29:29.057561 IMD: root @ 0xffffec00 62 entries.
9188 09:29:29.060791 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9189 09:29:29.064555 WARNING: RO_VPD is uninitialized or empty.
9190 09:29:29.070600 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9191 09:29:29.077789 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9192 09:29:29.090356 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9193 09:29:29.101802 BS: romstage times (exec / console): total (unknown) / 24092 ms
9194 09:29:29.102415
9195 09:29:29.102731
9196 09:29:29.111850 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9197 09:29:29.115532 ARM64: Exception handlers installed.
9198 09:29:29.118287 ARM64: Testing exception
9199 09:29:29.122089 ARM64: Done test exception
9200 09:29:29.122479 Enumerating buses...
9201 09:29:29.125000 Show all devs... Before device enumeration.
9202 09:29:29.128334 Root Device: enabled 1
9203 09:29:29.132016 CPU_CLUSTER: 0: enabled 1
9204 09:29:29.132415 CPU: 00: enabled 1
9205 09:29:29.135233 Compare with tree...
9206 09:29:29.135709 Root Device: enabled 1
9207 09:29:29.138087 CPU_CLUSTER: 0: enabled 1
9208 09:29:29.141905 CPU: 00: enabled 1
9209 09:29:29.142355 Root Device scanning...
9210 09:29:29.144835 scan_static_bus for Root Device
9211 09:29:29.148604 CPU_CLUSTER: 0 enabled
9212 09:29:29.151696 scan_static_bus for Root Device done
9213 09:29:29.155502 scan_bus: bus Root Device finished in 8 msecs
9214 09:29:29.155943 done
9215 09:29:29.161474 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9216 09:29:29.165162 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9217 09:29:29.171386 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9218 09:29:29.175480 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9219 09:29:29.178302 Allocating resources...
9220 09:29:29.178697 Reading resources...
9221 09:29:29.185142 Root Device read_resources bus 0 link: 0
9222 09:29:29.185615 DRAM rank0 size:0x100000000,
9223 09:29:29.188234 DRAM rank1 size=0x100000000
9224 09:29:29.191542 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9225 09:29:29.195305 CPU: 00 missing read_resources
9226 09:29:29.198747 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9227 09:29:29.205322 Root Device read_resources bus 0 link: 0 done
9228 09:29:29.205808 Done reading resources.
9229 09:29:29.211640 Show resources in subtree (Root Device)...After reading.
9230 09:29:29.215294 Root Device child on link 0 CPU_CLUSTER: 0
9231 09:29:29.218823 CPU_CLUSTER: 0 child on link 0 CPU: 00
9232 09:29:29.228636 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9233 09:29:29.229114 CPU: 00
9234 09:29:29.232303 Root Device assign_resources, bus 0 link: 0
9235 09:29:29.235437 CPU_CLUSTER: 0 missing set_resources
9236 09:29:29.238559 Root Device assign_resources, bus 0 link: 0 done
9237 09:29:29.242111 Done setting resources.
9238 09:29:29.249054 Show resources in subtree (Root Device)...After assigning values.
9239 09:29:29.251657 Root Device child on link 0 CPU_CLUSTER: 0
9240 09:29:29.255544 CPU_CLUSTER: 0 child on link 0 CPU: 00
9241 09:29:29.264921 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9242 09:29:29.265323 CPU: 00
9243 09:29:29.268855 Done allocating resources.
9244 09:29:29.272367 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9245 09:29:29.274863 Enabling resources...
9246 09:29:29.275260 done.
9247 09:29:29.278865 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9248 09:29:29.281932 Initializing devices...
9249 09:29:29.285035 Root Device init
9250 09:29:29.285428 init hardware done!
9251 09:29:29.288618 0x00000018: ctrlr->caps
9252 09:29:29.289018 52.000 MHz: ctrlr->f_max
9253 09:29:29.291552 0.400 MHz: ctrlr->f_min
9254 09:29:29.295250 0x40ff8080: ctrlr->voltages
9255 09:29:29.295651 sclk: 390625
9256 09:29:29.298317 Bus Width = 1
9257 09:29:29.298720 sclk: 390625
9258 09:29:29.299025 Bus Width = 1
9259 09:29:29.301813 Early init status = 3
9260 09:29:29.304986 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9261 09:29:29.309370 in-header: 03 fc 00 00 01 00 00 00
9262 09:29:29.312575 in-data: 00
9263 09:29:29.316097 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9264 09:29:29.320484 in-header: 03 fd 00 00 00 00 00 00
9265 09:29:29.323851 in-data:
9266 09:29:29.327540 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9267 09:29:29.331056 in-header: 03 fc 00 00 01 00 00 00
9268 09:29:29.333783 in-data: 00
9269 09:29:29.338030 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9270 09:29:29.342192 in-header: 03 fd 00 00 00 00 00 00
9271 09:29:29.345502 in-data:
9272 09:29:29.348992 [SSUSB] Setting up USB HOST controller...
9273 09:29:29.352635 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9274 09:29:29.355553 [SSUSB] phy power-on done.
9275 09:29:29.358719 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9276 09:29:29.365130 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9277 09:29:29.368706 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9278 09:29:29.375468 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9279 09:29:29.382640 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9280 09:29:29.388406 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9281 09:29:29.395192 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9282 09:29:29.401814 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9283 09:29:29.402250 SPM: binary array size = 0x9dc
9284 09:29:29.408560 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9285 09:29:29.415334 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9286 09:29:29.421884 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9287 09:29:29.425698 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9288 09:29:29.428256 configure_display: Starting display init
9289 09:29:29.465400 anx7625_power_on_init: Init interface.
9290 09:29:29.468822 anx7625_disable_pd_protocol: Disabled PD feature.
9291 09:29:29.471707 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9292 09:29:29.500077 anx7625_start_dp_work: Secure OCM version=00
9293 09:29:29.502690 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9294 09:29:29.517378 sp_tx_get_edid_block: EDID Block = 1
9295 09:29:29.620430 Extracted contents:
9296 09:29:29.623562 header: 00 ff ff ff ff ff ff 00
9297 09:29:29.627148 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9298 09:29:29.630131 version: 01 04
9299 09:29:29.633832 basic params: 95 1f 11 78 0a
9300 09:29:29.636443 chroma info: 76 90 94 55 54 90 27 21 50 54
9301 09:29:29.640186 established: 00 00 00
9302 09:29:29.646749 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9303 09:29:29.650339 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9304 09:29:29.656574 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9305 09:29:29.663263 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9306 09:29:29.670062 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9307 09:29:29.673882 extensions: 00
9308 09:29:29.674413 checksum: fb
9309 09:29:29.674723
9310 09:29:29.676703 Manufacturer: IVO Model 57d Serial Number 0
9311 09:29:29.679916 Made week 0 of 2020
9312 09:29:29.680304 EDID version: 1.4
9313 09:29:29.683875 Digital display
9314 09:29:29.686516 6 bits per primary color channel
9315 09:29:29.686914 DisplayPort interface
9316 09:29:29.690168 Maximum image size: 31 cm x 17 cm
9317 09:29:29.693684 Gamma: 220%
9318 09:29:29.694193 Check DPMS levels
9319 09:29:29.696783 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9320 09:29:29.700420 First detailed timing is preferred timing
9321 09:29:29.703175 Established timings supported:
9322 09:29:29.706535 Standard timings supported:
9323 09:29:29.706949 Detailed timings
9324 09:29:29.713596 Hex of detail: 383680a07038204018303c0035ae10000019
9325 09:29:29.716604 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9326 09:29:29.723345 0780 0798 07c8 0820 hborder 0
9327 09:29:29.726562 0438 043b 0447 0458 vborder 0
9328 09:29:29.726955 -hsync -vsync
9329 09:29:29.730175 Did detailed timing
9330 09:29:29.733175 Hex of detail: 000000000000000000000000000000000000
9331 09:29:29.737247 Manufacturer-specified data, tag 0
9332 09:29:29.743444 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9333 09:29:29.743849 ASCII string: InfoVision
9334 09:29:29.749946 Hex of detail: 000000fe00523134304e574635205248200a
9335 09:29:29.753127 ASCII string: R140NWF5 RH
9336 09:29:29.753523 Checksum
9337 09:29:29.753832 Checksum: 0xfb (valid)
9338 09:29:29.760019 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9339 09:29:29.763128 DSI data_rate: 832800000 bps
9340 09:29:29.766286 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9341 09:29:29.769854 anx7625_parse_edid: pixelclock(138800).
9342 09:29:29.776147 hactive(1920), hsync(48), hfp(24), hbp(88)
9343 09:29:29.779782 vactive(1080), vsync(12), vfp(3), vbp(17)
9344 09:29:29.782736 anx7625_dsi_config: config dsi.
9345 09:29:29.789650 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9346 09:29:29.801962 anx7625_dsi_config: success to config DSI
9347 09:29:29.805577 anx7625_dp_start: MIPI phy setup OK.
9348 09:29:29.808657 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9349 09:29:29.811930 mtk_ddp_mode_set invalid vrefresh 60
9350 09:29:29.815621 main_disp_path_setup
9351 09:29:29.816276 ovl_layer_smi_id_en
9352 09:29:29.818702 ovl_layer_smi_id_en
9353 09:29:29.819095 ccorr_config
9354 09:29:29.819399 aal_config
9355 09:29:29.822322 gamma_config
9356 09:29:29.822716 postmask_config
9357 09:29:29.825729 dither_config
9358 09:29:29.828547 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9359 09:29:29.835467 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9360 09:29:29.838853 Root Device init finished in 551 msecs
9361 09:29:29.841628 CPU_CLUSTER: 0 init
9362 09:29:29.848810 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9363 09:29:29.852195 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9364 09:29:29.855189 APU_MBOX 0x190000b0 = 0x10001
9365 09:29:29.858674 APU_MBOX 0x190001b0 = 0x10001
9366 09:29:29.862210 APU_MBOX 0x190005b0 = 0x10001
9367 09:29:29.865094 APU_MBOX 0x190006b0 = 0x10001
9368 09:29:29.868704 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9369 09:29:29.881279 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9370 09:29:29.893488 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9371 09:29:29.899985 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9372 09:29:29.911940 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9373 09:29:29.921148 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9374 09:29:29.924168 CPU_CLUSTER: 0 init finished in 81 msecs
9375 09:29:29.927436 Devices initialized
9376 09:29:29.930970 Show all devs... After init.
9377 09:29:29.931368 Root Device: enabled 1
9378 09:29:29.934496 CPU_CLUSTER: 0: enabled 1
9379 09:29:29.937861 CPU: 00: enabled 1
9380 09:29:29.941157 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9381 09:29:29.944902 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9382 09:29:29.948351 ELOG: NV offset 0x57f000 size 0x1000
9383 09:29:29.954344 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9384 09:29:29.960908 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9385 09:29:29.964883 ELOG: Event(17) added with size 13 at 2024-06-18 09:29:29 UTC
9386 09:29:29.967652 out: cmd=0x121: 03 db 21 01 00 00 00 00
9387 09:29:29.972339 in-header: 03 67 00 00 2c 00 00 00
9388 09:29:29.985751 in-data: dd 15 ed 1e ba 03 00 00 0a 00 00 00 06 80 00 00 93 7d c2 1e 06 80 00 00 51 b6 e9 1e 06 80 00 00 df cf eb 1e 06 80 00 00 3b 94 ec 1e
9389 09:29:29.992808 ELOG: Event(A1) added with size 10 at 2024-06-18 09:29:29 UTC
9390 09:29:29.999307 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9391 09:29:30.005379 ELOG: Event(A0) added with size 9 at 2024-06-18 09:29:30 UTC
9392 09:29:30.008805 elog_add_boot_reason: Logged dev mode boot
9393 09:29:30.012200 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9394 09:29:30.015819 Finalize devices...
9395 09:29:30.016219 Devices finalized
9396 09:29:30.021863 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9397 09:29:30.025808 Writing coreboot table at 0xffe64000
9398 09:29:30.029107 0. 000000000010a000-0000000000113fff: RAMSTAGE
9399 09:29:30.031970 1. 0000000040000000-00000000400fffff: RAM
9400 09:29:30.035973 2. 0000000040100000-000000004032afff: RAMSTAGE
9401 09:29:30.041931 3. 000000004032b000-00000000545fffff: RAM
9402 09:29:30.045943 4. 0000000054600000-000000005465ffff: BL31
9403 09:29:30.048973 5. 0000000054660000-00000000ffe63fff: RAM
9404 09:29:30.056172 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9405 09:29:30.058726 7. 0000000100000000-000000023fffffff: RAM
9406 09:29:30.059125 Passing 5 GPIOs to payload:
9407 09:29:30.065931 NAME | PORT | POLARITY | VALUE
9408 09:29:30.068710 EC in RW | 0x000000aa | low | undefined
9409 09:29:30.075453 EC interrupt | 0x00000005 | low | undefined
9410 09:29:30.078856 TPM interrupt | 0x000000ab | high | undefined
9411 09:29:30.082538 SD card detect | 0x00000011 | high | undefined
9412 09:29:30.089244 speaker enable | 0x00000093 | high | undefined
9413 09:29:30.091989 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9414 09:29:30.095372 in-header: 03 f9 00 00 02 00 00 00
9415 09:29:30.095826 in-data: 02 00
9416 09:29:30.098879 ADC[4]: Raw value=899483 ID=7
9417 09:29:30.102237 ADC[3]: Raw value=213336 ID=1
9418 09:29:30.102755 RAM Code: 0x71
9419 09:29:30.105932 ADC[6]: Raw value=74557 ID=0
9420 09:29:30.108567 ADC[5]: Raw value=212229 ID=1
9421 09:29:30.108969 SKU Code: 0x1
9422 09:29:30.115715 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f3bf
9423 09:29:30.119053 coreboot table: 964 bytes.
9424 09:29:30.122228 IMD ROOT 0. 0xfffff000 0x00001000
9425 09:29:30.125074 IMD SMALL 1. 0xffffe000 0x00001000
9426 09:29:30.129083 RO MCACHE 2. 0xffffc000 0x00001104
9427 09:29:30.132251 CONSOLE 3. 0xfff7c000 0x00080000
9428 09:29:30.135330 FMAP 4. 0xfff7b000 0x00000452
9429 09:29:30.138854 TIME STAMP 5. 0xfff7a000 0x00000910
9430 09:29:30.141814 VBOOT WORK 6. 0xfff66000 0x00014000
9431 09:29:30.145544 RAMOOPS 7. 0xffe66000 0x00100000
9432 09:29:30.148676 COREBOOT 8. 0xffe64000 0x00002000
9433 09:29:30.149073 IMD small region:
9434 09:29:30.152230 IMD ROOT 0. 0xffffec00 0x00000400
9435 09:29:30.155808 VPD 1. 0xffffeb80 0x0000006c
9436 09:29:30.158665 MMC STATUS 2. 0xffffeb60 0x00000004
9437 09:29:30.165657 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9438 09:29:30.166164 Probing TPM: done!
9439 09:29:30.172229 Connected to device vid:did:rid of 1ae0:0028:00
9440 09:29:30.179258 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9441 09:29:30.182163 Initialized TPM device CR50 revision 0
9442 09:29:30.186087 Checking cr50 for pending updates
9443 09:29:30.191915 Reading cr50 TPM mode
9444 09:29:30.200835 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9445 09:29:30.207416 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9446 09:29:30.247180 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9447 09:29:30.250182 Checking segment from ROM address 0x40100000
9448 09:29:30.254412 Checking segment from ROM address 0x4010001c
9449 09:29:30.260937 Loading segment from ROM address 0x40100000
9450 09:29:30.261425 code (compression=0)
9451 09:29:30.267511 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9452 09:29:30.277146 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9453 09:29:30.277551 it's not compressed!
9454 09:29:30.284183 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9455 09:29:30.287315 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9456 09:29:30.307838 Loading segment from ROM address 0x4010001c
9457 09:29:30.308303 Entry Point 0x80000000
9458 09:29:30.310721 Loaded segments
9459 09:29:30.314236 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9460 09:29:30.321272 Jumping to boot code at 0x80000000(0xffe64000)
9461 09:29:30.327849 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9462 09:29:30.334343 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9463 09:29:30.341680 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9464 09:29:30.345049 Checking segment from ROM address 0x40100000
9465 09:29:30.348813 Checking segment from ROM address 0x4010001c
9466 09:29:30.355908 Loading segment from ROM address 0x40100000
9467 09:29:30.356384 code (compression=1)
9468 09:29:30.361679 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9469 09:29:30.371883 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9470 09:29:30.372281 using LZMA
9471 09:29:30.380406 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9472 09:29:30.387542 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9473 09:29:30.390366 Loading segment from ROM address 0x4010001c
9474 09:29:30.390764 Entry Point 0x54601000
9475 09:29:30.393965 Loaded segments
9476 09:29:30.396978 NOTICE: MT8192 bl31_setup
9477 09:29:30.403954 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9478 09:29:30.406968 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9479 09:29:30.410539 WARNING: region 0:
9480 09:29:30.414041 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 09:29:30.414539 WARNING: region 1:
9482 09:29:30.420460 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9483 09:29:30.424172 WARNING: region 2:
9484 09:29:30.427350 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9485 09:29:30.430578 WARNING: region 3:
9486 09:29:30.434195 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9487 09:29:30.436890 WARNING: region 4:
9488 09:29:30.440464 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 09:29:30.444212 WARNING: region 5:
9490 09:29:30.446877 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 09:29:30.450572 WARNING: region 6:
9492 09:29:30.453932 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 09:29:30.454141 WARNING: region 7:
9494 09:29:30.460879 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 09:29:30.467956 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9496 09:29:30.470914 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9497 09:29:30.474102 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9498 09:29:30.480769 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9499 09:29:30.484271 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9500 09:29:30.487911 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9501 09:29:30.494301 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9502 09:29:30.497518 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9503 09:29:30.501017 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9504 09:29:30.507867 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9505 09:29:30.511575 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9506 09:29:30.514450 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9507 09:29:30.521226 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9508 09:29:30.524218 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9509 09:29:30.531316 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9510 09:29:30.534396 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9511 09:29:30.538446 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9512 09:29:30.544848 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9513 09:29:30.548013 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9514 09:29:30.551195 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9515 09:29:30.558415 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9516 09:29:30.561749 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9517 09:29:30.568533 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9518 09:29:30.571986 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9519 09:29:30.575061 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9520 09:29:30.581599 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9521 09:29:30.584963 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9522 09:29:30.588608 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9523 09:29:30.595417 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9524 09:29:30.598666 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9525 09:29:30.605195 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9526 09:29:30.608679 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9527 09:29:30.611766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9528 09:29:30.614854 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9529 09:29:30.622262 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9530 09:29:30.625327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9531 09:29:30.628185 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9532 09:29:30.631473 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9533 09:29:30.638701 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9534 09:29:30.641910 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9535 09:29:30.645383 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9536 09:29:30.648434 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9537 09:29:30.655282 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9538 09:29:30.658448 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9539 09:29:30.662174 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9540 09:29:30.665026 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9541 09:29:30.672048 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9542 09:29:30.675435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9543 09:29:30.678438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9544 09:29:30.685225 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9545 09:29:30.688544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9546 09:29:30.695168 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9547 09:29:30.698431 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9548 09:29:30.702163 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9549 09:29:30.708991 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9550 09:29:30.712013 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9551 09:29:30.718497 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9552 09:29:30.722166 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9553 09:29:30.728823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9554 09:29:30.731799 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9555 09:29:30.735586 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9556 09:29:30.741780 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9557 09:29:30.745540 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9558 09:29:30.752241 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9559 09:29:30.755275 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9560 09:29:30.762139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9561 09:29:30.765228 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9562 09:29:30.768986 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9563 09:29:30.775235 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9564 09:29:30.778800 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9565 09:29:30.785686 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9566 09:29:30.788661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9567 09:29:30.795495 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9568 09:29:30.798499 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9569 09:29:30.802143 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9570 09:29:30.808465 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9571 09:29:30.812415 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9572 09:29:30.818681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9573 09:29:30.822638 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9574 09:29:30.828919 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9575 09:29:30.832359 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9576 09:29:30.835658 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9577 09:29:30.842288 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9578 09:29:30.845734 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9579 09:29:30.852591 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9580 09:29:30.855647 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9581 09:29:30.862527 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9582 09:29:30.866095 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9583 09:29:30.869085 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9584 09:29:30.875816 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9585 09:29:30.879740 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9586 09:29:30.885742 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9587 09:29:30.889273 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9588 09:29:30.893056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9589 09:29:30.899229 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9590 09:29:30.902757 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9591 09:29:30.909687 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9592 09:29:30.912722 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9593 09:29:30.916311 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9594 09:29:30.919426 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9595 09:29:30.926482 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9596 09:29:30.929396 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9597 09:29:30.932672 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9598 09:29:30.939457 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9599 09:29:30.943038 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9600 09:29:30.946337 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9601 09:29:30.952723 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9602 09:29:30.956076 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9603 09:29:30.963035 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9604 09:29:30.966063 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9605 09:29:30.969757 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9606 09:29:30.976490 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9607 09:29:30.979817 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9608 09:29:30.986457 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9609 09:29:30.990046 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9610 09:29:30.992912 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9611 09:29:30.999905 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9612 09:29:31.002973 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9613 09:29:31.006612 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9614 09:29:31.013132 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9615 09:29:31.016338 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9616 09:29:31.019722 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9617 09:29:31.023393 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9618 09:29:31.026625 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9619 09:29:31.033050 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9620 09:29:31.036768 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9621 09:29:31.043481 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9622 09:29:31.046771 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9623 09:29:31.050344 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9624 09:29:31.056572 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9625 09:29:31.060271 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9626 09:29:31.063558 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9627 09:29:31.069841 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9628 09:29:31.073484 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9629 09:29:31.080092 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9630 09:29:31.083012 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9631 09:29:31.089768 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9632 09:29:31.093527 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9633 09:29:31.096520 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9634 09:29:31.103003 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9635 09:29:31.106735 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9636 09:29:31.109948 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9637 09:29:31.116725 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9638 09:29:31.120190 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9639 09:29:31.126745 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9640 09:29:31.130221 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9641 09:29:31.133318 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9642 09:29:31.139975 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9643 09:29:31.143776 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9644 09:29:31.146906 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9645 09:29:31.153247 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9646 09:29:31.156791 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9647 09:29:31.163579 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9648 09:29:31.166731 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9649 09:29:31.170265 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9650 09:29:31.176728 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9651 09:29:31.180166 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9652 09:29:31.183770 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9653 09:29:31.190200 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9654 09:29:31.193526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9655 09:29:31.200114 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9656 09:29:31.203781 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9657 09:29:31.207013 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9658 09:29:31.213699 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9659 09:29:31.216899 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9660 09:29:31.220581 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9661 09:29:31.226989 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9662 09:29:31.230342 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9663 09:29:31.236755 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9664 09:29:31.240224 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9665 09:29:31.244072 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9666 09:29:31.250281 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9667 09:29:31.253425 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9668 09:29:31.260417 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9669 09:29:31.263981 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9670 09:29:31.267476 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9671 09:29:31.273493 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9672 09:29:31.277035 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9673 09:29:31.283720 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9674 09:29:31.287314 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9675 09:29:31.290306 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9676 09:29:31.296882 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9677 09:29:31.300230 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9678 09:29:31.303620 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9679 09:29:31.310631 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9680 09:29:31.313463 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9681 09:29:31.320385 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9682 09:29:31.323793 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9683 09:29:31.326754 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9684 09:29:31.333454 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9685 09:29:31.337111 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9686 09:29:31.343236 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9687 09:29:31.346477 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9688 09:29:31.350293 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9689 09:29:31.356439 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9690 09:29:31.360167 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9691 09:29:31.366935 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9692 09:29:31.370179 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9693 09:29:31.376683 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9694 09:29:31.380329 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9695 09:29:31.383169 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9696 09:29:31.389709 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9697 09:29:31.393515 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9698 09:29:31.400047 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9699 09:29:31.403128 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9700 09:29:31.406532 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9701 09:29:31.413106 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9702 09:29:31.416511 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9703 09:29:31.423426 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9704 09:29:31.426485 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9705 09:29:31.429665 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9706 09:29:31.436661 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9707 09:29:31.439787 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9708 09:29:31.446156 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9709 09:29:31.449688 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9710 09:29:31.456277 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9711 09:29:31.459639 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9712 09:29:31.462821 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9713 09:29:31.469615 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9714 09:29:31.472687 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9715 09:29:31.479254 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9716 09:29:31.483037 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9717 09:29:31.486150 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9718 09:29:31.492804 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9719 09:29:31.496484 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9720 09:29:31.502816 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9721 09:29:31.506242 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9722 09:29:31.513074 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9723 09:29:31.516231 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9724 09:29:31.519449 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9725 09:29:31.523013 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9726 09:29:31.529369 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9727 09:29:31.532789 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9728 09:29:31.535877 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9729 09:29:31.539754 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9730 09:29:31.545905 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9731 09:29:31.549532 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9732 09:29:31.556169 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9733 09:29:31.559340 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9734 09:29:31.562856 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9735 09:29:31.569394 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9736 09:29:31.573098 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9737 09:29:31.576154 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9738 09:29:31.582879 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9739 09:29:31.586302 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9740 09:29:31.589501 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9741 09:29:31.596342 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9742 09:29:31.599330 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9743 09:29:31.602442 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9744 09:29:31.609191 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9745 09:29:31.612633 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9746 09:29:31.619040 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9747 09:29:31.622578 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9748 09:29:31.625837 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9749 09:29:31.632492 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9750 09:29:31.635936 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9751 09:29:31.639459 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9752 09:29:31.645864 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9753 09:29:31.649514 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9754 09:29:31.652537 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9755 09:29:31.659721 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9756 09:29:31.662992 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9757 09:29:31.669900 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9758 09:29:31.672883 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9759 09:29:31.676489 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9760 09:29:31.683207 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9761 09:29:31.686253 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9762 09:29:31.689754 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9763 09:29:31.696041 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9764 09:29:31.699652 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9765 09:29:31.702684 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9766 09:29:31.705835 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9767 09:29:31.712648 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9768 09:29:31.715743 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9769 09:29:31.719589 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9770 09:29:31.722681 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9771 09:29:31.725816 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9772 09:29:31.732858 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9773 09:29:31.735705 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9774 09:29:31.739328 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9775 09:29:31.746108 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9776 09:29:31.749232 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9777 09:29:31.753256 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9778 09:29:31.759246 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9779 09:29:31.762404 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9780 09:29:31.769121 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9781 09:29:31.772825 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9782 09:29:31.775895 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9783 09:29:31.782654 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9784 09:29:31.785624 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9785 09:29:31.789138 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9786 09:29:31.796071 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9787 09:29:31.799510 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9788 09:29:31.805803 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9789 09:29:31.809666 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9790 09:29:31.816016 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9791 09:29:31.819599 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9792 09:29:31.822634 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9793 09:29:31.829627 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9794 09:29:31.832685 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9795 09:29:31.839128 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9796 09:29:31.842881 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9797 09:29:31.845877 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9798 09:29:31.852791 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9799 09:29:31.855812 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9800 09:29:31.859594 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9801 09:29:31.865940 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9802 09:29:31.868882 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9803 09:29:31.875951 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9804 09:29:31.879128 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9805 09:29:31.885346 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9806 09:29:31.888848 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9807 09:29:31.895322 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9808 09:29:31.899054 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9809 09:29:31.902237 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9810 09:29:31.908779 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9811 09:29:31.912334 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9812 09:29:31.918611 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9813 09:29:31.922489 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9814 09:29:31.925454 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9815 09:29:31.932162 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9816 09:29:31.935928 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9817 09:29:31.941911 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9818 09:29:31.945346 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9819 09:29:31.948930 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9820 09:29:31.955617 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9821 09:29:31.958833 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9822 09:29:31.965777 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9823 09:29:31.968798 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9824 09:29:31.972082 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9825 09:29:31.978840 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9826 09:29:31.981891 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9827 09:29:31.988740 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9828 09:29:31.992240 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9829 09:29:31.995074 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9830 09:29:32.002185 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9831 09:29:32.005367 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9832 09:29:32.012244 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9833 09:29:32.015472 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9834 09:29:32.019055 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9835 09:29:32.025636 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9836 09:29:32.029089 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9837 09:29:32.036050 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9838 09:29:32.039068 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9839 09:29:32.042322 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9840 09:29:32.048890 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9841 09:29:32.052313 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9842 09:29:32.059014 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9843 09:29:32.062052 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9844 09:29:32.065956 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9845 09:29:32.071999 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9846 09:29:32.075741 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9847 09:29:32.082304 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9848 09:29:32.085478 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9849 09:29:32.089100 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9850 09:29:32.099483 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9851 09:29:32.099693 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9852 09:29:32.105402 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9853 09:29:32.108467 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9854 09:29:32.115390 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9855 09:29:32.118241 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9856 09:29:32.121459 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9857 09:29:32.128820 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9858 09:29:32.131544 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9859 09:29:32.138249 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9860 09:29:32.141797 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9861 09:29:32.148625 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9862 09:29:32.151977 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9863 09:29:32.158524 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9864 09:29:32.161725 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9865 09:29:32.165196 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9866 09:29:32.172082 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9867 09:29:32.175782 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9868 09:29:32.181848 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9869 09:29:32.185875 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9870 09:29:32.191956 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9871 09:29:32.195622 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9872 09:29:32.198626 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9873 09:29:32.205512 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9874 09:29:32.208493 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9875 09:29:32.215245 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9876 09:29:32.218948 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9877 09:29:32.225838 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9878 09:29:32.228696 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9879 09:29:32.232108 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9880 09:29:32.238904 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9881 09:29:32.242303 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9882 09:29:32.248927 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9883 09:29:32.251859 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9884 09:29:32.255702 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9885 09:29:32.262042 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9886 09:29:32.265788 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9887 09:29:32.272650 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9888 09:29:32.275451 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9889 09:29:32.279085 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9890 09:29:32.285742 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9891 09:29:32.289019 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9892 09:29:32.296091 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9893 09:29:32.299217 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9894 09:29:32.305919 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9895 09:29:32.309597 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9896 09:29:32.312459 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9897 09:29:32.319255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9898 09:29:32.322966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9899 09:29:32.329295 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9900 09:29:32.333516 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9901 09:29:32.339335 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9902 09:29:32.342735 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9903 09:29:32.349677 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9904 09:29:32.352880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9905 09:29:32.356435 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9906 09:29:32.363075 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9907 09:29:32.366433 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9908 09:29:32.372447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9909 09:29:32.376029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9910 09:29:32.382819 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9911 09:29:32.386096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9912 09:29:32.392691 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9913 09:29:32.396063 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9914 09:29:32.402934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9915 09:29:32.406424 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9916 09:29:32.413096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9917 09:29:32.416330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9918 09:29:32.423040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9919 09:29:32.426069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9920 09:29:32.432796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9921 09:29:32.435946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9922 09:29:32.442751 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9923 09:29:32.445869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9924 09:29:32.452747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9925 09:29:32.456351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9926 09:29:32.462871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9927 09:29:32.465874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9928 09:29:32.472817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9929 09:29:32.475859 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9930 09:29:32.476259 INFO: [APUAPC] vio 0
9931 09:29:32.483792 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9932 09:29:32.487327 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9933 09:29:32.490518 INFO: [APUAPC] D0_APC_0: 0x400510
9934 09:29:32.493598 INFO: [APUAPC] D0_APC_1: 0x0
9935 09:29:32.497426 INFO: [APUAPC] D0_APC_2: 0x1540
9936 09:29:32.500123 INFO: [APUAPC] D0_APC_3: 0x0
9937 09:29:32.503414 INFO: [APUAPC] D1_APC_0: 0xffffffff
9938 09:29:32.507231 INFO: [APUAPC] D1_APC_1: 0xffffffff
9939 09:29:32.510492 INFO: [APUAPC] D1_APC_2: 0x3fffff
9940 09:29:32.513764 INFO: [APUAPC] D1_APC_3: 0x0
9941 09:29:32.516752 INFO: [APUAPC] D2_APC_0: 0xffffffff
9942 09:29:32.520308 INFO: [APUAPC] D2_APC_1: 0xffffffff
9943 09:29:32.523798 INFO: [APUAPC] D2_APC_2: 0x3fffff
9944 09:29:32.526994 INFO: [APUAPC] D2_APC_3: 0x0
9945 09:29:32.530483 INFO: [APUAPC] D3_APC_0: 0xffffffff
9946 09:29:32.533484 INFO: [APUAPC] D3_APC_1: 0xffffffff
9947 09:29:32.537270 INFO: [APUAPC] D3_APC_2: 0x3fffff
9948 09:29:32.537669 INFO: [APUAPC] D3_APC_3: 0x0
9949 09:29:32.543964 INFO: [APUAPC] D4_APC_0: 0xffffffff
9950 09:29:32.547015 INFO: [APUAPC] D4_APC_1: 0xffffffff
9951 09:29:32.550281 INFO: [APUAPC] D4_APC_2: 0x3fffff
9952 09:29:32.550682 INFO: [APUAPC] D4_APC_3: 0x0
9953 09:29:32.553965 INFO: [APUAPC] D5_APC_0: 0xffffffff
9954 09:29:32.557126 INFO: [APUAPC] D5_APC_1: 0xffffffff
9955 09:29:32.560218 INFO: [APUAPC] D5_APC_2: 0x3fffff
9956 09:29:32.563564 INFO: [APUAPC] D5_APC_3: 0x0
9957 09:29:32.567165 INFO: [APUAPC] D6_APC_0: 0xffffffff
9958 09:29:32.570290 INFO: [APUAPC] D6_APC_1: 0xffffffff
9959 09:29:32.573926 INFO: [APUAPC] D6_APC_2: 0x3fffff
9960 09:29:32.576785 INFO: [APUAPC] D6_APC_3: 0x0
9961 09:29:32.579955 INFO: [APUAPC] D7_APC_0: 0xffffffff
9962 09:29:32.583749 INFO: [APUAPC] D7_APC_1: 0xffffffff
9963 09:29:32.586841 INFO: [APUAPC] D7_APC_2: 0x3fffff
9964 09:29:32.590048 INFO: [APUAPC] D7_APC_3: 0x0
9965 09:29:32.593643 INFO: [APUAPC] D8_APC_0: 0xffffffff
9966 09:29:32.596763 INFO: [APUAPC] D8_APC_1: 0xffffffff
9967 09:29:32.600481 INFO: [APUAPC] D8_APC_2: 0x3fffff
9968 09:29:32.603568 INFO: [APUAPC] D8_APC_3: 0x0
9969 09:29:32.606755 INFO: [APUAPC] D9_APC_0: 0xffffffff
9970 09:29:32.610454 INFO: [APUAPC] D9_APC_1: 0xffffffff
9971 09:29:32.613576 INFO: [APUAPC] D9_APC_2: 0x3fffff
9972 09:29:32.616620 INFO: [APUAPC] D9_APC_3: 0x0
9973 09:29:32.620033 INFO: [APUAPC] D10_APC_0: 0xffffffff
9974 09:29:32.623406 INFO: [APUAPC] D10_APC_1: 0xffffffff
9975 09:29:32.626833 INFO: [APUAPC] D10_APC_2: 0x3fffff
9976 09:29:32.629962 INFO: [APUAPC] D10_APC_3: 0x0
9977 09:29:32.633415 INFO: [APUAPC] D11_APC_0: 0xffffffff
9978 09:29:32.636694 INFO: [APUAPC] D11_APC_1: 0xffffffff
9979 09:29:32.639788 INFO: [APUAPC] D11_APC_2: 0x3fffff
9980 09:29:32.643404 INFO: [APUAPC] D11_APC_3: 0x0
9981 09:29:32.646570 INFO: [APUAPC] D12_APC_0: 0xffffffff
9982 09:29:32.650206 INFO: [APUAPC] D12_APC_1: 0xffffffff
9983 09:29:32.653397 INFO: [APUAPC] D12_APC_2: 0x3fffff
9984 09:29:32.656652 INFO: [APUAPC] D12_APC_3: 0x0
9985 09:29:32.660102 INFO: [APUAPC] D13_APC_0: 0xffffffff
9986 09:29:32.663365 INFO: [APUAPC] D13_APC_1: 0xffffffff
9987 09:29:32.666567 INFO: [APUAPC] D13_APC_2: 0x3fffff
9988 09:29:32.670469 INFO: [APUAPC] D13_APC_3: 0x0
9989 09:29:32.673556 INFO: [APUAPC] D14_APC_0: 0xffffffff
9990 09:29:32.676830 INFO: [APUAPC] D14_APC_1: 0xffffffff
9991 09:29:32.679935 INFO: [APUAPC] D14_APC_2: 0x3fffff
9992 09:29:32.683237 INFO: [APUAPC] D14_APC_3: 0x0
9993 09:29:32.687070 INFO: [APUAPC] D15_APC_0: 0xffffffff
9994 09:29:32.689924 INFO: [APUAPC] D15_APC_1: 0xffffffff
9995 09:29:32.693200 INFO: [APUAPC] D15_APC_2: 0x3fffff
9996 09:29:32.696701 INFO: [APUAPC] D15_APC_3: 0x0
9997 09:29:32.700291 INFO: [APUAPC] APC_CON: 0x4
9998 09:29:32.703525 INFO: [NOCDAPC] D0_APC_0: 0x0
9999 09:29:32.706379 INFO: [NOCDAPC] D0_APC_1: 0x0
10000 09:29:32.710070 INFO: [NOCDAPC] D1_APC_0: 0x0
10001 09:29:32.710463 INFO: [NOCDAPC] D1_APC_1: 0xfff
10002 09:29:32.713215 INFO: [NOCDAPC] D2_APC_0: 0x0
10003 09:29:32.717068 INFO: [NOCDAPC] D2_APC_1: 0xfff
10004 09:29:32.719885 INFO: [NOCDAPC] D3_APC_0: 0x0
10005 09:29:32.723131 INFO: [NOCDAPC] D3_APC_1: 0xfff
10006 09:29:32.726863 INFO: [NOCDAPC] D4_APC_0: 0x0
10007 09:29:32.730495 INFO: [NOCDAPC] D4_APC_1: 0xfff
10008 09:29:32.733352 INFO: [NOCDAPC] D5_APC_0: 0x0
10009 09:29:32.736724 INFO: [NOCDAPC] D5_APC_1: 0xfff
10010 09:29:32.739813 INFO: [NOCDAPC] D6_APC_0: 0x0
10011 09:29:32.740208 INFO: [NOCDAPC] D6_APC_1: 0xfff
10012 09:29:32.743283 INFO: [NOCDAPC] D7_APC_0: 0x0
10013 09:29:32.746635 INFO: [NOCDAPC] D7_APC_1: 0xfff
10014 09:29:32.749896 INFO: [NOCDAPC] D8_APC_0: 0x0
10015 09:29:32.753691 INFO: [NOCDAPC] D8_APC_1: 0xfff
10016 09:29:32.756669 INFO: [NOCDAPC] D9_APC_0: 0x0
10017 09:29:32.760277 INFO: [NOCDAPC] D9_APC_1: 0xfff
10018 09:29:32.763149 INFO: [NOCDAPC] D10_APC_0: 0x0
10019 09:29:32.766923 INFO: [NOCDAPC] D10_APC_1: 0xfff
10020 09:29:32.770054 INFO: [NOCDAPC] D11_APC_0: 0x0
10021 09:29:32.773170 INFO: [NOCDAPC] D11_APC_1: 0xfff
10022 09:29:32.776689 INFO: [NOCDAPC] D12_APC_0: 0x0
10023 09:29:32.779912 INFO: [NOCDAPC] D12_APC_1: 0xfff
10024 09:29:32.780364 INFO: [NOCDAPC] D13_APC_0: 0x0
10025 09:29:32.783526 INFO: [NOCDAPC] D13_APC_1: 0xfff
10026 09:29:32.786598 INFO: [NOCDAPC] D14_APC_0: 0x0
10027 09:29:32.790200 INFO: [NOCDAPC] D14_APC_1: 0xfff
10028 09:29:32.793308 INFO: [NOCDAPC] D15_APC_0: 0x0
10029 09:29:32.796969 INFO: [NOCDAPC] D15_APC_1: 0xfff
10030 09:29:32.800061 INFO: [NOCDAPC] APC_CON: 0x4
10031 09:29:32.803398 INFO: [APUAPC] set_apusys_apc done
10032 09:29:32.806828 INFO: [DEVAPC] devapc_init done
10033 09:29:32.810283 INFO: GICv3 without legacy support detected.
10034 09:29:32.813651 INFO: ARM GICv3 driver initialized in EL3
10035 09:29:32.816870 INFO: Maximum SPI INTID supported: 639
10036 09:29:32.823571 INFO: BL31: Initializing runtime services
10037 09:29:32.826720 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10038 09:29:32.830378 INFO: SPM: enable CPC mode
10039 09:29:32.836574 INFO: mcdi ready for mcusys-off-idle and system suspend
10040 09:29:32.840153 INFO: BL31: Preparing for EL3 exit to normal world
10041 09:29:32.843043 INFO: Entry point address = 0x80000000
10042 09:29:32.846737 INFO: SPSR = 0x8
10043 09:29:32.851832
10044 09:29:32.852247
10045 09:29:32.852560
10046 09:29:32.855210 Starting depthcharge on Spherion...
10047 09:29:32.855611
10048 09:29:32.855919 Wipe memory regions:
10049 09:29:32.856208
10050 09:29:32.858628 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10051 09:29:32.859122 start: 2.2.4 bootloader-commands (timeout 00:04:24) [common]
10052 09:29:32.859507 Setting prompt string to ['asurada:']
10053 09:29:32.859868 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:24)
10054 09:29:32.860472 [0x00000040000000, 0x00000054600000)
10055 09:29:32.980692
10056 09:29:32.981186 [0x00000054660000, 0x00000080000000)
10057 09:29:33.241654
10058 09:29:33.242177 [0x000000821a7280, 0x000000ffe64000)
10059 09:29:33.986343
10060 09:29:33.986798 [0x00000100000000, 0x00000240000000)
10061 09:29:35.875833
10062 09:29:35.879072 Initializing XHCI USB controller at 0x11200000.
10063 09:29:36.919220
10064 09:29:36.922216 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10065 09:29:36.922299
10066 09:29:36.922377
10067 09:29:36.922645 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10069 09:29:37.022977 asurada: tftpboot 192.168.201.1 14407667/tftp-deploy-x7pvf940/kernel/image.itb 14407667/tftp-deploy-x7pvf940/kernel/cmdline
10070 09:29:37.023204 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10071 09:29:37.023312 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10072 09:29:37.027461 tftpboot 192.168.201.1 14407667/tftp-deploy-x7pvf940/kernel/image.itp-deploy-x7pvf940/kernel/cmdline
10073 09:29:37.027540
10074 09:29:37.027600 Waiting for link
10075 09:29:37.185751
10076 09:29:37.186029 R8152: Initializing
10077 09:29:37.186162
10078 09:29:37.189359 Version 6 (ocp_data = 5c30)
10079 09:29:37.189586
10080 09:29:37.193003 R8152: Done initializing
10081 09:29:37.193176
10082 09:29:37.193299 Adding net device
10083 09:29:39.097239
10084 09:29:39.097375 done.
10085 09:29:39.097464
10086 09:29:39.097548 MAC: 00:24:32:30:78:52
10087 09:29:39.097628
10088 09:29:39.100605 Sending DHCP discover... done.
10089 09:29:39.100686
10090 09:29:48.949381 Waiting for reply... R8152: Bulk read error 0xffffffbf
10091 09:29:48.949914
10092 09:29:48.952876 Receive failed.
10093 09:29:48.953295
10094 09:29:48.953604 done.
10095 09:29:48.954056
10096 09:29:48.956336 Sending DHCP request... done.
10097 09:29:48.956734
10098 09:29:48.962747 Waiting for reply... done.
10099 09:29:48.963200
10100 09:29:48.963659 My ip is 192.168.201.14
10101 09:29:48.963984
10102 09:29:48.965687 The DHCP server ip is 192.168.201.1
10103 09:29:48.966130
10104 09:29:48.969340 TFTP server IP predefined by user: 192.168.201.1
10105 09:29:48.969750
10106 09:29:48.976052 Bootfile predefined by user: 14407667/tftp-deploy-x7pvf940/kernel/image.itb
10107 09:29:48.976337
10108 09:29:48.979144 Sending tftp read request... done.
10109 09:29:48.979433
10110 09:29:48.987924 Waiting for the transfer...
10111 09:29:48.988300
10112 09:29:49.697127 00000000 ################################################################
10113 09:29:49.697591
10114 09:29:50.414994 00080000 ################################################################
10115 09:29:50.415579
10116 09:29:51.136041 00100000 ################################################################
10117 09:29:51.136498
10118 09:29:51.852570 00180000 ################################################################
10119 09:29:51.853064
10120 09:29:52.554240 00200000 ################################################################
10121 09:29:52.554719
10122 09:29:53.265616 00280000 ################################################################
10123 09:29:53.266178
10124 09:29:53.991009 00300000 ################################################################
10125 09:29:53.991571
10126 09:29:54.721216 00380000 ################################################################
10127 09:29:54.721742
10128 09:29:55.451004 00400000 ################################################################
10129 09:29:55.451694
10130 09:29:56.154041 00480000 ################################################################
10131 09:29:56.154628
10132 09:29:56.885062 00500000 ################################################################
10133 09:29:56.885558
10134 09:29:57.609661 00580000 ################################################################
10135 09:29:57.610167
10136 09:29:58.324488 00600000 ################################################################
10137 09:29:58.325046
10138 09:29:59.029537 00680000 ################################################################
10139 09:29:59.030184
10140 09:29:59.705041 00700000 ################################################################
10141 09:29:59.705590
10142 09:30:00.417107 00780000 ################################################################
10143 09:30:00.417591
10144 09:30:01.091945 00800000 ################################################################
10145 09:30:01.092080
10146 09:30:01.773973 00880000 ################################################################
10147 09:30:01.774154
10148 09:30:02.470352 00900000 ################################################################
10149 09:30:02.470834
10150 09:30:03.210772 00980000 ################################################################
10151 09:30:03.211274
10152 09:30:03.940101 00a00000 ################################################################
10153 09:30:03.940604
10154 09:30:04.647991 00a80000 ################################################################
10155 09:30:04.648462
10156 09:30:05.371898 00b00000 ################################################################
10157 09:30:05.372355
10158 09:30:06.097660 00b80000 ################################################################
10159 09:30:06.098174
10160 09:30:06.843578 00c00000 ################################################################
10161 09:30:06.844039
10162 09:30:07.548900 00c80000 ################################################################
10163 09:30:07.549434
10164 09:30:08.270741 00d00000 ################################################################
10165 09:30:08.271244
10166 09:30:08.930124 00d80000 ################################################################
10167 09:30:08.930253
10168 09:30:09.526306 00e00000 ################################################################
10169 09:30:09.526797
10170 09:30:10.247481 00e80000 ################################################################
10171 09:30:10.247956
10172 09:30:10.922089 00f00000 ################################################################
10173 09:30:10.922220
10174 09:30:11.637358 00f80000 ################################################################
10175 09:30:11.637838
10176 09:30:12.320837 01000000 ################################################################
10177 09:30:12.321379
10178 09:30:13.056096 01080000 ################################################################
10179 09:30:13.056566
10180 09:30:13.787202 01100000 ################################################################
10181 09:30:13.787723
10182 09:30:14.472125 01180000 ################################################################
10183 09:30:14.472268
10184 09:30:15.108548 01200000 ################################################################
10185 09:30:15.109074
10186 09:30:15.778930 01280000 ################################################################
10187 09:30:15.779052
10188 09:30:16.448326 01300000 ################################################################
10189 09:30:16.448500
10190 09:30:17.091583 01380000 ################################################################
10191 09:30:17.091713
10192 09:30:17.681518 01400000 ################################################################
10193 09:30:17.681650
10194 09:30:18.254926 01480000 ################################################################
10195 09:30:18.255056
10196 09:30:18.840124 01500000 ################################################################
10197 09:30:18.840255
10198 09:30:19.424834 01580000 ################################################################
10199 09:30:19.424978
10200 09:30:19.999329 01600000 ################################################################
10201 09:30:19.999488
10202 09:30:20.571037 01680000 ################################################################
10203 09:30:20.571170
10204 09:30:21.182454 01700000 ################################################################
10205 09:30:21.182601
10206 09:30:21.776381 01780000 ################################################################
10207 09:30:21.776517
10208 09:30:22.362233 01800000 ################################################################
10209 09:30:22.362343
10210 09:30:22.932702 01880000 ################################################################
10211 09:30:22.932886
10212 09:30:23.497628 01900000 ################################################################
10213 09:30:23.497808
10214 09:30:24.063981 01980000 ################################################################
10215 09:30:24.064114
10216 09:30:24.622995 01a00000 ################################################################
10217 09:30:24.623124
10218 09:30:25.183566 01a80000 ################################################################
10219 09:30:25.183697
10220 09:30:25.763345 01b00000 ################################################################
10221 09:30:25.763519
10222 09:30:26.363303 01b80000 ################################################################
10223 09:30:26.363434
10224 09:30:26.950325 01c00000 ################################################################
10225 09:30:26.950498
10226 09:30:27.519499 01c80000 ################################################################
10227 09:30:27.519637
10228 09:30:28.086215 01d00000 ################################################################
10229 09:30:28.086357
10230 09:30:28.669391 01d80000 ################################################################
10231 09:30:28.669529
10232 09:30:29.225257 01e00000 ################################################################
10233 09:30:29.225423
10234 09:30:29.795102 01e80000 ################################################################
10235 09:30:29.795248
10236 09:30:30.360730 01f00000 ################################################################
10237 09:30:30.360884
10238 09:30:30.929884 01f80000 ################################################################
10239 09:30:30.930079
10240 09:30:31.496405 02000000 ################################################################
10241 09:30:31.496542
10242 09:30:32.068713 02080000 ################################################################
10243 09:30:32.068855
10244 09:30:32.659602 02100000 ################################################################
10245 09:30:32.659739
10246 09:30:33.238307 02180000 ################################################################
10247 09:30:33.238442
10248 09:30:33.808536 02200000 ################################################################
10249 09:30:33.808665
10250 09:30:34.399575 02280000 ################################################################
10251 09:30:34.399706
10252 09:30:34.984789 02300000 ################################################################
10253 09:30:34.984925
10254 09:30:35.574166 02380000 ################################################################
10255 09:30:35.574335
10256 09:30:36.136692 02400000 ################################################################
10257 09:30:36.136828
10258 09:30:36.711784 02480000 ################################################################
10259 09:30:36.711920
10260 09:30:37.284484 02500000 ################################################################
10261 09:30:37.284653
10262 09:30:37.878022 02580000 ################################################################
10263 09:30:37.878195
10264 09:30:38.468091 02600000 ################################################################
10265 09:30:38.468264
10266 09:30:39.054224 02680000 ################################################################
10267 09:30:39.054458
10268 09:30:39.630940 02700000 ################################################################
10269 09:30:39.631115
10270 09:30:40.230608 02780000 ################################################################
10271 09:30:40.230782
10272 09:30:40.819602 02800000 ################################################################
10273 09:30:40.819748
10274 09:30:41.437817 02880000 ################################################################
10275 09:30:41.438280
10276 09:30:42.152732 02900000 ################################################################
10277 09:30:42.152880
10278 09:30:42.867879 02980000 ################################################################
10279 09:30:42.868340
10280 09:30:43.566902 02a00000 ################################################################
10281 09:30:43.567383
10282 09:30:44.287657 02a80000 ################################################################
10283 09:30:44.288163
10284 09:30:45.009682 02b00000 ################################################################
10285 09:30:45.010185
10286 09:30:45.714507 02b80000 ################################################################
10287 09:30:45.715031
10288 09:30:46.451276 02c00000 ################################################################
10289 09:30:46.451824
10290 09:30:47.122189 02c80000 ################################################################
10291 09:30:47.122307
10292 09:30:47.812011 02d00000 ################################################################
10293 09:30:47.812591
10294 09:30:48.502597 02d80000 ################################################################
10295 09:30:48.502919
10296 09:30:49.154657 02e00000 ################################################################
10297 09:30:49.155137
10298 09:30:49.794848 02e80000 ################################################################
10299 09:30:49.795485
10300 09:30:50.438069 02f00000 ################################################################
10301 09:30:50.438225
10302 09:30:51.103210 02f80000 ################################################################
10303 09:30:51.103344
10304 09:30:51.745664 03000000 ################################################################
10305 09:30:51.745791
10306 09:30:52.407894 03080000 ################################################################
10307 09:30:52.408022
10308 09:30:52.984841 03100000 ################################################################
10309 09:30:52.984958
10310 09:30:53.562829 03180000 ################################################################
10311 09:30:53.562942
10312 09:30:54.119796 03200000 ################################################################
10313 09:30:54.119909
10314 09:30:54.670146 03280000 ################################################################
10315 09:30:54.670262
10316 09:30:55.188277 03300000 ################################################################
10317 09:30:55.188391
10318 09:30:55.589487 03380000 ################################################ done.
10319 09:30:55.589605
10320 09:30:55.592725 The bootfile was 54390942 bytes long.
10321 09:30:55.592828
10322 09:30:55.595822 Sending tftp read request... done.
10323 09:30:55.595900
10324 09:30:55.595988 Waiting for the transfer...
10325 09:30:55.596072
10326 09:30:55.599393 00000000 # done.
10327 09:30:55.599492
10328 09:30:55.606092 Command line loaded dynamically from TFTP file: 14407667/tftp-deploy-x7pvf940/kernel/cmdline
10329 09:30:55.606193
10330 09:30:55.619074 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10331 09:30:55.619159
10332 09:30:55.622564 Loading FIT.
10333 09:30:55.622642
10334 09:30:55.625641 Image ramdisk-1 has 41214930 bytes.
10335 09:30:55.625718
10336 09:30:55.625778 Image fdt-1 has 47258 bytes.
10337 09:30:55.628810
10338 09:30:55.628886 Image kernel-1 has 13126726 bytes.
10339 09:30:55.628946
10340 09:30:55.639034 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10341 09:30:55.639113
10342 09:30:55.655786 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10343 09:30:55.655868
10344 09:30:55.662525 Choosing best match conf-1 for compat google,spherion-rev2.
10345 09:30:55.666306
10346 09:30:55.671245 Connected to device vid:did:rid of 1ae0:0028:00
10347 09:30:55.679156
10348 09:30:55.682756 tpm_get_response: command 0x17b, return code 0x0
10349 09:30:55.682834
10350 09:30:55.689215 ec_init: CrosEC protocol v3 supported (256, 248)
10351 09:30:55.689293
10352 09:30:55.692533 tpm_cleanup: add release locality here.
10353 09:30:55.692611
10354 09:30:55.696202 Shutting down all USB controllers.
10355 09:30:55.696279
10356 09:30:55.699315 Removing current net device
10357 09:30:55.699397
10358 09:30:55.702913 Exiting depthcharge with code 4 at timestamp: 112239832
10359 09:30:55.702991
10360 09:30:55.705947 LZMA decompressing kernel-1 to 0x821a6718
10361 09:30:55.709188
10362 09:30:55.712906 LZMA decompressing kernel-1 to 0x40000000
10363 09:30:57.329731
10364 09:30:57.329845 jumping to kernel
10365 09:30:57.330374 end: 2.2.4 bootloader-commands (duration 00:01:24) [common]
10366 09:30:57.330469 start: 2.2.5 auto-login-action (timeout 00:02:59) [common]
10367 09:30:57.330539 Setting prompt string to ['Linux version [0-9]']
10368 09:30:57.330605 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10369 09:30:57.330670 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10370 09:30:57.411193
10371 09:30:57.414501 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10372 09:30:57.418076 start: 2.2.5.1 login-action (timeout 00:02:59) [common]
10373 09:30:57.418171 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10374 09:30:57.418240 Setting prompt string to []
10375 09:30:57.418315 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10376 09:30:57.418385 Using line separator: #'\n'#
10377 09:30:57.418476 No login prompt set.
10378 09:30:57.418536 Parsing kernel messages
10379 09:30:57.418589 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10380 09:30:57.418685 [login-action] Waiting for messages, (timeout 00:02:59)
10381 09:30:57.418747 Waiting using forced prompt support (timeout 00:01:30)
10382 09:30:57.437911 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j235720-arm64-gcc-10-defconfig-arm64-chromebook-gjv8m) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024
10383 09:30:57.441425 [ 0.000000] random: crng init done
10384 09:30:57.444408 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10385 09:30:57.448060 [ 0.000000] efi: UEFI not found.
10386 09:30:57.457855 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10387 09:30:57.464507 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10388 09:30:57.474764 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10389 09:30:57.484354 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10390 09:30:57.491315 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10391 09:30:57.494252 [ 0.000000] printk: bootconsole [mtk8250] enabled
10392 09:30:57.503014 [ 0.000000] NUMA: No NUMA configuration found
10393 09:30:57.509815 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10394 09:30:57.516593 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10395 09:30:57.516693 [ 0.000000] Zone ranges:
10396 09:30:57.522875 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10397 09:30:57.526571 [ 0.000000] DMA32 empty
10398 09:30:57.533127 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10399 09:30:57.536139 [ 0.000000] Movable zone start for each node
10400 09:30:57.539933 [ 0.000000] Early memory node ranges
10401 09:30:57.546436 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10402 09:30:57.552934 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10403 09:30:57.559853 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10404 09:30:57.566735 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10405 09:30:57.573173 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10406 09:30:57.579769 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10407 09:30:57.635692 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10408 09:30:57.642201 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10409 09:30:57.649050 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10410 09:30:57.652096 [ 0.000000] psci: probing for conduit method from DT.
10411 09:30:57.659041 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10412 09:30:57.662260 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10413 09:30:57.669053 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10414 09:30:57.672254 [ 0.000000] psci: SMC Calling Convention v1.2
10415 09:30:57.678926 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10416 09:30:57.681952 [ 0.000000] Detected VIPT I-cache on CPU0
10417 09:30:57.689268 [ 0.000000] CPU features: detected: GIC system register CPU interface
10418 09:30:57.695694 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10419 09:30:57.702588 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10420 09:30:57.708747 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10421 09:30:57.715349 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10422 09:30:57.721916 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10423 09:30:57.728791 [ 0.000000] alternatives: applying boot alternatives
10424 09:30:57.732410 [ 0.000000] Fallback order for Node 0: 0
10425 09:30:57.739071 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10426 09:30:57.742216 [ 0.000000] Policy zone: Normal
10427 09:30:57.759099 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10428 09:30:57.768566 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10429 09:30:57.779236 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10430 09:30:57.789349 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10431 09:30:57.796146 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10432 09:30:57.799101 <6>[ 0.000000] software IO TLB: area num 8.
10433 09:30:57.855213 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10434 09:30:58.004917 <6>[ 0.000000] Memory: 7923808K/8385536K available (18112K kernel code, 4120K rwdata, 22644K rodata, 8512K init, 616K bss, 428960K reserved, 32768K cma-reserved)
10435 09:30:58.011290 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10436 09:30:58.018212 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10437 09:30:58.021246 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10438 09:30:58.027943 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10439 09:30:58.034805 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10440 09:30:58.038001 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10441 09:30:58.048111 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10442 09:30:58.054906 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10443 09:30:58.058156 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10444 09:30:58.065491 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10445 09:30:58.068692 <6>[ 0.000000] GICv3: 608 SPIs implemented
10446 09:30:58.075449 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10447 09:30:58.079051 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10448 09:30:58.081960 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10449 09:30:58.091982 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10450 09:30:58.101891 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10451 09:30:58.115188 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10452 09:30:58.122263 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10453 09:30:58.131161 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10454 09:30:58.144673 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10455 09:30:58.150992 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10456 09:30:58.158112 <6>[ 0.009178] Console: colour dummy device 80x25
10457 09:30:58.167962 <6>[ 0.013936] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10458 09:30:58.170988 <6>[ 0.024443] pid_max: default: 32768 minimum: 301
10459 09:30:58.177755 <6>[ 0.029314] LSM: Security Framework initializing
10460 09:30:58.184255 <6>[ 0.034285] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10461 09:30:58.194184 <6>[ 0.042099] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10462 09:30:58.201169 <6>[ 0.051571] cblist_init_generic: Setting adjustable number of callback queues.
10463 09:30:58.207972 <6>[ 0.059015] cblist_init_generic: Setting shift to 3 and lim to 1.
10464 09:30:58.217500 <6>[ 0.065354] cblist_init_generic: Setting adjustable number of callback queues.
10465 09:30:58.221230 <6>[ 0.072781] cblist_init_generic: Setting shift to 3 and lim to 1.
10466 09:30:58.227740 <6>[ 0.079178] rcu: Hierarchical SRCU implementation.
10467 09:30:58.233943 <6>[ 0.084194] rcu: Max phase no-delay instances is 1000.
10468 09:30:58.240816 <6>[ 0.091249] EFI services will not be available.
10469 09:30:58.243999 <6>[ 0.096205] smp: Bringing up secondary CPUs ...
10470 09:30:58.251943 <6>[ 0.101284] Detected VIPT I-cache on CPU1
10471 09:30:58.258902 <6>[ 0.101356] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10472 09:30:58.265602 <6>[ 0.101388] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10473 09:30:58.268912 <6>[ 0.101722] Detected VIPT I-cache on CPU2
10474 09:30:58.275258 <6>[ 0.101775] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10475 09:30:58.282138 <6>[ 0.101792] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10476 09:30:58.288380 <6>[ 0.102050] Detected VIPT I-cache on CPU3
10477 09:30:58.295568 <6>[ 0.102097] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10478 09:30:58.302241 <6>[ 0.102111] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10479 09:30:58.305088 <6>[ 0.102413] CPU features: detected: Spectre-v4
10480 09:30:58.311803 <6>[ 0.102419] CPU features: detected: Spectre-BHB
10481 09:30:58.315267 <6>[ 0.102424] Detected PIPT I-cache on CPU4
10482 09:30:58.321706 <6>[ 0.102481] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10483 09:30:58.328253 <6>[ 0.102498] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10484 09:30:58.335348 <6>[ 0.102787] Detected PIPT I-cache on CPU5
10485 09:30:58.342166 <6>[ 0.102850] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10486 09:30:58.348453 <6>[ 0.102866] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10487 09:30:58.351588 <6>[ 0.103144] Detected PIPT I-cache on CPU6
10488 09:30:58.358320 <6>[ 0.103211] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10489 09:30:58.365104 <6>[ 0.103226] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10490 09:30:58.371599 <6>[ 0.103521] Detected PIPT I-cache on CPU7
10491 09:30:58.378395 <6>[ 0.103587] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10492 09:30:58.385285 <6>[ 0.103602] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10493 09:30:58.388167 <6>[ 0.103650] smp: Brought up 1 node, 8 CPUs
10494 09:30:58.391606 <6>[ 0.245065] SMP: Total of 8 processors activated.
10495 09:30:58.398577 <6>[ 0.249986] CPU features: detected: 32-bit EL0 Support
10496 09:30:58.408425 <6>[ 0.255350] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10497 09:30:58.415153 <6>[ 0.264150] CPU features: detected: Common not Private translations
10498 09:30:58.418258 <6>[ 0.270626] CPU features: detected: CRC32 instructions
10499 09:30:58.424758 <6>[ 0.275978] CPU features: detected: RCpc load-acquire (LDAPR)
10500 09:30:58.431507 <6>[ 0.281938] CPU features: detected: LSE atomic instructions
10501 09:30:58.438210 <6>[ 0.287719] CPU features: detected: Privileged Access Never
10502 09:30:58.441655 <6>[ 0.293499] CPU features: detected: RAS Extension Support
10503 09:30:58.448473 <6>[ 0.299107] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10504 09:30:58.455402 <6>[ 0.306327] CPU: All CPU(s) started at EL2
10505 09:30:58.458477 <6>[ 0.310643] alternatives: applying system-wide alternatives
10506 09:30:58.469730 <6>[ 0.321483] devtmpfs: initialized
10507 09:30:58.485140 <6>[ 0.330324] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10508 09:30:58.491927 <6>[ 0.340284] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10509 09:30:58.498590 <6>[ 0.348490] pinctrl core: initialized pinctrl subsystem
10510 09:30:58.501888 <6>[ 0.355167] DMI not present or invalid.
10511 09:30:58.508756 <6>[ 0.359578] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10512 09:30:58.518301 <6>[ 0.366462] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10513 09:30:58.525136 <6>[ 0.374053] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10514 09:30:58.535261 <6>[ 0.382285] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10515 09:30:58.538200 <6>[ 0.390528] audit: initializing netlink subsys (disabled)
10516 09:30:58.548113 <5>[ 0.396209] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10517 09:30:58.555124 <6>[ 0.396899] thermal_sys: Registered thermal governor 'step_wise'
10518 09:30:58.561753 <6>[ 0.404173] thermal_sys: Registered thermal governor 'power_allocator'
10519 09:30:58.564879 <6>[ 0.410428] cpuidle: using governor menu
10520 09:30:58.571672 <6>[ 0.421391] NET: Registered PF_QIPCRTR protocol family
10521 09:30:58.578484 <6>[ 0.426873] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10522 09:30:58.581541 <6>[ 0.433977] ASID allocator initialised with 32768 entries
10523 09:30:58.588967 <6>[ 0.440557] Serial: AMBA PL011 UART driver
10524 09:30:58.597460 <4>[ 0.449383] Trying to register duplicate clock ID: 134
10525 09:30:58.655965 <6>[ 0.510869] KASLR enabled
10526 09:30:58.670175 <6>[ 0.518582] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10527 09:30:58.677045 <6>[ 0.525598] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10528 09:30:58.683653 <6>[ 0.532088] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10529 09:30:58.690017 <6>[ 0.539093] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10530 09:30:58.696846 <6>[ 0.545580] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10531 09:30:58.703106 <6>[ 0.552586] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10532 09:30:58.709784 <6>[ 0.559073] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10533 09:30:58.716686 <6>[ 0.566078] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10534 09:30:58.719811 <6>[ 0.573594] ACPI: Interpreter disabled.
10535 09:30:58.728533 <6>[ 0.580018] iommu: Default domain type: Translated
10536 09:30:58.735197 <6>[ 0.585128] iommu: DMA domain TLB invalidation policy: strict mode
10537 09:30:58.738626 <5>[ 0.591790] SCSI subsystem initialized
10538 09:30:58.745274 <6>[ 0.595954] usbcore: registered new interface driver usbfs
10539 09:30:58.751996 <6>[ 0.601687] usbcore: registered new interface driver hub
10540 09:30:58.754898 <6>[ 0.607239] usbcore: registered new device driver usb
10541 09:30:58.761900 <6>[ 0.613335] pps_core: LinuxPPS API ver. 1 registered
10542 09:30:58.771799 <6>[ 0.618528] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10543 09:30:58.775349 <6>[ 0.627875] PTP clock support registered
10544 09:30:58.777948 <6>[ 0.632120] EDAC MC: Ver: 3.0.0
10545 09:30:58.785815 <6>[ 0.637266] FPGA manager framework
10546 09:30:58.792010 <6>[ 0.640952] Advanced Linux Sound Architecture Driver Initialized.
10547 09:30:58.795906 <6>[ 0.647688] vgaarb: loaded
10548 09:30:58.801903 <6>[ 0.650836] clocksource: Switched to clocksource arch_sys_counter
10549 09:30:58.805577 <5>[ 0.657274] VFS: Disk quotas dquot_6.6.0
10550 09:30:58.811743 <6>[ 0.661463] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10551 09:30:58.814875 <6>[ 0.668652] pnp: PnP ACPI: disabled
10552 09:30:58.823647 <6>[ 0.675391] NET: Registered PF_INET protocol family
10553 09:30:58.833553 <6>[ 0.680923] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10554 09:30:58.845046 <6>[ 0.693242] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10555 09:30:58.854837 <6>[ 0.702057] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10556 09:30:58.861431 <6>[ 0.710028] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10557 09:30:58.868251 <6>[ 0.718724] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10558 09:30:58.880520 <6>[ 0.728479] TCP: Hash tables configured (established 65536 bind 65536)
10559 09:30:58.887079 <6>[ 0.735340] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10560 09:30:58.893185 <6>[ 0.742540] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10561 09:30:58.899945 <6>[ 0.750239] NET: Registered PF_UNIX/PF_LOCAL protocol family
10562 09:30:58.906958 <6>[ 0.756390] RPC: Registered named UNIX socket transport module.
10563 09:30:58.909973 <6>[ 0.762543] RPC: Registered udp transport module.
10564 09:30:58.916951 <6>[ 0.767474] RPC: Registered tcp transport module.
10565 09:30:58.923226 <6>[ 0.772405] RPC: Registered tcp NFSv4.1 backchannel transport module.
10566 09:30:58.926908 <6>[ 0.779072] PCI: CLS 0 bytes, default 64
10567 09:30:58.930470 <6>[ 0.783477] Unpacking initramfs...
10568 09:30:58.939970 <6>[ 0.787182] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10569 09:30:58.946795 <6>[ 0.795800] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10570 09:30:58.953183 <6>[ 0.804595] kvm [1]: IPA Size Limit: 40 bits
10571 09:30:58.956706 <6>[ 0.809121] kvm [1]: GICv3: no GICV resource entry
10572 09:30:58.963720 <6>[ 0.814143] kvm [1]: disabling GICv2 emulation
10573 09:30:58.966458 <6>[ 0.818834] kvm [1]: GIC system register CPU interface enabled
10574 09:30:58.973625 <6>[ 0.824999] kvm [1]: vgic interrupt IRQ18
10575 09:30:58.979828 <6>[ 0.830894] kvm [1]: VHE mode initialized successfully
10576 09:30:58.986588 <5>[ 0.837312] Initialise system trusted keyrings
10577 09:30:58.993496 <6>[ 0.842116] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10578 09:30:59.000304 <6>[ 0.852093] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10579 09:30:59.007304 <5>[ 0.858481] NFS: Registering the id_resolver key type
10580 09:30:59.010313 <5>[ 0.863778] Key type id_resolver registered
10581 09:30:59.017233 <5>[ 0.868193] Key type id_legacy registered
10582 09:30:59.023416 <6>[ 0.872469] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10583 09:30:59.030317 <6>[ 0.879390] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10584 09:30:59.036887 <6>[ 0.887095] 9p: Installing v9fs 9p2000 file system support
10585 09:30:59.072906 <5>[ 0.924831] Key type asymmetric registered
10586 09:30:59.076361 <5>[ 0.929162] Asymmetric key parser 'x509' registered
10587 09:30:59.086321 <6>[ 0.934322] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10588 09:30:59.089542 <6>[ 0.941938] io scheduler mq-deadline registered
10589 09:30:59.093266 <6>[ 0.946705] io scheduler kyber registered
10590 09:30:59.111736 <6>[ 0.963623] EINJ: ACPI disabled.
10591 09:30:59.144242 <4>[ 0.989537] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10592 09:30:59.154158 <4>[ 1.000181] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 09:30:59.169310 <6>[ 1.020992] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10594 09:30:59.177047 <6>[ 1.028879] printk: console [ttyS0] disabled
10595 09:30:59.204911 <6>[ 1.053509] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10596 09:30:59.211690 <6>[ 1.062988] printk: console [ttyS0] enabled
10597 09:30:59.215235 <6>[ 1.062988] printk: console [ttyS0] enabled
10598 09:30:59.221772 <6>[ 1.071884] printk: bootconsole [mtk8250] disabled
10599 09:30:59.225255 <6>[ 1.071884] printk: bootconsole [mtk8250] disabled
10600 09:30:59.231817 <6>[ 1.082892] SuperH (H)SCI(F) driver initialized
10601 09:30:59.234854 <6>[ 1.088142] msm_serial: driver initialized
10602 09:30:59.248574 <6>[ 1.097060] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10603 09:30:59.259017 <6>[ 1.105603] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10604 09:30:59.265243 <6>[ 1.114143] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10605 09:30:59.275192 <6>[ 1.122770] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10606 09:30:59.281878 <6>[ 1.131482] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10607 09:30:59.292047 <6>[ 1.140195] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10608 09:30:59.301935 <6>[ 1.148734] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10609 09:30:59.308383 <6>[ 1.157529] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10610 09:30:59.318167 <6>[ 1.166070] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10611 09:30:59.329808 <6>[ 1.181422] loop: module loaded
10612 09:30:59.336081 <6>[ 1.187406] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10613 09:30:59.359236 <4>[ 1.210649] mtk-pmic-keys: Failed to locate of_node [id: -1]
10614 09:30:59.365848 <6>[ 1.217363] megasas: 07.719.03.00-rc1
10615 09:30:59.375119 <6>[ 1.226888] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10616 09:30:59.382965 <6>[ 1.234222] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10617 09:30:59.398950 <6>[ 1.250844] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10618 09:30:59.455894 <6>[ 1.300804] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10619 09:31:00.662008 <6>[ 2.513582] Freeing initrd memory: 40244K
10620 09:31:00.673200 <6>[ 2.525319] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10621 09:31:00.684352 <6>[ 2.536229] tun: Universal TUN/TAP device driver, 1.6
10622 09:31:00.687388 <6>[ 2.542273] thunder_xcv, ver 1.0
10623 09:31:00.691053 <6>[ 2.545777] thunder_bgx, ver 1.0
10624 09:31:00.694205 <6>[ 2.549275] nicpf, ver 1.0
10625 09:31:00.704772 <6>[ 2.553276] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10626 09:31:00.708062 <6>[ 2.560753] hns3: Copyright (c) 2017 Huawei Corporation.
10627 09:31:00.711332 <6>[ 2.566341] hclge is initializing
10628 09:31:00.718138 <6>[ 2.569923] e1000: Intel(R) PRO/1000 Network Driver
10629 09:31:00.724973 <6>[ 2.575052] e1000: Copyright (c) 1999-2006 Intel Corporation.
10630 09:31:00.728370 <6>[ 2.581063] e1000e: Intel(R) PRO/1000 Network Driver
10631 09:31:00.734557 <6>[ 2.586278] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10632 09:31:00.741334 <6>[ 2.592464] igb: Intel(R) Gigabit Ethernet Network Driver
10633 09:31:00.748028 <6>[ 2.598113] igb: Copyright (c) 2007-2014 Intel Corporation.
10634 09:31:00.754880 <6>[ 2.603947] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10635 09:31:00.761045 <6>[ 2.610465] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10636 09:31:00.764505 <6>[ 2.616923] sky2: driver version 1.30
10637 09:31:00.771440 <6>[ 2.621845] usbcore: registered new device driver r8152-cfgselector
10638 09:31:00.777657 <6>[ 2.628384] usbcore: registered new interface driver r8152
10639 09:31:00.781433 <6>[ 2.634194] VFIO - User Level meta-driver version: 0.3
10640 09:31:00.790884 <6>[ 2.642420] usbcore: registered new interface driver usb-storage
10641 09:31:00.797099 <6>[ 2.648863] usbcore: registered new device driver onboard-usb-hub
10642 09:31:00.805869 <6>[ 2.658004] mt6397-rtc mt6359-rtc: registered as rtc0
10643 09:31:00.816306 <6>[ 2.663472] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-18T09:31:00 UTC (1718703060)
10644 09:31:00.819556 <6>[ 2.673030] i2c_dev: i2c /dev entries driver
10645 09:31:00.832901 <4>[ 2.684987] cpu cpu0: supply cpu not found, using dummy regulator
10646 09:31:00.840158 <4>[ 2.691413] cpu cpu1: supply cpu not found, using dummy regulator
10647 09:31:00.846561 <4>[ 2.697818] cpu cpu2: supply cpu not found, using dummy regulator
10648 09:31:00.852910 <4>[ 2.704217] cpu cpu3: supply cpu not found, using dummy regulator
10649 09:31:00.859900 <4>[ 2.710638] cpu cpu4: supply cpu not found, using dummy regulator
10650 09:31:00.866586 <4>[ 2.717038] cpu cpu5: supply cpu not found, using dummy regulator
10651 09:31:00.872765 <4>[ 2.723439] cpu cpu6: supply cpu not found, using dummy regulator
10652 09:31:00.879608 <4>[ 2.729838] cpu cpu7: supply cpu not found, using dummy regulator
10653 09:31:00.898722 <6>[ 2.750479] cpu cpu0: EM: created perf domain
10654 09:31:00.901757 <6>[ 2.755407] cpu cpu4: EM: created perf domain
10655 09:31:00.909215 <6>[ 2.760978] sdhci: Secure Digital Host Controller Interface driver
10656 09:31:00.915839 <6>[ 2.767411] sdhci: Copyright(c) Pierre Ossman
10657 09:31:00.922623 <6>[ 2.772377] Synopsys Designware Multimedia Card Interface Driver
10658 09:31:00.928901 <6>[ 2.779030] sdhci-pltfm: SDHCI platform and OF driver helper
10659 09:31:00.932080 <6>[ 2.779172] mmc0: CQHCI version 5.10
10660 09:31:00.939088 <6>[ 2.789265] ledtrig-cpu: registered to indicate activity on CPUs
10661 09:31:00.945648 <6>[ 2.796295] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10662 09:31:00.951945 <6>[ 2.803355] usbcore: registered new interface driver usbhid
10663 09:31:00.955548 <6>[ 2.809178] usbhid: USB HID core driver
10664 09:31:00.961940 <6>[ 2.813374] spi_master spi0: will run message pump with realtime priority
10665 09:31:01.011394 <6>[ 2.856519] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10666 09:31:01.030490 <6>[ 2.872204] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10667 09:31:01.034218 <6>[ 2.884379] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16014
10668 09:31:01.041123 <6>[ 2.887450] cros-ec-spi spi0.0: Chrome EC device registered
10669 09:31:01.044530 <6>[ 2.897647] mmc0: Command Queue Engine enabled
10670 09:31:01.051176 <6>[ 2.902373] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10671 09:31:01.057964 <6>[ 2.909838] mmcblk0: mmc0:0001 DA4128 116 GiB
10672 09:31:01.068139 <6>[ 2.910452] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10673 09:31:01.071233 <6>[ 2.918405] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10674 09:31:01.077814 <6>[ 2.925051] NET: Registered PF_PACKET protocol family
10675 09:31:01.084410 <6>[ 2.930960] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10676 09:31:01.087959 <6>[ 2.935178] 9pnet: Installing 9P2000 support
10677 09:31:01.094266 <6>[ 2.940978] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10678 09:31:01.097399 <5>[ 2.944848] Key type dns_resolver registered
10679 09:31:01.104370 <6>[ 2.950682] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10680 09:31:01.107581 <6>[ 2.955137] registered taskstats version 1
10681 09:31:01.114245 <5>[ 2.965450] Loading compiled-in X.509 certificates
10682 09:31:01.142115 <4>[ 2.987531] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10683 09:31:01.152310 <4>[ 2.998226] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10684 09:31:01.166154 <6>[ 3.017918] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10685 09:31:01.172827 <6>[ 3.024773] xhci-mtk 11200000.usb: xHCI Host Controller
10686 09:31:01.179606 <6>[ 3.030289] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10687 09:31:01.189709 <6>[ 3.038142] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10688 09:31:01.196390 <6>[ 3.047578] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10689 09:31:01.203112 <6>[ 3.053743] xhci-mtk 11200000.usb: xHCI Host Controller
10690 09:31:01.209344 <6>[ 3.059245] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10691 09:31:01.216282 <6>[ 3.066905] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10692 09:31:01.222959 <6>[ 3.074655] hub 1-0:1.0: USB hub found
10693 09:31:01.225824 <6>[ 3.078681] hub 1-0:1.0: 1 port detected
10694 09:31:01.233163 <6>[ 3.082981] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10695 09:31:01.239985 <6>[ 3.091746] hub 2-0:1.0: USB hub found
10696 09:31:01.243136 <6>[ 3.095772] hub 2-0:1.0: 1 port detected
10697 09:31:01.252195 <6>[ 3.104019] mtk-msdc 11f70000.mmc: Got CD GPIO
10698 09:31:01.265312 <6>[ 3.113724] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10699 09:31:01.275265 <6>[ 3.122099] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10700 09:31:01.281815 <6>[ 3.130439] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10701 09:31:01.291596 <6>[ 3.138782] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10702 09:31:01.298420 <6>[ 3.147122] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10703 09:31:01.308260 <6>[ 3.155459] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10704 09:31:01.315238 <6>[ 3.163798] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10705 09:31:01.324533 <6>[ 3.172137] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10706 09:31:01.331778 <6>[ 3.180480] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10707 09:31:01.341118 <6>[ 3.188819] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10708 09:31:01.347850 <6>[ 3.197157] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10709 09:31:01.357557 <6>[ 3.205503] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10710 09:31:01.364300 <6>[ 3.213840] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10711 09:31:01.374291 <6>[ 3.222178] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10712 09:31:01.380656 <6>[ 3.230516] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10713 09:31:01.387589 <6>[ 3.239209] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10714 09:31:01.394208 <6>[ 3.246377] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10715 09:31:01.401395 <6>[ 3.253174] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10716 09:31:01.411124 <6>[ 3.259940] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10717 09:31:01.417844 <6>[ 3.266877] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10718 09:31:01.424605 <6>[ 3.273763] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10719 09:31:01.434542 <6>[ 3.282907] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10720 09:31:01.444435 <6>[ 3.292029] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10721 09:31:01.454435 <6>[ 3.301323] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10722 09:31:01.464276 <6>[ 3.310790] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10723 09:31:01.470805 <6>[ 3.320257] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10724 09:31:01.480892 <6>[ 3.329377] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10725 09:31:01.490967 <6>[ 3.338844] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10726 09:31:01.500877 <6>[ 3.347963] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10727 09:31:01.511030 <6>[ 3.357261] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10728 09:31:01.520522 <6>[ 3.367421] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10729 09:31:01.530475 <6>[ 3.379295] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10730 09:31:01.654172 <6>[ 3.503097] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10731 09:31:01.809477 <6>[ 3.661211] hub 1-1:1.0: USB hub found
10732 09:31:01.812510 <6>[ 3.665750] hub 1-1:1.0: 4 ports detected
10733 09:31:01.824681 <6>[ 3.676433] hub 1-1:1.0: USB hub found
10734 09:31:01.827516 <6>[ 3.680761] hub 1-1:1.0: 4 ports detected
10735 09:31:01.934248 <6>[ 3.783144] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10736 09:31:01.961426 <6>[ 3.813272] hub 2-1:1.0: USB hub found
10737 09:31:01.964576 <6>[ 3.817802] hub 2-1:1.0: 3 ports detected
10738 09:31:01.976128 <6>[ 3.828246] hub 2-1:1.0: USB hub found
10739 09:31:01.979690 <6>[ 3.832706] hub 2-1:1.0: 3 ports detected
10740 09:31:02.150438 <6>[ 3.999158] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10741 09:31:02.283329 <6>[ 4.135125] hub 1-1.4:1.0: USB hub found
10742 09:31:02.286165 <6>[ 4.139788] hub 1-1.4:1.0: 2 ports detected
10743 09:31:02.300989 <6>[ 4.153236] hub 1-1.4:1.0: USB hub found
10744 09:31:02.304094 <6>[ 4.157861] hub 1-1.4:1.0: 2 ports detected
10745 09:31:02.362697 <6>[ 4.211371] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10746 09:31:02.470770 <6>[ 4.319796] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10747 09:31:02.507508 <4>[ 4.356139] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10748 09:31:02.517426 <4>[ 4.365285] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10749 09:31:02.556500 <6>[ 4.408513] r8152 2-1.3:1.0 eth0: v1.12.13
10750 09:31:02.602097 <6>[ 4.451011] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10751 09:31:02.794249 <6>[ 4.643079] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10752 09:31:04.232769 <6>[ 6.084920] r8152 2-1.3:1.0 eth0: carrier on
10753 09:31:06.802462 <5>[ 6.114896] Sending DHCP requests .., OK
10754 09:31:06.809422 <6>[ 8.659228] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10755 09:31:06.812249 <6>[ 8.667507] IP-Config: Complete:
10756 09:31:06.825859 <6>[ 8.670993] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10757 09:31:06.832578 <6>[ 8.681695] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10758 09:31:06.838791 <6>[ 8.690304] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10759 09:31:06.845513 <6>[ 8.690311] nameserver0=192.168.201.1
10760 09:31:06.849136 <6>[ 8.702397] clk: Disabling unused clocks
10761 09:31:06.852475 <6>[ 8.707588] ALSA device list:
10762 09:31:06.855446 <6>[ 8.710908] No soundcards found.
10763 09:31:06.865683 <6>[ 8.718244] Freeing unused kernel memory: 8512K
10764 09:31:06.869361 <6>[ 8.723208] Run /init as init process
10765 09:31:06.896946 <6>[ 8.749461] NET: Registered PF_INET6 protocol family
10766 09:31:06.903656 <6>[ 8.756318] Segment Routing with IPv6
10767 09:31:06.906709 <6>[ 8.760279] In-situ OAM (IOAM) with IPv6
10768 09:31:06.947008 <30>[ 8.772991] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10769 09:31:06.953451 <30>[ 8.806028] systemd[1]: Detected architecture arm64.
10770 09:31:06.953529
10771 09:31:06.959813 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10772 09:31:06.959891
10773 09:31:06.974618 <30>[ 8.827160] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10774 09:31:07.090521 <30>[ 8.940134] systemd[1]: Queued start job for default target graphical.target.
10775 09:31:07.151367 <30>[ 9.000816] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10776 09:31:07.158197 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10777 09:31:07.178730 <30>[ 9.027672] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10778 09:31:07.188121 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10779 09:31:07.206732 <30>[ 9.056123] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10780 09:31:07.216919 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10781 09:31:07.235526 <30>[ 9.084544] systemd[1]: Created slice user.slice - User and Session Slice.
10782 09:31:07.241655 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10783 09:31:07.265751 <30>[ 9.111919] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10784 09:31:07.272660 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10785 09:31:07.293078 <30>[ 9.139363] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10786 09:31:07.299844 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10787 09:31:07.327472 <30>[ 9.167225] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10788 09:31:07.337703 <30>[ 9.187043] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10789 09:31:07.343921 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10790 09:31:07.362444 <30>[ 9.211566] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10791 09:31:07.371776 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10792 09:31:07.389822 <30>[ 9.239063] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10793 09:31:07.399818 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10794 09:31:07.414527 <30>[ 9.267242] systemd[1]: Reached target paths.target - Path Units.
10795 09:31:07.424509 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10796 09:31:07.442559 <30>[ 9.291591] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10797 09:31:07.448916 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10798 09:31:07.462751 <30>[ 9.315137] systemd[1]: Reached target slices.target - Slice Units.
10799 09:31:07.472443 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10800 09:31:07.487188 <30>[ 9.339619] systemd[1]: Reached target swap.target - Swaps.
10801 09:31:07.493273 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10802 09:31:07.514323 <30>[ 9.363633] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10803 09:31:07.524397 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10804 09:31:07.542009 <30>[ 9.391603] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10805 09:31:07.552417 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10806 09:31:07.571860 <30>[ 9.421335] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10807 09:31:07.582242 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10808 09:31:07.598607 <30>[ 9.447820] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10809 09:31:07.608392 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10810 09:31:07.626076 <30>[ 9.475753] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10811 09:31:07.632728 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10812 09:31:07.650385 <30>[ 9.499778] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10813 09:31:07.660507 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10814 09:31:07.679118 <30>[ 9.528534] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10815 09:31:07.688846 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10816 09:31:07.707147 <30>[ 9.556252] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10817 09:31:07.716866 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10818 09:31:07.769881 <30>[ 9.619212] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10819 09:31:07.776651 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10820 09:31:07.795859 <30>[ 9.645209] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10821 09:31:07.802211 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10822 09:31:07.841838 <30>[ 9.691496] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10823 09:31:07.848918 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10824 09:31:07.876630 <30>[ 9.719582] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10825 09:31:07.890456 <30>[ 9.740178] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10826 09:31:07.900380 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10827 09:31:07.923300 <30>[ 9.772692] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10828 09:31:07.930100 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10829 09:31:07.978654 <30>[ 9.827972] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10830 09:31:07.988343 Startin<6>[ 9.837354] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10831 09:31:07.995236 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10832 09:31:08.019340 <30>[ 9.868807] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10833 09:31:08.026144 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10834 09:31:08.051302 <30>[ 9.900500] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10835 09:31:08.061071 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10836 09:31:08.083161 <30>[ 9.932615] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10837 09:31:08.089676 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10838 09:31:08.158311 <30>[ 10.007583] systemd[1]: Starting systemd-journald.service - Journal Service...
10839 09:31:08.165017 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10840 09:31:08.185204 <30>[ 10.034624] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10841 09:31:08.192030 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10842 09:31:08.216234 <30>[ 10.062485] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10843 09:31:08.223097 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10844 09:31:08.246813 <30>[ 10.095998] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10845 09:31:08.256055 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10846 09:31:08.276850 <30>[ 10.126125] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10847 09:31:08.283225 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10848 09:31:08.307753 <30>[ 10.157060] systemd[1]: Started systemd-journald.service - Journal Service.
10849 09:31:08.314228 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10850 09:31:08.336063 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10851 09:31:08.354399 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10852 09:31:08.370311 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10853 09:31:08.386587 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10854 09:31:08.407253 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10855 09:31:08.431613 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10856 09:31:08.455929 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10857 09:31:08.480721 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10858 09:31:08.505464 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10859 09:31:08.525112 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10860 09:31:08.547727 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10861 09:31:08.572244 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10862 09:31:08.590432 See 'systemctl status systemd-remount-fs.service' for details.
10863 09:31:08.615382 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10864 09:31:08.640457 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10865 09:31:08.681926 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10866 09:31:08.702634 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10867 09:31:08.723830 <46>[ 10.573395] systemd-journald[182]: Received client request to flush runtime journal.
10868 09:31:08.730802 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10869 09:31:08.752668 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10870 09:31:08.773803 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10871 09:31:08.795746 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10872 09:31:08.815442 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10873 09:31:08.835283 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10874 09:31:08.854913 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10875 09:31:08.875252 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10876 09:31:08.918338 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10877 09:31:08.941047 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10878 09:31:08.958202 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10879 09:31:08.977883 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10880 09:31:09.034852 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10881 09:31:09.060024 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10882 09:31:09.084846 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10883 09:31:09.105045 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10884 09:31:09.150937 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10885 09:31:09.232175 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10886 09:31:09.256871 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10887 09:31:09.287570 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10888 09:31:09.323543 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10889 09:31:09.362634 <5>[ 11.212148] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10890 09:31:09.372629 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10891 09:31:09.423372 <5>[ 11.272976] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10892 09:31:09.429827 <5>[ 11.280617] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10893 09:31:09.440276 <4>[ 11.289845] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10894 09:31:09.447209 [[0;32m OK [<6>[ 11.300055] cfg80211: failed to load regulatory.db
10895 09:31:09.453394 0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10896 09:31:09.474668 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10897 09:31:09.494631 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10898 09:31:09.524902 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard <3>[ 11.372090] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10899 09:31:09.531504 unused blocks on<3>[ 11.381776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10900 09:31:09.534987 ce a week.
10901 09:31:09.541351 <3>[ 11.391383] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10902 09:31:09.554148 [[0;32m OK [<6>[ 11.404354] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10903 09:31:09.564045 <3>[ 11.406915] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10904 09:31:09.570792 0m] Reached targ<6>[ 11.415413] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10905 09:31:09.580679 et [0;1;39mtime<6>[ 11.419784] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10906 09:31:09.590510 rs.target[0m - <6>[ 11.419791] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10907 09:31:09.590589 Timer Units.
10908 09:31:09.600316 <4>[ 11.419968] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10909 09:31:09.610285 <6>[ 11.420650] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10910 09:31:09.617276 <6>[ 11.420655] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10911 09:31:09.623832 <3>[ 11.421310] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10912 09:31:09.633639 <6>[ 11.423249] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10913 09:31:09.640003 <6>[ 11.423284] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10914 09:31:09.650168 <6>[ 11.423290] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10915 09:31:09.656864 <6>[ 11.423299] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10916 09:31:09.666620 <6>[ 11.428915] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10917 09:31:09.674319 <6>[ 11.443820] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10918 09:31:09.681034 <3>[ 11.448625] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10919 09:31:09.690924 <3>[ 11.448640] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10920 09:31:09.697617 <3>[ 11.448644] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10921 09:31:09.707294 <3>[ 11.455197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10922 09:31:09.714981 <6>[ 11.459227] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10923 09:31:09.722110 <3>[ 11.479024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10924 09:31:09.732514 <4>[ 11.502146] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10925 09:31:09.736093 <4>[ 11.502146] Fallback method does not support PEC.
10926 09:31:09.743051 <6>[ 11.503241] mc: Linux media interface: v0.10
10927 09:31:09.749481 <3>[ 11.507133] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10928 09:31:09.756942 <6>[ 11.512130] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10929 09:31:09.763623 <6>[ 11.532159] remoteproc remoteproc0: scp is available
10930 09:31:09.771022 <3>[ 11.532346] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10931 09:31:09.777165 <4>[ 11.540055] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10932 09:31:09.783836 <6>[ 11.540682] remoteproc remoteproc0: powering up scp
10933 09:31:09.790756 <3>[ 11.540994] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 09:31:09.800623 <4>[ 11.542048] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10935 09:31:09.803868 <6>[ 11.548173] videodev: Linux video capture interface: v2.00
10936 09:31:09.814231 <3>[ 11.548635] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10937 09:31:09.821824 <3>[ 11.548649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10938 09:31:09.828214 <6>[ 11.557370] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10939 09:31:09.837903 <3>[ 11.564817] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10940 09:31:09.845049 <3>[ 11.564823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10941 09:31:09.852306 <6>[ 11.573514] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10942 09:31:09.859070 <3>[ 11.581583] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10943 09:31:09.869387 <3>[ 11.582640] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10944 09:31:09.875824 <3>[ 11.583484] power_supply sbs-5-000b: driver failed to report `status' property: -6
10945 09:31:09.885780 <3>[ 11.593748] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 09:31:09.896584 <6>[ 11.595697] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10947 09:31:09.903369 <3>[ 11.599764] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10948 09:31:09.910176 <6>[ 11.608198] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10949 09:31:09.919893 <6>[ 11.608536] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10950 09:31:09.926511 <3>[ 11.628877] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10951 09:31:09.933965 <6>[ 11.635787] pci_bus 0000:00: root bus resource [bus 00-ff]
10952 09:31:09.940576 <6>[ 11.635795] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10953 09:31:09.950715 <6>[ 11.635800] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10954 09:31:09.957049 <3>[ 11.641221] power_supply sbs-5-000b: driver failed to report `cycle_count' property: -6
10955 09:31:09.967439 <6>[ 11.649552] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10956 09:31:09.974977 <6>[ 11.649792] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10957 09:31:09.984731 <3>[ 11.677478] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 09:31:09.992334 <6>[ 11.679106] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10959 09:31:09.995997 <6>[ 11.679708] Bluetooth: Core ver 2.22
10960 09:31:09.999076 <6>[ 11.679862] NET: Registered PF_BLUETOOTH protocol family
10961 09:31:10.005764 <6>[ 11.679865] Bluetooth: HCI device and connection manager initialized
10962 09:31:10.012612 <6>[ 11.679912] Bluetooth: HCI socket layer initialized
10963 09:31:10.015693 <6>[ 11.679925] Bluetooth: L2CAP socket layer initialized
10964 09:31:10.022594 <6>[ 11.679949] Bluetooth: SCO socket layer initialized
10965 09:31:10.029775 <3>[ 11.708003] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10966 09:31:10.036693 <6>[ 11.709297] pci 0000:00:00.0: supports D1 D2
10967 09:31:10.042939 <6>[ 11.716545] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10968 09:31:10.050144 <6>[ 11.717326] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10969 09:31:10.056715 <6>[ 11.719289] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10970 09:31:10.070294 <6>[ 11.720659] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10971 09:31:10.076787 <6>[ 11.720877] usbcore: registered new interface driver uvcvideo
10972 09:31:10.083111 <6>[ 11.726084] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10973 09:31:10.089699 <6>[ 11.730145] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10974 09:31:10.099826 <6>[ 11.730767] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10975 09:31:10.106406 <6>[ 11.731202] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10976 09:31:10.112997 <6>[ 11.731242] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10977 09:31:10.119818 <6>[ 11.731267] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10978 09:31:10.129656 <6>[ 11.731288] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10979 09:31:10.133248 <6>[ 11.731416] pci 0000:01:00.0: supports D1 D2
10980 09:31:10.140011 <6>[ 11.731420] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10981 09:31:10.146936 <6>[ 11.733917] remoteproc remoteproc0: remote processor scp is now up
10982 09:31:10.153465 <6>[ 11.735114] usbcore: registered new interface driver btusb
10983 09:31:10.163320 <4>[ 11.736205] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10984 09:31:10.169469 <3>[ 11.736213] Bluetooth: hci0: Failed to load firmware file (-2)
10985 09:31:10.173118 <3>[ 11.736215] Bluetooth: hci0: Failed to set up firmware (-2)
10986 09:31:10.186208 <4>[ 11.736224] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10987 09:31:10.192656 <6>[ 11.743038] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10988 09:31:10.199571 <6>[ 11.745433] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10989 09:31:10.209576 <3>[ 11.754807] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10990 09:31:10.216109 <6>[ 11.761165] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10991 09:31:10.223090 <6>[ 11.761802] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10992 09:31:10.232885 <3>[ 11.793098] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10993 09:31:10.239594 <6>[ 11.798661] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10994 09:31:10.249427 <6>[ 11.798671] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10995 09:31:10.255599 <6>[ 11.798683] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10996 09:31:10.265588 <6>[ 12.114086] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10997 09:31:10.269192 <6>[ 12.122132] pci 0000:00:00.0: PCI bridge to [bus 01]
10998 09:31:10.278938 <6>[ 12.127358] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10999 09:31:10.285565 [[0;32m OK [<6>[ 12.135558] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11000 09:31:10.292263 0m] Listening on<6>[ 12.143717] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11001 09:31:10.299288 [0;1;39mdbus.s<6>[ 12.151400] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11002 09:31:10.305318 ocket[…- D-Bus System Message Bus Socket.
11003 09:31:10.326140 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11004 09:31:10.345710 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11005 09:31:10.361331 <6>[ 12.210627] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11006 09:31:10.367304 <6>[ 12.218180] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11007 09:31:10.391342 Starting [0;1;39mdbus.service[0m - D-<6>[ 12.244222] mt7921e 0000:01:00.0: ASIC revision: 79610010
11008 09:31:10.394350 Bus System Message Bus...
11009 09:31:10.429883 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11010 09:31:10.450111 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11011 09:31:10.474456 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11012 09:31:10.494920 <6>[ 12.344800] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11013 09:31:10.498443 <6>[ 12.344800]
11014 09:31:10.527456 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11015 09:31:10.548183 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11016 09:31:10.565187 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11017 09:31:10.580936 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11018 09:31:10.600259 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11019 09:31:10.654906 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11020 09:31:10.678738 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11021 09:31:10.701069 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11022 09:31:10.721431 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11023 09:31:10.766056 [[0;32m OK [0m] Started [0;<6>[ 12.614040] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11024 09:31:10.769118 1;39mgetty@tty1.service[0m - Getty on tty1.
11025 09:31:10.832137 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11026 09:31:10.850412 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11027 09:31:10.865780 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11028 09:31:10.884760 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11029 09:31:10.935862 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11030 09:31:10.960094 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11031 09:31:10.981312 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11032 09:31:11.020911 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11033 09:31:11.058450
11034 09:31:11.062188 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11035 09:31:11.062268
11036 09:31:11.065297 debian-bookworm-arm64 login: root (automatic login)
11037 09:31:11.065380
11038 09:31:11.077932 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 18 09:11:54 UTC 2024 aarch64
11039 09:31:11.078055
11040 09:31:11.084388 The programs included with the Debian GNU/Linux system are free software;
11041 09:31:11.091045 the exact distribution terms for each program are described in the
11042 09:31:11.094516 individual files in /usr/share/doc/*/copyright.
11043 09:31:11.094595
11044 09:31:11.101308 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11045 09:31:11.104144 permitted by applicable law.
11046 09:31:11.104554 Matched prompt #10: / #
11048 09:31:11.104743 Setting prompt string to ['/ #']
11049 09:31:11.104838 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11051 09:31:11.105031 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11052 09:31:11.105116 start: 2.2.6 expect-shell-connection (timeout 00:02:46) [common]
11053 09:31:11.105183 Setting prompt string to ['/ #']
11054 09:31:11.105271 Forcing a shell prompt, looking for ['/ #']
11056 09:31:11.155481 / #
11057 09:31:11.155667 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11058 09:31:11.155756 Waiting using forced prompt support (timeout 00:02:30)
11059 09:31:11.160237
11060 09:31:11.160506 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11061 09:31:11.160600 start: 2.2.7 export-device-env (timeout 00:02:46) [common]
11062 09:31:11.160688 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11063 09:31:11.160768 end: 2.2 depthcharge-retry (duration 00:02:14) [common]
11064 09:31:11.160849 end: 2 depthcharge-action (duration 00:02:14) [common]
11065 09:31:11.160931 start: 3 lava-test-retry (timeout 00:07:24) [common]
11066 09:31:11.161011 start: 3.1 lava-test-shell (timeout 00:07:24) [common]
11067 09:31:11.161080 Using namespace: common
11069 09:31:11.261359 / # #
11070 09:31:11.261542 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11071 09:31:11.266418 #
11072 09:31:11.266673 Using /lava-14407667
11074 09:31:11.366991 / # export SHELL=/bin/sh
11075 09:31:11.372392 export SHELL=/bin/sh
11077 09:31:11.472925 / # . /lava-14407667/environment
11078 09:31:11.478463 . /lava-14407667/environment
11080 09:31:11.579018 / # /lava-14407667/bin/lava-test-runner /lava-14407667/0
11081 09:31:11.579194 Test shell timeout: 10s (minimum of the action and connection timeout)
11082 09:31:11.583974 /lava-14407667/bin/lava-test-runner /lava-14407667/0
11083 09:31:11.615087 + export TESTRUN_ID=0_v4l2-compliance-uvc
11084 09:31:11.618171 + cd /lava-14407667/0/tests/0_v4l2-compliance-uvc
11085 09:31:11.618250 + cat uuid
11086 09:31:11.621918 + UUID=14407667_1.5.2.3.1
11087 09:31:11.622017 + set +x
11088 09:31:11.628462 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 14407667_1.5.2.3.1>
11089 09:31:11.628717 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 14407667_1.5.2.3.1
11090 09:31:11.628784 Starting test lava.0_v4l2-compliance-uvc (14407667_1.5.2.3.1)
11091 09:31:11.628863 Skipping test definition patterns.
11092 09:31:11.631583 + /usr/bin/v4l2-parser.sh -d uvcvideo
11093 09:31:11.638316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11094 09:31:11.638395 device: /dev/video0
11095 09:31:11.638622 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11097 09:31:11.660294 <6>[ 13.513564] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11098 09:31:18.030713 v4l2-compliance 1.27.0-1, 64 bits, 64-bit time_t
11099 09:31:18.040638 v4l2-compliance SHA: a18611d8960f 2024-03-08 13:09:54
11100 09:31:18.048403
11101 09:31:18.065800 Compliance test for uvcvideo device /dev/video0:
11102 09:31:18.073748
11103 09:31:18.084639 Driver Info:
11104 09:31:18.094459 Driver name : uvcvideo
11105 09:31:18.111895 Card type : HD User Facing: HD User Facing
11106 09:31:18.125013 Bus info : usb-11200000.usb-1.4.1
11107 09:31:18.131790 Driver version : 6.1.92
11108 09:31:18.145442 Capabilities : 0x84a00001
11109 09:31:18.161364 Metadata Capture
11110 09:31:18.170735 Streaming
11111 09:31:18.181589 Extended Pix Format
11112 09:31:18.191745 Device Capabilities
11113 09:31:18.202078 Device Caps : 0x04200001
11114 09:31:18.218514 Streaming
11115 09:31:18.228912 Extended Pix Format
11116 09:31:18.237834 Media Driver Info:
11117 09:31:18.249395 Driver name : uvcvideo
11118 09:31:18.263200 Model : HD User Facing: HD User Facing
11119 09:31:18.270632 Serial : 200901010001
11120 09:31:18.289494 Bus info : usb-11200000.usb-1.4.1
11121 09:31:18.297580 Media version : 6.1.92
11122 09:31:18.317080 Hardware revision: 0x00009758 (38744)
11123 09:31:18.325747 Driver version : 6.1.92
11124 09:31:18.336349 Interface Info:
11125 09:31:18.351706 <LAVA_SIGNAL_TESTSET START Interface-Info>
11126 09:31:18.351793 ID : 0x03000002
11127 09:31:18.352029 Received signal: <TESTSET> START Interface-Info
11128 09:31:18.352115 Starting test_set Interface-Info
11129 09:31:18.360755 Type : V4L Video
11130 09:31:18.373008 Entity Info:
11131 09:31:18.378950 <LAVA_SIGNAL_TESTSET STOP>
11132 09:31:18.379196 Received signal: <TESTSET> STOP
11133 09:31:18.379260 Closing test_set Interface-Info
11134 09:31:18.389188 <LAVA_SIGNAL_TESTSET START Entity-Info>
11135 09:31:18.389437 Received signal: <TESTSET> START Entity-Info
11136 09:31:18.389502 Starting test_set Entity-Info
11137 09:31:18.392110 ID : 0x00000001 (1)
11138 09:31:18.402735 Name : HD User Facing: HD User Facing
11139 09:31:18.410798 Function : V4L2 I/O
11140 09:31:18.420896 Flags : default
11141 09:31:18.434903 Pad 0x01000007 : 0: Sink
11142 09:31:18.455034 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11143 09:31:18.455151
11144 09:31:18.467381 Required ioctls:
11145 09:31:18.475083 <LAVA_SIGNAL_TESTSET STOP>
11146 09:31:18.475335 Received signal: <TESTSET> STOP
11147 09:31:18.475399 Closing test_set Entity-Info
11148 09:31:18.484943 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11149 09:31:18.485190 Received signal: <TESTSET> START Required-ioctls
11150 09:31:18.485255 Starting test_set Required-ioctls
11151 09:31:18.487823 test MC information (see 'Media Driver Info' above): OK
11152 09:31:18.512524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11153 09:31:18.512774 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11155 09:31:18.515696 test VIDIOC_QUERYCAP: OK
11156 09:31:18.537858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11157 09:31:18.538104 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11159 09:31:18.541217 test invalid ioctls: OK
11160 09:31:18.562017 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11161 09:31:18.562136
11162 09:31:18.562391 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11164 09:31:18.575918 Allow for multiple opens:
11165 09:31:18.584344 <LAVA_SIGNAL_TESTSET STOP>
11166 09:31:18.584591 Received signal: <TESTSET> STOP
11167 09:31:18.584654 Closing test_set Required-ioctls
11168 09:31:18.594281 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11169 09:31:18.594526 Received signal: <TESTSET> START Allow-for-multiple-opens
11170 09:31:18.594590 Starting test_set Allow-for-multiple-opens
11171 09:31:18.597766 test second /dev/video0 open: OK
11172 09:31:18.620463 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11173 09:31:18.620711 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11175 09:31:18.623598 test VIDIOC_QUERYCAP: OK
11176 09:31:18.644091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11177 09:31:18.644356 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11179 09:31:18.647113 test VIDIOC_G/S_PRIORITY: OK
11180 09:31:18.668388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11181 09:31:18.668657 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11183 09:31:18.671739 test for unlimited opens: OK
11184 09:31:18.693029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11185 09:31:18.693117
11186 09:31:18.693375 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11188 09:31:18.704706 Debug ioctls:
11189 09:31:18.712161 <LAVA_SIGNAL_TESTSET STOP>
11190 09:31:18.712406 Received signal: <TESTSET> STOP
11191 09:31:18.712471 Closing test_set Allow-for-multiple-opens
11192 09:31:18.721294 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11193 09:31:18.721538 Received signal: <TESTSET> START Debug-ioctls
11194 09:31:18.721605 Starting test_set Debug-ioctls
11195 09:31:18.724753 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11196 09:31:18.746321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11197 09:31:18.746571 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11199 09:31:18.753011 test VIDIOC_LOG_STATUS: OK (Not Supported)
11200 09:31:18.770747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11201 09:31:18.770853
11202 09:31:18.771107 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11204 09:31:18.782137 Input ioctls:
11205 09:31:18.792390 <LAVA_SIGNAL_TESTSET STOP>
11206 09:31:18.792660 Received signal: <TESTSET> STOP
11207 09:31:18.792757 Closing test_set Debug-ioctls
11208 09:31:18.803444 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11209 09:31:18.803699 Received signal: <TESTSET> START Input-ioctls
11210 09:31:18.803777 Starting test_set Input-ioctls
11211 09:31:18.806632 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11212 09:31:18.832098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11213 09:31:18.832359 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11215 09:31:18.835135 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11216 09:31:18.853455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11217 09:31:18.853743 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11219 09:31:18.859593 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11220 09:31:18.884721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11221 09:31:18.884970 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11223 09:31:18.891490 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11224 09:31:18.909392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11225 09:31:18.909637 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11227 09:31:18.912743 test VIDIOC_G/S/ENUMINPUT: OK
11228 09:31:18.935027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11229 09:31:18.935273 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11231 09:31:18.938727 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11232 09:31:18.958637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11233 09:31:18.958887 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11235 09:31:18.961893 Inputs: 1 Audio Inputs: 0 Tuners: 0
11236 09:31:18.973817
11237 09:31:18.991093 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11238 09:31:19.015628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11239 09:31:19.015877 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11241 09:31:19.022315 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11242 09:31:19.041540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11243 09:31:19.041811 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11245 09:31:19.048271 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11246 09:31:19.066482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11247 09:31:19.066725 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11249 09:31:19.072642 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11250 09:31:19.092877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11251 09:31:19.093147 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11253 09:31:19.099633 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11254 09:31:19.118397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11255 09:31:19.118476
11256 09:31:19.118703 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11258 09:31:19.139315 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11259 09:31:19.163763 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11260 09:31:19.164015 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11262 09:31:19.170359 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11263 09:31:19.191936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11264 09:31:19.192185 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11266 09:31:19.194893 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11267 09:31:19.213358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11268 09:31:19.213604 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11270 09:31:19.216396 test VIDIOC_G/S_EDID: OK (Not Supported)
11271 09:31:19.243182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11272 09:31:19.243324
11273 09:31:19.243622 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11275 09:31:19.254916 Control ioctls (Input 0):
11276 09:31:19.261168 <LAVA_SIGNAL_TESTSET STOP>
11277 09:31:19.261414 Received signal: <TESTSET> STOP
11278 09:31:19.261476 Closing test_set Input-ioctls
11279 09:31:19.277549 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11280 09:31:19.277802 Received signal: <TESTSET> START Control-ioctls-Input-0
11281 09:31:19.277883 Starting test_set Control-ioctls-Input-0
11282 09:31:19.281103 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11283 09:31:19.306699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11284 09:31:19.306781 test VIDIOC_QUERYCTRL: OK
11285 09:31:19.307008 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11287 09:31:19.331562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11288 09:31:19.331809 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11290 09:31:19.335265 test VIDIOC_G/S_CTRL: OK
11291 09:31:19.355473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11292 09:31:19.355721 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11294 09:31:19.358495 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11295 09:31:19.380095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11296 09:31:19.380343 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11298 09:31:19.387055 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11299 09:31:19.411090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11300 09:31:19.411337 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11302 09:31:19.414005 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11303 09:31:19.433248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11304 09:31:19.433495 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11306 09:31:19.436842 Standard Controls: 16 Private Controls: 0
11307 09:31:19.442334
11308 09:31:19.457784 Format ioctls (Input 0):
11309 09:31:19.465524 <LAVA_SIGNAL_TESTSET STOP>
11310 09:31:19.465770 Received signal: <TESTSET> STOP
11311 09:31:19.465832 Closing test_set Control-ioctls-Input-0
11312 09:31:19.475229 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11313 09:31:19.475505 Received signal: <TESTSET> START Format-ioctls-Input-0
11314 09:31:19.475570 Starting test_set Format-ioctls-Input-0
11315 09:31:19.478315 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11316 09:31:19.504491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11317 09:31:19.504742 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11319 09:31:19.507332 test VIDIOC_G/S_PARM: OK
11320 09:31:19.523311 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11321 09:31:19.523560 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11323 09:31:19.526342 test VIDIOC_G_FBUF: OK (Not Supported)
11324 09:31:19.549361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11325 09:31:19.549608 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11327 09:31:19.552373 test VIDIOC_G_FMT: OK
11328 09:31:19.574140 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11329 09:31:19.574386 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11331 09:31:19.577199 test VIDIOC_TRY_FMT: OK
11332 09:31:19.599509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11333 09:31:19.599755 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11335 09:31:19.605972 warn: v4l2-test-formats.cpp(1046): Could not set fmt2
11336 09:31:19.609121 test VIDIOC_S_FMT: OK
11337 09:31:19.633719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11338 09:31:19.633972 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11340 09:31:19.636583 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11341 09:31:19.659270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11342 09:31:19.659521 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11344 09:31:19.663062 test Cropping: OK (Not Supported)
11345 09:31:19.683855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11346 09:31:19.684099 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11348 09:31:19.686981 test Composing: OK (Not Supported)
11349 09:31:19.713310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11350 09:31:19.713554 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11352 09:31:19.716323 test Scaling: OK (Not Supported)
11353 09:31:19.738433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11354 09:31:19.738514
11355 09:31:19.738740 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11357 09:31:19.748751 Codec ioctls (Input 0):
11358 09:31:19.755657 <LAVA_SIGNAL_TESTSET STOP>
11359 09:31:19.755904 Received signal: <TESTSET> STOP
11360 09:31:19.755970 Closing test_set Format-ioctls-Input-0
11361 09:31:19.765143 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11362 09:31:19.765387 Received signal: <TESTSET> START Codec-ioctls-Input-0
11363 09:31:19.765451 Starting test_set Codec-ioctls-Input-0
11364 09:31:19.768396 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11365 09:31:19.793897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11366 09:31:19.794174 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11368 09:31:19.800786 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11369 09:31:19.824832 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11370 09:31:19.825080 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11372 09:31:19.831232 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11373 09:31:19.850684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11374 09:31:19.850813
11375 09:31:19.851093 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11377 09:31:19.863457 Buffer ioctls (Input 0):
11378 09:31:19.871203 <LAVA_SIGNAL_TESTSET STOP>
11379 09:31:19.871458 Received signal: <TESTSET> STOP
11380 09:31:19.871549 Closing test_set Codec-ioctls-Input-0
11381 09:31:19.880750 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11382 09:31:19.880995 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11383 09:31:19.881058 Starting test_set Buffer-ioctls-Input-0
11384 09:31:19.883687 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11385 09:31:19.914455 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11386 09:31:19.914703 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11388 09:31:19.917326 test CREATE_BUFS maximum buffers: OK
11389 09:31:19.935310 Received signal: <TESTCASE> TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass
11391 09:31:19.938779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CREATE_BUFS-maximum-buffers RESULT=pass>
11392 09:31:19.938858 test VIDIOC_EXPBUF: OK
11393 09:31:19.960317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11394 09:31:19.960564 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11396 09:31:19.963676 test Requests: OK (Not Supported)
11397 09:31:19.990593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11398 09:31:19.990672
11399 09:31:19.990899 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11401 09:31:20.004076 Test input 0:
11402 09:31:20.015631
11403 09:31:20.025186 Streaming ioctls:
11404 09:31:20.032009 <LAVA_SIGNAL_TESTSET STOP>
11405 09:31:20.032253 Received signal: <TESTSET> STOP
11406 09:31:20.032316 Closing test_set Buffer-ioctls-Input-0
11407 09:31:20.040756 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11408 09:31:20.040999 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11409 09:31:20.041063 Starting test_set Streaming-ioctls_Test-input-0
11410 09:31:20.044387 test read/write: OK (Not Supported)
11411 09:31:20.066172 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11412 09:31:20.066445 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11414 09:31:20.069405 test blocking wait: OK
11415 09:31:20.091650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11416 09:31:20.091895 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11418 09:31:20.098849 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11419 09:31:20.104034 test MMAP (no poll): FAIL
11420 09:31:20.129865 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11421 09:31:20.130115 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11423 09:31:20.136136 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11424 09:31:20.143385 test MMAP (select): FAIL
11425 09:31:20.170354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11426 09:31:20.170601 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11428 09:31:20.177239 fail: v4l2-test-buffers.cpp(1377): node->streamon(q.g_type()) != EINVAL
11429 09:31:20.181968 test MMAP (epoll): FAIL
11430 09:31:20.205847 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11431 09:31:20.205928
11432 09:31:20.206160 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11434 09:31:20.219170
11435 09:31:20.403086
11436 09:31:20.414446 test USERPTR (no poll): OK
11437 09:31:20.440927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11438 09:31:20.441012
11439 09:31:20.441240 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11441 09:31:20.453977
11442 09:31:20.637711
11443 09:31:20.648935 test USERPTR (select): OK
11444 09:31:20.673792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11445 09:31:20.674054 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11447 09:31:20.680626 test DMABUF: Cannot test, specify --expbuf-device
11448 09:31:20.684823
11449 09:31:20.706908 Total for uvcvideo device /dev/video0: 54, Succeeded: 51, Failed: 3, Warnings: 3
11450 09:31:20.710173 <LAVA_TEST_RUNNER EXIT>
11451 09:31:20.710417 ok: lava_test_shell seems to have completed
11452 09:31:20.710487 Marking unfinished test run as failed
11454 09:31:20.711330 CREATE_BUFS-maximum-buffers:
result: pass
set: Buffer-ioctls-Input-0
Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11455 09:31:20.711455 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11456 09:31:20.711536 end: 3 lava-test-retry (duration 00:00:10) [common]
11457 09:31:20.711622 start: 4 finalize (timeout 00:07:15) [common]
11458 09:31:20.711705 start: 4.1 power-off (timeout 00:00:30) [common]
11459 09:31:20.711836 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11460 09:31:20.915543 >> Command sent successfully.
11461 09:31:20.919083 Returned 0 in 0 seconds
11462 09:31:21.019451 end: 4.1 power-off (duration 00:00:00) [common]
11464 09:31:21.019735 start: 4.2 read-feedback (timeout 00:07:14) [common]
11465 09:31:21.019959 Listened to connection for namespace 'common' for up to 1s
11466 09:31:22.020906 Finalising connection for namespace 'common'
11467 09:31:22.021075 Disconnecting from shell: Finalise
11468 09:31:22.021158 / #
11469 09:31:22.121413 end: 4.2 read-feedback (duration 00:00:01) [common]
11470 09:31:22.121553 end: 4 finalize (duration 00:00:01) [common]
11471 09:31:22.121666 Cleaning after the job
11472 09:31:22.121767 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/ramdisk
11473 09:31:22.126304 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/kernel
11474 09:31:22.139211 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/dtb
11475 09:31:22.139389 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14407667/tftp-deploy-x7pvf940/modules
11476 09:31:22.144959 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14407667
11477 09:31:22.204019 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14407667
11478 09:31:22.204182 Job finished correctly