Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 22
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 23:40:58.828794 lava-dispatcher, installed at version: 2024.03
2 23:40:58.829026 start: 0 validate
3 23:40:58.829165 Start time: 2024-06-04 23:40:58.829158+00:00 (UTC)
4 23:40:58.829294 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:40:58.829424 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230703.0%2Farm64%2Frootfs.cpio.gz exists
6 23:40:59.088709 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:40:59.088873 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:40:59.339364 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:40:59.340288 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:41:19.121712 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:41:19.121886 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:41:19.626549 validate duration: 20.80
14 23:41:19.626893 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:41:19.627041 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:41:19.627186 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:41:19.627376 Not decompressing ramdisk as can be used compressed.
18 23:41:19.627514 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230703.0/arm64/rootfs.cpio.gz
19 23:41:19.627623 saving as /var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/ramdisk/rootfs.cpio.gz
20 23:41:19.627732 total size: 8181887 (7 MB)
21 23:41:22.719561 progress 0 % (0 MB)
22 23:41:22.722204 progress 5 % (0 MB)
23 23:41:22.724494 progress 10 % (0 MB)
24 23:41:22.726881 progress 15 % (1 MB)
25 23:41:22.729106 progress 20 % (1 MB)
26 23:41:22.731585 progress 25 % (1 MB)
27 23:41:22.733839 progress 30 % (2 MB)
28 23:41:22.736176 progress 35 % (2 MB)
29 23:41:22.738377 progress 40 % (3 MB)
30 23:41:22.740785 progress 45 % (3 MB)
31 23:41:22.743013 progress 50 % (3 MB)
32 23:41:22.745371 progress 55 % (4 MB)
33 23:41:22.747507 progress 60 % (4 MB)
34 23:41:22.749825 progress 65 % (5 MB)
35 23:41:22.751980 progress 70 % (5 MB)
36 23:41:22.754348 progress 75 % (5 MB)
37 23:41:22.756633 progress 80 % (6 MB)
38 23:41:22.758980 progress 85 % (6 MB)
39 23:41:22.761344 progress 90 % (7 MB)
40 23:41:22.763916 progress 95 % (7 MB)
41 23:41:22.766136 progress 100 % (7 MB)
42 23:41:22.766347 7 MB downloaded in 3.14 s (2.49 MB/s)
43 23:41:22.766591 end: 1.1.1 http-download (duration 00:00:03) [common]
45 23:41:22.767207 end: 1.1 download-retry (duration 00:00:03) [common]
46 23:41:22.767352 start: 1.2 download-retry (timeout 00:09:57) [common]
47 23:41:22.767538 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 23:41:22.767707 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:41:22.767819 saving as /var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/kernel/Image
50 23:41:22.767915 total size: 54682112 (52 MB)
51 23:41:22.768014 No compression specified
52 23:41:22.769766 progress 0 % (0 MB)
53 23:41:22.784585 progress 5 % (2 MB)
54 23:41:22.799229 progress 10 % (5 MB)
55 23:41:22.813803 progress 15 % (7 MB)
56 23:41:22.828161 progress 20 % (10 MB)
57 23:41:22.842910 progress 25 % (13 MB)
58 23:41:22.857538 progress 30 % (15 MB)
59 23:41:22.872245 progress 35 % (18 MB)
60 23:41:22.886898 progress 40 % (20 MB)
61 23:41:22.901448 progress 45 % (23 MB)
62 23:41:22.915993 progress 50 % (26 MB)
63 23:41:22.930408 progress 55 % (28 MB)
64 23:41:22.944951 progress 60 % (31 MB)
65 23:41:22.959375 progress 65 % (33 MB)
66 23:41:22.973961 progress 70 % (36 MB)
67 23:41:22.988595 progress 75 % (39 MB)
68 23:41:23.003346 progress 80 % (41 MB)
69 23:41:23.018668 progress 85 % (44 MB)
70 23:41:23.033838 progress 90 % (46 MB)
71 23:41:23.048872 progress 95 % (49 MB)
72 23:41:23.063507 progress 100 % (52 MB)
73 23:41:23.063823 52 MB downloaded in 0.30 s (176.24 MB/s)
74 23:41:23.064034 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:41:23.064452 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:41:23.064621 start: 1.3 download-retry (timeout 00:09:57) [common]
78 23:41:23.064763 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 23:41:23.064937 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:41:23.065096 saving as /var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/dtb/mt8192-asurada-spherion-r0.dtb
81 23:41:23.065194 total size: 47258 (0 MB)
82 23:41:23.065292 No compression specified
83 23:41:23.067049 progress 69 % (0 MB)
84 23:41:23.067386 progress 100 % (0 MB)
85 23:41:23.067608 0 MB downloaded in 0.00 s (18.69 MB/s)
86 23:41:23.067754 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:41:23.068093 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:41:23.068192 start: 1.4 download-retry (timeout 00:09:57) [common]
90 23:41:23.068317 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 23:41:23.068471 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:41:23.068585 saving as /var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/modules/modules.tar
93 23:41:23.068694 total size: 8603924 (8 MB)
94 23:41:23.068792 Using unxz to decompress xz
95 23:41:23.073234 progress 0 % (0 MB)
96 23:41:23.093308 progress 5 % (0 MB)
97 23:41:23.117598 progress 10 % (0 MB)
98 23:41:23.143170 progress 15 % (1 MB)
99 23:41:23.167896 progress 20 % (1 MB)
100 23:41:23.193746 progress 25 % (2 MB)
101 23:41:23.218878 progress 30 % (2 MB)
102 23:41:23.242525 progress 35 % (2 MB)
103 23:41:23.268707 progress 40 % (3 MB)
104 23:41:23.293185 progress 45 % (3 MB)
105 23:41:23.317432 progress 50 % (4 MB)
106 23:41:23.342830 progress 55 % (4 MB)
107 23:41:23.367422 progress 60 % (4 MB)
108 23:41:23.391138 progress 65 % (5 MB)
109 23:41:23.417252 progress 70 % (5 MB)
110 23:41:23.442867 progress 75 % (6 MB)
111 23:41:23.468208 progress 80 % (6 MB)
112 23:41:23.492568 progress 85 % (7 MB)
113 23:41:23.516454 progress 90 % (7 MB)
114 23:41:23.545712 progress 95 % (7 MB)
115 23:41:23.573657 progress 100 % (8 MB)
116 23:41:23.579114 8 MB downloaded in 0.51 s (16.08 MB/s)
117 23:41:23.579370 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:41:23.579637 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:41:23.579732 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 23:41:23.579827 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 23:41:23.579912 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:41:23.580000 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 23:41:23.580270 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz
125 23:41:23.580407 makedir: /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin
126 23:41:23.580513 makedir: /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/tests
127 23:41:23.580613 makedir: /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/results
128 23:41:23.580729 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-add-keys
129 23:41:23.580876 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-add-sources
130 23:41:23.581051 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-background-process-start
131 23:41:23.581184 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-background-process-stop
132 23:41:23.581310 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-common-functions
133 23:41:23.581435 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-echo-ipv4
134 23:41:23.581561 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-install-packages
135 23:41:23.581684 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-installed-packages
136 23:41:23.581808 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-os-build
137 23:41:23.581931 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-probe-channel
138 23:41:23.582054 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-probe-ip
139 23:41:23.582216 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-target-ip
140 23:41:23.582341 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-target-mac
141 23:41:23.582468 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-target-storage
142 23:41:23.582597 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-test-case
143 23:41:23.582721 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-test-event
144 23:41:23.582844 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-test-feedback
145 23:41:23.582966 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-test-raise
146 23:41:23.583089 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-test-reference
147 23:41:23.583214 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-test-runner
148 23:41:23.583337 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-test-set
149 23:41:23.583462 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-test-shell
150 23:41:23.583589 Updating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-install-packages (oe)
151 23:41:23.583741 Updating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/bin/lava-installed-packages (oe)
152 23:41:23.583864 Creating /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/environment
153 23:41:23.583963 LAVA metadata
154 23:41:23.584034 - LAVA_JOB_ID=14172925
155 23:41:23.584113 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:41:23.584232 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 23:41:23.584299 skipped lava-vland-overlay
158 23:41:23.584372 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:41:23.584454 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 23:41:23.584519 skipped lava-multinode-overlay
161 23:41:23.584591 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:41:23.584674 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 23:41:23.584747 Loading test definitions
164 23:41:23.584840 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 23:41:23.584914 Using /lava-14172925 at stage 0
166 23:41:23.585285 uuid=14172925_1.5.2.3.1 testdef=None
167 23:41:23.585376 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:41:23.585463 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 23:41:23.585992 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:41:23.586258 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 23:41:23.586891 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:41:23.587118 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 23:41:23.587726 runner path: /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/0/tests/0_dmesg test_uuid 14172925_1.5.2.3.1
176 23:41:23.587884 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:41:23.588094 Creating lava-test-runner.conf files
179 23:41:23.588158 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14172925/lava-overlay-785oakfz/lava-14172925/0 for stage 0
180 23:41:23.588247 - 0_dmesg
181 23:41:23.588345 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:41:23.588429 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
183 23:41:23.595740 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:41:23.595861 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
185 23:41:23.595955 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:41:23.596041 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:41:23.596129 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
188 23:41:23.833502 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
189 23:41:23.833875 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
190 23:41:23.833995 extracting modules file /var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172925/extract-overlay-ramdisk-xwcuogn7/ramdisk
191 23:41:24.049455 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:41:24.049633 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
193 23:41:24.049731 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172925/compress-overlay-0otjo3pk/overlay-1.5.2.4.tar.gz to ramdisk
194 23:41:24.049800 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172925/compress-overlay-0otjo3pk/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14172925/extract-overlay-ramdisk-xwcuogn7/ramdisk
195 23:41:24.056630 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:41:24.056757 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
197 23:41:24.056853 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:41:24.056947 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
199 23:41:24.057070 Building ramdisk /var/lib/lava/dispatcher/tmp/14172925/extract-overlay-ramdisk-xwcuogn7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14172925/extract-overlay-ramdisk-xwcuogn7/ramdisk
200 23:41:24.398045 >> 145119 blocks
201 23:41:26.657799 rename /var/lib/lava/dispatcher/tmp/14172925/extract-overlay-ramdisk-xwcuogn7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/ramdisk/ramdisk.cpio.gz
202 23:41:26.658322 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
203 23:41:26.658488 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 23:41:26.658628 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 23:41:26.658775 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/kernel/Image']
206 23:41:41.141001 Returned 0 in 14 seconds
207 23:41:41.241650 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/kernel/image.itb
208 23:41:41.629830 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:41:41.630207 output: Created: Wed Jun 5 00:41:41 2024
210 23:41:41.630285 output: Image 0 (kernel-1)
211 23:41:41.630350 output: Description:
212 23:41:41.630411 output: Created: Wed Jun 5 00:41:41 2024
213 23:41:41.630471 output: Type: Kernel Image
214 23:41:41.630532 output: Compression: lzma compressed
215 23:41:41.630593 output: Data Size: 13061430 Bytes = 12755.30 KiB = 12.46 MiB
216 23:41:41.630654 output: Architecture: AArch64
217 23:41:41.630713 output: OS: Linux
218 23:41:41.630769 output: Load Address: 0x00000000
219 23:41:41.630826 output: Entry Point: 0x00000000
220 23:41:41.630883 output: Hash algo: crc32
221 23:41:41.630938 output: Hash value: ecfb5096
222 23:41:41.630996 output: Image 1 (fdt-1)
223 23:41:41.631053 output: Description: mt8192-asurada-spherion-r0
224 23:41:41.631108 output: Created: Wed Jun 5 00:41:41 2024
225 23:41:41.631162 output: Type: Flat Device Tree
226 23:41:41.631217 output: Compression: uncompressed
227 23:41:41.631269 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 23:41:41.631322 output: Architecture: AArch64
229 23:41:41.631374 output: Hash algo: crc32
230 23:41:41.631425 output: Hash value: 0f8e4d2e
231 23:41:41.631478 output: Image 2 (ramdisk-1)
232 23:41:41.631530 output: Description: unavailable
233 23:41:41.631582 output: Created: Wed Jun 5 00:41:41 2024
234 23:41:41.631674 output: Type: RAMDisk Image
235 23:41:41.631735 output: Compression: Unknown Compression
236 23:41:41.631789 output: Data Size: 21346803 Bytes = 20846.49 KiB = 20.36 MiB
237 23:41:41.631843 output: Architecture: AArch64
238 23:41:41.631896 output: OS: Linux
239 23:41:41.631949 output: Load Address: unavailable
240 23:41:41.632001 output: Entry Point: unavailable
241 23:41:41.632053 output: Hash algo: crc32
242 23:41:41.632106 output: Hash value: 4052fdaf
243 23:41:41.632158 output: Default Configuration: 'conf-1'
244 23:41:41.632210 output: Configuration 0 (conf-1)
245 23:41:41.632262 output: Description: mt8192-asurada-spherion-r0
246 23:41:41.632314 output: Kernel: kernel-1
247 23:41:41.632366 output: Init Ramdisk: ramdisk-1
248 23:41:41.632418 output: FDT: fdt-1
249 23:41:41.632471 output: Loadables: kernel-1
250 23:41:41.632522 output:
251 23:41:41.632720 end: 1.5.8.1 prepare-fit (duration 00:00:15) [common]
252 23:41:41.632821 end: 1.5.8 prepare-kernel (duration 00:00:15) [common]
253 23:41:41.632928 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 23:41:41.633034 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 23:41:41.633115 No LXC device requested
256 23:41:41.633195 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:41:41.633279 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 23:41:41.633357 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:41:41.633423 Checking files for TFTP limit of 4294967296 bytes.
260 23:41:41.633991 end: 1 tftp-deploy (duration 00:00:22) [common]
261 23:41:41.634106 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:41:41.634194 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:41:41.634320 substitutions:
264 23:41:41.634385 - {DTB}: 14172925/tftp-deploy-jxr6d2y5/dtb/mt8192-asurada-spherion-r0.dtb
265 23:41:41.634450 - {INITRD}: 14172925/tftp-deploy-jxr6d2y5/ramdisk/ramdisk.cpio.gz
266 23:41:41.634508 - {KERNEL}: 14172925/tftp-deploy-jxr6d2y5/kernel/Image
267 23:41:41.634567 - {LAVA_MAC}: None
268 23:41:41.634624 - {PRESEED_CONFIG}: None
269 23:41:41.634680 - {PRESEED_LOCAL}: None
270 23:41:41.634735 - {RAMDISK}: 14172925/tftp-deploy-jxr6d2y5/ramdisk/ramdisk.cpio.gz
271 23:41:41.634790 - {ROOT_PART}: None
272 23:41:41.634844 - {ROOT}: None
273 23:41:41.634898 - {SERVER_IP}: 192.168.201.1
274 23:41:41.634951 - {TEE}: None
275 23:41:41.635007 Parsed boot commands:
276 23:41:41.635063 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:41:41.635240 Parsed boot commands: tftpboot 192.168.201.1 14172925/tftp-deploy-jxr6d2y5/kernel/image.itb 14172925/tftp-deploy-jxr6d2y5/kernel/cmdline
278 23:41:41.635328 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:41:41.635415 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:41:41.635506 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:41:41.635591 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:41:41.635664 Not connected, no need to disconnect.
283 23:41:41.635736 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:41:41.635817 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:41:41.635884 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 23:41:41.639296 Setting prompt string to ['lava-test: # ']
287 23:41:41.639672 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:41:41.639781 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:41:41.639883 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:41:41.639973 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:41:41.640199 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 23:41:46.773875 >> Command sent successfully.
293 23:41:46.778512 Returned 0 in 5 seconds
294 23:41:46.879435 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:41:46.881151 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:41:46.881733 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:41:46.882278 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:41:46.882639 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:41:46.882988 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:41:46.884374 [Enter `^Ec?' for help]
302 23:41:47.051759
303 23:41:47.052282
304 23:41:47.052617 F0: 102B 0000
305 23:41:47.053226
306 23:41:47.053632 F3: 1001 0000 [0200]
307 23:41:47.053944
308 23:41:47.056017 F3: 1001 0000
309 23:41:47.056459
310 23:41:47.056876 F7: 102D 0000
311 23:41:47.057316
312 23:41:47.057745 F1: 0000 0000
313 23:41:47.058141
314 23:41:47.059325 V0: 0000 0000 [0001]
315 23:41:47.059754
316 23:41:47.060187 00: 0007 8000
317 23:41:47.060618
318 23:41:47.063313 01: 0000 0000
319 23:41:47.063752
320 23:41:47.064187 BP: 0C00 0209 [0000]
321 23:41:47.064594
322 23:41:47.066751 G0: 1182 0000
323 23:41:47.067190
324 23:41:47.067624 EC: 0000 0021 [4000]
325 23:41:47.068033
326 23:41:47.070106 S7: 0000 0000 [0000]
327 23:41:47.070608
328 23:41:47.071015 CC: 0000 0000 [0001]
329 23:41:47.071401
330 23:41:47.073788 T0: 0000 0040 [010F]
331 23:41:47.074181
332 23:41:47.074580 Jump to BL
333 23:41:47.074958
334 23:41:47.099409
335 23:41:47.099964
336 23:41:47.106632 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 23:41:47.110667 ARM64: Exception handlers installed.
338 23:41:47.113950 ARM64: Testing exception
339 23:41:47.114425 ARM64: Done test exception
340 23:41:47.121310 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 23:41:47.132970 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 23:41:47.140706 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 23:41:47.150287 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 23:41:47.156916 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 23:41:47.163394 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 23:41:47.175692 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 23:41:47.181964 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 23:41:47.201615 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 23:41:47.205141 WDT: Last reset was cold boot
350 23:41:47.208581 SPI1(PAD0) initialized at 2873684 Hz
351 23:41:47.211791 SPI5(PAD0) initialized at 992727 Hz
352 23:41:47.214860 VBOOT: Loading verstage.
353 23:41:47.221789 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 23:41:47.225274 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 23:41:47.228545 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 23:41:47.231979 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 23:41:47.239416 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 23:41:47.245743 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 23:41:47.257114 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
360 23:41:47.257638
361 23:41:47.257972
362 23:41:47.266889 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 23:41:47.269917 ARM64: Exception handlers installed.
364 23:41:47.273179 ARM64: Testing exception
365 23:41:47.273707 ARM64: Done test exception
366 23:41:47.280268 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 23:41:47.283627 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 23:41:47.297851 Probing TPM: . done!
369 23:41:47.298378 TPM ready after 0 ms
370 23:41:47.304384 Connected to device vid:did:rid of 1ae0:0028:00
371 23:41:47.312080 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 23:41:47.369700 Initialized TPM device CR50 revision 0
373 23:41:47.381182 tlcl_send_startup: Startup return code is 0
374 23:41:47.381686 TPM: setup succeeded
375 23:41:47.392831 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 23:41:47.401974 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 23:41:47.414504 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 23:41:47.422584 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 23:41:47.426061 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 23:41:47.433224 in-header: 03 07 00 00 08 00 00 00
381 23:41:47.436671 in-data: aa e4 47 04 13 02 00 00
382 23:41:47.439478 Chrome EC: UHEPI supported
383 23:41:47.446847 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 23:41:47.450699 in-header: 03 ad 00 00 08 00 00 00
385 23:41:47.454482 in-data: 00 20 20 08 00 00 00 00
386 23:41:47.455010 Phase 1
387 23:41:47.458240 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 23:41:47.465525 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 23:41:47.469198 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 23:41:47.473063 Recovery requested (1009000e)
391 23:41:47.481647 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 23:41:47.487111 tlcl_extend: response is 0
393 23:41:47.496655 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 23:41:47.501930 tlcl_extend: response is 0
395 23:41:47.509189 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 23:41:47.529201 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 23:41:47.536098 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 23:41:47.536620
399 23:41:47.536962
400 23:41:47.546214 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 23:41:47.549977 ARM64: Exception handlers installed.
402 23:41:47.550458 ARM64: Testing exception
403 23:41:47.553458 ARM64: Done test exception
404 23:41:47.574392 pmic_efuse_setting: Set efuses in 11 msecs
405 23:41:47.578472 pmwrap_interface_init: Select PMIF_VLD_RDY
406 23:41:47.584603 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 23:41:47.588317 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 23:41:47.594883 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 23:41:47.598773 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 23:41:47.603281 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 23:41:47.606748 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 23:41:47.614209 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 23:41:47.617939 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 23:41:47.621642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 23:41:47.625551 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 23:41:47.632606 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 23:41:47.636171 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 23:41:47.640125 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 23:41:47.647390 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 23:41:47.651430 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 23:41:47.658658 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 23:41:47.665090 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 23:41:47.669261 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 23:41:47.676854 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 23:41:47.680087 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 23:41:47.688116 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 23:41:47.691415 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 23:41:47.699050 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 23:41:47.703002 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 23:41:47.706854 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 23:41:47.714117 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 23:41:47.717776 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 23:41:47.724963 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 23:41:47.729125 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 23:41:47.732392 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 23:41:47.740151 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 23:41:47.743944 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 23:41:47.747626 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 23:41:47.755005 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 23:41:47.768075 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 23:41:47.768774 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 23:41:47.769979 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 23:41:47.773867 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 23:41:47.778006 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 23:41:47.782607 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 23:41:47.784900 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 23:41:47.792185 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 23:41:47.795731 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 23:41:47.799457 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 23:41:47.803365 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 23:41:47.807409 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 23:41:47.811214 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 23:41:47.818375 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 23:41:47.821862 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 23:41:47.825584 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 23:41:47.829208 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 23:41:47.836885 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 23:41:47.844724 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 23:41:47.851767 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 23:41:47.859430 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 23:41:47.866522 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 23:41:47.870512 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 23:41:47.874876 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 23:41:47.881910 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:41:47.889247 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x12
466 23:41:47.893035 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 23:41:47.896772 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 23:41:47.903248 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 23:41:47.911883 [RTC]rtc_get_frequency_meter,154: input=15, output=789
470 23:41:47.921344 [RTC]rtc_get_frequency_meter,154: input=23, output=978
471 23:41:47.930773 [RTC]rtc_get_frequency_meter,154: input=19, output=883
472 23:41:47.940450 [RTC]rtc_get_frequency_meter,154: input=17, output=836
473 23:41:47.949783 [RTC]rtc_get_frequency_meter,154: input=16, output=813
474 23:41:47.959063 [RTC]rtc_get_frequency_meter,154: input=15, output=790
475 23:41:47.969930 [RTC]rtc_get_frequency_meter,154: input=16, output=812
476 23:41:47.973561 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 23:41:47.976644 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 23:41:47.980401 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 23:41:47.988053 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 23:41:47.991560 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 23:41:47.995675 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 23:41:47.996091 ADC[4]: Raw value=900959 ID=7
483 23:41:47.999282 ADC[3]: Raw value=213336 ID=1
484 23:41:48.003600 RAM Code: 0x71
485 23:41:48.007529 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 23:41:48.011287 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 23:41:48.018765 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 23:41:48.025806 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 23:41:48.029016 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 23:41:48.032802 in-header: 03 07 00 00 08 00 00 00
491 23:41:48.036798 in-data: aa e4 47 04 13 02 00 00
492 23:41:48.041015 Chrome EC: UHEPI supported
493 23:41:48.047431 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 23:41:48.051828 in-header: 03 ed 00 00 08 00 00 00
495 23:41:48.052257 in-data: 80 20 60 08 00 00 00 00
496 23:41:48.055214 MRC: failed to locate region type 0.
497 23:41:48.062829 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 23:41:48.066311 DRAM-K: Running full calibration
499 23:41:48.073547 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 23:41:48.073971 header.status = 0x0
501 23:41:48.077359 header.version = 0x6 (expected: 0x6)
502 23:41:48.081355 header.size = 0xd00 (expected: 0xd00)
503 23:41:48.081777 header.flags = 0x0
504 23:41:48.088481 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 23:41:48.107307 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
506 23:41:48.114595 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 23:41:48.115037 dram_init: ddr_geometry: 2
508 23:41:48.118578 [EMI] MDL number = 2
509 23:41:48.121808 [EMI] Get MDL freq = 0
510 23:41:48.122234 dram_init: ddr_type: 0
511 23:41:48.125339 is_discrete_lpddr4: 1
512 23:41:48.129436 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 23:41:48.129953
514 23:41:48.130307
515 23:41:48.130622 [Bian_co] ETT version 0.0.0.1
516 23:41:48.137057 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 23:41:48.137565
518 23:41:48.140535 dramc_set_vcore_voltage set vcore to 650000
519 23:41:48.141147 Read voltage for 800, 4
520 23:41:48.141605 Vio18 = 0
521 23:41:48.144401 Vcore = 650000
522 23:41:48.144894 Vdram = 0
523 23:41:48.145382 Vddq = 0
524 23:41:48.147607 Vmddr = 0
525 23:41:48.148145 dram_init: config_dvfs: 1
526 23:41:48.154380 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 23:41:48.157789 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 23:41:48.160934 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 23:41:48.167802 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 23:41:48.171187 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 23:41:48.174210 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 23:41:48.177413 MEM_TYPE=3, freq_sel=18
533 23:41:48.181210 sv_algorithm_assistance_LP4_1600
534 23:41:48.184299 ============ PULL DRAM RESETB DOWN ============
535 23:41:48.188081 ========== PULL DRAM RESETB DOWN end =========
536 23:41:48.191047 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 23:41:48.194709 ===================================
538 23:41:48.197672 LPDDR4 DRAM CONFIGURATION
539 23:41:48.201161 ===================================
540 23:41:48.204789 EX_ROW_EN[0] = 0x0
541 23:41:48.205362 EX_ROW_EN[1] = 0x0
542 23:41:48.208213 LP4Y_EN = 0x0
543 23:41:48.208633 WORK_FSP = 0x0
544 23:41:48.211597 WL = 0x2
545 23:41:48.212117 RL = 0x2
546 23:41:48.214624 BL = 0x2
547 23:41:48.215044 RPST = 0x0
548 23:41:48.218413 RD_PRE = 0x0
549 23:41:48.218988 WR_PRE = 0x1
550 23:41:48.221108 WR_PST = 0x0
551 23:41:48.221551 DBI_WR = 0x0
552 23:41:48.224543 DBI_RD = 0x0
553 23:41:48.225114 OTF = 0x1
554 23:41:48.228233 ===================================
555 23:41:48.231227 ===================================
556 23:41:48.235072 ANA top config
557 23:41:48.238066 ===================================
558 23:41:48.238484 DLL_ASYNC_EN = 0
559 23:41:48.241430 ALL_SLAVE_EN = 1
560 23:41:48.244630 NEW_RANK_MODE = 1
561 23:41:48.247961 DLL_IDLE_MODE = 1
562 23:41:48.251415 LP45_APHY_COMB_EN = 1
563 23:41:48.251826 TX_ODT_DIS = 1
564 23:41:48.254615 NEW_8X_MODE = 1
565 23:41:48.257970 ===================================
566 23:41:48.261470 ===================================
567 23:41:48.264690 data_rate = 1600
568 23:41:48.268202 CKR = 1
569 23:41:48.271868 DQ_P2S_RATIO = 8
570 23:41:48.275033 ===================================
571 23:41:48.275449 CA_P2S_RATIO = 8
572 23:41:48.278663 DQ_CA_OPEN = 0
573 23:41:48.281599 DQ_SEMI_OPEN = 0
574 23:41:48.284843 CA_SEMI_OPEN = 0
575 23:41:48.288778 CA_FULL_RATE = 0
576 23:41:48.289294 DQ_CKDIV4_EN = 1
577 23:41:48.291761 CA_CKDIV4_EN = 1
578 23:41:48.295072 CA_PREDIV_EN = 0
579 23:41:48.298931 PH8_DLY = 0
580 23:41:48.301770 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 23:41:48.305147 DQ_AAMCK_DIV = 4
582 23:41:48.305659 CA_AAMCK_DIV = 4
583 23:41:48.309113 CA_ADMCK_DIV = 4
584 23:41:48.312214 DQ_TRACK_CA_EN = 0
585 23:41:48.315079 CA_PICK = 800
586 23:41:48.318514 CA_MCKIO = 800
587 23:41:48.321911 MCKIO_SEMI = 0
588 23:41:48.325763 PLL_FREQ = 3068
589 23:41:48.326184 DQ_UI_PI_RATIO = 32
590 23:41:48.329858 CA_UI_PI_RATIO = 0
591 23:41:48.333266 ===================================
592 23:41:48.336941 ===================================
593 23:41:48.337393 memory_type:LPDDR4
594 23:41:48.341284 GP_NUM : 10
595 23:41:48.344262 SRAM_EN : 1
596 23:41:48.344870 MD32_EN : 0
597 23:41:48.348171 ===================================
598 23:41:48.351734 [ANA_INIT] >>>>>>>>>>>>>>
599 23:41:48.352327 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 23:41:48.355455 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 23:41:48.359434 ===================================
602 23:41:48.362616 data_rate = 1600,PCW = 0X7600
603 23:41:48.365989 ===================================
604 23:41:48.369057 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 23:41:48.376042 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 23:41:48.379548 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:41:48.386658 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 23:41:48.389660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 23:41:48.392649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:41:48.393201 [ANA_INIT] flow start
611 23:41:48.396108 [ANA_INIT] PLL >>>>>>>>
612 23:41:48.399551 [ANA_INIT] PLL <<<<<<<<
613 23:41:48.399964 [ANA_INIT] MIDPI >>>>>>>>
614 23:41:48.402687 [ANA_INIT] MIDPI <<<<<<<<
615 23:41:48.406323 [ANA_INIT] DLL >>>>>>>>
616 23:41:48.406971 [ANA_INIT] flow end
617 23:41:48.409503 ============ LP4 DIFF to SE enter ============
618 23:41:48.416587 ============ LP4 DIFF to SE exit ============
619 23:41:48.417253 [ANA_INIT] <<<<<<<<<<<<<
620 23:41:48.419364 [Flow] Enable top DCM control >>>>>
621 23:41:48.423222 [Flow] Enable top DCM control <<<<<
622 23:41:48.426505 Enable DLL master slave shuffle
623 23:41:48.433147 ==============================================================
624 23:41:48.433567 Gating Mode config
625 23:41:48.440122 ==============================================================
626 23:41:48.443016 Config description:
627 23:41:48.453126 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 23:41:48.459530 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 23:41:48.463200 SELPH_MODE 0: By rank 1: By Phase
630 23:41:48.470194 ==============================================================
631 23:41:48.470612 GAT_TRACK_EN = 1
632 23:41:48.473477 RX_GATING_MODE = 2
633 23:41:48.476609 RX_GATING_TRACK_MODE = 2
634 23:41:48.479752 SELPH_MODE = 1
635 23:41:48.483213 PICG_EARLY_EN = 1
636 23:41:48.486515 VALID_LAT_VALUE = 1
637 23:41:48.493473 ==============================================================
638 23:41:48.496710 Enter into Gating configuration >>>>
639 23:41:48.500422 Exit from Gating configuration <<<<
640 23:41:48.503302 Enter into DVFS_PRE_config >>>>>
641 23:41:48.513512 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 23:41:48.517166 Exit from DVFS_PRE_config <<<<<
643 23:41:48.520841 Enter into PICG configuration >>>>
644 23:41:48.523338 Exit from PICG configuration <<<<
645 23:41:48.523960 [RX_INPUT] configuration >>>>>
646 23:41:48.527004 [RX_INPUT] configuration <<<<<
647 23:41:48.534167 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 23:41:48.537399 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 23:41:48.544230 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 23:41:48.551468 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 23:41:48.557566 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 23:41:48.564292 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 23:41:48.568200 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 23:41:48.571537 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 23:41:48.574343 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 23:41:48.581238 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 23:41:48.584673 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 23:41:48.588027 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 23:41:48.591551 ===================================
660 23:41:48.595016 LPDDR4 DRAM CONFIGURATION
661 23:41:48.598529 ===================================
662 23:41:48.598973 EX_ROW_EN[0] = 0x0
663 23:41:48.602242 EX_ROW_EN[1] = 0x0
664 23:41:48.602668 LP4Y_EN = 0x0
665 23:41:48.604753 WORK_FSP = 0x0
666 23:41:48.605248 WL = 0x2
667 23:41:48.608022 RL = 0x2
668 23:41:48.608449 BL = 0x2
669 23:41:48.611534 RPST = 0x0
670 23:41:48.611960 RD_PRE = 0x0
671 23:41:48.614810 WR_PRE = 0x1
672 23:41:48.615421 WR_PST = 0x0
673 23:41:48.618337 DBI_WR = 0x0
674 23:41:48.618763 DBI_RD = 0x0
675 23:41:48.621844 OTF = 0x1
676 23:41:48.624964 ===================================
677 23:41:48.628319 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 23:41:48.631709 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 23:41:48.638742 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 23:41:48.642297 ===================================
681 23:41:48.642728 LPDDR4 DRAM CONFIGURATION
682 23:41:48.645876 ===================================
683 23:41:48.648536 EX_ROW_EN[0] = 0x10
684 23:41:48.652674 EX_ROW_EN[1] = 0x0
685 23:41:48.653141 LP4Y_EN = 0x0
686 23:41:48.655595 WORK_FSP = 0x0
687 23:41:48.656023 WL = 0x2
688 23:41:48.659079 RL = 0x2
689 23:41:48.659510 BL = 0x2
690 23:41:48.662878 RPST = 0x0
691 23:41:48.663415 RD_PRE = 0x0
692 23:41:48.665329 WR_PRE = 0x1
693 23:41:48.665756 WR_PST = 0x0
694 23:41:48.668942 DBI_WR = 0x0
695 23:41:48.669410 DBI_RD = 0x0
696 23:41:48.672450 OTF = 0x1
697 23:41:48.675951 ===================================
698 23:41:48.682352 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 23:41:48.685843 nWR fixed to 40
700 23:41:48.686384 [ModeRegInit_LP4] CH0 RK0
701 23:41:48.689497 [ModeRegInit_LP4] CH0 RK1
702 23:41:48.693012 [ModeRegInit_LP4] CH1 RK0
703 23:41:48.693550 [ModeRegInit_LP4] CH1 RK1
704 23:41:48.696188 match AC timing 13
705 23:41:48.699563 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 23:41:48.702430 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 23:41:48.709533 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 23:41:48.712357 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 23:41:48.719145 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 23:41:48.719567 [EMI DOE] emi_dcm 0
711 23:41:48.722348 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 23:41:48.722767 ==
713 23:41:48.725727 Dram Type= 6, Freq= 0, CH_0, rank 0
714 23:41:48.732782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 23:41:48.733253 ==
716 23:41:48.736743 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 23:41:48.742419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 23:41:48.752376 [CA 0] Center 37 (7~68) winsize 62
719 23:41:48.755619 [CA 1] Center 37 (6~68) winsize 63
720 23:41:48.758855 [CA 2] Center 35 (5~66) winsize 62
721 23:41:48.762136 [CA 3] Center 34 (4~65) winsize 62
722 23:41:48.765503 [CA 4] Center 34 (4~65) winsize 62
723 23:41:48.769145 [CA 5] Center 33 (3~64) winsize 62
724 23:41:48.769765
725 23:41:48.772649 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 23:41:48.773261
727 23:41:48.776016 [CATrainingPosCal] consider 1 rank data
728 23:41:48.778933 u2DelayCellTimex100 = 270/100 ps
729 23:41:48.782363 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
730 23:41:48.785665 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
731 23:41:48.792606 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
732 23:41:48.795526 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
733 23:41:48.799137 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
734 23:41:48.802619 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
735 23:41:48.803140
736 23:41:48.805971 CA PerBit enable=1, Macro0, CA PI delay=33
737 23:41:48.806401
738 23:41:48.808927 [CBTSetCACLKResult] CA Dly = 33
739 23:41:48.809395 CS Dly: 5 (0~36)
740 23:41:48.809730 ==
741 23:41:48.812370 Dram Type= 6, Freq= 0, CH_0, rank 1
742 23:41:48.818833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 23:41:48.819253 ==
744 23:41:48.822422 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 23:41:48.828947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 23:41:48.838271 [CA 0] Center 37 (6~68) winsize 63
747 23:41:48.841459 [CA 1] Center 37 (6~68) winsize 63
748 23:41:48.844824 [CA 2] Center 35 (5~66) winsize 62
749 23:41:48.848786 [CA 3] Center 35 (4~66) winsize 63
750 23:41:48.851940 [CA 4] Center 34 (3~65) winsize 63
751 23:41:48.855403 [CA 5] Center 33 (3~64) winsize 62
752 23:41:48.855975
753 23:41:48.858711 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 23:41:48.859280
755 23:41:48.861868 [CATrainingPosCal] consider 2 rank data
756 23:41:48.865333 u2DelayCellTimex100 = 270/100 ps
757 23:41:48.868601 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
758 23:41:48.872014 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
759 23:41:48.875161 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
760 23:41:48.882389 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
761 23:41:48.885627 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
762 23:41:48.888618 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
763 23:41:48.889201
764 23:41:48.892091 CA PerBit enable=1, Macro0, CA PI delay=33
765 23:41:48.892542
766 23:41:48.895030 [CBTSetCACLKResult] CA Dly = 33
767 23:41:48.895623 CS Dly: 6 (0~38)
768 23:41:48.896128
769 23:41:48.899115 ----->DramcWriteLeveling(PI) begin...
770 23:41:48.899721 ==
771 23:41:48.901929 Dram Type= 6, Freq= 0, CH_0, rank 0
772 23:41:48.909510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 23:41:48.909969 ==
774 23:41:48.910349 Write leveling (Byte 0): 30 => 30
775 23:41:48.912913 Write leveling (Byte 1): 30 => 30
776 23:41:48.916824 DramcWriteLeveling(PI) end<-----
777 23:41:48.917416
778 23:41:48.917830 ==
779 23:41:48.921112 Dram Type= 6, Freq= 0, CH_0, rank 0
780 23:41:48.924463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 23:41:48.925089 ==
782 23:41:48.927683 [Gating] SW mode calibration
783 23:41:48.935249 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 23:41:48.938552 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 23:41:48.945259 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 23:41:48.948833 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:41:48.951889 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 23:41:48.958784 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 23:41:48.962023 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:41:48.965549 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:41:48.968641 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:41:48.975541 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:41:48.979447 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:41:48.981972 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:41:48.989098 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:41:48.992645 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:41:48.995703 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:41:49.002677 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:41:49.006165 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:41:49.009559 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:41:49.016441 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:41:49.019730 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 23:41:49.023166 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 23:41:49.029313 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 23:41:49.033052 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:41:49.036410 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:41:49.039808 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:41:49.046546 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:41:49.049703 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:41:49.053346 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:41:49.060022 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:41:49.063402 0 9 12 | B1->B0 | 2929 3434 | 1 0 | (1 1) (0 0)
813 23:41:49.066827 0 9 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
814 23:41:49.073622 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:41:49.076598 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:41:49.080379 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:41:49.083733 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:41:49.090078 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:41:49.093175 0 10 8 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
820 23:41:49.096890 0 10 12 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (0 0)
821 23:41:49.103416 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 23:41:49.106949 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:41:49.110753 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:41:49.117040 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:41:49.120286 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:41:49.123581 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:41:49.130608 0 11 8 | B1->B0 | 2424 2f2f | 0 1 | (0 0) (0 0)
828 23:41:49.133576 0 11 12 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
829 23:41:49.137081 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
830 23:41:49.143931 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:41:49.147558 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:41:49.150687 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:41:49.154169 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:41:49.160491 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:41:49.163969 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
836 23:41:49.167331 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 23:41:49.173781 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:41:49.176898 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:41:49.180765 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:41:49.186942 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:41:49.190717 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:41:49.193991 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:41:49.200507 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:41:49.204272 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:41:49.207117 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:41:49.213785 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:41:49.217382 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:41:49.220834 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:41:49.224287 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:41:49.231041 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:41:49.233817 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 23:41:49.237686 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 23:41:49.240823 Total UI for P1: 0, mck2ui 16
854 23:41:49.244512 best dqsien dly found for B0: ( 0, 14, 8)
855 23:41:49.247958 Total UI for P1: 0, mck2ui 16
856 23:41:49.251111 best dqsien dly found for B1: ( 0, 14, 8)
857 23:41:49.254802 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
858 23:41:49.257612 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 23:41:49.258157
860 23:41:49.260747 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
861 23:41:49.267825 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 23:41:49.268345 [Gating] SW calibration Done
863 23:41:49.268687 ==
864 23:41:49.271441 Dram Type= 6, Freq= 0, CH_0, rank 0
865 23:41:49.277731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 23:41:49.278254 ==
867 23:41:49.278597 RX Vref Scan: 0
868 23:41:49.278917
869 23:41:49.281191 RX Vref 0 -> 0, step: 1
870 23:41:49.281703
871 23:41:49.284456 RX Delay -130 -> 252, step: 16
872 23:41:49.287799 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
873 23:41:49.291509 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
874 23:41:49.294528 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
875 23:41:49.301136 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
876 23:41:49.304597 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
877 23:41:49.308340 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
878 23:41:49.311197 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
879 23:41:49.314729 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
880 23:41:49.317884 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
881 23:41:49.324831 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
882 23:41:49.327991 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
883 23:41:49.331221 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
884 23:41:49.334731 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
885 23:41:49.337727 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
886 23:41:49.344673 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
887 23:41:49.348340 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
888 23:41:49.348855 ==
889 23:41:49.351495 Dram Type= 6, Freq= 0, CH_0, rank 0
890 23:41:49.355089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 23:41:49.355613 ==
892 23:41:49.358453 DQS Delay:
893 23:41:49.358876 DQS0 = 0, DQS1 = 0
894 23:41:49.359216 DQM Delay:
895 23:41:49.361228 DQM0 = 85, DQM1 = 77
896 23:41:49.361679 DQ Delay:
897 23:41:49.365229 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
898 23:41:49.368661 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =85
899 23:41:49.371570 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
900 23:41:49.374727 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
901 23:41:49.375150
902 23:41:49.375486
903 23:41:49.375797 ==
904 23:41:49.378094 Dram Type= 6, Freq= 0, CH_0, rank 0
905 23:41:49.384920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 23:41:49.385464 ==
907 23:41:49.385807
908 23:41:49.386119
909 23:41:49.386417 TX Vref Scan disable
910 23:41:49.388148 == TX Byte 0 ==
911 23:41:49.391876 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
912 23:41:49.395406 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
913 23:41:49.398110 == TX Byte 1 ==
914 23:41:49.401363 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
915 23:41:49.404715 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
916 23:41:49.408315 ==
917 23:41:49.411807 Dram Type= 6, Freq= 0, CH_0, rank 0
918 23:41:49.414826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 23:41:49.415393 ==
920 23:41:49.427327 TX Vref=22, minBit 5, minWin=27, winSum=439
921 23:41:49.430722 TX Vref=24, minBit 5, minWin=27, winSum=444
922 23:41:49.433879 TX Vref=26, minBit 3, minWin=27, winSum=445
923 23:41:49.437260 TX Vref=28, minBit 12, minWin=27, winSum=451
924 23:41:49.440820 TX Vref=30, minBit 2, minWin=28, winSum=454
925 23:41:49.443875 TX Vref=32, minBit 2, minWin=28, winSum=455
926 23:41:49.450480 [TxChooseVref] Worse bit 2, Min win 28, Win sum 455, Final Vref 32
927 23:41:49.450904
928 23:41:49.453812 Final TX Range 1 Vref 32
929 23:41:49.454250
930 23:41:49.454619 ==
931 23:41:49.457264 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:41:49.460845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 23:41:49.461528 ==
934 23:41:49.461920
935 23:41:49.462242
936 23:41:49.463980 TX Vref Scan disable
937 23:41:49.467244 == TX Byte 0 ==
938 23:41:49.470944 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
939 23:41:49.474267 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
940 23:41:49.477713 == TX Byte 1 ==
941 23:41:49.480833 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
942 23:41:49.484389 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
943 23:41:49.484811
944 23:41:49.487667 [DATLAT]
945 23:41:49.488132 Freq=800, CH0 RK0
946 23:41:49.488482
947 23:41:49.491271 DATLAT Default: 0xa
948 23:41:49.491783 0, 0xFFFF, sum = 0
949 23:41:49.494753 1, 0xFFFF, sum = 0
950 23:41:49.495266 2, 0xFFFF, sum = 0
951 23:41:49.497606 3, 0xFFFF, sum = 0
952 23:41:49.498029 4, 0xFFFF, sum = 0
953 23:41:49.500843 5, 0xFFFF, sum = 0
954 23:41:49.501569 6, 0xFFFF, sum = 0
955 23:41:49.504481 7, 0xFFFF, sum = 0
956 23:41:49.504931 8, 0x0, sum = 1
957 23:41:49.508007 9, 0x0, sum = 2
958 23:41:49.508443 10, 0x0, sum = 3
959 23:41:49.511016 11, 0x0, sum = 4
960 23:41:49.511424 best_step = 9
961 23:41:49.511799
962 23:41:49.512139 ==
963 23:41:49.514268 Dram Type= 6, Freq= 0, CH_0, rank 0
964 23:41:49.518012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
965 23:41:49.520863 ==
966 23:41:49.521359 RX Vref Scan: 1
967 23:41:49.521704
968 23:41:49.524876 Set Vref Range= 32 -> 127
969 23:41:49.525377
970 23:41:49.525756 RX Vref 32 -> 127, step: 1
971 23:41:49.526091
972 23:41:49.527763 RX Delay -95 -> 252, step: 8
973 23:41:49.528121
974 23:41:49.531145 Set Vref, RX VrefLevel [Byte0]: 32
975 23:41:49.534970 [Byte1]: 32
976 23:41:49.538061
977 23:41:49.538500 Set Vref, RX VrefLevel [Byte0]: 33
978 23:41:49.541644 [Byte1]: 33
979 23:41:49.546554
980 23:41:49.546980 Set Vref, RX VrefLevel [Byte0]: 34
981 23:41:49.549579 [Byte1]: 34
982 23:41:49.553377
983 23:41:49.553839 Set Vref, RX VrefLevel [Byte0]: 35
984 23:41:49.556617 [Byte1]: 35
985 23:41:49.561042
986 23:41:49.561474 Set Vref, RX VrefLevel [Byte0]: 36
987 23:41:49.564080 [Byte1]: 36
988 23:41:49.568399
989 23:41:49.569073 Set Vref, RX VrefLevel [Byte0]: 37
990 23:41:49.571878 [Byte1]: 37
991 23:41:49.576049
992 23:41:49.576494 Set Vref, RX VrefLevel [Byte0]: 38
993 23:41:49.579494 [Byte1]: 38
994 23:41:49.584105
995 23:41:49.584526 Set Vref, RX VrefLevel [Byte0]: 39
996 23:41:49.587505 [Byte1]: 39
997 23:41:49.591322
998 23:41:49.591903 Set Vref, RX VrefLevel [Byte0]: 40
999 23:41:49.594762 [Byte1]: 40
1000 23:41:49.599395
1001 23:41:49.599854 Set Vref, RX VrefLevel [Byte0]: 41
1002 23:41:49.602451 [Byte1]: 41
1003 23:41:49.606822
1004 23:41:49.607633 Set Vref, RX VrefLevel [Byte0]: 42
1005 23:41:49.610292 [Byte1]: 42
1006 23:41:49.614391
1007 23:41:49.614841 Set Vref, RX VrefLevel [Byte0]: 43
1008 23:41:49.617241 [Byte1]: 43
1009 23:41:49.621506
1010 23:41:49.622042 Set Vref, RX VrefLevel [Byte0]: 44
1011 23:41:49.625079 [Byte1]: 44
1012 23:41:49.629125
1013 23:41:49.629550 Set Vref, RX VrefLevel [Byte0]: 45
1014 23:41:49.632564 [Byte1]: 45
1015 23:41:49.636950
1016 23:41:49.637582 Set Vref, RX VrefLevel [Byte0]: 46
1017 23:41:49.640126 [Byte1]: 46
1018 23:41:49.644749
1019 23:41:49.645361 Set Vref, RX VrefLevel [Byte0]: 47
1020 23:41:49.647668 [Byte1]: 47
1021 23:41:49.652192
1022 23:41:49.652609 Set Vref, RX VrefLevel [Byte0]: 48
1023 23:41:49.655564 [Byte1]: 48
1024 23:41:49.659644
1025 23:41:49.660081 Set Vref, RX VrefLevel [Byte0]: 49
1026 23:41:49.662773 [Byte1]: 49
1027 23:41:49.667543
1028 23:41:49.667999 Set Vref, RX VrefLevel [Byte0]: 50
1029 23:41:49.670812 [Byte1]: 50
1030 23:41:49.674926
1031 23:41:49.675343 Set Vref, RX VrefLevel [Byte0]: 51
1032 23:41:49.678434 [Byte1]: 51
1033 23:41:49.682279
1034 23:41:49.682747 Set Vref, RX VrefLevel [Byte0]: 52
1035 23:41:49.685781 [Byte1]: 52
1036 23:41:49.689898
1037 23:41:49.690310 Set Vref, RX VrefLevel [Byte0]: 53
1038 23:41:49.693096 [Byte1]: 53
1039 23:41:49.697531
1040 23:41:49.697998 Set Vref, RX VrefLevel [Byte0]: 54
1041 23:41:49.700873 [Byte1]: 54
1042 23:41:49.705153
1043 23:41:49.705623 Set Vref, RX VrefLevel [Byte0]: 55
1044 23:41:49.708600 [Byte1]: 55
1045 23:41:49.712489
1046 23:41:49.712883 Set Vref, RX VrefLevel [Byte0]: 56
1047 23:41:49.715771 [Byte1]: 56
1048 23:41:49.720504
1049 23:41:49.720916 Set Vref, RX VrefLevel [Byte0]: 57
1050 23:41:49.723568 [Byte1]: 57
1051 23:41:49.727979
1052 23:41:49.728389 Set Vref, RX VrefLevel [Byte0]: 58
1053 23:41:49.731085 [Byte1]: 58
1054 23:41:49.735501
1055 23:41:49.735976 Set Vref, RX VrefLevel [Byte0]: 59
1056 23:41:49.739066 [Byte1]: 59
1057 23:41:49.743013
1058 23:41:49.743487 Set Vref, RX VrefLevel [Byte0]: 60
1059 23:41:49.746407 [Byte1]: 60
1060 23:41:49.751053
1061 23:41:49.751443 Set Vref, RX VrefLevel [Byte0]: 61
1062 23:41:49.753912 [Byte1]: 61
1063 23:41:49.758396
1064 23:41:49.758845 Set Vref, RX VrefLevel [Byte0]: 62
1065 23:41:49.761795 [Byte1]: 62
1066 23:41:49.765711
1067 23:41:49.766238 Set Vref, RX VrefLevel [Byte0]: 63
1068 23:41:49.769703 [Byte1]: 63
1069 23:41:49.773793
1070 23:41:49.774216 Set Vref, RX VrefLevel [Byte0]: 64
1071 23:41:49.776767 [Byte1]: 64
1072 23:41:49.781275
1073 23:41:49.781765 Set Vref, RX VrefLevel [Byte0]: 65
1074 23:41:49.784543 [Byte1]: 65
1075 23:41:49.788538
1076 23:41:49.788947 Set Vref, RX VrefLevel [Byte0]: 66
1077 23:41:49.792211 [Byte1]: 66
1078 23:41:49.796137
1079 23:41:49.796630 Set Vref, RX VrefLevel [Byte0]: 67
1080 23:41:49.799666 [Byte1]: 67
1081 23:41:49.803991
1082 23:41:49.804519 Set Vref, RX VrefLevel [Byte0]: 68
1083 23:41:49.807641 [Byte1]: 68
1084 23:41:49.811838
1085 23:41:49.812253 Set Vref, RX VrefLevel [Byte0]: 69
1086 23:41:49.814616 [Byte1]: 69
1087 23:41:49.818989
1088 23:41:49.819458 Set Vref, RX VrefLevel [Byte0]: 70
1089 23:41:49.822278 [Byte1]: 70
1090 23:41:49.826936
1091 23:41:49.827432 Set Vref, RX VrefLevel [Byte0]: 71
1092 23:41:49.829837 [Byte1]: 71
1093 23:41:49.833976
1094 23:41:49.834390 Set Vref, RX VrefLevel [Byte0]: 72
1095 23:41:49.838023 [Byte1]: 72
1096 23:41:49.842188
1097 23:41:49.842644 Set Vref, RX VrefLevel [Byte0]: 73
1098 23:41:49.845007 [Byte1]: 73
1099 23:41:49.849845
1100 23:41:49.850349 Set Vref, RX VrefLevel [Byte0]: 74
1101 23:41:49.853181 [Byte1]: 74
1102 23:41:49.857144
1103 23:41:49.857563 Set Vref, RX VrefLevel [Byte0]: 75
1104 23:41:49.860180 [Byte1]: 75
1105 23:41:49.864533
1106 23:41:49.864942 Set Vref, RX VrefLevel [Byte0]: 76
1107 23:41:49.867960 [Byte1]: 76
1108 23:41:49.872305
1109 23:41:49.872809 Set Vref, RX VrefLevel [Byte0]: 77
1110 23:41:49.875645 [Byte1]: 77
1111 23:41:49.880220
1112 23:41:49.880722 Set Vref, RX VrefLevel [Byte0]: 78
1113 23:41:49.883206 [Byte1]: 78
1114 23:41:49.887947
1115 23:41:49.888584 Set Vref, RX VrefLevel [Byte0]: 79
1116 23:41:49.890773 [Byte1]: 79
1117 23:41:49.895142
1118 23:41:49.895607 Final RX Vref Byte 0 = 65 to rank0
1119 23:41:49.898673 Final RX Vref Byte 1 = 57 to rank0
1120 23:41:49.901914 Final RX Vref Byte 0 = 65 to rank1
1121 23:41:49.905138 Final RX Vref Byte 1 = 57 to rank1==
1122 23:41:49.908963 Dram Type= 6, Freq= 0, CH_0, rank 0
1123 23:41:49.911828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1124 23:41:49.915397 ==
1125 23:41:49.915811 DQS Delay:
1126 23:41:49.916204 DQS0 = 0, DQS1 = 0
1127 23:41:49.918589 DQM Delay:
1128 23:41:49.919073 DQM0 = 87, DQM1 = 79
1129 23:41:49.922176 DQ Delay:
1130 23:41:49.922694 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1131 23:41:49.925144 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =92
1132 23:41:49.928594 DQ8 =68, DQ9 =64, DQ10 =84, DQ11 =76
1133 23:41:49.931664 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1134 23:41:49.935031
1135 23:41:49.935497
1136 23:41:49.941450 [DQSOSCAuto] RK0, (LSB)MR18= 0x2910, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1137 23:41:49.944706 CH0 RK0: MR19=606, MR18=2910
1138 23:41:49.951929 CH0_RK0: MR19=0x606, MR18=0x2910, DQSOSC=399, MR23=63, INC=92, DEC=61
1139 23:41:49.952340
1140 23:41:49.954783 ----->DramcWriteLeveling(PI) begin...
1141 23:41:49.955233 ==
1142 23:41:49.958320 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 23:41:49.961970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 23:41:49.962379 ==
1145 23:41:49.965111 Write leveling (Byte 0): 30 => 30
1146 23:41:49.968956 Write leveling (Byte 1): 30 => 30
1147 23:41:49.971829 DramcWriteLeveling(PI) end<-----
1148 23:41:49.972233
1149 23:41:49.972571 ==
1150 23:41:49.975150 Dram Type= 6, Freq= 0, CH_0, rank 1
1151 23:41:49.978248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1152 23:41:49.978701 ==
1153 23:41:49.981791 [Gating] SW mode calibration
1154 23:41:50.029435 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1155 23:41:50.029853 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1156 23:41:50.030539 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 23:41:50.030998 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1158 23:41:50.031504 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1159 23:41:50.031875 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:41:50.032289 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:41:50.032678 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:41:50.033199 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:41:50.033683 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:41:50.037491 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:41:50.040848 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:41:50.044057 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:41:50.047528 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:41:50.050867 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:41:50.054633 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:41:50.061094 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:41:50.064758 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:41:50.067757 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:41:50.074532 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1174 23:41:50.077640 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1175 23:41:50.081077 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1176 23:41:50.088021 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:41:50.091277 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:41:50.094460 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 23:41:50.098255 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 23:41:50.104238 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 23:41:50.107917 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1182 23:41:50.110966 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
1183 23:41:50.117719 0 9 12 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
1184 23:41:50.121210 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 23:41:50.124675 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 23:41:50.131331 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 23:41:50.134880 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 23:41:50.138348 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 23:41:50.145124 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
1190 23:41:50.148004 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
1191 23:41:50.151425 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1192 23:41:50.158579 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 23:41:50.162678 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 23:41:50.166151 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 23:41:50.170016 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 23:41:50.173374 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 23:41:50.180327 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
1198 23:41:50.183775 0 11 8 | B1->B0 | 2b2b 4242 | 0 0 | (0 0) (0 0)
1199 23:41:50.187190 0 11 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1200 23:41:50.190588 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 23:41:50.197480 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 23:41:50.200970 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 23:41:50.204397 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 23:41:50.210775 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 23:41:50.213927 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 23:41:50.218077 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1207 23:41:50.220893 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1208 23:41:50.227481 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:41:50.231080 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:41:50.234433 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:41:50.241076 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:41:50.244497 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:41:50.247748 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:41:50.254518 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:41:50.258097 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:41:50.261388 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:41:50.268422 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 23:41:50.271649 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 23:41:50.274633 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 23:41:50.278416 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 23:41:50.284735 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1222 23:41:50.288363 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1223 23:41:50.292020 Total UI for P1: 0, mck2ui 16
1224 23:41:50.295389 best dqsien dly found for B0: ( 0, 14, 4)
1225 23:41:50.298469 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1226 23:41:50.301798 Total UI for P1: 0, mck2ui 16
1227 23:41:50.305095 best dqsien dly found for B1: ( 0, 14, 8)
1228 23:41:50.308814 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1229 23:41:50.312371 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1230 23:41:50.312789
1231 23:41:50.315041 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1232 23:41:50.318455 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1233 23:41:50.322525 [Gating] SW calibration Done
1234 23:41:50.322944 ==
1235 23:41:50.325583 Dram Type= 6, Freq= 0, CH_0, rank 1
1236 23:41:50.332076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1237 23:41:50.332533 ==
1238 23:41:50.332959 RX Vref Scan: 0
1239 23:41:50.333395
1240 23:41:50.335581 RX Vref 0 -> 0, step: 1
1241 23:41:50.336003
1242 23:41:50.338973 RX Delay -130 -> 252, step: 16
1243 23:41:50.342302 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1244 23:41:50.345671 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1245 23:41:50.348950 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1246 23:41:50.352203 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1247 23:41:50.358909 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1248 23:41:50.362496 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1249 23:41:50.365466 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1250 23:41:50.369056 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1251 23:41:50.372296 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1252 23:41:50.375661 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1253 23:41:50.382489 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1254 23:41:50.385868 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1255 23:41:50.389108 iDelay=206, Bit 12, Center 69 (-50 ~ 189) 240
1256 23:41:50.392881 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1257 23:41:50.399148 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1258 23:41:50.402373 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1259 23:41:50.402793 ==
1260 23:41:50.405996 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 23:41:50.409040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1262 23:41:50.409461 ==
1263 23:41:50.409882 DQS Delay:
1264 23:41:50.412876 DQS0 = 0, DQS1 = 0
1265 23:41:50.413395 DQM Delay:
1266 23:41:50.415934 DQM0 = 85, DQM1 = 75
1267 23:41:50.416427 DQ Delay:
1268 23:41:50.419476 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1269 23:41:50.422634 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1270 23:41:50.426058 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1271 23:41:50.428919 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1272 23:41:50.429791
1273 23:41:50.430398
1274 23:41:50.430860 ==
1275 23:41:50.432592 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 23:41:50.436053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 23:41:50.436470 ==
1278 23:41:50.439628
1279 23:41:50.440042
1280 23:41:50.440366 TX Vref Scan disable
1281 23:41:50.442937 == TX Byte 0 ==
1282 23:41:50.445791 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1283 23:41:50.449256 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1284 23:41:50.452829 == TX Byte 1 ==
1285 23:41:50.456176 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1286 23:41:50.459513 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1287 23:41:50.459925 ==
1288 23:41:50.462464 Dram Type= 6, Freq= 0, CH_0, rank 1
1289 23:41:50.469161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1290 23:41:50.469592 ==
1291 23:41:50.480847 TX Vref=22, minBit 3, minWin=27, winSum=445
1292 23:41:50.484399 TX Vref=24, minBit 3, minWin=27, winSum=445
1293 23:41:50.487881 TX Vref=26, minBit 6, minWin=27, winSum=448
1294 23:41:50.491399 TX Vref=28, minBit 12, minWin=27, winSum=454
1295 23:41:50.494688 TX Vref=30, minBit 0, minWin=28, winSum=456
1296 23:41:50.497801 TX Vref=32, minBit 0, minWin=28, winSum=453
1297 23:41:50.504849 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1298 23:41:50.505303
1299 23:41:50.508103 Final TX Range 1 Vref 30
1300 23:41:50.508608
1301 23:41:50.509084 ==
1302 23:41:50.511841 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 23:41:50.514592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 23:41:50.515085 ==
1305 23:41:50.515445
1306 23:41:50.515755
1307 23:41:50.518181 TX Vref Scan disable
1308 23:41:50.521414 == TX Byte 0 ==
1309 23:41:50.524690 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1310 23:41:50.528046 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1311 23:41:50.531541 == TX Byte 1 ==
1312 23:41:50.534923 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1313 23:41:50.537994 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1314 23:41:50.538432
1315 23:41:50.541491 [DATLAT]
1316 23:41:50.541919 Freq=800, CH0 RK1
1317 23:41:50.542244
1318 23:41:50.544612 DATLAT Default: 0x9
1319 23:41:50.545084 0, 0xFFFF, sum = 0
1320 23:41:50.547896 1, 0xFFFF, sum = 0
1321 23:41:50.548316 2, 0xFFFF, sum = 0
1322 23:41:50.551209 3, 0xFFFF, sum = 0
1323 23:41:50.551667 4, 0xFFFF, sum = 0
1324 23:41:50.554676 5, 0xFFFF, sum = 0
1325 23:41:50.555253 6, 0xFFFF, sum = 0
1326 23:41:50.558110 7, 0xFFFF, sum = 0
1327 23:41:50.558640 8, 0xFFFF, sum = 0
1328 23:41:50.561922 9, 0x0, sum = 1
1329 23:41:50.562338 10, 0x0, sum = 2
1330 23:41:50.565099 11, 0x0, sum = 3
1331 23:41:50.565520 12, 0x0, sum = 4
1332 23:41:50.568491 best_step = 10
1333 23:41:50.568964
1334 23:41:50.569563 ==
1335 23:41:50.571771 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 23:41:50.574900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 23:41:50.575403 ==
1338 23:41:50.578119 RX Vref Scan: 0
1339 23:41:50.578578
1340 23:41:50.578948 RX Vref 0 -> 0, step: 1
1341 23:41:50.579327
1342 23:41:50.581618 RX Delay -95 -> 252, step: 8
1343 23:41:50.588147 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1344 23:41:50.591585 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1345 23:41:50.594913 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1346 23:41:50.598263 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1347 23:41:50.601529 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1348 23:41:50.604730 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1349 23:41:50.611514 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1350 23:41:50.614844 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1351 23:41:50.618278 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1352 23:41:50.621645 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1353 23:41:50.625401 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1354 23:41:50.631850 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1355 23:41:50.635073 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1356 23:41:50.638757 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1357 23:41:50.641963 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1358 23:41:50.645508 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1359 23:41:50.648329 ==
1360 23:41:50.651706 Dram Type= 6, Freq= 0, CH_0, rank 1
1361 23:41:50.655465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1362 23:41:50.655948 ==
1363 23:41:50.656290 DQS Delay:
1364 23:41:50.658216 DQS0 = 0, DQS1 = 0
1365 23:41:50.658629 DQM Delay:
1366 23:41:50.661778 DQM0 = 87, DQM1 = 78
1367 23:41:50.662204 DQ Delay:
1368 23:41:50.665373 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1369 23:41:50.668656 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1370 23:41:50.672091 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1371 23:41:50.675560 DQ12 =80, DQ13 =84, DQ14 =88, DQ15 =88
1372 23:41:50.676043
1373 23:41:50.676518
1374 23:41:50.682469 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
1375 23:41:50.685586 CH0 RK1: MR19=606, MR18=2E18
1376 23:41:50.692192 CH0_RK1: MR19=0x606, MR18=0x2E18, DQSOSC=398, MR23=63, INC=93, DEC=62
1377 23:41:50.695736 [RxdqsGatingPostProcess] freq 800
1378 23:41:50.698645 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1379 23:41:50.702085 Pre-setting of DQS Precalculation
1380 23:41:50.708691 [DualRankRxdatlatCal] RK0: 9, RK1: 10, Final_Datlat 10
1381 23:41:50.709159 ==
1382 23:41:50.712491 Dram Type= 6, Freq= 0, CH_1, rank 0
1383 23:41:50.715569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1384 23:41:50.715978 ==
1385 23:41:50.722425 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1386 23:41:50.725274 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1387 23:41:50.735838 [CA 0] Center 36 (6~67) winsize 62
1388 23:41:50.739086 [CA 1] Center 36 (6~66) winsize 61
1389 23:41:50.742502 [CA 2] Center 34 (4~64) winsize 61
1390 23:41:50.745887 [CA 3] Center 33 (3~64) winsize 62
1391 23:41:50.749486 [CA 4] Center 34 (4~65) winsize 62
1392 23:41:50.752863 [CA 5] Center 33 (3~64) winsize 62
1393 23:41:50.753329
1394 23:41:50.756298 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1395 23:41:50.756704
1396 23:41:50.759265 [CATrainingPosCal] consider 1 rank data
1397 23:41:50.762555 u2DelayCellTimex100 = 270/100 ps
1398 23:41:50.766415 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1399 23:41:50.769528 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1400 23:41:50.772932 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1401 23:41:50.779595 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1402 23:41:50.783493 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1403 23:41:50.787109 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1404 23:41:50.787624
1405 23:41:50.789468 CA PerBit enable=1, Macro0, CA PI delay=33
1406 23:41:50.789881
1407 23:41:50.792751 [CBTSetCACLKResult] CA Dly = 33
1408 23:41:50.793235 CS Dly: 4 (0~35)
1409 23:41:50.793567 ==
1410 23:41:50.796671 Dram Type= 6, Freq= 0, CH_1, rank 1
1411 23:41:50.803183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1412 23:41:50.803702 ==
1413 23:41:50.806568 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1414 23:41:50.813515 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1415 23:41:50.821887 [CA 0] Center 36 (6~66) winsize 61
1416 23:41:50.825844 [CA 1] Center 36 (6~66) winsize 61
1417 23:41:50.829798 [CA 2] Center 34 (4~65) winsize 62
1418 23:41:50.833590 [CA 3] Center 34 (3~65) winsize 63
1419 23:41:50.837400 [CA 4] Center 34 (4~65) winsize 62
1420 23:41:50.837967 [CA 5] Center 33 (3~64) winsize 62
1421 23:41:50.838343
1422 23:41:50.845186 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1423 23:41:50.845616
1424 23:41:50.848293 [CATrainingPosCal] consider 2 rank data
1425 23:41:50.848702 u2DelayCellTimex100 = 270/100 ps
1426 23:41:50.852101 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1427 23:41:50.856221 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1428 23:41:50.859488 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1429 23:41:50.863118 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1430 23:41:50.866318 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1431 23:41:50.869654 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1432 23:41:50.870089
1433 23:41:50.876736 CA PerBit enable=1, Macro0, CA PI delay=33
1434 23:41:50.877219
1435 23:41:50.879804 [CBTSetCACLKResult] CA Dly = 33
1436 23:41:50.880215 CS Dly: 4 (0~36)
1437 23:41:50.880563
1438 23:41:50.882964 ----->DramcWriteLeveling(PI) begin...
1439 23:41:50.883694 ==
1440 23:41:50.886774 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 23:41:50.889891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 23:41:50.890358 ==
1443 23:41:50.893494 Write leveling (Byte 0): 27 => 27
1444 23:41:50.896275 Write leveling (Byte 1): 28 => 28
1445 23:41:50.899969 DramcWriteLeveling(PI) end<-----
1446 23:41:50.900400
1447 23:41:50.900740 ==
1448 23:41:50.903175 Dram Type= 6, Freq= 0, CH_1, rank 0
1449 23:41:50.906268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1450 23:41:50.910011 ==
1451 23:41:50.910436 [Gating] SW mode calibration
1452 23:41:50.916846 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1453 23:41:50.923164 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1454 23:41:50.926587 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1455 23:41:50.933815 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1456 23:41:50.936486 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1457 23:41:50.940029 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:41:50.946838 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:41:50.950161 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:41:50.953659 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:41:50.956629 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:41:50.963775 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:41:50.967191 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:41:50.970629 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:41:50.976864 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:41:50.980099 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1467 23:41:50.984006 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:41:50.990684 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1469 23:41:50.993997 0 7 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1470 23:41:50.997395 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:41:51.003979 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:41:51.007439 0 8 8 | B1->B0 | 2323 2323 | 1 0 | (1 1) (1 1)
1473 23:41:51.010389 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1474 23:41:51.013861 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 23:41:51.021091 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 23:41:51.024173 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 23:41:51.027177 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 23:41:51.034191 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 23:41:51.037272 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1480 23:41:51.040740 0 9 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1481 23:41:51.047764 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 23:41:51.050802 0 9 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1483 23:41:51.054063 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 23:41:51.061043 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 23:41:51.064226 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 23:41:51.067833 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 23:41:51.070718 0 10 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
1488 23:41:51.077678 0 10 8 | B1->B0 | 2b2b 2f2f | 0 0 | (1 1) (0 0)
1489 23:41:51.081466 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1490 23:41:51.084534 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 23:41:51.091203 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 23:41:51.094587 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 23:41:51.097901 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 23:41:51.104537 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 23:41:51.108038 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 23:41:51.111324 0 11 8 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 0)
1497 23:41:51.117964 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 23:41:51.121703 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 23:41:51.124731 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 23:41:51.131790 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 23:41:51.135138 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 23:41:51.138249 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 23:41:51.141619 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 23:41:51.147912 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1505 23:41:51.151329 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1506 23:41:51.154805 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:41:51.161553 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:41:51.164969 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:41:51.168184 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:41:51.175283 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:41:51.178416 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:41:51.181895 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:41:51.188237 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:41:51.191984 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 23:41:51.195454 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 23:41:51.201926 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 23:41:51.205498 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 23:41:51.208382 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 23:41:51.211849 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1520 23:41:51.218674 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1521 23:41:51.221605 Total UI for P1: 0, mck2ui 16
1522 23:41:51.225446 best dqsien dly found for B0: ( 0, 14, 4)
1523 23:41:51.228957 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1524 23:41:51.231782 Total UI for P1: 0, mck2ui 16
1525 23:41:51.235393 best dqsien dly found for B1: ( 0, 14, 6)
1526 23:41:51.238499 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1527 23:41:51.241907 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1528 23:41:51.242360
1529 23:41:51.245813 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1530 23:41:51.249148 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1531 23:41:51.252504 [Gating] SW calibration Done
1532 23:41:51.253090 ==
1533 23:41:51.255750 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 23:41:51.259029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1535 23:41:51.259597 ==
1536 23:41:51.263319 RX Vref Scan: 0
1537 23:41:51.263870
1538 23:41:51.265407 RX Vref 0 -> 0, step: 1
1539 23:41:51.265856
1540 23:41:51.266210 RX Delay -130 -> 252, step: 16
1541 23:41:51.272293 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1542 23:41:51.275821 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1543 23:41:51.279448 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1544 23:41:51.282674 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1545 23:41:51.285777 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1546 23:41:51.292133 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1547 23:41:51.295747 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1548 23:41:51.299135 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1549 23:41:51.302545 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1550 23:41:51.305781 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1551 23:41:51.309591 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1552 23:41:51.315870 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1553 23:41:51.319486 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1554 23:41:51.322828 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1555 23:41:51.325625 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1556 23:41:51.332577 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1557 23:41:51.333036 ==
1558 23:41:51.336102 Dram Type= 6, Freq= 0, CH_1, rank 0
1559 23:41:51.339119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1560 23:41:51.339596 ==
1561 23:41:51.339922 DQS Delay:
1562 23:41:51.342572 DQS0 = 0, DQS1 = 0
1563 23:41:51.342978 DQM Delay:
1564 23:41:51.346195 DQM0 = 83, DQM1 = 77
1565 23:41:51.346601 DQ Delay:
1566 23:41:51.349413 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1567 23:41:51.352615 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1568 23:41:51.355913 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1569 23:41:51.359297 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1570 23:41:51.359848
1571 23:41:51.360283
1572 23:41:51.360797 ==
1573 23:41:51.362928 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 23:41:51.366504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 23:41:51.366937 ==
1576 23:41:51.367374
1577 23:41:51.367781
1578 23:41:51.369311 TX Vref Scan disable
1579 23:41:51.372640 == TX Byte 0 ==
1580 23:41:51.375942 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1581 23:41:51.379303 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1582 23:41:51.382773 == TX Byte 1 ==
1583 23:41:51.386263 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1584 23:41:51.389715 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1585 23:41:51.390122 ==
1586 23:41:51.393282 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 23:41:51.396526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 23:41:51.396935 ==
1589 23:41:51.411497 TX Vref=22, minBit 0, minWin=27, winSum=440
1590 23:41:51.414689 TX Vref=24, minBit 1, minWin=27, winSum=444
1591 23:41:51.418269 TX Vref=26, minBit 8, minWin=27, winSum=449
1592 23:41:51.421859 TX Vref=28, minBit 15, minWin=27, winSum=450
1593 23:41:51.425135 TX Vref=30, minBit 1, minWin=28, winSum=453
1594 23:41:51.428506 TX Vref=32, minBit 11, minWin=27, winSum=453
1595 23:41:51.434509 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 30
1596 23:41:51.435080
1597 23:41:51.438254 Final TX Range 1 Vref 30
1598 23:41:51.438922
1599 23:41:51.439267 ==
1600 23:41:51.441641 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 23:41:51.444942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 23:41:51.445392 ==
1603 23:41:51.445774
1604 23:41:51.446076
1605 23:41:51.447911 TX Vref Scan disable
1606 23:41:51.451745 == TX Byte 0 ==
1607 23:41:51.454909 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1608 23:41:51.457924 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1609 23:41:51.461927 == TX Byte 1 ==
1610 23:41:51.465086 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1611 23:41:51.468360 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1612 23:41:51.468789
1613 23:41:51.469251 [DATLAT]
1614 23:41:51.471497 Freq=800, CH1 RK0
1615 23:41:51.471998
1616 23:41:51.475453 DATLAT Default: 0xa
1617 23:41:51.475932 0, 0xFFFF, sum = 0
1618 23:41:51.478160 1, 0xFFFF, sum = 0
1619 23:41:51.478596 2, 0xFFFF, sum = 0
1620 23:41:51.482017 3, 0xFFFF, sum = 0
1621 23:41:51.482463 4, 0xFFFF, sum = 0
1622 23:41:51.485462 5, 0xFFFF, sum = 0
1623 23:41:51.485973 6, 0xFFFF, sum = 0
1624 23:41:51.488558 7, 0xFFFF, sum = 0
1625 23:41:51.489022 8, 0xFFFF, sum = 0
1626 23:41:51.491869 9, 0x0, sum = 1
1627 23:41:51.492292 10, 0x0, sum = 2
1628 23:41:51.495199 11, 0x0, sum = 3
1629 23:41:51.495611 12, 0x0, sum = 4
1630 23:41:51.495940 best_step = 10
1631 23:41:51.498661
1632 23:41:51.499063 ==
1633 23:41:51.501480 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 23:41:51.504912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 23:41:51.505353 ==
1636 23:41:51.505690 RX Vref Scan: 1
1637 23:41:51.505993
1638 23:41:51.508359 Set Vref Range= 32 -> 127
1639 23:41:51.508872
1640 23:41:51.512113 RX Vref 32 -> 127, step: 1
1641 23:41:51.512615
1642 23:41:51.515202 RX Delay -111 -> 252, step: 8
1643 23:41:51.515610
1644 23:41:51.518624 Set Vref, RX VrefLevel [Byte0]: 32
1645 23:41:51.522294 [Byte1]: 32
1646 23:41:51.522702
1647 23:41:51.526147 Set Vref, RX VrefLevel [Byte0]: 33
1648 23:41:51.528839 [Byte1]: 33
1649 23:41:51.529375
1650 23:41:51.532413 Set Vref, RX VrefLevel [Byte0]: 34
1651 23:41:51.535102 [Byte1]: 34
1652 23:41:51.539327
1653 23:41:51.539857 Set Vref, RX VrefLevel [Byte0]: 35
1654 23:41:51.541934 [Byte1]: 35
1655 23:41:51.546252
1656 23:41:51.546655 Set Vref, RX VrefLevel [Byte0]: 36
1657 23:41:51.549507 [Byte1]: 36
1658 23:41:51.554073
1659 23:41:51.554475 Set Vref, RX VrefLevel [Byte0]: 37
1660 23:41:51.557060 [Byte1]: 37
1661 23:41:51.562196
1662 23:41:51.562701 Set Vref, RX VrefLevel [Byte0]: 38
1663 23:41:51.564688 [Byte1]: 38
1664 23:41:51.569345
1665 23:41:51.569748 Set Vref, RX VrefLevel [Byte0]: 39
1666 23:41:51.572945 [Byte1]: 39
1667 23:41:51.576755
1668 23:41:51.577199 Set Vref, RX VrefLevel [Byte0]: 40
1669 23:41:51.580371 [Byte1]: 40
1670 23:41:51.584933
1671 23:41:51.585470 Set Vref, RX VrefLevel [Byte0]: 41
1672 23:41:51.588335 [Byte1]: 41
1673 23:41:51.592644
1674 23:41:51.593210 Set Vref, RX VrefLevel [Byte0]: 42
1675 23:41:51.596101 [Byte1]: 42
1676 23:41:51.600389
1677 23:41:51.600911 Set Vref, RX VrefLevel [Byte0]: 43
1678 23:41:51.604009 [Byte1]: 43
1679 23:41:51.607775
1680 23:41:51.608305 Set Vref, RX VrefLevel [Byte0]: 44
1681 23:41:51.611182 [Byte1]: 44
1682 23:41:51.615625
1683 23:41:51.616147 Set Vref, RX VrefLevel [Byte0]: 45
1684 23:41:51.618914 [Byte1]: 45
1685 23:41:51.623169
1686 23:41:51.623674 Set Vref, RX VrefLevel [Byte0]: 46
1687 23:41:51.626777 [Byte1]: 46
1688 23:41:51.630518
1689 23:41:51.631019 Set Vref, RX VrefLevel [Byte0]: 47
1690 23:41:51.634004 [Byte1]: 47
1691 23:41:51.638435
1692 23:41:51.638948 Set Vref, RX VrefLevel [Byte0]: 48
1693 23:41:51.641628 [Byte1]: 48
1694 23:41:51.646071
1695 23:41:51.646475 Set Vref, RX VrefLevel [Byte0]: 49
1696 23:41:51.649311 [Byte1]: 49
1697 23:41:51.653926
1698 23:41:51.654462 Set Vref, RX VrefLevel [Byte0]: 50
1699 23:41:51.656665 [Byte1]: 50
1700 23:41:51.661144
1701 23:41:51.661571 Set Vref, RX VrefLevel [Byte0]: 51
1702 23:41:51.664255 [Byte1]: 51
1703 23:41:51.668778
1704 23:41:51.669453 Set Vref, RX VrefLevel [Byte0]: 52
1705 23:41:51.672231 [Byte1]: 52
1706 23:41:51.677301
1707 23:41:51.677884 Set Vref, RX VrefLevel [Byte0]: 53
1708 23:41:51.679647 [Byte1]: 53
1709 23:41:51.684026
1710 23:41:51.684698 Set Vref, RX VrefLevel [Byte0]: 54
1711 23:41:51.687462 [Byte1]: 54
1712 23:41:51.692060
1713 23:41:51.692604 Set Vref, RX VrefLevel [Byte0]: 55
1714 23:41:51.695098 [Byte1]: 55
1715 23:41:51.699319
1716 23:41:51.699844 Set Vref, RX VrefLevel [Byte0]: 56
1717 23:41:51.702446 [Byte1]: 56
1718 23:41:51.707165
1719 23:41:51.707689 Set Vref, RX VrefLevel [Byte0]: 57
1720 23:41:51.710617 [Byte1]: 57
1721 23:41:51.714501
1722 23:41:51.715027 Set Vref, RX VrefLevel [Byte0]: 58
1723 23:41:51.718068 [Byte1]: 58
1724 23:41:51.722286
1725 23:41:51.722700 Set Vref, RX VrefLevel [Byte0]: 59
1726 23:41:51.725500 [Byte1]: 59
1727 23:41:51.729761
1728 23:41:51.730173 Set Vref, RX VrefLevel [Byte0]: 60
1729 23:41:51.733183 [Byte1]: 60
1730 23:41:51.737441
1731 23:41:51.737860 Set Vref, RX VrefLevel [Byte0]: 61
1732 23:41:51.741144 [Byte1]: 61
1733 23:41:51.745095
1734 23:41:51.745558 Set Vref, RX VrefLevel [Byte0]: 62
1735 23:41:51.748738 [Byte1]: 62
1736 23:41:51.752697
1737 23:41:51.753387 Set Vref, RX VrefLevel [Byte0]: 63
1738 23:41:51.755839 [Byte1]: 63
1739 23:41:51.760279
1740 23:41:51.760701 Set Vref, RX VrefLevel [Byte0]: 64
1741 23:41:51.763462 [Byte1]: 64
1742 23:41:51.768063
1743 23:41:51.768622 Set Vref, RX VrefLevel [Byte0]: 65
1744 23:41:51.771722 [Byte1]: 65
1745 23:41:51.775646
1746 23:41:51.776190 Set Vref, RX VrefLevel [Byte0]: 66
1747 23:41:51.779268 [Byte1]: 66
1748 23:41:51.783263
1749 23:41:51.783762 Set Vref, RX VrefLevel [Byte0]: 67
1750 23:41:51.786616 [Byte1]: 67
1751 23:41:51.791122
1752 23:41:51.791537 Set Vref, RX VrefLevel [Byte0]: 68
1753 23:41:51.794548 [Byte1]: 68
1754 23:41:51.798523
1755 23:41:51.798934 Set Vref, RX VrefLevel [Byte0]: 69
1756 23:41:51.802088 [Byte1]: 69
1757 23:41:51.806256
1758 23:41:51.806684 Set Vref, RX VrefLevel [Byte0]: 70
1759 23:41:51.809560 [Byte1]: 70
1760 23:41:51.814285
1761 23:41:51.814712 Set Vref, RX VrefLevel [Byte0]: 71
1762 23:41:51.817017 [Byte1]: 71
1763 23:41:51.821675
1764 23:41:51.822176 Set Vref, RX VrefLevel [Byte0]: 72
1765 23:41:51.825056 [Byte1]: 72
1766 23:41:51.829741
1767 23:41:51.830152 Set Vref, RX VrefLevel [Byte0]: 73
1768 23:41:51.832500 [Byte1]: 73
1769 23:41:51.836658
1770 23:41:51.837192 Set Vref, RX VrefLevel [Byte0]: 74
1771 23:41:51.840232 [Byte1]: 74
1772 23:41:51.844799
1773 23:41:51.845250 Set Vref, RX VrefLevel [Byte0]: 75
1774 23:41:51.848057 [Byte1]: 75
1775 23:41:51.852364
1776 23:41:51.852859 Set Vref, RX VrefLevel [Byte0]: 76
1777 23:41:51.855589 [Byte1]: 76
1778 23:41:51.859565
1779 23:41:51.859971 Set Vref, RX VrefLevel [Byte0]: 77
1780 23:41:51.863057 [Byte1]: 77
1781 23:41:51.867293
1782 23:41:51.867696 Set Vref, RX VrefLevel [Byte0]: 78
1783 23:41:51.870925 [Byte1]: 78
1784 23:41:51.875315
1785 23:41:51.875820 Set Vref, RX VrefLevel [Byte0]: 79
1786 23:41:51.878727 [Byte1]: 79
1787 23:41:51.883043
1788 23:41:51.883447 Final RX Vref Byte 0 = 63 to rank0
1789 23:41:51.886217 Final RX Vref Byte 1 = 61 to rank0
1790 23:41:51.889288 Final RX Vref Byte 0 = 63 to rank1
1791 23:41:51.892924 Final RX Vref Byte 1 = 61 to rank1==
1792 23:41:51.896286 Dram Type= 6, Freq= 0, CH_1, rank 0
1793 23:41:51.899469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1794 23:41:51.902789 ==
1795 23:41:51.903210 DQS Delay:
1796 23:41:51.903556 DQS0 = 0, DQS1 = 0
1797 23:41:51.906806 DQM Delay:
1798 23:41:51.907222 DQM0 = 83, DQM1 = 74
1799 23:41:51.909605 DQ Delay:
1800 23:41:51.910136 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1801 23:41:51.912966 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
1802 23:41:51.916592 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =72
1803 23:41:51.919823 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =76
1804 23:41:51.920226
1805 23:41:51.923488
1806 23:41:51.929753 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c01, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1807 23:41:51.933258 CH1 RK0: MR19=606, MR18=2C01
1808 23:41:51.940023 CH1_RK0: MR19=0x606, MR18=0x2C01, DQSOSC=398, MR23=63, INC=93, DEC=62
1809 23:41:51.940530
1810 23:41:51.943057 ----->DramcWriteLeveling(PI) begin...
1811 23:41:51.943667 ==
1812 23:41:51.946713 Dram Type= 6, Freq= 0, CH_1, rank 1
1813 23:41:51.949560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 23:41:51.950002 ==
1815 23:41:51.953171 Write leveling (Byte 0): 28 => 28
1816 23:41:51.956375 Write leveling (Byte 1): 28 => 28
1817 23:41:51.959743 DramcWriteLeveling(PI) end<-----
1818 23:41:51.960352
1819 23:41:51.960741 ==
1820 23:41:51.963079 Dram Type= 6, Freq= 0, CH_1, rank 1
1821 23:41:51.966925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1822 23:41:51.967356 ==
1823 23:41:51.970035 [Gating] SW mode calibration
1824 23:41:51.976691 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1825 23:41:51.983507 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1826 23:41:51.986850 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1827 23:41:51.990037 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1828 23:41:51.993273 0 6 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1829 23:41:52.000072 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:41:52.003345 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 23:41:52.006780 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 23:41:52.013509 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:41:52.016761 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 23:41:52.020746 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:41:52.026972 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:41:52.030393 0 7 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1837 23:41:52.034407 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:41:52.040969 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1839 23:41:52.044089 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:41:52.047633 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:41:52.051293 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 23:41:52.057621 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 23:41:52.061110 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1844 23:41:52.064546 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1845 23:41:52.070976 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 23:41:52.074219 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 23:41:52.077891 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 23:41:52.084619 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 23:41:52.087950 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 23:41:52.090862 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 23:41:52.097762 0 9 4 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
1852 23:41:52.100389 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1853 23:41:52.104064 0 9 12 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1854 23:41:52.110543 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1855 23:41:52.114310 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1856 23:41:52.117875 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1857 23:41:52.121485 0 9 28 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1858 23:41:52.128200 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1859 23:41:52.130909 0 10 4 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (1 0)
1860 23:41:52.134866 0 10 8 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
1861 23:41:52.140933 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 23:41:52.144411 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 23:41:52.147460 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 23:41:52.154176 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:41:52.157651 0 10 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1866 23:41:52.161280 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:41:52.167782 0 11 4 | B1->B0 | 2727 3535 | 0 0 | (0 0) (0 0)
1868 23:41:52.171430 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1869 23:41:52.174531 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 23:41:52.181647 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1871 23:41:52.185003 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1872 23:41:52.188355 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 23:41:52.191539 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 23:41:52.198019 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 23:41:52.201303 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1876 23:41:52.204525 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:41:52.211028 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 23:41:52.214473 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 23:41:52.217908 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 23:41:52.224361 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 23:41:52.228466 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 23:41:52.232047 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 23:41:52.238512 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 23:41:52.241862 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 23:41:52.245251 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 23:41:52.248398 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1887 23:41:52.254783 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1888 23:41:52.258071 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 23:41:52.261561 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 23:41:52.268316 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 23:41:52.271929 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1892 23:41:52.275342 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 23:41:52.278496 Total UI for P1: 0, mck2ui 16
1894 23:41:52.282162 best dqsien dly found for B0: ( 0, 14, 4)
1895 23:41:52.285268 Total UI for P1: 0, mck2ui 16
1896 23:41:52.288411 best dqsien dly found for B1: ( 0, 14, 6)
1897 23:41:52.291656 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1898 23:41:52.295279 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1899 23:41:52.295690
1900 23:41:52.298713 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1901 23:41:52.305528 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1902 23:41:52.305942 [Gating] SW calibration Done
1903 23:41:52.306266 ==
1904 23:41:52.308910 Dram Type= 6, Freq= 0, CH_1, rank 1
1905 23:41:52.315355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1906 23:41:52.315850 ==
1907 23:41:52.316181 RX Vref Scan: 0
1908 23:41:52.316486
1909 23:41:52.318388 RX Vref 0 -> 0, step: 1
1910 23:41:52.318799
1911 23:41:52.321887 RX Delay -130 -> 252, step: 16
1912 23:41:52.326026 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1913 23:41:52.329043 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1914 23:41:52.332379 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1915 23:41:52.335543 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1916 23:41:52.342241 iDelay=206, Bit 4, Center 69 (-50 ~ 189) 240
1917 23:41:52.345655 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1918 23:41:52.349082 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1919 23:41:52.352369 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1920 23:41:52.355366 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1921 23:41:52.362000 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1922 23:41:52.365439 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1923 23:41:52.368803 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1924 23:41:52.372349 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1925 23:41:52.375630 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1926 23:41:52.382582 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1927 23:41:52.385917 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1928 23:41:52.386366 ==
1929 23:41:52.389299 Dram Type= 6, Freq= 0, CH_1, rank 1
1930 23:41:52.392903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1931 23:41:52.393406 ==
1932 23:41:52.393738 DQS Delay:
1933 23:41:52.395828 DQS0 = 0, DQS1 = 0
1934 23:41:52.396279 DQM Delay:
1935 23:41:52.399146 DQM0 = 79, DQM1 = 77
1936 23:41:52.399555 DQ Delay:
1937 23:41:52.402596 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1938 23:41:52.405986 DQ4 =69, DQ5 =93, DQ6 =93, DQ7 =69
1939 23:41:52.409541 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1940 23:41:52.412648 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1941 23:41:52.413210
1942 23:41:52.413546
1943 23:41:52.413850 ==
1944 23:41:52.416022 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 23:41:52.419601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 23:41:52.420035 ==
1947 23:41:52.422750
1948 23:41:52.423174
1949 23:41:52.423606 TX Vref Scan disable
1950 23:41:52.426153 == TX Byte 0 ==
1951 23:41:52.429633 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1952 23:41:52.432852 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1953 23:41:52.436157 == TX Byte 1 ==
1954 23:41:52.439492 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1955 23:41:52.442902 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1956 23:41:52.443348 ==
1957 23:41:52.446321 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 23:41:52.453187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 23:41:52.453605 ==
1960 23:41:52.464658 TX Vref=22, minBit 5, minWin=27, winSum=445
1961 23:41:52.468176 TX Vref=24, minBit 0, minWin=27, winSum=443
1962 23:41:52.471272 TX Vref=26, minBit 10, minWin=27, winSum=446
1963 23:41:52.474354 TX Vref=28, minBit 10, minWin=27, winSum=446
1964 23:41:52.477695 TX Vref=30, minBit 0, minWin=28, winSum=450
1965 23:41:52.484552 TX Vref=32, minBit 11, minWin=27, winSum=450
1966 23:41:52.487978 [TxChooseVref] Worse bit 0, Min win 28, Win sum 450, Final Vref 30
1967 23:41:52.488487
1968 23:41:52.491156 Final TX Range 1 Vref 30
1969 23:41:52.491662
1970 23:41:52.491987 ==
1971 23:41:52.494150 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 23:41:52.497897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 23:41:52.498411 ==
1974 23:41:52.501179
1975 23:41:52.501605
1976 23:41:52.501942 TX Vref Scan disable
1977 23:41:52.504925 == TX Byte 0 ==
1978 23:41:52.508594 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1979 23:41:52.511240 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1980 23:41:52.514687 == TX Byte 1 ==
1981 23:41:52.518379 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1982 23:41:52.521273 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1983 23:41:52.525075
1984 23:41:52.525575 [DATLAT]
1985 23:41:52.525904 Freq=800, CH1 RK1
1986 23:41:52.526237
1987 23:41:52.528134 DATLAT Default: 0xa
1988 23:41:52.528540 0, 0xFFFF, sum = 0
1989 23:41:52.531745 1, 0xFFFF, sum = 0
1990 23:41:52.532255 2, 0xFFFF, sum = 0
1991 23:41:52.535290 3, 0xFFFF, sum = 0
1992 23:41:52.535801 4, 0xFFFF, sum = 0
1993 23:41:52.538236 5, 0xFFFF, sum = 0
1994 23:41:52.538737 6, 0xFFFF, sum = 0
1995 23:41:52.541546 7, 0xFFFF, sum = 0
1996 23:41:52.542056 8, 0xFFFF, sum = 0
1997 23:41:52.544866 9, 0x0, sum = 1
1998 23:41:52.545361 10, 0x0, sum = 2
1999 23:41:52.548231 11, 0x0, sum = 3
2000 23:41:52.548650 12, 0x0, sum = 4
2001 23:41:52.552021 best_step = 10
2002 23:41:52.552527
2003 23:41:52.552853 ==
2004 23:41:52.555260 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 23:41:52.558343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 23:41:52.558836 ==
2007 23:41:52.562139 RX Vref Scan: 0
2008 23:41:52.562697
2009 23:41:52.563180 RX Vref 0 -> 0, step: 1
2010 23:41:52.563634
2011 23:41:52.564723 RX Delay -95 -> 252, step: 8
2012 23:41:52.571880 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2013 23:41:52.575686 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2014 23:41:52.579024 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2015 23:41:52.581671 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2016 23:41:52.585492 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
2017 23:41:52.588482 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
2018 23:41:52.595220 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2019 23:41:52.598660 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2020 23:41:52.601730 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2021 23:41:52.605525 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2022 23:41:52.608601 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2023 23:41:52.615893 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2024 23:41:52.619335 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2025 23:41:52.622857 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2026 23:41:52.625127 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2027 23:41:52.629042 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2028 23:41:52.632280 ==
2029 23:41:52.632774 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 23:41:52.638847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 23:41:52.639362 ==
2032 23:41:52.639700 DQS Delay:
2033 23:41:52.642374 DQS0 = 0, DQS1 = 0
2034 23:41:52.642783 DQM Delay:
2035 23:41:52.643154 DQM0 = 79, DQM1 = 76
2036 23:41:52.645384 DQ Delay:
2037 23:41:52.648764 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2038 23:41:52.652223 DQ4 =76, DQ5 =88, DQ6 =92, DQ7 =76
2039 23:41:52.655539 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2040 23:41:52.658876 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
2041 23:41:52.659285
2042 23:41:52.659609
2043 23:41:52.665704 [DQSOSCAuto] RK1, (LSB)MR18= 0x242f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
2044 23:41:52.669283 CH1 RK1: MR19=606, MR18=242F
2045 23:41:52.676226 CH1_RK1: MR19=0x606, MR18=0x242F, DQSOSC=397, MR23=63, INC=93, DEC=62
2046 23:41:52.679268 [RxdqsGatingPostProcess] freq 800
2047 23:41:52.682915 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2048 23:41:52.686358 Pre-setting of DQS Precalculation
2049 23:41:52.693104 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2050 23:41:52.699495 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2051 23:41:52.706063 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2052 23:41:52.706596
2053 23:41:52.706934
2054 23:41:52.709586 [Calibration Summary] 1600 Mbps
2055 23:41:52.710214 CH 0, Rank 0
2056 23:41:52.712780 SW Impedance : PASS
2057 23:41:52.716142 DUTY Scan : NO K
2058 23:41:52.716693 ZQ Calibration : PASS
2059 23:41:52.719767 Jitter Meter : NO K
2060 23:41:52.720175 CBT Training : PASS
2061 23:41:52.722877 Write leveling : PASS
2062 23:41:52.726556 RX DQS gating : PASS
2063 23:41:52.726966 RX DQ/DQS(RDDQC) : PASS
2064 23:41:52.729801 TX DQ/DQS : PASS
2065 23:41:52.733352 RX DATLAT : PASS
2066 23:41:52.733788 RX DQ/DQS(Engine): PASS
2067 23:41:52.736094 TX OE : NO K
2068 23:41:52.736504 All Pass.
2069 23:41:52.736821
2070 23:41:52.739409 CH 0, Rank 1
2071 23:41:52.739946 SW Impedance : PASS
2072 23:41:52.742858 DUTY Scan : NO K
2073 23:41:52.746119 ZQ Calibration : PASS
2074 23:41:52.746695 Jitter Meter : NO K
2075 23:41:52.749752 CBT Training : PASS
2076 23:41:52.750200 Write leveling : PASS
2077 23:41:52.753233 RX DQS gating : PASS
2078 23:41:52.756605 RX DQ/DQS(RDDQC) : PASS
2079 23:41:52.757227 TX DQ/DQS : PASS
2080 23:41:52.759536 RX DATLAT : PASS
2081 23:41:52.763382 RX DQ/DQS(Engine): PASS
2082 23:41:52.763852 TX OE : NO K
2083 23:41:52.766561 All Pass.
2084 23:41:52.766987
2085 23:41:52.767416 CH 1, Rank 0
2086 23:41:52.769745 SW Impedance : PASS
2087 23:41:52.770173 DUTY Scan : NO K
2088 23:41:52.773377 ZQ Calibration : PASS
2089 23:41:52.776269 Jitter Meter : NO K
2090 23:41:52.776694 CBT Training : PASS
2091 23:41:52.780265 Write leveling : PASS
2092 23:41:52.780692 RX DQS gating : PASS
2093 23:41:52.783017 RX DQ/DQS(RDDQC) : PASS
2094 23:41:52.786693 TX DQ/DQS : PASS
2095 23:41:52.787260 RX DATLAT : PASS
2096 23:41:52.789755 RX DQ/DQS(Engine): PASS
2097 23:41:52.793188 TX OE : NO K
2098 23:41:52.793634 All Pass.
2099 23:41:52.794011
2100 23:41:52.794491 CH 1, Rank 1
2101 23:41:52.797069 SW Impedance : PASS
2102 23:41:52.799936 DUTY Scan : NO K
2103 23:41:52.800441 ZQ Calibration : PASS
2104 23:41:52.803124 Jitter Meter : NO K
2105 23:41:52.806614 CBT Training : PASS
2106 23:41:52.807021 Write leveling : PASS
2107 23:41:52.810135 RX DQS gating : PASS
2108 23:41:52.813328 RX DQ/DQS(RDDQC) : PASS
2109 23:41:52.813733 TX DQ/DQS : PASS
2110 23:41:52.816727 RX DATLAT : PASS
2111 23:41:52.817215 RX DQ/DQS(Engine): PASS
2112 23:41:52.820265 TX OE : NO K
2113 23:41:52.820676 All Pass.
2114 23:41:52.821035
2115 23:41:52.824359 DramC Write-DBI off
2116 23:41:52.827066 PER_BANK_REFRESH: Hybrid Mode
2117 23:41:52.827474 TX_TRACKING: ON
2118 23:41:52.830459 [GetDramInforAfterCalByMRR] Vendor 6.
2119 23:41:52.833650 [GetDramInforAfterCalByMRR] Revision 606.
2120 23:41:52.837474 [GetDramInforAfterCalByMRR] Revision 2 0.
2121 23:41:52.840306 MR0 0x3b3b
2122 23:41:52.840809 MR8 0x5151
2123 23:41:52.843742 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 23:41:52.844284
2125 23:41:52.847117 MR0 0x3b3b
2126 23:41:52.847644 MR8 0x5151
2127 23:41:52.850386 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2128 23:41:52.850946
2129 23:41:52.860468 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2130 23:41:52.864013 [FAST_K] Save calibration result to emmc
2131 23:41:52.867026 [FAST_K] Save calibration result to emmc
2132 23:41:52.867579 dram_init: config_dvfs: 1
2133 23:41:52.873907 dramc_set_vcore_voltage set vcore to 662500
2134 23:41:52.874367 Read voltage for 1200, 2
2135 23:41:52.877109 Vio18 = 0
2136 23:41:52.877522 Vcore = 662500
2137 23:41:52.877850 Vdram = 0
2138 23:41:52.878211 Vddq = 0
2139 23:41:52.880458 Vmddr = 0
2140 23:41:52.883898 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2141 23:41:52.890698 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2142 23:41:52.891189 MEM_TYPE=3, freq_sel=15
2143 23:41:52.893779 sv_algorithm_assistance_LP4_1600
2144 23:41:52.900965 ============ PULL DRAM RESETB DOWN ============
2145 23:41:52.904567 ========== PULL DRAM RESETB DOWN end =========
2146 23:41:52.907787 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2147 23:41:52.910983 ===================================
2148 23:41:52.914508 LPDDR4 DRAM CONFIGURATION
2149 23:41:52.917315 ===================================
2150 23:41:52.917861 EX_ROW_EN[0] = 0x0
2151 23:41:52.920778 EX_ROW_EN[1] = 0x0
2152 23:41:52.923873 LP4Y_EN = 0x0
2153 23:41:52.924281 WORK_FSP = 0x0
2154 23:41:52.927639 WL = 0x4
2155 23:41:52.928105 RL = 0x4
2156 23:41:52.931058 BL = 0x2
2157 23:41:52.931471 RPST = 0x0
2158 23:41:52.934619 RD_PRE = 0x0
2159 23:41:52.935041 WR_PRE = 0x1
2160 23:41:52.937933 WR_PST = 0x0
2161 23:41:52.938340 DBI_WR = 0x0
2162 23:41:52.940922 DBI_RD = 0x0
2163 23:41:52.941465 OTF = 0x1
2164 23:41:52.944274 ===================================
2165 23:41:52.947784 ===================================
2166 23:41:52.951125 ANA top config
2167 23:41:52.954916 ===================================
2168 23:41:52.955326 DLL_ASYNC_EN = 0
2169 23:41:52.958218 ALL_SLAVE_EN = 0
2170 23:41:52.961426 NEW_RANK_MODE = 1
2171 23:41:52.964519 DLL_IDLE_MODE = 1
2172 23:41:52.964946 LP45_APHY_COMB_EN = 1
2173 23:41:52.968479 TX_ODT_DIS = 1
2174 23:41:52.971678 NEW_8X_MODE = 1
2175 23:41:52.974749 ===================================
2176 23:41:52.978616 ===================================
2177 23:41:52.981437 data_rate = 2400
2178 23:41:52.985167 CKR = 1
2179 23:41:52.985598 DQ_P2S_RATIO = 8
2180 23:41:52.988739 ===================================
2181 23:41:52.991480 CA_P2S_RATIO = 8
2182 23:41:52.994801 DQ_CA_OPEN = 0
2183 23:41:52.998437 DQ_SEMI_OPEN = 0
2184 23:41:53.001973 CA_SEMI_OPEN = 0
2185 23:41:53.002383 CA_FULL_RATE = 0
2186 23:41:53.005401 DQ_CKDIV4_EN = 0
2187 23:41:53.008256 CA_CKDIV4_EN = 0
2188 23:41:53.012115 CA_PREDIV_EN = 0
2189 23:41:53.015472 PH8_DLY = 17
2190 23:41:53.018369 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2191 23:41:53.018859 DQ_AAMCK_DIV = 4
2192 23:41:53.021754 CA_AAMCK_DIV = 4
2193 23:41:53.025543 CA_ADMCK_DIV = 4
2194 23:41:53.028544 DQ_TRACK_CA_EN = 0
2195 23:41:53.032190 CA_PICK = 1200
2196 23:41:53.035265 CA_MCKIO = 1200
2197 23:41:53.035679 MCKIO_SEMI = 0
2198 23:41:53.039097 PLL_FREQ = 2366
2199 23:41:53.042273 DQ_UI_PI_RATIO = 32
2200 23:41:53.045907 CA_UI_PI_RATIO = 0
2201 23:41:53.048592 ===================================
2202 23:41:53.052555 ===================================
2203 23:41:53.055733 memory_type:LPDDR4
2204 23:41:53.056143 GP_NUM : 10
2205 23:41:53.059121 SRAM_EN : 1
2206 23:41:53.062151 MD32_EN : 0
2207 23:41:53.065838 ===================================
2208 23:41:53.066248 [ANA_INIT] >>>>>>>>>>>>>>
2209 23:41:53.068885 <<<<<< [CONFIGURE PHASE]: ANA_TX
2210 23:41:53.072225 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2211 23:41:53.075746 ===================================
2212 23:41:53.079382 data_rate = 2400,PCW = 0X5b00
2213 23:41:53.082686 ===================================
2214 23:41:53.085909 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2215 23:41:53.092884 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2216 23:41:53.095716 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2217 23:41:53.102344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2218 23:41:53.105812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2219 23:41:53.109048 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2220 23:41:53.109459 [ANA_INIT] flow start
2221 23:41:53.112592 [ANA_INIT] PLL >>>>>>>>
2222 23:41:53.116066 [ANA_INIT] PLL <<<<<<<<
2223 23:41:53.116575 [ANA_INIT] MIDPI >>>>>>>>
2224 23:41:53.119422 [ANA_INIT] MIDPI <<<<<<<<
2225 23:41:53.122846 [ANA_INIT] DLL >>>>>>>>
2226 23:41:53.123256 [ANA_INIT] DLL <<<<<<<<
2227 23:41:53.125592 [ANA_INIT] flow end
2228 23:41:53.129790 ============ LP4 DIFF to SE enter ============
2229 23:41:53.132348 ============ LP4 DIFF to SE exit ============
2230 23:41:53.136100 [ANA_INIT] <<<<<<<<<<<<<
2231 23:41:53.139219 [Flow] Enable top DCM control >>>>>
2232 23:41:53.142716 [Flow] Enable top DCM control <<<<<
2233 23:41:53.146199 Enable DLL master slave shuffle
2234 23:41:53.152494 ==============================================================
2235 23:41:53.152908 Gating Mode config
2236 23:41:53.159217 ==============================================================
2237 23:41:53.159845 Config description:
2238 23:41:53.169508 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2239 23:41:53.176376 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2240 23:41:53.183078 SELPH_MODE 0: By rank 1: By Phase
2241 23:41:53.186593 ==============================================================
2242 23:41:53.189449 GAT_TRACK_EN = 1
2243 23:41:53.192906 RX_GATING_MODE = 2
2244 23:41:53.196361 RX_GATING_TRACK_MODE = 2
2245 23:41:53.199412 SELPH_MODE = 1
2246 23:41:53.203110 PICG_EARLY_EN = 1
2247 23:41:53.206785 VALID_LAT_VALUE = 1
2248 23:41:53.209964 ==============================================================
2249 23:41:53.212743 Enter into Gating configuration >>>>
2250 23:41:53.216295 Exit from Gating configuration <<<<
2251 23:41:53.219833 Enter into DVFS_PRE_config >>>>>
2252 23:41:53.233278 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2253 23:41:53.233697 Exit from DVFS_PRE_config <<<<<
2254 23:41:53.236582 Enter into PICG configuration >>>>
2255 23:41:53.239742 Exit from PICG configuration <<<<
2256 23:41:53.242867 [RX_INPUT] configuration >>>>>
2257 23:41:53.246475 [RX_INPUT] configuration <<<<<
2258 23:41:53.253325 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2259 23:41:53.256764 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2260 23:41:53.262964 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2261 23:41:53.269675 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2262 23:41:53.276804 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2263 23:41:53.283629 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2264 23:41:53.286540 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2265 23:41:53.289940 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2266 23:41:53.293392 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2267 23:41:53.300527 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2268 23:41:53.303159 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2269 23:41:53.306589 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2270 23:41:53.309834 ===================================
2271 23:41:53.313227 LPDDR4 DRAM CONFIGURATION
2272 23:41:53.316912 ===================================
2273 23:41:53.317476 EX_ROW_EN[0] = 0x0
2274 23:41:53.320139 EX_ROW_EN[1] = 0x0
2275 23:41:53.320554 LP4Y_EN = 0x0
2276 23:41:53.323397 WORK_FSP = 0x0
2277 23:41:53.323968 WL = 0x4
2278 23:41:53.326949 RL = 0x4
2279 23:41:53.327572 BL = 0x2
2280 23:41:53.330337 RPST = 0x0
2281 23:41:53.330891 RD_PRE = 0x0
2282 23:41:53.333536 WR_PRE = 0x1
2283 23:41:53.334103 WR_PST = 0x0
2284 23:41:53.337276 DBI_WR = 0x0
2285 23:41:53.340475 DBI_RD = 0x0
2286 23:41:53.340882 OTF = 0x1
2287 23:41:53.343896 ===================================
2288 23:41:53.347244 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2289 23:41:53.350272 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2290 23:41:53.357228 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2291 23:41:53.360764 ===================================
2292 23:41:53.361350 LPDDR4 DRAM CONFIGURATION
2293 23:41:53.364382 ===================================
2294 23:41:53.367001 EX_ROW_EN[0] = 0x10
2295 23:41:53.370378 EX_ROW_EN[1] = 0x0
2296 23:41:53.370916 LP4Y_EN = 0x0
2297 23:41:53.373738 WORK_FSP = 0x0
2298 23:41:53.374143 WL = 0x4
2299 23:41:53.377340 RL = 0x4
2300 23:41:53.377745 BL = 0x2
2301 23:41:53.380283 RPST = 0x0
2302 23:41:53.380571 RD_PRE = 0x0
2303 23:41:53.383518 WR_PRE = 0x1
2304 23:41:53.383893 WR_PST = 0x0
2305 23:41:53.387070 DBI_WR = 0x0
2306 23:41:53.387311 DBI_RD = 0x0
2307 23:41:53.390555 OTF = 0x1
2308 23:41:53.394065 ===================================
2309 23:41:53.400784 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2310 23:41:53.400932 ==
2311 23:41:53.404237 Dram Type= 6, Freq= 0, CH_0, rank 0
2312 23:41:53.407591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2313 23:41:53.407740 ==
2314 23:41:53.410895 [Duty_Offset_Calibration]
2315 23:41:53.411042 B0:2 B1:-1 CA:1
2316 23:41:53.411159
2317 23:41:53.413759 [DutyScan_Calibration_Flow] k_type=0
2318 23:41:53.422861
2319 23:41:53.423006 ==CLK 0==
2320 23:41:53.426793 Final CLK duty delay cell = -4
2321 23:41:53.429462 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2322 23:41:53.432928 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2323 23:41:53.436265 [-4] AVG Duty = 4953%(X100)
2324 23:41:53.436497
2325 23:41:53.439801 CH0 CLK Duty spec in!! Max-Min= 156%
2326 23:41:53.443174 [DutyScan_Calibration_Flow] ====Done====
2327 23:41:53.443462
2328 23:41:53.446276 [DutyScan_Calibration_Flow] k_type=1
2329 23:41:53.460935
2330 23:41:53.461354 ==DQS 0 ==
2331 23:41:53.464304 Final DQS duty delay cell = -4
2332 23:41:53.467737 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2333 23:41:53.471998 [-4] MIN Duty = 4876%(X100), DQS PI = 10
2334 23:41:53.474730 [-4] AVG Duty = 4938%(X100)
2335 23:41:53.475104
2336 23:41:53.475403 ==DQS 1 ==
2337 23:41:53.478595 Final DQS duty delay cell = -4
2338 23:41:53.481210 [-4] MAX Duty = 5093%(X100), DQS PI = 16
2339 23:41:53.484691 [-4] MIN Duty = 5000%(X100), DQS PI = 44
2340 23:41:53.487781 [-4] AVG Duty = 5046%(X100)
2341 23:41:53.488245
2342 23:41:53.491692 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2343 23:41:53.492132
2344 23:41:53.494884 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2345 23:41:53.497802 [DutyScan_Calibration_Flow] ====Done====
2346 23:41:53.498176
2347 23:41:53.501405 [DutyScan_Calibration_Flow] k_type=3
2348 23:41:53.518651
2349 23:41:53.519033 ==DQM 0 ==
2350 23:41:53.521570 Final DQM duty delay cell = 0
2351 23:41:53.524851 [0] MAX Duty = 5000%(X100), DQS PI = 54
2352 23:41:53.528203 [0] MIN Duty = 4875%(X100), DQS PI = 2
2353 23:41:53.528471 [0] AVG Duty = 4937%(X100)
2354 23:41:53.531561
2355 23:41:53.531765 ==DQM 1 ==
2356 23:41:53.534756 Final DQM duty delay cell = 0
2357 23:41:53.537964 [0] MAX Duty = 5124%(X100), DQS PI = 32
2358 23:41:53.541581 [0] MIN Duty = 4969%(X100), DQS PI = 10
2359 23:41:53.541752 [0] AVG Duty = 5046%(X100)
2360 23:41:53.541887
2361 23:41:53.548003 CH0 DQM 0 Duty spec in!! Max-Min= 125%
2362 23:41:53.548175
2363 23:41:53.551371 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2364 23:41:53.554861 [DutyScan_Calibration_Flow] ====Done====
2365 23:41:53.555049
2366 23:41:53.557917 [DutyScan_Calibration_Flow] k_type=2
2367 23:41:53.573937
2368 23:41:53.574195 ==DQ 0 ==
2369 23:41:53.576947 Final DQ duty delay cell = -4
2370 23:41:53.580479 [-4] MAX Duty = 5062%(X100), DQS PI = 56
2371 23:41:53.584059 [-4] MIN Duty = 4844%(X100), DQS PI = 18
2372 23:41:53.587436 [-4] AVG Duty = 4953%(X100)
2373 23:41:53.587608
2374 23:41:53.587744 ==DQ 1 ==
2375 23:41:53.590292 Final DQ duty delay cell = 0
2376 23:41:53.593978 [0] MAX Duty = 5031%(X100), DQS PI = 18
2377 23:41:53.597218 [0] MIN Duty = 4907%(X100), DQS PI = 46
2378 23:41:53.597419 [0] AVG Duty = 4969%(X100)
2379 23:41:53.600730
2380 23:41:53.604161 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2381 23:41:53.604398
2382 23:41:53.607560 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2383 23:41:53.610800 [DutyScan_Calibration_Flow] ====Done====
2384 23:41:53.611422 ==
2385 23:41:53.614415 Dram Type= 6, Freq= 0, CH_1, rank 0
2386 23:41:53.617911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2387 23:41:53.618342 ==
2388 23:41:53.621019 [Duty_Offset_Calibration]
2389 23:41:53.621450 B0:1 B1:1 CA:2
2390 23:41:53.621794
2391 23:41:53.623966 [DutyScan_Calibration_Flow] k_type=0
2392 23:41:53.634015
2393 23:41:53.634479 ==CLK 0==
2394 23:41:53.638154 Final CLK duty delay cell = 0
2395 23:41:53.641066 [0] MAX Duty = 5156%(X100), DQS PI = 24
2396 23:41:53.644400 [0] MIN Duty = 4938%(X100), DQS PI = 42
2397 23:41:53.645015 [0] AVG Duty = 5047%(X100)
2398 23:41:53.645516
2399 23:41:53.647447 CH1 CLK Duty spec in!! Max-Min= 218%
2400 23:41:53.654634 [DutyScan_Calibration_Flow] ====Done====
2401 23:41:53.655052
2402 23:41:53.657612 [DutyScan_Calibration_Flow] k_type=1
2403 23:41:53.673355
2404 23:41:53.673526 ==DQS 0 ==
2405 23:41:53.676880 Final DQS duty delay cell = 0
2406 23:41:53.680170 [0] MAX Duty = 5031%(X100), DQS PI = 18
2407 23:41:53.683452 [0] MIN Duty = 4813%(X100), DQS PI = 50
2408 23:41:53.683567 [0] AVG Duty = 4922%(X100)
2409 23:41:53.686888
2410 23:41:53.686988 ==DQS 1 ==
2411 23:41:53.689968 Final DQS duty delay cell = 0
2412 23:41:53.693504 [0] MAX Duty = 5062%(X100), DQS PI = 60
2413 23:41:53.697033 [0] MIN Duty = 4907%(X100), DQS PI = 16
2414 23:41:53.697124 [0] AVG Duty = 4984%(X100)
2415 23:41:53.700076
2416 23:41:53.703280 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2417 23:41:53.703429
2418 23:41:53.707361 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2419 23:41:53.710168 [DutyScan_Calibration_Flow] ====Done====
2420 23:41:53.710248
2421 23:41:53.713385 [DutyScan_Calibration_Flow] k_type=3
2422 23:41:53.729774
2423 23:41:53.729919 ==DQM 0 ==
2424 23:41:53.733256 Final DQM duty delay cell = 0
2425 23:41:53.736700 [0] MAX Duty = 5093%(X100), DQS PI = 18
2426 23:41:53.740154 [0] MIN Duty = 4907%(X100), DQS PI = 48
2427 23:41:53.740276 [0] AVG Duty = 5000%(X100)
2428 23:41:53.743491
2429 23:41:53.743611 ==DQM 1 ==
2430 23:41:53.747118 Final DQM duty delay cell = 0
2431 23:41:53.750831 [0] MAX Duty = 5156%(X100), DQS PI = 62
2432 23:41:53.754228 [0] MIN Duty = 4938%(X100), DQS PI = 22
2433 23:41:53.754652 [0] AVG Duty = 5047%(X100)
2434 23:41:53.755111
2435 23:41:53.757201 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2436 23:41:53.760952
2437 23:41:53.764042 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2438 23:41:53.767511 [DutyScan_Calibration_Flow] ====Done====
2439 23:41:53.768168
2440 23:41:53.770464 [DutyScan_Calibration_Flow] k_type=2
2441 23:41:53.786371
2442 23:41:53.786571 ==DQ 0 ==
2443 23:41:53.789930 Final DQ duty delay cell = 0
2444 23:41:53.793080 [0] MAX Duty = 5124%(X100), DQS PI = 18
2445 23:41:53.796217 [0] MIN Duty = 4938%(X100), DQS PI = 14
2446 23:41:53.796373 [0] AVG Duty = 5031%(X100)
2447 23:41:53.796514
2448 23:41:53.799900 ==DQ 1 ==
2449 23:41:53.803450 Final DQ duty delay cell = 0
2450 23:41:53.806614 [0] MAX Duty = 5093%(X100), DQS PI = 8
2451 23:41:53.809995 [0] MIN Duty = 5031%(X100), DQS PI = 2
2452 23:41:53.810097 [0] AVG Duty = 5062%(X100)
2453 23:41:53.810190
2454 23:41:53.813237 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2455 23:41:53.813319
2456 23:41:53.816691 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2457 23:41:53.820009 [DutyScan_Calibration_Flow] ====Done====
2458 23:41:53.825520 nWR fixed to 30
2459 23:41:53.828730 [ModeRegInit_LP4] CH0 RK0
2460 23:41:53.828859 [ModeRegInit_LP4] CH0 RK1
2461 23:41:53.832285 [ModeRegInit_LP4] CH1 RK0
2462 23:41:53.835067 [ModeRegInit_LP4] CH1 RK1
2463 23:41:53.835199 match AC timing 7
2464 23:41:53.841958 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2465 23:41:53.845494 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2466 23:41:53.848638 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2467 23:41:53.855112 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2468 23:41:53.858613 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2469 23:41:53.858691 ==
2470 23:41:53.862358 Dram Type= 6, Freq= 0, CH_0, rank 0
2471 23:41:53.865709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2472 23:41:53.865792 ==
2473 23:41:53.871958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2474 23:41:53.878917 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2475 23:41:53.886809 [CA 0] Center 40 (10~71) winsize 62
2476 23:41:53.889732 [CA 1] Center 39 (9~70) winsize 62
2477 23:41:53.892932 [CA 2] Center 36 (6~67) winsize 62
2478 23:41:53.896162 [CA 3] Center 36 (5~67) winsize 63
2479 23:41:53.899524 [CA 4] Center 35 (5~65) winsize 61
2480 23:41:53.902830 [CA 5] Center 34 (4~64) winsize 61
2481 23:41:53.902973
2482 23:41:53.906839 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2483 23:41:53.906991
2484 23:41:53.910428 [CATrainingPosCal] consider 1 rank data
2485 23:41:53.913147 u2DelayCellTimex100 = 270/100 ps
2486 23:41:53.916284 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2487 23:41:53.919950 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2488 23:41:53.926812 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2489 23:41:53.930001 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2490 23:41:53.933245 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2491 23:41:53.937058 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2492 23:41:53.937129
2493 23:41:53.940010 CA PerBit enable=1, Macro0, CA PI delay=34
2494 23:41:53.940083
2495 23:41:53.943775 [CBTSetCACLKResult] CA Dly = 34
2496 23:41:53.943851 CS Dly: 7 (0~38)
2497 23:41:53.943919 ==
2498 23:41:53.946488 Dram Type= 6, Freq= 0, CH_0, rank 1
2499 23:41:53.953426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2500 23:41:53.953505 ==
2501 23:41:53.956590 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2502 23:41:53.963838 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2503 23:41:53.972163 [CA 0] Center 39 (9~70) winsize 62
2504 23:41:53.975705 [CA 1] Center 39 (9~70) winsize 62
2505 23:41:53.979003 [CA 2] Center 36 (6~67) winsize 62
2506 23:41:53.982491 [CA 3] Center 36 (6~67) winsize 62
2507 23:41:53.985708 [CA 4] Center 34 (4~65) winsize 62
2508 23:41:53.988812 [CA 5] Center 34 (4~64) winsize 61
2509 23:41:53.988937
2510 23:41:53.992053 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2511 23:41:53.992177
2512 23:41:53.996096 [CATrainingPosCal] consider 2 rank data
2513 23:41:53.999424 u2DelayCellTimex100 = 270/100 ps
2514 23:41:54.002366 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2515 23:41:54.005788 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2516 23:41:54.009258 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2517 23:41:54.015853 CA3 delay=36 (6~67),Diff = 2 PI (9 cell)
2518 23:41:54.019253 CA4 delay=35 (5~65),Diff = 1 PI (4 cell)
2519 23:41:54.022905 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2520 23:41:54.023323
2521 23:41:54.026393 CA PerBit enable=1, Macro0, CA PI delay=34
2522 23:41:54.026997
2523 23:41:54.029353 [CBTSetCACLKResult] CA Dly = 34
2524 23:41:54.029937 CS Dly: 8 (0~41)
2525 23:41:54.030299
2526 23:41:54.032678 ----->DramcWriteLeveling(PI) begin...
2527 23:41:54.033297 ==
2528 23:41:54.036341 Dram Type= 6, Freq= 0, CH_0, rank 0
2529 23:41:54.043052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2530 23:41:54.043472 ==
2531 23:41:54.046213 Write leveling (Byte 0): 30 => 30
2532 23:41:54.049812 Write leveling (Byte 1): 30 => 30
2533 23:41:54.050231 DramcWriteLeveling(PI) end<-----
2534 23:41:54.050560
2535 23:41:54.053303 ==
2536 23:41:54.056280 Dram Type= 6, Freq= 0, CH_0, rank 0
2537 23:41:54.059624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2538 23:41:54.060158 ==
2539 23:41:54.063348 [Gating] SW mode calibration
2540 23:41:54.070237 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2541 23:41:54.073380 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2542 23:41:54.080071 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 23:41:54.083897 0 15 4 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
2544 23:41:54.086341 0 15 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2545 23:41:54.089624 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2546 23:41:54.096511 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2547 23:41:54.100050 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2548 23:41:54.103163 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2549 23:41:54.110360 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2550 23:41:54.113757 1 0 0 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
2551 23:41:54.116866 1 0 4 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
2552 23:41:54.123461 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 23:41:54.127185 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 23:41:54.130352 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2555 23:41:54.136842 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2556 23:41:54.140040 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2557 23:41:54.143819 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2558 23:41:54.147426 1 1 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2559 23:41:54.153999 1 1 4 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
2560 23:41:54.157220 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 23:41:54.160759 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 23:41:54.167764 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2563 23:41:54.170617 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2564 23:41:54.174077 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 23:41:54.180602 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 23:41:54.184193 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2567 23:41:54.187451 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2568 23:41:54.194398 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 23:41:54.197790 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 23:41:54.200865 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 23:41:54.204636 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 23:41:54.211267 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 23:41:54.214726 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 23:41:54.217505 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 23:41:54.224396 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 23:41:54.227713 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 23:41:54.231142 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 23:41:54.237989 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2579 23:41:54.241221 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2580 23:41:54.244565 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2581 23:41:54.251571 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2582 23:41:54.254926 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2583 23:41:54.258226 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2584 23:41:54.264439 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 23:41:54.264862 Total UI for P1: 0, mck2ui 16
2586 23:41:54.268279 best dqsien dly found for B0: ( 1, 4, 2)
2587 23:41:54.271300 Total UI for P1: 0, mck2ui 16
2588 23:41:54.275056 best dqsien dly found for B1: ( 1, 4, 2)
2589 23:41:54.277973 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2590 23:41:54.281691 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2591 23:41:54.285182
2592 23:41:54.288301 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2593 23:41:54.291888 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2594 23:41:54.292433 [Gating] SW calibration Done
2595 23:41:54.294760 ==
2596 23:41:54.298323 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 23:41:54.301993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 23:41:54.302646 ==
2599 23:41:54.303026 RX Vref Scan: 0
2600 23:41:54.303422
2601 23:41:54.305302 RX Vref 0 -> 0, step: 1
2602 23:41:54.305759
2603 23:41:54.308564 RX Delay -40 -> 252, step: 8
2604 23:41:54.312217 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2605 23:41:54.314974 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2606 23:41:54.318408 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2607 23:41:54.325643 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2608 23:41:54.328758 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2609 23:41:54.332008 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2610 23:41:54.335128 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2611 23:41:54.338436 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2612 23:41:54.345193 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2613 23:41:54.348435 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2614 23:41:54.351767 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2615 23:41:54.355264 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2616 23:41:54.358565 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2617 23:41:54.361919 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2618 23:41:54.368412 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2619 23:41:54.371676 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2620 23:41:54.372134 ==
2621 23:41:54.375077 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 23:41:54.378752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 23:41:54.379299 ==
2624 23:41:54.381938 DQS Delay:
2625 23:41:54.382391 DQS0 = 0, DQS1 = 0
2626 23:41:54.382753 DQM Delay:
2627 23:41:54.385064 DQM0 = 114, DQM1 = 106
2628 23:41:54.385612 DQ Delay:
2629 23:41:54.388685 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2630 23:41:54.392264 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2631 23:41:54.395316 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2632 23:41:54.402218 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2633 23:41:54.402765
2634 23:41:54.403118
2635 23:41:54.403448 ==
2636 23:41:54.405057 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 23:41:54.409031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 23:41:54.409592 ==
2639 23:41:54.409954
2640 23:41:54.410287
2641 23:41:54.411805 TX Vref Scan disable
2642 23:41:54.412257 == TX Byte 0 ==
2643 23:41:54.418529 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2644 23:41:54.421867 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2645 23:41:54.422327 == TX Byte 1 ==
2646 23:41:54.428776 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2647 23:41:54.432575 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2648 23:41:54.433176 ==
2649 23:41:54.435921 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 23:41:54.438947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 23:41:54.439503 ==
2652 23:41:54.450919 TX Vref=22, minBit 7, minWin=24, winSum=418
2653 23:41:54.454181 TX Vref=24, minBit 5, minWin=25, winSum=422
2654 23:41:54.457924 TX Vref=26, minBit 1, minWin=25, winSum=424
2655 23:41:54.461137 TX Vref=28, minBit 0, minWin=26, winSum=425
2656 23:41:54.465037 TX Vref=30, minBit 3, minWin=26, winSum=430
2657 23:41:54.468042 TX Vref=32, minBit 0, minWin=26, winSum=430
2658 23:41:54.474838 [TxChooseVref] Worse bit 3, Min win 26, Win sum 430, Final Vref 30
2659 23:41:54.475309
2660 23:41:54.478313 Final TX Range 1 Vref 30
2661 23:41:54.478862
2662 23:41:54.479222 ==
2663 23:41:54.481588 Dram Type= 6, Freq= 0, CH_0, rank 0
2664 23:41:54.484605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2665 23:41:54.485099 ==
2666 23:41:54.485468
2667 23:41:54.485801
2668 23:41:54.487991 TX Vref Scan disable
2669 23:41:54.491270 == TX Byte 0 ==
2670 23:41:54.494738 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2671 23:41:54.498167 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2672 23:41:54.501492 == TX Byte 1 ==
2673 23:41:54.505057 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2674 23:41:54.508358 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2675 23:41:54.508773
2676 23:41:54.511277 [DATLAT]
2677 23:41:54.511683 Freq=1200, CH0 RK0
2678 23:41:54.512007
2679 23:41:54.515108 DATLAT Default: 0xd
2680 23:41:54.515517 0, 0xFFFF, sum = 0
2681 23:41:54.518319 1, 0xFFFF, sum = 0
2682 23:41:54.518975 2, 0xFFFF, sum = 0
2683 23:41:54.522171 3, 0xFFFF, sum = 0
2684 23:41:54.522730 4, 0xFFFF, sum = 0
2685 23:41:54.524747 5, 0xFFFF, sum = 0
2686 23:41:54.525358 6, 0xFFFF, sum = 0
2687 23:41:54.528284 7, 0xFFFF, sum = 0
2688 23:41:54.528875 8, 0xFFFF, sum = 0
2689 23:41:54.531664 9, 0xFFFF, sum = 0
2690 23:41:54.532121 10, 0xFFFF, sum = 0
2691 23:41:54.535264 11, 0xFFFF, sum = 0
2692 23:41:54.535700 12, 0x0, sum = 1
2693 23:41:54.538234 13, 0x0, sum = 2
2694 23:41:54.538657 14, 0x0, sum = 3
2695 23:41:54.541647 15, 0x0, sum = 4
2696 23:41:54.542211 best_step = 13
2697 23:41:54.542700
2698 23:41:54.543028 ==
2699 23:41:54.544751 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 23:41:54.548215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 23:41:54.551748 ==
2702 23:41:54.552313 RX Vref Scan: 1
2703 23:41:54.552865
2704 23:41:54.554696 Set Vref Range= 32 -> 127
2705 23:41:54.555232
2706 23:41:54.558478 RX Vref 32 -> 127, step: 1
2707 23:41:54.558917
2708 23:41:54.559302 RX Delay -21 -> 252, step: 4
2709 23:41:54.559656
2710 23:41:54.561583 Set Vref, RX VrefLevel [Byte0]: 32
2711 23:41:54.564889 [Byte1]: 32
2712 23:41:54.569318
2713 23:41:54.569733 Set Vref, RX VrefLevel [Byte0]: 33
2714 23:41:54.572879 [Byte1]: 33
2715 23:41:54.576860
2716 23:41:54.577321 Set Vref, RX VrefLevel [Byte0]: 34
2717 23:41:54.580487 [Byte1]: 34
2718 23:41:54.585109
2719 23:41:54.585524 Set Vref, RX VrefLevel [Byte0]: 35
2720 23:41:54.588795 [Byte1]: 35
2721 23:41:54.592733
2722 23:41:54.593270 Set Vref, RX VrefLevel [Byte0]: 36
2723 23:41:54.596337 [Byte1]: 36
2724 23:41:54.600551
2725 23:41:54.600964 Set Vref, RX VrefLevel [Byte0]: 37
2726 23:41:54.604125 [Byte1]: 37
2727 23:41:54.608548
2728 23:41:54.609048 Set Vref, RX VrefLevel [Byte0]: 38
2729 23:41:54.612035 [Byte1]: 38
2730 23:41:54.616615
2731 23:41:54.617040 Set Vref, RX VrefLevel [Byte0]: 39
2732 23:41:54.619858 [Byte1]: 39
2733 23:41:54.624570
2734 23:41:54.625040 Set Vref, RX VrefLevel [Byte0]: 40
2735 23:41:54.628039 [Byte1]: 40
2736 23:41:54.632604
2737 23:41:54.633051 Set Vref, RX VrefLevel [Byte0]: 41
2738 23:41:54.636178 [Byte1]: 41
2739 23:41:54.640906
2740 23:41:54.641353 Set Vref, RX VrefLevel [Byte0]: 42
2741 23:41:54.643515 [Byte1]: 42
2742 23:41:54.648209
2743 23:41:54.648618 Set Vref, RX VrefLevel [Byte0]: 43
2744 23:41:54.651650 [Byte1]: 43
2745 23:41:54.656189
2746 23:41:54.656596 Set Vref, RX VrefLevel [Byte0]: 44
2747 23:41:54.659824 [Byte1]: 44
2748 23:41:54.664038
2749 23:41:54.664446 Set Vref, RX VrefLevel [Byte0]: 45
2750 23:41:54.667594 [Byte1]: 45
2751 23:41:54.672349
2752 23:41:54.672775 Set Vref, RX VrefLevel [Byte0]: 46
2753 23:41:54.675405 [Byte1]: 46
2754 23:41:54.679722
2755 23:41:54.680311 Set Vref, RX VrefLevel [Byte0]: 47
2756 23:41:54.683477 [Byte1]: 47
2757 23:41:54.688268
2758 23:41:54.688811 Set Vref, RX VrefLevel [Byte0]: 48
2759 23:41:54.691131 [Byte1]: 48
2760 23:41:54.695866
2761 23:41:54.696277 Set Vref, RX VrefLevel [Byte0]: 49
2762 23:41:54.699188 [Byte1]: 49
2763 23:41:54.703975
2764 23:41:54.704430 Set Vref, RX VrefLevel [Byte0]: 50
2765 23:41:54.707155 [Byte1]: 50
2766 23:41:54.712310
2767 23:41:54.712720 Set Vref, RX VrefLevel [Byte0]: 51
2768 23:41:54.715334 [Byte1]: 51
2769 23:41:54.719973
2770 23:41:54.720384 Set Vref, RX VrefLevel [Byte0]: 52
2771 23:41:54.722903 [Byte1]: 52
2772 23:41:54.727450
2773 23:41:54.727872 Set Vref, RX VrefLevel [Byte0]: 53
2774 23:41:54.730850 [Byte1]: 53
2775 23:41:54.735440
2776 23:41:54.735859 Set Vref, RX VrefLevel [Byte0]: 54
2777 23:41:54.738930 [Byte1]: 54
2778 23:41:54.743345
2779 23:41:54.743868 Set Vref, RX VrefLevel [Byte0]: 55
2780 23:41:54.746781 [Byte1]: 55
2781 23:41:54.751278
2782 23:41:54.751693 Set Vref, RX VrefLevel [Byte0]: 56
2783 23:41:54.754512 [Byte1]: 56
2784 23:41:54.759156
2785 23:41:54.759577 Set Vref, RX VrefLevel [Byte0]: 57
2786 23:41:54.762817 [Byte1]: 57
2787 23:41:54.767069
2788 23:41:54.767472 Set Vref, RX VrefLevel [Byte0]: 58
2789 23:41:54.770878 [Byte1]: 58
2790 23:41:54.774891
2791 23:41:54.775289 Set Vref, RX VrefLevel [Byte0]: 59
2792 23:41:54.778695 [Byte1]: 59
2793 23:41:54.783259
2794 23:41:54.783686 Set Vref, RX VrefLevel [Byte0]: 60
2795 23:41:54.786550 [Byte1]: 60
2796 23:41:54.790678
2797 23:41:54.791080 Set Vref, RX VrefLevel [Byte0]: 61
2798 23:41:54.794082 [Byte1]: 61
2799 23:41:54.799443
2800 23:41:54.799850 Set Vref, RX VrefLevel [Byte0]: 62
2801 23:41:54.802129 [Byte1]: 62
2802 23:41:54.807419
2803 23:41:54.807829 Set Vref, RX VrefLevel [Byte0]: 63
2804 23:41:54.810517 [Byte1]: 63
2805 23:41:54.814934
2806 23:41:54.815374 Set Vref, RX VrefLevel [Byte0]: 64
2807 23:41:54.817975 [Byte1]: 64
2808 23:41:54.822878
2809 23:41:54.823344 Set Vref, RX VrefLevel [Byte0]: 65
2810 23:41:54.826146 [Byte1]: 65
2811 23:41:54.831302
2812 23:41:54.831732 Set Vref, RX VrefLevel [Byte0]: 66
2813 23:41:54.834404 [Byte1]: 66
2814 23:41:54.838634
2815 23:41:54.841821 Set Vref, RX VrefLevel [Byte0]: 67
2816 23:41:54.842239 [Byte1]: 67
2817 23:41:54.846404
2818 23:41:54.846847 Set Vref, RX VrefLevel [Byte0]: 68
2819 23:41:54.849753 [Byte1]: 68
2820 23:41:54.854593
2821 23:41:54.855008 Final RX Vref Byte 0 = 51 to rank0
2822 23:41:54.857747 Final RX Vref Byte 1 = 52 to rank0
2823 23:41:54.861228 Final RX Vref Byte 0 = 51 to rank1
2824 23:41:54.864586 Final RX Vref Byte 1 = 52 to rank1==
2825 23:41:54.868270 Dram Type= 6, Freq= 0, CH_0, rank 0
2826 23:41:54.871639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2827 23:41:54.874656 ==
2828 23:41:54.875087 DQS Delay:
2829 23:41:54.875521 DQS0 = 0, DQS1 = 0
2830 23:41:54.878126 DQM Delay:
2831 23:41:54.878558 DQM0 = 115, DQM1 = 105
2832 23:41:54.881097 DQ Delay:
2833 23:41:54.884407 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =114
2834 23:41:54.887779 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2835 23:41:54.891157 DQ8 =94, DQ9 =90, DQ10 =104, DQ11 =96
2836 23:41:54.894488 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2837 23:41:54.894927
2838 23:41:54.895254
2839 23:41:54.901482 [DQSOSCAuto] RK0, (LSB)MR18= 0xfeed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 410 ps
2840 23:41:54.904870 CH0 RK0: MR19=303, MR18=FEED
2841 23:41:54.911674 CH0_RK0: MR19=0x303, MR18=0xFEED, DQSOSC=410, MR23=63, INC=39, DEC=26
2842 23:41:54.912347
2843 23:41:54.915074 ----->DramcWriteLeveling(PI) begin...
2844 23:41:54.915484 ==
2845 23:41:54.918123 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 23:41:54.921590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 23:41:54.921999 ==
2848 23:41:54.924885 Write leveling (Byte 0): 32 => 32
2849 23:41:54.928449 Write leveling (Byte 1): 29 => 29
2850 23:41:54.932043 DramcWriteLeveling(PI) end<-----
2851 23:41:54.932709
2852 23:41:54.933220 ==
2853 23:41:54.934998 Dram Type= 6, Freq= 0, CH_0, rank 1
2854 23:41:54.938627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2855 23:41:54.939111 ==
2856 23:41:54.941968 [Gating] SW mode calibration
2857 23:41:54.948771 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2858 23:41:54.954976 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2859 23:41:54.958840 0 15 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
2860 23:41:54.965381 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
2861 23:41:54.968751 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 23:41:54.971904 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 23:41:54.975513 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 23:41:54.982044 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 23:41:54.985355 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2866 23:41:54.988619 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 1)
2867 23:41:54.995158 1 0 0 | B1->B0 | 2d2d 2323 | 1 1 | (0 1) (0 0)
2868 23:41:54.998476 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2869 23:41:55.001985 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 23:41:55.008615 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 23:41:55.011809 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 23:41:55.015555 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 23:41:55.022558 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2874 23:41:55.025452 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2875 23:41:55.029321 1 1 0 | B1->B0 | 3433 3e3e | 1 0 | (0 0) (0 0)
2876 23:41:55.035782 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 23:41:55.038496 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 23:41:55.041962 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 23:41:55.045338 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 23:41:55.052297 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 23:41:55.055570 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 23:41:55.058731 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2883 23:41:55.065335 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2884 23:41:55.068775 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2885 23:41:55.071839 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 23:41:55.079171 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 23:41:55.082526 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 23:41:55.085641 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 23:41:55.092596 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 23:41:55.096365 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 23:41:55.099530 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 23:41:55.103152 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 23:41:55.109552 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 23:41:55.112893 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 23:41:55.115842 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 23:41:55.123268 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 23:41:55.126355 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 23:41:55.129952 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2899 23:41:55.135855 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2900 23:41:55.136267 Total UI for P1: 0, mck2ui 16
2901 23:41:55.143036 best dqsien dly found for B0: ( 1, 3, 28)
2902 23:41:55.146468 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2903 23:41:55.149783 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 23:41:55.152690 Total UI for P1: 0, mck2ui 16
2905 23:41:55.156314 best dqsien dly found for B1: ( 1, 4, 2)
2906 23:41:55.159948 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2907 23:41:55.163092 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2908 23:41:55.163550
2909 23:41:55.166587 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2910 23:41:55.173050 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2911 23:41:55.173599 [Gating] SW calibration Done
2912 23:41:55.173965 ==
2913 23:41:55.176014 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 23:41:55.183056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 23:41:55.183547 ==
2916 23:41:55.183906 RX Vref Scan: 0
2917 23:41:55.184241
2918 23:41:55.186269 RX Vref 0 -> 0, step: 1
2919 23:41:55.186790
2920 23:41:55.189540 RX Delay -40 -> 252, step: 8
2921 23:41:55.193015 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2922 23:41:55.196676 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2923 23:41:55.200061 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2924 23:41:55.203195 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2925 23:41:55.210320 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2926 23:41:55.213371 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2927 23:41:55.216515 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2928 23:41:55.220272 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2929 23:41:55.223368 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2930 23:41:55.226840 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2931 23:41:55.233226 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2932 23:41:55.237040 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2933 23:41:55.240498 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2934 23:41:55.243807 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2935 23:41:55.246604 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2936 23:41:55.253467 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2937 23:41:55.254016 ==
2938 23:41:55.257049 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 23:41:55.260404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 23:41:55.261036 ==
2941 23:41:55.261418 DQS Delay:
2942 23:41:55.263182 DQS0 = 0, DQS1 = 0
2943 23:41:55.263633 DQM Delay:
2944 23:41:55.267308 DQM0 = 115, DQM1 = 106
2945 23:41:55.267875 DQ Delay:
2946 23:41:55.270235 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2947 23:41:55.273681 DQ4 =115, DQ5 =103, DQ6 =123, DQ7 =123
2948 23:41:55.277017 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2949 23:41:55.280750 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2950 23:41:55.281238
2951 23:41:55.281600
2952 23:41:55.283509 ==
2953 23:41:55.283961 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 23:41:55.290404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 23:41:55.290820 ==
2956 23:41:55.291142
2957 23:41:55.291441
2958 23:41:55.291732 TX Vref Scan disable
2959 23:41:55.294097 == TX Byte 0 ==
2960 23:41:55.297492 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2961 23:41:55.300910 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2962 23:41:55.304243 == TX Byte 1 ==
2963 23:41:55.307569 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2964 23:41:55.310874 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2965 23:41:55.314118 ==
2966 23:41:55.314527 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 23:41:55.321180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 23:41:55.321599 ==
2969 23:41:55.332230 TX Vref=22, minBit 0, minWin=25, winSum=425
2970 23:41:55.335351 TX Vref=24, minBit 1, minWin=26, winSum=431
2971 23:41:55.339230 TX Vref=26, minBit 4, minWin=26, winSum=434
2972 23:41:55.342296 TX Vref=28, minBit 12, minWin=26, winSum=436
2973 23:41:55.345863 TX Vref=30, minBit 0, minWin=27, winSum=440
2974 23:41:55.348642 TX Vref=32, minBit 12, minWin=26, winSum=436
2975 23:41:55.355853 [TxChooseVref] Worse bit 0, Min win 27, Win sum 440, Final Vref 30
2976 23:41:55.356372
2977 23:41:55.358725 Final TX Range 1 Vref 30
2978 23:41:55.359146
2979 23:41:55.359475 ==
2980 23:41:55.362572 Dram Type= 6, Freq= 0, CH_0, rank 1
2981 23:41:55.365788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2982 23:41:55.366208 ==
2983 23:41:55.366538
2984 23:41:55.369304
2985 23:41:55.369784 TX Vref Scan disable
2986 23:41:55.372399 == TX Byte 0 ==
2987 23:41:55.376028 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2988 23:41:55.379410 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2989 23:41:55.382415 == TX Byte 1 ==
2990 23:41:55.385850 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2991 23:41:55.388918 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2992 23:41:55.389375
2993 23:41:55.392869 [DATLAT]
2994 23:41:55.393331 Freq=1200, CH0 RK1
2995 23:41:55.393668
2996 23:41:55.396103 DATLAT Default: 0xd
2997 23:41:55.396512 0, 0xFFFF, sum = 0
2998 23:41:55.399150 1, 0xFFFF, sum = 0
2999 23:41:55.399565 2, 0xFFFF, sum = 0
3000 23:41:55.402561 3, 0xFFFF, sum = 0
3001 23:41:55.402981 4, 0xFFFF, sum = 0
3002 23:41:55.405765 5, 0xFFFF, sum = 0
3003 23:41:55.406184 6, 0xFFFF, sum = 0
3004 23:41:55.409461 7, 0xFFFF, sum = 0
3005 23:41:55.409984 8, 0xFFFF, sum = 0
3006 23:41:55.412689 9, 0xFFFF, sum = 0
3007 23:41:55.413139 10, 0xFFFF, sum = 0
3008 23:41:55.415787 11, 0xFFFF, sum = 0
3009 23:41:55.416200 12, 0x0, sum = 1
3010 23:41:55.419863 13, 0x0, sum = 2
3011 23:41:55.420379 14, 0x0, sum = 3
3012 23:41:55.422627 15, 0x0, sum = 4
3013 23:41:55.423147 best_step = 13
3014 23:41:55.423469
3015 23:41:55.423775 ==
3016 23:41:55.425958 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 23:41:55.432901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 23:41:55.433655 ==
3019 23:41:55.434009 RX Vref Scan: 0
3020 23:41:55.434316
3021 23:41:55.435942 RX Vref 0 -> 0, step: 1
3022 23:41:55.436351
3023 23:41:55.439492 RX Delay -21 -> 252, step: 4
3024 23:41:55.443091 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3025 23:41:55.446581 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3026 23:41:55.449974 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3027 23:41:55.456778 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3028 23:41:55.459551 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3029 23:41:55.463564 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3030 23:41:55.466981 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3031 23:41:55.470143 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3032 23:41:55.476431 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3033 23:41:55.480101 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3034 23:41:55.484078 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3035 23:41:55.486481 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3036 23:41:55.490192 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3037 23:41:55.496899 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3038 23:41:55.500359 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3039 23:41:55.503161 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3040 23:41:55.503710 ==
3041 23:41:55.506706 Dram Type= 6, Freq= 0, CH_0, rank 1
3042 23:41:55.510000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3043 23:41:55.510553 ==
3044 23:41:55.513542 DQS Delay:
3045 23:41:55.513998 DQS0 = 0, DQS1 = 0
3046 23:41:55.514360 DQM Delay:
3047 23:41:55.517177 DQM0 = 114, DQM1 = 104
3048 23:41:55.517632 DQ Delay:
3049 23:41:55.520613 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3050 23:41:55.524026 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3051 23:41:55.527474 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3052 23:41:55.533607 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114
3053 23:41:55.534145
3054 23:41:55.534503
3055 23:41:55.540196 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 410 ps
3056 23:41:55.543677 CH0 RK1: MR19=403, MR18=F1
3057 23:41:55.546804 CH0_RK1: MR19=0x403, MR18=0xF1, DQSOSC=410, MR23=63, INC=39, DEC=26
3058 23:41:55.550093 [RxdqsGatingPostProcess] freq 1200
3059 23:41:55.557096 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3060 23:41:55.560300 best DQS0 dly(2T, 0.5T) = (0, 12)
3061 23:41:55.563990 best DQS1 dly(2T, 0.5T) = (0, 12)
3062 23:41:55.566922 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3063 23:41:55.570261 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3064 23:41:55.573680 best DQS0 dly(2T, 0.5T) = (0, 11)
3065 23:41:55.576940 best DQS1 dly(2T, 0.5T) = (0, 12)
3066 23:41:55.580704 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3067 23:41:55.583759 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3068 23:41:55.584308 Pre-setting of DQS Precalculation
3069 23:41:55.590377 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3070 23:41:55.590930 ==
3071 23:41:55.593577 Dram Type= 6, Freq= 0, CH_1, rank 0
3072 23:41:55.597049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 23:41:55.597598 ==
3074 23:41:55.603635 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3075 23:41:55.610314 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3076 23:41:55.617581 [CA 0] Center 38 (9~68) winsize 60
3077 23:41:55.621419 [CA 1] Center 38 (8~68) winsize 61
3078 23:41:55.624625 [CA 2] Center 35 (5~65) winsize 61
3079 23:41:55.627635 [CA 3] Center 34 (4~65) winsize 62
3080 23:41:55.631390 [CA 4] Center 34 (4~65) winsize 62
3081 23:41:55.634460 [CA 5] Center 33 (4~63) winsize 60
3082 23:41:55.634921
3083 23:41:55.637569 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3084 23:41:55.638028
3085 23:41:55.641227 [CATrainingPosCal] consider 1 rank data
3086 23:41:55.644411 u2DelayCellTimex100 = 270/100 ps
3087 23:41:55.647886 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3088 23:41:55.651682 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3089 23:41:55.654508 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3090 23:41:55.661680 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3091 23:41:55.664279 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3092 23:41:55.667784 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3093 23:41:55.668308
3094 23:41:55.671482 CA PerBit enable=1, Macro0, CA PI delay=33
3095 23:41:55.671937
3096 23:41:55.674939 [CBTSetCACLKResult] CA Dly = 33
3097 23:41:55.675394 CS Dly: 6 (0~37)
3098 23:41:55.675752 ==
3099 23:41:55.677815 Dram Type= 6, Freq= 0, CH_1, rank 1
3100 23:41:55.684841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3101 23:41:55.685300 ==
3102 23:41:55.688431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3103 23:41:55.694416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3104 23:41:55.703608 [CA 0] Center 38 (8~68) winsize 61
3105 23:41:55.706704 [CA 1] Center 38 (8~68) winsize 61
3106 23:41:55.709801 [CA 2] Center 34 (4~65) winsize 62
3107 23:41:55.713089 [CA 3] Center 34 (4~65) winsize 62
3108 23:41:55.716570 [CA 4] Center 34 (4~65) winsize 62
3109 23:41:55.719807 [CA 5] Center 33 (3~63) winsize 61
3110 23:41:55.720216
3111 23:41:55.723142 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3112 23:41:55.723553
3113 23:41:55.726612 [CATrainingPosCal] consider 2 rank data
3114 23:41:55.729905 u2DelayCellTimex100 = 270/100 ps
3115 23:41:55.733061 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3116 23:41:55.736402 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3117 23:41:55.740166 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3118 23:41:55.746819 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3119 23:41:55.750386 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3120 23:41:55.753422 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3121 23:41:55.753979
3122 23:41:55.756946 CA PerBit enable=1, Macro0, CA PI delay=33
3123 23:41:55.757539
3124 23:41:55.760202 [CBTSetCACLKResult] CA Dly = 33
3125 23:41:55.760825 CS Dly: 7 (0~40)
3126 23:41:55.761272
3127 23:41:55.763310 ----->DramcWriteLeveling(PI) begin...
3128 23:41:55.763974 ==
3129 23:41:55.766571 Dram Type= 6, Freq= 0, CH_1, rank 0
3130 23:41:55.773484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 23:41:55.774097 ==
3132 23:41:55.777218 Write leveling (Byte 0): 28 => 28
3133 23:41:55.780247 Write leveling (Byte 1): 31 => 31
3134 23:41:55.780920 DramcWriteLeveling(PI) end<-----
3135 23:41:55.781514
3136 23:41:55.783693 ==
3137 23:41:55.784229 Dram Type= 6, Freq= 0, CH_1, rank 0
3138 23:41:55.790121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3139 23:41:55.790491 ==
3140 23:41:55.793665 [Gating] SW mode calibration
3141 23:41:55.800176 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3142 23:41:55.803304 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3143 23:41:55.810212 0 15 0 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
3144 23:41:55.813541 0 15 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3145 23:41:55.816860 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 23:41:55.820359 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 23:41:55.827327 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 23:41:55.830580 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 23:41:55.834026 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 23:41:55.840373 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
3151 23:41:55.843478 1 0 0 | B1->B0 | 2828 2e2e | 0 0 | (1 0) (1 0)
3152 23:41:55.846786 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 23:41:55.853406 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 23:41:55.856966 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 23:41:55.860234 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 23:41:55.866974 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3157 23:41:55.870371 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 23:41:55.874277 1 0 28 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
3159 23:41:55.880856 1 1 0 | B1->B0 | 4545 3939 | 0 0 | (0 0) (0 0)
3160 23:41:55.883810 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 23:41:55.887041 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 23:41:55.890383 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 23:41:55.897201 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 23:41:55.900468 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 23:41:55.903690 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 23:41:55.910626 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 23:41:55.913994 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3168 23:41:55.917397 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 23:41:55.924041 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 23:41:55.927425 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 23:41:55.930996 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 23:41:55.937586 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 23:41:55.940514 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 23:41:55.943811 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 23:41:55.950934 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 23:41:55.953905 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 23:41:55.957469 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 23:41:55.964390 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 23:41:55.967868 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 23:41:55.971209 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 23:41:55.974212 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 23:41:55.980838 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3183 23:41:55.984727 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3184 23:41:55.988074 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 23:41:55.991313 Total UI for P1: 0, mck2ui 16
3186 23:41:55.994505 best dqsien dly found for B0: ( 1, 3, 30)
3187 23:41:55.997466 Total UI for P1: 0, mck2ui 16
3188 23:41:56.001401 best dqsien dly found for B1: ( 1, 4, 0)
3189 23:41:56.004570 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3190 23:41:56.007562 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3191 23:41:56.007787
3192 23:41:56.010997 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3193 23:41:56.018007 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3194 23:41:56.018114 [Gating] SW calibration Done
3195 23:41:56.018204 ==
3196 23:41:56.021485 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 23:41:56.028198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 23:41:56.028277 ==
3199 23:41:56.028343 RX Vref Scan: 0
3200 23:41:56.028401
3201 23:41:56.031414 RX Vref 0 -> 0, step: 1
3202 23:41:56.031488
3203 23:41:56.034822 RX Delay -40 -> 252, step: 8
3204 23:41:56.038174 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3205 23:41:56.041265 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3206 23:41:56.044617 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3207 23:41:56.048157 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3208 23:41:56.055063 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3209 23:41:56.058122 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3210 23:41:56.061167 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3211 23:41:56.064970 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3212 23:41:56.067850 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3213 23:41:56.071377 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3214 23:41:56.078318 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3215 23:41:56.081484 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3216 23:41:56.084861 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3217 23:41:56.088214 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3218 23:41:56.094654 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3219 23:41:56.098682 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3220 23:41:56.098782 ==
3221 23:41:56.101353 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 23:41:56.105253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 23:41:56.105387 ==
3224 23:41:56.105511 DQS Delay:
3225 23:41:56.108386 DQS0 = 0, DQS1 = 0
3226 23:41:56.108518 DQM Delay:
3227 23:41:56.111927 DQM0 = 115, DQM1 = 108
3228 23:41:56.112033 DQ Delay:
3229 23:41:56.114811 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3230 23:41:56.118033 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3231 23:41:56.121779 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3232 23:41:56.125168 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3233 23:41:56.125273
3234 23:41:56.125368
3235 23:41:56.128536 ==
3236 23:41:56.131914 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 23:41:56.135096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 23:41:56.135209 ==
3239 23:41:56.135312
3240 23:41:56.135406
3241 23:41:56.138295 TX Vref Scan disable
3242 23:41:56.138409 == TX Byte 0 ==
3243 23:41:56.141851 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3244 23:41:56.148686 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3245 23:41:56.148829 == TX Byte 1 ==
3246 23:41:56.151468 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3247 23:41:56.158137 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3248 23:41:56.158356 ==
3249 23:41:56.161945 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 23:41:56.164907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 23:41:56.165084 ==
3252 23:41:56.177375 TX Vref=22, minBit 2, minWin=25, winSum=416
3253 23:41:56.180864 TX Vref=24, minBit 2, minWin=25, winSum=419
3254 23:41:56.183456 TX Vref=26, minBit 15, minWin=25, winSum=422
3255 23:41:56.187003 TX Vref=28, minBit 15, minWin=25, winSum=428
3256 23:41:56.190525 TX Vref=30, minBit 3, minWin=26, winSum=432
3257 23:41:56.197437 TX Vref=32, minBit 12, minWin=25, winSum=426
3258 23:41:56.200315 [TxChooseVref] Worse bit 3, Min win 26, Win sum 432, Final Vref 30
3259 23:41:56.200434
3260 23:41:56.203759 Final TX Range 1 Vref 30
3261 23:41:56.203876
3262 23:41:56.203983 ==
3263 23:41:56.207371 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 23:41:56.210398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 23:41:56.210495 ==
3266 23:41:56.210570
3267 23:41:56.214197
3268 23:41:56.214292 TX Vref Scan disable
3269 23:41:56.217281 == TX Byte 0 ==
3270 23:41:56.220839 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3271 23:41:56.224540 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3272 23:41:56.227315 == TX Byte 1 ==
3273 23:41:56.230772 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3274 23:41:56.234357 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3275 23:41:56.234452
3276 23:41:56.237917 [DATLAT]
3277 23:41:56.238010 Freq=1200, CH1 RK0
3278 23:41:56.238094
3279 23:41:56.240669 DATLAT Default: 0xd
3280 23:41:56.240763 0, 0xFFFF, sum = 0
3281 23:41:56.244112 1, 0xFFFF, sum = 0
3282 23:41:56.244207 2, 0xFFFF, sum = 0
3283 23:41:56.247620 3, 0xFFFF, sum = 0
3284 23:41:56.247723 4, 0xFFFF, sum = 0
3285 23:41:56.251186 5, 0xFFFF, sum = 0
3286 23:41:56.251289 6, 0xFFFF, sum = 0
3287 23:41:56.254656 7, 0xFFFF, sum = 0
3288 23:41:56.254809 8, 0xFFFF, sum = 0
3289 23:41:56.257765 9, 0xFFFF, sum = 0
3290 23:41:56.257890 10, 0xFFFF, sum = 0
3291 23:41:56.261037 11, 0xFFFF, sum = 0
3292 23:41:56.261210 12, 0x0, sum = 1
3293 23:41:56.264438 13, 0x0, sum = 2
3294 23:41:56.264576 14, 0x0, sum = 3
3295 23:41:56.267968 15, 0x0, sum = 4
3296 23:41:56.268123 best_step = 13
3297 23:41:56.268249
3298 23:41:56.268430 ==
3299 23:41:56.271253 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 23:41:56.277783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 23:41:56.277955 ==
3302 23:41:56.278127 RX Vref Scan: 1
3303 23:41:56.278300
3304 23:41:56.280763 Set Vref Range= 32 -> 127
3305 23:41:56.280951
3306 23:41:56.284831 RX Vref 32 -> 127, step: 1
3307 23:41:56.284997
3308 23:41:56.285121 RX Delay -21 -> 252, step: 4
3309 23:41:56.287914
3310 23:41:56.288065 Set Vref, RX VrefLevel [Byte0]: 32
3311 23:41:56.291364 [Byte1]: 32
3312 23:41:56.295563
3313 23:41:56.295654 Set Vref, RX VrefLevel [Byte0]: 33
3314 23:41:56.299260 [Byte1]: 33
3315 23:41:56.303440
3316 23:41:56.303551 Set Vref, RX VrefLevel [Byte0]: 34
3317 23:41:56.306615 [Byte1]: 34
3318 23:41:56.310982
3319 23:41:56.311097 Set Vref, RX VrefLevel [Byte0]: 35
3320 23:41:56.314411 [Byte1]: 35
3321 23:41:56.319819
3322 23:41:56.319930 Set Vref, RX VrefLevel [Byte0]: 36
3323 23:41:56.322282 [Byte1]: 36
3324 23:41:56.327399
3325 23:41:56.327469 Set Vref, RX VrefLevel [Byte0]: 37
3326 23:41:56.330888 [Byte1]: 37
3327 23:41:56.335016
3328 23:41:56.335110 Set Vref, RX VrefLevel [Byte0]: 38
3329 23:41:56.338592 [Byte1]: 38
3330 23:41:56.342974
3331 23:41:56.343074 Set Vref, RX VrefLevel [Byte0]: 39
3332 23:41:56.346269 [Byte1]: 39
3333 23:41:56.350595
3334 23:41:56.350697 Set Vref, RX VrefLevel [Byte0]: 40
3335 23:41:56.354319 [Byte1]: 40
3336 23:41:56.359027
3337 23:41:56.359137 Set Vref, RX VrefLevel [Byte0]: 41
3338 23:41:56.362353 [Byte1]: 41
3339 23:41:56.366973
3340 23:41:56.367076 Set Vref, RX VrefLevel [Byte0]: 42
3341 23:41:56.370044 [Byte1]: 42
3342 23:41:56.374792
3343 23:41:56.374876 Set Vref, RX VrefLevel [Byte0]: 43
3344 23:41:56.377700 [Byte1]: 43
3345 23:41:56.382885
3346 23:41:56.382974 Set Vref, RX VrefLevel [Byte0]: 44
3347 23:41:56.385837 [Byte1]: 44
3348 23:41:56.390794
3349 23:41:56.390886 Set Vref, RX VrefLevel [Byte0]: 45
3350 23:41:56.396883 [Byte1]: 45
3351 23:41:56.396988
3352 23:41:56.400376 Set Vref, RX VrefLevel [Byte0]: 46
3353 23:41:56.403881 [Byte1]: 46
3354 23:41:56.403959
3355 23:41:56.407249 Set Vref, RX VrefLevel [Byte0]: 47
3356 23:41:56.410216 [Byte1]: 47
3357 23:41:56.414714
3358 23:41:56.414792 Set Vref, RX VrefLevel [Byte0]: 48
3359 23:41:56.417701 [Byte1]: 48
3360 23:41:56.422072
3361 23:41:56.422150 Set Vref, RX VrefLevel [Byte0]: 49
3362 23:41:56.425549 [Byte1]: 49
3363 23:41:56.430130
3364 23:41:56.430265 Set Vref, RX VrefLevel [Byte0]: 50
3365 23:41:56.433264 [Byte1]: 50
3366 23:41:56.438140
3367 23:41:56.438219 Set Vref, RX VrefLevel [Byte0]: 51
3368 23:41:56.441563 [Byte1]: 51
3369 23:41:56.446177
3370 23:41:56.446259 Set Vref, RX VrefLevel [Byte0]: 52
3371 23:41:56.449612 [Byte1]: 52
3372 23:41:56.453529
3373 23:41:56.453608 Set Vref, RX VrefLevel [Byte0]: 53
3374 23:41:56.457272 [Byte1]: 53
3375 23:41:56.461504
3376 23:41:56.461603 Set Vref, RX VrefLevel [Byte0]: 54
3377 23:41:56.465121 [Byte1]: 54
3378 23:41:56.469990
3379 23:41:56.470069 Set Vref, RX VrefLevel [Byte0]: 55
3380 23:41:56.472871 [Byte1]: 55
3381 23:41:56.477656
3382 23:41:56.477735 Set Vref, RX VrefLevel [Byte0]: 56
3383 23:41:56.481085 [Byte1]: 56
3384 23:41:56.485570
3385 23:41:56.485702 Set Vref, RX VrefLevel [Byte0]: 57
3386 23:41:56.488778 [Byte1]: 57
3387 23:41:56.493515
3388 23:41:56.493702 Set Vref, RX VrefLevel [Byte0]: 58
3389 23:41:56.497006 [Byte1]: 58
3390 23:41:56.501309
3391 23:41:56.501395 Set Vref, RX VrefLevel [Byte0]: 59
3392 23:41:56.504579 [Byte1]: 59
3393 23:41:56.508987
3394 23:41:56.509088 Set Vref, RX VrefLevel [Byte0]: 60
3395 23:41:56.575516 [Byte1]: 60
3396 23:41:56.575653
3397 23:41:56.575719 Set Vref, RX VrefLevel [Byte0]: 61
3398 23:41:56.575778 [Byte1]: 61
3399 23:41:56.575839
3400 23:41:56.575932 Set Vref, RX VrefLevel [Byte0]: 62
3401 23:41:56.576005 [Byte1]: 62
3402 23:41:56.576062
3403 23:41:56.576116 Set Vref, RX VrefLevel [Byte0]: 63
3404 23:41:56.576171 [Byte1]: 63
3405 23:41:56.576224
3406 23:41:56.576277 Set Vref, RX VrefLevel [Byte0]: 64
3407 23:41:56.576329 [Byte1]: 64
3408 23:41:56.576381
3409 23:41:56.576432 Set Vref, RX VrefLevel [Byte0]: 65
3410 23:41:56.576507 [Byte1]: 65
3411 23:41:56.576561
3412 23:41:56.576615 Set Vref, RX VrefLevel [Byte0]: 66
3413 23:41:56.576668 [Byte1]: 66
3414 23:41:56.576721
3415 23:41:56.576774 Set Vref, RX VrefLevel [Byte0]: 67
3416 23:41:56.576827 [Byte1]: 67
3417 23:41:56.576879
3418 23:41:56.576932 Set Vref, RX VrefLevel [Byte0]: 68
3419 23:41:56.577182 [Byte1]: 68
3420 23:41:56.580540
3421 23:41:56.580628 Set Vref, RX VrefLevel [Byte0]: 69
3422 23:41:56.584112 [Byte1]: 69
3423 23:41:56.588329
3424 23:41:56.588411 Set Vref, RX VrefLevel [Byte0]: 70
3425 23:41:56.591982 [Byte1]: 70
3426 23:41:56.596472
3427 23:41:56.596550 Final RX Vref Byte 0 = 58 to rank0
3428 23:41:56.599947 Final RX Vref Byte 1 = 52 to rank0
3429 23:41:56.603120 Final RX Vref Byte 0 = 58 to rank1
3430 23:41:56.606677 Final RX Vref Byte 1 = 52 to rank1==
3431 23:41:56.609769 Dram Type= 6, Freq= 0, CH_1, rank 0
3432 23:41:56.613089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3433 23:41:56.616896 ==
3434 23:41:56.617046 DQS Delay:
3435 23:41:56.617145 DQS0 = 0, DQS1 = 0
3436 23:41:56.619747 DQM Delay:
3437 23:41:56.619844 DQM0 = 116, DQM1 = 109
3438 23:41:56.623733 DQ Delay:
3439 23:41:56.626532 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =114
3440 23:41:56.629969 DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =114
3441 23:41:56.633493 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =106
3442 23:41:56.636805 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3443 23:41:56.636909
3444 23:41:56.637043
3445 23:41:56.643299 [DQSOSCAuto] RK0, (LSB)MR18= 0xfde2, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3446 23:41:56.648604 CH1 RK0: MR19=303, MR18=FDE2
3447 23:41:56.653440 CH1_RK0: MR19=0x303, MR18=0xFDE2, DQSOSC=411, MR23=63, INC=38, DEC=25
3448 23:41:56.653580
3449 23:41:56.656548 ----->DramcWriteLeveling(PI) begin...
3450 23:41:56.656644 ==
3451 23:41:56.660051 Dram Type= 6, Freq= 0, CH_1, rank 1
3452 23:41:56.663715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3453 23:41:56.663809 ==
3454 23:41:56.666912 Write leveling (Byte 0): 26 => 26
3455 23:41:56.669930 Write leveling (Byte 1): 28 => 28
3456 23:41:56.673910 DramcWriteLeveling(PI) end<-----
3457 23:41:56.673990
3458 23:41:56.674052 ==
3459 23:41:56.677090 Dram Type= 6, Freq= 0, CH_1, rank 1
3460 23:41:56.680615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3461 23:41:56.680695 ==
3462 23:41:56.683783 [Gating] SW mode calibration
3463 23:41:56.690255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3464 23:41:56.697061 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3465 23:41:56.700747 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
3466 23:41:56.707190 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 23:41:56.710564 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3468 23:41:56.714039 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3469 23:41:56.720532 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3470 23:41:56.723962 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3471 23:41:56.726892 0 15 24 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
3472 23:41:56.730321 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3473 23:41:56.737152 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 23:41:56.740502 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 23:41:56.744050 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 23:41:56.750623 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3477 23:41:56.754030 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3478 23:41:56.756986 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3479 23:41:56.764128 1 0 24 | B1->B0 | 2626 4242 | 1 0 | (0 0) (1 1)
3480 23:41:56.767472 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3481 23:41:56.770346 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 23:41:56.777566 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 23:41:56.780360 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 23:41:56.784244 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3485 23:41:56.790693 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3486 23:41:56.793992 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3487 23:41:56.797466 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3488 23:41:56.803935 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3489 23:41:56.807025 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 23:41:56.810177 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 23:41:56.814140 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 23:41:56.820276 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 23:41:56.823765 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 23:41:56.827345 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 23:41:56.833398 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 23:41:56.837155 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 23:41:56.840482 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 23:41:56.846768 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 23:41:56.850105 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3500 23:41:56.853571 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3501 23:41:56.860255 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3502 23:41:56.863341 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3503 23:41:56.866721 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3504 23:41:56.873444 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3505 23:41:56.876564 Total UI for P1: 0, mck2ui 16
3506 23:41:56.879656 best dqsien dly found for B0: ( 1, 3, 24)
3507 23:41:56.883392 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 23:41:56.886671 Total UI for P1: 0, mck2ui 16
3509 23:41:56.889913 best dqsien dly found for B1: ( 1, 3, 28)
3510 23:41:56.893509 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3511 23:41:56.897020 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3512 23:41:56.897101
3513 23:41:56.900026 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3514 23:41:56.903278 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3515 23:41:56.906947 [Gating] SW calibration Done
3516 23:41:56.907029 ==
3517 23:41:56.910064 Dram Type= 6, Freq= 0, CH_1, rank 1
3518 23:41:56.913556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3519 23:41:56.917045 ==
3520 23:41:56.917149 RX Vref Scan: 0
3521 23:41:56.917239
3522 23:41:56.920098 RX Vref 0 -> 0, step: 1
3523 23:41:56.920201
3524 23:41:56.923491 RX Delay -40 -> 252, step: 8
3525 23:41:56.926750 iDelay=192, Bit 0, Center 115 (40 ~ 191) 152
3526 23:41:56.930070 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3527 23:41:56.933551 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3528 23:41:56.936920 iDelay=192, Bit 3, Center 111 (40 ~ 183) 144
3529 23:41:56.943155 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3530 23:41:56.946774 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3531 23:41:56.949720 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3532 23:41:56.953134 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3533 23:41:56.956815 iDelay=192, Bit 8, Center 99 (24 ~ 175) 152
3534 23:41:56.960106 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3535 23:41:56.966705 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3536 23:41:56.969924 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3537 23:41:56.973421 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3538 23:41:56.976610 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3539 23:41:56.979720 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3540 23:41:56.986610 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3541 23:41:56.986685 ==
3542 23:41:56.990423 Dram Type= 6, Freq= 0, CH_1, rank 1
3543 23:41:56.993455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3544 23:41:56.993526 ==
3545 23:41:56.993586 DQS Delay:
3546 23:41:56.996628 DQS0 = 0, DQS1 = 0
3547 23:41:56.996697 DQM Delay:
3548 23:41:56.999968 DQM0 = 112, DQM1 = 110
3549 23:41:57.000033 DQ Delay:
3550 23:41:57.003638 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3551 23:41:57.006970 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3552 23:41:57.010164 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3553 23:41:57.013699 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3554 23:41:57.013786
3555 23:41:57.013882
3556 23:41:57.016852 ==
3557 23:41:57.020062 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 23:41:57.023944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 23:41:57.024046 ==
3560 23:41:57.024142
3561 23:41:57.024210
3562 23:41:57.026735 TX Vref Scan disable
3563 23:41:57.026835 == TX Byte 0 ==
3564 23:41:57.030714 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3565 23:41:57.036631 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3566 23:41:57.036747 == TX Byte 1 ==
3567 23:41:57.040350 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3568 23:41:57.047165 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3569 23:41:57.047258 ==
3570 23:41:57.050015 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 23:41:57.053872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 23:41:57.053976 ==
3573 23:41:57.065339 TX Vref=22, minBit 0, minWin=25, winSum=415
3574 23:41:57.068885 TX Vref=24, minBit 1, minWin=25, winSum=420
3575 23:41:57.072409 TX Vref=26, minBit 0, minWin=26, winSum=431
3576 23:41:57.075273 TX Vref=28, minBit 1, minWin=25, winSum=431
3577 23:41:57.078988 TX Vref=30, minBit 3, minWin=26, winSum=432
3578 23:41:57.085412 TX Vref=32, minBit 1, minWin=26, winSum=434
3579 23:41:57.088423 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 32
3580 23:41:57.088527
3581 23:41:57.091898 Final TX Range 1 Vref 32
3582 23:41:57.092006
3583 23:41:57.092127 ==
3584 23:41:57.095442 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 23:41:57.098147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 23:41:57.098256 ==
3587 23:41:57.101501
3588 23:41:57.101604
3589 23:41:57.101684 TX Vref Scan disable
3590 23:41:57.105190 == TX Byte 0 ==
3591 23:41:57.108676 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3592 23:41:57.112102 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3593 23:41:57.115002 == TX Byte 1 ==
3594 23:41:57.118784 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3595 23:41:57.124855 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3596 23:41:57.124954
3597 23:41:57.125087 [DATLAT]
3598 23:41:57.125182 Freq=1200, CH1 RK1
3599 23:41:57.125273
3600 23:41:57.128371 DATLAT Default: 0xd
3601 23:41:57.128479 0, 0xFFFF, sum = 0
3602 23:41:57.131688 1, 0xFFFF, sum = 0
3603 23:41:57.131798 2, 0xFFFF, sum = 0
3604 23:41:57.135149 3, 0xFFFF, sum = 0
3605 23:41:57.138187 4, 0xFFFF, sum = 0
3606 23:41:57.138295 5, 0xFFFF, sum = 0
3607 23:41:57.141701 6, 0xFFFF, sum = 0
3608 23:41:57.141807 7, 0xFFFF, sum = 0
3609 23:41:57.144882 8, 0xFFFF, sum = 0
3610 23:41:57.144992 9, 0xFFFF, sum = 0
3611 23:41:57.148170 10, 0xFFFF, sum = 0
3612 23:41:57.148274 11, 0xFFFF, sum = 0
3613 23:41:57.151363 12, 0x0, sum = 1
3614 23:41:57.151473 13, 0x0, sum = 2
3615 23:41:57.154614 14, 0x0, sum = 3
3616 23:41:57.154721 15, 0x0, sum = 4
3617 23:41:57.159036 best_step = 13
3618 23:41:57.159142
3619 23:41:57.159240 ==
3620 23:41:57.161600 Dram Type= 6, Freq= 0, CH_1, rank 1
3621 23:41:57.164862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3622 23:41:57.164968 ==
3623 23:41:57.165082 RX Vref Scan: 0
3624 23:41:57.165145
3625 23:41:57.168260 RX Vref 0 -> 0, step: 1
3626 23:41:57.168340
3627 23:41:57.171619 RX Delay -21 -> 252, step: 4
3628 23:41:57.174852 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3629 23:41:57.181967 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3630 23:41:57.185198 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3631 23:41:57.187893 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3632 23:41:57.191841 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3633 23:41:57.194942 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3634 23:41:57.201565 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3635 23:41:57.204942 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3636 23:41:57.208230 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3637 23:41:57.211335 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3638 23:41:57.215146 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3639 23:41:57.218160 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3640 23:41:57.225194 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3641 23:41:57.228150 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3642 23:41:57.231458 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3643 23:41:57.235229 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3644 23:41:57.235309 ==
3645 23:41:57.238145 Dram Type= 6, Freq= 0, CH_1, rank 1
3646 23:41:57.244862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3647 23:41:57.244967 ==
3648 23:41:57.245082 DQS Delay:
3649 23:41:57.248146 DQS0 = 0, DQS1 = 0
3650 23:41:57.248244 DQM Delay:
3651 23:41:57.251473 DQM0 = 113, DQM1 = 110
3652 23:41:57.251569 DQ Delay:
3653 23:41:57.254725 DQ0 =114, DQ1 =110, DQ2 =104, DQ3 =112
3654 23:41:57.258092 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =110
3655 23:41:57.261368 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3656 23:41:57.264675 DQ12 =116, DQ13 =118, DQ14 =118, DQ15 =120
3657 23:41:57.264773
3658 23:41:57.264861
3659 23:41:57.274599 [DQSOSCAuto] RK1, (LSB)MR18= 0xfb02, (MSB)MR19= 0x304, tDQSOscB0 = 409 ps tDQSOscB1 = 412 ps
3660 23:41:57.274699 CH1 RK1: MR19=304, MR18=FB02
3661 23:41:57.281219 CH1_RK1: MR19=0x304, MR18=0xFB02, DQSOSC=409, MR23=63, INC=39, DEC=26
3662 23:41:57.284732 [RxdqsGatingPostProcess] freq 1200
3663 23:41:57.291384 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3664 23:41:57.295023 best DQS0 dly(2T, 0.5T) = (0, 11)
3665 23:41:57.298242 best DQS1 dly(2T, 0.5T) = (0, 12)
3666 23:41:57.301403 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3667 23:41:57.305018 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3668 23:41:57.305098 best DQS0 dly(2T, 0.5T) = (0, 11)
3669 23:41:57.308146 best DQS1 dly(2T, 0.5T) = (0, 11)
3670 23:41:57.311580 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3671 23:41:57.314970 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3672 23:41:57.318300 Pre-setting of DQS Precalculation
3673 23:41:57.324692 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3674 23:41:57.331557 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3675 23:41:57.338089 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3676 23:41:57.338190
3677 23:41:57.338285
3678 23:41:57.341989 [Calibration Summary] 2400 Mbps
3679 23:41:57.342069 CH 0, Rank 0
3680 23:41:57.345321 SW Impedance : PASS
3681 23:41:57.348260 DUTY Scan : NO K
3682 23:41:57.348329 ZQ Calibration : PASS
3683 23:41:57.352002 Jitter Meter : NO K
3684 23:41:57.355254 CBT Training : PASS
3685 23:41:57.355355 Write leveling : PASS
3686 23:41:57.358314 RX DQS gating : PASS
3687 23:41:57.361422 RX DQ/DQS(RDDQC) : PASS
3688 23:41:57.361517 TX DQ/DQS : PASS
3689 23:41:57.365003 RX DATLAT : PASS
3690 23:41:57.365118 RX DQ/DQS(Engine): PASS
3691 23:41:57.368850 TX OE : NO K
3692 23:41:57.368920 All Pass.
3693 23:41:57.369002
3694 23:41:57.371676 CH 0, Rank 1
3695 23:41:57.371756 SW Impedance : PASS
3696 23:41:57.375232 DUTY Scan : NO K
3697 23:41:57.378383 ZQ Calibration : PASS
3698 23:41:57.378463 Jitter Meter : NO K
3699 23:41:57.381809 CBT Training : PASS
3700 23:41:57.384971 Write leveling : PASS
3701 23:41:57.385076 RX DQS gating : PASS
3702 23:41:57.388190 RX DQ/DQS(RDDQC) : PASS
3703 23:41:57.391512 TX DQ/DQS : PASS
3704 23:41:57.391591 RX DATLAT : PASS
3705 23:41:57.395748 RX DQ/DQS(Engine): PASS
3706 23:41:57.398304 TX OE : NO K
3707 23:41:57.398399 All Pass.
3708 23:41:57.398493
3709 23:41:57.398566 CH 1, Rank 0
3710 23:41:57.401985 SW Impedance : PASS
3711 23:41:57.404953 DUTY Scan : NO K
3712 23:41:57.405055 ZQ Calibration : PASS
3713 23:41:57.408628 Jitter Meter : NO K
3714 23:41:57.408708 CBT Training : PASS
3715 23:41:57.411952 Write leveling : PASS
3716 23:41:57.415096 RX DQS gating : PASS
3717 23:41:57.415175 RX DQ/DQS(RDDQC) : PASS
3718 23:41:57.418679 TX DQ/DQS : PASS
3719 23:41:57.421947 RX DATLAT : PASS
3720 23:41:57.422026 RX DQ/DQS(Engine): PASS
3721 23:41:57.425131 TX OE : NO K
3722 23:41:57.425212 All Pass.
3723 23:41:57.425275
3724 23:41:57.428529 CH 1, Rank 1
3725 23:41:57.428608 SW Impedance : PASS
3726 23:41:57.431760 DUTY Scan : NO K
3727 23:41:57.434909 ZQ Calibration : PASS
3728 23:41:57.434988 Jitter Meter : NO K
3729 23:41:57.438452 CBT Training : PASS
3730 23:41:57.441829 Write leveling : PASS
3731 23:41:57.441909 RX DQS gating : PASS
3732 23:41:57.445244 RX DQ/DQS(RDDQC) : PASS
3733 23:41:57.445324 TX DQ/DQS : PASS
3734 23:41:57.448597 RX DATLAT : PASS
3735 23:41:57.451695 RX DQ/DQS(Engine): PASS
3736 23:41:57.451774 TX OE : NO K
3737 23:41:57.455000 All Pass.
3738 23:41:57.455079
3739 23:41:57.455141 DramC Write-DBI off
3740 23:41:57.458563 PER_BANK_REFRESH: Hybrid Mode
3741 23:41:57.461775 TX_TRACKING: ON
3742 23:41:57.468265 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3743 23:41:57.472424 [FAST_K] Save calibration result to emmc
3744 23:41:57.475165 dramc_set_vcore_voltage set vcore to 650000
3745 23:41:57.478740 Read voltage for 600, 5
3746 23:41:57.478820 Vio18 = 0
3747 23:41:57.481877 Vcore = 650000
3748 23:41:57.481956 Vdram = 0
3749 23:41:57.482019 Vddq = 0
3750 23:41:57.485396 Vmddr = 0
3751 23:41:57.488480 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3752 23:41:57.494906 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3753 23:41:57.494987 MEM_TYPE=3, freq_sel=19
3754 23:41:57.498592 sv_algorithm_assistance_LP4_1600
3755 23:41:57.505314 ============ PULL DRAM RESETB DOWN ============
3756 23:41:57.508300 ========== PULL DRAM RESETB DOWN end =========
3757 23:41:57.511725 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3758 23:41:57.515041 ===================================
3759 23:41:57.518662 LPDDR4 DRAM CONFIGURATION
3760 23:41:57.522109 ===================================
3761 23:41:57.522189 EX_ROW_EN[0] = 0x0
3762 23:41:57.525207 EX_ROW_EN[1] = 0x0
3763 23:41:57.528897 LP4Y_EN = 0x0
3764 23:41:57.528988 WORK_FSP = 0x0
3765 23:41:57.531849 WL = 0x2
3766 23:41:57.531944 RL = 0x2
3767 23:41:57.535173 BL = 0x2
3768 23:41:57.535253 RPST = 0x0
3769 23:41:57.538812 RD_PRE = 0x0
3770 23:41:57.538891 WR_PRE = 0x1
3771 23:41:57.541971 WR_PST = 0x0
3772 23:41:57.542050 DBI_WR = 0x0
3773 23:41:57.545155 DBI_RD = 0x0
3774 23:41:57.545234 OTF = 0x1
3775 23:41:57.548884 ===================================
3776 23:41:57.551845 ===================================
3777 23:41:57.555349 ANA top config
3778 23:41:57.558661 ===================================
3779 23:41:57.558748 DLL_ASYNC_EN = 0
3780 23:41:57.562298 ALL_SLAVE_EN = 1
3781 23:41:57.565528 NEW_RANK_MODE = 1
3782 23:41:57.568892 DLL_IDLE_MODE = 1
3783 23:41:57.569014 LP45_APHY_COMB_EN = 1
3784 23:41:57.572102 TX_ODT_DIS = 1
3785 23:41:57.575650 NEW_8X_MODE = 1
3786 23:41:57.578468 ===================================
3787 23:41:57.582047 ===================================
3788 23:41:57.584992 data_rate = 1200
3789 23:41:57.589270 CKR = 1
3790 23:41:57.592034 DQ_P2S_RATIO = 8
3791 23:41:57.595412 ===================================
3792 23:41:57.595509 CA_P2S_RATIO = 8
3793 23:41:57.598777 DQ_CA_OPEN = 0
3794 23:41:57.601822 DQ_SEMI_OPEN = 0
3795 23:41:57.605302 CA_SEMI_OPEN = 0
3796 23:41:57.608683 CA_FULL_RATE = 0
3797 23:41:57.608794 DQ_CKDIV4_EN = 1
3798 23:41:57.612030 CA_CKDIV4_EN = 1
3799 23:41:57.615577 CA_PREDIV_EN = 0
3800 23:41:57.618205 PH8_DLY = 0
3801 23:41:57.621409 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3802 23:41:57.624716 DQ_AAMCK_DIV = 4
3803 23:41:57.624822 CA_AAMCK_DIV = 4
3804 23:41:57.628113 CA_ADMCK_DIV = 4
3805 23:41:57.632206 DQ_TRACK_CA_EN = 0
3806 23:41:57.634763 CA_PICK = 600
3807 23:41:57.638265 CA_MCKIO = 600
3808 23:41:57.641690 MCKIO_SEMI = 0
3809 23:41:57.644929 PLL_FREQ = 2288
3810 23:41:57.645064 DQ_UI_PI_RATIO = 32
3811 23:41:57.648201 CA_UI_PI_RATIO = 0
3812 23:41:57.651618 ===================================
3813 23:41:57.654566 ===================================
3814 23:41:57.658214 memory_type:LPDDR4
3815 23:41:57.661559 GP_NUM : 10
3816 23:41:57.661658 SRAM_EN : 1
3817 23:41:57.664530 MD32_EN : 0
3818 23:41:57.667905 ===================================
3819 23:41:57.671372 [ANA_INIT] >>>>>>>>>>>>>>
3820 23:41:57.671457 <<<<<< [CONFIGURE PHASE]: ANA_TX
3821 23:41:57.678178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3822 23:41:57.678273 ===================================
3823 23:41:57.681506 data_rate = 1200,PCW = 0X5800
3824 23:41:57.684988 ===================================
3825 23:41:57.688424 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3826 23:41:57.695295 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3827 23:41:57.701626 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3828 23:41:57.704763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3829 23:41:57.708183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3830 23:41:57.711453 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3831 23:41:57.714825 [ANA_INIT] flow start
3832 23:41:57.714901 [ANA_INIT] PLL >>>>>>>>
3833 23:41:57.718543 [ANA_INIT] PLL <<<<<<<<
3834 23:41:57.721533 [ANA_INIT] MIDPI >>>>>>>>
3835 23:41:57.721615 [ANA_INIT] MIDPI <<<<<<<<
3836 23:41:57.725261 [ANA_INIT] DLL >>>>>>>>
3837 23:41:57.728454 [ANA_INIT] flow end
3838 23:41:57.731634 ============ LP4 DIFF to SE enter ============
3839 23:41:57.734741 ============ LP4 DIFF to SE exit ============
3840 23:41:57.738462 [ANA_INIT] <<<<<<<<<<<<<
3841 23:41:57.742025 [Flow] Enable top DCM control >>>>>
3842 23:41:57.744882 [Flow] Enable top DCM control <<<<<
3843 23:41:57.748420 Enable DLL master slave shuffle
3844 23:41:57.751649 ==============================================================
3845 23:41:57.754897 Gating Mode config
3846 23:41:57.761652 ==============================================================
3847 23:41:57.761766 Config description:
3848 23:41:57.771609 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3849 23:41:57.778342 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3850 23:41:57.781804 SELPH_MODE 0: By rank 1: By Phase
3851 23:41:57.788846 ==============================================================
3852 23:41:57.792076 GAT_TRACK_EN = 1
3853 23:41:57.795346 RX_GATING_MODE = 2
3854 23:41:57.798535 RX_GATING_TRACK_MODE = 2
3855 23:41:57.801690 SELPH_MODE = 1
3856 23:41:57.804898 PICG_EARLY_EN = 1
3857 23:41:57.805020 VALID_LAT_VALUE = 1
3858 23:41:57.812277 ==============================================================
3859 23:41:57.815125 Enter into Gating configuration >>>>
3860 23:41:57.818749 Exit from Gating configuration <<<<
3861 23:41:57.821701 Enter into DVFS_PRE_config >>>>>
3862 23:41:57.832168 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3863 23:41:57.835014 Exit from DVFS_PRE_config <<<<<
3864 23:41:57.838368 Enter into PICG configuration >>>>
3865 23:41:57.841934 Exit from PICG configuration <<<<
3866 23:41:57.845367 [RX_INPUT] configuration >>>>>
3867 23:41:57.848162 [RX_INPUT] configuration <<<<<
3868 23:41:57.851769 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3869 23:41:57.858331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3870 23:41:57.864740 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3871 23:41:57.871606 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3872 23:41:57.878244 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3873 23:41:57.884914 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3874 23:41:57.888540 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3875 23:41:57.892039 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3876 23:41:57.895038 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3877 23:41:57.898486 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3878 23:41:57.905246 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3879 23:41:57.908708 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3880 23:41:57.911631 ===================================
3881 23:41:57.915092 LPDDR4 DRAM CONFIGURATION
3882 23:41:57.918380 ===================================
3883 23:41:57.918461 EX_ROW_EN[0] = 0x0
3884 23:41:57.921723 EX_ROW_EN[1] = 0x0
3885 23:41:57.921802 LP4Y_EN = 0x0
3886 23:41:57.924649 WORK_FSP = 0x0
3887 23:41:57.924728 WL = 0x2
3888 23:41:57.928145 RL = 0x2
3889 23:41:57.928224 BL = 0x2
3890 23:41:57.931586 RPST = 0x0
3891 23:41:57.931666 RD_PRE = 0x0
3892 23:41:57.935470 WR_PRE = 0x1
3893 23:41:57.938362 WR_PST = 0x0
3894 23:41:57.938441 DBI_WR = 0x0
3895 23:41:57.941429 DBI_RD = 0x0
3896 23:41:57.941519 OTF = 0x1
3897 23:41:57.944594 ===================================
3898 23:41:57.948005 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3899 23:41:57.951273 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3900 23:41:57.958450 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3901 23:41:57.961847 ===================================
3902 23:41:57.965089 LPDDR4 DRAM CONFIGURATION
3903 23:41:57.968140 ===================================
3904 23:41:57.968220 EX_ROW_EN[0] = 0x10
3905 23:41:57.971536 EX_ROW_EN[1] = 0x0
3906 23:41:57.971616 LP4Y_EN = 0x0
3907 23:41:57.974958 WORK_FSP = 0x0
3908 23:41:57.975037 WL = 0x2
3909 23:41:57.978336 RL = 0x2
3910 23:41:57.978416 BL = 0x2
3911 23:41:57.981504 RPST = 0x0
3912 23:41:57.981583 RD_PRE = 0x0
3913 23:41:57.985149 WR_PRE = 0x1
3914 23:41:57.985229 WR_PST = 0x0
3915 23:41:57.988441 DBI_WR = 0x0
3916 23:41:57.988546 DBI_RD = 0x0
3917 23:41:57.991888 OTF = 0x1
3918 23:41:57.994685 ===================================
3919 23:41:58.001633 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3920 23:41:58.005178 nWR fixed to 30
3921 23:41:58.008070 [ModeRegInit_LP4] CH0 RK0
3922 23:41:58.008169 [ModeRegInit_LP4] CH0 RK1
3923 23:41:58.011442 [ModeRegInit_LP4] CH1 RK0
3924 23:41:58.014842 [ModeRegInit_LP4] CH1 RK1
3925 23:41:58.014912 match AC timing 17
3926 23:41:58.021323 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3927 23:41:58.024799 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3928 23:41:58.028649 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3929 23:41:58.035054 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3930 23:41:58.038471 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3931 23:41:58.038576 ==
3932 23:41:58.042120 Dram Type= 6, Freq= 0, CH_0, rank 0
3933 23:41:58.045378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3934 23:41:58.045457 ==
3935 23:41:58.051953 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3936 23:41:58.058531 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3937 23:41:58.061459 [CA 0] Center 36 (6~66) winsize 61
3938 23:41:58.065117 [CA 1] Center 36 (6~66) winsize 61
3939 23:41:58.067994 [CA 2] Center 34 (4~65) winsize 62
3940 23:41:58.071578 [CA 3] Center 34 (4~65) winsize 62
3941 23:41:58.075037 [CA 4] Center 33 (3~64) winsize 62
3942 23:41:58.078433 [CA 5] Center 33 (3~64) winsize 62
3943 23:41:58.078540
3944 23:41:58.081270 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3945 23:41:58.081373
3946 23:41:58.084997 [CATrainingPosCal] consider 1 rank data
3947 23:41:58.088377 u2DelayCellTimex100 = 270/100 ps
3948 23:41:58.091223 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3949 23:41:58.094893 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3950 23:41:58.098551 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 23:41:58.101511 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3952 23:41:58.104877 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 23:41:58.108351 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3954 23:41:58.108456
3955 23:41:58.114699 CA PerBit enable=1, Macro0, CA PI delay=33
3956 23:41:58.114810
3957 23:41:58.114891 [CBTSetCACLKResult] CA Dly = 33
3958 23:41:58.118142 CS Dly: 4 (0~35)
3959 23:41:58.118226 ==
3960 23:41:58.121355 Dram Type= 6, Freq= 0, CH_0, rank 1
3961 23:41:58.125141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 23:41:58.125246 ==
3963 23:41:58.131460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3964 23:41:58.138086 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3965 23:41:58.141480 [CA 0] Center 36 (6~66) winsize 61
3966 23:41:58.144623 [CA 1] Center 36 (6~66) winsize 61
3967 23:41:58.147902 [CA 2] Center 34 (4~65) winsize 62
3968 23:41:58.151564 [CA 3] Center 34 (4~64) winsize 61
3969 23:41:58.154601 [CA 4] Center 33 (3~64) winsize 62
3970 23:41:58.158195 [CA 5] Center 33 (3~64) winsize 62
3971 23:41:58.158267
3972 23:41:58.161040 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3973 23:41:58.161144
3974 23:41:58.164522 [CATrainingPosCal] consider 2 rank data
3975 23:41:58.167622 u2DelayCellTimex100 = 270/100 ps
3976 23:41:58.171029 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3977 23:41:58.174827 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3978 23:41:58.177766 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3979 23:41:58.181254 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3980 23:41:58.185049 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3981 23:41:58.187701 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3982 23:41:58.191172
3983 23:41:58.194487 CA PerBit enable=1, Macro0, CA PI delay=33
3984 23:41:58.194605
3985 23:41:58.197602 [CBTSetCACLKResult] CA Dly = 33
3986 23:41:58.197675 CS Dly: 4 (0~36)
3987 23:41:58.197736
3988 23:41:58.201245 ----->DramcWriteLeveling(PI) begin...
3989 23:41:58.201367 ==
3990 23:41:58.204575 Dram Type= 6, Freq= 0, CH_0, rank 0
3991 23:41:58.207541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3992 23:41:58.207687 ==
3993 23:41:58.211438 Write leveling (Byte 0): 32 => 32
3994 23:41:58.214377 Write leveling (Byte 1): 30 => 30
3995 23:41:58.217613 DramcWriteLeveling(PI) end<-----
3996 23:41:58.217714
3997 23:41:58.217836 ==
3998 23:41:58.221260 Dram Type= 6, Freq= 0, CH_0, rank 0
3999 23:41:58.227784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4000 23:41:58.227876 ==
4001 23:41:58.227939 [Gating] SW mode calibration
4002 23:41:58.237737 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4003 23:41:58.241155 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4004 23:41:58.244618 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4005 23:41:58.251257 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4006 23:41:58.254445 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4007 23:41:58.257337 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4008 23:41:58.264503 0 9 16 | B1->B0 | 3333 2b2b | 0 0 | (0 1) (1 0)
4009 23:41:58.267289 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 23:41:58.270674 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 23:41:58.277609 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 23:41:58.281131 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4013 23:41:58.284138 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4014 23:41:58.290920 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4015 23:41:58.294218 0 10 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4016 23:41:58.297501 0 10 16 | B1->B0 | 3030 3a3a | 0 0 | (1 1) (0 0)
4017 23:41:58.304106 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 23:41:58.307489 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 23:41:58.310816 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 23:41:58.317538 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 23:41:58.320848 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4022 23:41:58.324346 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4023 23:41:58.331249 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4024 23:41:58.334193 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4025 23:41:58.337659 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 23:41:58.340804 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 23:41:58.347808 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 23:41:58.350801 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 23:41:58.354006 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 23:41:58.360784 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 23:41:58.363981 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 23:41:58.367520 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 23:41:58.374125 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 23:41:58.377585 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 23:41:58.380919 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 23:41:58.387467 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 23:41:58.390664 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4038 23:41:58.394397 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4039 23:41:58.400669 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4040 23:41:58.404185 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4041 23:41:58.407557 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 23:41:58.410611 Total UI for P1: 0, mck2ui 16
4043 23:41:58.414128 best dqsien dly found for B0: ( 0, 13, 16)
4044 23:41:58.417664 Total UI for P1: 0, mck2ui 16
4045 23:41:58.420876 best dqsien dly found for B1: ( 0, 13, 16)
4046 23:41:58.424281 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4047 23:41:58.427792 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4048 23:41:58.427871
4049 23:41:58.430839 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4050 23:41:58.437721 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4051 23:41:58.437800 [Gating] SW calibration Done
4052 23:41:58.437865 ==
4053 23:41:58.440671 Dram Type= 6, Freq= 0, CH_0, rank 0
4054 23:41:58.447751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4055 23:41:58.447833 ==
4056 23:41:58.447897 RX Vref Scan: 0
4057 23:41:58.447972
4058 23:41:58.450701 RX Vref 0 -> 0, step: 1
4059 23:41:58.450801
4060 23:41:58.454576 RX Delay -230 -> 252, step: 16
4061 23:41:58.457717 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4062 23:41:58.460811 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4063 23:41:58.464376 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4064 23:41:58.471362 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4065 23:41:58.474673 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4066 23:41:58.477343 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4067 23:41:58.480741 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4068 23:41:58.487699 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4069 23:41:58.490990 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4070 23:41:58.494009 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4071 23:41:58.497539 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4072 23:41:58.500759 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4073 23:41:58.507586 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4074 23:41:58.510889 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4075 23:41:58.514070 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4076 23:41:58.517500 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4077 23:41:58.520930 ==
4078 23:41:58.523833 Dram Type= 6, Freq= 0, CH_0, rank 0
4079 23:41:58.527347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4080 23:41:58.527461 ==
4081 23:41:58.527556 DQS Delay:
4082 23:41:58.530815 DQS0 = 0, DQS1 = 0
4083 23:41:58.530919 DQM Delay:
4084 23:41:58.534361 DQM0 = 40, DQM1 = 31
4085 23:41:58.534465 DQ Delay:
4086 23:41:58.537385 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4087 23:41:58.540884 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4088 23:41:58.544293 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4089 23:41:58.547563 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4090 23:41:58.547669
4091 23:41:58.547761
4092 23:41:58.547860 ==
4093 23:41:58.550665 Dram Type= 6, Freq= 0, CH_0, rank 0
4094 23:41:58.554122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4095 23:41:58.554204 ==
4096 23:41:58.554268
4097 23:41:58.554327
4098 23:41:58.557555 TX Vref Scan disable
4099 23:41:58.560963 == TX Byte 0 ==
4100 23:41:58.564258 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4101 23:41:58.567681 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4102 23:41:58.571105 == TX Byte 1 ==
4103 23:41:58.574017 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4104 23:41:58.577498 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4105 23:41:58.577579 ==
4106 23:41:58.581009 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 23:41:58.584285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 23:41:58.584388 ==
4109 23:41:58.587635
4110 23:41:58.587732
4111 23:41:58.587824 TX Vref Scan disable
4112 23:41:58.591164 == TX Byte 0 ==
4113 23:41:58.594406 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4114 23:41:58.597771 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4115 23:41:58.601508 == TX Byte 1 ==
4116 23:41:58.604657 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4117 23:41:58.611834 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4118 23:41:58.611916
4119 23:41:58.611980 [DATLAT]
4120 23:41:58.612039 Freq=600, CH0 RK0
4121 23:41:58.612096
4122 23:41:58.614241 DATLAT Default: 0x9
4123 23:41:58.614322 0, 0xFFFF, sum = 0
4124 23:41:58.617910 1, 0xFFFF, sum = 0
4125 23:41:58.617992 2, 0xFFFF, sum = 0
4126 23:41:58.621113 3, 0xFFFF, sum = 0
4127 23:41:58.624767 4, 0xFFFF, sum = 0
4128 23:41:58.624849 5, 0xFFFF, sum = 0
4129 23:41:58.628176 6, 0xFFFF, sum = 0
4130 23:41:58.628258 7, 0xFFFF, sum = 0
4131 23:41:58.628323 8, 0x0, sum = 1
4132 23:41:58.631611 9, 0x0, sum = 2
4133 23:41:58.631719 10, 0x0, sum = 3
4134 23:41:58.634572 11, 0x0, sum = 4
4135 23:41:58.634672 best_step = 9
4136 23:41:58.634769
4137 23:41:58.634856 ==
4138 23:41:58.638274 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 23:41:58.644447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 23:41:58.644522 ==
4141 23:41:58.644601 RX Vref Scan: 1
4142 23:41:58.644662
4143 23:41:58.648697 RX Vref 0 -> 0, step: 1
4144 23:41:58.648778
4145 23:41:58.651225 RX Delay -195 -> 252, step: 8
4146 23:41:58.651306
4147 23:41:58.654959 Set Vref, RX VrefLevel [Byte0]: 51
4148 23:41:58.657751 [Byte1]: 52
4149 23:41:58.657830
4150 23:41:58.661192 Final RX Vref Byte 0 = 51 to rank0
4151 23:41:58.664462 Final RX Vref Byte 1 = 52 to rank0
4152 23:41:58.668420 Final RX Vref Byte 0 = 51 to rank1
4153 23:41:58.671248 Final RX Vref Byte 1 = 52 to rank1==
4154 23:41:58.674708 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 23:41:58.677823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 23:41:58.677929 ==
4157 23:41:58.681056 DQS Delay:
4158 23:41:58.681131 DQS0 = 0, DQS1 = 0
4159 23:41:58.681206 DQM Delay:
4160 23:41:58.684570 DQM0 = 42, DQM1 = 34
4161 23:41:58.684700 DQ Delay:
4162 23:41:58.687546 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4163 23:41:58.691072 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4164 23:41:58.694693 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4165 23:41:58.698298 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4166 23:41:58.698403
4167 23:41:58.698493
4168 23:41:58.707866 [DQSOSCAuto] RK0, (LSB)MR18= 0x4524, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 396 ps
4169 23:41:58.710763 CH0 RK0: MR19=808, MR18=4524
4170 23:41:58.714167 CH0_RK0: MR19=0x808, MR18=0x4524, DQSOSC=396, MR23=63, INC=167, DEC=111
4171 23:41:58.714274
4172 23:41:58.717949 ----->DramcWriteLeveling(PI) begin...
4173 23:41:58.720781 ==
4174 23:41:58.724431 Dram Type= 6, Freq= 0, CH_0, rank 1
4175 23:41:58.727825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4176 23:41:58.727927 ==
4177 23:41:58.731279 Write leveling (Byte 0): 31 => 31
4178 23:41:58.734553 Write leveling (Byte 1): 31 => 31
4179 23:41:58.737638 DramcWriteLeveling(PI) end<-----
4180 23:41:58.737742
4181 23:41:58.737832 ==
4182 23:41:58.741526 Dram Type= 6, Freq= 0, CH_0, rank 1
4183 23:41:58.744426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4184 23:41:58.744552 ==
4185 23:41:58.747873 [Gating] SW mode calibration
4186 23:41:58.754432 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4187 23:41:58.758031 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4188 23:41:58.764544 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4189 23:41:58.767949 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4190 23:41:58.770974 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4191 23:41:58.777843 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4192 23:41:58.781217 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
4193 23:41:58.784284 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4194 23:41:58.791050 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 23:41:58.794373 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 23:41:58.797752 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4197 23:41:58.804243 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4198 23:41:58.807813 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4199 23:41:58.810800 0 10 12 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (1 1)
4200 23:41:58.818055 0 10 16 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
4201 23:41:58.821096 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 23:41:58.824391 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 23:41:58.831259 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 23:41:58.834234 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4205 23:41:58.837527 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4206 23:41:58.844119 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 23:41:58.849663 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4208 23:41:58.851074 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 23:41:58.854487 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 23:41:58.861716 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 23:41:58.864854 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 23:41:58.868045 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 23:41:58.874889 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 23:41:58.877622 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 23:41:58.880853 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 23:41:58.887806 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 23:41:58.891312 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 23:41:58.894206 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 23:41:58.900900 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 23:41:58.904262 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4221 23:41:58.908553 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4222 23:41:58.914845 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4223 23:41:58.917927 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4224 23:41:58.921063 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 23:41:58.924404 Total UI for P1: 0, mck2ui 16
4226 23:41:58.927796 best dqsien dly found for B0: ( 0, 13, 12)
4227 23:41:58.931350 Total UI for P1: 0, mck2ui 16
4228 23:41:58.934518 best dqsien dly found for B1: ( 0, 13, 14)
4229 23:41:58.937920 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4230 23:41:58.941214 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4231 23:41:58.941318
4232 23:41:58.944505 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4233 23:41:58.950888 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4234 23:41:58.951008 [Gating] SW calibration Done
4235 23:41:58.954570 ==
4236 23:41:58.954671 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 23:41:58.961282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 23:41:58.961397 ==
4239 23:41:58.961492 RX Vref Scan: 0
4240 23:41:58.961587
4241 23:41:58.964523 RX Vref 0 -> 0, step: 1
4242 23:41:58.964629
4243 23:41:58.967931 RX Delay -230 -> 252, step: 16
4244 23:41:58.971216 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4245 23:41:58.974344 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4246 23:41:58.977621 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4247 23:41:58.984272 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4248 23:41:58.987774 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4249 23:41:58.991382 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4250 23:41:58.994382 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4251 23:41:59.001177 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4252 23:41:59.004349 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4253 23:41:59.007579 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4254 23:41:59.011404 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4255 23:41:59.014867 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4256 23:41:59.021311 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4257 23:41:59.024409 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4258 23:41:59.028479 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4259 23:41:59.031831 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4260 23:41:59.031947 ==
4261 23:41:59.034513 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 23:41:59.040868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 23:41:59.040992 ==
4264 23:41:59.041093 DQS Delay:
4265 23:41:59.044617 DQS0 = 0, DQS1 = 0
4266 23:41:59.044724 DQM Delay:
4267 23:41:59.047701 DQM0 = 40, DQM1 = 32
4268 23:41:59.047807 DQ Delay:
4269 23:41:59.051147 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =33
4270 23:41:59.054587 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4271 23:41:59.057987 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4272 23:41:59.061214 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =41
4273 23:41:59.061320
4274 23:41:59.061423
4275 23:41:59.061529 ==
4276 23:41:59.064675 Dram Type= 6, Freq= 0, CH_0, rank 1
4277 23:41:59.067542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4278 23:41:59.067649 ==
4279 23:41:59.067755
4280 23:41:59.067854
4281 23:41:59.070830 TX Vref Scan disable
4282 23:41:59.074361 == TX Byte 0 ==
4283 23:41:59.077406 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4284 23:41:59.080696 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4285 23:41:59.084788 == TX Byte 1 ==
4286 23:41:59.087908 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4287 23:41:59.090600 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4288 23:41:59.090686 ==
4289 23:41:59.094566 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 23:41:59.097950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 23:41:59.100942 ==
4292 23:41:59.101045
4293 23:41:59.101154
4294 23:41:59.101245 TX Vref Scan disable
4295 23:41:59.105062 == TX Byte 0 ==
4296 23:41:59.108448 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4297 23:41:59.111449 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4298 23:41:59.115031 == TX Byte 1 ==
4299 23:41:59.117963 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4300 23:41:59.121735 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4301 23:41:59.124656
4302 23:41:59.124760 [DATLAT]
4303 23:41:59.124860 Freq=600, CH0 RK1
4304 23:41:59.124951
4305 23:41:59.128317 DATLAT Default: 0x9
4306 23:41:59.128422 0, 0xFFFF, sum = 0
4307 23:41:59.131219 1, 0xFFFF, sum = 0
4308 23:41:59.131328 2, 0xFFFF, sum = 0
4309 23:41:59.134887 3, 0xFFFF, sum = 0
4310 23:41:59.134995 4, 0xFFFF, sum = 0
4311 23:41:59.138817 5, 0xFFFF, sum = 0
4312 23:41:59.138923 6, 0xFFFF, sum = 0
4313 23:41:59.141578 7, 0xFFFF, sum = 0
4314 23:41:59.141684 8, 0x0, sum = 1
4315 23:41:59.144787 9, 0x0, sum = 2
4316 23:41:59.144893 10, 0x0, sum = 3
4317 23:41:59.148216 11, 0x0, sum = 4
4318 23:41:59.148324 best_step = 9
4319 23:41:59.148419
4320 23:41:59.148517 ==
4321 23:41:59.151753 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 23:41:59.158065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 23:41:59.158196 ==
4324 23:41:59.158299 RX Vref Scan: 0
4325 23:41:59.158393
4326 23:41:59.161252 RX Vref 0 -> 0, step: 1
4327 23:41:59.161353
4328 23:41:59.164765 RX Delay -195 -> 252, step: 8
4329 23:41:59.168772 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4330 23:41:59.174598 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4331 23:41:59.178377 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4332 23:41:59.181348 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4333 23:41:59.185606 iDelay=205, Bit 4, Center 40 (-107 ~ 188) 296
4334 23:41:59.188210 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4335 23:41:59.194765 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4336 23:41:59.198236 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4337 23:41:59.201532 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4338 23:41:59.204984 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4339 23:41:59.208300 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4340 23:41:59.215093 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4341 23:41:59.218261 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4342 23:41:59.221365 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4343 23:41:59.224701 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4344 23:41:59.231485 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4345 23:41:59.231594 ==
4346 23:41:59.235031 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 23:41:59.237891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 23:41:59.237990 ==
4349 23:41:59.238079 DQS Delay:
4350 23:41:59.241712 DQS0 = 0, DQS1 = 0
4351 23:41:59.241824 DQM Delay:
4352 23:41:59.244874 DQM0 = 40, DQM1 = 32
4353 23:41:59.244981 DQ Delay:
4354 23:41:59.247976 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4355 23:41:59.251801 DQ4 =40, DQ5 =28, DQ6 =48, DQ7 =44
4356 23:41:59.254633 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =20
4357 23:41:59.258022 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4358 23:41:59.258098
4359 23:41:59.258161
4360 23:41:59.268391 [DQSOSCAuto] RK1, (LSB)MR18= 0x4d2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4361 23:41:59.268519 CH0 RK1: MR19=808, MR18=4D2F
4362 23:41:59.274952 CH0_RK1: MR19=0x808, MR18=0x4D2F, DQSOSC=395, MR23=63, INC=168, DEC=112
4363 23:41:59.278086 [RxdqsGatingPostProcess] freq 600
4364 23:41:59.284784 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4365 23:41:59.288223 Pre-setting of DQS Precalculation
4366 23:41:59.291685 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4367 23:41:59.291783 ==
4368 23:41:59.295697 Dram Type= 6, Freq= 0, CH_1, rank 0
4369 23:41:59.297943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 23:41:59.298045 ==
4371 23:41:59.305047 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 23:41:59.311458 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4373 23:41:59.314727 [CA 0] Center 35 (5~65) winsize 61
4374 23:41:59.318111 [CA 1] Center 35 (5~66) winsize 62
4375 23:41:59.321484 [CA 2] Center 34 (4~64) winsize 61
4376 23:41:59.324819 [CA 3] Center 33 (3~64) winsize 62
4377 23:41:59.328331 [CA 4] Center 34 (3~65) winsize 63
4378 23:41:59.331702 [CA 5] Center 33 (3~64) winsize 62
4379 23:41:59.331802
4380 23:41:59.334709 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4381 23:41:59.334808
4382 23:41:59.337991 [CATrainingPosCal] consider 1 rank data
4383 23:41:59.341239 u2DelayCellTimex100 = 270/100 ps
4384 23:41:59.344623 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4385 23:41:59.348035 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4386 23:41:59.351951 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4387 23:41:59.355031 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4388 23:41:59.358430 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4389 23:41:59.361693 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4390 23:41:59.364999
4391 23:41:59.368239 CA PerBit enable=1, Macro0, CA PI delay=33
4392 23:41:59.368366
4393 23:41:59.371660 [CBTSetCACLKResult] CA Dly = 33
4394 23:41:59.371780 CS Dly: 5 (0~36)
4395 23:41:59.371873 ==
4396 23:41:59.375299 Dram Type= 6, Freq= 0, CH_1, rank 1
4397 23:41:59.378299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 23:41:59.378416 ==
4399 23:41:59.385347 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4400 23:41:59.391739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4401 23:41:59.395136 [CA 0] Center 35 (5~66) winsize 62
4402 23:41:59.398399 [CA 1] Center 36 (6~66) winsize 61
4403 23:41:59.402159 [CA 2] Center 34 (3~65) winsize 63
4404 23:41:59.405145 [CA 3] Center 34 (3~65) winsize 63
4405 23:41:59.408317 [CA 4] Center 34 (3~65) winsize 63
4406 23:41:59.411521 [CA 5] Center 33 (3~64) winsize 62
4407 23:41:59.411655
4408 23:41:59.414650 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4409 23:41:59.414753
4410 23:41:59.418048 [CATrainingPosCal] consider 2 rank data
4411 23:41:59.421439 u2DelayCellTimex100 = 270/100 ps
4412 23:41:59.424816 CA0 delay=35 (5~65),Diff = 2 PI (19 cell)
4413 23:41:59.427910 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4414 23:41:59.431695 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4415 23:41:59.434621 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 23:41:59.438241 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4417 23:41:59.444529 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4418 23:41:59.444635
4419 23:41:59.447767 CA PerBit enable=1, Macro0, CA PI delay=33
4420 23:41:59.447841
4421 23:41:59.451395 [CBTSetCACLKResult] CA Dly = 33
4422 23:41:59.451493 CS Dly: 4 (0~35)
4423 23:41:59.451580
4424 23:41:59.454607 ----->DramcWriteLeveling(PI) begin...
4425 23:41:59.454705 ==
4426 23:41:59.457902 Dram Type= 6, Freq= 0, CH_1, rank 0
4427 23:41:59.461232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4428 23:41:59.464652 ==
4429 23:41:59.464738 Write leveling (Byte 0): 30 => 30
4430 23:41:59.468601 Write leveling (Byte 1): 32 => 32
4431 23:41:59.471881 DramcWriteLeveling(PI) end<-----
4432 23:41:59.471962
4433 23:41:59.472026 ==
4434 23:41:59.474704 Dram Type= 6, Freq= 0, CH_1, rank 0
4435 23:41:59.481039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4436 23:41:59.481128 ==
4437 23:41:59.484766 [Gating] SW mode calibration
4438 23:41:59.491374 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4439 23:41:59.495018 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4440 23:41:59.497898 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4441 23:41:59.504650 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4442 23:41:59.508089 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4443 23:41:59.511360 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4444 23:41:59.518307 0 9 16 | B1->B0 | 2525 2626 | 0 0 | (0 0) (1 1)
4445 23:41:59.521672 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 23:41:59.525114 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 23:41:59.531565 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 23:41:59.534962 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 23:41:59.538331 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4450 23:41:59.544969 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4451 23:41:59.548336 0 10 12 | B1->B0 | 2626 2b2b | 0 0 | (0 0) (0 0)
4452 23:41:59.551416 0 10 16 | B1->B0 | 3636 3e3e | 0 1 | (0 0) (0 0)
4453 23:41:59.558058 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 23:41:59.561702 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 23:41:59.564905 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 23:41:59.568368 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 23:41:59.575053 0 11 4 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
4458 23:41:59.578471 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4459 23:41:59.581861 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4460 23:41:59.588316 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4461 23:41:59.592026 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 23:41:59.594933 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 23:41:59.601776 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 23:41:59.605353 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 23:41:59.608788 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 23:41:59.614808 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 23:41:59.618143 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 23:41:59.622042 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 23:41:59.628107 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 23:41:59.631551 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 23:41:59.635265 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 23:41:59.641541 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 23:41:59.645450 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 23:41:59.648096 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4475 23:41:59.655042 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4476 23:41:59.658339 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4477 23:41:59.661403 Total UI for P1: 0, mck2ui 16
4478 23:41:59.665025 best dqsien dly found for B1: ( 0, 13, 12)
4479 23:41:59.668234 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 23:41:59.671424 Total UI for P1: 0, mck2ui 16
4481 23:41:59.675182 best dqsien dly found for B0: ( 0, 13, 16)
4482 23:41:59.678351 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4483 23:41:59.681728 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4484 23:41:59.681860
4485 23:41:59.684872 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4486 23:41:59.691695 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4487 23:41:59.691780 [Gating] SW calibration Done
4488 23:41:59.691864 ==
4489 23:41:59.695714 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 23:41:59.702209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 23:41:59.702298 ==
4492 23:41:59.702363 RX Vref Scan: 0
4493 23:41:59.702423
4494 23:41:59.704756 RX Vref 0 -> 0, step: 1
4495 23:41:59.704865
4496 23:41:59.708633 RX Delay -230 -> 252, step: 16
4497 23:41:59.711475 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4498 23:41:59.715147 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4499 23:41:59.718079 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4500 23:41:59.725117 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4501 23:41:59.728290 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4502 23:41:59.731707 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4503 23:41:59.734804 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4504 23:41:59.741910 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4505 23:41:59.744727 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4506 23:41:59.748454 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4507 23:41:59.751909 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4508 23:41:59.755246 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4509 23:41:59.761827 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4510 23:41:59.764841 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4511 23:41:59.768136 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4512 23:41:59.771552 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4513 23:41:59.774868 ==
4514 23:41:59.774947 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 23:41:59.781610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 23:41:59.781695 ==
4517 23:41:59.781760 DQS Delay:
4518 23:41:59.784683 DQS0 = 0, DQS1 = 0
4519 23:41:59.784784 DQM Delay:
4520 23:41:59.788086 DQM0 = 44, DQM1 = 35
4521 23:41:59.788197 DQ Delay:
4522 23:41:59.791799 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4523 23:41:59.795150 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4524 23:41:59.797941 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4525 23:41:59.801535 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4526 23:41:59.801626
4527 23:41:59.801691
4528 23:41:59.801750 ==
4529 23:41:59.804840 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 23:41:59.808257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 23:41:59.808366 ==
4532 23:41:59.808457
4533 23:41:59.808553
4534 23:41:59.811929 TX Vref Scan disable
4535 23:41:59.814751 == TX Byte 0 ==
4536 23:41:59.818315 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4537 23:41:59.821666 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4538 23:41:59.825126 == TX Byte 1 ==
4539 23:41:59.827978 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4540 23:41:59.831504 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4541 23:41:59.831589 ==
4542 23:41:59.835100 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 23:41:59.838076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 23:41:59.838171 ==
4545 23:41:59.841523
4546 23:41:59.841626
4547 23:41:59.841726 TX Vref Scan disable
4548 23:41:59.845183 == TX Byte 0 ==
4549 23:41:59.848481 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4550 23:41:59.851843 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4551 23:41:59.855682 == TX Byte 1 ==
4552 23:41:59.859024 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4553 23:41:59.861694 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4554 23:41:59.865231
4555 23:41:59.865378 [DATLAT]
4556 23:41:59.865515 Freq=600, CH1 RK0
4557 23:41:59.865635
4558 23:41:59.868819 DATLAT Default: 0x9
4559 23:41:59.868955 0, 0xFFFF, sum = 0
4560 23:41:59.871725 1, 0xFFFF, sum = 0
4561 23:41:59.871859 2, 0xFFFF, sum = 0
4562 23:41:59.874993 3, 0xFFFF, sum = 0
4563 23:41:59.875129 4, 0xFFFF, sum = 0
4564 23:41:59.878853 5, 0xFFFF, sum = 0
4565 23:41:59.882021 6, 0xFFFF, sum = 0
4566 23:41:59.882106 7, 0xFFFF, sum = 0
4567 23:41:59.882185 8, 0x0, sum = 1
4568 23:41:59.885213 9, 0x0, sum = 2
4569 23:41:59.885289 10, 0x0, sum = 3
4570 23:41:59.888835 11, 0x0, sum = 4
4571 23:41:59.888941 best_step = 9
4572 23:41:59.889042
4573 23:41:59.889142 ==
4574 23:41:59.891783 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 23:41:59.898745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 23:41:59.898850 ==
4577 23:41:59.898934 RX Vref Scan: 1
4578 23:41:59.898996
4579 23:41:59.901666 RX Vref 0 -> 0, step: 1
4580 23:41:59.901741
4581 23:41:59.905546 RX Delay -195 -> 252, step: 8
4582 23:41:59.905623
4583 23:41:59.908506 Set Vref, RX VrefLevel [Byte0]: 58
4584 23:41:59.912091 [Byte1]: 52
4585 23:41:59.912174
4586 23:41:59.915164 Final RX Vref Byte 0 = 58 to rank0
4587 23:41:59.919038 Final RX Vref Byte 1 = 52 to rank0
4588 23:41:59.921885 Final RX Vref Byte 0 = 58 to rank1
4589 23:41:59.925583 Final RX Vref Byte 1 = 52 to rank1==
4590 23:41:59.928364 Dram Type= 6, Freq= 0, CH_1, rank 0
4591 23:41:59.931971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 23:41:59.932108 ==
4593 23:41:59.935264 DQS Delay:
4594 23:41:59.935401 DQS0 = 0, DQS1 = 0
4595 23:41:59.935549 DQM Delay:
4596 23:41:59.938727 DQM0 = 40, DQM1 = 32
4597 23:41:59.938861 DQ Delay:
4598 23:41:59.941750 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4599 23:41:59.945181 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4600 23:41:59.948816 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4601 23:41:59.952071 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4602 23:41:59.952204
4603 23:41:59.952327
4604 23:41:59.961760 [DQSOSCAuto] RK0, (LSB)MR18= 0x470e, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4605 23:41:59.961896 CH1 RK0: MR19=808, MR18=470E
4606 23:41:59.968885 CH1_RK0: MR19=0x808, MR18=0x470E, DQSOSC=396, MR23=63, INC=167, DEC=111
4607 23:41:59.969016
4608 23:41:59.972193 ----->DramcWriteLeveling(PI) begin...
4609 23:41:59.972296 ==
4610 23:41:59.975393 Dram Type= 6, Freq= 0, CH_1, rank 1
4611 23:41:59.982216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4612 23:41:59.982331 ==
4613 23:41:59.985807 Write leveling (Byte 0): 32 => 32
4614 23:41:59.988967 Write leveling (Byte 1): 32 => 32
4615 23:41:59.989078 DramcWriteLeveling(PI) end<-----
4616 23:41:59.989183
4617 23:41:59.992162 ==
4618 23:41:59.995259 Dram Type= 6, Freq= 0, CH_1, rank 1
4619 23:41:59.998568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4620 23:41:59.998673 ==
4621 23:42:00.002165 [Gating] SW mode calibration
4622 23:42:00.008537 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4623 23:42:00.012539 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4624 23:42:00.018656 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4625 23:42:00.021869 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4626 23:42:00.025272 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4627 23:42:00.032318 0 9 12 | B1->B0 | 3131 2d2d | 1 0 | (1 1) (0 0)
4628 23:42:00.035116 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4629 23:42:00.038482 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4630 23:42:00.045215 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 23:42:00.048821 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4632 23:42:00.052315 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 23:42:00.058828 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4634 23:42:00.061623 0 10 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
4635 23:42:00.065376 0 10 12 | B1->B0 | 2e2e 3c3c | 0 0 | (0 0) (1 1)
4636 23:42:00.068843 0 10 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
4637 23:42:00.075342 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 23:42:00.079107 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 23:42:00.082596 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 23:42:00.088687 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 23:42:00.092111 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4642 23:42:00.095376 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 23:42:00.101853 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4644 23:42:00.105039 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 23:42:00.108365 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 23:42:00.115194 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 23:42:00.118503 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 23:42:00.122132 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 23:42:00.128775 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 23:42:00.131802 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 23:42:00.135224 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 23:42:00.141729 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 23:42:00.145491 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 23:42:00.148955 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 23:42:00.155307 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 23:42:00.159782 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 23:42:00.162194 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4658 23:42:00.165264 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4659 23:42:00.171790 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4660 23:42:00.175645 Total UI for P1: 0, mck2ui 16
4661 23:42:00.178931 best dqsien dly found for B0: ( 0, 13, 10)
4662 23:42:00.182247 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 23:42:00.185676 Total UI for P1: 0, mck2ui 16
4664 23:42:00.188602 best dqsien dly found for B1: ( 0, 13, 12)
4665 23:42:00.191836 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4666 23:42:00.195325 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4667 23:42:00.195413
4668 23:42:00.198894 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4669 23:42:00.201890 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4670 23:42:00.205334 [Gating] SW calibration Done
4671 23:42:00.205412 ==
4672 23:42:00.208614 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 23:42:00.215456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 23:42:00.215539 ==
4675 23:42:00.215605 RX Vref Scan: 0
4676 23:42:00.215668
4677 23:42:00.218560 RX Vref 0 -> 0, step: 1
4678 23:42:00.218631
4679 23:42:00.222358 RX Delay -230 -> 252, step: 16
4680 23:42:00.225197 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4681 23:42:00.228502 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4682 23:42:00.232055 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4683 23:42:00.239042 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4684 23:42:00.241955 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4685 23:42:00.245433 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4686 23:42:00.248530 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4687 23:42:00.252243 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4688 23:42:00.258504 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4689 23:42:00.261890 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4690 23:42:00.265280 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4691 23:42:00.268812 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4692 23:42:00.275253 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4693 23:42:00.278939 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4694 23:42:00.282208 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4695 23:42:00.285584 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4696 23:42:00.285689 ==
4697 23:42:00.288886 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 23:42:00.295141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 23:42:00.295249 ==
4700 23:42:00.295347 DQS Delay:
4701 23:42:00.298556 DQS0 = 0, DQS1 = 0
4702 23:42:00.298670 DQM Delay:
4703 23:42:00.298765 DQM0 = 40, DQM1 = 37
4704 23:42:00.302232 DQ Delay:
4705 23:42:00.305517 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4706 23:42:00.308517 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4707 23:42:00.312251 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4708 23:42:00.315431 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4709 23:42:00.315537
4710 23:42:00.315631
4711 23:42:00.315722 ==
4712 23:42:00.318689 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 23:42:00.321778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 23:42:00.321854 ==
4715 23:42:00.321919
4716 23:42:00.321979
4717 23:42:00.325208 TX Vref Scan disable
4718 23:42:00.325285 == TX Byte 0 ==
4719 23:42:00.332032 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4720 23:42:00.335382 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4721 23:42:00.335488 == TX Byte 1 ==
4722 23:42:00.342172 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4723 23:42:00.345372 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4724 23:42:00.345479 ==
4725 23:42:00.348856 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 23:42:00.352351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 23:42:00.352454 ==
4728 23:42:00.352550
4729 23:42:00.354945
4730 23:42:00.355049 TX Vref Scan disable
4731 23:42:00.358717 == TX Byte 0 ==
4732 23:42:00.361839 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4733 23:42:00.365542 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4734 23:42:00.368587 == TX Byte 1 ==
4735 23:42:00.371895 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4736 23:42:00.375654 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4737 23:42:00.378614
4738 23:42:00.378684 [DATLAT]
4739 23:42:00.378746 Freq=600, CH1 RK1
4740 23:42:00.378808
4741 23:42:00.381931 DATLAT Default: 0x9
4742 23:42:00.382007 0, 0xFFFF, sum = 0
4743 23:42:00.385330 1, 0xFFFF, sum = 0
4744 23:42:00.385406 2, 0xFFFF, sum = 0
4745 23:42:00.388670 3, 0xFFFF, sum = 0
4746 23:42:00.388742 4, 0xFFFF, sum = 0
4747 23:42:00.391583 5, 0xFFFF, sum = 0
4748 23:42:00.395068 6, 0xFFFF, sum = 0
4749 23:42:00.395143 7, 0xFFFF, sum = 0
4750 23:42:00.395206 8, 0x0, sum = 1
4751 23:42:00.398780 9, 0x0, sum = 2
4752 23:42:00.398862 10, 0x0, sum = 3
4753 23:42:00.402191 11, 0x0, sum = 4
4754 23:42:00.402264 best_step = 9
4755 23:42:00.402324
4756 23:42:00.402385 ==
4757 23:42:00.405046 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 23:42:00.411932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 23:42:00.412009 ==
4760 23:42:00.412071 RX Vref Scan: 0
4761 23:42:00.412131
4762 23:42:00.415132 RX Vref 0 -> 0, step: 1
4763 23:42:00.415200
4764 23:42:00.418474 RX Delay -179 -> 252, step: 8
4765 23:42:00.421733 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4766 23:42:00.428359 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4767 23:42:00.431994 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4768 23:42:00.435092 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4769 23:42:00.438363 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4770 23:42:00.441747 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4771 23:42:00.448697 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4772 23:42:00.452148 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4773 23:42:00.455429 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4774 23:42:00.458612 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4775 23:42:00.461714 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4776 23:42:00.469224 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4777 23:42:00.471963 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4778 23:42:00.476321 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4779 23:42:00.478941 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4780 23:42:00.485345 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4781 23:42:00.485425 ==
4782 23:42:00.488652 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 23:42:00.491884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 23:42:00.491995 ==
4785 23:42:00.492094 DQS Delay:
4786 23:42:00.495581 DQS0 = 0, DQS1 = 0
4787 23:42:00.495686 DQM Delay:
4788 23:42:00.498711 DQM0 = 38, DQM1 = 32
4789 23:42:00.498815 DQ Delay:
4790 23:42:00.502245 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4791 23:42:00.505579 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =32
4792 23:42:00.508826 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4793 23:42:00.512230 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4794 23:42:00.512336
4795 23:42:00.512430
4796 23:42:00.519232 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a49, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
4797 23:42:00.522347 CH1 RK1: MR19=808, MR18=3A49
4798 23:42:00.528816 CH1_RK1: MR19=0x808, MR18=0x3A49, DQSOSC=396, MR23=63, INC=167, DEC=111
4799 23:42:00.532668 [RxdqsGatingPostProcess] freq 600
4800 23:42:00.538788 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4801 23:42:00.541809 Pre-setting of DQS Precalculation
4802 23:42:00.545207 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4803 23:42:00.551978 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4804 23:42:00.558810 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4805 23:42:00.558923
4806 23:42:00.559028
4807 23:42:00.562153 [Calibration Summary] 1200 Mbps
4808 23:42:00.565480 CH 0, Rank 0
4809 23:42:00.565585 SW Impedance : PASS
4810 23:42:00.569206 DUTY Scan : NO K
4811 23:42:00.572193 ZQ Calibration : PASS
4812 23:42:00.572301 Jitter Meter : NO K
4813 23:42:00.575752 CBT Training : PASS
4814 23:42:00.578757 Write leveling : PASS
4815 23:42:00.578866 RX DQS gating : PASS
4816 23:42:00.582305 RX DQ/DQS(RDDQC) : PASS
4817 23:42:00.582412 TX DQ/DQS : PASS
4818 23:42:00.585614 RX DATLAT : PASS
4819 23:42:00.588489 RX DQ/DQS(Engine): PASS
4820 23:42:00.588593 TX OE : NO K
4821 23:42:00.591949 All Pass.
4822 23:42:00.592054
4823 23:42:00.592150 CH 0, Rank 1
4824 23:42:00.595549 SW Impedance : PASS
4825 23:42:00.595654 DUTY Scan : NO K
4826 23:42:00.598475 ZQ Calibration : PASS
4827 23:42:00.602261 Jitter Meter : NO K
4828 23:42:00.602363 CBT Training : PASS
4829 23:42:00.605574 Write leveling : PASS
4830 23:42:00.608800 RX DQS gating : PASS
4831 23:42:00.608902 RX DQ/DQS(RDDQC) : PASS
4832 23:42:00.612213 TX DQ/DQS : PASS
4833 23:42:00.615621 RX DATLAT : PASS
4834 23:42:00.615724 RX DQ/DQS(Engine): PASS
4835 23:42:00.618800 TX OE : NO K
4836 23:42:00.618903 All Pass.
4837 23:42:00.619007
4838 23:42:00.622067 CH 1, Rank 0
4839 23:42:00.622172 SW Impedance : PASS
4840 23:42:00.625884 DUTY Scan : NO K
4841 23:42:00.625992 ZQ Calibration : PASS
4842 23:42:00.629029 Jitter Meter : NO K
4843 23:42:00.632445 CBT Training : PASS
4844 23:42:00.632552 Write leveling : PASS
4845 23:42:00.635417 RX DQS gating : PASS
4846 23:42:00.638790 RX DQ/DQS(RDDQC) : PASS
4847 23:42:00.638895 TX DQ/DQS : PASS
4848 23:42:00.642034 RX DATLAT : PASS
4849 23:42:00.645434 RX DQ/DQS(Engine): PASS
4850 23:42:00.645538 TX OE : NO K
4851 23:42:00.649240 All Pass.
4852 23:42:00.649342
4853 23:42:00.649436 CH 1, Rank 1
4854 23:42:00.652229 SW Impedance : PASS
4855 23:42:00.652331 DUTY Scan : NO K
4856 23:42:00.655376 ZQ Calibration : PASS
4857 23:42:00.658806 Jitter Meter : NO K
4858 23:42:00.658912 CBT Training : PASS
4859 23:42:00.661902 Write leveling : PASS
4860 23:42:00.665656 RX DQS gating : PASS
4861 23:42:00.665765 RX DQ/DQS(RDDQC) : PASS
4862 23:42:00.668557 TX DQ/DQS : PASS
4863 23:42:00.668671 RX DATLAT : PASS
4864 23:42:00.672542 RX DQ/DQS(Engine): PASS
4865 23:42:00.675184 TX OE : NO K
4866 23:42:00.675295 All Pass.
4867 23:42:00.675387
4868 23:42:00.678578 DramC Write-DBI off
4869 23:42:00.678685 PER_BANK_REFRESH: Hybrid Mode
4870 23:42:00.681894 TX_TRACKING: ON
4871 23:42:00.688890 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4872 23:42:00.695952 [FAST_K] Save calibration result to emmc
4873 23:42:00.699330 dramc_set_vcore_voltage set vcore to 662500
4874 23:42:00.699442 Read voltage for 933, 3
4875 23:42:00.702751 Vio18 = 0
4876 23:42:00.702846 Vcore = 662500
4877 23:42:00.702932 Vdram = 0
4878 23:42:00.705575 Vddq = 0
4879 23:42:00.705673 Vmddr = 0
4880 23:42:00.709008 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4881 23:42:00.715431 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4882 23:42:00.718912 MEM_TYPE=3, freq_sel=17
4883 23:42:00.722202 sv_algorithm_assistance_LP4_1600
4884 23:42:00.725725 ============ PULL DRAM RESETB DOWN ============
4885 23:42:00.728852 ========== PULL DRAM RESETB DOWN end =========
4886 23:42:00.732136 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4887 23:42:00.735409 ===================================
4888 23:42:00.738689 LPDDR4 DRAM CONFIGURATION
4889 23:42:00.742024 ===================================
4890 23:42:00.745338 EX_ROW_EN[0] = 0x0
4891 23:42:00.745439 EX_ROW_EN[1] = 0x0
4892 23:42:00.749007 LP4Y_EN = 0x0
4893 23:42:00.749125 WORK_FSP = 0x0
4894 23:42:00.752285 WL = 0x3
4895 23:42:00.752385 RL = 0x3
4896 23:42:00.755474 BL = 0x2
4897 23:42:00.755583 RPST = 0x0
4898 23:42:00.759127 RD_PRE = 0x0
4899 23:42:00.759229 WR_PRE = 0x1
4900 23:42:00.761879 WR_PST = 0x0
4901 23:42:00.765333 DBI_WR = 0x0
4902 23:42:00.765435 DBI_RD = 0x0
4903 23:42:00.769214 OTF = 0x1
4904 23:42:00.771922 ===================================
4905 23:42:00.775309 ===================================
4906 23:42:00.775412 ANA top config
4907 23:42:00.778498 ===================================
4908 23:42:00.781855 DLL_ASYNC_EN = 0
4909 23:42:00.781964 ALL_SLAVE_EN = 1
4910 23:42:00.786477 NEW_RANK_MODE = 1
4911 23:42:00.788805 DLL_IDLE_MODE = 1
4912 23:42:00.792068 LP45_APHY_COMB_EN = 1
4913 23:42:00.795601 TX_ODT_DIS = 1
4914 23:42:00.795717 NEW_8X_MODE = 1
4915 23:42:00.798710 ===================================
4916 23:42:00.802147 ===================================
4917 23:42:00.805159 data_rate = 1866
4918 23:42:00.808809 CKR = 1
4919 23:42:00.811840 DQ_P2S_RATIO = 8
4920 23:42:00.815046 ===================================
4921 23:42:00.818598 CA_P2S_RATIO = 8
4922 23:42:00.821923 DQ_CA_OPEN = 0
4923 23:42:00.822030 DQ_SEMI_OPEN = 0
4924 23:42:00.825081 CA_SEMI_OPEN = 0
4925 23:42:00.828736 CA_FULL_RATE = 0
4926 23:42:00.831824 DQ_CKDIV4_EN = 1
4927 23:42:00.835104 CA_CKDIV4_EN = 1
4928 23:42:00.835218 CA_PREDIV_EN = 0
4929 23:42:00.838708 PH8_DLY = 0
4930 23:42:00.841793 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4931 23:42:00.845579 DQ_AAMCK_DIV = 4
4932 23:42:00.848794 CA_AAMCK_DIV = 4
4933 23:42:00.852279 CA_ADMCK_DIV = 4
4934 23:42:00.852392 DQ_TRACK_CA_EN = 0
4935 23:42:00.855584 CA_PICK = 933
4936 23:42:00.858896 CA_MCKIO = 933
4937 23:42:00.861947 MCKIO_SEMI = 0
4938 23:42:00.865804 PLL_FREQ = 3732
4939 23:42:00.868559 DQ_UI_PI_RATIO = 32
4940 23:42:00.872140 CA_UI_PI_RATIO = 0
4941 23:42:00.875609 ===================================
4942 23:42:00.878740 ===================================
4943 23:42:00.878869 memory_type:LPDDR4
4944 23:42:00.881812 GP_NUM : 10
4945 23:42:00.885275 SRAM_EN : 1
4946 23:42:00.885377 MD32_EN : 0
4947 23:42:00.888555 ===================================
4948 23:42:00.892297 [ANA_INIT] >>>>>>>>>>>>>>
4949 23:42:00.895530 <<<<<< [CONFIGURE PHASE]: ANA_TX
4950 23:42:00.898674 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4951 23:42:00.902000 ===================================
4952 23:42:00.905370 data_rate = 1866,PCW = 0X8f00
4953 23:42:00.908684 ===================================
4954 23:42:00.912142 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4955 23:42:00.915482 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4956 23:42:00.922113 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4957 23:42:00.925553 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4958 23:42:00.928804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4959 23:42:00.932382 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4960 23:42:00.935238 [ANA_INIT] flow start
4961 23:42:00.938786 [ANA_INIT] PLL >>>>>>>>
4962 23:42:00.938922 [ANA_INIT] PLL <<<<<<<<
4963 23:42:00.942285 [ANA_INIT] MIDPI >>>>>>>>
4964 23:42:00.945236 [ANA_INIT] MIDPI <<<<<<<<
4965 23:42:00.945319 [ANA_INIT] DLL >>>>>>>>
4966 23:42:00.949206 [ANA_INIT] flow end
4967 23:42:00.952050 ============ LP4 DIFF to SE enter ============
4968 23:42:00.955466 ============ LP4 DIFF to SE exit ============
4969 23:42:00.958957 [ANA_INIT] <<<<<<<<<<<<<
4970 23:42:00.962165 [Flow] Enable top DCM control >>>>>
4971 23:42:00.965343 [Flow] Enable top DCM control <<<<<
4972 23:42:00.968736 Enable DLL master slave shuffle
4973 23:42:00.976081 ==============================================================
4974 23:42:00.976236 Gating Mode config
4975 23:42:00.982511 ==============================================================
4976 23:42:00.982656 Config description:
4977 23:42:00.992536 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4978 23:42:00.999087 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4979 23:42:01.005553 SELPH_MODE 0: By rank 1: By Phase
4980 23:42:01.008756 ==============================================================
4981 23:42:01.011977 GAT_TRACK_EN = 1
4982 23:42:01.015699 RX_GATING_MODE = 2
4983 23:42:01.019066 RX_GATING_TRACK_MODE = 2
4984 23:42:01.022177 SELPH_MODE = 1
4985 23:42:01.025407 PICG_EARLY_EN = 1
4986 23:42:01.028604 VALID_LAT_VALUE = 1
4987 23:42:01.032199 ==============================================================
4988 23:42:01.036011 Enter into Gating configuration >>>>
4989 23:42:01.039162 Exit from Gating configuration <<<<
4990 23:42:01.042205 Enter into DVFS_PRE_config >>>>>
4991 23:42:01.055998 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4992 23:42:01.059389 Exit from DVFS_PRE_config <<<<<
4993 23:42:01.059492 Enter into PICG configuration >>>>
4994 23:42:01.062549 Exit from PICG configuration <<<<
4995 23:42:01.065810 [RX_INPUT] configuration >>>>>
4996 23:42:01.069038 [RX_INPUT] configuration <<<<<
4997 23:42:01.075608 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4998 23:42:01.078696 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4999 23:42:01.085352 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5000 23:42:01.092739 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5001 23:42:01.098971 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5002 23:42:01.105875 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5003 23:42:01.108970 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5004 23:42:01.112700 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5005 23:42:01.115613 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5006 23:42:01.122558 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5007 23:42:01.125803 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5008 23:42:01.128553 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5009 23:42:01.132068 ===================================
5010 23:42:01.135675 LPDDR4 DRAM CONFIGURATION
5011 23:42:01.138974 ===================================
5012 23:42:01.139059 EX_ROW_EN[0] = 0x0
5013 23:42:01.142627 EX_ROW_EN[1] = 0x0
5014 23:42:01.145735 LP4Y_EN = 0x0
5015 23:42:01.145820 WORK_FSP = 0x0
5016 23:42:01.148825 WL = 0x3
5017 23:42:01.148909 RL = 0x3
5018 23:42:01.152377 BL = 0x2
5019 23:42:01.152480 RPST = 0x0
5020 23:42:01.155397 RD_PRE = 0x0
5021 23:42:01.155482 WR_PRE = 0x1
5022 23:42:01.159095 WR_PST = 0x0
5023 23:42:01.159179 DBI_WR = 0x0
5024 23:42:01.162268 DBI_RD = 0x0
5025 23:42:01.162352 OTF = 0x1
5026 23:42:01.166158 ===================================
5027 23:42:01.168739 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5028 23:42:01.175701 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5029 23:42:01.178779 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5030 23:42:01.182523 ===================================
5031 23:42:01.185828 LPDDR4 DRAM CONFIGURATION
5032 23:42:01.188917 ===================================
5033 23:42:01.189066 EX_ROW_EN[0] = 0x10
5034 23:42:01.192705 EX_ROW_EN[1] = 0x0
5035 23:42:01.192813 LP4Y_EN = 0x0
5036 23:42:01.195733 WORK_FSP = 0x0
5037 23:42:01.195813 WL = 0x3
5038 23:42:01.199085 RL = 0x3
5039 23:42:01.199197 BL = 0x2
5040 23:42:01.202641 RPST = 0x0
5041 23:42:01.202744 RD_PRE = 0x0
5042 23:42:01.205751 WR_PRE = 0x1
5043 23:42:01.205855 WR_PST = 0x0
5044 23:42:01.209358 DBI_WR = 0x0
5045 23:42:01.209463 DBI_RD = 0x0
5046 23:42:01.212872 OTF = 0x1
5047 23:42:01.216097 ===================================
5048 23:42:01.222701 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5049 23:42:01.226028 nWR fixed to 30
5050 23:42:01.229027 [ModeRegInit_LP4] CH0 RK0
5051 23:42:01.229150 [ModeRegInit_LP4] CH0 RK1
5052 23:42:01.232636 [ModeRegInit_LP4] CH1 RK0
5053 23:42:01.236099 [ModeRegInit_LP4] CH1 RK1
5054 23:42:01.236198 match AC timing 9
5055 23:42:01.243496 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5056 23:42:01.246321 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5057 23:42:01.249603 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5058 23:42:01.255776 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5059 23:42:01.258905 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5060 23:42:01.259037 ==
5061 23:42:01.262546 Dram Type= 6, Freq= 0, CH_0, rank 0
5062 23:42:01.265863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5063 23:42:01.265946 ==
5064 23:42:01.272706 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5065 23:42:01.279223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5066 23:42:01.282601 [CA 0] Center 38 (8~69) winsize 62
5067 23:42:01.286039 [CA 1] Center 38 (8~68) winsize 61
5068 23:42:01.288952 [CA 2] Center 35 (5~66) winsize 62
5069 23:42:01.292593 [CA 3] Center 34 (4~65) winsize 62
5070 23:42:01.295727 [CA 4] Center 34 (4~65) winsize 62
5071 23:42:01.299291 [CA 5] Center 34 (4~64) winsize 61
5072 23:42:01.299374
5073 23:42:01.302373 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5074 23:42:01.302455
5075 23:42:01.305922 [CATrainingPosCal] consider 1 rank data
5076 23:42:01.309620 u2DelayCellTimex100 = 270/100 ps
5077 23:42:01.312959 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5078 23:42:01.315867 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5079 23:42:01.318942 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5080 23:42:01.322672 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5081 23:42:01.326043 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5082 23:42:01.329173 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5083 23:42:01.329282
5084 23:42:01.336052 CA PerBit enable=1, Macro0, CA PI delay=34
5085 23:42:01.336150
5086 23:42:01.336228 [CBTSetCACLKResult] CA Dly = 34
5087 23:42:01.339191 CS Dly: 6 (0~37)
5088 23:42:01.339271 ==
5089 23:42:01.342653 Dram Type= 6, Freq= 0, CH_0, rank 1
5090 23:42:01.345643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 23:42:01.345729 ==
5092 23:42:01.353191 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5093 23:42:01.359137 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5094 23:42:01.362915 [CA 0] Center 38 (8~69) winsize 62
5095 23:42:01.365702 [CA 1] Center 37 (7~68) winsize 62
5096 23:42:01.369109 [CA 2] Center 35 (5~66) winsize 62
5097 23:42:01.372623 [CA 3] Center 35 (5~66) winsize 62
5098 23:42:01.376139 [CA 4] Center 33 (3~64) winsize 62
5099 23:42:01.379936 [CA 5] Center 33 (3~64) winsize 62
5100 23:42:01.380019
5101 23:42:01.382565 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5102 23:42:01.382647
5103 23:42:01.385767 [CATrainingPosCal] consider 2 rank data
5104 23:42:01.389297 u2DelayCellTimex100 = 270/100 ps
5105 23:42:01.392938 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5106 23:42:01.396109 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5107 23:42:01.399619 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5108 23:42:01.402710 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5109 23:42:01.405956 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5110 23:42:01.409700 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5111 23:42:01.409783
5112 23:42:01.415785 CA PerBit enable=1, Macro0, CA PI delay=34
5113 23:42:01.415868
5114 23:42:01.415950 [CBTSetCACLKResult] CA Dly = 34
5115 23:42:01.419174 CS Dly: 7 (0~39)
5116 23:42:01.419256
5117 23:42:01.422823 ----->DramcWriteLeveling(PI) begin...
5118 23:42:01.422935 ==
5119 23:42:01.425863 Dram Type= 6, Freq= 0, CH_0, rank 0
5120 23:42:01.429233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5121 23:42:01.429340 ==
5122 23:42:01.432385 Write leveling (Byte 0): 32 => 32
5123 23:42:01.435816 Write leveling (Byte 1): 28 => 28
5124 23:42:01.439240 DramcWriteLeveling(PI) end<-----
5125 23:42:01.439344
5126 23:42:01.439443 ==
5127 23:42:01.442395 Dram Type= 6, Freq= 0, CH_0, rank 0
5128 23:42:01.445871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5129 23:42:01.449301 ==
5130 23:42:01.449406 [Gating] SW mode calibration
5131 23:42:01.455940 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5132 23:42:01.462413 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5133 23:42:01.466185 0 14 0 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
5134 23:42:01.472836 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5135 23:42:01.476066 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 23:42:01.479049 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 23:42:01.485665 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 23:42:01.489818 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 23:42:01.492585 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5140 23:42:01.499521 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5141 23:42:01.502356 0 15 0 | B1->B0 | 3131 2f2f | 1 0 | (1 0) (0 1)
5142 23:42:01.505575 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5143 23:42:01.509331 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 23:42:01.515877 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 23:42:01.519110 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 23:42:01.522665 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 23:42:01.529268 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5148 23:42:01.533146 0 15 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5149 23:42:01.535692 1 0 0 | B1->B0 | 2f2f 3e3e | 0 0 | (0 0) (0 0)
5150 23:42:01.542676 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5151 23:42:01.545845 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 23:42:01.549418 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 23:42:01.556011 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 23:42:01.559258 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5155 23:42:01.562662 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 23:42:01.569066 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5157 23:42:01.573280 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5158 23:42:01.575925 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 23:42:01.582536 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 23:42:01.585946 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 23:42:01.589279 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 23:42:01.595935 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 23:42:01.598960 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 23:42:01.602729 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 23:42:01.606058 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 23:42:01.612582 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 23:42:01.616117 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 23:42:01.619836 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 23:42:01.625934 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 23:42:01.629295 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 23:42:01.632742 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5172 23:42:01.639537 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5173 23:42:01.642830 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5174 23:42:01.645669 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5175 23:42:01.652391 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 23:42:01.652506 Total UI for P1: 0, mck2ui 16
5177 23:42:01.659326 best dqsien dly found for B0: ( 1, 3, 0)
5178 23:42:01.659433 Total UI for P1: 0, mck2ui 16
5179 23:42:01.665752 best dqsien dly found for B1: ( 1, 3, 2)
5180 23:42:01.669586 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5181 23:42:01.672618 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5182 23:42:01.672738
5183 23:42:01.676057 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5184 23:42:01.679887 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5185 23:42:01.683306 [Gating] SW calibration Done
5186 23:42:01.683387 ==
5187 23:42:01.686123 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 23:42:01.689223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 23:42:01.689336 ==
5190 23:42:01.689440 RX Vref Scan: 0
5191 23:42:01.692470
5192 23:42:01.692550 RX Vref 0 -> 0, step: 1
5193 23:42:01.692614
5194 23:42:01.696069 RX Delay -80 -> 252, step: 8
5195 23:42:01.699461 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5196 23:42:01.702905 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5197 23:42:01.709417 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5198 23:42:01.713112 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5199 23:42:01.715663 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5200 23:42:01.719893 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5201 23:42:01.722494 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5202 23:42:01.726095 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5203 23:42:01.732854 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5204 23:42:01.736033 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5205 23:42:01.739554 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5206 23:42:01.742537 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5207 23:42:01.746115 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5208 23:42:01.749410 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5209 23:42:01.756016 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5210 23:42:01.759323 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5211 23:42:01.759427 ==
5212 23:42:01.762844 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 23:42:01.766073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 23:42:01.766176 ==
5215 23:42:01.769487 DQS Delay:
5216 23:42:01.769564 DQS0 = 0, DQS1 = 0
5217 23:42:01.769624 DQM Delay:
5218 23:42:01.772729 DQM0 = 97, DQM1 = 87
5219 23:42:01.772826 DQ Delay:
5220 23:42:01.775987 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5221 23:42:01.779453 DQ4 =99, DQ5 =87, DQ6 =111, DQ7 =103
5222 23:42:01.782762 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5223 23:42:01.786410 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5224 23:42:01.786487
5225 23:42:01.786549
5226 23:42:01.786620 ==
5227 23:42:01.789784 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 23:42:01.796119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 23:42:01.796228 ==
5230 23:42:01.796327
5231 23:42:01.796401
5232 23:42:01.796491 TX Vref Scan disable
5233 23:42:01.799977 == TX Byte 0 ==
5234 23:42:01.803106 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5235 23:42:01.809280 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5236 23:42:01.809360 == TX Byte 1 ==
5237 23:42:01.812518 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5238 23:42:01.819253 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5239 23:42:01.819359 ==
5240 23:42:01.822496 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 23:42:01.826379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 23:42:01.826484 ==
5243 23:42:01.826579
5244 23:42:01.826672
5245 23:42:01.829531 TX Vref Scan disable
5246 23:42:01.829626 == TX Byte 0 ==
5247 23:42:01.836134 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5248 23:42:01.839427 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5249 23:42:01.839532 == TX Byte 1 ==
5250 23:42:01.845968 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5251 23:42:01.848949 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5252 23:42:01.849080
5253 23:42:01.849148 [DATLAT]
5254 23:42:01.852617 Freq=933, CH0 RK0
5255 23:42:01.852716
5256 23:42:01.852808 DATLAT Default: 0xd
5257 23:42:01.855727 0, 0xFFFF, sum = 0
5258 23:42:01.855827 1, 0xFFFF, sum = 0
5259 23:42:01.859072 2, 0xFFFF, sum = 0
5260 23:42:01.859178 3, 0xFFFF, sum = 0
5261 23:42:01.862378 4, 0xFFFF, sum = 0
5262 23:42:01.862493 5, 0xFFFF, sum = 0
5263 23:42:01.865931 6, 0xFFFF, sum = 0
5264 23:42:01.866042 7, 0xFFFF, sum = 0
5265 23:42:01.869403 8, 0xFFFF, sum = 0
5266 23:42:01.872777 9, 0xFFFF, sum = 0
5267 23:42:01.872874 10, 0x0, sum = 1
5268 23:42:01.872996 11, 0x0, sum = 2
5269 23:42:01.875883 12, 0x0, sum = 3
5270 23:42:01.875989 13, 0x0, sum = 4
5271 23:42:01.879078 best_step = 11
5272 23:42:01.879151
5273 23:42:01.879249 ==
5274 23:42:01.882389 Dram Type= 6, Freq= 0, CH_0, rank 0
5275 23:42:01.885625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5276 23:42:01.885703 ==
5277 23:42:01.889442 RX Vref Scan: 1
5278 23:42:01.889524
5279 23:42:01.889608 RX Vref 0 -> 0, step: 1
5280 23:42:01.889697
5281 23:42:01.892340 RX Delay -61 -> 252, step: 4
5282 23:42:01.892435
5283 23:42:01.895673 Set Vref, RX VrefLevel [Byte0]: 51
5284 23:42:01.899550 [Byte1]: 52
5285 23:42:01.903739
5286 23:42:01.903815 Final RX Vref Byte 0 = 51 to rank0
5287 23:42:01.906740 Final RX Vref Byte 1 = 52 to rank0
5288 23:42:01.909956 Final RX Vref Byte 0 = 51 to rank1
5289 23:42:01.913528 Final RX Vref Byte 1 = 52 to rank1==
5290 23:42:01.916760 Dram Type= 6, Freq= 0, CH_0, rank 0
5291 23:42:01.923291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 23:42:01.923397 ==
5293 23:42:01.923489 DQS Delay:
5294 23:42:01.923575 DQS0 = 0, DQS1 = 0
5295 23:42:01.926253 DQM Delay:
5296 23:42:01.926355 DQM0 = 96, DQM1 = 87
5297 23:42:01.930125 DQ Delay:
5298 23:42:01.933304 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =96
5299 23:42:01.936750 DQ4 =98, DQ5 =86, DQ6 =104, DQ7 =102
5300 23:42:01.940247 DQ8 =78, DQ9 =78, DQ10 =88, DQ11 =80
5301 23:42:01.943057 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =96
5302 23:42:01.943167
5303 23:42:01.943259
5304 23:42:01.950076 [DQSOSCAuto] RK0, (LSB)MR18= 0x1601, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5305 23:42:01.953097 CH0 RK0: MR19=505, MR18=1601
5306 23:42:01.959449 CH0_RK0: MR19=0x505, MR18=0x1601, DQSOSC=414, MR23=63, INC=63, DEC=42
5307 23:42:01.959552
5308 23:42:01.962785 ----->DramcWriteLeveling(PI) begin...
5309 23:42:01.962886 ==
5310 23:42:01.966294 Dram Type= 6, Freq= 0, CH_0, rank 1
5311 23:42:01.969511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 23:42:01.969585 ==
5313 23:42:01.972874 Write leveling (Byte 0): 31 => 31
5314 23:42:01.976114 Write leveling (Byte 1): 30 => 30
5315 23:42:01.979591 DramcWriteLeveling(PI) end<-----
5316 23:42:01.979694
5317 23:42:01.979791 ==
5318 23:42:01.982884 Dram Type= 6, Freq= 0, CH_0, rank 1
5319 23:42:01.986526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 23:42:01.986639 ==
5321 23:42:01.989950 [Gating] SW mode calibration
5322 23:42:01.996296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5323 23:42:02.002766 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5324 23:42:02.006105 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
5325 23:42:02.010165 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5326 23:42:02.016139 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 23:42:02.019787 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5328 23:42:02.023140 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5329 23:42:02.030202 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5330 23:42:02.032867 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5331 23:42:02.036606 0 14 28 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 0)
5332 23:42:02.043203 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5333 23:42:02.046337 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)
5334 23:42:02.049637 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 23:42:02.056046 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 23:42:02.059441 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5337 23:42:02.062792 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 23:42:02.069869 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 23:42:02.072724 0 15 28 | B1->B0 | 2a2a 3333 | 0 0 | (0 0) (0 0)
5340 23:42:02.076271 1 0 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5341 23:42:02.083378 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 23:42:02.086749 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 23:42:02.090086 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 23:42:02.093300 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 23:42:02.100230 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 23:42:02.102948 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 23:42:02.106713 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5348 23:42:02.113429 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5349 23:42:02.116592 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5350 23:42:02.119583 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 23:42:02.126588 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 23:42:02.129810 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 23:42:02.133413 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 23:42:02.140176 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 23:42:02.143530 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 23:42:02.146504 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 23:42:02.153114 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 23:42:02.156310 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 23:42:02.159661 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 23:42:02.166268 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 23:42:02.170198 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 23:42:02.172938 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 23:42:02.179815 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5364 23:42:02.179921 Total UI for P1: 0, mck2ui 16
5365 23:42:02.182792 best dqsien dly found for B0: ( 1, 2, 26)
5366 23:42:02.189612 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5367 23:42:02.193229 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 23:42:02.196522 Total UI for P1: 0, mck2ui 16
5369 23:42:02.199324 best dqsien dly found for B1: ( 1, 3, 0)
5370 23:42:02.203153 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5371 23:42:02.206207 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5372 23:42:02.206318
5373 23:42:02.209799 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5374 23:42:02.215956 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5375 23:42:02.216086 [Gating] SW calibration Done
5376 23:42:02.216204 ==
5377 23:42:02.219844 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 23:42:02.226576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 23:42:02.226662 ==
5380 23:42:02.226727 RX Vref Scan: 0
5381 23:42:02.226787
5382 23:42:02.229332 RX Vref 0 -> 0, step: 1
5383 23:42:02.229401
5384 23:42:02.233211 RX Delay -80 -> 252, step: 8
5385 23:42:02.236409 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5386 23:42:02.240062 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5387 23:42:02.243066 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5388 23:42:02.246191 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5389 23:42:02.249624 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5390 23:42:02.256511 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5391 23:42:02.259848 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5392 23:42:02.262685 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5393 23:42:02.266219 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5394 23:42:02.269272 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5395 23:42:02.272794 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5396 23:42:02.279400 iDelay=200, Bit 11, Center 75 (-16 ~ 167) 184
5397 23:42:02.282496 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5398 23:42:02.286204 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5399 23:42:02.289331 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5400 23:42:02.292867 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5401 23:42:02.293003 ==
5402 23:42:02.296121 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 23:42:02.302748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 23:42:02.302854 ==
5405 23:42:02.302946 DQS Delay:
5406 23:42:02.306483 DQS0 = 0, DQS1 = 0
5407 23:42:02.306590 DQM Delay:
5408 23:42:02.306682 DQM0 = 97, DQM1 = 87
5409 23:42:02.309421 DQ Delay:
5410 23:42:02.312593 DQ0 =99, DQ1 =95, DQ2 =95, DQ3 =95
5411 23:42:02.316426 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5412 23:42:02.319239 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =75
5413 23:42:02.322695 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5414 23:42:02.322805
5415 23:42:02.322896
5416 23:42:02.322982 ==
5417 23:42:02.325946 Dram Type= 6, Freq= 0, CH_0, rank 1
5418 23:42:02.329446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5419 23:42:02.329528 ==
5420 23:42:02.329593
5421 23:42:02.329651
5422 23:42:02.332445 TX Vref Scan disable
5423 23:42:02.332549 == TX Byte 0 ==
5424 23:42:02.340020 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5425 23:42:02.343002 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5426 23:42:02.343106 == TX Byte 1 ==
5427 23:42:02.349888 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5428 23:42:02.353133 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5429 23:42:02.353233 ==
5430 23:42:02.356569 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 23:42:02.359771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 23:42:02.359870 ==
5433 23:42:02.359959
5434 23:42:02.363205
5435 23:42:02.363302 TX Vref Scan disable
5436 23:42:02.366563 == TX Byte 0 ==
5437 23:42:02.369721 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5438 23:42:02.372803 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5439 23:42:02.375939 == TX Byte 1 ==
5440 23:42:02.379320 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5441 23:42:02.382999 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5442 23:42:02.383097
5443 23:42:02.386286 [DATLAT]
5444 23:42:02.386384 Freq=933, CH0 RK1
5445 23:42:02.386475
5446 23:42:02.389817 DATLAT Default: 0xb
5447 23:42:02.389911 0, 0xFFFF, sum = 0
5448 23:42:02.392847 1, 0xFFFF, sum = 0
5449 23:42:02.392943 2, 0xFFFF, sum = 0
5450 23:42:02.396026 3, 0xFFFF, sum = 0
5451 23:42:02.396124 4, 0xFFFF, sum = 0
5452 23:42:02.399657 5, 0xFFFF, sum = 0
5453 23:42:02.399753 6, 0xFFFF, sum = 0
5454 23:42:02.403046 7, 0xFFFF, sum = 0
5455 23:42:02.403155 8, 0xFFFF, sum = 0
5456 23:42:02.406199 9, 0xFFFF, sum = 0
5457 23:42:02.406379 10, 0x0, sum = 1
5458 23:42:02.409967 11, 0x0, sum = 2
5459 23:42:02.410062 12, 0x0, sum = 3
5460 23:42:02.412944 13, 0x0, sum = 4
5461 23:42:02.413080 best_step = 11
5462 23:42:02.413173
5463 23:42:02.413243 ==
5464 23:42:02.416120 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 23:42:02.423153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 23:42:02.423252 ==
5467 23:42:02.423340 RX Vref Scan: 0
5468 23:42:02.423426
5469 23:42:02.425961 RX Vref 0 -> 0, step: 1
5470 23:42:02.426066
5471 23:42:02.429438 RX Delay -61 -> 252, step: 4
5472 23:42:02.432648 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5473 23:42:02.436361 iDelay=199, Bit 1, Center 98 (7 ~ 190) 184
5474 23:42:02.443049 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5475 23:42:02.446224 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5476 23:42:02.449692 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5477 23:42:02.452717 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5478 23:42:02.456669 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5479 23:42:02.459887 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5480 23:42:02.466390 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5481 23:42:02.469836 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5482 23:42:02.472771 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5483 23:42:02.475985 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5484 23:42:02.479463 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5485 23:42:02.482879 iDelay=199, Bit 13, Center 94 (7 ~ 182) 176
5486 23:42:02.489721 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5487 23:42:02.492896 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5488 23:42:02.492995 ==
5489 23:42:02.496789 Dram Type= 6, Freq= 0, CH_0, rank 1
5490 23:42:02.499516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 23:42:02.499614 ==
5492 23:42:02.499702 DQS Delay:
5493 23:42:02.503267 DQS0 = 0, DQS1 = 0
5494 23:42:02.503362 DQM Delay:
5495 23:42:02.506515 DQM0 = 96, DQM1 = 88
5496 23:42:02.506588 DQ Delay:
5497 23:42:02.510031 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5498 23:42:02.513592 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5499 23:42:02.516146 DQ8 =82, DQ9 =78, DQ10 =88, DQ11 =80
5500 23:42:02.519538 DQ12 =92, DQ13 =94, DQ14 =100, DQ15 =96
5501 23:42:02.519620
5502 23:42:02.519684
5503 23:42:02.529930 [DQSOSCAuto] RK1, (LSB)MR18= 0x1907, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5504 23:42:02.530014 CH0 RK1: MR19=505, MR18=1907
5505 23:42:02.536475 CH0_RK1: MR19=0x505, MR18=0x1907, DQSOSC=413, MR23=63, INC=63, DEC=42
5506 23:42:02.539966 [RxdqsGatingPostProcess] freq 933
5507 23:42:02.546683 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5508 23:42:02.549919 best DQS0 dly(2T, 0.5T) = (0, 11)
5509 23:42:02.553230 best DQS1 dly(2T, 0.5T) = (0, 11)
5510 23:42:02.556796 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5511 23:42:02.559961 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5512 23:42:02.560043 best DQS0 dly(2T, 0.5T) = (0, 10)
5513 23:42:02.563167 best DQS1 dly(2T, 0.5T) = (0, 11)
5514 23:42:02.566900 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5515 23:42:02.569999 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5516 23:42:02.572907 Pre-setting of DQS Precalculation
5517 23:42:02.579960 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5518 23:42:02.580060 ==
5519 23:42:02.583243 Dram Type= 6, Freq= 0, CH_1, rank 0
5520 23:42:02.586727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 23:42:02.586807 ==
5522 23:42:02.593266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5523 23:42:02.596940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5524 23:42:02.601102 [CA 0] Center 36 (6~67) winsize 62
5525 23:42:02.604596 [CA 1] Center 36 (6~67) winsize 62
5526 23:42:02.607992 [CA 2] Center 34 (4~64) winsize 61
5527 23:42:02.610756 [CA 3] Center 33 (3~64) winsize 62
5528 23:42:02.614621 [CA 4] Center 34 (3~65) winsize 63
5529 23:42:02.617718 [CA 5] Center 33 (3~63) winsize 61
5530 23:42:02.617815
5531 23:42:02.621130 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5532 23:42:02.621226
5533 23:42:02.624757 [CATrainingPosCal] consider 1 rank data
5534 23:42:02.627868 u2DelayCellTimex100 = 270/100 ps
5535 23:42:02.631222 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5536 23:42:02.634077 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5537 23:42:02.640874 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5538 23:42:02.644068 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5539 23:42:02.647560 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5540 23:42:02.651325 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5541 23:42:02.651405
5542 23:42:02.654244 CA PerBit enable=1, Macro0, CA PI delay=33
5543 23:42:02.654323
5544 23:42:02.658067 [CBTSetCACLKResult] CA Dly = 33
5545 23:42:02.658146 CS Dly: 4 (0~35)
5546 23:42:02.658211 ==
5547 23:42:02.661077 Dram Type= 6, Freq= 0, CH_1, rank 1
5548 23:42:02.667630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 23:42:02.667710 ==
5550 23:42:02.670935 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5551 23:42:02.677565 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5552 23:42:02.681429 [CA 0] Center 36 (6~67) winsize 62
5553 23:42:02.684100 [CA 1] Center 36 (6~67) winsize 62
5554 23:42:02.687848 [CA 2] Center 33 (3~64) winsize 62
5555 23:42:02.690689 [CA 3] Center 33 (3~64) winsize 62
5556 23:42:02.694289 [CA 4] Center 34 (4~64) winsize 61
5557 23:42:02.697736 [CA 5] Center 32 (2~63) winsize 62
5558 23:42:02.697809
5559 23:42:02.700675 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5560 23:42:02.700767
5561 23:42:02.704199 [CATrainingPosCal] consider 2 rank data
5562 23:42:02.707722 u2DelayCellTimex100 = 270/100 ps
5563 23:42:02.710960 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5564 23:42:02.714409 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5565 23:42:02.720543 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5566 23:42:02.724360 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5567 23:42:02.727447 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5568 23:42:02.731032 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5569 23:42:02.731112
5570 23:42:02.734493 CA PerBit enable=1, Macro0, CA PI delay=33
5571 23:42:02.734600
5572 23:42:02.738467 [CBTSetCACLKResult] CA Dly = 33
5573 23:42:02.738548 CS Dly: 5 (0~38)
5574 23:42:02.738611
5575 23:42:02.740989 ----->DramcWriteLeveling(PI) begin...
5576 23:42:02.744308 ==
5577 23:42:02.744389 Dram Type= 6, Freq= 0, CH_1, rank 0
5578 23:42:02.750711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 23:42:02.750793 ==
5580 23:42:02.754152 Write leveling (Byte 0): 27 => 27
5581 23:42:02.757685 Write leveling (Byte 1): 28 => 28
5582 23:42:02.760866 DramcWriteLeveling(PI) end<-----
5583 23:42:02.760946
5584 23:42:02.761019 ==
5585 23:42:02.764446 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 23:42:02.767711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5587 23:42:02.767792 ==
5588 23:42:02.771209 [Gating] SW mode calibration
5589 23:42:02.777445 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5590 23:42:02.781170 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5591 23:42:02.787783 0 14 0 | B1->B0 | 2f2f 3131 | 0 0 | (0 0) (0 0)
5592 23:42:02.791277 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 23:42:02.794105 0 14 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5594 23:42:02.800846 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 23:42:02.804138 0 14 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5596 23:42:02.807996 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5597 23:42:02.814363 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5598 23:42:02.817795 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
5599 23:42:02.820607 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5600 23:42:02.827372 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5601 23:42:02.830819 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 23:42:02.834371 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 23:42:02.840730 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5604 23:42:02.844155 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5605 23:42:02.847709 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5606 23:42:02.854257 0 15 28 | B1->B0 | 2f2f 2323 | 0 1 | (0 0) (0 0)
5607 23:42:02.857323 1 0 0 | B1->B0 | 4545 4242 | 0 0 | (1 1) (0 0)
5608 23:42:02.861139 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 23:42:02.863996 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 23:42:02.871189 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 23:42:02.873984 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5612 23:42:02.877666 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 23:42:02.884004 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5614 23:42:02.887285 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5615 23:42:02.890901 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 23:42:02.897975 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 23:42:02.900582 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 23:42:02.904257 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 23:42:02.910777 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 23:42:02.913988 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 23:42:02.917476 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 23:42:02.924323 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 23:42:02.927516 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 23:42:02.930998 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 23:42:02.937550 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 23:42:02.940748 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5627 23:42:02.944128 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5628 23:42:02.950923 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5629 23:42:02.954353 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5630 23:42:02.957309 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5631 23:42:02.960887 Total UI for P1: 0, mck2ui 16
5632 23:42:02.964520 best dqsien dly found for B0: ( 1, 2, 26)
5633 23:42:02.968066 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5634 23:42:02.974133 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 23:42:02.977395 Total UI for P1: 0, mck2ui 16
5636 23:42:02.981126 best dqsien dly found for B1: ( 1, 2, 30)
5637 23:42:02.984248 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5638 23:42:02.987666 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5639 23:42:02.987749
5640 23:42:02.990900 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5641 23:42:02.994131 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5642 23:42:02.997750 [Gating] SW calibration Done
5643 23:42:02.997832 ==
5644 23:42:03.000719 Dram Type= 6, Freq= 0, CH_1, rank 0
5645 23:42:03.004355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5646 23:42:03.004438 ==
5647 23:42:03.007300 RX Vref Scan: 0
5648 23:42:03.007383
5649 23:42:03.007466 RX Vref 0 -> 0, step: 1
5650 23:42:03.007545
5651 23:42:03.011171 RX Delay -80 -> 252, step: 8
5652 23:42:03.014049 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5653 23:42:03.021397 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5654 23:42:03.024192 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5655 23:42:03.028037 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5656 23:42:03.031432 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5657 23:42:03.034001 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5658 23:42:03.037914 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5659 23:42:03.044380 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5660 23:42:03.048016 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5661 23:42:03.050744 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5662 23:42:03.054351 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5663 23:42:03.057799 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5664 23:42:03.064097 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5665 23:42:03.068090 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5666 23:42:03.071291 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5667 23:42:03.074515 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5668 23:42:03.074598 ==
5669 23:42:03.077772 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 23:42:03.081201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 23:42:03.081284 ==
5672 23:42:03.084407 DQS Delay:
5673 23:42:03.084489 DQS0 = 0, DQS1 = 0
5674 23:42:03.084571 DQM Delay:
5675 23:42:03.087907 DQM0 = 95, DQM1 = 88
5676 23:42:03.087990 DQ Delay:
5677 23:42:03.091172 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5678 23:42:03.095241 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5679 23:42:03.098408 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5680 23:42:03.101176 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5681 23:42:03.101258
5682 23:42:03.101342
5683 23:42:03.101420 ==
5684 23:42:03.104690 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 23:42:03.111209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 23:42:03.111292 ==
5687 23:42:03.111376
5688 23:42:03.111453
5689 23:42:03.111529 TX Vref Scan disable
5690 23:42:03.114660 == TX Byte 0 ==
5691 23:42:03.118432 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5692 23:42:03.121451 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5693 23:42:03.125467 == TX Byte 1 ==
5694 23:42:03.128369 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5695 23:42:03.131447 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5696 23:42:03.135364 ==
5697 23:42:03.138266 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 23:42:03.142012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 23:42:03.142094 ==
5700 23:42:03.142177
5701 23:42:03.142255
5702 23:42:03.145190 TX Vref Scan disable
5703 23:42:03.145273 == TX Byte 0 ==
5704 23:42:03.151585 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5705 23:42:03.154656 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5706 23:42:03.154739 == TX Byte 1 ==
5707 23:42:03.161918 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5708 23:42:03.165002 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5709 23:42:03.165101
5710 23:42:03.165183 [DATLAT]
5711 23:42:03.168139 Freq=933, CH1 RK0
5712 23:42:03.168222
5713 23:42:03.168305 DATLAT Default: 0xd
5714 23:42:03.171985 0, 0xFFFF, sum = 0
5715 23:42:03.172144 1, 0xFFFF, sum = 0
5716 23:42:03.175345 2, 0xFFFF, sum = 0
5717 23:42:03.175419 3, 0xFFFF, sum = 0
5718 23:42:03.178143 4, 0xFFFF, sum = 0
5719 23:42:03.178223 5, 0xFFFF, sum = 0
5720 23:42:03.181846 6, 0xFFFF, sum = 0
5721 23:42:03.181926 7, 0xFFFF, sum = 0
5722 23:42:03.185061 8, 0xFFFF, sum = 0
5723 23:42:03.185141 9, 0xFFFF, sum = 0
5724 23:42:03.188333 10, 0x0, sum = 1
5725 23:42:03.188413 11, 0x0, sum = 2
5726 23:42:03.192069 12, 0x0, sum = 3
5727 23:42:03.192156 13, 0x0, sum = 4
5728 23:42:03.195002 best_step = 11
5729 23:42:03.195080
5730 23:42:03.195141 ==
5731 23:42:03.198201 Dram Type= 6, Freq= 0, CH_1, rank 0
5732 23:42:03.201786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5733 23:42:03.201866 ==
5734 23:42:03.205441 RX Vref Scan: 1
5735 23:42:03.205548
5736 23:42:03.205640 RX Vref 0 -> 0, step: 1
5737 23:42:03.205726
5738 23:42:03.208655 RX Delay -61 -> 252, step: 4
5739 23:42:03.208734
5740 23:42:03.211854 Set Vref, RX VrefLevel [Byte0]: 58
5741 23:42:03.215185 [Byte1]: 52
5742 23:42:03.218776
5743 23:42:03.218875 Final RX Vref Byte 0 = 58 to rank0
5744 23:42:03.221898 Final RX Vref Byte 1 = 52 to rank0
5745 23:42:03.226052 Final RX Vref Byte 0 = 58 to rank1
5746 23:42:03.228550 Final RX Vref Byte 1 = 52 to rank1==
5747 23:42:03.232079 Dram Type= 6, Freq= 0, CH_1, rank 0
5748 23:42:03.238605 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 23:42:03.238684 ==
5750 23:42:03.238748 DQS Delay:
5751 23:42:03.238806 DQS0 = 0, DQS1 = 0
5752 23:42:03.241941 DQM Delay:
5753 23:42:03.242020 DQM0 = 97, DQM1 = 90
5754 23:42:03.245752 DQ Delay:
5755 23:42:03.249070 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =96
5756 23:42:03.252235 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5757 23:42:03.255656 DQ8 =78, DQ9 =78, DQ10 =94, DQ11 =88
5758 23:42:03.259115 DQ12 =98, DQ13 =98, DQ14 =96, DQ15 =96
5759 23:42:03.259187
5760 23:42:03.259247
5761 23:42:03.265768 [DQSOSCAuto] RK0, (LSB)MR18= 0x19f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 413 ps
5762 23:42:03.269105 CH1 RK0: MR19=504, MR18=19F6
5763 23:42:03.275267 CH1_RK0: MR19=0x504, MR18=0x19F6, DQSOSC=413, MR23=63, INC=63, DEC=42
5764 23:42:03.275348
5765 23:42:03.278586 ----->DramcWriteLeveling(PI) begin...
5766 23:42:03.278667 ==
5767 23:42:03.282079 Dram Type= 6, Freq= 0, CH_1, rank 1
5768 23:42:03.285299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 23:42:03.285378 ==
5770 23:42:03.289124 Write leveling (Byte 0): 27 => 27
5771 23:42:03.292581 Write leveling (Byte 1): 27 => 27
5772 23:42:03.295396 DramcWriteLeveling(PI) end<-----
5773 23:42:03.295516
5774 23:42:03.295619 ==
5775 23:42:03.298769 Dram Type= 6, Freq= 0, CH_1, rank 1
5776 23:42:03.301937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 23:42:03.302017 ==
5778 23:42:03.305314 [Gating] SW mode calibration
5779 23:42:03.312029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5780 23:42:03.318945 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5781 23:42:03.322138 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 23:42:03.325332 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5783 23:42:03.331848 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 23:42:03.335174 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5785 23:42:03.338410 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5786 23:42:03.345719 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5787 23:42:03.348389 0 14 24 | B1->B0 | 3131 2e2e | 1 0 | (1 0) (0 0)
5788 23:42:03.352351 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5789 23:42:03.358803 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 23:42:03.361927 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 23:42:03.365534 0 15 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5792 23:42:03.371843 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5793 23:42:03.375119 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5794 23:42:03.378725 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5795 23:42:03.385273 0 15 24 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
5796 23:42:03.388651 0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5797 23:42:03.391820 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 23:42:03.399047 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 23:42:03.401872 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 23:42:03.405164 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5801 23:42:03.411840 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5802 23:42:03.415592 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5803 23:42:03.418854 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5804 23:42:03.422137 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5805 23:42:03.429212 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5806 23:42:03.432146 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 23:42:03.435773 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 23:42:03.442424 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 23:42:03.445721 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 23:42:03.449098 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 23:42:03.455565 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 23:42:03.459081 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 23:42:03.462480 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 23:42:03.469006 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 23:42:03.472877 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 23:42:03.476087 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5817 23:42:03.479423 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5818 23:42:03.485949 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 23:42:03.489496 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5820 23:42:03.492526 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5821 23:42:03.496178 Total UI for P1: 0, mck2ui 16
5822 23:42:03.499425 best dqsien dly found for B0: ( 1, 2, 24)
5823 23:42:03.506023 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 23:42:03.506099 Total UI for P1: 0, mck2ui 16
5825 23:42:03.512445 best dqsien dly found for B1: ( 1, 2, 26)
5826 23:42:03.515604 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5827 23:42:03.518993 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5828 23:42:03.519072
5829 23:42:03.522682 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5830 23:42:03.525784 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5831 23:42:03.529257 [Gating] SW calibration Done
5832 23:42:03.529336 ==
5833 23:42:03.532441 Dram Type= 6, Freq= 0, CH_1, rank 1
5834 23:42:03.535890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5835 23:42:03.535971 ==
5836 23:42:03.538964 RX Vref Scan: 0
5837 23:42:03.539043
5838 23:42:03.539105 RX Vref 0 -> 0, step: 1
5839 23:42:03.539163
5840 23:42:03.542342 RX Delay -80 -> 252, step: 8
5841 23:42:03.545805 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5842 23:42:03.552549 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5843 23:42:03.556122 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5844 23:42:03.559130 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5845 23:42:03.562307 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5846 23:42:03.566534 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5847 23:42:03.569344 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5848 23:42:03.572675 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5849 23:42:03.579098 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5850 23:42:03.582464 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5851 23:42:03.586219 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5852 23:42:03.589787 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5853 23:42:03.592436 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5854 23:42:03.599255 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5855 23:42:03.602747 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5856 23:42:03.606121 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5857 23:42:03.606217 ==
5858 23:42:03.609687 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 23:42:03.613563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 23:42:03.613644 ==
5861 23:42:03.616123 DQS Delay:
5862 23:42:03.616211 DQS0 = 0, DQS1 = 0
5863 23:42:03.616274 DQM Delay:
5864 23:42:03.619416 DQM0 = 94, DQM1 = 89
5865 23:42:03.619495 DQ Delay:
5866 23:42:03.622628 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5867 23:42:03.626328 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5868 23:42:03.629542 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5869 23:42:03.633000 DQ12 =95, DQ13 =103, DQ14 =95, DQ15 =95
5870 23:42:03.633094
5871 23:42:03.633157
5872 23:42:03.633215 ==
5873 23:42:03.636255 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 23:42:03.642915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 23:42:03.642996 ==
5876 23:42:03.643059
5877 23:42:03.643117
5878 23:42:03.643173 TX Vref Scan disable
5879 23:42:03.646298 == TX Byte 0 ==
5880 23:42:03.649638 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5881 23:42:03.653103 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5882 23:42:03.656182 == TX Byte 1 ==
5883 23:42:03.659585 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5884 23:42:03.663028 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5885 23:42:03.666491 ==
5886 23:42:03.669858 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 23:42:03.673400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 23:42:03.673483 ==
5889 23:42:03.673565
5890 23:42:03.673643
5891 23:42:03.676215 TX Vref Scan disable
5892 23:42:03.676297 == TX Byte 0 ==
5893 23:42:03.682977 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5894 23:42:03.686319 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5895 23:42:03.686402 == TX Byte 1 ==
5896 23:42:03.692699 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5897 23:42:03.695998 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5898 23:42:03.696080
5899 23:42:03.696162 [DATLAT]
5900 23:42:03.699448 Freq=933, CH1 RK1
5901 23:42:03.699531
5902 23:42:03.699614 DATLAT Default: 0xb
5903 23:42:03.703078 0, 0xFFFF, sum = 0
5904 23:42:03.703161 1, 0xFFFF, sum = 0
5905 23:42:03.706464 2, 0xFFFF, sum = 0
5906 23:42:03.706560 3, 0xFFFF, sum = 0
5907 23:42:03.709815 4, 0xFFFF, sum = 0
5908 23:42:03.709898 5, 0xFFFF, sum = 0
5909 23:42:03.712889 6, 0xFFFF, sum = 0
5910 23:42:03.713035 7, 0xFFFF, sum = 0
5911 23:42:03.716308 8, 0xFFFF, sum = 0
5912 23:42:03.716410 9, 0xFFFF, sum = 0
5913 23:42:03.719329 10, 0x0, sum = 1
5914 23:42:03.719412 11, 0x0, sum = 2
5915 23:42:03.722894 12, 0x0, sum = 3
5916 23:42:03.722977 13, 0x0, sum = 4
5917 23:42:03.726251 best_step = 11
5918 23:42:03.726333
5919 23:42:03.726416 ==
5920 23:42:03.729777 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 23:42:03.732868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 23:42:03.732950 ==
5923 23:42:03.736365 RX Vref Scan: 0
5924 23:42:03.736447
5925 23:42:03.736529 RX Vref 0 -> 0, step: 1
5926 23:42:03.736607
5927 23:42:03.739613 RX Delay -61 -> 252, step: 4
5928 23:42:03.746764 iDelay=199, Bit 0, Center 98 (7 ~ 190) 184
5929 23:42:03.750284 iDelay=199, Bit 1, Center 90 (-1 ~ 182) 184
5930 23:42:03.753636 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5931 23:42:03.756695 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5932 23:42:03.760100 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5933 23:42:03.763617 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5934 23:42:03.769912 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5935 23:42:03.773458 iDelay=199, Bit 7, Center 90 (3 ~ 178) 176
5936 23:42:03.776678 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5937 23:42:03.779881 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5938 23:42:03.783365 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5939 23:42:03.786539 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5940 23:42:03.793616 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5941 23:42:03.796525 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5942 23:42:03.800208 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5943 23:42:03.803419 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5944 23:42:03.803501 ==
5945 23:42:03.806614 Dram Type= 6, Freq= 0, CH_1, rank 1
5946 23:42:03.813160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5947 23:42:03.813243 ==
5948 23:42:03.813327 DQS Delay:
5949 23:42:03.817003 DQS0 = 0, DQS1 = 0
5950 23:42:03.817099 DQM Delay:
5951 23:42:03.817181 DQM0 = 95, DQM1 = 91
5952 23:42:03.820245 DQ Delay:
5953 23:42:03.823427 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5954 23:42:03.827292 DQ4 =96, DQ5 =106, DQ6 =102, DQ7 =90
5955 23:42:03.830370 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =82
5956 23:42:03.833635 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
5957 23:42:03.833718
5958 23:42:03.833800
5959 23:42:03.840471 [DQSOSCAuto] RK1, (LSB)MR18= 0xe17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5960 23:42:03.843576 CH1 RK1: MR19=505, MR18=E17
5961 23:42:03.849971 CH1_RK1: MR19=0x505, MR18=0xE17, DQSOSC=414, MR23=63, INC=63, DEC=42
5962 23:42:03.853104 [RxdqsGatingPostProcess] freq 933
5963 23:42:03.856492 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5964 23:42:03.860250 best DQS0 dly(2T, 0.5T) = (0, 10)
5965 23:42:03.863803 best DQS1 dly(2T, 0.5T) = (0, 10)
5966 23:42:03.866633 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5967 23:42:03.870244 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5968 23:42:03.873094 best DQS0 dly(2T, 0.5T) = (0, 10)
5969 23:42:03.876357 best DQS1 dly(2T, 0.5T) = (0, 10)
5970 23:42:03.879962 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5971 23:42:03.883202 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5972 23:42:03.886778 Pre-setting of DQS Precalculation
5973 23:42:03.890129 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5974 23:42:03.896758 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5975 23:42:03.906647 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5976 23:42:03.906727
5977 23:42:03.906790
5978 23:42:03.910146 [Calibration Summary] 1866 Mbps
5979 23:42:03.910226 CH 0, Rank 0
5980 23:42:03.913357 SW Impedance : PASS
5981 23:42:03.913437 DUTY Scan : NO K
5982 23:42:03.916682 ZQ Calibration : PASS
5983 23:42:03.919845 Jitter Meter : NO K
5984 23:42:03.919925 CBT Training : PASS
5985 23:42:03.923651 Write leveling : PASS
5986 23:42:03.923734 RX DQS gating : PASS
5987 23:42:03.926912 RX DQ/DQS(RDDQC) : PASS
5988 23:42:03.930159 TX DQ/DQS : PASS
5989 23:42:03.930229 RX DATLAT : PASS
5990 23:42:03.933809 RX DQ/DQS(Engine): PASS
5991 23:42:03.936879 TX OE : NO K
5992 23:42:03.936980 All Pass.
5993 23:42:03.937059
5994 23:42:03.937117 CH 0, Rank 1
5995 23:42:03.940663 SW Impedance : PASS
5996 23:42:03.944292 DUTY Scan : NO K
5997 23:42:03.944398 ZQ Calibration : PASS
5998 23:42:03.946875 Jitter Meter : NO K
5999 23:42:03.950604 CBT Training : PASS
6000 23:42:03.950680 Write leveling : PASS
6001 23:42:03.953857 RX DQS gating : PASS
6002 23:42:03.953954 RX DQ/DQS(RDDQC) : PASS
6003 23:42:03.956945 TX DQ/DQS : PASS
6004 23:42:03.960284 RX DATLAT : PASS
6005 23:42:03.960379 RX DQ/DQS(Engine): PASS
6006 23:42:03.963981 TX OE : NO K
6007 23:42:03.964063 All Pass.
6008 23:42:03.964126
6009 23:42:03.966700 CH 1, Rank 0
6010 23:42:03.966777 SW Impedance : PASS
6011 23:42:03.970148 DUTY Scan : NO K
6012 23:42:03.973663 ZQ Calibration : PASS
6013 23:42:03.973739 Jitter Meter : NO K
6014 23:42:03.977318 CBT Training : PASS
6015 23:42:03.980307 Write leveling : PASS
6016 23:42:03.980394 RX DQS gating : PASS
6017 23:42:03.983452 RX DQ/DQS(RDDQC) : PASS
6018 23:42:03.987319 TX DQ/DQS : PASS
6019 23:42:03.987400 RX DATLAT : PASS
6020 23:42:03.990184 RX DQ/DQS(Engine): PASS
6021 23:42:03.993661 TX OE : NO K
6022 23:42:03.993743 All Pass.
6023 23:42:03.993807
6024 23:42:03.993866 CH 1, Rank 1
6025 23:42:03.996689 SW Impedance : PASS
6026 23:42:04.000440 DUTY Scan : NO K
6027 23:42:04.000521 ZQ Calibration : PASS
6028 23:42:04.004097 Jitter Meter : NO K
6029 23:42:04.004170 CBT Training : PASS
6030 23:42:04.006780 Write leveling : PASS
6031 23:42:04.010407 RX DQS gating : PASS
6032 23:42:04.010487 RX DQ/DQS(RDDQC) : PASS
6033 23:42:04.013712 TX DQ/DQS : PASS
6034 23:42:04.017092 RX DATLAT : PASS
6035 23:42:04.017199 RX DQ/DQS(Engine): PASS
6036 23:42:04.020400 TX OE : NO K
6037 23:42:04.020490 All Pass.
6038 23:42:04.020555
6039 23:42:04.023626 DramC Write-DBI off
6040 23:42:04.027328 PER_BANK_REFRESH: Hybrid Mode
6041 23:42:04.027432 TX_TRACKING: ON
6042 23:42:04.037254 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6043 23:42:04.040224 [FAST_K] Save calibration result to emmc
6044 23:42:04.043770 dramc_set_vcore_voltage set vcore to 650000
6045 23:42:04.046983 Read voltage for 400, 6
6046 23:42:04.047061 Vio18 = 0
6047 23:42:04.047124 Vcore = 650000
6048 23:42:04.050714 Vdram = 0
6049 23:42:04.050792 Vddq = 0
6050 23:42:04.050853 Vmddr = 0
6051 23:42:04.056717 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6052 23:42:04.060168 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6053 23:42:04.063569 MEM_TYPE=3, freq_sel=20
6054 23:42:04.066647 sv_algorithm_assistance_LP4_800
6055 23:42:04.070200 ============ PULL DRAM RESETB DOWN ============
6056 23:42:04.073612 ========== PULL DRAM RESETB DOWN end =========
6057 23:42:04.080168 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6058 23:42:04.083732 ===================================
6059 23:42:04.083811 LPDDR4 DRAM CONFIGURATION
6060 23:42:04.087155 ===================================
6061 23:42:04.089952 EX_ROW_EN[0] = 0x0
6062 23:42:04.093929 EX_ROW_EN[1] = 0x0
6063 23:42:04.094008 LP4Y_EN = 0x0
6064 23:42:04.097361 WORK_FSP = 0x0
6065 23:42:04.097440 WL = 0x2
6066 23:42:04.100561 RL = 0x2
6067 23:42:04.100639 BL = 0x2
6068 23:42:04.103422 RPST = 0x0
6069 23:42:04.103500 RD_PRE = 0x0
6070 23:42:04.106886 WR_PRE = 0x1
6071 23:42:04.106965 WR_PST = 0x0
6072 23:42:04.110430 DBI_WR = 0x0
6073 23:42:04.110509 DBI_RD = 0x0
6074 23:42:04.113519 OTF = 0x1
6075 23:42:04.116769 ===================================
6076 23:42:04.120296 ===================================
6077 23:42:04.120366 ANA top config
6078 23:42:04.123453 ===================================
6079 23:42:04.128039 DLL_ASYNC_EN = 0
6080 23:42:04.130069 ALL_SLAVE_EN = 1
6081 23:42:04.133713 NEW_RANK_MODE = 1
6082 23:42:04.133819 DLL_IDLE_MODE = 1
6083 23:42:04.136776 LP45_APHY_COMB_EN = 1
6084 23:42:04.140401 TX_ODT_DIS = 1
6085 23:42:04.143820 NEW_8X_MODE = 1
6086 23:42:04.146588 ===================================
6087 23:42:04.150226 ===================================
6088 23:42:04.153530 data_rate = 800
6089 23:42:04.153633 CKR = 1
6090 23:42:04.156706 DQ_P2S_RATIO = 4
6091 23:42:04.160060 ===================================
6092 23:42:04.163255 CA_P2S_RATIO = 4
6093 23:42:04.166511 DQ_CA_OPEN = 0
6094 23:42:04.170095 DQ_SEMI_OPEN = 1
6095 23:42:04.170191 CA_SEMI_OPEN = 1
6096 23:42:04.173585 CA_FULL_RATE = 0
6097 23:42:04.176870 DQ_CKDIV4_EN = 0
6098 23:42:04.180187 CA_CKDIV4_EN = 1
6099 23:42:04.183586 CA_PREDIV_EN = 0
6100 23:42:04.187041 PH8_DLY = 0
6101 23:42:04.187153 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6102 23:42:04.190625 DQ_AAMCK_DIV = 0
6103 23:42:04.193445 CA_AAMCK_DIV = 0
6104 23:42:04.197322 CA_ADMCK_DIV = 4
6105 23:42:04.199969 DQ_TRACK_CA_EN = 0
6106 23:42:04.204033 CA_PICK = 800
6107 23:42:04.204113 CA_MCKIO = 400
6108 23:42:04.206702 MCKIO_SEMI = 400
6109 23:42:04.210011 PLL_FREQ = 3016
6110 23:42:04.213412 DQ_UI_PI_RATIO = 32
6111 23:42:04.216859 CA_UI_PI_RATIO = 32
6112 23:42:04.219959 ===================================
6113 23:42:04.223501 ===================================
6114 23:42:04.227068 memory_type:LPDDR4
6115 23:42:04.227184 GP_NUM : 10
6116 23:42:04.230506 SRAM_EN : 1
6117 23:42:04.230588 MD32_EN : 0
6118 23:42:04.233569 ===================================
6119 23:42:04.237568 [ANA_INIT] >>>>>>>>>>>>>>
6120 23:42:04.240496 <<<<<< [CONFIGURE PHASE]: ANA_TX
6121 23:42:04.243557 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6122 23:42:04.246981 ===================================
6123 23:42:04.250341 data_rate = 800,PCW = 0X7400
6124 23:42:04.254298 ===================================
6125 23:42:04.256839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6126 23:42:04.263772 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6127 23:42:04.273958 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6128 23:42:04.276824 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6129 23:42:04.280524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6130 23:42:04.283469 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6131 23:42:04.286732 [ANA_INIT] flow start
6132 23:42:04.290631 [ANA_INIT] PLL >>>>>>>>
6133 23:42:04.290705 [ANA_INIT] PLL <<<<<<<<
6134 23:42:04.293279 [ANA_INIT] MIDPI >>>>>>>>
6135 23:42:04.297057 [ANA_INIT] MIDPI <<<<<<<<
6136 23:42:04.297128 [ANA_INIT] DLL >>>>>>>>
6137 23:42:04.299963 [ANA_INIT] flow end
6138 23:42:04.303292 ============ LP4 DIFF to SE enter ============
6139 23:42:04.309875 ============ LP4 DIFF to SE exit ============
6140 23:42:04.309984 [ANA_INIT] <<<<<<<<<<<<<
6141 23:42:04.313258 [Flow] Enable top DCM control >>>>>
6142 23:42:04.316655 [Flow] Enable top DCM control <<<<<
6143 23:42:04.320282 Enable DLL master slave shuffle
6144 23:42:04.327242 ==============================================================
6145 23:42:04.327325 Gating Mode config
6146 23:42:04.333357 ==============================================================
6147 23:42:04.336789 Config description:
6148 23:42:04.343254 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6149 23:42:04.350121 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6150 23:42:04.356835 SELPH_MODE 0: By rank 1: By Phase
6151 23:42:04.363602 ==============================================================
6152 23:42:04.363686 GAT_TRACK_EN = 0
6153 23:42:04.367039 RX_GATING_MODE = 2
6154 23:42:04.370046 RX_GATING_TRACK_MODE = 2
6155 23:42:04.373323 SELPH_MODE = 1
6156 23:42:04.376816 PICG_EARLY_EN = 1
6157 23:42:04.380050 VALID_LAT_VALUE = 1
6158 23:42:04.387480 ==============================================================
6159 23:42:04.390156 Enter into Gating configuration >>>>
6160 23:42:04.393428 Exit from Gating configuration <<<<
6161 23:42:04.396991 Enter into DVFS_PRE_config >>>>>
6162 23:42:04.406530 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6163 23:42:04.409686 Exit from DVFS_PRE_config <<<<<
6164 23:42:04.413742 Enter into PICG configuration >>>>
6165 23:42:04.416434 Exit from PICG configuration <<<<
6166 23:42:04.419949 [RX_INPUT] configuration >>>>>
6167 23:42:04.420032 [RX_INPUT] configuration <<<<<
6168 23:42:04.426878 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6169 23:42:04.433503 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6170 23:42:04.436775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6171 23:42:04.443490 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6172 23:42:04.450348 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6173 23:42:04.456673 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6174 23:42:04.460102 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6175 23:42:04.463476 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6176 23:42:04.466806 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6177 23:42:04.473343 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6178 23:42:04.477477 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6179 23:42:04.480333 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6180 23:42:04.483331 ===================================
6181 23:42:04.487110 LPDDR4 DRAM CONFIGURATION
6182 23:42:04.490412 ===================================
6183 23:42:04.493680 EX_ROW_EN[0] = 0x0
6184 23:42:04.493762 EX_ROW_EN[1] = 0x0
6185 23:42:04.497106 LP4Y_EN = 0x0
6186 23:42:04.497189 WORK_FSP = 0x0
6187 23:42:04.500329 WL = 0x2
6188 23:42:04.500412 RL = 0x2
6189 23:42:04.503181 BL = 0x2
6190 23:42:04.503252 RPST = 0x0
6191 23:42:04.506501 RD_PRE = 0x0
6192 23:42:04.506584 WR_PRE = 0x1
6193 23:42:04.510275 WR_PST = 0x0
6194 23:42:04.510356 DBI_WR = 0x0
6195 23:42:04.513493 DBI_RD = 0x0
6196 23:42:04.513575 OTF = 0x1
6197 23:42:04.516922 ===================================
6198 23:42:04.523530 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6199 23:42:04.526662 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6200 23:42:04.529952 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6201 23:42:04.533803 ===================================
6202 23:42:04.537193 LPDDR4 DRAM CONFIGURATION
6203 23:42:04.540224 ===================================
6204 23:42:04.543347 EX_ROW_EN[0] = 0x10
6205 23:42:04.543430 EX_ROW_EN[1] = 0x0
6206 23:42:04.546973 LP4Y_EN = 0x0
6207 23:42:04.547055 WORK_FSP = 0x0
6208 23:42:04.550429 WL = 0x2
6209 23:42:04.550511 RL = 0x2
6210 23:42:04.553311 BL = 0x2
6211 23:42:04.553394 RPST = 0x0
6212 23:42:04.556956 RD_PRE = 0x0
6213 23:42:04.557055 WR_PRE = 0x1
6214 23:42:04.560025 WR_PST = 0x0
6215 23:42:04.560106 DBI_WR = 0x0
6216 23:42:04.563669 DBI_RD = 0x0
6217 23:42:04.563750 OTF = 0x1
6218 23:42:04.566740 ===================================
6219 23:42:04.573669 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6220 23:42:04.577558 nWR fixed to 30
6221 23:42:04.581184 [ModeRegInit_LP4] CH0 RK0
6222 23:42:04.581266 [ModeRegInit_LP4] CH0 RK1
6223 23:42:04.584267 [ModeRegInit_LP4] CH1 RK0
6224 23:42:04.588009 [ModeRegInit_LP4] CH1 RK1
6225 23:42:04.588089 match AC timing 19
6226 23:42:04.594502 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6227 23:42:04.597785 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6228 23:42:04.601100 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6229 23:42:04.607905 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6230 23:42:04.611268 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6231 23:42:04.611349 ==
6232 23:42:04.614706 Dram Type= 6, Freq= 0, CH_0, rank 0
6233 23:42:04.618141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6234 23:42:04.618224 ==
6235 23:42:04.624767 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6236 23:42:04.631598 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6237 23:42:04.634512 [CA 0] Center 36 (8~64) winsize 57
6238 23:42:04.637848 [CA 1] Center 36 (8~64) winsize 57
6239 23:42:04.637930 [CA 2] Center 36 (8~64) winsize 57
6240 23:42:04.641331 [CA 3] Center 36 (8~64) winsize 57
6241 23:42:04.644641 [CA 4] Center 36 (8~64) winsize 57
6242 23:42:04.647854 [CA 5] Center 36 (8~64) winsize 57
6243 23:42:04.647953
6244 23:42:04.651193 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6245 23:42:04.654251
6246 23:42:04.658036 [CATrainingPosCal] consider 1 rank data
6247 23:42:04.658122 u2DelayCellTimex100 = 270/100 ps
6248 23:42:04.664274 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 23:42:04.667508 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 23:42:04.671005 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 23:42:04.674266 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 23:42:04.677665 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 23:42:04.681120 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 23:42:04.681200
6255 23:42:04.685336 CA PerBit enable=1, Macro0, CA PI delay=36
6256 23:42:04.685418
6257 23:42:04.687953 [CBTSetCACLKResult] CA Dly = 36
6258 23:42:04.692066 CS Dly: 1 (0~32)
6259 23:42:04.692146 ==
6260 23:42:04.694811 Dram Type= 6, Freq= 0, CH_0, rank 1
6261 23:42:04.697907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 23:42:04.697989 ==
6263 23:42:04.701254 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6264 23:42:04.708254 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6265 23:42:04.710997 [CA 0] Center 36 (8~64) winsize 57
6266 23:42:04.714383 [CA 1] Center 36 (8~64) winsize 57
6267 23:42:04.718017 [CA 2] Center 36 (8~64) winsize 57
6268 23:42:04.721113 [CA 3] Center 36 (8~64) winsize 57
6269 23:42:04.724534 [CA 4] Center 36 (8~64) winsize 57
6270 23:42:04.728175 [CA 5] Center 36 (8~64) winsize 57
6271 23:42:04.728255
6272 23:42:04.731383 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6273 23:42:04.731464
6274 23:42:04.734629 [CATrainingPosCal] consider 2 rank data
6275 23:42:04.738110 u2DelayCellTimex100 = 270/100 ps
6276 23:42:04.741482 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 23:42:04.744826 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 23:42:04.748053 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 23:42:04.751527 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 23:42:04.754694 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 23:42:04.758286 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 23:42:04.761478
6283 23:42:04.764510 CA PerBit enable=1, Macro0, CA PI delay=36
6284 23:42:04.764589
6285 23:42:04.767849 [CBTSetCACLKResult] CA Dly = 36
6286 23:42:04.767930 CS Dly: 1 (0~32)
6287 23:42:04.767993
6288 23:42:04.771148 ----->DramcWriteLeveling(PI) begin...
6289 23:42:04.771257 ==
6290 23:42:04.775152 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 23:42:04.778129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 23:42:04.780956 ==
6293 23:42:04.781049 Write leveling (Byte 0): 40 => 8
6294 23:42:04.784738 Write leveling (Byte 1): 32 => 0
6295 23:42:04.787836 DramcWriteLeveling(PI) end<-----
6296 23:42:04.787943
6297 23:42:04.788036 ==
6298 23:42:04.791066 Dram Type= 6, Freq= 0, CH_0, rank 0
6299 23:42:04.797700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6300 23:42:04.797784 ==
6301 23:42:04.797848 [Gating] SW mode calibration
6302 23:42:04.808054 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6303 23:42:04.811172 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6304 23:42:04.814689 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6305 23:42:04.821443 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6306 23:42:04.824631 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 23:42:04.827665 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6308 23:42:04.834313 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 23:42:04.837580 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6310 23:42:04.840911 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6311 23:42:04.847932 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6312 23:42:04.851385 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6313 23:42:04.854375 Total UI for P1: 0, mck2ui 16
6314 23:42:04.858178 best dqsien dly found for B0: ( 0, 14, 24)
6315 23:42:04.861207 Total UI for P1: 0, mck2ui 16
6316 23:42:04.864434 best dqsien dly found for B1: ( 0, 14, 24)
6317 23:42:04.867721 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6318 23:42:04.871365 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6319 23:42:04.871451
6320 23:42:04.874538 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6321 23:42:04.877877 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6322 23:42:04.881413 [Gating] SW calibration Done
6323 23:42:04.881488 ==
6324 23:42:04.884140 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 23:42:04.888338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 23:42:04.891306 ==
6327 23:42:04.891406 RX Vref Scan: 0
6328 23:42:04.891493
6329 23:42:04.894751 RX Vref 0 -> 0, step: 1
6330 23:42:04.894822
6331 23:42:04.897687 RX Delay -410 -> 252, step: 16
6332 23:42:04.900930 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6333 23:42:04.904019 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6334 23:42:04.907727 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6335 23:42:04.914030 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6336 23:42:04.918008 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6337 23:42:04.920713 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6338 23:42:04.924117 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6339 23:42:04.931129 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6340 23:42:04.934827 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6341 23:42:04.937832 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6342 23:42:04.941359 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6343 23:42:04.947789 iDelay=230, Bit 11, Center -43 (-282 ~ 197) 480
6344 23:42:04.951183 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6345 23:42:04.954978 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6346 23:42:04.957524 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6347 23:42:04.964333 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6348 23:42:04.964414 ==
6349 23:42:04.968188 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 23:42:04.971405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 23:42:04.971530 ==
6352 23:42:04.971594 DQS Delay:
6353 23:42:04.974527 DQS0 = 35, DQS1 = 51
6354 23:42:04.974640 DQM Delay:
6355 23:42:04.978241 DQM0 = 8, DQM1 = 11
6356 23:42:04.978320 DQ Delay:
6357 23:42:04.981185 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6358 23:42:04.984493 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6359 23:42:04.987749 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6360 23:42:04.991178 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6361 23:42:04.991259
6362 23:42:04.991323
6363 23:42:04.991383 ==
6364 23:42:04.994761 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 23:42:04.997815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 23:42:04.997897 ==
6367 23:42:04.997960
6368 23:42:04.998022
6369 23:42:05.000990 TX Vref Scan disable
6370 23:42:05.001073 == TX Byte 0 ==
6371 23:42:05.007864 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6372 23:42:05.011403 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6373 23:42:05.011486 == TX Byte 1 ==
6374 23:42:05.018244 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6375 23:42:05.021279 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6376 23:42:05.021378 ==
6377 23:42:05.024383 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 23:42:05.028002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 23:42:05.028075 ==
6380 23:42:05.028138
6381 23:42:05.028195
6382 23:42:05.031192 TX Vref Scan disable
6383 23:42:05.034489 == TX Byte 0 ==
6384 23:42:05.038122 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 23:42:05.041357 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 23:42:05.041440 == TX Byte 1 ==
6387 23:42:05.047928 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6388 23:42:05.051123 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6389 23:42:05.051203
6390 23:42:05.051284 [DATLAT]
6391 23:42:05.054429 Freq=400, CH0 RK0
6392 23:42:05.054503
6393 23:42:05.054582 DATLAT Default: 0xf
6394 23:42:05.057863 0, 0xFFFF, sum = 0
6395 23:42:05.057949 1, 0xFFFF, sum = 0
6396 23:42:05.061372 2, 0xFFFF, sum = 0
6397 23:42:05.061458 3, 0xFFFF, sum = 0
6398 23:42:05.064878 4, 0xFFFF, sum = 0
6399 23:42:05.065002 5, 0xFFFF, sum = 0
6400 23:42:05.068176 6, 0xFFFF, sum = 0
6401 23:42:05.071703 7, 0xFFFF, sum = 0
6402 23:42:05.071811 8, 0xFFFF, sum = 0
6403 23:42:05.074698 9, 0xFFFF, sum = 0
6404 23:42:05.074816 10, 0xFFFF, sum = 0
6405 23:42:05.077729 11, 0xFFFF, sum = 0
6406 23:42:05.077810 12, 0xFFFF, sum = 0
6407 23:42:05.081297 13, 0x0, sum = 1
6408 23:42:05.081368 14, 0x0, sum = 2
6409 23:42:05.084498 15, 0x0, sum = 3
6410 23:42:05.084569 16, 0x0, sum = 4
6411 23:42:05.084630 best_step = 14
6412 23:42:05.087971
6413 23:42:05.088043 ==
6414 23:42:05.091055 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 23:42:05.094436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 23:42:05.094509 ==
6417 23:42:05.094569 RX Vref Scan: 1
6418 23:42:05.094627
6419 23:42:05.097973 RX Vref 0 -> 0, step: 1
6420 23:42:05.098060
6421 23:42:05.101300 RX Delay -343 -> 252, step: 8
6422 23:42:05.101381
6423 23:42:05.104366 Set Vref, RX VrefLevel [Byte0]: 51
6424 23:42:05.108061 [Byte1]: 52
6425 23:42:05.111595
6426 23:42:05.111675 Final RX Vref Byte 0 = 51 to rank0
6427 23:42:05.114906 Final RX Vref Byte 1 = 52 to rank0
6428 23:42:05.118089 Final RX Vref Byte 0 = 51 to rank1
6429 23:42:05.121445 Final RX Vref Byte 1 = 52 to rank1==
6430 23:42:05.125173 Dram Type= 6, Freq= 0, CH_0, rank 0
6431 23:42:05.131715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6432 23:42:05.131810 ==
6433 23:42:05.131875 DQS Delay:
6434 23:42:05.131936 DQS0 = 44, DQS1 = 60
6435 23:42:05.134873 DQM Delay:
6436 23:42:05.134954 DQM0 = 11, DQM1 = 15
6437 23:42:05.138528 DQ Delay:
6438 23:42:05.141973 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =12
6439 23:42:05.142054 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6440 23:42:05.144831 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =12
6441 23:42:05.148400 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6442 23:42:05.148481
6443 23:42:05.151466
6444 23:42:05.158567 [DQSOSCAuto] RK0, (LSB)MR18= 0x8c59, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6445 23:42:05.161777 CH0 RK0: MR19=C0C, MR18=8C59
6446 23:42:05.168667 CH0_RK0: MR19=0xC0C, MR18=0x8C59, DQSOSC=392, MR23=63, INC=384, DEC=256
6447 23:42:05.168750 ==
6448 23:42:05.171716 Dram Type= 6, Freq= 0, CH_0, rank 1
6449 23:42:05.175317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 23:42:05.175399 ==
6451 23:42:05.178780 [Gating] SW mode calibration
6452 23:42:05.185253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6453 23:42:05.188762 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6454 23:42:05.195443 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6455 23:42:05.198412 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6456 23:42:05.202168 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 23:42:05.208171 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6458 23:42:05.211882 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 23:42:05.215141 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6460 23:42:05.222178 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6461 23:42:05.225699 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6462 23:42:05.228768 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6463 23:42:05.231469 Total UI for P1: 0, mck2ui 16
6464 23:42:05.235382 best dqsien dly found for B0: ( 0, 14, 24)
6465 23:42:05.238664 Total UI for P1: 0, mck2ui 16
6466 23:42:05.242109 best dqsien dly found for B1: ( 0, 14, 24)
6467 23:42:05.245279 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6468 23:42:05.248473 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6469 23:42:05.248626
6470 23:42:05.254784 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6471 23:42:05.258235 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6472 23:42:05.261716 [Gating] SW calibration Done
6473 23:42:05.261796 ==
6474 23:42:05.265219 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 23:42:05.268675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 23:42:05.268795 ==
6477 23:42:05.268859 RX Vref Scan: 0
6478 23:42:05.268921
6479 23:42:05.271756 RX Vref 0 -> 0, step: 1
6480 23:42:05.271874
6481 23:42:05.274986 RX Delay -410 -> 252, step: 16
6482 23:42:05.278213 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6483 23:42:05.284838 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6484 23:42:05.287995 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6485 23:42:05.291408 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6486 23:42:05.294716 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6487 23:42:05.301458 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6488 23:42:05.304754 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6489 23:42:05.308473 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6490 23:42:05.311918 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6491 23:42:05.315273 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6492 23:42:05.321549 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6493 23:42:05.324924 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6494 23:42:05.328807 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6495 23:42:05.335170 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6496 23:42:05.338377 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6497 23:42:05.341511 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6498 23:42:05.341591 ==
6499 23:42:05.344786 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 23:42:05.348069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 23:42:05.348150 ==
6502 23:42:05.351454 DQS Delay:
6503 23:42:05.351534 DQS0 = 43, DQS1 = 51
6504 23:42:05.354760 DQM Delay:
6505 23:42:05.354840 DQM0 = 11, DQM1 = 10
6506 23:42:05.354903 DQ Delay:
6507 23:42:05.358315 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6508 23:42:05.361688 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6509 23:42:05.365018 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6510 23:42:05.368146 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6511 23:42:05.368225
6512 23:42:05.368288
6513 23:42:05.368378 ==
6514 23:42:05.371533 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 23:42:05.378278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 23:42:05.378359 ==
6517 23:42:05.378421
6518 23:42:05.378479
6519 23:42:05.378534 TX Vref Scan disable
6520 23:42:05.381388 == TX Byte 0 ==
6521 23:42:05.384915 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6522 23:42:05.388187 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6523 23:42:05.391519 == TX Byte 1 ==
6524 23:42:05.395069 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6525 23:42:05.398057 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6526 23:42:05.398137 ==
6527 23:42:05.401786 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 23:42:05.408196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 23:42:05.408277 ==
6530 23:42:05.408339
6531 23:42:05.408398
6532 23:42:05.408454 TX Vref Scan disable
6533 23:42:05.411844 == TX Byte 0 ==
6534 23:42:05.414926 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6535 23:42:05.417994 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6536 23:42:05.421715 == TX Byte 1 ==
6537 23:42:05.425110 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6538 23:42:05.428014 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6539 23:42:05.428094
6540 23:42:05.431579 [DATLAT]
6541 23:42:05.431659 Freq=400, CH0 RK1
6542 23:42:05.431760
6543 23:42:05.434729 DATLAT Default: 0xe
6544 23:42:05.434823 0, 0xFFFF, sum = 0
6545 23:42:05.438528 1, 0xFFFF, sum = 0
6546 23:42:05.438610 2, 0xFFFF, sum = 0
6547 23:42:05.441763 3, 0xFFFF, sum = 0
6548 23:42:05.441844 4, 0xFFFF, sum = 0
6549 23:42:05.445265 5, 0xFFFF, sum = 0
6550 23:42:05.445346 6, 0xFFFF, sum = 0
6551 23:42:05.448474 7, 0xFFFF, sum = 0
6552 23:42:05.448555 8, 0xFFFF, sum = 0
6553 23:42:05.451490 9, 0xFFFF, sum = 0
6554 23:42:05.451573 10, 0xFFFF, sum = 0
6555 23:42:05.455214 11, 0xFFFF, sum = 0
6556 23:42:05.455297 12, 0xFFFF, sum = 0
6557 23:42:05.458318 13, 0x0, sum = 1
6558 23:42:05.458399 14, 0x0, sum = 2
6559 23:42:05.461801 15, 0x0, sum = 3
6560 23:42:05.461881 16, 0x0, sum = 4
6561 23:42:05.465165 best_step = 14
6562 23:42:05.465245
6563 23:42:05.465325 ==
6564 23:42:05.468441 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 23:42:05.472000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 23:42:05.472103 ==
6567 23:42:05.475312 RX Vref Scan: 0
6568 23:42:05.475413
6569 23:42:05.475521 RX Vref 0 -> 0, step: 1
6570 23:42:05.475603
6571 23:42:05.478079 RX Delay -343 -> 252, step: 8
6572 23:42:05.485801 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6573 23:42:05.489499 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6574 23:42:05.492583 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6575 23:42:05.496302 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6576 23:42:05.502747 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6577 23:42:05.506243 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6578 23:42:05.509598 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6579 23:42:05.512601 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6580 23:42:05.519604 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6581 23:42:05.523343 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6582 23:42:05.526034 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6583 23:42:05.529375 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6584 23:42:05.536258 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6585 23:42:05.539513 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6586 23:42:05.543087 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6587 23:42:05.546350 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6588 23:42:05.549636 ==
6589 23:42:05.549718 Dram Type= 6, Freq= 0, CH_0, rank 1
6590 23:42:05.556373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6591 23:42:05.556455 ==
6592 23:42:05.556520 DQS Delay:
6593 23:42:05.559790 DQS0 = 48, DQS1 = 60
6594 23:42:05.559871 DQM Delay:
6595 23:42:05.563228 DQM0 = 13, DQM1 = 13
6596 23:42:05.563309 DQ Delay:
6597 23:42:05.566506 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6598 23:42:05.569570 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6599 23:42:05.573404 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =4
6600 23:42:05.576761 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6601 23:42:05.576843
6602 23:42:05.576907
6603 23:42:05.582970 [DQSOSCAuto] RK1, (LSB)MR18= 0x9164, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6604 23:42:05.586298 CH0 RK1: MR19=C0C, MR18=9164
6605 23:42:05.593321 CH0_RK1: MR19=0xC0C, MR18=0x9164, DQSOSC=391, MR23=63, INC=386, DEC=257
6606 23:42:05.596181 [RxdqsGatingPostProcess] freq 400
6607 23:42:05.599528 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6608 23:42:05.602968 best DQS0 dly(2T, 0.5T) = (0, 10)
6609 23:42:05.606164 best DQS1 dly(2T, 0.5T) = (0, 10)
6610 23:42:05.609614 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6611 23:42:05.612764 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6612 23:42:05.616186 best DQS0 dly(2T, 0.5T) = (0, 10)
6613 23:42:05.619682 best DQS1 dly(2T, 0.5T) = (0, 10)
6614 23:42:05.623059 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6615 23:42:05.626184 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6616 23:42:05.629887 Pre-setting of DQS Precalculation
6617 23:42:05.633157 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6618 23:42:05.633238 ==
6619 23:42:05.636879 Dram Type= 6, Freq= 0, CH_1, rank 0
6620 23:42:05.642834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 23:42:05.642915 ==
6622 23:42:05.646385 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6623 23:42:05.653426 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6624 23:42:05.656564 [CA 0] Center 36 (8~64) winsize 57
6625 23:42:05.659746 [CA 1] Center 36 (8~64) winsize 57
6626 23:42:05.663390 [CA 2] Center 36 (8~64) winsize 57
6627 23:42:05.666711 [CA 3] Center 36 (8~64) winsize 57
6628 23:42:05.669943 [CA 4] Center 36 (8~64) winsize 57
6629 23:42:05.673207 [CA 5] Center 36 (8~64) winsize 57
6630 23:42:05.673289
6631 23:42:05.676508 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6632 23:42:05.676588
6633 23:42:05.679712 [CATrainingPosCal] consider 1 rank data
6634 23:42:05.683386 u2DelayCellTimex100 = 270/100 ps
6635 23:42:05.686234 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 23:42:05.690107 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 23:42:05.693316 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 23:42:05.696766 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 23:42:05.699620 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 23:42:05.702863 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 23:42:05.702956
6642 23:42:05.710151 CA PerBit enable=1, Macro0, CA PI delay=36
6643 23:42:05.710230
6644 23:42:05.710293 [CBTSetCACLKResult] CA Dly = 36
6645 23:42:05.712943 CS Dly: 1 (0~32)
6646 23:42:05.713066 ==
6647 23:42:05.716799 Dram Type= 6, Freq= 0, CH_1, rank 1
6648 23:42:05.719488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 23:42:05.719575 ==
6650 23:42:05.726436 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6651 23:42:05.733102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6652 23:42:05.736032 [CA 0] Center 36 (8~64) winsize 57
6653 23:42:05.739514 [CA 1] Center 36 (8~64) winsize 57
6654 23:42:05.742915 [CA 2] Center 36 (8~64) winsize 57
6655 23:42:05.742996 [CA 3] Center 36 (8~64) winsize 57
6656 23:42:05.746326 [CA 4] Center 36 (8~64) winsize 57
6657 23:42:05.749799 [CA 5] Center 36 (8~64) winsize 57
6658 23:42:05.749879
6659 23:42:05.753200 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6660 23:42:05.756197
6661 23:42:05.760174 [CATrainingPosCal] consider 2 rank data
6662 23:42:05.760250 u2DelayCellTimex100 = 270/100 ps
6663 23:42:05.766642 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 23:42:05.769661 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 23:42:05.773431 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 23:42:05.776559 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 23:42:05.780127 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 23:42:05.782902 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 23:42:05.783006
6670 23:42:05.786380 CA PerBit enable=1, Macro0, CA PI delay=36
6671 23:42:05.786460
6672 23:42:05.789807 [CBTSetCACLKResult] CA Dly = 36
6673 23:42:05.793412 CS Dly: 1 (0~32)
6674 23:42:05.793483
6675 23:42:05.796669 ----->DramcWriteLeveling(PI) begin...
6676 23:42:05.796740 ==
6677 23:42:05.800045 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 23:42:05.803391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 23:42:05.803471 ==
6680 23:42:05.806848 Write leveling (Byte 0): 40 => 8
6681 23:42:05.809924 Write leveling (Byte 1): 40 => 8
6682 23:42:05.813207 DramcWriteLeveling(PI) end<-----
6683 23:42:05.813286
6684 23:42:05.813349 ==
6685 23:42:05.816694 Dram Type= 6, Freq= 0, CH_1, rank 0
6686 23:42:05.819633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6687 23:42:05.819713 ==
6688 23:42:05.823129 [Gating] SW mode calibration
6689 23:42:05.829971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6690 23:42:05.836729 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6691 23:42:05.840005 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6692 23:42:05.843756 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6693 23:42:05.846301 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 23:42:05.853603 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6695 23:42:05.856688 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 23:42:05.859812 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6697 23:42:05.866704 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6698 23:42:05.869711 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6699 23:42:05.873182 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6700 23:42:05.876611 Total UI for P1: 0, mck2ui 16
6701 23:42:05.879617 best dqsien dly found for B0: ( 0, 14, 24)
6702 23:42:05.883110 Total UI for P1: 0, mck2ui 16
6703 23:42:05.886720 best dqsien dly found for B1: ( 0, 14, 24)
6704 23:42:05.890076 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6705 23:42:05.893389 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6706 23:42:05.896796
6707 23:42:05.900047 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6708 23:42:05.903325 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6709 23:42:05.906691 [Gating] SW calibration Done
6710 23:42:05.906771 ==
6711 23:42:05.910627 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 23:42:05.913522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 23:42:05.913602 ==
6714 23:42:05.913665 RX Vref Scan: 0
6715 23:42:05.913723
6716 23:42:05.916509 RX Vref 0 -> 0, step: 1
6717 23:42:05.916589
6718 23:42:05.919753 RX Delay -410 -> 252, step: 16
6719 23:42:05.923014 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6720 23:42:05.927619 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6721 23:42:05.933685 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6722 23:42:05.936637 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6723 23:42:05.940063 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6724 23:42:05.943600 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6725 23:42:05.949891 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6726 23:42:05.953744 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6727 23:42:05.956668 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6728 23:42:05.960864 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6729 23:42:05.966578 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6730 23:42:05.970150 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6731 23:42:05.973090 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6732 23:42:05.980153 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6733 23:42:05.983270 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6734 23:42:05.986317 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6735 23:42:05.986428 ==
6736 23:42:05.989618 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 23:42:05.993313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 23:42:05.993394 ==
6739 23:42:05.996349 DQS Delay:
6740 23:42:05.996478 DQS0 = 51, DQS1 = 59
6741 23:42:05.999932 DQM Delay:
6742 23:42:06.000029 DQM0 = 19, DQM1 = 16
6743 23:42:06.003247 DQ Delay:
6744 23:42:06.003343 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6745 23:42:06.006543 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6746 23:42:06.009720 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6747 23:42:06.013053 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6748 23:42:06.013133
6749 23:42:06.013196
6750 23:42:06.016293 ==
6751 23:42:06.016372 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 23:42:06.022770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 23:42:06.022851 ==
6754 23:42:06.022914
6755 23:42:06.022972
6756 23:42:06.026568 TX Vref Scan disable
6757 23:42:06.026647 == TX Byte 0 ==
6758 23:42:06.029752 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 23:42:06.036129 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 23:42:06.036210 == TX Byte 1 ==
6761 23:42:06.040111 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 23:42:06.042795 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 23:42:06.046568 ==
6764 23:42:06.049840 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 23:42:06.052874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 23:42:06.052955 ==
6767 23:42:06.053047
6768 23:42:06.053107
6769 23:42:06.056333 TX Vref Scan disable
6770 23:42:06.056430 == TX Byte 0 ==
6771 23:42:06.060194 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 23:42:06.066706 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 23:42:06.066786 == TX Byte 1 ==
6774 23:42:06.069656 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 23:42:06.076334 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 23:42:06.076451
6777 23:42:06.076519 [DATLAT]
6778 23:42:06.076578 Freq=400, CH1 RK0
6779 23:42:06.076635
6780 23:42:06.079564 DATLAT Default: 0xf
6781 23:42:06.079644 0, 0xFFFF, sum = 0
6782 23:42:06.082946 1, 0xFFFF, sum = 0
6783 23:42:06.083065 2, 0xFFFF, sum = 0
6784 23:42:06.086467 3, 0xFFFF, sum = 0
6785 23:42:06.086547 4, 0xFFFF, sum = 0
6786 23:42:06.089755 5, 0xFFFF, sum = 0
6787 23:42:06.089836 6, 0xFFFF, sum = 0
6788 23:42:06.093125 7, 0xFFFF, sum = 0
6789 23:42:06.096390 8, 0xFFFF, sum = 0
6790 23:42:06.096471 9, 0xFFFF, sum = 0
6791 23:42:06.100004 10, 0xFFFF, sum = 0
6792 23:42:06.100085 11, 0xFFFF, sum = 0
6793 23:42:06.103045 12, 0xFFFF, sum = 0
6794 23:42:06.103126 13, 0x0, sum = 1
6795 23:42:06.106116 14, 0x0, sum = 2
6796 23:42:06.106196 15, 0x0, sum = 3
6797 23:42:06.110327 16, 0x0, sum = 4
6798 23:42:06.110408 best_step = 14
6799 23:42:06.110471
6800 23:42:06.110530 ==
6801 23:42:06.112796 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 23:42:06.116024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 23:42:06.116130 ==
6804 23:42:06.119648 RX Vref Scan: 1
6805 23:42:06.119725
6806 23:42:06.123063 RX Vref 0 -> 0, step: 1
6807 23:42:06.123137
6808 23:42:06.123199 RX Delay -359 -> 252, step: 8
6809 23:42:06.123256
6810 23:42:06.126542 Set Vref, RX VrefLevel [Byte0]: 58
6811 23:42:06.129553 [Byte1]: 52
6812 23:42:06.135100
6813 23:42:06.135174 Final RX Vref Byte 0 = 58 to rank0
6814 23:42:06.138506 Final RX Vref Byte 1 = 52 to rank0
6815 23:42:06.141826 Final RX Vref Byte 0 = 58 to rank1
6816 23:42:06.145098 Final RX Vref Byte 1 = 52 to rank1==
6817 23:42:06.148263 Dram Type= 6, Freq= 0, CH_1, rank 0
6818 23:42:06.155257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6819 23:42:06.155361 ==
6820 23:42:06.155461 DQS Delay:
6821 23:42:06.159066 DQS0 = 48, DQS1 = 60
6822 23:42:06.159167 DQM Delay:
6823 23:42:06.159263 DQM0 = 12, DQM1 = 13
6824 23:42:06.161479 DQ Delay:
6825 23:42:06.165188 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6826 23:42:06.165268 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =8
6827 23:42:06.168597 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6828 23:42:06.172211 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6829 23:42:06.172291
6830 23:42:06.172390
6831 23:42:06.181767 [DQSOSCAuto] RK0, (LSB)MR18= 0x862d, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6832 23:42:06.184783 CH1 RK0: MR19=C0C, MR18=862D
6833 23:42:06.191522 CH1_RK0: MR19=0xC0C, MR18=0x862D, DQSOSC=393, MR23=63, INC=382, DEC=254
6834 23:42:06.191624 ==
6835 23:42:06.195239 Dram Type= 6, Freq= 0, CH_1, rank 1
6836 23:42:06.198411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 23:42:06.198509 ==
6838 23:42:06.201818 [Gating] SW mode calibration
6839 23:42:06.208705 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6840 23:42:06.211929 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6841 23:42:06.218546 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6842 23:42:06.222006 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6843 23:42:06.224963 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 23:42:06.231552 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6845 23:42:06.234974 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 23:42:06.238254 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6847 23:42:06.245074 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6848 23:42:06.248455 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6849 23:42:06.252005 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6850 23:42:06.255254 Total UI for P1: 0, mck2ui 16
6851 23:42:06.258664 best dqsien dly found for B0: ( 0, 14, 24)
6852 23:42:06.262117 Total UI for P1: 0, mck2ui 16
6853 23:42:06.265300 best dqsien dly found for B1: ( 0, 14, 24)
6854 23:42:06.268625 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6855 23:42:06.272210 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6856 23:42:06.272290
6857 23:42:06.275383 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6858 23:42:06.281629 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6859 23:42:06.281709 [Gating] SW calibration Done
6860 23:42:06.285022 ==
6861 23:42:06.285102 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 23:42:06.292062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 23:42:06.292142 ==
6864 23:42:06.292205 RX Vref Scan: 0
6865 23:42:06.292264
6866 23:42:06.295432 RX Vref 0 -> 0, step: 1
6867 23:42:06.295512
6868 23:42:06.298957 RX Delay -410 -> 252, step: 16
6869 23:42:06.301651 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6870 23:42:06.304960 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6871 23:42:06.312156 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6872 23:42:06.315018 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6873 23:42:06.318574 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6874 23:42:06.321937 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6875 23:42:06.328856 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6876 23:42:06.331949 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6877 23:42:06.335119 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6878 23:42:06.338872 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6879 23:42:06.345316 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6880 23:42:06.348872 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6881 23:42:06.352233 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6882 23:42:06.355581 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6883 23:42:06.362047 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6884 23:42:06.365649 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6885 23:42:06.365728 ==
6886 23:42:06.368960 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 23:42:06.372009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 23:42:06.372089 ==
6889 23:42:06.375521 DQS Delay:
6890 23:42:06.375600 DQS0 = 43, DQS1 = 59
6891 23:42:06.375663 DQM Delay:
6892 23:42:06.378582 DQM0 = 9, DQM1 = 19
6893 23:42:06.378662 DQ Delay:
6894 23:42:06.381943 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6895 23:42:06.385286 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6896 23:42:06.388693 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6897 23:42:06.392209 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6898 23:42:06.392289
6899 23:42:06.392351
6900 23:42:06.392410 ==
6901 23:42:06.395732 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 23:42:06.398586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 23:42:06.398688 ==
6904 23:42:06.398787
6905 23:42:06.402065
6906 23:42:06.402164 TX Vref Scan disable
6907 23:42:06.405251 == TX Byte 0 ==
6908 23:42:06.409111 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6909 23:42:06.412298 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6910 23:42:06.415944 == TX Byte 1 ==
6911 23:42:06.419088 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6912 23:42:06.422233 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6913 23:42:06.422307 ==
6914 23:42:06.425412 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 23:42:06.428919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 23:42:06.429023 ==
6917 23:42:06.429089
6918 23:42:06.429149
6919 23:42:06.432600 TX Vref Scan disable
6920 23:42:06.435793 == TX Byte 0 ==
6921 23:42:06.438898 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6922 23:42:06.442212 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6923 23:42:06.442293 == TX Byte 1 ==
6924 23:42:06.449000 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6925 23:42:06.452496 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6926 23:42:06.452577
6927 23:42:06.452640 [DATLAT]
6928 23:42:06.455835 Freq=400, CH1 RK1
6929 23:42:06.455915
6930 23:42:06.455978 DATLAT Default: 0xe
6931 23:42:06.459160 0, 0xFFFF, sum = 0
6932 23:42:06.459241 1, 0xFFFF, sum = 0
6933 23:42:06.462276 2, 0xFFFF, sum = 0
6934 23:42:06.462357 3, 0xFFFF, sum = 0
6935 23:42:06.465820 4, 0xFFFF, sum = 0
6936 23:42:06.465901 5, 0xFFFF, sum = 0
6937 23:42:06.468965 6, 0xFFFF, sum = 0
6938 23:42:06.469085 7, 0xFFFF, sum = 0
6939 23:42:06.472085 8, 0xFFFF, sum = 0
6940 23:42:06.475714 9, 0xFFFF, sum = 0
6941 23:42:06.475795 10, 0xFFFF, sum = 0
6942 23:42:06.479112 11, 0xFFFF, sum = 0
6943 23:42:06.479193 12, 0xFFFF, sum = 0
6944 23:42:06.482588 13, 0x0, sum = 1
6945 23:42:06.482686 14, 0x0, sum = 2
6946 23:42:06.485667 15, 0x0, sum = 3
6947 23:42:06.485748 16, 0x0, sum = 4
6948 23:42:06.485813 best_step = 14
6949 23:42:06.485872
6950 23:42:06.489235 ==
6951 23:42:06.489316 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 23:42:06.495741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 23:42:06.495826 ==
6954 23:42:06.495889 RX Vref Scan: 0
6955 23:42:06.495949
6956 23:42:06.499093 RX Vref 0 -> 0, step: 1
6957 23:42:06.499173
6958 23:42:06.502404 RX Delay -359 -> 252, step: 8
6959 23:42:06.509577 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6960 23:42:06.512530 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6961 23:42:06.516073 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6962 23:42:06.518964 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6963 23:42:06.525466 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6964 23:42:06.529034 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6965 23:42:06.532112 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6966 23:42:06.539086 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6967 23:42:06.542694 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6968 23:42:06.545703 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6969 23:42:06.548881 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6970 23:42:06.556063 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6971 23:42:06.558726 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6972 23:42:06.562219 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6973 23:42:06.565833 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6974 23:42:06.572563 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6975 23:42:06.572643 ==
6976 23:42:06.575671 Dram Type= 6, Freq= 0, CH_1, rank 1
6977 23:42:06.578578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6978 23:42:06.578660 ==
6979 23:42:06.578724 DQS Delay:
6980 23:42:06.582115 DQS0 = 52, DQS1 = 56
6981 23:42:06.582196 DQM Delay:
6982 23:42:06.585447 DQM0 = 13, DQM1 = 8
6983 23:42:06.585528 DQ Delay:
6984 23:42:06.588881 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6985 23:42:06.592028 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6986 23:42:06.595733 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6987 23:42:06.598680 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6988 23:42:06.598760
6989 23:42:06.598823
6990 23:42:06.606004 [DQSOSCAuto] RK1, (LSB)MR18= 0x7288, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6991 23:42:06.609206 CH1 RK1: MR19=C0C, MR18=7288
6992 23:42:06.615462 CH1_RK1: MR19=0xC0C, MR18=0x7288, DQSOSC=392, MR23=63, INC=384, DEC=256
6993 23:42:06.618824 [RxdqsGatingPostProcess] freq 400
6994 23:42:06.625490 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6995 23:42:06.625573 best DQS0 dly(2T, 0.5T) = (0, 10)
6996 23:42:06.628896 best DQS1 dly(2T, 0.5T) = (0, 10)
6997 23:42:06.631959 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6998 23:42:06.635752 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6999 23:42:06.639182 best DQS0 dly(2T, 0.5T) = (0, 10)
7000 23:42:06.642487 best DQS1 dly(2T, 0.5T) = (0, 10)
7001 23:42:06.646059 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7002 23:42:06.649334 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7003 23:42:06.652363 Pre-setting of DQS Precalculation
7004 23:42:06.655904 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7005 23:42:06.666327 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7006 23:42:06.672729 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7007 23:42:06.672851
7008 23:42:06.672942
7009 23:42:06.675623 [Calibration Summary] 800 Mbps
7010 23:42:06.675704 CH 0, Rank 0
7011 23:42:06.679128 SW Impedance : PASS
7012 23:42:06.679209 DUTY Scan : NO K
7013 23:42:06.682340 ZQ Calibration : PASS
7014 23:42:06.686093 Jitter Meter : NO K
7015 23:42:06.686199 CBT Training : PASS
7016 23:42:06.689404 Write leveling : PASS
7017 23:42:06.689484 RX DQS gating : PASS
7018 23:42:06.692641 RX DQ/DQS(RDDQC) : PASS
7019 23:42:06.695905 TX DQ/DQS : PASS
7020 23:42:06.695985 RX DATLAT : PASS
7021 23:42:06.699228 RX DQ/DQS(Engine): PASS
7022 23:42:06.702755 TX OE : NO K
7023 23:42:06.702850 All Pass.
7024 23:42:06.702912
7025 23:42:06.702972 CH 0, Rank 1
7026 23:42:06.706534 SW Impedance : PASS
7027 23:42:06.709538 DUTY Scan : NO K
7028 23:42:06.709618 ZQ Calibration : PASS
7029 23:42:06.712686 Jitter Meter : NO K
7030 23:42:06.716199 CBT Training : PASS
7031 23:42:06.716278 Write leveling : NO K
7032 23:42:06.719727 RX DQS gating : PASS
7033 23:42:06.722477 RX DQ/DQS(RDDQC) : PASS
7034 23:42:06.722556 TX DQ/DQS : PASS
7035 23:42:06.726253 RX DATLAT : PASS
7036 23:42:06.729107 RX DQ/DQS(Engine): PASS
7037 23:42:06.729187 TX OE : NO K
7038 23:42:06.729268 All Pass.
7039 23:42:06.732711
7040 23:42:06.732850 CH 1, Rank 0
7041 23:42:06.736102 SW Impedance : PASS
7042 23:42:06.736181 DUTY Scan : NO K
7043 23:42:06.739662 ZQ Calibration : PASS
7044 23:42:06.739742 Jitter Meter : NO K
7045 23:42:06.742845 CBT Training : PASS
7046 23:42:06.746174 Write leveling : PASS
7047 23:42:06.746254 RX DQS gating : PASS
7048 23:42:06.749167 RX DQ/DQS(RDDQC) : PASS
7049 23:42:06.752667 TX DQ/DQS : PASS
7050 23:42:06.752764 RX DATLAT : PASS
7051 23:42:06.755757 RX DQ/DQS(Engine): PASS
7052 23:42:06.759419 TX OE : NO K
7053 23:42:06.759515 All Pass.
7054 23:42:06.759601
7055 23:42:06.759694 CH 1, Rank 1
7056 23:42:06.762948 SW Impedance : PASS
7057 23:42:06.766033 DUTY Scan : NO K
7058 23:42:06.766103 ZQ Calibration : PASS
7059 23:42:06.769511 Jitter Meter : NO K
7060 23:42:06.773585 CBT Training : PASS
7061 23:42:06.773655 Write leveling : NO K
7062 23:42:06.776195 RX DQS gating : PASS
7063 23:42:06.776271 RX DQ/DQS(RDDQC) : PASS
7064 23:42:06.779522 TX DQ/DQS : PASS
7065 23:42:06.782799 RX DATLAT : PASS
7066 23:42:06.782883 RX DQ/DQS(Engine): PASS
7067 23:42:06.786388 TX OE : NO K
7068 23:42:06.786459 All Pass.
7069 23:42:06.786522
7070 23:42:06.789830 DramC Write-DBI off
7071 23:42:06.792963 PER_BANK_REFRESH: Hybrid Mode
7072 23:42:06.793089 TX_TRACKING: ON
7073 23:42:06.802952 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7074 23:42:06.806247 [FAST_K] Save calibration result to emmc
7075 23:42:06.809903 dramc_set_vcore_voltage set vcore to 725000
7076 23:42:06.812787 Read voltage for 1600, 0
7077 23:42:06.812895 Vio18 = 0
7078 23:42:06.813008 Vcore = 725000
7079 23:42:06.816236 Vdram = 0
7080 23:42:06.816347 Vddq = 0
7081 23:42:06.816448 Vmddr = 0
7082 23:42:06.822723 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7083 23:42:06.826228 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7084 23:42:06.829484 MEM_TYPE=3, freq_sel=13
7085 23:42:06.832768 sv_algorithm_assistance_LP4_3733
7086 23:42:06.836427 ============ PULL DRAM RESETB DOWN ============
7087 23:42:06.839680 ========== PULL DRAM RESETB DOWN end =========
7088 23:42:06.846045 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7089 23:42:06.849406 ===================================
7090 23:42:06.849520 LPDDR4 DRAM CONFIGURATION
7091 23:42:06.852649 ===================================
7092 23:42:06.856251 EX_ROW_EN[0] = 0x0
7093 23:42:06.859940 EX_ROW_EN[1] = 0x0
7094 23:42:06.860013 LP4Y_EN = 0x0
7095 23:42:06.863134 WORK_FSP = 0x1
7096 23:42:06.863202 WL = 0x5
7097 23:42:06.866711 RL = 0x5
7098 23:42:06.866809 BL = 0x2
7099 23:42:06.869498 RPST = 0x0
7100 23:42:06.869568 RD_PRE = 0x0
7101 23:42:06.872928 WR_PRE = 0x1
7102 23:42:06.873058 WR_PST = 0x1
7103 23:42:06.876390 DBI_WR = 0x0
7104 23:42:06.876500 DBI_RD = 0x0
7105 23:42:06.880156 OTF = 0x1
7106 23:42:06.882719 ===================================
7107 23:42:06.886272 ===================================
7108 23:42:06.886344 ANA top config
7109 23:42:06.889562 ===================================
7110 23:42:06.893258 DLL_ASYNC_EN = 0
7111 23:42:06.896517 ALL_SLAVE_EN = 0
7112 23:42:06.899619 NEW_RANK_MODE = 1
7113 23:42:06.899701 DLL_IDLE_MODE = 1
7114 23:42:06.903533 LP45_APHY_COMB_EN = 1
7115 23:42:06.906996 TX_ODT_DIS = 0
7116 23:42:06.909937 NEW_8X_MODE = 1
7117 23:42:06.913908 ===================================
7118 23:42:06.916522 ===================================
7119 23:42:06.916619 data_rate = 3200
7120 23:42:06.919799 CKR = 1
7121 23:42:06.923244 DQ_P2S_RATIO = 8
7122 23:42:06.926662 ===================================
7123 23:42:06.929499 CA_P2S_RATIO = 8
7124 23:42:06.932895 DQ_CA_OPEN = 0
7125 23:42:06.936423 DQ_SEMI_OPEN = 0
7126 23:42:06.936525 CA_SEMI_OPEN = 0
7127 23:42:06.939494 CA_FULL_RATE = 0
7128 23:42:06.943089 DQ_CKDIV4_EN = 0
7129 23:42:06.946230 CA_CKDIV4_EN = 0
7130 23:42:06.949580 CA_PREDIV_EN = 0
7131 23:42:06.952758 PH8_DLY = 12
7132 23:42:06.952858 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7133 23:42:06.956169 DQ_AAMCK_DIV = 4
7134 23:42:06.959302 CA_AAMCK_DIV = 4
7135 23:42:06.962775 CA_ADMCK_DIV = 4
7136 23:42:06.966240 DQ_TRACK_CA_EN = 0
7137 23:42:06.969769 CA_PICK = 1600
7138 23:42:06.969853 CA_MCKIO = 1600
7139 23:42:06.972998 MCKIO_SEMI = 0
7140 23:42:06.976435 PLL_FREQ = 3068
7141 23:42:06.979546 DQ_UI_PI_RATIO = 32
7142 23:42:06.983139 CA_UI_PI_RATIO = 0
7143 23:42:06.986327 ===================================
7144 23:42:06.990179 ===================================
7145 23:42:06.993229 memory_type:LPDDR4
7146 23:42:06.993307 GP_NUM : 10
7147 23:42:06.996533 SRAM_EN : 1
7148 23:42:06.996633 MD32_EN : 0
7149 23:42:06.999778 ===================================
7150 23:42:07.003302 [ANA_INIT] >>>>>>>>>>>>>>
7151 23:42:07.006349 <<<<<< [CONFIGURE PHASE]: ANA_TX
7152 23:42:07.009977 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7153 23:42:07.013343 ===================================
7154 23:42:07.016318 data_rate = 3200,PCW = 0X7600
7155 23:42:07.019826 ===================================
7156 23:42:07.022974 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7157 23:42:07.029796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7158 23:42:07.033088 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7159 23:42:07.036258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7160 23:42:07.042942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7161 23:42:07.047301 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7162 23:42:07.047397 [ANA_INIT] flow start
7163 23:42:07.050218 [ANA_INIT] PLL >>>>>>>>
7164 23:42:07.052894 [ANA_INIT] PLL <<<<<<<<
7165 23:42:07.053043 [ANA_INIT] MIDPI >>>>>>>>
7166 23:42:07.056611 [ANA_INIT] MIDPI <<<<<<<<
7167 23:42:07.059788 [ANA_INIT] DLL >>>>>>>>
7168 23:42:07.059901 [ANA_INIT] DLL <<<<<<<<
7169 23:42:07.063339 [ANA_INIT] flow end
7170 23:42:07.066669 ============ LP4 DIFF to SE enter ============
7171 23:42:07.069671 ============ LP4 DIFF to SE exit ============
7172 23:42:07.073225 [ANA_INIT] <<<<<<<<<<<<<
7173 23:42:07.076451 [Flow] Enable top DCM control >>>>>
7174 23:42:07.079578 [Flow] Enable top DCM control <<<<<
7175 23:42:07.083265 Enable DLL master slave shuffle
7176 23:42:07.089499 ==============================================================
7177 23:42:07.089606 Gating Mode config
7178 23:42:07.096610 ==============================================================
7179 23:42:07.096725 Config description:
7180 23:42:07.106376 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7181 23:42:07.113448 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7182 23:42:07.119558 SELPH_MODE 0: By rank 1: By Phase
7183 23:42:07.122884 ==============================================================
7184 23:42:07.127175 GAT_TRACK_EN = 1
7185 23:42:07.129566 RX_GATING_MODE = 2
7186 23:42:07.133044 RX_GATING_TRACK_MODE = 2
7187 23:42:07.136666 SELPH_MODE = 1
7188 23:42:07.140134 PICG_EARLY_EN = 1
7189 23:42:07.143034 VALID_LAT_VALUE = 1
7190 23:42:07.146700 ==============================================================
7191 23:42:07.150007 Enter into Gating configuration >>>>
7192 23:42:07.153279 Exit from Gating configuration <<<<
7193 23:42:07.156867 Enter into DVFS_PRE_config >>>>>
7194 23:42:07.169771 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7195 23:42:07.173242 Exit from DVFS_PRE_config <<<<<
7196 23:42:07.173318 Enter into PICG configuration >>>>
7197 23:42:07.176606 Exit from PICG configuration <<<<
7198 23:42:07.179930 [RX_INPUT] configuration >>>>>
7199 23:42:07.183276 [RX_INPUT] configuration <<<<<
7200 23:42:07.189674 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7201 23:42:07.193208 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7202 23:42:07.200172 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7203 23:42:07.206945 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7204 23:42:07.213440 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7205 23:42:07.220114 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7206 23:42:07.223824 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7207 23:42:07.226653 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7208 23:42:07.230181 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7209 23:42:07.236810 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7210 23:42:07.240318 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7211 23:42:07.243905 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7212 23:42:07.246749 ===================================
7213 23:42:07.250623 LPDDR4 DRAM CONFIGURATION
7214 23:42:07.253769 ===================================
7215 23:42:07.253875 EX_ROW_EN[0] = 0x0
7216 23:42:07.256934 EX_ROW_EN[1] = 0x0
7217 23:42:07.257047 LP4Y_EN = 0x0
7218 23:42:07.260706 WORK_FSP = 0x1
7219 23:42:07.260786 WL = 0x5
7220 23:42:07.263607 RL = 0x5
7221 23:42:07.263687 BL = 0x2
7222 23:42:07.267461 RPST = 0x0
7223 23:42:07.270252 RD_PRE = 0x0
7224 23:42:07.270332 WR_PRE = 0x1
7225 23:42:07.274253 WR_PST = 0x1
7226 23:42:07.274333 DBI_WR = 0x0
7227 23:42:07.277412 DBI_RD = 0x0
7228 23:42:07.277492 OTF = 0x1
7229 23:42:07.280615 ===================================
7230 23:42:07.283520 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7231 23:42:07.290060 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7232 23:42:07.293738 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7233 23:42:07.296833 ===================================
7234 23:42:07.300044 LPDDR4 DRAM CONFIGURATION
7235 23:42:07.303691 ===================================
7236 23:42:07.303771 EX_ROW_EN[0] = 0x10
7237 23:42:07.306933 EX_ROW_EN[1] = 0x0
7238 23:42:07.307013 LP4Y_EN = 0x0
7239 23:42:07.310269 WORK_FSP = 0x1
7240 23:42:07.310349 WL = 0x5
7241 23:42:07.314051 RL = 0x5
7242 23:42:07.314131 BL = 0x2
7243 23:42:07.316795 RPST = 0x0
7244 23:42:07.316875 RD_PRE = 0x0
7245 23:42:07.320055 WR_PRE = 0x1
7246 23:42:07.323503 WR_PST = 0x1
7247 23:42:07.323583 DBI_WR = 0x0
7248 23:42:07.326622 DBI_RD = 0x0
7249 23:42:07.326702 OTF = 0x1
7250 23:42:07.329987 ===================================
7251 23:42:07.336919 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7252 23:42:07.337053 ==
7253 23:42:07.339878 Dram Type= 6, Freq= 0, CH_0, rank 0
7254 23:42:07.343139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7255 23:42:07.343220 ==
7256 23:42:07.346731 [Duty_Offset_Calibration]
7257 23:42:07.346811 B0:2 B1:-1 CA:1
7258 23:42:07.349870
7259 23:42:07.353505 [DutyScan_Calibration_Flow] k_type=0
7260 23:42:07.360428
7261 23:42:07.360509 ==CLK 0==
7262 23:42:07.363837 Final CLK duty delay cell = -4
7263 23:42:07.366999 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7264 23:42:07.371075 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7265 23:42:07.373687 [-4] AVG Duty = 4937%(X100)
7266 23:42:07.373767
7267 23:42:07.377564 CH0 CLK Duty spec in!! Max-Min= 187%
7268 23:42:07.381129 [DutyScan_Calibration_Flow] ====Done====
7269 23:42:07.381210
7270 23:42:07.383922 [DutyScan_Calibration_Flow] k_type=1
7271 23:42:07.399889
7272 23:42:07.399970 ==DQS 0 ==
7273 23:42:07.403904 Final DQS duty delay cell = 0
7274 23:42:07.407148 [0] MAX Duty = 5125%(X100), DQS PI = 20
7275 23:42:07.410510 [0] MIN Duty = 5000%(X100), DQS PI = 14
7276 23:42:07.410590 [0] AVG Duty = 5062%(X100)
7277 23:42:07.413282
7278 23:42:07.413366 ==DQS 1 ==
7279 23:42:07.417273 Final DQS duty delay cell = -4
7280 23:42:07.420398 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7281 23:42:07.423754 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7282 23:42:07.427013 [-4] AVG Duty = 5046%(X100)
7283 23:42:07.427094
7284 23:42:07.430461 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7285 23:42:07.430542
7286 23:42:07.433692 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7287 23:42:07.436860 [DutyScan_Calibration_Flow] ====Done====
7288 23:42:07.436995
7289 23:42:07.439888 [DutyScan_Calibration_Flow] k_type=3
7290 23:42:07.457686
7291 23:42:07.457771 ==DQM 0 ==
7292 23:42:07.461195 Final DQM duty delay cell = 0
7293 23:42:07.465215 [0] MAX Duty = 5000%(X100), DQS PI = 20
7294 23:42:07.467706 [0] MIN Duty = 4875%(X100), DQS PI = 4
7295 23:42:07.467787 [0] AVG Duty = 4937%(X100)
7296 23:42:07.470763
7297 23:42:07.470842 ==DQM 1 ==
7298 23:42:07.474561 Final DQM duty delay cell = 0
7299 23:42:07.477477 [0] MAX Duty = 5218%(X100), DQS PI = 58
7300 23:42:07.480914 [0] MIN Duty = 4969%(X100), DQS PI = 20
7301 23:42:07.481026 [0] AVG Duty = 5093%(X100)
7302 23:42:07.484395
7303 23:42:07.487779 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7304 23:42:07.487857
7305 23:42:07.491171 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7306 23:42:07.494571 [DutyScan_Calibration_Flow] ====Done====
7307 23:42:07.494649
7308 23:42:07.497661 [DutyScan_Calibration_Flow] k_type=2
7309 23:42:07.514294
7310 23:42:07.514372 ==DQ 0 ==
7311 23:42:07.517406 Final DQ duty delay cell = -4
7312 23:42:07.520683 [-4] MAX Duty = 5031%(X100), DQS PI = 56
7313 23:42:07.524098 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7314 23:42:07.527251 [-4] AVG Duty = 4937%(X100)
7315 23:42:07.527330
7316 23:42:07.527392 ==DQ 1 ==
7317 23:42:07.530675 Final DQ duty delay cell = 0
7318 23:42:07.533771 [0] MAX Duty = 5031%(X100), DQS PI = 30
7319 23:42:07.536965 [0] MIN Duty = 4907%(X100), DQS PI = 18
7320 23:42:07.541271 [0] AVG Duty = 4969%(X100)
7321 23:42:07.541351
7322 23:42:07.544018 CH0 DQ 0 Duty spec in!! Max-Min= 187%
7323 23:42:07.544097
7324 23:42:07.547000 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7325 23:42:07.550717 [DutyScan_Calibration_Flow] ====Done====
7326 23:42:07.550797 ==
7327 23:42:07.554159 Dram Type= 6, Freq= 0, CH_1, rank 0
7328 23:42:07.557339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7329 23:42:07.557420 ==
7330 23:42:07.560836 [Duty_Offset_Calibration]
7331 23:42:07.560916 B0:1 B1:1 CA:2
7332 23:42:07.560988
7333 23:42:07.563756 [DutyScan_Calibration_Flow] k_type=0
7334 23:42:07.574650
7335 23:42:07.574730 ==CLK 0==
7336 23:42:07.578151 Final CLK duty delay cell = 0
7337 23:42:07.581217 [0] MAX Duty = 5156%(X100), DQS PI = 24
7338 23:42:07.584378 [0] MIN Duty = 4938%(X100), DQS PI = 50
7339 23:42:07.584458 [0] AVG Duty = 5047%(X100)
7340 23:42:07.587999
7341 23:42:07.591239 CH1 CLK Duty spec in!! Max-Min= 218%
7342 23:42:07.594382 [DutyScan_Calibration_Flow] ====Done====
7343 23:42:07.594484
7344 23:42:07.597614 [DutyScan_Calibration_Flow] k_type=1
7345 23:42:07.614141
7346 23:42:07.614248 ==DQS 0 ==
7347 23:42:07.617609 Final DQS duty delay cell = 0
7348 23:42:07.620858 [0] MAX Duty = 5062%(X100), DQS PI = 22
7349 23:42:07.624362 [0] MIN Duty = 4813%(X100), DQS PI = 50
7350 23:42:07.624467 [0] AVG Duty = 4937%(X100)
7351 23:42:07.627749
7352 23:42:07.627830 ==DQS 1 ==
7353 23:42:07.631072 Final DQS duty delay cell = 0
7354 23:42:07.634690 [0] MAX Duty = 5031%(X100), DQS PI = 34
7355 23:42:07.637385 [0] MIN Duty = 4938%(X100), DQS PI = 14
7356 23:42:07.637465 [0] AVG Duty = 4984%(X100)
7357 23:42:07.640842
7358 23:42:07.644835 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7359 23:42:07.644916
7360 23:42:07.647844 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7361 23:42:07.650809 [DutyScan_Calibration_Flow] ====Done====
7362 23:42:07.650890
7363 23:42:07.654562 [DutyScan_Calibration_Flow] k_type=3
7364 23:42:07.671194
7365 23:42:07.671274 ==DQM 0 ==
7366 23:42:07.674366 Final DQM duty delay cell = 0
7367 23:42:07.677526 [0] MAX Duty = 5124%(X100), DQS PI = 18
7368 23:42:07.681152 [0] MIN Duty = 4813%(X100), DQS PI = 50
7369 23:42:07.684062 [0] AVG Duty = 4968%(X100)
7370 23:42:07.684163
7371 23:42:07.684254 ==DQM 1 ==
7372 23:42:07.687638 Final DQM duty delay cell = 0
7373 23:42:07.690963 [0] MAX Duty = 5125%(X100), DQS PI = 8
7374 23:42:07.694178 [0] MIN Duty = 4875%(X100), DQS PI = 22
7375 23:42:07.697475 [0] AVG Duty = 5000%(X100)
7376 23:42:07.697582
7377 23:42:07.701102 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7378 23:42:07.701203
7379 23:42:07.704662 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7380 23:42:07.707725 [DutyScan_Calibration_Flow] ====Done====
7381 23:42:07.707834
7382 23:42:07.711255 [DutyScan_Calibration_Flow] k_type=2
7383 23:42:07.728010
7384 23:42:07.728116 ==DQ 0 ==
7385 23:42:07.731241 Final DQ duty delay cell = 0
7386 23:42:07.734746 [0] MAX Duty = 5156%(X100), DQS PI = 20
7387 23:42:07.738673 [0] MIN Duty = 4907%(X100), DQS PI = 52
7388 23:42:07.738786 [0] AVG Duty = 5031%(X100)
7389 23:42:07.741535
7390 23:42:07.741637 ==DQ 1 ==
7391 23:42:07.744599 Final DQ duty delay cell = 0
7392 23:42:07.747825 [0] MAX Duty = 5093%(X100), DQS PI = 6
7393 23:42:07.751199 [0] MIN Duty = 5031%(X100), DQS PI = 0
7394 23:42:07.751312 [0] AVG Duty = 5062%(X100)
7395 23:42:07.751409
7396 23:42:07.754954 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7397 23:42:07.755057
7398 23:42:07.758108 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7399 23:42:07.764532 [DutyScan_Calibration_Flow] ====Done====
7400 23:42:07.767889 nWR fixed to 30
7401 23:42:07.767992 [ModeRegInit_LP4] CH0 RK0
7402 23:42:07.771603 [ModeRegInit_LP4] CH0 RK1
7403 23:42:07.774649 [ModeRegInit_LP4] CH1 RK0
7404 23:42:07.774756 [ModeRegInit_LP4] CH1 RK1
7405 23:42:07.777668 match AC timing 5
7406 23:42:07.781512 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7407 23:42:07.784425 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7408 23:42:07.791094 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7409 23:42:07.794392 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7410 23:42:07.802006 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7411 23:42:07.802110 [MiockJmeterHQA]
7412 23:42:07.802212
7413 23:42:07.805010 [DramcMiockJmeter] u1RxGatingPI = 0
7414 23:42:07.805158 0 : 4363, 4137
7415 23:42:07.808227 4 : 4257, 4029
7416 23:42:07.808343 8 : 4252, 4027
7417 23:42:07.811186 12 : 4363, 4137
7418 23:42:07.811292 16 : 4360, 4138
7419 23:42:07.814471 20 : 4252, 4027
7420 23:42:07.814584 24 : 4252, 4027
7421 23:42:07.814677 28 : 4253, 4026
7422 23:42:07.817810 32 : 4363, 4138
7423 23:42:07.817916 36 : 4252, 4027
7424 23:42:07.821392 40 : 4363, 4137
7425 23:42:07.821472 44 : 4253, 4027
7426 23:42:07.824906 48 : 4252, 4027
7427 23:42:07.825047 52 : 4253, 4029
7428 23:42:07.828286 56 : 4254, 4029
7429 23:42:07.828404 60 : 4360, 4138
7430 23:42:07.828551 64 : 4253, 4027
7431 23:42:07.831547 68 : 4361, 4137
7432 23:42:07.831658 72 : 4250, 4027
7433 23:42:07.834909 76 : 4250, 4027
7434 23:42:07.835020 80 : 4250, 4027
7435 23:42:07.838300 84 : 4360, 4138
7436 23:42:07.838405 88 : 4250, 4027
7437 23:42:07.838500 92 : 4360, 4138
7438 23:42:07.841462 96 : 4249, 3498
7439 23:42:07.841573 100 : 4250, 0
7440 23:42:07.844721 104 : 4250, 0
7441 23:42:07.844832 108 : 4252, 0
7442 23:42:07.844927 112 : 4250, 0
7443 23:42:07.848059 116 : 4252, 0
7444 23:42:07.848167 120 : 4360, 0
7445 23:42:07.851609 124 : 4250, 0
7446 23:42:07.851719 128 : 4249, 0
7447 23:42:07.851816 132 : 4361, 0
7448 23:42:07.854967 136 : 4360, 0
7449 23:42:07.855073 140 : 4250, 0
7450 23:42:07.858305 144 : 4250, 0
7451 23:42:07.858408 148 : 4250, 0
7452 23:42:07.858499 152 : 4250, 0
7453 23:42:07.861603 156 : 4250, 0
7454 23:42:07.861696 160 : 4250, 0
7455 23:42:07.861789 164 : 4250, 0
7456 23:42:07.864996 168 : 4252, 0
7457 23:42:07.865098 172 : 4250, 0
7458 23:42:07.868413 176 : 4250, 0
7459 23:42:07.868523 180 : 4253, 0
7460 23:42:07.868625 184 : 4361, 0
7461 23:42:07.871527 188 : 4361, 0
7462 23:42:07.871638 192 : 4363, 0
7463 23:42:07.874935 196 : 4250, 0
7464 23:42:07.875044 200 : 4360, 0
7465 23:42:07.875143 204 : 4250, 0
7466 23:42:07.878422 208 : 4250, 0
7467 23:42:07.878532 212 : 4250, 60
7468 23:42:07.881893 216 : 4363, 3261
7469 23:42:07.882004 220 : 4250, 4026
7470 23:42:07.885158 224 : 4250, 4027
7471 23:42:07.885269 228 : 4250, 4027
7472 23:42:07.885364 232 : 4252, 4029
7473 23:42:07.888151 236 : 4250, 4026
7474 23:42:07.888250 240 : 4250, 4027
7475 23:42:07.891802 244 : 4250, 4027
7476 23:42:07.891903 248 : 4252, 4029
7477 23:42:07.895478 252 : 4250, 4027
7478 23:42:07.895580 256 : 4360, 4138
7479 23:42:07.898153 260 : 4360, 4138
7480 23:42:07.898256 264 : 4248, 4024
7481 23:42:07.901542 268 : 4363, 4139
7482 23:42:07.901659 272 : 4360, 4137
7483 23:42:07.904829 276 : 4250, 4027
7484 23:42:07.904937 280 : 4250, 4027
7485 23:42:07.908106 284 : 4252, 4029
7486 23:42:07.908214 288 : 4250, 4027
7487 23:42:07.908313 292 : 4250, 4027
7488 23:42:07.911710 296 : 4250, 4027
7489 23:42:07.911820 300 : 4252, 4029
7490 23:42:07.915138 304 : 4250, 4026
7491 23:42:07.915247 308 : 4360, 4138
7492 23:42:07.918425 312 : 4360, 4138
7493 23:42:07.918536 316 : 4250, 4027
7494 23:42:07.921743 320 : 4363, 4140
7495 23:42:07.921854 324 : 4360, 4138
7496 23:42:07.925227 328 : 4250, 4027
7497 23:42:07.925332 332 : 4250, 3009
7498 23:42:07.928317 336 : 4252, 210
7499 23:42:07.928419
7500 23:42:07.928523 MIOCK jitter meter ch=0
7501 23:42:07.928621
7502 23:42:07.931828 1T = (336-100) = 236 dly cells
7503 23:42:07.938365 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7504 23:42:07.938479 ==
7505 23:42:07.941926 Dram Type= 6, Freq= 0, CH_0, rank 0
7506 23:42:07.945158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7507 23:42:07.945262 ==
7508 23:42:07.951840 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7509 23:42:07.955344 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7510 23:42:07.958757 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7511 23:42:07.965806 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7512 23:42:07.974302 [CA 0] Center 44 (14~75) winsize 62
7513 23:42:07.977761 [CA 1] Center 44 (14~74) winsize 61
7514 23:42:07.981287 [CA 2] Center 39 (10~68) winsize 59
7515 23:42:07.984139 [CA 3] Center 39 (10~68) winsize 59
7516 23:42:07.988093 [CA 4] Center 37 (7~67) winsize 61
7517 23:42:07.991359 [CA 5] Center 37 (7~67) winsize 61
7518 23:42:07.991459
7519 23:42:07.994449 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7520 23:42:07.994546
7521 23:42:07.998210 [CATrainingPosCal] consider 1 rank data
7522 23:42:08.001404 u2DelayCellTimex100 = 275/100 ps
7523 23:42:08.004389 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7524 23:42:08.011181 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7525 23:42:08.014559 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7526 23:42:08.017736 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7527 23:42:08.021063 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7528 23:42:08.024463 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7529 23:42:08.024565
7530 23:42:08.028252 CA PerBit enable=1, Macro0, CA PI delay=37
7531 23:42:08.028352
7532 23:42:08.031292 [CBTSetCACLKResult] CA Dly = 37
7533 23:42:08.034390 CS Dly: 10 (0~41)
7534 23:42:08.037806 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7535 23:42:08.041195 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7536 23:42:08.041299 ==
7537 23:42:08.044357 Dram Type= 6, Freq= 0, CH_0, rank 1
7538 23:42:08.047571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7539 23:42:08.050841 ==
7540 23:42:08.054212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7541 23:42:08.057526 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7542 23:42:08.064427 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7543 23:42:08.068231 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7544 23:42:08.078393 [CA 0] Center 43 (13~74) winsize 62
7545 23:42:08.081307 [CA 1] Center 43 (13~74) winsize 62
7546 23:42:08.084814 [CA 2] Center 39 (10~69) winsize 60
7547 23:42:08.088164 [CA 3] Center 38 (9~68) winsize 60
7548 23:42:08.091305 [CA 4] Center 37 (7~67) winsize 61
7549 23:42:08.095202 [CA 5] Center 37 (7~67) winsize 61
7550 23:42:08.095302
7551 23:42:08.098478 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7552 23:42:08.098577
7553 23:42:08.102090 [CATrainingPosCal] consider 2 rank data
7554 23:42:08.104734 u2DelayCellTimex100 = 275/100 ps
7555 23:42:08.108120 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7556 23:42:08.115307 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7557 23:42:08.118481 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7558 23:42:08.121726 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7559 23:42:08.125076 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7560 23:42:08.128388 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7561 23:42:08.128491
7562 23:42:08.131669 CA PerBit enable=1, Macro0, CA PI delay=37
7563 23:42:08.131772
7564 23:42:08.134839 [CBTSetCACLKResult] CA Dly = 37
7565 23:42:08.138601 CS Dly: 11 (0~44)
7566 23:42:08.141765 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7567 23:42:08.144744 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7568 23:42:08.144883
7569 23:42:08.148477 ----->DramcWriteLeveling(PI) begin...
7570 23:42:08.148594 ==
7571 23:42:08.151879 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 23:42:08.155100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 23:42:08.158467 ==
7574 23:42:08.158567 Write leveling (Byte 0): 34 => 34
7575 23:42:08.161664 Write leveling (Byte 1): 29 => 29
7576 23:42:08.165001 DramcWriteLeveling(PI) end<-----
7577 23:42:08.165128
7578 23:42:08.165223 ==
7579 23:42:08.168185 Dram Type= 6, Freq= 0, CH_0, rank 0
7580 23:42:08.175111 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7581 23:42:08.175224 ==
7582 23:42:08.175318 [Gating] SW mode calibration
7583 23:42:08.184928 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7584 23:42:08.188790 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7585 23:42:08.191327 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 23:42:08.198378 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 23:42:08.201804 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7588 23:42:08.205086 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7589 23:42:08.211943 1 4 16 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
7590 23:42:08.215457 1 4 20 | B1->B0 | 2525 3434 | 1 0 | (1 1) (0 0)
7591 23:42:08.218511 1 4 24 | B1->B0 | 3130 3434 | 1 1 | (0 0) (1 1)
7592 23:42:08.225136 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 23:42:08.228956 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7594 23:42:08.231625 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7595 23:42:08.238623 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7596 23:42:08.241587 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7597 23:42:08.245479 1 5 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7598 23:42:08.251886 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7599 23:42:08.254908 1 5 24 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
7600 23:42:08.258578 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 23:42:08.262119 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 23:42:08.268787 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 23:42:08.271887 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7604 23:42:08.275450 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 23:42:08.281785 1 6 16 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7606 23:42:08.285244 1 6 20 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
7607 23:42:08.288590 1 6 24 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
7608 23:42:08.295152 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 23:42:08.299102 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 23:42:08.302707 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7611 23:42:08.308944 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 23:42:08.311718 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 23:42:08.315334 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7614 23:42:08.322213 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7615 23:42:08.325205 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7616 23:42:08.328755 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 23:42:08.335196 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 23:42:08.338732 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 23:42:08.342139 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 23:42:08.345719 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 23:42:08.352405 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 23:42:08.355368 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 23:42:08.358693 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 23:42:08.365348 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 23:42:08.369145 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 23:42:08.372034 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7627 23:42:08.378723 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7628 23:42:08.381890 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7629 23:42:08.385647 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7630 23:42:08.391948 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7631 23:42:08.395131 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7632 23:42:08.398614 Total UI for P1: 0, mck2ui 16
7633 23:42:08.402175 best dqsien dly found for B0: ( 1, 9, 18)
7634 23:42:08.405468 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 23:42:08.409287 Total UI for P1: 0, mck2ui 16
7636 23:42:08.412746 best dqsien dly found for B1: ( 1, 9, 22)
7637 23:42:08.415521 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7638 23:42:08.419069 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7639 23:42:08.419167
7640 23:42:08.422628 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7641 23:42:08.428670 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7642 23:42:08.428773 [Gating] SW calibration Done
7643 23:42:08.428868 ==
7644 23:42:08.432133 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 23:42:08.438824 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 23:42:08.438932 ==
7647 23:42:08.439029 RX Vref Scan: 0
7648 23:42:08.439116
7649 23:42:08.442123 RX Vref 0 -> 0, step: 1
7650 23:42:08.442224
7651 23:42:08.445656 RX Delay 0 -> 252, step: 8
7652 23:42:08.448803 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7653 23:42:08.452234 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7654 23:42:08.455585 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7655 23:42:08.459029 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7656 23:42:08.465725 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7657 23:42:08.468707 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7658 23:42:08.472294 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7659 23:42:08.475938 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7660 23:42:08.478843 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7661 23:42:08.485383 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7662 23:42:08.488601 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7663 23:42:08.492102 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7664 23:42:08.495275 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7665 23:42:08.498795 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7666 23:42:08.505220 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7667 23:42:08.508863 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7668 23:42:08.508969 ==
7669 23:42:08.512583 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 23:42:08.515668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 23:42:08.515772 ==
7672 23:42:08.518953 DQS Delay:
7673 23:42:08.519050 DQS0 = 0, DQS1 = 0
7674 23:42:08.519116 DQM Delay:
7675 23:42:08.522249 DQM0 = 132, DQM1 = 125
7676 23:42:08.522351 DQ Delay:
7677 23:42:08.525662 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7678 23:42:08.528851 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7679 23:42:08.532538 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7680 23:42:08.539055 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7681 23:42:08.539158
7682 23:42:08.539253
7683 23:42:08.539343 ==
7684 23:42:08.542126 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 23:42:08.545784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 23:42:08.545886 ==
7687 23:42:08.545983
7688 23:42:08.546078
7689 23:42:08.548733 TX Vref Scan disable
7690 23:42:08.548835 == TX Byte 0 ==
7691 23:42:08.555512 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7692 23:42:08.558768 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7693 23:42:08.558868 == TX Byte 1 ==
7694 23:42:08.565333 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7695 23:42:08.568784 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7696 23:42:08.568903 ==
7697 23:42:08.572390 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 23:42:08.575412 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 23:42:08.575522 ==
7700 23:42:08.590001
7701 23:42:08.593338 TX Vref early break, caculate TX vref
7702 23:42:08.596847 TX Vref=16, minBit 1, minWin=22, winSum=368
7703 23:42:08.600013 TX Vref=18, minBit 7, minWin=22, winSum=381
7704 23:42:08.603076 TX Vref=20, minBit 7, minWin=22, winSum=386
7705 23:42:08.606696 TX Vref=22, minBit 4, minWin=23, winSum=394
7706 23:42:08.609631 TX Vref=24, minBit 7, minWin=23, winSum=407
7707 23:42:08.616406 TX Vref=26, minBit 1, minWin=24, winSum=411
7708 23:42:08.619784 TX Vref=28, minBit 4, minWin=24, winSum=425
7709 23:42:08.623025 TX Vref=30, minBit 4, minWin=24, winSum=423
7710 23:42:08.626670 TX Vref=32, minBit 4, minWin=24, winSum=417
7711 23:42:08.629859 TX Vref=34, minBit 1, minWin=24, winSum=401
7712 23:42:08.636742 [TxChooseVref] Worse bit 4, Min win 24, Win sum 425, Final Vref 28
7713 23:42:08.636849
7714 23:42:08.639791 Final TX Range 0 Vref 28
7715 23:42:08.639892
7716 23:42:08.639984 ==
7717 23:42:08.643112 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 23:42:08.646357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 23:42:08.646436 ==
7720 23:42:08.646524
7721 23:42:08.646611
7722 23:42:08.649967 TX Vref Scan disable
7723 23:42:08.657043 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7724 23:42:08.657119 == TX Byte 0 ==
7725 23:42:08.660290 u2DelayCellOfst[0]=10 cells (3 PI)
7726 23:42:08.663411 u2DelayCellOfst[1]=17 cells (5 PI)
7727 23:42:08.667031 u2DelayCellOfst[2]=7 cells (2 PI)
7728 23:42:08.670506 u2DelayCellOfst[3]=14 cells (4 PI)
7729 23:42:08.673514 u2DelayCellOfst[4]=10 cells (3 PI)
7730 23:42:08.676733 u2DelayCellOfst[5]=0 cells (0 PI)
7731 23:42:08.676831 u2DelayCellOfst[6]=17 cells (5 PI)
7732 23:42:08.679815 u2DelayCellOfst[7]=17 cells (5 PI)
7733 23:42:08.686714 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7734 23:42:08.690051 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7735 23:42:08.690160 == TX Byte 1 ==
7736 23:42:08.693154 u2DelayCellOfst[8]=0 cells (0 PI)
7737 23:42:08.696645 u2DelayCellOfst[9]=0 cells (0 PI)
7738 23:42:08.699935 u2DelayCellOfst[10]=7 cells (2 PI)
7739 23:42:08.703106 u2DelayCellOfst[11]=0 cells (0 PI)
7740 23:42:08.706680 u2DelayCellOfst[12]=10 cells (3 PI)
7741 23:42:08.709906 u2DelayCellOfst[13]=10 cells (3 PI)
7742 23:42:08.713906 u2DelayCellOfst[14]=14 cells (4 PI)
7743 23:42:08.716545 u2DelayCellOfst[15]=7 cells (2 PI)
7744 23:42:08.720222 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7745 23:42:08.723222 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7746 23:42:08.726442 DramC Write-DBI on
7747 23:42:08.726546 ==
7748 23:42:08.729687 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 23:42:08.733256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 23:42:08.733359 ==
7751 23:42:08.733453
7752 23:42:08.733539
7753 23:42:08.736661 TX Vref Scan disable
7754 23:42:08.739892 == TX Byte 0 ==
7755 23:42:08.742697 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7756 23:42:08.746376 == TX Byte 1 ==
7757 23:42:08.749399 Update DQM dly =728 (2 ,6, 24) DQM OEN =(3 ,3)
7758 23:42:08.749505 DramC Write-DBI off
7759 23:42:08.749598
7760 23:42:08.753195 [DATLAT]
7761 23:42:08.753297 Freq=1600, CH0 RK0
7762 23:42:08.753393
7763 23:42:08.756178 DATLAT Default: 0xf
7764 23:42:08.756276 0, 0xFFFF, sum = 0
7765 23:42:08.760195 1, 0xFFFF, sum = 0
7766 23:42:08.760299 2, 0xFFFF, sum = 0
7767 23:42:08.763271 3, 0xFFFF, sum = 0
7768 23:42:08.763372 4, 0xFFFF, sum = 0
7769 23:42:08.766258 5, 0xFFFF, sum = 0
7770 23:42:08.766360 6, 0xFFFF, sum = 0
7771 23:42:08.769500 7, 0xFFFF, sum = 0
7772 23:42:08.769622 8, 0xFFFF, sum = 0
7773 23:42:08.772686 9, 0xFFFF, sum = 0
7774 23:42:08.775940 10, 0xFFFF, sum = 0
7775 23:42:08.776051 11, 0xFFFF, sum = 0
7776 23:42:08.779604 12, 0xFFFF, sum = 0
7777 23:42:08.779718 13, 0xFFFF, sum = 0
7778 23:42:08.782955 14, 0x0, sum = 1
7779 23:42:08.783058 15, 0x0, sum = 2
7780 23:42:08.786074 16, 0x0, sum = 3
7781 23:42:08.786176 17, 0x0, sum = 4
7782 23:42:08.786268 best_step = 15
7783 23:42:08.789862
7784 23:42:08.789955 ==
7785 23:42:08.793315 Dram Type= 6, Freq= 0, CH_0, rank 0
7786 23:42:08.796314 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7787 23:42:08.796411 ==
7788 23:42:08.796504 RX Vref Scan: 1
7789 23:42:08.796592
7790 23:42:08.799514 Set Vref Range= 24 -> 127
7791 23:42:08.799612
7792 23:42:08.802613 RX Vref 24 -> 127, step: 1
7793 23:42:08.802710
7794 23:42:08.806466 RX Delay 11 -> 252, step: 4
7795 23:42:08.806562
7796 23:42:08.809601 Set Vref, RX VrefLevel [Byte0]: 24
7797 23:42:08.813057 [Byte1]: 24
7798 23:42:08.813157
7799 23:42:08.816087 Set Vref, RX VrefLevel [Byte0]: 25
7800 23:42:08.819672 [Byte1]: 25
7801 23:42:08.819771
7802 23:42:08.822610 Set Vref, RX VrefLevel [Byte0]: 26
7803 23:42:08.826092 [Byte1]: 26
7804 23:42:08.829816
7805 23:42:08.829914 Set Vref, RX VrefLevel [Byte0]: 27
7806 23:42:08.833090 [Byte1]: 27
7807 23:42:08.837197
7808 23:42:08.837299 Set Vref, RX VrefLevel [Byte0]: 28
7809 23:42:08.840764 [Byte1]: 28
7810 23:42:08.844684
7811 23:42:08.844786 Set Vref, RX VrefLevel [Byte0]: 29
7812 23:42:08.848008 [Byte1]: 29
7813 23:42:08.852676
7814 23:42:08.852777 Set Vref, RX VrefLevel [Byte0]: 30
7815 23:42:08.855910 [Byte1]: 30
7816 23:42:08.860113
7817 23:42:08.860220 Set Vref, RX VrefLevel [Byte0]: 31
7818 23:42:08.863470 [Byte1]: 31
7819 23:42:08.867581
7820 23:42:08.867687 Set Vref, RX VrefLevel [Byte0]: 32
7821 23:42:08.870832 [Byte1]: 32
7822 23:42:08.875068
7823 23:42:08.875166 Set Vref, RX VrefLevel [Byte0]: 33
7824 23:42:08.878630 [Byte1]: 33
7825 23:42:08.882664
7826 23:42:08.882765 Set Vref, RX VrefLevel [Byte0]: 34
7827 23:42:08.886373 [Byte1]: 34
7828 23:42:08.890559
7829 23:42:08.890665 Set Vref, RX VrefLevel [Byte0]: 35
7830 23:42:08.893863 [Byte1]: 35
7831 23:42:08.897833
7832 23:42:08.897939 Set Vref, RX VrefLevel [Byte0]: 36
7833 23:42:08.901389 [Byte1]: 36
7834 23:42:08.905720
7835 23:42:08.905820 Set Vref, RX VrefLevel [Byte0]: 37
7836 23:42:08.909130 [Byte1]: 37
7837 23:42:08.913473
7838 23:42:08.913564 Set Vref, RX VrefLevel [Byte0]: 38
7839 23:42:08.916909 [Byte1]: 38
7840 23:42:08.920841
7841 23:42:08.920938 Set Vref, RX VrefLevel [Byte0]: 39
7842 23:42:08.924117 [Byte1]: 39
7843 23:42:08.928736
7844 23:42:08.928817 Set Vref, RX VrefLevel [Byte0]: 40
7845 23:42:08.932149 [Byte1]: 40
7846 23:42:08.936878
7847 23:42:08.936985 Set Vref, RX VrefLevel [Byte0]: 41
7848 23:42:08.939429 [Byte1]: 41
7849 23:42:08.944041
7850 23:42:08.944141 Set Vref, RX VrefLevel [Byte0]: 42
7851 23:42:08.947318 [Byte1]: 42
7852 23:42:08.951232
7853 23:42:08.951333 Set Vref, RX VrefLevel [Byte0]: 43
7854 23:42:08.954593 [Byte1]: 43
7855 23:42:08.959287
7856 23:42:08.959382 Set Vref, RX VrefLevel [Byte0]: 44
7857 23:42:08.962105 [Byte1]: 44
7858 23:42:08.966838
7859 23:42:08.966938 Set Vref, RX VrefLevel [Byte0]: 45
7860 23:42:08.970437 [Byte1]: 45
7861 23:42:08.974170
7862 23:42:08.974266 Set Vref, RX VrefLevel [Byte0]: 46
7863 23:42:08.977420 [Byte1]: 46
7864 23:42:08.982214
7865 23:42:08.982318 Set Vref, RX VrefLevel [Byte0]: 47
7866 23:42:08.984863 [Byte1]: 47
7867 23:42:08.989844
7868 23:42:08.989942 Set Vref, RX VrefLevel [Byte0]: 48
7869 23:42:08.992699 [Byte1]: 48
7870 23:42:08.997362
7871 23:42:08.997441 Set Vref, RX VrefLevel [Byte0]: 49
7872 23:42:09.000482 [Byte1]: 49
7873 23:42:09.004528
7874 23:42:09.004629 Set Vref, RX VrefLevel [Byte0]: 50
7875 23:42:09.008440 [Byte1]: 50
7876 23:42:09.012290
7877 23:42:09.012398 Set Vref, RX VrefLevel [Byte0]: 51
7878 23:42:09.016319 [Byte1]: 51
7879 23:42:09.019825
7880 23:42:09.019925 Set Vref, RX VrefLevel [Byte0]: 52
7881 23:42:09.023340 [Byte1]: 52
7882 23:42:09.027359
7883 23:42:09.027459 Set Vref, RX VrefLevel [Byte0]: 53
7884 23:42:09.030913 [Byte1]: 53
7885 23:42:09.035286
7886 23:42:09.035385 Set Vref, RX VrefLevel [Byte0]: 54
7887 23:42:09.038493 [Byte1]: 54
7888 23:42:09.042797
7889 23:42:09.042902 Set Vref, RX VrefLevel [Byte0]: 55
7890 23:42:09.046446 [Byte1]: 55
7891 23:42:09.050127
7892 23:42:09.050228 Set Vref, RX VrefLevel [Byte0]: 56
7893 23:42:09.053505 [Byte1]: 56
7894 23:42:09.058314
7895 23:42:09.058419 Set Vref, RX VrefLevel [Byte0]: 57
7896 23:42:09.061428 [Byte1]: 57
7897 23:42:09.065820
7898 23:42:09.065922 Set Vref, RX VrefLevel [Byte0]: 58
7899 23:42:09.068965 [Byte1]: 58
7900 23:42:09.073195
7901 23:42:09.073280 Set Vref, RX VrefLevel [Byte0]: 59
7902 23:42:09.076493 [Byte1]: 59
7903 23:42:09.080941
7904 23:42:09.081084 Set Vref, RX VrefLevel [Byte0]: 60
7905 23:42:09.084221 [Byte1]: 60
7906 23:42:09.088446
7907 23:42:09.088546 Set Vref, RX VrefLevel [Byte0]: 61
7908 23:42:09.091521 [Byte1]: 61
7909 23:42:09.096114
7910 23:42:09.096213 Set Vref, RX VrefLevel [Byte0]: 62
7911 23:42:09.099537 [Byte1]: 62
7912 23:42:09.103415
7913 23:42:09.103523 Set Vref, RX VrefLevel [Byte0]: 63
7914 23:42:09.107025 [Byte1]: 63
7915 23:42:09.111218
7916 23:42:09.111320 Set Vref, RX VrefLevel [Byte0]: 64
7917 23:42:09.114415 [Byte1]: 64
7918 23:42:09.118541
7919 23:42:09.118613 Set Vref, RX VrefLevel [Byte0]: 65
7920 23:42:09.122156 [Byte1]: 65
7921 23:42:09.126743
7922 23:42:09.126844 Set Vref, RX VrefLevel [Byte0]: 66
7923 23:42:09.130047 [Byte1]: 66
7924 23:42:09.134099
7925 23:42:09.134198 Set Vref, RX VrefLevel [Byte0]: 67
7926 23:42:09.137572 [Byte1]: 67
7927 23:42:09.141784
7928 23:42:09.141883 Set Vref, RX VrefLevel [Byte0]: 68
7929 23:42:09.144817 [Byte1]: 68
7930 23:42:09.149583
7931 23:42:09.149684 Set Vref, RX VrefLevel [Byte0]: 69
7932 23:42:09.152529 [Byte1]: 69
7933 23:42:09.156861
7934 23:42:09.156972 Set Vref, RX VrefLevel [Byte0]: 70
7935 23:42:09.160132 [Byte1]: 70
7936 23:42:09.164892
7937 23:42:09.165034 Set Vref, RX VrefLevel [Byte0]: 71
7938 23:42:09.167766 [Byte1]: 71
7939 23:42:09.172193
7940 23:42:09.172275 Set Vref, RX VrefLevel [Byte0]: 72
7941 23:42:09.175372 [Byte1]: 72
7942 23:42:09.180105
7943 23:42:09.180205 Set Vref, RX VrefLevel [Byte0]: 73
7944 23:42:09.182893 [Byte1]: 73
7945 23:42:09.187219
7946 23:42:09.187315 Set Vref, RX VrefLevel [Byte0]: 74
7947 23:42:09.190622 [Byte1]: 74
7948 23:42:09.195118
7949 23:42:09.195190 Set Vref, RX VrefLevel [Byte0]: 75
7950 23:42:09.198516 [Byte1]: 75
7951 23:42:09.203088
7952 23:42:09.203194 Set Vref, RX VrefLevel [Byte0]: 76
7953 23:42:09.206095 [Byte1]: 76
7954 23:42:09.210139
7955 23:42:09.210219 Final RX Vref Byte 0 = 54 to rank0
7956 23:42:09.213501 Final RX Vref Byte 1 = 60 to rank0
7957 23:42:09.216653 Final RX Vref Byte 0 = 54 to rank1
7958 23:42:09.220241 Final RX Vref Byte 1 = 60 to rank1==
7959 23:42:09.223501 Dram Type= 6, Freq= 0, CH_0, rank 0
7960 23:42:09.230136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7961 23:42:09.230247 ==
7962 23:42:09.230342 DQS Delay:
7963 23:42:09.230429 DQS0 = 0, DQS1 = 0
7964 23:42:09.233696 DQM Delay:
7965 23:42:09.233776 DQM0 = 129, DQM1 = 122
7966 23:42:09.236941 DQ Delay:
7967 23:42:09.240403 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7968 23:42:09.243956 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =138
7969 23:42:09.247282 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =118
7970 23:42:09.250399 DQ12 =128, DQ13 =126, DQ14 =132, DQ15 =132
7971 23:42:09.250500
7972 23:42:09.250591
7973 23:42:09.250677
7974 23:42:09.253946 [DramC_TX_OE_Calibration] TA2
7975 23:42:09.257128 Original DQ_B0 (3 6) =30, OEN = 27
7976 23:42:09.260554 Original DQ_B1 (3 6) =30, OEN = 27
7977 23:42:09.263435 24, 0x0, End_B0=24 End_B1=24
7978 23:42:09.263538 25, 0x0, End_B0=25 End_B1=25
7979 23:42:09.267062 26, 0x0, End_B0=26 End_B1=26
7980 23:42:09.270100 27, 0x0, End_B0=27 End_B1=27
7981 23:42:09.273543 28, 0x0, End_B0=28 End_B1=28
7982 23:42:09.273616 29, 0x0, End_B0=29 End_B1=29
7983 23:42:09.277325 30, 0x0, End_B0=30 End_B1=30
7984 23:42:09.280716 31, 0x4141, End_B0=30 End_B1=30
7985 23:42:09.283996 Byte0 end_step=30 best_step=27
7986 23:42:09.287378 Byte1 end_step=30 best_step=27
7987 23:42:09.290459 Byte0 TX OE(2T, 0.5T) = (3, 3)
7988 23:42:09.290564 Byte1 TX OE(2T, 0.5T) = (3, 3)
7989 23:42:09.290654
7990 23:42:09.290741
7991 23:42:09.300506 [DQSOSCAuto] RK0, (LSB)MR18= 0x1508, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
7992 23:42:09.303751 CH0 RK0: MR19=303, MR18=1508
7993 23:42:09.310714 CH0_RK0: MR19=0x303, MR18=0x1508, DQSOSC=399, MR23=63, INC=23, DEC=15
7994 23:42:09.310821
7995 23:42:09.313809 ----->DramcWriteLeveling(PI) begin...
7996 23:42:09.313913 ==
7997 23:42:09.316877 Dram Type= 6, Freq= 0, CH_0, rank 1
7998 23:42:09.320485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7999 23:42:09.320584 ==
8000 23:42:09.323765 Write leveling (Byte 0): 33 => 33
8001 23:42:09.327180 Write leveling (Byte 1): 28 => 28
8002 23:42:09.330778 DramcWriteLeveling(PI) end<-----
8003 23:42:09.330875
8004 23:42:09.330971 ==
8005 23:42:09.333988 Dram Type= 6, Freq= 0, CH_0, rank 1
8006 23:42:09.337051 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8007 23:42:09.337153 ==
8008 23:42:09.340656 [Gating] SW mode calibration
8009 23:42:09.347187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8010 23:42:09.354002 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8011 23:42:09.357766 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 23:42:09.360840 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 23:42:09.364137 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8014 23:42:09.370482 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8015 23:42:09.373757 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8016 23:42:09.376988 1 4 20 | B1->B0 | 2828 3434 | 0 1 | (1 1) (1 1)
8017 23:42:09.384071 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8018 23:42:09.387413 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8019 23:42:09.390641 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8020 23:42:09.397506 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8021 23:42:09.401154 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8022 23:42:09.404217 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
8023 23:42:09.410843 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8024 23:42:09.414470 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (1 0) (0 0)
8025 23:42:09.417660 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8026 23:42:09.424130 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8027 23:42:09.427585 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8028 23:42:09.430881 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8029 23:42:09.434428 1 6 8 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8030 23:42:09.441272 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8031 23:42:09.444454 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8032 23:42:09.447694 1 6 20 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
8033 23:42:09.454631 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 23:42:09.457711 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8035 23:42:09.461273 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8036 23:42:09.467792 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 23:42:09.471592 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8038 23:42:09.474783 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8039 23:42:09.481166 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8040 23:42:09.484630 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8041 23:42:09.487734 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8042 23:42:09.494382 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 23:42:09.497940 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 23:42:09.500965 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 23:42:09.507681 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 23:42:09.510981 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 23:42:09.514882 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 23:42:09.517751 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 23:42:09.524249 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 23:42:09.527784 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 23:42:09.530930 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 23:42:09.537430 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8053 23:42:09.540650 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8054 23:42:09.544257 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8055 23:42:09.550949 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8056 23:42:09.554103 Total UI for P1: 0, mck2ui 16
8057 23:42:09.557315 best dqsien dly found for B0: ( 1, 9, 8)
8058 23:42:09.561651 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8059 23:42:09.564339 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 23:42:09.567602 Total UI for P1: 0, mck2ui 16
8061 23:42:09.570775 best dqsien dly found for B1: ( 1, 9, 20)
8062 23:42:09.574700 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8063 23:42:09.577571 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8064 23:42:09.577671
8065 23:42:09.581503 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8066 23:42:09.587873 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8067 23:42:09.587979 [Gating] SW calibration Done
8068 23:42:09.591241 ==
8069 23:42:09.591322 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 23:42:09.597602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 23:42:09.597684 ==
8072 23:42:09.597760 RX Vref Scan: 0
8073 23:42:09.597822
8074 23:42:09.600987 RX Vref 0 -> 0, step: 1
8075 23:42:09.601075
8076 23:42:09.604607 RX Delay 0 -> 252, step: 8
8077 23:42:09.608621 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8078 23:42:09.611667 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8079 23:42:09.614791 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8080 23:42:09.621019 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8081 23:42:09.624463 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8082 23:42:09.627962 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8083 23:42:09.631197 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8084 23:42:09.634765 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8085 23:42:09.637989 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8086 23:42:09.644539 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8087 23:42:09.647694 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8088 23:42:09.651086 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8089 23:42:09.654509 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8090 23:42:09.660873 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8091 23:42:09.664112 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8092 23:42:09.667768 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8093 23:42:09.667871 ==
8094 23:42:09.670870 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 23:42:09.674442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 23:42:09.674542 ==
8097 23:42:09.677791 DQS Delay:
8098 23:42:09.677891 DQS0 = 0, DQS1 = 0
8099 23:42:09.680899 DQM Delay:
8100 23:42:09.681036 DQM0 = 130, DQM1 = 126
8101 23:42:09.681132 DQ Delay:
8102 23:42:09.687671 DQ0 =131, DQ1 =131, DQ2 =123, DQ3 =131
8103 23:42:09.691304 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8104 23:42:09.694142 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =119
8105 23:42:09.697544 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
8106 23:42:09.697645
8107 23:42:09.697734
8108 23:42:09.697823 ==
8109 23:42:09.700684 Dram Type= 6, Freq= 0, CH_0, rank 1
8110 23:42:09.704333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8111 23:42:09.704434 ==
8112 23:42:09.704524
8113 23:42:09.704613
8114 23:42:09.707400 TX Vref Scan disable
8115 23:42:09.711579 == TX Byte 0 ==
8116 23:42:09.714561 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8117 23:42:09.717386 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8118 23:42:09.721238 == TX Byte 1 ==
8119 23:42:09.724298 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8120 23:42:09.727623 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8121 23:42:09.727722 ==
8122 23:42:09.731022 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 23:42:09.734289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 23:42:09.737403 ==
8125 23:42:09.750195
8126 23:42:09.753572 TX Vref early break, caculate TX vref
8127 23:42:09.756829 TX Vref=16, minBit 1, minWin=22, winSum=374
8128 23:42:09.760134 TX Vref=18, minBit 0, minWin=23, winSum=383
8129 23:42:09.763343 TX Vref=20, minBit 0, minWin=23, winSum=390
8130 23:42:09.766638 TX Vref=22, minBit 1, minWin=24, winSum=402
8131 23:42:09.770609 TX Vref=24, minBit 0, minWin=24, winSum=405
8132 23:42:09.776692 TX Vref=26, minBit 0, minWin=25, winSum=419
8133 23:42:09.780064 TX Vref=28, minBit 4, minWin=24, winSum=413
8134 23:42:09.783522 TX Vref=30, minBit 1, minWin=25, winSum=420
8135 23:42:09.786923 TX Vref=32, minBit 0, minWin=24, winSum=413
8136 23:42:09.790171 TX Vref=34, minBit 13, minWin=23, winSum=406
8137 23:42:09.793372 TX Vref=36, minBit 3, minWin=23, winSum=393
8138 23:42:09.800313 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 30
8139 23:42:09.800416
8140 23:42:09.803468 Final TX Range 0 Vref 30
8141 23:42:09.803570
8142 23:42:09.803663 ==
8143 23:42:09.806952 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 23:42:09.810046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 23:42:09.810147 ==
8146 23:42:09.810240
8147 23:42:09.810330
8148 23:42:09.813599 TX Vref Scan disable
8149 23:42:09.820166 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8150 23:42:09.820269 == TX Byte 0 ==
8151 23:42:09.823680 u2DelayCellOfst[0]=14 cells (4 PI)
8152 23:42:09.826804 u2DelayCellOfst[1]=17 cells (5 PI)
8153 23:42:09.830324 u2DelayCellOfst[2]=10 cells (3 PI)
8154 23:42:09.833829 u2DelayCellOfst[3]=10 cells (3 PI)
8155 23:42:09.836828 u2DelayCellOfst[4]=10 cells (3 PI)
8156 23:42:09.840721 u2DelayCellOfst[5]=0 cells (0 PI)
8157 23:42:09.844229 u2DelayCellOfst[6]=17 cells (5 PI)
8158 23:42:09.846781 u2DelayCellOfst[7]=17 cells (5 PI)
8159 23:42:09.850186 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8160 23:42:09.853981 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8161 23:42:09.857478 == TX Byte 1 ==
8162 23:42:09.857578 u2DelayCellOfst[8]=0 cells (0 PI)
8163 23:42:09.860197 u2DelayCellOfst[9]=0 cells (0 PI)
8164 23:42:09.863571 u2DelayCellOfst[10]=7 cells (2 PI)
8165 23:42:09.866948 u2DelayCellOfst[11]=3 cells (1 PI)
8166 23:42:09.870237 u2DelayCellOfst[12]=14 cells (4 PI)
8167 23:42:09.873654 u2DelayCellOfst[13]=10 cells (3 PI)
8168 23:42:09.877260 u2DelayCellOfst[14]=14 cells (4 PI)
8169 23:42:09.880114 u2DelayCellOfst[15]=14 cells (4 PI)
8170 23:42:09.884284 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8171 23:42:09.890462 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8172 23:42:09.890568 DramC Write-DBI on
8173 23:42:09.890696 ==
8174 23:42:09.893643 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 23:42:09.897112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 23:42:09.897211 ==
8177 23:42:09.897303
8178 23:42:09.900454
8179 23:42:09.900555 TX Vref Scan disable
8180 23:42:09.903839 == TX Byte 0 ==
8181 23:42:09.907716 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8182 23:42:09.910675 == TX Byte 1 ==
8183 23:42:09.913749 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8184 23:42:09.913852 DramC Write-DBI off
8185 23:42:09.913944
8186 23:42:09.917242 [DATLAT]
8187 23:42:09.917341 Freq=1600, CH0 RK1
8188 23:42:09.917434
8189 23:42:09.920842 DATLAT Default: 0xf
8190 23:42:09.920941 0, 0xFFFF, sum = 0
8191 23:42:09.924332 1, 0xFFFF, sum = 0
8192 23:42:09.924434 2, 0xFFFF, sum = 0
8193 23:42:09.927798 3, 0xFFFF, sum = 0
8194 23:42:09.927898 4, 0xFFFF, sum = 0
8195 23:42:09.930463 5, 0xFFFF, sum = 0
8196 23:42:09.930564 6, 0xFFFF, sum = 0
8197 23:42:09.933674 7, 0xFFFF, sum = 0
8198 23:42:09.933776 8, 0xFFFF, sum = 0
8199 23:42:09.937180 9, 0xFFFF, sum = 0
8200 23:42:09.940629 10, 0xFFFF, sum = 0
8201 23:42:09.940731 11, 0xFFFF, sum = 0
8202 23:42:09.944060 12, 0xFFFF, sum = 0
8203 23:42:09.944164 13, 0xFFFF, sum = 0
8204 23:42:09.947468 14, 0x0, sum = 1
8205 23:42:09.947570 15, 0x0, sum = 2
8206 23:42:09.950605 16, 0x0, sum = 3
8207 23:42:09.950704 17, 0x0, sum = 4
8208 23:42:09.950800 best_step = 15
8209 23:42:09.953595
8210 23:42:09.953698 ==
8211 23:42:09.957416 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 23:42:09.960762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 23:42:09.960866 ==
8214 23:42:09.960960 RX Vref Scan: 0
8215 23:42:09.961092
8216 23:42:09.963691 RX Vref 0 -> 0, step: 1
8217 23:42:09.963797
8218 23:42:09.966993 RX Delay 11 -> 252, step: 4
8219 23:42:09.970122 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8220 23:42:09.977078 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8221 23:42:09.980601 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8222 23:42:09.983566 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8223 23:42:09.986850 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8224 23:42:09.990099 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8225 23:42:09.996802 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8226 23:42:10.000482 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8227 23:42:10.003330 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8228 23:42:10.006575 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8229 23:42:10.010190 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8230 23:42:10.016986 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8231 23:42:10.020025 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8232 23:42:10.023244 iDelay=191, Bit 13, Center 128 (75 ~ 182) 108
8233 23:42:10.026895 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8234 23:42:10.030302 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8235 23:42:10.033588 ==
8236 23:42:10.033686 Dram Type= 6, Freq= 0, CH_0, rank 1
8237 23:42:10.040912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8238 23:42:10.041034 ==
8239 23:42:10.041100 DQS Delay:
8240 23:42:10.043688 DQS0 = 0, DQS1 = 0
8241 23:42:10.043785 DQM Delay:
8242 23:42:10.046897 DQM0 = 126, DQM1 = 122
8243 23:42:10.046998 DQ Delay:
8244 23:42:10.049857 DQ0 =124, DQ1 =130, DQ2 =122, DQ3 =126
8245 23:42:10.053740 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =136
8246 23:42:10.056748 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =118
8247 23:42:10.060190 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8248 23:42:10.060286
8249 23:42:10.060383
8250 23:42:10.060468
8251 23:42:10.063494 [DramC_TX_OE_Calibration] TA2
8252 23:42:10.066586 Original DQ_B0 (3 6) =30, OEN = 27
8253 23:42:10.069615 Original DQ_B1 (3 6) =30, OEN = 27
8254 23:42:10.073833 24, 0x0, End_B0=24 End_B1=24
8255 23:42:10.076919 25, 0x0, End_B0=25 End_B1=25
8256 23:42:10.077048 26, 0x0, End_B0=26 End_B1=26
8257 23:42:10.080133 27, 0x0, End_B0=27 End_B1=27
8258 23:42:10.083457 28, 0x0, End_B0=28 End_B1=28
8259 23:42:10.086633 29, 0x0, End_B0=29 End_B1=29
8260 23:42:10.086707 30, 0x0, End_B0=30 End_B1=30
8261 23:42:10.089821 31, 0x4141, End_B0=30 End_B1=30
8262 23:42:10.093440 Byte0 end_step=30 best_step=27
8263 23:42:10.096476 Byte1 end_step=30 best_step=27
8264 23:42:10.099722 Byte0 TX OE(2T, 0.5T) = (3, 3)
8265 23:42:10.103260 Byte1 TX OE(2T, 0.5T) = (3, 3)
8266 23:42:10.103364
8267 23:42:10.103452
8268 23:42:10.110017 [DQSOSCAuto] RK1, (LSB)MR18= 0x150a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8269 23:42:10.113126 CH0 RK1: MR19=303, MR18=150A
8270 23:42:10.119631 CH0_RK1: MR19=0x303, MR18=0x150A, DQSOSC=399, MR23=63, INC=23, DEC=15
8271 23:42:10.123073 [RxdqsGatingPostProcess] freq 1600
8272 23:42:10.126357 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8273 23:42:10.130081 best DQS0 dly(2T, 0.5T) = (1, 1)
8274 23:42:10.133455 best DQS1 dly(2T, 0.5T) = (1, 1)
8275 23:42:10.136917 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8276 23:42:10.140088 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8277 23:42:10.143765 best DQS0 dly(2T, 0.5T) = (1, 1)
8278 23:42:10.146848 best DQS1 dly(2T, 0.5T) = (1, 1)
8279 23:42:10.150023 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8280 23:42:10.153236 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8281 23:42:10.156527 Pre-setting of DQS Precalculation
8282 23:42:10.159955 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8283 23:42:10.160037 ==
8284 23:42:10.163093 Dram Type= 6, Freq= 0, CH_1, rank 0
8285 23:42:10.167002 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8286 23:42:10.167099 ==
8287 23:42:10.173574 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8288 23:42:10.176631 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8289 23:42:10.183774 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8290 23:42:10.187123 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8291 23:42:10.196946 [CA 0] Center 42 (14~71) winsize 58
8292 23:42:10.200171 [CA 1] Center 42 (13~71) winsize 59
8293 23:42:10.203505 [CA 2] Center 37 (9~66) winsize 58
8294 23:42:10.207071 [CA 3] Center 36 (7~66) winsize 60
8295 23:42:10.210244 [CA 4] Center 37 (7~67) winsize 61
8296 23:42:10.213654 [CA 5] Center 36 (7~66) winsize 60
8297 23:42:10.213728
8298 23:42:10.216453 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8299 23:42:10.216552
8300 23:42:10.220162 [CATrainingPosCal] consider 1 rank data
8301 23:42:10.223085 u2DelayCellTimex100 = 275/100 ps
8302 23:42:10.226587 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8303 23:42:10.233244 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8304 23:42:10.236892 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8305 23:42:10.239927 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8306 23:42:10.243268 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8307 23:42:10.246442 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8308 23:42:10.246512
8309 23:42:10.249957 CA PerBit enable=1, Macro0, CA PI delay=36
8310 23:42:10.250051
8311 23:42:10.253611 [CBTSetCACLKResult] CA Dly = 36
8312 23:42:10.253691 CS Dly: 9 (0~40)
8313 23:42:10.260307 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8314 23:42:10.263636 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8315 23:42:10.263710 ==
8316 23:42:10.266979 Dram Type= 6, Freq= 0, CH_1, rank 1
8317 23:42:10.270355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 23:42:10.270435 ==
8319 23:42:10.276444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8320 23:42:10.280221 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8321 23:42:10.286708 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8322 23:42:10.290560 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8323 23:42:10.299912 [CA 0] Center 43 (14~72) winsize 59
8324 23:42:10.303285 [CA 1] Center 43 (14~72) winsize 59
8325 23:42:10.306703 [CA 2] Center 37 (8~67) winsize 60
8326 23:42:10.309800 [CA 3] Center 37 (8~67) winsize 60
8327 23:42:10.313246 [CA 4] Center 38 (8~68) winsize 61
8328 23:42:10.316584 [CA 5] Center 36 (7~66) winsize 60
8329 23:42:10.316654
8330 23:42:10.319803 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8331 23:42:10.319899
8332 23:42:10.322940 [CATrainingPosCal] consider 2 rank data
8333 23:42:10.326732 u2DelayCellTimex100 = 275/100 ps
8334 23:42:10.330049 CA0 delay=42 (14~71),Diff = 6 PI (21 cell)
8335 23:42:10.336899 CA1 delay=42 (14~71),Diff = 6 PI (21 cell)
8336 23:42:10.340103 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8337 23:42:10.343546 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8338 23:42:10.346739 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8339 23:42:10.350018 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8340 23:42:10.350098
8341 23:42:10.352958 CA PerBit enable=1, Macro0, CA PI delay=36
8342 23:42:10.353059
8343 23:42:10.356395 [CBTSetCACLKResult] CA Dly = 36
8344 23:42:10.356474 CS Dly: 10 (0~43)
8345 23:42:10.363456 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8346 23:42:10.366752 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8347 23:42:10.366858
8348 23:42:10.369924 ----->DramcWriteLeveling(PI) begin...
8349 23:42:10.370026 ==
8350 23:42:10.373578 Dram Type= 6, Freq= 0, CH_1, rank 0
8351 23:42:10.376543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8352 23:42:10.376646 ==
8353 23:42:10.380287 Write leveling (Byte 0): 25 => 25
8354 23:42:10.383174 Write leveling (Byte 1): 29 => 29
8355 23:42:10.386649 DramcWriteLeveling(PI) end<-----
8356 23:42:10.386750
8357 23:42:10.386843 ==
8358 23:42:10.389792 Dram Type= 6, Freq= 0, CH_1, rank 0
8359 23:42:10.396725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 23:42:10.396829 ==
8361 23:42:10.396922 [Gating] SW mode calibration
8362 23:42:10.406658 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8363 23:42:10.409849 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8364 23:42:10.413240 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 23:42:10.419638 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8366 23:42:10.422927 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8367 23:42:10.426472 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8368 23:42:10.433066 1 4 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8369 23:42:10.436544 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 23:42:10.439898 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 23:42:10.446806 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 23:42:10.449776 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8373 23:42:10.453583 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 23:42:10.460073 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 23:42:10.463477 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8376 23:42:10.466973 1 5 16 | B1->B0 | 2e2e 3232 | 1 0 | (1 0) (0 1)
8377 23:42:10.473259 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8378 23:42:10.476986 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 23:42:10.479683 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 23:42:10.482950 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 23:42:10.490219 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 23:42:10.493069 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 23:42:10.496618 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 23:42:10.503138 1 6 16 | B1->B0 | 3c3c 3838 | 0 0 | (0 0) (0 0)
8385 23:42:10.506471 1 6 20 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8386 23:42:10.509740 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 23:42:10.516563 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 23:42:10.519702 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 23:42:10.523212 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 23:42:10.529862 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 23:42:10.532932 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 23:42:10.536343 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8393 23:42:10.543222 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8394 23:42:10.546216 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 23:42:10.549961 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 23:42:10.556406 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 23:42:10.559468 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 23:42:10.563566 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 23:42:10.569802 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 23:42:10.572863 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 23:42:10.576336 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 23:42:10.583226 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 23:42:10.586322 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 23:42:10.589706 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 23:42:10.596108 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 23:42:10.599431 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 23:42:10.602807 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 23:42:10.609408 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8409 23:42:10.612910 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 23:42:10.616102 Total UI for P1: 0, mck2ui 16
8411 23:42:10.619672 best dqsien dly found for B0: ( 1, 9, 16)
8412 23:42:10.622740 Total UI for P1: 0, mck2ui 16
8413 23:42:10.626608 best dqsien dly found for B1: ( 1, 9, 16)
8414 23:42:10.629375 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8415 23:42:10.632833 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8416 23:42:10.632930
8417 23:42:10.635976 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8418 23:42:10.639595 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8419 23:42:10.642787 [Gating] SW calibration Done
8420 23:42:10.642890 ==
8421 23:42:10.646111 Dram Type= 6, Freq= 0, CH_1, rank 0
8422 23:42:10.649404 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8423 23:42:10.649484 ==
8424 23:42:10.652774 RX Vref Scan: 0
8425 23:42:10.652854
8426 23:42:10.656081 RX Vref 0 -> 0, step: 1
8427 23:42:10.656159
8428 23:42:10.656221 RX Delay 0 -> 252, step: 8
8429 23:42:10.663103 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8430 23:42:10.665963 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8431 23:42:10.669597 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8432 23:42:10.672682 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8433 23:42:10.676256 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8434 23:42:10.679486 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8435 23:42:10.686273 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8436 23:42:10.689563 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8437 23:42:10.693007 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8438 23:42:10.696588 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8439 23:42:10.700081 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8440 23:42:10.706119 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8441 23:42:10.709753 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8442 23:42:10.713064 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8443 23:42:10.716243 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8444 23:42:10.719792 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8445 23:42:10.723043 ==
8446 23:42:10.726367 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 23:42:10.729308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 23:42:10.729388 ==
8449 23:42:10.729452 DQS Delay:
8450 23:42:10.732715 DQS0 = 0, DQS1 = 0
8451 23:42:10.732795 DQM Delay:
8452 23:42:10.736434 DQM0 = 135, DQM1 = 127
8453 23:42:10.736513 DQ Delay:
8454 23:42:10.739417 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8455 23:42:10.742690 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =131
8456 23:42:10.746392 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8457 23:42:10.749295 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8458 23:42:10.749404
8459 23:42:10.749486
8460 23:42:10.749583 ==
8461 23:42:10.752823 Dram Type= 6, Freq= 0, CH_1, rank 0
8462 23:42:10.759443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8463 23:42:10.759520 ==
8464 23:42:10.759603
8465 23:42:10.759678
8466 23:42:10.759752 TX Vref Scan disable
8467 23:42:10.763133 == TX Byte 0 ==
8468 23:42:10.766755 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8469 23:42:10.773179 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8470 23:42:10.773258 == TX Byte 1 ==
8471 23:42:10.776474 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8472 23:42:10.783198 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8473 23:42:10.783279 ==
8474 23:42:10.786249 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 23:42:10.789324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 23:42:10.789407 ==
8477 23:42:10.802415
8478 23:42:10.805348 TX Vref early break, caculate TX vref
8479 23:42:10.808489 TX Vref=16, minBit 0, minWin=21, winSum=365
8480 23:42:10.812006 TX Vref=18, minBit 8, minWin=20, winSum=371
8481 23:42:10.815801 TX Vref=20, minBit 8, minWin=22, winSum=384
8482 23:42:10.819244 TX Vref=22, minBit 8, minWin=22, winSum=391
8483 23:42:10.822470 TX Vref=24, minBit 8, minWin=23, winSum=401
8484 23:42:10.828754 TX Vref=26, minBit 8, minWin=24, winSum=415
8485 23:42:10.832056 TX Vref=28, minBit 8, minWin=25, winSum=419
8486 23:42:10.835676 TX Vref=30, minBit 8, minWin=24, winSum=416
8487 23:42:10.839129 TX Vref=32, minBit 8, minWin=24, winSum=408
8488 23:42:10.842064 TX Vref=34, minBit 8, minWin=23, winSum=395
8489 23:42:10.848836 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 28
8490 23:42:10.848941
8491 23:42:10.852087 Final TX Range 0 Vref 28
8492 23:42:10.852166
8493 23:42:10.852229 ==
8494 23:42:10.855737 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 23:42:10.858947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 23:42:10.859027 ==
8497 23:42:10.859091
8498 23:42:10.859149
8499 23:42:10.862559 TX Vref Scan disable
8500 23:42:10.865697 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8501 23:42:10.869062 == TX Byte 0 ==
8502 23:42:10.872859 u2DelayCellOfst[0]=17 cells (5 PI)
8503 23:42:10.875815 u2DelayCellOfst[1]=10 cells (3 PI)
8504 23:42:10.878874 u2DelayCellOfst[2]=0 cells (0 PI)
8505 23:42:10.882414 u2DelayCellOfst[3]=7 cells (2 PI)
8506 23:42:10.882497 u2DelayCellOfst[4]=7 cells (2 PI)
8507 23:42:10.886060 u2DelayCellOfst[5]=17 cells (5 PI)
8508 23:42:10.889267 u2DelayCellOfst[6]=17 cells (5 PI)
8509 23:42:10.892366 u2DelayCellOfst[7]=3 cells (1 PI)
8510 23:42:10.899268 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8511 23:42:10.902340 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8512 23:42:10.902423 == TX Byte 1 ==
8513 23:42:10.905595 u2DelayCellOfst[8]=0 cells (0 PI)
8514 23:42:10.909267 u2DelayCellOfst[9]=7 cells (2 PI)
8515 23:42:10.912658 u2DelayCellOfst[10]=10 cells (3 PI)
8516 23:42:10.915660 u2DelayCellOfst[11]=7 cells (2 PI)
8517 23:42:10.919373 u2DelayCellOfst[12]=14 cells (4 PI)
8518 23:42:10.922722 u2DelayCellOfst[13]=17 cells (5 PI)
8519 23:42:10.926083 u2DelayCellOfst[14]=17 cells (5 PI)
8520 23:42:10.929393 u2DelayCellOfst[15]=17 cells (5 PI)
8521 23:42:10.932697 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8522 23:42:10.935876 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8523 23:42:10.939409 DramC Write-DBI on
8524 23:42:10.939488 ==
8525 23:42:10.942545 Dram Type= 6, Freq= 0, CH_1, rank 0
8526 23:42:10.946112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8527 23:42:10.946192 ==
8528 23:42:10.946255
8529 23:42:10.946313
8530 23:42:10.949201 TX Vref Scan disable
8531 23:42:10.952467 == TX Byte 0 ==
8532 23:42:10.956066 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8533 23:42:10.956146 == TX Byte 1 ==
8534 23:42:10.962523 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8535 23:42:10.962606 DramC Write-DBI off
8536 23:42:10.962668
8537 23:42:10.962726 [DATLAT]
8538 23:42:10.966149 Freq=1600, CH1 RK0
8539 23:42:10.966229
8540 23:42:10.969318 DATLAT Default: 0xf
8541 23:42:10.969398 0, 0xFFFF, sum = 0
8542 23:42:10.972859 1, 0xFFFF, sum = 0
8543 23:42:10.972940 2, 0xFFFF, sum = 0
8544 23:42:10.975839 3, 0xFFFF, sum = 0
8545 23:42:10.975920 4, 0xFFFF, sum = 0
8546 23:42:10.979156 5, 0xFFFF, sum = 0
8547 23:42:10.979262 6, 0xFFFF, sum = 0
8548 23:42:10.982849 7, 0xFFFF, sum = 0
8549 23:42:10.982956 8, 0xFFFF, sum = 0
8550 23:42:10.985912 9, 0xFFFF, sum = 0
8551 23:42:10.985993 10, 0xFFFF, sum = 0
8552 23:42:10.989100 11, 0xFFFF, sum = 0
8553 23:42:10.989181 12, 0xFFFF, sum = 0
8554 23:42:10.992693 13, 0xFFFF, sum = 0
8555 23:42:10.992799 14, 0x0, sum = 1
8556 23:42:10.995856 15, 0x0, sum = 2
8557 23:42:10.995974 16, 0x0, sum = 3
8558 23:42:10.999573 17, 0x0, sum = 4
8559 23:42:10.999680 best_step = 15
8560 23:42:10.999770
8561 23:42:10.999855 ==
8562 23:42:11.002898 Dram Type= 6, Freq= 0, CH_1, rank 0
8563 23:42:11.009185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8564 23:42:11.009265 ==
8565 23:42:11.009336 RX Vref Scan: 1
8566 23:42:11.009414
8567 23:42:11.012518 Set Vref Range= 24 -> 127
8568 23:42:11.012596
8569 23:42:11.015771 RX Vref 24 -> 127, step: 1
8570 23:42:11.015863
8571 23:42:11.015934 RX Delay 19 -> 252, step: 4
8572 23:42:11.016045
8573 23:42:11.019357 Set Vref, RX VrefLevel [Byte0]: 24
8574 23:42:11.022681 [Byte1]: 24
8575 23:42:11.026562
8576 23:42:11.026641 Set Vref, RX VrefLevel [Byte0]: 25
8577 23:42:11.029611 [Byte1]: 25
8578 23:42:11.034147
8579 23:42:11.034225 Set Vref, RX VrefLevel [Byte0]: 26
8580 23:42:11.037228 [Byte1]: 26
8581 23:42:11.041803
8582 23:42:11.041881 Set Vref, RX VrefLevel [Byte0]: 27
8583 23:42:11.044918 [Byte1]: 27
8584 23:42:11.049378
8585 23:42:11.049456 Set Vref, RX VrefLevel [Byte0]: 28
8586 23:42:11.052810 [Byte1]: 28
8587 23:42:11.056660
8588 23:42:11.056738 Set Vref, RX VrefLevel [Byte0]: 29
8589 23:42:11.060303 [Byte1]: 29
8590 23:42:11.064616
8591 23:42:11.064694 Set Vref, RX VrefLevel [Byte0]: 30
8592 23:42:11.067535 [Byte1]: 30
8593 23:42:11.072020
8594 23:42:11.072099 Set Vref, RX VrefLevel [Byte0]: 31
8595 23:42:11.075202 [Byte1]: 31
8596 23:42:11.079478
8597 23:42:11.079586 Set Vref, RX VrefLevel [Byte0]: 32
8598 23:42:11.083271 [Byte1]: 32
8599 23:42:11.087282
8600 23:42:11.087361 Set Vref, RX VrefLevel [Byte0]: 33
8601 23:42:11.090796 [Byte1]: 33
8602 23:42:11.095039
8603 23:42:11.095117 Set Vref, RX VrefLevel [Byte0]: 34
8604 23:42:11.098277 [Byte1]: 34
8605 23:42:11.102170
8606 23:42:11.102248 Set Vref, RX VrefLevel [Byte0]: 35
8607 23:42:11.105901 [Byte1]: 35
8608 23:42:11.109734
8609 23:42:11.109813 Set Vref, RX VrefLevel [Byte0]: 36
8610 23:42:11.113467 [Byte1]: 36
8611 23:42:11.117553
8612 23:42:11.117635 Set Vref, RX VrefLevel [Byte0]: 37
8613 23:42:11.120785 [Byte1]: 37
8614 23:42:11.125122
8615 23:42:11.125201 Set Vref, RX VrefLevel [Byte0]: 38
8616 23:42:11.128650 [Byte1]: 38
8617 23:42:11.132432
8618 23:42:11.132510 Set Vref, RX VrefLevel [Byte0]: 39
8619 23:42:11.135998 [Byte1]: 39
8620 23:42:11.139946
8621 23:42:11.140029 Set Vref, RX VrefLevel [Byte0]: 40
8622 23:42:11.143655 [Byte1]: 40
8623 23:42:11.147697
8624 23:42:11.147780 Set Vref, RX VrefLevel [Byte0]: 41
8625 23:42:11.150846 [Byte1]: 41
8626 23:42:11.155230
8627 23:42:11.158661 Set Vref, RX VrefLevel [Byte0]: 42
8628 23:42:11.158740 [Byte1]: 42
8629 23:42:11.163421
8630 23:42:11.163500 Set Vref, RX VrefLevel [Byte0]: 43
8631 23:42:11.166532 [Byte1]: 43
8632 23:42:11.170125
8633 23:42:11.170204 Set Vref, RX VrefLevel [Byte0]: 44
8634 23:42:11.173541 [Byte1]: 44
8635 23:42:11.178064
8636 23:42:11.178143 Set Vref, RX VrefLevel [Byte0]: 45
8637 23:42:11.181308 [Byte1]: 45
8638 23:42:11.185658
8639 23:42:11.185736 Set Vref, RX VrefLevel [Byte0]: 46
8640 23:42:11.188849 [Byte1]: 46
8641 23:42:11.193091
8642 23:42:11.193170 Set Vref, RX VrefLevel [Byte0]: 47
8643 23:42:11.196240 [Byte1]: 47
8644 23:42:11.200692
8645 23:42:11.200797 Set Vref, RX VrefLevel [Byte0]: 48
8646 23:42:11.204007 [Byte1]: 48
8647 23:42:11.208334
8648 23:42:11.208426 Set Vref, RX VrefLevel [Byte0]: 49
8649 23:42:11.211507 [Byte1]: 49
8650 23:42:11.216008
8651 23:42:11.216087 Set Vref, RX VrefLevel [Byte0]: 50
8652 23:42:11.219472 [Byte1]: 50
8653 23:42:11.223237
8654 23:42:11.223316 Set Vref, RX VrefLevel [Byte0]: 51
8655 23:42:11.226660 [Byte1]: 51
8656 23:42:11.231157
8657 23:42:11.231235 Set Vref, RX VrefLevel [Byte0]: 52
8658 23:42:11.234274 [Byte1]: 52
8659 23:42:11.238517
8660 23:42:11.238596 Set Vref, RX VrefLevel [Byte0]: 53
8661 23:42:11.241729 [Byte1]: 53
8662 23:42:11.246163
8663 23:42:11.246241 Set Vref, RX VrefLevel [Byte0]: 54
8664 23:42:11.249711 [Byte1]: 54
8665 23:42:11.253540
8666 23:42:11.253618 Set Vref, RX VrefLevel [Byte0]: 55
8667 23:42:11.257127 [Byte1]: 55
8668 23:42:11.261011
8669 23:42:11.261103 Set Vref, RX VrefLevel [Byte0]: 56
8670 23:42:11.264639 [Byte1]: 56
8671 23:42:11.268908
8672 23:42:11.269043 Set Vref, RX VrefLevel [Byte0]: 57
8673 23:42:11.271987 [Byte1]: 57
8674 23:42:11.276617
8675 23:42:11.276700 Set Vref, RX VrefLevel [Byte0]: 58
8676 23:42:11.279762 [Byte1]: 58
8677 23:42:11.283985
8678 23:42:11.284064 Set Vref, RX VrefLevel [Byte0]: 59
8679 23:42:11.287512 [Byte1]: 59
8680 23:42:11.291467
8681 23:42:11.291563 Set Vref, RX VrefLevel [Byte0]: 60
8682 23:42:11.295116 [Byte1]: 60
8683 23:42:11.298903
8684 23:42:11.298981 Set Vref, RX VrefLevel [Byte0]: 61
8685 23:42:11.302636 [Byte1]: 61
8686 23:42:11.306783
8687 23:42:11.306861 Set Vref, RX VrefLevel [Byte0]: 62
8688 23:42:11.309802 [Byte1]: 62
8689 23:42:11.314279
8690 23:42:11.314357 Set Vref, RX VrefLevel [Byte0]: 63
8691 23:42:11.317736 [Byte1]: 63
8692 23:42:11.322020
8693 23:42:11.322099 Set Vref, RX VrefLevel [Byte0]: 64
8694 23:42:11.325578 [Byte1]: 64
8695 23:42:11.329412
8696 23:42:11.329516 Set Vref, RX VrefLevel [Byte0]: 65
8697 23:42:11.332760 [Byte1]: 65
8698 23:42:11.337110
8699 23:42:11.337188 Set Vref, RX VrefLevel [Byte0]: 66
8700 23:42:11.340071 [Byte1]: 66
8701 23:42:11.344955
8702 23:42:11.345075 Set Vref, RX VrefLevel [Byte0]: 67
8703 23:42:11.348029 [Byte1]: 67
8704 23:42:11.351889
8705 23:42:11.351968 Set Vref, RX VrefLevel [Byte0]: 68
8706 23:42:11.355745 [Byte1]: 68
8707 23:42:11.359689
8708 23:42:11.359768 Set Vref, RX VrefLevel [Byte0]: 69
8709 23:42:11.363270 [Byte1]: 69
8710 23:42:11.367802
8711 23:42:11.367881 Set Vref, RX VrefLevel [Byte0]: 70
8712 23:42:11.370932 [Byte1]: 70
8713 23:42:11.374624
8714 23:42:11.374703 Set Vref, RX VrefLevel [Byte0]: 71
8715 23:42:11.377999 [Byte1]: 71
8716 23:42:11.382346
8717 23:42:11.382425 Set Vref, RX VrefLevel [Byte0]: 72
8718 23:42:11.385931 [Byte1]: 72
8719 23:42:11.389775
8720 23:42:11.389853 Set Vref, RX VrefLevel [Byte0]: 73
8721 23:42:11.393626 [Byte1]: 73
8722 23:42:11.397456
8723 23:42:11.397534 Set Vref, RX VrefLevel [Byte0]: 74
8724 23:42:11.400876 [Byte1]: 74
8725 23:42:11.405341
8726 23:42:11.405419 Final RX Vref Byte 0 = 64 to rank0
8727 23:42:11.408607 Final RX Vref Byte 1 = 54 to rank0
8728 23:42:11.411831 Final RX Vref Byte 0 = 64 to rank1
8729 23:42:11.415495 Final RX Vref Byte 1 = 54 to rank1==
8730 23:42:11.418797 Dram Type= 6, Freq= 0, CH_1, rank 0
8731 23:42:11.424935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8732 23:42:11.425062 ==
8733 23:42:11.425125 DQS Delay:
8734 23:42:11.425184 DQS0 = 0, DQS1 = 0
8735 23:42:11.428516 DQM Delay:
8736 23:42:11.428602 DQM0 = 131, DQM1 = 124
8737 23:42:11.432511 DQ Delay:
8738 23:42:11.434884 DQ0 =138, DQ1 =126, DQ2 =118, DQ3 =130
8739 23:42:11.438100 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8740 23:42:11.441666 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8741 23:42:11.444847 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8742 23:42:11.444982
8743 23:42:11.445065
8744 23:42:11.445124
8745 23:42:11.448798 [DramC_TX_OE_Calibration] TA2
8746 23:42:11.451902 Original DQ_B0 (3 6) =30, OEN = 27
8747 23:42:11.454944 Original DQ_B1 (3 6) =30, OEN = 27
8748 23:42:11.458430 24, 0x0, End_B0=24 End_B1=24
8749 23:42:11.458510 25, 0x0, End_B0=25 End_B1=25
8750 23:42:11.462256 26, 0x0, End_B0=26 End_B1=26
8751 23:42:11.465002 27, 0x0, End_B0=27 End_B1=27
8752 23:42:11.468360 28, 0x0, End_B0=28 End_B1=28
8753 23:42:11.468440 29, 0x0, End_B0=29 End_B1=29
8754 23:42:11.471751 30, 0x0, End_B0=30 End_B1=30
8755 23:42:11.475050 31, 0x4545, End_B0=30 End_B1=30
8756 23:42:11.478818 Byte0 end_step=30 best_step=27
8757 23:42:11.482022 Byte1 end_step=30 best_step=27
8758 23:42:11.485228 Byte0 TX OE(2T, 0.5T) = (3, 3)
8759 23:42:11.485329 Byte1 TX OE(2T, 0.5T) = (3, 3)
8760 23:42:11.485393
8761 23:42:11.485452
8762 23:42:11.495017 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fd, (MSB)MR19= 0x302, tDQSOscB0 = 411 ps tDQSOscB1 = 400 ps
8763 23:42:11.498359 CH1 RK0: MR19=302, MR18=13FD
8764 23:42:11.505462 CH1_RK0: MR19=0x302, MR18=0x13FD, DQSOSC=400, MR23=63, INC=23, DEC=15
8765 23:42:11.505542
8766 23:42:11.508414 ----->DramcWriteLeveling(PI) begin...
8767 23:42:11.508506 ==
8768 23:42:11.512252 Dram Type= 6, Freq= 0, CH_1, rank 1
8769 23:42:11.514961 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8770 23:42:11.515044 ==
8771 23:42:11.518373 Write leveling (Byte 0): 27 => 27
8772 23:42:11.521582 Write leveling (Byte 1): 27 => 27
8773 23:42:11.524922 DramcWriteLeveling(PI) end<-----
8774 23:42:11.525062
8775 23:42:11.525155 ==
8776 23:42:11.528287 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 23:42:11.532032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8778 23:42:11.532113 ==
8779 23:42:11.535426 [Gating] SW mode calibration
8780 23:42:11.542049 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8781 23:42:11.548287 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8782 23:42:11.552105 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 23:42:11.555181 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 23:42:11.561948 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 23:42:11.565585 1 4 12 | B1->B0 | 2323 3434 | 1 0 | (0 0) (0 0)
8786 23:42:11.568703 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8787 23:42:11.571773 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8788 23:42:11.578847 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8789 23:42:11.581894 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8790 23:42:11.585175 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 23:42:11.592289 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 23:42:11.595286 1 5 8 | B1->B0 | 3434 2c2c | 1 1 | (1 1) (1 0)
8793 23:42:11.598360 1 5 12 | B1->B0 | 2e2e 2525 | 1 1 | (1 0) (1 0)
8794 23:42:11.605343 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8795 23:42:11.608386 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8796 23:42:11.611740 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8797 23:42:11.618277 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8798 23:42:11.621856 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 23:42:11.625314 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8800 23:42:11.632050 1 6 8 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8801 23:42:11.634886 1 6 12 | B1->B0 | 3131 4444 | 0 0 | (0 0) (0 0)
8802 23:42:11.638933 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8803 23:42:11.645406 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8804 23:42:11.648757 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 23:42:11.651514 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8806 23:42:11.658531 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 23:42:11.661539 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 23:42:11.665198 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8809 23:42:11.671809 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8810 23:42:11.675448 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8811 23:42:11.678635 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 23:42:11.684997 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 23:42:11.688133 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 23:42:11.691496 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 23:42:11.698546 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 23:42:11.701850 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 23:42:11.704945 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 23:42:11.708033 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 23:42:11.715043 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 23:42:11.718540 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 23:42:11.721501 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 23:42:11.728117 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 23:42:11.731645 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 23:42:11.734836 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8825 23:42:11.741620 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8826 23:42:11.744889 Total UI for P1: 0, mck2ui 16
8827 23:42:11.748386 best dqsien dly found for B0: ( 1, 9, 8)
8828 23:42:11.751598 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8829 23:42:11.754932 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 23:42:11.758420 Total UI for P1: 0, mck2ui 16
8831 23:42:11.761709 best dqsien dly found for B1: ( 1, 9, 16)
8832 23:42:11.764637 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8833 23:42:11.768556 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8834 23:42:11.768661
8835 23:42:11.774879 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8836 23:42:11.778450 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8837 23:42:11.778529 [Gating] SW calibration Done
8838 23:42:11.781403 ==
8839 23:42:11.785477 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 23:42:11.788325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 23:42:11.788405 ==
8842 23:42:11.788469 RX Vref Scan: 0
8843 23:42:11.788528
8844 23:42:11.791651 RX Vref 0 -> 0, step: 1
8845 23:42:11.791731
8846 23:42:11.795245 RX Delay 0 -> 252, step: 8
8847 23:42:11.798542 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8848 23:42:11.802023 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8849 23:42:11.805476 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8850 23:42:11.811875 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8851 23:42:11.815393 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8852 23:42:11.818526 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8853 23:42:11.822089 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8854 23:42:11.824912 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8855 23:42:11.828296 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8856 23:42:11.834911 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8857 23:42:11.838753 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8858 23:42:11.841630 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8859 23:42:11.845368 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8860 23:42:11.848531 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8861 23:42:11.855116 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8862 23:42:11.858483 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8863 23:42:11.858580 ==
8864 23:42:11.861706 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 23:42:11.864946 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 23:42:11.865075 ==
8867 23:42:11.868624 DQS Delay:
8868 23:42:11.868700 DQS0 = 0, DQS1 = 0
8869 23:42:11.868796 DQM Delay:
8870 23:42:11.871557 DQM0 = 133, DQM1 = 128
8871 23:42:11.871654 DQ Delay:
8872 23:42:11.875154 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8873 23:42:11.878636 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8874 23:42:11.885281 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8875 23:42:11.888397 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8876 23:42:11.888480
8877 23:42:11.888563
8878 23:42:11.888642 ==
8879 23:42:11.891867 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 23:42:11.895524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 23:42:11.895608 ==
8882 23:42:11.895692
8883 23:42:11.895771
8884 23:42:11.898356 TX Vref Scan disable
8885 23:42:11.898439 == TX Byte 0 ==
8886 23:42:11.905116 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8887 23:42:11.908799 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8888 23:42:11.908883 == TX Byte 1 ==
8889 23:42:11.915121 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8890 23:42:11.918851 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8891 23:42:11.918934 ==
8892 23:42:11.922063 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 23:42:11.925358 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 23:42:11.925441 ==
8895 23:42:11.938820
8896 23:42:11.942282 TX Vref early break, caculate TX vref
8897 23:42:11.945261 TX Vref=16, minBit 6, minWin=22, winSum=374
8898 23:42:11.948748 TX Vref=18, minBit 0, minWin=23, winSum=387
8899 23:42:11.952420 TX Vref=20, minBit 0, minWin=24, winSum=394
8900 23:42:11.956151 TX Vref=22, minBit 1, minWin=24, winSum=402
8901 23:42:11.958869 TX Vref=24, minBit 0, minWin=25, winSum=411
8902 23:42:11.965175 TX Vref=26, minBit 11, minWin=25, winSum=422
8903 23:42:11.969057 TX Vref=28, minBit 0, minWin=26, winSum=426
8904 23:42:11.972046 TX Vref=30, minBit 0, minWin=24, winSum=425
8905 23:42:11.975195 TX Vref=32, minBit 0, minWin=24, winSum=411
8906 23:42:11.978659 TX Vref=34, minBit 0, minWin=24, winSum=403
8907 23:42:11.985372 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8908 23:42:11.985456
8909 23:42:11.988706 Final TX Range 0 Vref 28
8910 23:42:11.988789
8911 23:42:11.988889 ==
8912 23:42:11.992321 Dram Type= 6, Freq= 0, CH_1, rank 1
8913 23:42:11.995581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8914 23:42:11.995664 ==
8915 23:42:11.995748
8916 23:42:11.995826
8917 23:42:11.999150 TX Vref Scan disable
8918 23:42:12.002337 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8919 23:42:12.005940 == TX Byte 0 ==
8920 23:42:12.009305 u2DelayCellOfst[0]=17 cells (5 PI)
8921 23:42:12.012174 u2DelayCellOfst[1]=10 cells (3 PI)
8922 23:42:12.015597 u2DelayCellOfst[2]=0 cells (0 PI)
8923 23:42:12.018811 u2DelayCellOfst[3]=7 cells (2 PI)
8924 23:42:12.022379 u2DelayCellOfst[4]=7 cells (2 PI)
8925 23:42:12.025354 u2DelayCellOfst[5]=21 cells (6 PI)
8926 23:42:12.025436 u2DelayCellOfst[6]=17 cells (5 PI)
8927 23:42:12.028916 u2DelayCellOfst[7]=7 cells (2 PI)
8928 23:42:12.035401 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8929 23:42:12.038977 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8930 23:42:12.039060 == TX Byte 1 ==
8931 23:42:12.042193 u2DelayCellOfst[8]=0 cells (0 PI)
8932 23:42:12.045752 u2DelayCellOfst[9]=3 cells (1 PI)
8933 23:42:12.048629 u2DelayCellOfst[10]=10 cells (3 PI)
8934 23:42:12.052186 u2DelayCellOfst[11]=7 cells (2 PI)
8935 23:42:12.055567 u2DelayCellOfst[12]=14 cells (4 PI)
8936 23:42:12.058648 u2DelayCellOfst[13]=14 cells (4 PI)
8937 23:42:12.062096 u2DelayCellOfst[14]=17 cells (5 PI)
8938 23:42:12.066099 u2DelayCellOfst[15]=14 cells (4 PI)
8939 23:42:12.068881 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8940 23:42:12.072164 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8941 23:42:12.075557 DramC Write-DBI on
8942 23:42:12.075640 ==
8943 23:42:12.079133 Dram Type= 6, Freq= 0, CH_1, rank 1
8944 23:42:12.081890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8945 23:42:12.081973 ==
8946 23:42:12.082057
8947 23:42:12.082135
8948 23:42:12.085530 TX Vref Scan disable
8949 23:42:12.088727 == TX Byte 0 ==
8950 23:42:12.092104 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8951 23:42:12.095063 == TX Byte 1 ==
8952 23:42:12.098759 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8953 23:42:12.098842 DramC Write-DBI off
8954 23:42:12.098925
8955 23:42:12.102317 [DATLAT]
8956 23:42:12.102399 Freq=1600, CH1 RK1
8957 23:42:12.102483
8958 23:42:12.105781 DATLAT Default: 0xf
8959 23:42:12.105863 0, 0xFFFF, sum = 0
8960 23:42:12.108473 1, 0xFFFF, sum = 0
8961 23:42:12.108557 2, 0xFFFF, sum = 0
8962 23:42:12.112190 3, 0xFFFF, sum = 0
8963 23:42:12.112275 4, 0xFFFF, sum = 0
8964 23:42:12.115262 5, 0xFFFF, sum = 0
8965 23:42:12.115347 6, 0xFFFF, sum = 0
8966 23:42:12.118628 7, 0xFFFF, sum = 0
8967 23:42:12.118711 8, 0xFFFF, sum = 0
8968 23:42:12.122249 9, 0xFFFF, sum = 0
8969 23:42:12.125183 10, 0xFFFF, sum = 0
8970 23:42:12.125267 11, 0xFFFF, sum = 0
8971 23:42:12.129167 12, 0xFFFF, sum = 0
8972 23:42:12.129251 13, 0xFFFF, sum = 0
8973 23:42:12.131994 14, 0x0, sum = 1
8974 23:42:12.132078 15, 0x0, sum = 2
8975 23:42:12.135499 16, 0x0, sum = 3
8976 23:42:12.135583 17, 0x0, sum = 4
8977 23:42:12.135669 best_step = 15
8978 23:42:12.135750
8979 23:42:12.138729 ==
8980 23:42:12.142013 Dram Type= 6, Freq= 0, CH_1, rank 1
8981 23:42:12.145368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8982 23:42:12.145452 ==
8983 23:42:12.145552 RX Vref Scan: 0
8984 23:42:12.145657
8985 23:42:12.148389 RX Vref 0 -> 0, step: 1
8986 23:42:12.148468
8987 23:42:12.151954 RX Delay 11 -> 252, step: 4
8988 23:42:12.155211 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8989 23:42:12.158518 iDelay=191, Bit 1, Center 122 (71 ~ 174) 104
8990 23:42:12.165209 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8991 23:42:12.168904 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8992 23:42:12.172293 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8993 23:42:12.175520 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8994 23:42:12.178775 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8995 23:42:12.182443 iDelay=191, Bit 7, Center 124 (75 ~ 174) 100
8996 23:42:12.188846 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8997 23:42:12.191932 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8998 23:42:12.195844 iDelay=191, Bit 10, Center 126 (71 ~ 182) 112
8999 23:42:12.198592 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
9000 23:42:12.201940 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9001 23:42:12.208649 iDelay=191, Bit 13, Center 136 (83 ~ 190) 108
9002 23:42:12.212097 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
9003 23:42:12.215300 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
9004 23:42:12.215383 ==
9005 23:42:12.219026 Dram Type= 6, Freq= 0, CH_1, rank 1
9006 23:42:12.222879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9007 23:42:12.222959 ==
9008 23:42:12.225671 DQS Delay:
9009 23:42:12.225750 DQS0 = 0, DQS1 = 0
9010 23:42:12.229277 DQM Delay:
9011 23:42:12.229356 DQM0 = 129, DQM1 = 125
9012 23:42:12.232147 DQ Delay:
9013 23:42:12.235714 DQ0 =134, DQ1 =122, DQ2 =118, DQ3 =128
9014 23:42:12.239442 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =124
9015 23:42:12.242608 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =116
9016 23:42:12.245816 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9017 23:42:12.245907
9018 23:42:12.245976
9019 23:42:12.246036
9020 23:42:12.249028 [DramC_TX_OE_Calibration] TA2
9021 23:42:12.252402 Original DQ_B0 (3 6) =30, OEN = 27
9022 23:42:12.255310 Original DQ_B1 (3 6) =30, OEN = 27
9023 23:42:12.255386 24, 0x0, End_B0=24 End_B1=24
9024 23:42:12.258635 25, 0x0, End_B0=25 End_B1=25
9025 23:42:12.262335 26, 0x0, End_B0=26 End_B1=26
9026 23:42:12.265909 27, 0x0, End_B0=27 End_B1=27
9027 23:42:12.268950 28, 0x0, End_B0=28 End_B1=28
9028 23:42:12.269068 29, 0x0, End_B0=29 End_B1=29
9029 23:42:12.272322 30, 0x0, End_B0=30 End_B1=30
9030 23:42:12.276249 31, 0x4141, End_B0=30 End_B1=30
9031 23:42:12.278666 Byte0 end_step=30 best_step=27
9032 23:42:12.281936 Byte1 end_step=30 best_step=27
9033 23:42:12.282016 Byte0 TX OE(2T, 0.5T) = (3, 3)
9034 23:42:12.285569 Byte1 TX OE(2T, 0.5T) = (3, 3)
9035 23:42:12.285649
9036 23:42:12.285713
9037 23:42:12.295527 [DQSOSCAuto] RK1, (LSB)MR18= 0xd13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
9038 23:42:12.298811 CH1 RK1: MR19=303, MR18=D13
9039 23:42:12.302858 CH1_RK1: MR19=0x303, MR18=0xD13, DQSOSC=400, MR23=63, INC=23, DEC=15
9040 23:42:12.305972 [RxdqsGatingPostProcess] freq 1600
9041 23:42:12.312699 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9042 23:42:12.315479 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 23:42:12.319121 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 23:42:12.322392 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 23:42:12.325661 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 23:42:12.325757 best DQS0 dly(2T, 0.5T) = (1, 1)
9047 23:42:12.329575 best DQS1 dly(2T, 0.5T) = (1, 1)
9048 23:42:12.332594 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9049 23:42:12.335420 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9050 23:42:12.339207 Pre-setting of DQS Precalculation
9051 23:42:12.345553 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9052 23:42:12.352600 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9053 23:42:12.358996 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9054 23:42:12.359076
9055 23:42:12.359139
9056 23:42:12.362603 [Calibration Summary] 3200 Mbps
9057 23:42:12.362682 CH 0, Rank 0
9058 23:42:12.365763 SW Impedance : PASS
9059 23:42:12.368951 DUTY Scan : NO K
9060 23:42:12.369068 ZQ Calibration : PASS
9061 23:42:12.372434 Jitter Meter : NO K
9062 23:42:12.375735 CBT Training : PASS
9063 23:42:12.375815 Write leveling : PASS
9064 23:42:12.378876 RX DQS gating : PASS
9065 23:42:12.378959 RX DQ/DQS(RDDQC) : PASS
9066 23:42:12.382619 TX DQ/DQS : PASS
9067 23:42:12.385790 RX DATLAT : PASS
9068 23:42:12.385874 RX DQ/DQS(Engine): PASS
9069 23:42:12.389832 TX OE : PASS
9070 23:42:12.389915 All Pass.
9071 23:42:12.389999
9072 23:42:12.393007 CH 0, Rank 1
9073 23:42:12.393104 SW Impedance : PASS
9074 23:42:12.396157 DUTY Scan : NO K
9075 23:42:12.399052 ZQ Calibration : PASS
9076 23:42:12.399134 Jitter Meter : NO K
9077 23:42:12.402878 CBT Training : PASS
9078 23:42:12.405572 Write leveling : PASS
9079 23:42:12.405655 RX DQS gating : PASS
9080 23:42:12.409272 RX DQ/DQS(RDDQC) : PASS
9081 23:42:12.412631 TX DQ/DQS : PASS
9082 23:42:12.412714 RX DATLAT : PASS
9083 23:42:12.415945 RX DQ/DQS(Engine): PASS
9084 23:42:12.416028 TX OE : PASS
9085 23:42:12.419349 All Pass.
9086 23:42:12.419431
9087 23:42:12.419514 CH 1, Rank 0
9088 23:42:12.422194 SW Impedance : PASS
9089 23:42:12.422276 DUTY Scan : NO K
9090 23:42:12.426057 ZQ Calibration : PASS
9091 23:42:12.429257 Jitter Meter : NO K
9092 23:42:12.429339 CBT Training : PASS
9093 23:42:12.432503 Write leveling : PASS
9094 23:42:12.436261 RX DQS gating : PASS
9095 23:42:12.436343 RX DQ/DQS(RDDQC) : PASS
9096 23:42:12.439232 TX DQ/DQS : PASS
9097 23:42:12.442382 RX DATLAT : PASS
9098 23:42:12.442498 RX DQ/DQS(Engine): PASS
9099 23:42:12.446076 TX OE : PASS
9100 23:42:12.446171 All Pass.
9101 23:42:12.446255
9102 23:42:12.449402 CH 1, Rank 1
9103 23:42:12.449484 SW Impedance : PASS
9104 23:42:12.452677 DUTY Scan : NO K
9105 23:42:12.455888 ZQ Calibration : PASS
9106 23:42:12.455971 Jitter Meter : NO K
9107 23:42:12.459069 CBT Training : PASS
9108 23:42:12.459152 Write leveling : PASS
9109 23:42:12.463345 RX DQS gating : PASS
9110 23:42:12.465899 RX DQ/DQS(RDDQC) : PASS
9111 23:42:12.465981 TX DQ/DQS : PASS
9112 23:42:12.469724 RX DATLAT : PASS
9113 23:42:12.472579 RX DQ/DQS(Engine): PASS
9114 23:42:12.472661 TX OE : PASS
9115 23:42:12.476018 All Pass.
9116 23:42:12.476101
9117 23:42:12.476184 DramC Write-DBI on
9118 23:42:12.479330 PER_BANK_REFRESH: Hybrid Mode
9119 23:42:12.479413 TX_TRACKING: ON
9120 23:42:12.489333 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9121 23:42:12.499437 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9122 23:42:12.506070 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9123 23:42:12.509579 [FAST_K] Save calibration result to emmc
9124 23:42:12.513096 sync common calibartion params.
9125 23:42:12.513179 sync cbt_mode0:1, 1:1
9126 23:42:12.516299 dram_init: ddr_geometry: 2
9127 23:42:12.519233 dram_init: ddr_geometry: 2
9128 23:42:12.519316 dram_init: ddr_geometry: 2
9129 23:42:12.523187 0:dram_rank_size:100000000
9130 23:42:12.526073 1:dram_rank_size:100000000
9131 23:42:12.529391 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9132 23:42:12.532673 DFS_SHUFFLE_HW_MODE: ON
9133 23:42:12.535868 dramc_set_vcore_voltage set vcore to 725000
9134 23:42:12.539413 Read voltage for 1600, 0
9135 23:42:12.539496 Vio18 = 0
9136 23:42:12.542711 Vcore = 725000
9137 23:42:12.542793 Vdram = 0
9138 23:42:12.542877 Vddq = 0
9139 23:42:12.546111 Vmddr = 0
9140 23:42:12.546218 switch to 3200 Mbps bootup
9141 23:42:12.549487 [DramcRunTimeConfig]
9142 23:42:12.549570 PHYPLL
9143 23:42:12.552678 DPM_CONTROL_AFTERK: ON
9144 23:42:12.552760 PER_BANK_REFRESH: ON
9145 23:42:12.556163 REFRESH_OVERHEAD_REDUCTION: ON
9146 23:42:12.559364 CMD_PICG_NEW_MODE: OFF
9147 23:42:12.559447 XRTWTW_NEW_MODE: ON
9148 23:42:12.562622 XRTRTR_NEW_MODE: ON
9149 23:42:12.562714 TX_TRACKING: ON
9150 23:42:12.565933 RDSEL_TRACKING: OFF
9151 23:42:12.569253 DQS Precalculation for DVFS: ON
9152 23:42:12.569336 RX_TRACKING: OFF
9153 23:42:12.572751 HW_GATING DBG: ON
9154 23:42:12.572856 ZQCS_ENABLE_LP4: ON
9155 23:42:12.576141 RX_PICG_NEW_MODE: ON
9156 23:42:12.576223 TX_PICG_NEW_MODE: ON
9157 23:42:12.579112 ENABLE_RX_DCM_DPHY: ON
9158 23:42:12.582628 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9159 23:42:12.585712 DUMMY_READ_FOR_TRACKING: OFF
9160 23:42:12.585795 !!! SPM_CONTROL_AFTERK: OFF
9161 23:42:12.589655 !!! SPM could not control APHY
9162 23:42:12.592553 IMPEDANCE_TRACKING: ON
9163 23:42:12.592660 TEMP_SENSOR: ON
9164 23:42:12.595854 HW_SAVE_FOR_SR: OFF
9165 23:42:12.599235 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9166 23:42:12.602481 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9167 23:42:12.602563 Read ODT Tracking: ON
9168 23:42:12.605992 Refresh Rate DeBounce: ON
9169 23:42:12.609478 DFS_NO_QUEUE_FLUSH: ON
9170 23:42:12.612560 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9171 23:42:12.612646 ENABLE_DFS_RUNTIME_MRW: OFF
9172 23:42:12.616114 DDR_RESERVE_NEW_MODE: ON
9173 23:42:12.618937 MR_CBT_SWITCH_FREQ: ON
9174 23:42:12.619017 =========================
9175 23:42:12.639492 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9176 23:42:12.642522 dram_init: ddr_geometry: 2
9177 23:42:12.661081 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9178 23:42:12.664595 dram_init: dram init end (result: 0)
9179 23:42:12.670652 DRAM-K: Full calibration passed in 24593 msecs
9180 23:42:12.674033 MRC: failed to locate region type 0.
9181 23:42:12.674106 DRAM rank0 size:0x100000000,
9182 23:42:12.677765 DRAM rank1 size=0x100000000
9183 23:42:12.687999 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9184 23:42:12.694299 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9185 23:42:12.700885 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9186 23:42:12.707896 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9187 23:42:12.710921 DRAM rank0 size:0x100000000,
9188 23:42:12.714593 DRAM rank1 size=0x100000000
9189 23:42:12.714673 CBMEM:
9190 23:42:12.717737 IMD: root @ 0xfffff000 254 entries.
9191 23:42:12.721077 IMD: root @ 0xffffec00 62 entries.
9192 23:42:12.724287 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9193 23:42:12.727891 WARNING: RO_VPD is uninitialized or empty.
9194 23:42:12.734040 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9195 23:42:12.740963 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9196 23:42:12.753713 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9197 23:42:12.765412 BS: romstage times (exec / console): total (unknown) / 24100 ms
9198 23:42:12.765493
9199 23:42:12.765557
9200 23:42:12.774853 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9201 23:42:12.778615 ARM64: Exception handlers installed.
9202 23:42:12.781545 ARM64: Testing exception
9203 23:42:12.784952 ARM64: Done test exception
9204 23:42:12.785073 Enumerating buses...
9205 23:42:12.788456 Show all devs... Before device enumeration.
9206 23:42:12.791688 Root Device: enabled 1
9207 23:42:12.795373 CPU_CLUSTER: 0: enabled 1
9208 23:42:12.795452 CPU: 00: enabled 1
9209 23:42:12.798260 Compare with tree...
9210 23:42:12.798339 Root Device: enabled 1
9211 23:42:12.802254 CPU_CLUSTER: 0: enabled 1
9212 23:42:12.805078 CPU: 00: enabled 1
9213 23:42:12.805148 Root Device scanning...
9214 23:42:12.808130 scan_static_bus for Root Device
9215 23:42:12.811715 CPU_CLUSTER: 0 enabled
9216 23:42:12.814926 scan_static_bus for Root Device done
9217 23:42:12.818680 scan_bus: bus Root Device finished in 8 msecs
9218 23:42:12.818760 done
9219 23:42:12.824887 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9220 23:42:12.828414 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9221 23:42:12.835152 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9222 23:42:12.838549 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9223 23:42:12.841354 Allocating resources...
9224 23:42:12.841434 Reading resources...
9225 23:42:12.848043 Root Device read_resources bus 0 link: 0
9226 23:42:12.848143 DRAM rank0 size:0x100000000,
9227 23:42:12.851453 DRAM rank1 size=0x100000000
9228 23:42:12.854730 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9229 23:42:12.858098 CPU: 00 missing read_resources
9230 23:42:12.861715 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9231 23:42:12.868416 Root Device read_resources bus 0 link: 0 done
9232 23:42:12.868529 Done reading resources.
9233 23:42:12.874869 Show resources in subtree (Root Device)...After reading.
9234 23:42:12.878283 Root Device child on link 0 CPU_CLUSTER: 0
9235 23:42:12.881522 CPU_CLUSTER: 0 child on link 0 CPU: 00
9236 23:42:12.891731 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9237 23:42:12.891812 CPU: 00
9238 23:42:12.895296 Root Device assign_resources, bus 0 link: 0
9239 23:42:12.898402 CPU_CLUSTER: 0 missing set_resources
9240 23:42:12.901686 Root Device assign_resources, bus 0 link: 0 done
9241 23:42:12.905110 Done setting resources.
9242 23:42:12.912018 Show resources in subtree (Root Device)...After assigning values.
9243 23:42:12.914857 Root Device child on link 0 CPU_CLUSTER: 0
9244 23:42:12.917999 CPU_CLUSTER: 0 child on link 0 CPU: 00
9245 23:42:12.928600 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9246 23:42:12.928677 CPU: 00
9247 23:42:12.931843 Done allocating resources.
9248 23:42:12.934786 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9249 23:42:12.938074 Enabling resources...
9250 23:42:12.938148 done.
9251 23:42:12.941671 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9252 23:42:12.944875 Initializing devices...
9253 23:42:12.948473 Root Device init
9254 23:42:12.948552 init hardware done!
9255 23:42:12.951774 0x00000018: ctrlr->caps
9256 23:42:12.951847 52.000 MHz: ctrlr->f_max
9257 23:42:12.955170 0.400 MHz: ctrlr->f_min
9258 23:42:12.958336 0x40ff8080: ctrlr->voltages
9259 23:42:12.958421 sclk: 390625
9260 23:42:12.961651 Bus Width = 1
9261 23:42:12.961733 sclk: 390625
9262 23:42:12.961817 Bus Width = 1
9263 23:42:12.964908 Early init status = 3
9264 23:42:12.968529 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9265 23:42:12.972347 in-header: 03 fc 00 00 01 00 00 00
9266 23:42:12.975919 in-data: 00
9267 23:42:12.979012 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9268 23:42:12.983655 in-header: 03 fd 00 00 00 00 00 00
9269 23:42:12.987141 in-data:
9270 23:42:12.990369 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9271 23:42:12.993650 in-header: 03 fc 00 00 01 00 00 00
9272 23:42:12.997759 in-data: 00
9273 23:42:13.000165 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9274 23:42:13.005888 in-header: 03 fd 00 00 00 00 00 00
9275 23:42:13.009128 in-data:
9276 23:42:13.012112 [SSUSB] Setting up USB HOST controller...
9277 23:42:13.015927 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9278 23:42:13.018724 [SSUSB] phy power-on done.
9279 23:42:13.022543 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9280 23:42:13.029096 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9281 23:42:13.032859 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9282 23:42:13.038789 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9283 23:42:13.045426 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9284 23:42:13.051959 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9285 23:42:13.058563 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9286 23:42:13.065850 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9287 23:42:13.069508 SPM: binary array size = 0x9dc
9288 23:42:13.072049 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9289 23:42:13.078741 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9290 23:42:13.085642 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9291 23:42:13.089096 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9292 23:42:13.092293 configure_display: Starting display init
9293 23:42:13.129074 anx7625_power_on_init: Init interface.
9294 23:42:13.132235 anx7625_disable_pd_protocol: Disabled PD feature.
9295 23:42:13.135634 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9296 23:42:13.163518 anx7625_start_dp_work: Secure OCM version=00
9297 23:42:13.166662 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9298 23:42:13.181808 sp_tx_get_edid_block: EDID Block = 1
9299 23:42:13.284550 Extracted contents:
9300 23:42:13.287757 header: 00 ff ff ff ff ff ff 00
9301 23:42:13.290489 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9302 23:42:13.294131 version: 01 04
9303 23:42:13.297479 basic params: 95 1f 11 78 0a
9304 23:42:13.300833 chroma info: 76 90 94 55 54 90 27 21 50 54
9305 23:42:13.304452 established: 00 00 00
9306 23:42:13.307785 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9307 23:42:13.314162 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9308 23:42:13.320816 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9309 23:42:13.327395 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9310 23:42:13.334047 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9311 23:42:13.337234 extensions: 00
9312 23:42:13.337325 checksum: fb
9313 23:42:13.337414
9314 23:42:13.340965 Manufacturer: IVO Model 57d Serial Number 0
9315 23:42:13.344128 Made week 0 of 2020
9316 23:42:13.344206 EDID version: 1.4
9317 23:42:13.347357 Digital display
9318 23:42:13.350898 6 bits per primary color channel
9319 23:42:13.351013 DisplayPort interface
9320 23:42:13.354126 Maximum image size: 31 cm x 17 cm
9321 23:42:13.354204 Gamma: 220%
9322 23:42:13.357230 Check DPMS levels
9323 23:42:13.361029 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9324 23:42:13.364140 First detailed timing is preferred timing
9325 23:42:13.367411 Established timings supported:
9326 23:42:13.371125 Standard timings supported:
9327 23:42:13.371222 Detailed timings
9328 23:42:13.377607 Hex of detail: 383680a07038204018303c0035ae10000019
9329 23:42:13.380842 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9330 23:42:13.384377 0780 0798 07c8 0820 hborder 0
9331 23:42:13.391067 0438 043b 0447 0458 vborder 0
9332 23:42:13.391148 -hsync -vsync
9333 23:42:13.394141 Did detailed timing
9334 23:42:13.397410 Hex of detail: 000000000000000000000000000000000000
9335 23:42:13.400697 Manufacturer-specified data, tag 0
9336 23:42:13.407564 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9337 23:42:13.407644 ASCII string: InfoVision
9338 23:42:13.413992 Hex of detail: 000000fe00523134304e574635205248200a
9339 23:42:13.414072 ASCII string: R140NWF5 RH
9340 23:42:13.417285 Checksum
9341 23:42:13.417365 Checksum: 0xfb (valid)
9342 23:42:13.424173 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9343 23:42:13.427364 DSI data_rate: 832800000 bps
9344 23:42:13.430465 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9345 23:42:13.433743 anx7625_parse_edid: pixelclock(138800).
9346 23:42:13.440636 hactive(1920), hsync(48), hfp(24), hbp(88)
9347 23:42:13.444147 vactive(1080), vsync(12), vfp(3), vbp(17)
9348 23:42:13.447120 anx7625_dsi_config: config dsi.
9349 23:42:13.453901 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9350 23:42:13.465977 anx7625_dsi_config: success to config DSI
9351 23:42:13.469811 anx7625_dp_start: MIPI phy setup OK.
9352 23:42:13.473276 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9353 23:42:13.476359 mtk_ddp_mode_set invalid vrefresh 60
9354 23:42:13.479794 main_disp_path_setup
9355 23:42:13.479877 ovl_layer_smi_id_en
9356 23:42:13.483282 ovl_layer_smi_id_en
9357 23:42:13.483365 ccorr_config
9358 23:42:13.483449 aal_config
9359 23:42:13.486339 gamma_config
9360 23:42:13.486421 postmask_config
9361 23:42:13.489879 dither_config
9362 23:42:13.492885 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9363 23:42:13.499685 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9364 23:42:13.502940 Root Device init finished in 552 msecs
9365 23:42:13.503019 CPU_CLUSTER: 0 init
9366 23:42:13.513277 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9367 23:42:13.516566 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9368 23:42:13.519526 APU_MBOX 0x190000b0 = 0x10001
9369 23:42:13.523224 APU_MBOX 0x190001b0 = 0x10001
9370 23:42:13.526985 APU_MBOX 0x190005b0 = 0x10001
9371 23:42:13.529646 APU_MBOX 0x190006b0 = 0x10001
9372 23:42:13.532917 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9373 23:42:13.544929 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9374 23:42:13.557717 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9375 23:42:13.564232 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9376 23:42:13.576177 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9377 23:42:13.584733 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9378 23:42:13.588021 CPU_CLUSTER: 0 init finished in 81 msecs
9379 23:42:13.591607 Devices initialized
9380 23:42:13.594903 Show all devs... After init.
9381 23:42:13.594983 Root Device: enabled 1
9382 23:42:13.598627 CPU_CLUSTER: 0: enabled 1
9383 23:42:13.601750 CPU: 00: enabled 1
9384 23:42:13.604806 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9385 23:42:13.608245 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9386 23:42:13.611638 ELOG: NV offset 0x57f000 size 0x1000
9387 23:42:13.618192 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9388 23:42:13.625271 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9389 23:42:13.628032 ELOG: Event(17) added with size 13 at 2024-06-04 23:42:14 UTC
9390 23:42:13.631755 out: cmd=0x121: 03 db 21 01 00 00 00 00
9391 23:42:13.636062 in-header: 03 c9 00 00 2c 00 00 00
9392 23:42:13.649561 in-data: 96 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9393 23:42:13.655995 ELOG: Event(A1) added with size 10 at 2024-06-04 23:42:14 UTC
9394 23:42:13.662709 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9395 23:42:13.669442 ELOG: Event(A0) added with size 9 at 2024-06-04 23:42:14 UTC
9396 23:42:13.672619 elog_add_boot_reason: Logged dev mode boot
9397 23:42:13.675820 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9398 23:42:13.679192 Finalize devices...
9399 23:42:13.679271 Devices finalized
9400 23:42:13.685861 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9401 23:42:13.689252 Writing coreboot table at 0xffe64000
9402 23:42:13.692349 0. 000000000010a000-0000000000113fff: RAMSTAGE
9403 23:42:13.696432 1. 0000000040000000-00000000400fffff: RAM
9404 23:42:13.699549 2. 0000000040100000-000000004032afff: RAMSTAGE
9405 23:42:13.705746 3. 000000004032b000-00000000545fffff: RAM
9406 23:42:13.709595 4. 0000000054600000-000000005465ffff: BL31
9407 23:42:13.712962 5. 0000000054660000-00000000ffe63fff: RAM
9408 23:42:13.716119 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9409 23:42:13.722682 7. 0000000100000000-000000023fffffff: RAM
9410 23:42:13.722761 Passing 5 GPIOs to payload:
9411 23:42:13.729413 NAME | PORT | POLARITY | VALUE
9412 23:42:13.733000 EC in RW | 0x000000aa | low | undefined
9413 23:42:13.739407 EC interrupt | 0x00000005 | low | undefined
9414 23:42:13.742926 TPM interrupt | 0x000000ab | high | undefined
9415 23:42:13.745767 SD card detect | 0x00000011 | high | undefined
9416 23:42:13.752674 speaker enable | 0x00000093 | high | undefined
9417 23:42:13.756010 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9418 23:42:13.759272 in-header: 03 f9 00 00 02 00 00 00
9419 23:42:13.759351 in-data: 02 00
9420 23:42:13.762438 ADC[4]: Raw value=900590 ID=7
9421 23:42:13.765877 ADC[3]: Raw value=212967 ID=1
9422 23:42:13.765958 RAM Code: 0x71
9423 23:42:13.769711 ADC[6]: Raw value=74557 ID=0
9424 23:42:13.772720 ADC[5]: Raw value=212229 ID=1
9425 23:42:13.772801 SKU Code: 0x1
9426 23:42:13.779259 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 6bbf
9427 23:42:13.782684 coreboot table: 964 bytes.
9428 23:42:13.786187 IMD ROOT 0. 0xfffff000 0x00001000
9429 23:42:13.789295 IMD SMALL 1. 0xffffe000 0x00001000
9430 23:42:13.792960 RO MCACHE 2. 0xffffc000 0x00001104
9431 23:42:13.795940 CONSOLE 3. 0xfff7c000 0x00080000
9432 23:42:13.799266 FMAP 4. 0xfff7b000 0x00000452
9433 23:42:13.802844 TIME STAMP 5. 0xfff7a000 0x00000910
9434 23:42:13.805721 VBOOT WORK 6. 0xfff66000 0x00014000
9435 23:42:13.809139 RAMOOPS 7. 0xffe66000 0x00100000
9436 23:42:13.813177 COREBOOT 8. 0xffe64000 0x00002000
9437 23:42:13.813258 IMD small region:
9438 23:42:13.816127 IMD ROOT 0. 0xffffec00 0x00000400
9439 23:42:13.819319 VPD 1. 0xffffeb80 0x0000006c
9440 23:42:13.822419 MMC STATUS 2. 0xffffeb60 0x00000004
9441 23:42:13.828902 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9442 23:42:13.829039 Probing TPM: done!
9443 23:42:13.836060 Connected to device vid:did:rid of 1ae0:0028:00
9444 23:42:13.843073 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9445 23:42:13.846030 Initialized TPM device CR50 revision 0
9446 23:42:13.849743 Checking cr50 for pending updates
9447 23:42:13.855464 Reading cr50 TPM mode
9448 23:42:13.863929 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9449 23:42:13.871314 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9450 23:42:13.910726 read SPI 0x3990ec 0x4f1b0: 34845 us, 9298 KB/s, 74.384 Mbps
9451 23:42:13.914351 Checking segment from ROM address 0x40100000
9452 23:42:13.917674 Checking segment from ROM address 0x4010001c
9453 23:42:13.924339 Loading segment from ROM address 0x40100000
9454 23:42:13.924423 code (compression=0)
9455 23:42:13.931118 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9456 23:42:13.940836 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9457 23:42:13.940920 it's not compressed!
9458 23:42:13.947851 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9459 23:42:13.950963 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9460 23:42:13.971096 Loading segment from ROM address 0x4010001c
9461 23:42:13.971181 Entry Point 0x80000000
9462 23:42:13.974909 Loaded segments
9463 23:42:13.977864 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9464 23:42:13.981514 Jumping to boot code at 0x80000000(0xffe64000)
9465 23:42:13.991534 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9466 23:42:13.998160 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9467 23:42:14.005891 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9468 23:42:14.009157 Checking segment from ROM address 0x40100000
9469 23:42:14.012274 Checking segment from ROM address 0x4010001c
9470 23:42:14.016004 Loading segment from ROM address 0x40100000
9471 23:42:14.019280 code (compression=1)
9472 23:42:14.025585 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9473 23:42:14.035971 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9474 23:42:14.036052 using LZMA
9475 23:42:14.043832 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9476 23:42:14.050867 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9477 23:42:14.054084 Loading segment from ROM address 0x4010001c
9478 23:42:14.054164 Entry Point 0x54601000
9479 23:42:14.057604 Loaded segments
9480 23:42:14.060699 NOTICE: MT8192 bl31_setup
9481 23:42:14.068289 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9482 23:42:14.070957 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9483 23:42:14.074401 WARNING: region 0:
9484 23:42:14.077578 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 23:42:14.077657 WARNING: region 1:
9486 23:42:14.083988 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9487 23:42:14.087350 WARNING: region 2:
9488 23:42:14.091045 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9489 23:42:14.094207 WARNING: region 3:
9490 23:42:14.097825 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9491 23:42:14.101160 WARNING: region 4:
9492 23:42:14.107678 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9493 23:42:14.107759 WARNING: region 5:
9494 23:42:14.110996 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 23:42:14.114197 WARNING: region 6:
9496 23:42:14.118082 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9497 23:42:14.118160 WARNING: region 7:
9498 23:42:14.124647 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 23:42:14.131379 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9500 23:42:14.134384 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9501 23:42:14.137932 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9502 23:42:14.144946 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9503 23:42:14.148538 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9504 23:42:14.151256 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9505 23:42:14.158244 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9506 23:42:14.161659 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9507 23:42:14.165105 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9508 23:42:14.171893 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9509 23:42:14.175274 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9510 23:42:14.178615 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9511 23:42:14.184761 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9512 23:42:14.188844 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9513 23:42:14.194882 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9514 23:42:14.198446 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9515 23:42:14.201709 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9516 23:42:14.208946 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9517 23:42:14.211968 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9518 23:42:14.215739 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9519 23:42:14.221631 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9520 23:42:14.225342 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9521 23:42:14.231647 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9522 23:42:14.235015 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9523 23:42:14.238649 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9524 23:42:14.245182 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9525 23:42:14.248394 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9526 23:42:14.251835 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9527 23:42:14.259044 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9528 23:42:14.261955 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9529 23:42:14.268576 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9530 23:42:14.272085 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9531 23:42:14.275634 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9532 23:42:14.278865 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9533 23:42:14.285839 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9534 23:42:14.288675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9535 23:42:14.292141 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9536 23:42:14.295786 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9537 23:42:14.302426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9538 23:42:14.305604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9539 23:42:14.308806 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9540 23:42:14.312733 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9541 23:42:14.318952 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9542 23:42:14.322844 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9543 23:42:14.326016 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9544 23:42:14.329163 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9545 23:42:14.336213 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9546 23:42:14.339643 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9547 23:42:14.342835 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9548 23:42:14.349384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9549 23:42:14.352756 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9550 23:42:14.356001 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9551 23:42:14.362832 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9552 23:42:14.366239 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9553 23:42:14.372869 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9554 23:42:14.375922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9555 23:42:14.382845 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9556 23:42:14.386124 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9557 23:42:14.389492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9558 23:42:14.396059 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9559 23:42:14.399636 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9560 23:42:14.406347 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9561 23:42:14.409512 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9562 23:42:14.416859 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9563 23:42:14.419925 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9564 23:42:14.423396 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9565 23:42:14.429820 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9566 23:42:14.433267 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9567 23:42:14.439410 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9568 23:42:14.442854 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9569 23:42:14.450004 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9570 23:42:14.453378 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9571 23:42:14.456504 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9572 23:42:14.463049 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9573 23:42:14.466324 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9574 23:42:14.473456 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9575 23:42:14.476413 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9576 23:42:14.483721 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9577 23:42:14.486446 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9578 23:42:14.490313 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9579 23:42:14.497237 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9580 23:42:14.500163 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9581 23:42:14.506852 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9582 23:42:14.510312 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9583 23:42:14.513596 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9584 23:42:14.520527 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9585 23:42:14.523396 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9586 23:42:14.530446 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9587 23:42:14.533733 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9588 23:42:14.537149 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9589 23:42:14.543828 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9590 23:42:14.547372 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9591 23:42:14.553756 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9592 23:42:14.557063 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9593 23:42:14.563825 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9594 23:42:14.566911 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9595 23:42:14.570765 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9596 23:42:14.577656 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9597 23:42:14.580492 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9598 23:42:14.583738 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9599 23:42:14.587635 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9600 23:42:14.593721 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9601 23:42:14.597486 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9602 23:42:14.604040 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9603 23:42:14.607555 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9604 23:42:14.610789 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9605 23:42:14.617767 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9606 23:42:14.620862 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9607 23:42:14.627544 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9608 23:42:14.630580 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9609 23:42:14.633778 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9610 23:42:14.640541 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9611 23:42:14.644160 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9612 23:42:14.650986 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9613 23:42:14.654171 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9614 23:42:14.657326 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9615 23:42:14.660777 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9616 23:42:14.667328 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9617 23:42:14.670610 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9618 23:42:14.673910 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9619 23:42:14.680703 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9620 23:42:14.684516 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9621 23:42:14.687477 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9622 23:42:14.690641 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9623 23:42:14.696992 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9624 23:42:14.700650 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9625 23:42:14.707738 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9626 23:42:14.710850 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9627 23:42:14.714192 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9628 23:42:14.721079 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9629 23:42:14.724630 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9630 23:42:14.727697 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9631 23:42:14.734310 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9632 23:42:14.737425 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9633 23:42:14.744185 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9634 23:42:14.748012 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9635 23:42:14.750891 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9636 23:42:14.757856 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9637 23:42:14.761083 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9638 23:42:14.764326 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9639 23:42:14.771116 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9640 23:42:14.774501 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9641 23:42:14.781152 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9642 23:42:14.784176 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9643 23:42:14.787750 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9644 23:42:14.794651 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9645 23:42:14.797776 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9646 23:42:14.800937 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9647 23:42:14.807594 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9648 23:42:14.810826 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9649 23:42:14.817750 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9650 23:42:14.821217 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9651 23:42:14.825365 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9652 23:42:14.831371 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9653 23:42:14.834478 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9654 23:42:14.841221 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9655 23:42:14.844474 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9656 23:42:14.847723 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9657 23:42:14.854456 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9658 23:42:14.857828 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9659 23:42:14.861490 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9660 23:42:14.867860 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9661 23:42:14.871169 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9662 23:42:14.878318 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9663 23:42:14.882119 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9664 23:42:14.884886 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9665 23:42:14.891238 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9666 23:42:14.894973 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9667 23:42:14.898156 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9668 23:42:14.904919 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9669 23:42:14.908044 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9670 23:42:14.914976 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9671 23:42:14.917990 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9672 23:42:14.921333 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9673 23:42:14.927880 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9674 23:42:14.931558 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9675 23:42:14.938462 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9676 23:42:14.941587 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9677 23:42:14.944611 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9678 23:42:14.951656 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9679 23:42:14.954972 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9680 23:42:14.958364 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9681 23:42:14.965085 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9682 23:42:14.968417 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9683 23:42:14.974693 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9684 23:42:14.978495 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9685 23:42:14.981880 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9686 23:42:14.988646 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9687 23:42:14.992024 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9688 23:42:14.995303 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9689 23:42:15.001743 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9690 23:42:15.005335 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9691 23:42:15.012123 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9692 23:42:15.014924 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9693 23:42:15.021792 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9694 23:42:15.024918 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9695 23:42:15.028860 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9696 23:42:15.035186 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9697 23:42:15.038544 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9698 23:42:15.045389 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9699 23:42:15.048674 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9700 23:42:15.051785 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9701 23:42:15.058741 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9702 23:42:15.061736 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9703 23:42:15.068600 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9704 23:42:15.071927 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9705 23:42:15.075752 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9706 23:42:15.081757 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9707 23:42:15.085389 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9708 23:42:15.091761 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9709 23:42:15.095336 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9710 23:42:15.098613 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9711 23:42:15.105465 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9712 23:42:15.109006 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9713 23:42:15.115076 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9714 23:42:15.118578 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9715 23:42:15.124926 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9716 23:42:15.128650 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9717 23:42:15.132045 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9718 23:42:15.138796 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9719 23:42:15.142404 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9720 23:42:15.148454 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9721 23:42:15.151979 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9722 23:42:15.155384 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9723 23:42:15.161571 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9724 23:42:15.165318 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9725 23:42:15.171995 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9726 23:42:15.175283 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9727 23:42:15.178964 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9728 23:42:15.184852 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9729 23:42:15.188831 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9730 23:42:15.191689 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9731 23:42:15.195057 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9732 23:42:15.201966 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9733 23:42:15.204876 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9734 23:42:15.208187 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9735 23:42:15.215441 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9736 23:42:15.218939 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9737 23:42:15.221986 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9738 23:42:15.228687 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9739 23:42:15.231778 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9740 23:42:15.235360 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9741 23:42:15.242119 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9742 23:42:15.245695 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9743 23:42:15.248602 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9744 23:42:15.255438 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9745 23:42:15.258621 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9746 23:42:15.265090 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9747 23:42:15.268907 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9748 23:42:15.271699 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9749 23:42:15.278779 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9750 23:42:15.281945 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9751 23:42:15.285415 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9752 23:42:15.291968 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9753 23:42:15.295475 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9754 23:42:15.298644 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9755 23:42:15.305426 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9756 23:42:15.308726 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9757 23:42:15.312171 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9758 23:42:15.318944 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9759 23:42:15.322361 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9760 23:42:15.328761 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9761 23:42:15.332065 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9762 23:42:15.335350 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9763 23:42:15.341799 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9764 23:42:15.345508 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9765 23:42:15.348614 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9766 23:42:15.355250 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9767 23:42:15.358725 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9768 23:42:15.362264 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9769 23:42:15.365259 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9770 23:42:15.372289 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9771 23:42:15.375495 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9772 23:42:15.378898 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9773 23:42:15.382545 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9774 23:42:15.388844 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9775 23:42:15.392333 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9776 23:42:15.395613 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9777 23:42:15.398954 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9778 23:42:15.402549 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9779 23:42:15.409165 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9780 23:42:15.412213 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9781 23:42:15.415861 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9782 23:42:15.422533 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9783 23:42:15.425693 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9784 23:42:15.432968 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9785 23:42:15.435987 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9786 23:42:15.442691 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9787 23:42:15.445729 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9788 23:42:15.449021 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9789 23:42:15.455652 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9790 23:42:15.459311 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9791 23:42:15.465480 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9792 23:42:15.468953 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9793 23:42:15.472447 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9794 23:42:15.478911 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9795 23:42:15.482126 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9796 23:42:15.489232 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9797 23:42:15.492348 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9798 23:42:15.495658 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9799 23:42:15.502185 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9800 23:42:15.505638 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9801 23:42:15.512271 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9802 23:42:15.515808 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9803 23:42:15.522234 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9804 23:42:15.525762 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9805 23:42:15.529045 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9806 23:42:15.535726 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9807 23:42:15.539445 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9808 23:42:15.542081 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9809 23:42:15.549332 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9810 23:42:15.552244 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9811 23:42:15.558882 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9812 23:42:15.562244 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9813 23:42:15.565785 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9814 23:42:15.572294 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9815 23:42:15.576079 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9816 23:42:15.582215 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9817 23:42:15.585939 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9818 23:42:15.589052 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9819 23:42:15.595730 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9820 23:42:15.599491 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9821 23:42:15.606156 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9822 23:42:15.609513 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9823 23:42:15.612385 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9824 23:42:15.619765 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9825 23:42:15.622440 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9826 23:42:15.629111 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9827 23:42:15.632287 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9828 23:42:15.635590 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9829 23:42:15.642336 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9830 23:42:15.646219 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9831 23:42:15.652668 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9832 23:42:15.655811 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9833 23:42:15.659311 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9834 23:42:15.666136 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9835 23:42:15.669206 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9836 23:42:15.676023 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9837 23:42:15.679589 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9838 23:42:15.682822 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9839 23:42:15.689655 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9840 23:42:15.692485 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9841 23:42:15.699331 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9842 23:42:15.702691 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9843 23:42:15.706111 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9844 23:42:15.712541 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9845 23:42:15.716262 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9846 23:42:15.723482 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9847 23:42:15.726195 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9848 23:42:15.729257 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9849 23:42:15.736250 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9850 23:42:15.739666 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9851 23:42:15.746379 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9852 23:42:15.749279 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9853 23:42:15.753027 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9854 23:42:15.759209 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9855 23:42:15.762893 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9856 23:42:15.769270 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9857 23:42:15.772796 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9858 23:42:15.779555 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9859 23:42:15.783144 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9860 23:42:15.786522 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9861 23:42:15.793043 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9862 23:42:15.796604 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9863 23:42:15.803587 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9864 23:42:15.806756 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9865 23:42:15.812766 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9866 23:42:15.816248 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9867 23:42:15.819957 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9868 23:42:15.826460 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9869 23:42:15.829411 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9870 23:42:15.836196 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9871 23:42:15.839877 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9872 23:42:15.846755 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9873 23:42:15.849900 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9874 23:42:15.853117 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9875 23:42:15.859458 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9876 23:42:15.862937 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9877 23:42:15.869966 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9878 23:42:15.873227 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9879 23:42:15.876355 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9880 23:42:15.882880 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9881 23:42:15.886440 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9882 23:42:15.893312 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9883 23:42:15.896443 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9884 23:42:15.900422 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9885 23:42:15.906524 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9886 23:42:15.910167 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9887 23:42:15.916714 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9888 23:42:15.920183 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9889 23:42:15.926645 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9890 23:42:15.929951 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9891 23:42:15.936291 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9892 23:42:15.939863 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9893 23:42:15.943209 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9894 23:42:15.949958 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9895 23:42:15.953123 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9896 23:42:15.959694 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9897 23:42:15.963203 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9898 23:42:15.969735 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9899 23:42:15.973043 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9900 23:42:15.976731 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9901 23:42:15.983609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9902 23:42:15.986411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9903 23:42:15.993584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9904 23:42:15.996432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9905 23:42:16.003319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9906 23:42:16.006610 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9907 23:42:16.009935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9908 23:42:16.016257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9909 23:42:16.019843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9910 23:42:16.026483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9911 23:42:16.029761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9912 23:42:16.036384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9913 23:42:16.040795 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9914 23:42:16.046442 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9915 23:42:16.050033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9916 23:42:16.056711 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9917 23:42:16.060130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9918 23:42:16.066541 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9919 23:42:16.070128 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9920 23:42:16.076857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9921 23:42:16.079983 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9922 23:42:16.086448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9923 23:42:16.089989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9924 23:42:16.096664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9925 23:42:16.099885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9926 23:42:16.106744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9927 23:42:16.110143 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9928 23:42:16.116513 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9929 23:42:16.119799 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9930 23:42:16.126470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9931 23:42:16.130103 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9932 23:42:16.136576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9933 23:42:16.139999 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9934 23:42:16.140076 INFO: [APUAPC] vio 0
9935 23:42:16.147406 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9936 23:42:16.150651 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9937 23:42:16.154338 INFO: [APUAPC] D0_APC_0: 0x400510
9938 23:42:16.157459 INFO: [APUAPC] D0_APC_1: 0x0
9939 23:42:16.160944 INFO: [APUAPC] D0_APC_2: 0x1540
9940 23:42:16.164125 INFO: [APUAPC] D0_APC_3: 0x0
9941 23:42:16.167438 INFO: [APUAPC] D1_APC_0: 0xffffffff
9942 23:42:16.170639 INFO: [APUAPC] D1_APC_1: 0xffffffff
9943 23:42:16.173986 INFO: [APUAPC] D1_APC_2: 0x3fffff
9944 23:42:16.177502 INFO: [APUAPC] D1_APC_3: 0x0
9945 23:42:16.180696 INFO: [APUAPC] D2_APC_0: 0xffffffff
9946 23:42:16.184030 INFO: [APUAPC] D2_APC_1: 0xffffffff
9947 23:42:16.187237 INFO: [APUAPC] D2_APC_2: 0x3fffff
9948 23:42:16.190608 INFO: [APUAPC] D2_APC_3: 0x0
9949 23:42:16.193824 INFO: [APUAPC] D3_APC_0: 0xffffffff
9950 23:42:16.197281 INFO: [APUAPC] D3_APC_1: 0xffffffff
9951 23:42:16.200725 INFO: [APUAPC] D3_APC_2: 0x3fffff
9952 23:42:16.200831 INFO: [APUAPC] D3_APC_3: 0x0
9953 23:42:16.207235 INFO: [APUAPC] D4_APC_0: 0xffffffff
9954 23:42:16.210658 INFO: [APUAPC] D4_APC_1: 0xffffffff
9955 23:42:16.213833 INFO: [APUAPC] D4_APC_2: 0x3fffff
9956 23:42:16.213912 INFO: [APUAPC] D4_APC_3: 0x0
9957 23:42:16.217526 INFO: [APUAPC] D5_APC_0: 0xffffffff
9958 23:42:16.220288 INFO: [APUAPC] D5_APC_1: 0xffffffff
9959 23:42:16.223829 INFO: [APUAPC] D5_APC_2: 0x3fffff
9960 23:42:16.227777 INFO: [APUAPC] D5_APC_3: 0x0
9961 23:42:16.230363 INFO: [APUAPC] D6_APC_0: 0xffffffff
9962 23:42:16.233981 INFO: [APUAPC] D6_APC_1: 0xffffffff
9963 23:42:16.236815 INFO: [APUAPC] D6_APC_2: 0x3fffff
9964 23:42:16.240574 INFO: [APUAPC] D6_APC_3: 0x0
9965 23:42:16.243647 INFO: [APUAPC] D7_APC_0: 0xffffffff
9966 23:42:16.247315 INFO: [APUAPC] D7_APC_1: 0xffffffff
9967 23:42:16.250347 INFO: [APUAPC] D7_APC_2: 0x3fffff
9968 23:42:16.253492 INFO: [APUAPC] D7_APC_3: 0x0
9969 23:42:16.257032 INFO: [APUAPC] D8_APC_0: 0xffffffff
9970 23:42:16.260394 INFO: [APUAPC] D8_APC_1: 0xffffffff
9971 23:42:16.263792 INFO: [APUAPC] D8_APC_2: 0x3fffff
9972 23:42:16.266886 INFO: [APUAPC] D8_APC_3: 0x0
9973 23:42:16.270161 INFO: [APUAPC] D9_APC_0: 0xffffffff
9974 23:42:16.273426 INFO: [APUAPC] D9_APC_1: 0xffffffff
9975 23:42:16.276773 INFO: [APUAPC] D9_APC_2: 0x3fffff
9976 23:42:16.280131 INFO: [APUAPC] D9_APC_3: 0x0
9977 23:42:16.283407 INFO: [APUAPC] D10_APC_0: 0xffffffff
9978 23:42:16.287286 INFO: [APUAPC] D10_APC_1: 0xffffffff
9979 23:42:16.290276 INFO: [APUAPC] D10_APC_2: 0x3fffff
9980 23:42:16.293726 INFO: [APUAPC] D10_APC_3: 0x0
9981 23:42:16.297656 INFO: [APUAPC] D11_APC_0: 0xffffffff
9982 23:42:16.300226 INFO: [APUAPC] D11_APC_1: 0xffffffff
9983 23:42:16.303994 INFO: [APUAPC] D11_APC_2: 0x3fffff
9984 23:42:16.307472 INFO: [APUAPC] D11_APC_3: 0x0
9985 23:42:16.310760 INFO: [APUAPC] D12_APC_0: 0xffffffff
9986 23:42:16.314017 INFO: [APUAPC] D12_APC_1: 0xffffffff
9987 23:42:16.317283 INFO: [APUAPC] D12_APC_2: 0x3fffff
9988 23:42:16.320471 INFO: [APUAPC] D12_APC_3: 0x0
9989 23:42:16.323591 INFO: [APUAPC] D13_APC_0: 0xffffffff
9990 23:42:16.327115 INFO: [APUAPC] D13_APC_1: 0xffffffff
9991 23:42:16.330225 INFO: [APUAPC] D13_APC_2: 0x3fffff
9992 23:42:16.334027 INFO: [APUAPC] D13_APC_3: 0x0
9993 23:42:16.337120 INFO: [APUAPC] D14_APC_0: 0xffffffff
9994 23:42:16.340720 INFO: [APUAPC] D14_APC_1: 0xffffffff
9995 23:42:16.344056 INFO: [APUAPC] D14_APC_2: 0x3fffff
9996 23:42:16.347139 INFO: [APUAPC] D14_APC_3: 0x0
9997 23:42:16.350595 INFO: [APUAPC] D15_APC_0: 0xffffffff
9998 23:42:16.353879 INFO: [APUAPC] D15_APC_1: 0xffffffff
9999 23:42:16.356898 INFO: [APUAPC] D15_APC_2: 0x3fffff
10000 23:42:16.359927 INFO: [APUAPC] D15_APC_3: 0x0
10001 23:42:16.363308 INFO: [APUAPC] APC_CON: 0x4
10002 23:42:16.366683 INFO: [NOCDAPC] D0_APC_0: 0x0
10003 23:42:16.369987 INFO: [NOCDAPC] D0_APC_1: 0x0
10004 23:42:16.373929 INFO: [NOCDAPC] D1_APC_0: 0x0
10005 23:42:16.374008 INFO: [NOCDAPC] D1_APC_1: 0xfff
10006 23:42:16.376713 INFO: [NOCDAPC] D2_APC_0: 0x0
10007 23:42:16.380252 INFO: [NOCDAPC] D2_APC_1: 0xfff
10008 23:42:16.383659 INFO: [NOCDAPC] D3_APC_0: 0x0
10009 23:42:16.386780 INFO: [NOCDAPC] D3_APC_1: 0xfff
10010 23:42:16.390665 INFO: [NOCDAPC] D4_APC_0: 0x0
10011 23:42:16.393361 INFO: [NOCDAPC] D4_APC_1: 0xfff
10012 23:42:16.397214 INFO: [NOCDAPC] D5_APC_0: 0x0
10013 23:42:16.400677 INFO: [NOCDAPC] D5_APC_1: 0xfff
10014 23:42:16.403773 INFO: [NOCDAPC] D6_APC_0: 0x0
10015 23:42:16.403859 INFO: [NOCDAPC] D6_APC_1: 0xfff
10016 23:42:16.407172 INFO: [NOCDAPC] D7_APC_0: 0x0
10017 23:42:16.410890 INFO: [NOCDAPC] D7_APC_1: 0xfff
10018 23:42:16.413916 INFO: [NOCDAPC] D8_APC_0: 0x0
10019 23:42:16.417453 INFO: [NOCDAPC] D8_APC_1: 0xfff
10020 23:42:16.420766 INFO: [NOCDAPC] D9_APC_0: 0x0
10021 23:42:16.423899 INFO: [NOCDAPC] D9_APC_1: 0xfff
10022 23:42:16.427443 INFO: [NOCDAPC] D10_APC_0: 0x0
10023 23:42:16.430213 INFO: [NOCDAPC] D10_APC_1: 0xfff
10024 23:42:16.434012 INFO: [NOCDAPC] D11_APC_0: 0x0
10025 23:42:16.437390 INFO: [NOCDAPC] D11_APC_1: 0xfff
10026 23:42:16.437498 INFO: [NOCDAPC] D12_APC_0: 0x0
10027 23:42:16.440371 INFO: [NOCDAPC] D12_APC_1: 0xfff
10028 23:42:16.443722 INFO: [NOCDAPC] D13_APC_0: 0x0
10029 23:42:16.446910 INFO: [NOCDAPC] D13_APC_1: 0xfff
10030 23:42:16.450216 INFO: [NOCDAPC] D14_APC_0: 0x0
10031 23:42:16.453811 INFO: [NOCDAPC] D14_APC_1: 0xfff
10032 23:42:16.456884 INFO: [NOCDAPC] D15_APC_0: 0x0
10033 23:42:16.460504 INFO: [NOCDAPC] D15_APC_1: 0xfff
10034 23:42:16.463674 INFO: [NOCDAPC] APC_CON: 0x4
10035 23:42:16.467403 INFO: [APUAPC] set_apusys_apc done
10036 23:42:16.470610 INFO: [DEVAPC] devapc_init done
10037 23:42:16.474147 INFO: GICv3 without legacy support detected.
10038 23:42:16.476718 INFO: ARM GICv3 driver initialized in EL3
10039 23:42:16.480145 INFO: Maximum SPI INTID supported: 639
10040 23:42:16.486877 INFO: BL31: Initializing runtime services
10041 23:42:16.490140 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10042 23:42:16.493766 INFO: SPM: enable CPC mode
10043 23:42:16.500319 INFO: mcdi ready for mcusys-off-idle and system suspend
10044 23:42:16.503842 INFO: BL31: Preparing for EL3 exit to normal world
10045 23:42:16.506757 INFO: Entry point address = 0x80000000
10046 23:42:16.510112 INFO: SPSR = 0x8
10047 23:42:16.515992
10048 23:42:16.516072
10049 23:42:16.516137
10050 23:42:16.518719 Starting depthcharge on Spherion...
10051 23:42:16.518800
10052 23:42:16.518863 Wipe memory regions:
10053 23:42:16.518922
10054 23:42:16.519594 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10055 23:42:16.519692 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10056 23:42:16.519776 Setting prompt string to ['asurada:']
10057 23:42:16.519853 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10058 23:42:16.521932 [0x00000040000000, 0x00000054600000)
10059 23:42:16.644247
10060 23:42:16.644358 [0x00000054660000, 0x00000080000000)
10061 23:42:16.905045
10062 23:42:16.905209 [0x000000821a7280, 0x000000ffe64000)
10063 23:42:17.649767
10064 23:42:17.649906 [0x00000100000000, 0x00000240000000)
10065 23:42:19.539613
10066 23:42:19.542613 Initializing XHCI USB controller at 0x11200000.
10067 23:42:20.580448
10068 23:42:20.583532 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10069 23:42:20.583620
10070 23:42:20.583684
10071 23:42:20.583962 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10073 23:42:20.684311 asurada: tftpboot 192.168.201.1 14172925/tftp-deploy-jxr6d2y5/kernel/image.itb 14172925/tftp-deploy-jxr6d2y5/kernel/cmdline
10074 23:42:20.684434 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10075 23:42:20.684515 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10076 23:42:20.689573 tftpboot 192.168.201.1 14172925/tftp-deploy-jxr6d2y5/kernel/image.itp-deploy-jxr6d2y5/kernel/cmdline
10077 23:42:20.689655
10078 23:42:20.689718 Waiting for link
10079 23:42:20.849617
10080 23:42:20.849754 R8152: Initializing
10081 23:42:20.849820
10082 23:42:20.853024 Version 6 (ocp_data = 5c30)
10083 23:42:20.853105
10084 23:42:20.855851 R8152: Done initializing
10085 23:42:20.855930
10086 23:42:20.855993 Adding net device
10087 23:42:22.790252
10088 23:42:22.790389 done.
10089 23:42:22.790455
10090 23:42:22.790513 MAC: 00:24:32:30:78:52
10091 23:42:22.790569
10092 23:42:22.793386 Sending DHCP discover... done.
10093 23:42:22.793465
10094 23:42:22.796807 Waiting for reply... done.
10095 23:42:22.796885
10096 23:42:22.800161 Sending DHCP request... done.
10097 23:42:22.800275
10098 23:42:22.804716 Waiting for reply... done.
10099 23:42:22.804795
10100 23:42:22.804859 My ip is 192.168.201.14
10101 23:42:22.804917
10102 23:42:22.808129 The DHCP server ip is 192.168.201.1
10103 23:42:22.808208
10104 23:42:22.814427 TFTP server IP predefined by user: 192.168.201.1
10105 23:42:22.814506
10106 23:42:22.821743 Bootfile predefined by user: 14172925/tftp-deploy-jxr6d2y5/kernel/image.itb
10107 23:42:22.821836
10108 23:42:22.821926 Sending tftp read request... done.
10109 23:42:22.824756
10110 23:42:22.828302 Waiting for the transfer...
10111 23:42:22.828380
10112 23:42:23.368492 00000000 ################################################################
10113 23:42:23.368627
10114 23:42:23.898231 00080000 ################################################################
10115 23:42:23.898413
10116 23:42:24.437031 00100000 ################################################################
10117 23:42:24.437162
10118 23:42:25.001650 00180000 ################################################################
10119 23:42:25.001827
10120 23:42:25.551263 00200000 ################################################################
10121 23:42:25.551394
10122 23:42:26.106222 00280000 ################################################################
10123 23:42:26.106367
10124 23:42:26.655987 00300000 ################################################################
10125 23:42:26.656115
10126 23:42:27.193859 00380000 ################################################################
10127 23:42:27.193990
10128 23:42:27.738009 00400000 ################################################################
10129 23:42:27.738142
10130 23:42:28.282556 00480000 ################################################################
10131 23:42:28.282686
10132 23:42:28.822251 00500000 ################################################################
10133 23:42:28.822399
10134 23:42:29.371435 00580000 ################################################################
10135 23:42:29.371584
10136 23:42:29.908202 00600000 ################################################################
10137 23:42:29.908349
10138 23:42:30.506461 00680000 ################################################################
10139 23:42:30.506606
10140 23:42:31.111025 00700000 ################################################################
10141 23:42:31.111162
10142 23:42:31.792334 00780000 ################################################################
10143 23:42:31.792842
10144 23:42:32.405931 00800000 ################################################################
10145 23:42:32.406062
10146 23:42:32.954978 00880000 ################################################################
10147 23:42:32.955135
10148 23:42:33.533724 00900000 ################################################################
10149 23:42:33.533866
10150 23:42:34.098006 00980000 ################################################################
10151 23:42:34.098145
10152 23:42:34.675895 00a00000 ################################################################
10153 23:42:34.676077
10154 23:42:35.268348 00a80000 ################################################################
10155 23:42:35.268501
10156 23:42:35.842532 00b00000 ################################################################
10157 23:42:35.842678
10158 23:42:36.439714 00b80000 ################################################################
10159 23:42:36.439850
10160 23:42:37.016947 00c00000 ################################################################
10161 23:42:37.017104
10162 23:42:37.622092 00c80000 ################################################################
10163 23:42:37.622242
10164 23:42:38.221177 00d00000 ################################################################
10165 23:42:38.221314
10166 23:42:38.804868 00d80000 ################################################################
10167 23:42:38.805053
10168 23:42:39.343040 00e00000 ################################################################
10169 23:42:39.343190
10170 23:42:39.890825 00e80000 ################################################################
10171 23:42:39.890971
10172 23:42:40.435089 00f00000 ################################################################
10173 23:42:40.435238
10174 23:42:40.979954 00f80000 ################################################################
10175 23:42:40.980103
10176 23:42:41.517874 01000000 ################################################################
10177 23:42:41.518013
10178 23:42:42.052960 01080000 ################################################################
10179 23:42:42.053118
10180 23:42:42.611714 01100000 ################################################################
10181 23:42:42.611849
10182 23:42:43.167398 01180000 ################################################################
10183 23:42:43.167553
10184 23:42:43.711694 01200000 ################################################################
10185 23:42:43.711823
10186 23:42:44.255008 01280000 ################################################################
10187 23:42:44.255144
10188 23:42:44.793811 01300000 ################################################################
10189 23:42:44.793941
10190 23:42:45.327173 01380000 ################################################################
10191 23:42:45.327311
10192 23:42:45.858466 01400000 ################################################################
10193 23:42:45.858595
10194 23:42:46.398311 01480000 ################################################################
10195 23:42:46.398448
10196 23:42:46.926098 01500000 ################################################################
10197 23:42:46.926229
10198 23:42:47.471895 01580000 ################################################################
10199 23:42:47.472047
10200 23:42:48.013621 01600000 ################################################################
10201 23:42:48.013814
10202 23:42:48.550264 01680000 ################################################################
10203 23:42:48.550425
10204 23:42:49.094011 01700000 ################################################################
10205 23:42:49.094164
10206 23:42:49.641310 01780000 ################################################################
10207 23:42:49.641455
10208 23:42:50.251370 01800000 ################################################################
10209 23:42:50.251878
10210 23:42:50.934304 01880000 ################################################################
10211 23:42:50.934819
10212 23:42:51.604190 01900000 ################################################################
10213 23:42:51.604722
10214 23:42:52.272690 01980000 ################################################################
10215 23:42:52.273238
10216 23:42:52.906110 01a00000 ################################################################
10217 23:42:52.906256
10218 23:42:53.528527 01a80000 ################################################################
10219 23:42:53.529065
10220 23:42:54.187083 01b00000 ################################################################
10221 23:42:54.187650
10222 23:42:54.890905 01b80000 ################################################################
10223 23:42:54.891412
10224 23:42:55.565901 01c00000 ################################################################
10225 23:42:55.566583
10226 23:42:56.162960 01c80000 ################################################################
10227 23:42:56.163611
10228 23:42:56.800453 01d00000 ################################################################
10229 23:42:56.801027
10230 23:42:57.401093 01d80000 ################################################################
10231 23:42:57.401252
10232 23:42:58.027296 01e00000 ################################################################
10233 23:42:58.027828
10234 23:42:58.670801 01e80000 ################################################################
10235 23:42:58.670947
10236 23:42:59.266182 01f00000 ################################################################
10237 23:42:59.266684
10238 23:42:59.925252 01f80000 ################################################################
10239 23:42:59.925792
10240 23:43:00.556515 02000000 ################################################################
10241 23:43:00.556665
10242 23:43:01.018867 02080000 ############################################### done.
10243 23:43:01.019498
10244 23:43:01.022188 The bootfile was 34457526 bytes long.
10245 23:43:01.022713
10246 23:43:01.025207 Sending tftp read request... done.
10247 23:43:01.025569
10248 23:43:01.028425 Waiting for the transfer...
10249 23:43:01.028970
10250 23:43:01.032186 00000000 # done.
10251 23:43:01.032611
10252 23:43:01.039193 Command line loaded dynamically from TFTP file: 14172925/tftp-deploy-jxr6d2y5/kernel/cmdline
10253 23:43:01.039885
10254 23:43:01.052244 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10255 23:43:01.052797
10256 23:43:01.053336 Loading FIT.
10257 23:43:01.053794
10258 23:43:01.056681 Image ramdisk-1 has 21346803 bytes.
10259 23:43:01.057188
10260 23:43:01.060122 Image fdt-1 has 47258 bytes.
10261 23:43:01.060600
10262 23:43:01.062417 Image kernel-1 has 13061430 bytes.
10263 23:43:01.062711
10264 23:43:01.072628 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10265 23:43:01.072928
10266 23:43:01.089035 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10267 23:43:01.089424
10268 23:43:01.095227 Choosing best match conf-1 for compat google,spherion-rev2.
10269 23:43:01.095520
10270 23:43:01.102996 Connected to device vid:did:rid of 1ae0:0028:00
10271 23:43:01.111435
10272 23:43:01.115010 tpm_get_response: command 0x17b, return code 0x0
10273 23:43:01.115426
10274 23:43:01.117871 ec_init: CrosEC protocol v3 supported (256, 248)
10275 23:43:01.122043
10276 23:43:01.124907 tpm_cleanup: add release locality here.
10277 23:43:01.125526
10278 23:43:01.126003 Shutting down all USB controllers.
10279 23:43:01.126459
10280 23:43:01.129273 Removing current net device
10281 23:43:01.129688
10282 23:43:01.135495 Exiting depthcharge with code 4 at timestamp: 74033055
10283 23:43:01.136034
10284 23:43:01.139285 LZMA decompressing kernel-1 to 0x821a6718
10285 23:43:01.139770
10286 23:43:01.142918 LZMA decompressing kernel-1 to 0x40000000
10287 23:43:02.750557
10288 23:43:02.750712 jumping to kernel
10289 23:43:02.751181 end: 2.2.4 bootloader-commands (duration 00:00:46) [common]
10290 23:43:02.751281 start: 2.2.5 auto-login-action (timeout 00:03:39) [common]
10291 23:43:02.751358 Setting prompt string to ['Linux version [0-9]']
10292 23:43:02.751427 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10293 23:43:02.751494 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10294 23:43:02.833414
10295 23:43:02.836859 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10296 23:43:02.840638 start: 2.2.5.1 login-action (timeout 00:03:39) [common]
10297 23:43:02.840740 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10298 23:43:02.840827 Setting prompt string to []
10299 23:43:02.840906 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10300 23:43:02.840988 Using line separator: #'\n'#
10301 23:43:02.841062 No login prompt set.
10302 23:43:02.841123 Parsing kernel messages
10303 23:43:02.841179 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10304 23:43:02.841284 [login-action] Waiting for messages, (timeout 00:03:39)
10305 23:43:02.841349 Waiting using forced prompt support (timeout 00:01:49)
10306 23:43:02.859928 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j217067-arm64-gcc-10-defconfig-arm64-chromebook-s48tj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024
10307 23:43:02.863301 [ 0.000000] random: crng init done
10308 23:43:02.866360 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10309 23:43:02.870553 [ 0.000000] efi: UEFI not found.
10310 23:43:02.879926 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10311 23:43:02.886576 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10312 23:43:02.896911 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10313 23:43:02.907024 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10314 23:43:02.913506 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10315 23:43:02.916460 [ 0.000000] printk: bootconsole [mtk8250] enabled
10316 23:43:02.925282 [ 0.000000] NUMA: No NUMA configuration found
10317 23:43:02.931535 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10318 23:43:02.938328 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10319 23:43:02.938452 [ 0.000000] Zone ranges:
10320 23:43:02.945029 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10321 23:43:02.948524 [ 0.000000] DMA32 empty
10322 23:43:02.955004 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10323 23:43:02.958373 [ 0.000000] Movable zone start for each node
10324 23:43:02.962221 [ 0.000000] Early memory node ranges
10325 23:43:02.968525 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10326 23:43:02.975229 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10327 23:43:02.982017 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10328 23:43:02.989006 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10329 23:43:02.995090 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10330 23:43:03.001903 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10331 23:43:03.059136 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10332 23:43:03.065270 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10333 23:43:03.071982 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10334 23:43:03.076127 [ 0.000000] psci: probing for conduit method from DT.
10335 23:43:03.082870 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10336 23:43:03.085423 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10337 23:43:03.089074 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10338 23:43:03.095893 [ 0.000000] psci: SMC Calling Convention v1.2
10339 23:43:03.102517 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10340 23:43:03.105402 [ 0.000000] Detected VIPT I-cache on CPU0
10341 23:43:03.112321 [ 0.000000] CPU features: detected: GIC system register CPU interface
10342 23:43:03.118576 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10343 23:43:03.125372 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10344 23:43:03.131308 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10345 23:43:03.138859 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10346 23:43:03.144914 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10347 23:43:03.152096 [ 0.000000] alternatives: applying boot alternatives
10348 23:43:03.155179 [ 0.000000] Fallback order for Node 0: 0
10349 23:43:03.161605 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10350 23:43:03.165117 [ 0.000000] Policy zone: Normal
10351 23:43:03.181438 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10352 23:43:03.191625 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10353 23:43:03.203037 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10354 23:43:03.212427 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10355 23:43:03.219173 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10356 23:43:03.222783 <6>[ 0.000000] software IO TLB: area num 8.
10357 23:43:03.279089 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10358 23:43:03.428354 <6>[ 0.000000] Memory: 7943340K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 409428K reserved, 32768K cma-reserved)
10359 23:43:03.435375 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10360 23:43:03.442077 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10361 23:43:03.445230 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10362 23:43:03.452004 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10363 23:43:03.458199 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10364 23:43:03.462410 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10365 23:43:03.472361 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10366 23:43:03.478855 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10367 23:43:03.483182 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10368 23:43:03.489466 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10369 23:43:03.493060 <6>[ 0.000000] GICv3: 608 SPIs implemented
10370 23:43:03.499654 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10371 23:43:03.503814 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10372 23:43:03.506172 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10373 23:43:03.516023 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10374 23:43:03.525986 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10375 23:43:03.539850 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10376 23:43:03.545648 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10377 23:43:03.554595 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10378 23:43:03.567997 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10379 23:43:03.575359 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10380 23:43:03.582297 <6>[ 0.009175] Console: colour dummy device 80x25
10381 23:43:03.591969 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10382 23:43:03.594923 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10383 23:43:03.601325 <6>[ 0.029216] LSM: Security Framework initializing
10384 23:43:03.608451 <6>[ 0.034153] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10385 23:43:03.617817 <6>[ 0.041967] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10386 23:43:03.624708 <6>[ 0.051437] cblist_init_generic: Setting adjustable number of callback queues.
10387 23:43:03.631506 <6>[ 0.058882] cblist_init_generic: Setting shift to 3 and lim to 1.
10388 23:43:03.641614 <6>[ 0.065221] cblist_init_generic: Setting adjustable number of callback queues.
10389 23:43:03.644449 <6>[ 0.072695] cblist_init_generic: Setting shift to 3 and lim to 1.
10390 23:43:03.651103 <6>[ 0.079134] rcu: Hierarchical SRCU implementation.
10391 23:43:03.658344 <6>[ 0.084150] rcu: Max phase no-delay instances is 1000.
10392 23:43:03.664772 <6>[ 0.091176] EFI services will not be available.
10393 23:43:03.667900 <6>[ 0.096135] smp: Bringing up secondary CPUs ...
10394 23:43:03.676209 <6>[ 0.101184] Detected VIPT I-cache on CPU1
10395 23:43:03.683328 <6>[ 0.101256] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10396 23:43:03.689268 <6>[ 0.101288] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10397 23:43:03.694878 <6>[ 0.101624] Detected VIPT I-cache on CPU2
10398 23:43:03.700128 <6>[ 0.101677] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10399 23:43:03.706105 <6>[ 0.101694] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10400 23:43:03.712554 <6>[ 0.101952] Detected VIPT I-cache on CPU3
10401 23:43:03.719559 <6>[ 0.101998] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10402 23:43:03.726207 <6>[ 0.102012] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10403 23:43:03.729247 <6>[ 0.102312] CPU features: detected: Spectre-v4
10404 23:43:03.735499 <6>[ 0.102319] CPU features: detected: Spectre-BHB
10405 23:43:03.738921 <6>[ 0.102324] Detected PIPT I-cache on CPU4
10406 23:43:03.745591 <6>[ 0.102383] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10407 23:43:03.752683 <6>[ 0.102399] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10408 23:43:03.755498 <6>[ 0.102697] Detected PIPT I-cache on CPU5
10409 23:43:03.766068 <6>[ 0.102762] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10410 23:43:03.772282 <6>[ 0.102778] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10411 23:43:03.775670 <6>[ 0.103058] Detected PIPT I-cache on CPU6
10412 23:43:03.782653 <6>[ 0.103124] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10413 23:43:03.788770 <6>[ 0.103140] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10414 23:43:03.792885 <6>[ 0.103437] Detected PIPT I-cache on CPU7
10415 23:43:03.802898 <6>[ 0.103503] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10416 23:43:03.808860 <6>[ 0.103519] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10417 23:43:03.811924 <6>[ 0.103567] smp: Brought up 1 node, 8 CPUs
10418 23:43:03.816117 <6>[ 0.244781] SMP: Total of 8 processors activated.
10419 23:43:03.822156 <6>[ 0.249733] CPU features: detected: 32-bit EL0 Support
10420 23:43:03.832641 <6>[ 0.255130] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10421 23:43:03.838841 <6>[ 0.263930] CPU features: detected: Common not Private translations
10422 23:43:03.842101 <6>[ 0.270406] CPU features: detected: CRC32 instructions
10423 23:43:03.848605 <6>[ 0.275757] CPU features: detected: RCpc load-acquire (LDAPR)
10424 23:43:03.855518 <6>[ 0.281738] CPU features: detected: LSE atomic instructions
10425 23:43:03.861976 <6>[ 0.287555] CPU features: detected: Privileged Access Never
10426 23:43:03.865419 <6>[ 0.293370] CPU features: detected: RAS Extension Support
10427 23:43:03.871916 <6>[ 0.299014] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10428 23:43:03.879384 <6>[ 0.306235] CPU: All CPU(s) started at EL2
10429 23:43:03.882316 <6>[ 0.310552] alternatives: applying system-wide alternatives
10430 23:43:03.893728 <6>[ 0.321441] devtmpfs: initialized
10431 23:43:03.906413 <6>[ 0.330253] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10432 23:43:03.916510 <6>[ 0.340211] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10433 23:43:03.919399 <6>[ 0.348111] pinctrl core: initialized pinctrl subsystem
10434 23:43:03.926862 <6>[ 0.354777] DMI not present or invalid.
10435 23:43:03.933767 <6>[ 0.359184] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10436 23:43:03.940003 <6>[ 0.366039] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10437 23:43:03.950446 <6>[ 0.373632] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10438 23:43:03.957458 <6>[ 0.381850] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10439 23:43:03.963555 <6>[ 0.390090] audit: initializing netlink subsys (disabled)
10440 23:43:03.970289 <5>[ 0.395781] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10441 23:43:03.976902 <6>[ 0.396489] thermal_sys: Registered thermal governor 'step_wise'
10442 23:43:03.983823 <6>[ 0.403743] thermal_sys: Registered thermal governor 'power_allocator'
10443 23:43:03.986829 <6>[ 0.409998] cpuidle: using governor menu
10444 23:43:03.993784 <6>[ 0.420952] NET: Registered PF_QIPCRTR protocol family
10445 23:43:04.000394 <6>[ 0.426431] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10446 23:43:04.007125 <6>[ 0.433535] ASID allocator initialised with 32768 entries
10447 23:43:04.010022 <6>[ 0.440108] Serial: AMBA PL011 UART driver
10448 23:43:04.020852 <4>[ 0.448914] Trying to register duplicate clock ID: 134
10449 23:43:04.079295 <6>[ 0.510030] KASLR enabled
10450 23:43:04.093246 <6>[ 0.517740] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10451 23:43:04.099879 <6>[ 0.524757] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10452 23:43:04.106506 <6>[ 0.531248] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10453 23:43:04.113910 <6>[ 0.538249] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10454 23:43:04.119571 <6>[ 0.544739] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10455 23:43:04.126929 <6>[ 0.551741] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10456 23:43:04.132865 <6>[ 0.558231] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10457 23:43:04.139698 <6>[ 0.565236] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10458 23:43:04.143150 <6>[ 0.572732] ACPI: Interpreter disabled.
10459 23:43:04.151396 <6>[ 0.579144] iommu: Default domain type: Translated
10460 23:43:04.158190 <6>[ 0.584253] iommu: DMA domain TLB invalidation policy: strict mode
10461 23:43:04.161773 <5>[ 0.590912] SCSI subsystem initialized
10462 23:43:04.167965 <6>[ 0.595079] usbcore: registered new interface driver usbfs
10463 23:43:04.174556 <6>[ 0.600810] usbcore: registered new interface driver hub
10464 23:43:04.177640 <6>[ 0.606362] usbcore: registered new device driver usb
10465 23:43:04.184185 <6>[ 0.612451] pps_core: LinuxPPS API ver. 1 registered
10466 23:43:04.194336 <6>[ 0.617644] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10467 23:43:04.197927 <6>[ 0.626985] PTP clock support registered
10468 23:43:04.201378 <6>[ 0.631225] EDAC MC: Ver: 3.0.0
10469 23:43:04.208892 <6>[ 0.636361] FPGA manager framework
10470 23:43:04.215838 <6>[ 0.640048] Advanced Linux Sound Architecture Driver Initialized.
10471 23:43:04.218251 <6>[ 0.646823] vgaarb: loaded
10472 23:43:04.225379 <6>[ 0.649912] clocksource: Switched to clocksource arch_sys_counter
10473 23:43:04.228996 <5>[ 0.656351] VFS: Disk quotas dquot_6.6.0
10474 23:43:04.234712 <6>[ 0.660534] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10475 23:43:04.239030 <6>[ 0.667722] pnp: PnP ACPI: disabled
10476 23:43:04.246995 <6>[ 0.674399] NET: Registered PF_INET protocol family
10477 23:43:04.256448 <6>[ 0.679994] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10478 23:43:04.267714 <6>[ 0.692318] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10479 23:43:04.277488 <6>[ 0.701134] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10480 23:43:04.284950 <6>[ 0.709105] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10481 23:43:04.291271 <6>[ 0.717801] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10482 23:43:04.302854 <6>[ 0.727556] TCP: Hash tables configured (established 65536 bind 65536)
10483 23:43:04.310100 <6>[ 0.734422] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10484 23:43:04.316318 <6>[ 0.741622] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10485 23:43:04.322882 <6>[ 0.749326] NET: Registered PF_UNIX/PF_LOCAL protocol family
10486 23:43:04.329409 <6>[ 0.755477] RPC: Registered named UNIX socket transport module.
10487 23:43:04.332780 <6>[ 0.761627] RPC: Registered udp transport module.
10488 23:43:04.339592 <6>[ 0.766559] RPC: Registered tcp transport module.
10489 23:43:04.346915 <6>[ 0.771491] RPC: Registered tcp NFSv4.1 backchannel transport module.
10490 23:43:04.349867 <6>[ 0.778154] PCI: CLS 0 bytes, default 64
10491 23:43:04.353019 <6>[ 0.782494] Unpacking initramfs...
10492 23:43:04.369658 <6>[ 0.794462] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10493 23:43:04.380118 <6>[ 0.803096] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10494 23:43:04.383009 <6>[ 0.811926] kvm [1]: IPA Size Limit: 40 bits
10495 23:43:04.389840 <6>[ 0.816455] kvm [1]: GICv3: no GICV resource entry
10496 23:43:04.393591 <6>[ 0.821476] kvm [1]: disabling GICv2 emulation
10497 23:43:04.399587 <6>[ 0.826166] kvm [1]: GIC system register CPU interface enabled
10498 23:43:04.403522 <6>[ 0.832323] kvm [1]: vgic interrupt IRQ18
10499 23:43:04.409958 <6>[ 0.836676] kvm [1]: VHE mode initialized successfully
10500 23:43:04.417466 <5>[ 0.843194] Initialise system trusted keyrings
10501 23:43:04.423865 <6>[ 0.847986] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10502 23:43:04.429992 <6>[ 0.857985] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10503 23:43:04.436608 <5>[ 0.864363] NFS: Registering the id_resolver key type
10504 23:43:04.440358 <5>[ 0.869680] Key type id_resolver registered
10505 23:43:04.447191 <5>[ 0.874093] Key type id_legacy registered
10506 23:43:04.453012 <6>[ 0.878375] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10507 23:43:04.460031 <6>[ 0.885298] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10508 23:43:04.466724 <6>[ 0.893013] 9p: Installing v9fs 9p2000 file system support
10509 23:43:04.503041 <5>[ 0.930810] Key type asymmetric registered
10510 23:43:04.506743 <5>[ 0.935140] Asymmetric key parser 'x509' registered
10511 23:43:04.516395 <6>[ 0.940285] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10512 23:43:04.519678 <6>[ 0.947902] io scheduler mq-deadline registered
10513 23:43:04.523393 <6>[ 0.952679] io scheduler kyber registered
10514 23:43:04.542602 <6>[ 0.969658] EINJ: ACPI disabled.
10515 23:43:04.574631 <4>[ 0.995528] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10516 23:43:04.584690 <4>[ 1.006160] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10517 23:43:04.599265 <6>[ 1.027089] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10518 23:43:04.607204 <6>[ 1.035112] printk: console [ttyS0] disabled
10519 23:43:04.636101 <6>[ 1.059746] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10520 23:43:04.642661 <6>[ 1.069225] printk: console [ttyS0] enabled
10521 23:43:04.645662 <6>[ 1.069225] printk: console [ttyS0] enabled
10522 23:43:04.653093 <6>[ 1.078123] printk: bootconsole [mtk8250] disabled
10523 23:43:04.654916 <6>[ 1.078123] printk: bootconsole [mtk8250] disabled
10524 23:43:04.662449 <6>[ 1.089406] SuperH (H)SCI(F) driver initialized
10525 23:43:04.665181 <6>[ 1.094688] msm_serial: driver initialized
10526 23:43:04.679671 <6>[ 1.103680] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10527 23:43:04.689520 <6>[ 1.112229] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10528 23:43:04.696015 <6>[ 1.120770] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10529 23:43:04.706322 <6>[ 1.129400] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10530 23:43:04.712652 <6>[ 1.138106] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10531 23:43:04.722435 <6>[ 1.146824] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10532 23:43:04.733147 <6>[ 1.155373] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10533 23:43:04.739436 <6>[ 1.164182] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10534 23:43:04.749544 <6>[ 1.172726] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10535 23:43:04.761017 <6>[ 1.188251] loop: module loaded
10536 23:43:04.767767 <6>[ 1.194180] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10537 23:43:04.789558 <4>[ 1.217533] mtk-pmic-keys: Failed to locate of_node [id: -1]
10538 23:43:04.797356 <6>[ 1.224368] megasas: 07.719.03.00-rc1
10539 23:43:04.806493 <6>[ 1.234038] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10540 23:43:04.814370 <6>[ 1.241289] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10541 23:43:04.830379 <6>[ 1.257786] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10542 23:43:04.886373 <6>[ 1.307556] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10543 23:43:05.259354 <6>[ 1.687452] Freeing initrd memory: 20844K
10544 23:43:05.275511 <6>[ 1.703321] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10545 23:43:05.286573 <6>[ 1.714368] tun: Universal TUN/TAP device driver, 1.6
10546 23:43:05.289780 <6>[ 1.720430] thunder_xcv, ver 1.0
10547 23:43:05.293913 <6>[ 1.723936] thunder_bgx, ver 1.0
10548 23:43:05.296965 <6>[ 1.727432] nicpf, ver 1.0
10549 23:43:05.306847 <6>[ 1.731442] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10550 23:43:05.310138 <6>[ 1.738917] hns3: Copyright (c) 2017 Huawei Corporation.
10551 23:43:05.313618 <6>[ 1.744509] hclge is initializing
10552 23:43:05.320272 <6>[ 1.748092] e1000: Intel(R) PRO/1000 Network Driver
10553 23:43:05.327445 <6>[ 1.753221] e1000: Copyright (c) 1999-2006 Intel Corporation.
10554 23:43:05.330127 <6>[ 1.759234] e1000e: Intel(R) PRO/1000 Network Driver
10555 23:43:05.337426 <6>[ 1.764449] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10556 23:43:05.344111 <6>[ 1.770633] igb: Intel(R) Gigabit Ethernet Network Driver
10557 23:43:05.350543 <6>[ 1.776283] igb: Copyright (c) 2007-2014 Intel Corporation.
10558 23:43:05.357607 <6>[ 1.782118] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10559 23:43:05.361333 <6>[ 1.788636] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10560 23:43:05.367248 <6>[ 1.795102] sky2: driver version 1.30
10561 23:43:05.373928 <6>[ 1.800017] usbcore: registered new device driver r8152-cfgselector
10562 23:43:05.380140 <6>[ 1.806554] usbcore: registered new interface driver r8152
10563 23:43:05.383735 <6>[ 1.812374] VFIO - User Level meta-driver version: 0.3
10564 23:43:05.392735 <6>[ 1.820583] usbcore: registered new interface driver usb-storage
10565 23:43:05.399277 <6>[ 1.827029] usbcore: registered new device driver onboard-usb-hub
10566 23:43:05.408551 <6>[ 1.836148] mt6397-rtc mt6359-rtc: registered as rtc0
10567 23:43:05.418209 <6>[ 1.841609] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T23:43:06 UTC (1717544586)
10568 23:43:05.422043 <6>[ 1.851165] i2c_dev: i2c /dev entries driver
10569 23:43:05.438258 <6>[ 1.862783] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10570 23:43:05.445177 <4>[ 1.871510] cpu cpu0: supply cpu not found, using dummy regulator
10571 23:43:05.451853 <4>[ 1.877943] cpu cpu1: supply cpu not found, using dummy regulator
10572 23:43:05.458245 <4>[ 1.884361] cpu cpu2: supply cpu not found, using dummy regulator
10573 23:43:05.465100 <4>[ 1.890757] cpu cpu3: supply cpu not found, using dummy regulator
10574 23:43:05.471854 <4>[ 1.897152] cpu cpu4: supply cpu not found, using dummy regulator
10575 23:43:05.478844 <4>[ 1.903546] cpu cpu5: supply cpu not found, using dummy regulator
10576 23:43:05.481667 <4>[ 1.909948] cpu cpu6: supply cpu not found, using dummy regulator
10577 23:43:05.488329 <4>[ 1.916355] cpu cpu7: supply cpu not found, using dummy regulator
10578 23:43:05.509088 <6>[ 1.936979] cpu cpu0: EM: created perf domain
10579 23:43:05.512559 <6>[ 1.941901] cpu cpu4: EM: created perf domain
10580 23:43:05.520640 <6>[ 1.947523] sdhci: Secure Digital Host Controller Interface driver
10581 23:43:05.526113 <6>[ 1.953955] sdhci: Copyright(c) Pierre Ossman
10582 23:43:05.533929 <6>[ 1.958913] Synopsys Designware Multimedia Card Interface Driver
10583 23:43:05.540013 <6>[ 1.965541] sdhci-pltfm: SDHCI platform and OF driver helper
10584 23:43:05.542776 <6>[ 1.965689] mmc0: CQHCI version 5.10
10585 23:43:05.549839 <6>[ 1.975679] ledtrig-cpu: registered to indicate activity on CPUs
10586 23:43:05.556582 <6>[ 1.982686] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10587 23:43:05.562869 <6>[ 1.989737] usbcore: registered new interface driver usbhid
10588 23:43:05.566622 <6>[ 1.995559] usbhid: USB HID core driver
10589 23:43:05.573212 <6>[ 1.999756] spi_master spi0: will run message pump with realtime priority
10590 23:43:05.615377 <6>[ 2.036191] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10591 23:43:05.633662 <6>[ 2.051169] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10592 23:43:05.636739 <6>[ 2.064610] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17014
10593 23:43:05.645023 <6>[ 2.072149] cros-ec-spi spi0.0: Chrome EC device registered
10594 23:43:05.651655 <6>[ 2.078160] mmc0: Command Queue Engine enabled
10595 23:43:05.658593 <6>[ 2.082889] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10596 23:43:05.661645 <6>[ 2.090346] mmcblk0: mmc0:0001 DA4128 116 GiB
10597 23:43:05.670843 <6>[ 2.098879] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10598 23:43:05.678485 <6>[ 2.106226] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10599 23:43:05.688684 <6>[ 2.110916] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10600 23:43:05.691856 <6>[ 2.112070] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10601 23:43:05.698663 <6>[ 2.122009] NET: Registered PF_PACKET protocol family
10602 23:43:05.705540 <6>[ 2.126613] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10603 23:43:05.709137 <6>[ 2.131352] 9pnet: Installing 9P2000 support
10604 23:43:05.715104 <5>[ 2.142370] Key type dns_resolver registered
10605 23:43:05.718637 <6>[ 2.147348] registered taskstats version 1
10606 23:43:05.724905 <5>[ 2.151732] Loading compiled-in X.509 certificates
10607 23:43:05.752972 <4>[ 2.173815] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10608 23:43:05.762935 <4>[ 2.184541] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10609 23:43:05.781642 <6>[ 2.209289] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10610 23:43:05.788619 <6>[ 2.216224] xhci-mtk 11200000.usb: xHCI Host Controller
10611 23:43:05.794947 <6>[ 2.221728] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10612 23:43:05.805095 <6>[ 2.229578] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10613 23:43:05.812352 <6>[ 2.239002] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10614 23:43:05.819017 <6>[ 2.245076] xhci-mtk 11200000.usb: xHCI Host Controller
10615 23:43:05.825594 <6>[ 2.250556] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10616 23:43:05.831583 <6>[ 2.258203] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10617 23:43:05.838463 <6>[ 2.265840] hub 1-0:1.0: USB hub found
10618 23:43:05.841568 <6>[ 2.269855] hub 1-0:1.0: 1 port detected
10619 23:43:05.848920 <6>[ 2.274129] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10620 23:43:05.855265 <6>[ 2.282675] hub 2-0:1.0: USB hub found
10621 23:43:05.858566 <6>[ 2.286682] hub 2-0:1.0: 1 port detected
10622 23:43:05.865613 <6>[ 2.293506] mtk-msdc 11f70000.mmc: Got CD GPIO
10623 23:43:05.878879 <6>[ 2.303459] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10624 23:43:05.885429 <6>[ 2.311491] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10625 23:43:05.895524 <4>[ 2.319419] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10626 23:43:05.906273 <6>[ 2.328953] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10627 23:43:05.912162 <6>[ 2.337031] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10628 23:43:05.919189 <6>[ 2.345045] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10629 23:43:05.928811 <6>[ 2.352966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10630 23:43:05.935454 <6>[ 2.360783] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10631 23:43:05.945901 <6>[ 2.368599] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10632 23:43:05.955900 <6>[ 2.378981] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10633 23:43:05.962243 <6>[ 2.387365] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10634 23:43:05.971820 <6>[ 2.395710] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10635 23:43:05.979329 <6>[ 2.404048] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10636 23:43:05.988549 <6>[ 2.412386] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10637 23:43:05.995947 <6>[ 2.420724] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10638 23:43:06.005197 <6>[ 2.429061] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10639 23:43:06.011867 <6>[ 2.437399] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10640 23:43:06.021998 <6>[ 2.445738] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10641 23:43:06.029282 <6>[ 2.454075] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10642 23:43:06.039267 <6>[ 2.462415] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10643 23:43:06.044825 <6>[ 2.470755] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10644 23:43:06.055243 <6>[ 2.479093] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10645 23:43:06.061646 <6>[ 2.487430] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10646 23:43:06.071540 <6>[ 2.495767] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10647 23:43:06.078269 <6>[ 2.504496] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10648 23:43:06.084615 <6>[ 2.511630] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10649 23:43:06.091218 <6>[ 2.518386] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10650 23:43:06.097680 <6>[ 2.525138] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10651 23:43:06.104280 <6>[ 2.532061] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10652 23:43:06.114713 <6>[ 2.538932] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10653 23:43:06.124550 <6>[ 2.548067] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10654 23:43:06.134002 <6>[ 2.557187] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10655 23:43:06.143878 <6>[ 2.566481] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10656 23:43:06.150662 <6>[ 2.575947] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10657 23:43:06.160422 <6>[ 2.585413] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10658 23:43:06.170409 <6>[ 2.594532] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10659 23:43:06.181205 <6>[ 2.603998] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10660 23:43:06.190272 <6>[ 2.613118] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10661 23:43:06.200658 <6>[ 2.622412] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10662 23:43:06.210095 <6>[ 2.632572] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10663 23:43:06.220017 <6>[ 2.644074] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10664 23:43:06.273302 <6>[ 2.698190] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10665 23:43:06.427834 <6>[ 2.856141] hub 1-1:1.0: USB hub found
10666 23:43:06.431101 <6>[ 2.860683] hub 1-1:1.0: 4 ports detected
10667 23:43:06.440852 <6>[ 2.869257] hub 1-1:1.0: USB hub found
10668 23:43:06.444600 <6>[ 2.873651] hub 1-1:1.0: 4 ports detected
10669 23:43:06.552991 <6>[ 2.978389] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10670 23:43:06.580859 <6>[ 3.008487] hub 2-1:1.0: USB hub found
10671 23:43:06.583364 <6>[ 3.013006] hub 2-1:1.0: 3 ports detected
10672 23:43:06.593326 <6>[ 3.021445] hub 2-1:1.0: USB hub found
10673 23:43:06.596315 <6>[ 3.025822] hub 2-1:1.0: 3 ports detected
10674 23:43:06.765227 <6>[ 3.190246] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10675 23:43:06.897912 <6>[ 3.326145] hub 1-1.4:1.0: USB hub found
10676 23:43:06.900994 <6>[ 3.330825] hub 1-1.4:1.0: 2 ports detected
10677 23:43:06.910652 <6>[ 3.338863] hub 1-1.4:1.0: USB hub found
10678 23:43:06.913786 <6>[ 3.343417] hub 1-1.4:1.0: 2 ports detected
10679 23:43:06.977252 <6>[ 3.402418] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10680 23:43:07.085755 <6>[ 3.510923] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10681 23:43:07.122243 <4>[ 3.547398] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10682 23:43:07.132062 <4>[ 3.556493] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10683 23:43:07.172324 <6>[ 3.600029] r8152 2-1.3:1.0 eth0: v1.12.13
10684 23:43:07.209101 <6>[ 3.634246] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10685 23:43:07.400998 <6>[ 3.826262] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10686 23:43:08.736936 <6>[ 5.164295] r8152 2-1.3:1.0 eth0: carrier on
10687 23:43:11.649876 <5>[ 5.190037] Sending DHCP requests .., OK
10688 23:43:11.655577 <6>[ 8.082370] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10689 23:43:11.658966 <6>[ 8.090671] IP-Config: Complete:
10690 23:43:11.672749 <6>[ 8.094172] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10691 23:43:11.679645 <6>[ 8.104885] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10692 23:43:11.686571 <6>[ 8.113506] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10693 23:43:11.692491 <6>[ 8.113517] nameserver0=192.168.201.1
10694 23:43:11.695444 <6>[ 8.125685] clk: Disabling unused clocks
10695 23:43:11.698674 <6>[ 8.131246] ALSA device list:
10696 23:43:11.705370 <6>[ 8.134507] No soundcards found.
10697 23:43:11.713311 <6>[ 8.142329] Freeing unused kernel memory: 8512K
10698 23:43:11.716738 <6>[ 8.147363] Run /init as init process
10699 23:43:11.744608 Starting syslogd: OK
10700 23:43:11.751356 Starting klogd: OK
10701 23:43:11.760687 Running sysctl: OK
10702 23:43:11.766501 Populating /dev using udev: <30>[ 8.197498] udevd[195]: starting version 3.2.9
10703 23:43:11.778259 <27>[ 8.206666] udevd[195]: specified user 'tss' unknown
10704 23:43:11.784297 <27>[ 8.212076] udevd[195]: specified group 'tss' unknown
10705 23:43:11.787960 <30>[ 8.218691] udevd[196]: starting eudev-3.2.9
10706 23:43:11.809608 <27>[ 8.238547] udevd[196]: specified user 'tss' unknown
10707 23:43:11.816365 <27>[ 8.243925] udevd[196]: specified group 'tss' unknown
10708 23:43:11.969050 <6>[ 8.394599] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10709 23:43:11.976474 <6>[ 8.405555] remoteproc remoteproc0: scp is available
10710 23:43:11.983522 <6>[ 8.410963] remoteproc remoteproc0: powering up scp
10711 23:43:11.989949 <6>[ 8.416190] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10712 23:43:12.000376 <3>[ 8.419550] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 23:43:12.003616 <6>[ 8.424649] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10714 23:43:12.013084 <3>[ 8.432835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 23:43:12.019473 <6>[ 8.436797] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10716 23:43:12.029585 <6>[ 8.436847] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10717 23:43:12.036283 <6>[ 8.436867] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10718 23:43:12.046618 <6>[ 8.469303] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10719 23:43:12.052751 <3>[ 8.471582] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 23:43:12.064211 <3>[ 8.487448] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 23:43:12.069463 <3>[ 8.495820] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 23:43:12.079269 <3>[ 8.504033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 23:43:12.082676 <6>[ 8.508376] mc: Linux media interface: v0.10
10724 23:43:12.089362 <3>[ 8.512193] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 23:43:12.099405 <4>[ 8.512842] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10726 23:43:12.105948 <4>[ 8.512963] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10727 23:43:12.113188 <4>[ 8.523023] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10728 23:43:12.119859 <4>[ 8.523023] Fallback method does not support PEC.
10729 23:43:12.126244 <3>[ 8.524739] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10730 23:43:12.135950 <3>[ 8.549263] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10731 23:43:12.142879 <3>[ 8.553061] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 23:43:12.149822 <6>[ 8.555163] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10733 23:43:12.156540 <6>[ 8.555168] pci_bus 0000:00: root bus resource [bus 00-ff]
10734 23:43:12.163616 <6>[ 8.555172] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10735 23:43:12.173710 <6>[ 8.555174] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10736 23:43:12.180364 <6>[ 8.555208] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10737 23:43:12.187086 <6>[ 8.555221] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10738 23:43:12.189978 <6>[ 8.555291] pci 0000:00:00.0: supports D1 D2
10739 23:43:12.200142 <6>[ 8.555293] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10740 23:43:12.206759 <6>[ 8.556286] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10741 23:43:12.214066 <6>[ 8.556365] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10742 23:43:12.220154 <6>[ 8.556390] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10743 23:43:12.226737 <6>[ 8.556406] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10744 23:43:12.236264 <6>[ 8.556421] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10745 23:43:12.240488 <6>[ 8.556525] pci 0000:01:00.0: supports D1 D2
10746 23:43:12.246139 <6>[ 8.556527] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10747 23:43:12.256407 <6>[ 8.558422] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10748 23:43:12.266988 <6>[ 8.558709] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10749 23:43:12.272964 <6>[ 8.563217] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10750 23:43:12.282711 <6>[ 8.563266] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10751 23:43:12.289900 <6>[ 8.563274] remoteproc remoteproc0: remote processor scp is now up
10752 23:43:12.296473 <3>[ 8.569897] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 23:43:12.302580 <6>[ 8.570045] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10754 23:43:12.312903 <6>[ 8.570078] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10755 23:43:12.318937 <6>[ 8.570081] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10756 23:43:12.326124 <6>[ 8.570090] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10757 23:43:12.336061 <6>[ 8.570102] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10758 23:43:12.342337 <6>[ 8.570115] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10759 23:43:12.348920 <6>[ 8.570127] pci 0000:00:00.0: PCI bridge to [bus 01]
10760 23:43:12.356300 <6>[ 8.570132] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10761 23:43:12.362610 <6>[ 8.570253] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10762 23:43:12.368841 <6>[ 8.570734] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10763 23:43:12.375704 <6>[ 8.571154] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10764 23:43:12.382109 <3>[ 8.598946] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10765 23:43:12.392298 <3>[ 8.607570] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 23:43:12.399510 <3>[ 8.607574] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 23:43:12.409502 <3>[ 8.607628] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 23:43:12.415519 <6>[ 8.625234] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10769 23:43:12.425542 <3>[ 8.625828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 23:43:12.431799 <6>[ 8.647911] videodev: Linux video capture interface: v2.00
10771 23:43:12.439116 <6>[ 8.649684] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10772 23:43:12.448863 <6>[ 8.651877] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10773 23:43:12.455240 <3>[ 8.654682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 23:43:12.461878 <3>[ 8.654691] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10775 23:43:12.471941 <5>[ 8.656076] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10776 23:43:12.475311 <6>[ 8.674922] Bluetooth: Core ver 2.22
10777 23:43:12.482000 <3>[ 8.681093] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 23:43:12.491615 <5>[ 8.685094] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10779 23:43:12.498446 <5>[ 8.685325] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10780 23:43:12.508480 <4>[ 8.685381] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10781 23:43:12.511445 <6>[ 8.685387] cfg80211: failed to load regulatory.db
10782 23:43:12.518330 <6>[ 8.691238] NET: Registered PF_BLUETOOTH protocol family
10783 23:43:12.525530 <3>[ 8.700244] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 23:43:12.532291 <6>[ 8.707239] Bluetooth: HCI device and connection manager initialized
10785 23:43:12.538377 <6>[ 8.707256] Bluetooth: HCI socket layer initialized
10786 23:43:12.544888 <6>[ 8.723557] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10787 23:43:12.548172 <6>[ 8.730269] Bluetooth: L2CAP socket layer initialized
10788 23:43:12.554888 <6>[ 8.730279] Bluetooth: SCO socket layer initialized
10789 23:43:12.568000 <6>[ 8.738389] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10790 23:43:12.574734 <6>[ 8.754234] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10791 23:43:12.581425 <6>[ 8.761419] usbcore: registered new interface driver uvcvideo
10792 23:43:12.584664 <6>[ 8.797856] usbcore: registered new interface driver btusb
10793 23:43:12.592064 <6>[ 8.799106] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10794 23:43:12.604895 <4>[ 8.799206] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10795 23:43:12.611914 <3>[ 8.799216] Bluetooth: hci0: Failed to load firmware file (-2)
10796 23:43:12.614958 <3>[ 8.799219] Bluetooth: hci0: Failed to set up firmware (-2)
10797 23:43:12.621758 <6>[ 8.799220] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10798 23:43:12.631800 <4>[ 8.799223] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10799 23:43:12.638242 <6>[ 8.818231] mt7921e 0000:01:00.0: ASIC revision: 79610010
10800 23:43:12.740454 <6>[ 9.166181] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10801 23:43:12.740601 <6>[ 9.166181]
10802 23:43:12.744831 done
10803 23:43:12.753596 Saving random seed: OK
10804 23:43:12.764774 Starting network: ip: RTNETLINK answers: File exists
10805 23:43:12.768330 FAIL
10806 23:43:12.797413 Starting dropbear sshd: <6>[ 9.226612] NET: Registered PF_INET6 protocol family
10807 23:43:12.803885 <6>[ 9.233316] Segment Routing with IPv6
10808 23:43:12.807326 <6>[ 9.237300] In-situ OAM (IOAM) with IPv6
10809 23:43:12.811151 OK
10810 23:43:12.820262 /bin/sh: can't access tty; job control turned off
10811 23:43:12.820610 Matched prompt #10: / #
10813 23:43:12.820807 Setting prompt string to ['/ #']
10814 23:43:12.820897 end: 2.2.5.1 login-action (duration 00:00:10) [common]
10816 23:43:12.821136 end: 2.2.5 auto-login-action (duration 00:00:10) [common]
10817 23:43:12.821223 start: 2.2.6 expect-shell-connection (timeout 00:03:29) [common]
10818 23:43:12.821292 Setting prompt string to ['/ #']
10819 23:43:12.821350 Forcing a shell prompt, looking for ['/ #']
10821 23:43:12.871572 / #
10822 23:43:12.871725 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10823 23:43:12.871802 Waiting using forced prompt support (timeout 00:02:30)
10824 23:43:12.877173
10825 23:43:12.877453 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10826 23:43:12.877549 start: 2.2.7 export-device-env (timeout 00:03:29) [common]
10827 23:43:12.877637 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10828 23:43:12.877722 end: 2.2 depthcharge-retry (duration 00:01:31) [common]
10829 23:43:12.877801 end: 2 depthcharge-action (duration 00:01:31) [common]
10830 23:43:12.877886 start: 3 lava-test-retry (timeout 00:01:00) [common]
10831 23:43:12.877967 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10832 23:43:12.878041 Using namespace: common
10834 23:43:12.978390 / # #
10835 23:43:12.978555 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10836 23:43:12.984395 #
10837 23:43:12.984661 Using /lava-14172925
10839 23:43:13.085006 / # export SHELL=/bin/sh
10840 23:43:13.085227 <6>[ 9.435313] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10841 23:43:13.090580 export SHELL=/bin/sh
10843 23:43:13.191153 / # . /lava-14172925/environment
10844 23:43:13.196636 . /lava-14172925/environment
10846 23:43:13.297157 / # /lava-14172925/bin/lava-test-runner /lava-14172925/0
10847 23:43:13.297314 Test shell timeout: 10s (minimum of the action and connection timeout)
10848 23:43:13.302714 /lava-14172925/bin/lava-test-runner /lava-14172925/0
10849 23:43:13.323542 + export 'TESTRUN_ID=0_dmesg'
10850 23:43:13.330433 +<8>[ 9.758306] <LAVA_SIGNAL_STARTRUN 0_dmesg 14172925_1.5.2.3.1>
10851 23:43:13.330690 Received signal: <STARTRUN> 0_dmesg 14172925_1.5.2.3.1
10852 23:43:13.330760 Starting test lava.0_dmesg (14172925_1.5.2.3.1)
10853 23:43:13.330877 Skipping test definition patterns.
10854 23:43:13.333554 cd /lava-14172925/0/tests/0_dmesg
10855 23:43:13.333634 + cat uuid
10856 23:43:13.337191 + UUID=14172925_1.5.2.3.1
10857 23:43:13.337270 + set +x
10858 23:43:13.343415 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10859 23:43:13.353203 <8>[ 9.777446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10860 23:43:13.353453 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10862 23:43:13.371932 <8>[ 9.798058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10863 23:43:13.372211 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10865 23:43:13.394979 <8>[ 9.821067] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10866 23:43:13.395240 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10868 23:43:13.398345 + set +x
10869 23:43:13.402196 <8>[ 9.830389] <LAVA_SIGNAL_ENDRUN 0_dmesg 14172925_1.5.2.3.1>
10870 23:43:13.402445 Received signal: <ENDRUN> 0_dmesg 14172925_1.5.2.3.1
10871 23:43:13.402525 Ending use of test pattern.
10872 23:43:13.402585 Ending test lava.0_dmesg (14172925_1.5.2.3.1), duration 0.07
10874 23:43:13.405832 <LAVA_TEST_RUNNER EXIT>
10875 23:43:13.406081 ok: lava_test_shell seems to have completed
10876 23:43:13.406184 alert: pass
crit: pass
emerg: pass
10877 23:43:13.406269 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10878 23:43:13.406354 end: 3 lava-test-retry (duration 00:00:01) [common]
10879 23:43:13.406435 start: 4 finalize (timeout 00:08:06) [common]
10880 23:43:13.406521 start: 4.1 power-off (timeout 00:00:30) [common]
10881 23:43:13.406668 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
10882 23:43:13.482916 >> Command sent successfully.
10883 23:43:13.485314 Returned 0 in 0 seconds
10884 23:43:13.585832 end: 4.1 power-off (duration 00:00:00) [common]
10886 23:43:13.586155 start: 4.2 read-feedback (timeout 00:08:06) [common]
10887 23:43:13.586417 Listened to connection for namespace 'common' for up to 1s
10888 23:43:14.587377 Finalising connection for namespace 'common'
10889 23:43:14.587556 Disconnecting from shell: Finalise
10890 23:43:14.587637 / #
10891 23:43:14.687973 end: 4.2 read-feedback (duration 00:00:01) [common]
10892 23:43:14.688157 end: 4 finalize (duration 00:00:01) [common]
10893 23:43:14.688272 Cleaning after the job
10894 23:43:14.688369 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/ramdisk
10895 23:43:14.690710 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/kernel
10896 23:43:14.696958 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/dtb
10897 23:43:14.697162 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172925/tftp-deploy-jxr6d2y5/modules
10898 23:43:14.702038 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14172925
10899 23:43:14.740255 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14172925
10900 23:43:14.740423 Job finished correctly