Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 23:41:05.631195 lava-dispatcher, installed at version: 2024.03
2 23:41:05.631421 start: 0 validate
3 23:41:05.631559 Start time: 2024-06-04 23:41:05.631552+00:00 (UTC)
4 23:41:05.631691 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:41:05.631820 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:41:05.891561 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:41:05.891737 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:41:06.148172 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:41:06.148354 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:41:39.936987 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:41:39.937694 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:41:40.442847 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:41:40.443611 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:41:40.707037 validate duration: 35.08
16 23:41:40.708358 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:41:40.708928 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:41:40.709414 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:41:40.710029 Not decompressing ramdisk as can be used compressed.
20 23:41:40.710526 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/initrd.cpio.gz
21 23:41:40.710893 saving as /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/ramdisk/initrd.cpio.gz
22 23:41:40.711264 total size: 5628182 (5 MB)
23 23:41:43.994796 progress 0 % (0 MB)
24 23:41:44.003950 progress 5 % (0 MB)
25 23:41:44.013084 progress 10 % (0 MB)
26 23:41:44.020243 progress 15 % (0 MB)
27 23:41:44.026028 progress 20 % (1 MB)
28 23:41:44.029927 progress 25 % (1 MB)
29 23:41:44.033541 progress 30 % (1 MB)
30 23:41:44.036793 progress 35 % (1 MB)
31 23:41:44.039368 progress 40 % (2 MB)
32 23:41:44.042056 progress 45 % (2 MB)
33 23:41:44.044264 progress 50 % (2 MB)
34 23:41:44.046600 progress 55 % (2 MB)
35 23:41:44.048711 progress 60 % (3 MB)
36 23:41:44.050601 progress 65 % (3 MB)
37 23:41:44.052552 progress 70 % (3 MB)
38 23:41:44.054235 progress 75 % (4 MB)
39 23:41:44.056166 progress 80 % (4 MB)
40 23:41:44.057686 progress 85 % (4 MB)
41 23:41:44.059477 progress 90 % (4 MB)
42 23:41:44.061232 progress 95 % (5 MB)
43 23:41:44.062644 progress 100 % (5 MB)
44 23:41:44.062857 5 MB downloaded in 3.35 s (1.60 MB/s)
45 23:41:44.063014 end: 1.1.1 http-download (duration 00:00:03) [common]
47 23:41:44.063256 end: 1.1 download-retry (duration 00:00:03) [common]
48 23:41:44.063345 start: 1.2 download-retry (timeout 00:09:57) [common]
49 23:41:44.063435 start: 1.2.1 http-download (timeout 00:09:57) [common]
50 23:41:44.063573 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:41:44.063644 saving as /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/kernel/Image
52 23:41:44.063711 total size: 54682112 (52 MB)
53 23:41:44.063795 No compression specified
54 23:41:44.064944 progress 0 % (0 MB)
55 23:41:44.082040 progress 5 % (2 MB)
56 23:41:44.103626 progress 10 % (5 MB)
57 23:41:44.121449 progress 15 % (7 MB)
58 23:41:44.144391 progress 20 % (10 MB)
59 23:41:44.158308 progress 25 % (13 MB)
60 23:41:44.172085 progress 30 % (15 MB)
61 23:41:44.185997 progress 35 % (18 MB)
62 23:41:44.199807 progress 40 % (20 MB)
63 23:41:44.213518 progress 45 % (23 MB)
64 23:41:44.227503 progress 50 % (26 MB)
65 23:41:44.241404 progress 55 % (28 MB)
66 23:41:44.255358 progress 60 % (31 MB)
67 23:41:44.269090 progress 65 % (33 MB)
68 23:41:44.283069 progress 70 % (36 MB)
69 23:41:44.296743 progress 75 % (39 MB)
70 23:41:44.310656 progress 80 % (41 MB)
71 23:41:44.324292 progress 85 % (44 MB)
72 23:41:44.337999 progress 90 % (46 MB)
73 23:41:44.351919 progress 95 % (49 MB)
74 23:41:44.365555 progress 100 % (52 MB)
75 23:41:44.365807 52 MB downloaded in 0.30 s (172.63 MB/s)
76 23:41:44.365965 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:41:44.366278 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:41:44.366366 start: 1.3 download-retry (timeout 00:09:56) [common]
80 23:41:44.366451 start: 1.3.1 http-download (timeout 00:09:56) [common]
81 23:41:44.366587 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:41:44.366656 saving as /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/dtb/mt8192-asurada-spherion-r0.dtb
83 23:41:44.366718 total size: 47258 (0 MB)
84 23:41:44.366779 No compression specified
85 23:41:44.367894 progress 69 % (0 MB)
86 23:41:44.368172 progress 100 % (0 MB)
87 23:41:44.368331 0 MB downloaded in 0.00 s (27.99 MB/s)
88 23:41:44.368452 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:41:44.368676 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:41:44.368761 start: 1.4 download-retry (timeout 00:09:56) [common]
92 23:41:44.368845 start: 1.4.1 http-download (timeout 00:09:56) [common]
93 23:41:44.368958 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm/20240313.0/arm64/full.rootfs.tar.xz
94 23:41:44.369027 saving as /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/nfsrootfs/full.rootfs.tar
95 23:41:44.369089 total size: 107552908 (102 MB)
96 23:41:44.369151 Using unxz to decompress xz
97 23:41:44.373274 progress 0 % (0 MB)
98 23:41:44.673219 progress 5 % (5 MB)
99 23:41:44.988966 progress 10 % (10 MB)
100 23:41:45.300180 progress 15 % (15 MB)
101 23:41:45.621133 progress 20 % (20 MB)
102 23:41:45.884449 progress 25 % (25 MB)
103 23:41:46.172448 progress 30 % (30 MB)
104 23:41:46.483421 progress 35 % (35 MB)
105 23:41:46.648683 progress 40 % (41 MB)
106 23:41:46.844661 progress 45 % (46 MB)
107 23:41:47.150602 progress 50 % (51 MB)
108 23:41:47.447321 progress 55 % (56 MB)
109 23:41:47.772374 progress 60 % (61 MB)
110 23:41:48.099206 progress 65 % (66 MB)
111 23:41:48.419532 progress 70 % (71 MB)
112 23:41:48.743612 progress 75 % (76 MB)
113 23:41:49.042072 progress 80 % (82 MB)
114 23:41:49.350268 progress 85 % (87 MB)
115 23:41:49.654305 progress 90 % (92 MB)
116 23:41:49.961881 progress 95 % (97 MB)
117 23:41:50.294310 progress 100 % (102 MB)
118 23:41:50.299397 102 MB downloaded in 5.93 s (17.30 MB/s)
119 23:41:50.299742 end: 1.4.1 http-download (duration 00:00:06) [common]
121 23:41:50.300168 end: 1.4 download-retry (duration 00:00:06) [common]
122 23:41:50.300304 start: 1.5 download-retry (timeout 00:09:50) [common]
123 23:41:50.300437 start: 1.5.1 http-download (timeout 00:09:50) [common]
124 23:41:50.300640 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:41:50.300750 saving as /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/modules/modules.tar
126 23:41:50.300849 total size: 8603924 (8 MB)
127 23:41:50.300952 Using unxz to decompress xz
128 23:41:50.306259 progress 0 % (0 MB)
129 23:41:50.327016 progress 5 % (0 MB)
130 23:41:50.352914 progress 10 % (0 MB)
131 23:41:50.379366 progress 15 % (1 MB)
132 23:41:50.404741 progress 20 % (1 MB)
133 23:41:50.430832 progress 25 % (2 MB)
134 23:41:50.456362 progress 30 % (2 MB)
135 23:41:50.480304 progress 35 % (2 MB)
136 23:41:50.507042 progress 40 % (3 MB)
137 23:41:50.532581 progress 45 % (3 MB)
138 23:41:50.557627 progress 50 % (4 MB)
139 23:41:50.583158 progress 55 % (4 MB)
140 23:41:50.608680 progress 60 % (4 MB)
141 23:41:50.635105 progress 65 % (5 MB)
142 23:41:50.661946 progress 70 % (5 MB)
143 23:41:50.687834 progress 75 % (6 MB)
144 23:41:50.713777 progress 80 % (6 MB)
145 23:41:50.738009 progress 85 % (7 MB)
146 23:41:50.762601 progress 90 % (7 MB)
147 23:41:50.793644 progress 95 % (7 MB)
148 23:41:50.823812 progress 100 % (8 MB)
149 23:41:50.829596 8 MB downloaded in 0.53 s (15.52 MB/s)
150 23:41:50.829947 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:41:50.830409 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:41:50.830556 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 23:41:50.830699 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 23:41:52.965690 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14172911/extract-nfsrootfs-_uzfte3l
156 23:41:52.965892 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 23:41:52.965995 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:41:52.966285 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8
159 23:41:52.966424 makedir: /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin
160 23:41:52.966546 makedir: /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/tests
161 23:41:52.966650 makedir: /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/results
162 23:41:52.966754 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-add-keys
163 23:41:52.966899 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-add-sources
164 23:41:52.967030 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-background-process-start
165 23:41:52.967161 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-background-process-stop
166 23:41:52.967290 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-common-functions
167 23:41:52.967417 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-echo-ipv4
168 23:41:52.967545 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-install-packages
169 23:41:52.967672 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-installed-packages
170 23:41:52.967798 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-os-build
171 23:41:52.967924 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-probe-channel
172 23:41:52.968051 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-probe-ip
173 23:41:52.968178 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-target-ip
174 23:41:52.968309 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-target-mac
175 23:41:52.968437 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-target-storage
176 23:41:52.968576 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-test-case
177 23:41:52.968703 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-test-event
178 23:41:52.968829 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-test-feedback
179 23:41:52.968955 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-test-raise
180 23:41:52.969081 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-test-reference
181 23:41:52.969207 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-test-runner
182 23:41:52.969332 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-test-set
183 23:41:52.969456 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-test-shell
184 23:41:52.969583 Updating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-install-packages (oe)
185 23:41:52.969736 Updating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/bin/lava-installed-packages (oe)
186 23:41:52.969861 Creating /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/environment
187 23:41:52.969958 LAVA metadata
188 23:41:52.970026 - LAVA_JOB_ID=14172911
189 23:41:52.970091 - LAVA_DISPATCHER_IP=192.168.201.1
190 23:41:52.970199 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
191 23:41:52.970269 skipped lava-vland-overlay
192 23:41:52.970345 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 23:41:52.970427 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
194 23:41:52.970494 skipped lava-multinode-overlay
195 23:41:52.970570 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 23:41:52.970649 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
197 23:41:52.970724 Loading test definitions
198 23:41:52.970814 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
199 23:41:52.970887 Using /lava-14172911 at stage 0
200 23:41:52.971201 uuid=14172911_1.6.2.3.1 testdef=None
201 23:41:52.971293 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 23:41:52.971380 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
203 23:41:52.971902 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 23:41:52.972134 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
206 23:41:52.972789 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 23:41:52.973026 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
209 23:41:52.973655 runner path: /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/0/tests/0_dmesg test_uuid 14172911_1.6.2.3.1
210 23:41:52.973816 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 23:41:52.974030 Creating lava-test-runner.conf files
213 23:41:52.974096 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14172911/lava-overlay-rjitihi8/lava-14172911/0 for stage 0
214 23:41:52.974195 - 0_dmesg
215 23:41:52.974295 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 23:41:52.974383 start: 1.6.2.4 compress-overlay (timeout 00:09:48) [common]
217 23:41:52.980424 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 23:41:52.980532 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:48) [common]
219 23:41:52.980619 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 23:41:52.980706 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 23:41:52.980793 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:48) [common]
222 23:41:53.146130 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 23:41:53.146583 start: 1.6.4 extract-modules (timeout 00:09:48) [common]
224 23:41:53.146711 extracting modules file /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172911/extract-nfsrootfs-_uzfte3l
225 23:41:53.366559 extracting modules file /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172911/extract-overlay-ramdisk-sp9h1b30/ramdisk
226 23:41:53.587472 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 23:41:53.587645 start: 1.6.5 apply-overlay-tftp (timeout 00:09:47) [common]
228 23:41:53.587737 [common] Applying overlay to NFS
229 23:41:53.587806 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172911/compress-overlay-tpas1qix/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14172911/extract-nfsrootfs-_uzfte3l
230 23:41:53.594453 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 23:41:53.594569 start: 1.6.6 configure-preseed-file (timeout 00:09:47) [common]
232 23:41:53.594660 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 23:41:53.594752 start: 1.6.7 compress-ramdisk (timeout 00:09:47) [common]
234 23:41:53.594833 Building ramdisk /var/lib/lava/dispatcher/tmp/14172911/extract-overlay-ramdisk-sp9h1b30/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14172911/extract-overlay-ramdisk-sp9h1b30/ramdisk
235 23:41:53.901497 >> 130337 blocks
236 23:41:55.951773 rename /var/lib/lava/dispatcher/tmp/14172911/extract-overlay-ramdisk-sp9h1b30/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/ramdisk/ramdisk.cpio.gz
237 23:41:55.952234 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 23:41:55.952363 start: 1.6.8 prepare-kernel (timeout 00:09:45) [common]
239 23:41:55.952468 start: 1.6.8.1 prepare-fit (timeout 00:09:45) [common]
240 23:41:55.952567 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/kernel/Image']
241 23:42:09.891462 Returned 0 in 13 seconds
242 23:42:09.992123 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/kernel/image.itb
243 23:42:10.366587 output: FIT description: Kernel Image image with one or more FDT blobs
244 23:42:10.366976 output: Created: Wed Jun 5 00:42:10 2024
245 23:42:10.367060 output: Image 0 (kernel-1)
246 23:42:10.367156 output: Description:
247 23:42:10.367250 output: Created: Wed Jun 5 00:42:10 2024
248 23:42:10.367345 output: Type: Kernel Image
249 23:42:10.367441 output: Compression: lzma compressed
250 23:42:10.367535 output: Data Size: 13061430 Bytes = 12755.30 KiB = 12.46 MiB
251 23:42:10.367601 output: Architecture: AArch64
252 23:42:10.367661 output: OS: Linux
253 23:42:10.367721 output: Load Address: 0x00000000
254 23:42:10.367784 output: Entry Point: 0x00000000
255 23:42:10.367842 output: Hash algo: crc32
256 23:42:10.367901 output: Hash value: ecfb5096
257 23:42:10.367999 output: Image 1 (fdt-1)
258 23:42:10.368088 output: Description: mt8192-asurada-spherion-r0
259 23:42:10.368177 output: Created: Wed Jun 5 00:42:10 2024
260 23:42:10.368266 output: Type: Flat Device Tree
261 23:42:10.368356 output: Compression: uncompressed
262 23:42:10.368445 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
263 23:42:10.368531 output: Architecture: AArch64
264 23:42:10.368622 output: Hash algo: crc32
265 23:42:10.368709 output: Hash value: 0f8e4d2e
266 23:42:10.368797 output: Image 2 (ramdisk-1)
267 23:42:10.368887 output: Description: unavailable
268 23:42:10.368972 output: Created: Wed Jun 5 00:42:10 2024
269 23:42:10.369063 output: Type: RAMDisk Image
270 23:42:10.369151 output: Compression: Unknown Compression
271 23:42:10.369235 output: Data Size: 18735077 Bytes = 18295.97 KiB = 17.87 MiB
272 23:42:10.369324 output: Architecture: AArch64
273 23:42:10.369413 output: OS: Linux
274 23:42:10.369499 output: Load Address: unavailable
275 23:42:10.369583 output: Entry Point: unavailable
276 23:42:10.369673 output: Hash algo: crc32
277 23:42:10.369763 output: Hash value: 4f38e635
278 23:42:10.369848 output: Default Configuration: 'conf-1'
279 23:42:10.369933 output: Configuration 0 (conf-1)
280 23:42:10.370024 output: Description: mt8192-asurada-spherion-r0
281 23:42:10.370111 output: Kernel: kernel-1
282 23:42:10.370206 output: Init Ramdisk: ramdisk-1
283 23:42:10.370292 output: FDT: fdt-1
284 23:42:10.370381 output: Loadables: kernel-1
285 23:42:10.370445 output:
286 23:42:10.370657 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 23:42:10.370752 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 23:42:10.370884 end: 1.6 prepare-tftp-overlay (duration 00:00:20) [common]
289 23:42:10.371017 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:30) [common]
290 23:42:10.371145 No LXC device requested
291 23:42:10.371270 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 23:42:10.371395 start: 1.8 deploy-device-env (timeout 00:09:30) [common]
293 23:42:10.371507 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 23:42:10.371609 Checking files for TFTP limit of 4294967296 bytes.
295 23:42:10.372292 end: 1 tftp-deploy (duration 00:00:30) [common]
296 23:42:10.372439 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 23:42:10.372571 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 23:42:10.372749 substitutions:
299 23:42:10.372869 - {DTB}: 14172911/tftp-deploy-jrgn1tix/dtb/mt8192-asurada-spherion-r0.dtb
300 23:42:10.372975 - {INITRD}: 14172911/tftp-deploy-jrgn1tix/ramdisk/ramdisk.cpio.gz
301 23:42:10.373087 - {KERNEL}: 14172911/tftp-deploy-jrgn1tix/kernel/Image
302 23:42:10.373189 - {LAVA_MAC}: None
303 23:42:10.373297 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14172911/extract-nfsrootfs-_uzfte3l
304 23:42:10.373394 - {NFS_SERVER_IP}: 192.168.201.1
305 23:42:10.373485 - {PRESEED_CONFIG}: None
306 23:42:10.373573 - {PRESEED_LOCAL}: None
307 23:42:10.373663 - {RAMDISK}: 14172911/tftp-deploy-jrgn1tix/ramdisk/ramdisk.cpio.gz
308 23:42:10.373755 - {ROOT_PART}: None
309 23:42:10.373843 - {ROOT}: None
310 23:42:10.373929 - {SERVER_IP}: 192.168.201.1
311 23:42:10.374016 - {TEE}: None
312 23:42:10.374124 Parsed boot commands:
313 23:42:10.374254 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 23:42:10.374507 Parsed boot commands: tftpboot 192.168.201.1 14172911/tftp-deploy-jrgn1tix/kernel/image.itb 14172911/tftp-deploy-jrgn1tix/kernel/cmdline
315 23:42:10.374636 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 23:42:10.374770 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 23:42:10.374908 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 23:42:10.375001 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 23:42:10.375078 Not connected, no need to disconnect.
320 23:42:10.375155 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 23:42:10.375239 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 23:42:10.375308 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-9'
323 23:42:10.379478 Setting prompt string to ['lava-test: # ']
324 23:42:10.379974 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 23:42:10.380127 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 23:42:10.380269 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 23:42:10.380404 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 23:42:10.380715 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-9']
329 23:42:24.415944 Returned 0 in 14 seconds
330 23:42:24.516639 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
332 23:42:24.516991 end: 2.2.2 reset-device (duration 00:00:14) [common]
333 23:42:24.517090 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
334 23:42:24.517182 Setting prompt string to 'Starting depthcharge on Spherion...'
335 23:42:24.517253 Changing prompt to 'Starting depthcharge on Spherion...'
336 23:42:24.517319 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
337 23:42:24.517843 [Enter `^Ec?' for help]
338 23:42:24.517975
339 23:42:24.518093
340 23:42:24.518231 F0: 102B 0000
341 23:42:24.518328
342 23:42:24.518421 F3: 1001 0000 [0200]
343 23:42:24.518512
344 23:42:24.518600 F3: 1001 0000
345 23:42:24.518688
346 23:42:24.518777 F7: 102D 0000
347 23:42:24.518863
348 23:42:24.518948 F1: 0000 0000
349 23:42:24.519034
350 23:42:24.519119 V0: 0000 0000 [0001]
351 23:42:24.519204
352 23:42:24.519288 00: 0007 8000
353 23:42:24.519388
354 23:42:24.519475 01: 0000 0000
355 23:42:24.519561
356 23:42:24.519646 BP: 0C00 0209 [0000]
357 23:42:24.519730
358 23:42:24.519814 G0: 1182 0000
359 23:42:24.519897
360 23:42:24.519980 EC: 0000 0021 [4000]
361 23:42:24.520037
362 23:42:24.520091 S7: 0000 0000 [0000]
363 23:42:24.520145
364 23:42:24.520199 CC: 0000 0000 [0001]
365 23:42:24.520253
366 23:42:24.520308 T0: 0000 0040 [010F]
367 23:42:24.520374
368 23:42:24.520545 Jump to BL
369 23:42:24.520649
370 23:42:24.520710
371 23:42:24.520766
372 23:42:24.520822 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
373 23:42:24.520882 ARM64: Exception handlers installed.
374 23:42:24.520938 ARM64: Testing exception
375 23:42:24.520993 ARM64: Done test exception
376 23:42:24.521048 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
377 23:42:24.521103 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
378 23:42:24.521159 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
379 23:42:24.521213 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
380 23:42:24.521274 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
381 23:42:24.521330 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
382 23:42:24.521408 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
383 23:42:24.521500 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
384 23:42:24.521587 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
385 23:42:24.521672 WDT: Last reset was cold boot
386 23:42:24.521757 SPI1(PAD0) initialized at 2873684 Hz
387 23:42:24.521895 SPI5(PAD0) initialized at 992727 Hz
388 23:42:24.522025 VBOOT: Loading verstage.
389 23:42:24.522147 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
390 23:42:24.522234 FMAP: Found "FLASH" version 1.1 at 0x20000.
391 23:42:24.522292 FMAP: base = 0x0 size = 0x800000 #areas = 25
392 23:42:24.522348 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
393 23:42:24.522402 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
394 23:42:24.522458 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
395 23:42:24.522513 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
396 23:42:24.522568
397 23:42:24.522622
398 23:42:24.522677 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
399 23:42:24.522732 ARM64: Exception handlers installed.
400 23:42:24.522786 ARM64: Testing exception
401 23:42:24.522840 ARM64: Done test exception
402 23:42:24.522894 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
403 23:42:24.522948 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
404 23:42:24.523002 Probing TPM: . done!
405 23:42:24.523056 TPM ready after 0 ms
406 23:42:24.523110 Connected to device vid:did:rid of 1ae0:0028:00
407 23:42:24.523165 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
408 23:42:24.523220 Initialized TPM device CR50 revision 0
409 23:42:24.523274 tlcl_send_startup: Startup return code is 0
410 23:42:24.523328 TPM: setup succeeded
411 23:42:24.523382 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
412 23:42:24.523469 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
413 23:42:24.523549 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
414 23:42:24.523606 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 23:42:24.523662 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
416 23:42:24.523717 in-header: 03 07 00 00 08 00 00 00
417 23:42:24.523771 in-data: aa e4 47 04 13 02 00 00
418 23:42:24.523825 Chrome EC: UHEPI supported
419 23:42:24.523880 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
420 23:42:24.523935 in-header: 03 a9 00 00 08 00 00 00
421 23:42:24.523989 in-data: 84 60 60 08 00 00 00 00
422 23:42:24.524042 Phase 1
423 23:42:24.524097 FMAP: area GBB found @ 3f5000 (12032 bytes)
424 23:42:24.524152 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
425 23:42:24.524206 VB2:vb2_check_recovery() Recovery was requested manually
426 23:42:24.524261 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
427 23:42:24.524315 Recovery requested (1009000e)
428 23:42:24.524368 TPM: Extending digest for VBOOT: boot mode into PCR 0
429 23:42:24.524422 tlcl_extend: response is 0
430 23:42:24.524476 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
431 23:42:24.524531 tlcl_extend: response is 0
432 23:42:24.524585 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
433 23:42:24.524639 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
434 23:42:24.524694 BS: bootblock times (exec / console): total (unknown) / 148 ms
435 23:42:24.524747
436 23:42:24.524802
437 23:42:24.524855 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
438 23:42:24.524910 ARM64: Exception handlers installed.
439 23:42:24.524964 ARM64: Testing exception
440 23:42:24.525018 ARM64: Done test exception
441 23:42:24.525072 pmic_efuse_setting: Set efuses in 11 msecs
442 23:42:24.525126 pmwrap_interface_init: Select PMIF_VLD_RDY
443 23:42:24.525180 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
444 23:42:24.525234 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
445 23:42:24.525486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
446 23:42:24.525581 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
447 23:42:24.525795 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
448 23:42:24.525940 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
449 23:42:24.526038 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
450 23:42:24.526126 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
451 23:42:24.526241 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
452 23:42:24.526300 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
453 23:42:24.526356 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
454 23:42:24.526412 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
455 23:42:24.526467 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
456 23:42:24.526522 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
457 23:42:24.526576 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
458 23:42:24.526631 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
459 23:42:24.526686 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
460 23:42:24.526739 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
461 23:42:24.526794 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
462 23:42:24.526848 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
463 23:42:24.526902 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
464 23:42:24.526956 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
465 23:42:24.527012 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
466 23:42:24.527066 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
467 23:42:24.527120 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
468 23:42:24.527175 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
469 23:42:24.527229 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
470 23:42:24.527283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
471 23:42:24.527337 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
472 23:42:24.527391 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
473 23:42:24.527446 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
474 23:42:24.527500 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
475 23:42:24.527554 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
476 23:42:24.527609 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
477 23:42:24.527663 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
478 23:42:24.527716 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
479 23:42:24.527770 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
480 23:42:24.527824 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
481 23:42:24.527878 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
482 23:42:24.527931 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
483 23:42:24.527985 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
484 23:42:24.528038 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
485 23:42:24.528092 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
486 23:42:24.528145 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
487 23:42:24.528199 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
488 23:42:24.528252 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
489 23:42:24.528306 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
490 23:42:24.528359 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
491 23:42:24.528413 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
492 23:42:24.528467 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
493 23:42:24.528520 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
494 23:42:24.528574 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
495 23:42:24.528629 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
496 23:42:24.528683 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
497 23:42:24.528737 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
498 23:42:24.528792 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
499 23:42:24.528846 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
500 23:42:24.528900 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
501 23:42:24.528954 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 23:42:24.529007 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x32
503 23:42:24.529061 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
504 23:42:24.529116 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
505 23:42:24.529170 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
506 23:42:24.529223 [RTC]rtc_get_frequency_meter,154: input=15, output=835
507 23:42:24.529277 [RTC]rtc_get_frequency_meter,154: input=7, output=710
508 23:42:24.529330 [RTC]rtc_get_frequency_meter,154: input=11, output=772
509 23:42:24.529384 [RTC]rtc_get_frequency_meter,154: input=13, output=804
510 23:42:24.529439 [RTC]rtc_get_frequency_meter,154: input=12, output=788
511 23:42:24.529492 [RTC]rtc_get_frequency_meter,154: input=12, output=788
512 23:42:24.529545 [RTC]rtc_get_frequency_meter,154: input=13, output=802
513 23:42:24.529599 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
514 23:42:24.529653 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
515 23:42:24.529894 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
516 23:42:24.530009 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
517 23:42:24.530121 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
518 23:42:24.530223 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
519 23:42:24.530280 ADC[4]: Raw value=904879 ID=7
520 23:42:24.530335 ADC[3]: Raw value=213282 ID=1
521 23:42:24.530390 RAM Code: 0x71
522 23:42:24.530445 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
523 23:42:24.530546 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
524 23:42:24.530629 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
525 23:42:24.530686 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
526 23:42:24.530741 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
527 23:42:24.530795 in-header: 03 07 00 00 08 00 00 00
528 23:42:24.530850 in-data: aa e4 47 04 13 02 00 00
529 23:42:24.530904 Chrome EC: UHEPI supported
530 23:42:24.530959 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
531 23:42:24.531014 in-header: 03 a9 00 00 08 00 00 00
532 23:42:24.531068 in-data: 84 60 60 08 00 00 00 00
533 23:42:24.531122 MRC: failed to locate region type 0.
534 23:42:24.531185 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
535 23:42:24.531248 DRAM-K: Running full calibration
536 23:42:24.531359 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
537 23:42:24.531506 header.status = 0x0
538 23:42:24.531597 header.version = 0x6 (expected: 0x6)
539 23:42:24.531671 header.size = 0xd00 (expected: 0xd00)
540 23:42:24.531729 header.flags = 0x0
541 23:42:24.531785 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
542 23:42:24.531841 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
543 23:42:24.531897 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
544 23:42:24.531952 dram_init: ddr_geometry: 2
545 23:42:24.532007 [EMI] MDL number = 2
546 23:42:24.532071 [EMI] Get MDL freq = 0
547 23:42:24.532126 dram_init: ddr_type: 0
548 23:42:24.532180 is_discrete_lpddr4: 1
549 23:42:24.532235 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
550 23:42:24.532288
551 23:42:24.532342
552 23:42:24.532396 [Bian_co] ETT version 0.0.0.1
553 23:42:24.532457 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
554 23:42:24.532514
555 23:42:24.532568 dramc_set_vcore_voltage set vcore to 650000
556 23:42:24.532624 Read voltage for 800, 4
557 23:42:24.532678 Vio18 = 0
558 23:42:24.532732 Vcore = 650000
559 23:42:24.532786 Vdram = 0
560 23:42:24.532839 Vddq = 0
561 23:42:24.532894 Vmddr = 0
562 23:42:24.532959 dram_init: config_dvfs: 1
563 23:42:24.533016 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
564 23:42:24.533071 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
565 23:42:24.533126 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
566 23:42:24.533180 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
567 23:42:24.533235 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
568 23:42:24.533290 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
569 23:42:24.533344 MEM_TYPE=3, freq_sel=18
570 23:42:24.533404 sv_algorithm_assistance_LP4_1600
571 23:42:24.533460 ============ PULL DRAM RESETB DOWN ============
572 23:42:24.533515 ========== PULL DRAM RESETB DOWN end =========
573 23:42:24.533570 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
574 23:42:24.533624 ===================================
575 23:42:24.533679 LPDDR4 DRAM CONFIGURATION
576 23:42:24.533733 ===================================
577 23:42:24.533788 EX_ROW_EN[0] = 0x0
578 23:42:24.533842 EX_ROW_EN[1] = 0x0
579 23:42:24.533912 LP4Y_EN = 0x0
580 23:42:24.533998 WORK_FSP = 0x0
581 23:42:24.534083 WL = 0x2
582 23:42:24.534197 RL = 0x2
583 23:42:24.534271 BL = 0x2
584 23:42:24.534325 RPST = 0x0
585 23:42:24.534389 RD_PRE = 0x0
586 23:42:24.534444 WR_PRE = 0x1
587 23:42:24.534498 WR_PST = 0x0
588 23:42:24.534552 DBI_WR = 0x0
589 23:42:24.534606 DBI_RD = 0x0
590 23:42:24.534659 OTF = 0x1
591 23:42:24.534713 ===================================
592 23:42:24.534768 ===================================
593 23:42:24.534830 ANA top config
594 23:42:24.534887 ===================================
595 23:42:24.534942 DLL_ASYNC_EN = 0
596 23:42:24.534996 ALL_SLAVE_EN = 1
597 23:42:24.535050 NEW_RANK_MODE = 1
598 23:42:24.535107 DLL_IDLE_MODE = 1
599 23:42:24.535161 LP45_APHY_COMB_EN = 1
600 23:42:24.535221 TX_ODT_DIS = 1
601 23:42:24.535277 NEW_8X_MODE = 1
602 23:42:24.535332 ===================================
603 23:42:24.535386 ===================================
604 23:42:24.535441 data_rate = 1600
605 23:42:24.535495 CKR = 1
606 23:42:24.535549 DQ_P2S_RATIO = 8
607 23:42:24.535603 ===================================
608 23:42:24.535657 CA_P2S_RATIO = 8
609 23:42:24.535711 DQ_CA_OPEN = 0
610 23:42:24.535764 DQ_SEMI_OPEN = 0
611 23:42:24.535826 CA_SEMI_OPEN = 0
612 23:42:24.535881 CA_FULL_RATE = 0
613 23:42:24.535935 DQ_CKDIV4_EN = 1
614 23:42:24.535989 CA_CKDIV4_EN = 1
615 23:42:24.536043 CA_PREDIV_EN = 0
616 23:42:24.536097 PH8_DLY = 0
617 23:42:24.536166 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
618 23:42:24.536223 DQ_AAMCK_DIV = 4
619 23:42:24.536277 CA_AAMCK_DIV = 4
620 23:42:24.536331 CA_ADMCK_DIV = 4
621 23:42:24.536385 DQ_TRACK_CA_EN = 0
622 23:42:24.536439 CA_PICK = 800
623 23:42:24.536493 CA_MCKIO = 800
624 23:42:24.536547 MCKIO_SEMI = 0
625 23:42:24.536601 PLL_FREQ = 3068
626 23:42:24.536698 DQ_UI_PI_RATIO = 32
627 23:42:24.536751 CA_UI_PI_RATIO = 0
628 23:42:24.536805 ===================================
629 23:42:24.536897 ===================================
630 23:42:24.536983 memory_type:LPDDR4
631 23:42:24.537083 GP_NUM : 10
632 23:42:24.537233 SRAM_EN : 1
633 23:42:24.537337 MD32_EN : 0
634 23:42:24.537606 ===================================
635 23:42:24.537673 [ANA_INIT] >>>>>>>>>>>>>>
636 23:42:24.537732 <<<<<< [CONFIGURE PHASE]: ANA_TX
637 23:42:24.537813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
638 23:42:24.537901 ===================================
639 23:42:24.537987 data_rate = 1600,PCW = 0X7600
640 23:42:24.538073 ===================================
641 23:42:24.538159 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
642 23:42:24.538261 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
643 23:42:24.538318 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
644 23:42:24.538381 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
645 23:42:24.538436 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
646 23:42:24.538491 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
647 23:42:24.538545 [ANA_INIT] flow start
648 23:42:24.538599 [ANA_INIT] PLL >>>>>>>>
649 23:42:24.538663 [ANA_INIT] PLL <<<<<<<<
650 23:42:24.538767 [ANA_INIT] MIDPI >>>>>>>>
651 23:42:24.538904 [ANA_INIT] MIDPI <<<<<<<<
652 23:42:24.539000 [ANA_INIT] DLL >>>>>>>>
653 23:42:24.539059 [ANA_INIT] flow end
654 23:42:24.539115 ============ LP4 DIFF to SE enter ============
655 23:42:24.539172 ============ LP4 DIFF to SE exit ============
656 23:42:24.539227 [ANA_INIT] <<<<<<<<<<<<<
657 23:42:24.539283 [Flow] Enable top DCM control >>>>>
658 23:42:24.539338 [Flow] Enable top DCM control <<<<<
659 23:42:24.539392 Enable DLL master slave shuffle
660 23:42:24.539447 ==============================================================
661 23:42:24.539502 Gating Mode config
662 23:42:24.539556 ==============================================================
663 23:42:24.539611 Config description:
664 23:42:24.539665 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
665 23:42:24.539721 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
666 23:42:24.539776 SELPH_MODE 0: By rank 1: By Phase
667 23:42:24.539831 ==============================================================
668 23:42:24.539885 GAT_TRACK_EN = 1
669 23:42:24.539939 RX_GATING_MODE = 2
670 23:42:24.539994 RX_GATING_TRACK_MODE = 2
671 23:42:24.540048 SELPH_MODE = 1
672 23:42:24.540102 PICG_EARLY_EN = 1
673 23:42:24.540156 VALID_LAT_VALUE = 1
674 23:42:24.540210 ==============================================================
675 23:42:24.540273 Enter into Gating configuration >>>>
676 23:42:24.540357 Exit from Gating configuration <<<<
677 23:42:24.540415 Enter into DVFS_PRE_config >>>>>
678 23:42:24.540469 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
679 23:42:24.540526 Exit from DVFS_PRE_config <<<<<
680 23:42:24.540580 Enter into PICG configuration >>>>
681 23:42:24.540634 Exit from PICG configuration <<<<
682 23:42:24.540688 [RX_INPUT] configuration >>>>>
683 23:42:24.540742 [RX_INPUT] configuration <<<<<
684 23:42:24.540796 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
685 23:42:24.540850 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
686 23:42:24.540904 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
687 23:42:24.540959 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
688 23:42:24.541014 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
689 23:42:24.541068 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
690 23:42:24.541123 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
691 23:42:24.541177 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
692 23:42:24.541231 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
693 23:42:24.541286 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
694 23:42:24.541339 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
695 23:42:24.541396 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
696 23:42:24.541451 ===================================
697 23:42:24.541505 LPDDR4 DRAM CONFIGURATION
698 23:42:24.541559 ===================================
699 23:42:24.541613 EX_ROW_EN[0] = 0x0
700 23:42:24.541667 EX_ROW_EN[1] = 0x0
701 23:42:24.541720 LP4Y_EN = 0x0
702 23:42:24.541773 WORK_FSP = 0x0
703 23:42:24.541827 WL = 0x2
704 23:42:24.541880 RL = 0x2
705 23:42:24.541933 BL = 0x2
706 23:42:24.542003 RPST = 0x0
707 23:42:24.542057 RD_PRE = 0x0
708 23:42:24.542112 WR_PRE = 0x1
709 23:42:24.542175 WR_PST = 0x0
710 23:42:24.542246 DBI_WR = 0x0
711 23:42:24.542300 DBI_RD = 0x0
712 23:42:24.542353 OTF = 0x1
713 23:42:24.542407 ===================================
714 23:42:24.542462 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
715 23:42:24.542516 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
716 23:42:24.542570 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
717 23:42:24.542625 ===================================
718 23:42:24.542679 LPDDR4 DRAM CONFIGURATION
719 23:42:24.542733 ===================================
720 23:42:24.542786 EX_ROW_EN[0] = 0x10
721 23:42:24.542840 EX_ROW_EN[1] = 0x0
722 23:42:24.542894 LP4Y_EN = 0x0
723 23:42:24.542957 WORK_FSP = 0x0
724 23:42:24.543013 WL = 0x2
725 23:42:24.543068 RL = 0x2
726 23:42:24.543121 BL = 0x2
727 23:42:24.543175 RPST = 0x0
728 23:42:24.543228 RD_PRE = 0x0
729 23:42:24.543282 WR_PRE = 0x1
730 23:42:24.543337 WR_PST = 0x0
731 23:42:24.543390 DBI_WR = 0x0
732 23:42:24.543444 DBI_RD = 0x0
733 23:42:24.543497 OTF = 0x1
734 23:42:24.543551 ===================================
735 23:42:24.543605 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
736 23:42:24.543659 nWR fixed to 40
737 23:42:24.543715 [ModeRegInit_LP4] CH0 RK0
738 23:42:24.543768 [ModeRegInit_LP4] CH0 RK1
739 23:42:24.543822 [ModeRegInit_LP4] CH1 RK0
740 23:42:24.543876 [ModeRegInit_LP4] CH1 RK1
741 23:42:24.543930 match AC timing 13
742 23:42:24.543983 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
743 23:42:24.544228 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
744 23:42:24.544289 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
745 23:42:24.544346 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
746 23:42:24.544401 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
747 23:42:24.544456 [EMI DOE] emi_dcm 0
748 23:42:24.544510 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
749 23:42:24.544565 ==
750 23:42:24.544633 Dram Type= 6, Freq= 0, CH_0, rank 0
751 23:42:24.544691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
752 23:42:24.544745 ==
753 23:42:24.544800 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
754 23:42:24.544855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
755 23:42:24.544910 [CA 0] Center 37 (7~68) winsize 62
756 23:42:24.544974 [CA 1] Center 36 (6~67) winsize 62
757 23:42:24.545030 [CA 2] Center 34 (4~65) winsize 62
758 23:42:24.545085 [CA 3] Center 34 (4~65) winsize 62
759 23:42:24.545139 [CA 4] Center 33 (3~64) winsize 62
760 23:42:24.545194 [CA 5] Center 33 (3~64) winsize 62
761 23:42:24.545256
762 23:42:24.545312 [CmdBusTrainingLP45] Vref(ca) range 1: 32
763 23:42:24.545366
764 23:42:24.545513 [CATrainingPosCal] consider 1 rank data
765 23:42:24.545633 u2DelayCellTimex100 = 270/100 ps
766 23:42:24.545704 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
767 23:42:24.545798 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
768 23:42:24.545886 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
769 23:42:24.545973 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
770 23:42:24.546059 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
771 23:42:24.546144 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
772 23:42:24.546249
773 23:42:24.546314 CA PerBit enable=1, Macro0, CA PI delay=33
774 23:42:24.546371
775 23:42:24.546425 [CBTSetCACLKResult] CA Dly = 33
776 23:42:24.546480 CS Dly: 6 (0~37)
777 23:42:24.546534 ==
778 23:42:24.546588 Dram Type= 6, Freq= 0, CH_0, rank 1
779 23:42:24.546643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
780 23:42:24.546698 ==
781 23:42:24.546752 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
782 23:42:24.546844 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
783 23:42:24.546991 [CA 0] Center 37 (6~68) winsize 63
784 23:42:24.547091 [CA 1] Center 37 (7~68) winsize 62
785 23:42:24.547151 [CA 2] Center 34 (4~65) winsize 62
786 23:42:24.547207 [CA 3] Center 34 (4~65) winsize 62
787 23:42:24.547261 [CA 4] Center 33 (3~64) winsize 62
788 23:42:24.547315 [CA 5] Center 33 (2~64) winsize 63
789 23:42:24.547370
790 23:42:24.547424 [CmdBusTrainingLP45] Vref(ca) range 1: 32
791 23:42:24.547478
792 23:42:24.547532 [CATrainingPosCal] consider 2 rank data
793 23:42:24.547587 u2DelayCellTimex100 = 270/100 ps
794 23:42:24.547641 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
795 23:42:24.547696 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
796 23:42:24.547750 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
797 23:42:24.547804 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
798 23:42:24.547858 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
799 23:42:24.547911 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
800 23:42:24.547965
801 23:42:24.548019 CA PerBit enable=1, Macro0, CA PI delay=33
802 23:42:24.548073
803 23:42:24.548126 [CBTSetCACLKResult] CA Dly = 33
804 23:42:24.548180 CS Dly: 6 (0~38)
805 23:42:24.548234
806 23:42:24.548288 ----->DramcWriteLeveling(PI) begin...
807 23:42:24.548342 ==
808 23:42:24.548396 Dram Type= 6, Freq= 0, CH_0, rank 0
809 23:42:24.548452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 23:42:24.548506 ==
811 23:42:24.548560 Write leveling (Byte 0): 30 => 30
812 23:42:24.548614 Write leveling (Byte 1): 30 => 30
813 23:42:24.548668 DramcWriteLeveling(PI) end<-----
814 23:42:24.548722
815 23:42:24.548775 ==
816 23:42:24.548829 Dram Type= 6, Freq= 0, CH_0, rank 0
817 23:42:24.548883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
818 23:42:24.548937 ==
819 23:42:24.548991 [Gating] SW mode calibration
820 23:42:24.549045 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
821 23:42:24.549099 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
822 23:42:24.549153 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
823 23:42:24.549208 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
824 23:42:24.549262 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
825 23:42:24.549316 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
826 23:42:24.549370 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:42:24.549423 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 23:42:24.549477 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 23:42:24.549534 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 23:42:24.549588 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 23:42:24.549643 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 23:42:24.549697 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 23:42:24.549750 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 23:42:24.549804 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
835 23:42:24.549858 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 23:42:24.549911 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 23:42:24.549965 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 23:42:24.550019 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
839 23:42:24.550072 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
840 23:42:24.550126 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
841 23:42:24.550235 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
842 23:42:24.550323 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 23:42:24.550426 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
844 23:42:24.550495 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
845 23:42:24.550551 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
846 23:42:24.550607 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
847 23:42:24.550661 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
848 23:42:24.550716 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
849 23:42:24.550770 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
850 23:42:24.550825 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
851 23:42:24.551069 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
852 23:42:24.551131 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
853 23:42:24.551186 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
854 23:42:24.551240 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
855 23:42:24.551294 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
856 23:42:24.551348 0 10 8 | B1->B0 | 3333 2c2c | 0 0 | (1 1) (0 0)
857 23:42:24.551442 0 10 12 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
858 23:42:24.551497 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:42:24.551551 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:42:24.551605 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:42:24.551659 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:42:24.551713 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:42:24.551767 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
864 23:42:24.551821 0 11 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
865 23:42:24.551875 0 11 12 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
866 23:42:24.551928 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 23:42:24.551982 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 23:42:24.552036 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
869 23:42:24.552090 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 23:42:24.552143 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
871 23:42:24.552197 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 23:42:24.552250 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
873 23:42:24.552304 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
874 23:42:24.552358 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 23:42:24.552411 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 23:42:24.552465 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 23:42:24.552519 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 23:42:24.552573 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 23:42:24.552627 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 23:42:24.552681 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 23:42:24.552734 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 23:42:24.552788 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 23:42:24.552842 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 23:42:24.552896 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
885 23:42:24.552950 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
886 23:42:24.553003 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
887 23:42:24.553057 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
888 23:42:24.553110 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
889 23:42:24.553164 Total UI for P1: 0, mck2ui 16
890 23:42:24.553218 best dqsien dly found for B0: ( 0, 14, 4)
891 23:42:24.553272 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
892 23:42:24.553326 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 23:42:24.553380 Total UI for P1: 0, mck2ui 16
894 23:42:24.553434 best dqsien dly found for B1: ( 0, 14, 10)
895 23:42:24.553488 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
896 23:42:24.553541 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
897 23:42:24.553595
898 23:42:24.553649 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
899 23:42:24.553703 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
900 23:42:24.553757 [Gating] SW calibration Done
901 23:42:24.553811 ==
902 23:42:24.553865 Dram Type= 6, Freq= 0, CH_0, rank 0
903 23:42:24.553919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 23:42:24.553975 ==
905 23:42:24.554028 RX Vref Scan: 0
906 23:42:24.554082
907 23:42:24.554136 RX Vref 0 -> 0, step: 1
908 23:42:24.554237
909 23:42:24.554293 RX Delay -130 -> 252, step: 16
910 23:42:24.554348 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
911 23:42:24.554402 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
912 23:42:24.554456 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
913 23:42:24.554510 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
914 23:42:24.554564 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
915 23:42:24.554619 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
916 23:42:24.554673 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
917 23:42:24.554727 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
918 23:42:24.554781 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
919 23:42:24.554835 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
920 23:42:24.554888 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
921 23:42:24.554942 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
922 23:42:24.554996 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
923 23:42:24.555050 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
924 23:42:24.555104 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
925 23:42:24.555158 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
926 23:42:24.555211 ==
927 23:42:24.555265 Dram Type= 6, Freq= 0, CH_0, rank 0
928 23:42:24.555319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
929 23:42:24.555439 ==
930 23:42:24.555495 DQS Delay:
931 23:42:24.555550 DQS0 = 0, DQS1 = 0
932 23:42:24.555652 DQM Delay:
933 23:42:24.555707 DQM0 = 86, DQM1 = 73
934 23:42:24.555762 DQ Delay:
935 23:42:24.555815 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
936 23:42:24.555868 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
937 23:42:24.555922 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
938 23:42:24.555976 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =77
939 23:42:24.556033
940 23:42:24.556087
941 23:42:24.556141 ==
942 23:42:24.556195 Dram Type= 6, Freq= 0, CH_0, rank 0
943 23:42:24.556284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
944 23:42:24.556339 ==
945 23:42:24.556392
946 23:42:24.556445
947 23:42:24.556498 TX Vref Scan disable
948 23:42:24.556551 == TX Byte 0 ==
949 23:42:24.556633 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
950 23:42:24.556688 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
951 23:42:24.556741 == TX Byte 1 ==
952 23:42:24.556794 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
953 23:42:24.556847 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
954 23:42:24.556901 ==
955 23:42:24.556954 Dram Type= 6, Freq= 0, CH_0, rank 0
956 23:42:24.557037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
957 23:42:24.557091 ==
958 23:42:24.557336 TX Vref=22, minBit 5, minWin=27, winSum=443
959 23:42:24.557470 TX Vref=24, minBit 1, minWin=27, winSum=443
960 23:42:24.557564 TX Vref=26, minBit 5, minWin=27, winSum=447
961 23:42:24.557636 TX Vref=28, minBit 10, minWin=27, winSum=448
962 23:42:24.557692 TX Vref=30, minBit 4, minWin=27, winSum=445
963 23:42:24.557846 TX Vref=32, minBit 4, minWin=27, winSum=444
964 23:42:24.557990 [TxChooseVref] Worse bit 10, Min win 27, Win sum 448, Final Vref 28
965 23:42:24.558091
966 23:42:24.558202 Final TX Range 1 Vref 28
967 23:42:24.558277
968 23:42:24.558332 ==
969 23:42:24.558386 Dram Type= 6, Freq= 0, CH_0, rank 0
970 23:42:24.558441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
971 23:42:24.558495 ==
972 23:42:24.558549
973 23:42:24.558602
974 23:42:24.558655 TX Vref Scan disable
975 23:42:24.558709 == TX Byte 0 ==
976 23:42:24.558762 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
977 23:42:24.558816 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
978 23:42:24.558871 == TX Byte 1 ==
979 23:42:24.558924 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 23:42:24.558978 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 23:42:24.559031
982 23:42:24.559084 [DATLAT]
983 23:42:24.559137 Freq=800, CH0 RK0
984 23:42:24.559191
985 23:42:24.559244 DATLAT Default: 0xa
986 23:42:24.559297 0, 0xFFFF, sum = 0
987 23:42:24.559373 1, 0xFFFF, sum = 0
988 23:42:24.559444 2, 0xFFFF, sum = 0
989 23:42:24.559499 3, 0xFFFF, sum = 0
990 23:42:24.559554 4, 0xFFFF, sum = 0
991 23:42:24.559608 5, 0xFFFF, sum = 0
992 23:42:24.559662 6, 0xFFFF, sum = 0
993 23:42:24.559717 7, 0xFFFF, sum = 0
994 23:42:24.559772 8, 0xFFFF, sum = 0
995 23:42:24.559827 9, 0x0, sum = 1
996 23:42:24.559881 10, 0x0, sum = 2
997 23:42:24.559937 11, 0x0, sum = 3
998 23:42:24.559992 12, 0x0, sum = 4
999 23:42:24.560046 best_step = 10
1000 23:42:24.560100
1001 23:42:24.560153 ==
1002 23:42:24.560208 Dram Type= 6, Freq= 0, CH_0, rank 0
1003 23:42:24.560263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1004 23:42:24.560334 ==
1005 23:42:24.560448 RX Vref Scan: 1
1006 23:42:24.560503
1007 23:42:24.560557 Set Vref Range= 32 -> 127
1008 23:42:24.560612
1009 23:42:24.560666 RX Vref 32 -> 127, step: 1
1010 23:42:24.560720
1011 23:42:24.560774 RX Delay -111 -> 252, step: 8
1012 23:42:24.560829
1013 23:42:24.560946 Set Vref, RX VrefLevel [Byte0]: 32
1014 23:42:24.561000 [Byte1]: 32
1015 23:42:24.561054
1016 23:42:24.561108 Set Vref, RX VrefLevel [Byte0]: 33
1017 23:42:24.561163 [Byte1]: 33
1018 23:42:24.561218
1019 23:42:24.561272 Set Vref, RX VrefLevel [Byte0]: 34
1020 23:42:24.561326 [Byte1]: 34
1021 23:42:24.561424
1022 23:42:24.561569 Set Vref, RX VrefLevel [Byte0]: 35
1023 23:42:24.561695 [Byte1]: 35
1024 23:42:24.561792
1025 23:42:24.561885 Set Vref, RX VrefLevel [Byte0]: 36
1026 23:42:24.561975 [Byte1]: 36
1027 23:42:24.562061
1028 23:42:24.562146 Set Vref, RX VrefLevel [Byte0]: 37
1029 23:42:24.562248 [Byte1]: 37
1030 23:42:24.562303
1031 23:42:24.562357 Set Vref, RX VrefLevel [Byte0]: 38
1032 23:42:24.562412 [Byte1]: 38
1033 23:42:24.562466
1034 23:42:24.562519 Set Vref, RX VrefLevel [Byte0]: 39
1035 23:42:24.562572 [Byte1]: 39
1036 23:42:24.562626
1037 23:42:24.562679 Set Vref, RX VrefLevel [Byte0]: 40
1038 23:42:24.562732 [Byte1]: 40
1039 23:42:24.562786
1040 23:42:24.562840 Set Vref, RX VrefLevel [Byte0]: 41
1041 23:42:24.562893 [Byte1]: 41
1042 23:42:24.562947
1043 23:42:24.563000 Set Vref, RX VrefLevel [Byte0]: 42
1044 23:42:24.563054 [Byte1]: 42
1045 23:42:24.563107
1046 23:42:24.563160 Set Vref, RX VrefLevel [Byte0]: 43
1047 23:42:24.563213 [Byte1]: 43
1048 23:42:24.563266
1049 23:42:24.563319 Set Vref, RX VrefLevel [Byte0]: 44
1050 23:42:24.563373 [Byte1]: 44
1051 23:42:24.563425
1052 23:42:24.563478 Set Vref, RX VrefLevel [Byte0]: 45
1053 23:42:24.563532 [Byte1]: 45
1054 23:42:24.563586
1055 23:42:24.563639 Set Vref, RX VrefLevel [Byte0]: 46
1056 23:42:24.563692 [Byte1]: 46
1057 23:42:24.563746
1058 23:42:24.563799 Set Vref, RX VrefLevel [Byte0]: 47
1059 23:42:24.563852 [Byte1]: 47
1060 23:42:24.563905
1061 23:42:24.563959 Set Vref, RX VrefLevel [Byte0]: 48
1062 23:42:24.564012 [Byte1]: 48
1063 23:42:24.564065
1064 23:42:24.564118 Set Vref, RX VrefLevel [Byte0]: 49
1065 23:42:24.564171 [Byte1]: 49
1066 23:42:24.564224
1067 23:42:24.564277 Set Vref, RX VrefLevel [Byte0]: 50
1068 23:42:24.564330 [Byte1]: 50
1069 23:42:24.564383
1070 23:42:24.564436 Set Vref, RX VrefLevel [Byte0]: 51
1071 23:42:24.564490 [Byte1]: 51
1072 23:42:24.564543
1073 23:42:24.564595 Set Vref, RX VrefLevel [Byte0]: 52
1074 23:42:24.564649 [Byte1]: 52
1075 23:42:24.564702
1076 23:42:24.564755 Set Vref, RX VrefLevel [Byte0]: 53
1077 23:42:24.564808 [Byte1]: 53
1078 23:42:24.564861
1079 23:42:24.564914 Set Vref, RX VrefLevel [Byte0]: 54
1080 23:42:24.564967 [Byte1]: 54
1081 23:42:24.565020
1082 23:42:24.565073 Set Vref, RX VrefLevel [Byte0]: 55
1083 23:42:24.565126 [Byte1]: 55
1084 23:42:24.565179
1085 23:42:24.565232 Set Vref, RX VrefLevel [Byte0]: 56
1086 23:42:24.565285 [Byte1]: 56
1087 23:42:24.565338
1088 23:42:24.565428 Set Vref, RX VrefLevel [Byte0]: 57
1089 23:42:24.565529 [Byte1]: 57
1090 23:42:24.565584
1091 23:42:24.565638 Set Vref, RX VrefLevel [Byte0]: 58
1092 23:42:24.565692 [Byte1]: 58
1093 23:42:24.565746
1094 23:42:24.565800 Set Vref, RX VrefLevel [Byte0]: 59
1095 23:42:24.565855 [Byte1]: 59
1096 23:42:24.565909
1097 23:42:24.565964 Set Vref, RX VrefLevel [Byte0]: 60
1098 23:42:24.566019 [Byte1]: 60
1099 23:42:24.566074
1100 23:42:24.566127 Set Vref, RX VrefLevel [Byte0]: 61
1101 23:42:24.566200 [Byte1]: 61
1102 23:42:24.566257
1103 23:42:24.566311 Set Vref, RX VrefLevel [Byte0]: 62
1104 23:42:24.566366 [Byte1]: 62
1105 23:42:24.566421
1106 23:42:24.566475 Set Vref, RX VrefLevel [Byte0]: 63
1107 23:42:24.566530 [Byte1]: 63
1108 23:42:24.566583
1109 23:42:24.566637 Set Vref, RX VrefLevel [Byte0]: 64
1110 23:42:24.566692 [Byte1]: 64
1111 23:42:24.566747
1112 23:42:24.566801 Set Vref, RX VrefLevel [Byte0]: 65
1113 23:42:24.566856 [Byte1]: 65
1114 23:42:24.566910
1115 23:42:24.566965 Set Vref, RX VrefLevel [Byte0]: 66
1116 23:42:24.567020 [Byte1]: 66
1117 23:42:24.567075
1118 23:42:24.567129 Set Vref, RX VrefLevel [Byte0]: 67
1119 23:42:24.567184 [Byte1]: 67
1120 23:42:24.567238
1121 23:42:24.567292 Set Vref, RX VrefLevel [Byte0]: 68
1122 23:42:24.567348 [Byte1]: 68
1123 23:42:24.567402
1124 23:42:24.567456 Set Vref, RX VrefLevel [Byte0]: 69
1125 23:42:24.567703 [Byte1]: 69
1126 23:42:24.567765
1127 23:42:24.567821 Set Vref, RX VrefLevel [Byte0]: 70
1128 23:42:24.567876 [Byte1]: 70
1129 23:42:24.567935
1130 23:42:24.567994 Set Vref, RX VrefLevel [Byte0]: 71
1131 23:42:24.568108 [Byte1]: 71
1132 23:42:24.568214
1133 23:42:24.568478 Set Vref, RX VrefLevel [Byte0]: 72
1134 23:42:24.568617 [Byte1]: 72
1135 23:42:24.568738
1136 23:42:24.568825 Set Vref, RX VrefLevel [Byte0]: 73
1137 23:42:24.568915 [Byte1]: 73
1138 23:42:24.569001
1139 23:42:24.569087 Set Vref, RX VrefLevel [Byte0]: 74
1140 23:42:24.569176 [Byte1]: 74
1141 23:42:24.569261
1142 23:42:24.569354 Set Vref, RX VrefLevel [Byte0]: 75
1143 23:42:24.569445 [Byte1]: 75
1144 23:42:24.569505
1145 23:42:24.569590 Set Vref, RX VrefLevel [Byte0]: 76
1146 23:42:24.569646 [Byte1]: 76
1147 23:42:24.569701
1148 23:42:24.569755 Set Vref, RX VrefLevel [Byte0]: 77
1149 23:42:24.569810 [Byte1]: 77
1150 23:42:24.569864
1151 23:42:24.569919 Set Vref, RX VrefLevel [Byte0]: 78
1152 23:42:24.569973 [Byte1]: 78
1153 23:42:24.570028
1154 23:42:24.570088 Set Vref, RX VrefLevel [Byte0]: 79
1155 23:42:24.570181 [Byte1]: 79
1156 23:42:24.570240
1157 23:42:24.570295 Final RX Vref Byte 0 = 62 to rank0
1158 23:42:24.570351 Final RX Vref Byte 1 = 51 to rank0
1159 23:42:24.570406 Final RX Vref Byte 0 = 62 to rank1
1160 23:42:24.570461 Final RX Vref Byte 1 = 51 to rank1==
1161 23:42:24.570516 Dram Type= 6, Freq= 0, CH_0, rank 0
1162 23:42:24.570570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1163 23:42:24.570647 ==
1164 23:42:24.570754 DQS Delay:
1165 23:42:24.570822 DQS0 = 0, DQS1 = 0
1166 23:42:24.570876 DQM Delay:
1167 23:42:24.570930 DQM0 = 86, DQM1 = 76
1168 23:42:24.570983 DQ Delay:
1169 23:42:24.571082 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =80
1170 23:42:24.571166 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1171 23:42:24.571221 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1172 23:42:24.571275 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1173 23:42:24.571329
1174 23:42:24.571383
1175 23:42:24.571453 [DQSOSCAuto] RK0, (LSB)MR18= 0x4729, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
1176 23:42:24.571550 CH0 RK0: MR19=606, MR18=4729
1177 23:42:24.571612 CH0_RK0: MR19=0x606, MR18=0x4729, DQSOSC=392, MR23=63, INC=96, DEC=64
1178 23:42:24.571668
1179 23:42:24.571724 ----->DramcWriteLeveling(PI) begin...
1180 23:42:24.571780 ==
1181 23:42:24.571835 Dram Type= 6, Freq= 0, CH_0, rank 1
1182 23:42:24.571890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1183 23:42:24.571945 ==
1184 23:42:24.571999 Write leveling (Byte 0): 30 => 30
1185 23:42:24.572054 Write leveling (Byte 1): 29 => 29
1186 23:42:24.572108 DramcWriteLeveling(PI) end<-----
1187 23:42:24.572162
1188 23:42:24.572215 ==
1189 23:42:24.572270 Dram Type= 6, Freq= 0, CH_0, rank 1
1190 23:42:24.572324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1191 23:42:24.572379 ==
1192 23:42:24.572433 [Gating] SW mode calibration
1193 23:42:24.572487 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1194 23:42:24.572543 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1195 23:42:24.572597 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1196 23:42:24.572658 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1197 23:42:24.572715 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1198 23:42:24.572770 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1199 23:42:24.572824 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 23:42:24.572879 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 23:42:24.572932 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 23:42:24.572986 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 23:42:24.573041 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 23:42:24.573094 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 23:42:24.573148 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 23:42:24.573202 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 23:42:24.573256 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 23:42:24.573310 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 23:42:24.573364 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 23:42:24.573418 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 23:42:24.573472 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 23:42:24.573526 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1213 23:42:24.573580 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1214 23:42:24.573634 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1215 23:42:24.573688 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 23:42:24.573742 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 23:42:24.573796 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 23:42:24.573854 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 23:42:24.573908 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 23:42:24.573962 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 23:42:24.574016 0 9 8 | B1->B0 | 2322 2e2e | 1 0 | (0 0) (0 0)
1222 23:42:24.574070 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1223 23:42:24.574124 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 23:42:24.574207 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1225 23:42:24.574263 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1226 23:42:24.574316 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1227 23:42:24.574370 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1228 23:42:24.574440 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1229 23:42:24.574508 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (1 0) (0 0)
1230 23:42:24.574561 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:42:24.574614 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:42:24.574667 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:42:24.574720 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:42:24.574773 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:42:24.574826 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:42:24.574880 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1237 23:42:24.575129 0 11 8 | B1->B0 | 3030 3f3f | 0 1 | (0 0) (0 0)
1238 23:42:24.575219 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1239 23:42:24.575329 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 23:42:24.575437 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 23:42:24.575556 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1242 23:42:24.575663 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1243 23:42:24.575723 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1244 23:42:24.575778 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1245 23:42:24.575831 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1246 23:42:24.575885 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 23:42:24.575938 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 23:42:24.575992 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 23:42:24.576045 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 23:42:24.576098 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 23:42:24.576152 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 23:42:24.576205 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 23:42:24.576258 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 23:42:24.576311 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 23:42:24.576364 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 23:42:24.576417 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 23:42:24.576470 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 23:42:24.576523 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 23:42:24.576576 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 23:42:24.576630 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 23:42:24.576683 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1262 23:42:24.576736 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1263 23:42:24.576789 Total UI for P1: 0, mck2ui 16
1264 23:42:24.576843 best dqsien dly found for B0: ( 0, 14, 8)
1265 23:42:24.576896 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 23:42:24.576950 Total UI for P1: 0, mck2ui 16
1267 23:42:24.577003 best dqsien dly found for B1: ( 0, 14, 10)
1268 23:42:24.577057 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1269 23:42:24.577110 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1270 23:42:24.577163
1271 23:42:24.577217 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1272 23:42:24.577271 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1273 23:42:24.577324 [Gating] SW calibration Done
1274 23:42:24.577377 ==
1275 23:42:24.577430 Dram Type= 6, Freq= 0, CH_0, rank 1
1276 23:42:24.577483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1277 23:42:24.577537 ==
1278 23:42:24.577591 RX Vref Scan: 0
1279 23:42:24.577643
1280 23:42:24.577696 RX Vref 0 -> 0, step: 1
1281 23:42:24.577749
1282 23:42:24.577802 RX Delay -130 -> 252, step: 16
1283 23:42:24.577856 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1284 23:42:24.577910 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1285 23:42:24.577963 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1286 23:42:24.578016 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1287 23:42:24.578069 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1288 23:42:24.578122 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1289 23:42:24.578203 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1290 23:42:24.578271 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1291 23:42:24.578324 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1292 23:42:24.578378 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1293 23:42:24.578431 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1294 23:42:24.578484 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1295 23:42:24.578536 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1296 23:42:24.578590 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1297 23:42:24.578643 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1298 23:42:24.578695 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1299 23:42:24.578748 ==
1300 23:42:24.578801 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 23:42:24.578855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 23:42:24.578909 ==
1303 23:42:24.578961 DQS Delay:
1304 23:42:24.579014 DQS0 = 0, DQS1 = 0
1305 23:42:24.579126 DQM Delay:
1306 23:42:24.579274 DQM0 = 84, DQM1 = 76
1307 23:42:24.579364 DQ Delay:
1308 23:42:24.579422 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1309 23:42:24.579478 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1310 23:42:24.579533 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1311 23:42:24.579588 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1312 23:42:24.579642
1313 23:42:24.579695
1314 23:42:24.579748 ==
1315 23:42:24.579802 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 23:42:24.579856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 23:42:24.579909 ==
1318 23:42:24.579962
1319 23:42:24.580015
1320 23:42:24.580068 TX Vref Scan disable
1321 23:42:24.580122 == TX Byte 0 ==
1322 23:42:24.580175 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1323 23:42:24.580229 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1324 23:42:24.580283 == TX Byte 1 ==
1325 23:42:24.580336 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1326 23:42:24.580390 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1327 23:42:24.580443 ==
1328 23:42:24.580495 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 23:42:24.580549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 23:42:24.580602 ==
1331 23:42:24.580655 TX Vref=22, minBit 8, minWin=26, winSum=446
1332 23:42:24.580709 TX Vref=24, minBit 5, minWin=27, winSum=448
1333 23:42:24.580762 TX Vref=26, minBit 9, minWin=27, winSum=448
1334 23:42:24.580816 TX Vref=28, minBit 0, minWin=28, winSum=449
1335 23:42:24.580869 TX Vref=30, minBit 9, minWin=27, winSum=447
1336 23:42:24.580922 TX Vref=32, minBit 8, minWin=27, winSum=446
1337 23:42:24.580975 [TxChooseVref] Worse bit 0, Min win 28, Win sum 449, Final Vref 28
1338 23:42:24.581029
1339 23:42:24.581081 Final TX Range 1 Vref 28
1340 23:42:24.581134
1341 23:42:24.581187 ==
1342 23:42:24.581239 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 23:42:24.581292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 23:42:24.581345 ==
1345 23:42:24.581397
1346 23:42:24.581492
1347 23:42:24.581545 TX Vref Scan disable
1348 23:42:24.581598 == TX Byte 0 ==
1349 23:42:24.581723 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1350 23:42:24.581807 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1351 23:42:24.581898 == TX Byte 1 ==
1352 23:42:24.581984 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1353 23:42:24.582262 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1354 23:42:24.582364
1355 23:42:24.582420 [DATLAT]
1356 23:42:24.582474 Freq=800, CH0 RK1
1357 23:42:24.582528
1358 23:42:24.582581 DATLAT Default: 0xa
1359 23:42:24.582635 0, 0xFFFF, sum = 0
1360 23:42:24.582696 1, 0xFFFF, sum = 0
1361 23:42:24.582751 2, 0xFFFF, sum = 0
1362 23:42:24.582805 3, 0xFFFF, sum = 0
1363 23:42:24.582859 4, 0xFFFF, sum = 0
1364 23:42:24.582913 5, 0xFFFF, sum = 0
1365 23:42:24.582966 6, 0xFFFF, sum = 0
1366 23:42:24.583019 7, 0xFFFF, sum = 0
1367 23:42:24.583072 8, 0xFFFF, sum = 0
1368 23:42:24.583126 9, 0x0, sum = 1
1369 23:42:24.583179 10, 0x0, sum = 2
1370 23:42:24.583232 11, 0x0, sum = 3
1371 23:42:24.583285 12, 0x0, sum = 4
1372 23:42:24.583339 best_step = 10
1373 23:42:24.583391
1374 23:42:24.583445 ==
1375 23:42:24.583498 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 23:42:24.583552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 23:42:24.583605 ==
1378 23:42:24.583658 RX Vref Scan: 0
1379 23:42:24.583710
1380 23:42:24.583762 RX Vref 0 -> 0, step: 1
1381 23:42:24.583815
1382 23:42:24.583868 RX Delay -111 -> 252, step: 8
1383 23:42:24.583920 iDelay=209, Bit 0, Center 80 (-31 ~ 192) 224
1384 23:42:24.583973 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1385 23:42:24.584026 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1386 23:42:24.584079 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1387 23:42:24.584132 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1388 23:42:24.584184 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1389 23:42:24.584237 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1390 23:42:24.584297 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1391 23:42:24.584350 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1392 23:42:24.584403 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1393 23:42:24.584459 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1394 23:42:24.584514 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1395 23:42:24.584567 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1396 23:42:24.584619 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1397 23:42:24.584672 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1398 23:42:24.584724 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1399 23:42:24.584777 ==
1400 23:42:24.584830 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 23:42:24.584882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 23:42:24.584935 ==
1403 23:42:24.584987 DQS Delay:
1404 23:42:24.585040 DQS0 = 0, DQS1 = 0
1405 23:42:24.585092 DQM Delay:
1406 23:42:24.585144 DQM0 = 85, DQM1 = 76
1407 23:42:24.585196 DQ Delay:
1408 23:42:24.585248 DQ0 =80, DQ1 =92, DQ2 =80, DQ3 =80
1409 23:42:24.585301 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1410 23:42:24.585353 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
1411 23:42:24.585404 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1412 23:42:24.585457
1413 23:42:24.585509
1414 23:42:24.585562 [DQSOSCAuto] RK1, (LSB)MR18= 0x4208, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1415 23:42:24.585616 CH0 RK1: MR19=606, MR18=4208
1416 23:42:24.585669 CH0_RK1: MR19=0x606, MR18=0x4208, DQSOSC=393, MR23=63, INC=95, DEC=63
1417 23:42:24.585758 [RxdqsGatingPostProcess] freq 800
1418 23:42:24.585851 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1419 23:42:24.585936 Pre-setting of DQS Precalculation
1420 23:42:24.586047 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1421 23:42:24.586132 ==
1422 23:42:24.586226 Dram Type= 6, Freq= 0, CH_1, rank 0
1423 23:42:24.586282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 23:42:24.586336 ==
1425 23:42:24.586390 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1426 23:42:24.586444 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1427 23:42:24.586498 [CA 0] Center 36 (6~67) winsize 62
1428 23:42:24.586551 [CA 1] Center 36 (6~67) winsize 62
1429 23:42:24.586603 [CA 2] Center 34 (4~65) winsize 62
1430 23:42:24.586657 [CA 3] Center 34 (3~65) winsize 63
1431 23:42:24.586709 [CA 4] Center 34 (4~65) winsize 62
1432 23:42:24.586763 [CA 5] Center 34 (3~65) winsize 63
1433 23:42:24.586815
1434 23:42:24.586868 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1435 23:42:24.586920
1436 23:42:24.586973 [CATrainingPosCal] consider 1 rank data
1437 23:42:24.587025 u2DelayCellTimex100 = 270/100 ps
1438 23:42:24.587078 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1439 23:42:24.587130 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1440 23:42:24.587183 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1441 23:42:24.587235 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1442 23:42:24.587288 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1443 23:42:24.587340 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1444 23:42:24.587392
1445 23:42:24.587444 CA PerBit enable=1, Macro0, CA PI delay=34
1446 23:42:24.587497
1447 23:42:24.587549 [CBTSetCACLKResult] CA Dly = 34
1448 23:42:24.587601 CS Dly: 5 (0~36)
1449 23:42:24.587653 ==
1450 23:42:24.587706 Dram Type= 6, Freq= 0, CH_1, rank 1
1451 23:42:24.587758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1452 23:42:24.587812 ==
1453 23:42:24.587865 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1454 23:42:24.587918 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1455 23:42:24.587971 [CA 0] Center 36 (6~67) winsize 62
1456 23:42:24.588024 [CA 1] Center 37 (7~67) winsize 61
1457 23:42:24.588076 [CA 2] Center 34 (4~65) winsize 62
1458 23:42:24.588128 [CA 3] Center 34 (3~65) winsize 63
1459 23:42:24.588180 [CA 4] Center 34 (4~65) winsize 62
1460 23:42:24.588232 [CA 5] Center 34 (3~65) winsize 63
1461 23:42:24.588285
1462 23:42:24.588337 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1463 23:42:24.588389
1464 23:42:24.588442 [CATrainingPosCal] consider 2 rank data
1465 23:42:24.588494 u2DelayCellTimex100 = 270/100 ps
1466 23:42:24.588547 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1467 23:42:24.588600 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1468 23:42:24.588654 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1469 23:42:24.588706 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1470 23:42:24.588759 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1471 23:42:24.588812 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1472 23:42:24.588865
1473 23:42:24.588916 CA PerBit enable=1, Macro0, CA PI delay=34
1474 23:42:24.588969
1475 23:42:24.589021 [CBTSetCACLKResult] CA Dly = 34
1476 23:42:24.589081 CS Dly: 6 (0~38)
1477 23:42:24.589134
1478 23:42:24.589186 ----->DramcWriteLeveling(PI) begin...
1479 23:42:24.589241 ==
1480 23:42:24.589294 Dram Type= 6, Freq= 0, CH_1, rank 0
1481 23:42:24.589347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1482 23:42:24.589400 ==
1483 23:42:24.589453 Write leveling (Byte 0): 25 => 25
1484 23:42:24.589506 Write leveling (Byte 1): 28 => 28
1485 23:42:24.589559 DramcWriteLeveling(PI) end<-----
1486 23:42:24.589611
1487 23:42:24.589663 ==
1488 23:42:24.589716 Dram Type= 6, Freq= 0, CH_1, rank 0
1489 23:42:24.589967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1490 23:42:24.590080 ==
1491 23:42:24.590227 [Gating] SW mode calibration
1492 23:42:24.590338 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1493 23:42:24.590448 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1494 23:42:24.590558 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1495 23:42:24.590667 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1496 23:42:24.590775 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1497 23:42:24.590876 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 23:42:24.590969 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 23:42:24.591036 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 23:42:24.591090 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 23:42:24.591144 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 23:42:24.591197 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 23:42:24.591251 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 23:42:24.591304 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 23:42:24.591357 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 23:42:24.591409 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 23:42:24.591462 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 23:42:24.591514 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 23:42:24.591567 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 23:42:24.591620 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 23:42:24.591673 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1512 23:42:24.591726 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 23:42:24.591779 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 23:42:24.591831 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 23:42:24.591884 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 23:42:24.591941 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 23:42:24.591995 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 23:42:24.592048 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:42:24.592108 0 9 4 | B1->B0 | 2323 2323 | 1 1 | (1 1) (1 1)
1520 23:42:24.592165 0 9 8 | B1->B0 | 2c2c 3030 | 1 0 | (0 0) (0 0)
1521 23:42:24.592218 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 23:42:24.592271 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1523 23:42:24.592324 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1524 23:42:24.592376 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1525 23:42:24.592435 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1526 23:42:24.592489 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1527 23:42:24.592542 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1528 23:42:24.592595 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:42:24.592647 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:42:24.592699 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:42:24.592752 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:42:24.592804 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:42:24.592857 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:42:24.592910 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:42:24.592963 0 11 4 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
1536 23:42:24.593016 0 11 8 | B1->B0 | 3d3d 4343 | 0 0 | (0 0) (0 0)
1537 23:42:24.593069 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 23:42:24.593121 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 23:42:24.593174 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1540 23:42:24.593226 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1541 23:42:24.593278 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 23:42:24.593331 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 23:42:24.593384 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1544 23:42:24.593436 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1545 23:42:24.593489 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 23:42:24.593541 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 23:42:24.593594 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 23:42:24.593647 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 23:42:24.593699 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 23:42:24.593752 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 23:42:24.593805 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 23:42:24.593857 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 23:42:24.593910 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 23:42:24.593962 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 23:42:24.594015 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 23:42:24.594068 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 23:42:24.594121 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 23:42:24.594202 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 23:42:24.594271 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1560 23:42:24.594324 Total UI for P1: 0, mck2ui 16
1561 23:42:24.594378 best dqsien dly found for B0: ( 0, 14, 2)
1562 23:42:24.594431 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1563 23:42:24.594484 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 23:42:24.594537 Total UI for P1: 0, mck2ui 16
1565 23:42:24.594590 best dqsien dly found for B1: ( 0, 14, 6)
1566 23:42:24.594643 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1567 23:42:24.594696 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1568 23:42:24.594748
1569 23:42:24.594800 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1570 23:42:24.594853 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1571 23:42:24.594906 [Gating] SW calibration Done
1572 23:42:24.594958 ==
1573 23:42:24.595011 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 23:42:24.595258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 23:42:24.595368 ==
1576 23:42:24.595476 RX Vref Scan: 0
1577 23:42:24.595583
1578 23:42:24.595690 RX Vref 0 -> 0, step: 1
1579 23:42:24.595794
1580 23:42:24.595883 RX Delay -130 -> 252, step: 16
1581 23:42:24.595968 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1582 23:42:24.596056 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1583 23:42:24.596140 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1584 23:42:24.596224 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1585 23:42:24.596307 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1586 23:42:24.596391 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1587 23:42:24.596474 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1588 23:42:24.596557 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1589 23:42:24.596640 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1590 23:42:24.596724 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1591 23:42:24.596807 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1592 23:42:24.596890 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1593 23:42:24.596973 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1594 23:42:24.597056 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1595 23:42:24.597139 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1596 23:42:24.597223 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1597 23:42:24.597305 ==
1598 23:42:24.597388 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 23:42:24.597475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 23:42:24.597559 ==
1601 23:42:24.597642 DQS Delay:
1602 23:42:24.597748 DQS0 = 0, DQS1 = 0
1603 23:42:24.597846 DQM Delay:
1604 23:42:24.597928 DQM0 = 89, DQM1 = 78
1605 23:42:24.598011 DQ Delay:
1606 23:42:24.598093 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1607 23:42:24.598199 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1608 23:42:24.598271 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1609 23:42:24.598325 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1610 23:42:24.598378
1611 23:42:24.598431
1612 23:42:24.598483 ==
1613 23:42:24.598535 Dram Type= 6, Freq= 0, CH_1, rank 0
1614 23:42:24.598588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1615 23:42:24.598642 ==
1616 23:42:24.598694
1617 23:42:24.598746
1618 23:42:24.598798 TX Vref Scan disable
1619 23:42:24.598851 == TX Byte 0 ==
1620 23:42:24.598903 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1621 23:42:24.598956 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1622 23:42:24.599009 == TX Byte 1 ==
1623 23:42:24.599061 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1624 23:42:24.599115 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1625 23:42:24.599167 ==
1626 23:42:24.599219 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 23:42:24.599272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 23:42:24.599325 ==
1629 23:42:24.599378 TX Vref=22, minBit 0, minWin=27, winSum=440
1630 23:42:24.599431 TX Vref=24, minBit 8, minWin=27, winSum=448
1631 23:42:24.599484 TX Vref=26, minBit 9, minWin=27, winSum=446
1632 23:42:24.599537 TX Vref=28, minBit 15, minWin=27, winSum=452
1633 23:42:24.599590 TX Vref=30, minBit 8, minWin=27, winSum=446
1634 23:42:24.599643 TX Vref=32, minBit 0, minWin=27, winSum=443
1635 23:42:24.599696 [TxChooseVref] Worse bit 15, Min win 27, Win sum 452, Final Vref 28
1636 23:42:24.599749
1637 23:42:24.599802 Final TX Range 1 Vref 28
1638 23:42:24.599855
1639 23:42:24.599906 ==
1640 23:42:24.599958 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 23:42:24.600011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 23:42:24.600063 ==
1643 23:42:24.600116
1644 23:42:24.600167
1645 23:42:24.600219 TX Vref Scan disable
1646 23:42:24.600272 == TX Byte 0 ==
1647 23:42:24.600324 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1648 23:42:24.600377 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1649 23:42:24.600429 == TX Byte 1 ==
1650 23:42:24.600481 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1651 23:42:24.600534 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1652 23:42:24.600587
1653 23:42:24.600639 [DATLAT]
1654 23:42:24.600691 Freq=800, CH1 RK0
1655 23:42:24.600743
1656 23:42:24.600796 DATLAT Default: 0xa
1657 23:42:24.600848 0, 0xFFFF, sum = 0
1658 23:42:24.600901 1, 0xFFFF, sum = 0
1659 23:42:24.600955 2, 0xFFFF, sum = 0
1660 23:42:24.601009 3, 0xFFFF, sum = 0
1661 23:42:24.601062 4, 0xFFFF, sum = 0
1662 23:42:24.601115 5, 0xFFFF, sum = 0
1663 23:42:24.601168 6, 0xFFFF, sum = 0
1664 23:42:24.601221 7, 0xFFFF, sum = 0
1665 23:42:24.601275 8, 0xFFFF, sum = 0
1666 23:42:24.601327 9, 0x0, sum = 1
1667 23:42:24.601381 10, 0x0, sum = 2
1668 23:42:24.601434 11, 0x0, sum = 3
1669 23:42:24.601488 12, 0x0, sum = 4
1670 23:42:24.601541 best_step = 10
1671 23:42:24.601593
1672 23:42:24.601644 ==
1673 23:42:24.601697 Dram Type= 6, Freq= 0, CH_1, rank 0
1674 23:42:24.601777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1675 23:42:24.601844 ==
1676 23:42:24.601896 RX Vref Scan: 1
1677 23:42:24.601948
1678 23:42:24.602000 Set Vref Range= 32 -> 127
1679 23:42:24.602052
1680 23:42:24.602105 RX Vref 32 -> 127, step: 1
1681 23:42:24.602157
1682 23:42:24.602251 RX Delay -95 -> 252, step: 8
1683 23:42:24.602304
1684 23:42:24.602357 Set Vref, RX VrefLevel [Byte0]: 32
1685 23:42:24.602410 [Byte1]: 32
1686 23:42:24.602463
1687 23:42:24.602515 Set Vref, RX VrefLevel [Byte0]: 33
1688 23:42:24.602568 [Byte1]: 33
1689 23:42:24.602654
1690 23:42:24.602707 Set Vref, RX VrefLevel [Byte0]: 34
1691 23:42:24.602760 [Byte1]: 34
1692 23:42:24.602813
1693 23:42:24.602865 Set Vref, RX VrefLevel [Byte0]: 35
1694 23:42:24.602917 [Byte1]: 35
1695 23:42:24.602969
1696 23:42:24.603021 Set Vref, RX VrefLevel [Byte0]: 36
1697 23:42:24.603073 [Byte1]: 36
1698 23:42:24.603125
1699 23:42:24.603177 Set Vref, RX VrefLevel [Byte0]: 37
1700 23:42:24.603229 [Byte1]: 37
1701 23:42:24.603282
1702 23:42:24.603333 Set Vref, RX VrefLevel [Byte0]: 38
1703 23:42:24.603386 [Byte1]: 38
1704 23:42:24.603437
1705 23:42:24.603489 Set Vref, RX VrefLevel [Byte0]: 39
1706 23:42:24.603541 [Byte1]: 39
1707 23:42:24.603593
1708 23:42:24.603645 Set Vref, RX VrefLevel [Byte0]: 40
1709 23:42:24.603697 [Byte1]: 40
1710 23:42:24.603748
1711 23:42:24.603801 Set Vref, RX VrefLevel [Byte0]: 41
1712 23:42:24.603853 [Byte1]: 41
1713 23:42:24.603928
1714 23:42:24.603994 Set Vref, RX VrefLevel [Byte0]: 42
1715 23:42:24.604046 [Byte1]: 42
1716 23:42:24.604099
1717 23:42:24.604151 Set Vref, RX VrefLevel [Byte0]: 43
1718 23:42:24.604203 [Byte1]: 43
1719 23:42:24.604254
1720 23:42:24.604306 Set Vref, RX VrefLevel [Byte0]: 44
1721 23:42:24.604358 [Byte1]: 44
1722 23:42:24.604411
1723 23:42:24.604463 Set Vref, RX VrefLevel [Byte0]: 45
1724 23:42:24.604516 [Byte1]: 45
1725 23:42:24.604569
1726 23:42:24.604622 Set Vref, RX VrefLevel [Byte0]: 46
1727 23:42:24.604674 [Byte1]: 46
1728 23:42:24.604726
1729 23:42:24.604778 Set Vref, RX VrefLevel [Byte0]: 47
1730 23:42:24.604831 [Byte1]: 47
1731 23:42:24.604883
1732 23:42:24.605131 Set Vref, RX VrefLevel [Byte0]: 48
1733 23:42:24.605247 [Byte1]: 48
1734 23:42:24.605355
1735 23:42:24.605461 Set Vref, RX VrefLevel [Byte0]: 49
1736 23:42:24.605569 [Byte1]: 49
1737 23:42:24.605667
1738 23:42:24.605759 Set Vref, RX VrefLevel [Byte0]: 50
1739 23:42:24.605837 [Byte1]: 50
1740 23:42:24.605893
1741 23:42:24.605947 Set Vref, RX VrefLevel [Byte0]: 51
1742 23:42:24.606001 [Byte1]: 51
1743 23:42:24.606054
1744 23:42:24.606107 Set Vref, RX VrefLevel [Byte0]: 52
1745 23:42:24.606188 [Byte1]: 52
1746 23:42:24.606261
1747 23:42:24.606314 Set Vref, RX VrefLevel [Byte0]: 53
1748 23:42:24.606367 [Byte1]: 53
1749 23:42:24.606420
1750 23:42:24.606472 Set Vref, RX VrefLevel [Byte0]: 54
1751 23:42:24.606525 [Byte1]: 54
1752 23:42:24.606578
1753 23:42:24.606631 Set Vref, RX VrefLevel [Byte0]: 55
1754 23:42:24.606684 [Byte1]: 55
1755 23:42:24.606735
1756 23:42:24.606788 Set Vref, RX VrefLevel [Byte0]: 56
1757 23:42:24.606841 [Byte1]: 56
1758 23:42:24.606893
1759 23:42:24.606945 Set Vref, RX VrefLevel [Byte0]: 57
1760 23:42:24.606997 [Byte1]: 57
1761 23:42:24.607050
1762 23:42:24.607102 Set Vref, RX VrefLevel [Byte0]: 58
1763 23:42:24.607155 [Byte1]: 58
1764 23:42:24.607207
1765 23:42:24.607259 Set Vref, RX VrefLevel [Byte0]: 59
1766 23:42:24.607318 [Byte1]: 59
1767 23:42:24.607372
1768 23:42:24.607425 Set Vref, RX VrefLevel [Byte0]: 60
1769 23:42:24.607485 [Byte1]: 60
1770 23:42:24.607538
1771 23:42:24.607591 Set Vref, RX VrefLevel [Byte0]: 61
1772 23:42:24.607643 [Byte1]: 61
1773 23:42:24.607696
1774 23:42:24.607749 Set Vref, RX VrefLevel [Byte0]: 62
1775 23:42:24.607801 [Byte1]: 62
1776 23:42:24.607853
1777 23:42:24.607906 Set Vref, RX VrefLevel [Byte0]: 63
1778 23:42:24.607990 [Byte1]: 63
1779 23:42:24.608043
1780 23:42:24.608095 Set Vref, RX VrefLevel [Byte0]: 64
1781 23:42:24.608148 [Byte1]: 64
1782 23:42:24.608200
1783 23:42:24.608253 Set Vref, RX VrefLevel [Byte0]: 65
1784 23:42:24.608305 [Byte1]: 65
1785 23:42:24.608357
1786 23:42:24.608409 Set Vref, RX VrefLevel [Byte0]: 66
1787 23:42:24.608462 [Byte1]: 66
1788 23:42:24.608514
1789 23:42:24.608566 Set Vref, RX VrefLevel [Byte0]: 67
1790 23:42:24.608618 [Byte1]: 67
1791 23:42:24.608671
1792 23:42:24.608723 Set Vref, RX VrefLevel [Byte0]: 68
1793 23:42:24.608775 [Byte1]: 68
1794 23:42:24.608828
1795 23:42:24.608881 Set Vref, RX VrefLevel [Byte0]: 69
1796 23:42:24.608933 [Byte1]: 69
1797 23:42:24.608986
1798 23:42:24.609038 Set Vref, RX VrefLevel [Byte0]: 70
1799 23:42:24.609091 [Byte1]: 70
1800 23:42:24.609144
1801 23:42:24.609196 Set Vref, RX VrefLevel [Byte0]: 71
1802 23:42:24.609249 [Byte1]: 71
1803 23:42:24.609301
1804 23:42:24.609353 Set Vref, RX VrefLevel [Byte0]: 72
1805 23:42:24.609406 [Byte1]: 72
1806 23:42:24.609458
1807 23:42:24.609511 Set Vref, RX VrefLevel [Byte0]: 73
1808 23:42:24.609564 [Byte1]: 73
1809 23:42:24.609617
1810 23:42:24.609670 Set Vref, RX VrefLevel [Byte0]: 74
1811 23:42:24.609723 [Byte1]: 74
1812 23:42:24.609775
1813 23:42:24.609827 Set Vref, RX VrefLevel [Byte0]: 75
1814 23:42:24.609879 [Byte1]: 75
1815 23:42:24.609931
1816 23:42:24.609983 Set Vref, RX VrefLevel [Byte0]: 76
1817 23:42:24.610035 [Byte1]: 76
1818 23:42:24.610088
1819 23:42:24.610140 Set Vref, RX VrefLevel [Byte0]: 77
1820 23:42:24.610240 [Byte1]: 77
1821 23:42:24.610294
1822 23:42:24.610346 Final RX Vref Byte 0 = 57 to rank0
1823 23:42:24.610399 Final RX Vref Byte 1 = 64 to rank0
1824 23:42:24.610452 Final RX Vref Byte 0 = 57 to rank1
1825 23:42:24.610504 Final RX Vref Byte 1 = 64 to rank1==
1826 23:42:24.610557 Dram Type= 6, Freq= 0, CH_1, rank 0
1827 23:42:24.610610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1828 23:42:24.610662 ==
1829 23:42:24.610715 DQS Delay:
1830 23:42:24.610767 DQS0 = 0, DQS1 = 0
1831 23:42:24.610819 DQM Delay:
1832 23:42:24.610872 DQM0 = 86, DQM1 = 80
1833 23:42:24.610924 DQ Delay:
1834 23:42:24.610976 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1835 23:42:24.611029 DQ4 =80, DQ5 =100, DQ6 =96, DQ7 =80
1836 23:42:24.611081 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1837 23:42:24.611133 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =92
1838 23:42:24.611186
1839 23:42:24.611238
1840 23:42:24.611290 [DQSOSCAuto] RK0, (LSB)MR18= 0x311d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1841 23:42:24.611344 CH1 RK0: MR19=606, MR18=311D
1842 23:42:24.611396 CH1_RK0: MR19=0x606, MR18=0x311D, DQSOSC=397, MR23=63, INC=93, DEC=62
1843 23:42:24.611449
1844 23:42:24.611501 ----->DramcWriteLeveling(PI) begin...
1845 23:42:24.611555 ==
1846 23:42:24.611607 Dram Type= 6, Freq= 0, CH_1, rank 1
1847 23:42:24.611660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 23:42:24.611713 ==
1849 23:42:24.611765 Write leveling (Byte 0): 27 => 27
1850 23:42:24.611818 Write leveling (Byte 1): 28 => 28
1851 23:42:24.611870 DramcWriteLeveling(PI) end<-----
1852 23:42:24.611922
1853 23:42:24.611974 ==
1854 23:42:24.612027 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 23:42:24.612079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 23:42:24.612132 ==
1857 23:42:24.612185 [Gating] SW mode calibration
1858 23:42:24.612237 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1859 23:42:24.612291 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1860 23:42:24.612343 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1861 23:42:24.612396 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1862 23:42:24.612448 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 23:42:24.612501 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 23:42:24.612554 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:42:24.612606 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 23:42:24.612659 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:42:24.612711 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:42:24.612764 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:42:24.612816 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:42:24.612868 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:42:24.612920 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:42:24.613165 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:42:24.613226 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:42:24.613280 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:42:24.613333 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:42:24.613434 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1877 23:42:24.613560 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1878 23:42:24.613682 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1879 23:42:24.613776 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:42:24.613864 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:42:24.613919 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:42:24.613972 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:42:24.614025 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:42:24.614078 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:42:24.614132 0 9 4 | B1->B0 | 2323 2323 | 1 1 | (1 1) (1 1)
1886 23:42:24.614212 0 9 8 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1887 23:42:24.614282 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 23:42:24.614335 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 23:42:24.614388 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 23:42:24.614440 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 23:42:24.614493 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 23:42:24.614545 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 23:42:24.614598 0 10 4 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 0)
1894 23:42:24.614650 0 10 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1895 23:42:24.614703 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:42:24.614756 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:42:24.614808 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:42:24.614861 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 23:42:24.614913 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 23:42:24.614966 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 23:42:24.615018 0 11 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1902 23:42:24.615070 0 11 8 | B1->B0 | 4141 3a3a | 0 0 | (0 0) (1 1)
1903 23:42:24.615123 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 23:42:24.615176 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 23:42:24.615229 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 23:42:24.615281 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 23:42:24.615339 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 23:42:24.615392 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 23:42:24.615444 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1910 23:42:24.615497 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 23:42:24.615550 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 23:42:24.615602 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 23:42:24.615654 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 23:42:24.615707 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 23:42:24.615760 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 23:42:24.615812 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 23:42:24.615864 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:42:24.615918 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:42:24.615970 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:42:24.616023 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:42:24.616075 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:42:24.616127 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:42:24.616180 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:42:24.616232 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:42:24.616284 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1926 23:42:24.616337 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1927 23:42:24.616389 Total UI for P1: 0, mck2ui 16
1928 23:42:24.616443 best dqsien dly found for B1: ( 0, 14, 4)
1929 23:42:24.616495 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 23:42:24.616548 Total UI for P1: 0, mck2ui 16
1931 23:42:24.616601 best dqsien dly found for B0: ( 0, 14, 6)
1932 23:42:24.616653 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1933 23:42:24.616706 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1934 23:42:24.616758
1935 23:42:24.616811 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1936 23:42:24.616864 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1937 23:42:24.616915 [Gating] SW calibration Done
1938 23:42:24.616967 ==
1939 23:42:24.617019 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 23:42:24.617072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 23:42:24.617125 ==
1942 23:42:24.617177 RX Vref Scan: 0
1943 23:42:24.617229
1944 23:42:24.617282 RX Vref 0 -> 0, step: 1
1945 23:42:24.617334
1946 23:42:24.617386 RX Delay -130 -> 252, step: 16
1947 23:42:24.617439 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1948 23:42:24.617491 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1949 23:42:24.617544 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1950 23:42:24.617596 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1951 23:42:24.617648 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1952 23:42:24.617700 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1953 23:42:24.617776 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1954 23:42:24.617844 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1955 23:42:24.911672 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1956 23:42:24.912136 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1957 23:42:24.912561 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1958 23:42:24.912860 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1959 23:42:24.913317 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1960 23:42:24.913734 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1961 23:42:24.914141 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1962 23:42:24.914537 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1963 23:42:24.914866 ==
1964 23:42:24.915678 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 23:42:24.916220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 23:42:24.916733 ==
1967 23:42:24.917227 DQS Delay:
1968 23:42:24.917619 DQS0 = 0, DQS1 = 0
1969 23:42:24.918134 DQM Delay:
1970 23:42:24.918565 DQM0 = 87, DQM1 = 79
1971 23:42:24.919063 DQ Delay:
1972 23:42:24.919552 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1973 23:42:24.920083 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1974 23:42:24.920601 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1975 23:42:24.921051 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1976 23:42:24.921475
1977 23:42:24.921755
1978 23:42:24.922019 ==
1979 23:42:24.922458 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 23:42:24.922890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 23:42:24.923177 ==
1982 23:42:24.923442
1983 23:42:24.923699
1984 23:42:24.923951 TX Vref Scan disable
1985 23:42:24.924208 == TX Byte 0 ==
1986 23:42:24.924464 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1987 23:42:24.924723 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1988 23:42:24.924975 == TX Byte 1 ==
1989 23:42:24.925230 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1990 23:42:24.925484 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1991 23:42:24.925738 ==
1992 23:42:24.925989 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 23:42:24.926275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 23:42:24.926535 ==
1995 23:42:24.926788 TX Vref=22, minBit 1, minWin=27, winSum=448
1996 23:42:24.927045 TX Vref=24, minBit 1, minWin=27, winSum=447
1997 23:42:24.927300 TX Vref=26, minBit 9, minWin=26, winSum=452
1998 23:42:24.927557 TX Vref=28, minBit 8, minWin=27, winSum=449
1999 23:42:24.927813 TX Vref=30, minBit 9, minWin=27, winSum=449
2000 23:42:24.928065 TX Vref=32, minBit 8, minWin=27, winSum=451
2001 23:42:24.928323 [TxChooseVref] Worse bit 8, Min win 27, Win sum 451, Final Vref 32
2002 23:42:24.928581
2003 23:42:24.928836 Final TX Range 1 Vref 32
2004 23:42:24.929087
2005 23:42:24.929337 ==
2006 23:42:24.929591 Dram Type= 6, Freq= 0, CH_1, rank 1
2007 23:42:24.929847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2008 23:42:24.930099 ==
2009 23:42:24.930416
2010 23:42:24.930769
2011 23:42:24.931125 TX Vref Scan disable
2012 23:42:24.931392 == TX Byte 0 ==
2013 23:42:24.931649 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2014 23:42:24.931905 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2015 23:42:24.932159 == TX Byte 1 ==
2016 23:42:24.932411 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2017 23:42:24.932725 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2018 23:42:24.932984
2019 23:42:24.933237 [DATLAT]
2020 23:42:24.933492 Freq=800, CH1 RK1
2021 23:42:24.933914
2022 23:42:24.934356 DATLAT Default: 0xa
2023 23:42:24.934629 0, 0xFFFF, sum = 0
2024 23:42:24.934895 1, 0xFFFF, sum = 0
2025 23:42:24.935155 2, 0xFFFF, sum = 0
2026 23:42:24.935410 3, 0xFFFF, sum = 0
2027 23:42:24.935668 4, 0xFFFF, sum = 0
2028 23:42:24.935926 5, 0xFFFF, sum = 0
2029 23:42:24.936182 6, 0xFFFF, sum = 0
2030 23:42:24.936437 7, 0xFFFF, sum = 0
2031 23:42:24.936718 8, 0xFFFF, sum = 0
2032 23:42:24.937012 9, 0x0, sum = 1
2033 23:42:24.937356 10, 0x0, sum = 2
2034 23:42:24.937675 11, 0x0, sum = 3
2035 23:42:24.937939 12, 0x0, sum = 4
2036 23:42:24.938123 best_step = 10
2037 23:42:24.938359
2038 23:42:24.938543 ==
2039 23:42:24.938726 Dram Type= 6, Freq= 0, CH_1, rank 1
2040 23:42:24.938909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2041 23:42:24.939093 ==
2042 23:42:24.939275 RX Vref Scan: 0
2043 23:42:24.939457
2044 23:42:24.939635 RX Vref 0 -> 0, step: 1
2045 23:42:24.939816
2046 23:42:24.939998 RX Delay -95 -> 252, step: 8
2047 23:42:24.940183 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2048 23:42:24.940439 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2049 23:42:24.940685 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2050 23:42:24.940874 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2051 23:42:24.941059 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2052 23:42:24.941242 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2053 23:42:24.941428 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2054 23:42:24.941610 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2055 23:42:24.941792 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2056 23:42:24.941973 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2057 23:42:24.942155 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
2058 23:42:24.942377 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
2059 23:42:24.942561 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2060 23:42:24.942745 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2061 23:42:24.942926 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2062 23:42:24.943081 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2063 23:42:24.943220 ==
2064 23:42:24.943360 Dram Type= 6, Freq= 0, CH_1, rank 1
2065 23:42:24.943502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2066 23:42:24.943676 ==
2067 23:42:24.943821 DQS Delay:
2068 23:42:24.943962 DQS0 = 0, DQS1 = 0
2069 23:42:24.944104 DQM Delay:
2070 23:42:24.944244 DQM0 = 87, DQM1 = 79
2071 23:42:24.944385 DQ Delay:
2072 23:42:24.944545 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2073 23:42:24.944695 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2074 23:42:24.944837 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =68
2075 23:42:24.944977 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =88
2076 23:42:24.945118
2077 23:42:24.945258
2078 23:42:24.945397 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f18, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 402 ps
2079 23:42:24.945542 CH1 RK1: MR19=606, MR18=1F18
2080 23:42:24.945683 CH1_RK1: MR19=0x606, MR18=0x1F18, DQSOSC=402, MR23=63, INC=91, DEC=60
2081 23:42:24.945824 [RxdqsGatingPostProcess] freq 800
2082 23:42:24.945964 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2083 23:42:24.946105 Pre-setting of DQS Precalculation
2084 23:42:24.946286 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2085 23:42:24.946430 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2086 23:42:24.946573 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2087 23:42:24.946714
2088 23:42:24.946854
2089 23:42:24.946991 [Calibration Summary] 1600 Mbps
2090 23:42:24.947131 CH 0, Rank 0
2091 23:42:24.947270 SW Impedance : PASS
2092 23:42:24.947410 DUTY Scan : NO K
2093 23:42:24.947550 ZQ Calibration : PASS
2094 23:42:24.947690 Jitter Meter : NO K
2095 23:42:24.947830 CBT Training : PASS
2096 23:42:24.947968 Write leveling : PASS
2097 23:42:24.948080 RX DQS gating : PASS
2098 23:42:24.948193 RX DQ/DQS(RDDQC) : PASS
2099 23:42:24.948305 TX DQ/DQS : PASS
2100 23:42:24.948419 RX DATLAT : PASS
2101 23:42:24.948533 RX DQ/DQS(Engine): PASS
2102 23:42:24.948646 TX OE : NO K
2103 23:42:24.948761 All Pass.
2104 23:42:24.948875
2105 23:42:24.949025 CH 0, Rank 1
2106 23:42:24.949192 SW Impedance : PASS
2107 23:42:24.949313 DUTY Scan : NO K
2108 23:42:24.949430 ZQ Calibration : PASS
2109 23:42:24.949545 Jitter Meter : NO K
2110 23:42:24.949961 CBT Training : PASS
2111 23:42:24.950149 Write leveling : PASS
2112 23:42:24.950306 RX DQS gating : PASS
2113 23:42:24.950437 RX DQ/DQS(RDDQC) : PASS
2114 23:42:24.950563 TX DQ/DQS : PASS
2115 23:42:24.950687 RX DATLAT : PASS
2116 23:42:24.950807 RX DQ/DQS(Engine): PASS
2117 23:42:24.950925 TX OE : NO K
2118 23:42:24.951050 All Pass.
2119 23:42:24.951170
2120 23:42:24.951287 CH 1, Rank 0
2121 23:42:24.951405 SW Impedance : PASS
2122 23:42:24.951523 DUTY Scan : NO K
2123 23:42:24.951639 ZQ Calibration : PASS
2124 23:42:24.951756 Jitter Meter : NO K
2125 23:42:24.951873 CBT Training : PASS
2126 23:42:24.951986 Write leveling : PASS
2127 23:42:24.952101 RX DQS gating : PASS
2128 23:42:24.952215 RX DQ/DQS(RDDQC) : PASS
2129 23:42:24.952329 TX DQ/DQS : PASS
2130 23:42:24.952443 RX DATLAT : PASS
2131 23:42:24.952557 RX DQ/DQS(Engine): PASS
2132 23:42:24.952673 TX OE : NO K
2133 23:42:24.952788 All Pass.
2134 23:42:24.952902
2135 23:42:24.953014 CH 1, Rank 1
2136 23:42:24.953111 SW Impedance : PASS
2137 23:42:24.953208 DUTY Scan : NO K
2138 23:42:24.953303 ZQ Calibration : PASS
2139 23:42:24.953400 Jitter Meter : NO K
2140 23:42:24.953496 CBT Training : PASS
2141 23:42:24.953593 Write leveling : PASS
2142 23:42:24.953689 RX DQS gating : PASS
2143 23:42:24.953785 RX DQ/DQS(RDDQC) : PASS
2144 23:42:24.953881 TX DQ/DQS : PASS
2145 23:42:24.953977 RX DATLAT : PASS
2146 23:42:24.954072 RX DQ/DQS(Engine): PASS
2147 23:42:24.954173 TX OE : NO K
2148 23:42:24.954272 All Pass.
2149 23:42:24.954369
2150 23:42:24.954463 DramC Write-DBI off
2151 23:42:24.954560 PER_BANK_REFRESH: Hybrid Mode
2152 23:42:24.954657 TX_TRACKING: ON
2153 23:42:24.954752 [GetDramInforAfterCalByMRR] Vendor 6.
2154 23:42:24.954848 [GetDramInforAfterCalByMRR] Revision 606.
2155 23:42:24.954945 [GetDramInforAfterCalByMRR] Revision 2 0.
2156 23:42:24.955042 MR0 0x3b3b
2157 23:42:24.955138 MR8 0x5151
2158 23:42:24.955234 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2159 23:42:24.955330
2160 23:42:24.955427 MR0 0x3b3b
2161 23:42:24.955523 MR8 0x5151
2162 23:42:24.955619 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2163 23:42:24.955715
2164 23:42:24.955811 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2165 23:42:24.955909 [FAST_K] Save calibration result to emmc
2166 23:42:24.956006 [FAST_K] Save calibration result to emmc
2167 23:42:24.956103 dram_init: config_dvfs: 1
2168 23:42:24.956199 dramc_set_vcore_voltage set vcore to 662500
2169 23:42:24.956295 Read voltage for 1200, 2
2170 23:42:24.956392 Vio18 = 0
2171 23:42:24.956488 Vcore = 662500
2172 23:42:24.956585 Vdram = 0
2173 23:42:24.956680 Vddq = 0
2174 23:42:24.956775 Vmddr = 0
2175 23:42:24.956870 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2176 23:42:24.956967 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2177 23:42:24.957064 MEM_TYPE=3, freq_sel=15
2178 23:42:24.957159 sv_algorithm_assistance_LP4_1600
2179 23:42:24.957255 ============ PULL DRAM RESETB DOWN ============
2180 23:42:24.957352 ========== PULL DRAM RESETB DOWN end =========
2181 23:42:24.957449 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2182 23:42:24.957545 ===================================
2183 23:42:24.957642 LPDDR4 DRAM CONFIGURATION
2184 23:42:24.957738 ===================================
2185 23:42:24.957835 EX_ROW_EN[0] = 0x0
2186 23:42:24.957932 EX_ROW_EN[1] = 0x0
2187 23:42:24.958028 LP4Y_EN = 0x0
2188 23:42:24.958124 WORK_FSP = 0x0
2189 23:42:24.958227 WL = 0x4
2190 23:42:24.958324 RL = 0x4
2191 23:42:24.958420 BL = 0x2
2192 23:42:24.958515 RPST = 0x0
2193 23:42:24.958611 RD_PRE = 0x0
2194 23:42:24.958707 WR_PRE = 0x1
2195 23:42:24.958802 WR_PST = 0x0
2196 23:42:24.958896 DBI_WR = 0x0
2197 23:42:24.958992 DBI_RD = 0x0
2198 23:42:24.959087 OTF = 0x1
2199 23:42:24.959185 ===================================
2200 23:42:24.959283 ===================================
2201 23:42:24.959380 ANA top config
2202 23:42:24.959475 ===================================
2203 23:42:24.959571 DLL_ASYNC_EN = 0
2204 23:42:24.959667 ALL_SLAVE_EN = 0
2205 23:42:24.959764 NEW_RANK_MODE = 1
2206 23:42:24.959862 DLL_IDLE_MODE = 1
2207 23:42:24.959957 LP45_APHY_COMB_EN = 1
2208 23:42:24.960053 TX_ODT_DIS = 1
2209 23:42:24.960150 NEW_8X_MODE = 1
2210 23:42:24.960247 ===================================
2211 23:42:24.960344 ===================================
2212 23:42:24.960440 data_rate = 2400
2213 23:42:24.960536 CKR = 1
2214 23:42:24.960632 DQ_P2S_RATIO = 8
2215 23:42:24.960728 ===================================
2216 23:42:24.960825 CA_P2S_RATIO = 8
2217 23:42:24.960921 DQ_CA_OPEN = 0
2218 23:42:24.961017 DQ_SEMI_OPEN = 0
2219 23:42:24.961113 CA_SEMI_OPEN = 0
2220 23:42:24.961209 CA_FULL_RATE = 0
2221 23:42:24.961305 DQ_CKDIV4_EN = 0
2222 23:42:24.961401 CA_CKDIV4_EN = 0
2223 23:42:24.961497 CA_PREDIV_EN = 0
2224 23:42:24.961593 PH8_DLY = 17
2225 23:42:24.961690 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2226 23:42:24.961786 DQ_AAMCK_DIV = 4
2227 23:42:24.961882 CA_AAMCK_DIV = 4
2228 23:42:24.961977 CA_ADMCK_DIV = 4
2229 23:42:24.962074 DQ_TRACK_CA_EN = 0
2230 23:42:24.962177 CA_PICK = 1200
2231 23:42:24.962276 CA_MCKIO = 1200
2232 23:42:24.962371 MCKIO_SEMI = 0
2233 23:42:24.962466 PLL_FREQ = 2366
2234 23:42:24.962562 DQ_UI_PI_RATIO = 32
2235 23:42:24.962658 CA_UI_PI_RATIO = 0
2236 23:42:24.962754 ===================================
2237 23:42:24.962850 ===================================
2238 23:42:24.962946 memory_type:LPDDR4
2239 23:42:24.963041 GP_NUM : 10
2240 23:42:24.963136 SRAM_EN : 1
2241 23:42:24.963233 MD32_EN : 0
2242 23:42:24.963328 ===================================
2243 23:42:24.963424 [ANA_INIT] >>>>>>>>>>>>>>
2244 23:42:24.963519 <<<<<< [CONFIGURE PHASE]: ANA_TX
2245 23:42:24.963615 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2246 23:42:24.963711 ===================================
2247 23:42:24.963807 data_rate = 2400,PCW = 0X5b00
2248 23:42:24.963902 ===================================
2249 23:42:24.963993 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2250 23:42:24.964048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2251 23:42:24.964102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2252 23:42:24.964350 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2253 23:42:24.964411 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2254 23:42:24.964466 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2255 23:42:24.964521 [ANA_INIT] flow start
2256 23:42:24.964575 [ANA_INIT] PLL >>>>>>>>
2257 23:42:24.964629 [ANA_INIT] PLL <<<<<<<<
2258 23:42:24.964684 [ANA_INIT] MIDPI >>>>>>>>
2259 23:42:24.964738 [ANA_INIT] MIDPI <<<<<<<<
2260 23:42:24.964791 [ANA_INIT] DLL >>>>>>>>
2261 23:42:24.964845 [ANA_INIT] DLL <<<<<<<<
2262 23:42:24.964899 [ANA_INIT] flow end
2263 23:42:24.964952 ============ LP4 DIFF to SE enter ============
2264 23:42:24.965006 ============ LP4 DIFF to SE exit ============
2265 23:42:24.965061 [ANA_INIT] <<<<<<<<<<<<<
2266 23:42:24.965114 [Flow] Enable top DCM control >>>>>
2267 23:42:24.965168 [Flow] Enable top DCM control <<<<<
2268 23:42:24.965222 Enable DLL master slave shuffle
2269 23:42:24.965276 ==============================================================
2270 23:42:24.965331 Gating Mode config
2271 23:42:24.965384 ==============================================================
2272 23:42:24.965439 Config description:
2273 23:42:24.965493 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2274 23:42:24.965548 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2275 23:42:24.965602 SELPH_MODE 0: By rank 1: By Phase
2276 23:42:24.965657 ==============================================================
2277 23:42:24.965711 GAT_TRACK_EN = 1
2278 23:42:24.965764 RX_GATING_MODE = 2
2279 23:42:24.965818 RX_GATING_TRACK_MODE = 2
2280 23:42:24.965872 SELPH_MODE = 1
2281 23:42:24.965925 PICG_EARLY_EN = 1
2282 23:42:24.965979 VALID_LAT_VALUE = 1
2283 23:42:24.966033 ==============================================================
2284 23:42:24.966088 Enter into Gating configuration >>>>
2285 23:42:24.966143 Exit from Gating configuration <<<<
2286 23:42:24.966237 Enter into DVFS_PRE_config >>>>>
2287 23:42:24.966293 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2288 23:42:24.966348 Exit from DVFS_PRE_config <<<<<
2289 23:42:24.966403 Enter into PICG configuration >>>>
2290 23:42:24.966457 Exit from PICG configuration <<<<
2291 23:42:24.966511 [RX_INPUT] configuration >>>>>
2292 23:42:24.966564 [RX_INPUT] configuration <<<<<
2293 23:42:24.966656 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2294 23:42:24.966754 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2295 23:42:24.966824 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2296 23:42:24.966878 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2297 23:42:24.966933 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2298 23:42:24.966986 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2299 23:42:24.967040 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2300 23:42:24.967094 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2301 23:42:24.967148 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2302 23:42:24.967201 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2303 23:42:24.967255 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2304 23:42:24.967309 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2305 23:42:24.967363 ===================================
2306 23:42:24.967417 LPDDR4 DRAM CONFIGURATION
2307 23:42:24.967471 ===================================
2308 23:42:24.967524 EX_ROW_EN[0] = 0x0
2309 23:42:24.967578 EX_ROW_EN[1] = 0x0
2310 23:42:24.967631 LP4Y_EN = 0x0
2311 23:42:24.967685 WORK_FSP = 0x0
2312 23:42:24.967738 WL = 0x4
2313 23:42:24.967792 RL = 0x4
2314 23:42:24.967845 BL = 0x2
2315 23:42:24.967898 RPST = 0x0
2316 23:42:24.967952 RD_PRE = 0x0
2317 23:42:24.968005 WR_PRE = 0x1
2318 23:42:24.968058 WR_PST = 0x0
2319 23:42:24.968112 DBI_WR = 0x0
2320 23:42:24.968165 DBI_RD = 0x0
2321 23:42:24.968219 OTF = 0x1
2322 23:42:24.968273 ===================================
2323 23:42:24.968327 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2324 23:42:24.968381 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2325 23:42:24.968435 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2326 23:42:24.968489 ===================================
2327 23:42:24.968542 LPDDR4 DRAM CONFIGURATION
2328 23:42:24.968596 ===================================
2329 23:42:24.968650 EX_ROW_EN[0] = 0x10
2330 23:42:24.968704 EX_ROW_EN[1] = 0x0
2331 23:42:24.968757 LP4Y_EN = 0x0
2332 23:42:24.968810 WORK_FSP = 0x0
2333 23:42:24.968863 WL = 0x4
2334 23:42:24.968916 RL = 0x4
2335 23:42:24.968969 BL = 0x2
2336 23:42:24.969022 RPST = 0x0
2337 23:42:24.969075 RD_PRE = 0x0
2338 23:42:24.969128 WR_PRE = 0x1
2339 23:42:24.969181 WR_PST = 0x0
2340 23:42:24.969234 DBI_WR = 0x0
2341 23:42:24.969287 DBI_RD = 0x0
2342 23:42:24.969339 OTF = 0x1
2343 23:42:24.969392 ===================================
2344 23:42:24.969446 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2345 23:42:24.969499 ==
2346 23:42:24.969553 Dram Type= 6, Freq= 0, CH_0, rank 0
2347 23:42:24.969606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2348 23:42:24.969660 ==
2349 23:42:24.969713 [Duty_Offset_Calibration]
2350 23:42:24.969766 B0:1 B1:-1 CA:0
2351 23:42:24.969819
2352 23:42:24.969872 [DutyScan_Calibration_Flow] k_type=0
2353 23:42:24.969925
2354 23:42:24.969978 ==CLK 0==
2355 23:42:24.970047 Final CLK duty delay cell = 0
2356 23:42:24.970103 [0] MAX Duty = 5094%(X100), DQS PI = 14
2357 23:42:24.970157 [0] MIN Duty = 4907%(X100), DQS PI = 8
2358 23:42:24.970229 [0] AVG Duty = 5000%(X100)
2359 23:42:24.970282
2360 23:42:24.970335 CH0 CLK Duty spec in!! Max-Min= 187%
2361 23:42:24.970389 [DutyScan_Calibration_Flow] ====Done====
2362 23:42:24.970443
2363 23:42:24.970495 [DutyScan_Calibration_Flow] k_type=1
2364 23:42:24.970548
2365 23:42:24.970600 ==DQS 0 ==
2366 23:42:24.970654 Final DQS duty delay cell = -4
2367 23:42:24.970707 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2368 23:42:24.970760 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2369 23:42:24.970814 [-4] AVG Duty = 4968%(X100)
2370 23:42:24.970868
2371 23:42:24.970920 ==DQS 1 ==
2372 23:42:24.971167 Final DQS duty delay cell = 0
2373 23:42:24.971228 [0] MAX Duty = 5124%(X100), DQS PI = 6
2374 23:42:24.971285 [0] MIN Duty = 5000%(X100), DQS PI = 20
2375 23:42:24.971340 [0] AVG Duty = 5062%(X100)
2376 23:42:24.971394
2377 23:42:24.971448 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2378 23:42:24.971501
2379 23:42:24.971554 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2380 23:42:24.971608 [DutyScan_Calibration_Flow] ====Done====
2381 23:42:24.971661
2382 23:42:24.971714 [DutyScan_Calibration_Flow] k_type=3
2383 23:42:24.971767
2384 23:42:24.971820 ==DQM 0 ==
2385 23:42:24.971874 Final DQM duty delay cell = 0
2386 23:42:24.971929 [0] MAX Duty = 5062%(X100), DQS PI = 18
2387 23:42:24.971983 [0] MIN Duty = 4844%(X100), DQS PI = 8
2388 23:42:24.972036 [0] AVG Duty = 4953%(X100)
2389 23:42:24.972089
2390 23:42:24.972142 ==DQM 1 ==
2391 23:42:24.972195 Final DQM duty delay cell = 4
2392 23:42:24.972249 [4] MAX Duty = 5187%(X100), DQS PI = 32
2393 23:42:24.972302 [4] MIN Duty = 5000%(X100), DQS PI = 22
2394 23:42:24.972356 [4] AVG Duty = 5093%(X100)
2395 23:42:24.972409
2396 23:42:24.972462 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2397 23:42:24.972516
2398 23:42:24.972569 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2399 23:42:24.972623 [DutyScan_Calibration_Flow] ====Done====
2400 23:42:24.972676
2401 23:42:24.972729 [DutyScan_Calibration_Flow] k_type=2
2402 23:42:24.972783
2403 23:42:24.972836 ==DQ 0 ==
2404 23:42:24.972889 Final DQ duty delay cell = -4
2405 23:42:24.972943 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2406 23:42:24.972996 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2407 23:42:24.973050 [-4] AVG Duty = 4969%(X100)
2408 23:42:24.973102
2409 23:42:24.973156 ==DQ 1 ==
2410 23:42:24.973209 Final DQ duty delay cell = -4
2411 23:42:24.973262 [-4] MAX Duty = 4969%(X100), DQS PI = 52
2412 23:42:24.973315 [-4] MIN Duty = 4876%(X100), DQS PI = 14
2413 23:42:24.973368 [-4] AVG Duty = 4922%(X100)
2414 23:42:24.973422
2415 23:42:24.973475 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2416 23:42:24.973529
2417 23:42:24.973582 CH0 DQ 1 Duty spec in!! Max-Min= 93%
2418 23:42:24.973636 [DutyScan_Calibration_Flow] ====Done====
2419 23:42:24.973689 ==
2420 23:42:24.973743 Dram Type= 6, Freq= 0, CH_1, rank 0
2421 23:42:24.973797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2422 23:42:24.973850 ==
2423 23:42:24.973904 [Duty_Offset_Calibration]
2424 23:42:24.973957 B0:-1 B1:1 CA:1
2425 23:42:24.974011
2426 23:42:24.974065 [DutyScan_Calibration_Flow] k_type=0
2427 23:42:24.974118
2428 23:42:24.974176 ==CLK 0==
2429 23:42:24.974264 Final CLK duty delay cell = 0
2430 23:42:24.974318 [0] MAX Duty = 5156%(X100), DQS PI = 20
2431 23:42:24.974372 [0] MIN Duty = 4969%(X100), DQS PI = 60
2432 23:42:24.974425 [0] AVG Duty = 5062%(X100)
2433 23:42:24.974478
2434 23:42:24.974531 CH1 CLK Duty spec in!! Max-Min= 187%
2435 23:42:24.974584 [DutyScan_Calibration_Flow] ====Done====
2436 23:42:24.974637
2437 23:42:24.974691 [DutyScan_Calibration_Flow] k_type=1
2438 23:42:24.974744
2439 23:42:24.974797 ==DQS 0 ==
2440 23:42:24.974850 Final DQS duty delay cell = 0
2441 23:42:24.974903 [0] MAX Duty = 5125%(X100), DQS PI = 48
2442 23:42:24.974957 [0] MIN Duty = 4875%(X100), DQS PI = 6
2443 23:42:24.975010 [0] AVG Duty = 5000%(X100)
2444 23:42:24.975063
2445 23:42:24.975117 ==DQS 1 ==
2446 23:42:24.975170 Final DQS duty delay cell = 0
2447 23:42:24.975223 [0] MAX Duty = 5062%(X100), DQS PI = 12
2448 23:42:24.975277 [0] MIN Duty = 4969%(X100), DQS PI = 56
2449 23:42:24.975330 [0] AVG Duty = 5015%(X100)
2450 23:42:24.975383
2451 23:42:24.975435 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2452 23:42:24.975488
2453 23:42:24.975541 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2454 23:42:24.975594 [DutyScan_Calibration_Flow] ====Done====
2455 23:42:24.975647
2456 23:42:24.975700 [DutyScan_Calibration_Flow] k_type=3
2457 23:42:24.975752
2458 23:42:24.975805 ==DQM 0 ==
2459 23:42:24.975859 Final DQM duty delay cell = -4
2460 23:42:24.975913 [-4] MAX Duty = 5031%(X100), DQS PI = 36
2461 23:42:24.975966 [-4] MIN Duty = 4844%(X100), DQS PI = 6
2462 23:42:24.976018 [-4] AVG Duty = 4937%(X100)
2463 23:42:24.976071
2464 23:42:24.976124 ==DQM 1 ==
2465 23:42:24.976177 Final DQM duty delay cell = 0
2466 23:42:24.976230 [0] MAX Duty = 5125%(X100), DQS PI = 2
2467 23:42:24.976284 [0] MIN Duty = 4969%(X100), DQS PI = 28
2468 23:42:24.976337 [0] AVG Duty = 5047%(X100)
2469 23:42:24.976390
2470 23:42:24.976443 CH1 DQM 0 Duty spec in!! Max-Min= 187%
2471 23:42:24.976496
2472 23:42:24.976549 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2473 23:42:24.976602 [DutyScan_Calibration_Flow] ====Done====
2474 23:42:24.976654
2475 23:42:24.976707 [DutyScan_Calibration_Flow] k_type=2
2476 23:42:24.976760
2477 23:42:24.976813 ==DQ 0 ==
2478 23:42:24.976866 Final DQ duty delay cell = 0
2479 23:42:24.976920 [0] MAX Duty = 5187%(X100), DQS PI = 30
2480 23:42:24.976973 [0] MIN Duty = 4876%(X100), DQS PI = 8
2481 23:42:24.977025 [0] AVG Duty = 5031%(X100)
2482 23:42:24.977078
2483 23:42:24.977130 ==DQ 1 ==
2484 23:42:24.977183 Final DQ duty delay cell = 0
2485 23:42:24.977237 [0] MAX Duty = 5124%(X100), DQS PI = 10
2486 23:42:24.977290 [0] MIN Duty = 4969%(X100), DQS PI = 0
2487 23:42:24.977343 [0] AVG Duty = 5046%(X100)
2488 23:42:24.977395
2489 23:42:24.977448 CH1 DQ 0 Duty spec in!! Max-Min= 311%
2490 23:42:24.977500
2491 23:42:24.977553 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2492 23:42:24.977606 [DutyScan_Calibration_Flow] ====Done====
2493 23:42:24.977660 nWR fixed to 30
2494 23:42:24.977713 [ModeRegInit_LP4] CH0 RK0
2495 23:42:24.977766 [ModeRegInit_LP4] CH0 RK1
2496 23:42:24.977820 [ModeRegInit_LP4] CH1 RK0
2497 23:42:24.977873 [ModeRegInit_LP4] CH1 RK1
2498 23:42:24.977925 match AC timing 7
2499 23:42:24.977979 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2500 23:42:24.978032 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2501 23:42:24.978087 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2502 23:42:24.978140 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2503 23:42:24.978230 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2504 23:42:24.978284 ==
2505 23:42:24.978337 Dram Type= 6, Freq= 0, CH_0, rank 0
2506 23:42:24.978391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2507 23:42:24.978444 ==
2508 23:42:24.978498 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2509 23:42:24.978551 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2510 23:42:24.978604 [CA 0] Center 39 (9~70) winsize 62
2511 23:42:24.978658 [CA 1] Center 39 (9~70) winsize 62
2512 23:42:24.978711 [CA 2] Center 35 (5~66) winsize 62
2513 23:42:24.978765 [CA 3] Center 35 (5~65) winsize 61
2514 23:42:24.978817 [CA 4] Center 33 (3~64) winsize 62
2515 23:42:24.978871 [CA 5] Center 33 (4~63) winsize 60
2516 23:42:24.978923
2517 23:42:24.978976 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2518 23:42:24.979030
2519 23:42:24.979083 [CATrainingPosCal] consider 1 rank data
2520 23:42:24.979137 u2DelayCellTimex100 = 270/100 ps
2521 23:42:24.979189 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2522 23:42:24.979440 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2523 23:42:24.979501 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2524 23:42:24.979555 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2525 23:42:24.979609 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2526 23:42:24.979663 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2527 23:42:24.979716
2528 23:42:24.979769 CA PerBit enable=1, Macro0, CA PI delay=33
2529 23:42:24.979822
2530 23:42:24.979875 [CBTSetCACLKResult] CA Dly = 33
2531 23:42:24.979928 CS Dly: 8 (0~39)
2532 23:42:24.979981 ==
2533 23:42:24.980034 Dram Type= 6, Freq= 0, CH_0, rank 1
2534 23:42:24.980086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 23:42:24.980140 ==
2536 23:42:24.980192 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2537 23:42:24.980246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2538 23:42:24.980300 [CA 0] Center 39 (9~70) winsize 62
2539 23:42:24.980359 [CA 1] Center 39 (9~70) winsize 62
2540 23:42:24.980413 [CA 2] Center 35 (5~66) winsize 62
2541 23:42:24.980467 [CA 3] Center 34 (4~65) winsize 62
2542 23:42:24.980519 [CA 4] Center 33 (3~64) winsize 62
2543 23:42:24.980573 [CA 5] Center 33 (3~63) winsize 61
2544 23:42:24.980626
2545 23:42:24.980679 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2546 23:42:24.980732
2547 23:42:24.980786 [CATrainingPosCal] consider 2 rank data
2548 23:42:24.980840 u2DelayCellTimex100 = 270/100 ps
2549 23:42:24.980894 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2550 23:42:24.980947 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2551 23:42:24.981001 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2552 23:42:24.981054 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2553 23:42:24.981108 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2554 23:42:24.981161 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
2555 23:42:24.981215
2556 23:42:24.981268 CA PerBit enable=1, Macro0, CA PI delay=33
2557 23:42:24.981322
2558 23:42:24.981374 [CBTSetCACLKResult] CA Dly = 33
2559 23:42:24.981428 CS Dly: 9 (0~41)
2560 23:42:24.981482
2561 23:42:24.981535 ----->DramcWriteLeveling(PI) begin...
2562 23:42:24.981590 ==
2563 23:42:24.981644 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 23:42:24.981698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2565 23:42:24.981752 ==
2566 23:42:24.981805 Write leveling (Byte 0): 32 => 32
2567 23:42:24.981859 Write leveling (Byte 1): 30 => 30
2568 23:42:24.981913 DramcWriteLeveling(PI) end<-----
2569 23:42:24.981966
2570 23:42:24.982019 ==
2571 23:42:24.982072 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 23:42:24.982126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 23:42:24.982218 ==
2574 23:42:24.982273 [Gating] SW mode calibration
2575 23:42:24.982336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2576 23:42:24.982400 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2577 23:42:24.982462 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2578 23:42:24.982524 0 15 4 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
2579 23:42:24.982587 0 15 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2580 23:42:24.982649 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 23:42:24.982710 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 23:42:24.982771 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 23:42:24.982832 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 23:42:24.982893 0 15 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
2585 23:42:24.982953 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2586 23:42:24.983013 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 23:42:24.983074 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 23:42:24.983135 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 23:42:24.983195 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 23:42:24.983256 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 23:42:24.983316 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 23:42:24.983376 1 0 28 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
2593 23:42:24.983438 1 1 0 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)
2594 23:42:24.983498 1 1 4 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
2595 23:42:24.983558 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 23:42:24.983619 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 23:42:24.983679 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 23:42:24.983739 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 23:42:24.983800 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 23:42:24.983860 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2601 23:42:24.983920 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2602 23:42:24.983981 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2603 23:42:24.984040 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 23:42:24.984100 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 23:42:24.984160 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 23:42:24.984220 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 23:42:24.984280 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 23:42:24.984340 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 23:42:24.984400 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 23:42:24.984461 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:42:24.984521 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:42:24.984582 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:42:24.984643 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:42:24.984703 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:42:24.984764 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:42:24.984824 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2617 23:42:24.984884 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2618 23:42:24.984944 Total UI for P1: 0, mck2ui 16
2619 23:42:24.985005 best dqsien dly found for B0: ( 1, 3, 28)
2620 23:42:24.985065 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 23:42:24.985125 Total UI for P1: 0, mck2ui 16
2622 23:42:24.985185 best dqsien dly found for B1: ( 1, 4, 0)
2623 23:42:24.985245 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2624 23:42:24.985304 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2625 23:42:24.985364
2626 23:42:24.985614 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2627 23:42:24.985735 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2628 23:42:24.985825 [Gating] SW calibration Done
2629 23:42:24.985913 ==
2630 23:42:24.985970 Dram Type= 6, Freq= 0, CH_0, rank 0
2631 23:42:24.986027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2632 23:42:24.986083 ==
2633 23:42:24.986139 RX Vref Scan: 0
2634 23:42:24.986214
2635 23:42:24.986268 RX Vref 0 -> 0, step: 1
2636 23:42:24.986322
2637 23:42:24.986376 RX Delay -40 -> 252, step: 8
2638 23:42:24.986430 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2639 23:42:24.986484 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2640 23:42:24.986537 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2641 23:42:24.986591 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2642 23:42:24.986645 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2643 23:42:24.986698 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2644 23:42:24.986752 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2645 23:42:24.986806 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2646 23:42:24.986859 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2647 23:42:24.986913 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2648 23:42:24.986966 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2649 23:42:24.987020 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2650 23:42:24.987075 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2651 23:42:24.987128 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2652 23:42:24.987181 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2653 23:42:24.987235 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2654 23:42:24.987289 ==
2655 23:42:24.987341 Dram Type= 6, Freq= 0, CH_0, rank 0
2656 23:42:24.987395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2657 23:42:24.987449 ==
2658 23:42:24.987503 DQS Delay:
2659 23:42:24.987556 DQS0 = 0, DQS1 = 0
2660 23:42:24.987609 DQM Delay:
2661 23:42:24.987662 DQM0 = 118, DQM1 = 106
2662 23:42:24.987716 DQ Delay:
2663 23:42:24.987769 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2664 23:42:24.987822 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2665 23:42:24.987876 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2666 23:42:24.987929 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2667 23:42:24.987982
2668 23:42:24.988035
2669 23:42:24.988088 ==
2670 23:42:24.988141 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 23:42:24.988194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 23:42:24.988248 ==
2673 23:42:24.988301
2674 23:42:24.988354
2675 23:42:24.988407 TX Vref Scan disable
2676 23:42:24.988460 == TX Byte 0 ==
2677 23:42:24.988513 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2678 23:42:24.988567 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2679 23:42:24.988620 == TX Byte 1 ==
2680 23:42:24.988673 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2681 23:42:24.988726 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2682 23:42:24.988779 ==
2683 23:42:24.988832 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 23:42:24.988884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 23:42:24.988938 ==
2686 23:42:24.988991 TX Vref=22, minBit 1, minWin=25, winSum=416
2687 23:42:24.989045 TX Vref=24, minBit 13, minWin=25, winSum=424
2688 23:42:24.989098 TX Vref=26, minBit 1, minWin=26, winSum=427
2689 23:42:24.989152 TX Vref=28, minBit 4, minWin=26, winSum=431
2690 23:42:24.989206 TX Vref=30, minBit 10, minWin=26, winSum=432
2691 23:42:24.989261 TX Vref=32, minBit 4, minWin=26, winSum=430
2692 23:42:24.989314 [TxChooseVref] Worse bit 10, Min win 26, Win sum 432, Final Vref 30
2693 23:42:24.989368
2694 23:42:24.989421 Final TX Range 1 Vref 30
2695 23:42:24.989474
2696 23:42:24.989527 ==
2697 23:42:24.989580 Dram Type= 6, Freq= 0, CH_0, rank 0
2698 23:42:24.989634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2699 23:42:24.989687 ==
2700 23:42:24.989740
2701 23:42:24.989793
2702 23:42:24.989845 TX Vref Scan disable
2703 23:42:24.989898 == TX Byte 0 ==
2704 23:42:24.989950 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2705 23:42:24.990004 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2706 23:42:24.990058 == TX Byte 1 ==
2707 23:42:24.990111 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2708 23:42:24.990166 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2709 23:42:24.990221
2710 23:42:24.990274 [DATLAT]
2711 23:42:24.990327 Freq=1200, CH0 RK0
2712 23:42:24.990380
2713 23:42:24.990433 DATLAT Default: 0xd
2714 23:42:24.990487 0, 0xFFFF, sum = 0
2715 23:42:24.990542 1, 0xFFFF, sum = 0
2716 23:42:24.990597 2, 0xFFFF, sum = 0
2717 23:42:24.990651 3, 0xFFFF, sum = 0
2718 23:42:24.990744 4, 0xFFFF, sum = 0
2719 23:42:24.990799 5, 0xFFFF, sum = 0
2720 23:42:24.990852 6, 0xFFFF, sum = 0
2721 23:42:24.990906 7, 0xFFFF, sum = 0
2722 23:42:24.990959 8, 0xFFFF, sum = 0
2723 23:42:24.991013 9, 0xFFFF, sum = 0
2724 23:42:24.991066 10, 0xFFFF, sum = 0
2725 23:42:24.991121 11, 0xFFFF, sum = 0
2726 23:42:24.991175 12, 0x0, sum = 1
2727 23:42:24.991229 13, 0x0, sum = 2
2728 23:42:24.991284 14, 0x0, sum = 3
2729 23:42:24.991337 15, 0x0, sum = 4
2730 23:42:24.991391 best_step = 13
2731 23:42:24.991444
2732 23:42:24.991497 ==
2733 23:42:24.991550 Dram Type= 6, Freq= 0, CH_0, rank 0
2734 23:42:24.991604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2735 23:42:24.991658 ==
2736 23:42:24.991712 RX Vref Scan: 1
2737 23:42:24.991764
2738 23:42:24.991818 Set Vref Range= 32 -> 127
2739 23:42:24.991871
2740 23:42:24.991923 RX Vref 32 -> 127, step: 1
2741 23:42:24.991976
2742 23:42:24.992029 RX Delay -21 -> 252, step: 4
2743 23:42:24.992082
2744 23:42:24.992135 Set Vref, RX VrefLevel [Byte0]: 32
2745 23:42:24.992189 [Byte1]: 32
2746 23:42:24.992242
2747 23:42:24.992295 Set Vref, RX VrefLevel [Byte0]: 33
2748 23:42:24.992348 [Byte1]: 33
2749 23:42:24.992401
2750 23:42:24.992454 Set Vref, RX VrefLevel [Byte0]: 34
2751 23:42:24.992507 [Byte1]: 34
2752 23:42:24.992560
2753 23:42:24.992613 Set Vref, RX VrefLevel [Byte0]: 35
2754 23:42:24.992666 [Byte1]: 35
2755 23:42:24.992719
2756 23:42:24.992772 Set Vref, RX VrefLevel [Byte0]: 36
2757 23:42:24.992825 [Byte1]: 36
2758 23:42:24.992878
2759 23:42:24.992930 Set Vref, RX VrefLevel [Byte0]: 37
2760 23:42:24.992983 [Byte1]: 37
2761 23:42:24.993036
2762 23:42:24.993088 Set Vref, RX VrefLevel [Byte0]: 38
2763 23:42:24.993142 [Byte1]: 38
2764 23:42:24.993195
2765 23:42:24.993248 Set Vref, RX VrefLevel [Byte0]: 39
2766 23:42:24.993302 [Byte1]: 39
2767 23:42:24.993355
2768 23:42:24.993407 Set Vref, RX VrefLevel [Byte0]: 40
2769 23:42:24.993460 [Byte1]: 40
2770 23:42:24.993513
2771 23:42:24.993566 Set Vref, RX VrefLevel [Byte0]: 41
2772 23:42:24.993619 [Byte1]: 41
2773 23:42:24.993672
2774 23:42:24.993725 Set Vref, RX VrefLevel [Byte0]: 42
2775 23:42:24.993779 [Byte1]: 42
2776 23:42:24.993832
2777 23:42:24.993884 Set Vref, RX VrefLevel [Byte0]: 43
2778 23:42:24.993939 [Byte1]: 43
2779 23:42:24.993992
2780 23:42:24.994044 Set Vref, RX VrefLevel [Byte0]: 44
2781 23:42:24.994097 [Byte1]: 44
2782 23:42:24.994150
2783 23:42:24.994430 Set Vref, RX VrefLevel [Byte0]: 45
2784 23:42:24.994490 [Byte1]: 45
2785 23:42:24.994546
2786 23:42:24.994600 Set Vref, RX VrefLevel [Byte0]: 46
2787 23:42:24.994654 [Byte1]: 46
2788 23:42:24.994707
2789 23:42:24.994761 Set Vref, RX VrefLevel [Byte0]: 47
2790 23:42:24.994844 [Byte1]: 47
2791 23:42:24.994898
2792 23:42:24.994950 Set Vref, RX VrefLevel [Byte0]: 48
2793 23:42:24.995004 [Byte1]: 48
2794 23:42:24.995058
2795 23:42:24.995111 Set Vref, RX VrefLevel [Byte0]: 49
2796 23:42:24.995164 [Byte1]: 49
2797 23:42:24.995217
2798 23:42:24.995270 Set Vref, RX VrefLevel [Byte0]: 50
2799 23:42:24.995324 [Byte1]: 50
2800 23:42:24.995377
2801 23:42:24.995430 Set Vref, RX VrefLevel [Byte0]: 51
2802 23:42:24.995507 [Byte1]: 51
2803 23:42:24.995572
2804 23:42:24.995627 Set Vref, RX VrefLevel [Byte0]: 52
2805 23:42:24.995685 [Byte1]: 52
2806 23:42:24.995739
2807 23:42:24.995792 Set Vref, RX VrefLevel [Byte0]: 53
2808 23:42:24.995846 [Byte1]: 53
2809 23:42:24.995900
2810 23:42:24.995952 Set Vref, RX VrefLevel [Byte0]: 54
2811 23:42:24.996005 [Byte1]: 54
2812 23:42:24.996058
2813 23:42:24.996111 Set Vref, RX VrefLevel [Byte0]: 55
2814 23:42:24.996173 [Byte1]: 55
2815 23:42:24.996231
2816 23:42:24.996284 Set Vref, RX VrefLevel [Byte0]: 56
2817 23:42:24.996339 [Byte1]: 56
2818 23:42:24.996393
2819 23:42:24.996447 Set Vref, RX VrefLevel [Byte0]: 57
2820 23:42:24.996501 [Byte1]: 57
2821 23:42:24.996556
2822 23:42:24.996609 Set Vref, RX VrefLevel [Byte0]: 58
2823 23:42:24.996663 [Byte1]: 58
2824 23:42:24.996716
2825 23:42:24.996769 Set Vref, RX VrefLevel [Byte0]: 59
2826 23:42:24.996823 [Byte1]: 59
2827 23:42:24.996876
2828 23:42:24.996928 Set Vref, RX VrefLevel [Byte0]: 60
2829 23:42:24.996982 [Byte1]: 60
2830 23:42:24.997035
2831 23:42:24.997088 Set Vref, RX VrefLevel [Byte0]: 61
2832 23:42:24.997142 [Byte1]: 61
2833 23:42:24.997195
2834 23:42:24.997247 Set Vref, RX VrefLevel [Byte0]: 62
2835 23:42:24.997300 [Byte1]: 62
2836 23:42:24.997354
2837 23:42:24.997406 Set Vref, RX VrefLevel [Byte0]: 63
2838 23:42:24.997460 [Byte1]: 63
2839 23:42:24.997514
2840 23:42:24.997567 Set Vref, RX VrefLevel [Byte0]: 64
2841 23:42:24.997620 [Byte1]: 64
2842 23:42:24.997673
2843 23:42:24.997726 Set Vref, RX VrefLevel [Byte0]: 65
2844 23:42:24.997780 [Byte1]: 65
2845 23:42:24.997832
2846 23:42:24.997885 Set Vref, RX VrefLevel [Byte0]: 66
2847 23:42:24.997939 [Byte1]: 66
2848 23:42:24.997992
2849 23:42:24.998044 Set Vref, RX VrefLevel [Byte0]: 67
2850 23:42:24.998098 [Byte1]: 67
2851 23:42:24.998151
2852 23:42:24.998250 Set Vref, RX VrefLevel [Byte0]: 68
2853 23:42:24.998303 [Byte1]: 68
2854 23:42:24.998357
2855 23:42:24.998409 Set Vref, RX VrefLevel [Byte0]: 69
2856 23:42:24.998463 [Byte1]: 69
2857 23:42:24.998515
2858 23:42:24.998568 Set Vref, RX VrefLevel [Byte0]: 70
2859 23:42:24.998622 [Byte1]: 70
2860 23:42:24.998697
2861 23:42:24.998762 Set Vref, RX VrefLevel [Byte0]: 71
2862 23:42:24.998819 [Byte1]: 71
2863 23:42:24.998873
2864 23:42:24.998927 Set Vref, RX VrefLevel [Byte0]: 72
2865 23:42:24.998980 [Byte1]: 72
2866 23:42:24.999034
2867 23:42:24.999087 Set Vref, RX VrefLevel [Byte0]: 73
2868 23:42:24.999141 [Byte1]: 73
2869 23:42:24.999195
2870 23:42:24.999248 Set Vref, RX VrefLevel [Byte0]: 74
2871 23:42:24.999302 [Byte1]: 74
2872 23:42:24.999356
2873 23:42:24.999409 Set Vref, RX VrefLevel [Byte0]: 75
2874 23:42:24.999463 [Byte1]: 75
2875 23:42:24.999516
2876 23:42:24.999569 Set Vref, RX VrefLevel [Byte0]: 76
2877 23:42:24.999622 [Byte1]: 76
2878 23:42:24.999675
2879 23:42:24.999728 Set Vref, RX VrefLevel [Byte0]: 77
2880 23:42:24.999782 [Byte1]: 77
2881 23:42:24.999834
2882 23:42:24.999887 Set Vref, RX VrefLevel [Byte0]: 78
2883 23:42:24.999941 [Byte1]: 78
2884 23:42:24.999994
2885 23:42:25.000046 Final RX Vref Byte 0 = 59 to rank0
2886 23:42:25.000100 Final RX Vref Byte 1 = 58 to rank0
2887 23:42:25.000154 Final RX Vref Byte 0 = 59 to rank1
2888 23:42:25.000208 Final RX Vref Byte 1 = 58 to rank1==
2889 23:42:25.000261 Dram Type= 6, Freq= 0, CH_0, rank 0
2890 23:42:25.000314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 23:42:25.000369 ==
2892 23:42:25.000422 DQS Delay:
2893 23:42:25.000474 DQS0 = 0, DQS1 = 0
2894 23:42:25.000528 DQM Delay:
2895 23:42:25.000581 DQM0 = 118, DQM1 = 107
2896 23:42:25.000634 DQ Delay:
2897 23:42:25.000687 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =114
2898 23:42:25.000740 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =124
2899 23:42:25.000793 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =100
2900 23:42:25.000846 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2901 23:42:25.000900
2902 23:42:25.000952
2903 23:42:25.001006 [DQSOSCAuto] RK0, (LSB)MR18= 0x12fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 403 ps
2904 23:42:25.001061 CH0 RK0: MR19=403, MR18=12FE
2905 23:42:25.001115 CH0_RK0: MR19=0x403, MR18=0x12FE, DQSOSC=403, MR23=63, INC=40, DEC=26
2906 23:42:25.001168
2907 23:42:25.001222 ----->DramcWriteLeveling(PI) begin...
2908 23:42:25.001276 ==
2909 23:42:25.001330 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 23:42:25.001383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 23:42:25.001437 ==
2912 23:42:25.001490 Write leveling (Byte 0): 32 => 32
2913 23:42:25.001544 Write leveling (Byte 1): 32 => 32
2914 23:42:25.001597 DramcWriteLeveling(PI) end<-----
2915 23:42:25.001651
2916 23:42:25.001703 ==
2917 23:42:25.001756 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 23:42:25.001824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2919 23:42:25.001892 ==
2920 23:42:25.001945 [Gating] SW mode calibration
2921 23:42:25.001999 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2922 23:42:25.002053 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2923 23:42:25.002107 0 15 0 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
2924 23:42:25.002164 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2925 23:42:25.002249 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2926 23:42:25.002302 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2927 23:42:25.002376 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 23:42:25.002443 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 23:42:25.002693 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2930 23:42:25.002758 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2931 23:42:25.002814 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2932 23:42:25.002869 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 23:42:25.002924 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2934 23:42:25.002979 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2935 23:42:25.003033 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 23:42:25.003087 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 23:42:25.003140 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 23:42:25.003194 1 0 28 | B1->B0 | 2424 3232 | 0 0 | (0 0) (1 1)
2939 23:42:25.003247 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
2940 23:42:25.003302 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 23:42:25.003356 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 23:42:25.003410 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2943 23:42:25.003464 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 23:42:25.003517 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 23:42:25.003570 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 23:42:25.003624 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2947 23:42:25.003678 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 23:42:25.003731 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 23:42:25.003785 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 23:42:25.003838 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 23:42:25.003892 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 23:42:25.003946 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 23:42:25.003999 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 23:42:25.004053 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 23:42:25.004106 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 23:42:25.004159 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 23:42:25.004213 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 23:42:25.004266 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 23:42:25.004319 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 23:42:25.004373 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 23:42:25.004426 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2962 23:42:25.004480 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2963 23:42:25.004533 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2964 23:42:25.004586 Total UI for P1: 0, mck2ui 16
2965 23:42:25.004640 best dqsien dly found for B0: ( 1, 3, 26)
2966 23:42:25.004694 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 23:42:25.004748 Total UI for P1: 0, mck2ui 16
2968 23:42:25.004802 best dqsien dly found for B1: ( 1, 4, 0)
2969 23:42:25.004855 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2970 23:42:25.004909 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2971 23:42:25.004962
2972 23:42:25.005015 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2973 23:42:25.005069 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2974 23:42:25.005123 [Gating] SW calibration Done
2975 23:42:25.209546 ==
2976 23:42:25.209691 Dram Type= 6, Freq= 0, CH_0, rank 1
2977 23:42:25.209758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2978 23:42:25.209820 ==
2979 23:42:25.209894 RX Vref Scan: 0
2980 23:42:25.209956
2981 23:42:25.210017 RX Vref 0 -> 0, step: 1
2982 23:42:25.210076
2983 23:42:25.210135 RX Delay -40 -> 252, step: 8
2984 23:42:25.210211 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2985 23:42:25.210272 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2986 23:42:25.210331 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2987 23:42:25.210390 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2988 23:42:25.210449 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2989 23:42:25.210508 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2990 23:42:25.210566 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2991 23:42:25.210624 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2992 23:42:25.210682 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2993 23:42:25.210740 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2994 23:42:25.210797 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2995 23:42:25.210855 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2996 23:42:25.210912 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2997 23:42:25.210969 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2998 23:42:25.211026 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2999 23:42:25.211083 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3000 23:42:25.211140 ==
3001 23:42:25.211198 Dram Type= 6, Freq= 0, CH_0, rank 1
3002 23:42:25.211255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3003 23:42:25.211313 ==
3004 23:42:25.211370 DQS Delay:
3005 23:42:25.211426 DQS0 = 0, DQS1 = 0
3006 23:42:25.211484 DQM Delay:
3007 23:42:25.211542 DQM0 = 116, DQM1 = 108
3008 23:42:25.211599 DQ Delay:
3009 23:42:25.211656 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3010 23:42:25.211713 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3011 23:42:25.211770 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3012 23:42:25.211827 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
3013 23:42:25.211884
3014 23:42:25.211940
3015 23:42:25.211997 ==
3016 23:42:25.212055 Dram Type= 6, Freq= 0, CH_0, rank 1
3017 23:42:25.212112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3018 23:42:25.212169 ==
3019 23:42:25.212226
3020 23:42:25.212283
3021 23:42:25.212339 TX Vref Scan disable
3022 23:42:25.212396 == TX Byte 0 ==
3023 23:42:25.212457 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3024 23:42:25.212515 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3025 23:42:25.212573 == TX Byte 1 ==
3026 23:42:25.212630 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3027 23:42:25.212687 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3028 23:42:25.212744 ==
3029 23:42:25.212802 Dram Type= 6, Freq= 0, CH_0, rank 1
3030 23:42:25.212859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3031 23:42:25.212916 ==
3032 23:42:25.212974 TX Vref=22, minBit 0, minWin=26, winSum=420
3033 23:42:25.213033 TX Vref=24, minBit 5, minWin=25, winSum=423
3034 23:42:25.213091 TX Vref=26, minBit 1, minWin=26, winSum=427
3035 23:42:25.213149 TX Vref=28, minBit 2, minWin=26, winSum=431
3036 23:42:25.213206 TX Vref=30, minBit 1, minWin=27, winSum=435
3037 23:42:25.213479 TX Vref=32, minBit 10, minWin=26, winSum=430
3038 23:42:25.213581 [TxChooseVref] Worse bit 1, Min win 27, Win sum 435, Final Vref 30
3039 23:42:25.213699
3040 23:42:25.213816 Final TX Range 1 Vref 30
3041 23:42:25.213933
3042 23:42:25.214034 ==
3043 23:42:25.214131 Dram Type= 6, Freq= 0, CH_0, rank 1
3044 23:42:25.214202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 23:42:25.214262 ==
3046 23:42:25.214321
3047 23:42:25.214379
3048 23:42:25.214437 TX Vref Scan disable
3049 23:42:25.214494 == TX Byte 0 ==
3050 23:42:25.214561 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3051 23:42:25.214655 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3052 23:42:25.214744 == TX Byte 1 ==
3053 23:42:25.214834 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3054 23:42:25.214944 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3055 23:42:25.215040
3056 23:42:25.215135 [DATLAT]
3057 23:42:25.215231 Freq=1200, CH0 RK1
3058 23:42:25.215327
3059 23:42:25.215423 DATLAT Default: 0xd
3060 23:42:25.215521 0, 0xFFFF, sum = 0
3061 23:42:25.215620 1, 0xFFFF, sum = 0
3062 23:42:25.215719 2, 0xFFFF, sum = 0
3063 23:42:25.215818 3, 0xFFFF, sum = 0
3064 23:42:25.215926 4, 0xFFFF, sum = 0
3065 23:42:25.216011 5, 0xFFFF, sum = 0
3066 23:42:25.216075 6, 0xFFFF, sum = 0
3067 23:42:25.216131 7, 0xFFFF, sum = 0
3068 23:42:25.216187 8, 0xFFFF, sum = 0
3069 23:42:25.216242 9, 0xFFFF, sum = 0
3070 23:42:25.216297 10, 0xFFFF, sum = 0
3071 23:42:25.216351 11, 0xFFFF, sum = 0
3072 23:42:25.216407 12, 0x0, sum = 1
3073 23:42:25.216461 13, 0x0, sum = 2
3074 23:42:25.216516 14, 0x0, sum = 3
3075 23:42:25.216570 15, 0x0, sum = 4
3076 23:42:25.216624 best_step = 13
3077 23:42:25.216678
3078 23:42:25.216731 ==
3079 23:42:25.216785 Dram Type= 6, Freq= 0, CH_0, rank 1
3080 23:42:25.216839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 23:42:25.216894 ==
3082 23:42:25.216947 RX Vref Scan: 0
3083 23:42:25.217001
3084 23:42:25.217055 RX Vref 0 -> 0, step: 1
3085 23:42:25.217109
3086 23:42:25.217165 RX Delay -21 -> 252, step: 4
3087 23:42:25.217219 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3088 23:42:25.217274 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3089 23:42:25.217328 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3090 23:42:25.217382 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3091 23:42:25.217436 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3092 23:42:25.217490 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3093 23:42:25.217544 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3094 23:42:25.217598 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3095 23:42:25.217652 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3096 23:42:25.217707 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3097 23:42:25.217761 iDelay=199, Bit 10, Center 114 (47 ~ 182) 136
3098 23:42:25.217815 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3099 23:42:25.217869 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3100 23:42:25.217923 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3101 23:42:25.217977 iDelay=199, Bit 14, Center 122 (59 ~ 186) 128
3102 23:42:25.218031 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3103 23:42:25.218085 ==
3104 23:42:25.218139 Dram Type= 6, Freq= 0, CH_0, rank 1
3105 23:42:25.218225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3106 23:42:25.218296 ==
3107 23:42:25.218350 DQS Delay:
3108 23:42:25.218405 DQS0 = 0, DQS1 = 0
3109 23:42:25.218459 DQM Delay:
3110 23:42:25.218513 DQM0 = 116, DQM1 = 109
3111 23:42:25.218567 DQ Delay:
3112 23:42:25.218621 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3113 23:42:25.218676 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3114 23:42:25.218730 DQ8 =98, DQ9 =94, DQ10 =114, DQ11 =102
3115 23:42:25.218784 DQ12 =114, DQ13 =114, DQ14 =122, DQ15 =116
3116 23:42:25.218838
3117 23:42:25.218898
3118 23:42:25.218953 [DQSOSCAuto] RK1, (LSB)MR18= 0xfea, (MSB)MR19= 0x403, tDQSOscB0 = 419 ps tDQSOscB1 = 404 ps
3119 23:42:25.219008 CH0 RK1: MR19=403, MR18=FEA
3120 23:42:25.219063 CH0_RK1: MR19=0x403, MR18=0xFEA, DQSOSC=404, MR23=63, INC=40, DEC=26
3121 23:42:25.219118 [RxdqsGatingPostProcess] freq 1200
3122 23:42:25.219171 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3123 23:42:25.219226 best DQS0 dly(2T, 0.5T) = (0, 11)
3124 23:42:25.219280 best DQS1 dly(2T, 0.5T) = (0, 12)
3125 23:42:25.219334 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3126 23:42:25.219387 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3127 23:42:25.219441 best DQS0 dly(2T, 0.5T) = (0, 11)
3128 23:42:25.219495 best DQS1 dly(2T, 0.5T) = (0, 12)
3129 23:42:25.219549 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3130 23:42:25.219602 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3131 23:42:25.219656 Pre-setting of DQS Precalculation
3132 23:42:25.219710 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3133 23:42:25.219763 ==
3134 23:42:25.219817 Dram Type= 6, Freq= 0, CH_1, rank 0
3135 23:42:25.219871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 23:42:25.219925 ==
3137 23:42:25.219979 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3138 23:42:25.220033 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3139 23:42:25.220087 [CA 0] Center 37 (7~67) winsize 61
3140 23:42:25.220141 [CA 1] Center 38 (8~68) winsize 61
3141 23:42:25.220195 [CA 2] Center 34 (4~64) winsize 61
3142 23:42:25.220249 [CA 3] Center 33 (3~64) winsize 62
3143 23:42:25.220303 [CA 4] Center 34 (4~64) winsize 61
3144 23:42:25.220357 [CA 5] Center 33 (3~64) winsize 62
3145 23:42:25.220411
3146 23:42:25.220464 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3147 23:42:25.220519
3148 23:42:25.220580 [CATrainingPosCal] consider 1 rank data
3149 23:42:25.220635 u2DelayCellTimex100 = 270/100 ps
3150 23:42:25.220689 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3151 23:42:25.220790 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3152 23:42:25.220844 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3153 23:42:25.220898 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3154 23:42:25.220952 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 23:42:25.221006 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3156 23:42:25.221059
3157 23:42:25.221113 CA PerBit enable=1, Macro0, CA PI delay=33
3158 23:42:25.221166
3159 23:42:25.221219 [CBTSetCACLKResult] CA Dly = 33
3160 23:42:25.221273 CS Dly: 6 (0~37)
3161 23:42:25.221326 ==
3162 23:42:25.221380 Dram Type= 6, Freq= 0, CH_1, rank 1
3163 23:42:25.221434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3164 23:42:25.221488 ==
3165 23:42:25.221542 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3166 23:42:25.221596 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3167 23:42:25.221650 [CA 0] Center 37 (7~68) winsize 62
3168 23:42:25.221704 [CA 1] Center 38 (8~68) winsize 61
3169 23:42:25.221758 [CA 2] Center 34 (4~65) winsize 62
3170 23:42:25.221812 [CA 3] Center 33 (3~64) winsize 62
3171 23:42:25.222062 [CA 4] Center 34 (4~65) winsize 62
3172 23:42:25.222195 [CA 5] Center 33 (3~64) winsize 62
3173 23:42:25.222323
3174 23:42:25.222433 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3175 23:42:25.222529
3176 23:42:25.222619 [CATrainingPosCal] consider 2 rank data
3177 23:42:25.222700 u2DelayCellTimex100 = 270/100 ps
3178 23:42:25.222756 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3179 23:42:25.222812 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3180 23:42:25.222866 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3181 23:42:25.222921 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3182 23:42:25.222975 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3183 23:42:25.223030 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3184 23:42:25.223083
3185 23:42:25.223137 CA PerBit enable=1, Macro0, CA PI delay=33
3186 23:42:25.223192
3187 23:42:25.223246 [CBTSetCACLKResult] CA Dly = 33
3188 23:42:25.223300 CS Dly: 7 (0~40)
3189 23:42:25.223354
3190 23:42:25.223408 ----->DramcWriteLeveling(PI) begin...
3191 23:42:25.223463 ==
3192 23:42:25.223518 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 23:42:25.223573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 23:42:25.223627 ==
3195 23:42:25.223681 Write leveling (Byte 0): 25 => 25
3196 23:42:25.223735 Write leveling (Byte 1): 27 => 27
3197 23:42:25.223789 DramcWriteLeveling(PI) end<-----
3198 23:42:25.223843
3199 23:42:25.223902 ==
3200 23:42:25.223958 Dram Type= 6, Freq= 0, CH_1, rank 0
3201 23:42:25.224012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3202 23:42:25.224072 ==
3203 23:42:25.224127 [Gating] SW mode calibration
3204 23:42:25.224182 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3205 23:42:25.224237 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3206 23:42:25.224292 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3207 23:42:25.224347 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3208 23:42:25.224401 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 23:42:25.224455 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 23:42:25.224510 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 23:42:25.224563 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 23:42:25.224618 0 15 24 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
3213 23:42:25.224671 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
3214 23:42:25.224725 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 23:42:25.224779 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 23:42:25.224833 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 23:42:25.224887 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 23:42:25.224941 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 23:42:25.224995 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 23:42:25.225048 1 0 24 | B1->B0 | 2424 3535 | 0 1 | (0 0) (0 0)
3221 23:42:25.225102 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3222 23:42:25.225155 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 23:42:25.225209 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 23:42:25.225263 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 23:42:25.225317 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 23:42:25.225371 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 23:42:25.225424 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 23:42:25.225478 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3229 23:42:25.225532 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3230 23:42:25.225586 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 23:42:25.225643 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 23:42:25.225698 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 23:42:25.225757 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 23:42:25.225810 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 23:42:25.225864 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 23:42:25.225918 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 23:42:25.225971 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 23:42:25.226025 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 23:42:25.226079 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 23:42:25.226132 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 23:42:25.226231 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 23:42:25.226288 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 23:42:25.226342 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 23:42:25.226397 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3245 23:42:25.226451 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3246 23:42:25.226505 Total UI for P1: 0, mck2ui 16
3247 23:42:25.226560 best dqsien dly found for B0: ( 1, 3, 24)
3248 23:42:25.226614 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3249 23:42:25.226668 Total UI for P1: 0, mck2ui 16
3250 23:42:25.226722 best dqsien dly found for B1: ( 1, 3, 26)
3251 23:42:25.226777 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3252 23:42:25.226831 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3253 23:42:25.226884
3254 23:42:25.226938 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3255 23:42:25.226993 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3256 23:42:25.227047 [Gating] SW calibration Done
3257 23:42:25.227100 ==
3258 23:42:25.227155 Dram Type= 6, Freq= 0, CH_1, rank 0
3259 23:42:25.227209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 23:42:25.227264 ==
3261 23:42:25.227318 RX Vref Scan: 0
3262 23:42:25.227372
3263 23:42:25.227425 RX Vref 0 -> 0, step: 1
3264 23:42:25.227480
3265 23:42:25.227533 RX Delay -40 -> 252, step: 8
3266 23:42:25.227587 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3267 23:42:25.227642 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3268 23:42:25.227696 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3269 23:42:25.227750 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3270 23:42:25.227803 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3271 23:42:25.227857 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3272 23:42:25.227911 iDelay=208, Bit 6, Center 127 (56 ~ 199) 144
3273 23:42:25.227964 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3274 23:42:25.228018 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3275 23:42:25.228265 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3276 23:42:25.228328 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3277 23:42:25.228383 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3278 23:42:25.228438 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3279 23:42:25.228492 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3280 23:42:25.228545 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3281 23:42:25.228599 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3282 23:42:25.228654 ==
3283 23:42:25.228708 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 23:42:25.228762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 23:42:25.228816 ==
3286 23:42:25.228877 DQS Delay:
3287 23:42:25.228935 DQS0 = 0, DQS1 = 0
3288 23:42:25.228990 DQM Delay:
3289 23:42:25.229043 DQM0 = 118, DQM1 = 108
3290 23:42:25.229098 DQ Delay:
3291 23:42:25.229151 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3292 23:42:25.229237 DQ4 =111, DQ5 =131, DQ6 =127, DQ7 =115
3293 23:42:25.229291 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =95
3294 23:42:25.229345 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3295 23:42:25.229399
3296 23:42:25.229452
3297 23:42:25.229505 ==
3298 23:42:25.229559 Dram Type= 6, Freq= 0, CH_1, rank 0
3299 23:42:25.229613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3300 23:42:25.229667 ==
3301 23:42:25.229720
3302 23:42:25.229774
3303 23:42:25.229828 TX Vref Scan disable
3304 23:42:25.229881 == TX Byte 0 ==
3305 23:42:25.229935 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3306 23:42:25.229989 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3307 23:42:25.230043 == TX Byte 1 ==
3308 23:42:25.230097 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3309 23:42:25.230150 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3310 23:42:25.230216 ==
3311 23:42:25.230271 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 23:42:25.230326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 23:42:25.230381 ==
3314 23:42:25.230434 TX Vref=22, minBit 10, minWin=24, winSum=415
3315 23:42:25.230489 TX Vref=24, minBit 9, minWin=25, winSum=418
3316 23:42:25.230544 TX Vref=26, minBit 9, minWin=25, winSum=425
3317 23:42:25.230598 TX Vref=28, minBit 9, minWin=26, winSum=434
3318 23:42:25.230652 TX Vref=30, minBit 9, minWin=26, winSum=432
3319 23:42:25.230706 TX Vref=32, minBit 8, minWin=25, winSum=423
3320 23:42:25.230761 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 28
3321 23:42:25.230815
3322 23:42:25.230869 Final TX Range 1 Vref 28
3323 23:42:25.230923
3324 23:42:25.230976 ==
3325 23:42:25.231029 Dram Type= 6, Freq= 0, CH_1, rank 0
3326 23:42:25.231083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3327 23:42:25.231138 ==
3328 23:42:25.231191
3329 23:42:25.231245
3330 23:42:25.231315 TX Vref Scan disable
3331 23:42:25.231401 == TX Byte 0 ==
3332 23:42:25.231470 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3333 23:42:25.231523 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3334 23:42:25.231577 == TX Byte 1 ==
3335 23:42:25.231629 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3336 23:42:25.231683 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3337 23:42:25.231735
3338 23:42:25.231788 [DATLAT]
3339 23:42:25.231841 Freq=1200, CH1 RK0
3340 23:42:25.231894
3341 23:42:25.231947 DATLAT Default: 0xd
3342 23:42:25.232000 0, 0xFFFF, sum = 0
3343 23:42:25.232061 1, 0xFFFF, sum = 0
3344 23:42:25.232121 2, 0xFFFF, sum = 0
3345 23:42:25.232176 3, 0xFFFF, sum = 0
3346 23:42:25.232230 4, 0xFFFF, sum = 0
3347 23:42:25.232284 5, 0xFFFF, sum = 0
3348 23:42:25.232338 6, 0xFFFF, sum = 0
3349 23:42:25.232391 7, 0xFFFF, sum = 0
3350 23:42:25.232445 8, 0xFFFF, sum = 0
3351 23:42:25.232499 9, 0xFFFF, sum = 0
3352 23:42:25.232552 10, 0xFFFF, sum = 0
3353 23:42:25.232606 11, 0xFFFF, sum = 0
3354 23:42:25.232660 12, 0x0, sum = 1
3355 23:42:25.232713 13, 0x0, sum = 2
3356 23:42:25.232767 14, 0x0, sum = 3
3357 23:42:25.232820 15, 0x0, sum = 4
3358 23:42:25.232874 best_step = 13
3359 23:42:25.232926
3360 23:42:25.232979 ==
3361 23:42:25.233033 Dram Type= 6, Freq= 0, CH_1, rank 0
3362 23:42:25.233086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3363 23:42:25.233140 ==
3364 23:42:25.233193 RX Vref Scan: 1
3365 23:42:25.233246
3366 23:42:25.233299 Set Vref Range= 32 -> 127
3367 23:42:25.233352
3368 23:42:25.233404 RX Vref 32 -> 127, step: 1
3369 23:42:25.233457
3370 23:42:25.233510 RX Delay -21 -> 252, step: 4
3371 23:42:25.233563
3372 23:42:25.233615 Set Vref, RX VrefLevel [Byte0]: 32
3373 23:42:25.233668 [Byte1]: 32
3374 23:42:25.233721
3375 23:42:25.233773 Set Vref, RX VrefLevel [Byte0]: 33
3376 23:42:25.233828 [Byte1]: 33
3377 23:42:25.233881
3378 23:42:25.233934 Set Vref, RX VrefLevel [Byte0]: 34
3379 23:42:25.233987 [Byte1]: 34
3380 23:42:25.234039
3381 23:42:25.234092 Set Vref, RX VrefLevel [Byte0]: 35
3382 23:42:25.234145 [Byte1]: 35
3383 23:42:25.234209
3384 23:42:25.234262 Set Vref, RX VrefLevel [Byte0]: 36
3385 23:42:25.234316 [Byte1]: 36
3386 23:42:25.234369
3387 23:42:25.234423 Set Vref, RX VrefLevel [Byte0]: 37
3388 23:42:25.234476 [Byte1]: 37
3389 23:42:25.234530
3390 23:42:25.234583 Set Vref, RX VrefLevel [Byte0]: 38
3391 23:42:25.234637 [Byte1]: 38
3392 23:42:25.234690
3393 23:42:25.234742 Set Vref, RX VrefLevel [Byte0]: 39
3394 23:42:25.234796 [Byte1]: 39
3395 23:42:25.234849
3396 23:42:25.234902 Set Vref, RX VrefLevel [Byte0]: 40
3397 23:42:25.234955 [Byte1]: 40
3398 23:42:25.235008
3399 23:42:25.235061 Set Vref, RX VrefLevel [Byte0]: 41
3400 23:42:25.235114 [Byte1]: 41
3401 23:42:25.235166
3402 23:42:25.235220 Set Vref, RX VrefLevel [Byte0]: 42
3403 23:42:25.235273 [Byte1]: 42
3404 23:42:25.235330
3405 23:42:25.235385 Set Vref, RX VrefLevel [Byte0]: 43
3406 23:42:25.235443 [Byte1]: 43
3407 23:42:25.235497
3408 23:42:25.235550 Set Vref, RX VrefLevel [Byte0]: 44
3409 23:42:25.235603 [Byte1]: 44
3410 23:42:25.235656
3411 23:42:25.235709 Set Vref, RX VrefLevel [Byte0]: 45
3412 23:42:25.235762 [Byte1]: 45
3413 23:42:25.235815
3414 23:42:25.235867 Set Vref, RX VrefLevel [Byte0]: 46
3415 23:42:25.235920 [Byte1]: 46
3416 23:42:25.235973
3417 23:42:25.236026 Set Vref, RX VrefLevel [Byte0]: 47
3418 23:42:25.236079 [Byte1]: 47
3419 23:42:25.236133
3420 23:42:25.236185 Set Vref, RX VrefLevel [Byte0]: 48
3421 23:42:25.236238 [Byte1]: 48
3422 23:42:25.236291
3423 23:42:25.236344 Set Vref, RX VrefLevel [Byte0]: 49
3424 23:42:25.236398 [Byte1]: 49
3425 23:42:25.236450
3426 23:42:25.236503 Set Vref, RX VrefLevel [Byte0]: 50
3427 23:42:25.236557 [Byte1]: 50
3428 23:42:25.236610
3429 23:42:25.236663 Set Vref, RX VrefLevel [Byte0]: 51
3430 23:42:25.236716 [Byte1]: 51
3431 23:42:25.236769
3432 23:42:25.236822 Set Vref, RX VrefLevel [Byte0]: 52
3433 23:42:25.236874 [Byte1]: 52
3434 23:42:25.236927
3435 23:42:25.236980 Set Vref, RX VrefLevel [Byte0]: 53
3436 23:42:25.237033 [Byte1]: 53
3437 23:42:25.237086
3438 23:42:25.237333 Set Vref, RX VrefLevel [Byte0]: 54
3439 23:42:25.237395 [Byte1]: 54
3440 23:42:25.237450
3441 23:42:25.237504 Set Vref, RX VrefLevel [Byte0]: 55
3442 23:42:25.237558 [Byte1]: 55
3443 23:42:25.237612
3444 23:42:25.237665 Set Vref, RX VrefLevel [Byte0]: 56
3445 23:42:25.237718 [Byte1]: 56
3446 23:42:25.237772
3447 23:42:25.237825 Set Vref, RX VrefLevel [Byte0]: 57
3448 23:42:25.237878 [Byte1]: 57
3449 23:42:25.237931
3450 23:42:25.237985 Set Vref, RX VrefLevel [Byte0]: 58
3451 23:42:25.238038 [Byte1]: 58
3452 23:42:25.238091
3453 23:42:25.238143 Set Vref, RX VrefLevel [Byte0]: 59
3454 23:42:25.238243 [Byte1]: 59
3455 23:42:25.238298
3456 23:42:25.238352 Set Vref, RX VrefLevel [Byte0]: 60
3457 23:42:25.238404 [Byte1]: 60
3458 23:42:25.238458
3459 23:42:25.238510 Set Vref, RX VrefLevel [Byte0]: 61
3460 23:42:25.238564 [Byte1]: 61
3461 23:42:25.238618
3462 23:42:25.238671 Set Vref, RX VrefLevel [Byte0]: 62
3463 23:42:25.238724 [Byte1]: 62
3464 23:42:25.238779
3465 23:42:25.238836 Set Vref, RX VrefLevel [Byte0]: 63
3466 23:42:25.238895 [Byte1]: 63
3467 23:42:25.238949
3468 23:42:25.239002 Set Vref, RX VrefLevel [Byte0]: 64
3469 23:42:25.239055 [Byte1]: 64
3470 23:42:25.239108
3471 23:42:25.239161 Set Vref, RX VrefLevel [Byte0]: 65
3472 23:42:25.239214 [Byte1]: 65
3473 23:42:25.239267
3474 23:42:25.239320 Set Vref, RX VrefLevel [Byte0]: 66
3475 23:42:25.239374 [Byte1]: 66
3476 23:42:25.239427
3477 23:42:25.239481 Set Vref, RX VrefLevel [Byte0]: 67
3478 23:42:25.239534 [Byte1]: 67
3479 23:42:25.239586
3480 23:42:25.239639 Set Vref, RX VrefLevel [Byte0]: 68
3481 23:42:25.239692 [Byte1]: 68
3482 23:42:25.239745
3483 23:42:25.239798 Set Vref, RX VrefLevel [Byte0]: 69
3484 23:42:25.239851 [Byte1]: 69
3485 23:42:25.239903
3486 23:42:25.239956 Set Vref, RX VrefLevel [Byte0]: 70
3487 23:42:25.240009 [Byte1]: 70
3488 23:42:25.240062
3489 23:42:25.240115 Final RX Vref Byte 0 = 49 to rank0
3490 23:42:25.240168 Final RX Vref Byte 1 = 55 to rank0
3491 23:42:25.240222 Final RX Vref Byte 0 = 49 to rank1
3492 23:42:25.240276 Final RX Vref Byte 1 = 55 to rank1==
3493 23:42:25.240329 Dram Type= 6, Freq= 0, CH_1, rank 0
3494 23:42:25.240382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 23:42:25.240436 ==
3496 23:42:25.240489 DQS Delay:
3497 23:42:25.240542 DQS0 = 0, DQS1 = 0
3498 23:42:25.240595 DQM Delay:
3499 23:42:25.240648 DQM0 = 115, DQM1 = 110
3500 23:42:25.240702 DQ Delay:
3501 23:42:25.240755 DQ0 =118, DQ1 =110, DQ2 =108, DQ3 =110
3502 23:42:25.240809 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =112
3503 23:42:25.240863 DQ8 =98, DQ9 =102, DQ10 =112, DQ11 =100
3504 23:42:25.240917 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3505 23:42:25.240972
3506 23:42:25.241046
3507 23:42:25.241116 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3508 23:42:25.241191 CH1 RK0: MR19=403, MR18=4F7
3509 23:42:25.241264 CH1_RK0: MR19=0x403, MR18=0x4F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3510 23:42:25.241317
3511 23:42:25.241370 ----->DramcWriteLeveling(PI) begin...
3512 23:42:25.241425 ==
3513 23:42:25.241479 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 23:42:25.241532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 23:42:25.241586 ==
3516 23:42:25.241640 Write leveling (Byte 0): 24 => 24
3517 23:42:25.241694 Write leveling (Byte 1): 29 => 29
3518 23:42:25.241747 DramcWriteLeveling(PI) end<-----
3519 23:42:25.241800
3520 23:42:25.241853 ==
3521 23:42:25.241906 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 23:42:25.241960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3523 23:42:25.242015 ==
3524 23:42:25.242102 [Gating] SW mode calibration
3525 23:42:25.242228 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3526 23:42:25.242286 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3527 23:42:25.242340 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3528 23:42:25.242395 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 23:42:25.242449 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3530 23:42:25.242503 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3531 23:42:25.242557 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3532 23:42:25.242610 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3533 23:42:25.242663 0 15 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
3534 23:42:25.242717 0 15 28 | B1->B0 | 2424 2727 | 0 0 | (0 0) (1 0)
3535 23:42:25.242770 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 23:42:25.242824 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 23:42:25.242889 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3538 23:42:25.242983 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3539 23:42:25.243042 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3540 23:42:25.243097 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3541 23:42:25.243177 1 0 24 | B1->B0 | 3332 2929 | 1 1 | (0 0) (0 0)
3542 23:42:25.243244 1 0 28 | B1->B0 | 4646 4242 | 0 1 | (0 0) (0 0)
3543 23:42:25.243298 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 23:42:25.243352 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 23:42:25.243405 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3546 23:42:25.243459 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3547 23:42:25.243512 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3548 23:42:25.243565 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 23:42:25.243619 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 23:42:25.243672 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3551 23:42:25.243726 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 23:42:25.243779 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 23:42:25.243832 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 23:42:25.243885 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 23:42:25.243939 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 23:42:25.243992 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 23:42:25.244045 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 23:42:25.244099 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 23:42:25.244345 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 23:42:25.244405 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 23:42:25.244461 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 23:42:25.244515 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3563 23:42:25.244569 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3564 23:42:25.244623 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3565 23:42:25.244676 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3566 23:42:25.244730 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3567 23:42:25.244784 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3568 23:42:25.244837 Total UI for P1: 0, mck2ui 16
3569 23:42:25.244891 best dqsien dly found for B0: ( 1, 3, 28)
3570 23:42:25.244945 Total UI for P1: 0, mck2ui 16
3571 23:42:25.244998 best dqsien dly found for B1: ( 1, 3, 28)
3572 23:42:25.245052 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3573 23:42:25.245111 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3574 23:42:25.245165
3575 23:42:25.245218 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3576 23:42:25.245272 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3577 23:42:25.245325 [Gating] SW calibration Done
3578 23:42:25.245378 ==
3579 23:42:25.245432 Dram Type= 6, Freq= 0, CH_1, rank 1
3580 23:42:25.245485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3581 23:42:25.245539 ==
3582 23:42:25.245592 RX Vref Scan: 0
3583 23:42:25.245645
3584 23:42:25.245699 RX Vref 0 -> 0, step: 1
3585 23:42:25.245752
3586 23:42:25.245805 RX Delay -40 -> 252, step: 8
3587 23:42:25.245858 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3588 23:42:25.245912 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3589 23:42:25.245965 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3590 23:42:25.246018 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3591 23:42:25.246072 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3592 23:42:25.246125 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3593 23:42:25.246208 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3594 23:42:25.246278 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3595 23:42:25.246332 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3596 23:42:25.246385 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3597 23:42:25.246439 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3598 23:42:25.246493 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3599 23:42:25.246545 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3600 23:42:25.246599 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3601 23:42:25.246652 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3602 23:42:25.246705 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3603 23:42:25.246759 ==
3604 23:42:25.246812 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 23:42:25.246866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 23:42:25.246919 ==
3607 23:42:25.246973 DQS Delay:
3608 23:42:25.247026 DQS0 = 0, DQS1 = 0
3609 23:42:25.247080 DQM Delay:
3610 23:42:25.247133 DQM0 = 116, DQM1 = 110
3611 23:42:25.247187 DQ Delay:
3612 23:42:25.247240 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3613 23:42:25.247294 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3614 23:42:25.247348 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3615 23:42:25.247401 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3616 23:42:25.247455
3617 23:42:25.247508
3618 23:42:25.247561 ==
3619 23:42:25.247615 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 23:42:25.247668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 23:42:25.247722 ==
3622 23:42:25.247775
3623 23:42:25.247846
3624 23:42:25.247945 TX Vref Scan disable
3625 23:42:25.247999 == TX Byte 0 ==
3626 23:42:25.248069 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3627 23:42:25.248137 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3628 23:42:25.248191 == TX Byte 1 ==
3629 23:42:25.248244 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3630 23:42:25.248298 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3631 23:42:25.248351 ==
3632 23:42:25.248404 Dram Type= 6, Freq= 0, CH_1, rank 1
3633 23:42:25.248457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3634 23:42:25.248510 ==
3635 23:42:25.248563 TX Vref=22, minBit 9, minWin=24, winSum=428
3636 23:42:25.248617 TX Vref=24, minBit 9, minWin=25, winSum=428
3637 23:42:25.248671 TX Vref=26, minBit 15, minWin=26, winSum=435
3638 23:42:25.248724 TX Vref=28, minBit 9, minWin=26, winSum=437
3639 23:42:25.248778 TX Vref=30, minBit 8, minWin=26, winSum=434
3640 23:42:25.248831 TX Vref=32, minBit 8, minWin=26, winSum=436
3641 23:42:25.248885 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 28
3642 23:42:25.248938
3643 23:42:25.248992 Final TX Range 1 Vref 28
3644 23:42:25.249045
3645 23:42:25.249098 ==
3646 23:42:25.249151 Dram Type= 6, Freq= 0, CH_1, rank 1
3647 23:42:25.249204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3648 23:42:25.249257 ==
3649 23:42:25.249310
3650 23:42:25.249363
3651 23:42:25.249416 TX Vref Scan disable
3652 23:42:25.249469 == TX Byte 0 ==
3653 23:42:25.249522 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3654 23:42:25.249577 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3655 23:42:25.249630 == TX Byte 1 ==
3656 23:42:25.249686 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3657 23:42:25.249739 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3658 23:42:25.249792
3659 23:42:25.249845 [DATLAT]
3660 23:42:25.249897 Freq=1200, CH1 RK1
3661 23:42:25.249950
3662 23:42:25.250004 DATLAT Default: 0xd
3663 23:42:25.250057 0, 0xFFFF, sum = 0
3664 23:42:25.250112 1, 0xFFFF, sum = 0
3665 23:42:25.250192 2, 0xFFFF, sum = 0
3666 23:42:25.250262 3, 0xFFFF, sum = 0
3667 23:42:25.250316 4, 0xFFFF, sum = 0
3668 23:42:25.250370 5, 0xFFFF, sum = 0
3669 23:42:25.250424 6, 0xFFFF, sum = 0
3670 23:42:25.250478 7, 0xFFFF, sum = 0
3671 23:42:25.250531 8, 0xFFFF, sum = 0
3672 23:42:25.250585 9, 0xFFFF, sum = 0
3673 23:42:25.250639 10, 0xFFFF, sum = 0
3674 23:42:25.250693 11, 0xFFFF, sum = 0
3675 23:42:25.250747 12, 0x0, sum = 1
3676 23:42:25.250801 13, 0x0, sum = 2
3677 23:42:25.250855 14, 0x0, sum = 3
3678 23:42:25.250909 15, 0x0, sum = 4
3679 23:42:25.250963 best_step = 13
3680 23:42:25.251016
3681 23:42:25.251070 ==
3682 23:42:25.251123 Dram Type= 6, Freq= 0, CH_1, rank 1
3683 23:42:25.251177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3684 23:42:25.251231 ==
3685 23:42:25.251284 RX Vref Scan: 0
3686 23:42:25.251337
3687 23:42:25.251390 RX Vref 0 -> 0, step: 1
3688 23:42:25.251443
3689 23:42:25.251496 RX Delay -21 -> 252, step: 4
3690 23:42:25.251549 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3691 23:42:25.251602 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3692 23:42:25.251655 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3693 23:42:25.251709 iDelay=199, Bit 3, Center 114 (51 ~ 178) 128
3694 23:42:25.251761 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3695 23:42:25.251814 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3696 23:42:25.252059 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3697 23:42:25.252120 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3698 23:42:25.252175 iDelay=199, Bit 8, Center 96 (31 ~ 162) 132
3699 23:42:25.252229 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3700 23:42:25.252283 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3701 23:42:25.252336 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3702 23:42:25.252389 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3703 23:42:25.252443 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3704 23:42:25.252496 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3705 23:42:25.252549 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3706 23:42:25.252602 ==
3707 23:42:25.252655 Dram Type= 6, Freq= 0, CH_1, rank 1
3708 23:42:25.252708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3709 23:42:25.252761 ==
3710 23:42:25.252814 DQS Delay:
3711 23:42:25.252867 DQS0 = 0, DQS1 = 0
3712 23:42:25.252920 DQM Delay:
3713 23:42:25.252973 DQM0 = 117, DQM1 = 109
3714 23:42:25.253027 DQ Delay:
3715 23:42:25.253087 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3716 23:42:25.253170 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =116
3717 23:42:25.253227 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =100
3718 23:42:25.253282 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3719 23:42:25.253336
3720 23:42:25.253389
3721 23:42:25.253442 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6f0, (MSB)MR19= 0x303, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
3722 23:42:25.253497 CH1 RK1: MR19=303, MR18=F6F0
3723 23:42:25.253550 CH1_RK1: MR19=0x303, MR18=0xF6F0, DQSOSC=414, MR23=63, INC=38, DEC=25
3724 23:42:25.253604 [RxdqsGatingPostProcess] freq 1200
3725 23:42:25.253657 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3726 23:42:25.253711 best DQS0 dly(2T, 0.5T) = (0, 11)
3727 23:42:25.253764 best DQS1 dly(2T, 0.5T) = (0, 11)
3728 23:42:25.253818 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3729 23:42:25.253871 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3730 23:42:25.253924 best DQS0 dly(2T, 0.5T) = (0, 11)
3731 23:42:25.253978 best DQS1 dly(2T, 0.5T) = (0, 11)
3732 23:42:25.254031 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3733 23:42:25.254084 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3734 23:42:25.254137 Pre-setting of DQS Precalculation
3735 23:42:25.254240 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3736 23:42:25.254296 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3737 23:42:25.254351 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3738 23:42:25.254405
3739 23:42:25.254457
3740 23:42:25.254510 [Calibration Summary] 2400 Mbps
3741 23:42:25.254563 CH 0, Rank 0
3742 23:42:25.254617 SW Impedance : PASS
3743 23:42:25.254670 DUTY Scan : NO K
3744 23:42:25.254724 ZQ Calibration : PASS
3745 23:42:25.254776 Jitter Meter : NO K
3746 23:42:25.254829 CBT Training : PASS
3747 23:42:25.254882 Write leveling : PASS
3748 23:42:25.254935 RX DQS gating : PASS
3749 23:42:25.254987 RX DQ/DQS(RDDQC) : PASS
3750 23:42:25.255040 TX DQ/DQS : PASS
3751 23:42:25.255094 RX DATLAT : PASS
3752 23:42:25.255147 RX DQ/DQS(Engine): PASS
3753 23:42:25.255199 TX OE : NO K
3754 23:42:25.255252 All Pass.
3755 23:42:25.255306
3756 23:42:25.255359 CH 0, Rank 1
3757 23:42:25.255412 SW Impedance : PASS
3758 23:42:25.255465 DUTY Scan : NO K
3759 23:42:25.255519 ZQ Calibration : PASS
3760 23:42:25.255572 Jitter Meter : NO K
3761 23:42:25.255625 CBT Training : PASS
3762 23:42:25.255677 Write leveling : PASS
3763 23:42:25.255731 RX DQS gating : PASS
3764 23:42:25.255784 RX DQ/DQS(RDDQC) : PASS
3765 23:42:25.255838 TX DQ/DQS : PASS
3766 23:42:25.255890 RX DATLAT : PASS
3767 23:42:25.255944 RX DQ/DQS(Engine): PASS
3768 23:42:25.255997 TX OE : NO K
3769 23:42:25.256050 All Pass.
3770 23:42:25.256103
3771 23:42:25.256156 CH 1, Rank 0
3772 23:42:25.256209 SW Impedance : PASS
3773 23:42:25.256262 DUTY Scan : NO K
3774 23:42:25.256315 ZQ Calibration : PASS
3775 23:42:25.256369 Jitter Meter : NO K
3776 23:42:25.256422 CBT Training : PASS
3777 23:42:25.256476 Write leveling : PASS
3778 23:42:25.256529 RX DQS gating : PASS
3779 23:42:25.256582 RX DQ/DQS(RDDQC) : PASS
3780 23:42:25.256636 TX DQ/DQS : PASS
3781 23:42:25.256689 RX DATLAT : PASS
3782 23:42:25.256742 RX DQ/DQS(Engine): PASS
3783 23:42:25.256795 TX OE : NO K
3784 23:42:25.256848 All Pass.
3785 23:42:25.256901
3786 23:42:25.256954 CH 1, Rank 1
3787 23:42:25.257007 SW Impedance : PASS
3788 23:42:25.257095 DUTY Scan : NO K
3789 23:42:25.257154 ZQ Calibration : PASS
3790 23:42:25.257208 Jitter Meter : NO K
3791 23:42:25.257262 CBT Training : PASS
3792 23:42:25.257317 Write leveling : PASS
3793 23:42:25.257370 RX DQS gating : PASS
3794 23:42:25.257423 RX DQ/DQS(RDDQC) : PASS
3795 23:42:25.257477 TX DQ/DQS : PASS
3796 23:42:25.257530 RX DATLAT : PASS
3797 23:42:25.257584 RX DQ/DQS(Engine): PASS
3798 23:42:25.257636 TX OE : NO K
3799 23:42:25.257690 All Pass.
3800 23:42:25.257743
3801 23:42:25.257796 DramC Write-DBI off
3802 23:42:25.257850 PER_BANK_REFRESH: Hybrid Mode
3803 23:42:25.257904 TX_TRACKING: ON
3804 23:42:25.257958 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3805 23:42:25.258012 [FAST_K] Save calibration result to emmc
3806 23:42:25.258065 dramc_set_vcore_voltage set vcore to 650000
3807 23:42:25.258119 Read voltage for 600, 5
3808 23:42:25.258220 Vio18 = 0
3809 23:42:25.258274 Vcore = 650000
3810 23:42:25.258327 Vdram = 0
3811 23:42:25.258381 Vddq = 0
3812 23:42:25.258433 Vmddr = 0
3813 23:42:25.258487 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3814 23:42:25.258541 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3815 23:42:25.258594 MEM_TYPE=3, freq_sel=19
3816 23:42:25.258648 sv_algorithm_assistance_LP4_1600
3817 23:42:25.258702 ============ PULL DRAM RESETB DOWN ============
3818 23:42:25.258755 ========== PULL DRAM RESETB DOWN end =========
3819 23:42:25.258810 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3820 23:42:25.258864 ===================================
3821 23:42:25.258917 LPDDR4 DRAM CONFIGURATION
3822 23:42:25.258970 ===================================
3823 23:42:25.259024 EX_ROW_EN[0] = 0x0
3824 23:42:25.259077 EX_ROW_EN[1] = 0x0
3825 23:42:25.259130 LP4Y_EN = 0x0
3826 23:42:25.259183 WORK_FSP = 0x0
3827 23:42:25.259236 WL = 0x2
3828 23:42:25.259289 RL = 0x2
3829 23:42:25.259342 BL = 0x2
3830 23:42:25.259415 RPST = 0x0
3831 23:42:25.259502 RD_PRE = 0x0
3832 23:42:25.259570 WR_PRE = 0x1
3833 23:42:25.259623 WR_PST = 0x0
3834 23:42:25.259676 DBI_WR = 0x0
3835 23:42:25.259729 DBI_RD = 0x0
3836 23:42:25.259782 OTF = 0x1
3837 23:42:25.259835 ===================================
3838 23:42:25.260082 ===================================
3839 23:42:25.260142 ANA top config
3840 23:42:25.260198 ===================================
3841 23:42:25.260251 DLL_ASYNC_EN = 0
3842 23:42:25.260305 ALL_SLAVE_EN = 1
3843 23:42:25.260359 NEW_RANK_MODE = 1
3844 23:42:25.260414 DLL_IDLE_MODE = 1
3845 23:42:25.260468 LP45_APHY_COMB_EN = 1
3846 23:42:25.260521 TX_ODT_DIS = 1
3847 23:42:25.260575 NEW_8X_MODE = 1
3848 23:42:25.260629 ===================================
3849 23:42:25.260682 ===================================
3850 23:42:25.260736 data_rate = 1200
3851 23:42:25.260790 CKR = 1
3852 23:42:25.260844 DQ_P2S_RATIO = 8
3853 23:42:25.260897 ===================================
3854 23:42:25.260951 CA_P2S_RATIO = 8
3855 23:42:25.261004 DQ_CA_OPEN = 0
3856 23:42:25.261058 DQ_SEMI_OPEN = 0
3857 23:42:25.261111 CA_SEMI_OPEN = 0
3858 23:42:25.261163 CA_FULL_RATE = 0
3859 23:42:25.261217 DQ_CKDIV4_EN = 1
3860 23:42:25.261271 CA_CKDIV4_EN = 1
3861 23:42:25.261324 CA_PREDIV_EN = 0
3862 23:42:25.261378 PH8_DLY = 0
3863 23:42:25.261432 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3864 23:42:25.261485 DQ_AAMCK_DIV = 4
3865 23:42:25.261538 CA_AAMCK_DIV = 4
3866 23:42:25.261591 CA_ADMCK_DIV = 4
3867 23:42:25.261645 DQ_TRACK_CA_EN = 0
3868 23:42:25.261698 CA_PICK = 600
3869 23:42:25.261751 CA_MCKIO = 600
3870 23:42:25.261804 MCKIO_SEMI = 0
3871 23:42:25.261858 PLL_FREQ = 2288
3872 23:42:25.261911 DQ_UI_PI_RATIO = 32
3873 23:42:25.261964 CA_UI_PI_RATIO = 0
3874 23:42:25.262017 ===================================
3875 23:42:25.262071 ===================================
3876 23:42:25.262124 memory_type:LPDDR4
3877 23:42:25.262218 GP_NUM : 10
3878 23:42:25.262274 SRAM_EN : 1
3879 23:42:25.262327 MD32_EN : 0
3880 23:42:25.262380 ===================================
3881 23:42:25.262434 [ANA_INIT] >>>>>>>>>>>>>>
3882 23:42:25.262487 <<<<<< [CONFIGURE PHASE]: ANA_TX
3883 23:42:25.262542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3884 23:42:25.262595 ===================================
3885 23:42:25.262649 data_rate = 1200,PCW = 0X5800
3886 23:42:25.262702 ===================================
3887 23:42:25.262756 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3888 23:42:25.262810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3889 23:42:25.262863 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3890 23:42:25.262917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3891 23:42:25.262970 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3892 23:42:25.263024 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3893 23:42:25.263077 [ANA_INIT] flow start
3894 23:42:25.263130 [ANA_INIT] PLL >>>>>>>>
3895 23:42:25.263184 [ANA_INIT] PLL <<<<<<<<
3896 23:42:25.263236 [ANA_INIT] MIDPI >>>>>>>>
3897 23:42:25.263289 [ANA_INIT] MIDPI <<<<<<<<
3898 23:42:25.263342 [ANA_INIT] DLL >>>>>>>>
3899 23:42:25.263396 [ANA_INIT] flow end
3900 23:42:25.263449 ============ LP4 DIFF to SE enter ============
3901 23:42:25.263503 ============ LP4 DIFF to SE exit ============
3902 23:42:25.263557 [ANA_INIT] <<<<<<<<<<<<<
3903 23:42:25.263610 [Flow] Enable top DCM control >>>>>
3904 23:42:25.263663 [Flow] Enable top DCM control <<<<<
3905 23:42:25.263716 Enable DLL master slave shuffle
3906 23:42:25.263769 ==============================================================
3907 23:42:25.263823 Gating Mode config
3908 23:42:25.263876 ==============================================================
3909 23:42:25.263929 Config description:
3910 23:42:25.263983 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3911 23:42:25.264037 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3912 23:42:25.264091 SELPH_MODE 0: By rank 1: By Phase
3913 23:42:25.264145 ==============================================================
3914 23:42:25.264199 GAT_TRACK_EN = 1
3915 23:42:25.264253 RX_GATING_MODE = 2
3916 23:42:25.264306 RX_GATING_TRACK_MODE = 2
3917 23:42:25.264359 SELPH_MODE = 1
3918 23:42:25.264412 PICG_EARLY_EN = 1
3919 23:42:25.264465 VALID_LAT_VALUE = 1
3920 23:42:25.264519 ==============================================================
3921 23:42:25.264573 Enter into Gating configuration >>>>
3922 23:42:25.264626 Exit from Gating configuration <<<<
3923 23:42:25.264680 Enter into DVFS_PRE_config >>>>>
3924 23:42:25.264734 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3925 23:42:25.264788 Exit from DVFS_PRE_config <<<<<
3926 23:42:25.264842 Enter into PICG configuration >>>>
3927 23:42:25.264895 Exit from PICG configuration <<<<
3928 23:42:25.264948 [RX_INPUT] configuration >>>>>
3929 23:42:25.265001 [RX_INPUT] configuration <<<<<
3930 23:42:25.265071 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3931 23:42:25.268322 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3932 23:42:25.274651 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3933 23:42:25.278120 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3934 23:42:25.284677 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3935 23:42:25.291282 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3936 23:42:25.294659 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3937 23:42:25.301485 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3938 23:42:25.304857 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3939 23:42:25.308121 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3940 23:42:25.311566 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3941 23:42:25.317786 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3942 23:42:25.321315 ===================================
3943 23:42:25.321399 LPDDR4 DRAM CONFIGURATION
3944 23:42:25.324582 ===================================
3945 23:42:25.327889 EX_ROW_EN[0] = 0x0
3946 23:42:25.331186 EX_ROW_EN[1] = 0x0
3947 23:42:25.331268 LP4Y_EN = 0x0
3948 23:42:25.334540 WORK_FSP = 0x0
3949 23:42:25.334622 WL = 0x2
3950 23:42:25.337845 RL = 0x2
3951 23:42:25.338011 BL = 0x2
3952 23:42:25.341118 RPST = 0x0
3953 23:42:25.341243 RD_PRE = 0x0
3954 23:42:25.344371 WR_PRE = 0x1
3955 23:42:25.344466 WR_PST = 0x0
3956 23:42:25.347547 DBI_WR = 0x0
3957 23:42:25.347650 DBI_RD = 0x0
3958 23:42:25.350813 OTF = 0x1
3959 23:42:25.354584 ===================================
3960 23:42:25.357428 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3961 23:42:25.360888 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3962 23:42:25.367418 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3963 23:42:25.370641 ===================================
3964 23:42:25.370781 LPDDR4 DRAM CONFIGURATION
3965 23:42:25.374231 ===================================
3966 23:42:25.377497 EX_ROW_EN[0] = 0x10
3967 23:42:25.380555 EX_ROW_EN[1] = 0x0
3968 23:42:25.380736 LP4Y_EN = 0x0
3969 23:42:25.383674 WORK_FSP = 0x0
3970 23:42:25.383858 WL = 0x2
3971 23:42:25.387409 RL = 0x2
3972 23:42:25.387606 BL = 0x2
3973 23:42:25.396723 RPST = 0x0
3974 23:42:25.396956 RD_PRE = 0x0
3975 23:42:25.397153 WR_PRE = 0x1
3976 23:42:25.397368 WR_PST = 0x0
3977 23:42:25.397552 DBI_WR = 0x0
3978 23:42:25.397706 DBI_RD = 0x0
3979 23:42:25.400254 OTF = 0x1
3980 23:42:25.403470 ===================================
3981 23:42:25.410336 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3982 23:42:25.413386 nWR fixed to 30
3983 23:42:25.416695 [ModeRegInit_LP4] CH0 RK0
3984 23:42:25.416961 [ModeRegInit_LP4] CH0 RK1
3985 23:42:25.420134 [ModeRegInit_LP4] CH1 RK0
3986 23:42:25.423301 [ModeRegInit_LP4] CH1 RK1
3987 23:42:25.423582 match AC timing 17
3988 23:42:25.430207 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3989 23:42:25.433420 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3990 23:42:25.436439 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3991 23:42:25.442987 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3992 23:42:25.446317 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3993 23:42:25.446401 ==
3994 23:42:25.449620 Dram Type= 6, Freq= 0, CH_0, rank 0
3995 23:42:25.452712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3996 23:42:25.452823 ==
3997 23:42:25.459643 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3998 23:42:25.466580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3999 23:42:25.469831 [CA 0] Center 36 (6~66) winsize 61
4000 23:42:25.472595 [CA 1] Center 36 (6~66) winsize 61
4001 23:42:25.476306 [CA 2] Center 34 (3~65) winsize 63
4002 23:42:25.479846 [CA 3] Center 34 (4~65) winsize 62
4003 23:42:25.482500 [CA 4] Center 33 (3~64) winsize 62
4004 23:42:25.485970 [CA 5] Center 33 (3~64) winsize 62
4005 23:42:25.486053
4006 23:42:25.489383 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4007 23:42:25.489467
4008 23:42:25.493182 [CATrainingPosCal] consider 1 rank data
4009 23:42:25.496250 u2DelayCellTimex100 = 270/100 ps
4010 23:42:25.499088 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4011 23:42:25.502206 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4012 23:42:25.505888 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
4013 23:42:25.512931 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4014 23:42:25.516465 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4015 23:42:25.519399 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4016 23:42:25.519832
4017 23:42:25.522785 CA PerBit enable=1, Macro0, CA PI delay=33
4018 23:42:25.523215
4019 23:42:25.526116 [CBTSetCACLKResult] CA Dly = 33
4020 23:42:25.526706 CS Dly: 6 (0~37)
4021 23:42:25.527060 ==
4022 23:42:25.529378 Dram Type= 6, Freq= 0, CH_0, rank 1
4023 23:42:25.536053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 23:42:25.536487 ==
4025 23:42:25.538956 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4026 23:42:25.545719 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4027 23:42:25.549076 [CA 0] Center 35 (5~66) winsize 62
4028 23:42:25.552275 [CA 1] Center 36 (6~66) winsize 61
4029 23:42:25.555707 [CA 2] Center 34 (4~65) winsize 62
4030 23:42:25.559325 [CA 3] Center 33 (3~64) winsize 62
4031 23:42:25.562229 [CA 4] Center 33 (2~64) winsize 63
4032 23:42:25.565441 [CA 5] Center 33 (2~64) winsize 63
4033 23:42:25.565881
4034 23:42:25.568773 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4035 23:42:25.569208
4036 23:42:25.572277 [CATrainingPosCal] consider 2 rank data
4037 23:42:25.575221 u2DelayCellTimex100 = 270/100 ps
4038 23:42:25.578501 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4039 23:42:25.585238 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4040 23:42:25.588538 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4041 23:42:25.591593 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4042 23:42:25.594759 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4043 23:42:25.598649 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4044 23:42:25.599078
4045 23:42:25.602027 CA PerBit enable=1, Macro0, CA PI delay=33
4046 23:42:25.602513
4047 23:42:25.605054 [CBTSetCACLKResult] CA Dly = 33
4048 23:42:25.608437 CS Dly: 6 (0~37)
4049 23:42:25.608863
4050 23:42:25.611574 ----->DramcWriteLeveling(PI) begin...
4051 23:42:25.612008 ==
4052 23:42:25.614538 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 23:42:25.618034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 23:42:25.618518 ==
4055 23:42:25.621494 Write leveling (Byte 0): 31 => 31
4056 23:42:25.624690 Write leveling (Byte 1): 30 => 30
4057 23:42:25.627855 DramcWriteLeveling(PI) end<-----
4058 23:42:25.628289
4059 23:42:25.628629 ==
4060 23:42:25.631316 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 23:42:25.634438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 23:42:25.634876 ==
4063 23:42:25.638122 [Gating] SW mode calibration
4064 23:42:25.644120 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4065 23:42:25.650596 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4066 23:42:25.654349 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4067 23:42:25.676597 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4068 23:42:25.676744 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4069 23:42:25.676814 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
4070 23:42:25.676877 0 9 16 | B1->B0 | 3131 2b2b | 0 0 | (0 0) (1 1)
4071 23:42:25.677137 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 23:42:25.680454 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 23:42:25.687154 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 23:42:25.690132 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4075 23:42:25.693877 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4076 23:42:25.700097 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4077 23:42:25.703633 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4078 23:42:25.706910 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4079 23:42:25.713078 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 23:42:25.716656 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 23:42:25.719739 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 23:42:25.726383 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 23:42:25.730149 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4084 23:42:25.732873 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 23:42:25.739824 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 23:42:25.742704 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 23:42:25.746133 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 23:42:25.753140 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 23:42:25.756118 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 23:42:25.759519 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 23:42:25.765926 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 23:42:25.769173 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 23:42:25.772149 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 23:42:25.778912 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 23:42:25.782248 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 23:42:25.785550 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 23:42:25.792015 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 23:42:25.795297 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 23:42:25.798959 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4100 23:42:25.805391 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4101 23:42:25.808997 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4102 23:42:25.812358 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 23:42:25.815609 Total UI for P1: 0, mck2ui 16
4104 23:42:25.818983 best dqsien dly found for B0: ( 0, 13, 12)
4105 23:42:25.822391 Total UI for P1: 0, mck2ui 16
4106 23:42:25.825911 best dqsien dly found for B1: ( 0, 13, 12)
4107 23:42:25.829043 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4108 23:42:25.832570 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4109 23:42:25.832998
4110 23:42:25.838848 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4111 23:42:25.842085 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4112 23:42:25.842549 [Gating] SW calibration Done
4113 23:42:25.845353 ==
4114 23:42:25.848401 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 23:42:25.851968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 23:42:25.852395 ==
4117 23:42:25.852737 RX Vref Scan: 0
4118 23:42:25.853097
4119 23:42:25.855262 RX Vref 0 -> 0, step: 1
4120 23:42:25.855689
4121 23:42:25.858250 RX Delay -230 -> 252, step: 16
4122 23:42:25.861553 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4123 23:42:25.865298 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4124 23:42:25.871602 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4125 23:42:25.874904 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4126 23:42:25.878543 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4127 23:42:25.881685 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4128 23:42:25.888290 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4129 23:42:25.891387 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4130 23:42:25.894546 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4131 23:42:25.897903 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4132 23:42:25.901450 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4133 23:42:25.907939 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4134 23:42:25.911377 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4135 23:42:25.914916 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4136 23:42:25.918314 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4137 23:42:25.924554 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4138 23:42:25.924978 ==
4139 23:42:25.928276 Dram Type= 6, Freq= 0, CH_0, rank 0
4140 23:42:25.931048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4141 23:42:25.931477 ==
4142 23:42:25.931813 DQS Delay:
4143 23:42:25.934388 DQS0 = 0, DQS1 = 0
4144 23:42:25.934810 DQM Delay:
4145 23:42:25.937709 DQM0 = 41, DQM1 = 29
4146 23:42:25.938134 DQ Delay:
4147 23:42:25.941363 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4148 23:42:25.944333 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4149 23:42:25.947407 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4150 23:42:25.950748 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4151 23:42:25.951173
4152 23:42:25.951510
4153 23:42:25.951822 ==
4154 23:42:25.954433 Dram Type= 6, Freq= 0, CH_0, rank 0
4155 23:42:25.960607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4156 23:42:25.961169 ==
4157 23:42:25.961662
4158 23:42:25.962125
4159 23:42:25.962636 TX Vref Scan disable
4160 23:42:25.964039 == TX Byte 0 ==
4161 23:42:25.967377 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4162 23:42:25.974155 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4163 23:42:25.974761 == TX Byte 1 ==
4164 23:42:25.977340 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4165 23:42:25.984304 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4166 23:42:25.984729 ==
4167 23:42:25.987269 Dram Type= 6, Freq= 0, CH_0, rank 0
4168 23:42:25.990717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4169 23:42:25.991143 ==
4170 23:42:25.991481
4171 23:42:25.991793
4172 23:42:25.993650 TX Vref Scan disable
4173 23:42:25.997249 == TX Byte 0 ==
4174 23:42:26.000599 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4175 23:42:26.003749 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4176 23:42:26.007291 == TX Byte 1 ==
4177 23:42:26.010601 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4178 23:42:26.013914 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4179 23:42:26.014510
4180 23:42:26.014956 [DATLAT]
4181 23:42:26.017310 Freq=600, CH0 RK0
4182 23:42:26.017817
4183 23:42:26.020140 DATLAT Default: 0x9
4184 23:42:26.020572 0, 0xFFFF, sum = 0
4185 23:42:26.023840 1, 0xFFFF, sum = 0
4186 23:42:26.024283 2, 0xFFFF, sum = 0
4187 23:42:26.026763 3, 0xFFFF, sum = 0
4188 23:42:26.027222 4, 0xFFFF, sum = 0
4189 23:42:26.030749 5, 0xFFFF, sum = 0
4190 23:42:26.031193 6, 0xFFFF, sum = 0
4191 23:42:26.033473 7, 0xFFFF, sum = 0
4192 23:42:26.033915 8, 0x0, sum = 1
4193 23:42:26.036884 9, 0x0, sum = 2
4194 23:42:26.037327 10, 0x0, sum = 3
4195 23:42:26.040728 11, 0x0, sum = 4
4196 23:42:26.041171 best_step = 9
4197 23:42:26.041610
4198 23:42:26.042022 ==
4199 23:42:26.043686 Dram Type= 6, Freq= 0, CH_0, rank 0
4200 23:42:26.046797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4201 23:42:26.046882 ==
4202 23:42:26.049947 RX Vref Scan: 1
4203 23:42:26.050032
4204 23:42:26.053193 RX Vref 0 -> 0, step: 1
4205 23:42:26.053277
4206 23:42:26.053362 RX Delay -195 -> 252, step: 8
4207 23:42:26.056660
4208 23:42:26.056752 Set Vref, RX VrefLevel [Byte0]: 59
4209 23:42:26.059703 [Byte1]: 58
4210 23:42:26.064444
4211 23:42:26.064541 Final RX Vref Byte 0 = 59 to rank0
4212 23:42:26.068127 Final RX Vref Byte 1 = 58 to rank0
4213 23:42:26.071263 Final RX Vref Byte 0 = 59 to rank1
4214 23:42:26.074336 Final RX Vref Byte 1 = 58 to rank1==
4215 23:42:26.077438 Dram Type= 6, Freq= 0, CH_0, rank 0
4216 23:42:26.083991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 23:42:26.084077 ==
4218 23:42:26.084163 DQS Delay:
4219 23:42:26.088280 DQS0 = 0, DQS1 = 0
4220 23:42:26.088716 DQM Delay:
4221 23:42:26.089155 DQM0 = 43, DQM1 = 33
4222 23:42:26.091498 DQ Delay:
4223 23:42:26.094705 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4224 23:42:26.097499 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =48
4225 23:42:26.101114 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4226 23:42:26.104242 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4227 23:42:26.104721
4228 23:42:26.105225
4229 23:42:26.110596 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a41, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 389 ps
4230 23:42:26.114250 CH0 RK0: MR19=808, MR18=6A41
4231 23:42:26.120849 CH0_RK0: MR19=0x808, MR18=0x6A41, DQSOSC=389, MR23=63, INC=173, DEC=115
4232 23:42:26.121286
4233 23:42:26.124163 ----->DramcWriteLeveling(PI) begin...
4234 23:42:26.124604 ==
4235 23:42:26.127219 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 23:42:26.130612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 23:42:26.131050 ==
4238 23:42:26.133679 Write leveling (Byte 0): 33 => 33
4239 23:42:26.137248 Write leveling (Byte 1): 33 => 33
4240 23:42:26.140198 DramcWriteLeveling(PI) end<-----
4241 23:42:26.140633
4242 23:42:26.141072 ==
4243 23:42:26.143524 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 23:42:26.146974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 23:42:26.150453 ==
4246 23:42:26.150943 [Gating] SW mode calibration
4247 23:42:26.160394 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4248 23:42:26.163602 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4249 23:42:26.166949 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4250 23:42:26.173696 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4251 23:42:26.176836 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4252 23:42:26.180476 0 9 12 | B1->B0 | 3434 3232 | 0 0 | (1 1) (0 0)
4253 23:42:26.186646 0 9 16 | B1->B0 | 2f2f 2b2b | 0 0 | (1 1) (0 0)
4254 23:42:26.190131 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 23:42:26.193194 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4256 23:42:26.199807 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 23:42:26.203360 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 23:42:26.206925 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4259 23:42:26.213400 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4260 23:42:26.216478 0 10 12 | B1->B0 | 2424 2424 | 1 0 | (0 0) (0 0)
4261 23:42:26.219898 0 10 16 | B1->B0 | 3939 3d3d | 0 1 | (0 0) (0 0)
4262 23:42:26.226451 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 23:42:26.229775 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 23:42:26.233236 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 23:42:26.240073 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 23:42:26.242769 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 23:42:26.246672 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4268 23:42:26.252711 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4269 23:42:26.256026 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4270 23:42:26.260074 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 23:42:26.266214 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 23:42:26.269386 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 23:42:26.272671 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 23:42:26.279392 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 23:42:26.282683 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 23:42:26.285894 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 23:42:26.292202 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 23:42:26.295777 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 23:42:26.299651 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 23:42:26.305595 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 23:42:26.308895 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 23:42:26.312229 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4283 23:42:26.318606 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4284 23:42:26.322098 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4285 23:42:26.325531 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4286 23:42:26.328597 Total UI for P1: 0, mck2ui 16
4287 23:42:26.332249 best dqsien dly found for B0: ( 0, 13, 14)
4288 23:42:26.335356 Total UI for P1: 0, mck2ui 16
4289 23:42:26.338576 best dqsien dly found for B1: ( 0, 13, 14)
4290 23:42:26.342101 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4291 23:42:26.345290 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4292 23:42:26.345717
4293 23:42:26.351617 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4294 23:42:26.354990 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4295 23:42:26.358624 [Gating] SW calibration Done
4296 23:42:26.359186 ==
4297 23:42:26.361475 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 23:42:26.365011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 23:42:26.365443 ==
4300 23:42:26.365783 RX Vref Scan: 0
4301 23:42:26.366099
4302 23:42:26.368287 RX Vref 0 -> 0, step: 1
4303 23:42:26.368709
4304 23:42:26.371735 RX Delay -230 -> 252, step: 16
4305 23:42:26.374942 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4306 23:42:26.381244 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4307 23:42:26.384934 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4308 23:42:26.387967 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4309 23:42:26.391469 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4310 23:42:26.394610 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4311 23:42:26.401299 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4312 23:42:26.404592 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4313 23:42:26.407668 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4314 23:42:26.411075 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4315 23:42:26.417702 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4316 23:42:26.420922 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4317 23:42:26.424197 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4318 23:42:26.427666 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4319 23:42:26.434319 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4320 23:42:26.437829 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4321 23:42:26.438286 ==
4322 23:42:26.441220 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 23:42:26.444250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 23:42:26.444677 ==
4325 23:42:26.447200 DQS Delay:
4326 23:42:26.447658 DQS0 = 0, DQS1 = 0
4327 23:42:26.450565 DQM Delay:
4328 23:42:26.450986 DQM0 = 42, DQM1 = 35
4329 23:42:26.451325 DQ Delay:
4330 23:42:26.454062 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =41
4331 23:42:26.457566 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4332 23:42:26.460908 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4333 23:42:26.463703 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4334 23:42:26.464125
4335 23:42:26.464460
4336 23:42:26.467320 ==
4337 23:42:26.467742 Dram Type= 6, Freq= 0, CH_0, rank 1
4338 23:42:26.473622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 23:42:26.474052 ==
4340 23:42:26.474436
4341 23:42:26.474828
4342 23:42:26.476739 TX Vref Scan disable
4343 23:42:26.477040 == TX Byte 0 ==
4344 23:42:26.483109 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4345 23:42:26.486428 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4346 23:42:26.486611 == TX Byte 1 ==
4347 23:42:26.493181 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4348 23:42:26.496241 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4349 23:42:26.496424 ==
4350 23:42:26.499521 Dram Type= 6, Freq= 0, CH_0, rank 1
4351 23:42:26.503062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 23:42:26.503246 ==
4353 23:42:26.503391
4354 23:42:26.503527
4355 23:42:26.506087 TX Vref Scan disable
4356 23:42:26.509410 == TX Byte 0 ==
4357 23:42:26.512724 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4358 23:42:26.515882 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4359 23:42:26.519071 == TX Byte 1 ==
4360 23:42:26.522510 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4361 23:42:26.526068 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4362 23:42:26.529403
4363 23:42:26.529485 [DATLAT]
4364 23:42:26.529550 Freq=600, CH0 RK1
4365 23:42:26.529612
4366 23:42:26.532337 DATLAT Default: 0x9
4367 23:42:26.532419 0, 0xFFFF, sum = 0
4368 23:42:26.535450 1, 0xFFFF, sum = 0
4369 23:42:26.535533 2, 0xFFFF, sum = 0
4370 23:42:26.539249 3, 0xFFFF, sum = 0
4371 23:42:26.539333 4, 0xFFFF, sum = 0
4372 23:42:26.542358 5, 0xFFFF, sum = 0
4373 23:42:26.545548 6, 0xFFFF, sum = 0
4374 23:42:26.545633 7, 0xFFFF, sum = 0
4375 23:42:26.548912 8, 0x0, sum = 1
4376 23:42:26.548995 9, 0x0, sum = 2
4377 23:42:26.549062 10, 0x0, sum = 3
4378 23:42:26.552461 11, 0x0, sum = 4
4379 23:42:26.552545 best_step = 9
4380 23:42:26.552610
4381 23:42:26.552669 ==
4382 23:42:26.555387 Dram Type= 6, Freq= 0, CH_0, rank 1
4383 23:42:26.561910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4384 23:42:26.562020 ==
4385 23:42:26.562114 RX Vref Scan: 0
4386 23:42:26.562235
4387 23:42:26.565369 RX Vref 0 -> 0, step: 1
4388 23:42:26.565451
4389 23:42:26.568623 RX Delay -195 -> 252, step: 8
4390 23:42:26.572051 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4391 23:42:26.578369 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4392 23:42:26.581521 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4393 23:42:26.585142 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4394 23:42:26.588419 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4395 23:42:26.595336 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4396 23:42:26.598432 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4397 23:42:26.601747 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4398 23:42:26.604832 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4399 23:42:26.611302 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4400 23:42:26.615039 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4401 23:42:26.617902 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4402 23:42:26.621246 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4403 23:42:26.628189 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4404 23:42:26.631326 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4405 23:42:26.634730 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4406 23:42:26.634813 ==
4407 23:42:26.638088 Dram Type= 6, Freq= 0, CH_0, rank 1
4408 23:42:26.641449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 23:42:26.641532 ==
4410 23:42:26.644863 DQS Delay:
4411 23:42:26.644945 DQS0 = 0, DQS1 = 0
4412 23:42:26.648072 DQM Delay:
4413 23:42:26.648155 DQM0 = 42, DQM1 = 37
4414 23:42:26.648220 DQ Delay:
4415 23:42:26.651106 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4416 23:42:26.654353 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4417 23:42:26.657753 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =28
4418 23:42:26.660928 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4419 23:42:26.661011
4420 23:42:26.661078
4421 23:42:26.670773 [DQSOSCAuto] RK1, (LSB)MR18= 0x6114, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 391 ps
4422 23:42:26.674408 CH0 RK1: MR19=808, MR18=6114
4423 23:42:26.680733 CH0_RK1: MR19=0x808, MR18=0x6114, DQSOSC=391, MR23=63, INC=171, DEC=114
4424 23:42:26.684122 [RxdqsGatingPostProcess] freq 600
4425 23:42:26.687434 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4426 23:42:26.690669 Pre-setting of DQS Precalculation
4427 23:42:26.697531 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4428 23:42:26.697615 ==
4429 23:42:26.700429 Dram Type= 6, Freq= 0, CH_1, rank 0
4430 23:42:26.703864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4431 23:42:26.703948 ==
4432 23:42:26.710458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4433 23:42:26.713421 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4434 23:42:26.717875 [CA 0] Center 35 (5~66) winsize 62
4435 23:42:26.721292 [CA 1] Center 36 (6~66) winsize 61
4436 23:42:26.724808 [CA 2] Center 34 (4~65) winsize 62
4437 23:42:26.728106 [CA 3] Center 33 (3~64) winsize 62
4438 23:42:26.731003 [CA 4] Center 34 (4~65) winsize 62
4439 23:42:26.734196 [CA 5] Center 33 (3~64) winsize 62
4440 23:42:26.734279
4441 23:42:26.737699 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4442 23:42:26.737782
4443 23:42:26.740896 [CATrainingPosCal] consider 1 rank data
4444 23:42:26.744053 u2DelayCellTimex100 = 270/100 ps
4445 23:42:26.747742 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4446 23:42:26.754442 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4447 23:42:26.757684 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4448 23:42:26.760772 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4449 23:42:26.764064 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4450 23:42:26.767621 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4451 23:42:26.767704
4452 23:42:26.770898 CA PerBit enable=1, Macro0, CA PI delay=33
4453 23:42:26.770981
4454 23:42:26.773922 [CBTSetCACLKResult] CA Dly = 33
4455 23:42:26.777635 CS Dly: 5 (0~36)
4456 23:42:26.777718 ==
4457 23:42:26.780606 Dram Type= 6, Freq= 0, CH_1, rank 1
4458 23:42:26.784141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 23:42:26.784217 ==
4460 23:42:26.790856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4461 23:42:26.793990 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4462 23:42:26.797989 [CA 0] Center 36 (6~66) winsize 61
4463 23:42:26.801625 [CA 1] Center 36 (6~66) winsize 61
4464 23:42:26.804901 [CA 2] Center 34 (4~65) winsize 62
4465 23:42:26.808234 [CA 3] Center 34 (3~65) winsize 63
4466 23:42:26.811604 [CA 4] Center 34 (4~65) winsize 62
4467 23:42:26.814839 [CA 5] Center 33 (3~64) winsize 62
4468 23:42:26.814922
4469 23:42:26.817774 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4470 23:42:26.817858
4471 23:42:26.821374 [CATrainingPosCal] consider 2 rank data
4472 23:42:26.824252 u2DelayCellTimex100 = 270/100 ps
4473 23:42:26.827797 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4474 23:42:26.834036 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4475 23:42:26.837960 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4476 23:42:26.840663 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4477 23:42:26.844130 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4478 23:42:26.847406 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4479 23:42:26.847489
4480 23:42:26.850968 CA PerBit enable=1, Macro0, CA PI delay=33
4481 23:42:26.851051
4482 23:42:26.854090 [CBTSetCACLKResult] CA Dly = 33
4483 23:42:26.857011 CS Dly: 5 (0~36)
4484 23:42:26.857137
4485 23:42:26.860328 ----->DramcWriteLeveling(PI) begin...
4486 23:42:26.860412 ==
4487 23:42:26.864011 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 23:42:26.867187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 23:42:26.867271 ==
4490 23:42:26.870520 Write leveling (Byte 0): 29 => 29
4491 23:42:26.873487 Write leveling (Byte 1): 29 => 29
4492 23:42:26.877130 DramcWriteLeveling(PI) end<-----
4493 23:42:26.877214
4494 23:42:26.877279 ==
4495 23:42:26.879977 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 23:42:26.883752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 23:42:26.883842 ==
4498 23:42:26.886842 [Gating] SW mode calibration
4499 23:42:26.893392 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4500 23:42:26.900011 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4501 23:42:26.903259 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4502 23:42:26.906569 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4503 23:42:26.912999 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4504 23:42:26.916284 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (1 0)
4505 23:42:26.922642 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 23:42:26.926029 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 23:42:26.929248 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4508 23:42:26.936388 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4509 23:42:26.939219 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 23:42:26.942646 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4511 23:42:26.949467 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4512 23:42:26.952447 0 10 12 | B1->B0 | 3030 3c3c | 0 0 | (0 0) (0 0)
4513 23:42:26.956037 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4514 23:42:26.962590 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 23:42:26.965817 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 23:42:26.969150 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 23:42:26.976341 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 23:42:26.979446 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 23:42:26.982778 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 23:42:26.989445 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 23:42:26.992792 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 23:42:26.996098 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 23:42:26.999424 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 23:42:27.005587 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 23:42:27.009337 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 23:42:27.012490 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 23:42:27.018911 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 23:42:27.022220 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 23:42:27.028658 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 23:42:27.032036 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 23:42:27.035337 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 23:42:27.042144 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 23:42:27.045667 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 23:42:27.048864 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 23:42:27.055001 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4536 23:42:27.058276 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4537 23:42:27.061528 Total UI for P1: 0, mck2ui 16
4538 23:42:27.064849 best dqsien dly found for B0: ( 0, 13, 10)
4539 23:42:27.068206 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 23:42:27.071944 Total UI for P1: 0, mck2ui 16
4541 23:42:27.074739 best dqsien dly found for B1: ( 0, 13, 14)
4542 23:42:27.078018 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4543 23:42:27.081342 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4544 23:42:27.081767
4545 23:42:27.087874 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4546 23:42:27.091144 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4547 23:42:27.094577 [Gating] SW calibration Done
4548 23:42:27.095003 ==
4549 23:42:27.097709 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 23:42:27.101330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 23:42:27.101801 ==
4552 23:42:27.102143 RX Vref Scan: 0
4553 23:42:27.102514
4554 23:42:27.104546 RX Vref 0 -> 0, step: 1
4555 23:42:27.105032
4556 23:42:27.107991 RX Delay -230 -> 252, step: 16
4557 23:42:27.111036 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4558 23:42:27.114637 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4559 23:42:27.120850 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4560 23:42:27.124058 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4561 23:42:27.127205 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4562 23:42:27.130747 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4563 23:42:27.137425 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4564 23:42:27.140652 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4565 23:42:27.143842 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4566 23:42:27.147669 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4567 23:42:27.154103 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4568 23:42:27.156977 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4569 23:42:27.160796 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4570 23:42:27.163150 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4571 23:42:27.170393 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4572 23:42:27.172991 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4573 23:42:27.173074 ==
4574 23:42:27.176869 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 23:42:27.179973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 23:42:27.180057 ==
4577 23:42:27.182971 DQS Delay:
4578 23:42:27.183053 DQS0 = 0, DQS1 = 0
4579 23:42:27.183119 DQM Delay:
4580 23:42:27.186286 DQM0 = 46, DQM1 = 37
4581 23:42:27.186369 DQ Delay:
4582 23:42:27.190291 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4583 23:42:27.192884 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4584 23:42:27.196771 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4585 23:42:27.199426 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4586 23:42:27.199538
4587 23:42:27.199614
4588 23:42:27.199685 ==
4589 23:42:27.202684 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 23:42:27.209528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 23:42:27.209613 ==
4592 23:42:27.209679
4593 23:42:27.209741
4594 23:42:27.209825 TX Vref Scan disable
4595 23:42:27.213354 == TX Byte 0 ==
4596 23:42:27.216617 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4597 23:42:27.223122 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4598 23:42:27.223241 == TX Byte 1 ==
4599 23:42:27.226422 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4600 23:42:27.233363 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4601 23:42:27.233447 ==
4602 23:42:27.236124 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 23:42:27.239551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 23:42:27.239634 ==
4605 23:42:27.239700
4606 23:42:27.239760
4607 23:42:27.242863 TX Vref Scan disable
4608 23:42:27.246503 == TX Byte 0 ==
4609 23:42:27.249754 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4610 23:42:27.253380 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4611 23:42:27.256801 == TX Byte 1 ==
4612 23:42:27.259810 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4613 23:42:27.262940 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4614 23:42:27.263375
4615 23:42:27.263718 [DATLAT]
4616 23:42:27.266410 Freq=600, CH1 RK0
4617 23:42:27.266838
4618 23:42:27.269490 DATLAT Default: 0x9
4619 23:42:27.269913 0, 0xFFFF, sum = 0
4620 23:42:27.273186 1, 0xFFFF, sum = 0
4621 23:42:27.273616 2, 0xFFFF, sum = 0
4622 23:42:27.276167 3, 0xFFFF, sum = 0
4623 23:42:27.276603 4, 0xFFFF, sum = 0
4624 23:42:27.279584 5, 0xFFFF, sum = 0
4625 23:42:27.280017 6, 0xFFFF, sum = 0
4626 23:42:27.283397 7, 0xFFFF, sum = 0
4627 23:42:27.283826 8, 0x0, sum = 1
4628 23:42:27.286681 9, 0x0, sum = 2
4629 23:42:27.287116 10, 0x0, sum = 3
4630 23:42:27.289446 11, 0x0, sum = 4
4631 23:42:27.289893 best_step = 9
4632 23:42:27.290280
4633 23:42:27.290606 ==
4634 23:42:27.292737 Dram Type= 6, Freq= 0, CH_1, rank 0
4635 23:42:27.296009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 23:42:27.296463 ==
4637 23:42:27.299221 RX Vref Scan: 1
4638 23:42:27.299655
4639 23:42:27.302679 RX Vref 0 -> 0, step: 1
4640 23:42:27.303103
4641 23:42:27.303438 RX Delay -195 -> 252, step: 8
4642 23:42:27.305646
4643 23:42:27.306066 Set Vref, RX VrefLevel [Byte0]: 49
4644 23:42:27.309159 [Byte1]: 55
4645 23:42:27.314542
4646 23:42:27.315084 Final RX Vref Byte 0 = 49 to rank0
4647 23:42:27.317648 Final RX Vref Byte 1 = 55 to rank0
4648 23:42:27.320314 Final RX Vref Byte 0 = 49 to rank1
4649 23:42:27.323988 Final RX Vref Byte 1 = 55 to rank1==
4650 23:42:27.327371 Dram Type= 6, Freq= 0, CH_1, rank 0
4651 23:42:27.334116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 23:42:27.334592 ==
4653 23:42:27.334935 DQS Delay:
4654 23:42:27.335250 DQS0 = 0, DQS1 = 0
4655 23:42:27.337299 DQM Delay:
4656 23:42:27.337719 DQM0 = 48, DQM1 = 37
4657 23:42:27.340597 DQ Delay:
4658 23:42:27.344193 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4659 23:42:27.347413 DQ4 =44, DQ5 =60, DQ6 =56, DQ7 =44
4660 23:42:27.350307 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4661 23:42:27.353844 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =48
4662 23:42:27.354413
4663 23:42:27.354760
4664 23:42:27.360779 [DQSOSCAuto] RK0, (LSB)MR18= 0x4e33, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4665 23:42:27.363984 CH1 RK0: MR19=808, MR18=4E33
4666 23:42:27.370262 CH1_RK0: MR19=0x808, MR18=0x4E33, DQSOSC=395, MR23=63, INC=168, DEC=112
4667 23:42:27.370694
4668 23:42:27.374014 ----->DramcWriteLeveling(PI) begin...
4669 23:42:27.374480 ==
4670 23:42:27.376806 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 23:42:27.380324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 23:42:27.380760 ==
4673 23:42:27.383826 Write leveling (Byte 0): 29 => 29
4674 23:42:27.387317 Write leveling (Byte 1): 30 => 30
4675 23:42:27.390289 DramcWriteLeveling(PI) end<-----
4676 23:42:27.390724
4677 23:42:27.391133 ==
4678 23:42:27.393487 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 23:42:27.396821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 23:42:27.397386 ==
4681 23:42:27.399755 [Gating] SW mode calibration
4682 23:42:27.406666 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4683 23:42:27.413540 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4684 23:42:27.416645 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4685 23:42:27.423415 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4686 23:42:27.426599 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4687 23:42:27.430357 0 9 12 | B1->B0 | 3030 3232 | 1 0 | (1 0) (0 0)
4688 23:42:27.436419 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4689 23:42:27.439864 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 23:42:27.442921 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4691 23:42:27.449437 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4692 23:42:27.452772 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 23:42:27.456284 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4694 23:42:27.462926 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4695 23:42:27.466211 0 10 12 | B1->B0 | 3737 2828 | 0 0 | (0 0) (0 0)
4696 23:42:27.469410 0 10 16 | B1->B0 | 4545 3f3f | 0 0 | (0 0) (0 0)
4697 23:42:27.476115 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 23:42:27.479039 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 23:42:27.482318 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 23:42:27.489307 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 23:42:27.492745 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 23:42:27.496118 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 23:42:27.502447 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4704 23:42:27.505733 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 23:42:27.509151 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 23:42:27.515318 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 23:42:27.519102 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 23:42:27.522664 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 23:42:27.528828 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 23:42:27.531670 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 23:42:27.534957 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 23:42:27.541248 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 23:42:27.544705 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 23:42:27.548201 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 23:42:27.554815 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 23:42:27.558170 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 23:42:27.561344 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 23:42:27.567996 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 23:42:27.571270 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4720 23:42:27.574753 Total UI for P1: 0, mck2ui 16
4721 23:42:27.577998 best dqsien dly found for B1: ( 0, 13, 10)
4722 23:42:27.581009 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 23:42:27.584700 Total UI for P1: 0, mck2ui 16
4724 23:42:27.588276 best dqsien dly found for B0: ( 0, 13, 12)
4725 23:42:27.591408 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4726 23:42:27.594554 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4727 23:42:27.594782
4728 23:42:27.601063 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4729 23:42:27.604663 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4730 23:42:27.607839 [Gating] SW calibration Done
4731 23:42:27.608388 ==
4732 23:42:27.611489 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 23:42:27.614280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 23:42:27.614874 ==
4735 23:42:27.615375 RX Vref Scan: 0
4736 23:42:27.617773
4737 23:42:27.618318 RX Vref 0 -> 0, step: 1
4738 23:42:27.618682
4739 23:42:27.620867 RX Delay -230 -> 252, step: 16
4740 23:42:27.624359 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4741 23:42:27.630904 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4742 23:42:27.634203 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4743 23:42:27.637440 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4744 23:42:27.640888 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4745 23:42:27.644059 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4746 23:42:27.650395 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4747 23:42:27.654077 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4748 23:42:27.657368 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4749 23:42:27.660298 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4750 23:42:27.667131 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4751 23:42:27.670227 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4752 23:42:27.673574 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4753 23:42:27.676808 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4754 23:42:27.683596 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4755 23:42:27.686879 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4756 23:42:27.687486 ==
4757 23:42:27.689891 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 23:42:27.693039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 23:42:27.693621 ==
4760 23:42:27.696526 DQS Delay:
4761 23:42:27.697123 DQS0 = 0, DQS1 = 0
4762 23:42:27.697646 DQM Delay:
4763 23:42:27.699993 DQM0 = 44, DQM1 = 38
4764 23:42:27.700573 DQ Delay:
4765 23:42:27.703915 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4766 23:42:27.706985 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4767 23:42:27.710303 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4768 23:42:27.713060 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4769 23:42:27.713606
4770 23:42:27.714197
4771 23:42:27.714780 ==
4772 23:42:27.716325 Dram Type= 6, Freq= 0, CH_1, rank 1
4773 23:42:27.723471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4774 23:42:27.724027 ==
4775 23:42:27.724549
4776 23:42:27.725036
4777 23:42:27.725484 TX Vref Scan disable
4778 23:42:27.727279 == TX Byte 0 ==
4779 23:42:27.730563 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4780 23:42:27.736880 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4781 23:42:27.737415 == TX Byte 1 ==
4782 23:42:27.740352 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4783 23:42:27.746763 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4784 23:42:27.747311 ==
4785 23:42:27.750253 Dram Type= 6, Freq= 0, CH_1, rank 1
4786 23:42:27.753565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4787 23:42:27.754133 ==
4788 23:42:27.754682
4789 23:42:27.755211
4790 23:42:27.756541 TX Vref Scan disable
4791 23:42:27.760127 == TX Byte 0 ==
4792 23:42:27.763255 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4793 23:42:27.766256 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4794 23:42:27.769914 == TX Byte 1 ==
4795 23:42:27.772716 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4796 23:42:27.776235 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4797 23:42:27.776822
4798 23:42:27.777335 [DATLAT]
4799 23:42:27.779708 Freq=600, CH1 RK1
4800 23:42:27.780180
4801 23:42:27.782819 DATLAT Default: 0x9
4802 23:42:27.783250 0, 0xFFFF, sum = 0
4803 23:42:27.786278 1, 0xFFFF, sum = 0
4804 23:42:27.786709 2, 0xFFFF, sum = 0
4805 23:42:27.789541 3, 0xFFFF, sum = 0
4806 23:42:27.789970 4, 0xFFFF, sum = 0
4807 23:42:27.792659 5, 0xFFFF, sum = 0
4808 23:42:27.793300 6, 0xFFFF, sum = 0
4809 23:42:27.795945 7, 0xFFFF, sum = 0
4810 23:42:27.796376 8, 0x0, sum = 1
4811 23:42:27.799384 9, 0x0, sum = 2
4812 23:42:27.799815 10, 0x0, sum = 3
4813 23:42:27.802460 11, 0x0, sum = 4
4814 23:42:27.802892 best_step = 9
4815 23:42:27.803231
4816 23:42:27.803683 ==
4817 23:42:27.805720 Dram Type= 6, Freq= 0, CH_1, rank 1
4818 23:42:27.809263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4819 23:42:27.812233 ==
4820 23:42:27.812659 RX Vref Scan: 0
4821 23:42:27.812998
4822 23:42:27.816111 RX Vref 0 -> 0, step: 1
4823 23:42:27.816613
4824 23:42:27.819191 RX Delay -195 -> 252, step: 8
4825 23:42:27.822349 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4826 23:42:27.825824 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4827 23:42:27.832186 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4828 23:42:27.835718 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4829 23:42:27.838354 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4830 23:42:27.842019 iDelay=213, Bit 5, Center 60 (-83 ~ 204) 288
4831 23:42:27.848544 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4832 23:42:27.851939 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4833 23:42:27.854615 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4834 23:42:27.858213 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4835 23:42:27.861630 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4836 23:42:27.868024 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4837 23:42:27.871269 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4838 23:42:27.874983 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4839 23:42:27.878111 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4840 23:42:27.884656 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4841 23:42:27.884742 ==
4842 23:42:27.887893 Dram Type= 6, Freq= 0, CH_1, rank 1
4843 23:42:27.891366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4844 23:42:27.891479 ==
4845 23:42:27.891575 DQS Delay:
4846 23:42:27.894771 DQS0 = 0, DQS1 = 0
4847 23:42:27.894871 DQM Delay:
4848 23:42:27.898153 DQM0 = 46, DQM1 = 35
4849 23:42:27.898294 DQ Delay:
4850 23:42:27.900927 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4851 23:42:27.904302 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =44
4852 23:42:27.907621 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4853 23:42:27.911084 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =48
4854 23:42:27.911196
4855 23:42:27.911291
4856 23:42:27.920966 [DQSOSCAuto] RK1, (LSB)MR18= 0x3126, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
4857 23:42:27.921078 CH1 RK1: MR19=808, MR18=3126
4858 23:42:27.927261 CH1_RK1: MR19=0x808, MR18=0x3126, DQSOSC=400, MR23=63, INC=163, DEC=109
4859 23:42:27.930658 [RxdqsGatingPostProcess] freq 600
4860 23:42:27.937275 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4861 23:42:27.940852 Pre-setting of DQS Precalculation
4862 23:42:27.944025 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4863 23:42:27.954115 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4864 23:42:27.960520 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4865 23:42:27.960690
4866 23:42:27.960837
4867 23:42:27.963937 [Calibration Summary] 1200 Mbps
4868 23:42:27.964071 CH 0, Rank 0
4869 23:42:27.966918 SW Impedance : PASS
4870 23:42:27.967032 DUTY Scan : NO K
4871 23:42:27.970400 ZQ Calibration : PASS
4872 23:42:27.974037 Jitter Meter : NO K
4873 23:42:27.974144 CBT Training : PASS
4874 23:42:27.976761 Write leveling : PASS
4875 23:42:27.980197 RX DQS gating : PASS
4876 23:42:27.980310 RX DQ/DQS(RDDQC) : PASS
4877 23:42:27.983703 TX DQ/DQS : PASS
4878 23:42:27.987042 RX DATLAT : PASS
4879 23:42:27.987148 RX DQ/DQS(Engine): PASS
4880 23:42:27.990425 TX OE : NO K
4881 23:42:27.990534 All Pass.
4882 23:42:27.990629
4883 23:42:27.993763 CH 0, Rank 1
4884 23:42:27.993865 SW Impedance : PASS
4885 23:42:27.996672 DUTY Scan : NO K
4886 23:42:27.999837 ZQ Calibration : PASS
4887 23:42:27.999952 Jitter Meter : NO K
4888 23:42:28.003182 CBT Training : PASS
4889 23:42:28.003289 Write leveling : PASS
4890 23:42:28.006995 RX DQS gating : PASS
4891 23:42:28.010329 RX DQ/DQS(RDDQC) : PASS
4892 23:42:28.010441 TX DQ/DQS : PASS
4893 23:42:28.013318 RX DATLAT : PASS
4894 23:42:28.016421 RX DQ/DQS(Engine): PASS
4895 23:42:28.016525 TX OE : NO K
4896 23:42:28.019521 All Pass.
4897 23:42:28.019628
4898 23:42:28.019725 CH 1, Rank 0
4899 23:42:28.022851 SW Impedance : PASS
4900 23:42:28.022963 DUTY Scan : NO K
4901 23:42:28.026435 ZQ Calibration : PASS
4902 23:42:28.029768 Jitter Meter : NO K
4903 23:42:28.029913 CBT Training : PASS
4904 23:42:28.032889 Write leveling : PASS
4905 23:42:28.036397 RX DQS gating : PASS
4906 23:42:28.036507 RX DQ/DQS(RDDQC) : PASS
4907 23:42:28.039870 TX DQ/DQS : PASS
4908 23:42:28.042818 RX DATLAT : PASS
4909 23:42:28.042930 RX DQ/DQS(Engine): PASS
4910 23:42:28.046433 TX OE : NO K
4911 23:42:28.046541 All Pass.
4912 23:42:28.046636
4913 23:42:28.049719 CH 1, Rank 1
4914 23:42:28.049793 SW Impedance : PASS
4915 23:42:28.053039 DUTY Scan : NO K
4916 23:42:28.056221 ZQ Calibration : PASS
4917 23:42:28.056329 Jitter Meter : NO K
4918 23:42:28.059719 CBT Training : PASS
4919 23:42:28.062794 Write leveling : PASS
4920 23:42:28.062910 RX DQS gating : PASS
4921 23:42:28.066328 RX DQ/DQS(RDDQC) : PASS
4922 23:42:28.069403 TX DQ/DQS : PASS
4923 23:42:28.069494 RX DATLAT : PASS
4924 23:42:28.072712 RX DQ/DQS(Engine): PASS
4925 23:42:28.072816 TX OE : NO K
4926 23:42:28.075780 All Pass.
4927 23:42:28.075881
4928 23:42:28.075973 DramC Write-DBI off
4929 23:42:28.079167 PER_BANK_REFRESH: Hybrid Mode
4930 23:42:28.082796 TX_TRACKING: ON
4931 23:42:28.089290 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4932 23:42:28.092618 [FAST_K] Save calibration result to emmc
4933 23:42:28.099025 dramc_set_vcore_voltage set vcore to 662500
4934 23:42:28.099138 Read voltage for 933, 3
4935 23:42:28.099239 Vio18 = 0
4936 23:42:28.102691 Vcore = 662500
4937 23:42:28.102800 Vdram = 0
4938 23:42:28.102896 Vddq = 0
4939 23:42:28.105621 Vmddr = 0
4940 23:42:28.108925 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4941 23:42:28.115604 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4942 23:42:28.115698 MEM_TYPE=3, freq_sel=17
4943 23:42:28.119027 sv_algorithm_assistance_LP4_1600
4944 23:42:28.125650 ============ PULL DRAM RESETB DOWN ============
4945 23:42:28.129122 ========== PULL DRAM RESETB DOWN end =========
4946 23:42:28.132125 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4947 23:42:28.135536 ===================================
4948 23:42:28.138968 LPDDR4 DRAM CONFIGURATION
4949 23:42:28.142198 ===================================
4950 23:42:28.145477 EX_ROW_EN[0] = 0x0
4951 23:42:28.145562 EX_ROW_EN[1] = 0x0
4952 23:42:28.148754 LP4Y_EN = 0x0
4953 23:42:28.148838 WORK_FSP = 0x0
4954 23:42:28.152450 WL = 0x3
4955 23:42:28.152532 RL = 0x3
4956 23:42:28.155074 BL = 0x2
4957 23:42:28.155157 RPST = 0x0
4958 23:42:28.158884 RD_PRE = 0x0
4959 23:42:28.159031 WR_PRE = 0x1
4960 23:42:28.161803 WR_PST = 0x0
4961 23:42:28.161912 DBI_WR = 0x0
4962 23:42:28.165012 DBI_RD = 0x0
4963 23:42:28.168311 OTF = 0x1
4964 23:42:28.171883 ===================================
4965 23:42:28.174986 ===================================
4966 23:42:28.175105 ANA top config
4967 23:42:28.178430 ===================================
4968 23:42:28.181788 DLL_ASYNC_EN = 0
4969 23:42:28.181900 ALL_SLAVE_EN = 1
4970 23:42:28.184673 NEW_RANK_MODE = 1
4971 23:42:28.188181 DLL_IDLE_MODE = 1
4972 23:42:28.191653 LP45_APHY_COMB_EN = 1
4973 23:42:28.194558 TX_ODT_DIS = 1
4974 23:42:28.194664 NEW_8X_MODE = 1
4975 23:42:28.197908 ===================================
4976 23:42:28.201570 ===================================
4977 23:42:28.204853 data_rate = 1866
4978 23:42:28.208075 CKR = 1
4979 23:42:28.210975 DQ_P2S_RATIO = 8
4980 23:42:28.214526 ===================================
4981 23:42:28.218056 CA_P2S_RATIO = 8
4982 23:42:28.221093 DQ_CA_OPEN = 0
4983 23:42:28.221223 DQ_SEMI_OPEN = 0
4984 23:42:28.224395 CA_SEMI_OPEN = 0
4985 23:42:28.228041 CA_FULL_RATE = 0
4986 23:42:28.230832 DQ_CKDIV4_EN = 1
4987 23:42:28.234404 CA_CKDIV4_EN = 1
4988 23:42:28.237752 CA_PREDIV_EN = 0
4989 23:42:28.241170 PH8_DLY = 0
4990 23:42:28.241275 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4991 23:42:28.244621 DQ_AAMCK_DIV = 4
4992 23:42:28.247844 CA_AAMCK_DIV = 4
4993 23:42:28.250763 CA_ADMCK_DIV = 4
4994 23:42:28.253948 DQ_TRACK_CA_EN = 0
4995 23:42:28.257351 CA_PICK = 933
4996 23:42:28.257448 CA_MCKIO = 933
4997 23:42:28.260833 MCKIO_SEMI = 0
4998 23:42:28.264297 PLL_FREQ = 3732
4999 23:42:28.267214 DQ_UI_PI_RATIO = 32
5000 23:42:28.270720 CA_UI_PI_RATIO = 0
5001 23:42:28.274230 ===================================
5002 23:42:28.277316 ===================================
5003 23:42:28.280701 memory_type:LPDDR4
5004 23:42:28.280812 GP_NUM : 10
5005 23:42:28.284142 SRAM_EN : 1
5006 23:42:28.284225 MD32_EN : 0
5007 23:42:28.286913 ===================================
5008 23:42:28.290322 [ANA_INIT] >>>>>>>>>>>>>>
5009 23:42:28.293954 <<<<<< [CONFIGURE PHASE]: ANA_TX
5010 23:42:28.296984 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5011 23:42:28.300461 ===================================
5012 23:42:28.303635 data_rate = 1866,PCW = 0X8f00
5013 23:42:28.306943 ===================================
5014 23:42:28.310147 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5015 23:42:28.316699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5016 23:42:28.320068 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5017 23:42:28.327298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5018 23:42:28.330004 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5019 23:42:28.333244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5020 23:42:28.333347 [ANA_INIT] flow start
5021 23:42:28.336714 [ANA_INIT] PLL >>>>>>>>
5022 23:42:28.340203 [ANA_INIT] PLL <<<<<<<<
5023 23:42:28.340312 [ANA_INIT] MIDPI >>>>>>>>
5024 23:42:28.343415 [ANA_INIT] MIDPI <<<<<<<<
5025 23:42:28.347345 [ANA_INIT] DLL >>>>>>>>
5026 23:42:28.347432 [ANA_INIT] flow end
5027 23:42:28.353445 ============ LP4 DIFF to SE enter ============
5028 23:42:28.356468 ============ LP4 DIFF to SE exit ============
5029 23:42:28.360077 [ANA_INIT] <<<<<<<<<<<<<
5030 23:42:28.363135 [Flow] Enable top DCM control >>>>>
5031 23:42:28.366384 [Flow] Enable top DCM control <<<<<
5032 23:42:28.370042 Enable DLL master slave shuffle
5033 23:42:28.373061 ==============================================================
5034 23:42:28.376765 Gating Mode config
5035 23:42:28.379571 ==============================================================
5036 23:42:28.383055 Config description:
5037 23:42:28.392455 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5038 23:42:28.399323 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5039 23:42:28.402973 SELPH_MODE 0: By rank 1: By Phase
5040 23:42:28.409460 ==============================================================
5041 23:42:28.412447 GAT_TRACK_EN = 1
5042 23:42:28.416035 RX_GATING_MODE = 2
5043 23:42:28.419058 RX_GATING_TRACK_MODE = 2
5044 23:42:28.422765 SELPH_MODE = 1
5045 23:42:28.426195 PICG_EARLY_EN = 1
5046 23:42:28.428920 VALID_LAT_VALUE = 1
5047 23:42:28.432439 ==============================================================
5048 23:42:28.435516 Enter into Gating configuration >>>>
5049 23:42:28.439152 Exit from Gating configuration <<<<
5050 23:42:28.442109 Enter into DVFS_PRE_config >>>>>
5051 23:42:28.455122 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5052 23:42:28.458700 Exit from DVFS_PRE_config <<<<<
5053 23:42:28.458783 Enter into PICG configuration >>>>
5054 23:42:28.462050 Exit from PICG configuration <<<<
5055 23:42:28.465129 [RX_INPUT] configuration >>>>>
5056 23:42:28.468675 [RX_INPUT] configuration <<<<<
5057 23:42:28.475449 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5058 23:42:28.478649 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5059 23:42:28.485187 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5060 23:42:28.491594 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5061 23:42:28.498365 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5062 23:42:28.505331 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5063 23:42:28.508495 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5064 23:42:28.511632 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5065 23:42:28.514798 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5066 23:42:28.521491 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5067 23:42:28.524525 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5068 23:42:28.528344 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5069 23:42:28.531350 ===================================
5070 23:42:28.534592 LPDDR4 DRAM CONFIGURATION
5071 23:42:28.537945 ===================================
5072 23:42:28.541263 EX_ROW_EN[0] = 0x0
5073 23:42:28.541346 EX_ROW_EN[1] = 0x0
5074 23:42:28.544888 LP4Y_EN = 0x0
5075 23:42:28.544970 WORK_FSP = 0x0
5076 23:42:28.547729 WL = 0x3
5077 23:42:28.547811 RL = 0x3
5078 23:42:28.551161 BL = 0x2
5079 23:42:28.551250 RPST = 0x0
5080 23:42:28.554879 RD_PRE = 0x0
5081 23:42:28.554963 WR_PRE = 0x1
5082 23:42:28.557560 WR_PST = 0x0
5083 23:42:28.557642 DBI_WR = 0x0
5084 23:42:28.560982 DBI_RD = 0x0
5085 23:42:28.564652 OTF = 0x1
5086 23:42:28.567890 ===================================
5087 23:42:28.570922 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5088 23:42:28.574313 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5089 23:42:28.577291 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5090 23:42:28.580737 ===================================
5091 23:42:28.584562 LPDDR4 DRAM CONFIGURATION
5092 23:42:28.587810 ===================================
5093 23:42:28.590604 EX_ROW_EN[0] = 0x10
5094 23:42:28.590687 EX_ROW_EN[1] = 0x0
5095 23:42:28.594081 LP4Y_EN = 0x0
5096 23:42:28.594208 WORK_FSP = 0x0
5097 23:42:28.597903 WL = 0x3
5098 23:42:28.597985 RL = 0x3
5099 23:42:28.600591 BL = 0x2
5100 23:42:28.600674 RPST = 0x0
5101 23:42:28.604234 RD_PRE = 0x0
5102 23:42:28.604317 WR_PRE = 0x1
5103 23:42:28.607004 WR_PST = 0x0
5104 23:42:28.607115 DBI_WR = 0x0
5105 23:42:28.610435 DBI_RD = 0x0
5106 23:42:28.613977 OTF = 0x1
5107 23:42:28.617112 ===================================
5108 23:42:28.620484 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5109 23:42:28.625665 nWR fixed to 30
5110 23:42:28.628738 [ModeRegInit_LP4] CH0 RK0
5111 23:42:28.628825 [ModeRegInit_LP4] CH0 RK1
5112 23:42:28.632169 [ModeRegInit_LP4] CH1 RK0
5113 23:42:28.635495 [ModeRegInit_LP4] CH1 RK1
5114 23:42:28.635578 match AC timing 9
5115 23:42:28.642122 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5116 23:42:28.645514 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5117 23:42:28.648658 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5118 23:42:28.655176 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5119 23:42:28.658450 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5120 23:42:28.658533 ==
5121 23:42:28.661756 Dram Type= 6, Freq= 0, CH_0, rank 0
5122 23:42:28.665544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5123 23:42:28.665628 ==
5124 23:42:28.671907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5125 23:42:28.678467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5126 23:42:28.681320 [CA 0] Center 37 (7~68) winsize 62
5127 23:42:28.684541 [CA 1] Center 37 (7~68) winsize 62
5128 23:42:28.688356 [CA 2] Center 34 (4~65) winsize 62
5129 23:42:28.691263 [CA 3] Center 35 (5~65) winsize 61
5130 23:42:28.694876 [CA 4] Center 33 (3~64) winsize 62
5131 23:42:28.697864 [CA 5] Center 33 (3~63) winsize 61
5132 23:42:28.697947
5133 23:42:28.701316 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5134 23:42:28.701400
5135 23:42:28.704548 [CATrainingPosCal] consider 1 rank data
5136 23:42:28.707638 u2DelayCellTimex100 = 270/100 ps
5137 23:42:28.710971 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5138 23:42:28.714739 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5139 23:42:28.717707 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5140 23:42:28.724756 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5141 23:42:28.727654 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5142 23:42:28.730940 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5143 23:42:28.731011
5144 23:42:28.734553 CA PerBit enable=1, Macro0, CA PI delay=33
5145 23:42:28.734637
5146 23:42:28.737734 [CBTSetCACLKResult] CA Dly = 33
5147 23:42:28.737818 CS Dly: 7 (0~38)
5148 23:42:28.737884 ==
5149 23:42:28.741275 Dram Type= 6, Freq= 0, CH_0, rank 1
5150 23:42:28.748101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5151 23:42:28.748185 ==
5152 23:42:28.750780 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5153 23:42:28.757277 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5154 23:42:28.760462 [CA 0] Center 37 (7~68) winsize 62
5155 23:42:28.763977 [CA 1] Center 37 (7~68) winsize 62
5156 23:42:28.767499 [CA 2] Center 34 (4~65) winsize 62
5157 23:42:28.770557 [CA 3] Center 34 (4~65) winsize 62
5158 23:42:28.774705 [CA 4] Center 33 (3~64) winsize 62
5159 23:42:28.777323 [CA 5] Center 33 (3~63) winsize 61
5160 23:42:28.777406
5161 23:42:28.780534 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5162 23:42:28.780633
5163 23:42:28.783658 [CATrainingPosCal] consider 2 rank data
5164 23:42:28.786905 u2DelayCellTimex100 = 270/100 ps
5165 23:42:28.790597 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5166 23:42:28.797372 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5167 23:42:28.800291 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5168 23:42:28.803628 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5169 23:42:28.807287 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5170 23:42:28.810188 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5171 23:42:28.810285
5172 23:42:28.813574 CA PerBit enable=1, Macro0, CA PI delay=33
5173 23:42:28.813659
5174 23:42:28.816900 [CBTSetCACLKResult] CA Dly = 33
5175 23:42:28.820255 CS Dly: 7 (0~39)
5176 23:42:28.820338
5177 23:42:28.823258 ----->DramcWriteLeveling(PI) begin...
5178 23:42:28.823345 ==
5179 23:42:28.826661 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 23:42:28.830014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 23:42:28.830134 ==
5182 23:42:28.832962 Write leveling (Byte 0): 35 => 35
5183 23:42:28.836657 Write leveling (Byte 1): 27 => 27
5184 23:42:28.839841 DramcWriteLeveling(PI) end<-----
5185 23:42:28.839925
5186 23:42:28.839991 ==
5187 23:42:28.843183 Dram Type= 6, Freq= 0, CH_0, rank 0
5188 23:42:28.846349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5189 23:42:28.846433 ==
5190 23:42:28.849594 [Gating] SW mode calibration
5191 23:42:28.856149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5192 23:42:28.862754 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5193 23:42:28.865968 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5194 23:42:28.869502 0 14 4 | B1->B0 | 3332 3434 | 1 1 | (0 0) (1 1)
5195 23:42:28.876073 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5196 23:42:28.879508 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5197 23:42:28.882578 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 23:42:28.889138 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5199 23:42:28.892621 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5200 23:42:28.895897 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5201 23:42:28.902637 0 15 0 | B1->B0 | 3030 2424 | 0 0 | (0 0) (0 0)
5202 23:42:28.905726 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5203 23:42:28.908859 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5204 23:42:28.915455 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5205 23:42:28.918872 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 23:42:28.922391 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 23:42:28.928615 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5208 23:42:28.931880 0 15 28 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5209 23:42:28.935567 1 0 0 | B1->B0 | 2929 4242 | 0 0 | (0 0) (0 0)
5210 23:42:28.941641 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5211 23:42:28.945052 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 23:42:28.951947 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 23:42:28.954895 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 23:42:28.958605 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 23:42:28.964778 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5216 23:42:28.968136 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5217 23:42:28.971750 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5218 23:42:28.974805 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5219 23:42:28.981383 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 23:42:28.984741 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 23:42:28.988247 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 23:42:28.995341 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 23:42:28.998493 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 23:42:29.001287 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 23:42:29.008119 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 23:42:29.011247 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 23:42:29.014531 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 23:42:29.021171 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 23:42:29.024556 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 23:42:29.027586 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 23:42:29.034264 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5232 23:42:29.037313 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5233 23:42:29.040833 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5234 23:42:29.044145 Total UI for P1: 0, mck2ui 16
5235 23:42:29.047769 best dqsien dly found for B0: ( 1, 2, 26)
5236 23:42:29.053890 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5237 23:42:29.057398 Total UI for P1: 0, mck2ui 16
5238 23:42:29.060711 best dqsien dly found for B1: ( 1, 3, 0)
5239 23:42:29.064224 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5240 23:42:29.067464 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5241 23:42:29.067546
5242 23:42:29.070745 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5243 23:42:29.074259 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5244 23:42:29.077059 [Gating] SW calibration Done
5245 23:42:29.077162 ==
5246 23:42:29.080707 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 23:42:29.083644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 23:42:29.083755 ==
5249 23:42:29.087249 RX Vref Scan: 0
5250 23:42:29.087332
5251 23:42:29.090429 RX Vref 0 -> 0, step: 1
5252 23:42:29.090512
5253 23:42:29.090577 RX Delay -80 -> 252, step: 8
5254 23:42:29.097070 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5255 23:42:29.100423 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5256 23:42:29.103454 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5257 23:42:29.106871 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5258 23:42:29.110072 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5259 23:42:29.113564 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5260 23:42:29.120443 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5261 23:42:29.123486 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5262 23:42:29.126686 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5263 23:42:29.130428 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5264 23:42:29.133756 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5265 23:42:29.139992 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5266 23:42:29.143147 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5267 23:42:29.146702 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5268 23:42:29.150096 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5269 23:42:29.153296 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5270 23:42:29.153406 ==
5271 23:42:29.156745 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 23:42:29.163075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 23:42:29.163161 ==
5274 23:42:29.163226 DQS Delay:
5275 23:42:29.166438 DQS0 = 0, DQS1 = 0
5276 23:42:29.166520 DQM Delay:
5277 23:42:29.169557 DQM0 = 97, DQM1 = 86
5278 23:42:29.169640 DQ Delay:
5279 23:42:29.173091 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5280 23:42:29.176197 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5281 23:42:29.179547 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5282 23:42:29.183088 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5283 23:42:29.183171
5284 23:42:29.183236
5285 23:42:29.183296 ==
5286 23:42:29.186231 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 23:42:29.189770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 23:42:29.189853 ==
5289 23:42:29.189918
5290 23:42:29.189978
5291 23:42:29.192995 TX Vref Scan disable
5292 23:42:29.196684 == TX Byte 0 ==
5293 23:42:29.199567 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5294 23:42:29.202540 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5295 23:42:29.205832 == TX Byte 1 ==
5296 23:42:29.209285 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5297 23:42:29.212737 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5298 23:42:29.212826 ==
5299 23:42:29.216437 Dram Type= 6, Freq= 0, CH_0, rank 0
5300 23:42:29.222720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5301 23:42:29.223147 ==
5302 23:42:29.223479
5303 23:42:29.223789
5304 23:42:29.224087 TX Vref Scan disable
5305 23:42:29.227477 == TX Byte 0 ==
5306 23:42:29.230051 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5307 23:42:29.236538 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5308 23:42:29.236960 == TX Byte 1 ==
5309 23:42:29.240179 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5310 23:42:29.246504 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5311 23:42:29.246926
5312 23:42:29.247257 [DATLAT]
5313 23:42:29.247565 Freq=933, CH0 RK0
5314 23:42:29.247870
5315 23:42:29.250137 DATLAT Default: 0xd
5316 23:42:29.252931 0, 0xFFFF, sum = 0
5317 23:42:29.253362 1, 0xFFFF, sum = 0
5318 23:42:29.256921 2, 0xFFFF, sum = 0
5319 23:42:29.257350 3, 0xFFFF, sum = 0
5320 23:42:29.259553 4, 0xFFFF, sum = 0
5321 23:42:29.259980 5, 0xFFFF, sum = 0
5322 23:42:29.263078 6, 0xFFFF, sum = 0
5323 23:42:29.263508 7, 0xFFFF, sum = 0
5324 23:42:29.266357 8, 0xFFFF, sum = 0
5325 23:42:29.266812 9, 0xFFFF, sum = 0
5326 23:42:29.269842 10, 0x0, sum = 1
5327 23:42:29.270314 11, 0x0, sum = 2
5328 23:42:29.272968 12, 0x0, sum = 3
5329 23:42:29.273393 13, 0x0, sum = 4
5330 23:42:29.276020 best_step = 11
5331 23:42:29.276623
5332 23:42:29.277002 ==
5333 23:42:29.279271 Dram Type= 6, Freq= 0, CH_0, rank 0
5334 23:42:29.282607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 23:42:29.283111 ==
5336 23:42:29.283468 RX Vref Scan: 1
5337 23:42:29.285891
5338 23:42:29.286425 RX Vref 0 -> 0, step: 1
5339 23:42:29.286765
5340 23:42:29.289058 RX Delay -61 -> 252, step: 4
5341 23:42:29.289597
5342 23:42:29.292705 Set Vref, RX VrefLevel [Byte0]: 59
5343 23:42:29.295748 [Byte1]: 58
5344 23:42:29.299483
5345 23:42:29.302534 Final RX Vref Byte 0 = 59 to rank0
5346 23:42:29.302909 Final RX Vref Byte 1 = 58 to rank0
5347 23:42:29.305356 Final RX Vref Byte 0 = 59 to rank1
5348 23:42:29.309036 Final RX Vref Byte 1 = 58 to rank1==
5349 23:42:29.312603 Dram Type= 6, Freq= 0, CH_0, rank 0
5350 23:42:29.318890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 23:42:29.319078 ==
5352 23:42:29.319243 DQS Delay:
5353 23:42:29.322511 DQS0 = 0, DQS1 = 0
5354 23:42:29.322718 DQM Delay:
5355 23:42:29.322892 DQM0 = 97, DQM1 = 86
5356 23:42:29.325656 DQ Delay:
5357 23:42:29.328748 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =92
5358 23:42:29.332245 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =106
5359 23:42:29.335028 DQ8 =80, DQ9 =78, DQ10 =86, DQ11 =82
5360 23:42:29.338482 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5361 23:42:29.338619
5362 23:42:29.338743
5363 23:42:29.345093 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
5364 23:42:29.348168 CH0 RK0: MR19=505, MR18=2C13
5365 23:42:29.354689 CH0_RK0: MR19=0x505, MR18=0x2C13, DQSOSC=408, MR23=63, INC=65, DEC=43
5366 23:42:29.354948
5367 23:42:29.358085 ----->DramcWriteLeveling(PI) begin...
5368 23:42:29.358337 ==
5369 23:42:29.361774 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 23:42:29.364743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 23:42:29.365034 ==
5372 23:42:29.368164 Write leveling (Byte 0): 31 => 31
5373 23:42:29.371657 Write leveling (Byte 1): 29 => 29
5374 23:42:29.374904 DramcWriteLeveling(PI) end<-----
5375 23:42:29.375552
5376 23:42:29.376109 ==
5377 23:42:29.378273 Dram Type= 6, Freq= 0, CH_0, rank 1
5378 23:42:29.384966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5379 23:42:29.385492 ==
5380 23:42:29.385865 [Gating] SW mode calibration
5381 23:42:29.394894 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5382 23:42:29.398477 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5383 23:42:29.401462 0 14 0 | B1->B0 | 2b2b 3131 | 0 1 | (0 0) (1 1)
5384 23:42:29.408215 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5385 23:42:29.411364 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5386 23:42:29.414800 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 23:42:29.421250 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5388 23:42:29.424833 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5389 23:42:29.428317 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5390 23:42:29.434745 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
5391 23:42:29.437516 0 15 0 | B1->B0 | 2d2d 2727 | 1 1 | (0 1) (1 0)
5392 23:42:29.441442 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5393 23:42:29.447913 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5394 23:42:29.451162 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 23:42:29.454133 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 23:42:29.460764 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 23:42:29.464144 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 23:42:29.467386 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5399 23:42:29.474094 1 0 0 | B1->B0 | 3b3b 3e3e | 0 0 | (0 0) (1 1)
5400 23:42:29.477544 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5401 23:42:29.480569 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5402 23:42:29.487199 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 23:42:29.490488 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 23:42:29.494041 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 23:42:29.500853 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 23:42:29.503493 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 23:42:29.510069 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5408 23:42:29.513322 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 23:42:29.516877 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 23:42:29.523304 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 23:42:29.526822 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 23:42:29.529548 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 23:42:29.536707 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 23:42:29.539705 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 23:42:29.542945 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 23:42:29.549523 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 23:42:29.552677 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 23:42:29.556225 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 23:42:29.563198 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 23:42:29.565995 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 23:42:29.569770 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 23:42:29.576303 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5423 23:42:29.579753 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5424 23:42:29.582857 Total UI for P1: 0, mck2ui 16
5425 23:42:29.585892 best dqsien dly found for B0: ( 1, 2, 28)
5426 23:42:29.589563 Total UI for P1: 0, mck2ui 16
5427 23:42:29.592173 best dqsien dly found for B1: ( 1, 2, 28)
5428 23:42:29.595257 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5429 23:42:29.598700 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5430 23:42:29.598783
5431 23:42:29.601710 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5432 23:42:29.605104 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5433 23:42:29.608708 [Gating] SW calibration Done
5434 23:42:29.608792 ==
5435 23:42:29.612194 Dram Type= 6, Freq= 0, CH_0, rank 1
5436 23:42:29.615120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5437 23:42:29.615204 ==
5438 23:42:29.618453 RX Vref Scan: 0
5439 23:42:29.618537
5440 23:42:29.622102 RX Vref 0 -> 0, step: 1
5441 23:42:29.622247
5442 23:42:29.622316 RX Delay -80 -> 252, step: 8
5443 23:42:29.628654 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5444 23:42:29.632097 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5445 23:42:29.635346 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5446 23:42:29.638451 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5447 23:42:29.641760 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5448 23:42:29.644973 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5449 23:42:29.651805 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5450 23:42:29.655586 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5451 23:42:29.658483 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5452 23:42:29.661904 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5453 23:42:29.665143 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5454 23:42:29.671549 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5455 23:42:29.675118 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5456 23:42:29.677924 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5457 23:42:29.681884 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5458 23:42:29.684551 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5459 23:42:29.684629 ==
5460 23:42:29.687863 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 23:42:29.694511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 23:42:29.694592 ==
5463 23:42:29.694665 DQS Delay:
5464 23:42:29.697836 DQS0 = 0, DQS1 = 0
5465 23:42:29.697913 DQM Delay:
5466 23:42:29.697976 DQM0 = 96, DQM1 = 89
5467 23:42:29.701063 DQ Delay:
5468 23:42:29.704410 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5469 23:42:29.708033 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5470 23:42:29.711198 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5471 23:42:29.714408 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5472 23:42:29.714491
5473 23:42:29.714556
5474 23:42:29.714616 ==
5475 23:42:29.717507 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 23:42:29.721373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 23:42:29.721487 ==
5478 23:42:29.721581
5479 23:42:29.721682
5480 23:42:29.724876 TX Vref Scan disable
5481 23:42:29.727660 == TX Byte 0 ==
5482 23:42:29.731104 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5483 23:42:29.734136 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5484 23:42:29.737396 == TX Byte 1 ==
5485 23:42:29.740470 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5486 23:42:29.743829 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5487 23:42:29.743939 ==
5488 23:42:29.747382 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 23:42:29.754018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 23:42:29.754126 ==
5491 23:42:29.754244
5492 23:42:29.754306
5493 23:42:29.754365 TX Vref Scan disable
5494 23:42:29.757842 == TX Byte 0 ==
5495 23:42:29.761156 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5496 23:42:29.767674 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5497 23:42:29.767764 == TX Byte 1 ==
5498 23:42:29.770956 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5499 23:42:29.777679 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5500 23:42:29.777763
5501 23:42:29.777828 [DATLAT]
5502 23:42:29.777889 Freq=933, CH0 RK1
5503 23:42:29.777979
5504 23:42:29.781033 DATLAT Default: 0xb
5505 23:42:29.781102 0, 0xFFFF, sum = 0
5506 23:42:29.784305 1, 0xFFFF, sum = 0
5507 23:42:29.787462 2, 0xFFFF, sum = 0
5508 23:42:29.787548 3, 0xFFFF, sum = 0
5509 23:42:29.791082 4, 0xFFFF, sum = 0
5510 23:42:29.791172 5, 0xFFFF, sum = 0
5511 23:42:29.793863 6, 0xFFFF, sum = 0
5512 23:42:29.793948 7, 0xFFFF, sum = 0
5513 23:42:29.797648 8, 0xFFFF, sum = 0
5514 23:42:29.797733 9, 0xFFFF, sum = 0
5515 23:42:29.800741 10, 0x0, sum = 1
5516 23:42:29.800825 11, 0x0, sum = 2
5517 23:42:29.803932 12, 0x0, sum = 3
5518 23:42:29.804016 13, 0x0, sum = 4
5519 23:42:29.804083 best_step = 11
5520 23:42:29.807350
5521 23:42:29.807431 ==
5522 23:42:29.810659 Dram Type= 6, Freq= 0, CH_0, rank 1
5523 23:42:29.814197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5524 23:42:29.814280 ==
5525 23:42:29.814345 RX Vref Scan: 0
5526 23:42:29.814406
5527 23:42:29.817295 RX Vref 0 -> 0, step: 1
5528 23:42:29.817378
5529 23:42:29.820613 RX Delay -61 -> 252, step: 4
5530 23:42:29.826924 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5531 23:42:29.830294 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5532 23:42:29.833664 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5533 23:42:29.836917 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5534 23:42:29.840365 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5535 23:42:29.843734 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5536 23:42:29.850095 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5537 23:42:29.853364 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5538 23:42:29.857191 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5539 23:42:29.859807 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5540 23:42:29.863152 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5541 23:42:29.870062 iDelay=203, Bit 11, Center 84 (-5 ~ 174) 180
5542 23:42:29.873506 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5543 23:42:29.876937 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5544 23:42:29.880179 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5545 23:42:29.883290 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5546 23:42:29.886794 ==
5547 23:42:29.889504 Dram Type= 6, Freq= 0, CH_0, rank 1
5548 23:42:29.893078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 23:42:29.893174 ==
5550 23:42:29.893323 DQS Delay:
5551 23:42:29.896461 DQS0 = 0, DQS1 = 0
5552 23:42:29.896582 DQM Delay:
5553 23:42:29.899528 DQM0 = 95, DQM1 = 87
5554 23:42:29.899611 DQ Delay:
5555 23:42:29.902711 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5556 23:42:29.906071 DQ4 =96, DQ5 =86, DQ6 =106, DQ7 =104
5557 23:42:29.909371 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =84
5558 23:42:29.912868 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5559 23:42:29.912948
5560 23:42:29.913013
5561 23:42:29.919358 [DQSOSCAuto] RK1, (LSB)MR18= 0x27f7, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5562 23:42:29.923224 CH0 RK1: MR19=504, MR18=27F7
5563 23:42:29.929622 CH0_RK1: MR19=0x504, MR18=0x27F7, DQSOSC=409, MR23=63, INC=64, DEC=43
5564 23:42:29.932482 [RxdqsGatingPostProcess] freq 933
5565 23:42:29.939307 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5566 23:42:29.942403 best DQS0 dly(2T, 0.5T) = (0, 10)
5567 23:42:29.946051 best DQS1 dly(2T, 0.5T) = (0, 11)
5568 23:42:29.949340 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5569 23:42:29.952185 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5570 23:42:29.952280 best DQS0 dly(2T, 0.5T) = (0, 10)
5571 23:42:29.955921 best DQS1 dly(2T, 0.5T) = (0, 10)
5572 23:42:29.959226 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5573 23:42:29.962032 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5574 23:42:29.965756 Pre-setting of DQS Precalculation
5575 23:42:29.972319 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5576 23:42:29.972407 ==
5577 23:42:29.975618 Dram Type= 6, Freq= 0, CH_1, rank 0
5578 23:42:29.978955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 23:42:29.979041 ==
5580 23:42:29.985703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5581 23:42:29.991995 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5582 23:42:29.995121 [CA 0] Center 36 (6~67) winsize 62
5583 23:42:29.998722 [CA 1] Center 37 (6~68) winsize 63
5584 23:42:30.001686 [CA 2] Center 34 (4~65) winsize 62
5585 23:42:30.005307 [CA 3] Center 33 (3~64) winsize 62
5586 23:42:30.008314 [CA 4] Center 34 (4~65) winsize 62
5587 23:42:30.011735 [CA 5] Center 33 (3~64) winsize 62
5588 23:42:30.011840
5589 23:42:30.014914 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5590 23:42:30.014998
5591 23:42:30.018370 [CATrainingPosCal] consider 1 rank data
5592 23:42:30.021598 u2DelayCellTimex100 = 270/100 ps
5593 23:42:30.025715 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5594 23:42:30.028325 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5595 23:42:30.031541 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5596 23:42:30.035083 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5597 23:42:30.037851 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5598 23:42:30.041818 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5599 23:42:30.041901
5600 23:42:30.047981 CA PerBit enable=1, Macro0, CA PI delay=33
5601 23:42:30.048070
5602 23:42:30.048138 [CBTSetCACLKResult] CA Dly = 33
5603 23:42:30.051433 CS Dly: 6 (0~37)
5604 23:42:30.051508 ==
5605 23:42:30.054736 Dram Type= 6, Freq= 0, CH_1, rank 1
5606 23:42:30.057877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5607 23:42:30.057962 ==
5608 23:42:30.065126 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5609 23:42:30.071113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5610 23:42:30.074319 [CA 0] Center 36 (6~67) winsize 62
5611 23:42:30.077918 [CA 1] Center 37 (7~67) winsize 61
5612 23:42:30.081124 [CA 2] Center 34 (4~65) winsize 62
5613 23:42:30.084254 [CA 3] Center 33 (3~64) winsize 62
5614 23:42:30.087594 [CA 4] Center 34 (3~65) winsize 63
5615 23:42:30.090868 [CA 5] Center 33 (3~64) winsize 62
5616 23:42:30.090970
5617 23:42:30.093981 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5618 23:42:30.094067
5619 23:42:30.097057 [CATrainingPosCal] consider 2 rank data
5620 23:42:30.100474 u2DelayCellTimex100 = 270/100 ps
5621 23:42:30.103992 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5622 23:42:30.107878 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5623 23:42:30.110577 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5624 23:42:30.113746 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5625 23:42:30.120656 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5626 23:42:30.123973 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5627 23:42:30.124059
5628 23:42:30.126771 CA PerBit enable=1, Macro0, CA PI delay=33
5629 23:42:30.126860
5630 23:42:30.130455 [CBTSetCACLKResult] CA Dly = 33
5631 23:42:30.130540 CS Dly: 7 (0~39)
5632 23:42:30.130611
5633 23:42:30.133674 ----->DramcWriteLeveling(PI) begin...
5634 23:42:30.133765 ==
5635 23:42:30.136875 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 23:42:30.143657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 23:42:30.143745 ==
5638 23:42:30.147472 Write leveling (Byte 0): 25 => 25
5639 23:42:30.150272 Write leveling (Byte 1): 27 => 27
5640 23:42:30.150355 DramcWriteLeveling(PI) end<-----
5641 23:42:30.150422
5642 23:42:30.153386 ==
5643 23:42:30.156623 Dram Type= 6, Freq= 0, CH_1, rank 0
5644 23:42:30.159961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5645 23:42:30.160044 ==
5646 23:42:30.163453 [Gating] SW mode calibration
5647 23:42:30.169827 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5648 23:42:30.173129 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5649 23:42:30.179866 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 23:42:30.183513 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5651 23:42:30.186315 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5652 23:42:30.193120 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5653 23:42:30.196713 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5654 23:42:30.199925 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5655 23:42:30.206288 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5656 23:42:30.209362 0 14 28 | B1->B0 | 2c2c 2d2d | 1 0 | (1 0) (1 1)
5657 23:42:30.212875 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5658 23:42:30.222945 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5659 23:42:30.223221 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5660 23:42:30.226480 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5661 23:42:30.232765 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5662 23:42:30.236285 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5663 23:42:30.239562 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5664 23:42:30.246178 0 15 28 | B1->B0 | 3636 3c3c | 1 0 | (0 0) (0 0)
5665 23:42:30.249494 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 23:42:30.252794 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5667 23:42:30.259092 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 23:42:30.262241 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 23:42:30.265388 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5670 23:42:30.272118 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 23:42:30.275654 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5672 23:42:30.279127 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 23:42:30.285421 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 23:42:30.288629 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 23:42:30.292630 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 23:42:30.299157 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 23:42:30.302818 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 23:42:30.305452 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 23:42:30.312795 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 23:42:30.315889 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 23:42:30.319262 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 23:42:30.325653 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 23:42:30.328431 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 23:42:30.332245 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 23:42:30.338358 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 23:42:30.341679 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5687 23:42:30.344988 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5688 23:42:30.351619 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5689 23:42:30.355155 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5690 23:42:30.358416 Total UI for P1: 0, mck2ui 16
5691 23:42:30.361825 best dqsien dly found for B0: ( 1, 2, 24)
5692 23:42:30.365058 Total UI for P1: 0, mck2ui 16
5693 23:42:30.368003 best dqsien dly found for B1: ( 1, 2, 28)
5694 23:42:30.371448 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5695 23:42:30.374645 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5696 23:42:30.375068
5697 23:42:30.378469 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5698 23:42:30.381313 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5699 23:42:30.384886 [Gating] SW calibration Done
5700 23:42:30.385479 ==
5701 23:42:30.388342 Dram Type= 6, Freq= 0, CH_1, rank 0
5702 23:42:30.394536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5703 23:42:30.395130 ==
5704 23:42:30.395491 RX Vref Scan: 0
5705 23:42:30.395810
5706 23:42:30.398264 RX Vref 0 -> 0, step: 1
5707 23:42:30.398684
5708 23:42:30.401517 RX Delay -80 -> 252, step: 8
5709 23:42:30.404600 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5710 23:42:30.408123 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5711 23:42:30.411043 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5712 23:42:30.414473 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5713 23:42:30.418086 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5714 23:42:30.424726 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5715 23:42:30.427441 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5716 23:42:30.430744 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5717 23:42:30.434047 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5718 23:42:30.437462 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5719 23:42:30.444598 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5720 23:42:30.447807 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5721 23:42:30.451170 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5722 23:42:30.454460 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5723 23:42:30.457637 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5724 23:42:30.464043 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5725 23:42:30.464564 ==
5726 23:42:30.467186 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 23:42:30.470819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 23:42:30.471251 ==
5729 23:42:30.471590 DQS Delay:
5730 23:42:30.474070 DQS0 = 0, DQS1 = 0
5731 23:42:30.474573 DQM Delay:
5732 23:42:30.477815 DQM0 = 101, DQM1 = 91
5733 23:42:30.478398 DQ Delay:
5734 23:42:30.480798 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5735 23:42:30.483844 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =95
5736 23:42:30.487295 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =83
5737 23:42:30.490919 DQ12 =103, DQ13 =95, DQ14 =99, DQ15 =99
5738 23:42:30.491357
5739 23:42:30.491793
5740 23:42:30.492205 ==
5741 23:42:30.493819 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 23:42:30.497053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 23:42:30.500656 ==
5744 23:42:30.501093
5745 23:42:30.501429
5746 23:42:30.501745 TX Vref Scan disable
5747 23:42:30.503676 == TX Byte 0 ==
5748 23:42:30.507349 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5749 23:42:30.510263 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5750 23:42:30.513551 == TX Byte 1 ==
5751 23:42:30.516906 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5752 23:42:30.520367 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5753 23:42:30.523791 ==
5754 23:42:30.527230 Dram Type= 6, Freq= 0, CH_1, rank 0
5755 23:42:30.530787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5756 23:42:30.531214 ==
5757 23:42:30.531567
5758 23:42:30.531917
5759 23:42:30.533456 TX Vref Scan disable
5760 23:42:30.534054 == TX Byte 0 ==
5761 23:42:30.540256 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5762 23:42:30.543336 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5763 23:42:30.543759 == TX Byte 1 ==
5764 23:42:30.549742 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5765 23:42:30.553422 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5766 23:42:30.553841
5767 23:42:30.554212 [DATLAT]
5768 23:42:30.556483 Freq=933, CH1 RK0
5769 23:42:30.556906
5770 23:42:30.557282 DATLAT Default: 0xd
5771 23:42:30.560038 0, 0xFFFF, sum = 0
5772 23:42:30.560469 1, 0xFFFF, sum = 0
5773 23:42:30.563154 2, 0xFFFF, sum = 0
5774 23:42:30.563581 3, 0xFFFF, sum = 0
5775 23:42:30.566545 4, 0xFFFF, sum = 0
5776 23:42:30.570217 5, 0xFFFF, sum = 0
5777 23:42:30.570649 6, 0xFFFF, sum = 0
5778 23:42:30.572795 7, 0xFFFF, sum = 0
5779 23:42:30.573221 8, 0xFFFF, sum = 0
5780 23:42:30.576047 9, 0xFFFF, sum = 0
5781 23:42:30.576525 10, 0x0, sum = 1
5782 23:42:30.579496 11, 0x0, sum = 2
5783 23:42:30.579927 12, 0x0, sum = 3
5784 23:42:30.582718 13, 0x0, sum = 4
5785 23:42:30.583149 best_step = 11
5786 23:42:30.583481
5787 23:42:30.583792 ==
5788 23:42:30.586023 Dram Type= 6, Freq= 0, CH_1, rank 0
5789 23:42:30.589467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 23:42:30.590039 ==
5791 23:42:30.592842 RX Vref Scan: 1
5792 23:42:30.593432
5793 23:42:30.596081 RX Vref 0 -> 0, step: 1
5794 23:42:30.596673
5795 23:42:30.597176 RX Delay -61 -> 252, step: 4
5796 23:42:30.597678
5797 23:42:30.599223 Set Vref, RX VrefLevel [Byte0]: 49
5798 23:42:30.602436 [Byte1]: 55
5799 23:42:30.607709
5800 23:42:30.608155 Final RX Vref Byte 0 = 49 to rank0
5801 23:42:30.610931 Final RX Vref Byte 1 = 55 to rank0
5802 23:42:30.613705 Final RX Vref Byte 0 = 49 to rank1
5803 23:42:30.617497 Final RX Vref Byte 1 = 55 to rank1==
5804 23:42:30.620727 Dram Type= 6, Freq= 0, CH_1, rank 0
5805 23:42:30.627137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 23:42:30.627563 ==
5807 23:42:30.627897 DQS Delay:
5808 23:42:30.630342 DQS0 = 0, DQS1 = 0
5809 23:42:30.630766 DQM Delay:
5810 23:42:30.631099 DQM0 = 101, DQM1 = 93
5811 23:42:30.634113 DQ Delay:
5812 23:42:30.637295 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5813 23:42:30.640601 DQ4 =98, DQ5 =112, DQ6 =108, DQ7 =98
5814 23:42:30.643469 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =84
5815 23:42:30.647018 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =104
5816 23:42:30.647566
5817 23:42:30.647982
5818 23:42:30.653517 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 412 ps
5819 23:42:30.656655 CH1 RK0: MR19=505, MR18=1F0E
5820 23:42:30.663707 CH1_RK0: MR19=0x505, MR18=0x1F0E, DQSOSC=412, MR23=63, INC=63, DEC=42
5821 23:42:30.664160
5822 23:42:30.667170 ----->DramcWriteLeveling(PI) begin...
5823 23:42:30.667616 ==
5824 23:42:30.669979 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 23:42:30.673673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 23:42:30.674122 ==
5827 23:42:30.676959 Write leveling (Byte 0): 26 => 26
5828 23:42:30.680288 Write leveling (Byte 1): 27 => 27
5829 23:42:30.683299 DramcWriteLeveling(PI) end<-----
5830 23:42:30.683869
5831 23:42:30.684373 ==
5832 23:42:30.686642 Dram Type= 6, Freq= 0, CH_1, rank 1
5833 23:42:30.693180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5834 23:42:30.693761 ==
5835 23:42:30.694349 [Gating] SW mode calibration
5836 23:42:30.703626 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5837 23:42:30.706556 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5838 23:42:30.713085 0 14 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 1)
5839 23:42:30.716379 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5840 23:42:30.719898 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5841 23:42:30.723126 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5842 23:42:30.729623 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5843 23:42:30.732907 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5844 23:42:30.736291 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
5845 23:42:30.742563 0 14 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
5846 23:42:30.746282 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
5847 23:42:30.749333 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5848 23:42:30.755689 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5849 23:42:30.759271 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5850 23:42:30.765902 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5851 23:42:30.768995 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5852 23:42:30.772311 0 15 24 | B1->B0 | 2929 2323 | 0 0 | (1 1) (0 0)
5853 23:42:30.778801 0 15 28 | B1->B0 | 3c3c 3030 | 0 0 | (1 1) (0 0)
5854 23:42:30.781935 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 23:42:30.785652 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 23:42:30.791960 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5857 23:42:30.795439 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 23:42:30.798707 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 23:42:30.805449 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 23:42:30.809233 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5861 23:42:30.812122 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5862 23:42:30.818611 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5863 23:42:30.821923 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 23:42:30.824794 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 23:42:30.831536 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 23:42:30.834599 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 23:42:30.838029 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 23:42:30.845116 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 23:42:30.847778 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 23:42:30.851228 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 23:42:30.858004 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 23:42:30.861366 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 23:42:30.864628 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 23:42:30.870740 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 23:42:30.874446 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 23:42:30.877684 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5877 23:42:30.884265 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5878 23:42:30.884774 Total UI for P1: 0, mck2ui 16
5879 23:42:30.890880 best dqsien dly found for B0: ( 1, 2, 26)
5880 23:42:30.891313 Total UI for P1: 0, mck2ui 16
5881 23:42:30.897466 best dqsien dly found for B1: ( 1, 2, 24)
5882 23:42:30.900472 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5883 23:42:30.904133 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5884 23:42:30.904798
5885 23:42:30.906942 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5886 23:42:30.910904 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5887 23:42:30.913891 [Gating] SW calibration Done
5888 23:42:30.914479 ==
5889 23:42:30.916855 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 23:42:30.920241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 23:42:30.920799 ==
5892 23:42:30.923408 RX Vref Scan: 0
5893 23:42:30.923959
5894 23:42:30.924458 RX Vref 0 -> 0, step: 1
5895 23:42:30.924956
5896 23:42:30.926993 RX Delay -80 -> 252, step: 8
5897 23:42:30.930650 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5898 23:42:30.937140 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5899 23:42:30.940491 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5900 23:42:30.943702 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5901 23:42:30.946917 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5902 23:42:30.950099 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5903 23:42:30.956385 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5904 23:42:30.960188 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5905 23:42:30.963276 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5906 23:42:30.966594 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5907 23:42:30.969533 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5908 23:42:30.972984 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5909 23:42:30.979496 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5910 23:42:30.982842 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5911 23:42:30.986092 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5912 23:42:30.989533 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5913 23:42:30.990098 ==
5914 23:42:30.992846 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 23:42:30.999080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 23:42:30.999659 ==
5917 23:42:31.000191 DQS Delay:
5918 23:42:31.000777 DQS0 = 0, DQS1 = 0
5919 23:42:31.002351 DQM Delay:
5920 23:42:31.002867 DQM0 = 100, DQM1 = 91
5921 23:42:31.005592 DQ Delay:
5922 23:42:31.009287 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5923 23:42:31.012791 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5924 23:42:31.015764 DQ8 =79, DQ9 =79, DQ10 =95, DQ11 =83
5925 23:42:31.018985 DQ12 =103, DQ13 =99, DQ14 =95, DQ15 =99
5926 23:42:31.019650
5927 23:42:31.020146
5928 23:42:31.020611 ==
5929 23:42:31.022017 Dram Type= 6, Freq= 0, CH_1, rank 1
5930 23:42:31.025351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5931 23:42:31.025852 ==
5932 23:42:31.026395
5933 23:42:31.026943
5934 23:42:31.028629 TX Vref Scan disable
5935 23:42:31.031880 == TX Byte 0 ==
5936 23:42:31.035376 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5937 23:42:31.038983 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5938 23:42:31.042000 == TX Byte 1 ==
5939 23:42:31.045451 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5940 23:42:31.048713 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5941 23:42:31.049140 ==
5942 23:42:31.051813 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 23:42:31.058892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 23:42:31.059323 ==
5945 23:42:31.059673
5946 23:42:31.059988
5947 23:42:31.060286 TX Vref Scan disable
5948 23:42:31.062305 == TX Byte 0 ==
5949 23:42:31.065436 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5950 23:42:31.072082 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5951 23:42:31.072508 == TX Byte 1 ==
5952 23:42:31.075656 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5953 23:42:31.082243 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5954 23:42:31.082671
5955 23:42:31.083008 [DATLAT]
5956 23:42:31.083321 Freq=933, CH1 RK1
5957 23:42:31.083626
5958 23:42:31.085111 DATLAT Default: 0xb
5959 23:42:31.088674 0, 0xFFFF, sum = 0
5960 23:42:31.089335 1, 0xFFFF, sum = 0
5961 23:42:31.091888 2, 0xFFFF, sum = 0
5962 23:42:31.092520 3, 0xFFFF, sum = 0
5963 23:42:31.095111 4, 0xFFFF, sum = 0
5964 23:42:31.095649 5, 0xFFFF, sum = 0
5965 23:42:31.098765 6, 0xFFFF, sum = 0
5966 23:42:31.099202 7, 0xFFFF, sum = 0
5967 23:42:31.101769 8, 0xFFFF, sum = 0
5968 23:42:31.102408 9, 0xFFFF, sum = 0
5969 23:42:31.105055 10, 0x0, sum = 1
5970 23:42:31.105684 11, 0x0, sum = 2
5971 23:42:31.108212 12, 0x0, sum = 3
5972 23:42:31.108771 13, 0x0, sum = 4
5973 23:42:31.111567 best_step = 11
5974 23:42:31.112113
5975 23:42:31.112650 ==
5976 23:42:31.114885 Dram Type= 6, Freq= 0, CH_1, rank 1
5977 23:42:31.118721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5978 23:42:31.119250 ==
5979 23:42:31.119726 RX Vref Scan: 0
5980 23:42:31.121905
5981 23:42:31.122434 RX Vref 0 -> 0, step: 1
5982 23:42:31.123016
5983 23:42:31.124903 RX Delay -61 -> 252, step: 4
5984 23:42:31.131353 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
5985 23:42:31.134695 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
5986 23:42:31.137841 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
5987 23:42:31.141068 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
5988 23:42:31.144340 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
5989 23:42:31.150918 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
5990 23:42:31.154751 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
5991 23:42:31.157357 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
5992 23:42:31.161048 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
5993 23:42:31.164400 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
5994 23:42:31.170692 iDelay=207, Bit 10, Center 92 (-1 ~ 186) 188
5995 23:42:31.174112 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
5996 23:42:31.177056 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
5997 23:42:31.180521 iDelay=207, Bit 13, Center 98 (7 ~ 190) 184
5998 23:42:31.183515 iDelay=207, Bit 14, Center 102 (11 ~ 194) 184
5999 23:42:31.190079 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6000 23:42:31.190223 ==
6001 23:42:31.193273 Dram Type= 6, Freq= 0, CH_1, rank 1
6002 23:42:31.196612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6003 23:42:31.196714 ==
6004 23:42:31.196808 DQS Delay:
6005 23:42:31.199885 DQS0 = 0, DQS1 = 0
6006 23:42:31.199985 DQM Delay:
6007 23:42:31.203308 DQM0 = 101, DQM1 = 93
6008 23:42:31.203408 DQ Delay:
6009 23:42:31.206425 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
6010 23:42:31.209913 DQ4 =100, DQ5 =110, DQ6 =114, DQ7 =96
6011 23:42:31.213061 DQ8 =82, DQ9 =84, DQ10 =92, DQ11 =84
6012 23:42:31.216371 DQ12 =104, DQ13 =98, DQ14 =102, DQ15 =102
6013 23:42:31.216454
6014 23:42:31.216518
6015 23:42:31.226292 [DQSOSCAuto] RK1, (LSB)MR18= 0x700, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 419 ps
6016 23:42:31.226375 CH1 RK1: MR19=505, MR18=700
6017 23:42:31.232847 CH1_RK1: MR19=0x505, MR18=0x700, DQSOSC=419, MR23=63, INC=61, DEC=41
6018 23:42:31.236344 [RxdqsGatingPostProcess] freq 933
6019 23:42:31.242924 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6020 23:42:31.246600 best DQS0 dly(2T, 0.5T) = (0, 10)
6021 23:42:31.249785 best DQS1 dly(2T, 0.5T) = (0, 10)
6022 23:42:31.253196 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6023 23:42:31.256447 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6024 23:42:31.259944 best DQS0 dly(2T, 0.5T) = (0, 10)
6025 23:42:31.263112 best DQS1 dly(2T, 0.5T) = (0, 10)
6026 23:42:31.266361 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6027 23:42:31.269502 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6028 23:42:31.269962 Pre-setting of DQS Precalculation
6029 23:42:31.276289 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6030 23:42:31.282532 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6031 23:42:31.289502 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6032 23:42:31.290109
6033 23:42:31.290576
6034 23:42:31.292596 [Calibration Summary] 1866 Mbps
6035 23:42:31.295767 CH 0, Rank 0
6036 23:42:31.296371 SW Impedance : PASS
6037 23:42:31.299156 DUTY Scan : NO K
6038 23:42:31.302274 ZQ Calibration : PASS
6039 23:42:31.302849 Jitter Meter : NO K
6040 23:42:31.305524 CBT Training : PASS
6041 23:42:31.309298 Write leveling : PASS
6042 23:42:31.309734 RX DQS gating : PASS
6043 23:42:31.312661 RX DQ/DQS(RDDQC) : PASS
6044 23:42:31.315581 TX DQ/DQS : PASS
6045 23:42:31.316129 RX DATLAT : PASS
6046 23:42:31.319088 RX DQ/DQS(Engine): PASS
6047 23:42:31.322049 TX OE : NO K
6048 23:42:31.322536 All Pass.
6049 23:42:31.322914
6050 23:42:31.323301 CH 0, Rank 1
6051 23:42:31.325350 SW Impedance : PASS
6052 23:42:31.328707 DUTY Scan : NO K
6053 23:42:31.329304 ZQ Calibration : PASS
6054 23:42:31.332534 Jitter Meter : NO K
6055 23:42:31.335771 CBT Training : PASS
6056 23:42:31.336200 Write leveling : PASS
6057 23:42:31.339436 RX DQS gating : PASS
6058 23:42:31.340030 RX DQ/DQS(RDDQC) : PASS
6059 23:42:31.341948 TX DQ/DQS : PASS
6060 23:42:31.345344 RX DATLAT : PASS
6061 23:42:31.345904 RX DQ/DQS(Engine): PASS
6062 23:42:31.348443 TX OE : NO K
6063 23:42:31.348998 All Pass.
6064 23:42:31.349491
6065 23:42:31.351603 CH 1, Rank 0
6066 23:42:31.352127 SW Impedance : PASS
6067 23:42:31.355005 DUTY Scan : NO K
6068 23:42:31.358556 ZQ Calibration : PASS
6069 23:42:31.359171 Jitter Meter : NO K
6070 23:42:31.362234 CBT Training : PASS
6071 23:42:31.364935 Write leveling : PASS
6072 23:42:31.365492 RX DQS gating : PASS
6073 23:42:31.368452 RX DQ/DQS(RDDQC) : PASS
6074 23:42:31.371664 TX DQ/DQS : PASS
6075 23:42:31.372099 RX DATLAT : PASS
6076 23:42:31.374664 RX DQ/DQS(Engine): PASS
6077 23:42:31.378287 TX OE : NO K
6078 23:42:31.378738 All Pass.
6079 23:42:31.379082
6080 23:42:31.379421 CH 1, Rank 1
6081 23:42:31.381835 SW Impedance : PASS
6082 23:42:31.384577 DUTY Scan : NO K
6083 23:42:31.385181 ZQ Calibration : PASS
6084 23:42:31.388006 Jitter Meter : NO K
6085 23:42:31.391119 CBT Training : PASS
6086 23:42:31.391679 Write leveling : PASS
6087 23:42:31.394440 RX DQS gating : PASS
6088 23:42:31.397636 RX DQ/DQS(RDDQC) : PASS
6089 23:42:31.398263 TX DQ/DQS : PASS
6090 23:42:31.401155 RX DATLAT : PASS
6091 23:42:31.404622 RX DQ/DQS(Engine): PASS
6092 23:42:31.405219 TX OE : NO K
6093 23:42:31.408100 All Pass.
6094 23:42:31.408558
6095 23:42:31.408888 DramC Write-DBI off
6096 23:42:31.411425 PER_BANK_REFRESH: Hybrid Mode
6097 23:42:31.411850 TX_TRACKING: ON
6098 23:42:31.421203 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6099 23:42:31.424643 [FAST_K] Save calibration result to emmc
6100 23:42:31.427903 dramc_set_vcore_voltage set vcore to 650000
6101 23:42:31.430867 Read voltage for 400, 6
6102 23:42:31.431396 Vio18 = 0
6103 23:42:31.434491 Vcore = 650000
6104 23:42:31.434911 Vdram = 0
6105 23:42:31.435242 Vddq = 0
6106 23:42:31.435548 Vmddr = 0
6107 23:42:31.440679 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6108 23:42:31.447687 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6109 23:42:31.448111 MEM_TYPE=3, freq_sel=20
6110 23:42:31.450435 sv_algorithm_assistance_LP4_800
6111 23:42:31.454264 ============ PULL DRAM RESETB DOWN ============
6112 23:42:31.460598 ========== PULL DRAM RESETB DOWN end =========
6113 23:42:31.463971 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6114 23:42:31.467626 ===================================
6115 23:42:31.470832 LPDDR4 DRAM CONFIGURATION
6116 23:42:31.474147 ===================================
6117 23:42:31.474650 EX_ROW_EN[0] = 0x0
6118 23:42:31.477390 EX_ROW_EN[1] = 0x0
6119 23:42:31.480372 LP4Y_EN = 0x0
6120 23:42:31.480800 WORK_FSP = 0x0
6121 23:42:31.483707 WL = 0x2
6122 23:42:31.484137 RL = 0x2
6123 23:42:31.487294 BL = 0x2
6124 23:42:31.487888 RPST = 0x0
6125 23:42:31.490305 RD_PRE = 0x0
6126 23:42:31.490888 WR_PRE = 0x1
6127 23:42:31.493599 WR_PST = 0x0
6128 23:42:31.494151 DBI_WR = 0x0
6129 23:42:31.496774 DBI_RD = 0x0
6130 23:42:31.497338 OTF = 0x1
6131 23:42:31.500373 ===================================
6132 23:42:31.503776 ===================================
6133 23:42:31.506572 ANA top config
6134 23:42:31.509685 ===================================
6135 23:42:31.513177 DLL_ASYNC_EN = 0
6136 23:42:31.513729 ALL_SLAVE_EN = 1
6137 23:42:31.516750 NEW_RANK_MODE = 1
6138 23:42:31.520134 DLL_IDLE_MODE = 1
6139 23:42:31.523114 LP45_APHY_COMB_EN = 1
6140 23:42:31.523684 TX_ODT_DIS = 1
6141 23:42:31.526562 NEW_8X_MODE = 1
6142 23:42:31.530228 ===================================
6143 23:42:31.533409 ===================================
6144 23:42:31.536531 data_rate = 800
6145 23:42:31.539570 CKR = 1
6146 23:42:31.543366 DQ_P2S_RATIO = 4
6147 23:42:31.546275 ===================================
6148 23:42:31.549632 CA_P2S_RATIO = 4
6149 23:42:31.550223 DQ_CA_OPEN = 0
6150 23:42:31.553094 DQ_SEMI_OPEN = 1
6151 23:42:31.556836 CA_SEMI_OPEN = 1
6152 23:42:31.559710 CA_FULL_RATE = 0
6153 23:42:31.562968 DQ_CKDIV4_EN = 0
6154 23:42:31.565975 CA_CKDIV4_EN = 1
6155 23:42:31.566616 CA_PREDIV_EN = 0
6156 23:42:31.569477 PH8_DLY = 0
6157 23:42:31.572848 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6158 23:42:31.576133 DQ_AAMCK_DIV = 0
6159 23:42:31.579789 CA_AAMCK_DIV = 0
6160 23:42:31.583035 CA_ADMCK_DIV = 4
6161 23:42:31.583497 DQ_TRACK_CA_EN = 0
6162 23:42:31.585862 CA_PICK = 800
6163 23:42:31.589544 CA_MCKIO = 400
6164 23:42:31.592820 MCKIO_SEMI = 400
6165 23:42:31.595960 PLL_FREQ = 3016
6166 23:42:31.599507 DQ_UI_PI_RATIO = 32
6167 23:42:31.602510 CA_UI_PI_RATIO = 32
6168 23:42:31.606012 ===================================
6169 23:42:31.609035 ===================================
6170 23:42:31.612885 memory_type:LPDDR4
6171 23:42:31.613324 GP_NUM : 10
6172 23:42:31.616136 SRAM_EN : 1
6173 23:42:31.616557 MD32_EN : 0
6174 23:42:31.619430 ===================================
6175 23:42:31.622277 [ANA_INIT] >>>>>>>>>>>>>>
6176 23:42:31.625702 <<<<<< [CONFIGURE PHASE]: ANA_TX
6177 23:42:31.628763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6178 23:42:31.632164 ===================================
6179 23:42:31.635915 data_rate = 800,PCW = 0X7400
6180 23:42:31.639165 ===================================
6181 23:42:31.642042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6182 23:42:31.645570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6183 23:42:31.658559 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6184 23:42:31.662130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6185 23:42:31.664852 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6186 23:42:31.668283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6187 23:42:31.671654 [ANA_INIT] flow start
6188 23:42:31.675101 [ANA_INIT] PLL >>>>>>>>
6189 23:42:31.675523 [ANA_INIT] PLL <<<<<<<<
6190 23:42:31.678344 [ANA_INIT] MIDPI >>>>>>>>
6191 23:42:31.681686 [ANA_INIT] MIDPI <<<<<<<<
6192 23:42:31.684696 [ANA_INIT] DLL >>>>>>>>
6193 23:42:31.685150 [ANA_INIT] flow end
6194 23:42:31.688054 ============ LP4 DIFF to SE enter ============
6195 23:42:31.694835 ============ LP4 DIFF to SE exit ============
6196 23:42:31.695258 [ANA_INIT] <<<<<<<<<<<<<
6197 23:42:31.697791 [Flow] Enable top DCM control >>>>>
6198 23:42:31.701527 [Flow] Enable top DCM control <<<<<
6199 23:42:31.704300 Enable DLL master slave shuffle
6200 23:42:31.711440 ==============================================================
6201 23:42:31.714780 Gating Mode config
6202 23:42:31.717515 ==============================================================
6203 23:42:31.720615 Config description:
6204 23:42:31.731117 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6205 23:42:31.737309 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6206 23:42:31.740478 SELPH_MODE 0: By rank 1: By Phase
6207 23:42:31.747168 ==============================================================
6208 23:42:31.750285 GAT_TRACK_EN = 0
6209 23:42:31.753974 RX_GATING_MODE = 2
6210 23:42:31.757399 RX_GATING_TRACK_MODE = 2
6211 23:42:31.757859 SELPH_MODE = 1
6212 23:42:31.760359 PICG_EARLY_EN = 1
6213 23:42:31.764097 VALID_LAT_VALUE = 1
6214 23:42:31.770813 ==============================================================
6215 23:42:31.773430 Enter into Gating configuration >>>>
6216 23:42:31.777063 Exit from Gating configuration <<<<
6217 23:42:31.780622 Enter into DVFS_PRE_config >>>>>
6218 23:42:31.790895 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6219 23:42:31.793440 Exit from DVFS_PRE_config <<<<<
6220 23:42:31.796537 Enter into PICG configuration >>>>
6221 23:42:31.799839 Exit from PICG configuration <<<<
6222 23:42:31.803727 [RX_INPUT] configuration >>>>>
6223 23:42:31.806396 [RX_INPUT] configuration <<<<<
6224 23:42:31.812794 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6225 23:42:31.816517 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6226 23:42:31.822781 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6227 23:42:31.829670 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6228 23:42:31.836520 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6229 23:42:31.842768 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6230 23:42:31.845802 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6231 23:42:31.849517 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6232 23:42:31.852691 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6233 23:42:31.859768 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6234 23:42:31.862760 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6235 23:42:31.865798 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6236 23:42:31.869022 ===================================
6237 23:42:31.872379 LPDDR4 DRAM CONFIGURATION
6238 23:42:31.875540 ===================================
6239 23:42:31.878708 EX_ROW_EN[0] = 0x0
6240 23:42:31.879373 EX_ROW_EN[1] = 0x0
6241 23:42:31.882549 LP4Y_EN = 0x0
6242 23:42:31.883162 WORK_FSP = 0x0
6243 23:42:31.885512 WL = 0x2
6244 23:42:31.886157 RL = 0x2
6245 23:42:31.888667 BL = 0x2
6246 23:42:31.889039 RPST = 0x0
6247 23:42:31.892203 RD_PRE = 0x0
6248 23:42:31.892708 WR_PRE = 0x1
6249 23:42:31.895521 WR_PST = 0x0
6250 23:42:31.896049 DBI_WR = 0x0
6251 23:42:31.898881 DBI_RD = 0x0
6252 23:42:31.899253 OTF = 0x1
6253 23:42:31.902134 ===================================
6254 23:42:31.908774 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6255 23:42:31.912348 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6256 23:42:31.915249 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6257 23:42:31.918440 ===================================
6258 23:42:31.921868 LPDDR4 DRAM CONFIGURATION
6259 23:42:31.924874 ===================================
6260 23:42:31.928706 EX_ROW_EN[0] = 0x10
6261 23:42:31.929130 EX_ROW_EN[1] = 0x0
6262 23:42:31.931735 LP4Y_EN = 0x0
6263 23:42:31.932163 WORK_FSP = 0x0
6264 23:42:31.934966 WL = 0x2
6265 23:42:31.935426 RL = 0x2
6266 23:42:31.938217 BL = 0x2
6267 23:42:31.938642 RPST = 0x0
6268 23:42:31.942005 RD_PRE = 0x0
6269 23:42:31.942475 WR_PRE = 0x1
6270 23:42:31.945769 WR_PST = 0x0
6271 23:42:31.946329 DBI_WR = 0x0
6272 23:42:31.948545 DBI_RD = 0x0
6273 23:42:31.949071 OTF = 0x1
6274 23:42:31.951367 ===================================
6275 23:42:31.957886 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6276 23:42:31.962512 nWR fixed to 30
6277 23:42:31.966334 [ModeRegInit_LP4] CH0 RK0
6278 23:42:31.966799 [ModeRegInit_LP4] CH0 RK1
6279 23:42:31.969488 [ModeRegInit_LP4] CH1 RK0
6280 23:42:31.972628 [ModeRegInit_LP4] CH1 RK1
6281 23:42:31.973060 match AC timing 19
6282 23:42:31.979264 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6283 23:42:31.982317 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6284 23:42:31.985502 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6285 23:42:31.992357 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6286 23:42:31.995456 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6287 23:42:31.995873 ==
6288 23:42:31.999075 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 23:42:32.002513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 23:42:32.002971 ==
6291 23:42:32.009173 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6292 23:42:32.015320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6293 23:42:32.018662 [CA 0] Center 36 (8~64) winsize 57
6294 23:42:32.022261 [CA 1] Center 36 (8~64) winsize 57
6295 23:42:32.025708 [CA 2] Center 36 (8~64) winsize 57
6296 23:42:32.028811 [CA 3] Center 36 (8~64) winsize 57
6297 23:42:32.032021 [CA 4] Center 36 (8~64) winsize 57
6298 23:42:32.035213 [CA 5] Center 36 (8~64) winsize 57
6299 23:42:32.035709
6300 23:42:32.038117 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6301 23:42:32.038682
6302 23:42:32.041278 [CATrainingPosCal] consider 1 rank data
6303 23:42:32.044546 u2DelayCellTimex100 = 270/100 ps
6304 23:42:32.048359 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 23:42:32.051852 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 23:42:32.054629 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 23:42:32.057917 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 23:42:32.061636 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 23:42:32.064795 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 23:42:32.065223
6311 23:42:32.071170 CA PerBit enable=1, Macro0, CA PI delay=36
6312 23:42:32.071660
6313 23:42:32.074436 [CBTSetCACLKResult] CA Dly = 36
6314 23:42:32.074906 CS Dly: 1 (0~32)
6315 23:42:32.075319 ==
6316 23:42:32.078001 Dram Type= 6, Freq= 0, CH_0, rank 1
6317 23:42:32.080933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 23:42:32.081356 ==
6319 23:42:32.088061 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6320 23:42:32.094141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6321 23:42:32.097833 [CA 0] Center 36 (8~64) winsize 57
6322 23:42:32.101056 [CA 1] Center 36 (8~64) winsize 57
6323 23:42:32.104179 [CA 2] Center 36 (8~64) winsize 57
6324 23:42:32.107630 [CA 3] Center 36 (8~64) winsize 57
6325 23:42:32.111073 [CA 4] Center 36 (8~64) winsize 57
6326 23:42:32.111549 [CA 5] Center 36 (8~64) winsize 57
6327 23:42:32.114061
6328 23:42:32.117266 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6329 23:42:32.117932
6330 23:42:32.120657 [CATrainingPosCal] consider 2 rank data
6331 23:42:32.124134 u2DelayCellTimex100 = 270/100 ps
6332 23:42:32.127607 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 23:42:32.130885 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 23:42:32.134203 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 23:42:32.137671 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 23:42:32.140859 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 23:42:32.143800 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 23:42:32.144221
6339 23:42:32.146986 CA PerBit enable=1, Macro0, CA PI delay=36
6340 23:42:32.150295
6341 23:42:32.150589 [CBTSetCACLKResult] CA Dly = 36
6342 23:42:32.153869 CS Dly: 1 (0~32)
6343 23:42:32.154182
6344 23:42:32.156948 ----->DramcWriteLeveling(PI) begin...
6345 23:42:32.157349 ==
6346 23:42:32.160350 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 23:42:32.163422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 23:42:32.163720 ==
6349 23:42:32.166929 Write leveling (Byte 0): 40 => 8
6350 23:42:32.170425 Write leveling (Byte 1): 32 => 0
6351 23:42:32.173413 DramcWriteLeveling(PI) end<-----
6352 23:42:32.173710
6353 23:42:32.173942 ==
6354 23:42:32.176683 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 23:42:32.180148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 23:42:32.183263 ==
6357 23:42:32.183561 [Gating] SW mode calibration
6358 23:42:32.193218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6359 23:42:32.196701 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6360 23:42:32.200190 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6361 23:42:32.206093 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6362 23:42:32.209852 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6363 23:42:32.213110 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6364 23:42:32.219679 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6365 23:42:32.222510 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6366 23:42:32.226415 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6367 23:42:32.232736 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6368 23:42:32.235946 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6369 23:42:32.239334 Total UI for P1: 0, mck2ui 16
6370 23:42:32.242976 best dqsien dly found for B0: ( 0, 14, 24)
6371 23:42:32.246210 Total UI for P1: 0, mck2ui 16
6372 23:42:32.249030 best dqsien dly found for B1: ( 0, 14, 24)
6373 23:42:32.252494 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6374 23:42:32.255673 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6375 23:42:32.256107
6376 23:42:32.259075 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6377 23:42:32.265652 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6378 23:42:32.266000 [Gating] SW calibration Done
6379 23:42:32.266280 ==
6380 23:42:32.268939 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 23:42:32.275225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 23:42:32.275452 ==
6383 23:42:32.275603 RX Vref Scan: 0
6384 23:42:32.275741
6385 23:42:32.278724 RX Vref 0 -> 0, step: 1
6386 23:42:32.278917
6387 23:42:32.282179 RX Delay -410 -> 252, step: 16
6388 23:42:32.285173 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6389 23:42:32.288571 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6390 23:42:32.294769 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6391 23:42:32.298059 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6392 23:42:32.301643 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6393 23:42:32.304825 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6394 23:42:32.311168 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6395 23:42:32.314822 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6396 23:42:32.318226 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6397 23:42:32.321119 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6398 23:42:32.327890 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6399 23:42:32.331166 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6400 23:42:32.334753 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6401 23:42:32.341050 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6402 23:42:32.344180 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6403 23:42:32.347843 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6404 23:42:32.347950 ==
6405 23:42:32.351097 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 23:42:32.353932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 23:42:32.357238 ==
6408 23:42:32.357367 DQS Delay:
6409 23:42:32.357468 DQS0 = 43, DQS1 = 59
6410 23:42:32.360670 DQM Delay:
6411 23:42:32.360815 DQM0 = 9, DQM1 = 11
6412 23:42:32.364142 DQ Delay:
6413 23:42:32.364283 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6414 23:42:32.367243 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6415 23:42:32.370716 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6416 23:42:32.373731 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6417 23:42:32.373914
6418 23:42:32.374059
6419 23:42:32.377087 ==
6420 23:42:32.380695 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 23:42:32.384072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 23:42:32.384339 ==
6423 23:42:32.384546
6424 23:42:32.384735
6425 23:42:32.387284 TX Vref Scan disable
6426 23:42:32.387609 == TX Byte 0 ==
6427 23:42:32.390801 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6428 23:42:32.397559 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6429 23:42:32.397985 == TX Byte 1 ==
6430 23:42:32.400977 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6431 23:42:32.407212 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6432 23:42:32.407909 ==
6433 23:42:32.410895 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 23:42:32.413921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 23:42:32.414402 ==
6436 23:42:32.414746
6437 23:42:32.415062
6438 23:42:32.417265 TX Vref Scan disable
6439 23:42:32.417685 == TX Byte 0 ==
6440 23:42:32.420814 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6441 23:42:32.427420 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6442 23:42:32.427868 == TX Byte 1 ==
6443 23:42:32.433322 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6444 23:42:32.436710 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6445 23:42:32.436973
6446 23:42:32.437237 [DATLAT]
6447 23:42:32.440124 Freq=400, CH0 RK0
6448 23:42:32.440365
6449 23:42:32.440572 DATLAT Default: 0xf
6450 23:42:32.443120 0, 0xFFFF, sum = 0
6451 23:42:32.443307 1, 0xFFFF, sum = 0
6452 23:42:32.446760 2, 0xFFFF, sum = 0
6453 23:42:32.446917 3, 0xFFFF, sum = 0
6454 23:42:32.450102 4, 0xFFFF, sum = 0
6455 23:42:32.450251 5, 0xFFFF, sum = 0
6456 23:42:32.453158 6, 0xFFFF, sum = 0
6457 23:42:32.453291 7, 0xFFFF, sum = 0
6458 23:42:32.456489 8, 0xFFFF, sum = 0
6459 23:42:32.456610 9, 0xFFFF, sum = 0
6460 23:42:32.459859 10, 0xFFFF, sum = 0
6461 23:42:32.462695 11, 0xFFFF, sum = 0
6462 23:42:32.462800 12, 0xFFFF, sum = 0
6463 23:42:32.466024 13, 0x0, sum = 1
6464 23:42:32.466118 14, 0x0, sum = 2
6465 23:42:32.466205 15, 0x0, sum = 3
6466 23:42:32.469458 16, 0x0, sum = 4
6467 23:42:32.469542 best_step = 14
6468 23:42:32.469608
6469 23:42:32.472756 ==
6470 23:42:32.472840 Dram Type= 6, Freq= 0, CH_0, rank 0
6471 23:42:32.479345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 23:42:32.479429 ==
6473 23:42:32.479495 RX Vref Scan: 1
6474 23:42:32.479556
6475 23:42:32.482720 RX Vref 0 -> 0, step: 1
6476 23:42:32.482803
6477 23:42:32.486403 RX Delay -359 -> 252, step: 8
6478 23:42:32.486486
6479 23:42:32.489661 Set Vref, RX VrefLevel [Byte0]: 59
6480 23:42:32.492725 [Byte1]: 58
6481 23:42:32.496720
6482 23:42:32.496804 Final RX Vref Byte 0 = 59 to rank0
6483 23:42:32.499732 Final RX Vref Byte 1 = 58 to rank0
6484 23:42:32.502787 Final RX Vref Byte 0 = 59 to rank1
6485 23:42:32.506097 Final RX Vref Byte 1 = 58 to rank1==
6486 23:42:32.509328 Dram Type= 6, Freq= 0, CH_0, rank 0
6487 23:42:32.516232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 23:42:32.516318 ==
6489 23:42:32.516384 DQS Delay:
6490 23:42:32.519354 DQS0 = 48, DQS1 = 60
6491 23:42:32.519436 DQM Delay:
6492 23:42:32.519501 DQM0 = 11, DQM1 = 10
6493 23:42:32.522674 DQ Delay:
6494 23:42:32.525680 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6495 23:42:32.529240 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6496 23:42:32.532464 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6497 23:42:32.535827 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =20
6498 23:42:32.536018
6499 23:42:32.536116
6500 23:42:32.542607 [DQSOSCAuto] RK0, (LSB)MR18= 0xbf82, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6501 23:42:32.545735 CH0 RK0: MR19=C0C, MR18=BF82
6502 23:42:32.552848 CH0_RK0: MR19=0xC0C, MR18=0xBF82, DQSOSC=386, MR23=63, INC=396, DEC=264
6503 23:42:32.553089 ==
6504 23:42:32.555917 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 23:42:32.559194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 23:42:32.559427 ==
6507 23:42:32.562354 [Gating] SW mode calibration
6508 23:42:32.568921 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6509 23:42:32.575914 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6510 23:42:32.579080 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6511 23:42:32.582514 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6512 23:42:32.589031 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6513 23:42:32.592454 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6514 23:42:32.595554 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6515 23:42:32.602049 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6516 23:42:32.605735 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6517 23:42:32.608589 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6518 23:42:32.615183 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6519 23:42:32.618730 Total UI for P1: 0, mck2ui 16
6520 23:42:32.621984 best dqsien dly found for B0: ( 0, 14, 24)
6521 23:42:32.625132 Total UI for P1: 0, mck2ui 16
6522 23:42:32.628361 best dqsien dly found for B1: ( 0, 14, 24)
6523 23:42:32.632343 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6524 23:42:32.635034 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6525 23:42:32.635457
6526 23:42:32.638628 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6527 23:42:32.641502 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6528 23:42:32.644783 [Gating] SW calibration Done
6529 23:42:32.645205 ==
6530 23:42:32.648017 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 23:42:32.651265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 23:42:32.651688 ==
6533 23:42:32.654744 RX Vref Scan: 0
6534 23:42:32.655317
6535 23:42:32.658017 RX Vref 0 -> 0, step: 1
6536 23:42:32.658481
6537 23:42:32.661386 RX Delay -410 -> 252, step: 16
6538 23:42:32.664789 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6539 23:42:32.667516 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6540 23:42:32.670606 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6541 23:42:32.677213 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6542 23:42:32.681126 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6543 23:42:32.684361 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6544 23:42:32.687497 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6545 23:42:32.693635 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6546 23:42:32.696897 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6547 23:42:32.700631 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6548 23:42:32.703767 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6549 23:42:32.710425 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6550 23:42:32.713757 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6551 23:42:32.716745 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6552 23:42:32.723472 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6553 23:42:32.726621 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6554 23:42:32.726704 ==
6555 23:42:32.730006 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 23:42:32.733297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 23:42:32.733380 ==
6558 23:42:32.736919 DQS Delay:
6559 23:42:32.737000 DQS0 = 43, DQS1 = 59
6560 23:42:32.737064 DQM Delay:
6561 23:42:32.739899 DQM0 = 10, DQM1 = 15
6562 23:42:32.739981 DQ Delay:
6563 23:42:32.743505 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6564 23:42:32.746477 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6565 23:42:32.749807 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6566 23:42:32.753293 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6567 23:42:32.753375
6568 23:42:32.753440
6569 23:42:32.753499 ==
6570 23:42:32.756821 Dram Type= 6, Freq= 0, CH_0, rank 1
6571 23:42:32.763005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6572 23:42:32.763090 ==
6573 23:42:32.763155
6574 23:42:32.763216
6575 23:42:32.763275 TX Vref Scan disable
6576 23:42:32.766257 == TX Byte 0 ==
6577 23:42:32.769622 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6578 23:42:32.772825 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6579 23:42:32.776088 == TX Byte 1 ==
6580 23:42:32.779903 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6581 23:42:32.782890 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6582 23:42:32.782968 ==
6583 23:42:32.786415 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 23:42:32.793920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 23:42:32.794035 ==
6586 23:42:32.794130
6587 23:42:32.794246
6588 23:42:32.794306 TX Vref Scan disable
6589 23:42:32.796020 == TX Byte 0 ==
6590 23:42:32.799014 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6591 23:42:32.802761 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6592 23:42:32.806584 == TX Byte 1 ==
6593 23:42:32.809110 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6594 23:42:32.812955 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6595 23:42:32.813051
6596 23:42:32.815423 [DATLAT]
6597 23:42:32.815506 Freq=400, CH0 RK1
6598 23:42:32.815611
6599 23:42:32.819331 DATLAT Default: 0xe
6600 23:42:32.819415 0, 0xFFFF, sum = 0
6601 23:42:32.822344 1, 0xFFFF, sum = 0
6602 23:42:32.822464 2, 0xFFFF, sum = 0
6603 23:42:32.825892 3, 0xFFFF, sum = 0
6604 23:42:32.826000 4, 0xFFFF, sum = 0
6605 23:42:32.829042 5, 0xFFFF, sum = 0
6606 23:42:32.829116 6, 0xFFFF, sum = 0
6607 23:42:32.832113 7, 0xFFFF, sum = 0
6608 23:42:32.832188 8, 0xFFFF, sum = 0
6609 23:42:32.835391 9, 0xFFFF, sum = 0
6610 23:42:32.839085 10, 0xFFFF, sum = 0
6611 23:42:32.839165 11, 0xFFFF, sum = 0
6612 23:42:32.842257 12, 0xFFFF, sum = 0
6613 23:42:32.842336 13, 0x0, sum = 1
6614 23:42:32.845237 14, 0x0, sum = 2
6615 23:42:32.845310 15, 0x0, sum = 3
6616 23:42:32.849168 16, 0x0, sum = 4
6617 23:42:32.849255 best_step = 14
6618 23:42:32.849320
6619 23:42:32.849380 ==
6620 23:42:32.852334 Dram Type= 6, Freq= 0, CH_0, rank 1
6621 23:42:32.855285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6622 23:42:32.855363 ==
6623 23:42:32.858649 RX Vref Scan: 0
6624 23:42:32.858734
6625 23:42:32.861837 RX Vref 0 -> 0, step: 1
6626 23:42:32.861911
6627 23:42:32.861982 RX Delay -359 -> 252, step: 8
6628 23:42:32.870944 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6629 23:42:32.874360 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6630 23:42:32.877258 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6631 23:42:32.880764 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6632 23:42:32.887357 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6633 23:42:32.891067 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6634 23:42:32.893820 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6635 23:42:32.897224 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6636 23:42:32.903619 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6637 23:42:32.906778 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6638 23:42:32.910200 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6639 23:42:32.916941 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6640 23:42:32.920032 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6641 23:42:32.923739 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6642 23:42:32.926706 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6643 23:42:32.933121 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6644 23:42:32.933236 ==
6645 23:42:32.936653 Dram Type= 6, Freq= 0, CH_0, rank 1
6646 23:42:32.940238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 23:42:32.940338 ==
6648 23:42:32.940435 DQS Delay:
6649 23:42:32.943298 DQS0 = 44, DQS1 = 60
6650 23:42:32.943396 DQM Delay:
6651 23:42:32.946458 DQM0 = 7, DQM1 = 14
6652 23:42:32.946557 DQ Delay:
6653 23:42:32.949833 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6654 23:42:32.953129 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6655 23:42:32.956281 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6656 23:42:32.959778 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6657 23:42:32.959877
6658 23:42:32.959949
6659 23:42:32.966500 [DQSOSCAuto] RK1, (LSB)MR18= 0xbb45, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6660 23:42:32.969497 CH0 RK1: MR19=C0C, MR18=BB45
6661 23:42:32.976279 CH0_RK1: MR19=0xC0C, MR18=0xBB45, DQSOSC=386, MR23=63, INC=396, DEC=264
6662 23:42:32.979262 [RxdqsGatingPostProcess] freq 400
6663 23:42:32.985947 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6664 23:42:32.989211 best DQS0 dly(2T, 0.5T) = (0, 10)
6665 23:42:32.992623 best DQS1 dly(2T, 0.5T) = (0, 10)
6666 23:42:32.996327 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6667 23:42:32.999606 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6668 23:42:32.999690 best DQS0 dly(2T, 0.5T) = (0, 10)
6669 23:42:33.002552 best DQS1 dly(2T, 0.5T) = (0, 10)
6670 23:42:33.005766 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6671 23:42:33.008961 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6672 23:42:33.012358 Pre-setting of DQS Precalculation
6673 23:42:33.018770 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6674 23:42:33.018873 ==
6675 23:42:33.022342 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 23:42:33.025705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 23:42:33.025795 ==
6678 23:42:33.032155 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6679 23:42:33.038794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6680 23:42:33.041982 [CA 0] Center 36 (8~64) winsize 57
6681 23:42:33.045594 [CA 1] Center 36 (8~64) winsize 57
6682 23:42:33.045678 [CA 2] Center 36 (8~64) winsize 57
6683 23:42:33.048356 [CA 3] Center 36 (8~64) winsize 57
6684 23:42:33.051997 [CA 4] Center 36 (8~64) winsize 57
6685 23:42:33.055306 [CA 5] Center 36 (8~64) winsize 57
6686 23:42:33.055389
6687 23:42:33.058462 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6688 23:42:33.061731
6689 23:42:33.065157 [CATrainingPosCal] consider 1 rank data
6690 23:42:33.068384 u2DelayCellTimex100 = 270/100 ps
6691 23:42:33.071682 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 23:42:33.074950 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 23:42:33.078275 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 23:42:33.081558 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 23:42:33.085084 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 23:42:33.088033 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 23:42:33.088116
6698 23:42:33.091689 CA PerBit enable=1, Macro0, CA PI delay=36
6699 23:42:33.091788
6700 23:42:33.094718 [CBTSetCACLKResult] CA Dly = 36
6701 23:42:33.098223 CS Dly: 1 (0~32)
6702 23:42:33.098317 ==
6703 23:42:33.101209 Dram Type= 6, Freq= 0, CH_1, rank 1
6704 23:42:33.104489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 23:42:33.104574 ==
6706 23:42:33.111213 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6707 23:42:33.117816 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6708 23:42:33.121137 [CA 0] Center 36 (8~64) winsize 57
6709 23:42:33.121220 [CA 1] Center 36 (8~64) winsize 57
6710 23:42:33.124487 [CA 2] Center 36 (8~64) winsize 57
6711 23:42:33.128015 [CA 3] Center 36 (8~64) winsize 57
6712 23:42:33.131098 [CA 4] Center 36 (8~64) winsize 57
6713 23:42:33.134086 [CA 5] Center 36 (8~64) winsize 57
6714 23:42:33.134181
6715 23:42:33.137385 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6716 23:42:33.137468
6717 23:42:33.141452 [CATrainingPosCal] consider 2 rank data
6718 23:42:33.144183 u2DelayCellTimex100 = 270/100 ps
6719 23:42:33.147492 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 23:42:33.154330 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 23:42:33.157695 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 23:42:33.160960 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 23:42:33.163982 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 23:42:33.167065 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 23:42:33.167163
6726 23:42:33.170769 CA PerBit enable=1, Macro0, CA PI delay=36
6727 23:42:33.170852
6728 23:42:33.173704 [CBTSetCACLKResult] CA Dly = 36
6729 23:42:33.177703 CS Dly: 1 (0~32)
6730 23:42:33.177800
6731 23:42:33.180164 ----->DramcWriteLeveling(PI) begin...
6732 23:42:33.180249 ==
6733 23:42:33.183955 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 23:42:33.187226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 23:42:33.187308 ==
6736 23:42:33.190680 Write leveling (Byte 0): 40 => 8
6737 23:42:33.193448 Write leveling (Byte 1): 32 => 0
6738 23:42:33.197098 DramcWriteLeveling(PI) end<-----
6739 23:42:33.197192
6740 23:42:33.197323 ==
6741 23:42:33.200694 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 23:42:33.203730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 23:42:33.203844 ==
6744 23:42:33.206815 [Gating] SW mode calibration
6745 23:42:33.213290 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6746 23:42:33.219890 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6747 23:42:33.223928 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6748 23:42:33.226964 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6749 23:42:33.233411 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6750 23:42:33.236851 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6751 23:42:33.239938 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6752 23:42:33.246634 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6753 23:42:33.249889 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6754 23:42:33.253140 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6755 23:42:33.259428 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6756 23:42:33.262798 Total UI for P1: 0, mck2ui 16
6757 23:42:33.266659 best dqsien dly found for B0: ( 0, 14, 24)
6758 23:42:33.269234 Total UI for P1: 0, mck2ui 16
6759 23:42:33.273109 best dqsien dly found for B1: ( 0, 14, 24)
6760 23:42:33.275929 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6761 23:42:33.279464 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6762 23:42:33.279565
6763 23:42:33.282924 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6764 23:42:33.285975 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6765 23:42:33.289425 [Gating] SW calibration Done
6766 23:42:33.289507 ==
6767 23:42:33.292707 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 23:42:33.296113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 23:42:33.296197 ==
6770 23:42:33.299277 RX Vref Scan: 0
6771 23:42:33.299359
6772 23:42:33.302103 RX Vref 0 -> 0, step: 1
6773 23:42:33.302245
6774 23:42:33.302347 RX Delay -410 -> 252, step: 16
6775 23:42:33.309452 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6776 23:42:33.312329 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6777 23:42:33.315700 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6778 23:42:33.319267 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6779 23:42:33.325725 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6780 23:42:33.328912 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6781 23:42:33.332610 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6782 23:42:33.335890 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6783 23:42:33.342218 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6784 23:42:33.345517 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6785 23:42:33.348770 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6786 23:42:33.355406 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6787 23:42:33.358689 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6788 23:42:33.362089 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6789 23:42:33.365177 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6790 23:42:33.372195 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6791 23:42:33.372277 ==
6792 23:42:33.374943 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 23:42:33.378152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 23:42:33.378257 ==
6795 23:42:33.378323 DQS Delay:
6796 23:42:33.382005 DQS0 = 43, DQS1 = 51
6797 23:42:33.382114 DQM Delay:
6798 23:42:33.384875 DQM0 = 12, DQM1 = 14
6799 23:42:33.385004 DQ Delay:
6800 23:42:33.388328 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6801 23:42:33.391357 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6802 23:42:33.394701 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6803 23:42:33.398426 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6804 23:42:33.398531
6805 23:42:33.398612
6806 23:42:33.398673 ==
6807 23:42:33.401542 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 23:42:33.404610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 23:42:33.404696 ==
6810 23:42:33.404761
6811 23:42:33.408348
6812 23:42:33.408443 TX Vref Scan disable
6813 23:42:33.411286 == TX Byte 0 ==
6814 23:42:33.414750 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 23:42:33.418429 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 23:42:33.421778 == TX Byte 1 ==
6817 23:42:33.424732 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6818 23:42:33.428599 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6819 23:42:33.428681 ==
6820 23:42:33.431436 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 23:42:33.434801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 23:42:33.438109 ==
6823 23:42:33.438243
6824 23:42:33.438313
6825 23:42:33.438375 TX Vref Scan disable
6826 23:42:33.441331 == TX Byte 0 ==
6827 23:42:33.444407 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6828 23:42:33.447921 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6829 23:42:33.451503 == TX Byte 1 ==
6830 23:42:33.454557 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6831 23:42:33.457611 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6832 23:42:33.457694
6833 23:42:33.460759 [DATLAT]
6834 23:42:33.460842 Freq=400, CH1 RK0
6835 23:42:33.460908
6836 23:42:33.464399 DATLAT Default: 0xf
6837 23:42:33.464476 0, 0xFFFF, sum = 0
6838 23:42:33.468064 1, 0xFFFF, sum = 0
6839 23:42:33.468140 2, 0xFFFF, sum = 0
6840 23:42:33.470972 3, 0xFFFF, sum = 0
6841 23:42:33.471053 4, 0xFFFF, sum = 0
6842 23:42:33.474337 5, 0xFFFF, sum = 0
6843 23:42:33.474446 6, 0xFFFF, sum = 0
6844 23:42:33.477328 7, 0xFFFF, sum = 0
6845 23:42:33.477405 8, 0xFFFF, sum = 0
6846 23:42:33.480779 9, 0xFFFF, sum = 0
6847 23:42:33.484205 10, 0xFFFF, sum = 0
6848 23:42:33.484279 11, 0xFFFF, sum = 0
6849 23:42:33.487614 12, 0xFFFF, sum = 0
6850 23:42:33.487697 13, 0x0, sum = 1
6851 23:42:33.490332 14, 0x0, sum = 2
6852 23:42:33.490418 15, 0x0, sum = 3
6853 23:42:33.493813 16, 0x0, sum = 4
6854 23:42:33.493897 best_step = 14
6855 23:42:33.493962
6856 23:42:33.494023 ==
6857 23:42:33.497192 Dram Type= 6, Freq= 0, CH_1, rank 0
6858 23:42:33.500137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 23:42:33.500220 ==
6860 23:42:33.503713 RX Vref Scan: 1
6861 23:42:33.503813
6862 23:42:33.506699 RX Vref 0 -> 0, step: 1
6863 23:42:33.506781
6864 23:42:33.506846 RX Delay -343 -> 252, step: 8
6865 23:42:33.510044
6866 23:42:33.510145 Set Vref, RX VrefLevel [Byte0]: 49
6867 23:42:33.513542 [Byte1]: 55
6868 23:42:33.519282
6869 23:42:33.519364 Final RX Vref Byte 0 = 49 to rank0
6870 23:42:33.522870 Final RX Vref Byte 1 = 55 to rank0
6871 23:42:33.525726 Final RX Vref Byte 0 = 49 to rank1
6872 23:42:33.529075 Final RX Vref Byte 1 = 55 to rank1==
6873 23:42:33.532052 Dram Type= 6, Freq= 0, CH_1, rank 0
6874 23:42:33.538749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 23:42:33.538851 ==
6876 23:42:33.538919 DQS Delay:
6877 23:42:33.542356 DQS0 = 44, DQS1 = 56
6878 23:42:33.542438 DQM Delay:
6879 23:42:33.542503 DQM0 = 7, DQM1 = 12
6880 23:42:33.545413 DQ Delay:
6881 23:42:33.548892 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6882 23:42:33.548974 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6883 23:42:33.552064 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6884 23:42:33.555578 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
6885 23:42:33.555661
6886 23:42:33.558818
6887 23:42:33.565787 [DQSOSCAuto] RK0, (LSB)MR18= 0x976d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6888 23:42:33.568829 CH1 RK0: MR19=C0C, MR18=976D
6889 23:42:33.575513 CH1_RK0: MR19=0xC0C, MR18=0x976D, DQSOSC=390, MR23=63, INC=388, DEC=258
6890 23:42:33.575591 ==
6891 23:42:33.578812 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 23:42:33.581662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 23:42:33.581739 ==
6894 23:42:33.585165 [Gating] SW mode calibration
6895 23:42:33.591990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6896 23:42:33.598341 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6897 23:42:33.601604 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6898 23:42:33.605263 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6899 23:42:33.611295 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6900 23:42:33.615232 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6901 23:42:33.617985 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6902 23:42:33.624499 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6903 23:42:33.628358 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6904 23:42:33.631355 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6905 23:42:33.637791 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6906 23:42:33.637867 Total UI for P1: 0, mck2ui 16
6907 23:42:33.644444 best dqsien dly found for B0: ( 0, 14, 24)
6908 23:42:33.644519 Total UI for P1: 0, mck2ui 16
6909 23:42:33.650833 best dqsien dly found for B1: ( 0, 14, 24)
6910 23:42:33.654327 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6911 23:42:33.657777 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6912 23:42:33.657860
6913 23:42:33.661339 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6914 23:42:33.663965 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6915 23:42:33.667454 [Gating] SW calibration Done
6916 23:42:33.667536 ==
6917 23:42:33.670711 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 23:42:33.673960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 23:42:33.674042 ==
6920 23:42:33.676981 RX Vref Scan: 0
6921 23:42:33.677102
6922 23:42:33.677167 RX Vref 0 -> 0, step: 1
6923 23:42:33.680701
6924 23:42:33.680789 RX Delay -410 -> 252, step: 16
6925 23:42:33.687012 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6926 23:42:33.690512 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6927 23:42:33.693837 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6928 23:42:33.696951 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6929 23:42:33.703740 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6930 23:42:33.706850 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6931 23:42:33.710705 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6932 23:42:33.713959 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6933 23:42:33.719945 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6934 23:42:33.723602 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6935 23:42:33.726768 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6936 23:42:33.733937 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6937 23:42:33.736852 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6938 23:42:33.739853 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6939 23:42:33.743075 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6940 23:42:33.749926 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6941 23:42:33.750008 ==
6942 23:42:33.753230 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 23:42:33.756429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 23:42:33.756512 ==
6945 23:42:33.756577 DQS Delay:
6946 23:42:33.759960 DQS0 = 51, DQS1 = 51
6947 23:42:33.760042 DQM Delay:
6948 23:42:33.763273 DQM0 = 20, DQM1 = 15
6949 23:42:33.763355 DQ Delay:
6950 23:42:33.766428 DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16
6951 23:42:33.770004 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6952 23:42:33.773037 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6953 23:42:33.776230 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6954 23:42:33.776311
6955 23:42:33.776375
6956 23:42:33.776435 ==
6957 23:42:33.779830 Dram Type= 6, Freq= 0, CH_1, rank 1
6958 23:42:33.783341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6959 23:42:33.783423 ==
6960 23:42:33.786038
6961 23:42:33.786144
6962 23:42:33.786260 TX Vref Scan disable
6963 23:42:33.789707 == TX Byte 0 ==
6964 23:42:33.792765 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6965 23:42:33.796000 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6966 23:42:33.799508 == TX Byte 1 ==
6967 23:42:33.802532 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6968 23:42:33.806049 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6969 23:42:33.806149 ==
6970 23:42:33.809111 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 23:42:33.812526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 23:42:33.815765 ==
6973 23:42:33.815839
6974 23:42:33.815901
6975 23:42:33.815965 TX Vref Scan disable
6976 23:42:33.819534 == TX Byte 0 ==
6977 23:42:33.821997 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6978 23:42:33.826007 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6979 23:42:33.828974 == TX Byte 1 ==
6980 23:42:33.832417 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6981 23:42:33.835585 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6982 23:42:33.835670
6983 23:42:33.838783 [DATLAT]
6984 23:42:33.838870 Freq=400, CH1 RK1
6985 23:42:33.838974
6986 23:42:33.841781 DATLAT Default: 0xe
6987 23:42:33.841882 0, 0xFFFF, sum = 0
6988 23:42:33.845483 1, 0xFFFF, sum = 0
6989 23:42:33.845589 2, 0xFFFF, sum = 0
6990 23:42:33.848823 3, 0xFFFF, sum = 0
6991 23:42:33.848905 4, 0xFFFF, sum = 0
6992 23:42:33.851930 5, 0xFFFF, sum = 0
6993 23:42:33.852018 6, 0xFFFF, sum = 0
6994 23:42:33.855039 7, 0xFFFF, sum = 0
6995 23:42:33.855135 8, 0xFFFF, sum = 0
6996 23:42:33.858344 9, 0xFFFF, sum = 0
6997 23:42:33.858456 10, 0xFFFF, sum = 0
6998 23:42:33.861835 11, 0xFFFF, sum = 0
6999 23:42:33.864834 12, 0xFFFF, sum = 0
7000 23:42:33.864952 13, 0x0, sum = 1
7001 23:42:33.868570 14, 0x0, sum = 2
7002 23:42:33.868649 15, 0x0, sum = 3
7003 23:42:33.868741 16, 0x0, sum = 4
7004 23:42:33.872173 best_step = 14
7005 23:42:33.872264
7006 23:42:33.872365 ==
7007 23:42:33.875051 Dram Type= 6, Freq= 0, CH_1, rank 1
7008 23:42:33.878158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7009 23:42:33.878263 ==
7010 23:42:33.881454 RX Vref Scan: 0
7011 23:42:33.881530
7012 23:42:33.884927 RX Vref 0 -> 0, step: 1
7013 23:42:33.885010
7014 23:42:33.885075 RX Delay -343 -> 252, step: 8
7015 23:42:33.893469 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7016 23:42:33.896660 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
7017 23:42:33.900064 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7018 23:42:33.906637 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7019 23:42:33.909866 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7020 23:42:33.913265 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7021 23:42:33.916633 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7022 23:42:33.923324 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7023 23:42:33.926697 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7024 23:42:33.929677 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7025 23:42:33.933318 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7026 23:42:33.940024 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7027 23:42:33.943162 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7028 23:42:33.946482 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7029 23:42:33.949585 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7030 23:42:33.956466 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7031 23:42:33.956543 ==
7032 23:42:33.959649 Dram Type= 6, Freq= 0, CH_1, rank 1
7033 23:42:33.962444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7034 23:42:33.962543 ==
7035 23:42:33.962634 DQS Delay:
7036 23:42:33.965706 DQS0 = 48, DQS1 = 56
7037 23:42:33.965777 DQM Delay:
7038 23:42:33.969832 DQM0 = 12, DQM1 = 11
7039 23:42:33.969902 DQ Delay:
7040 23:42:33.972523 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
7041 23:42:33.976146 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7042 23:42:33.979159 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7043 23:42:33.982672 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7044 23:42:33.982741
7045 23:42:33.982801
7046 23:42:33.992264 [DQSOSCAuto] RK1, (LSB)MR18= 0x6f5f, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
7047 23:42:33.992340 CH1 RK1: MR19=C0C, MR18=6F5F
7048 23:42:33.998796 CH1_RK1: MR19=0xC0C, MR18=0x6F5F, DQSOSC=395, MR23=63, INC=378, DEC=252
7049 23:42:34.002324 [RxdqsGatingPostProcess] freq 400
7050 23:42:34.008658 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7051 23:42:34.012026 best DQS0 dly(2T, 0.5T) = (0, 10)
7052 23:42:34.015472 best DQS1 dly(2T, 0.5T) = (0, 10)
7053 23:42:34.018534 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7054 23:42:34.021918 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7055 23:42:34.025499 best DQS0 dly(2T, 0.5T) = (0, 10)
7056 23:42:34.025577 best DQS1 dly(2T, 0.5T) = (0, 10)
7057 23:42:34.028735 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7058 23:42:34.032000 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7059 23:42:34.035476 Pre-setting of DQS Precalculation
7060 23:42:34.041695 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7061 23:42:34.048432 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7062 23:42:34.055320 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7063 23:42:34.055393
7064 23:42:34.055456
7065 23:42:34.058191 [Calibration Summary] 800 Mbps
7066 23:42:34.062135 CH 0, Rank 0
7067 23:42:34.062227 SW Impedance : PASS
7068 23:42:34.065431 DUTY Scan : NO K
7069 23:42:34.065518 ZQ Calibration : PASS
7070 23:42:34.068360 Jitter Meter : NO K
7071 23:42:34.071701 CBT Training : PASS
7072 23:42:34.071784 Write leveling : PASS
7073 23:42:34.075152 RX DQS gating : PASS
7074 23:42:34.078073 RX DQ/DQS(RDDQC) : PASS
7075 23:42:34.078143 TX DQ/DQS : PASS
7076 23:42:34.081670 RX DATLAT : PASS
7077 23:42:34.084888 RX DQ/DQS(Engine): PASS
7078 23:42:34.084957 TX OE : NO K
7079 23:42:34.088054 All Pass.
7080 23:42:34.088129
7081 23:42:34.088189 CH 0, Rank 1
7082 23:42:34.091500 SW Impedance : PASS
7083 23:42:34.091574 DUTY Scan : NO K
7084 23:42:34.094758 ZQ Calibration : PASS
7085 23:42:34.097811 Jitter Meter : NO K
7086 23:42:34.097914 CBT Training : PASS
7087 23:42:34.101484 Write leveling : NO K
7088 23:42:34.104642 RX DQS gating : PASS
7089 23:42:34.104744 RX DQ/DQS(RDDQC) : PASS
7090 23:42:34.107780 TX DQ/DQS : PASS
7091 23:42:34.111264 RX DATLAT : PASS
7092 23:42:34.111360 RX DQ/DQS(Engine): PASS
7093 23:42:34.114337 TX OE : NO K
7094 23:42:34.114432 All Pass.
7095 23:42:34.114520
7096 23:42:34.117459 CH 1, Rank 0
7097 23:42:34.117529 SW Impedance : PASS
7098 23:42:34.120954 DUTY Scan : NO K
7099 23:42:34.124270 ZQ Calibration : PASS
7100 23:42:34.124340 Jitter Meter : NO K
7101 23:42:34.127474 CBT Training : PASS
7102 23:42:34.130944 Write leveling : PASS
7103 23:42:34.131012 RX DQS gating : PASS
7104 23:42:34.133910 RX DQ/DQS(RDDQC) : PASS
7105 23:42:34.137364 TX DQ/DQS : PASS
7106 23:42:34.137435 RX DATLAT : PASS
7107 23:42:34.140986 RX DQ/DQS(Engine): PASS
7108 23:42:34.141057 TX OE : NO K
7109 23:42:34.144110 All Pass.
7110 23:42:34.144180
7111 23:42:34.144241 CH 1, Rank 1
7112 23:42:34.147121 SW Impedance : PASS
7113 23:42:34.147188 DUTY Scan : NO K
7114 23:42:34.150767 ZQ Calibration : PASS
7115 23:42:34.154147 Jitter Meter : NO K
7116 23:42:34.154225 CBT Training : PASS
7117 23:42:34.157015 Write leveling : NO K
7118 23:42:34.160912 RX DQS gating : PASS
7119 23:42:34.160984 RX DQ/DQS(RDDQC) : PASS
7120 23:42:34.163605 TX DQ/DQS : PASS
7121 23:42:34.167223 RX DATLAT : PASS
7122 23:42:34.167304 RX DQ/DQS(Engine): PASS
7123 23:42:34.171053 TX OE : NO K
7124 23:42:34.171135 All Pass.
7125 23:42:34.171199
7126 23:42:34.173795 DramC Write-DBI off
7127 23:42:34.177036 PER_BANK_REFRESH: Hybrid Mode
7128 23:42:34.177118 TX_TRACKING: ON
7129 23:42:34.187369 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7130 23:42:34.190770 [FAST_K] Save calibration result to emmc
7131 23:42:34.194099 dramc_set_vcore_voltage set vcore to 725000
7132 23:42:34.196861 Read voltage for 1600, 0
7133 23:42:34.196961 Vio18 = 0
7134 23:42:34.197052 Vcore = 725000
7135 23:42:34.200252 Vdram = 0
7136 23:42:34.200328 Vddq = 0
7137 23:42:34.200390 Vmddr = 0
7138 23:42:34.206764 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7139 23:42:34.210017 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7140 23:42:34.213466 MEM_TYPE=3, freq_sel=13
7141 23:42:34.216603 sv_algorithm_assistance_LP4_3733
7142 23:42:34.220036 ============ PULL DRAM RESETB DOWN ============
7143 23:42:34.226817 ========== PULL DRAM RESETB DOWN end =========
7144 23:42:34.230088 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7145 23:42:34.233655 ===================================
7146 23:42:34.236553 LPDDR4 DRAM CONFIGURATION
7147 23:42:34.239906 ===================================
7148 23:42:34.240014 EX_ROW_EN[0] = 0x0
7149 23:42:34.243128 EX_ROW_EN[1] = 0x0
7150 23:42:34.243286 LP4Y_EN = 0x0
7151 23:42:34.246751 WORK_FSP = 0x1
7152 23:42:34.246827 WL = 0x5
7153 23:42:34.250127 RL = 0x5
7154 23:42:34.250245 BL = 0x2
7155 23:42:34.253079 RPST = 0x0
7156 23:42:34.253181 RD_PRE = 0x0
7157 23:42:34.256492 WR_PRE = 0x1
7158 23:42:34.259597 WR_PST = 0x1
7159 23:42:34.259701 DBI_WR = 0x0
7160 23:42:34.262872 DBI_RD = 0x0
7161 23:42:34.263071 OTF = 0x1
7162 23:42:34.266139 ===================================
7163 23:42:34.269451 ===================================
7164 23:42:34.272550 ANA top config
7165 23:42:34.276466 ===================================
7166 23:42:34.276575 DLL_ASYNC_EN = 0
7167 23:42:34.279181 ALL_SLAVE_EN = 0
7168 23:42:34.282494 NEW_RANK_MODE = 1
7169 23:42:34.286068 DLL_IDLE_MODE = 1
7170 23:42:34.286205 LP45_APHY_COMB_EN = 1
7171 23:42:34.289293 TX_ODT_DIS = 0
7172 23:42:34.292726 NEW_8X_MODE = 1
7173 23:42:34.296002 ===================================
7174 23:42:34.298847 ===================================
7175 23:42:34.302411 data_rate = 3200
7176 23:42:34.305965 CKR = 1
7177 23:42:34.308821 DQ_P2S_RATIO = 8
7178 23:42:34.312422 ===================================
7179 23:42:34.312524 CA_P2S_RATIO = 8
7180 23:42:34.315419 DQ_CA_OPEN = 0
7181 23:42:34.318691 DQ_SEMI_OPEN = 0
7182 23:42:34.322216 CA_SEMI_OPEN = 0
7183 23:42:34.325332 CA_FULL_RATE = 0
7184 23:42:34.328669 DQ_CKDIV4_EN = 0
7185 23:42:34.328806 CA_CKDIV4_EN = 0
7186 23:42:34.332228 CA_PREDIV_EN = 0
7187 23:42:34.335273 PH8_DLY = 12
7188 23:42:34.338531 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7189 23:42:34.341747 DQ_AAMCK_DIV = 4
7190 23:42:34.345051 CA_AAMCK_DIV = 4
7191 23:42:34.348902 CA_ADMCK_DIV = 4
7192 23:42:34.349003 DQ_TRACK_CA_EN = 0
7193 23:42:34.351799 CA_PICK = 1600
7194 23:42:34.354890 CA_MCKIO = 1600
7195 23:42:34.358899 MCKIO_SEMI = 0
7196 23:42:34.361584 PLL_FREQ = 3068
7197 23:42:34.365278 DQ_UI_PI_RATIO = 32
7198 23:42:34.368183 CA_UI_PI_RATIO = 0
7199 23:42:34.371569 ===================================
7200 23:42:34.374804 ===================================
7201 23:42:34.374876 memory_type:LPDDR4
7202 23:42:34.378308 GP_NUM : 10
7203 23:42:34.381582 SRAM_EN : 1
7204 23:42:34.381653 MD32_EN : 0
7205 23:42:34.384757 ===================================
7206 23:42:34.387723 [ANA_INIT] >>>>>>>>>>>>>>
7207 23:42:34.391011 <<<<<< [CONFIGURE PHASE]: ANA_TX
7208 23:42:34.394911 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7209 23:42:34.397627 ===================================
7210 23:42:34.400983 data_rate = 3200,PCW = 0X7600
7211 23:42:34.404583 ===================================
7212 23:42:34.407723 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7213 23:42:34.410879 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7214 23:42:34.417865 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7215 23:42:34.420923 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7216 23:42:34.424100 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7217 23:42:34.430837 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7218 23:42:34.430911 [ANA_INIT] flow start
7219 23:42:34.433984 [ANA_INIT] PLL >>>>>>>>
7220 23:42:34.437626 [ANA_INIT] PLL <<<<<<<<
7221 23:42:34.437724 [ANA_INIT] MIDPI >>>>>>>>
7222 23:42:34.440880 [ANA_INIT] MIDPI <<<<<<<<
7223 23:42:34.443976 [ANA_INIT] DLL >>>>>>>>
7224 23:42:34.444052 [ANA_INIT] DLL <<<<<<<<
7225 23:42:34.447150 [ANA_INIT] flow end
7226 23:42:34.450480 ============ LP4 DIFF to SE enter ============
7227 23:42:34.454009 ============ LP4 DIFF to SE exit ============
7228 23:42:34.457195 [ANA_INIT] <<<<<<<<<<<<<
7229 23:42:34.460573 [Flow] Enable top DCM control >>>>>
7230 23:42:34.463880 [Flow] Enable top DCM control <<<<<
7231 23:42:34.466996 Enable DLL master slave shuffle
7232 23:42:34.473991 ==============================================================
7233 23:42:34.474095 Gating Mode config
7234 23:42:34.480411 ==============================================================
7235 23:42:34.480487 Config description:
7236 23:42:34.490112 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7237 23:42:34.496793 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7238 23:42:34.503541 SELPH_MODE 0: By rank 1: By Phase
7239 23:42:34.510006 ==============================================================
7240 23:42:34.510116 GAT_TRACK_EN = 1
7241 23:42:34.513594 RX_GATING_MODE = 2
7242 23:42:34.516565 RX_GATING_TRACK_MODE = 2
7243 23:42:34.520172 SELPH_MODE = 1
7244 23:42:34.523225 PICG_EARLY_EN = 1
7245 23:42:34.526891 VALID_LAT_VALUE = 1
7246 23:42:34.533188 ==============================================================
7247 23:42:34.536390 Enter into Gating configuration >>>>
7248 23:42:34.539587 Exit from Gating configuration <<<<
7249 23:42:34.542941 Enter into DVFS_PRE_config >>>>>
7250 23:42:34.552614 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7251 23:42:34.556081 Exit from DVFS_PRE_config <<<<<
7252 23:42:34.559273 Enter into PICG configuration >>>>
7253 23:42:34.562710 Exit from PICG configuration <<<<
7254 23:42:34.566054 [RX_INPUT] configuration >>>>>
7255 23:42:34.569497 [RX_INPUT] configuration <<<<<
7256 23:42:34.572780 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7257 23:42:34.579689 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7258 23:42:34.585700 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7259 23:42:34.592851 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7260 23:42:34.596022 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7261 23:42:34.602291 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7262 23:42:34.605617 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7263 23:42:34.612283 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7264 23:42:34.615554 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7265 23:42:34.618988 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7266 23:42:34.622296 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7267 23:42:34.628487 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7268 23:42:34.631622 ===================================
7269 23:42:34.635184 LPDDR4 DRAM CONFIGURATION
7270 23:42:34.638449 ===================================
7271 23:42:34.638554 EX_ROW_EN[0] = 0x0
7272 23:42:34.642041 EX_ROW_EN[1] = 0x0
7273 23:42:34.642141 LP4Y_EN = 0x0
7274 23:42:34.645051 WORK_FSP = 0x1
7275 23:42:34.645156 WL = 0x5
7276 23:42:34.648048 RL = 0x5
7277 23:42:34.648145 BL = 0x2
7278 23:42:34.651859 RPST = 0x0
7279 23:42:34.651955 RD_PRE = 0x0
7280 23:42:34.654621 WR_PRE = 0x1
7281 23:42:34.658443 WR_PST = 0x1
7282 23:42:34.658543 DBI_WR = 0x0
7283 23:42:34.661561 DBI_RD = 0x0
7284 23:42:34.661660 OTF = 0x1
7285 23:42:34.664859 ===================================
7286 23:42:34.667889 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7287 23:42:34.674702 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7288 23:42:34.677483 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7289 23:42:34.681543 ===================================
7290 23:42:34.684296 LPDDR4 DRAM CONFIGURATION
7291 23:42:34.687445 ===================================
7292 23:42:34.687546 EX_ROW_EN[0] = 0x10
7293 23:42:34.690920 EX_ROW_EN[1] = 0x0
7294 23:42:34.690994 LP4Y_EN = 0x0
7295 23:42:34.694086 WORK_FSP = 0x1
7296 23:42:34.694204 WL = 0x5
7297 23:42:34.698105 RL = 0x5
7298 23:42:34.700814 BL = 0x2
7299 23:42:34.700912 RPST = 0x0
7300 23:42:34.704027 RD_PRE = 0x0
7301 23:42:34.704125 WR_PRE = 0x1
7302 23:42:34.707194 WR_PST = 0x1
7303 23:42:34.707289 DBI_WR = 0x0
7304 23:42:34.710342 DBI_RD = 0x0
7305 23:42:34.710412 OTF = 0x1
7306 23:42:34.713661 ===================================
7307 23:42:34.720404 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7308 23:42:34.720509 ==
7309 23:42:34.724077 Dram Type= 6, Freq= 0, CH_0, rank 0
7310 23:42:34.727065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7311 23:42:34.730253 ==
7312 23:42:34.730331 [Duty_Offset_Calibration]
7313 23:42:34.733926 B0:1 B1:-1 CA:0
7314 23:42:34.734028
7315 23:42:34.736655 [DutyScan_Calibration_Flow] k_type=0
7316 23:42:34.745820
7317 23:42:34.745929 ==CLK 0==
7318 23:42:34.748727 Final CLK duty delay cell = 0
7319 23:42:34.752619 [0] MAX Duty = 5124%(X100), DQS PI = 22
7320 23:42:34.755425 [0] MIN Duty = 4907%(X100), DQS PI = 6
7321 23:42:34.755496 [0] AVG Duty = 5015%(X100)
7322 23:42:34.759075
7323 23:42:34.762253 CH0 CLK Duty spec in!! Max-Min= 217%
7324 23:42:34.765526 [DutyScan_Calibration_Flow] ====Done====
7325 23:42:34.765625
7326 23:42:34.768859 [DutyScan_Calibration_Flow] k_type=1
7327 23:42:34.784862
7328 23:42:34.784972 ==DQS 0 ==
7329 23:42:34.788059 Final DQS duty delay cell = -4
7330 23:42:34.791398 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7331 23:42:34.794328 [-4] MIN Duty = 4844%(X100), DQS PI = 10
7332 23:42:34.797759 [-4] AVG Duty = 4922%(X100)
7333 23:42:34.797881
7334 23:42:34.797978 ==DQS 1 ==
7335 23:42:34.801044 Final DQS duty delay cell = 0
7336 23:42:34.804432 [0] MAX Duty = 5156%(X100), DQS PI = 2
7337 23:42:34.807925 [0] MIN Duty = 5000%(X100), DQS PI = 18
7338 23:42:34.811255 [0] AVG Duty = 5078%(X100)
7339 23:42:34.811358
7340 23:42:34.814620 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7341 23:42:34.814753
7342 23:42:34.817883 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7343 23:42:34.820781 [DutyScan_Calibration_Flow] ====Done====
7344 23:42:34.820882
7345 23:42:34.823950 [DutyScan_Calibration_Flow] k_type=3
7346 23:42:34.842083
7347 23:42:34.842225 ==DQM 0 ==
7348 23:42:34.845373 Final DQM duty delay cell = 0
7349 23:42:34.848789 [0] MAX Duty = 5093%(X100), DQS PI = 18
7350 23:42:34.852142 [0] MIN Duty = 4875%(X100), DQS PI = 10
7351 23:42:34.855628 [0] AVG Duty = 4984%(X100)
7352 23:42:34.855726
7353 23:42:34.855817 ==DQM 1 ==
7354 23:42:34.858686 Final DQM duty delay cell = 0
7355 23:42:34.862085 [0] MAX Duty = 5000%(X100), DQS PI = 4
7356 23:42:34.865721 [0] MIN Duty = 4813%(X100), DQS PI = 20
7357 23:42:34.868905 [0] AVG Duty = 4906%(X100)
7358 23:42:34.869006
7359 23:42:34.872264 CH0 DQM 0 Duty spec in!! Max-Min= 218%
7360 23:42:34.872361
7361 23:42:34.875844 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7362 23:42:34.878718 [DutyScan_Calibration_Flow] ====Done====
7363 23:42:34.878790
7364 23:42:34.882275 [DutyScan_Calibration_Flow] k_type=2
7365 23:42:34.898437
7366 23:42:34.898587 ==DQ 0 ==
7367 23:42:34.901614 Final DQ duty delay cell = -4
7368 23:42:34.905278 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7369 23:42:34.908693 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7370 23:42:34.911766 [-4] AVG Duty = 4953%(X100)
7371 23:42:34.911868
7372 23:42:34.911959 ==DQ 1 ==
7373 23:42:34.915416 Final DQ duty delay cell = 0
7374 23:42:34.918523 [0] MAX Duty = 5125%(X100), DQS PI = 48
7375 23:42:34.921551 [0] MIN Duty = 5000%(X100), DQS PI = 36
7376 23:42:34.924948 [0] AVG Duty = 5062%(X100)
7377 23:42:34.925046
7378 23:42:34.928262 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7379 23:42:34.928357
7380 23:42:34.931428 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7381 23:42:34.935131 [DutyScan_Calibration_Flow] ====Done====
7382 23:42:34.935231 ==
7383 23:42:34.938247 Dram Type= 6, Freq= 0, CH_1, rank 0
7384 23:42:34.941639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7385 23:42:34.941738 ==
7386 23:42:34.944898 [Duty_Offset_Calibration]
7387 23:42:34.944996 B0:-1 B1:1 CA:1
7388 23:42:34.945087
7389 23:42:34.948412 [DutyScan_Calibration_Flow] k_type=0
7390 23:42:34.959233
7391 23:42:34.959328 ==CLK 0==
7392 23:42:34.962875 Final CLK duty delay cell = 0
7393 23:42:34.965809 [0] MAX Duty = 5187%(X100), DQS PI = 22
7394 23:42:34.969671 [0] MIN Duty = 5000%(X100), DQS PI = 0
7395 23:42:34.969775 [0] AVG Duty = 5093%(X100)
7396 23:42:34.972502
7397 23:42:34.975475 CH1 CLK Duty spec in!! Max-Min= 187%
7398 23:42:34.979296 [DutyScan_Calibration_Flow] ====Done====
7399 23:42:34.979370
7400 23:42:34.982300 [DutyScan_Calibration_Flow] k_type=1
7401 23:42:34.999048
7402 23:42:34.999162 ==DQS 0 ==
7403 23:42:35.002109 Final DQS duty delay cell = 0
7404 23:42:35.005459 [0] MAX Duty = 5124%(X100), DQS PI = 18
7405 23:42:35.009290 [0] MIN Duty = 4938%(X100), DQS PI = 8
7406 23:42:35.011971 [0] AVG Duty = 5031%(X100)
7407 23:42:35.012092
7408 23:42:35.012218 ==DQS 1 ==
7409 23:42:35.015357 Final DQS duty delay cell = 0
7410 23:42:35.018549 [0] MAX Duty = 5093%(X100), DQS PI = 24
7411 23:42:35.022374 [0] MIN Duty = 4969%(X100), DQS PI = 54
7412 23:42:35.025830 [0] AVG Duty = 5031%(X100)
7413 23:42:35.025936
7414 23:42:35.028792 CH1 DQS 0 Duty spec in!! Max-Min= 186%
7415 23:42:35.028934
7416 23:42:35.031820 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7417 23:42:35.035259 [DutyScan_Calibration_Flow] ====Done====
7418 23:42:35.035330
7419 23:42:35.038758 [DutyScan_Calibration_Flow] k_type=3
7420 23:42:35.055619
7421 23:42:35.055740 ==DQM 0 ==
7422 23:42:35.059450 Final DQM duty delay cell = 0
7423 23:42:35.062601 [0] MAX Duty = 5218%(X100), DQS PI = 18
7424 23:42:35.065734 [0] MIN Duty = 5031%(X100), DQS PI = 8
7425 23:42:35.069203 [0] AVG Duty = 5124%(X100)
7426 23:42:35.069282
7427 23:42:35.069359 ==DQM 1 ==
7428 23:42:35.072475 Final DQM duty delay cell = 0
7429 23:42:35.075561 [0] MAX Duty = 5156%(X100), DQS PI = 8
7430 23:42:35.078696 [0] MIN Duty = 4938%(X100), DQS PI = 34
7431 23:42:35.082244 [0] AVG Duty = 5047%(X100)
7432 23:42:35.082367
7433 23:42:35.085569 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7434 23:42:35.085646
7435 23:42:35.088436 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7436 23:42:35.092474 [DutyScan_Calibration_Flow] ====Done====
7437 23:42:35.092553
7438 23:42:35.095526 [DutyScan_Calibration_Flow] k_type=2
7439 23:42:35.112657
7440 23:42:35.112775 ==DQ 0 ==
7441 23:42:35.115660 Final DQ duty delay cell = 0
7442 23:42:35.119219 [0] MAX Duty = 5156%(X100), DQS PI = 30
7443 23:42:35.122507 [0] MIN Duty = 4906%(X100), DQS PI = 8
7444 23:42:35.122620 [0] AVG Duty = 5031%(X100)
7445 23:42:35.122721
7446 23:42:35.125939 ==DQ 1 ==
7447 23:42:35.129096 Final DQ duty delay cell = 0
7448 23:42:35.132482 [0] MAX Duty = 5156%(X100), DQS PI = 8
7449 23:42:35.135952 [0] MIN Duty = 4969%(X100), DQS PI = 56
7450 23:42:35.136028 [0] AVG Duty = 5062%(X100)
7451 23:42:35.136091
7452 23:42:35.142224 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7453 23:42:35.142324
7454 23:42:35.145709 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7455 23:42:35.148926 [DutyScan_Calibration_Flow] ====Done====
7456 23:42:35.151980 nWR fixed to 30
7457 23:42:35.152077 [ModeRegInit_LP4] CH0 RK0
7458 23:42:35.155317 [ModeRegInit_LP4] CH0 RK1
7459 23:42:35.158596 [ModeRegInit_LP4] CH1 RK0
7460 23:42:35.161875 [ModeRegInit_LP4] CH1 RK1
7461 23:42:35.161974 match AC timing 5
7462 23:42:35.168463 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7463 23:42:35.172160 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7464 23:42:35.175495 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7465 23:42:35.181868 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7466 23:42:35.185090 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7467 23:42:35.185202 [MiockJmeterHQA]
7468 23:42:35.185325
7469 23:42:35.188508 [DramcMiockJmeter] u1RxGatingPI = 0
7470 23:42:35.191969 0 : 4257, 4030
7471 23:42:35.192076 4 : 4252, 4027
7472 23:42:35.194839 8 : 4368, 4140
7473 23:42:35.194943 12 : 4257, 4029
7474 23:42:35.195031 16 : 4368, 4140
7475 23:42:35.198772 20 : 4252, 4027
7476 23:42:35.198875 24 : 4360, 4138
7477 23:42:35.201718 28 : 4252, 4027
7478 23:42:35.201823 32 : 4250, 4027
7479 23:42:35.204805 36 : 4250, 4027
7480 23:42:35.204908 40 : 4363, 4137
7481 23:42:35.208022 44 : 4361, 4137
7482 23:42:35.208156 48 : 4252, 4027
7483 23:42:35.208265 52 : 4250, 4027
7484 23:42:35.211587 56 : 4250, 4027
7485 23:42:35.211693 60 : 4249, 4027
7486 23:42:35.214792 64 : 4250, 4027
7487 23:42:35.214909 68 : 4361, 4138
7488 23:42:35.218152 72 : 4250, 4027
7489 23:42:35.218249 76 : 4250, 4027
7490 23:42:35.221500 80 : 4252, 4027
7491 23:42:35.221604 84 : 4250, 4027
7492 23:42:35.221698 88 : 4250, 4027
7493 23:42:35.224866 92 : 4361, 363
7494 23:42:35.224970 96 : 4250, 0
7495 23:42:35.228442 100 : 4360, 0
7496 23:42:35.228588 104 : 4365, 0
7497 23:42:35.228685 108 : 4250, 0
7498 23:42:35.231542 112 : 4250, 0
7499 23:42:35.231617 116 : 4252, 0
7500 23:42:35.234760 120 : 4250, 0
7501 23:42:35.234864 124 : 4250, 0
7502 23:42:35.234957 128 : 4250, 0
7503 23:42:35.238216 132 : 4250, 0
7504 23:42:35.238291 136 : 4250, 0
7505 23:42:35.241213 140 : 4252, 0
7506 23:42:35.241310 144 : 4360, 0
7507 23:42:35.241405 148 : 4360, 0
7508 23:42:35.244701 152 : 4250, 0
7509 23:42:35.244801 156 : 4250, 0
7510 23:42:35.247927 160 : 4360, 0
7511 23:42:35.248003 164 : 4250, 0
7512 23:42:35.248066 168 : 4250, 0
7513 23:42:35.251035 172 : 4249, 0
7514 23:42:35.251133 176 : 4250, 0
7515 23:42:35.251200 180 : 4250, 0
7516 23:42:35.254743 184 : 4251, 0
7517 23:42:35.254851 188 : 4250, 0
7518 23:42:35.257990 192 : 4250, 0
7519 23:42:35.258091 196 : 4363, 0
7520 23:42:35.258192 200 : 4361, 0
7521 23:42:35.261360 204 : 4361, 0
7522 23:42:35.261464 208 : 4250, 0
7523 23:42:35.264487 212 : 4249, 0
7524 23:42:35.264592 216 : 4250, 0
7525 23:42:35.264688 220 : 4253, 0
7526 23:42:35.268234 224 : 4249, 306
7527 23:42:35.268339 228 : 4250, 3516
7528 23:42:35.271119 232 : 4360, 4138
7529 23:42:35.271219 236 : 4361, 4137
7530 23:42:35.274252 240 : 4250, 4027
7531 23:42:35.274357 244 : 4250, 4026
7532 23:42:35.277499 248 : 4361, 4137
7533 23:42:35.277600 252 : 4250, 4027
7534 23:42:35.281138 256 : 4249, 4027
7535 23:42:35.281240 260 : 4250, 4026
7536 23:42:35.284548 264 : 4250, 4027
7537 23:42:35.284653 268 : 4250, 4027
7538 23:42:35.284747 272 : 4250, 4027
7539 23:42:35.287446 276 : 4360, 4137
7540 23:42:35.287554 280 : 4250, 4027
7541 23:42:35.290787 284 : 4250, 4027
7542 23:42:35.290894 288 : 4361, 4138
7543 23:42:35.294152 292 : 4249, 4027
7544 23:42:35.294243 296 : 4250, 4026
7545 23:42:35.297274 300 : 4361, 4137
7546 23:42:35.297382 304 : 4250, 4027
7547 23:42:35.300468 308 : 4249, 4027
7548 23:42:35.300585 312 : 4253, 4029
7549 23:42:35.303728 316 : 4250, 4027
7550 23:42:35.303835 320 : 4250, 4027
7551 23:42:35.307215 324 : 4250, 4027
7552 23:42:35.307322 328 : 4360, 4137
7553 23:42:35.310500 332 : 4250, 4027
7554 23:42:35.310606 336 : 4250, 3852
7555 23:42:35.310712 340 : 4361, 1920
7556 23:42:35.314240
7557 23:42:35.314342 MIOCK jitter meter ch=0
7558 23:42:35.314437
7559 23:42:35.317144 1T = (340-92) = 248 dly cells
7560 23:42:35.323821 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7561 23:42:35.323927 ==
7562 23:42:35.326737 Dram Type= 6, Freq= 0, CH_0, rank 0
7563 23:42:35.330573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7564 23:42:35.330653 ==
7565 23:42:35.337588 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7566 23:42:35.340109 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7567 23:42:35.343504 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7568 23:42:35.349920 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7569 23:42:35.359609 [CA 0] Center 43 (13~74) winsize 62
7570 23:42:35.362777 [CA 1] Center 42 (12~73) winsize 62
7571 23:42:35.366178 [CA 2] Center 38 (9~68) winsize 60
7572 23:42:35.369601 [CA 3] Center 38 (8~68) winsize 61
7573 23:42:35.372483 [CA 4] Center 36 (7~66) winsize 60
7574 23:42:35.375745 [CA 5] Center 35 (6~65) winsize 60
7575 23:42:35.375826
7576 23:42:35.379029 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7577 23:42:35.379108
7578 23:42:35.385759 [CATrainingPosCal] consider 1 rank data
7579 23:42:35.385876 u2DelayCellTimex100 = 262/100 ps
7580 23:42:35.392286 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7581 23:42:35.395714 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7582 23:42:35.399011 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7583 23:42:35.402154 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7584 23:42:35.405251 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7585 23:42:35.409246 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7586 23:42:35.409359
7587 23:42:35.412024 CA PerBit enable=1, Macro0, CA PI delay=35
7588 23:42:35.412103
7589 23:42:35.415327 [CBTSetCACLKResult] CA Dly = 35
7590 23:42:35.418615 CS Dly: 11 (0~42)
7591 23:42:35.422268 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7592 23:42:35.425181 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7593 23:42:35.425264 ==
7594 23:42:35.428573 Dram Type= 6, Freq= 0, CH_0, rank 1
7595 23:42:35.435278 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7596 23:42:35.435371 ==
7597 23:42:35.438559 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7598 23:42:35.445051 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7599 23:42:35.447947 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7600 23:42:35.454573 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7601 23:42:35.463047 [CA 0] Center 43 (13~74) winsize 62
7602 23:42:35.466431 [CA 1] Center 44 (14~74) winsize 61
7603 23:42:35.469617 [CA 2] Center 38 (9~68) winsize 60
7604 23:42:35.472906 [CA 3] Center 38 (9~68) winsize 60
7605 23:42:35.476052 [CA 4] Center 36 (7~66) winsize 60
7606 23:42:35.479528 [CA 5] Center 36 (6~66) winsize 61
7607 23:42:35.479602
7608 23:42:35.482730 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7609 23:42:35.482807
7610 23:42:35.489657 [CATrainingPosCal] consider 2 rank data
7611 23:42:35.489773 u2DelayCellTimex100 = 262/100 ps
7612 23:42:35.495878 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7613 23:42:35.499617 CA1 delay=43 (14~73),Diff = 8 PI (29 cell)
7614 23:42:35.502887 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7615 23:42:35.506233 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7616 23:42:35.509145 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7617 23:42:35.512675 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7618 23:42:35.512779
7619 23:42:35.516202 CA PerBit enable=1, Macro0, CA PI delay=35
7620 23:42:35.516313
7621 23:42:35.519447 [CBTSetCACLKResult] CA Dly = 35
7622 23:42:35.522682 CS Dly: 12 (0~44)
7623 23:42:35.525634 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7624 23:42:35.529005 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7625 23:42:35.529108
7626 23:42:35.532219 ----->DramcWriteLeveling(PI) begin...
7627 23:42:35.532321 ==
7628 23:42:35.535459 Dram Type= 6, Freq= 0, CH_0, rank 0
7629 23:42:35.542113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7630 23:42:35.542231 ==
7631 23:42:35.545716 Write leveling (Byte 0): 34 => 34
7632 23:42:35.548753 Write leveling (Byte 1): 27 => 27
7633 23:42:35.552215 DramcWriteLeveling(PI) end<-----
7634 23:42:35.552327
7635 23:42:35.552423 ==
7636 23:42:35.555409 Dram Type= 6, Freq= 0, CH_0, rank 0
7637 23:42:35.558758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7638 23:42:35.558859 ==
7639 23:42:35.562233 [Gating] SW mode calibration
7640 23:42:35.568610 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7641 23:42:35.575164 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7642 23:42:35.578854 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 23:42:35.581621 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7644 23:42:35.588256 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7645 23:42:35.591346 1 4 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7646 23:42:35.595312 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7647 23:42:35.601529 1 4 20 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7648 23:42:35.604977 1 4 24 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
7649 23:42:35.608381 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7650 23:42:35.614945 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7651 23:42:35.617780 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7652 23:42:35.621433 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7653 23:42:35.627788 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7654 23:42:35.631881 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7655 23:42:35.634430 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7656 23:42:35.641071 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7657 23:42:35.644260 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7658 23:42:35.648101 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7659 23:42:35.654325 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7660 23:42:35.657472 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7661 23:42:35.660925 1 6 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7662 23:42:35.668067 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7663 23:42:35.671077 1 6 20 | B1->B0 | 302f 4646 | 1 0 | (0 0) (0 0)
7664 23:42:35.674071 1 6 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7665 23:42:35.680633 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7666 23:42:35.684404 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7667 23:42:35.687449 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 23:42:35.693657 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7669 23:42:35.697004 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7670 23:42:35.700231 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7671 23:42:35.706850 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7672 23:42:35.710294 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7673 23:42:35.713648 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 23:42:35.720472 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 23:42:35.723589 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 23:42:35.726806 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 23:42:35.729963 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 23:42:35.736532 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 23:42:35.739964 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 23:42:35.743247 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7681 23:42:35.749947 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7682 23:42:35.753344 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7683 23:42:35.756542 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 23:42:35.763120 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 23:42:35.766343 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7686 23:42:35.769477 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7687 23:42:35.773015 Total UI for P1: 0, mck2ui 16
7688 23:42:35.776361 best dqsien dly found for B0: ( 1, 9, 12)
7689 23:42:35.782899 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7690 23:42:35.786129 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7691 23:42:35.789353 Total UI for P1: 0, mck2ui 16
7692 23:42:35.793182 best dqsien dly found for B1: ( 1, 9, 18)
7693 23:42:35.796065 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7694 23:42:35.799538 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7695 23:42:35.799645
7696 23:42:35.802707 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7697 23:42:35.809429 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7698 23:42:35.809537 [Gating] SW calibration Done
7699 23:42:35.812453 ==
7700 23:42:35.815540 Dram Type= 6, Freq= 0, CH_0, rank 0
7701 23:42:35.819187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7702 23:42:35.819262 ==
7703 23:42:35.819326 RX Vref Scan: 0
7704 23:42:35.819386
7705 23:42:35.822115 RX Vref 0 -> 0, step: 1
7706 23:42:35.822208
7707 23:42:35.825696 RX Delay 0 -> 252, step: 8
7708 23:42:35.829003 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7709 23:42:35.832292 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7710 23:42:35.835475 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7711 23:42:35.842044 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7712 23:42:35.845852 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7713 23:42:35.848778 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7714 23:42:35.851780 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7715 23:42:35.855318 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7716 23:42:35.862197 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7717 23:42:35.865482 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7718 23:42:35.868840 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7719 23:42:35.871649 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7720 23:42:35.878215 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7721 23:42:35.881658 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7722 23:42:35.885230 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7723 23:42:35.888069 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7724 23:42:35.888155 ==
7725 23:42:35.891531 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 23:42:35.897870 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 23:42:35.897985 ==
7728 23:42:35.898081 DQS Delay:
7729 23:42:35.898188 DQS0 = 0, DQS1 = 0
7730 23:42:35.901232 DQM Delay:
7731 23:42:35.901322 DQM0 = 136, DQM1 = 125
7732 23:42:35.904567 DQ Delay:
7733 23:42:35.907963 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7734 23:42:35.911560 DQ4 =135, DQ5 =123, DQ6 =147, DQ7 =147
7735 23:42:35.914565 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7736 23:42:35.917580 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7737 23:42:35.917693
7738 23:42:35.917787
7739 23:42:35.917885 ==
7740 23:42:35.921224 Dram Type= 6, Freq= 0, CH_0, rank 0
7741 23:42:35.928008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7742 23:42:35.928121 ==
7743 23:42:35.928222
7744 23:42:35.928315
7745 23:42:35.928405 TX Vref Scan disable
7746 23:42:35.930781 == TX Byte 0 ==
7747 23:42:35.934084 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7748 23:42:35.940897 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7749 23:42:35.941006 == TX Byte 1 ==
7750 23:42:35.944024 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7751 23:42:35.950620 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7752 23:42:35.950708 ==
7753 23:42:35.954147 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 23:42:35.957013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 23:42:35.957114 ==
7756 23:42:35.970180
7757 23:42:35.973364 TX Vref early break, caculate TX vref
7758 23:42:35.977135 TX Vref=16, minBit 1, minWin=23, winSum=375
7759 23:42:35.980189 TX Vref=18, minBit 0, minWin=23, winSum=385
7760 23:42:35.983956 TX Vref=20, minBit 4, minWin=23, winSum=389
7761 23:42:35.986630 TX Vref=22, minBit 3, minWin=24, winSum=400
7762 23:42:35.989980 TX Vref=24, minBit 1, minWin=24, winSum=406
7763 23:42:35.996694 TX Vref=26, minBit 1, minWin=25, winSum=412
7764 23:42:35.999811 TX Vref=28, minBit 4, minWin=25, winSum=417
7765 23:42:36.003216 TX Vref=30, minBit 5, minWin=24, winSum=406
7766 23:42:36.006333 TX Vref=32, minBit 4, minWin=23, winSum=397
7767 23:42:36.009884 TX Vref=34, minBit 4, minWin=23, winSum=385
7768 23:42:36.016384 [TxChooseVref] Worse bit 4, Min win 25, Win sum 417, Final Vref 28
7769 23:42:36.016493
7770 23:42:36.019531 Final TX Range 0 Vref 28
7771 23:42:36.019626
7772 23:42:36.019713 ==
7773 23:42:36.023011 Dram Type= 6, Freq= 0, CH_0, rank 0
7774 23:42:36.026456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7775 23:42:36.026560 ==
7776 23:42:36.026656
7777 23:42:36.026757
7778 23:42:36.029325 TX Vref Scan disable
7779 23:42:36.036390 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7780 23:42:36.036505 == TX Byte 0 ==
7781 23:42:36.039891 u2DelayCellOfst[0]=14 cells (4 PI)
7782 23:42:36.042578 u2DelayCellOfst[1]=18 cells (5 PI)
7783 23:42:36.046018 u2DelayCellOfst[2]=14 cells (4 PI)
7784 23:42:36.049197 u2DelayCellOfst[3]=14 cells (4 PI)
7785 23:42:36.052442 u2DelayCellOfst[4]=11 cells (3 PI)
7786 23:42:36.056030 u2DelayCellOfst[5]=0 cells (0 PI)
7787 23:42:36.059108 u2DelayCellOfst[6]=18 cells (5 PI)
7788 23:42:36.062522 u2DelayCellOfst[7]=22 cells (6 PI)
7789 23:42:36.065732 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7790 23:42:36.069070 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7791 23:42:36.072433 == TX Byte 1 ==
7792 23:42:36.075556 u2DelayCellOfst[8]=0 cells (0 PI)
7793 23:42:36.079149 u2DelayCellOfst[9]=3 cells (1 PI)
7794 23:42:36.082220 u2DelayCellOfst[10]=7 cells (2 PI)
7795 23:42:36.085613 u2DelayCellOfst[11]=3 cells (1 PI)
7796 23:42:36.085699 u2DelayCellOfst[12]=11 cells (3 PI)
7797 23:42:36.088755 u2DelayCellOfst[13]=11 cells (3 PI)
7798 23:42:36.092119 u2DelayCellOfst[14]=18 cells (5 PI)
7799 23:42:36.095457 u2DelayCellOfst[15]=11 cells (3 PI)
7800 23:42:36.102443 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7801 23:42:36.105215 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7802 23:42:36.105293 DramC Write-DBI on
7803 23:42:36.108666 ==
7804 23:42:36.111823 Dram Type= 6, Freq= 0, CH_0, rank 0
7805 23:42:36.115090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7806 23:42:36.115175 ==
7807 23:42:36.115261
7808 23:42:36.115391
7809 23:42:36.118794 TX Vref Scan disable
7810 23:42:36.118894 == TX Byte 0 ==
7811 23:42:36.125179 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7812 23:42:36.125266 == TX Byte 1 ==
7813 23:42:36.128476 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7814 23:42:36.131631 DramC Write-DBI off
7815 23:42:36.131716
7816 23:42:36.131837 [DATLAT]
7817 23:42:36.134876 Freq=1600, CH0 RK0
7818 23:42:36.134962
7819 23:42:36.135047 DATLAT Default: 0xf
7820 23:42:36.138486 0, 0xFFFF, sum = 0
7821 23:42:36.138576 1, 0xFFFF, sum = 0
7822 23:42:36.141446 2, 0xFFFF, sum = 0
7823 23:42:36.144540 3, 0xFFFF, sum = 0
7824 23:42:36.144627 4, 0xFFFF, sum = 0
7825 23:42:36.147929 5, 0xFFFF, sum = 0
7826 23:42:36.148015 6, 0xFFFF, sum = 0
7827 23:42:36.151554 7, 0xFFFF, sum = 0
7828 23:42:36.151641 8, 0xFFFF, sum = 0
7829 23:42:36.154883 9, 0xFFFF, sum = 0
7830 23:42:36.154970 10, 0xFFFF, sum = 0
7831 23:42:36.157754 11, 0xFFFF, sum = 0
7832 23:42:36.157840 12, 0xFFFF, sum = 0
7833 23:42:36.161159 13, 0xFFFF, sum = 0
7834 23:42:36.161246 14, 0x0, sum = 1
7835 23:42:36.165086 15, 0x0, sum = 2
7836 23:42:36.165190 16, 0x0, sum = 3
7837 23:42:36.168016 17, 0x0, sum = 4
7838 23:42:36.168102 best_step = 15
7839 23:42:36.168189
7840 23:42:36.168272 ==
7841 23:42:36.171078 Dram Type= 6, Freq= 0, CH_0, rank 0
7842 23:42:36.174586 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7843 23:42:36.177840 ==
7844 23:42:36.177925 RX Vref Scan: 1
7845 23:42:36.178011
7846 23:42:36.181223 Set Vref Range= 24 -> 127
7847 23:42:36.181308
7848 23:42:36.184859 RX Vref 24 -> 127, step: 1
7849 23:42:36.184944
7850 23:42:36.185029 RX Delay 11 -> 252, step: 4
7851 23:42:36.185124
7852 23:42:36.188144 Set Vref, RX VrefLevel [Byte0]: 24
7853 23:42:36.190771 [Byte1]: 24
7854 23:42:36.194786
7855 23:42:36.194871 Set Vref, RX VrefLevel [Byte0]: 25
7856 23:42:36.198140 [Byte1]: 25
7857 23:42:36.202767
7858 23:42:36.202888 Set Vref, RX VrefLevel [Byte0]: 26
7859 23:42:36.205892 [Byte1]: 26
7860 23:42:36.209974
7861 23:42:36.210058 Set Vref, RX VrefLevel [Byte0]: 27
7862 23:42:36.213455 [Byte1]: 27
7863 23:42:36.218110
7864 23:42:36.218230 Set Vref, RX VrefLevel [Byte0]: 28
7865 23:42:36.221434 [Byte1]: 28
7866 23:42:36.225472
7867 23:42:36.225557 Set Vref, RX VrefLevel [Byte0]: 29
7868 23:42:36.228726 [Byte1]: 29
7869 23:42:36.233256
7870 23:42:36.233394 Set Vref, RX VrefLevel [Byte0]: 30
7871 23:42:36.236670 [Byte1]: 30
7872 23:42:36.240941
7873 23:42:36.241049 Set Vref, RX VrefLevel [Byte0]: 31
7874 23:42:36.244216 [Byte1]: 31
7875 23:42:36.248180
7876 23:42:36.248280 Set Vref, RX VrefLevel [Byte0]: 32
7877 23:42:36.251457 [Byte1]: 32
7878 23:42:36.255848
7879 23:42:36.255931 Set Vref, RX VrefLevel [Byte0]: 33
7880 23:42:36.262126 [Byte1]: 33
7881 23:42:36.262254
7882 23:42:36.265606 Set Vref, RX VrefLevel [Byte0]: 34
7883 23:42:36.268953 [Byte1]: 34
7884 23:42:36.269065
7885 23:42:36.272564 Set Vref, RX VrefLevel [Byte0]: 35
7886 23:42:36.276338 [Byte1]: 35
7887 23:42:36.278769
7888 23:42:36.278850 Set Vref, RX VrefLevel [Byte0]: 36
7889 23:42:36.282278 [Byte1]: 36
7890 23:42:36.286849
7891 23:42:36.286975 Set Vref, RX VrefLevel [Byte0]: 37
7892 23:42:36.289442 [Byte1]: 37
7893 23:42:36.293973
7894 23:42:36.294079 Set Vref, RX VrefLevel [Byte0]: 38
7895 23:42:36.297214 [Byte1]: 38
7896 23:42:36.301635
7897 23:42:36.301752 Set Vref, RX VrefLevel [Byte0]: 39
7898 23:42:36.304829 [Byte1]: 39
7899 23:42:36.309011
7900 23:42:36.309110 Set Vref, RX VrefLevel [Byte0]: 40
7901 23:42:36.312488 [Byte1]: 40
7902 23:42:36.316543
7903 23:42:36.316640 Set Vref, RX VrefLevel [Byte0]: 41
7904 23:42:36.320525 [Byte1]: 41
7905 23:42:36.324221
7906 23:42:36.324319 Set Vref, RX VrefLevel [Byte0]: 42
7907 23:42:36.328065 [Byte1]: 42
7908 23:42:36.332300
7909 23:42:36.332398 Set Vref, RX VrefLevel [Byte0]: 43
7910 23:42:36.335388 [Byte1]: 43
7911 23:42:36.339719
7912 23:42:36.339830 Set Vref, RX VrefLevel [Byte0]: 44
7913 23:42:36.343172 [Byte1]: 44
7914 23:42:36.347483
7915 23:42:36.347558 Set Vref, RX VrefLevel [Byte0]: 45
7916 23:42:36.350765 [Byte1]: 45
7917 23:42:36.354536
7918 23:42:36.354608 Set Vref, RX VrefLevel [Byte0]: 46
7919 23:42:36.358411 [Byte1]: 46
7920 23:42:36.362697
7921 23:42:36.362773 Set Vref, RX VrefLevel [Byte0]: 47
7922 23:42:36.366073 [Byte1]: 47
7923 23:42:36.370196
7924 23:42:36.370296 Set Vref, RX VrefLevel [Byte0]: 48
7925 23:42:36.373107 [Byte1]: 48
7926 23:42:36.377516
7927 23:42:36.377614 Set Vref, RX VrefLevel [Byte0]: 49
7928 23:42:36.381074 [Byte1]: 49
7929 23:42:36.385343
7930 23:42:36.385449 Set Vref, RX VrefLevel [Byte0]: 50
7931 23:42:36.388359 [Byte1]: 50
7932 23:42:36.393203
7933 23:42:36.393280 Set Vref, RX VrefLevel [Byte0]: 51
7934 23:42:36.396570 [Byte1]: 51
7935 23:42:36.400708
7936 23:42:36.400816 Set Vref, RX VrefLevel [Byte0]: 52
7937 23:42:36.404108 [Byte1]: 52
7938 23:42:36.408372
7939 23:42:36.408474 Set Vref, RX VrefLevel [Byte0]: 53
7940 23:42:36.411526 [Byte1]: 53
7941 23:42:36.415606
7942 23:42:36.415718 Set Vref, RX VrefLevel [Byte0]: 54
7943 23:42:36.418836 [Byte1]: 54
7944 23:42:36.423379
7945 23:42:36.423461 Set Vref, RX VrefLevel [Byte0]: 55
7946 23:42:36.426712 [Byte1]: 55
7947 23:42:36.431116
7948 23:42:36.431218 Set Vref, RX VrefLevel [Byte0]: 56
7949 23:42:36.434344 [Byte1]: 56
7950 23:42:36.439037
7951 23:42:36.439117 Set Vref, RX VrefLevel [Byte0]: 57
7952 23:42:36.442062 [Byte1]: 57
7953 23:42:36.446101
7954 23:42:36.446207 Set Vref, RX VrefLevel [Byte0]: 58
7955 23:42:36.449394 [Byte1]: 58
7956 23:42:36.453825
7957 23:42:36.453907 Set Vref, RX VrefLevel [Byte0]: 59
7958 23:42:36.456898 [Byte1]: 59
7959 23:42:36.461440
7960 23:42:36.461522 Set Vref, RX VrefLevel [Byte0]: 60
7961 23:42:36.464647 [Byte1]: 60
7962 23:42:36.469115
7963 23:42:36.469202 Set Vref, RX VrefLevel [Byte0]: 61
7964 23:42:36.472129 [Byte1]: 61
7965 23:42:36.476650
7966 23:42:36.476757 Set Vref, RX VrefLevel [Byte0]: 62
7967 23:42:36.480049 [Byte1]: 62
7968 23:42:36.484320
7969 23:42:36.484408 Set Vref, RX VrefLevel [Byte0]: 63
7970 23:42:36.487474 [Byte1]: 63
7971 23:42:36.491817
7972 23:42:36.491902 Set Vref, RX VrefLevel [Byte0]: 64
7973 23:42:36.495617 [Byte1]: 64
7974 23:42:36.499347
7975 23:42:36.499431 Set Vref, RX VrefLevel [Byte0]: 65
7976 23:42:36.502639 [Byte1]: 65
7977 23:42:36.506929
7978 23:42:36.507014 Set Vref, RX VrefLevel [Byte0]: 66
7979 23:42:36.510693 [Byte1]: 66
7980 23:42:36.515221
7981 23:42:36.515305 Set Vref, RX VrefLevel [Byte0]: 67
7982 23:42:36.517939 [Byte1]: 67
7983 23:42:36.522634
7984 23:42:36.522732 Set Vref, RX VrefLevel [Byte0]: 68
7985 23:42:36.525587 [Byte1]: 68
7986 23:42:36.530340
7987 23:42:36.530419 Set Vref, RX VrefLevel [Byte0]: 69
7988 23:42:36.533317 [Byte1]: 69
7989 23:42:36.537541
7990 23:42:36.537615 Set Vref, RX VrefLevel [Byte0]: 70
7991 23:42:36.540941 [Byte1]: 70
7992 23:42:36.545352
7993 23:42:36.545430 Set Vref, RX VrefLevel [Byte0]: 71
7994 23:42:36.548891 [Byte1]: 71
7995 23:42:36.552859
7996 23:42:36.552939 Set Vref, RX VrefLevel [Byte0]: 72
7997 23:42:36.555964 [Byte1]: 72
7998 23:42:36.560524
7999 23:42:36.560624 Set Vref, RX VrefLevel [Byte0]: 73
8000 23:42:36.563651 [Byte1]: 73
8001 23:42:36.568174
8002 23:42:36.568256 Set Vref, RX VrefLevel [Byte0]: 74
8003 23:42:36.571246 [Byte1]: 74
8004 23:42:36.575574
8005 23:42:36.575657 Set Vref, RX VrefLevel [Byte0]: 75
8006 23:42:36.578780 [Byte1]: 75
8007 23:42:36.583050
8008 23:42:36.583133 Set Vref, RX VrefLevel [Byte0]: 76
8009 23:42:36.586588 [Byte1]: 76
8010 23:42:36.590741
8011 23:42:36.590834 Set Vref, RX VrefLevel [Byte0]: 77
8012 23:42:36.594078 [Byte1]: 77
8013 23:42:36.598770
8014 23:42:36.598875 Set Vref, RX VrefLevel [Byte0]: 78
8015 23:42:36.601574 [Byte1]: 78
8016 23:42:36.605797
8017 23:42:36.605902 Final RX Vref Byte 0 = 65 to rank0
8018 23:42:36.609801 Final RX Vref Byte 1 = 58 to rank0
8019 23:42:36.612664 Final RX Vref Byte 0 = 65 to rank1
8020 23:42:36.616142 Final RX Vref Byte 1 = 58 to rank1==
8021 23:42:36.619476 Dram Type= 6, Freq= 0, CH_0, rank 0
8022 23:42:36.626288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8023 23:42:36.626373 ==
8024 23:42:36.626439 DQS Delay:
8025 23:42:36.626499 DQS0 = 0, DQS1 = 0
8026 23:42:36.629119 DQM Delay:
8027 23:42:36.629216 DQM0 = 133, DQM1 = 122
8028 23:42:36.632601 DQ Delay:
8029 23:42:36.635534 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8030 23:42:36.639164 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8031 23:42:36.642601 DQ8 =114, DQ9 =110, DQ10 =122, DQ11 =116
8032 23:42:36.645612 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
8033 23:42:36.645696
8034 23:42:36.645767
8035 23:42:36.645858
8036 23:42:36.649061 [DramC_TX_OE_Calibration] TA2
8037 23:42:36.652519 Original DQ_B0 (3 6) =30, OEN = 27
8038 23:42:36.655320 Original DQ_B1 (3 6) =30, OEN = 27
8039 23:42:36.658686 24, 0x0, End_B0=24 End_B1=24
8040 23:42:36.662303 25, 0x0, End_B0=25 End_B1=25
8041 23:42:36.662420 26, 0x0, End_B0=26 End_B1=26
8042 23:42:36.665603 27, 0x0, End_B0=27 End_B1=27
8043 23:42:36.668747 28, 0x0, End_B0=28 End_B1=28
8044 23:42:36.671831 29, 0x0, End_B0=29 End_B1=29
8045 23:42:36.671910 30, 0x0, End_B0=30 End_B1=30
8046 23:42:36.675094 31, 0x4141, End_B0=30 End_B1=30
8047 23:42:36.678641 Byte0 end_step=30 best_step=27
8048 23:42:36.681893 Byte1 end_step=30 best_step=27
8049 23:42:36.684939 Byte0 TX OE(2T, 0.5T) = (3, 3)
8050 23:42:36.688158 Byte1 TX OE(2T, 0.5T) = (3, 3)
8051 23:42:36.688258
8052 23:42:36.688361
8053 23:42:36.695009 [DQSOSCAuto] RK0, (LSB)MR18= 0x2416, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
8054 23:42:36.699217 CH0 RK0: MR19=303, MR18=2416
8055 23:42:36.705639 CH0_RK0: MR19=0x303, MR18=0x2416, DQSOSC=391, MR23=63, INC=24, DEC=16
8056 23:42:36.705791
8057 23:42:36.708355 ----->DramcWriteLeveling(PI) begin...
8058 23:42:36.708482 ==
8059 23:42:36.711695 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 23:42:36.715216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 23:42:36.715324 ==
8062 23:42:36.717877 Write leveling (Byte 0): 36 => 36
8063 23:42:36.721085 Write leveling (Byte 1): 29 => 29
8064 23:42:36.724740 DramcWriteLeveling(PI) end<-----
8065 23:42:36.724841
8066 23:42:36.724941 ==
8067 23:42:36.727957 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 23:42:36.734563 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 23:42:36.734671 ==
8070 23:42:36.734765 [Gating] SW mode calibration
8071 23:42:36.744336 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8072 23:42:36.747634 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8073 23:42:36.754115 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 23:42:36.757669 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8075 23:42:36.760681 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8076 23:42:36.767239 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8077 23:42:36.771027 1 4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8078 23:42:36.774198 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (1 1) (1 1)
8079 23:42:36.780301 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8080 23:42:36.783594 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8081 23:42:36.786863 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8082 23:42:36.793568 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8083 23:42:36.797045 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8084 23:42:36.799903 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
8085 23:42:36.807019 1 5 16 | B1->B0 | 3434 2626 | 0 0 | (1 0) (0 0)
8086 23:42:36.810006 1 5 20 | B1->B0 | 2626 2323 | 0 0 | (0 1) (0 0)
8087 23:42:36.813291 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8088 23:42:36.819644 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8089 23:42:36.823487 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8090 23:42:36.826756 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8091 23:42:36.833263 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8092 23:42:36.836294 1 6 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8093 23:42:36.839445 1 6 16 | B1->B0 | 2727 4545 | 0 0 | (1 1) (0 0)
8094 23:42:36.845983 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8095 23:42:36.849535 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8096 23:42:36.852527 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8097 23:42:36.859137 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8098 23:42:36.862429 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 23:42:36.865998 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8100 23:42:36.872713 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8101 23:42:36.875803 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8102 23:42:36.879496 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8103 23:42:36.886123 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8104 23:42:36.888883 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 23:42:36.892087 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 23:42:36.899040 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 23:42:36.902270 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8108 23:42:36.905715 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8109 23:42:36.912087 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8110 23:42:36.915685 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8111 23:42:36.918964 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8112 23:42:36.925471 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 23:42:36.928601 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 23:42:36.931909 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 23:42:36.938628 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8116 23:42:36.942216 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8117 23:42:36.945544 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8118 23:42:36.952071 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8119 23:42:36.952184 Total UI for P1: 0, mck2ui 16
8120 23:42:36.958536 best dqsien dly found for B0: ( 1, 9, 12)
8121 23:42:36.962070 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8122 23:42:36.964762 Total UI for P1: 0, mck2ui 16
8123 23:42:36.968139 best dqsien dly found for B1: ( 1, 9, 18)
8124 23:42:36.971241 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8125 23:42:36.974641 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8126 23:42:36.974752
8127 23:42:36.978079 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8128 23:42:36.981407 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8129 23:42:36.984616 [Gating] SW calibration Done
8130 23:42:36.984724 ==
8131 23:42:36.988019 Dram Type= 6, Freq= 0, CH_0, rank 1
8132 23:42:36.991362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8133 23:42:36.994378 ==
8134 23:42:36.994475 RX Vref Scan: 0
8135 23:42:36.994541
8136 23:42:36.997684 RX Vref 0 -> 0, step: 1
8137 23:42:36.997785
8138 23:42:37.001115 RX Delay 0 -> 252, step: 8
8139 23:42:37.004517 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8140 23:42:37.008078 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8141 23:42:37.010939 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8142 23:42:37.014155 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8143 23:42:37.020901 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8144 23:42:37.024404 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8145 23:42:37.027500 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8146 23:42:37.031221 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8147 23:42:37.034325 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8148 23:42:37.040997 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8149 23:42:37.044211 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8150 23:42:37.047378 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8151 23:42:37.051034 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8152 23:42:37.057219 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8153 23:42:37.060456 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8154 23:42:37.063874 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8155 23:42:37.063979 ==
8156 23:42:37.067041 Dram Type= 6, Freq= 0, CH_0, rank 1
8157 23:42:37.070029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8158 23:42:37.070133 ==
8159 23:42:37.073311 DQS Delay:
8160 23:42:37.073413 DQS0 = 0, DQS1 = 0
8161 23:42:37.077199 DQM Delay:
8162 23:42:37.077301 DQM0 = 132, DQM1 = 127
8163 23:42:37.077395 DQ Delay:
8164 23:42:37.083452 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8165 23:42:37.086857 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8166 23:42:37.090137 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8167 23:42:37.093618 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8168 23:42:37.093723
8169 23:42:37.093816
8170 23:42:37.093906 ==
8171 23:42:37.096618 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 23:42:37.099781 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 23:42:37.099885 ==
8174 23:42:37.099982
8175 23:42:37.100073
8176 23:42:37.103199 TX Vref Scan disable
8177 23:42:37.106610 == TX Byte 0 ==
8178 23:42:37.110213 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8179 23:42:37.113763 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8180 23:42:37.116659 == TX Byte 1 ==
8181 23:42:37.119959 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8182 23:42:37.123374 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8183 23:42:37.123478 ==
8184 23:42:37.126483 Dram Type= 6, Freq= 0, CH_0, rank 1
8185 23:42:37.133233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8186 23:42:37.133341 ==
8187 23:42:37.144452
8188 23:42:37.147405 TX Vref early break, caculate TX vref
8189 23:42:37.150580 TX Vref=16, minBit 0, minWin=23, winSum=378
8190 23:42:37.153522 TX Vref=18, minBit 0, minWin=23, winSum=388
8191 23:42:37.157065 TX Vref=20, minBit 1, minWin=23, winSum=395
8192 23:42:37.160440 TX Vref=22, minBit 1, minWin=24, winSum=404
8193 23:42:37.163931 TX Vref=24, minBit 1, minWin=24, winSum=410
8194 23:42:37.170705 TX Vref=26, minBit 0, minWin=25, winSum=420
8195 23:42:37.173967 TX Vref=28, minBit 0, minWin=25, winSum=417
8196 23:42:37.177172 TX Vref=30, minBit 0, minWin=24, winSum=404
8197 23:42:37.180169 TX Vref=32, minBit 5, minWin=23, winSum=396
8198 23:42:37.187127 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 26
8199 23:42:37.187234
8200 23:42:37.189955 Final TX Range 0 Vref 26
8201 23:42:37.190059
8202 23:42:37.190151 ==
8203 23:42:37.193411 Dram Type= 6, Freq= 0, CH_0, rank 1
8204 23:42:37.197100 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8205 23:42:37.197204 ==
8206 23:42:37.197326
8207 23:42:37.197416
8208 23:42:37.199959 TX Vref Scan disable
8209 23:42:37.206450 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8210 23:42:37.206557 == TX Byte 0 ==
8211 23:42:37.209965 u2DelayCellOfst[0]=14 cells (4 PI)
8212 23:42:37.213013 u2DelayCellOfst[1]=18 cells (5 PI)
8213 23:42:37.216394 u2DelayCellOfst[2]=14 cells (4 PI)
8214 23:42:37.219826 u2DelayCellOfst[3]=18 cells (5 PI)
8215 23:42:37.223217 u2DelayCellOfst[4]=11 cells (3 PI)
8216 23:42:37.226183 u2DelayCellOfst[5]=0 cells (0 PI)
8217 23:42:37.229667 u2DelayCellOfst[6]=18 cells (5 PI)
8218 23:42:37.232852 u2DelayCellOfst[7]=22 cells (6 PI)
8219 23:42:37.236314 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8220 23:42:37.239370 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8221 23:42:37.242812 == TX Byte 1 ==
8222 23:42:37.242892 u2DelayCellOfst[8]=0 cells (0 PI)
8223 23:42:37.246459 u2DelayCellOfst[9]=3 cells (1 PI)
8224 23:42:37.249817 u2DelayCellOfst[10]=11 cells (3 PI)
8225 23:42:37.252528 u2DelayCellOfst[11]=3 cells (1 PI)
8226 23:42:37.256215 u2DelayCellOfst[12]=14 cells (4 PI)
8227 23:42:37.259186 u2DelayCellOfst[13]=14 cells (4 PI)
8228 23:42:37.262640 u2DelayCellOfst[14]=18 cells (5 PI)
8229 23:42:37.266003 u2DelayCellOfst[15]=11 cells (3 PI)
8230 23:42:37.268997 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8231 23:42:37.275742 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8232 23:42:37.275836 DramC Write-DBI on
8233 23:42:37.275934 ==
8234 23:42:37.279264 Dram Type= 6, Freq= 0, CH_0, rank 1
8235 23:42:37.285643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8236 23:42:37.285746 ==
8237 23:42:37.285841
8238 23:42:37.285986
8239 23:42:37.286075 TX Vref Scan disable
8240 23:42:37.289578 == TX Byte 0 ==
8241 23:42:37.293347 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8242 23:42:37.296376 == TX Byte 1 ==
8243 23:42:37.299911 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8244 23:42:37.303202 DramC Write-DBI off
8245 23:42:37.303301
8246 23:42:37.303394 [DATLAT]
8247 23:42:37.303486 Freq=1600, CH0 RK1
8248 23:42:37.303574
8249 23:42:37.306411 DATLAT Default: 0xf
8250 23:42:37.306511 0, 0xFFFF, sum = 0
8251 23:42:37.309724 1, 0xFFFF, sum = 0
8252 23:42:37.312958 2, 0xFFFF, sum = 0
8253 23:42:37.313063 3, 0xFFFF, sum = 0
8254 23:42:37.316061 4, 0xFFFF, sum = 0
8255 23:42:37.316163 5, 0xFFFF, sum = 0
8256 23:42:37.319505 6, 0xFFFF, sum = 0
8257 23:42:37.319611 7, 0xFFFF, sum = 0
8258 23:42:37.322782 8, 0xFFFF, sum = 0
8259 23:42:37.322943 9, 0xFFFF, sum = 0
8260 23:42:37.326264 10, 0xFFFF, sum = 0
8261 23:42:37.326344 11, 0xFFFF, sum = 0
8262 23:42:37.329704 12, 0xFFFF, sum = 0
8263 23:42:37.329813 13, 0xFFFF, sum = 0
8264 23:42:37.332753 14, 0x0, sum = 1
8265 23:42:37.332874 15, 0x0, sum = 2
8266 23:42:37.335816 16, 0x0, sum = 3
8267 23:42:37.335917 17, 0x0, sum = 4
8268 23:42:37.339544 best_step = 15
8269 23:42:37.339622
8270 23:42:37.339685 ==
8271 23:42:37.342484 Dram Type= 6, Freq= 0, CH_0, rank 1
8272 23:42:37.345805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8273 23:42:37.345908 ==
8274 23:42:37.349034 RX Vref Scan: 0
8275 23:42:37.349128
8276 23:42:37.349220 RX Vref 0 -> 0, step: 1
8277 23:42:37.349308
8278 23:42:37.352278 RX Delay 11 -> 252, step: 4
8279 23:42:37.358978 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8280 23:42:37.362434 iDelay=195, Bit 1, Center 136 (83 ~ 190) 108
8281 23:42:37.365673 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8282 23:42:37.368751 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8283 23:42:37.372261 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8284 23:42:37.378707 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8285 23:42:37.382305 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8286 23:42:37.385878 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8287 23:42:37.388834 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8288 23:42:37.392415 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8289 23:42:37.398430 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8290 23:42:37.401956 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8291 23:42:37.405275 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8292 23:42:37.408981 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8293 23:42:37.411958 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8294 23:42:37.418485 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8295 23:42:37.418590 ==
8296 23:42:37.422039 Dram Type= 6, Freq= 0, CH_0, rank 1
8297 23:42:37.425284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 23:42:37.425392 ==
8299 23:42:37.425487 DQS Delay:
8300 23:42:37.428520 DQS0 = 0, DQS1 = 0
8301 23:42:37.428625 DQM Delay:
8302 23:42:37.431530 DQM0 = 130, DQM1 = 125
8303 23:42:37.431630 DQ Delay:
8304 23:42:37.434922 DQ0 =128, DQ1 =136, DQ2 =126, DQ3 =128
8305 23:42:37.438578 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8306 23:42:37.441220 DQ8 =116, DQ9 =112, DQ10 =128, DQ11 =120
8307 23:42:37.448088 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8308 23:42:37.448171
8309 23:42:37.448263
8310 23:42:37.448366
8311 23:42:37.451396 [DramC_TX_OE_Calibration] TA2
8312 23:42:37.454483 Original DQ_B0 (3 6) =30, OEN = 27
8313 23:42:37.454559 Original DQ_B1 (3 6) =30, OEN = 27
8314 23:42:37.457654 24, 0x0, End_B0=24 End_B1=24
8315 23:42:37.460981 25, 0x0, End_B0=25 End_B1=25
8316 23:42:37.464893 26, 0x0, End_B0=26 End_B1=26
8317 23:42:37.467576 27, 0x0, End_B0=27 End_B1=27
8318 23:42:37.467684 28, 0x0, End_B0=28 End_B1=28
8319 23:42:37.470797 29, 0x0, End_B0=29 End_B1=29
8320 23:42:37.474284 30, 0x0, End_B0=30 End_B1=30
8321 23:42:37.477943 31, 0x4141, End_B0=30 End_B1=30
8322 23:42:37.480721 Byte0 end_step=30 best_step=27
8323 23:42:37.484193 Byte1 end_step=30 best_step=27
8324 23:42:37.484276 Byte0 TX OE(2T, 0.5T) = (3, 3)
8325 23:42:37.487491 Byte1 TX OE(2T, 0.5T) = (3, 3)
8326 23:42:37.487613
8327 23:42:37.487715
8328 23:42:37.497354 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f02, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8329 23:42:37.500643 CH0 RK1: MR19=303, MR18=1F02
8330 23:42:37.503894 CH0_RK1: MR19=0x303, MR18=0x1F02, DQSOSC=394, MR23=63, INC=23, DEC=15
8331 23:42:37.507290 [RxdqsGatingPostProcess] freq 1600
8332 23:42:37.513947 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8333 23:42:37.517150 best DQS0 dly(2T, 0.5T) = (1, 1)
8334 23:42:37.520395 best DQS1 dly(2T, 0.5T) = (1, 1)
8335 23:42:37.523391 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8336 23:42:37.527475 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8337 23:42:37.530211 best DQS0 dly(2T, 0.5T) = (1, 1)
8338 23:42:37.533701 best DQS1 dly(2T, 0.5T) = (1, 1)
8339 23:42:37.537007 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8340 23:42:37.537114 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8341 23:42:37.540103 Pre-setting of DQS Precalculation
8342 23:42:37.546841 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8343 23:42:37.546944 ==
8344 23:42:37.550026 Dram Type= 6, Freq= 0, CH_1, rank 0
8345 23:42:37.553414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 23:42:37.553492 ==
8347 23:42:37.559896 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8348 23:42:37.563366 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8349 23:42:37.566385 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8350 23:42:37.573151 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8351 23:42:37.582819 [CA 0] Center 42 (13~72) winsize 60
8352 23:42:37.586380 [CA 1] Center 42 (13~72) winsize 60
8353 23:42:37.589446 [CA 2] Center 38 (9~67) winsize 59
8354 23:42:37.592792 [CA 3] Center 37 (8~66) winsize 59
8355 23:42:37.595903 [CA 4] Center 37 (8~67) winsize 60
8356 23:42:37.599130 [CA 5] Center 37 (8~67) winsize 60
8357 23:42:37.599212
8358 23:42:37.602601 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8359 23:42:37.602715
8360 23:42:37.609455 [CATrainingPosCal] consider 1 rank data
8361 23:42:37.609539 u2DelayCellTimex100 = 262/100 ps
8362 23:42:37.615639 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8363 23:42:37.618968 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8364 23:42:37.622306 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8365 23:42:37.625293 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8366 23:42:37.629124 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8367 23:42:37.632473 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8368 23:42:37.632557
8369 23:42:37.635113 CA PerBit enable=1, Macro0, CA PI delay=37
8370 23:42:37.635231
8371 23:42:37.639018 [CBTSetCACLKResult] CA Dly = 37
8372 23:42:37.642297 CS Dly: 9 (0~40)
8373 23:42:37.644992 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8374 23:42:37.648523 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8375 23:42:37.648633 ==
8376 23:42:37.651816 Dram Type= 6, Freq= 0, CH_1, rank 1
8377 23:42:37.658572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 23:42:37.658652 ==
8379 23:42:37.661642 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8380 23:42:37.668068 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8381 23:42:37.671612 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8382 23:42:37.678050 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8383 23:42:37.686131 [CA 0] Center 42 (12~72) winsize 61
8384 23:42:37.689386 [CA 1] Center 42 (13~72) winsize 60
8385 23:42:37.692469 [CA 2] Center 37 (8~67) winsize 60
8386 23:42:37.695872 [CA 3] Center 36 (7~66) winsize 60
8387 23:42:37.699197 [CA 4] Center 37 (7~67) winsize 61
8388 23:42:37.702590 [CA 5] Center 37 (8~67) winsize 60
8389 23:42:37.702696
8390 23:42:37.705516 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8391 23:42:37.705666
8392 23:42:37.708926 [CATrainingPosCal] consider 2 rank data
8393 23:42:37.712411 u2DelayCellTimex100 = 262/100 ps
8394 23:42:37.719201 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8395 23:42:37.722378 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8396 23:42:37.725947 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8397 23:42:37.728897 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8398 23:42:37.732275 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8399 23:42:37.735646 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8400 23:42:37.735748
8401 23:42:37.738367 CA PerBit enable=1, Macro0, CA PI delay=37
8402 23:42:37.738445
8403 23:42:37.741695 [CBTSetCACLKResult] CA Dly = 37
8404 23:42:37.745043 CS Dly: 10 (0~43)
8405 23:42:37.748403 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8406 23:42:37.752026 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8407 23:42:37.752132
8408 23:42:37.755093 ----->DramcWriteLeveling(PI) begin...
8409 23:42:37.755209 ==
8410 23:42:37.758284 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 23:42:37.765523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 23:42:37.765661 ==
8413 23:42:37.768479 Write leveling (Byte 0): 24 => 24
8414 23:42:37.771604 Write leveling (Byte 1): 27 => 27
8415 23:42:37.771717 DramcWriteLeveling(PI) end<-----
8416 23:42:37.774960
8417 23:42:37.775148 ==
8418 23:42:37.778591 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 23:42:37.781651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 23:42:37.781764 ==
8421 23:42:37.784832 [Gating] SW mode calibration
8422 23:42:37.791375 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8423 23:42:37.794847 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8424 23:42:37.801334 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8425 23:42:37.804671 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8426 23:42:37.808406 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8427 23:42:37.814980 1 4 12 | B1->B0 | 2f2f 3434 | 1 1 | (0 0) (1 1)
8428 23:42:37.817763 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 23:42:37.821406 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 23:42:37.827618 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8431 23:42:37.830743 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8432 23:42:37.837622 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8433 23:42:37.841001 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8434 23:42:37.844079 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8435 23:42:37.847767 1 5 12 | B1->B0 | 3030 2929 | 0 0 | (1 0) (1 0)
8436 23:42:37.854031 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 23:42:37.857330 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 23:42:37.860589 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 23:42:37.867136 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8440 23:42:37.870673 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8441 23:42:37.873799 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8442 23:42:37.880762 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8443 23:42:37.884080 1 6 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
8444 23:42:37.887101 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 23:42:37.893713 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 23:42:37.896984 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 23:42:37.900561 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 23:42:37.907368 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8449 23:42:37.910360 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8450 23:42:37.913757 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 23:42:37.920010 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8452 23:42:37.923343 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8453 23:42:37.926501 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 23:42:37.933182 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 23:42:37.936755 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 23:42:37.940064 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 23:42:37.946567 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 23:42:37.949685 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 23:42:37.953384 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 23:42:37.959787 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 23:42:37.963047 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 23:42:37.966358 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8463 23:42:37.972851 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8464 23:42:37.976469 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 23:42:37.979645 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 23:42:37.985945 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8467 23:42:37.989670 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8468 23:42:37.992621 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8469 23:42:37.996097 Total UI for P1: 0, mck2ui 16
8470 23:42:37.999474 best dqsien dly found for B0: ( 1, 9, 10)
8471 23:42:38.002647 Total UI for P1: 0, mck2ui 16
8472 23:42:38.005745 best dqsien dly found for B1: ( 1, 9, 10)
8473 23:42:38.008939 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8474 23:42:38.012584 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8475 23:42:38.015749
8476 23:42:38.019097 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8477 23:42:38.022438 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8478 23:42:38.025961 [Gating] SW calibration Done
8479 23:42:38.026079 ==
8480 23:42:38.029065 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 23:42:38.032209 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 23:42:38.032310 ==
8483 23:42:38.035411 RX Vref Scan: 0
8484 23:42:38.035494
8485 23:42:38.035587 RX Vref 0 -> 0, step: 1
8486 23:42:38.035682
8487 23:42:38.038984 RX Delay 0 -> 252, step: 8
8488 23:42:38.042375 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8489 23:42:38.045630 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8490 23:42:38.052718 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8491 23:42:38.055638 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8492 23:42:38.059035 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8493 23:42:38.061797 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8494 23:42:38.065952 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8495 23:42:38.072298 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8496 23:42:38.075068 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8497 23:42:38.078220 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8498 23:42:38.081740 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8499 23:42:38.088258 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8500 23:42:38.091900 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8501 23:42:38.094910 iDelay=208, Bit 13, Center 135 (72 ~ 199) 128
8502 23:42:38.098670 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8503 23:42:38.101443 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8504 23:42:38.104842 ==
8505 23:42:38.108186 Dram Type= 6, Freq= 0, CH_1, rank 0
8506 23:42:38.111267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8507 23:42:38.111340 ==
8508 23:42:38.111403 DQS Delay:
8509 23:42:38.114778 DQS0 = 0, DQS1 = 0
8510 23:42:38.114861 DQM Delay:
8511 23:42:38.117816 DQM0 = 136, DQM1 = 128
8512 23:42:38.117920 DQ Delay:
8513 23:42:38.121299 DQ0 =139, DQ1 =131, DQ2 =127, DQ3 =131
8514 23:42:38.124175 DQ4 =135, DQ5 =151, DQ6 =143, DQ7 =135
8515 23:42:38.127603 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
8516 23:42:38.131453 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8517 23:42:38.131526
8518 23:42:38.131588
8519 23:42:38.134623 ==
8520 23:42:38.137419 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 23:42:38.141148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 23:42:38.141269 ==
8523 23:42:38.141362
8524 23:42:38.141453
8525 23:42:38.144253 TX Vref Scan disable
8526 23:42:38.144359 == TX Byte 0 ==
8527 23:42:38.147492 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8528 23:42:38.154124 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8529 23:42:38.154252 == TX Byte 1 ==
8530 23:42:38.157246 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8531 23:42:38.164388 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8532 23:42:38.164500 ==
8533 23:42:38.167465 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 23:42:38.170493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 23:42:38.170571 ==
8536 23:42:38.183641
8537 23:42:38.186995 TX Vref early break, caculate TX vref
8538 23:42:38.190408 TX Vref=16, minBit 0, minWin=22, winSum=376
8539 23:42:38.193970 TX Vref=18, minBit 0, minWin=22, winSum=385
8540 23:42:38.196635 TX Vref=20, minBit 0, minWin=22, winSum=392
8541 23:42:38.200105 TX Vref=22, minBit 6, minWin=23, winSum=405
8542 23:42:38.203681 TX Vref=24, minBit 0, minWin=25, winSum=416
8543 23:42:38.210099 TX Vref=26, minBit 0, minWin=25, winSum=418
8544 23:42:38.213515 TX Vref=28, minBit 0, minWin=25, winSum=425
8545 23:42:38.217327 TX Vref=30, minBit 1, minWin=25, winSum=415
8546 23:42:38.219882 TX Vref=32, minBit 0, minWin=24, winSum=405
8547 23:42:38.223285 TX Vref=34, minBit 0, minWin=23, winSum=395
8548 23:42:38.230076 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
8549 23:42:38.230216
8550 23:42:38.233246 Final TX Range 0 Vref 28
8551 23:42:38.233347
8552 23:42:38.233440 ==
8553 23:42:38.236658 Dram Type= 6, Freq= 0, CH_1, rank 0
8554 23:42:38.239924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8555 23:42:38.240026 ==
8556 23:42:38.240117
8557 23:42:38.240207
8558 23:42:38.242923 TX Vref Scan disable
8559 23:42:38.249862 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8560 23:42:38.249971 == TX Byte 0 ==
8561 23:42:38.252926 u2DelayCellOfst[0]=18 cells (5 PI)
8562 23:42:38.256044 u2DelayCellOfst[1]=11 cells (3 PI)
8563 23:42:38.259574 u2DelayCellOfst[2]=0 cells (0 PI)
8564 23:42:38.262563 u2DelayCellOfst[3]=3 cells (1 PI)
8565 23:42:38.265837 u2DelayCellOfst[4]=7 cells (2 PI)
8566 23:42:38.269138 u2DelayCellOfst[5]=22 cells (6 PI)
8567 23:42:38.272558 u2DelayCellOfst[6]=18 cells (5 PI)
8568 23:42:38.275944 u2DelayCellOfst[7]=7 cells (2 PI)
8569 23:42:38.279195 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8570 23:42:38.282672 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8571 23:42:38.286060 == TX Byte 1 ==
8572 23:42:38.289369 u2DelayCellOfst[8]=0 cells (0 PI)
8573 23:42:38.292361 u2DelayCellOfst[9]=3 cells (1 PI)
8574 23:42:38.295800 u2DelayCellOfst[10]=11 cells (3 PI)
8575 23:42:38.298941 u2DelayCellOfst[11]=3 cells (1 PI)
8576 23:42:38.299019 u2DelayCellOfst[12]=14 cells (4 PI)
8577 23:42:38.301919 u2DelayCellOfst[13]=18 cells (5 PI)
8578 23:42:38.305127 u2DelayCellOfst[14]=18 cells (5 PI)
8579 23:42:38.308285 u2DelayCellOfst[15]=18 cells (5 PI)
8580 23:42:38.315327 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8581 23:42:38.318498 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8582 23:42:38.321519 DramC Write-DBI on
8583 23:42:38.321622 ==
8584 23:42:38.325114 Dram Type= 6, Freq= 0, CH_1, rank 0
8585 23:42:38.328414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8586 23:42:38.328519 ==
8587 23:42:38.328612
8588 23:42:38.328701
8589 23:42:38.331637 TX Vref Scan disable
8590 23:42:38.331715 == TX Byte 0 ==
8591 23:42:38.338102 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8592 23:42:38.338215 == TX Byte 1 ==
8593 23:42:38.341324 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8594 23:42:38.344655 DramC Write-DBI off
8595 23:42:38.344756
8596 23:42:38.344849 [DATLAT]
8597 23:42:38.348108 Freq=1600, CH1 RK0
8598 23:42:38.348217
8599 23:42:38.348309 DATLAT Default: 0xf
8600 23:42:38.351413 0, 0xFFFF, sum = 0
8601 23:42:38.351517 1, 0xFFFF, sum = 0
8602 23:42:38.354773 2, 0xFFFF, sum = 0
8603 23:42:38.354847 3, 0xFFFF, sum = 0
8604 23:42:38.357924 4, 0xFFFF, sum = 0
8605 23:42:38.361165 5, 0xFFFF, sum = 0
8606 23:42:38.361253 6, 0xFFFF, sum = 0
8607 23:42:38.364719 7, 0xFFFF, sum = 0
8608 23:42:38.364822 8, 0xFFFF, sum = 0
8609 23:42:38.368157 9, 0xFFFF, sum = 0
8610 23:42:38.368237 10, 0xFFFF, sum = 0
8611 23:42:38.372108 11, 0xFFFF, sum = 0
8612 23:42:38.372186 12, 0xFFFF, sum = 0
8613 23:42:38.374771 13, 0xFFFF, sum = 0
8614 23:42:38.374844 14, 0x0, sum = 1
8615 23:42:38.377895 15, 0x0, sum = 2
8616 23:42:38.377968 16, 0x0, sum = 3
8617 23:42:38.381489 17, 0x0, sum = 4
8618 23:42:38.381561 best_step = 15
8619 23:42:38.381638
8620 23:42:38.381699 ==
8621 23:42:38.384716 Dram Type= 6, Freq= 0, CH_1, rank 0
8622 23:42:38.387493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8623 23:42:38.391386 ==
8624 23:42:38.391459 RX Vref Scan: 1
8625 23:42:38.391539
8626 23:42:38.394742 Set Vref Range= 24 -> 127
8627 23:42:38.394814
8628 23:42:38.397792 RX Vref 24 -> 127, step: 1
8629 23:42:38.397868
8630 23:42:38.397957 RX Delay 11 -> 252, step: 4
8631 23:42:38.398044
8632 23:42:38.400681 Set Vref, RX VrefLevel [Byte0]: 24
8633 23:42:38.403902 [Byte1]: 24
8634 23:42:38.408007
8635 23:42:38.408096 Set Vref, RX VrefLevel [Byte0]: 25
8636 23:42:38.411248 [Byte1]: 25
8637 23:42:38.415878
8638 23:42:38.415978 Set Vref, RX VrefLevel [Byte0]: 26
8639 23:42:38.419108 [Byte1]: 26
8640 23:42:38.423397
8641 23:42:38.423467 Set Vref, RX VrefLevel [Byte0]: 27
8642 23:42:38.426999 [Byte1]: 27
8643 23:42:38.430983
8644 23:42:38.431057 Set Vref, RX VrefLevel [Byte0]: 28
8645 23:42:38.434677 [Byte1]: 28
8646 23:42:38.438413
8647 23:42:38.438488 Set Vref, RX VrefLevel [Byte0]: 29
8648 23:42:38.441615 [Byte1]: 29
8649 23:42:38.446378
8650 23:42:38.446454 Set Vref, RX VrefLevel [Byte0]: 30
8651 23:42:38.449530 [Byte1]: 30
8652 23:42:38.454031
8653 23:42:38.454111 Set Vref, RX VrefLevel [Byte0]: 31
8654 23:42:38.457257 [Byte1]: 31
8655 23:42:38.461486
8656 23:42:38.461589 Set Vref, RX VrefLevel [Byte0]: 32
8657 23:42:38.464574 [Byte1]: 32
8658 23:42:38.469399
8659 23:42:38.469477 Set Vref, RX VrefLevel [Byte0]: 33
8660 23:42:38.472475 [Byte1]: 33
8661 23:42:38.477139
8662 23:42:38.477231 Set Vref, RX VrefLevel [Byte0]: 34
8663 23:42:38.479769 [Byte1]: 34
8664 23:42:38.484520
8665 23:42:38.484631 Set Vref, RX VrefLevel [Byte0]: 35
8666 23:42:38.487512 [Byte1]: 35
8667 23:42:38.492171
8668 23:42:38.492275 Set Vref, RX VrefLevel [Byte0]: 36
8669 23:42:38.495067 [Byte1]: 36
8670 23:42:38.499481
8671 23:42:38.499560 Set Vref, RX VrefLevel [Byte0]: 37
8672 23:42:38.503002 [Byte1]: 37
8673 23:42:38.507266
8674 23:42:38.507350 Set Vref, RX VrefLevel [Byte0]: 38
8675 23:42:38.510373 [Byte1]: 38
8676 23:42:38.514792
8677 23:42:38.514892 Set Vref, RX VrefLevel [Byte0]: 39
8678 23:42:38.518004 [Byte1]: 39
8679 23:42:38.522761
8680 23:42:38.522840 Set Vref, RX VrefLevel [Byte0]: 40
8681 23:42:38.525376 [Byte1]: 40
8682 23:42:38.529829
8683 23:42:38.529940 Set Vref, RX VrefLevel [Byte0]: 41
8684 23:42:38.533281 [Byte1]: 41
8685 23:42:38.537787
8686 23:42:38.537898 Set Vref, RX VrefLevel [Byte0]: 42
8687 23:42:38.540607 [Byte1]: 42
8688 23:42:38.544989
8689 23:42:38.545065 Set Vref, RX VrefLevel [Byte0]: 43
8690 23:42:38.548521 [Byte1]: 43
8691 23:42:38.552840
8692 23:42:38.552950 Set Vref, RX VrefLevel [Byte0]: 44
8693 23:42:38.556245 [Byte1]: 44
8694 23:42:38.560653
8695 23:42:38.560728 Set Vref, RX VrefLevel [Byte0]: 45
8696 23:42:38.563585 [Byte1]: 45
8697 23:42:38.567755
8698 23:42:38.567857 Set Vref, RX VrefLevel [Byte0]: 46
8699 23:42:38.571523 [Byte1]: 46
8700 23:42:38.575508
8701 23:42:38.575586 Set Vref, RX VrefLevel [Byte0]: 47
8702 23:42:38.578610 [Byte1]: 47
8703 23:42:38.583175
8704 23:42:38.583284 Set Vref, RX VrefLevel [Byte0]: 48
8705 23:42:38.586297 [Byte1]: 48
8706 23:42:38.590779
8707 23:42:38.590856 Set Vref, RX VrefLevel [Byte0]: 49
8708 23:42:38.594247 [Byte1]: 49
8709 23:42:38.598251
8710 23:42:38.598329 Set Vref, RX VrefLevel [Byte0]: 50
8711 23:42:38.604949 [Byte1]: 50
8712 23:42:38.605049
8713 23:42:38.608174 Set Vref, RX VrefLevel [Byte0]: 51
8714 23:42:38.611290 [Byte1]: 51
8715 23:42:38.611377
8716 23:42:38.614443 Set Vref, RX VrefLevel [Byte0]: 52
8717 23:42:38.618210 [Byte1]: 52
8718 23:42:38.621447
8719 23:42:38.621529 Set Vref, RX VrefLevel [Byte0]: 53
8720 23:42:38.624805 [Byte1]: 53
8721 23:42:38.628718
8722 23:42:38.628799 Set Vref, RX VrefLevel [Byte0]: 54
8723 23:42:38.632421 [Byte1]: 54
8724 23:42:38.636807
8725 23:42:38.636911 Set Vref, RX VrefLevel [Byte0]: 55
8726 23:42:38.639990 [Byte1]: 55
8727 23:42:38.644425
8728 23:42:38.644501 Set Vref, RX VrefLevel [Byte0]: 56
8729 23:42:38.647343 [Byte1]: 56
8730 23:42:38.651687
8731 23:42:38.651787 Set Vref, RX VrefLevel [Byte0]: 57
8732 23:42:38.655079 [Byte1]: 57
8733 23:42:38.659257
8734 23:42:38.659355 Set Vref, RX VrefLevel [Byte0]: 58
8735 23:42:38.662669 [Byte1]: 58
8736 23:42:38.666811
8737 23:42:38.666892 Set Vref, RX VrefLevel [Byte0]: 59
8738 23:42:38.670280 [Byte1]: 59
8739 23:42:38.674742
8740 23:42:38.674816 Set Vref, RX VrefLevel [Byte0]: 60
8741 23:42:38.677811 [Byte1]: 60
8742 23:42:38.682047
8743 23:42:38.682153 Set Vref, RX VrefLevel [Byte0]: 61
8744 23:42:38.685616 [Byte1]: 61
8745 23:42:38.689589
8746 23:42:38.689695 Set Vref, RX VrefLevel [Byte0]: 62
8747 23:42:38.692989 [Byte1]: 62
8748 23:42:38.697286
8749 23:42:38.697376 Set Vref, RX VrefLevel [Byte0]: 63
8750 23:42:38.703668 [Byte1]: 63
8751 23:42:38.703751
8752 23:42:38.707262 Set Vref, RX VrefLevel [Byte0]: 64
8753 23:42:38.710138 [Byte1]: 64
8754 23:42:38.710256
8755 23:42:38.713617 Set Vref, RX VrefLevel [Byte0]: 65
8756 23:42:38.717069 [Byte1]: 65
8757 23:42:38.720406
8758 23:42:38.720517 Set Vref, RX VrefLevel [Byte0]: 66
8759 23:42:38.723271 [Byte1]: 66
8760 23:42:38.727899
8761 23:42:38.727974 Set Vref, RX VrefLevel [Byte0]: 67
8762 23:42:38.731510 [Byte1]: 67
8763 23:42:38.735847
8764 23:42:38.735952 Set Vref, RX VrefLevel [Byte0]: 68
8765 23:42:38.739004 [Byte1]: 68
8766 23:42:38.743204
8767 23:42:38.743308 Set Vref, RX VrefLevel [Byte0]: 69
8768 23:42:38.746383 [Byte1]: 69
8769 23:42:38.750547
8770 23:42:38.750652 Set Vref, RX VrefLevel [Byte0]: 70
8771 23:42:38.754062 [Byte1]: 70
8772 23:42:38.758170
8773 23:42:38.758278 Set Vref, RX VrefLevel [Byte0]: 71
8774 23:42:38.761834 [Byte1]: 71
8775 23:42:38.766025
8776 23:42:38.766102 Set Vref, RX VrefLevel [Byte0]: 72
8777 23:42:38.769203 [Byte1]: 72
8778 23:42:38.773294
8779 23:42:38.773386 Set Vref, RX VrefLevel [Byte0]: 73
8780 23:42:38.776554 [Byte1]: 73
8781 23:42:38.781496
8782 23:42:38.781570 Set Vref, RX VrefLevel [Byte0]: 74
8783 23:42:38.784904 [Byte1]: 74
8784 23:42:38.788598
8785 23:42:38.788705 Set Vref, RX VrefLevel [Byte0]: 75
8786 23:42:38.791798 [Byte1]: 75
8787 23:42:38.796398
8788 23:42:38.796508 Final RX Vref Byte 0 = 53 to rank0
8789 23:42:38.799464 Final RX Vref Byte 1 = 58 to rank0
8790 23:42:38.803220 Final RX Vref Byte 0 = 53 to rank1
8791 23:42:38.805997 Final RX Vref Byte 1 = 58 to rank1==
8792 23:42:38.809397 Dram Type= 6, Freq= 0, CH_1, rank 0
8793 23:42:38.816041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 23:42:38.816154 ==
8795 23:42:38.816240 DQS Delay:
8796 23:42:38.819135 DQS0 = 0, DQS1 = 0
8797 23:42:38.819206 DQM Delay:
8798 23:42:38.819275 DQM0 = 133, DQM1 = 127
8799 23:42:38.822538 DQ Delay:
8800 23:42:38.826305 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8801 23:42:38.829399 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =128
8802 23:42:38.833117 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =116
8803 23:42:38.835704 DQ12 =134, DQ13 =136, DQ14 =136, DQ15 =138
8804 23:42:38.835815
8805 23:42:38.835963
8806 23:42:38.836069
8807 23:42:38.839022 [DramC_TX_OE_Calibration] TA2
8808 23:42:38.842416 Original DQ_B0 (3 6) =30, OEN = 27
8809 23:42:38.845954 Original DQ_B1 (3 6) =30, OEN = 27
8810 23:42:38.848796 24, 0x0, End_B0=24 End_B1=24
8811 23:42:38.852165 25, 0x0, End_B0=25 End_B1=25
8812 23:42:38.852280 26, 0x0, End_B0=26 End_B1=26
8813 23:42:38.855582 27, 0x0, End_B0=27 End_B1=27
8814 23:42:38.859100 28, 0x0, End_B0=28 End_B1=28
8815 23:42:38.862079 29, 0x0, End_B0=29 End_B1=29
8816 23:42:38.862201 30, 0x0, End_B0=30 End_B1=30
8817 23:42:38.865477 31, 0x4141, End_B0=30 End_B1=30
8818 23:42:38.869003 Byte0 end_step=30 best_step=27
8819 23:42:38.872312 Byte1 end_step=30 best_step=27
8820 23:42:38.875388 Byte0 TX OE(2T, 0.5T) = (3, 3)
8821 23:42:38.878881 Byte1 TX OE(2T, 0.5T) = (3, 3)
8822 23:42:38.878967
8823 23:42:38.879042
8824 23:42:38.885908 [DQSOSCAuto] RK0, (LSB)MR18= 0x170d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8825 23:42:38.888721 CH1 RK0: MR19=303, MR18=170D
8826 23:42:38.895316 CH1_RK0: MR19=0x303, MR18=0x170D, DQSOSC=398, MR23=63, INC=23, DEC=15
8827 23:42:38.895406
8828 23:42:38.898230 ----->DramcWriteLeveling(PI) begin...
8829 23:42:38.898312 ==
8830 23:42:38.901776 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 23:42:38.905022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 23:42:38.905107 ==
8833 23:42:38.908136 Write leveling (Byte 0): 23 => 23
8834 23:42:38.911426 Write leveling (Byte 1): 27 => 27
8835 23:42:38.914824 DramcWriteLeveling(PI) end<-----
8836 23:42:38.914913
8837 23:42:38.915012 ==
8838 23:42:38.918080 Dram Type= 6, Freq= 0, CH_1, rank 1
8839 23:42:38.925029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8840 23:42:38.925116 ==
8841 23:42:38.925184 [Gating] SW mode calibration
8842 23:42:38.934515 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8843 23:42:38.938027 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8844 23:42:38.944830 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 23:42:38.947583 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 23:42:38.950774 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8847 23:42:38.958019 1 4 12 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 1)
8848 23:42:38.960788 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8849 23:42:38.963924 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8850 23:42:38.970632 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 23:42:38.973925 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 23:42:38.977177 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 23:42:38.983884 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8854 23:42:38.986917 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (0 1) (1 1)
8855 23:42:38.990286 1 5 12 | B1->B0 | 2525 3434 | 0 1 | (1 0) (1 0)
8856 23:42:38.997101 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8857 23:42:39.000014 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8858 23:42:39.003762 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 23:42:39.010232 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 23:42:39.013526 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 23:42:39.016562 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 23:42:39.023316 1 6 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8863 23:42:39.026719 1 6 12 | B1->B0 | 4646 2424 | 0 0 | (0 0) (0 0)
8864 23:42:39.029601 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8865 23:42:39.036404 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 23:42:39.039759 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 23:42:39.043153 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 23:42:39.049560 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 23:42:39.052977 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 23:42:39.056010 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8871 23:42:39.063269 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8872 23:42:39.066377 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8873 23:42:39.069369 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 23:42:39.075763 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 23:42:39.079348 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 23:42:39.082696 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 23:42:39.088812 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 23:42:39.092412 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 23:42:39.095672 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 23:42:39.102020 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 23:42:39.105502 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 23:42:39.109179 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 23:42:39.115341 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 23:42:39.118355 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 23:42:39.121933 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 23:42:39.128894 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8887 23:42:39.132087 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8888 23:42:39.135332 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8889 23:42:39.138406 Total UI for P1: 0, mck2ui 16
8890 23:42:39.141713 best dqsien dly found for B0: ( 1, 9, 12)
8891 23:42:39.145082 Total UI for P1: 0, mck2ui 16
8892 23:42:39.148107 best dqsien dly found for B1: ( 1, 9, 10)
8893 23:42:39.151365 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8894 23:42:39.154722 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8895 23:42:39.154795
8896 23:42:39.161563 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8897 23:42:39.165090 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8898 23:42:39.168026 [Gating] SW calibration Done
8899 23:42:39.168135 ==
8900 23:42:39.171900 Dram Type= 6, Freq= 0, CH_1, rank 1
8901 23:42:39.174985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8902 23:42:39.175064 ==
8903 23:42:39.175136 RX Vref Scan: 0
8904 23:42:39.175200
8905 23:42:39.177937 RX Vref 0 -> 0, step: 1
8906 23:42:39.178009
8907 23:42:39.181591 RX Delay 0 -> 252, step: 8
8908 23:42:39.184554 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8909 23:42:39.188438 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8910 23:42:39.194447 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8911 23:42:39.197851 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8912 23:42:39.200854 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8913 23:42:39.204159 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8914 23:42:39.207752 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8915 23:42:39.214019 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8916 23:42:39.217784 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8917 23:42:39.220931 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8918 23:42:39.224056 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8919 23:42:39.227371 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8920 23:42:39.234305 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8921 23:42:39.237143 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8922 23:42:39.240998 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8923 23:42:39.243867 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8924 23:42:39.243948 ==
8925 23:42:39.247007 Dram Type= 6, Freq= 0, CH_1, rank 1
8926 23:42:39.253524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8927 23:42:39.253636 ==
8928 23:42:39.253735 DQS Delay:
8929 23:42:39.257195 DQS0 = 0, DQS1 = 0
8930 23:42:39.257286 DQM Delay:
8931 23:42:39.260586 DQM0 = 136, DQM1 = 129
8932 23:42:39.260668 DQ Delay:
8933 23:42:39.263830 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8934 23:42:39.267104 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8935 23:42:39.270333 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8936 23:42:39.273494 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8937 23:42:39.273573
8938 23:42:39.273688
8939 23:42:39.273755 ==
8940 23:42:39.276906 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 23:42:39.283353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 23:42:39.283435 ==
8943 23:42:39.283500
8944 23:42:39.283583
8945 23:42:39.283662 TX Vref Scan disable
8946 23:42:39.287241 == TX Byte 0 ==
8947 23:42:39.290520 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8948 23:42:39.297051 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8949 23:42:39.297146 == TX Byte 1 ==
8950 23:42:39.300080 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8951 23:42:39.306621 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8952 23:42:39.306705 ==
8953 23:42:39.309863 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 23:42:39.313505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 23:42:39.313581 ==
8956 23:42:39.326085
8957 23:42:39.329377 TX Vref early break, caculate TX vref
8958 23:42:39.332361 TX Vref=16, minBit 0, minWin=22, winSum=379
8959 23:42:39.336366 TX Vref=18, minBit 1, minWin=23, winSum=393
8960 23:42:39.339485 TX Vref=20, minBit 0, minWin=24, winSum=397
8961 23:42:39.342389 TX Vref=22, minBit 0, minWin=24, winSum=406
8962 23:42:39.345974 TX Vref=24, minBit 5, minWin=24, winSum=412
8963 23:42:39.352556 TX Vref=26, minBit 0, minWin=25, winSum=417
8964 23:42:39.355809 TX Vref=28, minBit 0, minWin=24, winSum=418
8965 23:42:39.359003 TX Vref=30, minBit 0, minWin=23, winSum=412
8966 23:42:39.362767 TX Vref=32, minBit 0, minWin=24, winSum=405
8967 23:42:39.365419 TX Vref=34, minBit 0, minWin=23, winSum=393
8968 23:42:39.371957 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 26
8969 23:42:39.372067
8970 23:42:39.375380 Final TX Range 0 Vref 26
8971 23:42:39.375463
8972 23:42:39.375529 ==
8973 23:42:39.379341 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 23:42:39.382292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 23:42:39.382384 ==
8976 23:42:39.382454
8977 23:42:39.382515
8978 23:42:39.385867 TX Vref Scan disable
8979 23:42:39.392694 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8980 23:42:39.392806 == TX Byte 0 ==
8981 23:42:39.395441 u2DelayCellOfst[0]=18 cells (5 PI)
8982 23:42:39.398543 u2DelayCellOfst[1]=11 cells (3 PI)
8983 23:42:39.401878 u2DelayCellOfst[2]=0 cells (0 PI)
8984 23:42:39.405119 u2DelayCellOfst[3]=7 cells (2 PI)
8985 23:42:39.408357 u2DelayCellOfst[4]=7 cells (2 PI)
8986 23:42:39.412127 u2DelayCellOfst[5]=18 cells (5 PI)
8987 23:42:39.414880 u2DelayCellOfst[6]=18 cells (5 PI)
8988 23:42:39.418358 u2DelayCellOfst[7]=3 cells (1 PI)
8989 23:42:39.421681 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8990 23:42:39.424936 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8991 23:42:39.428216 == TX Byte 1 ==
8992 23:42:39.431549 u2DelayCellOfst[8]=0 cells (0 PI)
8993 23:42:39.431659 u2DelayCellOfst[9]=7 cells (2 PI)
8994 23:42:39.434761 u2DelayCellOfst[10]=11 cells (3 PI)
8995 23:42:39.438443 u2DelayCellOfst[11]=3 cells (1 PI)
8996 23:42:39.441430 u2DelayCellOfst[12]=14 cells (4 PI)
8997 23:42:39.444577 u2DelayCellOfst[13]=18 cells (5 PI)
8998 23:42:39.447863 u2DelayCellOfst[14]=18 cells (5 PI)
8999 23:42:39.451560 u2DelayCellOfst[15]=18 cells (5 PI)
9000 23:42:39.457748 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9001 23:42:39.461537 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9002 23:42:39.461612 DramC Write-DBI on
9003 23:42:39.461683 ==
9004 23:42:39.464764 Dram Type= 6, Freq= 0, CH_1, rank 1
9005 23:42:39.471258 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9006 23:42:39.471360 ==
9007 23:42:39.471448
9008 23:42:39.471512
9009 23:42:39.474256 TX Vref Scan disable
9010 23:42:39.474331 == TX Byte 0 ==
9011 23:42:39.480908 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9012 23:42:39.480993 == TX Byte 1 ==
9013 23:42:39.484360 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9014 23:42:39.487468 DramC Write-DBI off
9015 23:42:39.487547
9016 23:42:39.487619 [DATLAT]
9017 23:42:39.490759 Freq=1600, CH1 RK1
9018 23:42:39.490858
9019 23:42:39.490923 DATLAT Default: 0xf
9020 23:42:39.493929 0, 0xFFFF, sum = 0
9021 23:42:39.494035 1, 0xFFFF, sum = 0
9022 23:42:39.497119 2, 0xFFFF, sum = 0
9023 23:42:39.497228 3, 0xFFFF, sum = 0
9024 23:42:39.500658 4, 0xFFFF, sum = 0
9025 23:42:39.500737 5, 0xFFFF, sum = 0
9026 23:42:39.504099 6, 0xFFFF, sum = 0
9027 23:42:39.504180 7, 0xFFFF, sum = 0
9028 23:42:39.507053 8, 0xFFFF, sum = 0
9029 23:42:39.510767 9, 0xFFFF, sum = 0
9030 23:42:39.510844 10, 0xFFFF, sum = 0
9031 23:42:39.513454 11, 0xFFFF, sum = 0
9032 23:42:39.513528 12, 0xFFFF, sum = 0
9033 23:42:39.517406 13, 0xFFFF, sum = 0
9034 23:42:39.517479 14, 0x0, sum = 1
9035 23:42:39.520606 15, 0x0, sum = 2
9036 23:42:39.520680 16, 0x0, sum = 3
9037 23:42:39.523620 17, 0x0, sum = 4
9038 23:42:39.523706 best_step = 15
9039 23:42:39.523777
9040 23:42:39.523840 ==
9041 23:42:39.527028 Dram Type= 6, Freq= 0, CH_1, rank 1
9042 23:42:39.530292 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9043 23:42:39.533322 ==
9044 23:42:39.533402 RX Vref Scan: 0
9045 23:42:39.533467
9046 23:42:39.536869 RX Vref 0 -> 0, step: 1
9047 23:42:39.536943
9048 23:42:39.541995 RX Delay 11 -> 252, step: 4
9049 23:42:39.543229 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9050 23:42:39.546614 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9051 23:42:39.550137 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9052 23:42:39.556373 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9053 23:42:39.559683 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9054 23:42:39.563399 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9055 23:42:39.566563 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9056 23:42:39.569833 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9057 23:42:39.576450 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9058 23:42:39.580148 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9059 23:42:39.583108 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9060 23:42:39.586368 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9061 23:42:39.589639 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9062 23:42:39.596464 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9063 23:42:39.599496 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9064 23:42:39.602793 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9065 23:42:39.602877 ==
9066 23:42:39.606007 Dram Type= 6, Freq= 0, CH_1, rank 1
9067 23:42:39.609636 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9068 23:42:39.612578 ==
9069 23:42:39.612661 DQS Delay:
9070 23:42:39.612727 DQS0 = 0, DQS1 = 0
9071 23:42:39.615877 DQM Delay:
9072 23:42:39.615960 DQM0 = 133, DQM1 = 126
9073 23:42:39.619579 DQ Delay:
9074 23:42:39.622346 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9075 23:42:39.625614 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9076 23:42:39.629574 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9077 23:42:39.632547 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9078 23:42:39.632630
9079 23:42:39.632696
9080 23:42:39.632757
9081 23:42:39.635675 [DramC_TX_OE_Calibration] TA2
9082 23:42:39.639229 Original DQ_B0 (3 6) =30, OEN = 27
9083 23:42:39.642529 Original DQ_B1 (3 6) =30, OEN = 27
9084 23:42:39.645468 24, 0x0, End_B0=24 End_B1=24
9085 23:42:39.645623 25, 0x0, End_B0=25 End_B1=25
9086 23:42:39.648852 26, 0x0, End_B0=26 End_B1=26
9087 23:42:39.652201 27, 0x0, End_B0=27 End_B1=27
9088 23:42:39.655749 28, 0x0, End_B0=28 End_B1=28
9089 23:42:39.658767 29, 0x0, End_B0=29 End_B1=29
9090 23:42:39.658852 30, 0x0, End_B0=30 End_B1=30
9091 23:42:39.662155 31, 0x4141, End_B0=30 End_B1=30
9092 23:42:39.665307 Byte0 end_step=30 best_step=27
9093 23:42:39.668477 Byte1 end_step=30 best_step=27
9094 23:42:39.672242 Byte0 TX OE(2T, 0.5T) = (3, 3)
9095 23:42:39.674964 Byte1 TX OE(2T, 0.5T) = (3, 3)
9096 23:42:39.675047
9097 23:42:39.675141
9098 23:42:39.681867 [DQSOSCAuto] RK1, (LSB)MR18= 0xa06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9099 23:42:39.685373 CH1 RK1: MR19=303, MR18=A06
9100 23:42:39.691977 CH1_RK1: MR19=0x303, MR18=0xA06, DQSOSC=404, MR23=63, INC=22, DEC=15
9101 23:42:39.695499 [RxdqsGatingPostProcess] freq 1600
9102 23:42:39.698325 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9103 23:42:39.701571 best DQS0 dly(2T, 0.5T) = (1, 1)
9104 23:42:39.704966 best DQS1 dly(2T, 0.5T) = (1, 1)
9105 23:42:39.708273 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9106 23:42:39.711512 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9107 23:42:39.714883 best DQS0 dly(2T, 0.5T) = (1, 1)
9108 23:42:39.717929 best DQS1 dly(2T, 0.5T) = (1, 1)
9109 23:42:39.721451 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9110 23:42:39.724531 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9111 23:42:39.728160 Pre-setting of DQS Precalculation
9112 23:42:39.731130 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9113 23:42:39.737974 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9114 23:42:39.747888 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9115 23:42:39.747973
9116 23:42:39.748038
9117 23:42:39.751001 [Calibration Summary] 3200 Mbps
9118 23:42:39.751084 CH 0, Rank 0
9119 23:42:39.754054 SW Impedance : PASS
9120 23:42:39.754137 DUTY Scan : NO K
9121 23:42:39.757484 ZQ Calibration : PASS
9122 23:42:39.760783 Jitter Meter : NO K
9123 23:42:39.760867 CBT Training : PASS
9124 23:42:39.764395 Write leveling : PASS
9125 23:42:39.767623 RX DQS gating : PASS
9126 23:42:39.767706 RX DQ/DQS(RDDQC) : PASS
9127 23:42:39.770826 TX DQ/DQS : PASS
9128 23:42:39.770909 RX DATLAT : PASS
9129 23:42:39.774373 RX DQ/DQS(Engine): PASS
9130 23:42:39.777564 TX OE : PASS
9131 23:42:39.777646 All Pass.
9132 23:42:39.777712
9133 23:42:39.780430 CH 0, Rank 1
9134 23:42:39.780512 SW Impedance : PASS
9135 23:42:39.783605 DUTY Scan : NO K
9136 23:42:39.783695 ZQ Calibration : PASS
9137 23:42:39.787250 Jitter Meter : NO K
9138 23:42:39.790551 CBT Training : PASS
9139 23:42:39.790633 Write leveling : PASS
9140 23:42:39.794127 RX DQS gating : PASS
9141 23:42:39.797431 RX DQ/DQS(RDDQC) : PASS
9142 23:42:39.797514 TX DQ/DQS : PASS
9143 23:42:39.800117 RX DATLAT : PASS
9144 23:42:39.803747 RX DQ/DQS(Engine): PASS
9145 23:42:39.803898 TX OE : PASS
9146 23:42:39.806876 All Pass.
9147 23:42:39.806961
9148 23:42:39.807028 CH 1, Rank 0
9149 23:42:39.810412 SW Impedance : PASS
9150 23:42:39.810516 DUTY Scan : NO K
9151 23:42:39.813764 ZQ Calibration : PASS
9152 23:42:39.816705 Jitter Meter : NO K
9153 23:42:39.816779 CBT Training : PASS
9154 23:42:39.820442 Write leveling : PASS
9155 23:42:39.823877 RX DQS gating : PASS
9156 23:42:39.823959 RX DQ/DQS(RDDQC) : PASS
9157 23:42:39.826963 TX DQ/DQS : PASS
9158 23:42:39.830318 RX DATLAT : PASS
9159 23:42:39.830402 RX DQ/DQS(Engine): PASS
9160 23:42:39.833350 TX OE : PASS
9161 23:42:39.833457 All Pass.
9162 23:42:39.833536
9163 23:42:39.836596 CH 1, Rank 1
9164 23:42:39.836679 SW Impedance : PASS
9165 23:42:39.840130 DUTY Scan : NO K
9166 23:42:39.843266 ZQ Calibration : PASS
9167 23:42:39.843394 Jitter Meter : NO K
9168 23:42:39.846469 CBT Training : PASS
9169 23:42:39.846552 Write leveling : PASS
9170 23:42:39.849866 RX DQS gating : PASS
9171 23:42:39.853443 RX DQ/DQS(RDDQC) : PASS
9172 23:42:39.853522 TX DQ/DQS : PASS
9173 23:42:39.856333 RX DATLAT : PASS
9174 23:42:39.859808 RX DQ/DQS(Engine): PASS
9175 23:42:39.859884 TX OE : PASS
9176 23:42:39.862845 All Pass.
9177 23:42:39.862919
9178 23:42:39.862982 DramC Write-DBI on
9179 23:42:39.866266 PER_BANK_REFRESH: Hybrid Mode
9180 23:42:39.870105 TX_TRACKING: ON
9181 23:42:39.876369 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9182 23:42:39.886139 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9183 23:42:39.892618 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9184 23:42:39.896000 [FAST_K] Save calibration result to emmc
9185 23:42:39.899076 sync common calibartion params.
9186 23:42:39.899160 sync cbt_mode0:1, 1:1
9187 23:42:39.902578 dram_init: ddr_geometry: 2
9188 23:42:39.906010 dram_init: ddr_geometry: 2
9189 23:42:39.909266 dram_init: ddr_geometry: 2
9190 23:42:39.909370 0:dram_rank_size:100000000
9191 23:42:39.912464 1:dram_rank_size:100000000
9192 23:42:39.918869 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9193 23:42:39.918954 DFS_SHUFFLE_HW_MODE: ON
9194 23:42:39.925675 dramc_set_vcore_voltage set vcore to 725000
9195 23:42:39.925759 Read voltage for 1600, 0
9196 23:42:39.929200 Vio18 = 0
9197 23:42:39.929283 Vcore = 725000
9198 23:42:39.929349 Vdram = 0
9199 23:42:39.932157 Vddq = 0
9200 23:42:39.932239 Vmddr = 0
9201 23:42:39.935735 switch to 3200 Mbps bootup
9202 23:42:39.935818 [DramcRunTimeConfig]
9203 23:42:39.935884 PHYPLL
9204 23:42:39.939001 DPM_CONTROL_AFTERK: ON
9205 23:42:39.942434 PER_BANK_REFRESH: ON
9206 23:42:39.942520 REFRESH_OVERHEAD_REDUCTION: ON
9207 23:42:39.945366 CMD_PICG_NEW_MODE: OFF
9208 23:42:39.948586 XRTWTW_NEW_MODE: ON
9209 23:42:39.948669 XRTRTR_NEW_MODE: ON
9210 23:42:39.952145 TX_TRACKING: ON
9211 23:42:39.952220 RDSEL_TRACKING: OFF
9212 23:42:39.955512 DQS Precalculation for DVFS: ON
9213 23:42:39.958566 RX_TRACKING: OFF
9214 23:42:39.958649 HW_GATING DBG: ON
9215 23:42:39.961902 ZQCS_ENABLE_LP4: ON
9216 23:42:39.961982 RX_PICG_NEW_MODE: ON
9217 23:42:39.965271 TX_PICG_NEW_MODE: ON
9218 23:42:39.965349 ENABLE_RX_DCM_DPHY: ON
9219 23:42:39.968651 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9220 23:42:39.971710 DUMMY_READ_FOR_TRACKING: OFF
9221 23:42:39.975131 !!! SPM_CONTROL_AFTERK: OFF
9222 23:42:39.978333 !!! SPM could not control APHY
9223 23:42:39.978411 IMPEDANCE_TRACKING: ON
9224 23:42:39.981706 TEMP_SENSOR: ON
9225 23:42:39.981791 HW_SAVE_FOR_SR: OFF
9226 23:42:39.984864 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9227 23:42:39.988325 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9228 23:42:39.991412 Read ODT Tracking: ON
9229 23:42:39.994975 Refresh Rate DeBounce: ON
9230 23:42:39.995056 DFS_NO_QUEUE_FLUSH: ON
9231 23:42:39.998703 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9232 23:42:40.001301 ENABLE_DFS_RUNTIME_MRW: OFF
9233 23:42:40.004438 DDR_RESERVE_NEW_MODE: ON
9234 23:42:40.004527 MR_CBT_SWITCH_FREQ: ON
9235 23:42:40.008108 =========================
9236 23:42:40.026772 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9237 23:42:40.029901 dram_init: ddr_geometry: 2
9238 23:42:40.048138 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9239 23:42:40.051370 dram_init: dram init end (result: 0)
9240 23:42:40.058097 DRAM-K: Full calibration passed in 24641 msecs
9241 23:42:40.061713 MRC: failed to locate region type 0.
9242 23:42:40.061795 DRAM rank0 size:0x100000000,
9243 23:42:40.065166 DRAM rank1 size=0x100000000
9244 23:42:40.074597 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9245 23:42:40.081150 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9246 23:42:40.087588 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9247 23:42:40.097482 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9248 23:42:40.097571 DRAM rank0 size:0x100000000,
9249 23:42:40.101467 DRAM rank1 size=0x100000000
9250 23:42:40.101541 CBMEM:
9251 23:42:40.104506 IMD: root @ 0xfffff000 254 entries.
9252 23:42:40.107888 IMD: root @ 0xffffec00 62 entries.
9253 23:42:40.111418 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9254 23:42:40.117370 WARNING: RO_VPD is uninitialized or empty.
9255 23:42:40.120926 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9256 23:42:40.128359 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9257 23:42:40.141367 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9258 23:42:40.152379 BS: romstage times (exec / console): total (unknown) / 24128 ms
9259 23:42:40.152464
9260 23:42:40.152530
9261 23:42:40.162267 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9262 23:42:40.165448 ARM64: Exception handlers installed.
9263 23:42:40.168897 ARM64: Testing exception
9264 23:42:40.172612 ARM64: Done test exception
9265 23:42:40.172696 Enumerating buses...
9266 23:42:40.175440 Show all devs... Before device enumeration.
9267 23:42:40.178902 Root Device: enabled 1
9268 23:42:40.182220 CPU_CLUSTER: 0: enabled 1
9269 23:42:40.182320 CPU: 00: enabled 1
9270 23:42:40.185166 Compare with tree...
9271 23:42:40.185249 Root Device: enabled 1
9272 23:42:40.188824 CPU_CLUSTER: 0: enabled 1
9273 23:42:40.191874 CPU: 00: enabled 1
9274 23:42:40.191952 Root Device scanning...
9275 23:42:40.195404 scan_static_bus for Root Device
9276 23:42:40.199116 CPU_CLUSTER: 0 enabled
9277 23:42:40.201790 scan_static_bus for Root Device done
9278 23:42:40.205046 scan_bus: bus Root Device finished in 8 msecs
9279 23:42:40.205125 done
9280 23:42:40.211726 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9281 23:42:40.215263 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9282 23:42:40.221624 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9283 23:42:40.228146 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9284 23:42:40.228254 Allocating resources...
9285 23:42:40.231402 Reading resources...
9286 23:42:40.234649 Root Device read_resources bus 0 link: 0
9287 23:42:40.238540 DRAM rank0 size:0x100000000,
9288 23:42:40.238629 DRAM rank1 size=0x100000000
9289 23:42:40.244511 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9290 23:42:40.244659 CPU: 00 missing read_resources
9291 23:42:40.251489 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9292 23:42:40.254810 Root Device read_resources bus 0 link: 0 done
9293 23:42:40.257530 Done reading resources.
9294 23:42:40.260991 Show resources in subtree (Root Device)...After reading.
9295 23:42:40.264245 Root Device child on link 0 CPU_CLUSTER: 0
9296 23:42:40.267397 CPU_CLUSTER: 0 child on link 0 CPU: 00
9297 23:42:40.277750 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9298 23:42:40.277837 CPU: 00
9299 23:42:40.284244 Root Device assign_resources, bus 0 link: 0
9300 23:42:40.287660 CPU_CLUSTER: 0 missing set_resources
9301 23:42:40.290770 Root Device assign_resources, bus 0 link: 0 done
9302 23:42:40.294012 Done setting resources.
9303 23:42:40.297098 Show resources in subtree (Root Device)...After assigning values.
9304 23:42:40.304241 Root Device child on link 0 CPU_CLUSTER: 0
9305 23:42:40.307088 CPU_CLUSTER: 0 child on link 0 CPU: 00
9306 23:42:40.313804 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9307 23:42:40.316966 CPU: 00
9308 23:42:40.317045 Done allocating resources.
9309 23:42:40.323641 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9310 23:42:40.326354 Enabling resources...
9311 23:42:40.326438 done.
9312 23:42:40.329721 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9313 23:42:40.333064 Initializing devices...
9314 23:42:40.333171 Root Device init
9315 23:42:40.336775 init hardware done!
9316 23:42:40.340142 0x00000018: ctrlr->caps
9317 23:42:40.340260 52.000 MHz: ctrlr->f_max
9318 23:42:40.343003 0.400 MHz: ctrlr->f_min
9319 23:42:40.346411 0x40ff8080: ctrlr->voltages
9320 23:42:40.346508 sclk: 390625
9321 23:42:40.346606 Bus Width = 1
9322 23:42:40.350334 sclk: 390625
9323 23:42:40.350417 Bus Width = 1
9324 23:42:40.352985 Early init status = 3
9325 23:42:40.356536 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9326 23:42:40.360124 in-header: 03 fc 00 00 01 00 00 00
9327 23:42:40.363243 in-data: 00
9328 23:42:40.366614 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9329 23:42:40.371060 in-header: 03 fd 00 00 00 00 00 00
9330 23:42:40.374616 in-data:
9331 23:42:40.377818 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9332 23:42:40.381309 in-header: 03 fc 00 00 01 00 00 00
9333 23:42:40.384617 in-data: 00
9334 23:42:40.387834 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9335 23:42:40.392468 in-header: 03 fd 00 00 00 00 00 00
9336 23:42:40.396086 in-data:
9337 23:42:40.399450 [SSUSB] Setting up USB HOST controller...
9338 23:42:40.402514 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9339 23:42:40.405695 [SSUSB] phy power-on done.
9340 23:42:40.409100 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9341 23:42:40.415962 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9342 23:42:40.418866 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9343 23:42:40.425416 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9344 23:42:40.432133 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9345 23:42:40.438843 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9346 23:42:40.445853 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9347 23:42:40.452445 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9348 23:42:40.455535 SPM: binary array size = 0x9dc
9349 23:42:40.458427 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9350 23:42:40.465099 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9351 23:42:40.471930 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9352 23:42:40.478580 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9353 23:42:40.481647 configure_display: Starting display init
9354 23:42:40.515622 anx7625_power_on_init: Init interface.
9355 23:42:40.518880 anx7625_disable_pd_protocol: Disabled PD feature.
9356 23:42:40.522255 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9357 23:42:40.550018 anx7625_start_dp_work: Secure OCM version=00
9358 23:42:40.553564 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9359 23:42:40.568428 sp_tx_get_edid_block: EDID Block = 1
9360 23:42:40.670843 Extracted contents:
9361 23:42:40.674204 header: 00 ff ff ff ff ff ff 00
9362 23:42:40.677875 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9363 23:42:40.680642 version: 01 04
9364 23:42:40.684141 basic params: 95 1f 11 78 0a
9365 23:42:40.687392 chroma info: 76 90 94 55 54 90 27 21 50 54
9366 23:42:40.690657 established: 00 00 00
9367 23:42:40.697631 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9368 23:42:40.703917 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9369 23:42:40.706903 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9370 23:42:40.713521 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9371 23:42:40.720261 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9372 23:42:40.723974 extensions: 00
9373 23:42:40.724055 checksum: fb
9374 23:42:40.724120
9375 23:42:40.730364 Manufacturer: IVO Model 57d Serial Number 0
9376 23:42:40.730448 Made week 0 of 2020
9377 23:42:40.733368 EDID version: 1.4
9378 23:42:40.733455 Digital display
9379 23:42:40.737095 6 bits per primary color channel
9380 23:42:40.737206 DisplayPort interface
9381 23:42:40.739866 Maximum image size: 31 cm x 17 cm
9382 23:42:40.743177 Gamma: 220%
9383 23:42:40.743260 Check DPMS levels
9384 23:42:40.749689 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9385 23:42:40.753117 First detailed timing is preferred timing
9386 23:42:40.753195 Established timings supported:
9387 23:42:40.756340 Standard timings supported:
9388 23:42:40.759624 Detailed timings
9389 23:42:40.763404 Hex of detail: 383680a07038204018303c0035ae10000019
9390 23:42:40.769789 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9391 23:42:40.773532 0780 0798 07c8 0820 hborder 0
9392 23:42:40.776314 0438 043b 0447 0458 vborder 0
9393 23:42:40.779390 -hsync -vsync
9394 23:42:40.779468 Did detailed timing
9395 23:42:40.786296 Hex of detail: 000000000000000000000000000000000000
9396 23:42:40.789703 Manufacturer-specified data, tag 0
9397 23:42:40.792847 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9398 23:42:40.796480 ASCII string: InfoVision
9399 23:42:40.799615 Hex of detail: 000000fe00523134304e574635205248200a
9400 23:42:40.803241 ASCII string: R140NWF5 RH
9401 23:42:40.803317 Checksum
9402 23:42:40.806048 Checksum: 0xfb (valid)
9403 23:42:40.809289 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9404 23:42:40.812789 DSI data_rate: 832800000 bps
9405 23:42:40.819516 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9406 23:42:40.822653 anx7625_parse_edid: pixelclock(138800).
9407 23:42:40.825733 hactive(1920), hsync(48), hfp(24), hbp(88)
9408 23:42:40.829386 vactive(1080), vsync(12), vfp(3), vbp(17)
9409 23:42:40.832378 anx7625_dsi_config: config dsi.
9410 23:42:40.838763 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9411 23:42:40.853114 anx7625_dsi_config: success to config DSI
9412 23:42:40.856340 anx7625_dp_start: MIPI phy setup OK.
9413 23:42:40.859516 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9414 23:42:40.862863 mtk_ddp_mode_set invalid vrefresh 60
9415 23:42:40.866372 main_disp_path_setup
9416 23:42:40.866500 ovl_layer_smi_id_en
9417 23:42:40.869240 ovl_layer_smi_id_en
9418 23:42:40.869350 ccorr_config
9419 23:42:40.869451 aal_config
9420 23:42:40.872629 gamma_config
9421 23:42:40.872710 postmask_config
9422 23:42:40.875810 dither_config
9423 23:42:40.879203 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9424 23:42:40.885883 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9425 23:42:40.889029 Root Device init finished in 551 msecs
9426 23:42:40.892724 CPU_CLUSTER: 0 init
9427 23:42:40.899096 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9428 23:42:40.905663 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9429 23:42:40.905741 APU_MBOX 0x190000b0 = 0x10001
9430 23:42:40.908664 APU_MBOX 0x190001b0 = 0x10001
9431 23:42:40.912271 APU_MBOX 0x190005b0 = 0x10001
9432 23:42:40.915356 APU_MBOX 0x190006b0 = 0x10001
9433 23:42:40.921743 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9434 23:42:40.932241 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9435 23:42:40.944657 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9436 23:42:40.951057 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9437 23:42:40.962449 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9438 23:42:40.971996 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9439 23:42:40.975508 CPU_CLUSTER: 0 init finished in 81 msecs
9440 23:42:40.978385 Devices initialized
9441 23:42:40.981707 Show all devs... After init.
9442 23:42:40.981782 Root Device: enabled 1
9443 23:42:40.985311 CPU_CLUSTER: 0: enabled 1
9444 23:42:40.988297 CPU: 00: enabled 1
9445 23:42:40.991885 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9446 23:42:40.994871 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9447 23:42:40.997974 ELOG: NV offset 0x57f000 size 0x1000
9448 23:42:41.004631 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9449 23:42:41.011524 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9450 23:42:41.014611 ELOG: Event(17) added with size 13 at 2024-06-04 23:42:41 UTC
9451 23:42:41.021695 out: cmd=0x121: 03 db 21 01 00 00 00 00
9452 23:42:41.024524 in-header: 03 31 00 00 2c 00 00 00
9453 23:42:41.037801 in-data: 0b 73 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9454 23:42:41.041332 ELOG: Event(A1) added with size 10 at 2024-06-04 23:42:41 UTC
9455 23:42:41.048028 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9456 23:42:41.054132 ELOG: Event(A0) added with size 9 at 2024-06-04 23:42:41 UTC
9457 23:42:41.057596 elog_add_boot_reason: Logged dev mode boot
9458 23:42:41.064440 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9459 23:42:41.064527 Finalize devices...
9460 23:42:41.067340 Devices finalized
9461 23:42:41.070754 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9462 23:42:41.074207 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9463 23:42:41.077532 in-header: 03 07 00 00 08 00 00 00
9464 23:42:41.080677 in-data: aa e4 47 04 13 02 00 00
9465 23:42:41.083969 Chrome EC: UHEPI supported
9466 23:42:41.090412 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9467 23:42:41.094070 in-header: 03 a9 00 00 08 00 00 00
9468 23:42:41.097231 in-data: 84 60 60 08 00 00 00 00
9469 23:42:41.104089 ELOG: Event(91) added with size 10 at 2024-06-04 23:42:41 UTC
9470 23:42:41.107671 Chrome EC: clear events_b mask to 0x0000000020004000
9471 23:42:41.113951 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9472 23:42:41.118268 in-header: 03 fd 00 00 00 00 00 00
9473 23:42:41.121625 in-data:
9474 23:42:41.124925 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9475 23:42:41.128149 Writing coreboot table at 0xffe64000
9476 23:42:41.134588 0. 000000000010a000-0000000000113fff: RAMSTAGE
9477 23:42:41.138060 1. 0000000040000000-00000000400fffff: RAM
9478 23:42:41.141484 2. 0000000040100000-000000004032afff: RAMSTAGE
9479 23:42:41.144418 3. 000000004032b000-00000000545fffff: RAM
9480 23:42:41.147782 4. 0000000054600000-000000005465ffff: BL31
9481 23:42:41.151007 5. 0000000054660000-00000000ffe63fff: RAM
9482 23:42:41.157830 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9483 23:42:41.161495 7. 0000000100000000-000000023fffffff: RAM
9484 23:42:41.164392 Passing 5 GPIOs to payload:
9485 23:42:41.167719 NAME | PORT | POLARITY | VALUE
9486 23:42:41.174270 EC in RW | 0x000000aa | low | undefined
9487 23:42:41.177466 EC interrupt | 0x00000005 | low | undefined
9488 23:42:41.184317 TPM interrupt | 0x000000ab | high | undefined
9489 23:42:41.187336 SD card detect | 0x00000011 | high | undefined
9490 23:42:41.190784 speaker enable | 0x00000093 | high | undefined
9491 23:42:41.194285 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9492 23:42:41.198220 in-header: 03 f9 00 00 02 00 00 00
9493 23:42:41.201027 in-data: 02 00
9494 23:42:41.204597 ADC[4]: Raw value=902291 ID=7
9495 23:42:41.207933 ADC[3]: Raw value=214021 ID=1
9496 23:42:41.208039 RAM Code: 0x71
9497 23:42:41.210627 ADC[6]: Raw value=75036 ID=0
9498 23:42:41.214286 ADC[5]: Raw value=213652 ID=1
9499 23:42:41.214392 SKU Code: 0x1
9500 23:42:41.221261 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 2d14
9501 23:42:41.221342 coreboot table: 964 bytes.
9502 23:42:41.223962 IMD ROOT 0. 0xfffff000 0x00001000
9503 23:42:41.227513 IMD SMALL 1. 0xffffe000 0x00001000
9504 23:42:41.230871 RO MCACHE 2. 0xffffc000 0x00001104
9505 23:42:41.234022 CONSOLE 3. 0xfff7c000 0x00080000
9506 23:42:41.237064 FMAP 4. 0xfff7b000 0x00000452
9507 23:42:41.240244 TIME STAMP 5. 0xfff7a000 0x00000910
9508 23:42:41.243404 VBOOT WORK 6. 0xfff66000 0x00014000
9509 23:42:41.247210 RAMOOPS 7. 0xffe66000 0x00100000
9510 23:42:41.250337 COREBOOT 8. 0xffe64000 0x00002000
9511 23:42:41.253505 IMD small region:
9512 23:42:41.256610 IMD ROOT 0. 0xffffec00 0x00000400
9513 23:42:41.260105 VPD 1. 0xffffeb80 0x0000006c
9514 23:42:41.263373 MMC STATUS 2. 0xffffeb60 0x00000004
9515 23:42:41.270020 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9516 23:42:41.276737 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9517 23:42:41.315324 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9518 23:42:41.318545 Checking segment from ROM address 0x40100000
9519 23:42:41.322107 Checking segment from ROM address 0x4010001c
9520 23:42:41.328465 Loading segment from ROM address 0x40100000
9521 23:42:41.328576 code (compression=0)
9522 23:42:41.338429 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9523 23:42:41.344808 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9524 23:42:41.344913 it's not compressed!
9525 23:42:41.351585 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9526 23:42:41.358338 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9527 23:42:41.376059 Loading segment from ROM address 0x4010001c
9528 23:42:41.376162 Entry Point 0x80000000
9529 23:42:41.378850 Loaded segments
9530 23:42:41.382052 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9531 23:42:41.389015 Jumping to boot code at 0x80000000(0xffe64000)
9532 23:42:41.395441 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9533 23:42:41.402270 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9534 23:42:41.410128 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9535 23:42:41.413392 Checking segment from ROM address 0x40100000
9536 23:42:41.416584 Checking segment from ROM address 0x4010001c
9537 23:42:41.423636 Loading segment from ROM address 0x40100000
9538 23:42:41.423718 code (compression=1)
9539 23:42:41.430115 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9540 23:42:41.439785 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9541 23:42:41.439868 using LZMA
9542 23:42:41.448370 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9543 23:42:41.455283 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9544 23:42:41.458484 Loading segment from ROM address 0x4010001c
9545 23:42:41.458565 Entry Point 0x54601000
9546 23:42:41.461835 Loaded segments
9547 23:42:41.465262 NOTICE: MT8192 bl31_setup
9548 23:42:41.472183 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9549 23:42:41.475598 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9550 23:42:41.478771 WARNING: region 0:
9551 23:42:41.482343 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9552 23:42:41.482451 WARNING: region 1:
9553 23:42:41.488534 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9554 23:42:41.491719 WARNING: region 2:
9555 23:42:41.495268 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9556 23:42:41.498213 WARNING: region 3:
9557 23:42:41.504983 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9558 23:42:41.505094 WARNING: region 4:
9559 23:42:41.511787 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9560 23:42:41.511900 WARNING: region 5:
9561 23:42:41.515213 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9562 23:42:41.518113 WARNING: region 6:
9563 23:42:41.521535 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9564 23:42:41.525067 WARNING: region 7:
9565 23:42:41.528436 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9566 23:42:41.534734 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9567 23:42:41.537887 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9568 23:42:41.544754 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9569 23:42:41.547897 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9570 23:42:41.551754 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9571 23:42:41.558195 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9572 23:42:41.561237 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9573 23:42:41.564839 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9574 23:42:41.571082 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9575 23:42:41.574673 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9576 23:42:41.581306 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9577 23:42:41.584309 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9578 23:42:41.587524 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9579 23:42:41.594199 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9580 23:42:41.597593 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9581 23:42:41.600820 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9582 23:42:41.607443 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9583 23:42:41.610751 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9584 23:42:41.617806 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9585 23:42:41.620699 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9586 23:42:41.623970 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9587 23:42:41.630763 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9588 23:42:41.633957 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9589 23:42:41.640247 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9590 23:42:41.643898 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9591 23:42:41.646962 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9592 23:42:41.653579 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9593 23:42:41.656797 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9594 23:42:41.663924 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9595 23:42:41.666907 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9596 23:42:41.673392 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9597 23:42:41.676701 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9598 23:42:41.679972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9599 23:42:41.683870 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9600 23:42:41.689827 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9601 23:42:41.693291 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9602 23:42:41.696490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9603 23:42:41.699796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9604 23:42:41.706650 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9605 23:42:41.709929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9606 23:42:41.713450 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9607 23:42:41.716147 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9608 23:42:41.722909 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9609 23:42:41.726108 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9610 23:42:41.729477 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9611 23:42:41.735897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9612 23:42:41.739637 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9613 23:42:41.742530 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9614 23:42:41.749064 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9615 23:42:41.752790 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9616 23:42:41.756095 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9617 23:42:41.762637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9618 23:42:41.765586 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9619 23:42:41.772230 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9620 23:42:41.775642 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9621 23:42:41.782830 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9622 23:42:41.785547 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9623 23:42:41.792055 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9624 23:42:41.795587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9625 23:42:41.798647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9626 23:42:41.805359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9627 23:42:41.809138 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9628 23:42:41.815698 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9629 23:42:41.818486 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9630 23:42:41.825826 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9631 23:42:41.828482 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9632 23:42:41.834860 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9633 23:42:41.838498 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9634 23:42:41.841830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9635 23:42:41.848043 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9636 23:42:41.851434 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9637 23:42:41.858008 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9638 23:42:41.861535 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9639 23:42:41.868078 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9640 23:42:41.871150 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9641 23:42:41.878068 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9642 23:42:41.881430 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9643 23:42:41.887602 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9644 23:42:41.891123 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9645 23:42:41.894328 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9646 23:42:41.900832 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9647 23:42:41.904282 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9648 23:42:41.911070 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9649 23:42:41.914260 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9650 23:42:41.921065 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9651 23:42:41.924263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9652 23:42:41.927578 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9653 23:42:41.934343 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9654 23:42:41.937602 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9655 23:42:41.944262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9656 23:42:41.947039 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9657 23:42:41.953926 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9658 23:42:41.957348 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9659 23:42:41.963614 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9660 23:42:41.967217 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9661 23:42:41.973769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9662 23:42:41.976743 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9663 23:42:41.980195 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9664 23:42:41.983577 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9665 23:42:41.990315 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9666 23:42:41.993662 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9667 23:42:41.997231 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9668 23:42:42.003552 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9669 23:42:42.006438 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9670 23:42:42.013100 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9671 23:42:42.016376 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9672 23:42:42.020025 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9673 23:42:42.026142 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9674 23:42:42.029631 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9675 23:42:42.036099 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9676 23:42:42.039037 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9677 23:42:42.042627 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9678 23:42:42.049336 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9679 23:42:42.052299 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9680 23:42:42.059012 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9681 23:42:42.062545 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9682 23:42:42.065859 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9683 23:42:42.072030 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9684 23:42:42.075574 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9685 23:42:42.078577 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9686 23:42:42.085387 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9687 23:42:42.088421 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9688 23:42:42.092160 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9689 23:42:42.095769 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9690 23:42:42.101983 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9691 23:42:42.105563 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9692 23:42:42.111641 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9693 23:42:42.115310 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9694 23:42:42.118579 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9695 23:42:42.125051 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9696 23:42:42.128025 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9697 23:42:42.134369 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9698 23:42:42.137610 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9699 23:42:42.141120 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9700 23:42:42.148063 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9701 23:42:42.151290 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9702 23:42:42.157561 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9703 23:42:42.161157 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9704 23:42:42.164641 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9705 23:42:42.171140 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9706 23:42:42.174293 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9707 23:42:42.180598 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9708 23:42:42.184208 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9709 23:42:42.187413 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9710 23:42:42.194077 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9711 23:42:42.197272 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9712 23:42:42.203928 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9713 23:42:42.207484 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9714 23:42:42.210832 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9715 23:42:42.217132 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9716 23:42:42.220360 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9717 23:42:42.226915 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9718 23:42:42.230030 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9719 23:42:42.233444 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9720 23:42:42.240127 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9721 23:42:42.243535 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9722 23:42:42.250348 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9723 23:42:42.253285 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9724 23:42:42.256634 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9725 23:42:42.263510 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9726 23:42:42.266848 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9727 23:42:42.273096 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9728 23:42:42.276619 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9729 23:42:42.279636 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9730 23:42:42.286392 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9731 23:42:42.289291 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9732 23:42:42.296019 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9733 23:42:42.299887 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9734 23:42:42.302780 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9735 23:42:42.309800 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9736 23:42:42.312788 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9737 23:42:42.319032 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9738 23:42:42.322232 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9739 23:42:42.326034 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9740 23:42:42.332325 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9741 23:42:42.335611 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9742 23:42:42.342311 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9743 23:42:42.345793 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9744 23:42:42.349273 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9745 23:42:42.355797 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9746 23:42:42.358977 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9747 23:42:42.365308 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9748 23:42:42.368864 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9749 23:42:42.372368 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9750 23:42:42.378466 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9751 23:42:42.381727 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9752 23:42:42.388778 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9753 23:42:42.391853 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9754 23:42:42.395430 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9755 23:42:42.402043 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9756 23:42:42.404787 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9757 23:42:42.411569 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9758 23:42:42.414796 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9759 23:42:42.421516 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9760 23:42:42.424653 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9761 23:42:42.428346 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9762 23:42:42.434685 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9763 23:42:42.438339 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9764 23:42:42.444334 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9765 23:42:42.448126 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9766 23:42:42.454294 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9767 23:42:42.457654 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9768 23:42:42.461199 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9769 23:42:42.468160 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9770 23:42:42.471268 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9771 23:42:42.477332 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9772 23:42:42.481054 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9773 23:42:42.487458 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9774 23:42:42.490771 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9775 23:42:42.494075 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9776 23:42:42.500645 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9777 23:42:42.503810 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9778 23:42:42.510399 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9779 23:42:42.514271 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9780 23:42:42.520687 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9781 23:42:42.523971 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9782 23:42:42.527242 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9783 23:42:42.533319 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9784 23:42:42.537016 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9785 23:42:42.543524 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9786 23:42:42.546617 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9787 23:42:42.553514 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9788 23:42:42.556907 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9789 23:42:42.559928 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9790 23:42:42.566422 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9791 23:42:42.569631 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9792 23:42:42.576144 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9793 23:42:42.580037 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9794 23:42:42.583128 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9795 23:42:42.589637 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9796 23:42:42.593041 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9797 23:42:42.596325 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9798 23:42:42.599279 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9799 23:42:42.605737 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9800 23:42:42.609571 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9801 23:42:42.615822 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9802 23:42:42.618986 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9803 23:42:42.622356 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9804 23:42:42.629342 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9805 23:42:42.632834 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9806 23:42:42.636082 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9807 23:42:42.642157 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9808 23:42:42.645800 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9809 23:42:42.649245 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9810 23:42:42.655759 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9811 23:42:42.659171 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9812 23:42:42.665266 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9813 23:42:42.668677 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9814 23:42:42.671900 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9815 23:42:42.679026 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9816 23:42:42.682254 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9817 23:42:42.685405 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9818 23:42:42.692165 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9819 23:42:42.695636 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9820 23:42:42.698953 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9821 23:42:42.704972 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9822 23:42:42.708335 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9823 23:42:42.715071 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9824 23:42:42.718465 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9825 23:42:42.722080 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9826 23:42:42.728466 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9827 23:42:42.731503 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9828 23:42:42.738660 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9829 23:42:42.741732 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9830 23:42:42.745245 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9831 23:42:42.751814 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9832 23:42:42.754900 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9833 23:42:42.758172 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9834 23:42:42.764723 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9835 23:42:42.767935 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9836 23:42:42.770981 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9837 23:42:42.774515 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9838 23:42:42.781343 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9839 23:42:42.784357 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9840 23:42:42.787709 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9841 23:42:42.791055 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9842 23:42:42.797551 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9843 23:42:42.800651 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9844 23:42:42.804239 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9845 23:42:42.807885 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9846 23:42:42.814613 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9847 23:42:42.817604 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9848 23:42:42.820791 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9849 23:42:42.827153 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9850 23:42:42.830649 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9851 23:42:42.837142 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9852 23:42:42.840465 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9853 23:42:42.847128 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9854 23:42:42.850821 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9855 23:42:42.853894 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9856 23:42:42.860382 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9857 23:42:42.863751 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9858 23:42:42.870142 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9859 23:42:42.873399 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9860 23:42:42.877008 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9861 23:42:42.883794 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9862 23:42:42.887067 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9863 23:42:42.893605 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9864 23:42:42.896671 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9865 23:42:42.899931 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9866 23:42:42.906877 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9867 23:42:42.910041 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9868 23:42:42.916573 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9869 23:42:42.919893 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9870 23:42:42.926551 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9871 23:42:42.930074 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9872 23:42:42.933873 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9873 23:42:42.939654 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9874 23:42:42.943273 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9875 23:42:42.949839 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9876 23:42:42.952694 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9877 23:42:42.959273 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9878 23:42:42.962657 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9879 23:42:42.966034 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9880 23:42:42.973062 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9881 23:42:42.976081 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9882 23:42:42.982526 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9883 23:42:42.985600 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9884 23:42:42.988896 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9885 23:42:42.995623 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9886 23:42:42.999057 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9887 23:42:43.006041 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9888 23:42:43.009023 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9889 23:42:43.012105 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9890 23:42:43.018895 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9891 23:42:43.022119 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9892 23:42:43.028634 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9893 23:42:43.032066 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9894 23:42:43.038786 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9895 23:42:43.042013 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9896 23:42:43.045565 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9897 23:42:43.052127 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9898 23:42:43.055018 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9899 23:42:43.061537 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9900 23:42:43.064948 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9901 23:42:43.071464 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9902 23:42:43.075028 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9903 23:42:43.078377 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9904 23:42:43.084747 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9905 23:42:43.088197 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9906 23:42:43.094597 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9907 23:42:43.098051 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9908 23:42:43.101455 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9909 23:42:43.107854 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9910 23:42:43.111072 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9911 23:42:43.117736 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9912 23:42:43.121038 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9913 23:42:43.124586 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9914 23:42:43.131374 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9915 23:42:43.134154 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9916 23:42:43.140729 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9917 23:42:43.144038 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9918 23:42:43.151134 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9919 23:42:43.154132 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9920 23:42:43.157589 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9921 23:42:43.163826 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9922 23:42:43.167509 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9923 23:42:43.174120 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9924 23:42:43.177242 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9925 23:42:43.183430 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9926 23:42:43.186944 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9927 23:42:43.193639 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9928 23:42:43.196968 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9929 23:42:43.199997 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9930 23:42:43.206689 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9931 23:42:43.210033 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9932 23:42:43.216873 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9933 23:42:43.219835 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9934 23:42:43.226588 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9935 23:42:43.229651 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9936 23:42:43.236163 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9937 23:42:43.239735 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9938 23:42:43.246093 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9939 23:42:43.249731 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9940 23:42:43.252540 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9941 23:42:43.259360 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9942 23:42:43.262739 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9943 23:42:43.269415 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9944 23:42:43.272561 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9945 23:42:43.279136 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9946 23:42:43.282638 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9947 23:42:43.285795 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9948 23:42:43.292536 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9949 23:42:43.295809 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9950 23:42:43.302254 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9951 23:42:43.305344 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9952 23:42:43.312643 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9953 23:42:43.315872 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9954 23:42:43.321926 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9955 23:42:43.325180 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9956 23:42:43.331928 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9957 23:42:43.335315 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9958 23:42:43.338540 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9959 23:42:43.345410 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9960 23:42:43.348474 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9961 23:42:43.355335 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9962 23:42:43.358837 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9963 23:42:43.364861 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9964 23:42:43.368420 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9965 23:42:43.371473 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9966 23:42:43.378568 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9967 23:42:43.381685 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9968 23:42:43.388377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9969 23:42:43.391441 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9970 23:42:43.397867 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9971 23:42:43.401085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9972 23:42:43.408095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9973 23:42:43.411113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9974 23:42:43.414666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9975 23:42:43.421128 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9976 23:42:43.424480 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9977 23:42:43.430974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9978 23:42:43.434748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9979 23:42:43.441147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9980 23:42:43.444374 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9981 23:42:43.450880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9982 23:42:43.454429 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9983 23:42:43.461078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9984 23:42:43.464043 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9985 23:42:43.470590 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9986 23:42:43.474107 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9987 23:42:43.480461 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9988 23:42:43.483979 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9989 23:42:43.490324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9990 23:42:43.493831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9991 23:42:43.500497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9992 23:42:43.503577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9993 23:42:43.510036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9994 23:42:43.513907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9995 23:42:43.520052 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9996 23:42:43.526449 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9997 23:42:43.529943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9998 23:42:43.536497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9999 23:42:43.539726 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10000 23:42:43.543058 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10001 23:42:43.546408 INFO: [APUAPC] vio 0
10002 23:42:43.549686 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10003 23:42:43.556482 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10004 23:42:43.559917 INFO: [APUAPC] D0_APC_0: 0x400510
10005 23:42:43.563101 INFO: [APUAPC] D0_APC_1: 0x0
10006 23:42:43.566072 INFO: [APUAPC] D0_APC_2: 0x1540
10007 23:42:43.566158 INFO: [APUAPC] D0_APC_3: 0x0
10008 23:42:43.572767 INFO: [APUAPC] D1_APC_0: 0xffffffff
10009 23:42:43.575995 INFO: [APUAPC] D1_APC_1: 0xffffffff
10010 23:42:43.579345 INFO: [APUAPC] D1_APC_2: 0x3fffff
10011 23:42:43.579428 INFO: [APUAPC] D1_APC_3: 0x0
10012 23:42:43.582470 INFO: [APUAPC] D2_APC_0: 0xffffffff
10013 23:42:43.589801 INFO: [APUAPC] D2_APC_1: 0xffffffff
10014 23:42:43.593183 INFO: [APUAPC] D2_APC_2: 0x3fffff
10015 23:42:43.593297 INFO: [APUAPC] D2_APC_3: 0x0
10016 23:42:43.595802 INFO: [APUAPC] D3_APC_0: 0xffffffff
10017 23:42:43.599195 INFO: [APUAPC] D3_APC_1: 0xffffffff
10018 23:42:43.602423 INFO: [APUAPC] D3_APC_2: 0x3fffff
10019 23:42:43.605980 INFO: [APUAPC] D3_APC_3: 0x0
10020 23:42:43.609303 INFO: [APUAPC] D4_APC_0: 0xffffffff
10021 23:42:43.612336 INFO: [APUAPC] D4_APC_1: 0xffffffff
10022 23:42:43.615652 INFO: [APUAPC] D4_APC_2: 0x3fffff
10023 23:42:43.619340 INFO: [APUAPC] D4_APC_3: 0x0
10024 23:42:43.622321 INFO: [APUAPC] D5_APC_0: 0xffffffff
10025 23:42:43.625320 INFO: [APUAPC] D5_APC_1: 0xffffffff
10026 23:42:43.628662 INFO: [APUAPC] D5_APC_2: 0x3fffff
10027 23:42:43.632462 INFO: [APUAPC] D5_APC_3: 0x0
10028 23:42:43.635157 INFO: [APUAPC] D6_APC_0: 0xffffffff
10029 23:42:43.639075 INFO: [APUAPC] D6_APC_1: 0xffffffff
10030 23:42:43.642236 INFO: [APUAPC] D6_APC_2: 0x3fffff
10031 23:42:43.645260 INFO: [APUAPC] D6_APC_3: 0x0
10032 23:42:43.648360 INFO: [APUAPC] D7_APC_0: 0xffffffff
10033 23:42:43.652205 INFO: [APUAPC] D7_APC_1: 0xffffffff
10034 23:42:43.655434 INFO: [APUAPC] D7_APC_2: 0x3fffff
10035 23:42:43.658458 INFO: [APUAPC] D7_APC_3: 0x0
10036 23:42:43.661753 INFO: [APUAPC] D8_APC_0: 0xffffffff
10037 23:42:43.664955 INFO: [APUAPC] D8_APC_1: 0xffffffff
10038 23:42:43.668664 INFO: [APUAPC] D8_APC_2: 0x3fffff
10039 23:42:43.671735 INFO: [APUAPC] D8_APC_3: 0x0
10040 23:42:43.674973 INFO: [APUAPC] D9_APC_0: 0xffffffff
10041 23:42:43.678292 INFO: [APUAPC] D9_APC_1: 0xffffffff
10042 23:42:43.681604 INFO: [APUAPC] D9_APC_2: 0x3fffff
10043 23:42:43.685177 INFO: [APUAPC] D9_APC_3: 0x0
10044 23:42:43.687966 INFO: [APUAPC] D10_APC_0: 0xffffffff
10045 23:42:43.691421 INFO: [APUAPC] D10_APC_1: 0xffffffff
10046 23:42:43.694522 INFO: [APUAPC] D10_APC_2: 0x3fffff
10047 23:42:43.698059 INFO: [APUAPC] D10_APC_3: 0x0
10048 23:42:43.701399 INFO: [APUAPC] D11_APC_0: 0xffffffff
10049 23:42:43.704806 INFO: [APUAPC] D11_APC_1: 0xffffffff
10050 23:42:43.708018 INFO: [APUAPC] D11_APC_2: 0x3fffff
10051 23:42:43.711329 INFO: [APUAPC] D11_APC_3: 0x0
10052 23:42:43.715216 INFO: [APUAPC] D12_APC_0: 0xffffffff
10053 23:42:43.717821 INFO: [APUAPC] D12_APC_1: 0xffffffff
10054 23:42:43.721551 INFO: [APUAPC] D12_APC_2: 0x3fffff
10055 23:42:43.724672 INFO: [APUAPC] D12_APC_3: 0x0
10056 23:42:43.727511 INFO: [APUAPC] D13_APC_0: 0xffffffff
10057 23:42:43.730943 INFO: [APUAPC] D13_APC_1: 0xffffffff
10058 23:42:43.735085 INFO: [APUAPC] D13_APC_2: 0x3fffff
10059 23:42:43.737393 INFO: [APUAPC] D13_APC_3: 0x0
10060 23:42:43.741324 INFO: [APUAPC] D14_APC_0: 0xffffffff
10061 23:42:43.744325 INFO: [APUAPC] D14_APC_1: 0xffffffff
10062 23:42:43.747774 INFO: [APUAPC] D14_APC_2: 0x3fffff
10063 23:42:43.751043 INFO: [APUAPC] D14_APC_3: 0x0
10064 23:42:43.754258 INFO: [APUAPC] D15_APC_0: 0xffffffff
10065 23:42:43.757503 INFO: [APUAPC] D15_APC_1: 0xffffffff
10066 23:42:43.760752 INFO: [APUAPC] D15_APC_2: 0x3fffff
10067 23:42:43.763860 INFO: [APUAPC] D15_APC_3: 0x0
10068 23:42:43.767390 INFO: [APUAPC] APC_CON: 0x4
10069 23:42:43.770566 INFO: [NOCDAPC] D0_APC_0: 0x0
10070 23:42:43.774023 INFO: [NOCDAPC] D0_APC_1: 0x0
10071 23:42:43.777683 INFO: [NOCDAPC] D1_APC_0: 0x0
10072 23:42:43.780471 INFO: [NOCDAPC] D1_APC_1: 0xfff
10073 23:42:43.783735 INFO: [NOCDAPC] D2_APC_0: 0x0
10074 23:42:43.787019 INFO: [NOCDAPC] D2_APC_1: 0xfff
10075 23:42:43.787102 INFO: [NOCDAPC] D3_APC_0: 0x0
10076 23:42:43.790300 INFO: [NOCDAPC] D3_APC_1: 0xfff
10077 23:42:43.793662 INFO: [NOCDAPC] D4_APC_0: 0x0
10078 23:42:43.796847 INFO: [NOCDAPC] D4_APC_1: 0xfff
10079 23:42:43.800199 INFO: [NOCDAPC] D5_APC_0: 0x0
10080 23:42:43.803314 INFO: [NOCDAPC] D5_APC_1: 0xfff
10081 23:42:43.806880 INFO: [NOCDAPC] D6_APC_0: 0x0
10082 23:42:43.810440 INFO: [NOCDAPC] D6_APC_1: 0xfff
10083 23:42:43.813707 INFO: [NOCDAPC] D7_APC_0: 0x0
10084 23:42:43.816971 INFO: [NOCDAPC] D7_APC_1: 0xfff
10085 23:42:43.820606 INFO: [NOCDAPC] D8_APC_0: 0x0
10086 23:42:43.823742 INFO: [NOCDAPC] D8_APC_1: 0xfff
10087 23:42:43.823826 INFO: [NOCDAPC] D9_APC_0: 0x0
10088 23:42:43.827091 INFO: [NOCDAPC] D9_APC_1: 0xfff
10089 23:42:43.830446 INFO: [NOCDAPC] D10_APC_0: 0x0
10090 23:42:43.833486 INFO: [NOCDAPC] D10_APC_1: 0xfff
10091 23:42:43.836891 INFO: [NOCDAPC] D11_APC_0: 0x0
10092 23:42:43.840501 INFO: [NOCDAPC] D11_APC_1: 0xfff
10093 23:42:43.843492 INFO: [NOCDAPC] D12_APC_0: 0x0
10094 23:42:43.846505 INFO: [NOCDAPC] D12_APC_1: 0xfff
10095 23:42:43.849961 INFO: [NOCDAPC] D13_APC_0: 0x0
10096 23:42:43.853164 INFO: [NOCDAPC] D13_APC_1: 0xfff
10097 23:42:43.856164 INFO: [NOCDAPC] D14_APC_0: 0x0
10098 23:42:43.860028 INFO: [NOCDAPC] D14_APC_1: 0xfff
10099 23:42:43.862952 INFO: [NOCDAPC] D15_APC_0: 0x0
10100 23:42:43.866375 INFO: [NOCDAPC] D15_APC_1: 0xfff
10101 23:42:43.869620 INFO: [NOCDAPC] APC_CON: 0x4
10102 23:42:43.872869 INFO: [APUAPC] set_apusys_apc done
10103 23:42:43.876318 INFO: [DEVAPC] devapc_init done
10104 23:42:43.879647 INFO: GICv3 without legacy support detected.
10105 23:42:43.882771 INFO: ARM GICv3 driver initialized in EL3
10106 23:42:43.886332 INFO: Maximum SPI INTID supported: 639
10107 23:42:43.889254 INFO: BL31: Initializing runtime services
10108 23:42:43.895954 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10109 23:42:43.899547 INFO: SPM: enable CPC mode
10110 23:42:43.902495 INFO: mcdi ready for mcusys-off-idle and system suspend
10111 23:42:43.909944 INFO: BL31: Preparing for EL3 exit to normal world
10112 23:42:43.912641 INFO: Entry point address = 0x80000000
10113 23:42:43.915404 INFO: SPSR = 0x8
10114 23:42:43.920313
10115 23:42:43.920450
10116 23:42:43.920546
10117 23:42:43.923351 Starting depthcharge on Spherion...
10118 23:42:43.923451
10119 23:42:43.923588 Wipe memory regions:
10120 23:42:43.923695
10121 23:42:43.924501 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10122 23:42:43.924648 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
10123 23:42:43.924762 Setting prompt string to ['asurada:']
10124 23:42:43.924881 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
10125 23:42:43.926520 [0x00000040000000, 0x00000054600000)
10126 23:42:44.048966
10127 23:42:44.049134 [0x00000054660000, 0x00000080000000)
10128 23:42:44.309467
10129 23:42:44.309619 [0x000000821a7280, 0x000000ffe64000)
10130 23:42:45.053724
10131 23:42:45.053903 [0x00000100000000, 0x00000240000000)
10132 23:42:46.942287
10133 23:42:46.946232 Initializing XHCI USB controller at 0x11200000.
10134 23:42:47.983485
10135 23:42:47.987085 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10136 23:42:47.987174
10137 23:42:47.987240
10138 23:42:47.987533 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10140 23:42:48.087889 asurada: tftpboot 192.168.201.1 14172911/tftp-deploy-jrgn1tix/kernel/image.itb 14172911/tftp-deploy-jrgn1tix/kernel/cmdline
10141 23:42:48.088042 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10142 23:42:48.088151 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:22)
10143 23:42:48.092281 tftpboot 192.168.201.1 14172911/tftp-deploy-jrgn1tix/kernel/image.itp-deploy-jrgn1tix/kernel/cmdline
10144 23:42:48.092370
10145 23:42:48.092465 Waiting for link
10146 23:42:48.250565
10147 23:42:48.250748 R8152: Initializing
10148 23:42:48.250821
10149 23:42:48.253754 Version 6 (ocp_data = 5c30)
10150 23:42:48.253842
10151 23:42:48.257403 R8152: Done initializing
10152 23:42:48.257480
10153 23:42:48.257543 Adding net device
10154 23:42:50.115421
10155 23:42:50.115582 done.
10156 23:42:50.115661
10157 23:42:50.115734 MAC: 00:e0:4c:68:02:81
10158 23:42:50.115825
10159 23:42:50.119094 Sending DHCP discover... done.
10160 23:42:50.119204
10161 23:42:50.122301 Waiting for reply... done.
10162 23:42:50.122384
10163 23:42:50.125643 Sending DHCP request... done.
10164 23:42:50.125741
10165 23:42:50.130291 Waiting for reply... done.
10166 23:42:50.130383
10167 23:42:50.130486 My ip is 192.168.201.14
10168 23:42:50.130565
10169 23:42:50.133340 The DHCP server ip is 192.168.201.1
10170 23:42:50.133442
10171 23:42:50.139821 TFTP server IP predefined by user: 192.168.201.1
10172 23:42:50.139942
10173 23:42:50.146461 Bootfile predefined by user: 14172911/tftp-deploy-jrgn1tix/kernel/image.itb
10174 23:42:50.146571
10175 23:42:50.149897 Sending tftp read request... done.
10176 23:42:50.150003
10177 23:42:50.153464 Waiting for the transfer...
10178 23:42:50.153603
10179 23:42:50.676811 00000000 ################################################################
10180 23:42:50.676954
10181 23:42:51.208420 00080000 ################################################################
10182 23:42:51.208601
10183 23:42:51.750674 00100000 ################################################################
10184 23:42:51.750824
10185 23:42:52.285003 00180000 ################################################################
10186 23:42:52.285183
10187 23:42:52.818101 00200000 ################################################################
10188 23:42:52.818276
10189 23:42:53.349758 00280000 ################################################################
10190 23:42:53.349945
10191 23:42:53.887164 00300000 ################################################################
10192 23:42:53.887314
10193 23:42:54.426114 00380000 ################################################################
10194 23:42:54.426304
10195 23:42:54.949371 00400000 ################################################################
10196 23:42:54.949506
10197 23:42:55.484470 00480000 ################################################################
10198 23:42:55.484615
10199 23:42:56.026337 00500000 ################################################################
10200 23:42:56.026469
10201 23:42:56.586944 00580000 ################################################################
10202 23:42:56.587116
10203 23:42:57.131036 00600000 ################################################################
10204 23:42:57.131177
10205 23:42:57.663604 00680000 ################################################################
10206 23:42:57.663804
10207 23:42:58.200001 00700000 ################################################################
10208 23:42:58.200160
10209 23:42:58.749209 00780000 ################################################################
10210 23:42:58.749358
10211 23:42:59.280632 00800000 ################################################################
10212 23:42:59.280779
10213 23:42:59.809466 00880000 ################################################################
10214 23:42:59.809616
10215 23:43:00.338252 00900000 ################################################################
10216 23:43:00.338405
10217 23:43:00.890073 00980000 ################################################################
10218 23:43:00.890268
10219 23:43:01.424189 00a00000 ################################################################
10220 23:43:01.424345
10221 23:43:01.955863 00a80000 ################################################################
10222 23:43:01.955999
10223 23:43:02.500973 00b00000 ################################################################
10224 23:43:02.501134
10225 23:43:03.053998 00b80000 ################################################################
10226 23:43:03.054168
10227 23:43:03.594805 00c00000 ################################################################
10228 23:43:03.594940
10229 23:43:04.131065 00c80000 ################################################################
10230 23:43:04.131229
10231 23:43:04.676370 00d00000 ################################################################
10232 23:43:04.676522
10233 23:43:05.217653 00d80000 ################################################################
10234 23:43:05.217806
10235 23:43:05.765548 00e00000 ################################################################
10236 23:43:05.765689
10237 23:43:06.318449 00e80000 ################################################################
10238 23:43:06.318585
10239 23:43:06.851023 00f00000 ################################################################
10240 23:43:06.851168
10241 23:43:07.380795 00f80000 ################################################################
10242 23:43:07.380932
10243 23:43:07.915185 01000000 ################################################################
10244 23:43:07.915442
10245 23:43:08.456226 01080000 ################################################################
10246 23:43:08.456374
10247 23:43:09.003401 01100000 ################################################################
10248 23:43:09.003545
10249 23:43:09.537854 01180000 ################################################################
10250 23:43:09.538025
10251 23:43:10.078315 01200000 ################################################################
10252 23:43:10.078450
10253 23:43:10.626735 01280000 ################################################################
10254 23:43:10.626867
10255 23:43:11.171570 01300000 ################################################################
10256 23:43:11.171747
10257 23:43:11.840041 01380000 ################################################################
10258 23:43:11.840646
10259 23:43:12.541011 01400000 ################################################################
10260 23:43:12.541580
10261 23:43:13.255447 01480000 ################################################################
10262 23:43:13.255965
10263 23:43:13.880873 01500000 ################################################################
10264 23:43:13.881390
10265 23:43:14.473068 01580000 ################################################################
10266 23:43:14.473313
10267 23:43:15.089545 01600000 ################################################################
10268 23:43:15.090026
10269 23:43:15.789289 01680000 ################################################################
10270 23:43:15.789819
10271 23:43:16.508326 01700000 ################################################################
10272 23:43:16.508924
10273 23:43:17.144228 01780000 ################################################################
10274 23:43:17.144366
10275 23:43:17.792998 01800000 ################################################################
10276 23:43:17.793462
10277 23:43:18.362062 01880000 ################################################################
10278 23:43:18.362352
10279 23:43:18.979315 01900000 ################################################################
10280 23:43:18.979493
10281 23:43:19.589804 01980000 ################################################################
10282 23:43:19.590420
10283 23:43:20.280783 01a00000 ################################################################
10284 23:43:20.281306
10285 23:43:20.984620 01a80000 ################################################################
10286 23:43:20.985126
10287 23:43:21.682649 01b00000 ################################################################
10288 23:43:21.683153
10289 23:43:22.322377 01b80000 ################################################################
10290 23:43:22.322877
10291 23:43:23.018535 01c00000 ################################################################
10292 23:43:23.019033
10293 23:43:23.704828 01c80000 ################################################################
10294 23:43:23.704993
10295 23:43:24.400722 01d00000 ################################################################
10296 23:43:24.400889
10297 23:43:24.988289 01d80000 ################################################################
10298 23:43:24.988423
10299 23:43:25.415134 01e00000 ################################################ done.
10300 23:43:25.415267
10301 23:43:25.418116 The bootfile was 31845802 bytes long.
10302 23:43:25.418258
10303 23:43:25.421655 Sending tftp read request... done.
10304 23:43:25.421740
10305 23:43:25.421843 Waiting for the transfer...
10306 23:43:25.421945
10307 23:43:25.424805 00000000 # done.
10308 23:43:25.424892
10309 23:43:25.431807 Command line loaded dynamically from TFTP file: 14172911/tftp-deploy-jrgn1tix/kernel/cmdline
10310 23:43:25.431893
10311 23:43:25.455022 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172911/extract-nfsrootfs-_uzfte3l,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10312 23:43:25.455123
10313 23:43:25.455189 Loading FIT.
10314 23:43:25.455250
10315 23:43:25.457494 Image ramdisk-1 has 18735077 bytes.
10316 23:43:25.457570
10317 23:43:25.461101 Image fdt-1 has 47258 bytes.
10318 23:43:25.461177
10319 23:43:25.464537 Image kernel-1 has 13061430 bytes.
10320 23:43:25.464612
10321 23:43:25.474021 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10322 23:43:25.474139
10323 23:43:25.490902 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10324 23:43:25.490996
10325 23:43:25.497420 Choosing best match conf-1 for compat google,spherion-rev2.
10326 23:43:25.500867
10327 23:43:25.504880 Connected to device vid:did:rid of 1ae0:0028:00
10328 23:43:25.511942
10329 23:43:25.515772 tpm_get_response: command 0x17b, return code 0x0
10330 23:43:25.515866
10331 23:43:25.518923 ec_init: CrosEC protocol v3 supported (256, 248)
10332 23:43:25.523666
10333 23:43:25.526862 tpm_cleanup: add release locality here.
10334 23:43:25.526961
10335 23:43:25.527043 Shutting down all USB controllers.
10336 23:43:25.530173
10337 23:43:25.530260 Removing current net device
10338 23:43:25.530387
10339 23:43:25.536771 Exiting depthcharge with code 4 at timestamp: 71072966
10340 23:43:25.536862
10341 23:43:25.540268 LZMA decompressing kernel-1 to 0x821a6718
10342 23:43:25.540357
10343 23:43:25.543614 LZMA decompressing kernel-1 to 0x40000000
10344 23:43:27.153645
10345 23:43:27.153780 jumping to kernel
10346 23:43:27.154247 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10347 23:43:27.154345 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10348 23:43:27.154429 Setting prompt string to ['Linux version [0-9]']
10349 23:43:27.154499 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10350 23:43:27.154566 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10351 23:43:27.235129
10352 23:43:27.238385 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10353 23:43:27.241759 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10354 23:43:27.241853 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10355 23:43:27.241946 Setting prompt string to []
10356 23:43:27.242028 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10357 23:43:27.242123 Using line separator: #'\n'#
10358 23:43:27.242211 No login prompt set.
10359 23:43:27.242275 Parsing kernel messages
10360 23:43:27.242334 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10361 23:43:27.242443 [login-action] Waiting for messages, (timeout 00:03:43)
10362 23:43:27.242512 Waiting using forced prompt support (timeout 00:01:52)
10363 23:43:27.261417 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j217067-arm64-gcc-10-defconfig-arm64-chromebook-s48tj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024
10364 23:43:27.264830 [ 0.000000] random: crng init done
10365 23:43:27.271407 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10366 23:43:27.275021 [ 0.000000] efi: UEFI not found.
10367 23:43:27.281170 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10368 23:43:27.291216 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10369 23:43:27.297642 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10370 23:43:27.307730 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10371 23:43:27.314466 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10372 23:43:27.320859 [ 0.000000] printk: bootconsole [mtk8250] enabled
10373 23:43:27.327263 [ 0.000000] NUMA: No NUMA configuration found
10374 23:43:27.334480 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10375 23:43:27.337355 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10376 23:43:27.340684 [ 0.000000] Zone ranges:
10377 23:43:27.347377 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10378 23:43:27.350707 [ 0.000000] DMA32 empty
10379 23:43:27.357407 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10380 23:43:27.360397 [ 0.000000] Movable zone start for each node
10381 23:43:27.363916 [ 0.000000] Early memory node ranges
10382 23:43:27.370509 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10383 23:43:27.376870 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10384 23:43:27.383818 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10385 23:43:27.390091 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10386 23:43:27.396680 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10387 23:43:27.403271 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10388 23:43:27.459388 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10389 23:43:27.466140 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10390 23:43:27.472788 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10391 23:43:27.475962 [ 0.000000] psci: probing for conduit method from DT.
10392 23:43:27.483020 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10393 23:43:27.485872 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10394 23:43:27.492693 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10395 23:43:27.495945 [ 0.000000] psci: SMC Calling Convention v1.2
10396 23:43:27.502716 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10397 23:43:27.505678 [ 0.000000] Detected VIPT I-cache on CPU0
10398 23:43:27.512973 [ 0.000000] CPU features: detected: GIC system register CPU interface
10399 23:43:27.518985 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10400 23:43:27.525954 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10401 23:43:27.532330 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10402 23:43:27.542092 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10403 23:43:27.549166 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10404 23:43:27.551812 [ 0.000000] alternatives: applying boot alternatives
10405 23:43:27.558674 [ 0.000000] Fallback order for Node 0: 0
10406 23:43:27.565244 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10407 23:43:27.568461 [ 0.000000] Policy zone: Normal
10408 23:43:27.591681 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172911/extract-nfsrootfs-_uzfte3l,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10409 23:43:27.601493 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10410 23:43:27.612713 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10411 23:43:27.622572 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10412 23:43:27.629823 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10413 23:43:27.632326 <6>[ 0.000000] software IO TLB: area num 8.
10414 23:43:27.690353 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10415 23:43:27.840349 <6>[ 0.000000] Memory: 7945892K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406876K reserved, 32768K cma-reserved)
10416 23:43:27.846785 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10417 23:43:27.853038 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10418 23:43:27.856120 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10419 23:43:27.863264 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10420 23:43:27.869261 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10421 23:43:27.876395 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10422 23:43:27.882978 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10423 23:43:27.888878 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10424 23:43:27.896056 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10425 23:43:27.902292 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10426 23:43:27.905715 <6>[ 0.000000] GICv3: 608 SPIs implemented
10427 23:43:27.908573 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10428 23:43:27.915422 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10429 23:43:27.918499 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10430 23:43:27.925906 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10431 23:43:27.938523 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10432 23:43:27.951824 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10433 23:43:27.958210 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10434 23:43:27.967084 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10435 23:43:27.979690 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10436 23:43:27.986329 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10437 23:43:27.993695 <6>[ 0.009181] Console: colour dummy device 80x25
10438 23:43:28.003240 <6>[ 0.013909] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10439 23:43:28.009664 <6>[ 0.024415] pid_max: default: 32768 minimum: 301
10440 23:43:28.013463 <6>[ 0.029286] LSM: Security Framework initializing
10441 23:43:28.019674 <6>[ 0.034225] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10442 23:43:28.029313 <6>[ 0.042038] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10443 23:43:28.039815 <6>[ 0.051505] cblist_init_generic: Setting adjustable number of callback queues.
10444 23:43:28.042636 <6>[ 0.058949] cblist_init_generic: Setting shift to 3 and lim to 1.
10445 23:43:28.052495 <6>[ 0.065327] cblist_init_generic: Setting adjustable number of callback queues.
10446 23:43:28.058786 <6>[ 0.072754] cblist_init_generic: Setting shift to 3 and lim to 1.
10447 23:43:28.062446 <6>[ 0.079156] rcu: Hierarchical SRCU implementation.
10448 23:43:28.068953 <6>[ 0.084202] rcu: Max phase no-delay instances is 1000.
10449 23:43:28.075683 <6>[ 0.091241] EFI services will not be available.
10450 23:43:28.078593 <6>[ 0.096227] smp: Bringing up secondary CPUs ...
10451 23:43:28.087327 <6>[ 0.101277] Detected VIPT I-cache on CPU1
10452 23:43:28.094047 <6>[ 0.101348] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10453 23:43:28.100702 <6>[ 0.101381] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10454 23:43:28.104303 <6>[ 0.101715] Detected VIPT I-cache on CPU2
10455 23:43:28.113518 <6>[ 0.101766] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10456 23:43:28.120516 <6>[ 0.101782] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10457 23:43:28.123640 <6>[ 0.102039] Detected VIPT I-cache on CPU3
10458 23:43:28.130212 <6>[ 0.102085] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10459 23:43:28.136703 <6>[ 0.102099] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10460 23:43:28.143587 <6>[ 0.102404] CPU features: detected: Spectre-v4
10461 23:43:28.146592 <6>[ 0.102410] CPU features: detected: Spectre-BHB
10462 23:43:28.149953 <6>[ 0.102415] Detected PIPT I-cache on CPU4
10463 23:43:28.156639 <6>[ 0.102472] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10464 23:43:28.166052 <6>[ 0.102489] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10465 23:43:28.169378 <6>[ 0.102779] Detected PIPT I-cache on CPU5
10466 23:43:28.175919 <6>[ 0.102843] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10467 23:43:28.182735 <6>[ 0.102858] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10468 23:43:28.186121 <6>[ 0.103139] Detected PIPT I-cache on CPU6
10469 23:43:28.195649 <6>[ 0.103206] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10470 23:43:28.202434 <6>[ 0.103222] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10471 23:43:28.205857 <6>[ 0.103518] Detected PIPT I-cache on CPU7
10472 23:43:28.212712 <6>[ 0.103584] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10473 23:43:28.218784 <6>[ 0.103599] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10474 23:43:28.222316 <6>[ 0.103647] smp: Brought up 1 node, 8 CPUs
10475 23:43:28.228736 <6>[ 0.244961] SMP: Total of 8 processors activated.
10476 23:43:28.235768 <6>[ 0.249882] CPU features: detected: 32-bit EL0 Support
10477 23:43:28.241857 <6>[ 0.255245] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10478 23:43:28.248891 <6>[ 0.264100] CPU features: detected: Common not Private translations
10479 23:43:28.255392 <6>[ 0.270575] CPU features: detected: CRC32 instructions
10480 23:43:28.262012 <6>[ 0.275927] CPU features: detected: RCpc load-acquire (LDAPR)
10481 23:43:28.264925 <6>[ 0.281887] CPU features: detected: LSE atomic instructions
10482 23:43:28.271705 <6>[ 0.287668] CPU features: detected: Privileged Access Never
10483 23:43:28.278420 <6>[ 0.293448] CPU features: detected: RAS Extension Support
10484 23:43:28.285418 <6>[ 0.299057] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10485 23:43:28.288512 <6>[ 0.306276] CPU: All CPU(s) started at EL2
10486 23:43:28.294832 <6>[ 0.310592] alternatives: applying system-wide alternatives
10487 23:43:28.305229 <6>[ 0.321426] devtmpfs: initialized
10488 23:43:28.321074 <6>[ 0.330361] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10489 23:43:28.327597 <6>[ 0.340318] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10490 23:43:28.334017 <6>[ 0.348329] pinctrl core: initialized pinctrl subsystem
10491 23:43:28.337702 <6>[ 0.355022] DMI not present or invalid.
10492 23:43:28.343977 <6>[ 0.359434] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10493 23:43:28.353625 <6>[ 0.366295] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10494 23:43:28.360800 <6>[ 0.373875] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10495 23:43:28.370121 <6>[ 0.382094] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10496 23:43:28.373484 <6>[ 0.390337] audit: initializing netlink subsys (disabled)
10497 23:43:28.383066 <5>[ 0.396033] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10498 23:43:28.389685 <6>[ 0.396755] thermal_sys: Registered thermal governor 'step_wise'
10499 23:43:28.396581 <6>[ 0.404001] thermal_sys: Registered thermal governor 'power_allocator'
10500 23:43:28.399921 <6>[ 0.410254] cpuidle: using governor menu
10501 23:43:28.406281 <6>[ 0.421213] NET: Registered PF_QIPCRTR protocol family
10502 23:43:28.412933 <6>[ 0.426706] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10503 23:43:28.419654 <6>[ 0.433812] ASID allocator initialised with 32768 entries
10504 23:43:28.422576 <6>[ 0.440399] Serial: AMBA PL011 UART driver
10505 23:43:28.433150 <4>[ 0.449229] Trying to register duplicate clock ID: 134
10506 23:43:28.492687 <6>[ 0.512237] KASLR enabled
10507 23:43:28.507273 <6>[ 0.519948] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10508 23:43:28.513691 <6>[ 0.526960] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10509 23:43:28.520084 <6>[ 0.533447] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10510 23:43:28.526368 <6>[ 0.540450] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10511 23:43:28.533331 <6>[ 0.546937] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10512 23:43:28.540053 <6>[ 0.553945] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10513 23:43:28.546553 <6>[ 0.560433] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10514 23:43:28.553341 <6>[ 0.567437] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10515 23:43:28.556530 <6>[ 0.574898] ACPI: Interpreter disabled.
10516 23:43:28.565126 <6>[ 0.581318] iommu: Default domain type: Translated
10517 23:43:28.571685 <6>[ 0.586467] iommu: DMA domain TLB invalidation policy: strict mode
10518 23:43:28.575112 <5>[ 0.593129] SCSI subsystem initialized
10519 23:43:28.581488 <6>[ 0.597377] usbcore: registered new interface driver usbfs
10520 23:43:28.588450 <6>[ 0.603106] usbcore: registered new interface driver hub
10521 23:43:28.591532 <6>[ 0.608659] usbcore: registered new device driver usb
10522 23:43:28.598890 <6>[ 0.614776] pps_core: LinuxPPS API ver. 1 registered
10523 23:43:28.608521 <6>[ 0.619969] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10524 23:43:28.612353 <6>[ 0.629313] PTP clock support registered
10525 23:43:28.614848 <6>[ 0.633555] EDAC MC: Ver: 3.0.0
10526 23:43:28.622902 <6>[ 0.638744] FPGA manager framework
10527 23:43:28.626181 <6>[ 0.642418] Advanced Linux Sound Architecture Driver Initialized.
10528 23:43:28.629856 <6>[ 0.649194] vgaarb: loaded
10529 23:43:28.636394 <6>[ 0.652354] clocksource: Switched to clocksource arch_sys_counter
10530 23:43:28.642937 <5>[ 0.658797] VFS: Disk quotas dquot_6.6.0
10531 23:43:28.649801 <6>[ 0.662980] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10532 23:43:28.652772 <6>[ 0.670172] pnp: PnP ACPI: disabled
10533 23:43:28.660415 <6>[ 0.676843] NET: Registered PF_INET protocol family
10534 23:43:28.670463 <6>[ 0.682430] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10535 23:43:28.682399 <6>[ 0.694736] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10536 23:43:28.692111 <6>[ 0.703552] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10537 23:43:28.698520 <6>[ 0.711525] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10538 23:43:28.708528 <6>[ 0.720223] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10539 23:43:28.715051 <6>[ 0.729972] TCP: Hash tables configured (established 65536 bind 65536)
10540 23:43:28.721478 <6>[ 0.736838] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10541 23:43:28.731209 <6>[ 0.744032] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10542 23:43:28.737870 <6>[ 0.751738] NET: Registered PF_UNIX/PF_LOCAL protocol family
10543 23:43:28.744793 <6>[ 0.757881] RPC: Registered named UNIX socket transport module.
10544 23:43:28.748541 <6>[ 0.764038] RPC: Registered udp transport module.
10545 23:43:28.754289 <6>[ 0.768969] RPC: Registered tcp transport module.
10546 23:43:28.760932 <6>[ 0.773902] RPC: Registered tcp NFSv4.1 backchannel transport module.
10547 23:43:28.764498 <6>[ 0.780570] PCI: CLS 0 bytes, default 64
10548 23:43:28.767734 <6>[ 0.784957] Unpacking initramfs...
10549 23:43:28.777235 <6>[ 0.788670] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10550 23:43:28.784018 <6>[ 0.797289] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10551 23:43:28.790512 <6>[ 0.806092] kvm [1]: IPA Size Limit: 40 bits
10552 23:43:28.794066 <6>[ 0.810620] kvm [1]: GICv3: no GICV resource entry
10553 23:43:28.800283 <6>[ 0.815640] kvm [1]: disabling GICv2 emulation
10554 23:43:28.803961 <6>[ 0.820328] kvm [1]: GIC system register CPU interface enabled
10555 23:43:28.810288 <6>[ 0.826483] kvm [1]: vgic interrupt IRQ18
10556 23:43:28.817052 <6>[ 0.832430] kvm [1]: VHE mode initialized successfully
10557 23:43:28.823442 <5>[ 0.838831] Initialise system trusted keyrings
10558 23:43:28.830323 <6>[ 0.843609] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10559 23:43:28.838242 <6>[ 0.853645] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10560 23:43:28.844696 <5>[ 0.859994] NFS: Registering the id_resolver key type
10561 23:43:28.847699 <5>[ 0.865294] Key type id_resolver registered
10562 23:43:28.854076 <5>[ 0.869708] Key type id_legacy registered
10563 23:43:28.860329 <6>[ 0.873988] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10564 23:43:28.867487 <6>[ 0.880912] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10565 23:43:28.873626 <6>[ 0.888620] 9p: Installing v9fs 9p2000 file system support
10566 23:43:28.910726 <5>[ 0.927329] Key type asymmetric registered
10567 23:43:28.914633 <5>[ 0.931656] Asymmetric key parser 'x509' registered
10568 23:43:28.923939 <6>[ 0.936783] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10569 23:43:28.927235 <6>[ 0.944395] io scheduler mq-deadline registered
10570 23:43:28.930372 <6>[ 0.949152] io scheduler kyber registered
10571 23:43:28.949884 <6>[ 0.966166] EINJ: ACPI disabled.
10572 23:43:28.982718 <4>[ 0.992196] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10573 23:43:28.992896 <4>[ 1.002816] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10574 23:43:29.007881 <6>[ 1.023634] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10575 23:43:29.015300 <6>[ 1.031560] printk: console [ttyS0] disabled
10576 23:43:29.043405 <6>[ 1.056195] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10577 23:43:29.050457 <6>[ 1.065670] printk: console [ttyS0] enabled
10578 23:43:29.053553 <6>[ 1.065670] printk: console [ttyS0] enabled
10579 23:43:29.060305 <6>[ 1.074565] printk: bootconsole [mtk8250] disabled
10580 23:43:29.063485 <6>[ 1.074565] printk: bootconsole [mtk8250] disabled
10581 23:43:29.069787 <6>[ 1.085626] SuperH (H)SCI(F) driver initialized
10582 23:43:29.073050 <6>[ 1.090892] msm_serial: driver initialized
10583 23:43:29.087271 <6>[ 1.099794] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10584 23:43:29.097176 <6>[ 1.108348] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10585 23:43:29.103624 <6>[ 1.116891] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10586 23:43:29.113522 <6>[ 1.125518] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10587 23:43:29.123842 <6>[ 1.134224] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10588 23:43:29.129916 <6>[ 1.142943] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10589 23:43:29.140032 <6>[ 1.151483] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10590 23:43:29.146661 <6>[ 1.160284] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10591 23:43:29.156047 <6>[ 1.168827] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10592 23:43:29.168114 <6>[ 1.184440] loop: module loaded
10593 23:43:29.174812 <6>[ 1.190321] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10594 23:43:29.197244 <4>[ 1.213504] mtk-pmic-keys: Failed to locate of_node [id: -1]
10595 23:43:29.204145 <6>[ 1.220340] megasas: 07.719.03.00-rc1
10596 23:43:29.213633 <6>[ 1.229900] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10597 23:43:29.224234 <6>[ 1.239731] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10598 23:43:29.240228 <6>[ 1.256209] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10599 23:43:29.299780 <6>[ 1.309196] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10600 23:43:29.557675 <6>[ 1.573767] Freeing initrd memory: 18292K
10601 23:43:29.568872 <6>[ 1.585210] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10602 23:43:29.580503 <6>[ 1.596075] tun: Universal TUN/TAP device driver, 1.6
10603 23:43:29.583222 <6>[ 1.602128] thunder_xcv, ver 1.0
10604 23:43:29.586538 <6>[ 1.605633] thunder_bgx, ver 1.0
10605 23:43:29.590121 <6>[ 1.609127] nicpf, ver 1.0
10606 23:43:29.600191 <6>[ 1.613131] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10607 23:43:29.603957 <6>[ 1.620607] hns3: Copyright (c) 2017 Huawei Corporation.
10608 23:43:29.610525 <6>[ 1.626197] hclge is initializing
10609 23:43:29.614075 <6>[ 1.629780] e1000: Intel(R) PRO/1000 Network Driver
10610 23:43:29.620046 <6>[ 1.634909] e1000: Copyright (c) 1999-2006 Intel Corporation.
10611 23:43:29.623435 <6>[ 1.640921] e1000e: Intel(R) PRO/1000 Network Driver
10612 23:43:29.630114 <6>[ 1.646136] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10613 23:43:29.636999 <6>[ 1.652324] igb: Intel(R) Gigabit Ethernet Network Driver
10614 23:43:29.643796 <6>[ 1.657974] igb: Copyright (c) 2007-2014 Intel Corporation.
10615 23:43:29.650219 <6>[ 1.663809] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10616 23:43:29.656810 <6>[ 1.670327] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10617 23:43:29.659701 <6>[ 1.676784] sky2: driver version 1.30
10618 23:43:29.666665 <6>[ 1.681698] usbcore: registered new device driver r8152-cfgselector
10619 23:43:29.673165 <6>[ 1.688233] usbcore: registered new interface driver r8152
10620 23:43:29.679665 <6>[ 1.694052] VFIO - User Level meta-driver version: 0.3
10621 23:43:29.686131 <6>[ 1.702281] usbcore: registered new interface driver usb-storage
10622 23:43:29.692731 <6>[ 1.708725] usbcore: registered new device driver onboard-usb-hub
10623 23:43:29.701849 <6>[ 1.717861] mt6397-rtc mt6359-rtc: registered as rtc0
10624 23:43:29.711725 <6>[ 1.723322] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T23:43:29 UTC (1717544609)
10625 23:43:29.715204 <6>[ 1.732889] i2c_dev: i2c /dev entries driver
10626 23:43:29.732065 <6>[ 1.744646] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10627 23:43:29.739039 <4>[ 1.753367] cpu cpu0: supply cpu not found, using dummy regulator
10628 23:43:29.745255 <4>[ 1.759795] cpu cpu1: supply cpu not found, using dummy regulator
10629 23:43:29.751955 <4>[ 1.766226] cpu cpu2: supply cpu not found, using dummy regulator
10630 23:43:29.758127 <4>[ 1.772624] cpu cpu3: supply cpu not found, using dummy regulator
10631 23:43:29.765079 <4>[ 1.779020] cpu cpu4: supply cpu not found, using dummy regulator
10632 23:43:29.771810 <4>[ 1.785418] cpu cpu5: supply cpu not found, using dummy regulator
10633 23:43:29.778481 <4>[ 1.791812] cpu cpu6: supply cpu not found, using dummy regulator
10634 23:43:29.784818 <4>[ 1.798224] cpu cpu7: supply cpu not found, using dummy regulator
10635 23:43:29.803936 <6>[ 1.819859] cpu cpu0: EM: created perf domain
10636 23:43:29.807066 <6>[ 1.824792] cpu cpu4: EM: created perf domain
10637 23:43:29.814451 <6>[ 1.830367] sdhci: Secure Digital Host Controller Interface driver
10638 23:43:29.821120 <6>[ 1.836799] sdhci: Copyright(c) Pierre Ossman
10639 23:43:29.827559 <6>[ 1.841758] Synopsys Designware Multimedia Card Interface Driver
10640 23:43:29.834147 <6>[ 1.848398] sdhci-pltfm: SDHCI platform and OF driver helper
10641 23:43:29.837658 <6>[ 1.848508] mmc0: CQHCI version 5.10
10642 23:43:29.844157 <6>[ 1.858300] ledtrig-cpu: registered to indicate activity on CPUs
10643 23:43:29.850519 <6>[ 1.865335] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10644 23:43:29.857256 <6>[ 1.872390] usbcore: registered new interface driver usbhid
10645 23:43:29.860251 <6>[ 1.878226] usbhid: USB HID core driver
10646 23:43:29.866905 <6>[ 1.882387] spi_master spi0: will run message pump with realtime priority
10647 23:43:29.911482 <6>[ 1.921002] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10648 23:43:29.930746 <6>[ 1.937323] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10649 23:43:29.934129 <6>[ 1.949287] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17014
10650 23:43:29.943465 <6>[ 1.959219] cros-ec-spi spi0.0: Chrome EC device registered
10651 23:43:29.949916 <6>[ 1.965212] mmc0: Command Queue Engine enabled
10652 23:43:29.956381 <6>[ 1.969946] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10653 23:43:29.959840 <6>[ 1.977521] mmcblk0: mmc0:0001 DA4128 116 GiB
10654 23:43:29.972868 <6>[ 1.988725] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10655 23:43:29.983023 <6>[ 1.992624] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10656 23:43:29.989206 <6>[ 1.995837] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10657 23:43:29.992553 <6>[ 2.005186] NET: Registered PF_PACKET protocol family
10658 23:43:29.998793 <6>[ 2.009846] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10659 23:43:30.002600 <6>[ 2.014547] 9pnet: Installing 9P2000 support
10660 23:43:30.008820 <6>[ 2.020296] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10661 23:43:30.015696 <5>[ 2.024241] Key type dns_resolver registered
10662 23:43:30.018757 <6>[ 2.035707] registered taskstats version 1
10663 23:43:30.025527 <5>[ 2.040096] Loading compiled-in X.509 certificates
10664 23:43:30.051232 <4>[ 2.060904] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10665 23:43:30.061221 <4>[ 2.071634] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10666 23:43:30.079708 <6>[ 2.095781] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10667 23:43:30.086539 <6>[ 2.102650] xhci-mtk 11200000.usb: xHCI Host Controller
10668 23:43:30.093430 <6>[ 2.108172] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10669 23:43:30.103415 <6>[ 2.116084] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10670 23:43:30.110046 <6>[ 2.125554] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10671 23:43:30.117120 <6>[ 2.131765] xhci-mtk 11200000.usb: xHCI Host Controller
10672 23:43:30.123031 <6>[ 2.137269] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10673 23:43:30.129868 <6>[ 2.144921] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10674 23:43:30.137317 <6>[ 2.152747] hub 1-0:1.0: USB hub found
10675 23:43:30.140125 <6>[ 2.156769] hub 1-0:1.0: 1 port detected
10676 23:43:30.150060 <6>[ 2.161050] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10677 23:43:30.153182 <6>[ 2.169769] hub 2-0:1.0: USB hub found
10678 23:43:30.156353 <6>[ 2.173789] hub 2-0:1.0: 1 port detected
10679 23:43:30.164496 <6>[ 2.180889] mtk-msdc 11f70000.mmc: Got CD GPIO
10680 23:43:30.181932 <6>[ 2.194641] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10681 23:43:30.188689 <6>[ 2.202677] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10682 23:43:30.198132 <4>[ 2.210578] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10683 23:43:30.208862 <6>[ 2.220104] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10684 23:43:30.214912 <6>[ 2.228181] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10685 23:43:30.221328 <6>[ 2.236208] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10686 23:43:30.231301 <6>[ 2.244124] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10687 23:43:30.238310 <6>[ 2.251941] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10688 23:43:30.247905 <6>[ 2.259757] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10689 23:43:30.258113 <6>[ 2.270207] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10690 23:43:30.264637 <6>[ 2.278565] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10691 23:43:30.274623 <6>[ 2.286911] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10692 23:43:30.280972 <6>[ 2.295251] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10693 23:43:30.291320 <6>[ 2.303589] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10694 23:43:30.297400 <6>[ 2.311927] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10695 23:43:30.307907 <6>[ 2.320265] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10696 23:43:30.314453 <6>[ 2.328602] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10697 23:43:30.324298 <6>[ 2.336940] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10698 23:43:30.333972 <6>[ 2.345277] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10699 23:43:30.341116 <6>[ 2.353615] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10700 23:43:30.350569 <6>[ 2.361953] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10701 23:43:30.357477 <6>[ 2.370291] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10702 23:43:30.366883 <6>[ 2.378628] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10703 23:43:30.373984 <6>[ 2.386966] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10704 23:43:30.380176 <6>[ 2.395698] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10705 23:43:30.386944 <6>[ 2.402880] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10706 23:43:30.394032 <6>[ 2.409654] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10707 23:43:30.403741 <6>[ 2.416422] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10708 23:43:30.410251 <6>[ 2.423352] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10709 23:43:30.416588 <6>[ 2.430209] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10710 23:43:30.426703 <6>[ 2.439340] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10711 23:43:30.436527 <6>[ 2.448460] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10712 23:43:30.446318 <6>[ 2.457755] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10713 23:43:30.456618 <6>[ 2.467224] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10714 23:43:30.466311 <6>[ 2.476691] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10715 23:43:30.473056 <6>[ 2.485811] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10716 23:43:30.482391 <6>[ 2.495276] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10717 23:43:30.492827 <6>[ 2.504395] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10718 23:43:30.502845 <6>[ 2.513689] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10719 23:43:30.512364 <6>[ 2.523849] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10720 23:43:30.523200 <6>[ 2.535360] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10721 23:43:30.529209 <6>[ 2.545118] Trying to probe devices needed for running init ...
10722 23:43:30.564110 <6>[ 2.576642] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10723 23:43:30.716831 <6>[ 2.732968] hub 1-1:1.0: USB hub found
10724 23:43:30.720204 <6>[ 2.737324] hub 1-1:1.0: 4 ports detected
10725 23:43:30.728273 <6>[ 2.744043] hub 1-1:1.0: USB hub found
10726 23:43:30.730734 <6>[ 2.748518] hub 1-1:1.0: 4 ports detected
10727 23:43:30.843722 <6>[ 2.856782] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10728 23:43:30.868414 <6>[ 2.884707] hub 2-1:1.0: USB hub found
10729 23:43:30.871739 <6>[ 2.889057] hub 2-1:1.0: 3 ports detected
10730 23:43:30.879363 <6>[ 2.896041] hub 2-1:1.0: USB hub found
10731 23:43:30.883117 <6>[ 2.900540] hub 2-1:1.0: 3 ports detected
10732 23:43:31.059811 <6>[ 3.072654] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10733 23:43:31.192326 <6>[ 3.208540] hub 1-1.4:1.0: USB hub found
10734 23:43:31.195828 <6>[ 3.213168] hub 1-1.4:1.0: 2 ports detected
10735 23:43:31.204499 <6>[ 3.220536] hub 1-1.4:1.0: USB hub found
10736 23:43:31.207580 <6>[ 3.225087] hub 1-1.4:1.0: 2 ports detected
10737 23:43:31.275863 <6>[ 3.288818] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10738 23:43:31.384692 <6>[ 3.397299] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10739 23:43:31.420550 <4>[ 3.433401] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10740 23:43:31.430228 <4>[ 3.442494] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10741 23:43:31.465947 <6>[ 3.482219] r8152 2-1.3:1.0 eth0: v1.12.13
10742 23:43:31.503628 <6>[ 3.516671] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10743 23:43:31.695329 <6>[ 3.708497] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10744 23:43:33.130844 <6>[ 5.146894] r8152 2-1.3:1.0 eth0: carrier on
10745 23:43:36.147818 <5>[ 5.172464] Sending DHCP requests .., OK
10746 23:43:36.153988 <6>[ 8.168741] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10747 23:43:36.157515 <6>[ 8.177025] IP-Config: Complete:
10748 23:43:36.170284 <6>[ 8.180524] device=eth0, hwaddr=00:e0:4c:68:02:81, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10749 23:43:36.177366 <6>[ 8.191229] host=mt8192-asurada-spherion-r0-cbg-9, domain=lava-rack, nis-domain=(none)
10750 23:43:36.183277 <6>[ 8.199845] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10751 23:43:36.190059 <6>[ 8.199854] nameserver0=192.168.201.1
10752 23:43:36.193557 <6>[ 8.211995] clk: Disabling unused clocks
10753 23:43:36.197207 <6>[ 8.217532] ALSA device list:
10754 23:43:36.203350 <6>[ 8.220779] No soundcards found.
10755 23:43:36.211940 <6>[ 8.228618] Freeing unused kernel memory: 8512K
10756 23:43:36.214988 <6>[ 8.233592] Run /init as init process
10757 23:43:36.225630 Loading, please wait...
10758 23:43:36.255821 Starting systemd-udevd version 252.22-1~deb12u1
10759 23:43:36.529314 <6>[ 8.543158] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10760 23:43:36.539492 <6>[ 8.556067] remoteproc remoteproc0: scp is available
10761 23:43:36.545734 <6>[ 8.562604] remoteproc remoteproc0: powering up scp
10762 23:43:36.555605 <6>[ 8.567784] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10763 23:43:36.558980 <6>[ 8.576263] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10764 23:43:36.568948 <6>[ 8.577277] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10765 23:43:36.575539 <6>[ 8.589677] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10766 23:43:36.585800 <6>[ 8.599061] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10767 23:43:36.592114 <6>[ 8.608246] mc: Linux media interface: v0.10
10768 23:43:36.599061 <4>[ 8.608832] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10769 23:43:36.604831 <6>[ 8.613896] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10770 23:43:36.611640 <4>[ 8.620877] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10771 23:43:36.621574 <3>[ 8.624144] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10772 23:43:36.627971 <3>[ 8.624153] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10773 23:43:36.638179 <3>[ 8.624157] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10774 23:43:36.644534 <3>[ 8.624207] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10775 23:43:36.654498 <3>[ 8.624210] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10776 23:43:36.661261 <3>[ 8.624213] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10777 23:43:36.671140 <3>[ 8.624217] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10778 23:43:36.678157 <3>[ 8.624220] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10779 23:43:36.684854 <3>[ 8.624236] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10780 23:43:36.694566 <3>[ 8.624258] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 23:43:36.701418 <3>[ 8.624261] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 23:43:36.711034 <3>[ 8.624264] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10783 23:43:36.717854 <3>[ 8.624287] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 23:43:36.727969 <3>[ 8.624294] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10785 23:43:36.734087 <3>[ 8.624297] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10786 23:43:36.744098 <3>[ 8.624302] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10787 23:43:36.750602 <3>[ 8.624305] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10788 23:43:36.757680 <3>[ 8.624316] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10789 23:43:36.764413 <6>[ 8.662036] videodev: Linux video capture interface: v2.00
10790 23:43:36.770821 <6>[ 8.707323] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10791 23:43:36.780647 <6>[ 8.707364] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10792 23:43:36.787375 <6>[ 8.707372] remoteproc remoteproc0: remote processor scp is now up
10793 23:43:36.793969 <6>[ 8.725959] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10794 23:43:36.804220 <6>[ 8.740000] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10795 23:43:36.810894 <6>[ 8.740941] pci_bus 0000:00: root bus resource [bus 00-ff]
10796 23:43:36.817475 <6>[ 8.742259] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10797 23:43:36.826876 <6>[ 8.744837] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10798 23:43:36.834293 <4>[ 8.749031] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10799 23:43:36.840333 <4>[ 8.749031] Fallback method does not support PEC.
10800 23:43:36.850278 <6>[ 8.749183] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10801 23:43:36.857328 <6>[ 8.756870] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10802 23:43:36.863772 <3>[ 8.780589] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10803 23:43:36.873771 <6>[ 8.781188] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10804 23:43:36.884008 <6>[ 8.785053] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10805 23:43:36.886969 <6>[ 8.809299] Bluetooth: Core ver 2.22
10806 23:43:36.893252 <6>[ 8.816151] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10807 23:43:36.900426 <6>[ 8.825856] NET: Registered PF_BLUETOOTH protocol family
10808 23:43:36.906906 <6>[ 8.831543] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10809 23:43:36.913464 <6>[ 8.839780] Bluetooth: HCI device and connection manager initialized
10810 23:43:36.919954 <6>[ 8.839794] Bluetooth: HCI socket layer initialized
10811 23:43:36.923091 <6>[ 8.848106] pci 0000:00:00.0: supports D1 D2
10812 23:43:36.930134 <6>[ 8.861665] Bluetooth: L2CAP socket layer initialized
10813 23:43:36.936688 <6>[ 8.870694] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10814 23:43:36.943181 <6>[ 8.871651] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10815 23:43:36.956279 <6>[ 8.872926] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10816 23:43:36.959451 <6>[ 8.873258] usbcore: registered new interface driver uvcvideo
10817 23:43:36.966156 <6>[ 8.877823] Bluetooth: SCO socket layer initialized
10818 23:43:36.976286 <3>[ 8.884200] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10819 23:43:36.982648 <6>[ 8.887649] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10820 23:43:36.989069 <6>[ 8.916811] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10821 23:43:36.996042 <6>[ 8.921604] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10822 23:43:37.002402 <6>[ 8.941110] usbcore: registered new interface driver btusb
10823 23:43:37.012576 <4>[ 8.942140] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10824 23:43:37.018983 <3>[ 8.942150] Bluetooth: hci0: Failed to load firmware file (-2)
10825 23:43:37.025409 <3>[ 8.942154] Bluetooth: hci0: Failed to set up firmware (-2)
10826 23:43:37.035388 <4>[ 8.942159] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10827 23:43:37.041868 <6>[ 8.945210] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10828 23:43:37.048396 <6>[ 9.063749] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10829 23:43:37.055017 <6>[ 9.071232] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10830 23:43:37.061928 <6>[ 9.078809] pci 0000:01:00.0: supports D1 D2
10831 23:43:37.068298 <6>[ 9.083327] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10832 23:43:37.086756 <6>[ 9.100548] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10833 23:43:37.093955 <6>[ 9.107468] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10834 23:43:37.100039 <6>[ 9.115547] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10835 23:43:37.109899 <6>[ 9.123547] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10836 23:43:37.116251 <6>[ 9.131548] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10837 23:43:37.126052 <6>[ 9.139558] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10838 23:43:37.129639 <6>[ 9.147559] pci 0000:00:00.0: PCI bridge to [bus 01]
10839 23:43:37.139810 <6>[ 9.152775] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10840 23:43:37.146364 <6>[ 9.160897] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10841 23:43:37.152974 <6>[ 9.167717] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10842 23:43:37.159432 <6>[ 9.174495] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10843 23:43:37.174265 <5>[ 9.187835] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10844 23:43:37.197814 <5>[ 9.211690] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10845 23:43:37.204924 <5>[ 9.218757] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10846 23:43:37.214240 <4>[ 9.227172] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10847 23:43:37.217951 <6>[ 9.236045] cfg80211: failed to load regulatory.db
10848 23:43:37.258925 <6>[ 9.272592] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10849 23:43:37.265452 <6>[ 9.280110] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10850 23:43:37.287755 <6>[ 9.304598] mt7921e 0000:01:00.0: ASIC revision: 79610010
10851 23:43:37.390191 <6>[ 9.404054] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10852 23:43:37.393924 <6>[ 9.404054]
10853 23:43:37.397319 Begin: Loading essential drivers ... done.
10854 23:43:37.400127 Begin: Running /scripts/init-premount ... done.
10855 23:43:37.407094 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10856 23:43:37.416627 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10857 23:43:37.420057 Device /sys/class/net/eth0 found
10858 23:43:37.420480 done.
10859 23:43:37.432741 Begin: Waiting up to 180 secs for any network device to become available ... done.
10860 23:43:37.487581 IP-Config: eth0 hardware address 00:e0:4c:68:02:81 mtu 1500 DHCP
10861 23:43:37.495164 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10862 23:43:37.502157 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10863 23:43:37.508290 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10864 23:43:37.515223 host : mt8192-asurada-spherion-r0-cbg-9
10865 23:43:37.521782 domain : lava-rack
10866 23:43:37.524895 rootserver: 192.168.201.1 rootpath:
10867 23:43:37.528195 filename :
10868 23:43:37.657190 <6>[ 9.671136] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10869 23:43:37.683890 done.
10870 23:43:37.692877 Begin: Running /scripts/nfs-bottom ... done.
10871 23:43:37.710024 Begin: Running /scripts/init-bottom ... done.
10872 23:43:39.093649 <6>[ 11.111293] NET: Registered PF_INET6 protocol family
10873 23:43:39.100952 <6>[ 11.118488] Segment Routing with IPv6
10874 23:43:39.104295 <6>[ 11.122447] In-situ OAM (IOAM) with IPv6
10875 23:43:39.284623 <30>[ 11.275592] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10876 23:43:39.291508 <30>[ 11.308763] systemd[1]: Detected architecture arm64.
10877 23:43:39.302211
10878 23:43:39.305629 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10879 23:43:39.306206
10880 23:43:39.334024 <30>[ 11.350895] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10881 23:43:40.536557 <30>[ 12.550300] systemd[1]: Queued start job for default target graphical.target.
10882 23:43:40.580193 <30>[ 12.593822] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10883 23:43:40.586344 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10884 23:43:40.608937 <30>[ 12.622432] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10885 23:43:40.618873 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10886 23:43:40.636035 <30>[ 12.649995] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10887 23:43:40.646037 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10888 23:43:40.664079 <30>[ 12.678014] systemd[1]: Created slice user.slice - User and Session Slice.
10889 23:43:40.670755 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10890 23:43:40.694369 <30>[ 12.704953] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10891 23:43:40.704614 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10892 23:43:40.722233 <30>[ 12.732875] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10893 23:43:40.728992 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10894 23:43:40.757289 <30>[ 12.761314] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10895 23:43:40.767282 <30>[ 12.781226] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10896 23:43:40.773930 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10897 23:43:40.790991 <30>[ 12.804638] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10898 23:43:40.797675 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10899 23:43:40.815249 <30>[ 12.828713] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10900 23:43:40.824501 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10901 23:43:40.839119 <30>[ 12.856730] systemd[1]: Reached target paths.target - Path Units.
10902 23:43:40.849053 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10903 23:43:40.867096 <30>[ 12.881110] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10904 23:43:40.873540 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10905 23:43:40.887402 <30>[ 12.904650] systemd[1]: Reached target slices.target - Slice Units.
10906 23:43:40.897590 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10907 23:43:40.912293 <30>[ 12.929122] systemd[1]: Reached target swap.target - Swaps.
10908 23:43:40.918452 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10909 23:43:40.939696 <30>[ 12.953167] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10910 23:43:40.948920 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10911 23:43:40.967856 <30>[ 12.981635] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10912 23:43:40.977832 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10913 23:43:40.998584 <30>[ 13.012310] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10914 23:43:41.008323 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10915 23:43:41.024681 <30>[ 13.038432] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10916 23:43:41.034736 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10917 23:43:41.051297 <30>[ 13.065346] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10918 23:43:41.058284 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10919 23:43:41.076616 <30>[ 13.090550] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10920 23:43:41.086345 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10921 23:43:41.107240 <30>[ 13.121247] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10922 23:43:41.116998 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10923 23:43:41.135165 <30>[ 13.149163] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10924 23:43:41.144789 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10925 23:43:41.203033 <30>[ 13.216861] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10926 23:43:41.209052 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10927 23:43:41.231321 <30>[ 13.245278] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10928 23:43:41.238034 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10929 23:43:41.290606 <30>[ 13.304864] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10930 23:43:41.297204 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10931 23:43:41.321714 <30>[ 13.329218] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10932 23:43:41.337102 <30>[ 13.351166] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10933 23:43:41.347582 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10934 23:43:41.368446 <30>[ 13.382069] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10935 23:43:41.374689 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10936 23:43:41.398717 <30>[ 13.412248] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10937 23:43:41.404902 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10938 23:43:41.426815 <30>[ 13.440713] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10939 23:43:41.433444 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10940 23:43:41.449709 <6>[ 13.463659] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10941 23:43:41.463657 <30>[ 13.477667] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10942 23:43:41.473556 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10943 23:43:41.496373 <30>[ 13.510080] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10944 23:43:41.502954 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10945 23:43:41.528351 <30>[ 13.542017] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10946 23:43:41.537482 Starting [0;1;39mmodprobe@loop.ser…e<6>[ 13.553585] fuse: init (API version 7.37)
10947 23:43:41.541002 [0m - Load Kernel Module loop...
10948 23:43:41.567349 <30>[ 13.581311] systemd[1]: Starting systemd-journald.service - Journal Service...
10949 23:43:41.573631 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10950 23:43:41.627152 <30>[ 13.641295] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10951 23:43:41.633965 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10952 23:43:41.663315 <30>[ 13.674041] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10953 23:43:41.669631 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10954 23:43:41.697699 <30>[ 13.711484] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10955 23:43:41.707170 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10956 23:43:41.729828 <30>[ 13.743975] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10957 23:43:41.739839 <3>[ 13.753013] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 23:43:41.746891 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10959 23:43:41.773249 <3>[ 13.786914] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10960 23:43:41.779531 <30>[ 13.786948] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10961 23:43:41.789659 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10962 23:43:41.807258 <30>[ 13.820908] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10963 23:43:41.817380 [[0;32m OK [0m] Mounted [0;<3>[ 13.831126] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10964 23:43:41.824129 1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10965 23:43:41.844032 <30>[ 13.857167] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10966 23:43:41.850371 <3>[ 13.863516] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 23:43:41.860460 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10968 23:43:41.879678 <30>[ 13.893824] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10969 23:43:41.890039 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10970 23:43:41.896534 <3>[ 13.910490] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 23:43:41.907833 <30>[ 13.921569] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10972 23:43:41.914471 <30>[ 13.929424] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10973 23:43:41.924290 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10974 23:43:41.934003 <3>[ 13.948387] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 23:43:41.943860 <30>[ 13.958084] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10976 23:43:41.951199 <30>[ 13.966052] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10977 23:43:41.961143 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10978 23:43:41.967866 <3>[ 13.981536] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 23:43:41.980711 <30>[ 13.994845] systemd[1]: modprobe@drm.service: Deactivated successfully.
10980 23:43:41.987779 <30>[ 14.002544] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10981 23:43:42.000832 [[0;32m OK [0m] Finished [0<3>[ 14.012525] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 23:43:42.004055 ;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10983 23:43:42.024530 <30>[ 14.038785] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10984 23:43:42.031119 <3>[ 14.042947] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 23:43:42.040993 <30>[ 14.046867] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10986 23:43:42.051407 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10987 23:43:42.062025 <3>[ 14.076293] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10988 23:43:42.073207 <30>[ 14.086753] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10989 23:43:42.079450 <30>[ 14.094455] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10990 23:43:42.093250 [[0;32m OK [0m] Finished [0;1;39mmodprobe@f<3>[ 14.106046] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10991 23:43:42.096627 use.service[0m - Load Kernel Module fuse.
10992 23:43:42.116634 <30>[ 14.129839] systemd[1]: modprobe@loop.service: Deactivated successfully.
10993 23:43:42.122579 <30>[ 14.137738] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10994 23:43:42.133129 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10995 23:43:42.154870 <4>[ 14.162120] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10996 23:43:42.161637 <3>[ 14.177775] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -6
10997 23:43:42.171269 <30>[ 14.178614] systemd[1]: Started systemd-journald.service - Journal Service.
10998 23:43:42.177775 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10999 23:43:42.202982 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11000 23:43:42.220051 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11001 23:43:42.239758 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11002 23:43:42.259695 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11003 23:43:42.282284 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11004 23:43:42.351193 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11005 23:43:42.374040 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11006 23:43:42.431164 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11007 23:43:42.457831 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11008 23:43:42.486437 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11009 23:43:42.504991 <46>[ 14.519451] systemd-journald[312]: Received client request to flush runtime journal.
11010 23:43:42.511679 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11011 23:43:42.544939 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11012 23:43:42.563507 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11013 23:43:42.583389 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11014 23:43:42.603844 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11015 23:43:43.300445 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11016 23:43:43.351302 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11017 23:43:43.936430 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11018 23:43:44.015989 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11019 23:43:44.035265 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11020 23:43:44.054563 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11021 23:43:44.098641 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11022 23:43:44.119758 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11023 23:43:44.407645 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11024 23:43:44.479825 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11025 23:43:44.566400 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11026 23:43:44.830824 <6>[ 16.848991] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11027 23:43:44.840779 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11028 23:43:44.904142 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11029 23:43:44.956566 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11030 23:43:44.982355 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11031 23:43:45.007452 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11032 23:43:45.090896 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11033 23:43:45.118857 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11034 23:43:45.140963 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11035 23:43:45.159924 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11036 23:43:45.191777 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11037 23:43:45.239256 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11038 23:43:45.280656 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11039 23:43:45.306720 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11040 23:43:45.322538 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11041 23:43:45.339362 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11042 23:43:45.358271 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11043 23:43:45.374329 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11044 23:43:45.401037 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11045 23:43:45.422398 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11046 23:43:45.438060 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11047 23:43:45.459458 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11048 23:43:45.485049 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11049 23:43:45.502060 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11050 23:43:45.520600 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11051 23:43:45.538372 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11052 23:43:45.554638 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11053 23:43:45.591831 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11054 23:43:45.628019 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11055 23:43:45.717685 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11056 23:43:45.740126 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11057 23:43:45.793706 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11058 23:43:45.851282 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11059 23:43:45.899168 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11060 23:43:45.918884 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11061 23:43:45.988299 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11062 23:43:46.062867 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11063 23:43:46.092048 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11064 23:43:46.116305 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11065 23:43:46.136438 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11066 23:43:46.196935 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11067 23:43:46.245525 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11068 23:43:46.347300
11069 23:43:46.350388 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11070 23:43:46.350822
11071 23:43:46.353484 debian-bookworm-arm64 login: root (automatic login)
11072 23:43:46.353903
11073 23:43:46.671505 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024 aarch64
11074 23:43:46.672032
11075 23:43:46.677711 The programs included with the Debian GNU/Linux system are free software;
11076 23:43:46.684648 the exact distribution terms for each program are described in the
11077 23:43:46.688209 individual files in /usr/share/doc/*/copyright.
11078 23:43:46.688631
11079 23:43:46.694055 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11080 23:43:46.697704 permitted by applicable law.
11081 23:43:46.809193 Matched prompt #10: / #
11083 23:43:46.810377 Setting prompt string to ['/ #']
11084 23:43:46.810943 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11086 23:43:46.812108 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11087 23:43:46.812613 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
11088 23:43:46.813041 Setting prompt string to ['/ #']
11089 23:43:46.813423 Forcing a shell prompt, looking for ['/ #']
11091 23:43:46.864485 / #
11092 23:43:46.864831 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11093 23:43:46.865081 Waiting using forced prompt support (timeout 00:02:30)
11094 23:43:46.870343
11095 23:43:46.870981 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11096 23:43:46.871312 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
11098 23:43:46.972182 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172911/extract-nfsrootfs-_uzfte3l'
11099 23:43:46.978325 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172911/extract-nfsrootfs-_uzfte3l'
11101 23:43:47.080047 / # export NFS_SERVER_IP='192.168.201.1'
11102 23:43:47.086548 export NFS_SERVER_IP='192.168.201.1'
11103 23:43:47.087372 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11104 23:43:47.087871 end: 2.2 depthcharge-retry (duration 00:01:37) [common]
11105 23:43:47.088351 end: 2 depthcharge-action (duration 00:01:37) [common]
11106 23:43:47.088846 start: 3 lava-test-retry (timeout 00:01:00) [common]
11107 23:43:47.089333 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11108 23:43:47.089758 Using namespace: common
11110 23:43:47.190888 / # #
11111 23:43:47.191456 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11112 23:43:47.197663 #
11113 23:43:47.198373 Using /lava-14172911
11115 23:43:47.299470 / # export SHELL=/bin/sh
11116 23:43:47.305895 export SHELL=/bin/sh
11118 23:43:47.407388 / # . /lava-14172911/environment
11119 23:43:47.413219 . /lava-14172911/environment
11121 23:43:47.520820 / # /lava-14172911/bin/lava-test-runner /lava-14172911/0
11122 23:43:47.521411 Test shell timeout: 10s (minimum of the action and connection timeout)
11123 23:43:47.528011 /lava-14172911/bin/lava-test-runner /lava-14172911/0
11124 23:43:47.811636 + export TESTRUN_ID=0_dmesg
11125 23:43:47.815150 + cd /lava-14172911/0/tests/0_dmesg
11126 23:43:47.818707 + cat uuid
11127 23:43:47.836519 + UUID=14172911_1.<8>[ 19.851189] <LAVA_SIGNAL_STARTRUN 0_dmesg 14172911_1.6.2.3.1>
11128 23:43:47.836954 6.2.3.1
11129 23:43:47.837300 + set +x
11130 23:43:47.837943 Received signal: <STARTRUN> 0_dmesg 14172911_1.6.2.3.1
11131 23:43:47.838356 Starting test lava.0_dmesg (14172911_1.6.2.3.1)
11132 23:43:47.838773 Skipping test definition patterns.
11133 23:43:47.842965 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11134 23:43:47.981978 <8>[ 19.996860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11135 23:43:47.982804 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11137 23:43:48.090122 <8>[ 20.104595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11138 23:43:48.091067 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11140 23:43:48.196164 <8>[ 20.210712] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11141 23:43:48.196929 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11143 23:43:48.198873 + set +x
11144 23:43:48.202506 <8>[ 20.220399] <LAVA_SIGNAL_ENDRUN 0_dmesg 14172911_1.6.2.3.1>
11145 23:43:48.203337 Received signal: <ENDRUN> 0_dmesg 14172911_1.6.2.3.1
11146 23:43:48.203750 Ending use of test pattern.
11147 23:43:48.204146 Ending test lava.0_dmesg (14172911_1.6.2.3.1), duration 0.37
11149 23:43:48.209600 <LAVA_TEST_RUNNER EXIT>
11150 23:43:48.210270 ok: lava_test_shell seems to have completed
11151 23:43:48.210804 alert: pass
crit: pass
emerg: pass
11152 23:43:48.211211 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11153 23:43:48.211620 end: 3 lava-test-retry (duration 00:00:01) [common]
11154 23:43:48.212116 start: 4 finalize (timeout 00:07:52) [common]
11155 23:43:48.212722 start: 4.1 power-off (timeout 00:00:30) [common]
11156 23:43:48.213471 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-9', '--port=1', '--command=off']
11157 23:43:48.471039 >> Command sent successfully.
11158 23:43:48.481408 Returned 0 in 0 seconds
11159 23:43:48.582685 end: 4.1 power-off (duration 00:00:00) [common]
11161 23:43:48.584159 start: 4.2 read-feedback (timeout 00:07:52) [common]
11162 23:43:48.585513 Listened to connection for namespace 'common' for up to 1s
11163 23:43:49.585324 Finalising connection for namespace 'common'
11164 23:43:49.586283 Disconnecting from shell: Finalise
11165 23:43:49.586733 / #
11166 23:43:49.687755 end: 4.2 read-feedback (duration 00:00:01) [common]
11167 23:43:49.688486 end: 4 finalize (duration 00:00:01) [common]
11168 23:43:49.689112 Cleaning after the job
11169 23:43:49.689650 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/ramdisk
11170 23:43:49.699491 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/kernel
11171 23:43:49.731224 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/dtb
11172 23:43:49.731561 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/nfsrootfs
11173 23:43:49.793465 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172911/tftp-deploy-jrgn1tix/modules
11174 23:43:49.799004 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14172911
11175 23:43:50.112924 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14172911
11176 23:43:50.113104 Job finished correctly