Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 28
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 23:40:50.034328 lava-dispatcher, installed at version: 2024.03
2 23:40:50.034538 start: 0 validate
3 23:40:50.034678 Start time: 2024-06-04 23:40:50.034671+00:00 (UTC)
4 23:40:50.034807 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:40:50.034935 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-cros-ec%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:40:50.294026 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:40:50.294208 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:41:17.557085 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:41:17.557307 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:41:17.806092 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:41:17.806248 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:41:20.058968 validate duration: 30.02
14 23:41:20.059258 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:41:20.059368 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:41:20.059464 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:41:20.059594 Not decompressing ramdisk as can be used compressed.
18 23:41:20.059694 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-cros-ec/20240313.0/arm64/rootfs.cpio.gz
19 23:41:20.059760 saving as /var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/ramdisk/rootfs.cpio.gz
20 23:41:20.059823 total size: 39026414 (37 MB)
21 23:41:20.316839 progress 0 % (0 MB)
22 23:41:20.327214 progress 5 % (1 MB)
23 23:41:20.338335 progress 10 % (3 MB)
24 23:41:20.349309 progress 15 % (5 MB)
25 23:41:20.360397 progress 20 % (7 MB)
26 23:41:20.371327 progress 25 % (9 MB)
27 23:41:20.382509 progress 30 % (11 MB)
28 23:41:20.393441 progress 35 % (13 MB)
29 23:41:20.404552 progress 40 % (14 MB)
30 23:41:20.415519 progress 45 % (16 MB)
31 23:41:20.426733 progress 50 % (18 MB)
32 23:41:20.437942 progress 55 % (20 MB)
33 23:41:20.448124 progress 60 % (22 MB)
34 23:41:20.459013 progress 65 % (24 MB)
35 23:41:20.469186 progress 70 % (26 MB)
36 23:41:20.479473 progress 75 % (27 MB)
37 23:41:20.489817 progress 80 % (29 MB)
38 23:41:20.499909 progress 85 % (31 MB)
39 23:41:20.510133 progress 90 % (33 MB)
40 23:41:20.522118 progress 95 % (35 MB)
41 23:41:20.534054 progress 100 % (37 MB)
42 23:41:20.534415 37 MB downloaded in 0.47 s (78.42 MB/s)
43 23:41:20.534666 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:41:20.535092 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:41:20.535211 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:41:20.535344 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:41:20.535536 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:41:20.535645 saving as /var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/kernel/Image
50 23:41:20.535754 total size: 54682112 (52 MB)
51 23:41:20.535865 No compression specified
52 23:41:20.537608 progress 0 % (0 MB)
53 23:41:20.562125 progress 5 % (2 MB)
54 23:41:20.585873 progress 10 % (5 MB)
55 23:41:20.600197 progress 15 % (7 MB)
56 23:41:20.614105 progress 20 % (10 MB)
57 23:41:20.628159 progress 25 % (13 MB)
58 23:41:20.642213 progress 30 % (15 MB)
59 23:41:20.656494 progress 35 % (18 MB)
60 23:41:20.670659 progress 40 % (20 MB)
61 23:41:20.684906 progress 45 % (23 MB)
62 23:41:20.699040 progress 50 % (26 MB)
63 23:41:20.713174 progress 55 % (28 MB)
64 23:41:20.727306 progress 60 % (31 MB)
65 23:41:20.741279 progress 65 % (33 MB)
66 23:41:20.755686 progress 70 % (36 MB)
67 23:41:20.769847 progress 75 % (39 MB)
68 23:41:20.784127 progress 80 % (41 MB)
69 23:41:20.798444 progress 85 % (44 MB)
70 23:41:20.812525 progress 90 % (46 MB)
71 23:41:20.826493 progress 95 % (49 MB)
72 23:41:20.840272 progress 100 % (52 MB)
73 23:41:20.840537 52 MB downloaded in 0.30 s (171.10 MB/s)
74 23:41:20.840705 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:41:20.840948 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:41:20.841037 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:41:20.841122 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:41:20.841261 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:41:20.841332 saving as /var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/dtb/mt8192-asurada-spherion-r0.dtb
81 23:41:20.841394 total size: 47258 (0 MB)
82 23:41:20.841456 No compression specified
83 23:41:20.842552 progress 69 % (0 MB)
84 23:41:20.842837 progress 100 % (0 MB)
85 23:41:20.842996 0 MB downloaded in 0.00 s (28.18 MB/s)
86 23:41:20.843123 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:41:20.843351 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:41:20.843436 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:41:20.843520 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:41:20.843637 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:41:20.843706 saving as /var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/modules/modules.tar
93 23:41:20.843768 total size: 8603924 (8 MB)
94 23:41:20.843832 Using unxz to decompress xz
95 23:41:20.847925 progress 0 % (0 MB)
96 23:41:20.869534 progress 5 % (0 MB)
97 23:41:20.895779 progress 10 % (0 MB)
98 23:41:20.924035 progress 15 % (1 MB)
99 23:41:20.951754 progress 20 % (1 MB)
100 23:41:20.979952 progress 25 % (2 MB)
101 23:41:21.007316 progress 30 % (2 MB)
102 23:41:21.033381 progress 35 % (2 MB)
103 23:41:21.062310 progress 40 % (3 MB)
104 23:41:21.089451 progress 45 % (3 MB)
105 23:41:21.115952 progress 50 % (4 MB)
106 23:41:21.142171 progress 55 % (4 MB)
107 23:41:21.167771 progress 60 % (4 MB)
108 23:41:21.192698 progress 65 % (5 MB)
109 23:41:21.221075 progress 70 % (5 MB)
110 23:41:21.248680 progress 75 % (6 MB)
111 23:41:21.276581 progress 80 % (6 MB)
112 23:41:21.302884 progress 85 % (7 MB)
113 23:41:21.329567 progress 90 % (7 MB)
114 23:41:21.362229 progress 95 % (7 MB)
115 23:41:21.392337 progress 100 % (8 MB)
116 23:41:21.398021 8 MB downloaded in 0.55 s (14.80 MB/s)
117 23:41:21.398343 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:41:21.398763 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:41:21.398890 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:41:21.399029 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:41:21.399151 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:41:21.399273 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:41:21.399566 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u
125 23:41:21.399746 makedir: /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin
126 23:41:21.399861 makedir: /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/tests
127 23:41:21.399970 makedir: /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/results
128 23:41:21.400120 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-add-keys
129 23:41:21.400317 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-add-sources
130 23:41:21.400485 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-background-process-start
131 23:41:21.400662 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-background-process-stop
132 23:41:21.400799 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-common-functions
133 23:41:21.400944 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-echo-ipv4
134 23:41:21.401108 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-install-packages
135 23:41:21.401278 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-installed-packages
136 23:41:21.401444 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-os-build
137 23:41:21.401620 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-probe-channel
138 23:41:21.401758 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-probe-ip
139 23:41:21.401896 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-target-ip
140 23:41:21.402059 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-target-mac
141 23:41:21.402232 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-target-storage
142 23:41:21.402405 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-test-case
143 23:41:21.402572 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-test-event
144 23:41:21.402735 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-test-feedback
145 23:41:21.402899 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-test-raise
146 23:41:21.403072 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-test-reference
147 23:41:21.403235 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-test-runner
148 23:41:21.403402 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-test-set
149 23:41:21.403569 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-test-shell
150 23:41:21.403724 Updating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-install-packages (oe)
151 23:41:21.403886 Updating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/bin/lava-installed-packages (oe)
152 23:41:21.404043 Creating /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/environment
153 23:41:21.404184 LAVA metadata
154 23:41:21.404295 - LAVA_JOB_ID=14172912
155 23:41:21.404392 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:41:21.404553 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:41:21.404640 skipped lava-vland-overlay
158 23:41:21.404728 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:41:21.404817 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:41:21.404925 skipped lava-multinode-overlay
161 23:41:21.405044 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:41:21.405184 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:41:21.405297 Loading test definitions
164 23:41:21.405431 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:41:21.405550 Using /lava-14172912 at stage 0
166 23:41:21.405987 uuid=14172912_1.5.2.3.1 testdef=None
167 23:41:21.406114 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:41:21.406233 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:41:21.407006 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:41:21.407386 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:41:21.408303 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:41:21.408660 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:41:21.409395 runner path: /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/0/tests/0_cros-ec test_uuid 14172912_1.5.2.3.1
176 23:41:21.409601 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:41:21.409963 Creating lava-test-runner.conf files
179 23:41:21.410060 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14172912/lava-overlay-quinc16u/lava-14172912/0 for stage 0
180 23:41:21.410193 - 0_cros-ec
181 23:41:21.410330 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:41:21.410453 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:41:21.419421 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:41:21.419585 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:41:21.419704 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:41:21.419825 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:41:21.419942 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:41:22.706367 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:41:22.706763 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 23:41:22.706881 extracting modules file /var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172912/extract-overlay-ramdisk-ydvxhatb/ramdisk
191 23:41:22.962011 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:41:22.962189 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 23:41:22.962284 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172912/compress-overlay-_8q1t5a6/overlay-1.5.2.4.tar.gz to ramdisk
194 23:41:22.962359 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172912/compress-overlay-_8q1t5a6/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14172912/extract-overlay-ramdisk-ydvxhatb/ramdisk
195 23:41:22.969395 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:41:22.969534 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 23:41:22.969630 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:41:22.969724 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 23:41:22.969811 Building ramdisk /var/lib/lava/dispatcher/tmp/14172912/extract-overlay-ramdisk-ydvxhatb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14172912/extract-overlay-ramdisk-ydvxhatb/ramdisk
200 23:41:23.886327 >> 335873 blocks
201 23:41:29.283108 rename /var/lib/lava/dispatcher/tmp/14172912/extract-overlay-ramdisk-ydvxhatb/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/ramdisk/ramdisk.cpio.gz
202 23:41:29.283663 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 23:41:29.283833 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 23:41:29.283976 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 23:41:29.284154 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/kernel/Image']
206 23:41:44.124340 Returned 0 in 14 seconds
207 23:41:44.224946 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/kernel/image.itb
208 23:41:44.996351 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:41:44.996720 output: Created: Wed Jun 5 00:41:44 2024
210 23:41:44.996796 output: Image 0 (kernel-1)
211 23:41:44.996859 output: Description:
212 23:41:44.996919 output: Created: Wed Jun 5 00:41:44 2024
213 23:41:44.996982 output: Type: Kernel Image
214 23:41:44.997045 output: Compression: lzma compressed
215 23:41:44.997105 output: Data Size: 13061430 Bytes = 12755.30 KiB = 12.46 MiB
216 23:41:44.997169 output: Architecture: AArch64
217 23:41:44.997230 output: OS: Linux
218 23:41:44.997290 output: Load Address: 0x00000000
219 23:41:44.997349 output: Entry Point: 0x00000000
220 23:41:44.997409 output: Hash algo: crc32
221 23:41:44.997472 output: Hash value: ecfb5096
222 23:41:44.997542 output: Image 1 (fdt-1)
223 23:41:44.997603 output: Description: mt8192-asurada-spherion-r0
224 23:41:44.997660 output: Created: Wed Jun 5 00:41:44 2024
225 23:41:44.997716 output: Type: Flat Device Tree
226 23:41:44.997773 output: Compression: uncompressed
227 23:41:44.997827 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 23:41:44.997882 output: Architecture: AArch64
229 23:41:44.997936 output: Hash algo: crc32
230 23:41:44.997989 output: Hash value: 0f8e4d2e
231 23:41:44.998048 output: Image 2 (ramdisk-1)
232 23:41:44.998134 output: Description: unavailable
233 23:41:44.998211 output: Created: Wed Jun 5 00:41:44 2024
234 23:41:44.998295 output: Type: RAMDisk Image
235 23:41:44.998353 output: Compression: Unknown Compression
236 23:41:44.998408 output: Data Size: 52130845 Bytes = 50909.03 KiB = 49.72 MiB
237 23:41:44.998463 output: Architecture: AArch64
238 23:41:44.998518 output: OS: Linux
239 23:41:44.998573 output: Load Address: unavailable
240 23:41:44.998666 output: Entry Point: unavailable
241 23:41:44.998750 output: Hash algo: crc32
242 23:41:44.998834 output: Hash value: 5c2f7902
243 23:41:44.998918 output: Default Configuration: 'conf-1'
244 23:41:44.999003 output: Configuration 0 (conf-1)
245 23:41:44.999093 output: Description: mt8192-asurada-spherion-r0
246 23:41:44.999183 output: Kernel: kernel-1
247 23:41:44.999267 output: Init Ramdisk: ramdisk-1
248 23:41:44.999350 output: FDT: fdt-1
249 23:41:44.999433 output: Loadables: kernel-1
250 23:41:44.999516 output:
251 23:41:44.999761 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 23:41:44.999887 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 23:41:45.000029 end: 1.5 prepare-tftp-overlay (duration 00:00:24) [common]
254 23:41:45.000147 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 23:41:45.000261 No LXC device requested
256 23:41:45.000375 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:41:45.000492 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 23:41:45.000619 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:41:45.000725 Checking files for TFTP limit of 4294967296 bytes.
260 23:41:45.001304 end: 1 tftp-deploy (duration 00:00:25) [common]
261 23:41:45.001413 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:41:45.001513 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:41:45.001644 substitutions:
264 23:41:45.001713 - {DTB}: 14172912/tftp-deploy-1lu6qxlv/dtb/mt8192-asurada-spherion-r0.dtb
265 23:41:45.001777 - {INITRD}: 14172912/tftp-deploy-1lu6qxlv/ramdisk/ramdisk.cpio.gz
266 23:41:45.001837 - {KERNEL}: 14172912/tftp-deploy-1lu6qxlv/kernel/Image
267 23:41:45.001896 - {LAVA_MAC}: None
268 23:41:45.001968 - {PRESEED_CONFIG}: None
269 23:41:45.002029 - {PRESEED_LOCAL}: None
270 23:41:45.002102 - {RAMDISK}: 14172912/tftp-deploy-1lu6qxlv/ramdisk/ramdisk.cpio.gz
271 23:41:45.002169 - {ROOT_PART}: None
272 23:41:45.002236 - {ROOT}: None
273 23:41:45.002334 - {SERVER_IP}: 192.168.201.1
274 23:41:45.002424 - {TEE}: None
275 23:41:45.002511 Parsed boot commands:
276 23:41:45.002597 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:41:45.002826 Parsed boot commands: tftpboot 192.168.201.1 14172912/tftp-deploy-1lu6qxlv/kernel/image.itb 14172912/tftp-deploy-1lu6qxlv/kernel/cmdline
278 23:41:45.002946 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:41:45.003066 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:41:45.003195 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:41:45.003314 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:41:45.003413 Not connected, no need to disconnect.
283 23:41:45.003518 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:41:45.003631 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:41:45.003741 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
286 23:41:45.007553 Setting prompt string to ['lava-test: # ']
287 23:41:45.007961 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:41:45.008098 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:41:45.008237 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:41:45.008386 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:41:45.008774 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=reboot']
292 23:41:50.142149 >> Command sent successfully.
293 23:41:50.144641 Returned 0 in 5 seconds
294 23:41:50.245012 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:41:50.245465 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:41:50.245607 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:41:50.245724 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:41:50.245822 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:41:50.245922 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:41:50.246347 [Enter `^Ec?' for help]
302 23:41:50.417652
303 23:41:50.417828
304 23:41:50.417929 F0: 102B 0000
305 23:41:50.418026
306 23:41:50.418130 F3: 1001 0000 [0200]
307 23:41:50.420925
308 23:41:50.421036 F3: 1001 0000
309 23:41:50.421146
310 23:41:50.421239 F7: 102D 0000
311 23:41:50.421334
312 23:41:50.424108 F1: 0000 0000
313 23:41:50.424217
314 23:41:50.424313 V0: 0000 0000 [0001]
315 23:41:50.424405
316 23:41:50.427737 00: 0007 8000
317 23:41:50.427826
318 23:41:50.427891 01: 0000 0000
319 23:41:50.427953
320 23:41:50.430912 BP: 0C00 0209 [0000]
321 23:41:50.431019
322 23:41:50.431124 G0: 1182 0000
323 23:41:50.431217
324 23:41:50.434482 EC: 0000 0021 [4000]
325 23:41:50.434604
326 23:41:50.434701 S7: 0000 0000 [0000]
327 23:41:50.434796
328 23:41:50.438103 CC: 0000 0000 [0001]
329 23:41:50.438229
330 23:41:50.438328 T0: 0000 0040 [010F]
331 23:41:50.438423
332 23:41:50.438514 Jump to BL
333 23:41:50.441531
334 23:41:50.465222
335 23:41:50.465389
336 23:41:50.472935 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 23:41:50.476718 ARM64: Exception handlers installed.
338 23:41:50.479823 ARM64: Testing exception
339 23:41:50.483193 ARM64: Done test exception
340 23:41:50.489585 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 23:41:50.500004 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 23:41:50.506371 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 23:41:50.516576 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 23:41:50.523241 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 23:41:50.529745 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 23:41:50.541486 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 23:41:50.548496 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 23:41:50.567777 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 23:41:50.570825 WDT: Last reset was cold boot
350 23:41:50.574246 SPI1(PAD0) initialized at 2873684 Hz
351 23:41:50.577560 SPI5(PAD0) initialized at 992727 Hz
352 23:41:50.580878 VBOOT: Loading verstage.
353 23:41:50.587283 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 23:41:50.590764 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 23:41:50.593945 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 23:41:50.597859 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 23:41:50.604714 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 23:41:50.611460 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 23:41:50.622743 read SPI 0x96554 0xa1eb: 4593 us, 9024 KB/s, 72.192 Mbps
360 23:41:50.622912
361 23:41:50.623014
362 23:41:50.632266 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 23:41:50.635640 ARM64: Exception handlers installed.
364 23:41:50.638927 ARM64: Testing exception
365 23:41:50.639102 ARM64: Done test exception
366 23:41:50.646297 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 23:41:50.648912 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 23:41:50.663849 Probing TPM: . done!
369 23:41:50.664052 TPM ready after 0 ms
370 23:41:50.670338 Connected to device vid:did:rid of 1ae0:0028:00
371 23:41:50.676912 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 23:41:50.719160 Initialized TPM device CR50 revision 0
373 23:41:50.731421 tlcl_send_startup: Startup return code is 0
374 23:41:50.731629 TPM: setup succeeded
375 23:41:50.742396 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 23:41:50.751631 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 23:41:50.762580 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 23:41:50.772383 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 23:41:50.776172 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 23:41:50.779561 in-header: 03 07 00 00 08 00 00 00
381 23:41:50.783329 in-data: aa e4 47 04 13 02 00 00
382 23:41:50.787145 Chrome EC: UHEPI supported
383 23:41:50.790726 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 23:41:50.794753 in-header: 03 9d 00 00 08 00 00 00
385 23:41:50.798943 in-data: 10 20 20 08 00 00 00 00
386 23:41:50.799058 Phase 1
387 23:41:50.805755 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 23:41:50.809228 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 23:41:50.816727 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 23:41:50.820506 Recovery requested (1009000e)
391 23:41:50.825863 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 23:41:50.831110 tlcl_extend: response is 0
393 23:41:50.841600 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 23:41:50.845094 tlcl_extend: response is 0
395 23:41:50.852014 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 23:41:50.872752 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
397 23:41:50.879980 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 23:41:50.880119
399 23:41:50.880226
400 23:41:50.887463 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 23:41:50.891112 ARM64: Exception handlers installed.
402 23:41:50.894941 ARM64: Testing exception
403 23:41:50.895074 ARM64: Done test exception
404 23:41:50.914883 pmic_efuse_setting: Set efuses in 11 msecs
405 23:41:50.923398 pmwrap_interface_init: Select PMIF_VLD_RDY
406 23:41:50.927668 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 23:41:50.930728 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 23:41:50.937902 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 23:41:50.941657 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 23:41:50.945556 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 23:41:50.952368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 23:41:50.956184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 23:41:50.959777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 23:41:50.966906 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 23:41:50.969936 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 23:41:50.973045 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 23:41:50.979796 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 23:41:50.983277 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 23:41:50.989976 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 23:41:50.996567 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 23:41:50.999931 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 23:41:51.006728 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 23:41:51.013164 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 23:41:51.016514 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 23:41:51.023964 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 23:41:51.027851 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 23:41:51.034926 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 23:41:51.041586 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 23:41:51.045476 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 23:41:51.052545 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 23:41:51.055889 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 23:41:51.063400 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 23:41:51.066293 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 23:41:51.073251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 23:41:51.076892 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 23:41:51.080000 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 23:41:51.087914 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 23:41:51.091376 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 23:41:51.094978 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 23:41:51.102497 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 23:41:51.106368 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 23:41:51.112864 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 23:41:51.116075 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 23:41:51.119539 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 23:41:51.126067 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 23:41:51.129650 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 23:41:51.132775 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 23:41:51.139893 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 23:41:51.142741 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 23:41:51.146179 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 23:41:51.153052 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 23:41:51.156353 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 23:41:51.159771 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 23:41:51.162740 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 23:41:51.169537 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 23:41:51.173076 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 23:41:51.179905 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 23:41:51.189686 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 23:41:51.192945 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 23:41:51.202660 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 23:41:51.209336 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 23:41:51.216008 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 23:41:51.219306 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 23:41:51.222613 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:41:51.230123 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x7
466 23:41:51.236982 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 23:41:51.240552 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 23:41:51.243712 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 23:41:51.254530 [RTC]rtc_get_frequency_meter,154: input=15, output=794
470 23:41:51.257983 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
471 23:41:51.264672 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
472 23:41:51.268195 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
473 23:41:51.271693 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
474 23:41:51.274467 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
475 23:41:51.278358 ADC[4]: Raw value=898150 ID=7
476 23:41:51.281172 ADC[3]: Raw value=212700 ID=1
477 23:41:51.284656 RAM Code: 0x71
478 23:41:51.287997 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
479 23:41:51.291285 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
480 23:41:51.301215 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
481 23:41:51.308237 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
482 23:41:51.311531 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
483 23:41:51.315428 in-header: 03 07 00 00 08 00 00 00
484 23:41:51.318067 in-data: aa e4 47 04 13 02 00 00
485 23:41:51.321419 Chrome EC: UHEPI supported
486 23:41:51.325220 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
487 23:41:51.329476 in-header: 03 d5 00 00 08 00 00 00
488 23:41:51.333290 in-data: 98 20 60 08 00 00 00 00
489 23:41:51.336446 MRC: failed to locate region type 0.
490 23:41:51.344011 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
491 23:41:51.347897 DRAM-K: Running full calibration
492 23:41:51.354692 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
493 23:41:51.354827 header.status = 0x0
494 23:41:51.358332 header.version = 0x6 (expected: 0x6)
495 23:41:51.361444 header.size = 0xd00 (expected: 0xd00)
496 23:41:51.364764 header.flags = 0x0
497 23:41:51.368693 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
498 23:41:51.387015 read SPI 0x72590 0x1c583: 12501 us, 9287 KB/s, 74.296 Mbps
499 23:41:51.394505 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
500 23:41:51.398243 dram_init: ddr_geometry: 2
501 23:41:51.398406 [EMI] MDL number = 2
502 23:41:51.402091 [EMI] Get MDL freq = 0
503 23:41:51.402248 dram_init: ddr_type: 0
504 23:41:51.405418 is_discrete_lpddr4: 1
505 23:41:51.408970 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
506 23:41:51.409111
507 23:41:51.409230
508 23:41:51.412523 [Bian_co] ETT version 0.0.0.1
509 23:41:51.416037 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
510 23:41:51.416136
511 23:41:51.419498 dramc_set_vcore_voltage set vcore to 650000
512 23:41:51.423402 Read voltage for 800, 4
513 23:41:51.423512 Vio18 = 0
514 23:41:51.423584 Vcore = 650000
515 23:41:51.427203 Vdram = 0
516 23:41:51.427328 Vddq = 0
517 23:41:51.427427 Vmddr = 0
518 23:41:51.431109 dram_init: config_dvfs: 1
519 23:41:51.435089 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
520 23:41:51.438304 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
521 23:41:51.441948 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
522 23:41:51.445664 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
523 23:41:51.449721 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
524 23:41:51.453251 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
525 23:41:51.457248 MEM_TYPE=3, freq_sel=18
526 23:41:51.461101 sv_algorithm_assistance_LP4_1600
527 23:41:51.464201 ============ PULL DRAM RESETB DOWN ============
528 23:41:51.467836 ========== PULL DRAM RESETB DOWN end =========
529 23:41:51.474339 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
530 23:41:51.477738 ===================================
531 23:41:51.477884 LPDDR4 DRAM CONFIGURATION
532 23:41:51.481075 ===================================
533 23:41:51.484463 EX_ROW_EN[0] = 0x0
534 23:41:51.484584 EX_ROW_EN[1] = 0x0
535 23:41:51.487568 LP4Y_EN = 0x0
536 23:41:51.487666 WORK_FSP = 0x0
537 23:41:51.491317 WL = 0x2
538 23:41:51.491411 RL = 0x2
539 23:41:51.494851 BL = 0x2
540 23:41:51.497989 RPST = 0x0
541 23:41:51.498121 RD_PRE = 0x0
542 23:41:51.501070 WR_PRE = 0x1
543 23:41:51.501188 WR_PST = 0x0
544 23:41:51.504676 DBI_WR = 0x0
545 23:41:51.504775 DBI_RD = 0x0
546 23:41:51.507897 OTF = 0x1
547 23:41:51.511213 ===================================
548 23:41:51.514231 ===================================
549 23:41:51.514367 ANA top config
550 23:41:51.517569 ===================================
551 23:41:51.521070 DLL_ASYNC_EN = 0
552 23:41:51.524239 ALL_SLAVE_EN = 1
553 23:41:51.524379 NEW_RANK_MODE = 1
554 23:41:51.527454 DLL_IDLE_MODE = 1
555 23:41:51.530775 LP45_APHY_COMB_EN = 1
556 23:41:51.534480 TX_ODT_DIS = 1
557 23:41:51.534627 NEW_8X_MODE = 1
558 23:41:51.537743 ===================================
559 23:41:51.541027 ===================================
560 23:41:51.544330 data_rate = 1600
561 23:41:51.547666 CKR = 1
562 23:41:51.550943 DQ_P2S_RATIO = 8
563 23:41:51.554612 ===================================
564 23:41:51.558005 CA_P2S_RATIO = 8
565 23:41:51.560791 DQ_CA_OPEN = 0
566 23:41:51.560912 DQ_SEMI_OPEN = 0
567 23:41:51.564686 CA_SEMI_OPEN = 0
568 23:41:51.567670 CA_FULL_RATE = 0
569 23:41:51.571013 DQ_CKDIV4_EN = 1
570 23:41:51.574254 CA_CKDIV4_EN = 1
571 23:41:51.577974 CA_PREDIV_EN = 0
572 23:41:51.578120 PH8_DLY = 0
573 23:41:51.581330 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
574 23:41:51.584467 DQ_AAMCK_DIV = 4
575 23:41:51.587599 CA_AAMCK_DIV = 4
576 23:41:51.591309 CA_ADMCK_DIV = 4
577 23:41:51.591458 DQ_TRACK_CA_EN = 0
578 23:41:51.594648 CA_PICK = 800
579 23:41:51.597973 CA_MCKIO = 800
580 23:41:51.601454 MCKIO_SEMI = 0
581 23:41:51.604438 PLL_FREQ = 3068
582 23:41:51.607565 DQ_UI_PI_RATIO = 32
583 23:41:51.611338 CA_UI_PI_RATIO = 0
584 23:41:51.614299 ===================================
585 23:41:51.617730 ===================================
586 23:41:51.617834 memory_type:LPDDR4
587 23:41:51.620934 GP_NUM : 10
588 23:41:51.624615 SRAM_EN : 1
589 23:41:51.624741 MD32_EN : 0
590 23:41:51.627891 ===================================
591 23:41:51.631121 [ANA_INIT] >>>>>>>>>>>>>>
592 23:41:51.634315 <<<<<< [CONFIGURE PHASE]: ANA_TX
593 23:41:51.637631 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
594 23:41:51.640882 ===================================
595 23:41:51.644247 data_rate = 1600,PCW = 0X7600
596 23:41:51.647520 ===================================
597 23:41:51.651446 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
598 23:41:51.654132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
599 23:41:51.661007 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 23:41:51.664722 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
601 23:41:51.667864 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
602 23:41:51.671257 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
603 23:41:51.674776 [ANA_INIT] flow start
604 23:41:51.678594 [ANA_INIT] PLL >>>>>>>>
605 23:41:51.678733 [ANA_INIT] PLL <<<<<<<<
606 23:41:51.682288 [ANA_INIT] MIDPI >>>>>>>>
607 23:41:51.682388 [ANA_INIT] MIDPI <<<<<<<<
608 23:41:51.685791 [ANA_INIT] DLL >>>>>>>>
609 23:41:51.689787 [ANA_INIT] flow end
610 23:41:51.693088 ============ LP4 DIFF to SE enter ============
611 23:41:51.696906 ============ LP4 DIFF to SE exit ============
612 23:41:51.697019 [ANA_INIT] <<<<<<<<<<<<<
613 23:41:51.700369 [Flow] Enable top DCM control >>>>>
614 23:41:51.704290 [Flow] Enable top DCM control <<<<<
615 23:41:51.707606 Enable DLL master slave shuffle
616 23:41:51.715119 ==============================================================
617 23:41:51.715277 Gating Mode config
618 23:41:51.721932 ==============================================================
619 23:41:51.722085 Config description:
620 23:41:51.731790 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
621 23:41:51.738765 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
622 23:41:51.742001 SELPH_MODE 0: By rank 1: By Phase
623 23:41:51.748732 ==============================================================
624 23:41:51.751753 GAT_TRACK_EN = 1
625 23:41:51.755064 RX_GATING_MODE = 2
626 23:41:51.758341 RX_GATING_TRACK_MODE = 2
627 23:41:51.761962 SELPH_MODE = 1
628 23:41:51.765628 PICG_EARLY_EN = 1
629 23:41:51.768670 VALID_LAT_VALUE = 1
630 23:41:51.772006 ==============================================================
631 23:41:51.775415 Enter into Gating configuration >>>>
632 23:41:51.778440 Exit from Gating configuration <<<<
633 23:41:51.782151 Enter into DVFS_PRE_config >>>>>
634 23:41:51.792017 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
635 23:41:51.795395 Exit from DVFS_PRE_config <<<<<
636 23:41:51.798797 Enter into PICG configuration >>>>
637 23:41:51.802324 Exit from PICG configuration <<<<
638 23:41:51.805358 [RX_INPUT] configuration >>>>>
639 23:41:51.808555 [RX_INPUT] configuration <<<<<
640 23:41:51.815447 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
641 23:41:51.818791 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
642 23:41:51.825248 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
643 23:41:51.832254 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
644 23:41:51.838614 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
645 23:41:51.845314 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
646 23:41:51.848567 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
647 23:41:51.851899 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
648 23:41:51.855136 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
649 23:41:51.862039 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
650 23:41:51.865352 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
651 23:41:51.868734 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
652 23:41:51.871779 ===================================
653 23:41:51.875529 LPDDR4 DRAM CONFIGURATION
654 23:41:51.878799 ===================================
655 23:41:51.878893 EX_ROW_EN[0] = 0x0
656 23:41:51.882021 EX_ROW_EN[1] = 0x0
657 23:41:51.882131 LP4Y_EN = 0x0
658 23:41:51.885188 WORK_FSP = 0x0
659 23:41:51.885273 WL = 0x2
660 23:41:51.888676 RL = 0x2
661 23:41:51.891625 BL = 0x2
662 23:41:51.891730 RPST = 0x0
663 23:41:51.895405 RD_PRE = 0x0
664 23:41:51.895526 WR_PRE = 0x1
665 23:41:51.898545 WR_PST = 0x0
666 23:41:51.898661 DBI_WR = 0x0
667 23:41:51.901722 DBI_RD = 0x0
668 23:41:51.901840 OTF = 0x1
669 23:41:51.904855 ===================================
670 23:41:51.908789 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
671 23:41:51.912006 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
672 23:41:51.919069 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
673 23:41:51.922644 ===================================
674 23:41:51.922773 LPDDR4 DRAM CONFIGURATION
675 23:41:51.926215 ===================================
676 23:41:51.930132 EX_ROW_EN[0] = 0x10
677 23:41:51.930278 EX_ROW_EN[1] = 0x0
678 23:41:51.933559 LP4Y_EN = 0x0
679 23:41:51.933681 WORK_FSP = 0x0
680 23:41:51.937677 WL = 0x2
681 23:41:51.937823 RL = 0x2
682 23:41:51.941361 BL = 0x2
683 23:41:51.941485 RPST = 0x0
684 23:41:51.945567 RD_PRE = 0x0
685 23:41:51.945694 WR_PRE = 0x1
686 23:41:51.945796 WR_PST = 0x0
687 23:41:51.949155 DBI_WR = 0x0
688 23:41:51.949247 DBI_RD = 0x0
689 23:41:51.952681 OTF = 0x1
690 23:41:51.956000 ===================================
691 23:41:51.959892 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
692 23:41:51.965830 nWR fixed to 40
693 23:41:51.969043 [ModeRegInit_LP4] CH0 RK0
694 23:41:51.969159 [ModeRegInit_LP4] CH0 RK1
695 23:41:51.972865 [ModeRegInit_LP4] CH1 RK0
696 23:41:51.972971 [ModeRegInit_LP4] CH1 RK1
697 23:41:51.976872 match AC timing 13
698 23:41:51.980406 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
699 23:41:51.984191 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
700 23:41:51.987803 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
701 23:41:51.995330 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
702 23:41:51.999141 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
703 23:41:51.999266 [EMI DOE] emi_dcm 0
704 23:41:52.002859 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
705 23:41:52.006806 ==
706 23:41:52.006924 Dram Type= 6, Freq= 0, CH_0, rank 0
707 23:41:52.010603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
708 23:41:52.014481 ==
709 23:41:52.018225 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
710 23:41:52.024758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
711 23:41:52.033528 [CA 0] Center 38 (7~69) winsize 63
712 23:41:52.037229 [CA 1] Center 37 (7~68) winsize 62
713 23:41:52.040444 [CA 2] Center 35 (5~66) winsize 62
714 23:41:52.044678 [CA 3] Center 35 (5~65) winsize 61
715 23:41:52.048725 [CA 4] Center 34 (4~65) winsize 62
716 23:41:52.048894 [CA 5] Center 34 (4~65) winsize 62
717 23:41:52.049019
718 23:41:52.052471 [CmdBusTrainingLP45] Vref(ca) range 1: 34
719 23:41:52.052616
720 23:41:52.056076 [CATrainingPosCal] consider 1 rank data
721 23:41:52.060084 u2DelayCellTimex100 = 270/100 ps
722 23:41:52.063701 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
723 23:41:52.067485 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
724 23:41:52.071106 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
725 23:41:52.074821 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
726 23:41:52.078753 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
727 23:41:52.082161 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
728 23:41:52.082326
729 23:41:52.086304 CA PerBit enable=1, Macro0, CA PI delay=34
730 23:41:52.086451
731 23:41:52.089616 [CBTSetCACLKResult] CA Dly = 34
732 23:41:52.089759 CS Dly: 5 (0~36)
733 23:41:52.089883 ==
734 23:41:52.093376 Dram Type= 6, Freq= 0, CH_0, rank 1
735 23:41:52.097029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
736 23:41:52.097184 ==
737 23:41:52.104493 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
738 23:41:52.111481 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
739 23:41:52.118959 [CA 0] Center 38 (7~69) winsize 63
740 23:41:52.122238 [CA 1] Center 37 (7~68) winsize 62
741 23:41:52.126127 [CA 2] Center 35 (5~66) winsize 62
742 23:41:52.130043 [CA 3] Center 35 (5~66) winsize 62
743 23:41:52.133834 [CA 4] Center 34 (4~65) winsize 62
744 23:41:52.137088 [CA 5] Center 34 (4~65) winsize 62
745 23:41:52.137200
746 23:41:52.141295 [CmdBusTrainingLP45] Vref(ca) range 1: 32
747 23:41:52.141433
748 23:41:52.145006 [CATrainingPosCal] consider 2 rank data
749 23:41:52.145105 u2DelayCellTimex100 = 270/100 ps
750 23:41:52.148729 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
751 23:41:52.152514 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
752 23:41:52.156278 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
753 23:41:52.159611 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
754 23:41:52.163465 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
755 23:41:52.167369 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
756 23:41:52.167530
757 23:41:52.171091 CA PerBit enable=1, Macro0, CA PI delay=34
758 23:41:52.171237
759 23:41:52.174631 [CBTSetCACLKResult] CA Dly = 34
760 23:41:52.179061 CS Dly: 5 (0~37)
761 23:41:52.179200
762 23:41:52.183615 ----->DramcWriteLeveling(PI) begin...
763 23:41:52.183766 ==
764 23:41:52.183863 Dram Type= 6, Freq= 0, CH_0, rank 0
765 23:41:52.189961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
766 23:41:52.190107 ==
767 23:41:52.192883 Write leveling (Byte 0): 34 => 34
768 23:41:52.192992 Write leveling (Byte 1): 30 => 30
769 23:41:52.196218 DramcWriteLeveling(PI) end<-----
770 23:41:52.196366
771 23:41:52.196468 ==
772 23:41:52.199998 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:41:52.206183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 23:41:52.206302 ==
775 23:41:52.209760 [Gating] SW mode calibration
776 23:41:52.216848 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
777 23:41:52.219709 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
778 23:41:52.223280 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
779 23:41:52.229828 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 23:41:52.233155 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 23:41:52.236352 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
782 23:41:52.243277 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 23:41:52.246576 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 23:41:52.249882 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 23:41:52.256727 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 23:41:52.260487 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 23:41:52.264215 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 23:41:52.268099 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 23:41:52.271431 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:41:52.278195 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:41:52.281416 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:41:52.285065 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:41:52.291947 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:41:52.295423 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:41:52.298805 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
796 23:41:52.305226 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
797 23:41:52.309167 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
798 23:41:52.312334 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:41:52.315230 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:41:52.322226 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:41:52.325224 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:41:52.328958 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:41:52.335475 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 23:41:52.338949 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 23:41:52.341960 0 9 12 | B1->B0 | 2828 3131 | 0 1 | (0 0) (1 1)
806 23:41:52.348907 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
807 23:41:52.352329 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 23:41:52.355160 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 23:41:52.361908 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 23:41:52.365222 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 23:41:52.368942 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 23:41:52.375376 0 10 8 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
813 23:41:52.378692 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
814 23:41:52.382070 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 23:41:52.388971 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 23:41:52.392480 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 23:41:52.395671 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 23:41:52.398748 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 23:41:52.405685 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 23:41:52.408639 0 11 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
821 23:41:52.412331 0 11 12 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
822 23:41:52.418969 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
823 23:41:52.422243 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 23:41:52.425593 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 23:41:52.432017 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 23:41:52.435506 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 23:41:52.438716 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 23:41:52.445708 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
829 23:41:52.448956 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
830 23:41:52.452087 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
831 23:41:52.459152 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 23:41:52.462211 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 23:41:52.465295 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 23:41:52.471874 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 23:41:52.475661 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 23:41:52.478750 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 23:41:52.485291 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:41:52.488640 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:41:52.491873 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:41:52.498715 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:41:52.501993 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:41:52.505333 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:41:52.508940 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:41:52.515847 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
845 23:41:52.518653 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
846 23:41:52.522075 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 23:41:52.525255 Total UI for P1: 0, mck2ui 16
848 23:41:52.528810 best dqsien dly found for B0: ( 0, 14, 10)
849 23:41:52.532244 Total UI for P1: 0, mck2ui 16
850 23:41:52.535797 best dqsien dly found for B1: ( 0, 14, 10)
851 23:41:52.539262 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
852 23:41:52.542152 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
853 23:41:52.542263
854 23:41:52.548798 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
855 23:41:52.552086 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 23:41:52.555791 [Gating] SW calibration Done
857 23:41:52.555951 ==
858 23:41:52.558884 Dram Type= 6, Freq= 0, CH_0, rank 0
859 23:41:52.562161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 23:41:52.562313 ==
861 23:41:52.562444 RX Vref Scan: 0
862 23:41:52.562558
863 23:41:52.565378 RX Vref 0 -> 0, step: 1
864 23:41:52.565515
865 23:41:52.568546 RX Delay -130 -> 252, step: 16
866 23:41:52.572311 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
867 23:41:52.575631 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 23:41:52.582203 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
869 23:41:52.585363 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
870 23:41:52.588691 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
871 23:41:52.591842 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
872 23:41:52.595637 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 23:41:52.602028 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 23:41:52.605291 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 23:41:52.608931 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
876 23:41:52.612041 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 23:41:52.615582 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 23:41:52.622351 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 23:41:52.625432 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 23:41:52.628672 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 23:41:52.631892 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 23:41:52.632019 ==
883 23:41:52.635598 Dram Type= 6, Freq= 0, CH_0, rank 0
884 23:41:52.638895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 23:41:52.642245 ==
886 23:41:52.642395 DQS Delay:
887 23:41:52.642517 DQS0 = 0, DQS1 = 0
888 23:41:52.645557 DQM Delay:
889 23:41:52.645691 DQM0 = 82, DQM1 = 69
890 23:41:52.648744 DQ Delay:
891 23:41:52.652216 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
892 23:41:52.652367 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
893 23:41:52.655338 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
894 23:41:52.659234 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 23:41:52.662363
896 23:41:52.662510
897 23:41:52.662631 ==
898 23:41:52.665719 Dram Type= 6, Freq= 0, CH_0, rank 0
899 23:41:52.669414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 23:41:52.669515 ==
901 23:41:52.669588
902 23:41:52.669653
903 23:41:52.672497 TX Vref Scan disable
904 23:41:52.672615 == TX Byte 0 ==
905 23:41:52.676267 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
906 23:41:52.682779 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
907 23:41:52.682902 == TX Byte 1 ==
908 23:41:52.686032 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
909 23:41:52.692683 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
910 23:41:52.692805 ==
911 23:41:52.695858 Dram Type= 6, Freq= 0, CH_0, rank 0
912 23:41:52.699144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 23:41:52.699247 ==
914 23:41:52.712719 TX Vref=22, minBit 11, minWin=26, winSum=430
915 23:41:52.716079 TX Vref=24, minBit 1, minWin=27, winSum=437
916 23:41:52.719635 TX Vref=26, minBit 4, minWin=27, winSum=439
917 23:41:52.722466 TX Vref=28, minBit 8, minWin=27, winSum=444
918 23:41:52.725935 TX Vref=30, minBit 9, minWin=27, winSum=441
919 23:41:52.732513 TX Vref=32, minBit 9, minWin=26, winSum=438
920 23:41:52.736108 [TxChooseVref] Worse bit 8, Min win 27, Win sum 444, Final Vref 28
921 23:41:52.736275
922 23:41:52.739425 Final TX Range 1 Vref 28
923 23:41:52.739567
924 23:41:52.739691 ==
925 23:41:52.742719 Dram Type= 6, Freq= 0, CH_0, rank 0
926 23:41:52.746195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 23:41:52.746284 ==
928 23:41:52.746362
929 23:41:52.749290
930 23:41:52.749373 TX Vref Scan disable
931 23:41:52.753008 == TX Byte 0 ==
932 23:41:52.756082 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
933 23:41:52.759302 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
934 23:41:52.762664 == TX Byte 1 ==
935 23:41:52.766348 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
936 23:41:52.769321 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
937 23:41:52.772775
938 23:41:52.772897 [DATLAT]
939 23:41:52.772971 Freq=800, CH0 RK0
940 23:41:52.773038
941 23:41:52.776795 DATLAT Default: 0xa
942 23:41:52.776888 0, 0xFFFF, sum = 0
943 23:41:52.779584 1, 0xFFFF, sum = 0
944 23:41:52.779670 2, 0xFFFF, sum = 0
945 23:41:52.782632 3, 0xFFFF, sum = 0
946 23:41:52.782744 4, 0xFFFF, sum = 0
947 23:41:52.786163 5, 0xFFFF, sum = 0
948 23:41:52.786258 6, 0xFFFF, sum = 0
949 23:41:52.789566 7, 0xFFFF, sum = 0
950 23:41:52.789651 8, 0xFFFF, sum = 0
951 23:41:52.793260 9, 0x0, sum = 1
952 23:41:52.793380 10, 0x0, sum = 2
953 23:41:52.796462 11, 0x0, sum = 3
954 23:41:52.796548 12, 0x0, sum = 4
955 23:41:52.799739 best_step = 10
956 23:41:52.799846
957 23:41:52.799948 ==
958 23:41:52.802967 Dram Type= 6, Freq= 0, CH_0, rank 0
959 23:41:52.806158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 23:41:52.806257 ==
961 23:41:52.809353 RX Vref Scan: 1
962 23:41:52.809440
963 23:41:52.809516 Set Vref Range= 32 -> 127
964 23:41:52.809579
965 23:41:52.812752 RX Vref 32 -> 127, step: 1
966 23:41:52.812865
967 23:41:52.816724 RX Delay -111 -> 252, step: 8
968 23:41:52.816823
969 23:41:52.819891 Set Vref, RX VrefLevel [Byte0]: 32
970 23:41:52.822957 [Byte1]: 32
971 23:41:52.823054
972 23:41:52.826432 Set Vref, RX VrefLevel [Byte0]: 33
973 23:41:52.829594 [Byte1]: 33
974 23:41:52.833507
975 23:41:52.833610 Set Vref, RX VrefLevel [Byte0]: 34
976 23:41:52.836402 [Byte1]: 34
977 23:41:52.841161
978 23:41:52.841272 Set Vref, RX VrefLevel [Byte0]: 35
979 23:41:52.844240 [Byte1]: 35
980 23:41:52.848471
981 23:41:52.848608 Set Vref, RX VrefLevel [Byte0]: 36
982 23:41:52.851814 [Byte1]: 36
983 23:41:52.856100
984 23:41:52.856234 Set Vref, RX VrefLevel [Byte0]: 37
985 23:41:52.859473 [Byte1]: 37
986 23:41:52.864038
987 23:41:52.864176 Set Vref, RX VrefLevel [Byte0]: 38
988 23:41:52.867327 [Byte1]: 38
989 23:41:52.871605
990 23:41:52.871734 Set Vref, RX VrefLevel [Byte0]: 39
991 23:41:52.874800 [Byte1]: 39
992 23:41:52.879180
993 23:41:52.879315 Set Vref, RX VrefLevel [Byte0]: 40
994 23:41:52.882460 [Byte1]: 40
995 23:41:52.886643
996 23:41:52.886749 Set Vref, RX VrefLevel [Byte0]: 41
997 23:41:52.890179 [Byte1]: 41
998 23:41:52.894251
999 23:41:52.894350 Set Vref, RX VrefLevel [Byte0]: 42
1000 23:41:52.897579 [Byte1]: 42
1001 23:41:52.901874
1002 23:41:52.901991 Set Vref, RX VrefLevel [Byte0]: 43
1003 23:41:52.905228 [Byte1]: 43
1004 23:41:52.909635
1005 23:41:52.909744 Set Vref, RX VrefLevel [Byte0]: 44
1006 23:41:52.912998 [Byte1]: 44
1007 23:41:52.917312
1008 23:41:52.917415 Set Vref, RX VrefLevel [Byte0]: 45
1009 23:41:52.920606 [Byte1]: 45
1010 23:41:52.925263
1011 23:41:52.925389 Set Vref, RX VrefLevel [Byte0]: 46
1012 23:41:52.928817 [Byte1]: 46
1013 23:41:52.932654
1014 23:41:52.932762 Set Vref, RX VrefLevel [Byte0]: 47
1015 23:41:52.935853 [Byte1]: 47
1016 23:41:52.940657
1017 23:41:52.940812 Set Vref, RX VrefLevel [Byte0]: 48
1018 23:41:52.943698 [Byte1]: 48
1019 23:41:52.948473
1020 23:41:52.948612 Set Vref, RX VrefLevel [Byte0]: 49
1021 23:41:52.951607 [Byte1]: 49
1022 23:41:52.955568
1023 23:41:52.955711 Set Vref, RX VrefLevel [Byte0]: 50
1024 23:41:52.958754 [Byte1]: 50
1025 23:41:52.963127
1026 23:41:52.963259 Set Vref, RX VrefLevel [Byte0]: 51
1027 23:41:52.966245 [Byte1]: 51
1028 23:41:52.970618
1029 23:41:52.970741 Set Vref, RX VrefLevel [Byte0]: 52
1030 23:41:52.974512 [Byte1]: 52
1031 23:41:52.978686
1032 23:41:52.978805 Set Vref, RX VrefLevel [Byte0]: 53
1033 23:41:52.982063 [Byte1]: 53
1034 23:41:52.986097
1035 23:41:52.986214 Set Vref, RX VrefLevel [Byte0]: 54
1036 23:41:52.989196 [Byte1]: 54
1037 23:41:52.993876
1038 23:41:52.994000 Set Vref, RX VrefLevel [Byte0]: 55
1039 23:41:52.996739 [Byte1]: 55
1040 23:41:53.001189
1041 23:41:53.001321 Set Vref, RX VrefLevel [Byte0]: 56
1042 23:41:53.004648 [Byte1]: 56
1043 23:41:53.009135
1044 23:41:53.009263 Set Vref, RX VrefLevel [Byte0]: 57
1045 23:41:53.012236 [Byte1]: 57
1046 23:41:53.016807
1047 23:41:53.016908 Set Vref, RX VrefLevel [Byte0]: 58
1048 23:41:53.020021 [Byte1]: 58
1049 23:41:53.024424
1050 23:41:53.024529 Set Vref, RX VrefLevel [Byte0]: 59
1051 23:41:53.027511 [Byte1]: 59
1052 23:41:53.031968
1053 23:41:53.032074 Set Vref, RX VrefLevel [Byte0]: 60
1054 23:41:53.035264 [Byte1]: 60
1055 23:41:53.039765
1056 23:41:53.039894 Set Vref, RX VrefLevel [Byte0]: 61
1057 23:41:53.042870 [Byte1]: 61
1058 23:41:53.047066
1059 23:41:53.047167 Set Vref, RX VrefLevel [Byte0]: 62
1060 23:41:53.050485 [Byte1]: 62
1061 23:41:53.054985
1062 23:41:53.055084 Set Vref, RX VrefLevel [Byte0]: 63
1063 23:41:53.058266 [Byte1]: 63
1064 23:41:53.062916
1065 23:41:53.063026 Set Vref, RX VrefLevel [Byte0]: 64
1066 23:41:53.065815 [Byte1]: 64
1067 23:41:53.070136
1068 23:41:53.070291 Set Vref, RX VrefLevel [Byte0]: 65
1069 23:41:53.073349 [Byte1]: 65
1070 23:41:53.077830
1071 23:41:53.077970 Set Vref, RX VrefLevel [Byte0]: 66
1072 23:41:53.081099 [Byte1]: 66
1073 23:41:53.085540
1074 23:41:53.085684 Set Vref, RX VrefLevel [Byte0]: 67
1075 23:41:53.088813 [Byte1]: 67
1076 23:41:53.093205
1077 23:41:53.093347 Set Vref, RX VrefLevel [Byte0]: 68
1078 23:41:53.096489 [Byte1]: 68
1079 23:41:53.100664
1080 23:41:53.100784 Set Vref, RX VrefLevel [Byte0]: 69
1081 23:41:53.103865 [Byte1]: 69
1082 23:41:53.108316
1083 23:41:53.108446 Set Vref, RX VrefLevel [Byte0]: 70
1084 23:41:53.111476 [Byte1]: 70
1085 23:41:53.115891
1086 23:41:53.115986 Set Vref, RX VrefLevel [Byte0]: 71
1087 23:41:53.119194 [Byte1]: 71
1088 23:41:53.123706
1089 23:41:53.123837 Set Vref, RX VrefLevel [Byte0]: 72
1090 23:41:53.127115 [Byte1]: 72
1091 23:41:53.131355
1092 23:41:53.131455 Set Vref, RX VrefLevel [Byte0]: 73
1093 23:41:53.134795 [Byte1]: 73
1094 23:41:53.138952
1095 23:41:53.139054 Set Vref, RX VrefLevel [Byte0]: 74
1096 23:41:53.142239 [Byte1]: 74
1097 23:41:53.146473
1098 23:41:53.146568 Set Vref, RX VrefLevel [Byte0]: 75
1099 23:41:53.150214 [Byte1]: 75
1100 23:41:53.154571
1101 23:41:53.154668 Set Vref, RX VrefLevel [Byte0]: 76
1102 23:41:53.157754 [Byte1]: 76
1103 23:41:53.161660
1104 23:41:53.161790 Set Vref, RX VrefLevel [Byte0]: 77
1105 23:41:53.165327 [Byte1]: 77
1106 23:41:53.169330
1107 23:41:53.169424 Set Vref, RX VrefLevel [Byte0]: 78
1108 23:41:53.172918 [Byte1]: 78
1109 23:41:53.177159
1110 23:41:53.177299 Final RX Vref Byte 0 = 59 to rank0
1111 23:41:53.180366 Final RX Vref Byte 1 = 54 to rank0
1112 23:41:53.183732 Final RX Vref Byte 0 = 59 to rank1
1113 23:41:53.187496 Final RX Vref Byte 1 = 54 to rank1==
1114 23:41:53.190718 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 23:41:53.197396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 23:41:53.197533 ==
1117 23:41:53.197635 DQS Delay:
1118 23:41:53.197727 DQS0 = 0, DQS1 = 0
1119 23:41:53.200627 DQM Delay:
1120 23:41:53.200748 DQM0 = 81, DQM1 = 67
1121 23:41:53.203734 DQ Delay:
1122 23:41:53.206957 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1123 23:41:53.207062 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1124 23:41:53.210478 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1125 23:41:53.213815 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1126 23:41:53.217067
1127 23:41:53.217191
1128 23:41:53.224003 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1129 23:41:53.226974 CH0 RK0: MR19=606, MR18=2A29
1130 23:41:53.233742 CH0_RK0: MR19=0x606, MR18=0x2A29, DQSOSC=399, MR23=63, INC=92, DEC=61
1131 23:41:53.233919
1132 23:41:53.237308 ----->DramcWriteLeveling(PI) begin...
1133 23:41:53.237444 ==
1134 23:41:53.240483 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 23:41:53.243784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 23:41:53.243921 ==
1137 23:41:53.247176 Write leveling (Byte 0): 31 => 31
1138 23:41:53.250382 Write leveling (Byte 1): 29 => 29
1139 23:41:53.253994 DramcWriteLeveling(PI) end<-----
1140 23:41:53.254140
1141 23:41:53.254266 ==
1142 23:41:53.257172 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 23:41:53.260574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 23:41:53.260715 ==
1145 23:41:53.263894 [Gating] SW mode calibration
1146 23:41:53.270425 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 23:41:53.276897 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 23:41:53.280007 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 23:41:53.283677 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1150 23:41:53.290174 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1151 23:41:53.293683 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 23:41:53.296703 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 23:41:53.303344 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 23:41:53.306734 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 23:41:53.310292 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:41:53.317196 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:41:53.320277 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:41:53.323607 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:41:53.330397 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:41:53.333909 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:41:53.336678 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:41:53.343791 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:41:53.387702 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:41:53.388036 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1165 23:41:53.388113 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1166 23:41:53.388179 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1167 23:41:53.388662 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:41:53.388966 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:41:53.389076 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:41:53.389172 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:41:53.389281 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:41:53.389375 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:41:53.418459 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:41:53.418806 0 9 8 | B1->B0 | 2323 2c2c | 1 1 | (1 1) (0 0)
1175 23:41:53.418881 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1176 23:41:53.418958 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 23:41:53.419054 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 23:41:53.419308 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 23:41:53.422666 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 23:41:53.422778 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:41:53.425982 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
1182 23:41:53.429206 0 10 8 | B1->B0 | 3030 2626 | 0 0 | (1 0) (0 0)
1183 23:41:53.435555 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 23:41:53.438878 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:41:53.442319 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:41:53.449156 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:41:53.452348 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:41:53.455706 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:41:53.458979 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1190 23:41:53.465605 0 11 8 | B1->B0 | 3131 3c3c | 0 0 | (0 0) (0 0)
1191 23:41:53.469316 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1192 23:41:53.472284 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 23:41:53.479147 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 23:41:53.482355 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 23:41:53.485809 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:41:53.492121 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:41:53.496008 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 23:41:53.499543 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1199 23:41:53.503475 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1200 23:41:53.510695 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 23:41:53.514063 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 23:41:53.517808 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:41:53.520951 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:41:53.528294 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:41:53.532009 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:41:53.535324 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:41:53.538489 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:41:53.545109 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:41:53.548769 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:41:53.551566 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:41:53.558712 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:41:53.561602 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:41:53.565561 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1214 23:41:53.571542 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1215 23:41:53.575264 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 23:41:53.578278 Total UI for P1: 0, mck2ui 16
1217 23:41:53.581997 best dqsien dly found for B0: ( 0, 14, 6)
1218 23:41:53.585537 Total UI for P1: 0, mck2ui 16
1219 23:41:53.588741 best dqsien dly found for B1: ( 0, 14, 8)
1220 23:41:53.591881 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1221 23:41:53.595039 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1222 23:41:53.595155
1223 23:41:53.598488 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1224 23:41:53.602094 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 23:41:53.605308 [Gating] SW calibration Done
1226 23:41:53.605410 ==
1227 23:41:53.608668 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 23:41:53.611878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 23:41:53.611973 ==
1230 23:41:53.615321 RX Vref Scan: 0
1231 23:41:53.615414
1232 23:41:53.615484 RX Vref 0 -> 0, step: 1
1233 23:41:53.618732
1234 23:41:53.618852 RX Delay -130 -> 252, step: 16
1235 23:41:53.625435 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1236 23:41:53.628922 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1237 23:41:53.632229 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1238 23:41:53.635553 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1239 23:41:53.638942 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1240 23:41:53.645367 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1241 23:41:53.648932 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1242 23:41:53.652079 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1243 23:41:53.655164 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1244 23:41:53.658624 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1245 23:41:53.662206 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1246 23:41:53.668729 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1247 23:41:53.672216 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1248 23:41:53.675351 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1249 23:41:53.678679 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1250 23:41:53.685730 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1251 23:41:53.685857 ==
1252 23:41:53.688829 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 23:41:53.692054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 23:41:53.692180 ==
1255 23:41:53.692278 DQS Delay:
1256 23:41:53.695160 DQS0 = 0, DQS1 = 0
1257 23:41:53.695250 DQM Delay:
1258 23:41:53.699001 DQM0 = 78, DQM1 = 70
1259 23:41:53.699097 DQ Delay:
1260 23:41:53.702086 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =77
1261 23:41:53.705435 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =93
1262 23:41:53.708669 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1263 23:41:53.711887 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1264 23:41:53.711983
1265 23:41:53.712052
1266 23:41:53.712115 ==
1267 23:41:53.715519 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 23:41:53.718359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 23:41:53.718487 ==
1270 23:41:53.718577
1271 23:41:53.718641
1272 23:41:53.721852 TX Vref Scan disable
1273 23:41:53.725200 == TX Byte 0 ==
1274 23:41:53.728816 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1275 23:41:53.731826 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1276 23:41:53.735343 == TX Byte 1 ==
1277 23:41:53.738298 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1278 23:41:53.741940 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1279 23:41:53.742063 ==
1280 23:41:53.745322 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 23:41:53.751663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 23:41:53.751820 ==
1283 23:41:53.763644 TX Vref=22, minBit 9, minWin=26, winSum=434
1284 23:41:53.766554 TX Vref=24, minBit 1, minWin=27, winSum=437
1285 23:41:53.770253 TX Vref=26, minBit 1, minWin=27, winSum=440
1286 23:41:53.773665 TX Vref=28, minBit 1, minWin=27, winSum=441
1287 23:41:53.776708 TX Vref=30, minBit 14, minWin=27, winSum=448
1288 23:41:53.780728 TX Vref=32, minBit 1, minWin=27, winSum=443
1289 23:41:53.786949 [TxChooseVref] Worse bit 14, Min win 27, Win sum 448, Final Vref 30
1290 23:41:53.787115
1291 23:41:53.790179 Final TX Range 1 Vref 30
1292 23:41:53.790298
1293 23:41:53.790395 ==
1294 23:41:53.793801 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 23:41:53.797157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 23:41:53.797307 ==
1297 23:41:53.797424
1298 23:41:53.800392
1299 23:41:53.800529 TX Vref Scan disable
1300 23:41:53.803522 == TX Byte 0 ==
1301 23:41:53.806767 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1302 23:41:53.813598 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1303 23:41:53.813749 == TX Byte 1 ==
1304 23:41:53.816888 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1305 23:41:53.823147 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1306 23:41:53.823271
1307 23:41:53.823338 [DATLAT]
1308 23:41:53.823401 Freq=800, CH0 RK1
1309 23:41:53.823468
1310 23:41:53.826628 DATLAT Default: 0xa
1311 23:41:53.826712 0, 0xFFFF, sum = 0
1312 23:41:53.830162 1, 0xFFFF, sum = 0
1313 23:41:53.833508 2, 0xFFFF, sum = 0
1314 23:41:53.833610 3, 0xFFFF, sum = 0
1315 23:41:53.836545 4, 0xFFFF, sum = 0
1316 23:41:53.836638 5, 0xFFFF, sum = 0
1317 23:41:53.839706 6, 0xFFFF, sum = 0
1318 23:41:53.839829 7, 0xFFFF, sum = 0
1319 23:41:53.843524 8, 0xFFFF, sum = 0
1320 23:41:53.843620 9, 0x0, sum = 1
1321 23:41:53.846297 10, 0x0, sum = 2
1322 23:41:53.846380 11, 0x0, sum = 3
1323 23:41:53.850384 12, 0x0, sum = 4
1324 23:41:53.850478 best_step = 10
1325 23:41:53.850543
1326 23:41:53.850603 ==
1327 23:41:53.852870 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 23:41:53.856452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 23:41:53.856539 ==
1330 23:41:53.859837 RX Vref Scan: 0
1331 23:41:53.859921
1332 23:41:53.863070 RX Vref 0 -> 0, step: 1
1333 23:41:53.863192
1334 23:41:53.863286 RX Delay -111 -> 252, step: 8
1335 23:41:53.870435 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1336 23:41:53.873986 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1337 23:41:53.876879 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1338 23:41:53.880658 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1339 23:41:53.883927 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1340 23:41:53.890436 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1341 23:41:53.893556 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1342 23:41:53.897155 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1343 23:41:53.900423 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1344 23:41:53.903565 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1345 23:41:53.910137 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1346 23:41:53.913649 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1347 23:41:53.917330 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1348 23:41:53.920825 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1349 23:41:53.923750 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1350 23:41:53.930418 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1351 23:41:53.930536 ==
1352 23:41:53.933580 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 23:41:53.936982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 23:41:53.937085 ==
1355 23:41:53.937155 DQS Delay:
1356 23:41:53.940289 DQS0 = 0, DQS1 = 0
1357 23:41:53.940411 DQM Delay:
1358 23:41:53.943563 DQM0 = 78, DQM1 = 70
1359 23:41:53.943683 DQ Delay:
1360 23:41:53.946835 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1361 23:41:53.949933 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1362 23:41:53.953790 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1363 23:41:53.956625 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =76
1364 23:41:53.956715
1365 23:41:53.956781
1366 23:41:53.966976 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a25, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
1367 23:41:53.967120 CH0 RK1: MR19=606, MR18=4A25
1368 23:41:53.973526 CH0_RK1: MR19=0x606, MR18=0x4A25, DQSOSC=391, MR23=63, INC=96, DEC=64
1369 23:41:53.976730 [RxdqsGatingPostProcess] freq 800
1370 23:41:53.983531 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 23:41:53.986841 Pre-setting of DQS Precalculation
1372 23:41:53.990178 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 23:41:53.990266 ==
1374 23:41:53.993317 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 23:41:53.996584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 23:41:53.996680 ==
1377 23:41:54.003508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 23:41:54.009962 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 23:41:54.018768 [CA 0] Center 36 (6~66) winsize 61
1380 23:41:54.022007 [CA 1] Center 36 (6~67) winsize 62
1381 23:41:54.025167 [CA 2] Center 34 (4~64) winsize 61
1382 23:41:54.028489 [CA 3] Center 34 (4~64) winsize 61
1383 23:41:54.031769 [CA 4] Center 34 (4~64) winsize 61
1384 23:41:54.035204 [CA 5] Center 33 (3~64) winsize 62
1385 23:41:54.035306
1386 23:41:54.038626 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1387 23:41:54.038726
1388 23:41:54.041806 [CATrainingPosCal] consider 1 rank data
1389 23:41:54.045390 u2DelayCellTimex100 = 270/100 ps
1390 23:41:54.049092 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1391 23:41:54.052123 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1392 23:41:54.058664 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1393 23:41:54.061947 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1394 23:41:54.065140 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1395 23:41:54.068614 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1396 23:41:54.068765
1397 23:41:54.072109 CA PerBit enable=1, Macro0, CA PI delay=33
1398 23:41:54.072246
1399 23:41:54.075305 [CBTSetCACLKResult] CA Dly = 33
1400 23:41:54.075444 CS Dly: 4 (0~35)
1401 23:41:54.078599 ==
1402 23:41:54.078744 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 23:41:54.085062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 23:41:54.085227 ==
1405 23:41:54.088564 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 23:41:54.095319 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 23:41:54.104852 [CA 0] Center 37 (7~67) winsize 61
1408 23:41:54.108237 [CA 1] Center 37 (7~67) winsize 61
1409 23:41:54.111438 [CA 2] Center 34 (4~65) winsize 62
1410 23:41:54.114729 [CA 3] Center 34 (4~64) winsize 61
1411 23:41:54.117902 [CA 4] Center 34 (4~65) winsize 62
1412 23:41:54.121251 [CA 5] Center 33 (3~64) winsize 62
1413 23:41:54.121392
1414 23:41:54.124503 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1415 23:41:54.124644
1416 23:41:54.128320 [CATrainingPosCal] consider 2 rank data
1417 23:41:54.131578 u2DelayCellTimex100 = 270/100 ps
1418 23:41:54.134751 CA0 delay=36 (7~66),Diff = 3 PI (21 cell)
1419 23:41:54.138082 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
1420 23:41:54.144614 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1421 23:41:54.148231 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1422 23:41:54.151225 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1423 23:41:54.154922 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1424 23:41:54.155020
1425 23:41:54.158403 CA PerBit enable=1, Macro0, CA PI delay=33
1426 23:41:54.158500
1427 23:41:54.162152 [CBTSetCACLKResult] CA Dly = 33
1428 23:41:54.162264 CS Dly: 5 (0~38)
1429 23:41:54.162360
1430 23:41:54.165796 ----->DramcWriteLeveling(PI) begin...
1431 23:41:54.165900 ==
1432 23:41:54.169710 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 23:41:54.173402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 23:41:54.173505 ==
1435 23:41:54.177047 Write leveling (Byte 0): 30 => 30
1436 23:41:54.180828 Write leveling (Byte 1): 29 => 29
1437 23:41:54.184327 DramcWriteLeveling(PI) end<-----
1438 23:41:54.184457
1439 23:41:54.184570 ==
1440 23:41:54.187657 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 23:41:54.191418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 23:41:54.191553 ==
1443 23:41:54.194998 [Gating] SW mode calibration
1444 23:41:54.201613 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 23:41:54.205361 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 23:41:54.211531 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1447 23:41:54.214749 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 23:41:54.218645 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 23:41:54.225121 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 23:41:54.228361 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 23:41:54.231749 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 23:41:54.238259 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 23:41:54.241568 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:41:54.244828 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:41:54.251453 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:41:54.255025 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:41:54.258091 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:41:54.264800 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:41:54.268309 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:41:54.271359 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:41:54.274978 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:41:54.281333 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1463 23:41:54.285045 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:41:54.288144 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:41:54.294780 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:41:54.298041 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:41:54.301595 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:41:54.308328 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:41:54.311212 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:41:54.314850 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:41:54.321245 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:41:54.324649 0 9 8 | B1->B0 | 2c2c 2c2c | 0 1 | (0 0) (1 1)
1473 23:41:54.328332 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 23:41:54.334885 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 23:41:54.338117 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 23:41:54.341455 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 23:41:54.347931 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 23:41:54.351189 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 23:41:54.355035 0 10 4 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
1480 23:41:54.361520 0 10 8 | B1->B0 | 2c2c 2929 | 1 0 | (1 0) (1 0)
1481 23:41:54.364588 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 23:41:54.367925 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 23:41:54.374928 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:41:54.378431 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:41:54.381421 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:41:54.384993 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:41:54.391533 0 11 4 | B1->B0 | 2525 2626 | 0 1 | (0 0) (0 0)
1488 23:41:54.394649 0 11 8 | B1->B0 | 3838 3737 | 0 0 | (0 0) (0 0)
1489 23:41:54.398316 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 23:41:54.405142 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 23:41:54.408122 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 23:41:54.411470 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 23:41:54.418350 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 23:41:54.421352 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:41:54.424613 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 23:41:54.431463 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1497 23:41:54.434837 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1498 23:41:54.438137 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 23:41:54.444518 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 23:41:54.447752 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 23:41:54.450991 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:41:54.458128 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:41:54.461326 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:41:54.464618 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:41:54.471019 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:41:54.474883 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:41:54.477850 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:41:54.484612 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:41:54.487668 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:41:54.491134 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:41:54.495047 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:41:54.501256 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1513 23:41:54.504583 Total UI for P1: 0, mck2ui 16
1514 23:41:54.507791 best dqsien dly found for B0: ( 0, 14, 6)
1515 23:41:54.511437 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 23:41:54.514661 Total UI for P1: 0, mck2ui 16
1517 23:41:54.518233 best dqsien dly found for B1: ( 0, 14, 8)
1518 23:41:54.521696 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1519 23:41:54.524792 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1520 23:41:54.524899
1521 23:41:54.527814 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1522 23:41:54.531125 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1523 23:41:54.534463 [Gating] SW calibration Done
1524 23:41:54.534572 ==
1525 23:41:54.538068 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 23:41:54.541069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 23:41:54.544419 ==
1528 23:41:54.544525 RX Vref Scan: 0
1529 23:41:54.544618
1530 23:41:54.548154 RX Vref 0 -> 0, step: 1
1531 23:41:54.548260
1532 23:41:54.551464 RX Delay -130 -> 252, step: 16
1533 23:41:54.554733 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1534 23:41:54.558069 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1535 23:41:54.561323 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1536 23:41:54.564612 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1537 23:41:54.571197 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1538 23:41:54.574829 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1539 23:41:54.578051 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1540 23:41:54.581312 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1541 23:41:54.584518 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1542 23:41:54.588128 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1543 23:41:54.595040 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1544 23:41:54.598028 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1545 23:41:54.601497 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1546 23:41:54.604918 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1547 23:41:54.611365 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1548 23:41:54.614836 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1549 23:41:54.614947 ==
1550 23:41:54.618230 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 23:41:54.621468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 23:41:54.621555 ==
1553 23:41:54.624527 DQS Delay:
1554 23:41:54.624626 DQS0 = 0, DQS1 = 0
1555 23:41:54.624693 DQM Delay:
1556 23:41:54.627908 DQM0 = 81, DQM1 = 70
1557 23:41:54.627991 DQ Delay:
1558 23:41:54.630938 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1559 23:41:54.634935 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1560 23:41:54.637969 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
1561 23:41:54.641170 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1562 23:41:54.641255
1563 23:41:54.641323
1564 23:41:54.641385 ==
1565 23:41:54.644672 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 23:41:54.647675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 23:41:54.651471 ==
1568 23:41:54.651606
1569 23:41:54.651725
1570 23:41:54.651840 TX Vref Scan disable
1571 23:41:54.654723 == TX Byte 0 ==
1572 23:41:54.657929 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1573 23:41:54.661192 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1574 23:41:54.664517 == TX Byte 1 ==
1575 23:41:54.667908 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1576 23:41:54.671170 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1577 23:41:54.674424 ==
1578 23:41:54.677687 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 23:41:54.681283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 23:41:54.681373 ==
1581 23:41:54.693756 TX Vref=22, minBit 0, minWin=27, winSum=441
1582 23:41:54.696981 TX Vref=24, minBit 1, minWin=26, winSum=440
1583 23:41:54.700220 TX Vref=26, minBit 4, minWin=27, winSum=443
1584 23:41:54.703714 TX Vref=28, minBit 4, minWin=27, winSum=448
1585 23:41:54.706712 TX Vref=30, minBit 4, minWin=27, winSum=450
1586 23:41:54.710302 TX Vref=32, minBit 4, minWin=27, winSum=448
1587 23:41:54.717035 [TxChooseVref] Worse bit 4, Min win 27, Win sum 450, Final Vref 30
1588 23:41:54.717130
1589 23:41:54.720213 Final TX Range 1 Vref 30
1590 23:41:54.720297
1591 23:41:54.720383 ==
1592 23:41:54.723405 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 23:41:54.726888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 23:41:54.726976 ==
1595 23:41:54.727061
1596 23:41:54.727140
1597 23:41:54.730421 TX Vref Scan disable
1598 23:41:54.733451 == TX Byte 0 ==
1599 23:41:54.737165 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1600 23:41:54.741139 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1601 23:41:54.744313 == TX Byte 1 ==
1602 23:41:54.747932 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1603 23:41:54.751294 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1604 23:41:54.751403
1605 23:41:54.754618 [DATLAT]
1606 23:41:54.754721 Freq=800, CH1 RK0
1607 23:41:54.754822
1608 23:41:54.757912 DATLAT Default: 0xa
1609 23:41:54.757985 0, 0xFFFF, sum = 0
1610 23:41:54.761096 1, 0xFFFF, sum = 0
1611 23:41:54.761168 2, 0xFFFF, sum = 0
1612 23:41:54.764627 3, 0xFFFF, sum = 0
1613 23:41:54.764716 4, 0xFFFF, sum = 0
1614 23:41:54.767687 5, 0xFFFF, sum = 0
1615 23:41:54.767759 6, 0xFFFF, sum = 0
1616 23:41:54.771347 7, 0xFFFF, sum = 0
1617 23:41:54.771417 8, 0xFFFF, sum = 0
1618 23:41:54.774642 9, 0x0, sum = 1
1619 23:41:54.774723 10, 0x0, sum = 2
1620 23:41:54.777856 11, 0x0, sum = 3
1621 23:41:54.777943 12, 0x0, sum = 4
1622 23:41:54.778009 best_step = 10
1623 23:41:54.781271
1624 23:41:54.781342 ==
1625 23:41:54.784338 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 23:41:54.787546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 23:41:54.787622 ==
1628 23:41:54.787708 RX Vref Scan: 1
1629 23:41:54.787786
1630 23:41:54.791385 Set Vref Range= 32 -> 127
1631 23:41:54.791463
1632 23:41:54.794750 RX Vref 32 -> 127, step: 1
1633 23:41:54.794832
1634 23:41:54.797828 RX Delay -111 -> 252, step: 8
1635 23:41:54.797913
1636 23:41:54.801039 Set Vref, RX VrefLevel [Byte0]: 32
1637 23:41:54.804903 [Byte1]: 32
1638 23:41:54.805029
1639 23:41:54.807968 Set Vref, RX VrefLevel [Byte0]: 33
1640 23:41:54.811509 [Byte1]: 33
1641 23:41:54.811645
1642 23:41:54.814630 Set Vref, RX VrefLevel [Byte0]: 34
1643 23:41:54.817790 [Byte1]: 34
1644 23:41:54.821497
1645 23:41:54.821575 Set Vref, RX VrefLevel [Byte0]: 35
1646 23:41:54.825157 [Byte1]: 35
1647 23:41:54.829621
1648 23:41:54.829734 Set Vref, RX VrefLevel [Byte0]: 36
1649 23:41:54.832706 [Byte1]: 36
1650 23:41:54.836604
1651 23:41:54.836687 Set Vref, RX VrefLevel [Byte0]: 37
1652 23:41:54.839901 [Byte1]: 37
1653 23:41:54.844276
1654 23:41:54.844379 Set Vref, RX VrefLevel [Byte0]: 38
1655 23:41:54.847970 [Byte1]: 38
1656 23:41:54.852319
1657 23:41:54.852441 Set Vref, RX VrefLevel [Byte0]: 39
1658 23:41:54.855336 [Byte1]: 39
1659 23:41:54.860012
1660 23:41:54.860120 Set Vref, RX VrefLevel [Byte0]: 40
1661 23:41:54.863119 [Byte1]: 40
1662 23:41:54.867648
1663 23:41:54.867760 Set Vref, RX VrefLevel [Byte0]: 41
1664 23:41:54.870858 [Byte1]: 41
1665 23:41:54.875224
1666 23:41:54.875335 Set Vref, RX VrefLevel [Byte0]: 42
1667 23:41:54.878501 [Byte1]: 42
1668 23:41:54.882943
1669 23:41:54.883047 Set Vref, RX VrefLevel [Byte0]: 43
1670 23:41:54.886092 [Byte1]: 43
1671 23:41:54.890369
1672 23:41:54.890486 Set Vref, RX VrefLevel [Byte0]: 44
1673 23:41:54.893669 [Byte1]: 44
1674 23:41:54.897982
1675 23:41:54.898083 Set Vref, RX VrefLevel [Byte0]: 45
1676 23:41:54.901176 [Byte1]: 45
1677 23:41:54.905997
1678 23:41:54.906133 Set Vref, RX VrefLevel [Byte0]: 46
1679 23:41:54.909283 [Byte1]: 46
1680 23:41:54.913279
1681 23:41:54.913403 Set Vref, RX VrefLevel [Byte0]: 47
1682 23:41:54.916712 [Byte1]: 47
1683 23:41:54.920782
1684 23:41:54.920911 Set Vref, RX VrefLevel [Byte0]: 48
1685 23:41:54.924081 [Byte1]: 48
1686 23:41:54.928767
1687 23:41:54.928898 Set Vref, RX VrefLevel [Byte0]: 49
1688 23:41:54.931928 [Byte1]: 49
1689 23:41:54.936514
1690 23:41:54.936619 Set Vref, RX VrefLevel [Byte0]: 50
1691 23:41:54.939762 [Byte1]: 50
1692 23:41:54.944228
1693 23:41:54.944341 Set Vref, RX VrefLevel [Byte0]: 51
1694 23:41:54.947494 [Byte1]: 51
1695 23:41:54.951922
1696 23:41:54.952026 Set Vref, RX VrefLevel [Byte0]: 52
1697 23:41:54.954889 [Byte1]: 52
1698 23:41:54.959124
1699 23:41:54.959202 Set Vref, RX VrefLevel [Byte0]: 53
1700 23:41:54.962593 [Byte1]: 53
1701 23:41:54.967064
1702 23:41:54.967172 Set Vref, RX VrefLevel [Byte0]: 54
1703 23:41:54.970306 [Byte1]: 54
1704 23:41:54.974574
1705 23:41:54.974685 Set Vref, RX VrefLevel [Byte0]: 55
1706 23:41:54.978234 [Byte1]: 55
1707 23:41:54.982251
1708 23:41:54.982343 Set Vref, RX VrefLevel [Byte0]: 56
1709 23:41:54.985547 [Byte1]: 56
1710 23:41:54.989896
1711 23:41:54.990029 Set Vref, RX VrefLevel [Byte0]: 57
1712 23:41:54.992975 [Byte1]: 57
1713 23:41:54.997367
1714 23:41:54.997497 Set Vref, RX VrefLevel [Byte0]: 58
1715 23:41:55.000719 [Byte1]: 58
1716 23:41:55.004914
1717 23:41:55.005034 Set Vref, RX VrefLevel [Byte0]: 59
1718 23:41:55.008240 [Byte1]: 59
1719 23:41:55.012801
1720 23:41:55.012888 Set Vref, RX VrefLevel [Byte0]: 60
1721 23:41:55.016021 [Byte1]: 60
1722 23:41:55.020358
1723 23:41:55.020491 Set Vref, RX VrefLevel [Byte0]: 61
1724 23:41:55.023913 [Byte1]: 61
1725 23:41:55.028291
1726 23:41:55.028432 Set Vref, RX VrefLevel [Byte0]: 62
1727 23:41:55.031370 [Byte1]: 62
1728 23:41:55.035729
1729 23:41:55.035857 Set Vref, RX VrefLevel [Byte0]: 63
1730 23:41:55.039268 [Byte1]: 63
1731 23:41:55.043422
1732 23:41:55.043554 Set Vref, RX VrefLevel [Byte0]: 64
1733 23:41:55.046653 [Byte1]: 64
1734 23:41:55.051034
1735 23:41:55.051178 Set Vref, RX VrefLevel [Byte0]: 65
1736 23:41:55.054342 [Byte1]: 65
1737 23:41:55.058750
1738 23:41:55.058882 Set Vref, RX VrefLevel [Byte0]: 66
1739 23:41:55.062291 [Byte1]: 66
1740 23:41:55.066498
1741 23:41:55.066614 Set Vref, RX VrefLevel [Byte0]: 67
1742 23:41:55.069597 [Byte1]: 67
1743 23:41:55.074141
1744 23:41:55.074252 Set Vref, RX VrefLevel [Byte0]: 68
1745 23:41:55.077674 [Byte1]: 68
1746 23:41:55.081795
1747 23:41:55.081903 Set Vref, RX VrefLevel [Byte0]: 69
1748 23:41:55.084977 [Byte1]: 69
1749 23:41:55.088963
1750 23:41:55.089066 Set Vref, RX VrefLevel [Byte0]: 70
1751 23:41:55.092349 [Byte1]: 70
1752 23:41:55.096902
1753 23:41:55.097012 Set Vref, RX VrefLevel [Byte0]: 71
1754 23:41:55.100382 [Byte1]: 71
1755 23:41:55.104484
1756 23:41:55.104589 Set Vref, RX VrefLevel [Byte0]: 72
1757 23:41:55.107886 [Byte1]: 72
1758 23:41:55.112192
1759 23:41:55.112274 Set Vref, RX VrefLevel [Byte0]: 73
1760 23:41:55.115305 [Byte1]: 73
1761 23:41:55.119596
1762 23:41:55.119705 Set Vref, RX VrefLevel [Byte0]: 74
1763 23:41:55.122994 [Byte1]: 74
1764 23:41:55.127312
1765 23:41:55.127419 Final RX Vref Byte 0 = 61 to rank0
1766 23:41:55.130531 Final RX Vref Byte 1 = 54 to rank0
1767 23:41:55.134006 Final RX Vref Byte 0 = 61 to rank1
1768 23:41:55.137517 Final RX Vref Byte 1 = 54 to rank1==
1769 23:41:55.140685 Dram Type= 6, Freq= 0, CH_1, rank 0
1770 23:41:55.147283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1771 23:41:55.147381 ==
1772 23:41:55.147451 DQS Delay:
1773 23:41:55.147513 DQS0 = 0, DQS1 = 0
1774 23:41:55.150631 DQM Delay:
1775 23:41:55.150704 DQM0 = 80, DQM1 = 72
1776 23:41:55.154352 DQ Delay:
1777 23:41:55.157875 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1778 23:41:55.157953 DQ4 =76, DQ5 =96, DQ6 =92, DQ7 =76
1779 23:41:55.160713 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1780 23:41:55.164399 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
1781 23:41:55.167538
1782 23:41:55.167656
1783 23:41:55.174303 [DQSOSCAuto] RK0, (LSB)MR18= 0xf19, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 406 ps
1784 23:41:55.177516 CH1 RK0: MR19=606, MR18=F19
1785 23:41:55.184480 CH1_RK0: MR19=0x606, MR18=0xF19, DQSOSC=403, MR23=63, INC=90, DEC=60
1786 23:41:55.184610
1787 23:41:55.187575 ----->DramcWriteLeveling(PI) begin...
1788 23:41:55.187683 ==
1789 23:41:55.190885 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 23:41:55.193924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 23:41:55.194034 ==
1792 23:41:55.197527 Write leveling (Byte 0): 27 => 27
1793 23:41:55.200784 Write leveling (Byte 1): 27 => 27
1794 23:41:55.203845 DramcWriteLeveling(PI) end<-----
1795 23:41:55.203955
1796 23:41:55.204050 ==
1797 23:41:55.207038 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 23:41:55.210798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 23:41:55.210878 ==
1800 23:41:55.214065 [Gating] SW mode calibration
1801 23:41:55.220377 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1802 23:41:55.227601 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1803 23:41:55.230880 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1804 23:41:55.234220 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1805 23:41:55.240482 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 23:41:55.244024 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 23:41:55.247449 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 23:41:55.253753 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 23:41:55.257059 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 23:41:55.260886 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 23:41:55.267175 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 23:41:55.270286 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 23:41:55.274106 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 23:41:55.280309 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 23:41:55.283607 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 23:41:55.287363 0 7 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1817 23:41:55.290590 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:41:55.297228 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:41:55.300368 0 8 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1820 23:41:55.303678 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1821 23:41:55.310450 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1822 23:41:55.313595 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:41:55.316944 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:41:55.323806 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:41:55.327164 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:41:55.330403 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:41:55.337104 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:41:55.340482 0 9 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1829 23:41:55.343787 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1830 23:41:55.350669 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 23:41:55.353923 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 23:41:55.357075 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 23:41:55.364007 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 23:41:55.367302 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 23:41:55.370323 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1836 23:41:55.376885 0 10 4 | B1->B0 | 3232 2c2c | 0 0 | (1 1) (1 1)
1837 23:41:55.380670 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1838 23:41:55.383741 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:41:55.386965 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 23:41:55.394070 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:41:55.397268 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 23:41:55.400731 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 23:41:55.407099 0 11 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1844 23:41:55.410603 0 11 4 | B1->B0 | 3030 3939 | 1 0 | (0 0) (0 0)
1845 23:41:55.413711 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1846 23:41:55.420361 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 23:41:55.424204 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 23:41:55.427346 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 23:41:55.433722 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 23:41:55.436971 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 23:41:55.440309 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 23:41:55.447384 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1853 23:41:55.450634 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 23:41:55.453800 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 23:41:55.460457 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 23:41:55.463679 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 23:41:55.466902 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 23:41:55.473626 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 23:41:55.477188 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 23:41:55.480645 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 23:41:55.486940 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 23:41:55.490395 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 23:41:55.493717 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 23:41:55.496700 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 23:41:55.503921 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 23:41:55.507156 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 23:41:55.510398 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 23:41:55.516809 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1869 23:41:55.520168 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1870 23:41:55.524036 Total UI for P1: 0, mck2ui 16
1871 23:41:55.527296 best dqsien dly found for B0: ( 0, 14, 4)
1872 23:41:55.530581 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 23:41:55.533644 Total UI for P1: 0, mck2ui 16
1874 23:41:55.537026 best dqsien dly found for B1: ( 0, 14, 6)
1875 23:41:55.540206 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1876 23:41:55.543567 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1877 23:41:55.543646
1878 23:41:55.550252 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1879 23:41:55.553305 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1880 23:41:55.553391 [Gating] SW calibration Done
1881 23:41:55.557031 ==
1882 23:41:55.560193 Dram Type= 6, Freq= 0, CH_1, rank 1
1883 23:41:55.563669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1884 23:41:55.563763 ==
1885 23:41:55.563830 RX Vref Scan: 0
1886 23:41:55.563891
1887 23:41:55.566928 RX Vref 0 -> 0, step: 1
1888 23:41:55.567008
1889 23:41:55.570086 RX Delay -130 -> 252, step: 16
1890 23:41:55.573378 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1891 23:41:55.576943 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1892 23:41:55.583486 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1893 23:41:55.586713 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1894 23:41:55.590054 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1895 23:41:55.593312 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1896 23:41:55.597020 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1897 23:41:55.600173 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1898 23:41:55.606815 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1899 23:41:55.610590 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1900 23:41:55.613922 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1901 23:41:55.616797 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1902 23:41:55.620304 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1903 23:41:55.627200 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1904 23:41:55.630071 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1905 23:41:55.633431 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1906 23:41:55.633521 ==
1907 23:41:55.637030 Dram Type= 6, Freq= 0, CH_1, rank 1
1908 23:41:55.640167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1909 23:41:55.643316 ==
1910 23:41:55.643424 DQS Delay:
1911 23:41:55.643540 DQS0 = 0, DQS1 = 0
1912 23:41:55.646587 DQM Delay:
1913 23:41:55.646662 DQM0 = 78, DQM1 = 71
1914 23:41:55.646725 DQ Delay:
1915 23:41:55.650544 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1916 23:41:55.653769 DQ4 =77, DQ5 =85, DQ6 =93, DQ7 =77
1917 23:41:55.657012 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =61
1918 23:41:55.660094 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1919 23:41:55.660171
1920 23:41:55.660236
1921 23:41:55.663422 ==
1922 23:41:55.666593 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 23:41:55.670032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 23:41:55.670112 ==
1925 23:41:55.670191
1926 23:41:55.670252
1927 23:41:55.673693 TX Vref Scan disable
1928 23:41:55.673776 == TX Byte 0 ==
1929 23:41:55.676900 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1930 23:41:55.683716 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1931 23:41:55.683813 == TX Byte 1 ==
1932 23:41:55.687135 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1933 23:41:55.693651 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1934 23:41:55.693736 ==
1935 23:41:55.696921 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 23:41:55.700149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 23:41:55.700230 ==
1938 23:41:55.713111 TX Vref=22, minBit 1, minWin=27, winSum=448
1939 23:41:55.716918 TX Vref=24, minBit 0, minWin=28, winSum=454
1940 23:41:55.720105 TX Vref=26, minBit 0, minWin=28, winSum=458
1941 23:41:55.723218 TX Vref=28, minBit 5, minWin=27, winSum=458
1942 23:41:55.726319 TX Vref=30, minBit 5, minWin=27, winSum=458
1943 23:41:55.729779 TX Vref=32, minBit 0, minWin=28, winSum=458
1944 23:41:55.736766 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 26
1945 23:41:55.736890
1946 23:41:55.739699 Final TX Range 1 Vref 26
1947 23:41:55.739797
1948 23:41:55.739893 ==
1949 23:41:55.743480 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 23:41:55.746553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 23:41:55.746638 ==
1952 23:41:55.746703
1953 23:41:55.749592
1954 23:41:55.749673 TX Vref Scan disable
1955 23:41:55.753054 == TX Byte 0 ==
1956 23:41:55.756218 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1957 23:41:55.759668 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1958 23:41:55.763044 == TX Byte 1 ==
1959 23:41:55.766564 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1960 23:41:55.773043 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1961 23:41:55.773146
1962 23:41:55.773214 [DATLAT]
1963 23:41:55.773277 Freq=800, CH1 RK1
1964 23:41:55.773337
1965 23:41:55.776363 DATLAT Default: 0xa
1966 23:41:55.776473 0, 0xFFFF, sum = 0
1967 23:41:55.779557 1, 0xFFFF, sum = 0
1968 23:41:55.779676 2, 0xFFFF, sum = 0
1969 23:41:55.782779 3, 0xFFFF, sum = 0
1970 23:41:55.782894 4, 0xFFFF, sum = 0
1971 23:41:55.786388 5, 0xFFFF, sum = 0
1972 23:41:55.790096 6, 0xFFFF, sum = 0
1973 23:41:55.790210 7, 0xFFFF, sum = 0
1974 23:41:55.792802 8, 0xFFFF, sum = 0
1975 23:41:55.792918 9, 0x0, sum = 1
1976 23:41:55.793016 10, 0x0, sum = 2
1977 23:41:55.796659 11, 0x0, sum = 3
1978 23:41:55.796772 12, 0x0, sum = 4
1979 23:41:55.799859 best_step = 10
1980 23:41:55.799944
1981 23:41:55.800013 ==
1982 23:41:55.803137 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 23:41:55.806393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 23:41:55.806486 ==
1985 23:41:55.809664 RX Vref Scan: 0
1986 23:41:55.809746
1987 23:41:55.809813 RX Vref 0 -> 0, step: 1
1988 23:41:55.809876
1989 23:41:55.812961 RX Delay -111 -> 252, step: 8
1990 23:41:55.819855 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
1991 23:41:55.823228 iDelay=209, Bit 1, Center 68 (-55 ~ 192) 248
1992 23:41:55.826245 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1993 23:41:55.829551 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1994 23:41:55.834026 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1995 23:41:55.839511 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1996 23:41:55.843237 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1997 23:41:55.846135 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
1998 23:41:55.849901 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
1999 23:41:55.853041 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2000 23:41:55.859713 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2001 23:41:55.862935 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2002 23:41:55.866385 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2003 23:41:55.869896 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2004 23:41:55.876103 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2005 23:41:55.879515 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2006 23:41:55.879638 ==
2007 23:41:55.882863 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 23:41:55.886126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 23:41:55.886235 ==
2010 23:41:55.886336 DQS Delay:
2011 23:41:55.889661 DQS0 = 0, DQS1 = 0
2012 23:41:55.889742 DQM Delay:
2013 23:41:55.893147 DQM0 = 77, DQM1 = 74
2014 23:41:55.893278 DQ Delay:
2015 23:41:55.896326 DQ0 =84, DQ1 =68, DQ2 =68, DQ3 =72
2016 23:41:55.899727 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2017 23:41:55.903028 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2018 23:41:55.906333 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
2019 23:41:55.906465
2020 23:41:55.906582
2021 23:41:55.916019 [DQSOSCAuto] RK1, (LSB)MR18= 0x2239, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
2022 23:41:55.916158 CH1 RK1: MR19=606, MR18=2239
2023 23:41:55.922709 CH1_RK1: MR19=0x606, MR18=0x2239, DQSOSC=395, MR23=63, INC=94, DEC=63
2024 23:41:55.926436 [RxdqsGatingPostProcess] freq 800
2025 23:41:55.932879 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2026 23:41:55.936485 Pre-setting of DQS Precalculation
2027 23:41:55.940081 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2028 23:41:55.946195 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2029 23:41:55.952840 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2030 23:41:55.956485
2031 23:41:55.956606
2032 23:41:55.956675 [Calibration Summary] 1600 Mbps
2033 23:41:55.959783 CH 0, Rank 0
2034 23:41:55.959866 SW Impedance : PASS
2035 23:41:55.962932 DUTY Scan : NO K
2036 23:41:55.966357 ZQ Calibration : PASS
2037 23:41:55.966476 Jitter Meter : NO K
2038 23:41:55.969392 CBT Training : PASS
2039 23:41:55.972731 Write leveling : PASS
2040 23:41:55.972812 RX DQS gating : PASS
2041 23:41:55.976069 RX DQ/DQS(RDDQC) : PASS
2042 23:41:55.979282 TX DQ/DQS : PASS
2043 23:41:55.979373 RX DATLAT : PASS
2044 23:41:55.982814 RX DQ/DQS(Engine): PASS
2045 23:41:55.986236 TX OE : NO K
2046 23:41:55.986350 All Pass.
2047 23:41:55.986454
2048 23:41:55.986545 CH 0, Rank 1
2049 23:41:55.989310 SW Impedance : PASS
2050 23:41:55.992878 DUTY Scan : NO K
2051 23:41:55.992963 ZQ Calibration : PASS
2052 23:41:55.996372 Jitter Meter : NO K
2053 23:41:55.999854 CBT Training : PASS
2054 23:41:55.999941 Write leveling : PASS
2055 23:41:56.002585 RX DQS gating : PASS
2056 23:41:56.002670 RX DQ/DQS(RDDQC) : PASS
2057 23:41:56.006182 TX DQ/DQS : PASS
2058 23:41:56.009702 RX DATLAT : PASS
2059 23:41:56.009811 RX DQ/DQS(Engine): PASS
2060 23:41:56.012850 TX OE : NO K
2061 23:41:56.012928 All Pass.
2062 23:41:56.012998
2063 23:41:56.016288 CH 1, Rank 0
2064 23:41:56.016396 SW Impedance : PASS
2065 23:41:56.019525 DUTY Scan : NO K
2066 23:41:56.022893 ZQ Calibration : PASS
2067 23:41:56.023005 Jitter Meter : NO K
2068 23:41:56.026040 CBT Training : PASS
2069 23:41:56.029387 Write leveling : PASS
2070 23:41:56.029475 RX DQS gating : PASS
2071 23:41:56.032772 RX DQ/DQS(RDDQC) : PASS
2072 23:41:56.036062 TX DQ/DQS : PASS
2073 23:41:56.036150 RX DATLAT : PASS
2074 23:41:56.039283 RX DQ/DQS(Engine): PASS
2075 23:41:56.039394 TX OE : NO K
2076 23:41:56.042571 All Pass.
2077 23:41:56.042685
2078 23:41:56.042779 CH 1, Rank 1
2079 23:41:56.046307 SW Impedance : PASS
2080 23:41:56.046411 DUTY Scan : NO K
2081 23:41:56.049542 ZQ Calibration : PASS
2082 23:41:56.052727 Jitter Meter : NO K
2083 23:41:56.052812 CBT Training : PASS
2084 23:41:56.056066 Write leveling : PASS
2085 23:41:56.059308 RX DQS gating : PASS
2086 23:41:56.059396 RX DQ/DQS(RDDQC) : PASS
2087 23:41:56.062691 TX DQ/DQS : PASS
2088 23:41:56.066417 RX DATLAT : PASS
2089 23:41:56.066506 RX DQ/DQS(Engine): PASS
2090 23:41:56.069598 TX OE : NO K
2091 23:41:56.069730 All Pass.
2092 23:41:56.069847
2093 23:41:56.072507 DramC Write-DBI off
2094 23:41:56.076054 PER_BANK_REFRESH: Hybrid Mode
2095 23:41:56.076177 TX_TRACKING: ON
2096 23:41:56.079317 [GetDramInforAfterCalByMRR] Vendor 6.
2097 23:41:56.082657 [GetDramInforAfterCalByMRR] Revision 606.
2098 23:41:56.085818 [GetDramInforAfterCalByMRR] Revision 2 0.
2099 23:41:56.089706 MR0 0x3b3b
2100 23:41:56.089849 MR8 0x5151
2101 23:41:56.092350 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 23:41:56.092484
2103 23:41:56.092611 MR0 0x3b3b
2104 23:41:56.095935 MR8 0x5151
2105 23:41:56.099217 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2106 23:41:56.099353
2107 23:41:56.109324 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2108 23:41:56.112576 [FAST_K] Save calibration result to emmc
2109 23:41:56.116086 [FAST_K] Save calibration result to emmc
2110 23:41:56.116221 dram_init: config_dvfs: 1
2111 23:41:56.122871 dramc_set_vcore_voltage set vcore to 662500
2112 23:41:56.123016 Read voltage for 1200, 2
2113 23:41:56.126336 Vio18 = 0
2114 23:41:56.126472 Vcore = 662500
2115 23:41:56.126595 Vdram = 0
2116 23:41:56.129439 Vddq = 0
2117 23:41:56.129551 Vmddr = 0
2118 23:41:56.132579 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2119 23:41:56.139214 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2120 23:41:56.142407 MEM_TYPE=3, freq_sel=15
2121 23:41:56.142500 sv_algorithm_assistance_LP4_1600
2122 23:41:56.149334 ============ PULL DRAM RESETB DOWN ============
2123 23:41:56.152431 ========== PULL DRAM RESETB DOWN end =========
2124 23:41:56.155715 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2125 23:41:56.159003 ===================================
2126 23:41:56.162260 LPDDR4 DRAM CONFIGURATION
2127 23:41:56.165994 ===================================
2128 23:41:56.169215 EX_ROW_EN[0] = 0x0
2129 23:41:56.169304 EX_ROW_EN[1] = 0x0
2130 23:41:56.172544 LP4Y_EN = 0x0
2131 23:41:56.172637 WORK_FSP = 0x0
2132 23:41:56.175672 WL = 0x4
2133 23:41:56.175748 RL = 0x4
2134 23:41:56.179034 BL = 0x2
2135 23:41:56.179120 RPST = 0x0
2136 23:41:56.182129 RD_PRE = 0x0
2137 23:41:56.182211 WR_PRE = 0x1
2138 23:41:56.185836 WR_PST = 0x0
2139 23:41:56.185911 DBI_WR = 0x0
2140 23:41:56.189086 DBI_RD = 0x0
2141 23:41:56.189178 OTF = 0x1
2142 23:41:56.192322 ===================================
2143 23:41:56.195650 ===================================
2144 23:41:56.199186 ANA top config
2145 23:41:56.202439 ===================================
2146 23:41:56.205682 DLL_ASYNC_EN = 0
2147 23:41:56.205771 ALL_SLAVE_EN = 0
2148 23:41:56.208897 NEW_RANK_MODE = 1
2149 23:41:56.212536 DLL_IDLE_MODE = 1
2150 23:41:56.215772 LP45_APHY_COMB_EN = 1
2151 23:41:56.219195 TX_ODT_DIS = 1
2152 23:41:56.219295 NEW_8X_MODE = 1
2153 23:41:56.222401 ===================================
2154 23:41:56.225459 ===================================
2155 23:41:56.229062 data_rate = 2400
2156 23:41:56.232453 CKR = 1
2157 23:41:56.235789 DQ_P2S_RATIO = 8
2158 23:41:56.238845 ===================================
2159 23:41:56.242397 CA_P2S_RATIO = 8
2160 23:41:56.242480 DQ_CA_OPEN = 0
2161 23:41:56.245805 DQ_SEMI_OPEN = 0
2162 23:41:56.249585 CA_SEMI_OPEN = 0
2163 23:41:56.252309 CA_FULL_RATE = 0
2164 23:41:56.255690 DQ_CKDIV4_EN = 0
2165 23:41:56.259217 CA_CKDIV4_EN = 0
2166 23:41:56.259309 CA_PREDIV_EN = 0
2167 23:41:56.262410 PH8_DLY = 17
2168 23:41:56.265689 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2169 23:41:56.268949 DQ_AAMCK_DIV = 4
2170 23:41:56.272284 CA_AAMCK_DIV = 4
2171 23:41:56.276075 CA_ADMCK_DIV = 4
2172 23:41:56.276165 DQ_TRACK_CA_EN = 0
2173 23:41:56.279530 CA_PICK = 1200
2174 23:41:56.282610 CA_MCKIO = 1200
2175 23:41:56.285791 MCKIO_SEMI = 0
2176 23:41:56.289177 PLL_FREQ = 2366
2177 23:41:56.292285 DQ_UI_PI_RATIO = 32
2178 23:41:56.295569 CA_UI_PI_RATIO = 0
2179 23:41:56.298929 ===================================
2180 23:41:56.302632 ===================================
2181 23:41:56.302786 memory_type:LPDDR4
2182 23:41:56.305826 GP_NUM : 10
2183 23:41:56.309310 SRAM_EN : 1
2184 23:41:56.309408 MD32_EN : 0
2185 23:41:56.312528 ===================================
2186 23:41:56.316008 [ANA_INIT] >>>>>>>>>>>>>>
2187 23:41:56.319219 <<<<<< [CONFIGURE PHASE]: ANA_TX
2188 23:41:56.322582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2189 23:41:56.325958 ===================================
2190 23:41:56.329268 data_rate = 2400,PCW = 0X5b00
2191 23:41:56.332519 ===================================
2192 23:41:56.335524 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2193 23:41:56.339051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 23:41:56.345466 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2195 23:41:56.349383 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2196 23:41:56.352646 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2197 23:41:56.355544 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2198 23:41:56.359171 [ANA_INIT] flow start
2199 23:41:56.362405 [ANA_INIT] PLL >>>>>>>>
2200 23:41:56.362524 [ANA_INIT] PLL <<<<<<<<
2201 23:41:56.365928 [ANA_INIT] MIDPI >>>>>>>>
2202 23:41:56.368785 [ANA_INIT] MIDPI <<<<<<<<
2203 23:41:56.368877 [ANA_INIT] DLL >>>>>>>>
2204 23:41:56.372936 [ANA_INIT] DLL <<<<<<<<
2205 23:41:56.375376 [ANA_INIT] flow end
2206 23:41:56.379050 ============ LP4 DIFF to SE enter ============
2207 23:41:56.382328 ============ LP4 DIFF to SE exit ============
2208 23:41:56.385463 [ANA_INIT] <<<<<<<<<<<<<
2209 23:41:56.389444 [Flow] Enable top DCM control >>>>>
2210 23:41:56.392328 [Flow] Enable top DCM control <<<<<
2211 23:41:56.395845 Enable DLL master slave shuffle
2212 23:41:56.398958 ==============================================================
2213 23:41:56.402150 Gating Mode config
2214 23:41:56.409279 ==============================================================
2215 23:41:56.409431 Config description:
2216 23:41:56.418889 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2217 23:41:56.425668 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2218 23:41:56.429424 SELPH_MODE 0: By rank 1: By Phase
2219 23:41:56.436120 ==============================================================
2220 23:41:56.439346 GAT_TRACK_EN = 1
2221 23:41:56.442332 RX_GATING_MODE = 2
2222 23:41:56.446011 RX_GATING_TRACK_MODE = 2
2223 23:41:56.449146 SELPH_MODE = 1
2224 23:41:56.452380 PICG_EARLY_EN = 1
2225 23:41:56.452526 VALID_LAT_VALUE = 1
2226 23:41:56.459150 ==============================================================
2227 23:41:56.462269 Enter into Gating configuration >>>>
2228 23:41:56.465505 Exit from Gating configuration <<<<
2229 23:41:56.469239 Enter into DVFS_PRE_config >>>>>
2230 23:41:56.478945 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2231 23:41:56.482226 Exit from DVFS_PRE_config <<<<<
2232 23:41:56.486131 Enter into PICG configuration >>>>
2233 23:41:56.488990 Exit from PICG configuration <<<<
2234 23:41:56.492270 [RX_INPUT] configuration >>>>>
2235 23:41:56.495395 [RX_INPUT] configuration <<<<<
2236 23:41:56.498651 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2237 23:41:56.505395 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2238 23:41:56.512007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 23:41:56.518964 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 23:41:56.525539 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 23:41:56.532168 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 23:41:56.535540 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2243 23:41:56.538798 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2244 23:41:56.541998 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2245 23:41:56.545798 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2246 23:41:56.551967 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2247 23:41:56.555681 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2248 23:41:56.558880 ===================================
2249 23:41:56.562281 LPDDR4 DRAM CONFIGURATION
2250 23:41:56.565428 ===================================
2251 23:41:56.565517 EX_ROW_EN[0] = 0x0
2252 23:41:56.568515 EX_ROW_EN[1] = 0x0
2253 23:41:56.568623 LP4Y_EN = 0x0
2254 23:41:56.572061 WORK_FSP = 0x0
2255 23:41:56.572146 WL = 0x4
2256 23:41:56.575390 RL = 0x4
2257 23:41:56.575473 BL = 0x2
2258 23:41:56.578644 RPST = 0x0
2259 23:41:56.582318 RD_PRE = 0x0
2260 23:41:56.582410 WR_PRE = 0x1
2261 23:41:56.585598 WR_PST = 0x0
2262 23:41:56.585676 DBI_WR = 0x0
2263 23:41:56.589215 DBI_RD = 0x0
2264 23:41:56.589290 OTF = 0x1
2265 23:41:56.592033 ===================================
2266 23:41:56.595534 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2267 23:41:56.598703 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2268 23:41:56.605408 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2269 23:41:56.609225 ===================================
2270 23:41:56.612085 LPDDR4 DRAM CONFIGURATION
2271 23:41:56.612166 ===================================
2272 23:41:56.615706 EX_ROW_EN[0] = 0x10
2273 23:41:56.619022 EX_ROW_EN[1] = 0x0
2274 23:41:56.619104 LP4Y_EN = 0x0
2275 23:41:56.622253 WORK_FSP = 0x0
2276 23:41:56.622328 WL = 0x4
2277 23:41:56.625552 RL = 0x4
2278 23:41:56.625641 BL = 0x2
2279 23:41:56.628926 RPST = 0x0
2280 23:41:56.629030 RD_PRE = 0x0
2281 23:41:56.632052 WR_PRE = 0x1
2282 23:41:56.632145 WR_PST = 0x0
2283 23:41:56.635305 DBI_WR = 0x0
2284 23:41:56.635417 DBI_RD = 0x0
2285 23:41:56.638953 OTF = 0x1
2286 23:41:56.641947 ===================================
2287 23:41:56.648752 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2288 23:41:56.648844 ==
2289 23:41:56.652414 Dram Type= 6, Freq= 0, CH_0, rank 0
2290 23:41:56.655671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2291 23:41:56.655761 ==
2292 23:41:56.658688 [Duty_Offset_Calibration]
2293 23:41:56.658804 B0:2 B1:0 CA:3
2294 23:41:56.658909
2295 23:41:56.661940 [DutyScan_Calibration_Flow] k_type=0
2296 23:41:56.672865
2297 23:41:56.672969 ==CLK 0==
2298 23:41:56.675962 Final CLK duty delay cell = 0
2299 23:41:56.679444 [0] MAX Duty = 5031%(X100), DQS PI = 12
2300 23:41:56.682885 [0] MIN Duty = 4875%(X100), DQS PI = 58
2301 23:41:56.682963 [0] AVG Duty = 4953%(X100)
2302 23:41:56.685726
2303 23:41:56.685805 CH0 CLK Duty spec in!! Max-Min= 156%
2304 23:41:56.692433 [DutyScan_Calibration_Flow] ====Done====
2305 23:41:56.692518
2306 23:41:56.695954 [DutyScan_Calibration_Flow] k_type=1
2307 23:41:56.711472
2308 23:41:56.711580 ==DQS 0 ==
2309 23:41:56.714328 Final DQS duty delay cell = 0
2310 23:41:56.717661 [0] MAX Duty = 5062%(X100), DQS PI = 28
2311 23:41:56.721025 [0] MIN Duty = 4907%(X100), DQS PI = 44
2312 23:41:56.724208 [0] AVG Duty = 4984%(X100)
2313 23:41:56.724288
2314 23:41:56.724353 ==DQS 1 ==
2315 23:41:56.727523 Final DQS duty delay cell = -4
2316 23:41:56.730898 [-4] MAX Duty = 5000%(X100), DQS PI = 36
2317 23:41:56.734135 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2318 23:41:56.737894 [-4] AVG Duty = 4937%(X100)
2319 23:41:56.737976
2320 23:41:56.741252 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2321 23:41:56.741325
2322 23:41:56.744213 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2323 23:41:56.747871 [DutyScan_Calibration_Flow] ====Done====
2324 23:41:56.747949
2325 23:41:56.751007 [DutyScan_Calibration_Flow] k_type=3
2326 23:41:56.768687
2327 23:41:56.768819 ==DQM 0 ==
2328 23:41:56.772042 Final DQM duty delay cell = 0
2329 23:41:56.775215 [0] MAX Duty = 5124%(X100), DQS PI = 28
2330 23:41:56.778837 [0] MIN Duty = 4876%(X100), DQS PI = 48
2331 23:41:56.782082 [0] AVG Duty = 5000%(X100)
2332 23:41:56.782167
2333 23:41:56.782232 ==DQM 1 ==
2334 23:41:56.785450 Final DQM duty delay cell = 4
2335 23:41:56.788741 [4] MAX Duty = 5124%(X100), DQS PI = 50
2336 23:41:56.791911 [4] MIN Duty = 5000%(X100), DQS PI = 14
2337 23:41:56.795182 [4] AVG Duty = 5062%(X100)
2338 23:41:56.795277
2339 23:41:56.798279 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2340 23:41:56.798356
2341 23:41:56.801915 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2342 23:41:56.805612 [DutyScan_Calibration_Flow] ====Done====
2343 23:41:56.805723
2344 23:41:56.808787 [DutyScan_Calibration_Flow] k_type=2
2345 23:41:56.823481
2346 23:41:56.823611 ==DQ 0 ==
2347 23:41:56.827242 Final DQ duty delay cell = -4
2348 23:41:56.830306 [-4] MAX Duty = 5031%(X100), DQS PI = 18
2349 23:41:56.833432 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2350 23:41:56.837139 [-4] AVG Duty = 4969%(X100)
2351 23:41:56.837222
2352 23:41:56.837307 ==DQ 1 ==
2353 23:41:56.840047 Final DQ duty delay cell = -4
2354 23:41:56.844077 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2355 23:41:56.846751 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2356 23:41:56.850355 [-4] AVG Duty = 4938%(X100)
2357 23:41:56.850437
2358 23:41:56.853704 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2359 23:41:56.853789
2360 23:41:56.856997 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2361 23:41:56.860157 [DutyScan_Calibration_Flow] ====Done====
2362 23:41:56.860237 ==
2363 23:41:56.863564 Dram Type= 6, Freq= 0, CH_1, rank 0
2364 23:41:56.866980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2365 23:41:56.867086 ==
2366 23:41:56.870016 [Duty_Offset_Calibration]
2367 23:41:56.870097 B0:1 B1:-2 CA:0
2368 23:41:56.870185
2369 23:41:56.873258 [DutyScan_Calibration_Flow] k_type=0
2370 23:41:56.884030
2371 23:41:56.884142 ==CLK 0==
2372 23:41:56.887281 Final CLK duty delay cell = 0
2373 23:41:56.891185 [0] MAX Duty = 5031%(X100), DQS PI = 18
2374 23:41:56.894359 [0] MIN Duty = 4876%(X100), DQS PI = 2
2375 23:41:56.894441 [0] AVG Duty = 4953%(X100)
2376 23:41:56.894526
2377 23:41:56.897709 CH1 CLK Duty spec in!! Max-Min= 155%
2378 23:41:56.904047 [DutyScan_Calibration_Flow] ====Done====
2379 23:41:56.904146
2380 23:41:56.907610 [DutyScan_Calibration_Flow] k_type=1
2381 23:41:56.922823
2382 23:41:56.922946 ==DQS 0 ==
2383 23:41:56.926145 Final DQS duty delay cell = -4
2384 23:41:56.929455 [-4] MAX Duty = 5000%(X100), DQS PI = 24
2385 23:41:56.932817 [-4] MIN Duty = 4876%(X100), DQS PI = 52
2386 23:41:56.935914 [-4] AVG Duty = 4938%(X100)
2387 23:41:56.935998
2388 23:41:56.936064 ==DQS 1 ==
2389 23:41:56.939091 Final DQS duty delay cell = 0
2390 23:41:56.942781 [0] MAX Duty = 5093%(X100), DQS PI = 0
2391 23:41:56.945986 [0] MIN Duty = 4875%(X100), DQS PI = 26
2392 23:41:56.949053 [0] AVG Duty = 4984%(X100)
2393 23:41:56.949146
2394 23:41:56.952398 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2395 23:41:56.952510
2396 23:41:56.955683 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2397 23:41:56.959186 [DutyScan_Calibration_Flow] ====Done====
2398 23:41:56.959305
2399 23:41:56.962436 [DutyScan_Calibration_Flow] k_type=3
2400 23:41:56.979452
2401 23:41:56.979596 ==DQM 0 ==
2402 23:41:56.982561 Final DQM duty delay cell = 0
2403 23:41:56.985985 [0] MAX Duty = 5000%(X100), DQS PI = 20
2404 23:41:56.989775 [0] MIN Duty = 4844%(X100), DQS PI = 54
2405 23:41:56.992674 [0] AVG Duty = 4922%(X100)
2406 23:41:56.992766
2407 23:41:56.992835 ==DQM 1 ==
2408 23:41:56.995999 Final DQM duty delay cell = 0
2409 23:41:56.999149 [0] MAX Duty = 5031%(X100), DQS PI = 36
2410 23:41:57.002379 [0] MIN Duty = 4907%(X100), DQS PI = 4
2411 23:41:57.002486 [0] AVG Duty = 4969%(X100)
2412 23:41:57.006170
2413 23:41:57.009276 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2414 23:41:57.009361
2415 23:41:57.012754 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2416 23:41:57.015915 [DutyScan_Calibration_Flow] ====Done====
2417 23:41:57.015995
2418 23:41:57.019228 [DutyScan_Calibration_Flow] k_type=2
2419 23:41:57.035672
2420 23:41:57.035868 ==DQ 0 ==
2421 23:41:57.038938 Final DQ duty delay cell = 0
2422 23:41:57.042642 [0] MAX Duty = 5093%(X100), DQS PI = 20
2423 23:41:57.045975 [0] MIN Duty = 4938%(X100), DQS PI = 54
2424 23:41:57.046074 [0] AVG Duty = 5015%(X100)
2425 23:41:57.046140
2426 23:41:57.049197 ==DQ 1 ==
2427 23:41:57.052423 Final DQ duty delay cell = 0
2428 23:41:57.055713 [0] MAX Duty = 5125%(X100), DQS PI = 36
2429 23:41:57.059051 [0] MIN Duty = 4938%(X100), DQS PI = 26
2430 23:41:57.059139 [0] AVG Duty = 5031%(X100)
2431 23:41:57.059208
2432 23:41:57.062258 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2433 23:41:57.065737
2434 23:41:57.069287 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2435 23:41:57.072211 [DutyScan_Calibration_Flow] ====Done====
2436 23:41:57.075640 nWR fixed to 30
2437 23:41:57.075730 [ModeRegInit_LP4] CH0 RK0
2438 23:41:57.079061 [ModeRegInit_LP4] CH0 RK1
2439 23:41:57.082353 [ModeRegInit_LP4] CH1 RK0
2440 23:41:57.082447 [ModeRegInit_LP4] CH1 RK1
2441 23:41:57.085683 match AC timing 7
2442 23:41:57.089263 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2443 23:41:57.092466 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2444 23:41:57.099060 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2445 23:41:57.102558 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2446 23:41:57.108983 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2447 23:41:57.109093 ==
2448 23:41:57.112105 Dram Type= 6, Freq= 0, CH_0, rank 0
2449 23:41:57.115741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2450 23:41:57.115832 ==
2451 23:41:57.122501 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2452 23:41:57.125720 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2453 23:41:57.136389 [CA 0] Center 40 (10~71) winsize 62
2454 23:41:57.139187 [CA 1] Center 39 (9~70) winsize 62
2455 23:41:57.142525 [CA 2] Center 36 (6~66) winsize 61
2456 23:41:57.145669 [CA 3] Center 35 (5~66) winsize 62
2457 23:41:57.148993 [CA 4] Center 34 (4~65) winsize 62
2458 23:41:57.152353 [CA 5] Center 33 (3~63) winsize 61
2459 23:41:57.152464
2460 23:41:57.156034 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2461 23:41:57.156109
2462 23:41:57.159325 [CATrainingPosCal] consider 1 rank data
2463 23:41:57.162525 u2DelayCellTimex100 = 270/100 ps
2464 23:41:57.165967 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2465 23:41:57.172351 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2466 23:41:57.175616 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2467 23:41:57.179224 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2468 23:41:57.186348 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2469 23:41:57.186506 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2470 23:41:57.186627
2471 23:41:57.188955 CA PerBit enable=1, Macro0, CA PI delay=33
2472 23:41:57.189082
2473 23:41:57.192251 [CBTSetCACLKResult] CA Dly = 33
2474 23:41:57.192359 CS Dly: 7 (0~38)
2475 23:41:57.195817 ==
2476 23:41:57.199040 Dram Type= 6, Freq= 0, CH_0, rank 1
2477 23:41:57.202686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2478 23:41:57.202777 ==
2479 23:41:57.205699 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2480 23:41:57.212347 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2481 23:41:57.221800 [CA 0] Center 40 (10~71) winsize 62
2482 23:41:57.225034 [CA 1] Center 40 (10~70) winsize 61
2483 23:41:57.228725 [CA 2] Center 35 (5~66) winsize 62
2484 23:41:57.231659 [CA 3] Center 35 (5~66) winsize 62
2485 23:41:57.234955 [CA 4] Center 34 (4~65) winsize 62
2486 23:41:57.238819 [CA 5] Center 33 (3~63) winsize 61
2487 23:41:57.238922
2488 23:41:57.242196 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2489 23:41:57.242284
2490 23:41:57.245363 [CATrainingPosCal] consider 2 rank data
2491 23:41:57.248756 u2DelayCellTimex100 = 270/100 ps
2492 23:41:57.251977 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2493 23:41:57.258625 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2494 23:41:57.261805 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2495 23:41:57.265178 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2496 23:41:57.268434 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2497 23:41:57.271807 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2498 23:41:57.271939
2499 23:41:57.275686 CA PerBit enable=1, Macro0, CA PI delay=33
2500 23:41:57.275821
2501 23:41:57.278772 [CBTSetCACLKResult] CA Dly = 33
2502 23:41:57.278904 CS Dly: 7 (0~39)
2503 23:41:57.281967
2504 23:41:57.285303 ----->DramcWriteLeveling(PI) begin...
2505 23:41:57.285436 ==
2506 23:41:57.288458 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 23:41:57.291890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 23:41:57.292004 ==
2509 23:41:57.295013 Write leveling (Byte 0): 32 => 32
2510 23:41:57.298270 Write leveling (Byte 1): 29 => 29
2511 23:41:57.301951 DramcWriteLeveling(PI) end<-----
2512 23:41:57.302038
2513 23:41:57.302109 ==
2514 23:41:57.304943 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 23:41:57.308255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 23:41:57.308325 ==
2517 23:41:57.311582 [Gating] SW mode calibration
2518 23:41:57.318681 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2519 23:41:57.325049 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2520 23:41:57.328485 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 23:41:57.332048 0 15 4 | B1->B0 | 2928 3232 | 1 1 | (0 0) (1 1)
2522 23:41:57.338403 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 23:41:57.342051 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 23:41:57.345136 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 23:41:57.351791 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 23:41:57.354989 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 23:41:57.358206 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2528 23:41:57.361884 1 0 0 | B1->B0 | 3131 2525 | 1 0 | (1 1) (1 0)
2529 23:41:57.368299 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2530 23:41:57.371637 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 23:41:57.374866 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 23:41:57.381769 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 23:41:57.385149 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 23:41:57.388289 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 23:41:57.394913 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 23:41:57.398527 1 1 0 | B1->B0 | 2b2b 3737 | 0 0 | (0 0) (1 1)
2537 23:41:57.402156 1 1 4 | B1->B0 | 4040 4646 | 1 0 | (0 0) (0 0)
2538 23:41:57.408267 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 23:41:57.411518 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 23:41:57.415096 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 23:41:57.421481 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 23:41:57.425571 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 23:41:57.428551 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2544 23:41:57.434857 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2545 23:41:57.438110 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 23:41:57.441806 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 23:41:57.448066 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 23:41:57.451520 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 23:41:57.454918 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 23:41:57.458299 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 23:41:57.464787 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 23:41:57.468053 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 23:41:57.471590 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 23:41:57.478284 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 23:41:57.481656 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 23:41:57.485016 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 23:41:57.491639 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 23:41:57.494895 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 23:41:57.498312 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2560 23:41:57.504928 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2561 23:41:57.508215 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2562 23:41:57.511486 Total UI for P1: 0, mck2ui 16
2563 23:41:57.515261 best dqsien dly found for B0: ( 1, 3, 30)
2564 23:41:57.518249 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 23:41:57.521781 Total UI for P1: 0, mck2ui 16
2566 23:41:57.525152 best dqsien dly found for B1: ( 1, 4, 4)
2567 23:41:57.528393 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2568 23:41:57.531779 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2569 23:41:57.531864
2570 23:41:57.534938 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2571 23:41:57.541882 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2572 23:41:57.542040 [Gating] SW calibration Done
2573 23:41:57.542159 ==
2574 23:41:57.545131 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 23:41:57.551557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 23:41:57.551737 ==
2577 23:41:57.551859 RX Vref Scan: 0
2578 23:41:57.551977
2579 23:41:57.555048 RX Vref 0 -> 0, step: 1
2580 23:41:57.555192
2581 23:41:57.558480 RX Delay -40 -> 252, step: 8
2582 23:41:57.561860 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2583 23:41:57.565094 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2584 23:41:57.568297 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2585 23:41:57.575050 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2586 23:41:57.578351 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2587 23:41:57.581455 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2588 23:41:57.584907 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2589 23:41:57.588012 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2590 23:41:57.591540 iDelay=200, Bit 8, Center 95 (16 ~ 175) 160
2591 23:41:57.598171 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2592 23:41:57.601522 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2593 23:41:57.605225 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2594 23:41:57.608258 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2595 23:41:57.611881 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2596 23:41:57.618553 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2597 23:41:57.621775 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2598 23:41:57.621922 ==
2599 23:41:57.624994 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 23:41:57.628304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 23:41:57.628440 ==
2602 23:41:57.631533 DQS Delay:
2603 23:41:57.631674 DQS0 = 0, DQS1 = 0
2604 23:41:57.631788 DQM Delay:
2605 23:41:57.635008 DQM0 = 113, DQM1 = 103
2606 23:41:57.635102 DQ Delay:
2607 23:41:57.638326 DQ0 =115, DQ1 =111, DQ2 =115, DQ3 =107
2608 23:41:57.641324 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2609 23:41:57.644671 DQ8 =95, DQ9 =87, DQ10 =103, DQ11 =99
2610 23:41:57.651181 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2611 23:41:57.651277
2612 23:41:57.651347
2613 23:41:57.651409 ==
2614 23:41:57.654753 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 23:41:57.658361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 23:41:57.658502 ==
2617 23:41:57.658621
2618 23:41:57.658732
2619 23:41:57.661498 TX Vref Scan disable
2620 23:41:57.661626 == TX Byte 0 ==
2621 23:41:57.668188 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2622 23:41:57.671647 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2623 23:41:57.671796 == TX Byte 1 ==
2624 23:41:57.677870 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2625 23:41:57.681584 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2626 23:41:57.681726 ==
2627 23:41:57.684776 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 23:41:57.688009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 23:41:57.688121 ==
2630 23:41:57.700672 TX Vref=22, minBit 12, minWin=25, winSum=421
2631 23:41:57.703865 TX Vref=24, minBit 0, minWin=26, winSum=424
2632 23:41:57.707834 TX Vref=26, minBit 10, minWin=26, winSum=433
2633 23:41:57.710788 TX Vref=28, minBit 1, minWin=27, winSum=437
2634 23:41:57.713926 TX Vref=30, minBit 8, minWin=26, winSum=435
2635 23:41:57.721070 TX Vref=32, minBit 10, minWin=25, winSum=432
2636 23:41:57.724239 [TxChooseVref] Worse bit 1, Min win 27, Win sum 437, Final Vref 28
2637 23:41:57.724339
2638 23:41:57.727566 Final TX Range 1 Vref 28
2639 23:41:57.727654
2640 23:41:57.727721 ==
2641 23:41:57.730872 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 23:41:57.733834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 23:41:57.737216 ==
2644 23:41:57.737312
2645 23:41:57.737379
2646 23:41:57.737442 TX Vref Scan disable
2647 23:41:57.740673 == TX Byte 0 ==
2648 23:41:57.743890 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2649 23:41:57.747353 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2650 23:41:57.751127 == TX Byte 1 ==
2651 23:41:57.754401 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2652 23:41:57.757649 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2653 23:41:57.761127
2654 23:41:57.761220 [DATLAT]
2655 23:41:57.761288 Freq=1200, CH0 RK0
2656 23:41:57.761352
2657 23:41:57.764234 DATLAT Default: 0xd
2658 23:41:57.764316 0, 0xFFFF, sum = 0
2659 23:41:57.767278 1, 0xFFFF, sum = 0
2660 23:41:57.767397 2, 0xFFFF, sum = 0
2661 23:41:57.770648 3, 0xFFFF, sum = 0
2662 23:41:57.770737 4, 0xFFFF, sum = 0
2663 23:41:57.774264 5, 0xFFFF, sum = 0
2664 23:41:57.777619 6, 0xFFFF, sum = 0
2665 23:41:57.777712 7, 0xFFFF, sum = 0
2666 23:41:57.780767 8, 0xFFFF, sum = 0
2667 23:41:57.780859 9, 0xFFFF, sum = 0
2668 23:41:57.784184 10, 0xFFFF, sum = 0
2669 23:41:57.784276 11, 0xFFFF, sum = 0
2670 23:41:57.787347 12, 0x0, sum = 1
2671 23:41:57.787462 13, 0x0, sum = 2
2672 23:41:57.790731 14, 0x0, sum = 3
2673 23:41:57.790823 15, 0x0, sum = 4
2674 23:41:57.790892 best_step = 13
2675 23:41:57.790954
2676 23:41:57.794568 ==
2677 23:41:57.797664 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 23:41:57.800781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 23:41:57.800871 ==
2680 23:41:57.800941 RX Vref Scan: 1
2681 23:41:57.801003
2682 23:41:57.804042 Set Vref Range= 32 -> 127
2683 23:41:57.804128
2684 23:41:57.807373 RX Vref 32 -> 127, step: 1
2685 23:41:57.807461
2686 23:41:57.811036 RX Delay -37 -> 252, step: 4
2687 23:41:57.811124
2688 23:41:57.814100 Set Vref, RX VrefLevel [Byte0]: 32
2689 23:41:57.817633 [Byte1]: 32
2690 23:41:57.817724
2691 23:41:57.820708 Set Vref, RX VrefLevel [Byte0]: 33
2692 23:41:57.824075 [Byte1]: 33
2693 23:41:57.827373
2694 23:41:57.827466 Set Vref, RX VrefLevel [Byte0]: 34
2695 23:41:57.830733 [Byte1]: 34
2696 23:41:57.835212
2697 23:41:57.835303 Set Vref, RX VrefLevel [Byte0]: 35
2698 23:41:57.838796 [Byte1]: 35
2699 23:41:57.843131
2700 23:41:57.843253 Set Vref, RX VrefLevel [Byte0]: 36
2701 23:41:57.846673 [Byte1]: 36
2702 23:41:57.851358
2703 23:41:57.851478 Set Vref, RX VrefLevel [Byte0]: 37
2704 23:41:57.854834 [Byte1]: 37
2705 23:41:57.859111
2706 23:41:57.859228 Set Vref, RX VrefLevel [Byte0]: 38
2707 23:41:57.862944 [Byte1]: 38
2708 23:41:57.867413
2709 23:41:57.867550 Set Vref, RX VrefLevel [Byte0]: 39
2710 23:41:57.870599 [Byte1]: 39
2711 23:41:57.875587
2712 23:41:57.878823 Set Vref, RX VrefLevel [Byte0]: 40
2713 23:41:57.881982 [Byte1]: 40
2714 23:41:57.882116
2715 23:41:57.884993 Set Vref, RX VrefLevel [Byte0]: 41
2716 23:41:57.888481 [Byte1]: 41
2717 23:41:57.888618
2718 23:41:57.891994 Set Vref, RX VrefLevel [Byte0]: 42
2719 23:41:57.895329 [Byte1]: 42
2720 23:41:57.899607
2721 23:41:57.899742 Set Vref, RX VrefLevel [Byte0]: 43
2722 23:41:57.902954 [Byte1]: 43
2723 23:41:57.907748
2724 23:41:57.907880 Set Vref, RX VrefLevel [Byte0]: 44
2725 23:41:57.910658 [Byte1]: 44
2726 23:41:57.915215
2727 23:41:57.915358 Set Vref, RX VrefLevel [Byte0]: 45
2728 23:41:57.918571 [Byte1]: 45
2729 23:41:57.923369
2730 23:41:57.923505 Set Vref, RX VrefLevel [Byte0]: 46
2731 23:41:57.927129 [Byte1]: 46
2732 23:41:57.931257
2733 23:41:57.931388 Set Vref, RX VrefLevel [Byte0]: 47
2734 23:41:57.934829 [Byte1]: 47
2735 23:41:57.939790
2736 23:41:57.939933 Set Vref, RX VrefLevel [Byte0]: 48
2737 23:41:57.942609 [Byte1]: 48
2738 23:41:57.947602
2739 23:41:57.947727 Set Vref, RX VrefLevel [Byte0]: 49
2740 23:41:57.950928 [Byte1]: 49
2741 23:41:57.955109
2742 23:41:57.955218 Set Vref, RX VrefLevel [Byte0]: 50
2743 23:41:57.958612 [Byte1]: 50
2744 23:41:57.963254
2745 23:41:57.963397 Set Vref, RX VrefLevel [Byte0]: 51
2746 23:41:57.966818 [Byte1]: 51
2747 23:41:57.971115
2748 23:41:57.971242 Set Vref, RX VrefLevel [Byte0]: 52
2749 23:41:57.974510 [Byte1]: 52
2750 23:41:57.979373
2751 23:41:57.979487 Set Vref, RX VrefLevel [Byte0]: 53
2752 23:41:57.982632 [Byte1]: 53
2753 23:41:57.987537
2754 23:41:57.987634 Set Vref, RX VrefLevel [Byte0]: 54
2755 23:41:57.990607 [Byte1]: 54
2756 23:41:57.995130
2757 23:41:57.995224 Set Vref, RX VrefLevel [Byte0]: 55
2758 23:41:57.998561 [Byte1]: 55
2759 23:41:58.003534
2760 23:41:58.003654 Set Vref, RX VrefLevel [Byte0]: 56
2761 23:41:58.006812 [Byte1]: 56
2762 23:41:58.011139
2763 23:41:58.011255 Set Vref, RX VrefLevel [Byte0]: 57
2764 23:41:58.014843 [Byte1]: 57
2765 23:41:58.019155
2766 23:41:58.019262 Set Vref, RX VrefLevel [Byte0]: 58
2767 23:41:58.022778 [Byte1]: 58
2768 23:41:58.027596
2769 23:41:58.027695 Set Vref, RX VrefLevel [Byte0]: 59
2770 23:41:58.030900 [Byte1]: 59
2771 23:41:58.035399
2772 23:41:58.035494 Set Vref, RX VrefLevel [Byte0]: 60
2773 23:41:58.038649 [Byte1]: 60
2774 23:41:58.043343
2775 23:41:58.043466 Set Vref, RX VrefLevel [Byte0]: 61
2776 23:41:58.046654 [Byte1]: 61
2777 23:41:58.051295
2778 23:41:58.051385 Set Vref, RX VrefLevel [Byte0]: 62
2779 23:41:58.054826 [Byte1]: 62
2780 23:41:58.059252
2781 23:41:58.059342 Set Vref, RX VrefLevel [Byte0]: 63
2782 23:41:58.063028 [Byte1]: 63
2783 23:41:58.067122
2784 23:41:58.067208 Set Vref, RX VrefLevel [Byte0]: 64
2785 23:41:58.070656 [Byte1]: 64
2786 23:41:58.075253
2787 23:41:58.075346 Set Vref, RX VrefLevel [Byte0]: 65
2788 23:41:58.078736 [Byte1]: 65
2789 23:41:58.083259
2790 23:41:58.083349 Set Vref, RX VrefLevel [Byte0]: 66
2791 23:41:58.086942 [Byte1]: 66
2792 23:41:58.091269
2793 23:41:58.091383 Set Vref, RX VrefLevel [Byte0]: 67
2794 23:41:58.095003 [Byte1]: 67
2795 23:41:58.099339
2796 23:41:58.099458 Set Vref, RX VrefLevel [Byte0]: 68
2797 23:41:58.102651 [Byte1]: 68
2798 23:41:58.107096
2799 23:41:58.107200 Set Vref, RX VrefLevel [Byte0]: 69
2800 23:41:58.110570 [Byte1]: 69
2801 23:41:58.115363
2802 23:41:58.115479 Set Vref, RX VrefLevel [Byte0]: 70
2803 23:41:58.118630 [Byte1]: 70
2804 23:41:58.123495
2805 23:41:58.123618 Set Vref, RX VrefLevel [Byte0]: 71
2806 23:41:58.126556 [Byte1]: 71
2807 23:41:58.131268
2808 23:41:58.131355 Set Vref, RX VrefLevel [Byte0]: 72
2809 23:41:58.134657 [Byte1]: 72
2810 23:41:58.139470
2811 23:41:58.139555 Set Vref, RX VrefLevel [Byte0]: 73
2812 23:41:58.142826 [Byte1]: 73
2813 23:41:58.147653
2814 23:41:58.147764 Set Vref, RX VrefLevel [Byte0]: 74
2815 23:41:58.150741 [Byte1]: 74
2816 23:41:58.155159
2817 23:41:58.155266 Set Vref, RX VrefLevel [Byte0]: 75
2818 23:41:58.158461 [Byte1]: 75
2819 23:41:58.163566
2820 23:41:58.163652 Final RX Vref Byte 0 = 60 to rank0
2821 23:41:58.166806 Final RX Vref Byte 1 = 51 to rank0
2822 23:41:58.170168 Final RX Vref Byte 0 = 60 to rank1
2823 23:41:58.173692 Final RX Vref Byte 1 = 51 to rank1==
2824 23:41:58.176387 Dram Type= 6, Freq= 0, CH_0, rank 0
2825 23:41:58.183140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2826 23:41:58.183270 ==
2827 23:41:58.183370 DQS Delay:
2828 23:41:58.183465 DQS0 = 0, DQS1 = 0
2829 23:41:58.186556 DQM Delay:
2830 23:41:58.186662 DQM0 = 112, DQM1 = 101
2831 23:41:58.190563 DQ Delay:
2832 23:41:58.193476 DQ0 =112, DQ1 =112, DQ2 =110, DQ3 =108
2833 23:41:58.196861 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2834 23:41:58.200075 DQ8 =92, DQ9 =84, DQ10 =104, DQ11 =94
2835 23:41:58.203275 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2836 23:41:58.203391
2837 23:41:58.203489
2838 23:41:58.209714 [DQSOSCAuto] RK0, (LSB)MR18= 0x101, (MSB)MR19= 0x404, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
2839 23:41:58.213611 CH0 RK0: MR19=404, MR18=101
2840 23:41:58.219810 CH0_RK0: MR19=0x404, MR18=0x101, DQSOSC=409, MR23=63, INC=39, DEC=26
2841 23:41:58.219927
2842 23:41:58.223091 ----->DramcWriteLeveling(PI) begin...
2843 23:41:58.223182 ==
2844 23:41:58.226304 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 23:41:58.229745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2846 23:41:58.229833 ==
2847 23:41:58.233013 Write leveling (Byte 0): 33 => 33
2848 23:41:58.236376 Write leveling (Byte 1): 31 => 31
2849 23:41:58.240154 DramcWriteLeveling(PI) end<-----
2850 23:41:58.240240
2851 23:41:58.240307 ==
2852 23:41:58.243475 Dram Type= 6, Freq= 0, CH_0, rank 1
2853 23:41:58.246763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2854 23:41:58.249937 ==
2855 23:41:58.250023 [Gating] SW mode calibration
2856 23:41:58.260036 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2857 23:41:58.263387 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2858 23:41:58.266642 0 15 0 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
2859 23:41:58.273314 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 23:41:58.276668 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2861 23:41:58.280114 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2862 23:41:58.286549 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2863 23:41:58.290091 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 23:41:58.293492 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 1)
2865 23:41:58.299930 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
2866 23:41:58.303510 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 23:41:58.306647 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 23:41:58.313214 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2869 23:41:58.316577 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2870 23:41:58.319938 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 23:41:58.326746 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 23:41:58.330003 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2873 23:41:58.333361 1 0 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2874 23:41:58.336599 1 1 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2875 23:41:58.343104 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 23:41:58.346469 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 23:41:58.349983 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2878 23:41:58.356459 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 23:41:58.360242 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 23:41:58.363514 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 23:41:58.370125 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2882 23:41:58.373341 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 23:41:58.376679 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 23:41:58.383321 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 23:41:58.387019 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 23:41:58.390122 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 23:41:58.396532 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 23:41:58.400054 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 23:41:58.403100 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 23:41:58.409851 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 23:41:58.413215 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 23:41:58.417025 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 23:41:58.423534 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 23:41:58.426762 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 23:41:58.430004 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 23:41:58.433231 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2897 23:41:58.439772 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2898 23:41:58.443368 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2899 23:41:58.446763 Total UI for P1: 0, mck2ui 16
2900 23:41:58.449834 best dqsien dly found for B0: ( 1, 3, 26)
2901 23:41:58.453198 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2902 23:41:58.456832 Total UI for P1: 0, mck2ui 16
2903 23:41:58.459799 best dqsien dly found for B1: ( 1, 4, 0)
2904 23:41:58.463093 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2905 23:41:58.466385 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2906 23:41:58.466511
2907 23:41:58.472978 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2908 23:41:58.476326 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2909 23:41:58.476459 [Gating] SW calibration Done
2910 23:41:58.479492 ==
2911 23:41:58.483250 Dram Type= 6, Freq= 0, CH_0, rank 1
2912 23:41:58.486689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2913 23:41:58.486814 ==
2914 23:41:58.486926 RX Vref Scan: 0
2915 23:41:58.487041
2916 23:41:58.489698 RX Vref 0 -> 0, step: 1
2917 23:41:58.489823
2918 23:41:58.493274 RX Delay -40 -> 252, step: 8
2919 23:41:58.496404 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2920 23:41:58.499544 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2921 23:41:58.506279 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2922 23:41:58.509600 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2923 23:41:58.513178 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2924 23:41:58.516629 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2925 23:41:58.519832 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2926 23:41:58.523060 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2927 23:41:58.529479 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2928 23:41:58.533200 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2929 23:41:58.536340 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2930 23:41:58.539407 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2931 23:41:58.543221 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2932 23:41:58.549681 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2933 23:41:58.552942 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2934 23:41:58.556224 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
2935 23:41:58.556325 ==
2936 23:41:58.559659 Dram Type= 6, Freq= 0, CH_0, rank 1
2937 23:41:58.562993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2938 23:41:58.563101 ==
2939 23:41:58.566414 DQS Delay:
2940 23:41:58.566529 DQS0 = 0, DQS1 = 0
2941 23:41:58.569628 DQM Delay:
2942 23:41:58.569736 DQM0 = 112, DQM1 = 102
2943 23:41:58.572843 DQ Delay:
2944 23:41:58.576172 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2945 23:41:58.579603 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
2946 23:41:58.582953 DQ8 =91, DQ9 =83, DQ10 =107, DQ11 =95
2947 23:41:58.586585 DQ12 =107, DQ13 =111, DQ14 =115, DQ15 =107
2948 23:41:58.586711
2949 23:41:58.586824
2950 23:41:58.586935 ==
2951 23:41:58.589653 Dram Type= 6, Freq= 0, CH_0, rank 1
2952 23:41:58.592998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2953 23:41:58.593126 ==
2954 23:41:58.593240
2955 23:41:58.593353
2956 23:41:58.596197 TX Vref Scan disable
2957 23:41:58.599936 == TX Byte 0 ==
2958 23:41:58.603009 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2959 23:41:58.606632 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2960 23:41:58.609746 == TX Byte 1 ==
2961 23:41:58.612871 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2962 23:41:58.616080 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2963 23:41:58.616189 ==
2964 23:41:58.619586 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 23:41:58.622810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 23:41:58.622917 ==
2967 23:41:58.636099 TX Vref=22, minBit 0, minWin=26, winSum=424
2968 23:41:58.639429 TX Vref=24, minBit 1, minWin=26, winSum=428
2969 23:41:58.642668 TX Vref=26, minBit 0, minWin=26, winSum=433
2970 23:41:58.646011 TX Vref=28, minBit 0, minWin=26, winSum=438
2971 23:41:58.649722 TX Vref=30, minBit 1, minWin=27, winSum=440
2972 23:41:58.656032 TX Vref=32, minBit 1, minWin=26, winSum=441
2973 23:41:58.659267 [TxChooseVref] Worse bit 1, Min win 27, Win sum 440, Final Vref 30
2974 23:41:58.659374
2975 23:41:58.662585 Final TX Range 1 Vref 30
2976 23:41:58.662688
2977 23:41:58.662785 ==
2978 23:41:58.666238 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 23:41:58.669222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 23:41:58.669346 ==
2981 23:41:58.669445
2982 23:41:58.672565
2983 23:41:58.672664 TX Vref Scan disable
2984 23:41:58.675931 == TX Byte 0 ==
2985 23:41:58.679172 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2986 23:41:58.682503 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2987 23:41:58.685826 == TX Byte 1 ==
2988 23:41:58.689218 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2989 23:41:58.692985 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2990 23:41:58.693182
2991 23:41:58.696118 [DATLAT]
2992 23:41:58.696228 Freq=1200, CH0 RK1
2993 23:41:58.696324
2994 23:41:58.699321 DATLAT Default: 0xd
2995 23:41:58.699424 0, 0xFFFF, sum = 0
2996 23:41:58.702548 1, 0xFFFF, sum = 0
2997 23:41:58.702659 2, 0xFFFF, sum = 0
2998 23:41:58.705757 3, 0xFFFF, sum = 0
2999 23:41:58.705870 4, 0xFFFF, sum = 0
3000 23:41:58.709493 5, 0xFFFF, sum = 0
3001 23:41:58.709607 6, 0xFFFF, sum = 0
3002 23:41:58.712647 7, 0xFFFF, sum = 0
3003 23:41:58.715839 8, 0xFFFF, sum = 0
3004 23:41:58.715955 9, 0xFFFF, sum = 0
3005 23:41:58.719341 10, 0xFFFF, sum = 0
3006 23:41:58.719450 11, 0xFFFF, sum = 0
3007 23:41:58.722616 12, 0x0, sum = 1
3008 23:41:58.722720 13, 0x0, sum = 2
3009 23:41:58.725850 14, 0x0, sum = 3
3010 23:41:58.725955 15, 0x0, sum = 4
3011 23:41:58.726036 best_step = 13
3012 23:41:58.726098
3013 23:41:58.729166 ==
3014 23:41:58.732504 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 23:41:58.736402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 23:41:58.736536 ==
3017 23:41:58.736662 RX Vref Scan: 0
3018 23:41:58.736775
3019 23:41:58.739485 RX Vref 0 -> 0, step: 1
3020 23:41:58.739606
3021 23:41:58.742745 RX Delay -37 -> 252, step: 4
3022 23:41:58.746144 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3023 23:41:58.749236 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3024 23:41:58.755982 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3025 23:41:58.759384 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3026 23:41:58.762883 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3027 23:41:58.766037 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3028 23:41:58.769647 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3029 23:41:58.776188 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3030 23:41:58.779786 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3031 23:41:58.783072 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3032 23:41:58.786409 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3033 23:41:58.789569 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3034 23:41:58.796099 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3035 23:41:58.799689 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3036 23:41:58.803060 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3037 23:41:58.806271 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3038 23:41:58.806379 ==
3039 23:41:58.809747 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 23:41:58.816079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 23:41:58.816189 ==
3042 23:41:58.816290 DQS Delay:
3043 23:41:58.816389 DQS0 = 0, DQS1 = 0
3044 23:41:58.819356 DQM Delay:
3045 23:41:58.819461 DQM0 = 110, DQM1 = 100
3046 23:41:58.823001 DQ Delay:
3047 23:41:58.826587 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3048 23:41:58.829763 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =118
3049 23:41:58.832967 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =92
3050 23:41:58.836379 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3051 23:41:58.836488
3052 23:41:58.836586
3053 23:41:58.842958 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f8, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 403 ps
3054 23:41:58.845750 CH0 RK1: MR19=403, MR18=10F8
3055 23:41:58.852995 CH0_RK1: MR19=0x403, MR18=0x10F8, DQSOSC=403, MR23=63, INC=40, DEC=26
3056 23:41:58.855967 [RxdqsGatingPostProcess] freq 1200
3057 23:41:58.862871 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3058 23:41:58.866045 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 23:41:58.866188 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 23:41:58.869417 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 23:41:58.872597 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 23:41:58.876225 best DQS0 dly(2T, 0.5T) = (0, 11)
3063 23:41:58.879575 best DQS1 dly(2T, 0.5T) = (0, 12)
3064 23:41:58.882772 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3065 23:41:58.886210 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3066 23:41:58.889137 Pre-setting of DQS Precalculation
3067 23:41:58.895856 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3068 23:41:58.895977 ==
3069 23:41:58.899599 Dram Type= 6, Freq= 0, CH_1, rank 0
3070 23:41:58.902849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 23:41:58.902962 ==
3072 23:41:58.909198 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3073 23:41:58.912489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3074 23:41:58.922060 [CA 0] Center 37 (7~67) winsize 61
3075 23:41:58.925346 [CA 1] Center 37 (7~68) winsize 62
3076 23:41:58.928899 [CA 2] Center 34 (5~64) winsize 60
3077 23:41:58.932050 [CA 3] Center 33 (3~64) winsize 62
3078 23:41:58.935239 [CA 4] Center 34 (4~64) winsize 61
3079 23:41:58.938644 [CA 5] Center 33 (3~63) winsize 61
3080 23:41:58.938754
3081 23:41:58.941771 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3082 23:41:58.941882
3083 23:41:58.944994 [CATrainingPosCal] consider 1 rank data
3084 23:41:58.948379 u2DelayCellTimex100 = 270/100 ps
3085 23:41:58.952109 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3086 23:41:58.955429 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3087 23:41:58.961657 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3088 23:41:58.965248 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3089 23:41:58.968579 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3090 23:41:58.971999 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3091 23:41:58.972120
3092 23:41:58.975139 CA PerBit enable=1, Macro0, CA PI delay=33
3093 23:41:58.975249
3094 23:41:58.978827 [CBTSetCACLKResult] CA Dly = 33
3095 23:41:58.978937 CS Dly: 6 (0~37)
3096 23:41:58.979032 ==
3097 23:41:58.981902 Dram Type= 6, Freq= 0, CH_1, rank 1
3098 23:41:58.988424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3099 23:41:58.988547 ==
3100 23:41:58.992071 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3101 23:41:58.998682 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3102 23:41:59.007375 [CA 0] Center 37 (8~67) winsize 60
3103 23:41:59.011100 [CA 1] Center 37 (7~68) winsize 62
3104 23:41:59.014254 [CA 2] Center 34 (4~65) winsize 62
3105 23:41:59.017837 [CA 3] Center 33 (3~64) winsize 62
3106 23:41:59.021107 [CA 4] Center 34 (4~64) winsize 61
3107 23:41:59.024423 [CA 5] Center 33 (3~63) winsize 61
3108 23:41:59.024502
3109 23:41:59.027388 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3110 23:41:59.027470
3111 23:41:59.030858 [CATrainingPosCal] consider 2 rank data
3112 23:41:59.034179 u2DelayCellTimex100 = 270/100 ps
3113 23:41:59.037620 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3114 23:41:59.040946 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3115 23:41:59.047333 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3116 23:41:59.050710 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3117 23:41:59.053957 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3118 23:41:59.057752 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3119 23:41:59.057841
3120 23:41:59.061110 CA PerBit enable=1, Macro0, CA PI delay=33
3121 23:41:59.061187
3122 23:41:59.064273 [CBTSetCACLKResult] CA Dly = 33
3123 23:41:59.064387 CS Dly: 7 (0~39)
3124 23:41:59.064480
3125 23:41:59.067746 ----->DramcWriteLeveling(PI) begin...
3126 23:41:59.071008 ==
3127 23:41:59.074259 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 23:41:59.077589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 23:41:59.077696 ==
3130 23:41:59.080788 Write leveling (Byte 0): 24 => 24
3131 23:41:59.084066 Write leveling (Byte 1): 28 => 28
3132 23:41:59.087761 DramcWriteLeveling(PI) end<-----
3133 23:41:59.087843
3134 23:41:59.087908 ==
3135 23:41:59.091060 Dram Type= 6, Freq= 0, CH_1, rank 0
3136 23:41:59.094224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3137 23:41:59.094329 ==
3138 23:41:59.097379 [Gating] SW mode calibration
3139 23:41:59.104066 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3140 23:41:59.110538 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3141 23:41:59.114231 0 15 0 | B1->B0 | 3030 2c2c | 1 1 | (1 1) (0 0)
3142 23:41:59.117369 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 23:41:59.120725 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 23:41:59.127725 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3145 23:41:59.130595 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3146 23:41:59.133927 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3147 23:41:59.140617 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 23:41:59.144154 0 15 28 | B1->B0 | 2d2d 2a2a | 1 1 | (1 0) (1 0)
3149 23:41:59.147343 1 0 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3150 23:41:59.153580 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 23:41:59.157468 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 23:41:59.160271 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3153 23:41:59.167299 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 23:41:59.170493 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 23:41:59.173965 1 0 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3156 23:41:59.180429 1 0 28 | B1->B0 | 3c3c 3d3d | 0 1 | (1 1) (1 1)
3157 23:41:59.183875 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 23:41:59.187028 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 23:41:59.193884 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 23:41:59.197139 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3161 23:41:59.200455 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 23:41:59.207274 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 23:41:59.210349 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 23:41:59.213563 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3165 23:41:59.220587 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 23:41:59.223949 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 23:41:59.227135 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 23:41:59.230334 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 23:41:59.237383 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 23:41:59.240343 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 23:41:59.244165 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 23:41:59.250537 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 23:41:59.253864 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 23:41:59.257266 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 23:41:59.264135 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 23:41:59.267103 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 23:41:59.270574 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 23:41:59.277219 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 23:41:59.280501 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3180 23:41:59.283858 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3181 23:41:59.290286 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3182 23:41:59.290424 Total UI for P1: 0, mck2ui 16
3183 23:41:59.297656 best dqsien dly found for B1: ( 1, 3, 26)
3184 23:41:59.300913 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 23:41:59.304109 Total UI for P1: 0, mck2ui 16
3186 23:41:59.307391 best dqsien dly found for B0: ( 1, 3, 30)
3187 23:41:59.310830 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3188 23:41:59.314046 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3189 23:41:59.314170
3190 23:41:59.317104 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3191 23:41:59.320563 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3192 23:41:59.323880 [Gating] SW calibration Done
3193 23:41:59.324007 ==
3194 23:41:59.327544 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 23:41:59.330859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 23:41:59.330995 ==
3197 23:41:59.333956 RX Vref Scan: 0
3198 23:41:59.334084
3199 23:41:59.337121 RX Vref 0 -> 0, step: 1
3200 23:41:59.337250
3201 23:41:59.337366 RX Delay -40 -> 252, step: 8
3202 23:41:59.344172 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3203 23:41:59.347203 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3204 23:41:59.350515 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3205 23:41:59.353857 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3206 23:41:59.357325 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3207 23:41:59.363947 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3208 23:41:59.367051 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3209 23:41:59.370642 iDelay=200, Bit 7, Center 111 (32 ~ 191) 160
3210 23:41:59.373854 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3211 23:41:59.377431 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3212 23:41:59.380593 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3213 23:41:59.387237 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3214 23:41:59.390405 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3215 23:41:59.393849 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3216 23:41:59.397572 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3217 23:41:59.403998 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3218 23:41:59.404090 ==
3219 23:41:59.407079 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 23:41:59.410544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 23:41:59.410658 ==
3222 23:41:59.410769 DQS Delay:
3223 23:41:59.414155 DQS0 = 0, DQS1 = 0
3224 23:41:59.414290 DQM Delay:
3225 23:41:59.417392 DQM0 = 113, DQM1 = 104
3226 23:41:59.417470 DQ Delay:
3227 23:41:59.420625 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =111
3228 23:41:59.423899 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3229 23:41:59.427069 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
3230 23:41:59.430585 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3231 23:41:59.430699
3232 23:41:59.430794
3233 23:41:59.430885 ==
3234 23:41:59.433841 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 23:41:59.440431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 23:41:59.440550 ==
3237 23:41:59.440652
3238 23:41:59.440718
3239 23:41:59.440778 TX Vref Scan disable
3240 23:41:59.444241 == TX Byte 0 ==
3241 23:41:59.447330 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3242 23:41:59.453723 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3243 23:41:59.453815 == TX Byte 1 ==
3244 23:41:59.457618 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3245 23:41:59.464015 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3246 23:41:59.464104 ==
3247 23:41:59.467229 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 23:41:59.470373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 23:41:59.470496 ==
3250 23:41:59.482117 TX Vref=22, minBit 8, minWin=24, winSum=406
3251 23:41:59.485220 TX Vref=24, minBit 11, minWin=24, winSum=408
3252 23:41:59.488497 TX Vref=26, minBit 10, minWin=24, winSum=415
3253 23:41:59.492112 TX Vref=28, minBit 9, minWin=25, winSum=424
3254 23:41:59.495230 TX Vref=30, minBit 9, minWin=24, winSum=422
3255 23:41:59.502568 TX Vref=32, minBit 9, minWin=24, winSum=421
3256 23:41:59.505348 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 28
3257 23:41:59.505482
3258 23:41:59.508884 Final TX Range 1 Vref 28
3259 23:41:59.509015
3260 23:41:59.509124 ==
3261 23:41:59.512273 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 23:41:59.515505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 23:41:59.515633 ==
3264 23:41:59.515751
3265 23:41:59.518794
3266 23:41:59.518921 TX Vref Scan disable
3267 23:41:59.522104 == TX Byte 0 ==
3268 23:41:59.525375 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3269 23:41:59.528566 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3270 23:41:59.531886 == TX Byte 1 ==
3271 23:41:59.535202 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3272 23:41:59.538710 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3273 23:41:59.542178
3274 23:41:59.542308 [DATLAT]
3275 23:41:59.542422 Freq=1200, CH1 RK0
3276 23:41:59.542537
3277 23:41:59.545200 DATLAT Default: 0xd
3278 23:41:59.545327 0, 0xFFFF, sum = 0
3279 23:41:59.548527 1, 0xFFFF, sum = 0
3280 23:41:59.548665 2, 0xFFFF, sum = 0
3281 23:41:59.552022 3, 0xFFFF, sum = 0
3282 23:41:59.552151 4, 0xFFFF, sum = 0
3283 23:41:59.555672 5, 0xFFFF, sum = 0
3284 23:41:59.558935 6, 0xFFFF, sum = 0
3285 23:41:59.559068 7, 0xFFFF, sum = 0
3286 23:41:59.562154 8, 0xFFFF, sum = 0
3287 23:41:59.562284 9, 0xFFFF, sum = 0
3288 23:41:59.565507 10, 0xFFFF, sum = 0
3289 23:41:59.565620 11, 0xFFFF, sum = 0
3290 23:41:59.568678 12, 0x0, sum = 1
3291 23:41:59.568782 13, 0x0, sum = 2
3292 23:41:59.571876 14, 0x0, sum = 3
3293 23:41:59.571995 15, 0x0, sum = 4
3294 23:41:59.572095 best_step = 13
3295 23:41:59.572186
3296 23:41:59.575568 ==
3297 23:41:59.578466 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 23:41:59.581861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 23:41:59.581976 ==
3300 23:41:59.582070 RX Vref Scan: 1
3301 23:41:59.582160
3302 23:41:59.585228 Set Vref Range= 32 -> 127
3303 23:41:59.585342
3304 23:41:59.588507 RX Vref 32 -> 127, step: 1
3305 23:41:59.588606
3306 23:41:59.591661 RX Delay -21 -> 252, step: 4
3307 23:41:59.591760
3308 23:41:59.595417 Set Vref, RX VrefLevel [Byte0]: 32
3309 23:41:59.598526 [Byte1]: 32
3310 23:41:59.598641
3311 23:41:59.602067 Set Vref, RX VrefLevel [Byte0]: 33
3312 23:41:59.605167 [Byte1]: 33
3313 23:41:59.605262
3314 23:41:59.608506 Set Vref, RX VrefLevel [Byte0]: 34
3315 23:41:59.612104 [Byte1]: 34
3316 23:41:59.616330
3317 23:41:59.616442 Set Vref, RX VrefLevel [Byte0]: 35
3318 23:41:59.619417 [Byte1]: 35
3319 23:41:59.624005
3320 23:41:59.624120 Set Vref, RX VrefLevel [Byte0]: 36
3321 23:41:59.627759 [Byte1]: 36
3322 23:41:59.632082
3323 23:41:59.632186 Set Vref, RX VrefLevel [Byte0]: 37
3324 23:41:59.635343 [Byte1]: 37
3325 23:41:59.640394
3326 23:41:59.640502 Set Vref, RX VrefLevel [Byte0]: 38
3327 23:41:59.643069 [Byte1]: 38
3328 23:41:59.647740
3329 23:41:59.647823 Set Vref, RX VrefLevel [Byte0]: 39
3330 23:41:59.651267 [Byte1]: 39
3331 23:41:59.655776
3332 23:41:59.655886 Set Vref, RX VrefLevel [Byte0]: 40
3333 23:41:59.659059 [Byte1]: 40
3334 23:41:59.663958
3335 23:41:59.664068 Set Vref, RX VrefLevel [Byte0]: 41
3336 23:41:59.667330 [Byte1]: 41
3337 23:41:59.671723
3338 23:41:59.671806 Set Vref, RX VrefLevel [Byte0]: 42
3339 23:41:59.674734 [Byte1]: 42
3340 23:41:59.679700
3341 23:41:59.679780 Set Vref, RX VrefLevel [Byte0]: 43
3342 23:41:59.683057 [Byte1]: 43
3343 23:41:59.687630
3344 23:41:59.687744 Set Vref, RX VrefLevel [Byte0]: 44
3345 23:41:59.690734 [Byte1]: 44
3346 23:41:59.695751
3347 23:41:59.695836 Set Vref, RX VrefLevel [Byte0]: 45
3348 23:41:59.698825 [Byte1]: 45
3349 23:41:59.703492
3350 23:41:59.703576 Set Vref, RX VrefLevel [Byte0]: 46
3351 23:41:59.706613 [Byte1]: 46
3352 23:41:59.711276
3353 23:41:59.711363 Set Vref, RX VrefLevel [Byte0]: 47
3354 23:41:59.714771 [Byte1]: 47
3355 23:41:59.719023
3356 23:41:59.719106 Set Vref, RX VrefLevel [Byte0]: 48
3357 23:41:59.722820 [Byte1]: 48
3358 23:41:59.727201
3359 23:41:59.727312 Set Vref, RX VrefLevel [Byte0]: 49
3360 23:41:59.730748 [Byte1]: 49
3361 23:41:59.734951
3362 23:41:59.735036 Set Vref, RX VrefLevel [Byte0]: 50
3363 23:41:59.738305 [Byte1]: 50
3364 23:41:59.743263
3365 23:41:59.743383 Set Vref, RX VrefLevel [Byte0]: 51
3366 23:41:59.746566 [Byte1]: 51
3367 23:41:59.750941
3368 23:41:59.751029 Set Vref, RX VrefLevel [Byte0]: 52
3369 23:41:59.754142 [Byte1]: 52
3370 23:41:59.758792
3371 23:41:59.758877 Set Vref, RX VrefLevel [Byte0]: 53
3372 23:41:59.762094 [Byte1]: 53
3373 23:41:59.766641
3374 23:41:59.766732 Set Vref, RX VrefLevel [Byte0]: 54
3375 23:41:59.770285 [Byte1]: 54
3376 23:41:59.774937
3377 23:41:59.775058 Set Vref, RX VrefLevel [Byte0]: 55
3378 23:41:59.778089 [Byte1]: 55
3379 23:41:59.782506
3380 23:41:59.782590 Set Vref, RX VrefLevel [Byte0]: 56
3381 23:41:59.785871 [Byte1]: 56
3382 23:41:59.790655
3383 23:41:59.790760 Set Vref, RX VrefLevel [Byte0]: 57
3384 23:41:59.794001 [Byte1]: 57
3385 23:41:59.798413
3386 23:41:59.798500 Set Vref, RX VrefLevel [Byte0]: 58
3387 23:41:59.801723 [Byte1]: 58
3388 23:41:59.806350
3389 23:41:59.806437 Set Vref, RX VrefLevel [Byte0]: 59
3390 23:41:59.809516 [Byte1]: 59
3391 23:41:59.814349
3392 23:41:59.814434 Set Vref, RX VrefLevel [Byte0]: 60
3393 23:41:59.817342 [Byte1]: 60
3394 23:41:59.822349
3395 23:41:59.822441 Set Vref, RX VrefLevel [Byte0]: 61
3396 23:41:59.825603 [Byte1]: 61
3397 23:41:59.830148
3398 23:41:59.830241 Set Vref, RX VrefLevel [Byte0]: 62
3399 23:41:59.833352 [Byte1]: 62
3400 23:41:59.838245
3401 23:41:59.838331 Set Vref, RX VrefLevel [Byte0]: 63
3402 23:41:59.841273 [Byte1]: 63
3403 23:41:59.845760
3404 23:41:59.845859 Set Vref, RX VrefLevel [Byte0]: 64
3405 23:41:59.849654 [Byte1]: 64
3406 23:41:59.853835
3407 23:41:59.853929 Set Vref, RX VrefLevel [Byte0]: 65
3408 23:41:59.857171 [Byte1]: 65
3409 23:41:59.861885
3410 23:41:59.861977 Set Vref, RX VrefLevel [Byte0]: 66
3411 23:41:59.865139 [Byte1]: 66
3412 23:41:59.869510
3413 23:41:59.869621 Set Vref, RX VrefLevel [Byte0]: 67
3414 23:41:59.873131 [Byte1]: 67
3415 23:41:59.877658
3416 23:41:59.877747 Set Vref, RX VrefLevel [Byte0]: 68
3417 23:41:59.880984 [Byte1]: 68
3418 23:41:59.885476
3419 23:41:59.885568 Set Vref, RX VrefLevel [Byte0]: 69
3420 23:41:59.888751 [Byte1]: 69
3421 23:41:59.893552
3422 23:41:59.893640 Final RX Vref Byte 0 = 58 to rank0
3423 23:41:59.896846 Final RX Vref Byte 1 = 52 to rank0
3424 23:41:59.900097 Final RX Vref Byte 0 = 58 to rank1
3425 23:41:59.903401 Final RX Vref Byte 1 = 52 to rank1==
3426 23:41:59.907032 Dram Type= 6, Freq= 0, CH_1, rank 0
3427 23:41:59.913286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 23:41:59.913380 ==
3429 23:41:59.913450 DQS Delay:
3430 23:41:59.913513 DQS0 = 0, DQS1 = 0
3431 23:41:59.917004 DQM Delay:
3432 23:41:59.917126 DQM0 = 114, DQM1 = 105
3433 23:41:59.920293 DQ Delay:
3434 23:41:59.923383 DQ0 =116, DQ1 =108, DQ2 =104, DQ3 =112
3435 23:41:59.926820 DQ4 =112, DQ5 =124, DQ6 =126, DQ7 =112
3436 23:41:59.930433 DQ8 =92, DQ9 =98, DQ10 =104, DQ11 =100
3437 23:41:59.933565 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =110
3438 23:41:59.933655
3439 23:41:59.933723
3440 23:41:59.940383 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0f7, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3441 23:41:59.943660 CH1 RK0: MR19=303, MR18=F0F7
3442 23:41:59.950260 CH1_RK0: MR19=0x303, MR18=0xF0F7, DQSOSC=413, MR23=63, INC=38, DEC=25
3443 23:41:59.950383
3444 23:41:59.953209 ----->DramcWriteLeveling(PI) begin...
3445 23:41:59.953296 ==
3446 23:41:59.956496 Dram Type= 6, Freq= 0, CH_1, rank 1
3447 23:41:59.960073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3448 23:41:59.963750 ==
3449 23:41:59.963838 Write leveling (Byte 0): 26 => 26
3450 23:41:59.966718 Write leveling (Byte 1): 26 => 26
3451 23:41:59.970011 DramcWriteLeveling(PI) end<-----
3452 23:41:59.970125
3453 23:41:59.970226 ==
3454 23:41:59.973288 Dram Type= 6, Freq= 0, CH_1, rank 1
3455 23:41:59.979980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3456 23:41:59.980079 ==
3457 23:41:59.980147 [Gating] SW mode calibration
3458 23:41:59.990005 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3459 23:41:59.993121 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3460 23:41:59.996920 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3461 23:42:00.003410 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3462 23:42:00.006611 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 23:42:00.009872 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 23:42:00.016752 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 23:42:00.020101 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3466 23:42:00.023314 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
3467 23:42:00.030150 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3468 23:42:00.033243 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3469 23:42:00.036843 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 23:42:00.043157 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 23:42:00.046874 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 23:42:00.050169 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 23:42:00.056509 1 0 20 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
3474 23:42:00.060255 1 0 24 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
3475 23:42:00.063537 1 0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3476 23:42:00.069887 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 23:42:00.073309 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 23:42:00.076800 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 23:42:00.083418 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 23:42:00.086394 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 23:42:00.089843 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 23:42:00.096382 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3483 23:42:00.099817 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3484 23:42:00.103218 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 23:42:00.109591 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 23:42:00.112923 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 23:42:00.116659 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 23:42:00.122717 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 23:42:00.126268 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 23:42:00.129806 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 23:42:00.136018 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 23:42:00.139730 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 23:42:00.142842 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 23:42:00.149548 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 23:42:00.152284 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 23:42:00.155588 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 23:42:00.162603 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 23:42:00.165877 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3499 23:42:00.168989 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 23:42:00.172294 Total UI for P1: 0, mck2ui 16
3501 23:42:00.175540 best dqsien dly found for B0: ( 1, 3, 24)
3502 23:42:00.178865 Total UI for P1: 0, mck2ui 16
3503 23:42:00.182202 best dqsien dly found for B1: ( 1, 3, 26)
3504 23:42:00.185535 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3505 23:42:00.188703 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3506 23:42:00.188794
3507 23:42:00.192440 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3508 23:42:00.198707 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3509 23:42:00.198805 [Gating] SW calibration Done
3510 23:42:00.198875 ==
3511 23:42:00.202148 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 23:42:00.208641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 23:42:00.208736 ==
3514 23:42:00.208805 RX Vref Scan: 0
3515 23:42:00.208868
3516 23:42:00.212066 RX Vref 0 -> 0, step: 1
3517 23:42:00.212153
3518 23:42:00.215245 RX Delay -40 -> 252, step: 8
3519 23:42:00.219079 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
3520 23:42:00.222238 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3521 23:42:00.225501 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3522 23:42:00.232290 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3523 23:42:00.235641 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3524 23:42:00.239010 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3525 23:42:00.242237 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3526 23:42:00.245488 iDelay=200, Bit 7, Center 107 (32 ~ 183) 152
3527 23:42:00.249004 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3528 23:42:00.255235 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3529 23:42:00.258418 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3530 23:42:00.261960 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3531 23:42:00.265578 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3532 23:42:00.271899 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3533 23:42:00.275079 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3534 23:42:00.278292 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3535 23:42:00.278398 ==
3536 23:42:00.281612 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 23:42:00.285310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 23:42:00.285395 ==
3539 23:42:00.288530 DQS Delay:
3540 23:42:00.288652 DQS0 = 0, DQS1 = 0
3541 23:42:00.291629 DQM Delay:
3542 23:42:00.291740 DQM0 = 109, DQM1 = 107
3543 23:42:00.291811 DQ Delay:
3544 23:42:00.294911 DQ0 =111, DQ1 =107, DQ2 =99, DQ3 =107
3545 23:42:00.298796 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =107
3546 23:42:00.305322 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3547 23:42:00.308167 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3548 23:42:00.308284
3549 23:42:00.308378
3550 23:42:00.308469 ==
3551 23:42:00.311507 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 23:42:00.314856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 23:42:00.314940 ==
3554 23:42:00.315009
3555 23:42:00.315069
3556 23:42:00.318314 TX Vref Scan disable
3557 23:42:00.321961 == TX Byte 0 ==
3558 23:42:00.324885 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3559 23:42:00.328591 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3560 23:42:00.328675 == TX Byte 1 ==
3561 23:42:00.335072 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3562 23:42:00.338273 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3563 23:42:00.338354 ==
3564 23:42:00.341515 Dram Type= 6, Freq= 0, CH_1, rank 1
3565 23:42:00.344931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3566 23:42:00.345036 ==
3567 23:42:00.357712 TX Vref=22, minBit 9, minWin=25, winSum=417
3568 23:42:00.361103 TX Vref=24, minBit 0, minWin=26, winSum=424
3569 23:42:00.364458 TX Vref=26, minBit 3, minWin=26, winSum=427
3570 23:42:00.367635 TX Vref=28, minBit 9, minWin=26, winSum=433
3571 23:42:00.370913 TX Vref=30, minBit 9, minWin=25, winSum=430
3572 23:42:00.377589 TX Vref=32, minBit 1, minWin=25, winSum=429
3573 23:42:00.380795 [TxChooseVref] Worse bit 9, Min win 26, Win sum 433, Final Vref 28
3574 23:42:00.380881
3575 23:42:00.384143 Final TX Range 1 Vref 28
3576 23:42:00.384250
3577 23:42:00.384354 ==
3578 23:42:00.387425 Dram Type= 6, Freq= 0, CH_1, rank 1
3579 23:42:00.390678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3580 23:42:00.394276 ==
3581 23:42:00.394359
3582 23:42:00.394425
3583 23:42:00.394506 TX Vref Scan disable
3584 23:42:00.397426 == TX Byte 0 ==
3585 23:42:00.400653 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3586 23:42:00.404492 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3587 23:42:00.408119 == TX Byte 1 ==
3588 23:42:00.411236 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3589 23:42:00.413967 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3590 23:42:00.417398
3591 23:42:00.417504 [DATLAT]
3592 23:42:00.417606 Freq=1200, CH1 RK1
3593 23:42:00.417700
3594 23:42:00.421180 DATLAT Default: 0xd
3595 23:42:00.421258 0, 0xFFFF, sum = 0
3596 23:42:00.424200 1, 0xFFFF, sum = 0
3597 23:42:00.424287 2, 0xFFFF, sum = 0
3598 23:42:00.427615 3, 0xFFFF, sum = 0
3599 23:42:00.430567 4, 0xFFFF, sum = 0
3600 23:42:00.430680 5, 0xFFFF, sum = 0
3601 23:42:00.434215 6, 0xFFFF, sum = 0
3602 23:42:00.434299 7, 0xFFFF, sum = 0
3603 23:42:00.437576 8, 0xFFFF, sum = 0
3604 23:42:00.437709 9, 0xFFFF, sum = 0
3605 23:42:00.440606 10, 0xFFFF, sum = 0
3606 23:42:00.440737 11, 0xFFFF, sum = 0
3607 23:42:00.444477 12, 0x0, sum = 1
3608 23:42:00.444621 13, 0x0, sum = 2
3609 23:42:00.447741 14, 0x0, sum = 3
3610 23:42:00.447869 15, 0x0, sum = 4
3611 23:42:00.450892 best_step = 13
3612 23:42:00.451019
3613 23:42:00.451116 ==
3614 23:42:00.454127 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 23:42:00.457219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 23:42:00.457319 ==
3617 23:42:00.457411 RX Vref Scan: 0
3618 23:42:00.457503
3619 23:42:00.460543 RX Vref 0 -> 0, step: 1
3620 23:42:00.460679
3621 23:42:00.464129 RX Delay -21 -> 252, step: 4
3622 23:42:00.467131 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3623 23:42:00.473975 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3624 23:42:00.477183 iDelay=195, Bit 2, Center 104 (35 ~ 174) 140
3625 23:42:00.480369 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
3626 23:42:00.483753 iDelay=195, Bit 4, Center 110 (43 ~ 178) 136
3627 23:42:00.486956 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3628 23:42:00.493570 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3629 23:42:00.497275 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3630 23:42:00.500379 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3631 23:42:00.503588 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3632 23:42:00.506950 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3633 23:42:00.513489 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3634 23:42:00.516756 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3635 23:42:00.520021 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3636 23:42:00.523502 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3637 23:42:00.530212 iDelay=195, Bit 15, Center 118 (51 ~ 186) 136
3638 23:42:00.530342 ==
3639 23:42:00.533347 Dram Type= 6, Freq= 0, CH_1, rank 1
3640 23:42:00.537034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3641 23:42:00.537159 ==
3642 23:42:00.537257 DQS Delay:
3643 23:42:00.540099 DQS0 = 0, DQS1 = 0
3644 23:42:00.540211 DQM Delay:
3645 23:42:00.543715 DQM0 = 112, DQM1 = 110
3646 23:42:00.543830 DQ Delay:
3647 23:42:00.546557 DQ0 =114, DQ1 =110, DQ2 =104, DQ3 =110
3648 23:42:00.549931 DQ4 =110, DQ5 =120, DQ6 =122, DQ7 =110
3649 23:42:00.553171 DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =106
3650 23:42:00.556963 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =118
3651 23:42:00.557085
3652 23:42:00.557181
3653 23:42:00.566535 [DQSOSCAuto] RK1, (LSB)MR18= 0xf808, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3654 23:42:00.569705 CH1 RK1: MR19=304, MR18=F808
3655 23:42:00.573221 CH1_RK1: MR19=0x304, MR18=0xF808, DQSOSC=406, MR23=63, INC=39, DEC=26
3656 23:42:00.576743 [RxdqsGatingPostProcess] freq 1200
3657 23:42:00.583137 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3658 23:42:00.586600 best DQS0 dly(2T, 0.5T) = (0, 11)
3659 23:42:00.589963 best DQS1 dly(2T, 0.5T) = (0, 11)
3660 23:42:00.593134 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3661 23:42:00.596540 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3662 23:42:00.599748 best DQS0 dly(2T, 0.5T) = (0, 11)
3663 23:42:00.602819 best DQS1 dly(2T, 0.5T) = (0, 11)
3664 23:42:00.606612 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3665 23:42:00.609844 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3666 23:42:00.613097 Pre-setting of DQS Precalculation
3667 23:42:00.616427 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3668 23:42:00.623080 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3669 23:42:00.629502 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3670 23:42:00.632745
3671 23:42:00.632859
3672 23:42:00.632962 [Calibration Summary] 2400 Mbps
3673 23:42:00.636129 CH 0, Rank 0
3674 23:42:00.636238 SW Impedance : PASS
3675 23:42:00.639733 DUTY Scan : NO K
3676 23:42:00.642937 ZQ Calibration : PASS
3677 23:42:00.643050 Jitter Meter : NO K
3678 23:42:00.645976 CBT Training : PASS
3679 23:42:00.649240 Write leveling : PASS
3680 23:42:00.649352 RX DQS gating : PASS
3681 23:42:00.652512 RX DQ/DQS(RDDQC) : PASS
3682 23:42:00.655976 TX DQ/DQS : PASS
3683 23:42:00.656092 RX DATLAT : PASS
3684 23:42:00.659232 RX DQ/DQS(Engine): PASS
3685 23:42:00.662956 TX OE : NO K
3686 23:42:00.663080 All Pass.
3687 23:42:00.663178
3688 23:42:00.663270 CH 0, Rank 1
3689 23:42:00.665984 SW Impedance : PASS
3690 23:42:00.669368 DUTY Scan : NO K
3691 23:42:00.669455 ZQ Calibration : PASS
3692 23:42:00.672581 Jitter Meter : NO K
3693 23:42:00.676088 CBT Training : PASS
3694 23:42:00.676209 Write leveling : PASS
3695 23:42:00.679530 RX DQS gating : PASS
3696 23:42:00.679642 RX DQ/DQS(RDDQC) : PASS
3697 23:42:00.682893 TX DQ/DQS : PASS
3698 23:42:00.685900 RX DATLAT : PASS
3699 23:42:00.686019 RX DQ/DQS(Engine): PASS
3700 23:42:00.689323 TX OE : NO K
3701 23:42:00.689444 All Pass.
3702 23:42:00.689541
3703 23:42:00.692524 CH 1, Rank 0
3704 23:42:00.692644 SW Impedance : PASS
3705 23:42:00.696126 DUTY Scan : NO K
3706 23:42:00.699473 ZQ Calibration : PASS
3707 23:42:00.699557 Jitter Meter : NO K
3708 23:42:00.702272 CBT Training : PASS
3709 23:42:00.706043 Write leveling : PASS
3710 23:42:00.706157 RX DQS gating : PASS
3711 23:42:00.709014 RX DQ/DQS(RDDQC) : PASS
3712 23:42:00.712378 TX DQ/DQS : PASS
3713 23:42:00.712461 RX DATLAT : PASS
3714 23:42:00.715624 RX DQ/DQS(Engine): PASS
3715 23:42:00.719375 TX OE : NO K
3716 23:42:00.719458 All Pass.
3717 23:42:00.719524
3718 23:42:00.719585 CH 1, Rank 1
3719 23:42:00.722116 SW Impedance : PASS
3720 23:42:00.725888 DUTY Scan : NO K
3721 23:42:00.725968 ZQ Calibration : PASS
3722 23:42:00.729109 Jitter Meter : NO K
3723 23:42:00.732386 CBT Training : PASS
3724 23:42:00.732465 Write leveling : PASS
3725 23:42:00.735715 RX DQS gating : PASS
3726 23:42:00.735831 RX DQ/DQS(RDDQC) : PASS
3727 23:42:00.738843 TX DQ/DQS : PASS
3728 23:42:00.742178 RX DATLAT : PASS
3729 23:42:00.742261 RX DQ/DQS(Engine): PASS
3730 23:42:00.745987 TX OE : NO K
3731 23:42:00.746068 All Pass.
3732 23:42:00.746132
3733 23:42:00.748800 DramC Write-DBI off
3734 23:42:00.752279 PER_BANK_REFRESH: Hybrid Mode
3735 23:42:00.752366 TX_TRACKING: ON
3736 23:42:00.762260 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3737 23:42:00.765332 [FAST_K] Save calibration result to emmc
3738 23:42:00.768703 dramc_set_vcore_voltage set vcore to 650000
3739 23:42:00.771976 Read voltage for 600, 5
3740 23:42:00.772068 Vio18 = 0
3741 23:42:00.775373 Vcore = 650000
3742 23:42:00.775487 Vdram = 0
3743 23:42:00.775585 Vddq = 0
3744 23:42:00.775675 Vmddr = 0
3745 23:42:00.781971 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3746 23:42:00.788641 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3747 23:42:00.788739 MEM_TYPE=3, freq_sel=19
3748 23:42:00.792204 sv_algorithm_assistance_LP4_1600
3749 23:42:00.795122 ============ PULL DRAM RESETB DOWN ============
3750 23:42:00.801875 ========== PULL DRAM RESETB DOWN end =========
3751 23:42:00.805474 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3752 23:42:00.808457 ===================================
3753 23:42:00.812030 LPDDR4 DRAM CONFIGURATION
3754 23:42:00.815401 ===================================
3755 23:42:00.815481 EX_ROW_EN[0] = 0x0
3756 23:42:00.818695 EX_ROW_EN[1] = 0x0
3757 23:42:00.818774 LP4Y_EN = 0x0
3758 23:42:00.821993 WORK_FSP = 0x0
3759 23:42:00.822067 WL = 0x2
3760 23:42:00.825245 RL = 0x2
3761 23:42:00.825318 BL = 0x2
3762 23:42:00.828497 RPST = 0x0
3763 23:42:00.831711 RD_PRE = 0x0
3764 23:42:00.831787 WR_PRE = 0x1
3765 23:42:00.834946 WR_PST = 0x0
3766 23:42:00.835024 DBI_WR = 0x0
3767 23:42:00.838303 DBI_RD = 0x0
3768 23:42:00.838379 OTF = 0x1
3769 23:42:00.841421 ===================================
3770 23:42:00.844778 ===================================
3771 23:42:00.844866 ANA top config
3772 23:42:00.848637 ===================================
3773 23:42:00.851879 DLL_ASYNC_EN = 0
3774 23:42:00.854938 ALL_SLAVE_EN = 1
3775 23:42:00.858351 NEW_RANK_MODE = 1
3776 23:42:00.861788 DLL_IDLE_MODE = 1
3777 23:42:00.861871 LP45_APHY_COMB_EN = 1
3778 23:42:00.864956 TX_ODT_DIS = 1
3779 23:42:00.868154 NEW_8X_MODE = 1
3780 23:42:00.871267 ===================================
3781 23:42:00.874888 ===================================
3782 23:42:00.877937 data_rate = 1200
3783 23:42:00.881352 CKR = 1
3784 23:42:00.884757 DQ_P2S_RATIO = 8
3785 23:42:00.884884 ===================================
3786 23:42:00.888357 CA_P2S_RATIO = 8
3787 23:42:00.891741 DQ_CA_OPEN = 0
3788 23:42:00.894648 DQ_SEMI_OPEN = 0
3789 23:42:00.897921 CA_SEMI_OPEN = 0
3790 23:42:00.901294 CA_FULL_RATE = 0
3791 23:42:00.901421 DQ_CKDIV4_EN = 1
3792 23:42:00.904622 CA_CKDIV4_EN = 1
3793 23:42:00.908120 CA_PREDIV_EN = 0
3794 23:42:00.911671 PH8_DLY = 0
3795 23:42:00.914668 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3796 23:42:00.918221 DQ_AAMCK_DIV = 4
3797 23:42:00.918345 CA_AAMCK_DIV = 4
3798 23:42:00.921611 CA_ADMCK_DIV = 4
3799 23:42:00.924796 DQ_TRACK_CA_EN = 0
3800 23:42:00.928036 CA_PICK = 600
3801 23:42:00.931345 CA_MCKIO = 600
3802 23:42:00.934505 MCKIO_SEMI = 0
3803 23:42:00.937902 PLL_FREQ = 2288
3804 23:42:00.937985 DQ_UI_PI_RATIO = 32
3805 23:42:00.941418 CA_UI_PI_RATIO = 0
3806 23:42:00.944374 ===================================
3807 23:42:00.947657 ===================================
3808 23:42:00.951014 memory_type:LPDDR4
3809 23:42:00.955047 GP_NUM : 10
3810 23:42:00.955131 SRAM_EN : 1
3811 23:42:00.957973 MD32_EN : 0
3812 23:42:00.961143 ===================================
3813 23:42:00.964236 [ANA_INIT] >>>>>>>>>>>>>>
3814 23:42:00.964319 <<<<<< [CONFIGURE PHASE]: ANA_TX
3815 23:42:00.967903 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3816 23:42:00.971562 ===================================
3817 23:42:00.974402 data_rate = 1200,PCW = 0X5800
3818 23:42:00.977509 ===================================
3819 23:42:00.980674 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3820 23:42:00.987574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3821 23:42:00.994264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3822 23:42:00.997427 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3823 23:42:01.000873 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3824 23:42:01.003789 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3825 23:42:01.007027 [ANA_INIT] flow start
3826 23:42:01.007112 [ANA_INIT] PLL >>>>>>>>
3827 23:42:01.010566 [ANA_INIT] PLL <<<<<<<<
3828 23:42:01.014084 [ANA_INIT] MIDPI >>>>>>>>
3829 23:42:01.017072 [ANA_INIT] MIDPI <<<<<<<<
3830 23:42:01.017190 [ANA_INIT] DLL >>>>>>>>
3831 23:42:01.020344 [ANA_INIT] flow end
3832 23:42:01.023848 ============ LP4 DIFF to SE enter ============
3833 23:42:01.027019 ============ LP4 DIFF to SE exit ============
3834 23:42:01.030331 [ANA_INIT] <<<<<<<<<<<<<
3835 23:42:01.033739 [Flow] Enable top DCM control >>>>>
3836 23:42:01.037478 [Flow] Enable top DCM control <<<<<
3837 23:42:01.040197 Enable DLL master slave shuffle
3838 23:42:01.047096 ==============================================================
3839 23:42:01.047209 Gating Mode config
3840 23:42:01.053695 ==============================================================
3841 23:42:01.053792 Config description:
3842 23:42:01.063883 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3843 23:42:01.070269 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3844 23:42:01.077016 SELPH_MODE 0: By rank 1: By Phase
3845 23:42:01.080362 ==============================================================
3846 23:42:01.083527 GAT_TRACK_EN = 1
3847 23:42:01.086788 RX_GATING_MODE = 2
3848 23:42:01.089892 RX_GATING_TRACK_MODE = 2
3849 23:42:01.093534 SELPH_MODE = 1
3850 23:42:01.096953 PICG_EARLY_EN = 1
3851 23:42:01.100253 VALID_LAT_VALUE = 1
3852 23:42:01.106880 ==============================================================
3853 23:42:01.110013 Enter into Gating configuration >>>>
3854 23:42:01.113536 Exit from Gating configuration <<<<
3855 23:42:01.113650 Enter into DVFS_PRE_config >>>>>
3856 23:42:01.126761 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3857 23:42:01.129683 Exit from DVFS_PRE_config <<<<<
3858 23:42:01.133249 Enter into PICG configuration >>>>
3859 23:42:01.136530 Exit from PICG configuration <<<<
3860 23:42:01.136633 [RX_INPUT] configuration >>>>>
3861 23:42:01.139709 [RX_INPUT] configuration <<<<<
3862 23:42:01.146255 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3863 23:42:01.152871 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3864 23:42:01.156191 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3865 23:42:01.162774 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3866 23:42:01.169709 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3867 23:42:01.176271 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3868 23:42:01.179796 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3869 23:42:01.182514 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3870 23:42:01.189349 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3871 23:42:01.192616 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3872 23:42:01.195834 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3873 23:42:01.202275 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3874 23:42:01.205809 ===================================
3875 23:42:01.205960 LPDDR4 DRAM CONFIGURATION
3876 23:42:01.209096 ===================================
3877 23:42:01.212815 EX_ROW_EN[0] = 0x0
3878 23:42:01.212941 EX_ROW_EN[1] = 0x0
3879 23:42:01.215759 LP4Y_EN = 0x0
3880 23:42:01.215867 WORK_FSP = 0x0
3881 23:42:01.219285 WL = 0x2
3882 23:42:01.219398 RL = 0x2
3883 23:42:01.222628 BL = 0x2
3884 23:42:01.225895 RPST = 0x0
3885 23:42:01.225984 RD_PRE = 0x0
3886 23:42:01.229052 WR_PRE = 0x1
3887 23:42:01.229164 WR_PST = 0x0
3888 23:42:01.232330 DBI_WR = 0x0
3889 23:42:01.232442 DBI_RD = 0x0
3890 23:42:01.235760 OTF = 0x1
3891 23:42:01.238821 ===================================
3892 23:42:01.242178 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3893 23:42:01.245425 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3894 23:42:01.248704 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3895 23:42:01.252493 ===================================
3896 23:42:01.255254 LPDDR4 DRAM CONFIGURATION
3897 23:42:01.259249 ===================================
3898 23:42:01.262362 EX_ROW_EN[0] = 0x10
3899 23:42:01.262485 EX_ROW_EN[1] = 0x0
3900 23:42:01.265556 LP4Y_EN = 0x0
3901 23:42:01.265687 WORK_FSP = 0x0
3902 23:42:01.268762 WL = 0x2
3903 23:42:01.268896 RL = 0x2
3904 23:42:01.271861 BL = 0x2
3905 23:42:01.275174 RPST = 0x0
3906 23:42:01.275318 RD_PRE = 0x0
3907 23:42:01.278421 WR_PRE = 0x1
3908 23:42:01.278552 WR_PST = 0x0
3909 23:42:01.282288 DBI_WR = 0x0
3910 23:42:01.282409 DBI_RD = 0x0
3911 23:42:01.285537 OTF = 0x1
3912 23:42:01.289027 ===================================
3913 23:42:01.294943 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3914 23:42:01.298256 nWR fixed to 30
3915 23:42:01.298392 [ModeRegInit_LP4] CH0 RK0
3916 23:42:01.302062 [ModeRegInit_LP4] CH0 RK1
3917 23:42:01.305128 [ModeRegInit_LP4] CH1 RK0
3918 23:42:01.305238 [ModeRegInit_LP4] CH1 RK1
3919 23:42:01.308203 match AC timing 17
3920 23:42:01.311651 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3921 23:42:01.315392 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3922 23:42:01.321647 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3923 23:42:01.325071 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3924 23:42:01.331461 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3925 23:42:01.331555 ==
3926 23:42:01.334711 Dram Type= 6, Freq= 0, CH_0, rank 0
3927 23:42:01.338163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3928 23:42:01.338250 ==
3929 23:42:01.344899 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3930 23:42:01.351325 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3931 23:42:01.354567 [CA 0] Center 37 (7~67) winsize 61
3932 23:42:01.357922 [CA 1] Center 37 (7~67) winsize 61
3933 23:42:01.361291 [CA 2] Center 35 (5~65) winsize 61
3934 23:42:01.364564 [CA 3] Center 35 (5~65) winsize 61
3935 23:42:01.368245 [CA 4] Center 34 (4~65) winsize 62
3936 23:42:01.371524 [CA 5] Center 34 (3~65) winsize 63
3937 23:42:01.371647
3938 23:42:01.374542 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3939 23:42:01.374676
3940 23:42:01.377682 [CATrainingPosCal] consider 1 rank data
3941 23:42:01.381447 u2DelayCellTimex100 = 270/100 ps
3942 23:42:01.384459 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3943 23:42:01.387758 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3944 23:42:01.390979 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3945 23:42:01.394680 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3946 23:42:01.397749 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3947 23:42:01.401102 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
3948 23:42:01.401223
3949 23:42:01.404224 CA PerBit enable=1, Macro0, CA PI delay=34
3950 23:42:01.407653
3951 23:42:01.407802 [CBTSetCACLKResult] CA Dly = 34
3952 23:42:01.411001 CS Dly: 6 (0~37)
3953 23:42:01.411125 ==
3954 23:42:01.414102 Dram Type= 6, Freq= 0, CH_0, rank 1
3955 23:42:01.417676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3956 23:42:01.417783 ==
3957 23:42:01.424289 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3958 23:42:01.430783 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3959 23:42:01.434333 [CA 0] Center 37 (7~67) winsize 61
3960 23:42:01.437203 [CA 1] Center 37 (7~67) winsize 61
3961 23:42:01.440795 [CA 2] Center 35 (5~65) winsize 61
3962 23:42:01.443903 [CA 3] Center 34 (4~65) winsize 62
3963 23:42:01.447502 [CA 4] Center 34 (4~65) winsize 62
3964 23:42:01.450388 [CA 5] Center 33 (3~64) winsize 62
3965 23:42:01.450512
3966 23:42:01.454096 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3967 23:42:01.454185
3968 23:42:01.457253 [CATrainingPosCal] consider 2 rank data
3969 23:42:01.460353 u2DelayCellTimex100 = 270/100 ps
3970 23:42:01.463815 CA0 delay=37 (7~67),Diff = 4 PI (38 cell)
3971 23:42:01.467093 CA1 delay=37 (7~67),Diff = 4 PI (38 cell)
3972 23:42:01.470314 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3973 23:42:01.473891 CA3 delay=35 (5~65),Diff = 2 PI (19 cell)
3974 23:42:01.477046 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
3975 23:42:01.483899 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3976 23:42:01.484051
3977 23:42:01.487154 CA PerBit enable=1, Macro0, CA PI delay=33
3978 23:42:01.487264
3979 23:42:01.490406 [CBTSetCACLKResult] CA Dly = 33
3980 23:42:01.490485 CS Dly: 6 (0~37)
3981 23:42:01.490568
3982 23:42:01.493761 ----->DramcWriteLeveling(PI) begin...
3983 23:42:01.493840 ==
3984 23:42:01.497012 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 23:42:01.503407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 23:42:01.503540 ==
3987 23:42:01.506911 Write leveling (Byte 0): 33 => 33
3988 23:42:01.507042 Write leveling (Byte 1): 33 => 33
3989 23:42:01.510343 DramcWriteLeveling(PI) end<-----
3990 23:42:01.510427
3991 23:42:01.513547 ==
3992 23:42:01.513676 Dram Type= 6, Freq= 0, CH_0, rank 0
3993 23:42:01.520468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3994 23:42:01.520608 ==
3995 23:42:01.523564 [Gating] SW mode calibration
3996 23:42:01.530154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3997 23:42:01.533807 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3998 23:42:01.540021 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3999 23:42:01.543499 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4000 23:42:01.546512 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 23:42:01.553078 0 9 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
4002 23:42:01.556229 0 9 16 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (1 1)
4003 23:42:01.559512 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4004 23:42:01.566425 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4005 23:42:01.569798 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 23:42:01.572996 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 23:42:01.579931 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 23:42:01.583128 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 23:42:01.586132 0 10 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4010 23:42:01.592790 0 10 16 | B1->B0 | 3333 3a3a | 0 0 | (0 0) (1 1)
4011 23:42:01.596066 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4012 23:42:01.599383 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 23:42:01.605928 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 23:42:01.609215 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 23:42:01.612772 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 23:42:01.619530 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 23:42:01.622697 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 23:42:01.626017 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4019 23:42:01.632542 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 23:42:01.635694 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 23:42:01.639605 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 23:42:01.645618 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 23:42:01.648936 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 23:42:01.652263 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 23:42:01.659179 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 23:42:01.662382 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 23:42:01.665447 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 23:42:01.672456 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 23:42:01.675512 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 23:42:01.678575 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 23:42:01.685358 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 23:42:01.688530 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 23:42:01.692257 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4034 23:42:01.695522 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4035 23:42:01.698726 Total UI for P1: 0, mck2ui 16
4036 23:42:01.701960 best dqsien dly found for B0: ( 0, 13, 12)
4037 23:42:01.708490 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 23:42:01.711758 Total UI for P1: 0, mck2ui 16
4039 23:42:01.715126 best dqsien dly found for B1: ( 0, 13, 16)
4040 23:42:01.718696 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4041 23:42:01.722040 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4042 23:42:01.722174
4043 23:42:01.725335 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4044 23:42:01.728251 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4045 23:42:01.731849 [Gating] SW calibration Done
4046 23:42:01.731979 ==
4047 23:42:01.735143 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 23:42:01.738499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 23:42:01.738648 ==
4050 23:42:01.741804 RX Vref Scan: 0
4051 23:42:01.741932
4052 23:42:01.745592 RX Vref 0 -> 0, step: 1
4053 23:42:01.745721
4054 23:42:01.745839 RX Delay -230 -> 252, step: 16
4055 23:42:01.751900 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4056 23:42:01.755129 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4057 23:42:01.758459 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4058 23:42:01.761743 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4059 23:42:01.768103 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4060 23:42:01.771590 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4061 23:42:01.774733 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4062 23:42:01.777961 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4063 23:42:01.784902 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4064 23:42:01.788337 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4065 23:42:01.791618 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4066 23:42:01.794600 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4067 23:42:01.801231 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4068 23:42:01.804585 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4069 23:42:01.807715 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4070 23:42:01.811196 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4071 23:42:01.811359 ==
4072 23:42:01.814564 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 23:42:01.821278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 23:42:01.821452 ==
4075 23:42:01.821550 DQS Delay:
4076 23:42:01.824271 DQS0 = 0, DQS1 = 0
4077 23:42:01.824402 DQM Delay:
4078 23:42:01.824518 DQM0 = 38, DQM1 = 30
4079 23:42:01.827564 DQ Delay:
4080 23:42:01.831357 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4081 23:42:01.834488 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4082 23:42:01.837765 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4083 23:42:01.841049 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4084 23:42:01.841164
4085 23:42:01.841263
4086 23:42:01.841358 ==
4087 23:42:01.844487 Dram Type= 6, Freq= 0, CH_0, rank 0
4088 23:42:01.847701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4089 23:42:01.847794 ==
4090 23:42:01.847883
4091 23:42:01.847969
4092 23:42:01.851523 TX Vref Scan disable
4093 23:42:01.851625 == TX Byte 0 ==
4094 23:42:01.857832 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4095 23:42:01.861213 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4096 23:42:01.861350 == TX Byte 1 ==
4097 23:42:01.867708 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4098 23:42:01.871096 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4099 23:42:01.871242 ==
4100 23:42:01.874221 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 23:42:01.877831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 23:42:01.877956 ==
4103 23:42:01.878052
4104 23:42:01.880793
4105 23:42:01.880926 TX Vref Scan disable
4106 23:42:01.884195 == TX Byte 0 ==
4107 23:42:01.887391 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4108 23:42:01.894323 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4109 23:42:01.894512 == TX Byte 1 ==
4110 23:42:01.897483 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4111 23:42:01.904123 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4112 23:42:01.904293
4113 23:42:01.904410 [DATLAT]
4114 23:42:01.904521 Freq=600, CH0 RK0
4115 23:42:01.904641
4116 23:42:01.907681 DATLAT Default: 0x9
4117 23:42:01.907800 0, 0xFFFF, sum = 0
4118 23:42:01.910995 1, 0xFFFF, sum = 0
4119 23:42:01.911119 2, 0xFFFF, sum = 0
4120 23:42:01.914203 3, 0xFFFF, sum = 0
4121 23:42:01.917689 4, 0xFFFF, sum = 0
4122 23:42:01.917812 5, 0xFFFF, sum = 0
4123 23:42:01.920439 6, 0xFFFF, sum = 0
4124 23:42:01.920565 7, 0xFFFF, sum = 0
4125 23:42:01.923767 8, 0x0, sum = 1
4126 23:42:01.923884 9, 0x0, sum = 2
4127 23:42:01.923996 10, 0x0, sum = 3
4128 23:42:01.927032 11, 0x0, sum = 4
4129 23:42:01.927155 best_step = 9
4130 23:42:01.927266
4131 23:42:01.927377 ==
4132 23:42:01.930454 Dram Type= 6, Freq= 0, CH_0, rank 0
4133 23:42:01.937456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4134 23:42:01.937565 ==
4135 23:42:01.937659 RX Vref Scan: 1
4136 23:42:01.937749
4137 23:42:01.940741 RX Vref 0 -> 0, step: 1
4138 23:42:01.940838
4139 23:42:01.943868 RX Delay -195 -> 252, step: 8
4140 23:42:01.943955
4141 23:42:01.947137 Set Vref, RX VrefLevel [Byte0]: 60
4142 23:42:01.950549 [Byte1]: 51
4143 23:42:01.950663
4144 23:42:01.953787 Final RX Vref Byte 0 = 60 to rank0
4145 23:42:01.957167 Final RX Vref Byte 1 = 51 to rank0
4146 23:42:01.960516 Final RX Vref Byte 0 = 60 to rank1
4147 23:42:01.963883 Final RX Vref Byte 1 = 51 to rank1==
4148 23:42:01.967209 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 23:42:01.970480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 23:42:01.970583 ==
4151 23:42:01.973739 DQS Delay:
4152 23:42:01.973825 DQS0 = 0, DQS1 = 0
4153 23:42:01.976879 DQM Delay:
4154 23:42:01.976963 DQM0 = 34, DQM1 = 29
4155 23:42:01.977028 DQ Delay:
4156 23:42:01.980182 DQ0 =36, DQ1 =36, DQ2 =32, DQ3 =36
4157 23:42:01.983491 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4158 23:42:01.987133 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4159 23:42:01.990062 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4160 23:42:01.990139
4161 23:42:01.990203
4162 23:42:02.000304 [DQSOSCAuto] RK0, (LSB)MR18= 0x4442, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4163 23:42:02.003628 CH0 RK0: MR19=808, MR18=4442
4164 23:42:02.010288 CH0_RK0: MR19=0x808, MR18=0x4442, DQSOSC=396, MR23=63, INC=167, DEC=111
4165 23:42:02.010414
4166 23:42:02.013638 ----->DramcWriteLeveling(PI) begin...
4167 23:42:02.013763 ==
4168 23:42:02.017004 Dram Type= 6, Freq= 0, CH_0, rank 1
4169 23:42:02.020317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 23:42:02.020423 ==
4171 23:42:02.023081 Write leveling (Byte 0): 32 => 32
4172 23:42:02.027074 Write leveling (Byte 1): 31 => 31
4173 23:42:02.030246 DramcWriteLeveling(PI) end<-----
4174 23:42:02.030365
4175 23:42:02.030478 ==
4176 23:42:02.033507 Dram Type= 6, Freq= 0, CH_0, rank 1
4177 23:42:02.036695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4178 23:42:02.036802 ==
4179 23:42:02.040156 [Gating] SW mode calibration
4180 23:42:02.046527 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4181 23:42:02.053301 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4182 23:42:02.056489 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4183 23:42:02.060167 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4184 23:42:02.066426 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 23:42:02.069910 0 9 12 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
4186 23:42:02.073243 0 9 16 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
4187 23:42:02.079867 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4188 23:42:02.083189 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4189 23:42:02.086500 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 23:42:02.093252 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 23:42:02.096796 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 23:42:02.099761 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4193 23:42:02.106439 0 10 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
4194 23:42:02.110019 0 10 16 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
4195 23:42:02.112752 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 23:42:02.119529 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4197 23:42:02.122829 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 23:42:02.126166 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 23:42:02.132756 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 23:42:02.136119 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 23:42:02.139230 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4202 23:42:02.145754 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 23:42:02.149107 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 23:42:02.152520 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 23:42:02.159324 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 23:42:02.162510 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 23:42:02.165851 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 23:42:02.172192 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 23:42:02.176002 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 23:42:02.179297 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 23:42:02.186149 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 23:42:02.188744 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 23:42:02.192406 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 23:42:02.195464 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 23:42:02.202151 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 23:42:02.205364 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 23:42:02.211807 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4218 23:42:02.215431 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4219 23:42:02.218660 Total UI for P1: 0, mck2ui 16
4220 23:42:02.221883 best dqsien dly found for B0: ( 0, 13, 12)
4221 23:42:02.225134 Total UI for P1: 0, mck2ui 16
4222 23:42:02.229030 best dqsien dly found for B1: ( 0, 13, 14)
4223 23:42:02.231694 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4224 23:42:02.235078 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4225 23:42:02.235198
4226 23:42:02.238333 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4227 23:42:02.241646 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4228 23:42:02.244803 [Gating] SW calibration Done
4229 23:42:02.244907 ==
4230 23:42:02.248271 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 23:42:02.251987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 23:42:02.254876 ==
4233 23:42:02.254957 RX Vref Scan: 0
4234 23:42:02.255022
4235 23:42:02.258052 RX Vref 0 -> 0, step: 1
4236 23:42:02.258158
4237 23:42:02.261760 RX Delay -230 -> 252, step: 16
4238 23:42:02.264939 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4239 23:42:02.267992 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4240 23:42:02.271473 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4241 23:42:02.278162 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4242 23:42:02.281556 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4243 23:42:02.284689 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4244 23:42:02.288014 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4245 23:42:02.291641 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4246 23:42:02.297677 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4247 23:42:02.300899 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4248 23:42:02.304513 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4249 23:42:02.307989 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4250 23:42:02.314253 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4251 23:42:02.317543 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4252 23:42:02.320966 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4253 23:42:02.324359 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4254 23:42:02.324478 ==
4255 23:42:02.327889 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 23:42:02.334119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 23:42:02.334242 ==
4258 23:42:02.334352 DQS Delay:
4259 23:42:02.337536 DQS0 = 0, DQS1 = 0
4260 23:42:02.337655 DQM Delay:
4261 23:42:02.340827 DQM0 = 39, DQM1 = 31
4262 23:42:02.340945 DQ Delay:
4263 23:42:02.344114 DQ0 =41, DQ1 =33, DQ2 =41, DQ3 =33
4264 23:42:02.347269 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4265 23:42:02.350504 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4266 23:42:02.353877 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4267 23:42:02.353997
4268 23:42:02.354107
4269 23:42:02.354218 ==
4270 23:42:02.357274 Dram Type= 6, Freq= 0, CH_0, rank 1
4271 23:42:02.360392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4272 23:42:02.360512 ==
4273 23:42:02.360657
4274 23:42:02.360765
4275 23:42:02.364188 TX Vref Scan disable
4276 23:42:02.367349 == TX Byte 0 ==
4277 23:42:02.370773 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4278 23:42:02.374054 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4279 23:42:02.377621 == TX Byte 1 ==
4280 23:42:02.380391 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4281 23:42:02.384026 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4282 23:42:02.384109 ==
4283 23:42:02.387104 Dram Type= 6, Freq= 0, CH_0, rank 1
4284 23:42:02.390750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4285 23:42:02.393580 ==
4286 23:42:02.393662
4287 23:42:02.393727
4288 23:42:02.393788 TX Vref Scan disable
4289 23:42:02.398033 == TX Byte 0 ==
4290 23:42:02.400921 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4291 23:42:02.407399 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4292 23:42:02.407482 == TX Byte 1 ==
4293 23:42:02.410846 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4294 23:42:02.417638 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4295 23:42:02.417721
4296 23:42:02.417790 [DATLAT]
4297 23:42:02.417852 Freq=600, CH0 RK1
4298 23:42:02.417912
4299 23:42:02.420692 DATLAT Default: 0x9
4300 23:42:02.424005 0, 0xFFFF, sum = 0
4301 23:42:02.424088 1, 0xFFFF, sum = 0
4302 23:42:02.427532 2, 0xFFFF, sum = 0
4303 23:42:02.427658 3, 0xFFFF, sum = 0
4304 23:42:02.430876 4, 0xFFFF, sum = 0
4305 23:42:02.431001 5, 0xFFFF, sum = 0
4306 23:42:02.434046 6, 0xFFFF, sum = 0
4307 23:42:02.434173 7, 0xFFFF, sum = 0
4308 23:42:02.437330 8, 0x0, sum = 1
4309 23:42:02.437456 9, 0x0, sum = 2
4310 23:42:02.440427 10, 0x0, sum = 3
4311 23:42:02.440548 11, 0x0, sum = 4
4312 23:42:02.440672 best_step = 9
4313 23:42:02.440784
4314 23:42:02.444326 ==
4315 23:42:02.444450 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 23:42:02.450838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 23:42:02.450964 ==
4318 23:42:02.451077 RX Vref Scan: 0
4319 23:42:02.451192
4320 23:42:02.454026 RX Vref 0 -> 0, step: 1
4321 23:42:02.454148
4322 23:42:02.457485 RX Delay -195 -> 252, step: 8
4323 23:42:02.464000 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4324 23:42:02.467383 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4325 23:42:02.470668 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4326 23:42:02.474206 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4327 23:42:02.477149 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4328 23:42:02.483559 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4329 23:42:02.487256 iDelay=205, Bit 6, Center 40 (-123 ~ 204) 328
4330 23:42:02.490378 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4331 23:42:02.494263 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4332 23:42:02.497203 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4333 23:42:02.503588 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4334 23:42:02.506840 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4335 23:42:02.510244 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4336 23:42:02.516843 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4337 23:42:02.519994 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4338 23:42:02.523535 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4339 23:42:02.523657 ==
4340 23:42:02.526973 Dram Type= 6, Freq= 0, CH_0, rank 1
4341 23:42:02.530051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 23:42:02.530175 ==
4343 23:42:02.533306 DQS Delay:
4344 23:42:02.533427 DQS0 = 0, DQS1 = 0
4345 23:42:02.536444 DQM Delay:
4346 23:42:02.536567 DQM0 = 33, DQM1 = 28
4347 23:42:02.536707 DQ Delay:
4348 23:42:02.539964 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4349 23:42:02.543295 DQ4 =32, DQ5 =20, DQ6 =40, DQ7 =44
4350 23:42:02.546800 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4351 23:42:02.549961 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4352 23:42:02.550099
4353 23:42:02.550191
4354 23:42:02.559744 [DQSOSCAuto] RK1, (LSB)MR18= 0x7240, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4355 23:42:02.563019 CH0 RK1: MR19=808, MR18=7240
4356 23:42:02.569606 CH0_RK1: MR19=0x808, MR18=0x7240, DQSOSC=388, MR23=63, INC=174, DEC=116
4357 23:42:02.569703 [RxdqsGatingPostProcess] freq 600
4358 23:42:02.576205 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4359 23:42:02.579808 Pre-setting of DQS Precalculation
4360 23:42:02.583171 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4361 23:42:02.586482 ==
4362 23:42:02.589664 Dram Type= 6, Freq= 0, CH_1, rank 0
4363 23:42:02.592861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 23:42:02.592938 ==
4365 23:42:02.596774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 23:42:02.603063 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4367 23:42:02.606918 [CA 0] Center 36 (6~66) winsize 61
4368 23:42:02.610405 [CA 1] Center 36 (6~66) winsize 61
4369 23:42:02.613232 [CA 2] Center 34 (4~65) winsize 62
4370 23:42:02.617062 [CA 3] Center 34 (3~65) winsize 63
4371 23:42:02.619919 [CA 4] Center 34 (4~65) winsize 62
4372 23:42:02.623236 [CA 5] Center 33 (3~64) winsize 62
4373 23:42:02.623319
4374 23:42:02.626689 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4375 23:42:02.626770
4376 23:42:02.630300 [CATrainingPosCal] consider 1 rank data
4377 23:42:02.633230 u2DelayCellTimex100 = 270/100 ps
4378 23:42:02.636694 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4379 23:42:02.643058 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4380 23:42:02.646671 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4381 23:42:02.649673 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4382 23:42:02.653263 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4383 23:42:02.656421 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4384 23:42:02.656502
4385 23:42:02.659830 CA PerBit enable=1, Macro0, CA PI delay=33
4386 23:42:02.659911
4387 23:42:02.663591 [CBTSetCACLKResult] CA Dly = 33
4388 23:42:02.663672 CS Dly: 4 (0~35)
4389 23:42:02.666671 ==
4390 23:42:02.669539 Dram Type= 6, Freq= 0, CH_1, rank 1
4391 23:42:02.673445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4392 23:42:02.673526 ==
4393 23:42:02.676186 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4394 23:42:02.683320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4395 23:42:02.687025 [CA 0] Center 36 (6~66) winsize 61
4396 23:42:02.690218 [CA 1] Center 35 (5~66) winsize 62
4397 23:42:02.693304 [CA 2] Center 34 (3~65) winsize 63
4398 23:42:02.696519 [CA 3] Center 34 (3~65) winsize 63
4399 23:42:02.700253 [CA 4] Center 34 (4~65) winsize 62
4400 23:42:02.703538 [CA 5] Center 33 (3~64) winsize 62
4401 23:42:02.703646
4402 23:42:02.706717 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4403 23:42:02.706800
4404 23:42:02.710061 [CATrainingPosCal] consider 2 rank data
4405 23:42:02.713417 u2DelayCellTimex100 = 270/100 ps
4406 23:42:02.716875 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4407 23:42:02.723416 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4408 23:42:02.726864 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4409 23:42:02.729644 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4410 23:42:02.733002 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4411 23:42:02.736204 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4412 23:42:02.736285
4413 23:42:02.739724 CA PerBit enable=1, Macro0, CA PI delay=33
4414 23:42:02.739831
4415 23:42:02.743122 [CBTSetCACLKResult] CA Dly = 33
4416 23:42:02.746810 CS Dly: 5 (0~38)
4417 23:42:02.746892
4418 23:42:02.749748 ----->DramcWriteLeveling(PI) begin...
4419 23:42:02.749848 ==
4420 23:42:02.753252 Dram Type= 6, Freq= 0, CH_1, rank 0
4421 23:42:02.756293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 23:42:02.756392 ==
4423 23:42:02.759771 Write leveling (Byte 0): 29 => 29
4424 23:42:02.762896 Write leveling (Byte 1): 30 => 30
4425 23:42:02.766485 DramcWriteLeveling(PI) end<-----
4426 23:42:02.766559
4427 23:42:02.766621 ==
4428 23:42:02.769684 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 23:42:02.772800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 23:42:02.772905 ==
4431 23:42:02.776267 [Gating] SW mode calibration
4432 23:42:02.782857 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4433 23:42:02.789309 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4434 23:42:02.792435 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4435 23:42:02.795807 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4436 23:42:02.802681 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4437 23:42:02.806101 0 9 12 | B1->B0 | 3232 3030 | 0 1 | (0 0) (1 1)
4438 23:42:02.809135 0 9 16 | B1->B0 | 2c2c 2626 | 0 0 | (0 0) (0 0)
4439 23:42:02.815598 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4440 23:42:02.819012 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4441 23:42:02.822386 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4442 23:42:02.829044 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 23:42:02.832333 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 23:42:02.835581 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 23:42:02.842372 0 10 12 | B1->B0 | 3030 2d2c | 0 1 | (0 0) (0 0)
4446 23:42:02.845644 0 10 16 | B1->B0 | 4040 4545 | 0 0 | (1 1) (0 0)
4447 23:42:02.848976 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 23:42:02.856031 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4449 23:42:02.859383 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 23:42:02.862991 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 23:42:02.869059 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 23:42:02.872274 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 23:42:02.875483 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4454 23:42:02.878692 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4455 23:42:02.885322 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 23:42:02.888805 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 23:42:02.895398 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 23:42:02.898651 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 23:42:02.901960 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 23:42:02.908810 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 23:42:02.911643 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 23:42:02.915326 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 23:42:02.921545 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 23:42:02.924921 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 23:42:02.928350 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 23:42:02.934991 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 23:42:02.938311 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 23:42:02.941659 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 23:42:02.948275 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4470 23:42:02.951249 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 23:42:02.954894 Total UI for P1: 0, mck2ui 16
4472 23:42:02.958121 best dqsien dly found for B0: ( 0, 13, 14)
4473 23:42:02.961061 Total UI for P1: 0, mck2ui 16
4474 23:42:02.964785 best dqsien dly found for B1: ( 0, 13, 12)
4475 23:42:02.968086 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4476 23:42:02.971372 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4477 23:42:02.971492
4478 23:42:02.974697 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4479 23:42:02.977807 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4480 23:42:02.981062 [Gating] SW calibration Done
4481 23:42:02.981182 ==
4482 23:42:02.984435 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 23:42:02.987895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 23:42:02.990889 ==
4485 23:42:02.991009 RX Vref Scan: 0
4486 23:42:02.991120
4487 23:42:02.994334 RX Vref 0 -> 0, step: 1
4488 23:42:02.994456
4489 23:42:02.997593 RX Delay -230 -> 252, step: 16
4490 23:42:03.001050 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4491 23:42:03.004093 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4492 23:42:03.007263 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4493 23:42:03.014034 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4494 23:42:03.017244 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4495 23:42:03.020653 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4496 23:42:03.024005 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4497 23:42:03.027185 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4498 23:42:03.033559 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4499 23:42:03.037419 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4500 23:42:03.040778 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4501 23:42:03.043572 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4502 23:42:03.050423 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4503 23:42:03.053797 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4504 23:42:03.057029 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4505 23:42:03.060220 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4506 23:42:03.060340 ==
4507 23:42:03.063430 Dram Type= 6, Freq= 0, CH_1, rank 0
4508 23:42:03.069977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4509 23:42:03.070098 ==
4510 23:42:03.070209 DQS Delay:
4511 23:42:03.073466 DQS0 = 0, DQS1 = 0
4512 23:42:03.073586 DQM Delay:
4513 23:42:03.076739 DQM0 = 38, DQM1 = 28
4514 23:42:03.076856 DQ Delay:
4515 23:42:03.080154 DQ0 =49, DQ1 =33, DQ2 =25, DQ3 =33
4516 23:42:03.083409 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4517 23:42:03.087054 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4518 23:42:03.090311 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4519 23:42:03.090432
4520 23:42:03.090543
4521 23:42:03.090653 ==
4522 23:42:03.093392 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 23:42:03.096870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 23:42:03.097004 ==
4525 23:42:03.097112
4526 23:42:03.097221
4527 23:42:03.100012 TX Vref Scan disable
4528 23:42:03.103146 == TX Byte 0 ==
4529 23:42:03.106576 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4530 23:42:03.109921 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4531 23:42:03.113325 == TX Byte 1 ==
4532 23:42:03.116453 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4533 23:42:03.120054 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4534 23:42:03.120175 ==
4535 23:42:03.123114 Dram Type= 6, Freq= 0, CH_1, rank 0
4536 23:42:03.129421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4537 23:42:03.129543 ==
4538 23:42:03.129656
4539 23:42:03.129764
4540 23:42:03.129871 TX Vref Scan disable
4541 23:42:03.133770 == TX Byte 0 ==
4542 23:42:03.137481 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4543 23:42:03.144060 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4544 23:42:03.144183 == TX Byte 1 ==
4545 23:42:03.147286 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4546 23:42:03.153479 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4547 23:42:03.153602
4548 23:42:03.153714 [DATLAT]
4549 23:42:03.153825 Freq=600, CH1 RK0
4550 23:42:03.153937
4551 23:42:03.156856 DATLAT Default: 0x9
4552 23:42:03.156974 0, 0xFFFF, sum = 0
4553 23:42:03.160739 1, 0xFFFF, sum = 0
4554 23:42:03.160860 2, 0xFFFF, sum = 0
4555 23:42:03.163905 3, 0xFFFF, sum = 0
4556 23:42:03.166705 4, 0xFFFF, sum = 0
4557 23:42:03.166827 5, 0xFFFF, sum = 0
4558 23:42:03.170126 6, 0xFFFF, sum = 0
4559 23:42:03.170247 7, 0xFFFF, sum = 0
4560 23:42:03.173491 8, 0x0, sum = 1
4561 23:42:03.173613 9, 0x0, sum = 2
4562 23:42:03.173725 10, 0x0, sum = 3
4563 23:42:03.176497 11, 0x0, sum = 4
4564 23:42:03.176632 best_step = 9
4565 23:42:03.176777
4566 23:42:03.176903 ==
4567 23:42:03.180128 Dram Type= 6, Freq= 0, CH_1, rank 0
4568 23:42:03.186844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4569 23:42:03.186967 ==
4570 23:42:03.187077 RX Vref Scan: 1
4571 23:42:03.187185
4572 23:42:03.189939 RX Vref 0 -> 0, step: 1
4573 23:42:03.190055
4574 23:42:03.193367 RX Delay -195 -> 252, step: 8
4575 23:42:03.193490
4576 23:42:03.196478 Set Vref, RX VrefLevel [Byte0]: 58
4577 23:42:03.199961 [Byte1]: 52
4578 23:42:03.200081
4579 23:42:03.203133 Final RX Vref Byte 0 = 58 to rank0
4580 23:42:03.206346 Final RX Vref Byte 1 = 52 to rank0
4581 23:42:03.209824 Final RX Vref Byte 0 = 58 to rank1
4582 23:42:03.213053 Final RX Vref Byte 1 = 52 to rank1==
4583 23:42:03.216462 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 23:42:03.219858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 23:42:03.219978 ==
4586 23:42:03.223032 DQS Delay:
4587 23:42:03.223152 DQS0 = 0, DQS1 = 0
4588 23:42:03.226328 DQM Delay:
4589 23:42:03.226446 DQM0 = 39, DQM1 = 27
4590 23:42:03.226555 DQ Delay:
4591 23:42:03.229888 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4592 23:42:03.233004 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =36
4593 23:42:03.236383 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4594 23:42:03.239476 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4595 23:42:03.239597
4596 23:42:03.239708
4597 23:42:03.249812 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
4598 23:42:03.253150 CH1 RK0: MR19=808, MR18=2B38
4599 23:42:03.259881 CH1_RK0: MR19=0x808, MR18=0x2B38, DQSOSC=399, MR23=63, INC=164, DEC=109
4600 23:42:03.260005
4601 23:42:03.262777 ----->DramcWriteLeveling(PI) begin...
4602 23:42:03.262899 ==
4603 23:42:03.266593 Dram Type= 6, Freq= 0, CH_1, rank 1
4604 23:42:03.269839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4605 23:42:03.269961 ==
4606 23:42:03.272568 Write leveling (Byte 0): 28 => 28
4607 23:42:03.275854 Write leveling (Byte 1): 32 => 32
4608 23:42:03.279250 DramcWriteLeveling(PI) end<-----
4609 23:42:03.279369
4610 23:42:03.279481 ==
4611 23:42:03.282643 Dram Type= 6, Freq= 0, CH_1, rank 1
4612 23:42:03.286099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4613 23:42:03.286223 ==
4614 23:42:03.289137 [Gating] SW mode calibration
4615 23:42:03.296145 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4616 23:42:03.302574 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4617 23:42:03.305787 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4618 23:42:03.309044 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4619 23:42:03.315899 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4620 23:42:03.319516 0 9 12 | B1->B0 | 3131 2c2c | 1 0 | (1 0) (0 0)
4621 23:42:03.322674 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4622 23:42:03.329400 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4623 23:42:03.332663 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4624 23:42:03.335889 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 23:42:03.342398 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 23:42:03.345543 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 23:42:03.349394 0 10 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
4628 23:42:03.355606 0 10 12 | B1->B0 | 2b2b 4444 | 0 0 | (0 0) (0 0)
4629 23:42:03.359068 0 10 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
4630 23:42:03.362296 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 23:42:03.368817 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4632 23:42:03.372039 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 23:42:03.375420 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 23:42:03.382259 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 23:42:03.385405 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 23:42:03.388817 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4637 23:42:03.395253 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 23:42:03.398750 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 23:42:03.402222 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 23:42:03.408661 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 23:42:03.412063 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 23:42:03.415470 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 23:42:03.422023 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 23:42:03.425310 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 23:42:03.428878 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 23:42:03.432210 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 23:42:03.438819 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 23:42:03.442144 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 23:42:03.445630 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 23:42:03.451953 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 23:42:03.455559 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 23:42:03.458728 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4653 23:42:03.461662 Total UI for P1: 0, mck2ui 16
4654 23:42:03.465178 best dqsien dly found for B0: ( 0, 13, 10)
4655 23:42:03.471938 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 23:42:03.472062 Total UI for P1: 0, mck2ui 16
4657 23:42:03.478348 best dqsien dly found for B1: ( 0, 13, 12)
4658 23:42:03.481812 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4659 23:42:03.485275 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4660 23:42:03.485398
4661 23:42:03.488480 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4662 23:42:03.491865 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4663 23:42:03.495331 [Gating] SW calibration Done
4664 23:42:03.495455 ==
4665 23:42:03.498664 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 23:42:03.501889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 23:42:03.502013 ==
4668 23:42:03.504988 RX Vref Scan: 0
4669 23:42:03.505110
4670 23:42:03.508413 RX Vref 0 -> 0, step: 1
4671 23:42:03.508537
4672 23:42:03.508656 RX Delay -230 -> 252, step: 16
4673 23:42:03.514734 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4674 23:42:03.518215 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4675 23:42:03.521371 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4676 23:42:03.524760 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4677 23:42:03.531557 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4678 23:42:03.535040 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4679 23:42:03.538421 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4680 23:42:03.541515 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4681 23:42:03.544890 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4682 23:42:03.551828 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4683 23:42:03.554531 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4684 23:42:03.557911 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4685 23:42:03.561313 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4686 23:42:03.567672 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4687 23:42:03.571169 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4688 23:42:03.574789 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4689 23:42:03.574872 ==
4690 23:42:03.577973 Dram Type= 6, Freq= 0, CH_1, rank 1
4691 23:42:03.581385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4692 23:42:03.584677 ==
4693 23:42:03.584758 DQS Delay:
4694 23:42:03.584822 DQS0 = 0, DQS1 = 0
4695 23:42:03.587940 DQM Delay:
4696 23:42:03.588020 DQM0 = 35, DQM1 = 29
4697 23:42:03.591306 DQ Delay:
4698 23:42:03.594208 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4699 23:42:03.594288 DQ4 =33, DQ5 =49, DQ6 =41, DQ7 =33
4700 23:42:03.597599 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4701 23:42:03.600863 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4702 23:42:03.604318
4703 23:42:03.604398
4704 23:42:03.604461 ==
4705 23:42:03.607756 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 23:42:03.610881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 23:42:03.610963 ==
4708 23:42:03.611026
4709 23:42:03.611085
4710 23:42:03.614227 TX Vref Scan disable
4711 23:42:03.614307 == TX Byte 0 ==
4712 23:42:03.621080 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4713 23:42:03.624696 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4714 23:42:03.624777 == TX Byte 1 ==
4715 23:42:03.630967 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4716 23:42:03.634228 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4717 23:42:03.634308 ==
4718 23:42:03.637797 Dram Type= 6, Freq= 0, CH_1, rank 1
4719 23:42:03.641196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4720 23:42:03.641277 ==
4721 23:42:03.641341
4722 23:42:03.641400
4723 23:42:03.644495 TX Vref Scan disable
4724 23:42:03.647550 == TX Byte 0 ==
4725 23:42:03.651075 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4726 23:42:03.654243 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4727 23:42:03.657529 == TX Byte 1 ==
4728 23:42:03.660775 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4729 23:42:03.667532 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4730 23:42:03.667612
4731 23:42:03.667676 [DATLAT]
4732 23:42:03.667736 Freq=600, CH1 RK1
4733 23:42:03.667794
4734 23:42:03.670804 DATLAT Default: 0x9
4735 23:42:03.670884 0, 0xFFFF, sum = 0
4736 23:42:03.674160 1, 0xFFFF, sum = 0
4737 23:42:03.674241 2, 0xFFFF, sum = 0
4738 23:42:03.677074 3, 0xFFFF, sum = 0
4739 23:42:03.680509 4, 0xFFFF, sum = 0
4740 23:42:03.680664 5, 0xFFFF, sum = 0
4741 23:42:03.683945 6, 0xFFFF, sum = 0
4742 23:42:03.684068 7, 0xFFFF, sum = 0
4743 23:42:03.687146 8, 0x0, sum = 1
4744 23:42:03.687267 9, 0x0, sum = 2
4745 23:42:03.687382 10, 0x0, sum = 3
4746 23:42:03.690790 11, 0x0, sum = 4
4747 23:42:03.690915 best_step = 9
4748 23:42:03.691028
4749 23:42:03.691133 ==
4750 23:42:03.694058 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 23:42:03.700293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 23:42:03.700414 ==
4753 23:42:03.700529 RX Vref Scan: 0
4754 23:42:03.700678
4755 23:42:03.703593 RX Vref 0 -> 0, step: 1
4756 23:42:03.703714
4757 23:42:03.707024 RX Delay -195 -> 252, step: 8
4758 23:42:03.710353 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4759 23:42:03.717028 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4760 23:42:03.720225 iDelay=205, Bit 2, Center 20 (-139 ~ 180) 320
4761 23:42:03.723259 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4762 23:42:03.727121 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4763 23:42:03.733122 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4764 23:42:03.736526 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4765 23:42:03.739761 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4766 23:42:03.743061 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4767 23:42:03.749960 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4768 23:42:03.753214 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4769 23:42:03.756685 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4770 23:42:03.759815 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4771 23:42:03.766624 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4772 23:42:03.769457 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4773 23:42:03.772960 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4774 23:42:03.773045 ==
4775 23:42:03.776503 Dram Type= 6, Freq= 0, CH_1, rank 1
4776 23:42:03.779393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4777 23:42:03.779479 ==
4778 23:42:03.782679 DQS Delay:
4779 23:42:03.782764 DQS0 = 0, DQS1 = 0
4780 23:42:03.785994 DQM Delay:
4781 23:42:03.786078 DQM0 = 35, DQM1 = 29
4782 23:42:03.786164 DQ Delay:
4783 23:42:03.789720 DQ0 =40, DQ1 =32, DQ2 =20, DQ3 =32
4784 23:42:03.793427 DQ4 =32, DQ5 =44, DQ6 =48, DQ7 =36
4785 23:42:03.796057 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4786 23:42:03.799641 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4787 23:42:03.799771
4788 23:42:03.799873
4789 23:42:03.809345 [DQSOSCAuto] RK1, (LSB)MR18= 0x3b59, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 398 ps
4790 23:42:03.812568 CH1 RK1: MR19=808, MR18=3B59
4791 23:42:03.819216 CH1_RK1: MR19=0x808, MR18=0x3B59, DQSOSC=393, MR23=63, INC=169, DEC=113
4792 23:42:03.822770 [RxdqsGatingPostProcess] freq 600
4793 23:42:03.826080 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4794 23:42:03.829414 Pre-setting of DQS Precalculation
4795 23:42:03.836134 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4796 23:42:03.842562 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4797 23:42:03.848863 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4798 23:42:03.848951
4799 23:42:03.849037
4800 23:42:03.852494 [Calibration Summary] 1200 Mbps
4801 23:42:03.852602 CH 0, Rank 0
4802 23:42:03.855665 SW Impedance : PASS
4803 23:42:03.858978 DUTY Scan : NO K
4804 23:42:03.859063 ZQ Calibration : PASS
4805 23:42:03.862348 Jitter Meter : NO K
4806 23:42:03.862433 CBT Training : PASS
4807 23:42:03.865591 Write leveling : PASS
4808 23:42:03.868819 RX DQS gating : PASS
4809 23:42:03.868904 RX DQ/DQS(RDDQC) : PASS
4810 23:42:03.872248 TX DQ/DQS : PASS
4811 23:42:03.875576 RX DATLAT : PASS
4812 23:42:03.875794 RX DQ/DQS(Engine): PASS
4813 23:42:03.878840 TX OE : NO K
4814 23:42:03.878966 All Pass.
4815 23:42:03.879048
4816 23:42:03.882296 CH 0, Rank 1
4817 23:42:03.882380 SW Impedance : PASS
4818 23:42:03.885666 DUTY Scan : NO K
4819 23:42:03.889005 ZQ Calibration : PASS
4820 23:42:03.889090 Jitter Meter : NO K
4821 23:42:03.892193 CBT Training : PASS
4822 23:42:03.895065 Write leveling : PASS
4823 23:42:03.895149 RX DQS gating : PASS
4824 23:42:03.898467 RX DQ/DQS(RDDQC) : PASS
4825 23:42:03.902151 TX DQ/DQS : PASS
4826 23:42:03.902236 RX DATLAT : PASS
4827 23:42:03.905292 RX DQ/DQS(Engine): PASS
4828 23:42:03.908304 TX OE : NO K
4829 23:42:03.908415 All Pass.
4830 23:42:03.908516
4831 23:42:03.908658 CH 1, Rank 0
4832 23:42:03.911715 SW Impedance : PASS
4833 23:42:03.915118 DUTY Scan : NO K
4834 23:42:03.915227 ZQ Calibration : PASS
4835 23:42:03.918411 Jitter Meter : NO K
4836 23:42:03.921699 CBT Training : PASS
4837 23:42:03.921779 Write leveling : PASS
4838 23:42:03.924879 RX DQS gating : PASS
4839 23:42:03.928319 RX DQ/DQS(RDDQC) : PASS
4840 23:42:03.928399 TX DQ/DQS : PASS
4841 23:42:03.931660 RX DATLAT : PASS
4842 23:42:03.931740 RX DQ/DQS(Engine): PASS
4843 23:42:03.934879 TX OE : NO K
4844 23:42:03.934959 All Pass.
4845 23:42:03.935023
4846 23:42:03.938389 CH 1, Rank 1
4847 23:42:03.938469 SW Impedance : PASS
4848 23:42:03.941265 DUTY Scan : NO K
4849 23:42:03.944917 ZQ Calibration : PASS
4850 23:42:03.944998 Jitter Meter : NO K
4851 23:42:03.948190 CBT Training : PASS
4852 23:42:03.951279 Write leveling : PASS
4853 23:42:03.951359 RX DQS gating : PASS
4854 23:42:03.954647 RX DQ/DQS(RDDQC) : PASS
4855 23:42:03.957940 TX DQ/DQS : PASS
4856 23:42:03.958020 RX DATLAT : PASS
4857 23:42:03.961381 RX DQ/DQS(Engine): PASS
4858 23:42:03.964269 TX OE : NO K
4859 23:42:03.964349 All Pass.
4860 23:42:03.964413
4861 23:42:03.967516 DramC Write-DBI off
4862 23:42:03.967596 PER_BANK_REFRESH: Hybrid Mode
4863 23:42:03.970830 TX_TRACKING: ON
4864 23:42:03.981059 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4865 23:42:03.984041 [FAST_K] Save calibration result to emmc
4866 23:42:03.987430 dramc_set_vcore_voltage set vcore to 662500
4867 23:42:03.987514 Read voltage for 933, 3
4868 23:42:03.991034 Vio18 = 0
4869 23:42:03.991132 Vcore = 662500
4870 23:42:03.991207 Vdram = 0
4871 23:42:03.994427 Vddq = 0
4872 23:42:03.994508 Vmddr = 0
4873 23:42:03.997388 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4874 23:42:04.003855 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4875 23:42:04.007427 MEM_TYPE=3, freq_sel=17
4876 23:42:04.010541 sv_algorithm_assistance_LP4_1600
4877 23:42:04.014077 ============ PULL DRAM RESETB DOWN ============
4878 23:42:04.017541 ========== PULL DRAM RESETB DOWN end =========
4879 23:42:04.023995 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4880 23:42:04.027412 ===================================
4881 23:42:04.027520 LPDDR4 DRAM CONFIGURATION
4882 23:42:04.030687 ===================================
4883 23:42:04.034052 EX_ROW_EN[0] = 0x0
4884 23:42:04.034149 EX_ROW_EN[1] = 0x0
4885 23:42:04.037353 LP4Y_EN = 0x0
4886 23:42:04.040774 WORK_FSP = 0x0
4887 23:42:04.040855 WL = 0x3
4888 23:42:04.043961 RL = 0x3
4889 23:42:04.044042 BL = 0x2
4890 23:42:04.047111 RPST = 0x0
4891 23:42:04.047193 RD_PRE = 0x0
4892 23:42:04.050560 WR_PRE = 0x1
4893 23:42:04.050641 WR_PST = 0x0
4894 23:42:04.053954 DBI_WR = 0x0
4895 23:42:04.054052 DBI_RD = 0x0
4896 23:42:04.057310 OTF = 0x1
4897 23:42:04.060353 ===================================
4898 23:42:04.063817 ===================================
4899 23:42:04.063899 ANA top config
4900 23:42:04.066991 ===================================
4901 23:42:04.070482 DLL_ASYNC_EN = 0
4902 23:42:04.073851 ALL_SLAVE_EN = 1
4903 23:42:04.073965 NEW_RANK_MODE = 1
4904 23:42:04.077175 DLL_IDLE_MODE = 1
4905 23:42:04.079992 LP45_APHY_COMB_EN = 1
4906 23:42:04.083420 TX_ODT_DIS = 1
4907 23:42:04.086600 NEW_8X_MODE = 1
4908 23:42:04.089924 ===================================
4909 23:42:04.093132 ===================================
4910 23:42:04.097013 data_rate = 1866
4911 23:42:04.097094 CKR = 1
4912 23:42:04.099991 DQ_P2S_RATIO = 8
4913 23:42:04.103308 ===================================
4914 23:42:04.106361 CA_P2S_RATIO = 8
4915 23:42:04.109588 DQ_CA_OPEN = 0
4916 23:42:04.112954 DQ_SEMI_OPEN = 0
4917 23:42:04.116160 CA_SEMI_OPEN = 0
4918 23:42:04.116241 CA_FULL_RATE = 0
4919 23:42:04.119578 DQ_CKDIV4_EN = 1
4920 23:42:04.123192 CA_CKDIV4_EN = 1
4921 23:42:04.126371 CA_PREDIV_EN = 0
4922 23:42:04.129424 PH8_DLY = 0
4923 23:42:04.132780 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4924 23:42:04.132861 DQ_AAMCK_DIV = 4
4925 23:42:04.135879 CA_AAMCK_DIV = 4
4926 23:42:04.139866 CA_ADMCK_DIV = 4
4927 23:42:04.143073 DQ_TRACK_CA_EN = 0
4928 23:42:04.145961 CA_PICK = 933
4929 23:42:04.149423 CA_MCKIO = 933
4930 23:42:04.152598 MCKIO_SEMI = 0
4931 23:42:04.152694 PLL_FREQ = 3732
4932 23:42:04.156035 DQ_UI_PI_RATIO = 32
4933 23:42:04.159124 CA_UI_PI_RATIO = 0
4934 23:42:04.162457 ===================================
4935 23:42:04.165621 ===================================
4936 23:42:04.169367 memory_type:LPDDR4
4937 23:42:04.169449 GP_NUM : 10
4938 23:42:04.172572 SRAM_EN : 1
4939 23:42:04.175703 MD32_EN : 0
4940 23:42:04.179468 ===================================
4941 23:42:04.179551 [ANA_INIT] >>>>>>>>>>>>>>
4942 23:42:04.182216 <<<<<< [CONFIGURE PHASE]: ANA_TX
4943 23:42:04.185618 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4944 23:42:04.188904 ===================================
4945 23:42:04.192342 data_rate = 1866,PCW = 0X8f00
4946 23:42:04.195620 ===================================
4947 23:42:04.199040 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4948 23:42:04.205795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4949 23:42:04.212121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4950 23:42:04.215288 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4951 23:42:04.218876 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4952 23:42:04.222128 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4953 23:42:04.225454 [ANA_INIT] flow start
4954 23:42:04.225562 [ANA_INIT] PLL >>>>>>>>
4955 23:42:04.228594 [ANA_INIT] PLL <<<<<<<<
4956 23:42:04.231915 [ANA_INIT] MIDPI >>>>>>>>
4957 23:42:04.232023 [ANA_INIT] MIDPI <<<<<<<<
4958 23:42:04.235078 [ANA_INIT] DLL >>>>>>>>
4959 23:42:04.238719 [ANA_INIT] flow end
4960 23:42:04.241894 ============ LP4 DIFF to SE enter ============
4961 23:42:04.245241 ============ LP4 DIFF to SE exit ============
4962 23:42:04.248689 [ANA_INIT] <<<<<<<<<<<<<
4963 23:42:04.251937 [Flow] Enable top DCM control >>>>>
4964 23:42:04.255260 [Flow] Enable top DCM control <<<<<
4965 23:42:04.258124 Enable DLL master slave shuffle
4966 23:42:04.261733 ==============================================================
4967 23:42:04.264652 Gating Mode config
4968 23:42:04.271979 ==============================================================
4969 23:42:04.272083 Config description:
4970 23:42:04.281614 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4971 23:42:04.288322 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4972 23:42:04.294507 SELPH_MODE 0: By rank 1: By Phase
4973 23:42:04.297863 ==============================================================
4974 23:42:04.301139 GAT_TRACK_EN = 1
4975 23:42:04.304527 RX_GATING_MODE = 2
4976 23:42:04.307908 RX_GATING_TRACK_MODE = 2
4977 23:42:04.311189 SELPH_MODE = 1
4978 23:42:04.314592 PICG_EARLY_EN = 1
4979 23:42:04.317653 VALID_LAT_VALUE = 1
4980 23:42:04.321163 ==============================================================
4981 23:42:04.324230 Enter into Gating configuration >>>>
4982 23:42:04.327443 Exit from Gating configuration <<<<
4983 23:42:04.331295 Enter into DVFS_PRE_config >>>>>
4984 23:42:04.344374 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4985 23:42:04.347449 Exit from DVFS_PRE_config <<<<<
4986 23:42:04.350710 Enter into PICG configuration >>>>
4987 23:42:04.353919 Exit from PICG configuration <<<<
4988 23:42:04.354018 [RX_INPUT] configuration >>>>>
4989 23:42:04.357724 [RX_INPUT] configuration <<<<<
4990 23:42:04.363965 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4991 23:42:04.367344 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4992 23:42:04.373859 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4993 23:42:04.380703 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4994 23:42:04.386940 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4995 23:42:04.393906 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4996 23:42:04.396978 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4997 23:42:04.400496 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4998 23:42:04.407226 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4999 23:42:04.410452 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5000 23:42:04.413996 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5001 23:42:04.417380 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5002 23:42:04.420611 ===================================
5003 23:42:04.423682 LPDDR4 DRAM CONFIGURATION
5004 23:42:04.426749 ===================================
5005 23:42:04.430299 EX_ROW_EN[0] = 0x0
5006 23:42:04.430384 EX_ROW_EN[1] = 0x0
5007 23:42:04.433939 LP4Y_EN = 0x0
5008 23:42:04.434023 WORK_FSP = 0x0
5009 23:42:04.436884 WL = 0x3
5010 23:42:04.436993 RL = 0x3
5011 23:42:04.440240 BL = 0x2
5012 23:42:04.440362 RPST = 0x0
5013 23:42:04.443522 RD_PRE = 0x0
5014 23:42:04.443647 WR_PRE = 0x1
5015 23:42:04.446783 WR_PST = 0x0
5016 23:42:04.446906 DBI_WR = 0x0
5017 23:42:04.450071 DBI_RD = 0x0
5018 23:42:04.453503 OTF = 0x1
5019 23:42:04.456800 ===================================
5020 23:42:04.459955 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5021 23:42:04.463303 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5022 23:42:04.466935 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5023 23:42:04.470109 ===================================
5024 23:42:04.473459 LPDDR4 DRAM CONFIGURATION
5025 23:42:04.476838 ===================================
5026 23:42:04.480163 EX_ROW_EN[0] = 0x10
5027 23:42:04.480245 EX_ROW_EN[1] = 0x0
5028 23:42:04.483616 LP4Y_EN = 0x0
5029 23:42:04.483696 WORK_FSP = 0x0
5030 23:42:04.486674 WL = 0x3
5031 23:42:04.486754 RL = 0x3
5032 23:42:04.489715 BL = 0x2
5033 23:42:04.489795 RPST = 0x0
5034 23:42:04.493502 RD_PRE = 0x0
5035 23:42:04.493582 WR_PRE = 0x1
5036 23:42:04.496447 WR_PST = 0x0
5037 23:42:04.496546 DBI_WR = 0x0
5038 23:42:04.499718 DBI_RD = 0x0
5039 23:42:04.502914 OTF = 0x1
5040 23:42:04.506314 ===================================
5041 23:42:04.509597 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5042 23:42:04.514713 nWR fixed to 30
5043 23:42:04.518414 [ModeRegInit_LP4] CH0 RK0
5044 23:42:04.518497 [ModeRegInit_LP4] CH0 RK1
5045 23:42:04.521255 [ModeRegInit_LP4] CH1 RK0
5046 23:42:04.524549 [ModeRegInit_LP4] CH1 RK1
5047 23:42:04.524654 match AC timing 9
5048 23:42:04.531429 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5049 23:42:04.534611 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5050 23:42:04.537746 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5051 23:42:04.544731 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5052 23:42:04.548158 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5053 23:42:04.548278 ==
5054 23:42:04.551381 Dram Type= 6, Freq= 0, CH_0, rank 0
5055 23:42:04.554673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5056 23:42:04.554809 ==
5057 23:42:04.561424 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5058 23:42:04.568056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5059 23:42:04.571300 [CA 0] Center 38 (8~69) winsize 62
5060 23:42:04.574673 [CA 1] Center 38 (7~69) winsize 63
5061 23:42:04.578165 [CA 2] Center 36 (6~66) winsize 61
5062 23:42:04.581540 [CA 3] Center 34 (4~65) winsize 62
5063 23:42:04.584932 [CA 4] Center 34 (4~65) winsize 62
5064 23:42:04.588135 [CA 5] Center 33 (3~64) winsize 62
5065 23:42:04.588215
5066 23:42:04.591255 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5067 23:42:04.591336
5068 23:42:04.594239 [CATrainingPosCal] consider 1 rank data
5069 23:42:04.598001 u2DelayCellTimex100 = 270/100 ps
5070 23:42:04.600982 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5071 23:42:04.604238 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5072 23:42:04.608014 CA2 delay=36 (6~66),Diff = 3 PI (18 cell)
5073 23:42:04.611184 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5074 23:42:04.614703 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5075 23:42:04.621081 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5076 23:42:04.621187
5077 23:42:04.624360 CA PerBit enable=1, Macro0, CA PI delay=33
5078 23:42:04.624477
5079 23:42:04.627683 [CBTSetCACLKResult] CA Dly = 33
5080 23:42:04.627764 CS Dly: 6 (0~37)
5081 23:42:04.627828 ==
5082 23:42:04.630965 Dram Type= 6, Freq= 0, CH_0, rank 1
5083 23:42:04.634138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5084 23:42:04.637843 ==
5085 23:42:04.640786 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5086 23:42:04.647788 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5087 23:42:04.650871 [CA 0] Center 38 (7~69) winsize 63
5088 23:42:04.654312 [CA 1] Center 38 (7~69) winsize 63
5089 23:42:04.657655 [CA 2] Center 35 (5~66) winsize 62
5090 23:42:04.661122 [CA 3] Center 35 (5~66) winsize 62
5091 23:42:04.664341 [CA 4] Center 34 (4~65) winsize 62
5092 23:42:04.667727 [CA 5] Center 33 (3~64) winsize 62
5093 23:42:04.667807
5094 23:42:04.671086 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5095 23:42:04.671166
5096 23:42:04.674361 [CATrainingPosCal] consider 2 rank data
5097 23:42:04.677400 u2DelayCellTimex100 = 270/100 ps
5098 23:42:04.681035 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5099 23:42:04.684292 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5100 23:42:04.687419 CA2 delay=36 (6~66),Diff = 3 PI (18 cell)
5101 23:42:04.690621 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5102 23:42:04.697352 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5103 23:42:04.700618 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5104 23:42:04.700699
5105 23:42:04.703881 CA PerBit enable=1, Macro0, CA PI delay=33
5106 23:42:04.703961
5107 23:42:04.707210 [CBTSetCACLKResult] CA Dly = 33
5108 23:42:04.707291 CS Dly: 7 (0~39)
5109 23:42:04.707354
5110 23:42:04.710546 ----->DramcWriteLeveling(PI) begin...
5111 23:42:04.710627 ==
5112 23:42:04.713914 Dram Type= 6, Freq= 0, CH_0, rank 0
5113 23:42:04.720478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5114 23:42:04.720569 ==
5115 23:42:04.723715 Write leveling (Byte 0): 30 => 30
5116 23:42:04.727226 Write leveling (Byte 1): 30 => 30
5117 23:42:04.727307 DramcWriteLeveling(PI) end<-----
5118 23:42:04.730075
5119 23:42:04.730157 ==
5120 23:42:04.733478 Dram Type= 6, Freq= 0, CH_0, rank 0
5121 23:42:04.736729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5122 23:42:04.736811 ==
5123 23:42:04.740259 [Gating] SW mode calibration
5124 23:42:04.746879 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5125 23:42:04.750250 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5126 23:42:04.756819 0 14 0 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
5127 23:42:04.759757 0 14 4 | B1->B0 | 2d2d 3434 | 1 1 | (0 0) (1 1)
5128 23:42:04.763564 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5129 23:42:04.769980 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5130 23:42:04.773339 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 23:42:04.776738 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 23:42:04.783256 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 23:42:04.786588 0 14 28 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5134 23:42:04.789948 0 15 0 | B1->B0 | 3434 2d2d | 0 0 | (1 0) (1 1)
5135 23:42:04.796511 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5136 23:42:04.799568 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5137 23:42:04.803369 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5138 23:42:04.809752 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 23:42:04.813202 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 23:42:04.816421 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 23:42:04.822888 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5142 23:42:04.825913 1 0 0 | B1->B0 | 2f2f 4242 | 0 0 | (0 0) (0 0)
5143 23:42:04.829458 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 23:42:04.835998 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 23:42:04.839372 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5146 23:42:04.842594 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 23:42:04.849123 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 23:42:04.852363 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 23:42:04.855785 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 23:42:04.862330 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5151 23:42:04.865931 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5152 23:42:04.869335 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 23:42:04.875733 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 23:42:04.879158 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 23:42:04.882581 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 23:42:04.888679 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 23:42:04.892081 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 23:42:04.895472 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 23:42:04.902116 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 23:42:04.905475 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 23:42:04.908631 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 23:42:04.915921 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 23:42:04.918500 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 23:42:04.921766 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 23:42:04.928300 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5166 23:42:04.931579 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5167 23:42:04.934960 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 23:42:04.938274 Total UI for P1: 0, mck2ui 16
5169 23:42:04.941504 best dqsien dly found for B0: ( 1, 2, 30)
5170 23:42:04.945030 Total UI for P1: 0, mck2ui 16
5171 23:42:04.948167 best dqsien dly found for B1: ( 1, 3, 2)
5172 23:42:04.951806 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5173 23:42:04.955208 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5174 23:42:04.955290
5175 23:42:04.961382 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5176 23:42:04.964741 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5177 23:42:04.964823 [Gating] SW calibration Done
5178 23:42:04.968415 ==
5179 23:42:04.968512 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 23:42:04.974698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 23:42:04.974781 ==
5182 23:42:04.974846 RX Vref Scan: 0
5183 23:42:04.974907
5184 23:42:04.978448 RX Vref 0 -> 0, step: 1
5185 23:42:04.978529
5186 23:42:04.981255 RX Delay -80 -> 252, step: 8
5187 23:42:04.984729 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5188 23:42:04.988080 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5189 23:42:04.991337 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5190 23:42:04.998140 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5191 23:42:05.001448 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5192 23:42:05.004322 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5193 23:42:05.007593 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5194 23:42:05.010954 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5195 23:42:05.014244 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5196 23:42:05.020968 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5197 23:42:05.024501 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5198 23:42:05.027811 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5199 23:42:05.031158 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5200 23:42:05.037759 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5201 23:42:05.040937 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5202 23:42:05.044687 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5203 23:42:05.044768 ==
5204 23:42:05.048029 Dram Type= 6, Freq= 0, CH_0, rank 0
5205 23:42:05.051291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5206 23:42:05.051374 ==
5207 23:42:05.054343 DQS Delay:
5208 23:42:05.054426 DQS0 = 0, DQS1 = 0
5209 23:42:05.054491 DQM Delay:
5210 23:42:05.057947 DQM0 = 93, DQM1 = 82
5211 23:42:05.058030 DQ Delay:
5212 23:42:05.061279 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5213 23:42:05.064623 DQ4 =95, DQ5 =79, DQ6 =99, DQ7 =103
5214 23:42:05.067840 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5215 23:42:05.071216 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =87
5216 23:42:05.071297
5217 23:42:05.071362
5218 23:42:05.071421 ==
5219 23:42:05.074569 Dram Type= 6, Freq= 0, CH_0, rank 0
5220 23:42:05.080616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5221 23:42:05.080698 ==
5222 23:42:05.080763
5223 23:42:05.080823
5224 23:42:05.080880 TX Vref Scan disable
5225 23:42:05.084906 == TX Byte 0 ==
5226 23:42:05.088154 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5227 23:42:05.094320 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5228 23:42:05.094428 == TX Byte 1 ==
5229 23:42:05.097782 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5230 23:42:05.104332 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5231 23:42:05.104414 ==
5232 23:42:05.107573 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 23:42:05.110955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 23:42:05.111037 ==
5235 23:42:05.111101
5236 23:42:05.111160
5237 23:42:05.114329 TX Vref Scan disable
5238 23:42:05.114409 == TX Byte 0 ==
5239 23:42:05.121109 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5240 23:42:05.124591 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5241 23:42:05.124686 == TX Byte 1 ==
5242 23:42:05.130835 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5243 23:42:05.134038 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5244 23:42:05.134119
5245 23:42:05.134182 [DATLAT]
5246 23:42:05.137365 Freq=933, CH0 RK0
5247 23:42:05.137446
5248 23:42:05.137509 DATLAT Default: 0xd
5249 23:42:05.140723 0, 0xFFFF, sum = 0
5250 23:42:05.140804 1, 0xFFFF, sum = 0
5251 23:42:05.144037 2, 0xFFFF, sum = 0
5252 23:42:05.144167 3, 0xFFFF, sum = 0
5253 23:42:05.147277 4, 0xFFFF, sum = 0
5254 23:42:05.150832 5, 0xFFFF, sum = 0
5255 23:42:05.150956 6, 0xFFFF, sum = 0
5256 23:42:05.154016 7, 0xFFFF, sum = 0
5257 23:42:05.154141 8, 0xFFFF, sum = 0
5258 23:42:05.157518 9, 0xFFFF, sum = 0
5259 23:42:05.157624 10, 0x0, sum = 1
5260 23:42:05.161206 11, 0x0, sum = 2
5261 23:42:05.161311 12, 0x0, sum = 3
5262 23:42:05.161404 13, 0x0, sum = 4
5263 23:42:05.163863 best_step = 11
5264 23:42:05.163970
5265 23:42:05.164056 ==
5266 23:42:05.167526 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 23:42:05.170844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 23:42:05.170926 ==
5269 23:42:05.174025 RX Vref Scan: 1
5270 23:42:05.174106
5271 23:42:05.177391 RX Vref 0 -> 0, step: 1
5272 23:42:05.177522
5273 23:42:05.177664 RX Delay -69 -> 252, step: 4
5274 23:42:05.177788
5275 23:42:05.180715 Set Vref, RX VrefLevel [Byte0]: 60
5276 23:42:05.183658 [Byte1]: 51
5277 23:42:05.188451
5278 23:42:05.188532 Final RX Vref Byte 0 = 60 to rank0
5279 23:42:05.191622 Final RX Vref Byte 1 = 51 to rank0
5280 23:42:05.195244 Final RX Vref Byte 0 = 60 to rank1
5281 23:42:05.198623 Final RX Vref Byte 1 = 51 to rank1==
5282 23:42:05.201956 Dram Type= 6, Freq= 0, CH_0, rank 0
5283 23:42:05.208704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 23:42:05.208786 ==
5285 23:42:05.208851 DQS Delay:
5286 23:42:05.211991 DQS0 = 0, DQS1 = 0
5287 23:42:05.212072 DQM Delay:
5288 23:42:05.212137 DQM0 = 95, DQM1 = 84
5289 23:42:05.214854 DQ Delay:
5290 23:42:05.218158 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5291 23:42:05.221494 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =106
5292 23:42:05.224929 DQ8 =78, DQ9 =70, DQ10 =84, DQ11 =80
5293 23:42:05.228192 DQ12 =88, DQ13 =86, DQ14 =98, DQ15 =90
5294 23:42:05.228320
5295 23:42:05.228387
5296 23:42:05.234673 [DQSOSCAuto] RK0, (LSB)MR18= 0x1918, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5297 23:42:05.238103 CH0 RK0: MR19=505, MR18=1918
5298 23:42:05.244669 CH0_RK0: MR19=0x505, MR18=0x1918, DQSOSC=413, MR23=63, INC=63, DEC=42
5299 23:42:05.244751
5300 23:42:05.248064 ----->DramcWriteLeveling(PI) begin...
5301 23:42:05.248146 ==
5302 23:42:05.251307 Dram Type= 6, Freq= 0, CH_0, rank 1
5303 23:42:05.254653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 23:42:05.254734 ==
5305 23:42:05.257972 Write leveling (Byte 0): 30 => 30
5306 23:42:05.261609 Write leveling (Byte 1): 29 => 29
5307 23:42:05.264991 DramcWriteLeveling(PI) end<-----
5308 23:42:05.265072
5309 23:42:05.265136 ==
5310 23:42:05.268720 Dram Type= 6, Freq= 0, CH_0, rank 1
5311 23:42:05.271660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 23:42:05.274728 ==
5313 23:42:05.274826 [Gating] SW mode calibration
5314 23:42:05.280896 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5315 23:42:05.287932 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5316 23:42:05.291444 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5317 23:42:05.297544 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5318 23:42:05.300935 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5319 23:42:05.304305 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5320 23:42:05.311040 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5321 23:42:05.313880 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 23:42:05.317677 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 23:42:05.324020 0 14 28 | B1->B0 | 3333 2d2d | 0 0 | (0 1) (1 1)
5324 23:42:05.327214 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5325 23:42:05.330688 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5326 23:42:05.337152 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5327 23:42:05.340913 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5328 23:42:05.344145 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 23:42:05.350269 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 23:42:05.353646 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 23:42:05.356968 0 15 28 | B1->B0 | 2525 3838 | 0 0 | (0 0) (0 0)
5332 23:42:05.363947 1 0 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5333 23:42:05.366806 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 23:42:05.370141 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 23:42:05.377258 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5336 23:42:05.380551 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 23:42:05.383887 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 23:42:05.390644 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 23:42:05.393784 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5340 23:42:05.397390 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5341 23:42:05.400529 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 23:42:05.406694 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 23:42:05.410207 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5344 23:42:05.413424 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 23:42:05.420275 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 23:42:05.423787 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 23:42:05.426671 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 23:42:05.433398 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 23:42:05.436845 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 23:42:05.440074 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 23:42:05.446621 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 23:42:05.449968 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 23:42:05.453190 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 23:42:05.460128 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5355 23:42:05.463401 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5356 23:42:05.466629 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5357 23:42:05.469872 Total UI for P1: 0, mck2ui 16
5358 23:42:05.472689 best dqsien dly found for B0: ( 1, 2, 26)
5359 23:42:05.479454 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 23:42:05.482844 Total UI for P1: 0, mck2ui 16
5361 23:42:05.486041 best dqsien dly found for B1: ( 1, 3, 0)
5362 23:42:05.489731 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5363 23:42:05.493014 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5364 23:42:05.493096
5365 23:42:05.496416 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5366 23:42:05.499700 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5367 23:42:05.502676 [Gating] SW calibration Done
5368 23:42:05.502757 ==
5369 23:42:05.506161 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 23:42:05.509317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 23:42:05.509398 ==
5372 23:42:05.512862 RX Vref Scan: 0
5373 23:42:05.512943
5374 23:42:05.513007 RX Vref 0 -> 0, step: 1
5375 23:42:05.515725
5376 23:42:05.515805 RX Delay -80 -> 252, step: 8
5377 23:42:05.522321 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5378 23:42:05.525778 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5379 23:42:05.529256 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5380 23:42:05.532414 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5381 23:42:05.535617 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5382 23:42:05.539097 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5383 23:42:05.545717 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5384 23:42:05.548899 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5385 23:42:05.552282 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5386 23:42:05.555614 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5387 23:42:05.559032 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5388 23:42:05.565756 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5389 23:42:05.569031 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5390 23:42:05.572326 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5391 23:42:05.575642 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5392 23:42:05.578788 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5393 23:42:05.578869 ==
5394 23:42:05.582140 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 23:42:05.588760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 23:42:05.588842 ==
5397 23:42:05.588907 DQS Delay:
5398 23:42:05.592026 DQS0 = 0, DQS1 = 0
5399 23:42:05.592107 DQM Delay:
5400 23:42:05.592171 DQM0 = 91, DQM1 = 84
5401 23:42:05.595275 DQ Delay:
5402 23:42:05.599057 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87
5403 23:42:05.602354 DQ4 =91, DQ5 =75, DQ6 =99, DQ7 =103
5404 23:42:05.605706 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =75
5405 23:42:05.608858 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =87
5406 23:42:05.608939
5407 23:42:05.609003
5408 23:42:05.609063 ==
5409 23:42:05.612036 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 23:42:05.615707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 23:42:05.615845 ==
5412 23:42:05.615942
5413 23:42:05.616033
5414 23:42:05.619099 TX Vref Scan disable
5415 23:42:05.619179 == TX Byte 0 ==
5416 23:42:05.625079 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5417 23:42:05.628493 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5418 23:42:05.632196 == TX Byte 1 ==
5419 23:42:05.635403 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5420 23:42:05.638426 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5421 23:42:05.638507 ==
5422 23:42:05.641543 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 23:42:05.645333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 23:42:05.645415 ==
5425 23:42:05.648196
5426 23:42:05.648276
5427 23:42:05.648339 TX Vref Scan disable
5428 23:42:05.651699 == TX Byte 0 ==
5429 23:42:05.654990 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5430 23:42:05.658810 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5431 23:42:05.661755 == TX Byte 1 ==
5432 23:42:05.665186 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5433 23:42:05.668613 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5434 23:42:05.671878
5435 23:42:05.671958 [DATLAT]
5436 23:42:05.672023 Freq=933, CH0 RK1
5437 23:42:05.672083
5438 23:42:05.675123 DATLAT Default: 0xb
5439 23:42:05.675204 0, 0xFFFF, sum = 0
5440 23:42:05.678482 1, 0xFFFF, sum = 0
5441 23:42:05.678565 2, 0xFFFF, sum = 0
5442 23:42:05.681657 3, 0xFFFF, sum = 0
5443 23:42:05.684988 4, 0xFFFF, sum = 0
5444 23:42:05.685071 5, 0xFFFF, sum = 0
5445 23:42:05.688552 6, 0xFFFF, sum = 0
5446 23:42:05.688656 7, 0xFFFF, sum = 0
5447 23:42:05.691771 8, 0xFFFF, sum = 0
5448 23:42:05.691853 9, 0xFFFF, sum = 0
5449 23:42:05.695089 10, 0x0, sum = 1
5450 23:42:05.695188 11, 0x0, sum = 2
5451 23:42:05.695291 12, 0x0, sum = 3
5452 23:42:05.698290 13, 0x0, sum = 4
5453 23:42:05.698372 best_step = 11
5454 23:42:05.698436
5455 23:42:05.701481 ==
5456 23:42:05.701577 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 23:42:05.708685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 23:42:05.708767 ==
5459 23:42:05.708831 RX Vref Scan: 0
5460 23:42:05.708891
5461 23:42:05.711489 RX Vref 0 -> 0, step: 1
5462 23:42:05.711569
5463 23:42:05.715368 RX Delay -77 -> 252, step: 4
5464 23:42:05.718194 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5465 23:42:05.724833 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5466 23:42:05.728014 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5467 23:42:05.731440 iDelay=199, Bit 3, Center 90 (-5 ~ 186) 192
5468 23:42:05.735267 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5469 23:42:05.738038 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5470 23:42:05.741739 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5471 23:42:05.748251 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5472 23:42:05.751601 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5473 23:42:05.754579 iDelay=199, Bit 9, Center 68 (-21 ~ 158) 180
5474 23:42:05.758087 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5475 23:42:05.761619 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5476 23:42:05.768249 iDelay=199, Bit 12, Center 88 (-5 ~ 182) 188
5477 23:42:05.771645 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5478 23:42:05.774830 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5479 23:42:05.778134 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5480 23:42:05.778215 ==
5481 23:42:05.781216 Dram Type= 6, Freq= 0, CH_0, rank 1
5482 23:42:05.787800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5483 23:42:05.787881 ==
5484 23:42:05.787946 DQS Delay:
5485 23:42:05.791226 DQS0 = 0, DQS1 = 0
5486 23:42:05.791307 DQM Delay:
5487 23:42:05.791371 DQM0 = 92, DQM1 = 83
5488 23:42:05.794450 DQ Delay:
5489 23:42:05.797844 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =90
5490 23:42:05.801211 DQ4 =90, DQ5 =80, DQ6 =104, DQ7 =102
5491 23:42:05.804342 DQ8 =76, DQ9 =68, DQ10 =86, DQ11 =76
5492 23:42:05.807478 DQ12 =88, DQ13 =88, DQ14 =96, DQ15 =90
5493 23:42:05.807562
5494 23:42:05.807626
5495 23:42:05.814124 [DQSOSCAuto] RK1, (LSB)MR18= 0x3213, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5496 23:42:05.817405 CH0 RK1: MR19=505, MR18=3213
5497 23:42:05.824115 CH0_RK1: MR19=0x505, MR18=0x3213, DQSOSC=406, MR23=63, INC=65, DEC=43
5498 23:42:05.827698 [RxdqsGatingPostProcess] freq 933
5499 23:42:05.830646 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5500 23:42:05.833937 best DQS0 dly(2T, 0.5T) = (0, 10)
5501 23:42:05.837487 best DQS1 dly(2T, 0.5T) = (0, 11)
5502 23:42:05.841013 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5503 23:42:05.844267 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5504 23:42:05.847601 best DQS0 dly(2T, 0.5T) = (0, 10)
5505 23:42:05.850677 best DQS1 dly(2T, 0.5T) = (0, 11)
5506 23:42:05.854049 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5507 23:42:05.857466 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5508 23:42:05.860503 Pre-setting of DQS Precalculation
5509 23:42:05.863932 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5510 23:42:05.867495 ==
5511 23:42:05.867576 Dram Type= 6, Freq= 0, CH_1, rank 0
5512 23:42:05.873887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 23:42:05.873969 ==
5514 23:42:05.877306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5515 23:42:05.883694 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5516 23:42:05.887641 [CA 0] Center 37 (7~67) winsize 61
5517 23:42:05.890845 [CA 1] Center 37 (7~68) winsize 62
5518 23:42:05.894193 [CA 2] Center 35 (6~64) winsize 59
5519 23:42:05.897538 [CA 3] Center 34 (4~64) winsize 61
5520 23:42:05.901086 [CA 4] Center 34 (5~64) winsize 60
5521 23:42:05.903830 [CA 5] Center 33 (4~63) winsize 60
5522 23:42:05.903912
5523 23:42:05.907127 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5524 23:42:05.907208
5525 23:42:05.911052 [CATrainingPosCal] consider 1 rank data
5526 23:42:05.913897 u2DelayCellTimex100 = 270/100 ps
5527 23:42:05.917351 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5528 23:42:05.924138 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5529 23:42:05.927014 CA2 delay=35 (6~64),Diff = 2 PI (12 cell)
5530 23:42:05.930267 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5531 23:42:05.933555 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5532 23:42:05.936990 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5533 23:42:05.937071
5534 23:42:05.940129 CA PerBit enable=1, Macro0, CA PI delay=33
5535 23:42:05.940211
5536 23:42:05.943763 [CBTSetCACLKResult] CA Dly = 33
5537 23:42:05.946956 CS Dly: 6 (0~37)
5538 23:42:05.947051 ==
5539 23:42:05.950333 Dram Type= 6, Freq= 0, CH_1, rank 1
5540 23:42:05.953388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 23:42:05.953472 ==
5542 23:42:05.959909 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5543 23:42:05.963703 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5544 23:42:05.967469 [CA 0] Center 37 (7~68) winsize 62
5545 23:42:05.970693 [CA 1] Center 37 (7~68) winsize 62
5546 23:42:05.974151 [CA 2] Center 35 (5~65) winsize 61
5547 23:42:05.977486 [CA 3] Center 34 (4~64) winsize 61
5548 23:42:05.980704 [CA 4] Center 35 (5~65) winsize 61
5549 23:42:05.983910 [CA 5] Center 33 (3~64) winsize 62
5550 23:42:05.984025
5551 23:42:05.987368 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5552 23:42:05.987450
5553 23:42:05.990879 [CATrainingPosCal] consider 2 rank data
5554 23:42:05.994032 u2DelayCellTimex100 = 270/100 ps
5555 23:42:05.997129 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5556 23:42:06.003662 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5557 23:42:06.007019 CA2 delay=35 (6~64),Diff = 2 PI (12 cell)
5558 23:42:06.010954 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5559 23:42:06.013722 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5560 23:42:06.017125 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5561 23:42:06.017206
5562 23:42:06.020705 CA PerBit enable=1, Macro0, CA PI delay=33
5563 23:42:06.020786
5564 23:42:06.023570 [CBTSetCACLKResult] CA Dly = 33
5565 23:42:06.023651 CS Dly: 6 (0~38)
5566 23:42:06.027347
5567 23:42:06.030654 ----->DramcWriteLeveling(PI) begin...
5568 23:42:06.030737 ==
5569 23:42:06.034008 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 23:42:06.037359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5571 23:42:06.037441 ==
5572 23:42:06.040569 Write leveling (Byte 0): 25 => 25
5573 23:42:06.043586 Write leveling (Byte 1): 31 => 31
5574 23:42:06.047048 DramcWriteLeveling(PI) end<-----
5575 23:42:06.047129
5576 23:42:06.047192 ==
5577 23:42:06.050551 Dram Type= 6, Freq= 0, CH_1, rank 0
5578 23:42:06.053697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 23:42:06.053778 ==
5580 23:42:06.056776 [Gating] SW mode calibration
5581 23:42:06.063503 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5582 23:42:06.070402 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5583 23:42:06.073616 0 14 0 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)
5584 23:42:06.076974 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5585 23:42:06.083640 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5586 23:42:06.086825 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5587 23:42:06.090487 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 23:42:06.097113 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 23:42:06.100384 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 23:42:06.103928 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5591 23:42:06.107084 0 15 0 | B1->B0 | 2727 2424 | 0 0 | (0 0) (1 0)
5592 23:42:06.113870 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5593 23:42:06.117037 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5594 23:42:06.120368 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 23:42:06.126881 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 23:42:06.129990 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 23:42:06.133437 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 23:42:06.140208 0 15 28 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (0 0)
5599 23:42:06.143605 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5600 23:42:06.146884 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 23:42:06.153521 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5602 23:42:06.156533 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 23:42:06.159998 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 23:42:06.166461 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 23:42:06.169614 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5606 23:42:06.173091 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5607 23:42:06.180103 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5608 23:42:06.183270 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5609 23:42:06.186370 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5610 23:42:06.193035 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5611 23:42:06.196401 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 23:42:06.199877 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 23:42:06.206218 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 23:42:06.209773 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 23:42:06.212828 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 23:42:06.219622 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 23:42:06.222825 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 23:42:06.226216 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 23:42:06.232591 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 23:42:06.236307 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 23:42:06.239204 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 23:42:06.245950 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5623 23:42:06.249255 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 23:42:06.252490 Total UI for P1: 0, mck2ui 16
5625 23:42:06.255875 best dqsien dly found for B0: ( 1, 2, 28)
5626 23:42:06.259158 Total UI for P1: 0, mck2ui 16
5627 23:42:06.262628 best dqsien dly found for B1: ( 1, 2, 28)
5628 23:42:06.266074 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5629 23:42:06.269094 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5630 23:42:06.269176
5631 23:42:06.272292 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5632 23:42:06.275842 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5633 23:42:06.278934 [Gating] SW calibration Done
5634 23:42:06.279042 ==
5635 23:42:06.282246 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 23:42:06.285740 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 23:42:06.289008 ==
5638 23:42:06.289090 RX Vref Scan: 0
5639 23:42:06.289154
5640 23:42:06.292415 RX Vref 0 -> 0, step: 1
5641 23:42:06.292496
5642 23:42:06.295748 RX Delay -80 -> 252, step: 8
5643 23:42:06.299185 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5644 23:42:06.302314 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5645 23:42:06.305479 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5646 23:42:06.308501 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5647 23:42:06.315330 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5648 23:42:06.318430 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5649 23:42:06.322201 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5650 23:42:06.325553 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5651 23:42:06.328884 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5652 23:42:06.331708 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5653 23:42:06.338632 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5654 23:42:06.341778 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5655 23:42:06.345106 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5656 23:42:06.348427 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5657 23:42:06.352128 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5658 23:42:06.358796 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5659 23:42:06.358869 ==
5660 23:42:06.361755 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 23:42:06.365348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 23:42:06.365430 ==
5663 23:42:06.365495 DQS Delay:
5664 23:42:06.368519 DQS0 = 0, DQS1 = 0
5665 23:42:06.368629 DQM Delay:
5666 23:42:06.371618 DQM0 = 94, DQM1 = 85
5667 23:42:06.371715 DQ Delay:
5668 23:42:06.374987 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5669 23:42:06.378418 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5670 23:42:06.381801 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =83
5671 23:42:06.385147 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5672 23:42:06.385263
5673 23:42:06.385372
5674 23:42:06.385473 ==
5675 23:42:06.388308 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 23:42:06.391897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 23:42:06.392001 ==
5678 23:42:06.395356
5679 23:42:06.395472
5680 23:42:06.395568 TX Vref Scan disable
5681 23:42:06.398379 == TX Byte 0 ==
5682 23:42:06.401619 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5683 23:42:06.405162 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5684 23:42:06.408174 == TX Byte 1 ==
5685 23:42:06.411475 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5686 23:42:06.414961 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5687 23:42:06.415047 ==
5688 23:42:06.418102 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 23:42:06.424813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 23:42:06.424938 ==
5691 23:42:06.425034
5692 23:42:06.425124
5693 23:42:06.428189 TX Vref Scan disable
5694 23:42:06.428284 == TX Byte 0 ==
5695 23:42:06.434901 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5696 23:42:06.438239 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5697 23:42:06.438312 == TX Byte 1 ==
5698 23:42:06.444875 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5699 23:42:06.447931 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5700 23:42:06.448006
5701 23:42:06.448069 [DATLAT]
5702 23:42:06.451195 Freq=933, CH1 RK0
5703 23:42:06.451266
5704 23:42:06.451327 DATLAT Default: 0xd
5705 23:42:06.454572 0, 0xFFFF, sum = 0
5706 23:42:06.454643 1, 0xFFFF, sum = 0
5707 23:42:06.458100 2, 0xFFFF, sum = 0
5708 23:42:06.458201 3, 0xFFFF, sum = 0
5709 23:42:06.461247 4, 0xFFFF, sum = 0
5710 23:42:06.461324 5, 0xFFFF, sum = 0
5711 23:42:06.464841 6, 0xFFFF, sum = 0
5712 23:42:06.464912 7, 0xFFFF, sum = 0
5713 23:42:06.468078 8, 0xFFFF, sum = 0
5714 23:42:06.468179 9, 0xFFFF, sum = 0
5715 23:42:06.471363 10, 0x0, sum = 1
5716 23:42:06.471462 11, 0x0, sum = 2
5717 23:42:06.474668 12, 0x0, sum = 3
5718 23:42:06.474817 13, 0x0, sum = 4
5719 23:42:06.477957 best_step = 11
5720 23:42:06.478049
5721 23:42:06.478138 ==
5722 23:42:06.480765 Dram Type= 6, Freq= 0, CH_1, rank 0
5723 23:42:06.484242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5724 23:42:06.484343 ==
5725 23:42:06.487637 RX Vref Scan: 1
5726 23:42:06.487709
5727 23:42:06.487774 RX Vref 0 -> 0, step: 1
5728 23:42:06.487861
5729 23:42:06.490926 RX Delay -69 -> 252, step: 4
5730 23:42:06.491029
5731 23:42:06.494261 Set Vref, RX VrefLevel [Byte0]: 58
5732 23:42:06.497556 [Byte1]: 52
5733 23:42:06.501736
5734 23:42:06.501836 Final RX Vref Byte 0 = 58 to rank0
5735 23:42:06.505413 Final RX Vref Byte 1 = 52 to rank0
5736 23:42:06.508421 Final RX Vref Byte 0 = 58 to rank1
5737 23:42:06.511825 Final RX Vref Byte 1 = 52 to rank1==
5738 23:42:06.515129 Dram Type= 6, Freq= 0, CH_1, rank 0
5739 23:42:06.521555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 23:42:06.521675 ==
5741 23:42:06.521742 DQS Delay:
5742 23:42:06.524648 DQS0 = 0, DQS1 = 0
5743 23:42:06.524736 DQM Delay:
5744 23:42:06.524798 DQM0 = 97, DQM1 = 88
5745 23:42:06.527944 DQ Delay:
5746 23:42:06.531606 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =94
5747 23:42:06.534841 DQ4 =94, DQ5 =106, DQ6 =110, DQ7 =94
5748 23:42:06.538276 DQ8 =76, DQ9 =82, DQ10 =88, DQ11 =82
5749 23:42:06.541665 DQ12 =98, DQ13 =94, DQ14 =96, DQ15 =94
5750 23:42:06.541763
5751 23:42:06.541829
5752 23:42:06.548370 [DQSOSCAuto] RK0, (LSB)MR18= 0x70f, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 419 ps
5753 23:42:06.551471 CH1 RK0: MR19=505, MR18=70F
5754 23:42:06.558143 CH1_RK0: MR19=0x505, MR18=0x70F, DQSOSC=417, MR23=63, INC=62, DEC=41
5755 23:42:06.558247
5756 23:42:06.561347 ----->DramcWriteLeveling(PI) begin...
5757 23:42:06.561425 ==
5758 23:42:06.564710 Dram Type= 6, Freq= 0, CH_1, rank 1
5759 23:42:06.567996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5760 23:42:06.568068 ==
5761 23:42:06.571348 Write leveling (Byte 0): 27 => 27
5762 23:42:06.574860 Write leveling (Byte 1): 29 => 29
5763 23:42:06.578087 DramcWriteLeveling(PI) end<-----
5764 23:42:06.578184
5765 23:42:06.578273 ==
5766 23:42:06.581334 Dram Type= 6, Freq= 0, CH_1, rank 1
5767 23:42:06.584807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 23:42:06.584885 ==
5769 23:42:06.587957 [Gating] SW mode calibration
5770 23:42:06.594606 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5771 23:42:06.600990 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5772 23:42:06.604315 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5773 23:42:06.611244 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5774 23:42:06.614514 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5775 23:42:06.617631 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 23:42:06.624439 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 23:42:06.627577 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 23:42:06.630736 0 14 24 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (1 1)
5779 23:42:06.637515 0 14 28 | B1->B0 | 2929 2323 | 1 0 | (1 0) (1 0)
5780 23:42:06.640716 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5781 23:42:06.643944 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5782 23:42:06.647337 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5783 23:42:06.653997 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 23:42:06.657768 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 23:42:06.660688 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 23:42:06.667262 0 15 24 | B1->B0 | 2424 3030 | 0 1 | (0 0) (0 0)
5787 23:42:06.670683 0 15 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5788 23:42:06.673943 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5789 23:42:06.680443 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 23:42:06.684373 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5791 23:42:06.687694 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 23:42:06.693765 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 23:42:06.697431 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 23:42:06.700698 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5795 23:42:06.707365 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5796 23:42:06.710503 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 23:42:06.713904 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5798 23:42:06.720543 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5799 23:42:06.723961 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 23:42:06.727358 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 23:42:06.733862 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 23:42:06.736911 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 23:42:06.740355 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 23:42:06.746652 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 23:42:06.750052 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 23:42:06.753341 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 23:42:06.759791 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 23:42:06.763107 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 23:42:06.766727 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 23:42:06.773776 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5811 23:42:06.776703 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 23:42:06.779574 Total UI for P1: 0, mck2ui 16
5813 23:42:06.783306 best dqsien dly found for B0: ( 1, 2, 24)
5814 23:42:06.786406 Total UI for P1: 0, mck2ui 16
5815 23:42:06.789644 best dqsien dly found for B1: ( 1, 2, 26)
5816 23:42:06.793040 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5817 23:42:06.796319 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5818 23:42:06.796457
5819 23:42:06.799650 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5820 23:42:06.802814 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5821 23:42:06.806110 [Gating] SW calibration Done
5822 23:42:06.806211 ==
5823 23:42:06.809668 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 23:42:06.816064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 23:42:06.816172 ==
5826 23:42:06.816265 RX Vref Scan: 0
5827 23:42:06.816376
5828 23:42:06.819671 RX Vref 0 -> 0, step: 1
5829 23:42:06.819759
5830 23:42:06.823096 RX Delay -80 -> 252, step: 8
5831 23:42:06.825880 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5832 23:42:06.829222 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5833 23:42:06.833088 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5834 23:42:06.835930 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5835 23:42:06.842815 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5836 23:42:06.845799 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5837 23:42:06.849612 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5838 23:42:06.852738 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5839 23:42:06.855898 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5840 23:42:06.862345 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5841 23:42:06.865674 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5842 23:42:06.868966 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5843 23:42:06.872326 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5844 23:42:06.875574 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5845 23:42:06.879220 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5846 23:42:06.885327 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5847 23:42:06.885437 ==
5848 23:42:06.888845 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 23:42:06.892048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 23:42:06.892176 ==
5851 23:42:06.892293 DQS Delay:
5852 23:42:06.895430 DQS0 = 0, DQS1 = 0
5853 23:42:06.895557 DQM Delay:
5854 23:42:06.898728 DQM0 = 93, DQM1 = 88
5855 23:42:06.898853 DQ Delay:
5856 23:42:06.902038 DQ0 =95, DQ1 =87, DQ2 =83, DQ3 =91
5857 23:42:06.905492 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5858 23:42:06.908868 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5859 23:42:06.912067 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5860 23:42:06.912193
5861 23:42:06.912307
5862 23:42:06.912419 ==
5863 23:42:06.915598 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 23:42:06.918323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 23:42:06.921548 ==
5866 23:42:06.921673
5867 23:42:06.921781
5868 23:42:06.921885 TX Vref Scan disable
5869 23:42:06.924968 == TX Byte 0 ==
5870 23:42:06.928830 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5871 23:42:06.931602 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5872 23:42:06.935327 == TX Byte 1 ==
5873 23:42:06.938315 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5874 23:42:06.941770 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5875 23:42:06.944924 ==
5876 23:42:06.948159 Dram Type= 6, Freq= 0, CH_1, rank 1
5877 23:42:06.951529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5878 23:42:06.951658 ==
5879 23:42:06.951775
5880 23:42:06.951889
5881 23:42:06.954745 TX Vref Scan disable
5882 23:42:06.954869 == TX Byte 0 ==
5883 23:42:06.961480 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5884 23:42:06.964494 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5885 23:42:06.964630 == TX Byte 1 ==
5886 23:42:06.971584 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5887 23:42:06.974816 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5888 23:42:06.974902
5889 23:42:06.974969 [DATLAT]
5890 23:42:06.978151 Freq=933, CH1 RK1
5891 23:42:06.978234
5892 23:42:06.978300 DATLAT Default: 0xb
5893 23:42:06.981216 0, 0xFFFF, sum = 0
5894 23:42:06.981301 1, 0xFFFF, sum = 0
5895 23:42:06.984640 2, 0xFFFF, sum = 0
5896 23:42:06.984724 3, 0xFFFF, sum = 0
5897 23:42:06.987957 4, 0xFFFF, sum = 0
5898 23:42:06.991124 5, 0xFFFF, sum = 0
5899 23:42:06.991236 6, 0xFFFF, sum = 0
5900 23:42:06.994251 7, 0xFFFF, sum = 0
5901 23:42:06.994358 8, 0xFFFF, sum = 0
5902 23:42:06.997523 9, 0xFFFF, sum = 0
5903 23:42:06.997633 10, 0x0, sum = 1
5904 23:42:07.000888 11, 0x0, sum = 2
5905 23:42:07.000976 12, 0x0, sum = 3
5906 23:42:07.004211 13, 0x0, sum = 4
5907 23:42:07.004296 best_step = 11
5908 23:42:07.004362
5909 23:42:07.004424 ==
5910 23:42:07.007704 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 23:42:07.010965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 23:42:07.011051 ==
5913 23:42:07.014412 RX Vref Scan: 0
5914 23:42:07.014495
5915 23:42:07.017634 RX Vref 0 -> 0, step: 1
5916 23:42:07.017717
5917 23:42:07.017783 RX Delay -69 -> 252, step: 4
5918 23:42:07.025443 iDelay=203, Bit 0, Center 94 (-5 ~ 194) 200
5919 23:42:07.029099 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5920 23:42:07.032006 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5921 23:42:07.035649 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5922 23:42:07.038936 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5923 23:42:07.045586 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5924 23:42:07.048666 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5925 23:42:07.051826 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5926 23:42:07.055310 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5927 23:42:07.058769 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5928 23:42:07.061939 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5929 23:42:07.068427 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
5930 23:42:07.071769 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5931 23:42:07.075285 iDelay=203, Bit 13, Center 96 (3 ~ 190) 188
5932 23:42:07.078550 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5933 23:42:07.081950 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5934 23:42:07.082079 ==
5935 23:42:07.084827 Dram Type= 6, Freq= 0, CH_1, rank 1
5936 23:42:07.091557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5937 23:42:07.091694 ==
5938 23:42:07.091811 DQS Delay:
5939 23:42:07.094875 DQS0 = 0, DQS1 = 0
5940 23:42:07.095002 DQM Delay:
5941 23:42:07.095117 DQM0 = 91, DQM1 = 90
5942 23:42:07.098311 DQ Delay:
5943 23:42:07.101619 DQ0 =94, DQ1 =86, DQ2 =82, DQ3 =88
5944 23:42:07.104810 DQ4 =88, DQ5 =102, DQ6 =104, DQ7 =88
5945 23:42:07.108252 DQ8 =78, DQ9 =80, DQ10 =92, DQ11 =82
5946 23:42:07.111443 DQ12 =98, DQ13 =96, DQ14 =98, DQ15 =96
5947 23:42:07.111533
5948 23:42:07.111619
5949 23:42:07.117953 [DQSOSCAuto] RK1, (LSB)MR18= 0x1225, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
5950 23:42:07.121521 CH1 RK1: MR19=505, MR18=1225
5951 23:42:07.128139 CH1_RK1: MR19=0x505, MR18=0x1225, DQSOSC=410, MR23=63, INC=64, DEC=42
5952 23:42:07.131540 [RxdqsGatingPostProcess] freq 933
5953 23:42:07.137797 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5954 23:42:07.137877 best DQS0 dly(2T, 0.5T) = (0, 10)
5955 23:42:07.141305 best DQS1 dly(2T, 0.5T) = (0, 10)
5956 23:42:07.144462 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5957 23:42:07.147817 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5958 23:42:07.151207 best DQS0 dly(2T, 0.5T) = (0, 10)
5959 23:42:07.154472 best DQS1 dly(2T, 0.5T) = (0, 10)
5960 23:42:07.157957 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5961 23:42:07.161144 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5962 23:42:07.164452 Pre-setting of DQS Precalculation
5963 23:42:07.170922 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5964 23:42:07.177666 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5965 23:42:07.185553 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5966 23:42:07.185676
5967 23:42:07.185777
5968 23:42:07.187934 [Calibration Summary] 1866 Mbps
5969 23:42:07.188046 CH 0, Rank 0
5970 23:42:07.190634 SW Impedance : PASS
5971 23:42:07.194364 DUTY Scan : NO K
5972 23:42:07.194475 ZQ Calibration : PASS
5973 23:42:07.197727 Jitter Meter : NO K
5974 23:42:07.197816 CBT Training : PASS
5975 23:42:07.201060 Write leveling : PASS
5976 23:42:07.204236 RX DQS gating : PASS
5977 23:42:07.204319 RX DQ/DQS(RDDQC) : PASS
5978 23:42:07.207761 TX DQ/DQS : PASS
5979 23:42:07.210956 RX DATLAT : PASS
5980 23:42:07.211041 RX DQ/DQS(Engine): PASS
5981 23:42:07.214541 TX OE : NO K
5982 23:42:07.214627 All Pass.
5983 23:42:07.214712
5984 23:42:07.217731 CH 0, Rank 1
5985 23:42:07.217815 SW Impedance : PASS
5986 23:42:07.220847 DUTY Scan : NO K
5987 23:42:07.224105 ZQ Calibration : PASS
5988 23:42:07.224184 Jitter Meter : NO K
5989 23:42:07.227320 CBT Training : PASS
5990 23:42:07.230628 Write leveling : PASS
5991 23:42:07.230713 RX DQS gating : PASS
5992 23:42:07.233949 RX DQ/DQS(RDDQC) : PASS
5993 23:42:07.237223 TX DQ/DQS : PASS
5994 23:42:07.237308 RX DATLAT : PASS
5995 23:42:07.240531 RX DQ/DQS(Engine): PASS
5996 23:42:07.243870 TX OE : NO K
5997 23:42:07.243955 All Pass.
5998 23:42:07.244040
5999 23:42:07.244121 CH 1, Rank 0
6000 23:42:07.247430 SW Impedance : PASS
6001 23:42:07.250501 DUTY Scan : NO K
6002 23:42:07.250586 ZQ Calibration : PASS
6003 23:42:07.253783 Jitter Meter : NO K
6004 23:42:07.257186 CBT Training : PASS
6005 23:42:07.257271 Write leveling : PASS
6006 23:42:07.260485 RX DQS gating : PASS
6007 23:42:07.260599 RX DQ/DQS(RDDQC) : PASS
6008 23:42:07.263918 TX DQ/DQS : PASS
6009 23:42:07.267031 RX DATLAT : PASS
6010 23:42:07.267116 RX DQ/DQS(Engine): PASS
6011 23:42:07.270562 TX OE : NO K
6012 23:42:07.270647 All Pass.
6013 23:42:07.270732
6014 23:42:07.273685 CH 1, Rank 1
6015 23:42:07.273775 SW Impedance : PASS
6016 23:42:07.276938 DUTY Scan : NO K
6017 23:42:07.280075 ZQ Calibration : PASS
6018 23:42:07.280159 Jitter Meter : NO K
6019 23:42:07.283684 CBT Training : PASS
6020 23:42:07.286990 Write leveling : PASS
6021 23:42:07.287075 RX DQS gating : PASS
6022 23:42:07.290194 RX DQ/DQS(RDDQC) : PASS
6023 23:42:07.293558 TX DQ/DQS : PASS
6024 23:42:07.293642 RX DATLAT : PASS
6025 23:42:07.296843 RX DQ/DQS(Engine): PASS
6026 23:42:07.300477 TX OE : NO K
6027 23:42:07.300593 All Pass.
6028 23:42:07.300678
6029 23:42:07.300758 DramC Write-DBI off
6030 23:42:07.303295 PER_BANK_REFRESH: Hybrid Mode
6031 23:42:07.306699 TX_TRACKING: ON
6032 23:42:07.313246 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6033 23:42:07.317014 [FAST_K] Save calibration result to emmc
6034 23:42:07.323587 dramc_set_vcore_voltage set vcore to 650000
6035 23:42:07.323704 Read voltage for 400, 6
6036 23:42:07.326633 Vio18 = 0
6037 23:42:07.326709 Vcore = 650000
6038 23:42:07.326773 Vdram = 0
6039 23:42:07.330085 Vddq = 0
6040 23:42:07.330161 Vmddr = 0
6041 23:42:07.333797 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6042 23:42:07.339961 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6043 23:42:07.343240 MEM_TYPE=3, freq_sel=20
6044 23:42:07.346836 sv_algorithm_assistance_LP4_800
6045 23:42:07.350043 ============ PULL DRAM RESETB DOWN ============
6046 23:42:07.353062 ========== PULL DRAM RESETB DOWN end =========
6047 23:42:07.356506 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6048 23:42:07.359682 ===================================
6049 23:42:07.363562 LPDDR4 DRAM CONFIGURATION
6050 23:42:07.366372 ===================================
6051 23:42:07.369750 EX_ROW_EN[0] = 0x0
6052 23:42:07.369823 EX_ROW_EN[1] = 0x0
6053 23:42:07.372909 LP4Y_EN = 0x0
6054 23:42:07.372980 WORK_FSP = 0x0
6055 23:42:07.376437 WL = 0x2
6056 23:42:07.376512 RL = 0x2
6057 23:42:07.379871 BL = 0x2
6058 23:42:07.380034 RPST = 0x0
6059 23:42:07.382944 RD_PRE = 0x0
6060 23:42:07.383047 WR_PRE = 0x1
6061 23:42:07.386303 WR_PST = 0x0
6062 23:42:07.386425 DBI_WR = 0x0
6063 23:42:07.389672 DBI_RD = 0x0
6064 23:42:07.393037 OTF = 0x1
6065 23:42:07.396360 ===================================
6066 23:42:07.396483 ===================================
6067 23:42:07.399751 ANA top config
6068 23:42:07.403139 ===================================
6069 23:42:07.406316 DLL_ASYNC_EN = 0
6070 23:42:07.406426 ALL_SLAVE_EN = 1
6071 23:42:07.409845 NEW_RANK_MODE = 1
6072 23:42:07.413292 DLL_IDLE_MODE = 1
6073 23:42:07.416471 LP45_APHY_COMB_EN = 1
6074 23:42:07.419942 TX_ODT_DIS = 1
6075 23:42:07.420051 NEW_8X_MODE = 1
6076 23:42:07.423120 ===================================
6077 23:42:07.426274 ===================================
6078 23:42:07.429546 data_rate = 800
6079 23:42:07.432972 CKR = 1
6080 23:42:07.437071 DQ_P2S_RATIO = 4
6081 23:42:07.439646 ===================================
6082 23:42:07.442862 CA_P2S_RATIO = 4
6083 23:42:07.442944 DQ_CA_OPEN = 0
6084 23:42:07.446619 DQ_SEMI_OPEN = 1
6085 23:42:07.449957 CA_SEMI_OPEN = 1
6086 23:42:07.453385 CA_FULL_RATE = 0
6087 23:42:07.456725 DQ_CKDIV4_EN = 0
6088 23:42:07.459879 CA_CKDIV4_EN = 1
6089 23:42:07.459953 CA_PREDIV_EN = 0
6090 23:42:07.463124 PH8_DLY = 0
6091 23:42:07.466674 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6092 23:42:07.469950 DQ_AAMCK_DIV = 0
6093 23:42:07.472945 CA_AAMCK_DIV = 0
6094 23:42:07.476281 CA_ADMCK_DIV = 4
6095 23:42:07.476380 DQ_TRACK_CA_EN = 0
6096 23:42:07.479557 CA_PICK = 800
6097 23:42:07.483182 CA_MCKIO = 400
6098 23:42:07.486168 MCKIO_SEMI = 400
6099 23:42:07.489577 PLL_FREQ = 3016
6100 23:42:07.492944 DQ_UI_PI_RATIO = 32
6101 23:42:07.496202 CA_UI_PI_RATIO = 32
6102 23:42:07.499540 ===================================
6103 23:42:07.502834 ===================================
6104 23:42:07.502908 memory_type:LPDDR4
6105 23:42:07.506245 GP_NUM : 10
6106 23:42:07.509033 SRAM_EN : 1
6107 23:42:07.509141 MD32_EN : 0
6108 23:42:07.512424 ===================================
6109 23:42:07.515822 [ANA_INIT] >>>>>>>>>>>>>>
6110 23:42:07.519000 <<<<<< [CONFIGURE PHASE]: ANA_TX
6111 23:42:07.522494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6112 23:42:07.525924 ===================================
6113 23:42:07.529308 data_rate = 800,PCW = 0X7400
6114 23:42:07.532293 ===================================
6115 23:42:07.535762 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6116 23:42:07.539132 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6117 23:42:07.552480 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6118 23:42:07.555465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6119 23:42:07.558861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6120 23:42:07.562203 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6121 23:42:07.565504 [ANA_INIT] flow start
6122 23:42:07.568797 [ANA_INIT] PLL >>>>>>>>
6123 23:42:07.568903 [ANA_INIT] PLL <<<<<<<<
6124 23:42:07.571900 [ANA_INIT] MIDPI >>>>>>>>
6125 23:42:07.575532 [ANA_INIT] MIDPI <<<<<<<<
6126 23:42:07.575620 [ANA_INIT] DLL >>>>>>>>
6127 23:42:07.578345 [ANA_INIT] flow end
6128 23:42:07.581726 ============ LP4 DIFF to SE enter ============
6129 23:42:07.588604 ============ LP4 DIFF to SE exit ============
6130 23:42:07.588736 [ANA_INIT] <<<<<<<<<<<<<
6131 23:42:07.591684 [Flow] Enable top DCM control >>>>>
6132 23:42:07.595235 [Flow] Enable top DCM control <<<<<
6133 23:42:07.598571 Enable DLL master slave shuffle
6134 23:42:07.605396 ==============================================================
6135 23:42:07.605525 Gating Mode config
6136 23:42:07.611959 ==============================================================
6137 23:42:07.614824 Config description:
6138 23:42:07.624728 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6139 23:42:07.631523 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6140 23:42:07.634948 SELPH_MODE 0: By rank 1: By Phase
6141 23:42:07.641559 ==============================================================
6142 23:42:07.645040 GAT_TRACK_EN = 0
6143 23:42:07.645152 RX_GATING_MODE = 2
6144 23:42:07.648238 RX_GATING_TRACK_MODE = 2
6145 23:42:07.651254 SELPH_MODE = 1
6146 23:42:07.655053 PICG_EARLY_EN = 1
6147 23:42:07.658124 VALID_LAT_VALUE = 1
6148 23:42:07.665157 ==============================================================
6149 23:42:07.668239 Enter into Gating configuration >>>>
6150 23:42:07.671524 Exit from Gating configuration <<<<
6151 23:42:07.674822 Enter into DVFS_PRE_config >>>>>
6152 23:42:07.684470 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6153 23:42:07.688316 Exit from DVFS_PRE_config <<<<<
6154 23:42:07.691725 Enter into PICG configuration >>>>
6155 23:42:07.694965 Exit from PICG configuration <<<<
6156 23:42:07.698271 [RX_INPUT] configuration >>>>>
6157 23:42:07.698345 [RX_INPUT] configuration <<<<<
6158 23:42:07.704538 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6159 23:42:07.711243 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6160 23:42:07.718233 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6161 23:42:07.721062 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6162 23:42:07.727737 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6163 23:42:07.734679 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6164 23:42:07.737950 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6165 23:42:07.741366 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6166 23:42:07.748161 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6167 23:42:07.751594 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6168 23:42:07.754313 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6169 23:42:07.761140 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6170 23:42:07.764346 ===================================
6171 23:42:07.764435 LPDDR4 DRAM CONFIGURATION
6172 23:42:07.767581 ===================================
6173 23:42:07.771058 EX_ROW_EN[0] = 0x0
6174 23:42:07.774598 EX_ROW_EN[1] = 0x0
6175 23:42:07.774679 LP4Y_EN = 0x0
6176 23:42:07.778048 WORK_FSP = 0x0
6177 23:42:07.778125 WL = 0x2
6178 23:42:07.780870 RL = 0x2
6179 23:42:07.780966 BL = 0x2
6180 23:42:07.784104 RPST = 0x0
6181 23:42:07.784181 RD_PRE = 0x0
6182 23:42:07.787790 WR_PRE = 0x1
6183 23:42:07.787861 WR_PST = 0x0
6184 23:42:07.790612 DBI_WR = 0x0
6185 23:42:07.790694 DBI_RD = 0x0
6186 23:42:07.794191 OTF = 0x1
6187 23:42:07.797408 ===================================
6188 23:42:07.800479 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6189 23:42:07.803756 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6190 23:42:07.810812 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6191 23:42:07.813665 ===================================
6192 23:42:07.813778 LPDDR4 DRAM CONFIGURATION
6193 23:42:07.817143 ===================================
6194 23:42:07.820483 EX_ROW_EN[0] = 0x10
6195 23:42:07.823909 EX_ROW_EN[1] = 0x0
6196 23:42:07.824025 LP4Y_EN = 0x0
6197 23:42:07.827354 WORK_FSP = 0x0
6198 23:42:07.827461 WL = 0x2
6199 23:42:07.830740 RL = 0x2
6200 23:42:07.830839 BL = 0x2
6201 23:42:07.834100 RPST = 0x0
6202 23:42:07.834174 RD_PRE = 0x0
6203 23:42:07.836843 WR_PRE = 0x1
6204 23:42:07.836916 WR_PST = 0x0
6205 23:42:07.840228 DBI_WR = 0x0
6206 23:42:07.840332 DBI_RD = 0x0
6207 23:42:07.843489 OTF = 0x1
6208 23:42:07.846823 ===================================
6209 23:42:07.853906 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6210 23:42:07.857326 nWR fixed to 30
6211 23:42:07.857404 [ModeRegInit_LP4] CH0 RK0
6212 23:42:07.860100 [ModeRegInit_LP4] CH0 RK1
6213 23:42:07.863470 [ModeRegInit_LP4] CH1 RK0
6214 23:42:07.866750 [ModeRegInit_LP4] CH1 RK1
6215 23:42:07.866833 match AC timing 19
6216 23:42:07.870302 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6217 23:42:07.876710 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6218 23:42:07.880148 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6219 23:42:07.883528 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6220 23:42:07.890038 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6221 23:42:07.890146 ==
6222 23:42:07.893722 Dram Type= 6, Freq= 0, CH_0, rank 0
6223 23:42:07.896903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6224 23:42:07.897019 ==
6225 23:42:07.903293 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6226 23:42:07.910052 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6227 23:42:07.910158 [CA 0] Center 36 (8~64) winsize 57
6228 23:42:07.913281 [CA 1] Center 36 (8~64) winsize 57
6229 23:42:07.916907 [CA 2] Center 36 (8~64) winsize 57
6230 23:42:07.920208 [CA 3] Center 36 (8~64) winsize 57
6231 23:42:07.923231 [CA 4] Center 36 (8~64) winsize 57
6232 23:42:07.926871 [CA 5] Center 36 (8~64) winsize 57
6233 23:42:07.926998
6234 23:42:07.930031 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6235 23:42:07.930156
6236 23:42:07.933006 [CATrainingPosCal] consider 1 rank data
6237 23:42:07.936739 u2DelayCellTimex100 = 270/100 ps
6238 23:42:07.940079 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 23:42:07.946593 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 23:42:07.950076 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 23:42:07.953232 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 23:42:07.956301 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 23:42:07.959760 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 23:42:07.959885
6245 23:42:07.963125 CA PerBit enable=1, Macro0, CA PI delay=36
6246 23:42:07.963241
6247 23:42:07.966628 [CBTSetCACLKResult] CA Dly = 36
6248 23:42:07.966740 CS Dly: 1 (0~32)
6249 23:42:07.969767 ==
6250 23:42:07.972795 Dram Type= 6, Freq= 0, CH_0, rank 1
6251 23:42:07.976204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6252 23:42:07.976329 ==
6253 23:42:07.979487 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6254 23:42:07.986161 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6255 23:42:07.989524 [CA 0] Center 36 (8~64) winsize 57
6256 23:42:07.992811 [CA 1] Center 36 (8~64) winsize 57
6257 23:42:07.996149 [CA 2] Center 36 (8~64) winsize 57
6258 23:42:07.999533 [CA 3] Center 36 (8~64) winsize 57
6259 23:42:08.003001 [CA 4] Center 36 (8~64) winsize 57
6260 23:42:08.005937 [CA 5] Center 36 (8~64) winsize 57
6261 23:42:08.006060
6262 23:42:08.009589 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6263 23:42:08.009694
6264 23:42:08.012763 [CATrainingPosCal] consider 2 rank data
6265 23:42:08.016119 u2DelayCellTimex100 = 270/100 ps
6266 23:42:08.019215 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 23:42:08.022434 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 23:42:08.025921 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 23:42:08.029461 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 23:42:08.035661 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 23:42:08.039083 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 23:42:08.039220
6273 23:42:08.042327 CA PerBit enable=1, Macro0, CA PI delay=36
6274 23:42:08.042449
6275 23:42:08.045950 [CBTSetCACLKResult] CA Dly = 36
6276 23:42:08.046052 CS Dly: 1 (0~32)
6277 23:42:08.046143
6278 23:42:08.049105 ----->DramcWriteLeveling(PI) begin...
6279 23:42:08.049259 ==
6280 23:42:08.052318 Dram Type= 6, Freq= 0, CH_0, rank 0
6281 23:42:08.058967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6282 23:42:08.059077 ==
6283 23:42:08.062265 Write leveling (Byte 0): 40 => 8
6284 23:42:08.062373 Write leveling (Byte 1): 40 => 8
6285 23:42:08.066028 DramcWriteLeveling(PI) end<-----
6286 23:42:08.066153
6287 23:42:08.068835 ==
6288 23:42:08.068928 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 23:42:08.075676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 23:42:08.075768 ==
6291 23:42:08.079077 [Gating] SW mode calibration
6292 23:42:08.085363 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6293 23:42:08.088822 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6294 23:42:08.095893 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6295 23:42:08.099027 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6296 23:42:08.101962 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6297 23:42:08.108774 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6298 23:42:08.112073 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6299 23:42:08.115445 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6300 23:42:08.122103 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6301 23:42:08.125144 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 23:42:08.128576 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6303 23:42:08.132049 Total UI for P1: 0, mck2ui 16
6304 23:42:08.135318 best dqsien dly found for B0: ( 0, 14, 24)
6305 23:42:08.138420 Total UI for P1: 0, mck2ui 16
6306 23:42:08.141884 best dqsien dly found for B1: ( 0, 14, 24)
6307 23:42:08.145207 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6308 23:42:08.148719 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6309 23:42:08.148804
6310 23:42:08.155011 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6311 23:42:08.158451 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6312 23:42:08.161560 [Gating] SW calibration Done
6313 23:42:08.161667 ==
6314 23:42:08.165286 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 23:42:08.168342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 23:42:08.168446 ==
6317 23:42:08.168540 RX Vref Scan: 0
6318 23:42:08.168613
6319 23:42:08.171951 RX Vref 0 -> 0, step: 1
6320 23:42:08.172102
6321 23:42:08.175320 RX Delay -410 -> 252, step: 16
6322 23:42:08.178160 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6323 23:42:08.184650 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6324 23:42:08.188200 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6325 23:42:08.191700 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6326 23:42:08.195023 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6327 23:42:08.201626 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6328 23:42:08.204957 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6329 23:42:08.208299 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6330 23:42:08.211709 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6331 23:42:08.218133 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6332 23:42:08.221097 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6333 23:42:08.224540 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6334 23:42:08.227948 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6335 23:42:08.234780 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6336 23:42:08.237808 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6337 23:42:08.240974 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6338 23:42:08.241053 ==
6339 23:42:08.244328 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 23:42:08.247872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 23:42:08.251101 ==
6342 23:42:08.251181 DQS Delay:
6343 23:42:08.251246 DQS0 = 59, DQS1 = 59
6344 23:42:08.254439 DQM Delay:
6345 23:42:08.254542 DQM0 = 19, DQM1 = 10
6346 23:42:08.257937 DQ Delay:
6347 23:42:08.261141 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6348 23:42:08.261218 DQ4 =24, DQ5 =0, DQ6 =32, DQ7 =32
6349 23:42:08.264316 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6350 23:42:08.267545 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6351 23:42:08.267647
6352 23:42:08.271228
6353 23:42:08.271331 ==
6354 23:42:08.274617 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 23:42:08.277510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 23:42:08.277584 ==
6357 23:42:08.277647
6358 23:42:08.277706
6359 23:42:08.280913 TX Vref Scan disable
6360 23:42:08.280990 == TX Byte 0 ==
6361 23:42:08.284652 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6362 23:42:08.290731 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6363 23:42:08.290837 == TX Byte 1 ==
6364 23:42:08.294246 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 23:42:08.300841 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 23:42:08.300923 ==
6367 23:42:08.304042 Dram Type= 6, Freq= 0, CH_0, rank 0
6368 23:42:08.307498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6369 23:42:08.307612 ==
6370 23:42:08.307706
6371 23:42:08.307797
6372 23:42:08.310728 TX Vref Scan disable
6373 23:42:08.310828 == TX Byte 0 ==
6374 23:42:08.314182 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6375 23:42:08.320764 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6376 23:42:08.320842 == TX Byte 1 ==
6377 23:42:08.323943 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6378 23:42:08.330789 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6379 23:42:08.330866
6380 23:42:08.330930 [DATLAT]
6381 23:42:08.330993 Freq=400, CH0 RK0
6382 23:42:08.334364
6383 23:42:08.334470 DATLAT Default: 0xf
6384 23:42:08.337278 0, 0xFFFF, sum = 0
6385 23:42:08.337362 1, 0xFFFF, sum = 0
6386 23:42:08.340674 2, 0xFFFF, sum = 0
6387 23:42:08.340752 3, 0xFFFF, sum = 0
6388 23:42:08.343901 4, 0xFFFF, sum = 0
6389 23:42:08.343977 5, 0xFFFF, sum = 0
6390 23:42:08.347532 6, 0xFFFF, sum = 0
6391 23:42:08.347639 7, 0xFFFF, sum = 0
6392 23:42:08.350672 8, 0xFFFF, sum = 0
6393 23:42:08.350748 9, 0xFFFF, sum = 0
6394 23:42:08.353892 10, 0xFFFF, sum = 0
6395 23:42:08.353997 11, 0xFFFF, sum = 0
6396 23:42:08.357190 12, 0xFFFF, sum = 0
6397 23:42:08.357267 13, 0x0, sum = 1
6398 23:42:08.360677 14, 0x0, sum = 2
6399 23:42:08.360780 15, 0x0, sum = 3
6400 23:42:08.364081 16, 0x0, sum = 4
6401 23:42:08.364187 best_step = 14
6402 23:42:08.364277
6403 23:42:08.364369 ==
6404 23:42:08.366984 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 23:42:08.373646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 23:42:08.373749 ==
6407 23:42:08.373845 RX Vref Scan: 1
6408 23:42:08.373934
6409 23:42:08.376976 RX Vref 0 -> 0, step: 1
6410 23:42:08.377051
6411 23:42:08.380268 RX Delay -359 -> 252, step: 8
6412 23:42:08.380366
6413 23:42:08.383537 Set Vref, RX VrefLevel [Byte0]: 60
6414 23:42:08.386867 [Byte1]: 51
6415 23:42:08.390221
6416 23:42:08.390296 Final RX Vref Byte 0 = 60 to rank0
6417 23:42:08.393659 Final RX Vref Byte 1 = 51 to rank0
6418 23:42:08.397206 Final RX Vref Byte 0 = 60 to rank1
6419 23:42:08.400097 Final RX Vref Byte 1 = 51 to rank1==
6420 23:42:08.403365 Dram Type= 6, Freq= 0, CH_0, rank 0
6421 23:42:08.409990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 23:42:08.410074 ==
6423 23:42:08.410140 DQS Delay:
6424 23:42:08.410202 DQS0 = 56, DQS1 = 68
6425 23:42:08.413481 DQM Delay:
6426 23:42:08.413554 DQM0 = 11, DQM1 = 14
6427 23:42:08.416939 DQ Delay:
6428 23:42:08.420171 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =12
6429 23:42:08.420243 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6430 23:42:08.423476 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6431 23:42:08.426718 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6432 23:42:08.426795
6433 23:42:08.430468
6434 23:42:08.436432 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b89, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
6435 23:42:08.439701 CH0 RK0: MR19=C0C, MR18=8B89
6436 23:42:08.446540 CH0_RK0: MR19=0xC0C, MR18=0x8B89, DQSOSC=392, MR23=63, INC=384, DEC=256
6437 23:42:08.446651 ==
6438 23:42:08.449732 Dram Type= 6, Freq= 0, CH_0, rank 1
6439 23:42:08.453359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 23:42:08.453440 ==
6441 23:42:08.456765 [Gating] SW mode calibration
6442 23:42:08.463400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6443 23:42:08.469662 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6444 23:42:08.472877 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6445 23:42:08.476714 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6446 23:42:08.483410 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6447 23:42:08.486321 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6448 23:42:08.489708 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6449 23:42:08.493513 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6450 23:42:08.499806 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6451 23:42:08.503272 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 23:42:08.506504 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6453 23:42:08.509788 Total UI for P1: 0, mck2ui 16
6454 23:42:08.513159 best dqsien dly found for B0: ( 0, 14, 24)
6455 23:42:08.516416 Total UI for P1: 0, mck2ui 16
6456 23:42:08.519933 best dqsien dly found for B1: ( 0, 14, 24)
6457 23:42:08.523229 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6458 23:42:08.526732 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6459 23:42:08.529547
6460 23:42:08.532982 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6461 23:42:08.536425 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6462 23:42:08.539426 [Gating] SW calibration Done
6463 23:42:08.539515 ==
6464 23:42:08.542987 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 23:42:08.545827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 23:42:08.545906 ==
6467 23:42:08.549203 RX Vref Scan: 0
6468 23:42:08.549276
6469 23:42:08.549337 RX Vref 0 -> 0, step: 1
6470 23:42:08.549397
6471 23:42:08.552805 RX Delay -410 -> 252, step: 16
6472 23:42:08.556221 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6473 23:42:08.563196 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6474 23:42:08.566082 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6475 23:42:08.569486 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6476 23:42:08.572829 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6477 23:42:08.579582 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6478 23:42:08.582854 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6479 23:42:08.586125 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6480 23:42:08.589565 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6481 23:42:08.595626 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6482 23:42:08.599093 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6483 23:42:08.602253 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6484 23:42:08.605825 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6485 23:42:08.612574 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6486 23:42:08.615849 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6487 23:42:08.619210 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6488 23:42:08.619309 ==
6489 23:42:08.622165 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 23:42:08.628834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 23:42:08.628908 ==
6492 23:42:08.628983 DQS Delay:
6493 23:42:08.631976 DQS0 = 59, DQS1 = 59
6494 23:42:08.632046 DQM Delay:
6495 23:42:08.635417 DQM0 = 16, DQM1 = 10
6496 23:42:08.635487 DQ Delay:
6497 23:42:08.638719 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6498 23:42:08.642071 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6499 23:42:08.645096 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6500 23:42:08.648562 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6501 23:42:08.648653
6502 23:42:08.648715
6503 23:42:08.648773 ==
6504 23:42:08.652063 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 23:42:08.655476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 23:42:08.655604 ==
6507 23:42:08.655718
6508 23:42:08.655828
6509 23:42:08.658914 TX Vref Scan disable
6510 23:42:08.659032 == TX Byte 0 ==
6511 23:42:08.665413 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6512 23:42:08.668723 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6513 23:42:08.668805 == TX Byte 1 ==
6514 23:42:08.675378 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6515 23:42:08.678780 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6516 23:42:08.678860 ==
6517 23:42:08.681760 Dram Type= 6, Freq= 0, CH_0, rank 1
6518 23:42:08.685131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 23:42:08.685231 ==
6520 23:42:08.685329
6521 23:42:08.685434
6522 23:42:08.688451 TX Vref Scan disable
6523 23:42:08.688580 == TX Byte 0 ==
6524 23:42:08.695031 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6525 23:42:08.698449 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6526 23:42:08.698533 == TX Byte 1 ==
6527 23:42:08.705016 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6528 23:42:08.708470 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6529 23:42:08.708590
6530 23:42:08.708698 [DATLAT]
6531 23:42:08.711640 Freq=400, CH0 RK1
6532 23:42:08.711775
6533 23:42:08.711875 DATLAT Default: 0xe
6534 23:42:08.714910 0, 0xFFFF, sum = 0
6535 23:42:08.715023 1, 0xFFFF, sum = 0
6536 23:42:08.718173 2, 0xFFFF, sum = 0
6537 23:42:08.718299 3, 0xFFFF, sum = 0
6538 23:42:08.721598 4, 0xFFFF, sum = 0
6539 23:42:08.721699 5, 0xFFFF, sum = 0
6540 23:42:08.724930 6, 0xFFFF, sum = 0
6541 23:42:08.725015 7, 0xFFFF, sum = 0
6542 23:42:08.728218 8, 0xFFFF, sum = 0
6543 23:42:08.728342 9, 0xFFFF, sum = 0
6544 23:42:08.731748 10, 0xFFFF, sum = 0
6545 23:42:08.734561 11, 0xFFFF, sum = 0
6546 23:42:08.734647 12, 0xFFFF, sum = 0
6547 23:42:08.738061 13, 0x0, sum = 1
6548 23:42:08.738168 14, 0x0, sum = 2
6549 23:42:08.741314 15, 0x0, sum = 3
6550 23:42:08.741389 16, 0x0, sum = 4
6551 23:42:08.741454 best_step = 14
6552 23:42:08.741514
6553 23:42:08.744680 ==
6554 23:42:08.747784 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 23:42:08.751389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 23:42:08.751461 ==
6557 23:42:08.751522 RX Vref Scan: 0
6558 23:42:08.751615
6559 23:42:08.754721 RX Vref 0 -> 0, step: 1
6560 23:42:08.754831
6561 23:42:08.757807 RX Delay -359 -> 252, step: 8
6562 23:42:08.764930 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6563 23:42:08.767945 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6564 23:42:08.771790 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6565 23:42:08.774582 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6566 23:42:08.781275 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6567 23:42:08.784739 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6568 23:42:08.787956 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6569 23:42:08.791520 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6570 23:42:08.797841 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6571 23:42:08.801302 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6572 23:42:08.804589 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6573 23:42:08.811551 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6574 23:42:08.814242 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6575 23:42:08.817900 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6576 23:42:08.820973 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6577 23:42:08.827699 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6578 23:42:08.827809 ==
6579 23:42:08.831142 Dram Type= 6, Freq= 0, CH_0, rank 1
6580 23:42:08.834497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6581 23:42:08.834620 ==
6582 23:42:08.834717 DQS Delay:
6583 23:42:08.837491 DQS0 = 60, DQS1 = 72
6584 23:42:08.837590 DQM Delay:
6585 23:42:08.840887 DQM0 = 11, DQM1 = 17
6586 23:42:08.840994 DQ Delay:
6587 23:42:08.844335 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6588 23:42:08.847728 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6589 23:42:08.850961 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6590 23:42:08.854311 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6591 23:42:08.854397
6592 23:42:08.854483
6593 23:42:08.861220 [DQSOSCAuto] RK1, (LSB)MR18= 0xc77c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6594 23:42:08.864542 CH0 RK1: MR19=C0C, MR18=C77C
6595 23:42:08.870776 CH0_RK1: MR19=0xC0C, MR18=0xC77C, DQSOSC=385, MR23=63, INC=398, DEC=265
6596 23:42:08.874380 [RxdqsGatingPostProcess] freq 400
6597 23:42:08.881206 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6598 23:42:08.884284 best DQS0 dly(2T, 0.5T) = (0, 10)
6599 23:42:08.884402 best DQS1 dly(2T, 0.5T) = (0, 10)
6600 23:42:08.887674 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6601 23:42:08.890702 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6602 23:42:08.894017 best DQS0 dly(2T, 0.5T) = (0, 10)
6603 23:42:08.897448 best DQS1 dly(2T, 0.5T) = (0, 10)
6604 23:42:08.900904 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6605 23:42:08.903949 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6606 23:42:08.907359 Pre-setting of DQS Precalculation
6607 23:42:08.913782 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6608 23:42:08.913907 ==
6609 23:42:08.917216 Dram Type= 6, Freq= 0, CH_1, rank 0
6610 23:42:08.920667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 23:42:08.920791 ==
6612 23:42:08.927080 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6613 23:42:08.930328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6614 23:42:08.933878 [CA 0] Center 36 (8~64) winsize 57
6615 23:42:08.937193 [CA 1] Center 36 (8~64) winsize 57
6616 23:42:08.940478 [CA 2] Center 36 (8~64) winsize 57
6617 23:42:08.943931 [CA 3] Center 36 (8~64) winsize 57
6618 23:42:08.947200 [CA 4] Center 36 (8~64) winsize 57
6619 23:42:08.950549 [CA 5] Center 36 (8~64) winsize 57
6620 23:42:08.950674
6621 23:42:08.953498 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6622 23:42:08.953626
6623 23:42:08.957206 [CATrainingPosCal] consider 1 rank data
6624 23:42:08.960174 u2DelayCellTimex100 = 270/100 ps
6625 23:42:08.963898 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 23:42:08.966977 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 23:42:08.973591 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 23:42:08.977031 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 23:42:08.980238 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 23:42:08.983459 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 23:42:08.983581
6632 23:42:08.986839 CA PerBit enable=1, Macro0, CA PI delay=36
6633 23:42:08.986945
6634 23:42:08.990160 [CBTSetCACLKResult] CA Dly = 36
6635 23:42:08.990243 CS Dly: 1 (0~32)
6636 23:42:08.990309 ==
6637 23:42:08.993706 Dram Type= 6, Freq= 0, CH_1, rank 1
6638 23:42:08.999772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6639 23:42:08.999903 ==
6640 23:42:09.003341 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6641 23:42:09.010236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6642 23:42:09.013164 [CA 0] Center 36 (8~64) winsize 57
6643 23:42:09.016756 [CA 1] Center 36 (8~64) winsize 57
6644 23:42:09.019993 [CA 2] Center 36 (8~64) winsize 57
6645 23:42:09.023045 [CA 3] Center 36 (8~64) winsize 57
6646 23:42:09.026357 [CA 4] Center 36 (8~64) winsize 57
6647 23:42:09.029995 [CA 5] Center 36 (8~64) winsize 57
6648 23:42:09.030078
6649 23:42:09.032762 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6650 23:42:09.032845
6651 23:42:09.036263 [CATrainingPosCal] consider 2 rank data
6652 23:42:09.039919 u2DelayCellTimex100 = 270/100 ps
6653 23:42:09.042974 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 23:42:09.046529 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 23:42:09.049774 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 23:42:09.052817 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 23:42:09.056022 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 23:42:09.063170 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 23:42:09.063279
6660 23:42:09.066076 CA PerBit enable=1, Macro0, CA PI delay=36
6661 23:42:09.066185
6662 23:42:09.069732 [CBTSetCACLKResult] CA Dly = 36
6663 23:42:09.069815 CS Dly: 1 (0~32)
6664 23:42:09.069880
6665 23:42:09.073026 ----->DramcWriteLeveling(PI) begin...
6666 23:42:09.073109 ==
6667 23:42:09.076515 Dram Type= 6, Freq= 0, CH_1, rank 0
6668 23:42:09.079789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6669 23:42:09.083140 ==
6670 23:42:09.083225 Write leveling (Byte 0): 40 => 8
6671 23:42:09.086637 Write leveling (Byte 1): 40 => 8
6672 23:42:09.089806 DramcWriteLeveling(PI) end<-----
6673 23:42:09.089912
6674 23:42:09.090006 ==
6675 23:42:09.092917 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 23:42:09.099856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 23:42:09.099941 ==
6678 23:42:09.102735 [Gating] SW mode calibration
6679 23:42:09.109339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6680 23:42:09.112874 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6681 23:42:09.119608 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6682 23:42:09.122498 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6683 23:42:09.126101 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6684 23:42:09.132690 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6685 23:42:09.136088 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6686 23:42:09.139540 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6687 23:42:09.142354 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6688 23:42:09.149246 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 23:42:09.152387 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6690 23:42:09.156181 Total UI for P1: 0, mck2ui 16
6691 23:42:09.158897 best dqsien dly found for B0: ( 0, 14, 24)
6692 23:42:09.162642 Total UI for P1: 0, mck2ui 16
6693 23:42:09.165708 best dqsien dly found for B1: ( 0, 14, 24)
6694 23:42:09.168974 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6695 23:42:09.172462 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6696 23:42:09.172580
6697 23:42:09.175873 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6698 23:42:09.182298 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6699 23:42:09.182403 [Gating] SW calibration Done
6700 23:42:09.182476 ==
6701 23:42:09.185408 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 23:42:09.192300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 23:42:09.192430 ==
6704 23:42:09.192553 RX Vref Scan: 0
6705 23:42:09.192673
6706 23:42:09.195651 RX Vref 0 -> 0, step: 1
6707 23:42:09.195769
6708 23:42:09.198964 RX Delay -410 -> 252, step: 16
6709 23:42:09.202584 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6710 23:42:09.205560 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6711 23:42:09.211818 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6712 23:42:09.215378 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6713 23:42:09.218758 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6714 23:42:09.222084 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6715 23:42:09.229333 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6716 23:42:09.232178 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6717 23:42:09.235739 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6718 23:42:09.238801 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6719 23:42:09.244957 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6720 23:42:09.248491 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6721 23:42:09.252017 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6722 23:42:09.255202 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6723 23:42:09.261983 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6724 23:42:09.264949 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6725 23:42:09.265078 ==
6726 23:42:09.268199 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 23:42:09.271591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 23:42:09.271675 ==
6729 23:42:09.275318 DQS Delay:
6730 23:42:09.275407 DQS0 = 51, DQS1 = 67
6731 23:42:09.278468 DQM Delay:
6732 23:42:09.278544 DQM0 = 12, DQM1 = 19
6733 23:42:09.281473 DQ Delay:
6734 23:42:09.281549 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6735 23:42:09.284851 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6736 23:42:09.288187 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6737 23:42:09.291978 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6738 23:42:09.292066
6739 23:42:09.292132
6740 23:42:09.292193 ==
6741 23:42:09.294823 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 23:42:09.301582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 23:42:09.301667 ==
6744 23:42:09.301734
6745 23:42:09.301794
6746 23:42:09.301852 TX Vref Scan disable
6747 23:42:09.304739 == TX Byte 0 ==
6748 23:42:09.308180 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6749 23:42:09.311535 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6750 23:42:09.314548 == TX Byte 1 ==
6751 23:42:09.317742 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 23:42:09.321652 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 23:42:09.324391 ==
6754 23:42:09.328179 Dram Type= 6, Freq= 0, CH_1, rank 0
6755 23:42:09.331182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6756 23:42:09.331261 ==
6757 23:42:09.331325
6758 23:42:09.331386
6759 23:42:09.334686 TX Vref Scan disable
6760 23:42:09.334756 == TX Byte 0 ==
6761 23:42:09.338000 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6762 23:42:09.344681 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6763 23:42:09.344775 == TX Byte 1 ==
6764 23:42:09.347856 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 23:42:09.354460 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 23:42:09.354543
6767 23:42:09.354609 [DATLAT]
6768 23:42:09.354670 Freq=400, CH1 RK0
6769 23:42:09.354729
6770 23:42:09.358017 DATLAT Default: 0xf
6771 23:42:09.358100 0, 0xFFFF, sum = 0
6772 23:42:09.361813 1, 0xFFFF, sum = 0
6773 23:42:09.361924 2, 0xFFFF, sum = 0
6774 23:42:09.364157 3, 0xFFFF, sum = 0
6775 23:42:09.367582 4, 0xFFFF, sum = 0
6776 23:42:09.367667 5, 0xFFFF, sum = 0
6777 23:42:09.371304 6, 0xFFFF, sum = 0
6778 23:42:09.371388 7, 0xFFFF, sum = 0
6779 23:42:09.374443 8, 0xFFFF, sum = 0
6780 23:42:09.374526 9, 0xFFFF, sum = 0
6781 23:42:09.377829 10, 0xFFFF, sum = 0
6782 23:42:09.377913 11, 0xFFFF, sum = 0
6783 23:42:09.381047 12, 0xFFFF, sum = 0
6784 23:42:09.381129 13, 0x0, sum = 1
6785 23:42:09.384174 14, 0x0, sum = 2
6786 23:42:09.384283 15, 0x0, sum = 3
6787 23:42:09.387400 16, 0x0, sum = 4
6788 23:42:09.387483 best_step = 14
6789 23:42:09.387546
6790 23:42:09.387606 ==
6791 23:42:09.391081 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 23:42:09.394401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 23:42:09.394482 ==
6794 23:42:09.397695 RX Vref Scan: 1
6795 23:42:09.397785
6796 23:42:09.401289 RX Vref 0 -> 0, step: 1
6797 23:42:09.401370
6798 23:42:09.401433 RX Delay -375 -> 252, step: 8
6799 23:42:09.404612
6800 23:42:09.404693 Set Vref, RX VrefLevel [Byte0]: 58
6801 23:42:09.407852 [Byte1]: 52
6802 23:42:09.413465
6803 23:42:09.413545 Final RX Vref Byte 0 = 58 to rank0
6804 23:42:09.416828 Final RX Vref Byte 1 = 52 to rank0
6805 23:42:09.420116 Final RX Vref Byte 0 = 58 to rank1
6806 23:42:09.423526 Final RX Vref Byte 1 = 52 to rank1==
6807 23:42:09.426844 Dram Type= 6, Freq= 0, CH_1, rank 0
6808 23:42:09.433655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 23:42:09.433736 ==
6810 23:42:09.433800 DQS Delay:
6811 23:42:09.436392 DQS0 = 56, DQS1 = 64
6812 23:42:09.436472 DQM Delay:
6813 23:42:09.436537 DQM0 = 12, DQM1 = 10
6814 23:42:09.440064 DQ Delay:
6815 23:42:09.442951 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =8
6816 23:42:09.443032 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6817 23:42:09.446393 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6818 23:42:09.450187 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6819 23:42:09.450268
6820 23:42:09.453138
6821 23:42:09.459696 [DQSOSCAuto] RK0, (LSB)MR18= 0x5f72, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 397 ps
6822 23:42:09.462853 CH1 RK0: MR19=C0C, MR18=5F72
6823 23:42:09.469923 CH1_RK0: MR19=0xC0C, MR18=0x5F72, DQSOSC=395, MR23=63, INC=378, DEC=252
6824 23:42:09.470004 ==
6825 23:42:09.473035 Dram Type= 6, Freq= 0, CH_1, rank 1
6826 23:42:09.476240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 23:42:09.476347 ==
6828 23:42:09.479707 [Gating] SW mode calibration
6829 23:42:09.486372 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6830 23:42:09.493006 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6831 23:42:09.495917 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6832 23:42:09.499291 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6833 23:42:09.506029 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6834 23:42:09.509615 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6835 23:42:09.512459 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6836 23:42:09.519598 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6837 23:42:09.523023 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6838 23:42:09.526303 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 23:42:09.529615 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6840 23:42:09.532943 Total UI for P1: 0, mck2ui 16
6841 23:42:09.535732 best dqsien dly found for B0: ( 0, 14, 24)
6842 23:42:09.539221 Total UI for P1: 0, mck2ui 16
6843 23:42:09.542826 best dqsien dly found for B1: ( 0, 14, 24)
6844 23:42:09.545851 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6845 23:42:09.552540 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6846 23:42:09.552662
6847 23:42:09.556219 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6848 23:42:09.559170 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6849 23:42:09.562515 [Gating] SW calibration Done
6850 23:42:09.562622 ==
6851 23:42:09.565604 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 23:42:09.568929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 23:42:09.569010 ==
6854 23:42:09.572297 RX Vref Scan: 0
6855 23:42:09.572377
6856 23:42:09.572440 RX Vref 0 -> 0, step: 1
6857 23:42:09.572499
6858 23:42:09.575703 RX Delay -410 -> 252, step: 16
6859 23:42:09.579183 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6860 23:42:09.585782 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6861 23:42:09.588870 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6862 23:42:09.592437 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6863 23:42:09.598872 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6864 23:42:09.602091 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6865 23:42:09.605701 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6866 23:42:09.608555 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6867 23:42:09.615396 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6868 23:42:09.619010 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6869 23:42:09.622037 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6870 23:42:09.625548 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6871 23:42:09.631656 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6872 23:42:09.635101 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6873 23:42:09.638844 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6874 23:42:09.641634 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6875 23:42:09.645384 ==
6876 23:42:09.645465 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 23:42:09.651593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 23:42:09.651674 ==
6879 23:42:09.651738 DQS Delay:
6880 23:42:09.655238 DQS0 = 59, DQS1 = 59
6881 23:42:09.655318 DQM Delay:
6882 23:42:09.658314 DQM0 = 19, DQM1 = 15
6883 23:42:09.658412 DQ Delay:
6884 23:42:09.661636 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6885 23:42:09.664897 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6886 23:42:09.668227 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6887 23:42:09.671335 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6888 23:42:09.671441
6889 23:42:09.671532
6890 23:42:09.671626 ==
6891 23:42:09.674714 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 23:42:09.677990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 23:42:09.678071 ==
6894 23:42:09.678135
6895 23:42:09.678195
6896 23:42:09.681490 TX Vref Scan disable
6897 23:42:09.681570 == TX Byte 0 ==
6898 23:42:09.688228 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6899 23:42:09.691724 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6900 23:42:09.691805 == TX Byte 1 ==
6901 23:42:09.698166 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6902 23:42:09.701330 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6903 23:42:09.701411 ==
6904 23:42:09.704490 Dram Type= 6, Freq= 0, CH_1, rank 1
6905 23:42:09.707802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6906 23:42:09.707884 ==
6907 23:42:09.707948
6908 23:42:09.708007
6909 23:42:09.711043 TX Vref Scan disable
6910 23:42:09.714699 == TX Byte 0 ==
6911 23:42:09.717656 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6912 23:42:09.720949 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6913 23:42:09.724411 == TX Byte 1 ==
6914 23:42:09.727415 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6915 23:42:09.731026 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6916 23:42:09.731107
6917 23:42:09.731170 [DATLAT]
6918 23:42:09.734389 Freq=400, CH1 RK1
6919 23:42:09.734471
6920 23:42:09.734536 DATLAT Default: 0xe
6921 23:42:09.737349 0, 0xFFFF, sum = 0
6922 23:42:09.737435 1, 0xFFFF, sum = 0
6923 23:42:09.740977 2, 0xFFFF, sum = 0
6924 23:42:09.744237 3, 0xFFFF, sum = 0
6925 23:42:09.744319 4, 0xFFFF, sum = 0
6926 23:42:09.747657 5, 0xFFFF, sum = 0
6927 23:42:09.747739 6, 0xFFFF, sum = 0
6928 23:42:09.750997 7, 0xFFFF, sum = 0
6929 23:42:09.751078 8, 0xFFFF, sum = 0
6930 23:42:09.754323 9, 0xFFFF, sum = 0
6931 23:42:09.754405 10, 0xFFFF, sum = 0
6932 23:42:09.757096 11, 0xFFFF, sum = 0
6933 23:42:09.757178 12, 0xFFFF, sum = 0
6934 23:42:09.760752 13, 0x0, sum = 1
6935 23:42:09.760843 14, 0x0, sum = 2
6936 23:42:09.764151 15, 0x0, sum = 3
6937 23:42:09.764232 16, 0x0, sum = 4
6938 23:42:09.767118 best_step = 14
6939 23:42:09.767197
6940 23:42:09.767262 ==
6941 23:42:09.770711 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 23:42:09.773750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 23:42:09.773831 ==
6944 23:42:09.773894 RX Vref Scan: 0
6945 23:42:09.777205
6946 23:42:09.777284 RX Vref 0 -> 0, step: 1
6947 23:42:09.777348
6948 23:42:09.780407 RX Delay -359 -> 252, step: 8
6949 23:42:09.788224 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6950 23:42:09.791557 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6951 23:42:09.794923 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6952 23:42:09.798223 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6953 23:42:09.804488 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6954 23:42:09.807798 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6955 23:42:09.811041 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6956 23:42:09.814374 iDelay=217, Bit 7, Center -48 (-303 ~ 208) 512
6957 23:42:09.821105 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6958 23:42:09.824496 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6959 23:42:09.827977 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6960 23:42:09.834577 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6961 23:42:09.837666 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6962 23:42:09.841583 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6963 23:42:09.844437 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6964 23:42:09.850798 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6965 23:42:09.850875 ==
6966 23:42:09.854252 Dram Type= 6, Freq= 0, CH_1, rank 1
6967 23:42:09.857374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6968 23:42:09.857508 ==
6969 23:42:09.857619 DQS Delay:
6970 23:42:09.860831 DQS0 = 60, DQS1 = 64
6971 23:42:09.860956 DQM Delay:
6972 23:42:09.864030 DQM0 = 13, DQM1 = 10
6973 23:42:09.864207 DQ Delay:
6974 23:42:09.867300 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6975 23:42:09.870670 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =12
6976 23:42:09.873860 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6977 23:42:09.877200 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6978 23:42:09.877307
6979 23:42:09.877400
6980 23:42:09.884197 [DQSOSCAuto] RK1, (LSB)MR18= 0x7fae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 393 ps
6981 23:42:09.887126 CH1 RK1: MR19=C0C, MR18=7FAE
6982 23:42:09.893881 CH1_RK1: MR19=0xC0C, MR18=0x7FAE, DQSOSC=388, MR23=63, INC=392, DEC=261
6983 23:42:09.897414 [RxdqsGatingPostProcess] freq 400
6984 23:42:09.904127 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6985 23:42:09.907207 best DQS0 dly(2T, 0.5T) = (0, 10)
6986 23:42:09.907301 best DQS1 dly(2T, 0.5T) = (0, 10)
6987 23:42:09.910438 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6988 23:42:09.914332 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6989 23:42:09.916880 best DQS0 dly(2T, 0.5T) = (0, 10)
6990 23:42:09.920847 best DQS1 dly(2T, 0.5T) = (0, 10)
6991 23:42:09.923972 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6992 23:42:09.926876 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6993 23:42:09.930457 Pre-setting of DQS Precalculation
6994 23:42:09.937367 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6995 23:42:09.944064 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6996 23:42:09.950316 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6997 23:42:09.950422
6998 23:42:09.950515
6999 23:42:09.953400 [Calibration Summary] 800 Mbps
7000 23:42:09.953472 CH 0, Rank 0
7001 23:42:09.956639 SW Impedance : PASS
7002 23:42:09.960159 DUTY Scan : NO K
7003 23:42:09.960261 ZQ Calibration : PASS
7004 23:42:09.963688 Jitter Meter : NO K
7005 23:42:09.966776 CBT Training : PASS
7006 23:42:09.966879 Write leveling : PASS
7007 23:42:09.970184 RX DQS gating : PASS
7008 23:42:09.973243 RX DQ/DQS(RDDQC) : PASS
7009 23:42:09.973359 TX DQ/DQS : PASS
7010 23:42:09.976961 RX DATLAT : PASS
7011 23:42:09.977065 RX DQ/DQS(Engine): PASS
7012 23:42:09.980243 TX OE : NO K
7013 23:42:09.980341 All Pass.
7014 23:42:09.980430
7015 23:42:09.983538 CH 0, Rank 1
7016 23:42:09.983633 SW Impedance : PASS
7017 23:42:09.986892 DUTY Scan : NO K
7018 23:42:09.989921 ZQ Calibration : PASS
7019 23:42:09.990005 Jitter Meter : NO K
7020 23:42:09.993711 CBT Training : PASS
7021 23:42:09.997015 Write leveling : NO K
7022 23:42:09.997099 RX DQS gating : PASS
7023 23:42:10.000295 RX DQ/DQS(RDDQC) : PASS
7024 23:42:10.003699 TX DQ/DQS : PASS
7025 23:42:10.003786 RX DATLAT : PASS
7026 23:42:10.006490 RX DQ/DQS(Engine): PASS
7027 23:42:10.010343 TX OE : NO K
7028 23:42:10.010427 All Pass.
7029 23:42:10.010499
7030 23:42:10.010562 CH 1, Rank 0
7031 23:42:10.013494 SW Impedance : PASS
7032 23:42:10.016800 DUTY Scan : NO K
7033 23:42:10.016879 ZQ Calibration : PASS
7034 23:42:10.020055 Jitter Meter : NO K
7035 23:42:10.023262 CBT Training : PASS
7036 23:42:10.023338 Write leveling : PASS
7037 23:42:10.026527 RX DQS gating : PASS
7038 23:42:10.029900 RX DQ/DQS(RDDQC) : PASS
7039 23:42:10.029973 TX DQ/DQS : PASS
7040 23:42:10.033090 RX DATLAT : PASS
7041 23:42:10.033160 RX DQ/DQS(Engine): PASS
7042 23:42:10.036499 TX OE : NO K
7043 23:42:10.036573 All Pass.
7044 23:42:10.036634
7045 23:42:10.039763 CH 1, Rank 1
7046 23:42:10.042929 SW Impedance : PASS
7047 23:42:10.043002 DUTY Scan : NO K
7048 23:42:10.046228 ZQ Calibration : PASS
7049 23:42:10.046299 Jitter Meter : NO K
7050 23:42:10.049453 CBT Training : PASS
7051 23:42:10.053265 Write leveling : NO K
7052 23:42:10.053335 RX DQS gating : PASS
7053 23:42:10.056432 RX DQ/DQS(RDDQC) : PASS
7054 23:42:10.059695 TX DQ/DQS : PASS
7055 23:42:10.059809 RX DATLAT : PASS
7056 23:42:10.063127 RX DQ/DQS(Engine): PASS
7057 23:42:10.066361 TX OE : NO K
7058 23:42:10.066444 All Pass.
7059 23:42:10.066509
7060 23:42:10.069568 DramC Write-DBI off
7061 23:42:10.069650 PER_BANK_REFRESH: Hybrid Mode
7062 23:42:10.073073 TX_TRACKING: ON
7063 23:42:10.079248 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7064 23:42:10.086144 [FAST_K] Save calibration result to emmc
7065 23:42:10.089250 dramc_set_vcore_voltage set vcore to 725000
7066 23:42:10.089332 Read voltage for 1600, 0
7067 23:42:10.092702 Vio18 = 0
7068 23:42:10.092782 Vcore = 725000
7069 23:42:10.092846 Vdram = 0
7070 23:42:10.096180 Vddq = 0
7071 23:42:10.096259 Vmddr = 0
7072 23:42:10.099329 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7073 23:42:10.106183 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7074 23:42:10.109622 MEM_TYPE=3, freq_sel=13
7075 23:42:10.112943 sv_algorithm_assistance_LP4_3733
7076 23:42:10.115711 ============ PULL DRAM RESETB DOWN ============
7077 23:42:10.119373 ========== PULL DRAM RESETB DOWN end =========
7078 23:42:10.125860 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7079 23:42:10.129125 ===================================
7080 23:42:10.129209 LPDDR4 DRAM CONFIGURATION
7081 23:42:10.132404 ===================================
7082 23:42:10.135984 EX_ROW_EN[0] = 0x0
7083 23:42:10.136067 EX_ROW_EN[1] = 0x0
7084 23:42:10.139055 LP4Y_EN = 0x0
7085 23:42:10.139138 WORK_FSP = 0x1
7086 23:42:10.142737 WL = 0x5
7087 23:42:10.146033 RL = 0x5
7088 23:42:10.146117 BL = 0x2
7089 23:42:10.149195 RPST = 0x0
7090 23:42:10.149278 RD_PRE = 0x0
7091 23:42:10.152318 WR_PRE = 0x1
7092 23:42:10.152401 WR_PST = 0x1
7093 23:42:10.156151 DBI_WR = 0x0
7094 23:42:10.156235 DBI_RD = 0x0
7095 23:42:10.159489 OTF = 0x1
7096 23:42:10.162543 ===================================
7097 23:42:10.165847 ===================================
7098 23:42:10.165931 ANA top config
7099 23:42:10.169238 ===================================
7100 23:42:10.172615 DLL_ASYNC_EN = 0
7101 23:42:10.175998 ALL_SLAVE_EN = 0
7102 23:42:10.176081 NEW_RANK_MODE = 1
7103 23:42:10.178700 DLL_IDLE_MODE = 1
7104 23:42:10.182205 LP45_APHY_COMB_EN = 1
7105 23:42:10.185666 TX_ODT_DIS = 0
7106 23:42:10.189087 NEW_8X_MODE = 1
7107 23:42:10.189172 ===================================
7108 23:42:10.192195 ===================================
7109 23:42:10.195536 data_rate = 3200
7110 23:42:10.198864 CKR = 1
7111 23:42:10.202209 DQ_P2S_RATIO = 8
7112 23:42:10.205565 ===================================
7113 23:42:10.208768 CA_P2S_RATIO = 8
7114 23:42:10.211981 DQ_CA_OPEN = 0
7115 23:42:10.215311 DQ_SEMI_OPEN = 0
7116 23:42:10.215394 CA_SEMI_OPEN = 0
7117 23:42:10.219066 CA_FULL_RATE = 0
7118 23:42:10.222169 DQ_CKDIV4_EN = 0
7119 23:42:10.225562 CA_CKDIV4_EN = 0
7120 23:42:10.228897 CA_PREDIV_EN = 0
7121 23:42:10.232154 PH8_DLY = 12
7122 23:42:10.232238 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7123 23:42:10.235715 DQ_AAMCK_DIV = 4
7124 23:42:10.238420 CA_AAMCK_DIV = 4
7125 23:42:10.241751 CA_ADMCK_DIV = 4
7126 23:42:10.245148 DQ_TRACK_CA_EN = 0
7127 23:42:10.248601 CA_PICK = 1600
7128 23:42:10.251992 CA_MCKIO = 1600
7129 23:42:10.252076 MCKIO_SEMI = 0
7130 23:42:10.255016 PLL_FREQ = 3068
7131 23:42:10.258634 DQ_UI_PI_RATIO = 32
7132 23:42:10.261728 CA_UI_PI_RATIO = 0
7133 23:42:10.265028 ===================================
7134 23:42:10.268325 ===================================
7135 23:42:10.271694 memory_type:LPDDR4
7136 23:42:10.271778 GP_NUM : 10
7137 23:42:10.274964 SRAM_EN : 1
7138 23:42:10.278434 MD32_EN : 0
7139 23:42:10.278518 ===================================
7140 23:42:10.281503 [ANA_INIT] >>>>>>>>>>>>>>
7141 23:42:10.284992 <<<<<< [CONFIGURE PHASE]: ANA_TX
7142 23:42:10.288345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7143 23:42:10.291853 ===================================
7144 23:42:10.295244 data_rate = 3200,PCW = 0X7600
7145 23:42:10.298559 ===================================
7146 23:42:10.301640 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7147 23:42:10.308436 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7148 23:42:10.311600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7149 23:42:10.318075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7150 23:42:10.321472 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7151 23:42:10.325301 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7152 23:42:10.325399 [ANA_INIT] flow start
7153 23:42:10.328344 [ANA_INIT] PLL >>>>>>>>
7154 23:42:10.331595 [ANA_INIT] PLL <<<<<<<<
7155 23:42:10.331679 [ANA_INIT] MIDPI >>>>>>>>
7156 23:42:10.334815 [ANA_INIT] MIDPI <<<<<<<<
7157 23:42:10.338316 [ANA_INIT] DLL >>>>>>>>
7158 23:42:10.338400 [ANA_INIT] DLL <<<<<<<<
7159 23:42:10.341555 [ANA_INIT] flow end
7160 23:42:10.344813 ============ LP4 DIFF to SE enter ============
7161 23:42:10.351529 ============ LP4 DIFF to SE exit ============
7162 23:42:10.351614 [ANA_INIT] <<<<<<<<<<<<<
7163 23:42:10.354751 [Flow] Enable top DCM control >>>>>
7164 23:42:10.358198 [Flow] Enable top DCM control <<<<<
7165 23:42:10.361441 Enable DLL master slave shuffle
7166 23:42:10.367989 ==============================================================
7167 23:42:10.368074 Gating Mode config
7168 23:42:10.374591 ==============================================================
7169 23:42:10.377922 Config description:
7170 23:42:10.384500 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7171 23:42:10.391370 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7172 23:42:10.398131 SELPH_MODE 0: By rank 1: By Phase
7173 23:42:10.404548 ==============================================================
7174 23:42:10.404701 GAT_TRACK_EN = 1
7175 23:42:10.407671 RX_GATING_MODE = 2
7176 23:42:10.411225 RX_GATING_TRACK_MODE = 2
7177 23:42:10.414722 SELPH_MODE = 1
7178 23:42:10.417920 PICG_EARLY_EN = 1
7179 23:42:10.421138 VALID_LAT_VALUE = 1
7180 23:42:10.427518 ==============================================================
7181 23:42:10.431316 Enter into Gating configuration >>>>
7182 23:42:10.435111 Exit from Gating configuration <<<<
7183 23:42:10.437559 Enter into DVFS_PRE_config >>>>>
7184 23:42:10.447534 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7185 23:42:10.450948 Exit from DVFS_PRE_config <<<<<
7186 23:42:10.454314 Enter into PICG configuration >>>>
7187 23:42:10.457559 Exit from PICG configuration <<<<
7188 23:42:10.461060 [RX_INPUT] configuration >>>>>
7189 23:42:10.461144 [RX_INPUT] configuration <<<<<
7190 23:42:10.467720 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7191 23:42:10.474211 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7192 23:42:10.480709 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7193 23:42:10.483930 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7194 23:42:10.490676 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7195 23:42:10.497277 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7196 23:42:10.500898 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7197 23:42:10.504432 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7198 23:42:10.510872 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7199 23:42:10.514042 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7200 23:42:10.517492 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7201 23:42:10.524044 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7202 23:42:10.527309 ===================================
7203 23:42:10.527411 LPDDR4 DRAM CONFIGURATION
7204 23:42:10.530680 ===================================
7205 23:42:10.534055 EX_ROW_EN[0] = 0x0
7206 23:42:10.537100 EX_ROW_EN[1] = 0x0
7207 23:42:10.537182 LP4Y_EN = 0x0
7208 23:42:10.540543 WORK_FSP = 0x1
7209 23:42:10.540633 WL = 0x5
7210 23:42:10.543950 RL = 0x5
7211 23:42:10.544032 BL = 0x2
7212 23:42:10.547196 RPST = 0x0
7213 23:42:10.547313 RD_PRE = 0x0
7214 23:42:10.550591 WR_PRE = 0x1
7215 23:42:10.550672 WR_PST = 0x1
7216 23:42:10.553750 DBI_WR = 0x0
7217 23:42:10.553832 DBI_RD = 0x0
7218 23:42:10.557086 OTF = 0x1
7219 23:42:10.560305 ===================================
7220 23:42:10.563706 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7221 23:42:10.567128 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7222 23:42:10.573265 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7223 23:42:10.576706 ===================================
7224 23:42:10.576788 LPDDR4 DRAM CONFIGURATION
7225 23:42:10.580561 ===================================
7226 23:42:10.583376 EX_ROW_EN[0] = 0x10
7227 23:42:10.586596 EX_ROW_EN[1] = 0x0
7228 23:42:10.586678 LP4Y_EN = 0x0
7229 23:42:10.589935 WORK_FSP = 0x1
7230 23:42:10.590060 WL = 0x5
7231 23:42:10.593380 RL = 0x5
7232 23:42:10.593455 BL = 0x2
7233 23:42:10.597044 RPST = 0x0
7234 23:42:10.597118 RD_PRE = 0x0
7235 23:42:10.600284 WR_PRE = 0x1
7236 23:42:10.600358 WR_PST = 0x1
7237 23:42:10.603672 DBI_WR = 0x0
7238 23:42:10.603745 DBI_RD = 0x0
7239 23:42:10.606921 OTF = 0x1
7240 23:42:10.609912 ===================================
7241 23:42:10.616801 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7242 23:42:10.616879 ==
7243 23:42:10.619975 Dram Type= 6, Freq= 0, CH_0, rank 0
7244 23:42:10.622970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7245 23:42:10.623045 ==
7246 23:42:10.626338 [Duty_Offset_Calibration]
7247 23:42:10.626414 B0:2 B1:0 CA:3
7248 23:42:10.626476
7249 23:42:10.629818 [DutyScan_Calibration_Flow] k_type=0
7250 23:42:10.640408
7251 23:42:10.640488 ==CLK 0==
7252 23:42:10.643751 Final CLK duty delay cell = 0
7253 23:42:10.647065 [0] MAX Duty = 5031%(X100), DQS PI = 12
7254 23:42:10.650287 [0] MIN Duty = 4875%(X100), DQS PI = 54
7255 23:42:10.653424 [0] AVG Duty = 4953%(X100)
7256 23:42:10.653496
7257 23:42:10.656935 CH0 CLK Duty spec in!! Max-Min= 156%
7258 23:42:10.660008 [DutyScan_Calibration_Flow] ====Done====
7259 23:42:10.660078
7260 23:42:10.663097 [DutyScan_Calibration_Flow] k_type=1
7261 23:42:10.679216
7262 23:42:10.679322 ==DQS 0 ==
7263 23:42:10.682535 Final DQS duty delay cell = 0
7264 23:42:10.686031 [0] MAX Duty = 5062%(X100), DQS PI = 12
7265 23:42:10.689297 [0] MIN Duty = 4875%(X100), DQS PI = 48
7266 23:42:10.692698 [0] AVG Duty = 4968%(X100)
7267 23:42:10.692769
7268 23:42:10.692829 ==DQS 1 ==
7269 23:42:10.695692 Final DQS duty delay cell = -4
7270 23:42:10.699177 [-4] MAX Duty = 4938%(X100), DQS PI = 2
7271 23:42:10.702357 [-4] MIN Duty = 4844%(X100), DQS PI = 10
7272 23:42:10.705569 [-4] AVG Duty = 4891%(X100)
7273 23:42:10.705646
7274 23:42:10.709330 CH0 DQS 0 Duty spec in!! Max-Min= 187%
7275 23:42:10.709402
7276 23:42:10.712707 CH0 DQS 1 Duty spec in!! Max-Min= 94%
7277 23:42:10.715644 [DutyScan_Calibration_Flow] ====Done====
7278 23:42:10.715740
7279 23:42:10.718594 [DutyScan_Calibration_Flow] k_type=3
7280 23:42:10.737081
7281 23:42:10.737187 ==DQM 0 ==
7282 23:42:10.740404 Final DQM duty delay cell = 0
7283 23:42:10.743848 [0] MAX Duty = 5156%(X100), DQS PI = 30
7284 23:42:10.747120 [0] MIN Duty = 4875%(X100), DQS PI = 0
7285 23:42:10.747192 [0] AVG Duty = 5015%(X100)
7286 23:42:10.750546
7287 23:42:10.750621 ==DQM 1 ==
7288 23:42:10.754410 Final DQM duty delay cell = 4
7289 23:42:10.757104 [4] MAX Duty = 5187%(X100), DQS PI = 62
7290 23:42:10.760366 [4] MIN Duty = 5031%(X100), DQS PI = 12
7291 23:42:10.763777 [4] AVG Duty = 5109%(X100)
7292 23:42:10.763849
7293 23:42:10.767120 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7294 23:42:10.767221
7295 23:42:10.770398 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7296 23:42:10.773753 [DutyScan_Calibration_Flow] ====Done====
7297 23:42:10.773825
7298 23:42:10.777014 [DutyScan_Calibration_Flow] k_type=2
7299 23:42:10.793480
7300 23:42:10.793561 ==DQ 0 ==
7301 23:42:10.796541 Final DQ duty delay cell = -4
7302 23:42:10.799950 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7303 23:42:10.803155 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7304 23:42:10.806399 [-4] AVG Duty = 4938%(X100)
7305 23:42:10.806521
7306 23:42:10.806630 ==DQ 1 ==
7307 23:42:10.810041 Final DQ duty delay cell = 0
7308 23:42:10.813241 [0] MAX Duty = 5156%(X100), DQS PI = 58
7309 23:42:10.816721 [0] MIN Duty = 5000%(X100), DQS PI = 16
7310 23:42:10.819969 [0] AVG Duty = 5078%(X100)
7311 23:42:10.820091
7312 23:42:10.823127 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7313 23:42:10.823250
7314 23:42:10.826497 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7315 23:42:10.829617 [DutyScan_Calibration_Flow] ====Done====
7316 23:42:10.829739 ==
7317 23:42:10.832989 Dram Type= 6, Freq= 0, CH_1, rank 0
7318 23:42:10.836236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7319 23:42:10.836339 ==
7320 23:42:10.839595 [Duty_Offset_Calibration]
7321 23:42:10.839700 B0:1 B1:-2 CA:1
7322 23:42:10.839788
7323 23:42:10.843184 [DutyScan_Calibration_Flow] k_type=0
7324 23:42:10.854235
7325 23:42:10.854315 ==CLK 0==
7326 23:42:10.856970 Final CLK duty delay cell = 0
7327 23:42:10.860538 [0] MAX Duty = 5062%(X100), DQS PI = 22
7328 23:42:10.863792 [0] MIN Duty = 4844%(X100), DQS PI = 4
7329 23:42:10.863864 [0] AVG Duty = 4953%(X100)
7330 23:42:10.867132
7331 23:42:10.867212 CH1 CLK Duty spec in!! Max-Min= 218%
7332 23:42:10.873791 [DutyScan_Calibration_Flow] ====Done====
7333 23:42:10.873872
7334 23:42:10.877075 [DutyScan_Calibration_Flow] k_type=1
7335 23:42:10.892695
7336 23:42:10.892801 ==DQS 0 ==
7337 23:42:10.895668 Final DQS duty delay cell = -4
7338 23:42:10.899125 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7339 23:42:10.902736 [-4] MIN Duty = 4813%(X100), DQS PI = 52
7340 23:42:10.906225 [-4] AVG Duty = 4891%(X100)
7341 23:42:10.906298
7342 23:42:10.906358 ==DQS 1 ==
7343 23:42:10.909396 Final DQS duty delay cell = 0
7344 23:42:10.912476 [0] MAX Duty = 5093%(X100), DQS PI = 60
7345 23:42:10.915731 [0] MIN Duty = 4844%(X100), DQS PI = 24
7346 23:42:10.919513 [0] AVG Duty = 4968%(X100)
7347 23:42:10.919611
7348 23:42:10.922167 CH1 DQS 0 Duty spec in!! Max-Min= 156%
7349 23:42:10.922262
7350 23:42:10.925723 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7351 23:42:10.928877 [DutyScan_Calibration_Flow] ====Done====
7352 23:42:10.928947
7353 23:42:10.932631 [DutyScan_Calibration_Flow] k_type=3
7354 23:42:10.949574
7355 23:42:10.949651 ==DQM 0 ==
7356 23:42:10.953111 Final DQM duty delay cell = 0
7357 23:42:10.956328 [0] MAX Duty = 5031%(X100), DQS PI = 24
7358 23:42:10.959859 [0] MIN Duty = 4813%(X100), DQS PI = 54
7359 23:42:10.962998 [0] AVG Duty = 4922%(X100)
7360 23:42:10.963070
7361 23:42:10.963130 ==DQM 1 ==
7362 23:42:10.966269 Final DQM duty delay cell = 0
7363 23:42:10.969648 [0] MAX Duty = 5094%(X100), DQS PI = 36
7364 23:42:10.973107 [0] MIN Duty = 4875%(X100), DQS PI = 26
7365 23:42:10.976280 [0] AVG Duty = 4984%(X100)
7366 23:42:10.976377
7367 23:42:10.979720 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7368 23:42:10.979790
7369 23:42:10.983096 CH1 DQM 1 Duty spec in!! Max-Min= 219%
7370 23:42:10.985946 [DutyScan_Calibration_Flow] ====Done====
7371 23:42:10.986020
7372 23:42:10.989282 [DutyScan_Calibration_Flow] k_type=2
7373 23:42:11.006534
7374 23:42:11.006613 ==DQ 0 ==
7375 23:42:11.010013 Final DQ duty delay cell = 0
7376 23:42:11.013123 [0] MAX Duty = 5093%(X100), DQS PI = 20
7377 23:42:11.016477 [0] MIN Duty = 4907%(X100), DQS PI = 46
7378 23:42:11.019617 [0] AVG Duty = 5000%(X100)
7379 23:42:11.019691
7380 23:42:11.019752 ==DQ 1 ==
7381 23:42:11.023187 Final DQ duty delay cell = 0
7382 23:42:11.026577 [0] MAX Duty = 5125%(X100), DQS PI = 34
7383 23:42:11.029744 [0] MIN Duty = 4938%(X100), DQS PI = 26
7384 23:42:11.029816 [0] AVG Duty = 5031%(X100)
7385 23:42:11.033139
7386 23:42:11.036467 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7387 23:42:11.036583
7388 23:42:11.039559 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7389 23:42:11.043137 [DutyScan_Calibration_Flow] ====Done====
7390 23:42:11.046276 nWR fixed to 30
7391 23:42:11.049580 [ModeRegInit_LP4] CH0 RK0
7392 23:42:11.049652 [ModeRegInit_LP4] CH0 RK1
7393 23:42:11.052598 [ModeRegInit_LP4] CH1 RK0
7394 23:42:11.055963 [ModeRegInit_LP4] CH1 RK1
7395 23:42:11.056033 match AC timing 5
7396 23:42:11.062733 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7397 23:42:11.065732 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7398 23:42:11.069226 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7399 23:42:11.076206 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7400 23:42:11.079575 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7401 23:42:11.079704 [MiockJmeterHQA]
7402 23:42:11.079800
7403 23:42:11.082499 [DramcMiockJmeter] u1RxGatingPI = 0
7404 23:42:11.085761 0 : 4257, 4032
7405 23:42:11.085835 4 : 4255, 4029
7406 23:42:11.089026 8 : 4255, 4030
7407 23:42:11.089103 12 : 4258, 4031
7408 23:42:11.089167 16 : 4255, 4030
7409 23:42:11.092511 20 : 4252, 4027
7410 23:42:11.092621 24 : 4257, 4029
7411 23:42:11.095734 28 : 4257, 4029
7412 23:42:11.095807 32 : 4260, 4032
7413 23:42:11.099435 36 : 4257, 4029
7414 23:42:11.099534 40 : 4363, 4140
7415 23:42:11.102373 44 : 4253, 4029
7416 23:42:11.102460 48 : 4255, 4029
7417 23:42:11.102525 52 : 4257, 4032
7418 23:42:11.105615 56 : 4253, 4029
7419 23:42:11.105698 60 : 4255, 4029
7420 23:42:11.109199 64 : 4258, 4032
7421 23:42:11.109275 68 : 4365, 4140
7422 23:42:11.112280 72 : 4363, 4140
7423 23:42:11.112381 76 : 4253, 4029
7424 23:42:11.115505 80 : 4252, 4030
7425 23:42:11.115603 84 : 4257, 4032
7426 23:42:11.115672 88 : 4250, 4027
7427 23:42:11.119304 92 : 4252, 4029
7428 23:42:11.119405 96 : 4255, 4029
7429 23:42:11.122106 100 : 4253, 4029
7430 23:42:11.122177 104 : 4360, 3440
7431 23:42:11.125844 108 : 4252, 2
7432 23:42:11.125916 112 : 4255, 0
7433 23:42:11.125978 116 : 4254, 0
7434 23:42:11.129072 120 : 4255, 0
7435 23:42:11.129144 124 : 4255, 0
7436 23:42:11.132330 128 : 4252, 0
7437 23:42:11.132404 132 : 4255, 0
7438 23:42:11.132466 136 : 4255, 0
7439 23:42:11.135797 140 : 4365, 0
7440 23:42:11.135897 144 : 4252, 0
7441 23:42:11.139016 148 : 4255, 0
7442 23:42:11.139088 152 : 4253, 0
7443 23:42:11.139149 156 : 4365, 0
7444 23:42:11.142411 160 : 4255, 0
7445 23:42:11.142509 164 : 4252, 0
7446 23:42:11.142598 168 : 4252, 0
7447 23:42:11.145751 172 : 4257, 0
7448 23:42:11.145822 176 : 4252, 0
7449 23:42:11.148783 180 : 4254, 0
7450 23:42:11.148855 184 : 4252, 0
7451 23:42:11.148917 188 : 4253, 0
7452 23:42:11.152062 192 : 4254, 0
7453 23:42:11.152162 196 : 4252, 0
7454 23:42:11.155716 200 : 4258, 0
7455 23:42:11.155789 204 : 4252, 0
7456 23:42:11.155850 208 : 4252, 0
7457 23:42:11.159094 212 : 4257, 0
7458 23:42:11.159164 216 : 4363, 0
7459 23:42:11.162475 220 : 4252, 0
7460 23:42:11.162547 224 : 4363, 0
7461 23:42:11.162608 228 : 4363, 0
7462 23:42:11.165835 232 : 4252, 0
7463 23:42:11.165934 236 : 4363, 1187
7464 23:42:11.168812 240 : 4362, 4140
7465 23:42:11.168886 244 : 4365, 4140
7466 23:42:11.172303 248 : 4253, 4027
7467 23:42:11.172381 252 : 4368, 4142
7468 23:42:11.175881 256 : 4252, 4029
7469 23:42:11.175964 260 : 4252, 4030
7470 23:42:11.176029 264 : 4252, 4029
7471 23:42:11.179027 268 : 4258, 4034
7472 23:42:11.179138 272 : 4250, 4027
7473 23:42:11.182315 276 : 4252, 4029
7474 23:42:11.182397 280 : 4252, 4029
7475 23:42:11.185628 284 : 4252, 4029
7476 23:42:11.185710 288 : 4257, 4032
7477 23:42:11.188912 292 : 4252, 4029
7478 23:42:11.189027 296 : 4252, 4030
7479 23:42:11.192403 300 : 4362, 4140
7480 23:42:11.192512 304 : 4255, 4029
7481 23:42:11.195755 308 : 4365, 4139
7482 23:42:11.195831 312 : 4365, 4140
7483 23:42:11.198924 316 : 4360, 4137
7484 23:42:11.199023 320 : 4252, 4027
7485 23:42:11.199114 324 : 4255, 4029
7486 23:42:11.202315 328 : 4250, 4026
7487 23:42:11.202392 332 : 4252, 4030
7488 23:42:11.205446 336 : 4258, 4032
7489 23:42:11.205524 340 : 4366, 4140
7490 23:42:11.208538 344 : 4363, 4140
7491 23:42:11.208652 348 : 4252, 4029
7492 23:42:11.211874 352 : 4363, 4099
7493 23:42:11.211945 356 : 4366, 2905
7494 23:42:11.215462 360 : 4255, 0
7495 23:42:11.215564
7496 23:42:11.215653 MIOCK jitter meter ch=0
7497 23:42:11.215739
7498 23:42:11.218511 1T = (360-108) = 252 dly cells
7499 23:42:11.224889 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7500 23:42:11.224993 ==
7501 23:42:11.228220 Dram Type= 6, Freq= 0, CH_0, rank 0
7502 23:42:11.232437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7503 23:42:11.232510 ==
7504 23:42:11.238397 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7505 23:42:11.241721 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7506 23:42:11.245023 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7507 23:42:11.251753 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7508 23:42:11.261374 [CA 0] Center 44 (14~75) winsize 62
7509 23:42:11.264847 [CA 1] Center 43 (13~74) winsize 62
7510 23:42:11.268059 [CA 2] Center 40 (11~69) winsize 59
7511 23:42:11.271450 [CA 3] Center 39 (10~68) winsize 59
7512 23:42:11.274690 [CA 4] Center 37 (8~67) winsize 60
7513 23:42:11.277919 [CA 5] Center 37 (7~67) winsize 61
7514 23:42:11.277991
7515 23:42:11.281406 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7516 23:42:11.281478
7517 23:42:11.287957 [CATrainingPosCal] consider 1 rank data
7518 23:42:11.288033 u2DelayCellTimex100 = 258/100 ps
7519 23:42:11.294785 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7520 23:42:11.297744 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7521 23:42:11.301242 CA2 delay=40 (11~69),Diff = 3 PI (11 cell)
7522 23:42:11.304425 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7523 23:42:11.307710 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7524 23:42:11.311276 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7525 23:42:11.311377
7526 23:42:11.314453 CA PerBit enable=1, Macro0, CA PI delay=37
7527 23:42:11.314527
7528 23:42:11.317696 [CBTSetCACLKResult] CA Dly = 37
7529 23:42:11.321083 CS Dly: 11 (0~42)
7530 23:42:11.324759 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7531 23:42:11.328065 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7532 23:42:11.328137 ==
7533 23:42:11.331122 Dram Type= 6, Freq= 0, CH_0, rank 1
7534 23:42:11.337855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7535 23:42:11.337932 ==
7536 23:42:11.340998 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7537 23:42:11.347621 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7538 23:42:11.350903 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7539 23:42:11.357584 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7540 23:42:11.365623 [CA 0] Center 44 (13~75) winsize 63
7541 23:42:11.368931 [CA 1] Center 43 (13~74) winsize 62
7542 23:42:11.371908 [CA 2] Center 39 (10~69) winsize 60
7543 23:42:11.375189 [CA 3] Center 39 (10~68) winsize 59
7544 23:42:11.378599 [CA 4] Center 37 (7~67) winsize 61
7545 23:42:11.381846 [CA 5] Center 36 (7~66) winsize 60
7546 23:42:11.381919
7547 23:42:11.385195 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7548 23:42:11.385281
7549 23:42:11.391838 [CATrainingPosCal] consider 2 rank data
7550 23:42:11.391924 u2DelayCellTimex100 = 258/100 ps
7551 23:42:11.398343 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7552 23:42:11.401664 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7553 23:42:11.405130 CA2 delay=40 (11~69),Diff = 4 PI (15 cell)
7554 23:42:11.408483 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7555 23:42:11.411894 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7556 23:42:11.415030 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7557 23:42:11.415101
7558 23:42:11.418185 CA PerBit enable=1, Macro0, CA PI delay=36
7559 23:42:11.418257
7560 23:42:11.421934 [CBTSetCACLKResult] CA Dly = 36
7561 23:42:11.425281 CS Dly: 11 (0~42)
7562 23:42:11.428408 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7563 23:42:11.431776 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7564 23:42:11.431848
7565 23:42:11.435110 ----->DramcWriteLeveling(PI) begin...
7566 23:42:11.438102 ==
7567 23:42:11.438177 Dram Type= 6, Freq= 0, CH_0, rank 0
7568 23:42:11.444643 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 23:42:11.444766 ==
7570 23:42:11.448186 Write leveling (Byte 0): 34 => 34
7571 23:42:11.451370 Write leveling (Byte 1): 30 => 30
7572 23:42:11.454862 DramcWriteLeveling(PI) end<-----
7573 23:42:11.454935
7574 23:42:11.455000 ==
7575 23:42:11.458055 Dram Type= 6, Freq= 0, CH_0, rank 0
7576 23:42:11.461477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7577 23:42:11.461574 ==
7578 23:42:11.464964 [Gating] SW mode calibration
7579 23:42:11.471334 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7580 23:42:11.478020 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7581 23:42:11.481197 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 23:42:11.484506 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 23:42:11.491224 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 23:42:11.494294 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 23:42:11.497841 1 4 16 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7586 23:42:11.500946 1 4 20 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
7587 23:42:11.507654 1 4 24 | B1->B0 | 3131 3434 | 0 1 | (1 1) (1 1)
7588 23:42:11.511107 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 23:42:11.514559 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 23:42:11.521041 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 23:42:11.524667 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 23:42:11.527699 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 23:42:11.534097 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
7594 23:42:11.537528 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 0) (1 0)
7595 23:42:11.540922 1 5 24 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
7596 23:42:11.547114 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 23:42:11.551118 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 23:42:11.554235 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 23:42:11.560457 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 23:42:11.563873 1 6 12 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7601 23:42:11.567237 1 6 16 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7602 23:42:11.573703 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7603 23:42:11.577342 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7604 23:42:11.580756 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 23:42:11.586913 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 23:42:11.590497 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 23:42:11.593890 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 23:42:11.600024 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 23:42:11.603922 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7610 23:42:11.606738 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7611 23:42:11.613399 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7612 23:42:11.616753 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 23:42:11.620264 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 23:42:11.626890 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 23:42:11.629819 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 23:42:11.633460 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 23:42:11.639743 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 23:42:11.643242 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 23:42:11.646563 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 23:42:11.652930 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 23:42:11.656706 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 23:42:11.659817 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 23:42:11.666428 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 23:42:11.669710 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7625 23:42:11.673237 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7626 23:42:11.679602 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7627 23:42:11.679722 Total UI for P1: 0, mck2ui 16
7628 23:42:11.686558 best dqsien dly found for B0: ( 1, 9, 14)
7629 23:42:11.689839 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 23:42:11.693065 Total UI for P1: 0, mck2ui 16
7631 23:42:11.696247 best dqsien dly found for B1: ( 1, 9, 22)
7632 23:42:11.699663 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7633 23:42:11.702935 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7634 23:42:11.703017
7635 23:42:11.706128 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7636 23:42:11.709561 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7637 23:42:11.713091 [Gating] SW calibration Done
7638 23:42:11.713174 ==
7639 23:42:11.716088 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 23:42:11.719525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 23:42:11.723313 ==
7642 23:42:11.723395 RX Vref Scan: 0
7643 23:42:11.723460
7644 23:42:11.726377 RX Vref 0 -> 0, step: 1
7645 23:42:11.726458
7646 23:42:11.726552 RX Delay 0 -> 252, step: 8
7647 23:42:11.733108 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7648 23:42:11.736115 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7649 23:42:11.739848 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7650 23:42:11.743147 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7651 23:42:11.745946 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7652 23:42:11.752947 iDelay=200, Bit 5, Center 115 (64 ~ 167) 104
7653 23:42:11.756058 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7654 23:42:11.759492 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7655 23:42:11.762785 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7656 23:42:11.766340 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7657 23:42:11.773045 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7658 23:42:11.776342 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7659 23:42:11.779697 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7660 23:42:11.782864 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7661 23:42:11.786125 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7662 23:42:11.793026 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7663 23:42:11.793109 ==
7664 23:42:11.796148 Dram Type= 6, Freq= 0, CH_0, rank 0
7665 23:42:11.799432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7666 23:42:11.799533 ==
7667 23:42:11.799623 DQS Delay:
7668 23:42:11.802712 DQS0 = 0, DQS1 = 0
7669 23:42:11.802788 DQM Delay:
7670 23:42:11.805967 DQM0 = 128, DQM1 = 124
7671 23:42:11.806037 DQ Delay:
7672 23:42:11.809524 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7673 23:42:11.812834 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
7674 23:42:11.816082 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7675 23:42:11.819300 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7676 23:42:11.822748
7677 23:42:11.822847
7678 23:42:11.822936 ==
7679 23:42:11.825780 Dram Type= 6, Freq= 0, CH_0, rank 0
7680 23:42:11.829502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7681 23:42:11.829584 ==
7682 23:42:11.829680
7683 23:42:11.829741
7684 23:42:11.832620 TX Vref Scan disable
7685 23:42:11.832732 == TX Byte 0 ==
7686 23:42:11.839213 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7687 23:42:11.842360 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7688 23:42:11.842442 == TX Byte 1 ==
7689 23:42:11.849383 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7690 23:42:11.852930 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7691 23:42:11.853027 ==
7692 23:42:11.855652 Dram Type= 6, Freq= 0, CH_0, rank 0
7693 23:42:11.859386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7694 23:42:11.859509 ==
7695 23:42:11.873151
7696 23:42:11.876119 TX Vref early break, caculate TX vref
7697 23:42:11.879570 TX Vref=16, minBit 0, minWin=21, winSum=351
7698 23:42:11.882788 TX Vref=18, minBit 4, minWin=22, winSum=364
7699 23:42:11.885966 TX Vref=20, minBit 0, minWin=22, winSum=376
7700 23:42:11.889232 TX Vref=22, minBit 11, minWin=23, winSum=388
7701 23:42:11.892699 TX Vref=24, minBit 0, minWin=24, winSum=391
7702 23:42:11.899321 TX Vref=26, minBit 7, minWin=24, winSum=405
7703 23:42:11.902501 TX Vref=28, minBit 4, minWin=24, winSum=403
7704 23:42:11.905729 TX Vref=30, minBit 0, minWin=24, winSum=398
7705 23:42:11.909128 TX Vref=32, minBit 8, minWin=23, winSum=388
7706 23:42:11.912647 TX Vref=34, minBit 0, minWin=23, winSum=377
7707 23:42:11.919224 [TxChooseVref] Worse bit 7, Min win 24, Win sum 405, Final Vref 26
7708 23:42:11.919337
7709 23:42:11.922659 Final TX Range 0 Vref 26
7710 23:42:11.922741
7711 23:42:11.922806 ==
7712 23:42:11.925937 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 23:42:11.929064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 23:42:11.929146 ==
7715 23:42:11.929212
7716 23:42:11.929273
7717 23:42:11.932460 TX Vref Scan disable
7718 23:42:11.939153 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7719 23:42:11.939295 == TX Byte 0 ==
7720 23:42:11.942469 u2DelayCellOfst[0]=15 cells (4 PI)
7721 23:42:11.945687 u2DelayCellOfst[1]=18 cells (5 PI)
7722 23:42:11.948885 u2DelayCellOfst[2]=11 cells (3 PI)
7723 23:42:11.952232 u2DelayCellOfst[3]=15 cells (4 PI)
7724 23:42:11.955888 u2DelayCellOfst[4]=7 cells (2 PI)
7725 23:42:11.958912 u2DelayCellOfst[5]=0 cells (0 PI)
7726 23:42:11.962160 u2DelayCellOfst[6]=18 cells (5 PI)
7727 23:42:11.965765 u2DelayCellOfst[7]=18 cells (5 PI)
7728 23:42:11.968719 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7729 23:42:11.972515 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7730 23:42:11.975416 == TX Byte 1 ==
7731 23:42:11.978662 u2DelayCellOfst[8]=0 cells (0 PI)
7732 23:42:11.978762 u2DelayCellOfst[9]=0 cells (0 PI)
7733 23:42:11.982480 u2DelayCellOfst[10]=3 cells (1 PI)
7734 23:42:11.985411 u2DelayCellOfst[11]=3 cells (1 PI)
7735 23:42:11.988685 u2DelayCellOfst[12]=11 cells (3 PI)
7736 23:42:11.992053 u2DelayCellOfst[13]=7 cells (2 PI)
7737 23:42:11.995555 u2DelayCellOfst[14]=15 cells (4 PI)
7738 23:42:11.998716 u2DelayCellOfst[15]=7 cells (2 PI)
7739 23:42:12.002097 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7740 23:42:12.008711 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7741 23:42:12.008837 DramC Write-DBI on
7742 23:42:12.008950 ==
7743 23:42:12.012033 Dram Type= 6, Freq= 0, CH_0, rank 0
7744 23:42:12.018780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7745 23:42:12.018903 ==
7746 23:42:12.019017
7747 23:42:12.019128
7748 23:42:12.019238 TX Vref Scan disable
7749 23:42:12.022209 == TX Byte 0 ==
7750 23:42:12.025369 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7751 23:42:12.028803 == TX Byte 1 ==
7752 23:42:12.032141 Update DQM dly =727 (2 ,6, 23) DQM OEN =(3 ,3)
7753 23:42:12.035340 DramC Write-DBI off
7754 23:42:12.035460
7755 23:42:12.035573 [DATLAT]
7756 23:42:12.035685 Freq=1600, CH0 RK0
7757 23:42:12.035790
7758 23:42:12.038865 DATLAT Default: 0xf
7759 23:42:12.038984 0, 0xFFFF, sum = 0
7760 23:42:12.042317 1, 0xFFFF, sum = 0
7761 23:42:12.045705 2, 0xFFFF, sum = 0
7762 23:42:12.045830 3, 0xFFFF, sum = 0
7763 23:42:12.048888 4, 0xFFFF, sum = 0
7764 23:42:12.049010 5, 0xFFFF, sum = 0
7765 23:42:12.052004 6, 0xFFFF, sum = 0
7766 23:42:12.052122 7, 0xFFFF, sum = 0
7767 23:42:12.055417 8, 0xFFFF, sum = 0
7768 23:42:12.055539 9, 0xFFFF, sum = 0
7769 23:42:12.058878 10, 0xFFFF, sum = 0
7770 23:42:12.059001 11, 0xFFFF, sum = 0
7771 23:42:12.062101 12, 0xFFFF, sum = 0
7772 23:42:12.062226 13, 0xEFFF, sum = 0
7773 23:42:12.065193 14, 0x0, sum = 1
7774 23:42:12.065317 15, 0x0, sum = 2
7775 23:42:12.068533 16, 0x0, sum = 3
7776 23:42:12.068678 17, 0x0, sum = 4
7777 23:42:12.072002 best_step = 15
7778 23:42:12.072122
7779 23:42:12.072229 ==
7780 23:42:12.074943 Dram Type= 6, Freq= 0, CH_0, rank 0
7781 23:42:12.078639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7782 23:42:12.078738 ==
7783 23:42:12.082017 RX Vref Scan: 1
7784 23:42:12.082113
7785 23:42:12.082202 Set Vref Range= 24 -> 127
7786 23:42:12.082287
7787 23:42:12.085423 RX Vref 24 -> 127, step: 1
7788 23:42:12.085520
7789 23:42:12.088390 RX Delay 11 -> 252, step: 4
7790 23:42:12.088473
7791 23:42:12.091886 Set Vref, RX VrefLevel [Byte0]: 24
7792 23:42:12.095280 [Byte1]: 24
7793 23:42:12.095408
7794 23:42:12.098483 Set Vref, RX VrefLevel [Byte0]: 25
7795 23:42:12.101611 [Byte1]: 25
7796 23:42:12.105081
7797 23:42:12.105183 Set Vref, RX VrefLevel [Byte0]: 26
7798 23:42:12.108314 [Byte1]: 26
7799 23:42:12.112407
7800 23:42:12.112517 Set Vref, RX VrefLevel [Byte0]: 27
7801 23:42:12.115907 [Byte1]: 27
7802 23:42:12.120186
7803 23:42:12.120268 Set Vref, RX VrefLevel [Byte0]: 28
7804 23:42:12.123328 [Byte1]: 28
7805 23:42:12.127826
7806 23:42:12.127907 Set Vref, RX VrefLevel [Byte0]: 29
7807 23:42:12.131114 [Byte1]: 29
7808 23:42:12.135550
7809 23:42:12.135631 Set Vref, RX VrefLevel [Byte0]: 30
7810 23:42:12.138929 [Byte1]: 30
7811 23:42:12.142875
7812 23:42:12.142956 Set Vref, RX VrefLevel [Byte0]: 31
7813 23:42:12.146288 [Byte1]: 31
7814 23:42:12.150992
7815 23:42:12.151075 Set Vref, RX VrefLevel [Byte0]: 32
7816 23:42:12.154225 [Byte1]: 32
7817 23:42:12.158355
7818 23:42:12.158436 Set Vref, RX VrefLevel [Byte0]: 33
7819 23:42:12.161524 [Byte1]: 33
7820 23:42:12.166171
7821 23:42:12.169403 Set Vref, RX VrefLevel [Byte0]: 34
7822 23:42:12.172508 [Byte1]: 34
7823 23:42:12.172612
7824 23:42:12.175668 Set Vref, RX VrefLevel [Byte0]: 35
7825 23:42:12.179051 [Byte1]: 35
7826 23:42:12.179133
7827 23:42:12.182446 Set Vref, RX VrefLevel [Byte0]: 36
7828 23:42:12.185689 [Byte1]: 36
7829 23:42:12.189144
7830 23:42:12.189229 Set Vref, RX VrefLevel [Byte0]: 37
7831 23:42:12.192781 [Byte1]: 37
7832 23:42:12.196190
7833 23:42:12.196271 Set Vref, RX VrefLevel [Byte0]: 38
7834 23:42:12.199394 [Byte1]: 38
7835 23:42:12.203816
7836 23:42:12.203897 Set Vref, RX VrefLevel [Byte0]: 39
7837 23:42:12.207324 [Byte1]: 39
7838 23:42:12.211567
7839 23:42:12.211648 Set Vref, RX VrefLevel [Byte0]: 40
7840 23:42:12.214743 [Byte1]: 40
7841 23:42:12.219200
7842 23:42:12.219281 Set Vref, RX VrefLevel [Byte0]: 41
7843 23:42:12.222285 [Byte1]: 41
7844 23:42:12.226772
7845 23:42:12.226853 Set Vref, RX VrefLevel [Byte0]: 42
7846 23:42:12.230168 [Byte1]: 42
7847 23:42:12.234551
7848 23:42:12.234632 Set Vref, RX VrefLevel [Byte0]: 43
7849 23:42:12.237965 [Byte1]: 43
7850 23:42:12.241823
7851 23:42:12.241904 Set Vref, RX VrefLevel [Byte0]: 44
7852 23:42:12.245043 [Byte1]: 44
7853 23:42:12.249499
7854 23:42:12.249580 Set Vref, RX VrefLevel [Byte0]: 45
7855 23:42:12.253163 [Byte1]: 45
7856 23:42:12.257295
7857 23:42:12.257376 Set Vref, RX VrefLevel [Byte0]: 46
7858 23:42:12.260562 [Byte1]: 46
7859 23:42:12.264758
7860 23:42:12.264839 Set Vref, RX VrefLevel [Byte0]: 47
7861 23:42:12.268534 [Byte1]: 47
7862 23:42:12.272408
7863 23:42:12.272489 Set Vref, RX VrefLevel [Byte0]: 48
7864 23:42:12.275753 [Byte1]: 48
7865 23:42:12.280206
7866 23:42:12.280306 Set Vref, RX VrefLevel [Byte0]: 49
7867 23:42:12.283472 [Byte1]: 49
7868 23:42:12.287989
7869 23:42:12.288070 Set Vref, RX VrefLevel [Byte0]: 50
7870 23:42:12.290877 [Byte1]: 50
7871 23:42:12.295313
7872 23:42:12.295394 Set Vref, RX VrefLevel [Byte0]: 51
7873 23:42:12.298616 [Byte1]: 51
7874 23:42:12.302944
7875 23:42:12.303026 Set Vref, RX VrefLevel [Byte0]: 52
7876 23:42:12.306341 [Byte1]: 52
7877 23:42:12.310629
7878 23:42:12.310710 Set Vref, RX VrefLevel [Byte0]: 53
7879 23:42:12.313836 [Byte1]: 53
7880 23:42:12.317986
7881 23:42:12.318068 Set Vref, RX VrefLevel [Byte0]: 54
7882 23:42:12.321144 [Byte1]: 54
7883 23:42:12.325637
7884 23:42:12.325719 Set Vref, RX VrefLevel [Byte0]: 55
7885 23:42:12.328858 [Byte1]: 55
7886 23:42:12.333285
7887 23:42:12.333382 Set Vref, RX VrefLevel [Byte0]: 56
7888 23:42:12.336403 [Byte1]: 56
7889 23:42:12.340955
7890 23:42:12.341036 Set Vref, RX VrefLevel [Byte0]: 57
7891 23:42:12.344294 [Byte1]: 57
7892 23:42:12.348833
7893 23:42:12.348914 Set Vref, RX VrefLevel [Byte0]: 58
7894 23:42:12.351720 [Byte1]: 58
7895 23:42:12.356081
7896 23:42:12.356162 Set Vref, RX VrefLevel [Byte0]: 59
7897 23:42:12.359518 [Byte1]: 59
7898 23:42:12.363840
7899 23:42:12.363922 Set Vref, RX VrefLevel [Byte0]: 60
7900 23:42:12.367266 [Byte1]: 60
7901 23:42:12.371470
7902 23:42:12.371551 Set Vref, RX VrefLevel [Byte0]: 61
7903 23:42:12.375219 [Byte1]: 61
7904 23:42:12.379363
7905 23:42:12.379445 Set Vref, RX VrefLevel [Byte0]: 62
7906 23:42:12.382127 [Byte1]: 62
7907 23:42:12.386448
7908 23:42:12.386555 Set Vref, RX VrefLevel [Byte0]: 63
7909 23:42:12.389940 [Byte1]: 63
7910 23:42:12.394141
7911 23:42:12.394223 Set Vref, RX VrefLevel [Byte0]: 64
7912 23:42:12.397779 [Byte1]: 64
7913 23:42:12.402295
7914 23:42:12.402376 Set Vref, RX VrefLevel [Byte0]: 65
7915 23:42:12.405237 [Byte1]: 65
7916 23:42:12.409670
7917 23:42:12.409752 Set Vref, RX VrefLevel [Byte0]: 66
7918 23:42:12.412562 [Byte1]: 66
7919 23:42:12.416971
7920 23:42:12.417052 Set Vref, RX VrefLevel [Byte0]: 67
7921 23:42:12.420431 [Byte1]: 67
7922 23:42:12.424605
7923 23:42:12.424687 Set Vref, RX VrefLevel [Byte0]: 68
7924 23:42:12.428062 [Byte1]: 68
7925 23:42:12.432057
7926 23:42:12.432138 Set Vref, RX VrefLevel [Byte0]: 69
7927 23:42:12.435875 [Byte1]: 69
7928 23:42:12.439816
7929 23:42:12.439897 Set Vref, RX VrefLevel [Byte0]: 70
7930 23:42:12.443429 [Byte1]: 70
7931 23:42:12.447430
7932 23:42:12.447512 Set Vref, RX VrefLevel [Byte0]: 71
7933 23:42:12.451189 [Byte1]: 71
7934 23:42:12.455021
7935 23:42:12.455103 Set Vref, RX VrefLevel [Byte0]: 72
7936 23:42:12.458312 [Byte1]: 72
7937 23:42:12.462502
7938 23:42:12.462615 Set Vref, RX VrefLevel [Byte0]: 73
7939 23:42:12.466041 [Byte1]: 73
7940 23:42:12.470508
7941 23:42:12.470589 Set Vref, RX VrefLevel [Byte0]: 74
7942 23:42:12.474042 [Byte1]: 74
7943 23:42:12.477962
7944 23:42:12.478132 Set Vref, RX VrefLevel [Byte0]: 75
7945 23:42:12.481367 [Byte1]: 75
7946 23:42:12.485662
7947 23:42:12.485744 Set Vref, RX VrefLevel [Byte0]: 76
7948 23:42:12.488884 [Byte1]: 76
7949 23:42:12.493287
7950 23:42:12.493368 Final RX Vref Byte 0 = 62 to rank0
7951 23:42:12.496696 Final RX Vref Byte 1 = 60 to rank0
7952 23:42:12.500130 Final RX Vref Byte 0 = 62 to rank1
7953 23:42:12.503329 Final RX Vref Byte 1 = 60 to rank1==
7954 23:42:12.506562 Dram Type= 6, Freq= 0, CH_0, rank 0
7955 23:42:12.512999 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7956 23:42:12.513082 ==
7957 23:42:12.513147 DQS Delay:
7958 23:42:12.516294 DQS0 = 0, DQS1 = 0
7959 23:42:12.516376 DQM Delay:
7960 23:42:12.516441 DQM0 = 126, DQM1 = 120
7961 23:42:12.519641 DQ Delay:
7962 23:42:12.523081 DQ0 =124, DQ1 =128, DQ2 =126, DQ3 =122
7963 23:42:12.526170 DQ4 =126, DQ5 =112, DQ6 =132, DQ7 =138
7964 23:42:12.529379 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7965 23:42:12.532995 DQ12 =126, DQ13 =124, DQ14 =132, DQ15 =128
7966 23:42:12.533070
7967 23:42:12.533134
7968 23:42:12.533194
7969 23:42:12.536163 [DramC_TX_OE_Calibration] TA2
7970 23:42:12.539269 Original DQ_B0 (3 6) =30, OEN = 27
7971 23:42:12.542642 Original DQ_B1 (3 6) =30, OEN = 27
7972 23:42:12.546215 24, 0x0, End_B0=24 End_B1=24
7973 23:42:12.546285 25, 0x0, End_B0=25 End_B1=25
7974 23:42:12.549648 26, 0x0, End_B0=26 End_B1=26
7975 23:42:12.552952 27, 0x0, End_B0=27 End_B1=27
7976 23:42:12.555820 28, 0x0, End_B0=28 End_B1=28
7977 23:42:12.559638 29, 0x0, End_B0=29 End_B1=29
7978 23:42:12.559706 30, 0x0, End_B0=30 End_B1=30
7979 23:42:12.562967 31, 0x4141, End_B0=30 End_B1=30
7980 23:42:12.565809 Byte0 end_step=30 best_step=27
7981 23:42:12.569418 Byte1 end_step=30 best_step=27
7982 23:42:12.572491 Byte0 TX OE(2T, 0.5T) = (3, 3)
7983 23:42:12.576280 Byte1 TX OE(2T, 0.5T) = (3, 3)
7984 23:42:12.576350
7985 23:42:12.576410
7986 23:42:12.582789 [DQSOSCAuto] RK0, (LSB)MR18= 0x1716, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 398 ps
7987 23:42:12.586063 CH0 RK0: MR19=303, MR18=1716
7988 23:42:12.592566 CH0_RK0: MR19=0x303, MR18=0x1716, DQSOSC=398, MR23=63, INC=23, DEC=15
7989 23:42:12.592682
7990 23:42:12.595907 ----->DramcWriteLeveling(PI) begin...
7991 23:42:12.595979 ==
7992 23:42:12.599269 Dram Type= 6, Freq= 0, CH_0, rank 1
7993 23:42:12.602487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7994 23:42:12.602583 ==
7995 23:42:12.605810 Write leveling (Byte 0): 32 => 32
7996 23:42:12.608927 Write leveling (Byte 1): 29 => 29
7997 23:42:12.612274 DramcWriteLeveling(PI) end<-----
7998 23:42:12.612344
7999 23:42:12.612406 ==
8000 23:42:12.615767 Dram Type= 6, Freq= 0, CH_0, rank 1
8001 23:42:12.619022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8002 23:42:12.619119 ==
8003 23:42:12.622315 [Gating] SW mode calibration
8004 23:42:12.629170 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8005 23:42:12.635623 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8006 23:42:12.639194 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 23:42:12.645564 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 23:42:12.649271 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 23:42:12.652343 1 4 12 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8010 23:42:12.659033 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8011 23:42:12.662409 1 4 20 | B1->B0 | 3433 3434 | 1 1 | (1 1) (1 1)
8012 23:42:12.665744 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 23:42:12.671849 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 23:42:12.675570 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 23:42:12.678446 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 23:42:12.685349 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8017 23:42:12.688489 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
8018 23:42:12.691876 1 5 16 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8019 23:42:12.698407 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8020 23:42:12.701718 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 23:42:12.704974 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 23:42:12.708254 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 23:42:12.714896 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 23:42:12.718140 1 6 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8025 23:42:12.721699 1 6 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
8026 23:42:12.728343 1 6 16 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
8027 23:42:12.731644 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8028 23:42:12.734927 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 23:42:12.741480 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 23:42:12.744693 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 23:42:12.748408 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 23:42:12.755118 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8033 23:42:12.758069 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8034 23:42:12.761249 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8035 23:42:12.767793 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8036 23:42:12.771651 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 23:42:12.774470 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 23:42:12.781164 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 23:42:12.784719 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 23:42:12.788208 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 23:42:12.794524 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 23:42:12.798211 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 23:42:12.800940 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 23:42:12.807981 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 23:42:12.811258 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 23:42:12.814519 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 23:42:12.821169 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 23:42:12.824409 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8049 23:42:12.827786 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8050 23:42:12.831093 Total UI for P1: 0, mck2ui 16
8051 23:42:12.834545 best dqsien dly found for B0: ( 1, 9, 8)
8052 23:42:12.840808 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8053 23:42:12.844393 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8054 23:42:12.847491 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 23:42:12.851013 Total UI for P1: 0, mck2ui 16
8056 23:42:12.854226 best dqsien dly found for B1: ( 1, 9, 16)
8057 23:42:12.857453 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8058 23:42:12.860761 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8059 23:42:12.860838
8060 23:42:12.864201 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8061 23:42:12.870779 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8062 23:42:12.870879 [Gating] SW calibration Done
8063 23:42:12.874139 ==
8064 23:42:12.874234 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 23:42:12.880657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 23:42:12.880743 ==
8067 23:42:12.880835 RX Vref Scan: 0
8068 23:42:12.880924
8069 23:42:12.883874 RX Vref 0 -> 0, step: 1
8070 23:42:12.884001
8071 23:42:12.887202 RX Delay 0 -> 252, step: 8
8072 23:42:12.890427 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8073 23:42:12.893716 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8074 23:42:12.897212 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8075 23:42:12.903887 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8076 23:42:12.907595 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8077 23:42:12.910782 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8078 23:42:12.914024 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8079 23:42:12.917200 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8080 23:42:12.923720 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8081 23:42:12.927245 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8082 23:42:12.930625 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8083 23:42:12.933745 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8084 23:42:12.937081 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8085 23:42:12.943704 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8086 23:42:12.947370 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8087 23:42:12.950366 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8088 23:42:12.950441 ==
8089 23:42:12.953729 Dram Type= 6, Freq= 0, CH_0, rank 1
8090 23:42:12.957458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8091 23:42:12.957530 ==
8092 23:42:12.960443 DQS Delay:
8093 23:42:12.960541 DQS0 = 0, DQS1 = 0
8094 23:42:12.963730 DQM Delay:
8095 23:42:12.963798 DQM0 = 127, DQM1 = 122
8096 23:42:12.967190 DQ Delay:
8097 23:42:12.970436 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8098 23:42:12.973743 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8099 23:42:12.977062 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8100 23:42:12.980540 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
8101 23:42:12.980672
8102 23:42:12.980761
8103 23:42:12.980847 ==
8104 23:42:12.983781 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 23:42:12.986963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 23:42:12.987056 ==
8107 23:42:12.987145
8108 23:42:12.987231
8109 23:42:12.990416 TX Vref Scan disable
8110 23:42:12.993702 == TX Byte 0 ==
8111 23:42:12.997050 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8112 23:42:13.000388 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8113 23:42:13.003729 == TX Byte 1 ==
8114 23:42:13.007043 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8115 23:42:13.010254 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8116 23:42:13.010353 ==
8117 23:42:13.013950 Dram Type= 6, Freq= 0, CH_0, rank 1
8118 23:42:13.017279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8119 23:42:13.020041 ==
8120 23:42:13.032886
8121 23:42:13.036145 TX Vref early break, caculate TX vref
8122 23:42:13.039512 TX Vref=16, minBit 8, minWin=21, winSum=360
8123 23:42:13.042788 TX Vref=18, minBit 1, minWin=22, winSum=372
8124 23:42:13.046197 TX Vref=20, minBit 8, minWin=22, winSum=375
8125 23:42:13.049633 TX Vref=22, minBit 1, minWin=23, winSum=382
8126 23:42:13.052917 TX Vref=24, minBit 0, minWin=24, winSum=393
8127 23:42:13.059044 TX Vref=26, minBit 9, minWin=24, winSum=399
8128 23:42:13.062301 TX Vref=28, minBit 8, minWin=24, winSum=401
8129 23:42:13.065774 TX Vref=30, minBit 8, minWin=23, winSum=399
8130 23:42:13.068958 TX Vref=32, minBit 8, minWin=23, winSum=392
8131 23:42:13.072215 TX Vref=34, minBit 9, minWin=22, winSum=383
8132 23:42:13.075536 TX Vref=36, minBit 8, minWin=22, winSum=376
8133 23:42:13.082244 [TxChooseVref] Worse bit 8, Min win 24, Win sum 401, Final Vref 28
8134 23:42:13.082317
8135 23:42:13.085489 Final TX Range 0 Vref 28
8136 23:42:13.085557
8137 23:42:13.085617 ==
8138 23:42:13.089200 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 23:42:13.092521 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 23:42:13.092657 ==
8141 23:42:13.092750
8142 23:42:13.092837
8143 23:42:13.095872 TX Vref Scan disable
8144 23:42:13.102457 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8145 23:42:13.102557 == TX Byte 0 ==
8146 23:42:13.105593 u2DelayCellOfst[0]=15 cells (4 PI)
8147 23:42:13.109321 u2DelayCellOfst[1]=15 cells (4 PI)
8148 23:42:13.112045 u2DelayCellOfst[2]=11 cells (3 PI)
8149 23:42:13.115274 u2DelayCellOfst[3]=11 cells (3 PI)
8150 23:42:13.118855 u2DelayCellOfst[4]=7 cells (2 PI)
8151 23:42:13.121917 u2DelayCellOfst[5]=0 cells (0 PI)
8152 23:42:13.125389 u2DelayCellOfst[6]=18 cells (5 PI)
8153 23:42:13.128580 u2DelayCellOfst[7]=18 cells (5 PI)
8154 23:42:13.132171 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8155 23:42:13.135422 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8156 23:42:13.138767 == TX Byte 1 ==
8157 23:42:13.142070 u2DelayCellOfst[8]=0 cells (0 PI)
8158 23:42:13.145047 u2DelayCellOfst[9]=0 cells (0 PI)
8159 23:42:13.148401 u2DelayCellOfst[10]=7 cells (2 PI)
8160 23:42:13.148494 u2DelayCellOfst[11]=3 cells (1 PI)
8161 23:42:13.151629 u2DelayCellOfst[12]=11 cells (3 PI)
8162 23:42:13.155018 u2DelayCellOfst[13]=11 cells (3 PI)
8163 23:42:13.158370 u2DelayCellOfst[14]=15 cells (4 PI)
8164 23:42:13.161739 u2DelayCellOfst[15]=11 cells (3 PI)
8165 23:42:13.168491 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8166 23:42:13.171557 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8167 23:42:13.171639 DramC Write-DBI on
8168 23:42:13.175012 ==
8169 23:42:13.175094 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 23:42:13.181665 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 23:42:13.181744 ==
8172 23:42:13.181808
8173 23:42:13.181869
8174 23:42:13.185003 TX Vref Scan disable
8175 23:42:13.185072 == TX Byte 0 ==
8176 23:42:13.191698 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8177 23:42:13.191774 == TX Byte 1 ==
8178 23:42:13.194790 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8179 23:42:13.198046 DramC Write-DBI off
8180 23:42:13.198142
8181 23:42:13.198232 [DATLAT]
8182 23:42:13.201419 Freq=1600, CH0 RK1
8183 23:42:13.201515
8184 23:42:13.201602 DATLAT Default: 0xf
8185 23:42:13.204766 0, 0xFFFF, sum = 0
8186 23:42:13.204838 1, 0xFFFF, sum = 0
8187 23:42:13.207838 2, 0xFFFF, sum = 0
8188 23:42:13.207908 3, 0xFFFF, sum = 0
8189 23:42:13.211078 4, 0xFFFF, sum = 0
8190 23:42:13.211180 5, 0xFFFF, sum = 0
8191 23:42:13.214408 6, 0xFFFF, sum = 0
8192 23:42:13.214480 7, 0xFFFF, sum = 0
8193 23:42:13.217786 8, 0xFFFF, sum = 0
8194 23:42:13.221450 9, 0xFFFF, sum = 0
8195 23:42:13.221523 10, 0xFFFF, sum = 0
8196 23:42:13.224436 11, 0xFFFF, sum = 0
8197 23:42:13.224511 12, 0xFFFF, sum = 0
8198 23:42:13.227973 13, 0xCFFF, sum = 0
8199 23:42:13.228041 14, 0x0, sum = 1
8200 23:42:13.231155 15, 0x0, sum = 2
8201 23:42:13.231226 16, 0x0, sum = 3
8202 23:42:13.234316 17, 0x0, sum = 4
8203 23:42:13.234387 best_step = 15
8204 23:42:13.234450
8205 23:42:13.234530 ==
8206 23:42:13.237962 Dram Type= 6, Freq= 0, CH_0, rank 1
8207 23:42:13.241154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8208 23:42:13.241228 ==
8209 23:42:13.244783 RX Vref Scan: 0
8210 23:42:13.244854
8211 23:42:13.247781 RX Vref 0 -> 0, step: 1
8212 23:42:13.247883
8213 23:42:13.247973 RX Delay 3 -> 252, step: 4
8214 23:42:13.255065 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8215 23:42:13.257874 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8216 23:42:13.261636 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8217 23:42:13.264865 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8218 23:42:13.270994 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8219 23:42:13.274360 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8220 23:42:13.277716 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8221 23:42:13.281042 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8222 23:42:13.284230 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8223 23:42:13.291010 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8224 23:42:13.294296 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8225 23:42:13.297554 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8226 23:42:13.301235 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8227 23:42:13.304527 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8228 23:42:13.310816 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8229 23:42:13.313954 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8230 23:42:13.314035 ==
8231 23:42:13.317396 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 23:42:13.320941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 23:42:13.321023 ==
8234 23:42:13.324159 DQS Delay:
8235 23:42:13.324239 DQS0 = 0, DQS1 = 0
8236 23:42:13.324303 DQM Delay:
8237 23:42:13.327410 DQM0 = 124, DQM1 = 118
8238 23:42:13.327513 DQ Delay:
8239 23:42:13.330747 DQ0 =124, DQ1 =126, DQ2 =122, DQ3 =122
8240 23:42:13.334239 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8241 23:42:13.340765 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8242 23:42:13.343908 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8243 23:42:13.343988
8244 23:42:13.344052
8245 23:42:13.344111
8246 23:42:13.347193 [DramC_TX_OE_Calibration] TA2
8247 23:42:13.350481 Original DQ_B0 (3 6) =30, OEN = 27
8248 23:42:13.353745 Original DQ_B1 (3 6) =30, OEN = 27
8249 23:42:13.353827 24, 0x0, End_B0=24 End_B1=24
8250 23:42:13.357434 25, 0x0, End_B0=25 End_B1=25
8251 23:42:13.360399 26, 0x0, End_B0=26 End_B1=26
8252 23:42:13.364025 27, 0x0, End_B0=27 End_B1=27
8253 23:42:13.364107 28, 0x0, End_B0=28 End_B1=28
8254 23:42:13.366926 29, 0x0, End_B0=29 End_B1=29
8255 23:42:13.370229 30, 0x0, End_B0=30 End_B1=30
8256 23:42:13.373570 31, 0x4545, End_B0=30 End_B1=30
8257 23:42:13.376976 Byte0 end_step=30 best_step=27
8258 23:42:13.380322 Byte1 end_step=30 best_step=27
8259 23:42:13.380458 Byte0 TX OE(2T, 0.5T) = (3, 3)
8260 23:42:13.383578 Byte1 TX OE(2T, 0.5T) = (3, 3)
8261 23:42:13.383698
8262 23:42:13.383809
8263 23:42:13.393705 [DQSOSCAuto] RK1, (LSB)MR18= 0x2513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8264 23:42:13.396855 CH0 RK1: MR19=303, MR18=2513
8265 23:42:13.400186 CH0_RK1: MR19=0x303, MR18=0x2513, DQSOSC=391, MR23=63, INC=24, DEC=16
8266 23:42:13.403441 [RxdqsGatingPostProcess] freq 1600
8267 23:42:13.410008 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8268 23:42:13.413571 best DQS0 dly(2T, 0.5T) = (1, 1)
8269 23:42:13.416981 best DQS1 dly(2T, 0.5T) = (1, 1)
8270 23:42:13.420221 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8271 23:42:13.423425 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8272 23:42:13.426800 best DQS0 dly(2T, 0.5T) = (1, 1)
8273 23:42:13.426881 best DQS1 dly(2T, 0.5T) = (1, 1)
8274 23:42:13.430225 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8275 23:42:13.433527 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8276 23:42:13.437014 Pre-setting of DQS Precalculation
8277 23:42:13.443572 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8278 23:42:13.443655 ==
8279 23:42:13.446352 Dram Type= 6, Freq= 0, CH_1, rank 0
8280 23:42:13.450350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8281 23:42:13.450433 ==
8282 23:42:13.456365 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8283 23:42:13.459810 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8284 23:42:13.463076 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8285 23:42:13.470054 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8286 23:42:13.478937 [CA 0] Center 41 (12~71) winsize 60
8287 23:42:13.482262 [CA 1] Center 42 (13~72) winsize 60
8288 23:42:13.485553 [CA 2] Center 37 (9~66) winsize 58
8289 23:42:13.488869 [CA 3] Center 36 (7~66) winsize 60
8290 23:42:13.492276 [CA 4] Center 37 (8~67) winsize 60
8291 23:42:13.495621 [CA 5] Center 37 (8~66) winsize 59
8292 23:42:13.495717
8293 23:42:13.499027 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8294 23:42:13.499108
8295 23:42:13.502211 [CATrainingPosCal] consider 1 rank data
8296 23:42:13.505575 u2DelayCellTimex100 = 258/100 ps
8297 23:42:13.511909 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8298 23:42:13.515368 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8299 23:42:13.518663 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8300 23:42:13.522191 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8301 23:42:13.525292 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8302 23:42:13.528484 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8303 23:42:13.528622
8304 23:42:13.532032 CA PerBit enable=1, Macro0, CA PI delay=36
8305 23:42:13.532152
8306 23:42:13.535001 [CBTSetCACLKResult] CA Dly = 36
8307 23:42:13.538352 CS Dly: 9 (0~40)
8308 23:42:13.542014 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8309 23:42:13.544802 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8310 23:42:13.544921 ==
8311 23:42:13.548275 Dram Type= 6, Freq= 0, CH_1, rank 1
8312 23:42:13.554810 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8313 23:42:13.554931 ==
8314 23:42:13.558346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8315 23:42:13.561763 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8316 23:42:13.568479 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8317 23:42:13.574762 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8318 23:42:13.582222 [CA 0] Center 42 (13~71) winsize 59
8319 23:42:13.585708 [CA 1] Center 42 (12~72) winsize 61
8320 23:42:13.588733 [CA 2] Center 37 (8~67) winsize 60
8321 23:42:13.592019 [CA 3] Center 36 (7~66) winsize 60
8322 23:42:13.595700 [CA 4] Center 37 (8~67) winsize 60
8323 23:42:13.598771 [CA 5] Center 36 (6~66) winsize 61
8324 23:42:13.598894
8325 23:42:13.602104 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8326 23:42:13.602224
8327 23:42:13.605743 [CATrainingPosCal] consider 2 rank data
8328 23:42:13.608496 u2DelayCellTimex100 = 258/100 ps
8329 23:42:13.611821 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8330 23:42:13.618537 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8331 23:42:13.622225 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8332 23:42:13.625316 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8333 23:42:13.628896 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8334 23:42:13.631799 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8335 23:42:13.631918
8336 23:42:13.635352 CA PerBit enable=1, Macro0, CA PI delay=36
8337 23:42:13.635472
8338 23:42:13.638596 [CBTSetCACLKResult] CA Dly = 36
8339 23:42:13.642287 CS Dly: 10 (0~43)
8340 23:42:13.645494 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8341 23:42:13.648472 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8342 23:42:13.648634
8343 23:42:13.652044 ----->DramcWriteLeveling(PI) begin...
8344 23:42:13.652167 ==
8345 23:42:13.655498 Dram Type= 6, Freq= 0, CH_1, rank 0
8346 23:42:13.661523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8347 23:42:13.661646 ==
8348 23:42:13.664888 Write leveling (Byte 0): 26 => 26
8349 23:42:13.665009 Write leveling (Byte 1): 27 => 27
8350 23:42:13.668220 DramcWriteLeveling(PI) end<-----
8351 23:42:13.668342
8352 23:42:13.668456 ==
8353 23:42:13.671725 Dram Type= 6, Freq= 0, CH_1, rank 0
8354 23:42:13.678225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8355 23:42:13.678349 ==
8356 23:42:13.681717 [Gating] SW mode calibration
8357 23:42:13.688244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8358 23:42:13.691606 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8359 23:42:13.698049 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 23:42:13.701688 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 23:42:13.704530 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 23:42:13.711572 1 4 12 | B1->B0 | 2525 2322 | 0 1 | (0 0) (0 0)
8363 23:42:13.714535 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8364 23:42:13.717843 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 23:42:13.724474 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 23:42:13.727918 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 23:42:13.731356 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 23:42:13.737778 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 23:42:13.741300 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 23:42:13.744726 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8371 23:42:13.751377 1 5 16 | B1->B0 | 2525 2727 | 0 0 | (1 0) (1 0)
8372 23:42:13.754393 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 23:42:13.757809 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 23:42:13.764601 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 23:42:13.767828 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 23:42:13.771123 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 23:42:13.774666 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 23:42:13.781272 1 6 12 | B1->B0 | 3232 2727 | 0 0 | (0 0) (0 0)
8379 23:42:13.784431 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8380 23:42:13.787649 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 23:42:13.794160 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 23:42:13.797437 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 23:42:13.800711 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 23:42:13.807323 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 23:42:13.810860 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 23:42:13.814133 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 23:42:13.820490 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8388 23:42:13.823964 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8389 23:42:13.827263 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 23:42:13.833955 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 23:42:13.837213 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 23:42:13.840530 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 23:42:13.847089 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 23:42:13.850548 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 23:42:13.853993 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 23:42:13.860318 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 23:42:13.863582 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 23:42:13.866862 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 23:42:13.873442 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 23:42:13.876972 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 23:42:13.880049 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 23:42:13.886795 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8403 23:42:13.890066 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8404 23:42:13.893757 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 23:42:13.896763 Total UI for P1: 0, mck2ui 16
8406 23:42:13.900109 best dqsien dly found for B0: ( 1, 9, 14)
8407 23:42:13.903405 Total UI for P1: 0, mck2ui 16
8408 23:42:13.906764 best dqsien dly found for B1: ( 1, 9, 14)
8409 23:42:13.910055 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8410 23:42:13.913183 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8411 23:42:13.913257
8412 23:42:13.920051 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8413 23:42:13.923554 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8414 23:42:13.926741 [Gating] SW calibration Done
8415 23:42:13.926815 ==
8416 23:42:13.930111 Dram Type= 6, Freq= 0, CH_1, rank 0
8417 23:42:13.933236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8418 23:42:13.933314 ==
8419 23:42:13.933385 RX Vref Scan: 0
8420 23:42:13.933445
8421 23:42:13.936519 RX Vref 0 -> 0, step: 1
8422 23:42:13.936609
8423 23:42:13.939977 RX Delay 0 -> 252, step: 8
8424 23:42:13.943306 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8425 23:42:13.946236 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8426 23:42:13.952953 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8427 23:42:13.956212 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8428 23:42:13.959594 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8429 23:42:13.962878 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8430 23:42:13.966421 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8431 23:42:13.973092 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8432 23:42:13.976376 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8433 23:42:13.979604 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8434 23:42:13.982849 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8435 23:42:13.985971 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8436 23:42:13.992702 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8437 23:42:13.996266 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8438 23:42:13.999338 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8439 23:42:14.002435 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8440 23:42:14.002516 ==
8441 23:42:14.005768 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 23:42:14.012478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 23:42:14.012618 ==
8444 23:42:14.012685 DQS Delay:
8445 23:42:14.016200 DQS0 = 0, DQS1 = 0
8446 23:42:14.016281 DQM Delay:
8447 23:42:14.016345 DQM0 = 132, DQM1 = 125
8448 23:42:14.018989 DQ Delay:
8449 23:42:14.022579 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8450 23:42:14.025747 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =131
8451 23:42:14.029093 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8452 23:42:14.032615 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8453 23:42:14.032696
8454 23:42:14.032761
8455 23:42:14.032821 ==
8456 23:42:14.035974 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 23:42:14.039159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 23:42:14.042519 ==
8459 23:42:14.042600
8460 23:42:14.042664
8461 23:42:14.042724 TX Vref Scan disable
8462 23:42:14.046009 == TX Byte 0 ==
8463 23:42:14.048989 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8464 23:42:14.052491 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8465 23:42:14.055781 == TX Byte 1 ==
8466 23:42:14.059267 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8467 23:42:14.062102 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8468 23:42:14.065729 ==
8469 23:42:14.069149 Dram Type= 6, Freq= 0, CH_1, rank 0
8470 23:42:14.072026 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8471 23:42:14.072108 ==
8472 23:42:14.085552
8473 23:42:14.088904 TX Vref early break, caculate TX vref
8474 23:42:14.092115 TX Vref=16, minBit 5, minWin=22, winSum=365
8475 23:42:14.095701 TX Vref=18, minBit 5, minWin=21, winSum=368
8476 23:42:14.098532 TX Vref=20, minBit 1, minWin=23, winSum=384
8477 23:42:14.102091 TX Vref=22, minBit 9, minWin=23, winSum=393
8478 23:42:14.105281 TX Vref=24, minBit 1, minWin=24, winSum=403
8479 23:42:14.112268 TX Vref=26, minBit 1, minWin=25, winSum=412
8480 23:42:14.115591 TX Vref=28, minBit 5, minWin=24, winSum=416
8481 23:42:14.118887 TX Vref=30, minBit 1, minWin=24, winSum=414
8482 23:42:14.122229 TX Vref=32, minBit 1, minWin=24, winSum=406
8483 23:42:14.125353 TX Vref=34, minBit 1, minWin=23, winSum=397
8484 23:42:14.129005 TX Vref=36, minBit 0, minWin=23, winSum=387
8485 23:42:14.135566 [TxChooseVref] Worse bit 1, Min win 25, Win sum 412, Final Vref 26
8486 23:42:14.135646
8487 23:42:14.138761 Final TX Range 0 Vref 26
8488 23:42:14.138842
8489 23:42:14.138906 ==
8490 23:42:14.142169 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 23:42:14.145451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 23:42:14.145532 ==
8493 23:42:14.145596
8494 23:42:14.145657
8495 23:42:14.148832 TX Vref Scan disable
8496 23:42:14.155457 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8497 23:42:14.155553 == TX Byte 0 ==
8498 23:42:14.158550 u2DelayCellOfst[0]=22 cells (6 PI)
8499 23:42:14.162030 u2DelayCellOfst[1]=15 cells (4 PI)
8500 23:42:14.165200 u2DelayCellOfst[2]=0 cells (0 PI)
8501 23:42:14.168329 u2DelayCellOfst[3]=7 cells (2 PI)
8502 23:42:14.172272 u2DelayCellOfst[4]=11 cells (3 PI)
8503 23:42:14.175208 u2DelayCellOfst[5]=26 cells (7 PI)
8504 23:42:14.178601 u2DelayCellOfst[6]=22 cells (6 PI)
8505 23:42:14.181968 u2DelayCellOfst[7]=7 cells (2 PI)
8506 23:42:14.184871 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8507 23:42:14.188167 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8508 23:42:14.192131 == TX Byte 1 ==
8509 23:42:14.195000 u2DelayCellOfst[8]=0 cells (0 PI)
8510 23:42:14.195133 u2DelayCellOfst[9]=7 cells (2 PI)
8511 23:42:14.198311 u2DelayCellOfst[10]=15 cells (4 PI)
8512 23:42:14.201566 u2DelayCellOfst[11]=11 cells (3 PI)
8513 23:42:14.205084 u2DelayCellOfst[12]=15 cells (4 PI)
8514 23:42:14.208671 u2DelayCellOfst[13]=22 cells (6 PI)
8515 23:42:14.211468 u2DelayCellOfst[14]=22 cells (6 PI)
8516 23:42:14.214654 u2DelayCellOfst[15]=22 cells (6 PI)
8517 23:42:14.221134 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8518 23:42:14.224743 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8519 23:42:14.224868 DramC Write-DBI on
8520 23:42:14.224982 ==
8521 23:42:14.228009 Dram Type= 6, Freq= 0, CH_1, rank 0
8522 23:42:14.234838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8523 23:42:14.234970 ==
8524 23:42:14.235082
8525 23:42:14.235190
8526 23:42:14.235299 TX Vref Scan disable
8527 23:42:14.238693 == TX Byte 0 ==
8528 23:42:14.242011 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8529 23:42:14.245281 == TX Byte 1 ==
8530 23:42:14.248685 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8531 23:42:14.251947 DramC Write-DBI off
8532 23:42:14.252051
8533 23:42:14.252150 [DATLAT]
8534 23:42:14.252239 Freq=1600, CH1 RK0
8535 23:42:14.252326
8536 23:42:14.255345 DATLAT Default: 0xf
8537 23:42:14.255444 0, 0xFFFF, sum = 0
8538 23:42:14.258765 1, 0xFFFF, sum = 0
8539 23:42:14.261834 2, 0xFFFF, sum = 0
8540 23:42:14.261917 3, 0xFFFF, sum = 0
8541 23:42:14.265123 4, 0xFFFF, sum = 0
8542 23:42:14.265211 5, 0xFFFF, sum = 0
8543 23:42:14.268852 6, 0xFFFF, sum = 0
8544 23:42:14.268934 7, 0xFFFF, sum = 0
8545 23:42:14.272230 8, 0xFFFF, sum = 0
8546 23:42:14.272321 9, 0xFFFF, sum = 0
8547 23:42:14.274991 10, 0xFFFF, sum = 0
8548 23:42:14.275074 11, 0xFFFF, sum = 0
8549 23:42:14.278603 12, 0xFFFF, sum = 0
8550 23:42:14.278680 13, 0x8FFF, sum = 0
8551 23:42:14.281725 14, 0x0, sum = 1
8552 23:42:14.281797 15, 0x0, sum = 2
8553 23:42:14.284916 16, 0x0, sum = 3
8554 23:42:14.285047 17, 0x0, sum = 4
8555 23:42:14.288440 best_step = 15
8556 23:42:14.288581
8557 23:42:14.288710 ==
8558 23:42:14.291769 Dram Type= 6, Freq= 0, CH_1, rank 0
8559 23:42:14.295239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8560 23:42:14.295351 ==
8561 23:42:14.298691 RX Vref Scan: 1
8562 23:42:14.298775
8563 23:42:14.298859 Set Vref Range= 24 -> 127
8564 23:42:14.298939
8565 23:42:14.301878 RX Vref 24 -> 127, step: 1
8566 23:42:14.301962
8567 23:42:14.305288 RX Delay 11 -> 252, step: 4
8568 23:42:14.305372
8569 23:42:14.308450 Set Vref, RX VrefLevel [Byte0]: 24
8570 23:42:14.311721 [Byte1]: 24
8571 23:42:14.311805
8572 23:42:14.314982 Set Vref, RX VrefLevel [Byte0]: 25
8573 23:42:14.318251 [Byte1]: 25
8574 23:42:14.321606
8575 23:42:14.321690 Set Vref, RX VrefLevel [Byte0]: 26
8576 23:42:14.324894 [Byte1]: 26
8577 23:42:14.329178
8578 23:42:14.329262 Set Vref, RX VrefLevel [Byte0]: 27
8579 23:42:14.332524 [Byte1]: 27
8580 23:42:14.337107
8581 23:42:14.337191 Set Vref, RX VrefLevel [Byte0]: 28
8582 23:42:14.339967 [Byte1]: 28
8583 23:42:14.344150
8584 23:42:14.344234 Set Vref, RX VrefLevel [Byte0]: 29
8585 23:42:14.347718 [Byte1]: 29
8586 23:42:14.352168
8587 23:42:14.352252 Set Vref, RX VrefLevel [Byte0]: 30
8588 23:42:14.355437 [Byte1]: 30
8589 23:42:14.359974
8590 23:42:14.360058 Set Vref, RX VrefLevel [Byte0]: 31
8591 23:42:14.362808 [Byte1]: 31
8592 23:42:14.367472
8593 23:42:14.367556 Set Vref, RX VrefLevel [Byte0]: 32
8594 23:42:14.370617 [Byte1]: 32
8595 23:42:14.374622
8596 23:42:14.374703 Set Vref, RX VrefLevel [Byte0]: 33
8597 23:42:14.378278 [Byte1]: 33
8598 23:42:14.382434
8599 23:42:14.382509 Set Vref, RX VrefLevel [Byte0]: 34
8600 23:42:14.385703 [Byte1]: 34
8601 23:42:14.390226
8602 23:42:14.390348 Set Vref, RX VrefLevel [Byte0]: 35
8603 23:42:14.393228 [Byte1]: 35
8604 23:42:14.397756
8605 23:42:14.397840 Set Vref, RX VrefLevel [Byte0]: 36
8606 23:42:14.401048 [Byte1]: 36
8607 23:42:14.405244
8608 23:42:14.405328 Set Vref, RX VrefLevel [Byte0]: 37
8609 23:42:14.408482 [Byte1]: 37
8610 23:42:14.412997
8611 23:42:14.413081 Set Vref, RX VrefLevel [Byte0]: 38
8612 23:42:14.416208 [Byte1]: 38
8613 23:42:14.420431
8614 23:42:14.420515 Set Vref, RX VrefLevel [Byte0]: 39
8615 23:42:14.423577 [Byte1]: 39
8616 23:42:14.428378
8617 23:42:14.428462 Set Vref, RX VrefLevel [Byte0]: 40
8618 23:42:14.431931 [Byte1]: 40
8619 23:42:14.435727
8620 23:42:14.435812 Set Vref, RX VrefLevel [Byte0]: 41
8621 23:42:14.438787 [Byte1]: 41
8622 23:42:14.443479
8623 23:42:14.443562 Set Vref, RX VrefLevel [Byte0]: 42
8624 23:42:14.446488 [Byte1]: 42
8625 23:42:14.450675
8626 23:42:14.450762 Set Vref, RX VrefLevel [Byte0]: 43
8627 23:42:14.454147 [Byte1]: 43
8628 23:42:14.458645
8629 23:42:14.458729 Set Vref, RX VrefLevel [Byte0]: 44
8630 23:42:14.461889 [Byte1]: 44
8631 23:42:14.466436
8632 23:42:14.466520 Set Vref, RX VrefLevel [Byte0]: 45
8633 23:42:14.469690 [Byte1]: 45
8634 23:42:14.473749
8635 23:42:14.473831 Set Vref, RX VrefLevel [Byte0]: 46
8636 23:42:14.477066 [Byte1]: 46
8637 23:42:14.481598
8638 23:42:14.481681 Set Vref, RX VrefLevel [Byte0]: 47
8639 23:42:14.484918 [Byte1]: 47
8640 23:42:14.489295
8641 23:42:14.489379 Set Vref, RX VrefLevel [Byte0]: 48
8642 23:42:14.492657 [Byte1]: 48
8643 23:42:14.496653
8644 23:42:14.496736 Set Vref, RX VrefLevel [Byte0]: 49
8645 23:42:14.500124 [Byte1]: 49
8646 23:42:14.504110
8647 23:42:14.504218 Set Vref, RX VrefLevel [Byte0]: 50
8648 23:42:14.507615 [Byte1]: 50
8649 23:42:14.511622
8650 23:42:14.511705 Set Vref, RX VrefLevel [Byte0]: 51
8651 23:42:14.514961 [Byte1]: 51
8652 23:42:14.519615
8653 23:42:14.519699 Set Vref, RX VrefLevel [Byte0]: 52
8654 23:42:14.522968 [Byte1]: 52
8655 23:42:14.527265
8656 23:42:14.527348 Set Vref, RX VrefLevel [Byte0]: 53
8657 23:42:14.530261 [Byte1]: 53
8658 23:42:14.534932
8659 23:42:14.535015 Set Vref, RX VrefLevel [Byte0]: 54
8660 23:42:14.537739 [Byte1]: 54
8661 23:42:14.542202
8662 23:42:14.542285 Set Vref, RX VrefLevel [Byte0]: 55
8663 23:42:14.545527 [Byte1]: 55
8664 23:42:14.549712
8665 23:42:14.549796 Set Vref, RX VrefLevel [Byte0]: 56
8666 23:42:14.553077 [Byte1]: 56
8667 23:42:14.557405
8668 23:42:14.557489 Set Vref, RX VrefLevel [Byte0]: 57
8669 23:42:14.560837 [Byte1]: 57
8670 23:42:14.565245
8671 23:42:14.565329 Set Vref, RX VrefLevel [Byte0]: 58
8672 23:42:14.568525 [Byte1]: 58
8673 23:42:14.572967
8674 23:42:14.573050 Set Vref, RX VrefLevel [Byte0]: 59
8675 23:42:14.576269 [Byte1]: 59
8676 23:42:14.580212
8677 23:42:14.580295 Set Vref, RX VrefLevel [Byte0]: 60
8678 23:42:14.583640 [Byte1]: 60
8679 23:42:14.588143
8680 23:42:14.588245 Set Vref, RX VrefLevel [Byte0]: 61
8681 23:42:14.590993 [Byte1]: 61
8682 23:42:14.595422
8683 23:42:14.595506 Set Vref, RX VrefLevel [Byte0]: 62
8684 23:42:14.598690 [Byte1]: 62
8685 23:42:14.603269
8686 23:42:14.603353 Set Vref, RX VrefLevel [Byte0]: 63
8687 23:42:14.606482 [Byte1]: 63
8688 23:42:14.610756
8689 23:42:14.610840 Set Vref, RX VrefLevel [Byte0]: 64
8690 23:42:14.614190 [Byte1]: 64
8691 23:42:14.618365
8692 23:42:14.618449 Set Vref, RX VrefLevel [Byte0]: 65
8693 23:42:14.621509 [Byte1]: 65
8694 23:42:14.626315
8695 23:42:14.626398 Set Vref, RX VrefLevel [Byte0]: 66
8696 23:42:14.629190 [Byte1]: 66
8697 23:42:14.633709
8698 23:42:14.633793 Set Vref, RX VrefLevel [Byte0]: 67
8699 23:42:14.637228 [Byte1]: 67
8700 23:42:14.641334
8701 23:42:14.641418 Set Vref, RX VrefLevel [Byte0]: 68
8702 23:42:14.644740 [Byte1]: 68
8703 23:42:14.649122
8704 23:42:14.649206 Set Vref, RX VrefLevel [Byte0]: 69
8705 23:42:14.652166 [Byte1]: 69
8706 23:42:14.656380
8707 23:42:14.656491 Set Vref, RX VrefLevel [Byte0]: 70
8708 23:42:14.659628 [Byte1]: 70
8709 23:42:14.664181
8710 23:42:14.664262 Set Vref, RX VrefLevel [Byte0]: 71
8711 23:42:14.667462 [Byte1]: 71
8712 23:42:14.671682
8713 23:42:14.671763 Final RX Vref Byte 0 = 57 to rank0
8714 23:42:14.674826 Final RX Vref Byte 1 = 54 to rank0
8715 23:42:14.678310 Final RX Vref Byte 0 = 57 to rank1
8716 23:42:14.681722 Final RX Vref Byte 1 = 54 to rank1==
8717 23:42:14.684958 Dram Type= 6, Freq= 0, CH_1, rank 0
8718 23:42:14.691644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8719 23:42:14.691726 ==
8720 23:42:14.691791 DQS Delay:
8721 23:42:14.691852 DQS0 = 0, DQS1 = 0
8722 23:42:14.694972 DQM Delay:
8723 23:42:14.695056 DQM0 = 131, DQM1 = 123
8724 23:42:14.698216 DQ Delay:
8725 23:42:14.701712 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =130
8726 23:42:14.704533 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8727 23:42:14.708325 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8728 23:42:14.711155 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8729 23:42:14.711262
8730 23:42:14.711347
8731 23:42:14.711426
8732 23:42:14.714882 [DramC_TX_OE_Calibration] TA2
8733 23:42:14.718359 Original DQ_B0 (3 6) =30, OEN = 27
8734 23:42:14.721394 Original DQ_B1 (3 6) =30, OEN = 27
8735 23:42:14.724533 24, 0x0, End_B0=24 End_B1=24
8736 23:42:14.724667 25, 0x0, End_B0=25 End_B1=25
8737 23:42:14.727899 26, 0x0, End_B0=26 End_B1=26
8738 23:42:14.731263 27, 0x0, End_B0=27 End_B1=27
8739 23:42:14.734398 28, 0x0, End_B0=28 End_B1=28
8740 23:42:14.738037 29, 0x0, End_B0=29 End_B1=29
8741 23:42:14.738143 30, 0x0, End_B0=30 End_B1=30
8742 23:42:14.741418 31, 0x4545, End_B0=30 End_B1=30
8743 23:42:14.744424 Byte0 end_step=30 best_step=27
8744 23:42:14.747598 Byte1 end_step=30 best_step=27
8745 23:42:14.750939 Byte0 TX OE(2T, 0.5T) = (3, 3)
8746 23:42:14.754543 Byte1 TX OE(2T, 0.5T) = (3, 3)
8747 23:42:14.754641
8748 23:42:14.754723
8749 23:42:14.760932 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8750 23:42:14.764267 CH1 RK0: MR19=303, MR18=B0F
8751 23:42:14.770904 CH1_RK0: MR19=0x303, MR18=0xB0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8752 23:42:14.770989
8753 23:42:14.774167 ----->DramcWriteLeveling(PI) begin...
8754 23:42:14.774252 ==
8755 23:42:14.777686 Dram Type= 6, Freq= 0, CH_1, rank 1
8756 23:42:14.780989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8757 23:42:14.781074 ==
8758 23:42:14.784282 Write leveling (Byte 0): 24 => 24
8759 23:42:14.787491 Write leveling (Byte 1): 27 => 27
8760 23:42:14.790433 DramcWriteLeveling(PI) end<-----
8761 23:42:14.790555
8762 23:42:14.790639 ==
8763 23:42:14.793809 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 23:42:14.797168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 23:42:14.797254 ==
8766 23:42:14.800452 [Gating] SW mode calibration
8767 23:42:14.807256 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8768 23:42:14.813953 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8769 23:42:14.817076 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 23:42:14.823643 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 23:42:14.827306 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8772 23:42:14.830033 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
8773 23:42:14.836728 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8774 23:42:14.840393 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8775 23:42:14.843615 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8776 23:42:14.849876 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8777 23:42:14.853391 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8778 23:42:14.856790 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8779 23:42:14.863380 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
8780 23:42:14.866713 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
8781 23:42:14.869908 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8782 23:42:14.876432 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8783 23:42:14.879704 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8784 23:42:14.883052 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8785 23:42:14.889801 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8786 23:42:14.893170 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8787 23:42:14.896299 1 6 8 | B1->B0 | 2525 4141 | 0 0 | (0 0) (0 0)
8788 23:42:14.899875 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8789 23:42:14.906375 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8790 23:42:14.909564 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 23:42:14.912760 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8792 23:42:14.919397 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8793 23:42:14.923149 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 23:42:14.926488 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 23:42:14.932965 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8796 23:42:14.936238 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8797 23:42:14.939603 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 23:42:14.945892 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8799 23:42:14.949176 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8800 23:42:14.953060 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8801 23:42:14.959720 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8802 23:42:14.962548 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8803 23:42:14.966000 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8804 23:42:14.972480 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8805 23:42:14.975893 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 23:42:14.979185 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 23:42:14.986221 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 23:42:14.989124 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 23:42:14.992929 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 23:42:14.999488 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 23:42:15.002796 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8812 23:42:15.005876 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8813 23:42:15.009160 Total UI for P1: 0, mck2ui 16
8814 23:42:15.012498 best dqsien dly found for B0: ( 1, 9, 8)
8815 23:42:15.019412 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 23:42:15.019497 Total UI for P1: 0, mck2ui 16
8817 23:42:15.025475 best dqsien dly found for B1: ( 1, 9, 10)
8818 23:42:15.029281 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8819 23:42:15.032041 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8820 23:42:15.032124
8821 23:42:15.035504 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8822 23:42:15.039327 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8823 23:42:15.042490 [Gating] SW calibration Done
8824 23:42:15.042572 ==
8825 23:42:15.045771 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 23:42:15.048875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 23:42:15.048957 ==
8828 23:42:15.052538 RX Vref Scan: 0
8829 23:42:15.052700
8830 23:42:15.052770 RX Vref 0 -> 0, step: 1
8831 23:42:15.052834
8832 23:42:15.055753 RX Delay 0 -> 252, step: 8
8833 23:42:15.059191 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8834 23:42:15.065950 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8835 23:42:15.069265 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8836 23:42:15.072509 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8837 23:42:15.075462 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8838 23:42:15.079184 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8839 23:42:15.085593 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8840 23:42:15.088610 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8841 23:42:15.092299 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8842 23:42:15.095274 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8843 23:42:15.098380 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8844 23:42:15.105205 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8845 23:42:15.108361 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8846 23:42:15.111761 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8847 23:42:15.115094 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8848 23:42:15.118720 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8849 23:42:15.121863 ==
8850 23:42:15.121972 Dram Type= 6, Freq= 0, CH_1, rank 1
8851 23:42:15.128764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8852 23:42:15.128874 ==
8853 23:42:15.128991 DQS Delay:
8854 23:42:15.132033 DQS0 = 0, DQS1 = 0
8855 23:42:15.132180 DQM Delay:
8856 23:42:15.134710 DQM0 = 130, DQM1 = 128
8857 23:42:15.134837 DQ Delay:
8858 23:42:15.138173 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =127
8859 23:42:15.142051 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =127
8860 23:42:15.145160 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8861 23:42:15.148331 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8862 23:42:15.148412
8863 23:42:15.148477
8864 23:42:15.148538 ==
8865 23:42:15.151707 Dram Type= 6, Freq= 0, CH_1, rank 1
8866 23:42:15.158462 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8867 23:42:15.158545 ==
8868 23:42:15.158642
8869 23:42:15.158704
8870 23:42:15.158762 TX Vref Scan disable
8871 23:42:15.162182 == TX Byte 0 ==
8872 23:42:15.165418 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8873 23:42:15.168717 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8874 23:42:15.172145 == TX Byte 1 ==
8875 23:42:15.175404 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8876 23:42:15.181674 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8877 23:42:15.181802 ==
8878 23:42:15.185038 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 23:42:15.188261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 23:42:15.188387 ==
8881 23:42:15.201153
8882 23:42:15.204520 TX Vref early break, caculate TX vref
8883 23:42:15.207537 TX Vref=16, minBit 0, minWin=23, winSum=384
8884 23:42:15.210859 TX Vref=18, minBit 0, minWin=23, winSum=396
8885 23:42:15.214609 TX Vref=20, minBit 5, minWin=24, winSum=407
8886 23:42:15.217987 TX Vref=22, minBit 0, minWin=24, winSum=411
8887 23:42:15.220798 TX Vref=24, minBit 6, minWin=25, winSum=423
8888 23:42:15.227894 TX Vref=26, minBit 0, minWin=26, winSum=429
8889 23:42:15.230695 TX Vref=28, minBit 0, minWin=25, winSum=427
8890 23:42:15.233882 TX Vref=30, minBit 1, minWin=24, winSum=424
8891 23:42:15.237676 TX Vref=32, minBit 1, minWin=24, winSum=413
8892 23:42:15.240499 TX Vref=34, minBit 1, minWin=24, winSum=406
8893 23:42:15.247683 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 26
8894 23:42:15.247766
8895 23:42:15.251084 Final TX Range 0 Vref 26
8896 23:42:15.251171
8897 23:42:15.251237 ==
8898 23:42:15.253835 Dram Type= 6, Freq= 0, CH_1, rank 1
8899 23:42:15.257113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8900 23:42:15.257244 ==
8901 23:42:15.257356
8902 23:42:15.257468
8903 23:42:15.260353 TX Vref Scan disable
8904 23:42:15.267268 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8905 23:42:15.267393 == TX Byte 0 ==
8906 23:42:15.270189 u2DelayCellOfst[0]=18 cells (5 PI)
8907 23:42:15.273969 u2DelayCellOfst[1]=15 cells (4 PI)
8908 23:42:15.277343 u2DelayCellOfst[2]=0 cells (0 PI)
8909 23:42:15.280105 u2DelayCellOfst[3]=7 cells (2 PI)
8910 23:42:15.283532 u2DelayCellOfst[4]=7 cells (2 PI)
8911 23:42:15.286838 u2DelayCellOfst[5]=22 cells (6 PI)
8912 23:42:15.290257 u2DelayCellOfst[6]=22 cells (6 PI)
8913 23:42:15.293779 u2DelayCellOfst[7]=7 cells (2 PI)
8914 23:42:15.296568 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8915 23:42:15.300444 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8916 23:42:15.303652 == TX Byte 1 ==
8917 23:42:15.306869 u2DelayCellOfst[8]=0 cells (0 PI)
8918 23:42:15.306994 u2DelayCellOfst[9]=7 cells (2 PI)
8919 23:42:15.309854 u2DelayCellOfst[10]=11 cells (3 PI)
8920 23:42:15.313366 u2DelayCellOfst[11]=3 cells (1 PI)
8921 23:42:15.316879 u2DelayCellOfst[12]=15 cells (4 PI)
8922 23:42:15.320018 u2DelayCellOfst[13]=18 cells (5 PI)
8923 23:42:15.323334 u2DelayCellOfst[14]=18 cells (5 PI)
8924 23:42:15.326525 u2DelayCellOfst[15]=18 cells (5 PI)
8925 23:42:15.329855 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8926 23:42:15.336659 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8927 23:42:15.336785 DramC Write-DBI on
8928 23:42:15.336901 ==
8929 23:42:15.339683 Dram Type= 6, Freq= 0, CH_1, rank 1
8930 23:42:15.346245 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8931 23:42:15.346376 ==
8932 23:42:15.346492
8933 23:42:15.346604
8934 23:42:15.346720 TX Vref Scan disable
8935 23:42:15.350143 == TX Byte 0 ==
8936 23:42:15.353498 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8937 23:42:15.356798 == TX Byte 1 ==
8938 23:42:15.359825 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8939 23:42:15.363275 DramC Write-DBI off
8940 23:42:15.363398
8941 23:42:15.363508 [DATLAT]
8942 23:42:15.363627 Freq=1600, CH1 RK1
8943 23:42:15.363735
8944 23:42:15.366626 DATLAT Default: 0xf
8945 23:42:15.366750 0, 0xFFFF, sum = 0
8946 23:42:15.369806 1, 0xFFFF, sum = 0
8947 23:42:15.373686 2, 0xFFFF, sum = 0
8948 23:42:15.373825 3, 0xFFFF, sum = 0
8949 23:42:15.376763 4, 0xFFFF, sum = 0
8950 23:42:15.376888 5, 0xFFFF, sum = 0
8951 23:42:15.380208 6, 0xFFFF, sum = 0
8952 23:42:15.380334 7, 0xFFFF, sum = 0
8953 23:42:15.383604 8, 0xFFFF, sum = 0
8954 23:42:15.383730 9, 0xFFFF, sum = 0
8955 23:42:15.386923 10, 0xFFFF, sum = 0
8956 23:42:15.387047 11, 0xFFFF, sum = 0
8957 23:42:15.390306 12, 0xFFFF, sum = 0
8958 23:42:15.390438 13, 0x8FFF, sum = 0
8959 23:42:15.393182 14, 0x0, sum = 1
8960 23:42:15.393307 15, 0x0, sum = 2
8961 23:42:15.396935 16, 0x0, sum = 3
8962 23:42:15.397065 17, 0x0, sum = 4
8963 23:42:15.399895 best_step = 15
8964 23:42:15.400020
8965 23:42:15.400131 ==
8966 23:42:15.403358 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 23:42:15.406594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 23:42:15.406720 ==
8969 23:42:15.409530 RX Vref Scan: 0
8970 23:42:15.409653
8971 23:42:15.409770 RX Vref 0 -> 0, step: 1
8972 23:42:15.409885
8973 23:42:15.413156 RX Delay 3 -> 252, step: 4
8974 23:42:15.416401 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
8975 23:42:15.423080 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8976 23:42:15.426094 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
8977 23:42:15.429743 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8978 23:42:15.433037 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8979 23:42:15.436279 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8980 23:42:15.442943 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8981 23:42:15.446243 iDelay=195, Bit 7, Center 122 (67 ~ 178) 112
8982 23:42:15.449471 iDelay=195, Bit 8, Center 110 (51 ~ 170) 120
8983 23:42:15.452921 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8984 23:42:15.456724 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8985 23:42:15.462962 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
8986 23:42:15.466559 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8987 23:42:15.469855 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
8988 23:42:15.472541 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8989 23:42:15.479399 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
8990 23:42:15.479498 ==
8991 23:42:15.483182 Dram Type= 6, Freq= 0, CH_1, rank 1
8992 23:42:15.486020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8993 23:42:15.486102 ==
8994 23:42:15.486167 DQS Delay:
8995 23:42:15.489460 DQS0 = 0, DQS1 = 0
8996 23:42:15.489548 DQM Delay:
8997 23:42:15.492959 DQM0 = 127, DQM1 = 124
8998 23:42:15.493040 DQ Delay:
8999 23:42:15.496216 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =126
9000 23:42:15.499538 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =122
9001 23:42:15.502781 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =118
9002 23:42:15.505925 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =134
9003 23:42:15.506046
9004 23:42:15.506153
9005 23:42:15.506267
9006 23:42:15.509209 [DramC_TX_OE_Calibration] TA2
9007 23:42:15.512508 Original DQ_B0 (3 6) =30, OEN = 27
9008 23:42:15.515708 Original DQ_B1 (3 6) =30, OEN = 27
9009 23:42:15.519308 24, 0x0, End_B0=24 End_B1=24
9010 23:42:15.522842 25, 0x0, End_B0=25 End_B1=25
9011 23:42:15.525899 26, 0x0, End_B0=26 End_B1=26
9012 23:42:15.526023 27, 0x0, End_B0=27 End_B1=27
9013 23:42:15.529142 28, 0x0, End_B0=28 End_B1=28
9014 23:42:15.532711 29, 0x0, End_B0=29 End_B1=29
9015 23:42:15.535559 30, 0x0, End_B0=30 End_B1=30
9016 23:42:15.539203 31, 0x4545, End_B0=30 End_B1=30
9017 23:42:15.539334 Byte0 end_step=30 best_step=27
9018 23:42:15.542600 Byte1 end_step=30 best_step=27
9019 23:42:15.545980 Byte0 TX OE(2T, 0.5T) = (3, 3)
9020 23:42:15.549091 Byte1 TX OE(2T, 0.5T) = (3, 3)
9021 23:42:15.549216
9022 23:42:15.549332
9023 23:42:15.555700 [DQSOSCAuto] RK1, (LSB)MR18= 0x1420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
9024 23:42:15.558675 CH1 RK1: MR19=303, MR18=1420
9025 23:42:15.565422 CH1_RK1: MR19=0x303, MR18=0x1420, DQSOSC=393, MR23=63, INC=23, DEC=15
9026 23:42:15.568691 [RxdqsGatingPostProcess] freq 1600
9027 23:42:15.575566 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9028 23:42:15.579070 best DQS0 dly(2T, 0.5T) = (1, 1)
9029 23:42:15.579191 best DQS1 dly(2T, 0.5T) = (1, 1)
9030 23:42:15.582432 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9031 23:42:15.585664 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9032 23:42:15.589025 best DQS0 dly(2T, 0.5T) = (1, 1)
9033 23:42:15.592056 best DQS1 dly(2T, 0.5T) = (1, 1)
9034 23:42:15.595257 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9035 23:42:15.599083 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9036 23:42:15.601934 Pre-setting of DQS Precalculation
9037 23:42:15.605088 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9038 23:42:15.614943 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9039 23:42:15.621708 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9040 23:42:15.621832
9041 23:42:15.621947
9042 23:42:15.625309 [Calibration Summary] 3200 Mbps
9043 23:42:15.625431 CH 0, Rank 0
9044 23:42:15.628500 SW Impedance : PASS
9045 23:42:15.628656 DUTY Scan : NO K
9046 23:42:15.631730 ZQ Calibration : PASS
9047 23:42:15.635032 Jitter Meter : NO K
9048 23:42:15.635154 CBT Training : PASS
9049 23:42:15.638674 Write leveling : PASS
9050 23:42:15.641532 RX DQS gating : PASS
9051 23:42:15.641654 RX DQ/DQS(RDDQC) : PASS
9052 23:42:15.644791 TX DQ/DQS : PASS
9053 23:42:15.648175 RX DATLAT : PASS
9054 23:42:15.648297 RX DQ/DQS(Engine): PASS
9055 23:42:15.651559 TX OE : PASS
9056 23:42:15.651684 All Pass.
9057 23:42:15.651794
9058 23:42:15.654886 CH 0, Rank 1
9059 23:42:15.655006 SW Impedance : PASS
9060 23:42:15.658542 DUTY Scan : NO K
9061 23:42:15.661629 ZQ Calibration : PASS
9062 23:42:15.661751 Jitter Meter : NO K
9063 23:42:15.664779 CBT Training : PASS
9064 23:42:15.668130 Write leveling : PASS
9065 23:42:15.668251 RX DQS gating : PASS
9066 23:42:15.671528 RX DQ/DQS(RDDQC) : PASS
9067 23:42:15.674661 TX DQ/DQS : PASS
9068 23:42:15.674782 RX DATLAT : PASS
9069 23:42:15.677844 RX DQ/DQS(Engine): PASS
9070 23:42:15.681705 TX OE : PASS
9071 23:42:15.681827 All Pass.
9072 23:42:15.681938
9073 23:42:15.682049 CH 1, Rank 0
9074 23:42:15.684532 SW Impedance : PASS
9075 23:42:15.687948 DUTY Scan : NO K
9076 23:42:15.688066 ZQ Calibration : PASS
9077 23:42:15.691192 Jitter Meter : NO K
9078 23:42:15.691312 CBT Training : PASS
9079 23:42:15.694515 Write leveling : PASS
9080 23:42:15.697892 RX DQS gating : PASS
9081 23:42:15.698016 RX DQ/DQS(RDDQC) : PASS
9082 23:42:15.701274 TX DQ/DQS : PASS
9083 23:42:15.704451 RX DATLAT : PASS
9084 23:42:15.704597 RX DQ/DQS(Engine): PASS
9085 23:42:15.707803 TX OE : PASS
9086 23:42:15.707926 All Pass.
9087 23:42:15.708035
9088 23:42:15.711133 CH 1, Rank 1
9089 23:42:15.711254 SW Impedance : PASS
9090 23:42:15.714242 DUTY Scan : NO K
9091 23:42:15.717661 ZQ Calibration : PASS
9092 23:42:15.717781 Jitter Meter : NO K
9093 23:42:15.720989 CBT Training : PASS
9094 23:42:15.724369 Write leveling : PASS
9095 23:42:15.724449 RX DQS gating : PASS
9096 23:42:15.728035 RX DQ/DQS(RDDQC) : PASS
9097 23:42:15.730951 TX DQ/DQS : PASS
9098 23:42:15.731032 RX DATLAT : PASS
9099 23:42:15.734405 RX DQ/DQS(Engine): PASS
9100 23:42:15.737590 TX OE : PASS
9101 23:42:15.737673 All Pass.
9102 23:42:15.737738
9103 23:42:15.737798 DramC Write-DBI on
9104 23:42:15.741067 PER_BANK_REFRESH: Hybrid Mode
9105 23:42:15.744059 TX_TRACKING: ON
9106 23:42:15.750972 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9107 23:42:15.760695 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9108 23:42:15.767613 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9109 23:42:15.770729 [FAST_K] Save calibration result to emmc
9110 23:42:15.773961 sync common calibartion params.
9111 23:42:15.777327 sync cbt_mode0:1, 1:1
9112 23:42:15.777407 dram_init: ddr_geometry: 2
9113 23:42:15.780691 dram_init: ddr_geometry: 2
9114 23:42:15.783823 dram_init: ddr_geometry: 2
9115 23:42:15.783941 0:dram_rank_size:100000000
9116 23:42:15.787199 1:dram_rank_size:100000000
9117 23:42:15.793909 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9118 23:42:15.797225 DFS_SHUFFLE_HW_MODE: ON
9119 23:42:15.800702 dramc_set_vcore_voltage set vcore to 725000
9120 23:42:15.800815 Read voltage for 1600, 0
9121 23:42:15.804205 Vio18 = 0
9122 23:42:15.804284 Vcore = 725000
9123 23:42:15.804354 Vdram = 0
9124 23:42:15.807308 Vddq = 0
9125 23:42:15.807404 Vmddr = 0
9126 23:42:15.810527 switch to 3200 Mbps bootup
9127 23:42:15.810646 [DramcRunTimeConfig]
9128 23:42:15.810718 PHYPLL
9129 23:42:15.813731 DPM_CONTROL_AFTERK: ON
9130 23:42:15.816953 PER_BANK_REFRESH: ON
9131 23:42:15.817033 REFRESH_OVERHEAD_REDUCTION: ON
9132 23:42:15.820216 CMD_PICG_NEW_MODE: OFF
9133 23:42:15.823531 XRTWTW_NEW_MODE: ON
9134 23:42:15.823609 XRTRTR_NEW_MODE: ON
9135 23:42:15.826995 TX_TRACKING: ON
9136 23:42:15.827070 RDSEL_TRACKING: OFF
9137 23:42:15.830362 DQS Precalculation for DVFS: ON
9138 23:42:15.830535 RX_TRACKING: OFF
9139 23:42:15.833599 HW_GATING DBG: ON
9140 23:42:15.836770 ZQCS_ENABLE_LP4: ON
9141 23:42:15.836892 RX_PICG_NEW_MODE: ON
9142 23:42:15.840517 TX_PICG_NEW_MODE: ON
9143 23:42:15.840660 ENABLE_RX_DCM_DPHY: ON
9144 23:42:15.843577 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9145 23:42:15.846694 DUMMY_READ_FOR_TRACKING: OFF
9146 23:42:15.850437 !!! SPM_CONTROL_AFTERK: OFF
9147 23:42:15.853289 !!! SPM could not control APHY
9148 23:42:15.853443 IMPEDANCE_TRACKING: ON
9149 23:42:15.856891 TEMP_SENSOR: ON
9150 23:42:15.857012 HW_SAVE_FOR_SR: OFF
9151 23:42:15.860266 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9152 23:42:15.863413 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9153 23:42:15.866927 Read ODT Tracking: ON
9154 23:42:15.867050 Refresh Rate DeBounce: ON
9155 23:42:15.870434 DFS_NO_QUEUE_FLUSH: ON
9156 23:42:15.873496 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9157 23:42:15.876635 ENABLE_DFS_RUNTIME_MRW: OFF
9158 23:42:15.879874 DDR_RESERVE_NEW_MODE: ON
9159 23:42:15.880000 MR_CBT_SWITCH_FREQ: ON
9160 23:42:15.883156 =========================
9161 23:42:15.901801 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9162 23:42:15.904985 dram_init: ddr_geometry: 2
9163 23:42:15.923407 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9164 23:42:15.926630 dram_init: dram init end (result: 0)
9165 23:42:15.933329 DRAM-K: Full calibration passed in 24574 msecs
9166 23:42:15.936710 MRC: failed to locate region type 0.
9167 23:42:15.936793 DRAM rank0 size:0x100000000,
9168 23:42:15.939810 DRAM rank1 size=0x100000000
9169 23:42:15.949684 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9170 23:42:15.956106 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9171 23:42:15.962891 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9172 23:42:15.969630 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9173 23:42:15.972893 DRAM rank0 size:0x100000000,
9174 23:42:15.976204 DRAM rank1 size=0x100000000
9175 23:42:15.976287 CBMEM:
9176 23:42:15.979467 IMD: root @ 0xfffff000 254 entries.
9177 23:42:15.982789 IMD: root @ 0xffffec00 62 entries.
9178 23:42:15.985949 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9179 23:42:15.989345 WARNING: RO_VPD is uninitialized or empty.
9180 23:42:15.995963 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9181 23:42:16.003694 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9182 23:42:16.016121 read SPI 0x42894 0xe01e: 6228 us, 9212 KB/s, 73.696 Mbps
9183 23:42:16.027428 BS: romstage times (exec / console): total (unknown) / 24038 ms
9184 23:42:16.027555
9185 23:42:16.027666
9186 23:42:16.037431 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9187 23:42:16.040837 ARM64: Exception handlers installed.
9188 23:42:16.043896 ARM64: Testing exception
9189 23:42:16.047215 ARM64: Done test exception
9190 23:42:16.047351 Enumerating buses...
9191 23:42:16.050537 Show all devs... Before device enumeration.
9192 23:42:16.053912 Root Device: enabled 1
9193 23:42:16.057226 CPU_CLUSTER: 0: enabled 1
9194 23:42:16.057347 CPU: 00: enabled 1
9195 23:42:16.060570 Compare with tree...
9196 23:42:16.060686 Root Device: enabled 1
9197 23:42:16.063803 CPU_CLUSTER: 0: enabled 1
9198 23:42:16.067116 CPU: 00: enabled 1
9199 23:42:16.067234 Root Device scanning...
9200 23:42:16.070770 scan_static_bus for Root Device
9201 23:42:16.073705 CPU_CLUSTER: 0 enabled
9202 23:42:16.076683 scan_static_bus for Root Device done
9203 23:42:16.080197 scan_bus: bus Root Device finished in 8 msecs
9204 23:42:16.080324 done
9205 23:42:16.087023 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9206 23:42:16.090064 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9207 23:42:16.096950 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9208 23:42:16.100367 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9209 23:42:16.103445 Allocating resources...
9210 23:42:16.106611 Reading resources...
9211 23:42:16.110239 Root Device read_resources bus 0 link: 0
9212 23:42:16.113712 DRAM rank0 size:0x100000000,
9213 23:42:16.113802 DRAM rank1 size=0x100000000
9214 23:42:16.116743 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9215 23:42:16.120047 CPU: 00 missing read_resources
9216 23:42:16.126584 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9217 23:42:16.129904 Root Device read_resources bus 0 link: 0 done
9218 23:42:16.129976 Done reading resources.
9219 23:42:16.136480 Show resources in subtree (Root Device)...After reading.
9220 23:42:16.139728 Root Device child on link 0 CPU_CLUSTER: 0
9221 23:42:16.143408 CPU_CLUSTER: 0 child on link 0 CPU: 00
9222 23:42:16.153150 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9223 23:42:16.153229 CPU: 00
9224 23:42:16.156582 Root Device assign_resources, bus 0 link: 0
9225 23:42:16.159983 CPU_CLUSTER: 0 missing set_resources
9226 23:42:16.166677 Root Device assign_resources, bus 0 link: 0 done
9227 23:42:16.166756 Done setting resources.
9228 23:42:16.173240 Show resources in subtree (Root Device)...After assigning values.
9229 23:42:16.176573 Root Device child on link 0 CPU_CLUSTER: 0
9230 23:42:16.179899 CPU_CLUSTER: 0 child on link 0 CPU: 00
9231 23:42:16.189618 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9232 23:42:16.189705 CPU: 00
9233 23:42:16.192926 Done allocating resources.
9234 23:42:16.199324 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9235 23:42:16.199451 Enabling resources...
9236 23:42:16.199567 done.
9237 23:42:16.206012 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9238 23:42:16.206118 Initializing devices...
9239 23:42:16.209234 Root Device init
9240 23:42:16.212898 init hardware done!
9241 23:42:16.212983 0x00000018: ctrlr->caps
9242 23:42:16.216059 52.000 MHz: ctrlr->f_max
9243 23:42:16.216146 0.400 MHz: ctrlr->f_min
9244 23:42:16.219099 0x40ff8080: ctrlr->voltages
9245 23:42:16.222716 sclk: 390625
9246 23:42:16.222800 Bus Width = 1
9247 23:42:16.222885 sclk: 390625
9248 23:42:16.225934 Bus Width = 1
9249 23:42:16.226018 Early init status = 3
9250 23:42:16.232479 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9251 23:42:16.235645 in-header: 03 fc 00 00 01 00 00 00
9252 23:42:16.239118 in-data: 00
9253 23:42:16.242435 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9254 23:42:16.245879 in-header: 03 fd 00 00 00 00 00 00
9255 23:42:16.249732 in-data:
9256 23:42:16.252860 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9257 23:42:16.256157 in-header: 03 fc 00 00 01 00 00 00
9258 23:42:16.259560 in-data: 00
9259 23:42:16.262827 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9260 23:42:16.267285 in-header: 03 fd 00 00 00 00 00 00
9261 23:42:16.270623 in-data:
9262 23:42:16.274026 [SSUSB] Setting up USB HOST controller...
9263 23:42:16.277169 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9264 23:42:16.280411 [SSUSB] phy power-on done.
9265 23:42:16.283714 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9266 23:42:16.290291 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9267 23:42:16.293782 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9268 23:42:16.300360 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9269 23:42:16.306735 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9270 23:42:16.313400 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9271 23:42:16.320295 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9272 23:42:16.326537 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9273 23:42:16.330055 SPM: binary array size = 0x9dc
9274 23:42:16.332988 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9275 23:42:16.339690 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9276 23:42:16.346448 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9277 23:42:16.353180 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9278 23:42:16.356307 configure_display: Starting display init
9279 23:42:16.390579 anx7625_power_on_init: Init interface.
9280 23:42:16.393986 anx7625_disable_pd_protocol: Disabled PD feature.
9281 23:42:16.397068 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9282 23:42:16.424863 anx7625_start_dp_work: Secure OCM version=00
9283 23:42:16.428183 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9284 23:42:16.443334 sp_tx_get_edid_block: EDID Block = 1
9285 23:42:16.545542 Extracted contents:
9286 23:42:16.548708 header: 00 ff ff ff ff ff ff 00
9287 23:42:16.552238 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9288 23:42:16.555425 version: 01 04
9289 23:42:16.559168 basic params: 95 1f 11 78 0a
9290 23:42:16.562559 chroma info: 76 90 94 55 54 90 27 21 50 54
9291 23:42:16.565640 established: 00 00 00
9292 23:42:16.572198 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9293 23:42:16.575594 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9294 23:42:16.581762 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9295 23:42:16.588443 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9296 23:42:16.595009 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9297 23:42:16.598352 extensions: 00
9298 23:42:16.598433 checksum: fb
9299 23:42:16.598498
9300 23:42:16.601755 Manufacturer: IVO Model 57d Serial Number 0
9301 23:42:16.605085 Made week 0 of 2020
9302 23:42:16.608403 EDID version: 1.4
9303 23:42:16.608484 Digital display
9304 23:42:16.611716 6 bits per primary color channel
9305 23:42:16.611799 DisplayPort interface
9306 23:42:16.614922 Maximum image size: 31 cm x 17 cm
9307 23:42:16.618233 Gamma: 220%
9308 23:42:16.618313 Check DPMS levels
9309 23:42:16.621725 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9310 23:42:16.628378 First detailed timing is preferred timing
9311 23:42:16.628462 Established timings supported:
9312 23:42:16.631805 Standard timings supported:
9313 23:42:16.634713 Detailed timings
9314 23:42:16.638254 Hex of detail: 383680a07038204018303c0035ae10000019
9315 23:42:16.645097 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9316 23:42:16.648195 0780 0798 07c8 0820 hborder 0
9317 23:42:16.651517 0438 043b 0447 0458 vborder 0
9318 23:42:16.654594 -hsync -vsync
9319 23:42:16.654676 Did detailed timing
9320 23:42:16.661740 Hex of detail: 000000000000000000000000000000000000
9321 23:42:16.664902 Manufacturer-specified data, tag 0
9322 23:42:16.668276 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9323 23:42:16.671373 ASCII string: InfoVision
9324 23:42:16.674830 Hex of detail: 000000fe00523134304e574635205248200a
9325 23:42:16.678056 ASCII string: R140NWF5 RH
9326 23:42:16.678238 Checksum
9327 23:42:16.681295 Checksum: 0xfb (valid)
9328 23:42:16.684191 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9329 23:42:16.687614 DSI data_rate: 832800000 bps
9330 23:42:16.694428 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9331 23:42:16.697691 anx7625_parse_edid: pixelclock(138800).
9332 23:42:16.701085 hactive(1920), hsync(48), hfp(24), hbp(88)
9333 23:42:16.704432 vactive(1080), vsync(12), vfp(3), vbp(17)
9334 23:42:16.707696 anx7625_dsi_config: config dsi.
9335 23:42:16.714183 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9336 23:42:16.727812 anx7625_dsi_config: success to config DSI
9337 23:42:16.731157 anx7625_dp_start: MIPI phy setup OK.
9338 23:42:16.734400 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9339 23:42:16.737349 mtk_ddp_mode_set invalid vrefresh 60
9340 23:42:16.740791 main_disp_path_setup
9341 23:42:16.740871 ovl_layer_smi_id_en
9342 23:42:16.744301 ovl_layer_smi_id_en
9343 23:42:16.744383 ccorr_config
9344 23:42:16.744450 aal_config
9345 23:42:16.747445 gamma_config
9346 23:42:16.747527 postmask_config
9347 23:42:16.751082 dither_config
9348 23:42:16.754455 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9349 23:42:16.760714 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9350 23:42:16.764129 Root Device init finished in 551 msecs
9351 23:42:16.767350 CPU_CLUSTER: 0 init
9352 23:42:16.774237 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9353 23:42:16.777472 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9354 23:42:16.780537 APU_MBOX 0x190000b0 = 0x10001
9355 23:42:16.784063 APU_MBOX 0x190001b0 = 0x10001
9356 23:42:16.787205 APU_MBOX 0x190005b0 = 0x10001
9357 23:42:16.790591 APU_MBOX 0x190006b0 = 0x10001
9358 23:42:16.797257 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9359 23:42:16.806516 read SPI 0x539f4 0xe237: 6251 us, 9264 KB/s, 74.112 Mbps
9360 23:42:16.819011 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9361 23:42:16.825548 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9362 23:42:16.837317 read SPI 0x61c74 0xe8ef: 6413 us, 9298 KB/s, 74.384 Mbps
9363 23:42:16.846245 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9364 23:42:16.849763 CPU_CLUSTER: 0 init finished in 81 msecs
9365 23:42:16.853206 Devices initialized
9366 23:42:16.856291 Show all devs... After init.
9367 23:42:16.856368 Root Device: enabled 1
9368 23:42:16.859432 CPU_CLUSTER: 0: enabled 1
9369 23:42:16.862834 CPU: 00: enabled 1
9370 23:42:16.866343 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9371 23:42:16.869916 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9372 23:42:16.873300 ELOG: NV offset 0x57f000 size 0x1000
9373 23:42:16.879708 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9374 23:42:16.886114 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9375 23:42:16.889586 ELOG: Event(17) added with size 13 at 2024-06-04 23:42:18 UTC
9376 23:42:16.892826 out: cmd=0x121: 03 db 21 01 00 00 00 00
9377 23:42:16.897823 in-header: 03 61 00 00 2c 00 00 00
9378 23:42:16.911084 in-data: fe 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9379 23:42:16.917514 ELOG: Event(A1) added with size 10 at 2024-06-04 23:42:18 UTC
9380 23:42:16.924159 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9381 23:42:16.931308 ELOG: Event(A0) added with size 9 at 2024-06-04 23:42:18 UTC
9382 23:42:16.934570 elog_add_boot_reason: Logged dev mode boot
9383 23:42:16.937952 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9384 23:42:16.940545 Finalize devices...
9385 23:42:16.940629 Devices finalized
9386 23:42:16.947384 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9387 23:42:16.950607 Writing coreboot table at 0xffe64000
9388 23:42:16.954260 0. 000000000010a000-0000000000113fff: RAMSTAGE
9389 23:42:16.957738 1. 0000000040000000-00000000400fffff: RAM
9390 23:42:16.964095 2. 0000000040100000-000000004032afff: RAMSTAGE
9391 23:42:16.967768 3. 000000004032b000-00000000545fffff: RAM
9392 23:42:16.970701 4. 0000000054600000-000000005465ffff: BL31
9393 23:42:16.974309 5. 0000000054660000-00000000ffe63fff: RAM
9394 23:42:16.980682 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9395 23:42:16.984146 7. 0000000100000000-000000023fffffff: RAM
9396 23:42:16.984220 Passing 5 GPIOs to payload:
9397 23:42:16.990336 NAME | PORT | POLARITY | VALUE
9398 23:42:16.993954 EC in RW | 0x000000aa | low | undefined
9399 23:42:17.000635 EC interrupt | 0x00000005 | low | undefined
9400 23:42:17.003683 TPM interrupt | 0x000000ab | high | undefined
9401 23:42:17.006867 SD card detect | 0x00000011 | high | undefined
9402 23:42:17.013584 speaker enable | 0x00000093 | high | undefined
9403 23:42:17.016839 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9404 23:42:17.020520 in-header: 03 f9 00 00 02 00 00 00
9405 23:42:17.020610 in-data: 02 00
9406 23:42:17.023903 ADC[4]: Raw value=892971 ID=7
9407 23:42:17.026989 ADC[3]: Raw value=213440 ID=1
9408 23:42:17.030211 RAM Code: 0x71
9409 23:42:17.030289 ADC[6]: Raw value=74722 ID=0
9410 23:42:17.033579 ADC[5]: Raw value=213070 ID=1
9411 23:42:17.036976 SKU Code: 0x1
9412 23:42:17.040446 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7b2b
9413 23:42:17.043726 coreboot table: 964 bytes.
9414 23:42:17.047087 IMD ROOT 0. 0xfffff000 0x00001000
9415 23:42:17.050350 IMD SMALL 1. 0xffffe000 0x00001000
9416 23:42:17.053671 RO MCACHE 2. 0xffffc000 0x00001104
9417 23:42:17.056499 CONSOLE 3. 0xfff7c000 0x00080000
9418 23:42:17.060271 FMAP 4. 0xfff7b000 0x00000452
9419 23:42:17.063465 TIME STAMP 5. 0xfff7a000 0x00000910
9420 23:42:17.066510 VBOOT WORK 6. 0xfff66000 0x00014000
9421 23:42:17.069867 RAMOOPS 7. 0xffe66000 0x00100000
9422 23:42:17.073270 COREBOOT 8. 0xffe64000 0x00002000
9423 23:42:17.073348 IMD small region:
9424 23:42:17.076711 IMD ROOT 0. 0xffffec00 0x00000400
9425 23:42:17.080067 VPD 1. 0xffffeb80 0x0000006c
9426 23:42:17.086274 MMC STATUS 2. 0xffffeb60 0x00000004
9427 23:42:17.089750 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9428 23:42:17.092922 Probing TPM: done!
9429 23:42:17.096769 Connected to device vid:did:rid of 1ae0:0028:00
9430 23:42:17.106437 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9431 23:42:17.110114 Initialized TPM device CR50 revision 0
9432 23:42:17.113210 Checking cr50 for pending updates
9433 23:42:17.117167 Reading cr50 TPM mode
9434 23:42:17.125650 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9435 23:42:17.132306 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9436 23:42:17.172599 read SPI 0x3990ec 0x4f1b0: 34860 us, 9294 KB/s, 74.352 Mbps
9437 23:42:17.175734 Checking segment from ROM address 0x40100000
9438 23:42:17.179282 Checking segment from ROM address 0x4010001c
9439 23:42:17.185489 Loading segment from ROM address 0x40100000
9440 23:42:17.185572 code (compression=0)
9441 23:42:17.195560 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9442 23:42:17.202493 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9443 23:42:17.202577 it's not compressed!
9444 23:42:17.209066 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9445 23:42:17.212713 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9446 23:42:17.233009 Loading segment from ROM address 0x4010001c
9447 23:42:17.233144 Entry Point 0x80000000
9448 23:42:17.236103 Loaded segments
9449 23:42:17.239884 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9450 23:42:17.246110 Jumping to boot code at 0x80000000(0xffe64000)
9451 23:42:17.252644 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9452 23:42:17.259297 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9453 23:42:17.267171 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9454 23:42:17.270712 Checking segment from ROM address 0x40100000
9455 23:42:17.274375 Checking segment from ROM address 0x4010001c
9456 23:42:17.280511 Loading segment from ROM address 0x40100000
9457 23:42:17.280659 code (compression=1)
9458 23:42:17.287512 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9459 23:42:17.297267 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9460 23:42:17.297350 using LZMA
9461 23:42:17.305573 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9462 23:42:17.312270 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9463 23:42:17.315582 Loading segment from ROM address 0x4010001c
9464 23:42:17.315730 Entry Point 0x54601000
9465 23:42:17.319076 Loaded segments
9466 23:42:17.322544 NOTICE: MT8192 bl31_setup
9467 23:42:17.329392 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9468 23:42:17.332566 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9469 23:42:17.336155 WARNING: region 0:
9470 23:42:17.339548 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9471 23:42:17.339687 WARNING: region 1:
9472 23:42:17.345751 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9473 23:42:17.349041 WARNING: region 2:
9474 23:42:17.352345 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9475 23:42:17.355691 WARNING: region 3:
9476 23:42:17.359140 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9477 23:42:17.362514 WARNING: region 4:
9478 23:42:17.368858 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9479 23:42:17.368942 WARNING: region 5:
9480 23:42:17.372250 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 23:42:17.375910 WARNING: region 6:
9482 23:42:17.379154 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9483 23:42:17.382523 WARNING: region 7:
9484 23:42:17.385763 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9485 23:42:17.392636 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9486 23:42:17.395577 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9487 23:42:17.398761 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9488 23:42:17.405569 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9489 23:42:17.409106 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9490 23:42:17.412058 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9491 23:42:17.418806 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9492 23:42:17.422264 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9493 23:42:17.428679 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9494 23:42:17.431860 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9495 23:42:17.435198 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9496 23:42:17.442012 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9497 23:42:17.445183 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9498 23:42:17.451631 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9499 23:42:17.455236 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9500 23:42:17.458742 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9501 23:42:17.464925 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9502 23:42:17.468078 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9503 23:42:17.475425 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9504 23:42:17.478094 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9505 23:42:17.481374 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9506 23:42:17.488009 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9507 23:42:17.491508 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9508 23:42:17.494958 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9509 23:42:17.501527 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9510 23:42:17.504915 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9511 23:42:17.511828 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9512 23:42:17.514547 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9513 23:42:17.521396 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9514 23:42:17.524576 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9515 23:42:17.528150 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9516 23:42:17.534793 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9517 23:42:17.537928 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9518 23:42:17.541123 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9519 23:42:17.545112 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9520 23:42:17.551234 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9521 23:42:17.554691 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9522 23:42:17.557920 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9523 23:42:17.561380 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9524 23:42:17.568056 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9525 23:42:17.571170 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9526 23:42:17.574738 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9527 23:42:17.578087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9528 23:42:17.584768 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9529 23:42:17.588024 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9530 23:42:17.591425 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9531 23:42:17.594667 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9532 23:42:17.601522 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9533 23:42:17.604649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9534 23:42:17.611210 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9535 23:42:17.614541 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9536 23:42:17.617728 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9537 23:42:17.624510 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9538 23:42:17.627691 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9539 23:42:17.634561 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9540 23:42:17.637792 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9541 23:42:17.644439 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9542 23:42:17.647884 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9543 23:42:17.651187 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9544 23:42:17.657759 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9545 23:42:17.661225 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9546 23:42:17.667805 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9547 23:42:17.671145 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9548 23:42:17.678267 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9549 23:42:17.681589 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9550 23:42:17.684752 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9551 23:42:17.691711 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9552 23:42:17.694661 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9553 23:42:17.701326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9554 23:42:17.704650 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9555 23:42:17.711365 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9556 23:42:17.714611 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9557 23:42:17.717798 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9558 23:42:17.724635 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9559 23:42:17.727619 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9560 23:42:17.734631 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9561 23:42:17.737629 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9562 23:42:17.744365 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9563 23:42:17.747600 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9564 23:42:17.754710 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9565 23:42:17.757982 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9566 23:42:17.761294 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9567 23:42:17.768042 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9568 23:42:17.771539 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9569 23:42:17.777806 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9570 23:42:17.781023 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9571 23:42:17.784777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9572 23:42:17.791230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9573 23:42:17.794661 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9574 23:42:17.801289 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9575 23:42:17.804501 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9576 23:42:17.811233 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9577 23:42:17.814505 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9578 23:42:17.821146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9579 23:42:17.824678 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9580 23:42:17.827718 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9581 23:42:17.834767 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9582 23:42:17.838047 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9583 23:42:17.841345 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9584 23:42:17.844803 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9585 23:42:17.851449 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9586 23:42:17.854721 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9587 23:42:17.858005 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9588 23:42:17.864515 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9589 23:42:17.868030 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9590 23:42:17.874557 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9591 23:42:17.878013 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9592 23:42:17.881061 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9593 23:42:17.888172 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9594 23:42:17.891374 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9595 23:42:17.898055 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9596 23:42:17.901083 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9597 23:42:17.904336 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9598 23:42:17.910968 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9599 23:42:17.914280 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9600 23:42:17.921088 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9601 23:42:17.924532 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9602 23:42:17.927686 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9603 23:42:17.934500 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9604 23:42:17.937801 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9605 23:42:17.940850 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9606 23:42:17.944441 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9607 23:42:17.947657 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9608 23:42:17.954432 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9609 23:42:17.957999 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9610 23:42:17.964549 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9611 23:42:17.967645 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9612 23:42:17.971090 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9613 23:42:17.977871 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9614 23:42:17.981149 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9615 23:42:17.984450 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9616 23:42:17.991324 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9617 23:42:17.994606 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9618 23:42:18.001256 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9619 23:42:18.004425 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9620 23:42:18.008041 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9621 23:42:18.014562 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9622 23:42:18.017684 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9623 23:42:18.021015 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9624 23:42:18.027671 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9625 23:42:18.031079 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9626 23:42:18.037647 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9627 23:42:18.041410 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9628 23:42:18.044585 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9629 23:42:18.051210 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9630 23:42:18.054533 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9631 23:42:18.061235 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9632 23:42:18.064412 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9633 23:42:18.067661 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9634 23:42:18.074525 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9635 23:42:18.077513 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9636 23:42:18.084290 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9637 23:42:18.087533 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9638 23:42:18.091055 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9639 23:42:18.098010 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9640 23:42:18.101520 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9641 23:42:18.107622 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9642 23:42:18.111347 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9643 23:42:18.114261 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9644 23:42:18.121189 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9645 23:42:18.124531 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9646 23:42:18.127927 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9647 23:42:18.134078 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9648 23:42:18.137463 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9649 23:42:18.144102 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9650 23:42:18.147564 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9651 23:42:18.150754 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9652 23:42:18.157207 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9653 23:42:18.160471 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9654 23:42:18.167426 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9655 23:42:18.170363 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9656 23:42:18.173965 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9657 23:42:18.180383 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9658 23:42:18.183862 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9659 23:42:18.190593 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9660 23:42:18.193546 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9661 23:42:18.196849 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9662 23:42:18.203822 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9663 23:42:18.207232 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9664 23:42:18.210489 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9665 23:42:18.217173 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9666 23:42:18.220448 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9667 23:42:18.227277 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9668 23:42:18.230097 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9669 23:42:18.236640 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9670 23:42:18.240025 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9671 23:42:18.243482 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9672 23:42:18.250084 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9673 23:42:18.253404 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9674 23:42:18.259889 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9675 23:42:18.263519 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9676 23:42:18.266751 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9677 23:42:18.273354 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9678 23:42:18.276947 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9679 23:42:18.283562 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9680 23:42:18.286690 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9681 23:42:18.290103 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9682 23:42:18.296401 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9683 23:42:18.300215 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9684 23:42:18.306603 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9685 23:42:18.309964 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9686 23:42:18.316577 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9687 23:42:18.319943 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9688 23:42:18.323432 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9689 23:42:18.329874 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9690 23:42:18.333204 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9691 23:42:18.339700 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9692 23:42:18.342798 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9693 23:42:18.349521 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9694 23:42:18.353056 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9695 23:42:18.356630 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9696 23:42:18.362882 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9697 23:42:18.365957 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9698 23:42:18.372359 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9699 23:42:18.375769 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9700 23:42:18.379077 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9701 23:42:18.385822 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9702 23:42:18.389393 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9703 23:42:18.396026 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9704 23:42:18.399154 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9705 23:42:18.405620 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9706 23:42:18.409205 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9707 23:42:18.412040 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9708 23:42:18.418667 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9709 23:42:18.422054 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9710 23:42:18.429249 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9711 23:42:18.432395 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9712 23:42:18.439025 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9713 23:42:18.442318 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9714 23:42:18.445395 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9715 23:42:18.448751 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9716 23:42:18.455574 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9717 23:42:18.458969 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9718 23:42:18.461817 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9719 23:42:18.465127 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9720 23:42:18.471923 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9721 23:42:18.475367 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9722 23:42:18.482009 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9723 23:42:18.485204 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9724 23:42:18.488876 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9725 23:42:18.495151 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9726 23:42:18.498540 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9727 23:42:18.501973 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9728 23:42:18.508182 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9729 23:42:18.511764 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9730 23:42:18.518326 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9731 23:42:18.521667 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9732 23:42:18.525026 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9733 23:42:18.531589 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9734 23:42:18.534963 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9735 23:42:18.538277 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9736 23:42:18.545008 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9737 23:42:18.547731 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9738 23:42:18.550955 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9739 23:42:18.557637 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9740 23:42:18.561489 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9741 23:42:18.567919 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9742 23:42:18.570737 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9743 23:42:18.574198 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9744 23:42:18.580944 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9745 23:42:18.584352 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9746 23:42:18.590552 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9747 23:42:18.594509 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9748 23:42:18.597595 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9749 23:42:18.604157 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9750 23:42:18.606951 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9751 23:42:18.610531 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9752 23:42:18.617121 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9753 23:42:18.620105 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9754 23:42:18.624087 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9755 23:42:18.630044 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9756 23:42:18.633538 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9757 23:42:18.636679 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9758 23:42:18.640440 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9759 23:42:18.643801 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9760 23:42:18.650366 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9761 23:42:18.653733 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9762 23:42:18.657075 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9763 23:42:18.660223 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9764 23:42:18.666924 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9765 23:42:18.670232 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9766 23:42:18.673267 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9767 23:42:18.680355 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9768 23:42:18.683675 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9769 23:42:18.689899 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9770 23:42:18.693281 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9771 23:42:18.699938 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9772 23:42:18.703015 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9773 23:42:18.706512 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9774 23:42:18.713168 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9775 23:42:18.716580 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9776 23:42:18.719757 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9777 23:42:18.726544 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9778 23:42:18.729548 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9779 23:42:18.736697 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9780 23:42:18.739929 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9781 23:42:18.746539 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9782 23:42:18.749821 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9783 23:42:18.753106 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9784 23:42:18.759776 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9785 23:42:18.763060 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9786 23:42:18.769827 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9787 23:42:18.772690 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9788 23:42:18.776046 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9789 23:42:18.782973 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9790 23:42:18.786056 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9791 23:42:18.793034 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9792 23:42:18.796283 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9793 23:42:18.799220 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9794 23:42:18.805863 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9795 23:42:18.809093 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9796 23:42:18.815796 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9797 23:42:18.819117 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9798 23:42:18.825819 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9799 23:42:18.828808 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9800 23:42:18.832496 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9801 23:42:18.839129 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9802 23:42:18.842546 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9803 23:42:18.848980 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9804 23:42:18.852327 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9805 23:42:18.859028 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9806 23:42:18.862300 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9807 23:42:18.865622 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9808 23:42:18.872325 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9809 23:42:18.875762 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9810 23:42:18.879073 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9811 23:42:18.885841 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9812 23:42:18.889153 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9813 23:42:18.895421 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9814 23:42:18.899202 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9815 23:42:18.901941 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9816 23:42:18.908806 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9817 23:42:18.912098 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9818 23:42:18.918855 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9819 23:42:18.922005 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9820 23:42:18.928898 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9821 23:42:18.931976 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9822 23:42:18.935137 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9823 23:42:18.942430 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9824 23:42:18.945105 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9825 23:42:18.951909 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9826 23:42:18.955022 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9827 23:42:18.958366 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9828 23:42:18.965128 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9829 23:42:18.968488 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9830 23:42:18.975176 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9831 23:42:18.978396 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9832 23:42:18.981720 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9833 23:42:18.988425 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9834 23:42:18.991768 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9835 23:42:18.998441 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9836 23:42:19.001756 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9837 23:42:19.008705 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9838 23:42:19.011699 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9839 23:42:19.014635 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9840 23:42:19.021428 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9841 23:42:19.024738 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9842 23:42:19.031631 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9843 23:42:19.034900 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9844 23:42:19.041508 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9845 23:42:19.044793 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9846 23:42:19.047950 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9847 23:42:19.054842 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9848 23:42:19.058091 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9849 23:42:19.064669 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9850 23:42:19.068117 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9851 23:42:19.074953 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9852 23:42:19.077879 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9853 23:42:19.084377 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9854 23:42:19.087907 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9855 23:42:19.091265 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9856 23:42:19.098050 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9857 23:42:19.101156 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9858 23:42:19.107887 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9859 23:42:19.111167 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9860 23:42:19.117891 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9861 23:42:19.121190 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9862 23:42:19.124521 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9863 23:42:19.130803 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9864 23:42:19.134458 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9865 23:42:19.141003 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9866 23:42:19.144617 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9867 23:42:19.151016 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9868 23:42:19.154333 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9869 23:42:19.157572 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9870 23:42:19.164420 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9871 23:42:19.167505 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9872 23:42:19.174209 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9873 23:42:19.177170 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9874 23:42:19.183974 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9875 23:42:19.187461 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9876 23:42:19.194062 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9877 23:42:19.197488 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9878 23:42:19.200890 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9879 23:42:19.207038 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9880 23:42:19.210224 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9881 23:42:19.216948 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9882 23:42:19.220426 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9883 23:42:19.227124 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9884 23:42:19.230467 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9885 23:42:19.236772 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9886 23:42:19.240204 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9887 23:42:19.243579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9888 23:42:19.250040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9889 23:42:19.253360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9890 23:42:19.260285 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9891 23:42:19.263608 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9892 23:42:19.269894 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9893 23:42:19.273282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9894 23:42:19.276685 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9895 23:42:19.283029 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9896 23:42:19.286554 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9897 23:42:19.293050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9898 23:42:19.296242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9899 23:42:19.302705 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9900 23:42:19.306474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9901 23:42:19.313171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9902 23:42:19.316432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9903 23:42:19.323006 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9904 23:42:19.326398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9905 23:42:19.333136 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9906 23:42:19.336755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9907 23:42:19.342776 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9908 23:42:19.346197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9909 23:42:19.352951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9910 23:42:19.356125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9911 23:42:19.363137 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9912 23:42:19.366038 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9913 23:42:19.372740 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9914 23:42:19.376021 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9915 23:42:19.382408 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9916 23:42:19.386230 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9917 23:42:19.392293 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9918 23:42:19.395707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9919 23:42:19.402167 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9920 23:42:19.402248 INFO: [APUAPC] vio 0
9921 23:42:19.409039 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9922 23:42:19.412669 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9923 23:42:19.415866 INFO: [APUAPC] D0_APC_0: 0x400510
9924 23:42:19.419267 INFO: [APUAPC] D0_APC_1: 0x0
9925 23:42:19.422616 INFO: [APUAPC] D0_APC_2: 0x1540
9926 23:42:19.425414 INFO: [APUAPC] D0_APC_3: 0x0
9927 23:42:19.428819 INFO: [APUAPC] D1_APC_0: 0xffffffff
9928 23:42:19.432151 INFO: [APUAPC] D1_APC_1: 0xffffffff
9929 23:42:19.435409 INFO: [APUAPC] D1_APC_2: 0x3fffff
9930 23:42:19.438847 INFO: [APUAPC] D1_APC_3: 0x0
9931 23:42:19.442091 INFO: [APUAPC] D2_APC_0: 0xffffffff
9932 23:42:19.445480 INFO: [APUAPC] D2_APC_1: 0xffffffff
9933 23:42:19.449002 INFO: [APUAPC] D2_APC_2: 0x3fffff
9934 23:42:19.452303 INFO: [APUAPC] D2_APC_3: 0x0
9935 23:42:19.455697 INFO: [APUAPC] D3_APC_0: 0xffffffff
9936 23:42:19.458522 INFO: [APUAPC] D3_APC_1: 0xffffffff
9937 23:42:19.461779 INFO: [APUAPC] D3_APC_2: 0x3fffff
9938 23:42:19.465289 INFO: [APUAPC] D3_APC_3: 0x0
9939 23:42:19.468480 INFO: [APUAPC] D4_APC_0: 0xffffffff
9940 23:42:19.471914 INFO: [APUAPC] D4_APC_1: 0xffffffff
9941 23:42:19.475389 INFO: [APUAPC] D4_APC_2: 0x3fffff
9942 23:42:19.478522 INFO: [APUAPC] D4_APC_3: 0x0
9943 23:42:19.482010 INFO: [APUAPC] D5_APC_0: 0xffffffff
9944 23:42:19.485320 INFO: [APUAPC] D5_APC_1: 0xffffffff
9945 23:42:19.488633 INFO: [APUAPC] D5_APC_2: 0x3fffff
9946 23:42:19.488735 INFO: [APUAPC] D5_APC_3: 0x0
9947 23:42:19.492071 INFO: [APUAPC] D6_APC_0: 0xffffffff
9948 23:42:19.498429 INFO: [APUAPC] D6_APC_1: 0xffffffff
9949 23:42:19.498536 INFO: [APUAPC] D6_APC_2: 0x3fffff
9950 23:42:19.502019 INFO: [APUAPC] D6_APC_3: 0x0
9951 23:42:19.505382 INFO: [APUAPC] D7_APC_0: 0xffffffff
9952 23:42:19.508741 INFO: [APUAPC] D7_APC_1: 0xffffffff
9953 23:42:19.512243 INFO: [APUAPC] D7_APC_2: 0x3fffff
9954 23:42:19.515401 INFO: [APUAPC] D7_APC_3: 0x0
9955 23:42:19.518481 INFO: [APUAPC] D8_APC_0: 0xffffffff
9956 23:42:19.522266 INFO: [APUAPC] D8_APC_1: 0xffffffff
9957 23:42:19.525083 INFO: [APUAPC] D8_APC_2: 0x3fffff
9958 23:42:19.528522 INFO: [APUAPC] D8_APC_3: 0x0
9959 23:42:19.531817 INFO: [APUAPC] D9_APC_0: 0xffffffff
9960 23:42:19.535244 INFO: [APUAPC] D9_APC_1: 0xffffffff
9961 23:42:19.538625 INFO: [APUAPC] D9_APC_2: 0x3fffff
9962 23:42:19.541635 INFO: [APUAPC] D9_APC_3: 0x0
9963 23:42:19.545329 INFO: [APUAPC] D10_APC_0: 0xffffffff
9964 23:42:19.548735 INFO: [APUAPC] D10_APC_1: 0xffffffff
9965 23:42:19.552089 INFO: [APUAPC] D10_APC_2: 0x3fffff
9966 23:42:19.555116 INFO: [APUAPC] D10_APC_3: 0x0
9967 23:42:19.558444 INFO: [APUAPC] D11_APC_0: 0xffffffff
9968 23:42:19.561759 INFO: [APUAPC] D11_APC_1: 0xffffffff
9969 23:42:19.565128 INFO: [APUAPC] D11_APC_2: 0x3fffff
9970 23:42:19.568406 INFO: [APUAPC] D11_APC_3: 0x0
9971 23:42:19.571533 INFO: [APUAPC] D12_APC_0: 0xffffffff
9972 23:42:19.575311 INFO: [APUAPC] D12_APC_1: 0xffffffff
9973 23:42:19.578499 INFO: [APUAPC] D12_APC_2: 0x3fffff
9974 23:42:19.581713 INFO: [APUAPC] D12_APC_3: 0x0
9975 23:42:19.585166 INFO: [APUAPC] D13_APC_0: 0xffffffff
9976 23:42:19.588610 INFO: [APUAPC] D13_APC_1: 0xffffffff
9977 23:42:19.591443 INFO: [APUAPC] D13_APC_2: 0x3fffff
9978 23:42:19.594855 INFO: [APUAPC] D13_APC_3: 0x0
9979 23:42:19.598212 INFO: [APUAPC] D14_APC_0: 0xffffffff
9980 23:42:19.601813 INFO: [APUAPC] D14_APC_1: 0xffffffff
9981 23:42:19.604828 INFO: [APUAPC] D14_APC_2: 0x3fffff
9982 23:42:19.608459 INFO: [APUAPC] D14_APC_3: 0x0
9983 23:42:19.611591 INFO: [APUAPC] D15_APC_0: 0xffffffff
9984 23:42:19.614539 INFO: [APUAPC] D15_APC_1: 0xffffffff
9985 23:42:19.618301 INFO: [APUAPC] D15_APC_2: 0x3fffff
9986 23:42:19.621460 INFO: [APUAPC] D15_APC_3: 0x0
9987 23:42:19.625284 INFO: [APUAPC] APC_CON: 0x4
9988 23:42:19.628022 INFO: [NOCDAPC] D0_APC_0: 0x0
9989 23:42:19.631821 INFO: [NOCDAPC] D0_APC_1: 0x0
9990 23:42:19.634396 INFO: [NOCDAPC] D1_APC_0: 0x0
9991 23:42:19.637767 INFO: [NOCDAPC] D1_APC_1: 0xfff
9992 23:42:19.641165 INFO: [NOCDAPC] D2_APC_0: 0x0
9993 23:42:19.644490 INFO: [NOCDAPC] D2_APC_1: 0xfff
9994 23:42:19.644586 INFO: [NOCDAPC] D3_APC_0: 0x0
9995 23:42:19.647885 INFO: [NOCDAPC] D3_APC_1: 0xfff
9996 23:42:19.651292 INFO: [NOCDAPC] D4_APC_0: 0x0
9997 23:42:19.654765 INFO: [NOCDAPC] D4_APC_1: 0xfff
9998 23:42:19.658116 INFO: [NOCDAPC] D5_APC_0: 0x0
9999 23:42:19.661504 INFO: [NOCDAPC] D5_APC_1: 0xfff
10000 23:42:19.664755 INFO: [NOCDAPC] D6_APC_0: 0x0
10001 23:42:19.667602 INFO: [NOCDAPC] D6_APC_1: 0xfff
10002 23:42:19.670974 INFO: [NOCDAPC] D7_APC_0: 0x0
10003 23:42:19.674172 INFO: [NOCDAPC] D7_APC_1: 0xfff
10004 23:42:19.677397 INFO: [NOCDAPC] D8_APC_0: 0x0
10005 23:42:19.677483 INFO: [NOCDAPC] D8_APC_1: 0xfff
10006 23:42:19.680644 INFO: [NOCDAPC] D9_APC_0: 0x0
10007 23:42:19.684038 INFO: [NOCDAPC] D9_APC_1: 0xfff
10008 23:42:19.687618 INFO: [NOCDAPC] D10_APC_0: 0x0
10009 23:42:19.690986 INFO: [NOCDAPC] D10_APC_1: 0xfff
10010 23:42:19.694162 INFO: [NOCDAPC] D11_APC_0: 0x0
10011 23:42:19.697448 INFO: [NOCDAPC] D11_APC_1: 0xfff
10012 23:42:19.700916 INFO: [NOCDAPC] D12_APC_0: 0x0
10013 23:42:19.704213 INFO: [NOCDAPC] D12_APC_1: 0xfff
10014 23:42:19.707611 INFO: [NOCDAPC] D13_APC_0: 0x0
10015 23:42:19.710973 INFO: [NOCDAPC] D13_APC_1: 0xfff
10016 23:42:19.714348 INFO: [NOCDAPC] D14_APC_0: 0x0
10017 23:42:19.717356 INFO: [NOCDAPC] D14_APC_1: 0xfff
10018 23:42:19.720495 INFO: [NOCDAPC] D15_APC_0: 0x0
10019 23:42:19.723773 INFO: [NOCDAPC] D15_APC_1: 0xfff
10020 23:42:19.723883 INFO: [NOCDAPC] APC_CON: 0x4
10021 23:42:19.727375 INFO: [APUAPC] set_apusys_apc done
10022 23:42:19.730752 INFO: [DEVAPC] devapc_init done
10023 23:42:19.737000 INFO: GICv3 without legacy support detected.
10024 23:42:19.740479 INFO: ARM GICv3 driver initialized in EL3
10025 23:42:19.744124 INFO: Maximum SPI INTID supported: 639
10026 23:42:19.746936 INFO: BL31: Initializing runtime services
10027 23:42:19.753596 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10028 23:42:19.756921 INFO: SPM: enable CPC mode
10029 23:42:19.760384 INFO: mcdi ready for mcusys-off-idle and system suspend
10030 23:42:19.767084 INFO: BL31: Preparing for EL3 exit to normal world
10031 23:42:19.770218 INFO: Entry point address = 0x80000000
10032 23:42:19.770309 INFO: SPSR = 0x8
10033 23:42:19.777600
10034 23:42:19.777705
10035 23:42:19.777812
10036 23:42:19.780519 Starting depthcharge on Spherion...
10037 23:42:19.780615
10038 23:42:19.780691 Wipe memory regions:
10039 23:42:19.780752
10040 23:42:19.781432 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10041 23:42:19.781532 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10042 23:42:19.781620 Setting prompt string to ['asurada:']
10043 23:42:19.781711 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10044 23:42:19.784233 [0x00000040000000, 0x00000054600000)
10045 23:42:19.906310
10046 23:42:19.906472 [0x00000054660000, 0x00000080000000)
10047 23:42:20.167227
10048 23:42:20.167398 [0x000000821a7280, 0x000000ffe64000)
10049 23:42:20.911723
10050 23:42:20.911872 [0x00000100000000, 0x00000240000000)
10051 23:42:22.801521
10052 23:42:22.804809 Initializing XHCI USB controller at 0x11200000.
10053 23:42:23.842993
10054 23:42:23.845917 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10055 23:42:23.846040
10056 23:42:23.846134
10057 23:42:23.846452 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10059 23:42:23.946825 asurada: tftpboot 192.168.201.1 14172912/tftp-deploy-1lu6qxlv/kernel/image.itb 14172912/tftp-deploy-1lu6qxlv/kernel/cmdline
10060 23:42:23.947023 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10061 23:42:23.947209 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10062 23:42:23.951333 tftpboot 192.168.201.1 14172912/tftp-deploy-1lu6qxlv/kernel/image.itbtp-deploy-1lu6qxlv/kernel/cmdline
10063 23:42:23.951456
10064 23:42:23.951569 Waiting for link
10065 23:42:24.111960
10066 23:42:24.112101 R8152: Initializing
10067 23:42:24.112171
10068 23:42:24.115242 Version 6 (ocp_data = 5c30)
10069 23:42:24.115343
10070 23:42:24.118657 R8152: Done initializing
10071 23:42:24.118740
10072 23:42:24.118806 Adding net device
10073 23:42:26.210881
10074 23:42:26.211021 done.
10075 23:42:26.211093
10076 23:42:26.211172 MAC: 00:24:32:30:78:ff
10077 23:42:26.211275
10078 23:42:26.214151 Sending DHCP discover... done.
10079 23:42:26.214236
10080 23:42:26.217400 Waiting for reply... done.
10081 23:42:26.217482
10082 23:42:26.220521 Sending DHCP request... done.
10083 23:42:26.220643
10084 23:42:26.223972 Waiting for reply... done.
10085 23:42:26.224053
10086 23:42:26.224118 My ip is 192.168.201.21
10087 23:42:26.224179
10088 23:42:26.227245 The DHCP server ip is 192.168.201.1
10089 23:42:26.227327
10090 23:42:26.234528 TFTP server IP predefined by user: 192.168.201.1
10091 23:42:26.234610
10092 23:42:26.240578 Bootfile predefined by user: 14172912/tftp-deploy-1lu6qxlv/kernel/image.itb
10093 23:42:26.240676
10094 23:42:26.240740 Sending tftp read request... done.
10095 23:42:26.244112
10096 23:42:26.247453 Waiting for the transfer...
10097 23:42:26.247535
10098 23:42:26.780337 00000000 ################################################################
10099 23:42:26.780499
10100 23:42:27.308880 00080000 ################################################################
10101 23:42:27.309084
10102 23:42:27.831723 00100000 ################################################################
10103 23:42:27.831923
10104 23:42:28.363481 00180000 ################################################################
10105 23:42:28.363614
10106 23:42:28.900050 00200000 ################################################################
10107 23:42:28.900224
10108 23:42:29.438024 00280000 ################################################################
10109 23:42:29.438203
10110 23:42:29.976049 00300000 ################################################################
10111 23:42:29.976246
10112 23:42:30.504549 00380000 ################################################################
10113 23:42:30.504780
10114 23:42:31.050151 00400000 ################################################################
10115 23:42:31.050294
10116 23:42:31.617872 00480000 ################################################################
10117 23:42:31.618007
10118 23:42:32.172339 00500000 ################################################################
10119 23:42:32.172471
10120 23:42:32.741707 00580000 ################################################################
10121 23:42:32.741919
10122 23:42:33.306939 00600000 ################################################################
10123 23:42:33.307149
10124 23:42:33.867703 00680000 ################################################################
10125 23:42:33.867841
10126 23:42:34.421769 00700000 ################################################################
10127 23:42:34.421906
10128 23:42:34.969782 00780000 ################################################################
10129 23:42:34.969973
10130 23:42:35.499974 00800000 ################################################################
10131 23:42:35.500165
10132 23:42:36.045444 00880000 ################################################################
10133 23:42:36.045578
10134 23:42:36.590841 00900000 ################################################################
10135 23:42:36.591051
10136 23:42:37.141866 00980000 ################################################################
10137 23:42:37.142002
10138 23:42:37.688079 00a00000 ################################################################
10139 23:42:37.688270
10140 23:42:38.237841 00a80000 ################################################################
10141 23:42:38.238034
10142 23:42:38.788399 00b00000 ################################################################
10143 23:42:38.788569
10144 23:42:39.337047 00b80000 ################################################################
10145 23:42:39.337211
10146 23:42:39.899165 00c00000 ################################################################
10147 23:42:39.899314
10148 23:42:40.452156 00c80000 ################################################################
10149 23:42:40.452343
10150 23:42:41.002765 00d00000 ################################################################
10151 23:42:41.002902
10152 23:42:41.552040 00d80000 ################################################################
10153 23:42:41.552226
10154 23:42:42.106539 00e00000 ################################################################
10155 23:42:42.106684
10156 23:42:42.667822 00e80000 ################################################################
10157 23:42:42.667999
10158 23:42:43.243621 00f00000 ################################################################
10159 23:42:43.243769
10160 23:42:43.793543 00f80000 ################################################################
10161 23:42:43.793675
10162 23:42:44.335408 01000000 ################################################################
10163 23:42:44.335566
10164 23:42:44.901791 01080000 ################################################################
10165 23:42:44.901945
10166 23:42:45.478312 01100000 ################################################################
10167 23:42:45.478460
10168 23:42:46.071581 01180000 ################################################################
10169 23:42:46.071723
10170 23:42:46.640050 01200000 ################################################################
10171 23:42:46.640251
10172 23:42:47.227227 01280000 ################################################################
10173 23:42:47.227373
10174 23:42:47.794091 01300000 ################################################################
10175 23:42:47.794263
10176 23:42:48.356393 01380000 ################################################################
10177 23:42:48.356571
10178 23:42:48.927792 01400000 ################################################################
10179 23:42:48.927959
10180 23:42:49.490915 01480000 ################################################################
10181 23:42:49.491091
10182 23:42:50.052487 01500000 ################################################################
10183 23:42:50.052682
10184 23:42:50.615175 01580000 ################################################################
10185 23:42:50.615311
10186 23:42:51.175998 01600000 ################################################################
10187 23:42:51.176170
10188 23:42:51.723523 01680000 ################################################################
10189 23:42:51.723659
10190 23:42:52.252991 01700000 ################################################################
10191 23:42:52.253154
10192 23:42:52.790917 01780000 ################################################################
10193 23:42:52.791058
10194 23:42:53.344774 01800000 ################################################################
10195 23:42:53.344913
10196 23:42:53.887394 01880000 ################################################################
10197 23:42:53.887529
10198 23:42:54.460908 01900000 ################################################################
10199 23:42:54.461045
10200 23:42:55.013194 01980000 ################################################################
10201 23:42:55.013330
10202 23:42:55.566566 01a00000 ################################################################
10203 23:42:55.566743
10204 23:42:56.116342 01a80000 ################################################################
10205 23:42:56.116493
10206 23:42:56.679013 01b00000 ################################################################
10207 23:42:56.679237
10208 23:42:57.272701 01b80000 ################################################################
10209 23:42:57.272919
10210 23:42:57.831532 01c00000 ################################################################
10211 23:42:57.831727
10212 23:42:58.375380 01c80000 ################################################################
10213 23:42:58.375584
10214 23:42:58.920947 01d00000 ################################################################
10215 23:42:58.921166
10216 23:42:59.501558 01d80000 ################################################################
10217 23:42:59.501752
10218 23:43:00.086108 01e00000 ################################################################
10219 23:43:00.086251
10220 23:43:00.662494 01e80000 ################################################################
10221 23:43:00.662633
10222 23:43:01.199362 01f00000 ################################################################
10223 23:43:01.199514
10224 23:43:01.737224 01f80000 ################################################################
10225 23:43:01.737369
10226 23:43:02.267982 02000000 ################################################################
10227 23:43:02.268131
10228 23:43:02.797956 02080000 ################################################################
10229 23:43:02.798140
10230 23:43:03.332210 02100000 ################################################################
10231 23:43:03.332423
10232 23:43:03.868192 02180000 ################################################################
10233 23:43:03.868343
10234 23:43:04.404719 02200000 ################################################################
10235 23:43:04.404866
10236 23:43:04.942802 02280000 ################################################################
10237 23:43:04.942947
10238 23:43:05.475451 02300000 ################################################################
10239 23:43:05.475605
10240 23:43:06.017909 02380000 ################################################################
10241 23:43:06.018039
10242 23:43:06.565374 02400000 ################################################################
10243 23:43:06.565506
10244 23:43:07.125879 02480000 ################################################################
10245 23:43:07.126014
10246 23:43:07.676225 02500000 ################################################################
10247 23:43:07.676384
10248 23:43:08.225039 02580000 ################################################################
10249 23:43:08.225179
10250 23:43:08.769444 02600000 ################################################################
10251 23:43:08.769629
10252 23:43:09.317215 02680000 ################################################################
10253 23:43:09.317410
10254 23:43:09.845578 02700000 ################################################################
10255 23:43:09.845795
10256 23:43:10.380757 02780000 ################################################################
10257 23:43:10.380943
10258 23:43:10.915942 02800000 ################################################################
10259 23:43:10.916145
10260 23:43:11.454374 02880000 ################################################################
10261 23:43:11.454550
10262 23:43:11.996398 02900000 ################################################################
10263 23:43:11.996609
10264 23:43:12.536888 02980000 ################################################################
10265 23:43:12.537037
10266 23:43:13.092520 02a00000 ################################################################
10267 23:43:13.092711
10268 23:43:13.647985 02a80000 ################################################################
10269 23:43:13.648163
10270 23:43:14.205193 02b00000 ################################################################
10271 23:43:14.205382
10272 23:43:14.756810 02b80000 ################################################################
10273 23:43:14.756992
10274 23:43:15.298888 02c00000 ################################################################
10275 23:43:15.299079
10276 23:43:15.842160 02c80000 ################################################################
10277 23:43:15.842308
10278 23:43:16.396203 02d00000 ################################################################
10279 23:43:16.396412
10280 23:43:16.944314 02d80000 ################################################################
10281 23:43:16.944521
10282 23:43:17.504262 02e00000 ################################################################
10283 23:43:17.504426
10284 23:43:18.062769 02e80000 ################################################################
10285 23:43:18.062913
10286 23:43:18.627218 02f00000 ################################################################
10287 23:43:18.627415
10288 23:43:19.201910 02f80000 ################################################################
10289 23:43:19.202083
10290 23:43:19.789841 03000000 ################################################################
10291 23:43:19.790015
10292 23:43:20.382977 03080000 ################################################################
10293 23:43:20.383182
10294 23:43:20.987533 03100000 ################################################################
10295 23:43:20.987767
10296 23:43:21.590472 03180000 ################################################################
10297 23:43:21.590739
10298 23:43:22.134955 03200000 ################################################################
10299 23:43:22.135145
10300 23:43:22.713393 03280000 ################################################################
10301 23:43:22.713609
10302 23:43:23.262862 03300000 ################################################################
10303 23:43:23.263036
10304 23:43:23.795902 03380000 ################################################################
10305 23:43:23.796102
10306 23:43:24.330538 03400000 ################################################################
10307 23:43:24.330673
10308 23:43:24.883141 03480000 ################################################################
10309 23:43:24.883338
10310 23:43:25.410746 03500000 ################################################################
10311 23:43:25.410905
10312 23:43:25.941514 03580000 ################################################################
10313 23:43:25.941648
10314 23:43:26.472279 03600000 ################################################################
10315 23:43:26.472472
10316 23:43:27.032465 03680000 ################################################################
10317 23:43:27.032654
10318 23:43:27.581565 03700000 ################################################################
10319 23:43:27.581700
10320 23:43:28.120946 03780000 ################################################################
10321 23:43:28.121081
10322 23:43:28.665035 03800000 ################################################################
10323 23:43:28.665173
10324 23:43:29.199201 03880000 ################################################################
10325 23:43:29.199335
10326 23:43:29.728187 03900000 ################################################################
10327 23:43:29.728328
10328 23:43:30.264226 03980000 ################################################################
10329 23:43:30.264409
10330 23:43:30.797809 03a00000 ################################################################
10331 23:43:30.797954
10332 23:43:31.338521 03a80000 ################################################################
10333 23:43:31.338718
10334 23:43:31.880611 03b00000 ################################################################
10335 23:43:31.880745
10336 23:43:32.439745 03b80000 ################################################################
10337 23:43:32.439899
10338 23:43:32.999674 03c00000 ################################################################
10339 23:43:32.999814
10340 23:43:33.542212 03c80000 ################################################################
10341 23:43:33.542344
10342 23:43:34.082485 03d00000 ################################################################
10343 23:43:34.082619
10344 23:43:34.615244 03d80000 ################################################################
10345 23:43:34.615383
10346 23:43:34.850043 03e00000 ############################# done.
10347 23:43:34.850182
10348 23:43:34.853311 The bootfile was 65241570 bytes long.
10349 23:43:34.853403
10350 23:43:34.856167 Sending tftp read request... done.
10351 23:43:34.856252
10352 23:43:34.856320 Waiting for the transfer...
10353 23:43:34.859529
10354 23:43:34.859642 00000000 # done.
10355 23:43:34.859740
10356 23:43:34.866290 Command line loaded dynamically from TFTP file: 14172912/tftp-deploy-1lu6qxlv/kernel/cmdline
10357 23:43:34.866395
10358 23:43:34.879788 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10359 23:43:34.879880
10360 23:43:34.883097 Loading FIT.
10361 23:43:34.883182
10362 23:43:34.886429 Image ramdisk-1 has 52130845 bytes.
10363 23:43:34.886515
10364 23:43:34.889486 Image fdt-1 has 47258 bytes.
10365 23:43:34.889571
10366 23:43:34.889638 Image kernel-1 has 13061430 bytes.
10367 23:43:34.893109
10368 23:43:34.899258 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10369 23:43:34.899346
10370 23:43:34.916399 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10371 23:43:34.919258
10372 23:43:34.922646 Choosing best match conf-1 for compat google,spherion-rev2.
10373 23:43:34.927306
10374 23:43:34.932009 Connected to device vid:did:rid of 1ae0:0028:00
10375 23:43:34.938563
10376 23:43:34.942201 tpm_get_response: command 0x17b, return code 0x0
10377 23:43:34.942316
10378 23:43:34.945127 ec_init: CrosEC protocol v3 supported (256, 248)
10379 23:43:34.949482
10380 23:43:34.952551 tpm_cleanup: add release locality here.
10381 23:43:34.952669
10382 23:43:34.952764 Shutting down all USB controllers.
10383 23:43:34.955946
10384 23:43:34.956058 Removing current net device
10385 23:43:34.956156
10386 23:43:34.962678 Exiting depthcharge with code 4 at timestamp: 104494080
10387 23:43:34.962794
10388 23:43:34.965634 LZMA decompressing kernel-1 to 0x821a6718
10389 23:43:34.965745
10390 23:43:34.969004 LZMA decompressing kernel-1 to 0x40000000
10391 23:43:36.578523
10392 23:43:36.578665 jumping to kernel
10393 23:43:36.579196 end: 2.2.4 bootloader-commands (duration 00:01:17) [common]
10394 23:43:36.579300 start: 2.2.5 auto-login-action (timeout 00:03:08) [common]
10395 23:43:36.579379 Setting prompt string to ['Linux version [0-9]']
10396 23:43:36.579450 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10397 23:43:36.579524 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10398 23:43:36.661052
10399 23:43:36.663859 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10400 23:43:36.667663 start: 2.2.5.1 login-action (timeout 00:03:08) [common]
10401 23:43:36.667841 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10402 23:43:36.667973 Setting prompt string to []
10403 23:43:36.668106 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10404 23:43:36.668245 Using line separator: #'\n'#
10405 23:43:36.668352 No login prompt set.
10406 23:43:36.668472 Parsing kernel messages
10407 23:43:36.668588 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10408 23:43:36.668794 [login-action] Waiting for messages, (timeout 00:03:08)
10409 23:43:36.668917 Waiting using forced prompt support (timeout 00:01:34)
10410 23:43:36.687072 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j217067-arm64-gcc-10-defconfig-arm64-chromebook-s48tj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024
10411 23:43:36.690409 [ 0.000000] random: crng init done
10412 23:43:36.697233 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10413 23:43:36.700794 [ 0.000000] efi: UEFI not found.
10414 23:43:36.707017 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10415 23:43:36.713512 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10416 23:43:36.723821 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10417 23:43:36.733615 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10418 23:43:36.740476 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10419 23:43:36.746766 [ 0.000000] printk: bootconsole [mtk8250] enabled
10420 23:43:36.753456 [ 0.000000] NUMA: No NUMA configuration found
10421 23:43:36.759761 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10422 23:43:36.763531 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10423 23:43:36.766670 [ 0.000000] Zone ranges:
10424 23:43:36.773602 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10425 23:43:36.776688 [ 0.000000] DMA32 empty
10426 23:43:36.783106 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10427 23:43:36.786632 [ 0.000000] Movable zone start for each node
10428 23:43:36.789825 [ 0.000000] Early memory node ranges
10429 23:43:36.796445 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10430 23:43:36.802986 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10431 23:43:36.809665 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10432 23:43:36.816346 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10433 23:43:36.819688 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10434 23:43:36.829446 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10435 23:43:36.885043 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10436 23:43:36.891845 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10437 23:43:36.898429 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10438 23:43:36.901449 [ 0.000000] psci: probing for conduit method from DT.
10439 23:43:36.908087 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10440 23:43:36.911532 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10441 23:43:36.918074 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10442 23:43:36.921535 [ 0.000000] psci: SMC Calling Convention v1.2
10443 23:43:36.928090 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10444 23:43:36.931581 [ 0.000000] Detected VIPT I-cache on CPU0
10445 23:43:36.938387 [ 0.000000] CPU features: detected: GIC system register CPU interface
10446 23:43:36.944702 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10447 23:43:36.951592 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10448 23:43:36.957703 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10449 23:43:36.964330 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10450 23:43:36.974313 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10451 23:43:36.977634 [ 0.000000] alternatives: applying boot alternatives
10452 23:43:36.984289 [ 0.000000] Fallback order for Node 0: 0
10453 23:43:36.990925 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10454 23:43:36.994508 [ 0.000000] Policy zone: Normal
10455 23:43:37.007794 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10456 23:43:37.017628 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10457 23:43:37.028818 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10458 23:43:37.038988 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10459 23:43:37.045499 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10460 23:43:37.048964 <6>[ 0.000000] software IO TLB: area num 8.
10461 23:43:37.105329 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10462 23:43:37.254718 <6>[ 0.000000] Memory: 7913280K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 439488K reserved, 32768K cma-reserved)
10463 23:43:37.261111 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10464 23:43:37.267717 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10465 23:43:37.271240 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10466 23:43:37.277513 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10467 23:43:37.284315 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10468 23:43:37.287610 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10469 23:43:37.297348 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10470 23:43:37.304018 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10471 23:43:37.310667 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10472 23:43:37.317484 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10473 23:43:37.320635 <6>[ 0.000000] GICv3: 608 SPIs implemented
10474 23:43:37.324177 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10475 23:43:37.330568 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10476 23:43:37.333857 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10477 23:43:37.340285 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10478 23:43:37.353498 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10479 23:43:37.366951 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10480 23:43:37.373643 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10481 23:43:37.381314 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10482 23:43:37.394488 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10483 23:43:37.401065 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10484 23:43:37.407881 <6>[ 0.009229] Console: colour dummy device 80x25
10485 23:43:37.417784 <6>[ 0.013955] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10486 23:43:37.423958 <6>[ 0.024397] pid_max: default: 32768 minimum: 301
10487 23:43:37.427855 <6>[ 0.029262] LSM: Security Framework initializing
10488 23:43:37.433987 <6>[ 0.034199] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10489 23:43:37.444145 <6>[ 0.042015] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10490 23:43:37.454181 <6>[ 0.051427] cblist_init_generic: Setting adjustable number of callback queues.
10491 23:43:37.457211 <6>[ 0.058916] cblist_init_generic: Setting shift to 3 and lim to 1.
10492 23:43:37.467134 <6>[ 0.065256] cblist_init_generic: Setting adjustable number of callback queues.
10493 23:43:37.473690 <6>[ 0.072729] cblist_init_generic: Setting shift to 3 and lim to 1.
10494 23:43:37.477150 <6>[ 0.079130] rcu: Hierarchical SRCU implementation.
10495 23:43:37.483921 <6>[ 0.084146] rcu: Max phase no-delay instances is 1000.
10496 23:43:37.490139 <6>[ 0.091174] EFI services will not be available.
10497 23:43:37.493314 <6>[ 0.096153] smp: Bringing up secondary CPUs ...
10498 23:43:37.501929 <6>[ 0.101229] Detected VIPT I-cache on CPU1
10499 23:43:37.508589 <6>[ 0.101301] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10500 23:43:37.515434 <6>[ 0.101333] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10501 23:43:37.518378 <6>[ 0.101662] Detected VIPT I-cache on CPU2
10502 23:43:37.525065 <6>[ 0.101712] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10503 23:43:37.535150 <6>[ 0.101728] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10504 23:43:37.538486 <6>[ 0.101984] Detected VIPT I-cache on CPU3
10505 23:43:37.545277 <6>[ 0.102030] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10506 23:43:37.551537 <6>[ 0.102044] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10507 23:43:37.555164 <6>[ 0.102348] CPU features: detected: Spectre-v4
10508 23:43:37.561450 <6>[ 0.102354] CPU features: detected: Spectre-BHB
10509 23:43:37.565049 <6>[ 0.102359] Detected PIPT I-cache on CPU4
10510 23:43:37.571543 <6>[ 0.102417] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10511 23:43:37.577733 <6>[ 0.102434] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10512 23:43:37.584424 <6>[ 0.102727] Detected PIPT I-cache on CPU5
10513 23:43:37.591220 <6>[ 0.102790] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10514 23:43:37.597819 <6>[ 0.102806] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10515 23:43:37.601316 <6>[ 0.103083] Detected PIPT I-cache on CPU6
10516 23:43:37.607500 <6>[ 0.103148] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10517 23:43:37.614051 <6>[ 0.103164] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10518 23:43:37.620867 <6>[ 0.103460] Detected PIPT I-cache on CPU7
10519 23:43:37.627755 <6>[ 0.103525] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10520 23:43:37.633994 <6>[ 0.103540] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10521 23:43:37.637297 <6>[ 0.103587] smp: Brought up 1 node, 8 CPUs
10522 23:43:37.643967 <6>[ 0.244976] SMP: Total of 8 processors activated.
10523 23:43:37.647503 <6>[ 0.249896] CPU features: detected: 32-bit EL0 Support
10524 23:43:37.657281 <6>[ 0.255259] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10525 23:43:37.663569 <6>[ 0.264114] CPU features: detected: Common not Private translations
10526 23:43:37.670419 <6>[ 0.270590] CPU features: detected: CRC32 instructions
10527 23:43:37.673557 <6>[ 0.275941] CPU features: detected: RCpc load-acquire (LDAPR)
10528 23:43:37.680263 <6>[ 0.281901] CPU features: detected: LSE atomic instructions
10529 23:43:37.686944 <6>[ 0.287683] CPU features: detected: Privileged Access Never
10530 23:43:37.693783 <6>[ 0.293462] CPU features: detected: RAS Extension Support
10531 23:43:37.699997 <6>[ 0.299106] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10532 23:43:37.703399 <6>[ 0.306327] CPU: All CPU(s) started at EL2
10533 23:43:37.709721 <6>[ 0.310644] alternatives: applying system-wide alternatives
10534 23:43:37.719612 <6>[ 0.321478] devtmpfs: initialized
10535 23:43:37.735321 <6>[ 0.330284] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10536 23:43:37.741829 <6>[ 0.340245] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10537 23:43:37.748187 <6>[ 0.347947] pinctrl core: initialized pinctrl subsystem
10538 23:43:37.751646 <6>[ 0.354625] DMI not present or invalid.
10539 23:43:37.758170 <6>[ 0.359034] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10540 23:43:37.768280 <6>[ 0.365883] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10541 23:43:37.774604 <6>[ 0.373472] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10542 23:43:37.784822 <6>[ 0.381695] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10543 23:43:37.787961 <6>[ 0.389934] audit: initializing netlink subsys (disabled)
10544 23:43:37.798303 <5>[ 0.395627] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10545 23:43:37.804541 <6>[ 0.396341] thermal_sys: Registered thermal governor 'step_wise'
10546 23:43:37.811607 <6>[ 0.403595] thermal_sys: Registered thermal governor 'power_allocator'
10547 23:43:37.814386 <6>[ 0.409849] cpuidle: using governor menu
10548 23:43:37.820942 <6>[ 0.420809] NET: Registered PF_QIPCRTR protocol family
10549 23:43:37.827912 <6>[ 0.426291] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10550 23:43:37.831132 <6>[ 0.433399] ASID allocator initialised with 32768 entries
10551 23:43:37.838362 <6>[ 0.439972] Serial: AMBA PL011 UART driver
10552 23:43:37.847167 <4>[ 0.448794] Trying to register duplicate clock ID: 134
10553 23:43:37.904913 <6>[ 0.509963] KASLR enabled
10554 23:43:37.919460 <6>[ 0.517680] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10555 23:43:37.926065 <6>[ 0.524694] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10556 23:43:37.932656 <6>[ 0.531185] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10557 23:43:37.938839 <6>[ 0.538191] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10558 23:43:37.945875 <6>[ 0.544680] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10559 23:43:37.952111 <6>[ 0.551686] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10560 23:43:37.959239 <6>[ 0.558172] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10561 23:43:37.965733 <6>[ 0.565176] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10562 23:43:37.969012 <6>[ 0.572704] ACPI: Interpreter disabled.
10563 23:43:37.977631 <6>[ 0.579134] iommu: Default domain type: Translated
10564 23:43:37.983788 <6>[ 0.584248] iommu: DMA domain TLB invalidation policy: strict mode
10565 23:43:37.988898 <5>[ 0.590910] SCSI subsystem initialized
10566 23:43:37.994248 <6>[ 0.595080] usbcore: registered new interface driver usbfs
10567 23:43:38.000482 <6>[ 0.600814] usbcore: registered new interface driver hub
10568 23:43:38.003703 <6>[ 0.606368] usbcore: registered new device driver usb
10569 23:43:38.010903 <6>[ 0.612458] pps_core: LinuxPPS API ver. 1 registered
10570 23:43:38.020902 <6>[ 0.617650] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10571 23:43:38.023831 <6>[ 0.626998] PTP clock support registered
10572 23:43:38.027143 <6>[ 0.631242] EDAC MC: Ver: 3.0.0
10573 23:43:38.034955 <6>[ 0.636403] FPGA manager framework
10574 23:43:38.041123 <6>[ 0.640091] Advanced Linux Sound Architecture Driver Initialized.
10575 23:43:38.044327 <6>[ 0.646859] vgaarb: loaded
10576 23:43:38.051231 <6>[ 0.650010] clocksource: Switched to clocksource arch_sys_counter
10577 23:43:38.054596 <5>[ 0.656453] VFS: Disk quotas dquot_6.6.0
10578 23:43:38.061193 <6>[ 0.660640] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10579 23:43:38.064531 <6>[ 0.667830] pnp: PnP ACPI: disabled
10580 23:43:38.072790 <6>[ 0.674555] NET: Registered PF_INET protocol family
10581 23:43:38.083033 <6>[ 0.680150] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10582 23:43:38.094212 <6>[ 0.692472] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10583 23:43:38.104232 <6>[ 0.701287] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10584 23:43:38.110496 <6>[ 0.709257] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10585 23:43:38.120098 <6>[ 0.717958] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10586 23:43:38.126984 <6>[ 0.727714] TCP: Hash tables configured (established 65536 bind 65536)
10587 23:43:38.133597 <6>[ 0.734578] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10588 23:43:38.143212 <6>[ 0.741776] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10589 23:43:38.150336 <6>[ 0.749475] NET: Registered PF_UNIX/PF_LOCAL protocol family
10590 23:43:38.153609 <6>[ 0.755623] RPC: Registered named UNIX socket transport module.
10591 23:43:38.159938 <6>[ 0.761775] RPC: Registered udp transport module.
10592 23:43:38.163332 <6>[ 0.766709] RPC: Registered tcp transport module.
10593 23:43:38.169800 <6>[ 0.771641] RPC: Registered tcp NFSv4.1 backchannel transport module.
10594 23:43:38.176920 <6>[ 0.778303] PCI: CLS 0 bytes, default 64
10595 23:43:38.179987 <6>[ 0.782636] Unpacking initramfs...
10596 23:43:38.204040 <6>[ 0.802137] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10597 23:43:38.213689 <6>[ 0.810781] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10598 23:43:38.217331 <6>[ 0.819607] kvm [1]: IPA Size Limit: 40 bits
10599 23:43:38.223412 <6>[ 0.824134] kvm [1]: GICv3: no GICV resource entry
10600 23:43:38.226925 <6>[ 0.829155] kvm [1]: disabling GICv2 emulation
10601 23:43:38.233304 <6>[ 0.833836] kvm [1]: GIC system register CPU interface enabled
10602 23:43:38.236691 <6>[ 0.839986] kvm [1]: vgic interrupt IRQ18
10603 23:43:38.243362 <6>[ 0.844336] kvm [1]: VHE mode initialized successfully
10604 23:43:38.249965 <5>[ 0.850547] Initialise system trusted keyrings
10605 23:43:38.256486 <6>[ 0.855302] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10606 23:43:38.263497 <6>[ 0.865327] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10607 23:43:38.270309 <5>[ 0.871775] NFS: Registering the id_resolver key type
10608 23:43:38.273620 <5>[ 0.877084] Key type id_resolver registered
10609 23:43:38.280400 <5>[ 0.881498] Key type id_legacy registered
10610 23:43:38.286805 <6>[ 0.885773] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10611 23:43:38.293503 <6>[ 0.892695] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10612 23:43:38.300032 <6>[ 0.900416] 9p: Installing v9fs 9p2000 file system support
10613 23:43:38.336802 <5>[ 0.938561] Key type asymmetric registered
10614 23:43:38.340100 <5>[ 0.942890] Asymmetric key parser 'x509' registered
10615 23:43:38.350069 <6>[ 0.948024] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10616 23:43:38.353243 <6>[ 0.955638] io scheduler mq-deadline registered
10617 23:43:38.356513 <6>[ 0.960401] io scheduler kyber registered
10618 23:43:38.375234 <6>[ 0.977178] EINJ: ACPI disabled.
10619 23:43:38.407921 <4>[ 1.003222] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10620 23:43:38.417962 <4>[ 1.013835] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10621 23:43:38.433123 <6>[ 1.034514] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10622 23:43:38.440642 <6>[ 1.042436] printk: console [ttyS0] disabled
10623 23:43:38.468954 <6>[ 1.067070] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10624 23:43:38.475428 <6>[ 1.076545] printk: console [ttyS0] enabled
10625 23:43:38.478893 <6>[ 1.076545] printk: console [ttyS0] enabled
10626 23:43:38.485329 <6>[ 1.085441] printk: bootconsole [mtk8250] disabled
10627 23:43:38.488601 <6>[ 1.085441] printk: bootconsole [mtk8250] disabled
10628 23:43:38.495395 <6>[ 1.096453] SuperH (H)SCI(F) driver initialized
10629 23:43:38.498610 <6>[ 1.101746] msm_serial: driver initialized
10630 23:43:38.512470 <6>[ 1.110615] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10631 23:43:38.522160 <6>[ 1.119158] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10632 23:43:38.528547 <6>[ 1.127700] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10633 23:43:38.539002 <6>[ 1.136329] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10634 23:43:38.548790 <6>[ 1.145035] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10635 23:43:38.555095 <6>[ 1.153760] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10636 23:43:38.565287 <6>[ 1.162302] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10637 23:43:38.571959 <6>[ 1.171096] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10638 23:43:38.581974 <6>[ 1.179638] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10639 23:43:38.593258 <6>[ 1.195178] loop: module loaded
10640 23:43:38.599902 <6>[ 1.201157] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10641 23:43:38.622738 <4>[ 1.224452] mtk-pmic-keys: Failed to locate of_node [id: -1]
10642 23:43:38.629306 <6>[ 1.231231] megasas: 07.719.03.00-rc1
10643 23:43:38.638888 <6>[ 1.240752] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10644 23:43:38.651673 <6>[ 1.253381] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10645 23:43:38.668867 <6>[ 1.270081] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10646 23:43:38.724469 <6>[ 1.319983] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10647 23:43:40.430973 <6>[ 3.033126] Freeing initrd memory: 50904K
10648 23:43:40.442818 <6>[ 3.044979] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10649 23:43:40.453951 <6>[ 3.055841] tun: Universal TUN/TAP device driver, 1.6
10650 23:43:40.457386 <6>[ 3.061893] thunder_xcv, ver 1.0
10651 23:43:40.460743 <6>[ 3.065397] thunder_bgx, ver 1.0
10652 23:43:40.463563 <6>[ 3.068896] nicpf, ver 1.0
10653 23:43:40.474567 <6>[ 3.072888] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10654 23:43:40.477580 <6>[ 3.080363] hns3: Copyright (c) 2017 Huawei Corporation.
10655 23:43:40.481134 <6>[ 3.085958] hclge is initializing
10656 23:43:40.487931 <6>[ 3.089540] e1000: Intel(R) PRO/1000 Network Driver
10657 23:43:40.494188 <6>[ 3.094669] e1000: Copyright (c) 1999-2006 Intel Corporation.
10658 23:43:40.497467 <6>[ 3.100681] e1000e: Intel(R) PRO/1000 Network Driver
10659 23:43:40.504414 <6>[ 3.105897] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10660 23:43:40.510864 <6>[ 3.112081] igb: Intel(R) Gigabit Ethernet Network Driver
10661 23:43:40.517566 <6>[ 3.117730] igb: Copyright (c) 2007-2014 Intel Corporation.
10662 23:43:40.523833 <6>[ 3.123566] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10663 23:43:40.530674 <6>[ 3.130084] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10664 23:43:40.534004 <6>[ 3.136546] sky2: driver version 1.30
10665 23:43:40.540539 <6>[ 3.141460] usbcore: registered new device driver r8152-cfgselector
10666 23:43:40.546820 <6>[ 3.147998] usbcore: registered new interface driver r8152
10667 23:43:40.553519 <6>[ 3.153810] VFIO - User Level meta-driver version: 0.3
10668 23:43:40.560036 <6>[ 3.162045] usbcore: registered new interface driver usb-storage
10669 23:43:40.566861 <6>[ 3.168485] usbcore: registered new device driver onboard-usb-hub
10670 23:43:40.575496 <6>[ 3.177595] mt6397-rtc mt6359-rtc: registered as rtc0
10671 23:43:40.585639 <6>[ 3.183058] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T23:43:41 UTC (1717544621)
10672 23:43:40.589020 <6>[ 3.192618] i2c_dev: i2c /dev entries driver
10673 23:43:40.605877 <6>[ 3.204362] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10674 23:43:40.612497 <4>[ 3.213100] cpu cpu0: supply cpu not found, using dummy regulator
10675 23:43:40.618877 <4>[ 3.219524] cpu cpu1: supply cpu not found, using dummy regulator
10676 23:43:40.625752 <4>[ 3.225931] cpu cpu2: supply cpu not found, using dummy regulator
10677 23:43:40.632461 <4>[ 3.232337] cpu cpu3: supply cpu not found, using dummy regulator
10678 23:43:40.638564 <4>[ 3.238735] cpu cpu4: supply cpu not found, using dummy regulator
10679 23:43:40.645405 <4>[ 3.245149] cpu cpu5: supply cpu not found, using dummy regulator
10680 23:43:40.652340 <4>[ 3.251544] cpu cpu6: supply cpu not found, using dummy regulator
10681 23:43:40.658728 <4>[ 3.257941] cpu cpu7: supply cpu not found, using dummy regulator
10682 23:43:40.676500 <6>[ 3.278573] cpu cpu0: EM: created perf domain
10683 23:43:40.679878 <6>[ 3.283517] cpu cpu4: EM: created perf domain
10684 23:43:40.686908 <6>[ 3.289079] sdhci: Secure Digital Host Controller Interface driver
10685 23:43:40.693689 <6>[ 3.295512] sdhci: Copyright(c) Pierre Ossman
10686 23:43:40.700478 <6>[ 3.300460] Synopsys Designware Multimedia Card Interface Driver
10687 23:43:40.707253 <6>[ 3.307101] sdhci-pltfm: SDHCI platform and OF driver helper
10688 23:43:40.710165 <6>[ 3.307159] mmc0: CQHCI version 5.10
10689 23:43:40.717089 <6>[ 3.317360] ledtrig-cpu: registered to indicate activity on CPUs
10690 23:43:40.723610 <6>[ 3.324410] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10691 23:43:40.729972 <6>[ 3.331467] usbcore: registered new interface driver usbhid
10692 23:43:40.733444 <6>[ 3.337289] usbhid: USB HID core driver
10693 23:43:40.740094 <6>[ 3.341482] spi_master spi0: will run message pump with realtime priority
10694 23:43:40.784545 <6>[ 3.380105] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10695 23:43:40.803799 <6>[ 3.396139] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10696 23:43:40.807575 <6>[ 3.408529] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16414
10697 23:43:40.814661 <6>[ 3.416480] cros-ec-spi spi0.0: Chrome EC device registered
10698 23:43:40.821732 <6>[ 3.422516] mmc0: Command Queue Engine enabled
10699 23:43:40.828394 <6>[ 3.427291] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10700 23:43:40.831646 <6>[ 3.434941] mmcblk0: mmc0:0001 DA4128 116 GiB
10701 23:43:40.841247 <6>[ 3.443340] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10702 23:43:40.848753 <6>[ 3.450924] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10703 23:43:40.858719 <6>[ 3.456431] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10704 23:43:40.865627 <6>[ 3.456877] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10705 23:43:40.868890 <6>[ 3.467136] NET: Registered PF_PACKET protocol family
10706 23:43:40.875597 <6>[ 3.471704] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10707 23:43:40.878658 <6>[ 3.476342] 9pnet: Installing 9P2000 support
10708 23:43:40.885397 <5>[ 3.487350] Key type dns_resolver registered
10709 23:43:40.888865 <6>[ 3.492366] registered taskstats version 1
10710 23:43:40.895299 <5>[ 3.496751] Loading compiled-in X.509 certificates
10711 23:43:40.924657 <4>[ 3.520263] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10712 23:43:40.934821 <4>[ 3.531188] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10713 23:43:40.950812 <6>[ 3.552657] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10714 23:43:40.957910 <6>[ 3.559593] xhci-mtk 11200000.usb: xHCI Host Controller
10715 23:43:40.963943 <6>[ 3.565122] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10716 23:43:40.974473 <6>[ 3.572988] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10717 23:43:40.981375 <6>[ 3.582418] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10718 23:43:40.987846 <6>[ 3.588600] xhci-mtk 11200000.usb: xHCI Host Controller
10719 23:43:40.994018 <6>[ 3.594090] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10720 23:43:41.000813 <6>[ 3.601744] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10721 23:43:41.007623 <6>[ 3.609583] hub 1-0:1.0: USB hub found
10722 23:43:41.011028 <6>[ 3.613610] hub 1-0:1.0: 1 port detected
10723 23:43:41.020570 <6>[ 3.617900] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10724 23:43:41.024292 <6>[ 3.626647] hub 2-0:1.0: USB hub found
10725 23:43:41.027510 <6>[ 3.630669] hub 2-0:1.0: 1 port detected
10726 23:43:41.035693 <6>[ 3.637724] mtk-msdc 11f70000.mmc: Got CD GPIO
10727 23:43:41.048769 <6>[ 3.647714] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10728 23:43:41.055453 <6>[ 3.655745] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10729 23:43:41.065338 <4>[ 3.663657] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10730 23:43:41.075787 <6>[ 3.673216] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10731 23:43:41.082127 <6>[ 3.681300] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10732 23:43:41.088722 <6>[ 3.689323] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10733 23:43:41.098694 <6>[ 3.697245] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10734 23:43:41.104953 <6>[ 3.705063] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10735 23:43:41.115309 <6>[ 3.712884] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10736 23:43:41.125254 <6>[ 3.723293] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10737 23:43:41.131564 <6>[ 3.731651] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10738 23:43:41.141781 <6>[ 3.740000] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10739 23:43:41.148082 <6>[ 3.748339] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10740 23:43:41.157913 <6>[ 3.756676] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10741 23:43:41.164825 <6>[ 3.765014] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10742 23:43:41.174556 <6>[ 3.773353] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10743 23:43:41.184550 <6>[ 3.781692] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10744 23:43:41.190928 <6>[ 3.790032] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10745 23:43:41.200934 <6>[ 3.798370] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10746 23:43:41.207788 <6>[ 3.806708] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10747 23:43:41.217602 <6>[ 3.815045] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10748 23:43:41.224311 <6>[ 3.823384] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10749 23:43:41.234081 <6>[ 3.831722] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10750 23:43:41.240653 <6>[ 3.840059] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10751 23:43:41.247324 <6>[ 3.848777] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10752 23:43:41.253663 <6>[ 3.855919] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10753 23:43:41.260902 <6>[ 3.862693] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10754 23:43:41.271061 <6>[ 3.869455] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10755 23:43:41.277717 <6>[ 3.876389] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10756 23:43:41.283841 <6>[ 3.883240] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10757 23:43:41.294147 <6>[ 3.892377] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10758 23:43:41.303919 <6>[ 3.901498] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10759 23:43:41.313688 <6>[ 3.910795] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10760 23:43:41.323558 <6>[ 3.920262] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10761 23:43:41.330314 <6>[ 3.929727] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10762 23:43:41.340307 <6>[ 3.938848] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10763 23:43:41.350347 <6>[ 3.948315] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10764 23:43:41.360053 <6>[ 3.957432] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10765 23:43:41.369860 <6>[ 3.966726] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10766 23:43:41.379673 <6>[ 3.976886] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10767 23:43:41.389380 <6>[ 3.988296] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10768 23:43:41.435560 <6>[ 4.034309] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10769 23:43:41.590417 <6>[ 4.192175] hub 1-1:1.0: USB hub found
10770 23:43:41.593236 <6>[ 4.196665] hub 1-1:1.0: 4 ports detected
10771 23:43:41.603776 <6>[ 4.205706] hub 1-1:1.0: USB hub found
10772 23:43:41.606918 <6>[ 4.210317] hub 1-1:1.0: 4 ports detected
10773 23:43:41.716091 <6>[ 4.314625] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10774 23:43:41.742296 <6>[ 4.344024] hub 2-1:1.0: USB hub found
10775 23:43:41.745023 <6>[ 4.348518] hub 2-1:1.0: 3 ports detected
10776 23:43:41.754651 <6>[ 4.356621] hub 2-1:1.0: USB hub found
10777 23:43:41.758006 <6>[ 4.361063] hub 2-1:1.0: 3 ports detected
10778 23:43:41.931695 <6>[ 4.530326] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10779 23:43:42.063892 <6>[ 4.665897] hub 1-1.4:1.0: USB hub found
10780 23:43:42.067105 <6>[ 4.670489] hub 1-1.4:1.0: 2 ports detected
10781 23:43:42.075911 <6>[ 4.677922] hub 1-1.4:1.0: USB hub found
10782 23:43:42.079219 <6>[ 4.682546] hub 1-1.4:1.0: 2 ports detected
10783 23:43:42.143858 <6>[ 4.742483] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10784 23:43:42.252421 <6>[ 4.850958] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10785 23:43:42.288424 <4>[ 4.887285] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10786 23:43:42.298500 <4>[ 4.896395] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10787 23:43:42.333389 <6>[ 4.935474] r8152 2-1.3:1.0 eth0: v1.12.13
10788 23:43:42.375752 <6>[ 4.974376] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10789 23:43:42.567419 <6>[ 5.166343] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10790 23:43:44.001447 <6>[ 6.603773] r8152 2-1.3:1.0 eth0: carrier on
10791 23:43:46.199832 <5>[ 6.626086] Sending DHCP requests .., OK
10792 23:43:46.206322 <6>[ 8.806475] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.21
10793 23:43:46.209271 <6>[ 8.814768] IP-Config: Complete:
10794 23:43:46.222793 <6>[ 8.818268] device=eth0, hwaddr=00:24:32:30:78:ff, ipaddr=192.168.201.21, mask=255.255.255.0, gw=192.168.201.1
10795 23:43:46.229277 <6>[ 8.828977] host=mt8192-asurada-spherion-r0-cbg-8, domain=lava-rack, nis-domain=(none)
10796 23:43:46.236165 <6>[ 8.837595] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10797 23:43:46.242946 <6>[ 8.837605] nameserver0=192.168.201.1
10798 23:43:46.245883 <6>[ 8.849763] clk: Disabling unused clocks
10799 23:43:46.249279 <6>[ 8.855262] ALSA device list:
10800 23:43:46.255756 <6>[ 8.858540] No soundcards found.
10801 23:43:46.263818 <6>[ 8.866339] Freeing unused kernel memory: 8512K
10802 23:43:46.267353 <6>[ 8.871249] Run /init as init process
10803 23:43:46.297464 <6>[ 8.899817] NET: Registered PF_INET6 protocol family
10804 23:43:46.303838 <6>[ 8.906451] Segment Routing with IPv6
10805 23:43:46.307198 <6>[ 8.910392] In-situ OAM (IOAM) with IPv6
10806 23:43:46.352538 <30>[ 8.928807] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10807 23:43:46.359253 <30>[ 8.961849] systemd[1]: Detected architecture arm64.
10808 23:43:46.359377
10809 23:43:46.365733 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10810 23:43:46.365840
10811 23:43:46.379951 <30>[ 8.982463] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10812 23:43:46.546951 <30>[ 9.146333] systemd[1]: Queued start job for default target graphical.target.
10813 23:43:46.600818 <30>[ 9.199945] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10814 23:43:46.606967 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10815 23:43:46.627875 <30>[ 9.226873] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10816 23:43:46.637599 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10817 23:43:46.655857 <30>[ 9.255239] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10818 23:43:46.665694 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10819 23:43:46.684378 <30>[ 9.283698] systemd[1]: Created slice user.slice - User and Session Slice.
10820 23:43:46.691031 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10821 23:43:46.715197 <30>[ 9.311007] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10822 23:43:46.725030 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10823 23:43:46.742579 <30>[ 9.338444] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10824 23:43:46.748804 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10825 23:43:46.777224 <30>[ 9.366847] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10826 23:43:46.787510 <30>[ 9.386749] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10827 23:43:46.794054 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10828 23:43:46.811200 <30>[ 9.410694] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10829 23:43:46.821359 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10830 23:43:46.839320 <30>[ 9.438838] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10831 23:43:46.849637 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10832 23:43:46.864411 <30>[ 9.466840] systemd[1]: Reached target paths.target - Path Units.
10833 23:43:46.874084 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10834 23:43:46.891359 <30>[ 9.490779] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10835 23:43:46.898047 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10836 23:43:46.911737 <30>[ 9.514287] systemd[1]: Reached target slices.target - Slice Units.
10837 23:43:46.921862 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10838 23:43:46.936338 <30>[ 9.538807] systemd[1]: Reached target swap.target - Swaps.
10839 23:43:46.942440 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10840 23:43:46.963801 <30>[ 9.562826] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10841 23:43:46.973166 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10842 23:43:46.991681 <30>[ 9.591312] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10843 23:43:47.001716 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10844 23:43:47.021167 <30>[ 9.620278] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10845 23:43:47.030839 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10846 23:43:47.047766 <30>[ 9.646919] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10847 23:43:47.057401 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10848 23:43:47.075450 <30>[ 9.674886] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10849 23:43:47.082313 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10850 23:43:47.099437 <30>[ 9.698987] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10851 23:43:47.109202 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10852 23:43:47.127684 <30>[ 9.727018] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10853 23:43:47.137641 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10854 23:43:47.155353 <30>[ 9.754747] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10855 23:43:47.164881 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10856 23:43:47.230920 <30>[ 9.830534] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10857 23:43:47.237560 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10858 23:43:47.259411 <30>[ 9.858683] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10859 23:43:47.265696 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10860 23:43:47.311036 <30>[ 9.910415] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10861 23:43:47.317308 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10862 23:43:47.342161 <30>[ 9.934782] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10863 23:43:47.355709 <30>[ 9.955034] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10864 23:43:47.365535 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10865 23:43:47.387581 <30>[ 9.987073] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10866 23:43:47.394158 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10867 23:43:47.455251 <30>[ 10.054814] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10868 23:43:47.472054 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod..<6>[ 10.069454] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10869 23:43:47.472178 .
10870 23:43:47.496314 <30>[ 10.095699] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10871 23:43:47.502784 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10872 23:43:47.527391 <30>[ 10.126947] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10873 23:43:47.537106 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10874 23:43:47.557256 <30>[ 10.156846] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10875 23:43:47.564025 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10876 23:43:47.588655 <30>[ 10.187890] systemd[1]: Starting systemd-journald.service - Journal Service...
10877 23:43:47.594979 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10878 23:43:47.652056 <30>[ 10.251498] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10879 23:43:47.658444 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10880 23:43:47.687129 <30>[ 10.283526] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10881 23:43:47.694016 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10882 23:43:47.719967 <30>[ 10.319265] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10883 23:43:47.729866 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10884 23:43:47.767854 <30>[ 10.367266] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10885 23:43:47.774397 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10886 23:43:47.803130 <30>[ 10.402761] systemd[1]: Started systemd-journald.service - Journal Service.
10887 23:43:47.809621 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10888 23:43:47.829962 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10889 23:43:47.851123 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10890 23:43:47.871419 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10891 23:43:47.891813 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10892 23:43:47.917806 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10893 23:43:47.938059 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10894 23:43:47.958079 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10895 23:43:47.978262 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10896 23:43:48.002436 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10897 23:43:48.025034 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10898 23:43:48.048291 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10899 23:43:48.069607 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10900 23:43:48.087972 See 'systemctl status systemd-remount-fs.service' for details.
10901 23:43:48.098456 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10902 23:43:48.117668 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10903 23:43:48.159362 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10904 23:43:48.180178 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10905 23:43:48.197988 <46>[ 10.797436] systemd-journald[194]: Received client request to flush runtime journal.
10906 23:43:48.248073 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10907 23:43:48.276411 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10908 23:43:48.302025 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10909 23:43:48.333389 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10910 23:43:48.356452 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10911 23:43:48.380445 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10912 23:43:48.404041 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10913 23:43:48.424259 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10914 23:43:48.467403 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10915 23:43:48.499938 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10916 23:43:48.519396 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10917 23:43:48.534928 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10918 23:43:48.579774 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10919 23:43:48.599844 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10920 23:43:48.622613 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10921 23:43:48.673709 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10922 23:43:48.695601 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10923 23:43:48.717779 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10924 23:43:48.767256 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10925 23:43:48.789335 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10926 23:43:48.804855 <46>[ 11.407512] systemd-journald[194]: Time jumped backwards, rotating.
10927 23:43:48.815465 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10928 23:43:48.915363 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10929 23:43:48.931580 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10930 23:43:48.951599 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10931 23:43:48.973401 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10932 23:43:48.991023 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10933 23:43:49.008315 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10934 23:43:49.027374 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10935 23:43:49.039899 <3>[ 11.639454] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10936 23:43:49.046279 <3>[ 11.647593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10937 23:43:49.056378 <6>[ 11.654786] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10938 23:43:49.063438 <3>[ 11.655680] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10939 23:43:49.073032 <6>[ 11.663450] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10940 23:43:49.079904 <6>[ 11.680056] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10941 23:43:49.089867 <3>[ 11.689295] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10942 23:43:49.096662 <3>[ 11.697753] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10943 23:43:49.106240 <3>[ 11.705875] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10944 23:43:49.112864 <6>[ 11.708279] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10945 23:43:49.122788 <3>[ 11.713971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10946 23:43:49.129591 <3>[ 11.713979] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10947 23:43:49.135916 <3>[ 11.721781] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10948 23:43:49.142583 <6>[ 11.742342] remoteproc remoteproc0: scp is available
10949 23:43:49.149574 <6>[ 11.750998] remoteproc remoteproc0: powering up scp
10950 23:43:49.155967 <6>[ 11.756138] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10951 23:43:49.162585 <6>[ 11.764590] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10952 23:43:49.172361 Startin<3>[ 11.770435] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10953 23:43:49.179199 <3>[ 11.779823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10954 23:43:49.188925 g [0;1;39msyste<3>[ 11.787921] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10955 23:43:49.198791 md-networkd.…ice[0m - Network<6>[ 11.799240] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10956 23:43:49.208729 Configuration..<4>[ 11.799522] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10957 23:43:49.208858 .
10958 23:43:49.227302 <6>[ 11.827305] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10959 23:43:49.230760 <6>[ 11.834461] pci_bus 0000:00: root bus resource [bus 00-ff]
10960 23:43:49.240823 <6>[ 11.840233] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10961 23:43:49.250992 <6>[ 11.847660] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10962 23:43:49.257213 <4>[ 11.852481] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10963 23:43:49.263809 <4>[ 11.852481] Fallback method does not support PEC.
10964 23:43:49.270801 <6>[ 11.857829] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10965 23:43:49.280477 <6>[ 11.866825] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10966 23:43:49.283439 <6>[ 11.877732] mc: Linux media interface: v0.10
10967 23:43:49.290941 <6>[ 11.887604] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10968 23:43:49.300951 <3>[ 11.893180] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10969 23:43:49.307417 <4>[ 11.893230] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10970 23:43:49.314431 <6>[ 11.895939] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10971 23:43:49.324429 <6>[ 11.895992] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10972 23:43:49.328438 <6>[ 11.896001] remoteproc remoteproc0: remote processor scp is now up
10973 23:43:49.338067 <3>[ 11.900272] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 23:43:49.341382 <6>[ 11.908040] pci 0000:00:00.0: supports D1 D2
10975 23:43:49.351130 <3>[ 11.935886] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10976 23:43:49.357965 <3>[ 11.937061] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10977 23:43:49.364689 <6>[ 11.946369] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10978 23:43:49.374658 <3>[ 11.950388] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10979 23:43:49.380973 <3>[ 11.982153] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10980 23:43:49.390937 <3>[ 11.982163] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10981 23:43:49.403953 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - B<6>[ 12.004007] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10982 23:43:49.407299 asic System.
10983 23:43:49.417265 <6>[ 12.016401] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10984 23:43:49.427324 <3>[ 12.026433] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10985 23:43:49.437791 <6>[ 12.037242] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10986 23:43:49.446354 <6>[ 12.048993] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10987 23:43:49.455991 <6>[ 12.055308] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10988 23:43:49.462805 <6>[ 12.062799] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10989 23:43:49.469612 <6>[ 12.070284] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10990 23:43:49.475796 <6>[ 12.077870] pci 0000:01:00.0: supports D1 D2
10991 23:43:49.482649 <6>[ 12.082393] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10992 23:43:49.490530 <6>[ 12.093283] videodev: Linux video capture interface: v2.00
10993 23:43:49.527701 Starting [0;1;39mdbus.<5>[ 12.126465] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10994 23:43:49.531370 service[0m - D-Bus System Message Bus...
10995 23:43:49.557589 <5>[ 12.157410] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10996 23:43:49.564312 <5>[ 12.164833] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10997 23:43:49.573967 <4>[ 12.173258] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10998 23:43:49.580981 <6>[ 12.182159] cfg80211: failed to load regulatory.db
10999 23:43:49.616009 <6>[ 12.218782] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11000 23:43:49.626318 <6>[ 12.225883] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11001 23:43:49.632771 <6>[ 12.234527] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11002 23:43:49.647330 Starting [0;1;39msystemd-logind.se…i<6>[ 12.246288] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11003 23:43:49.657113 ce[0m - User Lo<6>[ 12.255513] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11004 23:43:49.663717 gin Management..<6>[ 12.255907] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11005 23:43:49.673422 <6>[ 12.264589] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11006 23:43:49.673592 .
11007 23:43:49.680227 <6>[ 12.281644] pci 0000:00:00.0: PCI bridge to [bus 01]
11008 23:43:49.690022 <6>[ 12.284373] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11009 23:43:49.700125 <6>[ 12.287035] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11010 23:43:49.706800 <6>[ 12.300427] usbcore: registered new interface driver uvcvideo
11011 23:43:49.710389 <6>[ 12.300539] Bluetooth: Core ver 2.22
11012 23:43:49.713269 <6>[ 12.300678] NET: Registered PF_BLUETOOTH protocol family
11013 23:43:49.719500 <6>[ 12.300680] Bluetooth: HCI device and connection manager initialized
11014 23:43:49.726492 <6>[ 12.300704] Bluetooth: HCI socket layer initialized
11015 23:43:49.732828 <6>[ 12.300711] Bluetooth: L2CAP socket layer initialized
11016 23:43:49.736367 <6>[ 12.300726] Bluetooth: SCO socket layer initialized
11017 23:43:49.743172 <6>[ 12.308052] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11018 23:43:49.753381 <6>[ 12.308880] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11019 23:43:49.756833 <6>[ 12.309699] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11020 23:43:49.767817 <6>[ 12.312807] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11021 23:43:49.770893 <6>[ 12.330700] usbcore: registered new interface driver btusb
11022 23:43:49.783996 <4>[ 12.331471] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11023 23:43:49.788002 <3>[ 12.331479] Bluetooth: hci0: Failed to load firmware file (-2)
11024 23:43:49.794671 <3>[ 12.331482] Bluetooth: hci0: Failed to set up firmware (-2)
11025 23:43:49.804871 <4>[ 12.331485] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11026 23:43:49.811231 <6>[ 12.335320] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11027 23:43:49.820953 <3>[ 12.335482] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11028 23:43:49.827960 <3>[ 12.371438] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11029 23:43:49.837501 <3>[ 12.372266] power_supply sbs-5-000b: driver failed to report `voltage_now' property: -6
11030 23:43:49.844334 <6>[ 12.375052] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11031 23:43:49.850749 <3>[ 12.380076] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11032 23:43:49.860863 <3>[ 12.400680] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11033 23:43:49.867635 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11034 23:43:49.892925 <3>[ 12.492282] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11035 23:43:49.903133 <6>[ 12.502714] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11036 23:43:49.909748 <6>[ 12.510248] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11037 23:43:49.916196 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11038 23:43:49.926621 <3>[ 12.526116] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11039 23:43:49.934034 <6>[ 12.536932] mt7921e 0000:01:00.0: ASIC revision: 79610010
11040 23:43:49.961501 <3>[ 12.561079] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11041 23:43:49.971143 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11042 23:43:49.992681 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11043 23:43:50.014723 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11044 23:43:50.038677 [[0;32m OK [0m] Reached target [0;1;39mnetw<6>[ 12.637741] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11045 23:43:50.041621 <6>[ 12.637741]
11046 23:43:50.044863 ork.target[0m - Network.
11047 23:43:50.063718 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11048 23:43:50.128704 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11049 23:43:50.152797 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11050 23:43:50.176751 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11051 23:43:50.197543 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11052 23:43:50.256798 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11053 23:43:50.281908 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11054 23:43:50.300157 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11055 23:43:50.306603 <6>[ 12.907254] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11056 23:43:50.317489 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11057 23:43:50.335633 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11058 23:43:50.388547 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11059 23:43:50.413945 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11060 23:43:50.435849 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11061 23:43:50.476636 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11062 23:43:50.528522
11063 23:43:50.531769 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11064 23:43:50.531857
11065 23:43:50.535206 debian-bookworm-arm64 login: root (automatic login)
11066 23:43:50.535295
11067 23:43:50.549211 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024 aarch64
11068 23:43:50.549353
11069 23:43:50.555722 The programs included with the Debian GNU/Linux system are free software;
11070 23:43:50.562861 the exact distribution terms for each program are described in the
11071 23:43:50.565576 individual files in /usr/share/doc/*/copyright.
11072 23:43:50.565663
11073 23:43:50.572115 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11074 23:43:50.575670 permitted by applicable law.
11075 23:43:50.576224 Matched prompt #10: / #
11077 23:43:50.576589 Setting prompt string to ['/ #']
11078 23:43:50.576744 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11080 23:43:50.577101 end: 2.2.5 auto-login-action (duration 00:00:14) [common]
11081 23:43:50.577249 start: 2.2.6 expect-shell-connection (timeout 00:02:54) [common]
11082 23:43:50.577374 Setting prompt string to ['/ #']
11083 23:43:50.577488 Forcing a shell prompt, looking for ['/ #']
11085 23:43:50.627781 / #
11086 23:43:50.627901 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11087 23:43:50.627980 Waiting using forced prompt support (timeout 00:02:30)
11088 23:43:50.632765
11089 23:43:50.633039 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11090 23:43:50.633139 start: 2.2.7 export-device-env (timeout 00:02:54) [common]
11091 23:43:50.633234 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11092 23:43:50.633320 end: 2.2 depthcharge-retry (duration 00:02:06) [common]
11093 23:43:50.633406 end: 2 depthcharge-action (duration 00:02:06) [common]
11094 23:43:50.633491 start: 3 lava-test-retry (timeout 00:05:00) [common]
11095 23:43:50.633579 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
11096 23:43:50.633652 Using namespace: common
11098 23:43:50.733949 / # #
11099 23:43:50.734173 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
11100 23:43:50.739184 #
11101 23:43:50.739510 Using /lava-14172912
11103 23:43:50.839824 / # export SHELL=/bin/sh
11104 23:43:50.844666 export SHELL=/bin/sh
11106 23:43:50.945239 / # . /lava-14172912/environment
11107 23:43:50.950819 . /lava-14172912/environment
11109 23:43:51.051327 / # /lava-14172912/bin/lava-test-runner /lava-14172912/0
11110 23:43:51.051493 Test shell timeout: 10s (minimum of the action and connection timeout)
11111 23:43:51.056827 /lava-14172912/bin/lava-test-runner /lava-14172912/0
11112 23:43:51.077640 + export TESTRUN_ID=0_cros-ec
11113 23:43:51.084571 +<8>[ 13.686400] <LAVA_SIGNAL_STARTRUN 0_cros-ec 14172912_1.5.2.3.1>
11114 23:43:51.084858 Received signal: <STARTRUN> 0_cros-ec 14172912_1.5.2.3.1
11115 23:43:51.084934 Starting test lava.0_cros-ec (14172912_1.5.2.3.1)
11116 23:43:51.085019 Skipping test definition patterns.
11117 23:43:51.087829 cd /lava-14172912/0/tests/0_cros-ec
11118 23:43:51.091202 + cat uuid
11119 23:43:51.091291 + UUID=14172912_1.5.2.3.1
11120 23:43:51.091361 + set +x
11121 23:43:51.097707 + python3 -m cros.runners.lava_runner -v
11122 23:43:51.171433 <6>[ 13.774704] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11123 23:43:51.566100 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_abi)
11124 23:43:51.572964 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
11125 23:43:51.573165
11126 23:43:51.579642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
11127 23:43:51.580008 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
11129 23:43:51.589136 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel.test_cros_ec_accel_iio_data_is_valid)
11130 23:43:51.599147 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
11131 23:43:51.599291
11132 23:43:51.605933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip>
11133 23:43:51.606258 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_valid RESULT=skip
11135 23:43:51.615704 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro.test_cros_ec_gyro_iio_abi)
11136 23:43:51.621972 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
11137 23:43:51.622091
11138 23:43:51.628767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
11139 23:43:51.629046 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
11141 23:43:51.635556 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_abi)
11142 23:43:51.641996 Checks the standard ABI for the main Embedded Controller. ... ok
11143 23:43:51.642110
11144 23:43:51.645631 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
11145 23:43:51.645928 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
11147 23:43:51.652174 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_chardev)
11148 23:43:51.658477 Checks the main Embedded controller character device. ... ok
11149 23:43:51.658672
11150 23:43:51.665180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
11151 23:43:51.665486 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
11153 23:43:51.671763 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_ec_hello)
11154 23:43:51.678486 Checks basic comunication with the main Embedded controller. ... ok
11155 23:43:51.678572
11156 23:43:51.685352 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
11157 23:43:51.685617 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
11159 23:43:51.691586 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_abi)
11160 23:43:51.697996 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
11161 23:43:51.698083
11162 23:43:51.705003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
11163 23:43:51.705260 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11165 23:43:51.711355 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_hello)
11166 23:43:51.717787 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11167 23:43:51.717903
11168 23:43:51.724820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11169 23:43:51.725102 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11171 23:43:51.731368 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_fp_reboot)
11172 23:43:51.738041 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11173 23:43:51.738125
11174 23:43:51.744458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11175 23:43:51.744713 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11177 23:43:51.750882 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_abi)
11178 23:43:51.761330 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11179 23:43:51.761418
11180 23:43:51.764028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11181 23:43:51.764309 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11183 23:43:51.770623 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_pd_hello)
11184 23:43:51.780684 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11185 23:43:51.780821
11186 23:43:51.787586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11187 23:43:51.787919 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11189 23:43:51.794115 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_abi)
11190 23:43:51.800473 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11191 23:43:51.800622
11192 23:43:51.807498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11193 23:43:51.807758 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11195 23:43:51.813833 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU.test_cros_tp_hello)
11196 23:43:51.820293 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11197 23:43:51.820371
11198 23:43:51.826926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11199 23:43:51.827180 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11201 23:43:51.837417 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM.test_cros_ec_pwm_backlight)
11202 23:43:51.843667 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11203 23:43:51.843784
11204 23:43:51.850345 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11205 23:43:51.850645 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11207 23:43:51.860167 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_battery_abi)
11208 23:43:51.863157 Check the cros battery ABI. ... skipped 'No BAT found'
11209 23:43:51.863273
11210 23:43:51.870173 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11211 23:43:51.870424 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11213 23:43:51.880111 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower.test_cros_ec_usbpd_charger_abi)
11214 23:43:51.886425 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11215 23:43:51.886510
11216 23:43:51.893279 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11217 23:43:51.893550 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11219 23:43:51.899534 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC.test_cros_ec_rtc_abi)
11220 23:43:51.906408 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11221 23:43:51.910002
11222 23:43:51.912880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11223 23:43:51.913145 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11225 23:43:51.922737 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon.test_cros_ec_extcon_usbc_abi)
11226 23:43:51.929834 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11227 23:43:51.929968
11228 23:43:51.936184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11229 23:43:51.936283
11230 23:43:51.936524 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11232 23:43:51.946070 --------------------------<8>[ 14.546758] <LAVA_SIGNAL_ENDRUN 0_cros-ec 14172912_1.5.2.3.1>
11233 23:43:51.946367 Received signal: <ENDRUN> 0_cros-ec 14172912_1.5.2.3.1
11234 23:43:51.946485 Ending use of test pattern.
11235 23:43:51.946577 Ending test lava.0_cros-ec (14172912_1.5.2.3.1), duration 0.86
11237 23:43:51.949407 --------------------------------------------
11238 23:43:51.949494 Ran 18 tests in 0.338s
11239 23:43:51.952601
11240 23:43:51.952725 OK (skipped=15)
11241 23:43:51.952839 + set +x
11242 23:43:51.955710 <LAVA_TEST_RUNNER EXIT>
11243 23:43:51.956014 ok: lava_test_shell seems to have completed
11244 23:43:51.956353 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_accel_iio_data_is_valid: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11245 23:43:51.956522 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11246 23:43:51.956668 end: 3 lava-test-retry (duration 00:00:01) [common]
11247 23:43:51.956821 start: 4 finalize (timeout 00:07:28) [common]
11248 23:43:51.957021 start: 4.1 power-off (timeout 00:00:30) [common]
11249 23:43:51.957311 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-8', '--port=1', '--command=off']
11250 23:43:52.036925 >> Command sent successfully.
11251 23:43:52.039865 Returned 0 in 0 seconds
11252 23:43:52.140245 end: 4.1 power-off (duration 00:00:00) [common]
11254 23:43:52.140583 start: 4.2 read-feedback (timeout 00:07:28) [common]
11255 23:43:52.140850 Listened to connection for namespace 'common' for up to 1s
11256 23:43:53.141779 Finalising connection for namespace 'common'
11257 23:43:53.141991 Disconnecting from shell: Finalise
11258 23:43:53.142108 / #
11259 23:43:53.242451 end: 4.2 read-feedback (duration 00:00:01) [common]
11260 23:43:53.242668 end: 4 finalize (duration 00:00:01) [common]
11261 23:43:53.242816 Cleaning after the job
11262 23:43:53.242956 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/ramdisk
11263 23:43:53.248857 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/kernel
11264 23:43:53.263635 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/dtb
11265 23:43:53.263872 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172912/tftp-deploy-1lu6qxlv/modules
11266 23:43:53.269500 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14172912
11267 23:43:53.365905 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14172912
11268 23:43:53.366087 Job finished correctly