Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 23:46:39.015030 lava-dispatcher, installed at version: 2024.03
2 23:46:39.015232 start: 0 validate
3 23:46:39.015369 Start time: 2024-06-04 23:46:39.015361+00:00 (UTC)
4 23:46:39.015514 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:46:39.015643 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:46:39.278845 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:46:39.279562 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:46:39.534964 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:46:39.535720 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:46:39.799689 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:46:39.800398 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:46:40.059781 validate duration: 1.04
14 23:46:40.061099 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:46:40.061708 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:46:40.062308 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:46:40.062901 Not decompressing ramdisk as can be used compressed.
18 23:46:40.063322 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 23:46:40.063646 saving as /var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/ramdisk/rootfs.cpio.gz
20 23:46:40.063963 total size: 47897469 (45 MB)
21 23:46:40.068764 progress 0 % (0 MB)
22 23:46:40.107731 progress 5 % (2 MB)
23 23:46:40.123793 progress 10 % (4 MB)
24 23:46:40.136191 progress 15 % (6 MB)
25 23:46:40.148263 progress 20 % (9 MB)
26 23:46:40.160273 progress 25 % (11 MB)
27 23:46:40.172357 progress 30 % (13 MB)
28 23:46:40.184452 progress 35 % (16 MB)
29 23:46:40.196575 progress 40 % (18 MB)
30 23:46:40.208950 progress 45 % (20 MB)
31 23:46:40.221250 progress 50 % (22 MB)
32 23:46:40.233600 progress 55 % (25 MB)
33 23:46:40.245967 progress 60 % (27 MB)
34 23:46:40.258019 progress 65 % (29 MB)
35 23:46:40.270104 progress 70 % (32 MB)
36 23:46:40.282127 progress 75 % (34 MB)
37 23:46:40.294194 progress 80 % (36 MB)
38 23:46:40.306303 progress 85 % (38 MB)
39 23:46:40.318380 progress 90 % (41 MB)
40 23:46:40.330328 progress 95 % (43 MB)
41 23:46:40.342213 progress 100 % (45 MB)
42 23:46:40.342426 45 MB downloaded in 0.28 s (164.03 MB/s)
43 23:46:40.342588 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:46:40.342829 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:46:40.342914 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:46:40.342997 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:46:40.343118 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:46:40.343185 saving as /var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/kernel/Image
50 23:46:40.343250 total size: 54682112 (52 MB)
51 23:46:40.343311 No compression specified
52 23:46:40.344398 progress 0 % (0 MB)
53 23:46:40.358007 progress 5 % (2 MB)
54 23:46:40.371592 progress 10 % (5 MB)
55 23:46:40.385261 progress 15 % (7 MB)
56 23:46:40.398925 progress 20 % (10 MB)
57 23:46:40.413068 progress 25 % (13 MB)
58 23:46:40.426848 progress 30 % (15 MB)
59 23:46:40.440770 progress 35 % (18 MB)
60 23:46:40.454644 progress 40 % (20 MB)
61 23:46:40.468532 progress 45 % (23 MB)
62 23:46:40.482384 progress 50 % (26 MB)
63 23:46:40.496047 progress 55 % (28 MB)
64 23:46:40.510020 progress 60 % (31 MB)
65 23:46:40.523773 progress 65 % (33 MB)
66 23:46:40.537702 progress 70 % (36 MB)
67 23:46:40.551726 progress 75 % (39 MB)
68 23:46:40.565913 progress 80 % (41 MB)
69 23:46:40.579536 progress 85 % (44 MB)
70 23:46:40.593195 progress 90 % (46 MB)
71 23:46:40.606990 progress 95 % (49 MB)
72 23:46:40.620519 progress 100 % (52 MB)
73 23:46:40.620755 52 MB downloaded in 0.28 s (187.92 MB/s)
74 23:46:40.620907 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:46:40.621181 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:46:40.621266 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:46:40.621349 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:46:40.621484 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:46:40.621552 saving as /var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/dtb/mt8192-asurada-spherion-r0.dtb
81 23:46:40.621612 total size: 47258 (0 MB)
82 23:46:40.621671 No compression specified
83 23:46:40.622773 progress 69 % (0 MB)
84 23:46:40.623045 progress 100 % (0 MB)
85 23:46:40.623199 0 MB downloaded in 0.00 s (28.44 MB/s)
86 23:46:40.623320 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:46:40.623538 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:46:40.623621 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:46:40.623703 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:46:40.623811 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:46:40.623878 saving as /var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/modules/modules.tar
93 23:46:40.623938 total size: 8603924 (8 MB)
94 23:46:40.623999 Using unxz to decompress xz
95 23:46:40.628039 progress 0 % (0 MB)
96 23:46:40.648633 progress 5 % (0 MB)
97 23:46:40.673727 progress 10 % (0 MB)
98 23:46:40.698850 progress 15 % (1 MB)
99 23:46:40.723263 progress 20 % (1 MB)
100 23:46:40.748458 progress 25 % (2 MB)
101 23:46:40.773226 progress 30 % (2 MB)
102 23:46:40.797634 progress 35 % (2 MB)
103 23:46:40.824540 progress 40 % (3 MB)
104 23:46:40.849413 progress 45 % (3 MB)
105 23:46:40.873258 progress 50 % (4 MB)
106 23:46:40.897889 progress 55 % (4 MB)
107 23:46:40.921876 progress 60 % (4 MB)
108 23:46:40.945339 progress 65 % (5 MB)
109 23:46:40.971311 progress 70 % (5 MB)
110 23:46:40.996297 progress 75 % (6 MB)
111 23:46:41.021363 progress 80 % (6 MB)
112 23:46:41.044666 progress 85 % (7 MB)
113 23:46:41.068094 progress 90 % (7 MB)
114 23:46:41.096847 progress 95 % (7 MB)
115 23:46:41.124441 progress 100 % (8 MB)
116 23:46:41.129962 8 MB downloaded in 0.51 s (16.22 MB/s)
117 23:46:41.130211 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:46:41.130499 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:46:41.130605 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:46:41.130714 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:46:41.130808 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:46:41.130925 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:46:41.131172 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo
125 23:46:41.131346 makedir: /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin
126 23:46:41.131490 makedir: /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/tests
127 23:46:41.131627 makedir: /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/results
128 23:46:41.131754 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-add-keys
129 23:46:41.131914 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-add-sources
130 23:46:41.132062 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-background-process-start
131 23:46:41.132236 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-background-process-stop
132 23:46:41.132404 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-common-functions
133 23:46:41.132567 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-echo-ipv4
134 23:46:41.132712 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-install-packages
135 23:46:41.132853 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-installed-packages
136 23:46:41.133021 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-os-build
137 23:46:41.133202 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-probe-channel
138 23:46:41.133370 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-probe-ip
139 23:46:41.133539 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-target-ip
140 23:46:41.133681 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-target-mac
141 23:46:41.133844 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-target-storage
142 23:46:41.133988 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-test-case
143 23:46:41.134130 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-test-event
144 23:46:41.134293 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-test-feedback
145 23:46:41.134432 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-test-raise
146 23:46:41.134573 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-test-reference
147 23:46:41.134738 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-test-runner
148 23:46:41.134914 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-test-set
149 23:46:41.135079 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-test-shell
150 23:46:41.135221 Updating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-install-packages (oe)
151 23:46:41.135386 Updating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/bin/lava-installed-packages (oe)
152 23:46:41.135522 Creating /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/environment
153 23:46:41.135633 LAVA metadata
154 23:46:41.135715 - LAVA_JOB_ID=14172991
155 23:46:41.135791 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:46:41.135935 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:46:41.136043 skipped lava-vland-overlay
158 23:46:41.136158 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:46:41.136282 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:46:41.136385 skipped lava-multinode-overlay
161 23:46:41.136510 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:46:41.136642 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:46:41.136752 Loading test definitions
164 23:46:41.136886 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:46:41.137038 Using /lava-14172991 at stage 0
166 23:46:41.137470 uuid=14172991_1.5.2.3.1 testdef=None
167 23:46:41.137592 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:46:41.137724 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:46:41.138444 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:46:41.138718 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:46:41.139343 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:46:41.139596 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:46:41.140435 runner path: /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/0/tests/0_igt-gpu-panfrost test_uuid 14172991_1.5.2.3.1
176 23:46:41.140630 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:46:41.140854 Creating lava-test-runner.conf files
179 23:46:41.140953 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14172991/lava-overlay-i0j_cgfo/lava-14172991/0 for stage 0
180 23:46:41.141091 - 0_igt-gpu-panfrost
181 23:46:41.141227 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:46:41.141350 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:46:41.150112 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:46:41.150249 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:46:41.150351 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:46:41.150452 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:46:41.150548 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:46:42.884630 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 23:46:42.885009 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 23:46:42.885193 extracting modules file /var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172991/extract-overlay-ramdisk-z352j_fk/ramdisk
191 23:46:43.107182 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:46:43.107347 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 23:46:43.107465 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172991/compress-overlay-hxy7aixz/overlay-1.5.2.4.tar.gz to ramdisk
194 23:46:43.107568 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172991/compress-overlay-hxy7aixz/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14172991/extract-overlay-ramdisk-z352j_fk/ramdisk
195 23:46:43.114806 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:46:43.114936 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 23:46:43.115063 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:46:43.115191 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 23:46:43.115309 Building ramdisk /var/lib/lava/dispatcher/tmp/14172991/extract-overlay-ramdisk-z352j_fk/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14172991/extract-overlay-ramdisk-z352j_fk/ramdisk
200 23:46:44.306353 >> 465920 blocks
201 23:46:50.454999 rename /var/lib/lava/dispatcher/tmp/14172991/extract-overlay-ramdisk-z352j_fk/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/ramdisk/ramdisk.cpio.gz
202 23:46:50.455497 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 23:46:50.455659 start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
204 23:46:50.455808 start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
205 23:46:50.455963 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/kernel/Image']
206 23:47:03.501769 Returned 0 in 13 seconds
207 23:47:03.602440 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/kernel/image.itb
208 23:47:04.456771 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:47:04.457214 output: Created: Wed Jun 5 00:47:04 2024
210 23:47:04.457320 output: Image 0 (kernel-1)
211 23:47:04.457422 output: Description:
212 23:47:04.457488 output: Created: Wed Jun 5 00:47:04 2024
213 23:47:04.457551 output: Type: Kernel Image
214 23:47:04.457642 output: Compression: lzma compressed
215 23:47:04.457703 output: Data Size: 13061430 Bytes = 12755.30 KiB = 12.46 MiB
216 23:47:04.457779 output: Architecture: AArch64
217 23:47:04.457870 output: OS: Linux
218 23:47:04.457965 output: Load Address: 0x00000000
219 23:47:04.458060 output: Entry Point: 0x00000000
220 23:47:04.458156 output: Hash algo: crc32
221 23:47:04.458247 output: Hash value: ecfb5096
222 23:47:04.458336 output: Image 1 (fdt-1)
223 23:47:04.458431 output: Description: mt8192-asurada-spherion-r0
224 23:47:04.458519 output: Created: Wed Jun 5 00:47:04 2024
225 23:47:04.458612 output: Type: Flat Device Tree
226 23:47:04.458694 output: Compression: uncompressed
227 23:47:04.458789 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 23:47:04.458871 output: Architecture: AArch64
229 23:47:04.458968 output: Hash algo: crc32
230 23:47:04.459049 output: Hash value: 0f8e4d2e
231 23:47:04.459145 output: Image 2 (ramdisk-1)
232 23:47:04.459228 output: Description: unavailable
233 23:47:04.459319 output: Created: Wed Jun 5 00:47:04 2024
234 23:47:04.459405 output: Type: RAMDisk Image
235 23:47:04.459490 output: Compression: Unknown Compression
236 23:47:04.459579 output: Data Size: 61005769 Bytes = 59575.95 KiB = 58.18 MiB
237 23:47:04.459660 output: Architecture: AArch64
238 23:47:04.459743 output: OS: Linux
239 23:47:04.459796 output: Load Address: unavailable
240 23:47:04.459855 output: Entry Point: unavailable
241 23:47:04.459945 output: Hash algo: crc32
242 23:47:04.460026 output: Hash value: 9807b97a
243 23:47:04.460122 output: Default Configuration: 'conf-1'
244 23:47:04.460203 output: Configuration 0 (conf-1)
245 23:47:04.460298 output: Description: mt8192-asurada-spherion-r0
246 23:47:04.460380 output: Kernel: kernel-1
247 23:47:04.460470 output: Init Ramdisk: ramdisk-1
248 23:47:04.460554 output: FDT: fdt-1
249 23:47:04.460641 output: Loadables: kernel-1
250 23:47:04.460734 output:
251 23:47:04.461014 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 23:47:04.461152 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 23:47:04.461306 end: 1.5 prepare-tftp-overlay (duration 00:00:23) [common]
254 23:47:04.461439 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:36) [common]
255 23:47:04.461547 No LXC device requested
256 23:47:04.461675 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:47:04.461793 start: 1.7 deploy-device-env (timeout 00:09:36) [common]
258 23:47:04.461911 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:47:04.462021 Checking files for TFTP limit of 4294967296 bytes.
260 23:47:04.462676 end: 1 tftp-deploy (duration 00:00:24) [common]
261 23:47:04.462827 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:47:04.462928 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:47:04.463085 substitutions:
264 23:47:04.463174 - {DTB}: 14172991/tftp-deploy-8tg3m569/dtb/mt8192-asurada-spherion-r0.dtb
265 23:47:04.463271 - {INITRD}: 14172991/tftp-deploy-8tg3m569/ramdisk/ramdisk.cpio.gz
266 23:47:04.463373 - {KERNEL}: 14172991/tftp-deploy-8tg3m569/kernel/Image
267 23:47:04.463462 - {LAVA_MAC}: None
268 23:47:04.463562 - {PRESEED_CONFIG}: None
269 23:47:04.463621 - {PRESEED_LOCAL}: None
270 23:47:04.463677 - {RAMDISK}: 14172991/tftp-deploy-8tg3m569/ramdisk/ramdisk.cpio.gz
271 23:47:04.463768 - {ROOT_PART}: None
272 23:47:04.463824 - {ROOT}: None
273 23:47:04.463878 - {SERVER_IP}: 192.168.201.1
274 23:47:04.463963 - {TEE}: None
275 23:47:04.464019 Parsed boot commands:
276 23:47:04.464072 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:47:04.464313 Parsed boot commands: tftpboot 192.168.201.1 14172991/tftp-deploy-8tg3m569/kernel/image.itb 14172991/tftp-deploy-8tg3m569/kernel/cmdline
278 23:47:04.464406 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:47:04.464507 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:47:04.464638 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:47:04.464772 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:47:04.464877 Not connected, no need to disconnect.
283 23:47:04.464993 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:47:04.465101 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:47:04.465174 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
286 23:47:04.468898 Setting prompt string to ['lava-test: # ']
287 23:47:04.469350 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:47:04.469471 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:47:04.469587 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:47:04.469701 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:47:04.470008 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=reboot']
292 23:47:09.619482 >> Command sent successfully.
293 23:47:09.631436 Returned 0 in 5 seconds
294 23:47:09.732672 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:47:09.734045 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:47:09.734508 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:47:09.735065 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:47:09.735439 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:47:09.735893 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:47:09.737761 [Enter `^Ec?' for help]
302 23:47:09.908187
303 23:47:09.908788
304 23:47:09.909189 F0: 102B 0000
305 23:47:09.909521
306 23:47:09.909847 F3: 1001 0000 [0200]
307 23:47:09.912205
308 23:47:09.912659 F3: 1001 0000
309 23:47:09.913029
310 23:47:09.913396 F7: 102D 0000
311 23:47:09.913704
312 23:47:09.913997 F1: 0000 0000
313 23:47:09.915344
314 23:47:09.915892 V0: 0000 0000 [0001]
315 23:47:09.916384
316 23:47:09.916737 00: 0007 8000
317 23:47:09.917106
318 23:47:09.919626 01: 0000 0000
319 23:47:09.920071
320 23:47:09.920443 BP: 0C00 0209 [0000]
321 23:47:09.920809
322 23:47:09.922889 G0: 1182 0000
323 23:47:09.923437
324 23:47:09.923937 EC: 0000 0021 [4000]
325 23:47:09.924394
326 23:47:09.927116 S7: 0000 0000 [0000]
327 23:47:09.927555
328 23:47:09.927898 CC: 0000 0000 [0001]
329 23:47:09.928259
330 23:47:09.930609 T0: 0000 0040 [010F]
331 23:47:09.931024
332 23:47:09.931504 Jump to BL
333 23:47:09.932057
334 23:47:09.955720
335 23:47:09.956230
336 23:47:09.962999 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 23:47:09.966724 ARM64: Exception handlers installed.
338 23:47:09.970122 ARM64: Testing exception
339 23:47:09.974204 ARM64: Done test exception
340 23:47:09.981363 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 23:47:09.988856 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 23:47:09.998492 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 23:47:10.005552 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 23:47:10.015567 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 23:47:10.022335 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 23:47:10.032846 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 23:47:10.039629 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 23:47:10.058476 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 23:47:10.061448 WDT: Last reset was cold boot
350 23:47:10.065127 SPI1(PAD0) initialized at 2873684 Hz
351 23:47:10.068259 SPI5(PAD0) initialized at 992727 Hz
352 23:47:10.071652 VBOOT: Loading verstage.
353 23:47:10.078520 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 23:47:10.081677 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 23:47:10.085300 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 23:47:10.088185 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 23:47:10.095602 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 23:47:10.102369 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 23:47:10.113265 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 23:47:10.113712
361 23:47:10.114150
362 23:47:10.123178 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 23:47:10.126774 ARM64: Exception handlers installed.
364 23:47:10.130086 ARM64: Testing exception
365 23:47:10.130573 ARM64: Done test exception
366 23:47:10.136428 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 23:47:10.140549 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 23:47:10.154488 Probing TPM: . done!
369 23:47:10.155077 TPM ready after 0 ms
370 23:47:10.161461 Connected to device vid:did:rid of 1ae0:0028:00
371 23:47:10.168418 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 23:47:10.227173 Initialized TPM device CR50 revision 0
373 23:47:10.238180 tlcl_send_startup: Startup return code is 0
374 23:47:10.238616 TPM: setup succeeded
375 23:47:10.250245 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 23:47:10.259228 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 23:47:10.270704 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 23:47:10.280142 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 23:47:10.283376 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 23:47:10.290717 in-header: 03 07 00 00 08 00 00 00
381 23:47:10.293832 in-data: aa e4 47 04 13 02 00 00
382 23:47:10.297510 Chrome EC: UHEPI supported
383 23:47:10.304725 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 23:47:10.308642 in-header: 03 ad 00 00 08 00 00 00
385 23:47:10.312475 in-data: 00 20 20 08 00 00 00 00
386 23:47:10.312893 Phase 1
387 23:47:10.316128 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 23:47:10.323366 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 23:47:10.326767 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 23:47:10.331390 Recovery requested (1009000e)
391 23:47:10.339254 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 23:47:10.344270 tlcl_extend: response is 0
393 23:47:10.353656 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 23:47:10.359689 tlcl_extend: response is 0
395 23:47:10.366664 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 23:47:10.386049 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 23:47:10.393136 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 23:47:10.393568
399 23:47:10.393907
400 23:47:10.403833 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 23:47:10.407281 ARM64: Exception handlers installed.
402 23:47:10.407800 ARM64: Testing exception
403 23:47:10.410624 ARM64: Done test exception
404 23:47:10.432133 pmic_efuse_setting: Set efuses in 11 msecs
405 23:47:10.435736 pmwrap_interface_init: Select PMIF_VLD_RDY
406 23:47:10.442891 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 23:47:10.445598 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 23:47:10.449110 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 23:47:10.457288 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 23:47:10.460557 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 23:47:10.464466 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 23:47:10.471669 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 23:47:10.475412 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 23:47:10.479213 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 23:47:10.482380 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 23:47:10.489665 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 23:47:10.493500 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 23:47:10.497700 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 23:47:10.504849 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 23:47:10.508524 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 23:47:10.516174 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 23:47:10.519484 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 23:47:10.527638 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 23:47:10.530825 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 23:47:10.538703 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 23:47:10.542402 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 23:47:10.549875 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 23:47:10.553115 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 23:47:10.560929 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 23:47:10.565188 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 23:47:10.572575 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 23:47:10.575611 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 23:47:10.579266 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 23:47:10.586951 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 23:47:10.590591 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 23:47:10.594291 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 23:47:10.601239 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 23:47:10.604809 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 23:47:10.612741 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 23:47:10.616167 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 23:47:10.619540 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 23:47:10.626722 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 23:47:10.630295 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 23:47:10.634394 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 23:47:10.641205 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 23:47:10.645600 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 23:47:10.648489 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 23:47:10.652592 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 23:47:10.656563 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 23:47:10.660556 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 23:47:10.668081 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 23:47:10.671242 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 23:47:10.675309 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 23:47:10.678744 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 23:47:10.682325 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 23:47:10.686247 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 23:47:10.692939 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 23:47:10.704694 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 23:47:10.708320 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 23:47:10.715856 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 23:47:10.722417 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 23:47:10.730199 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 23:47:10.733633 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 23:47:10.736942 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:47:10.744712 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x12
466 23:47:10.748406 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 23:47:10.757016 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
468 23:47:10.759904 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 23:47:10.769465 [RTC]rtc_get_frequency_meter,154: input=15, output=789
470 23:47:10.778940 [RTC]rtc_get_frequency_meter,154: input=23, output=977
471 23:47:10.787885 [RTC]rtc_get_frequency_meter,154: input=19, output=884
472 23:47:10.798139 [RTC]rtc_get_frequency_meter,154: input=17, output=837
473 23:47:10.807422 [RTC]rtc_get_frequency_meter,154: input=16, output=813
474 23:47:10.816954 [RTC]rtc_get_frequency_meter,154: input=15, output=790
475 23:47:10.827298 [RTC]rtc_get_frequency_meter,154: input=16, output=813
476 23:47:10.831005 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
477 23:47:10.834509 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
478 23:47:10.838019 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 23:47:10.845357 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 23:47:10.849213 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 23:47:10.853067 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 23:47:10.856363 ADC[4]: Raw value=902436 ID=7
483 23:47:10.856841 ADC[3]: Raw value=213336 ID=1
484 23:47:10.860351 RAM Code: 0x71
485 23:47:10.863826 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 23:47:10.867431 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 23:47:10.878241 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 23:47:10.882065 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 23:47:10.885457 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 23:47:10.890906 in-header: 03 07 00 00 08 00 00 00
491 23:47:10.894219 in-data: aa e4 47 04 13 02 00 00
492 23:47:10.897711 Chrome EC: UHEPI supported
493 23:47:10.904912 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 23:47:10.909216 in-header: 03 ed 00 00 08 00 00 00
495 23:47:10.909635 in-data: 80 20 60 08 00 00 00 00
496 23:47:10.912426 MRC: failed to locate region type 0.
497 23:47:10.919314 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 23:47:10.922731 DRAM-K: Running full calibration
499 23:47:10.930527 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 23:47:10.931182 header.status = 0x0
501 23:47:10.933797 header.version = 0x6 (expected: 0x6)
502 23:47:10.938148 header.size = 0xd00 (expected: 0xd00)
503 23:47:10.942110 header.flags = 0x0
504 23:47:10.944786 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 23:47:10.963842 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
506 23:47:10.971426 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 23:47:10.975522 dram_init: ddr_geometry: 2
508 23:47:10.975957 [EMI] MDL number = 2
509 23:47:10.979014 [EMI] Get MDL freq = 0
510 23:47:10.979461 dram_init: ddr_type: 0
511 23:47:10.982816 is_discrete_lpddr4: 1
512 23:47:10.986333 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 23:47:10.986818
514 23:47:10.987253
515 23:47:10.987666 [Bian_co] ETT version 0.0.0.1
516 23:47:10.993202 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 23:47:10.993684
518 23:47:10.997230 dramc_set_vcore_voltage set vcore to 650000
519 23:47:10.997661 Read voltage for 800, 4
520 23:47:11.000603 Vio18 = 0
521 23:47:11.001152 Vcore = 650000
522 23:47:11.001546 Vdram = 0
523 23:47:11.004174 Vddq = 0
524 23:47:11.004758 Vmddr = 0
525 23:47:11.007595 dram_init: config_dvfs: 1
526 23:47:11.011297 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 23:47:11.014755 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 23:47:11.021562 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
529 23:47:11.024965 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
530 23:47:11.027975 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
531 23:47:11.031585 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
532 23:47:11.034873 MEM_TYPE=3, freq_sel=18
533 23:47:11.037954 sv_algorithm_assistance_LP4_1600
534 23:47:11.041471 ============ PULL DRAM RESETB DOWN ============
535 23:47:11.044933 ========== PULL DRAM RESETB DOWN end =========
536 23:47:11.048200 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 23:47:11.051954 ===================================
538 23:47:11.055195 LPDDR4 DRAM CONFIGURATION
539 23:47:11.058339 ===================================
540 23:47:11.061552 EX_ROW_EN[0] = 0x0
541 23:47:11.062020 EX_ROW_EN[1] = 0x0
542 23:47:11.064967 LP4Y_EN = 0x0
543 23:47:11.065456 WORK_FSP = 0x0
544 23:47:11.068341 WL = 0x2
545 23:47:11.068755 RL = 0x2
546 23:47:11.071817 BL = 0x2
547 23:47:11.072233 RPST = 0x0
548 23:47:11.075019 RD_PRE = 0x0
549 23:47:11.075434 WR_PRE = 0x1
550 23:47:11.078319 WR_PST = 0x0
551 23:47:11.078785 DBI_WR = 0x0
552 23:47:11.081673 DBI_RD = 0x0
553 23:47:11.082087 OTF = 0x1
554 23:47:11.085229 ===================================
555 23:47:11.088738 ===================================
556 23:47:11.091794 ANA top config
557 23:47:11.095400 ===================================
558 23:47:11.098664 DLL_ASYNC_EN = 0
559 23:47:11.099169 ALL_SLAVE_EN = 1
560 23:47:11.101601 NEW_RANK_MODE = 1
561 23:47:11.105251 DLL_IDLE_MODE = 1
562 23:47:11.108469 LP45_APHY_COMB_EN = 1
563 23:47:11.108946 TX_ODT_DIS = 1
564 23:47:11.111858 NEW_8X_MODE = 1
565 23:47:11.115340 ===================================
566 23:47:11.118770 ===================================
567 23:47:11.122310 data_rate = 1600
568 23:47:11.125350 CKR = 1
569 23:47:11.129059 DQ_P2S_RATIO = 8
570 23:47:11.131754 ===================================
571 23:47:11.132193 CA_P2S_RATIO = 8
572 23:47:11.135255 DQ_CA_OPEN = 0
573 23:47:11.138984 DQ_SEMI_OPEN = 0
574 23:47:11.142289 CA_SEMI_OPEN = 0
575 23:47:11.145217 CA_FULL_RATE = 0
576 23:47:11.148874 DQ_CKDIV4_EN = 1
577 23:47:11.149368 CA_CKDIV4_EN = 1
578 23:47:11.152738 CA_PREDIV_EN = 0
579 23:47:11.155777 PH8_DLY = 0
580 23:47:11.158822 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 23:47:11.162081 DQ_AAMCK_DIV = 4
582 23:47:11.165359 CA_AAMCK_DIV = 4
583 23:47:11.165777 CA_ADMCK_DIV = 4
584 23:47:11.168683 DQ_TRACK_CA_EN = 0
585 23:47:11.172296 CA_PICK = 800
586 23:47:11.175608 CA_MCKIO = 800
587 23:47:11.178537 MCKIO_SEMI = 0
588 23:47:11.182593 PLL_FREQ = 3068
589 23:47:11.183055 DQ_UI_PI_RATIO = 32
590 23:47:11.186136 CA_UI_PI_RATIO = 0
591 23:47:11.189595 ===================================
592 23:47:11.193267 ===================================
593 23:47:11.197233 memory_type:LPDDR4
594 23:47:11.197669 GP_NUM : 10
595 23:47:11.200649 SRAM_EN : 1
596 23:47:11.201113 MD32_EN : 0
597 23:47:11.204444 ===================================
598 23:47:11.208010 [ANA_INIT] >>>>>>>>>>>>>>
599 23:47:11.211863 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 23:47:11.216010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 23:47:11.216617 ===================================
602 23:47:11.219130 data_rate = 1600,PCW = 0X7600
603 23:47:11.222566 ===================================
604 23:47:11.225808 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 23:47:11.232354 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 23:47:11.236039 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:47:11.242961 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 23:47:11.245773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 23:47:11.249190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:47:11.249367 [ANA_INIT] flow start
611 23:47:11.252330 [ANA_INIT] PLL >>>>>>>>
612 23:47:11.256178 [ANA_INIT] PLL <<<<<<<<
613 23:47:11.259350 [ANA_INIT] MIDPI >>>>>>>>
614 23:47:11.259502 [ANA_INIT] MIDPI <<<<<<<<
615 23:47:11.263008 [ANA_INIT] DLL >>>>>>>>
616 23:47:11.263141 [ANA_INIT] flow end
617 23:47:11.269303 ============ LP4 DIFF to SE enter ============
618 23:47:11.273224 ============ LP4 DIFF to SE exit ============
619 23:47:11.276233 [ANA_INIT] <<<<<<<<<<<<<
620 23:47:11.279694 [Flow] Enable top DCM control >>>>>
621 23:47:11.283242 [Flow] Enable top DCM control <<<<<
622 23:47:11.283366 Enable DLL master slave shuffle
623 23:47:11.289554 ==============================================================
624 23:47:11.293066 Gating Mode config
625 23:47:11.296537 ==============================================================
626 23:47:11.299476 Config description:
627 23:47:11.309673 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 23:47:11.316700 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 23:47:11.319871 SELPH_MODE 0: By rank 1: By Phase
630 23:47:11.326658 ==============================================================
631 23:47:11.329789 GAT_TRACK_EN = 1
632 23:47:11.333551 RX_GATING_MODE = 2
633 23:47:11.334002 RX_GATING_TRACK_MODE = 2
634 23:47:11.337025 SELPH_MODE = 1
635 23:47:11.340182 PICG_EARLY_EN = 1
636 23:47:11.344167 VALID_LAT_VALUE = 1
637 23:47:11.350106 ==============================================================
638 23:47:11.353601 Enter into Gating configuration >>>>
639 23:47:11.356914 Exit from Gating configuration <<<<
640 23:47:11.360086 Enter into DVFS_PRE_config >>>>>
641 23:47:11.370304 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 23:47:11.373545 Exit from DVFS_PRE_config <<<<<
643 23:47:11.377586 Enter into PICG configuration >>>>
644 23:47:11.380841 Exit from PICG configuration <<<<
645 23:47:11.383893 [RX_INPUT] configuration >>>>>
646 23:47:11.384401 [RX_INPUT] configuration <<<<<
647 23:47:11.390740 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 23:47:11.397152 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 23:47:11.401275 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 23:47:11.408070 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 23:47:11.414811 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 23:47:11.421854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 23:47:11.425146 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 23:47:11.427998 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 23:47:11.431358 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 23:47:11.438099 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 23:47:11.441911 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 23:47:11.445117 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 23:47:11.448802 ===================================
660 23:47:11.451575 LPDDR4 DRAM CONFIGURATION
661 23:47:11.455087 ===================================
662 23:47:11.455525 EX_ROW_EN[0] = 0x0
663 23:47:11.458369 EX_ROW_EN[1] = 0x0
664 23:47:11.462023 LP4Y_EN = 0x0
665 23:47:11.462442 WORK_FSP = 0x0
666 23:47:11.465522 WL = 0x2
667 23:47:11.465940 RL = 0x2
668 23:47:11.468599 BL = 0x2
669 23:47:11.469053 RPST = 0x0
670 23:47:11.471694 RD_PRE = 0x0
671 23:47:11.472113 WR_PRE = 0x1
672 23:47:11.475158 WR_PST = 0x0
673 23:47:11.475581 DBI_WR = 0x0
674 23:47:11.478808 DBI_RD = 0x0
675 23:47:11.479227 OTF = 0x1
676 23:47:11.481692 ===================================
677 23:47:11.485263 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 23:47:11.492033 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 23:47:11.495029 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 23:47:11.498505 ===================================
681 23:47:11.502283 LPDDR4 DRAM CONFIGURATION
682 23:47:11.505678 ===================================
683 23:47:11.506101 EX_ROW_EN[0] = 0x10
684 23:47:11.508705 EX_ROW_EN[1] = 0x0
685 23:47:11.509171 LP4Y_EN = 0x0
686 23:47:11.512144 WORK_FSP = 0x0
687 23:47:11.512563 WL = 0x2
688 23:47:11.515345 RL = 0x2
689 23:47:11.515779 BL = 0x2
690 23:47:11.518929 RPST = 0x0
691 23:47:11.519351 RD_PRE = 0x0
692 23:47:11.522331 WR_PRE = 0x1
693 23:47:11.522753 WR_PST = 0x0
694 23:47:11.525454 DBI_WR = 0x0
695 23:47:11.525873 DBI_RD = 0x0
696 23:47:11.528966 OTF = 0x1
697 23:47:11.532177 ===================================
698 23:47:11.538937 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 23:47:11.542385 nWR fixed to 40
700 23:47:11.545719 [ModeRegInit_LP4] CH0 RK0
701 23:47:11.546174 [ModeRegInit_LP4] CH0 RK1
702 23:47:11.549317 [ModeRegInit_LP4] CH1 RK0
703 23:47:11.552278 [ModeRegInit_LP4] CH1 RK1
704 23:47:11.552752 match AC timing 13
705 23:47:11.559223 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 23:47:11.562471 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 23:47:11.565993 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 23:47:11.572664 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 23:47:11.576067 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 23:47:11.576544 [EMI DOE] emi_dcm 0
711 23:47:11.582523 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 23:47:11.583105 ==
713 23:47:11.586311 Dram Type= 6, Freq= 0, CH_0, rank 0
714 23:47:11.589207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 23:47:11.589628 ==
716 23:47:11.596435 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 23:47:11.599279 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 23:47:11.609649 [CA 0] Center 37 (7~68) winsize 62
719 23:47:11.612744 [CA 1] Center 37 (6~68) winsize 63
720 23:47:11.616191 [CA 2] Center 35 (5~66) winsize 62
721 23:47:11.619568 [CA 3] Center 34 (4~65) winsize 62
722 23:47:11.623158 [CA 4] Center 34 (4~64) winsize 61
723 23:47:11.626333 [CA 5] Center 34 (4~64) winsize 61
724 23:47:11.626755
725 23:47:11.629890 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 23:47:11.630310
727 23:47:11.632831 [CATrainingPosCal] consider 1 rank data
728 23:47:11.636543 u2DelayCellTimex100 = 270/100 ps
729 23:47:11.639859 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
730 23:47:11.643296 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
731 23:47:11.646096 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
732 23:47:11.652833 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
733 23:47:11.656571 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
734 23:47:11.659931 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
735 23:47:11.660358
736 23:47:11.663133 CA PerBit enable=1, Macro0, CA PI delay=34
737 23:47:11.663557
738 23:47:11.666297 [CBTSetCACLKResult] CA Dly = 34
739 23:47:11.666820 CS Dly: 5 (0~36)
740 23:47:11.667295 ==
741 23:47:11.670087 Dram Type= 6, Freq= 0, CH_0, rank 1
742 23:47:11.676208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 23:47:11.676639 ==
744 23:47:11.679750 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 23:47:11.686511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 23:47:11.695866 [CA 0] Center 37 (6~68) winsize 63
747 23:47:11.699173 [CA 1] Center 37 (6~68) winsize 63
748 23:47:11.702540 [CA 2] Center 35 (4~66) winsize 63
749 23:47:11.705852 [CA 3] Center 35 (4~66) winsize 63
750 23:47:11.708768 [CA 4] Center 34 (3~65) winsize 63
751 23:47:11.712549 [CA 5] Center 33 (3~64) winsize 62
752 23:47:11.713026
753 23:47:11.715685 [CmdBusTrainingLP45] Vref(ca) range 1: 34
754 23:47:11.716107
755 23:47:11.719642 [CATrainingPosCal] consider 2 rank data
756 23:47:11.722212 u2DelayCellTimex100 = 270/100 ps
757 23:47:11.725919 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
758 23:47:11.729122 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
759 23:47:11.735576 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
760 23:47:11.739061 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
761 23:47:11.742519 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
762 23:47:11.746100 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
763 23:47:11.746557
764 23:47:11.748869 CA PerBit enable=1, Macro0, CA PI delay=34
765 23:47:11.749353
766 23:47:11.752764 [CBTSetCACLKResult] CA Dly = 34
767 23:47:11.753308 CS Dly: 5 (0~37)
768 23:47:11.753710
769 23:47:11.755724 ----->DramcWriteLeveling(PI) begin...
770 23:47:11.756211 ==
771 23:47:11.759185 Dram Type= 6, Freq= 0, CH_0, rank 0
772 23:47:11.766738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 23:47:11.767204 ==
774 23:47:11.767570 Write leveling (Byte 0): 28 => 28
775 23:47:11.770223 Write leveling (Byte 1): 29 => 29
776 23:47:11.773723 DramcWriteLeveling(PI) end<-----
777 23:47:11.774224
778 23:47:11.774619 ==
779 23:47:11.777495 Dram Type= 6, Freq= 0, CH_0, rank 0
780 23:47:11.780872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 23:47:11.781401 ==
782 23:47:11.784864 [Gating] SW mode calibration
783 23:47:11.791392 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 23:47:11.798779 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 23:47:11.802073 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 23:47:11.805468 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 23:47:11.808778 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
788 23:47:11.815146 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 23:47:11.818839 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:47:11.821878 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:47:11.829517 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:47:11.832338 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:47:11.835593 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:47:11.842235 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:47:11.845647 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:47:11.849021 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:47:11.855292 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:47:11.858673 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:47:11.862070 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:47:11.869238 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:47:11.872171 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:47:11.875906 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:47:11.879060 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
804 23:47:11.885409 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
805 23:47:11.889421 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:47:11.892534 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:47:11.899159 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:47:11.902695 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:47:11.905709 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:47:11.912858 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:47:11.915899 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
812 23:47:11.919472 0 9 12 | B1->B0 | 2a2a 3333 | 1 0 | (0 0) (0 0)
813 23:47:11.925701 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 23:47:11.929188 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:47:11.932814 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:47:11.938988 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:47:11.942628 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:47:11.945897 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:47:11.949596 0 10 8 | B1->B0 | 3333 3030 | 0 0 | (0 1) (0 1)
820 23:47:11.955980 0 10 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
821 23:47:11.959662 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 23:47:11.963082 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:47:11.969655 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:47:11.972865 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:47:11.976134 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:47:11.982612 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:47:11.986055 0 11 8 | B1->B0 | 2727 3030 | 0 0 | (0 0) (0 0)
828 23:47:11.989566 0 11 12 | B1->B0 | 3535 4141 | 0 0 | (0 0) (0 0)
829 23:47:11.995747 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
830 23:47:11.999264 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:47:12.002999 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:47:12.010082 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:47:12.012791 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:47:12.016325 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:47:12.022893 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 23:47:12.026345 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 23:47:12.029500 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:47:12.032537 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:47:12.039611 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:47:12.043238 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:47:12.046314 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:47:12.053082 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:47:12.056277 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:47:12.059354 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:47:12.066367 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:47:12.069737 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:47:12.073316 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:47:12.079875 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:47:12.083298 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:47:12.086715 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:47:12.089979 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
852 23:47:12.096518 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 23:47:12.100094 Total UI for P1: 0, mck2ui 16
854 23:47:12.103002 best dqsien dly found for B0: ( 0, 14, 8)
855 23:47:12.106811 Total UI for P1: 0, mck2ui 16
856 23:47:12.109670 best dqsien dly found for B1: ( 0, 14, 8)
857 23:47:12.113575 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
858 23:47:12.116443 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 23:47:12.116865
860 23:47:12.119991 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
861 23:47:12.123443 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 23:47:12.126821 [Gating] SW calibration Done
863 23:47:12.127262 ==
864 23:47:12.130109 Dram Type= 6, Freq= 0, CH_0, rank 0
865 23:47:12.133371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 23:47:12.133791 ==
867 23:47:12.136472 RX Vref Scan: 0
868 23:47:12.136888
869 23:47:12.137280 RX Vref 0 -> 0, step: 1
870 23:47:12.137599
871 23:47:12.139862 RX Delay -130 -> 252, step: 16
872 23:47:12.143375 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
873 23:47:12.150159 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
874 23:47:12.153436 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
875 23:47:12.156862 iDelay=206, Bit 3, Center 77 (-50 ~ 205) 256
876 23:47:12.160405 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
877 23:47:12.163378 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
878 23:47:12.170001 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
879 23:47:12.174252 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
880 23:47:12.177184 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
881 23:47:12.180068 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
882 23:47:12.183575 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
883 23:47:12.187032 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
884 23:47:12.193411 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
885 23:47:12.197069 iDelay=206, Bit 13, Center 77 (-34 ~ 189) 224
886 23:47:12.200762 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
887 23:47:12.204125 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
888 23:47:12.204546 ==
889 23:47:12.206866 Dram Type= 6, Freq= 0, CH_0, rank 0
890 23:47:12.213671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 23:47:12.214094 ==
892 23:47:12.214430 DQS Delay:
893 23:47:12.217152 DQS0 = 0, DQS1 = 0
894 23:47:12.217568 DQM Delay:
895 23:47:12.217903 DQM0 = 82, DQM1 = 77
896 23:47:12.220575 DQ Delay:
897 23:47:12.223970 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
898 23:47:12.226917 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =85
899 23:47:12.230299 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
900 23:47:12.233749 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
901 23:47:12.234166
902 23:47:12.234496
903 23:47:12.234805 ==
904 23:47:12.237214 Dram Type= 6, Freq= 0, CH_0, rank 0
905 23:47:12.240713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 23:47:12.241172 ==
907 23:47:12.241512
908 23:47:12.241818
909 23:47:12.244257 TX Vref Scan disable
910 23:47:12.244679 == TX Byte 0 ==
911 23:47:12.250945 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
912 23:47:12.254159 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
913 23:47:12.254586 == TX Byte 1 ==
914 23:47:12.260644 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
915 23:47:12.263975 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
916 23:47:12.264497 ==
917 23:47:12.267457 Dram Type= 6, Freq= 0, CH_0, rank 0
918 23:47:12.270283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 23:47:12.270707 ==
920 23:47:12.284247 TX Vref=22, minBit 0, minWin=27, winSum=440
921 23:47:12.287214 TX Vref=24, minBit 0, minWin=27, winSum=441
922 23:47:12.291041 TX Vref=26, minBit 1, minWin=27, winSum=445
923 23:47:12.294314 TX Vref=28, minBit 5, minWin=27, winSum=454
924 23:47:12.297850 TX Vref=30, minBit 2, minWin=28, winSum=454
925 23:47:12.300630 TX Vref=32, minBit 3, minWin=27, winSum=451
926 23:47:12.307504 [TxChooseVref] Worse bit 2, Min win 28, Win sum 454, Final Vref 30
927 23:47:12.307925
928 23:47:12.310987 Final TX Range 1 Vref 30
929 23:47:12.311408
930 23:47:12.311740 ==
931 23:47:12.314608 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:47:12.317443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 23:47:12.317869 ==
934 23:47:12.318203
935 23:47:12.320697
936 23:47:12.321140 TX Vref Scan disable
937 23:47:12.324437 == TX Byte 0 ==
938 23:47:12.327573 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
939 23:47:12.331078 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
940 23:47:12.334492 == TX Byte 1 ==
941 23:47:12.337501 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
942 23:47:12.341551 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
943 23:47:12.341977
944 23:47:12.344400 [DATLAT]
945 23:47:12.344815 Freq=800, CH0 RK0
946 23:47:12.345184
947 23:47:12.347508 DATLAT Default: 0xa
948 23:47:12.347926 0, 0xFFFF, sum = 0
949 23:47:12.351482 1, 0xFFFF, sum = 0
950 23:47:12.351924 2, 0xFFFF, sum = 0
951 23:47:12.354485 3, 0xFFFF, sum = 0
952 23:47:12.354907 4, 0xFFFF, sum = 0
953 23:47:12.357716 5, 0xFFFF, sum = 0
954 23:47:12.358141 6, 0xFFFF, sum = 0
955 23:47:12.361299 7, 0xFFFF, sum = 0
956 23:47:12.361722 8, 0xFFFF, sum = 0
957 23:47:12.364692 9, 0x0, sum = 1
958 23:47:12.365145 10, 0x0, sum = 2
959 23:47:12.367715 11, 0x0, sum = 3
960 23:47:12.368140 12, 0x0, sum = 4
961 23:47:12.371113 best_step = 10
962 23:47:12.371532
963 23:47:12.371864 ==
964 23:47:12.374372 Dram Type= 6, Freq= 0, CH_0, rank 0
965 23:47:12.377824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 23:47:12.378244 ==
967 23:47:12.381799 RX Vref Scan: 1
968 23:47:12.382213
969 23:47:12.382560 Set Vref Range= 32 -> 127
970 23:47:12.382872
971 23:47:12.385067 RX Vref 32 -> 127, step: 1
972 23:47:12.385500
973 23:47:12.388134 RX Delay -95 -> 252, step: 8
974 23:47:12.388549
975 23:47:12.391212 Set Vref, RX VrefLevel [Byte0]: 32
976 23:47:12.394964 [Byte1]: 32
977 23:47:12.395484
978 23:47:12.398386 Set Vref, RX VrefLevel [Byte0]: 33
979 23:47:12.401836 [Byte1]: 33
980 23:47:12.402312
981 23:47:12.405529 Set Vref, RX VrefLevel [Byte0]: 34
982 23:47:12.408783 [Byte1]: 34
983 23:47:12.412545
984 23:47:12.412959 Set Vref, RX VrefLevel [Byte0]: 35
985 23:47:12.415420 [Byte1]: 35
986 23:47:12.419453
987 23:47:12.419868 Set Vref, RX VrefLevel [Byte0]: 36
988 23:47:12.422589 [Byte1]: 36
989 23:47:12.427384
990 23:47:12.427799 Set Vref, RX VrefLevel [Byte0]: 37
991 23:47:12.430849 [Byte1]: 37
992 23:47:12.435392
993 23:47:12.435807 Set Vref, RX VrefLevel [Byte0]: 38
994 23:47:12.438952 [Byte1]: 38
995 23:47:12.442888
996 23:47:12.443321 Set Vref, RX VrefLevel [Byte0]: 39
997 23:47:12.446146 [Byte1]: 39
998 23:47:12.450270
999 23:47:12.450685 Set Vref, RX VrefLevel [Byte0]: 40
1000 23:47:12.453811 [Byte1]: 40
1001 23:47:12.458256
1002 23:47:12.458681 Set Vref, RX VrefLevel [Byte0]: 41
1003 23:47:12.461652 [Byte1]: 41
1004 23:47:12.466254
1005 23:47:12.466672 Set Vref, RX VrefLevel [Byte0]: 42
1006 23:47:12.469249 [Byte1]: 42
1007 23:47:12.472912
1008 23:47:12.473356 Set Vref, RX VrefLevel [Byte0]: 43
1009 23:47:12.476075 [Byte1]: 43
1010 23:47:12.480262
1011 23:47:12.480675 Set Vref, RX VrefLevel [Byte0]: 44
1012 23:47:12.483713 [Byte1]: 44
1013 23:47:12.487779
1014 23:47:12.488198 Set Vref, RX VrefLevel [Byte0]: 45
1015 23:47:12.491713 [Byte1]: 45
1016 23:47:12.495849
1017 23:47:12.496267 Set Vref, RX VrefLevel [Byte0]: 46
1018 23:47:12.498692 [Byte1]: 46
1019 23:47:12.503345
1020 23:47:12.503758 Set Vref, RX VrefLevel [Byte0]: 47
1021 23:47:12.506351 [Byte1]: 47
1022 23:47:12.511083
1023 23:47:12.511496 Set Vref, RX VrefLevel [Byte0]: 48
1024 23:47:12.514212 [Byte1]: 48
1025 23:47:12.518749
1026 23:47:12.519155 Set Vref, RX VrefLevel [Byte0]: 49
1027 23:47:12.521778 [Byte1]: 49
1028 23:47:12.526074
1029 23:47:12.526689 Set Vref, RX VrefLevel [Byte0]: 50
1030 23:47:12.529503 [Byte1]: 50
1031 23:47:12.533770
1032 23:47:12.534177 Set Vref, RX VrefLevel [Byte0]: 51
1033 23:47:12.536953 [Byte1]: 51
1034 23:47:12.540845
1035 23:47:12.541322 Set Vref, RX VrefLevel [Byte0]: 52
1036 23:47:12.544777 [Byte1]: 52
1037 23:47:12.549021
1038 23:47:12.549431 Set Vref, RX VrefLevel [Byte0]: 53
1039 23:47:12.552089 [Byte1]: 53
1040 23:47:12.556611
1041 23:47:12.557055 Set Vref, RX VrefLevel [Byte0]: 54
1042 23:47:12.559755 [Byte1]: 54
1043 23:47:12.564326
1044 23:47:12.564732 Set Vref, RX VrefLevel [Byte0]: 55
1045 23:47:12.567174 [Byte1]: 55
1046 23:47:12.571385
1047 23:47:12.571795 Set Vref, RX VrefLevel [Byte0]: 56
1048 23:47:12.575287 [Byte1]: 56
1049 23:47:12.579158
1050 23:47:12.579566 Set Vref, RX VrefLevel [Byte0]: 57
1051 23:47:12.582784 [Byte1]: 57
1052 23:47:12.587085
1053 23:47:12.587494 Set Vref, RX VrefLevel [Byte0]: 58
1054 23:47:12.589935 [Byte1]: 58
1055 23:47:12.594636
1056 23:47:12.595136 Set Vref, RX VrefLevel [Byte0]: 59
1057 23:47:12.597437 [Byte1]: 59
1058 23:47:12.602105
1059 23:47:12.602512 Set Vref, RX VrefLevel [Byte0]: 60
1060 23:47:12.605776 [Byte1]: 60
1061 23:47:12.609895
1062 23:47:12.610301 Set Vref, RX VrefLevel [Byte0]: 61
1063 23:47:12.613395 [Byte1]: 61
1064 23:47:12.617067
1065 23:47:12.617479 Set Vref, RX VrefLevel [Byte0]: 62
1066 23:47:12.620449 [Byte1]: 62
1067 23:47:12.624688
1068 23:47:12.625134 Set Vref, RX VrefLevel [Byte0]: 63
1069 23:47:12.628291 [Byte1]: 63
1070 23:47:12.632541
1071 23:47:12.632951 Set Vref, RX VrefLevel [Byte0]: 64
1072 23:47:12.635813 [Byte1]: 64
1073 23:47:12.640008
1074 23:47:12.640416 Set Vref, RX VrefLevel [Byte0]: 65
1075 23:47:12.643654 [Byte1]: 65
1076 23:47:12.647710
1077 23:47:12.648119 Set Vref, RX VrefLevel [Byte0]: 66
1078 23:47:12.650670 [Byte1]: 66
1079 23:47:12.654844
1080 23:47:12.655251 Set Vref, RX VrefLevel [Byte0]: 67
1081 23:47:12.658580 [Byte1]: 67
1082 23:47:12.662470
1083 23:47:12.662889 Set Vref, RX VrefLevel [Byte0]: 68
1084 23:47:12.665834 [Byte1]: 68
1085 23:47:12.670287
1086 23:47:12.670707 Set Vref, RX VrefLevel [Byte0]: 69
1087 23:47:12.673555 [Byte1]: 69
1088 23:47:12.678028
1089 23:47:12.678450 Set Vref, RX VrefLevel [Byte0]: 70
1090 23:47:12.681139 [Byte1]: 70
1091 23:47:12.685338
1092 23:47:12.685760 Set Vref, RX VrefLevel [Byte0]: 71
1093 23:47:12.688585 [Byte1]: 71
1094 23:47:12.692856
1095 23:47:12.693326 Set Vref, RX VrefLevel [Byte0]: 72
1096 23:47:12.696036 [Byte1]: 72
1097 23:47:12.701023
1098 23:47:12.701447 Set Vref, RX VrefLevel [Byte0]: 73
1099 23:47:12.704319 [Byte1]: 73
1100 23:47:12.708428
1101 23:47:12.708950 Set Vref, RX VrefLevel [Byte0]: 74
1102 23:47:12.711831 [Byte1]: 74
1103 23:47:12.715836
1104 23:47:12.716391 Set Vref, RX VrefLevel [Byte0]: 75
1105 23:47:12.719369 [Byte1]: 75
1106 23:47:12.723624
1107 23:47:12.724090 Set Vref, RX VrefLevel [Byte0]: 76
1108 23:47:12.726730 [Byte1]: 76
1109 23:47:12.730923
1110 23:47:12.731371 Final RX Vref Byte 0 = 60 to rank0
1111 23:47:12.734655 Final RX Vref Byte 1 = 57 to rank0
1112 23:47:12.737631 Final RX Vref Byte 0 = 60 to rank1
1113 23:47:12.741109 Final RX Vref Byte 1 = 57 to rank1==
1114 23:47:12.744839 Dram Type= 6, Freq= 0, CH_0, rank 0
1115 23:47:12.747947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1116 23:47:12.751577 ==
1117 23:47:12.752083 DQS Delay:
1118 23:47:12.752414 DQS0 = 0, DQS1 = 0
1119 23:47:12.754865 DQM Delay:
1120 23:47:12.755275 DQM0 = 88, DQM1 = 80
1121 23:47:12.757689 DQ Delay:
1122 23:47:12.761481 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1123 23:47:12.761896 DQ4 =92, DQ5 =76, DQ6 =96, DQ7 =92
1124 23:47:12.764688 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1125 23:47:12.767880 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1126 23:47:12.768325
1127 23:47:12.771041
1128 23:47:12.777738 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1129 23:47:12.781481 CH0 RK0: MR19=606, MR18=2A11
1130 23:47:12.787903 CH0_RK0: MR19=0x606, MR18=0x2A11, DQSOSC=399, MR23=63, INC=92, DEC=61
1131 23:47:12.788320
1132 23:47:12.791256 ----->DramcWriteLeveling(PI) begin...
1133 23:47:12.791675 ==
1134 23:47:12.794387 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 23:47:12.798029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 23:47:12.798443 ==
1137 23:47:12.801402 Write leveling (Byte 0): 28 => 28
1138 23:47:12.805057 Write leveling (Byte 1): 28 => 28
1139 23:47:12.812827 DramcWriteLeveling(PI) end<-----
1140 23:47:12.813513
1141 23:47:12.814029 ==
1142 23:47:12.814471 Dram Type= 6, Freq= 0, CH_0, rank 1
1143 23:47:12.815112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1144 23:47:12.815446 ==
1145 23:47:12.818147 [Gating] SW mode calibration
1146 23:47:12.825140 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1147 23:47:12.831862 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1148 23:47:12.835450 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1149 23:47:12.838467 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1150 23:47:12.842143 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1151 23:47:12.885926 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 23:47:12.886665 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 23:47:12.887073 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 23:47:12.887417 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 23:47:12.887728 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:47:12.888020 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:47:12.888428 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:47:12.888750 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:47:12.889094 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:47:12.889390 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:47:12.894658 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:47:12.897937 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:47:12.902047 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:47:12.904402 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:47:12.907881 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1166 23:47:12.915115 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1167 23:47:12.918291 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:47:12.921302 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:47:12.928513 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 23:47:12.931735 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:47:12.934657 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:47:12.941395 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:47:12.945157 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:47:12.948247 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1175 23:47:12.951892 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
1176 23:47:12.958433 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 23:47:12.961756 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 23:47:12.965239 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 23:47:12.971536 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 23:47:12.975643 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:47:12.978318 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1182 23:47:12.985037 0 10 8 | B1->B0 | 3434 2a2a | 0 0 | (1 1) (1 1)
1183 23:47:12.988718 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1184 23:47:12.991467 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:47:12.998342 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:47:13.001861 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:47:13.005673 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:47:13.008957 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:47:13.015774 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1190 23:47:13.019141 0 11 8 | B1->B0 | 2626 4141 | 0 0 | (0 0) (0 0)
1191 23:47:13.023071 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1192 23:47:13.026909 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 23:47:13.030769 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 23:47:13.037265 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 23:47:13.040403 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:47:13.044383 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:47:13.051068 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1198 23:47:13.054616 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1199 23:47:13.058181 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1200 23:47:13.061231 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 23:47:13.068124 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 23:47:13.071749 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:47:13.074872 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:47:13.081484 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:47:13.084878 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:47:13.088214 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:47:13.094740 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:47:13.098179 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:47:13.101396 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:47:13.108176 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:47:13.111713 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:47:13.115195 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:47:13.118478 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1214 23:47:13.125293 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1215 23:47:13.128518 Total UI for P1: 0, mck2ui 16
1216 23:47:13.132085 best dqsien dly found for B0: ( 0, 14, 4)
1217 23:47:13.134968 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 23:47:13.138320 Total UI for P1: 0, mck2ui 16
1219 23:47:13.141889 best dqsien dly found for B1: ( 0, 14, 8)
1220 23:47:13.145490 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1221 23:47:13.148627 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1222 23:47:13.149089
1223 23:47:13.152049 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1224 23:47:13.155211 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1225 23:47:13.158400 [Gating] SW calibration Done
1226 23:47:13.158809 ==
1227 23:47:13.161814 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 23:47:13.165070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 23:47:13.169081 ==
1230 23:47:13.169492 RX Vref Scan: 0
1231 23:47:13.169820
1232 23:47:13.172070 RX Vref 0 -> 0, step: 1
1233 23:47:13.172566
1234 23:47:13.175388 RX Delay -130 -> 252, step: 16
1235 23:47:13.178660 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1236 23:47:13.182087 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1237 23:47:13.185522 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1238 23:47:13.188752 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1239 23:47:13.192026 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1240 23:47:13.198991 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1241 23:47:13.202552 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1242 23:47:13.205585 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1243 23:47:13.208757 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1244 23:47:13.212222 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1245 23:47:13.218805 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1246 23:47:13.222188 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1247 23:47:13.225658 iDelay=222, Bit 12, Center 69 (-50 ~ 189) 240
1248 23:47:13.229175 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1249 23:47:13.232419 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1250 23:47:13.238827 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1251 23:47:13.239381 ==
1252 23:47:13.242199 Dram Type= 6, Freq= 0, CH_0, rank 1
1253 23:47:13.245770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1254 23:47:13.246232 ==
1255 23:47:13.246593 DQS Delay:
1256 23:47:13.249519 DQS0 = 0, DQS1 = 0
1257 23:47:13.249934 DQM Delay:
1258 23:47:13.252066 DQM0 = 86, DQM1 = 75
1259 23:47:13.252477 DQ Delay:
1260 23:47:13.255533 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1261 23:47:13.258998 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1262 23:47:13.262554 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1263 23:47:13.265984 DQ12 =69, DQ13 =85, DQ14 =85, DQ15 =85
1264 23:47:13.266412
1265 23:47:13.266740
1266 23:47:13.267044 ==
1267 23:47:13.269147 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 23:47:13.272793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 23:47:13.273250 ==
1270 23:47:13.273580
1271 23:47:13.273884
1272 23:47:13.276162 TX Vref Scan disable
1273 23:47:13.279674 == TX Byte 0 ==
1274 23:47:13.282556 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1275 23:47:13.285849 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1276 23:47:13.289356 == TX Byte 1 ==
1277 23:47:13.292910 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1278 23:47:13.295925 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1279 23:47:13.296454 ==
1280 23:47:13.299396 Dram Type= 6, Freq= 0, CH_0, rank 1
1281 23:47:13.302786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1282 23:47:13.306097 ==
1283 23:47:13.317820 TX Vref=22, minBit 3, minWin=27, winSum=439
1284 23:47:13.320871 TX Vref=24, minBit 3, minWin=27, winSum=444
1285 23:47:13.324342 TX Vref=26, minBit 3, minWin=27, winSum=449
1286 23:47:13.327741 TX Vref=28, minBit 3, minWin=27, winSum=452
1287 23:47:13.330897 TX Vref=30, minBit 9, minWin=27, winSum=453
1288 23:47:13.334456 TX Vref=32, minBit 13, minWin=27, winSum=449
1289 23:47:13.341048 [TxChooseVref] Worse bit 9, Min win 27, Win sum 453, Final Vref 30
1290 23:47:13.341504
1291 23:47:13.344666 Final TX Range 1 Vref 30
1292 23:47:13.345282
1293 23:47:13.345742 ==
1294 23:47:13.347410 Dram Type= 6, Freq= 0, CH_0, rank 1
1295 23:47:13.350910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1296 23:47:13.351357 ==
1297 23:47:13.351802
1298 23:47:13.352135
1299 23:47:13.354412 TX Vref Scan disable
1300 23:47:13.357442 == TX Byte 0 ==
1301 23:47:13.360886 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1302 23:47:13.364715 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1303 23:47:13.367549 == TX Byte 1 ==
1304 23:47:13.371020 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1305 23:47:13.374360 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1306 23:47:13.374764
1307 23:47:13.377963 [DATLAT]
1308 23:47:13.378369 Freq=800, CH0 RK1
1309 23:47:13.378691
1310 23:47:13.381347 DATLAT Default: 0xa
1311 23:47:13.381888 0, 0xFFFF, sum = 0
1312 23:47:13.384630 1, 0xFFFF, sum = 0
1313 23:47:13.385184 2, 0xFFFF, sum = 0
1314 23:47:13.388219 3, 0xFFFF, sum = 0
1315 23:47:13.388632 4, 0xFFFF, sum = 0
1316 23:47:13.391934 5, 0xFFFF, sum = 0
1317 23:47:13.392466 6, 0xFFFF, sum = 0
1318 23:47:13.394698 7, 0xFFFF, sum = 0
1319 23:47:13.395114 8, 0xFFFF, sum = 0
1320 23:47:13.398134 9, 0x0, sum = 1
1321 23:47:13.398577 10, 0x0, sum = 2
1322 23:47:13.401242 11, 0x0, sum = 3
1323 23:47:13.401792 12, 0x0, sum = 4
1324 23:47:13.404432 best_step = 10
1325 23:47:13.404912
1326 23:47:13.405401 ==
1327 23:47:13.407821 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 23:47:13.411412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 23:47:13.411873 ==
1330 23:47:13.412201 RX Vref Scan: 0
1331 23:47:13.415334
1332 23:47:13.415740 RX Vref 0 -> 0, step: 1
1333 23:47:13.416060
1334 23:47:13.418036 RX Delay -95 -> 252, step: 8
1335 23:47:13.421181 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1336 23:47:13.428063 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1337 23:47:13.431558 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1338 23:47:13.434601 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1339 23:47:13.438344 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1340 23:47:13.441481 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1341 23:47:13.448270 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1342 23:47:13.451863 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1343 23:47:13.454912 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1344 23:47:13.458374 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1345 23:47:13.461849 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1346 23:47:13.464811 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1347 23:47:13.471803 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1348 23:47:13.475189 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1349 23:47:13.478522 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1350 23:47:13.482138 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1351 23:47:13.482550 ==
1352 23:47:13.485188 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 23:47:13.491661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 23:47:13.492154 ==
1355 23:47:13.492477 DQS Delay:
1356 23:47:13.495288 DQS0 = 0, DQS1 = 0
1357 23:47:13.495691 DQM Delay:
1358 23:47:13.496085 DQM0 = 87, DQM1 = 77
1359 23:47:13.498715 DQ Delay:
1360 23:47:13.502458 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1361 23:47:13.505494 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1362 23:47:13.508762 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1363 23:47:13.511969 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1364 23:47:13.512369
1365 23:47:13.512774
1366 23:47:13.518924 [DQSOSCAuto] RK1, (LSB)MR18= 0x301a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1367 23:47:13.522225 CH0 RK1: MR19=606, MR18=301A
1368 23:47:13.528658 CH0_RK1: MR19=0x606, MR18=0x301A, DQSOSC=397, MR23=63, INC=93, DEC=62
1369 23:47:13.532242 [RxdqsGatingPostProcess] freq 800
1370 23:47:13.535531 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1371 23:47:13.538794 Pre-setting of DQS Precalculation
1372 23:47:13.545608 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1373 23:47:13.546186 ==
1374 23:47:13.548914 Dram Type= 6, Freq= 0, CH_1, rank 0
1375 23:47:13.552634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1376 23:47:13.553202 ==
1377 23:47:13.559073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1378 23:47:13.562315 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1379 23:47:13.572521 [CA 0] Center 36 (6~66) winsize 61
1380 23:47:13.575483 [CA 1] Center 36 (6~67) winsize 62
1381 23:47:13.578993 [CA 2] Center 34 (4~65) winsize 62
1382 23:47:13.582399 [CA 3] Center 34 (3~65) winsize 63
1383 23:47:13.585480 [CA 4] Center 34 (4~65) winsize 62
1384 23:47:13.588834 [CA 5] Center 33 (3~64) winsize 62
1385 23:47:13.589287
1386 23:47:13.592325 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1387 23:47:13.592739
1388 23:47:13.595539 [CATrainingPosCal] consider 1 rank data
1389 23:47:13.598925 u2DelayCellTimex100 = 270/100 ps
1390 23:47:13.602645 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1391 23:47:13.606019 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1392 23:47:13.608697 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1393 23:47:13.615565 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1394 23:47:13.618775 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1395 23:47:13.622455 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1396 23:47:13.622571
1397 23:47:13.625207 CA PerBit enable=1, Macro0, CA PI delay=33
1398 23:47:13.625320
1399 23:47:13.628592 [CBTSetCACLKResult] CA Dly = 33
1400 23:47:13.628711 CS Dly: 5 (0~36)
1401 23:47:13.628794 ==
1402 23:47:13.632272 Dram Type= 6, Freq= 0, CH_1, rank 1
1403 23:47:13.638937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 23:47:13.639020 ==
1405 23:47:13.642112 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1406 23:47:13.649337 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1407 23:47:13.658302 [CA 0] Center 36 (6~67) winsize 62
1408 23:47:13.661946 [CA 1] Center 36 (6~66) winsize 61
1409 23:47:13.664832 [CA 2] Center 34 (4~65) winsize 62
1410 23:47:13.668080 [CA 3] Center 33 (3~64) winsize 62
1411 23:47:13.671014 [CA 4] Center 34 (4~65) winsize 62
1412 23:47:13.674874 [CA 5] Center 33 (3~64) winsize 62
1413 23:47:13.674982
1414 23:47:13.677860 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1415 23:47:13.678018
1416 23:47:13.681988 [CATrainingPosCal] consider 2 rank data
1417 23:47:13.685622 u2DelayCellTimex100 = 270/100 ps
1418 23:47:13.689648 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1419 23:47:13.693301 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1420 23:47:13.696917 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1421 23:47:13.700918 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1422 23:47:13.704449 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1423 23:47:13.708485 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1424 23:47:13.708825
1425 23:47:13.712033 CA PerBit enable=1, Macro0, CA PI delay=33
1426 23:47:13.712410
1427 23:47:13.715872 [CBTSetCACLKResult] CA Dly = 33
1428 23:47:13.716208 CS Dly: 5 (0~37)
1429 23:47:13.716529
1430 23:47:13.719694 ----->DramcWriteLeveling(PI) begin...
1431 23:47:13.720108 ==
1432 23:47:13.722390 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 23:47:13.725866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 23:47:13.729216 ==
1435 23:47:13.729880 Write leveling (Byte 0): 25 => 25
1436 23:47:13.732628 Write leveling (Byte 1): 30 => 30
1437 23:47:13.735904 DramcWriteLeveling(PI) end<-----
1438 23:47:13.736428
1439 23:47:13.736768 ==
1440 23:47:13.739268 Dram Type= 6, Freq= 0, CH_1, rank 0
1441 23:47:13.746158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1442 23:47:13.746595 ==
1443 23:47:13.746951 [Gating] SW mode calibration
1444 23:47:13.756210 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1445 23:47:13.759420 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1446 23:47:13.762734 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1447 23:47:13.769088 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 23:47:13.772527 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 23:47:13.776061 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 23:47:13.782903 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 23:47:13.786146 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 23:47:13.789351 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 23:47:13.796249 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:47:13.799598 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:47:13.803029 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:47:13.809674 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:47:13.812836 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:47:13.816288 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:47:13.819515 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:47:13.826329 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:47:13.829818 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:47:13.833338 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:47:13.840121 0 8 4 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 1)
1464 23:47:13.843214 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1465 23:47:13.846461 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:47:13.853082 0 8 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1467 23:47:13.856421 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:47:13.860084 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:47:13.867082 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:47:13.870475 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:47:13.873442 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:47:13.876867 0 9 8 | B1->B0 | 2525 2929 | 0 0 | (0 0) (0 0)
1473 23:47:13.883210 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 23:47:13.886520 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 23:47:13.891006 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 23:47:13.896524 0 9 24 | B1->B0 | 3534 3434 | 1 1 | (1 1) (1 1)
1477 23:47:13.899903 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 23:47:13.903259 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 23:47:13.910256 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
1480 23:47:13.913626 0 10 8 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 0)
1481 23:47:13.916659 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 23:47:13.923545 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 23:47:13.927213 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 23:47:13.930039 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:47:13.933536 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:47:13.940662 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:47:13.943739 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1488 23:47:13.947360 0 11 8 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
1489 23:47:13.954154 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1490 23:47:13.956943 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 23:47:13.960343 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 23:47:13.967444 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 23:47:13.970710 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 23:47:13.973693 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:47:13.980470 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 23:47:13.983561 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1497 23:47:13.987098 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 23:47:13.993467 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 23:47:13.997068 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 23:47:14.000815 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 23:47:14.003915 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:47:14.010380 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:47:14.014118 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:47:14.017545 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:47:14.023762 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:47:14.027238 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:47:14.030623 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:47:14.037457 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:47:14.040774 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:47:14.044520 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:47:14.050819 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:47:14.054359 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1513 23:47:14.057192 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 23:47:14.060501 Total UI for P1: 0, mck2ui 16
1515 23:47:14.064062 best dqsien dly found for B0: ( 0, 14, 8)
1516 23:47:14.067660 Total UI for P1: 0, mck2ui 16
1517 23:47:14.070989 best dqsien dly found for B1: ( 0, 14, 8)
1518 23:47:14.074503 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1519 23:47:14.077664 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1520 23:47:14.077886
1521 23:47:14.081056 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1522 23:47:14.084453 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1523 23:47:14.087675 [Gating] SW calibration Done
1524 23:47:14.087894 ==
1525 23:47:14.090703 Dram Type= 6, Freq= 0, CH_1, rank 0
1526 23:47:14.097738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1527 23:47:14.097960 ==
1528 23:47:14.098136 RX Vref Scan: 0
1529 23:47:14.098298
1530 23:47:14.101118 RX Vref 0 -> 0, step: 1
1531 23:47:14.101339
1532 23:47:14.104098 RX Delay -130 -> 252, step: 16
1533 23:47:14.107644 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1534 23:47:14.111356 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1535 23:47:14.114443 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1536 23:47:14.117569 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1537 23:47:14.124339 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1538 23:47:14.127844 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1539 23:47:14.130994 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1540 23:47:14.134377 iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224
1541 23:47:14.137720 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1542 23:47:14.144780 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1543 23:47:14.147716 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1544 23:47:14.151179 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1545 23:47:14.154725 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1546 23:47:14.158150 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1547 23:47:14.164569 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1548 23:47:14.167923 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1549 23:47:14.168145 ==
1550 23:47:14.171271 Dram Type= 6, Freq= 0, CH_1, rank 0
1551 23:47:14.175063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1552 23:47:14.175285 ==
1553 23:47:14.175459 DQS Delay:
1554 23:47:14.177962 DQS0 = 0, DQS1 = 0
1555 23:47:14.178182 DQM Delay:
1556 23:47:14.181327 DQM0 = 84, DQM1 = 75
1557 23:47:14.181546 DQ Delay:
1558 23:47:14.184948 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1559 23:47:14.188295 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =77
1560 23:47:14.191846 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1561 23:47:14.194689 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1562 23:47:14.194917
1563 23:47:14.195101
1564 23:47:14.195267 ==
1565 23:47:14.198155 Dram Type= 6, Freq= 0, CH_1, rank 0
1566 23:47:14.201668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1567 23:47:14.201897 ==
1568 23:47:14.205475
1569 23:47:14.205705
1570 23:47:14.205892 TX Vref Scan disable
1571 23:47:14.208053 == TX Byte 0 ==
1572 23:47:14.211764 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1573 23:47:14.214997 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1574 23:47:14.218002 == TX Byte 1 ==
1575 23:47:14.221309 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1576 23:47:14.224746 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1577 23:47:14.225062 ==
1578 23:47:14.228767 Dram Type= 6, Freq= 0, CH_1, rank 0
1579 23:47:14.234752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1580 23:47:14.234838 ==
1581 23:47:14.246895 TX Vref=22, minBit 11, minWin=26, winSum=437
1582 23:47:14.250376 TX Vref=24, minBit 0, minWin=27, winSum=440
1583 23:47:14.253698 TX Vref=26, minBit 1, minWin=27, winSum=444
1584 23:47:14.257748 TX Vref=28, minBit 0, minWin=27, winSum=447
1585 23:47:14.260692 TX Vref=30, minBit 11, minWin=27, winSum=450
1586 23:47:14.264406 TX Vref=32, minBit 0, minWin=27, winSum=449
1587 23:47:14.271233 [TxChooseVref] Worse bit 11, Min win 27, Win sum 450, Final Vref 30
1588 23:47:14.271315
1589 23:47:14.274819 Final TX Range 1 Vref 30
1590 23:47:14.274900
1591 23:47:14.274963 ==
1592 23:47:14.278043 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 23:47:14.281372 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 23:47:14.281452 ==
1595 23:47:14.281515
1596 23:47:14.281574
1597 23:47:14.284953 TX Vref Scan disable
1598 23:47:14.288430 == TX Byte 0 ==
1599 23:47:14.291805 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1600 23:47:14.295249 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1601 23:47:14.298235 == TX Byte 1 ==
1602 23:47:14.301973 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1603 23:47:14.305455 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1604 23:47:14.305534
1605 23:47:14.305600 [DATLAT]
1606 23:47:14.308587 Freq=800, CH1 RK0
1607 23:47:14.308667
1608 23:47:14.311458 DATLAT Default: 0xa
1609 23:47:14.311538 0, 0xFFFF, sum = 0
1610 23:47:14.315097 1, 0xFFFF, sum = 0
1611 23:47:14.315178 2, 0xFFFF, sum = 0
1612 23:47:14.318306 3, 0xFFFF, sum = 0
1613 23:47:14.318388 4, 0xFFFF, sum = 0
1614 23:47:14.321520 5, 0xFFFF, sum = 0
1615 23:47:14.321601 6, 0xFFFF, sum = 0
1616 23:47:14.324947 7, 0xFFFF, sum = 0
1617 23:47:14.325069 8, 0xFFFF, sum = 0
1618 23:47:14.328265 9, 0x0, sum = 1
1619 23:47:14.328345 10, 0x0, sum = 2
1620 23:47:14.331990 11, 0x0, sum = 3
1621 23:47:14.332073 12, 0x0, sum = 4
1622 23:47:14.332138 best_step = 10
1623 23:47:14.332197
1624 23:47:14.335310 ==
1625 23:47:14.338605 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 23:47:14.341769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 23:47:14.341850 ==
1628 23:47:14.341913 RX Vref Scan: 1
1629 23:47:14.341973
1630 23:47:14.345413 Set Vref Range= 32 -> 127
1631 23:47:14.345506
1632 23:47:14.348343 RX Vref 32 -> 127, step: 1
1633 23:47:14.348423
1634 23:47:14.352184 RX Delay -111 -> 252, step: 8
1635 23:47:14.352264
1636 23:47:14.355112 Set Vref, RX VrefLevel [Byte0]: 32
1637 23:47:14.358631 [Byte1]: 32
1638 23:47:14.358711
1639 23:47:14.361639 Set Vref, RX VrefLevel [Byte0]: 33
1640 23:47:14.365202 [Byte1]: 33
1641 23:47:14.365285
1642 23:47:14.368678 Set Vref, RX VrefLevel [Byte0]: 34
1643 23:47:14.371647 [Byte1]: 34
1644 23:47:14.375803
1645 23:47:14.375882 Set Vref, RX VrefLevel [Byte0]: 35
1646 23:47:14.378539 [Byte1]: 35
1647 23:47:14.383319
1648 23:47:14.383401 Set Vref, RX VrefLevel [Byte0]: 36
1649 23:47:14.386103 [Byte1]: 36
1650 23:47:14.390610
1651 23:47:14.390689 Set Vref, RX VrefLevel [Byte0]: 37
1652 23:47:14.394320 [Byte1]: 37
1653 23:47:14.398363
1654 23:47:14.398448 Set Vref, RX VrefLevel [Byte0]: 38
1655 23:47:14.401921 [Byte1]: 38
1656 23:47:14.406094
1657 23:47:14.406203 Set Vref, RX VrefLevel [Byte0]: 39
1658 23:47:14.409474 [Byte1]: 39
1659 23:47:14.413929
1660 23:47:14.414038 Set Vref, RX VrefLevel [Byte0]: 40
1661 23:47:14.417386 [Byte1]: 40
1662 23:47:14.421945
1663 23:47:14.422077 Set Vref, RX VrefLevel [Byte0]: 41
1664 23:47:14.424472 [Byte1]: 41
1665 23:47:14.429132
1666 23:47:14.429212 Set Vref, RX VrefLevel [Byte0]: 42
1667 23:47:14.432063 [Byte1]: 42
1668 23:47:14.436802
1669 23:47:14.436894 Set Vref, RX VrefLevel [Byte0]: 43
1670 23:47:14.440014 [Byte1]: 43
1671 23:47:14.444665
1672 23:47:14.444765 Set Vref, RX VrefLevel [Byte0]: 44
1673 23:47:14.448105 [Byte1]: 44
1674 23:47:14.452294
1675 23:47:14.452413 Set Vref, RX VrefLevel [Byte0]: 45
1676 23:47:14.455324 [Byte1]: 45
1677 23:47:14.459909
1678 23:47:14.460041 Set Vref, RX VrefLevel [Byte0]: 46
1679 23:47:14.462905 [Byte1]: 46
1680 23:47:14.467841
1681 23:47:14.468010 Set Vref, RX VrefLevel [Byte0]: 47
1682 23:47:14.470833 [Byte1]: 47
1683 23:47:14.475384
1684 23:47:14.475580 Set Vref, RX VrefLevel [Byte0]: 48
1685 23:47:14.478208 [Byte1]: 48
1686 23:47:14.482991
1687 23:47:14.483292 Set Vref, RX VrefLevel [Byte0]: 49
1688 23:47:14.485882 [Byte1]: 49
1689 23:47:14.490518
1690 23:47:14.490897 Set Vref, RX VrefLevel [Byte0]: 50
1691 23:47:14.494007 [Byte1]: 50
1692 23:47:14.498514
1693 23:47:14.498924 Set Vref, RX VrefLevel [Byte0]: 51
1694 23:47:14.501743 [Byte1]: 51
1695 23:47:14.506245
1696 23:47:14.506658 Set Vref, RX VrefLevel [Byte0]: 52
1697 23:47:14.508874 [Byte1]: 52
1698 23:47:14.513458
1699 23:47:14.513866 Set Vref, RX VrefLevel [Byte0]: 53
1700 23:47:14.516884 [Byte1]: 53
1701 23:47:14.521134
1702 23:47:14.521575 Set Vref, RX VrefLevel [Byte0]: 54
1703 23:47:14.524678 [Byte1]: 54
1704 23:47:14.528747
1705 23:47:14.529240 Set Vref, RX VrefLevel [Byte0]: 55
1706 23:47:14.532077 [Byte1]: 55
1707 23:47:14.536347
1708 23:47:14.536771 Set Vref, RX VrefLevel [Byte0]: 56
1709 23:47:14.539613 [Byte1]: 56
1710 23:47:14.543777
1711 23:47:14.544266 Set Vref, RX VrefLevel [Byte0]: 57
1712 23:47:14.547030 [Byte1]: 57
1713 23:47:14.551548
1714 23:47:14.551848 Set Vref, RX VrefLevel [Byte0]: 58
1715 23:47:14.555064 [Byte1]: 58
1716 23:47:14.559308
1717 23:47:14.559532 Set Vref, RX VrefLevel [Byte0]: 59
1718 23:47:14.562217 [Byte1]: 59
1719 23:47:14.566855
1720 23:47:14.567076 Set Vref, RX VrefLevel [Byte0]: 60
1721 23:47:14.570174 [Byte1]: 60
1722 23:47:14.574522
1723 23:47:14.574742 Set Vref, RX VrefLevel [Byte0]: 61
1724 23:47:14.577710 [Byte1]: 61
1725 23:47:14.582054
1726 23:47:14.582277 Set Vref, RX VrefLevel [Byte0]: 62
1727 23:47:14.585686 [Byte1]: 62
1728 23:47:14.590109
1729 23:47:14.590331 Set Vref, RX VrefLevel [Byte0]: 63
1730 23:47:14.592856 [Byte1]: 63
1731 23:47:14.597448
1732 23:47:14.597669 Set Vref, RX VrefLevel [Byte0]: 64
1733 23:47:14.600482 [Byte1]: 64
1734 23:47:14.604995
1735 23:47:14.605231 Set Vref, RX VrefLevel [Byte0]: 65
1736 23:47:14.608529 [Byte1]: 65
1737 23:47:14.612533
1738 23:47:14.612753 Set Vref, RX VrefLevel [Byte0]: 66
1739 23:47:14.616099 [Byte1]: 66
1740 23:47:14.620514
1741 23:47:14.620735 Set Vref, RX VrefLevel [Byte0]: 67
1742 23:47:14.623794 [Byte1]: 67
1743 23:47:14.628010
1744 23:47:14.628259 Set Vref, RX VrefLevel [Byte0]: 68
1745 23:47:14.631326 [Byte1]: 68
1746 23:47:14.635413
1747 23:47:14.635635 Set Vref, RX VrefLevel [Byte0]: 69
1748 23:47:14.638950 [Byte1]: 69
1749 23:47:14.643009
1750 23:47:14.643231 Set Vref, RX VrefLevel [Byte0]: 70
1751 23:47:14.646439 [Byte1]: 70
1752 23:47:14.651062
1753 23:47:14.651281 Set Vref, RX VrefLevel [Byte0]: 71
1754 23:47:14.653921 [Byte1]: 71
1755 23:47:14.658756
1756 23:47:14.658979 Set Vref, RX VrefLevel [Byte0]: 72
1757 23:47:14.661639 [Byte1]: 72
1758 23:47:14.666027
1759 23:47:14.666246 Set Vref, RX VrefLevel [Byte0]: 73
1760 23:47:14.669440 [Byte1]: 73
1761 23:47:14.674190
1762 23:47:14.674409 Set Vref, RX VrefLevel [Byte0]: 74
1763 23:47:14.677350 [Byte1]: 74
1764 23:47:14.681674
1765 23:47:14.681895 Set Vref, RX VrefLevel [Byte0]: 75
1766 23:47:14.684644 [Byte1]: 75
1767 23:47:14.688874
1768 23:47:14.689121 Set Vref, RX VrefLevel [Byte0]: 76
1769 23:47:14.692692 [Byte1]: 76
1770 23:47:14.696767
1771 23:47:14.697002 Set Vref, RX VrefLevel [Byte0]: 77
1772 23:47:14.700171 [Byte1]: 77
1773 23:47:14.704365
1774 23:47:14.704592 Set Vref, RX VrefLevel [Byte0]: 78
1775 23:47:14.707585 [Byte1]: 78
1776 23:47:14.712134
1777 23:47:14.712356 Set Vref, RX VrefLevel [Byte0]: 79
1778 23:47:14.715461 [Byte1]: 79
1779 23:47:14.719508
1780 23:47:14.719752 Set Vref, RX VrefLevel [Byte0]: 80
1781 23:47:14.722810 [Byte1]: 80
1782 23:47:14.727371
1783 23:47:14.727601 Final RX Vref Byte 0 = 61 to rank0
1784 23:47:14.730798 Final RX Vref Byte 1 = 57 to rank0
1785 23:47:14.733939 Final RX Vref Byte 0 = 61 to rank1
1786 23:47:14.737432 Final RX Vref Byte 1 = 57 to rank1==
1787 23:47:14.740877 Dram Type= 6, Freq= 0, CH_1, rank 0
1788 23:47:14.743805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 23:47:14.747445 ==
1790 23:47:14.747756 DQS Delay:
1791 23:47:14.748011 DQS0 = 0, DQS1 = 0
1792 23:47:14.750891 DQM Delay:
1793 23:47:14.751186 DQM0 = 83, DQM1 = 73
1794 23:47:14.754469 DQ Delay:
1795 23:47:14.757688 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1796 23:47:14.757916 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =80
1797 23:47:14.760651 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1798 23:47:14.764143 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1799 23:47:14.764369
1800 23:47:14.767640
1801 23:47:14.774592 [DQSOSCAuto] RK0, (LSB)MR18= 0x24f9, (MSB)MR19= 0x605, tDQSOscB0 = 412 ps tDQSOscB1 = 400 ps
1802 23:47:14.777887 CH1 RK0: MR19=605, MR18=24F9
1803 23:47:14.784411 CH1_RK0: MR19=0x605, MR18=0x24F9, DQSOSC=400, MR23=63, INC=92, DEC=61
1804 23:47:14.784638
1805 23:47:14.788705 ----->DramcWriteLeveling(PI) begin...
1806 23:47:14.788929 ==
1807 23:47:14.791317 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 23:47:14.794949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 23:47:14.795172 ==
1810 23:47:14.797597 Write leveling (Byte 0): 30 => 30
1811 23:47:14.800884 Write leveling (Byte 1): 30 => 30
1812 23:47:14.804567 DramcWriteLeveling(PI) end<-----
1813 23:47:14.804882
1814 23:47:14.805162 ==
1815 23:47:14.808039 Dram Type= 6, Freq= 0, CH_1, rank 1
1816 23:47:14.811274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1817 23:47:14.811822 ==
1818 23:47:14.814771 [Gating] SW mode calibration
1819 23:47:14.821813 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1820 23:47:14.828128 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1821 23:47:14.831744 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1822 23:47:14.834812 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1823 23:47:14.838055 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:47:14.845534 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:47:14.847756 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:47:14.851515 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:47:14.858122 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:47:14.861524 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:47:14.864868 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 23:47:14.871809 0 7 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1831 23:47:14.874843 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 23:47:14.878134 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:47:14.884670 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1834 23:47:14.888433 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:47:14.891941 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1836 23:47:14.898392 0 7 28 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1837 23:47:14.901358 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1838 23:47:14.904859 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1839 23:47:14.911494 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1840 23:47:14.914909 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 23:47:14.918035 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 23:47:14.921692 0 8 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1843 23:47:14.928187 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 23:47:14.931313 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 23:47:14.934738 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 23:47:14.941215 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 23:47:14.944570 0 9 8 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
1848 23:47:14.948040 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1849 23:47:14.954946 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1850 23:47:14.958352 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 23:47:14.961602 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1852 23:47:14.968091 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 23:47:14.971783 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1854 23:47:14.974799 0 10 4 | B1->B0 | 3030 3030 | 0 0 | (0 0) (1 0)
1855 23:47:14.978551 0 10 8 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
1856 23:47:14.984994 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 23:47:14.988269 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 23:47:14.991832 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 23:47:14.998747 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1860 23:47:15.001888 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 23:47:15.005252 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 23:47:15.011766 0 11 4 | B1->B0 | 2b2b 3232 | 0 0 | (0 0) (0 0)
1863 23:47:15.014982 0 11 8 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
1864 23:47:15.018786 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1865 23:47:15.025170 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 23:47:15.028908 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 23:47:15.032065 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 23:47:15.038796 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 23:47:15.042047 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 23:47:15.045316 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1871 23:47:15.048920 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 23:47:15.055161 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 23:47:15.058752 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 23:47:15.062005 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 23:47:15.068820 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:47:15.071972 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:47:15.075543 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 23:47:15.082240 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 23:47:15.085953 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 23:47:15.089088 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 23:47:15.095653 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 23:47:15.099404 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 23:47:15.102357 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 23:47:15.105884 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 23:47:15.112700 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1886 23:47:15.115657 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1887 23:47:15.118946 Total UI for P1: 0, mck2ui 16
1888 23:47:15.122511 best dqsien dly found for B0: ( 0, 14, 0)
1889 23:47:15.125647 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 23:47:15.129449 Total UI for P1: 0, mck2ui 16
1891 23:47:15.132482 best dqsien dly found for B1: ( 0, 14, 4)
1892 23:47:15.135803 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1893 23:47:15.139076 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1894 23:47:15.139157
1895 23:47:15.146058 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1896 23:47:15.149407 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1897 23:47:15.149489 [Gating] SW calibration Done
1898 23:47:15.152914 ==
1899 23:47:15.153049 Dram Type= 6, Freq= 0, CH_1, rank 1
1900 23:47:15.159640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1901 23:47:15.159722 ==
1902 23:47:15.159786 RX Vref Scan: 0
1903 23:47:15.159846
1904 23:47:15.162898 RX Vref 0 -> 0, step: 1
1905 23:47:15.162978
1906 23:47:15.166272 RX Delay -130 -> 252, step: 16
1907 23:47:15.170034 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1908 23:47:15.173033 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1909 23:47:15.176276 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1910 23:47:15.182971 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1911 23:47:15.186092 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1912 23:47:15.189660 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1913 23:47:15.193143 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1914 23:47:15.196280 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1915 23:47:15.199701 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1916 23:47:15.206131 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1917 23:47:15.210030 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1918 23:47:15.213277 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1919 23:47:15.216169 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1920 23:47:15.219797 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1921 23:47:15.226145 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1922 23:47:15.229722 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1923 23:47:15.229803 ==
1924 23:47:15.233113 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 23:47:15.236886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 23:47:15.236968 ==
1927 23:47:15.240281 DQS Delay:
1928 23:47:15.240361 DQS0 = 0, DQS1 = 0
1929 23:47:15.240425 DQM Delay:
1930 23:47:15.243125 DQM0 = 82, DQM1 = 77
1931 23:47:15.243205 DQ Delay:
1932 23:47:15.246236 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1933 23:47:15.250076 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1934 23:47:15.252935 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1935 23:47:15.256603 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1936 23:47:15.256684
1937 23:47:15.256748
1938 23:47:15.256808 ==
1939 23:47:15.259619 Dram Type= 6, Freq= 0, CH_1, rank 1
1940 23:47:15.266629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1941 23:47:15.266715 ==
1942 23:47:15.266779
1943 23:47:15.266838
1944 23:47:15.266894 TX Vref Scan disable
1945 23:47:15.269683 == TX Byte 0 ==
1946 23:47:15.273421 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1947 23:47:15.277210 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1948 23:47:15.280295 == TX Byte 1 ==
1949 23:47:15.283445 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1950 23:47:15.286738 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1951 23:47:15.290005 ==
1952 23:47:15.293726 Dram Type= 6, Freq= 0, CH_1, rank 1
1953 23:47:15.296833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1954 23:47:15.296915 ==
1955 23:47:15.309243 TX Vref=22, minBit 0, minWin=27, winSum=441
1956 23:47:15.312450 TX Vref=24, minBit 1, minWin=27, winSum=442
1957 23:47:15.315419 TX Vref=26, minBit 1, minWin=27, winSum=447
1958 23:47:15.319383 TX Vref=28, minBit 1, minWin=27, winSum=448
1959 23:47:15.322635 TX Vref=30, minBit 0, minWin=28, winSum=451
1960 23:47:15.325724 TX Vref=32, minBit 3, minWin=27, winSum=449
1961 23:47:15.332367 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 30
1962 23:47:15.332477
1963 23:47:15.335623 Final TX Range 1 Vref 30
1964 23:47:15.335706
1965 23:47:15.335771 ==
1966 23:47:15.338834 Dram Type= 6, Freq= 0, CH_1, rank 1
1967 23:47:15.342678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1968 23:47:15.342759 ==
1969 23:47:15.342823
1970 23:47:15.342882
1971 23:47:15.345463 TX Vref Scan disable
1972 23:47:15.348779 == TX Byte 0 ==
1973 23:47:15.352178 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1974 23:47:15.356030 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1975 23:47:15.358872 == TX Byte 1 ==
1976 23:47:15.362502 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1977 23:47:15.365955 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1978 23:47:15.366036
1979 23:47:15.369390 [DATLAT]
1980 23:47:15.369471 Freq=800, CH1 RK1
1981 23:47:15.369535
1982 23:47:15.372454 DATLAT Default: 0xa
1983 23:47:15.372534 0, 0xFFFF, sum = 0
1984 23:47:15.375781 1, 0xFFFF, sum = 0
1985 23:47:15.375862 2, 0xFFFF, sum = 0
1986 23:47:15.378916 3, 0xFFFF, sum = 0
1987 23:47:15.378998 4, 0xFFFF, sum = 0
1988 23:47:15.382778 5, 0xFFFF, sum = 0
1989 23:47:15.382887 6, 0xFFFF, sum = 0
1990 23:47:15.385755 7, 0xFFFF, sum = 0
1991 23:47:15.385837 8, 0xFFFF, sum = 0
1992 23:47:15.389521 9, 0x0, sum = 1
1993 23:47:15.389604 10, 0x0, sum = 2
1994 23:47:15.392682 11, 0x0, sum = 3
1995 23:47:15.392764 12, 0x0, sum = 4
1996 23:47:15.395879 best_step = 10
1997 23:47:15.395960
1998 23:47:15.396024 ==
1999 23:47:15.399674 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 23:47:15.403037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 23:47:15.403120 ==
2002 23:47:15.403184 RX Vref Scan: 0
2003 23:47:15.403244
2004 23:47:15.406588 RX Vref 0 -> 0, step: 1
2005 23:47:15.406670
2006 23:47:15.409521 RX Delay -95 -> 252, step: 8
2007 23:47:15.412912 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2008 23:47:15.419928 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2009 23:47:15.422598 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2010 23:47:15.426502 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2011 23:47:15.429400 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
2012 23:47:15.432911 iDelay=209, Bit 5, Center 92 (-15 ~ 200) 216
2013 23:47:15.439880 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2014 23:47:15.443301 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2015 23:47:15.446478 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2016 23:47:15.449650 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2017 23:47:15.453396 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2018 23:47:15.456543 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2019 23:47:15.463429 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2020 23:47:15.466660 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2021 23:47:15.469863 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2022 23:47:15.473286 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2023 23:47:15.473366 ==
2024 23:47:15.476488 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 23:47:15.483493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 23:47:15.483576 ==
2027 23:47:15.483671 DQS Delay:
2028 23:47:15.483735 DQS0 = 0, DQS1 = 0
2029 23:47:15.486751 DQM Delay:
2030 23:47:15.486832 DQM0 = 80, DQM1 = 75
2031 23:47:15.490260 DQ Delay:
2032 23:47:15.493229 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2033 23:47:15.493309 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
2034 23:47:15.496872 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2035 23:47:15.500176 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =84
2036 23:47:15.503880
2037 23:47:15.503960
2038 23:47:15.510761 [DQSOSCAuto] RK1, (LSB)MR18= 0x222e, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2039 23:47:15.514084 CH1 RK1: MR19=606, MR18=222E
2040 23:47:15.520533 CH1_RK1: MR19=0x606, MR18=0x222E, DQSOSC=398, MR23=63, INC=93, DEC=62
2041 23:47:15.523639 [RxdqsGatingPostProcess] freq 800
2042 23:47:15.527371 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2043 23:47:15.530823 Pre-setting of DQS Precalculation
2044 23:47:15.537515 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2045 23:47:15.543971 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2046 23:47:15.550539 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2047 23:47:15.550951
2048 23:47:15.551276
2049 23:47:15.554579 [Calibration Summary] 1600 Mbps
2050 23:47:15.554992 CH 0, Rank 0
2051 23:47:15.557438 SW Impedance : PASS
2052 23:47:15.557912 DUTY Scan : NO K
2053 23:47:15.561083 ZQ Calibration : PASS
2054 23:47:15.564204 Jitter Meter : NO K
2055 23:47:15.564656 CBT Training : PASS
2056 23:47:15.567551 Write leveling : PASS
2057 23:47:15.570892 RX DQS gating : PASS
2058 23:47:15.571310 RX DQ/DQS(RDDQC) : PASS
2059 23:47:15.574245 TX DQ/DQS : PASS
2060 23:47:15.577695 RX DATLAT : PASS
2061 23:47:15.578109 RX DQ/DQS(Engine): PASS
2062 23:47:15.580900 TX OE : NO K
2063 23:47:15.581376 All Pass.
2064 23:47:15.581730
2065 23:47:15.584166 CH 0, Rank 1
2066 23:47:15.584590 SW Impedance : PASS
2067 23:47:15.587498 DUTY Scan : NO K
2068 23:47:15.587925 ZQ Calibration : PASS
2069 23:47:15.591166 Jitter Meter : NO K
2070 23:47:15.594471 CBT Training : PASS
2071 23:47:15.594782 Write leveling : PASS
2072 23:47:15.597854 RX DQS gating : PASS
2073 23:47:15.601090 RX DQ/DQS(RDDQC) : PASS
2074 23:47:15.601310 TX DQ/DQS : PASS
2075 23:47:15.604314 RX DATLAT : PASS
2076 23:47:15.607582 RX DQ/DQS(Engine): PASS
2077 23:47:15.607816 TX OE : NO K
2078 23:47:15.611416 All Pass.
2079 23:47:15.611553
2080 23:47:15.611658 CH 1, Rank 0
2081 23:47:15.614771 SW Impedance : PASS
2082 23:47:15.614909 DUTY Scan : NO K
2083 23:47:15.617866 ZQ Calibration : PASS
2084 23:47:15.618000 Jitter Meter : NO K
2085 23:47:15.621195 CBT Training : PASS
2086 23:47:15.624359 Write leveling : PASS
2087 23:47:15.624475 RX DQS gating : PASS
2088 23:47:15.627830 RX DQ/DQS(RDDQC) : PASS
2089 23:47:15.630893 TX DQ/DQS : PASS
2090 23:47:15.630991 RX DATLAT : PASS
2091 23:47:15.634546 RX DQ/DQS(Engine): PASS
2092 23:47:15.637958 TX OE : NO K
2093 23:47:15.638040 All Pass.
2094 23:47:15.638105
2095 23:47:15.638165 CH 1, Rank 1
2096 23:47:15.641296 SW Impedance : PASS
2097 23:47:15.644324 DUTY Scan : NO K
2098 23:47:15.644405 ZQ Calibration : PASS
2099 23:47:15.647530 Jitter Meter : NO K
2100 23:47:15.651204 CBT Training : PASS
2101 23:47:15.651284 Write leveling : PASS
2102 23:47:15.654762 RX DQS gating : PASS
2103 23:47:15.654842 RX DQ/DQS(RDDQC) : PASS
2104 23:47:15.657825 TX DQ/DQS : PASS
2105 23:47:15.661254 RX DATLAT : PASS
2106 23:47:15.661339 RX DQ/DQS(Engine): PASS
2107 23:47:15.664441 TX OE : NO K
2108 23:47:15.664526 All Pass.
2109 23:47:15.664593
2110 23:47:15.667626 DramC Write-DBI off
2111 23:47:15.670945 PER_BANK_REFRESH: Hybrid Mode
2112 23:47:15.671036 TX_TRACKING: ON
2113 23:47:15.674171 [GetDramInforAfterCalByMRR] Vendor 6.
2114 23:47:15.677682 [GetDramInforAfterCalByMRR] Revision 606.
2115 23:47:15.681900 [GetDramInforAfterCalByMRR] Revision 2 0.
2116 23:47:15.684615 MR0 0x3b3b
2117 23:47:15.684733 MR8 0x5151
2118 23:47:15.688415 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2119 23:47:15.688829
2120 23:47:15.689213 MR0 0x3b3b
2121 23:47:15.692039 MR8 0x5151
2122 23:47:15.695037 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2123 23:47:15.695453
2124 23:47:15.705345 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2125 23:47:15.708416 [FAST_K] Save calibration result to emmc
2126 23:47:15.712277 [FAST_K] Save calibration result to emmc
2127 23:47:15.712740 dram_init: config_dvfs: 1
2128 23:47:15.718306 dramc_set_vcore_voltage set vcore to 662500
2129 23:47:15.718721 Read voltage for 1200, 2
2130 23:47:15.721988 Vio18 = 0
2131 23:47:15.722402 Vcore = 662500
2132 23:47:15.722732 Vdram = 0
2133 23:47:15.723038 Vddq = 0
2134 23:47:15.724884 Vmddr = 0
2135 23:47:15.728441 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2136 23:47:15.734890 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2137 23:47:15.738221 MEM_TYPE=3, freq_sel=15
2138 23:47:15.738757 sv_algorithm_assistance_LP4_1600
2139 23:47:15.745139 ============ PULL DRAM RESETB DOWN ============
2140 23:47:15.748681 ========== PULL DRAM RESETB DOWN end =========
2141 23:47:15.751777 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2142 23:47:15.755289 ===================================
2143 23:47:15.758690 LPDDR4 DRAM CONFIGURATION
2144 23:47:15.762319 ===================================
2145 23:47:15.765620 EX_ROW_EN[0] = 0x0
2146 23:47:15.766037 EX_ROW_EN[1] = 0x0
2147 23:47:15.768700 LP4Y_EN = 0x0
2148 23:47:15.769187 WORK_FSP = 0x0
2149 23:47:15.772419 WL = 0x4
2150 23:47:15.772834 RL = 0x4
2151 23:47:15.775420 BL = 0x2
2152 23:47:15.775835 RPST = 0x0
2153 23:47:15.778420 RD_PRE = 0x0
2154 23:47:15.778839 WR_PRE = 0x1
2155 23:47:15.781839 WR_PST = 0x0
2156 23:47:15.782252 DBI_WR = 0x0
2157 23:47:15.785393 DBI_RD = 0x0
2158 23:47:15.785853 OTF = 0x1
2159 23:47:15.788764 ===================================
2160 23:47:15.792183 ===================================
2161 23:47:15.795690 ANA top config
2162 23:47:15.799006 ===================================
2163 23:47:15.799422 DLL_ASYNC_EN = 0
2164 23:47:15.802720 ALL_SLAVE_EN = 0
2165 23:47:15.805467 NEW_RANK_MODE = 1
2166 23:47:15.809275 DLL_IDLE_MODE = 1
2167 23:47:15.812089 LP45_APHY_COMB_EN = 1
2168 23:47:15.812503 TX_ODT_DIS = 1
2169 23:47:15.815825 NEW_8X_MODE = 1
2170 23:47:15.818715 ===================================
2171 23:47:15.822243 ===================================
2172 23:47:15.825615 data_rate = 2400
2173 23:47:15.828708 CKR = 1
2174 23:47:15.832571 DQ_P2S_RATIO = 8
2175 23:47:15.835470 ===================================
2176 23:47:15.835886 CA_P2S_RATIO = 8
2177 23:47:15.838932 DQ_CA_OPEN = 0
2178 23:47:15.843009 DQ_SEMI_OPEN = 0
2179 23:47:15.846219 CA_SEMI_OPEN = 0
2180 23:47:15.849550 CA_FULL_RATE = 0
2181 23:47:15.850074 DQ_CKDIV4_EN = 0
2182 23:47:15.852606 CA_CKDIV4_EN = 0
2183 23:47:15.856065 CA_PREDIV_EN = 0
2184 23:47:15.859836 PH8_DLY = 17
2185 23:47:15.862869 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2186 23:47:15.866085 DQ_AAMCK_DIV = 4
2187 23:47:15.866504 CA_AAMCK_DIV = 4
2188 23:47:15.869548 CA_ADMCK_DIV = 4
2189 23:47:15.873094 DQ_TRACK_CA_EN = 0
2190 23:47:15.876165 CA_PICK = 1200
2191 23:47:15.879237 CA_MCKIO = 1200
2192 23:47:15.882658 MCKIO_SEMI = 0
2193 23:47:15.886258 PLL_FREQ = 2366
2194 23:47:15.886673 DQ_UI_PI_RATIO = 32
2195 23:47:15.889578 CA_UI_PI_RATIO = 0
2196 23:47:15.893074 ===================================
2197 23:47:15.896265 ===================================
2198 23:47:15.900141 memory_type:LPDDR4
2199 23:47:15.902919 GP_NUM : 10
2200 23:47:15.903441 SRAM_EN : 1
2201 23:47:15.906244 MD32_EN : 0
2202 23:47:15.909834 ===================================
2203 23:47:15.910256 [ANA_INIT] >>>>>>>>>>>>>>
2204 23:47:15.913329 <<<<<< [CONFIGURE PHASE]: ANA_TX
2205 23:47:15.916497 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2206 23:47:15.919976 ===================================
2207 23:47:15.923227 data_rate = 2400,PCW = 0X5b00
2208 23:47:15.926165 ===================================
2209 23:47:15.929523 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2210 23:47:15.936087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2211 23:47:15.940220 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 23:47:15.946520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2213 23:47:15.949720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2214 23:47:15.952880 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2215 23:47:15.953344 [ANA_INIT] flow start
2216 23:47:15.956223 [ANA_INIT] PLL >>>>>>>>
2217 23:47:15.960084 [ANA_INIT] PLL <<<<<<<<
2218 23:47:15.960635 [ANA_INIT] MIDPI >>>>>>>>
2219 23:47:15.963630 [ANA_INIT] MIDPI <<<<<<<<
2220 23:47:15.967093 [ANA_INIT] DLL >>>>>>>>
2221 23:47:15.969648 [ANA_INIT] DLL <<<<<<<<
2222 23:47:15.970066 [ANA_INIT] flow end
2223 23:47:15.973397 ============ LP4 DIFF to SE enter ============
2224 23:47:15.980059 ============ LP4 DIFF to SE exit ============
2225 23:47:15.980481 [ANA_INIT] <<<<<<<<<<<<<
2226 23:47:15.983375 [Flow] Enable top DCM control >>>>>
2227 23:47:15.986593 [Flow] Enable top DCM control <<<<<
2228 23:47:15.989997 Enable DLL master slave shuffle
2229 23:47:15.996622 ==============================================================
2230 23:47:15.997176 Gating Mode config
2231 23:47:16.003464 ==============================================================
2232 23:47:16.006763 Config description:
2233 23:47:16.013518 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2234 23:47:16.020100 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2235 23:47:16.026534 SELPH_MODE 0: By rank 1: By Phase
2236 23:47:16.030271 ==============================================================
2237 23:47:16.034255 GAT_TRACK_EN = 1
2238 23:47:16.037034 RX_GATING_MODE = 2
2239 23:47:16.040065 RX_GATING_TRACK_MODE = 2
2240 23:47:16.043254 SELPH_MODE = 1
2241 23:47:16.046647 PICG_EARLY_EN = 1
2242 23:47:16.050025 VALID_LAT_VALUE = 1
2243 23:47:16.057206 ==============================================================
2244 23:47:16.060379 Enter into Gating configuration >>>>
2245 23:47:16.064030 Exit from Gating configuration <<<<
2246 23:47:16.064531 Enter into DVFS_PRE_config >>>>>
2247 23:47:16.076645 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2248 23:47:16.080530 Exit from DVFS_PRE_config <<<<<
2249 23:47:16.084120 Enter into PICG configuration >>>>
2250 23:47:16.087787 Exit from PICG configuration <<<<
2251 23:47:16.088247 [RX_INPUT] configuration >>>>>
2252 23:47:16.090463 [RX_INPUT] configuration <<<<<
2253 23:47:16.097130 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2254 23:47:16.100966 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2255 23:47:16.107313 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2256 23:47:16.113594 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2257 23:47:16.120540 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2258 23:47:16.127202 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2259 23:47:16.130891 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2260 23:47:16.134099 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2261 23:47:16.137069 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2262 23:47:16.144036 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2263 23:47:16.147316 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2264 23:47:16.150568 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 23:47:16.154209 ===================================
2266 23:47:16.157665 LPDDR4 DRAM CONFIGURATION
2267 23:47:16.161070 ===================================
2268 23:47:16.161479 EX_ROW_EN[0] = 0x0
2269 23:47:16.164426 EX_ROW_EN[1] = 0x0
2270 23:47:16.167165 LP4Y_EN = 0x0
2271 23:47:16.167729 WORK_FSP = 0x0
2272 23:47:16.170786 WL = 0x4
2273 23:47:16.171409 RL = 0x4
2274 23:47:16.174118 BL = 0x2
2275 23:47:16.174621 RPST = 0x0
2276 23:47:16.177986 RD_PRE = 0x0
2277 23:47:16.178394 WR_PRE = 0x1
2278 23:47:16.181423 WR_PST = 0x0
2279 23:47:16.182003 DBI_WR = 0x0
2280 23:47:16.184497 DBI_RD = 0x0
2281 23:47:16.184905 OTF = 0x1
2282 23:47:16.187423 ===================================
2283 23:47:16.190917 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2284 23:47:16.197414 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2285 23:47:16.201169 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2286 23:47:16.204324 ===================================
2287 23:47:16.207725 LPDDR4 DRAM CONFIGURATION
2288 23:47:16.211396 ===================================
2289 23:47:16.211808 EX_ROW_EN[0] = 0x10
2290 23:47:16.214512 EX_ROW_EN[1] = 0x0
2291 23:47:16.214919 LP4Y_EN = 0x0
2292 23:47:16.218290 WORK_FSP = 0x0
2293 23:47:16.218697 WL = 0x4
2294 23:47:16.221220 RL = 0x4
2295 23:47:16.221624 BL = 0x2
2296 23:47:16.224744 RPST = 0x0
2297 23:47:16.225316 RD_PRE = 0x0
2298 23:47:16.228099 WR_PRE = 0x1
2299 23:47:16.228534 WR_PST = 0x0
2300 23:47:16.231035 DBI_WR = 0x0
2301 23:47:16.231448 DBI_RD = 0x0
2302 23:47:16.234551 OTF = 0x1
2303 23:47:16.238924 ===================================
2304 23:47:16.245091 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2305 23:47:16.245532 ==
2306 23:47:16.247760 Dram Type= 6, Freq= 0, CH_0, rank 0
2307 23:47:16.251307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2308 23:47:16.251751 ==
2309 23:47:16.254390 [Duty_Offset_Calibration]
2310 23:47:16.254795 B0:2 B1:-1 CA:1
2311 23:47:16.255118
2312 23:47:16.258027 [DutyScan_Calibration_Flow] k_type=0
2313 23:47:16.267910
2314 23:47:16.268311 ==CLK 0==
2315 23:47:16.271171 Final CLK duty delay cell = -4
2316 23:47:16.274428 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2317 23:47:16.277540 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2318 23:47:16.281674 [-4] AVG Duty = 4953%(X100)
2319 23:47:16.282125
2320 23:47:16.284709 CH0 CLK Duty spec in!! Max-Min= 156%
2321 23:47:16.287895 [DutyScan_Calibration_Flow] ====Done====
2322 23:47:16.288409
2323 23:47:16.291303 [DutyScan_Calibration_Flow] k_type=1
2324 23:47:16.305665
2325 23:47:16.306067 ==DQS 0 ==
2326 23:47:16.308889 Final DQS duty delay cell = -4
2327 23:47:16.312825 [-4] MAX Duty = 5000%(X100), DQS PI = 48
2328 23:47:16.316035 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2329 23:47:16.319201 [-4] AVG Duty = 4938%(X100)
2330 23:47:16.319607
2331 23:47:16.319926 ==DQS 1 ==
2332 23:47:16.322486 Final DQS duty delay cell = -4
2333 23:47:16.325528 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2334 23:47:16.329378 [-4] MIN Duty = 5000%(X100), DQS PI = 50
2335 23:47:16.332398 [-4] AVG Duty = 5062%(X100)
2336 23:47:16.332872
2337 23:47:16.335942 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2338 23:47:16.336348
2339 23:47:16.339036 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2340 23:47:16.342386 [DutyScan_Calibration_Flow] ====Done====
2341 23:47:16.342790
2342 23:47:16.346019 [DutyScan_Calibration_Flow] k_type=3
2343 23:47:16.362435
2344 23:47:16.362598 ==DQM 0 ==
2345 23:47:16.365851 Final DQM duty delay cell = 0
2346 23:47:16.369443 [0] MAX Duty = 5000%(X100), DQS PI = 54
2347 23:47:16.372653 [0] MIN Duty = 4907%(X100), DQS PI = 2
2348 23:47:16.372775 [0] AVG Duty = 4953%(X100)
2349 23:47:16.376009
2350 23:47:16.376130 ==DQM 1 ==
2351 23:47:16.379156 Final DQM duty delay cell = 0
2352 23:47:16.382603 [0] MAX Duty = 5124%(X100), DQS PI = 62
2353 23:47:16.386375 [0] MIN Duty = 4969%(X100), DQS PI = 10
2354 23:47:16.386462 [0] AVG Duty = 5046%(X100)
2355 23:47:16.386526
2356 23:47:16.389919 CH0 DQM 0 Duty spec in!! Max-Min= 93%
2357 23:47:16.392425
2358 23:47:16.396331 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2359 23:47:16.399278 [DutyScan_Calibration_Flow] ====Done====
2360 23:47:16.399355
2361 23:47:16.402602 [DutyScan_Calibration_Flow] k_type=2
2362 23:47:16.418215
2363 23:47:16.418297 ==DQ 0 ==
2364 23:47:16.421756 Final DQ duty delay cell = -4
2365 23:47:16.425001 [-4] MAX Duty = 5031%(X100), DQS PI = 38
2366 23:47:16.428350 [-4] MIN Duty = 4876%(X100), DQS PI = 12
2367 23:47:16.431418 [-4] AVG Duty = 4953%(X100)
2368 23:47:16.431506
2369 23:47:16.431569 ==DQ 1 ==
2370 23:47:16.434669 Final DQ duty delay cell = 0
2371 23:47:16.438132 [0] MAX Duty = 5031%(X100), DQS PI = 18
2372 23:47:16.441601 [0] MIN Duty = 4907%(X100), DQS PI = 46
2373 23:47:16.441682 [0] AVG Duty = 4969%(X100)
2374 23:47:16.445081
2375 23:47:16.448737 CH0 DQ 0 Duty spec in!! Max-Min= 155%
2376 23:47:16.449280
2377 23:47:16.452008 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2378 23:47:16.455337 [DutyScan_Calibration_Flow] ====Done====
2379 23:47:16.455908 ==
2380 23:47:16.458668 Dram Type= 6, Freq= 0, CH_1, rank 0
2381 23:47:16.462066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2382 23:47:16.462749 ==
2383 23:47:16.465366 [Duty_Offset_Calibration]
2384 23:47:16.465980 B0:1 B1:1 CA:2
2385 23:47:16.466587
2386 23:47:16.468421 [DutyScan_Calibration_Flow] k_type=0
2387 23:47:16.478929
2388 23:47:16.479467 ==CLK 0==
2389 23:47:16.482252 Final CLK duty delay cell = 0
2390 23:47:16.485664 [0] MAX Duty = 5156%(X100), DQS PI = 24
2391 23:47:16.489104 [0] MIN Duty = 4938%(X100), DQS PI = 40
2392 23:47:16.489558 [0] AVG Duty = 5047%(X100)
2393 23:47:16.492266
2394 23:47:16.495289 CH1 CLK Duty spec in!! Max-Min= 218%
2395 23:47:16.498694 [DutyScan_Calibration_Flow] ====Done====
2396 23:47:16.499116
2397 23:47:16.502183 [DutyScan_Calibration_Flow] k_type=1
2398 23:47:16.517819
2399 23:47:16.518002 ==DQS 0 ==
2400 23:47:16.521477 Final DQS duty delay cell = 0
2401 23:47:16.524419 [0] MAX Duty = 5031%(X100), DQS PI = 18
2402 23:47:16.527734 [0] MIN Duty = 4875%(X100), DQS PI = 44
2403 23:47:16.527940 [0] AVG Duty = 4953%(X100)
2404 23:47:16.531377
2405 23:47:16.531521 ==DQS 1 ==
2406 23:47:16.534480 Final DQS duty delay cell = 0
2407 23:47:16.538265 [0] MAX Duty = 5062%(X100), DQS PI = 36
2408 23:47:16.540969 [0] MIN Duty = 4906%(X100), DQS PI = 16
2409 23:47:16.541109 [0] AVG Duty = 4984%(X100)
2410 23:47:16.544952
2411 23:47:16.547908 CH1 DQS 0 Duty spec in!! Max-Min= 156%
2412 23:47:16.548035
2413 23:47:16.551911 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2414 23:47:16.554825 [DutyScan_Calibration_Flow] ====Done====
2415 23:47:16.555035
2416 23:47:16.558397 [DutyScan_Calibration_Flow] k_type=3
2417 23:47:16.574468
2418 23:47:16.574737 ==DQM 0 ==
2419 23:47:16.578606 Final DQM duty delay cell = 0
2420 23:47:16.581302 [0] MAX Duty = 5093%(X100), DQS PI = 18
2421 23:47:16.584852 [0] MIN Duty = 4907%(X100), DQS PI = 48
2422 23:47:16.588064 [0] AVG Duty = 5000%(X100)
2423 23:47:16.588514
2424 23:47:16.588795 ==DQM 1 ==
2425 23:47:16.591629 Final DQM duty delay cell = 0
2426 23:47:16.594921 [0] MAX Duty = 5125%(X100), DQS PI = 0
2427 23:47:16.598228 [0] MIN Duty = 4938%(X100), DQS PI = 24
2428 23:47:16.598681 [0] AVG Duty = 5031%(X100)
2429 23:47:16.601878
2430 23:47:16.605024 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2431 23:47:16.605647
2432 23:47:16.608764 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2433 23:47:16.611886 [DutyScan_Calibration_Flow] ====Done====
2434 23:47:16.612451
2435 23:47:16.615366 [DutyScan_Calibration_Flow] k_type=2
2436 23:47:16.631346
2437 23:47:16.631897 ==DQ 0 ==
2438 23:47:16.634480 Final DQ duty delay cell = 0
2439 23:47:16.638103 [0] MAX Duty = 5124%(X100), DQS PI = 18
2440 23:47:16.641662 [0] MIN Duty = 4907%(X100), DQS PI = 50
2441 23:47:16.642114 [0] AVG Duty = 5015%(X100)
2442 23:47:16.642472
2443 23:47:16.644533 ==DQ 1 ==
2444 23:47:16.648334 Final DQ duty delay cell = 0
2445 23:47:16.651544 [0] MAX Duty = 5093%(X100), DQS PI = 10
2446 23:47:16.654507 [0] MIN Duty = 5031%(X100), DQS PI = 2
2447 23:47:16.654964 [0] AVG Duty = 5062%(X100)
2448 23:47:16.655325
2449 23:47:16.657803 CH1 DQ 0 Duty spec in!! Max-Min= 217%
2450 23:47:16.658259
2451 23:47:16.661634 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2452 23:47:16.668416 [DutyScan_Calibration_Flow] ====Done====
2453 23:47:16.672200 nWR fixed to 30
2454 23:47:16.672755 [ModeRegInit_LP4] CH0 RK0
2455 23:47:16.674540 [ModeRegInit_LP4] CH0 RK1
2456 23:47:16.677857 [ModeRegInit_LP4] CH1 RK0
2457 23:47:16.678309 [ModeRegInit_LP4] CH1 RK1
2458 23:47:16.681644 match AC timing 7
2459 23:47:16.684902 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2460 23:47:16.688366 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2461 23:47:16.694774 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2462 23:47:16.698177 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2463 23:47:16.705369 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2464 23:47:16.705926 ==
2465 23:47:16.708554 Dram Type= 6, Freq= 0, CH_0, rank 0
2466 23:47:16.712607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2467 23:47:16.713208 ==
2468 23:47:16.714950 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2469 23:47:16.721730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2470 23:47:16.731480 [CA 0] Center 40 (10~71) winsize 62
2471 23:47:16.734643 [CA 1] Center 39 (9~70) winsize 62
2472 23:47:16.738478 [CA 2] Center 36 (6~67) winsize 62
2473 23:47:16.741175 [CA 3] Center 35 (5~66) winsize 62
2474 23:47:16.744876 [CA 4] Center 34 (4~65) winsize 62
2475 23:47:16.748175 [CA 5] Center 34 (4~64) winsize 61
2476 23:47:16.748625
2477 23:47:16.751452 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2478 23:47:16.751997
2479 23:47:16.755064 [CATrainingPosCal] consider 1 rank data
2480 23:47:16.757716 u2DelayCellTimex100 = 270/100 ps
2481 23:47:16.761502 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2482 23:47:16.764558 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2483 23:47:16.771332 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2484 23:47:16.774392 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2485 23:47:16.777689 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2486 23:47:16.781694 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2487 23:47:16.782246
2488 23:47:16.784760 CA PerBit enable=1, Macro0, CA PI delay=34
2489 23:47:16.785358
2490 23:47:16.787909 [CBTSetCACLKResult] CA Dly = 34
2491 23:47:16.788457 CS Dly: 7 (0~38)
2492 23:47:16.788817 ==
2493 23:47:16.791462 Dram Type= 6, Freq= 0, CH_0, rank 1
2494 23:47:16.798194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 23:47:16.798644 ==
2496 23:47:16.801832 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2497 23:47:16.808072 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2498 23:47:16.817508 [CA 0] Center 39 (9~70) winsize 62
2499 23:47:16.820460 [CA 1] Center 40 (10~70) winsize 61
2500 23:47:16.823939 [CA 2] Center 36 (6~67) winsize 62
2501 23:47:16.827246 [CA 3] Center 35 (5~66) winsize 62
2502 23:47:16.831009 [CA 4] Center 34 (4~65) winsize 62
2503 23:47:16.834212 [CA 5] Center 34 (4~64) winsize 61
2504 23:47:16.834806
2505 23:47:16.837209 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2506 23:47:16.837731
2507 23:47:16.840795 [CATrainingPosCal] consider 2 rank data
2508 23:47:16.844294 u2DelayCellTimex100 = 270/100 ps
2509 23:47:16.847249 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2510 23:47:16.851366 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2511 23:47:16.857204 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2512 23:47:16.861233 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2513 23:47:16.863881 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2514 23:47:16.868092 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2515 23:47:16.868656
2516 23:47:16.870872 CA PerBit enable=1, Macro0, CA PI delay=34
2517 23:47:16.871326
2518 23:47:16.874052 [CBTSetCACLKResult] CA Dly = 34
2519 23:47:16.874503 CS Dly: 8 (0~41)
2520 23:47:16.874864
2521 23:47:16.877698 ----->DramcWriteLeveling(PI) begin...
2522 23:47:16.878256 ==
2523 23:47:16.880822 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 23:47:16.887745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 23:47:16.888320 ==
2526 23:47:16.891446 Write leveling (Byte 0): 32 => 32
2527 23:47:16.895164 Write leveling (Byte 1): 31 => 31
2528 23:47:16.895617 DramcWriteLeveling(PI) end<-----
2529 23:47:16.895980
2530 23:47:16.897680 ==
2531 23:47:16.901132 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 23:47:16.904463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2533 23:47:16.905058 ==
2534 23:47:16.908427 [Gating] SW mode calibration
2535 23:47:16.914774 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2536 23:47:16.918313 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2537 23:47:16.924727 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 23:47:16.927640 0 15 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2539 23:47:16.931264 0 15 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
2540 23:47:16.938123 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2541 23:47:16.940890 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 23:47:16.944423 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 23:47:16.947993 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 23:47:16.954611 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 23:47:16.958272 1 0 0 | B1->B0 | 3434 3232 | 1 1 | (1 0) (1 0)
2546 23:47:16.961751 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2547 23:47:16.968776 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2548 23:47:16.972183 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 23:47:16.975293 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 23:47:16.981719 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 23:47:16.985055 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 23:47:16.988421 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 23:47:16.995516 1 1 0 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
2554 23:47:16.998275 1 1 4 | B1->B0 | 3b3b 4444 | 1 0 | (1 1) (0 0)
2555 23:47:17.002545 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2556 23:47:17.005657 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 23:47:17.012051 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 23:47:17.015543 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 23:47:17.018880 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 23:47:17.025317 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 23:47:17.029079 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2562 23:47:17.032400 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2563 23:47:17.038591 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 23:47:17.042033 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 23:47:17.045702 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 23:47:17.052210 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 23:47:17.055624 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 23:47:17.059472 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 23:47:17.062223 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 23:47:17.069445 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 23:47:17.072958 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 23:47:17.076122 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 23:47:17.082467 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 23:47:17.085679 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 23:47:17.089359 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 23:47:17.096428 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 23:47:17.098948 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2578 23:47:17.102456 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2579 23:47:17.109276 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 23:47:17.109842 Total UI for P1: 0, mck2ui 16
2581 23:47:17.112906 best dqsien dly found for B0: ( 1, 4, 2)
2582 23:47:17.116053 Total UI for P1: 0, mck2ui 16
2583 23:47:17.119091 best dqsien dly found for B1: ( 1, 4, 4)
2584 23:47:17.122398 best DQS0 dly(MCK, UI, PI) = (1, 4, 2)
2585 23:47:17.129763 best DQS1 dly(MCK, UI, PI) = (1, 4, 4)
2586 23:47:17.130316
2587 23:47:17.132650 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 2)
2588 23:47:17.136520 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 4)
2589 23:47:17.139614 [Gating] SW calibration Done
2590 23:47:17.140137 ==
2591 23:47:17.142465 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 23:47:17.146063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 23:47:17.146521 ==
2594 23:47:17.146883 RX Vref Scan: 0
2595 23:47:17.147217
2596 23:47:17.149321 RX Vref 0 -> 0, step: 1
2597 23:47:17.149774
2598 23:47:17.153076 RX Delay -40 -> 252, step: 8
2599 23:47:17.156309 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2600 23:47:17.159340 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2601 23:47:17.163361 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2602 23:47:17.169702 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2603 23:47:17.173092 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2604 23:47:17.176638 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2605 23:47:17.180786 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2606 23:47:17.182914 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2607 23:47:17.186517 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2608 23:47:17.193382 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2609 23:47:17.196776 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2610 23:47:17.200333 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2611 23:47:17.203435 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2612 23:47:17.206681 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2613 23:47:17.213270 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2614 23:47:17.217269 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2615 23:47:17.217826 ==
2616 23:47:17.220324 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 23:47:17.223779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 23:47:17.224333 ==
2619 23:47:17.227561 DQS Delay:
2620 23:47:17.228112 DQS0 = 0, DQS1 = 0
2621 23:47:17.228474 DQM Delay:
2622 23:47:17.230443 DQM0 = 115, DQM1 = 107
2623 23:47:17.230892 DQ Delay:
2624 23:47:17.233923 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2625 23:47:17.236424 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2626 23:47:17.239928 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2627 23:47:17.243092 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2628 23:47:17.246509
2629 23:47:17.246958
2630 23:47:17.247314 ==
2631 23:47:17.250011 Dram Type= 6, Freq= 0, CH_0, rank 0
2632 23:47:17.253731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2633 23:47:17.254243 ==
2634 23:47:17.254914
2635 23:47:17.255422
2636 23:47:17.256619 TX Vref Scan disable
2637 23:47:17.257103 == TX Byte 0 ==
2638 23:47:17.263152 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2639 23:47:17.266796 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2640 23:47:17.267252 == TX Byte 1 ==
2641 23:47:17.273971 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2642 23:47:17.277002 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2643 23:47:17.277427 ==
2644 23:47:17.279935 Dram Type= 6, Freq= 0, CH_0, rank 0
2645 23:47:17.283536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2646 23:47:17.283965 ==
2647 23:47:17.295537 TX Vref=22, minBit 5, minWin=24, winSum=409
2648 23:47:17.299282 TX Vref=24, minBit 7, minWin=25, winSum=419
2649 23:47:17.302433 TX Vref=26, minBit 12, minWin=25, winSum=421
2650 23:47:17.305596 TX Vref=28, minBit 5, minWin=25, winSum=424
2651 23:47:17.309108 TX Vref=30, minBit 0, minWin=26, winSum=427
2652 23:47:17.312605 TX Vref=32, minBit 0, minWin=26, winSum=425
2653 23:47:17.318960 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 30
2654 23:47:17.319454
2655 23:47:17.322501 Final TX Range 1 Vref 30
2656 23:47:17.322910
2657 23:47:17.323307 ==
2658 23:47:17.325543 Dram Type= 6, Freq= 0, CH_0, rank 0
2659 23:47:17.329634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2660 23:47:17.330046 ==
2661 23:47:17.330481
2662 23:47:17.330851
2663 23:47:17.332707 TX Vref Scan disable
2664 23:47:17.336190 == TX Byte 0 ==
2665 23:47:17.339490 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2666 23:47:17.342780 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2667 23:47:17.346317 == TX Byte 1 ==
2668 23:47:17.349410 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2669 23:47:17.352741 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2670 23:47:17.353196
2671 23:47:17.356502 [DATLAT]
2672 23:47:17.357059 Freq=1200, CH0 RK0
2673 23:47:17.357403
2674 23:47:17.359742 DATLAT Default: 0xd
2675 23:47:17.360149 0, 0xFFFF, sum = 0
2676 23:47:17.362843 1, 0xFFFF, sum = 0
2677 23:47:17.363293 2, 0xFFFF, sum = 0
2678 23:47:17.366542 3, 0xFFFF, sum = 0
2679 23:47:17.367104 4, 0xFFFF, sum = 0
2680 23:47:17.369645 5, 0xFFFF, sum = 0
2681 23:47:17.370158 6, 0xFFFF, sum = 0
2682 23:47:17.373091 7, 0xFFFF, sum = 0
2683 23:47:17.373552 8, 0xFFFF, sum = 0
2684 23:47:17.376830 9, 0xFFFF, sum = 0
2685 23:47:17.377523 10, 0xFFFF, sum = 0
2686 23:47:17.379489 11, 0xFFFF, sum = 0
2687 23:47:17.379948 12, 0x0, sum = 1
2688 23:47:17.383072 13, 0x0, sum = 2
2689 23:47:17.383531 14, 0x0, sum = 3
2690 23:47:17.386683 15, 0x0, sum = 4
2691 23:47:17.387142 best_step = 13
2692 23:47:17.387501
2693 23:47:17.387834 ==
2694 23:47:17.389675 Dram Type= 6, Freq= 0, CH_0, rank 0
2695 23:47:17.396722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2696 23:47:17.397326 ==
2697 23:47:17.397693 RX Vref Scan: 1
2698 23:47:17.398026
2699 23:47:17.399986 Set Vref Range= 32 -> 127
2700 23:47:17.400440
2701 23:47:17.403352 RX Vref 32 -> 127, step: 1
2702 23:47:17.403908
2703 23:47:17.404271 RX Delay -21 -> 252, step: 4
2704 23:47:17.404610
2705 23:47:17.406759 Set Vref, RX VrefLevel [Byte0]: 32
2706 23:47:17.409632 [Byte1]: 32
2707 23:47:17.414180
2708 23:47:17.414733 Set Vref, RX VrefLevel [Byte0]: 33
2709 23:47:17.417879 [Byte1]: 33
2710 23:47:17.421808
2711 23:47:17.422263 Set Vref, RX VrefLevel [Byte0]: 34
2712 23:47:17.425085 [Byte1]: 34
2713 23:47:17.429928
2714 23:47:17.433378 Set Vref, RX VrefLevel [Byte0]: 35
2715 23:47:17.436688 [Byte1]: 35
2716 23:47:17.437281
2717 23:47:17.439772 Set Vref, RX VrefLevel [Byte0]: 36
2718 23:47:17.443172 [Byte1]: 36
2719 23:47:17.443735
2720 23:47:17.446742 Set Vref, RX VrefLevel [Byte0]: 37
2721 23:47:17.449833 [Byte1]: 37
2722 23:47:17.454116
2723 23:47:17.454667 Set Vref, RX VrefLevel [Byte0]: 38
2724 23:47:17.457069 [Byte1]: 38
2725 23:47:17.461987
2726 23:47:17.462538 Set Vref, RX VrefLevel [Byte0]: 39
2727 23:47:17.465085 [Byte1]: 39
2728 23:47:17.469444
2729 23:47:17.470004 Set Vref, RX VrefLevel [Byte0]: 40
2730 23:47:17.472965 [Byte1]: 40
2731 23:47:17.477588
2732 23:47:17.478143 Set Vref, RX VrefLevel [Byte0]: 41
2733 23:47:17.480588 [Byte1]: 41
2734 23:47:17.485427
2735 23:47:17.486000 Set Vref, RX VrefLevel [Byte0]: 42
2736 23:47:17.488896 [Byte1]: 42
2737 23:47:17.493168
2738 23:47:17.493617 Set Vref, RX VrefLevel [Byte0]: 43
2739 23:47:17.496738 [Byte1]: 43
2740 23:47:17.501518
2741 23:47:17.502078 Set Vref, RX VrefLevel [Byte0]: 44
2742 23:47:17.505010 [Byte1]: 44
2743 23:47:17.509493
2744 23:47:17.510054 Set Vref, RX VrefLevel [Byte0]: 45
2745 23:47:17.512534 [Byte1]: 45
2746 23:47:17.516932
2747 23:47:17.517518 Set Vref, RX VrefLevel [Byte0]: 46
2748 23:47:17.520257 [Byte1]: 46
2749 23:47:17.525137
2750 23:47:17.525706 Set Vref, RX VrefLevel [Byte0]: 47
2751 23:47:17.528522 [Byte1]: 47
2752 23:47:17.533343
2753 23:47:17.533894 Set Vref, RX VrefLevel [Byte0]: 48
2754 23:47:17.536243 [Byte1]: 48
2755 23:47:17.540892
2756 23:47:17.541700 Set Vref, RX VrefLevel [Byte0]: 49
2757 23:47:17.544669 [Byte1]: 49
2758 23:47:17.548819
2759 23:47:17.549431 Set Vref, RX VrefLevel [Byte0]: 50
2760 23:47:17.552333 [Byte1]: 50
2761 23:47:17.557340
2762 23:47:17.557888 Set Vref, RX VrefLevel [Byte0]: 51
2763 23:47:17.560401 [Byte1]: 51
2764 23:47:17.564405
2765 23:47:17.564858 Set Vref, RX VrefLevel [Byte0]: 52
2766 23:47:17.568217 [Byte1]: 52
2767 23:47:17.573021
2768 23:47:17.573593 Set Vref, RX VrefLevel [Byte0]: 53
2769 23:47:17.576168 [Byte1]: 53
2770 23:47:17.580961
2771 23:47:17.581553 Set Vref, RX VrefLevel [Byte0]: 54
2772 23:47:17.583656 [Byte1]: 54
2773 23:47:17.588334
2774 23:47:17.588969 Set Vref, RX VrefLevel [Byte0]: 55
2775 23:47:17.592099 [Byte1]: 55
2776 23:47:17.596170
2777 23:47:17.596626 Set Vref, RX VrefLevel [Byte0]: 56
2778 23:47:17.600124 [Byte1]: 56
2779 23:47:17.604598
2780 23:47:17.605199 Set Vref, RX VrefLevel [Byte0]: 57
2781 23:47:17.608238 [Byte1]: 57
2782 23:47:17.612381
2783 23:47:17.612949 Set Vref, RX VrefLevel [Byte0]: 58
2784 23:47:17.615895 [Byte1]: 58
2785 23:47:17.620173
2786 23:47:17.620722 Set Vref, RX VrefLevel [Byte0]: 59
2787 23:47:17.623495 [Byte1]: 59
2788 23:47:17.628751
2789 23:47:17.629351 Set Vref, RX VrefLevel [Byte0]: 60
2790 23:47:17.632107 [Byte1]: 60
2791 23:47:17.636347
2792 23:47:17.636897 Set Vref, RX VrefLevel [Byte0]: 61
2793 23:47:17.639159 [Byte1]: 61
2794 23:47:17.643863
2795 23:47:17.644316 Set Vref, RX VrefLevel [Byte0]: 62
2796 23:47:17.647474 [Byte1]: 62
2797 23:47:17.651808
2798 23:47:17.652358 Set Vref, RX VrefLevel [Byte0]: 63
2799 23:47:17.655489 [Byte1]: 63
2800 23:47:17.659733
2801 23:47:17.660284 Set Vref, RX VrefLevel [Byte0]: 64
2802 23:47:17.663464 [Byte1]: 64
2803 23:47:17.667743
2804 23:47:17.668291 Set Vref, RX VrefLevel [Byte0]: 65
2805 23:47:17.671055 [Byte1]: 65
2806 23:47:17.675832
2807 23:47:17.676383 Set Vref, RX VrefLevel [Byte0]: 66
2808 23:47:17.679064 [Byte1]: 66
2809 23:47:17.683596
2810 23:47:17.684153 Set Vref, RX VrefLevel [Byte0]: 67
2811 23:47:17.687563 [Byte1]: 67
2812 23:47:17.691719
2813 23:47:17.692273 Set Vref, RX VrefLevel [Byte0]: 68
2814 23:47:17.695161 [Byte1]: 68
2815 23:47:17.699855
2816 23:47:17.700407 Final RX Vref Byte 0 = 54 to rank0
2817 23:47:17.703028 Final RX Vref Byte 1 = 52 to rank0
2818 23:47:17.706218 Final RX Vref Byte 0 = 54 to rank1
2819 23:47:17.709657 Final RX Vref Byte 1 = 52 to rank1==
2820 23:47:17.713371 Dram Type= 6, Freq= 0, CH_0, rank 0
2821 23:47:17.719753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 23:47:17.720313 ==
2823 23:47:17.720677 DQS Delay:
2824 23:47:17.721057 DQS0 = 0, DQS1 = 0
2825 23:47:17.722895 DQM Delay:
2826 23:47:17.723344 DQM0 = 114, DQM1 = 104
2827 23:47:17.726638 DQ Delay:
2828 23:47:17.729510 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =112
2829 23:47:17.732561 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2830 23:47:17.736350 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2831 23:47:17.739457 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2832 23:47:17.739915
2833 23:47:17.740273
2834 23:47:17.746009 [DQSOSCAuto] RK0, (LSB)MR18= 0xfae9, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
2835 23:47:17.749503 CH0 RK0: MR19=303, MR18=FAE9
2836 23:47:17.756621 CH0_RK0: MR19=0x303, MR18=0xFAE9, DQSOSC=412, MR23=63, INC=38, DEC=25
2837 23:47:17.757209
2838 23:47:17.760251 ----->DramcWriteLeveling(PI) begin...
2839 23:47:17.760804 ==
2840 23:47:17.763038 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 23:47:17.766487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 23:47:17.767040 ==
2843 23:47:17.769603 Write leveling (Byte 0): 34 => 34
2844 23:47:17.772910 Write leveling (Byte 1): 27 => 27
2845 23:47:17.776344 DramcWriteLeveling(PI) end<-----
2846 23:47:17.776795
2847 23:47:17.777214 ==
2848 23:47:17.780211 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 23:47:17.783516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 23:47:17.784095 ==
2851 23:47:17.786346 [Gating] SW mode calibration
2852 23:47:17.793792 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2853 23:47:17.800026 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2854 23:47:17.803677 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2855 23:47:17.809970 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
2856 23:47:17.813786 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 23:47:17.816878 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 23:47:17.823440 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 23:47:17.826701 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 23:47:17.830231 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2861 23:47:17.833781 0 15 28 | B1->B0 | 3434 2323 | 1 1 | (1 1) (1 0)
2862 23:47:17.840174 1 0 0 | B1->B0 | 3131 2a2a | 0 0 | (1 0) (0 0)
2863 23:47:17.843228 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 23:47:17.847163 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 23:47:17.853879 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 23:47:17.857105 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 23:47:17.860725 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 23:47:17.867614 1 0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 1)
2869 23:47:17.870867 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2870 23:47:17.873933 1 1 0 | B1->B0 | 3838 4545 | 1 0 | (0 0) (0 0)
2871 23:47:17.877184 1 1 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
2872 23:47:17.884117 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 23:47:17.887184 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 23:47:17.891025 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 23:47:17.897382 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 23:47:17.900755 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2877 23:47:17.904517 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2878 23:47:17.910684 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2879 23:47:17.914155 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 23:47:17.917279 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 23:47:17.924609 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 23:47:17.927726 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 23:47:17.930409 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 23:47:17.937575 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 23:47:17.941042 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 23:47:17.944111 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 23:47:17.947495 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 23:47:17.954488 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 23:47:17.957528 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 23:47:17.961073 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 23:47:17.967973 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 23:47:17.971624 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 23:47:17.974495 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2894 23:47:17.981247 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2895 23:47:17.981799 Total UI for P1: 0, mck2ui 16
2896 23:47:17.988096 best dqsien dly found for B0: ( 1, 3, 28)
2897 23:47:17.991059 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 23:47:17.994530 Total UI for P1: 0, mck2ui 16
2899 23:47:17.997713 best dqsien dly found for B1: ( 1, 3, 30)
2900 23:47:18.001380 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2901 23:47:18.004518 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2902 23:47:18.005122
2903 23:47:18.008613 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2904 23:47:18.011573 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2905 23:47:18.014793 [Gating] SW calibration Done
2906 23:47:18.015253 ==
2907 23:47:18.017939 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 23:47:18.021808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 23:47:18.022267 ==
2910 23:47:18.024707 RX Vref Scan: 0
2911 23:47:18.025243
2912 23:47:18.028256 RX Vref 0 -> 0, step: 1
2913 23:47:18.028830
2914 23:47:18.029308 RX Delay -40 -> 252, step: 8
2915 23:47:18.035309 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2916 23:47:18.038218 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2917 23:47:18.041646 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2918 23:47:18.044609 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2919 23:47:18.048132 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2920 23:47:18.051735 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2921 23:47:18.058459 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2922 23:47:18.061706 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2923 23:47:18.065195 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2924 23:47:18.068501 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2925 23:47:18.071759 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2926 23:47:18.078627 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2927 23:47:18.081502 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2928 23:47:18.085153 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2929 23:47:18.088417 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2930 23:47:18.091707 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2931 23:47:18.094879 ==
2932 23:47:18.095335 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 23:47:18.101926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 23:47:18.102485 ==
2935 23:47:18.102853 DQS Delay:
2936 23:47:18.105012 DQS0 = 0, DQS1 = 0
2937 23:47:18.105471 DQM Delay:
2938 23:47:18.108321 DQM0 = 115, DQM1 = 106
2939 23:47:18.108903 DQ Delay:
2940 23:47:18.111431 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2941 23:47:18.115698 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2942 23:47:18.118348 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2943 23:47:18.122002 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2944 23:47:18.122438
2945 23:47:18.122759
2946 23:47:18.123062 ==
2947 23:47:18.125109 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 23:47:18.128537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 23:47:18.129101 ==
2950 23:47:18.131613
2951 23:47:18.132066
2952 23:47:18.132422 TX Vref Scan disable
2953 23:47:18.135549 == TX Byte 0 ==
2954 23:47:18.139284 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2955 23:47:18.142165 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2956 23:47:18.145265 == TX Byte 1 ==
2957 23:47:18.148691 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2958 23:47:18.151942 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2959 23:47:18.152395 ==
2960 23:47:18.155353 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 23:47:18.162776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 23:47:18.163332 ==
2963 23:47:18.173064 TX Vref=22, minBit 0, minWin=25, winSum=423
2964 23:47:18.177035 TX Vref=24, minBit 1, minWin=25, winSum=424
2965 23:47:18.180012 TX Vref=26, minBit 1, minWin=26, winSum=432
2966 23:47:18.183410 TX Vref=28, minBit 1, minWin=26, winSum=434
2967 23:47:18.186428 TX Vref=30, minBit 0, minWin=26, winSum=439
2968 23:47:18.190313 TX Vref=32, minBit 0, minWin=27, winSum=436
2969 23:47:18.196646 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 32
2970 23:47:18.197224
2971 23:47:18.199871 Final TX Range 1 Vref 32
2972 23:47:18.200427
2973 23:47:18.200790 ==
2974 23:47:18.203160 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 23:47:18.206993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 23:47:18.207457 ==
2977 23:47:18.207826
2978 23:47:18.208164
2979 23:47:18.210386 TX Vref Scan disable
2980 23:47:18.213841 == TX Byte 0 ==
2981 23:47:18.217054 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2982 23:47:18.220177 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2983 23:47:18.223507 == TX Byte 1 ==
2984 23:47:18.227544 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2985 23:47:18.230146 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2986 23:47:18.230624
2987 23:47:18.233482 [DATLAT]
2988 23:47:18.233942 Freq=1200, CH0 RK1
2989 23:47:18.234455
2990 23:47:18.236721 DATLAT Default: 0xd
2991 23:47:18.237294 0, 0xFFFF, sum = 0
2992 23:47:18.240316 1, 0xFFFF, sum = 0
2993 23:47:18.240778 2, 0xFFFF, sum = 0
2994 23:47:18.243820 3, 0xFFFF, sum = 0
2995 23:47:18.244342 4, 0xFFFF, sum = 0
2996 23:47:18.247072 5, 0xFFFF, sum = 0
2997 23:47:18.247538 6, 0xFFFF, sum = 0
2998 23:47:18.250193 7, 0xFFFF, sum = 0
2999 23:47:18.250657 8, 0xFFFF, sum = 0
3000 23:47:18.254018 9, 0xFFFF, sum = 0
3001 23:47:18.254745 10, 0xFFFF, sum = 0
3002 23:47:18.256707 11, 0xFFFF, sum = 0
3003 23:47:18.257382 12, 0x0, sum = 1
3004 23:47:18.260602 13, 0x0, sum = 2
3005 23:47:18.261202 14, 0x0, sum = 3
3006 23:47:18.263285 15, 0x0, sum = 4
3007 23:47:18.263702 best_step = 13
3008 23:47:18.264024
3009 23:47:18.264330 ==
3010 23:47:18.267162 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 23:47:18.273491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 23:47:18.273904 ==
3013 23:47:18.274246 RX Vref Scan: 0
3014 23:47:18.274553
3015 23:47:18.277541 RX Vref 0 -> 0, step: 1
3016 23:47:18.277967
3017 23:47:18.280288 RX Delay -21 -> 252, step: 4
3018 23:47:18.283752 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3019 23:47:18.287111 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3020 23:47:18.293541 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3021 23:47:18.296959 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3022 23:47:18.300149 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3023 23:47:18.304003 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3024 23:47:18.307189 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3025 23:47:18.310133 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3026 23:47:18.317145 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3027 23:47:18.320665 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3028 23:47:18.323858 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3029 23:47:18.327005 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3030 23:47:18.330592 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3031 23:47:18.337518 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3032 23:47:18.340279 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3033 23:47:18.344346 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3034 23:47:18.344763 ==
3035 23:47:18.347212 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 23:47:18.350436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 23:47:18.350857 ==
3038 23:47:18.353754 DQS Delay:
3039 23:47:18.354225 DQS0 = 0, DQS1 = 0
3040 23:47:18.354756 DQM Delay:
3041 23:47:18.357461 DQM0 = 114, DQM1 = 105
3042 23:47:18.357925 DQ Delay:
3043 23:47:18.360491 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3044 23:47:18.364130 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3045 23:47:18.367695 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
3046 23:47:18.374348 DQ12 =110, DQ13 =110, DQ14 =118, DQ15 =114
3047 23:47:18.374815
3048 23:47:18.375186
3049 23:47:18.381012 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3050 23:47:18.384365 CH0 RK1: MR19=403, MR18=2F4
3051 23:47:18.390944 CH0_RK1: MR19=0x403, MR18=0x2F4, DQSOSC=409, MR23=63, INC=39, DEC=26
3052 23:47:18.394484 [RxdqsGatingPostProcess] freq 1200
3053 23:47:18.397953 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3054 23:47:18.400777 best DQS0 dly(2T, 0.5T) = (0, 12)
3055 23:47:18.404247 best DQS1 dly(2T, 0.5T) = (0, 12)
3056 23:47:18.407510 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3057 23:47:18.410750 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3058 23:47:18.414314 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 23:47:18.417913 best DQS1 dly(2T, 0.5T) = (0, 11)
3060 23:47:18.421075 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 23:47:18.424224 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3062 23:47:18.427456 Pre-setting of DQS Precalculation
3063 23:47:18.431118 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3064 23:47:18.431708 ==
3065 23:47:18.434305 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 23:47:18.437776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 23:47:18.438190 ==
3068 23:47:18.444308 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3069 23:47:18.451026 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3070 23:47:18.458728 [CA 0] Center 38 (8~68) winsize 61
3071 23:47:18.462466 [CA 1] Center 38 (8~68) winsize 61
3072 23:47:18.465737 [CA 2] Center 35 (5~65) winsize 61
3073 23:47:18.468851 [CA 3] Center 34 (4~65) winsize 62
3074 23:47:18.472261 [CA 4] Center 34 (4~65) winsize 62
3075 23:47:18.475286 [CA 5] Center 33 (3~64) winsize 62
3076 23:47:18.475701
3077 23:47:18.478803 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3078 23:47:18.479211
3079 23:47:18.482316 [CATrainingPosCal] consider 1 rank data
3080 23:47:18.485348 u2DelayCellTimex100 = 270/100 ps
3081 23:47:18.489073 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3082 23:47:18.491896 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3083 23:47:18.499122 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3084 23:47:18.501929 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3085 23:47:18.505615 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3086 23:47:18.509031 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3087 23:47:18.509445
3088 23:47:18.512558 CA PerBit enable=1, Macro0, CA PI delay=33
3089 23:47:18.512967
3090 23:47:18.515721 [CBTSetCACLKResult] CA Dly = 33
3091 23:47:18.516129 CS Dly: 6 (0~37)
3092 23:47:18.516454 ==
3093 23:47:18.518575 Dram Type= 6, Freq= 0, CH_1, rank 1
3094 23:47:18.525489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 23:47:18.525900 ==
3096 23:47:18.528908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3097 23:47:18.535159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3098 23:47:18.544472 [CA 0] Center 38 (8~68) winsize 61
3099 23:47:18.547681 [CA 1] Center 38 (8~68) winsize 61
3100 23:47:18.551212 [CA 2] Center 34 (4~65) winsize 62
3101 23:47:18.554193 [CA 3] Center 34 (3~65) winsize 63
3102 23:47:18.557907 [CA 4] Center 34 (4~65) winsize 62
3103 23:47:18.561017 [CA 5] Center 33 (3~63) winsize 61
3104 23:47:18.561242
3105 23:47:18.564026 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3106 23:47:18.564106
3107 23:47:18.567285 [CATrainingPosCal] consider 2 rank data
3108 23:47:18.570788 u2DelayCellTimex100 = 270/100 ps
3109 23:47:18.574129 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3110 23:47:18.577351 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3111 23:47:18.583964 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3112 23:47:18.587419 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3113 23:47:18.590710 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3114 23:47:18.594153 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3115 23:47:18.594255
3116 23:47:18.597355 CA PerBit enable=1, Macro0, CA PI delay=33
3117 23:47:18.597436
3118 23:47:18.600850 [CBTSetCACLKResult] CA Dly = 33
3119 23:47:18.600956 CS Dly: 7 (0~40)
3120 23:47:18.601066
3121 23:47:18.604253 ----->DramcWriteLeveling(PI) begin...
3122 23:47:18.604340 ==
3123 23:47:18.607837 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 23:47:18.614506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 23:47:18.614681 ==
3126 23:47:18.617878 Write leveling (Byte 0): 28 => 28
3127 23:47:18.621179 Write leveling (Byte 1): 28 => 28
3128 23:47:18.621299 DramcWriteLeveling(PI) end<-----
3129 23:47:18.621394
3130 23:47:18.624724 ==
3131 23:47:18.627529 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 23:47:18.630998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 23:47:18.631150 ==
3134 23:47:18.634454 [Gating] SW mode calibration
3135 23:47:18.641585 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3136 23:47:18.644875 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3137 23:47:18.650999 0 15 0 | B1->B0 | 2828 2323 | 1 0 | (0 0) (0 0)
3138 23:47:18.654376 0 15 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3139 23:47:18.658037 0 15 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
3140 23:47:18.661199 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 23:47:18.668048 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 23:47:18.671782 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 23:47:18.674531 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 23:47:18.681842 0 15 28 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
3145 23:47:18.684945 1 0 0 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 0)
3146 23:47:18.687994 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 23:47:18.695138 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 23:47:18.698354 1 0 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3149 23:47:18.701821 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3150 23:47:18.708744 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 23:47:18.712301 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3152 23:47:18.716000 1 0 28 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
3153 23:47:18.721861 1 1 0 | B1->B0 | 4141 2c2c | 0 0 | (0 0) (0 0)
3154 23:47:18.725095 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 23:47:18.728854 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 23:47:18.732050 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 23:47:18.739020 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 23:47:18.742424 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 23:47:18.745737 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 23:47:18.752514 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3161 23:47:18.755742 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3162 23:47:18.759074 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 23:47:18.765797 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 23:47:18.769014 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 23:47:18.772423 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 23:47:18.779051 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 23:47:18.782381 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 23:47:18.786159 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 23:47:18.794237 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 23:47:18.795886 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 23:47:18.799166 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 23:47:18.802279 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 23:47:18.809211 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 23:47:18.813055 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 23:47:18.815930 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 23:47:18.822805 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3177 23:47:18.825896 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 23:47:18.829394 Total UI for P1: 0, mck2ui 16
3179 23:47:18.832898 best dqsien dly found for B0: ( 1, 3, 28)
3180 23:47:18.836332 Total UI for P1: 0, mck2ui 16
3181 23:47:18.839532 best dqsien dly found for B1: ( 1, 3, 30)
3182 23:47:18.843541 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3183 23:47:18.845942 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3184 23:47:18.846357
3185 23:47:18.849037 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3186 23:47:18.852713 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3187 23:47:18.856837 [Gating] SW calibration Done
3188 23:47:18.857403 ==
3189 23:47:18.859600 Dram Type= 6, Freq= 0, CH_1, rank 0
3190 23:47:18.863404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3191 23:47:18.863921 ==
3192 23:47:18.866564 RX Vref Scan: 0
3193 23:47:18.867076
3194 23:47:18.869640 RX Vref 0 -> 0, step: 1
3195 23:47:18.870047
3196 23:47:18.870371 RX Delay -40 -> 252, step: 8
3197 23:47:18.876523 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3198 23:47:18.880181 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3199 23:47:18.883164 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3200 23:47:18.886926 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3201 23:47:18.890197 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3202 23:47:18.896662 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3203 23:47:18.899910 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3204 23:47:18.903870 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3205 23:47:18.906548 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3206 23:47:18.910072 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3207 23:47:18.913708 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3208 23:47:18.920015 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3209 23:47:18.923059 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3210 23:47:18.926581 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3211 23:47:18.929820 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3212 23:47:18.933313 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3213 23:47:18.936256 ==
3214 23:47:18.939999 Dram Type= 6, Freq= 0, CH_1, rank 0
3215 23:47:18.943124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3216 23:47:18.943587 ==
3217 23:47:18.943953 DQS Delay:
3218 23:47:18.946244 DQS0 = 0, DQS1 = 0
3219 23:47:18.946654 DQM Delay:
3220 23:47:18.949940 DQM0 = 116, DQM1 = 109
3221 23:47:18.950463 DQ Delay:
3222 23:47:18.953109 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3223 23:47:18.956613 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3224 23:47:18.959579 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =107
3225 23:47:18.963055 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =115
3226 23:47:18.963440
3227 23:47:18.963789
3228 23:47:18.964107 ==
3229 23:47:18.966554 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 23:47:18.973533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 23:47:18.974008 ==
3232 23:47:18.974351
3233 23:47:18.974651
3234 23:47:18.974936 TX Vref Scan disable
3235 23:47:18.976553 == TX Byte 0 ==
3236 23:47:18.980200 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3237 23:47:18.983531 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3238 23:47:18.987063 == TX Byte 1 ==
3239 23:47:18.990210 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3240 23:47:18.993566 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3241 23:47:18.993974 ==
3242 23:47:18.996854 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 23:47:19.003634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 23:47:19.004082 ==
3245 23:47:19.014315 TX Vref=22, minBit 2, minWin=25, winSum=417
3246 23:47:19.017591 TX Vref=24, minBit 2, minWin=25, winSum=419
3247 23:47:19.020738 TX Vref=26, minBit 0, minWin=26, winSum=430
3248 23:47:19.024211 TX Vref=28, minBit 2, minWin=25, winSum=429
3249 23:47:19.027329 TX Vref=30, minBit 1, minWin=26, winSum=432
3250 23:47:19.030835 TX Vref=32, minBit 1, minWin=26, winSum=429
3251 23:47:19.037124 [TxChooseVref] Worse bit 1, Min win 26, Win sum 432, Final Vref 30
3252 23:47:19.037198
3253 23:47:19.040594 Final TX Range 1 Vref 30
3254 23:47:19.040665
3255 23:47:19.040724 ==
3256 23:47:19.043974 Dram Type= 6, Freq= 0, CH_1, rank 0
3257 23:47:19.047297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3258 23:47:19.047364 ==
3259 23:47:19.047425
3260 23:47:19.047486
3261 23:47:19.050635 TX Vref Scan disable
3262 23:47:19.054546 == TX Byte 0 ==
3263 23:47:19.057604 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3264 23:47:19.060693 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3265 23:47:19.064430 == TX Byte 1 ==
3266 23:47:19.067794 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3267 23:47:19.071139 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3268 23:47:19.071207
3269 23:47:19.074688 [DATLAT]
3270 23:47:19.074843 Freq=1200, CH1 RK0
3271 23:47:19.074916
3272 23:47:19.077811 DATLAT Default: 0xd
3273 23:47:19.077943 0, 0xFFFF, sum = 0
3274 23:47:19.080944 1, 0xFFFF, sum = 0
3275 23:47:19.081093 2, 0xFFFF, sum = 0
3276 23:47:19.084265 3, 0xFFFF, sum = 0
3277 23:47:19.084413 4, 0xFFFF, sum = 0
3278 23:47:19.087796 5, 0xFFFF, sum = 0
3279 23:47:19.087946 6, 0xFFFF, sum = 0
3280 23:47:19.091100 7, 0xFFFF, sum = 0
3281 23:47:19.091271 8, 0xFFFF, sum = 0
3282 23:47:19.094383 9, 0xFFFF, sum = 0
3283 23:47:19.094585 10, 0xFFFF, sum = 0
3284 23:47:19.098491 11, 0xFFFF, sum = 0
3285 23:47:19.098709 12, 0x0, sum = 1
3286 23:47:19.101263 13, 0x0, sum = 2
3287 23:47:19.101459 14, 0x0, sum = 3
3288 23:47:19.104722 15, 0x0, sum = 4
3289 23:47:19.104903 best_step = 13
3290 23:47:19.105062
3291 23:47:19.105196 ==
3292 23:47:19.108319 Dram Type= 6, Freq= 0, CH_1, rank 0
3293 23:47:19.114713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3294 23:47:19.114796 ==
3295 23:47:19.114860 RX Vref Scan: 1
3296 23:47:19.114919
3297 23:47:19.117956 Set Vref Range= 32 -> 127
3298 23:47:19.118041
3299 23:47:19.120995 RX Vref 32 -> 127, step: 1
3300 23:47:19.121084
3301 23:47:19.121170 RX Delay -21 -> 252, step: 4
3302 23:47:19.121239
3303 23:47:19.124940 Set Vref, RX VrefLevel [Byte0]: 32
3304 23:47:19.128172 [Byte1]: 32
3305 23:47:19.132659
3306 23:47:19.133121 Set Vref, RX VrefLevel [Byte0]: 33
3307 23:47:19.135884 [Byte1]: 33
3308 23:47:19.140407
3309 23:47:19.140810 Set Vref, RX VrefLevel [Byte0]: 34
3310 23:47:19.143501 [Byte1]: 34
3311 23:47:19.148588
3312 23:47:19.149038 Set Vref, RX VrefLevel [Byte0]: 35
3313 23:47:19.151924 [Byte1]: 35
3314 23:47:19.156386
3315 23:47:19.156787 Set Vref, RX VrefLevel [Byte0]: 36
3316 23:47:19.159619 [Byte1]: 36
3317 23:47:19.164319
3318 23:47:19.164721 Set Vref, RX VrefLevel [Byte0]: 37
3319 23:47:19.167827 [Byte1]: 37
3320 23:47:19.171781
3321 23:47:19.172210 Set Vref, RX VrefLevel [Byte0]: 38
3322 23:47:19.175501 [Byte1]: 38
3323 23:47:19.179776
3324 23:47:19.180204 Set Vref, RX VrefLevel [Byte0]: 39
3325 23:47:19.183413 [Byte1]: 39
3326 23:47:19.188832
3327 23:47:19.189273 Set Vref, RX VrefLevel [Byte0]: 40
3328 23:47:19.191520 [Byte1]: 40
3329 23:47:19.195766
3330 23:47:19.196225 Set Vref, RX VrefLevel [Byte0]: 41
3331 23:47:19.199164 [Byte1]: 41
3332 23:47:19.203773
3333 23:47:19.204206 Set Vref, RX VrefLevel [Byte0]: 42
3334 23:47:19.207235 [Byte1]: 42
3335 23:47:19.212096
3336 23:47:19.212566 Set Vref, RX VrefLevel [Byte0]: 43
3337 23:47:19.214831 [Byte1]: 43
3338 23:47:19.219945
3339 23:47:19.220385 Set Vref, RX VrefLevel [Byte0]: 44
3340 23:47:19.223172 [Byte1]: 44
3341 23:47:19.227540
3342 23:47:19.227942 Set Vref, RX VrefLevel [Byte0]: 45
3343 23:47:19.231116 [Byte1]: 45
3344 23:47:19.235679
3345 23:47:19.236082 Set Vref, RX VrefLevel [Byte0]: 46
3346 23:47:19.238836 [Byte1]: 46
3347 23:47:19.243348
3348 23:47:19.243764 Set Vref, RX VrefLevel [Byte0]: 47
3349 23:47:19.247033 [Byte1]: 47
3350 23:47:19.251581
3351 23:47:19.252016 Set Vref, RX VrefLevel [Byte0]: 48
3352 23:47:19.254648 [Byte1]: 48
3353 23:47:19.259247
3354 23:47:19.259697 Set Vref, RX VrefLevel [Byte0]: 49
3355 23:47:19.262779 [Byte1]: 49
3356 23:47:19.267423
3357 23:47:19.267928 Set Vref, RX VrefLevel [Byte0]: 50
3358 23:47:19.270748 [Byte1]: 50
3359 23:47:19.275557
3360 23:47:19.276087 Set Vref, RX VrefLevel [Byte0]: 51
3361 23:47:19.278557 [Byte1]: 51
3362 23:47:19.283057
3363 23:47:19.283464 Set Vref, RX VrefLevel [Byte0]: 52
3364 23:47:19.286678 [Byte1]: 52
3365 23:47:19.291074
3366 23:47:19.291481 Set Vref, RX VrefLevel [Byte0]: 53
3367 23:47:19.294159 [Byte1]: 53
3368 23:47:19.298873
3369 23:47:19.299283 Set Vref, RX VrefLevel [Byte0]: 54
3370 23:47:19.302588 [Byte1]: 54
3371 23:47:19.306817
3372 23:47:19.307223 Set Vref, RX VrefLevel [Byte0]: 55
3373 23:47:19.310803 [Byte1]: 55
3374 23:47:19.314924
3375 23:47:19.315462 Set Vref, RX VrefLevel [Byte0]: 56
3376 23:47:19.318181 [Byte1]: 56
3377 23:47:19.322530
3378 23:47:19.322960 Set Vref, RX VrefLevel [Byte0]: 57
3379 23:47:19.325513 [Byte1]: 57
3380 23:47:19.331082
3381 23:47:19.331610 Set Vref, RX VrefLevel [Byte0]: 58
3382 23:47:19.334331 [Byte1]: 58
3383 23:47:19.338586
3384 23:47:19.339026 Set Vref, RX VrefLevel [Byte0]: 59
3385 23:47:19.341896 [Byte1]: 59
3386 23:47:19.346739
3387 23:47:19.347152 Set Vref, RX VrefLevel [Byte0]: 60
3388 23:47:19.349576 [Byte1]: 60
3389 23:47:19.354892
3390 23:47:19.355431 Set Vref, RX VrefLevel [Byte0]: 61
3391 23:47:19.357390 [Byte1]: 61
3392 23:47:19.361942
3393 23:47:19.362436 Set Vref, RX VrefLevel [Byte0]: 62
3394 23:47:19.365536 [Byte1]: 62
3395 23:47:19.370206
3396 23:47:19.370618 Set Vref, RX VrefLevel [Byte0]: 63
3397 23:47:19.373087 [Byte1]: 63
3398 23:47:19.378127
3399 23:47:19.378538 Set Vref, RX VrefLevel [Byte0]: 64
3400 23:47:19.381162 [Byte1]: 64
3401 23:47:19.386010
3402 23:47:19.386419 Set Vref, RX VrefLevel [Byte0]: 65
3403 23:47:19.389361 [Byte1]: 65
3404 23:47:19.394231
3405 23:47:19.394642 Set Vref, RX VrefLevel [Byte0]: 66
3406 23:47:19.397324 [Byte1]: 66
3407 23:47:19.402211
3408 23:47:19.402718 Set Vref, RX VrefLevel [Byte0]: 67
3409 23:47:19.405223 [Byte1]: 67
3410 23:47:19.410014
3411 23:47:19.410513 Set Vref, RX VrefLevel [Byte0]: 68
3412 23:47:19.413213 [Byte1]: 68
3413 23:47:19.418273
3414 23:47:19.418824 Set Vref, RX VrefLevel [Byte0]: 69
3415 23:47:19.421401 [Byte1]: 69
3416 23:47:19.425685
3417 23:47:19.426250 Set Vref, RX VrefLevel [Byte0]: 70
3418 23:47:19.429272 [Byte1]: 70
3419 23:47:19.433704
3420 23:47:19.434261 Set Vref, RX VrefLevel [Byte0]: 71
3421 23:47:19.437060 [Byte1]: 71
3422 23:47:19.441701
3423 23:47:19.442154 Final RX Vref Byte 0 = 54 to rank0
3424 23:47:19.445458 Final RX Vref Byte 1 = 53 to rank0
3425 23:47:19.448797 Final RX Vref Byte 0 = 54 to rank1
3426 23:47:19.451859 Final RX Vref Byte 1 = 53 to rank1==
3427 23:47:19.455592 Dram Type= 6, Freq= 0, CH_1, rank 0
3428 23:47:19.458884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 23:47:19.462128 ==
3430 23:47:19.462582 DQS Delay:
3431 23:47:19.462945 DQS0 = 0, DQS1 = 0
3432 23:47:19.465643 DQM Delay:
3433 23:47:19.466189 DQM0 = 115, DQM1 = 109
3434 23:47:19.468403 DQ Delay:
3435 23:47:19.471993 DQ0 =116, DQ1 =108, DQ2 =104, DQ3 =112
3436 23:47:19.474928 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =112
3437 23:47:19.478587 DQ8 =96, DQ9 =98, DQ10 =112, DQ11 =106
3438 23:47:19.481764 DQ12 =116, DQ13 =116, DQ14 =116, DQ15 =114
3439 23:47:19.482220
3440 23:47:19.482582
3441 23:47:19.488266 [DQSOSCAuto] RK0, (LSB)MR18= 0xfde2, (MSB)MR19= 0x303, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
3442 23:47:19.491851 CH1 RK0: MR19=303, MR18=FDE2
3443 23:47:19.498785 CH1_RK0: MR19=0x303, MR18=0xFDE2, DQSOSC=411, MR23=63, INC=38, DEC=25
3444 23:47:19.499335
3445 23:47:19.501731 ----->DramcWriteLeveling(PI) begin...
3446 23:47:19.502188 ==
3447 23:47:19.505354 Dram Type= 6, Freq= 0, CH_1, rank 1
3448 23:47:19.508766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3449 23:47:19.509387 ==
3450 23:47:19.512016 Write leveling (Byte 0): 26 => 26
3451 23:47:19.515333 Write leveling (Byte 1): 28 => 28
3452 23:47:19.518443 DramcWriteLeveling(PI) end<-----
3453 23:47:19.518894
3454 23:47:19.519255 ==
3455 23:47:19.522322 Dram Type= 6, Freq= 0, CH_1, rank 1
3456 23:47:19.525675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3457 23:47:19.526140 ==
3458 23:47:19.529145 [Gating] SW mode calibration
3459 23:47:19.535460 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3460 23:47:19.542249 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3461 23:47:19.545488 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3462 23:47:19.552344 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 23:47:19.555407 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 23:47:19.559123 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 23:47:19.562135 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 23:47:19.568875 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3467 23:47:19.572424 0 15 24 | B1->B0 | 3535 2626 | 0 0 | (0 0) (0 0)
3468 23:47:19.575272 0 15 28 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
3469 23:47:19.582081 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 23:47:19.585740 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 23:47:19.588885 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 23:47:19.595684 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 23:47:19.598930 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 23:47:19.602949 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3475 23:47:19.608871 1 0 24 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
3476 23:47:19.612329 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 23:47:19.615961 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 23:47:19.622314 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 23:47:19.625641 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 23:47:19.629043 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 23:47:19.635451 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 23:47:19.639147 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 23:47:19.642693 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3484 23:47:19.648662 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3485 23:47:19.652289 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 23:47:19.655303 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 23:47:19.658963 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 23:47:19.665213 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 23:47:19.668562 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 23:47:19.672092 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 23:47:19.678925 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 23:47:19.682359 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 23:47:19.685354 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 23:47:19.691838 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 23:47:19.695463 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 23:47:19.698389 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 23:47:19.705225 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 23:47:19.708356 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3499 23:47:19.711717 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3500 23:47:19.718452 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3501 23:47:19.718870 Total UI for P1: 0, mck2ui 16
3502 23:47:19.725474 best dqsien dly found for B0: ( 1, 3, 22)
3503 23:47:19.728617 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 23:47:19.731860 Total UI for P1: 0, mck2ui 16
3505 23:47:19.735278 best dqsien dly found for B1: ( 1, 3, 28)
3506 23:47:19.738265 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3507 23:47:19.741837 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3508 23:47:19.742270
3509 23:47:19.745176 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3510 23:47:19.748512 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3511 23:47:19.751793 [Gating] SW calibration Done
3512 23:47:19.752226 ==
3513 23:47:19.755975 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 23:47:19.758693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 23:47:19.761920 ==
3516 23:47:19.762352 RX Vref Scan: 0
3517 23:47:19.762739
3518 23:47:19.765232 RX Vref 0 -> 0, step: 1
3519 23:47:19.765725
3520 23:47:19.766066 RX Delay -40 -> 252, step: 8
3521 23:47:19.771836 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3522 23:47:19.775145 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3523 23:47:19.778895 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3524 23:47:19.782295 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3525 23:47:19.785055 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3526 23:47:19.792022 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3527 23:47:19.795613 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3528 23:47:19.798451 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3529 23:47:19.802100 iDelay=200, Bit 8, Center 103 (32 ~ 175) 144
3530 23:47:19.805027 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3531 23:47:19.811978 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3532 23:47:19.815322 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3533 23:47:19.819100 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3534 23:47:19.822056 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3535 23:47:19.825492 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3536 23:47:19.831883 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3537 23:47:19.832300 ==
3538 23:47:19.835342 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 23:47:19.838713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 23:47:19.839132 ==
3541 23:47:19.839462 DQS Delay:
3542 23:47:19.842004 DQS0 = 0, DQS1 = 0
3543 23:47:19.842417 DQM Delay:
3544 23:47:19.845530 DQM0 = 113, DQM1 = 111
3545 23:47:19.845946 DQ Delay:
3546 23:47:19.848390 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =111
3547 23:47:19.851802 DQ4 =111, DQ5 =127, DQ6 =119, DQ7 =111
3548 23:47:19.855335 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3549 23:47:19.859225 DQ12 =115, DQ13 =123, DQ14 =119, DQ15 =119
3550 23:47:19.859754
3551 23:47:19.860127
3552 23:47:19.861822 ==
3553 23:47:19.865011 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 23:47:19.868962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 23:47:19.869451 ==
3556 23:47:19.869788
3557 23:47:19.870142
3558 23:47:19.871982 TX Vref Scan disable
3559 23:47:19.872434 == TX Byte 0 ==
3560 23:47:19.875309 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3561 23:47:19.882489 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3562 23:47:19.882996 == TX Byte 1 ==
3563 23:47:19.885134 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3564 23:47:19.891995 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3565 23:47:19.892550 ==
3566 23:47:19.895249 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 23:47:19.898528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 23:47:19.898974 ==
3569 23:47:19.910758 TX Vref=22, minBit 0, minWin=25, winSum=417
3570 23:47:19.914255 TX Vref=24, minBit 1, minWin=25, winSum=423
3571 23:47:19.917286 TX Vref=26, minBit 0, minWin=26, winSum=429
3572 23:47:19.920404 TX Vref=28, minBit 2, minWin=26, winSum=433
3573 23:47:19.923445 TX Vref=30, minBit 1, minWin=26, winSum=433
3574 23:47:19.926843 TX Vref=32, minBit 4, minWin=26, winSum=436
3575 23:47:19.933629 [TxChooseVref] Worse bit 4, Min win 26, Win sum 436, Final Vref 32
3576 23:47:19.933711
3577 23:47:19.937331 Final TX Range 1 Vref 32
3578 23:47:19.937418
3579 23:47:19.937487 ==
3580 23:47:19.940292 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 23:47:19.943885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 23:47:19.943980 ==
3583 23:47:19.944054
3584 23:47:19.947054
3585 23:47:19.947155 TX Vref Scan disable
3586 23:47:19.950095 == TX Byte 0 ==
3587 23:47:19.953498 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3588 23:47:19.957133 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3589 23:47:19.960668 == TX Byte 1 ==
3590 23:47:19.964296 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3591 23:47:19.966792 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3592 23:47:19.966943
3593 23:47:19.970588 [DATLAT]
3594 23:47:19.970738 Freq=1200, CH1 RK1
3595 23:47:19.970857
3596 23:47:19.973726 DATLAT Default: 0xd
3597 23:47:19.973897 0, 0xFFFF, sum = 0
3598 23:47:19.977349 1, 0xFFFF, sum = 0
3599 23:47:19.977553 2, 0xFFFF, sum = 0
3600 23:47:19.980228 3, 0xFFFF, sum = 0
3601 23:47:19.980429 4, 0xFFFF, sum = 0
3602 23:47:19.983442 5, 0xFFFF, sum = 0
3603 23:47:19.983683 6, 0xFFFF, sum = 0
3604 23:47:19.987090 7, 0xFFFF, sum = 0
3605 23:47:19.987388 8, 0xFFFF, sum = 0
3606 23:47:19.990305 9, 0xFFFF, sum = 0
3607 23:47:19.993501 10, 0xFFFF, sum = 0
3608 23:47:19.993893 11, 0xFFFF, sum = 0
3609 23:47:19.996918 12, 0x0, sum = 1
3610 23:47:19.997418 13, 0x0, sum = 2
3611 23:47:19.997761 14, 0x0, sum = 3
3612 23:47:20.000400 15, 0x0, sum = 4
3613 23:47:20.000847 best_step = 13
3614 23:47:20.001252
3615 23:47:20.003449 ==
3616 23:47:20.003864 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 23:47:20.010263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 23:47:20.010682 ==
3619 23:47:20.011015 RX Vref Scan: 0
3620 23:47:20.011328
3621 23:47:20.013684 RX Vref 0 -> 0, step: 1
3622 23:47:20.014121
3623 23:47:20.016854 RX Delay -21 -> 252, step: 4
3624 23:47:20.020969 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3625 23:47:20.023825 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3626 23:47:20.030531 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3627 23:47:20.033622 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3628 23:47:20.036955 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3629 23:47:20.040865 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3630 23:47:20.043784 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3631 23:47:20.050609 iDelay=191, Bit 7, Center 112 (47 ~ 178) 132
3632 23:47:20.053705 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3633 23:47:20.057440 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3634 23:47:20.060151 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3635 23:47:20.064127 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3636 23:47:20.070807 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3637 23:47:20.074239 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3638 23:47:20.077440 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3639 23:47:20.080244 iDelay=191, Bit 15, Center 118 (51 ~ 186) 136
3640 23:47:20.080660 ==
3641 23:47:20.083512 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 23:47:20.090414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 23:47:20.090925 ==
3644 23:47:20.091261 DQS Delay:
3645 23:47:20.093681 DQS0 = 0, DQS1 = 0
3646 23:47:20.094153 DQM Delay:
3647 23:47:20.094486 DQM0 = 113, DQM1 = 109
3648 23:47:20.097104 DQ Delay:
3649 23:47:20.100131 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3650 23:47:20.103794 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =112
3651 23:47:20.106707 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3652 23:47:20.110193 DQ12 =116, DQ13 =118, DQ14 =118, DQ15 =118
3653 23:47:20.110665
3654 23:47:20.111090
3655 23:47:20.120331 [DQSOSCAuto] RK1, (LSB)MR18= 0xf6fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps
3656 23:47:20.120857 CH1 RK1: MR19=303, MR18=F6FD
3657 23:47:20.126561 CH1_RK1: MR19=0x303, MR18=0xF6FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3658 23:47:20.130095 [RxdqsGatingPostProcess] freq 1200
3659 23:47:20.136831 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3660 23:47:20.140237 best DQS0 dly(2T, 0.5T) = (0, 11)
3661 23:47:20.143461 best DQS1 dly(2T, 0.5T) = (0, 11)
3662 23:47:20.146547 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3663 23:47:20.150202 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3664 23:47:20.150768 best DQS0 dly(2T, 0.5T) = (0, 11)
3665 23:47:20.153273 best DQS1 dly(2T, 0.5T) = (0, 11)
3666 23:47:20.156538 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3667 23:47:20.159910 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3668 23:47:20.163446 Pre-setting of DQS Precalculation
3669 23:47:20.170312 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3670 23:47:20.176942 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3671 23:47:20.183696 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3672 23:47:20.184220
3673 23:47:20.184556
3674 23:47:20.187068 [Calibration Summary] 2400 Mbps
3675 23:47:20.187583 CH 0, Rank 0
3676 23:47:20.190484 SW Impedance : PASS
3677 23:47:20.193790 DUTY Scan : NO K
3678 23:47:20.194204 ZQ Calibration : PASS
3679 23:47:20.196574 Jitter Meter : NO K
3680 23:47:20.200217 CBT Training : PASS
3681 23:47:20.200636 Write leveling : PASS
3682 23:47:20.203366 RX DQS gating : PASS
3683 23:47:20.207236 RX DQ/DQS(RDDQC) : PASS
3684 23:47:20.207756 TX DQ/DQS : PASS
3685 23:47:20.210213 RX DATLAT : PASS
3686 23:47:20.210629 RX DQ/DQS(Engine): PASS
3687 23:47:20.213990 TX OE : NO K
3688 23:47:20.214519 All Pass.
3689 23:47:20.214853
3690 23:47:20.217089 CH 0, Rank 1
3691 23:47:20.217624 SW Impedance : PASS
3692 23:47:20.220324 DUTY Scan : NO K
3693 23:47:20.224261 ZQ Calibration : PASS
3694 23:47:20.224778 Jitter Meter : NO K
3695 23:47:20.227044 CBT Training : PASS
3696 23:47:20.230823 Write leveling : PASS
3697 23:47:20.231337 RX DQS gating : PASS
3698 23:47:20.234310 RX DQ/DQS(RDDQC) : PASS
3699 23:47:20.237060 TX DQ/DQS : PASS
3700 23:47:20.237512 RX DATLAT : PASS
3701 23:47:20.240890 RX DQ/DQS(Engine): PASS
3702 23:47:20.243684 TX OE : NO K
3703 23:47:20.244103 All Pass.
3704 23:47:20.244433
3705 23:47:20.244738 CH 1, Rank 0
3706 23:47:20.246938 SW Impedance : PASS
3707 23:47:20.250359 DUTY Scan : NO K
3708 23:47:20.250814 ZQ Calibration : PASS
3709 23:47:20.254046 Jitter Meter : NO K
3710 23:47:20.254595 CBT Training : PASS
3711 23:47:20.256931 Write leveling : PASS
3712 23:47:20.260295 RX DQS gating : PASS
3713 23:47:20.260714 RX DQ/DQS(RDDQC) : PASS
3714 23:47:20.263711 TX DQ/DQS : PASS
3715 23:47:20.266993 RX DATLAT : PASS
3716 23:47:20.267505 RX DQ/DQS(Engine): PASS
3717 23:47:20.270530 TX OE : NO K
3718 23:47:20.270946 All Pass.
3719 23:47:20.271279
3720 23:47:20.273883 CH 1, Rank 1
3721 23:47:20.274296 SW Impedance : PASS
3722 23:47:20.276969 DUTY Scan : NO K
3723 23:47:20.280599 ZQ Calibration : PASS
3724 23:47:20.281047 Jitter Meter : NO K
3725 23:47:20.283752 CBT Training : PASS
3726 23:47:20.287052 Write leveling : PASS
3727 23:47:20.287465 RX DQS gating : PASS
3728 23:47:20.290318 RX DQ/DQS(RDDQC) : PASS
3729 23:47:20.290731 TX DQ/DQS : PASS
3730 23:47:20.293704 RX DATLAT : PASS
3731 23:47:20.297186 RX DQ/DQS(Engine): PASS
3732 23:47:20.297604 TX OE : NO K
3733 23:47:20.300626 All Pass.
3734 23:47:20.301066
3735 23:47:20.301398 DramC Write-DBI off
3736 23:47:20.303980 PER_BANK_REFRESH: Hybrid Mode
3737 23:47:20.307180 TX_TRACKING: ON
3738 23:47:20.313911 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3739 23:47:20.316866 [FAST_K] Save calibration result to emmc
3740 23:47:20.320151 dramc_set_vcore_voltage set vcore to 650000
3741 23:47:20.323748 Read voltage for 600, 5
3742 23:47:20.324162 Vio18 = 0
3743 23:47:20.326902 Vcore = 650000
3744 23:47:20.327315 Vdram = 0
3745 23:47:20.327643 Vddq = 0
3746 23:47:20.330600 Vmddr = 0
3747 23:47:20.333744 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3748 23:47:20.340485 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3749 23:47:20.341018 MEM_TYPE=3, freq_sel=19
3750 23:47:20.343876 sv_algorithm_assistance_LP4_1600
3751 23:47:20.350657 ============ PULL DRAM RESETB DOWN ============
3752 23:47:20.354111 ========== PULL DRAM RESETB DOWN end =========
3753 23:47:20.357253 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3754 23:47:20.361070 ===================================
3755 23:47:20.363743 LPDDR4 DRAM CONFIGURATION
3756 23:47:20.366916 ===================================
3757 23:47:20.367333 EX_ROW_EN[0] = 0x0
3758 23:47:20.370241 EX_ROW_EN[1] = 0x0
3759 23:47:20.373657 LP4Y_EN = 0x0
3760 23:47:20.374073 WORK_FSP = 0x0
3761 23:47:20.377368 WL = 0x2
3762 23:47:20.377781 RL = 0x2
3763 23:47:20.380519 BL = 0x2
3764 23:47:20.380932 RPST = 0x0
3765 23:47:20.383550 RD_PRE = 0x0
3766 23:47:20.383962 WR_PRE = 0x1
3767 23:47:20.387529 WR_PST = 0x0
3768 23:47:20.387945 DBI_WR = 0x0
3769 23:47:20.390547 DBI_RD = 0x0
3770 23:47:20.390961 OTF = 0x1
3771 23:47:20.394114 ===================================
3772 23:47:20.397053 ===================================
3773 23:47:20.400541 ANA top config
3774 23:47:20.404332 ===================================
3775 23:47:20.404856 DLL_ASYNC_EN = 0
3776 23:47:20.407158 ALL_SLAVE_EN = 1
3777 23:47:20.410383 NEW_RANK_MODE = 1
3778 23:47:20.413589 DLL_IDLE_MODE = 1
3779 23:47:20.414006 LP45_APHY_COMB_EN = 1
3780 23:47:20.417076 TX_ODT_DIS = 1
3781 23:47:20.420967 NEW_8X_MODE = 1
3782 23:47:20.423871 ===================================
3783 23:47:20.427601 ===================================
3784 23:47:20.430642 data_rate = 1200
3785 23:47:20.433614 CKR = 1
3786 23:47:20.437031 DQ_P2S_RATIO = 8
3787 23:47:20.440867 ===================================
3788 23:47:20.441426 CA_P2S_RATIO = 8
3789 23:47:20.443985 DQ_CA_OPEN = 0
3790 23:47:20.447087 DQ_SEMI_OPEN = 0
3791 23:47:20.450549 CA_SEMI_OPEN = 0
3792 23:47:20.453931 CA_FULL_RATE = 0
3793 23:47:20.454442 DQ_CKDIV4_EN = 1
3794 23:47:20.457050 CA_CKDIV4_EN = 1
3795 23:47:20.460713 CA_PREDIV_EN = 0
3796 23:47:20.463531 PH8_DLY = 0
3797 23:47:20.467871 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3798 23:47:20.470751 DQ_AAMCK_DIV = 4
3799 23:47:20.471273 CA_AAMCK_DIV = 4
3800 23:47:20.474681 CA_ADMCK_DIV = 4
3801 23:47:20.477649 DQ_TRACK_CA_EN = 0
3802 23:47:20.480748 CA_PICK = 600
3803 23:47:20.484855 CA_MCKIO = 600
3804 23:47:20.487553 MCKIO_SEMI = 0
3805 23:47:20.490823 PLL_FREQ = 2288
3806 23:47:20.491243 DQ_UI_PI_RATIO = 32
3807 23:47:20.493906 CA_UI_PI_RATIO = 0
3808 23:47:20.497383 ===================================
3809 23:47:20.501025 ===================================
3810 23:47:20.504455 memory_type:LPDDR4
3811 23:47:20.507537 GP_NUM : 10
3812 23:47:20.508058 SRAM_EN : 1
3813 23:47:20.510892 MD32_EN : 0
3814 23:47:20.514791 ===================================
3815 23:47:20.515347 [ANA_INIT] >>>>>>>>>>>>>>
3816 23:47:20.517376 <<<<<< [CONFIGURE PHASE]: ANA_TX
3817 23:47:20.520606 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3818 23:47:20.524175 ===================================
3819 23:47:20.527683 data_rate = 1200,PCW = 0X5800
3820 23:47:20.531278 ===================================
3821 23:47:20.534606 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3822 23:47:20.541256 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3823 23:47:20.543938 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3824 23:47:20.551312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3825 23:47:20.554055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3826 23:47:20.557503 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3827 23:47:20.561110 [ANA_INIT] flow start
3828 23:47:20.561653 [ANA_INIT] PLL >>>>>>>>
3829 23:47:20.564404 [ANA_INIT] PLL <<<<<<<<
3830 23:47:20.567712 [ANA_INIT] MIDPI >>>>>>>>
3831 23:47:20.568266 [ANA_INIT] MIDPI <<<<<<<<
3832 23:47:20.571137 [ANA_INIT] DLL >>>>>>>>
3833 23:47:20.574325 [ANA_INIT] flow end
3834 23:47:20.577544 ============ LP4 DIFF to SE enter ============
3835 23:47:20.581171 ============ LP4 DIFF to SE exit ============
3836 23:47:20.584068 [ANA_INIT] <<<<<<<<<<<<<
3837 23:47:20.587537 [Flow] Enable top DCM control >>>>>
3838 23:47:20.590522 [Flow] Enable top DCM control <<<<<
3839 23:47:20.594096 Enable DLL master slave shuffle
3840 23:47:20.597556 ==============================================================
3841 23:47:20.600453 Gating Mode config
3842 23:47:20.604188 ==============================================================
3843 23:47:20.607401 Config description:
3844 23:47:20.617285 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3845 23:47:20.624306 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3846 23:47:20.627573 SELPH_MODE 0: By rank 1: By Phase
3847 23:47:20.634483 ==============================================================
3848 23:47:20.637383 GAT_TRACK_EN = 1
3849 23:47:20.640714 RX_GATING_MODE = 2
3850 23:47:20.644099 RX_GATING_TRACK_MODE = 2
3851 23:47:20.646917 SELPH_MODE = 1
3852 23:47:20.650513 PICG_EARLY_EN = 1
3853 23:47:20.650974 VALID_LAT_VALUE = 1
3854 23:47:20.657137 ==============================================================
3855 23:47:20.661115 Enter into Gating configuration >>>>
3856 23:47:20.664218 Exit from Gating configuration <<<<
3857 23:47:20.667167 Enter into DVFS_PRE_config >>>>>
3858 23:47:20.677276 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3859 23:47:20.680846 Exit from DVFS_PRE_config <<<<<
3860 23:47:20.684075 Enter into PICG configuration >>>>
3861 23:47:20.687713 Exit from PICG configuration <<<<
3862 23:47:20.690697 [RX_INPUT] configuration >>>>>
3863 23:47:20.693829 [RX_INPUT] configuration <<<<<
3864 23:47:20.697382 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3865 23:47:20.703527 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3866 23:47:20.710435 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3867 23:47:20.716953 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3868 23:47:20.723552 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3869 23:47:20.727899 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3870 23:47:20.733874 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3871 23:47:20.737352 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3872 23:47:20.740553 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3873 23:47:20.743592 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3874 23:47:20.750676 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3875 23:47:20.753755 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3876 23:47:20.757051 ===================================
3877 23:47:20.760666 LPDDR4 DRAM CONFIGURATION
3878 23:47:20.763800 ===================================
3879 23:47:20.764219 EX_ROW_EN[0] = 0x0
3880 23:47:20.767578 EX_ROW_EN[1] = 0x0
3881 23:47:20.768081 LP4Y_EN = 0x0
3882 23:47:20.771020 WORK_FSP = 0x0
3883 23:47:20.771532 WL = 0x2
3884 23:47:20.774220 RL = 0x2
3885 23:47:20.774636 BL = 0x2
3886 23:47:20.776928 RPST = 0x0
3887 23:47:20.777395 RD_PRE = 0x0
3888 23:47:20.780288 WR_PRE = 0x1
3889 23:47:20.780756 WR_PST = 0x0
3890 23:47:20.783794 DBI_WR = 0x0
3891 23:47:20.784209 DBI_RD = 0x0
3892 23:47:20.787034 OTF = 0x1
3893 23:47:20.790231 ===================================
3894 23:47:20.793685 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3895 23:47:20.797390 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3896 23:47:20.803691 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3897 23:47:20.807932 ===================================
3898 23:47:20.808450 LPDDR4 DRAM CONFIGURATION
3899 23:47:20.810866 ===================================
3900 23:47:20.814423 EX_ROW_EN[0] = 0x10
3901 23:47:20.817053 EX_ROW_EN[1] = 0x0
3902 23:47:20.817469 LP4Y_EN = 0x0
3903 23:47:20.820399 WORK_FSP = 0x0
3904 23:47:20.820814 WL = 0x2
3905 23:47:20.823885 RL = 0x2
3906 23:47:20.824301 BL = 0x2
3907 23:47:20.826960 RPST = 0x0
3908 23:47:20.827375 RD_PRE = 0x0
3909 23:47:20.830477 WR_PRE = 0x1
3910 23:47:20.830895 WR_PST = 0x0
3911 23:47:20.834163 DBI_WR = 0x0
3912 23:47:20.834589 DBI_RD = 0x0
3913 23:47:20.836804 OTF = 0x1
3914 23:47:20.840629 ===================================
3915 23:47:20.846879 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3916 23:47:20.850549 nWR fixed to 30
3917 23:47:20.850966 [ModeRegInit_LP4] CH0 RK0
3918 23:47:20.853747 [ModeRegInit_LP4] CH0 RK1
3919 23:47:20.857078 [ModeRegInit_LP4] CH1 RK0
3920 23:47:20.860627 [ModeRegInit_LP4] CH1 RK1
3921 23:47:20.861077 match AC timing 17
3922 23:47:20.867095 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3923 23:47:20.870811 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3924 23:47:20.874219 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3925 23:47:20.880655 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3926 23:47:20.883907 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3927 23:47:20.884429 ==
3928 23:47:20.887040 Dram Type= 6, Freq= 0, CH_0, rank 0
3929 23:47:20.891051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3930 23:47:20.891470 ==
3931 23:47:20.897624 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3932 23:47:20.904207 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3933 23:47:20.907598 [CA 0] Center 36 (6~67) winsize 62
3934 23:47:20.911124 [CA 1] Center 36 (6~66) winsize 61
3935 23:47:20.914789 [CA 2] Center 34 (4~64) winsize 61
3936 23:47:20.917700 [CA 3] Center 34 (4~65) winsize 62
3937 23:47:20.921115 [CA 4] Center 34 (4~64) winsize 61
3938 23:47:20.921683 [CA 5] Center 33 (3~64) winsize 62
3939 23:47:20.922051
3940 23:47:20.927982 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3941 23:47:20.928540
3942 23:47:20.931190 [CATrainingPosCal] consider 1 rank data
3943 23:47:20.934818 u2DelayCellTimex100 = 270/100 ps
3944 23:47:20.937879 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3945 23:47:20.940626 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3946 23:47:20.944051 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3947 23:47:20.947576 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3948 23:47:20.951239 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3949 23:47:20.953970 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3950 23:47:20.954453
3951 23:47:20.957493 CA PerBit enable=1, Macro0, CA PI delay=33
3952 23:47:20.957951
3953 23:47:20.960675 [CBTSetCACLKResult] CA Dly = 33
3954 23:47:20.964234 CS Dly: 4 (0~35)
3955 23:47:20.964802 ==
3956 23:47:20.967710 Dram Type= 6, Freq= 0, CH_0, rank 1
3957 23:47:20.971142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 23:47:20.971703 ==
3959 23:47:20.977443 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3960 23:47:20.984159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3961 23:47:20.987166 [CA 0] Center 36 (6~66) winsize 61
3962 23:47:20.990766 [CA 1] Center 36 (6~66) winsize 61
3963 23:47:20.994385 [CA 2] Center 34 (4~65) winsize 62
3964 23:47:20.997234 [CA 3] Center 34 (4~65) winsize 62
3965 23:47:21.000712 [CA 4] Center 33 (3~64) winsize 62
3966 23:47:21.003503 [CA 5] Center 33 (3~64) winsize 62
3967 23:47:21.003963
3968 23:47:21.007947 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3969 23:47:21.008496
3970 23:47:21.011161 [CATrainingPosCal] consider 2 rank data
3971 23:47:21.013754 u2DelayCellTimex100 = 270/100 ps
3972 23:47:21.017441 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3973 23:47:21.020806 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3974 23:47:21.023862 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
3975 23:47:21.027510 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3976 23:47:21.030070 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
3977 23:47:21.033653 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 23:47:21.034114
3979 23:47:21.036872 CA PerBit enable=1, Macro0, CA PI delay=33
3980 23:47:21.040571
3981 23:47:21.041164 [CBTSetCACLKResult] CA Dly = 33
3982 23:47:21.043554 CS Dly: 4 (0~36)
3983 23:47:21.044013
3984 23:47:21.047031 ----->DramcWriteLeveling(PI) begin...
3985 23:47:21.047593 ==
3986 23:47:21.050096 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 23:47:21.053868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 23:47:21.054430 ==
3989 23:47:21.057601 Write leveling (Byte 0): 30 => 30
3990 23:47:21.060728 Write leveling (Byte 1): 30 => 30
3991 23:47:21.063640 DramcWriteLeveling(PI) end<-----
3992 23:47:21.064197
3993 23:47:21.064560 ==
3994 23:47:21.067490 Dram Type= 6, Freq= 0, CH_0, rank 0
3995 23:47:21.070411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3996 23:47:21.073331 ==
3997 23:47:21.073790 [Gating] SW mode calibration
3998 23:47:21.080617 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3999 23:47:21.087002 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4000 23:47:21.090422 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 23:47:21.097413 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 23:47:21.100696 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 23:47:21.103629 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 23:47:21.110126 0 9 16 | B1->B0 | 3232 3030 | 1 1 | (1 0) (1 1)
4005 23:47:21.113375 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 23:47:21.117123 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 23:47:21.123873 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 23:47:21.127477 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 23:47:21.129998 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 23:47:21.133588 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 23:47:21.140427 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 23:47:21.143681 0 10 16 | B1->B0 | 3030 3b3b | 0 0 | (0 0) (0 0)
4013 23:47:21.147159 0 10 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4014 23:47:21.153726 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 23:47:21.156890 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 23:47:21.160321 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 23:47:21.166632 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 23:47:21.170701 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 23:47:21.173665 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 23:47:21.180175 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4021 23:47:21.183463 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 23:47:21.186619 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 23:47:21.193631 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 23:47:21.196929 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 23:47:21.200277 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 23:47:21.206904 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 23:47:21.210277 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 23:47:21.213891 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 23:47:21.220394 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 23:47:21.223757 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 23:47:21.226879 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 23:47:21.230144 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 23:47:21.236704 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 23:47:21.240079 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 23:47:21.243598 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 23:47:21.250012 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4037 23:47:21.253854 Total UI for P1: 0, mck2ui 16
4038 23:47:21.256617 best dqsien dly found for B0: ( 0, 13, 14)
4039 23:47:21.260373 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 23:47:21.263496 Total UI for P1: 0, mck2ui 16
4041 23:47:21.266956 best dqsien dly found for B1: ( 0, 13, 16)
4042 23:47:21.270683 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4043 23:47:21.273864 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4044 23:47:21.274354
4045 23:47:21.277330 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4046 23:47:21.279869 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4047 23:47:21.283280 [Gating] SW calibration Done
4048 23:47:21.283821 ==
4049 23:47:21.287283 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 23:47:21.293703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 23:47:21.294259 ==
4052 23:47:21.294628 RX Vref Scan: 0
4053 23:47:21.294974
4054 23:47:21.297066 RX Vref 0 -> 0, step: 1
4055 23:47:21.297610
4056 23:47:21.299987 RX Delay -230 -> 252, step: 16
4057 23:47:21.303328 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4058 23:47:21.306666 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4059 23:47:21.310336 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4060 23:47:21.316817 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4061 23:47:21.320344 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4062 23:47:21.323606 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4063 23:47:21.327448 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4064 23:47:21.330290 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4065 23:47:21.336634 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4066 23:47:21.340318 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4067 23:47:21.344102 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4068 23:47:21.346380 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4069 23:47:21.353615 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4070 23:47:21.357098 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4071 23:47:21.360223 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4072 23:47:21.363726 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4073 23:47:21.364284 ==
4074 23:47:21.366870 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 23:47:21.373739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 23:47:21.374202 ==
4077 23:47:21.374570 DQS Delay:
4078 23:47:21.377143 DQS0 = 0, DQS1 = 0
4079 23:47:21.377602 DQM Delay:
4080 23:47:21.378028 DQM0 = 43, DQM1 = 32
4081 23:47:21.379858 DQ Delay:
4082 23:47:21.383485 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4083 23:47:21.386541 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4084 23:47:21.390312 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4085 23:47:21.393356 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4086 23:47:21.393951
4087 23:47:21.394343
4088 23:47:21.394683 ==
4089 23:47:21.397268 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 23:47:21.400299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 23:47:21.400851 ==
4092 23:47:21.401279
4093 23:47:21.401620
4094 23:47:21.403510 TX Vref Scan disable
4095 23:47:21.403965 == TX Byte 0 ==
4096 23:47:21.409848 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4097 23:47:21.413274 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4098 23:47:21.413737 == TX Byte 1 ==
4099 23:47:21.420602 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4100 23:47:21.423835 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4101 23:47:21.424415 ==
4102 23:47:21.426590 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 23:47:21.430753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 23:47:21.431320 ==
4105 23:47:21.431695
4106 23:47:21.432035
4107 23:47:21.433434 TX Vref Scan disable
4108 23:47:21.436970 == TX Byte 0 ==
4109 23:47:21.440512 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4110 23:47:21.443391 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4111 23:47:21.447302 == TX Byte 1 ==
4112 23:47:21.450331 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4113 23:47:21.453353 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4114 23:47:21.453909
4115 23:47:21.457251 [DATLAT]
4116 23:47:21.457844 Freq=600, CH0 RK0
4117 23:47:21.458219
4118 23:47:21.460357 DATLAT Default: 0x9
4119 23:47:21.460814 0, 0xFFFF, sum = 0
4120 23:47:21.463483 1, 0xFFFF, sum = 0
4121 23:47:21.463948 2, 0xFFFF, sum = 0
4122 23:47:21.466729 3, 0xFFFF, sum = 0
4123 23:47:21.467195 4, 0xFFFF, sum = 0
4124 23:47:21.470383 5, 0xFFFF, sum = 0
4125 23:47:21.470943 6, 0xFFFF, sum = 0
4126 23:47:21.473296 7, 0xFFFF, sum = 0
4127 23:47:21.473762 8, 0x0, sum = 1
4128 23:47:21.477100 9, 0x0, sum = 2
4129 23:47:21.477515 10, 0x0, sum = 3
4130 23:47:21.480671 11, 0x0, sum = 4
4131 23:47:21.481266 best_step = 9
4132 23:47:21.481635
4133 23:47:21.482054 ==
4134 23:47:21.483874 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 23:47:21.489930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 23:47:21.490470 ==
4137 23:47:21.490837 RX Vref Scan: 1
4138 23:47:21.491174
4139 23:47:21.493781 RX Vref 0 -> 0, step: 1
4140 23:47:21.494334
4141 23:47:21.496810 RX Delay -195 -> 252, step: 8
4142 23:47:21.497313
4143 23:47:21.499789 Set Vref, RX VrefLevel [Byte0]: 54
4144 23:47:21.503683 [Byte1]: 52
4145 23:47:21.504140
4146 23:47:21.506670 Final RX Vref Byte 0 = 54 to rank0
4147 23:47:21.510214 Final RX Vref Byte 1 = 52 to rank0
4148 23:47:21.513586 Final RX Vref Byte 0 = 54 to rank1
4149 23:47:21.516526 Final RX Vref Byte 1 = 52 to rank1==
4150 23:47:21.520201 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 23:47:21.523298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 23:47:21.523871 ==
4153 23:47:21.526834 DQS Delay:
4154 23:47:21.527290 DQS0 = 0, DQS1 = 0
4155 23:47:21.527656 DQM Delay:
4156 23:47:21.529798 DQM0 = 42, DQM1 = 33
4157 23:47:21.530331 DQ Delay:
4158 23:47:21.533237 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4159 23:47:21.536531 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4160 23:47:21.539299 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4161 23:47:21.543109 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4162 23:47:21.543529
4163 23:47:21.543860
4164 23:47:21.553250 [DQSOSCAuto] RK0, (LSB)MR18= 0x3d1c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4165 23:47:21.556057 CH0 RK0: MR19=808, MR18=3D1C
4166 23:47:21.559925 CH0_RK0: MR19=0x808, MR18=0x3D1C, DQSOSC=398, MR23=63, INC=165, DEC=110
4167 23:47:21.560533
4168 23:47:21.562868 ----->DramcWriteLeveling(PI) begin...
4169 23:47:21.566104 ==
4170 23:47:21.569438 Dram Type= 6, Freq= 0, CH_0, rank 1
4171 23:47:21.573032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 23:47:21.573456 ==
4173 23:47:21.576276 Write leveling (Byte 0): 32 => 32
4174 23:47:21.579785 Write leveling (Byte 1): 30 => 30
4175 23:47:21.582920 DramcWriteLeveling(PI) end<-----
4176 23:47:21.583338
4177 23:47:21.583672 ==
4178 23:47:21.586159 Dram Type= 6, Freq= 0, CH_0, rank 1
4179 23:47:21.589657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 23:47:21.590110 ==
4181 23:47:21.593556 [Gating] SW mode calibration
4182 23:47:21.599746 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4183 23:47:21.603271 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4184 23:47:21.609443 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 23:47:21.612926 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4186 23:47:21.616426 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4187 23:47:21.622985 0 9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
4188 23:47:21.626359 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
4189 23:47:21.629899 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 23:47:21.636229 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 23:47:21.639589 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 23:47:21.642795 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 23:47:21.649518 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 23:47:21.653079 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 23:47:21.656190 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4196 23:47:21.663272 0 10 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
4197 23:47:21.666204 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 23:47:21.669795 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 23:47:21.676110 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 23:47:21.679945 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 23:47:21.683246 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 23:47:21.689857 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 23:47:21.692726 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4204 23:47:21.696059 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4205 23:47:21.699459 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 23:47:21.706222 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 23:47:21.709908 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 23:47:21.713137 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 23:47:21.719630 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 23:47:21.722668 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 23:47:21.726261 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 23:47:21.733162 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 23:47:21.736240 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 23:47:21.740030 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 23:47:21.746429 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 23:47:21.749657 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 23:47:21.753157 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 23:47:21.759261 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 23:47:21.762682 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 23:47:21.766151 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4221 23:47:21.769682 Total UI for P1: 0, mck2ui 16
4222 23:47:21.773294 best dqsien dly found for B0: ( 0, 13, 14)
4223 23:47:21.779568 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 23:47:21.780110 Total UI for P1: 0, mck2ui 16
4225 23:47:21.782834 best dqsien dly found for B1: ( 0, 13, 16)
4226 23:47:21.789730 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4227 23:47:21.793340 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4228 23:47:21.793806
4229 23:47:21.796215 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4230 23:47:21.799879 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4231 23:47:21.803272 [Gating] SW calibration Done
4232 23:47:21.803860 ==
4233 23:47:21.806183 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 23:47:21.809757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 23:47:21.810218 ==
4236 23:47:21.813062 RX Vref Scan: 0
4237 23:47:21.813544
4238 23:47:21.813910 RX Vref 0 -> 0, step: 1
4239 23:47:21.814249
4240 23:47:21.816587 RX Delay -230 -> 252, step: 16
4241 23:47:21.819751 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4242 23:47:21.826402 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4243 23:47:21.829713 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4244 23:47:21.832971 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4245 23:47:21.836308 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4246 23:47:21.842949 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4247 23:47:21.846470 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4248 23:47:21.849278 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4249 23:47:21.852907 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4250 23:47:21.856054 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4251 23:47:21.862761 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4252 23:47:21.866501 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4253 23:47:21.869542 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4254 23:47:21.872887 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4255 23:47:21.879620 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4256 23:47:21.882992 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4257 23:47:21.883573 ==
4258 23:47:21.886360 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 23:47:21.889514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 23:47:21.889933 ==
4261 23:47:21.893158 DQS Delay:
4262 23:47:21.893576 DQS0 = 0, DQS1 = 0
4263 23:47:21.893907 DQM Delay:
4264 23:47:21.896181 DQM0 = 41, DQM1 = 32
4265 23:47:21.896595 DQ Delay:
4266 23:47:21.899449 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4267 23:47:21.903126 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4268 23:47:21.906425 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4269 23:47:21.909588 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4270 23:47:21.910007
4271 23:47:21.910336
4272 23:47:21.910641 ==
4273 23:47:21.912867 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 23:47:21.916709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 23:47:21.920061 ==
4276 23:47:21.920632
4277 23:47:21.921357
4278 23:47:21.921863 TX Vref Scan disable
4279 23:47:21.923404 == TX Byte 0 ==
4280 23:47:21.926726 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4281 23:47:21.929978 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4282 23:47:21.933573 == TX Byte 1 ==
4283 23:47:21.937298 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4284 23:47:21.940217 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4285 23:47:21.940632 ==
4286 23:47:21.943592 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 23:47:21.950140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 23:47:21.950557 ==
4289 23:47:21.950980
4290 23:47:21.951585
4291 23:47:21.952187 TX Vref Scan disable
4292 23:47:21.954599 == TX Byte 0 ==
4293 23:47:21.958012 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4294 23:47:21.964503 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4295 23:47:21.965111 == TX Byte 1 ==
4296 23:47:21.967970 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4297 23:47:21.974586 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4298 23:47:21.975003
4299 23:47:21.975332 [DATLAT]
4300 23:47:21.975638 Freq=600, CH0 RK1
4301 23:47:21.975939
4302 23:47:21.977618 DATLAT Default: 0x9
4303 23:47:21.978033 0, 0xFFFF, sum = 0
4304 23:47:21.980791 1, 0xFFFF, sum = 0
4305 23:47:21.981266 2, 0xFFFF, sum = 0
4306 23:47:21.984062 3, 0xFFFF, sum = 0
4307 23:47:21.987560 4, 0xFFFF, sum = 0
4308 23:47:21.987944 5, 0xFFFF, sum = 0
4309 23:47:21.991705 6, 0xFFFF, sum = 0
4310 23:47:21.992098 7, 0xFFFF, sum = 0
4311 23:47:21.992355 8, 0x0, sum = 1
4312 23:47:21.994356 9, 0x0, sum = 2
4313 23:47:21.994681 10, 0x0, sum = 3
4314 23:47:21.997573 11, 0x0, sum = 4
4315 23:47:21.997871 best_step = 9
4316 23:47:21.998134
4317 23:47:21.998453 ==
4318 23:47:22.000886 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 23:47:22.007810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 23:47:22.008108 ==
4321 23:47:22.008355 RX Vref Scan: 0
4322 23:47:22.008574
4323 23:47:22.010815 RX Vref 0 -> 0, step: 1
4324 23:47:22.011156
4325 23:47:22.014084 RX Delay -195 -> 252, step: 8
4326 23:47:22.018038 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4327 23:47:22.024241 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4328 23:47:22.027761 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4329 23:47:22.031216 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4330 23:47:22.034569 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4331 23:47:22.038278 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4332 23:47:22.045133 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4333 23:47:22.048382 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4334 23:47:22.051491 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4335 23:47:22.054421 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4336 23:47:22.061356 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4337 23:47:22.064600 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4338 23:47:22.067963 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4339 23:47:22.070866 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4340 23:47:22.074307 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4341 23:47:22.081042 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4342 23:47:22.081489 ==
4343 23:47:22.084428 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 23:47:22.087987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 23:47:22.088578 ==
4346 23:47:22.088920 DQS Delay:
4347 23:47:22.091523 DQS0 = 0, DQS1 = 0
4348 23:47:22.092026 DQM Delay:
4349 23:47:22.094531 DQM0 = 40, DQM1 = 34
4350 23:47:22.095053 DQ Delay:
4351 23:47:22.098512 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =40
4352 23:47:22.101261 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4353 23:47:22.104284 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4354 23:47:22.108088 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4355 23:47:22.108503
4356 23:47:22.108832
4357 23:47:22.118102 [DQSOSCAuto] RK1, (LSB)MR18= 0x4729, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4358 23:47:22.118656 CH0 RK1: MR19=808, MR18=4729
4359 23:47:22.124594 CH0_RK1: MR19=0x808, MR18=0x4729, DQSOSC=396, MR23=63, INC=167, DEC=111
4360 23:47:22.127963 [RxdqsGatingPostProcess] freq 600
4361 23:47:22.134450 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4362 23:47:22.137979 Pre-setting of DQS Precalculation
4363 23:47:22.141031 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4364 23:47:22.141761 ==
4365 23:47:22.144121 Dram Type= 6, Freq= 0, CH_1, rank 0
4366 23:47:22.147970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 23:47:22.148394 ==
4368 23:47:22.154656 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 23:47:22.161069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4370 23:47:22.164073 [CA 0] Center 35 (5~66) winsize 62
4371 23:47:22.167913 [CA 1] Center 35 (5~66) winsize 62
4372 23:47:22.171809 [CA 2] Center 34 (4~65) winsize 62
4373 23:47:22.174601 [CA 3] Center 33 (2~64) winsize 63
4374 23:47:22.178228 [CA 4] Center 33 (3~64) winsize 62
4375 23:47:22.181383 [CA 5] Center 33 (2~64) winsize 63
4376 23:47:22.181800
4377 23:47:22.185154 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4378 23:47:22.185666
4379 23:47:22.187639 [CATrainingPosCal] consider 1 rank data
4380 23:47:22.191157 u2DelayCellTimex100 = 270/100 ps
4381 23:47:22.194592 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4382 23:47:22.197753 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4383 23:47:22.201200 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4384 23:47:22.204511 CA3 delay=33 (2~64),Diff = 0 PI (0 cell)
4385 23:47:22.207593 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4386 23:47:22.214586 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4387 23:47:22.215136
4388 23:47:22.217952 CA PerBit enable=1, Macro0, CA PI delay=33
4389 23:47:22.218495
4390 23:47:22.221241 [CBTSetCACLKResult] CA Dly = 33
4391 23:47:22.221701 CS Dly: 4 (0~35)
4392 23:47:22.222072 ==
4393 23:47:22.224433 Dram Type= 6, Freq= 0, CH_1, rank 1
4394 23:47:22.227988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 23:47:22.231437 ==
4396 23:47:22.234643 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4397 23:47:22.241161 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4398 23:47:22.244931 [CA 0] Center 35 (5~66) winsize 62
4399 23:47:22.247695 [CA 1] Center 35 (5~66) winsize 62
4400 23:47:22.251182 [CA 2] Center 34 (3~65) winsize 63
4401 23:47:22.254587 [CA 3] Center 34 (3~65) winsize 63
4402 23:47:22.258174 [CA 4] Center 34 (3~65) winsize 63
4403 23:47:22.261056 [CA 5] Center 33 (3~64) winsize 62
4404 23:47:22.261521
4405 23:47:22.264356 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4406 23:47:22.264817
4407 23:47:22.267677 [CATrainingPosCal] consider 2 rank data
4408 23:47:22.271487 u2DelayCellTimex100 = 270/100 ps
4409 23:47:22.274281 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4410 23:47:22.277743 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4411 23:47:22.281622 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4412 23:47:22.284819 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4413 23:47:22.287934 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4414 23:47:22.295025 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4415 23:47:22.295560
4416 23:47:22.298024 CA PerBit enable=1, Macro0, CA PI delay=33
4417 23:47:22.298485
4418 23:47:22.301344 [CBTSetCACLKResult] CA Dly = 33
4419 23:47:22.301801 CS Dly: 4 (0~36)
4420 23:47:22.302171
4421 23:47:22.305276 ----->DramcWriteLeveling(PI) begin...
4422 23:47:22.305830 ==
4423 23:47:22.308227 Dram Type= 6, Freq= 0, CH_1, rank 0
4424 23:47:22.311545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 23:47:22.314836 ==
4426 23:47:22.315419 Write leveling (Byte 0): 29 => 29
4427 23:47:22.317931 Write leveling (Byte 1): 33 => 33
4428 23:47:22.321546 DramcWriteLeveling(PI) end<-----
4429 23:47:22.322111
4430 23:47:22.322480 ==
4431 23:47:22.324364 Dram Type= 6, Freq= 0, CH_1, rank 0
4432 23:47:22.331323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4433 23:47:22.331785 ==
4434 23:47:22.332154 [Gating] SW mode calibration
4435 23:47:22.341300 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4436 23:47:22.344932 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4437 23:47:22.348262 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4438 23:47:22.354370 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 23:47:22.358519 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4440 23:47:22.361404 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4441 23:47:22.368079 0 9 16 | B1->B0 | 2d2d 2525 | 0 0 | (0 0) (1 1)
4442 23:47:22.371826 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 23:47:22.375377 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 23:47:22.381421 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 23:47:22.384766 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 23:47:22.388471 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 23:47:22.394991 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4448 23:47:22.398304 0 10 12 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
4449 23:47:22.401659 0 10 16 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (0 0)
4450 23:47:22.408286 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 23:47:22.411834 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 23:47:22.414912 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 23:47:22.421569 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 23:47:22.424888 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 23:47:22.428326 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 23:47:22.431717 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 23:47:22.437677 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 23:47:22.441141 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 23:47:22.445088 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 23:47:22.451240 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 23:47:22.454469 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 23:47:22.457808 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 23:47:22.465090 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 23:47:22.467992 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 23:47:22.471229 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 23:47:22.478297 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 23:47:22.481591 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 23:47:22.484435 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 23:47:22.491743 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 23:47:22.495051 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 23:47:22.498121 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 23:47:22.505136 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4473 23:47:22.508096 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 23:47:22.511220 Total UI for P1: 0, mck2ui 16
4475 23:47:22.515092 best dqsien dly found for B0: ( 0, 13, 12)
4476 23:47:22.518150 Total UI for P1: 0, mck2ui 16
4477 23:47:22.521381 best dqsien dly found for B1: ( 0, 13, 14)
4478 23:47:22.524664 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4479 23:47:22.528063 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4480 23:47:22.528523
4481 23:47:22.532100 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4482 23:47:22.534780 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4483 23:47:22.538497 [Gating] SW calibration Done
4484 23:47:22.539150 ==
4485 23:47:22.541561 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 23:47:22.544639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 23:47:22.545152 ==
4488 23:47:22.548138 RX Vref Scan: 0
4489 23:47:22.548593
4490 23:47:22.551180 RX Vref 0 -> 0, step: 1
4491 23:47:22.551638
4492 23:47:22.552002 RX Delay -230 -> 252, step: 16
4493 23:47:22.558541 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4494 23:47:22.561231 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4495 23:47:22.565191 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4496 23:47:22.568006 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4497 23:47:22.574833 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4498 23:47:22.578359 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4499 23:47:22.581698 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4500 23:47:22.584752 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4501 23:47:22.588200 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4502 23:47:22.595320 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4503 23:47:22.598181 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4504 23:47:22.601881 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4505 23:47:22.605430 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4506 23:47:22.611820 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4507 23:47:22.615381 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4508 23:47:22.618379 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4509 23:47:22.618931 ==
4510 23:47:22.621631 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 23:47:22.624769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 23:47:22.625365 ==
4513 23:47:22.627918 DQS Delay:
4514 23:47:22.628374 DQS0 = 0, DQS1 = 0
4515 23:47:22.631871 DQM Delay:
4516 23:47:22.632419 DQM0 = 43, DQM1 = 35
4517 23:47:22.632787 DQ Delay:
4518 23:47:22.635063 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4519 23:47:22.637998 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4520 23:47:22.641221 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4521 23:47:22.646212 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4522 23:47:22.646768
4523 23:47:22.647136
4524 23:47:22.648592 ==
4525 23:47:22.651443 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 23:47:22.654619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 23:47:22.655086 ==
4528 23:47:22.655450
4529 23:47:22.655786
4530 23:47:22.657831 TX Vref Scan disable
4531 23:47:22.658292 == TX Byte 0 ==
4532 23:47:22.664616 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4533 23:47:22.668377 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4534 23:47:22.668836 == TX Byte 1 ==
4535 23:47:22.674780 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4536 23:47:22.677987 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4537 23:47:22.678450 ==
4538 23:47:22.681122 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 23:47:22.684934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 23:47:22.685437 ==
4541 23:47:22.685846
4542 23:47:22.686188
4543 23:47:22.688450 TX Vref Scan disable
4544 23:47:22.691134 == TX Byte 0 ==
4545 23:47:22.694456 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4546 23:47:22.698198 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4547 23:47:22.701666 == TX Byte 1 ==
4548 23:47:22.704998 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4549 23:47:22.707996 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4550 23:47:22.708610
4551 23:47:22.711619 [DATLAT]
4552 23:47:22.712169 Freq=600, CH1 RK0
4553 23:47:22.712536
4554 23:47:22.714819 DATLAT Default: 0x9
4555 23:47:22.715364 0, 0xFFFF, sum = 0
4556 23:47:22.717894 1, 0xFFFF, sum = 0
4557 23:47:22.718450 2, 0xFFFF, sum = 0
4558 23:47:22.721345 3, 0xFFFF, sum = 0
4559 23:47:22.721897 4, 0xFFFF, sum = 0
4560 23:47:22.724586 5, 0xFFFF, sum = 0
4561 23:47:22.725167 6, 0xFFFF, sum = 0
4562 23:47:22.728083 7, 0xFFFF, sum = 0
4563 23:47:22.728638 8, 0x0, sum = 1
4564 23:47:22.731578 9, 0x0, sum = 2
4565 23:47:22.732130 10, 0x0, sum = 3
4566 23:47:22.734515 11, 0x0, sum = 4
4567 23:47:22.735107 best_step = 9
4568 23:47:22.735480
4569 23:47:22.735816 ==
4570 23:47:22.737840 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 23:47:22.741579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 23:47:22.745090 ==
4573 23:47:22.745637 RX Vref Scan: 1
4574 23:47:22.746002
4575 23:47:22.748110 RX Vref 0 -> 0, step: 1
4576 23:47:22.748570
4577 23:47:22.748937 RX Delay -195 -> 252, step: 8
4578 23:47:22.751413
4579 23:47:22.751962 Set Vref, RX VrefLevel [Byte0]: 54
4580 23:47:22.755023 [Byte1]: 53
4581 23:47:22.759885
4582 23:47:22.760453 Final RX Vref Byte 0 = 54 to rank0
4583 23:47:22.763407 Final RX Vref Byte 1 = 53 to rank0
4584 23:47:22.766320 Final RX Vref Byte 0 = 54 to rank1
4585 23:47:22.769304 Final RX Vref Byte 1 = 53 to rank1==
4586 23:47:22.773012 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 23:47:22.780286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 23:47:22.780911 ==
4589 23:47:22.781333 DQS Delay:
4590 23:47:22.781679 DQS0 = 0, DQS1 = 0
4591 23:47:22.782803 DQM Delay:
4592 23:47:22.783260 DQM0 = 40, DQM1 = 33
4593 23:47:22.786100 DQ Delay:
4594 23:47:22.789730 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4595 23:47:22.790236 DQ4 =44, DQ5 =48, DQ6 =52, DQ7 =36
4596 23:47:22.792803 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4597 23:47:22.796264 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4598 23:47:22.800074
4599 23:47:22.800619
4600 23:47:22.806711 [DQSOSCAuto] RK0, (LSB)MR18= 0x4309, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4601 23:47:22.809667 CH1 RK0: MR19=808, MR18=4309
4602 23:47:22.816725 CH1_RK0: MR19=0x808, MR18=0x4309, DQSOSC=397, MR23=63, INC=166, DEC=110
4603 23:47:22.817317
4604 23:47:22.819858 ----->DramcWriteLeveling(PI) begin...
4605 23:47:22.820433 ==
4606 23:47:22.823220 Dram Type= 6, Freq= 0, CH_1, rank 1
4607 23:47:22.826817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 23:47:22.827368 ==
4609 23:47:22.829533 Write leveling (Byte 0): 31 => 31
4610 23:47:22.833598 Write leveling (Byte 1): 31 => 31
4611 23:47:22.836449 DramcWriteLeveling(PI) end<-----
4612 23:47:22.836906
4613 23:47:22.837313 ==
4614 23:47:22.839933 Dram Type= 6, Freq= 0, CH_1, rank 1
4615 23:47:22.842917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 23:47:22.843381 ==
4617 23:47:22.846106 [Gating] SW mode calibration
4618 23:47:22.853475 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4619 23:47:22.859758 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4620 23:47:22.863503 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4621 23:47:22.866356 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4622 23:47:22.872923 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4623 23:47:22.876756 0 9 12 | B1->B0 | 3030 2929 | 1 0 | (0 0) (1 1)
4624 23:47:22.880009 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4625 23:47:22.886103 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 23:47:22.889494 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4627 23:47:22.892644 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 23:47:22.899418 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 23:47:22.902970 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 23:47:22.906558 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4631 23:47:22.913371 0 10 12 | B1->B0 | 3434 3c3c | 0 0 | (0 0) (0 0)
4632 23:47:22.916618 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4633 23:47:22.920070 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 23:47:22.926256 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 23:47:22.930024 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 23:47:22.933366 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 23:47:22.936928 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 23:47:22.943310 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 23:47:22.946260 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4640 23:47:22.949550 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4641 23:47:22.956631 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 23:47:22.959429 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 23:47:22.963100 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 23:47:22.970054 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 23:47:22.973461 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 23:47:22.976352 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 23:47:22.983020 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 23:47:22.986557 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 23:47:22.989439 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 23:47:22.996460 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 23:47:22.999997 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 23:47:23.003190 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 23:47:23.010001 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 23:47:23.013021 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 23:47:23.016796 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4656 23:47:23.020284 Total UI for P1: 0, mck2ui 16
4657 23:47:23.023717 best dqsien dly found for B0: ( 0, 13, 10)
4658 23:47:23.027041 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 23:47:23.030024 Total UI for P1: 0, mck2ui 16
4660 23:47:23.033671 best dqsien dly found for B1: ( 0, 13, 14)
4661 23:47:23.036697 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4662 23:47:23.039802 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4663 23:47:23.043219
4664 23:47:23.047052 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4665 23:47:23.050430 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4666 23:47:23.053180 [Gating] SW calibration Done
4667 23:47:23.053728 ==
4668 23:47:23.057069 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 23:47:23.060000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 23:47:23.060589 ==
4671 23:47:23.060970 RX Vref Scan: 0
4672 23:47:23.061345
4673 23:47:23.063519 RX Vref 0 -> 0, step: 1
4674 23:47:23.064065
4675 23:47:23.066892 RX Delay -230 -> 252, step: 16
4676 23:47:23.069774 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4677 23:47:23.073755 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4678 23:47:23.080439 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4679 23:47:23.083273 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4680 23:47:23.086509 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4681 23:47:23.090066 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4682 23:47:23.096745 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4683 23:47:23.099793 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4684 23:47:23.103790 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4685 23:47:23.106339 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4686 23:47:23.109804 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4687 23:47:23.116925 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4688 23:47:23.119979 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4689 23:47:23.123067 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4690 23:47:23.126605 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4691 23:47:23.133264 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4692 23:47:23.133786 ==
4693 23:47:23.136249 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 23:47:23.139644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 23:47:23.140164 ==
4696 23:47:23.140583 DQS Delay:
4697 23:47:23.142861 DQS0 = 0, DQS1 = 0
4698 23:47:23.143395 DQM Delay:
4699 23:47:23.146091 DQM0 = 39, DQM1 = 36
4700 23:47:23.146543 DQ Delay:
4701 23:47:23.149994 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4702 23:47:23.153053 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4703 23:47:23.156261 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4704 23:47:23.159979 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4705 23:47:23.160431
4706 23:47:23.160935
4707 23:47:23.161329 ==
4708 23:47:23.163080 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 23:47:23.166354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 23:47:23.166774 ==
4711 23:47:23.167108
4712 23:47:23.167413
4713 23:47:23.169371 TX Vref Scan disable
4714 23:47:23.173042 == TX Byte 0 ==
4715 23:47:23.176842 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4716 23:47:23.179797 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4717 23:47:23.182910 == TX Byte 1 ==
4718 23:47:23.186333 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4719 23:47:23.189685 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4720 23:47:23.190104 ==
4721 23:47:23.193041 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 23:47:23.199974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 23:47:23.200383 ==
4724 23:47:23.200721
4725 23:47:23.201053
4726 23:47:23.201349 TX Vref Scan disable
4727 23:47:23.204153 == TX Byte 0 ==
4728 23:47:23.207489 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4729 23:47:23.210994 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4730 23:47:23.213883 == TX Byte 1 ==
4731 23:47:23.217323 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4732 23:47:23.224149 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4733 23:47:23.224605
4734 23:47:23.225068 [DATLAT]
4735 23:47:23.225446 Freq=600, CH1 RK1
4736 23:47:23.225758
4737 23:47:23.227395 DATLAT Default: 0x9
4738 23:47:23.227929 0, 0xFFFF, sum = 0
4739 23:47:23.230980 1, 0xFFFF, sum = 0
4740 23:47:23.231489 2, 0xFFFF, sum = 0
4741 23:47:23.234187 3, 0xFFFF, sum = 0
4742 23:47:23.234620 4, 0xFFFF, sum = 0
4743 23:47:23.237420 5, 0xFFFF, sum = 0
4744 23:47:23.240378 6, 0xFFFF, sum = 0
4745 23:47:23.240843 7, 0xFFFF, sum = 0
4746 23:47:23.241233 8, 0x0, sum = 1
4747 23:47:23.243908 9, 0x0, sum = 2
4748 23:47:23.244428 10, 0x0, sum = 3
4749 23:47:23.247462 11, 0x0, sum = 4
4750 23:47:23.248067 best_step = 9
4751 23:47:23.248517
4752 23:47:23.249036 ==
4753 23:47:23.250571 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 23:47:23.257280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 23:47:23.257733 ==
4756 23:47:23.258092 RX Vref Scan: 0
4757 23:47:23.258493
4758 23:47:23.261072 RX Vref 0 -> 0, step: 1
4759 23:47:23.261675
4760 23:47:23.264125 RX Delay -179 -> 252, step: 8
4761 23:47:23.267290 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4762 23:47:23.274447 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4763 23:47:23.277433 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4764 23:47:23.280566 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4765 23:47:23.284303 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4766 23:47:23.287728 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4767 23:47:23.294258 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4768 23:47:23.297671 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4769 23:47:23.301040 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4770 23:47:23.304345 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4771 23:47:23.307651 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4772 23:47:23.314344 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4773 23:47:23.317338 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4774 23:47:23.322254 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4775 23:47:23.324284 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4776 23:47:23.330885 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4777 23:47:23.331360 ==
4778 23:47:23.334484 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 23:47:23.337827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 23:47:23.338250 ==
4781 23:47:23.338582 DQS Delay:
4782 23:47:23.341110 DQS0 = 0, DQS1 = 0
4783 23:47:23.341619 DQM Delay:
4784 23:47:23.343944 DQM0 = 38, DQM1 = 33
4785 23:47:23.344449 DQ Delay:
4786 23:47:23.348030 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4787 23:47:23.351686 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4788 23:47:23.354190 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4789 23:47:23.358013 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4790 23:47:23.358569
4791 23:47:23.359033
4792 23:47:23.364004 [DQSOSCAuto] RK1, (LSB)MR18= 0x3342, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
4793 23:47:23.367753 CH1 RK1: MR19=808, MR18=3342
4794 23:47:23.374389 CH1_RK1: MR19=0x808, MR18=0x3342, DQSOSC=397, MR23=63, INC=166, DEC=110
4795 23:47:23.378458 [RxdqsGatingPostProcess] freq 600
4796 23:47:23.384650 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4797 23:47:23.387985 Pre-setting of DQS Precalculation
4798 23:47:23.391616 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4799 23:47:23.398069 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4800 23:47:23.404830 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4801 23:47:23.405464
4802 23:47:23.405833
4803 23:47:23.407998 [Calibration Summary] 1200 Mbps
4804 23:47:23.411344 CH 0, Rank 0
4805 23:47:23.411800 SW Impedance : PASS
4806 23:47:23.414974 DUTY Scan : NO K
4807 23:47:23.417965 ZQ Calibration : PASS
4808 23:47:23.418518 Jitter Meter : NO K
4809 23:47:23.421869 CBT Training : PASS
4810 23:47:23.422420 Write leveling : PASS
4811 23:47:23.424749 RX DQS gating : PASS
4812 23:47:23.428187 RX DQ/DQS(RDDQC) : PASS
4813 23:47:23.428743 TX DQ/DQS : PASS
4814 23:47:23.431212 RX DATLAT : PASS
4815 23:47:23.434832 RX DQ/DQS(Engine): PASS
4816 23:47:23.435385 TX OE : NO K
4817 23:47:23.437532 All Pass.
4818 23:47:23.438011
4819 23:47:23.438389 CH 0, Rank 1
4820 23:47:23.441013 SW Impedance : PASS
4821 23:47:23.441586 DUTY Scan : NO K
4822 23:47:23.444547 ZQ Calibration : PASS
4823 23:47:23.447861 Jitter Meter : NO K
4824 23:47:23.448318 CBT Training : PASS
4825 23:47:23.451647 Write leveling : PASS
4826 23:47:23.454808 RX DQS gating : PASS
4827 23:47:23.455419 RX DQ/DQS(RDDQC) : PASS
4828 23:47:23.458118 TX DQ/DQS : PASS
4829 23:47:23.458671 RX DATLAT : PASS
4830 23:47:23.461163 RX DQ/DQS(Engine): PASS
4831 23:47:23.464614 TX OE : NO K
4832 23:47:23.465206 All Pass.
4833 23:47:23.465580
4834 23:47:23.465921 CH 1, Rank 0
4835 23:47:23.468337 SW Impedance : PASS
4836 23:47:23.471446 DUTY Scan : NO K
4837 23:47:23.472241 ZQ Calibration : PASS
4838 23:47:23.474446 Jitter Meter : NO K
4839 23:47:23.477823 CBT Training : PASS
4840 23:47:23.478283 Write leveling : PASS
4841 23:47:23.481517 RX DQS gating : PASS
4842 23:47:23.484888 RX DQ/DQS(RDDQC) : PASS
4843 23:47:23.485506 TX DQ/DQS : PASS
4844 23:47:23.487942 RX DATLAT : PASS
4845 23:47:23.490969 RX DQ/DQS(Engine): PASS
4846 23:47:23.491430 TX OE : NO K
4847 23:47:23.494559 All Pass.
4848 23:47:23.495016
4849 23:47:23.495381 CH 1, Rank 1
4850 23:47:23.497757 SW Impedance : PASS
4851 23:47:23.498216 DUTY Scan : NO K
4852 23:47:23.501008 ZQ Calibration : PASS
4853 23:47:23.504568 Jitter Meter : NO K
4854 23:47:23.505072 CBT Training : PASS
4855 23:47:23.508162 Write leveling : PASS
4856 23:47:23.508620 RX DQS gating : PASS
4857 23:47:23.510893 RX DQ/DQS(RDDQC) : PASS
4858 23:47:23.514583 TX DQ/DQS : PASS
4859 23:47:23.515004 RX DATLAT : PASS
4860 23:47:23.518431 RX DQ/DQS(Engine): PASS
4861 23:47:23.521339 TX OE : NO K
4862 23:47:23.521854 All Pass.
4863 23:47:23.522232
4864 23:47:23.524433 DramC Write-DBI off
4865 23:47:23.524952 PER_BANK_REFRESH: Hybrid Mode
4866 23:47:23.527902 TX_TRACKING: ON
4867 23:47:23.534789 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4868 23:47:23.541417 [FAST_K] Save calibration result to emmc
4869 23:47:23.544251 dramc_set_vcore_voltage set vcore to 662500
4870 23:47:23.544671 Read voltage for 933, 3
4871 23:47:23.547475 Vio18 = 0
4872 23:47:23.547888 Vcore = 662500
4873 23:47:23.548218 Vdram = 0
4874 23:47:23.550665 Vddq = 0
4875 23:47:23.551080 Vmddr = 0
4876 23:47:23.554032 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4877 23:47:23.561052 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4878 23:47:23.564789 MEM_TYPE=3, freq_sel=17
4879 23:47:23.568135 sv_algorithm_assistance_LP4_1600
4880 23:47:23.570680 ============ PULL DRAM RESETB DOWN ============
4881 23:47:23.574126 ========== PULL DRAM RESETB DOWN end =========
4882 23:47:23.577726 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4883 23:47:23.580726 ===================================
4884 23:47:23.584766 LPDDR4 DRAM CONFIGURATION
4885 23:47:23.588343 ===================================
4886 23:47:23.591044 EX_ROW_EN[0] = 0x0
4887 23:47:23.591596 EX_ROW_EN[1] = 0x0
4888 23:47:23.594349 LP4Y_EN = 0x0
4889 23:47:23.594901 WORK_FSP = 0x0
4890 23:47:23.597838 WL = 0x3
4891 23:47:23.598387 RL = 0x3
4892 23:47:23.601182 BL = 0x2
4893 23:47:23.601639 RPST = 0x0
4894 23:47:23.604604 RD_PRE = 0x0
4895 23:47:23.605097 WR_PRE = 0x1
4896 23:47:23.607609 WR_PST = 0x0
4897 23:47:23.608067 DBI_WR = 0x0
4898 23:47:23.611012 DBI_RD = 0x0
4899 23:47:23.614475 OTF = 0x1
4900 23:47:23.614936 ===================================
4901 23:47:23.617956 ===================================
4902 23:47:23.621863 ANA top config
4903 23:47:23.624905 ===================================
4904 23:47:23.628180 DLL_ASYNC_EN = 0
4905 23:47:23.628645 ALL_SLAVE_EN = 1
4906 23:47:23.631463 NEW_RANK_MODE = 1
4907 23:47:23.634867 DLL_IDLE_MODE = 1
4908 23:47:23.638379 LP45_APHY_COMB_EN = 1
4909 23:47:23.638928 TX_ODT_DIS = 1
4910 23:47:23.641297 NEW_8X_MODE = 1
4911 23:47:23.644762 ===================================
4912 23:47:23.647877 ===================================
4913 23:47:23.651363 data_rate = 1866
4914 23:47:23.655004 CKR = 1
4915 23:47:23.658021 DQ_P2S_RATIO = 8
4916 23:47:23.661640 ===================================
4917 23:47:23.664898 CA_P2S_RATIO = 8
4918 23:47:23.665488 DQ_CA_OPEN = 0
4919 23:47:23.668693 DQ_SEMI_OPEN = 0
4920 23:47:23.671303 CA_SEMI_OPEN = 0
4921 23:47:23.674605 CA_FULL_RATE = 0
4922 23:47:23.678171 DQ_CKDIV4_EN = 1
4923 23:47:23.681464 CA_CKDIV4_EN = 1
4924 23:47:23.682058 CA_PREDIV_EN = 0
4925 23:47:23.684870 PH8_DLY = 0
4926 23:47:23.688101 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4927 23:47:23.691366 DQ_AAMCK_DIV = 4
4928 23:47:23.694456 CA_AAMCK_DIV = 4
4929 23:47:23.697841 CA_ADMCK_DIV = 4
4930 23:47:23.698366 DQ_TRACK_CA_EN = 0
4931 23:47:23.701374 CA_PICK = 933
4932 23:47:23.704551 CA_MCKIO = 933
4933 23:47:23.708062 MCKIO_SEMI = 0
4934 23:47:23.711235 PLL_FREQ = 3732
4935 23:47:23.714947 DQ_UI_PI_RATIO = 32
4936 23:47:23.715410 CA_UI_PI_RATIO = 0
4937 23:47:23.718571 ===================================
4938 23:47:23.721636 ===================================
4939 23:47:23.725229 memory_type:LPDDR4
4940 23:47:23.728372 GP_NUM : 10
4941 23:47:23.728922 SRAM_EN : 1
4942 23:47:23.731359 MD32_EN : 0
4943 23:47:23.734968 ===================================
4944 23:47:23.737761 [ANA_INIT] >>>>>>>>>>>>>>
4945 23:47:23.741528 <<<<<< [CONFIGURE PHASE]: ANA_TX
4946 23:47:23.744602 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4947 23:47:23.748673 ===================================
4948 23:47:23.749177 data_rate = 1866,PCW = 0X8f00
4949 23:47:23.751478 ===================================
4950 23:47:23.754548 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4951 23:47:23.761834 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4952 23:47:23.768740 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4953 23:47:23.771489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4954 23:47:23.774703 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4955 23:47:23.778758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4956 23:47:23.781813 [ANA_INIT] flow start
4957 23:47:23.782336 [ANA_INIT] PLL >>>>>>>>
4958 23:47:23.785233 [ANA_INIT] PLL <<<<<<<<
4959 23:47:23.788181 [ANA_INIT] MIDPI >>>>>>>>
4960 23:47:23.791543 [ANA_INIT] MIDPI <<<<<<<<
4961 23:47:23.792096 [ANA_INIT] DLL >>>>>>>>
4962 23:47:23.794844 [ANA_INIT] flow end
4963 23:47:23.798019 ============ LP4 DIFF to SE enter ============
4964 23:47:23.801635 ============ LP4 DIFF to SE exit ============
4965 23:47:23.805168 [ANA_INIT] <<<<<<<<<<<<<
4966 23:47:23.808586 [Flow] Enable top DCM control >>>>>
4967 23:47:23.811602 [Flow] Enable top DCM control <<<<<
4968 23:47:23.814831 Enable DLL master slave shuffle
4969 23:47:23.818415 ==============================================================
4970 23:47:23.821395 Gating Mode config
4971 23:47:23.828443 ==============================================================
4972 23:47:23.829065 Config description:
4973 23:47:23.838518 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4974 23:47:23.845124 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4975 23:47:23.848277 SELPH_MODE 0: By rank 1: By Phase
4976 23:47:23.855176 ==============================================================
4977 23:47:23.858393 GAT_TRACK_EN = 1
4978 23:47:23.861732 RX_GATING_MODE = 2
4979 23:47:23.865287 RX_GATING_TRACK_MODE = 2
4980 23:47:23.868472 SELPH_MODE = 1
4981 23:47:23.871749 PICG_EARLY_EN = 1
4982 23:47:23.875122 VALID_LAT_VALUE = 1
4983 23:47:23.878608 ==============================================================
4984 23:47:23.882025 Enter into Gating configuration >>>>
4985 23:47:23.885658 Exit from Gating configuration <<<<
4986 23:47:23.888295 Enter into DVFS_PRE_config >>>>>
4987 23:47:23.898621 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4988 23:47:23.902434 Exit from DVFS_PRE_config <<<<<
4989 23:47:23.905355 Enter into PICG configuration >>>>
4990 23:47:23.908521 Exit from PICG configuration <<<<
4991 23:47:23.912406 [RX_INPUT] configuration >>>>>
4992 23:47:23.915502 [RX_INPUT] configuration <<<<<
4993 23:47:23.918936 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4994 23:47:23.925696 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4995 23:47:23.932408 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4996 23:47:23.938817 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4997 23:47:23.945611 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4998 23:47:23.951906 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4999 23:47:23.955248 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5000 23:47:23.958985 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5001 23:47:23.961945 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5002 23:47:23.965085 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5003 23:47:23.972308 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5004 23:47:23.975440 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 23:47:23.979135 ===================================
5006 23:47:23.981720 LPDDR4 DRAM CONFIGURATION
5007 23:47:23.984856 ===================================
5008 23:47:23.985336 EX_ROW_EN[0] = 0x0
5009 23:47:23.988769 EX_ROW_EN[1] = 0x0
5010 23:47:23.989283 LP4Y_EN = 0x0
5011 23:47:23.992022 WORK_FSP = 0x0
5012 23:47:23.992569 WL = 0x3
5013 23:47:23.995589 RL = 0x3
5014 23:47:23.996192 BL = 0x2
5015 23:47:23.998702 RPST = 0x0
5016 23:47:23.999171 RD_PRE = 0x0
5017 23:47:24.001808 WR_PRE = 0x1
5018 23:47:24.002261 WR_PST = 0x0
5019 23:47:24.005411 DBI_WR = 0x0
5020 23:47:24.008550 DBI_RD = 0x0
5021 23:47:24.009044 OTF = 0x1
5022 23:47:24.011801 ===================================
5023 23:47:24.015319 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5024 23:47:24.018984 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5025 23:47:24.024881 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5026 23:47:24.028889 ===================================
5027 23:47:24.032250 LPDDR4 DRAM CONFIGURATION
5028 23:47:24.032755 ===================================
5029 23:47:24.035657 EX_ROW_EN[0] = 0x10
5030 23:47:24.038438 EX_ROW_EN[1] = 0x0
5031 23:47:24.038851 LP4Y_EN = 0x0
5032 23:47:24.041955 WORK_FSP = 0x0
5033 23:47:24.042369 WL = 0x3
5034 23:47:24.045352 RL = 0x3
5035 23:47:24.045856 BL = 0x2
5036 23:47:24.048478 RPST = 0x0
5037 23:47:24.048895 RD_PRE = 0x0
5038 23:47:24.051956 WR_PRE = 0x1
5039 23:47:24.052481 WR_PST = 0x0
5040 23:47:24.055462 DBI_WR = 0x0
5041 23:47:24.055934 DBI_RD = 0x0
5042 23:47:24.058262 OTF = 0x1
5043 23:47:24.061882 ===================================
5044 23:47:24.069058 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5045 23:47:24.072006 nWR fixed to 30
5046 23:47:24.075155 [ModeRegInit_LP4] CH0 RK0
5047 23:47:24.075648 [ModeRegInit_LP4] CH0 RK1
5048 23:47:24.078357 [ModeRegInit_LP4] CH1 RK0
5049 23:47:24.081775 [ModeRegInit_LP4] CH1 RK1
5050 23:47:24.082186 match AC timing 9
5051 23:47:24.089118 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5052 23:47:24.091839 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5053 23:47:24.094795 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5054 23:47:24.101897 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5055 23:47:24.104822 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5056 23:47:24.105278 ==
5057 23:47:24.108208 Dram Type= 6, Freq= 0, CH_0, rank 0
5058 23:47:24.112324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 23:47:24.112836 ==
5060 23:47:24.118655 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 23:47:24.124735 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5062 23:47:24.128235 [CA 0] Center 38 (8~69) winsize 62
5063 23:47:24.131711 [CA 1] Center 38 (7~69) winsize 63
5064 23:47:24.134985 [CA 2] Center 35 (5~66) winsize 62
5065 23:47:24.138279 [CA 3] Center 35 (5~65) winsize 61
5066 23:47:24.141950 [CA 4] Center 34 (4~65) winsize 62
5067 23:47:24.145268 [CA 5] Center 33 (3~64) winsize 62
5068 23:47:24.145775
5069 23:47:24.148419 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5070 23:47:24.148967
5071 23:47:24.151789 [CATrainingPosCal] consider 1 rank data
5072 23:47:24.154967 u2DelayCellTimex100 = 270/100 ps
5073 23:47:24.158512 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5074 23:47:24.161337 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5075 23:47:24.165114 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5076 23:47:24.168337 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5077 23:47:24.171617 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5078 23:47:24.174890 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5079 23:47:24.175391
5080 23:47:24.182258 CA PerBit enable=1, Macro0, CA PI delay=33
5081 23:47:24.182764
5082 23:47:24.183160 [CBTSetCACLKResult] CA Dly = 33
5083 23:47:24.185068 CS Dly: 6 (0~37)
5084 23:47:24.185484 ==
5085 23:47:24.188874 Dram Type= 6, Freq= 0, CH_0, rank 1
5086 23:47:24.191777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 23:47:24.192392 ==
5088 23:47:24.199200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5089 23:47:24.205242 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5090 23:47:24.208603 [CA 0] Center 38 (8~69) winsize 62
5091 23:47:24.212008 [CA 1] Center 38 (7~69) winsize 63
5092 23:47:24.215588 [CA 2] Center 35 (5~66) winsize 62
5093 23:47:24.218916 [CA 3] Center 35 (5~66) winsize 62
5094 23:47:24.221948 [CA 4] Center 33 (3~64) winsize 62
5095 23:47:24.225383 [CA 5] Center 33 (3~64) winsize 62
5096 23:47:24.225843
5097 23:47:24.228655 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5098 23:47:24.229239
5099 23:47:24.232185 [CATrainingPosCal] consider 2 rank data
5100 23:47:24.235226 u2DelayCellTimex100 = 270/100 ps
5101 23:47:24.238650 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5102 23:47:24.241847 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5103 23:47:24.245093 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5104 23:47:24.248780 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5105 23:47:24.252277 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5106 23:47:24.255319 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5107 23:47:24.255777
5108 23:47:24.258707 CA PerBit enable=1, Macro0, CA PI delay=33
5109 23:47:24.261913
5110 23:47:24.262463 [CBTSetCACLKResult] CA Dly = 33
5111 23:47:24.265312 CS Dly: 7 (0~39)
5112 23:47:24.265766
5113 23:47:24.268728 ----->DramcWriteLeveling(PI) begin...
5114 23:47:24.269223 ==
5115 23:47:24.271834 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 23:47:24.275040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 23:47:24.275515 ==
5118 23:47:24.278759 Write leveling (Byte 0): 27 => 27
5119 23:47:24.282329 Write leveling (Byte 1): 25 => 25
5120 23:47:24.285296 DramcWriteLeveling(PI) end<-----
5121 23:47:24.285749
5122 23:47:24.286161 ==
5123 23:47:24.288909 Dram Type= 6, Freq= 0, CH_0, rank 0
5124 23:47:24.292755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 23:47:24.293360 ==
5126 23:47:24.295398 [Gating] SW mode calibration
5127 23:47:24.302187 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5128 23:47:24.308846 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5129 23:47:24.312346 0 14 0 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
5130 23:47:24.318795 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5131 23:47:24.321780 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 23:47:24.325698 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 23:47:24.331855 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 23:47:24.335335 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 23:47:24.338710 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 23:47:24.342382 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 23:47:24.348741 0 15 0 | B1->B0 | 3030 2c2c | 1 0 | (1 1) (0 0)
5138 23:47:24.352097 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (1 0) (1 0)
5139 23:47:24.355279 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 23:47:24.362567 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 23:47:24.365569 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 23:47:24.368949 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 23:47:24.375338 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 23:47:24.378384 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5145 23:47:24.382336 1 0 0 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (0 0)
5146 23:47:24.388657 1 0 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5147 23:47:24.391945 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 23:47:24.394952 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 23:47:24.402325 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 23:47:24.405345 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 23:47:24.408418 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 23:47:24.415430 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 23:47:24.418861 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5154 23:47:24.422629 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5155 23:47:24.428797 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 23:47:24.431996 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 23:47:24.435193 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 23:47:24.438820 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 23:47:24.445062 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 23:47:24.448211 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 23:47:24.452247 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 23:47:24.458586 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 23:47:24.461765 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 23:47:24.465428 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 23:47:24.471899 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 23:47:24.475427 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 23:47:24.478258 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 23:47:24.485297 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5169 23:47:24.488373 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5170 23:47:24.492082 Total UI for P1: 0, mck2ui 16
5171 23:47:24.495059 best dqsien dly found for B0: ( 1, 2, 28)
5172 23:47:24.498676 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5173 23:47:24.505088 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 23:47:24.505553 Total UI for P1: 0, mck2ui 16
5175 23:47:24.512243 best dqsien dly found for B1: ( 1, 3, 0)
5176 23:47:24.514888 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5177 23:47:24.518482 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5178 23:47:24.518901
5179 23:47:24.521683 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5180 23:47:24.525114 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5181 23:47:24.528455 [Gating] SW calibration Done
5182 23:47:24.528953 ==
5183 23:47:24.532049 Dram Type= 6, Freq= 0, CH_0, rank 0
5184 23:47:24.535385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5185 23:47:24.535897 ==
5186 23:47:24.538275 RX Vref Scan: 0
5187 23:47:24.538692
5188 23:47:24.539023 RX Vref 0 -> 0, step: 1
5189 23:47:24.539332
5190 23:47:24.541710 RX Delay -80 -> 252, step: 8
5191 23:47:24.545572 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5192 23:47:24.548441 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5193 23:47:24.555258 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5194 23:47:24.558754 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5195 23:47:24.561947 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5196 23:47:24.565425 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5197 23:47:24.568433 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5198 23:47:24.572274 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5199 23:47:24.578523 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5200 23:47:24.581537 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5201 23:47:24.585367 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5202 23:47:24.588589 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5203 23:47:24.592244 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5204 23:47:24.595600 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5205 23:47:24.601681 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5206 23:47:24.605514 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5207 23:47:24.606059 ==
5208 23:47:24.608691 Dram Type= 6, Freq= 0, CH_0, rank 0
5209 23:47:24.612029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5210 23:47:24.612575 ==
5211 23:47:24.612946 DQS Delay:
5212 23:47:24.615273 DQS0 = 0, DQS1 = 0
5213 23:47:24.615824 DQM Delay:
5214 23:47:24.618927 DQM0 = 97, DQM1 = 86
5215 23:47:24.619606 DQ Delay:
5216 23:47:24.622070 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5217 23:47:24.625653 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5218 23:47:24.628471 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5219 23:47:24.633118 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5220 23:47:24.633665
5221 23:47:24.634030
5222 23:47:24.634371 ==
5223 23:47:24.635318 Dram Type= 6, Freq= 0, CH_0, rank 0
5224 23:47:24.641843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5225 23:47:24.642382 ==
5226 23:47:24.642748
5227 23:47:24.643084
5228 23:47:24.643402 TX Vref Scan disable
5229 23:47:24.645409 == TX Byte 0 ==
5230 23:47:24.648820 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5231 23:47:24.652018 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5232 23:47:24.655564 == TX Byte 1 ==
5233 23:47:24.658865 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5234 23:47:24.661786 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5235 23:47:24.665071 ==
5236 23:47:24.668414 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 23:47:24.671854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 23:47:24.672314 ==
5239 23:47:24.672674
5240 23:47:24.673082
5241 23:47:24.674902 TX Vref Scan disable
5242 23:47:24.675356 == TX Byte 0 ==
5243 23:47:24.681443 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5244 23:47:24.684857 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5245 23:47:24.685346 == TX Byte 1 ==
5246 23:47:24.691976 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5247 23:47:24.695140 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5248 23:47:24.695598
5249 23:47:24.695981 [DATLAT]
5250 23:47:24.698355 Freq=933, CH0 RK0
5251 23:47:24.698810
5252 23:47:24.699170 DATLAT Default: 0xd
5253 23:47:24.701781 0, 0xFFFF, sum = 0
5254 23:47:24.702243 1, 0xFFFF, sum = 0
5255 23:47:24.704896 2, 0xFFFF, sum = 0
5256 23:47:24.705389 3, 0xFFFF, sum = 0
5257 23:47:24.708501 4, 0xFFFF, sum = 0
5258 23:47:24.708963 5, 0xFFFF, sum = 0
5259 23:47:24.711829 6, 0xFFFF, sum = 0
5260 23:47:24.712473 7, 0xFFFF, sum = 0
5261 23:47:24.715385 8, 0xFFFF, sum = 0
5262 23:47:24.718160 9, 0xFFFF, sum = 0
5263 23:47:24.718582 10, 0x0, sum = 1
5264 23:47:24.718917 11, 0x0, sum = 2
5265 23:47:24.721408 12, 0x0, sum = 3
5266 23:47:24.721881 13, 0x0, sum = 4
5267 23:47:24.725064 best_step = 11
5268 23:47:24.725477
5269 23:47:24.725803 ==
5270 23:47:24.727998 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 23:47:24.731872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 23:47:24.732388 ==
5273 23:47:24.735297 RX Vref Scan: 1
5274 23:47:24.735813
5275 23:47:24.736151 RX Vref 0 -> 0, step: 1
5276 23:47:24.736463
5277 23:47:24.738243 RX Delay -61 -> 252, step: 4
5278 23:47:24.738746
5279 23:47:24.741646 Set Vref, RX VrefLevel [Byte0]: 54
5280 23:47:24.744963 [Byte1]: 52
5281 23:47:24.748836
5282 23:47:24.749525 Final RX Vref Byte 0 = 54 to rank0
5283 23:47:24.752491 Final RX Vref Byte 1 = 52 to rank0
5284 23:47:24.755790 Final RX Vref Byte 0 = 54 to rank1
5285 23:47:24.758958 Final RX Vref Byte 1 = 52 to rank1==
5286 23:47:24.762155 Dram Type= 6, Freq= 0, CH_0, rank 0
5287 23:47:24.769393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5288 23:47:24.769898 ==
5289 23:47:24.770231 DQS Delay:
5290 23:47:24.770540 DQS0 = 0, DQS1 = 0
5291 23:47:24.772739 DQM Delay:
5292 23:47:24.773223 DQM0 = 97, DQM1 = 88
5293 23:47:24.775979 DQ Delay:
5294 23:47:24.776386 DQ0 =98, DQ1 =98, DQ2 =94, DQ3 =94
5295 23:47:24.778966 DQ4 =98, DQ5 =86, DQ6 =106, DQ7 =102
5296 23:47:24.782401 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =80
5297 23:47:24.785767 DQ12 =94, DQ13 =90, DQ14 =98, DQ15 =98
5298 23:47:24.788931
5299 23:47:24.789379
5300 23:47:24.795846 [DQSOSCAuto] RK0, (LSB)MR18= 0x1501, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 415 ps
5301 23:47:24.799217 CH0 RK0: MR19=505, MR18=1501
5302 23:47:24.806270 CH0_RK0: MR19=0x505, MR18=0x1501, DQSOSC=415, MR23=63, INC=62, DEC=41
5303 23:47:24.806759
5304 23:47:24.809441 ----->DramcWriteLeveling(PI) begin...
5305 23:47:24.810094 ==
5306 23:47:24.812463 Dram Type= 6, Freq= 0, CH_0, rank 1
5307 23:47:24.815759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5308 23:47:24.816169 ==
5309 23:47:24.819394 Write leveling (Byte 0): 33 => 33
5310 23:47:24.822494 Write leveling (Byte 1): 30 => 30
5311 23:47:24.826167 DramcWriteLeveling(PI) end<-----
5312 23:47:24.826573
5313 23:47:24.826896 ==
5314 23:47:24.829204 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 23:47:24.832892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 23:47:24.833454 ==
5317 23:47:24.835996 [Gating] SW mode calibration
5318 23:47:24.842216 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5319 23:47:24.849600 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5320 23:47:24.852261 0 14 0 | B1->B0 | 2424 3434 | 1 1 | (1 1) (1 1)
5321 23:47:24.855444 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5322 23:47:24.862560 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 23:47:24.865881 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 23:47:24.869932 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 23:47:24.875848 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 23:47:24.879303 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5327 23:47:24.882893 0 14 28 | B1->B0 | 3434 3131 | 0 0 | (0 0) (1 1)
5328 23:47:24.889149 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5329 23:47:24.892562 0 15 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5330 23:47:24.895796 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 23:47:24.902645 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 23:47:24.906127 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 23:47:24.909455 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 23:47:24.915814 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 23:47:24.919330 0 15 28 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5336 23:47:24.922181 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5337 23:47:24.925676 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5338 23:47:24.932406 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 23:47:24.936326 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 23:47:24.939301 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 23:47:24.945849 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 23:47:24.949262 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 23:47:24.952832 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5344 23:47:24.959739 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5345 23:47:24.962720 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 23:47:24.965745 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 23:47:24.972815 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 23:47:24.976100 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 23:47:24.979167 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 23:47:24.985632 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 23:47:24.989085 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 23:47:24.992814 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 23:47:24.999470 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 23:47:25.002904 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 23:47:25.005908 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 23:47:25.012617 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 23:47:25.016417 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 23:47:25.019756 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5359 23:47:25.023200 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5360 23:47:25.026564 Total UI for P1: 0, mck2ui 16
5361 23:47:25.029661 best dqsien dly found for B0: ( 1, 2, 24)
5362 23:47:25.036141 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5363 23:47:25.039409 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 23:47:25.042912 Total UI for P1: 0, mck2ui 16
5365 23:47:25.046333 best dqsien dly found for B1: ( 1, 2, 30)
5366 23:47:25.049440 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5367 23:47:25.052640 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5368 23:47:25.053136
5369 23:47:25.056110 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5370 23:47:25.059135 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5371 23:47:25.062748 [Gating] SW calibration Done
5372 23:47:25.063368 ==
5373 23:47:25.065984 Dram Type= 6, Freq= 0, CH_0, rank 1
5374 23:47:25.069902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 23:47:25.072750 ==
5376 23:47:25.073338 RX Vref Scan: 0
5377 23:47:25.073707
5378 23:47:25.076052 RX Vref 0 -> 0, step: 1
5379 23:47:25.076730
5380 23:47:25.079404 RX Delay -80 -> 252, step: 8
5381 23:47:25.082547 iDelay=200, Bit 0, Center 99 (0 ~ 199) 200
5382 23:47:25.086210 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5383 23:47:25.089055 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5384 23:47:25.092743 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5385 23:47:25.095588 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5386 23:47:25.098968 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5387 23:47:25.105892 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5388 23:47:25.109361 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5389 23:47:25.112785 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5390 23:47:25.115853 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5391 23:47:25.119883 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5392 23:47:25.126508 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5393 23:47:25.129413 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5394 23:47:25.132559 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5395 23:47:25.136131 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5396 23:47:25.139482 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5397 23:47:25.139940 ==
5398 23:47:25.142849 Dram Type= 6, Freq= 0, CH_0, rank 1
5399 23:47:25.149323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5400 23:47:25.149810 ==
5401 23:47:25.150184 DQS Delay:
5402 23:47:25.150524 DQS0 = 0, DQS1 = 0
5403 23:47:25.152747 DQM Delay:
5404 23:47:25.153261 DQM0 = 97, DQM1 = 87
5405 23:47:25.156043 DQ Delay:
5406 23:47:25.159442 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5407 23:47:25.162738 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =103
5408 23:47:25.166243 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5409 23:47:25.169167 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5410 23:47:25.169723
5411 23:47:25.170285
5412 23:47:25.170656 ==
5413 23:47:25.172655 Dram Type= 6, Freq= 0, CH_0, rank 1
5414 23:47:25.175659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5415 23:47:25.176120 ==
5416 23:47:25.176478
5417 23:47:25.176885
5418 23:47:25.179076 TX Vref Scan disable
5419 23:47:25.179529 == TX Byte 0 ==
5420 23:47:25.186398 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5421 23:47:25.189073 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5422 23:47:25.189533 == TX Byte 1 ==
5423 23:47:25.196067 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5424 23:47:25.199257 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5425 23:47:25.199712 ==
5426 23:47:25.202301 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 23:47:25.206240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 23:47:25.206792 ==
5429 23:47:25.207157
5430 23:47:25.207498
5431 23:47:25.208972 TX Vref Scan disable
5432 23:47:25.213019 == TX Byte 0 ==
5433 23:47:25.216018 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5434 23:47:25.219242 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5435 23:47:25.222704 == TX Byte 1 ==
5436 23:47:25.226486 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5437 23:47:25.229438 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5438 23:47:25.229987
5439 23:47:25.233040 [DATLAT]
5440 23:47:25.233589 Freq=933, CH0 RK1
5441 23:47:25.233954
5442 23:47:25.236194 DATLAT Default: 0xb
5443 23:47:25.236742 0, 0xFFFF, sum = 0
5444 23:47:25.239301 1, 0xFFFF, sum = 0
5445 23:47:25.239765 2, 0xFFFF, sum = 0
5446 23:47:25.242422 3, 0xFFFF, sum = 0
5447 23:47:25.242936 4, 0xFFFF, sum = 0
5448 23:47:25.246337 5, 0xFFFF, sum = 0
5449 23:47:25.246854 6, 0xFFFF, sum = 0
5450 23:47:25.249460 7, 0xFFFF, sum = 0
5451 23:47:25.249940 8, 0xFFFF, sum = 0
5452 23:47:25.253061 9, 0xFFFF, sum = 0
5453 23:47:25.253525 10, 0x0, sum = 1
5454 23:47:25.255842 11, 0x0, sum = 2
5455 23:47:25.256299 12, 0x0, sum = 3
5456 23:47:25.259569 13, 0x0, sum = 4
5457 23:47:25.260056 best_step = 11
5458 23:47:25.260416
5459 23:47:25.260817 ==
5460 23:47:25.262453 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 23:47:25.266082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 23:47:25.269300 ==
5463 23:47:25.269719 RX Vref Scan: 0
5464 23:47:25.270050
5465 23:47:25.272617 RX Vref 0 -> 0, step: 1
5466 23:47:25.273211
5467 23:47:25.275739 RX Delay -69 -> 252, step: 4
5468 23:47:25.279265 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5469 23:47:25.282618 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5470 23:47:25.285949 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5471 23:47:25.292412 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5472 23:47:25.295722 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5473 23:47:25.298587 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5474 23:47:25.302461 iDelay=199, Bit 6, Center 108 (19 ~ 198) 180
5475 23:47:25.305272 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5476 23:47:25.308577 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5477 23:47:25.315540 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5478 23:47:25.318927 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5479 23:47:25.322293 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5480 23:47:25.325471 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5481 23:47:25.329173 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5482 23:47:25.335793 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5483 23:47:25.339408 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5484 23:47:25.339559 ==
5485 23:47:25.342314 Dram Type= 6, Freq= 0, CH_0, rank 1
5486 23:47:25.346014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 23:47:25.346222 ==
5488 23:47:25.346384 DQS Delay:
5489 23:47:25.349052 DQS0 = 0, DQS1 = 0
5490 23:47:25.349251 DQM Delay:
5491 23:47:25.352672 DQM0 = 95, DQM1 = 88
5492 23:47:25.352911 DQ Delay:
5493 23:47:25.355771 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5494 23:47:25.359162 DQ4 =94, DQ5 =84, DQ6 =108, DQ7 =104
5495 23:47:25.362839 DQ8 =82, DQ9 =80, DQ10 =88, DQ11 =78
5496 23:47:25.366278 DQ12 =92, DQ13 =92, DQ14 =102, DQ15 =94
5497 23:47:25.366696
5498 23:47:25.367029
5499 23:47:25.376457 [DQSOSCAuto] RK1, (LSB)MR18= 0x1805, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5500 23:47:25.376936 CH0 RK1: MR19=505, MR18=1805
5501 23:47:25.383124 CH0_RK1: MR19=0x505, MR18=0x1805, DQSOSC=414, MR23=63, INC=63, DEC=42
5502 23:47:25.386467 [RxdqsGatingPostProcess] freq 933
5503 23:47:25.392807 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5504 23:47:25.396278 best DQS0 dly(2T, 0.5T) = (0, 10)
5505 23:47:25.399364 best DQS1 dly(2T, 0.5T) = (0, 11)
5506 23:47:25.402977 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5507 23:47:25.403395 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5508 23:47:25.406326 best DQS0 dly(2T, 0.5T) = (0, 10)
5509 23:47:25.409765 best DQS1 dly(2T, 0.5T) = (0, 10)
5510 23:47:25.412749 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5511 23:47:25.416541 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5512 23:47:25.420386 Pre-setting of DQS Precalculation
5513 23:47:25.426694 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5514 23:47:25.427203 ==
5515 23:47:25.429946 Dram Type= 6, Freq= 0, CH_1, rank 0
5516 23:47:25.433503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 23:47:25.434067 ==
5518 23:47:25.440086 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5519 23:47:25.443468 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5520 23:47:25.447316 [CA 0] Center 36 (6~67) winsize 62
5521 23:47:25.450428 [CA 1] Center 36 (6~67) winsize 62
5522 23:47:25.454738 [CA 2] Center 34 (4~64) winsize 61
5523 23:47:25.457101 [CA 3] Center 33 (3~64) winsize 62
5524 23:47:25.460549 [CA 4] Center 33 (3~64) winsize 62
5525 23:47:25.464199 [CA 5] Center 33 (3~64) winsize 62
5526 23:47:25.464758
5527 23:47:25.467132 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5528 23:47:25.467655
5529 23:47:25.470569 [CATrainingPosCal] consider 1 rank data
5530 23:47:25.474056 u2DelayCellTimex100 = 270/100 ps
5531 23:47:25.476935 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5532 23:47:25.480634 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5533 23:47:25.487485 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5534 23:47:25.490624 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5535 23:47:25.493746 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5536 23:47:25.497308 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5537 23:47:25.497877
5538 23:47:25.500504 CA PerBit enable=1, Macro0, CA PI delay=33
5539 23:47:25.501100
5540 23:47:25.504092 [CBTSetCACLKResult] CA Dly = 33
5541 23:47:25.504653 CS Dly: 4 (0~35)
5542 23:47:25.505077 ==
5543 23:47:25.507278 Dram Type= 6, Freq= 0, CH_1, rank 1
5544 23:47:25.513762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 23:47:25.514312 ==
5546 23:47:25.517230 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5547 23:47:25.523887 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5548 23:47:25.527247 [CA 0] Center 36 (6~67) winsize 62
5549 23:47:25.530261 [CA 1] Center 36 (6~67) winsize 62
5550 23:47:25.533705 [CA 2] Center 33 (3~64) winsize 62
5551 23:47:25.537427 [CA 3] Center 34 (4~64) winsize 61
5552 23:47:25.540625 [CA 4] Center 34 (4~64) winsize 61
5553 23:47:25.544136 [CA 5] Center 32 (2~63) winsize 62
5554 23:47:25.544694
5555 23:47:25.547082 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5556 23:47:25.547538
5557 23:47:25.550970 [CATrainingPosCal] consider 2 rank data
5558 23:47:25.554035 u2DelayCellTimex100 = 270/100 ps
5559 23:47:25.557718 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 23:47:25.561211 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5561 23:47:25.564098 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5562 23:47:25.570960 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5563 23:47:25.574083 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5564 23:47:25.577086 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5565 23:47:25.577550
5566 23:47:25.580442 CA PerBit enable=1, Macro0, CA PI delay=33
5567 23:47:25.580899
5568 23:47:25.584128 [CBTSetCACLKResult] CA Dly = 33
5569 23:47:25.584586 CS Dly: 5 (0~38)
5570 23:47:25.584955
5571 23:47:25.587120 ----->DramcWriteLeveling(PI) begin...
5572 23:47:25.587584 ==
5573 23:47:25.590268 Dram Type= 6, Freq= 0, CH_1, rank 0
5574 23:47:25.597619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 23:47:25.598214 ==
5576 23:47:25.600242 Write leveling (Byte 0): 27 => 27
5577 23:47:25.603798 Write leveling (Byte 1): 27 => 27
5578 23:47:25.604257 DramcWriteLeveling(PI) end<-----
5579 23:47:25.607217
5580 23:47:25.607676 ==
5581 23:47:25.610595 Dram Type= 6, Freq= 0, CH_1, rank 0
5582 23:47:25.613722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5583 23:47:25.614139 ==
5584 23:47:25.616966 [Gating] SW mode calibration
5585 23:47:25.623583 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5586 23:47:25.626952 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5587 23:47:25.633548 0 14 0 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5588 23:47:25.637085 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 23:47:25.640033 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 23:47:25.647184 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 23:47:25.650228 0 14 16 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
5592 23:47:25.653770 0 14 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5593 23:47:25.660595 0 14 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5594 23:47:25.664264 0 14 28 | B1->B0 | 3030 3434 | 1 0 | (1 0) (0 1)
5595 23:47:25.667717 0 15 0 | B1->B0 | 2828 2a2a | 0 0 | (0 0) (0 0)
5596 23:47:25.674009 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5597 23:47:25.677254 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 23:47:25.680479 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 23:47:25.687567 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 23:47:25.690531 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 23:47:25.693554 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 23:47:25.700227 0 15 28 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (0 0)
5603 23:47:25.703663 1 0 0 | B1->B0 | 4343 4343 | 0 0 | (0 0) (0 0)
5604 23:47:25.706954 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 23:47:25.713921 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 23:47:25.716801 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 23:47:25.720580 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 23:47:25.723755 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 23:47:25.730244 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 23:47:25.733747 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5611 23:47:25.737143 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5612 23:47:25.743869 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 23:47:25.747415 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 23:47:25.750901 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 23:47:25.757450 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 23:47:25.760458 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 23:47:25.764185 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 23:47:25.770412 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 23:47:25.774083 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 23:47:25.776841 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 23:47:25.783656 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 23:47:25.786993 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 23:47:25.790355 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 23:47:25.796829 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 23:47:25.800296 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 23:47:25.803691 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 23:47:25.806648 Total UI for P1: 0, mck2ui 16
5628 23:47:25.810085 best dqsien dly found for B0: ( 1, 2, 26)
5629 23:47:25.813933 Total UI for P1: 0, mck2ui 16
5630 23:47:25.817188 best dqsien dly found for B1: ( 1, 2, 26)
5631 23:47:25.820872 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5632 23:47:25.823515 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5633 23:47:25.824077
5634 23:47:25.827060 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5635 23:47:25.830634 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5636 23:47:25.833969 [Gating] SW calibration Done
5637 23:47:25.834524 ==
5638 23:47:25.837048 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 23:47:25.843871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 23:47:25.844330 ==
5641 23:47:25.844690 RX Vref Scan: 0
5642 23:47:25.845071
5643 23:47:25.847012 RX Vref 0 -> 0, step: 1
5644 23:47:25.847470
5645 23:47:25.850282 RX Delay -80 -> 252, step: 8
5646 23:47:25.853694 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5647 23:47:25.857415 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5648 23:47:25.860743 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5649 23:47:25.863747 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5650 23:47:25.867051 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5651 23:47:25.874447 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5652 23:47:25.877173 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5653 23:47:25.880236 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5654 23:47:25.884055 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5655 23:47:25.886953 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5656 23:47:25.891176 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5657 23:47:25.897103 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5658 23:47:25.900819 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5659 23:47:25.903824 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5660 23:47:25.907511 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5661 23:47:25.910543 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5662 23:47:25.911002 ==
5663 23:47:25.913953 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 23:47:25.920951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 23:47:25.921654 ==
5666 23:47:25.922036 DQS Delay:
5667 23:47:25.924200 DQS0 = 0, DQS1 = 0
5668 23:47:25.924750 DQM Delay:
5669 23:47:25.925170 DQM0 = 95, DQM1 = 89
5670 23:47:25.927186 DQ Delay:
5671 23:47:25.930613 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =99
5672 23:47:25.934179 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5673 23:47:25.937224 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5674 23:47:25.940699 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5675 23:47:25.941423
5676 23:47:25.941836
5677 23:47:25.942193 ==
5678 23:47:25.943631 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 23:47:25.947163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 23:47:25.947626 ==
5681 23:47:25.947994
5682 23:47:25.948335
5683 23:47:25.950808 TX Vref Scan disable
5684 23:47:25.951353 == TX Byte 0 ==
5685 23:47:25.956833 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5686 23:47:25.961218 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5687 23:47:25.961770 == TX Byte 1 ==
5688 23:47:25.967193 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5689 23:47:25.970613 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5690 23:47:25.971164 ==
5691 23:47:25.974156 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 23:47:25.977245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 23:47:25.977711 ==
5694 23:47:25.978080
5695 23:47:25.978419
5696 23:47:25.980917 TX Vref Scan disable
5697 23:47:25.983835 == TX Byte 0 ==
5698 23:47:25.987360 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5699 23:47:25.990257 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5700 23:47:25.993759 == TX Byte 1 ==
5701 23:47:25.997386 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5702 23:47:26.000962 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5703 23:47:26.001461
5704 23:47:26.004494 [DATLAT]
5705 23:47:26.004946 Freq=933, CH1 RK0
5706 23:47:26.005357
5707 23:47:26.007024 DATLAT Default: 0xd
5708 23:47:26.007476 0, 0xFFFF, sum = 0
5709 23:47:26.010779 1, 0xFFFF, sum = 0
5710 23:47:26.011245 2, 0xFFFF, sum = 0
5711 23:47:26.013453 3, 0xFFFF, sum = 0
5712 23:47:26.013872 4, 0xFFFF, sum = 0
5713 23:47:26.017259 5, 0xFFFF, sum = 0
5714 23:47:26.017674 6, 0xFFFF, sum = 0
5715 23:47:26.021176 7, 0xFFFF, sum = 0
5716 23:47:26.021698 8, 0xFFFF, sum = 0
5717 23:47:26.024286 9, 0xFFFF, sum = 0
5718 23:47:26.024796 10, 0x0, sum = 1
5719 23:47:26.027632 11, 0x0, sum = 2
5720 23:47:26.028185 12, 0x0, sum = 3
5721 23:47:26.030828 13, 0x0, sum = 4
5722 23:47:26.031383 best_step = 11
5723 23:47:26.031747
5724 23:47:26.032081 ==
5725 23:47:26.034220 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 23:47:26.041366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 23:47:26.041906 ==
5728 23:47:26.042270 RX Vref Scan: 1
5729 23:47:26.042608
5730 23:47:26.043682 RX Vref 0 -> 0, step: 1
5731 23:47:26.044137
5732 23:47:26.047307 RX Delay -61 -> 252, step: 4
5733 23:47:26.047763
5734 23:47:26.050767 Set Vref, RX VrefLevel [Byte0]: 54
5735 23:47:26.053711 [Byte1]: 53
5736 23:47:26.054274
5737 23:47:26.057055 Final RX Vref Byte 0 = 54 to rank0
5738 23:47:26.060597 Final RX Vref Byte 1 = 53 to rank0
5739 23:47:26.064120 Final RX Vref Byte 0 = 54 to rank1
5740 23:47:26.066769 Final RX Vref Byte 1 = 53 to rank1==
5741 23:47:26.070715 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 23:47:26.073974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 23:47:26.074533 ==
5744 23:47:26.077083 DQS Delay:
5745 23:47:26.077555 DQS0 = 0, DQS1 = 0
5746 23:47:26.077923 DQM Delay:
5747 23:47:26.080621 DQM0 = 97, DQM1 = 90
5748 23:47:26.081223 DQ Delay:
5749 23:47:26.083523 DQ0 =100, DQ1 =92, DQ2 =84, DQ3 =98
5750 23:47:26.087142 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5751 23:47:26.090276 DQ8 =82, DQ9 =80, DQ10 =90, DQ11 =86
5752 23:47:26.093714 DQ12 =96, DQ13 =98, DQ14 =96, DQ15 =96
5753 23:47:26.094201
5754 23:47:26.094572
5755 23:47:26.103368 [DQSOSCAuto] RK0, (LSB)MR18= 0x13f0, (MSB)MR19= 0x504, tDQSOscB0 = 427 ps tDQSOscB1 = 415 ps
5756 23:47:26.107282 CH1 RK0: MR19=504, MR18=13F0
5757 23:47:26.110542 CH1_RK0: MR19=0x504, MR18=0x13F0, DQSOSC=415, MR23=63, INC=62, DEC=41
5758 23:47:26.113439
5759 23:47:26.117830 ----->DramcWriteLeveling(PI) begin...
5760 23:47:26.118257 ==
5761 23:47:26.120421 Dram Type= 6, Freq= 0, CH_1, rank 1
5762 23:47:26.123553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 23:47:26.123973 ==
5764 23:47:26.127091 Write leveling (Byte 0): 26 => 26
5765 23:47:26.130541 Write leveling (Byte 1): 27 => 27
5766 23:47:26.133720 DramcWriteLeveling(PI) end<-----
5767 23:47:26.134238
5768 23:47:26.134575 ==
5769 23:47:26.137140 Dram Type= 6, Freq= 0, CH_1, rank 1
5770 23:47:26.140120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 23:47:26.140635 ==
5772 23:47:26.143271 [Gating] SW mode calibration
5773 23:47:26.150092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5774 23:47:26.157170 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5775 23:47:26.160170 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 23:47:26.163862 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 23:47:26.170069 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 23:47:26.174056 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 23:47:26.176760 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 23:47:26.180338 0 14 20 | B1->B0 | 3535 3434 | 0 0 | (0 0) (0 1)
5781 23:47:26.186982 0 14 24 | B1->B0 | 3131 2d2d | 1 1 | (1 1) (1 1)
5782 23:47:26.190143 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5783 23:47:26.193720 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 23:47:26.200062 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 23:47:26.203530 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 23:47:26.206845 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 23:47:26.213369 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5788 23:47:26.216780 0 15 20 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
5789 23:47:26.219948 0 15 24 | B1->B0 | 2626 2e2e | 1 0 | (0 0) (0 0)
5790 23:47:26.226959 0 15 28 | B1->B0 | 3838 4040 | 0 0 | (0 0) (0 0)
5791 23:47:26.230081 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 23:47:26.233619 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 23:47:26.239816 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 23:47:26.243475 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 23:47:26.246807 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 23:47:26.253018 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 23:47:26.256765 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5798 23:47:26.260030 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5799 23:47:26.266448 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5800 23:47:26.270277 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 23:47:26.273702 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 23:47:26.279865 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 23:47:26.283359 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 23:47:26.286421 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 23:47:26.289930 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 23:47:26.297093 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 23:47:26.300180 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 23:47:26.303914 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 23:47:26.309938 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 23:47:26.313470 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 23:47:26.316803 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 23:47:26.323163 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 23:47:26.327115 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 23:47:26.330508 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 23:47:26.333614 Total UI for P1: 0, mck2ui 16
5816 23:47:26.336624 best dqsien dly found for B0: ( 1, 2, 26)
5817 23:47:26.340243 Total UI for P1: 0, mck2ui 16
5818 23:47:26.343560 best dqsien dly found for B1: ( 1, 2, 26)
5819 23:47:26.346794 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5820 23:47:26.350287 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5821 23:47:26.350836
5822 23:47:26.356927 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5823 23:47:26.360190 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5824 23:47:26.360747 [Gating] SW calibration Done
5825 23:47:26.363229 ==
5826 23:47:26.363688 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 23:47:26.369835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 23:47:26.370301 ==
5829 23:47:26.370670 RX Vref Scan: 0
5830 23:47:26.371012
5831 23:47:26.373258 RX Vref 0 -> 0, step: 1
5832 23:47:26.373717
5833 23:47:26.376762 RX Delay -80 -> 252, step: 8
5834 23:47:26.380713 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5835 23:47:26.383653 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5836 23:47:26.386858 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5837 23:47:26.390192 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5838 23:47:26.396779 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5839 23:47:26.400208 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5840 23:47:26.403745 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5841 23:47:26.406968 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5842 23:47:26.410734 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5843 23:47:26.413706 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5844 23:47:26.420383 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5845 23:47:26.423599 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5846 23:47:26.427228 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5847 23:47:26.430335 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5848 23:47:26.433753 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5849 23:47:26.436636 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5850 23:47:26.440385 ==
5851 23:47:26.440933 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 23:47:26.447070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 23:47:26.447639 ==
5854 23:47:26.448007 DQS Delay:
5855 23:47:26.450532 DQS0 = 0, DQS1 = 0
5856 23:47:26.451077 DQM Delay:
5857 23:47:26.453535 DQM0 = 94, DQM1 = 88
5858 23:47:26.453991 DQ Delay:
5859 23:47:26.457132 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5860 23:47:26.460446 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5861 23:47:26.463961 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =83
5862 23:47:26.466919 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5863 23:47:26.467379
5864 23:47:26.467743
5865 23:47:26.468129 ==
5866 23:47:26.470129 Dram Type= 6, Freq= 0, CH_1, rank 1
5867 23:47:26.473493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5868 23:47:26.473971 ==
5869 23:47:26.474335
5870 23:47:26.474676
5871 23:47:26.477279 TX Vref Scan disable
5872 23:47:26.480443 == TX Byte 0 ==
5873 23:47:26.484032 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5874 23:47:26.487149 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5875 23:47:26.490106 == TX Byte 1 ==
5876 23:47:26.493828 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5877 23:47:26.497388 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5878 23:47:26.497938 ==
5879 23:47:26.500670 Dram Type= 6, Freq= 0, CH_1, rank 1
5880 23:47:26.503735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5881 23:47:26.504295 ==
5882 23:47:26.507261
5883 23:47:26.507813
5884 23:47:26.508181 TX Vref Scan disable
5885 23:47:26.510055 == TX Byte 0 ==
5886 23:47:26.513478 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5887 23:47:26.520336 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5888 23:47:26.520875 == TX Byte 1 ==
5889 23:47:26.523575 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5890 23:47:26.530615 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5891 23:47:26.531168
5892 23:47:26.531538 [DATLAT]
5893 23:47:26.531875 Freq=933, CH1 RK1
5894 23:47:26.532204
5895 23:47:26.533549 DATLAT Default: 0xb
5896 23:47:26.534038 0, 0xFFFF, sum = 0
5897 23:47:26.537284 1, 0xFFFF, sum = 0
5898 23:47:26.537748 2, 0xFFFF, sum = 0
5899 23:47:26.540164 3, 0xFFFF, sum = 0
5900 23:47:26.540729 4, 0xFFFF, sum = 0
5901 23:47:26.544074 5, 0xFFFF, sum = 0
5902 23:47:26.544587 6, 0xFFFF, sum = 0
5903 23:47:26.547026 7, 0xFFFF, sum = 0
5904 23:47:26.547531 8, 0xFFFF, sum = 0
5905 23:47:26.550408 9, 0xFFFF, sum = 0
5906 23:47:26.550872 10, 0x0, sum = 1
5907 23:47:26.553775 11, 0x0, sum = 2
5908 23:47:26.554197 12, 0x0, sum = 3
5909 23:47:26.557508 13, 0x0, sum = 4
5910 23:47:26.557928 best_step = 11
5911 23:47:26.558254
5912 23:47:26.558559 ==
5913 23:47:26.560775 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 23:47:26.566853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 23:47:26.567366 ==
5916 23:47:26.567701 RX Vref Scan: 0
5917 23:47:26.568014
5918 23:47:26.570050 RX Vref 0 -> 0, step: 1
5919 23:47:26.570469
5920 23:47:26.573489 RX Delay -61 -> 252, step: 4
5921 23:47:26.577124 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5922 23:47:26.583827 iDelay=199, Bit 1, Center 88 (-1 ~ 178) 180
5923 23:47:26.586930 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5924 23:47:26.590451 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5925 23:47:26.594033 iDelay=199, Bit 4, Center 94 (-1 ~ 190) 192
5926 23:47:26.597238 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5927 23:47:26.600748 iDelay=199, Bit 6, Center 102 (11 ~ 194) 184
5928 23:47:26.607032 iDelay=199, Bit 7, Center 90 (-1 ~ 182) 184
5929 23:47:26.610532 iDelay=199, Bit 8, Center 80 (-13 ~ 174) 188
5930 23:47:26.613941 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5931 23:47:26.617234 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5932 23:47:26.620277 iDelay=199, Bit 11, Center 86 (-1 ~ 174) 176
5933 23:47:26.626833 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5934 23:47:26.629902 iDelay=199, Bit 13, Center 98 (7 ~ 190) 184
5935 23:47:26.633531 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5936 23:47:26.636908 iDelay=199, Bit 15, Center 98 (7 ~ 190) 184
5937 23:47:26.637518 ==
5938 23:47:26.640087 Dram Type= 6, Freq= 0, CH_1, rank 1
5939 23:47:26.643553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5940 23:47:26.644120 ==
5941 23:47:26.646805 DQS Delay:
5942 23:47:26.647261 DQS0 = 0, DQS1 = 0
5943 23:47:26.650517 DQM Delay:
5944 23:47:26.650975 DQM0 = 94, DQM1 = 91
5945 23:47:26.651340 DQ Delay:
5946 23:47:26.653454 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
5947 23:47:26.657022 DQ4 =94, DQ5 =106, DQ6 =102, DQ7 =90
5948 23:47:26.661015 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =86
5949 23:47:26.663413 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =98
5950 23:47:26.663977
5951 23:47:26.664345
5952 23:47:26.673779 [DQSOSCAuto] RK1, (LSB)MR18= 0xe17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
5953 23:47:26.677119 CH1 RK1: MR19=505, MR18=E17
5954 23:47:26.680529 CH1_RK1: MR19=0x505, MR18=0xE17, DQSOSC=414, MR23=63, INC=63, DEC=42
5955 23:47:26.683973 [RxdqsGatingPostProcess] freq 933
5956 23:47:26.690065 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5957 23:47:26.693478 best DQS0 dly(2T, 0.5T) = (0, 10)
5958 23:47:26.696859 best DQS1 dly(2T, 0.5T) = (0, 10)
5959 23:47:26.700588 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5960 23:47:26.703756 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5961 23:47:26.706934 best DQS0 dly(2T, 0.5T) = (0, 10)
5962 23:47:26.710255 best DQS1 dly(2T, 0.5T) = (0, 10)
5963 23:47:26.713872 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5964 23:47:26.717200 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5965 23:47:26.717760 Pre-setting of DQS Precalculation
5966 23:47:26.723330 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5967 23:47:26.730277 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5968 23:47:26.736846 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5969 23:47:26.737545
5970 23:47:26.738321
5971 23:47:26.740084 [Calibration Summary] 1866 Mbps
5972 23:47:26.743703 CH 0, Rank 0
5973 23:47:26.744157 SW Impedance : PASS
5974 23:47:26.747371 DUTY Scan : NO K
5975 23:47:26.750487 ZQ Calibration : PASS
5976 23:47:26.750947 Jitter Meter : NO K
5977 23:47:26.753213 CBT Training : PASS
5978 23:47:26.753713 Write leveling : PASS
5979 23:47:26.756797 RX DQS gating : PASS
5980 23:47:26.759738 RX DQ/DQS(RDDQC) : PASS
5981 23:47:26.760146 TX DQ/DQS : PASS
5982 23:47:26.763478 RX DATLAT : PASS
5983 23:47:26.766423 RX DQ/DQS(Engine): PASS
5984 23:47:26.766893 TX OE : NO K
5985 23:47:26.770048 All Pass.
5986 23:47:26.770455
5987 23:47:26.770828 CH 0, Rank 1
5988 23:47:26.774380 SW Impedance : PASS
5989 23:47:26.774924 DUTY Scan : NO K
5990 23:47:26.777036 ZQ Calibration : PASS
5991 23:47:26.779891 Jitter Meter : NO K
5992 23:47:26.780298 CBT Training : PASS
5993 23:47:26.783283 Write leveling : PASS
5994 23:47:26.786558 RX DQS gating : PASS
5995 23:47:26.786964 RX DQ/DQS(RDDQC) : PASS
5996 23:47:26.790431 TX DQ/DQS : PASS
5997 23:47:26.793142 RX DATLAT : PASS
5998 23:47:26.793775 RX DQ/DQS(Engine): PASS
5999 23:47:26.797021 TX OE : NO K
6000 23:47:26.797438 All Pass.
6001 23:47:26.797851
6002 23:47:26.798173 CH 1, Rank 0
6003 23:47:26.799744 SW Impedance : PASS
6004 23:47:26.803180 DUTY Scan : NO K
6005 23:47:26.803685 ZQ Calibration : PASS
6006 23:47:26.806972 Jitter Meter : NO K
6007 23:47:26.810155 CBT Training : PASS
6008 23:47:26.810563 Write leveling : PASS
6009 23:47:26.813520 RX DQS gating : PASS
6010 23:47:26.816279 RX DQ/DQS(RDDQC) : PASS
6011 23:47:26.816685 TX DQ/DQS : PASS
6012 23:47:26.819989 RX DATLAT : PASS
6013 23:47:26.823386 RX DQ/DQS(Engine): PASS
6014 23:47:26.823935 TX OE : NO K
6015 23:47:26.826781 All Pass.
6016 23:47:26.827186
6017 23:47:26.827710 CH 1, Rank 1
6018 23:47:26.829794 SW Impedance : PASS
6019 23:47:26.830223 DUTY Scan : NO K
6020 23:47:26.833393 ZQ Calibration : PASS
6021 23:47:26.836813 Jitter Meter : NO K
6022 23:47:26.837354 CBT Training : PASS
6023 23:47:26.839940 Write leveling : PASS
6024 23:47:26.840348 RX DQS gating : PASS
6025 23:47:26.843294 RX DQ/DQS(RDDQC) : PASS
6026 23:47:26.846889 TX DQ/DQS : PASS
6027 23:47:26.847301 RX DATLAT : PASS
6028 23:47:26.849893 RX DQ/DQS(Engine): PASS
6029 23:47:26.853469 TX OE : NO K
6030 23:47:26.853987 All Pass.
6031 23:47:26.854318
6032 23:47:26.856743 DramC Write-DBI off
6033 23:47:26.857187 PER_BANK_REFRESH: Hybrid Mode
6034 23:47:26.860252 TX_TRACKING: ON
6035 23:47:26.866887 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6036 23:47:26.873198 [FAST_K] Save calibration result to emmc
6037 23:47:26.877055 dramc_set_vcore_voltage set vcore to 650000
6038 23:47:26.877574 Read voltage for 400, 6
6039 23:47:26.880594 Vio18 = 0
6040 23:47:26.881304 Vcore = 650000
6041 23:47:26.881661 Vdram = 0
6042 23:47:26.883620 Vddq = 0
6043 23:47:26.883979 Vmddr = 0
6044 23:47:26.887132 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6045 23:47:26.893313 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6046 23:47:26.897080 MEM_TYPE=3, freq_sel=20
6047 23:47:26.899841 sv_algorithm_assistance_LP4_800
6048 23:47:26.903165 ============ PULL DRAM RESETB DOWN ============
6049 23:47:26.906703 ========== PULL DRAM RESETB DOWN end =========
6050 23:47:26.909909 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6051 23:47:26.913339 ===================================
6052 23:47:26.916520 LPDDR4 DRAM CONFIGURATION
6053 23:47:26.920039 ===================================
6054 23:47:26.923577 EX_ROW_EN[0] = 0x0
6055 23:47:26.923987 EX_ROW_EN[1] = 0x0
6056 23:47:26.927161 LP4Y_EN = 0x0
6057 23:47:26.927671 WORK_FSP = 0x0
6058 23:47:26.930568 WL = 0x2
6059 23:47:26.931075 RL = 0x2
6060 23:47:26.933754 BL = 0x2
6061 23:47:26.934260 RPST = 0x0
6062 23:47:26.937031 RD_PRE = 0x0
6063 23:47:26.937440 WR_PRE = 0x1
6064 23:47:26.939965 WR_PST = 0x0
6065 23:47:26.940468 DBI_WR = 0x0
6066 23:47:26.943325 DBI_RD = 0x0
6067 23:47:26.943733 OTF = 0x1
6068 23:47:26.946375 ===================================
6069 23:47:26.949746 ===================================
6070 23:47:26.953550 ANA top config
6071 23:47:26.956537 ===================================
6072 23:47:26.960311 DLL_ASYNC_EN = 0
6073 23:47:26.960818 ALL_SLAVE_EN = 1
6074 23:47:26.963870 NEW_RANK_MODE = 1
6075 23:47:26.967116 DLL_IDLE_MODE = 1
6076 23:47:26.970228 LP45_APHY_COMB_EN = 1
6077 23:47:26.973342 TX_ODT_DIS = 1
6078 23:47:26.973752 NEW_8X_MODE = 1
6079 23:47:26.977097 ===================================
6080 23:47:26.980416 ===================================
6081 23:47:26.983823 data_rate = 800
6082 23:47:26.986882 CKR = 1
6083 23:47:26.989796 DQ_P2S_RATIO = 4
6084 23:47:26.993476 ===================================
6085 23:47:26.996960 CA_P2S_RATIO = 4
6086 23:47:26.997531 DQ_CA_OPEN = 0
6087 23:47:27.000308 DQ_SEMI_OPEN = 1
6088 23:47:27.004054 CA_SEMI_OPEN = 1
6089 23:47:27.007055 CA_FULL_RATE = 0
6090 23:47:27.010673 DQ_CKDIV4_EN = 0
6091 23:47:27.014012 CA_CKDIV4_EN = 1
6092 23:47:27.014422 CA_PREDIV_EN = 0
6093 23:47:27.017124 PH8_DLY = 0
6094 23:47:27.020278 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6095 23:47:27.023662 DQ_AAMCK_DIV = 0
6096 23:47:27.027332 CA_AAMCK_DIV = 0
6097 23:47:27.030670 CA_ADMCK_DIV = 4
6098 23:47:27.031208 DQ_TRACK_CA_EN = 0
6099 23:47:27.033542 CA_PICK = 800
6100 23:47:27.036910 CA_MCKIO = 400
6101 23:47:27.040463 MCKIO_SEMI = 400
6102 23:47:27.043890 PLL_FREQ = 3016
6103 23:47:27.046916 DQ_UI_PI_RATIO = 32
6104 23:47:27.050128 CA_UI_PI_RATIO = 32
6105 23:47:27.053307 ===================================
6106 23:47:27.056963 ===================================
6107 23:47:27.057416 memory_type:LPDDR4
6108 23:47:27.060219 GP_NUM : 10
6109 23:47:27.060626 SRAM_EN : 1
6110 23:47:27.063466 MD32_EN : 0
6111 23:47:27.067249 ===================================
6112 23:47:27.070310 [ANA_INIT] >>>>>>>>>>>>>>
6113 23:47:27.074530 <<<<<< [CONFIGURE PHASE]: ANA_TX
6114 23:47:27.076739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6115 23:47:27.080322 ===================================
6116 23:47:27.080884 data_rate = 800,PCW = 0X7400
6117 23:47:27.084313 ===================================
6118 23:47:27.087228 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6119 23:47:27.093788 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6120 23:47:27.106919 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6121 23:47:27.110506 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6122 23:47:27.113639 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6123 23:47:27.117121 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6124 23:47:27.121099 [ANA_INIT] flow start
6125 23:47:27.121607 [ANA_INIT] PLL >>>>>>>>
6126 23:47:27.124023 [ANA_INIT] PLL <<<<<<<<
6127 23:47:27.126741 [ANA_INIT] MIDPI >>>>>>>>
6128 23:47:27.127148 [ANA_INIT] MIDPI <<<<<<<<
6129 23:47:27.130468 [ANA_INIT] DLL >>>>>>>>
6130 23:47:27.133866 [ANA_INIT] flow end
6131 23:47:27.137109 ============ LP4 DIFF to SE enter ============
6132 23:47:27.140860 ============ LP4 DIFF to SE exit ============
6133 23:47:27.144066 [ANA_INIT] <<<<<<<<<<<<<
6134 23:47:27.147192 [Flow] Enable top DCM control >>>>>
6135 23:47:27.150817 [Flow] Enable top DCM control <<<<<
6136 23:47:27.153963 Enable DLL master slave shuffle
6137 23:47:27.157335 ==============================================================
6138 23:47:27.160858 Gating Mode config
6139 23:47:27.167113 ==============================================================
6140 23:47:27.167658 Config description:
6141 23:47:27.177349 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6142 23:47:27.183854 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6143 23:47:27.187464 SELPH_MODE 0: By rank 1: By Phase
6144 23:47:27.193561 ==============================================================
6145 23:47:27.196843 GAT_TRACK_EN = 0
6146 23:47:27.200376 RX_GATING_MODE = 2
6147 23:47:27.203601 RX_GATING_TRACK_MODE = 2
6148 23:47:27.207522 SELPH_MODE = 1
6149 23:47:27.210278 PICG_EARLY_EN = 1
6150 23:47:27.210732 VALID_LAT_VALUE = 1
6151 23:47:27.217401 ==============================================================
6152 23:47:27.220635 Enter into Gating configuration >>>>
6153 23:47:27.224356 Exit from Gating configuration <<<<
6154 23:47:27.227762 Enter into DVFS_PRE_config >>>>>
6155 23:47:27.237337 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6156 23:47:27.240567 Exit from DVFS_PRE_config <<<<<
6157 23:47:27.243901 Enter into PICG configuration >>>>
6158 23:47:27.246916 Exit from PICG configuration <<<<
6159 23:47:27.250891 [RX_INPUT] configuration >>>>>
6160 23:47:27.253716 [RX_INPUT] configuration <<<<<
6161 23:47:27.256959 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6162 23:47:27.263820 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6163 23:47:27.270227 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6164 23:47:27.277163 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6165 23:47:27.283706 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6166 23:47:27.290386 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6167 23:47:27.293734 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6168 23:47:27.296806 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6169 23:47:27.300658 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6170 23:47:27.303597 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6171 23:47:27.310396 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6172 23:47:27.313448 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6173 23:47:27.316946 ===================================
6174 23:47:27.320275 LPDDR4 DRAM CONFIGURATION
6175 23:47:27.323983 ===================================
6176 23:47:27.324533 EX_ROW_EN[0] = 0x0
6177 23:47:27.327384 EX_ROW_EN[1] = 0x0
6178 23:47:27.327929 LP4Y_EN = 0x0
6179 23:47:27.330485 WORK_FSP = 0x0
6180 23:47:27.331036 WL = 0x2
6181 23:47:27.333560 RL = 0x2
6182 23:47:27.334007 BL = 0x2
6183 23:47:27.337335 RPST = 0x0
6184 23:47:27.337856 RD_PRE = 0x0
6185 23:47:27.341584 WR_PRE = 0x1
6186 23:47:27.342133 WR_PST = 0x0
6187 23:47:27.343528 DBI_WR = 0x0
6188 23:47:27.347692 DBI_RD = 0x0
6189 23:47:27.348245 OTF = 0x1
6190 23:47:27.350754 ===================================
6191 23:47:27.353578 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6192 23:47:27.357199 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6193 23:47:27.363811 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6194 23:47:27.367593 ===================================
6195 23:47:27.368139 LPDDR4 DRAM CONFIGURATION
6196 23:47:27.370824 ===================================
6197 23:47:27.374027 EX_ROW_EN[0] = 0x10
6198 23:47:27.377133 EX_ROW_EN[1] = 0x0
6199 23:47:27.377677 LP4Y_EN = 0x0
6200 23:47:27.380480 WORK_FSP = 0x0
6201 23:47:27.380928 WL = 0x2
6202 23:47:27.384113 RL = 0x2
6203 23:47:27.384660 BL = 0x2
6204 23:47:27.387118 RPST = 0x0
6205 23:47:27.387567 RD_PRE = 0x0
6206 23:47:27.390232 WR_PRE = 0x1
6207 23:47:27.390719 WR_PST = 0x0
6208 23:47:27.393972 DBI_WR = 0x0
6209 23:47:27.394419 DBI_RD = 0x0
6210 23:47:27.397029 OTF = 0x1
6211 23:47:27.400722 ===================================
6212 23:47:27.407166 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6213 23:47:27.410339 nWR fixed to 30
6214 23:47:27.410796 [ModeRegInit_LP4] CH0 RK0
6215 23:47:27.413999 [ModeRegInit_LP4] CH0 RK1
6216 23:47:27.417230 [ModeRegInit_LP4] CH1 RK0
6217 23:47:27.421054 [ModeRegInit_LP4] CH1 RK1
6218 23:47:27.421604 match AC timing 19
6219 23:47:27.424304 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6220 23:47:27.431251 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6221 23:47:27.434157 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6222 23:47:27.437210 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6223 23:47:27.444088 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6224 23:47:27.444673 ==
6225 23:47:27.446959 Dram Type= 6, Freq= 0, CH_0, rank 0
6226 23:47:27.451257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6227 23:47:27.451814 ==
6228 23:47:27.457269 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6229 23:47:27.464065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6230 23:47:27.464583 [CA 0] Center 36 (8~64) winsize 57
6231 23:47:27.466824 [CA 1] Center 36 (8~64) winsize 57
6232 23:47:27.470494 [CA 2] Center 36 (8~64) winsize 57
6233 23:47:27.474546 [CA 3] Center 36 (8~64) winsize 57
6234 23:47:27.477361 [CA 4] Center 36 (8~64) winsize 57
6235 23:47:27.480620 [CA 5] Center 36 (8~64) winsize 57
6236 23:47:27.481158
6237 23:47:27.484165 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6238 23:47:27.484672
6239 23:47:27.487556 [CATrainingPosCal] consider 1 rank data
6240 23:47:27.490675 u2DelayCellTimex100 = 270/100 ps
6241 23:47:27.493738 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 23:47:27.497180 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 23:47:27.503848 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 23:47:27.507322 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 23:47:27.510509 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 23:47:27.513776 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 23:47:27.514289
6248 23:47:27.517127 CA PerBit enable=1, Macro0, CA PI delay=36
6249 23:47:27.517663
6250 23:47:27.520618 [CBTSetCACLKResult] CA Dly = 36
6251 23:47:27.521167 CS Dly: 1 (0~32)
6252 23:47:27.521500 ==
6253 23:47:27.523945 Dram Type= 6, Freq= 0, CH_0, rank 1
6254 23:47:27.530664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6255 23:47:27.531175 ==
6256 23:47:27.533830 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6257 23:47:27.540516 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6258 23:47:27.544145 [CA 0] Center 36 (8~64) winsize 57
6259 23:47:27.547045 [CA 1] Center 36 (8~64) winsize 57
6260 23:47:27.550733 [CA 2] Center 36 (8~64) winsize 57
6261 23:47:27.553720 [CA 3] Center 36 (8~64) winsize 57
6262 23:47:27.556877 [CA 4] Center 36 (8~64) winsize 57
6263 23:47:27.560244 [CA 5] Center 36 (8~64) winsize 57
6264 23:47:27.560696
6265 23:47:27.563766 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6266 23:47:27.564314
6267 23:47:27.566995 [CATrainingPosCal] consider 2 rank data
6268 23:47:27.570536 u2DelayCellTimex100 = 270/100 ps
6269 23:47:27.573569 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 23:47:27.577324 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 23:47:27.580147 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 23:47:27.583785 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 23:47:27.586977 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 23:47:27.590122 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 23:47:27.593628
6276 23:47:27.597081 CA PerBit enable=1, Macro0, CA PI delay=36
6277 23:47:27.597637
6278 23:47:27.600209 [CBTSetCACLKResult] CA Dly = 36
6279 23:47:27.600658 CS Dly: 1 (0~32)
6280 23:47:27.601065
6281 23:47:27.603568 ----->DramcWriteLeveling(PI) begin...
6282 23:47:27.604115 ==
6283 23:47:27.606693 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 23:47:27.610049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 23:47:27.613766 ==
6286 23:47:27.614426 Write leveling (Byte 0): 40 => 8
6287 23:47:27.616758 Write leveling (Byte 1): 32 => 0
6288 23:47:27.620295 DramcWriteLeveling(PI) end<-----
6289 23:47:27.620801
6290 23:47:27.621194 ==
6291 23:47:27.623302 Dram Type= 6, Freq= 0, CH_0, rank 0
6292 23:47:27.629917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6293 23:47:27.630323 ==
6294 23:47:27.630645 [Gating] SW mode calibration
6295 23:47:27.639791 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6296 23:47:27.643107 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6297 23:47:27.646838 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6298 23:47:27.653551 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6299 23:47:27.657023 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6300 23:47:27.659867 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 23:47:27.667008 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6302 23:47:27.670086 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 23:47:27.673139 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 23:47:27.680219 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 23:47:27.683779 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6306 23:47:27.686484 Total UI for P1: 0, mck2ui 16
6307 23:47:27.690623 best dqsien dly found for B0: ( 0, 14, 24)
6308 23:47:27.693236 Total UI for P1: 0, mck2ui 16
6309 23:47:27.696827 best dqsien dly found for B1: ( 0, 14, 24)
6310 23:47:27.700150 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6311 23:47:27.703558 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6312 23:47:27.704070
6313 23:47:27.706418 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6314 23:47:27.710078 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6315 23:47:27.713100 [Gating] SW calibration Done
6316 23:47:27.713606 ==
6317 23:47:27.716789 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 23:47:27.720190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 23:47:27.723573 ==
6320 23:47:27.724077 RX Vref Scan: 0
6321 23:47:27.724428
6322 23:47:27.726901 RX Vref 0 -> 0, step: 1
6323 23:47:27.727307
6324 23:47:27.730090 RX Delay -410 -> 252, step: 16
6325 23:47:27.733688 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6326 23:47:27.736351 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6327 23:47:27.739659 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6328 23:47:27.746539 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6329 23:47:27.750092 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6330 23:47:27.753010 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6331 23:47:27.756626 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6332 23:47:27.763196 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6333 23:47:27.766638 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6334 23:47:27.770372 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6335 23:47:27.773315 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6336 23:47:27.779948 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6337 23:47:27.783483 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6338 23:47:27.786370 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6339 23:47:27.790136 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6340 23:47:27.796405 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6341 23:47:27.796937 ==
6342 23:47:27.799689 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 23:47:27.803418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 23:47:27.803961 ==
6345 23:47:27.804315 DQS Delay:
6346 23:47:27.806430 DQS0 = 35, DQS1 = 51
6347 23:47:27.806877 DQM Delay:
6348 23:47:27.809791 DQM0 = 6, DQM1 = 10
6349 23:47:27.810235 DQ Delay:
6350 23:47:27.813198 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6351 23:47:27.816426 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6352 23:47:27.819756 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6353 23:47:27.823443 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6354 23:47:27.823990
6355 23:47:27.824349
6356 23:47:27.824683 ==
6357 23:47:27.826330 Dram Type= 6, Freq= 0, CH_0, rank 0
6358 23:47:27.829681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 23:47:27.830136 ==
6360 23:47:27.830496
6361 23:47:27.830827
6362 23:47:27.832972 TX Vref Scan disable
6363 23:47:27.836477 == TX Byte 0 ==
6364 23:47:27.839824 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 23:47:27.843063 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 23:47:27.843563 == TX Byte 1 ==
6367 23:47:27.849680 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6368 23:47:27.853217 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6369 23:47:27.853670 ==
6370 23:47:27.856213 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 23:47:27.860043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 23:47:27.860598 ==
6373 23:47:27.860962
6374 23:47:27.863281
6375 23:47:27.863727 TX Vref Scan disable
6376 23:47:27.866004 == TX Byte 0 ==
6377 23:47:27.869349 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6378 23:47:27.873126 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6379 23:47:27.876622 == TX Byte 1 ==
6380 23:47:27.879691 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6381 23:47:27.882784 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6382 23:47:27.883239
6383 23:47:27.883600 [DATLAT]
6384 23:47:27.886231 Freq=400, CH0 RK0
6385 23:47:27.886679
6386 23:47:27.889462 DATLAT Default: 0xf
6387 23:47:27.889869 0, 0xFFFF, sum = 0
6388 23:47:27.892896 1, 0xFFFF, sum = 0
6389 23:47:27.893341 2, 0xFFFF, sum = 0
6390 23:47:27.896119 3, 0xFFFF, sum = 0
6391 23:47:27.896532 4, 0xFFFF, sum = 0
6392 23:47:27.899318 5, 0xFFFF, sum = 0
6393 23:47:27.899733 6, 0xFFFF, sum = 0
6394 23:47:27.902901 7, 0xFFFF, sum = 0
6395 23:47:27.903312 8, 0xFFFF, sum = 0
6396 23:47:27.905926 9, 0xFFFF, sum = 0
6397 23:47:27.906339 10, 0xFFFF, sum = 0
6398 23:47:27.909684 11, 0xFFFF, sum = 0
6399 23:47:27.910094 12, 0xFFFF, sum = 0
6400 23:47:27.912789 13, 0x0, sum = 1
6401 23:47:27.913236 14, 0x0, sum = 2
6402 23:47:27.915813 15, 0x0, sum = 3
6403 23:47:27.916248 16, 0x0, sum = 4
6404 23:47:27.919693 best_step = 14
6405 23:47:27.920193
6406 23:47:27.920521 ==
6407 23:47:27.922413 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 23:47:27.926097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 23:47:27.926510 ==
6410 23:47:27.929154 RX Vref Scan: 1
6411 23:47:27.929558
6412 23:47:27.929878 RX Vref 0 -> 0, step: 1
6413 23:47:27.930180
6414 23:47:27.932545 RX Delay -343 -> 252, step: 8
6415 23:47:27.932951
6416 23:47:27.936106 Set Vref, RX VrefLevel [Byte0]: 54
6417 23:47:27.939409 [Byte1]: 52
6418 23:47:27.943490
6419 23:47:27.944046 Final RX Vref Byte 0 = 54 to rank0
6420 23:47:27.946813 Final RX Vref Byte 1 = 52 to rank0
6421 23:47:27.950051 Final RX Vref Byte 0 = 54 to rank1
6422 23:47:27.953473 Final RX Vref Byte 1 = 52 to rank1==
6423 23:47:27.956867 Dram Type= 6, Freq= 0, CH_0, rank 0
6424 23:47:27.960446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6425 23:47:27.963545 ==
6426 23:47:27.963953 DQS Delay:
6427 23:47:27.964277 DQS0 = 44, DQS1 = 60
6428 23:47:27.967287 DQM Delay:
6429 23:47:27.967691 DQM0 = 11, DQM1 = 15
6430 23:47:27.970099 DQ Delay:
6431 23:47:27.973446 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6432 23:47:27.973856 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6433 23:47:27.977213 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =12
6434 23:47:27.980451 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6435 23:47:27.980857
6436 23:47:27.981219
6437 23:47:27.990259 [DQSOSCAuto] RK0, (LSB)MR18= 0x8250, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6438 23:47:27.993942 CH0 RK0: MR19=C0C, MR18=8250
6439 23:47:28.000439 CH0_RK0: MR19=0xC0C, MR18=0x8250, DQSOSC=393, MR23=63, INC=382, DEC=254
6440 23:47:28.000871 ==
6441 23:47:28.003835 Dram Type= 6, Freq= 0, CH_0, rank 1
6442 23:47:28.007032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6443 23:47:28.007531 ==
6444 23:47:28.010795 [Gating] SW mode calibration
6445 23:47:28.017364 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6446 23:47:28.020545 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6447 23:47:28.027486 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6448 23:47:28.030851 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6449 23:47:28.034224 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6450 23:47:28.040396 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 23:47:28.044073 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6452 23:47:28.047172 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 23:47:28.053648 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 23:47:28.057298 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 23:47:28.060388 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6456 23:47:28.064398 Total UI for P1: 0, mck2ui 16
6457 23:47:28.067071 best dqsien dly found for B0: ( 0, 14, 24)
6458 23:47:28.070387 Total UI for P1: 0, mck2ui 16
6459 23:47:28.073868 best dqsien dly found for B1: ( 0, 14, 24)
6460 23:47:28.077514 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6461 23:47:28.080770 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6462 23:47:28.081314
6463 23:47:28.084104 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6464 23:47:28.090980 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6465 23:47:28.091448 [Gating] SW calibration Done
6466 23:47:28.091778 ==
6467 23:47:28.093523 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 23:47:28.100935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 23:47:28.101390 ==
6470 23:47:28.101716 RX Vref Scan: 0
6471 23:47:28.102015
6472 23:47:28.103929 RX Vref 0 -> 0, step: 1
6473 23:47:28.104364
6474 23:47:28.107062 RX Delay -410 -> 252, step: 16
6475 23:47:28.110652 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6476 23:47:28.114074 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6477 23:47:28.121141 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6478 23:47:28.123770 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6479 23:47:28.127385 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6480 23:47:28.130769 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6481 23:47:28.137535 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6482 23:47:28.140938 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6483 23:47:28.143761 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6484 23:47:28.147725 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6485 23:47:28.154348 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6486 23:47:28.157757 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6487 23:47:28.160879 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6488 23:47:28.164064 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6489 23:47:28.170624 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6490 23:47:28.173950 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6491 23:47:28.174481 ==
6492 23:47:28.177020 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 23:47:28.180559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 23:47:28.181292 ==
6495 23:47:28.183917 DQS Delay:
6496 23:47:28.184526 DQS0 = 43, DQS1 = 51
6497 23:47:28.185215 DQM Delay:
6498 23:47:28.187240 DQM0 = 11, DQM1 = 10
6499 23:47:28.187879 DQ Delay:
6500 23:47:28.190541 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6501 23:47:28.194333 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6502 23:47:28.197102 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6503 23:47:28.200321 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6504 23:47:28.201046
6505 23:47:28.201599
6506 23:47:28.202063 ==
6507 23:47:28.203628 Dram Type= 6, Freq= 0, CH_0, rank 1
6508 23:47:28.207275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6509 23:47:28.207753 ==
6510 23:47:28.210516
6511 23:47:28.210919
6512 23:47:28.211276 TX Vref Scan disable
6513 23:47:28.213640 == TX Byte 0 ==
6514 23:47:28.217393 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6515 23:47:28.220890 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6516 23:47:28.224043 == TX Byte 1 ==
6517 23:47:28.228085 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6518 23:47:28.230384 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6519 23:47:28.230861 ==
6520 23:47:28.234475 Dram Type= 6, Freq= 0, CH_0, rank 1
6521 23:47:28.237081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6522 23:47:28.237542 ==
6523 23:47:28.240583
6524 23:47:28.241153
6525 23:47:28.241672 TX Vref Scan disable
6526 23:47:28.243998 == TX Byte 0 ==
6527 23:47:28.247449 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6528 23:47:28.250543 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6529 23:47:28.254007 == TX Byte 1 ==
6530 23:47:28.257619 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6531 23:47:28.260911 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6532 23:47:28.261403
6533 23:47:28.261767 [DATLAT]
6534 23:47:28.264419 Freq=400, CH0 RK1
6535 23:47:28.264875
6536 23:47:28.265286 DATLAT Default: 0xe
6537 23:47:28.267670 0, 0xFFFF, sum = 0
6538 23:47:28.268089 1, 0xFFFF, sum = 0
6539 23:47:28.270741 2, 0xFFFF, sum = 0
6540 23:47:28.271169 3, 0xFFFF, sum = 0
6541 23:47:28.274235 4, 0xFFFF, sum = 0
6542 23:47:28.277531 5, 0xFFFF, sum = 0
6543 23:47:28.277954 6, 0xFFFF, sum = 0
6544 23:47:28.281010 7, 0xFFFF, sum = 0
6545 23:47:28.281486 8, 0xFFFF, sum = 0
6546 23:47:28.284061 9, 0xFFFF, sum = 0
6547 23:47:28.284537 10, 0xFFFF, sum = 0
6548 23:47:28.287942 11, 0xFFFF, sum = 0
6549 23:47:28.288362 12, 0xFFFF, sum = 0
6550 23:47:28.291034 13, 0x0, sum = 1
6551 23:47:28.291456 14, 0x0, sum = 2
6552 23:47:28.294222 15, 0x0, sum = 3
6553 23:47:28.294695 16, 0x0, sum = 4
6554 23:47:28.295037 best_step = 14
6555 23:47:28.295385
6556 23:47:28.297603 ==
6557 23:47:28.301110 Dram Type= 6, Freq= 0, CH_0, rank 1
6558 23:47:28.304009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6559 23:47:28.304478 ==
6560 23:47:28.304822 RX Vref Scan: 0
6561 23:47:28.305233
6562 23:47:28.307560 RX Vref 0 -> 0, step: 1
6563 23:47:28.307977
6564 23:47:28.310712 RX Delay -343 -> 252, step: 8
6565 23:47:28.318051 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6566 23:47:28.321692 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6567 23:47:28.325225 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6568 23:47:28.327950 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6569 23:47:28.334912 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6570 23:47:28.338055 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6571 23:47:28.341606 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6572 23:47:28.344869 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6573 23:47:28.351560 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6574 23:47:28.354620 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6575 23:47:28.357997 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6576 23:47:28.361693 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6577 23:47:28.368416 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6578 23:47:28.371169 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6579 23:47:28.375291 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6580 23:47:28.377967 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6581 23:47:28.381519 ==
6582 23:47:28.385098 Dram Type= 6, Freq= 0, CH_0, rank 1
6583 23:47:28.388182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6584 23:47:28.388733 ==
6585 23:47:28.389156 DQS Delay:
6586 23:47:28.392367 DQS0 = 48, DQS1 = 60
6587 23:47:28.392920 DQM Delay:
6588 23:47:28.394813 DQM0 = 13, DQM1 = 13
6589 23:47:28.395271 DQ Delay:
6590 23:47:28.398135 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6591 23:47:28.401308 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6592 23:47:28.404492 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =4
6593 23:47:28.408064 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6594 23:47:28.408573
6595 23:47:28.408942
6596 23:47:28.414691 [DQSOSCAuto] RK1, (LSB)MR18= 0x976b, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6597 23:47:28.417761 CH0 RK1: MR19=C0C, MR18=976B
6598 23:47:28.424801 CH0_RK1: MR19=0xC0C, MR18=0x976B, DQSOSC=390, MR23=63, INC=388, DEC=258
6599 23:47:28.428070 [RxdqsGatingPostProcess] freq 400
6600 23:47:28.434750 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6601 23:47:28.435302 best DQS0 dly(2T, 0.5T) = (0, 10)
6602 23:47:28.438443 best DQS1 dly(2T, 0.5T) = (0, 10)
6603 23:47:28.440903 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6604 23:47:28.444588 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6605 23:47:28.447791 best DQS0 dly(2T, 0.5T) = (0, 10)
6606 23:47:28.451205 best DQS1 dly(2T, 0.5T) = (0, 10)
6607 23:47:28.454418 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6608 23:47:28.458230 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6609 23:47:28.461680 Pre-setting of DQS Precalculation
6610 23:47:28.464675 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6611 23:47:28.467875 ==
6612 23:47:28.471419 Dram Type= 6, Freq= 0, CH_1, rank 0
6613 23:47:28.474616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 23:47:28.475169 ==
6615 23:47:28.478268 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6616 23:47:28.484853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6617 23:47:28.488069 [CA 0] Center 36 (8~64) winsize 57
6618 23:47:28.491126 [CA 1] Center 36 (8~64) winsize 57
6619 23:47:28.494968 [CA 2] Center 36 (8~64) winsize 57
6620 23:47:28.497665 [CA 3] Center 36 (8~64) winsize 57
6621 23:47:28.501183 [CA 4] Center 36 (8~64) winsize 57
6622 23:47:28.504719 [CA 5] Center 36 (8~64) winsize 57
6623 23:47:28.505228
6624 23:47:28.508061 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6625 23:47:28.508606
6626 23:47:28.511177 [CATrainingPosCal] consider 1 rank data
6627 23:47:28.514659 u2DelayCellTimex100 = 270/100 ps
6628 23:47:28.517552 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 23:47:28.520924 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 23:47:28.524671 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 23:47:28.527770 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 23:47:28.531207 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 23:47:28.538459 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 23:47:28.539011
6635 23:47:28.540905 CA PerBit enable=1, Macro0, CA PI delay=36
6636 23:47:28.541451
6637 23:47:28.544498 [CBTSetCACLKResult] CA Dly = 36
6638 23:47:28.544955 CS Dly: 1 (0~32)
6639 23:47:28.545398 ==
6640 23:47:28.547766 Dram Type= 6, Freq= 0, CH_1, rank 1
6641 23:47:28.551448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 23:47:28.554558 ==
6643 23:47:28.558163 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6644 23:47:28.564524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6645 23:47:28.568020 [CA 0] Center 36 (8~64) winsize 57
6646 23:47:28.571347 [CA 1] Center 36 (8~64) winsize 57
6647 23:47:28.574881 [CA 2] Center 36 (8~64) winsize 57
6648 23:47:28.577996 [CA 3] Center 36 (8~64) winsize 57
6649 23:47:28.581477 [CA 4] Center 36 (8~64) winsize 57
6650 23:47:28.582031 [CA 5] Center 36 (8~64) winsize 57
6651 23:47:28.584671
6652 23:47:28.587836 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6653 23:47:28.588399
6654 23:47:28.591442 [CATrainingPosCal] consider 2 rank data
6655 23:47:28.594522 u2DelayCellTimex100 = 270/100 ps
6656 23:47:28.597996 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 23:47:28.601221 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 23:47:28.604752 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 23:47:28.609056 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 23:47:28.611614 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 23:47:28.614703 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 23:47:28.615252
6663 23:47:28.618247 CA PerBit enable=1, Macro0, CA PI delay=36
6664 23:47:28.618805
6665 23:47:28.621166 [CBTSetCACLKResult] CA Dly = 36
6666 23:47:28.624627 CS Dly: 1 (0~32)
6667 23:47:28.625132
6668 23:47:28.628257 ----->DramcWriteLeveling(PI) begin...
6669 23:47:28.628822 ==
6670 23:47:28.631378 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 23:47:28.635002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 23:47:28.635558 ==
6673 23:47:28.637887 Write leveling (Byte 0): 40 => 8
6674 23:47:28.641558 Write leveling (Byte 1): 40 => 8
6675 23:47:28.644463 DramcWriteLeveling(PI) end<-----
6676 23:47:28.645029
6677 23:47:28.645397 ==
6678 23:47:28.648002 Dram Type= 6, Freq= 0, CH_1, rank 0
6679 23:47:28.651779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6680 23:47:28.652335 ==
6681 23:47:28.654816 [Gating] SW mode calibration
6682 23:47:28.661331 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6683 23:47:28.667892 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6684 23:47:28.671183 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6685 23:47:28.675141 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6686 23:47:28.681900 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6687 23:47:28.685417 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 23:47:28.688700 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6689 23:47:28.694854 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 23:47:28.697801 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 23:47:28.701470 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 23:47:28.708110 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6693 23:47:28.708652 Total UI for P1: 0, mck2ui 16
6694 23:47:28.711697 best dqsien dly found for B0: ( 0, 14, 24)
6695 23:47:28.714910 Total UI for P1: 0, mck2ui 16
6696 23:47:28.718230 best dqsien dly found for B1: ( 0, 14, 24)
6697 23:47:28.722193 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6698 23:47:28.728072 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6699 23:47:28.728627
6700 23:47:28.731489 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6701 23:47:28.734935 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6702 23:47:28.738159 [Gating] SW calibration Done
6703 23:47:28.738614 ==
6704 23:47:28.741278 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 23:47:28.745010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 23:47:28.745486 ==
6707 23:47:28.748451 RX Vref Scan: 0
6708 23:47:28.748900
6709 23:47:28.749348 RX Vref 0 -> 0, step: 1
6710 23:47:28.749698
6711 23:47:28.751357 RX Delay -410 -> 252, step: 16
6712 23:47:28.755218 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6713 23:47:28.761718 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6714 23:47:28.765314 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6715 23:47:28.768734 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6716 23:47:28.771820 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6717 23:47:28.778424 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6718 23:47:28.782700 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6719 23:47:28.785091 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6720 23:47:28.788587 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6721 23:47:28.794818 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6722 23:47:28.798693 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6723 23:47:28.801720 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6724 23:47:28.805503 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6725 23:47:28.811937 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6726 23:47:28.815283 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6727 23:47:28.818281 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6728 23:47:28.818733 ==
6729 23:47:28.821987 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 23:47:28.825097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 23:47:28.828081 ==
6732 23:47:28.828534 DQS Delay:
6733 23:47:28.828890 DQS0 = 51, DQS1 = 59
6734 23:47:28.832075 DQM Delay:
6735 23:47:28.832620 DQM0 = 19, DQM1 = 16
6736 23:47:28.835079 DQ Delay:
6737 23:47:28.835555 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6738 23:47:28.838142 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6739 23:47:28.841773 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6740 23:47:28.845037 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6741 23:47:28.845637
6742 23:47:28.846000
6743 23:47:28.848085 ==
6744 23:47:28.851719 Dram Type= 6, Freq= 0, CH_1, rank 0
6745 23:47:28.855211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 23:47:28.855766 ==
6747 23:47:28.856130
6748 23:47:28.856465
6749 23:47:28.858608 TX Vref Scan disable
6750 23:47:28.859157 == TX Byte 0 ==
6751 23:47:28.862064 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 23:47:28.868815 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 23:47:28.869432 == TX Byte 1 ==
6754 23:47:28.871607 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6755 23:47:28.875215 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6756 23:47:28.878658 ==
6757 23:47:28.881931 Dram Type= 6, Freq= 0, CH_1, rank 0
6758 23:47:28.884799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6759 23:47:28.885286 ==
6760 23:47:28.885645
6761 23:47:28.885975
6762 23:47:28.888164 TX Vref Scan disable
6763 23:47:28.888614 == TX Byte 0 ==
6764 23:47:28.891854 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6765 23:47:28.898252 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6766 23:47:28.898788 == TX Byte 1 ==
6767 23:47:28.901856 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6768 23:47:28.908690 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6769 23:47:28.909277
6770 23:47:28.909640 [DATLAT]
6771 23:47:28.910019 Freq=400, CH1 RK0
6772 23:47:28.910347
6773 23:47:28.911943 DATLAT Default: 0xf
6774 23:47:28.912393 0, 0xFFFF, sum = 0
6775 23:47:28.915439 1, 0xFFFF, sum = 0
6776 23:47:28.915994 2, 0xFFFF, sum = 0
6777 23:47:28.918644 3, 0xFFFF, sum = 0
6778 23:47:28.919100 4, 0xFFFF, sum = 0
6779 23:47:28.921683 5, 0xFFFF, sum = 0
6780 23:47:28.922143 6, 0xFFFF, sum = 0
6781 23:47:28.925199 7, 0xFFFF, sum = 0
6782 23:47:28.928508 8, 0xFFFF, sum = 0
6783 23:47:28.929080 9, 0xFFFF, sum = 0
6784 23:47:28.931622 10, 0xFFFF, sum = 0
6785 23:47:28.932156 11, 0xFFFF, sum = 0
6786 23:47:28.935324 12, 0xFFFF, sum = 0
6787 23:47:28.935863 13, 0x0, sum = 1
6788 23:47:28.938234 14, 0x0, sum = 2
6789 23:47:28.938647 15, 0x0, sum = 3
6790 23:47:28.941465 16, 0x0, sum = 4
6791 23:47:28.941879 best_step = 14
6792 23:47:28.942236
6793 23:47:28.942540 ==
6794 23:47:28.944813 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 23:47:28.949108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 23:47:28.949633 ==
6797 23:47:28.951497 RX Vref Scan: 1
6798 23:47:28.951908
6799 23:47:28.955546 RX Vref 0 -> 0, step: 1
6800 23:47:28.956062
6801 23:47:28.956395 RX Delay -359 -> 252, step: 8
6802 23:47:28.956706
6803 23:47:28.958446 Set Vref, RX VrefLevel [Byte0]: 54
6804 23:47:28.961527 [Byte1]: 53
6805 23:47:28.967364
6806 23:47:28.967879 Final RX Vref Byte 0 = 54 to rank0
6807 23:47:28.970475 Final RX Vref Byte 1 = 53 to rank0
6808 23:47:28.973774 Final RX Vref Byte 0 = 54 to rank1
6809 23:47:28.977186 Final RX Vref Byte 1 = 53 to rank1==
6810 23:47:28.980937 Dram Type= 6, Freq= 0, CH_1, rank 0
6811 23:47:28.987100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6812 23:47:28.987656 ==
6813 23:47:28.988022 DQS Delay:
6814 23:47:28.990411 DQS0 = 48, DQS1 = 60
6815 23:47:28.990960 DQM Delay:
6816 23:47:28.991328 DQM0 = 12, DQM1 = 13
6817 23:47:28.993917 DQ Delay:
6818 23:47:28.997161 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6819 23:47:28.997716 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6820 23:47:29.000359 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =12
6821 23:47:29.004129 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6822 23:47:29.004696
6823 23:47:29.007100
6824 23:47:29.013459 [DQSOSCAuto] RK0, (LSB)MR18= 0x832b, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6825 23:47:29.017127 CH1 RK0: MR19=C0C, MR18=832B
6826 23:47:29.024117 CH1_RK0: MR19=0xC0C, MR18=0x832B, DQSOSC=393, MR23=63, INC=382, DEC=254
6827 23:47:29.024761 ==
6828 23:47:29.027455 Dram Type= 6, Freq= 0, CH_1, rank 1
6829 23:47:29.030678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6830 23:47:29.031256 ==
6831 23:47:29.033689 [Gating] SW mode calibration
6832 23:47:29.040908 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6833 23:47:29.044311 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6834 23:47:29.050452 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6835 23:47:29.053817 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6836 23:47:29.057442 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6837 23:47:29.064322 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 23:47:29.067220 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6839 23:47:29.070273 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 23:47:29.077344 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 23:47:29.080624 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 23:47:29.083778 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6843 23:47:29.087347 Total UI for P1: 0, mck2ui 16
6844 23:47:29.090442 best dqsien dly found for B0: ( 0, 14, 24)
6845 23:47:29.093914 Total UI for P1: 0, mck2ui 16
6846 23:47:29.097638 best dqsien dly found for B1: ( 0, 14, 24)
6847 23:47:29.100407 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6848 23:47:29.104348 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6849 23:47:29.104891
6850 23:47:29.110840 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6851 23:47:29.114030 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6852 23:47:29.114483 [Gating] SW calibration Done
6853 23:47:29.117451 ==
6854 23:47:29.117904 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 23:47:29.124157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 23:47:29.124845 ==
6857 23:47:29.125328 RX Vref Scan: 0
6858 23:47:29.125674
6859 23:47:29.127049 RX Vref 0 -> 0, step: 1
6860 23:47:29.127657
6861 23:47:29.130610 RX Delay -410 -> 252, step: 16
6862 23:47:29.133704 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6863 23:47:29.137506 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6864 23:47:29.143943 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6865 23:47:29.147545 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6866 23:47:29.150416 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6867 23:47:29.154134 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6868 23:47:29.160792 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6869 23:47:29.163843 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6870 23:47:29.167791 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6871 23:47:29.170771 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6872 23:47:29.177146 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6873 23:47:29.180680 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6874 23:47:29.184181 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6875 23:47:29.186980 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6876 23:47:29.194291 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6877 23:47:29.197702 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6878 23:47:29.198280 ==
6879 23:47:29.200508 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 23:47:29.204361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 23:47:29.204912 ==
6882 23:47:29.207135 DQS Delay:
6883 23:47:29.207584 DQS0 = 51, DQS1 = 59
6884 23:47:29.211075 DQM Delay:
6885 23:47:29.211619 DQM0 = 16, DQM1 = 19
6886 23:47:29.211984 DQ Delay:
6887 23:47:29.214155 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6888 23:47:29.217527 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6889 23:47:29.220931 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6890 23:47:29.224220 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =32
6891 23:47:29.224768
6892 23:47:29.225169
6893 23:47:29.225505 ==
6894 23:47:29.227605 Dram Type= 6, Freq= 0, CH_1, rank 1
6895 23:47:29.233655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6896 23:47:29.234196 ==
6897 23:47:29.234560
6898 23:47:29.234891
6899 23:47:29.235203 TX Vref Scan disable
6900 23:47:29.237697 == TX Byte 0 ==
6901 23:47:29.240259 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6902 23:47:29.243978 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6903 23:47:29.247705 == TX Byte 1 ==
6904 23:47:29.250228 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6905 23:47:29.253681 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6906 23:47:29.254281 ==
6907 23:47:29.257355 Dram Type= 6, Freq= 0, CH_1, rank 1
6908 23:47:29.264222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6909 23:47:29.264634 ==
6910 23:47:29.264964
6911 23:47:29.265310
6912 23:47:29.265603 TX Vref Scan disable
6913 23:47:29.267309 == TX Byte 0 ==
6914 23:47:29.270431 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6915 23:47:29.273647 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6916 23:47:29.277312 == TX Byte 1 ==
6917 23:47:29.280492 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6918 23:47:29.284060 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6919 23:47:29.284683
6920 23:47:29.288039 [DATLAT]
6921 23:47:29.288590 Freq=400, CH1 RK1
6922 23:47:29.288922
6923 23:47:29.290937 DATLAT Default: 0xe
6924 23:47:29.291563 0, 0xFFFF, sum = 0
6925 23:47:29.293866 1, 0xFFFF, sum = 0
6926 23:47:29.294284 2, 0xFFFF, sum = 0
6927 23:47:29.297203 3, 0xFFFF, sum = 0
6928 23:47:29.297615 4, 0xFFFF, sum = 0
6929 23:47:29.300915 5, 0xFFFF, sum = 0
6930 23:47:29.301399 6, 0xFFFF, sum = 0
6931 23:47:29.303758 7, 0xFFFF, sum = 0
6932 23:47:29.304173 8, 0xFFFF, sum = 0
6933 23:47:29.307220 9, 0xFFFF, sum = 0
6934 23:47:29.307637 10, 0xFFFF, sum = 0
6935 23:47:29.310858 11, 0xFFFF, sum = 0
6936 23:47:29.311275 12, 0xFFFF, sum = 0
6937 23:47:29.314237 13, 0x0, sum = 1
6938 23:47:29.314653 14, 0x0, sum = 2
6939 23:47:29.317656 15, 0x0, sum = 3
6940 23:47:29.318073 16, 0x0, sum = 4
6941 23:47:29.320904 best_step = 14
6942 23:47:29.321354
6943 23:47:29.321680 ==
6944 23:47:29.324046 Dram Type= 6, Freq= 0, CH_1, rank 1
6945 23:47:29.327530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6946 23:47:29.328045 ==
6947 23:47:29.330687 RX Vref Scan: 0
6948 23:47:29.331098
6949 23:47:29.331427 RX Vref 0 -> 0, step: 1
6950 23:47:29.331736
6951 23:47:29.334852 RX Delay -359 -> 252, step: 8
6952 23:47:29.341519 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6953 23:47:29.344941 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6954 23:47:29.348374 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6955 23:47:29.351698 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6956 23:47:29.358732 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6957 23:47:29.362172 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6958 23:47:29.365642 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6959 23:47:29.368743 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6960 23:47:29.375363 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6961 23:47:29.378579 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6962 23:47:29.382869 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6963 23:47:29.385180 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6964 23:47:29.392029 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6965 23:47:29.395523 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6966 23:47:29.398830 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6967 23:47:29.402001 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6968 23:47:29.405719 ==
6969 23:47:29.406126 Dram Type= 6, Freq= 0, CH_1, rank 1
6970 23:47:29.412363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6971 23:47:29.412775 ==
6972 23:47:29.413151 DQS Delay:
6973 23:47:29.415234 DQS0 = 52, DQS1 = 56
6974 23:47:29.415659 DQM Delay:
6975 23:47:29.418593 DQM0 = 13, DQM1 = 9
6976 23:47:29.419004 DQ Delay:
6977 23:47:29.421927 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6978 23:47:29.425786 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6979 23:47:29.428758 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6980 23:47:29.431993 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6981 23:47:29.432399
6982 23:47:29.432722
6983 23:47:29.439711 [DQSOSCAuto] RK1, (LSB)MR18= 0x7389, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6984 23:47:29.442019 CH1 RK1: MR19=C0C, MR18=7389
6985 23:47:29.448680 CH1_RK1: MR19=0xC0C, MR18=0x7389, DQSOSC=392, MR23=63, INC=384, DEC=256
6986 23:47:29.452073 [RxdqsGatingPostProcess] freq 400
6987 23:47:29.455283 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6988 23:47:29.458786 best DQS0 dly(2T, 0.5T) = (0, 10)
6989 23:47:29.462230 best DQS1 dly(2T, 0.5T) = (0, 10)
6990 23:47:29.465213 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6991 23:47:29.468635 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6992 23:47:29.472208 best DQS0 dly(2T, 0.5T) = (0, 10)
6993 23:47:29.475361 best DQS1 dly(2T, 0.5T) = (0, 10)
6994 23:47:29.479442 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6995 23:47:29.482062 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6996 23:47:29.485565 Pre-setting of DQS Precalculation
6997 23:47:29.489076 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6998 23:47:29.495763 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6999 23:47:29.505665 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7000 23:47:29.506207
7001 23:47:29.506566
7002 23:47:29.506898 [Calibration Summary] 800 Mbps
7003 23:47:29.509091 CH 0, Rank 0
7004 23:47:29.512843 SW Impedance : PASS
7005 23:47:29.513338 DUTY Scan : NO K
7006 23:47:29.516061 ZQ Calibration : PASS
7007 23:47:29.516607 Jitter Meter : NO K
7008 23:47:29.518671 CBT Training : PASS
7009 23:47:29.522491 Write leveling : PASS
7010 23:47:29.523046 RX DQS gating : PASS
7011 23:47:29.525569 RX DQ/DQS(RDDQC) : PASS
7012 23:47:29.529525 TX DQ/DQS : PASS
7013 23:47:29.530088 RX DATLAT : PASS
7014 23:47:29.532429 RX DQ/DQS(Engine): PASS
7015 23:47:29.535896 TX OE : NO K
7016 23:47:29.536447 All Pass.
7017 23:47:29.536811
7018 23:47:29.537190 CH 0, Rank 1
7019 23:47:29.538965 SW Impedance : PASS
7020 23:47:29.542348 DUTY Scan : NO K
7021 23:47:29.542805 ZQ Calibration : PASS
7022 23:47:29.545910 Jitter Meter : NO K
7023 23:47:29.548894 CBT Training : PASS
7024 23:47:29.549479 Write leveling : NO K
7025 23:47:29.552576 RX DQS gating : PASS
7026 23:47:29.553157 RX DQ/DQS(RDDQC) : PASS
7027 23:47:29.555537 TX DQ/DQS : PASS
7028 23:47:29.559483 RX DATLAT : PASS
7029 23:47:29.560038 RX DQ/DQS(Engine): PASS
7030 23:47:29.562111 TX OE : NO K
7031 23:47:29.562567 All Pass.
7032 23:47:29.562930
7033 23:47:29.565454 CH 1, Rank 0
7034 23:47:29.565906 SW Impedance : PASS
7035 23:47:29.569019 DUTY Scan : NO K
7036 23:47:29.572884 ZQ Calibration : PASS
7037 23:47:29.573520 Jitter Meter : NO K
7038 23:47:29.575317 CBT Training : PASS
7039 23:47:29.578682 Write leveling : PASS
7040 23:47:29.579162 RX DQS gating : PASS
7041 23:47:29.582342 RX DQ/DQS(RDDQC) : PASS
7042 23:47:29.585494 TX DQ/DQS : PASS
7043 23:47:29.586041 RX DATLAT : PASS
7044 23:47:29.589023 RX DQ/DQS(Engine): PASS
7045 23:47:29.592492 TX OE : NO K
7046 23:47:29.593102 All Pass.
7047 23:47:29.593468
7048 23:47:29.593803 CH 1, Rank 1
7049 23:47:29.595528 SW Impedance : PASS
7050 23:47:29.599261 DUTY Scan : NO K
7051 23:47:29.599816 ZQ Calibration : PASS
7052 23:47:29.602299 Jitter Meter : NO K
7053 23:47:29.602752 CBT Training : PASS
7054 23:47:29.605590 Write leveling : NO K
7055 23:47:29.608785 RX DQS gating : PASS
7056 23:47:29.609287 RX DQ/DQS(RDDQC) : PASS
7057 23:47:29.612249 TX DQ/DQS : PASS
7058 23:47:29.615595 RX DATLAT : PASS
7059 23:47:29.616137 RX DQ/DQS(Engine): PASS
7060 23:47:29.618551 TX OE : NO K
7061 23:47:29.619122 All Pass.
7062 23:47:29.619490
7063 23:47:29.622368 DramC Write-DBI off
7064 23:47:29.625222 PER_BANK_REFRESH: Hybrid Mode
7065 23:47:29.625947 TX_TRACKING: ON
7066 23:47:29.635648 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7067 23:47:29.638955 [FAST_K] Save calibration result to emmc
7068 23:47:29.642042 dramc_set_vcore_voltage set vcore to 725000
7069 23:47:29.645037 Read voltage for 1600, 0
7070 23:47:29.645516 Vio18 = 0
7071 23:47:29.645877 Vcore = 725000
7072 23:47:29.649193 Vdram = 0
7073 23:47:29.649782 Vddq = 0
7074 23:47:29.650147 Vmddr = 0
7075 23:47:29.655540 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7076 23:47:29.658786 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7077 23:47:29.662053 MEM_TYPE=3, freq_sel=13
7078 23:47:29.665363 sv_algorithm_assistance_LP4_3733
7079 23:47:29.668671 ============ PULL DRAM RESETB DOWN ============
7080 23:47:29.671930 ========== PULL DRAM RESETB DOWN end =========
7081 23:47:29.678579 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7082 23:47:29.682222 ===================================
7083 23:47:29.685197 LPDDR4 DRAM CONFIGURATION
7084 23:47:29.689381 ===================================
7085 23:47:29.689930 EX_ROW_EN[0] = 0x0
7086 23:47:29.692046 EX_ROW_EN[1] = 0x0
7087 23:47:29.692493 LP4Y_EN = 0x0
7088 23:47:29.695320 WORK_FSP = 0x1
7089 23:47:29.695771 WL = 0x5
7090 23:47:29.698654 RL = 0x5
7091 23:47:29.699101 BL = 0x2
7092 23:47:29.701987 RPST = 0x0
7093 23:47:29.702501 RD_PRE = 0x0
7094 23:47:29.705470 WR_PRE = 0x1
7095 23:47:29.705918 WR_PST = 0x1
7096 23:47:29.708574 DBI_WR = 0x0
7097 23:47:29.709057 DBI_RD = 0x0
7098 23:47:29.712035 OTF = 0x1
7099 23:47:29.715801 ===================================
7100 23:47:29.718857 ===================================
7101 23:47:29.719311 ANA top config
7102 23:47:29.721656 ===================================
7103 23:47:29.725318 DLL_ASYNC_EN = 0
7104 23:47:29.729075 ALL_SLAVE_EN = 0
7105 23:47:29.732421 NEW_RANK_MODE = 1
7106 23:47:29.732963 DLL_IDLE_MODE = 1
7107 23:47:29.735529 LP45_APHY_COMB_EN = 1
7108 23:47:29.739057 TX_ODT_DIS = 0
7109 23:47:29.741828 NEW_8X_MODE = 1
7110 23:47:29.745229 ===================================
7111 23:47:29.748664 ===================================
7112 23:47:29.751647 data_rate = 3200
7113 23:47:29.752169 CKR = 1
7114 23:47:29.756060 DQ_P2S_RATIO = 8
7115 23:47:29.759252 ===================================
7116 23:47:29.761880 CA_P2S_RATIO = 8
7117 23:47:29.765222 DQ_CA_OPEN = 0
7118 23:47:29.768909 DQ_SEMI_OPEN = 0
7119 23:47:29.771790 CA_SEMI_OPEN = 0
7120 23:47:29.772359 CA_FULL_RATE = 0
7121 23:47:29.775103 DQ_CKDIV4_EN = 0
7122 23:47:29.778771 CA_CKDIV4_EN = 0
7123 23:47:29.782486 CA_PREDIV_EN = 0
7124 23:47:29.785616 PH8_DLY = 12
7125 23:47:29.786068 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7126 23:47:29.789152 DQ_AAMCK_DIV = 4
7127 23:47:29.791782 CA_AAMCK_DIV = 4
7128 23:47:29.795722 CA_ADMCK_DIV = 4
7129 23:47:29.798631 DQ_TRACK_CA_EN = 0
7130 23:47:29.801875 CA_PICK = 1600
7131 23:47:29.805672 CA_MCKIO = 1600
7132 23:47:29.806221 MCKIO_SEMI = 0
7133 23:47:29.808544 PLL_FREQ = 3068
7134 23:47:29.811807 DQ_UI_PI_RATIO = 32
7135 23:47:29.815571 CA_UI_PI_RATIO = 0
7136 23:47:29.818906 ===================================
7137 23:47:29.822264 ===================================
7138 23:47:29.825677 memory_type:LPDDR4
7139 23:47:29.826238 GP_NUM : 10
7140 23:47:29.828735 SRAM_EN : 1
7141 23:47:29.832608 MD32_EN : 0
7142 23:47:29.835940 ===================================
7143 23:47:29.836490 [ANA_INIT] >>>>>>>>>>>>>>
7144 23:47:29.838644 <<<<<< [CONFIGURE PHASE]: ANA_TX
7145 23:47:29.841681 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7146 23:47:29.845094 ===================================
7147 23:47:29.849208 data_rate = 3200,PCW = 0X7600
7148 23:47:29.852007 ===================================
7149 23:47:29.855329 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7150 23:47:29.862185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7151 23:47:29.865567 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7152 23:47:29.872189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7153 23:47:29.875983 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7154 23:47:29.878650 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7155 23:47:29.879397 [ANA_INIT] flow start
7156 23:47:29.881774 [ANA_INIT] PLL >>>>>>>>
7157 23:47:29.885125 [ANA_INIT] PLL <<<<<<<<
7158 23:47:29.885622 [ANA_INIT] MIDPI >>>>>>>>
7159 23:47:29.888549 [ANA_INIT] MIDPI <<<<<<<<
7160 23:47:29.891519 [ANA_INIT] DLL >>>>>>>>
7161 23:47:29.892126 [ANA_INIT] DLL <<<<<<<<
7162 23:47:29.895195 [ANA_INIT] flow end
7163 23:47:29.898598 ============ LP4 DIFF to SE enter ============
7164 23:47:29.905278 ============ LP4 DIFF to SE exit ============
7165 23:47:29.905875 [ANA_INIT] <<<<<<<<<<<<<
7166 23:47:29.908540 [Flow] Enable top DCM control >>>>>
7167 23:47:29.911808 [Flow] Enable top DCM control <<<<<
7168 23:47:29.914925 Enable DLL master slave shuffle
7169 23:47:29.921984 ==============================================================
7170 23:47:29.922417 Gating Mode config
7171 23:47:29.929009 ==============================================================
7172 23:47:29.931464 Config description:
7173 23:47:29.938487 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7174 23:47:29.945002 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7175 23:47:29.951821 SELPH_MODE 0: By rank 1: By Phase
7176 23:47:29.955126 ==============================================================
7177 23:47:29.958893 GAT_TRACK_EN = 1
7178 23:47:29.962291 RX_GATING_MODE = 2
7179 23:47:29.965480 RX_GATING_TRACK_MODE = 2
7180 23:47:29.968809 SELPH_MODE = 1
7181 23:47:29.971930 PICG_EARLY_EN = 1
7182 23:47:29.975114 VALID_LAT_VALUE = 1
7183 23:47:29.982159 ==============================================================
7184 23:47:29.985790 Enter into Gating configuration >>>>
7185 23:47:29.989047 Exit from Gating configuration <<<<
7186 23:47:29.989469 Enter into DVFS_PRE_config >>>>>
7187 23:47:30.002671 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7188 23:47:30.005546 Exit from DVFS_PRE_config <<<<<
7189 23:47:30.009104 Enter into PICG configuration >>>>
7190 23:47:30.011785 Exit from PICG configuration <<<<
7191 23:47:30.012197 [RX_INPUT] configuration >>>>>
7192 23:47:30.015222 [RX_INPUT] configuration <<<<<
7193 23:47:30.021867 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7194 23:47:30.025397 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7195 23:47:30.031813 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7196 23:47:30.038945 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7197 23:47:30.045544 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7198 23:47:30.051805 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7199 23:47:30.055014 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7200 23:47:30.058317 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7201 23:47:30.065162 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7202 23:47:30.068805 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7203 23:47:30.071834 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7204 23:47:30.075006 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7205 23:47:30.078473 ===================================
7206 23:47:30.081838 LPDDR4 DRAM CONFIGURATION
7207 23:47:30.085237 ===================================
7208 23:47:30.088210 EX_ROW_EN[0] = 0x0
7209 23:47:30.088659 EX_ROW_EN[1] = 0x0
7210 23:47:30.091520 LP4Y_EN = 0x0
7211 23:47:30.091939 WORK_FSP = 0x1
7212 23:47:30.095285 WL = 0x5
7213 23:47:30.095732 RL = 0x5
7214 23:47:30.098612 BL = 0x2
7215 23:47:30.099040 RPST = 0x0
7216 23:47:30.101998 RD_PRE = 0x0
7217 23:47:30.102621 WR_PRE = 0x1
7218 23:47:30.105356 WR_PST = 0x1
7219 23:47:30.105766 DBI_WR = 0x0
7220 23:47:30.108656 DBI_RD = 0x0
7221 23:47:30.109198 OTF = 0x1
7222 23:47:30.111822 ===================================
7223 23:47:30.118242 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7224 23:47:30.122022 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7225 23:47:30.125341 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7226 23:47:30.128608 ===================================
7227 23:47:30.132824 LPDDR4 DRAM CONFIGURATION
7228 23:47:30.135082 ===================================
7229 23:47:30.135499 EX_ROW_EN[0] = 0x10
7230 23:47:30.139079 EX_ROW_EN[1] = 0x0
7231 23:47:30.142965 LP4Y_EN = 0x0
7232 23:47:30.143479 WORK_FSP = 0x1
7233 23:47:30.145158 WL = 0x5
7234 23:47:30.145611 RL = 0x5
7235 23:47:30.148796 BL = 0x2
7236 23:47:30.149242 RPST = 0x0
7237 23:47:30.152316 RD_PRE = 0x0
7238 23:47:30.152728 WR_PRE = 0x1
7239 23:47:30.156211 WR_PST = 0x1
7240 23:47:30.156729 DBI_WR = 0x0
7241 23:47:30.158463 DBI_RD = 0x0
7242 23:47:30.158979 OTF = 0x1
7243 23:47:30.161971 ===================================
7244 23:47:30.168566 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7245 23:47:30.169010 ==
7246 23:47:30.171632 Dram Type= 6, Freq= 0, CH_0, rank 0
7247 23:47:30.175327 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7248 23:47:30.178283 ==
7249 23:47:30.178698 [Duty_Offset_Calibration]
7250 23:47:30.181839 B0:2 B1:-1 CA:1
7251 23:47:30.182250
7252 23:47:30.185147 [DutyScan_Calibration_Flow] k_type=0
7253 23:47:30.193548
7254 23:47:30.194070 ==CLK 0==
7255 23:47:30.196734 Final CLK duty delay cell = -4
7256 23:47:30.200133 [-4] MAX Duty = 5031%(X100), DQS PI = 4
7257 23:47:30.202979 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7258 23:47:30.206590 [-4] AVG Duty = 4937%(X100)
7259 23:47:30.207058
7260 23:47:30.210260 CH0 CLK Duty spec in!! Max-Min= 187%
7261 23:47:30.213325 [DutyScan_Calibration_Flow] ====Done====
7262 23:47:30.213840
7263 23:47:30.216324 [DutyScan_Calibration_Flow] k_type=1
7264 23:47:30.232732
7265 23:47:30.233314 ==DQS 0 ==
7266 23:47:30.235938 Final DQS duty delay cell = 0
7267 23:47:30.240200 [0] MAX Duty = 5125%(X100), DQS PI = 20
7268 23:47:30.243128 [0] MIN Duty = 5031%(X100), DQS PI = 12
7269 23:47:30.246075 [0] AVG Duty = 5078%(X100)
7270 23:47:30.246533
7271 23:47:30.246900 ==DQS 1 ==
7272 23:47:30.249443 Final DQS duty delay cell = -4
7273 23:47:30.252708 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7274 23:47:30.256834 [-4] MIN Duty = 5031%(X100), DQS PI = 6
7275 23:47:30.259474 [-4] AVG Duty = 5062%(X100)
7276 23:47:30.259932
7277 23:47:30.263072 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7278 23:47:30.263659
7279 23:47:30.265736 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7280 23:47:30.269667 [DutyScan_Calibration_Flow] ====Done====
7281 23:47:30.270221
7282 23:47:30.272389 [DutyScan_Calibration_Flow] k_type=3
7283 23:47:30.289799
7284 23:47:30.290491 ==DQM 0 ==
7285 23:47:30.293172 Final DQM duty delay cell = 0
7286 23:47:30.296740 [0] MAX Duty = 5000%(X100), DQS PI = 18
7287 23:47:30.299910 [0] MIN Duty = 4875%(X100), DQS PI = 4
7288 23:47:30.303216 [0] AVG Duty = 4937%(X100)
7289 23:47:30.303865
7290 23:47:30.304240 ==DQM 1 ==
7291 23:47:30.306888 Final DQM duty delay cell = 0
7292 23:47:30.309999 [0] MAX Duty = 5218%(X100), DQS PI = 58
7293 23:47:30.313397 [0] MIN Duty = 4969%(X100), DQS PI = 18
7294 23:47:30.316934 [0] AVG Duty = 5093%(X100)
7295 23:47:30.317472
7296 23:47:30.320100 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7297 23:47:30.320549
7298 23:47:30.323136 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7299 23:47:30.326349 [DutyScan_Calibration_Flow] ====Done====
7300 23:47:30.326757
7301 23:47:30.329851 [DutyScan_Calibration_Flow] k_type=2
7302 23:47:30.346968
7303 23:47:30.347466 ==DQ 0 ==
7304 23:47:30.350116 Final DQ duty delay cell = 0
7305 23:47:30.353501 [0] MAX Duty = 5187%(X100), DQS PI = 56
7306 23:47:30.357450 [0] MIN Duty = 5031%(X100), DQS PI = 4
7307 23:47:30.357860 [0] AVG Duty = 5109%(X100)
7308 23:47:30.358181
7309 23:47:30.360639 ==DQ 1 ==
7310 23:47:30.363592 Final DQ duty delay cell = 0
7311 23:47:30.366799 [0] MAX Duty = 5000%(X100), DQS PI = 12
7312 23:47:30.370056 [0] MIN Duty = 4907%(X100), DQS PI = 42
7313 23:47:30.370464 [0] AVG Duty = 4953%(X100)
7314 23:47:30.370787
7315 23:47:30.373638 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7316 23:47:30.374047
7317 23:47:30.377349 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7318 23:47:30.383926 [DutyScan_Calibration_Flow] ====Done====
7319 23:47:30.384332 ==
7320 23:47:30.386860 Dram Type= 6, Freq= 0, CH_1, rank 0
7321 23:47:30.390535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7322 23:47:30.390942 ==
7323 23:47:30.393596 [Duty_Offset_Calibration]
7324 23:47:30.394003 B0:1 B1:1 CA:2
7325 23:47:30.394432
7326 23:47:30.397303 [DutyScan_Calibration_Flow] k_type=0
7327 23:47:30.407355
7328 23:47:30.407862 ==CLK 0==
7329 23:47:30.410838 Final CLK duty delay cell = 0
7330 23:47:30.414125 [0] MAX Duty = 5187%(X100), DQS PI = 24
7331 23:47:30.417829 [0] MIN Duty = 4938%(X100), DQS PI = 50
7332 23:47:30.418282 [0] AVG Duty = 5062%(X100)
7333 23:47:30.420297
7334 23:47:30.423901 CH1 CLK Duty spec in!! Max-Min= 249%
7335 23:47:30.427154 [DutyScan_Calibration_Flow] ====Done====
7336 23:47:30.427714
7337 23:47:30.430525 [DutyScan_Calibration_Flow] k_type=1
7338 23:47:30.447057
7339 23:47:30.447606 ==DQS 0 ==
7340 23:47:30.450294 Final DQS duty delay cell = 0
7341 23:47:30.453742 [0] MAX Duty = 5062%(X100), DQS PI = 20
7342 23:47:30.457065 [0] MIN Duty = 4813%(X100), DQS PI = 52
7343 23:47:30.459952 [0] AVG Duty = 4937%(X100)
7344 23:47:30.460493
7345 23:47:30.460851 ==DQS 1 ==
7346 23:47:30.463336 Final DQS duty delay cell = 0
7347 23:47:30.467039 [0] MAX Duty = 5031%(X100), DQS PI = 34
7348 23:47:30.470657 [0] MIN Duty = 4938%(X100), DQS PI = 12
7349 23:47:30.473926 [0] AVG Duty = 4984%(X100)
7350 23:47:30.474464
7351 23:47:30.476921 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7352 23:47:30.477505
7353 23:47:30.480280 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7354 23:47:30.483308 [DutyScan_Calibration_Flow] ====Done====
7355 23:47:30.483854
7356 23:47:30.486603 [DutyScan_Calibration_Flow] k_type=3
7357 23:47:30.503872
7358 23:47:30.504408 ==DQM 0 ==
7359 23:47:30.507060 Final DQM duty delay cell = 0
7360 23:47:30.510386 [0] MAX Duty = 5156%(X100), DQS PI = 20
7361 23:47:30.514023 [0] MIN Duty = 4844%(X100), DQS PI = 50
7362 23:47:30.516797 [0] AVG Duty = 5000%(X100)
7363 23:47:30.517304
7364 23:47:30.517662 ==DQM 1 ==
7365 23:47:30.520229 Final DQM duty delay cell = 0
7366 23:47:30.523761 [0] MAX Duty = 5156%(X100), DQS PI = 62
7367 23:47:30.527072 [0] MIN Duty = 4907%(X100), DQS PI = 20
7368 23:47:30.530635 [0] AVG Duty = 5031%(X100)
7369 23:47:30.531044
7370 23:47:30.533765 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7371 23:47:30.534175
7372 23:47:30.536853 CH1 DQM 1 Duty spec in!! Max-Min= 249%
7373 23:47:30.540249 [DutyScan_Calibration_Flow] ====Done====
7374 23:47:30.540664
7375 23:47:30.543377 [DutyScan_Calibration_Flow] k_type=2
7376 23:47:30.560568
7377 23:47:30.561236 ==DQ 0 ==
7378 23:47:30.563767 Final DQ duty delay cell = 0
7379 23:47:30.567745 [0] MAX Duty = 5156%(X100), DQS PI = 20
7380 23:47:30.570474 [0] MIN Duty = 4938%(X100), DQS PI = 52
7381 23:47:30.570886 [0] AVG Duty = 5047%(X100)
7382 23:47:30.573795
7383 23:47:30.574212 ==DQ 1 ==
7384 23:47:30.577346 Final DQ duty delay cell = 0
7385 23:47:30.580717 [0] MAX Duty = 5093%(X100), DQS PI = 32
7386 23:47:30.583789 [0] MIN Duty = 5031%(X100), DQS PI = 0
7387 23:47:30.584198 [0] AVG Duty = 5062%(X100)
7388 23:47:30.584523
7389 23:47:30.587260 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7390 23:47:30.590287
7391 23:47:30.590694 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7392 23:47:30.597341 [DutyScan_Calibration_Flow] ====Done====
7393 23:47:30.600632 nWR fixed to 30
7394 23:47:30.601181 [ModeRegInit_LP4] CH0 RK0
7395 23:47:30.603929 [ModeRegInit_LP4] CH0 RK1
7396 23:47:30.607237 [ModeRegInit_LP4] CH1 RK0
7397 23:47:30.607648 [ModeRegInit_LP4] CH1 RK1
7398 23:47:30.610690 match AC timing 5
7399 23:47:30.613972 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7400 23:47:30.617471 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7401 23:47:30.624761 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7402 23:47:30.627446 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7403 23:47:30.633829 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7404 23:47:30.634280 [MiockJmeterHQA]
7405 23:47:30.634605
7406 23:47:30.637803 [DramcMiockJmeter] u1RxGatingPI = 0
7407 23:47:30.638212 0 : 4366, 4137
7408 23:47:30.641060 4 : 4252, 4027
7409 23:47:30.641578 8 : 4363, 4137
7410 23:47:30.644325 12 : 4363, 4137
7411 23:47:30.644742 16 : 4363, 4137
7412 23:47:30.647449 20 : 4255, 4029
7413 23:47:30.647865 24 : 4252, 4026
7414 23:47:30.651322 28 : 4252, 4027
7415 23:47:30.651737 32 : 4363, 4137
7416 23:47:30.652072 36 : 4253, 4026
7417 23:47:30.654043 40 : 4360, 4138
7418 23:47:30.654514 44 : 4250, 4026
7419 23:47:30.657323 48 : 4250, 4027
7420 23:47:30.657745 52 : 4250, 4027
7421 23:47:30.660787 56 : 4253, 4029
7422 23:47:30.661325 60 : 4250, 4027
7423 23:47:30.661668 64 : 4250, 4027
7424 23:47:30.664033 68 : 4363, 4140
7425 23:47:30.664452 72 : 4250, 4027
7426 23:47:30.666994 76 : 4253, 4029
7427 23:47:30.667417 80 : 4250, 4027
7428 23:47:30.671008 84 : 4361, 4137
7429 23:47:30.671537 88 : 4250, 4026
7430 23:47:30.673747 92 : 4360, 4138
7431 23:47:30.674260 96 : 4250, 3399
7432 23:47:30.674603 100 : 4250, 0
7433 23:47:30.677042 104 : 4363, 0
7434 23:47:30.677471 108 : 4252, 0
7435 23:47:30.680349 112 : 4253, 0
7436 23:47:30.680804 116 : 4252, 0
7437 23:47:30.681222 120 : 4361, 0
7438 23:47:30.684123 124 : 4250, 0
7439 23:47:30.684633 128 : 4250, 0
7440 23:47:30.687792 132 : 4252, 0
7441 23:47:30.688302 136 : 4250, 0
7442 23:47:30.688701 140 : 4361, 0
7443 23:47:30.690670 144 : 4250, 0
7444 23:47:30.691092 148 : 4249, 0
7445 23:47:30.691426 152 : 4250, 0
7446 23:47:30.693756 156 : 4253, 0
7447 23:47:30.694177 160 : 4249, 0
7448 23:47:30.697430 164 : 4250, 0
7449 23:47:30.697942 168 : 4253, 0
7450 23:47:30.698280 172 : 4250, 0
7451 23:47:30.701278 176 : 4250, 0
7452 23:47:30.701793 180 : 4253, 0
7453 23:47:30.703889 184 : 4252, 0
7454 23:47:30.704323 188 : 4360, 0
7455 23:47:30.704657 192 : 4361, 0
7456 23:47:30.707460 196 : 4250, 0
7457 23:47:30.707882 200 : 4360, 0
7458 23:47:30.708257 204 : 4250, 0
7459 23:47:30.710930 208 : 4250, 0
7460 23:47:30.711349 212 : 4250, 88
7461 23:47:30.713700 216 : 4363, 3640
7462 23:47:30.714125 220 : 4250, 4027
7463 23:47:30.717484 224 : 4253, 4027
7464 23:47:30.717903 228 : 4250, 4027
7465 23:47:30.720646 232 : 4253, 4029
7466 23:47:30.721099 236 : 4250, 4027
7467 23:47:30.724105 240 : 4250, 4027
7468 23:47:30.724625 244 : 4250, 4026
7469 23:47:30.727048 248 : 4253, 4029
7470 23:47:30.727572 252 : 4250, 4027
7471 23:47:30.727910 256 : 4360, 4138
7472 23:47:30.730562 260 : 4361, 4137
7473 23:47:30.731083 264 : 4250, 4026
7474 23:47:30.733871 268 : 4363, 4139
7475 23:47:30.734333 272 : 4250, 4027
7476 23:47:30.737534 276 : 4250, 4027
7477 23:47:30.737995 280 : 4250, 4026
7478 23:47:30.741102 284 : 4253, 4029
7479 23:47:30.741582 288 : 4250, 4027
7480 23:47:30.744603 292 : 4250, 4027
7481 23:47:30.745209 296 : 4250, 4026
7482 23:47:30.747592 300 : 4253, 4029
7483 23:47:30.748055 304 : 4250, 4027
7484 23:47:30.748420 308 : 4360, 4138
7485 23:47:30.750718 312 : 4360, 4137
7486 23:47:30.751341 316 : 4250, 4026
7487 23:47:30.753886 320 : 4363, 4140
7488 23:47:30.754363 324 : 4250, 4027
7489 23:47:30.756964 328 : 4249, 4027
7490 23:47:30.757474 332 : 4250, 3118
7491 23:47:30.760622 336 : 4253, 265
7492 23:47:30.761065
7493 23:47:30.761397 MIOCK jitter meter ch=0
7494 23:47:30.761704
7495 23:47:30.763728 1T = (336-100) = 236 dly cells
7496 23:47:30.770548 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7497 23:47:30.770962 ==
7498 23:47:30.773639 Dram Type= 6, Freq= 0, CH_0, rank 0
7499 23:47:30.777460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7500 23:47:30.777874 ==
7501 23:47:30.783951 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7502 23:47:30.786936 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7503 23:47:30.793886 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7504 23:47:30.796934 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7505 23:47:30.807049 [CA 0] Center 44 (14~75) winsize 62
7506 23:47:30.810640 [CA 1] Center 43 (13~74) winsize 62
7507 23:47:30.813640 [CA 2] Center 39 (10~68) winsize 59
7508 23:47:30.817607 [CA 3] Center 39 (10~68) winsize 59
7509 23:47:30.820524 [CA 4] Center 37 (7~67) winsize 61
7510 23:47:30.823636 [CA 5] Center 37 (7~67) winsize 61
7511 23:47:30.824049
7512 23:47:30.827077 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7513 23:47:30.827488
7514 23:47:30.830909 [CATrainingPosCal] consider 1 rank data
7515 23:47:30.834137 u2DelayCellTimex100 = 275/100 ps
7516 23:47:30.837318 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7517 23:47:30.843767 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7518 23:47:30.847522 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7519 23:47:30.850570 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7520 23:47:30.854052 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7521 23:47:30.857384 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7522 23:47:30.857946
7523 23:47:30.860519 CA PerBit enable=1, Macro0, CA PI delay=37
7524 23:47:30.861003
7525 23:47:30.864077 [CBTSetCACLKResult] CA Dly = 37
7526 23:47:30.867180 CS Dly: 10 (0~41)
7527 23:47:30.870797 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7528 23:47:30.874234 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7529 23:47:30.874797 ==
7530 23:47:30.877601 Dram Type= 6, Freq= 0, CH_0, rank 1
7531 23:47:30.881022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7532 23:47:30.884185 ==
7533 23:47:30.887447 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7534 23:47:30.891117 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7535 23:47:30.897975 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7536 23:47:30.900610 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7537 23:47:30.911210 [CA 0] Center 43 (13~74) winsize 62
7538 23:47:30.913943 [CA 1] Center 43 (13~74) winsize 62
7539 23:47:30.917818 [CA 2] Center 39 (10~69) winsize 60
7540 23:47:30.921031 [CA 3] Center 38 (9~68) winsize 60
7541 23:47:30.924237 [CA 4] Center 37 (7~67) winsize 61
7542 23:47:30.927704 [CA 5] Center 37 (7~67) winsize 61
7543 23:47:30.928160
7544 23:47:30.930663 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7545 23:47:30.931120
7546 23:47:30.934149 [CATrainingPosCal] consider 2 rank data
7547 23:47:30.938161 u2DelayCellTimex100 = 275/100 ps
7548 23:47:30.940954 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7549 23:47:30.948011 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7550 23:47:30.950996 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7551 23:47:30.953966 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7552 23:47:30.957560 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7553 23:47:30.960802 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7554 23:47:30.961429
7555 23:47:30.964342 CA PerBit enable=1, Macro0, CA PI delay=37
7556 23:47:30.964757
7557 23:47:30.967896 [CBTSetCACLKResult] CA Dly = 37
7558 23:47:30.970982 CS Dly: 11 (0~44)
7559 23:47:30.974236 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7560 23:47:30.977608 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7561 23:47:30.978018
7562 23:47:30.981135 ----->DramcWriteLeveling(PI) begin...
7563 23:47:30.981553 ==
7564 23:47:30.984376 Dram Type= 6, Freq= 0, CH_0, rank 0
7565 23:47:30.987825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7566 23:47:30.990855 ==
7567 23:47:30.991263 Write leveling (Byte 0): 34 => 34
7568 23:47:30.994351 Write leveling (Byte 1): 28 => 28
7569 23:47:30.997624 DramcWriteLeveling(PI) end<-----
7570 23:47:30.998034
7571 23:47:30.998357 ==
7572 23:47:31.000962 Dram Type= 6, Freq= 0, CH_0, rank 0
7573 23:47:31.007464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7574 23:47:31.007881 ==
7575 23:47:31.008203 [Gating] SW mode calibration
7576 23:47:31.017870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7577 23:47:31.020788 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7578 23:47:31.027616 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 23:47:31.030705 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 23:47:31.034471 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 23:47:31.037621 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 23:47:31.044775 1 4 16 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7583 23:47:31.047719 1 4 20 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
7584 23:47:31.051253 1 4 24 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
7585 23:47:31.057603 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 23:47:31.060942 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 23:47:31.064645 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 23:47:31.071530 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7589 23:47:31.074239 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 23:47:31.077692 1 5 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
7591 23:47:31.084429 1 5 20 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
7592 23:47:31.087973 1 5 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
7593 23:47:31.091033 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7594 23:47:31.097927 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 23:47:31.101643 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 23:47:31.104811 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 23:47:31.110789 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7598 23:47:31.114822 1 6 16 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
7599 23:47:31.118219 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7600 23:47:31.121659 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7601 23:47:31.127616 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 23:47:31.131287 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 23:47:31.134855 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 23:47:31.141135 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 23:47:31.145062 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 23:47:31.147947 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7607 23:47:31.154312 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7608 23:47:31.158403 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7609 23:47:31.160909 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7610 23:47:31.167876 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 23:47:31.171458 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 23:47:31.174816 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 23:47:31.181154 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 23:47:31.184762 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 23:47:31.188112 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 23:47:31.194725 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 23:47:31.198025 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 23:47:31.201741 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 23:47:31.204879 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 23:47:31.211191 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 23:47:31.214809 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7622 23:47:31.218067 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7623 23:47:31.225030 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7624 23:47:31.228240 Total UI for P1: 0, mck2ui 16
7625 23:47:31.231812 best dqsien dly found for B0: ( 1, 9, 14)
7626 23:47:31.234401 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7627 23:47:31.238466 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 23:47:31.241699 Total UI for P1: 0, mck2ui 16
7629 23:47:31.244507 best dqsien dly found for B1: ( 1, 9, 22)
7630 23:47:31.248106 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7631 23:47:31.251667 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7632 23:47:31.252302
7633 23:47:31.257618 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7634 23:47:31.261441 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7635 23:47:31.264638 [Gating] SW calibration Done
7636 23:47:31.265131 ==
7637 23:47:31.267729 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 23:47:31.271107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 23:47:31.271664 ==
7640 23:47:31.272032 RX Vref Scan: 0
7641 23:47:31.272369
7642 23:47:31.274467 RX Vref 0 -> 0, step: 1
7643 23:47:31.274953
7644 23:47:31.278229 RX Delay 0 -> 252, step: 8
7645 23:47:31.281857 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7646 23:47:31.284177 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7647 23:47:31.291138 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7648 23:47:31.294457 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7649 23:47:31.297780 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7650 23:47:31.301087 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7651 23:47:31.304717 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7652 23:47:31.307749 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7653 23:47:31.314332 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7654 23:47:31.317704 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7655 23:47:31.321223 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7656 23:47:31.324115 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7657 23:47:31.331103 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7658 23:47:31.334202 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7659 23:47:31.337859 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7660 23:47:31.341044 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7661 23:47:31.341500 ==
7662 23:47:31.344416 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 23:47:31.347726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 23:47:31.351153 ==
7665 23:47:31.351706 DQS Delay:
7666 23:47:31.352093 DQS0 = 0, DQS1 = 0
7667 23:47:31.354072 DQM Delay:
7668 23:47:31.354526 DQM0 = 132, DQM1 = 124
7669 23:47:31.357483 DQ Delay:
7670 23:47:31.360844 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7671 23:47:31.364699 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7672 23:47:31.367598 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =115
7673 23:47:31.370854 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7674 23:47:31.371404
7675 23:47:31.371765
7676 23:47:31.372101 ==
7677 23:47:31.374278 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 23:47:31.377992 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 23:47:31.378453 ==
7680 23:47:31.378817
7681 23:47:31.379147
7682 23:47:31.381398 TX Vref Scan disable
7683 23:47:31.384880 == TX Byte 0 ==
7684 23:47:31.388290 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7685 23:47:31.391225 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7686 23:47:31.394530 == TX Byte 1 ==
7687 23:47:31.397732 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7688 23:47:31.401253 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7689 23:47:31.401802 ==
7690 23:47:31.404156 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 23:47:31.410869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 23:47:31.411430 ==
7693 23:47:31.424191
7694 23:47:31.427808 TX Vref early break, caculate TX vref
7695 23:47:31.430958 TX Vref=16, minBit 1, minWin=22, winSum=372
7696 23:47:31.434078 TX Vref=18, minBit 7, minWin=22, winSum=380
7697 23:47:31.438439 TX Vref=20, minBit 1, minWin=23, winSum=388
7698 23:47:31.441372 TX Vref=22, minBit 4, minWin=23, winSum=395
7699 23:47:31.445059 TX Vref=24, minBit 4, minWin=24, winSum=407
7700 23:47:31.451226 TX Vref=26, minBit 1, minWin=25, winSum=419
7701 23:47:31.454871 TX Vref=28, minBit 4, minWin=25, winSum=425
7702 23:47:31.457999 TX Vref=30, minBit 2, minWin=25, winSum=422
7703 23:47:31.461361 TX Vref=32, minBit 4, minWin=25, winSum=419
7704 23:47:31.464421 TX Vref=34, minBit 4, minWin=24, winSum=409
7705 23:47:31.467303 TX Vref=36, minBit 9, minWin=23, winSum=395
7706 23:47:31.474560 [TxChooseVref] Worse bit 4, Min win 25, Win sum 425, Final Vref 28
7707 23:47:31.475114
7708 23:47:31.477508 Final TX Range 0 Vref 28
7709 23:47:31.477968
7710 23:47:31.478328 ==
7711 23:47:31.481469 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 23:47:31.484277 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 23:47:31.484832 ==
7714 23:47:31.485280
7715 23:47:31.485621
7716 23:47:31.487846 TX Vref Scan disable
7717 23:47:31.495123 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7718 23:47:31.495680 == TX Byte 0 ==
7719 23:47:31.498002 u2DelayCellOfst[0]=17 cells (5 PI)
7720 23:47:31.501220 u2DelayCellOfst[1]=21 cells (6 PI)
7721 23:47:31.504774 u2DelayCellOfst[2]=10 cells (3 PI)
7722 23:47:31.508051 u2DelayCellOfst[3]=14 cells (4 PI)
7723 23:47:31.511303 u2DelayCellOfst[4]=10 cells (3 PI)
7724 23:47:31.514229 u2DelayCellOfst[5]=0 cells (0 PI)
7725 23:47:31.517819 u2DelayCellOfst[6]=21 cells (6 PI)
7726 23:47:31.521183 u2DelayCellOfst[7]=21 cells (6 PI)
7727 23:47:31.524550 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7728 23:47:31.528132 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7729 23:47:31.531635 == TX Byte 1 ==
7730 23:47:31.532191 u2DelayCellOfst[8]=0 cells (0 PI)
7731 23:47:31.534256 u2DelayCellOfst[9]=3 cells (1 PI)
7732 23:47:31.537456 u2DelayCellOfst[10]=10 cells (3 PI)
7733 23:47:31.541021 u2DelayCellOfst[11]=0 cells (0 PI)
7734 23:47:31.544013 u2DelayCellOfst[12]=14 cells (4 PI)
7735 23:47:31.547881 u2DelayCellOfst[13]=14 cells (4 PI)
7736 23:47:31.551491 u2DelayCellOfst[14]=17 cells (5 PI)
7737 23:47:31.554237 u2DelayCellOfst[15]=14 cells (4 PI)
7738 23:47:31.557483 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7739 23:47:31.564650 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7740 23:47:31.565228 DramC Write-DBI on
7741 23:47:31.565594 ==
7742 23:47:31.567409 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 23:47:31.570754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 23:47:31.574693 ==
7745 23:47:31.575245
7746 23:47:31.575607
7747 23:47:31.575940 TX Vref Scan disable
7748 23:47:31.577978 == TX Byte 0 ==
7749 23:47:31.581360 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7750 23:47:31.585276 == TX Byte 1 ==
7751 23:47:31.588706 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7752 23:47:31.589325 DramC Write-DBI off
7753 23:47:31.591313
7754 23:47:31.591763 [DATLAT]
7755 23:47:31.592123 Freq=1600, CH0 RK0
7756 23:47:31.592463
7757 23:47:31.594833 DATLAT Default: 0xf
7758 23:47:31.595284 0, 0xFFFF, sum = 0
7759 23:47:31.598173 1, 0xFFFF, sum = 0
7760 23:47:31.598634 2, 0xFFFF, sum = 0
7761 23:47:31.601652 3, 0xFFFF, sum = 0
7762 23:47:31.602214 4, 0xFFFF, sum = 0
7763 23:47:31.605183 5, 0xFFFF, sum = 0
7764 23:47:31.605791 6, 0xFFFF, sum = 0
7765 23:47:31.608693 7, 0xFFFF, sum = 0
7766 23:47:31.611088 8, 0xFFFF, sum = 0
7767 23:47:31.611550 9, 0xFFFF, sum = 0
7768 23:47:31.614528 10, 0xFFFF, sum = 0
7769 23:47:31.614991 11, 0xFFFF, sum = 0
7770 23:47:31.618117 12, 0xFFFF, sum = 0
7771 23:47:31.618683 13, 0xFFFF, sum = 0
7772 23:47:31.621046 14, 0x0, sum = 1
7773 23:47:31.621514 15, 0x0, sum = 2
7774 23:47:31.624704 16, 0x0, sum = 3
7775 23:47:31.625303 17, 0x0, sum = 4
7776 23:47:31.628288 best_step = 15
7777 23:47:31.628858
7778 23:47:31.629287 ==
7779 23:47:31.631440 Dram Type= 6, Freq= 0, CH_0, rank 0
7780 23:47:31.634515 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7781 23:47:31.634975 ==
7782 23:47:31.635337 RX Vref Scan: 1
7783 23:47:31.635672
7784 23:47:31.638043 Set Vref Range= 24 -> 127
7785 23:47:31.638496
7786 23:47:31.641552 RX Vref 24 -> 127, step: 1
7787 23:47:31.642008
7788 23:47:31.644506 RX Delay 11 -> 252, step: 4
7789 23:47:31.644961
7790 23:47:31.648352 Set Vref, RX VrefLevel [Byte0]: 24
7791 23:47:31.652061 [Byte1]: 24
7792 23:47:31.652747
7793 23:47:31.654373 Set Vref, RX VrefLevel [Byte0]: 25
7794 23:47:31.657832 [Byte1]: 25
7795 23:47:31.658293
7796 23:47:31.661300 Set Vref, RX VrefLevel [Byte0]: 26
7797 23:47:31.664274 [Byte1]: 26
7798 23:47:31.668280
7799 23:47:31.668734 Set Vref, RX VrefLevel [Byte0]: 27
7800 23:47:31.671446 [Byte1]: 27
7801 23:47:31.675744
7802 23:47:31.676158 Set Vref, RX VrefLevel [Byte0]: 28
7803 23:47:31.678744 [Byte1]: 28
7804 23:47:31.683354
7805 23:47:31.683761 Set Vref, RX VrefLevel [Byte0]: 29
7806 23:47:31.686628 [Byte1]: 29
7807 23:47:31.691464
7808 23:47:31.691873 Set Vref, RX VrefLevel [Byte0]: 30
7809 23:47:31.694624 [Byte1]: 30
7810 23:47:31.699691
7811 23:47:31.700116 Set Vref, RX VrefLevel [Byte0]: 31
7812 23:47:31.701995 [Byte1]: 31
7813 23:47:31.706179
7814 23:47:31.706589 Set Vref, RX VrefLevel [Byte0]: 32
7815 23:47:31.709523 [Byte1]: 32
7816 23:47:31.714194
7817 23:47:31.714633 Set Vref, RX VrefLevel [Byte0]: 33
7818 23:47:31.717443 [Byte1]: 33
7819 23:47:31.721187
7820 23:47:31.721597 Set Vref, RX VrefLevel [Byte0]: 34
7821 23:47:31.724861 [Byte1]: 34
7822 23:47:31.729345
7823 23:47:31.729754 Set Vref, RX VrefLevel [Byte0]: 35
7824 23:47:31.732048 [Byte1]: 35
7825 23:47:31.736510
7826 23:47:31.736919 Set Vref, RX VrefLevel [Byte0]: 36
7827 23:47:31.739894 [Byte1]: 36
7828 23:47:31.744432
7829 23:47:31.744841 Set Vref, RX VrefLevel [Byte0]: 37
7830 23:47:31.747446 [Byte1]: 37
7831 23:47:31.752216
7832 23:47:31.752624 Set Vref, RX VrefLevel [Byte0]: 38
7833 23:47:31.755293 [Byte1]: 38
7834 23:47:31.759526
7835 23:47:31.759932 Set Vref, RX VrefLevel [Byte0]: 39
7836 23:47:31.762623 [Byte1]: 39
7837 23:47:31.766826
7838 23:47:31.767236 Set Vref, RX VrefLevel [Byte0]: 40
7839 23:47:31.770344 [Byte1]: 40
7840 23:47:31.774956
7841 23:47:31.775379 Set Vref, RX VrefLevel [Byte0]: 41
7842 23:47:31.778355 [Byte1]: 41
7843 23:47:31.782240
7844 23:47:31.782755 Set Vref, RX VrefLevel [Byte0]: 42
7845 23:47:31.786033 [Byte1]: 42
7846 23:47:31.789920
7847 23:47:31.790331 Set Vref, RX VrefLevel [Byte0]: 43
7848 23:47:31.793378 [Byte1]: 43
7849 23:47:31.797526
7850 23:47:31.797941 Set Vref, RX VrefLevel [Byte0]: 44
7851 23:47:31.801181 [Byte1]: 44
7852 23:47:31.805182
7853 23:47:31.805595 Set Vref, RX VrefLevel [Byte0]: 45
7854 23:47:31.808504 [Byte1]: 45
7855 23:47:31.813061
7856 23:47:31.813578 Set Vref, RX VrefLevel [Byte0]: 46
7857 23:47:31.815941 [Byte1]: 46
7858 23:47:31.820933
7859 23:47:31.821434 Set Vref, RX VrefLevel [Byte0]: 47
7860 23:47:31.823721 [Byte1]: 47
7861 23:47:31.828657
7862 23:47:31.829202 Set Vref, RX VrefLevel [Byte0]: 48
7863 23:47:31.831402 [Byte1]: 48
7864 23:47:31.836243
7865 23:47:31.836772 Set Vref, RX VrefLevel [Byte0]: 49
7866 23:47:31.838881 [Byte1]: 49
7867 23:47:31.843595
7868 23:47:31.844109 Set Vref, RX VrefLevel [Byte0]: 50
7869 23:47:31.846418 [Byte1]: 50
7870 23:47:31.851216
7871 23:47:31.851731 Set Vref, RX VrefLevel [Byte0]: 51
7872 23:47:31.854318 [Byte1]: 51
7873 23:47:31.858540
7874 23:47:31.859051 Set Vref, RX VrefLevel [Byte0]: 52
7875 23:47:31.861501 [Byte1]: 52
7876 23:47:31.865763
7877 23:47:31.866177 Set Vref, RX VrefLevel [Byte0]: 53
7878 23:47:31.869444 [Byte1]: 53
7879 23:47:31.874060
7880 23:47:31.874599 Set Vref, RX VrefLevel [Byte0]: 54
7881 23:47:31.876944 [Byte1]: 54
7882 23:47:31.881437
7883 23:47:31.881846 Set Vref, RX VrefLevel [Byte0]: 55
7884 23:47:31.884735 [Byte1]: 55
7885 23:47:31.889233
7886 23:47:31.889737 Set Vref, RX VrefLevel [Byte0]: 56
7887 23:47:31.892592 [Byte1]: 56
7888 23:47:31.896498
7889 23:47:31.897064 Set Vref, RX VrefLevel [Byte0]: 57
7890 23:47:31.900272 [Byte1]: 57
7891 23:47:31.904618
7892 23:47:31.905241 Set Vref, RX VrefLevel [Byte0]: 58
7893 23:47:31.907912 [Byte1]: 58
7894 23:47:31.912515
7895 23:47:31.913132 Set Vref, RX VrefLevel [Byte0]: 59
7896 23:47:31.915601 [Byte1]: 59
7897 23:47:31.919371
7898 23:47:31.919824 Set Vref, RX VrefLevel [Byte0]: 60
7899 23:47:31.923145 [Byte1]: 60
7900 23:47:31.927564
7901 23:47:31.928182 Set Vref, RX VrefLevel [Byte0]: 61
7902 23:47:31.930744 [Byte1]: 61
7903 23:47:31.934678
7904 23:47:31.935231 Set Vref, RX VrefLevel [Byte0]: 62
7905 23:47:31.938203 [Byte1]: 62
7906 23:47:31.942501
7907 23:47:31.943105 Set Vref, RX VrefLevel [Byte0]: 63
7908 23:47:31.945858 [Byte1]: 63
7909 23:47:31.949834
7910 23:47:31.950397 Set Vref, RX VrefLevel [Byte0]: 64
7911 23:47:31.953630 [Byte1]: 64
7912 23:47:31.958276
7913 23:47:31.958735 Set Vref, RX VrefLevel [Byte0]: 65
7914 23:47:31.960803 [Byte1]: 65
7915 23:47:31.964936
7916 23:47:31.965426 Set Vref, RX VrefLevel [Byte0]: 66
7917 23:47:31.968173 [Byte1]: 66
7918 23:47:31.973451
7919 23:47:31.974004 Set Vref, RX VrefLevel [Byte0]: 67
7920 23:47:31.976015 [Byte1]: 67
7921 23:47:31.980474
7922 23:47:31.981062 Set Vref, RX VrefLevel [Byte0]: 68
7923 23:47:31.983689 [Byte1]: 68
7924 23:47:31.988090
7925 23:47:31.988649 Set Vref, RX VrefLevel [Byte0]: 69
7926 23:47:31.991476 [Byte1]: 69
7927 23:47:31.996166
7928 23:47:31.996716 Set Vref, RX VrefLevel [Byte0]: 70
7929 23:47:31.998813 [Byte1]: 70
7930 23:47:32.003855
7931 23:47:32.004415 Set Vref, RX VrefLevel [Byte0]: 71
7932 23:47:32.006349 [Byte1]: 71
7933 23:47:32.010855
7934 23:47:32.011410 Set Vref, RX VrefLevel [Byte0]: 72
7935 23:47:32.014047 [Byte1]: 72
7936 23:47:32.018717
7937 23:47:32.019271 Set Vref, RX VrefLevel [Byte0]: 73
7938 23:47:32.021632 [Byte1]: 73
7939 23:47:32.026668
7940 23:47:32.027224 Set Vref, RX VrefLevel [Byte0]: 74
7941 23:47:32.029066 [Byte1]: 74
7942 23:47:32.033986
7943 23:47:32.034561 Set Vref, RX VrefLevel [Byte0]: 75
7944 23:47:32.036643 [Byte1]: 75
7945 23:47:32.041335
7946 23:47:32.041894 Set Vref, RX VrefLevel [Byte0]: 76
7947 23:47:32.045116 [Byte1]: 76
7948 23:47:32.048929
7949 23:47:32.049544 Final RX Vref Byte 0 = 64 to rank0
7950 23:47:32.052867 Final RX Vref Byte 1 = 63 to rank0
7951 23:47:32.055508 Final RX Vref Byte 0 = 64 to rank1
7952 23:47:32.058707 Final RX Vref Byte 1 = 63 to rank1==
7953 23:47:32.062448 Dram Type= 6, Freq= 0, CH_0, rank 0
7954 23:47:32.068686 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7955 23:47:32.069189 ==
7956 23:47:32.069558 DQS Delay:
7957 23:47:32.069894 DQS0 = 0, DQS1 = 0
7958 23:47:32.072397 DQM Delay:
7959 23:47:32.072946 DQM0 = 129, DQM1 = 121
7960 23:47:32.076477 DQ Delay:
7961 23:47:32.078834 DQ0 =130, DQ1 =132, DQ2 =124, DQ3 =126
7962 23:47:32.081900 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7963 23:47:32.085379 DQ8 =110, DQ9 =108, DQ10 =122, DQ11 =116
7964 23:47:32.088634 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7965 23:47:32.089131
7966 23:47:32.089502
7967 23:47:32.089840
7968 23:47:32.092326 [DramC_TX_OE_Calibration] TA2
7969 23:47:32.095988 Original DQ_B0 (3 6) =30, OEN = 27
7970 23:47:32.099001 Original DQ_B1 (3 6) =30, OEN = 27
7971 23:47:32.102731 24, 0x0, End_B0=24 End_B1=24
7972 23:47:32.103297 25, 0x0, End_B0=25 End_B1=25
7973 23:47:32.105458 26, 0x0, End_B0=26 End_B1=26
7974 23:47:32.109060 27, 0x0, End_B0=27 End_B1=27
7975 23:47:32.112415 28, 0x0, End_B0=28 End_B1=28
7976 23:47:32.113114 29, 0x0, End_B0=29 End_B1=29
7977 23:47:32.115342 30, 0x0, End_B0=30 End_B1=30
7978 23:47:32.119364 31, 0x4141, End_B0=30 End_B1=30
7979 23:47:32.121878 Byte0 end_step=30 best_step=27
7980 23:47:32.125701 Byte1 end_step=30 best_step=27
7981 23:47:32.128858 Byte0 TX OE(2T, 0.5T) = (3, 3)
7982 23:47:32.129497 Byte1 TX OE(2T, 0.5T) = (3, 3)
7983 23:47:32.129868
7984 23:47:32.132340
7985 23:47:32.138818 [DQSOSCAuto] RK0, (LSB)MR18= 0x150a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
7986 23:47:32.142660 CH0 RK0: MR19=303, MR18=150A
7987 23:47:32.148963 CH0_RK0: MR19=0x303, MR18=0x150A, DQSOSC=399, MR23=63, INC=23, DEC=15
7988 23:47:32.149573
7989 23:47:32.152487 ----->DramcWriteLeveling(PI) begin...
7990 23:47:32.153111 ==
7991 23:47:32.156407 Dram Type= 6, Freq= 0, CH_0, rank 1
7992 23:47:32.158468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7993 23:47:32.158929 ==
7994 23:47:32.162479 Write leveling (Byte 0): 34 => 34
7995 23:47:32.165281 Write leveling (Byte 1): 28 => 28
7996 23:47:32.169045 DramcWriteLeveling(PI) end<-----
7997 23:47:32.169525
7998 23:47:32.169921 ==
7999 23:47:32.172060 Dram Type= 6, Freq= 0, CH_0, rank 1
8000 23:47:32.175667 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8001 23:47:32.176219 ==
8002 23:47:32.178812 [Gating] SW mode calibration
8003 23:47:32.185646 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8004 23:47:32.192183 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8005 23:47:32.195319 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 23:47:32.198599 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 23:47:32.205238 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8008 23:47:32.208912 1 4 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8009 23:47:32.212087 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8010 23:47:32.218630 1 4 20 | B1->B0 | 3130 3434 | 1 1 | (1 1) (1 1)
8011 23:47:32.221608 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8012 23:47:32.225525 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8013 23:47:32.232485 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8014 23:47:32.236052 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8015 23:47:32.239082 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8016 23:47:32.245595 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 1)
8017 23:47:32.248885 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8018 23:47:32.252028 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8019 23:47:32.259054 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8020 23:47:32.261892 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8021 23:47:32.265609 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8022 23:47:32.268546 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 23:47:32.275732 1 6 8 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
8024 23:47:32.279011 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8025 23:47:32.281913 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8026 23:47:32.289148 1 6 20 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8027 23:47:32.292141 1 6 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8028 23:47:32.295265 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8029 23:47:32.301877 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 23:47:32.305401 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8031 23:47:32.308870 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8032 23:47:32.315340 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8033 23:47:32.318672 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8034 23:47:32.322160 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8035 23:47:32.328682 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 23:47:32.332375 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 23:47:32.335787 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8038 23:47:32.342196 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 23:47:32.345377 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 23:47:32.348808 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 23:47:32.351987 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 23:47:32.358422 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 23:47:32.361832 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 23:47:32.364969 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 23:47:32.371979 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 23:47:32.375042 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 23:47:32.378539 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8048 23:47:32.385256 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8049 23:47:32.388173 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8050 23:47:32.391343 Total UI for P1: 0, mck2ui 16
8051 23:47:32.394783 best dqsien dly found for B0: ( 1, 9, 10)
8052 23:47:32.398440 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8053 23:47:32.404796 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 23:47:32.405280 Total UI for P1: 0, mck2ui 16
8055 23:47:32.411367 best dqsien dly found for B1: ( 1, 9, 18)
8056 23:47:32.415099 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8057 23:47:32.418482 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8058 23:47:32.418915
8059 23:47:32.421874 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8060 23:47:32.424538 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8061 23:47:32.427862 [Gating] SW calibration Done
8062 23:47:32.428273 ==
8063 23:47:32.431233 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 23:47:32.434077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 23:47:32.434158 ==
8066 23:47:32.437789 RX Vref Scan: 0
8067 23:47:32.437870
8068 23:47:32.437933 RX Vref 0 -> 0, step: 1
8069 23:47:32.440820
8070 23:47:32.440926 RX Delay 0 -> 252, step: 8
8071 23:47:32.444256 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8072 23:47:32.451189 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8073 23:47:32.454595 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8074 23:47:32.457910 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8075 23:47:32.461052 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8076 23:47:32.464615 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8077 23:47:32.471185 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8078 23:47:32.474349 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8079 23:47:32.477749 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8080 23:47:32.481209 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8081 23:47:32.484126 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8082 23:47:32.490745 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8083 23:47:32.494900 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8084 23:47:32.499056 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8085 23:47:32.500949 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8086 23:47:32.507695 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8087 23:47:32.508150 ==
8088 23:47:32.511572 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 23:47:32.514608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 23:47:32.515022 ==
8091 23:47:32.515349 DQS Delay:
8092 23:47:32.517901 DQS0 = 0, DQS1 = 0
8093 23:47:32.518315 DQM Delay:
8094 23:47:32.521462 DQM0 = 131, DQM1 = 124
8095 23:47:32.521876 DQ Delay:
8096 23:47:32.524863 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8097 23:47:32.527818 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8098 23:47:32.531579 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =115
8099 23:47:32.535215 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8100 23:47:32.535731
8101 23:47:32.536133
8102 23:47:32.536446 ==
8103 23:47:32.538500 Dram Type= 6, Freq= 0, CH_0, rank 1
8104 23:47:32.544834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8105 23:47:32.545393 ==
8106 23:47:32.545730
8107 23:47:32.546036
8108 23:47:32.546326 TX Vref Scan disable
8109 23:47:32.548792 == TX Byte 0 ==
8110 23:47:32.552204 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8111 23:47:32.555172 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8112 23:47:32.558308 == TX Byte 1 ==
8113 23:47:32.562230 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8114 23:47:32.564761 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8115 23:47:32.569085 ==
8116 23:47:32.571733 Dram Type= 6, Freq= 0, CH_0, rank 1
8117 23:47:32.575174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8118 23:47:32.575714 ==
8119 23:47:32.589284
8120 23:47:32.593094 TX Vref early break, caculate TX vref
8121 23:47:32.596529 TX Vref=16, minBit 0, minWin=23, winSum=379
8122 23:47:32.599155 TX Vref=18, minBit 9, minWin=23, winSum=386
8123 23:47:32.602613 TX Vref=20, minBit 1, minWin=24, winSum=400
8124 23:47:32.606038 TX Vref=22, minBit 3, minWin=24, winSum=407
8125 23:47:32.609752 TX Vref=24, minBit 2, minWin=25, winSum=413
8126 23:47:32.615587 TX Vref=26, minBit 3, minWin=25, winSum=424
8127 23:47:32.619442 TX Vref=28, minBit 0, minWin=26, winSum=427
8128 23:47:32.622721 TX Vref=30, minBit 4, minWin=25, winSum=425
8129 23:47:32.625827 TX Vref=32, minBit 2, minWin=25, winSum=416
8130 23:47:32.629180 TX Vref=34, minBit 4, minWin=24, winSum=408
8131 23:47:32.632126 TX Vref=36, minBit 0, minWin=24, winSum=398
8132 23:47:32.639013 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8133 23:47:32.639484
8134 23:47:32.642213 Final TX Range 0 Vref 28
8135 23:47:32.642669
8136 23:47:32.643006 ==
8137 23:47:32.645934 Dram Type= 6, Freq= 0, CH_0, rank 1
8138 23:47:32.648714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8139 23:47:32.649162 ==
8140 23:47:32.649497
8141 23:47:32.649798
8142 23:47:32.652080 TX Vref Scan disable
8143 23:47:32.659009 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8144 23:47:32.659424 == TX Byte 0 ==
8145 23:47:32.662129 u2DelayCellOfst[0]=10 cells (3 PI)
8146 23:47:32.665523 u2DelayCellOfst[1]=17 cells (5 PI)
8147 23:47:32.668403 u2DelayCellOfst[2]=7 cells (2 PI)
8148 23:47:32.672574 u2DelayCellOfst[3]=10 cells (3 PI)
8149 23:47:32.675771 u2DelayCellOfst[4]=7 cells (2 PI)
8150 23:47:32.678965 u2DelayCellOfst[5]=0 cells (0 PI)
8151 23:47:32.681996 u2DelayCellOfst[6]=17 cells (5 PI)
8152 23:47:32.685197 u2DelayCellOfst[7]=17 cells (5 PI)
8153 23:47:32.688514 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8154 23:47:32.692314 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8155 23:47:32.695628 == TX Byte 1 ==
8156 23:47:32.698447 u2DelayCellOfst[8]=0 cells (0 PI)
8157 23:47:32.698533 u2DelayCellOfst[9]=0 cells (0 PI)
8158 23:47:32.702158 u2DelayCellOfst[10]=7 cells (2 PI)
8159 23:47:32.705472 u2DelayCellOfst[11]=0 cells (0 PI)
8160 23:47:32.708589 u2DelayCellOfst[12]=14 cells (4 PI)
8161 23:47:32.711995 u2DelayCellOfst[13]=10 cells (3 PI)
8162 23:47:32.714976 u2DelayCellOfst[14]=17 cells (5 PI)
8163 23:47:32.718852 u2DelayCellOfst[15]=10 cells (3 PI)
8164 23:47:32.721811 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8165 23:47:32.728325 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8166 23:47:32.728475 DramC Write-DBI on
8167 23:47:32.728592 ==
8168 23:47:32.731786 Dram Type= 6, Freq= 0, CH_0, rank 1
8169 23:47:32.735468 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8170 23:47:32.738679 ==
8171 23:47:32.738759
8172 23:47:32.738821
8173 23:47:32.738879 TX Vref Scan disable
8174 23:47:32.742728 == TX Byte 0 ==
8175 23:47:32.745725 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8176 23:47:32.748468 == TX Byte 1 ==
8177 23:47:32.751749 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8178 23:47:32.755214 DramC Write-DBI off
8179 23:47:32.755314
8180 23:47:32.755393 [DATLAT]
8181 23:47:32.755466 Freq=1600, CH0 RK1
8182 23:47:32.755537
8183 23:47:32.758697 DATLAT Default: 0xf
8184 23:47:32.758807 0, 0xFFFF, sum = 0
8185 23:47:32.761918 1, 0xFFFF, sum = 0
8186 23:47:32.765576 2, 0xFFFF, sum = 0
8187 23:47:32.765699 3, 0xFFFF, sum = 0
8188 23:47:32.768695 4, 0xFFFF, sum = 0
8189 23:47:32.768776 5, 0xFFFF, sum = 0
8190 23:47:32.772144 6, 0xFFFF, sum = 0
8191 23:47:32.772226 7, 0xFFFF, sum = 0
8192 23:47:32.775598 8, 0xFFFF, sum = 0
8193 23:47:32.775770 9, 0xFFFF, sum = 0
8194 23:47:32.778903 10, 0xFFFF, sum = 0
8195 23:47:32.779058 11, 0xFFFF, sum = 0
8196 23:47:32.781805 12, 0xFFFF, sum = 0
8197 23:47:32.781945 13, 0xFFFF, sum = 0
8198 23:47:32.785322 14, 0x0, sum = 1
8199 23:47:32.785427 15, 0x0, sum = 2
8200 23:47:32.788286 16, 0x0, sum = 3
8201 23:47:32.788441 17, 0x0, sum = 4
8202 23:47:32.791754 best_step = 15
8203 23:47:32.791867
8204 23:47:32.791957 ==
8205 23:47:32.794965 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 23:47:32.798599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 23:47:32.798740 ==
8208 23:47:32.801686 RX Vref Scan: 0
8209 23:47:32.801828
8210 23:47:32.801937 RX Vref 0 -> 0, step: 1
8211 23:47:32.802040
8212 23:47:32.805016 RX Delay 11 -> 252, step: 4
8213 23:47:32.808430 iDelay=191, Bit 0, Center 130 (75 ~ 186) 112
8214 23:47:32.815222 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8215 23:47:32.819188 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8216 23:47:32.822511 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8217 23:47:32.825755 iDelay=191, Bit 4, Center 128 (75 ~ 182) 108
8218 23:47:32.829263 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8219 23:47:32.835447 iDelay=191, Bit 6, Center 136 (83 ~ 190) 108
8220 23:47:32.838656 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8221 23:47:32.841875 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8222 23:47:32.845189 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8223 23:47:32.848908 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8224 23:47:32.855310 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8225 23:47:32.858333 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8226 23:47:32.861779 iDelay=191, Bit 13, Center 128 (71 ~ 186) 116
8227 23:47:32.865403 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8228 23:47:32.868808 iDelay=191, Bit 15, Center 132 (75 ~ 190) 116
8229 23:47:32.869262 ==
8230 23:47:32.872560 Dram Type= 6, Freq= 0, CH_0, rank 1
8231 23:47:32.879523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8232 23:47:32.879938 ==
8233 23:47:32.880265 DQS Delay:
8234 23:47:32.882505 DQS0 = 0, DQS1 = 0
8235 23:47:32.882918 DQM Delay:
8236 23:47:32.885517 DQM0 = 128, DQM1 = 122
8237 23:47:32.885934 DQ Delay:
8238 23:47:32.889070 DQ0 =130, DQ1 =130, DQ2 =124, DQ3 =126
8239 23:47:32.892890 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8240 23:47:32.895406 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8241 23:47:32.898831 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8242 23:47:32.899245
8243 23:47:32.899566
8244 23:47:32.899928
8245 23:47:32.902191 [DramC_TX_OE_Calibration] TA2
8246 23:47:32.905878 Original DQ_B0 (3 6) =30, OEN = 27
8247 23:47:32.909488 Original DQ_B1 (3 6) =30, OEN = 27
8248 23:47:32.912442 24, 0x0, End_B0=24 End_B1=24
8249 23:47:32.913169 25, 0x0, End_B0=25 End_B1=25
8250 23:47:32.915262 26, 0x0, End_B0=26 End_B1=26
8251 23:47:32.919074 27, 0x0, End_B0=27 End_B1=27
8252 23:47:32.922239 28, 0x0, End_B0=28 End_B1=28
8253 23:47:32.925464 29, 0x0, End_B0=29 End_B1=29
8254 23:47:32.925881 30, 0x0, End_B0=30 End_B1=30
8255 23:47:32.928964 31, 0x4141, End_B0=30 End_B1=30
8256 23:47:32.932126 Byte0 end_step=30 best_step=27
8257 23:47:32.935731 Byte1 end_step=30 best_step=27
8258 23:47:32.939217 Byte0 TX OE(2T, 0.5T) = (3, 3)
8259 23:47:32.942532 Byte1 TX OE(2T, 0.5T) = (3, 3)
8260 23:47:32.942987
8261 23:47:32.943318
8262 23:47:32.949263 [DQSOSCAuto] RK1, (LSB)MR18= 0x150a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 399 ps
8263 23:47:32.952163 CH0 RK1: MR19=303, MR18=150A
8264 23:47:32.958800 CH0_RK1: MR19=0x303, MR18=0x150A, DQSOSC=399, MR23=63, INC=23, DEC=15
8265 23:47:32.962158 [RxdqsGatingPostProcess] freq 1600
8266 23:47:32.965435 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8267 23:47:32.968734 best DQS0 dly(2T, 0.5T) = (1, 1)
8268 23:47:32.972149 best DQS1 dly(2T, 0.5T) = (1, 1)
8269 23:47:32.975997 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8270 23:47:32.978766 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8271 23:47:32.982615 best DQS0 dly(2T, 0.5T) = (1, 1)
8272 23:47:32.985566 best DQS1 dly(2T, 0.5T) = (1, 1)
8273 23:47:32.988715 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8274 23:47:32.992123 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8275 23:47:32.995615 Pre-setting of DQS Precalculation
8276 23:47:32.999080 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8277 23:47:32.999176 ==
8278 23:47:33.001847 Dram Type= 6, Freq= 0, CH_1, rank 0
8279 23:47:33.004968 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8280 23:47:33.005088 ==
8281 23:47:33.012119 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8282 23:47:33.015539 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8283 23:47:33.021872 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8284 23:47:33.025944 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8285 23:47:33.035255 [CA 0] Center 41 (13~70) winsize 58
8286 23:47:33.038576 [CA 1] Center 41 (13~70) winsize 58
8287 23:47:33.042749 [CA 2] Center 37 (9~66) winsize 58
8288 23:47:33.045775 [CA 3] Center 36 (7~66) winsize 60
8289 23:47:33.048695 [CA 4] Center 37 (8~66) winsize 59
8290 23:47:33.052242 [CA 5] Center 36 (7~66) winsize 60
8291 23:47:33.052755
8292 23:47:33.055397 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8293 23:47:33.055835
8294 23:47:33.059042 [CATrainingPosCal] consider 1 rank data
8295 23:47:33.062028 u2DelayCellTimex100 = 275/100 ps
8296 23:47:33.065610 CA0 delay=41 (13~70),Diff = 5 PI (17 cell)
8297 23:47:33.072065 CA1 delay=41 (13~70),Diff = 5 PI (17 cell)
8298 23:47:33.075101 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8299 23:47:33.078991 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8300 23:47:33.082225 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8301 23:47:33.085899 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8302 23:47:33.086307
8303 23:47:33.088853 CA PerBit enable=1, Macro0, CA PI delay=36
8304 23:47:33.089231
8305 23:47:33.091779 [CBTSetCACLKResult] CA Dly = 36
8306 23:47:33.092051 CS Dly: 9 (0~40)
8307 23:47:33.098313 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8308 23:47:33.101842 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8309 23:47:33.101920 ==
8310 23:47:33.105537 Dram Type= 6, Freq= 0, CH_1, rank 1
8311 23:47:33.108674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8312 23:47:33.108779 ==
8313 23:47:33.115194 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8314 23:47:33.118425 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8315 23:47:33.125152 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8316 23:47:33.128289 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8317 23:47:33.138746 [CA 0] Center 43 (14~72) winsize 59
8318 23:47:33.142341 [CA 1] Center 43 (14~72) winsize 59
8319 23:47:33.145033 [CA 2] Center 37 (8~67) winsize 60
8320 23:47:33.148942 [CA 3] Center 37 (8~67) winsize 60
8321 23:47:33.151894 [CA 4] Center 38 (9~68) winsize 60
8322 23:47:33.155016 [CA 5] Center 37 (8~66) winsize 59
8323 23:47:33.155422
8324 23:47:33.158566 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8325 23:47:33.159019
8326 23:47:33.162202 [CATrainingPosCal] consider 2 rank data
8327 23:47:33.165959 u2DelayCellTimex100 = 275/100 ps
8328 23:47:33.168496 CA0 delay=42 (14~70),Diff = 5 PI (17 cell)
8329 23:47:33.175450 CA1 delay=42 (14~70),Diff = 5 PI (17 cell)
8330 23:47:33.178423 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8331 23:47:33.182007 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8332 23:47:33.185453 CA4 delay=37 (9~66),Diff = 0 PI (0 cell)
8333 23:47:33.188675 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8334 23:47:33.189263
8335 23:47:33.191983 CA PerBit enable=1, Macro0, CA PI delay=37
8336 23:47:33.192455
8337 23:47:33.195354 [CBTSetCACLKResult] CA Dly = 37
8338 23:47:33.195811 CS Dly: 11 (0~44)
8339 23:47:33.202166 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8340 23:47:33.205542 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8341 23:47:33.205949
8342 23:47:33.208557 ----->DramcWriteLeveling(PI) begin...
8343 23:47:33.209011 ==
8344 23:47:33.212000 Dram Type= 6, Freq= 0, CH_1, rank 0
8345 23:47:33.215194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 23:47:33.215610 ==
8347 23:47:33.218596 Write leveling (Byte 0): 23 => 23
8348 23:47:33.221781 Write leveling (Byte 1): 28 => 28
8349 23:47:33.225766 DramcWriteLeveling(PI) end<-----
8350 23:47:33.226178
8351 23:47:33.226500 ==
8352 23:47:33.229083 Dram Type= 6, Freq= 0, CH_1, rank 0
8353 23:47:33.231930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8354 23:47:33.235734 ==
8355 23:47:33.236154 [Gating] SW mode calibration
8356 23:47:33.245465 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8357 23:47:33.248784 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8358 23:47:33.251954 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 23:47:33.259134 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 23:47:33.261830 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 23:47:33.265385 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 23:47:33.272081 1 4 16 | B1->B0 | 2b2b 2828 | 0 0 | (0 0) (0 0)
8363 23:47:33.275447 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8364 23:47:33.278813 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8365 23:47:33.285691 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8366 23:47:33.288476 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 23:47:33.292008 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 23:47:33.299088 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 23:47:33.301798 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8370 23:47:33.305794 1 5 16 | B1->B0 | 2e2e 3434 | 0 0 | (1 0) (0 0)
8371 23:47:33.312022 1 5 20 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
8372 23:47:33.315394 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8373 23:47:33.318622 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8374 23:47:33.325293 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8375 23:47:33.328938 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 23:47:33.332002 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 23:47:33.335168 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 23:47:33.341974 1 6 16 | B1->B0 | 4141 3535 | 0 0 | (0 0) (1 1)
8379 23:47:33.344943 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 23:47:33.351525 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8381 23:47:33.354910 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8382 23:47:33.358762 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 23:47:33.361473 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 23:47:33.368188 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 23:47:33.372005 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 23:47:33.375016 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8387 23:47:33.381328 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8388 23:47:33.384657 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 23:47:33.387995 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8390 23:47:33.395118 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8391 23:47:33.398373 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 23:47:33.401883 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 23:47:33.408699 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 23:47:33.411875 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 23:47:33.415438 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 23:47:33.421755 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 23:47:33.424923 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 23:47:33.428307 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 23:47:33.431976 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 23:47:33.439021 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 23:47:33.442091 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 23:47:33.445255 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8403 23:47:33.451896 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 23:47:33.455063 Total UI for P1: 0, mck2ui 16
8405 23:47:33.458408 best dqsien dly found for B0: ( 1, 9, 16)
8406 23:47:33.462035 Total UI for P1: 0, mck2ui 16
8407 23:47:33.465086 best dqsien dly found for B1: ( 1, 9, 16)
8408 23:47:33.468420 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8409 23:47:33.471699 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8410 23:47:33.472108
8411 23:47:33.475616 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8412 23:47:33.478561 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8413 23:47:33.482271 [Gating] SW calibration Done
8414 23:47:33.482709 ==
8415 23:47:33.485008 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 23:47:33.488496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 23:47:33.488908 ==
8418 23:47:33.492260 RX Vref Scan: 0
8419 23:47:33.492795
8420 23:47:33.493317 RX Vref 0 -> 0, step: 1
8421 23:47:33.493881
8422 23:47:33.495551 RX Delay 0 -> 252, step: 8
8423 23:47:33.498656 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8424 23:47:33.505157 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8425 23:47:33.508660 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8426 23:47:33.512143 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8427 23:47:33.515276 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8428 23:47:33.519108 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8429 23:47:33.522412 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8430 23:47:33.528574 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8431 23:47:33.532206 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8432 23:47:33.535198 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8433 23:47:33.538646 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8434 23:47:33.542071 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8435 23:47:33.549269 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8436 23:47:33.552194 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8437 23:47:33.555510 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8438 23:47:33.558445 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8439 23:47:33.559120 ==
8440 23:47:33.561613 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 23:47:33.568646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 23:47:33.568736 ==
8443 23:47:33.568804 DQS Delay:
8444 23:47:33.571835 DQS0 = 0, DQS1 = 0
8445 23:47:33.571920 DQM Delay:
8446 23:47:33.571988 DQM0 = 134, DQM1 = 126
8447 23:47:33.575059 DQ Delay:
8448 23:47:33.578523 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8449 23:47:33.581697 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8450 23:47:33.585296 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8451 23:47:33.588783 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8452 23:47:33.588862
8453 23:47:33.588925
8454 23:47:33.589037 ==
8455 23:47:33.592107 Dram Type= 6, Freq= 0, CH_1, rank 0
8456 23:47:33.595450 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8457 23:47:33.598961 ==
8458 23:47:33.599041
8459 23:47:33.599103
8460 23:47:33.599162 TX Vref Scan disable
8461 23:47:33.601906 == TX Byte 0 ==
8462 23:47:33.605296 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8463 23:47:33.608328 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8464 23:47:33.611852 == TX Byte 1 ==
8465 23:47:33.615191 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8466 23:47:33.618607 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8467 23:47:33.618691 ==
8468 23:47:33.621997 Dram Type= 6, Freq= 0, CH_1, rank 0
8469 23:47:33.628242 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8470 23:47:33.628326 ==
8471 23:47:33.641125
8472 23:47:33.643865 TX Vref early break, caculate TX vref
8473 23:47:33.646999 TX Vref=16, minBit 8, minWin=21, winSum=364
8474 23:47:33.651036 TX Vref=18, minBit 8, minWin=21, winSum=373
8475 23:47:33.653875 TX Vref=20, minBit 8, minWin=22, winSum=388
8476 23:47:33.657224 TX Vref=22, minBit 8, minWin=22, winSum=395
8477 23:47:33.660719 TX Vref=24, minBit 8, minWin=23, winSum=404
8478 23:47:33.667352 TX Vref=26, minBit 8, minWin=24, winSum=412
8479 23:47:33.670928 TX Vref=28, minBit 0, minWin=25, winSum=421
8480 23:47:33.673814 TX Vref=30, minBit 8, minWin=25, winSum=421
8481 23:47:33.676885 TX Vref=32, minBit 11, minWin=24, winSum=414
8482 23:47:33.680551 TX Vref=34, minBit 0, minWin=24, winSum=397
8483 23:47:33.687033 [TxChooseVref] Worse bit 0, Min win 25, Win sum 421, Final Vref 28
8484 23:47:33.687114
8485 23:47:33.690301 Final TX Range 0 Vref 28
8486 23:47:33.690381
8487 23:47:33.690444 ==
8488 23:47:33.693900 Dram Type= 6, Freq= 0, CH_1, rank 0
8489 23:47:33.697211 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8490 23:47:33.697299 ==
8491 23:47:33.697366
8492 23:47:33.697429
8493 23:47:33.700416 TX Vref Scan disable
8494 23:47:33.707288 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8495 23:47:33.707387 == TX Byte 0 ==
8496 23:47:33.710579 u2DelayCellOfst[0]=17 cells (5 PI)
8497 23:47:33.713905 u2DelayCellOfst[1]=14 cells (4 PI)
8498 23:47:33.717326 u2DelayCellOfst[2]=0 cells (0 PI)
8499 23:47:33.720938 u2DelayCellOfst[3]=7 cells (2 PI)
8500 23:47:33.724131 u2DelayCellOfst[4]=7 cells (2 PI)
8501 23:47:33.727525 u2DelayCellOfst[5]=17 cells (5 PI)
8502 23:47:33.727986 u2DelayCellOfst[6]=17 cells (5 PI)
8503 23:47:33.731295 u2DelayCellOfst[7]=3 cells (1 PI)
8504 23:47:33.738090 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8505 23:47:33.740727 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8506 23:47:33.741303 == TX Byte 1 ==
8507 23:47:33.744099 u2DelayCellOfst[8]=0 cells (0 PI)
8508 23:47:33.747452 u2DelayCellOfst[9]=7 cells (2 PI)
8509 23:47:33.751205 u2DelayCellOfst[10]=10 cells (3 PI)
8510 23:47:33.754113 u2DelayCellOfst[11]=7 cells (2 PI)
8511 23:47:33.757377 u2DelayCellOfst[12]=14 cells (4 PI)
8512 23:47:33.760705 u2DelayCellOfst[13]=17 cells (5 PI)
8513 23:47:33.764303 u2DelayCellOfst[14]=17 cells (5 PI)
8514 23:47:33.767645 u2DelayCellOfst[15]=17 cells (5 PI)
8515 23:47:33.770656 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8516 23:47:33.774516 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8517 23:47:33.777424 DramC Write-DBI on
8518 23:47:33.777829 ==
8519 23:47:33.780772 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 23:47:33.784311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 23:47:33.784764 ==
8522 23:47:33.785176
8523 23:47:33.785558
8524 23:47:33.787636 TX Vref Scan disable
8525 23:47:33.791433 == TX Byte 0 ==
8526 23:47:33.794550 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8527 23:47:33.797756 == TX Byte 1 ==
8528 23:47:33.800934 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8529 23:47:33.801420 DramC Write-DBI off
8530 23:47:33.801758
8531 23:47:33.804159 [DATLAT]
8532 23:47:33.804566 Freq=1600, CH1 RK0
8533 23:47:33.804938
8534 23:47:33.807674 DATLAT Default: 0xf
8535 23:47:33.808079 0, 0xFFFF, sum = 0
8536 23:47:33.810917 1, 0xFFFF, sum = 0
8537 23:47:33.811330 2, 0xFFFF, sum = 0
8538 23:47:33.814178 3, 0xFFFF, sum = 0
8539 23:47:33.814594 4, 0xFFFF, sum = 0
8540 23:47:33.817441 5, 0xFFFF, sum = 0
8541 23:47:33.817902 6, 0xFFFF, sum = 0
8542 23:47:33.820651 7, 0xFFFF, sum = 0
8543 23:47:33.821183 8, 0xFFFF, sum = 0
8544 23:47:33.824107 9, 0xFFFF, sum = 0
8545 23:47:33.827386 10, 0xFFFF, sum = 0
8546 23:47:33.827798 11, 0xFFFF, sum = 0
8547 23:47:33.830792 12, 0xFFFF, sum = 0
8548 23:47:33.831237 13, 0xFFFF, sum = 0
8549 23:47:33.834005 14, 0x0, sum = 1
8550 23:47:33.834438 15, 0x0, sum = 2
8551 23:47:33.837444 16, 0x0, sum = 3
8552 23:47:33.837861 17, 0x0, sum = 4
8553 23:47:33.838226 best_step = 15
8554 23:47:33.838571
8555 23:47:33.840795 ==
8556 23:47:33.844131 Dram Type= 6, Freq= 0, CH_1, rank 0
8557 23:47:33.847780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8558 23:47:33.848188 ==
8559 23:47:33.848508 RX Vref Scan: 1
8560 23:47:33.848809
8561 23:47:33.850785 Set Vref Range= 24 -> 127
8562 23:47:33.851190
8563 23:47:33.854225 RX Vref 24 -> 127, step: 1
8564 23:47:33.854629
8565 23:47:33.857419 RX Delay 11 -> 252, step: 4
8566 23:47:33.857829
8567 23:47:33.860903 Set Vref, RX VrefLevel [Byte0]: 24
8568 23:47:33.864201 [Byte1]: 24
8569 23:47:33.864610
8570 23:47:33.867878 Set Vref, RX VrefLevel [Byte0]: 25
8571 23:47:33.870680 [Byte1]: 25
8572 23:47:33.871088
8573 23:47:33.874611 Set Vref, RX VrefLevel [Byte0]: 26
8574 23:47:33.877949 [Byte1]: 26
8575 23:47:33.881106
8576 23:47:33.881514 Set Vref, RX VrefLevel [Byte0]: 27
8577 23:47:33.884077 [Byte1]: 27
8578 23:47:33.888572
8579 23:47:33.889002 Set Vref, RX VrefLevel [Byte0]: 28
8580 23:47:33.891688 [Byte1]: 28
8581 23:47:33.896003
8582 23:47:33.896428 Set Vref, RX VrefLevel [Byte0]: 29
8583 23:47:33.899858 [Byte1]: 29
8584 23:47:33.903979
8585 23:47:33.904491 Set Vref, RX VrefLevel [Byte0]: 30
8586 23:47:33.907256 [Byte1]: 30
8587 23:47:33.911211
8588 23:47:33.911712 Set Vref, RX VrefLevel [Byte0]: 31
8589 23:47:33.914546 [Byte1]: 31
8590 23:47:33.918977
8591 23:47:33.919394 Set Vref, RX VrefLevel [Byte0]: 32
8592 23:47:33.921995 [Byte1]: 32
8593 23:47:33.926678
8594 23:47:33.927099 Set Vref, RX VrefLevel [Byte0]: 33
8595 23:47:33.929835 [Byte1]: 33
8596 23:47:33.934305
8597 23:47:33.934813 Set Vref, RX VrefLevel [Byte0]: 34
8598 23:47:33.937511 [Byte1]: 34
8599 23:47:33.941900
8600 23:47:33.942408 Set Vref, RX VrefLevel [Byte0]: 35
8601 23:47:33.945347 [Byte1]: 35
8602 23:47:33.949705
8603 23:47:33.950213 Set Vref, RX VrefLevel [Byte0]: 36
8604 23:47:33.953129 [Byte1]: 36
8605 23:47:33.957319
8606 23:47:33.957822 Set Vref, RX VrefLevel [Byte0]: 37
8607 23:47:33.960750 [Byte1]: 37
8608 23:47:33.964810
8609 23:47:33.965361 Set Vref, RX VrefLevel [Byte0]: 38
8610 23:47:33.968047 [Byte1]: 38
8611 23:47:33.972447
8612 23:47:33.972959 Set Vref, RX VrefLevel [Byte0]: 39
8613 23:47:33.975478 [Byte1]: 39
8614 23:47:33.980004
8615 23:47:33.980554 Set Vref, RX VrefLevel [Byte0]: 40
8616 23:47:33.983006 [Byte1]: 40
8617 23:47:33.987404
8618 23:47:33.987811 Set Vref, RX VrefLevel [Byte0]: 41
8619 23:47:33.990871 [Byte1]: 41
8620 23:47:33.994852
8621 23:47:33.995256 Set Vref, RX VrefLevel [Byte0]: 42
8622 23:47:33.998588 [Byte1]: 42
8623 23:47:34.002838
8624 23:47:34.003341 Set Vref, RX VrefLevel [Byte0]: 43
8625 23:47:34.006239 [Byte1]: 43
8626 23:47:34.010263
8627 23:47:34.010670 Set Vref, RX VrefLevel [Byte0]: 44
8628 23:47:34.013540 [Byte1]: 44
8629 23:47:34.018085
8630 23:47:34.018591 Set Vref, RX VrefLevel [Byte0]: 45
8631 23:47:34.021238 [Byte1]: 45
8632 23:47:34.025503
8633 23:47:34.025910 Set Vref, RX VrefLevel [Byte0]: 46
8634 23:47:34.028602 [Byte1]: 46
8635 23:47:34.033133
8636 23:47:34.033647 Set Vref, RX VrefLevel [Byte0]: 47
8637 23:47:34.036497 [Byte1]: 47
8638 23:47:34.040890
8639 23:47:34.041441 Set Vref, RX VrefLevel [Byte0]: 48
8640 23:47:34.044570 [Byte1]: 48
8641 23:47:34.048965
8642 23:47:34.049561 Set Vref, RX VrefLevel [Byte0]: 49
8643 23:47:34.052178 [Byte1]: 49
8644 23:47:34.056542
8645 23:47:34.057151 Set Vref, RX VrefLevel [Byte0]: 50
8646 23:47:34.059629 [Byte1]: 50
8647 23:47:34.064297
8648 23:47:34.064859 Set Vref, RX VrefLevel [Byte0]: 51
8649 23:47:34.066510 [Byte1]: 51
8650 23:47:34.071659
8651 23:47:34.072247 Set Vref, RX VrefLevel [Byte0]: 52
8652 23:47:34.074343 [Byte1]: 52
8653 23:47:34.078642
8654 23:47:34.079136 Set Vref, RX VrefLevel [Byte0]: 53
8655 23:47:34.082061 [Byte1]: 53
8656 23:47:34.086882
8657 23:47:34.087449 Set Vref, RX VrefLevel [Byte0]: 54
8658 23:47:34.089485 [Byte1]: 54
8659 23:47:34.094021
8660 23:47:34.094516 Set Vref, RX VrefLevel [Byte0]: 55
8661 23:47:34.097352 [Byte1]: 55
8662 23:47:34.101563
8663 23:47:34.102019 Set Vref, RX VrefLevel [Byte0]: 56
8664 23:47:34.104789 [Byte1]: 56
8665 23:47:34.109159
8666 23:47:34.109708 Set Vref, RX VrefLevel [Byte0]: 57
8667 23:47:34.112925 [Byte1]: 57
8668 23:47:34.117398
8669 23:47:34.117964 Set Vref, RX VrefLevel [Byte0]: 58
8670 23:47:34.120200 [Byte1]: 58
8671 23:47:34.124166
8672 23:47:34.124625 Set Vref, RX VrefLevel [Byte0]: 59
8673 23:47:34.127793 [Byte1]: 59
8674 23:47:34.132117
8675 23:47:34.132679 Set Vref, RX VrefLevel [Byte0]: 60
8676 23:47:34.135268 [Byte1]: 60
8677 23:47:34.139809
8678 23:47:34.140353 Set Vref, RX VrefLevel [Byte0]: 61
8679 23:47:34.142991 [Byte1]: 61
8680 23:47:34.148004
8681 23:47:34.148550 Set Vref, RX VrefLevel [Byte0]: 62
8682 23:47:34.150882 [Byte1]: 62
8683 23:47:34.154541
8684 23:47:34.155010 Set Vref, RX VrefLevel [Byte0]: 63
8685 23:47:34.158435 [Byte1]: 63
8686 23:47:34.162487
8687 23:47:34.163034 Set Vref, RX VrefLevel [Byte0]: 64
8688 23:47:34.165962 [Byte1]: 64
8689 23:47:34.170355
8690 23:47:34.170812 Set Vref, RX VrefLevel [Byte0]: 65
8691 23:47:34.173157 [Byte1]: 65
8692 23:47:34.178016
8693 23:47:34.178570 Set Vref, RX VrefLevel [Byte0]: 66
8694 23:47:34.181107 [Byte1]: 66
8695 23:47:34.185953
8696 23:47:34.186503 Set Vref, RX VrefLevel [Byte0]: 67
8697 23:47:34.188826 [Byte1]: 67
8698 23:47:34.192788
8699 23:47:34.193380 Set Vref, RX VrefLevel [Byte0]: 68
8700 23:47:34.196220 [Byte1]: 68
8701 23:47:34.200687
8702 23:47:34.201177 Set Vref, RX VrefLevel [Byte0]: 69
8703 23:47:34.204388 [Byte1]: 69
8704 23:47:34.208566
8705 23:47:34.209192 Set Vref, RX VrefLevel [Byte0]: 70
8706 23:47:34.211212 [Byte1]: 70
8707 23:47:34.216406
8708 23:47:34.216960 Set Vref, RX VrefLevel [Byte0]: 71
8709 23:47:34.218765 [Byte1]: 71
8710 23:47:34.223817
8711 23:47:34.224274 Set Vref, RX VrefLevel [Byte0]: 72
8712 23:47:34.226931 [Byte1]: 72
8713 23:47:34.230867
8714 23:47:34.231470 Set Vref, RX VrefLevel [Byte0]: 73
8715 23:47:34.234145 [Byte1]: 73
8716 23:47:34.239109
8717 23:47:34.239667 Set Vref, RX VrefLevel [Byte0]: 74
8718 23:47:34.242111 [Byte1]: 74
8719 23:47:34.246066
8720 23:47:34.246516 Final RX Vref Byte 0 = 60 to rank0
8721 23:47:34.249467 Final RX Vref Byte 1 = 59 to rank0
8722 23:47:34.252878 Final RX Vref Byte 0 = 60 to rank1
8723 23:47:34.256594 Final RX Vref Byte 1 = 59 to rank1==
8724 23:47:34.259772 Dram Type= 6, Freq= 0, CH_1, rank 0
8725 23:47:34.263094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 23:47:34.266373 ==
8727 23:47:34.266821 DQS Delay:
8728 23:47:34.267175 DQS0 = 0, DQS1 = 0
8729 23:47:34.269904 DQM Delay:
8730 23:47:34.270354 DQM0 = 131, DQM1 = 124
8731 23:47:34.273302 DQ Delay:
8732 23:47:34.276251 DQ0 =134, DQ1 =126, DQ2 =120, DQ3 =130
8733 23:47:34.279982 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8734 23:47:34.283145 DQ8 =112, DQ9 =114, DQ10 =126, DQ11 =118
8735 23:47:34.286238 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8736 23:47:34.286645
8737 23:47:34.286968
8738 23:47:34.287266
8739 23:47:34.290168 [DramC_TX_OE_Calibration] TA2
8740 23:47:34.293382 Original DQ_B0 (3 6) =30, OEN = 27
8741 23:47:34.296719 Original DQ_B1 (3 6) =30, OEN = 27
8742 23:47:34.299660 24, 0x0, End_B0=24 End_B1=24
8743 23:47:34.300074 25, 0x0, End_B0=25 End_B1=25
8744 23:47:34.303132 26, 0x0, End_B0=26 End_B1=26
8745 23:47:34.306137 27, 0x0, End_B0=27 End_B1=27
8746 23:47:34.309447 28, 0x0, End_B0=28 End_B1=28
8747 23:47:34.310000 29, 0x0, End_B0=29 End_B1=29
8748 23:47:34.313245 30, 0x0, End_B0=30 End_B1=30
8749 23:47:34.316383 31, 0x4141, End_B0=30 End_B1=30
8750 23:47:34.319391 Byte0 end_step=30 best_step=27
8751 23:47:34.322866 Byte1 end_step=30 best_step=27
8752 23:47:34.326154 Byte0 TX OE(2T, 0.5T) = (3, 3)
8753 23:47:34.326564 Byte1 TX OE(2T, 0.5T) = (3, 3)
8754 23:47:34.326891
8755 23:47:34.329718
8756 23:47:34.336021 [DQSOSCAuto] RK0, (LSB)MR18= 0x1601, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
8757 23:47:34.339929 CH1 RK0: MR19=303, MR18=1601
8758 23:47:34.346741 CH1_RK0: MR19=0x303, MR18=0x1601, DQSOSC=398, MR23=63, INC=23, DEC=15
8759 23:47:34.347232
8760 23:47:34.349586 ----->DramcWriteLeveling(PI) begin...
8761 23:47:34.350000 ==
8762 23:47:34.352740 Dram Type= 6, Freq= 0, CH_1, rank 1
8763 23:47:34.356502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8764 23:47:34.357049 ==
8765 23:47:34.359439 Write leveling (Byte 0): 25 => 25
8766 23:47:34.362658 Write leveling (Byte 1): 26 => 26
8767 23:47:34.366815 DramcWriteLeveling(PI) end<-----
8768 23:47:34.367229
8769 23:47:34.367752 ==
8770 23:47:34.369607 Dram Type= 6, Freq= 0, CH_1, rank 1
8771 23:47:34.373128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8772 23:47:34.373651 ==
8773 23:47:34.376536 [Gating] SW mode calibration
8774 23:47:34.383038 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8775 23:47:34.389361 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8776 23:47:34.393335 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8777 23:47:34.396425 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 23:47:34.402855 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8779 23:47:34.406984 1 4 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
8780 23:47:34.409949 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8781 23:47:34.413020 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 23:47:34.419701 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 23:47:34.423599 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 23:47:34.426445 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 23:47:34.433056 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 23:47:34.436300 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
8787 23:47:34.440067 1 5 12 | B1->B0 | 3232 2424 | 1 0 | (1 0) (0 0)
8788 23:47:34.447467 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 23:47:34.449617 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8790 23:47:34.453271 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 23:47:34.459664 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 23:47:34.463198 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 23:47:34.466625 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 23:47:34.473151 1 6 8 | B1->B0 | 2424 3737 | 0 0 | (0 0) (0 0)
8795 23:47:34.477095 1 6 12 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8796 23:47:34.479836 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8797 23:47:34.486784 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 23:47:34.489655 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 23:47:34.493192 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 23:47:34.496804 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 23:47:34.503836 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 23:47:34.506820 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8803 23:47:34.510003 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8804 23:47:34.516773 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8805 23:47:34.520086 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 23:47:34.523419 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 23:47:34.529720 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 23:47:34.533753 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 23:47:34.536842 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 23:47:34.543631 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 23:47:34.546657 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 23:47:34.550413 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 23:47:34.556738 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 23:47:34.560022 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 23:47:34.563505 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 23:47:34.570306 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 23:47:34.573098 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 23:47:34.576766 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8819 23:47:34.580355 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8820 23:47:34.586348 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8821 23:47:34.590779 Total UI for P1: 0, mck2ui 16
8822 23:47:34.593386 best dqsien dly found for B0: ( 1, 9, 10)
8823 23:47:34.596816 Total UI for P1: 0, mck2ui 16
8824 23:47:34.599874 best dqsien dly found for B1: ( 1, 9, 12)
8825 23:47:34.603955 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8826 23:47:34.606763 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8827 23:47:34.607316
8828 23:47:34.610027 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8829 23:47:34.613489 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8830 23:47:34.617017 [Gating] SW calibration Done
8831 23:47:34.617596 ==
8832 23:47:34.620213 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 23:47:34.623261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 23:47:34.623809 ==
8835 23:47:34.627284 RX Vref Scan: 0
8836 23:47:34.627832
8837 23:47:34.628200 RX Vref 0 -> 0, step: 1
8838 23:47:34.630641
8839 23:47:34.631183 RX Delay 0 -> 252, step: 8
8840 23:47:34.633151 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8841 23:47:34.640376 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8842 23:47:34.643858 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8843 23:47:34.646545 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8844 23:47:34.650152 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8845 23:47:34.653663 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8846 23:47:34.659893 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8847 23:47:34.663335 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8848 23:47:34.666666 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8849 23:47:34.670277 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8850 23:47:34.673089 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8851 23:47:34.679935 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8852 23:47:34.683230 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8853 23:47:34.686473 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8854 23:47:34.690173 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8855 23:47:34.697217 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8856 23:47:34.697770 ==
8857 23:47:34.700081 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 23:47:34.703995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 23:47:34.704547 ==
8860 23:47:34.704918 DQS Delay:
8861 23:47:34.707082 DQS0 = 0, DQS1 = 0
8862 23:47:34.707656 DQM Delay:
8863 23:47:34.709830 DQM0 = 132, DQM1 = 129
8864 23:47:34.710278 DQ Delay:
8865 23:47:34.713350 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8866 23:47:34.716852 DQ4 =131, DQ5 =147, DQ6 =139, DQ7 =127
8867 23:47:34.720774 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8868 23:47:34.723329 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8869 23:47:34.723780
8870 23:47:34.724136
8871 23:47:34.724468 ==
8872 23:47:34.726952 Dram Type= 6, Freq= 0, CH_1, rank 1
8873 23:47:34.733250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8874 23:47:34.733802 ==
8875 23:47:34.734159
8876 23:47:34.734490
8877 23:47:34.734806 TX Vref Scan disable
8878 23:47:34.737045 == TX Byte 0 ==
8879 23:47:34.740282 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8880 23:47:34.747109 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8881 23:47:34.747654 == TX Byte 1 ==
8882 23:47:34.750252 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8883 23:47:34.753777 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8884 23:47:34.757583 ==
8885 23:47:34.760540 Dram Type= 6, Freq= 0, CH_1, rank 1
8886 23:47:34.763618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8887 23:47:34.764217 ==
8888 23:47:34.777116
8889 23:47:34.779996 TX Vref early break, caculate TX vref
8890 23:47:34.783143 TX Vref=16, minBit 8, minWin=22, winSum=378
8891 23:47:34.787256 TX Vref=18, minBit 0, minWin=24, winSum=392
8892 23:47:34.789801 TX Vref=20, minBit 1, minWin=24, winSum=397
8893 23:47:34.793208 TX Vref=22, minBit 8, minWin=24, winSum=406
8894 23:47:34.796373 TX Vref=24, minBit 0, minWin=25, winSum=416
8895 23:47:34.803239 TX Vref=26, minBit 0, minWin=25, winSum=424
8896 23:47:34.807172 TX Vref=28, minBit 1, minWin=26, winSum=427
8897 23:47:34.810161 TX Vref=30, minBit 0, minWin=25, winSum=424
8898 23:47:34.814544 TX Vref=32, minBit 0, minWin=25, winSum=421
8899 23:47:34.817359 TX Vref=34, minBit 0, minWin=25, winSum=409
8900 23:47:34.820046 TX Vref=36, minBit 5, minWin=24, winSum=404
8901 23:47:34.826974 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 28
8902 23:47:34.827543
8903 23:47:34.830159 Final TX Range 0 Vref 28
8904 23:47:34.830609
8905 23:47:34.830961 ==
8906 23:47:34.833578 Dram Type= 6, Freq= 0, CH_1, rank 1
8907 23:47:34.836548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8908 23:47:34.837142 ==
8909 23:47:34.837511
8910 23:47:34.837843
8911 23:47:34.840092 TX Vref Scan disable
8912 23:47:34.846823 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8913 23:47:34.847375 == TX Byte 0 ==
8914 23:47:34.850180 u2DelayCellOfst[0]=17 cells (5 PI)
8915 23:47:34.853256 u2DelayCellOfst[1]=10 cells (3 PI)
8916 23:47:34.856871 u2DelayCellOfst[2]=0 cells (0 PI)
8917 23:47:34.860308 u2DelayCellOfst[3]=7 cells (2 PI)
8918 23:47:34.863210 u2DelayCellOfst[4]=10 cells (3 PI)
8919 23:47:34.866651 u2DelayCellOfst[5]=21 cells (6 PI)
8920 23:47:34.870016 u2DelayCellOfst[6]=17 cells (5 PI)
8921 23:47:34.872917 u2DelayCellOfst[7]=7 cells (2 PI)
8922 23:47:34.876802 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8923 23:47:34.880397 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8924 23:47:34.883029 == TX Byte 1 ==
8925 23:47:34.883478 u2DelayCellOfst[8]=0 cells (0 PI)
8926 23:47:34.886753 u2DelayCellOfst[9]=3 cells (1 PI)
8927 23:47:34.889926 u2DelayCellOfst[10]=10 cells (3 PI)
8928 23:47:34.893410 u2DelayCellOfst[11]=7 cells (2 PI)
8929 23:47:34.896775 u2DelayCellOfst[12]=14 cells (4 PI)
8930 23:47:34.899731 u2DelayCellOfst[13]=17 cells (5 PI)
8931 23:47:34.903805 u2DelayCellOfst[14]=17 cells (5 PI)
8932 23:47:34.906711 u2DelayCellOfst[15]=14 cells (4 PI)
8933 23:47:34.909906 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8934 23:47:34.916702 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8935 23:47:34.917313 DramC Write-DBI on
8936 23:47:34.917686 ==
8937 23:47:34.919724 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 23:47:34.926143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 23:47:34.926710 ==
8940 23:47:34.927082
8941 23:47:34.927414
8942 23:47:34.927735 TX Vref Scan disable
8943 23:47:34.929690 == TX Byte 0 ==
8944 23:47:34.933157 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8945 23:47:34.936819 == TX Byte 1 ==
8946 23:47:34.940490 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8947 23:47:34.943710 DramC Write-DBI off
8948 23:47:34.944254
8949 23:47:34.944609 [DATLAT]
8950 23:47:34.944940 Freq=1600, CH1 RK1
8951 23:47:34.945353
8952 23:47:34.947183 DATLAT Default: 0xf
8953 23:47:34.947738 0, 0xFFFF, sum = 0
8954 23:47:34.950159 1, 0xFFFF, sum = 0
8955 23:47:34.950623 2, 0xFFFF, sum = 0
8956 23:47:34.953430 3, 0xFFFF, sum = 0
8957 23:47:34.953892 4, 0xFFFF, sum = 0
8958 23:47:34.957044 5, 0xFFFF, sum = 0
8959 23:47:34.957612 6, 0xFFFF, sum = 0
8960 23:47:34.959949 7, 0xFFFF, sum = 0
8961 23:47:34.963715 8, 0xFFFF, sum = 0
8962 23:47:34.964275 9, 0xFFFF, sum = 0
8963 23:47:34.966907 10, 0xFFFF, sum = 0
8964 23:47:34.967461 11, 0xFFFF, sum = 0
8965 23:47:34.970117 12, 0xFFFF, sum = 0
8966 23:47:34.970579 13, 0xFFFF, sum = 0
8967 23:47:34.973538 14, 0x0, sum = 1
8968 23:47:34.974130 15, 0x0, sum = 2
8969 23:47:34.977369 16, 0x0, sum = 3
8970 23:47:34.977924 17, 0x0, sum = 4
8971 23:47:34.980123 best_step = 15
8972 23:47:34.980603
8973 23:47:34.980961 ==
8974 23:47:34.983575 Dram Type= 6, Freq= 0, CH_1, rank 1
8975 23:47:34.987121 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8976 23:47:34.987671 ==
8977 23:47:34.988035 RX Vref Scan: 0
8978 23:47:34.988372
8979 23:47:34.990330 RX Vref 0 -> 0, step: 1
8980 23:47:34.990879
8981 23:47:34.994076 RX Delay 11 -> 252, step: 4
8982 23:47:34.996462 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8983 23:47:35.000358 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8984 23:47:35.006647 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
8985 23:47:35.010072 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8986 23:47:35.013227 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
8987 23:47:35.017531 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
8988 23:47:35.020502 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8989 23:47:35.026637 iDelay=191, Bit 7, Center 124 (71 ~ 178) 108
8990 23:47:35.030050 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
8991 23:47:35.033475 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8992 23:47:35.036642 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8993 23:47:35.039813 iDelay=191, Bit 11, Center 118 (63 ~ 174) 112
8994 23:47:35.046824 iDelay=191, Bit 12, Center 132 (79 ~ 186) 108
8995 23:47:35.050159 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8996 23:47:35.053123 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8997 23:47:35.057406 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
8998 23:47:35.057955 ==
8999 23:47:35.060243 Dram Type= 6, Freq= 0, CH_1, rank 1
9000 23:47:35.066843 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9001 23:47:35.067391 ==
9002 23:47:35.067761 DQS Delay:
9003 23:47:35.070190 DQS0 = 0, DQS1 = 0
9004 23:47:35.070650 DQM Delay:
9005 23:47:35.071016 DQM0 = 129, DQM1 = 126
9006 23:47:35.073081 DQ Delay:
9007 23:47:35.076483 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9008 23:47:35.080363 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =124
9009 23:47:35.083285 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9010 23:47:35.086522 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =136
9011 23:47:35.086985
9012 23:47:35.087348
9013 23:47:35.087685
9014 23:47:35.090712 [DramC_TX_OE_Calibration] TA2
9015 23:47:35.093773 Original DQ_B0 (3 6) =30, OEN = 27
9016 23:47:35.096958 Original DQ_B1 (3 6) =30, OEN = 27
9017 23:47:35.100196 24, 0x0, End_B0=24 End_B1=24
9018 23:47:35.100753 25, 0x0, End_B0=25 End_B1=25
9019 23:47:35.103727 26, 0x0, End_B0=26 End_B1=26
9020 23:47:35.107007 27, 0x0, End_B0=27 End_B1=27
9021 23:47:35.109917 28, 0x0, End_B0=28 End_B1=28
9022 23:47:35.110476 29, 0x0, End_B0=29 End_B1=29
9023 23:47:35.113636 30, 0x0, End_B0=30 End_B1=30
9024 23:47:35.116869 31, 0x5151, End_B0=30 End_B1=30
9025 23:47:35.119827 Byte0 end_step=30 best_step=27
9026 23:47:35.123282 Byte1 end_step=30 best_step=27
9027 23:47:35.126811 Byte0 TX OE(2T, 0.5T) = (3, 3)
9028 23:47:35.127270 Byte1 TX OE(2T, 0.5T) = (3, 3)
9029 23:47:35.127634
9030 23:47:35.129804
9031 23:47:35.136591 [DQSOSCAuto] RK1, (LSB)MR18= 0xf15, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9032 23:47:35.140749 CH1 RK1: MR19=303, MR18=F15
9033 23:47:35.146806 CH1_RK1: MR19=0x303, MR18=0xF15, DQSOSC=399, MR23=63, INC=23, DEC=15
9034 23:47:35.147379 [RxdqsGatingPostProcess] freq 1600
9035 23:47:35.153332 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9036 23:47:35.156694 best DQS0 dly(2T, 0.5T) = (1, 1)
9037 23:47:35.160132 best DQS1 dly(2T, 0.5T) = (1, 1)
9038 23:47:35.162987 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9039 23:47:35.166892 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9040 23:47:35.169689 best DQS0 dly(2T, 0.5T) = (1, 1)
9041 23:47:35.173319 best DQS1 dly(2T, 0.5T) = (1, 1)
9042 23:47:35.176780 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9043 23:47:35.180017 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9044 23:47:35.180570 Pre-setting of DQS Precalculation
9045 23:47:35.186831 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9046 23:47:35.193606 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9047 23:47:35.200165 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9048 23:47:35.200702
9049 23:47:35.201091
9050 23:47:35.203162 [Calibration Summary] 3200 Mbps
9051 23:47:35.206178 CH 0, Rank 0
9052 23:47:35.206632 SW Impedance : PASS
9053 23:47:35.209910 DUTY Scan : NO K
9054 23:47:35.213655 ZQ Calibration : PASS
9055 23:47:35.214196 Jitter Meter : NO K
9056 23:47:35.216924 CBT Training : PASS
9057 23:47:35.217523 Write leveling : PASS
9058 23:47:35.219965 RX DQS gating : PASS
9059 23:47:35.223742 RX DQ/DQS(RDDQC) : PASS
9060 23:47:35.224359 TX DQ/DQS : PASS
9061 23:47:35.226473 RX DATLAT : PASS
9062 23:47:35.230010 RX DQ/DQS(Engine): PASS
9063 23:47:35.230467 TX OE : PASS
9064 23:47:35.232970 All Pass.
9065 23:47:35.233460
9066 23:47:35.233820 CH 0, Rank 1
9067 23:47:35.236835 SW Impedance : PASS
9068 23:47:35.237400 DUTY Scan : NO K
9069 23:47:35.239877 ZQ Calibration : PASS
9070 23:47:35.243534 Jitter Meter : NO K
9071 23:47:35.244146 CBT Training : PASS
9072 23:47:35.246748 Write leveling : PASS
9073 23:47:35.249823 RX DQS gating : PASS
9074 23:47:35.250287 RX DQ/DQS(RDDQC) : PASS
9075 23:47:35.253658 TX DQ/DQS : PASS
9076 23:47:35.254213 RX DATLAT : PASS
9077 23:47:35.256599 RX DQ/DQS(Engine): PASS
9078 23:47:35.260442 TX OE : PASS
9079 23:47:35.260898 All Pass.
9080 23:47:35.261364
9081 23:47:35.261706 CH 1, Rank 0
9082 23:47:35.263120 SW Impedance : PASS
9083 23:47:35.266790 DUTY Scan : NO K
9084 23:47:35.267340 ZQ Calibration : PASS
9085 23:47:35.270634 Jitter Meter : NO K
9086 23:47:35.273171 CBT Training : PASS
9087 23:47:35.273629 Write leveling : PASS
9088 23:47:35.276771 RX DQS gating : PASS
9089 23:47:35.279732 RX DQ/DQS(RDDQC) : PASS
9090 23:47:35.280193 TX DQ/DQS : PASS
9091 23:47:35.282922 RX DATLAT : PASS
9092 23:47:35.286670 RX DQ/DQS(Engine): PASS
9093 23:47:35.287124 TX OE : PASS
9094 23:47:35.290256 All Pass.
9095 23:47:35.290807
9096 23:47:35.291173 CH 1, Rank 1
9097 23:47:35.293498 SW Impedance : PASS
9098 23:47:35.294115 DUTY Scan : NO K
9099 23:47:35.296953 ZQ Calibration : PASS
9100 23:47:35.300445 Jitter Meter : NO K
9101 23:47:35.301025 CBT Training : PASS
9102 23:47:35.303662 Write leveling : PASS
9103 23:47:35.304116 RX DQS gating : PASS
9104 23:47:35.306398 RX DQ/DQS(RDDQC) : PASS
9105 23:47:35.310218 TX DQ/DQS : PASS
9106 23:47:35.310775 RX DATLAT : PASS
9107 23:47:35.313571 RX DQ/DQS(Engine): PASS
9108 23:47:35.316676 TX OE : PASS
9109 23:47:35.317279 All Pass.
9110 23:47:35.317650
9111 23:47:35.317984 DramC Write-DBI on
9112 23:47:35.320423 PER_BANK_REFRESH: Hybrid Mode
9113 23:47:35.323240 TX_TRACKING: ON
9114 23:47:35.329826 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9115 23:47:35.340347 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9116 23:47:35.346515 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9117 23:47:35.350050 [FAST_K] Save calibration result to emmc
9118 23:47:35.353436 sync common calibartion params.
9119 23:47:35.356838 sync cbt_mode0:1, 1:1
9120 23:47:35.357443 dram_init: ddr_geometry: 2
9121 23:47:35.359960 dram_init: ddr_geometry: 2
9122 23:47:35.363293 dram_init: ddr_geometry: 2
9123 23:47:35.363748 0:dram_rank_size:100000000
9124 23:47:35.366605 1:dram_rank_size:100000000
9125 23:47:35.372953 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9126 23:47:35.376348 DFS_SHUFFLE_HW_MODE: ON
9127 23:47:35.379890 dramc_set_vcore_voltage set vcore to 725000
9128 23:47:35.380436 Read voltage for 1600, 0
9129 23:47:35.382926 Vio18 = 0
9130 23:47:35.383381 Vcore = 725000
9131 23:47:35.383739 Vdram = 0
9132 23:47:35.386399 Vddq = 0
9133 23:47:35.386852 Vmddr = 0
9134 23:47:35.390280 switch to 3200 Mbps bootup
9135 23:47:35.390826 [DramcRunTimeConfig]
9136 23:47:35.391193 PHYPLL
9137 23:47:35.393201 DPM_CONTROL_AFTERK: ON
9138 23:47:35.396516 PER_BANK_REFRESH: ON
9139 23:47:35.397116 REFRESH_OVERHEAD_REDUCTION: ON
9140 23:47:35.400256 CMD_PICG_NEW_MODE: OFF
9141 23:47:35.403663 XRTWTW_NEW_MODE: ON
9142 23:47:35.404117 XRTRTR_NEW_MODE: ON
9143 23:47:35.406386 TX_TRACKING: ON
9144 23:47:35.406939 RDSEL_TRACKING: OFF
9145 23:47:35.409706 DQS Precalculation for DVFS: ON
9146 23:47:35.410181 RX_TRACKING: OFF
9147 23:47:35.413421 HW_GATING DBG: ON
9148 23:47:35.413872 ZQCS_ENABLE_LP4: ON
9149 23:47:35.416521 RX_PICG_NEW_MODE: ON
9150 23:47:35.419893 TX_PICG_NEW_MODE: ON
9151 23:47:35.420350 ENABLE_RX_DCM_DPHY: ON
9152 23:47:35.423155 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9153 23:47:35.426438 DUMMY_READ_FOR_TRACKING: OFF
9154 23:47:35.430021 !!! SPM_CONTROL_AFTERK: OFF
9155 23:47:35.430507 !!! SPM could not control APHY
9156 23:47:35.433338 IMPEDANCE_TRACKING: ON
9157 23:47:35.436369 TEMP_SENSOR: ON
9158 23:47:35.436784 HW_SAVE_FOR_SR: OFF
9159 23:47:35.439457 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9160 23:47:35.443582 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9161 23:47:35.446962 Read ODT Tracking: ON
9162 23:47:35.447471 Refresh Rate DeBounce: ON
9163 23:47:35.449920 DFS_NO_QUEUE_FLUSH: ON
9164 23:47:35.453352 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9165 23:47:35.456325 ENABLE_DFS_RUNTIME_MRW: OFF
9166 23:47:35.456852 DDR_RESERVE_NEW_MODE: ON
9167 23:47:35.459674 MR_CBT_SWITCH_FREQ: ON
9168 23:47:35.463349 =========================
9169 23:47:35.481219 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9170 23:47:35.484581 dram_init: ddr_geometry: 2
9171 23:47:35.502701 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9172 23:47:35.505968 dram_init: dram init end (result: 0)
9173 23:47:35.512630 DRAM-K: Full calibration passed in 24577 msecs
9174 23:47:35.515951 MRC: failed to locate region type 0.
9175 23:47:35.516735 DRAM rank0 size:0x100000000,
9176 23:47:35.519361 DRAM rank1 size=0x100000000
9177 23:47:35.529064 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9178 23:47:35.536160 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9179 23:47:35.542427 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9180 23:47:35.548950 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9181 23:47:35.552752 DRAM rank0 size:0x100000000,
9182 23:47:35.556390 DRAM rank1 size=0x100000000
9183 23:47:35.556804 CBMEM:
9184 23:47:35.559182 IMD: root @ 0xfffff000 254 entries.
9185 23:47:35.562892 IMD: root @ 0xffffec00 62 entries.
9186 23:47:35.566171 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9187 23:47:35.569381 WARNING: RO_VPD is uninitialized or empty.
9188 23:47:35.575836 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9189 23:47:35.583254 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9190 23:47:35.595401 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9191 23:47:35.606573 BS: romstage times (exec / console): total (unknown) / 24077 ms
9192 23:47:35.607113
9193 23:47:35.607472
9194 23:47:35.617397 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9195 23:47:35.619909 ARM64: Exception handlers installed.
9196 23:47:35.623693 ARM64: Testing exception
9197 23:47:35.626673 ARM64: Done test exception
9198 23:47:35.627127 Enumerating buses...
9199 23:47:35.629852 Show all devs... Before device enumeration.
9200 23:47:35.633641 Root Device: enabled 1
9201 23:47:35.637131 CPU_CLUSTER: 0: enabled 1
9202 23:47:35.637587 CPU: 00: enabled 1
9203 23:47:35.640174 Compare with tree...
9204 23:47:35.640717 Root Device: enabled 1
9205 23:47:35.643843 CPU_CLUSTER: 0: enabled 1
9206 23:47:35.647070 CPU: 00: enabled 1
9207 23:47:35.647615 Root Device scanning...
9208 23:47:35.650255 scan_static_bus for Root Device
9209 23:47:35.653351 CPU_CLUSTER: 0 enabled
9210 23:47:35.656680 scan_static_bus for Root Device done
9211 23:47:35.660333 scan_bus: bus Root Device finished in 8 msecs
9212 23:47:35.660787 done
9213 23:47:35.667207 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9214 23:47:35.671141 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9215 23:47:35.677049 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9216 23:47:35.680637 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9217 23:47:35.683563 Allocating resources...
9218 23:47:35.684011 Reading resources...
9219 23:47:35.690101 Root Device read_resources bus 0 link: 0
9220 23:47:35.690576 DRAM rank0 size:0x100000000,
9221 23:47:35.693591 DRAM rank1 size=0x100000000
9222 23:47:35.697209 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9223 23:47:35.700229 CPU: 00 missing read_resources
9224 23:47:35.703669 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9225 23:47:35.710489 Root Device read_resources bus 0 link: 0 done
9226 23:47:35.711044 Done reading resources.
9227 23:47:35.716678 Show resources in subtree (Root Device)...After reading.
9228 23:47:35.720175 Root Device child on link 0 CPU_CLUSTER: 0
9229 23:47:35.723754 CPU_CLUSTER: 0 child on link 0 CPU: 00
9230 23:47:35.733231 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9231 23:47:35.733767 CPU: 00
9232 23:47:35.736942 Root Device assign_resources, bus 0 link: 0
9233 23:47:35.740100 CPU_CLUSTER: 0 missing set_resources
9234 23:47:35.743444 Root Device assign_resources, bus 0 link: 0 done
9235 23:47:35.746776 Done setting resources.
9236 23:47:35.753213 Show resources in subtree (Root Device)...After assigning values.
9237 23:47:35.756717 Root Device child on link 0 CPU_CLUSTER: 0
9238 23:47:35.760262 CPU_CLUSTER: 0 child on link 0 CPU: 00
9239 23:47:35.770239 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9240 23:47:35.770778 CPU: 00
9241 23:47:35.773669 Done allocating resources.
9242 23:47:35.777410 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9243 23:47:35.780028 Enabling resources...
9244 23:47:35.780491 done.
9245 23:47:35.784128 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9246 23:47:35.786524 Initializing devices...
9247 23:47:35.789977 Root Device init
9248 23:47:35.790533 init hardware done!
9249 23:47:35.793930 0x00000018: ctrlr->caps
9250 23:47:35.794491 52.000 MHz: ctrlr->f_max
9251 23:47:35.796616 0.400 MHz: ctrlr->f_min
9252 23:47:35.800054 0x40ff8080: ctrlr->voltages
9253 23:47:35.800613 sclk: 390625
9254 23:47:35.804142 Bus Width = 1
9255 23:47:35.804699 sclk: 390625
9256 23:47:35.805112 Bus Width = 1
9257 23:47:35.806986 Early init status = 3
9258 23:47:35.809895 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9259 23:47:35.815017 in-header: 03 fc 00 00 01 00 00 00
9260 23:47:35.818175 in-data: 00
9261 23:47:35.822247 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9262 23:47:35.827605 in-header: 03 fd 00 00 00 00 00 00
9263 23:47:35.830672 in-data:
9264 23:47:35.833865 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9265 23:47:35.838279 in-header: 03 fc 00 00 01 00 00 00
9266 23:47:35.841661 in-data: 00
9267 23:47:35.845273 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9268 23:47:35.850655 in-header: 03 fd 00 00 00 00 00 00
9269 23:47:35.853925 in-data:
9270 23:47:35.857246 [SSUSB] Setting up USB HOST controller...
9271 23:47:35.860794 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9272 23:47:35.864255 [SSUSB] phy power-on done.
9273 23:47:35.867436 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9274 23:47:35.873740 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9275 23:47:35.877272 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9276 23:47:35.883411 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9277 23:47:35.890430 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9278 23:47:35.897363 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9279 23:47:35.903986 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9280 23:47:35.910284 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9281 23:47:35.910696 SPM: binary array size = 0x9dc
9282 23:47:35.916861 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9283 23:47:35.923458 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9284 23:47:35.930542 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9285 23:47:35.933957 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9286 23:47:35.937300 configure_display: Starting display init
9287 23:47:35.973672 anx7625_power_on_init: Init interface.
9288 23:47:35.976880 anx7625_disable_pd_protocol: Disabled PD feature.
9289 23:47:35.980866 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9290 23:47:36.008095 anx7625_start_dp_work: Secure OCM version=00
9291 23:47:36.011499 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9292 23:47:36.026048 sp_tx_get_edid_block: EDID Block = 1
9293 23:47:36.129052 Extracted contents:
9294 23:47:36.132038 header: 00 ff ff ff ff ff ff 00
9295 23:47:36.135726 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9296 23:47:36.138888 version: 01 04
9297 23:47:36.141869 basic params: 95 1f 11 78 0a
9298 23:47:36.145449 chroma info: 76 90 94 55 54 90 27 21 50 54
9299 23:47:36.148707 established: 00 00 00
9300 23:47:36.155296 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9301 23:47:36.158942 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9302 23:47:36.165611 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9303 23:47:36.172343 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9304 23:47:36.178682 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9305 23:47:36.182022 extensions: 00
9306 23:47:36.182469 checksum: fb
9307 23:47:36.182821
9308 23:47:36.185341 Manufacturer: IVO Model 57d Serial Number 0
9309 23:47:36.188633 Made week 0 of 2020
9310 23:47:36.189063 EDID version: 1.4
9311 23:47:36.192786 Digital display
9312 23:47:36.195596 6 bits per primary color channel
9313 23:47:36.196001 DisplayPort interface
9314 23:47:36.198765 Maximum image size: 31 cm x 17 cm
9315 23:47:36.199166 Gamma: 220%
9316 23:47:36.202190 Check DPMS levels
9317 23:47:36.205891 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9318 23:47:36.209085 First detailed timing is preferred timing
9319 23:47:36.211776 Established timings supported:
9320 23:47:36.215507 Standard timings supported:
9321 23:47:36.215908 Detailed timings
9322 23:47:36.222225 Hex of detail: 383680a07038204018303c0035ae10000019
9323 23:47:36.225551 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9324 23:47:36.229317 0780 0798 07c8 0820 hborder 0
9325 23:47:36.235262 0438 043b 0447 0458 vborder 0
9326 23:47:36.235756 -hsync -vsync
9327 23:47:36.239474 Did detailed timing
9328 23:47:36.242188 Hex of detail: 000000000000000000000000000000000000
9329 23:47:36.245418 Manufacturer-specified data, tag 0
9330 23:47:36.252258 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9331 23:47:36.252815 ASCII string: InfoVision
9332 23:47:36.259363 Hex of detail: 000000fe00523134304e574635205248200a
9333 23:47:36.260038 ASCII string: R140NWF5 RH
9334 23:47:36.262049 Checksum
9335 23:47:36.262492 Checksum: 0xfb (valid)
9336 23:47:36.268567 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9337 23:47:36.269068 DSI data_rate: 832800000 bps
9338 23:47:36.276386 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9339 23:47:36.279729 anx7625_parse_edid: pixelclock(138800).
9340 23:47:36.282889 hactive(1920), hsync(48), hfp(24), hbp(88)
9341 23:47:36.286331 vactive(1080), vsync(12), vfp(3), vbp(17)
9342 23:47:36.289337 anx7625_dsi_config: config dsi.
9343 23:47:36.296611 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9344 23:47:36.310760 anx7625_dsi_config: success to config DSI
9345 23:47:36.313995 anx7625_dp_start: MIPI phy setup OK.
9346 23:47:36.317651 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9347 23:47:36.320875 mtk_ddp_mode_set invalid vrefresh 60
9348 23:47:36.324245 main_disp_path_setup
9349 23:47:36.324652 ovl_layer_smi_id_en
9350 23:47:36.327654 ovl_layer_smi_id_en
9351 23:47:36.328060 ccorr_config
9352 23:47:36.328399 aal_config
9353 23:47:36.331242 gamma_config
9354 23:47:36.331791 postmask_config
9355 23:47:36.334274 dither_config
9356 23:47:36.337683 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9357 23:47:36.344359 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9358 23:47:36.347686 Root Device init finished in 555 msecs
9359 23:47:36.348093 CPU_CLUSTER: 0 init
9360 23:47:36.357633 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9361 23:47:36.361135 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9362 23:47:36.364549 APU_MBOX 0x190000b0 = 0x10001
9363 23:47:36.367877 APU_MBOX 0x190001b0 = 0x10001
9364 23:47:36.371146 APU_MBOX 0x190005b0 = 0x10001
9365 23:47:36.371654 APU_MBOX 0x190006b0 = 0x10001
9366 23:47:36.377957 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9367 23:47:36.389823 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9368 23:47:36.402521 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9369 23:47:36.409040 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9370 23:47:36.421013 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9371 23:47:36.429962 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9372 23:47:36.433311 CPU_CLUSTER: 0 init finished in 81 msecs
9373 23:47:36.436138 Devices initialized
9374 23:47:36.439937 Show all devs... After init.
9375 23:47:36.440476 Root Device: enabled 1
9376 23:47:36.443046 CPU_CLUSTER: 0: enabled 1
9377 23:47:36.446677 CPU: 00: enabled 1
9378 23:47:36.449545 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9379 23:47:36.453303 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9380 23:47:36.456304 ELOG: NV offset 0x57f000 size 0x1000
9381 23:47:36.463277 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9382 23:47:36.470062 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9383 23:47:36.473319 ELOG: Event(17) added with size 13 at 2024-06-04 23:47:36 UTC
9384 23:47:36.476312 out: cmd=0x121: 03 db 21 01 00 00 00 00
9385 23:47:36.481332 in-header: 03 d3 00 00 2c 00 00 00
9386 23:47:36.494298 in-data: 8c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9387 23:47:36.500790 ELOG: Event(A1) added with size 10 at 2024-06-04 23:47:36 UTC
9388 23:47:36.507323 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9389 23:47:36.513616 ELOG: Event(A0) added with size 9 at 2024-06-04 23:47:36 UTC
9390 23:47:36.517481 elog_add_boot_reason: Logged dev mode boot
9391 23:47:36.520940 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9392 23:47:36.523942 Finalize devices...
9393 23:47:36.524391 Devices finalized
9394 23:47:36.530966 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9395 23:47:36.533873 Writing coreboot table at 0xffe64000
9396 23:47:36.537864 0. 000000000010a000-0000000000113fff: RAMSTAGE
9397 23:47:36.540761 1. 0000000040000000-00000000400fffff: RAM
9398 23:47:36.544473 2. 0000000040100000-000000004032afff: RAMSTAGE
9399 23:47:36.550806 3. 000000004032b000-00000000545fffff: RAM
9400 23:47:36.554093 4. 0000000054600000-000000005465ffff: BL31
9401 23:47:36.557747 5. 0000000054660000-00000000ffe63fff: RAM
9402 23:47:36.560402 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9403 23:47:36.567684 7. 0000000100000000-000000023fffffff: RAM
9404 23:47:36.568235 Passing 5 GPIOs to payload:
9405 23:47:36.574406 NAME | PORT | POLARITY | VALUE
9406 23:47:36.577935 EC in RW | 0x000000aa | low | undefined
9407 23:47:36.580945 EC interrupt | 0x00000005 | low | undefined
9408 23:47:36.587753 TPM interrupt | 0x000000ab | high | undefined
9409 23:47:36.591035 SD card detect | 0x00000011 | high | undefined
9410 23:47:36.597582 speaker enable | 0x00000093 | high | undefined
9411 23:47:36.600564 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9412 23:47:36.604789 in-header: 03 f9 00 00 02 00 00 00
9413 23:47:36.605304 in-data: 02 00
9414 23:47:36.607487 ADC[4]: Raw value=900590 ID=7
9415 23:47:36.610830 ADC[3]: Raw value=213336 ID=1
9416 23:47:36.611301 RAM Code: 0x71
9417 23:47:36.614037 ADC[6]: Raw value=74557 ID=0
9418 23:47:36.617904 ADC[5]: Raw value=211860 ID=1
9419 23:47:36.618370 SKU Code: 0x1
9420 23:47:36.624206 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 6bbf
9421 23:47:36.628180 coreboot table: 964 bytes.
9422 23:47:36.630995 IMD ROOT 0. 0xfffff000 0x00001000
9423 23:47:36.634148 IMD SMALL 1. 0xffffe000 0x00001000
9424 23:47:36.638281 RO MCACHE 2. 0xffffc000 0x00001104
9425 23:47:36.641065 CONSOLE 3. 0xfff7c000 0x00080000
9426 23:47:36.641538 FMAP 4. 0xfff7b000 0x00000452
9427 23:47:36.644518 TIME STAMP 5. 0xfff7a000 0x00000910
9428 23:47:36.647615 VBOOT WORK 6. 0xfff66000 0x00014000
9429 23:47:36.651013 RAMOOPS 7. 0xffe66000 0x00100000
9430 23:47:36.654002 COREBOOT 8. 0xffe64000 0x00002000
9431 23:47:36.657945 IMD small region:
9432 23:47:36.660588 IMD ROOT 0. 0xffffec00 0x00000400
9433 23:47:36.664377 VPD 1. 0xffffeb80 0x0000006c
9434 23:47:36.667586 MMC STATUS 2. 0xffffeb60 0x00000004
9435 23:47:36.674065 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9436 23:47:36.674483 Probing TPM: done!
9437 23:47:36.681531 Connected to device vid:did:rid of 1ae0:0028:00
9438 23:47:36.687832 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9439 23:47:36.691559 Initialized TPM device CR50 revision 0
9440 23:47:36.694833 Checking cr50 for pending updates
9441 23:47:36.699811 Reading cr50 TPM mode
9442 23:47:36.708785 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9443 23:47:36.715278 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9444 23:47:36.755543 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9445 23:47:36.758944 Checking segment from ROM address 0x40100000
9446 23:47:36.762118 Checking segment from ROM address 0x4010001c
9447 23:47:36.768787 Loading segment from ROM address 0x40100000
9448 23:47:36.769365 code (compression=0)
9449 23:47:36.775543 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9450 23:47:36.785529 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9451 23:47:36.786100 it's not compressed!
9452 23:47:36.792529 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9453 23:47:36.795824 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9454 23:47:36.815994 Loading segment from ROM address 0x4010001c
9455 23:47:36.816552 Entry Point 0x80000000
9456 23:47:36.818959 Loaded segments
9457 23:47:36.822619 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9458 23:47:36.829356 Jumping to boot code at 0x80000000(0xffe64000)
9459 23:47:36.835999 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9460 23:47:36.842741 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9461 23:47:36.850756 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9462 23:47:36.854194 Checking segment from ROM address 0x40100000
9463 23:47:36.857122 Checking segment from ROM address 0x4010001c
9464 23:47:36.863718 Loading segment from ROM address 0x40100000
9465 23:47:36.864253 code (compression=1)
9466 23:47:36.871347 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9467 23:47:36.880134 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9468 23:47:36.880683 using LZMA
9469 23:47:36.888914 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9470 23:47:36.895298 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9471 23:47:36.898442 Loading segment from ROM address 0x4010001c
9472 23:47:36.898900 Entry Point 0x54601000
9473 23:47:36.902102 Loaded segments
9474 23:47:36.905647 NOTICE: MT8192 bl31_setup
9475 23:47:36.912346 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9476 23:47:36.915861 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9477 23:47:36.919459 WARNING: region 0:
9478 23:47:36.922006 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 23:47:36.922464 WARNING: region 1:
9480 23:47:36.929266 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9481 23:47:36.932430 WARNING: region 2:
9482 23:47:36.935631 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9483 23:47:36.939402 WARNING: region 3:
9484 23:47:36.942196 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9485 23:47:36.945430 WARNING: region 4:
9486 23:47:36.948714 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9487 23:47:36.952809 WARNING: region 5:
9488 23:47:36.956259 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 23:47:36.959773 WARNING: region 6:
9490 23:47:36.962654 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 23:47:36.963205 WARNING: region 7:
9492 23:47:36.969134 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 23:47:36.976252 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9494 23:47:36.979347 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9495 23:47:36.982951 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9496 23:47:36.989308 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9497 23:47:36.992938 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9498 23:47:36.995974 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9499 23:47:37.002728 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9500 23:47:37.005824 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9501 23:47:37.009710 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9502 23:47:37.015798 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9503 23:47:37.019986 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9504 23:47:37.023036 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9505 23:47:37.029398 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9506 23:47:37.032862 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9507 23:47:37.039721 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9508 23:47:37.042675 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9509 23:47:37.046194 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9510 23:47:37.052804 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9511 23:47:37.056767 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9512 23:47:37.059414 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9513 23:47:37.066386 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9514 23:47:37.069504 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9515 23:47:37.076500 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9516 23:47:37.079387 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9517 23:47:37.082675 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9518 23:47:37.089963 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9519 23:47:37.092884 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9520 23:47:37.095994 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9521 23:47:37.102769 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9522 23:47:37.106376 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9523 23:47:37.112936 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9524 23:47:37.116368 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9525 23:47:37.119824 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9526 23:47:37.122988 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9527 23:47:37.129657 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9528 23:47:37.133433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9529 23:47:37.136784 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9530 23:47:37.140329 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9531 23:47:37.147111 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9532 23:47:37.150129 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9533 23:47:37.153739 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9534 23:47:37.157158 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9535 23:47:37.163675 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9536 23:47:37.167085 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9537 23:47:37.170866 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9538 23:47:37.174515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9539 23:47:37.180441 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9540 23:47:37.183673 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9541 23:47:37.187123 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9542 23:47:37.194473 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9543 23:47:37.196951 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9544 23:47:37.203591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9545 23:47:37.207459 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9546 23:47:37.210624 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9547 23:47:37.217340 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9548 23:47:37.220519 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9549 23:47:37.227309 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9550 23:47:37.230744 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9551 23:47:37.233977 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9552 23:47:37.240456 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9553 23:47:37.243945 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9554 23:47:37.250496 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9555 23:47:37.254297 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9556 23:47:37.261276 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9557 23:47:37.264173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9558 23:47:37.268014 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9559 23:47:37.274619 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9560 23:47:37.277705 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9561 23:47:37.284146 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9562 23:47:37.287628 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9563 23:47:37.294472 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9564 23:47:37.298427 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9565 23:47:37.301030 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9566 23:47:37.307486 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9567 23:47:37.311729 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9568 23:47:37.318232 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9569 23:47:37.321221 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9570 23:47:37.327776 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9571 23:47:37.331077 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9572 23:47:37.334441 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9573 23:47:37.341292 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9574 23:47:37.344682 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9575 23:47:37.351720 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9576 23:47:37.354935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9577 23:47:37.358381 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9578 23:47:37.364762 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9579 23:47:37.368007 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9580 23:47:37.375204 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9581 23:47:37.377960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9582 23:47:37.384939 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9583 23:47:37.388230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9584 23:47:37.391491 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9585 23:47:37.398284 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9586 23:47:37.402306 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9587 23:47:37.408326 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9588 23:47:37.412034 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9589 23:47:37.415319 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9590 23:47:37.421302 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9591 23:47:37.425587 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9592 23:47:37.428172 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9593 23:47:37.431677 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9594 23:47:37.438178 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9595 23:47:37.441465 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9596 23:47:37.448694 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9597 23:47:37.451530 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9598 23:47:37.455193 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9599 23:47:37.461663 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9600 23:47:37.464945 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9601 23:47:37.471716 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9602 23:47:37.475167 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9603 23:47:37.478612 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9604 23:47:37.485447 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9605 23:47:37.488680 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9606 23:47:37.491856 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9607 23:47:37.499152 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9608 23:47:37.502067 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9609 23:47:37.505400 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9610 23:47:37.512265 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9611 23:47:37.515716 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9612 23:47:37.518671 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9613 23:47:37.525680 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9614 23:47:37.528893 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9615 23:47:37.531864 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9616 23:47:37.535623 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9617 23:47:37.542253 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9618 23:47:37.545539 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9619 23:47:37.548836 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9620 23:47:37.555740 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9621 23:47:37.559092 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9622 23:47:37.565499 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9623 23:47:37.569411 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9624 23:47:37.572368 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9625 23:47:37.579178 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9626 23:47:37.582670 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9627 23:47:37.585900 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9628 23:47:37.592307 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9629 23:47:37.596057 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9630 23:47:37.599033 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9631 23:47:37.606430 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9632 23:47:37.609452 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9633 23:47:37.616262 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9634 23:47:37.619302 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9635 23:47:37.623117 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9636 23:47:37.629505 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9637 23:47:37.633031 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9638 23:47:37.639890 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9639 23:47:37.642987 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9640 23:47:37.646103 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9641 23:47:37.652804 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9642 23:47:37.656450 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9643 23:47:37.659386 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9644 23:47:37.666441 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9645 23:47:37.669555 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9646 23:47:37.676864 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9647 23:47:37.680117 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9648 23:47:37.683076 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9649 23:47:37.689864 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9650 23:47:37.693564 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9651 23:47:37.696600 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9652 23:47:37.703064 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9653 23:47:37.706766 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9654 23:47:37.713458 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9655 23:47:37.716568 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9656 23:47:37.720144 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9657 23:47:37.726614 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9658 23:47:37.729994 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9659 23:47:37.732964 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9660 23:47:37.740127 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9661 23:47:37.743381 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9662 23:47:37.749892 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9663 23:47:37.753610 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9664 23:47:37.756597 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9665 23:47:37.763575 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9666 23:47:37.766361 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9667 23:47:37.773414 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9668 23:47:37.776615 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9669 23:47:37.780325 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9670 23:47:37.787068 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9671 23:47:37.790214 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9672 23:47:37.793504 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9673 23:47:37.800077 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9674 23:47:37.803164 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9675 23:47:37.809932 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9676 23:47:37.813097 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9677 23:47:37.816680 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9678 23:47:37.823162 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9679 23:47:37.826545 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9680 23:47:37.833613 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9681 23:47:37.836317 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9682 23:47:37.839881 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9683 23:47:37.846712 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9684 23:47:37.849823 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9685 23:47:37.856602 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9686 23:47:37.859874 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9687 23:47:37.863094 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9688 23:47:37.870034 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9689 23:47:37.872878 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9690 23:47:37.879860 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9691 23:47:37.883017 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9692 23:47:37.889982 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9693 23:47:37.892854 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9694 23:47:37.896139 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9695 23:47:37.903250 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9696 23:47:37.907022 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9697 23:47:37.913340 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9698 23:47:37.916668 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9699 23:47:37.920124 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9700 23:47:37.926332 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9701 23:47:37.929928 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9702 23:47:37.936659 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9703 23:47:37.940165 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9704 23:47:37.943533 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9705 23:47:37.949824 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9706 23:47:37.953465 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9707 23:47:37.960197 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9708 23:47:37.963210 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9709 23:47:37.966716 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9710 23:47:37.973192 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9711 23:47:37.976426 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9712 23:47:37.983370 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9713 23:47:37.986600 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9714 23:47:37.990113 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9715 23:47:37.996615 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9716 23:47:37.999865 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9717 23:47:38.006782 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9718 23:47:38.010105 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9719 23:47:38.016530 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9720 23:47:38.020018 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9721 23:47:38.023085 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9722 23:47:38.029678 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9723 23:47:38.033450 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9724 23:47:38.036709 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9725 23:47:38.039969 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9726 23:47:38.043342 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9727 23:47:38.049960 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9728 23:47:38.053213 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9729 23:47:38.059689 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9730 23:47:38.063187 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9731 23:47:38.066099 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9732 23:47:38.073098 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9733 23:47:38.076316 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9734 23:47:38.079938 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9735 23:47:38.086584 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9736 23:47:38.090010 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9737 23:47:38.096520 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9738 23:47:38.099456 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9739 23:47:38.103086 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9740 23:47:38.110212 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9741 23:47:38.112811 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9742 23:47:38.116390 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9743 23:47:38.122861 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9744 23:47:38.126426 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9745 23:47:38.129733 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9746 23:47:38.136741 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9747 23:47:38.139503 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9748 23:47:38.142895 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9749 23:47:38.149684 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9750 23:47:38.153104 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9751 23:47:38.159459 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9752 23:47:38.163001 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9753 23:47:38.166232 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9754 23:47:38.172652 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9755 23:47:38.176287 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9756 23:47:38.179658 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9757 23:47:38.186343 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9758 23:47:38.189640 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9759 23:47:38.196295 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9760 23:47:38.199740 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9761 23:47:38.203176 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9762 23:47:38.206452 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9763 23:47:38.212814 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9764 23:47:38.216008 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9765 23:47:38.219474 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9766 23:47:38.222643 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9767 23:47:38.227039 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9768 23:47:38.232781 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9769 23:47:38.236730 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9770 23:47:38.239708 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9771 23:47:38.243097 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9772 23:47:38.250147 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9773 23:47:38.253620 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9774 23:47:38.256112 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9775 23:47:38.263358 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9776 23:47:38.266747 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9777 23:47:38.272905 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9778 23:47:38.276283 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9779 23:47:38.279589 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9780 23:47:38.286404 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9781 23:47:38.289593 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9782 23:47:38.293456 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9783 23:47:38.300347 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9784 23:47:38.303724 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9785 23:47:38.310045 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9786 23:47:38.312912 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9787 23:47:38.320334 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9788 23:47:38.323807 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9789 23:47:38.327144 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9790 23:47:38.333685 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9791 23:47:38.336903 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9792 23:47:38.340242 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9793 23:47:38.346597 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9794 23:47:38.350058 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9795 23:47:38.357072 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9796 23:47:38.359648 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9797 23:47:38.366955 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9798 23:47:38.369808 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9799 23:47:38.373382 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9800 23:47:38.380659 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9801 23:47:38.383742 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9802 23:47:38.390925 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9803 23:47:38.393344 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9804 23:47:38.397110 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9805 23:47:38.403393 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9806 23:47:38.406660 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9807 23:47:38.410497 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9808 23:47:38.417216 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9809 23:47:38.420540 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9810 23:47:38.427098 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9811 23:47:38.430160 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9812 23:47:38.436875 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9813 23:47:38.440583 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9814 23:47:38.443157 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9815 23:47:38.450586 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9816 23:47:38.453501 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9817 23:47:38.456950 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9818 23:47:38.463283 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9819 23:47:38.466895 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9820 23:47:38.473196 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9821 23:47:38.476717 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9822 23:47:38.480083 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9823 23:47:38.486611 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9824 23:47:38.489783 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9825 23:47:38.496641 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9826 23:47:38.500314 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9827 23:47:38.506482 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9828 23:47:38.509715 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9829 23:47:38.513533 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9830 23:47:38.519799 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9831 23:47:38.523867 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9832 23:47:38.529929 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9833 23:47:38.533367 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9834 23:47:38.537148 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9835 23:47:38.543610 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9836 23:47:38.546745 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9837 23:47:38.553939 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9838 23:47:38.557187 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9839 23:47:38.560500 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9840 23:47:38.566427 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9841 23:47:38.570271 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9842 23:47:38.577006 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9843 23:47:38.580469 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9844 23:47:38.584000 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9845 23:47:38.590374 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9846 23:47:38.593684 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9847 23:47:38.600546 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9848 23:47:38.604041 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9849 23:47:38.607120 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9850 23:47:38.613966 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9851 23:47:38.617670 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9852 23:47:38.623930 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9853 23:47:38.627033 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9854 23:47:38.630483 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9855 23:47:38.637169 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9856 23:47:38.640129 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9857 23:47:38.646869 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9858 23:47:38.649990 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9859 23:47:38.656882 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9860 23:47:38.660109 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9861 23:47:38.667187 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9862 23:47:38.670482 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9863 23:47:38.673761 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9864 23:47:38.679982 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9865 23:47:38.683472 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9866 23:47:38.690259 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9867 23:47:38.693508 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9868 23:47:38.700637 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9869 23:47:38.703733 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9870 23:47:38.706961 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9871 23:47:38.713823 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9872 23:47:38.717273 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9873 23:47:38.723667 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9874 23:47:38.726842 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9875 23:47:38.733738 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9876 23:47:38.737211 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9877 23:47:38.740332 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9878 23:47:38.747077 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9879 23:47:38.750515 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9880 23:47:38.757180 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9881 23:47:38.760717 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9882 23:47:38.763579 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9883 23:47:38.770725 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9884 23:47:38.774242 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9885 23:47:38.780383 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9886 23:47:38.783590 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9887 23:47:38.790270 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9888 23:47:38.793524 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9889 23:47:38.796856 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9890 23:47:38.803416 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9891 23:47:38.806883 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9892 23:47:38.813390 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9893 23:47:38.816906 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9894 23:47:38.823512 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9895 23:47:38.826880 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9896 23:47:38.830591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9897 23:47:38.837211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9898 23:47:38.840761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9899 23:47:38.847132 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9900 23:47:38.851015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9901 23:47:38.857431 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9902 23:47:38.860645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9903 23:47:38.867470 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9904 23:47:38.870612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9905 23:47:38.877288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9906 23:47:38.880190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9907 23:47:38.887488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9908 23:47:38.890515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9909 23:47:38.893897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9910 23:47:38.900397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9911 23:47:38.903766 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9912 23:47:38.910159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9913 23:47:38.913412 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9914 23:47:38.920001 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9915 23:47:38.923505 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9916 23:47:38.930388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9917 23:47:38.933615 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9918 23:47:38.940010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9919 23:47:38.943803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9920 23:47:38.950377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9921 23:47:38.953331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9922 23:47:38.960183 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9923 23:47:38.963214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9924 23:47:38.970246 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9925 23:47:38.973849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9926 23:47:38.980654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9927 23:47:38.983588 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9928 23:47:38.986795 INFO: [APUAPC] vio 0
9929 23:47:38.990181 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9930 23:47:38.996818 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9931 23:47:39.000263 INFO: [APUAPC] D0_APC_0: 0x400510
9932 23:47:39.000349 INFO: [APUAPC] D0_APC_1: 0x0
9933 23:47:39.003739 INFO: [APUAPC] D0_APC_2: 0x1540
9934 23:47:39.007218 INFO: [APUAPC] D0_APC_3: 0x0
9935 23:47:39.010177 INFO: [APUAPC] D1_APC_0: 0xffffffff
9936 23:47:39.013592 INFO: [APUAPC] D1_APC_1: 0xffffffff
9937 23:47:39.016832 INFO: [APUAPC] D1_APC_2: 0x3fffff
9938 23:47:39.020168 INFO: [APUAPC] D1_APC_3: 0x0
9939 23:47:39.023485 INFO: [APUAPC] D2_APC_0: 0xffffffff
9940 23:47:39.026832 INFO: [APUAPC] D2_APC_1: 0xffffffff
9941 23:47:39.030238 INFO: [APUAPC] D2_APC_2: 0x3fffff
9942 23:47:39.033241 INFO: [APUAPC] D2_APC_3: 0x0
9943 23:47:39.036942 INFO: [APUAPC] D3_APC_0: 0xffffffff
9944 23:47:39.040406 INFO: [APUAPC] D3_APC_1: 0xffffffff
9945 23:47:39.043336 INFO: [APUAPC] D3_APC_2: 0x3fffff
9946 23:47:39.046411 INFO: [APUAPC] D3_APC_3: 0x0
9947 23:47:39.049882 INFO: [APUAPC] D4_APC_0: 0xffffffff
9948 23:47:39.053968 INFO: [APUAPC] D4_APC_1: 0xffffffff
9949 23:47:39.056798 INFO: [APUAPC] D4_APC_2: 0x3fffff
9950 23:47:39.060195 INFO: [APUAPC] D4_APC_3: 0x0
9951 23:47:39.063639 INFO: [APUAPC] D5_APC_0: 0xffffffff
9952 23:47:39.066804 INFO: [APUAPC] D5_APC_1: 0xffffffff
9953 23:47:39.069818 INFO: [APUAPC] D5_APC_2: 0x3fffff
9954 23:47:39.073692 INFO: [APUAPC] D5_APC_3: 0x0
9955 23:47:39.077287 INFO: [APUAPC] D6_APC_0: 0xffffffff
9956 23:47:39.079942 INFO: [APUAPC] D6_APC_1: 0xffffffff
9957 23:47:39.083323 INFO: [APUAPC] D6_APC_2: 0x3fffff
9958 23:47:39.086996 INFO: [APUAPC] D6_APC_3: 0x0
9959 23:47:39.090410 INFO: [APUAPC] D7_APC_0: 0xffffffff
9960 23:47:39.093292 INFO: [APUAPC] D7_APC_1: 0xffffffff
9961 23:47:39.096752 INFO: [APUAPC] D7_APC_2: 0x3fffff
9962 23:47:39.100114 INFO: [APUAPC] D7_APC_3: 0x0
9963 23:47:39.103741 INFO: [APUAPC] D8_APC_0: 0xffffffff
9964 23:47:39.106627 INFO: [APUAPC] D8_APC_1: 0xffffffff
9965 23:47:39.109945 INFO: [APUAPC] D8_APC_2: 0x3fffff
9966 23:47:39.110027 INFO: [APUAPC] D8_APC_3: 0x0
9967 23:47:39.113596 INFO: [APUAPC] D9_APC_0: 0xffffffff
9968 23:47:39.119818 INFO: [APUAPC] D9_APC_1: 0xffffffff
9969 23:47:39.119926 INFO: [APUAPC] D9_APC_2: 0x3fffff
9970 23:47:39.122918 INFO: [APUAPC] D9_APC_3: 0x0
9971 23:47:39.126474 INFO: [APUAPC] D10_APC_0: 0xffffffff
9972 23:47:39.130373 INFO: [APUAPC] D10_APC_1: 0xffffffff
9973 23:47:39.133626 INFO: [APUAPC] D10_APC_2: 0x3fffff
9974 23:47:39.136848 INFO: [APUAPC] D10_APC_3: 0x0
9975 23:47:39.140219 INFO: [APUAPC] D11_APC_0: 0xffffffff
9976 23:47:39.143472 INFO: [APUAPC] D11_APC_1: 0xffffffff
9977 23:47:39.146851 INFO: [APUAPC] D11_APC_2: 0x3fffff
9978 23:47:39.150048 INFO: [APUAPC] D11_APC_3: 0x0
9979 23:47:39.153546 INFO: [APUAPC] D12_APC_0: 0xffffffff
9980 23:47:39.157294 INFO: [APUAPC] D12_APC_1: 0xffffffff
9981 23:47:39.160453 INFO: [APUAPC] D12_APC_2: 0x3fffff
9982 23:47:39.164382 INFO: [APUAPC] D12_APC_3: 0x0
9983 23:47:39.166919 INFO: [APUAPC] D13_APC_0: 0xffffffff
9984 23:47:39.171001 INFO: [APUAPC] D13_APC_1: 0xffffffff
9985 23:47:39.174067 INFO: [APUAPC] D13_APC_2: 0x3fffff
9986 23:47:39.177043 INFO: [APUAPC] D13_APC_3: 0x0
9987 23:47:39.180543 INFO: [APUAPC] D14_APC_0: 0xffffffff
9988 23:47:39.183830 INFO: [APUAPC] D14_APC_1: 0xffffffff
9989 23:47:39.187288 INFO: [APUAPC] D14_APC_2: 0x3fffff
9990 23:47:39.190812 INFO: [APUAPC] D14_APC_3: 0x0
9991 23:47:39.194021 INFO: [APUAPC] D15_APC_0: 0xffffffff
9992 23:47:39.197263 INFO: [APUAPC] D15_APC_1: 0xffffffff
9993 23:47:39.201093 INFO: [APUAPC] D15_APC_2: 0x3fffff
9994 23:47:39.203753 INFO: [APUAPC] D15_APC_3: 0x0
9995 23:47:39.207784 INFO: [APUAPC] APC_CON: 0x4
9996 23:47:39.210935 INFO: [NOCDAPC] D0_APC_0: 0x0
9997 23:47:39.213719 INFO: [NOCDAPC] D0_APC_1: 0x0
9998 23:47:39.217136 INFO: [NOCDAPC] D1_APC_0: 0x0
9999 23:47:39.220756 INFO: [NOCDAPC] D1_APC_1: 0xfff
10000 23:47:39.223820 INFO: [NOCDAPC] D2_APC_0: 0x0
10001 23:47:39.227157 INFO: [NOCDAPC] D2_APC_1: 0xfff
10002 23:47:39.227586 INFO: [NOCDAPC] D3_APC_0: 0x0
10003 23:47:39.230482 INFO: [NOCDAPC] D3_APC_1: 0xfff
10004 23:47:39.233734 INFO: [NOCDAPC] D4_APC_0: 0x0
10005 23:47:39.236931 INFO: [NOCDAPC] D4_APC_1: 0xfff
10006 23:47:39.240533 INFO: [NOCDAPC] D5_APC_0: 0x0
10007 23:47:39.244023 INFO: [NOCDAPC] D5_APC_1: 0xfff
10008 23:47:39.247155 INFO: [NOCDAPC] D6_APC_0: 0x0
10009 23:47:39.250770 INFO: [NOCDAPC] D6_APC_1: 0xfff
10010 23:47:39.253839 INFO: [NOCDAPC] D7_APC_0: 0x0
10011 23:47:39.256926 INFO: [NOCDAPC] D7_APC_1: 0xfff
10012 23:47:39.257570 INFO: [NOCDAPC] D8_APC_0: 0x0
10013 23:47:39.260313 INFO: [NOCDAPC] D8_APC_1: 0xfff
10014 23:47:39.263606 INFO: [NOCDAPC] D9_APC_0: 0x0
10015 23:47:39.267383 INFO: [NOCDAPC] D9_APC_1: 0xfff
10016 23:47:39.270471 INFO: [NOCDAPC] D10_APC_0: 0x0
10017 23:47:39.274232 INFO: [NOCDAPC] D10_APC_1: 0xfff
10018 23:47:39.277308 INFO: [NOCDAPC] D11_APC_0: 0x0
10019 23:47:39.280783 INFO: [NOCDAPC] D11_APC_1: 0xfff
10020 23:47:39.284224 INFO: [NOCDAPC] D12_APC_0: 0x0
10021 23:47:39.287238 INFO: [NOCDAPC] D12_APC_1: 0xfff
10022 23:47:39.290525 INFO: [NOCDAPC] D13_APC_0: 0x0
10023 23:47:39.294102 INFO: [NOCDAPC] D13_APC_1: 0xfff
10024 23:47:39.294531 INFO: [NOCDAPC] D14_APC_0: 0x0
10025 23:47:39.297060 INFO: [NOCDAPC] D14_APC_1: 0xfff
10026 23:47:39.300575 INFO: [NOCDAPC] D15_APC_0: 0x0
10027 23:47:39.303853 INFO: [NOCDAPC] D15_APC_1: 0xfff
10028 23:47:39.307292 INFO: [NOCDAPC] APC_CON: 0x4
10029 23:47:39.310428 INFO: [APUAPC] set_apusys_apc done
10030 23:47:39.314036 INFO: [DEVAPC] devapc_init done
10031 23:47:39.317356 INFO: GICv3 without legacy support detected.
10032 23:47:39.323769 INFO: ARM GICv3 driver initialized in EL3
10033 23:47:39.327524 INFO: Maximum SPI INTID supported: 639
10034 23:47:39.330586 INFO: BL31: Initializing runtime services
10035 23:47:39.337103 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10036 23:47:39.337402 INFO: SPM: enable CPC mode
10037 23:47:39.344046 INFO: mcdi ready for mcusys-off-idle and system suspend
10038 23:47:39.347015 INFO: BL31: Preparing for EL3 exit to normal world
10039 23:47:39.353774 INFO: Entry point address = 0x80000000
10040 23:47:39.354255 INFO: SPSR = 0x8
10041 23:47:39.360117
10042 23:47:39.360667
10043 23:47:39.361070
10044 23:47:39.363703 Starting depthcharge on Spherion...
10045 23:47:39.364250
10046 23:47:39.364615 Wipe memory regions:
10047 23:47:39.364952
10048 23:47:39.367713 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10049 23:47:39.368259 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10050 23:47:39.368721 Setting prompt string to ['asurada:']
10051 23:47:39.369204 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10052 23:47:39.369934 [0x00000040000000, 0x00000054600000)
10053 23:47:39.488884
10054 23:47:39.489377 [0x00000054660000, 0x00000080000000)
10055 23:47:39.749593
10056 23:47:39.750354 [0x000000821a7280, 0x000000ffe64000)
10057 23:47:40.494219
10058 23:47:40.494369 [0x00000100000000, 0x00000240000000)
10059 23:47:42.383826
10060 23:47:42.387742 Initializing XHCI USB controller at 0x11200000.
10061 23:47:43.425757
10062 23:47:43.428301 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10063 23:47:43.428393
10064 23:47:43.428465
10065 23:47:43.428744 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10067 23:47:43.529056 asurada: tftpboot 192.168.201.1 14172991/tftp-deploy-8tg3m569/kernel/image.itb 14172991/tftp-deploy-8tg3m569/kernel/cmdline
10068 23:47:43.529231 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10069 23:47:43.529312 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10070 23:47:43.533558 tftpboot 192.168.201.1 14172991/tftp-deploy-8tg3m569/kernel/image.itp-deploy-8tg3m569/kernel/cmdline
10071 23:47:43.533643
10072 23:47:43.533710 Waiting for link
10073 23:47:43.694475
10074 23:47:43.694643 R8152: Initializing
10075 23:47:43.694709
10076 23:47:43.697777 Version 6 (ocp_data = 5c30)
10077 23:47:43.697872
10078 23:47:43.700617 R8152: Done initializing
10079 23:47:43.700697
10080 23:47:43.700761 Adding net device
10081 23:47:45.603965
10082 23:47:45.604116 done.
10083 23:47:45.604183
10084 23:47:45.604243 MAC: 00:24:32:30:78:52
10085 23:47:45.604301
10086 23:47:45.607147 Sending DHCP discover... done.
10087 23:47:45.607262
10088 23:47:45.610291 Waiting for reply... done.
10089 23:47:45.610400
10090 23:47:45.613396 Sending DHCP request... done.
10091 23:47:45.613484
10092 23:47:45.617868 Waiting for reply... done.
10093 23:47:45.617951
10094 23:47:45.618015 My ip is 192.168.201.14
10095 23:47:45.618075
10096 23:47:45.621495 The DHCP server ip is 192.168.201.1
10097 23:47:45.621577
10098 23:47:45.627796 TFTP server IP predefined by user: 192.168.201.1
10099 23:47:45.627880
10100 23:47:45.634549 Bootfile predefined by user: 14172991/tftp-deploy-8tg3m569/kernel/image.itb
10101 23:47:45.634635
10102 23:47:45.634700 Sending tftp read request... done.
10103 23:47:45.638140
10104 23:47:45.641780 Waiting for the transfer...
10105 23:47:45.641864
10106 23:47:46.221560 00000000 ################################################################
10107 23:47:46.221699
10108 23:47:46.812606 00080000 ################################################################
10109 23:47:46.812752
10110 23:47:47.412875 00100000 ################################################################
10111 23:47:47.413047
10112 23:47:47.991816 00180000 ################################################################
10113 23:47:47.992044
10114 23:47:48.560120 00200000 ################################################################
10115 23:47:48.560263
10116 23:47:49.128822 00280000 ################################################################
10117 23:47:49.128988
10118 23:47:49.757045 00300000 ################################################################
10119 23:47:49.757250
10120 23:47:50.299567 00380000 ################################################################
10121 23:47:50.299716
10122 23:47:50.826049 00400000 ################################################################
10123 23:47:50.826249
10124 23:47:51.419865 00480000 ################################################################
10125 23:47:51.420014
10126 23:47:51.975375 00500000 ################################################################
10127 23:47:51.975518
10128 23:47:52.529290 00580000 ################################################################
10129 23:47:52.529439
10130 23:47:53.097884 00600000 ################################################################
10131 23:47:53.098024
10132 23:47:53.649193 00680000 ################################################################
10133 23:47:53.649334
10134 23:47:54.172854 00700000 ################################################################
10135 23:47:54.173033
10136 23:47:54.704037 00780000 ################################################################
10137 23:47:54.704183
10138 23:47:55.242464 00800000 ################################################################
10139 23:47:55.242610
10140 23:47:55.789416 00880000 ################################################################
10141 23:47:55.789558
10142 23:47:56.339851 00900000 ################################################################
10143 23:47:56.339998
10144 23:47:56.906146 00980000 ################################################################
10145 23:47:56.906291
10146 23:47:57.465034 00a00000 ################################################################
10147 23:47:57.465183
10148 23:47:57.996200 00a80000 ################################################################
10149 23:47:57.996344
10150 23:47:58.552540 00b00000 ################################################################
10151 23:47:58.552685
10152 23:47:59.115651 00b80000 ################################################################
10153 23:47:59.115786
10154 23:47:59.681612 00c00000 ################################################################
10155 23:47:59.681755
10156 23:48:00.254836 00c80000 ################################################################
10157 23:48:00.254985
10158 23:48:00.833417 00d00000 ################################################################
10159 23:48:00.833560
10160 23:48:01.426900 00d80000 ################################################################
10161 23:48:01.427145
10162 23:48:02.138129 00e00000 ################################################################
10163 23:48:02.138569
10164 23:48:02.810525 00e80000 ################################################################
10165 23:48:02.810963
10166 23:48:03.507894 00f00000 ################################################################
10167 23:48:03.508416
10168 23:48:04.218037 00f80000 ################################################################
10169 23:48:04.218555
10170 23:48:04.916291 01000000 ################################################################
10171 23:48:04.916803
10172 23:48:05.613435 01080000 ################################################################
10173 23:48:05.613954
10174 23:48:06.313052 01100000 ################################################################
10175 23:48:06.313577
10176 23:48:07.018440 01180000 ################################################################
10177 23:48:07.019022
10178 23:48:07.725375 01200000 ################################################################
10179 23:48:07.725893
10180 23:48:08.448054 01280000 ################################################################
10181 23:48:08.448549
10182 23:48:09.121865 01300000 ################################################################
10183 23:48:09.122376
10184 23:48:09.830841 01380000 ################################################################
10185 23:48:09.831411
10186 23:48:10.557726 01400000 ################################################################
10187 23:48:10.558253
10188 23:48:11.260136 01480000 ################################################################
10189 23:48:11.260655
10190 23:48:11.969790 01500000 ################################################################
10191 23:48:11.970484
10192 23:48:12.679337 01580000 ################################################################
10193 23:48:12.679866
10194 23:48:13.297919 01600000 ################################################################
10195 23:48:13.298328
10196 23:48:13.995741 01680000 ################################################################
10197 23:48:13.996231
10198 23:48:14.689610 01700000 ################################################################
10199 23:48:14.690103
10200 23:48:15.370355 01780000 ################################################################
10201 23:48:15.370836
10202 23:48:16.055899 01800000 ################################################################
10203 23:48:16.056431
10204 23:48:16.736651 01880000 ################################################################
10205 23:48:16.737374
10206 23:48:17.361584 01900000 ################################################################
10207 23:48:17.361723
10208 23:48:18.020229 01980000 ################################################################
10209 23:48:18.020864
10210 23:48:18.638692 01a00000 ################################################################
10211 23:48:18.638829
10212 23:48:19.182025 01a80000 ################################################################
10213 23:48:19.182156
10214 23:48:19.791693 01b00000 ################################################################
10215 23:48:19.792259
10216 23:48:20.402264 01b80000 ################################################################
10217 23:48:20.402756
10218 23:48:21.100408 01c00000 ################################################################
10219 23:48:21.100944
10220 23:48:21.707591 01c80000 ################################################################
10221 23:48:21.707726
10222 23:48:22.233597 01d00000 ################################################################
10223 23:48:22.233730
10224 23:48:22.789161 01d80000 ################################################################
10225 23:48:22.789303
10226 23:48:23.310609 01e00000 ################################################################
10227 23:48:23.310748
10228 23:48:23.830349 01e80000 ################################################################
10229 23:48:23.830483
10230 23:48:24.372388 01f00000 ################################################################
10231 23:48:24.372523
10232 23:48:24.938166 01f80000 ################################################################
10233 23:48:24.938340
10234 23:48:25.495447 02000000 ################################################################
10235 23:48:25.495588
10236 23:48:26.017656 02080000 ################################################################
10237 23:48:26.017799
10238 23:48:26.563867 02100000 ################################################################
10239 23:48:26.564006
10240 23:48:27.093961 02180000 ################################################################
10241 23:48:27.094097
10242 23:48:27.625274 02200000 ################################################################
10243 23:48:27.625428
10244 23:48:28.149732 02280000 ################################################################
10245 23:48:28.149887
10246 23:48:28.695577 02300000 ################################################################
10247 23:48:28.695755
10248 23:48:29.255500 02380000 ################################################################
10249 23:48:29.255649
10250 23:48:29.798020 02400000 ################################################################
10251 23:48:29.798170
10252 23:48:30.331209 02480000 ################################################################
10253 23:48:30.331353
10254 23:48:30.864437 02500000 ################################################################
10255 23:48:30.864575
10256 23:48:31.396319 02580000 ################################################################
10257 23:48:31.396460
10258 23:48:31.950727 02600000 ################################################################
10259 23:48:31.950872
10260 23:48:32.485248 02680000 ################################################################
10261 23:48:32.485382
10262 23:48:33.017761 02700000 ################################################################
10263 23:48:33.017906
10264 23:48:33.542627 02780000 ################################################################
10265 23:48:33.542772
10266 23:48:34.087757 02800000 ################################################################
10267 23:48:34.087885
10268 23:48:34.617949 02880000 ################################################################
10269 23:48:34.618092
10270 23:48:35.174911 02900000 ################################################################
10271 23:48:35.175078
10272 23:48:35.717688 02980000 ################################################################
10273 23:48:35.717837
10274 23:48:36.270153 02a00000 ################################################################
10275 23:48:36.270294
10276 23:48:36.827794 02a80000 ################################################################
10277 23:48:36.827937
10278 23:48:37.396136 02b00000 ################################################################
10279 23:48:37.396280
10280 23:48:38.074906 02b80000 ################################################################
10281 23:48:38.075427
10282 23:48:38.789269 02c00000 ################################################################
10283 23:48:38.789866
10284 23:48:39.471200 02c80000 ################################################################
10285 23:48:39.471701
10286 23:48:40.085002 02d00000 ################################################################
10287 23:48:40.085261
10288 23:48:40.696958 02d80000 ################################################################
10289 23:48:40.697146
10290 23:48:41.322337 02e00000 ################################################################
10291 23:48:41.322477
10292 23:48:41.943826 02e80000 ################################################################
10293 23:48:41.944307
10294 23:48:42.622355 02f00000 ################################################################
10295 23:48:42.622903
10296 23:48:43.341458 02f80000 ################################################################
10297 23:48:43.342029
10298 23:48:44.055599 03000000 ################################################################
10299 23:48:44.056106
10300 23:48:44.767724 03080000 ################################################################
10301 23:48:44.768239
10302 23:48:45.481866 03100000 ################################################################
10303 23:48:45.482393
10304 23:48:46.199912 03180000 ################################################################
10305 23:48:46.200411
10306 23:48:46.912499 03200000 ################################################################
10307 23:48:46.913094
10308 23:48:47.613382 03280000 ################################################################
10309 23:48:47.614019
10310 23:48:48.340184 03300000 ################################################################
10311 23:48:48.340702
10312 23:48:49.011280 03380000 ################################################################
10313 23:48:49.011419
10314 23:48:49.668507 03400000 ################################################################
10315 23:48:49.668773
10316 23:48:50.299665 03480000 ################################################################
10317 23:48:50.299814
10318 23:48:50.917819 03500000 ################################################################
10319 23:48:50.918416
10320 23:48:51.518389 03580000 ################################################################
10321 23:48:51.518594
10322 23:48:52.205517 03600000 ################################################################
10323 23:48:52.206036
10324 23:48:52.900542 03680000 ################################################################
10325 23:48:52.900883
10326 23:48:53.520940 03700000 ################################################################
10327 23:48:53.521539
10328 23:48:54.116170 03780000 ################################################################
10329 23:48:54.116312
10330 23:48:54.670060 03800000 ################################################################
10331 23:48:54.670210
10332 23:48:55.228681 03880000 ################################################################
10333 23:48:55.228823
10334 23:48:55.862244 03900000 ################################################################
10335 23:48:55.862813
10336 23:48:56.480891 03980000 ################################################################
10337 23:48:56.481083
10338 23:48:57.126863 03a00000 ################################################################
10339 23:48:57.127036
10340 23:48:57.687025 03a80000 ################################################################
10341 23:48:57.687161
10342 23:48:58.312834 03b00000 ################################################################
10343 23:48:58.313383
10344 23:48:59.013733 03b80000 ################################################################
10345 23:48:59.014236
10346 23:48:59.673489 03c00000 ################################################################
10347 23:48:59.674021
10348 23:49:00.261340 03c80000 ################################################################
10349 23:49:00.261471
10350 23:49:00.898578 03d00000 ################################################################
10351 23:49:00.899146
10352 23:49:01.563801 03d80000 ################################################################
10353 23:49:01.563934
10354 23:49:02.170376 03e00000 ################################################################
10355 23:49:02.170700
10356 23:49:02.814032 03e80000 ################################################################
10357 23:49:02.814334
10358 23:49:03.463013 03f00000 ################################################################
10359 23:49:03.463162
10360 23:49:04.068483 03f80000 ################################################################
10361 23:49:04.068657
10362 23:49:04.785092 04000000 ################################################################
10363 23:49:04.785682
10364 23:49:05.506480 04080000 ################################################################
10365 23:49:05.507058
10366 23:49:06.229588 04100000 ################################################################
10367 23:49:06.230128
10368 23:49:06.943320 04180000 ################################################################
10369 23:49:06.943820
10370 23:49:07.643818 04200000 ################################################################
10371 23:49:07.644345
10372 23:49:08.330238 04280000 ################################################################
10373 23:49:08.330764
10374 23:49:09.048215 04300000 ################################################################
10375 23:49:09.048723
10376 23:49:09.761142 04380000 ################################################################
10377 23:49:09.761683
10378 23:49:10.486860 04400000 ################################################################
10379 23:49:10.487439
10380 23:49:11.210641 04480000 ################################################################
10381 23:49:11.211203
10382 23:49:11.933123 04500000 ################################################################
10383 23:49:11.933616
10384 23:49:12.646685 04580000 ################################################################
10385 23:49:12.647185
10386 23:49:13.344392 04600000 ################################################################
10387 23:49:13.344901
10388 23:49:13.602008 04680000 ######################## done.
10389 23:49:13.602520
10390 23:49:13.606409 The bootfile was 74116494 bytes long.
10391 23:49:13.606822
10392 23:49:13.608525 Sending tftp read request... done.
10393 23:49:13.608937
10394 23:49:13.612192 Waiting for the transfer...
10395 23:49:13.612600
10396 23:49:13.612924 00000000 # done.
10397 23:49:13.613271
10398 23:49:13.619349 Command line loaded dynamically from TFTP file: 14172991/tftp-deploy-8tg3m569/kernel/cmdline
10399 23:49:13.619852
10400 23:49:13.632433 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10401 23:49:13.635565
10402 23:49:13.636081 Loading FIT.
10403 23:49:13.636414
10404 23:49:13.638760 Image ramdisk-1 has 61005769 bytes.
10405 23:49:13.639171
10406 23:49:13.643255 Image fdt-1 has 47258 bytes.
10407 23:49:13.643772
10408 23:49:13.644103 Image kernel-1 has 13061430 bytes.
10409 23:49:13.645655
10410 23:49:13.652563 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10411 23:49:13.653132
10412 23:49:13.668858 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10413 23:49:13.673346
10414 23:49:13.675449 Choosing best match conf-1 for compat google,spherion-rev2.
10415 23:49:13.679968
10416 23:49:13.685501 Connected to device vid:did:rid of 1ae0:0028:00
10417 23:49:13.693311
10418 23:49:13.696189 tpm_get_response: command 0x17b, return code 0x0
10419 23:49:13.696642
10420 23:49:13.699809 ec_init: CrosEC protocol v3 supported (256, 248)
10421 23:49:13.703461
10422 23:49:13.707384 tpm_cleanup: add release locality here.
10423 23:49:13.707931
10424 23:49:13.708292 Shutting down all USB controllers.
10425 23:49:13.710037
10426 23:49:13.710416 Removing current net device
10427 23:49:13.710750
10428 23:49:13.717417 Exiting depthcharge with code 4 at timestamp: 123758051
10429 23:49:13.718011
10430 23:49:13.720477 LZMA decompressing kernel-1 to 0x821a6718
10431 23:49:13.720934
10432 23:49:13.723338 LZMA decompressing kernel-1 to 0x40000000
10433 23:49:15.333787
10434 23:49:15.334328 jumping to kernel
10435 23:49:15.336482 end: 2.2.4 bootloader-commands (duration 00:01:36) [common]
10436 23:49:15.337076 start: 2.2.5 auto-login-action (timeout 00:02:49) [common]
10437 23:49:15.337481 Setting prompt string to ['Linux version [0-9]']
10438 23:49:15.337860 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10439 23:49:15.338240 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10440 23:49:15.415697
10441 23:49:15.418519 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10442 23:49:15.422961 start: 2.2.5.1 login-action (timeout 00:02:49) [common]
10443 23:49:15.423503 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10444 23:49:15.423904 Setting prompt string to []
10445 23:49:15.424312 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10446 23:49:15.424705 Using line separator: #'\n'#
10447 23:49:15.425069 No login prompt set.
10448 23:49:15.425400 Parsing kernel messages
10449 23:49:15.425698 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10450 23:49:15.426259 [login-action] Waiting for messages, (timeout 00:02:49)
10451 23:49:15.426620 Waiting using forced prompt support (timeout 00:01:25)
10452 23:49:15.441886 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j217067-arm64-gcc-10-defconfig-arm64-chromebook-s48tj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024
10453 23:49:15.445416 [ 0.000000] random: crng init done
10454 23:49:15.452030 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10455 23:49:15.455316 [ 0.000000] efi: UEFI not found.
10456 23:49:15.462869 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10457 23:49:15.468634 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10458 23:49:15.478502 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10459 23:49:15.488892 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10460 23:49:15.494960 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10461 23:49:15.501594 [ 0.000000] printk: bootconsole [mtk8250] enabled
10462 23:49:15.508778 [ 0.000000] NUMA: No NUMA configuration found
10463 23:49:15.514992 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10464 23:49:15.518669 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10465 23:49:15.521887 [ 0.000000] Zone ranges:
10466 23:49:15.528152 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10467 23:49:15.531946 [ 0.000000] DMA32 empty
10468 23:49:15.538448 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10469 23:49:15.541175 [ 0.000000] Movable zone start for each node
10470 23:49:15.545279 [ 0.000000] Early memory node ranges
10471 23:49:15.551702 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10472 23:49:15.557929 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10473 23:49:15.565179 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10474 23:49:15.569857 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10475 23:49:15.575031 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10476 23:49:15.581657 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10477 23:49:15.640340 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10478 23:49:15.646960 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10479 23:49:15.653439 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10480 23:49:15.656942 [ 0.000000] psci: probing for conduit method from DT.
10481 23:49:15.663543 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10482 23:49:15.666642 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10483 23:49:15.673494 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10484 23:49:15.676575 [ 0.000000] psci: SMC Calling Convention v1.2
10485 23:49:15.683541 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10486 23:49:15.687096 [ 0.000000] Detected VIPT I-cache on CPU0
10487 23:49:15.693607 [ 0.000000] CPU features: detected: GIC system register CPU interface
10488 23:49:15.701005 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10489 23:49:15.707259 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10490 23:49:15.714084 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10491 23:49:15.720414 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10492 23:49:15.727468 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10493 23:49:15.733341 [ 0.000000] alternatives: applying boot alternatives
10494 23:49:15.736958 [ 0.000000] Fallback order for Node 0: 0
10495 23:49:15.743123 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10496 23:49:15.747017 [ 0.000000] Policy zone: Normal
10497 23:49:15.763896 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10498 23:49:15.773587 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10499 23:49:15.785046 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10500 23:49:15.794498 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10501 23:49:15.801345 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10502 23:49:15.804221 <6>[ 0.000000] software IO TLB: area num 8.
10503 23:49:15.861129 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10504 23:49:16.010410 <6>[ 0.000000] Memory: 7904612K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 448156K reserved, 32768K cma-reserved)
10505 23:49:16.017391 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10506 23:49:16.023891 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10507 23:49:16.027504 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10508 23:49:16.033861 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10509 23:49:16.040713 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10510 23:49:16.043437 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10511 23:49:16.053527 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10512 23:49:16.061147 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10513 23:49:16.064059 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10514 23:49:16.071361 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10515 23:49:16.074686 <6>[ 0.000000] GICv3: 608 SPIs implemented
10516 23:49:16.081192 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10517 23:49:16.084768 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10518 23:49:16.088063 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10519 23:49:16.098364 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10520 23:49:16.107932 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10521 23:49:16.121379 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10522 23:49:16.127885 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10523 23:49:16.137236 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10524 23:49:16.149874 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10525 23:49:16.157356 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10526 23:49:16.163041 <6>[ 0.009155] Console: colour dummy device 80x25
10527 23:49:16.173274 <6>[ 0.013884] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10528 23:49:16.180313 <6>[ 0.024325] pid_max: default: 32768 minimum: 301
10529 23:49:16.183672 <6>[ 0.029226] LSM: Security Framework initializing
10530 23:49:16.190128 <6>[ 0.034165] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10531 23:49:16.199795 <6>[ 0.041979] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10532 23:49:16.206716 <6>[ 0.051403] cblist_init_generic: Setting adjustable number of callback queues.
10533 23:49:16.213573 <6>[ 0.058847] cblist_init_generic: Setting shift to 3 and lim to 1.
10534 23:49:16.223581 <6>[ 0.065185] cblist_init_generic: Setting adjustable number of callback queues.
10535 23:49:16.229683 <6>[ 0.072613] cblist_init_generic: Setting shift to 3 and lim to 1.
10536 23:49:16.233367 <6>[ 0.079050] rcu: Hierarchical SRCU implementation.
10537 23:49:16.240011 <6>[ 0.084065] rcu: Max phase no-delay instances is 1000.
10538 23:49:16.246503 <6>[ 0.091086] EFI services will not be available.
10539 23:49:16.249685 <6>[ 0.096041] smp: Bringing up secondary CPUs ...
10540 23:49:16.257781 <6>[ 0.101090] Detected VIPT I-cache on CPU1
10541 23:49:16.264084 <6>[ 0.101162] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10542 23:49:16.271166 <6>[ 0.101193] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10543 23:49:16.274583 <6>[ 0.101534] Detected VIPT I-cache on CPU2
10544 23:49:16.280617 <6>[ 0.101586] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10545 23:49:16.287368 <6>[ 0.101602] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10546 23:49:16.294311 <6>[ 0.101861] Detected VIPT I-cache on CPU3
10547 23:49:16.301567 <6>[ 0.101909] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10548 23:49:16.307991 <6>[ 0.101923] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10549 23:49:16.311402 <6>[ 0.102226] CPU features: detected: Spectre-v4
10550 23:49:16.317940 <6>[ 0.102233] CPU features: detected: Spectre-BHB
10551 23:49:16.321127 <6>[ 0.102237] Detected PIPT I-cache on CPU4
10552 23:49:16.327911 <6>[ 0.102295] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10553 23:49:16.334176 <6>[ 0.102311] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10554 23:49:16.341175 <6>[ 0.102603] Detected PIPT I-cache on CPU5
10555 23:49:16.347592 <6>[ 0.102665] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10556 23:49:16.354254 <6>[ 0.102681] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10557 23:49:16.357865 <6>[ 0.102960] Detected PIPT I-cache on CPU6
10558 23:49:16.364425 <6>[ 0.103027] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10559 23:49:16.371166 <6>[ 0.103043] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10560 23:49:16.374642 <6>[ 0.103339] Detected PIPT I-cache on CPU7
10561 23:49:16.384224 <6>[ 0.103404] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10562 23:49:16.390834 <6>[ 0.103420] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10563 23:49:16.394502 <6>[ 0.103468] smp: Brought up 1 node, 8 CPUs
10564 23:49:16.397748 <6>[ 0.244953] SMP: Total of 8 processors activated.
10565 23:49:16.404447 <6>[ 0.249905] CPU features: detected: 32-bit EL0 Support
10566 23:49:16.414507 <6>[ 0.255301] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10567 23:49:16.420682 <6>[ 0.264101] CPU features: detected: Common not Private translations
10568 23:49:16.424404 <6>[ 0.270577] CPU features: detected: CRC32 instructions
10569 23:49:16.431172 <6>[ 0.275962] CPU features: detected: RCpc load-acquire (LDAPR)
10570 23:49:16.437874 <6>[ 0.281922] CPU features: detected: LSE atomic instructions
10571 23:49:16.444795 <6>[ 0.287703] CPU features: detected: Privileged Access Never
10572 23:49:16.447756 <6>[ 0.293518] CPU features: detected: RAS Extension Support
10573 23:49:16.454523 <6>[ 0.299162] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10574 23:49:16.461272 <6>[ 0.306389] CPU: All CPU(s) started at EL2
10575 23:49:16.464541 <6>[ 0.310706] alternatives: applying system-wide alternatives
10576 23:49:16.475729 <6>[ 0.321547] devtmpfs: initialized
10577 23:49:16.488455 <6>[ 0.330404] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10578 23:49:16.497925 <6>[ 0.340368] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10579 23:49:16.504750 <6>[ 0.348388] pinctrl core: initialized pinctrl subsystem
10580 23:49:16.507799 <6>[ 0.355071] DMI not present or invalid.
10581 23:49:16.514236 <6>[ 0.359483] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10582 23:49:16.524857 <6>[ 0.366339] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10583 23:49:16.531393 <6>[ 0.373924] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10584 23:49:16.541233 <6>[ 0.382143] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10585 23:49:16.544471 <6>[ 0.390382] audit: initializing netlink subsys (disabled)
10586 23:49:16.554821 <5>[ 0.396072] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10587 23:49:16.557727 <6>[ 0.396792] thermal_sys: Registered thermal governor 'step_wise'
10588 23:49:16.568458 <6>[ 0.404041] thermal_sys: Registered thermal governor 'power_allocator'
10589 23:49:16.571602 <6>[ 0.410295] cpuidle: using governor menu
10590 23:49:16.574963 <6>[ 0.421259] NET: Registered PF_QIPCRTR protocol family
10591 23:49:16.584290 <6>[ 0.426739] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10592 23:49:16.588130 <6>[ 0.433844] ASID allocator initialised with 32768 entries
10593 23:49:16.594545 <6>[ 0.440426] Serial: AMBA PL011 UART driver
10594 23:49:16.603517 <4>[ 0.449206] Trying to register duplicate clock ID: 134
10595 23:49:16.661372 <6>[ 0.510516] KASLR enabled
10596 23:49:16.675579 <6>[ 0.518286] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10597 23:49:16.682173 <6>[ 0.525304] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10598 23:49:16.689676 <6>[ 0.531795] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10599 23:49:16.695719 <6>[ 0.538801] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10600 23:49:16.702573 <6>[ 0.545286] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10601 23:49:16.709197 <6>[ 0.552292] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10602 23:49:16.715760 <6>[ 0.558778] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10603 23:49:16.722413 <6>[ 0.565785] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10604 23:49:16.725652 <6>[ 0.573300] ACPI: Interpreter disabled.
10605 23:49:16.733788 <6>[ 0.579667] iommu: Default domain type: Translated
10606 23:49:16.740791 <6>[ 0.584779] iommu: DMA domain TLB invalidation policy: strict mode
10607 23:49:16.744159 <5>[ 0.591442] SCSI subsystem initialized
10608 23:49:16.750833 <6>[ 0.595609] usbcore: registered new interface driver usbfs
10609 23:49:16.757541 <6>[ 0.601341] usbcore: registered new interface driver hub
10610 23:49:16.760284 <6>[ 0.606891] usbcore: registered new device driver usb
10611 23:49:16.767084 <6>[ 0.612982] pps_core: LinuxPPS API ver. 1 registered
10612 23:49:16.776873 <6>[ 0.618176] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10613 23:49:16.780800 <6>[ 0.627520] PTP clock support registered
10614 23:49:16.783638 <6>[ 0.631761] EDAC MC: Ver: 3.0.0
10615 23:49:16.792618 <6>[ 0.636922] FPGA manager framework
10616 23:49:16.795601 <6>[ 0.640610] Advanced Linux Sound Architecture Driver Initialized.
10617 23:49:16.797871 <6>[ 0.647386] vgaarb: loaded
10618 23:49:16.804672 <6>[ 0.650537] clocksource: Switched to clocksource arch_sys_counter
10619 23:49:16.811163 <5>[ 0.656982] VFS: Disk quotas dquot_6.6.0
10620 23:49:16.818305 <6>[ 0.661166] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10621 23:49:16.821578 <6>[ 0.668353] pnp: PnP ACPI: disabled
10622 23:49:16.829194 <6>[ 0.675098] NET: Registered PF_INET protocol family
10623 23:49:16.838847 <6>[ 0.680693] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10624 23:49:16.850873 <6>[ 0.693006] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10625 23:49:16.860582 <6>[ 0.701822] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10626 23:49:16.867082 <6>[ 0.709790] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10627 23:49:16.873675 <6>[ 0.718491] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10628 23:49:16.886074 <6>[ 0.728252] TCP: Hash tables configured (established 65536 bind 65536)
10629 23:49:16.891868 <6>[ 0.735114] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10630 23:49:16.899223 <6>[ 0.742310] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10631 23:49:16.905433 <6>[ 0.750009] NET: Registered PF_UNIX/PF_LOCAL protocol family
10632 23:49:16.912120 <6>[ 0.756161] RPC: Registered named UNIX socket transport module.
10633 23:49:16.915468 <6>[ 0.762314] RPC: Registered udp transport module.
10634 23:49:16.922388 <6>[ 0.767243] RPC: Registered tcp transport module.
10635 23:49:16.929133 <6>[ 0.772177] RPC: Registered tcp NFSv4.1 backchannel transport module.
10636 23:49:16.931996 <6>[ 0.778842] PCI: CLS 0 bytes, default 64
10637 23:49:16.935573 <6>[ 0.783180] Unpacking initramfs...
10638 23:49:16.960312 <6>[ 0.802653] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10639 23:49:16.970649 <6>[ 0.811302] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10640 23:49:16.973298 <6>[ 0.820128] kvm [1]: IPA Size Limit: 40 bits
10641 23:49:16.980525 <6>[ 0.824660] kvm [1]: GICv3: no GICV resource entry
10642 23:49:16.983285 <6>[ 0.829678] kvm [1]: disabling GICv2 emulation
10643 23:49:16.989873 <6>[ 0.834365] kvm [1]: GIC system register CPU interface enabled
10644 23:49:16.993721 <6>[ 0.840532] kvm [1]: vgic interrupt IRQ18
10645 23:49:17.000504 <6>[ 0.844886] kvm [1]: VHE mode initialized successfully
10646 23:49:17.007247 <5>[ 0.851367] Initialise system trusted keyrings
10647 23:49:17.013535 <6>[ 0.856173] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10648 23:49:17.020131 <6>[ 0.866171] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10649 23:49:17.027022 <5>[ 0.872549] NFS: Registering the id_resolver key type
10650 23:49:17.030110 <5>[ 0.877846] Key type id_resolver registered
10651 23:49:17.037124 <5>[ 0.882262] Key type id_legacy registered
10652 23:49:17.043832 <6>[ 0.886546] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10653 23:49:17.050185 <6>[ 0.893467] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10654 23:49:17.056839 <6>[ 0.901182] 9p: Installing v9fs 9p2000 file system support
10655 23:49:17.093046 <5>[ 0.938648] Key type asymmetric registered
10656 23:49:17.095848 <5>[ 0.942980] Asymmetric key parser 'x509' registered
10657 23:49:17.105975 <6>[ 0.948120] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10658 23:49:17.109521 <6>[ 0.955733] io scheduler mq-deadline registered
10659 23:49:17.112673 <6>[ 0.960511] io scheduler kyber registered
10660 23:49:17.131430 <6>[ 0.977425] EINJ: ACPI disabled.
10661 23:49:17.164425 <4>[ 1.003531] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10662 23:49:17.174540 <4>[ 1.014143] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10663 23:49:17.189152 <6>[ 1.034893] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10664 23:49:17.197078 <6>[ 1.042810] printk: console [ttyS0] disabled
10665 23:49:17.225416 <6>[ 1.067435] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10666 23:49:17.231487 <6>[ 1.076906] printk: console [ttyS0] enabled
10667 23:49:17.235162 <6>[ 1.076906] printk: console [ttyS0] enabled
10668 23:49:17.241886 <6>[ 1.085801] printk: bootconsole [mtk8250] disabled
10669 23:49:17.244935 <6>[ 1.085801] printk: bootconsole [mtk8250] disabled
10670 23:49:17.251272 <6>[ 1.096810] SuperH (H)SCI(F) driver initialized
10671 23:49:17.254488 <6>[ 1.102099] msm_serial: driver initialized
10672 23:49:17.268581 <6>[ 1.110962] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10673 23:49:17.278275 <6>[ 1.119505] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10674 23:49:17.285306 <6>[ 1.128047] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10675 23:49:17.295350 <6>[ 1.136676] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10676 23:49:17.301350 <6>[ 1.145385] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10677 23:49:17.311690 <6>[ 1.154104] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10678 23:49:17.321841 <6>[ 1.162644] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10679 23:49:17.327992 <6>[ 1.171438] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10680 23:49:17.338696 <6>[ 1.179982] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10681 23:49:17.349931 <6>[ 1.195595] loop: module loaded
10682 23:49:17.356338 <6>[ 1.201416] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10683 23:49:17.378647 <4>[ 1.224577] mtk-pmic-keys: Failed to locate of_node [id: -1]
10684 23:49:17.385887 <6>[ 1.231346] megasas: 07.719.03.00-rc1
10685 23:49:17.394725 <6>[ 1.240902] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10686 23:49:17.404288 <6>[ 1.249903] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10687 23:49:17.421106 <6>[ 1.266427] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10688 23:49:17.477187 <6>[ 1.316474] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10689 23:49:19.636231 <6>[ 3.482972] Freeing initrd memory: 59572K
10690 23:49:19.648393 <6>[ 3.494867] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10691 23:49:19.659672 <6>[ 3.505730] tun: Universal TUN/TAP device driver, 1.6
10692 23:49:19.662769 <6>[ 3.511787] thunder_xcv, ver 1.0
10693 23:49:19.666222 <6>[ 3.515291] thunder_bgx, ver 1.0
10694 23:49:19.669138 <6>[ 3.518789] nicpf, ver 1.0
10695 23:49:19.679851 <6>[ 3.522783] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10696 23:49:19.683587 <6>[ 3.530258] hns3: Copyright (c) 2017 Huawei Corporation.
10697 23:49:19.689787 <6>[ 3.535844] hclge is initializing
10698 23:49:19.692946 <6>[ 3.539424] e1000: Intel(R) PRO/1000 Network Driver
10699 23:49:19.700070 <6>[ 3.544552] e1000: Copyright (c) 1999-2006 Intel Corporation.
10700 23:49:19.703417 <6>[ 3.550566] e1000e: Intel(R) PRO/1000 Network Driver
10701 23:49:19.709637 <6>[ 3.555781] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10702 23:49:19.715980 <6>[ 3.561965] igb: Intel(R) Gigabit Ethernet Network Driver
10703 23:49:19.722990 <6>[ 3.567615] igb: Copyright (c) 2007-2014 Intel Corporation.
10704 23:49:19.729502 <6>[ 3.573450] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10705 23:49:19.736396 <6>[ 3.579968] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10706 23:49:19.739802 <6>[ 3.586428] sky2: driver version 1.30
10707 23:49:19.745931 <6>[ 3.591348] usbcore: registered new device driver r8152-cfgselector
10708 23:49:19.752821 <6>[ 3.597884] usbcore: registered new interface driver r8152
10709 23:49:19.759601 <6>[ 3.603698] VFIO - User Level meta-driver version: 0.3
10710 23:49:19.765852 <6>[ 3.611906] usbcore: registered new interface driver usb-storage
10711 23:49:19.772531 <6>[ 3.618348] usbcore: registered new device driver onboard-usb-hub
10712 23:49:19.781379 <6>[ 3.627449] mt6397-rtc mt6359-rtc: registered as rtc0
10713 23:49:19.791307 <6>[ 3.632910] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T23:49:19 UTC (1717544959)
10714 23:49:19.794023 <6>[ 3.642468] i2c_dev: i2c /dev entries driver
10715 23:49:19.811604 <6>[ 3.654276] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10716 23:49:19.817744 <4>[ 3.662998] cpu cpu0: supply cpu not found, using dummy regulator
10717 23:49:19.824843 <4>[ 3.669421] cpu cpu1: supply cpu not found, using dummy regulator
10718 23:49:19.831345 <4>[ 3.675830] cpu cpu2: supply cpu not found, using dummy regulator
10719 23:49:19.838038 <4>[ 3.682247] cpu cpu3: supply cpu not found, using dummy regulator
10720 23:49:19.844937 <4>[ 3.688644] cpu cpu4: supply cpu not found, using dummy regulator
10721 23:49:19.851788 <4>[ 3.695041] cpu cpu5: supply cpu not found, using dummy regulator
10722 23:49:19.858865 <4>[ 3.701436] cpu cpu6: supply cpu not found, using dummy regulator
10723 23:49:19.861658 <4>[ 3.707847] cpu cpu7: supply cpu not found, using dummy regulator
10724 23:49:19.883464 <6>[ 3.729486] cpu cpu0: EM: created perf domain
10725 23:49:19.886717 <6>[ 3.734399] cpu cpu4: EM: created perf domain
10726 23:49:19.893679 <6>[ 3.739973] sdhci: Secure Digital Host Controller Interface driver
10727 23:49:19.900592 <6>[ 3.746405] sdhci: Copyright(c) Pierre Ossman
10728 23:49:19.907011 <6>[ 3.751351] Synopsys Designware Multimedia Card Interface Driver
10729 23:49:19.913492 <6>[ 3.757987] sdhci-pltfm: SDHCI platform and OF driver helper
10730 23:49:19.917189 <6>[ 3.758022] mmc0: CQHCI version 5.10
10731 23:49:19.923537 <6>[ 3.768319] ledtrig-cpu: registered to indicate activity on CPUs
10732 23:49:19.930170 <6>[ 3.775316] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10733 23:49:19.937238 <6>[ 3.782365] usbcore: registered new interface driver usbhid
10734 23:49:19.940459 <6>[ 3.788187] usbhid: USB HID core driver
10735 23:49:19.946939 <6>[ 3.792389] spi_master spi0: will run message pump with realtime priority
10736 23:49:19.989233 <6>[ 3.829041] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10737 23:49:20.008422 <6>[ 3.844472] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10738 23:49:20.012080 <6>[ 3.858486] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x15414
10739 23:49:20.018511 <6>[ 3.864732] cros-ec-spi spi0.0: Chrome EC device registered
10740 23:49:20.025464 <6>[ 3.870756] mmc0: Command Queue Engine enabled
10741 23:49:20.032160 <6>[ 3.875523] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10742 23:49:20.035269 <6>[ 3.883254] mmcblk0: mmc0:0001 DA4128 116 GiB
10743 23:49:20.045605 <6>[ 3.892011] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10744 23:49:20.053457 <6>[ 3.899425] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10745 23:49:20.060155 <6>[ 3.905588] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10746 23:49:20.067184 <6>[ 3.911803] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10747 23:49:20.076450 <6>[ 3.911904] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10748 23:49:20.083404 <6>[ 3.928905] NET: Registered PF_PACKET protocol family
10749 23:49:20.087183 <6>[ 3.934296] 9pnet: Installing 9P2000 support
10750 23:49:20.093731 <5>[ 3.938867] Key type dns_resolver registered
10751 23:49:20.097053 <6>[ 3.943822] registered taskstats version 1
10752 23:49:20.103654 <5>[ 3.948207] Loading compiled-in X.509 certificates
10753 23:49:20.132882 <4>[ 3.972010] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10754 23:49:20.142631 <4>[ 3.982928] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10755 23:49:20.156444 <6>[ 4.003016] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10756 23:49:20.163720 <6>[ 4.009921] xhci-mtk 11200000.usb: xHCI Host Controller
10757 23:49:20.170261 <6>[ 4.015477] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10758 23:49:20.180778 <6>[ 4.023370] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10759 23:49:20.187005 <6>[ 4.032820] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10760 23:49:20.194356 <6>[ 4.038990] xhci-mtk 11200000.usb: xHCI Host Controller
10761 23:49:20.200267 <6>[ 4.044486] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10762 23:49:20.207411 <6>[ 4.052143] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10763 23:49:20.213901 <6>[ 4.059994] hub 1-0:1.0: USB hub found
10764 23:49:20.217005 <6>[ 4.064020] hub 1-0:1.0: 1 port detected
10765 23:49:20.223911 <6>[ 4.068314] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10766 23:49:20.230926 <6>[ 4.077048] hub 2-0:1.0: USB hub found
10767 23:49:20.234021 <6>[ 4.081070] hub 2-0:1.0: 1 port detected
10768 23:49:20.241582 <6>[ 4.088102] mtk-msdc 11f70000.mmc: Got CD GPIO
10769 23:49:20.255304 <6>[ 4.097843] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10770 23:49:20.261982 <6>[ 4.105877] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10771 23:49:20.271540 <4>[ 4.113817] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10772 23:49:20.281544 <6>[ 4.123382] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10773 23:49:20.288490 <6>[ 4.131459] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10774 23:49:20.294687 <6>[ 4.139477] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10775 23:49:20.305351 <6>[ 4.147397] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10776 23:49:20.311913 <6>[ 4.155216] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10777 23:49:20.321445 <6>[ 4.163034] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10778 23:49:20.331453 <6>[ 4.173460] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10779 23:49:20.338652 <6>[ 4.181820] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10780 23:49:20.348337 <6>[ 4.190166] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10781 23:49:20.354568 <6>[ 4.198505] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10782 23:49:20.364404 <6>[ 4.206843] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10783 23:49:20.371328 <6>[ 4.215184] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10784 23:49:20.381335 <6>[ 4.223522] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10785 23:49:20.388008 <6>[ 4.231860] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10786 23:49:20.397966 <6>[ 4.240204] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10787 23:49:20.404195 <6>[ 4.248542] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10788 23:49:20.414625 <6>[ 4.256879] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10789 23:49:20.420699 <6>[ 4.265217] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10790 23:49:20.431216 <6>[ 4.273555] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10791 23:49:20.437623 <6>[ 4.281894] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10792 23:49:20.447784 <6>[ 4.290232] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10793 23:49:20.454777 <6>[ 4.298976] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10794 23:49:20.460951 <6>[ 4.306132] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10795 23:49:20.467593 <6>[ 4.312887] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10796 23:49:20.474561 <6>[ 4.319644] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10797 23:49:20.481248 <6>[ 4.326577] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10798 23:49:20.491219 <6>[ 4.333427] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10799 23:49:20.501692 <6>[ 4.342557] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10800 23:49:20.511216 <6>[ 4.351676] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10801 23:49:20.517625 <6>[ 4.360973] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10802 23:49:20.527438 <6>[ 4.370442] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10803 23:49:20.537371 <6>[ 4.379909] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10804 23:49:20.547336 <6>[ 4.389029] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10805 23:49:20.557653 <6>[ 4.398495] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10806 23:49:20.564606 <6>[ 4.407623] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10807 23:49:20.573797 <6>[ 4.416917] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10808 23:49:20.587908 <6>[ 4.427076] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10809 23:49:20.597860 <6>[ 4.438732] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10810 23:49:20.647643 <6>[ 4.490788] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10811 23:49:20.802296 <6>[ 4.648548] hub 1-1:1.0: USB hub found
10812 23:49:20.805342 <6>[ 4.653071] hub 1-1:1.0: 4 ports detected
10813 23:49:20.816131 <6>[ 4.662080] hub 1-1:1.0: USB hub found
10814 23:49:20.819453 <6>[ 4.666418] hub 1-1:1.0: 4 ports detected
10815 23:49:20.927624 <6>[ 4.770978] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10816 23:49:20.953898 <6>[ 4.800279] hub 2-1:1.0: USB hub found
10817 23:49:20.957212 <6>[ 4.804752] hub 2-1:1.0: 3 ports detected
10818 23:49:20.965905 <6>[ 4.812702] hub 2-1:1.0: USB hub found
10819 23:49:20.969426 <6>[ 4.817148] hub 2-1:1.0: 3 ports detected
10820 23:49:21.143262 <6>[ 4.986819] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10821 23:49:21.276007 <6>[ 5.122786] hub 1-1.4:1.0: USB hub found
10822 23:49:21.279502 <6>[ 5.127455] hub 1-1.4:1.0: 2 ports detected
10823 23:49:21.289283 <6>[ 5.136115] hub 1-1.4:1.0: USB hub found
10824 23:49:21.292696 <6>[ 5.140651] hub 1-1.4:1.0: 2 ports detected
10825 23:49:21.360176 <6>[ 5.203066] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10826 23:49:21.467870 <6>[ 5.311488] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10827 23:49:21.505264 <4>[ 5.348624] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10828 23:49:21.515005 <4>[ 5.357740] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10829 23:49:21.553617 <6>[ 5.400404] r8152 2-1.3:1.0 eth0: v1.12.13
10830 23:49:21.590858 <6>[ 5.434859] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10831 23:49:21.782972 <6>[ 5.626875] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10832 23:49:23.207528 <6>[ 7.054214] r8152 2-1.3:1.0 eth0: carrier on
10833 23:49:23.404733 <5>[ 7.074609] Sending DHCP requests ., OK
10834 23:49:23.410626 <6>[ 7.254998] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10835 23:49:23.414141 <6>[ 7.263292] IP-Config: Complete:
10836 23:49:23.427693 <6>[ 7.266791] device=eth0, hwaddr=00:24:32:30:78:52, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10837 23:49:23.434305 <6>[ 7.277497] host=mt8192-asurada-spherion-r0-cbg-3, domain=lava-rack, nis-domain=(none)
10838 23:49:23.440580 <6>[ 7.286115] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10839 23:49:23.447520 <6>[ 7.286125] nameserver0=192.168.201.1
10840 23:49:23.451048 <6>[ 7.298291] clk: Disabling unused clocks
10841 23:49:23.453733 <6>[ 7.303917] ALSA device list:
10842 23:49:23.460332 <6>[ 7.307203] No soundcards found.
10843 23:49:23.468286 <6>[ 7.314748] Freeing unused kernel memory: 8512K
10844 23:49:23.471712 <6>[ 7.319652] Run /init as init process
10845 23:49:23.501418 <6>[ 7.348238] NET: Registered PF_INET6 protocol family
10846 23:49:23.508454 <6>[ 7.355037] Segment Routing with IPv6
10847 23:49:23.511443 <6>[ 7.359006] In-situ OAM (IOAM) with IPv6
10848 23:49:23.552377 <30>[ 7.372159] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10849 23:49:23.558566 <30>[ 7.405215] systemd[1]: Detected architecture arm64.
10850 23:49:23.559087
10851 23:49:23.564999 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10852 23:49:23.565500
10853 23:49:23.580479 <30>[ 7.426903] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10854 23:49:23.696915 <30>[ 7.539949] systemd[1]: Queued start job for default target graphical.target.
10855 23:49:23.749467 <30>[ 7.592645] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10856 23:49:23.755788 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10857 23:49:23.776711 <30>[ 7.620028] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10858 23:49:23.783425 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10859 23:49:23.804870 <30>[ 7.647899] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10860 23:49:23.814984 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10861 23:49:23.833029 <30>[ 7.676403] systemd[1]: Created slice user.slice - User and Session Slice.
10862 23:49:23.839472 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10863 23:49:23.863017 <30>[ 7.703106] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10864 23:49:23.869634 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10865 23:49:23.891530 <30>[ 7.731045] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10866 23:49:23.897626 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10867 23:49:23.925529 <30>[ 7.759317] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10868 23:49:23.936646 <30>[ 7.779203] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10869 23:49:23.942356 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10870 23:49:23.959738 <30>[ 7.803222] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10871 23:49:23.966396 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10872 23:49:23.988076 <30>[ 7.831340] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10873 23:49:23.997991 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10874 23:49:24.012511 <30>[ 7.859330] systemd[1]: Reached target paths.target - Path Units.
10875 23:49:24.022612 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10876 23:49:24.040424 <30>[ 7.883305] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10877 23:49:24.046855 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10878 23:49:24.060659 <30>[ 7.906823] systemd[1]: Reached target slices.target - Slice Units.
10879 23:49:24.070366 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10880 23:49:24.084722 <30>[ 7.931313] systemd[1]: Reached target swap.target - Swaps.
10881 23:49:24.091311 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10882 23:49:24.112209 <30>[ 7.955332] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10883 23:49:24.122130 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10884 23:49:24.140258 <30>[ 7.983191] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10885 23:49:24.149678 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10886 23:49:24.168954 <30>[ 8.012273] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10887 23:49:24.178719 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10888 23:49:24.195927 <30>[ 8.039418] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10889 23:49:24.205787 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10890 23:49:24.224904 <30>[ 8.068137] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10891 23:49:24.231036 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10892 23:49:24.252365 <30>[ 8.095515] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10893 23:49:24.261899 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10894 23:49:24.280101 <30>[ 8.123311] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10895 23:49:24.290357 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10896 23:49:24.347460 <30>[ 8.191055] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10897 23:49:24.354359 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10898 23:49:24.374854 <30>[ 8.218168] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10899 23:49:24.381102 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10900 23:49:24.401471 <30>[ 8.245033] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10901 23:49:24.409994 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10902 23:49:24.434057 <30>[ 8.271070] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10903 23:49:24.464119 <30>[ 8.307487] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10904 23:49:24.473986 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10905 23:49:24.496582 <30>[ 8.339964] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10906 23:49:24.503647 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10907 23:49:24.528525 <30>[ 8.372074] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10908 23:49:24.539102 Startin<6>[ 8.381457] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10909 23:49:24.545230 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10910 23:49:24.608255 <30>[ 8.451680] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10911 23:49:24.615288 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10912 23:49:24.640494 <30>[ 8.484017] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10913 23:49:24.647028 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10914 23:49:24.671820 <30>[ 8.515272] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10915 23:49:24.678644 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10916 23:49:24.703752 <30>[ 8.547007] systemd[1]: Starting systemd-journald.service - Journal Service...
10917 23:49:24.710315 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10918 23:49:24.729976 <30>[ 8.573600] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10919 23:49:24.736675 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10920 23:49:24.761997 <30>[ 8.601948] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10921 23:49:24.768182 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10922 23:49:24.791818 <30>[ 8.634934] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10923 23:49:24.801954 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10924 23:49:24.856364 <30>[ 8.699784] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10925 23:49:24.863039 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10926 23:49:24.888739 <30>[ 8.731677] systemd[1]: Started systemd-journald.service - Journal Service.
10927 23:49:24.894787 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10928 23:49:24.914037 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10929 23:49:24.932193 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10930 23:49:24.947662 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10931 23:49:24.965337 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10932 23:49:24.986296 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10933 23:49:25.010057 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10934 23:49:25.030761 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10935 23:49:25.050575 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10936 23:49:25.075022 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10937 23:49:25.095966 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10938 23:49:25.113962 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10939 23:49:25.134322 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10940 23:49:25.140914 See 'systemctl status systemd-remount-fs.service' for details.
10941 23:49:25.150983 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10942 23:49:25.170706 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10943 23:49:25.216558 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10944 23:49:25.236045 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10945 23:49:25.257168 <46>[ 9.100550] systemd-journald[193]: Received client request to flush runtime journal.
10946 23:49:25.263512 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10947 23:49:25.288509 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10948 23:49:25.311904 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10949 23:49:25.337554 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10950 23:49:25.356654 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10951 23:49:25.377146 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10952 23:49:25.396640 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10953 23:49:25.416804 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10954 23:49:25.464664 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10955 23:49:25.487463 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10956 23:49:25.507620 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10957 23:49:25.524099 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10958 23:49:25.592124 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10959 23:49:25.617278 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10960 23:49:25.642574 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10961 23:49:25.663001 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10962 23:49:25.720339 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10963 23:49:25.886232 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10964 23:49:25.914407 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10965 23:49:25.957870 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10966 23:49:25.984866 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10967 23:49:26.004342 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10968 23:49:26.024290 [[0;32m OK [<6>[ 9.869170] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10969 23:49:26.034395 0m] Started [0;<6>[ 9.877255] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10970 23:49:26.043990 1;39msystemd-tmp<6>[ 9.887040] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10971 23:49:26.050208 files-c… Cleanup of Temporary Directories.
10972 23:49:26.063908 <3>[ 9.907121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10973 23:49:26.070590 <6>[ 9.912347] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10974 23:49:26.077088 <3>[ 9.915489] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10975 23:49:26.087424 <4>[ 9.919665] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10976 23:49:26.093547 <4>[ 9.927690] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10977 23:49:26.100423 <3>[ 9.930766] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10978 23:49:26.107370 <6>[ 9.949912] remoteproc remoteproc0: scp is available
10979 23:49:26.110608 <6>[ 9.958729] remoteproc remoteproc0: powering up scp
10980 23:49:26.120275 <3>[ 9.960689] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10981 23:49:26.127400 <6>[ 9.963880] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10982 23:49:26.136921 <3>[ 9.971962] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10983 23:49:26.143793 <6>[ 9.980408] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10984 23:49:26.149809 <3>[ 9.988451] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10985 23:49:26.160094 [[0;32m OK [<3>[ 10.002184] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10986 23:49:26.166160 <3>[ 10.011652] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10987 23:49:26.180164 0m] Reached target [0;1;39mtime<3>[ 10.021692] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10988 23:49:26.186297 -set.target[0m <6>[ 10.028070] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10989 23:49:26.196590 - System Time Se<3>[ 10.033004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10990 23:49:26.197310 t.
10991 23:49:26.202725 <6>[ 10.039106] pci_bus 0000:00: root bus resource [bus 00-ff]
10992 23:49:26.209640 <6>[ 10.039130] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10993 23:49:26.215760 <6>[ 10.042084] mc: Linux media interface: v0.10
10994 23:49:26.222909 <6>[ 10.042351] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10995 23:49:26.229645 <3>[ 10.048516] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10996 23:49:26.239890 <3>[ 10.048524] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10997 23:49:26.246315 <3>[ 10.063088] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10998 23:49:26.256590 <6>[ 10.066775] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10999 23:49:26.263143 <3>[ 10.074131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11000 23:49:26.273693 <3>[ 10.074142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11001 23:49:26.279908 <3>[ 10.074151] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11002 23:49:26.286993 <6>[ 10.082604] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
11003 23:49:26.293303 <6>[ 10.083534] videodev: Linux video capture interface: v2.00
11004 23:49:26.301035 <3>[ 10.090303] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11005 23:49:26.310718 <4>[ 10.090389] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
11006 23:49:26.314398 <4>[ 10.090389] Fallback method does not support PEC.
11007 23:49:26.321536 <6>[ 10.098400] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
11008 23:49:26.331836 <6>[ 10.099750] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
11009 23:49:26.338601 <3>[ 10.107520] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11010 23:49:26.348460 <6>[ 10.115038] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
11011 23:49:26.355084 <6>[ 10.115048] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
11012 23:49:26.362656 <3>[ 10.115348] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11013 23:49:26.369474 <6>[ 10.116492] pci 0000:00:00.0: supports D1 D2
11014 23:49:26.375930 <6>[ 10.124499] remoteproc remoteproc0: remote processor scp is now up
11015 23:49:26.383107 <6>[ 10.132527] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11016 23:49:26.390431 <6>[ 10.141178] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
11017 23:49:26.400196 <6>[ 10.145584] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
11018 23:49:26.411306 <6>[ 10.152995] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
11019 23:49:26.417616 <3>[ 10.153983] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11020 23:49:26.427354 <3>[ 10.154791] power_supply sbs-5-000b: driver failed to report `current_avg' property: -6
11021 23:49:26.430614 <6>[ 10.166511] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
11022 23:49:26.441426 <3>[ 10.178305] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11023 23:49:26.447673 <6>[ 10.183188] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
11024 23:49:26.457990 <6>[ 10.203384] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
11025 23:49:26.464470 <6>[ 10.207554] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
11026 23:49:26.471140 <6>[ 10.207574] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
11027 23:49:26.475037 <6>[ 10.207700] pci 0000:01:00.0: supports D1 D2
11028 23:49:26.478966 <6>[ 10.216353] Bluetooth: Core ver 2.22
11029 23:49:26.488719 <6>[ 10.218781] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
11030 23:49:26.495332 <6>[ 10.220185] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
11031 23:49:26.505897 <3>[ 10.225697] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11032 23:49:26.512265 <3>[ 10.226506] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
11033 23:49:26.519265 <6>[ 10.226688] NET: Registered PF_BLUETOOTH protocol family
11034 23:49:26.525656 <6>[ 10.227399] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11035 23:49:26.536667 <6>[ 10.228451] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11036 23:49:26.543484 <6>[ 10.228571] usbcore: registered new interface driver uvcvideo
11037 23:49:26.550181 <6>[ 10.231978] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
11038 23:49:26.560266 <6>[ 10.232026] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
11039 23:49:26.567074 <6>[ 10.232032] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11040 23:49:26.574463 <6>[ 10.232048] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11041 23:49:26.584225 <6>[ 10.232063] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11042 23:49:26.591180 <6>[ 10.232079] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11043 23:49:26.594199 <6>[ 10.232091] pci 0000:00:00.0: PCI bridge to [bus 01]
11044 23:49:26.604937 <6>[ 10.232098] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11045 23:49:26.611258 <6>[ 10.232458] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11046 23:49:26.617963 <6>[ 10.233965] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
11047 23:49:26.624826 <3>[ 10.239648] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11048 23:49:26.631081 <6>[ 10.243567] Bluetooth: HCI device and connection manager initialized
11049 23:49:26.638432 <6>[ 10.243583] Bluetooth: HCI socket layer initialized
11050 23:49:26.641526 <6>[ 10.243593] Bluetooth: L2CAP socket layer initialized
11051 23:49:26.648214 <6>[ 10.252107] pcieport 0000:00:00.0: AER: enabled with IRQ 282
11052 23:49:26.654574 <6>[ 10.260889] Bluetooth: SCO socket layer initialized
11053 23:49:26.661141 <6>[ 10.261437] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11054 23:49:26.667414 <3>[ 10.262112] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11055 23:49:26.677707 <3>[ 10.287325] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11056 23:49:26.684029 <5>[ 10.287531] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11057 23:49:26.690601 <5>[ 10.303180] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11058 23:49:26.700813 <3>[ 10.329148] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11059 23:49:26.710615 <5>[ 10.332640] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11060 23:49:26.713815 <6>[ 10.341238] usbcore: registered new interface driver btusb
11061 23:49:26.727583 <4>[ 10.342391] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11062 23:49:26.731018 <3>[ 10.342400] Bluetooth: hci0: Failed to load firmware file (-2)
11063 23:49:26.736922 <3>[ 10.342403] Bluetooth: hci0: Failed to set up firmware (-2)
11064 23:49:26.747331 <4>[ 10.342407] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11065 23:49:26.757287 <4>[ 10.347340] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11066 23:49:26.764222 <6>[ 10.438218] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11067 23:49:26.770887 <6>[ 10.443025] cfg80211: failed to load regulatory.db
11068 23:49:26.774005 <6>[ 10.448282] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11069 23:49:26.783825 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11070 23:49:26.798992 <6>[ 10.645824] mt7921e 0000:01:00.0: ASIC revision: 79610010
11071 23:49:26.806169 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11072 23:49:26.823356 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11073 23:49:26.843359 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11074 23:49:26.859587 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11075 23:49:26.902568 <6>[ 10.746632] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11076 23:49:26.906506 <6>[ 10.746632]
11077 23:49:26.913868 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11078 23:49:26.956205 Startin<46>[ 10.786917] systemd-journald[193]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.0 (1536 of 2047 items, 524288 file size, 341 bytes per hash table item), suggesting rotation.
11079 23:49:26.973556 g [0;1;39msyste<46>[ 10.809509] systemd-journald[193]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11080 23:49:26.979506 md-logind.se…ice[0m - User Login Management...
11081 23:49:27.003922 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11082 23:49:27.022561 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11083 23:49:27.063261 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11084 23:49:27.125161 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11085 23:49:27.145952 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11086 23:49:27.164366 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11087 23:49:27.173665 <6>[ 11.016061] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11088 23:49:27.184768 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11089 23:49:27.230311 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11090 23:49:27.250310 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11091 23:49:27.269574 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11092 23:49:27.285378 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11093 23:49:27.305669 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11094 23:49:27.367827 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11095 23:49:27.393299 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11096 23:49:27.418646 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11097 23:49:27.485911 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11098 23:49:27.506605 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11099 23:49:27.530972 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11100 23:49:27.567429
11101 23:49:27.571478 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11102 23:49:27.572032
11103 23:49:27.574312 debian-bookworm-arm64 login: root (automatic login)
11104 23:49:27.574837
11105 23:49:27.592946 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024 aarch64
11106 23:49:27.593547
11107 23:49:27.599660 The programs included with the Debian GNU/Linux system are free software;
11108 23:49:27.606002 the exact distribution terms for each program are described in the
11109 23:49:27.610153 individual files in /usr/share/doc/*/copyright.
11110 23:49:27.610609
11111 23:49:27.616279 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11112 23:49:27.619895 permitted by applicable law.
11113 23:49:27.621516 Matched prompt #10: / #
11115 23:49:27.622610 Setting prompt string to ['/ #']
11116 23:49:27.623094 end: 2.2.5.1 login-action (duration 00:00:12) [common]
11118 23:49:27.624359 end: 2.2.5 auto-login-action (duration 00:00:12) [common]
11119 23:49:27.624837 start: 2.2.6 expect-shell-connection (timeout 00:02:37) [common]
11120 23:49:27.625267 Setting prompt string to ['/ #']
11121 23:49:27.625603 Forcing a shell prompt, looking for ['/ #']
11123 23:49:27.676529 / #
11124 23:49:27.677220 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11125 23:49:27.677661 Waiting using forced prompt support (timeout 00:02:30)
11126 23:49:27.683050
11127 23:49:27.683982 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11128 23:49:27.684503 start: 2.2.7 export-device-env (timeout 00:02:37) [common]
11129 23:49:27.685028 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11130 23:49:27.685500 end: 2.2 depthcharge-retry (duration 00:02:23) [common]
11131 23:49:27.685956 end: 2 depthcharge-action (duration 00:02:23) [common]
11132 23:49:27.686416 start: 3 lava-test-retry (timeout 00:07:12) [common]
11133 23:49:27.686877 start: 3.1 lava-test-shell (timeout 00:07:12) [common]
11134 23:49:27.687280 Using namespace: common
11136 23:49:27.788449 / # #
11137 23:49:27.789125 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11138 23:49:27.795128 #
11139 23:49:27.796011 Using /lava-14172991
11141 23:49:27.897175 / # export SHELL=/bin/sh
11142 23:49:27.903762 export SHELL=/bin/sh
11144 23:49:28.005294 / # . /lava-14172991/environment
11145 23:49:28.011573 . /lava-14172991/environment
11147 23:49:28.113068 / # /lava-14172991/bin/lava-test-runner /lava-14172991/0
11148 23:49:28.113626 Test shell timeout: 10s (minimum of the action and connection timeout)
11149 23:49:28.115044 <6>[ 11.885718] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11150 23:49:28.119324 /lava-14172991/bin/lava-test-runner /lava-14172991/0
11151 23:49:28.161548 + export TESTRUN<8>[ 11.990409] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 14172991_1.5.2.3.1>
11152 23:49:28.162113 _ID=0_igt-gpu-panfrost
11153 23:49:28.162485 + cd /lava-14172991/0/tests/0_igt-gpu-panfrost
11154 23:49:28.162831 + cat uuid
11155 23:49:28.163247 + UUID=14172991_1.5.2.3.1
11156 23:49:28.163585 + set +x
11157 23:49:28.164204 Received signal: <STARTRUN> 0_igt-gpu-panfrost 14172991_1.5.2.3.1
11158 23:49:28.164581 Starting test lava.0_igt-gpu-panfrost (14172991_1.5.2.3.1)
11159 23:49:28.165012 Skipping test definition patterns.
11160 23:49:28.168414 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param <8>[ 12.014912] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11161 23:49:28.169142 Received signal: <TESTSET> START panfrost_gem_new
11162 23:49:28.169543 Starting test_set panfrost_gem_new
11163 23:49:28.171836 panfrost_prime panfrost_submit
11164 23:49:28.190165 <14>[ 12.037226] [IGT] panfrost_gem_new: executing
11165 23:49:28.196686 IGT-Version: 1.28-ga44ebfe (aarc<14>[ 12.044587] [IGT] panfrost_gem_new: exiting, ret=77
11166 23:49:28.200627 h64) (Linux: 6.1.92-cip22 aarch64)
11167 23:49:28.212942 Using IGT_SRANDOM=1717544967 for randomisati<8>[ 12.055965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11168 23:49:28.213512 on
11169 23:49:28.214283 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11171 23:49:28.219576 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11172 23:49:28.223259 Test requirement: !(fd<0)
11173 23:49:28.230150 No known gpu found for chipset flags 0x32 (panf<14>[ 12.077526] [IGT] panfrost_gem_new: executing
11174 23:49:28.230710 rost)
11175 23:49:28.239815 Last errno: 2, No such fi<14>[ 12.085129] [IGT] panfrost_gem_new: exiting, ret=77
11176 23:49:28.240268 le or directory
11177 23:49:28.243365 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11178 23:49:28.249703 IG<8>[ 12.095733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11179 23:49:28.250518 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11181 23:49:28.256554 T-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11182 23:49:28.261540 Using IGT_SRANDOM=1717544967 for randomisation
11183 23:49:28.269838 Test requirement not met in function drm_open_<14>[ 12.116683] [IGT] panfrost_gem_new: executing
11184 23:49:28.276627 driver, file ../lib/drmtest.c:69<14>[ 12.123907] [IGT] panfrost_gem_new: exiting, ret=77
11185 23:49:28.277235 4:
11186 23:49:28.279722 Test requirement: !(fd<0)
11187 23:49:28.293366 No known gpu found for chipset flags 0x32 (panfro<8>[ 12.135540] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11188 23:49:28.293927 st)
11189 23:49:28.294573 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11191 23:49:28.296261 Last errno: 2, No such file or directory
11192 23:49:28.299723 <8>[ 12.146861] <LAVA_SIGNAL_TESTSET STOP>
11193 23:49:28.300568 Received signal: <TESTSET> STOP
11194 23:49:28.300964 Closing test_set panfrost_gem_new
11195 23:49:28.303599 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11196 23:49:28.309850 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11197 23:49:28.312733 Using IGT_SRANDOM=1717544967 for randomisation
11198 23:49:28.326757 Test requirement not met in function drm_open_driver, file ../lib/d<8>[ 12.170688] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11199 23:49:28.327319 rmtest.c:694:
11200 23:49:28.327962 Received signal: <TESTSET> START panfrost_get_param
11201 23:49:28.328338 Starting test_set panfrost_get_param
11202 23:49:28.329268 Test requirement: !(fd<0)
11203 23:49:28.333064 No known gpu found for chipset flags 0x32 (panfrost)
11204 23:49:28.336169 Last errno: 2, No such file or directory
11205 23:49:28.343237 [1mSubtest gem-new-ze<14>[ 12.191019] [IGT] panfrost_get_param: executing
11206 23:49:28.346197 roed: SKIP (0.000s)[0m
11207 23:49:28.353844 IGT-Ver<14>[ 12.198625] [IGT] panfrost_get_param: exiting, ret=77
11208 23:49:28.355833 sion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11209 23:49:28.366446 Usi<8>[ 12.209929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11210 23:49:28.367281 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11212 23:49:28.369397 ng IGT_SRANDOM=1717544968 for randomisation
11213 23:49:28.376356 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11214 23:49:28.379711 Test requirement: !(fd<0)
11215 23:49:28.383087 No kno<14>[ 12.230631] [IGT] panfrost_get_param: executing
11216 23:49:28.392538 wn gpu found for chipset flags 0<14>[ 12.238138] [IGT] panfrost_get_param: exiting, ret=77
11217 23:49:28.393122 x32 (panfrost)
11218 23:49:28.396862 Last errno: 2, No such file or directory
11219 23:49:28.406252 [1mSubtest base-param<8>[ 12.250230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11220 23:49:28.407129 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11222 23:49:28.409090 s: SKIP (0.000s)[0m
11223 23:49:28.412510 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11224 23:49:28.419341 Using IGT_SRANDOM=1717544968 for randomisation
11225 23:49:28.425977 Test requirement not m<14>[ 12.271511] [IGT] panfrost_get_param: executing
11226 23:49:28.432356 et in function drm_open_driver, <14>[ 12.279015] [IGT] panfrost_get_param: exiting, ret=77
11227 23:49:28.435614 file ../lib/drmtest.c:694:
11228 23:49:28.438968 Test requirement: !(fd<0)
11229 23:49:28.445631 No known gpu found for ch<8>[ 12.291437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11230 23:49:28.446481 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11232 23:49:28.448835 ipset flags 0x32 (panfrost)
11233 23:49:28.452596 Las<8>[ 12.301036] <LAVA_SIGNAL_TESTSET STOP>
11234 23:49:28.453475 Received signal: <TESTSET> STOP
11235 23:49:28.453866 Closing test_set panfrost_get_param
11236 23:49:28.455974 t errno: 2, No such file or directory
11237 23:49:28.462457 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11238 23:49:28.465927 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11239 23:49:28.472315 Using IGT_SRANDOM=1717544968 for randomisation
11240 23:49:28.476097 Received signal: <TESTSET> START panfrost_prime
11241 23:49:28.476670 Starting test_set panfrost_prime
11242 23:49:28.478791 Test re<8>[ 12.323889] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11243 23:49:28.482422 quirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11244 23:49:28.485924 Test requirement: !(fd<0)
11245 23:49:28.492439 No known gpu found for chipset flags 0x32 (panfrost)
11246 23:49:28.495874 Last<14>[ 12.343175] [IGT] panfrost_prime: executing
11247 23:49:28.502210 errno: 2, No such file or direc<14>[ 12.350280] [IGT] panfrost_prime: exiting, ret=77
11248 23:49:28.505498 tory
11249 23:49:28.508753 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11250 23:49:28.522089 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 <8>[ 12.365227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11251 23:49:28.522655 aarch64)
11252 23:49:28.523307 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11254 23:49:28.529537 Using IGT_SRANDOM=1717<8>[ 12.374641] <LAVA_SIGNAL_TESTSET STOP>
11255 23:49:28.530097 544968 for randomisation
11256 23:49:28.530748 Received signal: <TESTSET> STOP
11257 23:49:28.531113 Closing test_set panfrost_prime
11258 23:49:28.538422 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11259 23:49:28.538888 Test requirement: !(fd<0)
11260 23:49:28.545227 No known gpu found for chipset flags 0x32 (panfrost)
11261 23:49:28.548899 Last errno: 2, No such file or directory
11262 23:49:28.552113 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11263 23:49:28.560120 <8>[ 12.407336] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11264 23:49:28.561165 Received signal: <TESTSET> START panfrost_submit
11265 23:49:28.561581 Starting test_set panfrost_submit
11266 23:49:28.590211 <14>[ 12.437228] [IGT] panfrost_submit: executing
11267 23:49:28.600049 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 12.445274] [IGT] panfrost_submit: exiting, ret=77
11268 23:49:28.600622 .92-cip22 aarch64)
11269 23:49:28.607264 Using IGT_SRANDOM=1717544968 for randomisation
11270 23:49:28.613271 Test requirement not met in <8>[ 12.458856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11271 23:49:28.614015 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11273 23:49:28.620375 function drm_open_driver, file ../lib/drmtest.c:694:
11274 23:49:28.620940 Test requirement: !(fd<0)
11275 23:49:28.626605 No known gpu found for chipset flags 0x32 (panfrost)
11276 23:49:28.630418 Last errno: 2, No such file or directory
11277 23:49:28.633096 [1mSubtest pan-submit: SKIP (0.000s)[0m
11278 23:49:28.643734 <14>[ 12.491053] [IGT] panfrost_submit: executing
11279 23:49:28.653536 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 12.499350] [IGT] panfrost_submit: exiting, ret=77
11280 23:49:28.654091 .92-cip22 aarch64)
11281 23:49:28.660878 Using IGT_SRANDOM=1717544968 for randomisation
11282 23:49:28.670366 Test requirement not met in <8>[ 12.513455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11283 23:49:28.671112 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11285 23:49:28.674273 function drm_open_driver, file ../lib/drmtest.c:694:
11286 23:49:28.677814 Test requirement: !(fd<0)
11287 23:49:28.680624 No known gpu found for chipset flags 0x32 (panfrost)
11288 23:49:28.683877 Last errno: 2, No such file or directory
11289 23:49:28.690209 [1mSubtest pan<14>[ 12.537635] [IGT] panfrost_submit: executing
11290 23:49:28.697354 -submit-error-no-jc: SKIP (0.000<14>[ 12.545181] [IGT] panfrost_submit: exiting, ret=77
11291 23:49:28.700829 s)[0m
11292 23:49:28.703848 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11293 23:49:28.717009 Using IGT_SRANDOM=1717544968 for ran<8>[ 12.559363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11294 23:49:28.717585 domisation
11295 23:49:28.718376 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11297 23:49:28.724077 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11298 23:49:28.727006 Test requirement: !(fd<0)
11299 23:49:28.733543 No known gpu found for chipset flags 0x32 (panfrost)
11300 23:49:28.736863 Last errno: 2, No such file or directory
11301 23:49:28.743631 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s<14>[ 12.592510] [IGT] panfrost_submit: executing
11302 23:49:28.746865 )[0m
11303 23:49:28.754139 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 12.600770] [IGT] panfrost_submit: exiting, ret=77
11304 23:49:28.756843 .92-cip22 aarch64)
11305 23:49:28.760015 Using IGT_SRANDOM=1717544968 for randomisation
11306 23:49:28.770278 Test require<8>[ 12.612903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11307 23:49:28.771180 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11309 23:49:28.776779 ment not met in function drm_open_driver, file ../lib/drmtest.c:694:
11310 23:49:28.780487 Test requirement: !(fd<0)
11311 23:49:28.783631 No known gpu found for chipset flags 0x32 (panfrost)
11312 23:49:28.786622 Last errno: 2, No such file or directory
11313 23:49:28.794290 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11314 23:49:28.797114 <14>[ 12.645024] [IGT] panfrost_submit: executing
11315 23:49:28.797696
11316 23:49:28.806633 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 12.653218] [IGT] panfrost_submit: exiting, ret=77
11317 23:49:28.810129 .92-cip22 aarch64)
11318 23:49:28.813535 Using IGT_SRANDOM=1717544968 for randomisation
11319 23:49:28.827221 Test requirement not met in function drm_ope<8>[ 12.668096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11320 23:49:28.828067 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11322 23:49:28.829816 n_driver, file ../lib/drmtest.c:694:
11323 23:49:28.830309 Test requirement: !(fd<0)
11324 23:49:28.837826 No known gpu found for chipset flags 0x32 (panfrost)
11325 23:49:28.839726 Last errno: 2, No such file or directory
11326 23:49:28.846711 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11327 23:49:28.855718 <14>[ 12.702532] [IGT] panfrost_submit: executing
11328 23:49:28.865871 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1<14>[ 12.710495] [IGT] panfrost_submit: exiting, ret=77
11329 23:49:28.866428 .92-cip22 aarch64)
11330 23:49:28.871903 Using IGT_SRANDOM=1717544968 for randomisation
11331 23:49:28.881962 Test requirement not met in function drm_ope<8>[ 12.725647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11332 23:49:28.882811 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11334 23:49:28.885183 n_driver, file ../lib/drmtest.c:694:
11335 23:49:28.889245 Test requirement: !(fd<0)
11336 23:49:28.892556 No known gpu found for chipset flags 0x32 (panfrost)
11337 23:49:28.895285 Last errno: 2, No such file or directory
11338 23:49:28.901736 [1mSubtest pan<14>[ 12.749921] [IGT] panfrost_submit: executing
11339 23:49:28.911762 -submit-error-bad-out-sync: SKIP<14>[ 12.757153] [IGT] panfrost_submit: exiting, ret=77
11340 23:49:28.912308 (0.000s)[0m
11341 23:49:28.924760 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64<8>[ 12.769750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11342 23:49:28.925438 )
11343 23:49:28.926074 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11345 23:49:28.928618 Using IGT_SRANDOM=1717544968 for randomisation
11346 23:49:28.935079 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11347 23:49:28.938764 Test requirement: !(fd<0)
11348 23:49:28.941964 No known gpu found for chipset flags 0x32 (panfrost)
11349 23:49:28.945317 Last errno: 2, No such file or directory
11350 23:49:28.951726 [1mSubtest pan-<14>[ 12.799916] [IGT] panfrost_submit: executing
11351 23:49:28.954722 reset: SKIP (0.000s)[0m
11352 23:49:28.961914 IGT-Version: 1.28-ga44<14>[ 12.808490] [IGT] panfrost_submit: exiting, ret=77
11353 23:49:28.965264 ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11354 23:49:28.971766 Using IGT_SRANDOM=1717544968 for randomisation
11355 23:49:28.978164 Te<8>[ 12.821492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11356 23:49:28.978901 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11358 23:49:28.985145 st requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11359 23:49:28.988440 Test requirement: !(fd<0)
11360 23:49:28.992350 No known gpu found for chipset flags 0x32 (panfrost)
11361 23:49:28.998723 Last errno: 2, <14>[ 12.844725] [IGT] panfrost_submit: executing
11362 23:49:29.002057 No such file or directory
11363 23:49:29.005148 [1mS<14>[ 12.852540] [IGT] panfrost_submit: exiting, ret=77
11364 23:49:29.012101 ubtest pan-submit-and-close: SKIP (0.000s)[0m
11365 23:49:29.018529 IGT-Version: 1.2<8>[ 12.863076] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11366 23:49:29.019380 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11368 23:49:29.024678 8-ga44ebfe (aarch64) (Linux: 6.1<8>[ 12.873149] <LAVA_SIGNAL_TESTSET STOP>
11369 23:49:29.025576 Received signal: <TESTSET> STOP
11370 23:49:29.025960 Closing test_set panfrost_submit
11371 23:49:29.035084 .92-cip22 aarch6<8>[ 12.879161] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 14172991_1.5.2.3.1>
11372 23:49:29.035667 4)
11373 23:49:29.036338 Received signal: <ENDRUN> 0_igt-gpu-panfrost 14172991_1.5.2.3.1
11374 23:49:29.036768 Ending use of test pattern.
11375 23:49:29.037205 Ending test lava.0_igt-gpu-panfrost (14172991_1.5.2.3.1), duration 0.87
11377 23:49:29.038873 Using IGT_SRANDOM=1717544968 for randomisation
11378 23:49:29.044807 Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:694:
11379 23:49:29.048270 Test requirement: !(fd<0)
11380 23:49:29.051251 No known gpu found for chipset flags 0x32 (panfrost)
11381 23:49:29.058029 Last errno: 2, No such file or directory
11382 23:49:29.061693 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11383 23:49:29.062246 + set +x
11384 23:49:29.064461 <LAVA_TEST_RUNNER EXIT>
11385 23:49:29.065333 ok: lava_test_shell seems to have completed
11386 23:49:29.067079 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11387 23:49:29.067603 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11388 23:49:29.068058 end: 3 lava-test-retry (duration 00:00:01) [common]
11389 23:49:29.068531 start: 4 finalize (timeout 00:07:11) [common]
11390 23:49:29.069032 start: 4.1 power-off (timeout 00:00:30) [common]
11391 23:49:29.069839 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-3', '--port=1', '--command=off']
11392 23:49:29.193503 >> Command sent successfully.
11393 23:49:29.204050 Returned 0 in 0 seconds
11394 23:49:29.305313 end: 4.1 power-off (duration 00:00:00) [common]
11396 23:49:29.306728 start: 4.2 read-feedback (timeout 00:07:11) [common]
11397 23:49:29.307911 Listened to connection for namespace 'common' for up to 1s
11398 23:49:30.308629 Finalising connection for namespace 'common'
11399 23:49:30.309542 Disconnecting from shell: Finalise
11400 23:49:30.310193 / #
11401 23:49:30.411607 end: 4.2 read-feedback (duration 00:00:01) [common]
11402 23:49:30.412357 end: 4 finalize (duration 00:00:01) [common]
11403 23:49:30.412967 Cleaning after the job
11404 23:49:30.413539 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/ramdisk
11405 23:49:30.444218 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/kernel
11406 23:49:30.473514 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/dtb
11407 23:49:30.473812 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172991/tftp-deploy-8tg3m569/modules
11408 23:49:30.480637 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14172991
11409 23:49:30.589707 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14172991
11410 23:49:30.589891 Job finished correctly