Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 30
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 23:48:33.389325 lava-dispatcher, installed at version: 2024.03
2 23:48:33.389600 start: 0 validate
3 23:48:33.389793 Start time: 2024-06-04 23:48:33.389784+00:00 (UTC)
4 23:48:33.389974 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:48:33.390195 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-igt%2F20240313.0%2Farm64%2Frootfs.cpio.gz exists
6 23:48:33.649441 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:48:33.649626 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:48:33.906704 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:48:33.906877 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:48:34.165091 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:48:34.165247 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:48:34.424979 validate duration: 1.04
14 23:48:34.425267 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:48:34.425383 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:48:34.425484 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:48:34.425620 Not decompressing ramdisk as can be used compressed.
18 23:48:34.425760 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-igt/20240313.0/arm64/rootfs.cpio.gz
19 23:48:34.425827 saving as /var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/ramdisk/rootfs.cpio.gz
20 23:48:34.425890 total size: 47897469 (45 MB)
21 23:48:34.427105 progress 0 % (0 MB)
22 23:48:34.440195 progress 5 % (2 MB)
23 23:48:34.453303 progress 10 % (4 MB)
24 23:48:34.467513 progress 15 % (6 MB)
25 23:48:34.481564 progress 20 % (9 MB)
26 23:48:34.494803 progress 25 % (11 MB)
27 23:48:34.507777 progress 30 % (13 MB)
28 23:48:34.520373 progress 35 % (16 MB)
29 23:48:34.533573 progress 40 % (18 MB)
30 23:48:34.547355 progress 45 % (20 MB)
31 23:48:34.561142 progress 50 % (22 MB)
32 23:48:34.573943 progress 55 % (25 MB)
33 23:48:34.587116 progress 60 % (27 MB)
34 23:48:34.599821 progress 65 % (29 MB)
35 23:48:34.612763 progress 70 % (32 MB)
36 23:48:34.625469 progress 75 % (34 MB)
37 23:48:34.638311 progress 80 % (36 MB)
38 23:48:34.651632 progress 85 % (38 MB)
39 23:48:34.665074 progress 90 % (41 MB)
40 23:48:34.677915 progress 95 % (43 MB)
41 23:48:34.690577 progress 100 % (45 MB)
42 23:48:34.690842 45 MB downloaded in 0.26 s (172.40 MB/s)
43 23:48:34.691010 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:48:34.691325 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:48:34.691431 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:48:34.691520 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:48:34.691682 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:48:34.691783 saving as /var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/kernel/Image
50 23:48:34.691878 total size: 54682112 (52 MB)
51 23:48:34.691969 No compression specified
52 23:48:34.693198 progress 0 % (0 MB)
53 23:48:34.707848 progress 5 % (2 MB)
54 23:48:34.722690 progress 10 % (5 MB)
55 23:48:34.737620 progress 15 % (7 MB)
56 23:48:34.752371 progress 20 % (10 MB)
57 23:48:34.767121 progress 25 % (13 MB)
58 23:48:34.781531 progress 30 % (15 MB)
59 23:48:34.796324 progress 35 % (18 MB)
60 23:48:34.811164 progress 40 % (20 MB)
61 23:48:34.825691 progress 45 % (23 MB)
62 23:48:34.840312 progress 50 % (26 MB)
63 23:48:34.855067 progress 55 % (28 MB)
64 23:48:34.869872 progress 60 % (31 MB)
65 23:48:34.884417 progress 65 % (33 MB)
66 23:48:34.899177 progress 70 % (36 MB)
67 23:48:34.914340 progress 75 % (39 MB)
68 23:48:34.929140 progress 80 % (41 MB)
69 23:48:34.943860 progress 85 % (44 MB)
70 23:48:34.958520 progress 90 % (46 MB)
71 23:48:34.973376 progress 95 % (49 MB)
72 23:48:34.987864 progress 100 % (52 MB)
73 23:48:34.988150 52 MB downloaded in 0.30 s (176.02 MB/s)
74 23:48:34.988304 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:48:34.988564 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:48:34.988650 start: 1.3 download-retry (timeout 00:09:59) [common]
78 23:48:34.988733 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 23:48:34.988878 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:48:34.988951 saving as /var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/dtb/mt8192-asurada-spherion-r0.dtb
81 23:48:34.989032 total size: 47258 (0 MB)
82 23:48:34.989097 No compression specified
83 23:48:34.990786 progress 69 % (0 MB)
84 23:48:34.991092 progress 100 % (0 MB)
85 23:48:34.991258 0 MB downloaded in 0.00 s (20.27 MB/s)
86 23:48:34.991394 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:48:34.991619 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:48:34.991731 start: 1.4 download-retry (timeout 00:09:59) [common]
90 23:48:34.991832 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 23:48:34.991965 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:48:34.992033 saving as /var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/modules/modules.tar
93 23:48:34.992094 total size: 8603924 (8 MB)
94 23:48:34.992155 Using unxz to decompress xz
95 23:48:34.997069 progress 0 % (0 MB)
96 23:48:35.017804 progress 5 % (0 MB)
97 23:48:35.043126 progress 10 % (0 MB)
98 23:48:35.069383 progress 15 % (1 MB)
99 23:48:35.095193 progress 20 % (1 MB)
100 23:48:35.121588 progress 25 % (2 MB)
101 23:48:35.147980 progress 30 % (2 MB)
102 23:48:35.172414 progress 35 % (2 MB)
103 23:48:35.199412 progress 40 % (3 MB)
104 23:48:35.224584 progress 45 % (3 MB)
105 23:48:35.249288 progress 50 % (4 MB)
106 23:48:35.274858 progress 55 % (4 MB)
107 23:48:35.300000 progress 60 % (4 MB)
108 23:48:35.325175 progress 65 % (5 MB)
109 23:48:35.352303 progress 70 % (5 MB)
110 23:48:35.378229 progress 75 % (6 MB)
111 23:48:35.404078 progress 80 % (6 MB)
112 23:48:35.428456 progress 85 % (7 MB)
113 23:48:35.453529 progress 90 % (7 MB)
114 23:48:35.483821 progress 95 % (7 MB)
115 23:48:35.512385 progress 100 % (8 MB)
116 23:48:35.517951 8 MB downloaded in 0.53 s (15.60 MB/s)
117 23:48:35.518260 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:48:35.518565 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:48:35.518675 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:48:35.518788 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:48:35.518887 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:48:35.518995 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:48:35.519260 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea
125 23:48:35.519446 makedir: /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin
126 23:48:35.519601 makedir: /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/tests
127 23:48:35.519748 makedir: /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/results
128 23:48:35.519885 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-add-keys
129 23:48:35.520090 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-add-sources
130 23:48:35.520270 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-background-process-start
131 23:48:35.520469 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-background-process-stop
132 23:48:35.520650 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-common-functions
133 23:48:35.520804 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-echo-ipv4
134 23:48:35.520954 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-install-packages
135 23:48:35.521105 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-installed-packages
136 23:48:35.521279 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-os-build
137 23:48:35.521454 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-probe-channel
138 23:48:35.521628 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-probe-ip
139 23:48:35.521809 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-target-ip
140 23:48:35.521956 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-target-mac
141 23:48:35.522106 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-target-storage
142 23:48:35.522285 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-test-case
143 23:48:35.522460 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-test-event
144 23:48:35.522633 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-test-feedback
145 23:48:35.522811 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-test-raise
146 23:48:35.522974 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-test-reference
147 23:48:35.523148 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-test-runner
148 23:48:35.523323 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-test-set
149 23:48:35.523496 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-test-shell
150 23:48:35.523648 Updating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-install-packages (oe)
151 23:48:35.523828 Updating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/bin/lava-installed-packages (oe)
152 23:48:35.523999 Creating /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/environment
153 23:48:35.524146 LAVA metadata
154 23:48:35.524257 - LAVA_JOB_ID=14172959
155 23:48:35.524368 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:48:35.524507 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:48:35.524587 skipped lava-vland-overlay
158 23:48:35.524695 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:48:35.524798 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:48:35.524907 skipped lava-multinode-overlay
161 23:48:35.525028 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:48:35.525159 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:48:35.525279 Loading test definitions
164 23:48:35.525421 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:48:35.525536 Using /lava-14172959 at stage 0
166 23:48:35.525999 uuid=14172959_1.5.2.3.1 testdef=None
167 23:48:35.526127 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:48:35.526257 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:48:35.527010 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:48:35.527391 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:48:35.528056 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:48:35.528425 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:48:35.529060 runner path: /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/0/tests/0_igt-kms-mediatek test_uuid 14172959_1.5.2.3.1
176 23:48:35.529239 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:48:35.529476 Creating lava-test-runner.conf files
179 23:48:35.529582 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14172959/lava-overlay-k38opjea/lava-14172959/0 for stage 0
180 23:48:35.529728 - 0_igt-kms-mediatek
181 23:48:35.529870 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:48:35.529999 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:48:35.537763 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:48:35.537905 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:48:35.538026 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:48:35.538134 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:48:35.538239 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:48:37.353158 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:02) [common]
189 23:48:37.353550 start: 1.5.4 extract-modules (timeout 00:09:57) [common]
190 23:48:37.353688 extracting modules file /var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172959/extract-overlay-ramdisk-tp6b03jx/ramdisk
191 23:48:37.587528 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:48:37.587713 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 23:48:37.587833 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172959/compress-overlay-1n_wtfal/overlay-1.5.2.4.tar.gz to ramdisk
194 23:48:37.587915 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172959/compress-overlay-1n_wtfal/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14172959/extract-overlay-ramdisk-tp6b03jx/ramdisk
195 23:48:37.594751 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:48:37.594919 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 23:48:37.595037 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:48:37.595147 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 23:48:37.595285 Building ramdisk /var/lib/lava/dispatcher/tmp/14172959/extract-overlay-ramdisk-tp6b03jx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14172959/extract-overlay-ramdisk-tp6b03jx/ramdisk
200 23:48:38.848046 >> 465921 blocks
201 23:48:45.415305 rename /var/lib/lava/dispatcher/tmp/14172959/extract-overlay-ramdisk-tp6b03jx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/ramdisk/ramdisk.cpio.gz
202 23:48:45.415802 end: 1.5.7 compress-ramdisk (duration 00:00:08) [common]
203 23:48:45.415950 start: 1.5.8 prepare-kernel (timeout 00:09:49) [common]
204 23:48:45.416106 start: 1.5.8.1 prepare-fit (timeout 00:09:49) [common]
205 23:48:45.416255 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/kernel/Image']
206 23:49:00.263779 Returned 0 in 14 seconds
207 23:49:00.364422 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/kernel/image.itb
208 23:49:01.233724 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:49:01.234123 output: Created: Wed Jun 5 00:49:01 2024
210 23:49:01.234234 output: Image 0 (kernel-1)
211 23:49:01.234329 output: Description:
212 23:49:01.234415 output: Created: Wed Jun 5 00:49:01 2024
213 23:49:01.234481 output: Type: Kernel Image
214 23:49:01.234545 output: Compression: lzma compressed
215 23:49:01.234608 output: Data Size: 13061430 Bytes = 12755.30 KiB = 12.46 MiB
216 23:49:01.234682 output: Architecture: AArch64
217 23:49:01.234779 output: OS: Linux
218 23:49:01.234888 output: Load Address: 0x00000000
219 23:49:01.234996 output: Entry Point: 0x00000000
220 23:49:01.235089 output: Hash algo: crc32
221 23:49:01.235177 output: Hash value: ecfb5096
222 23:49:01.235267 output: Image 1 (fdt-1)
223 23:49:01.235352 output: Description: mt8192-asurada-spherion-r0
224 23:49:01.235426 output: Created: Wed Jun 5 00:49:01 2024
225 23:49:01.235489 output: Type: Flat Device Tree
226 23:49:01.235545 output: Compression: uncompressed
227 23:49:01.235599 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
228 23:49:01.235654 output: Architecture: AArch64
229 23:49:01.235708 output: Hash algo: crc32
230 23:49:01.235762 output: Hash value: 0f8e4d2e
231 23:49:01.235816 output: Image 2 (ramdisk-1)
232 23:49:01.235869 output: Description: unavailable
233 23:49:01.235924 output: Created: Wed Jun 5 00:49:01 2024
234 23:49:01.235984 output: Type: RAMDisk Image
235 23:49:01.236069 output: Compression: Unknown Compression
236 23:49:01.236153 output: Data Size: 61007758 Bytes = 59577.89 KiB = 58.18 MiB
237 23:49:01.236241 output: Architecture: AArch64
238 23:49:01.236326 output: OS: Linux
239 23:49:01.236425 output: Load Address: unavailable
240 23:49:01.236486 output: Entry Point: unavailable
241 23:49:01.236543 output: Hash algo: crc32
242 23:49:01.236598 output: Hash value: 85bb53df
243 23:49:01.236652 output: Default Configuration: 'conf-1'
244 23:49:01.236706 output: Configuration 0 (conf-1)
245 23:49:01.236760 output: Description: mt8192-asurada-spherion-r0
246 23:49:01.236813 output: Kernel: kernel-1
247 23:49:01.236868 output: Init Ramdisk: ramdisk-1
248 23:49:01.236921 output: FDT: fdt-1
249 23:49:01.236977 output: Loadables: kernel-1
250 23:49:01.237037 output:
251 23:49:01.237248 end: 1.5.8.1 prepare-fit (duration 00:00:16) [common]
252 23:49:01.237347 end: 1.5.8 prepare-kernel (duration 00:00:16) [common]
253 23:49:01.237453 end: 1.5 prepare-tftp-overlay (duration 00:00:26) [common]
254 23:49:01.237554 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:33) [common]
255 23:49:01.237641 No LXC device requested
256 23:49:01.237725 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:49:01.237813 start: 1.7 deploy-device-env (timeout 00:09:33) [common]
258 23:49:01.237892 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:49:01.237967 Checking files for TFTP limit of 4294967296 bytes.
260 23:49:01.238481 end: 1 tftp-deploy (duration 00:00:27) [common]
261 23:49:01.238592 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:49:01.238690 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:49:01.238816 substitutions:
264 23:49:01.238882 - {DTB}: 14172959/tftp-deploy-tcbr0s4c/dtb/mt8192-asurada-spherion-r0.dtb
265 23:49:01.238968 - {INITRD}: 14172959/tftp-deploy-tcbr0s4c/ramdisk/ramdisk.cpio.gz
266 23:49:01.239031 - {KERNEL}: 14172959/tftp-deploy-tcbr0s4c/kernel/Image
267 23:49:01.239089 - {LAVA_MAC}: None
268 23:49:01.239152 - {PRESEED_CONFIG}: None
269 23:49:01.239211 - {PRESEED_LOCAL}: None
270 23:49:01.239267 - {RAMDISK}: 14172959/tftp-deploy-tcbr0s4c/ramdisk/ramdisk.cpio.gz
271 23:49:01.239323 - {ROOT_PART}: None
272 23:49:01.239381 - {ROOT}: None
273 23:49:01.239436 - {SERVER_IP}: 192.168.201.1
274 23:49:01.239491 - {TEE}: None
275 23:49:01.239546 Parsed boot commands:
276 23:49:01.239600 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:49:01.239782 Parsed boot commands: tftpboot 192.168.201.1 14172959/tftp-deploy-tcbr0s4c/kernel/image.itb 14172959/tftp-deploy-tcbr0s4c/kernel/cmdline
278 23:49:01.239874 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:49:01.239966 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:49:01.240060 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:49:01.240150 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:49:01.240224 Not connected, no need to disconnect.
283 23:49:01.240333 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:49:01.240426 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:49:01.240494 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 23:49:01.244599 Setting prompt string to ['lava-test: # ']
287 23:49:01.245020 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:49:01.245131 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:49:01.245240 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:49:01.245333 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:49:01.245532 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
292 23:49:06.386630 >> Command sent successfully.
293 23:49:06.389143 Returned 0 in 5 seconds
294 23:49:06.489503 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:49:06.489937 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:49:06.490071 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:49:06.490191 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:49:06.490289 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:49:06.490387 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:49:06.490955 [Enter `^Ec?' for help]
302 23:49:06.664567
303 23:49:06.664714
304 23:49:06.664814 F0: 102B 0000
305 23:49:06.664904
306 23:49:06.664989 F3: 1001 0000 [0200]
307 23:49:06.668333
308 23:49:06.668450 F3: 1001 0000
309 23:49:06.668544
310 23:49:06.668628 F7: 102D 0000
311 23:49:06.668710
312 23:49:06.671729 F1: 0000 0000
313 23:49:06.671844
314 23:49:06.671916 V0: 0000 0000 [0001]
315 23:49:06.671981
316 23:49:06.674949 00: 0007 8000
317 23:49:06.675047
318 23:49:06.675138 01: 0000 0000
319 23:49:06.675245
320 23:49:06.678303 BP: 0C00 0209 [0000]
321 23:49:06.678420
322 23:49:06.678511 G0: 1182 0000
323 23:49:06.678595
324 23:49:06.681698 EC: 0000 0021 [4000]
325 23:49:06.681790
326 23:49:06.681881 S7: 0000 0000 [0000]
327 23:49:06.681966
328 23:49:06.685568 CC: 0000 0000 [0001]
329 23:49:06.685695
330 23:49:06.685801 T0: 0000 0040 [010F]
331 23:49:06.685905
332 23:49:06.686003 Jump to BL
333 23:49:06.686100
334 23:49:06.712051
335 23:49:06.712231
336 23:49:06.719261 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
337 23:49:06.722549 ARM64: Exception handlers installed.
338 23:49:06.726384 ARM64: Testing exception
339 23:49:06.729292 ARM64: Done test exception
340 23:49:06.736524 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
341 23:49:06.746747 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
342 23:49:06.753267 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
343 23:49:06.763208 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
344 23:49:06.770045 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
345 23:49:06.776779 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
346 23:49:06.788804 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
347 23:49:06.795524 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
348 23:49:06.815038 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
349 23:49:06.818399 WDT: Last reset was cold boot
350 23:49:06.821563 SPI1(PAD0) initialized at 2873684 Hz
351 23:49:06.824426 SPI5(PAD0) initialized at 992727 Hz
352 23:49:06.827678 VBOOT: Loading verstage.
353 23:49:06.835009 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
354 23:49:06.838443 FMAP: Found "FLASH" version 1.1 at 0x20000.
355 23:49:06.841292 FMAP: base = 0x0 size = 0x800000 #areas = 25
356 23:49:06.845034 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
357 23:49:06.851910 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
358 23:49:06.858665 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
359 23:49:06.869480 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
360 23:49:06.869636
361 23:49:06.869747
362 23:49:06.880240 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
363 23:49:06.883265 ARM64: Exception handlers installed.
364 23:49:06.886465 ARM64: Testing exception
365 23:49:06.886564 ARM64: Done test exception
366 23:49:06.893660 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
367 23:49:06.896874 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
368 23:49:06.910731 Probing TPM: . done!
369 23:49:06.910866 TPM ready after 0 ms
370 23:49:06.918241 Connected to device vid:did:rid of 1ae0:0028:00
371 23:49:06.924992 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
372 23:49:06.995279 Initialized TPM device CR50 revision 0
373 23:49:07.007448 tlcl_send_startup: Startup return code is 0
374 23:49:07.007654 TPM: setup succeeded
375 23:49:07.018770 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
376 23:49:07.028799 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
377 23:49:07.043074 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
378 23:49:07.050674 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
379 23:49:07.050804 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
380 23:49:07.055323 in-header: 03 07 00 00 08 00 00 00
381 23:49:07.059111 in-data: aa e4 47 04 13 02 00 00
382 23:49:07.062698 Chrome EC: UHEPI supported
383 23:49:07.070142 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
384 23:49:07.073478 in-header: 03 95 00 00 08 00 00 00
385 23:49:07.073632 in-data: 18 20 20 08 00 00 00 00
386 23:49:07.077662 Phase 1
387 23:49:07.080922 FMAP: area GBB found @ 3f5000 (12032 bytes)
388 23:49:07.084886 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
389 23:49:07.092112 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
390 23:49:07.096302 Recovery requested (1009000e)
391 23:49:07.106235 TPM: Extending digest for VBOOT: boot mode into PCR 0
392 23:49:07.110012 tlcl_extend: response is 0
393 23:49:07.118710 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
394 23:49:07.124788 tlcl_extend: response is 0
395 23:49:07.131039 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
396 23:49:07.151053 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
397 23:49:07.157687 BS: bootblock times (exec / console): total (unknown) / 148 ms
398 23:49:07.157840
399 23:49:07.157956
400 23:49:07.167542 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
401 23:49:07.170891 ARM64: Exception handlers installed.
402 23:49:07.174305 ARM64: Testing exception
403 23:49:07.174443 ARM64: Done test exception
404 23:49:07.196774 pmic_efuse_setting: Set efuses in 11 msecs
405 23:49:07.200091 pmwrap_interface_init: Select PMIF_VLD_RDY
406 23:49:07.207744 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
407 23:49:07.211453 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
408 23:49:07.214688 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
409 23:49:07.222393 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
410 23:49:07.226076 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
411 23:49:07.229365 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
412 23:49:07.233184 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
413 23:49:07.240602 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
414 23:49:07.244254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
415 23:49:07.247759 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
416 23:49:07.255531 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
417 23:49:07.259138 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
418 23:49:07.262756 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
419 23:49:07.270396 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
420 23:49:07.273543 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
421 23:49:07.281108 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
422 23:49:07.285051 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
423 23:49:07.292266 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
424 23:49:07.296239 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
425 23:49:07.303417 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
426 23:49:07.306844 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
427 23:49:07.314779 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
428 23:49:07.318220 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
429 23:49:07.325457 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
430 23:49:07.328968 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
431 23:49:07.336659 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
432 23:49:07.340104 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
433 23:49:07.347489 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
434 23:49:07.351499 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
435 23:49:07.354934 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
436 23:49:07.362108 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
437 23:49:07.365866 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
438 23:49:07.369813 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
439 23:49:07.377208 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
440 23:49:07.381027 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
441 23:49:07.384381 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
442 23:49:07.392077 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
443 23:49:07.395460 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
444 23:49:07.399547 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
445 23:49:07.402981 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
446 23:49:07.410338 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
447 23:49:07.414552 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
448 23:49:07.417822 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
449 23:49:07.421787 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
450 23:49:07.425196 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
451 23:49:07.432523 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
452 23:49:07.435741 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
453 23:49:07.439502 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
454 23:49:07.443072 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
455 23:49:07.446946 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
456 23:49:07.450241 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
457 23:49:07.457622 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
458 23:49:07.469089 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
459 23:49:07.473183 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
460 23:49:07.479879 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
461 23:49:07.488174 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
462 23:49:07.495354 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
463 23:49:07.499749 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
464 23:49:07.502839 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:49:07.510438 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x36
466 23:49:07.513844 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
467 23:49:07.521678 [RTC]rtc_osc_init,62: osc32con val = 0xde70
468 23:49:07.524725 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
469 23:49:07.534429 [RTC]rtc_get_frequency_meter,154: input=15, output=760
470 23:49:07.543919 [RTC]rtc_get_frequency_meter,154: input=23, output=942
471 23:49:07.553673 [RTC]rtc_get_frequency_meter,154: input=19, output=850
472 23:49:07.562680 [RTC]rtc_get_frequency_meter,154: input=17, output=803
473 23:49:07.572105 [RTC]rtc_get_frequency_meter,154: input=16, output=782
474 23:49:07.581378 [RTC]rtc_get_frequency_meter,154: input=16, output=783
475 23:49:07.591813 [RTC]rtc_get_frequency_meter,154: input=17, output=805
476 23:49:07.595430 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
477 23:49:07.599258 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
478 23:49:07.603353 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
479 23:49:07.610354 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
480 23:49:07.614168 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
481 23:49:07.617662 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
482 23:49:07.621034 ADC[4]: Raw value=906203 ID=7
483 23:49:07.621171 ADC[3]: Raw value=213810 ID=1
484 23:49:07.624972 RAM Code: 0x71
485 23:49:07.628715 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
486 23:49:07.632920 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
487 23:49:07.644036 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
488 23:49:07.647648 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
489 23:49:07.650754 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
490 23:49:07.654597 in-header: 03 07 00 00 08 00 00 00
491 23:49:07.658309 in-data: aa e4 47 04 13 02 00 00
492 23:49:07.662208 Chrome EC: UHEPI supported
493 23:49:07.669557 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
494 23:49:07.673081 in-header: 03 95 00 00 08 00 00 00
495 23:49:07.673231 in-data: 18 20 20 08 00 00 00 00
496 23:49:07.677188 MRC: failed to locate region type 0.
497 23:49:07.684273 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
498 23:49:07.687746 DRAM-K: Running full calibration
499 23:49:07.695426 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
500 23:49:07.695639 header.status = 0x0
501 23:49:07.699681 header.version = 0x6 (expected: 0x6)
502 23:49:07.703047 header.size = 0xd00 (expected: 0xd00)
503 23:49:07.703164 header.flags = 0x0
504 23:49:07.709917 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
505 23:49:07.728686 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
506 23:49:07.735502 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
507 23:49:07.738989 dram_init: ddr_geometry: 2
508 23:49:07.739141 [EMI] MDL number = 2
509 23:49:07.743260 [EMI] Get MDL freq = 0
510 23:49:07.743389 dram_init: ddr_type: 0
511 23:49:07.746626 is_discrete_lpddr4: 1
512 23:49:07.750622 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
513 23:49:07.750737
514 23:49:07.750808
515 23:49:07.750872 [Bian_co] ETT version 0.0.0.1
516 23:49:07.757474 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
517 23:49:07.757626
518 23:49:07.761464 dramc_set_vcore_voltage set vcore to 650000
519 23:49:07.761571 Read voltage for 800, 4
520 23:49:07.764817 Vio18 = 0
521 23:49:07.764914 Vcore = 650000
522 23:49:07.764985 Vdram = 0
523 23:49:07.765050 Vddq = 0
524 23:49:07.769047 Vmddr = 0
525 23:49:07.769146 dram_init: config_dvfs: 1
526 23:49:07.776085 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
527 23:49:07.780262 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
528 23:49:07.783527 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
529 23:49:07.787213 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
530 23:49:07.790987 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
531 23:49:07.794582 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
532 23:49:07.797912 MEM_TYPE=3, freq_sel=18
533 23:49:07.801348 sv_algorithm_assistance_LP4_1600
534 23:49:07.804863 ============ PULL DRAM RESETB DOWN ============
535 23:49:07.808234 ========== PULL DRAM RESETB DOWN end =========
536 23:49:07.815540 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
537 23:49:07.815667 ===================================
538 23:49:07.819522 LPDDR4 DRAM CONFIGURATION
539 23:49:07.822707 ===================================
540 23:49:07.826719 EX_ROW_EN[0] = 0x0
541 23:49:07.826815 EX_ROW_EN[1] = 0x0
542 23:49:07.830283 LP4Y_EN = 0x0
543 23:49:07.830378 WORK_FSP = 0x0
544 23:49:07.830448 WL = 0x2
545 23:49:07.833630 RL = 0x2
546 23:49:07.833715 BL = 0x2
547 23:49:07.836924 RPST = 0x0
548 23:49:07.837005 RD_PRE = 0x0
549 23:49:07.840523 WR_PRE = 0x1
550 23:49:07.843754 WR_PST = 0x0
551 23:49:07.843849 DBI_WR = 0x0
552 23:49:07.847220 DBI_RD = 0x0
553 23:49:07.847301 OTF = 0x1
554 23:49:07.850555 ===================================
555 23:49:07.854030 ===================================
556 23:49:07.854127 ANA top config
557 23:49:07.857422 ===================================
558 23:49:07.860840 DLL_ASYNC_EN = 0
559 23:49:07.863504 ALL_SLAVE_EN = 1
560 23:49:07.867382 NEW_RANK_MODE = 1
561 23:49:07.867513 DLL_IDLE_MODE = 1
562 23:49:07.870801 LP45_APHY_COMB_EN = 1
563 23:49:07.874373 TX_ODT_DIS = 1
564 23:49:07.877751 NEW_8X_MODE = 1
565 23:49:07.880934 ===================================
566 23:49:07.884462 ===================================
567 23:49:07.888185 data_rate = 1600
568 23:49:07.888277 CKR = 1
569 23:49:07.891051 DQ_P2S_RATIO = 8
570 23:49:07.894511 ===================================
571 23:49:07.897699 CA_P2S_RATIO = 8
572 23:49:07.901226 DQ_CA_OPEN = 0
573 23:49:07.904428 DQ_SEMI_OPEN = 0
574 23:49:07.904532 CA_SEMI_OPEN = 0
575 23:49:07.907754 CA_FULL_RATE = 0
576 23:49:07.911112 DQ_CKDIV4_EN = 1
577 23:49:07.914449 CA_CKDIV4_EN = 1
578 23:49:07.917855 CA_PREDIV_EN = 0
579 23:49:07.920989 PH8_DLY = 0
580 23:49:07.921128 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
581 23:49:07.924212 DQ_AAMCK_DIV = 4
582 23:49:07.927968 CA_AAMCK_DIV = 4
583 23:49:07.931720 CA_ADMCK_DIV = 4
584 23:49:07.935044 DQ_TRACK_CA_EN = 0
585 23:49:07.935129 CA_PICK = 800
586 23:49:07.939014 CA_MCKIO = 800
587 23:49:07.942980 MCKIO_SEMI = 0
588 23:49:07.946602 PLL_FREQ = 3068
589 23:49:07.946713 DQ_UI_PI_RATIO = 32
590 23:49:07.950229 CA_UI_PI_RATIO = 0
591 23:49:07.953922 ===================================
592 23:49:07.957336 ===================================
593 23:49:07.961555 memory_type:LPDDR4
594 23:49:07.961638 GP_NUM : 10
595 23:49:07.965692 SRAM_EN : 1
596 23:49:07.965804 MD32_EN : 0
597 23:49:07.968345 ===================================
598 23:49:07.971742 [ANA_INIT] >>>>>>>>>>>>>>
599 23:49:07.975109 <<<<<< [CONFIGURE PHASE]: ANA_TX
600 23:49:07.978743 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
601 23:49:07.982046 ===================================
602 23:49:07.985422 data_rate = 1600,PCW = 0X7600
603 23:49:07.988866 ===================================
604 23:49:07.992225 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
605 23:49:07.995507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
606 23:49:08.002014 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:49:08.005389 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
608 23:49:08.008826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
609 23:49:08.012037 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:49:08.015409 [ANA_INIT] flow start
611 23:49:08.018790 [ANA_INIT] PLL >>>>>>>>
612 23:49:08.018879 [ANA_INIT] PLL <<<<<<<<
613 23:49:08.022099 [ANA_INIT] MIDPI >>>>>>>>
614 23:49:08.025896 [ANA_INIT] MIDPI <<<<<<<<
615 23:49:08.025982 [ANA_INIT] DLL >>>>>>>>
616 23:49:08.028876 [ANA_INIT] flow end
617 23:49:08.032287 ============ LP4 DIFF to SE enter ============
618 23:49:08.035748 ============ LP4 DIFF to SE exit ============
619 23:49:08.039336 [ANA_INIT] <<<<<<<<<<<<<
620 23:49:08.042475 [Flow] Enable top DCM control >>>>>
621 23:49:08.045404 [Flow] Enable top DCM control <<<<<
622 23:49:08.048785 Enable DLL master slave shuffle
623 23:49:08.056020 ==============================================================
624 23:49:08.056117 Gating Mode config
625 23:49:08.062036 ==============================================================
626 23:49:08.062142 Config description:
627 23:49:08.071978 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
628 23:49:08.078951 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
629 23:49:08.085563 SELPH_MODE 0: By rank 1: By Phase
630 23:49:08.089016 ==============================================================
631 23:49:08.092267 GAT_TRACK_EN = 1
632 23:49:08.095545 RX_GATING_MODE = 2
633 23:49:08.098931 RX_GATING_TRACK_MODE = 2
634 23:49:08.102752 SELPH_MODE = 1
635 23:49:08.105727 PICG_EARLY_EN = 1
636 23:49:08.109055 VALID_LAT_VALUE = 1
637 23:49:08.112231 ==============================================================
638 23:49:08.116143 Enter into Gating configuration >>>>
639 23:49:08.119508 Exit from Gating configuration <<<<
640 23:49:08.122203 Enter into DVFS_PRE_config >>>>>
641 23:49:08.135801 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
642 23:49:08.138896 Exit from DVFS_PRE_config <<<<<
643 23:49:08.138994 Enter into PICG configuration >>>>
644 23:49:08.142561 Exit from PICG configuration <<<<
645 23:49:08.145924 [RX_INPUT] configuration >>>>>
646 23:49:08.149218 [RX_INPUT] configuration <<<<<
647 23:49:08.155773 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
648 23:49:08.159536 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
649 23:49:08.166154 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
650 23:49:08.172662 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
651 23:49:08.179528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
652 23:49:08.185853 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
653 23:49:08.189484 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
654 23:49:08.192370 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
655 23:49:08.195581 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
656 23:49:08.202778 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
657 23:49:08.206112 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
658 23:49:08.209337 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
659 23:49:08.212504 ===================================
660 23:49:08.216055 LPDDR4 DRAM CONFIGURATION
661 23:49:08.219152 ===================================
662 23:49:08.219241 EX_ROW_EN[0] = 0x0
663 23:49:08.222447 EX_ROW_EN[1] = 0x0
664 23:49:08.222535 LP4Y_EN = 0x0
665 23:49:08.225825 WORK_FSP = 0x0
666 23:49:08.229035 WL = 0x2
667 23:49:08.229116 RL = 0x2
668 23:49:08.233021 BL = 0x2
669 23:49:08.233108 RPST = 0x0
670 23:49:08.236425 RD_PRE = 0x0
671 23:49:08.236509 WR_PRE = 0x1
672 23:49:08.239653 WR_PST = 0x0
673 23:49:08.239737 DBI_WR = 0x0
674 23:49:08.242943 DBI_RD = 0x0
675 23:49:08.243029 OTF = 0x1
676 23:49:08.245796 ===================================
677 23:49:08.249291 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
678 23:49:08.255996 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
679 23:49:08.259524 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
680 23:49:08.262893 ===================================
681 23:49:08.266339 LPDDR4 DRAM CONFIGURATION
682 23:49:08.269078 ===================================
683 23:49:08.269190 EX_ROW_EN[0] = 0x10
684 23:49:08.273152 EX_ROW_EN[1] = 0x0
685 23:49:08.273239 LP4Y_EN = 0x0
686 23:49:08.276305 WORK_FSP = 0x0
687 23:49:08.276430 WL = 0x2
688 23:49:08.279682 RL = 0x2
689 23:49:08.279768 BL = 0x2
690 23:49:08.282670 RPST = 0x0
691 23:49:08.282755 RD_PRE = 0x0
692 23:49:08.285963 WR_PRE = 0x1
693 23:49:08.286048 WR_PST = 0x0
694 23:49:08.289150 DBI_WR = 0x0
695 23:49:08.292448 DBI_RD = 0x0
696 23:49:08.292534 OTF = 0x1
697 23:49:08.296024 ===================================
698 23:49:08.302776 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
699 23:49:08.306403 nWR fixed to 40
700 23:49:08.309611 [ModeRegInit_LP4] CH0 RK0
701 23:49:08.309697 [ModeRegInit_LP4] CH0 RK1
702 23:49:08.312866 [ModeRegInit_LP4] CH1 RK0
703 23:49:08.316257 [ModeRegInit_LP4] CH1 RK1
704 23:49:08.316353 match AC timing 13
705 23:49:08.323096 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
706 23:49:08.326144 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
707 23:49:08.329540 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
708 23:49:08.336059 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
709 23:49:08.339636 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
710 23:49:08.339730 [EMI DOE] emi_dcm 0
711 23:49:08.346425 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
712 23:49:08.346518 ==
713 23:49:08.349836 Dram Type= 6, Freq= 0, CH_0, rank 0
714 23:49:08.353398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
715 23:49:08.353500 ==
716 23:49:08.359597 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
717 23:49:08.363071 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
718 23:49:08.373343 [CA 0] Center 36 (6~67) winsize 62
719 23:49:08.376682 [CA 1] Center 36 (6~67) winsize 62
720 23:49:08.379910 [CA 2] Center 34 (4~65) winsize 62
721 23:49:08.383305 [CA 3] Center 33 (3~64) winsize 62
722 23:49:08.387073 [CA 4] Center 33 (3~64) winsize 62
723 23:49:08.390156 [CA 5] Center 32 (3~62) winsize 60
724 23:49:08.390242
725 23:49:08.393532 [CmdBusTrainingLP45] Vref(ca) range 1: 34
726 23:49:08.393618
727 23:49:08.396832 [CATrainingPosCal] consider 1 rank data
728 23:49:08.399931 u2DelayCellTimex100 = 270/100 ps
729 23:49:08.403850 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
730 23:49:08.407091 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
731 23:49:08.413846 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
732 23:49:08.417202 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
733 23:49:08.420605 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
734 23:49:08.423671 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
735 23:49:08.423787
736 23:49:08.427090 CA PerBit enable=1, Macro0, CA PI delay=32
737 23:49:08.427189
738 23:49:08.430565 [CBTSetCACLKResult] CA Dly = 32
739 23:49:08.430679 CS Dly: 4 (0~35)
740 23:49:08.430781 ==
741 23:49:08.433694 Dram Type= 6, Freq= 0, CH_0, rank 1
742 23:49:08.440243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
743 23:49:08.440403 ==
744 23:49:08.443513 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
745 23:49:08.450150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
746 23:49:08.459606 [CA 0] Center 36 (6~67) winsize 62
747 23:49:08.462819 [CA 1] Center 36 (6~67) winsize 62
748 23:49:08.466128 [CA 2] Center 33 (3~64) winsize 62
749 23:49:08.469684 [CA 3] Center 33 (3~64) winsize 62
750 23:49:08.472746 [CA 4] Center 32 (2~63) winsize 62
751 23:49:08.475985 [CA 5] Center 32 (2~63) winsize 62
752 23:49:08.476069
753 23:49:08.479989 [CmdBusTrainingLP45] Vref(ca) range 1: 32
754 23:49:08.480097
755 23:49:08.483189 [CATrainingPosCal] consider 2 rank data
756 23:49:08.486665 u2DelayCellTimex100 = 270/100 ps
757 23:49:08.489996 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
758 23:49:08.493264 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
759 23:49:08.499616 CA2 delay=34 (4~64),Diff = 2 PI (14 cell)
760 23:49:08.502928 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
761 23:49:08.506308 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
762 23:49:08.509739 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
763 23:49:08.509826
764 23:49:08.513772 CA PerBit enable=1, Macro0, CA PI delay=32
765 23:49:08.513874
766 23:49:08.517664 [CBTSetCACLKResult] CA Dly = 32
767 23:49:08.517751 CS Dly: 4 (0~36)
768 23:49:08.517819
769 23:49:08.521032 ----->DramcWriteLeveling(PI) begin...
770 23:49:08.521124 ==
771 23:49:08.525054 Dram Type= 6, Freq= 0, CH_0, rank 0
772 23:49:08.528449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
773 23:49:08.528562 ==
774 23:49:08.531794 Write leveling (Byte 0): 35 => 35
775 23:49:08.535170 Write leveling (Byte 1): 30 => 30
776 23:49:08.538448 DramcWriteLeveling(PI) end<-----
777 23:49:08.538534
778 23:49:08.538602 ==
779 23:49:08.542587 Dram Type= 6, Freq= 0, CH_0, rank 0
780 23:49:08.546142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
781 23:49:08.546251 ==
782 23:49:08.549073 [Gating] SW mode calibration
783 23:49:08.556223 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
784 23:49:08.563050 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
785 23:49:08.566308 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
786 23:49:08.569642 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
787 23:49:08.572662 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
788 23:49:08.579433 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 23:49:08.582726 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:49:08.585673 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:49:08.592649 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:49:08.595973 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:49:08.599458 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:49:08.605903 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:49:08.609580 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:49:08.612451 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:49:08.619766 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:49:08.622985 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:49:08.625677 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:49:08.632298 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:49:08.636299 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:49:08.639612 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 23:49:08.645775 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
804 23:49:08.649150 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 23:49:08.652875 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:49:08.659201 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:49:08.662481 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:49:08.666275 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:49:08.672307 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:49:08.675790 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
811 23:49:08.679069 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
812 23:49:08.682431 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
813 23:49:08.689147 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 23:49:08.692368 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:49:08.696271 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:49:08.702594 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:49:08.706205 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:49:08.709137 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
819 23:49:08.716138 0 10 8 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
820 23:49:08.719347 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
821 23:49:08.722484 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 23:49:08.729285 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:49:08.732652 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:49:08.735802 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:49:08.743030 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:49:08.746439 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
827 23:49:08.749729 0 11 8 | B1->B0 | 3131 4242 | 1 0 | (0 0) (0 0)
828 23:49:08.752982 0 11 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
829 23:49:08.759531 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 23:49:08.762798 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:49:08.765958 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:49:08.773031 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:49:08.776276 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:49:08.779609 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:49:08.786207 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 23:49:08.789622 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 23:49:08.792952 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:49:08.799542 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:49:08.802787 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:49:08.806122 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:49:08.812772 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:49:08.816067 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:49:08.819331 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:49:08.826432 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:49:08.829665 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:49:08.832682 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:49:08.839687 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:49:08.842742 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:49:08.846550 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:49:08.849454 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
851 23:49:08.856361 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 23:49:08.859647 Total UI for P1: 0, mck2ui 16
853 23:49:08.862765 best dqsien dly found for B0: ( 0, 14, 4)
854 23:49:08.866597 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
855 23:49:08.870484 Total UI for P1: 0, mck2ui 16
856 23:49:08.873872 best dqsien dly found for B1: ( 0, 14, 8)
857 23:49:08.877101 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
858 23:49:08.880384 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
859 23:49:08.880481
860 23:49:08.883417 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
861 23:49:08.886950 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 23:49:08.890681 [Gating] SW calibration Done
863 23:49:08.890774 ==
864 23:49:08.893406 Dram Type= 6, Freq= 0, CH_0, rank 0
865 23:49:08.897425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
866 23:49:08.897517 ==
867 23:49:08.900727 RX Vref Scan: 0
868 23:49:08.900815
869 23:49:08.900885 RX Vref 0 -> 0, step: 1
870 23:49:08.900955
871 23:49:08.904151 RX Delay -130 -> 252, step: 16
872 23:49:08.907271 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
873 23:49:08.913849 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
874 23:49:08.917150 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
875 23:49:08.920461 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
876 23:49:08.923828 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
877 23:49:08.927069 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
878 23:49:08.934286 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
879 23:49:08.937651 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
880 23:49:08.940781 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
881 23:49:08.943986 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
882 23:49:08.947021 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
883 23:49:08.954044 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
884 23:49:08.957280 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
885 23:49:08.960664 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
886 23:49:08.963821 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
887 23:49:08.967544 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
888 23:49:08.970625 ==
889 23:49:08.974357 Dram Type= 6, Freq= 0, CH_0, rank 0
890 23:49:08.977061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
891 23:49:08.977143 ==
892 23:49:08.977209 DQS Delay:
893 23:49:08.980598 DQS0 = 0, DQS1 = 0
894 23:49:08.980674 DQM Delay:
895 23:49:08.983795 DQM0 = 88, DQM1 = 81
896 23:49:08.983875 DQ Delay:
897 23:49:08.987282 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
898 23:49:08.990474 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
899 23:49:08.994227 DQ8 =69, DQ9 =77, DQ10 =77, DQ11 =77
900 23:49:08.997196 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
901 23:49:08.997283
902 23:49:08.997384
903 23:49:08.997448 ==
904 23:49:09.000769 Dram Type= 6, Freq= 0, CH_0, rank 0
905 23:49:09.003969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
906 23:49:09.004079 ==
907 23:49:09.004161
908 23:49:09.004224
909 23:49:09.007264 TX Vref Scan disable
910 23:49:09.010659 == TX Byte 0 ==
911 23:49:09.014446 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
912 23:49:09.017664 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
913 23:49:09.017752 == TX Byte 1 ==
914 23:49:09.024465 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
915 23:49:09.027735 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
916 23:49:09.027824 ==
917 23:49:09.030971 Dram Type= 6, Freq= 0, CH_0, rank 0
918 23:49:09.034041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
919 23:49:09.034128 ==
920 23:49:09.049029 TX Vref=22, minBit 8, minWin=27, winSum=447
921 23:49:09.052219 TX Vref=24, minBit 9, minWin=27, winSum=452
922 23:49:09.055277 TX Vref=26, minBit 9, minWin=27, winSum=453
923 23:49:09.058932 TX Vref=28, minBit 5, minWin=28, winSum=457
924 23:49:09.062272 TX Vref=30, minBit 8, minWin=27, winSum=455
925 23:49:09.065683 TX Vref=32, minBit 2, minWin=28, winSum=453
926 23:49:09.072477 [TxChooseVref] Worse bit 5, Min win 28, Win sum 457, Final Vref 28
927 23:49:09.072583
928 23:49:09.075810 Final TX Range 1 Vref 28
929 23:49:09.075900
930 23:49:09.075968 ==
931 23:49:09.079067 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:49:09.082432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 23:49:09.082522 ==
934 23:49:09.082590
935 23:49:09.082652
936 23:49:09.085863 TX Vref Scan disable
937 23:49:09.088831 == TX Byte 0 ==
938 23:49:09.092569 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
939 23:49:09.095634 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
940 23:49:09.099119 == TX Byte 1 ==
941 23:49:09.102273 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
942 23:49:09.105904 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
943 23:49:09.106012
944 23:49:09.109131 [DATLAT]
945 23:49:09.109217 Freq=800, CH0 RK0
946 23:49:09.109285
947 23:49:09.112706 DATLAT Default: 0xa
948 23:49:09.112794 0, 0xFFFF, sum = 0
949 23:49:09.115795 1, 0xFFFF, sum = 0
950 23:49:09.115881 2, 0xFFFF, sum = 0
951 23:49:09.119091 3, 0xFFFF, sum = 0
952 23:49:09.119179 4, 0xFFFF, sum = 0
953 23:49:09.122246 5, 0xFFFF, sum = 0
954 23:49:09.122335 6, 0xFFFF, sum = 0
955 23:49:09.125998 7, 0xFFFF, sum = 0
956 23:49:09.126099 8, 0xFFFF, sum = 0
957 23:49:09.129222 9, 0x0, sum = 1
958 23:49:09.129309 10, 0x0, sum = 2
959 23:49:09.132274 11, 0x0, sum = 3
960 23:49:09.132413 12, 0x0, sum = 4
961 23:49:09.135597 best_step = 10
962 23:49:09.135682
963 23:49:09.135749 ==
964 23:49:09.138880 Dram Type= 6, Freq= 0, CH_0, rank 0
965 23:49:09.142246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
966 23:49:09.142337 ==
967 23:49:09.146262 RX Vref Scan: 1
968 23:49:09.146378
969 23:49:09.146445 Set Vref Range= 32 -> 127
970 23:49:09.146508
971 23:49:09.149433 RX Vref 32 -> 127, step: 1
972 23:49:09.149518
973 23:49:09.152763 RX Delay -79 -> 252, step: 8
974 23:49:09.152848
975 23:49:09.156173 Set Vref, RX VrefLevel [Byte0]: 32
976 23:49:09.159259 [Byte1]: 32
977 23:49:09.159346
978 23:49:09.162893 Set Vref, RX VrefLevel [Byte0]: 33
979 23:49:09.165940 [Byte1]: 33
980 23:49:09.166058
981 23:49:09.169912 Set Vref, RX VrefLevel [Byte0]: 34
982 23:49:09.172714 [Byte1]: 34
983 23:49:09.176788
984 23:49:09.176879 Set Vref, RX VrefLevel [Byte0]: 35
985 23:49:09.180743 [Byte1]: 35
986 23:49:09.184808
987 23:49:09.184973 Set Vref, RX VrefLevel [Byte0]: 36
988 23:49:09.188678 [Byte1]: 36
989 23:49:09.192827
990 23:49:09.192939 Set Vref, RX VrefLevel [Byte0]: 37
991 23:49:09.195609 [Byte1]: 37
992 23:49:09.199475
993 23:49:09.199602 Set Vref, RX VrefLevel [Byte0]: 38
994 23:49:09.203315 [Byte1]: 38
995 23:49:09.207179
996 23:49:09.207265 Set Vref, RX VrefLevel [Byte0]: 39
997 23:49:09.210408 [Byte1]: 39
998 23:49:09.214163
999 23:49:09.214285 Set Vref, RX VrefLevel [Byte0]: 40
1000 23:49:09.217794 [Byte1]: 40
1001 23:49:09.221541
1002 23:49:09.221631 Set Vref, RX VrefLevel [Byte0]: 41
1003 23:49:09.225084 [Byte1]: 41
1004 23:49:09.229538
1005 23:49:09.229621 Set Vref, RX VrefLevel [Byte0]: 42
1006 23:49:09.232669 [Byte1]: 42
1007 23:49:09.236739
1008 23:49:09.236823 Set Vref, RX VrefLevel [Byte0]: 43
1009 23:49:09.240291 [Byte1]: 43
1010 23:49:09.244661
1011 23:49:09.244739 Set Vref, RX VrefLevel [Byte0]: 44
1012 23:49:09.247884 [Byte1]: 44
1013 23:49:09.252015
1014 23:49:09.252095 Set Vref, RX VrefLevel [Byte0]: 45
1015 23:49:09.255142 [Byte1]: 45
1016 23:49:09.259938
1017 23:49:09.260023 Set Vref, RX VrefLevel [Byte0]: 46
1018 23:49:09.262622 [Byte1]: 46
1019 23:49:09.267365
1020 23:49:09.267447 Set Vref, RX VrefLevel [Byte0]: 47
1021 23:49:09.270515 [Byte1]: 47
1022 23:49:09.274683
1023 23:49:09.274771 Set Vref, RX VrefLevel [Byte0]: 48
1024 23:49:09.277983 [Byte1]: 48
1025 23:49:09.282484
1026 23:49:09.282578 Set Vref, RX VrefLevel [Byte0]: 49
1027 23:49:09.285792 [Byte1]: 49
1028 23:49:09.289771
1029 23:49:09.289852 Set Vref, RX VrefLevel [Byte0]: 50
1030 23:49:09.293210 [Byte1]: 50
1031 23:49:09.297193
1032 23:49:09.297269 Set Vref, RX VrefLevel [Byte0]: 51
1033 23:49:09.300494 [Byte1]: 51
1034 23:49:09.305113
1035 23:49:09.305192 Set Vref, RX VrefLevel [Byte0]: 52
1036 23:49:09.308412 [Byte1]: 52
1037 23:49:09.312442
1038 23:49:09.312519 Set Vref, RX VrefLevel [Byte0]: 53
1039 23:49:09.315729 [Byte1]: 53
1040 23:49:09.320057
1041 23:49:09.320141 Set Vref, RX VrefLevel [Byte0]: 54
1042 23:49:09.323250 [Byte1]: 54
1043 23:49:09.327935
1044 23:49:09.328016 Set Vref, RX VrefLevel [Byte0]: 55
1045 23:49:09.331247 [Byte1]: 55
1046 23:49:09.334996
1047 23:49:09.335082 Set Vref, RX VrefLevel [Byte0]: 56
1048 23:49:09.338762 [Byte1]: 56
1049 23:49:09.342580
1050 23:49:09.342696 Set Vref, RX VrefLevel [Byte0]: 57
1051 23:49:09.345957 [Byte1]: 57
1052 23:49:09.350652
1053 23:49:09.350735 Set Vref, RX VrefLevel [Byte0]: 58
1054 23:49:09.353631 [Byte1]: 58
1055 23:49:09.357736
1056 23:49:09.357820 Set Vref, RX VrefLevel [Byte0]: 59
1057 23:49:09.361168 [Byte1]: 59
1058 23:49:09.365346
1059 23:49:09.365425 Set Vref, RX VrefLevel [Byte0]: 60
1060 23:49:09.368754 [Byte1]: 60
1061 23:49:09.373186
1062 23:49:09.373273 Set Vref, RX VrefLevel [Byte0]: 61
1063 23:49:09.376469 [Byte1]: 61
1064 23:49:09.380292
1065 23:49:09.380428 Set Vref, RX VrefLevel [Byte0]: 62
1066 23:49:09.384060 [Byte1]: 62
1067 23:49:09.388256
1068 23:49:09.388395 Set Vref, RX VrefLevel [Byte0]: 63
1069 23:49:09.391083 [Byte1]: 63
1070 23:49:09.395279
1071 23:49:09.395360 Set Vref, RX VrefLevel [Byte0]: 64
1072 23:49:09.399285 [Byte1]: 64
1073 23:49:09.403309
1074 23:49:09.403391 Set Vref, RX VrefLevel [Byte0]: 65
1075 23:49:09.406720 [Byte1]: 65
1076 23:49:09.410772
1077 23:49:09.410880 Set Vref, RX VrefLevel [Byte0]: 66
1078 23:49:09.414067 [Byte1]: 66
1079 23:49:09.418261
1080 23:49:09.418347 Set Vref, RX VrefLevel [Byte0]: 67
1081 23:49:09.421721 [Byte1]: 67
1082 23:49:09.425532
1083 23:49:09.425613 Set Vref, RX VrefLevel [Byte0]: 68
1084 23:49:09.428740 [Byte1]: 68
1085 23:49:09.433254
1086 23:49:09.433335 Set Vref, RX VrefLevel [Byte0]: 69
1087 23:49:09.436568 [Byte1]: 69
1088 23:49:09.441069
1089 23:49:09.441150 Set Vref, RX VrefLevel [Byte0]: 70
1090 23:49:09.444258 [Byte1]: 70
1091 23:49:09.448511
1092 23:49:09.448598 Set Vref, RX VrefLevel [Byte0]: 71
1093 23:49:09.451473 [Byte1]: 71
1094 23:49:09.456113
1095 23:49:09.456193 Set Vref, RX VrefLevel [Byte0]: 72
1096 23:49:09.459510 [Byte1]: 72
1097 23:49:09.463534
1098 23:49:09.463620 Set Vref, RX VrefLevel [Byte0]: 73
1099 23:49:09.466842 [Byte1]: 73
1100 23:49:09.471118
1101 23:49:09.471212 Set Vref, RX VrefLevel [Byte0]: 74
1102 23:49:09.474498 [Byte1]: 74
1103 23:49:09.478769
1104 23:49:09.478863 Set Vref, RX VrefLevel [Byte0]: 75
1105 23:49:09.481789 [Byte1]: 75
1106 23:49:09.486370
1107 23:49:09.486491 Set Vref, RX VrefLevel [Byte0]: 76
1108 23:49:09.489290 [Byte1]: 76
1109 23:49:09.493536
1110 23:49:09.493666 Set Vref, RX VrefLevel [Byte0]: 77
1111 23:49:09.497214 [Byte1]: 77
1112 23:49:09.501465
1113 23:49:09.501543 Final RX Vref Byte 0 = 60 to rank0
1114 23:49:09.504451 Final RX Vref Byte 1 = 65 to rank0
1115 23:49:09.507960 Final RX Vref Byte 0 = 60 to rank1
1116 23:49:09.511271 Final RX Vref Byte 1 = 65 to rank1==
1117 23:49:09.514598 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 23:49:09.518004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 23:49:09.521378 ==
1120 23:49:09.521463 DQS Delay:
1121 23:49:09.521527 DQS0 = 0, DQS1 = 0
1122 23:49:09.524621 DQM Delay:
1123 23:49:09.524729 DQM0 = 92, DQM1 = 86
1124 23:49:09.527906 DQ Delay:
1125 23:49:09.527982 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1126 23:49:09.531607 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1127 23:49:09.534809 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =76
1128 23:49:09.538026 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1129 23:49:09.541511
1130 23:49:09.541588
1131 23:49:09.547995 [DQSOSCAuto] RK0, (LSB)MR18= 0x4940, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1132 23:49:09.551264 CH0 RK0: MR19=606, MR18=4940
1133 23:49:09.558314 CH0_RK0: MR19=0x606, MR18=0x4940, DQSOSC=391, MR23=63, INC=96, DEC=64
1134 23:49:09.558405
1135 23:49:09.561498 ----->DramcWriteLeveling(PI) begin...
1136 23:49:09.561575 ==
1137 23:49:09.564809 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 23:49:09.568130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 23:49:09.568208 ==
1140 23:49:09.571320 Write leveling (Byte 0): 33 => 33
1141 23:49:09.575234 Write leveling (Byte 1): 28 => 28
1142 23:49:09.578330 DramcWriteLeveling(PI) end<-----
1143 23:49:09.578409
1144 23:49:09.578473 ==
1145 23:49:09.581527 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 23:49:09.626139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 23:49:09.626308 ==
1148 23:49:09.626378 [Gating] SW mode calibration
1149 23:49:09.626667 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 23:49:09.626769 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 23:49:09.626834 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 23:49:09.626933 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 23:49:09.627057 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1154 23:49:09.627187 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 23:49:09.627303 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:49:09.627393 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:49:09.669853 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:49:09.670172 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:49:09.670244 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:49:09.670326 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:49:09.670390 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:49:09.670465 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:49:09.670717 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:49:09.670971 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:49:09.671036 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:49:09.671096 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:49:09.676827 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:49:09.679390 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:49:09.683215 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1170 23:49:09.689538 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 23:49:09.692966 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:49:09.696251 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:49:09.700103 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:49:09.706511 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:49:09.709826 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:49:09.713049 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:49:09.719413 0 9 8 | B1->B0 | 2a2a 2b2b | 0 1 | (0 0) (1 1)
1178 23:49:09.723142 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 23:49:09.726197 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 23:49:09.732907 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:49:09.736122 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 23:49:09.739759 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 23:49:09.746321 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 23:49:09.749669 0 10 4 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
1185 23:49:09.752702 0 10 8 | B1->B0 | 2c2c 2929 | 1 0 | (1 1) (0 0)
1186 23:49:09.760603 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:49:09.763834 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:49:09.767684 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:49:09.771647 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:49:09.774702 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:49:09.781274 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 23:49:09.785162 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1193 23:49:09.789156 0 11 8 | B1->B0 | 3e3e 3e3e | 0 0 | (0 0) (0 0)
1194 23:49:09.792221 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 23:49:09.799387 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:49:09.802720 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:49:09.805893 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 23:49:09.812914 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 23:49:09.815613 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 23:49:09.818995 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 23:49:09.826113 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1202 23:49:09.829412 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:49:09.832760 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:49:09.839283 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:49:09.842928 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:49:09.846030 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:49:09.849462 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:49:09.855779 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:49:09.859650 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:49:09.862926 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:49:09.869613 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:49:09.872423 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:49:09.876379 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:49:09.882528 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:49:09.886426 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:49:09.889054 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:49:09.895652 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1218 23:49:09.899269 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1219 23:49:09.902669 Total UI for P1: 0, mck2ui 16
1220 23:49:09.905963 best dqsien dly found for B0: ( 0, 14, 8)
1221 23:49:09.909181 Total UI for P1: 0, mck2ui 16
1222 23:49:09.912452 best dqsien dly found for B1: ( 0, 14, 8)
1223 23:49:09.916077 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1224 23:49:09.919266 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1225 23:49:09.919347
1226 23:49:09.922553 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1227 23:49:09.925913 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 23:49:09.929303 [Gating] SW calibration Done
1229 23:49:09.929397 ==
1230 23:49:09.932404 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 23:49:09.936368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 23:49:09.936465 ==
1233 23:49:09.939737 RX Vref Scan: 0
1234 23:49:09.939815
1235 23:49:09.943057 RX Vref 0 -> 0, step: 1
1236 23:49:09.943135
1237 23:49:09.943203 RX Delay -130 -> 252, step: 16
1238 23:49:09.949201 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1239 23:49:09.952526 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1240 23:49:09.956292 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1241 23:49:09.959570 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1242 23:49:09.962647 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1243 23:49:09.969524 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1244 23:49:09.972784 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1245 23:49:09.976188 iDelay=222, Bit 7, Center 109 (-2 ~ 221) 224
1246 23:49:09.979692 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1247 23:49:09.982959 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
1248 23:49:09.986402 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1249 23:49:09.992728 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1250 23:49:09.996531 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1251 23:49:09.999823 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1252 23:49:10.002942 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1253 23:49:10.009685 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1254 23:49:10.009776 ==
1255 23:49:10.012998 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 23:49:10.016330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 23:49:10.016458 ==
1258 23:49:10.016525 DQS Delay:
1259 23:49:10.019603 DQS0 = 0, DQS1 = 0
1260 23:49:10.019697 DQM Delay:
1261 23:49:10.022751 DQM0 = 92, DQM1 = 82
1262 23:49:10.022836 DQ Delay:
1263 23:49:10.026634 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1264 23:49:10.029848 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =109
1265 23:49:10.033150 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1266 23:49:10.036416 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1267 23:49:10.036503
1268 23:49:10.036569
1269 23:49:10.036629 ==
1270 23:49:10.039683 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 23:49:10.042959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 23:49:10.043042 ==
1273 23:49:10.043108
1274 23:49:10.043168
1275 23:49:10.046183 TX Vref Scan disable
1276 23:49:10.049435 == TX Byte 0 ==
1277 23:49:10.052798 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1278 23:49:10.056045 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1279 23:49:10.059326 == TX Byte 1 ==
1280 23:49:10.063213 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1281 23:49:10.066595 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1282 23:49:10.066680 ==
1283 23:49:10.069805 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 23:49:10.076211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 23:49:10.076299 ==
1286 23:49:10.088184 TX Vref=22, minBit 8, minWin=27, winSum=444
1287 23:49:10.091326 TX Vref=24, minBit 9, minWin=27, winSum=451
1288 23:49:10.095501 TX Vref=26, minBit 1, minWin=28, winSum=460
1289 23:49:10.098377 TX Vref=28, minBit 5, minWin=28, winSum=458
1290 23:49:10.101889 TX Vref=30, minBit 5, minWin=28, winSum=458
1291 23:49:10.108318 TX Vref=32, minBit 12, minWin=27, winSum=454
1292 23:49:10.112186 [TxChooseVref] Worse bit 1, Min win 28, Win sum 460, Final Vref 26
1293 23:49:10.112276
1294 23:49:10.114957 Final TX Range 1 Vref 26
1295 23:49:10.115075
1296 23:49:10.115141 ==
1297 23:49:10.118372 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 23:49:10.121812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 23:49:10.121898 ==
1300 23:49:10.121963
1301 23:49:10.125145
1302 23:49:10.125252 TX Vref Scan disable
1303 23:49:10.128722 == TX Byte 0 ==
1304 23:49:10.131685 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1305 23:49:10.135275 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1306 23:49:10.138564 == TX Byte 1 ==
1307 23:49:10.141796 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1308 23:49:10.144971 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1309 23:49:10.148211
1310 23:49:10.148346 [DATLAT]
1311 23:49:10.148429 Freq=800, CH0 RK1
1312 23:49:10.148492
1313 23:49:10.151508 DATLAT Default: 0xa
1314 23:49:10.151590 0, 0xFFFF, sum = 0
1315 23:49:10.155454 1, 0xFFFF, sum = 0
1316 23:49:10.155538 2, 0xFFFF, sum = 0
1317 23:49:10.158795 3, 0xFFFF, sum = 0
1318 23:49:10.158878 4, 0xFFFF, sum = 0
1319 23:49:10.161638 5, 0xFFFF, sum = 0
1320 23:49:10.161724 6, 0xFFFF, sum = 0
1321 23:49:10.164984 7, 0xFFFF, sum = 0
1322 23:49:10.168240 8, 0xFFFF, sum = 0
1323 23:49:10.168362 9, 0x0, sum = 1
1324 23:49:10.168465 10, 0x0, sum = 2
1325 23:49:10.171698 11, 0x0, sum = 3
1326 23:49:10.171783 12, 0x0, sum = 4
1327 23:49:10.175034 best_step = 10
1328 23:49:10.175118
1329 23:49:10.175185 ==
1330 23:49:10.178412 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 23:49:10.181489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 23:49:10.181572 ==
1333 23:49:10.185216 RX Vref Scan: 0
1334 23:49:10.185296
1335 23:49:10.185360 RX Vref 0 -> 0, step: 1
1336 23:49:10.185419
1337 23:49:10.188368 RX Delay -79 -> 252, step: 8
1338 23:49:10.195359 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1339 23:49:10.198815 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1340 23:49:10.202052 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1341 23:49:10.205374 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1342 23:49:10.208688 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1343 23:49:10.211903 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1344 23:49:10.218864 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1345 23:49:10.222025 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1346 23:49:10.225195 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1347 23:49:10.228425 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1348 23:49:10.232109 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1349 23:49:10.238574 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1350 23:49:10.242064 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1351 23:49:10.245484 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1352 23:49:10.248562 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1353 23:49:10.255587 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1354 23:49:10.255690 ==
1355 23:49:10.258597 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 23:49:10.261931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 23:49:10.262015 ==
1358 23:49:10.262156 DQS Delay:
1359 23:49:10.265369 DQS0 = 0, DQS1 = 0
1360 23:49:10.265454 DQM Delay:
1361 23:49:10.268575 DQM0 = 93, DQM1 = 83
1362 23:49:10.268659 DQ Delay:
1363 23:49:10.272036 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1364 23:49:10.275381 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1365 23:49:10.278766 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1366 23:49:10.282206 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =88
1367 23:49:10.282294
1368 23:49:10.282359
1369 23:49:10.288644 [DQSOSCAuto] RK1, (LSB)MR18= 0x4010, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1370 23:49:10.291692 CH0 RK1: MR19=606, MR18=4010
1371 23:49:10.298806 CH0_RK1: MR19=0x606, MR18=0x4010, DQSOSC=393, MR23=63, INC=95, DEC=63
1372 23:49:10.302006 [RxdqsGatingPostProcess] freq 800
1373 23:49:10.308609 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1374 23:49:10.308706 Pre-setting of DQS Precalculation
1375 23:49:10.315434 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1376 23:49:10.315521 ==
1377 23:49:10.318832 Dram Type= 6, Freq= 0, CH_1, rank 0
1378 23:49:10.322354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 23:49:10.322439 ==
1380 23:49:10.328746 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1381 23:49:10.335055 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1382 23:49:10.343384 [CA 0] Center 36 (6~67) winsize 62
1383 23:49:10.346419 [CA 1] Center 36 (6~67) winsize 62
1384 23:49:10.349856 [CA 2] Center 34 (4~65) winsize 62
1385 23:49:10.353410 [CA 3] Center 34 (4~65) winsize 62
1386 23:49:10.356558 [CA 4] Center 34 (4~65) winsize 62
1387 23:49:10.360227 [CA 5] Center 34 (4~64) winsize 61
1388 23:49:10.360304
1389 23:49:10.363923 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1390 23:49:10.364014
1391 23:49:10.366718 [CATrainingPosCal] consider 1 rank data
1392 23:49:10.370168 u2DelayCellTimex100 = 270/100 ps
1393 23:49:10.373315 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1394 23:49:10.376822 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 23:49:10.383250 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1396 23:49:10.386646 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1397 23:49:10.389914 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1398 23:49:10.393234 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1399 23:49:10.393311
1400 23:49:10.396957 CA PerBit enable=1, Macro0, CA PI delay=34
1401 23:49:10.397035
1402 23:49:10.400203 [CBTSetCACLKResult] CA Dly = 34
1403 23:49:10.400308 CS Dly: 6 (0~37)
1404 23:49:10.400394 ==
1405 23:49:10.403149 Dram Type= 6, Freq= 0, CH_1, rank 1
1406 23:49:10.410358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 23:49:10.410448 ==
1408 23:49:10.413562 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 23:49:10.420314 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 23:49:10.430048 [CA 0] Center 36 (6~67) winsize 62
1411 23:49:10.433962 [CA 1] Center 37 (6~68) winsize 63
1412 23:49:10.437279 [CA 2] Center 35 (4~66) winsize 63
1413 23:49:10.441264 [CA 3] Center 35 (4~66) winsize 63
1414 23:49:10.445168 [CA 4] Center 35 (4~66) winsize 63
1415 23:49:10.445254 [CA 5] Center 34 (4~65) winsize 62
1416 23:49:10.445375
1417 23:49:10.448987 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1418 23:49:10.449070
1419 23:49:10.452639 [CATrainingPosCal] consider 2 rank data
1420 23:49:10.456605 u2DelayCellTimex100 = 270/100 ps
1421 23:49:10.459938 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1422 23:49:10.463195 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 23:49:10.466345 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1424 23:49:10.472869 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1425 23:49:10.476046 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1426 23:49:10.479874 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 23:49:10.479979
1428 23:49:10.483027 CA PerBit enable=1, Macro0, CA PI delay=34
1429 23:49:10.483110
1430 23:49:10.486085 [CBTSetCACLKResult] CA Dly = 34
1431 23:49:10.486173 CS Dly: 7 (0~39)
1432 23:49:10.486239
1433 23:49:10.489831 ----->DramcWriteLeveling(PI) begin...
1434 23:49:10.492822 ==
1435 23:49:10.492906 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 23:49:10.499337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 23:49:10.499450 ==
1438 23:49:10.503167 Write leveling (Byte 0): 25 => 25
1439 23:49:10.506485 Write leveling (Byte 1): 29 => 29
1440 23:49:10.506569 DramcWriteLeveling(PI) end<-----
1441 23:49:10.509625
1442 23:49:10.509709 ==
1443 23:49:10.513297 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 23:49:10.516645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 23:49:10.516744 ==
1446 23:49:10.519873 [Gating] SW mode calibration
1447 23:49:10.526306 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1448 23:49:10.529537 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1449 23:49:10.536710 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1450 23:49:10.539962 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1451 23:49:10.543127 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 23:49:10.549635 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 23:49:10.552865 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 23:49:10.556701 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:49:10.563119 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:49:10.566572 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:49:10.569575 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:49:10.576209 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:49:10.579515 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:49:10.583298 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:49:10.586623 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:49:10.593238 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:49:10.596647 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:49:10.599895 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:49:10.606574 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1466 23:49:10.609877 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1467 23:49:10.613136 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 23:49:10.620007 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:49:10.623212 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:49:10.626633 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:49:10.633272 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:49:10.636519 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:49:10.639772 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:49:10.646828 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
1475 23:49:10.650024 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1476 23:49:10.653349 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 23:49:10.656784 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 23:49:10.663784 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 23:49:10.666892 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 23:49:10.670033 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 23:49:10.677042 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1482 23:49:10.680436 0 10 4 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (1 0)
1483 23:49:10.683689 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1484 23:49:10.690153 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:49:10.693602 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:49:10.696905 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:49:10.703694 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:49:10.706956 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:49:10.710402 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 23:49:10.716986 0 11 4 | B1->B0 | 2929 3333 | 0 0 | (0 0) (0 0)
1491 23:49:10.720302 0 11 8 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
1492 23:49:10.723614 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 23:49:10.729890 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 23:49:10.733645 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:49:10.736710 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 23:49:10.740063 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 23:49:10.746679 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 23:49:10.750439 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1499 23:49:10.753867 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1500 23:49:10.760103 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 23:49:10.763578 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:49:10.767017 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:49:10.773519 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:49:10.776926 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:49:10.780390 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:49:10.786938 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:49:10.790270 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:49:10.793513 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:49:10.800797 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:49:10.804160 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:49:10.806902 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:49:10.810259 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:49:10.817009 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:49:10.820294 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1515 23:49:10.823750 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1516 23:49:10.827061 Total UI for P1: 0, mck2ui 16
1517 23:49:10.830390 best dqsien dly found for B1: ( 0, 14, 4)
1518 23:49:10.836977 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 23:49:10.837060 Total UI for P1: 0, mck2ui 16
1520 23:49:10.843627 best dqsien dly found for B0: ( 0, 14, 6)
1521 23:49:10.846979 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1522 23:49:10.850613 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1523 23:49:10.850699
1524 23:49:10.853546 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 23:49:10.857117 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1526 23:49:10.860394 [Gating] SW calibration Done
1527 23:49:10.860561 ==
1528 23:49:10.863639 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 23:49:10.867380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 23:49:10.867533 ==
1531 23:49:10.870768 RX Vref Scan: 0
1532 23:49:10.870869
1533 23:49:10.870966 RX Vref 0 -> 0, step: 1
1534 23:49:10.871027
1535 23:49:10.873780 RX Delay -130 -> 252, step: 16
1536 23:49:10.877355 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1537 23:49:10.884073 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1538 23:49:10.887276 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1539 23:49:10.891043 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1540 23:49:10.894094 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1541 23:49:10.897419 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1542 23:49:10.903713 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1543 23:49:10.907096 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1544 23:49:10.910791 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1545 23:49:10.913813 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1546 23:49:10.917283 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1547 23:49:10.923720 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1548 23:49:10.927127 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1549 23:49:10.930534 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1550 23:49:10.934007 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1551 23:49:10.937283 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1552 23:49:10.937368 ==
1553 23:49:10.940491 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 23:49:10.947719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 23:49:10.947808 ==
1556 23:49:10.947876 DQS Delay:
1557 23:49:10.950939 DQS0 = 0, DQS1 = 0
1558 23:49:10.951023 DQM Delay:
1559 23:49:10.951089 DQM0 = 92, DQM1 = 86
1560 23:49:10.954435 DQ Delay:
1561 23:49:10.957781 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1562 23:49:10.961147 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1563 23:49:10.964437 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1564 23:49:10.967868 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1565 23:49:10.967952
1566 23:49:10.968017
1567 23:49:10.968078 ==
1568 23:49:10.970613 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 23:49:10.973979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 23:49:10.974064 ==
1571 23:49:10.974129
1572 23:49:10.974190
1573 23:49:10.977323 TX Vref Scan disable
1574 23:49:10.977434 == TX Byte 0 ==
1575 23:49:10.984344 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1576 23:49:10.987706 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1577 23:49:10.987792 == TX Byte 1 ==
1578 23:49:10.994235 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1579 23:49:10.997572 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1580 23:49:10.997657 ==
1581 23:49:11.001334 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 23:49:11.004459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 23:49:11.004544 ==
1584 23:49:11.018629 TX Vref=22, minBit 0, minWin=26, winSum=435
1585 23:49:11.021701 TX Vref=24, minBit 1, minWin=26, winSum=440
1586 23:49:11.025244 TX Vref=26, minBit 0, minWin=27, winSum=444
1587 23:49:11.028601 TX Vref=28, minBit 1, minWin=27, winSum=446
1588 23:49:11.031975 TX Vref=30, minBit 1, minWin=27, winSum=450
1589 23:49:11.035498 TX Vref=32, minBit 0, minWin=27, winSum=444
1590 23:49:11.041800 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 30
1591 23:49:11.041902
1592 23:49:11.044945 Final TX Range 1 Vref 30
1593 23:49:11.045045
1594 23:49:11.045110 ==
1595 23:49:11.048826 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 23:49:11.051576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 23:49:11.051661 ==
1598 23:49:11.051726
1599 23:49:11.055248
1600 23:49:11.055331 TX Vref Scan disable
1601 23:49:11.058341 == TX Byte 0 ==
1602 23:49:11.061669 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1603 23:49:11.065742 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1604 23:49:11.068460 == TX Byte 1 ==
1605 23:49:11.071874 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1606 23:49:11.075177 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1607 23:49:11.075288
1608 23:49:11.078610 [DATLAT]
1609 23:49:11.078710 Freq=800, CH1 RK0
1610 23:49:11.078819
1611 23:49:11.081825 DATLAT Default: 0xa
1612 23:49:11.081907 0, 0xFFFF, sum = 0
1613 23:49:11.085615 1, 0xFFFF, sum = 0
1614 23:49:11.085700 2, 0xFFFF, sum = 0
1615 23:49:11.088944 3, 0xFFFF, sum = 0
1616 23:49:11.089052 4, 0xFFFF, sum = 0
1617 23:49:11.092386 5, 0xFFFF, sum = 0
1618 23:49:11.092471 6, 0xFFFF, sum = 0
1619 23:49:11.095743 7, 0xFFFF, sum = 0
1620 23:49:11.095827 8, 0xFFFF, sum = 0
1621 23:49:11.099205 9, 0x0, sum = 1
1622 23:49:11.099325 10, 0x0, sum = 2
1623 23:49:11.102521 11, 0x0, sum = 3
1624 23:49:11.102605 12, 0x0, sum = 4
1625 23:49:11.105896 best_step = 10
1626 23:49:11.105976
1627 23:49:11.106040 ==
1628 23:49:11.109302 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 23:49:11.112036 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 23:49:11.112168 ==
1631 23:49:11.115555 RX Vref Scan: 1
1632 23:49:11.115637
1633 23:49:11.115702 Set Vref Range= 32 -> 127
1634 23:49:11.115763
1635 23:49:11.118628 RX Vref 32 -> 127, step: 1
1636 23:49:11.118738
1637 23:49:11.122325 RX Delay -79 -> 252, step: 8
1638 23:49:11.122408
1639 23:49:11.125361 Set Vref, RX VrefLevel [Byte0]: 32
1640 23:49:11.128659 [Byte1]: 32
1641 23:49:11.128773
1642 23:49:11.131875 Set Vref, RX VrefLevel [Byte0]: 33
1643 23:49:11.135475 [Byte1]: 33
1644 23:49:11.138711
1645 23:49:11.138806 Set Vref, RX VrefLevel [Byte0]: 34
1646 23:49:11.141762 [Byte1]: 34
1647 23:49:11.146251
1648 23:49:11.146335 Set Vref, RX VrefLevel [Byte0]: 35
1649 23:49:11.149313 [Byte1]: 35
1650 23:49:11.153638
1651 23:49:11.153722 Set Vref, RX VrefLevel [Byte0]: 36
1652 23:49:11.157271 [Byte1]: 36
1653 23:49:11.161525
1654 23:49:11.161611 Set Vref, RX VrefLevel [Byte0]: 37
1655 23:49:11.164577 [Byte1]: 37
1656 23:49:11.168816
1657 23:49:11.168900 Set Vref, RX VrefLevel [Byte0]: 38
1658 23:49:11.172171 [Byte1]: 38
1659 23:49:11.176561
1660 23:49:11.176651 Set Vref, RX VrefLevel [Byte0]: 39
1661 23:49:11.179800 [Byte1]: 39
1662 23:49:11.184012
1663 23:49:11.184096 Set Vref, RX VrefLevel [Byte0]: 40
1664 23:49:11.187287 [Byte1]: 40
1665 23:49:11.191850
1666 23:49:11.191934 Set Vref, RX VrefLevel [Byte0]: 41
1667 23:49:11.195090 [Byte1]: 41
1668 23:49:11.198983
1669 23:49:11.199096 Set Vref, RX VrefLevel [Byte0]: 42
1670 23:49:11.202386 [Byte1]: 42
1671 23:49:11.206364
1672 23:49:11.206449 Set Vref, RX VrefLevel [Byte0]: 43
1673 23:49:11.210329 [Byte1]: 43
1674 23:49:11.214428
1675 23:49:11.214510 Set Vref, RX VrefLevel [Byte0]: 44
1676 23:49:11.217750 [Byte1]: 44
1677 23:49:11.221767
1678 23:49:11.221850 Set Vref, RX VrefLevel [Byte0]: 45
1679 23:49:11.224986 [Byte1]: 45
1680 23:49:11.229535
1681 23:49:11.229618 Set Vref, RX VrefLevel [Byte0]: 46
1682 23:49:11.233000 [Byte1]: 46
1683 23:49:11.236594
1684 23:49:11.236710 Set Vref, RX VrefLevel [Byte0]: 47
1685 23:49:11.240402 [Byte1]: 47
1686 23:49:11.244498
1687 23:49:11.244592 Set Vref, RX VrefLevel [Byte0]: 48
1688 23:49:11.247685 [Byte1]: 48
1689 23:49:11.252049
1690 23:49:11.252208 Set Vref, RX VrefLevel [Byte0]: 49
1691 23:49:11.255277 [Byte1]: 49
1692 23:49:11.259775
1693 23:49:11.260010 Set Vref, RX VrefLevel [Byte0]: 50
1694 23:49:11.263031 [Byte1]: 50
1695 23:49:11.267127
1696 23:49:11.267277 Set Vref, RX VrefLevel [Byte0]: 51
1697 23:49:11.270065 [Byte1]: 51
1698 23:49:11.274769
1699 23:49:11.274873 Set Vref, RX VrefLevel [Byte0]: 52
1700 23:49:11.278046 [Byte1]: 52
1701 23:49:11.282022
1702 23:49:11.282139 Set Vref, RX VrefLevel [Byte0]: 53
1703 23:49:11.285452 [Byte1]: 53
1704 23:49:11.289905
1705 23:49:11.289991 Set Vref, RX VrefLevel [Byte0]: 54
1706 23:49:11.292867 [Byte1]: 54
1707 23:49:11.297280
1708 23:49:11.297397 Set Vref, RX VrefLevel [Byte0]: 55
1709 23:49:11.300621 [Byte1]: 55
1710 23:49:11.304971
1711 23:49:11.305053 Set Vref, RX VrefLevel [Byte0]: 56
1712 23:49:11.308175 [Byte1]: 56
1713 23:49:11.312404
1714 23:49:11.312488 Set Vref, RX VrefLevel [Byte0]: 57
1715 23:49:11.315710 [Byte1]: 57
1716 23:49:11.319937
1717 23:49:11.320034 Set Vref, RX VrefLevel [Byte0]: 58
1718 23:49:11.322751 [Byte1]: 58
1719 23:49:11.327565
1720 23:49:11.327652 Set Vref, RX VrefLevel [Byte0]: 59
1721 23:49:11.330409 [Byte1]: 59
1722 23:49:11.335052
1723 23:49:11.335135 Set Vref, RX VrefLevel [Byte0]: 60
1724 23:49:11.338319 [Byte1]: 60
1725 23:49:11.342744
1726 23:49:11.342852 Set Vref, RX VrefLevel [Byte0]: 61
1727 23:49:11.345981 [Byte1]: 61
1728 23:49:11.349911
1729 23:49:11.349997 Set Vref, RX VrefLevel [Byte0]: 62
1730 23:49:11.353196 [Byte1]: 62
1731 23:49:11.357763
1732 23:49:11.357847 Set Vref, RX VrefLevel [Byte0]: 63
1733 23:49:11.360941 [Byte1]: 63
1734 23:49:11.365237
1735 23:49:11.365321 Set Vref, RX VrefLevel [Byte0]: 64
1736 23:49:11.368327 [Byte1]: 64
1737 23:49:11.372990
1738 23:49:11.373077 Set Vref, RX VrefLevel [Byte0]: 65
1739 23:49:11.375892 [Byte1]: 65
1740 23:49:11.379927
1741 23:49:11.380020 Set Vref, RX VrefLevel [Byte0]: 66
1742 23:49:11.383777 [Byte1]: 66
1743 23:49:11.387862
1744 23:49:11.387951 Set Vref, RX VrefLevel [Byte0]: 67
1745 23:49:11.391306 [Byte1]: 67
1746 23:49:11.395341
1747 23:49:11.395445 Set Vref, RX VrefLevel [Byte0]: 68
1748 23:49:11.398731 [Byte1]: 68
1749 23:49:11.402746
1750 23:49:11.402834 Set Vref, RX VrefLevel [Byte0]: 69
1751 23:49:11.405989 [Byte1]: 69
1752 23:49:11.410407
1753 23:49:11.410494 Set Vref, RX VrefLevel [Byte0]: 70
1754 23:49:11.413531 [Byte1]: 70
1755 23:49:11.418013
1756 23:49:11.418101 Set Vref, RX VrefLevel [Byte0]: 71
1757 23:49:11.421292 [Byte1]: 71
1758 23:49:11.425429
1759 23:49:11.425511 Set Vref, RX VrefLevel [Byte0]: 72
1760 23:49:11.429093 [Byte1]: 72
1761 23:49:11.433752
1762 23:49:11.433833 Set Vref, RX VrefLevel [Byte0]: 73
1763 23:49:11.436519 [Byte1]: 73
1764 23:49:11.440534
1765 23:49:11.440616 Set Vref, RX VrefLevel [Byte0]: 74
1766 23:49:11.443930 [Byte1]: 74
1767 23:49:11.448266
1768 23:49:11.448372 Set Vref, RX VrefLevel [Byte0]: 75
1769 23:49:11.451546 [Byte1]: 75
1770 23:49:11.455452
1771 23:49:11.455534 Set Vref, RX VrefLevel [Byte0]: 76
1772 23:49:11.458675 [Byte1]: 76
1773 23:49:11.463491
1774 23:49:11.463578 Final RX Vref Byte 0 = 54 to rank0
1775 23:49:11.466725 Final RX Vref Byte 1 = 59 to rank0
1776 23:49:11.469922 Final RX Vref Byte 0 = 54 to rank1
1777 23:49:11.473113 Final RX Vref Byte 1 = 59 to rank1==
1778 23:49:11.476268 Dram Type= 6, Freq= 0, CH_1, rank 0
1779 23:49:11.482945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1780 23:49:11.483037 ==
1781 23:49:11.483103 DQS Delay:
1782 23:49:11.483164 DQS0 = 0, DQS1 = 0
1783 23:49:11.486729 DQM Delay:
1784 23:49:11.486811 DQM0 = 95, DQM1 = 89
1785 23:49:11.489771 DQ Delay:
1786 23:49:11.493160 DQ0 =96, DQ1 =88, DQ2 =88, DQ3 =88
1787 23:49:11.496543 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1788 23:49:11.500040 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1789 23:49:11.503360 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1790 23:49:11.503477
1791 23:49:11.503566
1792 23:49:11.509692 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
1793 23:49:11.513225 CH1 RK0: MR19=606, MR18=2E4B
1794 23:49:11.520008 CH1_RK0: MR19=0x606, MR18=0x2E4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1795 23:49:11.520125
1796 23:49:11.523305 ----->DramcWriteLeveling(PI) begin...
1797 23:49:11.523413 ==
1798 23:49:11.526565 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 23:49:11.529832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 23:49:11.529919 ==
1801 23:49:11.533714 Write leveling (Byte 0): 30 => 30
1802 23:49:11.536842 Write leveling (Byte 1): 26 => 26
1803 23:49:11.539860 DramcWriteLeveling(PI) end<-----
1804 23:49:11.539945
1805 23:49:11.540030 ==
1806 23:49:11.542937 Dram Type= 6, Freq= 0, CH_1, rank 1
1807 23:49:11.546696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1808 23:49:11.546810 ==
1809 23:49:11.550088 [Gating] SW mode calibration
1810 23:49:11.556390 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1811 23:49:11.563240 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1812 23:49:11.566659 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1813 23:49:11.570082 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1814 23:49:11.576707 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 23:49:11.580215 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 23:49:11.583565 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 23:49:11.590054 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:49:11.593216 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:49:11.596337 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:49:11.603473 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 23:49:11.606956 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:49:11.609621 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:49:11.616532 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:49:11.619923 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:49:11.623436 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:49:11.626277 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:49:11.633046 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1828 23:49:11.636431 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1829 23:49:11.639811 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1830 23:49:11.646557 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 23:49:11.650303 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 23:49:11.653253 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:49:11.660227 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 23:49:11.663601 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:49:11.666549 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:49:11.673609 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:49:11.676942 0 9 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (1 1)
1838 23:49:11.680306 0 9 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
1839 23:49:11.686992 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 23:49:11.690367 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 23:49:11.693522 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 23:49:11.696878 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 23:49:11.703683 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1844 23:49:11.706688 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 23:49:11.710433 0 10 4 | B1->B0 | 2a2a 3030 | 1 0 | (1 0) (0 1)
1846 23:49:11.716761 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 23:49:11.720085 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 23:49:11.723564 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 23:49:11.730219 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 23:49:11.733590 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 23:49:11.736896 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:49:11.743478 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:49:11.746872 0 11 4 | B1->B0 | 3636 2c2c | 0 0 | (1 1) (0 0)
1854 23:49:11.750333 0 11 8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
1855 23:49:11.757046 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 23:49:11.760184 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 23:49:11.763561 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 23:49:11.770418 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 23:49:11.773736 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 23:49:11.777278 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 23:49:11.780368 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1862 23:49:11.786952 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1863 23:49:11.790675 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 23:49:11.794104 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 23:49:11.800858 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 23:49:11.804250 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 23:49:11.807470 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 23:49:11.814249 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 23:49:11.817521 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 23:49:11.820771 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 23:49:11.827174 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 23:49:11.830490 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 23:49:11.833742 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 23:49:11.840693 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 23:49:11.844306 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:49:11.847578 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:49:11.853808 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1878 23:49:11.857315 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1879 23:49:11.860935 Total UI for P1: 0, mck2ui 16
1880 23:49:11.863638 best dqsien dly found for B0: ( 0, 14, 6)
1881 23:49:11.867618 Total UI for P1: 0, mck2ui 16
1882 23:49:11.871097 best dqsien dly found for B1: ( 0, 14, 4)
1883 23:49:11.874446 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1884 23:49:11.877311 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1885 23:49:11.877417
1886 23:49:11.880605 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1887 23:49:11.884064 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1888 23:49:11.887515 [Gating] SW calibration Done
1889 23:49:11.887603 ==
1890 23:49:11.890874 Dram Type= 6, Freq= 0, CH_1, rank 1
1891 23:49:11.894249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1892 23:49:11.894368 ==
1893 23:49:11.897374 RX Vref Scan: 0
1894 23:49:11.897451
1895 23:49:11.897515 RX Vref 0 -> 0, step: 1
1896 23:49:11.897584
1897 23:49:11.900944 RX Delay -130 -> 252, step: 16
1898 23:49:11.904085 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1899 23:49:11.911044 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1900 23:49:11.914214 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1901 23:49:11.917556 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1902 23:49:11.920751 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1903 23:49:11.924278 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1904 23:49:11.930839 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1905 23:49:11.933991 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1906 23:49:11.938001 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1907 23:49:11.941166 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1908 23:49:11.944308 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1909 23:49:11.950878 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1910 23:49:11.954258 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1911 23:49:11.957844 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1912 23:49:11.961245 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1913 23:49:11.964613 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1914 23:49:11.964725 ==
1915 23:49:11.967916 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 23:49:11.974534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 23:49:11.974652 ==
1918 23:49:11.974753 DQS Delay:
1919 23:49:11.977954 DQS0 = 0, DQS1 = 0
1920 23:49:11.978069 DQM Delay:
1921 23:49:11.978172 DQM0 = 91, DQM1 = 86
1922 23:49:11.981423 DQ Delay:
1923 23:49:11.984923 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1924 23:49:11.988241 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1925 23:49:11.991600 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1926 23:49:11.995004 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1927 23:49:11.995116
1928 23:49:11.995216
1929 23:49:11.995315 ==
1930 23:49:11.997895 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 23:49:12.001447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 23:49:12.001557 ==
1933 23:49:12.001651
1934 23:49:12.001745
1935 23:49:12.004842 TX Vref Scan disable
1936 23:49:12.004944 == TX Byte 0 ==
1937 23:49:12.011646 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1938 23:49:12.015192 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1939 23:49:12.015298 == TX Byte 1 ==
1940 23:49:12.021711 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1941 23:49:12.024731 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1942 23:49:12.024841 ==
1943 23:49:12.028765 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 23:49:12.031978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 23:49:12.032091 ==
1946 23:49:12.045705 TX Vref=22, minBit 0, minWin=27, winSum=440
1947 23:49:12.049044 TX Vref=24, minBit 0, minWin=27, winSum=440
1948 23:49:12.052722 TX Vref=26, minBit 0, minWin=27, winSum=442
1949 23:49:12.055639 TX Vref=28, minBit 2, minWin=27, winSum=444
1950 23:49:12.059362 TX Vref=30, minBit 0, minWin=27, winSum=449
1951 23:49:12.062540 TX Vref=32, minBit 0, minWin=27, winSum=444
1952 23:49:12.069338 [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 30
1953 23:49:12.069453
1954 23:49:12.072409 Final TX Range 1 Vref 30
1955 23:49:12.072519
1956 23:49:12.072613 ==
1957 23:49:12.076269 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 23:49:12.079574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 23:49:12.079696 ==
1960 23:49:12.079795
1961 23:49:12.079870
1962 23:49:12.082827 TX Vref Scan disable
1963 23:49:12.086267 == TX Byte 0 ==
1964 23:49:12.089594 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1965 23:49:12.093055 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1966 23:49:12.095688 == TX Byte 1 ==
1967 23:49:12.099061 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1968 23:49:12.102570 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1969 23:49:12.102679
1970 23:49:12.106106 [DATLAT]
1971 23:49:12.106212 Freq=800, CH1 RK1
1972 23:49:12.106308
1973 23:49:12.109523 DATLAT Default: 0xa
1974 23:49:12.109634 0, 0xFFFF, sum = 0
1975 23:49:12.113100 1, 0xFFFF, sum = 0
1976 23:49:12.113225 2, 0xFFFF, sum = 0
1977 23:49:12.115812 3, 0xFFFF, sum = 0
1978 23:49:12.115923 4, 0xFFFF, sum = 0
1979 23:49:12.119232 5, 0xFFFF, sum = 0
1980 23:49:12.119344 6, 0xFFFF, sum = 0
1981 23:49:12.122612 7, 0xFFFF, sum = 0
1982 23:49:12.122725 8, 0xFFFF, sum = 0
1983 23:49:12.125959 9, 0x0, sum = 1
1984 23:49:12.126051 10, 0x0, sum = 2
1985 23:49:12.129322 11, 0x0, sum = 3
1986 23:49:12.129434 12, 0x0, sum = 4
1987 23:49:12.132383 best_step = 10
1988 23:49:12.132495
1989 23:49:12.132592 ==
1990 23:49:12.135907 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 23:49:12.139338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 23:49:12.139445 ==
1993 23:49:12.142788 RX Vref Scan: 0
1994 23:49:12.142895
1995 23:49:12.142991 RX Vref 0 -> 0, step: 1
1996 23:49:12.143081
1997 23:49:12.146208 RX Delay -79 -> 252, step: 8
1998 23:49:12.152971 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1999 23:49:12.155740 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2000 23:49:12.159285 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2001 23:49:12.162659 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2002 23:49:12.165918 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2003 23:49:12.169628 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2004 23:49:12.175810 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2005 23:49:12.179122 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2006 23:49:12.182326 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2007 23:49:12.186204 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2008 23:49:12.189278 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2009 23:49:12.196131 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2010 23:49:12.199829 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2011 23:49:12.203119 iDelay=209, Bit 13, Center 104 (9 ~ 200) 192
2012 23:49:12.206237 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2013 23:49:12.209089 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2014 23:49:12.209200 ==
2015 23:49:12.212532 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 23:49:12.219246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 23:49:12.219356 ==
2018 23:49:12.219431 DQS Delay:
2019 23:49:12.222554 DQS0 = 0, DQS1 = 0
2020 23:49:12.222662 DQM Delay:
2021 23:49:12.222757 DQM0 = 97, DQM1 = 91
2022 23:49:12.225879 DQ Delay:
2023 23:49:12.229320 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2024 23:49:12.232761 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2025 23:49:12.235862 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =88
2026 23:49:12.239554 DQ12 =100, DQ13 =104, DQ14 =96, DQ15 =96
2027 23:49:12.239662
2028 23:49:12.239777
2029 23:49:12.246136 [DQSOSCAuto] RK1, (LSB)MR18= 0x4610, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2030 23:49:12.249477 CH1 RK1: MR19=606, MR18=4610
2031 23:49:12.255701 CH1_RK1: MR19=0x606, MR18=0x4610, DQSOSC=392, MR23=63, INC=96, DEC=64
2032 23:49:12.259651 [RxdqsGatingPostProcess] freq 800
2033 23:49:12.262917 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2034 23:49:12.266382 Pre-setting of DQS Precalculation
2035 23:49:12.272416 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2036 23:49:12.279161 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2037 23:49:12.285960 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2038 23:49:12.286073
2039 23:49:12.286180
2040 23:49:12.289249 [Calibration Summary] 1600 Mbps
2041 23:49:12.292509 CH 0, Rank 0
2042 23:49:12.292621 SW Impedance : PASS
2043 23:49:12.296252 DUTY Scan : NO K
2044 23:49:12.296367 ZQ Calibration : PASS
2045 23:49:12.299169 Jitter Meter : NO K
2046 23:49:12.302712 CBT Training : PASS
2047 23:49:12.302829 Write leveling : PASS
2048 23:49:12.306259 RX DQS gating : PASS
2049 23:49:12.309273 RX DQ/DQS(RDDQC) : PASS
2050 23:49:12.309358 TX DQ/DQS : PASS
2051 23:49:12.312331 RX DATLAT : PASS
2052 23:49:12.316002 RX DQ/DQS(Engine): PASS
2053 23:49:12.316116 TX OE : NO K
2054 23:49:12.319223 All Pass.
2055 23:49:12.319340
2056 23:49:12.319452 CH 0, Rank 1
2057 23:49:12.322647 SW Impedance : PASS
2058 23:49:12.322761 DUTY Scan : NO K
2059 23:49:12.326141 ZQ Calibration : PASS
2060 23:49:12.329507 Jitter Meter : NO K
2061 23:49:12.329622 CBT Training : PASS
2062 23:49:12.332621 Write leveling : PASS
2063 23:49:12.332706 RX DQS gating : PASS
2064 23:49:12.335758 RX DQ/DQS(RDDQC) : PASS
2065 23:49:12.339096 TX DQ/DQS : PASS
2066 23:49:12.339208 RX DATLAT : PASS
2067 23:49:12.342910 RX DQ/DQS(Engine): PASS
2068 23:49:12.345890 TX OE : NO K
2069 23:49:12.346008 All Pass.
2070 23:49:12.346104
2071 23:49:12.346195 CH 1, Rank 0
2072 23:49:12.349070 SW Impedance : PASS
2073 23:49:12.353201 DUTY Scan : NO K
2074 23:49:12.353288 ZQ Calibration : PASS
2075 23:49:12.355947 Jitter Meter : NO K
2076 23:49:12.359340 CBT Training : PASS
2077 23:49:12.359425 Write leveling : PASS
2078 23:49:12.363134 RX DQS gating : PASS
2079 23:49:12.366550 RX DQ/DQS(RDDQC) : PASS
2080 23:49:12.366663 TX DQ/DQS : PASS
2081 23:49:12.369374 RX DATLAT : PASS
2082 23:49:12.369485 RX DQ/DQS(Engine): PASS
2083 23:49:12.372803 TX OE : NO K
2084 23:49:12.372891 All Pass.
2085 23:49:12.372958
2086 23:49:12.376666 CH 1, Rank 1
2087 23:49:12.376773 SW Impedance : PASS
2088 23:49:12.379306 DUTY Scan : NO K
2089 23:49:12.383354 ZQ Calibration : PASS
2090 23:49:12.383449 Jitter Meter : NO K
2091 23:49:12.386002 CBT Training : PASS
2092 23:49:12.389934 Write leveling : PASS
2093 23:49:12.390037 RX DQS gating : PASS
2094 23:49:12.393114 RX DQ/DQS(RDDQC) : PASS
2095 23:49:12.396412 TX DQ/DQS : PASS
2096 23:49:12.396518 RX DATLAT : PASS
2097 23:49:12.399879 RX DQ/DQS(Engine): PASS
2098 23:49:12.399980 TX OE : NO K
2099 23:49:12.403270 All Pass.
2100 23:49:12.403366
2101 23:49:12.403430 DramC Write-DBI off
2102 23:49:12.406615 PER_BANK_REFRESH: Hybrid Mode
2103 23:49:12.410029 TX_TRACKING: ON
2104 23:49:12.413285 [GetDramInforAfterCalByMRR] Vendor 6.
2105 23:49:12.416489 [GetDramInforAfterCalByMRR] Revision 606.
2106 23:49:12.419479 [GetDramInforAfterCalByMRR] Revision 2 0.
2107 23:49:12.419587 MR0 0x3b3b
2108 23:49:12.419677 MR8 0x5151
2109 23:49:12.426758 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 23:49:12.426879
2111 23:49:12.426988 MR0 0x3b3b
2112 23:49:12.427099 MR8 0x5151
2113 23:49:12.430062 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 23:49:12.430175
2115 23:49:12.439826 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2116 23:49:12.442765 [FAST_K] Save calibration result to emmc
2117 23:49:12.446629 [FAST_K] Save calibration result to emmc
2118 23:49:12.449759 dram_init: config_dvfs: 1
2119 23:49:12.452886 dramc_set_vcore_voltage set vcore to 662500
2120 23:49:12.456303 Read voltage for 1200, 2
2121 23:49:12.456423 Vio18 = 0
2122 23:49:12.456519 Vcore = 662500
2123 23:49:12.459387 Vdram = 0
2124 23:49:12.459496 Vddq = 0
2125 23:49:12.459563 Vmddr = 0
2126 23:49:12.466143 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2127 23:49:12.469818 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2128 23:49:12.472904 MEM_TYPE=3, freq_sel=15
2129 23:49:12.476319 sv_algorithm_assistance_LP4_1600
2130 23:49:12.479768 ============ PULL DRAM RESETB DOWN ============
2131 23:49:12.486188 ========== PULL DRAM RESETB DOWN end =========
2132 23:49:12.489778 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2133 23:49:12.493034 ===================================
2134 23:49:12.496305 LPDDR4 DRAM CONFIGURATION
2135 23:49:12.499668 ===================================
2136 23:49:12.499785 EX_ROW_EN[0] = 0x0
2137 23:49:12.503022 EX_ROW_EN[1] = 0x0
2138 23:49:12.503133 LP4Y_EN = 0x0
2139 23:49:12.506648 WORK_FSP = 0x0
2140 23:49:12.506768 WL = 0x4
2141 23:49:12.510081 RL = 0x4
2142 23:49:12.510200 BL = 0x2
2143 23:49:12.512830 RPST = 0x0
2144 23:49:12.512947 RD_PRE = 0x0
2145 23:49:12.516018 WR_PRE = 0x1
2146 23:49:12.516141 WR_PST = 0x0
2147 23:49:12.519869 DBI_WR = 0x0
2148 23:49:12.519994 DBI_RD = 0x0
2149 23:49:12.522649 OTF = 0x1
2150 23:49:12.526711 ===================================
2151 23:49:12.529853 ===================================
2152 23:49:12.529971 ANA top config
2153 23:49:12.532907 ===================================
2154 23:49:12.536278 DLL_ASYNC_EN = 0
2155 23:49:12.539748 ALL_SLAVE_EN = 0
2156 23:49:12.542988 NEW_RANK_MODE = 1
2157 23:49:12.543076 DLL_IDLE_MODE = 1
2158 23:49:12.546369 LP45_APHY_COMB_EN = 1
2159 23:49:12.549757 TX_ODT_DIS = 1
2160 23:49:12.553133 NEW_8X_MODE = 1
2161 23:49:12.556475 ===================================
2162 23:49:12.559673 ===================================
2163 23:49:12.563574 data_rate = 2400
2164 23:49:12.563672 CKR = 1
2165 23:49:12.566797 DQ_P2S_RATIO = 8
2166 23:49:12.570107 ===================================
2167 23:49:12.573320 CA_P2S_RATIO = 8
2168 23:49:12.576308 DQ_CA_OPEN = 0
2169 23:49:12.579813 DQ_SEMI_OPEN = 0
2170 23:49:12.579928 CA_SEMI_OPEN = 0
2171 23:49:12.583239 CA_FULL_RATE = 0
2172 23:49:12.586653 DQ_CKDIV4_EN = 0
2173 23:49:12.590044 CA_CKDIV4_EN = 0
2174 23:49:12.592988 CA_PREDIV_EN = 0
2175 23:49:12.596381 PH8_DLY = 17
2176 23:49:12.596493 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2177 23:49:12.600040 DQ_AAMCK_DIV = 4
2178 23:49:12.603254 CA_AAMCK_DIV = 4
2179 23:49:12.606602 CA_ADMCK_DIV = 4
2180 23:49:12.610031 DQ_TRACK_CA_EN = 0
2181 23:49:12.613371 CA_PICK = 1200
2182 23:49:12.616677 CA_MCKIO = 1200
2183 23:49:12.616763 MCKIO_SEMI = 0
2184 23:49:12.619960 PLL_FREQ = 2366
2185 23:49:12.623207 DQ_UI_PI_RATIO = 32
2186 23:49:12.626485 CA_UI_PI_RATIO = 0
2187 23:49:12.630350 ===================================
2188 23:49:12.633470 ===================================
2189 23:49:12.636674 memory_type:LPDDR4
2190 23:49:12.636759 GP_NUM : 10
2191 23:49:12.640466 SRAM_EN : 1
2192 23:49:12.640553 MD32_EN : 0
2193 23:49:12.643787 ===================================
2194 23:49:12.647332 [ANA_INIT] >>>>>>>>>>>>>>
2195 23:49:12.649993 <<<<<< [CONFIGURE PHASE]: ANA_TX
2196 23:49:12.653520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2197 23:49:12.656948 ===================================
2198 23:49:12.660413 data_rate = 2400,PCW = 0X5b00
2199 23:49:12.663918 ===================================
2200 23:49:12.666673 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2201 23:49:12.670551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 23:49:12.676536 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 23:49:12.683615 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2204 23:49:12.687026 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2205 23:49:12.690316 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2206 23:49:12.690394 [ANA_INIT] flow start
2207 23:49:12.693631 [ANA_INIT] PLL >>>>>>>>
2208 23:49:12.696650 [ANA_INIT] PLL <<<<<<<<
2209 23:49:12.696734 [ANA_INIT] MIDPI >>>>>>>>
2210 23:49:12.700317 [ANA_INIT] MIDPI <<<<<<<<
2211 23:49:12.703224 [ANA_INIT] DLL >>>>>>>>
2212 23:49:12.703307 [ANA_INIT] DLL <<<<<<<<
2213 23:49:12.706530 [ANA_INIT] flow end
2214 23:49:12.710095 ============ LP4 DIFF to SE enter ============
2215 23:49:12.713773 ============ LP4 DIFF to SE exit ============
2216 23:49:12.716741 [ANA_INIT] <<<<<<<<<<<<<
2217 23:49:12.719809 [Flow] Enable top DCM control >>>>>
2218 23:49:12.723193 [Flow] Enable top DCM control <<<<<
2219 23:49:12.726551 Enable DLL master slave shuffle
2220 23:49:12.733870 ==============================================================
2221 23:49:12.733957 Gating Mode config
2222 23:49:12.740030 ==============================================================
2223 23:49:12.740121 Config description:
2224 23:49:12.750408 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2225 23:49:12.757153 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2226 23:49:12.763285 SELPH_MODE 0: By rank 1: By Phase
2227 23:49:12.766690 ==============================================================
2228 23:49:12.769988 GAT_TRACK_EN = 1
2229 23:49:12.773877 RX_GATING_MODE = 2
2230 23:49:12.777179 RX_GATING_TRACK_MODE = 2
2231 23:49:12.780448 SELPH_MODE = 1
2232 23:49:12.783893 PICG_EARLY_EN = 1
2233 23:49:12.787262 VALID_LAT_VALUE = 1
2234 23:49:12.789994 ==============================================================
2235 23:49:12.793425 Enter into Gating configuration >>>>
2236 23:49:12.796870 Exit from Gating configuration <<<<
2237 23:49:12.800290 Enter into DVFS_PRE_config >>>>>
2238 23:49:12.813408 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2239 23:49:12.817190 Exit from DVFS_PRE_config <<<<<
2240 23:49:12.820116 Enter into PICG configuration >>>>
2241 23:49:12.820238 Exit from PICG configuration <<<<
2242 23:49:12.823638 [RX_INPUT] configuration >>>>>
2243 23:49:12.827140 [RX_INPUT] configuration <<<<<
2244 23:49:12.833825 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2245 23:49:12.836877 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2246 23:49:12.843403 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 23:49:12.850264 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 23:49:12.857005 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 23:49:12.863839 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 23:49:12.867295 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2251 23:49:12.870627 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2252 23:49:12.873347 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2253 23:49:12.880220 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2254 23:49:12.883681 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2255 23:49:12.886909 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2256 23:49:12.890268 ===================================
2257 23:49:12.893677 LPDDR4 DRAM CONFIGURATION
2258 23:49:12.897045 ===================================
2259 23:49:12.897148 EX_ROW_EN[0] = 0x0
2260 23:49:12.900219 EX_ROW_EN[1] = 0x0
2261 23:49:12.903720 LP4Y_EN = 0x0
2262 23:49:12.903829 WORK_FSP = 0x0
2263 23:49:12.907036 WL = 0x4
2264 23:49:12.907128 RL = 0x4
2265 23:49:12.910404 BL = 0x2
2266 23:49:12.910483 RPST = 0x0
2267 23:49:12.913613 RD_PRE = 0x0
2268 23:49:12.913782 WR_PRE = 0x1
2269 23:49:12.917440 WR_PST = 0x0
2270 23:49:12.917513 DBI_WR = 0x0
2271 23:49:12.920804 DBI_RD = 0x0
2272 23:49:12.920891 OTF = 0x1
2273 23:49:12.923522 ===================================
2274 23:49:12.926902 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2275 23:49:12.933629 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2276 23:49:12.937542 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2277 23:49:12.940674 ===================================
2278 23:49:12.943780 LPDDR4 DRAM CONFIGURATION
2279 23:49:12.947314 ===================================
2280 23:49:12.947413 EX_ROW_EN[0] = 0x10
2281 23:49:12.950348 EX_ROW_EN[1] = 0x0
2282 23:49:12.950431 LP4Y_EN = 0x0
2283 23:49:12.953881 WORK_FSP = 0x0
2284 23:49:12.953974 WL = 0x4
2285 23:49:12.957478 RL = 0x4
2286 23:49:12.957567 BL = 0x2
2287 23:49:12.960751 RPST = 0x0
2288 23:49:12.960862 RD_PRE = 0x0
2289 23:49:12.964316 WR_PRE = 0x1
2290 23:49:12.964407 WR_PST = 0x0
2291 23:49:12.967379 DBI_WR = 0x0
2292 23:49:12.971036 DBI_RD = 0x0
2293 23:49:12.971145 OTF = 0x1
2294 23:49:12.974333 ===================================
2295 23:49:12.980970 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2296 23:49:12.981063 ==
2297 23:49:12.984202 Dram Type= 6, Freq= 0, CH_0, rank 0
2298 23:49:12.987655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2299 23:49:12.987736 ==
2300 23:49:12.990906 [Duty_Offset_Calibration]
2301 23:49:12.990980 B0:2 B1:1 CA:1
2302 23:49:12.991048
2303 23:49:12.994146 [DutyScan_Calibration_Flow] k_type=0
2304 23:49:13.004719
2305 23:49:13.004800 ==CLK 0==
2306 23:49:13.007949 Final CLK duty delay cell = 0
2307 23:49:13.011352 [0] MAX Duty = 5218%(X100), DQS PI = 24
2308 23:49:13.014713 [0] MIN Duty = 4875%(X100), DQS PI = 0
2309 23:49:13.014792 [0] AVG Duty = 5046%(X100)
2310 23:49:13.017994
2311 23:49:13.018096 CH0 CLK Duty spec in!! Max-Min= 343%
2312 23:49:13.025141 [DutyScan_Calibration_Flow] ====Done====
2313 23:49:13.025222
2314 23:49:13.028405 [DutyScan_Calibration_Flow] k_type=1
2315 23:49:13.043621
2316 23:49:13.043735 ==DQS 0 ==
2317 23:49:13.046760 Final DQS duty delay cell = -4
2318 23:49:13.050079 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2319 23:49:13.053653 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2320 23:49:13.056777 [-4] AVG Duty = 4937%(X100)
2321 23:49:13.056867
2322 23:49:13.056933 ==DQS 1 ==
2323 23:49:13.059798 Final DQS duty delay cell = 0
2324 23:49:13.063571 [0] MAX Duty = 5156%(X100), DQS PI = 62
2325 23:49:13.066526 [0] MIN Duty = 5000%(X100), DQS PI = 32
2326 23:49:13.070284 [0] AVG Duty = 5078%(X100)
2327 23:49:13.070407
2328 23:49:13.073647 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2329 23:49:13.073759
2330 23:49:13.076899 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2331 23:49:13.080114 [DutyScan_Calibration_Flow] ====Done====
2332 23:49:13.080225
2333 23:49:13.083148 [DutyScan_Calibration_Flow] k_type=3
2334 23:49:13.100085
2335 23:49:13.100173 ==DQM 0 ==
2336 23:49:13.103361 Final DQM duty delay cell = 0
2337 23:49:13.106588 [0] MAX Duty = 5156%(X100), DQS PI = 30
2338 23:49:13.109829 [0] MIN Duty = 4906%(X100), DQS PI = 52
2339 23:49:13.113113 [0] AVG Duty = 5031%(X100)
2340 23:49:13.113196
2341 23:49:13.113262 ==DQM 1 ==
2342 23:49:13.117156 Final DQM duty delay cell = 0
2343 23:49:13.120443 [0] MAX Duty = 5093%(X100), DQS PI = 0
2344 23:49:13.123746 [0] MIN Duty = 5031%(X100), DQS PI = 14
2345 23:49:13.123827 [0] AVG Duty = 5062%(X100)
2346 23:49:13.126923
2347 23:49:13.130303 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2348 23:49:13.130387
2349 23:49:13.133671 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2350 23:49:13.136942 [DutyScan_Calibration_Flow] ====Done====
2351 23:49:13.137049
2352 23:49:13.140117 [DutyScan_Calibration_Flow] k_type=2
2353 23:49:13.156728
2354 23:49:13.156814 ==DQ 0 ==
2355 23:49:13.159814 Final DQ duty delay cell = 0
2356 23:49:13.163660 [0] MAX Duty = 5031%(X100), DQS PI = 26
2357 23:49:13.166413 [0] MIN Duty = 4875%(X100), DQS PI = 62
2358 23:49:13.166540 [0] AVG Duty = 4953%(X100)
2359 23:49:13.166638
2360 23:49:13.170092 ==DQ 1 ==
2361 23:49:13.173344 Final DQ duty delay cell = 0
2362 23:49:13.176579 [0] MAX Duty = 5093%(X100), DQS PI = 24
2363 23:49:13.179787 [0] MIN Duty = 4907%(X100), DQS PI = 36
2364 23:49:13.179870 [0] AVG Duty = 5000%(X100)
2365 23:49:13.179935
2366 23:49:13.183154 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2367 23:49:13.183262
2368 23:49:13.186563 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2369 23:49:13.193723 [DutyScan_Calibration_Flow] ====Done====
2370 23:49:13.193805 ==
2371 23:49:13.196751 Dram Type= 6, Freq= 0, CH_1, rank 0
2372 23:49:13.199872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 23:49:13.199971 ==
2374 23:49:13.203544 [Duty_Offset_Calibration]
2375 23:49:13.203664 B0:1 B1:0 CA:0
2376 23:49:13.203747
2377 23:49:13.206583 [DutyScan_Calibration_Flow] k_type=0
2378 23:49:13.215604
2379 23:49:13.215724 ==CLK 0==
2380 23:49:13.218913 Final CLK duty delay cell = -4
2381 23:49:13.222342 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2382 23:49:13.226024 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2383 23:49:13.229200 [-4] AVG Duty = 4969%(X100)
2384 23:49:13.229289
2385 23:49:13.232609 CH1 CLK Duty spec in!! Max-Min= 124%
2386 23:49:13.236128 [DutyScan_Calibration_Flow] ====Done====
2387 23:49:13.236240
2388 23:49:13.238781 [DutyScan_Calibration_Flow] k_type=1
2389 23:49:13.255937
2390 23:49:13.256057 ==DQS 0 ==
2391 23:49:13.264217 Final DQS duty delay cell = 0
2392 23:49:13.264415 [0] MAX Duty = 5062%(X100), DQS PI = 14
2393 23:49:13.265843 [0] MIN Duty = 4844%(X100), DQS PI = 0
2394 23:49:13.265930 [0] AVG Duty = 4953%(X100)
2395 23:49:13.268883
2396 23:49:13.269010 ==DQS 1 ==
2397 23:49:13.272141 Final DQS duty delay cell = 0
2398 23:49:13.275627 [0] MAX Duty = 5187%(X100), DQS PI = 18
2399 23:49:13.278740 [0] MIN Duty = 4969%(X100), DQS PI = 8
2400 23:49:13.278825 [0] AVG Duty = 5078%(X100)
2401 23:49:13.278922
2402 23:49:13.285611 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2403 23:49:13.285725
2404 23:49:13.289272 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2405 23:49:13.292660 [DutyScan_Calibration_Flow] ====Done====
2406 23:49:13.292786
2407 23:49:13.295955 [DutyScan_Calibration_Flow] k_type=3
2408 23:49:13.312271
2409 23:49:13.312453 ==DQM 0 ==
2410 23:49:13.316044 Final DQM duty delay cell = 0
2411 23:49:13.318754 [0] MAX Duty = 5156%(X100), DQS PI = 6
2412 23:49:13.322057 [0] MIN Duty = 5000%(X100), DQS PI = 62
2413 23:49:13.322188 [0] AVG Duty = 5078%(X100)
2414 23:49:13.322290
2415 23:49:13.325808 ==DQM 1 ==
2416 23:49:13.329097 Final DQM duty delay cell = 0
2417 23:49:13.332295 [0] MAX Duty = 5031%(X100), DQS PI = 24
2418 23:49:13.335497 [0] MIN Duty = 4875%(X100), DQS PI = 38
2419 23:49:13.335617 [0] AVG Duty = 4953%(X100)
2420 23:49:13.338854
2421 23:49:13.342779 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2422 23:49:13.342948
2423 23:49:13.345501 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2424 23:49:13.348914 [DutyScan_Calibration_Flow] ====Done====
2425 23:49:13.349068
2426 23:49:13.352157 [DutyScan_Calibration_Flow] k_type=2
2427 23:49:13.368279
2428 23:49:13.368511 ==DQ 0 ==
2429 23:49:13.371495 Final DQ duty delay cell = -4
2430 23:49:13.374746 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2431 23:49:13.377734 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2432 23:49:13.377883 [-4] AVG Duty = 5000%(X100)
2433 23:49:13.381487
2434 23:49:13.381632 ==DQ 1 ==
2435 23:49:13.384617 Final DQ duty delay cell = 0
2436 23:49:13.387918 [0] MAX Duty = 5125%(X100), DQS PI = 20
2437 23:49:13.391158 [0] MIN Duty = 4969%(X100), DQS PI = 10
2438 23:49:13.391304 [0] AVG Duty = 5047%(X100)
2439 23:49:13.391403
2440 23:49:13.394919 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2441 23:49:13.397984
2442 23:49:13.401305 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2443 23:49:13.404588 [DutyScan_Calibration_Flow] ====Done====
2444 23:49:13.408078 nWR fixed to 30
2445 23:49:13.408214 [ModeRegInit_LP4] CH0 RK0
2446 23:49:13.411397 [ModeRegInit_LP4] CH0 RK1
2447 23:49:13.414799 [ModeRegInit_LP4] CH1 RK0
2448 23:49:13.414923 [ModeRegInit_LP4] CH1 RK1
2449 23:49:13.418172 match AC timing 7
2450 23:49:13.421366 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2451 23:49:13.424864 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2452 23:49:13.431100 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2453 23:49:13.434850 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2454 23:49:13.441337 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2455 23:49:13.441514 ==
2456 23:49:13.444473 Dram Type= 6, Freq= 0, CH_0, rank 0
2457 23:49:13.447974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2458 23:49:13.448069 ==
2459 23:49:13.454745 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2460 23:49:13.457911 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2461 23:49:13.467907 [CA 0] Center 39 (8~70) winsize 63
2462 23:49:13.471342 [CA 1] Center 39 (8~70) winsize 63
2463 23:49:13.474631 [CA 2] Center 35 (5~66) winsize 62
2464 23:49:13.478021 [CA 3] Center 34 (4~65) winsize 62
2465 23:49:13.481218 [CA 4] Center 33 (3~64) winsize 62
2466 23:49:13.485025 [CA 5] Center 32 (3~62) winsize 60
2467 23:49:13.485145
2468 23:49:13.488099 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2469 23:49:13.488217
2470 23:49:13.491230 [CATrainingPosCal] consider 1 rank data
2471 23:49:13.495012 u2DelayCellTimex100 = 270/100 ps
2472 23:49:13.498092 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2473 23:49:13.501258 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2474 23:49:13.508118 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2475 23:49:13.511543 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2476 23:49:13.514887 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2477 23:49:13.518302 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2478 23:49:13.518395
2479 23:49:13.521083 CA PerBit enable=1, Macro0, CA PI delay=32
2480 23:49:13.521174
2481 23:49:13.524392 [CBTSetCACLKResult] CA Dly = 32
2482 23:49:13.524485 CS Dly: 6 (0~37)
2483 23:49:13.528432 ==
2484 23:49:13.528556 Dram Type= 6, Freq= 0, CH_0, rank 1
2485 23:49:13.534409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2486 23:49:13.534521 ==
2487 23:49:13.537683 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2488 23:49:13.544539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2489 23:49:13.553860 [CA 0] Center 38 (8~69) winsize 62
2490 23:49:13.556876 [CA 1] Center 38 (8~69) winsize 62
2491 23:49:13.560324 [CA 2] Center 35 (5~66) winsize 62
2492 23:49:13.564236 [CA 3] Center 34 (4~65) winsize 62
2493 23:49:13.567414 [CA 4] Center 33 (3~64) winsize 62
2494 23:49:13.570368 [CA 5] Center 32 (3~62) winsize 60
2495 23:49:13.570452
2496 23:49:13.573622 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2497 23:49:13.573706
2498 23:49:13.577472 [CATrainingPosCal] consider 2 rank data
2499 23:49:13.580481 u2DelayCellTimex100 = 270/100 ps
2500 23:49:13.584157 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2501 23:49:13.587366 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2502 23:49:13.593836 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2503 23:49:13.597026 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2504 23:49:13.600640 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2505 23:49:13.603916 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2506 23:49:13.603997
2507 23:49:13.607180 CA PerBit enable=1, Macro0, CA PI delay=32
2508 23:49:13.607256
2509 23:49:13.610429 [CBTSetCACLKResult] CA Dly = 32
2510 23:49:13.610516 CS Dly: 6 (0~38)
2511 23:49:13.610581
2512 23:49:13.614391 ----->DramcWriteLeveling(PI) begin...
2513 23:49:13.614482 ==
2514 23:49:13.617491 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 23:49:13.624269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 23:49:13.624379 ==
2517 23:49:13.627719 Write leveling (Byte 0): 33 => 33
2518 23:49:13.630998 Write leveling (Byte 1): 28 => 28
2519 23:49:13.631079 DramcWriteLeveling(PI) end<-----
2520 23:49:13.633719
2521 23:49:13.633799 ==
2522 23:49:13.637086 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 23:49:13.640325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 23:49:13.640424 ==
2525 23:49:13.644245 [Gating] SW mode calibration
2526 23:49:13.650994 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2527 23:49:13.653758 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2528 23:49:13.661007 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2529 23:49:13.664287 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
2530 23:49:13.667681 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 23:49:13.674429 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 23:49:13.677648 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 23:49:13.680733 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 23:49:13.687765 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
2535 23:49:13.691385 0 15 28 | B1->B0 | 3434 2424 | 0 0 | (0 0) (0 1)
2536 23:49:13.694078 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2537 23:49:13.697353 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2538 23:49:13.704281 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 23:49:13.707429 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 23:49:13.711607 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 23:49:13.717707 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 23:49:13.721253 1 0 24 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (1 1)
2543 23:49:13.724275 1 0 28 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
2544 23:49:13.730938 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2545 23:49:13.734274 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2546 23:49:13.737872 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 23:49:13.744209 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 23:49:13.747444 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 23:49:13.750709 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 23:49:13.757822 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 23:49:13.761078 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2552 23:49:13.764307 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2553 23:49:13.771113 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 23:49:13.774066 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 23:49:13.777907 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 23:49:13.784590 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 23:49:13.787993 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 23:49:13.791028 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 23:49:13.794299 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 23:49:13.800785 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 23:49:13.804242 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 23:49:13.808006 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 23:49:13.814026 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 23:49:13.817289 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 23:49:13.820694 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 23:49:13.827624 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2567 23:49:13.830774 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2568 23:49:13.834245 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2569 23:49:13.837702 Total UI for P1: 0, mck2ui 16
2570 23:49:13.841205 best dqsien dly found for B0: ( 1, 3, 26)
2571 23:49:13.847555 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 23:49:13.847645 Total UI for P1: 0, mck2ui 16
2573 23:49:13.854245 best dqsien dly found for B1: ( 1, 4, 0)
2574 23:49:13.857537 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2575 23:49:13.861121 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2576 23:49:13.861204
2577 23:49:13.864301 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2578 23:49:13.867864 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2579 23:49:13.871029 [Gating] SW calibration Done
2580 23:49:13.871107 ==
2581 23:49:13.874701 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 23:49:13.878050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 23:49:13.878128 ==
2584 23:49:13.881237 RX Vref Scan: 0
2585 23:49:13.881336
2586 23:49:13.881401 RX Vref 0 -> 0, step: 1
2587 23:49:13.881463
2588 23:49:13.884600 RX Delay -40 -> 252, step: 8
2589 23:49:13.887827 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2590 23:49:13.894439 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2591 23:49:13.897677 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2592 23:49:13.900973 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2593 23:49:13.904389 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2594 23:49:13.907748 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2595 23:49:13.910818 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2596 23:49:13.917430 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2597 23:49:13.920749 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2598 23:49:13.924172 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2599 23:49:13.927980 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2600 23:49:13.931302 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2601 23:49:13.937835 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2602 23:49:13.941028 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2603 23:49:13.944195 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2604 23:49:13.947536 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2605 23:49:13.947643 ==
2606 23:49:13.950748 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 23:49:13.957847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 23:49:13.957932 ==
2609 23:49:13.957998 DQS Delay:
2610 23:49:13.958061 DQS0 = 0, DQS1 = 0
2611 23:49:13.961156 DQM Delay:
2612 23:49:13.961361 DQM0 = 121, DQM1 = 113
2613 23:49:13.964262 DQ Delay:
2614 23:49:13.967996 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2615 23:49:13.971439 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2616 23:49:13.974648 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2617 23:49:13.977860 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2618 23:49:13.977943
2619 23:49:13.978008
2620 23:49:13.978067 ==
2621 23:49:13.981631 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 23:49:13.984708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 23:49:13.984787 ==
2624 23:49:13.988227
2625 23:49:13.988325
2626 23:49:13.988445 TX Vref Scan disable
2627 23:49:13.991371 == TX Byte 0 ==
2628 23:49:13.994341 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2629 23:49:13.997642 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2630 23:49:14.001426 == TX Byte 1 ==
2631 23:49:14.004654 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2632 23:49:14.007816 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2633 23:49:14.007897 ==
2634 23:49:14.011046 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 23:49:14.017528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 23:49:14.017613 ==
2637 23:49:14.028647 TX Vref=22, minBit 10, minWin=24, winSum=403
2638 23:49:14.031886 TX Vref=24, minBit 1, minWin=25, winSum=414
2639 23:49:14.035246 TX Vref=26, minBit 7, minWin=25, winSum=417
2640 23:49:14.038620 TX Vref=28, minBit 10, minWin=25, winSum=422
2641 23:49:14.041821 TX Vref=30, minBit 0, minWin=26, winSum=422
2642 23:49:14.048983 TX Vref=32, minBit 10, minWin=25, winSum=419
2643 23:49:14.052249 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 30
2644 23:49:14.052386
2645 23:49:14.055366 Final TX Range 1 Vref 30
2646 23:49:14.055446
2647 23:49:14.055510 ==
2648 23:49:14.058621 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 23:49:14.062470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 23:49:14.062581 ==
2651 23:49:14.062686
2652 23:49:14.065669
2653 23:49:14.065753 TX Vref Scan disable
2654 23:49:14.069146 == TX Byte 0 ==
2655 23:49:14.072281 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2656 23:49:14.075546 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2657 23:49:14.078899 == TX Byte 1 ==
2658 23:49:14.082047 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2659 23:49:14.085708 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2660 23:49:14.085802
2661 23:49:14.089056 [DATLAT]
2662 23:49:14.089136 Freq=1200, CH0 RK0
2663 23:49:14.089200
2664 23:49:14.092678 DATLAT Default: 0xd
2665 23:49:14.092752 0, 0xFFFF, sum = 0
2666 23:49:14.095658 1, 0xFFFF, sum = 0
2667 23:49:14.095734 2, 0xFFFF, sum = 0
2668 23:49:14.098961 3, 0xFFFF, sum = 0
2669 23:49:14.099035 4, 0xFFFF, sum = 0
2670 23:49:14.102101 5, 0xFFFF, sum = 0
2671 23:49:14.102177 6, 0xFFFF, sum = 0
2672 23:49:14.105377 7, 0xFFFF, sum = 0
2673 23:49:14.105452 8, 0xFFFF, sum = 0
2674 23:49:14.108838 9, 0xFFFF, sum = 0
2675 23:49:14.112033 10, 0xFFFF, sum = 0
2676 23:49:14.112105 11, 0xFFFF, sum = 0
2677 23:49:14.115337 12, 0x0, sum = 1
2678 23:49:14.115422 13, 0x0, sum = 2
2679 23:49:14.115528 14, 0x0, sum = 3
2680 23:49:14.119125 15, 0x0, sum = 4
2681 23:49:14.119197 best_step = 13
2682 23:49:14.119258
2683 23:49:14.122117 ==
2684 23:49:14.122188 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 23:49:14.128984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 23:49:14.129105 ==
2687 23:49:14.129201 RX Vref Scan: 1
2688 23:49:14.129276
2689 23:49:14.131862 Set Vref Range= 32 -> 127
2690 23:49:14.131963
2691 23:49:14.135298 RX Vref 32 -> 127, step: 1
2692 23:49:14.135381
2693 23:49:14.138777 RX Delay -13 -> 252, step: 4
2694 23:49:14.138902
2695 23:49:14.141912 Set Vref, RX VrefLevel [Byte0]: 32
2696 23:49:14.145123 [Byte1]: 32
2697 23:49:14.145206
2698 23:49:14.148953 Set Vref, RX VrefLevel [Byte0]: 33
2699 23:49:14.152190 [Byte1]: 33
2700 23:49:14.152272
2701 23:49:14.155308 Set Vref, RX VrefLevel [Byte0]: 34
2702 23:49:14.159198 [Byte1]: 34
2703 23:49:14.163122
2704 23:49:14.163204 Set Vref, RX VrefLevel [Byte0]: 35
2705 23:49:14.166357 [Byte1]: 35
2706 23:49:14.170887
2707 23:49:14.170968 Set Vref, RX VrefLevel [Byte0]: 36
2708 23:49:14.174049 [Byte1]: 36
2709 23:49:14.178664
2710 23:49:14.178788 Set Vref, RX VrefLevel [Byte0]: 37
2711 23:49:14.181957 [Byte1]: 37
2712 23:49:14.186393
2713 23:49:14.186553 Set Vref, RX VrefLevel [Byte0]: 38
2714 23:49:14.189581 [Byte1]: 38
2715 23:49:14.194452
2716 23:49:14.194570 Set Vref, RX VrefLevel [Byte0]: 39
2717 23:49:14.197844 [Byte1]: 39
2718 23:49:14.202474
2719 23:49:14.202583 Set Vref, RX VrefLevel [Byte0]: 40
2720 23:49:14.205632 [Byte1]: 40
2721 23:49:14.210235
2722 23:49:14.210368 Set Vref, RX VrefLevel [Byte0]: 41
2723 23:49:14.213571 [Byte1]: 41
2724 23:49:14.217999
2725 23:49:14.218107 Set Vref, RX VrefLevel [Byte0]: 42
2726 23:49:14.221157 [Byte1]: 42
2727 23:49:14.226238
2728 23:49:14.226351 Set Vref, RX VrefLevel [Byte0]: 43
2729 23:49:14.229391 [Byte1]: 43
2730 23:49:14.233842
2731 23:49:14.233954 Set Vref, RX VrefLevel [Byte0]: 44
2732 23:49:14.236868 [Byte1]: 44
2733 23:49:14.241515
2734 23:49:14.241631 Set Vref, RX VrefLevel [Byte0]: 45
2735 23:49:14.244927 [Byte1]: 45
2736 23:49:14.249777
2737 23:49:14.249898 Set Vref, RX VrefLevel [Byte0]: 46
2738 23:49:14.253067 [Byte1]: 46
2739 23:49:14.257631
2740 23:49:14.257738 Set Vref, RX VrefLevel [Byte0]: 47
2741 23:49:14.260720 [Byte1]: 47
2742 23:49:14.265610
2743 23:49:14.265731 Set Vref, RX VrefLevel [Byte0]: 48
2744 23:49:14.269291 [Byte1]: 48
2745 23:49:14.273294
2746 23:49:14.273407 Set Vref, RX VrefLevel [Byte0]: 49
2747 23:49:14.276582 [Byte1]: 49
2748 23:49:14.281057
2749 23:49:14.281170 Set Vref, RX VrefLevel [Byte0]: 50
2750 23:49:14.284304 [Byte1]: 50
2751 23:49:14.289122
2752 23:49:14.289234 Set Vref, RX VrefLevel [Byte0]: 51
2753 23:49:14.292797 [Byte1]: 51
2754 23:49:14.297291
2755 23:49:14.297401 Set Vref, RX VrefLevel [Byte0]: 52
2756 23:49:14.300542 [Byte1]: 52
2757 23:49:14.304842
2758 23:49:14.304956 Set Vref, RX VrefLevel [Byte0]: 53
2759 23:49:14.308487 [Byte1]: 53
2760 23:49:14.313006
2761 23:49:14.313121 Set Vref, RX VrefLevel [Byte0]: 54
2762 23:49:14.316447 [Byte1]: 54
2763 23:49:14.320539
2764 23:49:14.320624 Set Vref, RX VrefLevel [Byte0]: 55
2765 23:49:14.324333 [Byte1]: 55
2766 23:49:14.328616
2767 23:49:14.328711 Set Vref, RX VrefLevel [Byte0]: 56
2768 23:49:14.331768 [Byte1]: 56
2769 23:49:14.336275
2770 23:49:14.336389 Set Vref, RX VrefLevel [Byte0]: 57
2771 23:49:14.339652 [Byte1]: 57
2772 23:49:14.344217
2773 23:49:14.344327 Set Vref, RX VrefLevel [Byte0]: 58
2774 23:49:14.347416 [Byte1]: 58
2775 23:49:14.352458
2776 23:49:14.352549 Set Vref, RX VrefLevel [Byte0]: 59
2777 23:49:14.355361 [Byte1]: 59
2778 23:49:14.360046
2779 23:49:14.360141 Set Vref, RX VrefLevel [Byte0]: 60
2780 23:49:14.363707 [Byte1]: 60
2781 23:49:14.368255
2782 23:49:14.368375 Set Vref, RX VrefLevel [Byte0]: 61
2783 23:49:14.371314 [Byte1]: 61
2784 23:49:14.376538
2785 23:49:14.376659 Set Vref, RX VrefLevel [Byte0]: 62
2786 23:49:14.379545 [Byte1]: 62
2787 23:49:14.383764
2788 23:49:14.383874 Set Vref, RX VrefLevel [Byte0]: 63
2789 23:49:14.386847 [Byte1]: 63
2790 23:49:14.391903
2791 23:49:14.392031 Set Vref, RX VrefLevel [Byte0]: 64
2792 23:49:14.395138 [Byte1]: 64
2793 23:49:14.399838
2794 23:49:14.399941 Set Vref, RX VrefLevel [Byte0]: 65
2795 23:49:14.403201 [Byte1]: 65
2796 23:49:14.407583
2797 23:49:14.407681 Set Vref, RX VrefLevel [Byte0]: 66
2798 23:49:14.410845 [Byte1]: 66
2799 23:49:14.415389
2800 23:49:14.415495 Set Vref, RX VrefLevel [Byte0]: 67
2801 23:49:14.418539 [Byte1]: 67
2802 23:49:14.423217
2803 23:49:14.423352 Set Vref, RX VrefLevel [Byte0]: 68
2804 23:49:14.426291 [Byte1]: 68
2805 23:49:14.430945
2806 23:49:14.431065 Set Vref, RX VrefLevel [Byte0]: 69
2807 23:49:14.434552 [Byte1]: 69
2808 23:49:14.438854
2809 23:49:14.439002 Final RX Vref Byte 0 = 57 to rank0
2810 23:49:14.442119 Final RX Vref Byte 1 = 48 to rank0
2811 23:49:14.445980 Final RX Vref Byte 0 = 57 to rank1
2812 23:49:14.449241 Final RX Vref Byte 1 = 48 to rank1==
2813 23:49:14.452517 Dram Type= 6, Freq= 0, CH_0, rank 0
2814 23:49:14.455753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2815 23:49:14.458911 ==
2816 23:49:14.459037 DQS Delay:
2817 23:49:14.459147 DQS0 = 0, DQS1 = 0
2818 23:49:14.462495 DQM Delay:
2819 23:49:14.462605 DQM0 = 120, DQM1 = 111
2820 23:49:14.466060 DQ Delay:
2821 23:49:14.469463 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118
2822 23:49:14.472442 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2823 23:49:14.476046 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106
2824 23:49:14.479159 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2825 23:49:14.479276
2826 23:49:14.479379
2827 23:49:14.486220 [DQSOSCAuto] RK0, (LSB)MR18= 0x140e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2828 23:49:14.489241 CH0 RK0: MR19=404, MR18=140E
2829 23:49:14.496218 CH0_RK0: MR19=0x404, MR18=0x140E, DQSOSC=402, MR23=63, INC=40, DEC=27
2830 23:49:14.496354
2831 23:49:14.499452 ----->DramcWriteLeveling(PI) begin...
2832 23:49:14.499563 ==
2833 23:49:14.502610 Dram Type= 6, Freq= 0, CH_0, rank 1
2834 23:49:14.506266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2835 23:49:14.506380 ==
2836 23:49:14.509233 Write leveling (Byte 0): 34 => 34
2837 23:49:14.512532 Write leveling (Byte 1): 29 => 29
2838 23:49:14.516395 DramcWriteLeveling(PI) end<-----
2839 23:49:14.516528
2840 23:49:14.516625 ==
2841 23:49:14.519554 Dram Type= 6, Freq= 0, CH_0, rank 1
2842 23:49:14.523022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2843 23:49:14.525939 ==
2844 23:49:14.526061 [Gating] SW mode calibration
2845 23:49:14.532614 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2846 23:49:14.539668 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2847 23:49:14.543043 0 15 0 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 0)
2848 23:49:14.549512 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 23:49:14.552805 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 23:49:14.556222 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 23:49:14.562607 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 23:49:14.566462 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 23:49:14.569555 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 23:49:14.576164 0 15 28 | B1->B0 | 2e2e 2c2c | 0 0 | (1 0) (1 0)
2855 23:49:14.579457 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 23:49:14.583071 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 23:49:14.589639 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 23:49:14.593130 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 23:49:14.596089 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 23:49:14.603056 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 23:49:14.606271 1 0 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
2862 23:49:14.609280 1 0 28 | B1->B0 | 3636 3939 | 0 1 | (0 0) (0 0)
2863 23:49:14.613015 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 23:49:14.619607 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 23:49:14.622552 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 23:49:14.626457 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 23:49:14.633028 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 23:49:14.636129 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 23:49:14.639787 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 23:49:14.646518 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2871 23:49:14.649698 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2872 23:49:14.652906 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 23:49:14.660050 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 23:49:14.662976 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 23:49:14.666409 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 23:49:14.669538 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 23:49:14.676548 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 23:49:14.679838 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 23:49:14.683353 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 23:49:14.689713 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 23:49:14.693274 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 23:49:14.696229 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 23:49:14.703559 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 23:49:14.706852 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 23:49:14.709895 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 23:49:14.716246 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2887 23:49:14.720209 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 23:49:14.723689 Total UI for P1: 0, mck2ui 16
2889 23:49:14.726495 best dqsien dly found for B0: ( 1, 3, 28)
2890 23:49:14.729831 Total UI for P1: 0, mck2ui 16
2891 23:49:14.733291 best dqsien dly found for B1: ( 1, 3, 28)
2892 23:49:14.736309 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2893 23:49:14.739535 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2894 23:49:14.739681
2895 23:49:14.742798 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2896 23:49:14.746494 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2897 23:49:14.749480 [Gating] SW calibration Done
2898 23:49:14.749569 ==
2899 23:49:14.753355 Dram Type= 6, Freq= 0, CH_0, rank 1
2900 23:49:14.756787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2901 23:49:14.756873 ==
2902 23:49:14.759724 RX Vref Scan: 0
2903 23:49:14.759807
2904 23:49:14.763378 RX Vref 0 -> 0, step: 1
2905 23:49:14.763462
2906 23:49:14.763544 RX Delay -40 -> 252, step: 8
2907 23:49:14.769999 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2908 23:49:14.773514 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2909 23:49:14.776831 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2910 23:49:14.780176 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2911 23:49:14.783350 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2912 23:49:14.790407 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2913 23:49:14.793863 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2914 23:49:14.797239 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2915 23:49:14.800298 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2916 23:49:14.803424 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2917 23:49:14.806912 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2918 23:49:14.813972 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2919 23:49:14.817466 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2920 23:49:14.819922 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2921 23:49:14.823639 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2922 23:49:14.830239 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2923 23:49:14.830430 ==
2924 23:49:14.833446 Dram Type= 6, Freq= 0, CH_0, rank 1
2925 23:49:14.836978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2926 23:49:14.837139 ==
2927 23:49:14.837285 DQS Delay:
2928 23:49:14.840530 DQS0 = 0, DQS1 = 0
2929 23:49:14.840666 DQM Delay:
2930 23:49:14.843697 DQM0 = 122, DQM1 = 112
2931 23:49:14.843853 DQ Delay:
2932 23:49:14.847034 DQ0 =119, DQ1 =119, DQ2 =123, DQ3 =119
2933 23:49:14.850471 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2934 23:49:14.853657 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2935 23:49:14.857253 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2936 23:49:14.857415
2937 23:49:14.857560
2938 23:49:14.857701 ==
2939 23:49:14.860404 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 23:49:14.866936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 23:49:14.867100 ==
2942 23:49:14.867247
2943 23:49:14.867387
2944 23:49:14.867525 TX Vref Scan disable
2945 23:49:14.870819 == TX Byte 0 ==
2946 23:49:14.874121 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2947 23:49:14.877094 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2948 23:49:14.880875 == TX Byte 1 ==
2949 23:49:14.883863 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2950 23:49:14.886993 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2951 23:49:14.890798 ==
2952 23:49:14.894027 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 23:49:14.897156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 23:49:14.897245 ==
2955 23:49:14.908661 TX Vref=22, minBit 5, minWin=24, winSum=413
2956 23:49:14.912203 TX Vref=24, minBit 2, minWin=25, winSum=416
2957 23:49:14.915674 TX Vref=26, minBit 0, minWin=26, winSum=423
2958 23:49:14.919134 TX Vref=28, minBit 5, minWin=26, winSum=429
2959 23:49:14.922521 TX Vref=30, minBit 0, minWin=26, winSum=428
2960 23:49:14.925511 TX Vref=32, minBit 0, minWin=25, winSum=425
2961 23:49:14.932814 [TxChooseVref] Worse bit 5, Min win 26, Win sum 429, Final Vref 28
2962 23:49:14.932911
2963 23:49:14.935884 Final TX Range 1 Vref 28
2964 23:49:14.935970
2965 23:49:14.936043 ==
2966 23:49:14.939142 Dram Type= 6, Freq= 0, CH_0, rank 1
2967 23:49:14.942443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2968 23:49:14.942529 ==
2969 23:49:14.942596
2970 23:49:14.942657
2971 23:49:14.945671 TX Vref Scan disable
2972 23:49:14.949595 == TX Byte 0 ==
2973 23:49:14.952855 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2974 23:49:14.956040 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2975 23:49:14.959060 == TX Byte 1 ==
2976 23:49:14.962591 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2977 23:49:14.966089 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2978 23:49:14.966192
2979 23:49:14.969119 [DATLAT]
2980 23:49:14.969206 Freq=1200, CH0 RK1
2981 23:49:14.969274
2982 23:49:14.972388 DATLAT Default: 0xd
2983 23:49:14.972477 0, 0xFFFF, sum = 0
2984 23:49:14.976309 1, 0xFFFF, sum = 0
2985 23:49:14.976414 2, 0xFFFF, sum = 0
2986 23:49:14.979553 3, 0xFFFF, sum = 0
2987 23:49:14.979645 4, 0xFFFF, sum = 0
2988 23:49:14.982221 5, 0xFFFF, sum = 0
2989 23:49:14.982344 6, 0xFFFF, sum = 0
2990 23:49:14.986047 7, 0xFFFF, sum = 0
2991 23:49:14.986199 8, 0xFFFF, sum = 0
2992 23:49:14.989080 9, 0xFFFF, sum = 0
2993 23:49:14.992151 10, 0xFFFF, sum = 0
2994 23:49:14.992295 11, 0xFFFF, sum = 0
2995 23:49:14.995622 12, 0x0, sum = 1
2996 23:49:14.995773 13, 0x0, sum = 2
2997 23:49:14.995911 14, 0x0, sum = 3
2998 23:49:14.999079 15, 0x0, sum = 4
2999 23:49:14.999198 best_step = 13
3000 23:49:14.999304
3001 23:49:14.999407 ==
3002 23:49:15.002520 Dram Type= 6, Freq= 0, CH_0, rank 1
3003 23:49:15.009420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3004 23:49:15.009532 ==
3005 23:49:15.009602 RX Vref Scan: 0
3006 23:49:15.009666
3007 23:49:15.012992 RX Vref 0 -> 0, step: 1
3008 23:49:15.013080
3009 23:49:15.016092 RX Delay -13 -> 252, step: 4
3010 23:49:15.019010 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3011 23:49:15.022544 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3012 23:49:15.029355 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3013 23:49:15.032474 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3014 23:49:15.035601 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3015 23:49:15.039013 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3016 23:49:15.042611 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3017 23:49:15.049251 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3018 23:49:15.052283 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3019 23:49:15.055611 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3020 23:49:15.058935 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3021 23:49:15.062832 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3022 23:49:15.069436 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3023 23:49:15.072589 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3024 23:49:15.075808 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3025 23:49:15.079366 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3026 23:49:15.079471 ==
3027 23:49:15.082312 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 23:49:15.086005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 23:49:15.089186 ==
3030 23:49:15.089306 DQS Delay:
3031 23:49:15.089374 DQS0 = 0, DQS1 = 0
3032 23:49:15.093174 DQM Delay:
3033 23:49:15.093323 DQM0 = 121, DQM1 = 109
3034 23:49:15.096271 DQ Delay:
3035 23:49:15.099575 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3036 23:49:15.102840 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3037 23:49:15.106125 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3038 23:49:15.109534 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3039 23:49:15.109607
3040 23:49:15.109669
3041 23:49:15.116319 [DQSOSCAuto] RK1, (LSB)MR18= 0x12f3, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3042 23:49:15.119602 CH0 RK1: MR19=403, MR18=12F3
3043 23:49:15.126128 CH0_RK1: MR19=0x403, MR18=0x12F3, DQSOSC=403, MR23=63, INC=40, DEC=26
3044 23:49:15.129443 [RxdqsGatingPostProcess] freq 1200
3045 23:49:15.136228 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3046 23:49:15.136366 best DQS0 dly(2T, 0.5T) = (0, 11)
3047 23:49:15.139883 best DQS1 dly(2T, 0.5T) = (0, 12)
3048 23:49:15.142556 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3049 23:49:15.145979 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3050 23:49:15.149466 best DQS0 dly(2T, 0.5T) = (0, 11)
3051 23:49:15.152542 best DQS1 dly(2T, 0.5T) = (0, 11)
3052 23:49:15.156288 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3053 23:49:15.159520 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3054 23:49:15.162712 Pre-setting of DQS Precalculation
3055 23:49:15.165969 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3056 23:49:15.169398 ==
3057 23:49:15.173201 Dram Type= 6, Freq= 0, CH_1, rank 0
3058 23:49:15.176460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3059 23:49:15.176546 ==
3060 23:49:15.179760 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3061 23:49:15.186266 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3062 23:49:15.195057 [CA 0] Center 37 (7~68) winsize 62
3063 23:49:15.198694 [CA 1] Center 37 (7~68) winsize 62
3064 23:49:15.202057 [CA 2] Center 35 (5~65) winsize 61
3065 23:49:15.205411 [CA 3] Center 34 (4~64) winsize 61
3066 23:49:15.208174 [CA 4] Center 34 (4~64) winsize 61
3067 23:49:15.212092 [CA 5] Center 33 (3~63) winsize 61
3068 23:49:15.212215
3069 23:49:15.215310 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3070 23:49:15.215423
3071 23:49:15.218614 [CATrainingPosCal] consider 1 rank data
3072 23:49:15.222128 u2DelayCellTimex100 = 270/100 ps
3073 23:49:15.225075 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3074 23:49:15.228586 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3075 23:49:15.235296 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3076 23:49:15.238505 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3077 23:49:15.241834 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3078 23:49:15.245135 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3079 23:49:15.245234
3080 23:49:15.248689 CA PerBit enable=1, Macro0, CA PI delay=33
3081 23:49:15.248774
3082 23:49:15.251573 [CBTSetCACLKResult] CA Dly = 33
3083 23:49:15.251657 CS Dly: 7 (0~38)
3084 23:49:15.251724 ==
3085 23:49:15.254932 Dram Type= 6, Freq= 0, CH_1, rank 1
3086 23:49:15.262025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3087 23:49:15.262112 ==
3088 23:49:15.265385 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3089 23:49:15.271641 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3090 23:49:15.280743 [CA 0] Center 37 (7~68) winsize 62
3091 23:49:15.283907 [CA 1] Center 38 (7~69) winsize 63
3092 23:49:15.287975 [CA 2] Center 35 (5~65) winsize 61
3093 23:49:15.291127 [CA 3] Center 34 (4~65) winsize 62
3094 23:49:15.294332 [CA 4] Center 34 (4~65) winsize 62
3095 23:49:15.297630 [CA 5] Center 33 (3~64) winsize 62
3096 23:49:15.297741
3097 23:49:15.300877 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3098 23:49:15.300985
3099 23:49:15.304075 [CATrainingPosCal] consider 2 rank data
3100 23:49:15.307255 u2DelayCellTimex100 = 270/100 ps
3101 23:49:15.310950 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3102 23:49:15.314356 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3103 23:49:15.320813 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3104 23:49:15.324328 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3105 23:49:15.327691 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3106 23:49:15.330940 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3107 23:49:15.331057
3108 23:49:15.334100 CA PerBit enable=1, Macro0, CA PI delay=33
3109 23:49:15.334215
3110 23:49:15.337253 [CBTSetCACLKResult] CA Dly = 33
3111 23:49:15.337360 CS Dly: 8 (0~41)
3112 23:49:15.337457
3113 23:49:15.340519 ----->DramcWriteLeveling(PI) begin...
3114 23:49:15.344361 ==
3115 23:49:15.344473 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 23:49:15.350942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3117 23:49:15.351059 ==
3118 23:49:15.354259 Write leveling (Byte 0): 28 => 28
3119 23:49:15.357791 Write leveling (Byte 1): 28 => 28
3120 23:49:15.357905 DramcWriteLeveling(PI) end<-----
3121 23:49:15.360769
3122 23:49:15.360879 ==
3123 23:49:15.364290 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 23:49:15.367508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 23:49:15.367618 ==
3126 23:49:15.371012 [Gating] SW mode calibration
3127 23:49:15.377467 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3128 23:49:15.381026 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3129 23:49:15.387589 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 23:49:15.391159 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 23:49:15.394395 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 23:49:15.400983 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 23:49:15.404283 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 23:49:15.407544 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 23:49:15.414645 0 15 24 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
3136 23:49:15.417878 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3137 23:49:15.420901 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 23:49:15.427559 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 23:49:15.431252 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 23:49:15.434359 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 23:49:15.437962 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 23:49:15.444755 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 23:49:15.448279 1 0 24 | B1->B0 | 3434 4040 | 1 0 | (0 0) (0 0)
3144 23:49:15.451277 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 23:49:15.457770 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 23:49:15.461185 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 23:49:15.464869 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 23:49:15.471449 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 23:49:15.474590 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 23:49:15.477703 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 23:49:15.484749 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3152 23:49:15.487824 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3153 23:49:15.491612 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 23:49:15.497986 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 23:49:15.501168 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 23:49:15.504782 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 23:49:15.511541 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 23:49:15.514762 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 23:49:15.518136 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 23:49:15.521418 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 23:49:15.527752 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 23:49:15.531331 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 23:49:15.534526 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 23:49:15.541593 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 23:49:15.544782 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 23:49:15.547888 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 23:49:15.554544 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3168 23:49:15.557843 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3169 23:49:15.561592 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3170 23:49:15.564807 Total UI for P1: 0, mck2ui 16
3171 23:49:15.568018 best dqsien dly found for B0: ( 1, 3, 26)
3172 23:49:15.571825 Total UI for P1: 0, mck2ui 16
3173 23:49:15.575056 best dqsien dly found for B1: ( 1, 3, 26)
3174 23:49:15.578240 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3175 23:49:15.581347 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3176 23:49:15.581452
3177 23:49:15.584999 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3178 23:49:15.591585 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3179 23:49:15.591672 [Gating] SW calibration Done
3180 23:49:15.591739 ==
3181 23:49:15.594889 Dram Type= 6, Freq= 0, CH_1, rank 0
3182 23:49:15.602149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3183 23:49:15.602253 ==
3184 23:49:15.602320 RX Vref Scan: 0
3185 23:49:15.602381
3186 23:49:15.605122 RX Vref 0 -> 0, step: 1
3187 23:49:15.605194
3188 23:49:15.608582 RX Delay -40 -> 252, step: 8
3189 23:49:15.611850 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3190 23:49:15.615432 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3191 23:49:15.618526 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3192 23:49:15.621479 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3193 23:49:15.628677 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3194 23:49:15.631770 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3195 23:49:15.634984 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3196 23:49:15.638464 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3197 23:49:15.641597 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3198 23:49:15.648759 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3199 23:49:15.652012 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3200 23:49:15.655242 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3201 23:49:15.658437 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3202 23:49:15.661630 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3203 23:49:15.668551 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3204 23:49:15.672025 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3205 23:49:15.672101 ==
3206 23:49:15.675109 Dram Type= 6, Freq= 0, CH_1, rank 0
3207 23:49:15.678780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3208 23:49:15.678893 ==
3209 23:49:15.681973 DQS Delay:
3210 23:49:15.682055 DQS0 = 0, DQS1 = 0
3211 23:49:15.682151 DQM Delay:
3212 23:49:15.685173 DQM0 = 120, DQM1 = 116
3213 23:49:15.685256 DQ Delay:
3214 23:49:15.688615 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3215 23:49:15.691799 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3216 23:49:15.695400 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3217 23:49:15.701654 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3218 23:49:15.701773
3219 23:49:15.701893
3220 23:49:15.701997 ==
3221 23:49:15.704871 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 23:49:15.708609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 23:49:15.708692 ==
3224 23:49:15.708757
3225 23:49:15.708817
3226 23:49:15.711948 TX Vref Scan disable
3227 23:49:15.712049 == TX Byte 0 ==
3228 23:49:15.718457 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3229 23:49:15.721781 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3230 23:49:15.721866 == TX Byte 1 ==
3231 23:49:15.728550 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3232 23:49:15.731723 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3233 23:49:15.731808 ==
3234 23:49:15.735095 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 23:49:15.738452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 23:49:15.738539 ==
3237 23:49:15.750774 TX Vref=22, minBit 9, minWin=24, winSum=409
3238 23:49:15.754042 TX Vref=24, minBit 9, minWin=25, winSum=418
3239 23:49:15.757432 TX Vref=26, minBit 9, minWin=25, winSum=422
3240 23:49:15.761492 TX Vref=28, minBit 1, minWin=26, winSum=427
3241 23:49:15.764577 TX Vref=30, minBit 1, minWin=26, winSum=429
3242 23:49:15.767803 TX Vref=32, minBit 9, minWin=26, winSum=430
3243 23:49:15.774288 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 32
3244 23:49:15.774379
3245 23:49:15.778146 Final TX Range 1 Vref 32
3246 23:49:15.778266
3247 23:49:15.778338 ==
3248 23:49:15.781120 Dram Type= 6, Freq= 0, CH_1, rank 0
3249 23:49:15.784209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3250 23:49:15.784325 ==
3251 23:49:15.784407
3252 23:49:15.784470
3253 23:49:15.787927 TX Vref Scan disable
3254 23:49:15.791430 == TX Byte 0 ==
3255 23:49:15.794597 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3256 23:49:15.798137 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3257 23:49:15.801301 == TX Byte 1 ==
3258 23:49:15.804892 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3259 23:49:15.808193 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3260 23:49:15.808272
3261 23:49:15.811247 [DATLAT]
3262 23:49:15.811324 Freq=1200, CH1 RK0
3263 23:49:15.811388
3264 23:49:15.814460 DATLAT Default: 0xd
3265 23:49:15.814536 0, 0xFFFF, sum = 0
3266 23:49:15.817745 1, 0xFFFF, sum = 0
3267 23:49:15.817824 2, 0xFFFF, sum = 0
3268 23:49:15.821162 3, 0xFFFF, sum = 0
3269 23:49:15.821248 4, 0xFFFF, sum = 0
3270 23:49:15.824886 5, 0xFFFF, sum = 0
3271 23:49:15.824972 6, 0xFFFF, sum = 0
3272 23:49:15.828094 7, 0xFFFF, sum = 0
3273 23:49:15.828209 8, 0xFFFF, sum = 0
3274 23:49:15.831427 9, 0xFFFF, sum = 0
3275 23:49:15.831533 10, 0xFFFF, sum = 0
3276 23:49:15.834660 11, 0xFFFF, sum = 0
3277 23:49:15.834764 12, 0x0, sum = 1
3278 23:49:15.838585 13, 0x0, sum = 2
3279 23:49:15.838672 14, 0x0, sum = 3
3280 23:49:15.841536 15, 0x0, sum = 4
3281 23:49:15.841626 best_step = 13
3282 23:49:15.841693
3283 23:49:15.841755 ==
3284 23:49:15.844805 Dram Type= 6, Freq= 0, CH_1, rank 0
3285 23:49:15.851404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3286 23:49:15.851492 ==
3287 23:49:15.851559 RX Vref Scan: 1
3288 23:49:15.851622
3289 23:49:15.854871 Set Vref Range= 32 -> 127
3290 23:49:15.854955
3291 23:49:15.858158 RX Vref 32 -> 127, step: 1
3292 23:49:15.858242
3293 23:49:15.858308 RX Delay -5 -> 252, step: 4
3294 23:49:15.858369
3295 23:49:15.861540 Set Vref, RX VrefLevel [Byte0]: 32
3296 23:49:15.864795 [Byte1]: 32
3297 23:49:15.869239
3298 23:49:15.869367 Set Vref, RX VrefLevel [Byte0]: 33
3299 23:49:15.872543 [Byte1]: 33
3300 23:49:15.877038
3301 23:49:15.877162 Set Vref, RX VrefLevel [Byte0]: 34
3302 23:49:15.880240 [Byte1]: 34
3303 23:49:15.884684
3304 23:49:15.884811 Set Vref, RX VrefLevel [Byte0]: 35
3305 23:49:15.887905 [Byte1]: 35
3306 23:49:15.892512
3307 23:49:15.892638 Set Vref, RX VrefLevel [Byte0]: 36
3308 23:49:15.896066 [Byte1]: 36
3309 23:49:15.900508
3310 23:49:15.900623 Set Vref, RX VrefLevel [Byte0]: 37
3311 23:49:15.903823 [Byte1]: 37
3312 23:49:15.908450
3313 23:49:15.908590 Set Vref, RX VrefLevel [Byte0]: 38
3314 23:49:15.911321 [Byte1]: 38
3315 23:49:15.915983
3316 23:49:15.916071 Set Vref, RX VrefLevel [Byte0]: 39
3317 23:49:15.919651 [Byte1]: 39
3318 23:49:15.924068
3319 23:49:15.924188 Set Vref, RX VrefLevel [Byte0]: 40
3320 23:49:15.927254 [Byte1]: 40
3321 23:49:15.931823
3322 23:49:15.931926 Set Vref, RX VrefLevel [Byte0]: 41
3323 23:49:15.938349 [Byte1]: 41
3324 23:49:15.938438
3325 23:49:15.941615 Set Vref, RX VrefLevel [Byte0]: 42
3326 23:49:15.944728 [Byte1]: 42
3327 23:49:15.944829
3328 23:49:15.948547 Set Vref, RX VrefLevel [Byte0]: 43
3329 23:49:15.952110 [Byte1]: 43
3330 23:49:15.955622
3331 23:49:15.955728 Set Vref, RX VrefLevel [Byte0]: 44
3332 23:49:15.958521 [Byte1]: 44
3333 23:49:15.963529
3334 23:49:15.963644 Set Vref, RX VrefLevel [Byte0]: 45
3335 23:49:15.966559 [Byte1]: 45
3336 23:49:15.971296
3337 23:49:15.971408 Set Vref, RX VrefLevel [Byte0]: 46
3338 23:49:15.974110 [Byte1]: 46
3339 23:49:15.979031
3340 23:49:15.979147 Set Vref, RX VrefLevel [Byte0]: 47
3341 23:49:15.982440 [Byte1]: 47
3342 23:49:15.986915
3343 23:49:15.987037 Set Vref, RX VrefLevel [Byte0]: 48
3344 23:49:15.990416 [Byte1]: 48
3345 23:49:15.994783
3346 23:49:15.994899 Set Vref, RX VrefLevel [Byte0]: 49
3347 23:49:15.998088 [Byte1]: 49
3348 23:49:16.002617
3349 23:49:16.002725 Set Vref, RX VrefLevel [Byte0]: 50
3350 23:49:16.005886 [Byte1]: 50
3351 23:49:16.010372
3352 23:49:16.010479 Set Vref, RX VrefLevel [Byte0]: 51
3353 23:49:16.013451 [Byte1]: 51
3354 23:49:16.018404
3355 23:49:16.018518 Set Vref, RX VrefLevel [Byte0]: 52
3356 23:49:16.021569 [Byte1]: 52
3357 23:49:16.026147
3358 23:49:16.026264 Set Vref, RX VrefLevel [Byte0]: 53
3359 23:49:16.029158 [Byte1]: 53
3360 23:49:16.034074
3361 23:49:16.034213 Set Vref, RX VrefLevel [Byte0]: 54
3362 23:49:16.037079 [Byte1]: 54
3363 23:49:16.041545
3364 23:49:16.041667 Set Vref, RX VrefLevel [Byte0]: 55
3365 23:49:16.044786 [Byte1]: 55
3366 23:49:16.049944
3367 23:49:16.050102 Set Vref, RX VrefLevel [Byte0]: 56
3368 23:49:16.053202 [Byte1]: 56
3369 23:49:16.057917
3370 23:49:16.058026 Set Vref, RX VrefLevel [Byte0]: 57
3371 23:49:16.060767 [Byte1]: 57
3372 23:49:16.064972
3373 23:49:16.065112 Set Vref, RX VrefLevel [Byte0]: 58
3374 23:49:16.068677 [Byte1]: 58
3375 23:49:16.073248
3376 23:49:16.073350 Set Vref, RX VrefLevel [Byte0]: 59
3377 23:49:16.076491 [Byte1]: 59
3378 23:49:16.081022
3379 23:49:16.081138 Set Vref, RX VrefLevel [Byte0]: 60
3380 23:49:16.084155 [Byte1]: 60
3381 23:49:16.088927
3382 23:49:16.089061 Set Vref, RX VrefLevel [Byte0]: 61
3383 23:49:16.092226 [Byte1]: 61
3384 23:49:16.096790
3385 23:49:16.096919 Set Vref, RX VrefLevel [Byte0]: 62
3386 23:49:16.103290 [Byte1]: 62
3387 23:49:16.103429
3388 23:49:16.106314 Set Vref, RX VrefLevel [Byte0]: 63
3389 23:49:16.110268 [Byte1]: 63
3390 23:49:16.110392
3391 23:49:16.113293 Set Vref, RX VrefLevel [Byte0]: 64
3392 23:49:16.116529 [Byte1]: 64
3393 23:49:16.120313
3394 23:49:16.120430 Set Vref, RX VrefLevel [Byte0]: 65
3395 23:49:16.123826 [Byte1]: 65
3396 23:49:16.128260
3397 23:49:16.128350 Set Vref, RX VrefLevel [Byte0]: 66
3398 23:49:16.131417 [Byte1]: 66
3399 23:49:16.135731
3400 23:49:16.135813 Set Vref, RX VrefLevel [Byte0]: 67
3401 23:49:16.139309 [Byte1]: 67
3402 23:49:16.144035
3403 23:49:16.144110 Final RX Vref Byte 0 = 54 to rank0
3404 23:49:16.147055 Final RX Vref Byte 1 = 55 to rank0
3405 23:49:16.150350 Final RX Vref Byte 0 = 54 to rank1
3406 23:49:16.153576 Final RX Vref Byte 1 = 55 to rank1==
3407 23:49:16.157313 Dram Type= 6, Freq= 0, CH_1, rank 0
3408 23:49:16.163902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3409 23:49:16.164015 ==
3410 23:49:16.164106 DQS Delay:
3411 23:49:16.164196 DQS0 = 0, DQS1 = 0
3412 23:49:16.167228 DQM Delay:
3413 23:49:16.167332 DQM0 = 120, DQM1 = 118
3414 23:49:16.170530 DQ Delay:
3415 23:49:16.173925 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3416 23:49:16.177901 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3417 23:49:16.180800 DQ8 =104, DQ9 =110, DQ10 =120, DQ11 =112
3418 23:49:16.184258 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3419 23:49:16.184386
3420 23:49:16.184482
3421 23:49:16.190391 [DQSOSCAuto] RK0, (LSB)MR18= 0x115, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3422 23:49:16.194238 CH1 RK0: MR19=404, MR18=115
3423 23:49:16.200850 CH1_RK0: MR19=0x404, MR18=0x115, DQSOSC=401, MR23=63, INC=40, DEC=27
3424 23:49:16.200961
3425 23:49:16.203834 ----->DramcWriteLeveling(PI) begin...
3426 23:49:16.203941 ==
3427 23:49:16.207598 Dram Type= 6, Freq= 0, CH_1, rank 1
3428 23:49:16.210843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 23:49:16.210955 ==
3430 23:49:16.213789 Write leveling (Byte 0): 26 => 26
3431 23:49:16.217263 Write leveling (Byte 1): 31 => 31
3432 23:49:16.220705 DramcWriteLeveling(PI) end<-----
3433 23:49:16.220813
3434 23:49:16.220906 ==
3435 23:49:16.223856 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 23:49:16.227672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 23:49:16.230665 ==
3438 23:49:16.230777 [Gating] SW mode calibration
3439 23:49:16.240456 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3440 23:49:16.244492 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3441 23:49:16.247447 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 23:49:16.253949 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 23:49:16.257485 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 23:49:16.260572 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 23:49:16.267566 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3446 23:49:16.270797 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3447 23:49:16.274019 0 15 24 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 0)
3448 23:49:16.280543 0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
3449 23:49:16.283923 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 23:49:16.287108 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 23:49:16.294195 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 23:49:16.297393 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 23:49:16.300939 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3454 23:49:16.303960 1 0 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3455 23:49:16.310988 1 0 24 | B1->B0 | 4242 2929 | 0 0 | (0 0) (1 1)
3456 23:49:16.314421 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 23:49:16.317662 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 23:49:16.323645 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 23:49:16.327435 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 23:49:16.330521 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 23:49:16.337353 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3462 23:49:16.340718 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3463 23:49:16.343853 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3464 23:49:16.350898 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3465 23:49:16.353944 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 23:49:16.357439 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 23:49:16.363858 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 23:49:16.366913 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 23:49:16.370694 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 23:49:16.376887 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 23:49:16.380234 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 23:49:16.383627 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 23:49:16.390075 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 23:49:16.393749 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 23:49:16.396973 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 23:49:16.403720 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 23:49:16.406928 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 23:49:16.410233 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3479 23:49:16.416808 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3480 23:49:16.420243 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3481 23:49:16.423637 Total UI for P1: 0, mck2ui 16
3482 23:49:16.426963 best dqsien dly found for B1: ( 1, 3, 22)
3483 23:49:16.430345 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3484 23:49:16.433713 Total UI for P1: 0, mck2ui 16
3485 23:49:16.437146 best dqsien dly found for B0: ( 1, 3, 26)
3486 23:49:16.440206 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3487 23:49:16.443734 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3488 23:49:16.443849
3489 23:49:16.446719 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3490 23:49:16.453653 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3491 23:49:16.453783 [Gating] SW calibration Done
3492 23:49:16.453883 ==
3493 23:49:16.456906 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 23:49:16.463206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 23:49:16.463365 ==
3496 23:49:16.463461 RX Vref Scan: 0
3497 23:49:16.463536
3498 23:49:16.466562 RX Vref 0 -> 0, step: 1
3499 23:49:16.466673
3500 23:49:16.470035 RX Delay -40 -> 252, step: 8
3501 23:49:16.473090 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3502 23:49:16.476924 iDelay=200, Bit 1, Center 119 (56 ~ 183) 128
3503 23:49:16.479986 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3504 23:49:16.487201 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3505 23:49:16.490439 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3506 23:49:16.493536 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3507 23:49:16.496843 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3508 23:49:16.499882 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3509 23:49:16.506940 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3510 23:49:16.510335 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3511 23:49:16.513598 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3512 23:49:16.516764 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3513 23:49:16.520036 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3514 23:49:16.526620 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3515 23:49:16.529903 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3516 23:49:16.533299 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3517 23:49:16.533432 ==
3518 23:49:16.536650 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 23:49:16.540001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 23:49:16.540088 ==
3521 23:49:16.543327 DQS Delay:
3522 23:49:16.543402 DQS0 = 0, DQS1 = 0
3523 23:49:16.546529 DQM Delay:
3524 23:49:16.546610 DQM0 = 121, DQM1 = 117
3525 23:49:16.546689 DQ Delay:
3526 23:49:16.549887 DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119
3527 23:49:16.556935 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3528 23:49:16.560131 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3529 23:49:16.563125 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3530 23:49:16.563210
3531 23:49:16.563276
3532 23:49:16.563336 ==
3533 23:49:16.566779 Dram Type= 6, Freq= 0, CH_1, rank 1
3534 23:49:16.569627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3535 23:49:16.569748 ==
3536 23:49:16.569853
3537 23:49:16.569944
3538 23:49:16.573311 TX Vref Scan disable
3539 23:49:16.576551 == TX Byte 0 ==
3540 23:49:16.579998 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3541 23:49:16.583326 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3542 23:49:16.586555 == TX Byte 1 ==
3543 23:49:16.589817 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3544 23:49:16.592929 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3545 23:49:16.593012 ==
3546 23:49:16.596502 Dram Type= 6, Freq= 0, CH_1, rank 1
3547 23:49:16.599430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3548 23:49:16.602671 ==
3549 23:49:16.613319 TX Vref=22, minBit 9, minWin=25, winSum=421
3550 23:49:16.616329 TX Vref=24, minBit 0, minWin=26, winSum=424
3551 23:49:16.619988 TX Vref=26, minBit 2, minWin=26, winSum=430
3552 23:49:16.623319 TX Vref=28, minBit 2, minWin=26, winSum=431
3553 23:49:16.626643 TX Vref=30, minBit 9, minWin=26, winSum=437
3554 23:49:16.632846 TX Vref=32, minBit 9, minWin=26, winSum=433
3555 23:49:16.636313 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
3556 23:49:16.636440
3557 23:49:16.639678 Final TX Range 1 Vref 30
3558 23:49:16.639788
3559 23:49:16.639883 ==
3560 23:49:16.643205 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 23:49:16.646578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 23:49:16.646690 ==
3563 23:49:16.649903
3564 23:49:16.650012
3565 23:49:16.650107 TX Vref Scan disable
3566 23:49:16.653176 == TX Byte 0 ==
3567 23:49:16.656495 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3568 23:49:16.659849 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3569 23:49:16.663233 == TX Byte 1 ==
3570 23:49:16.666434 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3571 23:49:16.669822 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3572 23:49:16.669933
3573 23:49:16.673023 [DATLAT]
3574 23:49:16.673127 Freq=1200, CH1 RK1
3575 23:49:16.673223
3576 23:49:16.676328 DATLAT Default: 0xd
3577 23:49:16.676438 0, 0xFFFF, sum = 0
3578 23:49:16.679860 1, 0xFFFF, sum = 0
3579 23:49:16.679971 2, 0xFFFF, sum = 0
3580 23:49:16.683364 3, 0xFFFF, sum = 0
3581 23:49:16.683475 4, 0xFFFF, sum = 0
3582 23:49:16.686192 5, 0xFFFF, sum = 0
3583 23:49:16.686304 6, 0xFFFF, sum = 0
3584 23:49:16.689590 7, 0xFFFF, sum = 0
3585 23:49:16.693033 8, 0xFFFF, sum = 0
3586 23:49:16.693147 9, 0xFFFF, sum = 0
3587 23:49:16.696190 10, 0xFFFF, sum = 0
3588 23:49:16.696303 11, 0xFFFF, sum = 0
3589 23:49:16.699507 12, 0x0, sum = 1
3590 23:49:16.699616 13, 0x0, sum = 2
3591 23:49:16.702643 14, 0x0, sum = 3
3592 23:49:16.702755 15, 0x0, sum = 4
3593 23:49:16.702853 best_step = 13
3594 23:49:16.706862
3595 23:49:16.706971 ==
3596 23:49:16.709556 Dram Type= 6, Freq= 0, CH_1, rank 1
3597 23:49:16.713164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3598 23:49:16.713272 ==
3599 23:49:16.713371 RX Vref Scan: 0
3600 23:49:16.713465
3601 23:49:16.716283 RX Vref 0 -> 0, step: 1
3602 23:49:16.716401
3603 23:49:16.719420 RX Delay -5 -> 252, step: 4
3604 23:49:16.723514 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3605 23:49:16.729278 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3606 23:49:16.732931 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3607 23:49:16.736348 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3608 23:49:16.739303 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3609 23:49:16.742610 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3610 23:49:16.749256 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3611 23:49:16.752545 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3612 23:49:16.755782 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3613 23:49:16.759146 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3614 23:49:16.762861 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3615 23:49:16.769562 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3616 23:49:16.772552 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3617 23:49:16.775787 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3618 23:49:16.779037 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3619 23:49:16.785526 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3620 23:49:16.785636 ==
3621 23:49:16.788778 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 23:49:16.792087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 23:49:16.792195 ==
3624 23:49:16.792294 DQS Delay:
3625 23:49:16.795243 DQS0 = 0, DQS1 = 0
3626 23:49:16.795350 DQM Delay:
3627 23:49:16.799019 DQM0 = 120, DQM1 = 118
3628 23:49:16.799128 DQ Delay:
3629 23:49:16.802185 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3630 23:49:16.805461 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3631 23:49:16.808750 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3632 23:49:16.812099 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3633 23:49:16.812218
3634 23:49:16.812315
3635 23:49:16.821870 [DQSOSCAuto] RK1, (LSB)MR18= 0x10ec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 403 ps
3636 23:49:16.825042 CH1 RK1: MR19=403, MR18=10EC
3637 23:49:16.828717 CH1_RK1: MR19=0x403, MR18=0x10EC, DQSOSC=403, MR23=63, INC=40, DEC=26
3638 23:49:16.831926 [RxdqsGatingPostProcess] freq 1200
3639 23:49:16.838815 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3640 23:49:16.841957 best DQS0 dly(2T, 0.5T) = (0, 11)
3641 23:49:16.845321 best DQS1 dly(2T, 0.5T) = (0, 11)
3642 23:49:16.848551 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3643 23:49:16.852237 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3644 23:49:16.855559 best DQS0 dly(2T, 0.5T) = (0, 11)
3645 23:49:16.858966 best DQS1 dly(2T, 0.5T) = (0, 11)
3646 23:49:16.862317 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3647 23:49:16.865645 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3648 23:49:16.868456 Pre-setting of DQS Precalculation
3649 23:49:16.871787 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3650 23:49:16.878670 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3651 23:49:16.885380 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3652 23:49:16.885527
3653 23:49:16.888802
3654 23:49:16.888911 [Calibration Summary] 2400 Mbps
3655 23:49:16.892114 CH 0, Rank 0
3656 23:49:16.892220 SW Impedance : PASS
3657 23:49:16.895351 DUTY Scan : NO K
3658 23:49:16.898720 ZQ Calibration : PASS
3659 23:49:16.898843 Jitter Meter : NO K
3660 23:49:16.902381 CBT Training : PASS
3661 23:49:16.905551 Write leveling : PASS
3662 23:49:16.905654 RX DQS gating : PASS
3663 23:49:16.908891 RX DQ/DQS(RDDQC) : PASS
3664 23:49:16.911590 TX DQ/DQS : PASS
3665 23:49:16.911693 RX DATLAT : PASS
3666 23:49:16.915557 RX DQ/DQS(Engine): PASS
3667 23:49:16.915680 TX OE : NO K
3668 23:49:16.918509 All Pass.
3669 23:49:16.918613
3670 23:49:16.918706 CH 0, Rank 1
3671 23:49:16.922030 SW Impedance : PASS
3672 23:49:16.922119 DUTY Scan : NO K
3673 23:49:16.924960 ZQ Calibration : PASS
3674 23:49:16.928265 Jitter Meter : NO K
3675 23:49:16.928373 CBT Training : PASS
3676 23:49:16.932310 Write leveling : PASS
3677 23:49:16.935264 RX DQS gating : PASS
3678 23:49:16.935376 RX DQ/DQS(RDDQC) : PASS
3679 23:49:16.938232 TX DQ/DQS : PASS
3680 23:49:16.941626 RX DATLAT : PASS
3681 23:49:16.941707 RX DQ/DQS(Engine): PASS
3682 23:49:16.945344 TX OE : NO K
3683 23:49:16.945452 All Pass.
3684 23:49:16.945546
3685 23:49:16.948352 CH 1, Rank 0
3686 23:49:16.948455 SW Impedance : PASS
3687 23:49:16.951904 DUTY Scan : NO K
3688 23:49:16.955302 ZQ Calibration : PASS
3689 23:49:16.955380 Jitter Meter : NO K
3690 23:49:16.958460 CBT Training : PASS
3691 23:49:16.961877 Write leveling : PASS
3692 23:49:16.961955 RX DQS gating : PASS
3693 23:49:16.965393 RX DQ/DQS(RDDQC) : PASS
3694 23:49:16.965474 TX DQ/DQS : PASS
3695 23:49:16.968872 RX DATLAT : PASS
3696 23:49:16.972055 RX DQ/DQS(Engine): PASS
3697 23:49:16.972138 TX OE : NO K
3698 23:49:16.975569 All Pass.
3699 23:49:16.975675
3700 23:49:16.975768 CH 1, Rank 1
3701 23:49:16.978315 SW Impedance : PASS
3702 23:49:16.978390 DUTY Scan : NO K
3703 23:49:16.981684 ZQ Calibration : PASS
3704 23:49:16.985214 Jitter Meter : NO K
3705 23:49:16.985319 CBT Training : PASS
3706 23:49:16.988678 Write leveling : PASS
3707 23:49:16.991823 RX DQS gating : PASS
3708 23:49:16.991897 RX DQ/DQS(RDDQC) : PASS
3709 23:49:16.995188 TX DQ/DQS : PASS
3710 23:49:16.998581 RX DATLAT : PASS
3711 23:49:16.998666 RX DQ/DQS(Engine): PASS
3712 23:49:17.001869 TX OE : NO K
3713 23:49:17.001954 All Pass.
3714 23:49:17.002020
3715 23:49:17.005316 DramC Write-DBI off
3716 23:49:17.008573 PER_BANK_REFRESH: Hybrid Mode
3717 23:49:17.008658 TX_TRACKING: ON
3718 23:49:17.018331 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3719 23:49:17.021783 [FAST_K] Save calibration result to emmc
3720 23:49:17.025017 dramc_set_vcore_voltage set vcore to 650000
3721 23:49:17.028512 Read voltage for 600, 5
3722 23:49:17.028626 Vio18 = 0
3723 23:49:17.028724 Vcore = 650000
3724 23:49:17.031969 Vdram = 0
3725 23:49:17.032055 Vddq = 0
3726 23:49:17.032122 Vmddr = 0
3727 23:49:17.038191 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3728 23:49:17.041474 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3729 23:49:17.044771 MEM_TYPE=3, freq_sel=19
3730 23:49:17.048465 sv_algorithm_assistance_LP4_1600
3731 23:49:17.051644 ============ PULL DRAM RESETB DOWN ============
3732 23:49:17.055152 ========== PULL DRAM RESETB DOWN end =========
3733 23:49:17.061440 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3734 23:49:17.065279 ===================================
3735 23:49:17.065366 LPDDR4 DRAM CONFIGURATION
3736 23:49:17.068409 ===================================
3737 23:49:17.071528 EX_ROW_EN[0] = 0x0
3738 23:49:17.074978 EX_ROW_EN[1] = 0x0
3739 23:49:17.075063 LP4Y_EN = 0x0
3740 23:49:17.078176 WORK_FSP = 0x0
3741 23:49:17.078261 WL = 0x2
3742 23:49:17.081748 RL = 0x2
3743 23:49:17.081833 BL = 0x2
3744 23:49:17.084733 RPST = 0x0
3745 23:49:17.084819 RD_PRE = 0x0
3746 23:49:17.088727 WR_PRE = 0x1
3747 23:49:17.088815 WR_PST = 0x0
3748 23:49:17.092015 DBI_WR = 0x0
3749 23:49:17.092099 DBI_RD = 0x0
3750 23:49:17.094553 OTF = 0x1
3751 23:49:17.098325 ===================================
3752 23:49:17.101596 ===================================
3753 23:49:17.101711 ANA top config
3754 23:49:17.105111 ===================================
3755 23:49:17.108666 DLL_ASYNC_EN = 0
3756 23:49:17.111069 ALL_SLAVE_EN = 1
3757 23:49:17.114436 NEW_RANK_MODE = 1
3758 23:49:17.114560 DLL_IDLE_MODE = 1
3759 23:49:17.117799 LP45_APHY_COMB_EN = 1
3760 23:49:17.121089 TX_ODT_DIS = 1
3761 23:49:17.124977 NEW_8X_MODE = 1
3762 23:49:17.128570 ===================================
3763 23:49:17.131670 ===================================
3764 23:49:17.131758 data_rate = 1200
3765 23:49:17.135135 CKR = 1
3766 23:49:17.138446 DQ_P2S_RATIO = 8
3767 23:49:17.141578 ===================================
3768 23:49:17.144886 CA_P2S_RATIO = 8
3769 23:49:17.148043 DQ_CA_OPEN = 0
3770 23:49:17.151444 DQ_SEMI_OPEN = 0
3771 23:49:17.151538 CA_SEMI_OPEN = 0
3772 23:49:17.154692 CA_FULL_RATE = 0
3773 23:49:17.157929 DQ_CKDIV4_EN = 1
3774 23:49:17.161338 CA_CKDIV4_EN = 1
3775 23:49:17.164845 CA_PREDIV_EN = 0
3776 23:49:17.168288 PH8_DLY = 0
3777 23:49:17.168396 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3778 23:49:17.171368 DQ_AAMCK_DIV = 4
3779 23:49:17.174801 CA_AAMCK_DIV = 4
3780 23:49:17.178106 CA_ADMCK_DIV = 4
3781 23:49:17.181394 DQ_TRACK_CA_EN = 0
3782 23:49:17.185074 CA_PICK = 600
3783 23:49:17.185156 CA_MCKIO = 600
3784 23:49:17.188633 MCKIO_SEMI = 0
3785 23:49:17.191103 PLL_FREQ = 2288
3786 23:49:17.194961 DQ_UI_PI_RATIO = 32
3787 23:49:17.198257 CA_UI_PI_RATIO = 0
3788 23:49:17.201434 ===================================
3789 23:49:17.204435 ===================================
3790 23:49:17.208189 memory_type:LPDDR4
3791 23:49:17.208302 GP_NUM : 10
3792 23:49:17.211398 SRAM_EN : 1
3793 23:49:17.211509 MD32_EN : 0
3794 23:49:17.214529 ===================================
3795 23:49:17.217981 [ANA_INIT] >>>>>>>>>>>>>>
3796 23:49:17.221336 <<<<<< [CONFIGURE PHASE]: ANA_TX
3797 23:49:17.224794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3798 23:49:17.228281 ===================================
3799 23:49:17.231608 data_rate = 1200,PCW = 0X5800
3800 23:49:17.234939 ===================================
3801 23:49:17.238259 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3802 23:49:17.241600 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3803 23:49:17.248008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3804 23:49:17.254360 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3805 23:49:17.257756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3806 23:49:17.261099 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3807 23:49:17.261233 [ANA_INIT] flow start
3808 23:49:17.264518 [ANA_INIT] PLL >>>>>>>>
3809 23:49:17.267858 [ANA_INIT] PLL <<<<<<<<
3810 23:49:17.267970 [ANA_INIT] MIDPI >>>>>>>>
3811 23:49:17.271210 [ANA_INIT] MIDPI <<<<<<<<
3812 23:49:17.274463 [ANA_INIT] DLL >>>>>>>>
3813 23:49:17.274574 [ANA_INIT] flow end
3814 23:49:17.281444 ============ LP4 DIFF to SE enter ============
3815 23:49:17.284429 ============ LP4 DIFF to SE exit ============
3816 23:49:17.284538 [ANA_INIT] <<<<<<<<<<<<<
3817 23:49:17.287546 [Flow] Enable top DCM control >>>>>
3818 23:49:17.291211 [Flow] Enable top DCM control <<<<<
3819 23:49:17.294533 Enable DLL master slave shuffle
3820 23:49:17.301038 ==============================================================
3821 23:49:17.304156 Gating Mode config
3822 23:49:17.307490 ==============================================================
3823 23:49:17.311334 Config description:
3824 23:49:17.321132 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3825 23:49:17.327688 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3826 23:49:17.331067 SELPH_MODE 0: By rank 1: By Phase
3827 23:49:17.337872 ==============================================================
3828 23:49:17.341187 GAT_TRACK_EN = 1
3829 23:49:17.344494 RX_GATING_MODE = 2
3830 23:49:17.347723 RX_GATING_TRACK_MODE = 2
3831 23:49:17.347834 SELPH_MODE = 1
3832 23:49:17.351031 PICG_EARLY_EN = 1
3833 23:49:17.354387 VALID_LAT_VALUE = 1
3834 23:49:17.360802 ==============================================================
3835 23:49:17.363916 Enter into Gating configuration >>>>
3836 23:49:17.367267 Exit from Gating configuration <<<<
3837 23:49:17.370559 Enter into DVFS_PRE_config >>>>>
3838 23:49:17.380688 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3839 23:49:17.384007 Exit from DVFS_PRE_config <<<<<
3840 23:49:17.387700 Enter into PICG configuration >>>>
3841 23:49:17.390907 Exit from PICG configuration <<<<
3842 23:49:17.393962 [RX_INPUT] configuration >>>>>
3843 23:49:17.397478 [RX_INPUT] configuration <<<<<
3844 23:49:17.400655 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3845 23:49:17.407644 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3846 23:49:17.414143 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3847 23:49:17.420647 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3848 23:49:17.424026 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3849 23:49:17.430476 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3850 23:49:17.434167 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3851 23:49:17.440629 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3852 23:49:17.443697 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3853 23:49:17.446987 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3854 23:49:17.450303 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3855 23:49:17.457053 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3856 23:49:17.460439 ===================================
3857 23:49:17.463954 LPDDR4 DRAM CONFIGURATION
3858 23:49:17.464063 ===================================
3859 23:49:17.467183 EX_ROW_EN[0] = 0x0
3860 23:49:17.470364 EX_ROW_EN[1] = 0x0
3861 23:49:17.470471 LP4Y_EN = 0x0
3862 23:49:17.474127 WORK_FSP = 0x0
3863 23:49:17.474235 WL = 0x2
3864 23:49:17.477619 RL = 0x2
3865 23:49:17.477727 BL = 0x2
3866 23:49:17.480189 RPST = 0x0
3867 23:49:17.480297 RD_PRE = 0x0
3868 23:49:17.483684 WR_PRE = 0x1
3869 23:49:17.483790 WR_PST = 0x0
3870 23:49:17.487031 DBI_WR = 0x0
3871 23:49:17.487157 DBI_RD = 0x0
3872 23:49:17.490349 OTF = 0x1
3873 23:49:17.493737 ===================================
3874 23:49:17.497162 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3875 23:49:17.500497 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3876 23:49:17.506661 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3877 23:49:17.510417 ===================================
3878 23:49:17.510514 LPDDR4 DRAM CONFIGURATION
3879 23:49:17.513488 ===================================
3880 23:49:17.516606 EX_ROW_EN[0] = 0x10
3881 23:49:17.520489 EX_ROW_EN[1] = 0x0
3882 23:49:17.520600 LP4Y_EN = 0x0
3883 23:49:17.523350 WORK_FSP = 0x0
3884 23:49:17.523458 WL = 0x2
3885 23:49:17.526645 RL = 0x2
3886 23:49:17.526755 BL = 0x2
3887 23:49:17.530352 RPST = 0x0
3888 23:49:17.530465 RD_PRE = 0x0
3889 23:49:17.533613 WR_PRE = 0x1
3890 23:49:17.533724 WR_PST = 0x0
3891 23:49:17.536912 DBI_WR = 0x0
3892 23:49:17.537021 DBI_RD = 0x0
3893 23:49:17.540307 OTF = 0x1
3894 23:49:17.543433 ===================================
3895 23:49:17.549995 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3896 23:49:17.553780 nWR fixed to 30
3897 23:49:17.553896 [ModeRegInit_LP4] CH0 RK0
3898 23:49:17.556938 [ModeRegInit_LP4] CH0 RK1
3899 23:49:17.560214 [ModeRegInit_LP4] CH1 RK0
3900 23:49:17.563655 [ModeRegInit_LP4] CH1 RK1
3901 23:49:17.563770 match AC timing 17
3902 23:49:17.569768 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3903 23:49:17.573263 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3904 23:49:17.576553 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3905 23:49:17.583080 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3906 23:49:17.586716 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3907 23:49:17.586828 ==
3908 23:49:17.590034 Dram Type= 6, Freq= 0, CH_0, rank 0
3909 23:49:17.592798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3910 23:49:17.592910 ==
3911 23:49:17.599510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3912 23:49:17.606079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3913 23:49:17.609464 [CA 0] Center 36 (5~67) winsize 63
3914 23:49:17.612860 [CA 1] Center 36 (5~67) winsize 63
3915 23:49:17.616259 [CA 2] Center 33 (3~64) winsize 62
3916 23:49:17.619381 [CA 3] Center 33 (2~64) winsize 63
3917 23:49:17.622919 [CA 4] Center 33 (2~64) winsize 63
3918 23:49:17.626115 [CA 5] Center 32 (1~63) winsize 63
3919 23:49:17.626221
3920 23:49:17.629753 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3921 23:49:17.629872
3922 23:49:17.632703 [CATrainingPosCal] consider 1 rank data
3923 23:49:17.636120 u2DelayCellTimex100 = 270/100 ps
3924 23:49:17.639264 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3925 23:49:17.642581 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3926 23:49:17.645890 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3927 23:49:17.649220 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3928 23:49:17.652524 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3929 23:49:17.655989 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
3930 23:49:17.656103
3931 23:49:17.663076 CA PerBit enable=1, Macro0, CA PI delay=32
3932 23:49:17.663190
3933 23:49:17.663285 [CBTSetCACLKResult] CA Dly = 32
3934 23:49:17.666241 CS Dly: 4 (0~35)
3935 23:49:17.666351 ==
3936 23:49:17.669875 Dram Type= 6, Freq= 0, CH_0, rank 1
3937 23:49:17.672954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3938 23:49:17.673068 ==
3939 23:49:17.679478 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3940 23:49:17.686205 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3941 23:49:17.689591 [CA 0] Center 35 (5~66) winsize 62
3942 23:49:17.692881 [CA 1] Center 35 (5~66) winsize 62
3943 23:49:17.696353 [CA 2] Center 34 (3~65) winsize 63
3944 23:49:17.699661 [CA 3] Center 33 (3~64) winsize 62
3945 23:49:17.703014 [CA 4] Center 32 (2~63) winsize 62
3946 23:49:17.706406 [CA 5] Center 32 (2~62) winsize 61
3947 23:49:17.706499
3948 23:49:17.709760 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3949 23:49:17.709841
3950 23:49:17.712502 [CATrainingPosCal] consider 2 rank data
3951 23:49:17.716127 u2DelayCellTimex100 = 270/100 ps
3952 23:49:17.719379 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3953 23:49:17.722646 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3954 23:49:17.725909 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3955 23:49:17.729171 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3956 23:49:17.732761 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3957 23:49:17.735941 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
3958 23:49:17.739178
3959 23:49:17.742430 CA PerBit enable=1, Macro0, CA PI delay=32
3960 23:49:17.742509
3961 23:49:17.746018 [CBTSetCACLKResult] CA Dly = 32
3962 23:49:17.746094 CS Dly: 4 (0~36)
3963 23:49:17.746158
3964 23:49:17.749103 ----->DramcWriteLeveling(PI) begin...
3965 23:49:17.749184 ==
3966 23:49:17.752730 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 23:49:17.755711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3968 23:49:17.758978 ==
3969 23:49:17.759060 Write leveling (Byte 0): 33 => 33
3970 23:49:17.762548 Write leveling (Byte 1): 32 => 32
3971 23:49:17.766364 DramcWriteLeveling(PI) end<-----
3972 23:49:17.766471
3973 23:49:17.766570 ==
3974 23:49:17.768882 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 23:49:17.775811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 23:49:17.775895 ==
3977 23:49:17.775962 [Gating] SW mode calibration
3978 23:49:17.785514 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3979 23:49:17.788737 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3980 23:49:17.792803 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 23:49:17.799489 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3982 23:49:17.802693 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3983 23:49:17.805961 0 9 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
3984 23:49:17.812089 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3985 23:49:17.815949 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 23:49:17.818768 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 23:49:17.825632 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 23:49:17.828906 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 23:49:17.832316 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3990 23:49:17.838897 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3991 23:49:17.842258 0 10 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (1 1)
3992 23:49:17.845637 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
3993 23:49:17.852064 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 23:49:17.855852 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 23:49:17.858708 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 23:49:17.865435 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 23:49:17.869100 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 23:49:17.872242 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3999 23:49:17.879199 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4000 23:49:17.882512 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 23:49:17.885950 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 23:49:17.889107 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 23:49:17.895577 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 23:49:17.898929 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 23:49:17.902299 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 23:49:17.909150 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 23:49:17.912085 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 23:49:17.915983 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 23:49:17.922018 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 23:49:17.925402 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 23:49:17.928678 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 23:49:17.935821 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 23:49:17.938869 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 23:49:17.942105 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 23:49:17.948600 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4016 23:49:17.951911 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4017 23:49:17.955197 Total UI for P1: 0, mck2ui 16
4018 23:49:17.958525 best dqsien dly found for B0: ( 0, 13, 12)
4019 23:49:17.962363 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 23:49:17.965554 Total UI for P1: 0, mck2ui 16
4021 23:49:17.969265 best dqsien dly found for B1: ( 0, 13, 18)
4022 23:49:17.972131 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4023 23:49:17.975488 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4024 23:49:17.978815
4025 23:49:17.982067 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4026 23:49:17.985237 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4027 23:49:17.988495 [Gating] SW calibration Done
4028 23:49:17.988602 ==
4029 23:49:17.992149 Dram Type= 6, Freq= 0, CH_0, rank 0
4030 23:49:17.995112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4031 23:49:17.995222 ==
4032 23:49:17.995317 RX Vref Scan: 0
4033 23:49:17.995409
4034 23:49:17.998602 RX Vref 0 -> 0, step: 1
4035 23:49:17.998712
4036 23:49:18.001700 RX Delay -230 -> 252, step: 16
4037 23:49:18.004984 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4038 23:49:18.011594 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4039 23:49:18.015262 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4040 23:49:18.018406 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4041 23:49:18.021973 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4042 23:49:18.024948 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4043 23:49:18.031764 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4044 23:49:18.035096 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4045 23:49:18.038149 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4046 23:49:18.041416 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4047 23:49:18.048482 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4048 23:49:18.051723 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4049 23:49:18.055153 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4050 23:49:18.058261 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4051 23:49:18.064850 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4052 23:49:18.068071 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4053 23:49:18.068158 ==
4054 23:49:18.071444 Dram Type= 6, Freq= 0, CH_0, rank 0
4055 23:49:18.074949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4056 23:49:18.075040 ==
4057 23:49:18.078040 DQS Delay:
4058 23:49:18.078120 DQS0 = 0, DQS1 = 0
4059 23:49:18.078185 DQM Delay:
4060 23:49:18.081272 DQM0 = 49, DQM1 = 46
4061 23:49:18.081383 DQ Delay:
4062 23:49:18.084358 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4063 23:49:18.087780 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4064 23:49:18.091506 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4065 23:49:18.094842 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4066 23:49:18.094952
4067 23:49:18.095047
4068 23:49:18.095137 ==
4069 23:49:18.098061 Dram Type= 6, Freq= 0, CH_0, rank 0
4070 23:49:18.104503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4071 23:49:18.104611 ==
4072 23:49:18.104705
4073 23:49:18.104796
4074 23:49:18.104886 TX Vref Scan disable
4075 23:49:18.107558 == TX Byte 0 ==
4076 23:49:18.111115 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4077 23:49:18.118081 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4078 23:49:18.118190 == TX Byte 1 ==
4079 23:49:18.121217 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4080 23:49:18.127844 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4081 23:49:18.127953 ==
4082 23:49:18.131036 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 23:49:18.134086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 23:49:18.134196 ==
4085 23:49:18.134287
4086 23:49:18.134375
4087 23:49:18.137697 TX Vref Scan disable
4088 23:49:18.140782 == TX Byte 0 ==
4089 23:49:18.144275 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4090 23:49:18.147698 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4091 23:49:18.150881 == TX Byte 1 ==
4092 23:49:18.154026 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4093 23:49:18.157269 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4094 23:49:18.157375
4095 23:49:18.157467 [DATLAT]
4096 23:49:18.161309 Freq=600, CH0 RK0
4097 23:49:18.161414
4098 23:49:18.161504 DATLAT Default: 0x9
4099 23:49:18.163978 0, 0xFFFF, sum = 0
4100 23:49:18.167794 1, 0xFFFF, sum = 0
4101 23:49:18.167902 2, 0xFFFF, sum = 0
4102 23:49:18.171118 3, 0xFFFF, sum = 0
4103 23:49:18.171298 4, 0xFFFF, sum = 0
4104 23:49:18.174419 5, 0xFFFF, sum = 0
4105 23:49:18.174558 6, 0xFFFF, sum = 0
4106 23:49:18.177364 7, 0xFFFF, sum = 0
4107 23:49:18.177473 8, 0x0, sum = 1
4108 23:49:18.180706 9, 0x0, sum = 2
4109 23:49:18.180815 10, 0x0, sum = 3
4110 23:49:18.180908 11, 0x0, sum = 4
4111 23:49:18.183913 best_step = 9
4112 23:49:18.183996
4113 23:49:18.184061 ==
4114 23:49:18.187222 Dram Type= 6, Freq= 0, CH_0, rank 0
4115 23:49:18.190582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4116 23:49:18.190673 ==
4117 23:49:18.193858 RX Vref Scan: 1
4118 23:49:18.193949
4119 23:49:18.194030 RX Vref 0 -> 0, step: 1
4120 23:49:18.197284
4121 23:49:18.197372 RX Delay -163 -> 252, step: 8
4122 23:49:18.197452
4123 23:49:18.200596 Set Vref, RX VrefLevel [Byte0]: 57
4124 23:49:18.203978 [Byte1]: 48
4125 23:49:18.208076
4126 23:49:18.208161 Final RX Vref Byte 0 = 57 to rank0
4127 23:49:18.211460 Final RX Vref Byte 1 = 48 to rank0
4128 23:49:18.214741 Final RX Vref Byte 0 = 57 to rank1
4129 23:49:18.218042 Final RX Vref Byte 1 = 48 to rank1==
4130 23:49:18.221197 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 23:49:18.227895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 23:49:18.227979 ==
4133 23:49:18.228053 DQS Delay:
4134 23:49:18.228115 DQS0 = 0, DQS1 = 0
4135 23:49:18.231667 DQM Delay:
4136 23:49:18.231759 DQM0 = 52, DQM1 = 45
4137 23:49:18.234491 DQ Delay:
4138 23:49:18.238322 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4139 23:49:18.241460 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =60
4140 23:49:18.241547 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4141 23:49:18.245131 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4142 23:49:18.248188
4143 23:49:18.248272
4144 23:49:18.254673 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4145 23:49:18.258417 CH0 RK0: MR19=808, MR18=6D61
4146 23:49:18.264829 CH0_RK0: MR19=0x808, MR18=0x6D61, DQSOSC=389, MR23=63, INC=173, DEC=115
4147 23:49:18.264950
4148 23:49:18.268106 ----->DramcWriteLeveling(PI) begin...
4149 23:49:18.268224 ==
4150 23:49:18.271212 Dram Type= 6, Freq= 0, CH_0, rank 1
4151 23:49:18.274655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 23:49:18.274738 ==
4153 23:49:18.278348 Write leveling (Byte 0): 34 => 34
4154 23:49:18.281945 Write leveling (Byte 1): 32 => 32
4155 23:49:18.284559 DramcWriteLeveling(PI) end<-----
4156 23:49:18.284670
4157 23:49:18.284765 ==
4158 23:49:18.288242 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 23:49:18.291530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 23:49:18.291643 ==
4161 23:49:18.294987 [Gating] SW mode calibration
4162 23:49:18.300941 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4163 23:49:18.307630 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4164 23:49:18.310882 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 23:49:18.317583 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4166 23:49:18.320931 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4167 23:49:18.324395 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 0) (1 1)
4168 23:49:18.327697 0 9 16 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
4169 23:49:18.334291 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 23:49:18.337743 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 23:49:18.341376 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 23:49:18.347517 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4173 23:49:18.350738 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4174 23:49:18.353928 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4175 23:49:18.360666 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4176 23:49:18.364018 0 10 16 | B1->B0 | 4040 4343 | 0 0 | (0 0) (0 0)
4177 23:49:18.367885 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 23:49:18.374016 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 23:49:18.377599 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 23:49:18.380601 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 23:49:18.387819 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4182 23:49:18.390879 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4183 23:49:18.394184 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4184 23:49:18.400183 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4185 23:49:18.403641 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 23:49:18.407060 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 23:49:18.413842 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 23:49:18.417371 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 23:49:18.420744 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 23:49:18.426834 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 23:49:18.430455 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 23:49:18.433791 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 23:49:18.440348 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 23:49:18.443841 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 23:49:18.447302 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 23:49:18.453435 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 23:49:18.456970 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 23:49:18.460061 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 23:49:18.467048 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4200 23:49:18.470446 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 23:49:18.473696 Total UI for P1: 0, mck2ui 16
4202 23:49:18.477063 best dqsien dly found for B0: ( 0, 13, 12)
4203 23:49:18.480305 Total UI for P1: 0, mck2ui 16
4204 23:49:18.483529 best dqsien dly found for B1: ( 0, 13, 12)
4205 23:49:18.486742 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4206 23:49:18.489812 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4207 23:49:18.489909
4208 23:49:18.493599 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4209 23:49:18.496780 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4210 23:49:18.500044 [Gating] SW calibration Done
4211 23:49:18.500175 ==
4212 23:49:18.503250 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 23:49:18.506557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 23:49:18.509795 ==
4215 23:49:18.509883 RX Vref Scan: 0
4216 23:49:18.509959
4217 23:49:18.513062 RX Vref 0 -> 0, step: 1
4218 23:49:18.513182
4219 23:49:18.516395 RX Delay -230 -> 252, step: 16
4220 23:49:18.519750 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4221 23:49:18.523217 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4222 23:49:18.526624 iDelay=218, Bit 2, Center 57 (-86 ~ 201) 288
4223 23:49:18.530051 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4224 23:49:18.536261 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4225 23:49:18.539501 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4226 23:49:18.543285 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4227 23:49:18.546623 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4228 23:49:18.549908 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4229 23:49:18.556554 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4230 23:49:18.559978 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4231 23:49:18.562756 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4232 23:49:18.566093 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4233 23:49:18.573364 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4234 23:49:18.576369 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4235 23:49:18.579609 iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288
4236 23:49:18.579718 ==
4237 23:49:18.582917 Dram Type= 6, Freq= 0, CH_0, rank 1
4238 23:49:18.586618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4239 23:49:18.586727 ==
4240 23:49:18.589810 DQS Delay:
4241 23:49:18.589896 DQS0 = 0, DQS1 = 0
4242 23:49:18.589968 DQM Delay:
4243 23:49:18.593140 DQM0 = 60, DQM1 = 48
4244 23:49:18.593224 DQ Delay:
4245 23:49:18.596432 DQ0 =57, DQ1 =57, DQ2 =57, DQ3 =57
4246 23:49:18.600090 DQ4 =65, DQ5 =57, DQ6 =65, DQ7 =65
4247 23:49:18.603139 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =33
4248 23:49:18.606350 DQ12 =57, DQ13 =57, DQ14 =57, DQ15 =57
4249 23:49:18.606430
4250 23:49:18.606496
4251 23:49:18.606567 ==
4252 23:49:18.609651 Dram Type= 6, Freq= 0, CH_0, rank 1
4253 23:49:18.616222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4254 23:49:18.616309 ==
4255 23:49:18.616414
4256 23:49:18.616507
4257 23:49:18.616601 TX Vref Scan disable
4258 23:49:18.620055 == TX Byte 0 ==
4259 23:49:18.623695 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4260 23:49:18.629869 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4261 23:49:18.629956 == TX Byte 1 ==
4262 23:49:18.633630 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4263 23:49:18.636794 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4264 23:49:18.640076 ==
4265 23:49:18.643627 Dram Type= 6, Freq= 0, CH_0, rank 1
4266 23:49:18.647012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4267 23:49:18.647098 ==
4268 23:49:18.647166
4269 23:49:18.647228
4270 23:49:18.650119 TX Vref Scan disable
4271 23:49:18.653639 == TX Byte 0 ==
4272 23:49:18.656531 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4273 23:49:18.660006 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4274 23:49:18.660091 == TX Byte 1 ==
4275 23:49:18.667056 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4276 23:49:18.670445 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4277 23:49:18.670526
4278 23:49:18.670593 [DATLAT]
4279 23:49:18.673748 Freq=600, CH0 RK1
4280 23:49:18.673831
4281 23:49:18.673898 DATLAT Default: 0x9
4282 23:49:18.677084 0, 0xFFFF, sum = 0
4283 23:49:18.677164 1, 0xFFFF, sum = 0
4284 23:49:18.680363 2, 0xFFFF, sum = 0
4285 23:49:18.680439 3, 0xFFFF, sum = 0
4286 23:49:18.683596 4, 0xFFFF, sum = 0
4287 23:49:18.683672 5, 0xFFFF, sum = 0
4288 23:49:18.687022 6, 0xFFFF, sum = 0
4289 23:49:18.690276 7, 0xFFFF, sum = 0
4290 23:49:18.690364 8, 0x0, sum = 1
4291 23:49:18.690431 9, 0x0, sum = 2
4292 23:49:18.693344 10, 0x0, sum = 3
4293 23:49:18.693421 11, 0x0, sum = 4
4294 23:49:18.696465 best_step = 9
4295 23:49:18.696539
4296 23:49:18.696600 ==
4297 23:49:18.700307 Dram Type= 6, Freq= 0, CH_0, rank 1
4298 23:49:18.703239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4299 23:49:18.703323 ==
4300 23:49:18.706769 RX Vref Scan: 0
4301 23:49:18.706840
4302 23:49:18.706920 RX Vref 0 -> 0, step: 1
4303 23:49:18.707006
4304 23:49:18.709493 RX Delay -163 -> 252, step: 8
4305 23:49:18.717283 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4306 23:49:18.720806 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4307 23:49:18.724076 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4308 23:49:18.726799 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4309 23:49:18.730562 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4310 23:49:18.736741 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4311 23:49:18.740354 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4312 23:49:18.743611 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4313 23:49:18.747129 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4314 23:49:18.750081 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4315 23:49:18.756996 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4316 23:49:18.760433 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4317 23:49:18.763932 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4318 23:49:18.767268 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4319 23:49:18.773360 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4320 23:49:18.776984 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4321 23:49:18.777068 ==
4322 23:49:18.780311 Dram Type= 6, Freq= 0, CH_0, rank 1
4323 23:49:18.783742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4324 23:49:18.783826 ==
4325 23:49:18.783893 DQS Delay:
4326 23:49:18.787076 DQS0 = 0, DQS1 = 0
4327 23:49:18.787170 DQM Delay:
4328 23:49:18.790480 DQM0 = 54, DQM1 = 47
4329 23:49:18.790564 DQ Delay:
4330 23:49:18.793836 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4331 23:49:18.797047 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =64
4332 23:49:18.800452 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4333 23:49:18.803731 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4334 23:49:18.803821
4335 23:49:18.803887
4336 23:49:18.813649 [DQSOSCAuto] RK1, (LSB)MR18= 0x6323, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4337 23:49:18.813733 CH0 RK1: MR19=808, MR18=6323
4338 23:49:18.820107 CH0_RK1: MR19=0x808, MR18=0x6323, DQSOSC=391, MR23=63, INC=171, DEC=114
4339 23:49:18.823530 [RxdqsGatingPostProcess] freq 600
4340 23:49:18.830146 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4341 23:49:18.833401 Pre-setting of DQS Precalculation
4342 23:49:18.836769 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4343 23:49:18.836872 ==
4344 23:49:18.840003 Dram Type= 6, Freq= 0, CH_1, rank 0
4345 23:49:18.843395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 23:49:18.846679 ==
4347 23:49:18.849905 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4348 23:49:18.856539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4349 23:49:18.860418 [CA 0] Center 36 (6~67) winsize 62
4350 23:49:18.863603 [CA 1] Center 36 (6~67) winsize 62
4351 23:49:18.866749 [CA 2] Center 35 (4~66) winsize 63
4352 23:49:18.869814 [CA 3] Center 34 (4~65) winsize 62
4353 23:49:18.873409 [CA 4] Center 34 (4~65) winsize 62
4354 23:49:18.876520 [CA 5] Center 34 (4~65) winsize 62
4355 23:49:18.876600
4356 23:49:18.880514 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4357 23:49:18.880611
4358 23:49:18.883677 [CATrainingPosCal] consider 1 rank data
4359 23:49:18.886942 u2DelayCellTimex100 = 270/100 ps
4360 23:49:18.889758 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4361 23:49:18.893100 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4362 23:49:18.896425 CA2 delay=35 (4~66),Diff = 1 PI (9 cell)
4363 23:49:18.899698 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4364 23:49:18.906302 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4365 23:49:18.910416 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4366 23:49:18.910522
4367 23:49:18.913499 CA PerBit enable=1, Macro0, CA PI delay=34
4368 23:49:18.913602
4369 23:49:18.916779 [CBTSetCACLKResult] CA Dly = 34
4370 23:49:18.916880 CS Dly: 5 (0~36)
4371 23:49:18.916975 ==
4372 23:49:18.920172 Dram Type= 6, Freq= 0, CH_1, rank 1
4373 23:49:18.926812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4374 23:49:18.926975 ==
4375 23:49:18.930251 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4376 23:49:18.936305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4377 23:49:18.940207 [CA 0] Center 36 (5~67) winsize 63
4378 23:49:18.943269 [CA 1] Center 36 (6~67) winsize 62
4379 23:49:18.946907 [CA 2] Center 35 (5~66) winsize 62
4380 23:49:18.949635 [CA 3] Center 35 (4~66) winsize 63
4381 23:49:18.952980 [CA 4] Center 34 (4~65) winsize 62
4382 23:49:18.956306 [CA 5] Center 34 (4~65) winsize 62
4383 23:49:18.956421
4384 23:49:18.959613 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4385 23:49:18.959712
4386 23:49:18.962882 [CATrainingPosCal] consider 2 rank data
4387 23:49:18.966286 u2DelayCellTimex100 = 270/100 ps
4388 23:49:18.969585 CA0 delay=36 (6~67),Diff = 2 PI (19 cell)
4389 23:49:18.972946 CA1 delay=36 (6~67),Diff = 2 PI (19 cell)
4390 23:49:18.976380 CA2 delay=35 (5~66),Diff = 1 PI (9 cell)
4391 23:49:18.983094 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 23:49:18.986492 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4393 23:49:18.989464 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4394 23:49:18.989570
4395 23:49:18.992725 CA PerBit enable=1, Macro0, CA PI delay=34
4396 23:49:18.992831
4397 23:49:18.996775 [CBTSetCACLKResult] CA Dly = 34
4398 23:49:18.996852 CS Dly: 6 (0~38)
4399 23:49:18.996916
4400 23:49:18.999420 ----->DramcWriteLeveling(PI) begin...
4401 23:49:18.999516 ==
4402 23:49:19.002714 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 23:49:19.009336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4404 23:49:19.009422 ==
4405 23:49:19.012764 Write leveling (Byte 0): 32 => 32
4406 23:49:19.016234 Write leveling (Byte 1): 28 => 28
4407 23:49:19.016310 DramcWriteLeveling(PI) end<-----
4408 23:49:19.019799
4409 23:49:19.019871 ==
4410 23:49:19.023115 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 23:49:19.026509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 23:49:19.026584 ==
4413 23:49:19.029677 [Gating] SW mode calibration
4414 23:49:19.036036 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4415 23:49:19.039392 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4416 23:49:19.046269 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 23:49:19.049607 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 23:49:19.052946 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4419 23:49:19.059356 0 9 12 | B1->B0 | 3030 3030 | 1 1 | (1 1) (1 1)
4420 23:49:19.062574 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 23:49:19.066600 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 23:49:19.072952 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 23:49:19.076350 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 23:49:19.079846 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 23:49:19.085928 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 23:49:19.089320 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4427 23:49:19.093076 0 10 12 | B1->B0 | 3636 3a3a | 1 1 | (0 0) (0 0)
4428 23:49:19.099389 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 23:49:19.102948 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 23:49:19.105931 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 23:49:19.112780 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 23:49:19.115904 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 23:49:19.119122 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 23:49:19.126047 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4435 23:49:19.129441 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4436 23:49:19.132832 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 23:49:19.139521 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 23:49:19.142512 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 23:49:19.145591 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 23:49:19.152234 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 23:49:19.155596 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 23:49:19.159017 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 23:49:19.162375 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 23:49:19.168963 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 23:49:19.172186 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 23:49:19.175621 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 23:49:19.182459 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 23:49:19.185911 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 23:49:19.189213 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 23:49:19.195295 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 23:49:19.199348 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4452 23:49:19.202396 Total UI for P1: 0, mck2ui 16
4453 23:49:19.205683 best dqsien dly found for B0: ( 0, 13, 10)
4454 23:49:19.209095 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 23:49:19.212067 Total UI for P1: 0, mck2ui 16
4456 23:49:19.215635 best dqsien dly found for B1: ( 0, 13, 12)
4457 23:49:19.219121 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4458 23:49:19.222278 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4459 23:49:19.222354
4460 23:49:19.228905 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4461 23:49:19.232509 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4462 23:49:19.235248 [Gating] SW calibration Done
4463 23:49:19.235324 ==
4464 23:49:19.238547 Dram Type= 6, Freq= 0, CH_1, rank 0
4465 23:49:19.241961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4466 23:49:19.242039 ==
4467 23:49:19.242103 RX Vref Scan: 0
4468 23:49:19.242169
4469 23:49:19.245216 RX Vref 0 -> 0, step: 1
4470 23:49:19.245298
4471 23:49:19.248746 RX Delay -230 -> 252, step: 16
4472 23:49:19.251863 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4473 23:49:19.255274 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4474 23:49:19.262259 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4475 23:49:19.265465 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4476 23:49:19.268764 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4477 23:49:19.272605 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4478 23:49:19.278857 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4479 23:49:19.281958 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4480 23:49:19.285096 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4481 23:49:19.288418 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4482 23:49:19.291849 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4483 23:49:19.298649 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4484 23:49:19.301940 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4485 23:49:19.305131 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4486 23:49:19.308524 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4487 23:49:19.315387 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4488 23:49:19.315467 ==
4489 23:49:19.318535 Dram Type= 6, Freq= 0, CH_1, rank 0
4490 23:49:19.321757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4491 23:49:19.321845 ==
4492 23:49:19.321912 DQS Delay:
4493 23:49:19.325422 DQS0 = 0, DQS1 = 0
4494 23:49:19.325519 DQM Delay:
4495 23:49:19.328702 DQM0 = 47, DQM1 = 44
4496 23:49:19.328786 DQ Delay:
4497 23:49:19.331704 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41
4498 23:49:19.335390 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4499 23:49:19.338404 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4500 23:49:19.341985 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4501 23:49:19.342106
4502 23:49:19.342203
4503 23:49:19.342350 ==
4504 23:49:19.345162 Dram Type= 6, Freq= 0, CH_1, rank 0
4505 23:49:19.348528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4506 23:49:19.351889 ==
4507 23:49:19.352005
4508 23:49:19.352071
4509 23:49:19.352132 TX Vref Scan disable
4510 23:49:19.355274 == TX Byte 0 ==
4511 23:49:19.358738 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4512 23:49:19.361967 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4513 23:49:19.365192 == TX Byte 1 ==
4514 23:49:19.369077 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4515 23:49:19.371866 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4516 23:49:19.372051 ==
4517 23:49:19.375412 Dram Type= 6, Freq= 0, CH_1, rank 0
4518 23:49:19.382322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4519 23:49:19.382441 ==
4520 23:49:19.382512
4521 23:49:19.382573
4522 23:49:19.382632 TX Vref Scan disable
4523 23:49:19.386269 == TX Byte 0 ==
4524 23:49:19.389718 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4525 23:49:19.396337 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4526 23:49:19.396462 == TX Byte 1 ==
4527 23:49:19.399753 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4528 23:49:19.406362 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4529 23:49:19.406449
4530 23:49:19.406515 [DATLAT]
4531 23:49:19.406576 Freq=600, CH1 RK0
4532 23:49:19.406636
4533 23:49:19.409478 DATLAT Default: 0x9
4534 23:49:19.409560 0, 0xFFFF, sum = 0
4535 23:49:19.412898 1, 0xFFFF, sum = 0
4536 23:49:19.412983 2, 0xFFFF, sum = 0
4537 23:49:19.416182 3, 0xFFFF, sum = 0
4538 23:49:19.419569 4, 0xFFFF, sum = 0
4539 23:49:19.419653 5, 0xFFFF, sum = 0
4540 23:49:19.422818 6, 0xFFFF, sum = 0
4541 23:49:19.422902 7, 0xFFFF, sum = 0
4542 23:49:19.426189 8, 0x0, sum = 1
4543 23:49:19.426272 9, 0x0, sum = 2
4544 23:49:19.426339 10, 0x0, sum = 3
4545 23:49:19.430274 11, 0x0, sum = 4
4546 23:49:19.430358 best_step = 9
4547 23:49:19.430423
4548 23:49:19.430483 ==
4549 23:49:19.433305 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 23:49:19.439882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 23:49:19.439966 ==
4552 23:49:19.440031 RX Vref Scan: 1
4553 23:49:19.440092
4554 23:49:19.443001 RX Vref 0 -> 0, step: 1
4555 23:49:19.443083
4556 23:49:19.446599 RX Delay -163 -> 252, step: 8
4557 23:49:19.446682
4558 23:49:19.449719 Set Vref, RX VrefLevel [Byte0]: 54
4559 23:49:19.453455 [Byte1]: 55
4560 23:49:19.453558
4561 23:49:19.456849 Final RX Vref Byte 0 = 54 to rank0
4562 23:49:19.460126 Final RX Vref Byte 1 = 55 to rank0
4563 23:49:19.463429 Final RX Vref Byte 0 = 54 to rank1
4564 23:49:19.466785 Final RX Vref Byte 1 = 55 to rank1==
4565 23:49:19.470133 Dram Type= 6, Freq= 0, CH_1, rank 0
4566 23:49:19.472834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4567 23:49:19.472917 ==
4568 23:49:19.476695 DQS Delay:
4569 23:49:19.476778 DQS0 = 0, DQS1 = 0
4570 23:49:19.476842 DQM Delay:
4571 23:49:19.480078 DQM0 = 48, DQM1 = 44
4572 23:49:19.480160 DQ Delay:
4573 23:49:19.483436 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4574 23:49:19.486652 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4575 23:49:19.489914 DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =36
4576 23:49:19.493341 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4577 23:49:19.493424
4578 23:49:19.493489
4579 23:49:19.503232 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d73, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4580 23:49:19.503316 CH1 RK0: MR19=808, MR18=4D73
4581 23:49:19.509369 CH1_RK0: MR19=0x808, MR18=0x4D73, DQSOSC=388, MR23=63, INC=174, DEC=116
4582 23:49:19.509455
4583 23:49:19.512850 ----->DramcWriteLeveling(PI) begin...
4584 23:49:19.515954 ==
4585 23:49:19.519808 Dram Type= 6, Freq= 0, CH_1, rank 1
4586 23:49:19.523228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4587 23:49:19.523304 ==
4588 23:49:19.526487 Write leveling (Byte 0): 31 => 31
4589 23:49:19.529781 Write leveling (Byte 1): 31 => 31
4590 23:49:19.532935 DramcWriteLeveling(PI) end<-----
4591 23:49:19.533012
4592 23:49:19.533076 ==
4593 23:49:19.536208 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 23:49:19.539298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 23:49:19.539376 ==
4596 23:49:19.542648 [Gating] SW mode calibration
4597 23:49:19.549799 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4598 23:49:19.553077 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4599 23:49:19.559493 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4600 23:49:19.562542 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4601 23:49:19.566504 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4602 23:49:19.572581 0 9 12 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
4603 23:49:19.575966 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 23:49:19.579319 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 23:49:19.585927 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 23:49:19.589383 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 23:49:19.592764 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 23:49:19.599515 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4609 23:49:19.602522 0 10 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
4610 23:49:19.605921 0 10 12 | B1->B0 | 3b3b 3939 | 0 0 | (0 0) (1 1)
4611 23:49:19.612886 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 23:49:19.615932 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 23:49:19.619150 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 23:49:19.626215 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 23:49:19.629041 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 23:49:19.632410 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 23:49:19.639167 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 23:49:19.642804 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4619 23:49:19.645526 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 23:49:19.652243 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 23:49:19.655475 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 23:49:19.658854 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 23:49:19.665870 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 23:49:19.668871 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 23:49:19.672316 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 23:49:19.679154 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 23:49:19.682480 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 23:49:19.685722 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 23:49:19.691831 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 23:49:19.695226 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 23:49:19.698505 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 23:49:19.702445 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 23:49:19.708873 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4634 23:49:19.712296 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4635 23:49:19.715432 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 23:49:19.718741 Total UI for P1: 0, mck2ui 16
4637 23:49:19.722141 best dqsien dly found for B0: ( 0, 13, 10)
4638 23:49:19.725378 Total UI for P1: 0, mck2ui 16
4639 23:49:19.728863 best dqsien dly found for B1: ( 0, 13, 10)
4640 23:49:19.731785 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4641 23:49:19.738673 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4642 23:49:19.738754
4643 23:49:19.741818 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4644 23:49:19.745411 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4645 23:49:19.748564 [Gating] SW calibration Done
4646 23:49:19.748638 ==
4647 23:49:19.751696 Dram Type= 6, Freq= 0, CH_1, rank 1
4648 23:49:19.754961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4649 23:49:19.755071 ==
4650 23:49:19.758263 RX Vref Scan: 0
4651 23:49:19.758337
4652 23:49:19.758414 RX Vref 0 -> 0, step: 1
4653 23:49:19.758475
4654 23:49:19.761509 RX Delay -230 -> 252, step: 16
4655 23:49:19.764831 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4656 23:49:19.771530 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4657 23:49:19.775401 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4658 23:49:19.778493 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4659 23:49:19.781682 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4660 23:49:19.785303 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4661 23:49:19.791479 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4662 23:49:19.795413 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4663 23:49:19.798078 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4664 23:49:19.801464 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4665 23:49:19.808693 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4666 23:49:19.811852 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4667 23:49:19.814868 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4668 23:49:19.818325 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4669 23:49:19.825282 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4670 23:49:19.828516 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4671 23:49:19.828600 ==
4672 23:49:19.831879 Dram Type= 6, Freq= 0, CH_1, rank 1
4673 23:49:19.835094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4674 23:49:19.835202 ==
4675 23:49:19.835296 DQS Delay:
4676 23:49:19.838455 DQS0 = 0, DQS1 = 0
4677 23:49:19.838557 DQM Delay:
4678 23:49:19.841525 DQM0 = 50, DQM1 = 48
4679 23:49:19.841601 DQ Delay:
4680 23:49:19.844845 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4681 23:49:19.848075 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4682 23:49:19.851334 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4683 23:49:19.855215 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4684 23:49:19.855318
4685 23:49:19.855413
4686 23:49:19.855502 ==
4687 23:49:19.858209 Dram Type= 6, Freq= 0, CH_1, rank 1
4688 23:49:19.861281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4689 23:49:19.864800 ==
4690 23:49:19.864905
4691 23:49:19.865011
4692 23:49:19.865101 TX Vref Scan disable
4693 23:49:19.868009 == TX Byte 0 ==
4694 23:49:19.871385 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4695 23:49:19.874754 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4696 23:49:19.878106 == TX Byte 1 ==
4697 23:49:19.881558 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4698 23:49:19.884693 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4699 23:49:19.888595 ==
4700 23:49:19.888673 Dram Type= 6, Freq= 0, CH_1, rank 1
4701 23:49:19.895576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4702 23:49:19.895669 ==
4703 23:49:19.895773
4704 23:49:19.895880
4705 23:49:19.897997 TX Vref Scan disable
4706 23:49:19.898101 == TX Byte 0 ==
4707 23:49:19.904859 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4708 23:49:19.908201 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4709 23:49:19.908304 == TX Byte 1 ==
4710 23:49:19.915257 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4711 23:49:19.918203 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4712 23:49:19.918310
4713 23:49:19.918405 [DATLAT]
4714 23:49:19.921345 Freq=600, CH1 RK1
4715 23:49:19.921456
4716 23:49:19.921549 DATLAT Default: 0x9
4717 23:49:19.924884 0, 0xFFFF, sum = 0
4718 23:49:19.924964 1, 0xFFFF, sum = 0
4719 23:49:19.927915 2, 0xFFFF, sum = 0
4720 23:49:19.928017 3, 0xFFFF, sum = 0
4721 23:49:19.931165 4, 0xFFFF, sum = 0
4722 23:49:19.934539 5, 0xFFFF, sum = 0
4723 23:49:19.934646 6, 0xFFFF, sum = 0
4724 23:49:19.937898 7, 0xFFFF, sum = 0
4725 23:49:19.938002 8, 0x0, sum = 1
4726 23:49:19.938099 9, 0x0, sum = 2
4727 23:49:19.941184 10, 0x0, sum = 3
4728 23:49:19.941286 11, 0x0, sum = 4
4729 23:49:19.944502 best_step = 9
4730 23:49:19.944604
4731 23:49:19.944696 ==
4732 23:49:19.947664 Dram Type= 6, Freq= 0, CH_1, rank 1
4733 23:49:19.951001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4734 23:49:19.951101 ==
4735 23:49:19.954393 RX Vref Scan: 0
4736 23:49:19.954495
4737 23:49:19.954589 RX Vref 0 -> 0, step: 1
4738 23:49:19.954680
4739 23:49:19.957641 RX Delay -163 -> 252, step: 8
4740 23:49:19.964864 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4741 23:49:19.968149 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4742 23:49:19.971447 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4743 23:49:19.975009 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4744 23:49:19.981704 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4745 23:49:19.984712 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4746 23:49:19.987811 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4747 23:49:19.991718 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4748 23:49:19.995337 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4749 23:49:20.001888 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4750 23:49:20.004607 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4751 23:49:20.008610 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4752 23:49:20.011612 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4753 23:49:20.015269 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4754 23:49:20.021728 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4755 23:49:20.024644 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4756 23:49:20.024738 ==
4757 23:49:20.027991 Dram Type= 6, Freq= 0, CH_1, rank 1
4758 23:49:20.031529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 23:49:20.031643 ==
4760 23:49:20.035123 DQS Delay:
4761 23:49:20.035230 DQS0 = 0, DQS1 = 0
4762 23:49:20.035328 DQM Delay:
4763 23:49:20.038137 DQM0 = 49, DQM1 = 45
4764 23:49:20.038241 DQ Delay:
4765 23:49:20.041524 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4766 23:49:20.044883 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4767 23:49:20.047994 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4768 23:49:20.051788 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4769 23:49:20.051895
4770 23:49:20.052001
4771 23:49:20.061400 [DQSOSCAuto] RK1, (LSB)MR18= 0x6b22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4772 23:49:20.061509 CH1 RK1: MR19=808, MR18=6B22
4773 23:49:20.067829 CH1_RK1: MR19=0x808, MR18=0x6B22, DQSOSC=389, MR23=63, INC=173, DEC=115
4774 23:49:20.071331 [RxdqsGatingPostProcess] freq 600
4775 23:49:20.077649 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4776 23:49:20.080965 Pre-setting of DQS Precalculation
4777 23:49:20.084174 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4778 23:49:20.091295 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4779 23:49:20.100844 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4780 23:49:20.100986
4781 23:49:20.101093
4782 23:49:20.104222 [Calibration Summary] 1200 Mbps
4783 23:49:20.104321 CH 0, Rank 0
4784 23:49:20.107563 SW Impedance : PASS
4785 23:49:20.107637 DUTY Scan : NO K
4786 23:49:20.110822 ZQ Calibration : PASS
4787 23:49:20.114829 Jitter Meter : NO K
4788 23:49:20.114935 CBT Training : PASS
4789 23:49:20.117465 Write leveling : PASS
4790 23:49:20.117563 RX DQS gating : PASS
4791 23:49:20.120810 RX DQ/DQS(RDDQC) : PASS
4792 23:49:20.124203 TX DQ/DQS : PASS
4793 23:49:20.124305 RX DATLAT : PASS
4794 23:49:20.127331 RX DQ/DQS(Engine): PASS
4795 23:49:20.130668 TX OE : NO K
4796 23:49:20.130769 All Pass.
4797 23:49:20.130864
4798 23:49:20.130953 CH 0, Rank 1
4799 23:49:20.134483 SW Impedance : PASS
4800 23:49:20.137582 DUTY Scan : NO K
4801 23:49:20.137680 ZQ Calibration : PASS
4802 23:49:20.140626 Jitter Meter : NO K
4803 23:49:20.144407 CBT Training : PASS
4804 23:49:20.144513 Write leveling : PASS
4805 23:49:20.147428 RX DQS gating : PASS
4806 23:49:20.151008 RX DQ/DQS(RDDQC) : PASS
4807 23:49:20.151115 TX DQ/DQS : PASS
4808 23:49:20.154451 RX DATLAT : PASS
4809 23:49:20.157611 RX DQ/DQS(Engine): PASS
4810 23:49:20.157717 TX OE : NO K
4811 23:49:20.157791 All Pass.
4812 23:49:20.160906
4813 23:49:20.160989 CH 1, Rank 0
4814 23:49:20.164406 SW Impedance : PASS
4815 23:49:20.164488 DUTY Scan : NO K
4816 23:49:20.167348 ZQ Calibration : PASS
4817 23:49:20.167452 Jitter Meter : NO K
4818 23:49:20.170666 CBT Training : PASS
4819 23:49:20.173940 Write leveling : PASS
4820 23:49:20.174014 RX DQS gating : PASS
4821 23:49:20.177206 RX DQ/DQS(RDDQC) : PASS
4822 23:49:20.180549 TX DQ/DQS : PASS
4823 23:49:20.180630 RX DATLAT : PASS
4824 23:49:20.183862 RX DQ/DQS(Engine): PASS
4825 23:49:20.187175 TX OE : NO K
4826 23:49:20.187277 All Pass.
4827 23:49:20.187372
4828 23:49:20.187462 CH 1, Rank 1
4829 23:49:20.190520 SW Impedance : PASS
4830 23:49:20.193870 DUTY Scan : NO K
4831 23:49:20.193977 ZQ Calibration : PASS
4832 23:49:20.197200 Jitter Meter : NO K
4833 23:49:20.200433 CBT Training : PASS
4834 23:49:20.200511 Write leveling : PASS
4835 23:49:20.203684 RX DQS gating : PASS
4836 23:49:20.207417 RX DQ/DQS(RDDQC) : PASS
4837 23:49:20.207500 TX DQ/DQS : PASS
4838 23:49:20.210400 RX DATLAT : PASS
4839 23:49:20.213938 RX DQ/DQS(Engine): PASS
4840 23:49:20.214044 TX OE : NO K
4841 23:49:20.214138 All Pass.
4842 23:49:20.217414
4843 23:49:20.217523 DramC Write-DBI off
4844 23:49:20.220858 PER_BANK_REFRESH: Hybrid Mode
4845 23:49:20.220955 TX_TRACKING: ON
4846 23:49:20.230642 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4847 23:49:20.234196 [FAST_K] Save calibration result to emmc
4848 23:49:20.237315 dramc_set_vcore_voltage set vcore to 662500
4849 23:49:20.240444 Read voltage for 933, 3
4850 23:49:20.240528 Vio18 = 0
4851 23:49:20.243741 Vcore = 662500
4852 23:49:20.243846 Vdram = 0
4853 23:49:20.243940 Vddq = 0
4854 23:49:20.244031 Vmddr = 0
4855 23:49:20.250848 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4856 23:49:20.254230 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4857 23:49:20.257467 MEM_TYPE=3, freq_sel=17
4858 23:49:20.260770 sv_algorithm_assistance_LP4_1600
4859 23:49:20.263878 ============ PULL DRAM RESETB DOWN ============
4860 23:49:20.267519 ========== PULL DRAM RESETB DOWN end =========
4861 23:49:20.274152 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4862 23:49:20.277788 ===================================
4863 23:49:20.281191 LPDDR4 DRAM CONFIGURATION
4864 23:49:20.284300 ===================================
4865 23:49:20.284400 EX_ROW_EN[0] = 0x0
4866 23:49:20.287220 EX_ROW_EN[1] = 0x0
4867 23:49:20.287321 LP4Y_EN = 0x0
4868 23:49:20.291180 WORK_FSP = 0x0
4869 23:49:20.291256 WL = 0x3
4870 23:49:20.294466 RL = 0x3
4871 23:49:20.294575 BL = 0x2
4872 23:49:20.297229 RPST = 0x0
4873 23:49:20.297331 RD_PRE = 0x0
4874 23:49:20.300526 WR_PRE = 0x1
4875 23:49:20.300609 WR_PST = 0x0
4876 23:49:20.303936 DBI_WR = 0x0
4877 23:49:20.304038 DBI_RD = 0x0
4878 23:49:20.307338 OTF = 0x1
4879 23:49:20.310506 ===================================
4880 23:49:20.313827 ===================================
4881 23:49:20.313930 ANA top config
4882 23:49:20.317399 ===================================
4883 23:49:20.320330 DLL_ASYNC_EN = 0
4884 23:49:20.324253 ALL_SLAVE_EN = 1
4885 23:49:20.327441 NEW_RANK_MODE = 1
4886 23:49:20.327546 DLL_IDLE_MODE = 1
4887 23:49:20.330372 LP45_APHY_COMB_EN = 1
4888 23:49:20.333859 TX_ODT_DIS = 1
4889 23:49:20.342857 NEW_8X_MODE = 1
4890 23:49:20.343014 ===================================
4891 23:49:20.343629 ===================================
4892 23:49:20.346936 data_rate = 1866
4893 23:49:20.350324 CKR = 1
4894 23:49:20.350432 DQ_P2S_RATIO = 8
4895 23:49:20.353736 ===================================
4896 23:49:20.357023 CA_P2S_RATIO = 8
4897 23:49:20.360816 DQ_CA_OPEN = 0
4898 23:49:20.364123 DQ_SEMI_OPEN = 0
4899 23:49:20.367504 CA_SEMI_OPEN = 0
4900 23:49:20.367619 CA_FULL_RATE = 0
4901 23:49:20.370891 DQ_CKDIV4_EN = 1
4902 23:49:20.373834 CA_CKDIV4_EN = 1
4903 23:49:20.377562 CA_PREDIV_EN = 0
4904 23:49:20.380414 PH8_DLY = 0
4905 23:49:20.384244 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4906 23:49:20.384352 DQ_AAMCK_DIV = 4
4907 23:49:20.387240 CA_AAMCK_DIV = 4
4908 23:49:20.390642 CA_ADMCK_DIV = 4
4909 23:49:20.393912 DQ_TRACK_CA_EN = 0
4910 23:49:20.397057 CA_PICK = 933
4911 23:49:20.400208 CA_MCKIO = 933
4912 23:49:20.403749 MCKIO_SEMI = 0
4913 23:49:20.403862 PLL_FREQ = 3732
4914 23:49:20.407373 DQ_UI_PI_RATIO = 32
4915 23:49:20.410679 CA_UI_PI_RATIO = 0
4916 23:49:20.414190 ===================================
4917 23:49:20.416759 ===================================
4918 23:49:20.420049 memory_type:LPDDR4
4919 23:49:20.420157 GP_NUM : 10
4920 23:49:20.423430 SRAM_EN : 1
4921 23:49:20.426694 MD32_EN : 0
4922 23:49:20.429965 ===================================
4923 23:49:20.430067 [ANA_INIT] >>>>>>>>>>>>>>
4924 23:49:20.433880 <<<<<< [CONFIGURE PHASE]: ANA_TX
4925 23:49:20.437388 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4926 23:49:20.440411 ===================================
4927 23:49:20.443409 data_rate = 1866,PCW = 0X8f00
4928 23:49:20.446859 ===================================
4929 23:49:20.450327 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4930 23:49:20.457263 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4931 23:49:20.460653 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4932 23:49:20.467330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4933 23:49:20.470495 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4934 23:49:20.474479 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4935 23:49:20.474648 [ANA_INIT] flow start
4936 23:49:20.477302 [ANA_INIT] PLL >>>>>>>>
4937 23:49:20.480679 [ANA_INIT] PLL <<<<<<<<
4938 23:49:20.483493 [ANA_INIT] MIDPI >>>>>>>>
4939 23:49:20.483711 [ANA_INIT] MIDPI <<<<<<<<
4940 23:49:20.486857 [ANA_INIT] DLL >>>>>>>>
4941 23:49:20.486992 [ANA_INIT] flow end
4942 23:49:20.493703 ============ LP4 DIFF to SE enter ============
4943 23:49:20.497061 ============ LP4 DIFF to SE exit ============
4944 23:49:20.500437 [ANA_INIT] <<<<<<<<<<<<<
4945 23:49:20.503555 [Flow] Enable top DCM control >>>>>
4946 23:49:20.507207 [Flow] Enable top DCM control <<<<<
4947 23:49:20.510251 Enable DLL master slave shuffle
4948 23:49:20.513677 ==============================================================
4949 23:49:20.516989 Gating Mode config
4950 23:49:20.519978 ==============================================================
4951 23:49:20.523468 Config description:
4952 23:49:20.533545 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4953 23:49:20.540177 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4954 23:49:20.543542 SELPH_MODE 0: By rank 1: By Phase
4955 23:49:20.550236 ==============================================================
4956 23:49:20.553436 GAT_TRACK_EN = 1
4957 23:49:20.557063 RX_GATING_MODE = 2
4958 23:49:20.560147 RX_GATING_TRACK_MODE = 2
4959 23:49:20.563908 SELPH_MODE = 1
4960 23:49:20.564015 PICG_EARLY_EN = 1
4961 23:49:20.567013 VALID_LAT_VALUE = 1
4962 23:49:20.573779 ==============================================================
4963 23:49:20.576680 Enter into Gating configuration >>>>
4964 23:49:20.580415 Exit from Gating configuration <<<<
4965 23:49:20.583643 Enter into DVFS_PRE_config >>>>>
4966 23:49:20.593839 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4967 23:49:20.597188 Exit from DVFS_PRE_config <<<<<
4968 23:49:20.600610 Enter into PICG configuration >>>>
4969 23:49:20.603290 Exit from PICG configuration <<<<
4970 23:49:20.606586 [RX_INPUT] configuration >>>>>
4971 23:49:20.610050 [RX_INPUT] configuration <<<<<
4972 23:49:20.613730 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4973 23:49:20.620420 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4974 23:49:20.627028 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4975 23:49:20.633410 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4976 23:49:20.640246 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4977 23:49:20.643156 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4978 23:49:20.649889 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4979 23:49:20.653203 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4980 23:49:20.656537 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4981 23:49:20.659874 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4982 23:49:20.666619 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4983 23:49:20.670267 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4984 23:49:20.673570 ===================================
4985 23:49:20.676280 LPDDR4 DRAM CONFIGURATION
4986 23:49:20.680085 ===================================
4987 23:49:20.680187 EX_ROW_EN[0] = 0x0
4988 23:49:20.683249 EX_ROW_EN[1] = 0x0
4989 23:49:20.683341 LP4Y_EN = 0x0
4990 23:49:20.686319 WORK_FSP = 0x0
4991 23:49:20.686486 WL = 0x3
4992 23:49:20.689964 RL = 0x3
4993 23:49:20.690073 BL = 0x2
4994 23:49:20.693058 RPST = 0x0
4995 23:49:20.693169 RD_PRE = 0x0
4996 23:49:20.696510 WR_PRE = 0x1
4997 23:49:20.696618 WR_PST = 0x0
4998 23:49:20.699729 DBI_WR = 0x0
4999 23:49:20.702967 DBI_RD = 0x0
5000 23:49:20.703106 OTF = 0x1
5001 23:49:20.706332 ===================================
5002 23:49:20.709710 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5003 23:49:20.712976 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5004 23:49:20.719528 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 23:49:20.722942 ===================================
5006 23:49:20.726299 LPDDR4 DRAM CONFIGURATION
5007 23:49:20.729560 ===================================
5008 23:49:20.729682 EX_ROW_EN[0] = 0x10
5009 23:49:20.733065 EX_ROW_EN[1] = 0x0
5010 23:49:20.733173 LP4Y_EN = 0x0
5011 23:49:20.736296 WORK_FSP = 0x0
5012 23:49:20.736393 WL = 0x3
5013 23:49:20.739612 RL = 0x3
5014 23:49:20.739690 BL = 0x2
5015 23:49:20.742947 RPST = 0x0
5016 23:49:20.743048 RD_PRE = 0x0
5017 23:49:20.746232 WR_PRE = 0x1
5018 23:49:20.746340 WR_PST = 0x0
5019 23:49:20.749496 DBI_WR = 0x0
5020 23:49:20.749598 DBI_RD = 0x0
5021 23:49:20.752583 OTF = 0x1
5022 23:49:20.756299 ===================================
5023 23:49:20.762464 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5024 23:49:20.765747 nWR fixed to 30
5025 23:49:20.769063 [ModeRegInit_LP4] CH0 RK0
5026 23:49:20.769139 [ModeRegInit_LP4] CH0 RK1
5027 23:49:20.772418 [ModeRegInit_LP4] CH1 RK0
5028 23:49:20.776250 [ModeRegInit_LP4] CH1 RK1
5029 23:49:20.776376 match AC timing 9
5030 23:49:20.782399 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5031 23:49:20.786238 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5032 23:49:20.788963 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5033 23:49:20.795557 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5034 23:49:20.799449 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5035 23:49:20.799539 ==
5036 23:49:20.802710 Dram Type= 6, Freq= 0, CH_0, rank 0
5037 23:49:20.805846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5038 23:49:20.805926 ==
5039 23:49:20.812417 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5040 23:49:20.819486 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5041 23:49:20.822560 [CA 0] Center 37 (6~68) winsize 63
5042 23:49:20.826088 [CA 1] Center 37 (7~68) winsize 62
5043 23:49:20.829334 [CA 2] Center 34 (4~65) winsize 62
5044 23:49:20.832546 [CA 3] Center 33 (3~64) winsize 62
5045 23:49:20.835844 [CA 4] Center 33 (3~64) winsize 62
5046 23:49:20.839557 [CA 5] Center 32 (2~62) winsize 61
5047 23:49:20.839637
5048 23:49:20.842540 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5049 23:49:20.842619
5050 23:49:20.846156 [CATrainingPosCal] consider 1 rank data
5051 23:49:20.849508 u2DelayCellTimex100 = 270/100 ps
5052 23:49:20.852997 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5053 23:49:20.856264 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5054 23:49:20.859683 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5055 23:49:20.862728 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5056 23:49:20.865841 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5057 23:49:20.869617 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5058 23:49:20.869698
5059 23:49:20.876050 CA PerBit enable=1, Macro0, CA PI delay=32
5060 23:49:20.876135
5061 23:49:20.876238 [CBTSetCACLKResult] CA Dly = 32
5062 23:49:20.879544 CS Dly: 5 (0~36)
5063 23:49:20.879623 ==
5064 23:49:20.882586 Dram Type= 6, Freq= 0, CH_0, rank 1
5065 23:49:20.885955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5066 23:49:20.886037 ==
5067 23:49:20.892511 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5068 23:49:20.899236 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5069 23:49:20.902755 [CA 0] Center 37 (6~68) winsize 63
5070 23:49:20.905921 [CA 1] Center 37 (7~68) winsize 62
5071 23:49:20.909322 [CA 2] Center 34 (4~65) winsize 62
5072 23:49:20.912603 [CA 3] Center 34 (4~65) winsize 62
5073 23:49:20.915808 [CA 4] Center 32 (2~63) winsize 62
5074 23:49:20.919015 [CA 5] Center 32 (2~62) winsize 61
5075 23:49:20.919093
5076 23:49:20.922466 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5077 23:49:20.922544
5078 23:49:20.926167 [CATrainingPosCal] consider 2 rank data
5079 23:49:20.929278 u2DelayCellTimex100 = 270/100 ps
5080 23:49:20.932464 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5081 23:49:20.936200 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5082 23:49:20.939506 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5083 23:49:20.942222 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5084 23:49:20.945736 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5085 23:49:20.949138 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5086 23:49:20.949217
5087 23:49:20.955587 CA PerBit enable=1, Macro0, CA PI delay=32
5088 23:49:20.955668
5089 23:49:20.958736 [CBTSetCACLKResult] CA Dly = 32
5090 23:49:20.958821 CS Dly: 5 (0~37)
5091 23:49:20.958898
5092 23:49:20.962146 ----->DramcWriteLeveling(PI) begin...
5093 23:49:20.962252 ==
5094 23:49:20.965431 Dram Type= 6, Freq= 0, CH_0, rank 0
5095 23:49:20.968869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5096 23:49:20.972070 ==
5097 23:49:20.972167 Write leveling (Byte 0): 32 => 32
5098 23:49:20.975492 Write leveling (Byte 1): 29 => 29
5099 23:49:20.978648 DramcWriteLeveling(PI) end<-----
5100 23:49:20.978728
5101 23:49:20.978811 ==
5102 23:49:20.982303 Dram Type= 6, Freq= 0, CH_0, rank 0
5103 23:49:20.988634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5104 23:49:20.988744 ==
5105 23:49:20.991809 [Gating] SW mode calibration
5106 23:49:20.998491 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5107 23:49:21.001766 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5108 23:49:21.008476 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5109 23:49:21.011855 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 23:49:21.015244 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 23:49:21.021978 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 23:49:21.025310 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 23:49:21.028577 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 23:49:21.031818 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5115 23:49:21.038593 0 14 28 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 1)
5116 23:49:21.041830 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5117 23:49:21.044963 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 23:49:21.051603 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 23:49:21.054977 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 23:49:21.058528 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 23:49:21.065194 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 23:49:21.068300 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5123 23:49:21.071649 0 15 28 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
5124 23:49:21.078353 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5125 23:49:21.081715 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 23:49:21.085070 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 23:49:21.091790 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 23:49:21.094972 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 23:49:21.098594 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 23:49:21.105103 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5131 23:49:21.107976 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5132 23:49:21.111735 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 23:49:21.118267 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 23:49:21.121683 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 23:49:21.125067 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 23:49:21.131308 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 23:49:21.134724 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 23:49:21.137951 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 23:49:21.144749 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 23:49:21.148256 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 23:49:21.151587 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 23:49:21.157696 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 23:49:21.161339 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 23:49:21.164326 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 23:49:21.171567 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 23:49:21.174660 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 23:49:21.178035 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5148 23:49:21.184475 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 23:49:21.184558 Total UI for P1: 0, mck2ui 16
5150 23:49:21.191260 best dqsien dly found for B0: ( 1, 2, 28)
5151 23:49:21.191366 Total UI for P1: 0, mck2ui 16
5152 23:49:21.194621 best dqsien dly found for B1: ( 1, 2, 28)
5153 23:49:21.201256 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5154 23:49:21.204643 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5155 23:49:21.204717
5156 23:49:21.207887 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5157 23:49:21.211038 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5158 23:49:21.214088 [Gating] SW calibration Done
5159 23:49:21.214164 ==
5160 23:49:21.217480 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 23:49:21.220631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 23:49:21.220703 ==
5163 23:49:21.224285 RX Vref Scan: 0
5164 23:49:21.224409
5165 23:49:21.224472 RX Vref 0 -> 0, step: 1
5166 23:49:21.224530
5167 23:49:21.227719 RX Delay -80 -> 252, step: 8
5168 23:49:21.230984 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5169 23:49:21.237303 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5170 23:49:21.240636 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5171 23:49:21.243885 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5172 23:49:21.247268 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5173 23:49:21.250751 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5174 23:49:21.253987 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5175 23:49:21.260717 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5176 23:49:21.264133 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5177 23:49:21.267509 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5178 23:49:21.270714 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5179 23:49:21.273769 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5180 23:49:21.277461 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5181 23:49:21.284101 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5182 23:49:21.287249 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5183 23:49:21.290711 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5184 23:49:21.290793 ==
5185 23:49:21.294053 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 23:49:21.297541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 23:49:21.297618 ==
5188 23:49:21.300270 DQS Delay:
5189 23:49:21.300362 DQS0 = 0, DQS1 = 0
5190 23:49:21.300442 DQM Delay:
5191 23:49:21.303887 DQM0 = 105, DQM1 = 93
5192 23:49:21.303968 DQ Delay:
5193 23:49:21.307074 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5194 23:49:21.310341 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5195 23:49:21.313771 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =91
5196 23:49:21.317113 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5197 23:49:21.317220
5198 23:49:21.317316
5199 23:49:21.320246 ==
5200 23:49:21.323596 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 23:49:21.327002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 23:49:21.327084 ==
5203 23:49:21.327148
5204 23:49:21.327207
5205 23:49:21.330337 TX Vref Scan disable
5206 23:49:21.330417 == TX Byte 0 ==
5207 23:49:21.336748 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5208 23:49:21.340485 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5209 23:49:21.340566 == TX Byte 1 ==
5210 23:49:21.347119 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5211 23:49:21.350067 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5212 23:49:21.350169 ==
5213 23:49:21.353501 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 23:49:21.356890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 23:49:21.356964 ==
5216 23:49:21.357026
5217 23:49:21.357083
5218 23:49:21.360451 TX Vref Scan disable
5219 23:49:21.363476 == TX Byte 0 ==
5220 23:49:21.366973 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5221 23:49:21.370348 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5222 23:49:21.373719 == TX Byte 1 ==
5223 23:49:21.376910 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5224 23:49:21.380225 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5225 23:49:21.380294
5226 23:49:21.383398 [DATLAT]
5227 23:49:21.383465 Freq=933, CH0 RK0
5228 23:49:21.383525
5229 23:49:21.386714 DATLAT Default: 0xd
5230 23:49:21.386794 0, 0xFFFF, sum = 0
5231 23:49:21.389910 1, 0xFFFF, sum = 0
5232 23:49:21.389996 2, 0xFFFF, sum = 0
5233 23:49:21.393213 3, 0xFFFF, sum = 0
5234 23:49:21.393298 4, 0xFFFF, sum = 0
5235 23:49:21.397103 5, 0xFFFF, sum = 0
5236 23:49:21.397187 6, 0xFFFF, sum = 0
5237 23:49:21.400167 7, 0xFFFF, sum = 0
5238 23:49:21.400270 8, 0xFFFF, sum = 0
5239 23:49:21.403670 9, 0xFFFF, sum = 0
5240 23:49:21.403758 10, 0x0, sum = 1
5241 23:49:21.406876 11, 0x0, sum = 2
5242 23:49:21.406952 12, 0x0, sum = 3
5243 23:49:21.410329 13, 0x0, sum = 4
5244 23:49:21.410412 best_step = 11
5245 23:49:21.410473
5246 23:49:21.410534 ==
5247 23:49:21.413669 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 23:49:21.416930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 23:49:21.420242 ==
5250 23:49:21.420317 RX Vref Scan: 1
5251 23:49:21.420427
5252 23:49:21.423595 RX Vref 0 -> 0, step: 1
5253 23:49:21.423668
5254 23:49:21.427026 RX Delay -53 -> 252, step: 4
5255 23:49:21.427099
5256 23:49:21.430344 Set Vref, RX VrefLevel [Byte0]: 57
5257 23:49:21.430415 [Byte1]: 48
5258 23:49:21.434982
5259 23:49:21.435064 Final RX Vref Byte 0 = 57 to rank0
5260 23:49:21.438455 Final RX Vref Byte 1 = 48 to rank0
5261 23:49:21.442064 Final RX Vref Byte 0 = 57 to rank1
5262 23:49:21.444919 Final RX Vref Byte 1 = 48 to rank1==
5263 23:49:21.448873 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 23:49:21.455096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 23:49:21.455179 ==
5266 23:49:21.455245 DQS Delay:
5267 23:49:21.455305 DQS0 = 0, DQS1 = 0
5268 23:49:21.458207 DQM Delay:
5269 23:49:21.458285 DQM0 = 105, DQM1 = 94
5270 23:49:21.462005 DQ Delay:
5271 23:49:21.465235 DQ0 =104, DQ1 =104, DQ2 =104, DQ3 =102
5272 23:49:21.468563 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5273 23:49:21.472009 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =88
5274 23:49:21.474697 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5275 23:49:21.474778
5276 23:49:21.474841
5277 23:49:21.481490 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5278 23:49:21.484748 CH0 RK0: MR19=505, MR18=322A
5279 23:49:21.491757 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5280 23:49:21.491877
5281 23:49:21.494859 ----->DramcWriteLeveling(PI) begin...
5282 23:49:21.494958 ==
5283 23:49:21.498266 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 23:49:21.501736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 23:49:21.501827 ==
5286 23:49:21.505178 Write leveling (Byte 0): 31 => 31
5287 23:49:21.508538 Write leveling (Byte 1): 31 => 31
5288 23:49:21.511670 DramcWriteLeveling(PI) end<-----
5289 23:49:21.511753
5290 23:49:21.511819 ==
5291 23:49:21.514716 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 23:49:21.521562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 23:49:21.521657 ==
5294 23:49:21.521724 [Gating] SW mode calibration
5295 23:49:21.531567 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5296 23:49:21.534961 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5297 23:49:21.538356 0 14 0 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
5298 23:49:21.544987 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 23:49:21.548695 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 23:49:21.551386 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 23:49:21.558319 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 23:49:21.561546 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 23:49:21.564846 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 23:49:21.571284 0 14 28 | B1->B0 | 2d2d 2c2c | 0 0 | (0 1) (0 0)
5305 23:49:21.575030 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5306 23:49:21.578203 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 23:49:21.584936 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 23:49:21.588438 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 23:49:21.591146 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 23:49:21.598122 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 23:49:21.601211 0 15 24 | B1->B0 | 2828 2626 | 0 1 | (0 0) (0 0)
5312 23:49:21.604529 0 15 28 | B1->B0 | 4040 3838 | 0 1 | (0 0) (0 0)
5313 23:49:21.611376 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 23:49:21.614661 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 23:49:21.618201 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 23:49:21.624616 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 23:49:21.627779 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 23:49:21.631418 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 23:49:21.638078 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 23:49:21.640830 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5321 23:49:21.644229 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 23:49:21.650860 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 23:49:21.654236 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 23:49:21.657651 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 23:49:21.661031 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 23:49:21.667805 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 23:49:21.671022 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 23:49:21.674150 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 23:49:21.681396 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 23:49:21.684275 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 23:49:21.687342 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 23:49:21.694189 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 23:49:21.697786 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 23:49:21.701022 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 23:49:21.707408 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 23:49:21.710427 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5337 23:49:21.713772 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 23:49:21.717085 Total UI for P1: 0, mck2ui 16
5339 23:49:21.720536 best dqsien dly found for B0: ( 1, 2, 28)
5340 23:49:21.723861 Total UI for P1: 0, mck2ui 16
5341 23:49:21.727312 best dqsien dly found for B1: ( 1, 2, 28)
5342 23:49:21.730698 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5343 23:49:21.733977 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5344 23:49:21.737288
5345 23:49:21.740529 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5346 23:49:21.743529 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5347 23:49:21.747015 [Gating] SW calibration Done
5348 23:49:21.747164 ==
5349 23:49:21.750486 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 23:49:21.753513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 23:49:21.753657 ==
5352 23:49:21.753771 RX Vref Scan: 0
5353 23:49:21.753887
5354 23:49:21.756929 RX Vref 0 -> 0, step: 1
5355 23:49:21.757024
5356 23:49:21.760331 RX Delay -80 -> 252, step: 8
5357 23:49:21.763762 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5358 23:49:21.767175 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5359 23:49:21.773320 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5360 23:49:21.776868 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5361 23:49:21.780229 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5362 23:49:21.783512 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5363 23:49:21.787031 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5364 23:49:21.789982 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5365 23:49:21.796449 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5366 23:49:21.800345 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5367 23:49:21.803552 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5368 23:49:21.806491 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5369 23:49:21.809760 iDelay=208, Bit 12, Center 99 (16 ~ 183) 168
5370 23:49:21.813381 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5371 23:49:21.819780 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5372 23:49:21.822968 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5373 23:49:21.823076 ==
5374 23:49:21.826783 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 23:49:21.829854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 23:49:21.829944 ==
5377 23:49:21.833064 DQS Delay:
5378 23:49:21.833152 DQS0 = 0, DQS1 = 0
5379 23:49:21.833239 DQM Delay:
5380 23:49:21.836452 DQM0 = 104, DQM1 = 95
5381 23:49:21.836539 DQ Delay:
5382 23:49:21.839930 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5383 23:49:21.843381 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =111
5384 23:49:21.846807 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5385 23:49:21.849564 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =103
5386 23:49:21.853405
5387 23:49:21.853484
5388 23:49:21.853560 ==
5389 23:49:21.856532 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 23:49:21.860038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 23:49:21.860128 ==
5392 23:49:21.860203
5393 23:49:21.860265
5394 23:49:21.862966 TX Vref Scan disable
5395 23:49:21.863046 == TX Byte 0 ==
5396 23:49:21.869807 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5397 23:49:21.873144 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5398 23:49:21.873226 == TX Byte 1 ==
5399 23:49:21.879384 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5400 23:49:21.882842 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5401 23:49:21.882929 ==
5402 23:49:21.886326 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 23:49:21.889419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 23:49:21.889501 ==
5405 23:49:21.889577
5406 23:49:21.889638
5407 23:49:21.892895 TX Vref Scan disable
5408 23:49:21.896213 == TX Byte 0 ==
5409 23:49:21.899703 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5410 23:49:21.903091 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5411 23:49:21.905974 == TX Byte 1 ==
5412 23:49:21.909264 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5413 23:49:21.912737 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5414 23:49:21.912819
5415 23:49:21.915906 [DATLAT]
5416 23:49:21.915987 Freq=933, CH0 RK1
5417 23:49:21.916100
5418 23:49:21.919595 DATLAT Default: 0xb
5419 23:49:21.919687 0, 0xFFFF, sum = 0
5420 23:49:21.922949 1, 0xFFFF, sum = 0
5421 23:49:21.923043 2, 0xFFFF, sum = 0
5422 23:49:21.926318 3, 0xFFFF, sum = 0
5423 23:49:21.926412 4, 0xFFFF, sum = 0
5424 23:49:21.929653 5, 0xFFFF, sum = 0
5425 23:49:21.929732 6, 0xFFFF, sum = 0
5426 23:49:21.932408 7, 0xFFFF, sum = 0
5427 23:49:21.932485 8, 0xFFFF, sum = 0
5428 23:49:21.935817 9, 0xFFFF, sum = 0
5429 23:49:21.935894 10, 0x0, sum = 1
5430 23:49:21.939514 11, 0x0, sum = 2
5431 23:49:21.939599 12, 0x0, sum = 3
5432 23:49:21.942571 13, 0x0, sum = 4
5433 23:49:21.942655 best_step = 11
5434 23:49:21.942733
5435 23:49:21.942795 ==
5436 23:49:21.946096 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 23:49:21.953035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 23:49:21.953124 ==
5439 23:49:21.953192 RX Vref Scan: 0
5440 23:49:21.953265
5441 23:49:21.956030 RX Vref 0 -> 0, step: 1
5442 23:49:21.956106
5443 23:49:21.959307 RX Delay -45 -> 252, step: 4
5444 23:49:21.962552 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5445 23:49:21.965796 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5446 23:49:21.972779 iDelay=199, Bit 2, Center 100 (11 ~ 190) 180
5447 23:49:21.975869 iDelay=199, Bit 3, Center 100 (11 ~ 190) 180
5448 23:49:21.979535 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5449 23:49:21.982681 iDelay=199, Bit 5, Center 98 (7 ~ 190) 184
5450 23:49:21.985554 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5451 23:49:21.992443 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5452 23:49:21.995457 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5453 23:49:21.998869 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5454 23:49:22.002297 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5455 23:49:22.005731 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5456 23:49:22.009274 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5457 23:49:22.016177 iDelay=199, Bit 13, Center 96 (11 ~ 182) 172
5458 23:49:22.018735 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5459 23:49:22.022194 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5460 23:49:22.022269 ==
5461 23:49:22.025422 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 23:49:22.029170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 23:49:22.032161 ==
5464 23:49:22.032236 DQS Delay:
5465 23:49:22.032298 DQS0 = 0, DQS1 = 0
5466 23:49:22.035214 DQM Delay:
5467 23:49:22.035334 DQM0 = 104, DQM1 = 93
5468 23:49:22.038651 DQ Delay:
5469 23:49:22.042243 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =100
5470 23:49:22.045561 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5471 23:49:22.048928 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =86
5472 23:49:22.052178 DQ12 =100, DQ13 =96, DQ14 =102, DQ15 =102
5473 23:49:22.052279
5474 23:49:22.052409
5475 23:49:22.058939 [DQSOSCAuto] RK1, (LSB)MR18= 0x2902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5476 23:49:22.062793 CH0 RK1: MR19=505, MR18=2902
5477 23:49:22.068602 CH0_RK1: MR19=0x505, MR18=0x2902, DQSOSC=408, MR23=63, INC=65, DEC=43
5478 23:49:22.071861 [RxdqsGatingPostProcess] freq 933
5479 23:49:22.075099 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5480 23:49:22.078613 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 23:49:22.081896 best DQS1 dly(2T, 0.5T) = (0, 10)
5482 23:49:22.085101 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 23:49:22.088597 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5484 23:49:22.091683 best DQS0 dly(2T, 0.5T) = (0, 10)
5485 23:49:22.095490 best DQS1 dly(2T, 0.5T) = (0, 10)
5486 23:49:22.098685 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5487 23:49:22.101957 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5488 23:49:22.105370 Pre-setting of DQS Precalculation
5489 23:49:22.108901 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5490 23:49:22.111690 ==
5491 23:49:22.111771 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 23:49:22.118762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 23:49:22.118843 ==
5494 23:49:22.121966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5495 23:49:22.128076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5496 23:49:22.132261 [CA 0] Center 36 (6~67) winsize 62
5497 23:49:22.135707 [CA 1] Center 36 (6~67) winsize 62
5498 23:49:22.138911 [CA 2] Center 34 (4~65) winsize 62
5499 23:49:22.142018 [CA 3] Center 34 (4~65) winsize 62
5500 23:49:22.145323 [CA 4] Center 34 (4~64) winsize 61
5501 23:49:22.148840 [CA 5] Center 33 (3~64) winsize 62
5502 23:49:22.148915
5503 23:49:22.151632 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5504 23:49:22.151707
5505 23:49:22.154991 [CATrainingPosCal] consider 1 rank data
5506 23:49:22.158523 u2DelayCellTimex100 = 270/100 ps
5507 23:49:22.161917 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5508 23:49:22.165106 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5509 23:49:22.171928 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5510 23:49:22.175260 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5511 23:49:22.178533 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5512 23:49:22.181891 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5513 23:49:22.181961
5514 23:49:22.185332 CA PerBit enable=1, Macro0, CA PI delay=33
5515 23:49:22.185400
5516 23:49:22.188787 [CBTSetCACLKResult] CA Dly = 33
5517 23:49:22.188868 CS Dly: 7 (0~38)
5518 23:49:22.191539 ==
5519 23:49:22.191607 Dram Type= 6, Freq= 0, CH_1, rank 1
5520 23:49:22.198727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 23:49:22.198804 ==
5522 23:49:22.201886 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5523 23:49:22.208604 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5524 23:49:22.212102 [CA 0] Center 36 (6~67) winsize 62
5525 23:49:22.215113 [CA 1] Center 37 (7~68) winsize 62
5526 23:49:22.218841 [CA 2] Center 35 (5~66) winsize 62
5527 23:49:22.222410 [CA 3] Center 34 (4~65) winsize 62
5528 23:49:22.225526 [CA 4] Center 34 (4~65) winsize 62
5529 23:49:22.228961 [CA 5] Center 33 (3~64) winsize 62
5530 23:49:22.229034
5531 23:49:22.232224 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5532 23:49:22.232296
5533 23:49:22.235003 [CATrainingPosCal] consider 2 rank data
5534 23:49:22.238345 u2DelayCellTimex100 = 270/100 ps
5535 23:49:22.241754 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5536 23:49:22.245042 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5537 23:49:22.251687 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5538 23:49:22.254946 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5539 23:49:22.258710 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5540 23:49:22.261800 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5541 23:49:22.261875
5542 23:49:22.264975 CA PerBit enable=1, Macro0, CA PI delay=33
5543 23:49:22.265052
5544 23:49:22.268410 [CBTSetCACLKResult] CA Dly = 33
5545 23:49:22.268480 CS Dly: 8 (0~40)
5546 23:49:22.268553
5547 23:49:22.274974 ----->DramcWriteLeveling(PI) begin...
5548 23:49:22.275055 ==
5549 23:49:22.278214 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 23:49:22.281811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 23:49:22.281891 ==
5552 23:49:22.284799 Write leveling (Byte 0): 27 => 27
5553 23:49:22.288209 Write leveling (Byte 1): 27 => 27
5554 23:49:22.291989 DramcWriteLeveling(PI) end<-----
5555 23:49:22.292094
5556 23:49:22.292186 ==
5557 23:49:22.294652 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 23:49:22.298090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 23:49:22.298177 ==
5560 23:49:22.301531 [Gating] SW mode calibration
5561 23:49:22.308172 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5562 23:49:22.314573 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5563 23:49:22.318628 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 23:49:22.321686 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 23:49:22.327937 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 23:49:22.331790 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 23:49:22.334758 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 23:49:22.338061 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 23:49:22.344698 0 14 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5570 23:49:22.348108 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (1 0)
5571 23:49:22.351594 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 23:49:22.358440 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 23:49:22.361274 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 23:49:22.364535 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 23:49:22.371911 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 23:49:22.374818 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 23:49:22.377868 0 15 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5578 23:49:22.384760 0 15 28 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
5579 23:49:22.388066 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 23:49:22.391365 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 23:49:22.397736 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 23:49:22.401358 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 23:49:22.404361 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 23:49:22.410954 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 23:49:22.414992 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5586 23:49:22.418214 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 23:49:22.425012 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 23:49:22.427721 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 23:49:22.431131 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 23:49:22.438034 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 23:49:22.441015 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 23:49:22.444383 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 23:49:22.451154 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 23:49:22.454553 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 23:49:22.457406 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 23:49:22.464847 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 23:49:22.467605 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 23:49:22.470923 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 23:49:22.477749 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 23:49:22.481072 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 23:49:22.484370 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5602 23:49:22.487648 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5603 23:49:22.490745 Total UI for P1: 0, mck2ui 16
5604 23:49:22.494530 best dqsien dly found for B0: ( 1, 2, 24)
5605 23:49:22.500651 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 23:49:22.503998 Total UI for P1: 0, mck2ui 16
5607 23:49:22.507193 best dqsien dly found for B1: ( 1, 2, 26)
5608 23:49:22.511088 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5609 23:49:22.514308 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5610 23:49:22.514425
5611 23:49:22.517403 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5612 23:49:22.520959 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5613 23:49:22.524082 [Gating] SW calibration Done
5614 23:49:22.524179 ==
5615 23:49:22.527416 Dram Type= 6, Freq= 0, CH_1, rank 0
5616 23:49:22.530690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5617 23:49:22.530768 ==
5618 23:49:22.534167 RX Vref Scan: 0
5619 23:49:22.534272
5620 23:49:22.534369 RX Vref 0 -> 0, step: 1
5621 23:49:22.537577
5622 23:49:22.537654 RX Delay -80 -> 252, step: 8
5623 23:49:22.544485 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5624 23:49:22.547693 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5625 23:49:22.550725 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5626 23:49:22.554466 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5627 23:49:22.557288 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5628 23:49:22.560690 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5629 23:49:22.567398 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5630 23:49:22.570976 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5631 23:49:22.574269 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5632 23:49:22.577551 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5633 23:49:22.580955 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5634 23:49:22.583652 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5635 23:49:22.590383 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5636 23:49:22.594280 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5637 23:49:22.597520 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5638 23:49:22.600701 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5639 23:49:22.600777 ==
5640 23:49:22.603855 Dram Type= 6, Freq= 0, CH_1, rank 0
5641 23:49:22.610501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5642 23:49:22.610586 ==
5643 23:49:22.610661 DQS Delay:
5644 23:49:22.610723 DQS0 = 0, DQS1 = 0
5645 23:49:22.613714 DQM Delay:
5646 23:49:22.613803 DQM0 = 103, DQM1 = 99
5647 23:49:22.617254 DQ Delay:
5648 23:49:22.620611 DQ0 =111, DQ1 =95, DQ2 =91, DQ3 =99
5649 23:49:22.623940 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5650 23:49:22.627190 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5651 23:49:22.630209 DQ12 =107, DQ13 =107, DQ14 =107, DQ15 =107
5652 23:49:22.630330
5653 23:49:22.630411
5654 23:49:22.630525 ==
5655 23:49:22.633832 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 23:49:22.637230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 23:49:22.637333 ==
5658 23:49:22.637444
5659 23:49:22.637519
5660 23:49:22.640706 TX Vref Scan disable
5661 23:49:22.643599 == TX Byte 0 ==
5662 23:49:22.647326 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5663 23:49:22.650427 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5664 23:49:22.653694 == TX Byte 1 ==
5665 23:49:22.657025 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5666 23:49:22.660263 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5667 23:49:22.660405 ==
5668 23:49:22.663492 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 23:49:22.667292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 23:49:22.670698 ==
5671 23:49:22.670804
5672 23:49:22.670885
5673 23:49:22.670977 TX Vref Scan disable
5674 23:49:22.674135 == TX Byte 0 ==
5675 23:49:22.676928 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5676 23:49:22.683635 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5677 23:49:22.683753 == TX Byte 1 ==
5678 23:49:22.687139 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5679 23:49:22.693665 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5680 23:49:22.693769
5681 23:49:22.693869 [DATLAT]
5682 23:49:22.693945 Freq=933, CH1 RK0
5683 23:49:22.694038
5684 23:49:22.696995 DATLAT Default: 0xd
5685 23:49:22.697096 0, 0xFFFF, sum = 0
5686 23:49:22.700271 1, 0xFFFF, sum = 0
5687 23:49:22.700416 2, 0xFFFF, sum = 0
5688 23:49:22.703653 3, 0xFFFF, sum = 0
5689 23:49:22.706926 4, 0xFFFF, sum = 0
5690 23:49:22.707027 5, 0xFFFF, sum = 0
5691 23:49:22.710120 6, 0xFFFF, sum = 0
5692 23:49:22.710220 7, 0xFFFF, sum = 0
5693 23:49:22.713653 8, 0xFFFF, sum = 0
5694 23:49:22.713754 9, 0xFFFF, sum = 0
5695 23:49:22.717231 10, 0x0, sum = 1
5696 23:49:22.717377 11, 0x0, sum = 2
5697 23:49:22.720655 12, 0x0, sum = 3
5698 23:49:22.720741 13, 0x0, sum = 4
5699 23:49:22.720809 best_step = 11
5700 23:49:22.720871
5701 23:49:22.723972 ==
5702 23:49:22.724058 Dram Type= 6, Freq= 0, CH_1, rank 0
5703 23:49:22.730280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5704 23:49:22.730364 ==
5705 23:49:22.730431 RX Vref Scan: 1
5706 23:49:22.730492
5707 23:49:22.733734 RX Vref 0 -> 0, step: 1
5708 23:49:22.733819
5709 23:49:22.737139 RX Delay -45 -> 252, step: 4
5710 23:49:22.737224
5711 23:49:22.740528 Set Vref, RX VrefLevel [Byte0]: 54
5712 23:49:22.743231 [Byte1]: 55
5713 23:49:22.743316
5714 23:49:22.747271 Final RX Vref Byte 0 = 54 to rank0
5715 23:49:22.750130 Final RX Vref Byte 1 = 55 to rank0
5716 23:49:22.753556 Final RX Vref Byte 0 = 54 to rank1
5717 23:49:22.757001 Final RX Vref Byte 1 = 55 to rank1==
5718 23:49:22.760280 Dram Type= 6, Freq= 0, CH_1, rank 0
5719 23:49:22.763748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5720 23:49:22.766375 ==
5721 23:49:22.766470 DQS Delay:
5722 23:49:22.766550 DQS0 = 0, DQS1 = 0
5723 23:49:22.769971 DQM Delay:
5724 23:49:22.770058 DQM0 = 103, DQM1 = 100
5725 23:49:22.773117 DQ Delay:
5726 23:49:22.776436 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5727 23:49:22.780107 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5728 23:49:22.783216 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =94
5729 23:49:22.786192 DQ12 =104, DQ13 =108, DQ14 =110, DQ15 =108
5730 23:49:22.786427
5731 23:49:22.786578
5732 23:49:22.792817 [DQSOSCAuto] RK0, (LSB)MR18= 0x172f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5733 23:49:22.796273 CH1 RK0: MR19=505, MR18=172F
5734 23:49:22.803189 CH1_RK0: MR19=0x505, MR18=0x172F, DQSOSC=407, MR23=63, INC=65, DEC=43
5735 23:49:22.803317
5736 23:49:22.806548 ----->DramcWriteLeveling(PI) begin...
5737 23:49:22.806638 ==
5738 23:49:22.809899 Dram Type= 6, Freq= 0, CH_1, rank 1
5739 23:49:22.813213 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5740 23:49:22.813308 ==
5741 23:49:22.816551 Write leveling (Byte 0): 28 => 28
5742 23:49:22.819674 Write leveling (Byte 1): 28 => 28
5743 23:49:22.822733 DramcWriteLeveling(PI) end<-----
5744 23:49:22.822808
5745 23:49:22.822880 ==
5746 23:49:22.826473 Dram Type= 6, Freq= 0, CH_1, rank 1
5747 23:49:22.829852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5748 23:49:22.833067 ==
5749 23:49:22.833151 [Gating] SW mode calibration
5750 23:49:22.842763 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5751 23:49:22.846093 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5752 23:49:22.849581 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 23:49:22.856359 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 23:49:22.859214 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 23:49:22.862500 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 23:49:22.869270 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 23:49:22.872669 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 23:49:22.876446 0 14 24 | B1->B0 | 2f2f 3030 | 0 1 | (0 0) (1 0)
5759 23:49:22.882684 0 14 28 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 0)
5760 23:49:22.886192 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 23:49:22.889680 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 23:49:22.895826 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 23:49:22.899731 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 23:49:22.902890 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 23:49:22.909500 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 23:49:22.912472 0 15 24 | B1->B0 | 3737 2828 | 0 0 | (0 0) (0 0)
5767 23:49:22.915946 0 15 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5768 23:49:22.922904 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 23:49:22.926175 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 23:49:22.929363 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 23:49:22.932479 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 23:49:22.939214 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 23:49:22.942473 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5774 23:49:22.945763 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5775 23:49:22.952616 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5776 23:49:22.955763 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 23:49:22.959182 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 23:49:22.965904 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 23:49:22.969223 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 23:49:22.972466 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 23:49:22.979299 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 23:49:22.982609 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 23:49:22.985937 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 23:49:22.992487 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 23:49:22.995887 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 23:49:22.998696 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 23:49:23.005558 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 23:49:23.009034 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 23:49:23.012465 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 23:49:23.018853 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5791 23:49:23.038717 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5792 23:49:23.038918 Total UI for P1: 0, mck2ui 16
5793 23:49:23.039066 best dqsien dly found for B0: ( 1, 2, 24)
5794 23:49:23.039214 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 23:49:23.039336 Total UI for P1: 0, mck2ui 16
5796 23:49:23.039423 best dqsien dly found for B1: ( 1, 2, 26)
5797 23:49:23.041768 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5798 23:49:23.045626 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5799 23:49:23.045713
5800 23:49:23.052107 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5801 23:49:23.055668 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5802 23:49:23.055795 [Gating] SW calibration Done
5803 23:49:23.059066 ==
5804 23:49:23.062195 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 23:49:23.065065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 23:49:23.065152 ==
5807 23:49:23.065225 RX Vref Scan: 0
5808 23:49:23.065286
5809 23:49:23.068644 RX Vref 0 -> 0, step: 1
5810 23:49:23.068718
5811 23:49:23.071888 RX Delay -80 -> 252, step: 8
5812 23:49:23.075241 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5813 23:49:23.078583 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5814 23:49:23.081971 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5815 23:49:23.088831 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5816 23:49:23.091588 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5817 23:49:23.094882 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5818 23:49:23.098236 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5819 23:49:23.101638 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5820 23:49:23.105458 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5821 23:49:23.108811 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5822 23:49:23.115540 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5823 23:49:23.118772 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5824 23:49:23.121838 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5825 23:49:23.125122 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5826 23:49:23.128605 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5827 23:49:23.135421 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5828 23:49:23.135580 ==
5829 23:49:23.138812 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 23:49:23.142240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 23:49:23.142344 ==
5832 23:49:23.142433 DQS Delay:
5833 23:49:23.145519 DQS0 = 0, DQS1 = 0
5834 23:49:23.145596 DQM Delay:
5835 23:49:23.148723 DQM0 = 101, DQM1 = 99
5836 23:49:23.148814 DQ Delay:
5837 23:49:23.151845 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5838 23:49:23.155044 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5839 23:49:23.158635 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5840 23:49:23.161555 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5841 23:49:23.161635
5842 23:49:23.161701
5843 23:49:23.161782 ==
5844 23:49:23.165127 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 23:49:23.171697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 23:49:23.171778 ==
5847 23:49:23.171894
5848 23:49:23.171958
5849 23:49:23.172017 TX Vref Scan disable
5850 23:49:23.175302 == TX Byte 0 ==
5851 23:49:23.178312 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5852 23:49:23.182177 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5853 23:49:23.185508 == TX Byte 1 ==
5854 23:49:23.188292 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5855 23:49:23.191691 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5856 23:49:23.195139 ==
5857 23:49:23.198549 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 23:49:23.201905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 23:49:23.201992 ==
5860 23:49:23.202057
5861 23:49:23.202118
5862 23:49:23.205269 TX Vref Scan disable
5863 23:49:23.205348 == TX Byte 0 ==
5864 23:49:23.212072 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5865 23:49:23.215491 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5866 23:49:23.215575 == TX Byte 1 ==
5867 23:49:23.221647 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5868 23:49:23.224918 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5869 23:49:23.225023
5870 23:49:23.225090 [DATLAT]
5871 23:49:23.228262 Freq=933, CH1 RK1
5872 23:49:23.228336
5873 23:49:23.228434 DATLAT Default: 0xb
5874 23:49:23.231803 0, 0xFFFF, sum = 0
5875 23:49:23.231933 1, 0xFFFF, sum = 0
5876 23:49:23.235045 2, 0xFFFF, sum = 0
5877 23:49:23.235133 3, 0xFFFF, sum = 0
5878 23:49:23.238239 4, 0xFFFF, sum = 0
5879 23:49:23.238312 5, 0xFFFF, sum = 0
5880 23:49:23.242076 6, 0xFFFF, sum = 0
5881 23:49:23.242168 7, 0xFFFF, sum = 0
5882 23:49:23.244810 8, 0xFFFF, sum = 0
5883 23:49:23.244898 9, 0xFFFF, sum = 0
5884 23:49:23.248162 10, 0x0, sum = 1
5885 23:49:23.248241 11, 0x0, sum = 2
5886 23:49:23.251668 12, 0x0, sum = 3
5887 23:49:23.251798 13, 0x0, sum = 4
5888 23:49:23.254992 best_step = 11
5889 23:49:23.255126
5890 23:49:23.255258 ==
5891 23:49:23.258447 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 23:49:23.261891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 23:49:23.262010 ==
5894 23:49:23.265395 RX Vref Scan: 0
5895 23:49:23.265477
5896 23:49:23.265580 RX Vref 0 -> 0, step: 1
5897 23:49:23.265651
5898 23:49:23.268476 RX Delay -45 -> 252, step: 4
5899 23:49:23.275216 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5900 23:49:23.278856 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5901 23:49:23.281737 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5902 23:49:23.285269 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5903 23:49:23.288911 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5904 23:49:23.295607 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5905 23:49:23.298896 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5906 23:49:23.302260 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5907 23:49:23.305476 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5908 23:49:23.308294 iDelay=203, Bit 9, Center 86 (-1 ~ 174) 176
5909 23:49:23.314976 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5910 23:49:23.318351 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5911 23:49:23.321595 iDelay=203, Bit 12, Center 106 (19 ~ 194) 176
5912 23:49:23.324918 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5913 23:49:23.328271 iDelay=203, Bit 14, Center 108 (27 ~ 190) 164
5914 23:49:23.335007 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5915 23:49:23.335098 ==
5916 23:49:23.338248 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 23:49:23.341912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 23:49:23.342010 ==
5919 23:49:23.342092 DQS Delay:
5920 23:49:23.345102 DQS0 = 0, DQS1 = 0
5921 23:49:23.345184 DQM Delay:
5922 23:49:23.348230 DQM0 = 105, DQM1 = 100
5923 23:49:23.348318 DQ Delay:
5924 23:49:23.351651 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5925 23:49:23.355134 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5926 23:49:23.358632 DQ8 =92, DQ9 =86, DQ10 =100, DQ11 =94
5927 23:49:23.361740 DQ12 =106, DQ13 =108, DQ14 =108, DQ15 =110
5928 23:49:23.361860
5929 23:49:23.361960
5930 23:49:23.371546 [DQSOSCAuto] RK1, (LSB)MR18= 0x3003, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 406 ps
5931 23:49:23.374781 CH1 RK1: MR19=505, MR18=3003
5932 23:49:23.378127 CH1_RK1: MR19=0x505, MR18=0x3003, DQSOSC=406, MR23=63, INC=65, DEC=43
5933 23:49:23.382000 [RxdqsGatingPostProcess] freq 933
5934 23:49:23.388610 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5935 23:49:23.391785 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 23:49:23.394949 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 23:49:23.397946 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 23:49:23.401246 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 23:49:23.405058 best DQS0 dly(2T, 0.5T) = (0, 10)
5940 23:49:23.408050 best DQS1 dly(2T, 0.5T) = (0, 10)
5941 23:49:23.411514 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5942 23:49:23.414613 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5943 23:49:23.418030 Pre-setting of DQS Precalculation
5944 23:49:23.421285 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5945 23:49:23.428182 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5946 23:49:23.434274 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5947 23:49:23.437537
5948 23:49:23.437706
5949 23:49:23.437806 [Calibration Summary] 1866 Mbps
5950 23:49:23.440949 CH 0, Rank 0
5951 23:49:23.441097 SW Impedance : PASS
5952 23:49:23.444255 DUTY Scan : NO K
5953 23:49:23.447590 ZQ Calibration : PASS
5954 23:49:23.447740 Jitter Meter : NO K
5955 23:49:23.451083 CBT Training : PASS
5956 23:49:23.454475 Write leveling : PASS
5957 23:49:23.454584 RX DQS gating : PASS
5958 23:49:23.457643 RX DQ/DQS(RDDQC) : PASS
5959 23:49:23.461491 TX DQ/DQS : PASS
5960 23:49:23.461579 RX DATLAT : PASS
5961 23:49:23.464697 RX DQ/DQS(Engine): PASS
5962 23:49:23.467574 TX OE : NO K
5963 23:49:23.467655 All Pass.
5964 23:49:23.467756
5965 23:49:23.467854 CH 0, Rank 1
5966 23:49:23.470959 SW Impedance : PASS
5967 23:49:23.474347 DUTY Scan : NO K
5968 23:49:23.474431 ZQ Calibration : PASS
5969 23:49:23.477747 Jitter Meter : NO K
5970 23:49:23.481180 CBT Training : PASS
5971 23:49:23.481281 Write leveling : PASS
5972 23:49:23.484501 RX DQS gating : PASS
5973 23:49:23.484603 RX DQ/DQS(RDDQC) : PASS
5974 23:49:23.487692 TX DQ/DQS : PASS
5975 23:49:23.490852 RX DATLAT : PASS
5976 23:49:23.490959 RX DQ/DQS(Engine): PASS
5977 23:49:23.494255 TX OE : NO K
5978 23:49:23.494329 All Pass.
5979 23:49:23.494394
5980 23:49:23.497603 CH 1, Rank 0
5981 23:49:23.497681 SW Impedance : PASS
5982 23:49:23.500802 DUTY Scan : NO K
5983 23:49:23.503935 ZQ Calibration : PASS
5984 23:49:23.504034 Jitter Meter : NO K
5985 23:49:23.507374 CBT Training : PASS
5986 23:49:23.510669 Write leveling : PASS
5987 23:49:23.510767 RX DQS gating : PASS
5988 23:49:23.514561 RX DQ/DQS(RDDQC) : PASS
5989 23:49:23.517489 TX DQ/DQS : PASS
5990 23:49:23.517563 RX DATLAT : PASS
5991 23:49:23.520655 RX DQ/DQS(Engine): PASS
5992 23:49:23.524473 TX OE : NO K
5993 23:49:23.524553 All Pass.
5994 23:49:23.524626
5995 23:49:23.524688 CH 1, Rank 1
5996 23:49:23.527756 SW Impedance : PASS
5997 23:49:23.530750 DUTY Scan : NO K
5998 23:49:23.530863 ZQ Calibration : PASS
5999 23:49:23.534092 Jitter Meter : NO K
6000 23:49:23.534206 CBT Training : PASS
6001 23:49:23.537501 Write leveling : PASS
6002 23:49:23.540862 RX DQS gating : PASS
6003 23:49:23.540972 RX DQ/DQS(RDDQC) : PASS
6004 23:49:23.544357 TX DQ/DQS : PASS
6005 23:49:23.547654 RX DATLAT : PASS
6006 23:49:23.547739 RX DQ/DQS(Engine): PASS
6007 23:49:23.550454 TX OE : NO K
6008 23:49:23.550562 All Pass.
6009 23:49:23.550655
6010 23:49:23.553897 DramC Write-DBI off
6011 23:49:23.557622 PER_BANK_REFRESH: Hybrid Mode
6012 23:49:23.557699 TX_TRACKING: ON
6013 23:49:23.567067 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6014 23:49:23.570758 [FAST_K] Save calibration result to emmc
6015 23:49:23.573893 dramc_set_vcore_voltage set vcore to 650000
6016 23:49:23.577311 Read voltage for 400, 6
6017 23:49:23.577393 Vio18 = 0
6018 23:49:23.577460 Vcore = 650000
6019 23:49:23.580719 Vdram = 0
6020 23:49:23.580796 Vddq = 0
6021 23:49:23.580858 Vmddr = 0
6022 23:49:23.586960 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6023 23:49:23.590432 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6024 23:49:23.593839 MEM_TYPE=3, freq_sel=20
6025 23:49:23.597421 sv_algorithm_assistance_LP4_800
6026 23:49:23.600448 ============ PULL DRAM RESETB DOWN ============
6027 23:49:23.603864 ========== PULL DRAM RESETB DOWN end =========
6028 23:49:23.610372 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6029 23:49:23.613744 ===================================
6030 23:49:23.617220 LPDDR4 DRAM CONFIGURATION
6031 23:49:23.620733 ===================================
6032 23:49:23.620829 EX_ROW_EN[0] = 0x0
6033 23:49:23.623525 EX_ROW_EN[1] = 0x0
6034 23:49:23.623618 LP4Y_EN = 0x0
6035 23:49:23.626933 WORK_FSP = 0x0
6036 23:49:23.627039 WL = 0x2
6037 23:49:23.630223 RL = 0x2
6038 23:49:23.630312 BL = 0x2
6039 23:49:23.633558 RPST = 0x0
6040 23:49:23.633635 RD_PRE = 0x0
6041 23:49:23.636808 WR_PRE = 0x1
6042 23:49:23.636913 WR_PST = 0x0
6043 23:49:23.640550 DBI_WR = 0x0
6044 23:49:23.640632 DBI_RD = 0x0
6045 23:49:23.643534 OTF = 0x1
6046 23:49:23.647235 ===================================
6047 23:49:23.650468 ===================================
6048 23:49:23.650572 ANA top config
6049 23:49:23.653926 ===================================
6050 23:49:23.657367 DLL_ASYNC_EN = 0
6051 23:49:23.660891 ALL_SLAVE_EN = 1
6052 23:49:23.663363 NEW_RANK_MODE = 1
6053 23:49:23.663465 DLL_IDLE_MODE = 1
6054 23:49:23.666793 LP45_APHY_COMB_EN = 1
6055 23:49:23.670267 TX_ODT_DIS = 1
6056 23:49:23.673563 NEW_8X_MODE = 1
6057 23:49:23.676827 ===================================
6058 23:49:23.680067 ===================================
6059 23:49:23.683772 data_rate = 800
6060 23:49:23.683891 CKR = 1
6061 23:49:23.686726 DQ_P2S_RATIO = 4
6062 23:49:23.690137 ===================================
6063 23:49:23.693633 CA_P2S_RATIO = 4
6064 23:49:23.697221 DQ_CA_OPEN = 0
6065 23:49:23.700102 DQ_SEMI_OPEN = 1
6066 23:49:23.703836 CA_SEMI_OPEN = 1
6067 23:49:23.703956 CA_FULL_RATE = 0
6068 23:49:23.706901 DQ_CKDIV4_EN = 0
6069 23:49:23.709983 CA_CKDIV4_EN = 1
6070 23:49:23.713797 CA_PREDIV_EN = 0
6071 23:49:23.716994 PH8_DLY = 0
6072 23:49:23.720302 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6073 23:49:23.720444 DQ_AAMCK_DIV = 0
6074 23:49:23.723585 CA_AAMCK_DIV = 0
6075 23:49:23.726974 CA_ADMCK_DIV = 4
6076 23:49:23.730358 DQ_TRACK_CA_EN = 0
6077 23:49:23.733654 CA_PICK = 800
6078 23:49:23.736332 CA_MCKIO = 400
6079 23:49:23.739896 MCKIO_SEMI = 400
6080 23:49:23.740009 PLL_FREQ = 3016
6081 23:49:23.743326 DQ_UI_PI_RATIO = 32
6082 23:49:23.746661 CA_UI_PI_RATIO = 32
6083 23:49:23.749949 ===================================
6084 23:49:23.753269 ===================================
6085 23:49:23.756500 memory_type:LPDDR4
6086 23:49:23.760033 GP_NUM : 10
6087 23:49:23.760125 SRAM_EN : 1
6088 23:49:23.763524 MD32_EN : 0
6089 23:49:23.767082 ===================================
6090 23:49:23.767159 [ANA_INIT] >>>>>>>>>>>>>>
6091 23:49:23.770433 <<<<<< [CONFIGURE PHASE]: ANA_TX
6092 23:49:23.773188 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6093 23:49:23.776579 ===================================
6094 23:49:23.779822 data_rate = 800,PCW = 0X7400
6095 23:49:23.783224 ===================================
6096 23:49:23.786587 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6097 23:49:23.793355 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 23:49:23.803422 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 23:49:23.810069 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6100 23:49:23.813399 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6101 23:49:23.816702 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6102 23:49:23.816786 [ANA_INIT] flow start
6103 23:49:23.819838 [ANA_INIT] PLL >>>>>>>>
6104 23:49:23.823576 [ANA_INIT] PLL <<<<<<<<
6105 23:49:23.823676 [ANA_INIT] MIDPI >>>>>>>>
6106 23:49:23.826650 [ANA_INIT] MIDPI <<<<<<<<
6107 23:49:23.829927 [ANA_INIT] DLL >>>>>>>>
6108 23:49:23.830014 [ANA_INIT] flow end
6109 23:49:23.836650 ============ LP4 DIFF to SE enter ============
6110 23:49:23.840047 ============ LP4 DIFF to SE exit ============
6111 23:49:23.843432 [ANA_INIT] <<<<<<<<<<<<<
6112 23:49:23.843535 [Flow] Enable top DCM control >>>>>
6113 23:49:23.846406 [Flow] Enable top DCM control <<<<<
6114 23:49:23.849703 Enable DLL master slave shuffle
6115 23:49:23.856297 ==============================================================
6116 23:49:23.859863 Gating Mode config
6117 23:49:23.863219 ==============================================================
6118 23:49:23.866577 Config description:
6119 23:49:23.876648 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6120 23:49:23.882862 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6121 23:49:23.886619 SELPH_MODE 0: By rank 1: By Phase
6122 23:49:23.893248 ==============================================================
6123 23:49:23.896536 GAT_TRACK_EN = 0
6124 23:49:23.900026 RX_GATING_MODE = 2
6125 23:49:23.900132 RX_GATING_TRACK_MODE = 2
6126 23:49:23.902933 SELPH_MODE = 1
6127 23:49:23.906449 PICG_EARLY_EN = 1
6128 23:49:23.909466 VALID_LAT_VALUE = 1
6129 23:49:23.916446 ==============================================================
6130 23:49:23.919606 Enter into Gating configuration >>>>
6131 23:49:23.922930 Exit from Gating configuration <<<<
6132 23:49:23.926263 Enter into DVFS_PRE_config >>>>>
6133 23:49:23.936506 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6134 23:49:23.939883 Exit from DVFS_PRE_config <<<<<
6135 23:49:23.943359 Enter into PICG configuration >>>>
6136 23:49:23.946065 Exit from PICG configuration <<<<
6137 23:49:23.949474 [RX_INPUT] configuration >>>>>
6138 23:49:23.953076 [RX_INPUT] configuration <<<<<
6139 23:49:23.956326 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6140 23:49:23.962561 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6141 23:49:23.969446 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 23:49:23.975955 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 23:49:23.979387 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 23:49:23.986151 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 23:49:23.992937 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6146 23:49:23.996141 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6147 23:49:23.999307 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6148 23:49:24.002750 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6149 23:49:24.005713 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6150 23:49:24.012626 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6151 23:49:24.015426 ===================================
6152 23:49:24.019390 LPDDR4 DRAM CONFIGURATION
6153 23:49:24.022605 ===================================
6154 23:49:24.022684 EX_ROW_EN[0] = 0x0
6155 23:49:24.025731 EX_ROW_EN[1] = 0x0
6156 23:49:24.025805 LP4Y_EN = 0x0
6157 23:49:24.028755 WORK_FSP = 0x0
6158 23:49:24.028880 WL = 0x2
6159 23:49:24.032507 RL = 0x2
6160 23:49:24.032614 BL = 0x2
6161 23:49:24.035807 RPST = 0x0
6162 23:49:24.035881 RD_PRE = 0x0
6163 23:49:24.038928 WR_PRE = 0x1
6164 23:49:24.039060 WR_PST = 0x0
6165 23:49:24.042435 DBI_WR = 0x0
6166 23:49:24.042511 DBI_RD = 0x0
6167 23:49:24.045469 OTF = 0x1
6168 23:49:24.049022 ===================================
6169 23:49:24.052636 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6170 23:49:24.055218 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6171 23:49:24.062022 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 23:49:24.065596 ===================================
6173 23:49:24.068527 LPDDR4 DRAM CONFIGURATION
6174 23:49:24.071780 ===================================
6175 23:49:24.071889 EX_ROW_EN[0] = 0x10
6176 23:49:24.075266 EX_ROW_EN[1] = 0x0
6177 23:49:24.075409 LP4Y_EN = 0x0
6178 23:49:24.078641 WORK_FSP = 0x0
6179 23:49:24.078728 WL = 0x2
6180 23:49:24.082067 RL = 0x2
6181 23:49:24.082147 BL = 0x2
6182 23:49:24.085522 RPST = 0x0
6183 23:49:24.085603 RD_PRE = 0x0
6184 23:49:24.088959 WR_PRE = 0x1
6185 23:49:24.089039 WR_PST = 0x0
6186 23:49:24.092244 DBI_WR = 0x0
6187 23:49:24.092372 DBI_RD = 0x0
6188 23:49:24.095717 OTF = 0x1
6189 23:49:24.098439 ===================================
6190 23:49:24.105281 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6191 23:49:24.108649 nWR fixed to 30
6192 23:49:24.112214 [ModeRegInit_LP4] CH0 RK0
6193 23:49:24.112320 [ModeRegInit_LP4] CH0 RK1
6194 23:49:24.115196 [ModeRegInit_LP4] CH1 RK0
6195 23:49:24.119034 [ModeRegInit_LP4] CH1 RK1
6196 23:49:24.119114 match AC timing 19
6197 23:49:24.125123 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6198 23:49:24.128735 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6199 23:49:24.132096 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6200 23:49:24.138392 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6201 23:49:24.142237 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6202 23:49:24.142392 ==
6203 23:49:24.145447 Dram Type= 6, Freq= 0, CH_0, rank 0
6204 23:49:24.148404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6205 23:49:24.148487 ==
6206 23:49:24.155291 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6207 23:49:24.161821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6208 23:49:24.164908 [CA 0] Center 36 (8~64) winsize 57
6209 23:49:24.168257 [CA 1] Center 36 (8~64) winsize 57
6210 23:49:24.168385 [CA 2] Center 36 (8~64) winsize 57
6211 23:49:24.171749 [CA 3] Center 36 (8~64) winsize 57
6212 23:49:24.175320 [CA 4] Center 36 (8~64) winsize 57
6213 23:49:24.178688 [CA 5] Center 36 (8~64) winsize 57
6214 23:49:24.178815
6215 23:49:24.182163 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6216 23:49:24.182244
6217 23:49:24.188301 [CATrainingPosCal] consider 1 rank data
6218 23:49:24.188426 u2DelayCellTimex100 = 270/100 ps
6219 23:49:24.191794 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 23:49:24.198495 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 23:49:24.201979 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 23:49:24.204831 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 23:49:24.208214 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 23:49:24.211660 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 23:49:24.211735
6226 23:49:24.214987 CA PerBit enable=1, Macro0, CA PI delay=36
6227 23:49:24.215064
6228 23:49:24.218397 [CBTSetCACLKResult] CA Dly = 36
6229 23:49:24.221923 CS Dly: 1 (0~32)
6230 23:49:24.221999 ==
6231 23:49:24.225261 Dram Type= 6, Freq= 0, CH_0, rank 1
6232 23:49:24.227958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 23:49:24.228040 ==
6234 23:49:24.235369 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 23:49:24.237828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6236 23:49:24.241458 [CA 0] Center 36 (8~64) winsize 57
6237 23:49:24.244490 [CA 1] Center 36 (8~64) winsize 57
6238 23:49:24.248380 [CA 2] Center 36 (8~64) winsize 57
6239 23:49:24.251575 [CA 3] Center 36 (8~64) winsize 57
6240 23:49:24.254704 [CA 4] Center 36 (8~64) winsize 57
6241 23:49:24.258051 [CA 5] Center 36 (8~64) winsize 57
6242 23:49:24.258137
6243 23:49:24.261111 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6244 23:49:24.261206
6245 23:49:24.265138 [CATrainingPosCal] consider 2 rank data
6246 23:49:24.268217 u2DelayCellTimex100 = 270/100 ps
6247 23:49:24.271450 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 23:49:24.274557 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 23:49:24.277878 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 23:49:24.284613 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 23:49:24.287930 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 23:49:24.291395 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 23:49:24.291473
6254 23:49:24.294817 CA PerBit enable=1, Macro0, CA PI delay=36
6255 23:49:24.294893
6256 23:49:24.297989 [CBTSetCACLKResult] CA Dly = 36
6257 23:49:24.298066 CS Dly: 1 (0~32)
6258 23:49:24.298130
6259 23:49:24.301205 ----->DramcWriteLeveling(PI) begin...
6260 23:49:24.301291 ==
6261 23:49:24.304671 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 23:49:24.311448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 23:49:24.311532 ==
6264 23:49:24.314245 Write leveling (Byte 0): 40 => 8
6265 23:49:24.317571 Write leveling (Byte 1): 40 => 8
6266 23:49:24.317653 DramcWriteLeveling(PI) end<-----
6267 23:49:24.317718
6268 23:49:24.320961 ==
6269 23:49:24.324359 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 23:49:24.327595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 23:49:24.327675 ==
6272 23:49:24.330958 [Gating] SW mode calibration
6273 23:49:24.337720 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6274 23:49:24.341110 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6275 23:49:24.347530 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 23:49:24.350781 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 23:49:24.354485 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 23:49:24.361104 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 23:49:24.364184 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 23:49:24.367410 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 23:49:24.374449 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 23:49:24.377675 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 23:49:24.381137 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 23:49:24.384539 Total UI for P1: 0, mck2ui 16
6285 23:49:24.387687 best dqsien dly found for B0: ( 0, 14, 24)
6286 23:49:24.390771 Total UI for P1: 0, mck2ui 16
6287 23:49:24.394509 best dqsien dly found for B1: ( 0, 14, 24)
6288 23:49:24.397885 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6289 23:49:24.400940 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6290 23:49:24.401025
6291 23:49:24.404137 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 23:49:24.410941 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 23:49:24.411036 [Gating] SW calibration Done
6294 23:49:24.414413 ==
6295 23:49:24.414507 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 23:49:24.420598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 23:49:24.420694 ==
6298 23:49:24.420765 RX Vref Scan: 0
6299 23:49:24.420828
6300 23:49:24.424007 RX Vref 0 -> 0, step: 1
6301 23:49:24.424101
6302 23:49:24.427549 RX Delay -410 -> 252, step: 16
6303 23:49:24.430702 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6304 23:49:24.434130 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6305 23:49:24.440884 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6306 23:49:24.444301 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6307 23:49:24.447854 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6308 23:49:24.450594 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6309 23:49:24.457164 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6310 23:49:24.460523 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6311 23:49:24.463946 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6312 23:49:24.467652 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6313 23:49:24.473986 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6314 23:49:24.477476 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6315 23:49:24.480522 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6316 23:49:24.483890 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6317 23:49:24.490322 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6318 23:49:24.494044 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6319 23:49:24.494154 ==
6320 23:49:24.497310 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 23:49:24.500488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 23:49:24.500581 ==
6323 23:49:24.503656 DQS Delay:
6324 23:49:24.503734 DQS0 = 27, DQS1 = 35
6325 23:49:24.507203 DQM Delay:
6326 23:49:24.507317 DQM0 = 9, DQM1 = 11
6327 23:49:24.507382 DQ Delay:
6328 23:49:24.510682 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6329 23:49:24.513786 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6330 23:49:24.516894 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6331 23:49:24.520267 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6332 23:49:24.520394
6333 23:49:24.520471
6334 23:49:24.520533 ==
6335 23:49:24.523643 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 23:49:24.530477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 23:49:24.530556 ==
6338 23:49:24.530646
6339 23:49:24.530743
6340 23:49:24.530840 TX Vref Scan disable
6341 23:49:24.533949 == TX Byte 0 ==
6342 23:49:24.537116 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 23:49:24.540615 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 23:49:24.544046 == TX Byte 1 ==
6345 23:49:24.547446 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6346 23:49:24.550737 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6347 23:49:24.550825 ==
6348 23:49:24.553699 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 23:49:24.560646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 23:49:24.560743 ==
6351 23:49:24.560816
6352 23:49:24.560894
6353 23:49:24.560956 TX Vref Scan disable
6354 23:49:24.564015 == TX Byte 0 ==
6355 23:49:24.567585 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 23:49:24.570656 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 23:49:24.573956 == TX Byte 1 ==
6358 23:49:24.577171 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6359 23:49:24.580467 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6360 23:49:24.580559
6361 23:49:24.583798 [DATLAT]
6362 23:49:24.583870 Freq=400, CH0 RK0
6363 23:49:24.583932
6364 23:49:24.587022 DATLAT Default: 0xf
6365 23:49:24.587097 0, 0xFFFF, sum = 0
6366 23:49:24.590050 1, 0xFFFF, sum = 0
6367 23:49:24.590127 2, 0xFFFF, sum = 0
6368 23:49:24.593149 3, 0xFFFF, sum = 0
6369 23:49:24.593246 4, 0xFFFF, sum = 0
6370 23:49:24.596590 5, 0xFFFF, sum = 0
6371 23:49:24.596670 6, 0xFFFF, sum = 0
6372 23:49:24.600412 7, 0xFFFF, sum = 0
6373 23:49:24.600503 8, 0xFFFF, sum = 0
6374 23:49:24.603629 9, 0xFFFF, sum = 0
6375 23:49:24.603713 10, 0xFFFF, sum = 0
6376 23:49:24.606711 11, 0xFFFF, sum = 0
6377 23:49:24.610471 12, 0xFFFF, sum = 0
6378 23:49:24.610556 13, 0x0, sum = 1
6379 23:49:24.613347 14, 0x0, sum = 2
6380 23:49:24.613429 15, 0x0, sum = 3
6381 23:49:24.613539 16, 0x0, sum = 4
6382 23:49:24.616482 best_step = 14
6383 23:49:24.616591
6384 23:49:24.616701 ==
6385 23:49:24.620128 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 23:49:24.623203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 23:49:24.623311 ==
6388 23:49:24.626592 RX Vref Scan: 1
6389 23:49:24.626694
6390 23:49:24.626799 RX Vref 0 -> 0, step: 1
6391 23:49:24.629923
6392 23:49:24.630026 RX Delay -311 -> 252, step: 8
6393 23:49:24.630134
6394 23:49:24.633303 Set Vref, RX VrefLevel [Byte0]: 57
6395 23:49:24.636772 [Byte1]: 48
6396 23:49:24.641433
6397 23:49:24.641571 Final RX Vref Byte 0 = 57 to rank0
6398 23:49:24.644749 Final RX Vref Byte 1 = 48 to rank0
6399 23:49:24.648231 Final RX Vref Byte 0 = 57 to rank1
6400 23:49:24.651763 Final RX Vref Byte 1 = 48 to rank1==
6401 23:49:24.655271 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 23:49:24.661524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 23:49:24.661722 ==
6404 23:49:24.661845 DQS Delay:
6405 23:49:24.664923 DQS0 = 28, DQS1 = 36
6406 23:49:24.665073 DQM Delay:
6407 23:49:24.665204 DQM0 = 11, DQM1 = 12
6408 23:49:24.668282 DQ Delay:
6409 23:49:24.671602 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6410 23:49:24.671749 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6411 23:49:24.674944 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6412 23:49:24.678334 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6413 23:49:24.678500
6414 23:49:24.681636
6415 23:49:24.688089 [DQSOSCAuto] RK0, (LSB)MR18= 0xccb9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6416 23:49:24.691396 CH0 RK0: MR19=C0C, MR18=CCB9
6417 23:49:24.698173 CH0_RK0: MR19=0xC0C, MR18=0xCCB9, DQSOSC=384, MR23=63, INC=400, DEC=267
6418 23:49:24.698293 ==
6419 23:49:24.701474 Dram Type= 6, Freq= 0, CH_0, rank 1
6420 23:49:24.704783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 23:49:24.704893 ==
6422 23:49:24.707984 [Gating] SW mode calibration
6423 23:49:24.714707 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6424 23:49:24.717919 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6425 23:49:24.724737 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 23:49:24.727996 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 23:49:24.731581 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 23:49:24.737877 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 23:49:24.741466 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 23:49:24.744839 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 23:49:24.751327 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 23:49:24.754302 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 23:49:24.757646 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 23:49:24.761149 Total UI for P1: 0, mck2ui 16
6435 23:49:24.764592 best dqsien dly found for B0: ( 0, 14, 24)
6436 23:49:24.767920 Total UI for P1: 0, mck2ui 16
6437 23:49:24.771212 best dqsien dly found for B1: ( 0, 14, 24)
6438 23:49:24.774491 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6439 23:49:24.777852 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6440 23:49:24.781323
6441 23:49:24.784709 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 23:49:24.788022 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 23:49:24.791359 [Gating] SW calibration Done
6444 23:49:24.791490 ==
6445 23:49:24.794933 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 23:49:24.798215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 23:49:24.798347 ==
6448 23:49:24.798458 RX Vref Scan: 0
6449 23:49:24.798559
6450 23:49:24.801082 RX Vref 0 -> 0, step: 1
6451 23:49:24.801195
6452 23:49:24.804475 RX Delay -410 -> 252, step: 16
6453 23:49:24.807702 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6454 23:49:24.814759 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6455 23:49:24.817832 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6456 23:49:24.821214 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6457 23:49:24.824483 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6458 23:49:24.831062 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6459 23:49:24.834152 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6460 23:49:24.837758 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6461 23:49:24.840978 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6462 23:49:24.844644 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6463 23:49:24.850987 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6464 23:49:24.854355 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6465 23:49:24.857506 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6466 23:49:24.864300 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6467 23:49:24.867218 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6468 23:49:24.870866 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6469 23:49:24.870972 ==
6470 23:49:24.873868 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 23:49:24.880610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 23:49:24.880729 ==
6473 23:49:24.880828 DQS Delay:
6474 23:49:24.880900 DQS0 = 27, DQS1 = 35
6475 23:49:24.883879 DQM Delay:
6476 23:49:24.883984 DQM0 = 12, DQM1 = 12
6477 23:49:24.887255 DQ Delay:
6478 23:49:24.887372 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6479 23:49:24.890733 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6480 23:49:24.894025 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6481 23:49:24.897347 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6482 23:49:24.897461
6483 23:49:24.897555
6484 23:49:24.900986 ==
6485 23:49:24.901094 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 23:49:24.907615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 23:49:24.907732 ==
6488 23:49:24.907830
6489 23:49:24.907926
6490 23:49:24.910451 TX Vref Scan disable
6491 23:49:24.910571 == TX Byte 0 ==
6492 23:49:24.914287 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6493 23:49:24.917592 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6494 23:49:24.920502 == TX Byte 1 ==
6495 23:49:24.923759 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6496 23:49:24.927039 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6497 23:49:24.930262 ==
6498 23:49:24.930368 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 23:49:24.936952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 23:49:24.937093 ==
6501 23:49:24.937201
6502 23:49:24.937292
6503 23:49:24.940418 TX Vref Scan disable
6504 23:49:24.940526 == TX Byte 0 ==
6505 23:49:24.943583 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6506 23:49:24.950337 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6507 23:49:24.950485 == TX Byte 1 ==
6508 23:49:24.953583 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6509 23:49:24.956803 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6510 23:49:24.960196
6511 23:49:24.960326 [DATLAT]
6512 23:49:24.960407 Freq=400, CH0 RK1
6513 23:49:24.960472
6514 23:49:24.963583 DATLAT Default: 0xe
6515 23:49:24.963710 0, 0xFFFF, sum = 0
6516 23:49:24.967067 1, 0xFFFF, sum = 0
6517 23:49:24.967151 2, 0xFFFF, sum = 0
6518 23:49:24.970313 3, 0xFFFF, sum = 0
6519 23:49:24.973684 4, 0xFFFF, sum = 0
6520 23:49:24.973770 5, 0xFFFF, sum = 0
6521 23:49:24.976945 6, 0xFFFF, sum = 0
6522 23:49:24.977024 7, 0xFFFF, sum = 0
6523 23:49:24.980067 8, 0xFFFF, sum = 0
6524 23:49:24.980145 9, 0xFFFF, sum = 0
6525 23:49:24.983145 10, 0xFFFF, sum = 0
6526 23:49:24.983222 11, 0xFFFF, sum = 0
6527 23:49:24.986708 12, 0xFFFF, sum = 0
6528 23:49:24.986787 13, 0x0, sum = 1
6529 23:49:24.989795 14, 0x0, sum = 2
6530 23:49:24.989881 15, 0x0, sum = 3
6531 23:49:24.993104 16, 0x0, sum = 4
6532 23:49:24.993189 best_step = 14
6533 23:49:24.993255
6534 23:49:24.993316 ==
6535 23:49:24.996458 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 23:49:24.999739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 23:49:25.003035 ==
6538 23:49:25.003152 RX Vref Scan: 0
6539 23:49:25.003247
6540 23:49:25.006727 RX Vref 0 -> 0, step: 1
6541 23:49:25.006835
6542 23:49:25.010124 RX Delay -311 -> 252, step: 8
6543 23:49:25.013510 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6544 23:49:25.020180 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6545 23:49:25.022930 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6546 23:49:25.026225 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6547 23:49:25.029726 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6548 23:49:25.036299 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6549 23:49:25.040021 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6550 23:49:25.043377 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6551 23:49:25.046775 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6552 23:49:25.053236 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6553 23:49:25.056354 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6554 23:49:25.059638 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6555 23:49:25.063557 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6556 23:49:25.069580 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6557 23:49:25.073002 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6558 23:49:25.076396 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6559 23:49:25.076508 ==
6560 23:49:25.079590 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 23:49:25.082934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 23:49:25.086402 ==
6563 23:49:25.086488 DQS Delay:
6564 23:49:25.086558 DQS0 = 24, DQS1 = 32
6565 23:49:25.089784 DQM Delay:
6566 23:49:25.089868 DQM0 = 9, DQM1 = 10
6567 23:49:25.093045 DQ Delay:
6568 23:49:25.093130 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6569 23:49:25.096329 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6570 23:49:25.099904 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6571 23:49:25.102994 DQ12 =16, DQ13 =12, DQ14 =20, DQ15 =16
6572 23:49:25.103080
6573 23:49:25.103147
6574 23:49:25.112877 [DQSOSCAuto] RK1, (LSB)MR18= 0xc061, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps
6575 23:49:25.116343 CH0 RK1: MR19=C0C, MR18=C061
6576 23:49:25.122836 CH0_RK1: MR19=0xC0C, MR18=0xC061, DQSOSC=386, MR23=63, INC=396, DEC=264
6577 23:49:25.122925 [RxdqsGatingPostProcess] freq 400
6578 23:49:25.129785 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6579 23:49:25.133305 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 23:49:25.136629 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 23:49:25.139467 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 23:49:25.142813 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 23:49:25.146009 best DQS0 dly(2T, 0.5T) = (0, 10)
6584 23:49:25.149667 best DQS1 dly(2T, 0.5T) = (0, 10)
6585 23:49:25.152762 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6586 23:49:25.155991 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6587 23:49:25.159253 Pre-setting of DQS Precalculation
6588 23:49:25.162624 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6589 23:49:25.162715 ==
6590 23:49:25.166343 Dram Type= 6, Freq= 0, CH_1, rank 0
6591 23:49:25.169410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 23:49:25.169504 ==
6593 23:49:25.176515 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6594 23:49:25.183046 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6595 23:49:25.186429 [CA 0] Center 36 (8~64) winsize 57
6596 23:49:25.190069 [CA 1] Center 36 (8~64) winsize 57
6597 23:49:25.192671 [CA 2] Center 36 (8~64) winsize 57
6598 23:49:25.196110 [CA 3] Center 36 (8~64) winsize 57
6599 23:49:25.199546 [CA 4] Center 36 (8~64) winsize 57
6600 23:49:25.199631 [CA 5] Center 36 (8~64) winsize 57
6601 23:49:25.203032
6602 23:49:25.205954 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6603 23:49:25.206038
6604 23:49:25.209685 [CATrainingPosCal] consider 1 rank data
6605 23:49:25.212582 u2DelayCellTimex100 = 270/100 ps
6606 23:49:25.216010 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 23:49:25.219101 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 23:49:25.222923 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 23:49:25.226157 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 23:49:25.229399 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 23:49:25.232888 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 23:49:25.232999
6613 23:49:25.236319 CA PerBit enable=1, Macro0, CA PI delay=36
6614 23:49:25.236434
6615 23:49:25.239775 [CBTSetCACLKResult] CA Dly = 36
6616 23:49:25.242628 CS Dly: 1 (0~32)
6617 23:49:25.242738 ==
6618 23:49:25.246009 Dram Type= 6, Freq= 0, CH_1, rank 1
6619 23:49:25.249361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 23:49:25.249448 ==
6621 23:49:25.256036 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 23:49:25.262511 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6623 23:49:25.262657 [CA 0] Center 36 (8~64) winsize 57
6624 23:49:25.266482 [CA 1] Center 36 (8~64) winsize 57
6625 23:49:25.269482 [CA 2] Center 36 (8~64) winsize 57
6626 23:49:25.272688 [CA 3] Center 36 (8~64) winsize 57
6627 23:49:25.275865 [CA 4] Center 36 (8~64) winsize 57
6628 23:49:25.279673 [CA 5] Center 36 (8~64) winsize 57
6629 23:49:25.279750
6630 23:49:25.282718 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6631 23:49:25.282793
6632 23:49:25.286086 [CATrainingPosCal] consider 2 rank data
6633 23:49:25.289553 u2DelayCellTimex100 = 270/100 ps
6634 23:49:25.292702 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 23:49:25.299425 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 23:49:25.302957 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 23:49:25.306145 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 23:49:25.308950 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 23:49:25.312221 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 23:49:25.312303
6641 23:49:25.315605 CA PerBit enable=1, Macro0, CA PI delay=36
6642 23:49:25.315687
6643 23:49:25.318850 [CBTSetCACLKResult] CA Dly = 36
6644 23:49:25.318933 CS Dly: 1 (0~32)
6645 23:49:25.322204
6646 23:49:25.325951 ----->DramcWriteLeveling(PI) begin...
6647 23:49:25.326036 ==
6648 23:49:25.329037 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 23:49:25.332145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 23:49:25.332228 ==
6651 23:49:25.335643 Write leveling (Byte 0): 40 => 8
6652 23:49:25.339015 Write leveling (Byte 1): 40 => 8
6653 23:49:25.341942 DramcWriteLeveling(PI) end<-----
6654 23:49:25.342023
6655 23:49:25.342088 ==
6656 23:49:25.345244 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 23:49:25.348659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 23:49:25.348742 ==
6659 23:49:25.352097 [Gating] SW mode calibration
6660 23:49:25.358603 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6661 23:49:25.365266 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6662 23:49:25.368729 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 23:49:25.372096 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 23:49:25.378918 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 23:49:25.381979 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 23:49:25.385910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 23:49:25.389013 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 23:49:25.395670 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 23:49:25.398708 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 23:49:25.401932 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 23:49:25.405364 Total UI for P1: 0, mck2ui 16
6672 23:49:25.408815 best dqsien dly found for B0: ( 0, 14, 24)
6673 23:49:25.412211 Total UI for P1: 0, mck2ui 16
6674 23:49:25.415763 best dqsien dly found for B1: ( 0, 14, 24)
6675 23:49:25.418576 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6676 23:49:25.425361 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6677 23:49:25.425449
6678 23:49:25.428621 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 23:49:25.431997 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 23:49:25.435218 [Gating] SW calibration Done
6681 23:49:25.435332 ==
6682 23:49:25.438722 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 23:49:25.441920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 23:49:25.442034 ==
6685 23:49:25.442119 RX Vref Scan: 0
6686 23:49:25.445217
6687 23:49:25.445326 RX Vref 0 -> 0, step: 1
6688 23:49:25.445393
6689 23:49:25.448451 RX Delay -410 -> 252, step: 16
6690 23:49:25.451974 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6691 23:49:25.458538 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6692 23:49:25.462007 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6693 23:49:25.465358 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6694 23:49:25.468578 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6695 23:49:25.475465 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6696 23:49:25.478247 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6697 23:49:25.482254 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6698 23:49:25.485531 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6699 23:49:25.491996 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6700 23:49:25.495399 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6701 23:49:25.498593 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6702 23:49:25.501859 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6703 23:49:25.508499 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6704 23:49:25.511649 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6705 23:49:25.514988 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6706 23:49:25.515072 ==
6707 23:49:25.518409 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 23:49:25.524616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 23:49:25.524699 ==
6710 23:49:25.524764 DQS Delay:
6711 23:49:25.528101 DQS0 = 35, DQS1 = 35
6712 23:49:25.528183 DQM Delay:
6713 23:49:25.528247 DQM0 = 17, DQM1 = 13
6714 23:49:25.531582 DQ Delay:
6715 23:49:25.534978 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6716 23:49:25.538316 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6717 23:49:25.538397 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6718 23:49:25.541370 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6719 23:49:25.544868
6720 23:49:25.544950
6721 23:49:25.545015 ==
6722 23:49:25.548418 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 23:49:25.551531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 23:49:25.551615 ==
6725 23:49:25.551680
6726 23:49:25.551739
6727 23:49:25.555065 TX Vref Scan disable
6728 23:49:25.555147 == TX Byte 0 ==
6729 23:49:25.558341 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 23:49:25.564656 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 23:49:25.564740 == TX Byte 1 ==
6732 23:49:25.568197 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 23:49:25.574992 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 23:49:25.575074 ==
6735 23:49:25.578107 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 23:49:25.581503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 23:49:25.581585 ==
6738 23:49:25.581651
6739 23:49:25.581711
6740 23:49:25.584872 TX Vref Scan disable
6741 23:49:25.584954 == TX Byte 0 ==
6742 23:49:25.588179 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 23:49:25.594827 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 23:49:25.594912 == TX Byte 1 ==
6745 23:49:25.598235 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 23:49:25.604835 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 23:49:25.604923
6748 23:49:25.604987 [DATLAT]
6749 23:49:25.605080 Freq=400, CH1 RK0
6750 23:49:25.608259
6751 23:49:25.608365 DATLAT Default: 0xf
6752 23:49:25.611003 0, 0xFFFF, sum = 0
6753 23:49:25.611086 1, 0xFFFF, sum = 0
6754 23:49:25.614250 2, 0xFFFF, sum = 0
6755 23:49:25.614332 3, 0xFFFF, sum = 0
6756 23:49:25.618347 4, 0xFFFF, sum = 0
6757 23:49:25.618430 5, 0xFFFF, sum = 0
6758 23:49:25.621024 6, 0xFFFF, sum = 0
6759 23:49:25.621107 7, 0xFFFF, sum = 0
6760 23:49:25.624183 8, 0xFFFF, sum = 0
6761 23:49:25.624266 9, 0xFFFF, sum = 0
6762 23:49:25.628093 10, 0xFFFF, sum = 0
6763 23:49:25.628176 11, 0xFFFF, sum = 0
6764 23:49:25.631645 12, 0xFFFF, sum = 0
6765 23:49:25.631728 13, 0x0, sum = 1
6766 23:49:25.634278 14, 0x0, sum = 2
6767 23:49:25.634361 15, 0x0, sum = 3
6768 23:49:25.637757 16, 0x0, sum = 4
6769 23:49:25.637839 best_step = 14
6770 23:49:25.637903
6771 23:49:25.637963 ==
6772 23:49:25.640979 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 23:49:25.647747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 23:49:25.647829 ==
6775 23:49:25.647895 RX Vref Scan: 1
6776 23:49:25.647955
6777 23:49:25.650702 RX Vref 0 -> 0, step: 1
6778 23:49:25.650783
6779 23:49:25.654590 RX Delay -311 -> 252, step: 8
6780 23:49:25.654672
6781 23:49:25.657323 Set Vref, RX VrefLevel [Byte0]: 54
6782 23:49:25.660687 [Byte1]: 55
6783 23:49:25.660768
6784 23:49:25.664120 Final RX Vref Byte 0 = 54 to rank0
6785 23:49:25.667557 Final RX Vref Byte 1 = 55 to rank0
6786 23:49:25.670749 Final RX Vref Byte 0 = 54 to rank1
6787 23:49:25.674215 Final RX Vref Byte 1 = 55 to rank1==
6788 23:49:25.677433 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 23:49:25.680536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 23:49:25.680618 ==
6791 23:49:25.684283 DQS Delay:
6792 23:49:25.684388 DQS0 = 28, DQS1 = 32
6793 23:49:25.687473 DQM Delay:
6794 23:49:25.687554 DQM0 = 9, DQM1 = 9
6795 23:49:25.687618 DQ Delay:
6796 23:49:25.691112 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6797 23:49:25.694422 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6798 23:49:25.697720 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6799 23:49:25.700942 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6800 23:49:25.701026
6801 23:49:25.701092
6802 23:49:25.710960 [DQSOSCAuto] RK0, (LSB)MR18= 0x91ca, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6803 23:49:25.711044 CH1 RK0: MR19=C0C, MR18=91CA
6804 23:49:25.717064 CH1_RK0: MR19=0xC0C, MR18=0x91CA, DQSOSC=384, MR23=63, INC=400, DEC=267
6805 23:49:25.717148 ==
6806 23:49:25.720738 Dram Type= 6, Freq= 0, CH_1, rank 1
6807 23:49:25.727228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 23:49:25.727317 ==
6809 23:49:25.730588 [Gating] SW mode calibration
6810 23:49:25.737409 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6811 23:49:25.740572 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6812 23:49:25.747229 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 23:49:25.750659 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6814 23:49:25.753538 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 23:49:25.760582 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 23:49:25.763960 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 23:49:25.766716 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 23:49:25.773506 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 23:49:25.776724 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 23:49:25.780216 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 23:49:25.783698 Total UI for P1: 0, mck2ui 16
6822 23:49:25.786979 best dqsien dly found for B0: ( 0, 14, 24)
6823 23:49:25.790241 Total UI for P1: 0, mck2ui 16
6824 23:49:25.793501 best dqsien dly found for B1: ( 0, 14, 24)
6825 23:49:25.796884 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6826 23:49:25.800254 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6827 23:49:25.800392
6828 23:49:25.806408 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 23:49:25.809633 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 23:49:25.809717 [Gating] SW calibration Done
6831 23:49:25.813098 ==
6832 23:49:25.816663 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 23:49:25.820079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 23:49:25.820189 ==
6835 23:49:25.820293 RX Vref Scan: 0
6836 23:49:25.820397
6837 23:49:25.822816 RX Vref 0 -> 0, step: 1
6838 23:49:25.822898
6839 23:49:25.826224 RX Delay -410 -> 252, step: 16
6840 23:49:25.829815 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6841 23:49:25.836658 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6842 23:49:25.839347 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6843 23:49:25.842883 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6844 23:49:25.846244 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6845 23:49:25.849484 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6846 23:49:25.856303 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6847 23:49:25.859409 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6848 23:49:25.862617 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6849 23:49:25.866462 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6850 23:49:25.873180 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6851 23:49:25.876530 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6852 23:49:25.879834 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6853 23:49:25.883004 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6854 23:49:25.889580 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6855 23:49:25.893111 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6856 23:49:25.893194 ==
6857 23:49:25.896193 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 23:49:25.899431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 23:49:25.899515 ==
6860 23:49:25.902702 DQS Delay:
6861 23:49:25.902789 DQS0 = 35, DQS1 = 35
6862 23:49:25.905839 DQM Delay:
6863 23:49:25.905944 DQM0 = 18, DQM1 = 14
6864 23:49:25.909720 DQ Delay:
6865 23:49:25.909805 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6866 23:49:25.912979 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6867 23:49:25.916236 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6868 23:49:25.919402 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6869 23:49:25.919487
6870 23:49:25.919554
6871 23:49:25.922612 ==
6872 23:49:25.922698 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 23:49:25.929529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 23:49:25.929655 ==
6875 23:49:25.929763
6876 23:49:25.929857
6877 23:49:25.933199 TX Vref Scan disable
6878 23:49:25.933319 == TX Byte 0 ==
6879 23:49:25.936309 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6880 23:49:25.939004 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6881 23:49:25.942432 == TX Byte 1 ==
6882 23:49:25.945852 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6883 23:49:25.949231 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6884 23:49:25.952698 ==
6885 23:49:25.952807 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 23:49:25.959509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 23:49:25.959624 ==
6888 23:49:25.959726
6889 23:49:25.959830
6890 23:49:25.962719 TX Vref Scan disable
6891 23:49:25.962838 == TX Byte 0 ==
6892 23:49:25.965889 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6893 23:49:25.972404 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6894 23:49:25.972515 == TX Byte 1 ==
6895 23:49:25.975778 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6896 23:49:25.979291 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6897 23:49:25.982507
6898 23:49:25.982583 [DATLAT]
6899 23:49:25.982647 Freq=400, CH1 RK1
6900 23:49:25.982708
6901 23:49:25.985886 DATLAT Default: 0xe
6902 23:49:25.985960 0, 0xFFFF, sum = 0
6903 23:49:25.989104 1, 0xFFFF, sum = 0
6904 23:49:25.989209 2, 0xFFFF, sum = 0
6905 23:49:25.992452 3, 0xFFFF, sum = 0
6906 23:49:25.992554 4, 0xFFFF, sum = 0
6907 23:49:25.995970 5, 0xFFFF, sum = 0
6908 23:49:25.996071 6, 0xFFFF, sum = 0
6909 23:49:25.999376 7, 0xFFFF, sum = 0
6910 23:49:25.999481 8, 0xFFFF, sum = 0
6911 23:49:26.002837 9, 0xFFFF, sum = 0
6912 23:49:26.005690 10, 0xFFFF, sum = 0
6913 23:49:26.005775 11, 0xFFFF, sum = 0
6914 23:49:26.009383 12, 0xFFFF, sum = 0
6915 23:49:26.009495 13, 0x0, sum = 1
6916 23:49:26.012674 14, 0x0, sum = 2
6917 23:49:26.012753 15, 0x0, sum = 3
6918 23:49:26.015975 16, 0x0, sum = 4
6919 23:49:26.016079 best_step = 14
6920 23:49:26.016170
6921 23:49:26.016259 ==
6922 23:49:26.019334 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 23:49:26.022664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 23:49:26.022749 ==
6925 23:49:26.026047 RX Vref Scan: 0
6926 23:49:26.026131
6927 23:49:26.029252 RX Vref 0 -> 0, step: 1
6928 23:49:26.029336
6929 23:49:26.029402 RX Delay -311 -> 252, step: 8
6930 23:49:26.037744 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6931 23:49:26.040899 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6932 23:49:26.044423 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6933 23:49:26.047914 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6934 23:49:26.054614 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6935 23:49:26.057360 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6936 23:49:26.060775 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6937 23:49:26.064240 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6938 23:49:26.070946 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6939 23:49:26.074710 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6940 23:49:26.077724 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6941 23:49:26.081308 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6942 23:49:26.087757 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6943 23:49:26.091108 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6944 23:49:26.094434 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6945 23:49:26.097793 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6946 23:49:26.101255 ==
6947 23:49:26.104602 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 23:49:26.107355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 23:49:26.107466 ==
6950 23:49:26.107562 DQS Delay:
6951 23:49:26.110809 DQS0 = 28, DQS1 = 36
6952 23:49:26.110892 DQM Delay:
6953 23:49:26.114257 DQM0 = 10, DQM1 = 14
6954 23:49:26.114341 DQ Delay:
6955 23:49:26.117464 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6956 23:49:26.121250 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6957 23:49:26.124276 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6958 23:49:26.127673 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6959 23:49:26.127755
6960 23:49:26.127820
6961 23:49:26.134277 [DQSOSCAuto] RK1, (LSB)MR18= 0xc252, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6962 23:49:26.137331 CH1 RK1: MR19=C0C, MR18=C252
6963 23:49:26.144109 CH1_RK1: MR19=0xC0C, MR18=0xC252, DQSOSC=385, MR23=63, INC=398, DEC=265
6964 23:49:26.147360 [RxdqsGatingPostProcess] freq 400
6965 23:49:26.150764 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6966 23:49:26.154084 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 23:49:26.157438 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 23:49:26.160849 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 23:49:26.163616 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 23:49:26.166993 best DQS0 dly(2T, 0.5T) = (0, 10)
6971 23:49:26.170576 best DQS1 dly(2T, 0.5T) = (0, 10)
6972 23:49:26.174018 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6973 23:49:26.177328 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6974 23:49:26.181151 Pre-setting of DQS Precalculation
6975 23:49:26.184097 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6976 23:49:26.193966 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6977 23:49:26.200688 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6978 23:49:26.200773
6979 23:49:26.200837
6980 23:49:26.203702 [Calibration Summary] 800 Mbps
6981 23:49:26.203779 CH 0, Rank 0
6982 23:49:26.207490 SW Impedance : PASS
6983 23:49:26.207615 DUTY Scan : NO K
6984 23:49:26.210952 ZQ Calibration : PASS
6985 23:49:26.213755 Jitter Meter : NO K
6986 23:49:26.213844 CBT Training : PASS
6987 23:49:26.217225 Write leveling : PASS
6988 23:49:26.220621 RX DQS gating : PASS
6989 23:49:26.220704 RX DQ/DQS(RDDQC) : PASS
6990 23:49:26.223870 TX DQ/DQS : PASS
6991 23:49:26.227101 RX DATLAT : PASS
6992 23:49:26.227178 RX DQ/DQS(Engine): PASS
6993 23:49:26.230380 TX OE : NO K
6994 23:49:26.230454 All Pass.
6995 23:49:26.230515
6996 23:49:26.234316 CH 0, Rank 1
6997 23:49:26.234388 SW Impedance : PASS
6998 23:49:26.237296 DUTY Scan : NO K
6999 23:49:26.237371 ZQ Calibration : PASS
7000 23:49:26.240633 Jitter Meter : NO K
7001 23:49:26.243916 CBT Training : PASS
7002 23:49:26.243990 Write leveling : NO K
7003 23:49:26.247199 RX DQS gating : PASS
7004 23:49:26.250513 RX DQ/DQS(RDDQC) : PASS
7005 23:49:26.250588 TX DQ/DQS : PASS
7006 23:49:26.254246 RX DATLAT : PASS
7007 23:49:26.257273 RX DQ/DQS(Engine): PASS
7008 23:49:26.257346 TX OE : NO K
7009 23:49:26.260817 All Pass.
7010 23:49:26.260894
7011 23:49:26.260957 CH 1, Rank 0
7012 23:49:26.264282 SW Impedance : PASS
7013 23:49:26.264381 DUTY Scan : NO K
7014 23:49:26.267032 ZQ Calibration : PASS
7015 23:49:26.270417 Jitter Meter : NO K
7016 23:49:26.270492 CBT Training : PASS
7017 23:49:26.273830 Write leveling : PASS
7018 23:49:26.277117 RX DQS gating : PASS
7019 23:49:26.277192 RX DQ/DQS(RDDQC) : PASS
7020 23:49:26.280472 TX DQ/DQS : PASS
7021 23:49:26.280573 RX DATLAT : PASS
7022 23:49:26.283969 RX DQ/DQS(Engine): PASS
7023 23:49:26.287410 TX OE : NO K
7024 23:49:26.287483 All Pass.
7025 23:49:26.287544
7026 23:49:26.287602 CH 1, Rank 1
7027 23:49:26.290271 SW Impedance : PASS
7028 23:49:26.293508 DUTY Scan : NO K
7029 23:49:26.293609 ZQ Calibration : PASS
7030 23:49:26.296853 Jitter Meter : NO K
7031 23:49:26.300479 CBT Training : PASS
7032 23:49:26.300584 Write leveling : NO K
7033 23:49:26.303647 RX DQS gating : PASS
7034 23:49:26.306913 RX DQ/DQS(RDDQC) : PASS
7035 23:49:26.307018 TX DQ/DQS : PASS
7036 23:49:26.310205 RX DATLAT : PASS
7037 23:49:26.314003 RX DQ/DQS(Engine): PASS
7038 23:49:26.314080 TX OE : NO K
7039 23:49:26.314144 All Pass.
7040 23:49:26.317223
7041 23:49:26.317300 DramC Write-DBI off
7042 23:49:26.320450 PER_BANK_REFRESH: Hybrid Mode
7043 23:49:26.320528 TX_TRACKING: ON
7044 23:49:26.330251 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7045 23:49:26.333456 [FAST_K] Save calibration result to emmc
7046 23:49:26.336903 dramc_set_vcore_voltage set vcore to 725000
7047 23:49:26.340316 Read voltage for 1600, 0
7048 23:49:26.340436 Vio18 = 0
7049 23:49:26.343958 Vcore = 725000
7050 23:49:26.344031 Vdram = 0
7051 23:49:26.344092 Vddq = 0
7052 23:49:26.344151 Vmddr = 0
7053 23:49:26.350111 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7054 23:49:26.357195 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7055 23:49:26.357276 MEM_TYPE=3, freq_sel=13
7056 23:49:26.360603 sv_algorithm_assistance_LP4_3733
7057 23:49:26.363516 ============ PULL DRAM RESETB DOWN ============
7058 23:49:26.370339 ========== PULL DRAM RESETB DOWN end =========
7059 23:49:26.373977 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7060 23:49:26.376580 ===================================
7061 23:49:26.379874 LPDDR4 DRAM CONFIGURATION
7062 23:49:26.383807 ===================================
7063 23:49:26.383886 EX_ROW_EN[0] = 0x0
7064 23:49:26.386552 EX_ROW_EN[1] = 0x0
7065 23:49:26.386636 LP4Y_EN = 0x0
7066 23:49:26.389934 WORK_FSP = 0x1
7067 23:49:26.393272 WL = 0x5
7068 23:49:26.393377 RL = 0x5
7069 23:49:26.396682 BL = 0x2
7070 23:49:26.396765 RPST = 0x0
7071 23:49:26.400084 RD_PRE = 0x0
7072 23:49:26.400212 WR_PRE = 0x1
7073 23:49:26.403496 WR_PST = 0x1
7074 23:49:26.403602 DBI_WR = 0x0
7075 23:49:26.406943 DBI_RD = 0x0
7076 23:49:26.407058 OTF = 0x1
7077 23:49:26.410120 ===================================
7078 23:49:26.413441 ===================================
7079 23:49:26.416198 ANA top config
7080 23:49:26.420013 ===================================
7081 23:49:26.420092 DLL_ASYNC_EN = 0
7082 23:49:26.423222 ALL_SLAVE_EN = 0
7083 23:49:26.426510 NEW_RANK_MODE = 1
7084 23:49:26.429862 DLL_IDLE_MODE = 1
7085 23:49:26.433217 LP45_APHY_COMB_EN = 1
7086 23:49:26.433322 TX_ODT_DIS = 0
7087 23:49:26.436513 NEW_8X_MODE = 1
7088 23:49:26.439819 ===================================
7089 23:49:26.443280 ===================================
7090 23:49:26.446053 data_rate = 3200
7091 23:49:26.449429 CKR = 1
7092 23:49:26.453283 DQ_P2S_RATIO = 8
7093 23:49:26.456300 ===================================
7094 23:49:26.456428 CA_P2S_RATIO = 8
7095 23:49:26.459880 DQ_CA_OPEN = 0
7096 23:49:26.462652 DQ_SEMI_OPEN = 0
7097 23:49:26.466400 CA_SEMI_OPEN = 0
7098 23:49:26.469644 CA_FULL_RATE = 0
7099 23:49:26.472973 DQ_CKDIV4_EN = 0
7100 23:49:26.473090 CA_CKDIV4_EN = 0
7101 23:49:26.476394 CA_PREDIV_EN = 0
7102 23:49:26.479571 PH8_DLY = 12
7103 23:49:26.482758 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7104 23:49:26.485879 DQ_AAMCK_DIV = 4
7105 23:49:26.489704 CA_AAMCK_DIV = 4
7106 23:49:26.489797 CA_ADMCK_DIV = 4
7107 23:49:26.492469 DQ_TRACK_CA_EN = 0
7108 23:49:26.495838 CA_PICK = 1600
7109 23:49:26.499308 CA_MCKIO = 1600
7110 23:49:26.502658 MCKIO_SEMI = 0
7111 23:49:26.506184 PLL_FREQ = 3068
7112 23:49:26.509513 DQ_UI_PI_RATIO = 32
7113 23:49:26.512458 CA_UI_PI_RATIO = 0
7114 23:49:26.515617 ===================================
7115 23:49:26.519441 ===================================
7116 23:49:26.519544 memory_type:LPDDR4
7117 23:49:26.522187 GP_NUM : 10
7118 23:49:26.525506 SRAM_EN : 1
7119 23:49:26.525609 MD32_EN : 0
7120 23:49:26.529299 ===================================
7121 23:49:26.532502 [ANA_INIT] >>>>>>>>>>>>>>
7122 23:49:26.535900 <<<<<< [CONFIGURE PHASE]: ANA_TX
7123 23:49:26.539055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7124 23:49:26.542317 ===================================
7125 23:49:26.545790 data_rate = 3200,PCW = 0X7600
7126 23:49:26.549306 ===================================
7127 23:49:26.552675 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7128 23:49:26.555380 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 23:49:26.562142 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 23:49:26.565403 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7131 23:49:26.569058 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7132 23:49:26.572011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7133 23:49:26.575547 [ANA_INIT] flow start
7134 23:49:26.578890 [ANA_INIT] PLL >>>>>>>>
7135 23:49:26.578997 [ANA_INIT] PLL <<<<<<<<
7136 23:49:26.582085 [ANA_INIT] MIDPI >>>>>>>>
7137 23:49:26.585323 [ANA_INIT] MIDPI <<<<<<<<
7138 23:49:26.585427 [ANA_INIT] DLL >>>>>>>>
7139 23:49:26.588498 [ANA_INIT] DLL <<<<<<<<
7140 23:49:26.592320 [ANA_INIT] flow end
7141 23:49:26.595522 ============ LP4 DIFF to SE enter ============
7142 23:49:26.598635 ============ LP4 DIFF to SE exit ============
7143 23:49:26.601850 [ANA_INIT] <<<<<<<<<<<<<
7144 23:49:26.605642 [Flow] Enable top DCM control >>>>>
7145 23:49:26.608463 [Flow] Enable top DCM control <<<<<
7146 23:49:26.611821 Enable DLL master slave shuffle
7147 23:49:26.615223 ==============================================================
7148 23:49:26.618647 Gating Mode config
7149 23:49:26.625103 ==============================================================
7150 23:49:26.625209 Config description:
7151 23:49:26.635180 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7152 23:49:26.641823 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7153 23:49:26.648534 SELPH_MODE 0: By rank 1: By Phase
7154 23:49:26.651948 ==============================================================
7155 23:49:26.655418 GAT_TRACK_EN = 1
7156 23:49:26.658821 RX_GATING_MODE = 2
7157 23:49:26.662214 RX_GATING_TRACK_MODE = 2
7158 23:49:26.665501 SELPH_MODE = 1
7159 23:49:26.668226 PICG_EARLY_EN = 1
7160 23:49:26.671640 VALID_LAT_VALUE = 1
7161 23:49:26.674964 ==============================================================
7162 23:49:26.678423 Enter into Gating configuration >>>>
7163 23:49:26.681768 Exit from Gating configuration <<<<
7164 23:49:26.685064 Enter into DVFS_PRE_config >>>>>
7165 23:49:26.698308 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7166 23:49:26.701327 Exit from DVFS_PRE_config <<<<<
7167 23:49:26.701439 Enter into PICG configuration >>>>
7168 23:49:26.705084 Exit from PICG configuration <<<<
7169 23:49:26.708294 [RX_INPUT] configuration >>>>>
7170 23:49:26.711361 [RX_INPUT] configuration <<<<<
7171 23:49:26.718161 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7172 23:49:26.721243 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7173 23:49:26.727997 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 23:49:26.734787 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 23:49:26.741666 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 23:49:26.747900 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 23:49:26.751202 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7178 23:49:26.754689 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7179 23:49:26.758015 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7180 23:49:26.765113 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7181 23:49:26.768279 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7182 23:49:26.771797 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7183 23:49:26.774500 ===================================
7184 23:49:26.777916 LPDDR4 DRAM CONFIGURATION
7185 23:49:26.781349 ===================================
7186 23:49:26.781431 EX_ROW_EN[0] = 0x0
7187 23:49:26.784804 EX_ROW_EN[1] = 0x0
7188 23:49:26.788135 LP4Y_EN = 0x0
7189 23:49:26.788209 WORK_FSP = 0x1
7190 23:49:26.791534 WL = 0x5
7191 23:49:26.791610 RL = 0x5
7192 23:49:26.795035 BL = 0x2
7193 23:49:26.795113 RPST = 0x0
7194 23:49:26.798263 RD_PRE = 0x0
7195 23:49:26.798337 WR_PRE = 0x1
7196 23:49:26.801667 WR_PST = 0x1
7197 23:49:26.801759 DBI_WR = 0x0
7198 23:49:26.804568 DBI_RD = 0x0
7199 23:49:26.804715 OTF = 0x1
7200 23:49:26.808083 ===================================
7201 23:49:26.811629 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7202 23:49:26.818504 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7203 23:49:26.821534 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 23:49:26.824749 ===================================
7205 23:49:26.828131 LPDDR4 DRAM CONFIGURATION
7206 23:49:26.831592 ===================================
7207 23:49:26.831673 EX_ROW_EN[0] = 0x10
7208 23:49:26.834662 EX_ROW_EN[1] = 0x0
7209 23:49:26.834743 LP4Y_EN = 0x0
7210 23:49:26.838345 WORK_FSP = 0x1
7211 23:49:26.841285 WL = 0x5
7212 23:49:26.841366 RL = 0x5
7213 23:49:26.844820 BL = 0x2
7214 23:49:26.844903 RPST = 0x0
7215 23:49:26.847901 RD_PRE = 0x0
7216 23:49:26.847983 WR_PRE = 0x1
7217 23:49:26.851512 WR_PST = 0x1
7218 23:49:26.851600 DBI_WR = 0x0
7219 23:49:26.854720 DBI_RD = 0x0
7220 23:49:26.854801 OTF = 0x1
7221 23:49:26.857758 ===================================
7222 23:49:26.864795 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7223 23:49:26.864879 ==
7224 23:49:26.868113 Dram Type= 6, Freq= 0, CH_0, rank 0
7225 23:49:26.871460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7226 23:49:26.871543 ==
7227 23:49:26.874282 [Duty_Offset_Calibration]
7228 23:49:26.877677 B0:2 B1:1 CA:1
7229 23:49:26.877759
7230 23:49:26.881066 [DutyScan_Calibration_Flow] k_type=0
7231 23:49:26.889943
7232 23:49:26.890025 ==CLK 0==
7233 23:49:26.893338 Final CLK duty delay cell = 0
7234 23:49:26.896673 [0] MAX Duty = 5156%(X100), DQS PI = 22
7235 23:49:26.899349 [0] MIN Duty = 4907%(X100), DQS PI = 0
7236 23:49:26.899431 [0] AVG Duty = 5031%(X100)
7237 23:49:26.902770
7238 23:49:26.906149 CH0 CLK Duty spec in!! Max-Min= 249%
7239 23:49:26.909431 [DutyScan_Calibration_Flow] ====Done====
7240 23:49:26.909513
7241 23:49:26.912681 [DutyScan_Calibration_Flow] k_type=1
7242 23:49:26.928907
7243 23:49:26.929002 ==DQS 0 ==
7244 23:49:26.932283 Final DQS duty delay cell = -4
7245 23:49:26.935078 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7246 23:49:26.938537 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7247 23:49:26.942040 [-4] AVG Duty = 4891%(X100)
7248 23:49:26.942116
7249 23:49:26.942178 ==DQS 1 ==
7250 23:49:26.945206 Final DQS duty delay cell = 0
7251 23:49:26.948269 [0] MAX Duty = 5187%(X100), DQS PI = 20
7252 23:49:26.952036 [0] MIN Duty = 5031%(X100), DQS PI = 50
7253 23:49:26.955666 [0] AVG Duty = 5109%(X100)
7254 23:49:26.955749
7255 23:49:26.958774 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7256 23:49:26.958855
7257 23:49:26.962249 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7258 23:49:26.965268 [DutyScan_Calibration_Flow] ====Done====
7259 23:49:26.965351
7260 23:49:26.968748 [DutyScan_Calibration_Flow] k_type=3
7261 23:49:26.986234
7262 23:49:26.986339 ==DQM 0 ==
7263 23:49:26.989752 Final DQM duty delay cell = 0
7264 23:49:26.993160 [0] MAX Duty = 5187%(X100), DQS PI = 28
7265 23:49:26.995860 [0] MIN Duty = 4844%(X100), DQS PI = 60
7266 23:49:26.999419 [0] AVG Duty = 5015%(X100)
7267 23:49:26.999552
7268 23:49:26.999618 ==DQM 1 ==
7269 23:49:27.002684 Final DQM duty delay cell = 0
7270 23:49:27.006109 [0] MAX Duty = 5187%(X100), DQS PI = 6
7271 23:49:27.009337 [0] MIN Duty = 5031%(X100), DQS PI = 50
7272 23:49:27.012617 [0] AVG Duty = 5109%(X100)
7273 23:49:27.012703
7274 23:49:27.016015 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7275 23:49:27.016115
7276 23:49:27.019324 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7277 23:49:27.022635 [DutyScan_Calibration_Flow] ====Done====
7278 23:49:27.022720
7279 23:49:27.025850 [DutyScan_Calibration_Flow] k_type=2
7280 23:49:27.043583
7281 23:49:27.043680 ==DQ 0 ==
7282 23:49:27.047073 Final DQ duty delay cell = 0
7283 23:49:27.049814 [0] MAX Duty = 5062%(X100), DQS PI = 24
7284 23:49:27.053293 [0] MIN Duty = 4907%(X100), DQS PI = 0
7285 23:49:27.053384 [0] AVG Duty = 4984%(X100)
7286 23:49:27.053452
7287 23:49:27.056901 ==DQ 1 ==
7288 23:49:27.060198 Final DQ duty delay cell = 0
7289 23:49:27.063356 [0] MAX Duty = 5156%(X100), DQS PI = 22
7290 23:49:27.067088 [0] MIN Duty = 4907%(X100), DQS PI = 34
7291 23:49:27.067173 [0] AVG Duty = 5031%(X100)
7292 23:49:27.067239
7293 23:49:27.070243 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7294 23:49:27.070328
7295 23:49:27.073356 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7296 23:49:27.080014 [DutyScan_Calibration_Flow] ====Done====
7297 23:49:27.080101 ==
7298 23:49:27.083077 Dram Type= 6, Freq= 0, CH_1, rank 0
7299 23:49:27.086805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 23:49:27.086893 ==
7301 23:49:27.089689 [Duty_Offset_Calibration]
7302 23:49:27.089774 B0:1 B1:0 CA:0
7303 23:49:27.089840
7304 23:49:27.093570 [DutyScan_Calibration_Flow] k_type=0
7305 23:49:27.103000
7306 23:49:27.103094 ==CLK 0==
7307 23:49:27.105747 Final CLK duty delay cell = -4
7308 23:49:27.109219 [-4] MAX Duty = 4969%(X100), DQS PI = 28
7309 23:49:27.113130 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7310 23:49:27.116266 [-4] AVG Duty = 4906%(X100)
7311 23:49:27.116360
7312 23:49:27.119662 CH1 CLK Duty spec in!! Max-Min= 125%
7313 23:49:27.122501 [DutyScan_Calibration_Flow] ====Done====
7314 23:49:27.122583
7315 23:49:27.126107 [DutyScan_Calibration_Flow] k_type=1
7316 23:49:27.142950
7317 23:49:27.143037 ==DQS 0 ==
7318 23:49:27.145950 Final DQS duty delay cell = 0
7319 23:49:27.149400 [0] MAX Duty = 5094%(X100), DQS PI = 46
7320 23:49:27.152738 [0] MIN Duty = 4875%(X100), DQS PI = 10
7321 23:49:27.156113 [0] AVG Duty = 4984%(X100)
7322 23:49:27.156195
7323 23:49:27.156259 ==DQS 1 ==
7324 23:49:27.159535 Final DQS duty delay cell = 0
7325 23:49:27.162836 [0] MAX Duty = 5249%(X100), DQS PI = 48
7326 23:49:27.166300 [0] MIN Duty = 4907%(X100), DQS PI = 40
7327 23:49:27.169106 [0] AVG Duty = 5078%(X100)
7328 23:49:27.169189
7329 23:49:27.172361 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7330 23:49:27.172458
7331 23:49:27.176255 CH1 DQS 1 Duty spec in!! Max-Min= 342%
7332 23:49:27.178971 [DutyScan_Calibration_Flow] ====Done====
7333 23:49:27.179159
7334 23:49:27.182290 [DutyScan_Calibration_Flow] k_type=3
7335 23:49:27.199808
7336 23:49:27.199903 ==DQM 0 ==
7337 23:49:27.203200 Final DQM duty delay cell = 0
7338 23:49:27.206481 [0] MAX Duty = 5187%(X100), DQS PI = 40
7339 23:49:27.209521 [0] MIN Duty = 5031%(X100), DQS PI = 14
7340 23:49:27.212924 [0] AVG Duty = 5109%(X100)
7341 23:49:27.213031
7342 23:49:27.213126 ==DQM 1 ==
7343 23:49:27.216285 Final DQM duty delay cell = 0
7344 23:49:27.219596 [0] MAX Duty = 5093%(X100), DQS PI = 10
7345 23:49:27.222734 [0] MIN Duty = 4907%(X100), DQS PI = 0
7346 23:49:27.226133 [0] AVG Duty = 5000%(X100)
7347 23:49:27.226296
7348 23:49:27.229446 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7349 23:49:27.229552
7350 23:49:27.232854 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7351 23:49:27.236385 [DutyScan_Calibration_Flow] ====Done====
7352 23:49:27.236493
7353 23:49:27.239796 [DutyScan_Calibration_Flow] k_type=2
7354 23:49:27.255564
7355 23:49:27.255688 ==DQ 0 ==
7356 23:49:27.259131 Final DQ duty delay cell = -4
7357 23:49:27.262597 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7358 23:49:27.265934 [-4] MIN Duty = 4875%(X100), DQS PI = 6
7359 23:49:27.268680 [-4] AVG Duty = 4953%(X100)
7360 23:49:27.268781
7361 23:49:27.268878 ==DQ 1 ==
7362 23:49:27.272188 Final DQ duty delay cell = 0
7363 23:49:27.275325 [0] MAX Duty = 5125%(X100), DQS PI = 10
7364 23:49:27.278702 [0] MIN Duty = 4938%(X100), DQS PI = 0
7365 23:49:27.278805 [0] AVG Duty = 5031%(X100)
7366 23:49:27.282112
7367 23:49:27.285428 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7368 23:49:27.285505
7369 23:49:27.288849 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7370 23:49:27.291836 [DutyScan_Calibration_Flow] ====Done====
7371 23:49:27.295788 nWR fixed to 30
7372 23:49:27.295897 [ModeRegInit_LP4] CH0 RK0
7373 23:49:27.298885 [ModeRegInit_LP4] CH0 RK1
7374 23:49:27.302093 [ModeRegInit_LP4] CH1 RK0
7375 23:49:27.305560 [ModeRegInit_LP4] CH1 RK1
7376 23:49:27.305665 match AC timing 5
7377 23:49:27.312180 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7378 23:49:27.315428 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7379 23:49:27.318421 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7380 23:49:27.325278 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7381 23:49:27.328425 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7382 23:49:27.328528 [MiockJmeterHQA]
7383 23:49:27.328621
7384 23:49:27.331757 [DramcMiockJmeter] u1RxGatingPI = 0
7385 23:49:27.335194 0 : 4368, 4140
7386 23:49:27.335301 4 : 4252, 4027
7387 23:49:27.338550 8 : 4363, 4137
7388 23:49:27.338653 12 : 4250, 4027
7389 23:49:27.338750 16 : 4253, 4027
7390 23:49:27.342202 20 : 4363, 4137
7391 23:49:27.342301 24 : 4360, 4138
7392 23:49:27.345395 28 : 4252, 4026
7393 23:49:27.345484 32 : 4252, 4027
7394 23:49:27.348625 36 : 4252, 4027
7395 23:49:27.348702 40 : 4253, 4026
7396 23:49:27.352021 44 : 4255, 4030
7397 23:49:27.352128 48 : 4360, 4137
7398 23:49:27.352225 52 : 4252, 4027
7399 23:49:27.355368 56 : 4250, 4026
7400 23:49:27.355475 60 : 4252, 4026
7401 23:49:27.358597 64 : 4252, 4030
7402 23:49:27.358713 68 : 4250, 4026
7403 23:49:27.361764 72 : 4363, 4137
7404 23:49:27.361875 76 : 4360, 4138
7405 23:49:27.365077 80 : 4250, 4026
7406 23:49:27.365154 84 : 4250, 4027
7407 23:49:27.365218 88 : 4250, 61
7408 23:49:27.368458 92 : 4253, 0
7409 23:49:27.368557 96 : 4250, 0
7410 23:49:27.368650 100 : 4249, 0
7411 23:49:27.371894 104 : 4250, 0
7412 23:49:27.371992 108 : 4252, 0
7413 23:49:27.375024 112 : 4361, 0
7414 23:49:27.375131 116 : 4250, 0
7415 23:49:27.375224 120 : 4250, 0
7416 23:49:27.378456 124 : 4360, 0
7417 23:49:27.378556 128 : 4250, 0
7418 23:49:27.381815 132 : 4360, 0
7419 23:49:27.381916 136 : 4250, 0
7420 23:49:27.382056 140 : 4250, 0
7421 23:49:27.385200 144 : 4249, 0
7422 23:49:27.385302 148 : 4252, 0
7423 23:49:27.388555 152 : 4250, 0
7424 23:49:27.388668 156 : 4250, 0
7425 23:49:27.388766 160 : 4253, 0
7426 23:49:27.391927 164 : 4361, 0
7427 23:49:27.392040 168 : 4360, 0
7428 23:49:27.392136 172 : 4363, 0
7429 23:49:27.395185 176 : 4360, 0
7430 23:49:27.395295 180 : 4250, 0
7431 23:49:27.398215 184 : 4361, 0
7432 23:49:27.398318 188 : 4250, 0
7433 23:49:27.398417 192 : 4250, 0
7434 23:49:27.401640 196 : 4249, 0
7435 23:49:27.401724 200 : 4252, 0
7436 23:49:27.404837 204 : 4250, 1292
7437 23:49:27.404947 208 : 4250, 4002
7438 23:49:27.408002 212 : 4363, 4140
7439 23:49:27.408114 216 : 4250, 4026
7440 23:49:27.411552 220 : 4250, 4026
7441 23:49:27.411623 224 : 4250, 4027
7442 23:49:27.411690 228 : 4252, 4030
7443 23:49:27.414552 232 : 4250, 4026
7444 23:49:27.414660 236 : 4250, 4026
7445 23:49:27.417905 240 : 4361, 4137
7446 23:49:27.418007 244 : 4250, 4027
7447 23:49:27.421858 248 : 4250, 4027
7448 23:49:27.421961 252 : 4361, 4137
7449 23:49:27.425077 256 : 4250, 4026
7450 23:49:27.425156 260 : 4250, 4027
7451 23:49:27.428237 264 : 4363, 4140
7452 23:49:27.428358 268 : 4250, 4027
7453 23:49:27.431182 272 : 4250, 4026
7454 23:49:27.431287 276 : 4250, 4027
7455 23:49:27.434535 280 : 4253, 4029
7456 23:49:27.434638 284 : 4250, 4027
7457 23:49:27.434731 288 : 4250, 4026
7458 23:49:27.437825 292 : 4361, 4137
7459 23:49:27.437927 296 : 4250, 4027
7460 23:49:27.441403 300 : 4250, 4026
7461 23:49:27.441508 304 : 4361, 4137
7462 23:49:27.444552 308 : 4250, 3943
7463 23:49:27.444657 312 : 4250, 1822
7464 23:49:27.444753
7465 23:49:27.448050 MIOCK jitter meter ch=0
7466 23:49:27.448150
7467 23:49:27.451196 1T = (312-88) = 224 dly cells
7468 23:49:27.458077 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7469 23:49:27.458180 ==
7470 23:49:27.461367 Dram Type= 6, Freq= 0, CH_0, rank 0
7471 23:49:27.464570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7472 23:49:27.464677 ==
7473 23:49:27.471086 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7474 23:49:27.474492 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7475 23:49:27.477890 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7476 23:49:27.484629 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7477 23:49:27.493529 [CA 0] Center 42 (12~73) winsize 62
7478 23:49:27.496835 [CA 1] Center 42 (12~73) winsize 62
7479 23:49:27.499752 [CA 2] Center 37 (8~67) winsize 60
7480 23:49:27.502874 [CA 3] Center 37 (7~67) winsize 61
7481 23:49:27.506290 [CA 4] Center 36 (6~66) winsize 61
7482 23:49:27.509638 [CA 5] Center 35 (6~64) winsize 59
7483 23:49:27.509739
7484 23:49:27.512886 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7485 23:49:27.512985
7486 23:49:27.516490 [CATrainingPosCal] consider 1 rank data
7487 23:49:27.519543 u2DelayCellTimex100 = 290/100 ps
7488 23:49:27.522774 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7489 23:49:27.529692 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7490 23:49:27.533214 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7491 23:49:27.536730 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7492 23:49:27.539403 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7493 23:49:27.543172 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7494 23:49:27.543293
7495 23:49:27.546220 CA PerBit enable=1, Macro0, CA PI delay=35
7496 23:49:27.546320
7497 23:49:27.549796 [CBTSetCACLKResult] CA Dly = 35
7498 23:49:27.552761 CS Dly: 9 (0~40)
7499 23:49:27.556684 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7500 23:49:27.559688 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7501 23:49:27.559796 ==
7502 23:49:27.562787 Dram Type= 6, Freq= 0, CH_0, rank 1
7503 23:49:27.566227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 23:49:27.566341 ==
7505 23:49:27.572814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 23:49:27.576185 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 23:49:27.583041 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 23:49:27.586428 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 23:49:27.596694 [CA 0] Center 42 (12~73) winsize 62
7510 23:49:27.599905 [CA 1] Center 42 (12~73) winsize 62
7511 23:49:27.603089 [CA 2] Center 38 (8~68) winsize 61
7512 23:49:27.606387 [CA 3] Center 38 (8~68) winsize 61
7513 23:49:27.609662 [CA 4] Center 36 (6~66) winsize 61
7514 23:49:27.613002 [CA 5] Center 35 (5~65) winsize 61
7515 23:49:27.613116
7516 23:49:27.616554 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7517 23:49:27.616633
7518 23:49:27.619901 [CATrainingPosCal] consider 2 rank data
7519 23:49:27.623205 u2DelayCellTimex100 = 290/100 ps
7520 23:49:27.626541 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7521 23:49:27.633249 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7522 23:49:27.636521 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7523 23:49:27.639485 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7524 23:49:27.643267 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7525 23:49:27.646086 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7526 23:49:27.646190
7527 23:49:27.649503 CA PerBit enable=1, Macro0, CA PI delay=35
7528 23:49:27.649605
7529 23:49:27.653081 [CBTSetCACLKResult] CA Dly = 35
7530 23:49:27.656166 CS Dly: 10 (0~42)
7531 23:49:27.659418 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 23:49:27.662970 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 23:49:27.663073
7534 23:49:27.666343 ----->DramcWriteLeveling(PI) begin...
7535 23:49:27.666448 ==
7536 23:49:27.669274 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 23:49:27.672714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 23:49:27.676254 ==
7539 23:49:27.679380 Write leveling (Byte 0): 35 => 35
7540 23:49:27.679483 Write leveling (Byte 1): 26 => 26
7541 23:49:27.682393 DramcWriteLeveling(PI) end<-----
7542 23:49:27.682488
7543 23:49:27.682559 ==
7544 23:49:27.686350 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 23:49:27.692701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 23:49:27.692810 ==
7547 23:49:27.695760 [Gating] SW mode calibration
7548 23:49:27.702639 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7549 23:49:27.706003 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7550 23:49:27.712830 1 4 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7551 23:49:27.715856 1 4 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7552 23:49:27.719197 1 4 8 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7553 23:49:27.722578 1 4 12 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (1 1)
7554 23:49:27.729568 1 4 16 | B1->B0 | 2323 3b3a | 0 1 | (0 0) (0 0)
7555 23:49:27.733035 1 4 20 | B1->B0 | 3434 3939 | 1 1 | (1 1) (0 0)
7556 23:49:27.736358 1 4 24 | B1->B0 | 3434 3939 | 1 0 | (1 1) (1 1)
7557 23:49:27.742898 1 4 28 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (1 1)
7558 23:49:27.746271 1 5 0 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)
7559 23:49:27.749505 1 5 4 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7560 23:49:27.756017 1 5 8 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7561 23:49:27.759319 1 5 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
7562 23:49:27.762640 1 5 16 | B1->B0 | 3434 3231 | 1 1 | (1 0) (0 0)
7563 23:49:27.769416 1 5 20 | B1->B0 | 2525 2d2d | 0 1 | (1 0) (0 0)
7564 23:49:27.772193 1 5 24 | B1->B0 | 2323 2929 | 0 1 | (1 0) (0 0)
7565 23:49:27.776040 1 5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7566 23:49:27.782464 1 6 0 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
7567 23:49:27.786047 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7568 23:49:27.789418 1 6 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
7569 23:49:27.795727 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7570 23:49:27.799399 1 6 16 | B1->B0 | 2c2c 4645 | 0 1 | (0 0) (0 0)
7571 23:49:27.802485 1 6 20 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)
7572 23:49:27.809148 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 23:49:27.812690 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 23:49:27.815434 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 23:49:27.822514 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 23:49:27.825604 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 23:49:27.828820 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7578 23:49:27.835681 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7579 23:49:27.838924 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7580 23:49:27.842471 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7581 23:49:27.849225 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 23:49:27.852586 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 23:49:27.855368 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 23:49:27.861834 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 23:49:27.865130 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 23:49:27.868564 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 23:49:27.871893 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 23:49:27.878800 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 23:49:27.882238 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 23:49:27.885535 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 23:49:27.892343 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 23:49:27.895501 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 23:49:27.898558 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 23:49:27.905662 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7595 23:49:27.908794 Total UI for P1: 0, mck2ui 16
7596 23:49:27.911965 best dqsien dly found for B0: ( 1, 9, 12)
7597 23:49:27.915466 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7598 23:49:27.918663 Total UI for P1: 0, mck2ui 16
7599 23:49:27.922041 best dqsien dly found for B1: ( 1, 9, 18)
7600 23:49:27.925410 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7601 23:49:27.928585 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7602 23:49:27.928667
7603 23:49:27.931934 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7604 23:49:27.935043 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7605 23:49:27.938226 [Gating] SW calibration Done
7606 23:49:27.938336 ==
7607 23:49:27.941674 Dram Type= 6, Freq= 0, CH_0, rank 0
7608 23:49:27.949145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7609 23:49:27.949254 ==
7610 23:49:27.949352 RX Vref Scan: 0
7611 23:49:27.949442
7612 23:49:27.951630 RX Vref 0 -> 0, step: 1
7613 23:49:27.951731
7614 23:49:27.955023 RX Delay 0 -> 252, step: 8
7615 23:49:27.958446 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7616 23:49:27.961783 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7617 23:49:27.965020 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7618 23:49:27.968902 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7619 23:49:27.975698 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7620 23:49:27.978859 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7621 23:49:27.982292 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7622 23:49:27.984988 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7623 23:49:27.988277 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7624 23:49:27.992251 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7625 23:49:27.998765 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7626 23:49:28.001951 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7627 23:49:28.005236 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7628 23:49:28.008286 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7629 23:49:28.011783 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7630 23:49:28.018308 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7631 23:49:28.018391 ==
7632 23:49:28.022065 Dram Type= 6, Freq= 0, CH_0, rank 0
7633 23:49:28.025129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7634 23:49:28.025229 ==
7635 23:49:28.025295 DQS Delay:
7636 23:49:28.028224 DQS0 = 0, DQS1 = 0
7637 23:49:28.028307 DQM Delay:
7638 23:49:28.031471 DQM0 = 137, DQM1 = 129
7639 23:49:28.031553 DQ Delay:
7640 23:49:28.035038 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =135
7641 23:49:28.038407 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7642 23:49:28.041726 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7643 23:49:28.044880 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
7644 23:49:28.048201
7645 23:49:28.048322
7646 23:49:28.048442 ==
7647 23:49:28.051681 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 23:49:28.055156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 23:49:28.055275 ==
7650 23:49:28.055374
7651 23:49:28.055463
7652 23:49:28.058239 TX Vref Scan disable
7653 23:49:28.058340 == TX Byte 0 ==
7654 23:49:28.064839 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7655 23:49:28.068535 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7656 23:49:28.068646 == TX Byte 1 ==
7657 23:49:28.075175 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7658 23:49:28.078339 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7659 23:49:28.078441 ==
7660 23:49:28.081231 Dram Type= 6, Freq= 0, CH_0, rank 0
7661 23:49:28.084573 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7662 23:49:28.084647 ==
7663 23:49:28.099221
7664 23:49:28.102482 TX Vref early break, caculate TX vref
7665 23:49:28.106030 TX Vref=16, minBit 0, minWin=23, winSum=378
7666 23:49:28.109372 TX Vref=18, minBit 3, minWin=23, winSum=390
7667 23:49:28.112431 TX Vref=20, minBit 0, minWin=24, winSum=402
7668 23:49:28.115879 TX Vref=22, minBit 1, minWin=24, winSum=410
7669 23:49:28.119194 TX Vref=24, minBit 4, minWin=24, winSum=414
7670 23:49:28.125560 TX Vref=26, minBit 2, minWin=25, winSum=426
7671 23:49:28.129153 TX Vref=28, minBit 1, minWin=25, winSum=420
7672 23:49:28.132271 TX Vref=30, minBit 1, minWin=24, winSum=411
7673 23:49:28.135930 TX Vref=32, minBit 6, minWin=23, winSum=404
7674 23:49:28.138948 TX Vref=34, minBit 2, minWin=23, winSum=394
7675 23:49:28.145485 [TxChooseVref] Worse bit 2, Min win 25, Win sum 426, Final Vref 26
7676 23:49:28.145566
7677 23:49:28.149311 Final TX Range 0 Vref 26
7678 23:49:28.149393
7679 23:49:28.149458 ==
7680 23:49:28.152443 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 23:49:28.155783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 23:49:28.155867 ==
7683 23:49:28.155933
7684 23:49:28.156006
7685 23:49:28.159011 TX Vref Scan disable
7686 23:49:28.165610 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7687 23:49:28.165693 == TX Byte 0 ==
7688 23:49:28.168966 u2DelayCellOfst[0]=10 cells (3 PI)
7689 23:49:28.172379 u2DelayCellOfst[1]=13 cells (4 PI)
7690 23:49:28.175794 u2DelayCellOfst[2]=10 cells (3 PI)
7691 23:49:28.179103 u2DelayCellOfst[3]=10 cells (3 PI)
7692 23:49:28.182451 u2DelayCellOfst[4]=6 cells (2 PI)
7693 23:49:28.185879 u2DelayCellOfst[5]=0 cells (0 PI)
7694 23:49:28.189047 u2DelayCellOfst[6]=16 cells (5 PI)
7695 23:49:28.192533 u2DelayCellOfst[7]=16 cells (5 PI)
7696 23:49:28.195958 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7697 23:49:28.199274 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7698 23:49:28.202602 == TX Byte 1 ==
7699 23:49:28.202686 u2DelayCellOfst[8]=3 cells (1 PI)
7700 23:49:28.205546 u2DelayCellOfst[9]=0 cells (0 PI)
7701 23:49:28.208930 u2DelayCellOfst[10]=6 cells (2 PI)
7702 23:49:28.212256 u2DelayCellOfst[11]=3 cells (1 PI)
7703 23:49:28.215652 u2DelayCellOfst[12]=10 cells (3 PI)
7704 23:49:28.219307 u2DelayCellOfst[13]=13 cells (4 PI)
7705 23:49:28.222631 u2DelayCellOfst[14]=16 cells (5 PI)
7706 23:49:28.226062 u2DelayCellOfst[15]=10 cells (3 PI)
7707 23:49:28.228819 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7708 23:49:28.235762 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7709 23:49:28.235843 DramC Write-DBI on
7710 23:49:28.235908 ==
7711 23:49:28.238986 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 23:49:28.242215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 23:49:28.242296 ==
7714 23:49:28.245538
7715 23:49:28.245618
7716 23:49:28.245681 TX Vref Scan disable
7717 23:49:28.248682 == TX Byte 0 ==
7718 23:49:28.252390 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7719 23:49:28.255936 == TX Byte 1 ==
7720 23:49:28.258997 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7721 23:49:28.262601 DramC Write-DBI off
7722 23:49:28.262682
7723 23:49:28.262745 [DATLAT]
7724 23:49:28.262803 Freq=1600, CH0 RK0
7725 23:49:28.262861
7726 23:49:28.266041 DATLAT Default: 0xf
7727 23:49:28.266121 0, 0xFFFF, sum = 0
7728 23:49:28.268963 1, 0xFFFF, sum = 0
7729 23:49:28.269045 2, 0xFFFF, sum = 0
7730 23:49:28.272054 3, 0xFFFF, sum = 0
7731 23:49:28.275287 4, 0xFFFF, sum = 0
7732 23:49:28.275368 5, 0xFFFF, sum = 0
7733 23:49:28.278695 6, 0xFFFF, sum = 0
7734 23:49:28.278776 7, 0xFFFF, sum = 0
7735 23:49:28.281976 8, 0xFFFF, sum = 0
7736 23:49:28.282057 9, 0xFFFF, sum = 0
7737 23:49:28.285513 10, 0xFFFF, sum = 0
7738 23:49:28.285594 11, 0xFFFF, sum = 0
7739 23:49:28.288727 12, 0xFFFF, sum = 0
7740 23:49:28.288809 13, 0xFFFF, sum = 0
7741 23:49:28.291911 14, 0x0, sum = 1
7742 23:49:28.291992 15, 0x0, sum = 2
7743 23:49:28.295277 16, 0x0, sum = 3
7744 23:49:28.295358 17, 0x0, sum = 4
7745 23:49:28.298553 best_step = 15
7746 23:49:28.298633
7747 23:49:28.298696 ==
7748 23:49:28.301839 Dram Type= 6, Freq= 0, CH_0, rank 0
7749 23:49:28.305233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7750 23:49:28.305314 ==
7751 23:49:28.305378 RX Vref Scan: 1
7752 23:49:28.308631
7753 23:49:28.308710 Set Vref Range= 24 -> 127
7754 23:49:28.308774
7755 23:49:28.312038 RX Vref 24 -> 127, step: 1
7756 23:49:28.312118
7757 23:49:28.315468 RX Delay 19 -> 252, step: 4
7758 23:49:28.315549
7759 23:49:28.318762 Set Vref, RX VrefLevel [Byte0]: 24
7760 23:49:28.322085 [Byte1]: 24
7761 23:49:28.322165
7762 23:49:28.325477 Set Vref, RX VrefLevel [Byte0]: 25
7763 23:49:28.328878 [Byte1]: 25
7764 23:49:28.328959
7765 23:49:28.331669 Set Vref, RX VrefLevel [Byte0]: 26
7766 23:49:28.335056 [Byte1]: 26
7767 23:49:28.339085
7768 23:49:28.339165 Set Vref, RX VrefLevel [Byte0]: 27
7769 23:49:28.342484 [Byte1]: 27
7770 23:49:28.346528
7771 23:49:28.346608 Set Vref, RX VrefLevel [Byte0]: 28
7772 23:49:28.349810 [Byte1]: 28
7773 23:49:28.354418
7774 23:49:28.354498 Set Vref, RX VrefLevel [Byte0]: 29
7775 23:49:28.357941 [Byte1]: 29
7776 23:49:28.361588
7777 23:49:28.361668 Set Vref, RX VrefLevel [Byte0]: 30
7778 23:49:28.365202 [Byte1]: 30
7779 23:49:28.369453
7780 23:49:28.369533 Set Vref, RX VrefLevel [Byte0]: 31
7781 23:49:28.372497 [Byte1]: 31
7782 23:49:28.376870
7783 23:49:28.376950 Set Vref, RX VrefLevel [Byte0]: 32
7784 23:49:28.380042 [Byte1]: 32
7785 23:49:28.384312
7786 23:49:28.384430 Set Vref, RX VrefLevel [Byte0]: 33
7787 23:49:28.387622 [Byte1]: 33
7788 23:49:28.392477
7789 23:49:28.392560 Set Vref, RX VrefLevel [Byte0]: 34
7790 23:49:28.395326 [Byte1]: 34
7791 23:49:28.400042
7792 23:49:28.400122 Set Vref, RX VrefLevel [Byte0]: 35
7793 23:49:28.403301 [Byte1]: 35
7794 23:49:28.407252
7795 23:49:28.407378 Set Vref, RX VrefLevel [Byte0]: 36
7796 23:49:28.410892 [Byte1]: 36
7797 23:49:28.414949
7798 23:49:28.415044 Set Vref, RX VrefLevel [Byte0]: 37
7799 23:49:28.418272 [Byte1]: 37
7800 23:49:28.422243
7801 23:49:28.422323 Set Vref, RX VrefLevel [Byte0]: 38
7802 23:49:28.425696 [Byte1]: 38
7803 23:49:28.430331
7804 23:49:28.430414 Set Vref, RX VrefLevel [Byte0]: 39
7805 23:49:28.433579 [Byte1]: 39
7806 23:49:28.437789
7807 23:49:28.437905 Set Vref, RX VrefLevel [Byte0]: 40
7808 23:49:28.441247 [Byte1]: 40
7809 23:49:28.445292
7810 23:49:28.445363 Set Vref, RX VrefLevel [Byte0]: 41
7811 23:49:28.448070 [Byte1]: 41
7812 23:49:28.452778
7813 23:49:28.452871 Set Vref, RX VrefLevel [Byte0]: 42
7814 23:49:28.456184 [Byte1]: 42
7815 23:49:28.460269
7816 23:49:28.460407 Set Vref, RX VrefLevel [Byte0]: 43
7817 23:49:28.463715 [Byte1]: 43
7818 23:49:28.467739
7819 23:49:28.467841 Set Vref, RX VrefLevel [Byte0]: 44
7820 23:49:28.470966 [Byte1]: 44
7821 23:49:28.475292
7822 23:49:28.475457 Set Vref, RX VrefLevel [Byte0]: 45
7823 23:49:28.478374 [Byte1]: 45
7824 23:49:28.482705
7825 23:49:28.482807 Set Vref, RX VrefLevel [Byte0]: 46
7826 23:49:28.486523 [Byte1]: 46
7827 23:49:28.490311
7828 23:49:28.490415 Set Vref, RX VrefLevel [Byte0]: 47
7829 23:49:28.494005 [Byte1]: 47
7830 23:49:28.498195
7831 23:49:28.498303 Set Vref, RX VrefLevel [Byte0]: 48
7832 23:49:28.501348 [Byte1]: 48
7833 23:49:28.505552
7834 23:49:28.505664 Set Vref, RX VrefLevel [Byte0]: 49
7835 23:49:28.508713 [Byte1]: 49
7836 23:49:28.513038
7837 23:49:28.513117 Set Vref, RX VrefLevel [Byte0]: 50
7838 23:49:28.516579 [Byte1]: 50
7839 23:49:28.520632
7840 23:49:28.523899 Set Vref, RX VrefLevel [Byte0]: 51
7841 23:49:28.523997 [Byte1]: 51
7842 23:49:28.528755
7843 23:49:28.528855 Set Vref, RX VrefLevel [Byte0]: 52
7844 23:49:28.531670 [Byte1]: 52
7845 23:49:28.536096
7846 23:49:28.536199 Set Vref, RX VrefLevel [Byte0]: 53
7847 23:49:28.539325 [Byte1]: 53
7848 23:49:28.543416
7849 23:49:28.543524 Set Vref, RX VrefLevel [Byte0]: 54
7850 23:49:28.546902 [Byte1]: 54
7851 23:49:28.551001
7852 23:49:28.551106 Set Vref, RX VrefLevel [Byte0]: 55
7853 23:49:28.554590 [Byte1]: 55
7854 23:49:28.558538
7855 23:49:28.558645 Set Vref, RX VrefLevel [Byte0]: 56
7856 23:49:28.562056 [Byte1]: 56
7857 23:49:28.566027
7858 23:49:28.566134 Set Vref, RX VrefLevel [Byte0]: 57
7859 23:49:28.569358 [Byte1]: 57
7860 23:49:28.574039
7861 23:49:28.574143 Set Vref, RX VrefLevel [Byte0]: 58
7862 23:49:28.577391 [Byte1]: 58
7863 23:49:28.581218
7864 23:49:28.581325 Set Vref, RX VrefLevel [Byte0]: 59
7865 23:49:28.584438 [Byte1]: 59
7866 23:49:28.588870
7867 23:49:28.588983 Set Vref, RX VrefLevel [Byte0]: 60
7868 23:49:28.592612 [Byte1]: 60
7869 23:49:28.596694
7870 23:49:28.596795 Set Vref, RX VrefLevel [Byte0]: 61
7871 23:49:28.600207 [Byte1]: 61
7872 23:49:28.604328
7873 23:49:28.604466 Set Vref, RX VrefLevel [Byte0]: 62
7874 23:49:28.607479 [Byte1]: 62
7875 23:49:28.611506
7876 23:49:28.611586 Set Vref, RX VrefLevel [Byte0]: 63
7877 23:49:28.614800 [Byte1]: 63
7878 23:49:28.619115
7879 23:49:28.619195 Set Vref, RX VrefLevel [Byte0]: 64
7880 23:49:28.622771 [Byte1]: 64
7881 23:49:28.626825
7882 23:49:28.626905 Set Vref, RX VrefLevel [Byte0]: 65
7883 23:49:28.630392 [Byte1]: 65
7884 23:49:28.634663
7885 23:49:28.634745 Set Vref, RX VrefLevel [Byte0]: 66
7886 23:49:28.637742 [Byte1]: 66
7887 23:49:28.642110
7888 23:49:28.642226 Set Vref, RX VrefLevel [Byte0]: 67
7889 23:49:28.645381 [Byte1]: 67
7890 23:49:28.649484
7891 23:49:28.649593 Set Vref, RX VrefLevel [Byte0]: 68
7892 23:49:28.652862 [Byte1]: 68
7893 23:49:28.657041
7894 23:49:28.657152 Set Vref, RX VrefLevel [Byte0]: 69
7895 23:49:28.660424 [Byte1]: 69
7896 23:49:28.664521
7897 23:49:28.664612 Set Vref, RX VrefLevel [Byte0]: 70
7898 23:49:28.667979 [Byte1]: 70
7899 23:49:28.672869
7900 23:49:28.672952 Set Vref, RX VrefLevel [Byte0]: 71
7901 23:49:28.675415 [Byte1]: 71
7902 23:49:28.680102
7903 23:49:28.680182 Set Vref, RX VrefLevel [Byte0]: 72
7904 23:49:28.683106 [Byte1]: 72
7905 23:49:28.687491
7906 23:49:28.687567 Set Vref, RX VrefLevel [Byte0]: 73
7907 23:49:28.691380 [Byte1]: 73
7908 23:49:28.695001
7909 23:49:28.695071 Set Vref, RX VrefLevel [Byte0]: 74
7910 23:49:28.698123 [Byte1]: 74
7911 23:49:28.702691
7912 23:49:28.702799 Set Vref, RX VrefLevel [Byte0]: 75
7913 23:49:28.706011 [Byte1]: 75
7914 23:49:28.710554
7915 23:49:28.710666 Final RX Vref Byte 0 = 55 to rank0
7916 23:49:28.713298 Final RX Vref Byte 1 = 61 to rank0
7917 23:49:28.716714 Final RX Vref Byte 0 = 55 to rank1
7918 23:49:28.719936 Final RX Vref Byte 1 = 61 to rank1==
7919 23:49:28.723307 Dram Type= 6, Freq= 0, CH_0, rank 0
7920 23:49:28.729872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7921 23:49:28.729983 ==
7922 23:49:28.730087 DQS Delay:
7923 23:49:28.730176 DQS0 = 0, DQS1 = 0
7924 23:49:28.733237 DQM Delay:
7925 23:49:28.733350 DQM0 = 133, DQM1 = 128
7926 23:49:28.736477 DQ Delay:
7927 23:49:28.740313 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7928 23:49:28.743429 DQ4 =132, DQ5 =122, DQ6 =138, DQ7 =138
7929 23:49:28.746458 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7930 23:49:28.750127 DQ12 =134, DQ13 =134, DQ14 =138, DQ15 =134
7931 23:49:28.750240
7932 23:49:28.750333
7933 23:49:28.750433
7934 23:49:28.753841 [DramC_TX_OE_Calibration] TA2
7935 23:49:28.756826 Original DQ_B0 (3 6) =30, OEN = 27
7936 23:49:28.760261 Original DQ_B1 (3 6) =30, OEN = 27
7937 23:49:28.763634 24, 0x0, End_B0=24 End_B1=24
7938 23:49:28.763791 25, 0x0, End_B0=25 End_B1=25
7939 23:49:28.766941 26, 0x0, End_B0=26 End_B1=26
7940 23:49:28.770436 27, 0x0, End_B0=27 End_B1=27
7941 23:49:28.773267 28, 0x0, End_B0=28 End_B1=28
7942 23:49:28.773352 29, 0x0, End_B0=29 End_B1=29
7943 23:49:28.776469 30, 0x0, End_B0=30 End_B1=30
7944 23:49:28.779951 31, 0x4141, End_B0=30 End_B1=30
7945 23:49:28.783389 Byte0 end_step=30 best_step=27
7946 23:49:28.786674 Byte1 end_step=30 best_step=27
7947 23:49:28.790108 Byte0 TX OE(2T, 0.5T) = (3, 3)
7948 23:49:28.793692 Byte1 TX OE(2T, 0.5T) = (3, 3)
7949 23:49:28.793773
7950 23:49:28.793837
7951 23:49:28.800139 [DQSOSCAuto] RK0, (LSB)MR18= 0x241f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 391 ps
7952 23:49:28.803297 CH0 RK0: MR19=303, MR18=241F
7953 23:49:28.809482 CH0_RK0: MR19=0x303, MR18=0x241F, DQSOSC=391, MR23=63, INC=24, DEC=16
7954 23:49:28.809568
7955 23:49:28.813221 ----->DramcWriteLeveling(PI) begin...
7956 23:49:28.813298 ==
7957 23:49:28.816318 Dram Type= 6, Freq= 0, CH_0, rank 1
7958 23:49:28.819982 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7959 23:49:28.820088 ==
7960 23:49:28.822825 Write leveling (Byte 0): 34 => 34
7961 23:49:28.826093 Write leveling (Byte 1): 27 => 27
7962 23:49:28.829404 DramcWriteLeveling(PI) end<-----
7963 23:49:28.829484
7964 23:49:28.829546 ==
7965 23:49:28.832862 Dram Type= 6, Freq= 0, CH_0, rank 1
7966 23:49:28.836315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 23:49:28.836421 ==
7968 23:49:28.839816 [Gating] SW mode calibration
7969 23:49:28.846450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7970 23:49:28.853391 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7971 23:49:28.856122 1 4 0 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7972 23:49:28.859732 1 4 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
7973 23:49:28.866726 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7974 23:49:28.869675 1 4 12 | B1->B0 | 2323 3231 | 0 1 | (0 0) (1 1)
7975 23:49:28.872683 1 4 16 | B1->B0 | 3131 3b3a | 1 1 | (1 1) (0 0)
7976 23:49:28.879582 1 4 20 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (0 0)
7977 23:49:28.882897 1 4 24 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7978 23:49:28.886003 1 4 28 | B1->B0 | 3434 3d3d | 1 0 | (1 1) (0 0)
7979 23:49:28.892547 1 5 0 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
7980 23:49:28.896087 1 5 4 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)
7981 23:49:28.899496 1 5 8 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
7982 23:49:28.906367 1 5 12 | B1->B0 | 3434 3837 | 1 1 | (1 0) (0 1)
7983 23:49:28.909512 1 5 16 | B1->B0 | 2f2f 3231 | 0 1 | (0 1) (1 0)
7984 23:49:28.912740 1 5 20 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7985 23:49:28.919215 1 5 24 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7986 23:49:28.922538 1 5 28 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7987 23:49:28.925792 1 6 0 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
7988 23:49:28.932671 1 6 4 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
7989 23:49:28.935913 1 6 8 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7990 23:49:28.939212 1 6 12 | B1->B0 | 2424 3736 | 0 1 | (0 0) (0 0)
7991 23:49:28.945981 1 6 16 | B1->B0 | 3c3c 4545 | 0 1 | (0 0) (0 0)
7992 23:49:28.949507 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 23:49:28.952204 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 23:49:28.958970 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7995 23:49:28.962407 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 23:49:28.966006 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 23:49:28.972509 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 23:49:28.975952 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7999 23:49:28.979253 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8000 23:49:28.985445 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 23:49:28.989262 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 23:49:28.992118 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 23:49:28.995944 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 23:49:29.002692 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 23:49:29.005648 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 23:49:29.008949 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 23:49:29.015609 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 23:49:29.018858 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 23:49:29.022128 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 23:49:29.028645 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 23:49:29.032568 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 23:49:29.035801 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 23:49:29.042056 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 23:49:29.045339 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8015 23:49:29.048646 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8016 23:49:29.055493 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 23:49:29.055572 Total UI for P1: 0, mck2ui 16
8018 23:49:29.062369 best dqsien dly found for B0: ( 1, 9, 14)
8019 23:49:29.062454 Total UI for P1: 0, mck2ui 16
8020 23:49:29.068897 best dqsien dly found for B1: ( 1, 9, 14)
8021 23:49:29.072117 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8022 23:49:29.075517 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8023 23:49:29.075627
8024 23:49:29.078841 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8025 23:49:29.082347 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8026 23:49:29.085775 [Gating] SW calibration Done
8027 23:49:29.085854 ==
8028 23:49:29.089070 Dram Type= 6, Freq= 0, CH_0, rank 1
8029 23:49:29.092285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8030 23:49:29.092401 ==
8031 23:49:29.095824 RX Vref Scan: 0
8032 23:49:29.095906
8033 23:49:29.095969 RX Vref 0 -> 0, step: 1
8034 23:49:29.096032
8035 23:49:29.098511 RX Delay 0 -> 252, step: 8
8036 23:49:29.101884 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8037 23:49:29.108770 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8038 23:49:29.112176 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8039 23:49:29.115637 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8040 23:49:29.118314 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8041 23:49:29.122283 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8042 23:49:29.128356 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8043 23:49:29.131609 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8044 23:49:29.134924 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8045 23:49:29.138653 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8046 23:49:29.141933 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8047 23:49:29.148619 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8048 23:49:29.151733 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8049 23:49:29.155350 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8050 23:49:29.158534 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8051 23:49:29.161845 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8052 23:49:29.165196 ==
8053 23:49:29.168596 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 23:49:29.171972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 23:49:29.172081 ==
8056 23:49:29.172194 DQS Delay:
8057 23:49:29.175190 DQS0 = 0, DQS1 = 0
8058 23:49:29.175267 DQM Delay:
8059 23:49:29.178558 DQM0 = 136, DQM1 = 130
8060 23:49:29.178635 DQ Delay:
8061 23:49:29.181898 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8062 23:49:29.185183 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8063 23:49:29.188617 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =123
8064 23:49:29.192048 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8065 23:49:29.192157
8066 23:49:29.192260
8067 23:49:29.192356 ==
8068 23:49:29.195515 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 23:49:29.201534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 23:49:29.201622 ==
8071 23:49:29.201687
8072 23:49:29.201745
8073 23:49:29.201801 TX Vref Scan disable
8074 23:49:29.205342 == TX Byte 0 ==
8075 23:49:29.208827 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8076 23:49:29.212231 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8077 23:49:29.215550 == TX Byte 1 ==
8078 23:49:29.218668 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8079 23:49:29.222352 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8080 23:49:29.225441 ==
8081 23:49:29.228868 Dram Type= 6, Freq= 0, CH_0, rank 1
8082 23:49:29.232276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8083 23:49:29.232382 ==
8084 23:49:29.245263
8085 23:49:29.248486 TX Vref early break, caculate TX vref
8086 23:49:29.251678 TX Vref=16, minBit 0, minWin=23, winSum=389
8087 23:49:29.255043 TX Vref=18, minBit 1, minWin=23, winSum=397
8088 23:49:29.258390 TX Vref=20, minBit 1, minWin=24, winSum=407
8089 23:49:29.261581 TX Vref=22, minBit 1, minWin=23, winSum=411
8090 23:49:29.265257 TX Vref=24, minBit 1, minWin=25, winSum=421
8091 23:49:29.271571 TX Vref=26, minBit 0, minWin=25, winSum=427
8092 23:49:29.274868 TX Vref=28, minBit 7, minWin=25, winSum=426
8093 23:49:29.278522 TX Vref=30, minBit 4, minWin=25, winSum=419
8094 23:49:29.281729 TX Vref=32, minBit 0, minWin=25, winSum=410
8095 23:49:29.285111 TX Vref=34, minBit 0, minWin=24, winSum=402
8096 23:49:29.291413 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 26
8097 23:49:29.291513
8098 23:49:29.294905 Final TX Range 0 Vref 26
8099 23:49:29.294990
8100 23:49:29.295054 ==
8101 23:49:29.298252 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 23:49:29.301801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 23:49:29.301883 ==
8104 23:49:29.301946
8105 23:49:29.302005
8106 23:49:29.304462 TX Vref Scan disable
8107 23:49:29.311160 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8108 23:49:29.311243 == TX Byte 0 ==
8109 23:49:29.314422 u2DelayCellOfst[0]=10 cells (3 PI)
8110 23:49:29.317903 u2DelayCellOfst[1]=16 cells (5 PI)
8111 23:49:29.321254 u2DelayCellOfst[2]=10 cells (3 PI)
8112 23:49:29.324583 u2DelayCellOfst[3]=10 cells (3 PI)
8113 23:49:29.327797 u2DelayCellOfst[4]=6 cells (2 PI)
8114 23:49:29.330828 u2DelayCellOfst[5]=0 cells (0 PI)
8115 23:49:29.334328 u2DelayCellOfst[6]=16 cells (5 PI)
8116 23:49:29.337707 u2DelayCellOfst[7]=13 cells (4 PI)
8117 23:49:29.340668 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8118 23:49:29.343975 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8119 23:49:29.347579 == TX Byte 1 ==
8120 23:49:29.350964 u2DelayCellOfst[8]=0 cells (0 PI)
8121 23:49:29.354516 u2DelayCellOfst[9]=0 cells (0 PI)
8122 23:49:29.354599 u2DelayCellOfst[10]=3 cells (1 PI)
8123 23:49:29.357473 u2DelayCellOfst[11]=0 cells (0 PI)
8124 23:49:29.360723 u2DelayCellOfst[12]=6 cells (2 PI)
8125 23:49:29.364151 u2DelayCellOfst[13]=6 cells (2 PI)
8126 23:49:29.367796 u2DelayCellOfst[14]=13 cells (4 PI)
8127 23:49:29.371021 u2DelayCellOfst[15]=6 cells (2 PI)
8128 23:49:29.374214 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8129 23:49:29.380173 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8130 23:49:29.380257 DramC Write-DBI on
8131 23:49:29.380322 ==
8132 23:49:29.384035 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 23:49:29.390387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 23:49:29.390488 ==
8135 23:49:29.390556
8136 23:49:29.390615
8137 23:49:29.390672 TX Vref Scan disable
8138 23:49:29.394216 == TX Byte 0 ==
8139 23:49:29.397563 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8140 23:49:29.400938 == TX Byte 1 ==
8141 23:49:29.404311 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8142 23:49:29.407622 DramC Write-DBI off
8143 23:49:29.407703
8144 23:49:29.407767 [DATLAT]
8145 23:49:29.407826 Freq=1600, CH0 RK1
8146 23:49:29.407884
8147 23:49:29.410935 DATLAT Default: 0xf
8148 23:49:29.411016 0, 0xFFFF, sum = 0
8149 23:49:29.414442 1, 0xFFFF, sum = 0
8150 23:49:29.414525 2, 0xFFFF, sum = 0
8151 23:49:29.417755 3, 0xFFFF, sum = 0
8152 23:49:29.421002 4, 0xFFFF, sum = 0
8153 23:49:29.421098 5, 0xFFFF, sum = 0
8154 23:49:29.424190 6, 0xFFFF, sum = 0
8155 23:49:29.424273 7, 0xFFFF, sum = 0
8156 23:49:29.427268 8, 0xFFFF, sum = 0
8157 23:49:29.427376 9, 0xFFFF, sum = 0
8158 23:49:29.430510 10, 0xFFFF, sum = 0
8159 23:49:29.430593 11, 0xFFFF, sum = 0
8160 23:49:29.433877 12, 0xFFFF, sum = 0
8161 23:49:29.433959 13, 0xFFFF, sum = 0
8162 23:49:29.437273 14, 0x0, sum = 1
8163 23:49:29.437355 15, 0x0, sum = 2
8164 23:49:29.440622 16, 0x0, sum = 3
8165 23:49:29.440704 17, 0x0, sum = 4
8166 23:49:29.443856 best_step = 15
8167 23:49:29.443935
8168 23:49:29.443998 ==
8169 23:49:29.446994 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 23:49:29.450650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 23:49:29.450732 ==
8172 23:49:29.453576 RX Vref Scan: 0
8173 23:49:29.453657
8174 23:49:29.453719 RX Vref 0 -> 0, step: 1
8175 23:49:29.453779
8176 23:49:29.457252 RX Delay 19 -> 252, step: 4
8177 23:49:29.460491 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8178 23:49:29.466965 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8179 23:49:29.470813 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8180 23:49:29.473568 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8181 23:49:29.476871 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8182 23:49:29.480211 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8183 23:49:29.486928 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8184 23:49:29.490614 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8185 23:49:29.493656 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8186 23:49:29.497252 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8187 23:49:29.500478 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8188 23:49:29.506925 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8189 23:49:29.510379 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8190 23:49:29.513843 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8191 23:49:29.516580 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8192 23:49:29.523499 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8193 23:49:29.523580 ==
8194 23:49:29.526816 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 23:49:29.530022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 23:49:29.530103 ==
8197 23:49:29.530167 DQS Delay:
8198 23:49:29.533265 DQS0 = 0, DQS1 = 0
8199 23:49:29.533361 DQM Delay:
8200 23:49:29.536587 DQM0 = 134, DQM1 = 127
8201 23:49:29.536668 DQ Delay:
8202 23:49:29.539866 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8203 23:49:29.543322 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8204 23:49:29.546986 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8205 23:49:29.550150 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8206 23:49:29.550231
8207 23:49:29.550294
8208 23:49:29.550352
8209 23:49:29.553530 [DramC_TX_OE_Calibration] TA2
8210 23:49:29.556920 Original DQ_B0 (3 6) =30, OEN = 27
8211 23:49:29.560258 Original DQ_B1 (3 6) =30, OEN = 27
8212 23:49:29.563589 24, 0x0, End_B0=24 End_B1=24
8213 23:49:29.566357 25, 0x0, End_B0=25 End_B1=25
8214 23:49:29.566439 26, 0x0, End_B0=26 End_B1=26
8215 23:49:29.570154 27, 0x0, End_B0=27 End_B1=27
8216 23:49:29.573738 28, 0x0, End_B0=28 End_B1=28
8217 23:49:29.576735 29, 0x0, End_B0=29 End_B1=29
8218 23:49:29.579743 30, 0x0, End_B0=30 End_B1=30
8219 23:49:29.579826 31, 0x4545, End_B0=30 End_B1=30
8220 23:49:29.583525 Byte0 end_step=30 best_step=27
8221 23:49:29.586928 Byte1 end_step=30 best_step=27
8222 23:49:29.590353 Byte0 TX OE(2T, 0.5T) = (3, 3)
8223 23:49:29.593637 Byte1 TX OE(2T, 0.5T) = (3, 3)
8224 23:49:29.593717
8225 23:49:29.593781
8226 23:49:29.599855 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8227 23:49:29.603121 CH0 RK1: MR19=303, MR18=220A
8228 23:49:29.610072 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8229 23:49:29.613023 [RxdqsGatingPostProcess] freq 1600
8230 23:49:29.619793 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8231 23:49:29.619877 best DQS0 dly(2T, 0.5T) = (1, 1)
8232 23:49:29.623236 best DQS1 dly(2T, 0.5T) = (1, 1)
8233 23:49:29.626563 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8234 23:49:29.629828 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8235 23:49:29.633331 best DQS0 dly(2T, 0.5T) = (1, 1)
8236 23:49:29.636723 best DQS1 dly(2T, 0.5T) = (1, 1)
8237 23:49:29.640093 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8238 23:49:29.643344 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8239 23:49:29.646695 Pre-setting of DQS Precalculation
8240 23:49:29.649494 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8241 23:49:29.649582 ==
8242 23:49:29.652827 Dram Type= 6, Freq= 0, CH_1, rank 0
8243 23:49:29.659555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 23:49:29.659643 ==
8245 23:49:29.662898 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8246 23:49:29.669507 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8247 23:49:29.672989 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8248 23:49:29.679663 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8249 23:49:29.687233 [CA 0] Center 41 (12~71) winsize 60
8250 23:49:29.690617 [CA 1] Center 41 (12~71) winsize 60
8251 23:49:29.694217 [CA 2] Center 38 (9~68) winsize 60
8252 23:49:29.697241 [CA 3] Center 38 (9~67) winsize 59
8253 23:49:29.700327 [CA 4] Center 37 (8~67) winsize 60
8254 23:49:29.704117 [CA 5] Center 37 (8~66) winsize 59
8255 23:49:29.704200
8256 23:49:29.706830 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8257 23:49:29.706913
8258 23:49:29.710196 [CATrainingPosCal] consider 1 rank data
8259 23:49:29.713764 u2DelayCellTimex100 = 290/100 ps
8260 23:49:29.717138 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8261 23:49:29.723985 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8262 23:49:29.727018 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8263 23:49:29.730138 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8264 23:49:29.734147 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8265 23:49:29.736970 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8266 23:49:29.737055
8267 23:49:29.740280 CA PerBit enable=1, Macro0, CA PI delay=37
8268 23:49:29.740384
8269 23:49:29.743817 [CBTSetCACLKResult] CA Dly = 37
8270 23:49:29.747276 CS Dly: 10 (0~41)
8271 23:49:29.750371 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8272 23:49:29.753780 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8273 23:49:29.753863 ==
8274 23:49:29.757022 Dram Type= 6, Freq= 0, CH_1, rank 1
8275 23:49:29.760556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 23:49:29.763848 ==
8277 23:49:29.767327 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8278 23:49:29.770048 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8279 23:49:29.777164 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8280 23:49:29.779949 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8281 23:49:29.790894 [CA 0] Center 42 (12~72) winsize 61
8282 23:49:29.794279 [CA 1] Center 41 (12~71) winsize 60
8283 23:49:29.797543 [CA 2] Center 38 (9~68) winsize 60
8284 23:49:29.800244 [CA 3] Center 38 (9~67) winsize 59
8285 23:49:29.804091 [CA 4] Center 38 (8~68) winsize 61
8286 23:49:29.807342 [CA 5] Center 37 (8~67) winsize 60
8287 23:49:29.807442
8288 23:49:29.810377 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8289 23:49:29.810461
8290 23:49:29.814010 [CATrainingPosCal] consider 2 rank data
8291 23:49:29.817098 u2DelayCellTimex100 = 290/100 ps
8292 23:49:29.820268 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8293 23:49:29.827404 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8294 23:49:29.830542 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8295 23:49:29.833644 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8296 23:49:29.837542 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8297 23:49:29.840650 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8298 23:49:29.840732
8299 23:49:29.843805 CA PerBit enable=1, Macro0, CA PI delay=37
8300 23:49:29.843887
8301 23:49:29.847173 [CBTSetCACLKResult] CA Dly = 37
8302 23:49:29.850600 CS Dly: 11 (0~44)
8303 23:49:29.853475 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8304 23:49:29.857213 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8305 23:49:29.857295
8306 23:49:29.860483 ----->DramcWriteLeveling(PI) begin...
8307 23:49:29.860600 ==
8308 23:49:29.863698 Dram Type= 6, Freq= 0, CH_1, rank 0
8309 23:49:29.867125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 23:49:29.869962 ==
8311 23:49:29.870037 Write leveling (Byte 0): 25 => 25
8312 23:49:29.873444 Write leveling (Byte 1): 26 => 26
8313 23:49:29.876641 DramcWriteLeveling(PI) end<-----
8314 23:49:29.876715
8315 23:49:29.876776 ==
8316 23:49:29.879981 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 23:49:29.886642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 23:49:29.886721 ==
8319 23:49:29.890159 [Gating] SW mode calibration
8320 23:49:29.896515 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8321 23:49:29.899766 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8322 23:49:29.906661 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 23:49:29.909963 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 23:49:29.913330 1 4 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8325 23:49:29.919779 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 23:49:29.923589 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 23:49:29.926885 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 23:49:29.933282 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 23:49:29.936310 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 23:49:29.939973 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 23:49:29.942990 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 23:49:29.949523 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8333 23:49:29.953325 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
8334 23:49:29.956430 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 23:49:29.963201 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 23:49:29.966485 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 23:49:29.969707 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 23:49:29.976569 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 23:49:29.979897 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 23:49:29.983064 1 6 8 | B1->B0 | 2424 4040 | 0 0 | (0 0) (0 0)
8341 23:49:29.989925 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (1 1) (0 0)
8342 23:49:29.992670 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 23:49:29.996039 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 23:49:30.002961 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 23:49:30.006591 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 23:49:30.009338 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 23:49:30.015922 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 23:49:30.019312 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8349 23:49:30.022849 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8350 23:49:30.029492 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8351 23:49:30.032608 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 23:49:30.035737 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 23:49:30.042528 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 23:49:30.045858 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 23:49:30.049173 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 23:49:30.056106 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 23:49:30.059453 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 23:49:30.062524 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 23:49:30.069566 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 23:49:30.072485 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 23:49:30.075568 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 23:49:30.082582 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 23:49:30.085802 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 23:49:30.088902 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8365 23:49:30.095668 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8366 23:49:30.099035 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 23:49:30.102355 Total UI for P1: 0, mck2ui 16
8368 23:49:30.105748 best dqsien dly found for B0: ( 1, 9, 10)
8369 23:49:30.109174 Total UI for P1: 0, mck2ui 16
8370 23:49:30.111985 best dqsien dly found for B1: ( 1, 9, 10)
8371 23:49:30.115405 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8372 23:49:30.118854 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8373 23:49:30.118938
8374 23:49:30.122275 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8375 23:49:30.125794 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8376 23:49:30.129211 [Gating] SW calibration Done
8377 23:49:30.129295 ==
8378 23:49:30.131928 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 23:49:30.135453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 23:49:30.135552 ==
8381 23:49:30.138727 RX Vref Scan: 0
8382 23:49:30.138855
8383 23:49:30.141877 RX Vref 0 -> 0, step: 1
8384 23:49:30.141961
8385 23:49:30.142025 RX Delay 0 -> 252, step: 8
8386 23:49:30.149245 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8387 23:49:30.151955 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8388 23:49:30.155347 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8389 23:49:30.158801 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8390 23:49:30.161918 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8391 23:49:30.168512 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8392 23:49:30.171784 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8393 23:49:30.175970 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8394 23:49:30.179145 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8395 23:49:30.181875 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8396 23:49:30.188867 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8397 23:49:30.192112 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8398 23:49:30.195591 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8399 23:49:30.198563 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8400 23:49:30.202077 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8401 23:49:30.208627 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8402 23:49:30.208724 ==
8403 23:49:30.211622 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 23:49:30.214976 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 23:49:30.215078 ==
8406 23:49:30.215145 DQS Delay:
8407 23:49:30.218382 DQS0 = 0, DQS1 = 0
8408 23:49:30.218471 DQM Delay:
8409 23:49:30.221627 DQM0 = 136, DQM1 = 132
8410 23:49:30.221704 DQ Delay:
8411 23:49:30.225136 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8412 23:49:30.228537 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8413 23:49:30.232055 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8414 23:49:30.235656 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8415 23:49:30.235767
8416 23:49:30.238259
8417 23:49:30.238354 ==
8418 23:49:30.241644 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 23:49:30.245366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 23:49:30.245448 ==
8421 23:49:30.245512
8422 23:49:30.245579
8423 23:49:30.248528 TX Vref Scan disable
8424 23:49:30.248630 == TX Byte 0 ==
8425 23:49:30.255045 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8426 23:49:30.258532 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8427 23:49:30.258642 == TX Byte 1 ==
8428 23:49:30.264635 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8429 23:49:30.267974 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8430 23:49:30.268078 ==
8431 23:49:30.271347 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 23:49:30.274758 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 23:49:30.274877 ==
8434 23:49:30.289197
8435 23:49:30.292494 TX Vref early break, caculate TX vref
8436 23:49:30.295720 TX Vref=16, minBit 0, minWin=22, winSum=379
8437 23:49:30.298625 TX Vref=18, minBit 1, minWin=23, winSum=390
8438 23:49:30.301861 TX Vref=20, minBit 1, minWin=23, winSum=399
8439 23:49:30.305276 TX Vref=22, minBit 1, minWin=24, winSum=410
8440 23:49:30.308944 TX Vref=24, minBit 0, minWin=25, winSum=418
8441 23:49:30.315607 TX Vref=26, minBit 0, minWin=25, winSum=426
8442 23:49:30.318626 TX Vref=28, minBit 2, minWin=25, winSum=428
8443 23:49:30.322097 TX Vref=30, minBit 0, minWin=25, winSum=422
8444 23:49:30.325043 TX Vref=32, minBit 0, minWin=24, winSum=415
8445 23:49:30.328988 TX Vref=34, minBit 5, minWin=24, winSum=406
8446 23:49:30.331760 TX Vref=36, minBit 0, minWin=23, winSum=396
8447 23:49:30.338696 [TxChooseVref] Worse bit 2, Min win 25, Win sum 428, Final Vref 28
8448 23:49:30.338776
8449 23:49:30.342055 Final TX Range 0 Vref 28
8450 23:49:30.342133
8451 23:49:30.342215 ==
8452 23:49:30.345450 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 23:49:30.348243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 23:49:30.348373 ==
8455 23:49:30.348472
8456 23:49:30.351584
8457 23:49:30.351684 TX Vref Scan disable
8458 23:49:30.358226 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8459 23:49:30.358341 == TX Byte 0 ==
8460 23:49:30.362078 u2DelayCellOfst[0]=20 cells (6 PI)
8461 23:49:30.365506 u2DelayCellOfst[1]=13 cells (4 PI)
8462 23:49:30.368787 u2DelayCellOfst[2]=0 cells (0 PI)
8463 23:49:30.371690 u2DelayCellOfst[3]=10 cells (3 PI)
8464 23:49:30.375414 u2DelayCellOfst[4]=13 cells (4 PI)
8465 23:49:30.378743 u2DelayCellOfst[5]=20 cells (6 PI)
8466 23:49:30.381970 u2DelayCellOfst[6]=20 cells (6 PI)
8467 23:49:30.384801 u2DelayCellOfst[7]=10 cells (3 PI)
8468 23:49:30.388224 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8469 23:49:30.391786 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8470 23:49:30.394935 == TX Byte 1 ==
8471 23:49:30.398213 u2DelayCellOfst[8]=0 cells (0 PI)
8472 23:49:30.401641 u2DelayCellOfst[9]=0 cells (0 PI)
8473 23:49:30.401724 u2DelayCellOfst[10]=10 cells (3 PI)
8474 23:49:30.405300 u2DelayCellOfst[11]=0 cells (0 PI)
8475 23:49:30.408764 u2DelayCellOfst[12]=13 cells (4 PI)
8476 23:49:30.411518 u2DelayCellOfst[13]=13 cells (4 PI)
8477 23:49:30.414836 u2DelayCellOfst[14]=13 cells (4 PI)
8478 23:49:30.418038 u2DelayCellOfst[15]=13 cells (4 PI)
8479 23:49:30.425305 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8480 23:49:30.428015 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8481 23:49:30.428129 DramC Write-DBI on
8482 23:49:30.428225 ==
8483 23:49:30.431239 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 23:49:30.437997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 23:49:30.438085 ==
8486 23:49:30.438153
8487 23:49:30.438215
8488 23:49:30.438275 TX Vref Scan disable
8489 23:49:30.442242 == TX Byte 0 ==
8490 23:49:30.445784 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8491 23:49:30.448627 == TX Byte 1 ==
8492 23:49:30.452088 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8493 23:49:30.455453 DramC Write-DBI off
8494 23:49:30.455539
8495 23:49:30.455604 [DATLAT]
8496 23:49:30.455665 Freq=1600, CH1 RK0
8497 23:49:30.455724
8498 23:49:30.458716 DATLAT Default: 0xf
8499 23:49:30.458801 0, 0xFFFF, sum = 0
8500 23:49:30.462162 1, 0xFFFF, sum = 0
8501 23:49:30.465589 2, 0xFFFF, sum = 0
8502 23:49:30.465673 3, 0xFFFF, sum = 0
8503 23:49:30.468891 4, 0xFFFF, sum = 0
8504 23:49:30.468977 5, 0xFFFF, sum = 0
8505 23:49:30.472313 6, 0xFFFF, sum = 0
8506 23:49:30.472446 7, 0xFFFF, sum = 0
8507 23:49:30.475789 8, 0xFFFF, sum = 0
8508 23:49:30.475877 9, 0xFFFF, sum = 0
8509 23:49:30.478900 10, 0xFFFF, sum = 0
8510 23:49:30.478984 11, 0xFFFF, sum = 0
8511 23:49:30.482229 12, 0xFFFF, sum = 0
8512 23:49:30.482312 13, 0xFFFF, sum = 0
8513 23:49:30.485496 14, 0x0, sum = 1
8514 23:49:30.485579 15, 0x0, sum = 2
8515 23:49:30.488786 16, 0x0, sum = 3
8516 23:49:30.488870 17, 0x0, sum = 4
8517 23:49:30.492290 best_step = 15
8518 23:49:30.492425
8519 23:49:30.492491 ==
8520 23:49:30.495066 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 23:49:30.498486 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 23:49:30.498596 ==
8523 23:49:30.501926 RX Vref Scan: 1
8524 23:49:30.502008
8525 23:49:30.502073 Set Vref Range= 24 -> 127
8526 23:49:30.502133
8527 23:49:30.505488 RX Vref 24 -> 127, step: 1
8528 23:49:30.505571
8529 23:49:30.508637 RX Delay 27 -> 252, step: 4
8530 23:49:30.508720
8531 23:49:30.511909 Set Vref, RX VrefLevel [Byte0]: 24
8532 23:49:30.515377 [Byte1]: 24
8533 23:49:30.515460
8534 23:49:30.518784 Set Vref, RX VrefLevel [Byte0]: 25
8535 23:49:30.522119 [Byte1]: 25
8536 23:49:30.522227
8537 23:49:30.525507 Set Vref, RX VrefLevel [Byte0]: 26
8538 23:49:30.528673 [Byte1]: 26
8539 23:49:30.532720
8540 23:49:30.532805 Set Vref, RX VrefLevel [Byte0]: 27
8541 23:49:30.535534 [Byte1]: 27
8542 23:49:30.539720
8543 23:49:30.539835 Set Vref, RX VrefLevel [Byte0]: 28
8544 23:49:30.543118 [Byte1]: 28
8545 23:49:30.547681
8546 23:49:30.547796 Set Vref, RX VrefLevel [Byte0]: 29
8547 23:49:30.550835 [Byte1]: 29
8548 23:49:30.555208
8549 23:49:30.555316 Set Vref, RX VrefLevel [Byte0]: 30
8550 23:49:30.558168 [Byte1]: 30
8551 23:49:30.562474
8552 23:49:30.562583 Set Vref, RX VrefLevel [Byte0]: 31
8553 23:49:30.565886 [Byte1]: 31
8554 23:49:30.570076
8555 23:49:30.570218 Set Vref, RX VrefLevel [Byte0]: 32
8556 23:49:30.573254 [Byte1]: 32
8557 23:49:30.577976
8558 23:49:30.578096 Set Vref, RX VrefLevel [Byte0]: 33
8559 23:49:30.580699 [Byte1]: 33
8560 23:49:30.585573
8561 23:49:30.585689 Set Vref, RX VrefLevel [Byte0]: 34
8562 23:49:30.588740 [Byte1]: 34
8563 23:49:30.592531
8564 23:49:30.592646 Set Vref, RX VrefLevel [Byte0]: 35
8565 23:49:30.595961 [Byte1]: 35
8566 23:49:30.600111
8567 23:49:30.600197 Set Vref, RX VrefLevel [Byte0]: 36
8568 23:49:30.603563 [Byte1]: 36
8569 23:49:30.607452
8570 23:49:30.607566 Set Vref, RX VrefLevel [Byte0]: 37
8571 23:49:30.610757 [Byte1]: 37
8572 23:49:30.614978
8573 23:49:30.615090 Set Vref, RX VrefLevel [Byte0]: 38
8574 23:49:30.619014 [Byte1]: 38
8575 23:49:30.623018
8576 23:49:30.623106 Set Vref, RX VrefLevel [Byte0]: 39
8577 23:49:30.625753 [Byte1]: 39
8578 23:49:30.630605
8579 23:49:30.630719 Set Vref, RX VrefLevel [Byte0]: 40
8580 23:49:30.633906 [Byte1]: 40
8581 23:49:30.637642
8582 23:49:30.637757 Set Vref, RX VrefLevel [Byte0]: 41
8583 23:49:30.640986 [Byte1]: 41
8584 23:49:30.645245
8585 23:49:30.645354 Set Vref, RX VrefLevel [Byte0]: 42
8586 23:49:30.648669 [Byte1]: 42
8587 23:49:30.652699
8588 23:49:30.652808 Set Vref, RX VrefLevel [Byte0]: 43
8589 23:49:30.656010 [Byte1]: 43
8590 23:49:30.660267
8591 23:49:30.660392 Set Vref, RX VrefLevel [Byte0]: 44
8592 23:49:30.663480 [Byte1]: 44
8593 23:49:30.668080
8594 23:49:30.668190 Set Vref, RX VrefLevel [Byte0]: 45
8595 23:49:30.671211 [Byte1]: 45
8596 23:49:30.675441
8597 23:49:30.675558 Set Vref, RX VrefLevel [Byte0]: 46
8598 23:49:30.678962 [Byte1]: 46
8599 23:49:30.682806
8600 23:49:30.682922 Set Vref, RX VrefLevel [Byte0]: 47
8601 23:49:30.686251 [Byte1]: 47
8602 23:49:30.690266
8603 23:49:30.690381 Set Vref, RX VrefLevel [Byte0]: 48
8604 23:49:30.693679 [Byte1]: 48
8605 23:49:30.698055
8606 23:49:30.698164 Set Vref, RX VrefLevel [Byte0]: 49
8607 23:49:30.701167 [Byte1]: 49
8608 23:49:30.705365
8609 23:49:30.705499 Set Vref, RX VrefLevel [Byte0]: 50
8610 23:49:30.708764 [Byte1]: 50
8611 23:49:30.713517
8612 23:49:30.713650 Set Vref, RX VrefLevel [Byte0]: 51
8613 23:49:30.716259 [Byte1]: 51
8614 23:49:30.720309
8615 23:49:30.720410 Set Vref, RX VrefLevel [Byte0]: 52
8616 23:49:30.724130 [Byte1]: 52
8617 23:49:30.728203
8618 23:49:30.728316 Set Vref, RX VrefLevel [Byte0]: 53
8619 23:49:30.731713 [Byte1]: 53
8620 23:49:30.735698
8621 23:49:30.735797 Set Vref, RX VrefLevel [Byte0]: 54
8622 23:49:30.738850 [Byte1]: 54
8623 23:49:30.743381
8624 23:49:30.743470 Set Vref, RX VrefLevel [Byte0]: 55
8625 23:49:30.746666 [Byte1]: 55
8626 23:49:30.750839
8627 23:49:30.750916 Set Vref, RX VrefLevel [Byte0]: 56
8628 23:49:30.754272 [Byte1]: 56
8629 23:49:30.758299
8630 23:49:30.758410 Set Vref, RX VrefLevel [Byte0]: 57
8631 23:49:30.761540 [Byte1]: 57
8632 23:49:30.765820
8633 23:49:30.765932 Set Vref, RX VrefLevel [Byte0]: 58
8634 23:49:30.769330 [Byte1]: 58
8635 23:49:30.773373
8636 23:49:30.773481 Set Vref, RX VrefLevel [Byte0]: 59
8637 23:49:30.776882 [Byte1]: 59
8638 23:49:30.780918
8639 23:49:30.781030 Set Vref, RX VrefLevel [Byte0]: 60
8640 23:49:30.784112 [Byte1]: 60
8641 23:49:30.788487
8642 23:49:30.788635 Set Vref, RX VrefLevel [Byte0]: 61
8643 23:49:30.791493 [Byte1]: 61
8644 23:49:30.796197
8645 23:49:30.796302 Set Vref, RX VrefLevel [Byte0]: 62
8646 23:49:30.799318 [Byte1]: 62
8647 23:49:30.803346
8648 23:49:30.803450 Set Vref, RX VrefLevel [Byte0]: 63
8649 23:49:30.806839 [Byte1]: 63
8650 23:49:30.811287
8651 23:49:30.811406 Set Vref, RX VrefLevel [Byte0]: 64
8652 23:49:30.814383 [Byte1]: 64
8653 23:49:30.818472
8654 23:49:30.818583 Set Vref, RX VrefLevel [Byte0]: 65
8655 23:49:30.821641 [Byte1]: 65
8656 23:49:30.826320
8657 23:49:30.826438 Set Vref, RX VrefLevel [Byte0]: 66
8658 23:49:30.829713 [Byte1]: 66
8659 23:49:30.833736
8660 23:49:30.833870 Set Vref, RX VrefLevel [Byte0]: 67
8661 23:49:30.837168 [Byte1]: 67
8662 23:49:30.841171
8663 23:49:30.841282 Set Vref, RX VrefLevel [Byte0]: 68
8664 23:49:30.844766 [Byte1]: 68
8665 23:49:30.848632
8666 23:49:30.848769 Set Vref, RX VrefLevel [Byte0]: 69
8667 23:49:30.852083 [Byte1]: 69
8668 23:49:30.856228
8669 23:49:30.856365 Set Vref, RX VrefLevel [Byte0]: 70
8670 23:49:30.859654 [Byte1]: 70
8671 23:49:30.863662
8672 23:49:30.863771 Set Vref, RX VrefLevel [Byte0]: 71
8673 23:49:30.867118 [Byte1]: 71
8674 23:49:30.871255
8675 23:49:30.871360 Set Vref, RX VrefLevel [Byte0]: 72
8676 23:49:30.874621 [Byte1]: 72
8677 23:49:30.878657
8678 23:49:30.878763 Set Vref, RX VrefLevel [Byte0]: 73
8679 23:49:30.882047 [Byte1]: 73
8680 23:49:30.886257
8681 23:49:30.886427 Set Vref, RX VrefLevel [Byte0]: 74
8682 23:49:30.889609 [Byte1]: 74
8683 23:49:30.893743
8684 23:49:30.893841 Set Vref, RX VrefLevel [Byte0]: 75
8685 23:49:30.897028 [Byte1]: 75
8686 23:49:30.901505
8687 23:49:30.901625 Set Vref, RX VrefLevel [Byte0]: 76
8688 23:49:30.904718 [Byte1]: 76
8689 23:49:30.909069
8690 23:49:30.909188 Set Vref, RX VrefLevel [Byte0]: 77
8691 23:49:30.911925 [Byte1]: 77
8692 23:49:30.916480
8693 23:49:30.916633 Final RX Vref Byte 0 = 58 to rank0
8694 23:49:30.919495 Final RX Vref Byte 1 = 55 to rank0
8695 23:49:30.923476 Final RX Vref Byte 0 = 58 to rank1
8696 23:49:30.926594 Final RX Vref Byte 1 = 55 to rank1==
8697 23:49:30.929635 Dram Type= 6, Freq= 0, CH_1, rank 0
8698 23:49:30.936222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8699 23:49:30.936349 ==
8700 23:49:30.936428 DQS Delay:
8701 23:49:30.936545 DQS0 = 0, DQS1 = 0
8702 23:49:30.939430 DQM Delay:
8703 23:49:30.939539 DQM0 = 134, DQM1 = 131
8704 23:49:30.942803 DQ Delay:
8705 23:49:30.946265 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8706 23:49:30.949798 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8707 23:49:30.953062 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8708 23:49:30.956481 DQ12 =138, DQ13 =138, DQ14 =140, DQ15 =140
8709 23:49:30.956590
8710 23:49:30.956686
8711 23:49:30.956775
8712 23:49:30.959833 [DramC_TX_OE_Calibration] TA2
8713 23:49:30.963247 Original DQ_B0 (3 6) =30, OEN = 27
8714 23:49:30.966649 Original DQ_B1 (3 6) =30, OEN = 27
8715 23:49:30.969885 24, 0x0, End_B0=24 End_B1=24
8716 23:49:30.969975 25, 0x0, End_B0=25 End_B1=25
8717 23:49:30.972674 26, 0x0, End_B0=26 End_B1=26
8718 23:49:30.976241 27, 0x0, End_B0=27 End_B1=27
8719 23:49:30.979474 28, 0x0, End_B0=28 End_B1=28
8720 23:49:30.979567 29, 0x0, End_B0=29 End_B1=29
8721 23:49:30.982917 30, 0x0, End_B0=30 End_B1=30
8722 23:49:30.986421 31, 0x4141, End_B0=30 End_B1=30
8723 23:49:30.989881 Byte0 end_step=30 best_step=27
8724 23:49:30.992603 Byte1 end_step=30 best_step=27
8725 23:49:30.996071 Byte0 TX OE(2T, 0.5T) = (3, 3)
8726 23:49:30.999593 Byte1 TX OE(2T, 0.5T) = (3, 3)
8727 23:49:30.999704
8728 23:49:30.999796
8729 23:49:31.006488 [DQSOSCAuto] RK0, (LSB)MR18= 0x1926, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8730 23:49:31.009185 CH1 RK0: MR19=303, MR18=1926
8731 23:49:31.015936 CH1_RK0: MR19=0x303, MR18=0x1926, DQSOSC=390, MR23=63, INC=24, DEC=16
8732 23:49:31.016024
8733 23:49:31.019328 ----->DramcWriteLeveling(PI) begin...
8734 23:49:31.019438 ==
8735 23:49:31.022477 Dram Type= 6, Freq= 0, CH_1, rank 1
8736 23:49:31.026375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 23:49:31.026488 ==
8738 23:49:31.029376 Write leveling (Byte 0): 24 => 24
8739 23:49:31.032789 Write leveling (Byte 1): 29 => 29
8740 23:49:31.036027 DramcWriteLeveling(PI) end<-----
8741 23:49:31.036147
8742 23:49:31.036240 ==
8743 23:49:31.039357 Dram Type= 6, Freq= 0, CH_1, rank 1
8744 23:49:31.042773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 23:49:31.042891 ==
8746 23:49:31.046194 [Gating] SW mode calibration
8747 23:49:31.052662 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8748 23:49:31.059355 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8749 23:49:31.062706 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 23:49:31.066214 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 23:49:31.072496 1 4 8 | B1->B0 | 2d2d 2323 | 1 0 | (0 0) (0 0)
8752 23:49:31.075868 1 4 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8753 23:49:31.079292 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 23:49:31.085855 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 23:49:31.089568 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 23:49:31.092665 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 23:49:31.099306 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 23:49:31.102713 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8759 23:49:31.106189 1 5 8 | B1->B0 | 3333 3434 | 0 0 | (0 1) (0 0)
8760 23:49:31.112307 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 23:49:31.115991 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 23:49:31.119261 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 23:49:31.126121 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 23:49:31.129649 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 23:49:31.132336 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 23:49:31.139089 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8767 23:49:31.142410 1 6 8 | B1->B0 | 3333 2323 | 1 0 | (0 0) (0 0)
8768 23:49:31.145760 1 6 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8769 23:49:31.149499 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 23:49:31.156024 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 23:49:31.159152 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 23:49:31.162689 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 23:49:31.169533 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 23:49:31.172462 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 23:49:31.176055 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8776 23:49:31.182597 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8777 23:49:31.185595 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 23:49:31.188967 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 23:49:31.196051 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 23:49:31.199757 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 23:49:31.202340 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 23:49:31.209328 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 23:49:31.212751 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 23:49:31.215357 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 23:49:31.222472 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 23:49:31.225665 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 23:49:31.229085 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 23:49:31.235879 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 23:49:31.239262 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 23:49:31.242144 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8791 23:49:31.249069 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8792 23:49:31.252278 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8793 23:49:31.255473 Total UI for P1: 0, mck2ui 16
8794 23:49:31.258962 best dqsien dly found for B1: ( 1, 9, 6)
8795 23:49:31.262390 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 23:49:31.265731 Total UI for P1: 0, mck2ui 16
8797 23:49:31.268508 best dqsien dly found for B0: ( 1, 9, 12)
8798 23:49:31.272197 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8799 23:49:31.275501 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8800 23:49:31.275837
8801 23:49:31.278957 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8802 23:49:31.285674 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8803 23:49:31.285950 [Gating] SW calibration Done
8804 23:49:31.288992 ==
8805 23:49:31.289347 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 23:49:31.295699 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 23:49:31.295791 ==
8808 23:49:31.295895 RX Vref Scan: 0
8809 23:49:31.295996
8810 23:49:31.298624 RX Vref 0 -> 0, step: 1
8811 23:49:31.298711
8812 23:49:31.302302 RX Delay 0 -> 252, step: 8
8813 23:49:31.305358 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8814 23:49:31.309064 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8815 23:49:31.311988 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8816 23:49:31.318994 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8817 23:49:31.321859 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8818 23:49:31.325039 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8819 23:49:31.328359 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8820 23:49:31.331754 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8821 23:49:31.338726 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8822 23:49:31.342221 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8823 23:49:31.344924 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8824 23:49:31.348201 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8825 23:49:31.351695 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8826 23:49:31.358475 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8827 23:49:31.361539 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8828 23:49:31.364812 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8829 23:49:31.364924 ==
8830 23:49:31.368251 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 23:49:31.371799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 23:49:31.371912 ==
8833 23:49:31.374826 DQS Delay:
8834 23:49:31.374913 DQS0 = 0, DQS1 = 0
8835 23:49:31.377919 DQM Delay:
8836 23:49:31.378008 DQM0 = 136, DQM1 = 133
8837 23:49:31.381350 DQ Delay:
8838 23:49:31.385031 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8839 23:49:31.388295 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8840 23:49:31.391618 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8841 23:49:31.394868 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8842 23:49:31.394977
8843 23:49:31.395072
8844 23:49:31.395165 ==
8845 23:49:31.398332 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 23:49:31.401692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 23:49:31.401780 ==
8848 23:49:31.401847
8849 23:49:31.401908
8850 23:49:31.404962 TX Vref Scan disable
8851 23:49:31.408279 == TX Byte 0 ==
8852 23:49:31.411072 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8853 23:49:31.414715 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8854 23:49:31.418071 == TX Byte 1 ==
8855 23:49:31.421318 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8856 23:49:31.424738 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8857 23:49:31.424848 ==
8858 23:49:31.427898 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 23:49:31.434302 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 23:49:31.434408 ==
8861 23:49:31.447380
8862 23:49:31.450544 TX Vref early break, caculate TX vref
8863 23:49:31.453986 TX Vref=16, minBit 0, minWin=23, winSum=383
8864 23:49:31.457497 TX Vref=18, minBit 0, minWin=23, winSum=393
8865 23:49:31.460348 TX Vref=20, minBit 1, minWin=24, winSum=400
8866 23:49:31.463624 TX Vref=22, minBit 0, minWin=25, winSum=413
8867 23:49:31.467053 TX Vref=24, minBit 0, minWin=24, winSum=417
8868 23:49:31.474153 TX Vref=26, minBit 0, minWin=25, winSum=425
8869 23:49:31.477503 TX Vref=28, minBit 1, minWin=25, winSum=426
8870 23:49:31.481086 TX Vref=30, minBit 0, minWin=25, winSum=418
8871 23:49:31.483568 TX Vref=32, minBit 0, minWin=24, winSum=414
8872 23:49:31.486880 TX Vref=34, minBit 0, minWin=25, winSum=405
8873 23:49:31.490331 TX Vref=36, minBit 0, minWin=23, winSum=396
8874 23:49:31.496745 [TxChooseVref] Worse bit 1, Min win 25, Win sum 426, Final Vref 28
8875 23:49:31.496832
8876 23:49:31.500567 Final TX Range 0 Vref 28
8877 23:49:31.500652
8878 23:49:31.500727 ==
8879 23:49:31.503721 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 23:49:31.507113 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 23:49:31.507220 ==
8882 23:49:31.507314
8883 23:49:31.507446
8884 23:49:31.509953 TX Vref Scan disable
8885 23:49:31.516765 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8886 23:49:31.516869 == TX Byte 0 ==
8887 23:49:31.520059 u2DelayCellOfst[0]=16 cells (5 PI)
8888 23:49:31.523343 u2DelayCellOfst[1]=13 cells (4 PI)
8889 23:49:31.526708 u2DelayCellOfst[2]=0 cells (0 PI)
8890 23:49:31.530078 u2DelayCellOfst[3]=6 cells (2 PI)
8891 23:49:31.533584 u2DelayCellOfst[4]=10 cells (3 PI)
8892 23:49:31.536888 u2DelayCellOfst[5]=20 cells (6 PI)
8893 23:49:31.540287 u2DelayCellOfst[6]=20 cells (6 PI)
8894 23:49:31.543655 u2DelayCellOfst[7]=6 cells (2 PI)
8895 23:49:31.547185 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8896 23:49:31.550802 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8897 23:49:31.553537 == TX Byte 1 ==
8898 23:49:31.557124 u2DelayCellOfst[8]=0 cells (0 PI)
8899 23:49:31.557304 u2DelayCellOfst[9]=3 cells (1 PI)
8900 23:49:31.560159 u2DelayCellOfst[10]=10 cells (3 PI)
8901 23:49:31.563831 u2DelayCellOfst[11]=3 cells (1 PI)
8902 23:49:31.567000 u2DelayCellOfst[12]=13 cells (4 PI)
8903 23:49:31.569978 u2DelayCellOfst[13]=13 cells (4 PI)
8904 23:49:31.573566 u2DelayCellOfst[14]=13 cells (4 PI)
8905 23:49:31.576824 u2DelayCellOfst[15]=16 cells (5 PI)
8906 23:49:31.580219 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8907 23:49:31.586918 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8908 23:49:31.587010 DramC Write-DBI on
8909 23:49:31.587096 ==
8910 23:49:31.590525 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 23:49:31.597172 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 23:49:31.597278 ==
8913 23:49:31.597379
8914 23:49:31.597478
8915 23:49:31.597574 TX Vref Scan disable
8916 23:49:31.600305 == TX Byte 0 ==
8917 23:49:31.603675 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8918 23:49:31.607383 == TX Byte 1 ==
8919 23:49:31.610488 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8920 23:49:31.613898 DramC Write-DBI off
8921 23:49:31.613989
8922 23:49:31.614074 [DATLAT]
8923 23:49:31.614153 Freq=1600, CH1 RK1
8924 23:49:31.614232
8925 23:49:31.617046 DATLAT Default: 0xf
8926 23:49:31.617157 0, 0xFFFF, sum = 0
8927 23:49:31.620487 1, 0xFFFF, sum = 0
8928 23:49:31.620578 2, 0xFFFF, sum = 0
8929 23:49:31.623852 3, 0xFFFF, sum = 0
8930 23:49:31.627228 4, 0xFFFF, sum = 0
8931 23:49:31.627338 5, 0xFFFF, sum = 0
8932 23:49:31.630503 6, 0xFFFF, sum = 0
8933 23:49:31.630612 7, 0xFFFF, sum = 0
8934 23:49:31.634002 8, 0xFFFF, sum = 0
8935 23:49:31.634111 9, 0xFFFF, sum = 0
8936 23:49:31.636835 10, 0xFFFF, sum = 0
8937 23:49:31.636941 11, 0xFFFF, sum = 0
8938 23:49:31.640265 12, 0xFFFF, sum = 0
8939 23:49:31.640378 13, 0xFFFF, sum = 0
8940 23:49:31.643723 14, 0x0, sum = 1
8941 23:49:31.643829 15, 0x0, sum = 2
8942 23:49:31.647156 16, 0x0, sum = 3
8943 23:49:31.647259 17, 0x0, sum = 4
8944 23:49:31.649991 best_step = 15
8945 23:49:31.650092
8946 23:49:31.650187 ==
8947 23:49:31.653511 Dram Type= 6, Freq= 0, CH_1, rank 1
8948 23:49:31.657001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8949 23:49:31.657108 ==
8950 23:49:31.660251 RX Vref Scan: 0
8951 23:49:31.660364
8952 23:49:31.660441 RX Vref 0 -> 0, step: 1
8953 23:49:31.660504
8954 23:49:31.663712 RX Delay 19 -> 252, step: 4
8955 23:49:31.667143 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8956 23:49:31.673530 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8957 23:49:31.676483 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8958 23:49:31.680336 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8959 23:49:31.683158 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8960 23:49:31.686960 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8961 23:49:31.689951 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8962 23:49:31.696297 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8963 23:49:31.699957 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8964 23:49:31.703318 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8965 23:49:31.706513 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8966 23:49:31.713548 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8967 23:49:31.716671 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8968 23:49:31.719827 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8969 23:49:31.723485 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8970 23:49:31.727012 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8971 23:49:31.727191 ==
8972 23:49:31.729670 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 23:49:31.736261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 23:49:31.736382 ==
8975 23:49:31.736499 DQS Delay:
8976 23:49:31.740266 DQS0 = 0, DQS1 = 0
8977 23:49:31.740380 DQM Delay:
8978 23:49:31.743470 DQM0 = 134, DQM1 = 130
8979 23:49:31.743626 DQ Delay:
8980 23:49:31.746276 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8981 23:49:31.749870 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8982 23:49:31.753208 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
8983 23:49:31.756719 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
8984 23:49:31.756812
8985 23:49:31.756891
8986 23:49:31.756964
8987 23:49:31.759410 [DramC_TX_OE_Calibration] TA2
8988 23:49:31.763036 Original DQ_B0 (3 6) =30, OEN = 27
8989 23:49:31.766286 Original DQ_B1 (3 6) =30, OEN = 27
8990 23:49:31.769749 24, 0x0, End_B0=24 End_B1=24
8991 23:49:31.773246 25, 0x0, End_B0=25 End_B1=25
8992 23:49:31.773330 26, 0x0, End_B0=26 End_B1=26
8993 23:49:31.776593 27, 0x0, End_B0=27 End_B1=27
8994 23:49:31.779840 28, 0x0, End_B0=28 End_B1=28
8995 23:49:31.783246 29, 0x0, End_B0=29 End_B1=29
8996 23:49:31.783355 30, 0x0, End_B0=30 End_B1=30
8997 23:49:31.786062 31, 0x4141, End_B0=30 End_B1=30
8998 23:49:31.789653 Byte0 end_step=30 best_step=27
8999 23:49:31.792939 Byte1 end_step=30 best_step=27
9000 23:49:31.796292 Byte0 TX OE(2T, 0.5T) = (3, 3)
9001 23:49:31.799510 Byte1 TX OE(2T, 0.5T) = (3, 3)
9002 23:49:31.799594
9003 23:49:31.799677
9004 23:49:31.806217 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
9005 23:49:31.809673 CH1 RK1: MR19=303, MR18=2409
9006 23:49:31.816235 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
9007 23:49:31.819380 [RxdqsGatingPostProcess] freq 1600
9008 23:49:31.823011 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9009 23:49:31.825819 best DQS0 dly(2T, 0.5T) = (1, 1)
9010 23:49:31.829163 best DQS1 dly(2T, 0.5T) = (1, 1)
9011 23:49:31.832565 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9012 23:49:31.836092 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9013 23:49:31.839247 best DQS0 dly(2T, 0.5T) = (1, 1)
9014 23:49:31.842858 best DQS1 dly(2T, 0.5T) = (1, 1)
9015 23:49:31.846246 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9016 23:49:31.849060 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9017 23:49:31.852485 Pre-setting of DQS Precalculation
9018 23:49:31.856080 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9019 23:49:31.862460 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9020 23:49:31.872882 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9021 23:49:31.872984
9022 23:49:31.873070
9023 23:49:31.876264 [Calibration Summary] 3200 Mbps
9024 23:49:31.876397 CH 0, Rank 0
9025 23:49:31.879164 SW Impedance : PASS
9026 23:49:31.879248 DUTY Scan : NO K
9027 23:49:31.882634 ZQ Calibration : PASS
9028 23:49:31.882756 Jitter Meter : NO K
9029 23:49:31.885951 CBT Training : PASS
9030 23:49:31.889573 Write leveling : PASS
9031 23:49:31.889657 RX DQS gating : PASS
9032 23:49:31.892828 RX DQ/DQS(RDDQC) : PASS
9033 23:49:31.896070 TX DQ/DQS : PASS
9034 23:49:31.896153 RX DATLAT : PASS
9035 23:49:31.898985 RX DQ/DQS(Engine): PASS
9036 23:49:31.902779 TX OE : PASS
9037 23:49:31.902864 All Pass.
9038 23:49:31.902947
9039 23:49:31.903026 CH 0, Rank 1
9040 23:49:31.905559 SW Impedance : PASS
9041 23:49:31.909016 DUTY Scan : NO K
9042 23:49:31.909103 ZQ Calibration : PASS
9043 23:49:31.912471 Jitter Meter : NO K
9044 23:49:31.916025 CBT Training : PASS
9045 23:49:31.916109 Write leveling : PASS
9046 23:49:31.919269 RX DQS gating : PASS
9047 23:49:31.922433 RX DQ/DQS(RDDQC) : PASS
9048 23:49:31.922537 TX DQ/DQS : PASS
9049 23:49:31.925597 RX DATLAT : PASS
9050 23:49:31.925703 RX DQ/DQS(Engine): PASS
9051 23:49:31.928946 TX OE : PASS
9052 23:49:31.929055 All Pass.
9053 23:49:31.929179
9054 23:49:31.932220 CH 1, Rank 0
9055 23:49:31.932354 SW Impedance : PASS
9056 23:49:31.935590 DUTY Scan : NO K
9057 23:49:31.939396 ZQ Calibration : PASS
9058 23:49:31.939474 Jitter Meter : NO K
9059 23:49:31.942427 CBT Training : PASS
9060 23:49:31.946056 Write leveling : PASS
9061 23:49:31.946163 RX DQS gating : PASS
9062 23:49:31.949174 RX DQ/DQS(RDDQC) : PASS
9063 23:49:31.952646 TX DQ/DQS : PASS
9064 23:49:31.952727 RX DATLAT : PASS
9065 23:49:31.955658 RX DQ/DQS(Engine): PASS
9066 23:49:31.958949 TX OE : PASS
9067 23:49:31.959042 All Pass.
9068 23:49:31.959105
9069 23:49:31.959171 CH 1, Rank 1
9070 23:49:31.962055 SW Impedance : PASS
9071 23:49:31.966043 DUTY Scan : NO K
9072 23:49:31.966148 ZQ Calibration : PASS
9073 23:49:31.968837 Jitter Meter : NO K
9074 23:49:31.972270 CBT Training : PASS
9075 23:49:31.972408 Write leveling : PASS
9076 23:49:31.975763 RX DQS gating : PASS
9077 23:49:31.979260 RX DQ/DQS(RDDQC) : PASS
9078 23:49:31.979332 TX DQ/DQS : PASS
9079 23:49:31.982643 RX DATLAT : PASS
9080 23:49:31.982717 RX DQ/DQS(Engine): PASS
9081 23:49:31.985429 TX OE : PASS
9082 23:49:31.985519 All Pass.
9083 23:49:31.985582
9084 23:49:31.988890 DramC Write-DBI on
9085 23:49:31.992333 PER_BANK_REFRESH: Hybrid Mode
9086 23:49:31.992450 TX_TRACKING: ON
9087 23:49:32.002451 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9088 23:49:32.008560 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9089 23:49:32.019061 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9090 23:49:32.021894 [FAST_K] Save calibration result to emmc
9091 23:49:32.022002 sync common calibartion params.
9092 23:49:32.025253 sync cbt_mode0:1, 1:1
9093 23:49:32.028546 dram_init: ddr_geometry: 2
9094 23:49:32.032414 dram_init: ddr_geometry: 2
9095 23:49:32.032492 dram_init: ddr_geometry: 2
9096 23:49:32.035568 0:dram_rank_size:100000000
9097 23:49:32.038940 1:dram_rank_size:100000000
9098 23:49:32.042400 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9099 23:49:32.045778 DFS_SHUFFLE_HW_MODE: ON
9100 23:49:32.048709 dramc_set_vcore_voltage set vcore to 725000
9101 23:49:32.051941 Read voltage for 1600, 0
9102 23:49:32.052023 Vio18 = 0
9103 23:49:32.055101 Vcore = 725000
9104 23:49:32.055184 Vdram = 0
9105 23:49:32.055267 Vddq = 0
9106 23:49:32.055345 Vmddr = 0
9107 23:49:32.059063 switch to 3200 Mbps bootup
9108 23:49:32.062215 [DramcRunTimeConfig]
9109 23:49:32.062299 PHYPLL
9110 23:49:32.065643 DPM_CONTROL_AFTERK: ON
9111 23:49:32.065739 PER_BANK_REFRESH: ON
9112 23:49:32.068674 REFRESH_OVERHEAD_REDUCTION: ON
9113 23:49:32.071713 CMD_PICG_NEW_MODE: OFF
9114 23:49:32.071890 XRTWTW_NEW_MODE: ON
9115 23:49:32.075237 XRTRTR_NEW_MODE: ON
9116 23:49:32.075335 TX_TRACKING: ON
9117 23:49:32.078728 RDSEL_TRACKING: OFF
9118 23:49:32.078811 DQS Precalculation for DVFS: ON
9119 23:49:32.081900 RX_TRACKING: OFF
9120 23:49:32.081982 HW_GATING DBG: ON
9121 23:49:32.085108 ZQCS_ENABLE_LP4: ON
9122 23:49:32.088372 RX_PICG_NEW_MODE: ON
9123 23:49:32.088455 TX_PICG_NEW_MODE: ON
9124 23:49:32.091858 ENABLE_RX_DCM_DPHY: ON
9125 23:49:32.095235 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9126 23:49:32.095316 DUMMY_READ_FOR_TRACKING: OFF
9127 23:49:32.098621 !!! SPM_CONTROL_AFTERK: OFF
9128 23:49:32.102168 !!! SPM could not control APHY
9129 23:49:32.104902 IMPEDANCE_TRACKING: ON
9130 23:49:32.105007 TEMP_SENSOR: ON
9131 23:49:32.108231 HW_SAVE_FOR_SR: OFF
9132 23:49:32.111685 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9133 23:49:32.115109 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9134 23:49:32.115214 Read ODT Tracking: ON
9135 23:49:32.118467 Refresh Rate DeBounce: ON
9136 23:49:32.121584 DFS_NO_QUEUE_FLUSH: ON
9137 23:49:32.125278 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9138 23:49:32.125380 ENABLE_DFS_RUNTIME_MRW: OFF
9139 23:49:32.128015 DDR_RESERVE_NEW_MODE: ON
9140 23:49:32.131275 MR_CBT_SWITCH_FREQ: ON
9141 23:49:32.131367 =========================
9142 23:49:32.151915 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9143 23:49:32.155151 dram_init: ddr_geometry: 2
9144 23:49:32.173345 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9145 23:49:32.176737 dram_init: dram init end (result: 0)
9146 23:49:32.182772 DRAM-K: Full calibration passed in 24483 msecs
9147 23:49:32.186583 MRC: failed to locate region type 0.
9148 23:49:32.186694 DRAM rank0 size:0x100000000,
9149 23:49:32.189648 DRAM rank1 size=0x100000000
9150 23:49:32.199597 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9151 23:49:32.206528 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9152 23:49:32.213213 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9153 23:49:32.219500 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9154 23:49:32.223144 DRAM rank0 size:0x100000000,
9155 23:49:32.226352 DRAM rank1 size=0x100000000
9156 23:49:32.226463 CBMEM:
9157 23:49:32.229837 IMD: root @ 0xfffff000 254 entries.
9158 23:49:32.233292 IMD: root @ 0xffffec00 62 entries.
9159 23:49:32.235996 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9160 23:49:32.239575 WARNING: RO_VPD is uninitialized or empty.
9161 23:49:32.246253 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9162 23:49:32.253301 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9163 23:49:32.266134 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9164 23:49:32.276797 BS: romstage times (exec / console): total (unknown) / 24007 ms
9165 23:49:32.276937
9166 23:49:32.277039
9167 23:49:32.287351 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9168 23:49:32.290517 ARM64: Exception handlers installed.
9169 23:49:32.293539 ARM64: Testing exception
9170 23:49:32.296837 ARM64: Done test exception
9171 23:49:32.296925 Enumerating buses...
9172 23:49:32.300640 Show all devs... Before device enumeration.
9173 23:49:32.303899 Root Device: enabled 1
9174 23:49:32.307337 CPU_CLUSTER: 0: enabled 1
9175 23:49:32.307446 CPU: 00: enabled 1
9176 23:49:32.310020 Compare with tree...
9177 23:49:32.310129 Root Device: enabled 1
9178 23:49:32.313191 CPU_CLUSTER: 0: enabled 1
9179 23:49:32.317091 CPU: 00: enabled 1
9180 23:49:32.317204 Root Device scanning...
9181 23:49:32.320103 scan_static_bus for Root Device
9182 23:49:32.323658 CPU_CLUSTER: 0 enabled
9183 23:49:32.326418 scan_static_bus for Root Device done
9184 23:49:32.330053 scan_bus: bus Root Device finished in 8 msecs
9185 23:49:32.330167 done
9186 23:49:32.336701 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9187 23:49:32.340253 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9188 23:49:32.346268 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9189 23:49:32.349836 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9190 23:49:32.353420 Allocating resources...
9191 23:49:32.356734 Reading resources...
9192 23:49:32.360021 Root Device read_resources bus 0 link: 0
9193 23:49:32.363239 DRAM rank0 size:0x100000000,
9194 23:49:32.363357 DRAM rank1 size=0x100000000
9195 23:49:32.366465 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9196 23:49:32.369648 CPU: 00 missing read_resources
9197 23:49:32.376659 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9198 23:49:32.379954 Root Device read_resources bus 0 link: 0 done
9199 23:49:32.380069 Done reading resources.
9200 23:49:32.386724 Show resources in subtree (Root Device)...After reading.
9201 23:49:32.389596 Root Device child on link 0 CPU_CLUSTER: 0
9202 23:49:32.392874 CPU_CLUSTER: 0 child on link 0 CPU: 00
9203 23:49:32.403192 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9204 23:49:32.403280 CPU: 00
9205 23:49:32.406334 Root Device assign_resources, bus 0 link: 0
9206 23:49:32.410234 CPU_CLUSTER: 0 missing set_resources
9207 23:49:32.416206 Root Device assign_resources, bus 0 link: 0 done
9208 23:49:32.416332 Done setting resources.
9209 23:49:32.423223 Show resources in subtree (Root Device)...After assigning values.
9210 23:49:32.426568 Root Device child on link 0 CPU_CLUSTER: 0
9211 23:49:32.429953 CPU_CLUSTER: 0 child on link 0 CPU: 00
9212 23:49:32.439831 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9213 23:49:32.439924 CPU: 00
9214 23:49:32.442867 Done allocating resources.
9215 23:49:32.446198 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9216 23:49:32.449841 Enabling resources...
9217 23:49:32.449929 done.
9218 23:49:32.455951 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9219 23:49:32.456107 Initializing devices...
9220 23:49:32.459426 Root Device init
9221 23:49:32.459510 init hardware done!
9222 23:49:32.462865 0x00000018: ctrlr->caps
9223 23:49:32.466243 52.000 MHz: ctrlr->f_max
9224 23:49:32.466353 0.400 MHz: ctrlr->f_min
9225 23:49:32.469588 0x40ff8080: ctrlr->voltages
9226 23:49:32.469686 sclk: 390625
9227 23:49:32.472789 Bus Width = 1
9228 23:49:32.472869 sclk: 390625
9229 23:49:32.476219 Bus Width = 1
9230 23:49:32.476325 Early init status = 3
9231 23:49:32.482614 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9232 23:49:32.486293 in-header: 03 fc 00 00 01 00 00 00
9233 23:49:32.486374 in-data: 00
9234 23:49:32.492452 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9235 23:49:32.496289 in-header: 03 fd 00 00 00 00 00 00
9236 23:49:32.499262 in-data:
9237 23:49:32.502722 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9238 23:49:32.506275 in-header: 03 fc 00 00 01 00 00 00
9239 23:49:32.509525 in-data: 00
9240 23:49:32.512775 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9241 23:49:32.517304 in-header: 03 fd 00 00 00 00 00 00
9242 23:49:32.520736 in-data:
9243 23:49:32.524228 [SSUSB] Setting up USB HOST controller...
9244 23:49:32.527136 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9245 23:49:32.530724 [SSUSB] phy power-on done.
9246 23:49:32.533796 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9247 23:49:32.540556 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9248 23:49:32.543893 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9249 23:49:32.550549 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9250 23:49:32.557082 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9251 23:49:32.563241 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9252 23:49:32.569884 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9253 23:49:32.576559 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9254 23:49:32.579945 SPM: binary array size = 0x9dc
9255 23:49:32.583547 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9256 23:49:32.590285 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9257 23:49:32.596739 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9258 23:49:32.602893 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9259 23:49:32.606235 configure_display: Starting display init
9260 23:49:32.640809 anx7625_power_on_init: Init interface.
9261 23:49:32.643573 anx7625_disable_pd_protocol: Disabled PD feature.
9262 23:49:32.647160 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9263 23:49:32.674902 anx7625_start_dp_work: Secure OCM version=00
9264 23:49:32.678161 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9265 23:49:32.692918 sp_tx_get_edid_block: EDID Block = 1
9266 23:49:32.795425 Extracted contents:
9267 23:49:32.798988 header: 00 ff ff ff ff ff ff 00
9268 23:49:32.801951 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9269 23:49:32.805671 version: 01 04
9270 23:49:32.808628 basic params: 95 1f 11 78 0a
9271 23:49:32.811788 chroma info: 76 90 94 55 54 90 27 21 50 54
9272 23:49:32.815240 established: 00 00 00
9273 23:49:32.821781 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9274 23:49:32.825039 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9275 23:49:32.831950 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9276 23:49:32.838378 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9277 23:49:32.844954 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9278 23:49:32.848794 extensions: 00
9279 23:49:32.848913 checksum: fb
9280 23:49:32.849039
9281 23:49:32.851616 Manufacturer: IVO Model 57d Serial Number 0
9282 23:49:32.855199 Made week 0 of 2020
9283 23:49:32.855311 EDID version: 1.4
9284 23:49:32.858622 Digital display
9285 23:49:32.861523 6 bits per primary color channel
9286 23:49:32.861639 DisplayPort interface
9287 23:49:32.864982 Maximum image size: 31 cm x 17 cm
9288 23:49:32.868371 Gamma: 220%
9289 23:49:32.868489 Check DPMS levels
9290 23:49:32.871973 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9291 23:49:32.875385 First detailed timing is preferred timing
9292 23:49:32.878293 Established timings supported:
9293 23:49:32.881687 Standard timings supported:
9294 23:49:32.885122 Detailed timings
9295 23:49:32.888642 Hex of detail: 383680a07038204018303c0035ae10000019
9296 23:49:32.891372 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9297 23:49:32.898336 0780 0798 07c8 0820 hborder 0
9298 23:49:32.901765 0438 043b 0447 0458 vborder 0
9299 23:49:32.904863 -hsync -vsync
9300 23:49:32.904977 Did detailed timing
9301 23:49:32.908214 Hex of detail: 000000000000000000000000000000000000
9302 23:49:32.911575 Manufacturer-specified data, tag 0
9303 23:49:32.918700 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9304 23:49:32.918811 ASCII string: InfoVision
9305 23:49:32.925331 Hex of detail: 000000fe00523134304e574635205248200a
9306 23:49:32.928230 ASCII string: R140NWF5 RH
9307 23:49:32.928333 Checksum
9308 23:49:32.928434 Checksum: 0xfb (valid)
9309 23:49:32.935059 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9310 23:49:32.938282 DSI data_rate: 832800000 bps
9311 23:49:32.941719 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9312 23:49:32.948500 anx7625_parse_edid: pixelclock(138800).
9313 23:49:32.951401 hactive(1920), hsync(48), hfp(24), hbp(88)
9314 23:49:32.955104 vactive(1080), vsync(12), vfp(3), vbp(17)
9315 23:49:32.958543 anx7625_dsi_config: config dsi.
9316 23:49:32.964855 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9317 23:49:32.977544 anx7625_dsi_config: success to config DSI
9318 23:49:32.980887 anx7625_dp_start: MIPI phy setup OK.
9319 23:49:32.983787 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9320 23:49:32.987206 mtk_ddp_mode_set invalid vrefresh 60
9321 23:49:32.990571 main_disp_path_setup
9322 23:49:32.990653 ovl_layer_smi_id_en
9323 23:49:32.994111 ovl_layer_smi_id_en
9324 23:49:32.994233 ccorr_config
9325 23:49:32.994338 aal_config
9326 23:49:32.997564 gamma_config
9327 23:49:32.997684 postmask_config
9328 23:49:33.000888 dither_config
9329 23:49:33.004281 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9330 23:49:33.012176 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9331 23:49:33.014436 Root Device init finished in 551 msecs
9332 23:49:33.014551 CPU_CLUSTER: 0 init
9333 23:49:33.024146 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9334 23:49:33.027514 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9335 23:49:33.030707 APU_MBOX 0x190000b0 = 0x10001
9336 23:49:33.034254 APU_MBOX 0x190001b0 = 0x10001
9337 23:49:33.037512 APU_MBOX 0x190005b0 = 0x10001
9338 23:49:33.040671 APU_MBOX 0x190006b0 = 0x10001
9339 23:49:33.043633 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9340 23:49:33.056738 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9341 23:49:33.069161 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9342 23:49:33.075293 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9343 23:49:33.087106 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9344 23:49:33.096251 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9345 23:49:33.099655 CPU_CLUSTER: 0 init finished in 81 msecs
9346 23:49:33.103230 Devices initialized
9347 23:49:33.106598 Show all devs... After init.
9348 23:49:33.106705 Root Device: enabled 1
9349 23:49:33.109990 CPU_CLUSTER: 0: enabled 1
9350 23:49:33.112655 CPU: 00: enabled 1
9351 23:49:33.116034 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9352 23:49:33.119859 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9353 23:49:33.123084 ELOG: NV offset 0x57f000 size 0x1000
9354 23:49:33.129300 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9355 23:49:33.136141 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9356 23:49:33.139594 ELOG: Event(17) added with size 13 at 2024-06-04 23:44:51 UTC
9357 23:49:33.145745 out: cmd=0x121: 03 db 21 01 00 00 00 00
9358 23:49:33.149357 in-header: 03 bb 00 00 2c 00 00 00
9359 23:49:33.159479 in-data: a4 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9360 23:49:33.165682 ELOG: Event(A1) added with size 10 at 2024-06-04 23:44:51 UTC
9361 23:49:33.172748 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9362 23:49:33.179366 ELOG: Event(A0) added with size 9 at 2024-06-04 23:44:51 UTC
9363 23:49:33.182304 elog_add_boot_reason: Logged dev mode boot
9364 23:49:33.188863 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9365 23:49:33.188972 Finalize devices...
9366 23:49:33.192089 Devices finalized
9367 23:49:33.195250 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9368 23:49:33.199041 Writing coreboot table at 0xffe64000
9369 23:49:33.202157 0. 000000000010a000-0000000000113fff: RAMSTAGE
9370 23:49:33.205560 1. 0000000040000000-00000000400fffff: RAM
9371 23:49:33.211940 2. 0000000040100000-000000004032afff: RAMSTAGE
9372 23:49:33.215341 3. 000000004032b000-00000000545fffff: RAM
9373 23:49:33.218731 4. 0000000054600000-000000005465ffff: BL31
9374 23:49:33.222056 5. 0000000054660000-00000000ffe63fff: RAM
9375 23:49:33.228840 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9376 23:49:33.232275 7. 0000000100000000-000000023fffffff: RAM
9377 23:49:33.235746 Passing 5 GPIOs to payload:
9378 23:49:33.239178 NAME | PORT | POLARITY | VALUE
9379 23:49:33.241803 EC in RW | 0x000000aa | low | undefined
9380 23:49:33.248850 EC interrupt | 0x00000005 | low | undefined
9381 23:49:33.252201 TPM interrupt | 0x000000ab | high | undefined
9382 23:49:33.258444 SD card detect | 0x00000011 | high | undefined
9383 23:49:33.261802 speaker enable | 0x00000093 | high | undefined
9384 23:49:33.265223 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9385 23:49:33.268428 in-header: 03 f9 00 00 02 00 00 00
9386 23:49:33.271717 in-data: 02 00
9387 23:49:33.271848 ADC[4]: Raw value=903988 ID=7
9388 23:49:33.275637 ADC[3]: Raw value=213441 ID=1
9389 23:49:33.278770 RAM Code: 0x71
9390 23:49:33.278879 ADC[6]: Raw value=75332 ID=0
9391 23:49:33.281890 ADC[5]: Raw value=212703 ID=1
9392 23:49:33.285308 SKU Code: 0x1
9393 23:49:33.288760 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3b2d
9394 23:49:33.292245 coreboot table: 964 bytes.
9395 23:49:33.295097 IMD ROOT 0. 0xfffff000 0x00001000
9396 23:49:33.298540 IMD SMALL 1. 0xffffe000 0x00001000
9397 23:49:33.301846 RO MCACHE 2. 0xffffc000 0x00001104
9398 23:49:33.305447 CONSOLE 3. 0xfff7c000 0x00080000
9399 23:49:33.308504 FMAP 4. 0xfff7b000 0x00000452
9400 23:49:33.311738 TIME STAMP 5. 0xfff7a000 0x00000910
9401 23:49:33.314909 VBOOT WORK 6. 0xfff66000 0x00014000
9402 23:49:33.318320 RAMOOPS 7. 0xffe66000 0x00100000
9403 23:49:33.321587 COREBOOT 8. 0xffe64000 0x00002000
9404 23:49:33.321690 IMD small region:
9405 23:49:33.328489 IMD ROOT 0. 0xffffec00 0x00000400
9406 23:49:33.331649 VPD 1. 0xffffeb80 0x0000006c
9407 23:49:33.335032 MMC STATUS 2. 0xffffeb60 0x00000004
9408 23:49:33.338628 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9409 23:49:33.341194 Probing TPM: done!
9410 23:49:33.345203 Connected to device vid:did:rid of 1ae0:0028:00
9411 23:49:33.355510 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9412 23:49:33.358474 Initialized TPM device CR50 revision 0
9413 23:49:33.362457 Checking cr50 for pending updates
9414 23:49:33.365870 Reading cr50 TPM mode
9415 23:49:33.374569 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9416 23:49:33.381134 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9417 23:49:33.421235 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9418 23:49:33.424830 Checking segment from ROM address 0x40100000
9419 23:49:33.428305 Checking segment from ROM address 0x4010001c
9420 23:49:33.434493 Loading segment from ROM address 0x40100000
9421 23:49:33.434609 code (compression=0)
9422 23:49:33.445194 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9423 23:49:33.451566 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9424 23:49:33.451696 it's not compressed!
9425 23:49:33.458333 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9426 23:49:33.461702 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9427 23:49:33.481923 Loading segment from ROM address 0x4010001c
9428 23:49:33.482057 Entry Point 0x80000000
9429 23:49:33.485039 Loaded segments
9430 23:49:33.488540 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9431 23:49:33.495472 Jumping to boot code at 0x80000000(0xffe64000)
9432 23:49:33.502051 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9433 23:49:33.508618 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9434 23:49:33.516721 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9435 23:49:33.519314 Checking segment from ROM address 0x40100000
9436 23:49:33.523029 Checking segment from ROM address 0x4010001c
9437 23:49:33.529523 Loading segment from ROM address 0x40100000
9438 23:49:33.529647 code (compression=1)
9439 23:49:33.536000 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9440 23:49:33.546426 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9441 23:49:33.546520 using LZMA
9442 23:49:33.554366 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9443 23:49:33.560969 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9444 23:49:33.564712 Loading segment from ROM address 0x4010001c
9445 23:49:33.564821 Entry Point 0x54601000
9446 23:49:33.568196 Loaded segments
9447 23:49:33.570929 NOTICE: MT8192 bl31_setup
9448 23:49:33.578445 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9449 23:49:33.582179 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9450 23:49:33.585254 WARNING: region 0:
9451 23:49:33.588566 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9452 23:49:33.588682 WARNING: region 1:
9453 23:49:33.595288 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9454 23:49:33.598021 WARNING: region 2:
9455 23:49:33.601455 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9456 23:49:33.604792 WARNING: region 3:
9457 23:49:33.608098 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9458 23:49:33.611466 WARNING: region 4:
9459 23:49:33.614719 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9460 23:49:33.618072 WARNING: region 5:
9461 23:49:33.621551 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 23:49:33.624961 WARNING: region 6:
9463 23:49:33.628319 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 23:49:33.628440 WARNING: region 7:
9465 23:49:33.634766 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 23:49:33.641549 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9467 23:49:33.644930 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9468 23:49:33.648258 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9469 23:49:33.654642 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9470 23:49:33.658557 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9471 23:49:33.662138 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9472 23:49:33.668603 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9473 23:49:33.671827 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9474 23:49:33.675367 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9475 23:49:33.681584 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9476 23:49:33.685117 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9477 23:49:33.691796 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9478 23:49:33.695129 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9479 23:49:33.698311 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9480 23:49:33.705161 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9481 23:49:33.708599 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9482 23:49:33.711839 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9483 23:49:33.718472 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9484 23:49:33.721860 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9485 23:49:33.725355 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9486 23:49:33.732037 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9487 23:49:33.735424 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9488 23:49:33.742076 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9489 23:49:33.744977 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9490 23:49:33.748505 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9491 23:49:33.755236 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9492 23:49:33.758370 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9493 23:49:33.765546 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9494 23:49:33.768836 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9495 23:49:33.771774 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9496 23:49:33.778497 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9497 23:49:33.781943 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9498 23:49:33.785265 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9499 23:49:33.791837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9500 23:49:33.795482 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9501 23:49:33.798423 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9502 23:49:33.802183 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9503 23:49:33.808826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9504 23:49:33.812030 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9505 23:49:33.815374 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9506 23:49:33.818856 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9507 23:49:33.825475 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9508 23:49:33.829017 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9509 23:49:33.831730 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9510 23:49:33.835015 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9511 23:49:33.841960 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9512 23:49:33.845426 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9513 23:49:33.848552 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9514 23:49:33.855589 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9515 23:49:33.858956 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9516 23:49:33.862105 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9517 23:49:33.868920 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9518 23:49:33.872281 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9519 23:49:33.878631 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9520 23:49:33.882050 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9521 23:49:33.885611 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9522 23:49:33.892507 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9523 23:49:33.895831 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9524 23:49:33.902053 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9525 23:49:33.905389 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9526 23:49:33.912250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9527 23:49:33.915395 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9528 23:49:33.922351 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9529 23:49:33.925431 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9530 23:49:33.929000 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9531 23:49:33.935382 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9532 23:49:33.939314 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9533 23:49:33.945929 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9534 23:49:33.948702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9535 23:49:33.955543 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9536 23:49:33.959373 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9537 23:49:33.962304 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9538 23:49:33.969146 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9539 23:49:33.972508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9540 23:49:33.979035 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9541 23:49:33.982461 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9542 23:49:33.988765 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9543 23:49:33.992359 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9544 23:49:33.995957 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9545 23:49:34.002721 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9546 23:49:34.006031 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9547 23:49:34.012243 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9548 23:49:34.015594 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9549 23:49:34.022621 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9550 23:49:34.025989 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9551 23:49:34.029471 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9552 23:49:34.036173 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9553 23:49:34.039218 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9554 23:49:34.045947 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9555 23:49:34.048968 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9556 23:49:34.052890 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9557 23:49:34.058963 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9558 23:49:34.062381 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9559 23:49:34.069210 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9560 23:49:34.072809 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9561 23:49:34.078890 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9562 23:49:34.082441 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9563 23:49:34.085518 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9564 23:49:34.089541 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9565 23:49:34.096457 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9566 23:49:34.099678 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9567 23:49:34.102882 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9568 23:49:34.109043 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9569 23:49:34.112553 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9570 23:49:34.118834 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9571 23:49:34.122358 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9572 23:49:34.125600 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9573 23:49:34.132708 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9574 23:49:34.136229 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9575 23:49:34.142561 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9576 23:49:34.146126 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9577 23:49:34.149322 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9578 23:49:34.156332 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9579 23:49:34.159488 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9580 23:49:34.165570 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9581 23:49:34.169329 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9582 23:49:34.172763 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9583 23:49:34.175906 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9584 23:49:34.182693 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9585 23:49:34.185806 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9586 23:49:34.189169 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9587 23:49:34.192626 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9588 23:49:34.199011 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9589 23:49:34.202864 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9590 23:49:34.206091 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9591 23:49:34.212316 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9592 23:49:34.215911 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9593 23:49:34.222852 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9594 23:49:34.225638 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9595 23:49:34.229101 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9596 23:49:34.235919 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9597 23:49:34.239207 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9598 23:49:34.242505 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9599 23:49:34.249313 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9600 23:49:34.252760 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9601 23:49:34.259659 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9602 23:49:34.262901 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9603 23:49:34.266185 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9604 23:49:34.272754 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9605 23:49:34.276174 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9606 23:49:34.279422 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9607 23:49:34.286145 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9608 23:49:34.289687 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9609 23:49:34.296123 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9610 23:49:34.299418 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9611 23:49:34.302584 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9612 23:49:34.309234 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9613 23:49:34.312865 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9614 23:49:34.319755 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9615 23:49:34.322981 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9616 23:49:34.326247 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9617 23:49:34.333304 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9618 23:49:34.335990 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9619 23:49:34.339595 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9620 23:49:34.345992 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9621 23:49:34.349511 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9622 23:49:34.356301 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9623 23:49:34.360080 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9624 23:49:34.363381 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9625 23:49:34.369663 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9626 23:49:34.373099 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9627 23:49:34.379865 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9628 23:49:34.382588 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9629 23:49:34.386024 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9630 23:49:34.392654 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9631 23:49:34.396036 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9632 23:49:34.399409 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9633 23:49:34.405859 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9634 23:49:34.409472 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9635 23:49:34.416133 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9636 23:49:34.419437 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9637 23:49:34.422603 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9638 23:49:34.429420 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9639 23:49:34.432491 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9640 23:49:34.439543 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9641 23:49:34.443028 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9642 23:49:34.446331 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9643 23:49:34.452820 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9644 23:49:34.456281 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9645 23:49:34.459661 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9646 23:49:34.466398 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9647 23:49:34.469696 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9648 23:49:34.475950 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9649 23:49:34.479294 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9650 23:49:34.482615 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9651 23:49:34.489394 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9652 23:49:34.492752 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9653 23:49:34.499440 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9654 23:49:34.502285 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9655 23:49:34.505650 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9656 23:49:34.512464 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9657 23:49:34.515489 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9658 23:49:34.522565 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9659 23:49:34.525430 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9660 23:49:34.531895 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9661 23:49:34.535194 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9662 23:49:34.538759 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9663 23:49:34.545188 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9664 23:49:34.548925 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9665 23:49:34.555262 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9666 23:49:34.558478 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9667 23:49:34.561856 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9668 23:49:34.568589 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9669 23:49:34.571834 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9670 23:49:34.578602 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9671 23:49:34.582087 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9672 23:49:34.588719 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9673 23:49:34.592010 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9674 23:49:34.595255 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9675 23:49:34.601815 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9676 23:49:34.605156 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9677 23:49:34.612010 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9678 23:49:34.615376 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9679 23:49:34.622365 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9680 23:49:34.625708 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9681 23:49:34.628462 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9682 23:49:34.635255 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9683 23:49:34.638689 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9684 23:49:34.645114 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9685 23:49:34.648143 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9686 23:49:34.651759 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9687 23:49:34.658294 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9688 23:49:34.661723 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9689 23:49:34.668307 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9690 23:49:34.671349 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9691 23:49:34.678424 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9692 23:49:34.681549 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9693 23:49:34.685151 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9694 23:49:34.691223 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9695 23:49:34.694568 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9696 23:49:34.697848 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9697 23:49:34.701294 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9698 23:49:34.708038 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9699 23:49:34.711602 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9700 23:49:34.714965 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9701 23:49:34.721754 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9702 23:49:34.724627 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9703 23:49:34.727917 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9704 23:49:34.734688 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9705 23:49:34.738106 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9706 23:49:34.741683 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9707 23:49:34.748274 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9708 23:49:34.751099 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9709 23:49:34.757816 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9710 23:49:34.761262 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9711 23:49:34.764510 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9712 23:49:34.771266 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9713 23:49:34.774470 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9714 23:49:34.777731 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9715 23:49:34.784490 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9716 23:49:34.787521 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9717 23:49:34.794528 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9718 23:49:34.798001 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9719 23:49:34.800856 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9720 23:49:34.807455 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9721 23:49:34.811148 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9722 23:49:34.814278 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9723 23:49:34.821076 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9724 23:49:34.824631 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9725 23:49:34.827615 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9726 23:49:34.834280 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9727 23:49:34.837734 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9728 23:49:34.844507 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9729 23:49:34.847857 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9730 23:49:34.850557 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9731 23:49:34.857485 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9732 23:49:34.860849 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9733 23:49:34.863859 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9734 23:49:34.870695 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9735 23:49:34.873934 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9736 23:49:34.877379 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9737 23:49:34.880814 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9738 23:49:34.887491 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9739 23:49:34.890425 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9740 23:49:34.893727 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9741 23:49:34.897309 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9742 23:49:34.900772 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9743 23:49:34.907423 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9744 23:49:34.910625 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9745 23:49:34.913778 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9746 23:49:34.920224 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9747 23:49:34.923736 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9748 23:49:34.927234 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9749 23:49:34.934058 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9750 23:49:34.937216 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9751 23:49:34.943743 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9752 23:49:34.947169 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9753 23:49:34.950620 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9754 23:49:34.956885 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9755 23:49:34.960214 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9756 23:49:34.966877 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9757 23:49:34.970338 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9758 23:49:34.973926 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9759 23:49:34.980310 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9760 23:49:34.983587 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9761 23:49:34.990718 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9762 23:49:34.993791 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9763 23:49:34.996882 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9764 23:49:35.003742 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9765 23:49:35.007389 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9766 23:49:35.013582 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9767 23:49:35.016988 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9768 23:49:35.023916 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9769 23:49:35.027113 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9770 23:49:35.030275 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9771 23:49:35.036780 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9772 23:49:35.039986 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9773 23:49:35.043572 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9774 23:49:35.050263 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9775 23:49:35.053249 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9776 23:49:35.060178 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9777 23:49:35.063731 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9778 23:49:35.069894 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9779 23:49:35.073413 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9780 23:49:35.076913 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9781 23:49:35.083045 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9782 23:49:35.086397 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9783 23:49:35.093765 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9784 23:49:35.096377 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9785 23:49:35.099783 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9786 23:49:35.106765 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9787 23:49:35.110103 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9788 23:49:35.116467 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9789 23:49:35.119766 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9790 23:49:35.123107 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9791 23:49:35.129868 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9792 23:49:35.133040 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9793 23:49:35.139700 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9794 23:49:35.143155 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9795 23:49:35.146605 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9796 23:49:35.153136 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9797 23:49:35.156544 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9798 23:49:35.163333 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9799 23:49:35.166708 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9800 23:49:35.172769 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9801 23:49:35.176299 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9802 23:49:35.179725 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9803 23:49:35.186307 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9804 23:49:35.189616 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9805 23:49:35.192981 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9806 23:49:35.199735 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9807 23:49:35.203098 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9808 23:49:35.209653 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9809 23:49:35.212951 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9810 23:49:35.219302 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9811 23:49:35.222815 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9812 23:49:35.226273 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9813 23:49:35.233033 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9814 23:49:35.235825 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9815 23:49:35.242920 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9816 23:49:35.246404 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9817 23:49:35.249201 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9818 23:49:35.255934 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9819 23:49:35.259364 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9820 23:49:35.266127 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9821 23:49:35.269582 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9822 23:49:35.275857 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9823 23:49:35.279268 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9824 23:49:35.282635 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9825 23:49:35.289144 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9826 23:49:35.292310 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9827 23:49:35.299004 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9828 23:49:35.302256 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9829 23:49:35.309208 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9830 23:49:35.312439 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9831 23:49:35.315861 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9832 23:49:35.322426 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9833 23:49:35.325957 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9834 23:49:35.332220 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9835 23:49:35.335653 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9836 23:49:35.342436 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9837 23:49:35.345633 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9838 23:49:35.348987 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9839 23:49:35.355683 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9840 23:49:35.359076 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9841 23:49:35.365787 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9842 23:49:35.369258 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9843 23:49:35.375432 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9844 23:49:35.378811 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9845 23:49:35.382228 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9846 23:49:35.388672 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9847 23:49:35.392024 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9848 23:49:35.398539 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9849 23:49:35.402367 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9850 23:49:35.408573 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9851 23:49:35.412029 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9852 23:49:35.415435 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9853 23:49:35.421801 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9854 23:49:35.425690 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9855 23:49:35.431797 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9856 23:49:35.435359 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9857 23:49:35.442347 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9858 23:49:35.445691 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9859 23:49:35.448898 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9860 23:49:35.455336 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9861 23:49:35.458670 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9862 23:49:35.465469 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9863 23:49:35.468862 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9864 23:49:35.475626 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9865 23:49:35.479001 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9866 23:49:35.485102 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9867 23:49:35.488669 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9868 23:49:35.491963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9869 23:49:35.498719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9870 23:49:35.501472 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9871 23:49:35.508392 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9872 23:49:35.511854 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9873 23:49:35.518066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9874 23:49:35.521447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9875 23:49:35.528479 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9876 23:49:35.531722 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9877 23:49:35.538477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9878 23:49:35.541842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9879 23:49:35.545346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9880 23:49:35.551791 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9881 23:49:35.554829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9882 23:49:35.561757 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9883 23:49:35.564673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9884 23:49:35.571448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9885 23:49:35.574857 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9886 23:49:35.581413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9887 23:49:35.584728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9888 23:49:35.591562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9889 23:49:35.594976 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9890 23:49:35.601219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9891 23:49:35.604509 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9892 23:49:35.611255 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9893 23:49:35.614401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9894 23:49:35.621235 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9895 23:49:35.624603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9896 23:49:35.631345 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9897 23:49:35.634829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9898 23:49:35.641067 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9899 23:49:35.644378 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9900 23:49:35.651339 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9901 23:49:35.651443 INFO: [APUAPC] vio 0
9902 23:49:35.658221 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9903 23:49:35.660949 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9904 23:49:35.664306 INFO: [APUAPC] D0_APC_0: 0x400510
9905 23:49:35.667769 INFO: [APUAPC] D0_APC_1: 0x0
9906 23:49:35.671531 INFO: [APUAPC] D0_APC_2: 0x1540
9907 23:49:35.674644 INFO: [APUAPC] D0_APC_3: 0x0
9908 23:49:35.677974 INFO: [APUAPC] D1_APC_0: 0xffffffff
9909 23:49:35.681557 INFO: [APUAPC] D1_APC_1: 0xffffffff
9910 23:49:35.684968 INFO: [APUAPC] D1_APC_2: 0x3fffff
9911 23:49:35.688170 INFO: [APUAPC] D1_APC_3: 0x0
9912 23:49:35.691435 INFO: [APUAPC] D2_APC_0: 0xffffffff
9913 23:49:35.694603 INFO: [APUAPC] D2_APC_1: 0xffffffff
9914 23:49:35.698022 INFO: [APUAPC] D2_APC_2: 0x3fffff
9915 23:49:35.701077 INFO: [APUAPC] D2_APC_3: 0x0
9916 23:49:35.704858 INFO: [APUAPC] D3_APC_0: 0xffffffff
9917 23:49:35.707917 INFO: [APUAPC] D3_APC_1: 0xffffffff
9918 23:49:35.711477 INFO: [APUAPC] D3_APC_2: 0x3fffff
9919 23:49:35.714772 INFO: [APUAPC] D3_APC_3: 0x0
9920 23:49:35.717369 INFO: [APUAPC] D4_APC_0: 0xffffffff
9921 23:49:35.721247 INFO: [APUAPC] D4_APC_1: 0xffffffff
9922 23:49:35.724808 INFO: [APUAPC] D4_APC_2: 0x3fffff
9923 23:49:35.724923 INFO: [APUAPC] D4_APC_3: 0x0
9924 23:49:35.730708 INFO: [APUAPC] D5_APC_0: 0xffffffff
9925 23:49:35.734033 INFO: [APUAPC] D5_APC_1: 0xffffffff
9926 23:49:35.737504 INFO: [APUAPC] D5_APC_2: 0x3fffff
9927 23:49:35.737586 INFO: [APUAPC] D5_APC_3: 0x0
9928 23:49:35.740924 INFO: [APUAPC] D6_APC_0: 0xffffffff
9929 23:49:35.744456 INFO: [APUAPC] D6_APC_1: 0xffffffff
9930 23:49:35.747517 INFO: [APUAPC] D6_APC_2: 0x3fffff
9931 23:49:35.750985 INFO: [APUAPC] D6_APC_3: 0x0
9932 23:49:35.754448 INFO: [APUAPC] D7_APC_0: 0xffffffff
9933 23:49:35.757284 INFO: [APUAPC] D7_APC_1: 0xffffffff
9934 23:49:35.760589 INFO: [APUAPC] D7_APC_2: 0x3fffff
9935 23:49:35.764051 INFO: [APUAPC] D7_APC_3: 0x0
9936 23:49:35.767454 INFO: [APUAPC] D8_APC_0: 0xffffffff
9937 23:49:35.770820 INFO: [APUAPC] D8_APC_1: 0xffffffff
9938 23:49:35.774241 INFO: [APUAPC] D8_APC_2: 0x3fffff
9939 23:49:35.777587 INFO: [APUAPC] D8_APC_3: 0x0
9940 23:49:35.780778 INFO: [APUAPC] D9_APC_0: 0xffffffff
9941 23:49:35.784267 INFO: [APUAPC] D9_APC_1: 0xffffffff
9942 23:49:35.787472 INFO: [APUAPC] D9_APC_2: 0x3fffff
9943 23:49:35.791092 INFO: [APUAPC] D9_APC_3: 0x0
9944 23:49:35.794228 INFO: [APUAPC] D10_APC_0: 0xffffffff
9945 23:49:35.796959 INFO: [APUAPC] D10_APC_1: 0xffffffff
9946 23:49:35.800645 INFO: [APUAPC] D10_APC_2: 0x3fffff
9947 23:49:35.803725 INFO: [APUAPC] D10_APC_3: 0x0
9948 23:49:35.806981 INFO: [APUAPC] D11_APC_0: 0xffffffff
9949 23:49:35.810658 INFO: [APUAPC] D11_APC_1: 0xffffffff
9950 23:49:35.813793 INFO: [APUAPC] D11_APC_2: 0x3fffff
9951 23:49:35.817374 INFO: [APUAPC] D11_APC_3: 0x0
9952 23:49:35.820587 INFO: [APUAPC] D12_APC_0: 0xffffffff
9953 23:49:35.823697 INFO: [APUAPC] D12_APC_1: 0xffffffff
9954 23:49:35.827367 INFO: [APUAPC] D12_APC_2: 0x3fffff
9955 23:49:35.830352 INFO: [APUAPC] D12_APC_3: 0x0
9956 23:49:35.833511 INFO: [APUAPC] D13_APC_0: 0xffffffff
9957 23:49:35.836873 INFO: [APUAPC] D13_APC_1: 0xffffffff
9958 23:49:35.840249 INFO: [APUAPC] D13_APC_2: 0x3fffff
9959 23:49:35.843851 INFO: [APUAPC] D13_APC_3: 0x0
9960 23:49:35.847101 INFO: [APUAPC] D14_APC_0: 0xffffffff
9961 23:49:35.850531 INFO: [APUAPC] D14_APC_1: 0xffffffff
9962 23:49:35.853715 INFO: [APUAPC] D14_APC_2: 0x3fffff
9963 23:49:35.857245 INFO: [APUAPC] D14_APC_3: 0x0
9964 23:49:35.859908 INFO: [APUAPC] D15_APC_0: 0xffffffff
9965 23:49:35.863399 INFO: [APUAPC] D15_APC_1: 0xffffffff
9966 23:49:35.867034 INFO: [APUAPC] D15_APC_2: 0x3fffff
9967 23:49:35.870452 INFO: [APUAPC] D15_APC_3: 0x0
9968 23:49:35.873718 INFO: [APUAPC] APC_CON: 0x4
9969 23:49:35.877239 INFO: [NOCDAPC] D0_APC_0: 0x0
9970 23:49:35.880676 INFO: [NOCDAPC] D0_APC_1: 0x0
9971 23:49:35.883373 INFO: [NOCDAPC] D1_APC_0: 0x0
9972 23:49:35.886766 INFO: [NOCDAPC] D1_APC_1: 0xfff
9973 23:49:35.886877 INFO: [NOCDAPC] D2_APC_0: 0x0
9974 23:49:35.890049 INFO: [NOCDAPC] D2_APC_1: 0xfff
9975 23:49:35.894012 INFO: [NOCDAPC] D3_APC_0: 0x0
9976 23:49:35.896800 INFO: [NOCDAPC] D3_APC_1: 0xfff
9977 23:49:35.900218 INFO: [NOCDAPC] D4_APC_0: 0x0
9978 23:49:35.903647 INFO: [NOCDAPC] D4_APC_1: 0xfff
9979 23:49:35.906940 INFO: [NOCDAPC] D5_APC_0: 0x0
9980 23:49:35.909652 INFO: [NOCDAPC] D5_APC_1: 0xfff
9981 23:49:35.912987 INFO: [NOCDAPC] D6_APC_0: 0x0
9982 23:49:35.916318 INFO: [NOCDAPC] D6_APC_1: 0xfff
9983 23:49:35.919627 INFO: [NOCDAPC] D7_APC_0: 0x0
9984 23:49:35.923220 INFO: [NOCDAPC] D7_APC_1: 0xfff
9985 23:49:35.926408 INFO: [NOCDAPC] D8_APC_0: 0x0
9986 23:49:35.926512 INFO: [NOCDAPC] D8_APC_1: 0xfff
9987 23:49:35.929653 INFO: [NOCDAPC] D9_APC_0: 0x0
9988 23:49:35.933105 INFO: [NOCDAPC] D9_APC_1: 0xfff
9989 23:49:35.936263 INFO: [NOCDAPC] D10_APC_0: 0x0
9990 23:49:35.939631 INFO: [NOCDAPC] D10_APC_1: 0xfff
9991 23:49:35.942989 INFO: [NOCDAPC] D11_APC_0: 0x0
9992 23:49:35.946273 INFO: [NOCDAPC] D11_APC_1: 0xfff
9993 23:49:35.949412 INFO: [NOCDAPC] D12_APC_0: 0x0
9994 23:49:35.952476 INFO: [NOCDAPC] D12_APC_1: 0xfff
9995 23:49:35.956010 INFO: [NOCDAPC] D13_APC_0: 0x0
9996 23:49:35.959486 INFO: [NOCDAPC] D13_APC_1: 0xfff
9997 23:49:35.962681 INFO: [NOCDAPC] D14_APC_0: 0x0
9998 23:49:35.965847 INFO: [NOCDAPC] D14_APC_1: 0xfff
9999 23:49:35.968805 INFO: [NOCDAPC] D15_APC_0: 0x0
10000 23:49:35.972062 INFO: [NOCDAPC] D15_APC_1: 0xfff
10001 23:49:35.972206 INFO: [NOCDAPC] APC_CON: 0x4
10002 23:49:35.975600 INFO: [APUAPC] set_apusys_apc done
10003 23:49:35.978967 INFO: [DEVAPC] devapc_init done
10004 23:49:35.985907 INFO: GICv3 without legacy support detected.
10005 23:49:35.988989 INFO: ARM GICv3 driver initialized in EL3
10006 23:49:35.992542 INFO: Maximum SPI INTID supported: 639
10007 23:49:35.995825 INFO: BL31: Initializing runtime services
10008 23:49:36.044686 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10009 23:49:36.044820 INFO: SPM: enable CPC mode
10010 23:49:36.044920 INFO: mcdi ready for mcusys-off-idle and system suspend
10011 23:49:36.045011 INFO: BL31: Preparing for EL3 exit to normal world
10012 23:49:36.045100 INFO: Entry point address = 0x80000000
10013 23:49:36.045188 INFO: SPSR = 0x8
10014 23:49:36.045248
10015 23:49:36.045304
10016 23:49:36.045358
10017 23:49:36.045411 Starting depthcharge on Spherion...
10018 23:49:36.045465
10019 23:49:36.045517 Wipe memory regions:
10020 23:49:36.045569
10021 23:49:36.045621 [0x00000040000000, 0x00000054600000)
10022 23:49:36.046291 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10023 23:49:36.046391 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10024 23:49:36.046472 Setting prompt string to ['asurada:']
10025 23:49:36.046553 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10026 23:49:36.154654
10027 23:49:36.154807 [0x00000054660000, 0x00000080000000)
10028 23:49:36.415456
10029 23:49:36.415615 [0x000000821a7280, 0x000000ffe64000)
10030 23:49:37.160735
10031 23:49:37.160898 [0x00000100000000, 0x00000240000000)
10032 23:49:39.050690
10033 23:49:39.054070 Initializing XHCI USB controller at 0x11200000.
10034 23:49:40.091637
10035 23:49:40.094921 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10036 23:49:40.095015
10037 23:49:40.095084
10038 23:49:40.095363 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10040 23:49:40.195686 asurada: tftpboot 192.168.201.1 14172959/tftp-deploy-tcbr0s4c/kernel/image.itb 14172959/tftp-deploy-tcbr0s4c/kernel/cmdline
10041 23:49:40.195866 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10042 23:49:40.195971 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10043 23:49:40.200769 tftpboot 192.168.201.1 14172959/tftp-deploy-tcbr0s4c/kernel/image.itp-deploy-tcbr0s4c/kernel/cmdline
10044 23:49:40.200862
10045 23:49:40.200931 Waiting for link
10046 23:49:40.360876
10047 23:49:40.361008 R8152: Initializing
10048 23:49:40.361077
10049 23:49:40.364104 Version 9 (ocp_data = 6010)
10050 23:49:40.364205
10051 23:49:40.367511 R8152: Done initializing
10052 23:49:40.367583
10053 23:49:40.367645 Adding net device
10054 23:49:42.313078
10055 23:49:42.313252 done.
10056 23:49:42.313350
10057 23:49:42.313440 MAC: 00:e0:4c:78:7a:aa
10058 23:49:42.313536
10059 23:49:42.316498 Sending DHCP discover... done.
10060 23:49:42.316600
10061 23:49:42.319805 Waiting for reply... done.
10062 23:49:42.319986
10063 23:49:42.323164 Sending DHCP request... done.
10064 23:49:42.323265
10065 23:49:42.323357 Waiting for reply... done.
10066 23:49:42.323456
10067 23:49:42.326794 My ip is 192.168.201.12
10068 23:49:42.326900
10069 23:49:42.329911 The DHCP server ip is 192.168.201.1
10070 23:49:42.330014
10071 23:49:42.333200 TFTP server IP predefined by user: 192.168.201.1
10072 23:49:42.333301
10073 23:49:42.339795 Bootfile predefined by user: 14172959/tftp-deploy-tcbr0s4c/kernel/image.itb
10074 23:49:42.339901
10075 23:49:42.342764 Sending tftp read request... done.
10076 23:49:42.342866
10077 23:49:42.346428 Waiting for the transfer...
10078 23:49:42.346533
10079 23:49:42.593190 00000000 ################################################################
10080 23:49:42.593334
10081 23:49:42.837522 00080000 ################################################################
10082 23:49:42.837685
10083 23:49:43.082553 00100000 ################################################################
10084 23:49:43.082716
10085 23:49:43.328426 00180000 ################################################################
10086 23:49:43.328563
10087 23:49:43.576942 00200000 ################################################################
10088 23:49:43.577082
10089 23:49:43.826398 00280000 ################################################################
10090 23:49:43.826538
10091 23:49:44.080112 00300000 ################################################################
10092 23:49:44.080286
10093 23:49:44.328709 00380000 ################################################################
10094 23:49:44.328853
10095 23:49:44.572127 00400000 ################################################################
10096 23:49:44.572288
10097 23:49:44.811997 00480000 ################################################################
10098 23:49:44.812157
10099 23:49:45.052845 00500000 ################################################################
10100 23:49:45.052979
10101 23:49:45.291497 00580000 ################################################################
10102 23:49:45.291635
10103 23:49:45.530362 00600000 ################################################################
10104 23:49:45.530532
10105 23:49:45.772666 00680000 ################################################################
10106 23:49:45.772812
10107 23:49:46.015811 00700000 ################################################################
10108 23:49:46.015959
10109 23:49:46.254558 00780000 ################################################################
10110 23:49:46.254730
10111 23:49:46.490107 00800000 ################################################################
10112 23:49:46.490313
10113 23:49:46.732187 00880000 ################################################################
10114 23:49:46.732363
10115 23:49:46.975604 00900000 ################################################################
10116 23:49:46.975767
10117 23:49:47.214470 00980000 ################################################################
10118 23:49:47.214635
10119 23:49:47.455583 00a00000 ################################################################
10120 23:49:47.455754
10121 23:49:47.698504 00a80000 ################################################################
10122 23:49:47.698662
10123 23:49:47.944748 00b00000 ################################################################
10124 23:49:47.944919
10125 23:49:48.189556 00b80000 ################################################################
10126 23:49:48.189694
10127 23:49:48.431737 00c00000 ################################################################
10128 23:49:48.431917
10129 23:49:48.672542 00c80000 ################################################################
10130 23:49:48.672682
10131 23:49:48.911265 00d00000 ################################################################
10132 23:49:48.911401
10133 23:49:49.159608 00d80000 ################################################################
10134 23:49:49.159764
10135 23:49:49.409652 00e00000 ################################################################
10136 23:49:49.409829
10137 23:49:49.656956 00e80000 ################################################################
10138 23:49:49.657123
10139 23:49:49.903275 00f00000 ################################################################
10140 23:49:49.903424
10141 23:49:50.150959 00f80000 ################################################################
10142 23:49:50.151120
10143 23:49:50.403238 01000000 ################################################################
10144 23:49:50.403379
10145 23:49:50.655199 01080000 ################################################################
10146 23:49:50.655335
10147 23:49:50.904107 01100000 ################################################################
10148 23:49:50.904271
10149 23:49:51.158572 01180000 ################################################################
10150 23:49:51.158714
10151 23:49:51.406455 01200000 ################################################################
10152 23:49:51.406592
10153 23:49:51.651337 01280000 ################################################################
10154 23:49:51.651513
10155 23:49:51.898472 01300000 ################################################################
10156 23:49:51.898628
10157 23:49:52.144913 01380000 ################################################################
10158 23:49:52.145043
10159 23:49:52.392663 01400000 ################################################################
10160 23:49:52.392809
10161 23:49:52.641745 01480000 ################################################################
10162 23:49:52.641905
10163 23:49:52.896137 01500000 ################################################################
10164 23:49:52.896299
10165 23:49:53.147929 01580000 ################################################################
10166 23:49:53.148121
10167 23:49:53.404607 01600000 ################################################################
10168 23:49:53.404768
10169 23:49:53.653956 01680000 ################################################################
10170 23:49:53.654127
10171 23:49:53.903011 01700000 ################################################################
10172 23:49:53.903190
10173 23:49:54.152288 01780000 ################################################################
10174 23:49:54.152445
10175 23:49:54.403414 01800000 ################################################################
10176 23:49:54.403616
10177 23:49:54.653148 01880000 ################################################################
10178 23:49:54.653328
10179 23:49:54.902943 01900000 ################################################################
10180 23:49:54.903130
10181 23:49:55.148249 01980000 ################################################################
10182 23:49:55.148439
10183 23:49:55.393956 01a00000 ################################################################
10184 23:49:55.394132
10185 23:49:55.640358 01a80000 ################################################################
10186 23:49:55.640547
10187 23:49:55.885785 01b00000 ################################################################
10188 23:49:55.885958
10189 23:49:56.127686 01b80000 ################################################################
10190 23:49:56.127965
10191 23:49:56.371550 01c00000 ################################################################
10192 23:49:56.371691
10193 23:49:56.620521 01c80000 ################################################################
10194 23:49:56.620673
10195 23:49:56.862168 01d00000 ################################################################
10196 23:49:56.862311
10197 23:49:57.104855 01d80000 ################################################################
10198 23:49:57.105024
10199 23:49:57.348940 01e00000 ################################################################
10200 23:49:57.349099
10201 23:49:57.594799 01e80000 ################################################################
10202 23:49:57.594932
10203 23:49:57.839969 01f00000 ################################################################
10204 23:49:57.840144
10205 23:49:58.087065 01f80000 ################################################################
10206 23:49:58.087229
10207 23:49:58.332157 02000000 ################################################################
10208 23:49:58.332352
10209 23:49:58.578143 02080000 ################################################################
10210 23:49:58.578283
10211 23:49:58.823717 02100000 ################################################################
10212 23:49:58.823861
10213 23:49:59.073460 02180000 ################################################################
10214 23:49:59.073604
10215 23:49:59.321699 02200000 ################################################################
10216 23:49:59.321846
10217 23:49:59.567792 02280000 ################################################################
10218 23:49:59.567932
10219 23:49:59.812847 02300000 ################################################################
10220 23:49:59.812984
10221 23:50:00.066547 02380000 ################################################################
10222 23:50:00.066685
10223 23:50:00.317166 02400000 ################################################################
10224 23:50:00.317298
10225 23:50:00.563589 02480000 ################################################################
10226 23:50:00.563759
10227 23:50:00.810595 02500000 ################################################################
10228 23:50:00.810753
10229 23:50:01.061445 02580000 ################################################################
10230 23:50:01.061575
10231 23:50:01.307262 02600000 ################################################################
10232 23:50:01.307439
10233 23:50:01.577050 02680000 ################################################################
10234 23:50:01.577182
10235 23:50:01.822286 02700000 ################################################################
10236 23:50:01.822448
10237 23:50:02.069074 02780000 ################################################################
10238 23:50:02.069235
10239 23:50:02.317141 02800000 ################################################################
10240 23:50:02.317280
10241 23:50:02.563725 02880000 ################################################################
10242 23:50:02.563864
10243 23:50:02.813121 02900000 ################################################################
10244 23:50:02.813293
10245 23:50:03.170259 02980000 ################################################################
10246 23:50:03.170405
10247 23:50:03.425201 02a00000 ################################################################
10248 23:50:03.425345
10249 23:50:03.696286 02a80000 ################################################################
10250 23:50:03.696444
10251 23:50:03.953155 02b00000 ################################################################
10252 23:50:03.953294
10253 23:50:04.210796 02b80000 ################################################################
10254 23:50:04.210933
10255 23:50:04.459609 02c00000 ################################################################
10256 23:50:04.459746
10257 23:50:04.713416 02c80000 ################################################################
10258 23:50:04.713557
10259 23:50:04.955871 02d00000 ################################################################
10260 23:50:04.956035
10261 23:50:05.208224 02d80000 ################################################################
10262 23:50:05.208394
10263 23:50:05.457605 02e00000 ################################################################
10264 23:50:05.457748
10265 23:50:05.712766 02e80000 ################################################################
10266 23:50:05.712929
10267 23:50:05.957774 02f00000 ################################################################
10268 23:50:05.957939
10269 23:50:06.207385 02f80000 ################################################################
10270 23:50:06.207518
10271 23:50:06.459303 03000000 ################################################################
10272 23:50:06.459438
10273 23:50:06.712806 03080000 ################################################################
10274 23:50:06.712971
10275 23:50:06.984194 03100000 ################################################################
10276 23:50:06.984351
10277 23:50:07.262535 03180000 ################################################################
10278 23:50:07.262692
10279 23:50:07.784791 03200000 ################################################################
10280 23:50:07.784951
10281 23:50:08.043337 03280000 ################################################################
10282 23:50:08.043476
10283 23:50:08.283570 03300000 ################################################################
10284 23:50:08.283705
10285 23:50:08.527281 03380000 ################################################################
10286 23:50:08.527413
10287 23:50:08.774633 03400000 ################################################################
10288 23:50:08.774804
10289 23:50:09.042293 03480000 ################################################################
10290 23:50:09.042459
10291 23:50:09.300635 03500000 ################################################################
10292 23:50:09.300800
10293 23:50:09.556344 03580000 ################################################################
10294 23:50:09.556486
10295 23:50:09.813778 03600000 ################################################################
10296 23:50:09.813923
10297 23:50:10.070405 03680000 ################################################################
10298 23:50:10.070571
10299 23:50:10.327416 03700000 ################################################################
10300 23:50:10.327546
10301 23:50:10.582827 03780000 ################################################################
10302 23:50:10.583011
10303 23:50:10.835981 03800000 ################################################################
10304 23:50:10.836127
10305 23:50:11.095451 03880000 ################################################################
10306 23:50:11.095597
10307 23:50:11.349039 03900000 ################################################################
10308 23:50:11.349181
10309 23:50:11.601207 03980000 ################################################################
10310 23:50:11.601371
10311 23:50:11.853377 03a00000 ################################################################
10312 23:50:11.853544
10313 23:50:12.107592 03a80000 ################################################################
10314 23:50:12.107760
10315 23:50:12.365514 03b00000 ################################################################
10316 23:50:12.365648
10317 23:50:12.625465 03b80000 ################################################################
10318 23:50:12.625629
10319 23:50:12.885289 03c00000 ################################################################
10320 23:50:12.885420
10321 23:50:13.146220 03c80000 ################################################################
10322 23:50:13.146366
10323 23:50:13.404198 03d00000 ################################################################
10324 23:50:13.404364
10325 23:50:13.657526 03d80000 ################################################################
10326 23:50:13.657695
10327 23:50:13.917285 03e00000 ################################################################
10328 23:50:13.917445
10329 23:50:14.173312 03e80000 ################################################################
10330 23:50:14.173446
10331 23:50:14.427231 03f00000 ################################################################
10332 23:50:14.427394
10333 23:50:14.686536 03f80000 ################################################################
10334 23:50:14.686706
10335 23:50:14.938183 04000000 ################################################################
10336 23:50:14.938357
10337 23:50:15.191538 04080000 ################################################################
10338 23:50:15.191709
10339 23:50:15.440753 04100000 ################################################################
10340 23:50:15.440893
10341 23:50:15.688132 04180000 ################################################################
10342 23:50:15.688276
10343 23:50:15.932216 04200000 ################################################################
10344 23:50:15.932381
10345 23:50:16.176457 04280000 ################################################################
10346 23:50:16.176593
10347 23:50:16.425727 04300000 ################################################################
10348 23:50:16.425893
10349 23:50:16.681267 04380000 ################################################################
10350 23:50:16.681430
10351 23:50:16.928355 04400000 ################################################################
10352 23:50:16.928523
10353 23:50:17.179490 04480000 ################################################################
10354 23:50:17.179656
10355 23:50:17.428086 04500000 ################################################################
10356 23:50:17.428254
10357 23:50:17.680960 04580000 ################################################################
10358 23:50:17.681131
10359 23:50:17.933690 04600000 ################################################################
10360 23:50:17.933837
10361 23:50:18.024984 04680000 ######################## done.
10362 23:50:18.025140
10363 23:50:18.028194 The bootfile was 74118482 bytes long.
10364 23:50:18.028305
10365 23:50:18.031684 Sending tftp read request... done.
10366 23:50:18.031761
10367 23:50:18.034603 Waiting for the transfer...
10368 23:50:18.034712
10369 23:50:18.037955 00000000 # done.
10370 23:50:18.038061
10371 23:50:18.045177 Command line loaded dynamically from TFTP file: 14172959/tftp-deploy-tcbr0s4c/kernel/cmdline
10372 23:50:18.045286
10373 23:50:18.058373 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10374 23:50:18.058487
10375 23:50:18.061180 Loading FIT.
10376 23:50:18.061281
10377 23:50:18.061373 Image ramdisk-1 has 61007758 bytes.
10378 23:50:18.064572
10379 23:50:18.064645 Image fdt-1 has 47258 bytes.
10380 23:50:18.064709
10381 23:50:18.067883 Image kernel-1 has 13061430 bytes.
10382 23:50:18.067982
10383 23:50:18.077859 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10384 23:50:18.077965
10385 23:50:18.094792 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10386 23:50:18.094897
10387 23:50:18.101278 Choosing best match conf-1 for compat google,spherion-rev2.
10388 23:50:18.104408
10389 23:50:18.109537 Connected to device vid:did:rid of 1ae0:0028:00
10390 23:50:18.117269
10391 23:50:18.121222 tpm_get_response: command 0x17b, return code 0x0
10392 23:50:18.121329
10393 23:50:18.123935 ec_init: CrosEC protocol v3 supported (256, 248)
10394 23:50:18.128788
10395 23:50:18.132172 tpm_cleanup: add release locality here.
10396 23:50:18.132246
10397 23:50:18.132309 Shutting down all USB controllers.
10398 23:50:18.132381
10399 23:50:18.135531 Removing current net device
10400 23:50:18.135600
10401 23:50:18.141903 Exiting depthcharge with code 4 at timestamp: 71426012
10402 23:50:18.142009
10403 23:50:18.145129 LZMA decompressing kernel-1 to 0x821a6718
10404 23:50:18.145210
10405 23:50:18.148158 LZMA decompressing kernel-1 to 0x40000000
10406 23:50:19.757576
10407 23:50:19.757715 jumping to kernel
10408 23:50:19.758263 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10409 23:50:19.758361 start: 2.2.5 auto-login-action (timeout 00:03:41) [common]
10410 23:50:19.758441 Setting prompt string to ['Linux version [0-9]']
10411 23:50:19.758511 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10412 23:50:19.758591 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10413 23:50:19.840749
10414 23:50:19.843858 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10415 23:50:19.848018 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10416 23:50:19.848152 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10417 23:50:19.848258 Setting prompt string to []
10418 23:50:19.848374 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10419 23:50:19.848490 Using line separator: #'\n'#
10420 23:50:19.848581 No login prompt set.
10421 23:50:19.848685 Parsing kernel messages
10422 23:50:19.848774 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10423 23:50:19.848947 [login-action] Waiting for messages, (timeout 00:03:41)
10424 23:50:19.849045 Waiting using forced prompt support (timeout 00:01:51)
10425 23:50:19.867714 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j217067-arm64-gcc-10-defconfig-arm64-chromebook-s48tj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024
10426 23:50:19.871189 [ 0.000000] random: crng init done
10427 23:50:19.877127 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10428 23:50:19.880440 [ 0.000000] efi: UEFI not found.
10429 23:50:19.887275 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10430 23:50:19.893944 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10431 23:50:19.903881 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10432 23:50:19.913935 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10433 23:50:19.920554 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10434 23:50:19.926833 [ 0.000000] printk: bootconsole [mtk8250] enabled
10435 23:50:19.930655 [ 0.000000] NUMA: No NUMA configuration found
10436 23:50:19.940549 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10437 23:50:19.943634 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10438 23:50:19.947125 [ 0.000000] Zone ranges:
10439 23:50:19.953800 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10440 23:50:19.956894 [ 0.000000] DMA32 empty
10441 23:50:19.963632 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10442 23:50:19.966735 [ 0.000000] Movable zone start for each node
10443 23:50:19.970365 [ 0.000000] Early memory node ranges
10444 23:50:19.976562 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10445 23:50:19.983735 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10446 23:50:19.990554 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10447 23:50:19.993957 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10448 23:50:20.000018 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10449 23:50:20.007209 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10450 23:50:20.065247 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10451 23:50:20.072251 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10452 23:50:20.078963 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10453 23:50:20.081861 [ 0.000000] psci: probing for conduit method from DT.
10454 23:50:20.088769 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10455 23:50:20.092215 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10456 23:50:20.098921 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10457 23:50:20.102364 [ 0.000000] psci: SMC Calling Convention v1.2
10458 23:50:20.108609 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10459 23:50:20.111865 [ 0.000000] Detected VIPT I-cache on CPU0
10460 23:50:20.118420 [ 0.000000] CPU features: detected: GIC system register CPU interface
10461 23:50:20.124674 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10462 23:50:20.131650 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10463 23:50:20.138103 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10464 23:50:20.144978 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10465 23:50:20.154857 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10466 23:50:20.158395 [ 0.000000] alternatives: applying boot alternatives
10467 23:50:20.164636 [ 0.000000] Fallback order for Node 0: 0
10468 23:50:20.171476 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10469 23:50:20.174800 [ 0.000000] Policy zone: Normal
10470 23:50:20.187934 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10471 23:50:20.197627 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10472 23:50:20.209511 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10473 23:50:20.219592 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10474 23:50:20.226273 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10475 23:50:20.229664 <6>[ 0.000000] software IO TLB: area num 8.
10476 23:50:20.286176 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10477 23:50:20.435405 <6>[ 0.000000] Memory: 7904604K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 448164K reserved, 32768K cma-reserved)
10478 23:50:20.441602 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10479 23:50:20.448225 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10480 23:50:20.451612 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10481 23:50:20.458399 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10482 23:50:20.465173 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10483 23:50:20.468452 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10484 23:50:20.478656 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10485 23:50:20.484786 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10486 23:50:20.491590 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10487 23:50:20.498370 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10488 23:50:20.501759 <6>[ 0.000000] GICv3: 608 SPIs implemented
10489 23:50:20.504716 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10490 23:50:20.511576 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10491 23:50:20.514823 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10492 23:50:20.521575 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10493 23:50:20.534846 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10494 23:50:20.544693 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10495 23:50:20.554571 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10496 23:50:20.561596 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10497 23:50:20.575191 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10498 23:50:20.582131 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10499 23:50:20.588371 <6>[ 0.009178] Console: colour dummy device 80x25
10500 23:50:20.598605 <6>[ 0.013936] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10501 23:50:20.601899 <6>[ 0.024442] pid_max: default: 32768 minimum: 301
10502 23:50:20.608015 <6>[ 0.029345] LSM: Security Framework initializing
10503 23:50:20.615313 <6>[ 0.034283] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10504 23:50:20.625231 <6>[ 0.042102] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10505 23:50:20.631994 <6>[ 0.051528] cblist_init_generic: Setting adjustable number of callback queues.
10506 23:50:20.638559 <6>[ 0.058972] cblist_init_generic: Setting shift to 3 and lim to 1.
10507 23:50:20.648541 <6>[ 0.065350] cblist_init_generic: Setting adjustable number of callback queues.
10508 23:50:20.651858 <6>[ 0.072777] cblist_init_generic: Setting shift to 3 and lim to 1.
10509 23:50:20.658354 <6>[ 0.079178] rcu: Hierarchical SRCU implementation.
10510 23:50:20.664942 <6>[ 0.084225] rcu: Max phase no-delay instances is 1000.
10511 23:50:20.668131 <6>[ 0.091250] EFI services will not be available.
10512 23:50:20.674717 <6>[ 0.096206] smp: Bringing up secondary CPUs ...
10513 23:50:20.682303 <6>[ 0.101259] Detected VIPT I-cache on CPU1
10514 23:50:20.689229 <6>[ 0.101330] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10515 23:50:20.696100 <6>[ 0.101363] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10516 23:50:20.699001 <6>[ 0.101697] Detected VIPT I-cache on CPU2
10517 23:50:20.705752 <6>[ 0.101747] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10518 23:50:20.712460 <6>[ 0.101763] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10519 23:50:20.718936 <6>[ 0.102021] Detected VIPT I-cache on CPU3
10520 23:50:20.725847 <6>[ 0.102068] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10521 23:50:20.732394 <6>[ 0.102082] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10522 23:50:20.735821 <6>[ 0.102386] CPU features: detected: Spectre-v4
10523 23:50:20.742267 <6>[ 0.102393] CPU features: detected: Spectre-BHB
10524 23:50:20.745967 <6>[ 0.102397] Detected PIPT I-cache on CPU4
10525 23:50:20.752320 <6>[ 0.102455] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10526 23:50:20.758892 <6>[ 0.102472] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10527 23:50:20.765391 <6>[ 0.102770] Detected PIPT I-cache on CPU5
10528 23:50:20.772243 <6>[ 0.102833] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10529 23:50:20.779095 <6>[ 0.102848] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10530 23:50:20.782285 <6>[ 0.103130] Detected PIPT I-cache on CPU6
10531 23:50:20.788652 <6>[ 0.103198] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10532 23:50:20.795366 <6>[ 0.103214] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10533 23:50:20.802153 <6>[ 0.103511] Detected PIPT I-cache on CPU7
10534 23:50:20.808963 <6>[ 0.103576] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10535 23:50:20.815057 <6>[ 0.103592] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10536 23:50:20.818470 <6>[ 0.103639] smp: Brought up 1 node, 8 CPUs
10537 23:50:20.825150 <6>[ 0.245081] SMP: Total of 8 processors activated.
10538 23:50:20.828356 <6>[ 0.250002] CPU features: detected: 32-bit EL0 Support
10539 23:50:20.838580 <6>[ 0.255364] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10540 23:50:20.845202 <6>[ 0.264164] CPU features: detected: Common not Private translations
10541 23:50:20.848653 <6>[ 0.270640] CPU features: detected: CRC32 instructions
10542 23:50:20.855107 <6>[ 0.275992] CPU features: detected: RCpc load-acquire (LDAPR)
10543 23:50:20.861762 <6>[ 0.281952] CPU features: detected: LSE atomic instructions
10544 23:50:20.868194 <6>[ 0.287733] CPU features: detected: Privileged Access Never
10545 23:50:20.871728 <6>[ 0.293513] CPU features: detected: RAS Extension Support
10546 23:50:20.881822 <6>[ 0.299156] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10547 23:50:20.885064 <6>[ 0.306375] CPU: All CPU(s) started at EL2
10548 23:50:20.891745 <6>[ 0.310692] alternatives: applying system-wide alternatives
10549 23:50:20.900658 <6>[ 0.321532] devtmpfs: initialized
10550 23:50:20.912819 <6>[ 0.330433] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10551 23:50:20.922389 <6>[ 0.340389] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10552 23:50:20.929091 <6>[ 0.348406] pinctrl core: initialized pinctrl subsystem
10553 23:50:20.932505 <6>[ 0.355085] DMI not present or invalid.
10554 23:50:20.938913 <6>[ 0.359503] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10555 23:50:20.948595 <6>[ 0.366358] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10556 23:50:20.955294 <6>[ 0.373945] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10557 23:50:20.965450 <6>[ 0.382166] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10558 23:50:20.968594 <6>[ 0.390407] audit: initializing netlink subsys (disabled)
10559 23:50:20.978561 <5>[ 0.396101] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10560 23:50:20.985284 <6>[ 0.396815] thermal_sys: Registered thermal governor 'step_wise'
10561 23:50:20.991721 <6>[ 0.404070] thermal_sys: Registered thermal governor 'power_allocator'
10562 23:50:20.994977 <6>[ 0.410322] cpuidle: using governor menu
10563 23:50:21.001495 <6>[ 0.421286] NET: Registered PF_QIPCRTR protocol family
10564 23:50:21.008715 <6>[ 0.426760] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10565 23:50:21.014816 <6>[ 0.433865] ASID allocator initialised with 32768 entries
10566 23:50:21.018191 <6>[ 0.440412] Serial: AMBA PL011 UART driver
10567 23:50:21.028249 <4>[ 0.449244] Trying to register duplicate clock ID: 134
10568 23:50:21.087835 <6>[ 0.512106] KASLR enabled
10569 23:50:21.102140 <6>[ 0.519871] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10570 23:50:21.109054 <6>[ 0.526886] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10571 23:50:21.115169 <6>[ 0.533372] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10572 23:50:21.121826 <6>[ 0.540375] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10573 23:50:21.128569 <6>[ 0.546863] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10574 23:50:21.135226 <6>[ 0.553868] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10575 23:50:21.141334 <6>[ 0.560353] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10576 23:50:21.148199 <6>[ 0.567359] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10577 23:50:21.151597 <6>[ 0.574857] ACPI: Interpreter disabled.
10578 23:50:21.159998 <6>[ 0.581302] iommu: Default domain type: Translated
10579 23:50:21.167096 <6>[ 0.586413] iommu: DMA domain TLB invalidation policy: strict mode
10580 23:50:21.170326 <5>[ 0.593078] SCSI subsystem initialized
10581 23:50:21.177173 <6>[ 0.597243] usbcore: registered new interface driver usbfs
10582 23:50:21.183613 <6>[ 0.602975] usbcore: registered new interface driver hub
10583 23:50:21.186757 <6>[ 0.608529] usbcore: registered new device driver usb
10584 23:50:21.193761 <6>[ 0.614620] pps_core: LinuxPPS API ver. 1 registered
10585 23:50:21.203684 <6>[ 0.619815] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10586 23:50:21.207126 <6>[ 0.629162] PTP clock support registered
10587 23:50:21.209808 <6>[ 0.633404] EDAC MC: Ver: 3.0.0
10588 23:50:21.217489 <6>[ 0.638565] FPGA manager framework
10589 23:50:21.223983 <6>[ 0.642255] Advanced Linux Sound Architecture Driver Initialized.
10590 23:50:21.227135 <6>[ 0.649035] vgaarb: loaded
10591 23:50:21.233794 <6>[ 0.652203] clocksource: Switched to clocksource arch_sys_counter
10592 23:50:21.237247 <5>[ 0.658650] VFS: Disk quotas dquot_6.6.0
10593 23:50:21.243899 <6>[ 0.662834] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10594 23:50:21.247226 <6>[ 0.670025] pnp: PnP ACPI: disabled
10595 23:50:21.255949 <6>[ 0.676725] NET: Registered PF_INET protocol family
10596 23:50:21.265241 <6>[ 0.682325] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10597 23:50:21.277035 <6>[ 0.694659] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10598 23:50:21.286580 <6>[ 0.703470] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10599 23:50:21.293210 <6>[ 0.711447] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10600 23:50:21.300143 <6>[ 0.720147] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10601 23:50:21.312317 <6>[ 0.729894] TCP: Hash tables configured (established 65536 bind 65536)
10602 23:50:21.318610 <6>[ 0.736761] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10603 23:50:21.325230 <6>[ 0.743962] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10604 23:50:21.331820 <6>[ 0.751667] NET: Registered PF_UNIX/PF_LOCAL protocol family
10605 23:50:21.338740 <6>[ 0.757813] RPC: Registered named UNIX socket transport module.
10606 23:50:21.342148 <6>[ 0.763970] RPC: Registered udp transport module.
10607 23:50:21.348843 <6>[ 0.768901] RPC: Registered tcp transport module.
10608 23:50:21.355632 <6>[ 0.773834] RPC: Registered tcp NFSv4.1 backchannel transport module.
10609 23:50:21.358359 <6>[ 0.780503] PCI: CLS 0 bytes, default 64
10610 23:50:21.361730 <6>[ 0.784805] Unpacking initramfs...
10611 23:50:21.383301 <6>[ 0.800803] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10612 23:50:21.392782 <6>[ 0.809445] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10613 23:50:21.396122 <6>[ 0.818293] kvm [1]: IPA Size Limit: 40 bits
10614 23:50:21.402960 <6>[ 0.822813] kvm [1]: GICv3: no GICV resource entry
10615 23:50:21.406259 <6>[ 0.827832] kvm [1]: disabling GICv2 emulation
10616 23:50:21.412628 <6>[ 0.832518] kvm [1]: GIC system register CPU interface enabled
10617 23:50:21.415806 <6>[ 0.838670] kvm [1]: vgic interrupt IRQ18
10618 23:50:21.422580 <6>[ 0.843025] kvm [1]: VHE mode initialized successfully
10619 23:50:21.429109 <5>[ 0.849386] Initialise system trusted keyrings
10620 23:50:21.435898 <6>[ 0.854208] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10621 23:50:21.443525 <6>[ 0.864265] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10622 23:50:21.449627 <5>[ 0.870669] NFS: Registering the id_resolver key type
10623 23:50:21.453166 <5>[ 0.875992] Key type id_resolver registered
10624 23:50:21.459451 <5>[ 0.880408] Key type id_legacy registered
10625 23:50:21.466485 <6>[ 0.884688] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10626 23:50:21.473205 <6>[ 0.891608] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10627 23:50:21.479809 <6>[ 0.899344] 9p: Installing v9fs 9p2000 file system support
10628 23:50:21.515327 <5>[ 0.936831] Key type asymmetric registered
10629 23:50:21.518781 <5>[ 0.941162] Asymmetric key parser 'x509' registered
10630 23:50:21.528741 <6>[ 0.946301] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10631 23:50:21.532458 <6>[ 0.953914] io scheduler mq-deadline registered
10632 23:50:21.535094 <6>[ 0.958690] io scheduler kyber registered
10633 23:50:21.554798 <6>[ 0.975722] EINJ: ACPI disabled.
10634 23:50:21.586793 <4>[ 1.001497] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10635 23:50:21.596635 <4>[ 1.012100] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10636 23:50:21.611879 <6>[ 1.032758] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10637 23:50:21.619362 <6>[ 1.040718] printk: console [ttyS0] disabled
10638 23:50:21.647807 <6>[ 1.065344] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10639 23:50:21.654040 <6>[ 1.074810] printk: console [ttyS0] enabled
10640 23:50:21.657470 <6>[ 1.074810] printk: console [ttyS0] enabled
10641 23:50:21.664357 <6>[ 1.083703] printk: bootconsole [mtk8250] disabled
10642 23:50:21.667087 <6>[ 1.083703] printk: bootconsole [mtk8250] disabled
10643 23:50:21.674162 <6>[ 1.094772] SuperH (H)SCI(F) driver initialized
10644 23:50:21.677534 <6>[ 1.100047] msm_serial: driver initialized
10645 23:50:21.690885 <6>[ 1.108988] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10646 23:50:21.701203 <6>[ 1.117537] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10647 23:50:21.707809 <6>[ 1.126079] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10648 23:50:21.717217 <6>[ 1.134707] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10649 23:50:21.727452 <6>[ 1.143414] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10650 23:50:21.733969 <6>[ 1.152128] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10651 23:50:21.743941 <6>[ 1.160668] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10652 23:50:21.751138 <6>[ 1.169476] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10653 23:50:21.760870 <6>[ 1.178020] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10654 23:50:21.772886 <6>[ 1.193658] loop: module loaded
10655 23:50:21.778966 <6>[ 1.199643] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10656 23:50:21.801882 <4>[ 1.223241] mtk-pmic-keys: Failed to locate of_node [id: -1]
10657 23:50:21.809160 <6>[ 1.230212] megasas: 07.719.03.00-rc1
10658 23:50:21.818891 <6>[ 1.240009] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10659 23:50:21.830334 <6>[ 1.251575] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10660 23:50:21.847207 <6>[ 1.268292] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10661 23:50:21.903820 <6>[ 1.318429] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10662 23:50:24.087509 <6>[ 3.508795] Freeing initrd memory: 59576K
10663 23:50:24.099486 <6>[ 3.520582] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10664 23:50:24.110232 <6>[ 3.531508] tun: Universal TUN/TAP device driver, 1.6
10665 23:50:24.113609 <6>[ 3.537565] thunder_xcv, ver 1.0
10666 23:50:24.116773 <6>[ 3.541070] thunder_bgx, ver 1.0
10667 23:50:24.119889 <6>[ 3.544563] nicpf, ver 1.0
10668 23:50:24.130963 <6>[ 3.548572] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10669 23:50:24.133916 <6>[ 3.556047] hns3: Copyright (c) 2017 Huawei Corporation.
10670 23:50:24.137021 <6>[ 3.561635] hclge is initializing
10671 23:50:24.143755 <6>[ 3.565214] e1000: Intel(R) PRO/1000 Network Driver
10672 23:50:24.150450 <6>[ 3.570342] e1000: Copyright (c) 1999-2006 Intel Corporation.
10673 23:50:24.153968 <6>[ 3.576354] e1000e: Intel(R) PRO/1000 Network Driver
10674 23:50:24.160747 <6>[ 3.581570] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10675 23:50:24.166919 <6>[ 3.587757] igb: Intel(R) Gigabit Ethernet Network Driver
10676 23:50:24.173695 <6>[ 3.593407] igb: Copyright (c) 2007-2014 Intel Corporation.
10677 23:50:24.180123 <6>[ 3.599243] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10678 23:50:24.187223 <6>[ 3.605761] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10679 23:50:24.190074 <6>[ 3.612224] sky2: driver version 1.30
10680 23:50:24.197112 <6>[ 3.617143] usbcore: registered new device driver r8152-cfgselector
10681 23:50:24.203739 <6>[ 3.623678] usbcore: registered new interface driver r8152
10682 23:50:24.209723 <6>[ 3.629500] VFIO - User Level meta-driver version: 0.3
10683 23:50:24.216556 <6>[ 3.637724] usbcore: registered new interface driver usb-storage
10684 23:50:24.223313 <6>[ 3.644166] usbcore: registered new device driver onboard-usb-hub
10685 23:50:24.232234 <6>[ 3.653299] mt6397-rtc mt6359-rtc: registered as rtc0
10686 23:50:24.241808 <6>[ 3.658762] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T23:45:42 UTC (1717544742)
10687 23:50:24.245106 <6>[ 3.668327] i2c_dev: i2c /dev entries driver
10688 23:50:24.261802 <6>[ 3.680036] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10689 23:50:24.268683 <4>[ 3.688772] cpu cpu0: supply cpu not found, using dummy regulator
10690 23:50:24.275559 <4>[ 3.695199] cpu cpu1: supply cpu not found, using dummy regulator
10691 23:50:24.281632 <4>[ 3.701604] cpu cpu2: supply cpu not found, using dummy regulator
10692 23:50:24.288307 <4>[ 3.708022] cpu cpu3: supply cpu not found, using dummy regulator
10693 23:50:24.294925 <4>[ 3.714417] cpu cpu4: supply cpu not found, using dummy regulator
10694 23:50:24.302161 <4>[ 3.720811] cpu cpu5: supply cpu not found, using dummy regulator
10695 23:50:24.308668 <4>[ 3.727207] cpu cpu6: supply cpu not found, using dummy regulator
10696 23:50:24.314848 <4>[ 3.733604] cpu cpu7: supply cpu not found, using dummy regulator
10697 23:50:24.333163 <6>[ 3.754259] cpu cpu0: EM: created perf domain
10698 23:50:24.336324 <6>[ 3.759181] cpu cpu4: EM: created perf domain
10699 23:50:24.343632 <6>[ 3.764776] sdhci: Secure Digital Host Controller Interface driver
10700 23:50:24.349995 <6>[ 3.771205] sdhci: Copyright(c) Pierre Ossman
10701 23:50:24.356821 <6>[ 3.776165] Synopsys Designware Multimedia Card Interface Driver
10702 23:50:24.362941 <6>[ 3.782792] sdhci-pltfm: SDHCI platform and OF driver helper
10703 23:50:24.366420 <6>[ 3.782805] mmc0: CQHCI version 5.10
10704 23:50:24.373361 <6>[ 3.793144] ledtrig-cpu: registered to indicate activity on CPUs
10705 23:50:24.379983 <6>[ 3.800190] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10706 23:50:24.386726 <6>[ 3.807236] usbcore: registered new interface driver usbhid
10707 23:50:24.389502 <6>[ 3.813058] usbhid: USB HID core driver
10708 23:50:24.396594 <6>[ 3.817273] spi_master spi0: will run message pump with realtime priority
10709 23:50:24.443847 <6>[ 3.858643] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10710 23:50:24.463481 <6>[ 3.874329] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10711 23:50:24.466961 <6>[ 3.886497] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16814
10712 23:50:24.473527 <6>[ 3.889565] cros-ec-spi spi0.0: Chrome EC device registered
10713 23:50:24.476848 <6>[ 3.899777] mmc0: Command Queue Engine enabled
10714 23:50:24.483572 <6>[ 3.904524] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10715 23:50:24.490246 <6>[ 3.911879] mmcblk0: mmc0:0001 DA4128 116 GiB
10716 23:50:24.500223 <6>[ 3.912777] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10717 23:50:24.503701 <6>[ 3.919550] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10718 23:50:24.510521 <6>[ 3.927045] NET: Registered PF_PACKET protocol family
10719 23:50:24.516683 <6>[ 3.932661] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10720 23:50:24.520127 <6>[ 3.937212] 9pnet: Installing 9P2000 support
10721 23:50:24.527019 <6>[ 3.942910] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10722 23:50:24.530302 <5>[ 3.946903] Key type dns_resolver registered
10723 23:50:24.537140 <6>[ 3.952635] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10724 23:50:24.540491 <6>[ 3.957188] registered taskstats version 1
10725 23:50:24.547041 <5>[ 3.967501] Loading compiled-in X.509 certificates
10726 23:50:24.576536 <4>[ 3.991155] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10727 23:50:24.586534 <4>[ 4.001864] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10728 23:50:24.601034 <6>[ 4.022353] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10729 23:50:24.608217 <6>[ 4.029375] xhci-mtk 11200000.usb: xHCI Host Controller
10730 23:50:24.614325 <6>[ 4.034891] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10731 23:50:24.624592 <6>[ 4.042721] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10732 23:50:24.631574 <6>[ 4.052150] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10733 23:50:24.638274 <6>[ 4.058243] xhci-mtk 11200000.usb: xHCI Host Controller
10734 23:50:24.644679 <6>[ 4.063727] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10735 23:50:24.651209 <6>[ 4.071377] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10736 23:50:24.657733 <6>[ 4.079024] hub 1-0:1.0: USB hub found
10737 23:50:24.661204 <6>[ 4.083051] hub 1-0:1.0: 1 port detected
10738 23:50:24.668000 <6>[ 4.087345] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10739 23:50:24.674557 <6>[ 4.095886] hub 2-0:1.0: USB hub found
10740 23:50:24.677912 <6>[ 4.099908] hub 2-0:1.0: 1 port detected
10741 23:50:24.685923 <6>[ 4.107152] mtk-msdc 11f70000.mmc: Got CD GPIO
10742 23:50:24.698010 <6>[ 4.116163] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10743 23:50:24.704727 <6>[ 4.124192] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10744 23:50:24.714457 <4>[ 4.132282] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10745 23:50:24.724835 <6>[ 4.141847] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10746 23:50:24.731628 <6>[ 4.149968] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10747 23:50:24.737692 <6>[ 4.157995] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10748 23:50:24.747716 <6>[ 4.165930] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10749 23:50:24.754572 <6>[ 4.173749] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10750 23:50:24.764445 <6>[ 4.181577] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10751 23:50:24.774478 <6>[ 4.191981] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10752 23:50:24.781023 <6>[ 4.200356] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10753 23:50:24.791273 <6>[ 4.208699] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10754 23:50:24.797437 <6>[ 4.217048] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10755 23:50:24.807814 <6>[ 4.225387] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10756 23:50:24.814349 <6>[ 4.233736] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10757 23:50:24.823836 <6>[ 4.242077] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10758 23:50:24.830680 <6>[ 4.250426] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10759 23:50:24.840422 <6>[ 4.258764] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10760 23:50:24.850277 <6>[ 4.267113] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10761 23:50:24.856996 <6>[ 4.275452] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10762 23:50:24.867206 <6>[ 4.283793] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10763 23:50:24.873429 <6>[ 4.292132] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10764 23:50:24.883603 <6>[ 4.300470] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10765 23:50:24.890143 <6>[ 4.308807] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10766 23:50:24.896723 <6>[ 4.317677] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10767 23:50:24.903500 <6>[ 4.325004] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10768 23:50:24.910333 <6>[ 4.331883] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10769 23:50:24.920435 <6>[ 4.338666] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10770 23:50:24.926990 <6>[ 4.345625] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10771 23:50:24.933557 <6>[ 4.352520] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10772 23:50:24.943343 <6>[ 4.361655] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10773 23:50:24.953495 <6>[ 4.370775] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10774 23:50:24.963244 <6>[ 4.380093] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10775 23:50:24.973407 <6>[ 4.389567] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10776 23:50:24.983069 <6>[ 4.399034] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10777 23:50:24.990271 <6>[ 4.408154] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10778 23:50:24.999444 <6>[ 4.417620] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10779 23:50:25.009581 <6>[ 4.426738] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10780 23:50:25.019598 <6>[ 4.436032] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10781 23:50:25.029687 <6>[ 4.446192] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10782 23:50:25.039820 <6>[ 4.458099] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10783 23:50:25.066310 <6>[ 4.484838] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10784 23:50:25.094750 <6>[ 4.516059] hub 2-1:1.0: USB hub found
10785 23:50:25.098027 <6>[ 4.520583] hub 2-1:1.0: 3 ports detected
10786 23:50:25.106080 <6>[ 4.527808] hub 2-1:1.0: USB hub found
10787 23:50:25.109363 <6>[ 4.532180] hub 2-1:1.0: 3 ports detected
10788 23:50:25.218027 <6>[ 4.636398] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10789 23:50:25.373201 <6>[ 4.794508] hub 1-1:1.0: USB hub found
10790 23:50:25.376560 <6>[ 4.799050] hub 1-1:1.0: 4 ports detected
10791 23:50:25.386087 <6>[ 4.807644] hub 1-1:1.0: USB hub found
10792 23:50:25.389516 <6>[ 4.812195] hub 1-1:1.0: 4 ports detected
10793 23:50:25.458613 <6>[ 4.876725] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10794 23:50:25.566934 <6>[ 4.985199] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10795 23:50:25.602021 <4>[ 5.020446] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10796 23:50:25.611939 <4>[ 5.029605] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10797 23:50:25.651885 <6>[ 5.073317] r8152 2-1.3:1.0 eth0: v1.12.13
10798 23:50:25.722020 <6>[ 5.140485] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10799 23:50:25.854667 <6>[ 5.276080] hub 1-1.4:1.0: USB hub found
10800 23:50:25.857933 <6>[ 5.280717] hub 1-1.4:1.0: 2 ports detected
10801 23:50:25.867303 <6>[ 5.288756] hub 1-1.4:1.0: USB hub found
10802 23:50:25.870452 <6>[ 5.293318] hub 1-1.4:1.0: 2 ports detected
10803 23:50:26.169995 <6>[ 5.588479] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10804 23:50:26.361801 <6>[ 5.780319] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10805 23:50:27.286048 <6>[ 6.707663] r8152 2-1.3:1.0 eth0: carrier on
10806 23:50:30.258367 <5>[ 6.728248] Sending DHCP requests .., OK
10807 23:50:30.264842 <6>[ 9.684623] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10808 23:50:30.268247 <6>[ 9.692917] IP-Config: Complete:
10809 23:50:30.281377 <6>[ 9.696410] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10810 23:50:30.288231 <6>[ 9.707127] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10811 23:50:30.294901 <6>[ 9.715746] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10812 23:50:30.300989 <6>[ 9.715755] nameserver0=192.168.201.1
10813 23:50:30.304199 <6>[ 9.727913] clk: Disabling unused clocks
10814 23:50:30.308082 <6>[ 9.733323] ALSA device list:
10815 23:50:30.314871 <6>[ 9.736615] No soundcards found.
10816 23:50:30.321664 <6>[ 9.743935] Freeing unused kernel memory: 8512K
10817 23:50:30.325035 <6>[ 9.748849] Run /init as init process
10818 23:50:30.354169 <6>[ 9.776295] NET: Registered PF_INET6 protocol family
10819 23:50:30.360861 <6>[ 9.783097] Segment Routing with IPv6
10820 23:50:30.364089 <6>[ 9.787042] In-situ OAM (IOAM) with IPv6
10821 23:50:30.407517 <30>[ 9.802993] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10822 23:50:30.414187 <30>[ 9.836074] systemd[1]: Detected architecture arm64.
10823 23:50:30.414298
10824 23:50:30.420574 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10825 23:50:30.420663
10826 23:50:30.438428 <30>[ 9.860491] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10827 23:50:30.549452 <30>[ 9.968242] systemd[1]: Queued start job for default target graphical.target.
10828 23:50:30.583770 <30>[ 10.002411] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10829 23:50:30.590176 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10830 23:50:30.614401 <30>[ 10.033151] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10831 23:50:30.623925 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10832 23:50:30.643661 <30>[ 10.062177] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10833 23:50:30.653319 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10834 23:50:30.671551 <30>[ 10.089994] systemd[1]: Created slice user.slice - User and Session Slice.
10835 23:50:30.677763 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10836 23:50:30.702011 <30>[ 10.117236] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10837 23:50:30.708255 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10838 23:50:30.729156 <30>[ 10.144665] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10839 23:50:30.735741 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10840 23:50:30.764492 <30>[ 10.173062] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10841 23:50:30.774395 <30>[ 10.192951] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10842 23:50:30.780573 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10843 23:50:30.797529 <30>[ 10.216521] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10844 23:50:30.803926 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10845 23:50:30.822214 <30>[ 10.240559] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10846 23:50:30.831505 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10847 23:50:30.846573 <30>[ 10.268587] systemd[1]: Reached target paths.target - Path Units.
10848 23:50:30.852935 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10849 23:50:30.874241 <30>[ 10.292926] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10850 23:50:30.880627 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10851 23:50:30.894196 <30>[ 10.316466] systemd[1]: Reached target slices.target - Slice Units.
10852 23:50:30.904456 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10853 23:50:30.918948 <30>[ 10.340969] systemd[1]: Reached target swap.target - Swaps.
10854 23:50:30.925292 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10855 23:50:30.946040 <30>[ 10.364977] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10856 23:50:30.956168 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10857 23:50:30.974110 <30>[ 10.392960] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10858 23:50:30.984151 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10859 23:50:31.003700 <30>[ 10.422713] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10860 23:50:31.014033 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10861 23:50:31.030417 <30>[ 10.449239] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10862 23:50:31.040576 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10863 23:50:31.059249 <30>[ 10.477798] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10864 23:50:31.065359 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10865 23:50:31.086470 <30>[ 10.505157] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10866 23:50:31.096337 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10867 23:50:31.114439 <30>[ 10.532978] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10868 23:50:31.124148 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10869 23:50:31.189825 <30>[ 10.608716] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10870 23:50:31.196211 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10871 23:50:31.215298 <30>[ 10.634283] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10872 23:50:31.221944 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10873 23:50:31.244152 <30>[ 10.662665] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10874 23:50:31.250191 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10875 23:50:31.276494 <30>[ 10.688744] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10876 23:50:31.318613 <30>[ 10.737178] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10877 23:50:31.328248 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10878 23:50:31.351205 <30>[ 10.769748] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10879 23:50:31.357671 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10880 23:50:31.418285 <30>[ 10.837162] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10881 23:50:31.427924 Startin<6>[ 10.846549] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10882 23:50:31.434822 g [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10883 23:50:31.458752 <30>[ 10.877613] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10884 23:50:31.465362 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10885 23:50:31.491059 <30>[ 10.909675] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10886 23:50:31.500836 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10887 23:50:31.549808 <30>[ 10.968958] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10888 23:50:31.556699 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10889 23:50:31.586549 <30>[ 11.005253] systemd[1]: Starting systemd-journald.service - Journal Service...
10890 23:50:31.592538 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10891 23:50:31.612372 <30>[ 11.031187] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10892 23:50:31.618730 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10893 23:50:31.643730 <30>[ 11.059567] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10894 23:50:31.650665 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10895 23:50:31.673537 <30>[ 11.092473] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10896 23:50:31.683367 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10897 23:50:31.704819 <30>[ 11.123449] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10898 23:50:31.714712 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10899 23:50:31.734627 <30>[ 11.153250] systemd[1]: Started systemd-journald.service - Journal Service.
10900 23:50:31.741283 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10901 23:50:31.760305 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10902 23:50:31.778350 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10903 23:50:31.798487 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10904 23:50:31.818623 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10905 23:50:31.839377 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10906 23:50:31.859986 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10907 23:50:31.880200 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10908 23:50:31.900154 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10909 23:50:31.921345 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10910 23:50:31.940408 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10911 23:50:31.960283 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10912 23:50:31.980538 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-re…ount Root and Kernel File Systems.
10913 23:50:31.987365 See 'systemctl status systemd-remount-fs.service' for details.
10914 23:50:31.997098 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10915 23:50:32.016526 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10916 23:50:32.062486 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10917 23:50:32.087803 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10918 23:50:32.103224 <46>[ 11.522403] systemd-journald[191]: Received client request to flush runtime journal.
10919 23:50:32.115024 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10920 23:50:32.138516 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10921 23:50:32.161635 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10922 23:50:32.184190 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10923 23:50:32.203305 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10924 23:50:32.223162 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10925 23:50:32.243160 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10926 23:50:32.262584 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10927 23:50:32.310649 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10928 23:50:32.343893 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10929 23:50:32.362160 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10930 23:50:32.377742 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10931 23:50:32.434511 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10932 23:50:32.458204 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10933 23:50:32.477471 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10934 23:50:32.520093 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10935 23:50:32.543207 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10936 23:50:32.564381 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10937 23:50:32.625060 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10938 23:50:32.649825 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10939 23:50:32.680801 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10940 23:50:32.786104 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10941 23:50:32.803623 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10942 23:50:32.822699 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10943 23:50:32.839854 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10944 23:50:32.859579 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10945 23:50:32.877254 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10946 23:50:32.883759 <6>[ 12.304255] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10947 23:50:32.895261 [[0;32m OK [0m] Reached targ<6>[ 12.316859] remoteproc remoteproc0: scp is available
10948 23:50:32.901876 et [0;1;39msock<6>[ 12.322829] remoteproc remoteproc0: powering up scp
10949 23:50:32.908318 <6>[ 12.323449] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10950 23:50:32.918452 ets.target[0m -<6>[ 12.329046] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10951 23:50:32.928177 <6>[ 12.337540] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10952 23:50:32.928288 Socket Units.
10953 23:50:32.934798 <6>[ 12.346562] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10954 23:50:32.934936
10955 23:50:32.944925 <6>[ 12.355192] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10956 23:50:32.951728 <3>[ 12.355565] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10957 23:50:32.958405 <6>[ 12.356533] mc: Linux media interface: v0.10
10958 23:50:32.961908 <6>[ 12.377137] videodev: Linux video capture interface: v2.00
10959 23:50:32.971651 <3>[ 12.379556] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10960 23:50:32.978416 <4>[ 12.389725] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10961 23:50:32.984895 <3>[ 12.389865] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10962 23:50:32.994534 <4>[ 12.402595] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10963 23:50:33.001003 <6>[ 12.404480] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10964 23:50:33.008198 <3>[ 12.406447] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10965 23:50:33.017483 <4>[ 12.431479] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10966 23:50:33.024253 <4>[ 12.431479] Fallback method does not support PEC.
10967 23:50:33.030607 <3>[ 12.436522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10968 23:50:33.040709 <3>[ 12.458478] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10969 23:50:33.047534 <3>[ 12.466639] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10970 23:50:33.054540 <3>[ 12.474762] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10971 23:50:33.067142 [[0;32m OK [<6>[ 12.478886] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10972 23:50:33.074032 0m] Reached targ<6>[ 12.480028] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10973 23:50:33.080947 <6>[ 12.480033] pci_bus 0000:00: root bus resource [bus 00-ff]
10974 23:50:33.087564 <6>[ 12.480037] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10975 23:50:33.100442 et [0;1;39mbasi<6>[ 12.480039] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10976 23:50:33.106934 c.target[0m - B<6>[ 12.480067] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10977 23:50:33.113844 <6>[ 12.480080] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10978 23:50:33.116880 asic System.
10979 23:50:33.120691 <6>[ 12.480150] pci 0000:00:00.0: supports D1 D2
10980 23:50:33.127431 <6>[ 12.480154] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10981 23:50:33.136928 <6>[ 12.481149] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10982 23:50:33.140020 <6>[ 12.481235] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10983 23:50:33.150284 <6>[ 12.481260] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10984 23:50:33.157230 <6>[ 12.481277] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10985 23:50:33.163370 <6>[ 12.481293] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10986 23:50:33.170072 <6>[ 12.481401] pci 0000:01:00.0: supports D1 D2
10987 23:50:33.177004 <6>[ 12.481403] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10988 23:50:33.183262 <3>[ 12.483032] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10989 23:50:33.189992 <6>[ 12.494392] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10990 23:50:33.196733 <6>[ 12.494410] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10991 23:50:33.206383 <6>[ 12.494456] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10992 23:50:33.213689 <6>[ 12.494466] remoteproc remoteproc0: remote processor scp is now up
10993 23:50:33.220799 <6>[ 12.495143] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10994 23:50:33.230920 <3>[ 12.502711] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10995 23:50:33.237130 <6>[ 12.508352] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10996 23:50:33.247223 <6>[ 12.509688] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10997 23:50:33.254587 <6>[ 12.512369] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10998 23:50:33.261447 <3>[ 12.515458] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10999 23:50:33.271714 <6>[ 12.516893] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
11000 23:50:33.278267 <6>[ 12.526743] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
11001 23:50:33.288622 <3>[ 12.534428] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11002 23:50:33.295499 <6>[ 12.541876] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
11003 23:50:33.305356 <3>[ 12.548165] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11004 23:50:33.311773 <6>[ 12.554586] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
11005 23:50:33.318476 <3>[ 12.562848] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11006 23:50:33.322698 <6>[ 12.563777] Bluetooth: Core ver 2.22
11007 23:50:33.329745 <6>[ 12.563939] NET: Registered PF_BLUETOOTH protocol family
11008 23:50:33.335984 <6>[ 12.563942] Bluetooth: HCI device and connection manager initialized
11009 23:50:33.342858 <6>[ 12.563969] Bluetooth: HCI socket layer initialized
11010 23:50:33.346212 <6>[ 12.563977] Bluetooth: L2CAP socket layer initialized
11011 23:50:33.352824 <6>[ 12.563998] Bluetooth: SCO socket layer initialized
11012 23:50:33.360150 <6>[ 12.569100] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
11013 23:50:33.367167 <3>[ 12.576577] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11014 23:50:33.373270 <6>[ 12.584044] pci 0000:00:00.0: PCI bridge to [bus 01]
11015 23:50:33.380033 <6>[ 12.584051] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
11016 23:50:33.387246 <6>[ 12.586370] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11017 23:50:33.400948 <6>[ 12.587490] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
11018 23:50:33.407374 <6>[ 12.587590] usbcore: registered new interface driver uvcvideo
11019 23:50:33.414081 <3>[ 12.591562] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11020 23:50:33.420731 <6>[ 12.596352] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
11021 23:50:33.427612 <3>[ 12.602936] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11022 23:50:33.433788 <6>[ 12.603918] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
11023 23:50:33.440527 <6>[ 12.611798] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
11024 23:50:33.447500 <6>[ 12.611947] usbcore: registered new interface driver btusb
11025 23:50:33.457143 <4>[ 12.612897] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
11026 23:50:33.463665 <3>[ 12.612913] Bluetooth: hci0: Failed to load firmware file (-2)
11027 23:50:33.470479 <3>[ 12.612917] Bluetooth: hci0: Failed to set up firmware (-2)
11028 23:50:33.481121 <4>[ 12.612922] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
11029 23:50:33.487794 <3>[ 12.617916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
11030 23:50:33.494134 <6>[ 12.625303] pcieport 0000:00:00.0: AER: enabled with IRQ 283
11031 23:50:33.504188 <3>[ 12.662343] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11032 23:50:33.511915 <5>[ 12.693225] cfg80211: Loading compiled-in X.509 certificates for regulatory database
11033 23:50:33.518208 <3>[ 12.693674] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11034 23:50:33.528007 <3>[ 12.694391] power_supply sbs-5-000b: driver failed to report `temp' property: -6
11035 23:50:33.534746 <3>[ 12.713727] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11036 23:50:33.541526 <5>[ 12.727415] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
11037 23:50:33.551246 <3>[ 12.731524] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6
11038 23:50:33.558091 <5>[ 12.739898] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
11039 23:50:33.568508 <3>[ 12.753819] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11040 23:50:33.578848 <4>[ 12.756907] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
11041 23:50:33.585660 <3>[ 12.783959] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11042 23:50:33.592325 <6>[ 12.787481] cfg80211: failed to load regulatory.db
11043 23:50:33.599502 <3>[ 12.818309] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11044 23:50:33.605979 <6>[ 12.875129] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
11045 23:50:33.616294 <3>[ 12.907369] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11046 23:50:33.623910 <6>[ 12.907811] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
11047 23:50:33.630392 <3>[ 12.938045] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11048 23:50:33.637247 <6>[ 12.958949] mt7921e 0000:01:00.0: ASIC revision: 79610010
11049 23:50:33.643874 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11050 23:50:33.685034 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11051 23:50:33.717637 <46>[ 13.123297] systemd-journald[191]: Data hash table of /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal has a fill level at 75.2 (1539 of 2047 items, 524288 file size, 340 bytes per hash table item), suggesting rotation.
11052 23:50:33.730752 <46>[ 13.144752] systemd-journald[191]: /var/log/journal/c3f909ee3e324895ab90ff2613af9260/system.journal: Journal header limits reached or header out-of-date, rotating.
11053 23:50:33.745234 Starting [0;1;39msyste<6>[ 13.162438] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
11054 23:50:33.745324 <6>[ 13.162438]
11055 23:50:33.751206 md-user-sess…vice[0m - Permit User Sessions...
11056 23:50:33.773613 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11057 23:50:33.794991 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11058 23:50:33.818184 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11059 23:50:33.840557 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11060 23:50:33.860260 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11061 23:50:33.901367 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11062 23:50:33.945704 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11063 23:50:33.961157 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11064 23:50:34.001789 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11065 23:50:34.022573 [[0;32m OK [0m] Started [0;1;39msystemd-log<6>[ 13.442045] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
11066 23:50:34.028762 ind.service[0m - User Login Management.
11067 23:50:34.046836 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11068 23:50:34.068755 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11069 23:50:34.086524 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11070 23:50:34.138934 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11071 23:50:34.163116 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11072 23:50:34.184987 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11073 23:50:34.224450 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11074 23:50:34.269484
11075 23:50:34.272707 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11076 23:50:34.272799
11077 23:50:34.275964 debian-bookworm-arm64 login: root (automatic login)
11078 23:50:34.276042
11079 23:50:34.297964 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024 aarch64
11080 23:50:34.298065
11081 23:50:34.305221 The programs included with the Debian GNU/Linux system are free software;
11082 23:50:34.311266 the exact distribution terms for each program are described in the
11083 23:50:34.314596 individual files in /usr/share/doc/*/copyright.
11084 23:50:34.314677
11085 23:50:34.321505 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11086 23:50:34.324724 permitted by applicable law.
11087 23:50:34.325101 Matched prompt #10: / #
11089 23:50:34.325300 Setting prompt string to ['/ #']
11090 23:50:34.325394 end: 2.2.5.1 login-action (duration 00:00:14) [common]
11092 23:50:34.325580 end: 2.2.5 auto-login-action (duration 00:00:15) [common]
11093 23:50:34.325664 start: 2.2.6 expect-shell-connection (timeout 00:03:27) [common]
11094 23:50:34.325735 Setting prompt string to ['/ #']
11095 23:50:34.325795 Forcing a shell prompt, looking for ['/ #']
11097 23:50:34.375988 / #
11098 23:50:34.376142 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11099 23:50:34.376251 Waiting using forced prompt support (timeout 00:02:30)
11100 23:50:34.380664
11101 23:50:34.380938 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11102 23:50:34.381034 start: 2.2.7 export-device-env (timeout 00:03:27) [common]
11103 23:50:34.381123 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11104 23:50:34.381205 end: 2.2 depthcharge-retry (duration 00:01:33) [common]
11105 23:50:34.381287 end: 2 depthcharge-action (duration 00:01:33) [common]
11106 23:50:34.381369 start: 3 lava-test-retry (timeout 00:08:00) [common]
11107 23:50:34.381453 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
11108 23:50:34.381522 Using namespace: common
11110 23:50:34.481918 / # #
11111 23:50:34.482083 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11112 23:50:34.487393 #
11113 23:50:34.487663 Using /lava-14172959
11115 23:50:34.588073 / # export SHELL=/bin/sh
11116 23:50:34.593984 export SHELL=/bin/sh
11118 23:50:34.694545 / # . /lava-14172959/environment
11119 23:50:34.699858 . /lava-14172959/environment
11121 23:50:34.800388 / # /lava-14172959/bin/lava-test-runner /lava-14172959/0
11122 23:50:34.800610 Test shell timeout: 10s (minimum of the action and connection timeout)
11123 23:50:34.805741 /lava-14172959/bin/lava-test-runner /lava-14172959/0
11124 23:50:34.830034 + export TESTRUN_ID=0_igt-kms-me<8>[ 14.250603] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 14172959_1.5.2.3.1>
11125 23:50:34.830367 Received signal: <STARTRUN> 0_igt-kms-mediatek 14172959_1.5.2.3.1
11126 23:50:34.830505 Starting test lava.0_igt-kms-mediatek (14172959_1.5.2.3.1)
11127 23:50:34.830629 Skipping test definition patterns.
11128 23:50:34.833333 diatek
11129 23:50:34.836530 + cd /lava-14172959/0/tests/0_igt-kms-mediatek
11130 23:50:34.836616 + cat uuid
11131 23:50:34.840058 + UUID=14172959_1.5.2.3.1
11132 23:50:34.840146 + set +x
11133 23:50:34.856486 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_re<8>[ 14.279014] <LAVA_SIGNAL_TESTSET START core_auth>
11134 23:50:34.856754 Received signal: <TESTSET> START core_auth
11135 23:50:34.856839 Starting test_set core_auth
11136 23:50:34.866455 ad kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11137 23:50:34.876896 <14>[ 14.299630] [IGT] core_auth: executing
11138 23:50:34.884152 IGT-Version: 1.2<14>[ 14.304010] [IGT] core_auth: starting subtest getclient-simple
11139 23:50:34.893414 8-ga44ebfe (aarc<14>[ 14.311786] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
11140 23:50:34.896871 h64) (Linux: 6.1<14>[ 14.319893] [IGT] core_auth: exiting, ret=0
11141 23:50:34.903605 <6>[ 14.325168] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
11142 23:50:34.907119 .92-cip22 aarch64)
11143 23:50:34.910702 Using IGT_SRANDOM=1717544753 for randomisation
11144 23:50:34.920130 Starting subtest: getclient-<8>[ 14.338619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11145 23:50:34.920252 simple
11146 23:50:34.920529 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11148 23:50:34.923406 Opened device: /dev/dri/card0
11149 23:50:34.927207 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11150 23:50:34.938738 <14>[ 14.361066] [IGT] core_auth: executing
11151 23:50:34.945299 IGT-Version: 1.2<14>[ 14.365442] [IGT] core_auth: starting subtest getclient-master-drop
11152 23:50:34.955125 8-ga44ebfe (aarc<14>[ 14.373509] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
11153 23:50:34.961577 h64) (Linux: 6.1<14>[ 14.382187] [IGT] core_auth: exiting, ret=0
11154 23:50:34.961664 .92-cip22 aarch64)
11155 23:50:34.972088 Using IGT_SRANDOM=1717544753<8>[ 14.392147] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11156 23:50:34.972359 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11158 23:50:34.975216 for randomisation
11159 23:50:34.978489 Starting subtest: getclient-master-drop
11160 23:50:34.981823 Opened device: /dev/dri/card0
11161 23:50:34.985023 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11162 23:50:34.991841 <14>[ 14.414381] [IGT] core_auth: executing
11163 23:50:34.998401 IGT-Version: 1.2<14>[ 14.419134] [IGT] core_auth: starting subtest basic-auth
11164 23:50:35.005009 8-ga44ebfe (aarc<14>[ 14.426138] [IGT] core_auth: finished subtest basic-auth, SUCCESS
11165 23:50:35.011831 h64) (Linux: 6.1<14>[ 14.434021] [IGT] core_auth: exiting, ret=0
11166 23:50:35.015407 .92-cip22 aarch64)
11167 23:50:35.025006 Using IGT_SRANDOM=1717544753 for randomisati<8>[ 14.444450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11168 23:50:35.025097 on
11169 23:50:35.025339 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11171 23:50:35.028459 Opened device: /dev/dri/card0
11172 23:50:35.031607 Starting subtest: basic-auth
11173 23:50:35.034811 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11174 23:50:35.058608 <14>[ 14.481111] [IGT] core_auth: executing
11175 23:50:35.065287 IGT-Version: 1.2<14>[ 14.485916] [IGT] core_auth: starting subtest many-magics
11176 23:50:35.068510 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11177 23:50:35.075243 Using IGT_SRANDOM=1717544753 for randomisation
11178 23:50:35.081809 Opened device: /dev/dri/card<14>[ 14.503177] [IGT] core_auth: finished subtest many-magics, SUCCESS
11179 23:50:35.081900 0
11180 23:50:35.088345 Starting subt<14>[ 14.510163] [IGT] core_auth: exiting, ret=0
11181 23:50:35.091766 est: many-magics
11182 23:50:35.095125 Reopening device failed after 1020 opens
11183 23:50:35.101930 [1m<8>[ 14.521231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11184 23:50:35.102207 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11186 23:50:35.105299 Subtest many-mag<8>[ 14.529892] <LAVA_SIGNAL_TESTSET STOP>
11187 23:50:35.105550 Received signal: <TESTSET> STOP
11188 23:50:35.105622 Closing test_set core_auth
11189 23:50:35.108593 ics: SUCCESS (0.011s)[0m
11190 23:50:35.139756 <14>[ 14.562095] [IGT] core_getclient: executing
11191 23:50:35.145942 IGT-Version: 1.2<14>[ 14.567018] [IGT] core_getclient: exiting, ret=0
11192 23:50:35.149345 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11193 23:50:35.159538 Using IGT_SR<8>[ 14.578224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11194 23:50:35.159831 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11196 23:50:35.162581 ANDOM=1717544753 for randomisation
11197 23:50:35.162666 Opened device: /dev/dri/card0
11198 23:50:35.166064 SUCCESS (0.006s)
11199 23:50:35.189942 <14>[ 14.612267] [IGT] core_getstats: executing
11200 23:50:35.196561 IGT-Version: 1.2<14>[ 14.617074] [IGT] core_getstats: exiting, ret=0
11201 23:50:35.199808 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11202 23:50:35.206878 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11204 23:50:35.209869 Using IGT_SR<8>[ 14.627634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11205 23:50:35.209951 ANDOM=1717544753 for randomisation
11206 23:50:35.213316 Opened device: /dev/dri/card0
11207 23:50:35.216515 SUCCESS (0.006s)
11208 23:50:35.241080 <14>[ 14.663722] [IGT] core_getversion: executing
11209 23:50:35.247851 IGT-Version: 1.2<14>[ 14.668686] [IGT] core_getversion: exiting, ret=0
11210 23:50:35.251089 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11211 23:50:35.260784 Using IGT_SR<8>[ 14.679458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11212 23:50:35.261054 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11214 23:50:35.264225 ANDOM=1717544753 for randomisation
11215 23:50:35.264334 Opened device: /dev/dri/card0
11216 23:50:35.267543 SUCCESS (0.006s)
11217 23:50:35.292196 <14>[ 14.714664] [IGT] core_setmaster_vs_auth: executing
11218 23:50:35.298401 IGT-Version: 1.2<14>[ 14.720313] [IGT] core_setmaster_vs_auth: exiting, ret=0
11219 23:50:35.305065 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11220 23:50:35.315519 Using IGT_SRANDOM=1717544753<8>[ 14.733006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11221 23:50:35.315620 for randomisation
11222 23:50:35.315867 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11224 23:50:35.318937 Opened device: /dev/dri/card0
11225 23:50:35.321508 SUCCESS (0.007s)
11226 23:50:35.335551 <8>[ 14.758218] <LAVA_SIGNAL_TESTSET START drm_read>
11227 23:50:35.335809 Received signal: <TESTSET> START drm_read
11228 23:50:35.335881 Starting test_set drm_read
11229 23:50:35.354085 <14>[ 14.776782] [IGT] drm_read: executing
11230 23:50:35.357386 IGT-Version: 1.2<14>[ 14.781293] [IGT] drm_read: exiting, ret=77
11231 23:50:35.363944 8-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11232 23:50:35.370640 Using IGT_SR<8>[ 14.791870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11233 23:50:35.370900 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11235 23:50:35.373905 ANDOM=1717544753 for randomisation
11236 23:50:35.377664 Opened device: /dev/dri/card0
11237 23:50:35.384150 No KMS driver or no outputs, pipes: 16, outputs: 0
11238 23:50:35.390835 [1mSubtest invalid-buffer: SKIP (0.000s)<14>[ 14.813086] [IGT] drm_read: executing
11239 23:50:35.390921 [0m
11240 23:50:35.394085 <14>[ 14.818063] [IGT] drm_read: exiting, ret=77
11241 23:50:35.407022 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<8>[ 14.827371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11242 23:50:35.407115 4)
11243 23:50:35.407358 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11245 23:50:35.413608 Using IGT_SRANDOM=1717544753 for randomisation
11246 23:50:35.413694 Opened device: /dev/dri/card0
11247 23:50:35.420448 No KMS driver or no outputs, pipes: 16, outputs: 0
11248 23:50:35.426899 [1mSubtest fault-buffer:<14>[ 14.848389] [IGT] drm_read: executing
11249 23:50:35.430298 SKIP (0.000s)[<14>[ 14.853820] [IGT] drm_read: exiting, ret=77
11250 23:50:35.433405 0m
11251 23:50:35.443703 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aa<8>[ 14.863889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11252 23:50:35.443837 rch64)
11253 23:50:35.444115 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11255 23:50:35.450098 Using IGT_SRANDOM=1717544753 for randomisation
11256 23:50:35.453427 Opened device: /dev/dri/card0
11257 23:50:35.456641 No KMS driver or no outputs, pipes: 16, outputs: 0
11258 23:50:35.462856 [1mSubtest empty-blo<14>[ 14.884755] [IGT] drm_read: executing
11259 23:50:35.466556 ck: SKIP (0.000s<14>[ 14.890151] [IGT] drm_read: exiting, ret=77
11260 23:50:35.469972 )[0m
11261 23:50:35.479615 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22<8>[ 14.900527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11262 23:50:35.479909 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11264 23:50:35.483006 aarch64)
11265 23:50:35.486191 Using IGT_SRANDOM=1717544753 for randomisation
11266 23:50:35.489622 Opened device: /dev/dri/card0
11267 23:50:35.492820 No KMS driver or no outputs, pipes: 16, outputs: 0
11268 23:50:35.499786 [1mSubtest empty-<14>[ 14.922109] [IGT] drm_read: executing
11269 23:50:35.505881 nonblock: SKIP (<14>[ 14.926851] [IGT] drm_read: exiting, ret=77
11270 23:50:35.505995 0.000s)[0m
11271 23:50:35.516468 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92<8>[ 14.936905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11272 23:50:35.516750 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11274 23:50:35.519663 -cip22 aarch64)
11275 23:50:35.523001 Using IGT_SRANDOM=1717544753 for randomisation
11276 23:50:35.526133 Opened device: /dev/dri/card0
11277 23:50:35.529157 No KMS driver or no outputs, pipes: 16, outputs: 0
11278 23:50:35.535920 [1mSubtest <14>[ 14.958888] [IGT] drm_read: executing
11279 23:50:35.542801 short-buffer-blo<14>[ 14.963982] [IGT] drm_read: exiting, ret=77
11280 23:50:35.542896 ck: SKIP (0.000s)[0m
11281 23:50:35.556193 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<8>[ 14.974062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11282 23:50:35.556305 ux: 6.1.92-cip22 aarch64)
11283 23:50:35.556585 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11285 23:50:35.562739 Using IGT_SRANDOM=1717544753 for randomisation
11286 23:50:35.566229 Opened device: /dev/dri/card0
11287 23:50:35.569528 No KMS driver or no outputs, pipes: 16, outputs: 0
11288 23:50:35.572705 [<14>[ 14.996413] [IGT] drm_read: executing
11289 23:50:35.579372 1mSubtest short-<14>[ 15.001264] [IGT] drm_read: exiting, ret=77
11290 23:50:35.582791 buffer-nonblock: SKIP (0.000s)[0m
11291 23:50:35.592826 IGT-Version: 1.28-ga44ebfe (<8>[ 15.011288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11292 23:50:35.593091 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11294 23:50:35.599339 aarch64) (Linux: 6.1.92-cip22 aa<8>[ 15.021635] <LAVA_SIGNAL_TESTSET STOP>
11295 23:50:35.599452 rch64)
11296 23:50:35.599700 Received signal: <TESTSET> STOP
11297 23:50:35.599767 Closing test_set drm_read
11298 23:50:35.602596 Using IGT_SRANDOM=1717544753 for randomisation
11299 23:50:35.605949 Opened device: /dev/dri/card0
11300 23:50:35.612296 No KMS driver or no outputs, pipes: 16, outputs: 0
11301 23:50:35.615574 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11302 23:50:35.622466 <8>[ 15.043593] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11303 23:50:35.622752 Received signal: <TESTSET> START kms_addfb_basic
11304 23:50:35.622850 Starting test_set kms_addfb_basic
11305 23:50:35.640136 <14>[ 15.063003] [IGT] kms_addfb_basic: executing
11306 23:50:35.653301 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<14>[ 15.072134] [IGT] kms_addfb_basic: starting subtest unused-handle
11307 23:50:35.653436 4)
11308 23:50:35.660098 Using IGT_SR<14>[ 15.080009] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
11309 23:50:35.663352 ANDOM=1717544753 for randomisation
11310 23:50:35.666682 Opened device: /dev/dri/card0
11311 23:50:35.673564 Starting subtest: unused-hand<14>[ 15.096800] [IGT] kms_addfb_basic: exiting, ret=0
11312 23:50:35.673647 le
11313 23:50:35.679914 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11314 23:50:35.686499 Test requirement not met in<8>[ 15.107748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11315 23:50:35.686766 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11317 23:50:35.693523 function igt_require_intel, file ../lib/drmtest.c:880:
11318 23:50:35.696805 Test requirement: is_intel_device(fd)
11319 23:50:35.709882 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:88<14>[ 15.130423] [IGT] kms_addfb_basic: executing
11320 23:50:35.710017 0:
11321 23:50:35.713278 Test requirement: is_intel_device(fd)
11322 23:50:35.719766 No KMS driver or no o<14>[ 15.140344] [IGT] kms_addfb_basic: starting subtest unused-pitches
11323 23:50:35.730157 utputs, pipes: 1<14>[ 15.148334] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
11324 23:50:35.730287 6, outputs: 0
11325 23:50:35.736149 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11326 23:50:35.743200 Using IGT_SRA<14>[ 15.165005] [IGT] kms_addfb_basic: exiting, ret=0
11327 23:50:35.746189 NDOM=1717544753 for randomisation
11328 23:50:35.749725 Opened device: /dev/dri/card0
11329 23:50:35.756072 Starting subte<8>[ 15.176119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11330 23:50:35.756403 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11332 23:50:35.759858 st: unused-pitches
11333 23:50:35.762625 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11334 23:50:35.769519 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11335 23:50:35.775971 Test requirement: is_i<14>[ 15.198508] [IGT] kms_addfb_basic: executing
11336 23:50:35.779200 ntel_device(fd)
11337 23:50:35.789365 Test requirement not met in function igt_requir<14>[ 15.208903] [IGT] kms_addfb_basic: starting subtest unused-offsets
11338 23:50:35.795840 e_intel, file ..<14>[ 15.216704] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
11339 23:50:35.799325 /lib/drmtest.c:880:
11340 23:50:35.802486 Test requirement: is_intel_device(fd)
11341 23:50:35.812811 No KMS driver or no outputs, pipes: <14>[ 15.233477] [IGT] kms_addfb_basic: exiting, ret=0
11342 23:50:35.812923 16, outputs: 0
11343 23:50:35.825569 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch6<8>[ 15.244571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11344 23:50:35.825670 4)
11345 23:50:35.825933 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11347 23:50:35.829017 Using IGT_SRANDOM=1717544754 for randomisation
11348 23:50:35.832643 Opened device: /dev/dri/card0
11349 23:50:35.836051 Starting subtest: unused-offsets
11350 23:50:35.838698 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11351 23:50:35.845458 Test requ<14>[ 15.267060] [IGT] kms_addfb_basic: executing
11352 23:50:35.859144 irement not met in function igt_require_intel, file ../lib/drmte<14>[ 15.277235] [IGT] kms_addfb_basic: starting subtest unused-modifier
11353 23:50:35.859264 st.c:880:
11354 23:50:35.865767 Test <14>[ 15.285176] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
11355 23:50:35.868935 requirement: is_intel_device(fd)
11356 23:50:35.878803 Test requirement not met in function igt_require_intel, file .<14>[ 15.302173] [IGT] kms_addfb_basic: exiting, ret=0
11357 23:50:35.881855 ./lib/drmtest.c:880:
11358 23:50:35.885301 Test requirement: is_intel_device(fd)
11359 23:50:35.892286 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11361 23:50:35.895699 No KMS driver or no<8>[ 15.313191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11362 23:50:35.895788 outputs, pipes: 16, outputs: 0
11363 23:50:35.902244 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11364 23:50:35.905561 Using IGT_SRANDOM=1717544754 for randomisation
11365 23:50:35.915056 Opened device: /dev/dri/car<14>[ 15.335748] [IGT] kms_addfb_basic: executing
11366 23:50:35.915166 d0
11367 23:50:35.918246 Starting subtest: unused-modifier
11368 23:50:35.925606 [1mSubtest unused-modifi<14>[ 15.346045] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11369 23:50:35.935640 er: SUCCESS (0.0<14>[ 15.354493] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11370 23:50:35.935750 00s)[0m
11371 23:50:35.944920 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11372 23:50:35.948543 Te<14>[ 15.371262] [IGT] kms_addfb_basic: exiting, ret=77
11373 23:50:35.952001 st requirement: is_intel_device(fd)
11374 23:50:35.961955 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11376 23:50:35.965237 Test requirement not met in function igt_re<8>[ 15.382497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11377 23:50:35.968528 quire_intel, file ../lib/drmtest.c:880:
11378 23:50:35.971724 Test requirement: is_intel_device(fd)
11379 23:50:35.974790 No KMS driver or no outputs, pipes: 16, outputs: 0
11380 23:50:35.985006 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<14>[ 15.405281] [IGT] kms_addfb_basic: executing
11381 23:50:35.985122 6.1.92-cip22 aarch64)
11382 23:50:35.998011 Using IGT_SRANDOM=1717544754 for randomi<14>[ 15.415704] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11383 23:50:35.998114 sation
11384 23:50:36.004485 Opened d<14>[ 15.424619] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11385 23:50:36.007892 evice: /dev/dri/card0
11386 23:50:36.011127 Starting subtest: clobberred-modifier
11387 23:50:36.021918 Test requirement not met in functi<14>[ 15.442311] [IGT] kms_addfb_basic: exiting, ret=77
11388 23:50:36.024429 on igt_require_i915, file ../lib/drmtest.c:885:
11389 23:50:36.034926 Test requirement: is_i915_devic<8>[ 15.453416] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11390 23:50:36.035031 e(fd)
11391 23:50:36.035298 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11393 23:50:36.041287 [1mSubtest clobberred-modifier: SKIP (0.000s)[0m
11394 23:50:36.048133 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11395 23:50:36.054761 Test requirement: is_intel_device<14>[ 15.477245] [IGT] kms_addfb_basic: executing
11396 23:50:36.054851 (fd)
11397 23:50:36.067414 Test requirement not met in function igt_require_intel, fi<14>[ 15.487342] [IGT] kms_addfb_basic: starting subtest legacy-format
11398 23:50:36.071174 le ../lib/drmtest.c:880:
11399 23:50:36.074490 Test requirement: is_intel_device(fd)
11400 23:50:36.080984 No KMS driver o<14>[ 15.501071] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11401 23:50:36.084201 r no outputs, pipes: 16, outputs: 0
11402 23:50:36.094296 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 a<14>[ 15.517255] [IGT] kms_addfb_basic: exiting, ret=0
11403 23:50:36.094402 arch64)
11404 23:50:36.101094 Using IGT_SRANDOM=1717544754 for randomisation
11405 23:50:36.107533 Opened <8>[ 15.527961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11406 23:50:36.107802 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11408 23:50:36.110853 device: /dev/dri/card0
11409 23:50:36.114117 Starting subtest: invalid-smem-bo-on-discrete
11410 23:50:36.120576 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11411 23:50:36.127585 Test requirement: is_<14>[ 15.549337] [IGT] kms_addfb_basic: executing
11412 23:50:36.130611 intel_device(fd)
11413 23:50:36.133601 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11414 23:50:36.140307 Te<14>[ 15.561834] [IGT] kms_addfb_basic: starting subtest no-handle
11415 23:50:36.150187 st requirement n<14>[ 15.568546] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11416 23:50:36.153984 ot met in function igt_require_intel, file ../lib/drmtest.c:880:
11417 23:50:36.160079 Test requireme<14>[ 15.582664] [IGT] kms_addfb_basic: exiting, ret=0
11418 23:50:36.163391 nt: is_intel_device(fd)
11419 23:50:36.173426 Test requirement not met in function ig<8>[ 15.594055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11420 23:50:36.173705 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11422 23:50:36.176856 t_require_intel, file ../lib/drmtest.c:880:
11423 23:50:36.180235 Test requirement: is_intel_device(fd)
11424 23:50:36.186709 No KMS driver or no outputs, pipes: 16, outputs: 0
11425 23:50:36.193749 IGT-Version: 1.28-ga44ebfe (aarch64) (Li<14>[ 15.615437] [IGT] kms_addfb_basic: executing
11426 23:50:36.196507 nux: 6.1.92-cip22 aarch64)
11427 23:50:36.200091 Using IGT_SRANDOM=1717544754 for randomisation
11428 23:50:36.206869 Open<14>[ 15.627611] [IGT] kms_addfb_basic: starting subtest basic
11429 23:50:36.213487 ed device: /dev/<14>[ 15.633980] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11430 23:50:36.213657 dri/card0
11431 23:50:36.216779 Starting subtest: legacy-format
11432 23:50:36.226605 Successfully fuzzed 10000 {bpp, dept<14>[ 15.647735] [IGT] kms_addfb_basic: exiting, ret=0
11433 23:50:36.226759 h} variations
11434 23:50:36.229747 [1mSubtest legacy-format: SUCCESS (0.006s)[0m
11435 23:50:36.240094 Test requirement<8>[ 15.659433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11436 23:50:36.240383 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11438 23:50:36.246501 not met in function igt_require_intel, file ../lib/drmtest.c:880:
11439 23:50:36.249862 Test requirement: is_intel_device(fd)
11440 23:50:36.260009 Test requirement not met in function igt_require_intel, file ../lib/d<14>[ 15.681188] [IGT] kms_addfb_basic: executing
11441 23:50:36.260161 rmtest.c:880:
11442 23:50:36.263217 Test requirement: is_intel_device(fd)
11443 23:50:36.272787 No KMS driver or no output<14>[ 15.693694] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11444 23:50:36.279636 s, pipes: 16, ou<14>[ 15.700628] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11445 23:50:36.282941 tputs: 0
11446 23:50:36.289498 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11447 23:50:36.292501 Us<14>[ 15.714876] [IGT] kms_addfb_basic: exiting, ret=0
11448 23:50:36.296645 ing IGT_SRANDOM=1717544754 for randomisation
11449 23:50:36.299888 Opened device: /dev/dri/card0
11450 23:50:36.306376 Sta<8>[ 15.726723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11451 23:50:36.306640 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11453 23:50:36.309752 rting subtest: no-handle
11454 23:50:36.312487 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11455 23:50:36.319728 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11456 23:50:36.326245 Test requirement: is_<14>[ 15.748995] [IGT] kms_addfb_basic: executing
11457 23:50:36.329473 intel_device(fd)
11458 23:50:36.339417 Test requirement not met in function igt_require_intel, file .<14>[ 15.761540] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11459 23:50:36.349341 ./lib/drmtest.c:<14>[ 15.768536] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11460 23:50:36.349434 880:
11461 23:50:36.352601 Test requirement: is_intel_device(fd)
11462 23:50:36.362603 No KMS driver or no outputs, pipes:<14>[ 15.782863] [IGT] kms_addfb_basic: exiting, ret=0
11463 23:50:36.362722 16, outputs: 0
11464 23:50:36.375744 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch<8>[ 15.794776] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11465 23:50:36.375844 64)
11466 23:50:36.376108 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11468 23:50:36.378696 Using IGT_SRANDOM=1717544754 for randomisation
11469 23:50:36.382295 Opened device: /dev/dri/card0
11470 23:50:36.385683 Starting subtest: basic
11471 23:50:36.388935 [1mSubtest basic: SUCCESS (0.000s)[0m
11472 23:50:36.395488 Test requirement not met i<14>[ 15.817032] [IGT] kms_addfb_basic: executing
11473 23:50:36.398653 n function igt_require_intel, file ../lib/drmtest.c:880:
11474 23:50:36.408888 Test requirement: is_i<14>[ 15.829422] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11475 23:50:36.408990 ntel_device(fd)
11476 23:50:36.415484 <14>[ 15.836296] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11477 23:50:36.415600
11478 23:50:36.428878 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:8<14>[ 15.850714] [IGT] kms_addfb_basic: exiting, ret=0
11479 23:50:36.428985 80:
11480 23:50:36.432128 Test requirement: is_intel_device(fd)
11481 23:50:36.442413 No KMS driver or no outputs, pipes: <8>[ 15.862558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11482 23:50:36.442700 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11484 23:50:36.445727 16, outputs: 0
11485 23:50:36.449054 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11486 23:50:36.455100 Using IGT_SRANDOM=1717544754 for randomisation
11487 23:50:36.458599 Opened device: /dev/dri/card0
11488 23:50:36.461771 Starting subt<14>[ 15.885047] [IGT] kms_addfb_basic: executing
11489 23:50:36.465122 est: bad-pitch-0
11490 23:50:36.468509 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11491 23:50:36.475452 Test requiremen<14>[ 15.897399] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11492 23:50:36.485329 t not met in fun<14>[ 15.904429] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11493 23:50:36.488554 ction igt_require_intel, file ../lib/drmtest.c:880:
11494 23:50:36.498376 Test requirement: is_intel_<14>[ 15.918876] [IGT] kms_addfb_basic: exiting, ret=0
11495 23:50:36.498483 device(fd)
11496 23:50:36.511278 Test requirement not met in function igt_require_intel, file ../lib/<8>[ 15.930605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11497 23:50:36.511391 drmtest.c:880:
11498 23:50:36.511650 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11500 23:50:36.514859 Test requirement: is_intel_device(fd)
11501 23:50:36.521472 No KMS driver or no outputs, pipes: 16, outputs: 0
11502 23:50:36.527661 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11503 23:50:36.531301 U<14>[ 15.953186] [IGT] kms_addfb_basic: executing
11504 23:50:36.534553 sing IGT_SRANDOM=1717544754 for randomisation
11505 23:50:36.538166 Opened device: /dev/dri/card0
11506 23:50:36.544352 St<14>[ 15.965567] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11507 23:50:36.554130 arting subtest: <14>[ 15.972624] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11508 23:50:36.554320 bad-pitch-32
11509 23:50:36.557399 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11510 23:50:36.564196 Test requirement n<14>[ 15.987091] [IGT] kms_addfb_basic: exiting, ret=0
11511 23:50:36.570881 ot met in function igt_require_intel, file ../lib/drmtest.c:880:
11512 23:50:36.580862 Test requireme<8>[ 15.998856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11513 23:50:36.580969 nt: is_intel_device(fd)
11514 23:50:36.581226 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11516 23:50:36.590611 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11517 23:50:36.594035 Test requirement: is_intel_device(fd)
11518 23:50:36.600354 No KMS driver or no outputs,<14>[ 16.021341] [IGT] kms_addfb_basic: executing
11519 23:50:36.600508 pipes: 16, outputs: 0
11520 23:50:36.613731 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip2<14>[ 16.033951] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11521 23:50:36.613827 2 aarch64)
11522 23:50:36.620227 Usin<14>[ 16.040823] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11523 23:50:36.626780 g IGT_SRANDOM=1717544754 for randomisation
11524 23:50:36.626871 Opened device: /dev/dri/card0
11525 23:50:36.633455 Start<14>[ 16.055413] [IGT] kms_addfb_basic: exiting, ret=0
11526 23:50:36.636768 ing subtest: bad-pitch-63
11527 23:50:36.640054 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11528 23:50:36.646892 Test <8>[ 16.067444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11529 23:50:36.647156 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11531 23:50:36.656505 requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11532 23:50:36.659513 Test requirement: is_intel_device(fd)
11533 23:50:36.666572 Test requirement not met in function igt_require_intel, fi<14>[ 16.089913] [IGT] kms_addfb_basic: executing
11534 23:50:36.669676 le ../lib/drmtest.c:880:
11535 23:50:36.672770 Test requirement: is_intel_device(fd)
11536 23:50:36.682750 No KMS driver o<14>[ 16.102211] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11537 23:50:36.689399 r no outputs, pi<14>[ 16.109291] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11538 23:50:36.692581 pes: 16, outputs: 0
11539 23:50:36.702537 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 a<14>[ 16.123752] [IGT] kms_addfb_basic: exiting, ret=0
11540 23:50:36.702639 arch64)
11541 23:50:36.705700 Using IGT_SRANDOM=1717544754 for randomisation
11542 23:50:36.715624 Opened device: /dev/dri<8>[ 16.135420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11543 23:50:36.715714 /card0
11544 23:50:36.715951 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11546 23:50:36.719013 Starting subtest: bad-pitch-128
11547 23:50:36.722474 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11548 23:50:36.735485 Test requirement not met in function igt_require_intel, file ../lib/dr<14>[ 16.157792] [IGT] kms_addfb_basic: executing
11549 23:50:36.735641 mtest.c:880:
11550 23:50:36.738627 Test requirement: is_intel_device(fd)
11551 23:50:36.748856 Test requirement not met in<14>[ 16.169204] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11552 23:50:36.755719 function igt_re<14>[ 16.176321] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11553 23:50:36.761882 quire_intel, file ../lib/drmtest.c:880:
11554 23:50:36.765439 Test requirement: is_intel_device(fd)
11555 23:50:36.768790 <14>[ 16.190953] [IGT] kms_addfb_basic: exiting, ret=0
11556 23:50:36.775451 No KMS driver or no outputs, pipes: 16, outputs: 0
11557 23:50:36.782011 IGT-Version: 1.28-ga44ebfe (<8>[ 16.202876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11558 23:50:36.782325 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11560 23:50:36.788248 aarch64) (Linux: 6.1.92-cip22 aarch64)
11561 23:50:36.792064 Using IGT_SRANDOM=1717544754 for randomisation
11562 23:50:36.794837 Opened device: /dev/dri/card0
11563 23:50:36.794936 Starting subtest: bad-pitch-256
11564 23:50:36.802087 [1mSubt<14>[ 16.225058] [IGT] kms_addfb_basic: executing
11565 23:50:36.804818 est bad-pitch-256: SUCCESS (0.000s)[0m
11566 23:50:36.817970 Test requirement not met in function igt_require_intel, file ../lib/drm<14>[ 16.238769] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11567 23:50:36.821648 test.c:880:
11568 23:50:36.827922 Tes<14>[ 16.246786] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11569 23:50:36.831296 t requirement: is_intel_device(fd)
11570 23:50:36.838113 Test require<14>[ 16.260091] [IGT] kms_addfb_basic: exiting, ret=0
11571 23:50:36.844776 ment not met in function igt_require_intel, file ../lib/drmtest.c:880:
11572 23:50:36.851476 Test req<8>[ 16.271007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11573 23:50:36.851735 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11575 23:50:36.854741 uirement: is_intel_device(fd)
11576 23:50:36.857938 No KMS driver or no outputs, pipes: 16, outputs: 0
11577 23:50:36.864728 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11578 23:50:36.871478 Using IGT_SRANDOM=1717544<14>[ 16.294220] [IGT] kms_addfb_basic: executing
11579 23:50:36.874843 754 for randomisation
11580 23:50:36.878126 Opened device: /dev/dri/card0
11581 23:50:36.881612 Starting subtest: bad-pitch-1024
11582 23:50:36.888151 [1mSubtest bad-pitch-10<14>[ 16.308304] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11583 23:50:36.897603 24: SUCCESS (0.0<14>[ 16.316476] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11584 23:50:36.897725 00s)[0m
11585 23:50:36.907684 Test requirement not met in function i<14>[ 16.329285] [IGT] kms_addfb_basic: exiting, ret=0
11586 23:50:36.910826 gt_require_intel, file ../lib/drmtest.c:880:
11587 23:50:36.920871 Test requirement: is_intel_device(<8>[ 16.340201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11588 23:50:36.920989 fd)
11589 23:50:36.921237 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11591 23:50:36.927302 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11592 23:50:36.930902 Test requirement: is_intel_device(fd)
11593 23:50:36.940690 No KMS driver or no outputs, pip<14>[ 16.362472] [IGT] kms_addfb_basic: executing
11594 23:50:36.940778 es: 16, outputs: 0
11595 23:50:36.947305 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11596 23:50:36.957071 Using IGT_SRANDOM=171754<14>[ 16.376024] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11597 23:50:36.964003 4754 for randomi<14>[ 16.384288] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11598 23:50:36.967362 sation
11599 23:50:36.970572 Opened device: /dev/dri/card0
11600 23:50:36.977143 Starting subtest: bad-pit<14>[ 16.397691] [IGT] kms_addfb_basic: exiting, ret=0
11601 23:50:36.977227 ch-999
11602 23:50:36.980626 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11603 23:50:36.990445 Test requirement not me<8>[ 16.409755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11604 23:50:36.990714 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11606 23:50:36.997076 t in function igt_require_intel, file ../lib/drmtest.c:880:
11607 23:50:37.000283 Test requirement: is_intel_device(fd)
11608 23:50:37.010428 Test requirement not met in function igt_require_intel, file<14>[ 16.432593] [IGT] kms_addfb_basic: executing
11609 23:50:37.010518 ../lib/drmtest.c:880:
11610 23:50:37.013825 Test requirement: is_intel_device(fd)
11611 23:50:37.027257 No KMS driver or no outputs, pipes: 16, outputs: <14>[ 16.445976] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11612 23:50:37.027362 0
11613 23:50:37.033359 IGT-Version: <14>[ 16.454085] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11614 23:50:37.043303 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aar<14>[ 16.466834] [IGT] kms_addfb_basic: exiting, ret=0
11615 23:50:37.043393 ch64)
11616 23:50:37.050742 Using IGT_SRANDOM=1717544754 for randomisation
11617 23:50:37.056848 Opened device: /dev/dri/c<8>[ 16.477778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11618 23:50:37.057124 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11620 23:50:37.060191 ard0
11621 23:50:37.063407 Starting subtest: bad-pitch-65536
11622 23:50:37.067261 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11623 23:50:37.073676 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11624 23:50:37.076752 <14>[ 16.500431] [IGT] kms_addfb_basic: executing
11625 23:50:37.083559 Test requirement: is_intel_device(fd)
11626 23:50:37.090386 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11627 23:50:37.096841 Test <14>[ 16.516979] [IGT] kms_addfb_basic: starting subtest master-rmfb
11628 23:50:37.103387 requirement: is_<14>[ 16.524079] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11629 23:50:37.106668 intel_device(fd)
11630 23:50:37.113504 No KMS driver <14>[ 16.534615] [IGT] kms_addfb_basic: exiting, ret=0
11631 23:50:37.116737 or no outputs, pipes: 16, outputs: 0
11632 23:50:37.123650 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11634 23:50:37.126772 IGT-Version: 1.28-ga44ebfe<8>[ 16.545088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11635 23:50:37.130020 (aarch64) (Linux: 6.1.92-cip22 aarch64)
11636 23:50:37.133514 Using IGT_SRANDOM=1717544755 for randomisation
11637 23:50:37.136789 Opened device: /dev/dri/card0
11638 23:50:37.139934 Starting subtest: invalid-get-prop-any
11639 23:50:37.146498 [1mSubtest inv<14>[ 16.567446] [IGT] kms_addfb_basic: executing
11640 23:50:37.149535 alid-get-prop-any: SUCCESS (0.000s)[0m
11641 23:50:37.156664 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11642 23:50:37.166441 Test requirement: i<14>[ 16.585217] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11643 23:50:37.172809 s_intel_device(f<14>[ 16.592971] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11644 23:50:37.176110 d)
11645 23:50:37.179435 Test require<14>[ 16.602661] [IGT] kms_addfb_basic: exiting, ret=0
11646 23:50:37.192775 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11648 23:50:37.195750 ment not met in function igt_require_intel, file ../lib/drmtest.<8>[ 16.613272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11649 23:50:37.195829 c:880:
11650 23:50:37.199249 Test requirement: is_intel_device(fd)
11651 23:50:37.202424 No KMS driver or no outputs, pipes: 16, outputs: 0
11652 23:50:37.213188 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aar<14>[ 16.635947] [IGT] kms_addfb_basic: executing
11653 23:50:37.213299 ch64)
11654 23:50:37.219141 Using IGT_SRANDOM=1717544755 for randomisation
11655 23:50:37.219224 Opened device: /dev/dri/card0
11656 23:50:37.222558 Starting subtest: invalid-get-prop
11657 23:50:37.232586 [1mSubtest invalid-ge<14>[ 16.653411] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11658 23:50:37.235914 t-prop: SUCCESS (0.000s)[0m
11659 23:50:37.242535 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11660 23:50:37.245878 Test requirement: is_intel_device(fd)
11661 23:50:37.252617 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11662 23:50:37.255771 Test requirement: is_intel_device(fd)
11663 23:50:37.262574 No KMS driver or no outputs, pipes: 16, outputs: 0
11664 23:50:37.265847 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11665 23:50:37.272497 Using IGT_SRANDOM=1717544755 for randomisation
11666 23:50:37.272608 Opened device: /dev/dri/card0
11667 23:50:37.279016 Starting subtest: invalid-set-prop-any
11668 23:50:37.282480 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11669 23:50:37.288926 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11670 23:50:37.292387 Test requirement: is_intel_device(fd)
11671 23:50:37.299035 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11672 23:50:37.302349 Test requirement: is_intel_device(fd)
11673 23:50:37.308597 No KMS driver or no outputs, pipes: 16, outputs: 0
11674 23:50:37.315500 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11675 23:50:37.318848 Using IGT_SRANDOM=1717544755 for randomisation
11676 23:50:37.322133 Opened device: /dev/dri/card0
11677 23:50:37.325328 Starting subtest: invalid-set-prop
11678 23:50:37.328736 [1mSubtest invalid-set-prop: SUCCESS (0.000s)[0m
11679 23:50:37.335243 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11680 23:50:37.338655 Test requirement: is_intel_device(fd)
11681 23:50:37.345216 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11682 23:50:37.348528 Test requirement: is_intel_device(fd)
11683 23:50:37.355124 No KMS driver or no outputs, pipes: 16, outputs: 0
11684 23:50:37.362015 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11685 23:50:37.365363 Using IGT_SRANDOM=1717544755 for randomisation
11686 23:50:37.368775 Opened device: /dev/dri/card0
11687 23:50:37.368920 Starting subtest: master-rmfb
11688 23:50:37.375185 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11689 23:50:37.381820 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11690 23:50:37.385335 Test requirement: is_intel_device(fd)
11691 23:50:37.391891 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11692 23:50:37.395418 Test requirement: is_intel_device(fd)
11693 23:50:37.398079 No KMS driver or no outputs, pipes: 16, outputs: 0
11694 23:50:37.405133 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11695 23:50:37.412043 Using IGT_SRANDOM=1717544755 for randomisation
11696 23:50:37.412185 Opened device: /dev/dri/card0
11697 23:50:37.415032 Starting subtest: addfb25-modifier-no-flag
11698 23:50:37.421606 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11699 23:50:37.428162 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11700 23:50:37.431434 Test requirement: is_intel_device(fd)
11701 23:50:37.438382 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11702 23:50:37.441413 Test requirement: is_intel_device(fd)
11703 23:50:37.447995 No KMS driver or no outputs, pipes: 16, outputs: 0
11704 23:50:37.454804 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11705 23:50:37.457979 Using IGT_SRANDOM=1717544755 for randomisation
11706 23:50:37.461325 Opened device: /dev/dri/card0
11707 23:50:37.464699 Starting subtest: addfb25-bad-modifier
11708 23:50:37.474233 (kms_addfb_basic:441) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11709 23:50:37.490939 (kms_addfb_basic:441) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11710 23:50:37.497562 (kms_addfb_basic:441) CRITICAL: error: 0 != -1
11711 23:50:37.497643 Stack trace:
11712 23:50:37.500905 #0 ../lib/igt_core.c:1989 __igt_fail_assert()
11713 23:50:37.504443 #1 [<unknown>+0xc6594358]
11714 23:50:37.507493 #2 [<unknown>+0xc6595fbc]
11715 23:50:37.507568 #3 [<unknown>+0xc659156c]
11716 23:50:37.510844 #4 [__libc_init_first+0x80]
11717 23:50:37.514184 #5 [__libc_start_main+0x98]
11718 23:50:37.517592 #6 [<unknown>+0xc65915b0]
11719 23:50:37.520861 Subtest addfb25-bad-modifier failed.
11720 23:50:37.520943 **** DEBUG ****
11721 23:50:37.530842 (kms_addfb_basic:441) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11722 23:50:37.540772 (kms_addfb_basic:441) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:714:
11723 23:50:37.557270 (kms_addfb_basic:441) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11724 23:50:37.560266 (kms_addfb_basic:441) CRITICAL: error: 0 != -1
11725 23:50:37.567010 (kms_addfb_basic:441) igt_core-INFO: Stack trace:
11726 23:50:37.580690 (kms_addfb_basic:441) igt_core-INFO: #0 ../lib/igt_core.c:1989 __igt_fail<14>[ 16.999835] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11727 23:50:37.580841 _assert()
11728 23:50:37.587180 (kms_<14>[ 17.008863] [IGT] kms_addfb_basic: exiting, ret=98
11729 23:50:37.593745 addfb_basic:441) igt_core-INFO: #1 [<unknown>+0xc6594358]
11730 23:50:37.600525 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11732 23:50:37.603479 (kms_addfb_basic:44<8>[ 17.021299] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11733 23:50:37.606763 1) igt_core-INFO: #2 [<unknown>+0xc6595fbc]
11734 23:50:37.613468 (kms_addfb_basic:441) igt_core-INFO: #3 [<unknown>+0xc659156c]
11735 23:50:37.620192 (kms_addfb_basic:441) igt_core-INFO: #4 [__li<14>[ 17.043737] [IGT] kms_addfb_basic: executing
11736 23:50:37.623638 bc_init_first+0x80]
11737 23:50:37.630168 (kms_addfb_basic:441) igt_core-INFO: #5 [__libc_start_main+0x98]
11738 23:50:37.633305 (kms_addfb_basic:441) igt_core-INFO: #6 [<unknown>+0xc65915b0]
11739 23:50:37.639924 **** <14>[ 17.061441] [IGT] kms_addfb_basic: exiting, ret=77
11740 23:50:37.640029 END ****
11741 23:50:37.646789 [1mSubtest addfb25-bad-modifier: FAIL (0.339s)[0m
11742 23:50:37.652868 <8>[ 17.072086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11743 23:50:37.652948
11744 23:50:37.653188 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11746 23:50:37.659458 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11747 23:50:37.666300 Test requirement: is_intel_device(fd)
11748 23:50:37.672943 Test requirement not met in function<14>[ 17.094449] [IGT] kms_addfb_basic: executing
11749 23:50:37.675980 igt_require_intel, file ../lib/drmtest.c:880:
11750 23:50:37.679563 Test requirement: is_intel_device(fd)
11751 23:50:37.686265 No KMS driver or no outputs, pipes: 16, outputs: 0
11752 23:50:37.692726 IGT-Version: 1.28-ga4<14>[ 17.113387] [IGT] kms_addfb_basic: exiting, ret=77
11753 23:50:37.696445 4ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11754 23:50:37.705892 Using IGT_SRANDOM<8>[ 17.124139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11755 23:50:37.706188 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11757 23:50:37.709697 =1717544755 for randomisation
11758 23:50:37.709780 Opened device: /dev/dri/card0
11759 23:50:37.719252 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11760 23:50:37.722756 Test requireme<14>[ 17.146380] [IGT] kms_addfb_basic: executing
11761 23:50:37.726382 nt: is_intel_device(fd)
11762 23:50:37.732731 [1mSubtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11763 23:50:37.742809 Test requirement not met in function igt_require_intel, file ../lib/drm<14>[ 17.164237] [IGT] kms_addfb_basic: exiting, ret=77
11764 23:50:37.742917 test.c:880:
11765 23:50:37.746185 Test requirement: is_intel_device(fd)
11766 23:50:37.756030 No KMS drive<8>[ 17.175316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11767 23:50:37.756316 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11769 23:50:37.759214 r or no outputs, pipes: 16, outputs: 0
11770 23:50:37.765966 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11771 23:50:37.769494 Using IGT_SRANDOM=1717544755 for randomisation
11772 23:50:37.776200 Open<14>[ 17.198477] [IGT] kms_addfb_basic: executing
11773 23:50:37.779390 ed device: /dev/dri/card0
11774 23:50:37.785740 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11775 23:50:37.789385 Test requirement: is_intel_device(fd)
11776 23:50:37.795915 [1mSubtes<14>[ 17.216285] [IGT] kms_addfb_basic: exiting, ret=77
11777 23:50:37.799134 t addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11778 23:50:37.808705 Test requirement no<8>[ 17.227509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11779 23:50:37.808961 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11781 23:50:37.812540 t met in function igt_require_intel, file ../lib/drmtest.c:880:
11782 23:50:37.815436 Test requirement: is_intel_device(fd)
11783 23:50:37.821906 No KMS driver or no outputs, pipes: 16, outputs: 0
11784 23:50:37.825887 IGT-<14>[ 17.249085] [IGT] kms_addfb_basic: executing
11785 23:50:37.832164 Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11786 23:50:37.835570 Using IGT_SRANDOM=1717544755 for randomisation
11787 23:50:37.839011 Opened device: /dev/dri/card0
11788 23:50:37.845550 Test requirement <14>[ 17.267150] [IGT] kms_addfb_basic: exiting, ret=77
11789 23:50:37.858767 not met in function igt_require_intel, file ../lib/drmtest.c:880<8>[ 17.278137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11790 23:50:37.858856 :
11791 23:50:37.859100 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11793 23:50:37.862121 Test requirement: is_intel_device(fd)
11794 23:50:37.868730 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11795 23:50:37.878725 Test requirement not met in function igt_require_int<14>[ 17.300890] [IGT] kms_addfb_basic: executing
11796 23:50:37.882236 el, file ../lib/drmtest.c:880:
11797 23:50:37.885495 Test requirement: is_intel_device(fd)
11798 23:50:37.888829 No KMS driver or no outputs, pipes: 16, outputs: 0
11799 23:50:37.898779 IGT-Version: 1.28-ga44ebfe (aarch64) <14>[ 17.318680] [IGT] kms_addfb_basic: exiting, ret=77
11800 23:50:37.898865 (Linux: 6.1.92-cip22 aarch64)
11801 23:50:37.909052 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11803 23:50:37.911968 Using IGT_SRANDOM=1717544756 for <8>[ 17.329697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11804 23:50:37.912057 randomisation
11805 23:50:37.915318 Opened device: /dev/dri/card0
11806 23:50:37.922000 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11807 23:50:37.928466 Test requirement: is_intel_dev<14>[ 17.351849] [IGT] kms_addfb_basic: executing
11808 23:50:37.928550 ice(fd)
11809 23:50:37.938463 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11810 23:50:37.941934 Test requirement: is_intel_device(fd)
11811 23:50:37.948197 [1mSubtest basic-x-tiled-le<14>[ 17.369700] [IGT] kms_addfb_basic: exiting, ret=77
11812 23:50:37.951298 gacy: SKIP (0.000s)[0m
11813 23:50:37.961879 No KMS driver or no outputs, pipes: 16,<8>[ 17.380631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11814 23:50:37.962039 outputs: 0
11815 23:50:37.962331 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11817 23:50:37.968376 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11818 23:50:37.971879 Using IGT_SRANDOM=1717544756 for randomisation
11819 23:50:37.974800 Opened device: /dev/dri/card0
11820 23:50:37.978450 <14>[ 17.402752] [IGT] kms_addfb_basic: executing
11821 23:50:37.988049 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11822 23:50:37.991155 Test requirement: is_intel_device(fd)
11823 23:50:37.997936 Test requirement not met in function <14>[ 17.420618] [IGT] kms_addfb_basic: exiting, ret=77
11824 23:50:38.001671 igt_require_intel, file ../lib/drmtest.c:880:
11825 23:50:38.011229 Test requirement:<8>[ 17.431531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11826 23:50:38.011500 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11828 23:50:38.014584 is_intel_device(fd)
11829 23:50:38.017761 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11830 23:50:38.021510 No KMS driver or no outputs, pipes: 16, outputs: 0
11831 23:50:38.031593 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux:<14>[ 17.453097] [IGT] kms_addfb_basic: executing
11832 23:50:38.034241 6.1.92-cip22 aarch64)
11833 23:50:38.037582 Using IGT_SRANDOM=1717544756 for randomisation
11834 23:50:38.040958 Opened device: /dev/dri/card0
11835 23:50:38.050876 Test requirement not met in function igt_require_intel, f<14>[ 17.471892] [IGT] kms_addfb_basic: exiting, ret=77
11836 23:50:38.050953 ile ../lib/drmtest.c:880:
11837 23:50:38.060926 Test requirement: is_intel_device(fd)<8>[ 17.482655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11838 23:50:38.061006
11839 23:50:38.061240 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11841 23:50:38.071016 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11842 23:50:38.074603 Test requirement: is_intel_device(fd)
11843 23:50:38.080926 [1mSubtest tile-pitch-mismatch: SK<14>[ 17.503401] [IGT] kms_addfb_basic: executing
11844 23:50:38.081035 IP (0.000s)[0m
11845 23:50:38.087307 No KMS driver or no outputs, pipes: 16, outputs: 0
11846 23:50:38.094375 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11847 23:50:38.100831 Using IGT_SRANDOM=17175<14>[ 17.521589] [IGT] kms_addfb_basic: exiting, ret=77
11848 23:50:38.100910 44756 for randomisation
11849 23:50:38.103830 Opened device: /dev/dri/card0
11850 23:50:38.110800 Test req<8>[ 17.532598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11851 23:50:38.111080 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11853 23:50:38.117572 uirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11854 23:50:38.124043 Test requirement: is_intel_device(fd)
11855 23:50:38.130579 Test requirement not met in function igt_requ<14>[ 17.553607] [IGT] kms_addfb_basic: executing
11856 23:50:38.133732 ire_intel, file ../lib/drmtest.c:880:
11857 23:50:38.137056 Test requirement: is_intel_device(fd)
11858 23:50:38.143935 [1mSubtest basic-y-tiled-legacy: SKIP (0.000s)[0m
11859 23:50:38.150795 No KMS driver or no outputs, <14>[ 17.571601] [IGT] kms_addfb_basic: exiting, ret=77
11860 23:50:38.150962 pipes: 16, outputs: 0
11861 23:50:38.163638 IGT-Version: 1.28-ga44ebfe (aarch64) (Lin<8>[ 17.582810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11862 23:50:38.163791 ux: 6.1.92-cip22 aarch64)
11863 23:50:38.164070 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11865 23:50:38.170379 Using IGT_SRANDOM=1717544756 for randomisation
11866 23:50:38.170557 Opened device: /dev/dri/card0
11867 23:50:38.180183 Test requirement not met in function igt_require_intel<14>[ 17.604337] [IGT] kms_addfb_basic: executing
11868 23:50:38.183606 , file ../lib/drmtest.c:880:
11869 23:50:38.186861 Test requirement: is_intel_device(fd)
11870 23:50:38.193372 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11871 23:50:38.199883 Test re<14>[ 17.621760] [IGT] kms_addfb_basic: exiting, ret=77
11872 23:50:38.203740 quirement: is_intel_device(fd)
11873 23:50:38.213490 No KMS driver or no outputs, pip<8>[ 17.632950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11874 23:50:38.213577 es: 16, outputs: 0
11875 23:50:38.213818 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11877 23:50:38.216744 [1mSubtest size-max: SKIP (0.000s)[0m
11878 23:50:38.222831 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11879 23:50:38.229943 Using IGT_SRANDOM=1717544756 fo<14>[ 17.653747] [IGT] kms_addfb_basic: executing
11880 23:50:38.233097 r randomisation
11881 23:50:38.236520 Opened device: /dev/dri/card0
11882 23:50:38.242634 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11883 23:50:38.249751 Test requirement: is_intel_d<14>[ 17.671845] [IGT] kms_addfb_basic: exiting, ret=77
11884 23:50:38.249848 evice(fd)
11885 23:50:38.262933 Test requirement not met in function igt_require_inte<8>[ 17.682845] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11886 23:50:38.263203 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11888 23:50:38.266504 l, file ../lib/drmtest.c:880:
11889 23:50:38.270008 Test requirement: is_intel_device(fd)
11890 23:50:38.275961 No KMS driver or no outputs, pipes: 16, outputs: 0
11891 23:50:38.282723 [1mSubtest too-wide: SKIP (0.000s)[0<14>[ 17.705569] [IGT] kms_addfb_basic: executing
11892 23:50:38.282811 m
11893 23:50:38.289666 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11894 23:50:38.292863 Using IGT_SRANDOM=1717544756 for randomisation
11895 23:50:38.296265 Opened device: /dev/dri/card0
11896 23:50:38.302518 Test requi<14>[ 17.723226] [IGT] kms_addfb_basic: exiting, ret=77
11897 23:50:38.315713 rement not met in function igt_require_intel, file ../lib/drmtes<8>[ 17.734025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11898 23:50:38.315809 t.c:880:
11899 23:50:38.316083 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11901 23:50:38.319474 Test requirement: is_intel_device(fd)
11902 23:50:38.326244 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11903 23:50:38.332441 Test requirement: is_intel_<14>[ 17.756538] [IGT] kms_addfb_basic: executing
11904 23:50:38.335737 device(fd)
11905 23:50:38.338842 No KMS driver or no outputs, pipes: 16, outputs: 0
11906 23:50:38.342383 [1mSubtest too-high: SKIP (0.000s)[0m
11907 23:50:38.352511 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip<14>[ 17.774342] [IGT] kms_addfb_basic: exiting, ret=77
11908 23:50:38.355586 22 aarch64)
11909 23:50:38.358687 Using IGT_SRANDOM=1717544756 for randomisation
11910 23:50:38.365250 Ope<8>[ 17.785655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11911 23:50:38.365514 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11913 23:50:38.368634 ned device: /dev/dri/card0
11914 23:50:38.375348 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11915 23:50:38.379093 Test requirement: is_intel_device(fd)
11916 23:50:38.385545 Test requ<14>[ 17.807967] [IGT] kms_addfb_basic: executing
11917 23:50:38.391807 irement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11918 23:50:38.395520 Test requirement: is_intel_device(fd)
11919 23:50:38.405529 No KMS driver or no outputs, pipes: 16, output<14>[ 17.825541] [IGT] kms_addfb_basic: exiting, ret=77
11920 23:50:38.405625 s: 0
11921 23:50:38.408832 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11922 23:50:38.418881 IGT-Version: <8>[ 17.836518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11923 23:50:38.419145 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11925 23:50:38.421621 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11926 23:50:38.428236 Using IGT_SRANDOM=1717544756 for randomisation
11927 23:50:38.428364 Opened device: /dev/dri/card0
11928 23:50:38.435311 Test requirement not met i<14>[ 17.859224] [IGT] kms_addfb_basic: executing
11929 23:50:38.441813 n function igt_require_intel, file ../lib/drmtest.c:880:
11930 23:50:38.445210 Test requirement: is_intel_device(fd)
11931 23:50:38.455007 Test requirement not met in function igt_require_intel, file ..<14>[ 17.877386] [IGT] kms_addfb_basic: exiting, ret=77
11932 23:50:38.458284 /lib/drmtest.c:880:
11933 23:50:38.461425 Test requirement: is_intel_device(fd)
11934 23:50:38.468466 No K<8>[ 17.887871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11935 23:50:38.468724 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11937 23:50:38.474963 MS driver or no outputs, pipes: <8>[ 17.898859] <LAVA_SIGNAL_TESTSET STOP>
11938 23:50:38.475216 Received signal: <TESTSET> STOP
11939 23:50:38.475288 Closing test_set kms_addfb_basic
11940 23:50:38.478444 16, outputs: 0
11941 23:50:38.481484 [1mSubtest small-bo: SKIP (0.000s)[0m
11942 23:50:38.484708 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
11943 23:50:38.491778 Using IGT_SRANDOM=1717544756 for randomisation
11944 23:50:38.491869 Opened device: /dev/dri/card0
11945 23:50:38.498339 Received signal: <TESTSET> START kms_atomic
11946 23:50:38.498422 Starting test_set kms_atomic
11947 23:50:38.501916 Test requirement not<8>[ 17.921778] <LAVA_SIGNAL_TESTSET START kms_atomic>
11948 23:50:38.504906 met in function igt_require_intel, file ../lib/drmtest.c:880:
11949 23:50:38.508033 Test requirement: is_intel_device(fd)
11950 23:50:38.517718 Test requirement not met in function igt_require_intel, f<14>[ 17.941653] [IGT] kms_atomic: executing
11951 23:50:38.524430 ile ../lib/drmte<14>[ 17.946539] [IGT] kms_atomic: exiting, ret=77
11952 23:50:38.524522 st.c:880:
11953 23:50:38.527788 Test requirement: is_intel_device(fd)
11954 23:50:38.537920 No KMS driver <8>[ 17.956640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11955 23:50:38.538178 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11957 23:50:38.540976 or no outputs, pipes: 16, outputs: 0
11958 23:50:38.544538 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11959 23:50:38.554265 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch<14>[ 17.978918] [IGT] kms_atomic: executing
11960 23:50:38.557615 64)
11961 23:50:38.560702 Using IGT_S<14>[ 17.984041] [IGT] kms_atomic: exiting, ret=77
11962 23:50:38.564036 RANDOM=1717544756 for randomisation
11963 23:50:38.574254 Opened device: /dev/dri/car<8>[ 17.994101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11964 23:50:38.574339 d0
11965 23:50:38.574578 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11967 23:50:38.583798 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11968 23:50:38.587601 Test requirement: is_intel_device(fd)
11969 23:50:38.593883 Test requirement not met in funct<14>[ 18.016595] [IGT] kms_atomic: executing
11970 23:50:38.600517 ion igt_require_<14>[ 18.021531] [IGT] kms_atomic: exiting, ret=77
11971 23:50:38.604261 intel, file ../lib/drmtest.c:880:
11972 23:50:38.613904 Test requirement: is_intel_de<8>[ 18.032442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11973 23:50:38.613995 vice(fd)
11974 23:50:38.614256 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11976 23:50:38.620229 No KMS driver or no outputs, pipes: 16, outputs: 0
11977 23:50:38.624131 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.000s)[0m
11978 23:50:38.630559 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<14>[ 18.055508] [IGT] kms_atomic: executing
11979 23:50:38.637071 : 6.1.92-cip22 a<14>[ 18.060460] [IGT] kms_atomic: exiting, ret=77
11980 23:50:38.640175 arch64)
11981 23:50:38.643537 Using IGT_SRANDOM=1717544756 for randomisation
11982 23:50:38.650703 Opened <8>[ 18.071097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11983 23:50:38.650971 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11985 23:50:38.653755 device: /dev/dri/card0
11986 23:50:38.660276 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
11987 23:50:38.663645 Test requirement: is_intel_device(fd)
11988 23:50:38.670164 Test requirement not met in f<14>[ 18.093174] [IGT] kms_atomic: executing
11989 23:50:38.677269 unction igt_requ<14>[ 18.099227] [IGT] kms_atomic: exiting, ret=77
11990 23:50:38.680379 ire_intel, file ../lib/drmtest.c:880:
11991 23:50:38.690102 Test requirement: is_inte<8>[ 18.109671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11992 23:50:38.690223 l_device(fd)
11993 23:50:38.690527 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11995 23:50:38.693394 No KMS driver or no outputs, pipes: 16, outputs: 0
11996 23:50:38.700518 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11997 23:50:38.706845 IGT-Version: 1.28-ga44ebfe (aarch64) (<14>[ 18.131023] [IGT] kms_atomic: executing
11998 23:50:38.713120 Linux: 6.1.92-ci<14>[ 18.135957] [IGT] kms_atomic: exiting, ret=77
11999 23:50:38.713276 p22 aarch64)
12000 23:50:38.719848 Using IGT_SRANDOM=1717544756 for randomisation
12001 23:50:38.726858 Op<8>[ 18.146355] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
12002 23:50:38.727203 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
12004 23:50:38.730272 ened device: /dev/dri/card0
12005 23:50:38.736718 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12006 23:50:38.740528 Test requirement: is_intel_device(fd)
12007 23:50:38.746816 Test requirement not met<14>[ 18.169099] [IGT] kms_atomic: executing
12008 23:50:38.753278 in function igt<14>[ 18.174809] [IGT] kms_atomic: exiting, ret=77
12009 23:50:38.756482 _require_intel, file ../lib/drmtest.c:880:
12010 23:50:38.766251 Test requirement: is<8>[ 18.184883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
12011 23:50:38.766337 _intel_device(fd)
12012 23:50:38.766580 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
12014 23:50:38.773347 No KMS driver or no outputs, pipes: 16, outputs: 0
12015 23:50:38.776534 [1mSubtest addfb25-y-tiled-small-legacy: SKIP (0.000s)[0m
12016 23:50:38.783015 IGT-Version: 1.28-ga44ebfe (<14>[ 18.206969] [IGT] kms_atomic: executing
12017 23:50:38.789521 aarch64) (Linux:<14>[ 18.212309] [IGT] kms_atomic: exiting, ret=77
12018 23:50:38.792923 6.1.92-cip22 aarch64)
12019 23:50:38.802884 Using IGT_SRANDOM=1717544756 for randomi<8>[ 18.222461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
12020 23:50:38.802991 sation
12021 23:50:38.803271 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
12023 23:50:38.806181 Opened device: /dev/dri/card0
12024 23:50:38.812812 Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:880:
12025 23:50:38.816168 Test requirement: is_intel_device(fd)
12026 23:50:38.825834 Test requirement not met in function igt_requi<14>[ 18.248882] [IGT] kms_atomic: executing
12027 23:50:38.832810 re_intel, file .<14>[ 18.254486] [IGT] kms_atomic: exiting, ret=77
12028 23:50:38.832895 ./lib/drmtest.c:880:
12029 23:50:38.836104 Test requirement: is_intel_device(fd)
12030 23:50:38.845889 No <8>[ 18.264899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
12031 23:50:38.846147 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
12033 23:50:38.849393 KMS driver or no outputs, pipes: 16, outputs: 0
12034 23:50:38.852282 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
12035 23:50:38.862873 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch<14>[ 18.286696] [IGT] kms_atomic: executing
12036 23:50:38.862959 64)
12037 23:50:38.869190 Using IGT_S<14>[ 18.291925] [IGT] kms_atomic: exiting, ret=77
12038 23:50:38.872477 RANDOM=1717544756 for randomisation
12039 23:50:38.882275 Opened device: /dev/dri/car<8>[ 18.302370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
12040 23:50:38.882361 d0
12041 23:50:38.882601 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
12043 23:50:38.889191 No KMS driver or no outputs, pipes: 16, outputs: 0
12044 23:50:38.892295 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
12045 23:50:38.902142 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92<14>[ 18.324663] [IGT] kms_atomic: executing
12046 23:50:38.902226 -cip22 aarch64)
12047 23:50:38.909044 <14>[ 18.329889] [IGT] kms_atomic: exiting, ret=77
12048 23:50:38.909128
12049 23:50:38.912121 Using IGT_SRANDOM=1717544756 for randomisation
12050 23:50:38.922048 Opened device: <8>[ 18.340196] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
12051 23:50:38.922131 /dev/dri/card0
12052 23:50:38.922368 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
12054 23:50:38.925277 No KMS driver or no outputs, pipes: 16, outputs: 0
12055 23:50:38.932268 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
12056 23:50:38.939024 IGT-Version: 1.28-ga44ebfe (aarch64) (L<14>[ 18.361834] [IGT] kms_atomic: executing
12057 23:50:38.945537 inux: 6.1.92-cip<14>[ 18.367572] [IGT] kms_atomic: exiting, ret=77
12058 23:50:38.945618 22 aarch64)
12059 23:50:38.948934 Using IGT_SRANDOM=1717544756 for randomisation
12060 23:50:38.959223 Ope<8>[ 18.377643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-plane-damage RESULT=skip>
12061 23:50:38.959507 Received signal: <TESTCASE> TEST_CASE_ID=atomic-plane-damage RESULT=skip
12063 23:50:38.962300 ned device: /dev/dri/card0
12064 23:50:38.965785 No K<8>[ 18.387808] <LAVA_SIGNAL_TESTSET STOP>
12065 23:50:38.966030 Received signal: <TESTSET> STOP
12066 23:50:38.966123 Closing test_set kms_atomic
12067 23:50:38.969166 MS driver or no outputs, pipes: 16, outputs: 0
12068 23:50:38.975414 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
12069 23:50:38.982420 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12070 23:50:38.988672 Using IGT_SRANDOM=1717544<8>[ 18.409971] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
12071 23:50:38.988969 Received signal: <TESTSET> START kms_flip_event_leak
12072 23:50:38.989087 Starting test_set kms_flip_event_leak
12073 23:50:38.991820 756 for randomisation
12074 23:50:38.995666 Opened device: /dev/dri/card0
12075 23:50:38.998819 No KMS driver or no outputs, pipes: 16, outputs: 0
12076 23:50:39.002302 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
12077 23:50:39.011701 IGT-Version: 1.28-ga44ebfe (aarch<14>[ 18.433846] [IGT] kms_flip_event_leak: executing
12078 23:50:39.018481 64) (Linux: 6.1.<14>[ 18.439335] [IGT] kms_flip_event_leak: exiting, ret=77
12079 23:50:39.018567 92-cip22 aarch64)
12080 23:50:39.028234 Using IGT_SRANDOM=1717544756 for randomisatio<8>[ 18.450710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12081 23:50:39.028347 n
12082 23:50:39.028616 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12084 23:50:39.035474 Opened device: /dev/dri/card0<8>[ 18.459381] <LAVA_SIGNAL_TESTSET STOP>
12085 23:50:39.035555
12086 23:50:39.035790 Received signal: <TESTSET> STOP
12087 23:50:39.035856 Closing test_set kms_flip_event_leak
12088 23:50:39.041814 No KMS driver or no outputs, pipes: 16, outputs: 0
12089 23:50:39.045166 [1mSubtest test-only: SKIP (0.000s)[0m
12090 23:50:39.051682 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12091 23:50:39.058486 Using IGT_SRANDOM=1717544756<8>[ 18.481074] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
12092 23:50:39.058729 Received signal: <TESTSET> START kms_prop_blob
12093 23:50:39.058797 Starting test_set kms_prop_blob
12094 23:50:39.061788 for randomisation
12095 23:50:39.061856 Opened device: /dev/dri/card0
12096 23:50:39.068069 No KMS driver or no outputs, pipes: 16, outputs: 0
12097 23:50:39.071934 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
12098 23:50:39.078168 IGT-V<14>[ 18.500337] [IGT] kms_prop_blob: executing
12099 23:50:39.084809 ersion: 1.28-ga4<14>[ 18.505422] [IGT] kms_prop_blob: starting subtest basic
12100 23:50:39.091425 4ebfe (aarch64) <14>[ 18.512147] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
12101 23:50:39.098370 (Linux: 6.1.92-c<14>[ 18.519963] [IGT] kms_prop_blob: exiting, ret=0
12102 23:50:39.098452 ip22 aarch64)
12103 23:50:39.104777 Using IGT_SRANDOM=1717544756 for randomisation
12104 23:50:39.111559 O<8>[ 18.530436] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
12105 23:50:39.111643 pened device: /dev/dri/card0
12106 23:50:39.111882 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
12108 23:50:39.118511 No KMS driver or no outputs, pipes: 16, outputs: 0
12109 23:50:39.121517 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
12110 23:50:39.127997 IGT-Version: 1.28-ga44ebf<14>[ 18.551660] [IGT] kms_prop_blob: executing
12111 23:50:39.134359 e (aarch64) (Lin<14>[ 18.556823] [IGT] kms_prop_blob: starting subtest blob-prop-core
12112 23:50:39.144792 ux: 6.1.92-cip22<14>[ 18.564347] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
12113 23:50:39.144958 aarch64)
12114 23:50:39.151357 Using<14>[ 18.572938] [IGT] kms_prop_blob: exiting, ret=0
12115 23:50:39.154666 IGT_SRANDOM=1717544757 for randomisation
12116 23:50:39.164803 Opened device: /dev/d<8>[ 18.583590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
12117 23:50:39.164882 ri/card0
12118 23:50:39.165161 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
12120 23:50:39.167684 No KMS driver or no outputs, pipes: 16, outputs: 0
12121 23:50:39.174414 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
12122 23:50:39.184284 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip<14>[ 18.605875] [IGT] kms_prop_blob: executing
12123 23:50:39.184416 22 aarch64)
12124 23:50:39.190820 Usi<14>[ 18.612065] [IGT] kms_prop_blob: starting subtest blob-prop-validate
12125 23:50:39.201039 ng IGT_SRANDOM=1<14>[ 18.619985] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
12126 23:50:39.207555 717544757 for ra<14>[ 18.628873] [IGT] kms_prop_blob: exiting, ret=0
12127 23:50:39.207699 ndomisation
12128 23:50:39.211439 Opened device: /dev/dri/card0
12129 23:50:39.221159 No KMS driver or no <8>[ 18.639566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
12130 23:50:39.221421 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12132 23:50:39.224309 outputs, pipes: 16, outputs: 0
12133 23:50:39.227264 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
12134 23:50:39.234147 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12135 23:50:39.237462 Using IG<14>[ 18.661615] [IGT] kms_prop_blob: executing
12136 23:50:39.247504 T_SRANDOM=171754<14>[ 18.666919] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12137 23:50:39.254104 4757 for randomi<14>[ 18.674868] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
12138 23:50:39.257501 sation
12139 23:50:39.260605 Opened d<14>[ 18.683700] [IGT] kms_prop_blob: exiting, ret=0
12140 23:50:39.263826 evice: /dev/dri/card0
12141 23:50:39.274178 No KMS driver or no outputs, pipes: 16, o<8>[ 18.694302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12142 23:50:39.274463 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12144 23:50:39.277275 utputs: 0
12145 23:50:39.280725 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
12146 23:50:39.287415 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12147 23:50:39.294130 Using IGT_SRANDOM=17175<14>[ 18.716753] [IGT] kms_prop_blob: executing
12148 23:50:39.300865 44757 for random<14>[ 18.721925] [IGT] kms_prop_blob: starting subtest blob-multiple
12149 23:50:39.300949 isation
12150 23:50:39.310635 Opened <14>[ 18.729453] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
12151 23:50:39.317135 device: /dev/dri<14>[ 18.737797] [IGT] kms_prop_blob: exiting, ret=0
12152 23:50:39.317216 /card0
12153 23:50:39.320139 No KMS driver or no outputs, pipes: 16, outputs: 0
12154 23:50:39.326778 [1m<8>[ 18.748368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12155 23:50:39.327050 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12157 23:50:39.341663 Subtest atomic-invalid-params: SKIP (0.000s)[0m
12158 23:50:39.341763 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12159 23:50:39.346507 Using IGT_SRANDOM=1717544757 for randomisa<14>[ 18.770034] [IGT] kms_prop_blob: executing
12160 23:50:39.346592 tion
12161 23:50:39.356820 Opened dev<14>[ 18.775326] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12162 23:50:39.363299 ice: /dev/dri/ca<14>[ 18.783369] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
12163 23:50:39.363390 rd0
12164 23:50:39.369761 No KMS driv<14>[ 18.792479] [IGT] kms_prop_blob: exiting, ret=0
12165 23:50:39.373375 er or no outputs, pipes: 16, outputs: 0
12166 23:50:39.383127 [1mSubtest atomic-plan<8>[ 18.802867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12167 23:50:39.383392 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12169 23:50:39.386351 e-damage: SKIP (0.000s)[0m
12170 23:50:39.393138 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12171 23:50:39.396682 Using IGT_SRANDOM=1717544757 for randomisation
12172 23:50:39.403165 Opened device: <14>[ 18.825426] [IGT] kms_prop_blob: executing
12173 23:50:39.403247 /dev/dri/card0
12174 23:50:39.409985 <14>[ 18.830720] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12175 23:50:39.419967 No KMS driver or<14>[ 18.838404] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
12176 23:50:39.426411 no outputs, pip<14>[ 18.847160] [IGT] kms_prop_blob: exiting, ret=0
12177 23:50:39.426492 es: 16, outputs: 0
12178 23:50:39.429451 [1mSubtest basic: SKIP (0.000s)[0m
12179 23:50:39.439860 IGT-Ve<8>[ 18.857698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12180 23:50:39.440137 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12182 23:50:39.442685 rsion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12183 23:50:39.446155 Using IGT_SRANDOM=1717544757 for randomisation
12184 23:50:39.449591 Opened device: /dev/dri/card0
12185 23:50:39.456202 Starting subtest: b<14>[ 18.879974] [IGT] kms_prop_blob: executing
12186 23:50:39.456298 asic
12187 23:50:39.466073 [1mSubtes<14>[ 18.885172] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12188 23:50:39.472528 t basic: SUCCESS<14>[ 18.893085] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
12189 23:50:39.476449 (0.000s)[0m
12190 23:50:39.479637 I<14>[ 18.902394] [IGT] kms_prop_blob: exiting, ret=0
12191 23:50:39.492910 GT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64<8>[ 18.912766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12192 23:50:39.493043 )
12193 23:50:39.493288 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12195 23:50:39.499600 Using IGT_SRANDOM=1717544757 for randomisation
12196 23:50:39.499684 Opened device: /dev/dri/card0
12197 23:50:39.502667 Starting subtest: blob-prop-core
12198 23:50:39.512329 [1mSubtest blob-prop-core: SUCCESS (0.000s)<14>[ 18.935380] [IGT] kms_prop_blob: executing
12199 23:50:39.512510 [0m
12200 23:50:39.519538 IGT-Versio<14>[ 18.940528] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12201 23:50:39.529411 n: 1.28-ga44ebfe<14>[ 18.948162] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
12202 23:50:39.535752 (aarch64) (Linu<14>[ 18.956916] [IGT] kms_prop_blob: exiting, ret=0
12203 23:50:39.538946 x: 6.1.92-cip22 aarch64)
12204 23:50:39.549143 Using IGT_SRANDOM=1717544757 for rando<8>[ 18.967590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12205 23:50:39.549228 misation
12206 23:50:39.549468 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12208 23:50:39.555402 Opened device: /dev/dr<8>[ 18.977483] <LAVA_SIGNAL_TESTSET STOP>
12209 23:50:39.555484 i/card0
12210 23:50:39.555719 Received signal: <TESTSET> STOP
12211 23:50:39.555785 Closing test_set kms_prop_blob
12212 23:50:39.559106 Starting subtest: blob-prop-validate
12213 23:50:39.562110 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12214 23:50:39.568807 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12215 23:50:39.575211 Using IGT_SRANDOM=17175<8>[ 18.999567] <LAVA_SIGNAL_TESTSET START kms_setmode>
12216 23:50:39.575466 Received signal: <TESTSET> START kms_setmode
12217 23:50:39.575535 Starting test_set kms_setmode
12218 23:50:39.579043 44757 for randomisation
12219 23:50:39.582111 Opened device: /dev/dri/card0
12220 23:50:39.585461 Starting subtest: blob-prop-lifetime
12221 23:50:39.588807 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12222 23:50:39.595296 IGT-Version:<14>[ 19.018143] [IGT] kms_setmode: executing
12223 23:50:39.602270 1.28-ga44ebfe (<14>[ 19.023388] [IGT] kms_setmode: starting subtest basic
12224 23:50:39.608814 aarch64) (Linux:<14>[ 19.029872] [IGT] kms_setmode: finished subtest basic, SKIP
12225 23:50:39.615713 6.1.92-cip22 aa<14>[ 19.037248] [IGT] kms_setmode: exiting, ret=77
12226 23:50:39.615796 rch64)
12227 23:50:39.618785 Using IGT_SRANDOM=1717544757 for randomisation
12228 23:50:39.628946 Opened d<8>[ 19.047825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12229 23:50:39.629030 evice: /dev/dri/card0
12230 23:50:39.629268 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12232 23:50:39.632255 Starting subtest: blob-multiple
12233 23:50:39.635058 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12234 23:50:39.641750 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12235 23:50:39.645521 Usi<14>[ 19.069342] [IGT] kms_setmode: executing
12236 23:50:39.655095 ng IGT_SRANDOM=1<14>[ 19.075440] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12237 23:50:39.665307 717544757 for ra<14>[ 19.083425] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
12238 23:50:39.665463 ndomisation
12239 23:50:39.671720 Ope<14>[ 19.092475] [IGT] kms_setmode: exiting, ret=77
12240 23:50:39.671919 ned device: /dev/dri/card0
12241 23:50:39.684946 Starting subtest: invalid-get-prop-a<8>[ 19.102875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12242 23:50:39.685160 ny
12243 23:50:39.685460 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12245 23:50:39.688174 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12246 23:50:39.694987 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12247 23:50:39.701872 Using IGT_SRANDOM=1717544757 for<14>[ 19.125895] [IGT] kms_setmode: executing
12248 23:50:39.704824 randomisation
12249 23:50:39.711823 <14>[ 19.130625] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12250 23:50:39.721347 Opened device: /<14>[ 19.138925] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
12251 23:50:39.721435 dev/dri/card0
12252 23:50:39.724480 S<14>[ 19.148003] [IGT] kms_setmode: exiting, ret=77
12253 23:50:39.727682 tarting subtest: invalid-get-prop
12254 23:50:39.737851 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12256 23:50:39.741837 [1mSubtest invalid-get-prop:<8>[ 19.158442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12257 23:50:39.741933 SUCCESS (0.000s)[0m
12258 23:50:39.747913 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12259 23:50:39.751277 Using IGT_SRANDOM=1717544757 for randomisation
12260 23:50:39.757848 Opened device: /dev/d<14>[ 19.181391] [IGT] kms_setmode: executing
12261 23:50:39.757931 ri/card0
12262 23:50:39.767761 Starti<14>[ 19.186411] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12263 23:50:39.774363 ng subtest: inva<14>[ 19.194963] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
12264 23:50:39.781147 lid-set-prop-any<14>[ 19.204306] [IGT] kms_setmode: exiting, ret=77
12265 23:50:39.781254
12266 23:50:39.787740 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12267 23:50:39.794348 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12269 23:50:39.797814 IGT-Ve<8>[ 19.214790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12270 23:50:39.801001 rsion: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12271 23:50:39.804388 Using IGT_SRANDOM=1717544757 for randomisation
12272 23:50:39.807426 Opened device: /dev/dri/card0
12273 23:50:39.814438 Starting subtest: i<14>[ 19.237803] [IGT] kms_setmode: executing
12274 23:50:39.817597 nvalid-set-prop
12275 23:50:39.824160 <14>[ 19.243138] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12276 23:50:39.824246
12277 23:50:39.830823 [1mSubtest inv<14>[ 19.250902] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
12278 23:50:39.837951 alid-set-prop: S<14>[ 19.259580] [IGT] kms_setmode: exiting, ret=77
12279 23:50:39.840865 UCCESS (0.000s)[0m
12280 23:50:39.850566 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux<8>[ 19.270105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12281 23:50:39.850856 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12283 23:50:39.853964 : 6.1.92-cip22 aarch64)
12284 23:50:39.857308 Using IGT_SRANDOM=1717544757 for randomisation
12285 23:50:39.861033 Opened device: /dev/dri/card0
12286 23:50:39.861135 Starting subtest: basic
12287 23:50:39.863721 No dynamic tests executed.
12288 23:50:39.867404 [1<14>[ 19.292534] [IGT] kms_setmode: executing
12289 23:50:39.877290 mSubtest basic: <14>[ 19.297729] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12290 23:50:39.887079 <14>[ 19.306639] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
12291 23:50:39.894002 SKIP (0.000s)[0<14>[ 19.315246] [IGT] kms_setmode: exiting, ret=77
12292 23:50:39.894124 m
12293 23:50:39.907500 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aar<8>[ 19.325963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12294 23:50:39.907613 ch64)
12295 23:50:39.907903 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12297 23:50:39.913769 Using IGT_SRANDOM=1717544<8>[ 19.338198] <LAVA_SIGNAL_TESTSET STOP>
12298 23:50:39.914072 Received signal: <TESTSET> STOP
12299 23:50:39.914185 Closing test_set kms_setmode
12300 23:50:39.917888 757 for randomisation
12301 23:50:39.920748 Opened device: /dev/dri/card0
12302 23:50:39.923727 Starting subtest: basic-clone-single-crtc
12303 23:50:39.923835 No dynamic tests executed.
12304 23:50:39.930348 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12305 23:50:39.940424 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 a<8>[ 19.363421] <LAVA_SIGNAL_TESTSET START kms_vblank>
12306 23:50:39.940505 arch64)
12307 23:50:39.940746 Received signal: <TESTSET> START kms_vblank
12308 23:50:39.940854 Starting test_set kms_vblank
12309 23:50:39.943871 Using IGT_SRANDOM=1717544757 for randomisation
12310 23:50:39.946972 Opened device: /dev/dri/card0
12311 23:50:39.950582 Starting subtest: invalid-clone-single-crtc
12312 23:50:39.953882 No dynamic tests executed.
12313 23:50:39.960572 [1mSubtest inv<14>[ 19.382447] [IGT] kms_vblank: executing
12314 23:50:39.967190 alid-clone-singl<14>[ 19.388586] [IGT] kms_vblank: exiting, ret=77
12315 23:50:39.967309 e-crtc: SKIP (0.000s)[0m
12316 23:50:39.976676 IGT-Version: 1.28-ga44ebfe (aarch64) <8>[ 19.398785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12317 23:50:39.976957 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12319 23:50:39.980248 (Linux: 6.1.92-cip22 aarch64)
12320 23:50:39.983700 Using IGT_SRANDOM=1717544757 for randomisation
12321 23:50:39.986908 Opened device: /dev/dri/card0
12322 23:50:39.993366 Starting subtest: invalid-clone-exclusive-crtc
12323 23:50:39.997061 No<14>[ 19.419321] [IGT] kms_vblank: executing
12324 23:50:40.003605 dynamic tests e<14>[ 19.424965] [IGT] kms_vblank: exiting, ret=77
12325 23:50:40.003686 xecuted.
12326 23:50:40.013732 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s<8>[ 19.435377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12327 23:50:40.014017 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12329 23:50:40.016980 )[0m
12330 23:50:40.020292 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12331 23:50:40.027168 Using IGT_SRANDOM=1717544758 for randomisation
12332 23:50:40.027268 Opened device: /dev/dri/card0
12333 23:50:40.033476 Starti<14>[ 19.456579] [IGT] kms_vblank: executing
12334 23:50:40.040259 ng subtest: clon<14>[ 19.461369] [IGT] kms_vblank: exiting, ret=77
12335 23:50:40.040422 e-exclusive-crtc
12336 23:50:40.043602 No dynamic tests executed.
12337 23:50:40.050104 [1mSubtest clone-<8>[ 19.472537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=accuracy-idle RESULT=skip>
12338 23:50:40.050363 Received signal: <TESTCASE> TEST_CASE_ID=accuracy-idle RESULT=skip
12340 23:50:40.053434 exclusive-crtc: SKIP (0.000s)[0m
12341 23:50:40.059729 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12342 23:50:40.063415 Using IGT_SRANDOM=1717544758 for randomisation
12343 23:50:40.069807 Opened de<14>[ 19.493235] [IGT] kms_vblank: executing
12344 23:50:40.076647 vice: /dev/dri/c<14>[ 19.498264] [IGT] kms_vblank: exiting, ret=77
12345 23:50:40.076799 ard0
12346 23:50:40.079429 Starting subtest: invalid-clone-single-crtc-stealing
12347 23:50:40.089405 No dynamic tests exe<8>[ 19.509533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle RESULT=skip>
12348 23:50:40.089520 cuted.
12349 23:50:40.089827 Received signal: <TESTCASE> TEST_CASE_ID=query-idle RESULT=skip
12351 23:50:40.096115 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12352 23:50:40.103395 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12353 23:50:40.105885 Using IGT_SRANDOM<14>[ 19.531159] [IGT] kms_vblank: executing
12354 23:50:40.113043 =1717544758 for <14>[ 19.536357] [IGT] kms_vblank: exiting, ret=77
12355 23:50:40.116291 randomisation
12356 23:50:40.119687 Opened device: /dev/dri/card0
12357 23:50:40.126163 No KMS driver or n<8>[ 19.547239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-idle-hang RESULT=skip>
12358 23:50:40.126450 Received signal: <TESTCASE> TEST_CASE_ID=query-idle-hang RESULT=skip
12360 23:50:40.129572 o outputs, pipes: 16, outputs: 0
12361 23:50:40.132775 [1mSubtest invalid: SKIP (0.000s)[0m
12362 23:50:40.139402 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12363 23:50:40.145691 Using IGT_SRANDOM=<14>[ 19.568538] [IGT] kms_vblank: executing
12364 23:50:40.149433 1717544758 for r<14>[ 19.573346] [IGT] kms_vblank: exiting, ret=77
12365 23:50:40.152670 andomisation
12366 23:50:40.155614 Opened device: /dev/dri/card0
12367 23:50:40.165597 No KMS driver or no outputs, pipes:<8>[ 19.585659] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked RESULT=skip>
12368 23:50:40.165686 16, outputs: 0
12369 23:50:40.165946 Received signal: <TESTCASE> TEST_CASE_ID=query-forked RESULT=skip
12371 23:50:40.169510 [1mSubtest crtc-id: SKIP (0.000s)[0m
12372 23:50:40.176138 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12373 23:50:40.182564 Using IGT_SRANDOM=1717544758 for ra<14>[ 19.606996] [IGT] kms_vblank: executing
12374 23:50:40.185883 ndomisation
12375 23:50:40.189054 Ope<14>[ 19.611791] [IGT] kms_vblank: exiting, ret=77
12376 23:50:40.192218 ned device: /dev/dri/card0
12377 23:50:40.202676 No KMS driver or no outputs, pipes: <8>[ 19.622754] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-hang RESULT=skip>
12378 23:50:40.202757 16, outputs: 0
12379 23:50:40.203001 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-hang RESULT=skip
12381 23:50:40.208742 [1mSubtest accuracy-idle: SKIP (0.000s)[0m
12382 23:50:40.212314 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12383 23:50:40.219084 Using IGT_SRANDOM=1717544758 f<14>[ 19.644205] [IGT] kms_vblank: executing
12384 23:50:40.225578 or randomisation<14>[ 19.648985] [IGT] kms_vblank: exiting, ret=77
12385 23:50:40.225698
12386 23:50:40.229369 Opened device: /dev/dri/card0
12387 23:50:40.239266 No KMS driver or no outputs, pipes: 16, outputs<8>[ 19.660881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy RESULT=skip>
12388 23:50:40.239526 Received signal: <TESTCASE> TEST_CASE_ID=query-busy RESULT=skip
12390 23:50:40.242616 : 0
12391 23:50:40.245671 [1mSubtest query-idle: SKIP (0.000s)[0m
12392 23:50:40.252267 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12393 23:50:40.255384 Using IGT_SRANDOM=1717544758 for randomisation
12394 23:50:40.262126 Opened device: /dev/dri/card<14>[ 19.684508] [IGT] kms_vblank: executing
12395 23:50:40.262208 0
12396 23:50:40.268655 No KMS driver<14>[ 19.689928] [IGT] kms_vblank: exiting, ret=77
12397 23:50:40.272007 or no outputs, pipes: 16, outputs: 0
12398 23:50:40.282082 [1mSubtest query-idle-hang: SKIP (0.000s<8>[ 19.701899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-busy-hang RESULT=skip>
12399 23:50:40.282165 )[0m
12400 23:50:40.282406 Received signal: <TESTCASE> TEST_CASE_ID=query-busy-hang RESULT=skip
12402 23:50:40.288634 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12403 23:50:40.292073 Using IGT_SRANDOM=1717544758 for randomisation
12404 23:50:40.294994 Opened device: /dev/dri/card0
12405 23:50:40.298579 No KMS<14>[ 19.723517] [IGT] kms_vblank: executing
12406 23:50:40.305504 driver or no ou<14>[ 19.728509] [IGT] kms_vblank: exiting, ret=77
12407 23:50:40.308734 tputs, pipes: 16, outputs: 0
12408 23:50:40.318431 [1mSubtest query-forked: SKIP (0.<8>[ 19.739441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy RESULT=skip>
12409 23:50:40.318540 000s)[0m
12410 23:50:40.318822 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy RESULT=skip
12412 23:50:40.324919 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12413 23:50:40.328628 Using IGT_SRANDOM=1717544758 for randomisation
12414 23:50:40.331578 Opened device: /dev/dri/card0
12415 23:50:40.338419 No<14>[ 19.760705] [IGT] kms_vblank: executing
12416 23:50:40.341902 KMS driver or n<14>[ 19.765674] [IGT] kms_vblank: exiting, ret=77
12417 23:50:40.345055 o outputs, pipes: 16, outputs: 0
12418 23:50:40.354978 [1mSubtest query-forked-hang:<8>[ 19.776827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=query-forked-busy-hang RESULT=skip>
12419 23:50:40.355238 Received signal: <TESTCASE> TEST_CASE_ID=query-forked-busy-hang RESULT=skip
12421 23:50:40.358151 SKIP (0.000s)[0m
12422 23:50:40.364656 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12423 23:50:40.368025 Using IGT_SRANDOM=1717544758 for randomisation
12424 23:50:40.371389 Opened device: /dev/dri/card0
12425 23:50:40.378311 No KMS driver or no outpu<14>[ 19.801202] [IGT] kms_vblank: executing
12426 23:50:40.384865 ts, pipes: 16, o<14>[ 19.806108] [IGT] kms_vblank: exiting, ret=77
12427 23:50:40.384950 utputs: 0
12428 23:50:40.388483 [1mSubtest query-busy: SKIP (0.000s)[0m
12429 23:50:40.398362 IGT-Version: 1.28-ga44ebfe<8>[ 19.817398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle RESULT=skip>
12430 23:50:40.398620 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle RESULT=skip
12432 23:50:40.401350 (aarch64) (Linux: 6.1.92-cip22 aarch64)
12433 23:50:40.404956 Using IGT_SRANDOM=1717544758 for randomisation
12434 23:50:40.408009 Opened device: /dev/dri/card0
12435 23:50:40.415134 No KMS driver or no outputs, pipes: 16,<14>[ 19.838826] [IGT] kms_vblank: executing
12436 23:50:40.418317 outputs: 0
12437 23:50:40.421321 [1<14>[ 19.844066] [IGT] kms_vblank: exiting, ret=77
12438 23:50:40.424999 mSubtest query-busy-hang: SKIP (0.000s)[0m
12439 23:50:40.434925 IGT-Version: 1.28-ga44ebfe (aarch64<8>[ 19.855398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-idle-hang RESULT=skip>
12440 23:50:40.435195 Received signal: <TESTCASE> TEST_CASE_ID=wait-idle-hang RESULT=skip
12442 23:50:40.438240 ) (Linux: 6.1.92-cip22 aarch64)
12443 23:50:40.441267 Using IGT_SRANDOM=1717544758 for randomisation
12444 23:50:40.444793 Opened device: /dev/dri/card0
12445 23:50:40.455241 No KMS driver or no outputs, pipes: 16, outputs:<14>[ 19.877369] [IGT] kms_vblank: executing
12446 23:50:40.455355 0
12447 23:50:40.461988 [1mSubtest <14>[ 19.882560] [IGT] kms_vblank: exiting, ret=77
12448 23:50:40.464903 query-forked-busy: SKIP (0.000s)[0m
12449 23:50:40.471996 IGT-Version: 1.28-ga44ebfe<8>[ 19.893623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked RESULT=skip>
12450 23:50:40.472255 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked RESULT=skip
12452 23:50:40.475224 (aarch64) (Linux: 6.1.92-cip22 aarch64)
12453 23:50:40.481735 Using IGT_SRANDOM=1717544758 for randomisation
12454 23:50:40.481816 Opened device: /dev/dri/card0
12455 23:50:40.488062 No KMS driver or no outputs, pipes: 16, outputs: 0
12456 23:50:40.494758 [1mSubtest query-f<14>[ 19.917241] [IGT] kms_vblank: executing
12457 23:50:40.498389 orked-busy-hang:<14>[ 19.922204] [IGT] kms_vblank: exiting, ret=77
12458 23:50:40.501618 SKIP (0.000s)[0m
12459 23:50:40.514812 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aa<8>[ 19.933407] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-hang RESULT=skip>
12460 23:50:40.514916 rch64)
12461 23:50:40.515162 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-hang RESULT=skip
12463 23:50:40.518165 Using IGT_SRANDOM=1717544758 for randomisation
12464 23:50:40.521805 Opened device: /dev/dri/card0
12465 23:50:40.524355 No KMS driver or no outputs, pipes: 16, outputs: 0
12466 23:50:40.531526 [1mSubtest wait-idle<14>[ 19.955437] [IGT] kms_vblank: executing
12467 23:50:40.537867 : SKIP (0.000s)<14>[ 19.960579] [IGT] kms_vblank: exiting, ret=77
12468 23:50:40.537946 [0m
12469 23:50:40.551114 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 a<8>[ 19.971752] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy RESULT=skip>
12470 23:50:40.551207 arch64)
12471 23:50:40.551450 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy RESULT=skip
12473 23:50:40.554289 Using IGT_SRANDOM=1717544758 for randomisation
12474 23:50:40.557377 Opened device: /dev/dri/card0
12475 23:50:40.560773 No KMS driver or no outputs, pipes: 16, outputs: 0
12476 23:50:40.567795 [1mSubtest wait-idl<14>[ 19.992159] [IGT] kms_vblank: executing
12477 23:50:40.573953 e-hang: SKIP (0.<14>[ 19.997249] [IGT] kms_vblank: exiting, ret=77
12478 23:50:40.574033 000s)[0m
12479 23:50:40.587513 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-c<8>[ 20.008297] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-busy-hang RESULT=skip>
12480 23:50:40.587603 ip22 aarch64)
12481 23:50:40.587848 Received signal: <TESTCASE> TEST_CASE_ID=wait-busy-hang RESULT=skip
12483 23:50:40.594164 Using IGT_SRANDOM=1717544758 for randomisation
12484 23:50:40.594271 Opened device: /dev/dri/card0
12485 23:50:40.600904 No KMS driver or no outputs, pipes: 16, outputs: 0
12486 23:50:40.603869 [1mSubtest wa<14>[ 20.029379] [IGT] kms_vblank: executing
12487 23:50:40.610791 it-forked: SKIP <14>[ 20.034179] [IGT] kms_vblank: exiting, ret=77
12488 23:50:40.614189 (0.000s)[0m
12489 23:50:40.623901 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.9<8>[ 20.045303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy RESULT=skip>
12490 23:50:40.624161 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy RESULT=skip
12492 23:50:40.627188 2-cip22 aarch64)
12493 23:50:40.630699 Using IGT_SRANDOM=1717544758 for randomisation
12494 23:50:40.634143 Opened device: /dev/dri/card0
12495 23:50:40.636964 No KMS driver or no outputs, pipes: 16, outputs: 0
12496 23:50:40.643791 [1mSubtest<14>[ 20.066066] [IGT] kms_vblank: executing
12497 23:50:40.646937 wait-forked-han<14>[ 20.071372] [IGT] kms_vblank: exiting, ret=77
12498 23:50:40.650677 g: SKIP (0.000s)[0m
12499 23:50:40.663531 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 <8>[ 20.082582] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=wait-forked-busy-hang RESULT=skip>
12500 23:50:40.663655 aarch64)
12501 23:50:40.663924 Received signal: <TESTCASE> TEST_CASE_ID=wait-forked-busy-hang RESULT=skip
12503 23:50:40.667476 Using IGT_SRANDOM=1717544758 for randomisation
12504 23:50:40.670398 Opened device: /dev/dri/card0
12505 23:50:40.676982 No KMS driver or no outputs, pipes: 16, outputs: 0
12506 23:50:40.680707 [1mSubtest wait-bu<14>[ 20.105591] [IGT] kms_vblank: executing
12507 23:50:40.687137 sy: SKIP (0.000s<14>[ 20.110503] [IGT] kms_vblank: exiting, ret=77
12508 23:50:40.687233 )[0m
12509 23:50:40.700204 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22<8>[ 20.121380] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle RESULT=skip>
12510 23:50:40.700486 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle RESULT=skip
12512 23:50:40.703516 aarch64)
12513 23:50:40.707212 Using IGT_SRANDOM=1717544758 for randomisation
12514 23:50:40.710333 Opened device: /dev/dri/card0
12515 23:50:40.713892 No KMS driver or no outputs, pipes: 16, outputs: 0
12516 23:50:40.716799 [1mSubtest wait-busy-hang: SKIP (0.000s)[0m
12517 23:50:40.723776 IGT<14>[ 20.145617] [IGT] kms_vblank: executing
12518 23:50:40.726766 -Version: 1.28-g<14>[ 20.150818] [IGT] kms_vblank: exiting, ret=77
12519 23:50:40.733483 a44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12520 23:50:40.740196 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip
12522 23:50:40.743549 Using IGT_SRAND<8>[ 20.161792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-idle-hang RESULT=skip>
12523 23:50:40.743654 OM=1717544758 for randomisation
12524 23:50:40.747091 Opened device: /dev/dri/card0
12525 23:50:40.753154 No KMS driver or no outputs, pipes: 16, outputs: 0
12526 23:50:40.756884 [1mSubtest wait-forked-busy: SKIP (0.000s)[0m
12527 23:50:40.763632 IGT-Version: 1.28-ga44ebfe <14>[ 20.186406] [IGT] kms_vblank: executing
12528 23:50:40.770084 (aarch64) (Linux<14>[ 20.191453] [IGT] kms_vblank: exiting, ret=77
12529 23:50:40.770166 : 6.1.92-cip22 aarch64)
12530 23:50:40.783719 Using IGT_SRANDOM=1717544758 for random<8>[ 20.202530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip>
12531 23:50:40.783802 isation
12532 23:50:40.784044 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-rpm RESULT=skip
12534 23:50:40.786529 Opened device: /dev/dri/card0
12535 23:50:40.790155 No KMS driver or no outputs, pipes: 16, outputs: 0
12536 23:50:40.796296 [1mSubtest wait-forked-busy-hang: SKIP (0.000s)[0m
12537 23:50:40.803213 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6<14>[ 20.226073] [IGT] kms_vblank: executing
12538 23:50:40.810218 .1.92-cip22 aarc<14>[ 20.232108] [IGT] kms_vblank: exiting, ret=77
12539 23:50:40.810299 h64)
12540 23:50:40.813374 Using IGT_SRANDOM=1717544758 for randomisation
12541 23:50:40.823254 Opened device: /dev/dri/ca<8>[ 20.243338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip>
12542 23:50:40.823567 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-dpms-suspend RESULT=skip
12544 23:50:40.826332 rd0
12545 23:50:40.830839 No KMS driver or no outputs, pipes: 16, outputs: 0
12546 23:50:40.833357 [1mSubtest ts-continuation-idle: SKIP (0.000s)[0m
12547 23:50:40.843372 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.9<14>[ 20.266833] [IGT] kms_vblank: executing
12548 23:50:40.849844 2-cip22 aarch64)<14>[ 20.271729] [IGT] kms_vblank: exiting, ret=77
12549 23:50:40.849961
12550 23:50:40.853402 Using IGT_SRANDOM=1717544758 for randomisation
12551 23:50:40.863091 Opened device:<8>[ 20.282737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-suspend RESULT=skip>
12552 23:50:40.863198 /dev/dri/card0
12553 23:50:40.863471 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-suspend RESULT=skip
12555 23:50:40.869717 No KMS driver or no outputs, pipes: 16, outputs: 0
12556 23:50:40.873339 [1mSubtest ts-continuation-idle-hang: SKIP (0.000s)[0m
12557 23:50:40.882958 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64<14>[ 20.306944] [IGT] kms_vblank: executing
12558 23:50:40.883043 )
12559 23:50:40.889565 Using IGT_SRA<14>[ 20.312304] [IGT] kms_vblank: exiting, ret=77
12560 23:50:40.893228 NDOM=1717544758 for randomisation
12561 23:50:40.896263 Opened device: /dev/dri/card0
12562 23:50:40.902795 No KMS driver <8>[ 20.323547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset RESULT=skip>
12563 23:50:40.903051 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset RESULT=skip
12565 23:50:40.906404 or no outputs, pipes: 16, outputs: 0
12566 23:50:40.912881 [1mSubtest ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12567 23:50:40.922773 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64<14>[ 20.346403] [IGT] kms_vblank: executing
12568 23:50:40.922888 )
12569 23:50:40.929208 Using IGT_SRA<14>[ 20.351512] [IGT] kms_vblank: exiting, ret=77
12570 23:50:40.933018 NDOM=1717544759 for randomisation
12571 23:50:40.942799 Opened device: /dev/dri/card0<8>[ 20.362673] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip>
12572 23:50:40.942911
12573 23:50:40.943197 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-hang RESULT=skip
12575 23:50:40.946282 No KMS driver or no outputs, pipes: 16, outputs: 0
12576 23:50:40.952587 [1mSubtest ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12577 23:50:40.959552 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12578 23:50:40.962531 Using IGT<14>[ 20.387011] [IGT] kms_vblank: executing
12579 23:50:40.969331 _SRANDOM=1717544<14>[ 20.392562] [IGT] kms_vblank: exiting, ret=77
12580 23:50:40.972883 759 for randomisation
12581 23:50:40.975808 Opened device: /dev/dri/card0
12582 23:50:40.986109 No KMS driver or no output<8>[ 20.403753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip>
12583 23:50:40.986220 s, pipes: 16, outputs: 0
12584 23:50:40.986496 Received signal: <TESTCASE> TEST_CASE_ID=ts-continuation-modeset-rpm RESULT=skip
12586 23:50:40.992370 [1mSu<8>[ 20.415169] <LAVA_SIGNAL_TESTSET STOP>
12587 23:50:40.992637 Received signal: <TESTSET> STOP
12588 23:50:40.992737 Closing test_set kms_vblank
12589 23:50:40.998856 btest ts-continu<8>[ 20.421016] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 14172959_1.5.2.3.1>
12590 23:50:40.999129 Received signal: <ENDRUN> 0_igt-kms-mediatek 14172959_1.5.2.3.1
12591 23:50:40.999234 Ending use of test pattern.
12592 23:50:40.999328 Ending test lava.0_igt-kms-mediatek (14172959_1.5.2.3.1), duration 6.17
12594 23:50:41.002834 ation-suspend: SKIP (0.000s)[0m
12595 23:50:41.008988 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12596 23:50:41.012525 Using IGT_SRANDOM=1717544759 for randomisation
12597 23:50:41.015385 Opened device: /dev/dri/card0
12598 23:50:41.018827 No KMS driver or no outputs, pipes: 16, outputs: 0
12599 23:50:41.025511 [1mSubtest ts-continuation-modeset: SKIP (0.000s)[0m
12600 23:50:41.032178 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12601 23:50:41.035376 Using IGT_SRANDOM=1717544759 for randomisation
12602 23:50:41.038629 Opened device: /dev/dri/card0
12603 23:50:41.041916 No KMS driver or no outputs, pipes: 16, outputs: 0
12604 23:50:41.048991 [1mSubtest ts-continuation-modeset-hang: SKIP (0.000s)[0m
12605 23:50:41.052375 IGT-Version: 1.28-ga44ebfe (aarch64) (Linux: 6.1.92-cip22 aarch64)
12606 23:50:41.058873 Using IGT_SRANDOM=1717544759 for randomisation
12607 23:50:41.062217 Opened device: /dev/dri/card0
12608 23:50:41.065498 No KMS driver or no outputs, pipes: 16, outputs: 0
12609 23:50:41.068863 [1mSubtest ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12610 23:50:41.072233 + set +x
12611 23:50:41.072317 <LAVA_TEST_RUNNER EXIT>
12612 23:50:41.072568 ok: lava_test_shell seems to have completed
12613 23:50:41.074076 accuracy-idle:
result: skip
set: kms_vblank
addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic-plane-damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
query-busy:
result: skip
set: kms_vblank
query-busy-hang:
result: skip
set: kms_vblank
query-forked:
result: skip
set: kms_vblank
query-forked-busy:
result: skip
set: kms_vblank
query-forked-busy-hang:
result: skip
set: kms_vblank
query-forked-hang:
result: skip
set: kms_vblank
query-idle:
result: skip
set: kms_vblank
query-idle-hang:
result: skip
set: kms_vblank
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
ts-continuation-idle:
result: skip
set: kms_vblank
ts-continuation-idle-hang:
result: skip
set: kms_vblank
ts-continuation-modeset:
result: skip
set: kms_vblank
ts-continuation-modeset-hang:
result: skip
set: kms_vblank
ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
ts-continuation-suspend:
result: skip
set: kms_vblank
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
wait-busy:
result: skip
set: kms_vblank
wait-busy-hang:
result: skip
set: kms_vblank
wait-forked:
result: skip
set: kms_vblank
wait-forked-busy:
result: skip
set: kms_vblank
wait-forked-busy-hang:
result: skip
set: kms_vblank
wait-forked-hang:
result: skip
set: kms_vblank
wait-idle:
result: skip
set: kms_vblank
wait-idle-hang:
result: skip
set: kms_vblank
12614 23:50:41.074218 end: 3.1 lava-test-shell (duration 00:00:07) [common]
12615 23:50:41.074303 end: 3 lava-test-retry (duration 00:00:07) [common]
12616 23:50:41.074388 start: 4 finalize (timeout 00:07:53) [common]
12617 23:50:41.074473 start: 4.1 power-off (timeout 00:00:30) [common]
12618 23:50:41.074617 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
12619 23:50:41.151552 >> Command sent successfully.
12620 23:50:41.154242 Returned 0 in 0 seconds
12621 23:50:41.254710 end: 4.1 power-off (duration 00:00:00) [common]
12623 23:50:41.255051 start: 4.2 read-feedback (timeout 00:07:53) [common]
12624 23:50:41.255364 Listened to connection for namespace 'common' for up to 1s
12625 23:50:42.256283 Finalising connection for namespace 'common'
12626 23:50:42.256487 Disconnecting from shell: Finalise
12627 23:50:42.256563 / #
12628 23:50:42.356894 end: 4.2 read-feedback (duration 00:00:01) [common]
12629 23:50:42.357081 end: 4 finalize (duration 00:00:01) [common]
12630 23:50:42.357202 Cleaning after the job
12631 23:50:42.357312 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/ramdisk
12632 23:50:42.363938 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/kernel
12633 23:50:42.379225 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/dtb
12634 23:50:42.379449 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172959/tftp-deploy-tcbr0s4c/modules
12635 23:50:42.385090 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14172959
12636 23:50:42.496505 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14172959
12637 23:50:42.496682 Job finished correctly