Boot log: mt8183-kukui-jacuzzi-juniper-sku16
- Errors: 0
- Kernel Errors: 50
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 89
1 23:44:30.789577 lava-dispatcher, installed at version: 2024.03
2 23:44:30.789812 start: 0 validate
3 23:44:30.789960 Start time: 2024-06-04 23:44:30.789952+00:00 (UTC)
4 23:44:30.790097 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:44:30.790251 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:44:31.046071 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:44:31.046262 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:44:31.303680 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:44:31.303870 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8183-kukui-jacuzzi-juniper-sku16.dtb exists
10 23:44:31.560781 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:44:31.560961 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:44:31.818694 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:44:31.818873 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:44:32.077804 validate duration: 1.29
16 23:44:32.078109 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:44:32.078218 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:44:32.078314 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:44:32.078450 Not decompressing ramdisk as can be used compressed.
20 23:44:32.078544 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:44:32.078616 saving as /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/ramdisk/initrd.cpio.gz
22 23:44:32.078688 total size: 5628169 (5 MB)
23 23:44:32.079908 progress 0 % (0 MB)
24 23:44:32.081747 progress 5 % (0 MB)
25 23:44:32.083582 progress 10 % (0 MB)
26 23:44:32.085141 progress 15 % (0 MB)
27 23:44:32.086875 progress 20 % (1 MB)
28 23:44:32.088545 progress 25 % (1 MB)
29 23:44:32.090291 progress 30 % (1 MB)
30 23:44:32.092029 progress 35 % (1 MB)
31 23:44:32.093556 progress 40 % (2 MB)
32 23:44:32.095384 progress 45 % (2 MB)
33 23:44:32.096930 progress 50 % (2 MB)
34 23:44:32.098634 progress 55 % (2 MB)
35 23:44:32.100407 progress 60 % (3 MB)
36 23:44:32.101930 progress 65 % (3 MB)
37 23:44:32.103674 progress 70 % (3 MB)
38 23:44:32.105249 progress 75 % (4 MB)
39 23:44:32.107187 progress 80 % (4 MB)
40 23:44:32.108742 progress 85 % (4 MB)
41 23:44:32.110519 progress 90 % (4 MB)
42 23:44:32.112257 progress 95 % (5 MB)
43 23:44:32.113798 progress 100 % (5 MB)
44 23:44:32.114031 5 MB downloaded in 0.04 s (151.87 MB/s)
45 23:44:32.114203 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:44:32.114477 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:44:32.114572 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:44:32.114683 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:44:32.114901 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:44:32.115005 saving as /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/kernel/Image
52 23:44:32.115077 total size: 54682112 (52 MB)
53 23:44:32.115147 No compression specified
54 23:44:32.116408 progress 0 % (0 MB)
55 23:44:32.132179 progress 5 % (2 MB)
56 23:44:32.148132 progress 10 % (5 MB)
57 23:44:32.164030 progress 15 % (7 MB)
58 23:44:32.179556 progress 20 % (10 MB)
59 23:44:32.195218 progress 25 % (13 MB)
60 23:44:32.210710 progress 30 % (15 MB)
61 23:44:32.226366 progress 35 % (18 MB)
62 23:44:32.241959 progress 40 % (20 MB)
63 23:44:32.257532 progress 45 % (23 MB)
64 23:44:32.273260 progress 50 % (26 MB)
65 23:44:32.288775 progress 55 % (28 MB)
66 23:44:32.306168 progress 60 % (31 MB)
67 23:44:32.330387 progress 65 % (33 MB)
68 23:44:32.346165 progress 70 % (36 MB)
69 23:44:32.361415 progress 75 % (39 MB)
70 23:44:32.376852 progress 80 % (41 MB)
71 23:44:32.392084 progress 85 % (44 MB)
72 23:44:32.407298 progress 90 % (46 MB)
73 23:44:32.422520 progress 95 % (49 MB)
74 23:44:32.437458 progress 100 % (52 MB)
75 23:44:32.437750 52 MB downloaded in 0.32 s (161.62 MB/s)
76 23:44:32.437918 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:44:32.438173 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:44:32.438269 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:44:32.438364 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:44:32.438514 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8183-kukui-jacuzzi-juniper-sku16.dtb
82 23:44:32.438590 saving as /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
83 23:44:32.438657 total size: 57695 (0 MB)
84 23:44:32.438726 No compression specified
85 23:44:32.439966 progress 56 % (0 MB)
86 23:44:32.440283 progress 100 % (0 MB)
87 23:44:32.440508 0 MB downloaded in 0.00 s (29.78 MB/s)
88 23:44:32.440645 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:44:32.440897 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:44:32.440992 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:44:32.441083 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:44:32.441209 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:44:32.441283 saving as /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/nfsrootfs/full.rootfs.tar
95 23:44:32.441350 total size: 120894716 (115 MB)
96 23:44:32.441418 Using unxz to decompress xz
97 23:44:32.445786 progress 0 % (0 MB)
98 23:44:32.842931 progress 5 % (5 MB)
99 23:44:33.252659 progress 10 % (11 MB)
100 23:44:33.654017 progress 15 % (17 MB)
101 23:44:34.026478 progress 20 % (23 MB)
102 23:44:34.361969 progress 25 % (28 MB)
103 23:44:34.755439 progress 30 % (34 MB)
104 23:44:35.126970 progress 35 % (40 MB)
105 23:44:35.309321 progress 40 % (46 MB)
106 23:44:35.505766 progress 45 % (51 MB)
107 23:44:35.848608 progress 50 % (57 MB)
108 23:44:36.260174 progress 55 % (63 MB)
109 23:44:36.650398 progress 60 % (69 MB)
110 23:44:37.029464 progress 65 % (74 MB)
111 23:44:37.418203 progress 70 % (80 MB)
112 23:44:37.849503 progress 75 % (86 MB)
113 23:44:38.266016 progress 80 % (92 MB)
114 23:44:38.673920 progress 85 % (98 MB)
115 23:44:39.096447 progress 90 % (103 MB)
116 23:44:39.483321 progress 95 % (109 MB)
117 23:44:39.897715 progress 100 % (115 MB)
118 23:44:39.903926 115 MB downloaded in 7.46 s (15.45 MB/s)
119 23:44:39.904228 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:44:39.904536 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:44:39.904648 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:44:39.904770 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:44:39.904937 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:44:39.905015 saving as /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/modules/modules.tar
126 23:44:39.905082 total size: 8603924 (8 MB)
127 23:44:39.905154 Using unxz to decompress xz
128 23:44:39.910000 progress 0 % (0 MB)
129 23:44:39.933237 progress 5 % (0 MB)
130 23:44:39.961014 progress 10 % (0 MB)
131 23:44:39.990463 progress 15 % (1 MB)
132 23:44:40.019979 progress 20 % (1 MB)
133 23:44:40.049489 progress 25 % (2 MB)
134 23:44:40.078229 progress 30 % (2 MB)
135 23:44:40.105946 progress 35 % (2 MB)
136 23:44:40.135945 progress 40 % (3 MB)
137 23:44:40.164642 progress 45 % (3 MB)
138 23:44:40.192728 progress 50 % (4 MB)
139 23:44:40.221996 progress 55 % (4 MB)
140 23:44:40.250513 progress 60 % (4 MB)
141 23:44:40.278446 progress 65 % (5 MB)
142 23:44:40.309321 progress 70 % (5 MB)
143 23:44:40.338881 progress 75 % (6 MB)
144 23:44:40.369534 progress 80 % (6 MB)
145 23:44:40.397469 progress 85 % (7 MB)
146 23:44:40.425489 progress 90 % (7 MB)
147 23:44:40.459391 progress 95 % (7 MB)
148 23:44:40.491760 progress 100 % (8 MB)
149 23:44:40.498080 8 MB downloaded in 0.59 s (13.84 MB/s)
150 23:44:40.498417 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:44:40.498863 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:44:40.498969 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 23:44:40.499073 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 23:44:44.402111 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14172940/extract-nfsrootfs-kqrq6156
156 23:44:44.402313 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:44:44.402434 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:44:44.402660 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t
159 23:44:44.402842 makedir: /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin
160 23:44:44.402965 makedir: /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/tests
161 23:44:44.403070 makedir: /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/results
162 23:44:44.403178 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-add-keys
163 23:44:44.403333 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-add-sources
164 23:44:44.403534 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-background-process-start
165 23:44:44.403710 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-background-process-stop
166 23:44:44.403847 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-common-functions
167 23:44:44.403987 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-echo-ipv4
168 23:44:44.404122 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-install-packages
169 23:44:44.404259 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-installed-packages
170 23:44:44.404394 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-os-build
171 23:44:44.404528 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-probe-channel
172 23:44:44.404668 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-probe-ip
173 23:44:44.404803 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-target-ip
174 23:44:44.404941 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-target-mac
175 23:44:44.405074 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-target-storage
176 23:44:44.405209 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-test-case
177 23:44:44.405347 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-test-event
178 23:44:44.405479 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-test-feedback
179 23:44:44.405612 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-test-raise
180 23:44:44.405744 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-test-reference
181 23:44:44.405882 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-test-runner
182 23:44:44.406016 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-test-set
183 23:44:44.406151 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-test-shell
184 23:44:44.406294 Updating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-add-keys (debian)
185 23:44:44.431089 Updating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-add-sources (debian)
186 23:44:44.431297 Updating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-install-packages (debian)
187 23:44:44.431468 Updating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-installed-packages (debian)
188 23:44:44.431625 Updating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/bin/lava-os-build (debian)
189 23:44:44.431757 Creating /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/environment
190 23:44:44.431875 LAVA metadata
191 23:44:44.431951 - LAVA_JOB_ID=14172940
192 23:44:44.432025 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:44:44.432147 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:44:44.432222 skipped lava-vland-overlay
195 23:44:44.432305 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:44:44.432393 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:44:44.432462 skipped lava-multinode-overlay
198 23:44:44.432544 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:44:44.432630 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:44:44.432715 Loading test definitions
201 23:44:44.432814 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:44:44.432896 Using /lava-14172940 at stage 0
203 23:44:44.433213 uuid=14172940_1.6.2.3.1 testdef=None
204 23:44:44.433309 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:44:44.433401 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:44:44.433902 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:44:44.434152 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:44:44.434749 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:44:44.435007 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:44:44.438080 runner path: /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/0/tests/0_timesync-off test_uuid 14172940_1.6.2.3.1
213 23:44:44.438260 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:44:44.438516 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:44:44.438595 Using /lava-14172940 at stage 0
217 23:44:44.438706 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:44:44.438801 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/0/tests/1_kselftest-alsa'
219 23:44:46.531723 Running '/usr/bin/git checkout kernelci.org
220 23:44:46.697169 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 23:44:46.698033 uuid=14172940_1.6.2.3.5 testdef=None
222 23:44:46.698216 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 23:44:46.698523 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 23:44:46.699389 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:44:46.699679 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 23:44:46.700817 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:44:46.701116 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 23:44:46.702224 runner path: /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/0/tests/1_kselftest-alsa test_uuid 14172940_1.6.2.3.5
232 23:44:46.702325 BOARD='mt8183-kukui-jacuzzi-juniper-sku16'
233 23:44:46.702397 BRANCH='cip'
234 23:44:46.702463 SKIPFILE='/dev/null'
235 23:44:46.702527 SKIP_INSTALL='True'
236 23:44:46.702601 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:44:46.702695 TST_CASENAME=''
238 23:44:46.702775 TST_CMDFILES='alsa'
239 23:44:46.702989 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:44:46.703391 Creating lava-test-runner.conf files
242 23:44:46.703475 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14172940/lava-overlay-q_e3y_2t/lava-14172940/0 for stage 0
243 23:44:46.703577 - 0_timesync-off
244 23:44:46.703675 - 1_kselftest-alsa
245 23:44:46.703784 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 23:44:46.703884 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 23:44:55.186046 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:44:55.186214 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 23:44:55.186315 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:44:55.186426 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 23:44:55.186526 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 23:44:55.386444 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:44:55.386924 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 23:44:55.387087 extracting modules file /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172940/extract-nfsrootfs-kqrq6156
255 23:44:55.646084 extracting modules file /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172940/extract-overlay-ramdisk-l_1_5bbq/ramdisk
256 23:44:55.989955 end: 1.6.4 extract-modules (duration 00:00:01) [common]
257 23:44:55.990170 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 23:44:55.990340 [common] Applying overlay to NFS
259 23:44:55.990457 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172940/compress-overlay-n0wojcax/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14172940/extract-nfsrootfs-kqrq6156
260 23:44:57.048993 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:44:57.049211 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 23:44:57.049364 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:44:57.049499 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 23:44:57.049624 Building ramdisk /var/lib/lava/dispatcher/tmp/14172940/extract-overlay-ramdisk-l_1_5bbq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14172940/extract-overlay-ramdisk-l_1_5bbq/ramdisk
265 23:44:57.399111 >> 130337 blocks
266 23:44:59.730597 rename /var/lib/lava/dispatcher/tmp/14172940/extract-overlay-ramdisk-l_1_5bbq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/ramdisk/ramdisk.cpio.gz
267 23:44:59.731140 end: 1.6.7 compress-ramdisk (duration 00:00:03) [common]
268 23:44:59.731315 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 23:44:59.731479 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 23:44:59.731644 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/kernel/Image']
271 23:45:15.265020 Returned 0 in 15 seconds
272 23:45:15.365671 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb -i /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/kernel/image.itb
273 23:45:15.778874 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:45:15.779291 output: Created: Wed Jun 5 00:45:15 2024
275 23:45:15.779435 output: Image 0 (kernel-1)
276 23:45:15.779548 output: Description:
277 23:45:15.779677 output: Created: Wed Jun 5 00:45:15 2024
278 23:45:15.779783 output: Type: Kernel Image
279 23:45:15.779900 output: Compression: lzma compressed
280 23:45:15.780024 output: Data Size: 13061430 Bytes = 12755.30 KiB = 12.46 MiB
281 23:45:15.780125 output: Architecture: AArch64
282 23:45:15.780225 output: OS: Linux
283 23:45:15.780322 output: Load Address: 0x00000000
284 23:45:15.780419 output: Entry Point: 0x00000000
285 23:45:15.780486 output: Hash algo: crc32
286 23:45:15.780551 output: Hash value: ecfb5096
287 23:45:15.780614 output: Image 1 (fdt-1)
288 23:45:15.780678 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
289 23:45:15.780756 output: Created: Wed Jun 5 00:45:15 2024
290 23:45:15.780872 output: Type: Flat Device Tree
291 23:45:15.780975 output: Compression: uncompressed
292 23:45:15.781078 output: Data Size: 57695 Bytes = 56.34 KiB = 0.06 MiB
293 23:45:15.781150 output: Architecture: AArch64
294 23:45:15.781249 output: Hash algo: crc32
295 23:45:15.781354 output: Hash value: a9713552
296 23:45:15.781453 output: Image 2 (ramdisk-1)
297 23:45:15.781551 output: Description: unavailable
298 23:45:15.781646 output: Created: Wed Jun 5 00:45:15 2024
299 23:45:15.781750 output: Type: RAMDisk Image
300 23:45:15.781848 output: Compression: Unknown Compression
301 23:45:15.781943 output: Data Size: 18728667 Bytes = 18289.71 KiB = 17.86 MiB
302 23:45:15.782039 output: Architecture: AArch64
303 23:45:15.782145 output: OS: Linux
304 23:45:15.782240 output: Load Address: unavailable
305 23:45:15.782336 output: Entry Point: unavailable
306 23:45:15.782430 output: Hash algo: crc32
307 23:45:15.782535 output: Hash value: 7eae562b
308 23:45:15.782630 output: Default Configuration: 'conf-1'
309 23:45:15.782725 output: Configuration 0 (conf-1)
310 23:45:15.782821 output: Description: mt8183-kukui-jacuzzi-juniper-sku16
311 23:45:15.782925 output: Kernel: kernel-1
312 23:45:15.783020 output: Init Ramdisk: ramdisk-1
313 23:45:15.783115 output: FDT: fdt-1
314 23:45:15.783209 output: Loadables: kernel-1
315 23:45:15.783302 output:
316 23:45:15.783582 end: 1.6.8.1 prepare-fit (duration 00:00:16) [common]
317 23:45:15.783734 end: 1.6.8 prepare-kernel (duration 00:00:16) [common]
318 23:45:15.783892 end: 1.6 prepare-tftp-overlay (duration 00:00:35) [common]
319 23:45:15.784015 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:16) [common]
320 23:45:15.784105 No LXC device requested
321 23:45:15.784193 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:45:15.784290 start: 1.8 deploy-device-env (timeout 00:09:16) [common]
323 23:45:15.784379 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:45:15.784456 Checking files for TFTP limit of 4294967296 bytes.
325 23:45:15.785035 end: 1 tftp-deploy (duration 00:00:44) [common]
326 23:45:15.785158 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:45:15.785266 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:45:15.785414 substitutions:
329 23:45:15.785488 - {DTB}: 14172940/tftp-deploy-j2ocngpm/dtb/mt8183-kukui-jacuzzi-juniper-sku16.dtb
330 23:45:15.785561 - {INITRD}: 14172940/tftp-deploy-j2ocngpm/ramdisk/ramdisk.cpio.gz
331 23:45:15.785641 - {KERNEL}: 14172940/tftp-deploy-j2ocngpm/kernel/Image
332 23:45:15.785707 - {LAVA_MAC}: None
333 23:45:15.785771 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14172940/extract-nfsrootfs-kqrq6156
334 23:45:15.785835 - {NFS_SERVER_IP}: 192.168.201.1
335 23:45:15.785896 - {PRESEED_CONFIG}: None
336 23:45:15.785956 - {PRESEED_LOCAL}: None
337 23:45:15.786051 - {RAMDISK}: 14172940/tftp-deploy-j2ocngpm/ramdisk/ramdisk.cpio.gz
338 23:45:15.786145 - {ROOT_PART}: None
339 23:45:15.786238 - {ROOT}: None
340 23:45:15.786330 - {SERVER_IP}: 192.168.201.1
341 23:45:15.786422 - {TEE}: None
342 23:45:15.786514 Parsed boot commands:
343 23:45:15.786604 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:45:15.786863 Parsed boot commands: tftpboot 192.168.201.1 14172940/tftp-deploy-j2ocngpm/kernel/image.itb 14172940/tftp-deploy-j2ocngpm/kernel/cmdline
345 23:45:15.786993 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:45:15.787123 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:45:15.787262 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:45:15.787389 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:45:15.787485 Not connected, no need to disconnect.
350 23:45:15.787568 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:45:15.787661 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:45:15.787739 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8183-kukui-jacuzzi-juniper-sku16-cbg-0'
353 23:45:15.791800 Setting prompt string to ['lava-test: # ']
354 23:45:15.792224 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:45:15.792348 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:45:15.792452 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:45:15.792550 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:45:15.792752 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8183-kukui-jacuzzi-juniper-sku16-cbg-0']
359 23:45:38.030353 Returned 0 in 22 seconds
360 23:45:38.131053 end: 2.2.2.1 pdu-reboot (duration 00:00:22) [common]
362 23:45:38.131409 end: 2.2.2 reset-device (duration 00:00:22) [common]
363 23:45:38.131524 start: 2.2.3 depthcharge-start (timeout 00:04:38) [common]
364 23:45:38.131623 Setting prompt string to 'Starting depthcharge on Juniper...'
365 23:45:38.131698 Changing prompt to 'Starting depthcharge on Juniper...'
366 23:45:38.131779 depthcharge-start: Wait for prompt Starting depthcharge on Juniper... (timeout 00:05:00)
367 23:45:38.132224 [Enter `^Ec?' for help]
368 23:45:38.132317 [DL] 00000000 00000000 010701
369 23:45:38.132396
370 23:45:38.132469
371 23:45:38.132539 F0: 102B 0000
372 23:45:38.132605
373 23:45:38.132671 F3: 1006 0033 [0200]
374 23:45:38.132736
375 23:45:38.132801 F3: 4001 00E0 [0200]
376 23:45:38.132863
377 23:45:38.132923 F3: 0000 0000
378 23:45:38.132985
379 23:45:38.133045 V0: 0000 0000 [0001]
380 23:45:38.133105
381 23:45:38.133164 00: 1027 0002
382 23:45:38.133228
383 23:45:38.133288 01: 0000 0000
384 23:45:38.133350
385 23:45:38.133409 BP: 0C00 0251 [0000]
386 23:45:38.133469
387 23:45:38.133528 G0: 1182 0000
388 23:45:38.133588
389 23:45:38.133647 EC: 0004 0000 [0001]
390 23:45:38.133706
391 23:45:38.133765 S7: 0000 0000 [0000]
392 23:45:38.133825
393 23:45:38.133884 CC: 0000 0000 [0001]
394 23:45:38.133943
395 23:45:38.134002 T0: 0000 00DB [000F]
396 23:45:38.134062
397 23:45:38.134121 Jump to BL
398 23:45:38.134180
399 23:45:38.134239
400 23:45:38.134298
401 23:45:38.134356 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 verstage starting (log level: 8)...
402 23:45:38.134420 ARM64: Exception handlers installed.
403 23:45:38.134480 ARM64: Testing exception
404 23:45:38.134540 ARM64: Done test exception
405 23:45:38.134599 WDT: Last reset was cold boot
406 23:45:38.134658 SPI0(PAD0) initialized at 992727 Hz
407 23:45:38.134718 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
408 23:45:38.134778 Manufacturer: ef
409 23:45:38.134866 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
410 23:45:38.134929 Probing TPM: . done!
411 23:45:38.134989 TPM ready after 0 ms
412 23:45:38.135050 Connected to device vid:did:rid of 1ae0:0028:00
413 23:45:38.135111 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
414 23:45:38.135173 Initialized TPM device CR50 revision 0
415 23:45:38.135233 tlcl_send_startup: Startup return code is 0
416 23:45:38.135293 TPM: setup succeeded
417 23:45:38.135353 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
418 23:45:38.135427 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
419 23:45:38.135491 in-header: 03 19 00 00 08 00 00 00
420 23:45:38.135552 in-data: a2 e0 47 00 13 00 00 00
421 23:45:38.135612 Chrome EC: UHEPI supported
422 23:45:38.135671 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
423 23:45:38.135732 in-header: 03 a1 00 00 08 00 00 00
424 23:45:38.135791 in-data: 84 60 60 10 00 00 00 00
425 23:45:38.135851 Phase 1
426 23:45:38.135911 FMAP: area GBB found @ 3f5000 (12032 bytes)
427 23:45:38.135972 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
428 23:45:38.136032 VB2:vb2_check_recovery() Recovery was requested manually
429 23:45:38.136092 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x0
430 23:45:38.136152 Recovery requested (1009000e)
431 23:45:38.136212 tlcl_extend: response is 0
432 23:45:38.136271 tlcl_extend: response is 0
433 23:45:38.136331
434 23:45:38.136390
435 23:45:38.136449 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 romstage starting (log level: 8)...
436 23:45:38.136510 ARM64: Exception handlers installed.
437 23:45:38.136569 ARM64: Testing exception
438 23:45:38.136629 ARM64: Done test exception
439 23:45:38.136688 [RTC]rtc_enable_dcxo,41: con=0x482, osc32con=0xc268, sec=0x2004
440 23:45:38.136749 [RTC]rtc_check_state,142: con=482, pwrkey1=a357, pwrkey2=67d2
441 23:45:38.136808 [RTC]rtc_eosc_cali,157: PMIC_RG_FQMTR_CKSEL=0x4a
442 23:45:38.136868 [RTC]rtc_get_frequency_meter,134: input=0xf, output=916
443 23:45:38.136928 [RTC]rtc_get_frequency_meter,134: input=0x7, output=778
444 23:45:38.136987 [RTC]rtc_get_frequency_meter,134: input=0xb, output=848
445 23:45:38.137047 [RTC]rtc_get_frequency_meter,134: input=0x9, output=811
446 23:45:38.137107 [RTC]rtc_get_frequency_meter,134: input=0x8, output=796
447 23:45:38.137180 [RTC]rtc_osc_init,208: EOSC32 cali val = 0xc268
448 23:45:38.137242 [RTC]rtc_boot_common,186: irqsta=0, bbpu=0, con=482
449 23:45:38.137303 [RTC]rtc_bbpu_power_on,373: rtc_write_trigger=1
450 23:45:38.137371 [RTC]rtc_bbpu_power_on,376: done BBPU=0x9
451 23:45:38.137433 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
452 23:45:38.137494 in-header: 03 19 00 00 08 00 00 00
453 23:45:38.137557 in-data: a2 e0 47 00 13 00 00 00
454 23:45:38.137617 Chrome EC: UHEPI supported
455 23:45:38.137694 out: cmd=0xa4: 03 5d a4 00 00 00 0c 00 00 01 00 00 f4 fb 00 00 00 00 00 00
456 23:45:38.137759 in-header: 03 a1 00 00 08 00 00 00
457 23:45:38.137823 in-data: 84 60 60 10 00 00 00 00
458 23:45:38.137887 Skip loading cached calibration data
459 23:45:38.137951 out: cmd=0xa4: 03 7f a4 00 00 00 0c 00 00 01 00 00 d0 ff ff ff 00 00 00 00
460 23:45:38.138016 in-header: 03 a1 00 00 08 00 00 00
461 23:45:38.138080 in-data: 84 60 60 10 00 00 00 00
462 23:45:38.138144 out: cmd=0xa4: 03 79 a4 00 00 00 0c 00 00 01 00 00 f0 7e 11 00 84 60 60 10
463 23:45:38.138209 in-header: 03 a1 00 00 08 00 00 00
464 23:45:38.138273 in-data: 84 60 60 10 00 00 00 00
465 23:45:38.138337 ADC[3]: Raw value=216216 ID=1
466 23:45:38.138401 Manufacturer: ef
467 23:45:38.138465 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
468 23:45:38.138530 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
469 23:45:38.138595 CBFS @ 21000 size 3d4000
470 23:45:38.138659 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
471 23:45:38.138724 CBFS: Locating 'sdram-lpddr4x-H9HCNNNCPMALHR-4GB'
472 23:45:38.138795 CBFS: Found @ offset 3c700 size 44
473 23:45:38.138882 DRAM-K: Full Calibration
474 23:45:38.138949 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
475 23:45:38.139015 CBFS @ 21000 size 3d4000
476 23:45:38.139079 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
477 23:45:38.139144 CBFS: Locating 'fallback/dram'
478 23:45:38.139208 CBFS: Found @ offset 24b00 size 12268
479 23:45:38.139272 read SPI 0x45b44 0x1224c: 22774 us, 3263 KB/s, 26.104 Mbps
480 23:45:38.139337 ddr_geometry: 1, config: 0x0
481 23:45:38.139402 header.status = 0x0
482 23:45:38.139480 header.magic = 0x44524d4b (expected: 0x44524d4b)
483 23:45:38.139545 header.version = 0x5 (expected: 0x5)
484 23:45:38.139609 header.size = 0x8f0 (expected: 0x8f0)
485 23:45:38.139673 header.config = 0x0
486 23:45:38.139737 header.flags = 0x0
487 23:45:38.139801 header.checksum = 0x0
488 23:45:38.140066 dram_init: MediaTek DRAM firmware version: 1.5.0, accepting param version 5
489 23:45:38.140139 Set DRAM voltage: vdram1 = 1125000, vddq = 600000
490 23:45:38.140205 Get DRAM voltage to vdram1 = 1125000, vddq = 600000
491 23:45:38.140270 ddr_geometry:1
492 23:45:38.140335 [EMI] new MDL number = 1
493 23:45:38.140399 dram_cbt_mode_extern: 0
494 23:45:38.140464 dram_cbt_mode [RK0]: 0, [RK1]: 0
495 23:45:38.140529 Rank info: 0 emi_setting_index: 1 CONA[0xf053f154]
496 23:45:38.140594
497 23:45:38.140658
498 23:45:38.140722 [Bianco] ETT version 0.0.0.1
499 23:45:38.140787 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
500 23:45:38.140851
501 23:45:38.140915 vSetVcoreByFreq with vcore:762500, freq=1600
502 23:45:38.140981
503 23:45:38.141049 [DramcInit]
504 23:45:38.141113 AutoRefreshCKEOff AutoREF OFF
505 23:45:38.141178 DDRPhyPLLSetting-CKEOFF
506 23:45:38.141242 DDRPhyPLLSetting-CKEON
507 23:45:38.141304
508 23:45:38.141368 Enable WDQS
509 23:45:38.141432 [ModeRegInit_LP4] CH0 RK0
510 23:45:38.141496 Write Rank0 MR13 =0x18
511 23:45:38.141560 Write Rank0 MR12 =0x5d
512 23:45:38.141623 Write Rank0 MR1 =0x56
513 23:45:38.141687 Write Rank0 MR2 =0x1a
514 23:45:38.141750 Write Rank0 MR11 =0x0
515 23:45:38.141814 Write Rank0 MR22 =0x38
516 23:45:38.141878 Write Rank0 MR14 =0x5d
517 23:45:38.141941 Write Rank0 MR3 =0x30
518 23:45:38.142005 Write Rank0 MR13 =0x58
519 23:45:38.142068 Write Rank0 MR12 =0x5d
520 23:45:38.142132 Write Rank0 MR1 =0x56
521 23:45:38.142195 Write Rank0 MR2 =0x2d
522 23:45:38.142259 Write Rank0 MR11 =0x23
523 23:45:38.142323 Write Rank0 MR22 =0x34
524 23:45:38.142386 Write Rank0 MR14 =0x10
525 23:45:38.142450 Write Rank0 MR3 =0x30
526 23:45:38.142514 Write Rank0 MR13 =0xd8
527 23:45:38.142578 [ModeRegInit_LP4] CH0 RK1
528 23:45:38.142642 Write Rank1 MR13 =0x18
529 23:45:38.142705 Write Rank1 MR12 =0x5d
530 23:45:38.142768 Write Rank1 MR1 =0x56
531 23:45:38.142832 Write Rank1 MR2 =0x1a
532 23:45:38.142895 Write Rank1 MR11 =0x0
533 23:45:38.142958 Write Rank1 MR22 =0x38
534 23:45:38.143022 Write Rank1 MR14 =0x5d
535 23:45:38.143086 Write Rank1 MR3 =0x30
536 23:45:38.143150 Write Rank1 MR13 =0x58
537 23:45:38.143214 Write Rank1 MR12 =0x5d
538 23:45:38.143277 Write Rank1 MR1 =0x56
539 23:45:38.143341 Write Rank1 MR2 =0x2d
540 23:45:38.143414 Write Rank1 MR11 =0x23
541 23:45:38.143482 Write Rank1 MR22 =0x34
542 23:45:38.143546 Write Rank1 MR14 =0x10
543 23:45:38.143610 Write Rank1 MR3 =0x30
544 23:45:38.143673 Write Rank1 MR13 =0xd8
545 23:45:38.143736 [ModeRegInit_LP4] CH1 RK0
546 23:45:38.143800 Write Rank0 MR13 =0x18
547 23:45:38.143864 Write Rank0 MR12 =0x5d
548 23:45:38.143926 Write Rank0 MR1 =0x56
549 23:45:38.143990 Write Rank0 MR2 =0x1a
550 23:45:38.144054 Write Rank0 MR11 =0x0
551 23:45:38.144118 Write Rank0 MR22 =0x38
552 23:45:38.144181 Write Rank0 MR14 =0x5d
553 23:45:38.144244 Write Rank0 MR3 =0x30
554 23:45:38.144308 Write Rank0 MR13 =0x58
555 23:45:38.144372 Write Rank0 MR12 =0x5d
556 23:45:38.144435 Write Rank0 MR1 =0x56
557 23:45:38.144499 Write Rank0 MR2 =0x2d
558 23:45:38.144563 Write Rank0 MR11 =0x23
559 23:45:38.144626 Write Rank0 MR22 =0x34
560 23:45:38.144689 Write Rank0 MR14 =0x10
561 23:45:38.144752 Write Rank0 MR3 =0x30
562 23:45:38.144816 Write Rank0 MR13 =0xd8
563 23:45:38.144879 [ModeRegInit_LP4] CH1 RK1
564 23:45:38.144943 Write Rank1 MR13 =0x18
565 23:45:38.145006 Write Rank1 MR12 =0x5d
566 23:45:38.145069 Write Rank1 MR1 =0x56
567 23:45:38.145132 Write Rank1 MR2 =0x1a
568 23:45:38.145196 Write Rank1 MR11 =0x0
569 23:45:38.145260 Write Rank1 MR22 =0x38
570 23:45:38.145323 Write Rank1 MR14 =0x5d
571 23:45:38.145387 Write Rank1 MR3 =0x30
572 23:45:38.145450 Write Rank1 MR13 =0x58
573 23:45:38.145514 Write Rank1 MR12 =0x5d
574 23:45:38.145578 Write Rank1 MR1 =0x56
575 23:45:38.145640 Write Rank1 MR2 =0x2d
576 23:45:38.145703 Write Rank1 MR11 =0x23
577 23:45:38.145767 Write Rank1 MR22 =0x34
578 23:45:38.145830 Write Rank1 MR14 =0x10
579 23:45:38.145894 Write Rank1 MR3 =0x30
580 23:45:38.145958 Write Rank1 MR13 =0xd8
581 23:45:38.146021 match AC timing 3
582 23:45:38.146085 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
583 23:45:38.146150 [MiockJmeterHQA]
584 23:45:38.146213 vSetVcoreByFreq with vcore:762500, freq=1600
585 23:45:38.146278
586 23:45:38.146341 MIOCK jitter meter ch=0
587 23:45:38.146405
588 23:45:38.146482 1T = (102-17) = 85 dly cells
589 23:45:38.146551 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 735/100 ps
590 23:45:38.146617 vSetVcoreByFreq with vcore:725000, freq=1200
591 23:45:38.146682
592 23:45:38.146745 MIOCK jitter meter ch=0
593 23:45:38.146809
594 23:45:38.146872 1T = (96-16) = 80 dly cells
595 23:45:38.146938 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
596 23:45:38.147003 vSetVcoreByFreq with vcore:725000, freq=800
597 23:45:38.147067
598 23:45:38.147130 MIOCK jitter meter ch=0
599 23:45:38.147201
600 23:45:38.147311 1T = (96-16) = 80 dly cells
601 23:45:38.147426 Clock freq = 1599 MHz, period = 625 ps, 1 dly cell = 781/100 ps
602 23:45:38.147498 vSetVcoreByFreq with vcore:762500, freq=1600
603 23:45:38.147564 vSetVcoreByFreq with vcore:762500, freq=1600
604 23:45:38.147629
605 23:45:38.147694 K DRVP
606 23:45:38.147758 1. OCD DRVP=0 CALOUT=0
607 23:45:38.147824 1. OCD DRVP=1 CALOUT=0
608 23:45:38.147894 1. OCD DRVP=2 CALOUT=0
609 23:45:38.147960 1. OCD DRVP=3 CALOUT=0
610 23:45:38.148026 1. OCD DRVP=4 CALOUT=0
611 23:45:38.148092 1. OCD DRVP=5 CALOUT=0
612 23:45:38.148157 1. OCD DRVP=6 CALOUT=0
613 23:45:38.148223 1. OCD DRVP=7 CALOUT=0
614 23:45:38.148289 1. OCD DRVP=8 CALOUT=0
615 23:45:38.148355 1. OCD DRVP=9 CALOUT=1
616 23:45:38.148421
617 23:45:38.148484 1. OCD DRVP calibration OK! DRVP=9
618 23:45:38.148549
619 23:45:38.148632
620 23:45:38.148700
621 23:45:38.148764 K ODTN
622 23:45:38.148828 3. OCD ODTN=0 ,CALOUT=1
623 23:45:38.148898 3. OCD ODTN=1 ,CALOUT=1
624 23:45:38.148964 3. OCD ODTN=2 ,CALOUT=1
625 23:45:38.149029 3. OCD ODTN=3 ,CALOUT=1
626 23:45:38.149095 3. OCD ODTN=4 ,CALOUT=1
627 23:45:38.149160 3. OCD ODTN=5 ,CALOUT=1
628 23:45:38.149225 3. OCD ODTN=6 ,CALOUT=1
629 23:45:38.149290 3. OCD ODTN=7 ,CALOUT=0
630 23:45:38.149355
631 23:45:38.149419 3. OCD ODTN calibration OK! ODTN=7
632 23:45:38.149484
633 23:45:38.149548 [SwImpedanceCal] DRVP=9, DRVN=9, ODTN=7
634 23:45:38.149612 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15
635 23:45:38.149677 term_option=0, Reg: DRVP=9, DRVN=7, ODTN=15 (After Adjust)
636 23:45:38.149741
637 23:45:38.149805 K DRVP
638 23:45:38.149868 1. OCD DRVP=0 CALOUT=0
639 23:45:38.149933 1. OCD DRVP=1 CALOUT=0
640 23:45:38.149997 1. OCD DRVP=2 CALOUT=0
641 23:45:38.150062 1. OCD DRVP=3 CALOUT=0
642 23:45:38.150127 1. OCD DRVP=4 CALOUT=0
643 23:45:38.150193 1. OCD DRVP=5 CALOUT=0
644 23:45:38.150258 1. OCD DRVP=6 CALOUT=0
645 23:45:38.150324 1. OCD DRVP=7 CALOUT=0
646 23:45:38.150389 1. OCD DRVP=8 CALOUT=0
647 23:45:38.150459 1. OCD DRVP=9 CALOUT=0
648 23:45:38.150545 1. OCD DRVP=10 CALOUT=0
649 23:45:38.150657 1. OCD DRVP=11 CALOUT=1
650 23:45:38.150729
651 23:45:38.150795 1. OCD DRVP calibration OK! DRVP=11
652 23:45:38.150861
653 23:45:38.150924
654 23:45:38.150987
655 23:45:38.151051 K ODTN
656 23:45:38.151114 3. OCD ODTN=0 ,CALOUT=1
657 23:45:38.151373 3. OCD ODTN=1 ,CALOUT=1
658 23:45:38.151467 3. OCD ODTN=2 ,CALOUT=1
659 23:45:38.151537 3. OCD ODTN=3 ,CALOUT=1
660 23:45:38.151603 3. OCD ODTN=4 ,CALOUT=1
661 23:45:38.151669 3. OCD ODTN=5 ,CALOUT=1
662 23:45:38.151734 3. OCD ODTN=6 ,CALOUT=1
663 23:45:38.151800 3. OCD ODTN=7 ,CALOUT=1
664 23:45:38.151866 3. OCD ODTN=8 ,CALOUT=1
665 23:45:38.151931 3. OCD ODTN=9 ,CALOUT=1
666 23:45:38.151999 3. OCD ODTN=10 ,CALOUT=1
667 23:45:38.152065 3. OCD ODTN=11 ,CALOUT=1
668 23:45:38.152130 3. OCD ODTN=12 ,CALOUT=1
669 23:45:38.152196 3. OCD ODTN=13 ,CALOUT=1
670 23:45:38.152261 3. OCD ODTN=14 ,CALOUT=1
671 23:45:38.152326 3. OCD ODTN=15 ,CALOUT=0
672 23:45:38.152391
673 23:45:38.152454 3. OCD ODTN calibration OK! ODTN=15
674 23:45:38.152520
675 23:45:38.152583 [SwImpedanceCal] DRVP=11, DRVN=9, ODTN=15
676 23:45:38.152647 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15
677 23:45:38.152711 term_option=1, Reg: DRVP=11, DRVN=9, ODTN=15 (After Adjust)
678 23:45:38.152776
679 23:45:38.152840 [DramcInit]
680 23:45:38.152904 AutoRefreshCKEOff AutoREF OFF
681 23:45:38.152968 DDRPhyPLLSetting-CKEOFF
682 23:45:38.153032 DDRPhyPLLSetting-CKEON
683 23:45:38.153096
684 23:45:38.153159 Enable WDQS
685 23:45:38.153222 ==
686 23:45:38.153286 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
687 23:45:38.153350 fsp= 1, odt_onoff= 1, Byte mode= 0
688 23:45:38.153415 ==
689 23:45:38.153478 [Duty_Offset_Calibration]
690 23:45:38.153542
691 23:45:38.153605 ===========================
692 23:45:38.153668 B0:1 B1:1 CA:1
693 23:45:38.153732 ==
694 23:45:38.153796 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
695 23:45:38.153860 fsp= 1, odt_onoff= 1, Byte mode= 0
696 23:45:38.153925 ==
697 23:45:38.153988 [Duty_Offset_Calibration]
698 23:45:38.154052
699 23:45:38.154115 ===========================
700 23:45:38.154179 B0:1 B1:0 CA:2
701 23:45:38.154242 [ModeRegInit_LP4] CH0 RK0
702 23:45:38.154305 Write Rank0 MR13 =0x18
703 23:45:38.154369 Write Rank0 MR12 =0x5d
704 23:45:38.154433 Write Rank0 MR1 =0x56
705 23:45:38.154496 Write Rank0 MR2 =0x1a
706 23:45:38.154565 Write Rank0 MR11 =0x0
707 23:45:38.154652 Write Rank0 MR22 =0x38
708 23:45:38.154718 Write Rank0 MR14 =0x5d
709 23:45:38.154783 Write Rank0 MR3 =0x30
710 23:45:38.154847 Write Rank0 MR13 =0x58
711 23:45:38.154910 Write Rank0 MR12 =0x5d
712 23:45:38.154973 Write Rank0 MR1 =0x56
713 23:45:38.155036 Write Rank0 MR2 =0x2d
714 23:45:38.155100 Write Rank0 MR11 =0x23
715 23:45:38.155163 Write Rank0 MR22 =0x34
716 23:45:38.155227 Write Rank0 MR14 =0x10
717 23:45:38.155291 Write Rank0 MR3 =0x30
718 23:45:38.155354 Write Rank0 MR13 =0xd8
719 23:45:38.155429 [ModeRegInit_LP4] CH0 RK1
720 23:45:38.155495 Write Rank1 MR13 =0x18
721 23:45:38.155559 Write Rank1 MR12 =0x5d
722 23:45:38.155623 Write Rank1 MR1 =0x56
723 23:45:38.155687 Write Rank1 MR2 =0x1a
724 23:45:38.155750 Write Rank1 MR11 =0x0
725 23:45:38.155813 Write Rank1 MR22 =0x38
726 23:45:38.155877 Write Rank1 MR14 =0x5d
727 23:45:38.155940 Write Rank1 MR3 =0x30
728 23:45:38.156004 Write Rank1 MR13 =0x58
729 23:45:38.156067 Write Rank1 MR12 =0x5d
730 23:45:38.156131 Write Rank1 MR1 =0x56
731 23:45:38.156195 Write Rank1 MR2 =0x2d
732 23:45:38.156259 Write Rank1 MR11 =0x23
733 23:45:38.156322 Write Rank1 MR22 =0x34
734 23:45:38.156386 Write Rank1 MR14 =0x10
735 23:45:38.156449 Write Rank1 MR3 =0x30
736 23:45:38.156513 Write Rank1 MR13 =0xd8
737 23:45:38.156576 [ModeRegInit_LP4] CH1 RK0
738 23:45:38.156640 Write Rank0 MR13 =0x18
739 23:45:38.156703 Write Rank0 MR12 =0x5d
740 23:45:38.156767 Write Rank0 MR1 =0x56
741 23:45:38.156830 Write Rank0 MR2 =0x1a
742 23:45:38.156894 Write Rank0 MR11 =0x0
743 23:45:38.156957 Write Rank0 MR22 =0x38
744 23:45:38.157021 Write Rank0 MR14 =0x5d
745 23:45:38.157084 Write Rank0 MR3 =0x30
746 23:45:38.157147 Write Rank0 MR13 =0x58
747 23:45:38.157211 Write Rank0 MR12 =0x5d
748 23:45:38.157274 Write Rank0 MR1 =0x56
749 23:45:38.157338 Write Rank0 MR2 =0x2d
750 23:45:38.157401 Write Rank0 MR11 =0x23
751 23:45:38.157464 Write Rank0 MR22 =0x34
752 23:45:38.157527 Write Rank0 MR14 =0x10
753 23:45:38.157590 Write Rank0 MR3 =0x30
754 23:45:38.157654 Write Rank0 MR13 =0xd8
755 23:45:38.157717 [ModeRegInit_LP4] CH1 RK1
756 23:45:38.157781 Write Rank1 MR13 =0x18
757 23:45:38.157844 Write Rank1 MR12 =0x5d
758 23:45:38.157906 Write Rank1 MR1 =0x56
759 23:45:38.157970 Write Rank1 MR2 =0x1a
760 23:45:38.158033 Write Rank1 MR11 =0x0
761 23:45:38.158097 Write Rank1 MR22 =0x38
762 23:45:38.158161 Write Rank1 MR14 =0x5d
763 23:45:38.158224 Write Rank1 MR3 =0x30
764 23:45:38.158287 Write Rank1 MR13 =0x58
765 23:45:38.158350 Write Rank1 MR12 =0x5d
766 23:45:38.158413 Write Rank1 MR1 =0x56
767 23:45:38.158476 Write Rank1 MR2 =0x2d
768 23:45:38.158539 Write Rank1 MR11 =0x23
769 23:45:38.158603 Write Rank1 MR22 =0x34
770 23:45:38.158666 Write Rank1 MR14 =0x10
771 23:45:38.158729 Write Rank1 MR3 =0x30
772 23:45:38.158792 Write Rank1 MR13 =0xd8
773 23:45:38.158856 match AC timing 3
774 23:45:38.158920 [DdrUpdateACTimingReg] Freq = 1600, tRFCab = 141, tRFCab_05T = 0, TXREFCNT = 159, tRFCpb = 65, tRFCpb_05T = 0
775 23:45:38.158985 DramC Write-DBI off
776 23:45:38.159049 DramC Read-DBI off
777 23:45:38.159113 Write Rank0 MR13 =0x59
778 23:45:38.159176 ==
779 23:45:38.159241 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
780 23:45:38.159305 fsp= 1, odt_onoff= 1, Byte mode= 0
781 23:45:38.159370 ==
782 23:45:38.159450 === u2Vref_new: 0x56 --> 0x2d
783 23:45:38.159516 === u2Vref_new: 0x58 --> 0x38
784 23:45:38.159581 === u2Vref_new: 0x5a --> 0x39
785 23:45:38.159646 === u2Vref_new: 0x5c --> 0x3c
786 23:45:38.159710 === u2Vref_new: 0x5e --> 0x3d
787 23:45:38.159774 === u2Vref_new: 0x60 --> 0xa0
788 23:45:38.159839 [CA 0] Center 34 (6~63) winsize 58
789 23:45:38.159903 [CA 1] Center 36 (9~63) winsize 55
790 23:45:38.159967 [CA 2] Center 29 (0~58) winsize 59
791 23:45:38.160031 [CA 3] Center 24 (-3~52) winsize 56
792 23:45:38.160095 [CA 4] Center 25 (-3~53) winsize 57
793 23:45:38.160159 [CA 5] Center 29 (0~59) winsize 60
794 23:45:38.160223
795 23:45:38.160287 [CATrainingPosCal] consider 1 rank data
796 23:45:38.160351 u2DelayCellTimex100 = 735/100 ps
797 23:45:38.160415 CA0 delay=34 (6~63),Diff = 10 PI (13 cell)
798 23:45:38.160480 CA1 delay=36 (9~63),Diff = 12 PI (15 cell)
799 23:45:38.160545 CA2 delay=29 (0~58),Diff = 5 PI (6 cell)
800 23:45:38.160609 CA3 delay=24 (-3~52),Diff = 0 PI (0 cell)
801 23:45:38.160673 CA4 delay=25 (-3~53),Diff = 1 PI (1 cell)
802 23:45:38.160736 CA5 delay=29 (0~59),Diff = 5 PI (6 cell)
803 23:45:38.160800
804 23:45:38.160863 CA PerBit enable=1, Macro0, CA PI delay=24
805 23:45:38.160926 === u2Vref_new: 0x5e --> 0x3d
806 23:45:38.160990
807 23:45:38.161053 Vref(ca) range 1: 30
808 23:45:38.161118
809 23:45:38.161182 CS Dly= 9 (40-0-32)
810 23:45:38.161246 Write Rank0 MR13 =0xd8
811 23:45:38.161310 Write Rank0 MR13 =0xd8
812 23:45:38.161373 Write Rank0 MR12 =0x5e
813 23:45:38.161436 Write Rank1 MR13 =0x59
814 23:45:38.161500 ==
815 23:45:38.161563 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
816 23:45:38.161846 fsp= 1, odt_onoff= 1, Byte mode= 0
817 23:45:38.161919 ==
818 23:45:38.161985 === u2Vref_new: 0x56 --> 0x2d
819 23:45:38.162051 === u2Vref_new: 0x58 --> 0x38
820 23:45:38.162115 === u2Vref_new: 0x5a --> 0x39
821 23:45:38.162180 === u2Vref_new: 0x5c --> 0x3c
822 23:45:38.162244 === u2Vref_new: 0x5e --> 0x3d
823 23:45:38.162308 === u2Vref_new: 0x60 --> 0xa0
824 23:45:38.162388 [CA 0] Center 35 (8~63) winsize 56
825 23:45:38.162464 [CA 1] Center 36 (9~63) winsize 55
826 23:45:38.162529 [CA 2] Center 31 (3~60) winsize 58
827 23:45:38.162593 [CA 3] Center 26 (-2~54) winsize 57
828 23:45:38.162670 [CA 4] Center 26 (-2~55) winsize 58
829 23:45:38.162729 [CA 5] Center 31 (2~61) winsize 60
830 23:45:38.162788
831 23:45:38.162846 [CATrainingPosCal] consider 2 rank data
832 23:45:38.162905 u2DelayCellTimex100 = 735/100 ps
833 23:45:38.162964 CA0 delay=35 (8~63),Diff = 10 PI (13 cell)
834 23:45:38.163024 CA1 delay=36 (9~63),Diff = 11 PI (14 cell)
835 23:45:38.163083 CA2 delay=30 (3~58),Diff = 5 PI (6 cell)
836 23:45:38.163142 CA3 delay=25 (-2~52),Diff = 0 PI (0 cell)
837 23:45:38.163201 CA4 delay=25 (-2~53),Diff = 0 PI (0 cell)
838 23:45:38.163260 CA5 delay=30 (2~59),Diff = 5 PI (6 cell)
839 23:45:38.163318
840 23:45:38.163377 CA PerBit enable=1, Macro0, CA PI delay=25
841 23:45:38.163460 === u2Vref_new: 0x60 --> 0xa0
842 23:45:38.163526
843 23:45:38.163586 Vref(ca) range 1: 32
844 23:45:38.163646
845 23:45:38.163705 CS Dly= 8 (39-0-32)
846 23:45:38.163764 Write Rank1 MR13 =0xd8
847 23:45:38.163823 Write Rank1 MR13 =0xd8
848 23:45:38.163882 Write Rank1 MR12 =0x60
849 23:45:38.163941 [RankSwap] Rank num 2, (Multi 1), Rank 0
850 23:45:38.164001 Write Rank0 MR2 =0xad
851 23:45:38.164059 [Write Leveling]
852 23:45:38.164119 delay byte0 byte1 byte2 byte3
853 23:45:38.164178
854 23:45:38.164237 10 0 0
855 23:45:38.164298 11 0 0
856 23:45:38.164359 12 0 0
857 23:45:38.164419 13 0 0
858 23:45:38.164479 14 0 0
859 23:45:38.164539 15 0 0
860 23:45:38.164598 16 0 0
861 23:45:38.164658 17 0 0
862 23:45:38.164717 18 0 0
863 23:45:38.164776 19 0 0
864 23:45:38.164836 20 0 0
865 23:45:38.164896 21 0 0
866 23:45:38.164955 22 0 0
867 23:45:38.165014 23 0 0
868 23:45:38.165074 24 0 ff
869 23:45:38.165134 25 0 ff
870 23:45:38.165193 26 0 ff
871 23:45:38.165253 27 0 ff
872 23:45:38.165313 28 0 ff
873 23:45:38.165372 29 0 ff
874 23:45:38.165433 30 0 ff
875 23:45:38.165493 31 ff ff
876 23:45:38.165553 32 ff ff
877 23:45:38.165612 33 ff ff
878 23:45:38.165672 34 ff ff
879 23:45:38.165731 35 ff ff
880 23:45:38.165791 36 ff ff
881 23:45:38.165851 37 ff ff
882 23:45:38.165910 pass bytecount = 0xff (0xff: all bytes pass)
883 23:45:38.165969
884 23:45:38.166028 DQS0 dly: 31
885 23:45:38.166087 DQS1 dly: 24
886 23:45:38.166145 Write Rank0 MR2 =0x2d
887 23:45:38.166205 [RankSwap] Rank num 2, (Multi 1), Rank 0
888 23:45:38.166264 Write Rank0 MR1 =0xd6
889 23:45:38.166323 [Gating]
890 23:45:38.166381 ==
891 23:45:38.166440 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
892 23:45:38.166499 fsp= 1, odt_onoff= 1, Byte mode= 0
893 23:45:38.166558 ==
894 23:45:38.166618 3 1 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
895 23:45:38.166678 3 1 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
896 23:45:38.166738 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
897 23:45:38.166798 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
898 23:45:38.166859 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
899 23:45:38.166919 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
900 23:45:38.166981 3 1 24 |1110 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
901 23:45:38.167042 3 1 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
902 23:45:38.167102 3 2 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
903 23:45:38.167162 3 2 4 |3534 2828 |(11 11)(11 11) |(0 0)(1 1)| 0
904 23:45:38.167223 3 2 8 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
905 23:45:38.167283 3 2 12 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
906 23:45:38.167343 3 2 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
907 23:45:38.167407 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
908 23:45:38.167476 3 2 24 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
909 23:45:38.167537 3 2 28 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
910 23:45:38.167598 3 3 0 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
911 23:45:38.167658 3 3 4 |3534 2121 |(11 11)(11 11) |(0 0)(1 1)| 0
912 23:45:38.167723 3 3 8 |3534 2928 |(11 11)(11 11) |(0 0)(1 1)| 0
913 23:45:38.167784 3 3 12 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
914 23:45:38.167845 [Byte 1] Lead/lag falling Transition (3, 3, 12)
915 23:45:38.167904 3 3 16 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
916 23:45:38.167964 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
917 23:45:38.168025 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
918 23:45:38.168085 3 3 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
919 23:45:38.168145 3 4 0 |3d3d 201 |(11 11)(11 11) |(1 1)(0 1)| 0
920 23:45:38.168205 3 4 4 |3d3d 1c1b |(11 11)(11 11) |(1 1)(1 1)| 0
921 23:45:38.168266 3 4 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
922 23:45:38.168326 3 4 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
923 23:45:38.168386 3 4 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
924 23:45:38.168446 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
925 23:45:38.168505 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
926 23:45:38.168565 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
927 23:45:38.168625 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
928 23:45:38.168685 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
929 23:45:38.168746 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
930 23:45:38.168805 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
931 23:45:38.168865 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
932 23:45:38.168925 [Byte 0] Lead/lag falling Transition (3, 5, 16)
933 23:45:38.168985 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
934 23:45:38.169045 [Byte 0] Lead/lag Transition tap number (2)
935 23:45:38.169104 [Byte 1] Lead/lag falling Transition (3, 5, 20)
936 23:45:38.169163 3 5 24 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
937 23:45:38.169223 3 5 28 |a0a 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
938 23:45:38.169283 [Byte 1] Lead/lag Transition tap number (3)
939 23:45:38.169540 3 6 0 |4646 403 |(0 0)(11 11) |(0 0)(0 0)| 0
940 23:45:38.169608 [Byte 0]First pass (3, 6, 0)
941 23:45:38.169669 3 6 4 |4646 202 |(0 0)(11 11) |(0 0)(0 0)| 0
942 23:45:38.169730 3 6 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
943 23:45:38.169790 [Byte 1]First pass (3, 6, 8)
944 23:45:38.169850 3 6 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
945 23:45:38.169910 3 6 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
946 23:45:38.169971 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
947 23:45:38.170053 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
948 23:45:38.170152 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
949 23:45:38.170248 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
950 23:45:38.170353 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
951 23:45:38.170419 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
952 23:45:38.170480 All bytes gating window > 1UI, Early break!
953 23:45:38.170539
954 23:45:38.170599 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 20)
955 23:45:38.170659
956 23:45:38.170717 best DQS1 dly(2T, 0.5T, PI) = (3, 5, 26)
957 23:45:38.170776
958 23:45:38.170835
959 23:45:38.170893
960 23:45:38.170951 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 20)
961 23:45:38.171010
962 23:45:38.171068 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 1, 26)
963 23:45:38.171127
964 23:45:38.171186
965 23:45:38.171243 Write Rank0 MR1 =0x56
966 23:45:38.171301
967 23:45:38.171359 best RODT dly(2T, 0.5T) = (2, 2)
968 23:45:38.171427
969 23:45:38.171487 best RODT dly(2T, 0.5T) = (2, 2)
970 23:45:38.171546 ==
971 23:45:38.171605 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
972 23:45:38.171665 fsp= 1, odt_onoff= 1, Byte mode= 0
973 23:45:38.171724 ==
974 23:45:38.171783 Start DQ dly to find pass range UseTestEngine =0
975 23:45:38.171843 x-axis: bit #, y-axis: DQ dly (-127~63)
976 23:45:38.171903 RX Vref Scan = 0
977 23:45:38.171962 -26, [0] xxxxxxxx xxxxxxxx [MSB]
978 23:45:38.172023 -25, [0] xxxxxxxx xxxxxxxx [MSB]
979 23:45:38.172084 -24, [0] xxxxxxxx xxxxxxxx [MSB]
980 23:45:38.172144 -23, [0] xxxxxxxx xxxxxxxx [MSB]
981 23:45:38.172205 -22, [0] xxxxxxxx xxxxxxxx [MSB]
982 23:45:38.172265 -21, [0] xxxxxxxx xxxxxxxx [MSB]
983 23:45:38.172325 -20, [0] xxxxxxxx xxxxxxxx [MSB]
984 23:45:38.172413 -19, [0] xxxxxxxx xxxxxxxx [MSB]
985 23:45:38.172511 -18, [0] xxxxxxxx xxxxxxxx [MSB]
986 23:45:38.172574 -17, [0] xxxxxxxx xxxxxxxx [MSB]
987 23:45:38.172634 -16, [0] xxxxxxxx xxxxxxxx [MSB]
988 23:45:38.172695 -15, [0] xxxxxxxx xxxxxxxx [MSB]
989 23:45:38.172757 -14, [0] xxxxxxxx xxxxxxxx [MSB]
990 23:45:38.172817 -13, [0] xxxxxxxx xxxxxxxx [MSB]
991 23:45:38.172878 -12, [0] xxxxxxxx xxxxxxxx [MSB]
992 23:45:38.172939 -11, [0] xxxxxxxx xxxxxxxx [MSB]
993 23:45:38.172999 -10, [0] xxxxxxxx xxxxxxxx [MSB]
994 23:45:38.173060 -9, [0] xxxxxxxx xxxxxxxx [MSB]
995 23:45:38.173121 -8, [0] xxxxxxxx xxxxxxxx [MSB]
996 23:45:38.173181 -7, [0] xxxxxxxx xxxxxxxx [MSB]
997 23:45:38.173241 -6, [0] xxxxxxxx xxxxxxxx [MSB]
998 23:45:38.173301 -5, [0] xxxxxxxx xxxxxxxx [MSB]
999 23:45:38.173361 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1000 23:45:38.173422 -3, [0] xxxxxxxx oxxxxxxx [MSB]
1001 23:45:38.173482 -2, [0] xxxoxxxx oxxxxxxx [MSB]
1002 23:45:38.173542 -1, [0] xxxoxxxx ooxoxxxx [MSB]
1003 23:45:38.173601 0, [0] xxxoxoxx ooxoxoxx [MSB]
1004 23:45:38.173662 1, [0] xxxoxoox ooxoooxx [MSB]
1005 23:45:38.173722 2, [0] xxxoxoox ooxoooxx [MSB]
1006 23:45:38.173782 3, [0] xxxoxooo ooxoooox [MSB]
1007 23:45:38.173842 4, [0] xxxoxooo ooxoooox [MSB]
1008 23:45:38.173902 5, [0] xooooooo ooxooooo [MSB]
1009 23:45:38.173961 6, [0] oooooooo ooxooooo [MSB]
1010 23:45:38.174022 7, [0] oooooooo ooxooooo [MSB]
1011 23:45:38.174083 32, [0] oooxoooo oooooooo [MSB]
1012 23:45:38.174144 33, [0] oooxoooo xooooooo [MSB]
1013 23:45:38.174204 34, [0] oooxoooo xooooooo [MSB]
1014 23:45:38.174265 35, [0] oooxoxoo xooooooo [MSB]
1015 23:45:38.174325 36, [0] oooxoxoo xooxoooo [MSB]
1016 23:45:38.174385 37, [0] oooxoxxx xxoxoooo [MSB]
1017 23:45:38.174445 38, [0] oooxoxxx xxoxxoxo [MSB]
1018 23:45:38.174505 39, [0] oooxxxxx xxoxxxxo [MSB]
1019 23:45:38.174565 40, [0] xooxxxxx xxoxxxxo [MSB]
1020 23:45:38.174625 41, [0] xxxxxxxx xxoxxxxo [MSB]
1021 23:45:38.174685 42, [0] xxxxxxxx xxoxxxxx [MSB]
1022 23:45:38.174745 43, [0] xxxxxxxx xxoxxxxx [MSB]
1023 23:45:38.174804 44, [0] xxxxxxxx xxxxxxxx [MSB]
1024 23:45:38.174865 iDelay=44, Bit 0, Center 22 (6 ~ 39) 34
1025 23:45:38.174933 iDelay=44, Bit 1, Center 22 (5 ~ 40) 36
1026 23:45:38.174998 iDelay=44, Bit 2, Center 22 (5 ~ 40) 36
1027 23:45:38.175058 iDelay=44, Bit 3, Center 14 (-2 ~ 31) 34
1028 23:45:38.175118 iDelay=44, Bit 4, Center 21 (5 ~ 38) 34
1029 23:45:38.175177 iDelay=44, Bit 5, Center 17 (0 ~ 34) 35
1030 23:45:38.175235 iDelay=44, Bit 6, Center 18 (1 ~ 36) 36
1031 23:45:38.175294 iDelay=44, Bit 7, Center 19 (3 ~ 36) 34
1032 23:45:38.175353 iDelay=44, Bit 8, Center 14 (-3 ~ 32) 36
1033 23:45:38.175417 iDelay=44, Bit 9, Center 17 (-1 ~ 36) 38
1034 23:45:38.175476 iDelay=44, Bit 10, Center 25 (8 ~ 43) 36
1035 23:45:38.175535 iDelay=44, Bit 11, Center 17 (-1 ~ 35) 37
1036 23:45:38.175608 iDelay=44, Bit 12, Center 19 (1 ~ 37) 37
1037 23:45:38.175679 iDelay=44, Bit 13, Center 19 (0 ~ 38) 39
1038 23:45:38.175738 iDelay=44, Bit 14, Center 20 (3 ~ 37) 35
1039 23:45:38.175796 iDelay=44, Bit 15, Center 23 (5 ~ 41) 37
1040 23:45:38.175855 ==
1041 23:45:38.175913 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1042 23:45:38.175972 fsp= 1, odt_onoff= 1, Byte mode= 0
1043 23:45:38.176031 ==
1044 23:45:38.176089 DQS Delay:
1045 23:45:38.176148 DQS0 = 0, DQS1 = 0
1046 23:45:38.176207 DQM Delay:
1047 23:45:38.176265 DQM0 = 19, DQM1 = 19
1048 23:45:38.176323 DQ Delay:
1049 23:45:38.176381 DQ0 =22, DQ1 =22, DQ2 =22, DQ3 =14
1050 23:45:38.176440 DQ4 =21, DQ5 =17, DQ6 =18, DQ7 =19
1051 23:45:38.176498 DQ8 =14, DQ9 =17, DQ10 =25, DQ11 =17
1052 23:45:38.176556 DQ12 =19, DQ13 =19, DQ14 =20, DQ15 =23
1053 23:45:38.176615
1054 23:45:38.176673
1055 23:45:38.176730 DramC Write-DBI off
1056 23:45:38.176789 ==
1057 23:45:38.176849 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1058 23:45:38.176908 fsp= 1, odt_onoff= 1, Byte mode= 0
1059 23:45:38.176966 ==
1060 23:45:38.177024 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1061 23:45:38.177083
1062 23:45:38.177141 Begin, DQ Scan Range 920~1176
1063 23:45:38.177199
1064 23:45:38.177256
1065 23:45:38.177314 TX Vref Scan disable
1066 23:45:38.177372 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1067 23:45:38.177432 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1068 23:45:38.177493 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1069 23:45:38.177553 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1070 23:45:38.177613 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1071 23:45:38.177873 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1072 23:45:38.177944 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1073 23:45:38.178006 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1074 23:45:38.178066 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1075 23:45:38.178126 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1076 23:45:38.178186 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1077 23:45:38.178246 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1078 23:45:38.178307 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1079 23:45:38.178379 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1080 23:45:38.178441 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1081 23:45:38.178501 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1082 23:45:38.178560 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1083 23:45:38.178620 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1084 23:45:38.178680 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1085 23:45:38.178741 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1086 23:45:38.178801 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1087 23:45:38.178862 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1088 23:45:38.178922 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1089 23:45:38.178981 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1090 23:45:38.179041 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1091 23:45:38.179101 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1092 23:45:38.179161 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1093 23:45:38.179222 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1094 23:45:38.179282 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1095 23:45:38.179342 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1096 23:45:38.179401 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1097 23:45:38.179469 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1098 23:45:38.179529 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1099 23:45:38.179589 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1100 23:45:38.179650 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1101 23:45:38.179709 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1102 23:45:38.179769 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1103 23:45:38.179828 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1104 23:45:38.179887 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1105 23:45:38.179948 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1106 23:45:38.180008 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1107 23:45:38.180068 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1108 23:45:38.180128 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1109 23:45:38.180188 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1110 23:45:38.180247 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1111 23:45:38.180307 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1112 23:45:38.180368 966 |3 6 6|[0] xxxxxxxx oxxxxxxx [MSB]
1113 23:45:38.180428 967 |3 6 7|[0] xxxxxxxx oxxoxxxx [MSB]
1114 23:45:38.180489 968 |3 6 8|[0] xxxxxxxx ooxoooox [MSB]
1115 23:45:38.180549 969 |3 6 9|[0] xxxxxxxx ooxoooox [MSB]
1116 23:45:38.180608 970 |3 6 10|[0] xxxxxxxx ooxoooox [MSB]
1117 23:45:38.180668 971 |3 6 11|[0] xxxxxxxx ooxooooo [MSB]
1118 23:45:38.180728 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
1119 23:45:38.180795 973 |3 6 13|[0] xxxoxoox oooooooo [MSB]
1120 23:45:38.180873 974 |3 6 14|[0] xxxoooox oooooooo [MSB]
1121 23:45:38.180934 985 |3 6 25|[0] oooooooo xooooooo [MSB]
1122 23:45:38.180995 986 |3 6 26|[0] oooooooo xooooooo [MSB]
1123 23:45:38.181054 987 |3 6 27|[0] oooooooo xooxoooo [MSB]
1124 23:45:38.181114 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1125 23:45:38.181174 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1126 23:45:38.181233 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1127 23:45:38.181293 991 |3 6 31|[0] oooxoooo xxxxxxxx [MSB]
1128 23:45:38.181353 992 |3 6 32|[0] oooxoooo xxxxxxxx [MSB]
1129 23:45:38.181413 993 |3 6 33|[0] oooxoxoo xxxxxxxx [MSB]
1130 23:45:38.181472 994 |3 6 34|[0] oooxoxxo xxxxxxxx [MSB]
1131 23:45:38.181532 995 |3 6 35|[0] oooxxxxx xxxxxxxx [MSB]
1132 23:45:38.181592 996 |3 6 36|[0] xxxxxxxx xxxxxxxx [MSB]
1133 23:45:38.181652 Byte0, DQ PI dly=983, DQM PI dly= 983
1134 23:45:38.181710 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
1135 23:45:38.181770
1136 23:45:38.181828 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
1137 23:45:38.181887
1138 23:45:38.181945 Byte1, DQ PI dly=977, DQM PI dly= 977
1139 23:45:38.182004 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
1140 23:45:38.182062
1141 23:45:38.182120 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
1142 23:45:38.182178
1143 23:45:38.182236 ==
1144 23:45:38.182294 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1145 23:45:38.182352 fsp= 1, odt_onoff= 1, Byte mode= 0
1146 23:45:38.182411 ==
1147 23:45:38.182470 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1148 23:45:38.182528
1149 23:45:38.182586 Begin, DQ Scan Range 953~1017
1150 23:45:38.182644 Write Rank0 MR14 =0x0
1151 23:45:38.182702
1152 23:45:38.182760 CH=0, VrefRange= 0, VrefLevel = 0
1153 23:45:38.182818 TX Bit0 (977~991) 15 984, Bit8 (967~978) 12 972,
1154 23:45:38.182877 TX Bit1 (976~991) 16 983, Bit9 (969~983) 15 976,
1155 23:45:38.182936 TX Bit2 (977~991) 15 984, Bit10 (975~986) 12 980,
1156 23:45:38.182995 TX Bit3 (972~984) 13 978, Bit11 (968~982) 15 975,
1157 23:45:38.183054 TX Bit4 (977~990) 14 983, Bit12 (971~983) 13 977,
1158 23:45:38.183118 TX Bit5 (974~988) 15 981, Bit13 (970~983) 14 976,
1159 23:45:38.183182 TX Bit6 (976~988) 13 982, Bit14 (969~984) 16 976,
1160 23:45:38.183241 TX Bit7 (977~989) 13 983, Bit15 (974~985) 12 979,
1161 23:45:38.183300
1162 23:45:38.183371 Write Rank0 MR14 =0x2
1163 23:45:38.183444
1164 23:45:38.183503 CH=0, VrefRange= 0, VrefLevel = 2
1165 23:45:38.183562 TX Bit0 (977~992) 16 984, Bit8 (967~979) 13 973,
1166 23:45:38.183622 TX Bit1 (976~991) 16 983, Bit9 (969~984) 16 976,
1167 23:45:38.183681 TX Bit2 (977~992) 16 984, Bit10 (975~988) 14 981,
1168 23:45:38.183740 TX Bit3 (972~985) 14 978, Bit11 (968~982) 15 975,
1169 23:45:38.183799 TX Bit4 (976~991) 16 983, Bit12 (970~984) 15 977,
1170 23:45:38.183858 TX Bit5 (974~988) 15 981, Bit13 (969~984) 16 976,
1171 23:45:38.183917 TX Bit6 (976~990) 15 983, Bit14 (969~985) 17 977,
1172 23:45:38.183975 TX Bit7 (977~990) 14 983, Bit15 (974~987) 14 980,
1173 23:45:38.184033
1174 23:45:38.184091 Write Rank0 MR14 =0x4
1175 23:45:38.184149
1176 23:45:38.184207 CH=0, VrefRange= 0, VrefLevel = 4
1177 23:45:38.184265 TX Bit0 (977~992) 16 984, Bit8 (967~981) 15 974,
1178 23:45:38.184525 TX Bit1 (976~992) 17 984, Bit9 (969~984) 16 976,
1179 23:45:38.184598 TX Bit2 (977~992) 16 984, Bit10 (975~989) 15 982,
1180 23:45:38.184661 TX Bit3 (971~986) 16 978, Bit11 (968~983) 16 975,
1181 23:45:38.184721 TX Bit4 (976~991) 16 983, Bit12 (970~984) 15 977,
1182 23:45:38.184781 TX Bit5 (974~989) 16 981, Bit13 (969~984) 16 976,
1183 23:45:38.184842 TX Bit6 (975~990) 16 982, Bit14 (969~985) 17 977,
1184 23:45:38.184901 TX Bit7 (976~991) 16 983, Bit15 (974~988) 15 981,
1185 23:45:38.184959
1186 23:45:38.185020 Write Rank0 MR14 =0x6
1187 23:45:38.185079
1188 23:45:38.185136 CH=0, VrefRange= 0, VrefLevel = 6
1189 23:45:38.185195 TX Bit0 (977~993) 17 985, Bit8 (967~982) 16 974,
1190 23:45:38.185253 TX Bit1 (976~992) 17 984, Bit9 (968~985) 18 976,
1191 23:45:38.185313 TX Bit2 (976~993) 18 984, Bit10 (974~990) 17 982,
1192 23:45:38.185373 TX Bit3 (970~987) 18 978, Bit11 (967~983) 17 975,
1193 23:45:38.185432 TX Bit4 (976~991) 16 983, Bit12 (970~985) 16 977,
1194 23:45:38.185491 TX Bit5 (973~990) 18 981, Bit13 (969~985) 17 977,
1195 23:45:38.185550 TX Bit6 (975~991) 17 983, Bit14 (968~986) 19 977,
1196 23:45:38.185610 TX Bit7 (976~991) 16 983, Bit15 (973~989) 17 981,
1197 23:45:38.185668
1198 23:45:38.185726 Write Rank0 MR14 =0x8
1199 23:45:38.185785
1200 23:45:38.185843 CH=0, VrefRange= 0, VrefLevel = 8
1201 23:45:38.185902 TX Bit0 (976~993) 18 984, Bit8 (967~982) 16 974,
1202 23:45:38.185961 TX Bit1 (975~993) 19 984, Bit9 (968~985) 18 976,
1203 23:45:38.186019 TX Bit2 (976~993) 18 984, Bit10 (973~990) 18 981,
1204 23:45:38.186078 TX Bit3 (970~988) 19 979, Bit11 (967~984) 18 975,
1205 23:45:38.186138 TX Bit4 (976~992) 17 984, Bit12 (969~985) 17 977,
1206 23:45:38.186197 TX Bit5 (973~991) 19 982, Bit13 (969~985) 17 977,
1207 23:45:38.186268 TX Bit6 (975~991) 17 983, Bit14 (968~986) 19 977,
1208 23:45:38.186339 TX Bit7 (976~992) 17 984, Bit15 (973~989) 17 981,
1209 23:45:38.186399
1210 23:45:38.186457 Write Rank0 MR14 =0xa
1211 23:45:38.186515
1212 23:45:38.186573 CH=0, VrefRange= 0, VrefLevel = 10
1213 23:45:38.186633 TX Bit0 (976~994) 19 985, Bit8 (966~982) 17 974,
1214 23:45:38.186691 TX Bit1 (975~993) 19 984, Bit9 (967~985) 19 976,
1215 23:45:38.186750 TX Bit2 (976~993) 18 984, Bit10 (973~990) 18 981,
1216 23:45:38.186809 TX Bit3 (970~988) 19 979, Bit11 (967~984) 18 975,
1217 23:45:38.186867 TX Bit4 (975~992) 18 983, Bit12 (969~985) 17 977,
1218 23:45:38.186927 TX Bit5 (972~991) 20 981, Bit13 (969~986) 18 977,
1219 23:45:38.186986 TX Bit6 (974~992) 19 983, Bit14 (968~987) 20 977,
1220 23:45:38.187044 TX Bit7 (976~992) 17 984, Bit15 (972~989) 18 980,
1221 23:45:38.187102
1222 23:45:38.187161 Write Rank0 MR14 =0xc
1223 23:45:38.187219
1224 23:45:38.187277 CH=0, VrefRange= 0, VrefLevel = 12
1225 23:45:38.187336 TX Bit0 (976~995) 20 985, Bit8 (966~983) 18 974,
1226 23:45:38.187395 TX Bit1 (975~993) 19 984, Bit9 (968~986) 19 977,
1227 23:45:38.187467 TX Bit2 (976~994) 19 985, Bit10 (972~991) 20 981,
1228 23:45:38.187527 TX Bit3 (970~990) 21 980, Bit11 (967~985) 19 976,
1229 23:45:38.187586 TX Bit4 (975~992) 18 983, Bit12 (969~986) 18 977,
1230 23:45:38.187645 TX Bit5 (972~992) 21 982, Bit13 (968~986) 19 977,
1231 23:45:38.187704 TX Bit6 (974~992) 19 983, Bit14 (968~988) 21 978,
1232 23:45:38.187763 TX Bit7 (976~992) 17 984, Bit15 (972~990) 19 981,
1233 23:45:38.187821
1234 23:45:38.187879 Write Rank0 MR14 =0xe
1235 23:45:38.187937
1236 23:45:38.187995 CH=0, VrefRange= 0, VrefLevel = 14
1237 23:45:38.188054 TX Bit0 (976~995) 20 985, Bit8 (966~984) 19 975,
1238 23:45:38.188113 TX Bit1 (975~994) 20 984, Bit9 (968~987) 20 977,
1239 23:45:38.188172 TX Bit2 (976~995) 20 985, Bit10 (972~991) 20 981,
1240 23:45:38.188231 TX Bit3 (969~990) 22 979, Bit11 (967~985) 19 976,
1241 23:45:38.188290 TX Bit4 (975~993) 19 984, Bit12 (968~987) 20 977,
1242 23:45:38.188349 TX Bit5 (971~992) 22 981, Bit13 (968~987) 20 977,
1243 23:45:38.188407 TX Bit6 (973~992) 20 982, Bit14 (968~989) 22 978,
1244 23:45:38.188465 TX Bit7 (976~993) 18 984, Bit15 (971~990) 20 980,
1245 23:45:38.188524
1246 23:45:38.188582 Write Rank0 MR14 =0x10
1247 23:45:38.188640
1248 23:45:38.188697 CH=0, VrefRange= 0, VrefLevel = 16
1249 23:45:38.188755 TX Bit0 (976~996) 21 986, Bit8 (965~984) 20 974,
1250 23:45:38.188814 TX Bit1 (974~994) 21 984, Bit9 (968~987) 20 977,
1251 23:45:38.188873 TX Bit2 (975~995) 21 985, Bit10 (971~991) 21 981,
1252 23:45:38.188932 TX Bit3 (969~990) 22 979, Bit11 (966~986) 21 976,
1253 23:45:38.188991 TX Bit4 (974~994) 21 984, Bit12 (968~988) 21 978,
1254 23:45:38.189050 TX Bit5 (971~992) 22 981, Bit13 (968~988) 21 978,
1255 23:45:38.189109 TX Bit6 (973~993) 21 983, Bit14 (968~990) 23 979,
1256 23:45:38.189168 TX Bit7 (975~993) 19 984, Bit15 (971~991) 21 981,
1257 23:45:38.189226
1258 23:45:38.189284 Write Rank0 MR14 =0x12
1259 23:45:38.189342
1260 23:45:38.189400 CH=0, VrefRange= 0, VrefLevel = 18
1261 23:45:38.189458 TX Bit0 (976~997) 22 986, Bit8 (965~984) 20 974,
1262 23:45:38.189517 TX Bit1 (975~995) 21 985, Bit9 (967~988) 22 977,
1263 23:45:38.189576 TX Bit2 (975~997) 23 986, Bit10 (971~992) 22 981,
1264 23:45:38.189634 TX Bit3 (969~990) 22 979, Bit11 (966~987) 22 976,
1265 23:45:38.189693 TX Bit4 (974~994) 21 984, Bit12 (968~988) 21 978,
1266 23:45:38.189751 TX Bit5 (971~993) 23 982, Bit13 (968~988) 21 978,
1267 23:45:38.189809 TX Bit6 (972~993) 22 982, Bit14 (968~990) 23 979,
1268 23:45:38.189868 TX Bit7 (975~994) 20 984, Bit15 (970~991) 22 980,
1269 23:45:38.189926
1270 23:45:38.189984 Write Rank0 MR14 =0x14
1271 23:45:38.190042
1272 23:45:38.190100 CH=0, VrefRange= 0, VrefLevel = 20
1273 23:45:38.190159 TX Bit0 (975~997) 23 986, Bit8 (965~985) 21 975,
1274 23:45:38.190218 TX Bit1 (974~996) 23 985, Bit9 (967~989) 23 978,
1275 23:45:38.190277 TX Bit2 (975~997) 23 986, Bit10 (970~992) 23 981,
1276 23:45:38.190336 TX Bit3 (968~991) 24 979, Bit11 (966~987) 22 976,
1277 23:45:38.190394 TX Bit4 (974~995) 22 984, Bit12 (968~989) 22 978,
1278 23:45:38.190649 TX Bit5 (970~993) 24 981, Bit13 (968~989) 22 978,
1279 23:45:38.190716 TX Bit6 (972~993) 22 982, Bit14 (968~990) 23 979,
1280 23:45:38.190777 TX Bit7 (974~995) 22 984, Bit15 (970~992) 23 981,
1281 23:45:38.190836
1282 23:45:38.190895 Write Rank0 MR14 =0x16
1283 23:45:38.190953
1284 23:45:38.191012 CH=0, VrefRange= 0, VrefLevel = 22
1285 23:45:38.191070 TX Bit0 (975~998) 24 986, Bit8 (964~986) 23 975,
1286 23:45:38.191130 TX Bit1 (974~996) 23 985, Bit9 (967~989) 23 978,
1287 23:45:38.191189 TX Bit2 (975~998) 24 986, Bit10 (971~992) 22 981,
1288 23:45:38.191248 TX Bit3 (968~991) 24 979, Bit11 (966~987) 22 976,
1289 23:45:38.191307 TX Bit4 (973~995) 23 984, Bit12 (968~990) 23 979,
1290 23:45:38.191366 TX Bit5 (970~993) 24 981, Bit13 (967~990) 24 978,
1291 23:45:38.191432 TX Bit6 (971~994) 24 982, Bit14 (967~990) 24 978,
1292 23:45:38.191491 TX Bit7 (974~995) 22 984, Bit15 (969~992) 24 980,
1293 23:45:38.191550
1294 23:45:38.191608 Write Rank0 MR14 =0x18
1295 23:45:38.191666
1296 23:45:38.191724 CH=0, VrefRange= 0, VrefLevel = 24
1297 23:45:38.191783 TX Bit0 (975~998) 24 986, Bit8 (964~986) 23 975,
1298 23:45:38.191842 TX Bit1 (973~997) 25 985, Bit9 (967~990) 24 978,
1299 23:45:38.191901 TX Bit2 (974~998) 25 986, Bit10 (970~993) 24 981,
1300 23:45:38.191960 TX Bit3 (968~991) 24 979, Bit11 (965~988) 24 976,
1301 23:45:38.192020 TX Bit4 (973~996) 24 984, Bit12 (967~990) 24 978,
1302 23:45:38.192078 TX Bit5 (970~994) 25 982, Bit13 (967~990) 24 978,
1303 23:45:38.192137 TX Bit6 (971~995) 25 983, Bit14 (967~991) 25 979,
1304 23:45:38.192195 TX Bit7 (974~996) 23 985, Bit15 (970~992) 23 981,
1305 23:45:38.192254
1306 23:45:38.192312 Write Rank0 MR14 =0x1a
1307 23:45:38.192371
1308 23:45:38.192429 CH=0, VrefRange= 0, VrefLevel = 26
1309 23:45:38.192488 TX Bit0 (975~998) 24 986, Bit8 (963~987) 25 975,
1310 23:45:38.192546 TX Bit1 (974~998) 25 986, Bit9 (967~990) 24 978,
1311 23:45:38.192605 TX Bit2 (974~998) 25 986, Bit10 (970~993) 24 981,
1312 23:45:38.192664 TX Bit3 (968~992) 25 980, Bit11 (965~989) 25 977,
1313 23:45:38.192723 TX Bit4 (973~997) 25 985, Bit12 (967~990) 24 978,
1314 23:45:38.192782 TX Bit5 (969~994) 26 981, Bit13 (967~990) 24 978,
1315 23:45:38.192841 TX Bit6 (971~995) 25 983, Bit14 (967~991) 25 979,
1316 23:45:38.192900 TX Bit7 (973~996) 24 984, Bit15 (970~993) 24 981,
1317 23:45:38.192958
1318 23:45:38.193015 Write Rank0 MR14 =0x1c
1319 23:45:38.193073
1320 23:45:38.193130 CH=0, VrefRange= 0, VrefLevel = 28
1321 23:45:38.193188 TX Bit0 (975~998) 24 986, Bit8 (963~987) 25 975,
1322 23:45:38.193247 TX Bit1 (974~998) 25 986, Bit9 (967~990) 24 978,
1323 23:45:38.193305 TX Bit2 (974~998) 25 986, Bit10 (970~993) 24 981,
1324 23:45:38.193364 TX Bit3 (968~992) 25 980, Bit11 (965~989) 25 977,
1325 23:45:38.193422 TX Bit4 (973~997) 25 985, Bit12 (967~990) 24 978,
1326 23:45:38.193481 TX Bit5 (969~994) 26 981, Bit13 (967~990) 24 978,
1327 23:45:38.193539 TX Bit6 (971~995) 25 983, Bit14 (967~991) 25 979,
1328 23:45:38.193598 TX Bit7 (973~996) 24 984, Bit15 (970~993) 24 981,
1329 23:45:38.193656
1330 23:45:38.193714 Write Rank0 MR14 =0x1e
1331 23:45:38.193771
1332 23:45:38.193830 CH=0, VrefRange= 0, VrefLevel = 30
1333 23:45:38.193888 TX Bit0 (975~998) 24 986, Bit8 (963~987) 25 975,
1334 23:45:38.193946 TX Bit1 (974~998) 25 986, Bit9 (967~990) 24 978,
1335 23:45:38.194005 TX Bit2 (974~998) 25 986, Bit10 (970~993) 24 981,
1336 23:45:38.194064 TX Bit3 (968~992) 25 980, Bit11 (965~989) 25 977,
1337 23:45:38.194123 TX Bit4 (973~997) 25 985, Bit12 (967~990) 24 978,
1338 23:45:38.194182 TX Bit5 (969~994) 26 981, Bit13 (967~990) 24 978,
1339 23:45:38.194240 TX Bit6 (971~995) 25 983, Bit14 (967~991) 25 979,
1340 23:45:38.194299 TX Bit7 (973~996) 24 984, Bit15 (970~993) 24 981,
1341 23:45:38.194358
1342 23:45:38.194416 Write Rank0 MR14 =0x20
1343 23:45:38.194474
1344 23:45:38.194532 CH=0, VrefRange= 0, VrefLevel = 32
1345 23:45:38.194590 TX Bit0 (975~998) 24 986, Bit8 (963~987) 25 975,
1346 23:45:38.194649 TX Bit1 (974~998) 25 986, Bit9 (967~990) 24 978,
1347 23:45:38.194708 TX Bit2 (974~998) 25 986, Bit10 (970~993) 24 981,
1348 23:45:38.194766 TX Bit3 (968~992) 25 980, Bit11 (965~989) 25 977,
1349 23:45:38.194825 TX Bit4 (973~997) 25 985, Bit12 (967~990) 24 978,
1350 23:45:38.194884 TX Bit5 (969~994) 26 981, Bit13 (967~990) 24 978,
1351 23:45:38.194943 TX Bit6 (971~995) 25 983, Bit14 (967~991) 25 979,
1352 23:45:38.195001 TX Bit7 (973~996) 24 984, Bit15 (970~993) 24 981,
1353 23:45:38.195059
1354 23:45:38.195117 wait MRW command Rank0 MR14 =0x22 fired (1)
1355 23:45:38.195176 Write Rank0 MR14 =0x22
1356 23:45:38.195257
1357 23:45:38.195352 CH=0, VrefRange= 0, VrefLevel = 34
1358 23:45:38.195443 TX Bit0 (975~998) 24 986, Bit8 (963~987) 25 975,
1359 23:45:38.195506 TX Bit1 (974~998) 25 986, Bit9 (967~990) 24 978,
1360 23:45:38.195566 TX Bit2 (974~998) 25 986, Bit10 (970~993) 24 981,
1361 23:45:38.195625 TX Bit3 (968~992) 25 980, Bit11 (965~989) 25 977,
1362 23:45:38.195684 TX Bit4 (973~997) 25 985, Bit12 (967~990) 24 978,
1363 23:45:38.195746 TX Bit5 (969~994) 26 981, Bit13 (967~990) 24 978,
1364 23:45:38.195805 TX Bit6 (971~995) 25 983, Bit14 (967~991) 25 979,
1365 23:45:38.195863 TX Bit7 (973~996) 24 984, Bit15 (970~993) 24 981,
1366 23:45:38.195921
1367 23:45:38.195979 Write Rank0 MR14 =0x24
1368 23:45:38.196036
1369 23:45:38.196094 CH=0, VrefRange= 0, VrefLevel = 36
1370 23:45:38.196152 TX Bit0 (975~998) 24 986, Bit8 (963~987) 25 975,
1371 23:45:38.196211 TX Bit1 (974~998) 25 986, Bit9 (967~990) 24 978,
1372 23:45:38.196269 TX Bit2 (974~998) 25 986, Bit10 (970~993) 24 981,
1373 23:45:38.196327 TX Bit3 (968~992) 25 980, Bit11 (965~989) 25 977,
1374 23:45:38.196385 TX Bit4 (973~997) 25 985, Bit12 (967~990) 24 978,
1375 23:45:38.196443 TX Bit5 (969~994) 26 981, Bit13 (967~990) 24 978,
1376 23:45:38.196515 TX Bit6 (971~995) 25 983, Bit14 (967~991) 25 979,
1377 23:45:38.196786 TX Bit7 (973~996) 24 984, Bit15 (970~993) 24 981,
1378 23:45:38.196863
1379 23:45:38.196923
1380 23:45:38.196982 TX Vref found, early break! 372< 374
1381 23:45:38.197042 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
1382 23:45:38.197101 u1DelayCellOfst[0]=7 cells (6 PI)
1383 23:45:38.197161 u1DelayCellOfst[1]=7 cells (6 PI)
1384 23:45:38.197219 u1DelayCellOfst[2]=7 cells (6 PI)
1385 23:45:38.197277 u1DelayCellOfst[3]=0 cells (0 PI)
1386 23:45:38.197335 u1DelayCellOfst[4]=6 cells (5 PI)
1387 23:45:38.197393 u1DelayCellOfst[5]=1 cells (1 PI)
1388 23:45:38.197452 u1DelayCellOfst[6]=3 cells (3 PI)
1389 23:45:38.197511 u1DelayCellOfst[7]=5 cells (4 PI)
1390 23:45:38.197570 Byte0, DQ PI dly=980, DQM PI dly= 983
1391 23:45:38.197628 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
1392 23:45:38.197688
1393 23:45:38.197746 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
1394 23:45:38.197805
1395 23:45:38.197863 u1DelayCellOfst[8]=0 cells (0 PI)
1396 23:45:38.197920 u1DelayCellOfst[9]=3 cells (3 PI)
1397 23:45:38.197978 u1DelayCellOfst[10]=7 cells (6 PI)
1398 23:45:38.198037 u1DelayCellOfst[11]=2 cells (2 PI)
1399 23:45:38.198096 u1DelayCellOfst[12]=3 cells (3 PI)
1400 23:45:38.198155 u1DelayCellOfst[13]=3 cells (3 PI)
1401 23:45:38.198213 u1DelayCellOfst[14]=5 cells (4 PI)
1402 23:45:38.198270 u1DelayCellOfst[15]=7 cells (6 PI)
1403 23:45:38.198328 Byte1, DQ PI dly=975, DQM PI dly= 978
1404 23:45:38.198386 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 15)
1405 23:45:38.198445
1406 23:45:38.198503 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 15)
1407 23:45:38.198561
1408 23:45:38.198618 Write Rank0 MR14 =0x1a
1409 23:45:38.198676
1410 23:45:38.198733 Final TX Range 0 Vref 26
1411 23:45:38.198792
1412 23:45:38.198849 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
1413 23:45:38.198907
1414 23:45:38.198964 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
1415 23:45:38.199022 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1416 23:45:38.199081 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1417 23:45:38.199139 Write Rank0 MR3 =0xb0
1418 23:45:38.199197 DramC Write-DBI on
1419 23:45:38.199255 ==
1420 23:45:38.199313 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1421 23:45:38.199372 fsp= 1, odt_onoff= 1, Byte mode= 0
1422 23:45:38.199446 ==
1423 23:45:38.199505 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
1424 23:45:38.199563
1425 23:45:38.199620 Begin, DQ Scan Range 698~762
1426 23:45:38.199678
1427 23:45:38.199736
1428 23:45:38.199793 TX Vref Scan disable
1429 23:45:38.199851 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1430 23:45:38.199911 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1431 23:45:38.199971 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1432 23:45:38.200031 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1433 23:45:38.200089 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1434 23:45:38.200149 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1435 23:45:38.200208 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1436 23:45:38.200267 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1437 23:45:38.200327 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1438 23:45:38.200387 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1439 23:45:38.200447 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1440 23:45:38.200506 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1441 23:45:38.200565 710 |2 6 6|[0] xxxxxxxx oooooooo [MSB]
1442 23:45:38.200625 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
1443 23:45:38.200684 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
1444 23:45:38.200743 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
1445 23:45:38.200803 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
1446 23:45:38.200861 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
1447 23:45:38.200921 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
1448 23:45:38.200980 734 |2 6 30|[0] oooooooo xxxxxxxx [MSB]
1449 23:45:38.201039 735 |2 6 31|[0] oooooooo xxxxxxxx [MSB]
1450 23:45:38.201098 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
1451 23:45:38.201157 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
1452 23:45:38.201217 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
1453 23:45:38.201276 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
1454 23:45:38.201335 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
1455 23:45:38.201395 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
1456 23:45:38.201454 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
1457 23:45:38.201513 743 |2 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
1458 23:45:38.201572 Byte0, DQ PI dly=729, DQM PI dly= 729
1459 23:45:38.201630 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 25)
1460 23:45:38.201688
1461 23:45:38.201746 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 25)
1462 23:45:38.201804
1463 23:45:38.201861 Byte1, DQ PI dly=721, DQM PI dly= 721
1464 23:45:38.201919 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 17)
1465 23:45:38.201977
1466 23:45:38.202034 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 17)
1467 23:45:38.202093
1468 23:45:38.202150 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
1469 23:45:38.202209 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
1470 23:45:38.202268 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
1471 23:45:38.202326 Write Rank0 MR3 =0x30
1472 23:45:38.202384 DramC Write-DBI off
1473 23:45:38.202442
1474 23:45:38.202498 [DATLAT]
1475 23:45:38.202565 Freq=1600, CH0 RK0, use_rxtx_scan=0
1476 23:45:38.202626
1477 23:45:38.202684 DATLAT Default: 0xf
1478 23:45:38.202755 7, 0xFFFF, sum=0
1479 23:45:38.202816 8, 0xFFFF, sum=0
1480 23:45:38.202876 9, 0xFFFF, sum=0
1481 23:45:38.202955 10, 0xFFFF, sum=0
1482 23:45:38.203016 11, 0xFFFF, sum=0
1483 23:45:38.203076 12, 0xFFFF, sum=0
1484 23:45:38.203145 13, 0xFFFF, sum=0
1485 23:45:38.203205 14, 0x0, sum=1
1486 23:45:38.203264 15, 0x0, sum=2
1487 23:45:38.203356 16, 0x0, sum=3
1488 23:45:38.203446 17, 0x0, sum=4
1489 23:45:38.203512 pattern=2 first_step=14 total pass=5 best_step=16
1490 23:45:38.203572 ==
1491 23:45:38.203631 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1492 23:45:38.203690 fsp= 1, odt_onoff= 1, Byte mode= 0
1493 23:45:38.203749 ==
1494 23:45:38.203806 Start DQ dly to find pass range UseTestEngine =1
1495 23:45:38.203865 x-axis: bit #, y-axis: DQ dly (-127~63)
1496 23:45:38.203923 RX Vref Scan = 1
1497 23:45:38.203981
1498 23:45:38.204058 RX Vref found, early break!
1499 23:45:38.204144
1500 23:45:38.204218 Final RX Vref 12, apply to both rank0 and 1
1501 23:45:38.204285 ==
1502 23:45:38.204344 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 0
1503 23:45:38.204443 fsp= 1, odt_onoff= 1, Byte mode= 0
1504 23:45:38.204510 ==
1505 23:45:38.204570 DQS Delay:
1506 23:45:38.204651 DQS0 = 0, DQS1 = 0
1507 23:45:38.204711 DQM Delay:
1508 23:45:38.204784 DQM0 = 19, DQM1 = 19
1509 23:45:38.205087 DQ Delay:
1510 23:45:38.205200 DQ0 =22, DQ1 =21, DQ2 =21, DQ3 =15
1511 23:45:38.205298 DQ4 =21, DQ5 =17, DQ6 =19, DQ7 =20
1512 23:45:38.205391 DQ8 =15, DQ9 =17, DQ10 =25, DQ11 =16
1513 23:45:38.205484 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =23
1514 23:45:38.205574
1515 23:45:38.205664
1516 23:45:38.205754
1517 23:45:38.205854 [DramC_TX_OE_Calibration] TA2
1518 23:45:38.205947 Original DQ_B0 (3 6) =30, OEN = 27
1519 23:45:38.206048 Original DQ_B1 (3 6) =30, OEN = 27
1520 23:45:38.206113 23, 0x0, End_B0=23 End_B1=23
1521 23:45:38.206175 24, 0x0, End_B0=24 End_B1=24
1522 23:45:38.206235 25, 0x0, End_B0=25 End_B1=25
1523 23:45:38.206295 26, 0x0, End_B0=26 End_B1=26
1524 23:45:38.206354 27, 0x0, End_B0=27 End_B1=27
1525 23:45:38.206414 28, 0x0, End_B0=28 End_B1=28
1526 23:45:38.206473 29, 0x0, End_B0=29 End_B1=29
1527 23:45:38.206533 30, 0x0, End_B0=30 End_B1=30
1528 23:45:38.206592 31, 0xFFFF, End_B0=30 End_B1=30
1529 23:45:38.206652 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1530 23:45:38.206711 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
1531 23:45:38.206771
1532 23:45:38.206829
1533 23:45:38.206886 Write Rank0 MR23 =0x3f
1534 23:45:38.206943 [DQSOSC]
1535 23:45:38.207001 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1536 23:45:38.207060 CH0_RK0: MR19=0x303, MR18=0x1111, DQSOSC=401, MR23=63, INC=15, DEC=22
1537 23:45:38.207118 Write Rank0 MR23 =0x3f
1538 23:45:38.207176 [DQSOSC]
1539 23:45:38.207234 [DQSOSCAuto] RK0, (LSB)MR18= 0x1111, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1540 23:45:38.207292 CH0 RK0: MR19=303, MR18=1111
1541 23:45:38.207350 [RankSwap] Rank num 2, (Multi 1), Rank 1
1542 23:45:38.207418 Write Rank0 MR2 =0xad
1543 23:45:38.207478 [Write Leveling]
1544 23:45:38.207536 delay byte0 byte1 byte2 byte3
1545 23:45:38.207594
1546 23:45:38.207651 10 0 0
1547 23:45:38.207710 11 0 0
1548 23:45:38.207770 12 0 0
1549 23:45:38.207828 13 0 0
1550 23:45:38.207887 14 0 0
1551 23:45:38.207945 15 0 0
1552 23:45:38.208005 16 0 0
1553 23:45:38.208064 17 0 0
1554 23:45:38.208123 18 0 0
1555 23:45:38.208190 19 0 0
1556 23:45:38.208259 20 0 0
1557 23:45:38.208318 21 0 0
1558 23:45:38.208384 22 0 0
1559 23:45:38.208483 23 0 0
1560 23:45:38.208546 24 0 ff
1561 23:45:38.208626 25 ff ff
1562 23:45:38.208688 26 0 ff
1563 23:45:38.208749 27 ff ff
1564 23:45:38.208835 28 ff ff
1565 23:45:38.208897 29 ff ff
1566 23:45:38.208970 30 ff ff
1567 23:45:38.209059 31 ff ff
1568 23:45:38.209120 32 ff ff
1569 23:45:38.209202 33 ff ff
1570 23:45:38.209265 pass bytecount = 0xff (0xff: all bytes pass)
1571 23:45:38.209325
1572 23:45:38.209419 DQS0 dly: 27
1573 23:45:38.209511 DQS1 dly: 24
1574 23:45:38.209614 Write Rank0 MR2 =0x2d
1575 23:45:38.209707 [RankSwap] Rank num 2, (Multi 1), Rank 0
1576 23:45:38.209817 Write Rank1 MR1 =0xd6
1577 23:45:38.209910 [Gating]
1578 23:45:38.210012 ==
1579 23:45:38.210106 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1580 23:45:38.210205 fsp= 1, odt_onoff= 1, Byte mode= 0
1581 23:45:38.210268 ==
1582 23:45:38.210355 3 1 0 |2c2b 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1583 23:45:38.210418 3 1 4 |2c2b 3534 |(11 11)(11 11) |(0 0)(0 0)| 0
1584 23:45:38.210479 3 1 8 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1585 23:45:38.210585 3 1 12 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1586 23:45:38.210649 3 1 16 |2c2b 3534 |(11 11)(11 11) |(1 0)(1 1)| 0
1587 23:45:38.210720 3 1 20 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1588 23:45:38.210818 3 1 24 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1589 23:45:38.210914 3 1 28 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1590 23:45:38.211020 3 2 0 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1591 23:45:38.211123 3 2 4 |2c2b 3534 |(11 11)(11 11) |(1 0)(0 1)| 0
1592 23:45:38.211189 3 2 8 |302 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1593 23:45:38.211250 3 2 12 |3534 2928 |(11 11)(11 11) |(0 0)(1 1)| 0
1594 23:45:38.211335 3 2 16 |3534 2b2b |(11 11)(11 11) |(0 0)(1 1)| 0
1595 23:45:38.211440 3 2 20 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1596 23:45:38.211506 3 2 24 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1597 23:45:38.211567 3 2 28 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1598 23:45:38.211627 3 3 0 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1599 23:45:38.211687 3 3 4 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1600 23:45:38.211748 3 3 8 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1601 23:45:38.211808 3 3 12 |3534 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1602 23:45:38.211867 3 3 16 |3534 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
1603 23:45:38.211927 3 3 20 |3534 707 |(11 11)(11 11) |(0 0)(1 1)| 0
1604 23:45:38.211986 3 3 24 |3534 3534 |(11 11)(11 11) |(0 0)(1 1)| 0
1605 23:45:38.212046 [Byte 1] Lead/lag falling Transition (3, 3, 24)
1606 23:45:38.212105 3 3 28 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1607 23:45:38.212165 3 4 0 |3534 3534 |(11 11)(11 11) |(0 0)(0 1)| 0
1608 23:45:38.212225 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 1)| 0
1609 23:45:38.212285 3 4 8 |201 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
1610 23:45:38.212344 3 4 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
1611 23:45:38.212404 3 4 16 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
1612 23:45:38.212464 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1613 23:45:38.212522 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1614 23:45:38.212582 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1615 23:45:38.212668 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1616 23:45:38.212731 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1617 23:45:38.212792 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1618 23:45:38.212851 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1619 23:45:38.212930 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1620 23:45:38.212993 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1621 23:45:38.213054 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1622 23:45:38.213163 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1623 23:45:38.213228 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
1624 23:45:38.213293 [Byte 0] Lead/lag falling Transition (3, 6, 0)
1625 23:45:38.213354 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
1626 23:45:38.213414 [Byte 0] Lead/lag Transition tap number (2)
1627 23:45:38.213678 [Byte 1] Lead/lag falling Transition (3, 6, 4)
1628 23:45:38.213748 3 6 8 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
1629 23:45:38.213817 [Byte 1] Lead/lag Transition tap number (2)
1630 23:45:38.213893 3 6 12 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
1631 23:45:38.213955 [Byte 0]First pass (3, 6, 12)
1632 23:45:38.214029 3 6 16 |4646 1c1c |(0 0)(11 11) |(0 0)(0 0)| 0
1633 23:45:38.214117 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1634 23:45:38.214180 [Byte 1]First pass (3, 6, 20)
1635 23:45:38.214281 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1636 23:45:38.214377 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1637 23:45:38.214473 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1638 23:45:38.214567 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1639 23:45:38.214661 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1640 23:45:38.214755 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1641 23:45:38.214849 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1642 23:45:38.214943 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
1643 23:45:38.215037 All bytes gating window > 1UI, Early break!
1644 23:45:38.215127
1645 23:45:38.215218 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 4)
1646 23:45:38.215309
1647 23:45:38.215399 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
1648 23:45:38.215505
1649 23:45:38.215595
1650 23:45:38.215685
1651 23:45:38.215775 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 4)
1652 23:45:38.215865
1653 23:45:38.215955 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
1654 23:45:38.216045
1655 23:45:38.216134
1656 23:45:38.216224 Write Rank1 MR1 =0x56
1657 23:45:38.216314
1658 23:45:38.216404 best RODT dly(2T, 0.5T) = (2, 3)
1659 23:45:38.216476
1660 23:45:38.216535 best RODT dly(2T, 0.5T) = (2, 3)
1661 23:45:38.216593 ==
1662 23:45:38.216652 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1663 23:45:38.216710 fsp= 1, odt_onoff= 1, Byte mode= 0
1664 23:45:38.216769 ==
1665 23:45:38.216828 Start DQ dly to find pass range UseTestEngine =0
1666 23:45:38.216886 x-axis: bit #, y-axis: DQ dly (-127~63)
1667 23:45:38.216945 RX Vref Scan = 0
1668 23:45:38.217003 -26, [0] xxxxxxxx xxxxxxxx [MSB]
1669 23:45:38.217064 -25, [0] xxxxxxxx xxxxxxxx [MSB]
1670 23:45:38.217123 -24, [0] xxxxxxxx xxxxxxxx [MSB]
1671 23:45:38.217183 -23, [0] xxxxxxxx xxxxxxxx [MSB]
1672 23:45:38.217242 -22, [0] xxxxxxxx xxxxxxxx [MSB]
1673 23:45:38.217302 -21, [0] xxxxxxxx xxxxxxxx [MSB]
1674 23:45:38.217360 -20, [0] xxxxxxxx xxxxxxxx [MSB]
1675 23:45:38.217421 -19, [0] xxxxxxxx xxxxxxxx [MSB]
1676 23:45:38.217481 -18, [0] xxxxxxxx xxxxxxxx [MSB]
1677 23:45:38.217541 -17, [0] xxxxxxxx xxxxxxxx [MSB]
1678 23:45:38.217600 -16, [0] xxxxxxxx xxxxxxxx [MSB]
1679 23:45:38.217659 -15, [0] xxxxxxxx xxxxxxxx [MSB]
1680 23:45:38.217718 -14, [0] xxxxxxxx xxxxxxxx [MSB]
1681 23:45:38.217777 -13, [0] xxxxxxxx xxxxxxxx [MSB]
1682 23:45:38.217837 -12, [0] xxxxxxxx xxxxxxxx [MSB]
1683 23:45:38.217895 -11, [0] xxxxxxxx xxxxxxxx [MSB]
1684 23:45:38.217954 -10, [0] xxxxxxxx xxxxxxxx [MSB]
1685 23:45:38.218013 -9, [0] xxxxxxxx xxxxxxxx [MSB]
1686 23:45:38.218073 -8, [0] xxxxxxxx xxxxxxxx [MSB]
1687 23:45:38.218132 -7, [0] xxxxxxxx xxxxxxxx [MSB]
1688 23:45:38.218191 -6, [0] xxxxxxxx xxxxxxxx [MSB]
1689 23:45:38.218250 -5, [0] xxxxxxxx xxxxxxxx [MSB]
1690 23:45:38.218310 -4, [0] xxxxxxxx xxxxxxxx [MSB]
1691 23:45:38.218369 -3, [0] xxxxxxxx oxxoxxxx [MSB]
1692 23:45:38.218428 -2, [0] xxxxxxxx oxxoxxxx [MSB]
1693 23:45:38.218487 -1, [0] xxxoxxxx oxxoxxxx [MSB]
1694 23:45:38.218556 0, [0] xxxoxxxx ooxoxxxx [MSB]
1695 23:45:38.218619 1, [0] xxxoxoxx ooxooxxx [MSB]
1696 23:45:38.218678 2, [0] xxxoxooo ooxoooox [MSB]
1697 23:45:38.218738 3, [0] xxxooooo ooxoooox [MSB]
1698 23:45:38.218797 4, [0] xooooooo ooxoooox [MSB]
1699 23:45:38.218856 5, [0] oooooooo ooxoooox [MSB]
1700 23:45:38.218936 6, [0] oooooooo ooxooooo [MSB]
1701 23:45:38.218997 34, [0] oooooooo xooooooo [MSB]
1702 23:45:38.219058 35, [0] oooxoooo xooooooo [MSB]
1703 23:45:38.219142 36, [0] oooxoooo xooxoooo [MSB]
1704 23:45:38.219204 37, [0] oooxoxoo xxoxoxoo [MSB]
1705 23:45:38.219265 38, [0] oooxoxoo xxoxoxxo [MSB]
1706 23:45:38.219380 39, [0] oooxoxxx xxoxxxxo [MSB]
1707 23:45:38.219471 40, [0] oooxoxxx xxoxxxxo [MSB]
1708 23:45:38.219539 41, [0] oxxxxxxx xxoxxxxx [MSB]
1709 23:45:38.219599 42, [0] oxxxxxxx xxoxxxxx [MSB]
1710 23:45:38.219677 43, [0] xxxxxxxx xxoxxxxx [MSB]
1711 23:45:38.219741 44, [0] xxxxxxxx xxoxxxxx [MSB]
1712 23:45:38.219802 45, [0] xxxxxxxx xxxxxxxx [MSB]
1713 23:45:38.219875 iDelay=45, Bit 0, Center 23 (5 ~ 42) 38
1714 23:45:38.219960 iDelay=45, Bit 1, Center 22 (4 ~ 40) 37
1715 23:45:38.220022 iDelay=45, Bit 2, Center 22 (4 ~ 40) 37
1716 23:45:38.220085 iDelay=45, Bit 3, Center 16 (-1 ~ 34) 36
1717 23:45:38.220144 iDelay=45, Bit 4, Center 21 (3 ~ 40) 38
1718 23:45:38.220204 iDelay=45, Bit 5, Center 18 (1 ~ 36) 36
1719 23:45:38.220281 iDelay=45, Bit 6, Center 20 (2 ~ 38) 37
1720 23:45:38.220342 iDelay=45, Bit 7, Center 20 (2 ~ 38) 37
1721 23:45:38.220401 iDelay=45, Bit 8, Center 15 (-3 ~ 33) 37
1722 23:45:38.220505 iDelay=45, Bit 9, Center 18 (0 ~ 36) 37
1723 23:45:38.220570 iDelay=45, Bit 10, Center 25 (7 ~ 44) 38
1724 23:45:38.220644 iDelay=45, Bit 11, Center 16 (-3 ~ 35) 39
1725 23:45:38.220709 iDelay=45, Bit 12, Center 19 (1 ~ 38) 38
1726 23:45:38.220768 iDelay=45, Bit 13, Center 19 (2 ~ 36) 35
1727 23:45:38.220864 iDelay=45, Bit 14, Center 19 (2 ~ 37) 36
1728 23:45:38.220928 iDelay=45, Bit 15, Center 23 (6 ~ 40) 35
1729 23:45:38.220988 ==
1730 23:45:38.221091 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1731 23:45:38.221184 fsp= 1, odt_onoff= 1, Byte mode= 0
1732 23:45:38.221286 ==
1733 23:45:38.221379 DQS Delay:
1734 23:45:38.221480 DQS0 = 0, DQS1 = 0
1735 23:45:38.221574 DQM Delay:
1736 23:45:38.221671 DQM0 = 20, DQM1 = 19
1737 23:45:38.221764 DQ Delay:
1738 23:45:38.221859 DQ0 =23, DQ1 =22, DQ2 =22, DQ3 =16
1739 23:45:38.221951 DQ4 =21, DQ5 =18, DQ6 =20, DQ7 =20
1740 23:45:38.222044 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =16
1741 23:45:38.222135 DQ12 =19, DQ13 =19, DQ14 =19, DQ15 =23
1742 23:45:38.222229
1743 23:45:38.222319
1744 23:45:38.222416 DramC Write-DBI off
1745 23:45:38.222507 ==
1746 23:45:38.222606 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1747 23:45:38.222699 fsp= 1, odt_onoff= 1, Byte mode= 0
1748 23:45:38.222795 ==
1749 23:45:38.222888 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
1750 23:45:38.222985
1751 23:45:38.223076 Begin, DQ Scan Range 920~1176
1752 23:45:38.223170
1753 23:45:38.223260
1754 23:45:38.223358 TX Vref Scan disable
1755 23:45:38.223460 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
1756 23:45:38.223577 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
1757 23:45:38.223883 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
1758 23:45:38.224000 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
1759 23:45:38.224083 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
1760 23:45:38.224147 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
1761 23:45:38.224208 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
1762 23:45:38.224269 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
1763 23:45:38.224329 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
1764 23:45:38.224389 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
1765 23:45:38.224449 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
1766 23:45:38.224509 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
1767 23:45:38.224569 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
1768 23:45:38.224629 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
1769 23:45:38.224689 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
1770 23:45:38.224750 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
1771 23:45:38.224809 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
1772 23:45:38.224869 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
1773 23:45:38.224929 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
1774 23:45:38.224988 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
1775 23:45:38.225047 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
1776 23:45:38.225108 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
1777 23:45:38.225167 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
1778 23:45:38.225226 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
1779 23:45:38.225285 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
1780 23:45:38.225345 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
1781 23:45:38.225404 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
1782 23:45:38.225463 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
1783 23:45:38.225531 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
1784 23:45:38.225599 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
1785 23:45:38.225659 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
1786 23:45:38.225727 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
1787 23:45:38.225840 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
1788 23:45:38.225953 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
1789 23:45:38.226058 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
1790 23:45:38.226164 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
1791 23:45:38.226260 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
1792 23:45:38.226372 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
1793 23:45:38.226442 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
1794 23:45:38.226542 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
1795 23:45:38.226638 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
1796 23:45:38.226746 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
1797 23:45:38.226842 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
1798 23:45:38.226957 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
1799 23:45:38.227054 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
1800 23:45:38.227150 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
1801 23:45:38.227249 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
1802 23:45:38.227345 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
1803 23:45:38.227441 968 |3 6 8|[0] xxxxxxxx ooxoxxxx [MSB]
1804 23:45:38.227505 969 |3 6 9|[0] xxxxxxxx ooxooxxx [MSB]
1805 23:45:38.227565 970 |3 6 10|[0] xxxxxxxx ooxooxox [MSB]
1806 23:45:38.227632 971 |3 6 11|[0] xxxxxxxx ooxoooox [MSB]
1807 23:45:38.227702 972 |3 6 12|[0] xxxxxxxx ooxoooox [MSB]
1808 23:45:38.227762 973 |3 6 13|[0] xxxxxxxx ooxoooox [MSB]
1809 23:45:38.227822 974 |3 6 14|[0] xxxxxxxx ooxooooo [MSB]
1810 23:45:38.227907 975 |3 6 15|[0] xoxooooo oooooooo [MSB]
1811 23:45:38.227969 976 |3 6 16|[0] ooxooooo oooooooo [MSB]
1812 23:45:38.228042 987 |3 6 27|[0] oooooooo xooxoooo [MSB]
1813 23:45:38.228151 988 |3 6 28|[0] oooooooo xxxxxxxx [MSB]
1814 23:45:38.228256 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
1815 23:45:38.228353 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
1816 23:45:38.228447 991 |3 6 31|[0] oooxoooo xxxxxxxx [MSB]
1817 23:45:38.228511 992 |3 6 32|[0] oooxoxoo xxxxxxxx [MSB]
1818 23:45:38.228571 993 |3 6 33|[0] xxxxxxxx xxxxxxxx [MSB]
1819 23:45:38.228674 Byte0, DQ PI dly=983, DQM PI dly= 983
1820 23:45:38.228766 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 23)
1821 23:45:38.228878
1822 23:45:38.228971 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 23)
1823 23:45:38.229073
1824 23:45:38.229164 Byte1, DQ PI dly=979, DQM PI dly= 979
1825 23:45:38.229256 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
1826 23:45:38.229347
1827 23:45:38.229437 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
1828 23:45:38.229528
1829 23:45:38.229618 ==
1830 23:45:38.229710 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
1831 23:45:38.229802 fsp= 1, odt_onoff= 1, Byte mode= 0
1832 23:45:38.229893 ==
1833 23:45:38.229990 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
1834 23:45:38.230087
1835 23:45:38.230178 Begin, DQ Scan Range 955~1019
1836 23:45:38.230269 Write Rank1 MR14 =0x0
1837 23:45:38.230360
1838 23:45:38.230450 CH=0, VrefRange= 0, VrefLevel = 0
1839 23:45:38.230542 TX Bit0 (978~991) 14 984, Bit8 (969~982) 14 975,
1840 23:45:38.230633 TX Bit1 (977~989) 13 983, Bit9 (971~984) 14 977,
1841 23:45:38.230725 TX Bit2 (978~990) 13 984, Bit10 (977~983) 7 980,
1842 23:45:38.230817 TX Bit3 (972~983) 12 977, Bit11 (971~983) 13 977,
1843 23:45:38.230909 TX Bit4 (977~990) 14 983, Bit12 (973~983) 11 978,
1844 23:45:38.231000 TX Bit5 (974~986) 13 980, Bit13 (975~983) 9 979,
1845 23:45:38.231092 TX Bit6 (975~988) 14 981, Bit14 (974~983) 10 978,
1846 23:45:38.231184 TX Bit7 (977~990) 14 983, Bit15 (976~983) 8 979,
1847 23:45:38.231274
1848 23:45:38.231364 Write Rank1 MR14 =0x2
1849 23:45:38.231449
1850 23:45:38.231510 CH=0, VrefRange= 0, VrefLevel = 2
1851 23:45:38.231569 TX Bit0 (978~992) 15 985, Bit8 (969~983) 15 976,
1852 23:45:38.231629 TX Bit1 (977~990) 14 983, Bit9 (971~985) 15 978,
1853 23:45:38.231688 TX Bit2 (978~991) 14 984, Bit10 (976~990) 15 983,
1854 23:45:38.231747 TX Bit3 (971~984) 14 977, Bit11 (970~983) 14 976,
1855 23:45:38.231806 TX Bit4 (976~990) 15 983, Bit12 (973~985) 13 979,
1856 23:45:38.231865 TX Bit5 (974~986) 13 980, Bit13 (974~983) 10 978,
1857 23:45:38.231924 TX Bit6 (975~989) 15 982, Bit14 (973~985) 13 979,
1858 23:45:38.231983 TX Bit7 (976~990) 15 983, Bit15 (976~989) 14 982,
1859 23:45:38.232041
1860 23:45:38.232099 Write Rank1 MR14 =0x4
1861 23:45:38.232157
1862 23:45:38.232215 CH=0, VrefRange= 0, VrefLevel = 4
1863 23:45:38.232273 TX Bit0 (977~992) 16 984, Bit8 (969~983) 15 976,
1864 23:45:38.232529 TX Bit1 (977~991) 15 984, Bit9 (971~985) 15 978,
1865 23:45:38.232595 TX Bit2 (978~991) 14 984, Bit10 (977~990) 14 983,
1866 23:45:38.232655 TX Bit3 (971~984) 14 977, Bit11 (969~983) 15 976,
1867 23:45:38.232715 TX Bit4 (976~991) 16 983, Bit12 (972~986) 15 979,
1868 23:45:38.232775 TX Bit5 (973~988) 16 980, Bit13 (973~984) 12 978,
1869 23:45:38.232835 TX Bit6 (975~990) 16 982, Bit14 (973~986) 14 979,
1870 23:45:38.232893 TX Bit7 (976~991) 16 983, Bit15 (975~990) 16 982,
1871 23:45:38.232952
1872 23:45:38.233009 Write Rank1 MR14 =0x6
1873 23:45:38.233068
1874 23:45:38.233126 CH=0, VrefRange= 0, VrefLevel = 6
1875 23:45:38.233184 TX Bit0 (977~993) 17 985, Bit8 (968~984) 17 976,
1876 23:45:38.233244 TX Bit1 (977~991) 15 984, Bit9 (970~986) 17 978,
1877 23:45:38.233302 TX Bit2 (978~991) 14 984, Bit10 (976~991) 16 983,
1878 23:45:38.233361 TX Bit3 (970~985) 16 977, Bit11 (969~984) 16 976,
1879 23:45:38.233420 TX Bit4 (976~991) 16 983, Bit12 (971~986) 16 978,
1880 23:45:38.233479 TX Bit5 (973~989) 17 981, Bit13 (973~985) 13 979,
1881 23:45:38.233537 TX Bit6 (974~990) 17 982, Bit14 (972~987) 16 979,
1882 23:45:38.233596 TX Bit7 (975~991) 17 983, Bit15 (975~991) 17 983,
1883 23:45:38.233653
1884 23:45:38.233711 Write Rank1 MR14 =0x8
1885 23:45:38.233770
1886 23:45:38.233827 CH=0, VrefRange= 0, VrefLevel = 8
1887 23:45:38.233886 TX Bit0 (977~993) 17 985, Bit8 (969~984) 16 976,
1888 23:45:38.233944 TX Bit1 (976~991) 16 983, Bit9 (969~987) 19 978,
1889 23:45:38.234002 TX Bit2 (977~992) 16 984, Bit10 (976~991) 16 983,
1890 23:45:38.234061 TX Bit3 (970~986) 17 978, Bit11 (969~984) 16 976,
1891 23:45:38.234119 TX Bit4 (975~991) 17 983, Bit12 (971~987) 17 979,
1892 23:45:38.234177 TX Bit5 (972~990) 19 981, Bit13 (972~985) 14 978,
1893 23:45:38.234235 TX Bit6 (974~991) 18 982, Bit14 (971~988) 18 979,
1894 23:45:38.234294 TX Bit7 (975~992) 18 983, Bit15 (975~991) 17 983,
1895 23:45:38.234373
1896 23:45:38.234433 Write Rank1 MR14 =0xa
1897 23:45:38.234492
1898 23:45:38.234590 CH=0, VrefRange= 0, VrefLevel = 10
1899 23:45:38.234655 TX Bit0 (977~994) 18 985, Bit8 (968~985) 18 976,
1900 23:45:38.234717 TX Bit1 (976~992) 17 984, Bit9 (969~988) 20 978,
1901 23:45:38.234777 TX Bit2 (977~992) 16 984, Bit10 (975~992) 18 983,
1902 23:45:38.234836 TX Bit3 (970~987) 18 978, Bit11 (969~985) 17 977,
1903 23:45:38.234895 TX Bit4 (975~992) 18 983, Bit12 (971~988) 18 979,
1904 23:45:38.234955 TX Bit5 (972~990) 19 981, Bit13 (972~985) 14 978,
1905 23:45:38.235043 TX Bit6 (974~991) 18 982, Bit14 (971~989) 19 980,
1906 23:45:38.235136 TX Bit7 (975~992) 18 983, Bit15 (975~991) 17 983,
1907 23:45:38.235241
1908 23:45:38.235334 Write Rank1 MR14 =0xc
1909 23:45:38.235458
1910 23:45:38.235525 CH=0, VrefRange= 0, VrefLevel = 12
1911 23:45:38.235605 TX Bit0 (977~994) 18 985, Bit8 (968~985) 18 976,
1912 23:45:38.235669 TX Bit1 (976~992) 17 984, Bit9 (969~989) 21 979,
1913 23:45:38.235728 TX Bit2 (977~993) 17 985, Bit10 (975~992) 18 983,
1914 23:45:38.235824 TX Bit3 (970~988) 19 979, Bit11 (968~986) 19 977,
1915 23:45:38.235889 TX Bit4 (975~992) 18 983, Bit12 (970~989) 20 979,
1916 23:45:38.235948 TX Bit5 (972~990) 19 981, Bit13 (972~986) 15 979,
1917 23:45:38.236027 TX Bit6 (973~991) 19 982, Bit14 (971~990) 20 980,
1918 23:45:38.236088 TX Bit7 (974~992) 19 983, Bit15 (975~992) 18 983,
1919 23:45:38.236150
1920 23:45:38.236209 Write Rank1 MR14 =0xe
1921 23:45:38.236267
1922 23:45:38.236325 CH=0, VrefRange= 0, VrefLevel = 14
1923 23:45:38.236383 TX Bit0 (976~995) 20 985, Bit8 (968~985) 18 976,
1924 23:45:38.236442 TX Bit1 (976~993) 18 984, Bit9 (969~989) 21 979,
1925 23:45:38.236519 TX Bit2 (977~994) 18 985, Bit10 (975~992) 18 983,
1926 23:45:38.236580 TX Bit3 (969~989) 21 979, Bit11 (968~986) 19 977,
1927 23:45:38.236640 TX Bit4 (975~993) 19 984, Bit12 (970~990) 21 980,
1928 23:45:38.236725 TX Bit5 (971~991) 21 981, Bit13 (971~987) 17 979,
1929 23:45:38.236787 TX Bit6 (973~992) 20 982, Bit14 (971~990) 20 980,
1930 23:45:38.236848 TX Bit7 (974~993) 20 983, Bit15 (974~992) 19 983,
1931 23:45:38.236959
1932 23:45:38.237054 Write Rank1 MR14 =0x10
1933 23:45:38.237155
1934 23:45:38.237253 CH=0, VrefRange= 0, VrefLevel = 16
1935 23:45:38.237359 TX Bit0 (976~996) 21 986, Bit8 (967~986) 20 976,
1936 23:45:38.237461 TX Bit1 (975~993) 19 984, Bit9 (969~990) 22 979,
1937 23:45:38.237568 TX Bit2 (976~994) 19 985, Bit10 (975~993) 19 984,
1938 23:45:38.237670 TX Bit3 (969~989) 21 979, Bit11 (968~987) 20 977,
1939 23:45:38.237764 TX Bit4 (974~993) 20 983, Bit12 (969~990) 22 979,
1940 23:45:38.237872 TX Bit5 (971~991) 21 981, Bit13 (970~988) 19 979,
1941 23:45:38.237977 TX Bit6 (972~992) 21 982, Bit14 (970~990) 21 980,
1942 23:45:38.238069 TX Bit7 (974~993) 20 983, Bit15 (974~992) 19 983,
1943 23:45:38.238167
1944 23:45:38.238258 Write Rank1 MR14 =0x12
1945 23:45:38.238362
1946 23:45:38.238454 CH=0, VrefRange= 0, VrefLevel = 18
1947 23:45:38.238521 TX Bit0 (976~997) 22 986, Bit8 (967~987) 21 977,
1948 23:45:38.238582 TX Bit1 (975~994) 20 984, Bit9 (968~990) 23 979,
1949 23:45:38.238641 TX Bit2 (977~995) 19 986, Bit10 (975~993) 19 984,
1950 23:45:38.238701 TX Bit3 (969~990) 22 979, Bit11 (968~988) 21 978,
1951 23:45:38.238760 TX Bit4 (974~994) 21 984, Bit12 (969~990) 22 979,
1952 23:45:38.238822 TX Bit5 (970~992) 23 981, Bit13 (970~989) 20 979,
1953 23:45:38.238921 TX Bit6 (972~993) 22 982, Bit14 (970~990) 21 980,
1954 23:45:38.239014 TX Bit7 (973~994) 22 983, Bit15 (974~993) 20 983,
1955 23:45:38.239105
1956 23:45:38.239195 Write Rank1 MR14 =0x14
1957 23:45:38.239286
1958 23:45:38.239376 CH=0, VrefRange= 0, VrefLevel = 20
1959 23:45:38.239467 TX Bit0 (976~997) 22 986, Bit8 (967~988) 22 977,
1960 23:45:38.239528 TX Bit1 (974~994) 21 984, Bit9 (969~990) 22 979,
1961 23:45:38.239588 TX Bit2 (976~995) 20 985, Bit10 (974~994) 21 984,
1962 23:45:38.239646 TX Bit3 (969~990) 22 979, Bit11 (968~988) 21 978,
1963 23:45:38.239705 TX Bit4 (973~995) 23 984, Bit12 (969~991) 23 980,
1964 23:45:38.239968 TX Bit5 (970~992) 23 981, Bit13 (970~989) 20 979,
1965 23:45:38.240037 TX Bit6 (971~993) 23 982, Bit14 (969~991) 23 980,
1966 23:45:38.240097 TX Bit7 (973~995) 23 984, Bit15 (974~993) 20 983,
1967 23:45:38.240157
1968 23:45:38.240216 Write Rank1 MR14 =0x16
1969 23:45:38.240275
1970 23:45:38.240333 CH=0, VrefRange= 0, VrefLevel = 22
1971 23:45:38.240392 TX Bit0 (976~997) 22 986, Bit8 (967~989) 23 978,
1972 23:45:38.240451 TX Bit1 (974~995) 22 984, Bit9 (968~991) 24 979,
1973 23:45:38.240509 TX Bit2 (976~996) 21 986, Bit10 (974~995) 22 984,
1974 23:45:38.240568 TX Bit3 (969~990) 22 979, Bit11 (967~989) 23 978,
1975 23:45:38.240627 TX Bit4 (973~995) 23 984, Bit12 (969~991) 23 980,
1976 23:45:38.376629 TX Bit5 (970~992) 23 981, Bit13 (970~990) 21 980,
1977 23:45:38.376947 TX Bit6 (971~994) 24 982, Bit14 (969~991) 23 980,
1978 23:45:38.377165 TX Bit7 (972~995) 24 983, Bit15 (973~994) 22 983,
1979 23:45:38.377335
1980 23:45:38.377496 Write Rank1 MR14 =0x18
1981 23:45:38.377653
1982 23:45:38.377806 CH=0, VrefRange= 0, VrefLevel = 24
1983 23:45:38.377958 TX Bit0 (975~998) 24 986, Bit8 (967~990) 24 978,
1984 23:45:38.378110 TX Bit1 (974~996) 23 985, Bit9 (968~991) 24 979,
1985 23:45:38.378259 TX Bit2 (976~997) 22 986, Bit10 (973~994) 22 983,
1986 23:45:38.378408 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
1987 23:45:38.378555 TX Bit4 (973~996) 24 984, Bit12 (969~991) 23 980,
1988 23:45:38.378704 TX Bit5 (970~993) 24 981, Bit13 (969~990) 22 979,
1989 23:45:38.378851 TX Bit6 (971~994) 24 982, Bit14 (969~991) 23 980,
1990 23:45:38.378998 TX Bit7 (972~996) 25 984, Bit15 (972~995) 24 983,
1991 23:45:38.379143
1992 23:45:38.379289 Write Rank1 MR14 =0x1a
1993 23:45:38.379499
1994 23:45:38.379656 CH=0, VrefRange= 0, VrefLevel = 26
1995 23:45:38.379804 TX Bit0 (975~998) 24 986, Bit8 (966~990) 25 978,
1996 23:45:38.379950 TX Bit1 (974~996) 23 985, Bit9 (968~991) 24 979,
1997 23:45:38.380098 TX Bit2 (975~997) 23 986, Bit10 (973~997) 25 985,
1998 23:45:38.380245 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
1999 23:45:38.380390 TX Bit4 (972~997) 26 984, Bit12 (969~992) 24 980,
2000 23:45:38.380535 TX Bit5 (970~993) 24 981, Bit13 (969~990) 22 979,
2001 23:45:38.380681 TX Bit6 (971~994) 24 982, Bit14 (969~992) 24 980,
2002 23:45:38.380827 TX Bit7 (971~997) 27 984, Bit15 (972~995) 24 983,
2003 23:45:38.380972
2004 23:45:38.381115 Write Rank1 MR14 =0x1c
2005 23:45:38.381259
2006 23:45:38.381402 CH=0, VrefRange= 0, VrefLevel = 28
2007 23:45:38.381547 TX Bit0 (975~998) 24 986, Bit8 (966~990) 25 978,
2008 23:45:38.381695 TX Bit1 (973~997) 25 985, Bit9 (968~991) 24 979,
2009 23:45:38.381840 TX Bit2 (975~998) 24 986, Bit10 (972~996) 25 984,
2010 23:45:38.381987 TX Bit3 (968~991) 24 979, Bit11 (967~990) 24 978,
2011 23:45:38.382133 TX Bit4 (972~997) 26 984, Bit12 (968~992) 25 980,
2012 23:45:38.382279 TX Bit5 (969~993) 25 981, Bit13 (969~991) 23 980,
2013 23:45:38.382426 TX Bit6 (970~995) 26 982, Bit14 (969~992) 24 980,
2014 23:45:38.382572 TX Bit7 (971~997) 27 984, Bit15 (971~996) 26 983,
2015 23:45:38.382718
2016 23:45:38.382860 Write Rank1 MR14 =0x1e
2017 23:45:38.383005
2018 23:45:38.383148 CH=0, VrefRange= 0, VrefLevel = 30
2019 23:45:38.383294 TX Bit0 (974~998) 25 986, Bit8 (966~990) 25 978,
2020 23:45:38.383462 TX Bit1 (973~997) 25 985, Bit9 (968~991) 24 979,
2021 23:45:38.383612 TX Bit2 (975~998) 24 986, Bit10 (972~997) 26 984,
2022 23:45:38.383758 TX Bit3 (968~992) 25 980, Bit11 (967~990) 24 978,
2023 23:45:38.383903 TX Bit4 (971~997) 27 984, Bit12 (968~992) 25 980,
2024 23:45:38.384048 TX Bit5 (969~994) 26 981, Bit13 (969~991) 23 980,
2025 23:45:38.384192 TX Bit6 (970~996) 27 983, Bit14 (968~992) 25 980,
2026 23:45:38.384338 TX Bit7 (971~997) 27 984, Bit15 (971~996) 26 983,
2027 23:45:38.384482
2028 23:45:38.384625 Write Rank1 MR14 =0x20
2029 23:45:38.384768
2030 23:45:38.384912 CH=0, VrefRange= 0, VrefLevel = 32
2031 23:45:38.385058 TX Bit0 (974~999) 26 986, Bit8 (966~990) 25 978,
2032 23:45:38.385204 TX Bit1 (973~998) 26 985, Bit9 (968~990) 23 979,
2033 23:45:38.385349 TX Bit2 (975~998) 24 986, Bit10 (972~997) 26 984,
2034 23:45:38.385494 TX Bit3 (968~992) 25 980, Bit11 (967~990) 24 978,
2035 23:45:38.385639 TX Bit4 (971~998) 28 984, Bit12 (968~992) 25 980,
2036 23:45:38.385783 TX Bit5 (969~994) 26 981, Bit13 (969~991) 23 980,
2037 23:45:38.385929 TX Bit6 (970~996) 27 983, Bit14 (968~992) 25 980,
2038 23:45:38.386075 TX Bit7 (972~998) 27 985, Bit15 (970~995) 26 982,
2039 23:45:38.386220
2040 23:45:38.386365 Write Rank1 MR14 =0x22
2041 23:45:38.386509
2042 23:45:38.386652 CH=0, VrefRange= 0, VrefLevel = 34
2043 23:45:38.386798 TX Bit0 (974~999) 26 986, Bit8 (966~990) 25 978,
2044 23:45:38.386942 TX Bit1 (973~998) 26 985, Bit9 (968~990) 23 979,
2045 23:45:38.387088 TX Bit2 (975~998) 24 986, Bit10 (972~997) 26 984,
2046 23:45:38.387232 TX Bit3 (968~992) 25 980, Bit11 (967~990) 24 978,
2047 23:45:38.387377 TX Bit4 (971~998) 28 984, Bit12 (968~992) 25 980,
2048 23:45:38.387552 TX Bit5 (969~994) 26 981, Bit13 (969~991) 23 980,
2049 23:45:38.387700 TX Bit6 (970~996) 27 983, Bit14 (968~992) 25 980,
2050 23:45:38.387845 TX Bit7 (972~998) 27 985, Bit15 (970~995) 26 982,
2051 23:45:38.387990
2052 23:45:38.388132 Write Rank1 MR14 =0x24
2053 23:45:38.388287
2054 23:45:38.388469 CH=0, VrefRange= 0, VrefLevel = 36
2055 23:45:38.388623 TX Bit0 (974~999) 26 986, Bit8 (966~990) 25 978,
2056 23:45:38.388783 TX Bit1 (973~998) 26 985, Bit9 (968~990) 23 979,
2057 23:45:38.388965 TX Bit2 (975~998) 24 986, Bit10 (972~997) 26 984,
2058 23:45:38.389214 TX Bit3 (968~992) 25 980, Bit11 (967~990) 24 978,
2059 23:45:38.389443 TX Bit4 (971~998) 28 984, Bit12 (968~992) 25 980,
2060 23:45:38.389669 TX Bit5 (969~994) 26 981, Bit13 (969~991) 23 980,
2061 23:45:38.389894 TX Bit6 (970~996) 27 983, Bit14 (968~992) 25 980,
2062 23:45:38.390119 TX Bit7 (972~998) 27 985, Bit15 (970~995) 26 982,
2063 23:45:38.390340
2064 23:45:38.390561 Write Rank1 MR14 =0x26
2065 23:45:38.390794
2066 23:45:38.391020 CH=0, VrefRange= 0, VrefLevel = 38
2067 23:45:38.391528 TX Bit0 (974~999) 26 986, Bit8 (966~990) 25 978,
2068 23:45:38.391701 TX Bit1 (973~998) 26 985, Bit9 (968~990) 23 979,
2069 23:45:38.391852 TX Bit2 (975~998) 24 986, Bit10 (972~997) 26 984,
2070 23:45:38.391999 TX Bit3 (968~992) 25 980, Bit11 (967~990) 24 978,
2071 23:45:38.392146 TX Bit4 (971~998) 28 984, Bit12 (968~992) 25 980,
2072 23:45:38.392291 TX Bit5 (969~994) 26 981, Bit13 (969~991) 23 980,
2073 23:45:38.392437 TX Bit6 (970~996) 27 983, Bit14 (968~992) 25 980,
2074 23:45:38.392582 TX Bit7 (972~998) 27 985, Bit15 (970~995) 26 982,
2075 23:45:38.392727
2076 23:45:38.392881
2077 23:45:38.393102 TX Vref found, early break! 381< 385
2078 23:45:38.393348 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2079 23:45:38.393568 u1DelayCellOfst[0]=7 cells (6 PI)
2080 23:45:38.393773 u1DelayCellOfst[1]=6 cells (5 PI)
2081 23:45:38.393939 u1DelayCellOfst[2]=7 cells (6 PI)
2082 23:45:38.394086 u1DelayCellOfst[3]=0 cells (0 PI)
2083 23:45:38.394232 u1DelayCellOfst[4]=5 cells (4 PI)
2084 23:45:38.394374 u1DelayCellOfst[5]=1 cells (1 PI)
2085 23:45:38.394518 u1DelayCellOfst[6]=3 cells (3 PI)
2086 23:45:38.394661 u1DelayCellOfst[7]=6 cells (5 PI)
2087 23:45:38.394804 Byte0, DQ PI dly=980, DQM PI dly= 983
2088 23:45:38.394949 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 20)
2089 23:45:38.395095
2090 23:45:38.395236 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 20)
2091 23:45:38.395383
2092 23:45:38.395549 u1DelayCellOfst[8]=0 cells (0 PI)
2093 23:45:38.395696 u1DelayCellOfst[9]=1 cells (1 PI)
2094 23:45:38.395841 u1DelayCellOfst[10]=7 cells (6 PI)
2095 23:45:38.395985 u1DelayCellOfst[11]=0 cells (0 PI)
2096 23:45:38.396128 u1DelayCellOfst[12]=2 cells (2 PI)
2097 23:45:38.396270 u1DelayCellOfst[13]=2 cells (2 PI)
2098 23:45:38.396413 u1DelayCellOfst[14]=2 cells (2 PI)
2099 23:45:38.396555 u1DelayCellOfst[15]=5 cells (4 PI)
2100 23:45:38.396698 Byte1, DQ PI dly=978, DQM PI dly= 981
2101 23:45:38.396844 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
2102 23:45:38.396989
2103 23:45:38.397134 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
2104 23:45:38.397279
2105 23:45:38.397424 Write Rank1 MR14 =0x20
2106 23:45:38.397570
2107 23:45:38.397720 Final TX Range 0 Vref 32
2108 23:45:38.397865
2109 23:45:38.398008 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2110 23:45:38.398155
2111 23:45:38.398299 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2112 23:45:38.398445 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2113 23:45:38.398591 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2114 23:45:38.398737 Write Rank1 MR3 =0xb0
2115 23:45:38.398881 DramC Write-DBI on
2116 23:45:38.399026 ==
2117 23:45:38.399170 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2118 23:45:38.399316 fsp= 1, odt_onoff= 1, Byte mode= 0
2119 23:45:38.399485 ==
2120 23:45:38.399633 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2121 23:45:38.399780
2122 23:45:38.399924 Begin, DQ Scan Range 701~765
2123 23:45:38.400068
2124 23:45:38.400212
2125 23:45:38.400355 TX Vref Scan disable
2126 23:45:38.400501 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2127 23:45:38.400651 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2128 23:45:38.400799 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2129 23:45:38.400946 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2130 23:45:38.401096 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2131 23:45:38.401244 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2132 23:45:38.401391 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2133 23:45:38.401539 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2134 23:45:38.401688 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2135 23:45:38.401837 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2136 23:45:38.401985 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
2137 23:45:38.402132 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
2138 23:45:38.402279 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
2139 23:45:38.402427 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
2140 23:45:38.402575 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
2141 23:45:38.402725 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
2142 23:45:38.402843 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
2143 23:45:38.402961 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
2144 23:45:38.403081 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
2145 23:45:38.403200 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
2146 23:45:38.403319 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
2147 23:45:38.403455 743 |2 6 39|[0] xxxxxxxx xxxxxxxx [MSB]
2148 23:45:38.403580 Byte0, DQ PI dly=728, DQM PI dly= 728
2149 23:45:38.403698 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 24)
2150 23:45:38.403815
2151 23:45:38.403932 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 24)
2152 23:45:38.404049
2153 23:45:38.404165 Byte1, DQ PI dly=723, DQM PI dly= 723
2154 23:45:38.404282 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
2155 23:45:38.404399
2156 23:45:38.404515 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
2157 23:45:38.404631
2158 23:45:38.404747 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
2159 23:45:38.404865 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2160 23:45:38.404983 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2161 23:45:38.405099 Write Rank1 MR3 =0x30
2162 23:45:38.405216 DramC Write-DBI off
2163 23:45:38.405331
2164 23:45:38.405447 [DATLAT]
2165 23:45:38.405562 Freq=1600, CH0 RK1, use_rxtx_scan=0
2166 23:45:38.405679
2167 23:45:38.405794 DATLAT Default: 0x10
2168 23:45:38.405910 7, 0xFFFF, sum=0
2169 23:45:38.406029 8, 0xFFFF, sum=0
2170 23:45:38.406147 9, 0xFFFF, sum=0
2171 23:45:38.406264 10, 0xFFFF, sum=0
2172 23:45:38.406382 11, 0xFFFF, sum=0
2173 23:45:38.406501 12, 0xFFFF, sum=0
2174 23:45:38.406618 13, 0xFFFF, sum=0
2175 23:45:38.406736 14, 0x0, sum=1
2176 23:45:38.406854 15, 0x0, sum=2
2177 23:45:38.406972 16, 0x0, sum=3
2178 23:45:38.407090 17, 0x0, sum=4
2179 23:45:38.407207 pattern=2 first_step=14 total pass=5 best_step=16
2180 23:45:38.407324 ==
2181 23:45:38.407461 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2182 23:45:38.407583 fsp= 1, odt_onoff= 1, Byte mode= 0
2183 23:45:38.407704 ==
2184 23:45:38.407801 Start DQ dly to find pass range UseTestEngine =1
2185 23:45:38.407899 x-axis: bit #, y-axis: DQ dly (-127~63)
2186 23:45:38.408003 RX Vref Scan = 0
2187 23:45:38.408101 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2188 23:45:38.408201 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2189 23:45:38.408301 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2190 23:45:38.408625 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2191 23:45:38.408738 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2192 23:45:38.408840 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2193 23:45:38.408941 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2194 23:45:38.409042 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2195 23:45:38.409142 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2196 23:45:38.409242 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2197 23:45:38.409342 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2198 23:45:38.409441 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2199 23:45:38.409540 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2200 23:45:38.409640 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2201 23:45:38.409740 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2202 23:45:38.409839 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2203 23:45:38.409938 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2204 23:45:38.410037 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2205 23:45:38.410137 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2206 23:45:38.410236 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2207 23:45:38.410335 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2208 23:45:38.410447 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2209 23:45:38.410552 -4, [0] xxxxxxxx xxxxxxxx [MSB]
2210 23:45:38.410651 -3, [0] xxxxxxxx xxxxxxxx [MSB]
2211 23:45:38.410750 -2, [0] xxxoxxxx oxxoxxxx [MSB]
2212 23:45:38.410849 -1, [0] xxxoxxxx oxxoxxxx [MSB]
2213 23:45:38.410948 0, [0] xxxoxxxx oxxoxxxx [MSB]
2214 23:45:38.411048 1, [0] xxxoxxxx ooxooxxx [MSB]
2215 23:45:38.411148 2, [0] xxxoxoxx ooxoooox [MSB]
2216 23:45:38.411248 3, [0] xxxoxooo ooxoooox [MSB]
2217 23:45:38.411347 4, [0] xxxoxooo ooxoooox [MSB]
2218 23:45:38.411478 5, [0] xoxooooo ooxoooox [MSB]
2219 23:45:38.411655 6, [0] oooooooo ooxooooo [MSB]
2220 23:45:38.411805 33, [0] oooooooo xooooooo [MSB]
2221 23:45:38.411910 34, [0] oooooooo xooooooo [MSB]
2222 23:45:38.412011 35, [0] oooxoxoo xooxoxoo [MSB]
2223 23:45:38.412111 36, [0] oooxoxoo xooxoxoo [MSB]
2224 23:45:38.412210 37, [0] oooxoxxo xxoxoxoo [MSB]
2225 23:45:38.412310 38, [0] oooxoxxo xxoxxxoo [MSB]
2226 23:45:38.412410 39, [0] oxxxxxxx xxoxxxxo [MSB]
2227 23:45:38.412510 40, [0] oxxxxxxx xxoxxxxx [MSB]
2228 23:45:38.412609 41, [0] xxxxxxxx xxoxxxxx [MSB]
2229 23:45:38.412714 42, [0] xxxxxxxx xxoxxxxx [MSB]
2230 23:45:38.412814 43, [0] xxxxxxxx xxoxxxxx [MSB]
2231 23:45:38.412905 44, [0] xxxxxxxx xxxxxxxx [MSB]
2232 23:45:38.412991 iDelay=44, Bit 0, Center 23 (6 ~ 40) 35
2233 23:45:38.413075 iDelay=44, Bit 1, Center 21 (5 ~ 38) 34
2234 23:45:38.413160 iDelay=44, Bit 2, Center 22 (6 ~ 38) 33
2235 23:45:38.413243 iDelay=44, Bit 3, Center 16 (-2 ~ 34) 37
2236 23:45:38.413327 iDelay=44, Bit 4, Center 21 (5 ~ 38) 34
2237 23:45:38.413410 iDelay=44, Bit 5, Center 18 (2 ~ 34) 33
2238 23:45:38.413494 iDelay=44, Bit 6, Center 19 (3 ~ 36) 34
2239 23:45:38.413577 iDelay=44, Bit 7, Center 20 (3 ~ 38) 36
2240 23:45:38.413659 iDelay=44, Bit 8, Center 15 (-2 ~ 32) 35
2241 23:45:38.413742 iDelay=44, Bit 9, Center 18 (1 ~ 36) 36
2242 23:45:38.413826 iDelay=44, Bit 10, Center 25 (7 ~ 43) 37
2243 23:45:38.413910 iDelay=44, Bit 11, Center 16 (-2 ~ 34) 37
2244 23:45:38.413994 iDelay=44, Bit 12, Center 19 (1 ~ 37) 37
2245 23:45:38.414078 iDelay=44, Bit 13, Center 18 (2 ~ 34) 33
2246 23:45:38.414161 iDelay=44, Bit 14, Center 20 (2 ~ 38) 37
2247 23:45:38.414245 iDelay=44, Bit 15, Center 22 (6 ~ 39) 34
2248 23:45:38.414329 ==
2249 23:45:38.414412 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_0, rank 1
2250 23:45:38.414497 fsp= 1, odt_onoff= 1, Byte mode= 0
2251 23:45:38.414581 ==
2252 23:45:38.414665 DQS Delay:
2253 23:45:38.414748 DQS0 = 0, DQS1 = 0
2254 23:45:38.414831 DQM Delay:
2255 23:45:38.414915 DQM0 = 20, DQM1 = 19
2256 23:45:38.414998 DQ Delay:
2257 23:45:38.415081 DQ0 =23, DQ1 =21, DQ2 =22, DQ3 =16
2258 23:45:38.415166 DQ4 =21, DQ5 =18, DQ6 =19, DQ7 =20
2259 23:45:38.415272 DQ8 =15, DQ9 =18, DQ10 =25, DQ11 =16
2260 23:45:38.415362 DQ12 =19, DQ13 =18, DQ14 =20, DQ15 =22
2261 23:45:38.415462
2262 23:45:38.415546
2263 23:45:38.415629
2264 23:45:38.415931 [DramC_TX_OE_Calibration] TA2
2265 23:45:38.419328 Original DQ_B0 (3 6) =30, OEN = 27
2266 23:45:38.422391 Original DQ_B1 (3 6) =30, OEN = 27
2267 23:45:38.425947 23, 0x0, End_B0=23 End_B1=23
2268 23:45:38.426062 24, 0x0, End_B0=24 End_B1=24
2269 23:45:38.429463 25, 0x0, End_B0=25 End_B1=25
2270 23:45:38.432781 26, 0x0, End_B0=26 End_B1=26
2271 23:45:38.435877 27, 0x0, End_B0=27 End_B1=27
2272 23:45:38.439281 28, 0x0, End_B0=28 End_B1=28
2273 23:45:38.439396 29, 0x0, End_B0=29 End_B1=29
2274 23:45:38.442739 30, 0x0, End_B0=30 End_B1=30
2275 23:45:38.445945 31, 0xFFFF, End_B0=30 End_B1=30
2276 23:45:38.452686 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2277 23:45:38.456064 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
2278 23:45:38.456179
2279 23:45:38.456268
2280 23:45:38.459711 Write Rank1 MR23 =0x3f
2281 23:45:38.459868 [DQSOSC]
2282 23:45:38.469227 [DQSOSCAuto] RK1, (LSB)MR18= 0xdada, (MSB)MR19= 0x202, tDQSOscB0 = 431 ps tDQSOscB1 = 431 ps
2283 23:45:38.476111 CH0_RK1: MR19=0x202, MR18=0xDADA, DQSOSC=431, MR23=63, INC=13, DEC=19
2284 23:45:38.476273 Write Rank1 MR23 =0x3f
2285 23:45:38.476406 [DQSOSC]
2286 23:45:38.485710 [DQSOSCAuto] RK1, (LSB)MR18= 0xd8d8, (MSB)MR19= 0x202, tDQSOscB0 = 432 ps tDQSOscB1 = 432 ps
2287 23:45:38.489291 CH0 RK1: MR19=202, MR18=D8D8
2288 23:45:38.492846 [RxdqsGatingPostProcess] freq 1600
2289 23:45:38.496139 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
2290 23:45:38.496253 Rank: 0
2291 23:45:38.498984 best DQS0 dly(2T, 0.5T) = (2, 5)
2292 23:45:38.502455 best DQS1 dly(2T, 0.5T) = (2, 5)
2293 23:45:38.506034 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
2294 23:45:38.509376 best DQS1 P1 dly(2T, 0.5T) = (3, 1)
2295 23:45:38.509467 Rank: 1
2296 23:45:38.512992 best DQS0 dly(2T, 0.5T) = (2, 6)
2297 23:45:38.516024 best DQS1 dly(2T, 0.5T) = (2, 6)
2298 23:45:38.519322 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
2299 23:45:38.522848 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
2300 23:45:38.526226 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
2301 23:45:38.529569 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
2302 23:45:38.536089 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
2303 23:45:38.539305 Write Rank0 MR13 =0x59
2304 23:45:38.539462 ==
2305 23:45:38.542456 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2306 23:45:38.546096 fsp= 1, odt_onoff= 1, Byte mode= 0
2307 23:45:38.546227 ==
2308 23:45:38.549072 === u2Vref_new: 0x56 --> 0x3a
2309 23:45:38.552590 === u2Vref_new: 0x58 --> 0x58
2310 23:45:38.556067 === u2Vref_new: 0x5a --> 0x5a
2311 23:45:38.559542 === u2Vref_new: 0x5c --> 0x78
2312 23:45:38.562521 === u2Vref_new: 0x5e --> 0x7a
2313 23:45:38.565904 === u2Vref_new: 0x60 --> 0x90
2314 23:45:38.569028 [CA 0] Center 38 (13~63) winsize 51
2315 23:45:38.572396 [CA 1] Center 37 (12~63) winsize 52
2316 23:45:38.575818 [CA 2] Center 34 (6~63) winsize 58
2317 23:45:38.575960 [CA 3] Center 34 (6~63) winsize 58
2318 23:45:38.579355 [CA 4] Center 34 (6~63) winsize 58
2319 23:45:38.582543 [CA 5] Center 28 (-1~58) winsize 60
2320 23:45:38.582715
2321 23:45:38.585855 [CATrainingPosCal] consider 1 rank data
2322 23:45:38.589371 u2DelayCellTimex100 = 735/100 ps
2323 23:45:38.596103 CA0 delay=38 (13~63),Diff = 10 PI (13 cell)
2324 23:45:38.599377 CA1 delay=37 (12~63),Diff = 9 PI (11 cell)
2325 23:45:38.602858 CA2 delay=34 (6~63),Diff = 6 PI (7 cell)
2326 23:45:38.606186 CA3 delay=34 (6~63),Diff = 6 PI (7 cell)
2327 23:45:38.609713 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2328 23:45:38.612511 CA5 delay=28 (-1~58),Diff = 0 PI (0 cell)
2329 23:45:38.612781
2330 23:45:38.616066 CA PerBit enable=1, Macro0, CA PI delay=28
2331 23:45:38.619364 === u2Vref_new: 0x5e --> 0x7a
2332 23:45:38.619583
2333 23:45:38.623023 Vref(ca) range 1: 30
2334 23:45:38.623286
2335 23:45:38.623555 CS Dly= 10 (41-0-32)
2336 23:45:38.626248 Write Rank0 MR13 =0xd8
2337 23:45:38.629159 Write Rank0 MR13 =0xd8
2338 23:45:38.629340 Write Rank0 MR12 =0x5e
2339 23:45:38.632653 Write Rank1 MR13 =0x59
2340 23:45:38.632840 ==
2341 23:45:38.635926 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
2342 23:45:38.639820 fsp= 1, odt_onoff= 1, Byte mode= 0
2343 23:45:38.640006 ==
2344 23:45:38.642964 === u2Vref_new: 0x56 --> 0x3a
2345 23:45:38.646217 === u2Vref_new: 0x58 --> 0x58
2346 23:45:38.649552 === u2Vref_new: 0x5a --> 0x5a
2347 23:45:38.653102 === u2Vref_new: 0x5c --> 0x78
2348 23:45:38.656236 === u2Vref_new: 0x5e --> 0x7a
2349 23:45:38.659855 === u2Vref_new: 0x60 --> 0x90
2350 23:45:38.662675 [CA 0] Center 38 (13~63) winsize 51
2351 23:45:38.666106 [CA 1] Center 37 (12~63) winsize 52
2352 23:45:38.669626 [CA 2] Center 35 (7~63) winsize 57
2353 23:45:38.673004 [CA 3] Center 35 (7~63) winsize 57
2354 23:45:38.676377 [CA 4] Center 34 (6~63) winsize 58
2355 23:45:38.679507 [CA 5] Center 27 (-3~57) winsize 61
2356 23:45:38.679671
2357 23:45:38.683046 [CATrainingPosCal] consider 2 rank data
2358 23:45:38.683289 u2DelayCellTimex100 = 735/100 ps
2359 23:45:38.689565 CA0 delay=38 (13~63),Diff = 10 PI (13 cell)
2360 23:45:38.692672 CA1 delay=37 (12~63),Diff = 9 PI (11 cell)
2361 23:45:38.696180 CA2 delay=35 (7~63),Diff = 7 PI (9 cell)
2362 23:45:38.699548 CA3 delay=35 (7~63),Diff = 7 PI (9 cell)
2363 23:45:38.702776 CA4 delay=34 (6~63),Diff = 6 PI (7 cell)
2364 23:45:38.706663 CA5 delay=28 (-1~57),Diff = 0 PI (0 cell)
2365 23:45:38.706858
2366 23:45:38.709569 CA PerBit enable=1, Macro0, CA PI delay=28
2367 23:45:38.713227 === u2Vref_new: 0x5c --> 0x78
2368 23:45:38.713471
2369 23:45:38.716104 Vref(ca) range 1: 28
2370 23:45:38.716288
2371 23:45:38.716446 CS Dly= 10 (41-0-32)
2372 23:45:38.719673 Write Rank1 MR13 =0xd8
2373 23:45:38.722993 Write Rank1 MR13 =0xd8
2374 23:45:38.723242 Write Rank1 MR12 =0x5c
2375 23:45:38.726176 [RankSwap] Rank num 2, (Multi 1), Rank 0
2376 23:45:38.729490 Write Rank0 MR2 =0xad
2377 23:45:38.729573 [Write Leveling]
2378 23:45:38.732824 delay byte0 byte1 byte2 byte3
2379 23:45:38.732923
2380 23:45:38.736242 10 0 0
2381 23:45:38.736338 11 0 0
2382 23:45:38.739631 12 0 0
2383 23:45:38.739717 13 0 0
2384 23:45:38.739786 14 0 0
2385 23:45:38.743041 15 0 0
2386 23:45:38.743149 16 0 0
2387 23:45:38.746375 17 0 0
2388 23:45:38.746487 18 0 0
2389 23:45:38.746567 19 0 0
2390 23:45:38.749795 20 0 0
2391 23:45:38.749909 21 0 0
2392 23:45:38.753010 22 0 0
2393 23:45:38.753103 23 0 ff
2394 23:45:38.756311 24 0 ff
2395 23:45:38.756401 25 0 ff
2396 23:45:38.756473 26 0 ff
2397 23:45:38.759425 27 0 ff
2398 23:45:38.759548 28 0 ff
2399 23:45:38.762915 29 0 ff
2400 23:45:38.763002 30 0 ff
2401 23:45:38.766057 31 0 ff
2402 23:45:38.766147 32 0 ff
2403 23:45:38.769339 33 ff ff
2404 23:45:38.769425 34 ff ff
2405 23:45:38.772925 35 ff ff
2406 23:45:38.773013 36 ff ff
2407 23:45:38.773084 37 ff ff
2408 23:45:38.776404 38 ff ff
2409 23:45:38.776491 39 ff ff
2410 23:45:38.782677 pass bytecount = 0xff (0xff: all bytes pass)
2411 23:45:38.782764
2412 23:45:38.782832 DQS0 dly: 33
2413 23:45:38.782897 DQS1 dly: 23
2414 23:45:38.786102 Write Rank0 MR2 =0x2d
2415 23:45:38.789555 [RankSwap] Rank num 2, (Multi 1), Rank 0
2416 23:45:38.792804 Write Rank0 MR1 =0xd6
2417 23:45:38.792893 [Gating]
2418 23:45:38.792963 ==
2419 23:45:38.799776 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2420 23:45:38.799866 fsp= 1, odt_onoff= 1, Byte mode= 0
2421 23:45:38.802887 ==
2422 23:45:38.806081 3 1 0 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2423 23:45:38.809495 3 1 4 |3534 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2424 23:45:38.813105 3 1 8 |3534 2c2b |(11 11)(11 11) |(0 0)(1 1)| 0
2425 23:45:38.819748 3 1 12 |3534 2c2b |(11 11)(11 11) |(1 1)(1 1)| 0
2426 23:45:38.823061 3 1 16 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
2427 23:45:38.826386 3 1 20 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
2428 23:45:38.833361 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2429 23:45:38.836590 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2430 23:45:38.839833 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2431 23:45:38.846473 3 2 4 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2432 23:45:38.849724 3 2 8 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2433 23:45:38.853474 3 2 12 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
2434 23:45:38.856416 3 2 16 |807 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2435 23:45:38.863374 3 2 20 |3d3d 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
2436 23:45:38.866431 3 2 24 |3d3d 1c1b |(11 11)(11 11) |(1 1)(0 0)| 0
2437 23:45:38.870223 3 2 28 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2438 23:45:38.876689 3 3 0 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2439 23:45:38.880187 3 3 4 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2440 23:45:38.883035 3 3 8 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2441 23:45:38.889578 3 3 12 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2442 23:45:38.893288 3 3 16 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2443 23:45:38.896521 3 3 20 |403 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2444 23:45:38.899690 3 3 24 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
2445 23:45:38.906600 [Byte 0] Lead/lag falling Transition (3, 3, 24)
2446 23:45:38.909979 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2447 23:45:38.912878 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
2448 23:45:38.916795 [Byte 1] Lead/lag Transition tap number (1)
2449 23:45:38.923062 3 4 4 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2450 23:45:38.926468 3 4 8 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2451 23:45:38.930122 3 4 12 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
2452 23:45:38.936702 3 4 16 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
2453 23:45:38.940079 3 4 20 |3d3d 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
2454 23:45:38.943343 3 4 24 |3d3d 1a19 |(11 11)(11 11) |(1 1)(1 1)| 0
2455 23:45:38.950190 3 4 28 |3d3d adc7 |(11 11)(11 11) |(1 1)(1 1)| 0
2456 23:45:38.953856 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2457 23:45:38.956595 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2458 23:45:38.963384 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2459 23:45:38.966570 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2460 23:45:38.969769 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2461 23:45:38.973168 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2462 23:45:38.980141 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2463 23:45:38.983577 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2464 23:45:38.987011 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2465 23:45:38.993322 3 6 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2466 23:45:38.996753 3 6 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
2467 23:45:39.000110 [Byte 0] Lead/lag falling Transition (3, 6, 8)
2468 23:45:39.006957 3 6 12 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
2469 23:45:39.010205 [Byte 0] Lead/lag Transition tap number (2)
2470 23:45:39.013245 3 6 16 |202 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
2471 23:45:39.016653 [Byte 1] Lead/lag falling Transition (3, 6, 16)
2472 23:45:39.023390 3 6 20 |202 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
2473 23:45:39.026862 [Byte 1] Lead/lag Transition tap number (2)
2474 23:45:39.030164 3 6 24 |4646 1211 |(0 0)(11 11) |(0 0)(0 0)| 0
2475 23:45:39.033225 [Byte 0]First pass (3, 6, 24)
2476 23:45:39.036388 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2477 23:45:39.039896 [Byte 1]First pass (3, 6, 28)
2478 23:45:39.043341 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2479 23:45:39.046783 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2480 23:45:39.049713 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2481 23:45:39.056390 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2482 23:45:39.059903 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2483 23:45:39.063350 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2484 23:45:39.066698 3 7 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2485 23:45:39.072976 3 7 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
2486 23:45:39.076408 All bytes gating window > 1UI, Early break!
2487 23:45:39.076507
2488 23:45:39.079733 best DQS0 dly(2T, 0.5T, PI) = (3, 6, 12)
2489 23:45:39.079832
2490 23:45:39.082796 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 20)
2491 23:45:39.082927
2492 23:45:39.083040
2493 23:45:39.083148
2494 23:45:39.086036 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 2, 12)
2495 23:45:39.086170
2496 23:45:39.093239 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 20)
2497 23:45:39.093368
2498 23:45:39.093478
2499 23:45:39.093585 Write Rank0 MR1 =0x56
2500 23:45:39.093672
2501 23:45:39.096265 best RODT dly(2T, 0.5T) = (2, 3)
2502 23:45:39.096363
2503 23:45:39.099613 best RODT dly(2T, 0.5T) = (2, 3)
2504 23:45:39.099711 ==
2505 23:45:39.106271 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2506 23:45:39.110333 fsp= 1, odt_onoff= 1, Byte mode= 0
2507 23:45:39.110478 ==
2508 23:45:39.113486 Start DQ dly to find pass range UseTestEngine =0
2509 23:45:39.116571 x-axis: bit #, y-axis: DQ dly (-127~63)
2510 23:45:39.116695 RX Vref Scan = 0
2511 23:45:39.119746 -26, [0] xxxxxxxx xxxxxxxx [MSB]
2512 23:45:39.122754 -25, [0] xxxxxxxx xxxxxxxx [MSB]
2513 23:45:39.126645 -24, [0] xxxxxxxx xxxxxxxx [MSB]
2514 23:45:39.129453 -23, [0] xxxxxxxx xxxxxxxx [MSB]
2515 23:45:39.132956 -22, [0] xxxxxxxx xxxxxxxx [MSB]
2516 23:45:39.136446 -21, [0] xxxxxxxx xxxxxxxx [MSB]
2517 23:45:39.139832 -20, [0] xxxxxxxx xxxxxxxx [MSB]
2518 23:45:39.142875 -19, [0] xxxxxxxx xxxxxxxx [MSB]
2519 23:45:39.142970 -18, [0] xxxxxxxx xxxxxxxx [MSB]
2520 23:45:39.146338 -17, [0] xxxxxxxx xxxxxxxx [MSB]
2521 23:45:39.149297 -16, [0] xxxxxxxx xxxxxxxx [MSB]
2522 23:45:39.152842 -15, [0] xxxxxxxx xxxxxxxx [MSB]
2523 23:45:39.156682 -14, [0] xxxxxxxx xxxxxxxx [MSB]
2524 23:45:39.159368 -13, [0] xxxxxxxx xxxxxxxx [MSB]
2525 23:45:39.162860 -12, [0] xxxxxxxx xxxxxxxx [MSB]
2526 23:45:39.166293 -11, [0] xxxxxxxx xxxxxxxx [MSB]
2527 23:45:39.166385 -10, [0] xxxxxxxx xxxxxxxx [MSB]
2528 23:45:39.169492 -9, [0] xxxxxxxx xxxxxxxx [MSB]
2529 23:45:39.173117 -8, [0] xxxxxxxx xxxxxxxx [MSB]
2530 23:45:39.176014 -7, [0] xxxxxxxx xxxxxxxx [MSB]
2531 23:45:39.179657 -6, [0] xxxxxxxx xxxxxxxx [MSB]
2532 23:45:39.183758 -5, [0] xxxxxxxx xxxxxxxx [MSB]
2533 23:45:39.186082 -4, [0] xxxxxxxx xxxxxxxo [MSB]
2534 23:45:39.186173 -3, [0] xxxxxxxx xxxxxxxo [MSB]
2535 23:45:39.189328 -2, [0] xxxxxxxx xoxxxxxo [MSB]
2536 23:45:39.193018 -1, [0] xxxxxxxx xoxxxxxo [MSB]
2537 23:45:39.196676 0, [0] xxxoxxxx ooxxxxxo [MSB]
2538 23:45:39.199259 1, [0] xxooxxxx ooxxxxxo [MSB]
2539 23:45:39.202685 2, [0] xxooxxxx ooxxxxxo [MSB]
2540 23:45:39.205708 3, [0] xxooxxxo oooxxxxo [MSB]
2541 23:45:39.205800 4, [0] oxoooxxo oooxooxo [MSB]
2542 23:45:39.209422 6, [0] oooooooo ooooooxo [MSB]
2543 23:45:39.212722 32, [0] oooooooo ooooooox [MSB]
2544 23:45:39.216079 33, [0] oooooooo ooooooox [MSB]
2545 23:45:39.219414 34, [0] oooooooo ooooooox [MSB]
2546 23:45:39.223080 35, [0] oooxoooo ooooooox [MSB]
2547 23:45:39.223173 36, [0] oooxoooo xxooooox [MSB]
2548 23:45:39.225791 37, [0] ooxxoooo xxooooox [MSB]
2549 23:45:39.229198 38, [0] ooxxoooo xxooooox [MSB]
2550 23:45:39.233013 39, [0] ooxxooox xxooooox [MSB]
2551 23:45:39.236159 40, [0] oxxxooox xxxoooox [MSB]
2552 23:45:39.239462 41, [0] oxxxxoox xxxxxxox [MSB]
2553 23:45:39.242394 42, [0] xxxxxxxx xxxxxxxx [MSB]
2554 23:45:39.245823 iDelay=42, Bit 0, Center 22 (4 ~ 41) 38
2555 23:45:39.249274 iDelay=42, Bit 1, Center 22 (5 ~ 39) 35
2556 23:45:39.252477 iDelay=42, Bit 2, Center 18 (1 ~ 36) 36
2557 23:45:39.255825 iDelay=42, Bit 3, Center 17 (0 ~ 34) 35
2558 23:45:39.259182 iDelay=42, Bit 4, Center 22 (4 ~ 40) 37
2559 23:45:39.262412 iDelay=42, Bit 5, Center 23 (5 ~ 41) 37
2560 23:45:39.265748 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
2561 23:45:39.269191 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
2562 23:45:39.272740 iDelay=42, Bit 8, Center 17 (0 ~ 35) 36
2563 23:45:39.275649 iDelay=42, Bit 9, Center 16 (-2 ~ 35) 38
2564 23:45:39.279172 iDelay=42, Bit 10, Center 21 (3 ~ 39) 37
2565 23:45:39.282466 iDelay=42, Bit 11, Center 22 (5 ~ 40) 36
2566 23:45:39.288867 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
2567 23:45:39.292465 iDelay=42, Bit 13, Center 22 (4 ~ 40) 37
2568 23:45:39.295784 iDelay=42, Bit 14, Center 24 (7 ~ 41) 35
2569 23:45:39.299197 iDelay=42, Bit 15, Center 13 (-4 ~ 31) 36
2570 23:45:39.299287 ==
2571 23:45:39.302446 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2572 23:45:39.305803 fsp= 1, odt_onoff= 1, Byte mode= 0
2573 23:45:39.305893 ==
2574 23:45:39.309108 DQS Delay:
2575 23:45:39.309198 DQS0 = 0, DQS1 = 0
2576 23:45:39.313579 DQM Delay:
2577 23:45:39.313697 DQM0 = 20, DQM1 = 19
2578 23:45:39.313800 DQ Delay:
2579 23:45:39.315647 DQ0 =22, DQ1 =22, DQ2 =18, DQ3 =17
2580 23:45:39.319206 DQ4 =22, DQ5 =23, DQ6 =23, DQ7 =20
2581 23:45:39.322721 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
2582 23:45:39.325856 DQ12 =22, DQ13 =22, DQ14 =24, DQ15 =13
2583 23:45:39.325961
2584 23:45:39.326075
2585 23:45:39.329353 DramC Write-DBI off
2586 23:45:39.329444 ==
2587 23:45:39.332643 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2588 23:45:39.336033 fsp= 1, odt_onoff= 1, Byte mode= 0
2589 23:45:39.338831 ==
2590 23:45:39.342187 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
2591 23:45:39.342279
2592 23:45:39.345745 Begin, DQ Scan Range 919~1175
2593 23:45:39.345836
2594 23:45:39.345907
2595 23:45:39.345973 TX Vref Scan disable
2596 23:45:39.349162 919 |3 4 23|[0] xxxxxxxx xxxxxxxx [MSB]
2597 23:45:39.355830 920 |3 4 24|[0] xxxxxxxx xxxxxxxx [MSB]
2598 23:45:39.358774 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
2599 23:45:39.362329 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
2600 23:45:39.365612 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
2601 23:45:39.368923 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
2602 23:45:39.372313 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
2603 23:45:39.375272 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
2604 23:45:39.378749 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
2605 23:45:39.382072 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
2606 23:45:39.385432 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
2607 23:45:39.388690 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
2608 23:45:39.391908 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
2609 23:45:39.395339 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
2610 23:45:39.398412 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
2611 23:45:39.402174 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
2612 23:45:39.408645 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
2613 23:45:39.412146 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
2614 23:45:39.415217 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
2615 23:45:39.418867 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
2616 23:45:39.421698 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
2617 23:45:39.424938 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
2618 23:45:39.428620 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
2619 23:45:39.431755 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
2620 23:45:39.434876 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
2621 23:45:39.438501 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
2622 23:45:39.441939 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
2623 23:45:39.444961 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
2624 23:45:39.448599 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
2625 23:45:39.451509 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
2626 23:45:39.455022 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
2627 23:45:39.461353 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
2628 23:45:39.464943 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
2629 23:45:39.468038 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
2630 23:45:39.471588 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2631 23:45:39.474920 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2632 23:45:39.478220 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2633 23:45:39.481335 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2634 23:45:39.484687 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2635 23:45:39.488004 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2636 23:45:39.491758 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2637 23:45:39.495060 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2638 23:45:39.498088 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2639 23:45:39.501568 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2640 23:45:39.505055 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2641 23:45:39.507873 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2642 23:45:39.511455 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2643 23:45:39.514740 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
2644 23:45:39.518123 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
2645 23:45:39.521805 968 |3 6 8|[0] xxxxxxxx xxxxxxxo [MSB]
2646 23:45:39.524496 969 |3 6 9|[0] xxxxxxxx ooxxxxxo [MSB]
2647 23:45:39.531849 970 |3 6 10|[0] xxxxxxxx oooxoxoo [MSB]
2648 23:45:39.534699 971 |3 6 11|[0] xxxxxxxx oooooxoo [MSB]
2649 23:45:39.538088 972 |3 6 12|[0] xxxxxxxx oooooooo [MSB]
2650 23:45:39.541338 973 |3 6 13|[0] xxxxxxxx oooooooo [MSB]
2651 23:45:39.544674 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
2652 23:45:39.548137 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
2653 23:45:39.551268 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
2654 23:45:39.554960 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
2655 23:45:39.558141 978 |3 6 18|[0] xxxxxxxx oooooooo [MSB]
2656 23:45:39.561382 979 |3 6 19|[0] xxxxxxxx oooooooo [MSB]
2657 23:45:39.564393 980 |3 6 20|[0] xxxxxxxx oooooooo [MSB]
2658 23:45:39.567907 981 |3 6 21|[0] xooooxoo oooooooo [MSB]
2659 23:45:39.571305 982 |3 6 22|[0] oooooxoo oooooooo [MSB]
2660 23:45:39.574564 985 |3 6 25|[0] oooooooo ooooooox [MSB]
2661 23:45:39.581116 986 |3 6 26|[0] oooooooo oxooooox [MSB]
2662 23:45:39.584467 987 |3 6 27|[0] oooooooo xxooooox [MSB]
2663 23:45:39.588113 988 |3 6 28|[0] oooooooo xxooooox [MSB]
2664 23:45:39.591331 989 |3 6 29|[0] oooooooo xxxxxxxx [MSB]
2665 23:45:39.594268 990 |3 6 30|[0] oooooooo xxxxxxxx [MSB]
2666 23:45:39.597767 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
2667 23:45:39.601067 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
2668 23:45:39.604494 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
2669 23:45:39.607819 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
2670 23:45:39.611376 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
2671 23:45:39.614308 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
2672 23:45:39.617669 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
2673 23:45:39.620767 998 |3 6 38|[0] oooooooo xxxxxxxx [MSB]
2674 23:45:39.624154 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
2675 23:45:39.627639 1000 |3 6 40|[0] oooxoooo xxxxxxxx [MSB]
2676 23:45:39.634354 1001 |3 6 41|[0] ooxxooox xxxxxxxx [MSB]
2677 23:45:39.637511 1002 |3 6 42|[0] xxxxxxxx xxxxxxxx [MSB]
2678 23:45:39.640982 Byte0, DQ PI dly=990, DQM PI dly= 990
2679 23:45:39.644737 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 30)
2680 23:45:39.644858
2681 23:45:39.648050 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 30)
2682 23:45:39.648172
2683 23:45:39.651165 Byte1, DQ PI dly=978, DQM PI dly= 978
2684 23:45:39.657404 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 18)
2685 23:45:39.657535
2686 23:45:39.661038 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 18)
2687 23:45:39.661166
2688 23:45:39.661264 ==
2689 23:45:39.667582 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2690 23:45:39.671154 fsp= 1, odt_onoff= 1, Byte mode= 0
2691 23:45:39.671274 ==
2692 23:45:39.674808 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
2693 23:45:39.674924
2694 23:45:39.677763 Begin, DQ Scan Range 954~1018
2695 23:45:39.677886 Write Rank0 MR14 =0x0
2696 23:45:39.687708
2697 23:45:39.687827 CH=1, VrefRange= 0, VrefLevel = 0
2698 23:45:39.694076 TX Bit0 (984~999) 16 991, Bit8 (970~983) 14 976,
2699 23:45:39.697907 TX Bit1 (983~996) 14 989, Bit9 (971~982) 12 976,
2700 23:45:39.704121 TX Bit2 (981~995) 15 988, Bit10 (974~985) 12 979,
2701 23:45:39.707449 TX Bit3 (979~992) 14 985, Bit11 (976~985) 10 980,
2702 23:45:39.711105 TX Bit4 (983~998) 16 990, Bit12 (973~985) 13 979,
2703 23:45:39.717962 TX Bit5 (985~998) 14 991, Bit13 (976~986) 11 981,
2704 23:45:39.721099 TX Bit6 (984~997) 14 990, Bit14 (973~985) 13 979,
2705 23:45:39.724490 TX Bit7 (984~996) 13 990, Bit15 (968~978) 11 973,
2706 23:45:39.727741
2707 23:45:39.727868 Write Rank0 MR14 =0x2
2708 23:45:39.737031
2709 23:45:39.737193 CH=1, VrefRange= 0, VrefLevel = 2
2710 23:45:39.743886 TX Bit0 (984~1000) 17 992, Bit8 (971~983) 13 977,
2711 23:45:39.746721 TX Bit1 (983~996) 14 989, Bit9 (971~983) 13 977,
2712 23:45:39.753702 TX Bit2 (981~996) 16 988, Bit10 (974~985) 12 979,
2713 23:45:39.756945 TX Bit3 (979~993) 15 986, Bit11 (974~986) 13 980,
2714 23:45:39.760339 TX Bit4 (983~998) 16 990, Bit12 (973~987) 15 980,
2715 23:45:39.766960 TX Bit5 (984~999) 16 991, Bit13 (975~987) 13 981,
2716 23:45:39.770317 TX Bit6 (983~998) 16 990, Bit14 (972~986) 15 979,
2717 23:45:39.773450 TX Bit7 (983~997) 15 990, Bit15 (968~978) 11 973,
2718 23:45:39.773534
2719 23:45:39.776984 Write Rank0 MR14 =0x4
2720 23:45:39.786565
2721 23:45:39.786688 CH=1, VrefRange= 0, VrefLevel = 4
2722 23:45:39.792684 TX Bit0 (983~1000) 18 991, Bit8 (970~984) 15 977,
2723 23:45:39.795914 TX Bit1 (982~998) 17 990, Bit9 (970~983) 14 976,
2724 23:45:39.803303 TX Bit2 (981~997) 17 989, Bit10 (973~986) 14 979,
2725 23:45:39.806033 TX Bit3 (978~994) 17 986, Bit11 (974~987) 14 980,
2726 23:45:39.809813 TX Bit4 (982~999) 18 990, Bit12 (973~987) 15 980,
2727 23:45:39.816371 TX Bit5 (984~999) 16 991, Bit13 (975~988) 14 981,
2728 23:45:39.819788 TX Bit6 (983~999) 17 991, Bit14 (971~986) 16 978,
2729 23:45:39.822855 TX Bit7 (983~998) 16 990, Bit15 (968~980) 13 974,
2730 23:45:39.823008
2731 23:45:39.826134 Write Rank0 MR14 =0x6
2732 23:45:39.835681
2733 23:45:39.835797 CH=1, VrefRange= 0, VrefLevel = 6
2734 23:45:39.842696 TX Bit0 (983~1001) 19 992, Bit8 (970~984) 15 977,
2735 23:45:39.845830 TX Bit1 (983~998) 16 990, Bit9 (970~983) 14 976,
2736 23:45:39.852775 TX Bit2 (979~998) 20 988, Bit10 (971~987) 17 979,
2737 23:45:39.855355 TX Bit3 (978~994) 17 986, Bit11 (974~988) 15 981,
2738 23:45:39.858902 TX Bit4 (982~999) 18 990, Bit12 (972~988) 17 980,
2739 23:45:39.865754 TX Bit5 (984~1000) 17 992, Bit13 (975~989) 15 982,
2740 23:45:39.868762 TX Bit6 (982~999) 18 990, Bit14 (972~987) 16 979,
2741 23:45:39.872101 TX Bit7 (982~998) 17 990, Bit15 (967~981) 15 974,
2742 23:45:39.875212
2743 23:45:39.875436 Write Rank0 MR14 =0x8
2744 23:45:39.884935
2745 23:45:39.885323 CH=1, VrefRange= 0, VrefLevel = 8
2746 23:45:39.891917 TX Bit0 (983~1000) 18 991, Bit8 (970~985) 16 977,
2747 23:45:39.895265 TX Bit1 (981~999) 19 990, Bit9 (970~984) 15 977,
2748 23:45:39.901851 TX Bit2 (979~998) 20 988, Bit10 (971~988) 18 979,
2749 23:45:39.905137 TX Bit3 (978~994) 17 986, Bit11 (973~989) 17 981,
2750 23:45:39.908458 TX Bit4 (981~1000) 20 990, Bit12 (971~989) 19 980,
2751 23:45:39.915123 TX Bit5 (984~1000) 17 992, Bit13 (974~989) 16 981,
2752 23:45:39.918576 TX Bit6 (982~999) 18 990, Bit14 (971~988) 18 979,
2753 23:45:39.924909 TX Bit7 (982~999) 18 990, Bit15 (968~982) 15 975,
2754 23:45:39.925215
2755 23:45:39.925487 Write Rank0 MR14 =0xa
2756 23:45:39.934435
2757 23:45:39.938040 CH=1, VrefRange= 0, VrefLevel = 10
2758 23:45:39.941412 TX Bit0 (983~1001) 19 992, Bit8 (969~985) 17 977,
2759 23:45:39.944377 TX Bit1 (981~999) 19 990, Bit9 (969~984) 16 976,
2760 23:45:39.951284 TX Bit2 (979~999) 21 989, Bit10 (971~989) 19 980,
2761 23:45:39.954566 TX Bit3 (978~995) 18 986, Bit11 (973~990) 18 981,
2762 23:45:39.957769 TX Bit4 (981~1000) 20 990, Bit12 (971~990) 20 980,
2763 23:45:39.965025 TX Bit5 (983~1000) 18 991, Bit13 (974~990) 17 982,
2764 23:45:39.967965 TX Bit6 (982~1000) 19 991, Bit14 (971~988) 18 979,
2765 23:45:39.974690 TX Bit7 (982~999) 18 990, Bit15 (967~983) 17 975,
2766 23:45:39.974919
2767 23:45:39.975148 Write Rank0 MR14 =0xc
2768 23:45:39.984608
2769 23:45:39.987920 CH=1, VrefRange= 0, VrefLevel = 12
2770 23:45:39.991117 TX Bit0 (982~1002) 21 992, Bit8 (969~985) 17 977,
2771 23:45:39.994543 TX Bit1 (980~1000) 21 990, Bit9 (969~984) 16 976,
2772 23:45:40.001775 TX Bit2 (979~999) 21 989, Bit10 (971~990) 20 980,
2773 23:45:40.004451 TX Bit3 (977~996) 20 986, Bit11 (972~990) 19 981,
2774 23:45:40.007784 TX Bit4 (981~1000) 20 990, Bit12 (970~990) 21 980,
2775 23:45:40.014807 TX Bit5 (983~1001) 19 992, Bit13 (973~990) 18 981,
2776 23:45:40.017967 TX Bit6 (982~1000) 19 991, Bit14 (970~989) 20 979,
2777 23:45:40.024518 TX Bit7 (982~1000) 19 991, Bit15 (966~983) 18 974,
2778 23:45:40.024821
2779 23:45:40.025078 Write Rank0 MR14 =0xe
2780 23:45:40.034751
2781 23:45:40.037763 CH=1, VrefRange= 0, VrefLevel = 14
2782 23:45:40.041500 TX Bit0 (982~1002) 21 992, Bit8 (969~986) 18 977,
2783 23:45:40.044784 TX Bit1 (980~1000) 21 990, Bit9 (969~985) 17 977,
2784 23:45:40.051018 TX Bit2 (978~1000) 23 989, Bit10 (970~990) 21 980,
2785 23:45:40.054695 TX Bit3 (977~996) 20 986, Bit11 (971~990) 20 980,
2786 23:45:40.058140 TX Bit4 (981~1001) 21 991, Bit12 (971~991) 21 981,
2787 23:45:40.064731 TX Bit5 (983~1001) 19 992, Bit13 (974~991) 18 982,
2788 23:45:40.067906 TX Bit6 (981~1000) 20 990, Bit14 (970~990) 21 980,
2789 23:45:40.074316 TX Bit7 (981~1000) 20 990, Bit15 (966~984) 19 975,
2790 23:45:40.074411
2791 23:45:40.074504 Write Rank0 MR14 =0x10
2792 23:45:40.085165
2793 23:45:40.088106 CH=1, VrefRange= 0, VrefLevel = 16
2794 23:45:40.091702 TX Bit0 (982~1002) 21 992, Bit8 (969~987) 19 978,
2795 23:45:40.095064 TX Bit1 (980~1001) 22 990, Bit9 (969~985) 17 977,
2796 23:45:40.101302 TX Bit2 (978~1000) 23 989, Bit10 (971~991) 21 981,
2797 23:45:40.104798 TX Bit3 (977~998) 22 987, Bit11 (970~991) 22 980,
2798 23:45:40.108222 TX Bit4 (980~1001) 22 990, Bit12 (970~991) 22 980,
2799 23:45:40.114522 TX Bit5 (983~1001) 19 992, Bit13 (973~991) 19 982,
2800 23:45:40.118218 TX Bit6 (981~1001) 21 991, Bit14 (970~991) 22 980,
2801 23:45:40.124772 TX Bit7 (980~1000) 21 990, Bit15 (966~984) 19 975,
2802 23:45:40.124865
2803 23:45:40.124958 Write Rank0 MR14 =0x12
2804 23:45:40.135092
2805 23:45:40.138578 CH=1, VrefRange= 0, VrefLevel = 18
2806 23:45:40.141695 TX Bit0 (981~1002) 22 991, Bit8 (969~988) 20 978,
2807 23:45:40.144995 TX Bit1 (979~1001) 23 990, Bit9 (969~986) 18 977,
2808 23:45:40.151585 TX Bit2 (978~1000) 23 989, Bit10 (970~991) 22 980,
2809 23:45:40.154896 TX Bit3 (977~998) 22 987, Bit11 (970~991) 22 980,
2810 23:45:40.158605 TX Bit4 (980~1001) 22 990, Bit12 (970~992) 23 981,
2811 23:45:40.164912 TX Bit5 (982~1002) 21 992, Bit13 (972~991) 20 981,
2812 23:45:40.168395 TX Bit6 (980~1001) 22 990, Bit14 (970~991) 22 980,
2813 23:45:40.174884 TX Bit7 (980~1001) 22 990, Bit15 (965~984) 20 974,
2814 23:45:40.174977
2815 23:45:40.175072 Write Rank0 MR14 =0x14
2816 23:45:40.185425
2817 23:45:40.189037 CH=1, VrefRange= 0, VrefLevel = 20
2818 23:45:40.192009 TX Bit0 (981~1003) 23 992, Bit8 (969~989) 21 979,
2819 23:45:40.195320 TX Bit1 (979~1001) 23 990, Bit9 (969~987) 19 978,
2820 23:45:40.202242 TX Bit2 (978~1001) 24 989, Bit10 (970~991) 22 980,
2821 23:45:40.205437 TX Bit3 (977~999) 23 988, Bit11 (970~991) 22 980,
2822 23:45:40.209016 TX Bit4 (979~1002) 24 990, Bit12 (970~992) 23 981,
2823 23:45:40.215307 TX Bit5 (982~1002) 21 992, Bit13 (972~991) 20 981,
2824 23:45:40.218655 TX Bit6 (980~1001) 22 990, Bit14 (970~991) 22 980,
2825 23:45:40.225515 TX Bit7 (980~1001) 22 990, Bit15 (965~985) 21 975,
2826 23:45:40.225608
2827 23:45:40.225680 Write Rank0 MR14 =0x16
2828 23:45:40.236186
2829 23:45:40.239917 CH=1, VrefRange= 0, VrefLevel = 22
2830 23:45:40.242654 TX Bit0 (981~1004) 24 992, Bit8 (968~989) 22 978,
2831 23:45:40.245970 TX Bit1 (979~1002) 24 990, Bit9 (969~987) 19 978,
2832 23:45:40.252976 TX Bit2 (978~1001) 24 989, Bit10 (970~992) 23 981,
2833 23:45:40.255830 TX Bit3 (977~999) 23 988, Bit11 (970~992) 23 981,
2834 23:45:40.259393 TX Bit4 (979~1002) 24 990, Bit12 (970~992) 23 981,
2835 23:45:40.266357 TX Bit5 (981~1003) 23 992, Bit13 (971~992) 22 981,
2836 23:45:40.269271 TX Bit6 (979~1002) 24 990, Bit14 (969~992) 24 980,
2837 23:45:40.276165 TX Bit7 (979~1002) 24 990, Bit15 (964~985) 22 974,
2838 23:45:40.276253
2839 23:45:40.276325 Write Rank0 MR14 =0x18
2840 23:45:40.286753
2841 23:45:40.290457 CH=1, VrefRange= 0, VrefLevel = 24
2842 23:45:40.293944 TX Bit0 (980~1005) 26 992, Bit8 (968~990) 23 979,
2843 23:45:40.296871 TX Bit1 (978~1002) 25 990, Bit9 (968~988) 21 978,
2844 23:45:40.303824 TX Bit2 (978~1001) 24 989, Bit10 (970~992) 23 981,
2845 23:45:40.306975 TX Bit3 (976~999) 24 987, Bit11 (970~992) 23 981,
2846 23:45:40.310573 TX Bit4 (978~1003) 26 990, Bit12 (970~993) 24 981,
2847 23:45:40.316707 TX Bit5 (981~1003) 23 992, Bit13 (971~992) 22 981,
2848 23:45:40.320130 TX Bit6 (979~1003) 25 991, Bit14 (970~992) 23 981,
2849 23:45:40.326991 TX Bit7 (979~1002) 24 990, Bit15 (964~986) 23 975,
2850 23:45:40.327084
2851 23:45:40.327155 Write Rank0 MR14 =0x1a
2852 23:45:40.337795
2853 23:45:40.337886 CH=1, VrefRange= 0, VrefLevel = 26
2854 23:45:40.344793 TX Bit0 (980~1006) 27 993, Bit8 (968~990) 23 979,
2855 23:45:40.348449 TX Bit1 (978~1002) 25 990, Bit9 (967~989) 23 978,
2856 23:45:40.354657 TX Bit2 (977~1002) 26 989, Bit10 (969~992) 24 980,
2857 23:45:40.357764 TX Bit3 (976~1000) 25 988, Bit11 (970~992) 23 981,
2858 23:45:40.361438 TX Bit4 (978~1003) 26 990, Bit12 (969~993) 25 981,
2859 23:45:40.367916 TX Bit5 (981~1004) 24 992, Bit13 (971~993) 23 982,
2860 23:45:40.371674 TX Bit6 (979~1003) 25 991, Bit14 (969~992) 24 980,
2861 23:45:40.377961 TX Bit7 (979~1002) 24 990, Bit15 (963~986) 24 974,
2862 23:45:40.378053
2863 23:45:40.380924 wait MRW command Rank0 MR14 =0x1c fired (1)
2864 23:45:40.381018 Write Rank0 MR14 =0x1c
2865 23:45:40.392520
2866 23:45:40.396092 CH=1, VrefRange= 0, VrefLevel = 28
2867 23:45:40.399206 TX Bit0 (980~1006) 27 993, Bit8 (968~990) 23 979,
2868 23:45:40.402395 TX Bit1 (978~1002) 25 990, Bit9 (967~989) 23 978,
2869 23:45:40.409174 TX Bit2 (977~1002) 26 989, Bit10 (969~992) 24 980,
2870 23:45:40.412981 TX Bit3 (976~1000) 25 988, Bit11 (970~992) 23 981,
2871 23:45:40.419000 TX Bit4 (978~1003) 26 990, Bit12 (969~993) 25 981,
2872 23:45:40.422738 TX Bit5 (981~1004) 24 992, Bit13 (971~993) 23 982,
2873 23:45:40.425540 TX Bit6 (979~1003) 25 991, Bit14 (969~992) 24 980,
2874 23:45:40.432237 TX Bit7 (979~1002) 24 990, Bit15 (963~986) 24 974,
2875 23:45:40.432329
2876 23:45:40.432401 Write Rank0 MR14 =0x1e
2877 23:45:40.443683
2878 23:45:40.447027 CH=1, VrefRange= 0, VrefLevel = 30
2879 23:45:40.450729 TX Bit0 (980~1006) 27 993, Bit8 (967~991) 25 979,
2880 23:45:40.453949 TX Bit1 (978~1003) 26 990, Bit9 (968~990) 23 979,
2881 23:45:40.460536 TX Bit2 (977~1002) 26 989, Bit10 (969~992) 24 980,
2882 23:45:40.463305 TX Bit3 (976~1000) 25 988, Bit11 (969~993) 25 981,
2883 23:45:40.467034 TX Bit4 (979~1004) 26 991, Bit12 (969~993) 25 981,
2884 23:45:40.473777 TX Bit5 (980~1005) 26 992, Bit13 (970~993) 24 981,
2885 23:45:40.476945 TX Bit6 (978~1003) 26 990, Bit14 (969~993) 25 981,
2886 23:45:40.483248 TX Bit7 (978~1003) 26 990, Bit15 (963~986) 24 974,
2887 23:45:40.483340
2888 23:45:40.483421 Write Rank0 MR14 =0x20
2889 23:45:40.494455
2890 23:45:40.497966 CH=1, VrefRange= 0, VrefLevel = 32
2891 23:45:40.501253 TX Bit0 (979~1006) 28 992, Bit8 (967~991) 25 979,
2892 23:45:40.504694 TX Bit1 (978~1004) 27 991, Bit9 (968~990) 23 979,
2893 23:45:40.511006 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
2894 23:45:40.515066 TX Bit3 (976~999) 24 987, Bit11 (969~993) 25 981,
2895 23:45:40.517956 TX Bit4 (979~1004) 26 991, Bit12 (970~992) 23 981,
2896 23:45:40.524092 TX Bit5 (979~1006) 28 992, Bit13 (970~993) 24 981,
2897 23:45:40.527845 TX Bit6 (978~1005) 28 991, Bit14 (969~992) 24 980,
2898 23:45:40.534508 TX Bit7 (978~1004) 27 991, Bit15 (962~986) 25 974,
2899 23:45:40.534627
2900 23:45:40.534733 Write Rank0 MR14 =0x22
2901 23:45:40.545740
2902 23:45:40.548924 CH=1, VrefRange= 0, VrefLevel = 34
2903 23:45:40.552357 TX Bit0 (979~1006) 28 992, Bit8 (967~991) 25 979,
2904 23:45:40.555676 TX Bit1 (978~1004) 27 991, Bit9 (968~990) 23 979,
2905 23:45:40.562254 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
2906 23:45:40.565776 TX Bit3 (976~999) 24 987, Bit11 (969~993) 25 981,
2907 23:45:40.568736 TX Bit4 (979~1004) 26 991, Bit12 (970~992) 23 981,
2908 23:45:40.575746 TX Bit5 (979~1006) 28 992, Bit13 (970~993) 24 981,
2909 23:45:40.578750 TX Bit6 (978~1005) 28 991, Bit14 (969~992) 24 980,
2910 23:45:40.585267 TX Bit7 (978~1004) 27 991, Bit15 (962~986) 25 974,
2911 23:45:40.585352
2912 23:45:40.585422 Write Rank0 MR14 =0x24
2913 23:45:40.596485
2914 23:45:40.599458 CH=1, VrefRange= 0, VrefLevel = 36
2915 23:45:40.602986 TX Bit0 (979~1006) 28 992, Bit8 (967~991) 25 979,
2916 23:45:40.606477 TX Bit1 (978~1004) 27 991, Bit9 (968~990) 23 979,
2917 23:45:40.613046 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
2918 23:45:40.616430 TX Bit3 (976~999) 24 987, Bit11 (969~993) 25 981,
2919 23:45:40.619910 TX Bit4 (979~1004) 26 991, Bit12 (970~992) 23 981,
2920 23:45:40.626390 TX Bit5 (979~1006) 28 992, Bit13 (970~993) 24 981,
2921 23:45:40.629635 TX Bit6 (978~1005) 28 991, Bit14 (969~992) 24 980,
2922 23:45:40.636116 TX Bit7 (978~1004) 27 991, Bit15 (962~986) 25 974,
2923 23:45:40.636208
2924 23:45:40.636279 Write Rank0 MR14 =0x26
2925 23:45:40.647099
2926 23:45:40.650526 CH=1, VrefRange= 0, VrefLevel = 38
2927 23:45:40.653776 TX Bit0 (979~1006) 28 992, Bit8 (967~991) 25 979,
2928 23:45:40.656971 TX Bit1 (978~1004) 27 991, Bit9 (968~990) 23 979,
2929 23:45:40.663755 TX Bit2 (977~1001) 25 989, Bit10 (969~992) 24 980,
2930 23:45:40.667208 TX Bit3 (976~999) 24 987, Bit11 (969~993) 25 981,
2931 23:45:40.670084 TX Bit4 (979~1004) 26 991, Bit12 (970~992) 23 981,
2932 23:45:40.676844 TX Bit5 (979~1006) 28 992, Bit13 (970~993) 24 981,
2933 23:45:40.680280 TX Bit6 (978~1005) 28 991, Bit14 (969~992) 24 980,
2934 23:45:40.687123 TX Bit7 (978~1004) 27 991, Bit15 (962~986) 25 974,
2935 23:45:40.687233
2936 23:45:40.687373
2937 23:45:40.690238 TX Vref found, early break! 384< 385
2938 23:45:40.693840 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
2939 23:45:40.697244 u1DelayCellOfst[0]=6 cells (5 PI)
2940 23:45:40.700630 u1DelayCellOfst[1]=5 cells (4 PI)
2941 23:45:40.703530 u1DelayCellOfst[2]=2 cells (2 PI)
2942 23:45:40.706931 u1DelayCellOfst[3]=0 cells (0 PI)
2943 23:45:40.710265 u1DelayCellOfst[4]=5 cells (4 PI)
2944 23:45:40.713802 u1DelayCellOfst[5]=6 cells (5 PI)
2945 23:45:40.713966 u1DelayCellOfst[6]=5 cells (4 PI)
2946 23:45:40.717303 u1DelayCellOfst[7]=5 cells (4 PI)
2947 23:45:40.720182 Byte0, DQ PI dly=987, DQM PI dly= 989
2948 23:45:40.727034 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
2949 23:45:40.727199
2950 23:45:40.730624 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
2951 23:45:40.730788
2952 23:45:40.734050 u1DelayCellOfst[8]=6 cells (5 PI)
2953 23:45:40.737240 u1DelayCellOfst[9]=6 cells (5 PI)
2954 23:45:40.740100 u1DelayCellOfst[10]=7 cells (6 PI)
2955 23:45:40.743940 u1DelayCellOfst[11]=9 cells (7 PI)
2956 23:45:40.746896 u1DelayCellOfst[12]=9 cells (7 PI)
2957 23:45:40.750028 u1DelayCellOfst[13]=9 cells (7 PI)
2958 23:45:40.753581 u1DelayCellOfst[14]=7 cells (6 PI)
2959 23:45:40.753775 u1DelayCellOfst[15]=0 cells (0 PI)
2960 23:45:40.757297 Byte1, DQ PI dly=974, DQM PI dly= 977
2961 23:45:40.763503 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 14)
2962 23:45:40.763681
2963 23:45:40.766644 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 14)
2964 23:45:40.766807
2965 23:45:40.770239 Write Rank0 MR14 =0x20
2966 23:45:40.770329
2967 23:45:40.773242 Final TX Range 0 Vref 32
2968 23:45:40.773341
2969 23:45:40.780110 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
2970 23:45:40.780201
2971 23:45:40.783632 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
2972 23:45:40.793239 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
2973 23:45:40.800451 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
2974 23:45:40.800542 Write Rank0 MR3 =0xb0
2975 23:45:40.803323 DramC Write-DBI on
2976 23:45:40.803421 ==
2977 23:45:40.806958 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
2978 23:45:40.810382 fsp= 1, odt_onoff= 1, Byte mode= 0
2979 23:45:40.810472 ==
2980 23:45:40.816997 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
2981 23:45:40.817087
2982 23:45:40.819958 Begin, DQ Scan Range 697~761
2983 23:45:40.820048
2984 23:45:40.820118
2985 23:45:40.820183 TX Vref Scan disable
2986 23:45:40.823412 697 |2 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
2987 23:45:40.826443 698 |2 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
2988 23:45:40.830535 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
2989 23:45:40.833423 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
2990 23:45:40.840487 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
2991 23:45:40.843369 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
2992 23:45:40.846669 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
2993 23:45:40.850379 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
2994 23:45:40.853503 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
2995 23:45:40.856863 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
2996 23:45:40.860464 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
2997 23:45:40.863457 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
2998 23:45:40.866869 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
2999 23:45:40.870483 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3000 23:45:40.873417 711 |2 6 7|[0] xxxxxxxx oooooooo [MSB]
3001 23:45:40.876651 712 |2 6 8|[0] xxxxxxxx oooooooo [MSB]
3002 23:45:40.880027 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3003 23:45:40.883777 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3004 23:45:40.887918 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3005 23:45:40.890602 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3006 23:45:40.893821 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3007 23:45:40.896974 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3008 23:45:40.900691 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3009 23:45:40.903606 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3010 23:45:40.907026 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3011 23:45:40.913876 722 |2 6 18|[0] xxxxxxxx oooooooo [MSB]
3012 23:45:40.917167 736 |2 6 32|[0] oooooooo xxxxxxxx [MSB]
3013 23:45:40.920044 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3014 23:45:40.923513 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3015 23:45:40.926925 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3016 23:45:40.933720 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3017 23:45:40.936720 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3018 23:45:40.940337 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3019 23:45:40.943908 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3020 23:45:40.947041 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3021 23:45:40.950857 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3022 23:45:40.953347 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3023 23:45:40.956838 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3024 23:45:40.960125 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3025 23:45:40.963818 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3026 23:45:40.966901 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3027 23:45:40.970284 751 |2 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
3028 23:45:40.973297 Byte0, DQ PI dly=736, DQM PI dly= 736
3029 23:45:40.980041 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 32)
3030 23:45:40.980593
3031 23:45:40.983546 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 32)
3032 23:45:40.984067
3033 23:45:40.986770 Byte1, DQ PI dly=723, DQM PI dly= 723
3034 23:45:40.990199 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 19)
3035 23:45:40.990743
3036 23:45:40.996394 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 19)
3037 23:45:40.996926
3038 23:45:41.002926 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3039 23:45:41.009928 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3040 23:45:41.016483 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3041 23:45:41.016905 Write Rank0 MR3 =0x30
3042 23:45:41.019865 DramC Write-DBI off
3043 23:45:41.020317
3044 23:45:41.020643 [DATLAT]
3045 23:45:41.023200 Freq=1600, CH1 RK0, use_rxtx_scan=0
3046 23:45:41.023740
3047 23:45:41.026687 DATLAT Default: 0xf
3048 23:45:41.027114 7, 0xFFFF, sum=0
3049 23:45:41.030118 8, 0xFFFF, sum=0
3050 23:45:41.030535 9, 0xFFFF, sum=0
3051 23:45:41.033050 10, 0xFFFF, sum=0
3052 23:45:41.033464 11, 0xFFFF, sum=0
3053 23:45:41.036491 12, 0xFFFF, sum=0
3054 23:45:41.036907 13, 0xFFFF, sum=0
3055 23:45:41.040036 14, 0x0, sum=1
3056 23:45:41.040455 15, 0x0, sum=2
3057 23:45:41.040786 16, 0x0, sum=3
3058 23:45:41.042789 17, 0x0, sum=4
3059 23:45:41.045997 pattern=2 first_step=14 total pass=5 best_step=16
3060 23:45:41.046509 ==
3061 23:45:41.053171 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3062 23:45:41.056080 fsp= 1, odt_onoff= 1, Byte mode= 0
3063 23:45:41.056495 ==
3064 23:45:41.059457 Start DQ dly to find pass range UseTestEngine =1
3065 23:45:41.062979 x-axis: bit #, y-axis: DQ dly (-127~63)
3066 23:45:41.065912 RX Vref Scan = 1
3067 23:45:41.172625
3068 23:45:41.172913 RX Vref found, early break!
3069 23:45:41.173093
3070 23:45:41.178836 Final RX Vref 11, apply to both rank0 and 1
3071 23:45:41.179034 ==
3072 23:45:41.182218 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 0
3073 23:45:41.185682 fsp= 1, odt_onoff= 1, Byte mode= 0
3074 23:45:41.185878 ==
3075 23:45:41.188625 DQS Delay:
3076 23:45:41.188803 DQS0 = 0, DQS1 = 0
3077 23:45:41.188942 DQM Delay:
3078 23:45:41.192021 DQM0 = 20, DQM1 = 19
3079 23:45:41.192199 DQ Delay:
3080 23:45:41.195398 DQ0 =22, DQ1 =22, DQ2 =18, DQ3 =16
3081 23:45:41.198716 DQ4 =22, DQ5 =23, DQ6 =23, DQ7 =20
3082 23:45:41.202166 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =22
3083 23:45:41.205395 DQ12 =22, DQ13 =21, DQ14 =23, DQ15 =13
3084 23:45:41.205589
3085 23:45:41.205769
3086 23:45:41.205994
3087 23:45:41.208750 [DramC_TX_OE_Calibration] TA2
3088 23:45:41.211646 Original DQ_B0 (3 6) =30, OEN = 27
3089 23:45:41.215624 Original DQ_B1 (3 6) =30, OEN = 27
3090 23:45:41.218590 23, 0x0, End_B0=23 End_B1=23
3091 23:45:41.218816 24, 0x0, End_B0=24 End_B1=24
3092 23:45:41.222057 25, 0x0, End_B0=25 End_B1=25
3093 23:45:41.225326 26, 0x0, End_B0=26 End_B1=26
3094 23:45:41.228580 27, 0x0, End_B0=27 End_B1=27
3095 23:45:41.231925 28, 0x0, End_B0=28 End_B1=28
3096 23:45:41.232118 29, 0x0, End_B0=29 End_B1=29
3097 23:45:41.235185 30, 0x0, End_B0=30 End_B1=30
3098 23:45:41.238541 31, 0xFFFF, End_B0=30 End_B1=30
3099 23:45:41.245065 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3100 23:45:41.248623 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3101 23:45:41.248802
3102 23:45:41.248942
3103 23:45:41.251718 Write Rank0 MR23 =0x3f
3104 23:45:41.251897 [DQSOSC]
3105 23:45:41.261907 [DQSOSCAuto] RK0, (LSB)MR18= 0xc1c1, (MSB)MR19= 0x202, tDQSOscB0 = 446 ps tDQSOscB1 = 446 ps
3106 23:45:41.268610 CH1_RK0: MR19=0x202, MR18=0xC1C1, DQSOSC=446, MR23=63, INC=12, DEC=18
3107 23:45:41.268790 Write Rank0 MR23 =0x3f
3108 23:45:41.268931 [DQSOSC]
3109 23:45:41.278424 [DQSOSCAuto] RK0, (LSB)MR18= 0xbdbd, (MSB)MR19= 0x202, tDQSOscB0 = 449 ps tDQSOscB1 = 449 ps
3110 23:45:41.281981 CH1 RK0: MR19=202, MR18=BDBD
3111 23:45:41.284899 [RankSwap] Rank num 2, (Multi 1), Rank 1
3112 23:45:41.285083 Write Rank0 MR2 =0xad
3113 23:45:41.288349 [Write Leveling]
3114 23:45:41.292087 delay byte0 byte1 byte2 byte3
3115 23:45:41.292265
3116 23:45:41.292403 10 0 0
3117 23:45:41.294752 11 0 0
3118 23:45:41.294932 12 0 0
3119 23:45:41.295076 13 0 0
3120 23:45:41.298139 14 0 0
3121 23:45:41.298320 15 0 0
3122 23:45:41.301587 16 0 0
3123 23:45:41.301768 17 0 0
3124 23:45:41.304924 18 0 0
3125 23:45:41.305116 19 0 0
3126 23:45:41.305262 20 0 0
3127 23:45:41.308089 21 0 0
3128 23:45:41.308268 22 0 0
3129 23:45:41.311629 23 0 0
3130 23:45:41.311810 24 0 0
3131 23:45:41.311952 25 0 ff
3132 23:45:41.314868 26 0 ff
3133 23:45:41.315047 27 0 ff
3134 23:45:41.317878 28 0 ff
3135 23:45:41.318149 29 0 ff
3136 23:45:41.321684 30 0 ff
3137 23:45:41.321776 31 0 ff
3138 23:45:41.324576 32 0 ff
3139 23:45:41.324668 33 0 ff
3140 23:45:41.324740 34 0 ff
3141 23:45:41.327984 35 ff ff
3142 23:45:41.328076 36 ff ff
3143 23:45:41.331335 37 ff ff
3144 23:45:41.331457 38 ff ff
3145 23:45:41.334678 39 ff ff
3146 23:45:41.334774 40 ff ff
3147 23:45:41.337812 41 ff ff
3148 23:45:41.341287 pass bytecount = 0xff (0xff: all bytes pass)
3149 23:45:41.341377
3150 23:45:41.341448 DQS0 dly: 35
3151 23:45:41.344805 DQS1 dly: 25
3152 23:45:41.344896 Write Rank0 MR2 =0x2d
3153 23:45:41.348239 [RankSwap] Rank num 2, (Multi 1), Rank 0
3154 23:45:41.351582 Write Rank1 MR1 =0xd6
3155 23:45:41.351673 [Gating]
3156 23:45:41.351744 ==
3157 23:45:41.358078 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3158 23:45:41.361552 fsp= 1, odt_onoff= 1, Byte mode= 0
3159 23:45:41.361644 ==
3160 23:45:41.364570 3 1 0 |3636 2c2b |(0 0)(11 11) |(1 1)(1 1)| 0
3161 23:45:41.368380 3 1 4 |3534 2c2b |(11 11)(11 11) |(1 1)(0 0)| 0
3162 23:45:41.374739 3 1 8 |1111 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3163 23:45:41.378440 3 1 12 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3164 23:45:41.381392 3 1 16 |2b2a 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3165 23:45:41.387923 3 1 20 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3166 23:45:41.391392 3 1 24 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3167 23:45:41.394333 3 1 28 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3168 23:45:41.401501 3 2 0 |3534 2c2b |(11 11)(11 11) |(0 1)(1 0)| 0
3169 23:45:41.404775 3 2 4 |3535 2c2b |(11 10)(11 11) |(1 1)(1 0)| 0
3170 23:45:41.407664 3 2 8 |3d3d 2c2b |(11 11)(11 11) |(1 1)(1 0)| 0
3171 23:45:41.411153 3 2 12 |3d3d 302 |(0 0)(11 1) |(0 0)(0 0)| 0
3172 23:45:41.417943 3 2 16 |e0e 201f |(11 11)(11 11) |(1 1)(0 0)| 0
3173 23:45:41.421130 3 2 20 |3b3b 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3174 23:45:41.424437 3 2 24 |3d3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3175 23:45:41.431485 3 2 28 |1e1d 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3176 23:45:41.434810 3 3 0 |3c3c 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3177 23:45:41.437869 3 3 4 |909 3534 |(1 1)(11 11) |(1 1)(0 0)| 0
3178 23:45:41.441134 3 3 8 |504 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3179 23:45:41.447918 3 3 12 |3534 3534 |(11 11)(11 11) |(1 1)(1 1)| 0
3180 23:45:41.451393 [Byte 0] Lead/lag falling Transition (3, 3, 12)
3181 23:45:41.454957 3 3 16 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3182 23:45:41.461259 3 3 20 |3534 3534 |(11 11)(11 11) |(0 1)(1 1)| 0
3183 23:45:41.464740 3 3 24 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3184 23:45:41.468026 3 3 28 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3185 23:45:41.474344 3 4 0 |3534 3534 |(11 11)(11 11) |(0 1)(0 0)| 0
3186 23:45:41.478244 3 4 4 |3534 3534 |(11 11)(11 11) |(1 1)(0 0)| 0
3187 23:45:41.481474 3 4 8 |2323 3534 |(11 11)(11 11) |(1 1)(0 1)| 0
3188 23:45:41.484466 3 4 12 |3d3d 201 |(11 11)(11 11) |(1 1)(1 1)| 0
3189 23:45:41.491264 3 4 16 |3d3d e0e |(11 11)(11 11) |(1 1)(1 1)| 0
3190 23:45:41.494399 3 4 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3191 23:45:41.498022 3 4 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3192 23:45:41.504449 3 4 28 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3193 23:45:41.508025 3 5 0 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3194 23:45:41.510889 3 5 4 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3195 23:45:41.517790 3 5 8 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3196 23:45:41.520842 3 5 12 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3197 23:45:41.524588 3 5 16 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3198 23:45:41.530756 3 5 20 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3199 23:45:41.534302 3 5 24 |3d3d 3d3d |(11 11)(11 11) |(1 1)(1 1)| 0
3200 23:45:41.538031 [Byte 0] Lead/lag falling Transition (3, 5, 24)
3201 23:45:41.543871 3 5 28 |3d3d 3d3d |(11 11)(11 11) |(1 0)(1 1)| 0
3202 23:45:41.547623 [Byte 0] Lead/lag Transition tap number (2)
3203 23:45:41.551262 3 6 0 |3d3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3204 23:45:41.554062 3 6 4 |3e3d 3d3d |(11 11)(11 11) |(0 0)(1 1)| 0
3205 23:45:41.560991 [Byte 1] Lead/lag falling Transition (3, 6, 4)
3206 23:45:41.563869 3 6 8 |808 3d3d |(11 11)(11 11) |(0 0)(1 0)| 0
3207 23:45:41.567276 [Byte 1] Lead/lag Transition tap number (2)
3208 23:45:41.570883 3 6 12 |4646 3e3d |(0 0)(11 11) |(0 0)(0 0)| 0
3209 23:45:41.574108 [Byte 0]First pass (3, 6, 12)
3210 23:45:41.577760 3 6 16 |4646 1414 |(0 0)(11 11) |(0 0)(0 0)| 0
3211 23:45:41.584010 3 6 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3212 23:45:41.584103 [Byte 1]First pass (3, 6, 20)
3213 23:45:41.590377 3 6 24 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3214 23:45:41.594269 3 6 28 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3215 23:45:41.597473 3 7 0 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3216 23:45:41.600626 3 7 4 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3217 23:45:41.604090 3 7 8 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3218 23:45:41.610699 3 7 12 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3219 23:45:41.613786 3 7 16 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3220 23:45:41.617522 3 7 20 |4646 4646 |(0 0)(0 0) |(0 0)(0 0)| 0
3221 23:45:41.620815 All bytes gating window > 1UI, Early break!
3222 23:45:41.620906
3223 23:45:41.624438 best DQS0 dly(2T, 0.5T, PI) = (3, 5, 28)
3224 23:45:41.624529
3225 23:45:41.627193 best DQS1 dly(2T, 0.5T, PI) = (3, 6, 8)
3226 23:45:41.627284
3227 23:45:41.630663
3228 23:45:41.630752
3229 23:45:41.634139 best DQS0 P1 dly(2T, 0.5T, PI) = (4, 1, 28)
3230 23:45:41.634258
3231 23:45:41.637692 best DQS1 P1 dly(2T, 0.5T, PI) = (4, 2, 8)
3232 23:45:41.637783
3233 23:45:41.637856
3234 23:45:41.640886 Write Rank1 MR1 =0x56
3235 23:45:41.640977
3236 23:45:41.643908 best RODT dly(2T, 0.5T) = (2, 2)
3237 23:45:41.643999
3238 23:45:41.644071 best RODT dly(2T, 0.5T) = (2, 3)
3239 23:45:41.647067 ==
3240 23:45:41.650427 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3241 23:45:41.653787 fsp= 1, odt_onoff= 1, Byte mode= 0
3242 23:45:41.653879 ==
3243 23:45:41.657249 Start DQ dly to find pass range UseTestEngine =0
3244 23:45:41.660585 x-axis: bit #, y-axis: DQ dly (-127~63)
3245 23:45:41.663623 RX Vref Scan = 0
3246 23:45:41.667245 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3247 23:45:41.670674 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3248 23:45:41.673669 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3249 23:45:41.673760 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3250 23:45:41.677352 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3251 23:45:41.680734 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3252 23:45:41.684232 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3253 23:45:41.687606 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3254 23:45:41.690432 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3255 23:45:41.694042 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3256 23:45:41.697176 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3257 23:45:41.700846 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3258 23:45:41.700941 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3259 23:45:41.704012 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3260 23:45:41.707398 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3261 23:45:41.710439 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3262 23:45:41.714111 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3263 23:45:41.717711 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3264 23:45:41.720670 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3265 23:45:41.721096 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3266 23:45:41.724082 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3267 23:45:41.727210 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3268 23:45:41.730739 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3269 23:45:41.734297 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3270 23:45:41.737462 -2, [0] xxxoxxxx xoxxxxxo [MSB]
3271 23:45:41.740642 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3272 23:45:41.741060 0, [0] xxooxxxx ooxxxxxo [MSB]
3273 23:45:41.743900 1, [0] xxooxxxx ooxxxxxo [MSB]
3274 23:45:41.747321 2, [0] xxooxxxx ooxxxxxo [MSB]
3275 23:45:41.750763 3, [0] xxoooxxo oooxxxxo [MSB]
3276 23:45:41.754032 4, [0] xxoooxxo oooxxxxo [MSB]
3277 23:45:41.757508 5, [0] oooooxoo ooooooxo [MSB]
3278 23:45:41.760712 32, [0] oooooooo ooooooox [MSB]
3279 23:45:41.761234 33, [0] oooooooo ooooooox [MSB]
3280 23:45:41.763929 34, [0] oooooooo ooooooox [MSB]
3281 23:45:41.767839 35, [0] oooxoooo xxooooox [MSB]
3282 23:45:41.770607 36, [0] oooxoooo xxooooox [MSB]
3283 23:45:41.774289 37, [0] ooxxoooo xxooooox [MSB]
3284 23:45:41.777190 38, [0] ooxxoooo xxooooox [MSB]
3285 23:45:41.780407 39, [0] oxxxxoox xxooooox [MSB]
3286 23:45:41.780960 40, [0] oxxxxoox xxxoooox [MSB]
3287 23:45:41.783866 41, [0] oxxxxoox xxxxxxox [MSB]
3288 23:45:41.786820 42, [0] xxxxxxxx xxxxxxxx [MSB]
3289 23:45:41.790729 iDelay=42, Bit 0, Center 23 (5 ~ 41) 37
3290 23:45:41.793790 iDelay=42, Bit 1, Center 21 (5 ~ 38) 34
3291 23:45:41.796829 iDelay=42, Bit 2, Center 18 (0 ~ 36) 37
3292 23:45:41.800247 iDelay=42, Bit 3, Center 16 (-2 ~ 34) 37
3293 23:45:41.803568 iDelay=42, Bit 4, Center 20 (3 ~ 38) 36
3294 23:45:41.810011 iDelay=42, Bit 5, Center 23 (6 ~ 41) 36
3295 23:45:41.813396 iDelay=42, Bit 6, Center 23 (5 ~ 41) 37
3296 23:45:41.816674 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
3297 23:45:41.819767 iDelay=42, Bit 8, Center 17 (0 ~ 34) 35
3298 23:45:41.823582 iDelay=42, Bit 9, Center 16 (-2 ~ 34) 37
3299 23:45:41.826735 iDelay=42, Bit 10, Center 21 (3 ~ 39) 37
3300 23:45:41.829793 iDelay=42, Bit 11, Center 22 (5 ~ 40) 36
3301 23:45:41.833611 iDelay=42, Bit 12, Center 22 (5 ~ 40) 36
3302 23:45:41.836424 iDelay=42, Bit 13, Center 22 (5 ~ 40) 36
3303 23:45:41.839975 iDelay=42, Bit 14, Center 23 (6 ~ 41) 36
3304 23:45:41.843515 iDelay=42, Bit 15, Center 14 (-3 ~ 31) 35
3305 23:45:41.846681 ==
3306 23:45:41.849883 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3307 23:45:41.853051 fsp= 1, odt_onoff= 1, Byte mode= 0
3308 23:45:41.853483 ==
3309 23:45:41.853969 DQS Delay:
3310 23:45:41.856364 DQS0 = 0, DQS1 = 0
3311 23:45:41.856780 DQM Delay:
3312 23:45:41.860125 DQM0 = 20, DQM1 = 19
3313 23:45:41.860538 DQ Delay:
3314 23:45:41.862906 DQ0 =23, DQ1 =21, DQ2 =18, DQ3 =16
3315 23:45:41.866617 DQ4 =20, DQ5 =23, DQ6 =23, DQ7 =20
3316 23:45:41.869797 DQ8 =17, DQ9 =16, DQ10 =21, DQ11 =22
3317 23:45:41.873432 DQ12 =22, DQ13 =22, DQ14 =23, DQ15 =14
3318 23:45:41.873945
3319 23:45:41.874274
3320 23:45:41.876269 DramC Write-DBI off
3321 23:45:41.876681 ==
3322 23:45:41.880192 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3323 23:45:41.883335 fsp= 1, odt_onoff= 1, Byte mode= 0
3324 23:45:41.883911 ==
3325 23:45:41.889577 [TxWindowPerbitCal] calType=2, VrefScanEnable 0
3326 23:45:41.890088
3327 23:45:41.890417 Begin, DQ Scan Range 921~1177
3328 23:45:41.890740
3329 23:45:41.892763
3330 23:45:41.893180 TX Vref Scan disable
3331 23:45:41.896222 921 |3 4 25|[0] xxxxxxxx xxxxxxxx [MSB]
3332 23:45:41.899734 922 |3 4 26|[0] xxxxxxxx xxxxxxxx [MSB]
3333 23:45:41.903051 923 |3 4 27|[0] xxxxxxxx xxxxxxxx [MSB]
3334 23:45:41.906682 924 |3 4 28|[0] xxxxxxxx xxxxxxxx [MSB]
3335 23:45:41.909270 925 |3 4 29|[0] xxxxxxxx xxxxxxxx [MSB]
3336 23:45:41.916338 926 |3 4 30|[0] xxxxxxxx xxxxxxxx [MSB]
3337 23:45:41.919758 927 |3 4 31|[0] xxxxxxxx xxxxxxxx [MSB]
3338 23:45:41.922947 928 |3 4 32|[0] xxxxxxxx xxxxxxxx [MSB]
3339 23:45:41.925992 929 |3 4 33|[0] xxxxxxxx xxxxxxxx [MSB]
3340 23:45:41.929436 930 |3 4 34|[0] xxxxxxxx xxxxxxxx [MSB]
3341 23:45:41.932270 931 |3 4 35|[0] xxxxxxxx xxxxxxxx [MSB]
3342 23:45:41.935658 932 |3 4 36|[0] xxxxxxxx xxxxxxxx [MSB]
3343 23:45:41.939148 933 |3 4 37|[0] xxxxxxxx xxxxxxxx [MSB]
3344 23:45:41.942413 934 |3 4 38|[0] xxxxxxxx xxxxxxxx [MSB]
3345 23:45:41.945488 935 |3 4 39|[0] xxxxxxxx xxxxxxxx [MSB]
3346 23:45:41.948990 936 |3 4 40|[0] xxxxxxxx xxxxxxxx [MSB]
3347 23:45:41.952032 937 |3 4 41|[0] xxxxxxxx xxxxxxxx [MSB]
3348 23:45:41.955840 938 |3 4 42|[0] xxxxxxxx xxxxxxxx [MSB]
3349 23:45:41.959246 939 |3 4 43|[0] xxxxxxxx xxxxxxxx [MSB]
3350 23:45:41.962280 940 |3 4 44|[0] xxxxxxxx xxxxxxxx [MSB]
3351 23:45:41.965603 941 |3 4 45|[0] xxxxxxxx xxxxxxxx [MSB]
3352 23:45:41.972176 942 |3 4 46|[0] xxxxxxxx xxxxxxxx [MSB]
3353 23:45:41.976111 943 |3 4 47|[0] xxxxxxxx xxxxxxxx [MSB]
3354 23:45:41.979377 944 |3 4 48|[0] xxxxxxxx xxxxxxxx [MSB]
3355 23:45:41.982241 945 |3 4 49|[0] xxxxxxxx xxxxxxxx [MSB]
3356 23:45:41.985383 946 |3 4 50|[0] xxxxxxxx xxxxxxxx [MSB]
3357 23:45:41.989485 947 |3 4 51|[0] xxxxxxxx xxxxxxxx [MSB]
3358 23:45:41.992410 948 |3 4 52|[0] xxxxxxxx xxxxxxxx [MSB]
3359 23:45:41.995772 949 |3 4 53|[0] xxxxxxxx xxxxxxxx [MSB]
3360 23:45:41.998969 950 |3 4 54|[0] xxxxxxxx xxxxxxxx [MSB]
3361 23:45:42.002302 951 |3 4 55|[0] xxxxxxxx xxxxxxxx [MSB]
3362 23:45:42.005556 952 |3 4 56|[0] xxxxxxxx xxxxxxxx [MSB]
3363 23:45:42.009478 953 |3 4 57|[0] xxxxxxxx xxxxxxxx [MSB]
3364 23:45:42.012458 954 |3 4 58|[0] xxxxxxxx xxxxxxxx [MSB]
3365 23:45:42.015928 955 |3 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3366 23:45:42.018727 956 |3 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3367 23:45:42.026080 957 |3 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3368 23:45:42.028877 958 |3 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3369 23:45:42.032431 959 |3 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3370 23:45:42.035642 960 |3 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3371 23:45:42.039467 961 |3 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3372 23:45:42.041901 962 |3 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3373 23:45:42.045663 963 |3 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3374 23:45:42.048791 964 |3 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3375 23:45:42.052134 965 |3 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3376 23:45:42.055572 966 |3 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3377 23:45:42.058630 967 |3 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3378 23:45:42.061639 968 |3 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3379 23:45:42.064838 969 |3 6 9|[0] xxxxxxxx xxxxxxxo [MSB]
3380 23:45:42.068109 970 |3 6 10|[0] xxxxxxxx ooxxxxxo [MSB]
3381 23:45:42.071364 971 |3 6 11|[0] xxxxxxxx ooxxxxxo [MSB]
3382 23:45:42.074983 972 |3 6 12|[0] xxxxxxxx oooxxxxo [MSB]
3383 23:45:42.078389 973 |3 6 13|[0] xxxxxxxx oooooxoo [MSB]
3384 23:45:42.081438 974 |3 6 14|[0] xxxxxxxx oooooooo [MSB]
3385 23:45:42.084789 975 |3 6 15|[0] xxxxxxxx oooooooo [MSB]
3386 23:45:42.088427 976 |3 6 16|[0] xxxxxxxx oooooooo [MSB]
3387 23:45:42.095110 977 |3 6 17|[0] xxxxxxxx oooooooo [MSB]
3388 23:45:42.098067 978 |3 6 18|[0] xxooxxxx oooooooo [MSB]
3389 23:45:42.101270 979 |3 6 19|[0] xooooxox oooooooo [MSB]
3390 23:45:42.104538 980 |3 6 20|[0] ooooooox oooooooo [MSB]
3391 23:45:42.108311 986 |3 6 26|[0] oooooooo ooooooox [MSB]
3392 23:45:42.111519 987 |3 6 27|[0] oooooooo ooooooox [MSB]
3393 23:45:42.114634 988 |3 6 28|[0] oooooooo ooooooox [MSB]
3394 23:45:42.118216 989 |3 6 29|[0] oooooooo ooooooox [MSB]
3395 23:45:42.121332 990 |3 6 30|[0] oooooooo oxooooox [MSB]
3396 23:45:42.124856 991 |3 6 31|[0] oooooooo xxxxxxxx [MSB]
3397 23:45:42.128304 992 |3 6 32|[0] oooooooo xxxxxxxx [MSB]
3398 23:45:42.135350 993 |3 6 33|[0] oooooooo xxxxxxxx [MSB]
3399 23:45:42.138383 994 |3 6 34|[0] oooooooo xxxxxxxx [MSB]
3400 23:45:42.141586 995 |3 6 35|[0] oooooooo xxxxxxxx [MSB]
3401 23:45:42.144985 996 |3 6 36|[0] oooooooo xxxxxxxx [MSB]
3402 23:45:42.147946 997 |3 6 37|[0] oooooooo xxxxxxxx [MSB]
3403 23:45:42.151682 998 |3 6 38|[0] oooxoooo xxxxxxxx [MSB]
3404 23:45:42.154543 999 |3 6 39|[0] oooxoooo xxxxxxxx [MSB]
3405 23:45:42.158287 1000 |3 6 40|[0] ooxxooox xxxxxxxx [MSB]
3406 23:45:42.161404 1001 |3 6 41|[0] ooxxxoox xxxxxxxx [MSB]
3407 23:45:42.164759 1002 |3 6 42|[0] oxxxxoxx xxxxxxxx [MSB]
3408 23:45:42.168136 1003 |3 6 43|[0] xxxxxxxx xxxxxxxx [MSB]
3409 23:45:42.171367 Byte0, DQ PI dly=989, DQM PI dly= 989
3410 23:45:42.178350 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 29)
3411 23:45:42.178835
3412 23:45:42.181247 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 29)
3413 23:45:42.181658
3414 23:45:42.184689 Byte1, DQ PI dly=979, DQM PI dly= 979
3415 23:45:42.188066 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 19)
3416 23:45:42.188483
3417 23:45:42.194782 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 19)
3418 23:45:42.195191
3419 23:45:42.195615 ==
3420 23:45:42.197951 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3421 23:45:42.200977 fsp= 1, odt_onoff= 1, Byte mode= 0
3422 23:45:42.201388 ==
3423 23:45:42.207918 [TxWindowPerbitCal] calType=0, VrefScanEnable 1
3424 23:45:42.208339
3425 23:45:42.208661 Begin, DQ Scan Range 955~1019
3426 23:45:42.211272 Write Rank1 MR14 =0x0
3427 23:45:42.220035
3428 23:45:42.220439 CH=1, VrefRange= 0, VrefLevel = 0
3429 23:45:42.226992 TX Bit0 (983~998) 16 990, Bit8 (971~985) 15 978,
3430 23:45:42.229837 TX Bit1 (983~997) 15 990, Bit9 (973~985) 13 979,
3431 23:45:42.236857 TX Bit2 (980~994) 15 987, Bit10 (976~986) 11 981,
3432 23:45:42.240121 TX Bit3 (978~991) 14 984, Bit11 (976~988) 13 982,
3433 23:45:42.243481 TX Bit4 (982~997) 16 989, Bit12 (977~986) 10 981,
3434 23:45:42.250099 TX Bit5 (983~998) 16 990, Bit13 (976~988) 13 982,
3435 23:45:42.253478 TX Bit6 (983~998) 16 990, Bit14 (976~986) 11 981,
3436 23:45:42.256850 TX Bit7 (984~995) 12 989, Bit15 (969~979) 11 974,
3437 23:45:42.257263
3438 23:45:42.259658 Write Rank1 MR14 =0x2
3439 23:45:42.268862
3440 23:45:42.269289 CH=1, VrefRange= 0, VrefLevel = 2
3441 23:45:42.275865 TX Bit0 (983~999) 17 991, Bit8 (971~985) 15 978,
3442 23:45:42.279210 TX Bit1 (982~997) 16 989, Bit9 (972~985) 14 978,
3443 23:45:42.285857 TX Bit2 (979~995) 17 987, Bit10 (975~987) 13 981,
3444 23:45:42.289266 TX Bit3 (978~992) 15 985, Bit11 (976~988) 13 982,
3445 23:45:42.292222 TX Bit4 (981~997) 17 989, Bit12 (976~987) 12 981,
3446 23:45:42.299085 TX Bit5 (983~998) 16 990, Bit13 (976~989) 14 982,
3447 23:45:42.302623 TX Bit6 (982~998) 17 990, Bit14 (976~987) 12 981,
3448 23:45:42.306083 TX Bit7 (984~996) 13 990, Bit15 (970~981) 12 975,
3449 23:45:42.306610
3450 23:45:42.308669 Write Rank1 MR14 =0x4
3451 23:45:42.318208
3452 23:45:42.318615 CH=1, VrefRange= 0, VrefLevel = 4
3453 23:45:42.324411 TX Bit0 (983~999) 17 991, Bit8 (971~985) 15 978,
3454 23:45:42.328008 TX Bit1 (981~998) 18 989, Bit9 (971~985) 15 978,
3455 23:45:42.334465 TX Bit2 (979~996) 18 987, Bit10 (975~988) 14 981,
3456 23:45:42.337833 TX Bit3 (978~992) 15 985, Bit11 (975~990) 16 982,
3457 23:45:42.340906 TX Bit4 (981~997) 17 989, Bit12 (976~988) 13 982,
3458 23:45:42.348106 TX Bit5 (982~999) 18 990, Bit13 (976~991) 16 983,
3459 23:45:42.350996 TX Bit6 (982~998) 17 990, Bit14 (976~987) 12 981,
3460 23:45:42.354488 TX Bit7 (983~997) 15 990, Bit15 (969~983) 15 976,
3461 23:45:42.357672
3462 23:45:42.358084 Write Rank1 MR14 =0x6
3463 23:45:42.367356
3464 23:45:42.367914 CH=1, VrefRange= 0, VrefLevel = 6
3465 23:45:42.374416 TX Bit0 (982~1000) 19 991, Bit8 (970~986) 17 978,
3466 23:45:42.376937 TX Bit1 (981~998) 18 989, Bit9 (971~986) 16 978,
3467 23:45:42.384046 TX Bit2 (979~997) 19 988, Bit10 (975~988) 14 981,
3468 23:45:42.387160 TX Bit3 (978~993) 16 985, Bit11 (975~990) 16 982,
3469 23:45:42.390795 TX Bit4 (981~998) 18 989, Bit12 (975~990) 16 982,
3470 23:45:42.397760 TX Bit5 (982~1000) 19 991, Bit13 (975~991) 17 983,
3471 23:45:42.400665 TX Bit6 (981~999) 19 990, Bit14 (975~988) 14 981,
3472 23:45:42.403739 TX Bit7 (983~998) 16 990, Bit15 (969~983) 15 976,
3473 23:45:42.404270
3474 23:45:42.407655 Write Rank1 MR14 =0x8
3475 23:45:42.416692
3476 23:45:42.417210 CH=1, VrefRange= 0, VrefLevel = 8
3477 23:45:42.423536 TX Bit0 (982~1000) 19 991, Bit8 (970~986) 17 978,
3478 23:45:42.426106 TX Bit1 (980~999) 20 989, Bit9 (971~986) 16 978,
3479 23:45:42.433373 TX Bit2 (979~997) 19 988, Bit10 (974~990) 17 982,
3480 23:45:42.436449 TX Bit3 (978~994) 17 986, Bit11 (975~991) 17 983,
3481 23:45:42.440022 TX Bit4 (980~999) 20 989, Bit12 (975~990) 16 982,
3482 23:45:42.446451 TX Bit5 (982~1000) 19 991, Bit13 (975~991) 17 983,
3483 23:45:42.450017 TX Bit6 (981~999) 19 990, Bit14 (975~989) 15 982,
3484 23:45:42.453043 TX Bit7 (983~998) 16 990, Bit15 (969~983) 15 976,
3485 23:45:42.453460
3486 23:45:42.456324 Write Rank1 MR14 =0xa
3487 23:45:42.465410
3488 23:45:42.468949 CH=1, VrefRange= 0, VrefLevel = 10
3489 23:45:42.472505 TX Bit0 (981~1000) 20 990, Bit8 (970~987) 18 978,
3490 23:45:42.475444 TX Bit1 (980~999) 20 989, Bit9 (970~987) 18 978,
3491 23:45:42.482620 TX Bit2 (978~998) 21 988, Bit10 (973~989) 17 981,
3492 23:45:42.486194 TX Bit3 (977~995) 19 986, Bit11 (974~991) 18 982,
3493 23:45:42.488757 TX Bit4 (980~999) 20 989, Bit12 (975~991) 17 983,
3494 23:45:42.495557 TX Bit5 (982~1000) 19 991, Bit13 (975~992) 18 983,
3495 23:45:42.498895 TX Bit6 (980~999) 20 989, Bit14 (974~989) 16 981,
3496 23:45:42.502775 TX Bit7 (982~998) 17 990, Bit15 (968~984) 17 976,
3497 23:45:42.503302
3498 23:45:42.505650 Write Rank1 MR14 =0xc
3499 23:45:42.514992
3500 23:45:42.518412 CH=1, VrefRange= 0, VrefLevel = 12
3501 23:45:42.521805 TX Bit0 (981~1001) 21 991, Bit8 (970~987) 18 978,
3502 23:45:42.525140 TX Bit1 (979~1000) 22 989, Bit9 (970~987) 18 978,
3503 23:45:42.531969 TX Bit2 (978~998) 21 988, Bit10 (974~991) 18 982,
3504 23:45:42.535249 TX Bit3 (977~996) 20 986, Bit11 (974~991) 18 982,
3505 23:45:42.538970 TX Bit4 (979~999) 21 989, Bit12 (974~991) 18 982,
3506 23:45:42.545332 TX Bit5 (981~1001) 21 991, Bit13 (974~992) 19 983,
3507 23:45:42.548572 TX Bit6 (980~1000) 21 990, Bit14 (974~991) 18 982,
3508 23:45:42.555030 TX Bit7 (982~999) 18 990, Bit15 (968~984) 17 976,
3509 23:45:42.555586
3510 23:45:42.555917 Write Rank1 MR14 =0xe
3511 23:45:42.565333
3512 23:45:42.568320 CH=1, VrefRange= 0, VrefLevel = 14
3513 23:45:42.571245 TX Bit0 (981~1002) 22 991, Bit8 (969~988) 20 978,
3514 23:45:42.574929 TX Bit1 (979~1000) 22 989, Bit9 (970~988) 19 979,
3515 23:45:42.581466 TX Bit2 (978~999) 22 988, Bit10 (973~991) 19 982,
3516 23:45:42.584638 TX Bit3 (978~997) 20 987, Bit11 (974~992) 19 983,
3517 23:45:42.587968 TX Bit4 (979~1000) 22 989, Bit12 (975~991) 17 983,
3518 23:45:42.594720 TX Bit5 (981~1001) 21 991, Bit13 (974~992) 19 983,
3519 23:45:42.598020 TX Bit6 (980~1000) 21 990, Bit14 (973~991) 19 982,
3520 23:45:42.604124 TX Bit7 (982~999) 18 990, Bit15 (968~985) 18 976,
3521 23:45:42.604539
3522 23:45:42.604898 Write Rank1 MR14 =0x10
3523 23:45:42.615099
3524 23:45:42.618599 CH=1, VrefRange= 0, VrefLevel = 16
3525 23:45:42.621570 TX Bit0 (980~1002) 23 991, Bit8 (970~990) 21 980,
3526 23:45:42.625053 TX Bit1 (979~1000) 22 989, Bit9 (970~989) 20 979,
3527 23:45:42.631574 TX Bit2 (978~999) 22 988, Bit10 (972~991) 20 981,
3528 23:45:42.635100 TX Bit3 (977~997) 21 987, Bit11 (973~992) 20 982,
3529 23:45:42.638473 TX Bit4 (979~1000) 22 989, Bit12 (974~992) 19 983,
3530 23:45:42.645059 TX Bit5 (980~1002) 23 991, Bit13 (973~993) 21 983,
3531 23:45:42.648105 TX Bit6 (979~1001) 23 990, Bit14 (973~991) 19 982,
3532 23:45:42.655072 TX Bit7 (981~1000) 20 990, Bit15 (968~985) 18 976,
3533 23:45:42.655622
3534 23:45:42.655952 Write Rank1 MR14 =0x12
3535 23:45:42.665466
3536 23:45:42.668642 CH=1, VrefRange= 0, VrefLevel = 18
3537 23:45:42.672310 TX Bit0 (980~1003) 24 991, Bit8 (969~990) 22 979,
3538 23:45:42.675545 TX Bit1 (979~1001) 23 990, Bit9 (969~989) 21 979,
3539 23:45:42.682022 TX Bit2 (978~999) 22 988, Bit10 (972~992) 21 982,
3540 23:45:42.685604 TX Bit3 (977~998) 22 987, Bit11 (973~993) 21 983,
3541 23:45:42.688792 TX Bit4 (979~1001) 23 990, Bit12 (973~992) 20 982,
3542 23:45:42.695609 TX Bit5 (980~1002) 23 991, Bit13 (974~993) 20 983,
3543 23:45:42.698672 TX Bit6 (979~1001) 23 990, Bit14 (972~992) 21 982,
3544 23:45:42.705099 TX Bit7 (981~1000) 20 990, Bit15 (967~986) 20 976,
3545 23:45:42.705515
3546 23:45:42.705842 Write Rank1 MR14 =0x14
3547 23:45:42.715456
3548 23:45:42.718971 CH=1, VrefRange= 0, VrefLevel = 20
3549 23:45:42.722344 TX Bit0 (980~1004) 25 992, Bit8 (969~991) 23 980,
3550 23:45:42.725473 TX Bit1 (979~1001) 23 990, Bit9 (970~990) 21 980,
3551 23:45:42.732077 TX Bit2 (978~1000) 23 989, Bit10 (971~992) 22 981,
3552 23:45:42.735828 TX Bit3 (977~998) 22 987, Bit11 (972~993) 22 982,
3553 23:45:42.738641 TX Bit4 (978~1001) 24 989, Bit12 (972~992) 21 982,
3554 23:45:42.746016 TX Bit5 (979~1003) 25 991, Bit13 (973~993) 21 983,
3555 23:45:42.749155 TX Bit6 (979~1001) 23 990, Bit14 (972~992) 21 982,
3556 23:45:42.755521 TX Bit7 (980~1000) 21 990, Bit15 (967~986) 20 976,
3557 23:45:42.756047
3558 23:45:42.756373 Write Rank1 MR14 =0x16
3559 23:45:42.766211
3560 23:45:42.769894 CH=1, VrefRange= 0, VrefLevel = 22
3561 23:45:42.773177 TX Bit0 (979~1004) 26 991, Bit8 (969~991) 23 980,
3562 23:45:42.776553 TX Bit1 (978~1002) 25 990, Bit9 (969~991) 23 980,
3563 23:45:42.783353 TX Bit2 (978~1000) 23 989, Bit10 (971~992) 22 981,
3564 23:45:42.786530 TX Bit3 (976~998) 23 987, Bit11 (972~993) 22 982,
3565 23:45:42.789653 TX Bit4 (978~1002) 25 990, Bit12 (972~993) 22 982,
3566 23:45:42.796618 TX Bit5 (979~1004) 26 991, Bit13 (972~993) 22 982,
3567 23:45:42.799647 TX Bit6 (978~1002) 25 990, Bit14 (971~992) 22 981,
3568 23:45:42.806030 TX Bit7 (979~1001) 23 990, Bit15 (967~987) 21 977,
3569 23:45:42.806449
3570 23:45:42.809208 wait MRW command Rank1 MR14 =0x18 fired (1)
3571 23:45:42.809617 Write Rank1 MR14 =0x18
3572 23:45:42.820730
3573 23:45:42.824150 CH=1, VrefRange= 0, VrefLevel = 24
3574 23:45:42.827461 TX Bit0 (979~1005) 27 992, Bit8 (969~991) 23 980,
3575 23:45:42.830920 TX Bit1 (978~1003) 26 990, Bit9 (969~991) 23 980,
3576 23:45:42.837277 TX Bit2 (977~1000) 24 988, Bit10 (971~993) 23 982,
3577 23:45:42.840745 TX Bit3 (976~999) 24 987, Bit11 (972~993) 22 982,
3578 23:45:42.843947 TX Bit4 (978~1002) 25 990, Bit12 (972~993) 22 982,
3579 23:45:42.850576 TX Bit5 (979~1004) 26 991, Bit13 (972~994) 23 983,
3580 23:45:42.854010 TX Bit6 (978~1003) 26 990, Bit14 (971~992) 22 981,
3581 23:45:42.860409 TX Bit7 (979~1001) 23 990, Bit15 (967~987) 21 977,
3582 23:45:42.860826
3583 23:45:42.861149 Write Rank1 MR14 =0x1a
3584 23:45:42.872018
3585 23:45:42.874818 CH=1, VrefRange= 0, VrefLevel = 26
3586 23:45:42.878250 TX Bit0 (979~1005) 27 992, Bit8 (969~992) 24 980,
3587 23:45:42.881612 TX Bit1 (979~1003) 25 991, Bit9 (969~991) 23 980,
3588 23:45:42.887898 TX Bit2 (977~1001) 25 989, Bit10 (970~993) 24 981,
3589 23:45:42.891467 TX Bit3 (976~999) 24 987, Bit11 (971~994) 24 982,
3590 23:45:42.894603 TX Bit4 (978~1003) 26 990, Bit12 (971~993) 23 982,
3591 23:45:42.900930 TX Bit5 (979~1005) 27 992, Bit13 (971~995) 25 983,
3592 23:45:42.904484 TX Bit6 (978~1003) 26 990, Bit14 (970~993) 24 981,
3593 23:45:42.911386 TX Bit7 (979~1002) 24 990, Bit15 (967~988) 22 977,
3594 23:45:42.911950
3595 23:45:42.912277 Write Rank1 MR14 =0x1c
3596 23:45:42.922328
3597 23:45:42.925495 CH=1, VrefRange= 0, VrefLevel = 28
3598 23:45:42.928867 TX Bit0 (978~1006) 29 992, Bit8 (968~992) 25 980,
3599 23:45:42.931946 TX Bit1 (978~1004) 27 991, Bit9 (969~991) 23 980,
3600 23:45:42.938807 TX Bit2 (977~1001) 25 989, Bit10 (970~993) 24 981,
3601 23:45:42.942178 TX Bit3 (975~999) 25 987, Bit11 (971~994) 24 982,
3602 23:45:42.945907 TX Bit4 (978~1004) 27 991, Bit12 (971~993) 23 982,
3603 23:45:42.951990 TX Bit5 (978~1006) 29 992, Bit13 (971~995) 25 983,
3604 23:45:42.955032 TX Bit6 (978~1004) 27 991, Bit14 (971~993) 23 982,
3605 23:45:42.961852 TX Bit7 (979~1003) 25 991, Bit15 (966~988) 23 977,
3606 23:45:42.962268
3607 23:45:42.962589 Write Rank1 MR14 =0x1e
3608 23:45:42.972919
3609 23:45:42.976148 CH=1, VrefRange= 0, VrefLevel = 30
3610 23:45:42.979698 TX Bit0 (979~1006) 28 992, Bit8 (968~992) 25 980,
3611 23:45:42.983057 TX Bit1 (978~1004) 27 991, Bit9 (969~992) 24 980,
3612 23:45:42.989321 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
3613 23:45:42.993000 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
3614 23:45:42.996469 TX Bit4 (978~1004) 27 991, Bit12 (971~994) 24 982,
3615 23:45:43.002942 TX Bit5 (979~1005) 27 992, Bit13 (971~994) 24 982,
3616 23:45:43.006504 TX Bit6 (978~1005) 28 991, Bit14 (970~993) 24 981,
3617 23:45:43.012796 TX Bit7 (978~1003) 26 990, Bit15 (966~989) 24 977,
3618 23:45:43.013300
3619 23:45:43.013627 Write Rank1 MR14 =0x20
3620 23:45:43.024251
3621 23:45:43.027228 CH=1, VrefRange= 0, VrefLevel = 32
3622 23:45:43.031467 TX Bit0 (979~1006) 28 992, Bit8 (968~992) 25 980,
3623 23:45:43.034352 TX Bit1 (978~1004) 27 991, Bit9 (969~992) 24 980,
3624 23:45:43.040561 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
3625 23:45:43.043922 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
3626 23:45:43.047284 TX Bit4 (978~1004) 27 991, Bit12 (971~994) 24 982,
3627 23:45:43.053640 TX Bit5 (979~1005) 27 992, Bit13 (971~994) 24 982,
3628 23:45:43.057255 TX Bit6 (978~1005) 28 991, Bit14 (970~993) 24 981,
3629 23:45:43.064046 TX Bit7 (978~1003) 26 990, Bit15 (966~989) 24 977,
3630 23:45:43.064579
3631 23:45:43.064909 Write Rank1 MR14 =0x22
3632 23:45:43.074956
3633 23:45:43.078386 CH=1, VrefRange= 0, VrefLevel = 34
3634 23:45:43.081120 TX Bit0 (979~1006) 28 992, Bit8 (968~992) 25 980,
3635 23:45:43.084589 TX Bit1 (978~1004) 27 991, Bit9 (969~992) 24 980,
3636 23:45:43.091873 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
3637 23:45:43.094554 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
3638 23:45:43.098156 TX Bit4 (978~1004) 27 991, Bit12 (971~994) 24 982,
3639 23:45:43.104493 TX Bit5 (979~1005) 27 992, Bit13 (971~994) 24 982,
3640 23:45:43.107887 TX Bit6 (978~1005) 28 991, Bit14 (970~993) 24 981,
3641 23:45:43.114425 TX Bit7 (978~1003) 26 990, Bit15 (966~989) 24 977,
3642 23:45:43.114973
3643 23:45:43.115489 Write Rank1 MR14 =0x24
3644 23:45:43.125709
3645 23:45:43.126220 CH=1, VrefRange= 0, VrefLevel = 36
3646 23:45:43.132385 TX Bit0 (979~1006) 28 992, Bit8 (968~992) 25 980,
3647 23:45:43.135838 TX Bit1 (978~1004) 27 991, Bit9 (969~992) 24 980,
3648 23:45:43.142188 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
3649 23:45:43.145545 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
3650 23:45:43.148697 TX Bit4 (978~1004) 27 991, Bit12 (971~994) 24 982,
3651 23:45:43.155579 TX Bit5 (979~1005) 27 992, Bit13 (971~994) 24 982,
3652 23:45:43.158574 TX Bit6 (978~1005) 28 991, Bit14 (970~993) 24 981,
3653 23:45:43.165549 TX Bit7 (978~1003) 26 990, Bit15 (966~989) 24 977,
3654 23:45:43.166061
3655 23:45:43.166388 Write Rank1 MR14 =0x26
3656 23:45:43.176310
3657 23:45:43.179630 CH=1, VrefRange= 0, VrefLevel = 38
3658 23:45:43.182484 TX Bit0 (979~1006) 28 992, Bit8 (968~992) 25 980,
3659 23:45:43.186257 TX Bit1 (978~1004) 27 991, Bit9 (969~992) 24 980,
3660 23:45:43.192739 TX Bit2 (977~1002) 26 989, Bit10 (970~993) 24 981,
3661 23:45:43.196146 TX Bit3 (975~999) 25 987, Bit11 (970~994) 25 982,
3662 23:45:43.199768 TX Bit4 (978~1004) 27 991, Bit12 (971~994) 24 982,
3663 23:45:43.206083 TX Bit5 (979~1005) 27 992, Bit13 (971~994) 24 982,
3664 23:45:43.209047 TX Bit6 (978~1005) 28 991, Bit14 (970~993) 24 981,
3665 23:45:43.215858 TX Bit7 (978~1003) 26 990, Bit15 (966~989) 24 977,
3666 23:45:43.216554
3667 23:45:43.217172
3668 23:45:43.219652 TX Vref found, early break! 386< 387
3669 23:45:43.222898 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =735/100 ps
3670 23:45:43.226045 u1DelayCellOfst[0]=6 cells (5 PI)
3671 23:45:43.229042 u1DelayCellOfst[1]=5 cells (4 PI)
3672 23:45:43.232634 u1DelayCellOfst[2]=2 cells (2 PI)
3673 23:45:43.235972 u1DelayCellOfst[3]=0 cells (0 PI)
3674 23:45:43.239349 u1DelayCellOfst[4]=5 cells (4 PI)
3675 23:45:43.242864 u1DelayCellOfst[5]=6 cells (5 PI)
3676 23:45:43.243277 u1DelayCellOfst[6]=5 cells (4 PI)
3677 23:45:43.245863 u1DelayCellOfst[7]=3 cells (3 PI)
3678 23:45:43.249329 Byte0, DQ PI dly=987, DQM PI dly= 989
3679 23:45:43.256133 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 27)
3680 23:45:43.256709
3681 23:45:43.259570 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 27)
3682 23:45:43.259984
3683 23:45:43.262505 u1DelayCellOfst[8]=3 cells (3 PI)
3684 23:45:43.265782 u1DelayCellOfst[9]=3 cells (3 PI)
3685 23:45:43.269246 u1DelayCellOfst[10]=5 cells (4 PI)
3686 23:45:43.272908 u1DelayCellOfst[11]=6 cells (5 PI)
3687 23:45:43.276313 u1DelayCellOfst[12]=6 cells (5 PI)
3688 23:45:43.279292 u1DelayCellOfst[13]=6 cells (5 PI)
3689 23:45:43.279814 u1DelayCellOfst[14]=5 cells (4 PI)
3690 23:45:43.282898 u1DelayCellOfst[15]=0 cells (0 PI)
3691 23:45:43.286339 Byte1, DQ PI dly=977, DQM PI dly= 979
3692 23:45:43.293214 Final DQ PI dly(LargeUI, SmallUI, PI) =(3 ,6, 17)
3693 23:45:43.293639
3694 23:45:43.296549 OEN DQ PI dly(LargeUI, SmallUI, PI) =(3 ,3, 17)
3695 23:45:43.296964
3696 23:45:43.299341 Write Rank1 MR14 =0x1e
3697 23:45:43.299811
3698 23:45:43.300132 Final TX Range 0 Vref 30
3699 23:45:43.300433
3700 23:45:43.306236 [TX_K_DQM_WITH_WDBI] Step1: K DQM with DBI_ON, and check DQM window spec.
3701 23:45:43.306730
3702 23:45:43.312673 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3703 23:45:43.319705 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3704 23:45:43.329414 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3705 23:45:43.329832 Write Rank1 MR3 =0xb0
3706 23:45:43.332802 DramC Write-DBI on
3707 23:45:43.333353 ==
3708 23:45:43.336203 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3709 23:45:43.339223 fsp= 1, odt_onoff= 1, Byte mode= 0
3710 23:45:43.339711 ==
3711 23:45:43.346527 [TxWindowPerbitCal] calType=1, VrefScanEnable 0
3712 23:45:43.346989
3713 23:45:43.347326 Begin, DQ Scan Range 699~763
3714 23:45:43.349252
3715 23:45:43.349663
3716 23:45:43.350013 TX Vref Scan disable
3717 23:45:43.352998 699 |2 4 59|[0] xxxxxxxx xxxxxxxx [MSB]
3718 23:45:43.355855 700 |2 4 60|[0] xxxxxxxx xxxxxxxx [MSB]
3719 23:45:43.359218 701 |2 4 61|[0] xxxxxxxx xxxxxxxx [MSB]
3720 23:45:43.362832 702 |2 4 62|[0] xxxxxxxx xxxxxxxx [MSB]
3721 23:45:43.366010 703 |2 4 63|[0] xxxxxxxx xxxxxxxx [MSB]
3722 23:45:43.372401 704 |2 6 0|[0] xxxxxxxx xxxxxxxx [MSB]
3723 23:45:43.375855 705 |2 6 1|[0] xxxxxxxx xxxxxxxx [MSB]
3724 23:45:43.378682 706 |2 6 2|[0] xxxxxxxx xxxxxxxx [MSB]
3725 23:45:43.382210 707 |2 6 3|[0] xxxxxxxx xxxxxxxx [MSB]
3726 23:45:43.385640 708 |2 6 4|[0] xxxxxxxx xxxxxxxx [MSB]
3727 23:45:43.388835 709 |2 6 5|[0] xxxxxxxx xxxxxxxx [MSB]
3728 23:45:43.392314 710 |2 6 6|[0] xxxxxxxx xxxxxxxx [MSB]
3729 23:45:43.395984 711 |2 6 7|[0] xxxxxxxx xxxxxxxx [MSB]
3730 23:45:43.398858 712 |2 6 8|[0] xxxxxxxx xxxxxxxx [MSB]
3731 23:45:43.402302 713 |2 6 9|[0] xxxxxxxx oooooooo [MSB]
3732 23:45:43.405912 714 |2 6 10|[0] xxxxxxxx oooooooo [MSB]
3733 23:45:43.409193 715 |2 6 11|[0] xxxxxxxx oooooooo [MSB]
3734 23:45:43.412398 716 |2 6 12|[0] xxxxxxxx oooooooo [MSB]
3735 23:45:43.415881 717 |2 6 13|[0] xxxxxxxx oooooooo [MSB]
3736 23:45:43.419127 718 |2 6 14|[0] xxxxxxxx oooooooo [MSB]
3737 23:45:43.422337 719 |2 6 15|[0] xxxxxxxx oooooooo [MSB]
3738 23:45:43.425979 720 |2 6 16|[0] xxxxxxxx oooooooo [MSB]
3739 23:45:43.429678 721 |2 6 17|[0] xxxxxxxx oooooooo [MSB]
3740 23:45:43.437550 737 |2 6 33|[0] oooooooo xxxxxxxx [MSB]
3741 23:45:43.440896 738 |2 6 34|[0] oooooooo xxxxxxxx [MSB]
3742 23:45:43.444329 739 |2 6 35|[0] oooooooo xxxxxxxx [MSB]
3743 23:45:43.447699 740 |2 6 36|[0] oooooooo xxxxxxxx [MSB]
3744 23:45:43.450674 741 |2 6 37|[0] oooooooo xxxxxxxx [MSB]
3745 23:45:43.454188 742 |2 6 38|[0] oooooooo xxxxxxxx [MSB]
3746 23:45:43.457445 743 |2 6 39|[0] oooooooo xxxxxxxx [MSB]
3747 23:45:43.460966 744 |2 6 40|[0] oooooooo xxxxxxxx [MSB]
3748 23:45:43.464544 745 |2 6 41|[0] oooooooo xxxxxxxx [MSB]
3749 23:45:43.467595 746 |2 6 42|[0] oooooooo xxxxxxxx [MSB]
3750 23:45:43.470980 747 |2 6 43|[0] oooooooo xxxxxxxx [MSB]
3751 23:45:43.474449 748 |2 6 44|[0] oooooooo xxxxxxxx [MSB]
3752 23:45:43.477167 749 |2 6 45|[0] oooooooo xxxxxxxx [MSB]
3753 23:45:43.480942 750 |2 6 46|[0] oooooooo xxxxxxxx [MSB]
3754 23:45:43.484280 751 |2 6 47|[0] xxxxxxxx xxxxxxxx [MSB]
3755 23:45:43.487211 Byte0, DQ PI dly=736, DQM PI dly= 736
3756 23:45:43.494011 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 32)
3757 23:45:43.494479
3758 23:45:43.497292 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 32)
3759 23:45:43.497744
3760 23:45:43.500533 Byte1, DQ PI dly=724, DQM PI dly= 724
3761 23:45:43.507288 Final DQ PI dly(LargeUI, SmallUI, PI) =(2 ,6, 20)
3762 23:45:43.507932
3763 23:45:43.510873 OEN DQ PI dly(LargeUI, SmallUI, PI) =(2 ,3, 20)
3764 23:45:43.511283
3765 23:45:43.517551 Before -1MCK, ucdq_final_ui_large_dqs0 = 2, ucdq_final_ui_large_dqs1 = 2
3766 23:45:43.524003 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3767 23:45:43.530779 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3768 23:45:43.534118 Write Rank1 MR3 =0x30
3769 23:45:43.534524 DramC Write-DBI off
3770 23:45:43.534843
3771 23:45:43.537199 [DATLAT]
3772 23:45:43.540512 Freq=1600, CH1 RK1, use_rxtx_scan=0
3773 23:45:43.540960
3774 23:45:43.541406 DATLAT Default: 0x10
3775 23:45:43.543714 7, 0xFFFF, sum=0
3776 23:45:43.544150 8, 0xFFFF, sum=0
3777 23:45:43.547225 9, 0xFFFF, sum=0
3778 23:45:43.547707 10, 0xFFFF, sum=0
3779 23:45:43.550096 11, 0xFFFF, sum=0
3780 23:45:43.550533 12, 0xFFFF, sum=0
3781 23:45:43.553429 13, 0xFFFF, sum=0
3782 23:45:43.553864 14, 0x0, sum=1
3783 23:45:43.554302 15, 0x0, sum=2
3784 23:45:43.557428 16, 0x0, sum=3
3785 23:45:43.557981 17, 0x0, sum=4
3786 23:45:43.563751 pattern=2 first_step=14 total pass=5 best_step=16
3787 23:45:43.564188 ==
3788 23:45:43.567388 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3789 23:45:43.570025 fsp= 1, odt_onoff= 1, Byte mode= 0
3790 23:45:43.570586 ==
3791 23:45:43.573722 Start DQ dly to find pass range UseTestEngine =1
3792 23:45:43.580469 x-axis: bit #, y-axis: DQ dly (-127~63)
3793 23:45:43.581005 RX Vref Scan = 0
3794 23:45:43.583281 -26, [0] xxxxxxxx xxxxxxxx [MSB]
3795 23:45:43.586967 -25, [0] xxxxxxxx xxxxxxxx [MSB]
3796 23:45:43.590061 -24, [0] xxxxxxxx xxxxxxxx [MSB]
3797 23:45:43.593122 -23, [0] xxxxxxxx xxxxxxxx [MSB]
3798 23:45:43.593560 -22, [0] xxxxxxxx xxxxxxxx [MSB]
3799 23:45:43.597261 -21, [0] xxxxxxxx xxxxxxxx [MSB]
3800 23:45:43.600086 -20, [0] xxxxxxxx xxxxxxxx [MSB]
3801 23:45:43.603106 -19, [0] xxxxxxxx xxxxxxxx [MSB]
3802 23:45:43.606460 -18, [0] xxxxxxxx xxxxxxxx [MSB]
3803 23:45:43.609585 -17, [0] xxxxxxxx xxxxxxxx [MSB]
3804 23:45:43.613621 -16, [0] xxxxxxxx xxxxxxxx [MSB]
3805 23:45:43.616534 -15, [0] xxxxxxxx xxxxxxxx [MSB]
3806 23:45:43.616956 -14, [0] xxxxxxxx xxxxxxxx [MSB]
3807 23:45:43.619545 -13, [0] xxxxxxxx xxxxxxxx [MSB]
3808 23:45:43.622985 -12, [0] xxxxxxxx xxxxxxxx [MSB]
3809 23:45:43.626252 -11, [0] xxxxxxxx xxxxxxxx [MSB]
3810 23:45:43.629543 -10, [0] xxxxxxxx xxxxxxxx [MSB]
3811 23:45:43.632921 -9, [0] xxxxxxxx xxxxxxxx [MSB]
3812 23:45:43.636406 -8, [0] xxxxxxxx xxxxxxxx [MSB]
3813 23:45:43.639756 -7, [0] xxxxxxxx xxxxxxxx [MSB]
3814 23:45:43.640300 -6, [0] xxxxxxxx xxxxxxxx [MSB]
3815 23:45:43.643299 -5, [0] xxxxxxxx xxxxxxxx [MSB]
3816 23:45:43.646302 -4, [0] xxxxxxxx xxxxxxxx [MSB]
3817 23:45:43.649648 -3, [0] xxxxxxxx xxxxxxxo [MSB]
3818 23:45:43.653164 -2, [0] xxxoxxxx xxxxxxxo [MSB]
3819 23:45:43.656423 -1, [0] xxxoxxxx xoxxxxxo [MSB]
3820 23:45:43.659900 0, [0] xxxoxxxx ooxxxxxo [MSB]
3821 23:45:43.660340 1, [0] xxooxxxx ooxxxxxo [MSB]
3822 23:45:43.663299 2, [0] xxooxxxx ooxxxxxo [MSB]
3823 23:45:43.666839 3, [0] oxooxxxo oooxxxxo [MSB]
3824 23:45:43.669980 4, [0] oxoooxxo ooooooxo [MSB]
3825 23:45:43.673214 5, [0] ooooooxo oooooooo [MSB]
3826 23:45:43.676568 32, [0] oooooooo ooooooox [MSB]
3827 23:45:43.680050 33, [0] oooooooo ooooooox [MSB]
3828 23:45:43.683670 34, [0] oooooooo ooooooox [MSB]
3829 23:45:43.687064 35, [0] oooxoooo oxooooox [MSB]
3830 23:45:43.689947 36, [0] oooxoooo xxooooox [MSB]
3831 23:45:43.690495 37, [0] ooxxoooo xxooooox [MSB]
3832 23:45:43.693380 38, [0] ooxxoooo xxooooox [MSB]
3833 23:45:43.696449 39, [0] ooxxooox xxxoooox [MSB]
3834 23:45:43.699962 40, [0] oxxxxoox xxxoooox [MSB]
3835 23:45:43.703257 41, [0] xxxxxxox xxxxxxxx [MSB]
3836 23:45:43.706271 42, [0] xxxxxxxx xxxxxxxx [MSB]
3837 23:45:43.710046 iDelay=42, Bit 0, Center 21 (3 ~ 40) 38
3838 23:45:43.713119 iDelay=42, Bit 1, Center 22 (5 ~ 39) 35
3839 23:45:43.715969 iDelay=42, Bit 2, Center 18 (1 ~ 36) 36
3840 23:45:43.719700 iDelay=42, Bit 3, Center 16 (-2 ~ 34) 37
3841 23:45:43.722489 iDelay=42, Bit 4, Center 21 (4 ~ 39) 36
3842 23:45:43.725790 iDelay=42, Bit 5, Center 22 (5 ~ 40) 36
3843 23:45:43.729206 iDelay=42, Bit 6, Center 23 (6 ~ 41) 36
3844 23:45:43.732889 iDelay=42, Bit 7, Center 20 (3 ~ 38) 36
3845 23:45:43.736219 iDelay=42, Bit 8, Center 17 (0 ~ 35) 36
3846 23:45:43.739356 iDelay=42, Bit 9, Center 16 (-1 ~ 34) 36
3847 23:45:43.746098 iDelay=42, Bit 10, Center 20 (3 ~ 38) 36
3848 23:45:43.749367 iDelay=42, Bit 11, Center 22 (4 ~ 40) 37
3849 23:45:43.752507 iDelay=42, Bit 12, Center 22 (4 ~ 40) 37
3850 23:45:43.755983 iDelay=42, Bit 13, Center 22 (4 ~ 40) 37
3851 23:45:43.759147 iDelay=42, Bit 14, Center 22 (5 ~ 40) 36
3852 23:45:43.762616 iDelay=42, Bit 15, Center 14 (-3 ~ 31) 35
3853 23:45:43.763029 ==
3854 23:45:43.769847 Dram Type= 6, Freq= 1596, FreqGroup= 1600, CH_1, rank 1
3855 23:45:43.772711 fsp= 1, odt_onoff= 1, Byte mode= 0
3856 23:45:43.773129 ==
3857 23:45:43.773455 DQS Delay:
3858 23:45:43.773756 DQS0 = 0, DQS1 = 0
3859 23:45:43.775971 DQM Delay:
3860 23:45:43.776381 DQM0 = 20, DQM1 = 19
3861 23:45:43.779491 DQ Delay:
3862 23:45:43.782237 DQ0 =21, DQ1 =22, DQ2 =18, DQ3 =16
3863 23:45:43.786135 DQ4 =21, DQ5 =22, DQ6 =23, DQ7 =20
3864 23:45:43.789621 DQ8 =17, DQ9 =16, DQ10 =20, DQ11 =22
3865 23:45:43.792222 DQ12 =22, DQ13 =22, DQ14 =22, DQ15 =14
3866 23:45:43.792634
3867 23:45:43.792956
3868 23:45:43.793256
3869 23:45:43.795494 [DramC_TX_OE_Calibration] TA2
3870 23:45:43.795911 Original DQ_B0 (3 6) =30, OEN = 27
3871 23:45:43.798852 Original DQ_B1 (3 6) =30, OEN = 27
3872 23:45:43.802582 23, 0x0, End_B0=23 End_B1=23
3873 23:45:43.806076 24, 0x0, End_B0=24 End_B1=24
3874 23:45:43.808753 25, 0x0, End_B0=25 End_B1=25
3875 23:45:43.812396 26, 0x0, End_B0=26 End_B1=26
3876 23:45:43.812815 27, 0x0, End_B0=27 End_B1=27
3877 23:45:43.815845 28, 0x0, End_B0=28 End_B1=28
3878 23:45:43.819362 29, 0x0, End_B0=29 End_B1=29
3879 23:45:43.822543 30, 0x0, End_B0=30 End_B1=30
3880 23:45:43.822962 31, 0xFFFF, End_B0=30 End_B1=30
3881 23:45:43.829000 Byte0 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3882 23:45:43.836314 Byte1 end_step=30 best_step=27 Final TX OE(2T, 0.5T) = (3, 3)
3883 23:45:43.836821
3884 23:45:43.837148
3885 23:45:43.837448 Write Rank1 MR23 =0x3f
3886 23:45:43.838981 [DQSOSC]
3887 23:45:43.846249 [DQSOSCAuto] RK1, (LSB)MR18= 0xcece, (MSB)MR19= 0x202, tDQSOscB0 = 438 ps tDQSOscB1 = 438 ps
3888 23:45:43.852456 CH1_RK1: MR19=0x202, MR18=0xCECE, DQSOSC=438, MR23=63, INC=12, DEC=19
3889 23:45:43.855761 Write Rank1 MR23 =0x3f
3890 23:45:43.856266 [DQSOSC]
3891 23:45:43.862347 [DQSOSCAuto] RK1, (LSB)MR18= 0xcccc, (MSB)MR19= 0x202, tDQSOscB0 = 439 ps tDQSOscB1 = 439 ps
3892 23:45:43.866012 CH1 RK1: MR19=202, MR18=CCCC
3893 23:45:43.869052 [RxdqsGatingPostProcess] freq 1600
3894 23:45:43.875846 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
3895 23:45:43.876354 Rank: 0
3896 23:45:43.878940 best DQS0 dly(2T, 0.5T) = (2, 6)
3897 23:45:43.882523 best DQS1 dly(2T, 0.5T) = (2, 6)
3898 23:45:43.885782 best DQS0 P1 dly(2T, 0.5T) = (3, 2)
3899 23:45:43.888891 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3900 23:45:43.889504 Rank: 1
3901 23:45:43.891966 best DQS0 dly(2T, 0.5T) = (2, 5)
3902 23:45:43.895151 best DQS1 dly(2T, 0.5T) = (2, 6)
3903 23:45:43.899213 best DQS0 P1 dly(2T, 0.5T) = (3, 1)
3904 23:45:43.902090 best DQS1 P1 dly(2T, 0.5T) = (3, 2)
3905 23:45:43.905812 TX_dly_DQSgated check: min 2 max 3, ChangeDQSINCTL=-1
3906 23:45:43.908853 DQSINCTL=5, RANKINCTL=3, u4XRTR2R=9
3907 23:45:43.915771 [DualRankRxdatlatCal] RK0: 16, RK1: 16, Final_Datlat 16
3908 23:45:43.916282
3909 23:45:43.916609
3910 23:45:43.919383 [Calibration Summary] Freqency 1600
3911 23:45:43.919957 CH 0, Rank 0
3912 23:45:43.920286 All Pass.
3913 23:45:43.920591
3914 23:45:43.921628 CH 0, Rank 1
3915 23:45:43.922036 All Pass.
3916 23:45:43.922357
3917 23:45:43.922655 CH 1, Rank 0
3918 23:45:43.925315 All Pass.
3919 23:45:43.925727
3920 23:45:43.926049 CH 1, Rank 1
3921 23:45:43.926349 All Pass.
3922 23:45:43.926635
3923 23:45:43.931780 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3924 23:45:43.939242 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3925 23:45:43.948831 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3926 23:45:43.949342 Write Rank0 MR3 =0xb0
3927 23:45:43.955534 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3928 23:45:43.962259 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3929 23:45:43.968848 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3930 23:45:43.972106 Write Rank1 MR3 =0xb0
3931 23:45:43.978767 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3932 23:45:43.985139 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3933 23:45:43.991484 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3934 23:45:43.994922 Write Rank0 MR3 =0xb0
3935 23:45:44.001708 Before -1MCK, ucdq_final_ui_large_dqs0 = 3, ucdq_final_ui_large_dqs1 = 3
3936 23:45:44.008621 Before -1MCK, ucdq_final_dqm_ui_large_dqs0 = 3, ucdq_final_dqm_ui_large_dqs1 = 3
3937 23:45:44.014860 After -1MCK, ucdq_final_dqm_ui_large_dqs0 = 2, ucdq_final_dqm_ui_large_dqs1 = 2
3938 23:45:44.015355 Write Rank1 MR3 =0xb0
3939 23:45:44.018238 DramC Write-DBI on
3940 23:45:44.021853 [GetDramInforAfterCalByMRR] Vendor 6.
3941 23:45:44.024926 [GetDramInforAfterCalByMRR] Revision 505.
3942 23:45:44.025334 MR8 1111
3943 23:45:44.031559 CH0, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3944 23:45:44.031976 MR8 1111
3945 23:45:44.038094 CH0, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3946 23:45:44.038508 MR8 1111
3947 23:45:44.041537 CH1, RK0, DieNum 1, Density 80000000, RKsize 80000000.
3948 23:45:44.045065 MR8 1111
3949 23:45:44.047932 CH1, RK1, DieNum 1, Density 80000000, RKsize 80000000.
3950 23:45:44.058075 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 119, TRFCpb 44, TRFCpb_05T 0
3951 23:45:44.058596 Write Rank0 MR13 =0xd0
3952 23:45:44.061451 Write Rank1 MR13 =0xd0
3953 23:45:44.064757 Write Rank0 MR13 =0xd0
3954 23:45:44.065263 Write Rank1 MR13 =0xd0
3955 23:45:44.068066 Save calibration result to emmc
3956 23:45:44.068584
3957 23:45:44.068917
3958 23:45:44.071839 [DramcModeReg_Check] Freq_1600, FSP_1
3959 23:45:44.075165 FSP_1, CH_0, RK0
3960 23:45:44.075759 Write Rank0 MR13 =0xd8
3961 23:45:44.077926 MR12 = 0x5e (global = 0x5e) match
3962 23:45:44.081171 MR14 = 0x1a (global = 0x1a) match
3963 23:45:44.084639 FSP_1, CH_0, RK1
3964 23:45:44.085053 Write Rank1 MR13 =0xd8
3965 23:45:44.088203 MR12 = 0x60 (global = 0x60) match
3966 23:45:44.091490 MR14 = 0x20 (global = 0x20) match
3967 23:45:44.094699 FSP_1, CH_1, RK0
3968 23:45:44.095222 Write Rank0 MR13 =0xd8
3969 23:45:44.098237 MR12 = 0x5e (global = 0x5e) match
3970 23:45:44.101235 MR14 = 0x20 (global = 0x20) match
3971 23:45:44.104681 FSP_1, CH_1, RK1
3972 23:45:44.105191 Write Rank1 MR13 =0xd8
3973 23:45:44.108244 MR12 = 0x5c (global = 0x5c) match
3974 23:45:44.111345 MR14 = 0x1e (global = 0x1e) match
3975 23:45:44.111898
3976 23:45:44.114584 [MEM_TEST] 02: After DFS, before run time config
3977 23:45:44.126868 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
3978 23:45:44.127360
3979 23:45:44.127769 [TA2_TEST]
3980 23:45:44.128077 === TA2 HW
3981 23:45:44.130159 TA2 PAT: XTALK
3982 23:45:44.133670 HW channel(0) Rank(0), TA2 pass, pass_cnt:1, err_cnt:0
3983 23:45:44.140744 HW channel(0) Rank(1), TA2 pass, pass_cnt:2, err_cnt:0
3984 23:45:44.143643 HW channel(1) Rank(0), TA2 pass, pass_cnt:3, err_cnt:0
3985 23:45:44.146727 HW channel(1) Rank(1), TA2 pass, pass_cnt:4, err_cnt:0
3986 23:45:44.150300
3987 23:45:44.150710
3988 23:45:44.151031 Settings after calibration
3989 23:45:44.151332
3990 23:45:44.153695 [DramcRunTimeConfig]
3991 23:45:44.156682 TransferPLLToSPMControl - MODE SW PHYPLL
3992 23:45:44.157121 TX_TRACKING: ON
3993 23:45:44.159879 RX_TRACKING: ON
3994 23:45:44.160250 HW_GATING: ON
3995 23:45:44.163265 HW_GATING DBG: OFF
3996 23:45:44.163692 ddr_geometry:1
3997 23:45:44.166946 ddr_geometry:1
3998 23:45:44.167482 ddr_geometry:1
3999 23:45:44.170151 ddr_geometry:1
4000 23:45:44.170554 ddr_geometry:1
4001 23:45:44.170870 ddr_geometry:1
4002 23:45:44.173467 ddr_geometry:1
4003 23:45:44.173868 ddr_geometry:1
4004 23:45:44.177039 High Freq DUMMY_READ_FOR_TRACKING: ON
4005 23:45:44.179824 ZQCS_ENABLE_LP4: OFF
4006 23:45:44.183728 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
4007 23:45:44.187134 DUMMY_READ_FOR_DQS_GATING_RETRY: OFF
4008 23:45:44.187686 SPM_CONTROL_AFTERK: ON
4009 23:45:44.190239 IMPEDANCE_TRACKING: ON
4010 23:45:44.190744 TEMP_SENSOR: ON
4011 23:45:44.193389 PER_BANK_REFRESH: ON
4012 23:45:44.193792 HW_SAVE_FOR_SR: ON
4013 23:45:44.199590 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4014 23:45:44.199999 CLK_FREE_FUN_FOR_DRAMC_PSEL: ON
4015 23:45:44.206658 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: ON
4016 23:45:44.207168 Read ODT Tracking: ON
4017 23:45:44.209721 =========================
4018 23:45:44.210125
4019 23:45:44.210444 [TA2_TEST]
4020 23:45:44.210743 === TA2 HW
4021 23:45:44.216808 HW channel(0) Rank(0), TA2 pass, pass_cnt:5, err_cnt:0
4022 23:45:44.219803 HW channel(0) Rank(1), TA2 pass, pass_cnt:6, err_cnt:0
4023 23:45:44.226796 HW channel(1) Rank(0), TA2 pass, pass_cnt:7, err_cnt:0
4024 23:45:44.230006 HW channel(1) Rank(1), TA2 pass, pass_cnt:8, err_cnt:0
4025 23:45:44.230416
4026 23:45:44.232634 [MEM_TEST] 03: After run time config
4027 23:45:44.245137 [MEM_TEST] Rank 0 OK.(uiFixedAddr 0x40000000, Pass count =16384, Fail count =0)
4028 23:45:44.248015 [complex_mem_test] start addr:0x40024000, len:131072
4029 23:45:44.452467 1st complex R/W mem test pass
4030 23:45:44.458938 save_calibration_params with freq_sel:1, frequency:1600, _MappingFreqArray:0
4031 23:45:44.462277 sync preloader write leveling
4032 23:45:44.465209 sync preloader cbt_mr12
4033 23:45:44.469095 sync preloader cbt_clk_dly
4034 23:45:44.469215 sync preloader cbt_cmd_dly
4035 23:45:44.472206 sync preloader cbt_cs
4036 23:45:44.475485 sync preloader cbt_ca_perbit_delay
4037 23:45:44.475609 sync preloader clk_delay
4038 23:45:44.478864 sync preloader dqs_delay
4039 23:45:44.481883 sync preloader u1Gating2T_Save
4040 23:45:44.485226 sync preloader u1Gating05T_Save
4041 23:45:44.488756 sync preloader u1Gatingfine_tune_Save
4042 23:45:44.491856 sync preloader u1Gatingucpass_count_Save
4043 23:45:44.495024 sync preloader u1TxWindowPerbitVref_Save
4044 23:45:44.498534 sync preloader u1TxCenter_min_Save
4045 23:45:44.501895 sync preloader u1TxCenter_max_Save
4046 23:45:44.505477 sync preloader u1Txwin_center_Save
4047 23:45:44.508897 sync preloader u1Txfirst_pass_Save
4048 23:45:44.511821 sync preloader u1Txlast_pass_Save
4049 23:45:44.511962 sync preloader u1RxDatlat_Save
4050 23:45:44.515456 sync preloader u1RxWinPerbitVref_Save
4051 23:45:44.522467 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4052 23:45:44.525136 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4053 23:45:44.528774 sync preloader delay_cell_unit
4054 23:45:44.535512 save_calibration_params with freq_sel:3, frequency:1200, _MappingFreqArray:1
4055 23:45:44.538846 sync preloader write leveling
4056 23:45:44.539257 sync preloader cbt_mr12
4057 23:45:44.542196 sync preloader cbt_clk_dly
4058 23:45:44.545364 sync preloader cbt_cmd_dly
4059 23:45:44.545781 sync preloader cbt_cs
4060 23:45:44.548897 sync preloader cbt_ca_perbit_delay
4061 23:45:44.552240 sync preloader clk_delay
4062 23:45:44.555814 sync preloader dqs_delay
4063 23:45:44.556196 sync preloader u1Gating2T_Save
4064 23:45:44.559086 sync preloader u1Gating05T_Save
4065 23:45:44.562366 sync preloader u1Gatingfine_tune_Save
4066 23:45:44.565663 sync preloader u1Gatingucpass_count_Save
4067 23:45:44.569101 sync preloader u1TxWindowPerbitVref_Save
4068 23:45:44.572316 sync preloader u1TxCenter_min_Save
4069 23:45:44.575859 sync preloader u1TxCenter_max_Save
4070 23:45:44.579113 sync preloader u1Txwin_center_Save
4071 23:45:44.582573 sync preloader u1Txfirst_pass_Save
4072 23:45:44.585876 sync preloader u1Txlast_pass_Save
4073 23:45:44.588948 sync preloader u1RxDatlat_Save
4074 23:45:44.592220 sync preloader u1RxWinPerbitVref_Save
4075 23:45:44.595110 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4076 23:45:44.598565 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4077 23:45:44.601934 sync preloader delay_cell_unit
4078 23:45:44.608878 save_calibration_params with freq_sel:5, frequency:800, _MappingFreqArray:2
4079 23:45:44.611798 sync preloader write leveling
4080 23:45:44.614905 sync preloader cbt_mr12
4081 23:45:44.619057 sync preloader cbt_clk_dly
4082 23:45:44.619650 sync preloader cbt_cmd_dly
4083 23:45:44.621827 sync preloader cbt_cs
4084 23:45:44.625184 sync preloader cbt_ca_perbit_delay
4085 23:45:44.625743 sync preloader clk_delay
4086 23:45:44.628633 sync preloader dqs_delay
4087 23:45:44.631534 sync preloader u1Gating2T_Save
4088 23:45:44.635097 sync preloader u1Gating05T_Save
4089 23:45:44.638362 sync preloader u1Gatingfine_tune_Save
4090 23:45:44.641523 sync preloader u1Gatingucpass_count_Save
4091 23:45:44.645029 sync preloader u1TxWindowPerbitVref_Save
4092 23:45:44.648366 sync preloader u1TxCenter_min_Save
4093 23:45:44.651554 sync preloader u1TxCenter_max_Save
4094 23:45:44.654413 sync preloader u1Txwin_center_Save
4095 23:45:44.657990 sync preloader u1Txfirst_pass_Save
4096 23:45:44.661410 sync preloader u1Txlast_pass_Save
4097 23:45:44.661566 sync preloader u1RxDatlat_Save
4098 23:45:44.664771 sync preloader u1RxWinPerbitVref_Save
4099 23:45:44.671206 sync preloader u1RxWinPerbitDQ_firsbypass_Save
4100 23:45:44.674793 sync preloader u1RxWinPerbitDQ_lastbypass_Save
4101 23:45:44.677815 sync preloader delay_cell_unit
4102 23:45:44.681264 just_for_test_dump_coreboot_params dump all params
4103 23:45:44.684425 dump source = 0x0
4104 23:45:44.684511 dump params frequency:1600
4105 23:45:44.687927 dump params rank number:2
4106 23:45:44.688011
4107 23:45:44.691084 dump params write leveling
4108 23:45:44.694266 write leveling[0][0][0] = 0x1f
4109 23:45:44.697522 write leveling[0][0][1] = 0x18
4110 23:45:44.697603 write leveling[0][1][0] = 0x1b
4111 23:45:44.700823 write leveling[0][1][1] = 0x18
4112 23:45:44.704805 write leveling[1][0][0] = 0x21
4113 23:45:44.707661 write leveling[1][0][1] = 0x17
4114 23:45:44.711098 write leveling[1][1][0] = 0x23
4115 23:45:44.714061 write leveling[1][1][1] = 0x19
4116 23:45:44.714152 dump params cbt_cs
4117 23:45:44.717594 cbt_cs[0][0] = 0x8
4118 23:45:44.717684 cbt_cs[0][1] = 0x8
4119 23:45:44.721114 cbt_cs[1][0] = 0xa
4120 23:45:44.721204 cbt_cs[1][1] = 0xa
4121 23:45:44.724345 dump params cbt_mr12
4122 23:45:44.724436 cbt_mr12[0][0] = 0x1e
4123 23:45:44.727858 cbt_mr12[0][1] = 0x20
4124 23:45:44.730766 cbt_mr12[1][0] = 0x1e
4125 23:45:44.730856 cbt_mr12[1][1] = 0x1c
4126 23:45:44.734255 dump params tx window
4127 23:45:44.734345 tx_center_min[0][0][0] = 980
4128 23:45:44.737499 tx_center_max[0][0][0] = 986
4129 23:45:44.741085 tx_center_min[0][0][1] = 975
4130 23:45:44.744021 tx_center_max[0][0][1] = 981
4131 23:45:44.747777 tx_center_min[0][1][0] = 980
4132 23:45:44.747879 tx_center_max[0][1][0] = 986
4133 23:45:44.750520 tx_center_min[0][1][1] = 978
4134 23:45:44.754130 tx_center_max[0][1][1] = 984
4135 23:45:44.757575 tx_center_min[1][0][0] = 987
4136 23:45:44.760910 tx_center_max[1][0][0] = 992
4137 23:45:44.761027 tx_center_min[1][0][1] = 974
4138 23:45:44.764077 tx_center_max[1][0][1] = 981
4139 23:45:44.767568 tx_center_min[1][1][0] = 987
4140 23:45:44.771199 tx_center_max[1][1][0] = 992
4141 23:45:44.774313 tx_center_min[1][1][1] = 977
4142 23:45:44.774434 tx_center_max[1][1][1] = 982
4143 23:45:44.777908 dump params tx window
4144 23:45:44.781216 tx_win_center[0][0][0] = 986
4145 23:45:44.781383 tx_first_pass[0][0][0] = 975
4146 23:45:44.784499 tx_last_pass[0][0][0] = 998
4147 23:45:44.787789 tx_win_center[0][0][1] = 986
4148 23:45:44.791278 tx_first_pass[0][0][1] = 974
4149 23:45:44.794523 tx_last_pass[0][0][1] = 998
4150 23:45:44.794699 tx_win_center[0][0][2] = 986
4151 23:45:44.797867 tx_first_pass[0][0][2] = 974
4152 23:45:44.800883 tx_last_pass[0][0][2] = 998
4153 23:45:44.804271 tx_win_center[0][0][3] = 980
4154 23:45:44.804431 tx_first_pass[0][0][3] = 968
4155 23:45:44.807443 tx_last_pass[0][0][3] = 992
4156 23:45:44.811052 tx_win_center[0][0][4] = 985
4157 23:45:44.814452 tx_first_pass[0][0][4] = 973
4158 23:45:44.817390 tx_last_pass[0][0][4] = 997
4159 23:45:44.817560 tx_win_center[0][0][5] = 981
4160 23:45:44.821379 tx_first_pass[0][0][5] = 969
4161 23:45:44.824339 tx_last_pass[0][0][5] = 994
4162 23:45:44.827665 tx_win_center[0][0][6] = 983
4163 23:45:44.827834 tx_first_pass[0][0][6] = 971
4164 23:45:44.831264 tx_last_pass[0][0][6] = 995
4165 23:45:44.834256 tx_win_center[0][0][7] = 984
4166 23:45:44.837543 tx_first_pass[0][0][7] = 973
4167 23:45:44.840704 tx_last_pass[0][0][7] = 996
4168 23:45:44.840928 tx_win_center[0][0][8] = 975
4169 23:45:44.844128 tx_first_pass[0][0][8] = 963
4170 23:45:44.847394 tx_last_pass[0][0][8] = 987
4171 23:45:44.850918 tx_win_center[0][0][9] = 978
4172 23:45:44.851080 tx_first_pass[0][0][9] = 967
4173 23:45:44.854502 tx_last_pass[0][0][9] = 990
4174 23:45:44.882459 tx_win_center[0][0][10] = 981
4175 23:45:44.882776 tx_first_pass[0][0][10] = 970
4176 23:45:44.883054 tx_last_pass[0][0][10] = 993
4177 23:45:44.883332 tx_win_center[0][0][11] = 977
4178 23:45:44.883745 tx_first_pass[0][0][11] = 965
4179 23:45:44.884011 tx_last_pass[0][0][11] = 989
4180 23:45:44.884270 tx_win_center[0][0][12] = 978
4181 23:45:44.884526 tx_first_pass[0][0][12] = 967
4182 23:45:44.884778 tx_last_pass[0][0][12] = 990
4183 23:45:44.885030 tx_win_center[0][0][13] = 978
4184 23:45:44.885570 tx_first_pass[0][0][13] = 967
4185 23:45:44.887900 tx_last_pass[0][0][13] = 990
4186 23:45:44.890890 tx_win_center[0][0][14] = 979
4187 23:45:44.891174 tx_first_pass[0][0][14] = 967
4188 23:45:44.894144 tx_last_pass[0][0][14] = 991
4189 23:45:44.897661 tx_win_center[0][0][15] = 981
4190 23:45:44.900747 tx_first_pass[0][0][15] = 970
4191 23:45:44.904181 tx_last_pass[0][0][15] = 993
4192 23:45:44.904474 tx_win_center[0][1][0] = 986
4193 23:45:44.907343 tx_first_pass[0][1][0] = 974
4194 23:45:44.911247 tx_last_pass[0][1][0] = 999
4195 23:45:44.914267 tx_win_center[0][1][1] = 985
4196 23:45:44.917285 tx_first_pass[0][1][1] = 973
4197 23:45:44.917561 tx_last_pass[0][1][1] = 998
4198 23:45:44.920853 tx_win_center[0][1][2] = 986
4199 23:45:44.923975 tx_first_pass[0][1][2] = 975
4200 23:45:44.927435 tx_last_pass[0][1][2] = 998
4201 23:45:44.927721 tx_win_center[0][1][3] = 980
4202 23:45:44.930959 tx_first_pass[0][1][3] = 968
4203 23:45:44.934256 tx_last_pass[0][1][3] = 992
4204 23:45:44.937259 tx_win_center[0][1][4] = 984
4205 23:45:44.940850 tx_first_pass[0][1][4] = 971
4206 23:45:44.941022 tx_last_pass[0][1][4] = 998
4207 23:45:44.943812 tx_win_center[0][1][5] = 981
4208 23:45:44.947123 tx_first_pass[0][1][5] = 969
4209 23:45:44.950370 tx_last_pass[0][1][5] = 994
4210 23:45:44.950597 tx_win_center[0][1][6] = 983
4211 23:45:44.953734 tx_first_pass[0][1][6] = 970
4212 23:45:44.957363 tx_last_pass[0][1][6] = 996
4213 23:45:44.960401 tx_win_center[0][1][7] = 985
4214 23:45:44.964167 tx_first_pass[0][1][7] = 972
4215 23:45:44.964525 tx_last_pass[0][1][7] = 998
4216 23:45:44.967701 tx_win_center[0][1][8] = 978
4217 23:45:44.971146 tx_first_pass[0][1][8] = 966
4218 23:45:44.974303 tx_last_pass[0][1][8] = 990
4219 23:45:44.974847 tx_win_center[0][1][9] = 979
4220 23:45:44.977158 tx_first_pass[0][1][9] = 968
4221 23:45:44.980629 tx_last_pass[0][1][9] = 990
4222 23:45:44.984066 tx_win_center[0][1][10] = 984
4223 23:45:44.987741 tx_first_pass[0][1][10] = 972
4224 23:45:44.988118 tx_last_pass[0][1][10] = 997
4225 23:45:44.990854 tx_win_center[0][1][11] = 978
4226 23:45:44.994262 tx_first_pass[0][1][11] = 967
4227 23:45:44.997657 tx_last_pass[0][1][11] = 990
4228 23:45:45.000575 tx_win_center[0][1][12] = 980
4229 23:45:45.000742 tx_first_pass[0][1][12] = 968
4230 23:45:45.004053 tx_last_pass[0][1][12] = 992
4231 23:45:45.007449 tx_win_center[0][1][13] = 980
4232 23:45:45.010359 tx_first_pass[0][1][13] = 969
4233 23:45:45.014363 tx_last_pass[0][1][13] = 991
4234 23:45:45.014553 tx_win_center[0][1][14] = 980
4235 23:45:45.017498 tx_first_pass[0][1][14] = 968
4236 23:45:45.020478 tx_last_pass[0][1][14] = 992
4237 23:45:45.023529 tx_win_center[0][1][15] = 982
4238 23:45:45.027162 tx_first_pass[0][1][15] = 970
4239 23:45:45.027327 tx_last_pass[0][1][15] = 995
4240 23:45:45.030023 tx_win_center[1][0][0] = 992
4241 23:45:45.033772 tx_first_pass[1][0][0] = 979
4242 23:45:45.037305 tx_last_pass[1][0][0] = 1006
4243 23:45:45.040103 tx_win_center[1][0][1] = 991
4244 23:45:45.040205 tx_first_pass[1][0][1] = 978
4245 23:45:45.043547 tx_last_pass[1][0][1] = 1004
4246 23:45:45.047182 tx_win_center[1][0][2] = 989
4247 23:45:45.050457 tx_first_pass[1][0][2] = 977
4248 23:45:45.053797 tx_last_pass[1][0][2] = 1001
4249 23:45:45.053890 tx_win_center[1][0][3] = 987
4250 23:45:45.057005 tx_first_pass[1][0][3] = 976
4251 23:45:45.060155 tx_last_pass[1][0][3] = 999
4252 23:45:45.063357 tx_win_center[1][0][4] = 991
4253 23:45:45.063469 tx_first_pass[1][0][4] = 979
4254 23:45:45.067109 tx_last_pass[1][0][4] = 1004
4255 23:45:45.070077 tx_win_center[1][0][5] = 992
4256 23:45:45.073698 tx_first_pass[1][0][5] = 979
4257 23:45:45.076907 tx_last_pass[1][0][5] = 1006
4258 23:45:45.077003 tx_win_center[1][0][6] = 991
4259 23:45:45.080335 tx_first_pass[1][0][6] = 978
4260 23:45:45.083760 tx_last_pass[1][0][6] = 1005
4261 23:45:45.087078 tx_win_center[1][0][7] = 991
4262 23:45:45.090047 tx_first_pass[1][0][7] = 978
4263 23:45:45.090140 tx_last_pass[1][0][7] = 1004
4264 23:45:45.093392 tx_win_center[1][0][8] = 979
4265 23:45:45.097450 tx_first_pass[1][0][8] = 967
4266 23:45:45.100337 tx_last_pass[1][0][8] = 991
4267 23:45:45.100429 tx_win_center[1][0][9] = 979
4268 23:45:45.103601 tx_first_pass[1][0][9] = 968
4269 23:45:45.107162 tx_last_pass[1][0][9] = 990
4270 23:45:45.110266 tx_win_center[1][0][10] = 980
4271 23:45:45.113490 tx_first_pass[1][0][10] = 969
4272 23:45:45.113583 tx_last_pass[1][0][10] = 992
4273 23:45:45.116906 tx_win_center[1][0][11] = 981
4274 23:45:45.120220 tx_first_pass[1][0][11] = 969
4275 23:45:45.123370 tx_last_pass[1][0][11] = 993
4276 23:45:45.126619 tx_win_center[1][0][12] = 981
4277 23:45:45.126712 tx_first_pass[1][0][12] = 970
4278 23:45:45.130284 tx_last_pass[1][0][12] = 992
4279 23:45:45.133462 tx_win_center[1][0][13] = 981
4280 23:45:45.136684 tx_first_pass[1][0][13] = 970
4281 23:45:45.140095 tx_last_pass[1][0][13] = 993
4282 23:45:45.140198 tx_win_center[1][0][14] = 980
4283 23:45:45.143567 tx_first_pass[1][0][14] = 969
4284 23:45:45.146686 tx_last_pass[1][0][14] = 992
4285 23:45:45.150004 tx_win_center[1][0][15] = 974
4286 23:45:45.153290 tx_first_pass[1][0][15] = 962
4287 23:45:45.153381 tx_last_pass[1][0][15] = 986
4288 23:45:45.156651 tx_win_center[1][1][0] = 992
4289 23:45:45.160112 tx_first_pass[1][1][0] = 979
4290 23:45:45.163562 tx_last_pass[1][1][0] = 1006
4291 23:45:45.166925 tx_win_center[1][1][1] = 991
4292 23:45:45.167026 tx_first_pass[1][1][1] = 978
4293 23:45:45.170065 tx_last_pass[1][1][1] = 1004
4294 23:45:45.173192 tx_win_center[1][1][2] = 989
4295 23:45:45.176746 tx_first_pass[1][1][2] = 977
4296 23:45:45.176850 tx_last_pass[1][1][2] = 1002
4297 23:45:45.179876 tx_win_center[1][1][3] = 987
4298 23:45:45.183280 tx_first_pass[1][1][3] = 975
4299 23:45:45.186544 tx_last_pass[1][1][3] = 999
4300 23:45:45.189862 tx_win_center[1][1][4] = 991
4301 23:45:45.189953 tx_first_pass[1][1][4] = 978
4302 23:45:45.193247 tx_last_pass[1][1][4] = 1004
4303 23:45:45.196796 tx_win_center[1][1][5] = 992
4304 23:45:45.200103 tx_first_pass[1][1][5] = 979
4305 23:45:45.203286 tx_last_pass[1][1][5] = 1005
4306 23:45:45.203377 tx_win_center[1][1][6] = 991
4307 23:45:45.206663 tx_first_pass[1][1][6] = 978
4308 23:45:45.209964 tx_last_pass[1][1][6] = 1005
4309 23:45:45.213179 tx_win_center[1][1][7] = 990
4310 23:45:45.213269 tx_first_pass[1][1][7] = 978
4311 23:45:45.217070 tx_last_pass[1][1][7] = 1003
4312 23:45:45.219948 tx_win_center[1][1][8] = 980
4313 23:45:45.223207 tx_first_pass[1][1][8] = 968
4314 23:45:45.226540 tx_last_pass[1][1][8] = 992
4315 23:45:45.226630 tx_win_center[1][1][9] = 980
4316 23:45:45.229762 tx_first_pass[1][1][9] = 969
4317 23:45:45.233542 tx_last_pass[1][1][9] = 992
4318 23:45:45.236462 tx_win_center[1][1][10] = 981
4319 23:45:45.239841 tx_first_pass[1][1][10] = 970
4320 23:45:45.239948 tx_last_pass[1][1][10] = 993
4321 23:45:45.242963 tx_win_center[1][1][11] = 982
4322 23:45:45.246729 tx_first_pass[1][1][11] = 970
4323 23:45:45.249652 tx_last_pass[1][1][11] = 994
4324 23:45:45.253241 tx_win_center[1][1][12] = 982
4325 23:45:45.253333 tx_first_pass[1][1][12] = 971
4326 23:45:45.256381 tx_last_pass[1][1][12] = 994
4327 23:45:45.259563 tx_win_center[1][1][13] = 982
4328 23:45:45.263027 tx_first_pass[1][1][13] = 971
4329 23:45:45.266451 tx_last_pass[1][1][13] = 994
4330 23:45:45.266544 tx_win_center[1][1][14] = 981
4331 23:45:45.269826 tx_first_pass[1][1][14] = 970
4332 23:45:45.273443 tx_last_pass[1][1][14] = 993
4333 23:45:45.276327 tx_win_center[1][1][15] = 977
4334 23:45:45.279546 tx_first_pass[1][1][15] = 966
4335 23:45:45.279671 tx_last_pass[1][1][15] = 989
4336 23:45:45.282936 dump params rx window
4337 23:45:45.286267 rx_firspass[0][0][0] = 5
4338 23:45:45.286416 rx_lastpass[0][0][0] = 38
4339 23:45:45.289541 rx_firspass[0][0][1] = 5
4340 23:45:45.292870 rx_lastpass[0][0][1] = 36
4341 23:45:45.293015 rx_firspass[0][0][2] = 6
4342 23:45:45.296341 rx_lastpass[0][0][2] = 36
4343 23:45:45.299699 rx_firspass[0][0][3] = -2
4344 23:45:45.303032 rx_lastpass[0][0][3] = 31
4345 23:45:45.303261 rx_firspass[0][0][4] = 5
4346 23:45:45.306271 rx_lastpass[0][0][4] = 37
4347 23:45:45.309750 rx_firspass[0][0][5] = 2
4348 23:45:45.309935 rx_lastpass[0][0][5] = 32
4349 23:45:45.313102 rx_firspass[0][0][6] = 3
4350 23:45:45.315940 rx_lastpass[0][0][6] = 34
4351 23:45:45.320028 rx_firspass[0][0][7] = 5
4352 23:45:45.320194 rx_lastpass[0][0][7] = 36
4353 23:45:45.322816 rx_firspass[0][0][8] = -1
4354 23:45:45.326354 rx_lastpass[0][0][8] = 32
4355 23:45:45.326536 rx_firspass[0][0][9] = 1
4356 23:45:45.329583 rx_lastpass[0][0][9] = 32
4357 23:45:45.333238 rx_firspass[0][0][10] = 9
4358 23:45:45.336155 rx_lastpass[0][0][10] = 41
4359 23:45:45.336397 rx_firspass[0][0][11] = 1
4360 23:45:45.339710 rx_lastpass[0][0][11] = 32
4361 23:45:45.342900 rx_firspass[0][0][12] = 2
4362 23:45:45.343161 rx_lastpass[0][0][12] = 36
4363 23:45:45.346434 rx_firspass[0][0][13] = 4
4364 23:45:45.349673 rx_lastpass[0][0][13] = 33
4365 23:45:45.353121 rx_firspass[0][0][14] = 3
4366 23:45:45.353386 rx_lastpass[0][0][14] = 37
4367 23:45:45.356266 rx_firspass[0][0][15] = 8
4368 23:45:45.359601 rx_lastpass[0][0][15] = 37
4369 23:45:45.359866 rx_firspass[0][1][0] = 6
4370 23:45:45.362926 rx_lastpass[0][1][0] = 40
4371 23:45:45.366392 rx_firspass[0][1][1] = 5
4372 23:45:45.369745 rx_lastpass[0][1][1] = 38
4373 23:45:45.369930 rx_firspass[0][1][2] = 6
4374 23:45:45.373173 rx_lastpass[0][1][2] = 38
4375 23:45:45.375799 rx_firspass[0][1][3] = -2
4376 23:45:45.375982 rx_lastpass[0][1][3] = 34
4377 23:45:45.379254 rx_firspass[0][1][4] = 5
4378 23:45:45.382605 rx_lastpass[0][1][4] = 38
4379 23:45:45.382788 rx_firspass[0][1][5] = 2
4380 23:45:45.386186 rx_lastpass[0][1][5] = 34
4381 23:45:45.389157 rx_firspass[0][1][6] = 3
4382 23:45:45.392693 rx_lastpass[0][1][6] = 36
4383 23:45:45.392773 rx_firspass[0][1][7] = 3
4384 23:45:45.396341 rx_lastpass[0][1][7] = 38
4385 23:45:45.399401 rx_firspass[0][1][8] = -2
4386 23:45:45.399512 rx_lastpass[0][1][8] = 32
4387 23:45:45.402880 rx_firspass[0][1][9] = 1
4388 23:45:45.405778 rx_lastpass[0][1][9] = 36
4389 23:45:45.409454 rx_firspass[0][1][10] = 7
4390 23:45:45.409566 rx_lastpass[0][1][10] = 43
4391 23:45:45.412861 rx_firspass[0][1][11] = -2
4392 23:45:45.416195 rx_lastpass[0][1][11] = 34
4393 23:45:45.416333 rx_firspass[0][1][12] = 1
4394 23:45:45.419021 rx_lastpass[0][1][12] = 37
4395 23:45:45.422933 rx_firspass[0][1][13] = 2
4396 23:45:45.425727 rx_lastpass[0][1][13] = 34
4397 23:45:45.425892 rx_firspass[0][1][14] = 2
4398 23:45:45.429224 rx_lastpass[0][1][14] = 38
4399 23:45:45.432528 rx_firspass[0][1][15] = 6
4400 23:45:45.435725 rx_lastpass[0][1][15] = 39
4401 23:45:45.435974 rx_firspass[1][0][0] = 5
4402 23:45:45.439656 rx_lastpass[1][0][0] = 39
4403 23:45:45.442749 rx_firspass[1][0][1] = 5
4404 23:45:45.443074 rx_lastpass[1][0][1] = 38
4405 23:45:45.446425 rx_firspass[1][0][2] = 2
4406 23:45:45.449219 rx_lastpass[1][0][2] = 35
4407 23:45:45.449627 rx_firspass[1][0][3] = 0
4408 23:45:45.452773 rx_lastpass[1][0][3] = 33
4409 23:45:45.456377 rx_firspass[1][0][4] = 5
4410 23:45:45.459395 rx_lastpass[1][0][4] = 38
4411 23:45:45.459848 rx_firspass[1][0][5] = 8
4412 23:45:45.462783 rx_lastpass[1][0][5] = 39
4413 23:45:45.466412 rx_firspass[1][0][6] = 7
4414 23:45:45.466856 rx_lastpass[1][0][6] = 40
4415 23:45:45.469572 rx_firspass[1][0][7] = 5
4416 23:45:45.472714 rx_lastpass[1][0][7] = 38
4417 23:45:45.473156 rx_firspass[1][0][8] = 1
4418 23:45:45.476169 rx_lastpass[1][0][8] = 33
4419 23:45:45.479584 rx_firspass[1][0][9] = 1
4420 23:45:45.483056 rx_lastpass[1][0][9] = 32
4421 23:45:45.483678 rx_firspass[1][0][10] = 5
4422 23:45:45.486423 rx_lastpass[1][0][10] = 35
4423 23:45:45.489567 rx_firspass[1][0][11] = 6
4424 23:45:45.490071 rx_lastpass[1][0][11] = 38
4425 23:45:45.492804 rx_firspass[1][0][12] = 6
4426 23:45:45.496264 rx_lastpass[1][0][12] = 38
4427 23:45:45.499664 rx_firspass[1][0][13] = 6
4428 23:45:45.500121 rx_lastpass[1][0][13] = 37
4429 23:45:45.502785 rx_firspass[1][0][14] = 7
4430 23:45:45.506128 rx_lastpass[1][0][14] = 38
4431 23:45:45.506531 rx_firspass[1][0][15] = -3
4432 23:45:45.509422 rx_lastpass[1][0][15] = 30
4433 23:45:45.512782 rx_firspass[1][1][0] = 3
4434 23:45:45.516306 rx_lastpass[1][1][0] = 40
4435 23:45:45.516938 rx_firspass[1][1][1] = 5
4436 23:45:45.519703 rx_lastpass[1][1][1] = 39
4437 23:45:45.522871 rx_firspass[1][1][2] = 1
4438 23:45:45.523304 rx_lastpass[1][1][2] = 36
4439 23:45:45.526216 rx_firspass[1][1][3] = -2
4440 23:45:45.529774 rx_lastpass[1][1][3] = 34
4441 23:45:45.532945 rx_firspass[1][1][4] = 4
4442 23:45:45.533364 rx_lastpass[1][1][4] = 39
4443 23:45:45.536299 rx_firspass[1][1][5] = 5
4444 23:45:45.539201 rx_lastpass[1][1][5] = 40
4445 23:45:45.539673 rx_firspass[1][1][6] = 6
4446 23:45:45.542940 rx_lastpass[1][1][6] = 41
4447 23:45:45.545801 rx_firspass[1][1][7] = 3
4448 23:45:45.546240 rx_lastpass[1][1][7] = 38
4449 23:45:45.549229 rx_firspass[1][1][8] = 0
4450 23:45:45.552485 rx_lastpass[1][1][8] = 35
4451 23:45:45.556284 rx_firspass[1][1][9] = -1
4452 23:45:45.556782 rx_lastpass[1][1][9] = 34
4453 23:45:45.559132 rx_firspass[1][1][10] = 3
4454 23:45:45.562426 rx_lastpass[1][1][10] = 38
4455 23:45:45.562867 rx_firspass[1][1][11] = 4
4456 23:45:45.566128 rx_lastpass[1][1][11] = 40
4457 23:45:45.569568 rx_firspass[1][1][12] = 4
4458 23:45:45.572769 rx_lastpass[1][1][12] = 40
4459 23:45:45.573185 rx_firspass[1][1][13] = 4
4460 23:45:45.576036 rx_lastpass[1][1][13] = 40
4461 23:45:45.579280 rx_firspass[1][1][14] = 5
4462 23:45:45.582757 rx_lastpass[1][1][14] = 40
4463 23:45:45.583275 rx_firspass[1][1][15] = -3
4464 23:45:45.585963 rx_lastpass[1][1][15] = 31
4465 23:45:45.589412 dump params clk_delay
4466 23:45:45.589858 clk_delay[0] = 1
4467 23:45:45.592400 clk_delay[1] = 0
4468 23:45:45.592844 dump params dqs_delay
4469 23:45:45.595673 dqs_delay[0][0] = -2
4470 23:45:45.596138 dqs_delay[0][1] = 0
4471 23:45:45.599011 dqs_delay[1][0] = 0
4472 23:45:45.599545 dqs_delay[1][1] = 0
4473 23:45:45.602639 dump params delay_cell_unit = 735
4474 23:45:45.605697 dump source = 0x0
4475 23:45:45.609109 dump params frequency:1200
4476 23:45:45.609521 dump params rank number:2
4477 23:45:45.609927
4478 23:45:45.612449 dump params write leveling
4479 23:45:45.615860 write leveling[0][0][0] = 0x0
4480 23:45:45.619143 write leveling[0][0][1] = 0x0
4481 23:45:45.619715 write leveling[0][1][0] = 0x0
4482 23:45:45.622406 write leveling[0][1][1] = 0x0
4483 23:45:45.626022 write leveling[1][0][0] = 0x0
4484 23:45:45.628924 write leveling[1][0][1] = 0x0
4485 23:45:45.632307 write leveling[1][1][0] = 0x0
4486 23:45:45.635627 write leveling[1][1][1] = 0x0
4487 23:45:45.636102 dump params cbt_cs
4488 23:45:45.638450 cbt_cs[0][0] = 0x0
4489 23:45:45.638972 cbt_cs[0][1] = 0x0
4490 23:45:45.641965 cbt_cs[1][0] = 0x0
4491 23:45:45.642406 cbt_cs[1][1] = 0x0
4492 23:45:45.645301 dump params cbt_mr12
4493 23:45:45.645738 cbt_mr12[0][0] = 0x0
4494 23:45:45.648685 cbt_mr12[0][1] = 0x0
4495 23:45:45.649174 cbt_mr12[1][0] = 0x0
4496 23:45:45.652189 cbt_mr12[1][1] = 0x0
4497 23:45:45.655495 dump params tx window
4498 23:45:45.655899 tx_center_min[0][0][0] = 0
4499 23:45:45.658719 tx_center_max[0][0][0] = 0
4500 23:45:45.661828 tx_center_min[0][0][1] = 0
4501 23:45:45.665194 tx_center_max[0][0][1] = 0
4502 23:45:45.665673 tx_center_min[0][1][0] = 0
4503 23:45:45.668310 tx_center_max[0][1][0] = 0
4504 23:45:45.671727 tx_center_min[0][1][1] = 0
4505 23:45:45.675216 tx_center_max[0][1][1] = 0
4506 23:45:45.675724 tx_center_min[1][0][0] = 0
4507 23:45:45.678099 tx_center_max[1][0][0] = 0
4508 23:45:45.681805 tx_center_min[1][0][1] = 0
4509 23:45:45.682256 tx_center_max[1][0][1] = 0
4510 23:45:45.685147 tx_center_min[1][1][0] = 0
4511 23:45:45.688280 tx_center_max[1][1][0] = 0
4512 23:45:45.691750 tx_center_min[1][1][1] = 0
4513 23:45:45.692231 tx_center_max[1][1][1] = 0
4514 23:45:45.695200 dump params tx window
4515 23:45:45.698027 tx_win_center[0][0][0] = 0
4516 23:45:45.701551 tx_first_pass[0][0][0] = 0
4517 23:45:45.702027 tx_last_pass[0][0][0] = 0
4518 23:45:45.705007 tx_win_center[0][0][1] = 0
4519 23:45:45.708564 tx_first_pass[0][0][1] = 0
4520 23:45:45.709136 tx_last_pass[0][0][1] = 0
4521 23:45:45.711476 tx_win_center[0][0][2] = 0
4522 23:45:45.714679 tx_first_pass[0][0][2] = 0
4523 23:45:45.717763 tx_last_pass[0][0][2] = 0
4524 23:45:45.718251 tx_win_center[0][0][3] = 0
4525 23:45:45.721346 tx_first_pass[0][0][3] = 0
4526 23:45:45.724420 tx_last_pass[0][0][3] = 0
4527 23:45:45.727627 tx_win_center[0][0][4] = 0
4528 23:45:45.728109 tx_first_pass[0][0][4] = 0
4529 23:45:45.730912 tx_last_pass[0][0][4] = 0
4530 23:45:45.734585 tx_win_center[0][0][5] = 0
4531 23:45:45.737902 tx_first_pass[0][0][5] = 0
4532 23:45:45.738378 tx_last_pass[0][0][5] = 0
4533 23:45:45.741143 tx_win_center[0][0][6] = 0
4534 23:45:45.744015 tx_first_pass[0][0][6] = 0
4535 23:45:45.744493 tx_last_pass[0][0][6] = 0
4536 23:45:45.747495 tx_win_center[0][0][7] = 0
4537 23:45:45.750885 tx_first_pass[0][0][7] = 0
4538 23:45:45.754184 tx_last_pass[0][0][7] = 0
4539 23:45:45.754640 tx_win_center[0][0][8] = 0
4540 23:45:45.757592 tx_first_pass[0][0][8] = 0
4541 23:45:45.761158 tx_last_pass[0][0][8] = 0
4542 23:45:45.764025 tx_win_center[0][0][9] = 0
4543 23:45:45.764493 tx_first_pass[0][0][9] = 0
4544 23:45:45.767240 tx_last_pass[0][0][9] = 0
4545 23:45:45.771039 tx_win_center[0][0][10] = 0
4546 23:45:45.773845 tx_first_pass[0][0][10] = 0
4547 23:45:45.774300 tx_last_pass[0][0][10] = 0
4548 23:45:45.777217 tx_win_center[0][0][11] = 0
4549 23:45:45.780746 tx_first_pass[0][0][11] = 0
4550 23:45:45.784134 tx_last_pass[0][0][11] = 0
4551 23:45:45.784609 tx_win_center[0][0][12] = 0
4552 23:45:45.787642 tx_first_pass[0][0][12] = 0
4553 23:45:45.790572 tx_last_pass[0][0][12] = 0
4554 23:45:45.794021 tx_win_center[0][0][13] = 0
4555 23:45:45.794442 tx_first_pass[0][0][13] = 0
4556 23:45:45.797076 tx_last_pass[0][0][13] = 0
4557 23:45:45.800515 tx_win_center[0][0][14] = 0
4558 23:45:45.804008 tx_first_pass[0][0][14] = 0
4559 23:45:45.804475 tx_last_pass[0][0][14] = 0
4560 23:45:45.807012 tx_win_center[0][0][15] = 0
4561 23:45:45.811000 tx_first_pass[0][0][15] = 0
4562 23:45:45.814230 tx_last_pass[0][0][15] = 0
4563 23:45:45.814695 tx_win_center[0][1][0] = 0
4564 23:45:45.817223 tx_first_pass[0][1][0] = 0
4565 23:45:45.820513 tx_last_pass[0][1][0] = 0
4566 23:45:45.820929 tx_win_center[0][1][1] = 0
4567 23:45:45.823946 tx_first_pass[0][1][1] = 0
4568 23:45:45.827868 tx_last_pass[0][1][1] = 0
4569 23:45:45.830876 tx_win_center[0][1][2] = 0
4570 23:45:45.831338 tx_first_pass[0][1][2] = 0
4571 23:45:45.834022 tx_last_pass[0][1][2] = 0
4572 23:45:45.837176 tx_win_center[0][1][3] = 0
4573 23:45:45.840577 tx_first_pass[0][1][3] = 0
4574 23:45:45.841029 tx_last_pass[0][1][3] = 0
4575 23:45:45.843701 tx_win_center[0][1][4] = 0
4576 23:45:45.847244 tx_first_pass[0][1][4] = 0
4577 23:45:45.847716 tx_last_pass[0][1][4] = 0
4578 23:45:45.850490 tx_win_center[0][1][5] = 0
4579 23:45:45.853854 tx_first_pass[0][1][5] = 0
4580 23:45:45.857316 tx_last_pass[0][1][5] = 0
4581 23:45:45.857729 tx_win_center[0][1][6] = 0
4582 23:45:45.860608 tx_first_pass[0][1][6] = 0
4583 23:45:45.864010 tx_last_pass[0][1][6] = 0
4584 23:45:45.866885 tx_win_center[0][1][7] = 0
4585 23:45:45.867292 tx_first_pass[0][1][7] = 0
4586 23:45:45.870354 tx_last_pass[0][1][7] = 0
4587 23:45:45.873517 tx_win_center[0][1][8] = 0
4588 23:45:45.873921 tx_first_pass[0][1][8] = 0
4589 23:45:45.877059 tx_last_pass[0][1][8] = 0
4590 23:45:45.880395 tx_win_center[0][1][9] = 0
4591 23:45:45.883762 tx_first_pass[0][1][9] = 0
4592 23:45:45.884167 tx_last_pass[0][1][9] = 0
4593 23:45:45.887296 tx_win_center[0][1][10] = 0
4594 23:45:45.890683 tx_first_pass[0][1][10] = 0
4595 23:45:45.893748 tx_last_pass[0][1][10] = 0
4596 23:45:45.894156 tx_win_center[0][1][11] = 0
4597 23:45:45.896894 tx_first_pass[0][1][11] = 0
4598 23:45:45.900260 tx_last_pass[0][1][11] = 0
4599 23:45:45.903837 tx_win_center[0][1][12] = 0
4600 23:45:45.904245 tx_first_pass[0][1][12] = 0
4601 23:45:45.906933 tx_last_pass[0][1][12] = 0
4602 23:45:45.910234 tx_win_center[0][1][13] = 0
4603 23:45:45.913729 tx_first_pass[0][1][13] = 0
4604 23:45:45.914139 tx_last_pass[0][1][13] = 0
4605 23:45:45.917341 tx_win_center[0][1][14] = 0
4606 23:45:45.920139 tx_first_pass[0][1][14] = 0
4607 23:45:45.924163 tx_last_pass[0][1][14] = 0
4608 23:45:45.924659 tx_win_center[0][1][15] = 0
4609 23:45:45.926884 tx_first_pass[0][1][15] = 0
4610 23:45:45.930284 tx_last_pass[0][1][15] = 0
4611 23:45:45.933686 tx_win_center[1][0][0] = 0
4612 23:45:45.934111 tx_first_pass[1][0][0] = 0
4613 23:45:45.937354 tx_last_pass[1][0][0] = 0
4614 23:45:45.940759 tx_win_center[1][0][1] = 0
4615 23:45:45.941241 tx_first_pass[1][0][1] = 0
4616 23:45:45.944178 tx_last_pass[1][0][1] = 0
4617 23:45:45.947327 tx_win_center[1][0][2] = 0
4618 23:45:45.950402 tx_first_pass[1][0][2] = 0
4619 23:45:45.950857 tx_last_pass[1][0][2] = 0
4620 23:45:45.953672 tx_win_center[1][0][3] = 0
4621 23:45:45.957017 tx_first_pass[1][0][3] = 0
4622 23:45:45.960188 tx_last_pass[1][0][3] = 0
4623 23:45:45.960603 tx_win_center[1][0][4] = 0
4624 23:45:45.963484 tx_first_pass[1][0][4] = 0
4625 23:45:45.967282 tx_last_pass[1][0][4] = 0
4626 23:45:45.967808 tx_win_center[1][0][5] = 0
4627 23:45:45.969971 tx_first_pass[1][0][5] = 0
4628 23:45:45.973772 tx_last_pass[1][0][5] = 0
4629 23:45:45.977247 tx_win_center[1][0][6] = 0
4630 23:45:45.977563 tx_first_pass[1][0][6] = 0
4631 23:45:45.980350 tx_last_pass[1][0][6] = 0
4632 23:45:45.983063 tx_win_center[1][0][7] = 0
4633 23:45:45.986600 tx_first_pass[1][0][7] = 0
4634 23:45:45.986780 tx_last_pass[1][0][7] = 0
4635 23:45:45.989991 tx_win_center[1][0][8] = 0
4636 23:45:45.993370 tx_first_pass[1][0][8] = 0
4637 23:45:45.993551 tx_last_pass[1][0][8] = 0
4638 23:45:45.996778 tx_win_center[1][0][9] = 0
4639 23:45:46.000089 tx_first_pass[1][0][9] = 0
4640 23:45:46.003331 tx_last_pass[1][0][9] = 0
4641 23:45:46.003524 tx_win_center[1][0][10] = 0
4642 23:45:46.006603 tx_first_pass[1][0][10] = 0
4643 23:45:46.009997 tx_last_pass[1][0][10] = 0
4644 23:45:46.013152 tx_win_center[1][0][11] = 0
4645 23:45:46.013360 tx_first_pass[1][0][11] = 0
4646 23:45:46.016541 tx_last_pass[1][0][11] = 0
4647 23:45:46.020163 tx_win_center[1][0][12] = 0
4648 23:45:46.022921 tx_first_pass[1][0][12] = 0
4649 23:45:46.023239 tx_last_pass[1][0][12] = 0
4650 23:45:46.026802 tx_win_center[1][0][13] = 0
4651 23:45:46.029789 tx_first_pass[1][0][13] = 0
4652 23:45:46.033090 tx_last_pass[1][0][13] = 0
4653 23:45:46.033506 tx_win_center[1][0][14] = 0
4654 23:45:46.036590 tx_first_pass[1][0][14] = 0
4655 23:45:46.039924 tx_last_pass[1][0][14] = 0
4656 23:45:46.043169 tx_win_center[1][0][15] = 0
4657 23:45:46.043624 tx_first_pass[1][0][15] = 0
4658 23:45:46.046923 tx_last_pass[1][0][15] = 0
4659 23:45:46.050189 tx_win_center[1][1][0] = 0
4660 23:45:46.053091 tx_first_pass[1][1][0] = 0
4661 23:45:46.053505 tx_last_pass[1][1][0] = 0
4662 23:45:46.056554 tx_win_center[1][1][1] = 0
4663 23:45:46.059850 tx_first_pass[1][1][1] = 0
4664 23:45:46.063444 tx_last_pass[1][1][1] = 0
4665 23:45:46.063856 tx_win_center[1][1][2] = 0
4666 23:45:46.066595 tx_first_pass[1][1][2] = 0
4667 23:45:46.069774 tx_last_pass[1][1][2] = 0
4668 23:45:46.070182 tx_win_center[1][1][3] = 0
4669 23:45:46.073401 tx_first_pass[1][1][3] = 0
4670 23:45:46.076293 tx_last_pass[1][1][3] = 0
4671 23:45:46.079785 tx_win_center[1][1][4] = 0
4672 23:45:46.080197 tx_first_pass[1][1][4] = 0
4673 23:45:46.083126 tx_last_pass[1][1][4] = 0
4674 23:45:46.086397 tx_win_center[1][1][5] = 0
4675 23:45:46.090190 tx_first_pass[1][1][5] = 0
4676 23:45:46.090602 tx_last_pass[1][1][5] = 0
4677 23:45:46.093151 tx_win_center[1][1][6] = 0
4678 23:45:46.096587 tx_first_pass[1][1][6] = 0
4679 23:45:46.097001 tx_last_pass[1][1][6] = 0
4680 23:45:46.100015 tx_win_center[1][1][7] = 0
4681 23:45:46.103696 tx_first_pass[1][1][7] = 0
4682 23:45:46.106638 tx_last_pass[1][1][7] = 0
4683 23:45:46.107049 tx_win_center[1][1][8] = 0
4684 23:45:46.110370 tx_first_pass[1][1][8] = 0
4685 23:45:46.113552 tx_last_pass[1][1][8] = 0
4686 23:45:46.113983 tx_win_center[1][1][9] = 0
4687 23:45:46.116454 tx_first_pass[1][1][9] = 0
4688 23:45:46.119708 tx_last_pass[1][1][9] = 0
4689 23:45:46.122872 tx_win_center[1][1][10] = 0
4690 23:45:46.123257 tx_first_pass[1][1][10] = 0
4691 23:45:46.126492 tx_last_pass[1][1][10] = 0
4692 23:45:46.129641 tx_win_center[1][1][11] = 0
4693 23:45:46.133015 tx_first_pass[1][1][11] = 0
4694 23:45:46.133512 tx_last_pass[1][1][11] = 0
4695 23:45:46.136263 tx_win_center[1][1][12] = 0
4696 23:45:46.140024 tx_first_pass[1][1][12] = 0
4697 23:45:46.142776 tx_last_pass[1][1][12] = 0
4698 23:45:46.143216 tx_win_center[1][1][13] = 0
4699 23:45:46.146090 tx_first_pass[1][1][13] = 0
4700 23:45:46.149617 tx_last_pass[1][1][13] = 0
4701 23:45:46.153154 tx_win_center[1][1][14] = 0
4702 23:45:46.153580 tx_first_pass[1][1][14] = 0
4703 23:45:46.156109 tx_last_pass[1][1][14] = 0
4704 23:45:46.159470 tx_win_center[1][1][15] = 0
4705 23:45:46.163072 tx_first_pass[1][1][15] = 0
4706 23:45:46.166406 tx_last_pass[1][1][15] = 0
4707 23:45:46.166841 dump params rx window
4708 23:45:46.169431 rx_firspass[0][0][0] = 0
4709 23:45:46.169873 rx_lastpass[0][0][0] = 0
4710 23:45:46.172697 rx_firspass[0][0][1] = 0
4711 23:45:46.175952 rx_lastpass[0][0][1] = 0
4712 23:45:46.179261 rx_firspass[0][0][2] = 0
4713 23:45:46.179716 rx_lastpass[0][0][2] = 0
4714 23:45:46.182866 rx_firspass[0][0][3] = 0
4715 23:45:46.185858 rx_lastpass[0][0][3] = 0
4716 23:45:46.186300 rx_firspass[0][0][4] = 0
4717 23:45:46.189318 rx_lastpass[0][0][4] = 0
4718 23:45:46.192767 rx_firspass[0][0][5] = 0
4719 23:45:46.193263 rx_lastpass[0][0][5] = 0
4720 23:45:46.195884 rx_firspass[0][0][6] = 0
4721 23:45:46.199316 rx_lastpass[0][0][6] = 0
4722 23:45:46.199822 rx_firspass[0][0][7] = 0
4723 23:45:46.202743 rx_lastpass[0][0][7] = 0
4724 23:45:46.206143 rx_firspass[0][0][8] = 0
4725 23:45:46.206634 rx_lastpass[0][0][8] = 0
4726 23:45:46.208989 rx_firspass[0][0][9] = 0
4727 23:45:46.212809 rx_lastpass[0][0][9] = 0
4728 23:45:46.216128 rx_firspass[0][0][10] = 0
4729 23:45:46.216538 rx_lastpass[0][0][10] = 0
4730 23:45:46.218947 rx_firspass[0][0][11] = 0
4731 23:45:46.222392 rx_lastpass[0][0][11] = 0
4732 23:45:46.222801 rx_firspass[0][0][12] = 0
4733 23:45:46.225719 rx_lastpass[0][0][12] = 0
4734 23:45:46.229217 rx_firspass[0][0][13] = 0
4735 23:45:46.232536 rx_lastpass[0][0][13] = 0
4736 23:45:46.232948 rx_firspass[0][0][14] = 0
4737 23:45:46.235516 rx_lastpass[0][0][14] = 0
4738 23:45:46.239076 rx_firspass[0][0][15] = 0
4739 23:45:46.239519 rx_lastpass[0][0][15] = 0
4740 23:45:46.242441 rx_firspass[0][1][0] = 0
4741 23:45:46.246031 rx_lastpass[0][1][0] = 0
4742 23:45:46.249169 rx_firspass[0][1][1] = 0
4743 23:45:46.249596 rx_lastpass[0][1][1] = 0
4744 23:45:46.252197 rx_firspass[0][1][2] = 0
4745 23:45:46.255892 rx_lastpass[0][1][2] = 0
4746 23:45:46.256301 rx_firspass[0][1][3] = 0
4747 23:45:46.259566 rx_lastpass[0][1][3] = 0
4748 23:45:46.262262 rx_firspass[0][1][4] = 0
4749 23:45:46.262672 rx_lastpass[0][1][4] = 0
4750 23:45:46.265603 rx_firspass[0][1][5] = 0
4751 23:45:46.269026 rx_lastpass[0][1][5] = 0
4752 23:45:46.269437 rx_firspass[0][1][6] = 0
4753 23:45:46.272176 rx_lastpass[0][1][6] = 0
4754 23:45:46.275382 rx_firspass[0][1][7] = 0
4755 23:45:46.275821 rx_lastpass[0][1][7] = 0
4756 23:45:46.278756 rx_firspass[0][1][8] = 0
4757 23:45:46.282303 rx_lastpass[0][1][8] = 0
4758 23:45:46.285800 rx_firspass[0][1][9] = 0
4759 23:45:46.286209 rx_lastpass[0][1][9] = 0
4760 23:45:46.289064 rx_firspass[0][1][10] = 0
4761 23:45:46.292087 rx_lastpass[0][1][10] = 0
4762 23:45:46.292497 rx_firspass[0][1][11] = 0
4763 23:45:46.295335 rx_lastpass[0][1][11] = 0
4764 23:45:46.299087 rx_firspass[0][1][12] = 0
4765 23:45:46.302115 rx_lastpass[0][1][12] = 0
4766 23:45:46.302527 rx_firspass[0][1][13] = 0
4767 23:45:46.305440 rx_lastpass[0][1][13] = 0
4768 23:45:46.308604 rx_firspass[0][1][14] = 0
4769 23:45:46.309016 rx_lastpass[0][1][14] = 0
4770 23:45:46.311931 rx_firspass[0][1][15] = 0
4771 23:45:46.315198 rx_lastpass[0][1][15] = 0
4772 23:45:46.315666 rx_firspass[1][0][0] = 0
4773 23:45:46.319267 rx_lastpass[1][0][0] = 0
4774 23:45:46.321866 rx_firspass[1][0][1] = 0
4775 23:45:46.325445 rx_lastpass[1][0][1] = 0
4776 23:45:46.325861 rx_firspass[1][0][2] = 0
4777 23:45:46.328766 rx_lastpass[1][0][2] = 0
4778 23:45:46.332035 rx_firspass[1][0][3] = 0
4779 23:45:46.332125 rx_lastpass[1][0][3] = 0
4780 23:45:46.335076 rx_firspass[1][0][4] = 0
4781 23:45:46.338478 rx_lastpass[1][0][4] = 0
4782 23:45:46.338568 rx_firspass[1][0][5] = 0
4783 23:45:46.341909 rx_lastpass[1][0][5] = 0
4784 23:45:46.345141 rx_firspass[1][0][6] = 0
4785 23:45:46.345234 rx_lastpass[1][0][6] = 0
4786 23:45:46.348405 rx_firspass[1][0][7] = 0
4787 23:45:46.351344 rx_lastpass[1][0][7] = 0
4788 23:45:46.351483 rx_firspass[1][0][8] = 0
4789 23:45:46.354808 rx_lastpass[1][0][8] = 0
4790 23:45:46.358416 rx_firspass[1][0][9] = 0
4791 23:45:46.361715 rx_lastpass[1][0][9] = 0
4792 23:45:46.361829 rx_firspass[1][0][10] = 0
4793 23:45:46.364968 rx_lastpass[1][0][10] = 0
4794 23:45:46.368038 rx_firspass[1][0][11] = 0
4795 23:45:46.368166 rx_lastpass[1][0][11] = 0
4796 23:45:46.371728 rx_firspass[1][0][12] = 0
4797 23:45:46.374989 rx_lastpass[1][0][12] = 0
4798 23:45:46.375130 rx_firspass[1][0][13] = 0
4799 23:45:46.378178 rx_lastpass[1][0][13] = 0
4800 23:45:46.381550 rx_firspass[1][0][14] = 0
4801 23:45:46.385098 rx_lastpass[1][0][14] = 0
4802 23:45:46.385284 rx_firspass[1][0][15] = 0
4803 23:45:46.388468 rx_lastpass[1][0][15] = 0
4804 23:45:46.391913 rx_firspass[1][1][0] = 0
4805 23:45:46.392132 rx_lastpass[1][1][0] = 0
4806 23:45:46.394838 rx_firspass[1][1][1] = 0
4807 23:45:46.398326 rx_lastpass[1][1][1] = 0
4808 23:45:46.398673 rx_firspass[1][1][2] = 0
4809 23:45:46.401635 rx_lastpass[1][1][2] = 0
4810 23:45:46.405327 rx_firspass[1][1][3] = 0
4811 23:45:46.408625 rx_lastpass[1][1][3] = 0
4812 23:45:46.409033 rx_firspass[1][1][4] = 0
4813 23:45:46.411996 rx_lastpass[1][1][4] = 0
4814 23:45:46.414880 rx_firspass[1][1][5] = 0
4815 23:45:46.415287 rx_lastpass[1][1][5] = 0
4816 23:45:46.418251 rx_firspass[1][1][6] = 0
4817 23:45:46.421703 rx_lastpass[1][1][6] = 0
4818 23:45:46.422116 rx_firspass[1][1][7] = 0
4819 23:45:46.424885 rx_lastpass[1][1][7] = 0
4820 23:45:46.428691 rx_firspass[1][1][8] = 0
4821 23:45:46.429099 rx_lastpass[1][1][8] = 0
4822 23:45:46.431667 rx_firspass[1][1][9] = 0
4823 23:45:46.434821 rx_lastpass[1][1][9] = 0
4824 23:45:46.437817 rx_firspass[1][1][10] = 0
4825 23:45:46.437906 rx_lastpass[1][1][10] = 0
4826 23:45:46.441293 rx_firspass[1][1][11] = 0
4827 23:45:46.444847 rx_lastpass[1][1][11] = 0
4828 23:45:46.444953 rx_firspass[1][1][12] = 0
4829 23:45:46.448228 rx_lastpass[1][1][12] = 0
4830 23:45:46.451038 rx_firspass[1][1][13] = 0
4831 23:45:46.454466 rx_lastpass[1][1][13] = 0
4832 23:45:46.454556 rx_firspass[1][1][14] = 0
4833 23:45:46.457728 rx_lastpass[1][1][14] = 0
4834 23:45:46.461605 rx_firspass[1][1][15] = 0
4835 23:45:46.461694 rx_lastpass[1][1][15] = 0
4836 23:45:46.464844 dump params clk_delay
4837 23:45:46.464934 clk_delay[0] = 0
4838 23:45:46.467920 clk_delay[1] = 0
4839 23:45:46.468009 dump params dqs_delay
4840 23:45:46.471080 dqs_delay[0][0] = 0
4841 23:45:46.474523 dqs_delay[0][1] = 0
4842 23:45:46.474619 dqs_delay[1][0] = 0
4843 23:45:46.477918 dqs_delay[1][1] = 0
4844 23:45:46.481653 dump params delay_cell_unit = 735
4845 23:45:46.481759 dump source = 0x0
4846 23:45:46.485067 dump params frequency:800
4847 23:45:46.485182 dump params rank number:2
4848 23:45:46.487709
4849 23:45:46.487824 dump params write leveling
4850 23:45:46.491831 write leveling[0][0][0] = 0x0
4851 23:45:46.494521 write leveling[0][0][1] = 0x0
4852 23:45:46.497904 write leveling[0][1][0] = 0x0
4853 23:45:46.498046 write leveling[0][1][1] = 0x0
4854 23:45:46.501284 write leveling[1][0][0] = 0x0
4855 23:45:46.504781 write leveling[1][0][1] = 0x0
4856 23:45:46.508115 write leveling[1][1][0] = 0x0
4857 23:45:46.511290 write leveling[1][1][1] = 0x0
4858 23:45:46.511549 dump params cbt_cs
4859 23:45:46.514687 cbt_cs[0][0] = 0x0
4860 23:45:46.514955 cbt_cs[0][1] = 0x0
4861 23:45:46.518062 cbt_cs[1][0] = 0x0
4862 23:45:46.518330 cbt_cs[1][1] = 0x0
4863 23:45:46.521546 dump params cbt_mr12
4864 23:45:46.521895 cbt_mr12[0][0] = 0x0
4865 23:45:46.525076 cbt_mr12[0][1] = 0x0
4866 23:45:46.528965 cbt_mr12[1][0] = 0x0
4867 23:45:46.529399 cbt_mr12[1][1] = 0x0
4868 23:45:46.531764 dump params tx window
4869 23:45:46.532174 tx_center_min[0][0][0] = 0
4870 23:45:46.534803 tx_center_max[0][0][0] = 0
4871 23:45:46.538104 tx_center_min[0][0][1] = 0
4872 23:45:46.541309 tx_center_max[0][0][1] = 0
4873 23:45:46.541719 tx_center_min[0][1][0] = 0
4874 23:45:46.545086 tx_center_max[0][1][0] = 0
4875 23:45:46.547937 tx_center_min[0][1][1] = 0
4876 23:45:46.551369 tx_center_max[0][1][1] = 0
4877 23:45:46.551818 tx_center_min[1][0][0] = 0
4878 23:45:46.554832 tx_center_max[1][0][0] = 0
4879 23:45:46.558342 tx_center_min[1][0][1] = 0
4880 23:45:46.561732 tx_center_max[1][0][1] = 0
4881 23:45:46.562147 tx_center_min[1][1][0] = 0
4882 23:45:46.565104 tx_center_max[1][1][0] = 0
4883 23:45:46.568476 tx_center_min[1][1][1] = 0
4884 23:45:46.568941 tx_center_max[1][1][1] = 0
4885 23:45:46.571517 dump params tx window
4886 23:45:46.574970 tx_win_center[0][0][0] = 0
4887 23:45:46.578533 tx_first_pass[0][0][0] = 0
4888 23:45:46.578622 tx_last_pass[0][0][0] = 0
4889 23:45:46.581450 tx_win_center[0][0][1] = 0
4890 23:45:46.584480 tx_first_pass[0][0][1] = 0
4891 23:45:46.584569 tx_last_pass[0][0][1] = 0
4892 23:45:46.587676 tx_win_center[0][0][2] = 0
4893 23:45:46.590682 tx_first_pass[0][0][2] = 0
4894 23:45:46.594040 tx_last_pass[0][0][2] = 0
4895 23:45:46.594129 tx_win_center[0][0][3] = 0
4896 23:45:46.597744 tx_first_pass[0][0][3] = 0
4897 23:45:46.601188 tx_last_pass[0][0][3] = 0
4898 23:45:46.604082 tx_win_center[0][0][4] = 0
4899 23:45:46.604202 tx_first_pass[0][0][4] = 0
4900 23:45:46.607417 tx_last_pass[0][0][4] = 0
4901 23:45:46.610873 tx_win_center[0][0][5] = 0
4902 23:45:46.610966 tx_first_pass[0][0][5] = 0
4903 23:45:46.614422 tx_last_pass[0][0][5] = 0
4904 23:45:46.617872 tx_win_center[0][0][6] = 0
4905 23:45:46.621070 tx_first_pass[0][0][6] = 0
4906 23:45:46.621160 tx_last_pass[0][0][6] = 0
4907 23:45:46.624322 tx_win_center[0][0][7] = 0
4908 23:45:46.627894 tx_first_pass[0][0][7] = 0
4909 23:45:46.631266 tx_last_pass[0][0][7] = 0
4910 23:45:46.631371 tx_win_center[0][0][8] = 0
4911 23:45:46.634487 tx_first_pass[0][0][8] = 0
4912 23:45:46.637743 tx_last_pass[0][0][8] = 0
4913 23:45:46.637895 tx_win_center[0][0][9] = 0
4914 23:45:46.640951 tx_first_pass[0][0][9] = 0
4915 23:45:46.644250 tx_last_pass[0][0][9] = 0
4916 23:45:46.647506 tx_win_center[0][0][10] = 0
4917 23:45:46.647702 tx_first_pass[0][0][10] = 0
4918 23:45:46.650991 tx_last_pass[0][0][10] = 0
4919 23:45:46.653947 tx_win_center[0][0][11] = 0
4920 23:45:46.657576 tx_first_pass[0][0][11] = 0
4921 23:45:46.657762 tx_last_pass[0][0][11] = 0
4922 23:45:46.660947 tx_win_center[0][0][12] = 0
4923 23:45:46.664346 tx_first_pass[0][0][12] = 0
4924 23:45:46.667440 tx_last_pass[0][0][12] = 0
4925 23:45:46.670778 tx_win_center[0][0][13] = 0
4926 23:45:46.671235 tx_first_pass[0][0][13] = 0
4927 23:45:46.674130 tx_last_pass[0][0][13] = 0
4928 23:45:46.677342 tx_win_center[0][0][14] = 0
4929 23:45:46.680772 tx_first_pass[0][0][14] = 0
4930 23:45:46.681186 tx_last_pass[0][0][14] = 0
4931 23:45:46.684196 tx_win_center[0][0][15] = 0
4932 23:45:46.687581 tx_first_pass[0][0][15] = 0
4933 23:45:46.690873 tx_last_pass[0][0][15] = 0
4934 23:45:46.691283 tx_win_center[0][1][0] = 0
4935 23:45:46.693875 tx_first_pass[0][1][0] = 0
4936 23:45:46.697291 tx_last_pass[0][1][0] = 0
4937 23:45:46.697704 tx_win_center[0][1][1] = 0
4938 23:45:46.700362 tx_first_pass[0][1][1] = 0
4939 23:45:46.704186 tx_last_pass[0][1][1] = 0
4940 23:45:46.707389 tx_win_center[0][1][2] = 0
4941 23:45:46.707848 tx_first_pass[0][1][2] = 0
4942 23:45:46.710813 tx_last_pass[0][1][2] = 0
4943 23:45:46.713660 tx_win_center[0][1][3] = 0
4944 23:45:46.717131 tx_first_pass[0][1][3] = 0
4945 23:45:46.717542 tx_last_pass[0][1][3] = 0
4946 23:45:46.720409 tx_win_center[0][1][4] = 0
4947 23:45:46.723694 tx_first_pass[0][1][4] = 0
4948 23:45:46.724104 tx_last_pass[0][1][4] = 0
4949 23:45:46.726994 tx_win_center[0][1][5] = 0
4950 23:45:46.730762 tx_first_pass[0][1][5] = 0
4951 23:45:46.733504 tx_last_pass[0][1][5] = 0
4952 23:45:46.734292 tx_win_center[0][1][6] = 0
4953 23:45:46.736886 tx_first_pass[0][1][6] = 0
4954 23:45:46.740166 tx_last_pass[0][1][6] = 0
4955 23:45:46.743717 tx_win_center[0][1][7] = 0
4956 23:45:46.744130 tx_first_pass[0][1][7] = 0
4957 23:45:46.747010 tx_last_pass[0][1][7] = 0
4958 23:45:46.750332 tx_win_center[0][1][8] = 0
4959 23:45:46.750804 tx_first_pass[0][1][8] = 0
4960 23:45:46.753778 tx_last_pass[0][1][8] = 0
4961 23:45:46.757281 tx_win_center[0][1][9] = 0
4962 23:45:46.760341 tx_first_pass[0][1][9] = 0
4963 23:45:46.760807 tx_last_pass[0][1][9] = 0
4964 23:45:46.763373 tx_win_center[0][1][10] = 0
4965 23:45:46.766789 tx_first_pass[0][1][10] = 0
4966 23:45:46.770136 tx_last_pass[0][1][10] = 0
4967 23:45:46.770608 tx_win_center[0][1][11] = 0
4968 23:45:46.773745 tx_first_pass[0][1][11] = 0
4969 23:45:46.777322 tx_last_pass[0][1][11] = 0
4970 23:45:46.780505 tx_win_center[0][1][12] = 0
4971 23:45:46.780974 tx_first_pass[0][1][12] = 0
4972 23:45:46.783885 tx_last_pass[0][1][12] = 0
4973 23:45:46.787063 tx_win_center[0][1][13] = 0
4974 23:45:46.790348 tx_first_pass[0][1][13] = 0
4975 23:45:46.790932 tx_last_pass[0][1][13] = 0
4976 23:45:46.793702 tx_win_center[0][1][14] = 0
4977 23:45:46.797103 tx_first_pass[0][1][14] = 0
4978 23:45:46.800464 tx_last_pass[0][1][14] = 0
4979 23:45:46.800958 tx_win_center[0][1][15] = 0
4980 23:45:46.803382 tx_first_pass[0][1][15] = 0
4981 23:45:46.806991 tx_last_pass[0][1][15] = 0
4982 23:45:46.809889 tx_win_center[1][0][0] = 0
4983 23:45:46.810343 tx_first_pass[1][0][0] = 0
4984 23:45:46.813334 tx_last_pass[1][0][0] = 0
4985 23:45:46.816729 tx_win_center[1][0][1] = 0
4986 23:45:46.820316 tx_first_pass[1][0][1] = 0
4987 23:45:46.820794 tx_last_pass[1][0][1] = 0
4988 23:45:46.823674 tx_win_center[1][0][2] = 0
4989 23:45:46.827183 tx_first_pass[1][0][2] = 0
4990 23:45:46.827656 tx_last_pass[1][0][2] = 0
4991 23:45:46.830670 tx_win_center[1][0][3] = 0
4992 23:45:46.833755 tx_first_pass[1][0][3] = 0
4993 23:45:46.836884 tx_last_pass[1][0][3] = 0
4994 23:45:46.837361 tx_win_center[1][0][4] = 0
4995 23:45:46.840385 tx_first_pass[1][0][4] = 0
4996 23:45:46.843667 tx_last_pass[1][0][4] = 0
4997 23:45:46.844096 tx_win_center[1][0][5] = 0
4998 23:45:46.846968 tx_first_pass[1][0][5] = 0
4999 23:45:46.850470 tx_last_pass[1][0][5] = 0
5000 23:45:46.853592 tx_win_center[1][0][6] = 0
5001 23:45:46.854152 tx_first_pass[1][0][6] = 0
5002 23:45:46.856967 tx_last_pass[1][0][6] = 0
5003 23:45:46.860243 tx_win_center[1][0][7] = 0
5004 23:45:46.863712 tx_first_pass[1][0][7] = 0
5005 23:45:46.864153 tx_last_pass[1][0][7] = 0
5006 23:45:46.867265 tx_win_center[1][0][8] = 0
5007 23:45:46.870692 tx_first_pass[1][0][8] = 0
5008 23:45:46.871102 tx_last_pass[1][0][8] = 0
5009 23:45:46.873947 tx_win_center[1][0][9] = 0
5010 23:45:46.877201 tx_first_pass[1][0][9] = 0
5011 23:45:46.880196 tx_last_pass[1][0][9] = 0
5012 23:45:46.880606 tx_win_center[1][0][10] = 0
5013 23:45:46.883836 tx_first_pass[1][0][10] = 0
5014 23:45:46.887181 tx_last_pass[1][0][10] = 0
5015 23:45:46.890582 tx_win_center[1][0][11] = 0
5016 23:45:46.890992 tx_first_pass[1][0][11] = 0
5017 23:45:46.894261 tx_last_pass[1][0][11] = 0
5018 23:45:46.897112 tx_win_center[1][0][12] = 0
5019 23:45:46.900406 tx_first_pass[1][0][12] = 0
5020 23:45:46.900846 tx_last_pass[1][0][12] = 0
5021 23:45:46.903870 tx_win_center[1][0][13] = 0
5022 23:45:46.907120 tx_first_pass[1][0][13] = 0
5023 23:45:46.910330 tx_last_pass[1][0][13] = 0
5024 23:45:46.910759 tx_win_center[1][0][14] = 0
5025 23:45:46.913784 tx_first_pass[1][0][14] = 0
5026 23:45:46.917090 tx_last_pass[1][0][14] = 0
5027 23:45:46.920099 tx_win_center[1][0][15] = 0
5028 23:45:46.920510 tx_first_pass[1][0][15] = 0
5029 23:45:46.923785 tx_last_pass[1][0][15] = 0
5030 23:45:46.927321 tx_win_center[1][1][0] = 0
5031 23:45:46.930628 tx_first_pass[1][1][0] = 0
5032 23:45:46.931037 tx_last_pass[1][1][0] = 0
5033 23:45:46.934158 tx_win_center[1][1][1] = 0
5034 23:45:46.937184 tx_first_pass[1][1][1] = 0
5035 23:45:46.937596 tx_last_pass[1][1][1] = 0
5036 23:45:46.940590 tx_win_center[1][1][2] = 0
5037 23:45:46.943788 tx_first_pass[1][1][2] = 0
5038 23:45:46.946951 tx_last_pass[1][1][2] = 0
5039 23:45:46.947360 tx_win_center[1][1][3] = 0
5040 23:45:46.950358 tx_first_pass[1][1][3] = 0
5041 23:45:46.953811 tx_last_pass[1][1][3] = 0
5042 23:45:46.954380 tx_win_center[1][1][4] = 0
5043 23:45:46.957027 tx_first_pass[1][1][4] = 0
5044 23:45:46.960577 tx_last_pass[1][1][4] = 0
5045 23:45:46.963730 tx_win_center[1][1][5] = 0
5046 23:45:46.964228 tx_first_pass[1][1][5] = 0
5047 23:45:46.967131 tx_last_pass[1][1][5] = 0
5048 23:45:46.970619 tx_win_center[1][1][6] = 0
5049 23:45:46.974040 tx_first_pass[1][1][6] = 0
5050 23:45:46.974452 tx_last_pass[1][1][6] = 0
5051 23:45:46.976935 tx_win_center[1][1][7] = 0
5052 23:45:46.980812 tx_first_pass[1][1][7] = 0
5053 23:45:46.981226 tx_last_pass[1][1][7] = 0
5054 23:45:46.983591 tx_win_center[1][1][8] = 0
5055 23:45:46.986860 tx_first_pass[1][1][8] = 0
5056 23:45:46.990331 tx_last_pass[1][1][8] = 0
5057 23:45:46.990742 tx_win_center[1][1][9] = 0
5058 23:45:46.994012 tx_first_pass[1][1][9] = 0
5059 23:45:46.996769 tx_last_pass[1][1][9] = 0
5060 23:45:47.000199 tx_win_center[1][1][10] = 0
5061 23:45:47.000609 tx_first_pass[1][1][10] = 0
5062 23:45:47.003665 tx_last_pass[1][1][10] = 0
5063 23:45:47.007023 tx_win_center[1][1][11] = 0
5064 23:45:47.009973 tx_first_pass[1][1][11] = 0
5065 23:45:47.010382 tx_last_pass[1][1][11] = 0
5066 23:45:47.013695 tx_win_center[1][1][12] = 0
5067 23:45:47.016507 tx_first_pass[1][1][12] = 0
5068 23:45:47.019800 tx_last_pass[1][1][12] = 0
5069 23:45:47.020240 tx_win_center[1][1][13] = 0
5070 23:45:47.023282 tx_first_pass[1][1][13] = 0
5071 23:45:47.026651 tx_last_pass[1][1][13] = 0
5072 23:45:47.029784 tx_win_center[1][1][14] = 0
5073 23:45:47.030195 tx_first_pass[1][1][14] = 0
5074 23:45:47.033045 tx_last_pass[1][1][14] = 0
5075 23:45:47.036723 tx_win_center[1][1][15] = 0
5076 23:45:47.039952 tx_first_pass[1][1][15] = 0
5077 23:45:47.040544 tx_last_pass[1][1][15] = 0
5078 23:45:47.043568 dump params rx window
5079 23:45:47.046814 rx_firspass[0][0][0] = 0
5080 23:45:47.047222 rx_lastpass[0][0][0] = 0
5081 23:45:47.050126 rx_firspass[0][0][1] = 0
5082 23:45:47.053270 rx_lastpass[0][0][1] = 0
5083 23:45:47.053680 rx_firspass[0][0][2] = 0
5084 23:45:47.056351 rx_lastpass[0][0][2] = 0
5085 23:45:47.059707 rx_firspass[0][0][3] = 0
5086 23:45:47.060117 rx_lastpass[0][0][3] = 0
5087 23:45:47.063380 rx_firspass[0][0][4] = 0
5088 23:45:47.066954 rx_lastpass[0][0][4] = 0
5089 23:45:47.070489 rx_firspass[0][0][5] = 0
5090 23:45:47.070900 rx_lastpass[0][0][5] = 0
5091 23:45:47.073149 rx_firspass[0][0][6] = 0
5092 23:45:47.076647 rx_lastpass[0][0][6] = 0
5093 23:45:47.077058 rx_firspass[0][0][7] = 0
5094 23:45:47.079961 rx_lastpass[0][0][7] = 0
5095 23:45:47.083555 rx_firspass[0][0][8] = 0
5096 23:45:47.083970 rx_lastpass[0][0][8] = 0
5097 23:45:47.086784 rx_firspass[0][0][9] = 0
5098 23:45:47.090183 rx_lastpass[0][0][9] = 0
5099 23:45:47.090593 rx_firspass[0][0][10] = 0
5100 23:45:47.093087 rx_lastpass[0][0][10] = 0
5101 23:45:47.096531 rx_firspass[0][0][11] = 0
5102 23:45:47.099854 rx_lastpass[0][0][11] = 0
5103 23:45:47.100266 rx_firspass[0][0][12] = 0
5104 23:45:47.103270 rx_lastpass[0][0][12] = 0
5105 23:45:47.106834 rx_firspass[0][0][13] = 0
5106 23:45:47.107312 rx_lastpass[0][0][13] = 0
5107 23:45:47.109763 rx_firspass[0][0][14] = 0
5108 23:45:47.112877 rx_lastpass[0][0][14] = 0
5109 23:45:47.116472 rx_firspass[0][0][15] = 0
5110 23:45:47.116896 rx_lastpass[0][0][15] = 0
5111 23:45:47.119792 rx_firspass[0][1][0] = 0
5112 23:45:47.123136 rx_lastpass[0][1][0] = 0
5113 23:45:47.123647 rx_firspass[0][1][1] = 0
5114 23:45:47.126124 rx_lastpass[0][1][1] = 0
5115 23:45:47.129827 rx_firspass[0][1][2] = 0
5116 23:45:47.130255 rx_lastpass[0][1][2] = 0
5117 23:45:47.132811 rx_firspass[0][1][3] = 0
5118 23:45:47.136041 rx_lastpass[0][1][3] = 0
5119 23:45:47.136456 rx_firspass[0][1][4] = 0
5120 23:45:47.139482 rx_lastpass[0][1][4] = 0
5121 23:45:47.142597 rx_firspass[0][1][5] = 0
5122 23:45:47.146138 rx_lastpass[0][1][5] = 0
5123 23:45:47.146549 rx_firspass[0][1][6] = 0
5124 23:45:47.149451 rx_lastpass[0][1][6] = 0
5125 23:45:47.152941 rx_firspass[0][1][7] = 0
5126 23:45:47.153348 rx_lastpass[0][1][7] = 0
5127 23:45:47.156234 rx_firspass[0][1][8] = 0
5128 23:45:47.159256 rx_lastpass[0][1][8] = 0
5129 23:45:47.159696 rx_firspass[0][1][9] = 0
5130 23:45:47.162940 rx_lastpass[0][1][9] = 0
5131 23:45:47.166130 rx_firspass[0][1][10] = 0
5132 23:45:47.166536 rx_lastpass[0][1][10] = 0
5133 23:45:47.169560 rx_firspass[0][1][11] = 0
5134 23:45:47.172909 rx_lastpass[0][1][11] = 0
5135 23:45:47.176181 rx_firspass[0][1][12] = 0
5136 23:45:47.176588 rx_lastpass[0][1][12] = 0
5137 23:45:47.179151 rx_firspass[0][1][13] = 0
5138 23:45:47.182597 rx_lastpass[0][1][13] = 0
5139 23:45:47.183007 rx_firspass[0][1][14] = 0
5140 23:45:47.185791 rx_lastpass[0][1][14] = 0
5141 23:45:47.189273 rx_firspass[0][1][15] = 0
5142 23:45:47.192842 rx_lastpass[0][1][15] = 0
5143 23:45:47.193253 rx_firspass[1][0][0] = 0
5144 23:45:47.196343 rx_lastpass[1][0][0] = 0
5145 23:45:47.199204 rx_firspass[1][0][1] = 0
5146 23:45:47.199647 rx_lastpass[1][0][1] = 0
5147 23:45:47.202173 rx_firspass[1][0][2] = 0
5148 23:45:47.205629 rx_lastpass[1][0][2] = 0
5149 23:45:47.205726 rx_firspass[1][0][3] = 0
5150 23:45:47.209220 rx_lastpass[1][0][3] = 0
5151 23:45:47.212648 rx_firspass[1][0][4] = 0
5152 23:45:47.215313 rx_lastpass[1][0][4] = 0
5153 23:45:47.215436 rx_firspass[1][0][5] = 0
5154 23:45:47.218661 rx_lastpass[1][0][5] = 0
5155 23:45:47.222356 rx_firspass[1][0][6] = 0
5156 23:45:47.222483 rx_lastpass[1][0][6] = 0
5157 23:45:47.225237 rx_firspass[1][0][7] = 0
5158 23:45:47.228679 rx_lastpass[1][0][7] = 0
5159 23:45:47.228841 rx_firspass[1][0][8] = 0
5160 23:45:47.232095 rx_lastpass[1][0][8] = 0
5161 23:45:47.235278 rx_firspass[1][0][9] = 0
5162 23:45:47.235482 rx_lastpass[1][0][9] = 0
5163 23:45:47.239121 rx_firspass[1][0][10] = 0
5164 23:45:47.242014 rx_lastpass[1][0][10] = 0
5165 23:45:47.245331 rx_firspass[1][0][11] = 0
5166 23:45:47.245602 rx_lastpass[1][0][11] = 0
5167 23:45:47.248602 rx_firspass[1][0][12] = 0
5168 23:45:47.252517 rx_lastpass[1][0][12] = 0
5169 23:45:47.252864 rx_firspass[1][0][13] = 0
5170 23:45:47.255975 rx_lastpass[1][0][13] = 0
5171 23:45:47.258768 rx_firspass[1][0][14] = 0
5172 23:45:47.262025 rx_lastpass[1][0][14] = 0
5173 23:45:47.262452 rx_firspass[1][0][15] = 0
5174 23:45:47.265680 rx_lastpass[1][0][15] = 0
5175 23:45:47.269064 rx_firspass[1][1][0] = 0
5176 23:45:47.269473 rx_lastpass[1][1][0] = 0
5177 23:45:47.272484 rx_firspass[1][1][1] = 0
5178 23:45:47.275454 rx_lastpass[1][1][1] = 0
5179 23:45:47.275866 rx_firspass[1][1][2] = 0
5180 23:45:47.278972 rx_lastpass[1][1][2] = 0
5181 23:45:47.282266 rx_firspass[1][1][3] = 0
5182 23:45:47.282676 rx_lastpass[1][1][3] = 0
5183 23:45:47.285884 rx_firspass[1][1][4] = 0
5184 23:45:47.289359 rx_lastpass[1][1][4] = 0
5185 23:45:47.289832 rx_firspass[1][1][5] = 0
5186 23:45:47.292158 rx_lastpass[1][1][5] = 0
5187 23:45:47.295920 rx_firspass[1][1][6] = 0
5188 23:45:47.299268 rx_lastpass[1][1][6] = 0
5189 23:45:47.299769 rx_firspass[1][1][7] = 0
5190 23:45:47.302640 rx_lastpass[1][1][7] = 0
5191 23:45:47.305831 rx_firspass[1][1][8] = 0
5192 23:45:47.306310 rx_lastpass[1][1][8] = 0
5193 23:45:47.309217 rx_firspass[1][1][9] = 0
5194 23:45:47.312134 rx_lastpass[1][1][9] = 0
5195 23:45:47.312599 rx_firspass[1][1][10] = 0
5196 23:45:47.315514 rx_lastpass[1][1][10] = 0
5197 23:45:47.319080 rx_firspass[1][1][11] = 0
5198 23:45:47.319550 rx_lastpass[1][1][11] = 0
5199 23:45:47.322623 rx_firspass[1][1][12] = 0
5200 23:45:47.325875 rx_lastpass[1][1][12] = 0
5201 23:45:47.329044 rx_firspass[1][1][13] = 0
5202 23:45:47.329533 rx_lastpass[1][1][13] = 0
5203 23:45:47.332622 rx_firspass[1][1][14] = 0
5204 23:45:47.336007 rx_lastpass[1][1][14] = 0
5205 23:45:47.336491 rx_firspass[1][1][15] = 0
5206 23:45:47.338866 rx_lastpass[1][1][15] = 0
5207 23:45:47.342712 dump params clk_delay
5208 23:45:47.343194 clk_delay[0] = 0
5209 23:45:47.345857 clk_delay[1] = 0
5210 23:45:47.346329 dump params dqs_delay
5211 23:45:47.349247 dqs_delay[0][0] = 0
5212 23:45:47.349705 dqs_delay[0][1] = 0
5213 23:45:47.352250 dqs_delay[1][0] = 0
5214 23:45:47.352712 dqs_delay[1][1] = 0
5215 23:45:47.356139 dump params delay_cell_unit = 735
5216 23:45:47.359312 mt_set_emi_preloader end
5217 23:45:47.362652 [mt_mem_init] dram size: 0x100000000, rank number: 2
5218 23:45:47.368906 [complex_mem_test] start addr:0x40000000, len:20480
5219 23:45:47.404981 [mt_mem_init] preloader addr:0x40000000 complex R/W mem test pass : 0
5220 23:45:47.411714 [complex_mem_test] start addr:0x80000000, len:20480
5221 23:45:47.447379 [mt_mem_init] preloader addr:0x80000000 complex R/W mem test pass : 0
5222 23:45:47.454384 [complex_mem_test] start addr:0xc0000000, len:20480
5223 23:45:47.489557 [mt_mem_init] preloader addr:0xc0000000 complex R/W mem test pass : 0
5224 23:45:47.496102 [complex_mem_test] start addr:0x56000000, len:8192
5225 23:45:47.512634 [MEM] 1st complex R/W mem test pass (start addr:0x56000000)
5226 23:45:47.512791 ddr_geometry:1
5227 23:45:47.518974 [complex_mem_test] start addr:0x80000000, len:8192
5228 23:45:47.536684 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
5229 23:45:47.539992 dram_init: dram init end (result: 0)
5230 23:45:47.546415 Successfully loaded DRAM blobs and ran DRAM calibration
5231 23:45:47.556150 Mapping address range [0000000040000000:0000000140000000) as cacheable | read-write | non-secure | normal
5232 23:45:47.556287 CBMEM:
5233 23:45:47.559795 IMD: root @ 00000000fffff000 254 entries.
5234 23:45:47.563038 IMD: root @ 00000000ffffec00 62 entries.
5235 23:45:47.570060 VBOOT: copying vboot_working_data (256 bytes) to CBMEM...
5236 23:45:47.576092 out: cmd=0xa4: 03 6c a4 00 00 00 0c 00 00 01 00 00 50 7f 11 00 00 00 00 00
5237 23:45:47.579464 in-header: 03 a1 00 00 08 00 00 00
5238 23:45:47.582464 in-data: 84 60 60 10 00 00 00 00
5239 23:45:47.585768 Chrome EC: clear events_b mask to 0x0000000020004000
5240 23:45:47.593496 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
5241 23:45:47.596774 in-header: 03 fd 00 00 00 00 00 00
5242 23:45:47.596896 in-data:
5243 23:45:47.603954 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5244 23:45:47.604045 CBFS @ 21000 size 3d4000
5245 23:45:47.610005 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5246 23:45:47.613597 CBFS: Locating 'fallback/ramstage'
5247 23:45:47.616642 CBFS: Found @ offset 10d40 size d563
5248 23:45:47.638294 read SPI 0x31d94 0xd547: 16640 us, 3281 KB/s, 26.248 Mbps
5249 23:45:47.650634 Accumulated console time in romstage 13607 ms
5250 23:45:47.651171
5251 23:45:47.651699
5252 23:45:47.660806 coreboot-v1.9308_26_0.0.22-10565-g8487d48179 Sun Jan 30 03:25:20 UTC 2022 ramstage starting (log level: 8)...
5253 23:45:47.663698 ARM64: Exception handlers installed.
5254 23:45:47.664001 ARM64: Testing exception
5255 23:45:47.667115 ARM64: Done test exception
5256 23:45:47.670520 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
5257 23:45:47.673740 Manufacturer: ef
5258 23:45:47.676860 SF: Detected W25Q64DW with sector size 0x1000, total 0x800000
5259 23:45:47.683710 WARNING: RO_VPD is uninitialized or empty.
5260 23:45:47.686987 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5261 23:45:47.690328 FMAP: area RW_VPD found @ 550000 (16384 bytes)
5262 23:45:47.699812 read SPI 0x550600 0x3a00: 4532 us, 3276 KB/s, 26.208 Mbps
5263 23:45:47.703498 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
5264 23:45:47.710312 BS: BS_DEV_INIT_CHIPS times (ms): entry 0 run 0 exit 0
5265 23:45:47.710418 Enumerating buses...
5266 23:45:47.716643 Show all devs... Before device enumeration.
5267 23:45:47.716724 Root Device: enabled 1
5268 23:45:47.720006 CPU_CLUSTER: 0: enabled 1
5269 23:45:47.720125 CPU: 00: enabled 1
5270 23:45:47.723474 Compare with tree...
5271 23:45:47.727031 Root Device: enabled 1
5272 23:45:47.727121 CPU_CLUSTER: 0: enabled 1
5273 23:45:47.729777 CPU: 00: enabled 1
5274 23:45:47.733152 Root Device scanning...
5275 23:45:47.733241 root_dev_scan_bus for Root Device
5276 23:45:47.736422 CPU_CLUSTER: 0 enabled
5277 23:45:47.740044 root_dev_scan_bus for Root Device done
5278 23:45:47.746745 scan_bus: scanning of bus Root Device took 10689 usecs
5279 23:45:47.746836 done
5280 23:45:47.750226 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 0 exit 0
5281 23:45:47.752986 Allocating resources...
5282 23:45:47.753078 Reading resources...
5283 23:45:47.756689 Root Device read_resources bus 0 link: 0
5284 23:45:47.763068 CPU_CLUSTER: 0 read_resources bus 0 link: 0
5285 23:45:47.763158 CPU: 00 missing read_resources
5286 23:45:47.769889 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
5287 23:45:47.773510 Root Device read_resources bus 0 link: 0 done
5288 23:45:47.776203 Done reading resources.
5289 23:45:47.779642 Show resources in subtree (Root Device)...After reading.
5290 23:45:47.782971 Root Device child on link 0 CPU_CLUSTER: 0
5291 23:45:47.786748 CPU_CLUSTER: 0 child on link 0 CPU: 00
5292 23:45:47.796342 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5293 23:45:47.796481 CPU: 00
5294 23:45:47.799740 Setting resources...
5295 23:45:47.803167 Root Device assign_resources, bus 0 link: 0
5296 23:45:47.806727 CPU_CLUSTER: 0 missing set_resources
5297 23:45:47.809572 Root Device assign_resources, bus 0 link: 0
5298 23:45:47.812978 Done setting resources.
5299 23:45:47.819658 Show resources in subtree (Root Device)...After assigning values.
5300 23:45:47.822933 Root Device child on link 0 CPU_CLUSTER: 0
5301 23:45:47.826437 CPU_CLUSTER: 0 child on link 0 CPU: 00
5302 23:45:47.836234 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
5303 23:45:47.836392 CPU: 00
5304 23:45:47.840019 Done allocating resources.
5305 23:45:47.842863 BS: BS_DEV_RESOURCES times (ms): entry 0 run 0 exit 0
5306 23:45:47.846341 Enabling resources...
5307 23:45:47.846431 done.
5308 23:45:47.849827 BS: BS_DEV_ENABLE times (ms): entry 0 run 0 exit 0
5309 23:45:47.852693 Initializing devices...
5310 23:45:47.852783 Root Device init ...
5311 23:45:47.856195 mainboard_init: Starting display init.
5312 23:45:47.859704 ADC[4]: Raw value=76102 ID=0
5313 23:45:47.882589 anx7625_power_on_init: Init interface.
5314 23:45:47.886119 anx7625_disable_pd_protocol: Disabled PD feature.
5315 23:45:47.892912 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
5316 23:45:47.939543 anx7625_start_dp_work: Secure OCM version=00
5317 23:45:47.942921 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
5318 23:45:47.959707 sp_tx_get_edid_block: EDID Block = 1
5319 23:45:48.077432 Extracted contents:
5320 23:45:48.080366 header: 00 ff ff ff ff ff ff 00
5321 23:45:48.083723 serial number: 06 af 5c 14 00 00 00 00 00 1a
5322 23:45:48.087196 version: 01 04
5323 23:45:48.090730 basic params: 95 1a 0e 78 02
5324 23:45:48.094065 chroma info: 99 85 95 55 56 92 28 22 50 54
5325 23:45:48.097243 established: 00 00 00
5326 23:45:48.104028 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
5327 23:45:48.107296 descriptor 1: ce 1d 56 ea 50 00 1a 30 30 20 46 00 00 90 10 00 00 18
5328 23:45:48.113750 descriptor 2: 00 00 00 0f 00 00 00 00 00 00 00 00 00 00 00 00 00 20
5329 23:45:48.120902 descriptor 3: 00 00 00 fe 00 41 55 4f 0a 20 20 20 20 20 20 20 20 20
5330 23:45:48.127080 descriptor 4: 00 00 00 fe 00 42 31 31 36 58 41 42 30 31 2e 34 20 0a
5331 23:45:48.130470 extensions: 00
5332 23:45:48.130777 checksum: ae
5333 23:45:48.130993
5334 23:45:48.134084 Manufacturer: AUO Model 145c Serial Number 0
5335 23:45:48.137204 Made week 0 of 2016
5336 23:45:48.137474 EDID version: 1.4
5337 23:45:48.140775 Digital display
5338 23:45:48.143986 6 bits per primary color channel
5339 23:45:48.144259 DisplayPort interface
5340 23:45:48.147479 Maximum image size: 26 cm x 14 cm
5341 23:45:48.150495 Gamma: 220%
5342 23:45:48.150790 Check DPMS levels
5343 23:45:48.153892 Supported color formats: RGB 4:4:4
5344 23:45:48.157429 First detailed timing is preferred timing
5345 23:45:48.160673 Established timings supported:
5346 23:45:48.163782 Standard timings supported:
5347 23:45:48.164176 Detailed timings
5348 23:45:48.170618 Hex of detail: ce1d56ea50001a3030204600009010000018
5349 23:45:48.173951 Detailed mode (IN HEX): Clock 76300 KHz, 100 mm x 90 mm
5350 23:45:48.176852 0556 0586 05a6 0640 hborder 0
5351 23:45:48.180582 0300 0304 030a 031a vborder 0
5352 23:45:48.183834 -hsync -vsync
5353 23:45:48.187150 Did detailed timing
5354 23:45:48.190446 Hex of detail: 0000000f0000000000000000000000000020
5355 23:45:48.194124 Manufacturer-specified data, tag 15
5356 23:45:48.196736 Hex of detail: 000000fe0041554f0a202020202020202020
5357 23:45:48.200216 ASCII string: AUO
5358 23:45:48.203720 Hex of detail: 000000fe004231313658414230312e34200a
5359 23:45:48.207164 ASCII string: B116XAB01.4
5360 23:45:48.207563 Checksum
5361 23:45:48.210215 Checksum: 0xae (valid)
5362 23:45:48.216882 get_active_panel: Found ID 1: 'AUO B116XAB01.4 ' 1366x768@0Hz
5363 23:45:48.217436 DSI data_rate: 457800000 bps
5364 23:45:48.224226 anx7625_parse_edid: set default k value to 0x3d for panel
5365 23:45:48.227413 anx7625_parse_edid: pixelclock(76300).
5366 23:45:48.230548 hactive(1366), hsync(32), hfp(48), hbp(154)
5367 23:45:48.234005 vactive(768), vsync(6), vfp(4), vbp(16)
5368 23:45:48.237405 anx7625_dsi_config: config dsi.
5369 23:45:48.245500 anx7625_dsi_video_config: compute M(12500992), N(552960), divider(8).
5370 23:45:48.266126 anx7625_dsi_config: success to config DSI
5371 23:45:48.269993 anx7625_dp_start: MIPI phy setup OK.
5372 23:45:48.272779 [SSUSB] Setting up USB HOST controller...
5373 23:45:48.276285 [SSUSB] u3phy_ports_enable u2p:1, u3p:0
5374 23:45:48.276374 [SSUSB] phy power-on done.
5375 23:45:48.283768 out: cmd=0xf: 03 da 0f 00 00 00 04 00 10 00 00 00
5376 23:45:48.286633 in-header: 03 fc 01 00 00 00 00 00
5377 23:45:48.286751 in-data:
5378 23:45:48.290144 handle_proto3_response: EC response with error code: 1
5379 23:45:48.293429 SPM: pcm index = 1
5380 23:45:48.296952 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5381 23:45:48.300225 CBFS @ 21000 size 3d4000
5382 23:45:48.306612 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5383 23:45:48.310352 CBFS: Locating 'pcm_allinone_lp4_3200.bin'
5384 23:45:48.313502 CBFS: Found @ offset 1e7c0 size 1026
5385 23:45:48.319914 read SPI 0x3f808 0x1026: 1272 us, 3250 KB/s, 26.000 Mbps
5386 23:45:48.323714 SPM: binary array size = 2988
5387 23:45:48.327021 SPM: version = pcm_allinone_v1.17.2_20180829
5388 23:45:48.330100 SPM binary loaded in 32 msecs
5389 23:45:48.337652 spm_kick_im_to_fetch: ptr = 000000004021eec2
5390 23:45:48.340645 spm_kick_im_to_fetch: len = 2988
5391 23:45:48.340735 SPM: spm_kick_pcm_to_run
5392 23:45:48.344187 SPM: spm_kick_pcm_to_run done
5393 23:45:48.347421 SPM: spm_init done in 52 msecs
5394 23:45:48.350847 Root Device init finished in 494975 usecs
5395 23:45:48.354320 CPU_CLUSTER: 0 init ...
5396 23:45:48.360898 Mapping address range [0000000000200000:0000000000280000) as cacheable | read-write | secure | device
5397 23:45:48.367678 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5398 23:45:48.370834 CBFS @ 21000 size 3d4000
5399 23:45:48.374092 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5400 23:45:48.377901 CBFS: Locating 'sspm.bin'
5401 23:45:48.380974 CBFS: Found @ offset 208c0 size 41cb
5402 23:45:48.390788 read SPI 0x418f8 0x41cb: 5141 us, 3276 KB/s, 26.208 Mbps
5403 23:45:48.398361 CPU_CLUSTER: 0 init finished in 42803 usecs
5404 23:45:48.398451 Devices initialized
5405 23:45:48.401919 Show all devs... After init.
5406 23:45:48.405330 Root Device: enabled 1
5407 23:45:48.405419 CPU_CLUSTER: 0: enabled 1
5408 23:45:48.409065 CPU: 00: enabled 1
5409 23:45:48.411780 BS: BS_DEV_INIT times (ms): entry 0 run 224 exit 0
5410 23:45:48.415302 FMAP: area RW_ELOG found @ 558000 (4096 bytes)
5411 23:45:48.418815 ELOG: NV offset 0x558000 size 0x1000
5412 23:45:48.426372 read SPI 0x558000 0x1000: 1263 us, 3243 KB/s, 25.944 Mbps
5413 23:45:48.432384 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
5414 23:45:48.435828 ELOG: Event(17) added with size 13 at 2024-06-04 23:44:51 UTC
5415 23:45:48.442484 out: cmd=0x121: 03 db 21 01 00 00 00 00
5416 23:45:48.445903 in-header: 03 bf 00 00 2c 00 00 00
5417 23:45:48.455603 in-data: 63 4b 00 00 00 00 00 00 02 10 00 00 06 80 00 00 bb 96 07 00 06 80 00 00 37 d4 63 00 06 80 00 00 6a 27 01 00 06 80 00 00 92 4e 02 00
5418 23:45:48.458777 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
5419 23:45:48.462417 in-header: 03 19 00 00 08 00 00 00
5420 23:45:48.465750 in-data: a2 e0 47 00 13 00 00 00
5421 23:45:48.468976 Chrome EC: UHEPI supported
5422 23:45:48.475242 out: cmd=0xa4: 03 54 a4 00 00 00 0c 00 00 01 00 00 f8 ff 01 00 00 00 00 00
5423 23:45:48.478599 in-header: 03 e1 00 00 08 00 00 00
5424 23:45:48.482190 in-data: 84 20 60 10 00 00 00 00
5425 23:45:48.485403 FMAP: area RW_NVRAM found @ 554000 (8192 bytes)
5426 23:45:48.492278 out: cmd=0xa4: 03 c9 a4 00 00 00 0c 00 00 01 00 00 00 20 23 40 00 00 00 00
5427 23:45:48.495482 in-header: 03 e1 00 00 08 00 00 00
5428 23:45:48.498991 in-data: 84 20 60 10 00 00 00 00
5429 23:45:48.505369 ELOG: Event(A1) added with size 10 at 2024-06-04 23:44:51 UTC
5430 23:45:48.511872 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
5431 23:45:48.518789 ELOG: Event(A0) added with size 9 at 2024-06-04 23:44:51 UTC
5432 23:45:48.521709 elog_add_boot_reason: Logged dev mode boot
5433 23:45:48.521799 Finalize devices...
5434 23:45:48.525650 Devices finalized
5435 23:45:48.528743 BS: BS_POST_DEVICE times (ms): entry 3 run 0 exit 0
5436 23:45:48.535542 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
5437 23:45:48.538357 ELOG: Event(91) added with size 10 at 2024-06-04 23:44:51 UTC
5438 23:45:48.542016 Writing coreboot table at 0xffeda000
5439 23:45:48.548164 0. 0000000000114000-000000000011efff: RAMSTAGE
5440 23:45:48.551474 1. 0000000040000000-000000004023cfff: RAMSTAGE
5441 23:45:48.554860 2. 000000004023d000-00000000545fffff: RAM
5442 23:45:48.558211 3. 0000000054600000-000000005465ffff: BL31
5443 23:45:48.562008 4. 0000000054660000-00000000ffed9fff: RAM
5444 23:45:48.568073 5. 00000000ffeda000-00000000ffffffff: CONFIGURATION TABLES
5445 23:45:48.571805 6. 0000000100000000-000000013fffffff: RAM
5446 23:45:48.575045 Passing 5 GPIOs to payload:
5447 23:45:48.578214 NAME | PORT | POLARITY | VALUE
5448 23:45:48.584890 write protect | 0x00000096 | low | high
5449 23:45:48.588094 EC in RW | 0x000000b1 | high | undefined
5450 23:45:48.591756 EC interrupt | 0x00000097 | low | undefined
5451 23:45:48.598288 TPM interrupt | 0x00000099 | high | undefined
5452 23:45:48.601822 speaker enable | 0x000000af | high | undefined
5453 23:45:48.604627 out: cmd=0x6: 03 f7 06 00 00 00 00 00
5454 23:45:48.608314 in-header: 03 f7 00 00 02 00 00 00
5455 23:45:48.611393 in-data: 04 00
5456 23:45:48.611492 Board ID: 4
5457 23:45:48.614772 ADC[3]: Raw value=215504 ID=1
5458 23:45:48.614863 RAM code: 1
5459 23:45:48.618219 SKU ID: 16
5460 23:45:48.621719 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5461 23:45:48.624654 CBFS @ 21000 size 3d4000
5462 23:45:48.627962 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5463 23:45:48.634952 Wrote coreboot table at: 00000000ffeda000, 0x394 bytes, checksum 834c
5464 23:45:48.638205 coreboot table: 940 bytes.
5465 23:45:48.641735 IMD ROOT 0. 00000000fffff000 00001000
5466 23:45:48.644885 IMD SMALL 1. 00000000ffffe000 00001000
5467 23:45:48.648167 CONSOLE 2. 00000000fffde000 00020000
5468 23:45:48.651584 FMAP 3. 00000000fffdd000 0000047c
5469 23:45:48.654487 TIME STAMP 4. 00000000fffdc000 00000910
5470 23:45:48.657723 RAMOOPS 5. 00000000ffedc000 00100000
5471 23:45:48.661378 COREBOOT 6. 00000000ffeda000 00002000
5472 23:45:48.664744 IMD small region:
5473 23:45:48.667639 IMD ROOT 0. 00000000ffffec00 00000400
5474 23:45:48.671321 VBOOT WORK 1. 00000000ffffeb00 00000100
5475 23:45:48.674443 EC HOSTEVENT 2. 00000000ffffeae0 00000008
5476 23:45:48.677904 VPD 3. 00000000ffffea60 0000006c
5477 23:45:48.684551 BS: BS_WRITE_TABLES times (ms): entry 0 run 0 exit 0
5478 23:45:48.691087 out: cmd=0xa4: 03 95 a4 00 00 00 0c 00 00 01 00 00 24 32 21 40 00 00 00 00
5479 23:45:48.694393 in-header: 03 e1 00 00 08 00 00 00
5480 23:45:48.697631 in-data: 84 20 60 10 00 00 00 00
5481 23:45:48.700797 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5482 23:45:48.704404 CBFS @ 21000 size 3d4000
5483 23:45:48.707672 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5484 23:45:48.710822 CBFS: Locating 'fallback/payload'
5485 23:45:48.720376 CBFS: Found @ offset dc040 size 439a0
5486 23:45:48.808083 read SPI 0xfd078 0x439a0: 84379 us, 3281 KB/s, 26.248 Mbps
5487 23:45:48.812017 Checking segment from ROM address 0x0000000040003a00
5488 23:45:48.817991 Checking segment from ROM address 0x0000000040003a1c
5489 23:45:48.821348 Loading segment from ROM address 0x0000000040003a00
5490 23:45:48.825304 code (compression=0)
5491 23:45:48.831520 New segment dstaddr 0x0000000080000000 memsize 0x11994a0 srcaddr 0x0000000040003a38 filesize 0x43968
5492 23:45:48.841590 Loading Segment: addr: 0x0000000080000000 memsz: 0x00000000011994a0 filesz: 0x0000000000043968
5493 23:45:48.845107 it's not compressed!
5494 23:45:48.848505 [ 0x80000000, 80043968, 0x811994a0) <- 40003a38
5495 23:45:48.855140 Clearing Segment: addr: 0x0000000080043968 memsz: 0x0000000001155b38
5496 23:45:48.862596 Loading segment from ROM address 0x0000000040003a1c
5497 23:45:48.866079 Entry Point 0x0000000080000000
5498 23:45:48.866169 Loaded segments
5499 23:45:48.872248 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 92 exit 0
5500 23:45:48.876043 Jumping to boot code at 0000000080000000(00000000ffeda000)
5501 23:45:48.885509 CPU0: stack: 0000000000114000 - 0000000000118000, lowest used address 0000000000117540, stack used: 2752 bytes
5502 23:45:48.888912 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
5503 23:45:48.892373 CBFS @ 21000 size 3d4000
5504 23:45:48.898930 CBFS: 'Master Header Locator' located CBFS at [21000:3f5000)
5505 23:45:48.902287 CBFS: Locating 'fallback/bl31'
5506 23:45:48.905566 CBFS: Found @ offset 36dc0 size 5820
5507 23:45:48.916556 read SPI 0x57de8 0x5820: 6880 us, 3279 KB/s, 26.232 Mbps
5508 23:45:48.919969 Checking segment from ROM address 0x0000000040003a00
5509 23:45:48.926727 Checking segment from ROM address 0x0000000040003a1c
5510 23:45:48.929595 Loading segment from ROM address 0x0000000040003a00
5511 23:45:48.933359 code (compression=1)
5512 23:45:48.939739 New segment dstaddr 0x0000000054600000 memsize 0x29000 srcaddr 0x0000000040003a38 filesize 0x57e8
5513 23:45:48.949414 Loading Segment: addr: 0x0000000054600000 memsz: 0x0000000000029000 filesz: 0x00000000000057e8
5514 23:45:48.949505 using LZMA
5515 23:45:48.958119 [ 0x54600000, 5460f420, 0x54629000) <- 40003a38
5516 23:45:48.964670 Clearing Segment: addr: 0x000000005460f420 memsz: 0x0000000000019be0
5517 23:45:48.968353 Loading segment from ROM address 0x0000000040003a1c
5518 23:45:48.971713 Entry Point 0x0000000054601000
5519 23:45:48.971804 Loaded segments
5520 23:45:48.975055 NOTICE: MT8183 bl31_setup
5521 23:45:48.982076 NOTICE: BL31: v2.1(debug):v2.1-806-g3addeb68c
5522 23:45:48.985548 NOTICE: BL31: Built : Sun Jan 30 03:25:20 UTC 2022
5523 23:45:48.988766 INFO: [DEVAPC] dump DEVAPC registers:
5524 23:45:48.998302 INFO: [DEVAPC] (INFRA)D0_APC_0 = 0x0, (INFRA)D1_APC_0 = 0xfcfffffc, (INFRA)D2_APC_0 = 0x0
5525 23:45:49.005105 INFO: [DEVAPC] (INFRA)D0_APC_1 = 0x0, (INFRA)D1_APC_1 = 0xffffffff, (INFRA)D2_APC_1 = 0x0
5526 23:45:49.015228 INFO: [DEVAPC] (INFRA)D0_APC_2 = 0x0, (INFRA)D1_APC_2 = 0xffffffff, (INFRA)D2_APC_2 = 0x0
5527 23:45:49.021881 INFO: [DEVAPC] (INFRA)D0_APC_3 = 0x0, (INFRA)D1_APC_3 = 0xffffffff, (INFRA)D2_APC_3 = 0x0
5528 23:45:49.031743 INFO: [DEVAPC] (INFRA)D0_APC_4 = 0x80000000, (INFRA)D1_APC_4 = 0xffffffff, (INFRA)D2_APC_4 = 0x0
5529 23:45:49.038429 INFO: [DEVAPC] (INFRA)D0_APC_5 = 0x2aaa, (INFRA)D1_APC_5 = 0xfcff3fff, (INFRA)D2_APC_5 = 0x0
5530 23:45:49.048620 INFO: [DEVAPC] (INFRA)D0_APC_6 = 0x0, (INFRA)D1_APC_6 = 0xffffffff, (INFRA)D2_APC_6 = 0x0
5531 23:45:49.055462 INFO: [DEVAPC] (INFRA)D0_APC_7 = 0x0, (INFRA)D1_APC_7 = 0xffffffff, (INFRA)D2_APC_7 = 0x0
5532 23:45:49.061438 INFO: [DEVAPC] (INFRA)D0_APC_8 = 0x0, (INFRA)D1_APC_8 = 0xffffffff, (INFRA)D2_APC_8 = 0x0
5533 23:45:49.071617 INFO: [DEVAPC] (INFRA)D0_APC_9 = 0x0, (INFRA)D1_APC_9 = 0xffffffff, (INFRA)D2_APC_9 = 0x0
5534 23:45:49.078194 INFO: [DEVAPC] (INFRA)D0_APC_10 = 0x0, (INFRA)D1_APC_10 = 0xffffffff, (INFRA)D2_APC_10 = 0x0
5535 23:45:49.087965 INFO: [DEVAPC] (INFRA)D0_APC_11 = 0x0, (INFRA)D1_APC_11 = 0xffffffff, (INFRA)D2_APC_11 = 0x0
5536 23:45:49.094871 INFO: [DEVAPC] (INFRA)D0_APC_12 = 0x0, (INFRA)D1_APC_12 = 0xff, (INFRA)D2_APC_12 = 0x0
5537 23:45:49.104498 INFO: [DEVAPC] (MM)D0_APC_0 = 0x0, (MM)D1_APC_0 = 0xffc000ff, (MM)D2_APC_0 = 0x0
5538 23:45:49.111495 INFO: [DEVAPC] (MM)D0_APC_1 = 0x0, (MM)D1_APC_1 = 0x3fffffff, (MM)D2_APC_1 = 0x0
5539 23:45:49.117761 INFO: [DEVAPC] (MM)D0_APC_2 = 0x0, (MM)D1_APC_2 = 0xcffff33c, (MM)D2_APC_2 = 0x0
5540 23:45:49.124358 INFO: [DEVAPC] (MM)D0_APC_3 = 0x0, (MM)D1_APC_3 = 0x3ccfc0ff, (MM)D2_APC_3 = 0x0
5541 23:45:49.130889 INFO: [DEVAPC] (MM)D0_APC_4 = 0x0, (MM)D1_APC_4 = 0xffff0000, (MM)D2_APC_4 = 0x0
5542 23:45:49.141000 INFO: [DEVAPC] (MM)D0_APC_5 = 0x0, (MM)D1_APC_5 = 0xffffffff, (MM)D2_APC_5 = 0x0
5543 23:45:49.147612 INFO: [DEVAPC] (MM)D0_APC_6 = 0x0, (MM)D1_APC_6 = 0xffffffff, (MM)D2_APC_6 = 0x0
5544 23:45:49.154633 INFO: [DEVAPC] (MM)D0_APC_7 = 0x0, (MM)D1_APC_7 = 0xffffffff, (MM)D2_APC_7 = 0x0
5545 23:45:49.160695 INFO: [DEVAPC] (MM)D0_APC_8 = 0x0, (MM)D1_APC_8 = 0x3ffffff, (MM)D2_APC_8 = 0x0
5546 23:45:49.164089 INFO: [DEVAPC] MAS_DOM_0 = 0x1
5547 23:45:49.167578 INFO: [DEVAPC] MAS_DOM_1 = 0x200
5548 23:45:49.170757 INFO: [DEVAPC] MAS_DOM_2 = 0x0
5549 23:45:49.173957 INFO: [DEVAPC] MAS_DOM_3 = 0x2000
5550 23:45:49.177322 INFO: [DEVAPC] MAS_SEC_0 = 0x8000000
5551 23:45:49.183980 INFO: [DEVAPC] (INFRA)MAS_DOMAIN_REMAP_0 = 0x88, (INFRA)MAS_DOMAIN_REMAP_1 = 0x0
5552 23:45:49.190585 INFO: [DEVAPC] (MM)MAS_DOMAIN_REMAP_0 = 0x24
5553 23:45:49.190675 WARNING: region 0:
5554 23:45:49.194236 WARNING: apc:0x168, sa:0x0, ea:0xfff
5555 23:45:49.197037 WARNING: region 1:
5556 23:45:49.200080 WARNING: apc:0x140, sa:0x1000, ea:0x128f
5557 23:45:49.200170 WARNING: region 2:
5558 23:45:49.206862 WARNING: apc:0x168, sa:0x1290, ea:0x1fff
5559 23:45:49.206953 WARNING: region 3:
5560 23:45:49.210335 WARNING: apc:0x168, sa:0x2000, ea:0xbfff
5561 23:45:49.213725 WARNING: region 4:
5562 23:45:49.217189 WARNING: apc:0x168, sa:0xc000, ea:0x1ffff
5563 23:45:49.217279 WARNING: region 5:
5564 23:45:49.220839 WARNING: apc:0x0, sa:0x0, ea:0x0
5565 23:45:49.223876 WARNING: region 6:
5566 23:45:49.227049 WARNING: apc:0x0, sa:0x0, ea:0x0
5567 23:45:49.227139 WARNING: region 7:
5568 23:45:49.230085 WARNING: apc:0x0, sa:0x0, ea:0x0
5569 23:45:49.237080 INFO: GICv3 without legacy support detected. ARM GICv3 driver initialized in EL3
5570 23:45:49.240308 INFO: SPM: enable SPMC mode
5571 23:45:49.243718 NOTICE: spm_boot_init() start
5572 23:45:49.246938 NOTICE: spm_boot_init() end
5573 23:45:49.250109 INFO: BL31: Initializing runtime services
5574 23:45:49.256466 INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
5575 23:45:49.260053 INFO: BL31: Preparing for EL3 exit to normal world
5576 23:45:49.263294 INFO: Entry point address = 0x80000000
5577 23:45:49.266632 INFO: SPSR = 0x8
5578 23:45:49.288869
5579 23:45:49.289004
5580 23:45:49.289094
5581 23:45:49.289592 end: 2.2.3 depthcharge-start (duration 00:00:11) [common]
5582 23:45:49.289707 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
5583 23:45:49.289800 Setting prompt string to ['jacuzzi:']
5584 23:45:49.289893 bootloader-commands: Wait for prompt ['jacuzzi:'] (timeout 00:04:26)
5585 23:45:49.291897 Starting depthcharge on Juniper...
5586 23:45:49.291988
5587 23:45:49.295165 vboot_handoff: creating legacy vboot_handoff structure
5588 23:45:49.295283
5589 23:45:49.298395 ec_init(0): CrosEC protocol v3 supported (544, 544)
5590 23:45:49.298486
5591 23:45:49.301755 Wipe memory regions:
5592 23:45:49.301846
5593 23:45:49.304723 [0x00000040000000, 0x00000054600000)
5594 23:45:49.347848
5595 23:45:49.347942 [0x00000054660000, 0x00000080000000)
5596 23:45:49.439072
5597 23:45:49.439213 [0x000000811994a0, 0x000000ffeda000)
5598 23:45:49.698780
5599 23:45:49.698933 [0x00000100000000, 0x00000140000000)
5600 23:45:49.831645
5601 23:45:49.834353 Initializing XHCI USB controller at 0x11200000.
5602 23:45:49.857646
5603 23:45:49.860934 [firmware-jacuzzi-12573.B-collabora] Jun 8 2022 08:18:54
5604 23:45:49.861026
5605 23:45:49.861097
5606 23:45:49.861424 Setting prompt string to ['jacuzzi:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5608 23:45:49.961780 jacuzzi: tftpboot 192.168.201.1 14172940/tftp-deploy-j2ocngpm/kernel/image.itb 14172940/tftp-deploy-j2ocngpm/kernel/cmdline
5609 23:45:49.961940 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5610 23:45:49.962051 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:26)
5611 23:45:49.966525 tftpboot 192.168.201.1 14172940/tftp-deploy-j2ocngpm/kernel/image.itbtp-deploy-j2ocngpm/kernel/cmdline
5612 23:45:49.966648
5613 23:45:49.966752 Waiting for link
5614 23:45:50.371464
5615 23:45:50.371681 R8152: Initializing
5616 23:45:50.371812
5617 23:45:50.374914 Version 9 (ocp_data = 6010)
5618 23:45:50.375102
5619 23:45:50.377698 R8152: Done initializing
5620 23:45:50.377885
5621 23:45:50.378033 Adding net device
5622 23:45:50.763648
5623 23:45:50.763804 done.
5624 23:45:50.763878
5625 23:45:50.763944 MAC: 00:e0:4c:68:0b:b9
5626 23:45:50.764008
5627 23:45:50.766847 Sending DHCP discover... done.
5628 23:45:50.766958
5629 23:45:50.770062 Waiting for reply... done.
5630 23:45:50.770179
5631 23:45:50.773854 Sending DHCP request... done.
5632 23:45:50.773969
5633 23:45:50.774043 Waiting for reply... done.
5634 23:45:50.774109
5635 23:45:50.776878 My ip is 192.168.201.13
5636 23:45:50.776971
5637 23:45:50.780401 The DHCP server ip is 192.168.201.1
5638 23:45:50.780495
5639 23:45:50.783566 TFTP server IP predefined by user: 192.168.201.1
5640 23:45:50.783668
5641 23:45:50.789874 Bootfile predefined by user: 14172940/tftp-deploy-j2ocngpm/kernel/image.itb
5642 23:45:50.789982
5643 23:45:50.793714 Sending tftp read request... done.
5644 23:45:50.793830
5645 23:45:50.796894 Waiting for the transfer...
5646 23:45:50.797019
5647 23:45:51.079684 00000000 ################################################################
5648 23:45:51.079853
5649 23:45:51.350055 00080000 ################################################################
5650 23:45:51.350203
5651 23:45:51.619739 00100000 ################################################################
5652 23:45:51.619882
5653 23:45:51.872085 00180000 ################################################################
5654 23:45:51.872263
5655 23:45:52.138035 00200000 ################################################################
5656 23:45:52.138178
5657 23:45:52.404835 00280000 ################################################################
5658 23:45:52.404978
5659 23:45:52.687548 00300000 ################################################################
5660 23:45:52.687712
5661 23:45:52.964689 00380000 ################################################################
5662 23:45:52.964852
5663 23:45:53.227755 00400000 ################################################################
5664 23:45:53.227903
5665 23:45:53.500888 00480000 ################################################################
5666 23:45:53.501040
5667 23:45:53.780483 00500000 ################################################################
5668 23:45:53.780638
5669 23:45:54.051810 00580000 ################################################################
5670 23:45:54.051960
5671 23:45:54.324066 00600000 ################################################################
5672 23:45:54.324230
5673 23:45:54.584422 00680000 ################################################################
5674 23:45:54.584580
5675 23:45:54.853903 00700000 ################################################################
5676 23:45:54.854067
5677 23:45:55.136619 00780000 ################################################################
5678 23:45:55.136762
5679 23:45:55.430975 00800000 ################################################################
5680 23:45:55.431190
5681 23:45:55.729330 00880000 ################################################################
5682 23:45:55.729516
5683 23:45:56.018551 00900000 ################################################################
5684 23:45:56.018708
5685 23:45:56.318819 00980000 ################################################################
5686 23:45:56.318977
5687 23:45:56.618636 00a00000 ################################################################
5688 23:45:56.618794
5689 23:45:56.918690 00a80000 ################################################################
5690 23:45:56.918842
5691 23:45:57.192885 00b00000 ################################################################
5692 23:45:57.193028
5693 23:45:57.488278 00b80000 ################################################################
5694 23:45:57.488424
5695 23:45:57.782776 00c00000 ################################################################
5696 23:45:57.782933
5697 23:45:58.059845 00c80000 ################################################################
5698 23:45:58.060006
5699 23:45:58.337375 00d00000 ################################################################
5700 23:45:58.337530
5701 23:45:58.634349 00d80000 ################################################################
5702 23:45:58.634529
5703 23:45:58.921850 00e00000 ################################################################
5704 23:45:58.922052
5705 23:45:59.200793 00e80000 ################################################################
5706 23:45:59.200959
5707 23:45:59.490867 00f00000 ################################################################
5708 23:45:59.491028
5709 23:45:59.774677 00f80000 ################################################################
5710 23:45:59.774863
5711 23:46:00.058606 01000000 ################################################################
5712 23:46:00.058757
5713 23:46:00.339953 01080000 ################################################################
5714 23:46:00.340098
5715 23:46:00.612051 01100000 ################################################################
5716 23:46:00.612209
5717 23:46:00.867774 01180000 ################################################################
5718 23:46:00.867931
5719 23:46:01.125598 01200000 ################################################################
5720 23:46:01.125758
5721 23:46:01.388834 01280000 ################################################################
5722 23:46:01.389054
5723 23:46:01.665473 01300000 ################################################################
5724 23:46:01.665694
5725 23:46:01.956725 01380000 ################################################################
5726 23:46:01.956944
5727 23:46:02.242268 01400000 ################################################################
5728 23:46:02.242429
5729 23:46:02.539367 01480000 ################################################################
5730 23:46:02.539537
5731 23:46:02.844725 01500000 ################################################################
5732 23:46:02.844913
5733 23:46:03.142468 01580000 ################################################################
5734 23:46:03.142654
5735 23:46:03.423654 01600000 ################################################################
5736 23:46:03.423904
5737 23:46:03.716161 01680000 ################################################################
5738 23:46:03.716319
5739 23:46:04.012713 01700000 ################################################################
5740 23:46:04.012874
5741 23:46:04.301009 01780000 ################################################################
5742 23:46:04.301155
5743 23:46:04.637512 01800000 ################################################################
5744 23:46:04.637928
5745 23:46:04.940474 01880000 ################################################################
5746 23:46:04.940627
5747 23:46:05.199479 01900000 ################################################################
5748 23:46:05.199694
5749 23:46:05.451319 01980000 ################################################################
5750 23:46:05.451486
5751 23:46:05.711696 01a00000 ################################################################
5752 23:46:05.711853
5753 23:46:05.971799 01a80000 ################################################################
5754 23:46:05.972009
5755 23:46:06.252724 01b00000 ################################################################
5756 23:46:06.252881
5757 23:46:06.542958 01b80000 ################################################################
5758 23:46:06.543137
5759 23:46:06.842569 01c00000 ################################################################
5760 23:46:06.842731
5761 23:46:07.139693 01c80000 ################################################################
5762 23:46:07.139850
5763 23:46:07.424109 01d00000 ################################################################
5764 23:46:07.424263
5765 23:46:07.724412 01d80000 ################################################################
5766 23:46:07.724560
5767 23:46:07.948024 01e00000 ################################################ done.
5768 23:46:07.948173
5769 23:46:07.951574 The bootfile was 31849842 bytes long.
5770 23:46:07.951668
5771 23:46:07.954809 Sending tftp read request... done.
5772 23:46:07.954911
5773 23:46:07.954982 Waiting for the transfer...
5774 23:46:07.955048
5775 23:46:07.957690 00000000 # done.
5776 23:46:07.957783
5777 23:46:07.964548 Command line loaded dynamically from TFTP file: 14172940/tftp-deploy-j2ocngpm/kernel/cmdline
5778 23:46:07.964640
5779 23:46:07.991577 The command line is: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172940/extract-nfsrootfs-kqrq6156,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5780 23:46:07.991676
5781 23:46:07.991747 Loading FIT.
5782 23:46:07.991814
5783 23:46:07.994737 Image ramdisk-1 has 18728667 bytes.
5784 23:46:07.994828
5785 23:46:07.997858 Image fdt-1 has 57695 bytes.
5786 23:46:07.997949
5787 23:46:08.001170 Image kernel-1 has 13061430 bytes.
5788 23:46:08.001260
5789 23:46:08.011156 Compat preference: google,juniper-rev4-sku16 google,juniper-sku16 google,juniper-rev4 google,juniper
5790 23:46:08.011248
5791 23:46:08.020835 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,juniper-sku16 (match) google,juniper mediatek,mt8183
5792 23:46:08.020928
5793 23:46:08.027779 Choosing best match conf-1 for compat google,juniper-sku16.
5794 23:46:08.031750
5795 23:46:08.069518 Connected to device vid:did:rid of 1ae0:0028:00
5796 23:46:08.079939
5797 23:46:08.083297 tpm_get_response: command 0x17b, return code 0x0
5798 23:46:08.083388
5799 23:46:08.086790 tpm_cleanup: add release locality here.
5800 23:46:08.086884
5801 23:46:08.090197 Shutting down all USB controllers.
5802 23:46:08.090288
5803 23:46:08.093490 Removing current net device
5804 23:46:08.093580
5805 23:46:08.096914 Exiting depthcharge with code 4 at timestamp: 36059446
5806 23:46:08.097005
5807 23:46:08.100064 LZMA decompressing kernel-1 to 0x80193568
5808 23:46:08.100155
5809 23:46:08.106784 LZMA decompressing kernel-1 to 0x40000000
5810 23:46:09.962117
5811 23:46:09.962273 jumping to kernel
5812 23:46:09.962753 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
5813 23:46:09.962859 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
5814 23:46:09.962941 Setting prompt string to ['Linux version [0-9]']
5815 23:46:09.963016 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
5816 23:46:09.963089 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
5817 23:46:10.037341
5818 23:46:10.040640 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]
5819 23:46:10.044540 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
5820 23:46:10.044644 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
5821 23:46:10.044724 Setting prompt string to []
5822 23:46:10.044841 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
5823 23:46:10.044921 Using line separator: #'\n'#
5824 23:46:10.044986 No login prompt set.
5825 23:46:10.045052 Parsing kernel messages
5826 23:46:10.045112 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
5827 23:46:10.045221 [login-action] Waiting for messages, (timeout 00:04:06)
5828 23:46:10.045293 Waiting using forced prompt support (timeout 00:02:03)
5829 23:46:10.063949 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j217067-arm64-gcc-10-defconfig-arm64-chromebook-s48tj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024
5830 23:46:10.067514 [ 0.000000] random: crng init done
5831 23:46:10.074163 [ 0.000000] Machine model: Google juniper sku16 board
5832 23:46:10.077745 [ 0.000000] efi: UEFI not found.
5833 23:46:10.084186 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
5834 23:46:10.090729 [ 0.000000] OF: reserved mem: initialized node memory@50000000, compatible id shared-dma-pool
5835 23:46:10.100543 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
5836 23:46:10.104019 [ 0.000000] printk: bootconsole [mtk8250] enabled
5837 23:46:10.112146 [ 0.000000] NUMA: No NUMA configuration found
5838 23:46:10.119164 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
5839 23:46:10.125554 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7bea00-0x13f7c0fff]
5840 23:46:10.125647 [ 0.000000] Zone ranges:
5841 23:46:10.132376 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
5842 23:46:10.135635 [ 0.000000] DMA32 empty
5843 23:46:10.142302 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
5844 23:46:10.145499 [ 0.000000] Movable zone start for each node
5845 23:46:10.148554 [ 0.000000] Early memory node ranges
5846 23:46:10.155307 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
5847 23:46:10.161876 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
5848 23:46:10.168831 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
5849 23:46:10.175313 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
5850 23:46:10.182198 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
5851 23:46:10.188375 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
5852 23:46:10.205011 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
5853 23:46:10.211365 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
5854 23:46:10.217936 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
5855 23:46:10.221322 [ 0.000000] psci: probing for conduit method from DT.
5856 23:46:10.228131 [ 0.000000] psci: PSCIv1.1 detected in firmware.
5857 23:46:10.231712 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
5858 23:46:10.237628 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
5859 23:46:10.241193 [ 0.000000] psci: SMC Calling Convention v1.1
5860 23:46:10.247677 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
5861 23:46:10.251398 [ 0.000000] Detected VIPT I-cache on CPU0
5862 23:46:10.257855 [ 0.000000] CPU features: detected: GIC system register CPU interface
5863 23:46:10.264108 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
5864 23:46:10.270623 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
5865 23:46:10.277335 [ 0.000000] CPU features: detected: ARM erratum 845719
5866 23:46:10.280908 [ 0.000000] alternatives: applying boot alternatives
5867 23:46:10.284015 [ 0.000000] Fallback order for Node 0: 0
5868 23:46:10.290653 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
5869 23:46:10.293981 [ 0.000000] Policy zone: Normal
5870 23:46:10.320639 [ 0.000000] Kernel command line: earlyprintk=ttyS0,115200n8 console=tty1 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172940/extract-nfsrootfs-kqrq6156,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
5871 23:46:10.334279 <5>[ 0.000000] Unknown kernel command line parameters "earlyprintk=ttyS0,115200n8 tftpserverip=192.168.201.1", will be passed to user space.
5872 23:46:10.344109 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
5873 23:46:10.350987 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
5874 23:46:10.357440 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
5875 23:46:10.363695 <6>[ 0.000000] software IO TLB: area num 8.
5876 23:46:10.387898 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
5877 23:46:10.446268 <6>[ 0.000000] Memory: 3896912K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 261552K reserved, 32768K cma-reserved)
5878 23:46:10.453036 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
5879 23:46:10.459259 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
5880 23:46:10.462711 <6>[ 0.000000] rcu: RCU event tracing is enabled.
5881 23:46:10.469254 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
5882 23:46:10.475874 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
5883 23:46:10.479167 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
5884 23:46:10.488969 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
5885 23:46:10.495734 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
5886 23:46:10.502347 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
5887 23:46:10.512204 <6>[ 0.000000] GIC: enabling workaround for GICv3: Mediatek Chromebook GICR save problem
5888 23:46:10.515331 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
5889 23:46:10.518913 <6>[ 0.000000] GICv3: 640 SPIs implemented
5890 23:46:10.525348 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
5891 23:46:10.529166 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
5892 23:46:10.535260 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
5893 23:46:10.541966 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c100000
5894 23:46:10.552329 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@1[1] /cpus/cpu@2[2] /cpus/cpu@3[3] }
5895 23:46:10.565461 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@100[4] /cpus/cpu@101[5] /cpus/cpu@102[6] /cpus/cpu@103[7] }
5896 23:46:10.571761 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
5897 23:46:10.583823 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
5898 23:46:10.596234 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
5899 23:46:10.602841 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
5900 23:46:10.609759 <6>[ 0.009465] Console: colour dummy device 80x25
5901 23:46:10.613387 <6>[ 0.014515] printk: console [tty1] enabled
5902 23:46:10.623023 <6>[ 0.018902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
5903 23:46:10.629739 <6>[ 0.029367] pid_max: default: 32768 minimum: 301
5904 23:46:10.634436 <6>[ 0.034250] LSM: Security Framework initializing
5905 23:46:10.643309 <6>[ 0.039164] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5906 23:46:10.650050 <6>[ 0.046788] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
5907 23:46:10.656951 <4>[ 0.055662] cacheinfo: Unable to detect cache hierarchy for CPU 0
5908 23:46:10.666149 <6>[ 0.062289] cblist_init_generic: Setting adjustable number of callback queues.
5909 23:46:10.673206 <6>[ 0.069735] cblist_init_generic: Setting shift to 3 and lim to 1.
5910 23:46:10.679345 <6>[ 0.076089] cblist_init_generic: Setting adjustable number of callback queues.
5911 23:46:10.686142 <6>[ 0.083533] cblist_init_generic: Setting shift to 3 and lim to 1.
5912 23:46:10.689491 <6>[ 0.089930] rcu: Hierarchical SRCU implementation.
5913 23:46:10.695983 <6>[ 0.094956] rcu: Max phase no-delay instances is 1000.
5914 23:46:10.703785 <6>[ 0.102883] EFI services will not be available.
5915 23:46:10.706735 <6>[ 0.107832] smp: Bringing up secondary CPUs ...
5916 23:46:10.717315 <6>[ 0.113145] Detected VIPT I-cache on CPU1
5917 23:46:10.723628 <4>[ 0.113191] cacheinfo: Unable to detect cache hierarchy for CPU 1
5918 23:46:10.730562 <6>[ 0.113200] GICv3: CPU1: found redistributor 1 region 0:0x000000000c120000
5919 23:46:10.737055 <6>[ 0.113232] CPU1: Booted secondary processor 0x0000000001 [0x410fd034]
5920 23:46:10.740368 <6>[ 0.113716] Detected VIPT I-cache on CPU2
5921 23:46:10.747296 <4>[ 0.113749] cacheinfo: Unable to detect cache hierarchy for CPU 2
5922 23:46:10.753838 <6>[ 0.113754] GICv3: CPU2: found redistributor 2 region 0:0x000000000c140000
5923 23:46:10.760500 <6>[ 0.113767] CPU2: Booted secondary processor 0x0000000002 [0x410fd034]
5924 23:46:10.763895 <6>[ 0.114211] Detected VIPT I-cache on CPU3
5925 23:46:10.770231 <4>[ 0.114241] cacheinfo: Unable to detect cache hierarchy for CPU 3
5926 23:46:10.777036 <6>[ 0.114245] GICv3: CPU3: found redistributor 3 region 0:0x000000000c160000
5927 23:46:10.787035 <6>[ 0.114256] CPU3: Booted secondary processor 0x0000000003 [0x410fd034]
5928 23:46:10.790544 <6>[ 0.114831] CPU features: detected: Spectre-v2
5929 23:46:10.793693 <6>[ 0.114841] CPU features: detected: Spectre-BHB
5930 23:46:10.800339 <6>[ 0.114845] CPU features: detected: ARM erratum 858921
5931 23:46:10.803392 <6>[ 0.114850] Detected VIPT I-cache on CPU4
5932 23:46:10.810083 <4>[ 0.114898] cacheinfo: Unable to detect cache hierarchy for CPU 4
5933 23:46:10.816891 <6>[ 0.114906] GICv3: CPU4: found redistributor 100 region 0:0x000000000c180000
5934 23:46:10.823518 <6>[ 0.114914] arch_timer: Enabling local workaround for ARM erratum 858921
5935 23:46:10.830197 <6>[ 0.114924] arch_timer: CPU4: Trapping CNTVCT access
5936 23:46:10.836690 <6>[ 0.114932] CPU4: Booted secondary processor 0x0000000100 [0x410fd092]
5937 23:46:10.840257 <6>[ 0.115418] Detected VIPT I-cache on CPU5
5938 23:46:10.846828 <4>[ 0.115459] cacheinfo: Unable to detect cache hierarchy for CPU 5
5939 23:46:10.853253 <6>[ 0.115465] GICv3: CPU5: found redistributor 101 region 0:0x000000000c1a0000
5940 23:46:10.859992 <6>[ 0.115472] arch_timer: Enabling local workaround for ARM erratum 858921
5941 23:46:10.866571 <6>[ 0.115478] arch_timer: CPU5: Trapping CNTVCT access
5942 23:46:10.873159 <6>[ 0.115483] CPU5: Booted secondary processor 0x0000000101 [0x410fd092]
5943 23:46:10.876406 <6>[ 0.116018] Detected VIPT I-cache on CPU6
5944 23:46:10.883258 <4>[ 0.116064] cacheinfo: Unable to detect cache hierarchy for CPU 6
5945 23:46:10.889905 <6>[ 0.116070] GICv3: CPU6: found redistributor 102 region 0:0x000000000c1c0000
5946 23:46:10.899523 <6>[ 0.116077] arch_timer: Enabling local workaround for ARM erratum 858921
5947 23:46:10.902922 <6>[ 0.116084] arch_timer: CPU6: Trapping CNTVCT access
5948 23:46:10.909827 <6>[ 0.116089] CPU6: Booted secondary processor 0x0000000102 [0x410fd092]
5949 23:46:10.912997 <6>[ 0.116618] Detected VIPT I-cache on CPU7
5950 23:46:10.919232 <4>[ 0.116661] cacheinfo: Unable to detect cache hierarchy for CPU 7
5951 23:46:10.929537 <6>[ 0.116667] GICv3: CPU7: found redistributor 103 region 0:0x000000000c1e0000
5952 23:46:10.936206 <6>[ 0.116674] arch_timer: Enabling local workaround for ARM erratum 858921
5953 23:46:10.939303 <6>[ 0.116681] arch_timer: CPU7: Trapping CNTVCT access
5954 23:46:10.945952 <6>[ 0.116686] CPU7: Booted secondary processor 0x0000000103 [0x410fd092]
5955 23:46:10.949253 <6>[ 0.116734] smp: Brought up 1 node, 8 CPUs
5956 23:46:10.956019 <6>[ 0.355602] SMP: Total of 8 processors activated.
5957 23:46:10.962506 <6>[ 0.360538] CPU features: detected: 32-bit EL0 Support
5958 23:46:10.965967 <6>[ 0.365909] CPU features: detected: 32-bit EL1 Support
5959 23:46:10.972656 <6>[ 0.371275] CPU features: detected: CRC32 instructions
5960 23:46:10.975978 <6>[ 0.376702] CPU: All CPU(s) started at EL2
5961 23:46:10.982707 <6>[ 0.381040] alternatives: applying system-wide alternatives
5962 23:46:10.989622 <6>[ 0.389029] devtmpfs: initialized
5963 23:46:11.001698 <6>[ 0.397993] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
5964 23:46:11.011794 <6>[ 0.407943] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
5965 23:46:11.015230 <6>[ 0.415673] pinctrl core: initialized pinctrl subsystem
5966 23:46:11.023372 <6>[ 0.422777] DMI not present or invalid.
5967 23:46:11.030274 <6>[ 0.427145] NET: Registered PF_NETLINK/PF_ROUTE protocol family
5968 23:46:11.036772 <6>[ 0.434043] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
5969 23:46:11.046728 <6>[ 0.441555] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
5970 23:46:11.053147 <6>[ 0.449726] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
5971 23:46:11.059955 <6>[ 0.457871] audit: initializing netlink subsys (disabled)
5972 23:46:11.066251 <5>[ 0.463553] audit: type=2000 audit(0.332:1): state=initialized audit_enabled=0 res=1
5973 23:46:11.072955 <6>[ 0.464513] thermal_sys: Registered thermal governor 'step_wise'
5974 23:46:11.079619 <6>[ 0.471505] thermal_sys: Registered thermal governor 'power_allocator'
5975 23:46:11.082951 <6>[ 0.477754] cpuidle: using governor menu
5976 23:46:11.089513 <6>[ 0.488702] NET: Registered PF_QIPCRTR protocol family
5977 23:46:11.096426 <6>[ 0.494189] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
5978 23:46:11.102997 <6>[ 0.501284] ASID allocator initialised with 32768 entries
5979 23:46:11.109025 <6>[ 0.508055] Serial: AMBA PL011 UART driver
5980 23:46:11.118968 <4>[ 0.518438] Trying to register duplicate clock ID: 113
5981 23:46:11.177505 <6>[ 0.573713] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5982 23:46:11.191929 <6>[ 0.588037] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
5983 23:46:11.195194 <6>[ 0.597780] KASLR enabled
5984 23:46:11.209806 <6>[ 0.605794] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
5985 23:46:11.216317 <6>[ 0.612799] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
5986 23:46:11.222562 <6>[ 0.619278] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
5987 23:46:11.229816 <6>[ 0.626269] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
5988 23:46:11.236157 <6>[ 0.632743] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
5989 23:46:11.242994 <6>[ 0.639734] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
5990 23:46:11.249634 <6>[ 0.646207] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
5991 23:46:11.255993 <6>[ 0.653197] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
5992 23:46:11.259152 <6>[ 0.660759] ACPI: Interpreter disabled.
5993 23:46:11.269423 <6>[ 0.668701] iommu: Default domain type: Translated
5994 23:46:11.275844 <6>[ 0.673811] iommu: DMA domain TLB invalidation policy: strict mode
5995 23:46:11.279305 <5>[ 0.680446] SCSI subsystem initialized
5996 23:46:11.286113 <6>[ 0.684868] usbcore: registered new interface driver usbfs
5997 23:46:11.292322 <6>[ 0.690596] usbcore: registered new interface driver hub
5998 23:46:11.295768 <6>[ 0.696139] usbcore: registered new device driver usb
5999 23:46:11.303003 <6>[ 0.702429] pps_core: LinuxPPS API ver. 1 registered
6000 23:46:11.313072 <6>[ 0.707614] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
6001 23:46:11.316162 <6>[ 0.716939] PTP clock support registered
6002 23:46:11.319232 <6>[ 0.721194] EDAC MC: Ver: 3.0.0
6003 23:46:11.327713 <6>[ 0.726814] FPGA manager framework
6004 23:46:11.333950 <6>[ 0.730498] Advanced Linux Sound Architecture Driver Initialized.
6005 23:46:11.337237 <6>[ 0.737248] vgaarb: loaded
6006 23:46:11.343806 <6>[ 0.740374] clocksource: Switched to clocksource arch_sys_counter
6007 23:46:11.347074 <5>[ 0.746804] VFS: Disk quotas dquot_6.6.0
6008 23:46:11.353524 <6>[ 0.750980] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
6009 23:46:11.356793 <6>[ 0.758153] pnp: PnP ACPI: disabled
6010 23:46:11.365390 <6>[ 0.765012] NET: Registered PF_INET protocol family
6011 23:46:11.372221 <6>[ 0.770245] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
6012 23:46:11.383669 <6>[ 0.780157] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
6013 23:46:11.394189 <6>[ 0.788910] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
6014 23:46:11.400370 <6>[ 0.796861] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
6015 23:46:11.407284 <6>[ 0.805092] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
6016 23:46:11.413922 <6>[ 0.813187] TCP: Hash tables configured (established 32768 bind 32768)
6017 23:46:11.423622 <6>[ 0.820015] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
6018 23:46:11.430250 <6>[ 0.826988] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
6019 23:46:11.436794 <6>[ 0.834469] NET: Registered PF_UNIX/PF_LOCAL protocol family
6020 23:46:11.443522 <6>[ 0.840603] RPC: Registered named UNIX socket transport module.
6021 23:46:11.446848 <6>[ 0.846749] RPC: Registered udp transport module.
6022 23:46:11.453489 <6>[ 0.851673] RPC: Registered tcp transport module.
6023 23:46:11.459890 <6>[ 0.856596] RPC: Registered tcp NFSv4.1 backchannel transport module.
6024 23:46:11.463357 <6>[ 0.863251] PCI: CLS 0 bytes, default 64
6025 23:46:11.466670 <6>[ 0.867539] Unpacking initramfs...
6026 23:46:11.488831 <6>[ 0.884956] hw perfevents: enabled with armv8_cortex_a53 PMU driver, 7 counters available
6027 23:46:11.498691 <6>[ 0.893579] hw perfevents: enabled with armv8_cortex_a73 PMU driver, 7 counters available
6028 23:46:11.502020 <6>[ 0.902425] kvm [1]: IPA Size Limit: 40 bits
6029 23:46:11.509478 <6>[ 0.908734] kvm [1]: vgic-v2@c420000
6030 23:46:11.512219 <6>[ 0.912550] kvm [1]: GIC system register CPU interface enabled
6031 23:46:11.519088 <6>[ 0.918710] kvm [1]: vgic interrupt IRQ18
6032 23:46:11.522533 <6>[ 0.923058] kvm [1]: Hyp mode initialized successfully
6033 23:46:11.529623 <5>[ 0.929377] Initialise system trusted keyrings
6034 23:46:11.536227 <6>[ 0.934224] workingset: timestamp_bits=42 max_order=20 bucket_order=0
6035 23:46:11.544528 <6>[ 0.944178] squashfs: version 4.0 (2009/01/31) Phillip Lougher
6036 23:46:11.551140 <5>[ 0.950604] NFS: Registering the id_resolver key type
6037 23:46:11.554690 <5>[ 0.955913] Key type id_resolver registered
6038 23:46:11.561134 <5>[ 0.960327] Key type id_legacy registered
6039 23:46:11.567741 <6>[ 0.964638] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
6040 23:46:11.574569 <6>[ 0.971558] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
6041 23:46:11.581234 <6>[ 0.979313] 9p: Installing v9fs 9p2000 file system support
6042 23:46:11.609479 <5>[ 1.009131] Key type asymmetric registered
6043 23:46:11.612813 <5>[ 1.013476] Asymmetric key parser 'x509' registered
6044 23:46:11.623185 <6>[ 1.018631] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
6045 23:46:11.626462 <6>[ 1.026244] io scheduler mq-deadline registered
6046 23:46:11.629248 <6>[ 1.030999] io scheduler kyber registered
6047 23:46:11.652262 <6>[ 1.051723] EINJ: ACPI disabled.
6048 23:46:11.658728 <4>[ 1.055484] of_fixed_factor_clk: probe of fixed-factor-clock-13m failed with error -17
6049 23:46:11.696359 <6>[ 1.096023] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
6050 23:46:11.705187 <6>[ 1.104542] printk: console [ttyS0] disabled
6051 23:46:11.733046 <6>[ 1.129190] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 242, base_baud = 1625000) is a ST16650V2
6052 23:46:11.739994 <6>[ 1.138664] printk: console [ttyS0] enabled
6053 23:46:11.743022 <6>[ 1.138664] printk: console [ttyS0] enabled
6054 23:46:11.749836 <6>[ 1.147584] printk: bootconsole [mtk8250] disabled
6055 23:46:11.752635 <6>[ 1.147584] printk: bootconsole [mtk8250] disabled
6056 23:46:11.762626 <3>[ 1.158111] mt8183-pinctrl 10005000.pinctrl: pin_config_group_set op failed for group 47
6057 23:46:11.769327 <3>[ 1.166492] mt6577-uart 11003000.serial: Error applying setting, reverse things back
6058 23:46:11.798796 <6>[ 1.194901] 11003000.serial: ttyS1 at MMIO 0x11003000 (irq = 243, base_baud = 1625000) is a ST16650V2
6059 23:46:11.805114 <6>[ 1.204558] serial serial0: tty port ttyS1 registered
6060 23:46:11.811624 <6>[ 1.211140] SuperH (H)SCI(F) driver initialized
6061 23:46:11.815089 <6>[ 1.216649] msm_serial: driver initialized
6062 23:46:11.830831 <6>[ 1.226914] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14008000
6063 23:46:11.840517 <6>[ 1.235514] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14009000
6064 23:46:11.847200 <6>[ 1.244090] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@1400a000
6065 23:46:11.857132 <6>[ 1.252667] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400b000
6066 23:46:11.864084 <6>[ 1.261327] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@1400c000
6067 23:46:11.873826 <6>[ 1.269994] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@1400e000
6068 23:46:11.883933 <6>[ 1.278737] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400f000
6069 23:46:11.890736 <6>[ 1.287478] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@14010000
6070 23:46:11.900666 <6>[ 1.296046] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@14011000
6071 23:46:11.910229 <6>[ 1.304853] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/dsi@14014000
6072 23:46:11.917520 <4>[ 1.317269] cacheinfo: Unable to detect cache hierarchy for CPU 0
6073 23:46:11.926864 <6>[ 1.326711] loop: module loaded
6074 23:46:11.939142 <6>[ 1.338619] vsim1: Bringing 1800000uV into 2700000-2700000uV
6075 23:46:11.957641 <6>[ 1.356714] megasas: 07.719.03.00-rc1
6076 23:46:11.965760 <6>[ 1.365560] spi-nor spi1.0: w25q64dw (8192 Kbytes)
6077 23:46:11.980561 <6>[ 1.379756] tpm_tis_spi spi0.0: TPM ready IRQ confirmed on attempt 2
6078 23:46:11.997218 <6>[ 1.396509] tpm_tis_spi spi0.0: 2.0 TPM (device-id 0x28, rev-id 0)
6079 23:46:12.053993 <6>[ 1.446674] tpm_tis_spi spi0.0: Cr50 firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1d
6080 23:46:12.077783 <6>[ 1.477459] Freeing initrd memory: 18284K
6081 23:46:12.093623 <4>[ 1.489248] sysfs: cannot create duplicate filename '/bus/platform/devices/fixed-factor-clock-13m'
6082 23:46:12.099549 <4>[ 1.498485] CPU: 6 PID: 1 Comm: swapper/0 Not tainted 6.1.92-cip22 #1
6083 23:46:12.106765 <4>[ 1.505183] Hardware name: Google juniper sku16 board (DT)
6084 23:46:12.110339 <4>[ 1.510922] Call trace:
6085 23:46:12.113367 <4>[ 1.513623] dump_backtrace.part.0+0xe0/0xf0
6086 23:46:12.116686 <4>[ 1.518159] show_stack+0x18/0x30
6087 23:46:12.119938 <4>[ 1.521731] dump_stack_lvl+0x68/0x84
6088 23:46:12.122911 <4>[ 1.525653] dump_stack+0x18/0x34
6089 23:46:12.129695 <4>[ 1.529223] sysfs_warn_dup+0x64/0x80
6090 23:46:12.133015 <4>[ 1.533145] sysfs_do_create_link_sd+0xf0/0x100
6091 23:46:12.136496 <4>[ 1.537932] sysfs_create_link+0x20/0x40
6092 23:46:12.143218 <4>[ 1.542111] bus_add_device+0x68/0x10c
6093 23:46:12.146692 <4>[ 1.546117] device_add+0x340/0x7ac
6094 23:46:12.149881 <4>[ 1.549860] of_device_add+0x44/0x60
6095 23:46:12.152936 <4>[ 1.553694] of_platform_device_create_pdata+0x90/0x120
6096 23:46:12.160087 <4>[ 1.559176] of_platform_bus_create+0x170/0x370
6097 23:46:12.163354 <4>[ 1.563962] of_platform_populate+0x50/0xfc
6098 23:46:12.169527 <4>[ 1.568402] parse_mtd_partitions+0x1dc/0x510
6099 23:46:12.173116 <4>[ 1.573016] mtd_device_parse_register+0xf8/0x2e0
6100 23:46:12.176224 <4>[ 1.577974] spi_nor_probe+0x21c/0x2f0
6101 23:46:12.179400 <4>[ 1.581980] spi_mem_probe+0x6c/0xb0
6102 23:46:12.186273 <4>[ 1.585812] spi_probe+0x84/0xe4
6103 23:46:12.189712 <4>[ 1.589294] really_probe+0xbc/0x2e0
6104 23:46:12.192686 <4>[ 1.593124] __driver_probe_device+0x78/0x11c
6105 23:46:12.196342 <4>[ 1.597736] driver_probe_device+0xd8/0x160
6106 23:46:12.202933 <4>[ 1.602174] __device_attach_driver+0xb8/0x134
6107 23:46:12.206543 <4>[ 1.606873] bus_for_each_drv+0x78/0xd0
6108 23:46:12.209407 <4>[ 1.610963] __device_attach+0xa8/0x1c0
6109 23:46:12.215877 <4>[ 1.615053] device_initial_probe+0x14/0x20
6110 23:46:12.219593 <4>[ 1.619491] bus_probe_device+0x9c/0xa4
6111 23:46:12.222653 <4>[ 1.623582] device_add+0x3ac/0x7ac
6112 23:46:12.226209 <4>[ 1.627324] __spi_add_device+0x78/0x120
6113 23:46:12.229396 <4>[ 1.631502] spi_add_device+0x40/0x7c
6114 23:46:12.236034 <4>[ 1.635420] spi_register_controller+0x610/0xad0
6115 23:46:12.239511 <4>[ 1.640292] devm_spi_register_controller+0x4c/0xa4
6116 23:46:12.246153 <4>[ 1.645425] mtk_spi_probe+0x3f8/0x650
6117 23:46:12.249910 <4>[ 1.649430] platform_probe+0x68/0xe0
6118 23:46:12.253287 <4>[ 1.653348] really_probe+0xbc/0x2e0
6119 23:46:12.256494 <4>[ 1.657179] __driver_probe_device+0x78/0x11c
6120 23:46:12.262991 <4>[ 1.661790] driver_probe_device+0xd8/0x160
6121 23:46:12.266445 <4>[ 1.666228] __driver_attach+0x94/0x19c
6122 23:46:12.270011 <4>[ 1.670318] bus_for_each_dev+0x70/0xd0
6123 23:46:12.272978 <4>[ 1.674408] driver_attach+0x24/0x30
6124 23:46:12.276174 <4>[ 1.678238] bus_add_driver+0x154/0x20c
6125 23:46:12.283196 <4>[ 1.682328] driver_register+0x78/0x130
6126 23:46:12.286611 <4>[ 1.686419] __platform_driver_register+0x28/0x34
6127 23:46:12.290004 <4>[ 1.691378] mtk_spi_driver_init+0x1c/0x28
6128 23:46:12.296419 <4>[ 1.695732] do_one_initcall+0x50/0x1d0
6129 23:46:12.299667 <4>[ 1.699823] kernel_init_freeable+0x21c/0x288
6130 23:46:12.303525 <4>[ 1.704436] kernel_init+0x24/0x12c
6131 23:46:12.306010 <4>[ 1.708181] ret_from_fork+0x10/0x20
6132 23:46:12.317442 <6>[ 1.717081] tun: Universal TUN/TAP device driver, 1.6
6133 23:46:12.321392 <6>[ 1.723361] thunder_xcv, ver 1.0
6134 23:46:12.324163 <6>[ 1.726874] thunder_bgx, ver 1.0
6135 23:46:12.327559 <6>[ 1.730375] nicpf, ver 1.0
6136 23:46:12.338344 <6>[ 1.734724] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
6137 23:46:12.342171 <6>[ 1.742208] hns3: Copyright (c) 2017 Huawei Corporation.
6138 23:46:12.345621 <6>[ 1.747806] hclge is initializing
6139 23:46:12.351806 <6>[ 1.751396] e1000: Intel(R) PRO/1000 Network Driver
6140 23:46:12.358634 <6>[ 1.756531] e1000: Copyright (c) 1999-2006 Intel Corporation.
6141 23:46:12.361705 <6>[ 1.762552] e1000e: Intel(R) PRO/1000 Network Driver
6142 23:46:12.368552 <6>[ 1.767773] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
6143 23:46:12.375142 <6>[ 1.773968] igb: Intel(R) Gigabit Ethernet Network Driver
6144 23:46:12.382217 <6>[ 1.779623] igb: Copyright (c) 2007-2014 Intel Corporation.
6145 23:46:12.388306 <6>[ 1.785466] igbvf: Intel(R) Gigabit Virtual Function Network Driver
6146 23:46:12.394945 <6>[ 1.791988] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
6147 23:46:12.398403 <6>[ 1.798534] sky2: driver version 1.30
6148 23:46:12.404743 <6>[ 1.803766] usbcore: registered new device driver r8152-cfgselector
6149 23:46:12.411842 <6>[ 1.810308] usbcore: registered new interface driver r8152
6150 23:46:12.418689 <6>[ 1.816139] VFIO - User Level meta-driver version: 0.3
6151 23:46:12.425080 <6>[ 1.823918] mtu3 11201000.usb: uwk - reg:0x420, version:101
6152 23:46:12.432316 <4>[ 1.829793] mtu3 11201000.usb: supply vbus not found, using dummy regulator
6153 23:46:12.437960 <6>[ 1.837065] mtu3 11201000.usb: dr_mode: 1, drd: auto
6154 23:46:12.444613 <6>[ 1.842290] mtu3 11201000.usb: u2p_dis_msk: 0, u3p_dis_msk: 0
6155 23:46:12.448249 <6>[ 1.848477] mtu3 11201000.usb: usb3-drd: 0
6156 23:46:12.457863 <6>[ 1.854019] mtu3 11201000.usb: xHCI platform device register success...
6157 23:46:12.464569 <4>[ 1.862627] xhci-mtk 11200000.usb: supply vbus not found, using dummy regulator
6158 23:46:12.471530 <6>[ 1.870574] xhci-mtk 11200000.usb: xHCI Host Controller
6159 23:46:12.477841 <6>[ 1.876083] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
6160 23:46:12.484941 <6>[ 1.883805] xhci-mtk 11200000.usb: USB3 root hub has no ports
6161 23:46:12.494967 <6>[ 1.889835] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
6162 23:46:12.501456 <6>[ 1.899257] xhci-mtk 11200000.usb: irq 253, io mem 0x11200000
6163 23:46:12.504934 <6>[ 1.905328] xhci-mtk 11200000.usb: xHCI Host Controller
6164 23:46:12.514957 <6>[ 1.910815] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
6165 23:46:12.521546 <6>[ 1.918473] xhci-mtk 11200000.usb: Host supports USB 3.0 SuperSpeed
6166 23:46:12.524958 <6>[ 1.925286] hub 1-0:1.0: USB hub found
6167 23:46:12.528483 <6>[ 1.929315] hub 1-0:1.0: 1 port detected
6168 23:46:12.538890 <6>[ 1.934669] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
6169 23:46:12.542091 <6>[ 1.943285] hub 2-0:1.0: USB hub found
6170 23:46:12.548789 <3>[ 1.947310] hub 2-0:1.0: config failed, hub doesn't have any ports! (err -19)
6171 23:46:12.555427 <6>[ 1.955194] usbcore: registered new interface driver usb-storage
6172 23:46:12.562391 <6>[ 1.961789] usbcore: registered new device driver onboard-usb-hub
6173 23:46:12.580140 <4>[ 1.976485] onboard-usb-hub 11200000.usb:hub@1: supply vdd not found, using dummy regulator
6174 23:46:12.589457 <6>[ 1.988697] mt6397-rtc mt6358-rtc: registered as rtc0
6175 23:46:12.599397 <6>[ 1.994177] mt6397-rtc mt6358-rtc: setting system clock to 2024-06-04T23:45:15 UTC (1717544715)
6176 23:46:12.602790 <6>[ 2.004060] i2c_dev: i2c /dev entries driver
6177 23:46:12.614827 <6>[ 2.010436] platform panel: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6178 23:46:12.624109 <6>[ 2.018819] platform 14014000.dsi: Fixed dependency cycle(s) with /soc/i2c@11008000/anx7625@58
6179 23:46:12.627360 <6>[ 2.027725] i2c 4-0058: Fixed dependency cycle(s) with /panel
6180 23:46:12.637540 <6>[ 2.033798] i2c 4-0058: Fixed dependency cycle(s) with /soc/dsi@14014000
6181 23:46:12.644301 <3>[ 2.041256] anx7625 4-0058: [drm:anx7625_i2c_probe] *ERROR* fail to find dsi host.
6182 23:46:12.661894 <6>[ 2.058357] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
6183 23:46:12.670488 <6>[ 2.069776] cpu cpu0: EM: created perf domain
6184 23:46:12.680357 <6>[ 2.075273] cpufreq: cpufreq_online: CPU4: Running at unlisted initial frequency: 1199999 KHz, changing to: 1248000 KHz
6185 23:46:12.687291 <6>[ 2.086573] cpu cpu4: EM: created perf domain
6186 23:46:12.693853 <6>[ 2.093535] sdhci: Secure Digital Host Controller Interface driver
6187 23:46:12.700597 <6>[ 2.099989] sdhci: Copyright(c) Pierre Ossman
6188 23:46:12.707166 <6>[ 2.105385] Synopsys Designware Multimedia Card Interface Driver
6189 23:46:12.713889 <6>[ 2.105915] mtk-msdc 11240000.mmc: allocated mmc-pwrseq
6190 23:46:12.717297 <6>[ 2.112442] sdhci-pltfm: SDHCI platform and OF driver helper
6191 23:46:12.725592 <6>[ 2.125129] ledtrig-cpu: registered to indicate activity on CPUs
6192 23:46:12.733613 <6>[ 2.132849] usbcore: registered new interface driver usbhid
6193 23:46:12.736581 <6>[ 2.138687] usbhid: USB HID core driver
6194 23:46:12.748013 <6>[ 2.142992] spi_master spi2: will run message pump with realtime priority
6195 23:46:12.751522 <4>[ 2.143212] i2c_hid_of 2-002c: supply vdd not found, using dummy regulator
6196 23:46:12.758705 <4>[ 2.157336] i2c_hid_of 2-002c: supply vddl not found, using dummy regulator
6197 23:46:12.772424 <6>[ 2.164813] input: cros_ec as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input0
6198 23:46:12.790721 <6>[ 2.180281] input: cros_ec_buttons as /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:keyboard-controller/input/input1
6199 23:46:12.797874 <4>[ 2.188081] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6200 23:46:12.804396 <6>[ 2.201804] cros-ec-spi spi2.0: Chrome EC device registered
6201 23:46:12.811058 <4>[ 2.208225] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6202 23:46:12.823547 <4>[ 2.219577] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6203 23:46:12.830032 <4>[ 2.228643] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6204 23:46:12.843516 <6>[ 2.239962] mmc1: new ultra high speed SDR104 SDIO card at address 0001
6205 23:46:12.850486 <6>[ 2.249247] mtk-msdc 11230000.mmc: Final PAD_DS_TUNE: 0x13014
6206 23:46:12.857556 <6>[ 2.257172] mmc0: new HS400 MMC card at address 0001
6207 23:46:12.864484 <6>[ 2.263273] mmcblk0: mmc0:0001 DA4032 29.1 GiB
6208 23:46:12.872834 <6>[ 2.272605] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
6209 23:46:12.882502 <6>[ 2.282056] mmcblk0boot0: mmc0:0001 DA4032 4.00 MiB
6210 23:46:12.889797 <6>[ 2.289111] mmcblk0boot1: mmc0:0001 DA4032 4.00 MiB
6211 23:46:12.896543 <6>[ 2.295778] mmcblk0rpmb: mmc0:0001 DA4032 16.0 MiB, chardev (507:0)
6212 23:46:12.906974 <6>[ 2.302903] mt6358-sound mt6358-sound: mt6358_platform_driver_probe(), dev name mt6358-sound
6213 23:46:12.920210 <6>[ 2.309304] input: hid-over-i2c 06CB:CDB5 Mouse as /devices/platform/soc/11009000.i2c/i2c-2/2-002c/0018:06CB:CDB5.0001/input/input2
6214 23:46:12.930441 <6>[ 2.316929] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6215 23:46:12.939866 <6>[ 2.323892] hid-generic 0018:06CB:CDB5.0001: input: I2C HID v1.00 Mouse [hid-over-i2c 06CB:CDB5] on 2-002c
6216 23:46:12.946797 <6>[ 2.336516] NET: Registered PF_PACKET protocol family
6217 23:46:12.949718 <6>[ 2.349956] 9pnet: Installing 9P2000 support
6218 23:46:12.956516 <6>[ 2.352395] usb 1-1: new high-speed USB device number 2 using xhci-mtk
6219 23:46:12.960052 <5>[ 2.354541] Key type dns_resolver registered
6220 23:46:12.966890 <6>[ 2.366475] registered taskstats version 1
6221 23:46:12.970161 <5>[ 2.370850] Loading compiled-in X.509 certificates
6222 23:46:13.020293 <3>[ 2.416195] anx7625 4-0058: [drm:anx7625_link_bridge] *ERROR* fail to parse DT for panel : -517
6223 23:46:13.047886 <4>[ 2.443807] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: No cache defaults, reading back from HW
6224 23:46:13.061469 <6>[ 2.454430] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 20
6225 23:46:13.071417 <6>[ 2.466589] mt8183_mt6358_ts3a227 mt8183-sound: mt8183_mt6358_ts3a227_max98357_dev_probe Can't find pin state wov -19
6226 23:46:13.084615 <3>[ 2.477816] debugfs: Directory '11220000.audio-controller:mt8183-afe-pcm' with parent 'mt8183_mt6358_ts3a227_max98357' already present!
6227 23:46:13.100320 <3>[ 2.493408] mt8183_mt6358_ts3a227 mt8183-sound: ASoC: driver name too long 'mt8183_mt6358_ts3a227_max98357' -> 'mt8183_mt6358_t'
6228 23:46:13.107042 <3>[ 2.505895] debugfs: File 'Playback' in directory 'dapm' already present!
6229 23:46:13.114169 <6>[ 2.511500] hub 1-1:1.0: USB hub found
6230 23:46:13.120598 <3>[ 2.512941] debugfs: File 'Capture' in directory 'dapm' already present!
6231 23:46:13.123542 <6>[ 2.517306] hub 1-1:1.0: 3 ports detected
6232 23:46:13.133658 <6>[ 2.526298] input: mt8183_mt6358_ts3a227_max98357 Headset Jack as /devices/platform/mt8183-sound/sound/card0/input4
6233 23:46:13.145182 <6>[ 2.541471] mtk-iommu 10205000.iommu: bound 14017000.larb (ops mtk_smi_larb_component_ops)
6234 23:46:13.155112 <6>[ 2.550053] mtk-iommu 10205000.iommu: bound 16010000.larb (ops mtk_smi_larb_component_ops)
6235 23:46:13.162036 <6>[ 2.558723] mtk-iommu 10205000.iommu: bound 1502f000.larb (ops mtk_smi_larb_component_ops)
6236 23:46:13.172174 <6>[ 2.567288] mtk-iommu 10205000.iommu: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
6237 23:46:13.178179 <6>[ 2.575815] mtk-iommu 10205000.iommu: bound 17010000.larb (ops mtk_smi_larb_component_ops)
6238 23:46:13.188346 <6>[ 2.584333] mtk-iommu 10205000.iommu: bound 15021000.larb (ops mtk_smi_larb_component_ops)
6239 23:46:13.198207 <6>[ 2.592852] mtk-iommu 10205000.iommu: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
6240 23:46:13.204678 <6>[ 2.602079] mediatek-disp-ovl 14008000.ovl: Adding to iommu group 0
6241 23:46:13.211283 <6>[ 2.609598] mediatek-disp-ovl 14009000.ovl: Adding to iommu group 0
6242 23:46:13.217788 <6>[ 2.616889] mediatek-disp-ovl 1400a000.ovl: Adding to iommu group 0
6243 23:46:13.228007 <6>[ 2.624130] mediatek-disp-rdma 1400b000.rdma: Adding to iommu group 0
6244 23:46:13.234430 <6>[ 2.631538] mediatek-disp-rdma 1400c000.rdma: Adding to iommu group 0
6245 23:46:13.241187 <6>[ 2.639801] panfrost 13040000.gpu: clock rate = 511999970
6246 23:46:13.251131 <6>[ 2.645494] panfrost 13040000.gpu: [drm:panfrost_devfreq_init] More than 1 supply is not supported yet
6247 23:46:13.257618 <6>[ 2.655754] panfrost 13040000.gpu: mali-g72 id 0x6221 major 0x0 minor 0x3 status 0x0
6248 23:46:13.268227 <6>[ 2.663791] panfrost 13040000.gpu: features: 00000000,000004f7, issues: 00000000,00000400
6249 23:46:13.281057 <6>[ 2.672224] panfrost 13040000.gpu: Features: L2:0x07120206 Shader:0x00000000 Tiler:0x00000809 Mem:0x1 MMU:0x00002830 AS:0xff JS:0x7
6250 23:46:13.287534 <6>[ 2.684303] panfrost 13040000.gpu: shader_present=0x7 l2_present=0x1
6251 23:46:13.298232 <6>[ 2.694234] [drm] Initialized panfrost 1.2.0 20180908 for 13040000.gpu on minor 0
6252 23:46:13.308049 <6>[ 2.703255] mediatek-drm mediatek-drm.1.auto: bound 14008000.ovl (ops mtk_disp_ovl_component_ops)
6253 23:46:13.317847 <6>[ 2.712403] mediatek-drm mediatek-drm.1.auto: bound 14009000.ovl (ops mtk_disp_ovl_component_ops)
6254 23:46:13.324834 <6>[ 2.721534] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ovl (ops mtk_disp_ovl_component_ops)
6255 23:46:13.334468 <6>[ 2.730663] mediatek-drm mediatek-drm.1.auto: bound 1400b000.rdma (ops mtk_disp_rdma_component_ops)
6256 23:46:13.344355 <6>[ 2.739964] mediatek-drm mediatek-drm.1.auto: bound 1400c000.rdma (ops mtk_disp_rdma_component_ops)
6257 23:46:13.354465 <6>[ 2.749270] mediatek-drm mediatek-drm.1.auto: bound 1400e000.color (ops mtk_disp_color_component_ops)
6258 23:46:13.364571 <6>[ 2.758743] mediatek-drm mediatek-drm.1.auto: bound 1400f000.ccorr (ops mtk_disp_ccorr_component_ops)
6259 23:46:13.374223 <6>[ 2.768216] mediatek-drm mediatek-drm.1.auto: bound 14010000.aal (ops mtk_disp_aal_component_ops)
6260 23:46:13.380943 <6>[ 2.777343] mediatek-drm mediatek-drm.1.auto: bound 14011000.gamma (ops mtk_disp_gamma_component_ops)
6261 23:46:13.428266 <6>[ 2.824408] usb 1-1.2: new high-speed USB device number 3 using xhci-mtk
6262 23:46:13.456655 <6>[ 2.852781] mediatek-drm mediatek-drm.1.auto: bound 14014000.dsi (ops mtk_dsi_component_ops)
6263 23:46:13.466258 <6>[ 2.861655] mediatek-drm mediatek-drm.1.auto: Not creating crtc 1 because component 10 is disabled or missing
6264 23:46:13.477061 <6>[ 2.873121] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 1
6265 23:46:13.612430 <6>[ 3.008661] r8152-cfgselector 1-1.2: reset high-speed USB device number 3 using xhci-mtk
6266 23:46:14.170169 <4>[ 3.120142] r8152 1-1.2:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
6267 23:46:14.180378 <4>[ 3.120169] r8152 1-1.2:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
6268 23:46:14.183766 <6>[ 3.157176] r8152 1-1.2:1.0 eth0: v1.12.13
6269 23:46:14.190411 <6>[ 3.236402] usb 1-1.3: new high-speed USB device number 4 using xhci-mtk
6270 23:46:14.197041 <6>[ 3.549981] Console: switching to colour frame buffer device 170x48
6271 23:46:14.207146 <6>[ 3.602182] mediatek-drm mediatek-drm.1.auto: [drm] fb0: mediatekdrmfb frame buffer device
6272 23:46:14.225302 <6>[ 3.621551] input: wifi-wakeup as /devices/platform/wifi-wakeup/input/input5
6273 23:46:14.232027 <6>[ 3.629898] input: volume-buttons as /devices/platform/volume-buttons/input/input6
6274 23:46:15.378016 <6>[ 4.777293] r8152 1-1.2:1.0 eth0: carrier on
6275 23:46:15.421267 <5>[ 4.804407] Sending DHCP requests ., OK
6276 23:46:15.427803 <6>[ 4.824794] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.13
6277 23:46:15.430722 <6>[ 4.833227] IP-Config: Complete:
6278 23:46:15.443970 <6>[ 4.836798] device=eth0, hwaddr=00:e0:4c:68:0b:b9, ipaddr=192.168.201.13, mask=255.255.255.0, gw=192.168.201.1
6279 23:46:15.453979 <6>[ 4.847703] host=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0, domain=lava-rack, nis-domain=(none)
6280 23:46:15.461005 <6>[ 4.857187] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
6281 23:46:15.464331 <6>[ 4.857197] nameserver0=192.168.201.1
6282 23:46:15.470492 <6>[ 4.869525] clk: Disabling unused clocks
6283 23:46:15.474270 <6>[ 4.874609] ALSA device list:
6284 23:46:15.477126 <6>[ 4.877901] #0: mt8183_mt6358_ts3a227_max98357
6285 23:46:15.490120 <6>[ 4.889829] Freeing unused kernel memory: 8512K
6286 23:46:15.497920 <6>[ 4.897552] Run /init as init process
6287 23:46:15.510453 Loading, please wait...
6288 23:46:15.548326 Starting systemd-udevd version 252.22-1~deb12u1
6289 23:46:15.865477 <3>[ 5.265032] mtk-scp 10500000.scp: invalid resource
6290 23:46:15.872188 <3>[ 5.266483] thermal_sys: Failed to find 'trips' node
6291 23:46:15.879072 <6>[ 5.270234] mtk-scp 10500000.scp: assigned reserved memory node memory@50000000
6292 23:46:15.885587 <3>[ 5.275368] thermal_sys: Failed to find trip points for thermal-sensor1 id=0
6293 23:46:15.895533 <3>[ 5.275379] generic-adc-thermal thermal-sensor1: Thermal zone sensor register failed: -22
6294 23:46:15.905561 <3>[ 5.283517] mt8183-pinctrl 10005000.pinctrl: pin GPIO7 already requested by 2-002c; cannot claim for 2-0015
6295 23:46:15.912155 <4>[ 5.290369] generic-adc-thermal: probe of thermal-sensor1 failed with error -22
6296 23:46:15.918511 <3>[ 5.298691] mt8183-pinctrl 10005000.pinctrl: pin-7 (2-0015) status -22
6297 23:46:15.931966 <3>[ 5.298695] mt8183-pinctrl 10005000.pinctrl: could not request pin 7 (GPIO7) from group GPIO7 on device pinctrl_paris
6298 23:46:15.938481 <3>[ 5.298699] elan_i2c 2-0015: Error applying setting, reverse things back
6299 23:46:15.945460 <4>[ 5.300053] elants_i2c 0-0010: supply vcc33 not found, using dummy regulator
6300 23:46:15.951625 <6>[ 5.301933] remoteproc remoteproc0: scp is available
6301 23:46:15.958774 <4>[ 5.302023] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6302 23:46:15.965259 <6>[ 5.302031] remoteproc remoteproc0: powering up scp
6303 23:46:15.975104 <4>[ 5.302046] remoteproc remoteproc0: Direct firmware load for scp.img failed with error -2
6304 23:46:15.981853 <3>[ 5.302050] remoteproc remoteproc0: request_firmware failed: -2
6305 23:46:15.988170 <3>[ 5.310047] thermal_sys: Failed to find 'trips' node
6306 23:46:15.994906 <4>[ 5.328014] elants_i2c 0-0010: supply vccio not found, using dummy regulator
6307 23:46:16.001790 <3>[ 5.334855] thermal_sys: Failed to find trip points for thermal-sensor2 id=0
6308 23:46:16.011755 <3>[ 5.334865] generic-adc-thermal thermal-sensor2: Thermal zone sensor register failed: -22
6309 23:46:16.018483 <4>[ 5.334868] generic-adc-thermal: probe of thermal-sensor2 failed with error -22
6310 23:46:16.024928 <6>[ 5.352722] mc: Linux media interface: v0.10
6311 23:46:16.031571 <3>[ 5.361097] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6312 23:46:16.038291 <6>[ 5.391936] videodev: Linux video capture interface: v2.00
6313 23:46:16.048044 <3>[ 5.392343] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6314 23:46:16.054695 <6>[ 5.392719] sbs-battery 12-000b: sbs-battery: battery gas gauge device registered
6315 23:46:16.061104 <6>[ 5.392864] cs_system_cfg: CoreSight Configuration manager initialised
6316 23:46:16.071301 <5>[ 5.405287] cfg80211: Loading compiled-in X.509 certificates for regulatory database
6317 23:46:16.077796 <3>[ 5.406959] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6318 23:46:16.084831 <5>[ 5.430031] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
6319 23:46:16.094571 <3>[ 5.437546] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6320 23:46:16.101023 <5>[ 5.443593] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
6321 23:46:16.110947 <3>[ 5.451679] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6322 23:46:16.121314 <4>[ 5.459470] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
6323 23:46:16.127861 <3>[ 5.466293] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6324 23:46:16.135229 <6>[ 5.474341] cfg80211: failed to load regulatory.db
6325 23:46:16.142016 <3>[ 5.482796] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6326 23:46:16.152847 <6>[ 5.496414] input: Elan Touchscreen as /devices/platform/soc/11007000.i2c/i2c-0/0-0010/input/input7
6327 23:46:16.163181 <3>[ 5.498084] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6328 23:46:16.169549 <6>[ 5.516438] coresight-cpu-debug d410000.cpu-debug: Coresight debug-CPU0 initialized
6329 23:46:16.179581 <3>[ 5.524994] OF: graph: no port node found in /soc/spi@11012000/cros-ec@0/typec/connector@0
6330 23:46:16.185852 <6>[ 5.533725] coresight-cpu-debug d510000.cpu-debug: Coresight debug-CPU1 initialized
6331 23:46:16.189150 <6>[ 5.547541] Bluetooth: Core ver 2.22
6332 23:46:16.199402 <6>[ 5.549363] coresight-cpu-debug d610000.cpu-debug: Coresight debug-CPU2 initialized
6333 23:46:16.205763 <6>[ 5.550917] usb 1-1.3: Found UVC 1.00 device HD WebCam (04f2:b567)
6334 23:46:16.212270 <6>[ 5.558483] NET: Registered PF_BLUETOOTH protocol family
6335 23:46:16.218830 <6>[ 5.559112] mtk-mdp3 14001000.dma-controller0: Adding to iommu group 0
6336 23:46:16.225959 <6>[ 5.559160] mtk-jpeg 17030000.venc_jpg: Adding to iommu group 0
6337 23:46:16.235433 <6>[ 5.559573] mtk-jpeg 17030000.venc_jpg: mtk-jpeg-enc device registered as /dev/video0 (81,0)
6338 23:46:16.242059 <6>[ 5.559747] mtk-mdp3 14001000.dma-controller0: Driver registered as /dev/video1
6339 23:46:16.248696 <6>[ 5.567158] coresight-cpu-debug d710000.cpu-debug: Coresight debug-CPU3 initialized
6340 23:46:16.262559 <6>[ 5.569416] input: HD WebCam: HD WebCam as /devices/platform/soc/11201000.usb/11200000.usb/usb1/1-1/1-1.3/1-1.3:1.0/input/input8
6341 23:46:16.268848 <6>[ 5.569564] usbcore: registered new interface driver uvcvideo
6342 23:46:16.275394 <6>[ 5.574858] Bluetooth: HCI device and connection manager initialized
6343 23:46:16.282341 <6>[ 5.574872] Bluetooth: HCI socket layer initialized
6344 23:46:16.288934 <6>[ 5.574877] Bluetooth: L2CAP socket layer initialized
6345 23:46:16.295098 <6>[ 5.583725] coresight-cpu-debug d810000.cpu-debug: Coresight debug-CPU4 initialized
6346 23:46:16.301819 <6>[ 5.591302] Bluetooth: SCO socket layer initialized
6347 23:46:16.311671 <6>[ 5.595243] coresight-cpu-debug d910000.cpu-debug: Coresight debug-CPU5 initialized
6348 23:46:16.315112 <6>[ 5.624179] Bluetooth: HCI UART driver ver 2.3
6349 23:46:16.324737 <6>[ 5.626140] ath10k_sdio mmc1:0001:1: qca6174 hw3.2 sdio target 0x05030000 chip_id 0x00000000 sub 0000:0000
6350 23:46:16.335049 <6>[ 5.626154] ath10k_sdio mmc1:0001:1: kconfig debug 0 debugfs 0 tracing 0 dfs 0 testmode 0
6351 23:46:16.348807 <6>[ 5.626494] ath10k_sdio mmc1:0001:1: firmware ver WLAN.RMH.4.4.1-00174 api 6 features wowlan,ignore-otp,mfp crc32 7319fa77
6352 23:46:16.354870 <6>[ 5.630332] coresight-cpu-debug da10000.cpu-debug: Coresight debug-CPU6 initialized
6353 23:46:16.362357 <6>[ 5.638847] Bluetooth: HCI UART protocol H4 registered
6354 23:46:16.368917 <6>[ 5.638879] Bluetooth: HCI UART protocol LL registered
6355 23:46:16.375338 <6>[ 5.654325] coresight-cpu-debug db10000.cpu-debug: Coresight debug-CPU7 initialized
6356 23:46:16.382019 <6>[ 5.655049] Bluetooth: HCI UART protocol Three-wire (H5) registered
6357 23:46:16.392106 <6>[ 5.783432] ath10k_sdio mmc1:0001:1: board_file api 2 bmi_id 0:4 crc32 d2863f91
6358 23:46:16.398819 <6>[ 5.788687] Bluetooth: HCI UART protocol Broadcom registered
6359 23:46:16.431279 <6>[ 5.830631] Bluetooth: HCI UART protocol QCA registered
6360 23:46:16.437792 <6>[ 5.831489] Bluetooth: hci0: setting up ROME/QCA6390
6361 23:46:16.445437 <6>[ 5.836123] Bluetooth: HCI UART protocol Marvell registered
6362 23:46:16.461561 Begin: Loading essential drivers ... done.
6363 23:46:16.464405 Begin: Running /scripts/init-premount ... done.
6364 23:46:16.471419 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
6365 23:46:16.487717 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to <4>[ 5.882184] sbs-battery 12-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
6366 23:46:16.490992 <4>[ 5.882184] Fallback method does not support PEC.
6367 23:46:16.494490 become available
6368 23:46:16.497697 Device /sys/class/net/eth0 found
6369 23:46:16.497789 done.
6370 23:46:16.511457 Begin: Waiting u<3>[ 5.907269] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6371 23:46:16.517683 p to 180 secs for any network device to become available ... done.
6372 23:46:16.527949 <3>[ 5.923995] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6373 23:46:16.549093 IP-Config: eth0 hardware address 00:e0:4c:68:0b:b9 mtu 1500 DHCP
6374 23:46:16.555367 IP-Config: eth0 complete (dhcp from 192.168.201.1):
6375 23:46:16.562138 address: 192.168.201.13 broadcast: 192.168.201.255 netmask: 255.255.255.0
6376 23:46:16.569254 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
6377 23:46:16.575647 host : mt8183-kukui-jacuzzi-juniper-sku16-cbg-0
6378 23:46:16.582242 domain : lava-rack
6379 23:46:16.585459 rootserver: 192.168.201.1 rootpath:
6380 23:46:16.585568 filename :
6381 23:46:16.672177 <3>[ 6.071653] Bluetooth: hci0: Frame reassembly failed (-84)
6382 23:46:16.750055 done.
6383 23:46:16.757961 Begin: Running /scripts/nfs-bottom ... done.
6384 23:46:16.773618 Begin: Running /scripts/init-bottom ... <6>[ 6.169620] ath10k_sdio mmc1:0001:1: htt-ver 3.87 wmi-op 4 htt-op 3 cal otp max-sta 32 raw 0 hwcrypto 1
6385 23:46:16.776704 done.
6386 23:46:16.857489 <4>[ 6.253761] mmc1: queuing unknown CIS tuple 0x01 [d9 01 ff] (3 bytes)
6387 23:46:16.877972 <4>[ 6.274390] mmc1: queuing unknown CIS tuple 0x1a [01 01 00 02 07] (5 bytes)
6388 23:46:16.894115 <4>[ 6.290449] mmc1: queuing unknown CIS tuple 0x1b [c1 41 30 30 ff ff 32 00] (8 bytes)
6389 23:46:16.904316 <4>[ 6.303896] mmc1: queuing unknown CIS tuple 0x14 [] (0 bytes)
6390 23:46:16.938129 <6>[ 6.337647] Bluetooth: hci0: QCA Product ID :0x00000008
6391 23:46:16.949026 <6>[ 6.348311] Bluetooth: hci0: QCA SOC Version :0x00000044
6392 23:46:16.958645 <6>[ 6.358219] Bluetooth: hci0: QCA ROM Version :0x00000302
6393 23:46:16.968470 <6>[ 6.368006] Bluetooth: hci0: QCA Patch Version:0x00000111
6394 23:46:16.978030 <6>[ 6.377262] Bluetooth: hci0: QCA controller version 0x00440302
6395 23:46:16.990248 <6>[ 6.386550] Bluetooth: hci0: QCA Downloading qca/rampatch_00440302.bin
6396 23:46:17.001232 <4>[ 6.397073] bluetooth hci0: Direct firmware load for qca/rampatch_00440302.bin failed with error -2
6397 23:46:17.012943 <3>[ 6.409294] Bluetooth: hci0: QCA Failed to request file: qca/rampatch_00440302.bin (-2)
6398 23:46:17.021349 <3>[ 6.420987] Bluetooth: hci0: QCA Failed to download patch (-2)
6399 23:46:18.154015 <6>[ 7.553325] NET: Registered PF_INET6 protocol family
6400 23:46:18.166036 <6>[ 7.565590] Segment Routing with IPv6
6401 23:46:18.174251 <6>[ 7.573496] In-situ OAM (IOAM) with IPv6
6402 23:46:18.345368 <30>[ 7.718224] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
6403 23:46:18.364947 <30>[ 7.764151] systemd[1]: Detected architecture arm64.
6404 23:46:18.376509
6405 23:46:18.379962 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
6406 23:46:18.380104
6407 23:46:18.401466 <30>[ 7.801181] systemd[1]: Hostname set to <debian-bookworm-arm64>.
6408 23:46:19.372689 <30>[ 8.768606] systemd[1]: Queued start job for default target graphical.target.
6409 23:46:19.417747 <30>[ 8.813681] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
6410 23:46:19.429712 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
6411 23:46:19.450477 <30>[ 8.846636] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
6412 23:46:19.463902 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
6413 23:46:19.483046 <30>[ 8.878817] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
6414 23:46:19.496991 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
6415 23:46:19.514070 <30>[ 8.910027] systemd[1]: Created slice user.slice - User and Session Slice.
6416 23:46:19.525835 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
6417 23:46:19.548411 <30>[ 8.940982] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
6418 23:46:19.561014 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
6419 23:46:19.580260 <30>[ 8.972810] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
6420 23:46:19.592018 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
6421 23:46:19.618621 <30>[ 9.004770] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
6422 23:46:19.637639 <30>[ 9.034023] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
6423 23:46:19.646421 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
6424 23:46:19.664642 <30>[ 9.060575] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
6425 23:46:19.677653 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
6426 23:46:19.696483 <30>[ 9.092669] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
6427 23:46:19.710723 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
6428 23:46:19.725430 <30>[ 9.124670] systemd[1]: Reached target paths.target - Path Units.
6429 23:46:19.740201 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
6430 23:46:19.756317 <30>[ 9.152570] systemd[1]: Reached target remote-fs.target - Remote File Systems.
6431 23:46:19.768865 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
6432 23:46:19.781229 <30>[ 9.180536] systemd[1]: Reached target slices.target - Slice Units.
6433 23:46:19.795944 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
6434 23:46:19.809384 <30>[ 9.208602] systemd[1]: Reached target swap.target - Swaps.
6435 23:46:19.819374 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
6436 23:46:19.840700 <30>[ 9.236618] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
6437 23:46:19.854033 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
6438 23:46:19.872950 <30>[ 9.268964] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
6439 23:46:19.886350 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
6440 23:46:19.907610 <30>[ 9.303569] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
6441 23:46:19.919527 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
6442 23:46:19.937866 <30>[ 9.334093] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
6443 23:46:19.952057 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
6444 23:46:19.969247 <30>[ 9.365297] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
6445 23:46:19.981219 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
6446 23:46:19.998109 <30>[ 9.394174] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
6447 23:46:20.011346 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
6448 23:46:20.031044 <30>[ 9.427219] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
6449 23:46:20.044151 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
6450 23:46:20.061199 <30>[ 9.457165] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
6451 23:46:20.073760 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
6452 23:46:20.117047 <30>[ 9.513295] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
6453 23:46:20.128663 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
6454 23:46:20.149867 <30>[ 9.545757] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
6455 23:46:20.162419 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
6456 23:46:20.186174 <30>[ 9.582495] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
6457 23:46:20.198385 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
6458 23:46:20.223707 <30>[ 9.613074] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
6459 23:46:20.243916 <30>[ 9.639871] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
6460 23:46:20.256264 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
6461 23:46:20.282715 <30>[ 9.678612] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
6462 23:46:20.293709 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
6463 23:46:20.337765 <30>[ 9.733599] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
6464 23:46:20.350434 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6465 23:46:20.375398 <30>[ 9.771336] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
6466 23:46:20.387099 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
6467 23:46:20.401043 <6>[ 9.797182] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
6468 23:46:20.415725 <30>[ 9.811927] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
6469 23:46:20.427388 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6470 23:46:20.473738 <30>[ 9.869701] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
6471 23:46:20.484877 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
6472 23:46:20.509928 <30>[ 9.905955] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
6473 23:46:20.518705 Startin<6>[ 9.918312] fuse: init (API version 7.37)
6474 23:46:20.525372 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6475 23:46:20.555607 <30>[ 9.951626] systemd[1]: Starting systemd-journald.service - Journal Service...
6476 23:46:20.565682 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
6477 23:46:20.591197 <30>[ 9.987062] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
6478 23:46:20.602005 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
6479 23:46:20.652208 <30>[ 10.045034] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
6480 23:46:20.663394 Starting [0;1;39msystemd-network-g… units from Kernel command line...
6481 23:46:20.683785 <30>[ 10.079908] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
6482 23:46:20.696267 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
6483 23:46:20.716325 <30>[ 10.112032] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
6484 23:46:20.731682 Starting [0;1;39msyste<3>[ 10.125685] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6485 23:46:20.735187 md-udev-trig…[0m - Coldplug All udev Devices...
6486 23:46:20.747734 <3>[ 10.143134] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6487 23:46:20.760133 <30>[ 10.157911] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
6488 23:46:20.770175 <3>[ 10.161977] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6489 23:46:20.787981 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File S<3>[ 10.181902] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6490 23:46:20.788140 ystem.
6491 23:46:20.804726 <3>[ 10.200417] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6492 23:46:20.813062 <30>[ 10.201065] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
6493 23:46:20.819430 <3>[ 10.215847] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6494 23:46:20.835930 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
6495 23:46:20.842827 <3>[ 10.240223] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6496 23:46:20.858644 <30>[ 10.253173] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
6497 23:46:20.865188 <3>[ 10.258811] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6498 23:46:20.878014 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
6499 23:46:20.897486 <30>[ 10.293352] systemd[1]: Started systemd-journald.service - Journal Service.
6500 23:46:20.907581 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
6501 23:46:20.929108 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
6502 23:46:20.951726 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
6503 23:46:20.971853 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6504 23:46:20.992004 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
6505 23:46:21.011426 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6506 23:46:21.031735 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
6507 23:46:21.051169 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6508 23:46:21.073970 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
6509 23:46:21.097902 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
6510 23:46:21.117982 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
6511 23:46:21.139649 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
6512 23:46:21.189059 <4>[ 10.578427] synth uevent: /devices/platform/soc/11012000.spi/spi_master/spi2/spi2.0/11012000.spi:cros-ec@0:i2c-tunnel/i2c-12/12-000b/power_supply/sbs-12-000b: failed to send uevent
6513 23:46:21.200975 <3>[ 10.596165] power_supply sbs-12-000b: uevent: failed to send synthetic uevent: -5
6514 23:46:21.211125 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
6515 23:46:21.235215 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
6516 23:46:21.286719 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
6517 23:46:21.312855 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
6518 23:46:21.341281 Starting [0;1;39msystemd-sysctl.se…c<46>[ 10.737367] systemd-journald[320]: Received client request to flush runtime journal.
6519 23:46:21.345005 e[0m - Apply Kernel Variables...
6520 23:46:21.389888 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
6521 23:46:21.677069 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
6522 23:46:21.698579 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
6523 23:46:21.717941 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
6524 23:46:21.738676 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
6525 23:46:22.130378 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
6526 23:46:22.487512 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
6527 23:46:22.526205 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
6528 23:46:22.792020 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
6529 23:46:22.916014 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
6530 23:46:22.934012 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
6531 23:46:22.953221 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
6532 23:46:23.002545 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
6533 23:46:23.028310 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
6534 23:46:23.290297 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
6535 23:46:23.314053 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
6536 23:46:23.387375 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
6537 23:46:23.456818 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
6538 23:46:23.586767 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
6539 23:46:23.594407 <4>[ 12.992834] power_supply_show_property: 4 callbacks suppressed
6540 23:46:23.601179 <3>[ 12.992851] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6541 23:46:23.612321 <3>[ 12.997376] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6542 23:46:23.626905 Starting [0;1;39msystemd-update-ut…rd System Boot/Sh<3>[ 13.022874] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6543 23:46:23.630213 utdown in UTMP...
6544 23:46:23.642734 <3>[ 13.038264] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6545 23:46:23.658838 <3>[ 13.054598] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6546 23:46:23.674902 <3>[ 13.070503] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6547 23:46:23.691258 <3>[ 13.086746] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6548 23:46:23.707961 <3>[ 13.103422] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6549 23:46:23.723331 <3>[ 13.119201] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6550 23:46:23.737960 <3>[ 13.133946] power_supply sbs-12-000b: driver failed to report `technology' property: -5
6551 23:46:23.852171 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
6552 23:46:23.872863 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
6553 23:46:23.889737 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
6554 23:46:23.925077 Starting [0;1;39msystemd-backlight…ess of backlight:backlight_lcd0...
6555 23:46:23.979190 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of backlight:backlight_lcd0.
6556 23:46:24.022163 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
6557 23:46:24.048691 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
6558 23:46:24.075461 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
6559 23:46:24.133989 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
6560 23:46:24.157459 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
6561 23:46:24.178270 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
6562 23:46:24.197886 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
6563 23:46:24.221856 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
6564 23:46:24.243937 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
6565 23:46:24.263393 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
6566 23:46:24.286968 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
6567 23:46:24.312093 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
6568 23:46:24.332920 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
6569 23:46:24.349210 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
6570 23:46:24.370400 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
6571 23:46:24.427067 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
6572 23:46:24.445381 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
6573 23:46:24.463472 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
6574 23:46:24.487361 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
6575 23:46:24.505111 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
6576 23:46:24.520841 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
6577 23:46:24.538765 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
6578 23:46:24.556863 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
6579 23:46:24.573166 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
6580 23:46:24.617600 Starting [0;1;39malsa-restore.serv…- Save/Restore Sound Card State...
6581 23:46:24.635803 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
6582 23:46:24.670006 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
6583 23:46:24.769780 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
6584 23:46:24.794500 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
6585 23:46:24.817100 [[0;32m OK [0m] Finished [0;1;39malsa-restore.serv…m - Save/Restore Sound Card State.
6586 23:46:24.838377 [[0;32m OK [0m] Reached target [0;1;39msound.target[0m - Sound Card.
6587 23:46:24.990655 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
6588 23:46:25.041563 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
6589 23:46:25.086834 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
6590 23:46:25.111205 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
6591 23:46:25.133645 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
6592 23:46:25.163632 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
6593 23:46:25.185928 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
6594 23:46:25.206459 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
6595 23:46:25.224576 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
6596 23:46:25.278881 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
6597 23:46:25.377816 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
6598 23:46:25.470624
6599 23:46:25.473809 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
6600 23:46:25.473962
6601 23:46:25.477027 debian-bookworm-arm64 login: root (automatic login)
6602 23:46:25.477120
6603 23:46:25.732959 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024 aarch64
6604 23:46:25.733129
6605 23:46:25.739306 The programs included with the Debian GNU/Linux system are free software;
6606 23:46:25.746110 the exact distribution terms for each program are described in the
6607 23:46:25.749851 individual files in /usr/share/doc/*/copyright.
6608 23:46:25.749986
6609 23:46:25.756034 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
6610 23:46:25.759430 permitted by applicable law.
6611 23:46:26.804742 Matched prompt #10: / #
6613 23:46:26.805055 Setting prompt string to ['/ #']
6614 23:46:26.805161 end: 2.2.5.1 login-action (duration 00:00:17) [common]
6616 23:46:26.805376 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
6617 23:46:26.805474 start: 2.2.6 expect-shell-connection (timeout 00:03:49) [common]
6618 23:46:26.805551 Setting prompt string to ['/ #']
6619 23:46:26.805618 Forcing a shell prompt, looking for ['/ #']
6621 23:46:26.855832 / #
6622 23:46:26.856014 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
6623 23:46:26.856108 Waiting using forced prompt support (timeout 00:02:30)
6624 23:46:26.860660
6625 23:46:26.860969 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
6626 23:46:26.861084 start: 2.2.7 export-device-env (timeout 00:03:49) [common]
6628 23:46:26.961486 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172940/extract-nfsrootfs-kqrq6156'
6629 23:46:26.966368 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172940/extract-nfsrootfs-kqrq6156'
6631 23:46:27.066925 / # export NFS_SERVER_IP='192.168.201.1'
6632 23:46:27.071431 export NFS_SERVER_IP='192.168.201.1'
6633 23:46:27.071738 end: 2.2.7 export-device-env (duration 00:00:00) [common]
6634 23:46:27.071852 end: 2.2 depthcharge-retry (duration 00:01:11) [common]
6635 23:46:27.071958 end: 2 depthcharge-action (duration 00:01:11) [common]
6636 23:46:27.072059 start: 3 lava-test-retry (timeout 00:08:05) [common]
6637 23:46:27.072162 start: 3.1 lava-test-shell (timeout 00:08:05) [common]
6638 23:46:27.072248 Using namespace: common
6640 23:46:27.172639 / # #
6641 23:46:27.172820 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
6642 23:46:27.178172 #
6643 23:46:27.178455 Using /lava-14172940
6645 23:46:27.278832 / # export SHELL=/bin/bash
6646 23:46:27.283684 export SHELL=/bin/bash
6648 23:46:27.384271 / # . /lava-14172940/environment
6649 23:46:27.389587 . /lava-14172940/environment
6651 23:46:27.493554 / # /lava-14172940/bin/lava-test-runner /lava-14172940/0
6652 23:46:27.493735 Test shell timeout: 10s (minimum of the action and connection timeout)
6653 23:46:27.498258 /lava-14172940/bin/lava-test-runner /lava-14172940/0
6654 23:46:27.713128 + export TESTRUN_ID=0_timesync-off
6655 23:46:27.716255 + TESTRUN_ID=0_timesync-off
6656 23:46:27.719300 + cd /lava-14172940/0/tests/0_timesync-off
6657 23:46:27.722770 ++ cat uuid
6658 23:46:27.727686 + UUID=14172940_1.6.2.3.1
6659 23:46:27.727817 + set +x
6660 23:46:27.734323 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14172940_1.6.2.3.1>
6661 23:46:27.734645 Received signal: <STARTRUN> 0_timesync-off 14172940_1.6.2.3.1
6662 23:46:27.734770 Starting test lava.0_timesync-off (14172940_1.6.2.3.1)
6663 23:46:27.734913 Skipping test definition patterns.
6664 23:46:27.737871 + systemctl stop systemd-timesyncd
6665 23:46:27.797341 + set +x
6666 23:46:27.800107 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14172940_1.6.2.3.1>
6667 23:46:27.800431 Received signal: <ENDRUN> 0_timesync-off 14172940_1.6.2.3.1
6668 23:46:27.800573 Ending use of test pattern.
6669 23:46:27.800678 Ending test lava.0_timesync-off (14172940_1.6.2.3.1), duration 0.07
6671 23:46:27.867672 + export TESTRUN_ID=1_kselftest-alsa
6672 23:46:27.867874 + TESTRUN_ID=1_kselftest-alsa
6673 23:46:27.873849 + cd /lava-14172940/0/tests/1_kselftest-alsa
6674 23:46:27.873986 ++ cat uuid
6675 23:46:27.877135 + UUID=14172940_1.6.2.3.5
6676 23:46:27.877258 + set +x
6677 23:46:27.880374 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14172940_1.6.2.3.5>
6678 23:46:27.880681 Received signal: <STARTRUN> 1_kselftest-alsa 14172940_1.6.2.3.5
6679 23:46:27.880798 Starting test lava.1_kselftest-alsa (14172940_1.6.2.3.5)
6680 23:46:27.880933 Skipping test definition patterns.
6681 23:46:27.884178 + cd ./automated/linux/kselftest/
6682 23:46:27.910713 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8183-kukui-jacuzzi-juniper-sku16 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
6683 23:46:27.943010 INFO: install_deps skipped
6684 23:46:28.423843 --2024-06-04 23:45:31-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
6685 23:46:28.430501 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
6686 23:46:28.553885 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
6687 23:46:28.682032 HTTP request sent, awaiting response... 200 OK
6688 23:46:28.685611 Length: 1642752 (1.6M) [application/octet-stream]
6689 23:46:28.688763 Saving to: 'kselftest_armhf.tar.gz'
6690 23:46:28.688883
6691 23:46:28.688986
6692 23:46:28.939133 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
6693 23:46:29.195820 kselftest_armhf.tar 2%[ ] 43.57K 168KB/s
6694 23:46:29.452816 kselftest_armhf.tar 13%[=> ] 213.25K 411KB/s
6695 23:46:29.743102 kselftest_armhf.tar 55%[==========> ] 894.83K 1.12MB/s
6696 23:46:29.749521 kselftest_armhf.tar 97%[==================> ] 1.52M 1.42MB/s
6697 23:46:29.756322 kselftest_armhf.tar 100%[===================>] 1.57M 1.46MB/s in 1.1s
6698 23:46:29.756469
6699 23:46:29.895142 2024-06-04 23:45:32 (1.46 MB/s) - 'kselftest_armhf.tar.gz' saved [1642752/1642752]
6700 23:46:29.895344
6701 23:46:33.888737 skiplist:
6702 23:46:33.892184 ========================================
6703 23:46:33.894962 ========================================
6704 23:46:33.933926 alsa:mixer-test
6705 23:46:33.951688 ============== Tests to run ===============
6706 23:46:33.951855 alsa:mixer-test
6707 23:46:33.954973 ===========End Tests to run ===============
6708 23:46:33.959756 shardfile-alsa pass
6709 23:46:34.060799 <12>[ 23.459500] kselftest: Running tests in alsa
6710 23:46:34.072800 TAP version 13
6711 23:46:34.087850 1..1
6712 23:46:34.103991 # selftests: alsa: mixer-test
6713 23:46:34.246973 <6>[ 23.639543] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6714 23:46:34.260447 <6>[ 23.651938] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6715 23:46:34.273380 <6>[ 23.664233] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 1
6716 23:46:34.283377 <6>[ 23.676516] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6717 23:46:34.296651 <6>[ 23.688760] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_adda_dmic_set(), kcontrol name MTKAIF_DMIC, mtkaif_dmic 0
6718 23:46:34.309678 <6>[ 23.701258] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6719 23:46:34.320049 <6>[ 23.712792] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6720 23:46:34.333339 <6>[ 23.724214] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 1
6721 23:46:34.342917 <6>[ 23.735617] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6722 23:46:34.352881 <6>[ 23.747048] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S5_HD_Mux, hd_en 0
6723 23:46:34.366510 <6>[ 23.758580] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6724 23:46:34.376482 <6>[ 23.769918] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6725 23:46:34.389437 <6>[ 23.781253] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 1
6726 23:46:34.399269 <6>[ 23.792585] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6727 23:46:34.412729 <6>[ 23.803938] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S3_HD_Mux, hd_en 0
6728 23:46:34.422817 <6>[ 23.815284] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6729 23:46:34.432771 <6>[ 23.826618] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6730 23:46:34.445867 <6>[ 23.837947] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 1
6731 23:46:34.456027 <6>[ 23.849278] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6732 23:46:34.469483 <6>[ 23.860626] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S2_HD_Mux, hd_en 0
6733 23:46:34.479320 <6>[ 23.871966] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6734 23:46:34.489181 <6>[ 23.883297] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6735 23:46:34.502369 <6>[ 23.894625] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 1
6736 23:46:34.512547 <6>[ 23.905954] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6737 23:46:34.526008 <6>[ 23.917289] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S1_HD_Mux, hd_en 0
6738 23:46:34.535775 <6>[ 23.928630] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6739 23:46:34.545886 <6>[ 23.939964] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6740 23:46:34.559072 <6>[ 23.951292] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 1
6741 23:46:34.569027 <6>[ 23.962623] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6742 23:46:34.582248 <6>[ 23.973955] mt8183-audio 11220000.audio-controller:mt8183-afe-pcm: mt8183_i2s_hd_set(), kcontrol name I2S0_HD_Mux, hd_en 0
6743 23:46:34.582458 # TAP version 13
6744 23:46:34.585505 # 1..658
6745 23:46:34.585651 # ok 1 get_value.0.93
6746 23:46:34.589051 # ok 2 name.0.93
6747 23:46:34.589186 # ok 3 write_default.0.93
6748 23:46:34.592384 # ok 4 write_valid.0.93
6749 23:46:34.595262 # ok 5 write_invalid.0.93
6750 23:46:34.595412 # ok 6 event_missing.0.93
6751 23:46:34.598656 # ok 7 event_spurious.0.93
6752 23:46:34.602237 # ok 8 get_value.0.92
6753 23:46:34.602349 # ok 9 name.0.92
6754 23:46:34.605722 # ok 10 write_default.0.92
6755 23:46:34.608459 # ok 11 write_valid.0.92
6756 23:46:34.608555 # ok 12 write_invalid.0.92
6757 23:46:34.611686 # ok 13 event_missing.0.92
6758 23:46:34.615243 # ok 14 event_spurious.0.92
6759 23:46:34.615346 # ok 15 get_value.0.91
6760 23:46:34.618413 # ok 16 name.0.91
6761 23:46:34.622012 # ok 17 write_default.0.91
6762 23:46:34.622113 # ok 18 write_valid.0.91
6763 23:46:34.625326 # ok 19 write_invalid.0.91
6764 23:46:34.628651 # ok 20 event_missing.0.91
6765 23:46:34.631979 # ok 21 event_spurious.0.91
6766 23:46:34.632094 # ok 22 get_value.0.90
6767 23:46:34.635400 # ok 23 name.0.90
6768 23:46:34.638557 # ok 24 write_default.0.90
6769 23:46:34.638679 # ok 25 write_valid.0.90
6770 23:46:34.641776 # ok 26 write_invalid.0.90
6771 23:46:34.645258 # ok 27 event_missing.0.90
6772 23:46:34.648065 # ok 28 event_spurious.0.90
6773 23:46:34.648171 # ok 29 get_value.0.89
6774 23:46:34.651359 # ok 30 name.0.89
6775 23:46:34.654694 # ok 31 write_default.0.89
6776 23:46:34.654812 # ok 32 write_valid.0.89
6777 23:46:34.658227 # ok 33 write_invalid.0.89
6778 23:46:34.661625 # ok 34 event_missing.0.89
6779 23:46:34.664767 # ok 35 event_spurious.0.89
6780 23:46:34.664911 # ok 36 get_value.0.88
6781 23:46:34.668114 # ok 37 name.0.88
6782 23:46:34.668226 # ok 38 write_default.0.88
6783 23:46:34.674795 # # Spurious event generated for AIF Out Mux
6784 23:46:34.678020 # # AIF Out Mux.0 expected 1 but read 0, is_volatile 0
6785 23:46:34.681406 # # Spurious event generated for AIF Out Mux
6786 23:46:34.684412 # not ok 39 write_valid.0.88
6787 23:46:34.687706 # ok 40 write_invalid.0.88
6788 23:46:34.691135 # ok 41 event_missing.0.88
6789 23:46:34.691270 # not ok 42 event_spurious.0.88
6790 23:46:34.694645 # ok 43 get_value.0.87
6791 23:46:34.697885 # ok 44 name.0.87
6792 23:46:34.697979 # ok 45 write_default.0.87
6793 23:46:34.701383 # ok 46 write_valid.0.87
6794 23:46:34.704678 # ok 47 write_invalid.0.87
6795 23:46:34.707549 # ok 48 event_missing.0.87
6796 23:46:34.707644 # ok 49 event_spurious.0.87
6797 23:46:34.711020 # ok 50 get_value.0.86
6798 23:46:34.711113 # ok 51 name.0.86
6799 23:46:34.714575 # ok 52 write_default.0.86
6800 23:46:34.721369 # # HPR Mux.0 expected 5 but read 0, is_volatile 0
6801 23:46:34.724183 # # HPR Mux.0 expected 6 but read 0, is_volatile 0
6802 23:46:34.727644 # # HPR Mux.0 expected 7 but read 0, is_volatile 0
6803 23:46:34.731272 # not ok 53 write_valid.0.86
6804 23:46:34.734393 # ok 54 write_invalid.0.86
6805 23:46:34.734487 # ok 55 event_missing.0.86
6806 23:46:34.737686 # ok 56 event_spurious.0.86
6807 23:46:34.740861 # ok 57 get_value.0.85
6808 23:46:34.740956 # ok 58 name.0.85
6809 23:46:34.744168 # ok 59 write_default.0.85
6810 23:46:34.747479 # # HPL Mux.0 expected 5 but read 0, is_volatile 0
6811 23:46:34.754171 # # HPL Mux.0 expected 6 but read 0, is_volatile 0
6812 23:46:34.757532 # # HPL Mux.0 expected 7 but read 0, is_volatile 0
6813 23:46:34.760813 # not ok 60 write_valid.0.85
6814 23:46:34.764169 # ok 61 write_invalid.0.85
6815 23:46:34.764267 # ok 62 event_missing.0.85
6816 23:46:34.767479 # ok 63 event_spurious.0.85
6817 23:46:34.770908 # ok 64 get_value.0.84
6818 23:46:34.771048 # ok 65 name.0.84
6819 23:46:34.774092 # ok 66 write_default.0.84
6820 23:46:34.777144 # ok 67 write_valid.0.84
6821 23:46:34.777256 # ok 68 write_invalid.0.84
6822 23:46:34.780756 # ok 69 event_missing.0.84
6823 23:46:34.784067 # ok 70 event_spurious.0.84
6824 23:46:34.787359 # ok 71 get_value.0.83
6825 23:46:34.787468 # ok 72 name.0.83
6826 23:46:34.790803 # ok 73 write_default.0.83
6827 23:46:34.790895 # ok 74 write_valid.0.83
6828 23:46:34.794124 # ok 75 write_invalid.0.83
6829 23:46:34.797035 # ok 76 event_missing.0.83
6830 23:46:34.800557 # ok 77 event_spurious.0.83
6831 23:46:34.800647 # ok 78 get_value.0.82
6832 23:46:34.803916 # ok 79 name.0.82
6833 23:46:34.807371 # # Headset Jack is not writeable
6834 23:46:34.810313 # ok 80 # SKIP write_default.0.82
6835 23:46:34.813530 # # Headset Jack is not writeable
6836 23:46:34.813659 # ok 81 # SKIP write_valid.0.82
6837 23:46:34.816966 # # Headset Jack is not writeable
6838 23:46:34.820414 # ok 82 # SKIP write_invalid.0.82
6839 23:46:34.823836 # ok 83 event_missing.0.82
6840 23:46:34.827293 # ok 84 event_spurious.0.82
6841 23:46:34.827521 # ok 85 get_value.0.81
6842 23:46:34.830303 # ok 86 name.0.81
6843 23:46:34.833556 # ok 87 write_default.0.81
6844 23:46:34.837625 # # No event generated for Wake-on-Voice Phase2 Switch
6845 23:46:34.843782 # # No event generated for Wake-on-Voice Phase2 Switch
6846 23:46:34.843971 # ok 88 write_valid.0.81
6847 23:46:34.850659 # # Wake-on-Voice Phase2 Switch.0 Invalid boolean value 2
6848 23:46:34.853945 # # No event generated for Wake-on-Voice Phase2 Switch
6849 23:46:34.857133 # not ok 89 write_invalid.0.81
6850 23:46:34.860513 # not ok 90 event_missing.0.81
6851 23:46:34.863737 # ok 91 event_spurious.0.81
6852 23:46:34.863908 # ok 92 get_value.0.80
6853 23:46:34.867112 # ok 93 name.0.80
6854 23:46:34.870575 # ok 94 write_default.0.80
6855 23:46:34.870716 # ok 95 write_valid.0.80
6856 23:46:34.873826 # ok 96 write_invalid.0.80
6857 23:46:34.877048 # ok 97 event_missing.0.80
6858 23:46:34.877215 # ok 98 event_spurious.0.80
6859 23:46:34.883476 # # Handset Volume.0 value -13 less than minimum 0
6860 23:46:34.883643 # not ok 99 get_value.0.79
6861 23:46:34.887081 # ok 100 name.0.79
6862 23:46:34.890248 # # snd_ctl_elem_write() failed: Invalid argument
6863 23:46:34.893544 # not ok 101 write_default.0.79
6864 23:46:34.900519 # # snd_ctl_elem_write() failed: Invalid argument
6865 23:46:34.900620 # not ok 102 write_valid.0.79
6866 23:46:34.907028 # # snd_ctl_elem_write() failed: Invalid argument
6867 23:46:34.910271 # not ok 103 write_invalid.0.79
6868 23:46:34.910363 # ok 104 event_missing.0.79
6869 23:46:34.913744 # ok 105 event_spurious.0.79
6870 23:46:34.916532 # # Lineout Volume.0 value -13 less than minimum 0
6871 23:46:34.923307 # # Lineout Volume.1 value -13 less than minimum 0
6872 23:46:34.926618 # not ok 106 get_value.0.78
6873 23:46:34.926729 # ok 107 name.0.78
6874 23:46:34.930097 # # snd_ctl_elem_write() failed: Invalid argument
6875 23:46:34.933659 # not ok 108 write_default.0.78
6876 23:46:34.940359 # # snd_ctl_elem_write() failed: Invalid argument
6877 23:46:34.940487 # not ok 109 write_valid.0.78
6878 23:46:34.946694 # # snd_ctl_elem_write() failed: Invalid argument
6879 23:46:34.950142 # not ok 110 write_invalid.0.78
6880 23:46:34.950249 # ok 111 event_missing.0.78
6881 23:46:34.953499 # ok 112 event_spurious.0.78
6882 23:46:34.959737 # # Headphone Volume.0 value -13 less than minimum 0
6883 23:46:34.963578 # # Headphone Volume.1 value -13 less than minimum 0
6884 23:46:34.966382 # not ok 113 get_value.0.77
6885 23:46:34.966482 # ok 114 name.0.77
6886 23:46:34.973542 # # snd_ctl_elem_write() failed: Invalid argument
6887 23:46:34.976719 # not ok 115 write_default.0.77
6888 23:46:34.979567 # # snd_ctl_elem_write() failed: Invalid argument
6889 23:46:34.983092 # not ok 116 write_valid.0.77
6890 23:46:34.986766 # # snd_ctl_elem_write() failed: Invalid argument
6891 23:46:34.989771 # not ok 117 write_invalid.0.77
6892 23:46:34.993007 # ok 118 event_missing.0.77
6893 23:46:34.993106 # ok 119 event_spurious.0.77
6894 23:46:34.996765 # ok 120 get_value.0.76
6895 23:46:35.002867 # # 0.76 ADDA_DL_CH2 PCM_2_CAP_CH2 is a writeable boolean but not a Switch
6896 23:46:35.006228 # not ok 121 name.0.76
6897 23:46:35.006336 # ok 122 write_default.0.76
6898 23:46:35.009695 # ok 123 write_valid.0.76
6899 23:46:35.013324 # ok 124 write_invalid.0.76
6900 23:46:35.016448 # ok 125 event_missing.0.76
6901 23:46:35.016559 # ok 126 event_spurious.0.76
6902 23:46:35.019891 # ok 127 get_value.0.75
6903 23:46:35.026065 # # 0.75 ADDA_DL_CH2 PCM_1_CAP_CH2 is a writeable boolean but not a Switch
6904 23:46:35.029482 # not ok 128 name.0.75
6905 23:46:35.029587 # ok 129 write_default.0.75
6906 23:46:35.032883 # ok 130 write_valid.0.75
6907 23:46:35.036207 # ok 131 write_invalid.0.75
6908 23:46:35.039731 # ok 132 event_missing.0.75
6909 23:46:35.039841 # ok 133 event_spurious.0.75
6910 23:46:35.043121 # ok 134 get_value.0.74
6911 23:46:35.049450 # # 0.74 ADDA_DL_CH2 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6912 23:46:35.052769 # not ok 135 name.0.74
6913 23:46:35.056126 # ok 136 write_default.0.74
6914 23:46:35.056247 # ok 137 write_valid.0.74
6915 23:46:35.059685 # ok 138 write_invalid.0.74
6916 23:46:35.063259 # ok 139 event_missing.0.74
6917 23:46:35.063378 # ok 140 event_spurious.0.74
6918 23:46:35.066190 # ok 141 get_value.0.73
6919 23:46:35.072565 # # 0.73 ADDA_DL_CH2 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
6920 23:46:35.075870 # not ok 142 name.0.73
6921 23:46:35.079309 # ok 143 write_default.0.73
6922 23:46:35.079436 # ok 144 write_valid.0.73
6923 23:46:35.082582 # ok 145 write_invalid.0.73
6924 23:46:35.085775 # ok 146 event_missing.0.73
6925 23:46:35.089339 # ok 147 event_spurious.0.73
6926 23:46:35.089429 # ok 148 get_value.0.72
6927 23:46:35.095980 # # 0.72 ADDA_DL_CH2 ADDA_UL_CH1 is a writeable boolean but not a Switch
6928 23:46:35.099306 # not ok 149 name.0.72
6929 23:46:35.102523 # ok 150 write_default.0.72
6930 23:46:35.102613 # ok 151 write_valid.0.72
6931 23:46:35.105674 # ok 152 write_invalid.0.72
6932 23:46:35.109213 # ok 153 event_missing.0.72
6933 23:46:35.112781 # ok 154 event_spurious.0.72
6934 23:46:35.112895 # ok 155 get_value.0.71
6935 23:46:35.119650 # # 0.71 ADDA_DL_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
6936 23:46:35.122453 # not ok 156 name.0.71
6937 23:46:35.125743 # ok 157 write_default.0.71
6938 23:46:35.125842 # ok 158 write_valid.0.71
6939 23:46:35.129025 # ok 159 write_invalid.0.71
6940 23:46:35.132459 # ok 160 event_missing.0.71
6941 23:46:35.135710 # ok 161 event_spurious.0.71
6942 23:46:35.135802 # ok 162 get_value.0.70
6943 23:46:35.142397 # # 0.70 ADDA_DL_CH2 DL3_CH2 is a writeable boolean but not a Switch
6944 23:46:35.145762 # not ok 163 name.0.70
6945 23:46:35.145854 # ok 164 write_default.0.70
6946 23:46:35.149075 # ok 165 write_valid.0.70
6947 23:46:35.152584 # ok 166 write_invalid.0.70
6948 23:46:35.155326 # ok 167 event_missing.0.70
6949 23:46:35.155430 # ok 168 event_spurious.0.70
6950 23:46:35.158729 # ok 169 get_value.0.69
6951 23:46:35.166044 # # 0.69 ADDA_DL_CH2 DL3_CH1 is a writeable boolean but not a Switch
6952 23:46:35.168458 # not ok 170 name.0.69
6953 23:46:35.168559 # ok 171 write_default.0.69
6954 23:46:35.171661 # ok 172 write_valid.0.69
6955 23:46:35.175008 # ok 173 write_invalid.0.69
6956 23:46:35.178490 # ok 174 event_missing.0.69
6957 23:46:35.178614 # ok 175 event_spurious.0.69
6958 23:46:35.182138 # ok 176 get_value.0.68
6959 23:46:35.188432 # # 0.68 ADDA_DL_CH2 DL2_CH2 is a writeable boolean but not a Switch
6960 23:46:35.188526 # not ok 177 name.0.68
6961 23:46:35.191869 # ok 178 write_default.0.68
6962 23:46:35.194871 # ok 179 write_valid.0.68
6963 23:46:35.198417 # ok 180 write_invalid.0.68
6964 23:46:35.198512 # ok 181 event_missing.0.68
6965 23:46:35.201665 # ok 182 event_spurious.0.68
6966 23:46:35.205014 # ok 183 get_value.0.67
6967 23:46:35.211560 # # 0.67 ADDA_DL_CH2 DL2_CH1 is a writeable boolean but not a Switch
6968 23:46:35.211651 # not ok 184 name.0.67
6969 23:46:35.214936 # ok 185 write_default.0.67
6970 23:46:35.217987 # ok 186 write_valid.0.67
6971 23:46:35.221467 # ok 187 write_invalid.0.67
6972 23:46:35.221591 # ok 188 event_missing.0.67
6973 23:46:35.224525 # ok 189 event_spurious.0.67
6974 23:46:35.228266 # ok 190 get_value.0.66
6975 23:46:35.234629 # # 0.66 ADDA_DL_CH2 DL1_CH2 is a writeable boolean but not a Switch
6976 23:46:35.234722 # not ok 191 name.0.66
6977 23:46:35.238237 # ok 192 write_default.0.66
6978 23:46:35.241308 # ok 193 write_valid.0.66
6979 23:46:35.241399 # ok 194 write_invalid.0.66
6980 23:46:35.244732 # ok 195 event_missing.0.66
6981 23:46:35.248209 # ok 196 event_spurious.0.66
6982 23:46:35.251460 # ok 197 get_value.0.65
6983 23:46:35.258364 # # 0.65 ADDA_DL_CH2 DL1_CH1 is a writeable boolean but not a Switch
6984 23:46:35.258460 # not ok 198 name.0.65
6985 23:46:35.261760 # ok 199 write_default.0.65
6986 23:46:35.264962 # ok 200 write_valid.0.65
6987 23:46:35.265081 # ok 201 write_invalid.0.65
6988 23:46:35.267856 # ok 202 event_missing.0.65
6989 23:46:35.271491 # ok 203 event_spurious.0.65
6990 23:46:35.274634 # ok 204 get_value.0.64
6991 23:46:35.281661 # # 0.64 ADDA_DL_CH1 PCM_2_CAP_CH1 is a writeable boolean but not a Switch
6992 23:46:35.281752 # not ok 205 name.0.64
6993 23:46:35.285189 # ok 206 write_default.0.64
6994 23:46:35.288039 # ok 207 write_valid.0.64
6995 23:46:35.288130 # ok 208 write_invalid.0.64
6996 23:46:35.291613 # ok 209 event_missing.0.64
6997 23:46:35.294743 # ok 210 event_spurious.0.64
6998 23:46:35.298009 # ok 211 get_value.0.63
6999 23:46:35.305030 # # 0.63 ADDA_DL_CH1 PCM_1_CAP_CH1 is a writeable boolean but not a Switch
7000 23:46:35.305120 # not ok 212 name.0.63
7001 23:46:35.308569 # ok 213 write_default.0.63
7002 23:46:35.311320 # ok 214 write_valid.0.63
7003 23:46:35.311441 # ok 215 write_invalid.0.63
7004 23:46:35.314933 # ok 216 event_missing.0.63
7005 23:46:35.318193 # ok 217 event_spurious.0.63
7006 23:46:35.321724 # ok 218 get_value.0.62
7007 23:46:35.324708 # # 0.62 ADDA_DL_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7008 23:46:35.328222 # not ok 219 name.0.62
7009 23:46:35.331775 # ok 220 write_default.0.62
7010 23:46:35.334807 # ok 221 write_valid.0.62
7011 23:46:35.334919 # ok 222 write_invalid.0.62
7012 23:46:35.337855 # ok 223 event_missing.0.62
7013 23:46:35.341463 # ok 224 event_spurious.0.62
7014 23:46:35.344821 # ok 225 get_value.0.61
7015 23:46:35.347858 # # 0.61 ADDA_DL_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7016 23:46:35.351206 # not ok 226 name.0.61
7017 23:46:35.354646 # ok 227 write_default.0.61
7018 23:46:35.357893 # ok 228 write_valid.0.61
7019 23:46:35.357984 # ok 229 write_invalid.0.61
7020 23:46:35.361235 # ok 230 event_missing.0.61
7021 23:46:35.364713 # ok 231 event_spurious.0.61
7022 23:46:35.367606 # ok 232 get_value.0.60
7023 23:46:35.370954 # # 0.60 ADDA_DL_CH1 DL3_CH1 is a writeable boolean but not a Switch
7024 23:46:35.374468 # not ok 233 name.0.60
7025 23:46:35.377910 # ok 234 write_default.0.60
7026 23:46:35.378001 # ok 235 write_valid.0.60
7027 23:46:35.380932 # ok 236 write_invalid.0.60
7028 23:46:35.384035 # ok 237 event_missing.0.60
7029 23:46:35.387789 # ok 238 event_spurious.0.60
7030 23:46:35.387880 # ok 239 get_value.0.59
7031 23:46:35.394191 # # 0.59 ADDA_DL_CH1 DL2_CH1 is a writeable boolean but not a Switch
7032 23:46:35.397557 # not ok 240 name.0.59
7033 23:46:35.401073 # ok 241 write_default.0.59
7034 23:46:35.401186 # ok 242 write_valid.0.59
7035 23:46:35.404217 # ok 243 write_invalid.0.59
7036 23:46:35.407349 # ok 244 event_missing.0.59
7037 23:46:35.410650 # ok 245 event_spurious.0.59
7038 23:46:35.410741 # ok 246 get_value.0.58
7039 23:46:35.417580 # # 0.58 ADDA_DL_CH1 DL1_CH1 is a writeable boolean but not a Switch
7040 23:46:35.420980 # not ok 247 name.0.58
7041 23:46:35.424225 # ok 248 write_default.0.58
7042 23:46:35.424316 # ok 249 write_valid.0.58
7043 23:46:35.427788 # ok 250 write_invalid.0.58
7044 23:46:35.430498 # ok 251 event_missing.0.58
7045 23:46:35.433886 # ok 252 event_spurious.0.58
7046 23:46:35.433977 # ok 253 get_value.0.57
7047 23:46:35.440714 # # 0.57 I2S5_CH2 DL3_CH2 is a writeable boolean but not a Switch
7048 23:46:35.444037 # not ok 254 name.0.57
7049 23:46:35.444131 # ok 255 write_default.0.57
7050 23:46:35.447547 # ok 256 write_valid.0.57
7051 23:46:35.450544 # ok 257 write_invalid.0.57
7052 23:46:35.454316 # ok 258 event_missing.0.57
7053 23:46:35.454407 # ok 259 event_spurious.0.57
7054 23:46:35.457609 # ok 260 get_value.0.56
7055 23:46:35.464238 # # 0.56 I2S5_CH2 DL2_CH2 is a writeable boolean but not a Switch
7056 23:46:35.464333 # not ok 261 name.0.56
7057 23:46:35.467533 # ok 262 write_default.0.56
7058 23:46:35.470503 # ok 263 write_valid.0.56
7059 23:46:35.474201 # ok 264 write_invalid.0.56
7060 23:46:35.474294 # ok 265 event_missing.0.56
7061 23:46:35.477187 # ok 266 event_spurious.0.56
7062 23:46:35.480322 # ok 267 get_value.0.55
7063 23:46:35.487025 # # 0.55 I2S5_CH2 DL1_CH2 is a writeable boolean but not a Switch
7064 23:46:35.487121 # not ok 268 name.0.55
7065 23:46:35.490728 # ok 269 write_default.0.55
7066 23:46:35.493932 # ok 270 write_valid.0.55
7067 23:46:35.494032 # ok 271 write_invalid.0.55
7068 23:46:35.497339 # ok 272 event_missing.0.55
7069 23:46:35.500798 # ok 273 event_spurious.0.55
7070 23:46:35.503630 # ok 274 get_value.0.54
7071 23:46:35.506951 # # 0.54 I2S5_CH1 DL3_CH1 is a writeable boolean but not a Switch
7072 23:46:35.510762 # not ok 275 name.0.54
7073 23:46:35.513830 # ok 276 write_default.0.54
7074 23:46:35.513948 # ok 277 write_valid.0.54
7075 23:46:35.517293 # ok 278 write_invalid.0.54
7076 23:46:35.520679 # ok 279 event_missing.0.54
7077 23:46:35.523563 # ok 280 event_spurious.0.54
7078 23:46:35.523681 # ok 281 get_value.0.53
7079 23:46:35.530430 # # 0.53 I2S5_CH1 DL2_CH1 is a writeable boolean but not a Switch
7080 23:46:35.533780 # not ok 282 name.0.53
7081 23:46:35.537164 # ok 283 write_default.0.53
7082 23:46:35.537256 # ok 284 write_valid.0.53
7083 23:46:35.540041 # ok 285 write_invalid.0.53
7084 23:46:35.543364 # ok 286 event_missing.0.53
7085 23:46:35.547015 # ok 287 event_spurious.0.53
7086 23:46:35.547112 # ok 288 get_value.0.52
7087 23:46:35.553276 # # 0.52 I2S5_CH1 DL1_CH1 is a writeable boolean but not a Switch
7088 23:46:35.556726 # not ok 289 name.0.52
7089 23:46:35.559938 # ok 290 write_default.0.52
7090 23:46:35.563425 # ok 291 write_valid.0.52
7091 23:46:35.563543 # ok 292 write_invalid.0.52
7092 23:46:35.566915 # ok 293 event_missing.0.52
7093 23:46:35.570229 # ok 294 event_spurious.0.52
7094 23:46:35.573504 # ok 295 get_value.0.51
7095 23:46:35.580069 # # 0.51 I2S3_CH2 DL3_CH2 is a writeable boolean but not a Switch
7096 23:46:35.580161 # not ok 296 name.0.51
7097 23:46:35.583358 # ok 297 write_default.0.51
7098 23:46:35.586993 # ok 298 write_valid.0.51
7099 23:46:35.590145 # ok 299 write_invalid.0.51
7100 23:46:35.590235 # ok 300 event_missing.0.51
7101 23:46:35.593707 # ok 301 event_spurious.0.51
7102 23:46:35.597032 # ok 302 get_value.0.50
7103 23:46:35.603809 # # 0.50 I2S3_CH2 DL2_CH2 is a writeable boolean but not a Switch
7104 23:46:35.603903 # not ok 303 name.0.50
7105 23:46:35.607232 # ok 304 write_default.0.50
7106 23:46:35.610011 # ok 305 write_valid.0.50
7107 23:46:35.613646 # ok 306 write_invalid.0.50
7108 23:46:35.613737 # ok 307 event_missing.0.50
7109 23:46:35.617372 # ok 308 event_spurious.0.50
7110 23:46:35.621499 # ok 309 get_value.0.49
7111 23:46:35.626757 # # 0.49 I2S3_CH2 DL1_CH2 is a writeable boolean but not a Switch
7112 23:46:35.626851 # not ok 310 name.0.49
7113 23:46:35.630031 # ok 311 write_default.0.49
7114 23:46:35.633501 # ok 312 write_valid.0.49
7115 23:46:35.633593 # ok 313 write_invalid.0.49
7116 23:46:35.636881 # ok 314 event_missing.0.49
7117 23:46:35.639707 # ok 315 event_spurious.0.49
7118 23:46:35.643180 # ok 316 get_value.0.48
7119 23:46:35.650086 # # 0.48 I2S3_CH1 DL3_CH1 is a writeable boolean but not a Switch
7120 23:46:35.650178 # not ok 317 name.0.48
7121 23:46:35.653380 # ok 318 write_default.0.48
7122 23:46:35.656392 # ok 319 write_valid.0.48
7123 23:46:35.660195 # ok 320 write_invalid.0.48
7124 23:46:35.660287 # ok 321 event_missing.0.48
7125 23:46:35.663348 # ok 322 event_spurious.0.48
7126 23:46:35.666692 # ok 323 get_value.0.47
7127 23:46:35.669658 # # 0.47 I2S3_CH1 DL2_CH1 is a writeable boolean but not a Switch
7128 23:46:35.673250 # not ok 324 name.0.47
7129 23:46:35.676751 # ok 325 write_default.0.47
7130 23:46:35.679925 # ok 326 write_valid.0.47
7131 23:46:35.680018 # ok 327 write_invalid.0.47
7132 23:46:35.683167 # ok 328 event_missing.0.47
7133 23:46:35.686679 # ok 329 event_spurious.0.47
7134 23:46:35.686771 # ok 330 get_value.0.46
7135 23:46:35.693298 # # 0.46 I2S3_CH1 DL1_CH1 is a writeable boolean but not a Switch
7136 23:46:35.696620 # not ok 331 name.0.46
7137 23:46:35.699737 # ok 332 write_default.0.46
7138 23:46:35.699848 # ok 333 write_valid.0.46
7139 23:46:35.702887 # ok 334 write_invalid.0.46
7140 23:46:35.706596 # ok 335 event_missing.0.46
7141 23:46:35.709530 # ok 336 event_spurious.0.46
7142 23:46:35.709636 # ok 337 get_value.0.45
7143 23:46:35.716522 # # 0.45 I2S1_CH2 DL3_CH2 is a writeable boolean but not a Switch
7144 23:46:35.719370 # not ok 338 name.0.45
7145 23:46:35.719517 # ok 339 write_default.0.45
7146 23:46:35.723066 # ok 340 write_valid.0.45
7147 23:46:35.726060 # ok 341 write_invalid.0.45
7148 23:46:35.729640 # ok 342 event_missing.0.45
7149 23:46:35.729722 # ok 343 event_spurious.0.45
7150 23:46:35.733033 # ok 344 get_value.0.44
7151 23:46:35.739550 # # 0.44 I2S1_CH2 DL2_CH2 is a writeable boolean but not a Switch
7152 23:46:35.739648 # not ok 345 name.0.44
7153 23:46:35.742748 # ok 346 write_default.0.44
7154 23:46:35.746325 # ok 347 write_valid.0.44
7155 23:46:35.749846 # ok 348 write_invalid.0.44
7156 23:46:35.749939 # ok 349 event_missing.0.44
7157 23:46:35.752560 # ok 350 event_spurious.0.44
7158 23:46:35.755973 # ok 351 get_value.0.43
7159 23:46:35.762740 # # 0.43 I2S1_CH2 DL1_CH2 is a writeable boolean but not a Switch
7160 23:46:35.762833 # not ok 352 name.0.43
7161 23:46:35.765952 # ok 353 write_default.0.43
7162 23:46:35.769349 # ok 354 write_valid.0.43
7163 23:46:35.769440 # ok 355 write_invalid.0.43
7164 23:46:35.772706 # ok 356 event_missing.0.43
7165 23:46:35.776232 # ok 357 event_spurious.0.43
7166 23:46:35.779095 # ok 358 get_value.0.42
7167 23:46:35.782659 # # 0.42 I2S1_CH1 DL3_CH1 is a writeable boolean but not a Switch
7168 23:46:35.786059 # not ok 359 name.0.42
7169 23:46:35.789312 # ok 360 write_default.0.42
7170 23:46:35.792329 # ok 361 write_valid.0.42
7171 23:46:35.792421 # ok 362 write_invalid.0.42
7172 23:46:35.795690 # ok 363 event_missing.0.42
7173 23:46:35.798968 # ok 364 event_spurious.0.42
7174 23:46:35.799081 # ok 365 get_value.0.41
7175 23:46:35.806149 # # 0.41 I2S1_CH1 DL2_CH1 is a writeable boolean but not a Switch
7176 23:46:35.809220 # not ok 366 name.0.41
7177 23:46:35.812659 # ok 367 write_default.0.41
7178 23:46:35.812750 # ok 368 write_valid.0.41
7179 23:46:35.815898 # ok 369 write_invalid.0.41
7180 23:46:35.818993 # ok 370 event_missing.0.41
7181 23:46:35.822396 # ok 371 event_spurious.0.41
7182 23:46:35.822486 # ok 372 get_value.0.40
7183 23:46:35.829213 # # 0.40 I2S1_CH1 DL1_CH1 is a writeable boolean but not a Switch
7184 23:46:35.831994 # not ok 373 name.0.40
7185 23:46:35.832090 # ok 374 write_default.0.40
7186 23:46:35.835814 # ok 375 write_valid.0.40
7187 23:46:35.838842 # ok 376 write_invalid.0.40
7188 23:46:35.842276 # ok 377 event_missing.0.40
7189 23:46:35.842372 # ok 378 event_spurious.0.40
7190 23:46:35.845799 # ok 379 get_value.0.39
7191 23:46:35.852552 # # 0.39 PCM_2_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7192 23:46:35.855308 # not ok 380 name.0.39
7193 23:46:35.855438 # ok 381 write_default.0.39
7194 23:46:35.858726 # ok 382 write_valid.0.39
7195 23:46:35.862212 # ok 383 write_invalid.0.39
7196 23:46:35.865461 # ok 384 event_missing.0.39
7197 23:46:35.865556 # ok 385 event_spurious.0.39
7198 23:46:35.869127 # ok 386 get_value.0.38
7199 23:46:35.875668 # # 0.38 PCM_2_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7200 23:46:35.875765 # not ok 387 name.0.38
7201 23:46:35.879164 # ok 388 write_default.0.38
7202 23:46:35.882494 # ok 389 write_valid.0.38
7203 23:46:35.885429 # ok 390 write_invalid.0.38
7204 23:46:35.885524 # ok 391 event_missing.0.38
7205 23:46:35.888822 # ok 392 event_spurious.0.38
7206 23:46:35.891894 # ok 393 get_value.0.37
7207 23:46:35.898518 # # 0.37 PCM_2_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7208 23:46:35.898614 # not ok 394 name.0.37
7209 23:46:35.902204 # ok 395 write_default.0.37
7210 23:46:35.905814 # ok 396 write_valid.0.37
7211 23:46:35.909042 # ok 397 write_invalid.0.37
7212 23:46:35.909134 # ok 398 event_missing.0.37
7213 23:46:35.912005 # ok 399 event_spurious.0.37
7214 23:46:35.915368 # ok 400 get_value.0.36
7215 23:46:35.922279 # # 0.36 PCM_2_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7216 23:46:35.922403 # not ok 401 name.0.36
7217 23:46:35.924965 # ok 402 write_default.0.36
7218 23:46:35.928226 # ok 403 write_valid.0.36
7219 23:46:35.931921 # ok 404 write_invalid.0.36
7220 23:46:35.932042 # ok 405 event_missing.0.36
7221 23:46:35.934862 # ok 406 event_spurious.0.36
7222 23:46:35.938346 # ok 407 get_value.0.35
7223 23:46:35.945079 # # 0.35 PCM_2_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7224 23:46:35.945210 # not ok 408 name.0.35
7225 23:46:35.948261 # ok 409 write_default.0.35
7226 23:46:35.951580 # ok 410 write_valid.0.35
7227 23:46:35.955053 # ok 411 write_invalid.0.35
7228 23:46:35.958417 # ok 412 event_missing.0.35
7229 23:46:35.958508 # ok 413 event_spurious.0.35
7230 23:46:35.961888 # ok 414 get_value.0.34
7231 23:46:35.968080 # # 0.34 PCM_1_PB_CH4 DL1_CH1 is a writeable boolean but not a Switch
7232 23:46:35.971366 # not ok 415 name.0.34
7233 23:46:35.971500 # ok 416 write_default.0.34
7234 23:46:35.974600 # ok 417 write_valid.0.34
7235 23:46:35.978209 # ok 418 write_invalid.0.34
7236 23:46:35.981591 # ok 419 event_missing.0.34
7237 23:46:35.984980 # ok 420 event_spurious.0.34
7238 23:46:35.985070 # ok 421 get_value.0.33
7239 23:46:35.991205 # # 0.33 PCM_1_PB_CH2 DL2_CH2 is a writeable boolean but not a Switch
7240 23:46:35.994817 # not ok 422 name.0.33
7241 23:46:35.997907 # ok 423 write_default.0.33
7242 23:46:35.998009 # ok 424 write_valid.0.33
7243 23:46:36.001170 # ok 425 write_invalid.0.33
7244 23:46:36.004416 # ok 426 event_missing.0.33
7245 23:46:36.007820 # ok 427 event_spurious.0.33
7246 23:46:36.007919 # ok 428 get_value.0.32
7247 23:46:36.014580 # # 0.32 PCM_1_PB_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7248 23:46:36.017729 # not ok 429 name.0.32
7249 23:46:36.021221 # ok 430 write_default.0.32
7250 23:46:36.024601 # ok 431 write_valid.0.32
7251 23:46:36.024694 # ok 432 write_invalid.0.32
7252 23:46:36.027992 # ok 433 event_missing.0.32
7253 23:46:36.030901 # ok 434 event_spurious.0.32
7254 23:46:36.034216 # ok 435 get_value.0.31
7255 23:46:36.037666 # # 0.31 PCM_1_PB_CH1 DL2_CH1 is a writeable boolean but not a Switch
7256 23:46:36.040990 # not ok 436 name.0.31
7257 23:46:36.044171 # ok 437 write_default.0.31
7258 23:46:36.047824 # ok 438 write_valid.0.31
7259 23:46:36.047937 # ok 439 write_invalid.0.31
7260 23:46:36.050852 # ok 440 event_missing.0.31
7261 23:46:36.054339 # ok 441 event_spurious.0.31
7262 23:46:36.057330 # ok 442 get_value.0.30
7263 23:46:36.064155 # # 0.30 PCM_1_PB_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7264 23:46:36.064281 # not ok 443 name.0.30
7265 23:46:36.067509 # ok 444 write_default.0.30
7266 23:46:36.070999 # ok 445 write_valid.0.30
7267 23:46:36.074419 # ok 446 write_invalid.0.30
7268 23:46:36.074509 # ok 447 event_missing.0.30
7269 23:46:36.077826 # ok 448 event_spurious.0.30
7270 23:46:36.080974 # ok 449 get_value.0.29
7271 23:46:36.081064 # ok 450 name.0.29
7272 23:46:36.084180 # ok 451 write_default.0.29
7273 23:46:36.087699 # ok 452 write_valid.0.29
7274 23:46:36.091062 # ok 453 write_invalid.0.29
7275 23:46:36.091153 # ok 454 event_missing.0.29
7276 23:46:36.094447 # ok 455 event_spurious.0.29
7277 23:46:36.097407 # ok 456 get_value.0.28
7278 23:46:36.097501 # ok 457 name.0.28
7279 23:46:36.101156 # ok 458 write_default.0.28
7280 23:46:36.104080 # ok 459 write_valid.0.28
7281 23:46:36.107745 # ok 460 write_invalid.0.28
7282 23:46:36.111241 # ok 461 event_missing.0.28
7283 23:46:36.111330 # ok 462 event_spurious.0.28
7284 23:46:36.114471 # ok 463 get_value.0.27
7285 23:46:36.117484 # ok 464 name.0.27
7286 23:46:36.117574 # ok 465 write_default.0.27
7287 23:46:36.120731 # ok 466 write_valid.0.27
7288 23:46:36.124240 # ok 467 write_invalid.0.27
7289 23:46:36.127325 # ok 468 event_missing.0.27
7290 23:46:36.130824 # ok 469 event_spurious.0.27
7291 23:46:36.130915 # ok 470 get_value.0.26
7292 23:46:36.133716 # ok 471 name.0.26
7293 23:46:36.136872 # ok 472 write_default.0.26
7294 23:46:36.136991 # ok 473 write_valid.0.26
7295 23:46:36.140260 # ok 474 write_invalid.0.26
7296 23:46:36.143640 # ok 475 event_missing.0.26
7297 23:46:36.147005 # ok 476 event_spurious.0.26
7298 23:46:36.147120 # ok 477 get_value.0.25
7299 23:46:36.150414 # ok 478 name.0.25
7300 23:46:36.153898 # ok 479 write_default.0.25
7301 23:46:36.153988 # ok 480 write_valid.0.25
7302 23:46:36.157206 # ok 481 write_invalid.0.25
7303 23:46:36.160074 # ok 482 event_missing.0.25
7304 23:46:36.163824 # ok 483 event_spurious.0.25
7305 23:46:36.163949 # ok 484 get_value.0.24
7306 23:46:36.167266 # ok 485 name.0.24
7307 23:46:36.170189 # ok 486 write_default.0.24
7308 23:46:36.173343 # ok 487 write_valid.0.24
7309 23:46:36.173459 # ok 488 write_invalid.0.24
7310 23:46:36.176502 # ok 489 event_missing.0.24
7311 23:46:36.180112 # ok 490 event_spurious.0.24
7312 23:46:36.183346 # ok 491 get_value.0.23
7313 23:46:36.183475 # ok 492 name.0.23
7314 23:46:36.186646 # ok 493 write_default.0.23
7315 23:46:36.190069 # ok 494 write_valid.0.23
7316 23:46:36.193377 # ok 495 write_invalid.0.23
7317 23:46:36.193495 # ok 496 event_missing.0.23
7318 23:46:36.196739 # ok 497 event_spurious.0.23
7319 23:46:36.199703 # ok 498 get_value.0.22
7320 23:46:36.199815 # ok 499 name.0.22
7321 23:46:36.203128 # ok 500 write_default.0.22
7322 23:46:36.206638 # ok 501 write_valid.0.22
7323 23:46:36.209941 # ok 502 write_invalid.0.22
7324 23:46:36.210058 # ok 503 event_missing.0.22
7325 23:46:36.213162 # ok 504 event_spurious.0.22
7326 23:46:36.216335 # ok 505 get_value.0.21
7327 23:46:36.222640 # # 0.21 UL_MONO_1_CH1 ADDA_UL_CH2 is a writeable boolean but not a Switch
7328 23:46:36.226137 # not ok 506 name.0.21
7329 23:46:36.226254 # ok 507 write_default.0.21
7330 23:46:36.229449 # ok 508 write_valid.0.21
7331 23:46:36.232946 # ok 509 write_invalid.0.21
7332 23:46:36.236470 # ok 510 event_missing.0.21
7333 23:46:36.239526 # ok 511 event_spurious.0.21
7334 23:46:36.239639 # ok 512 get_value.0.20
7335 23:46:36.246130 # # 0.20 UL_MONO_1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7336 23:46:36.249521 # not ok 513 name.0.20
7337 23:46:36.252567 # ok 514 write_default.0.20
7338 23:46:36.256134 # ok 515 write_valid.0.20
7339 23:46:36.256251 # ok 516 write_invalid.0.20
7340 23:46:36.259348 # ok 517 event_missing.0.20
7341 23:46:36.262362 # ok 518 event_spurious.0.20
7342 23:46:36.265825 # ok 519 get_value.0.19
7343 23:46:36.272669 # # 0.19 UL4_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7344 23:46:36.272759 # not ok 520 name.0.19
7345 23:46:36.275957 # ok 521 write_default.0.19
7346 23:46:36.279139 # ok 522 write_valid.0.19
7347 23:46:36.279222 # ok 523 write_invalid.0.19
7348 23:46:36.282225 # ok 524 event_missing.0.19
7349 23:46:36.285727 # ok 525 event_spurious.0.19
7350 23:46:36.288835 # ok 526 get_value.0.18
7351 23:46:36.292370 # # 0.18 UL4_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7352 23:46:36.295480 # not ok 527 name.0.18
7353 23:46:36.299042 # ok 528 write_default.0.18
7354 23:46:36.302094 # ok 529 write_valid.0.18
7355 23:46:36.302205 # ok 530 write_invalid.0.18
7356 23:46:36.305284 # ok 531 event_missing.0.18
7357 23:46:36.308562 # ok 532 event_spurious.0.18
7358 23:46:36.312130 # ok 533 get_value.0.17
7359 23:46:36.315588 # # 0.17 UL3_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7360 23:46:36.318800 # not ok 534 name.0.17
7361 23:46:36.321979 # ok 535 write_default.0.17
7362 23:46:36.322098 # ok 536 write_valid.0.17
7363 23:46:36.325395 # ok 537 write_invalid.0.17
7364 23:46:36.328683 # ok 538 event_missing.0.17
7365 23:46:36.332039 # ok 539 event_spurious.0.17
7366 23:46:36.332157 # ok 540 get_value.0.16
7367 23:46:36.338857 # # 0.16 UL3_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7368 23:46:36.341748 # not ok 541 name.0.16
7369 23:46:36.345171 # ok 542 write_default.0.16
7370 23:46:36.345254 # ok 543 write_valid.0.16
7371 23:46:36.348617 # ok 544 write_invalid.0.16
7372 23:46:36.351914 # ok 545 event_missing.0.16
7373 23:46:36.355157 # ok 546 event_spurious.0.16
7374 23:46:36.355247 # ok 547 get_value.0.15
7375 23:46:36.362102 # # 0.15 UL3_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7376 23:46:36.365374 # not ok 548 name.0.15
7377 23:46:36.365461 # ok 549 write_default.0.15
7378 23:46:36.368713 # ok 550 write_valid.0.15
7379 23:46:36.371845 # ok 551 write_invalid.0.15
7380 23:46:36.375035 # ok 552 event_missing.0.15
7381 23:46:36.375116 # ok 553 event_spurious.0.15
7382 23:46:36.378425 # ok 554 get_value.0.14
7383 23:46:36.385070 # # 0.14 UL3_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7384 23:46:36.385157 # not ok 555 name.0.14
7385 23:46:36.388511 # ok 556 write_default.0.14
7386 23:46:36.391900 # ok 557 write_valid.0.14
7387 23:46:36.395335 # ok 558 write_invalid.0.14
7388 23:46:36.395445 # ok 559 event_missing.0.14
7389 23:46:36.398354 # ok 560 event_spurious.0.14
7390 23:46:36.401705 # ok 561 get_value.0.13
7391 23:46:36.408057 # # 0.13 UL2_CH2 I2S2_CH2 is a writeable boolean but not a Switch
7392 23:46:36.408179 # not ok 562 name.0.13
7393 23:46:36.411498 # ok 563 write_default.0.13
7394 23:46:36.414720 # ok 564 write_valid.0.13
7395 23:46:36.418029 # ok 565 write_invalid.0.13
7396 23:46:36.418121 # ok 566 event_missing.0.13
7397 23:46:36.421475 # ok 567 event_spurious.0.13
7398 23:46:36.424686 # ok 568 get_value.0.12
7399 23:46:36.431085 # # 0.12 UL2_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7400 23:46:36.431173 # not ok 569 name.0.12
7401 23:46:36.434604 # ok 570 write_default.0.12
7402 23:46:36.438022 # ok 571 write_valid.0.12
7403 23:46:36.438112 # ok 572 write_invalid.0.12
7404 23:46:36.441700 # ok 573 event_missing.0.12
7405 23:46:36.444872 # ok 574 event_spurious.0.12
7406 23:46:36.448309 # ok 575 get_value.0.11
7407 23:46:36.451103 # # 0.11 UL2_CH1 I2S2_CH1 is a writeable boolean but not a Switch
7408 23:46:36.454592 # not ok 576 name.0.11
7409 23:46:36.467193 # ok 577 write_default.0.11
7410 23:46:36.467339 # ok 578 write_valid.0.11
7411 23:46:36.467448 # ok 579 write_invalid.0.11
7412 23:46:36.467518 # ok 580 event_missing.0.11
7413 23:46:36.468042 # ok 581 event_spurious.0.11
7414 23:46:36.468140 # ok 582 get_value.0.10
7415 23:46:36.474446 # # 0.10 UL2_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7416 23:46:36.477811 # not ok 583 name.0.10
7417 23:46:36.481312 # ok 584 write_default.0.10
7418 23:46:36.481431 # ok 585 write_valid.0.10
7419 23:46:36.484731 # ok 586 write_invalid.0.10
7420 23:46:36.487826 # ok 587 event_missing.0.10
7421 23:46:36.490947 # ok 588 event_spurious.0.10
7422 23:46:36.491038 # ok 589 get_value.0.9
7423 23:46:36.497624 # # 0.9 UL1_CH2 I2S0_CH2 is a writeable boolean but not a Switch
7424 23:46:36.501314 # not ok 590 name.0.9
7425 23:46:36.501405 # ok 591 write_default.0.9
7426 23:46:36.504184 # ok 592 write_valid.0.9
7427 23:46:36.507592 # ok 593 write_invalid.0.9
7428 23:46:36.507677 # ok 594 event_missing.0.9
7429 23:46:36.511029 # ok 595 event_spurious.0.9
7430 23:46:36.514249 # ok 596 get_value.0.8
7431 23:46:36.520884 # # 0.8 UL1_CH2 ADDA_UL_CH2 is a writeable boolean but not a Switch
7432 23:46:36.520974 # not ok 597 name.0.8
7433 23:46:36.524321 # ok 598 write_default.0.8
7434 23:46:36.527527 # ok 599 write_valid.0.8
7435 23:46:36.527638 # ok 600 write_invalid.0.8
7436 23:46:36.530995 # ok 601 event_missing.0.8
7437 23:46:36.533961 # ok 602 event_spurious.0.8
7438 23:46:36.537350 # ok 603 get_value.0.7
7439 23:46:36.541012 # # 0.7 UL1_CH1 I2S0_CH1 is a writeable boolean but not a Switch
7440 23:46:36.544148 # not ok 604 name.0.7
7441 23:46:36.547567 # ok 605 write_default.0.7
7442 23:46:36.547650 # ok 606 write_valid.0.7
7443 23:46:36.550464 # ok 607 write_invalid.0.7
7444 23:46:36.554055 # ok 608 event_missing.0.7
7445 23:46:36.557375 # ok 609 event_spurious.0.7
7446 23:46:36.557466 # ok 610 get_value.0.6
7447 23:46:36.564486 # # 0.6 UL1_CH1 ADDA_UL_CH1 is a writeable boolean but not a Switch
7448 23:46:36.567055 # not ok 611 name.0.6
7449 23:46:36.567172 # ok 612 write_default.0.6
7450 23:46:36.570616 # ok 613 write_valid.0.6
7451 23:46:36.573858 # ok 614 write_invalid.0.6
7452 23:46:36.573977 # ok 615 event_missing.0.6
7453 23:46:36.577340 # ok 616 event_spurious.0.6
7454 23:46:36.580600 # ok 617 get_value.0.5
7455 23:46:36.580717 # ok 618 name.0.5
7456 23:46:36.583965 # ok 619 write_default.0.5
7457 23:46:36.587362 # # No event generated for MTKAIF_DMIC
7458 23:46:36.590443 # # No event generated for MTKAIF_DMIC
7459 23:46:36.593486 # ok 620 write_valid.0.5
7460 23:46:36.597033 # ok 621 write_invalid.0.5
7461 23:46:36.597142 # not ok 622 event_missing.0.5
7462 23:46:36.600773 # ok 623 event_spurious.0.5
7463 23:46:36.603943 # ok 624 get_value.0.4
7464 23:46:36.604026 # ok 625 name.0.4
7465 23:46:36.606860 # ok 626 write_default.0.4
7466 23:46:36.610433 # # No event generated for I2S5_HD_Mux
7467 23:46:36.613848 # # No event generated for I2S5_HD_Mux
7468 23:46:36.616605 # ok 627 write_valid.0.4
7469 23:46:36.620256 # ok 628 write_invalid.0.4
7470 23:46:36.620346 # not ok 629 event_missing.0.4
7471 23:46:36.623254 # ok 630 event_spurious.0.4
7472 23:46:36.626558 # ok 631 get_value.0.3
7473 23:46:36.626660 # ok 632 name.0.3
7474 23:46:36.629941 # ok 633 write_default.0.3
7475 23:46:36.633690 # # No event generated for I2S3_HD_Mux
7476 23:46:36.636740 # # No event generated for I2S3_HD_Mux
7477 23:46:36.639758 # ok 634 write_valid.0.3
7478 23:46:36.643204 # ok 635 write_invalid.0.3
7479 23:46:36.643291 # not ok 636 event_missing.0.3
7480 23:46:36.646681 # ok 637 event_spurious.0.3
7481 23:46:36.649778 # ok 638 get_value.0.2
7482 23:46:36.649861 # ok 639 name.0.2
7483 23:46:36.653306 # ok 640 write_default.0.2
7484 23:46:36.656828 # # No event generated for I2S2_HD_Mux
7485 23:46:36.659657 # # No event generated for I2S2_HD_Mux
7486 23:46:36.663065 # ok 641 write_valid.0.2
7487 23:46:36.666533 # ok 642 write_invalid.0.2
7488 23:46:36.666613 # not ok 643 event_missing.0.2
7489 23:46:36.669950 # ok 644 event_spurious.0.2
7490 23:46:36.673426 # ok 645 get_value.0.1
7491 23:46:36.673503 # ok 646 name.0.1
7492 23:46:36.676370 # ok 647 write_default.0.1
7493 23:46:36.679803 # # No event generated for I2S1_HD_Mux
7494 23:46:36.683243 # # No event generated for I2S1_HD_Mux
7495 23:46:36.686570 # ok 648 write_valid.0.1
7496 23:46:36.690005 # ok 649 write_invalid.0.1
7497 23:46:36.690122 # not ok 650 event_missing.0.1
7498 23:46:36.693236 # ok 651 event_spurious.0.1
7499 23:46:36.696333 # ok 652 get_value.0.0
7500 23:46:36.696450 # ok 653 name.0.0
7501 23:46:36.699639 # ok 654 write_default.0.0
7502 23:46:36.702639 # # No event generated for I2S0_HD_Mux
7503 23:46:36.706455 # # No event generated for I2S0_HD_Mux
7504 23:46:36.709252 # ok 655 write_valid.0.0
7505 23:46:36.712826 # ok 656 write_invalid.0.0
7506 23:46:36.716430 # not ok 657 event_missing.0.0
7507 23:46:36.716546 # ok 658 event_spurious.0.0
7508 23:46:36.722718 # # Totals: pass:568 fail:87 xfail:0 xpass:0 skip:3 error:0
7509 23:46:36.726015 ok 1 selftests: alsa: mixer-test
7510 23:46:38.242369 alsa_mixer-test_get_value_0_93 pass
7511 23:46:38.245911 alsa_mixer-test_name_0_93 pass
7512 23:46:38.248820 alsa_mixer-test_write_default_0_93 pass
7513 23:46:38.252286 alsa_mixer-test_write_valid_0_93 pass
7514 23:46:38.259095 alsa_mixer-test_write_invalid_0_93 pass
7515 23:46:38.261972 alsa_mixer-test_event_missing_0_93 pass
7516 23:46:38.265218 alsa_mixer-test_event_spurious_0_93 pass
7517 23:46:38.269084 alsa_mixer-test_get_value_0_92 pass
7518 23:46:38.272445 alsa_mixer-test_name_0_92 pass
7519 23:46:38.275144 alsa_mixer-test_write_default_0_92 pass
7520 23:46:38.278861 alsa_mixer-test_write_valid_0_92 pass
7521 23:46:38.282176 alsa_mixer-test_write_invalid_0_92 pass
7522 23:46:38.285164 alsa_mixer-test_event_missing_0_92 pass
7523 23:46:38.288591 alsa_mixer-test_event_spurious_0_92 pass
7524 23:46:38.291928 alsa_mixer-test_get_value_0_91 pass
7525 23:46:38.295052 alsa_mixer-test_name_0_91 pass
7526 23:46:38.298617 alsa_mixer-test_write_default_0_91 pass
7527 23:46:38.302088 alsa_mixer-test_write_valid_0_91 pass
7528 23:46:38.305487 alsa_mixer-test_write_invalid_0_91 pass
7529 23:46:38.308545 alsa_mixer-test_event_missing_0_91 pass
7530 23:46:38.311731 alsa_mixer-test_event_spurious_0_91 pass
7531 23:46:38.315413 alsa_mixer-test_get_value_0_90 pass
7532 23:46:38.318331 alsa_mixer-test_name_0_90 pass
7533 23:46:38.321858 alsa_mixer-test_write_default_0_90 pass
7534 23:46:38.325337 alsa_mixer-test_write_valid_0_90 pass
7535 23:46:38.331740 alsa_mixer-test_write_invalid_0_90 pass
7536 23:46:38.335092 alsa_mixer-test_event_missing_0_90 pass
7537 23:46:38.338588 alsa_mixer-test_event_spurious_0_90 pass
7538 23:46:38.342149 alsa_mixer-test_get_value_0_89 pass
7539 23:46:38.344930 alsa_mixer-test_name_0_89 pass
7540 23:46:38.348451 alsa_mixer-test_write_default_0_89 pass
7541 23:46:38.351419 alsa_mixer-test_write_valid_0_89 pass
7542 23:46:38.354822 alsa_mixer-test_write_invalid_0_89 pass
7543 23:46:38.358117 alsa_mixer-test_event_missing_0_89 pass
7544 23:46:38.361677 alsa_mixer-test_event_spurious_0_89 pass
7545 23:46:38.365139 alsa_mixer-test_get_value_0_88 pass
7546 23:46:38.368522 alsa_mixer-test_name_0_88 pass
7547 23:46:38.371486 alsa_mixer-test_write_default_0_88 pass
7548 23:46:38.374910 alsa_mixer-test_write_valid_0_88 fail
7549 23:46:38.378055 alsa_mixer-test_write_invalid_0_88 pass
7550 23:46:38.381525 alsa_mixer-test_event_missing_0_88 pass
7551 23:46:38.387913 alsa_mixer-test_event_spurious_0_88 fail
7552 23:46:38.391346 alsa_mixer-test_get_value_0_87 pass
7553 23:46:38.391472 alsa_mixer-test_name_0_87 pass
7554 23:46:38.398185 alsa_mixer-test_write_default_0_87 pass
7555 23:46:38.401596 alsa_mixer-test_write_valid_0_87 pass
7556 23:46:38.404918 alsa_mixer-test_write_invalid_0_87 pass
7557 23:46:38.407918 alsa_mixer-test_event_missing_0_87 pass
7558 23:46:38.411734 alsa_mixer-test_event_spurious_0_87 pass
7559 23:46:38.414706 alsa_mixer-test_get_value_0_86 pass
7560 23:46:38.418027 alsa_mixer-test_name_0_86 pass
7561 23:46:38.421110 alsa_mixer-test_write_default_0_86 pass
7562 23:46:38.424834 alsa_mixer-test_write_valid_0_86 fail
7563 23:46:38.428022 alsa_mixer-test_write_invalid_0_86 pass
7564 23:46:38.431291 alsa_mixer-test_event_missing_0_86 pass
7565 23:46:38.434603 alsa_mixer-test_event_spurious_0_86 pass
7566 23:46:38.437834 alsa_mixer-test_get_value_0_85 pass
7567 23:46:38.441195 alsa_mixer-test_name_0_85 pass
7568 23:46:38.444556 alsa_mixer-test_write_default_0_85 pass
7569 23:46:38.448144 alsa_mixer-test_write_valid_0_85 fail
7570 23:46:38.451327 alsa_mixer-test_write_invalid_0_85 pass
7571 23:46:38.457874 alsa_mixer-test_event_missing_0_85 pass
7572 23:46:38.461181 alsa_mixer-test_event_spurious_0_85 pass
7573 23:46:38.464599 alsa_mixer-test_get_value_0_84 pass
7574 23:46:38.468084 alsa_mixer-test_name_0_84 pass
7575 23:46:38.471109 alsa_mixer-test_write_default_0_84 pass
7576 23:46:38.474408 alsa_mixer-test_write_valid_0_84 pass
7577 23:46:38.477868 alsa_mixer-test_write_invalid_0_84 pass
7578 23:46:38.480867 alsa_mixer-test_event_missing_0_84 pass
7579 23:46:38.484611 alsa_mixer-test_event_spurious_0_84 pass
7580 23:46:38.487625 alsa_mixer-test_get_value_0_83 pass
7581 23:46:38.490833 alsa_mixer-test_name_0_83 pass
7582 23:46:38.494415 alsa_mixer-test_write_default_0_83 pass
7583 23:46:38.497349 alsa_mixer-test_write_valid_0_83 pass
7584 23:46:38.500844 alsa_mixer-test_write_invalid_0_83 pass
7585 23:46:38.504019 alsa_mixer-test_event_missing_0_83 pass
7586 23:46:38.507353 alsa_mixer-test_event_spurious_0_83 pass
7587 23:46:38.510771 alsa_mixer-test_get_value_0_82 pass
7588 23:46:38.514359 alsa_mixer-test_name_0_82 pass
7589 23:46:38.517620 alsa_mixer-test_write_default_0_82 skip
7590 23:46:38.520452 alsa_mixer-test_write_valid_0_82 skip
7591 23:46:38.527355 alsa_mixer-test_write_invalid_0_82 skip
7592 23:46:38.530728 alsa_mixer-test_event_missing_0_82 pass
7593 23:46:38.533945 alsa_mixer-test_event_spurious_0_82 pass
7594 23:46:38.537391 alsa_mixer-test_get_value_0_81 pass
7595 23:46:38.540706 alsa_mixer-test_name_0_81 pass
7596 23:46:38.543520 alsa_mixer-test_write_default_0_81 pass
7597 23:46:38.547121 alsa_mixer-test_write_valid_0_81 pass
7598 23:46:38.550893 alsa_mixer-test_write_invalid_0_81 fail
7599 23:46:38.553793 alsa_mixer-test_event_missing_0_81 fail
7600 23:46:38.557195 alsa_mixer-test_event_spurious_0_81 pass
7601 23:46:38.560771 alsa_mixer-test_get_value_0_80 pass
7602 23:46:38.564036 alsa_mixer-test_name_0_80 pass
7603 23:46:38.567369 alsa_mixer-test_write_default_0_80 pass
7604 23:46:38.570642 alsa_mixer-test_write_valid_0_80 pass
7605 23:46:38.573637 alsa_mixer-test_write_invalid_0_80 pass
7606 23:46:38.576997 alsa_mixer-test_event_missing_0_80 pass
7607 23:46:38.583987 alsa_mixer-test_event_spurious_0_80 pass
7608 23:46:38.587335 alsa_mixer-test_get_value_0_79 fail
7609 23:46:38.587435 alsa_mixer-test_name_0_79 pass
7610 23:46:38.590409 alsa_mixer-test_write_default_0_79 fail
7611 23:46:38.596861 alsa_mixer-test_write_valid_0_79 fail
7612 23:46:38.600595 alsa_mixer-test_write_invalid_0_79 fail
7613 23:46:38.604088 alsa_mixer-test_event_missing_0_79 pass
7614 23:46:38.607000 alsa_mixer-test_event_spurious_0_79 pass
7615 23:46:38.610277 alsa_mixer-test_get_value_0_78 fail
7616 23:46:38.613615 alsa_mixer-test_name_0_78 pass
7617 23:46:38.617087 alsa_mixer-test_write_default_0_78 fail
7618 23:46:38.620330 alsa_mixer-test_write_valid_0_78 fail
7619 23:46:38.623680 alsa_mixer-test_write_invalid_0_78 fail
7620 23:46:38.627180 alsa_mixer-test_event_missing_0_78 pass
7621 23:46:38.630111 alsa_mixer-test_event_spurious_0_78 pass
7622 23:46:38.633620 alsa_mixer-test_get_value_0_77 fail
7623 23:46:38.637229 alsa_mixer-test_name_0_77 pass
7624 23:46:38.640498 alsa_mixer-test_write_default_0_77 fail
7625 23:46:38.643341 alsa_mixer-test_write_valid_0_77 fail
7626 23:46:38.646664 alsa_mixer-test_write_invalid_0_77 fail
7627 23:46:38.649935 alsa_mixer-test_event_missing_0_77 pass
7628 23:46:38.653680 alsa_mixer-test_event_spurious_0_77 pass
7629 23:46:38.656896 alsa_mixer-test_get_value_0_76 pass
7630 23:46:38.660116 alsa_mixer-test_name_0_76 fail
7631 23:46:38.663261 alsa_mixer-test_write_default_0_76 pass
7632 23:46:38.666679 alsa_mixer-test_write_valid_0_76 pass
7633 23:46:38.670208 alsa_mixer-test_write_invalid_0_76 pass
7634 23:46:38.672970 alsa_mixer-test_event_missing_0_76 pass
7635 23:46:38.676858 alsa_mixer-test_event_spurious_0_76 pass
7636 23:46:38.679787 alsa_mixer-test_get_value_0_75 pass
7637 23:46:38.683210 alsa_mixer-test_name_0_75 fail
7638 23:46:38.686596 alsa_mixer-test_write_default_0_75 pass
7639 23:46:38.690056 alsa_mixer-test_write_valid_0_75 pass
7640 23:46:38.693499 alsa_mixer-test_write_invalid_0_75 pass
7641 23:46:38.696383 alsa_mixer-test_event_missing_0_75 pass
7642 23:46:38.699827 alsa_mixer-test_event_spurious_0_75 pass
7643 23:46:38.703185 alsa_mixer-test_get_value_0_74 pass
7644 23:46:38.706368 alsa_mixer-test_name_0_74 fail
7645 23:46:38.709967 alsa_mixer-test_write_default_0_74 pass
7646 23:46:38.713532 alsa_mixer-test_write_valid_0_74 pass
7647 23:46:38.716413 alsa_mixer-test_write_invalid_0_74 pass
7648 23:46:38.720160 alsa_mixer-test_event_missing_0_74 pass
7649 23:46:38.723455 alsa_mixer-test_event_spurious_0_74 pass
7650 23:46:38.726910 alsa_mixer-test_get_value_0_73 pass
7651 23:46:38.729828 alsa_mixer-test_name_0_73 fail
7652 23:46:38.733422 alsa_mixer-test_write_default_0_73 pass
7653 23:46:38.736767 alsa_mixer-test_write_valid_0_73 pass
7654 23:46:38.739766 alsa_mixer-test_write_invalid_0_73 pass
7655 23:46:38.743138 alsa_mixer-test_event_missing_0_73 pass
7656 23:46:38.749544 alsa_mixer-test_event_spurious_0_73 pass
7657 23:46:38.753091 alsa_mixer-test_get_value_0_72 pass
7658 23:46:38.753184 alsa_mixer-test_name_0_72 fail
7659 23:46:38.760069 alsa_mixer-test_write_default_0_72 pass
7660 23:46:38.763138 alsa_mixer-test_write_valid_0_72 pass
7661 23:46:38.766404 alsa_mixer-test_write_invalid_0_72 pass
7662 23:46:38.769720 alsa_mixer-test_event_missing_0_72 pass
7663 23:46:38.773135 alsa_mixer-test_event_spurious_0_72 pass
7664 23:46:38.776460 alsa_mixer-test_get_value_0_71 pass
7665 23:46:38.779740 alsa_mixer-test_name_0_71 fail
7666 23:46:38.782859 alsa_mixer-test_write_default_0_71 pass
7667 23:46:38.786213 alsa_mixer-test_write_valid_0_71 pass
7668 23:46:38.789633 alsa_mixer-test_write_invalid_0_71 pass
7669 23:46:38.793063 alsa_mixer-test_event_missing_0_71 pass
7670 23:46:38.796494 alsa_mixer-test_event_spurious_0_71 pass
7671 23:46:38.799383 alsa_mixer-test_get_value_0_70 pass
7672 23:46:38.802814 alsa_mixer-test_name_0_70 fail
7673 23:46:38.806255 alsa_mixer-test_write_default_0_70 pass
7674 23:46:38.809618 alsa_mixer-test_write_valid_0_70 pass
7675 23:46:38.816420 alsa_mixer-test_write_invalid_0_70 pass
7676 23:46:38.819334 alsa_mixer-test_event_missing_0_70 pass
7677 23:46:38.822566 alsa_mixer-test_event_spurious_0_70 pass
7678 23:46:38.825995 alsa_mixer-test_get_value_0_69 pass
7679 23:46:38.829427 alsa_mixer-test_name_0_69 fail
7680 23:46:38.832962 alsa_mixer-test_write_default_0_69 pass
7681 23:46:38.835981 alsa_mixer-test_write_valid_0_69 pass
7682 23:46:38.839444 alsa_mixer-test_write_invalid_0_69 pass
7683 23:46:38.842954 alsa_mixer-test_event_missing_0_69 pass
7684 23:46:38.845748 alsa_mixer-test_event_spurious_0_69 pass
7685 23:46:38.849337 alsa_mixer-test_get_value_0_68 pass
7686 23:46:38.852650 alsa_mixer-test_name_0_68 fail
7687 23:46:38.855696 alsa_mixer-test_write_default_0_68 pass
7688 23:46:38.859186 alsa_mixer-test_write_valid_0_68 pass
7689 23:46:38.862377 alsa_mixer-test_write_invalid_0_68 pass
7690 23:46:38.865933 alsa_mixer-test_event_missing_0_68 pass
7691 23:46:38.872433 alsa_mixer-test_event_spurious_0_68 pass
7692 23:46:38.875730 alsa_mixer-test_get_value_0_67 pass
7693 23:46:38.875822 alsa_mixer-test_name_0_67 fail
7694 23:46:38.882677 alsa_mixer-test_write_default_0_67 pass
7695 23:46:38.886108 alsa_mixer-test_write_valid_0_67 pass
7696 23:46:38.888835 alsa_mixer-test_write_invalid_0_67 pass
7697 23:46:38.892359 alsa_mixer-test_event_missing_0_67 pass
7698 23:46:38.896070 alsa_mixer-test_event_spurious_0_67 pass
7699 23:46:38.898973 alsa_mixer-test_get_value_0_66 pass
7700 23:46:38.902377 alsa_mixer-test_name_0_66 fail
7701 23:46:38.905358 alsa_mixer-test_write_default_0_66 pass
7702 23:46:38.909233 alsa_mixer-test_write_valid_0_66 pass
7703 23:46:38.912227 alsa_mixer-test_write_invalid_0_66 pass
7704 23:46:38.915420 alsa_mixer-test_event_missing_0_66 pass
7705 23:46:38.919007 alsa_mixer-test_event_spurious_0_66 pass
7706 23:46:38.922153 alsa_mixer-test_get_value_0_65 pass
7707 23:46:38.925559 alsa_mixer-test_name_0_65 fail
7708 23:46:38.928944 alsa_mixer-test_write_default_0_65 pass
7709 23:46:38.932453 alsa_mixer-test_write_valid_0_65 pass
7710 23:46:38.935223 alsa_mixer-test_write_invalid_0_65 pass
7711 23:46:38.938966 alsa_mixer-test_event_missing_0_65 pass
7712 23:46:38.941869 alsa_mixer-test_event_spurious_0_65 pass
7713 23:46:38.945395 alsa_mixer-test_get_value_0_64 pass
7714 23:46:38.948509 alsa_mixer-test_name_0_64 fail
7715 23:46:38.952277 alsa_mixer-test_write_default_0_64 pass
7716 23:46:38.955187 alsa_mixer-test_write_valid_0_64 pass
7717 23:46:38.958789 alsa_mixer-test_write_invalid_0_64 pass
7718 23:46:38.965101 alsa_mixer-test_event_missing_0_64 pass
7719 23:46:38.968597 alsa_mixer-test_event_spurious_0_64 pass
7720 23:46:38.972139 alsa_mixer-test_get_value_0_63 pass
7721 23:46:38.972230 alsa_mixer-test_name_0_63 fail
7722 23:46:38.975492 alsa_mixer-test_write_default_0_63 pass
7723 23:46:38.981916 alsa_mixer-test_write_valid_0_63 pass
7724 23:46:38.985302 alsa_mixer-test_write_invalid_0_63 pass
7725 23:46:38.988795 alsa_mixer-test_event_missing_0_63 pass
7726 23:46:38.991631 alsa_mixer-test_event_spurious_0_63 pass
7727 23:46:38.995274 alsa_mixer-test_get_value_0_62 pass
7728 23:46:38.998573 alsa_mixer-test_name_0_62 fail
7729 23:46:39.002046 alsa_mixer-test_write_default_0_62 pass
7730 23:46:39.005448 alsa_mixer-test_write_valid_0_62 pass
7731 23:46:39.008610 alsa_mixer-test_write_invalid_0_62 pass
7732 23:46:39.011762 alsa_mixer-test_event_missing_0_62 pass
7733 23:46:39.015206 alsa_mixer-test_event_spurious_0_62 pass
7734 23:46:39.018620 alsa_mixer-test_get_value_0_61 pass
7735 23:46:39.021619 alsa_mixer-test_name_0_61 fail
7736 23:46:39.025061 alsa_mixer-test_write_default_0_61 pass
7737 23:46:39.028462 alsa_mixer-test_write_valid_0_61 pass
7738 23:46:39.031717 alsa_mixer-test_write_invalid_0_61 pass
7739 23:46:39.034957 alsa_mixer-test_event_missing_0_61 pass
7740 23:46:39.041470 alsa_mixer-test_event_spurious_0_61 pass
7741 23:46:39.044810 alsa_mixer-test_get_value_0_60 pass
7742 23:46:39.048065 alsa_mixer-test_name_0_60 fail
7743 23:46:39.051706 alsa_mixer-test_write_default_0_60 pass
7744 23:46:39.055069 alsa_mixer-test_write_valid_0_60 pass
7745 23:46:39.058239 alsa_mixer-test_write_invalid_0_60 pass
7746 23:46:39.061229 alsa_mixer-test_event_missing_0_60 pass
7747 23:46:39.064566 alsa_mixer-test_event_spurious_0_60 pass
7748 23:46:39.067923 alsa_mixer-test_get_value_0_59 pass
7749 23:46:39.071398 alsa_mixer-test_name_0_59 fail
7750 23:46:39.074788 alsa_mixer-test_write_default_0_59 pass
7751 23:46:39.078203 alsa_mixer-test_write_valid_0_59 pass
7752 23:46:39.081500 alsa_mixer-test_write_invalid_0_59 pass
7753 23:46:39.085099 alsa_mixer-test_event_missing_0_59 pass
7754 23:46:39.088382 alsa_mixer-test_event_spurious_0_59 pass
7755 23:46:39.091172 alsa_mixer-test_get_value_0_58 pass
7756 23:46:39.094662 alsa_mixer-test_name_0_58 fail
7757 23:46:39.097931 alsa_mixer-test_write_default_0_58 pass
7758 23:46:39.100912 alsa_mixer-test_write_valid_0_58 pass
7759 23:46:39.104408 alsa_mixer-test_write_invalid_0_58 pass
7760 23:46:39.107818 alsa_mixer-test_event_missing_0_58 pass
7761 23:46:39.111070 alsa_mixer-test_event_spurious_0_58 pass
7762 23:46:39.114593 alsa_mixer-test_get_value_0_57 pass
7763 23:46:39.117509 alsa_mixer-test_name_0_57 fail
7764 23:46:39.121297 alsa_mixer-test_write_default_0_57 pass
7765 23:46:39.124622 alsa_mixer-test_write_valid_0_57 pass
7766 23:46:39.127615 alsa_mixer-test_write_invalid_0_57 pass
7767 23:46:39.130904 alsa_mixer-test_event_missing_0_57 pass
7768 23:46:39.137849 alsa_mixer-test_event_spurious_0_57 pass
7769 23:46:39.141077 alsa_mixer-test_get_value_0_56 pass
7770 23:46:39.141170 alsa_mixer-test_name_0_56 fail
7771 23:46:39.144196 alsa_mixer-test_write_default_0_56 pass
7772 23:46:39.147628 alsa_mixer-test_write_valid_0_56 pass
7773 23:46:39.154615 alsa_mixer-test_write_invalid_0_56 pass
7774 23:46:39.157357 alsa_mixer-test_event_missing_0_56 pass
7775 23:46:39.160678 alsa_mixer-test_event_spurious_0_56 pass
7776 23:46:39.163991 alsa_mixer-test_get_value_0_55 pass
7777 23:46:39.167366 alsa_mixer-test_name_0_55 fail
7778 23:46:39.170735 alsa_mixer-test_write_default_0_55 pass
7779 23:46:39.174250 alsa_mixer-test_write_valid_0_55 pass
7780 23:46:39.177294 alsa_mixer-test_write_invalid_0_55 pass
7781 23:46:39.180871 alsa_mixer-test_event_missing_0_55 pass
7782 23:46:39.184056 alsa_mixer-test_event_spurious_0_55 pass
7783 23:46:39.187360 alsa_mixer-test_get_value_0_54 pass
7784 23:46:39.190828 alsa_mixer-test_name_0_54 fail
7785 23:46:39.194371 alsa_mixer-test_write_default_0_54 pass
7786 23:46:39.197631 alsa_mixer-test_write_valid_0_54 pass
7787 23:46:39.200924 alsa_mixer-test_write_invalid_0_54 pass
7788 23:46:39.204474 alsa_mixer-test_event_missing_0_54 pass
7789 23:46:39.210319 alsa_mixer-test_event_spurious_0_54 pass
7790 23:46:39.210732 alsa_mixer-test_get_value_0_53 pass
7791 23:46:39.214144 alsa_mixer-test_name_0_53 fail
7792 23:46:39.217699 alsa_mixer-test_write_default_0_53 pass
7793 23:46:39.221362 alsa_mixer-test_write_valid_0_53 pass
7794 23:46:39.224072 alsa_mixer-test_write_invalid_0_53 pass
7795 23:46:39.227581 alsa_mixer-test_event_missing_0_53 pass
7796 23:46:39.234413 alsa_mixer-test_event_spurious_0_53 pass
7797 23:46:39.237625 alsa_mixer-test_get_value_0_52 pass
7798 23:46:39.237717 alsa_mixer-test_name_0_52 fail
7799 23:46:39.244416 alsa_mixer-test_write_default_0_52 pass
7800 23:46:39.247519 alsa_mixer-test_write_valid_0_52 pass
7801 23:46:39.250893 alsa_mixer-test_write_invalid_0_52 pass
7802 23:46:39.254139 alsa_mixer-test_event_missing_0_52 pass
7803 23:46:39.257271 alsa_mixer-test_event_spurious_0_52 pass
7804 23:46:39.260896 alsa_mixer-test_get_value_0_51 pass
7805 23:46:39.264149 alsa_mixer-test_name_0_51 fail
7806 23:46:39.267428 alsa_mixer-test_write_default_0_51 pass
7807 23:46:39.271064 alsa_mixer-test_write_valid_0_51 pass
7808 23:46:39.274006 alsa_mixer-test_write_invalid_0_51 pass
7809 23:46:39.277449 alsa_mixer-test_event_missing_0_51 pass
7810 23:46:39.283776 alsa_mixer-test_event_spurious_0_51 pass
7811 23:46:39.287435 alsa_mixer-test_get_value_0_50 pass
7812 23:46:39.287543 alsa_mixer-test_name_0_50 fail
7813 23:46:39.294051 alsa_mixer-test_write_default_0_50 pass
7814 23:46:39.297016 alsa_mixer-test_write_valid_0_50 pass
7815 23:46:39.300293 alsa_mixer-test_write_invalid_0_50 pass
7816 23:46:39.303932 alsa_mixer-test_event_missing_0_50 pass
7817 23:46:39.307221 alsa_mixer-test_event_spurious_0_50 pass
7818 23:46:39.310342 alsa_mixer-test_get_value_0_49 pass
7819 23:46:39.313800 alsa_mixer-test_name_0_49 fail
7820 23:46:39.316706 alsa_mixer-test_write_default_0_49 pass
7821 23:46:39.320116 alsa_mixer-test_write_valid_0_49 pass
7822 23:46:39.323512 alsa_mixer-test_write_invalid_0_49 pass
7823 23:46:39.327094 alsa_mixer-test_event_missing_0_49 pass
7824 23:46:39.329946 alsa_mixer-test_event_spurious_0_49 pass
7825 23:46:39.333469 alsa_mixer-test_get_value_0_48 pass
7826 23:46:39.337162 alsa_mixer-test_name_0_48 fail
7827 23:46:39.339998 alsa_mixer-test_write_default_0_48 pass
7828 23:46:39.343653 alsa_mixer-test_write_valid_0_48 pass
7829 23:46:39.346511 alsa_mixer-test_write_invalid_0_48 pass
7830 23:46:39.353303 alsa_mixer-test_event_missing_0_48 pass
7831 23:46:39.356423 alsa_mixer-test_event_spurious_0_48 pass
7832 23:46:39.360149 alsa_mixer-test_get_value_0_47 pass
7833 23:46:39.363197 alsa_mixer-test_name_0_47 fail
7834 23:46:39.366743 alsa_mixer-test_write_default_0_47 pass
7835 23:46:39.369878 alsa_mixer-test_write_valid_0_47 pass
7836 23:46:39.372941 alsa_mixer-test_write_invalid_0_47 pass
7837 23:46:39.376716 alsa_mixer-test_event_missing_0_47 pass
7838 23:46:39.379772 alsa_mixer-test_event_spurious_0_47 pass
7839 23:46:39.383026 alsa_mixer-test_get_value_0_46 pass
7840 23:46:39.386262 alsa_mixer-test_name_0_46 fail
7841 23:46:39.389655 alsa_mixer-test_write_default_0_46 pass
7842 23:46:39.393003 alsa_mixer-test_write_valid_0_46 pass
7843 23:46:39.396440 alsa_mixer-test_write_invalid_0_46 pass
7844 23:46:39.399610 alsa_mixer-test_event_missing_0_46 pass
7845 23:46:39.405898 alsa_mixer-test_event_spurious_0_46 pass
7846 23:46:39.409646 alsa_mixer-test_get_value_0_45 pass
7847 23:46:39.409739 alsa_mixer-test_name_0_45 fail
7848 23:46:39.413186 alsa_mixer-test_write_default_0_45 pass
7849 23:46:39.416149 alsa_mixer-test_write_valid_0_45 pass
7850 23:46:39.423000 alsa_mixer-test_write_invalid_0_45 pass
7851 23:46:39.426531 alsa_mixer-test_event_missing_0_45 pass
7852 23:46:39.429332 alsa_mixer-test_event_spurious_0_45 pass
7853 23:46:39.432889 alsa_mixer-test_get_value_0_44 pass
7854 23:46:39.435930 alsa_mixer-test_name_0_44 fail
7855 23:46:39.439317 alsa_mixer-test_write_default_0_44 pass
7856 23:46:39.442909 alsa_mixer-test_write_valid_0_44 pass
7857 23:46:39.446378 alsa_mixer-test_write_invalid_0_44 pass
7858 23:46:39.449879 alsa_mixer-test_event_missing_0_44 pass
7859 23:46:39.452749 alsa_mixer-test_event_spurious_0_44 pass
7860 23:46:39.455791 alsa_mixer-test_get_value_0_43 pass
7861 23:46:39.459769 alsa_mixer-test_name_0_43 fail
7862 23:46:39.462481 alsa_mixer-test_write_default_0_43 pass
7863 23:46:39.466279 alsa_mixer-test_write_valid_0_43 pass
7864 23:46:39.469628 alsa_mixer-test_write_invalid_0_43 pass
7865 23:46:39.472727 alsa_mixer-test_event_missing_0_43 pass
7866 23:46:39.479561 alsa_mixer-test_event_spurious_0_43 pass
7867 23:46:39.482975 alsa_mixer-test_get_value_0_42 pass
7868 23:46:39.483066 alsa_mixer-test_name_0_42 fail
7869 23:46:39.489500 alsa_mixer-test_write_default_0_42 pass
7870 23:46:39.492524 alsa_mixer-test_write_valid_0_42 pass
7871 23:46:39.495945 alsa_mixer-test_write_invalid_0_42 pass
7872 23:46:39.499500 alsa_mixer-test_event_missing_0_42 pass
7873 23:46:39.502585 alsa_mixer-test_event_spurious_0_42 pass
7874 23:46:39.506042 alsa_mixer-test_get_value_0_41 pass
7875 23:46:39.509445 alsa_mixer-test_name_0_41 fail
7876 23:46:39.512558 alsa_mixer-test_write_default_0_41 pass
7877 23:46:39.515806 alsa_mixer-test_write_valid_0_41 pass
7878 23:46:39.519330 alsa_mixer-test_write_invalid_0_41 pass
7879 23:46:39.522355 alsa_mixer-test_event_missing_0_41 pass
7880 23:46:39.525710 alsa_mixer-test_event_spurious_0_41 pass
7881 23:46:39.529057 alsa_mixer-test_get_value_0_40 pass
7882 23:46:39.532609 alsa_mixer-test_name_0_40 fail
7883 23:46:39.535420 alsa_mixer-test_write_default_0_40 pass
7884 23:46:39.539050 alsa_mixer-test_write_valid_0_40 pass
7885 23:46:39.545897 alsa_mixer-test_write_invalid_0_40 pass
7886 23:46:39.549037 alsa_mixer-test_event_missing_0_40 pass
7887 23:46:39.552296 alsa_mixer-test_event_spurious_0_40 pass
7888 23:46:39.555751 alsa_mixer-test_get_value_0_39 pass
7889 23:46:39.558736 alsa_mixer-test_name_0_39 fail
7890 23:46:39.562760 alsa_mixer-test_write_default_0_39 pass
7891 23:46:39.565379 alsa_mixer-test_write_valid_0_39 pass
7892 23:46:39.568792 alsa_mixer-test_write_invalid_0_39 pass
7893 23:46:39.572342 alsa_mixer-test_event_missing_0_39 pass
7894 23:46:39.575667 alsa_mixer-test_event_spurious_0_39 pass
7895 23:46:39.578890 alsa_mixer-test_get_value_0_38 pass
7896 23:46:39.581857 alsa_mixer-test_name_0_38 fail
7897 23:46:39.585269 alsa_mixer-test_write_default_0_38 pass
7898 23:46:39.588981 alsa_mixer-test_write_valid_0_38 pass
7899 23:46:39.591767 alsa_mixer-test_write_invalid_0_38 pass
7900 23:46:39.598747 alsa_mixer-test_event_missing_0_38 pass
7901 23:46:39.601660 alsa_mixer-test_event_spurious_0_38 pass
7902 23:46:39.605226 alsa_mixer-test_get_value_0_37 pass
7903 23:46:39.608319 alsa_mixer-test_name_0_37 fail
7904 23:46:39.611610 alsa_mixer-test_write_default_0_37 pass
7905 23:46:39.614949 alsa_mixer-test_write_valid_0_37 pass
7906 23:46:39.618309 alsa_mixer-test_write_invalid_0_37 pass
7907 23:46:39.621554 alsa_mixer-test_event_missing_0_37 pass
7908 23:46:39.624944 alsa_mixer-test_event_spurious_0_37 pass
7909 23:46:39.628603 alsa_mixer-test_get_value_0_36 pass
7910 23:46:39.631524 alsa_mixer-test_name_0_36 fail
7911 23:46:39.634945 alsa_mixer-test_write_default_0_36 pass
7912 23:46:39.638459 alsa_mixer-test_write_valid_0_36 pass
7913 23:46:39.641961 alsa_mixer-test_write_invalid_0_36 pass
7914 23:46:39.645323 alsa_mixer-test_event_missing_0_36 pass
7915 23:46:39.648326 alsa_mixer-test_event_spurious_0_36 pass
7916 23:46:39.651882 alsa_mixer-test_get_value_0_35 pass
7917 23:46:39.655152 alsa_mixer-test_name_0_35 fail
7918 23:46:39.658615 alsa_mixer-test_write_default_0_35 pass
7919 23:46:39.662225 alsa_mixer-test_write_valid_0_35 pass
7920 23:46:39.665097 alsa_mixer-test_write_invalid_0_35 pass
7921 23:46:39.668226 alsa_mixer-test_event_missing_0_35 pass
7922 23:46:39.671700 alsa_mixer-test_event_spurious_0_35 pass
7923 23:46:39.675185 alsa_mixer-test_get_value_0_34 pass
7924 23:46:39.678528 alsa_mixer-test_name_0_34 fail
7925 23:46:39.681795 alsa_mixer-test_write_default_0_34 pass
7926 23:46:39.685428 alsa_mixer-test_write_valid_0_34 pass
7927 23:46:39.688280 alsa_mixer-test_write_invalid_0_34 pass
7928 23:46:39.691536 alsa_mixer-test_event_missing_0_34 pass
7929 23:46:39.695157 alsa_mixer-test_event_spurious_0_34 pass
7930 23:46:39.701571 alsa_mixer-test_get_value_0_33 pass
7931 23:46:39.701666 alsa_mixer-test_name_0_33 fail
7932 23:46:39.704973 alsa_mixer-test_write_default_0_33 pass
7933 23:46:39.711327 alsa_mixer-test_write_valid_0_33 pass
7934 23:46:39.714852 alsa_mixer-test_write_invalid_0_33 pass
7935 23:46:39.718063 alsa_mixer-test_event_missing_0_33 pass
7936 23:46:39.721554 alsa_mixer-test_event_spurious_0_33 pass
7937 23:46:39.724746 alsa_mixer-test_get_value_0_32 pass
7938 23:46:39.728023 alsa_mixer-test_name_0_32 fail
7939 23:46:39.731181 alsa_mixer-test_write_default_0_32 pass
7940 23:46:39.734841 alsa_mixer-test_write_valid_0_32 pass
7941 23:46:39.738103 alsa_mixer-test_write_invalid_0_32 pass
7942 23:46:39.741214 alsa_mixer-test_event_missing_0_32 pass
7943 23:46:39.744417 alsa_mixer-test_event_spurious_0_32 pass
7944 23:46:39.748021 alsa_mixer-test_get_value_0_31 pass
7945 23:46:39.751152 alsa_mixer-test_name_0_31 fail
7946 23:46:39.755004 alsa_mixer-test_write_default_0_31 pass
7947 23:46:39.757969 alsa_mixer-test_write_valid_0_31 pass
7948 23:46:39.761491 alsa_mixer-test_write_invalid_0_31 pass
7949 23:46:39.767937 alsa_mixer-test_event_missing_0_31 pass
7950 23:46:39.771375 alsa_mixer-test_event_spurious_0_31 pass
7951 23:46:39.774225 alsa_mixer-test_get_value_0_30 pass
7952 23:46:39.778165 alsa_mixer-test_name_0_30 fail
7953 23:46:39.780940 alsa_mixer-test_write_default_0_30 pass
7954 23:46:39.784233 alsa_mixer-test_write_valid_0_30 pass
7955 23:46:39.787536 alsa_mixer-test_write_invalid_0_30 pass
7956 23:46:39.791354 alsa_mixer-test_event_missing_0_30 pass
7957 23:46:39.794443 alsa_mixer-test_event_spurious_0_30 pass
7958 23:46:39.797743 alsa_mixer-test_get_value_0_29 pass
7959 23:46:39.800718 alsa_mixer-test_name_0_29 pass
7960 23:46:39.804403 alsa_mixer-test_write_default_0_29 pass
7961 23:46:39.807782 alsa_mixer-test_write_valid_0_29 pass
7962 23:46:39.810759 alsa_mixer-test_write_invalid_0_29 pass
7963 23:46:39.814124 alsa_mixer-test_event_missing_0_29 pass
7964 23:46:39.821240 alsa_mixer-test_event_spurious_0_29 pass
7965 23:46:39.824182 alsa_mixer-test_get_value_0_28 pass
7966 23:46:39.824274 alsa_mixer-test_name_0_28 pass
7967 23:46:39.827612 alsa_mixer-test_write_default_0_28 pass
7968 23:46:39.834421 alsa_mixer-test_write_valid_0_28 pass
7969 23:46:39.837476 alsa_mixer-test_write_invalid_0_28 pass
7970 23:46:39.840736 alsa_mixer-test_event_missing_0_28 pass
7971 23:46:39.843905 alsa_mixer-test_event_spurious_0_28 pass
7972 23:46:39.847083 alsa_mixer-test_get_value_0_27 pass
7973 23:46:39.850747 alsa_mixer-test_name_0_27 pass
7974 23:46:39.854320 alsa_mixer-test_write_default_0_27 pass
7975 23:46:39.857092 alsa_mixer-test_write_valid_0_27 pass
7976 23:46:39.860602 alsa_mixer-test_write_invalid_0_27 pass
7977 23:46:39.864049 alsa_mixer-test_event_missing_0_27 pass
7978 23:46:39.867118 alsa_mixer-test_event_spurious_0_27 pass
7979 23:46:39.870410 alsa_mixer-test_get_value_0_26 pass
7980 23:46:39.873730 alsa_mixer-test_name_0_26 pass
7981 23:46:39.876828 alsa_mixer-test_write_default_0_26 pass
7982 23:46:39.880272 alsa_mixer-test_write_valid_0_26 pass
7983 23:46:39.887000 alsa_mixer-test_write_invalid_0_26 pass
7984 23:46:39.890216 alsa_mixer-test_event_missing_0_26 pass
7985 23:46:39.894075 alsa_mixer-test_event_spurious_0_26 pass
7986 23:46:39.896937 alsa_mixer-test_get_value_0_25 pass
7987 23:46:39.900660 alsa_mixer-test_name_0_25 pass
7988 23:46:39.903727 alsa_mixer-test_write_default_0_25 pass
7989 23:46:39.907044 alsa_mixer-test_write_valid_0_25 pass
7990 23:46:39.910468 alsa_mixer-test_write_invalid_0_25 pass
7991 23:46:39.913407 alsa_mixer-test_event_missing_0_25 pass
7992 23:46:39.916802 alsa_mixer-test_event_spurious_0_25 pass
7993 23:46:39.920202 alsa_mixer-test_get_value_0_24 pass
7994 23:46:39.923636 alsa_mixer-test_name_0_24 pass
7995 23:46:39.927069 alsa_mixer-test_write_default_0_24 pass
7996 23:46:39.930473 alsa_mixer-test_write_valid_0_24 pass
7997 23:46:39.933278 alsa_mixer-test_write_invalid_0_24 pass
7998 23:46:39.936883 alsa_mixer-test_event_missing_0_24 pass
7999 23:46:39.943546 alsa_mixer-test_event_spurious_0_24 pass
8000 23:46:39.946888 alsa_mixer-test_get_value_0_23 pass
8001 23:46:39.946979 alsa_mixer-test_name_0_23 pass
8002 23:46:39.953246 alsa_mixer-test_write_default_0_23 pass
8003 23:46:39.956725 alsa_mixer-test_write_valid_0_23 pass
8004 23:46:39.959694 alsa_mixer-test_write_invalid_0_23 pass
8005 23:46:39.963170 alsa_mixer-test_event_missing_0_23 pass
8006 23:46:39.966502 alsa_mixer-test_event_spurious_0_23 pass
8007 23:46:39.969960 alsa_mixer-test_get_value_0_22 pass
8008 23:46:39.973261 alsa_mixer-test_name_0_22 pass
8009 23:46:39.976550 alsa_mixer-test_write_default_0_22 pass
8010 23:46:39.979806 alsa_mixer-test_write_valid_0_22 pass
8011 23:46:39.982962 alsa_mixer-test_write_invalid_0_22 pass
8012 23:46:39.986385 alsa_mixer-test_event_missing_0_22 pass
8013 23:46:39.989827 alsa_mixer-test_event_spurious_0_22 pass
8014 23:46:39.992856 alsa_mixer-test_get_value_0_21 pass
8015 23:46:39.996478 alsa_mixer-test_name_0_21 fail
8016 23:46:39.999842 alsa_mixer-test_write_default_0_21 pass
8017 23:46:40.003104 alsa_mixer-test_write_valid_0_21 pass
8018 23:46:40.006402 alsa_mixer-test_write_invalid_0_21 pass
8019 23:46:40.009892 alsa_mixer-test_event_missing_0_21 pass
8020 23:46:40.012835 alsa_mixer-test_event_spurious_0_21 pass
8021 23:46:40.016114 alsa_mixer-test_get_value_0_20 pass
8022 23:46:40.019531 alsa_mixer-test_name_0_20 fail
8023 23:46:40.023018 alsa_mixer-test_write_default_0_20 pass
8024 23:46:40.025930 alsa_mixer-test_write_valid_0_20 pass
8025 23:46:40.029296 alsa_mixer-test_write_invalid_0_20 pass
8026 23:46:40.032603 alsa_mixer-test_event_missing_0_20 pass
8027 23:46:40.036082 alsa_mixer-test_event_spurious_0_20 pass
8028 23:46:40.039336 alsa_mixer-test_get_value_0_19 pass
8029 23:46:40.042832 alsa_mixer-test_name_0_19 fail
8030 23:46:40.046277 alsa_mixer-test_write_default_0_19 pass
8031 23:46:40.049260 alsa_mixer-test_write_valid_0_19 pass
8032 23:46:40.052634 alsa_mixer-test_write_invalid_0_19 pass
8033 23:46:40.055910 alsa_mixer-test_event_missing_0_19 pass
8034 23:46:40.059228 alsa_mixer-test_event_spurious_0_19 pass
8035 23:46:40.062525 alsa_mixer-test_get_value_0_18 pass
8036 23:46:40.065827 alsa_mixer-test_name_0_18 fail
8037 23:46:40.069177 alsa_mixer-test_write_default_0_18 pass
8038 23:46:40.072624 alsa_mixer-test_write_valid_0_18 pass
8039 23:46:40.075983 alsa_mixer-test_write_invalid_0_18 pass
8040 23:46:40.082378 alsa_mixer-test_event_missing_0_18 pass
8041 23:46:40.085848 alsa_mixer-test_event_spurious_0_18 pass
8042 23:46:40.089134 alsa_mixer-test_get_value_0_17 pass
8043 23:46:40.089225 alsa_mixer-test_name_0_17 fail
8044 23:46:40.092609 alsa_mixer-test_write_default_0_17 pass
8045 23:46:40.095942 alsa_mixer-test_write_valid_0_17 pass
8046 23:46:40.102764 alsa_mixer-test_write_invalid_0_17 pass
8047 23:46:40.106143 alsa_mixer-test_event_missing_0_17 pass
8048 23:46:40.109406 alsa_mixer-test_event_spurious_0_17 pass
8049 23:46:40.112537 alsa_mixer-test_get_value_0_16 pass
8050 23:46:40.115412 alsa_mixer-test_name_0_16 fail
8051 23:46:40.119351 alsa_mixer-test_write_default_0_16 pass
8052 23:46:40.122311 alsa_mixer-test_write_valid_0_16 pass
8053 23:46:40.125673 alsa_mixer-test_write_invalid_0_16 pass
8054 23:46:40.129193 alsa_mixer-test_event_missing_0_16 pass
8055 23:46:40.132138 alsa_mixer-test_event_spurious_0_16 pass
8056 23:46:40.135462 alsa_mixer-test_get_value_0_15 pass
8057 23:46:40.138795 alsa_mixer-test_name_0_15 fail
8058 23:46:40.142221 alsa_mixer-test_write_default_0_15 pass
8059 23:46:40.145731 alsa_mixer-test_write_valid_0_15 pass
8060 23:46:40.148660 alsa_mixer-test_write_invalid_0_15 pass
8061 23:46:40.151974 alsa_mixer-test_event_missing_0_15 pass
8062 23:46:40.155346 alsa_mixer-test_event_spurious_0_15 pass
8063 23:46:40.158950 alsa_mixer-test_get_value_0_14 pass
8064 23:46:40.161821 alsa_mixer-test_name_0_14 fail
8065 23:46:40.165334 alsa_mixer-test_write_default_0_14 pass
8066 23:46:40.168444 alsa_mixer-test_write_valid_0_14 pass
8067 23:46:40.171728 alsa_mixer-test_write_invalid_0_14 pass
8068 23:46:40.175163 alsa_mixer-test_event_missing_0_14 pass
8069 23:46:40.178543 alsa_mixer-test_event_spurious_0_14 pass
8070 23:46:40.181905 alsa_mixer-test_get_value_0_13 pass
8071 23:46:40.185444 alsa_mixer-test_name_0_13 fail
8072 23:46:40.188815 alsa_mixer-test_write_default_0_13 pass
8073 23:46:40.192126 alsa_mixer-test_write_valid_0_13 pass
8074 23:46:40.195127 alsa_mixer-test_write_invalid_0_13 pass
8075 23:46:40.198485 alsa_mixer-test_event_missing_0_13 pass
8076 23:46:40.201806 alsa_mixer-test_event_spurious_0_13 pass
8077 23:46:40.205405 alsa_mixer-test_get_value_0_12 pass
8078 23:46:40.208494 alsa_mixer-test_name_0_12 fail
8079 23:46:40.211694 alsa_mixer-test_write_default_0_12 pass
8080 23:46:40.215334 alsa_mixer-test_write_valid_0_12 pass
8081 23:46:40.221749 alsa_mixer-test_write_invalid_0_12 pass
8082 23:46:40.224942 alsa_mixer-test_event_missing_0_12 pass
8083 23:46:40.228182 alsa_mixer-test_event_spurious_0_12 pass
8084 23:46:40.231835 alsa_mixer-test_get_value_0_11 pass
8085 23:46:40.235373 alsa_mixer-test_name_0_11 fail
8086 23:46:40.238182 alsa_mixer-test_write_default_0_11 pass
8087 23:46:40.241446 alsa_mixer-test_write_valid_0_11 pass
8088 23:46:40.245008 alsa_mixer-test_write_invalid_0_11 pass
8089 23:46:40.248464 alsa_mixer-test_event_missing_0_11 pass
8090 23:46:40.251861 alsa_mixer-test_event_spurious_0_11 pass
8091 23:46:40.254921 alsa_mixer-test_get_value_0_10 pass
8092 23:46:40.258199 alsa_mixer-test_name_0_10 fail
8093 23:46:40.261539 alsa_mixer-test_write_default_0_10 pass
8094 23:46:40.264869 alsa_mixer-test_write_valid_0_10 pass
8095 23:46:40.268385 alsa_mixer-test_write_invalid_0_10 pass
8096 23:46:40.271755 alsa_mixer-test_event_missing_0_10 pass
8097 23:46:40.278299 alsa_mixer-test_event_spurious_0_10 pass
8098 23:46:40.278390 alsa_mixer-test_get_value_0_9 pass
8099 23:46:40.281436 alsa_mixer-test_name_0_9 fail
8100 23:46:40.285114 alsa_mixer-test_write_default_0_9 pass
8101 23:46:40.288158 alsa_mixer-test_write_valid_0_9 pass
8102 23:46:40.291375 alsa_mixer-test_write_invalid_0_9 pass
8103 23:46:40.295420 alsa_mixer-test_event_missing_0_9 pass
8104 23:46:40.301871 alsa_mixer-test_event_spurious_0_9 pass
8105 23:46:40.301963 alsa_mixer-test_get_value_0_8 pass
8106 23:46:40.305299 alsa_mixer-test_name_0_8 fail
8107 23:46:40.308511 alsa_mixer-test_write_default_0_8 pass
8108 23:46:40.311600 alsa_mixer-test_write_valid_0_8 pass
8109 23:46:40.314911 alsa_mixer-test_write_invalid_0_8 pass
8110 23:46:40.318159 alsa_mixer-test_event_missing_0_8 pass
8111 23:46:40.325045 alsa_mixer-test_event_spurious_0_8 pass
8112 23:46:40.325137 alsa_mixer-test_get_value_0_7 pass
8113 23:46:40.328385 alsa_mixer-test_name_0_7 fail
8114 23:46:40.331522 alsa_mixer-test_write_default_0_7 pass
8115 23:46:40.334640 alsa_mixer-test_write_valid_0_7 pass
8116 23:46:40.338000 alsa_mixer-test_write_invalid_0_7 pass
8117 23:46:40.341168 alsa_mixer-test_event_missing_0_7 pass
8118 23:46:40.348496 alsa_mixer-test_event_spurious_0_7 pass
8119 23:46:40.348623 alsa_mixer-test_get_value_0_6 pass
8120 23:46:40.351208 alsa_mixer-test_name_0_6 fail
8121 23:46:40.354562 alsa_mixer-test_write_default_0_6 pass
8122 23:46:40.358109 alsa_mixer-test_write_valid_0_6 pass
8123 23:46:40.360987 alsa_mixer-test_write_invalid_0_6 pass
8124 23:46:40.364597 alsa_mixer-test_event_missing_0_6 pass
8125 23:46:40.371254 alsa_mixer-test_event_spurious_0_6 pass
8126 23:46:40.371346 alsa_mixer-test_get_value_0_5 pass
8127 23:46:40.374289 alsa_mixer-test_name_0_5 pass
8128 23:46:40.377766 alsa_mixer-test_write_default_0_5 pass
8129 23:46:40.381027 alsa_mixer-test_write_valid_0_5 pass
8130 23:46:40.384171 alsa_mixer-test_write_invalid_0_5 pass
8131 23:46:40.387266 alsa_mixer-test_event_missing_0_5 fail
8132 23:46:40.394522 alsa_mixer-test_event_spurious_0_5 pass
8133 23:46:40.394615 alsa_mixer-test_get_value_0_4 pass
8134 23:46:40.397285 alsa_mixer-test_name_0_4 pass
8135 23:46:40.400545 alsa_mixer-test_write_default_0_4 pass
8136 23:46:40.404184 alsa_mixer-test_write_valid_0_4 pass
8137 23:46:40.407514 alsa_mixer-test_write_invalid_0_4 pass
8138 23:46:40.410394 alsa_mixer-test_event_missing_0_4 fail
8139 23:46:40.417124 alsa_mixer-test_event_spurious_0_4 pass
8140 23:46:40.417217 alsa_mixer-test_get_value_0_3 pass
8141 23:46:40.420616 alsa_mixer-test_name_0_3 pass
8142 23:46:40.423994 alsa_mixer-test_write_default_0_3 pass
8143 23:46:40.427373 alsa_mixer-test_write_valid_0_3 pass
8144 23:46:40.430182 alsa_mixer-test_write_invalid_0_3 pass
8145 23:46:40.433731 alsa_mixer-test_event_missing_0_3 fail
8146 23:46:40.440181 alsa_mixer-test_event_spurious_0_3 pass
8147 23:46:40.440298 alsa_mixer-test_get_value_0_2 pass
8148 23:46:40.443361 alsa_mixer-test_name_0_2 pass
8149 23:46:40.447137 alsa_mixer-test_write_default_0_2 pass
8150 23:46:40.450379 alsa_mixer-test_write_valid_0_2 pass
8151 23:46:40.453583 alsa_mixer-test_write_invalid_0_2 pass
8152 23:46:40.456597 alsa_mixer-test_event_missing_0_2 fail
8153 23:46:40.463599 alsa_mixer-test_event_spurious_0_2 pass
8154 23:46:40.463691 alsa_mixer-test_get_value_0_1 pass
8155 23:46:40.466695 alsa_mixer-test_name_0_1 pass
8156 23:46:40.470113 alsa_mixer-test_write_default_0_1 pass
8157 23:46:40.472966 alsa_mixer-test_write_valid_0_1 pass
8158 23:46:40.476285 alsa_mixer-test_write_invalid_0_1 pass
8159 23:46:40.479583 alsa_mixer-test_event_missing_0_1 fail
8160 23:46:40.483146 alsa_mixer-test_event_spurious_0_1 pass
8161 23:46:40.486767 alsa_mixer-test_get_value_0_0 pass
8162 23:46:40.489656 alsa_mixer-test_name_0_0 pass
8163 23:46:40.492908 alsa_mixer-test_write_default_0_0 pass
8164 23:46:40.496562 alsa_mixer-test_write_valid_0_0 pass
8165 23:46:40.499614 alsa_mixer-test_write_invalid_0_0 pass
8166 23:46:40.502953 alsa_mixer-test_event_missing_0_0 fail
8167 23:46:40.506456 alsa_mixer-test_event_spurious_0_0 pass
8168 23:46:40.509992 alsa_mixer-test pass
8169 23:46:40.513259 + ../../utils/send-to-lava.sh ./output/result.txt
8170 23:46:40.519995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
8171 23:46:40.520303 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
8173 23:46:40.526361 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass>
8174 23:46:40.526626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_93 RESULT=pass
8176 23:46:40.533096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass>
8177 23:46:40.533360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_93 RESULT=pass
8179 23:46:40.539382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass>
8180 23:46:40.539653 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_93 RESULT=pass
8182 23:46:40.546057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass>
8183 23:46:40.546328 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_93 RESULT=pass
8185 23:46:40.556160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass>
8186 23:46:40.556426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_93 RESULT=pass
8188 23:46:40.592833 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass>
8189 23:46:40.593123 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_93 RESULT=pass
8191 23:46:40.633875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass>
8192 23:46:40.634227 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_93 RESULT=pass
8194 23:46:40.675800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass>
8195 23:46:40.676119 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_92 RESULT=pass
8197 23:46:40.713316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass>
8198 23:46:40.713608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_92 RESULT=pass
8200 23:46:40.759882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass>
8201 23:46:40.760200 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_92 RESULT=pass
8203 23:46:40.801768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass>
8204 23:46:40.802074 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_92 RESULT=pass
8206 23:46:40.839103 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass>
8207 23:46:40.839432 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_92 RESULT=pass
8209 23:46:40.884646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass>
8210 23:46:40.884969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_92 RESULT=pass
8212 23:46:40.920105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass>
8213 23:46:40.920420 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_92 RESULT=pass
8215 23:46:40.956643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass>
8216 23:46:40.956964 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_91 RESULT=pass
8218 23:46:40.994004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass>
8219 23:46:40.994314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_91 RESULT=pass
8221 23:46:41.035628 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass>
8222 23:46:41.035928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_91 RESULT=pass
8224 23:46:41.075197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass>
8225 23:46:41.075537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_91 RESULT=pass
8227 23:46:41.113667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass>
8228 23:46:41.113961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_91 RESULT=pass
8230 23:46:41.153989 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass>
8231 23:46:41.154327 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_91 RESULT=pass
8233 23:46:41.197241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass>
8234 23:46:41.197556 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_91 RESULT=pass
8236 23:46:41.233966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass>
8237 23:46:41.234278 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_90 RESULT=pass
8239 23:46:41.271949 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass>
8240 23:46:41.272261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_90 RESULT=pass
8242 23:46:41.322106 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass>
8243 23:46:41.322433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_90 RESULT=pass
8245 23:46:41.364071 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass>
8246 23:46:41.364402 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_90 RESULT=pass
8248 23:46:41.404204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass>
8249 23:46:41.404531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_90 RESULT=pass
8251 23:46:41.448921 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass>
8252 23:46:41.449256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_90 RESULT=pass
8254 23:46:41.487157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass>
8255 23:46:41.487514 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_90 RESULT=pass
8257 23:46:41.528083 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass>
8258 23:46:41.528445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_89 RESULT=pass
8260 23:46:41.562059 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass>
8261 23:46:41.562391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_89 RESULT=pass
8263 23:46:41.604276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass>
8264 23:46:41.604609 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_89 RESULT=pass
8266 23:46:41.644606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass>
8267 23:46:41.644928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_89 RESULT=pass
8269 23:46:41.687737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass>
8270 23:46:41.688058 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_89 RESULT=pass
8272 23:46:41.735747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass>
8273 23:46:41.736082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_89 RESULT=pass
8275 23:46:41.780424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass>
8276 23:46:41.780792 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_89 RESULT=pass
8278 23:46:41.833315 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass>
8279 23:46:41.833646 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_88 RESULT=pass
8281 23:46:41.870681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass>
8282 23:46:41.871009 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_88 RESULT=pass
8284 23:46:41.910548 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass>
8285 23:46:41.910926 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_88 RESULT=pass
8287 23:46:41.956011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail>
8288 23:46:41.956356 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_88 RESULT=fail
8290 23:46:41.997736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass>
8291 23:46:41.998087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_88 RESULT=pass
8293 23:46:42.051607 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass>
8294 23:46:42.051937 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_88 RESULT=pass
8296 23:46:42.098740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail>
8297 23:46:42.099066 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_88 RESULT=fail
8299 23:46:42.138602 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass>
8300 23:46:42.138924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_87 RESULT=pass
8302 23:46:42.173221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass>
8303 23:46:42.173548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_87 RESULT=pass
8305 23:46:42.217062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass>
8306 23:46:42.217385 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_87 RESULT=pass
8308 23:46:42.259577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass>
8309 23:46:42.259891 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_87 RESULT=pass
8311 23:46:42.313068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass>
8312 23:46:42.313387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_87 RESULT=pass
8314 23:46:42.360301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass>
8315 23:46:42.360623 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_87 RESULT=pass
8317 23:46:42.400540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass>
8318 23:46:42.400847 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_87 RESULT=pass
8320 23:46:42.441890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass>
8321 23:46:42.442236 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_86 RESULT=pass
8323 23:46:42.484087 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass
8325 23:46:42.487303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_86 RESULT=pass>
8326 23:46:42.526965 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass>
8327 23:46:42.527269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_86 RESULT=pass
8329 23:46:42.563940 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail>
8330 23:46:42.564244 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_86 RESULT=fail
8332 23:46:42.607540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass>
8333 23:46:42.607829 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_86 RESULT=pass
8335 23:46:42.645875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass>
8336 23:46:42.646201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_86 RESULT=pass
8338 23:46:42.681257 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass>
8339 23:46:42.681590 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_86 RESULT=pass
8341 23:46:42.720152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass>
8342 23:46:42.720490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_85 RESULT=pass
8344 23:46:42.753704 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass>
8345 23:46:42.754003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_85 RESULT=pass
8347 23:46:42.791685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass>
8348 23:46:42.792021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_85 RESULT=pass
8350 23:46:42.829787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail>
8351 23:46:42.830091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_85 RESULT=fail
8353 23:46:42.870713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass>
8354 23:46:42.871035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_85 RESULT=pass
8356 23:46:42.907269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass>
8357 23:46:42.907615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_85 RESULT=pass
8359 23:46:42.946031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass>
8360 23:46:42.946314 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_85 RESULT=pass
8362 23:46:42.981874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass>
8363 23:46:42.982156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_84 RESULT=pass
8365 23:46:43.013797 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass>
8366 23:46:43.014112 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_84 RESULT=pass
8368 23:46:43.048844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass>
8369 23:46:43.049146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_84 RESULT=pass
8371 23:46:43.085983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass>
8372 23:46:43.086263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_84 RESULT=pass
8374 23:46:43.128094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass>
8375 23:46:43.128399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_84 RESULT=pass
8377 23:46:43.166251 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass>
8378 23:46:43.166530 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_84 RESULT=pass
8380 23:46:43.206637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass>
8381 23:46:43.206910 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_84 RESULT=pass
8383 23:46:43.248217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass>
8384 23:46:43.248497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_83 RESULT=pass
8386 23:46:43.285248 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass>
8387 23:46:43.285522 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_83 RESULT=pass
8389 23:46:43.330164 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass>
8390 23:46:43.330436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_83 RESULT=pass
8392 23:46:43.369650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass>
8393 23:46:43.369925 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_83 RESULT=pass
8395 23:46:43.411605 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass>
8396 23:46:43.411897 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_83 RESULT=pass
8398 23:46:43.452420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass>
8399 23:46:43.452695 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_83 RESULT=pass
8401 23:46:43.496306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass>
8402 23:46:43.496582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_83 RESULT=pass
8404 23:46:43.535702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass>
8405 23:46:43.535999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_82 RESULT=pass
8407 23:46:43.570591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass>
8408 23:46:43.570919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_82 RESULT=pass
8410 23:46:43.609661 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip>
8411 23:46:43.609939 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_82 RESULT=skip
8413 23:46:43.648232 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip>
8414 23:46:43.648506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_82 RESULT=skip
8416 23:46:43.690839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip>
8417 23:46:43.691164 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_82 RESULT=skip
8419 23:46:43.729018 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass>
8420 23:46:43.729304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_82 RESULT=pass
8422 23:46:43.767938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass>
8423 23:46:43.768260 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_82 RESULT=pass
8425 23:46:43.805271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass>
8426 23:46:43.805579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_81 RESULT=pass
8428 23:46:43.843330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass>
8429 23:46:43.843670 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_81 RESULT=pass
8431 23:46:43.884774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass>
8432 23:46:43.885113 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_81 RESULT=pass
8434 23:46:43.921342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass>
8435 23:46:43.921703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_81 RESULT=pass
8437 23:46:43.960498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail>
8438 23:46:43.960867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_81 RESULT=fail
8440 23:46:43.999329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail>
8441 23:46:43.999675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_81 RESULT=fail
8443 23:46:44.038035 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass>
8444 23:46:44.038387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_81 RESULT=pass
8446 23:46:44.073721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass>
8447 23:46:44.074050 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_80 RESULT=pass
8449 23:46:44.109183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass>
8450 23:46:44.109510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_80 RESULT=pass
8452 23:46:44.153193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass>
8453 23:46:44.153506 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_80 RESULT=pass
8455 23:46:44.191391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass>
8456 23:46:44.191703 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_80 RESULT=pass
8458 23:46:44.226885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass>
8459 23:46:44.227193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_80 RESULT=pass
8461 23:46:44.261196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass>
8462 23:46:44.261497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_80 RESULT=pass
8464 23:46:44.299166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass>
8465 23:46:44.299442 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_80 RESULT=pass
8467 23:46:44.336970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail>
8468 23:46:44.337304 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_79 RESULT=fail
8470 23:46:44.370254 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass>
8471 23:46:44.370584 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_79 RESULT=pass
8473 23:46:44.414148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail>
8474 23:46:44.414479 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_79 RESULT=fail
8476 23:46:44.454514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail>
8477 23:46:44.454846 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_79 RESULT=fail
8479 23:46:44.494539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail>
8480 23:46:44.494875 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_79 RESULT=fail
8482 23:46:44.535731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass>
8483 23:46:44.536065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_79 RESULT=pass
8485 23:46:44.575524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass>
8486 23:46:44.575858 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_79 RESULT=pass
8488 23:46:44.615246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail>
8489 23:46:44.615599 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_78 RESULT=fail
8491 23:46:44.649715 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass>
8492 23:46:44.650052 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_78 RESULT=pass
8494 23:46:44.688202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail>
8495 23:46:44.688553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_78 RESULT=fail
8497 23:46:44.726927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail>
8498 23:46:44.727288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_78 RESULT=fail
8500 23:46:44.764861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail>
8501 23:46:44.765239 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_78 RESULT=fail
8503 23:46:44.803927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass>
8504 23:46:44.804264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_78 RESULT=pass
8506 23:46:44.844122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass>
8507 23:46:44.844460 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_78 RESULT=pass
8509 23:46:44.879355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail>
8510 23:46:44.879692 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_77 RESULT=fail
8512 23:46:44.914117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass>
8513 23:46:44.914407 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_77 RESULT=pass
8515 23:46:44.953442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail>
8516 23:46:44.953799 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_77 RESULT=fail
8518 23:46:44.987025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail>
8519 23:46:44.987372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_77 RESULT=fail
8521 23:46:45.023241 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail>
8522 23:46:45.023579 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_77 RESULT=fail
8524 23:46:45.059261 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass>
8525 23:46:45.059593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_77 RESULT=pass
8527 23:46:45.095196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass>
8528 23:46:45.095538 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_77 RESULT=pass
8530 23:46:45.132718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass>
8531 23:46:45.133065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_76 RESULT=pass
8533 23:46:45.166267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail>
8534 23:46:45.166596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_76 RESULT=fail
8536 23:46:45.202819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass>
8537 23:46:45.203114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_76 RESULT=pass
8539 23:46:45.237022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass>
8540 23:46:45.237353 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_76 RESULT=pass
8542 23:46:45.271353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass>
8543 23:46:45.271654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_76 RESULT=pass
8545 23:46:45.303635 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass>
8546 23:46:45.303927 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_76 RESULT=pass
8548 23:46:45.335880 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass>
8549 23:46:45.336222 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_76 RESULT=pass
8551 23:46:45.373566 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass>
8552 23:46:45.373916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_75 RESULT=pass
8554 23:46:45.408678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail>
8555 23:46:45.408969 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_75 RESULT=fail
8557 23:46:45.447282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass>
8558 23:46:45.447607 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_75 RESULT=pass
8560 23:46:45.479486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass>
8561 23:46:45.479822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_75 RESULT=pass
8563 23:46:45.523411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass>
8564 23:46:45.523726 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_75 RESULT=pass
8566 23:46:45.561911 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass>
8567 23:46:45.562221 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_75 RESULT=pass
8569 23:46:45.603267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass>
8570 23:46:45.603633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_75 RESULT=pass
8572 23:46:45.641434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass>
8573 23:46:45.641757 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_74 RESULT=pass
8575 23:46:45.680031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail>
8576 23:46:45.680352 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_74 RESULT=fail
8578 23:46:45.721063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass>
8579 23:46:45.721380 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_74 RESULT=pass
8581 23:46:45.762589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass>
8582 23:46:45.762907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_74 RESULT=pass
8584 23:46:45.803759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass>
8585 23:46:45.804080 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_74 RESULT=pass
8587 23:46:45.842929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass>
8588 23:46:45.843251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_74 RESULT=pass
8590 23:46:45.877813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass>
8591 23:46:45.878136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_74 RESULT=pass
8593 23:46:45.921672 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass>
8594 23:46:45.921990 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_73 RESULT=pass
8596 23:46:45.951857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail>
8597 23:46:45.952133 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_73 RESULT=fail
8599 23:46:45.995342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass>
8600 23:46:45.995635 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_73 RESULT=pass
8602 23:46:46.029699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass>
8603 23:46:46.029985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_73 RESULT=pass
8605 23:46:46.064307 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass>
8606 23:46:46.064592 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_73 RESULT=pass
8608 23:46:46.097280 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass>
8609 23:46:46.097634 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_73 RESULT=pass
8611 23:46:46.133585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass>
8612 23:46:46.133962 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_73 RESULT=pass
8614 23:46:46.167678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass>
8615 23:46:46.167985 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_72 RESULT=pass
8617 23:46:46.205785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail>
8618 23:46:46.206057 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_72 RESULT=fail
8620 23:46:46.248766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass>
8621 23:46:46.249054 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_72 RESULT=pass
8623 23:46:46.284166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass>
8624 23:46:46.284447 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_72 RESULT=pass
8626 23:46:46.319324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass>
8627 23:46:46.319627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_72 RESULT=pass
8629 23:46:46.356270 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass>
8630 23:46:46.356548 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_72 RESULT=pass
8632 23:46:46.393049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass>
8633 23:46:46.393324 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_72 RESULT=pass
8635 23:46:46.396451 <6>[ 35.797882] vaux18: disabling
8636 23:46:46.399580 <6>[ 35.801382] vio28: disabling
8637 23:46:46.429542 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass>
8638 23:46:46.429811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_71 RESULT=pass
8640 23:46:46.462740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail>
8641 23:46:46.463015 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_71 RESULT=fail
8643 23:46:46.503044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass>
8644 23:46:46.503317 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_71 RESULT=pass
8646 23:46:46.537094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass>
8647 23:46:46.537364 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_71 RESULT=pass
8649 23:46:46.573317 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass>
8650 23:46:46.573594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_71 RESULT=pass
8652 23:46:46.613390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass>
8653 23:46:46.613666 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_71 RESULT=pass
8655 23:46:46.651838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass>
8656 23:46:46.652118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_71 RESULT=pass
8658 23:46:46.691952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass>
8659 23:46:46.692234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_70 RESULT=pass
8661 23:46:46.732888 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail>
8662 23:46:46.733168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_70 RESULT=fail
8664 23:46:46.782693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass>
8665 23:46:46.782989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_70 RESULT=pass
8667 23:46:46.819121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass>
8668 23:46:46.819393 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_70 RESULT=pass
8670 23:46:46.857175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass>
8671 23:46:46.857462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_70 RESULT=pass
8673 23:46:46.901336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass>
8674 23:46:46.901624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_70 RESULT=pass
8676 23:46:46.940115 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass>
8677 23:46:46.940389 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_70 RESULT=pass
8679 23:46:46.980929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass>
8680 23:46:46.981216 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_69 RESULT=pass
8682 23:46:47.017025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail>
8683 23:46:47.017302 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_69 RESULT=fail
8685 23:46:47.058302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass>
8686 23:46:47.058581 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_69 RESULT=pass
8688 23:46:47.094638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass>
8689 23:46:47.094916 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_69 RESULT=pass
8691 23:46:47.129774 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass>
8692 23:46:47.130051 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_69 RESULT=pass
8694 23:46:47.170224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass>
8695 23:46:47.170544 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_69 RESULT=pass
8697 23:46:47.212493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass>
8698 23:46:47.212800 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_69 RESULT=pass
8700 23:46:47.247588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass>
8701 23:46:47.247872 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_68 RESULT=pass
8703 23:46:47.278719 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail>
8704 23:46:47.279030 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_68 RESULT=fail
8706 23:46:47.318917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass>
8707 23:46:47.319193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_68 RESULT=pass
8709 23:46:47.355743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass>
8710 23:46:47.356059 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_68 RESULT=pass
8712 23:46:47.393110 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass>
8713 23:46:47.393383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_68 RESULT=pass
8715 23:46:47.425044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass>
8716 23:46:47.425311 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_68 RESULT=pass
8718 23:46:47.459347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass>
8719 23:46:47.459642 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_68 RESULT=pass
8721 23:46:47.495342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass>
8722 23:46:47.495637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_67 RESULT=pass
8724 23:46:47.525842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail>
8725 23:46:47.526110 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_67 RESULT=fail
8727 23:46:47.564652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass>
8728 23:46:47.564978 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_67 RESULT=pass
8730 23:46:47.607356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass>
8731 23:46:47.607714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_67 RESULT=pass
8733 23:46:47.650638 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass>
8734 23:46:47.651035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_67 RESULT=pass
8736 23:46:47.687573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass>
8737 23:46:47.687960 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_67 RESULT=pass
8739 23:46:47.725947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass>
8740 23:46:47.726333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_67 RESULT=pass
8742 23:46:47.766577 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass>
8743 23:46:47.766898 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_66 RESULT=pass
8745 23:46:47.806334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail>
8746 23:46:47.806861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_66 RESULT=fail
8748 23:46:47.858242 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass>
8749 23:46:47.858794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_66 RESULT=pass
8751 23:46:47.900419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass>
8752 23:46:47.900982 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_66 RESULT=pass
8754 23:46:47.941359 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass>
8755 23:46:47.941968 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_66 RESULT=pass
8757 23:46:47.981818 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass>
8758 23:46:47.982383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_66 RESULT=pass
8760 23:46:48.023077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass>
8761 23:46:48.023664 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_66 RESULT=pass
8763 23:46:48.062838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass>
8764 23:46:48.063434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_65 RESULT=pass
8766 23:46:48.101623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail>
8767 23:46:48.101892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_65 RESULT=fail
8769 23:46:48.146142 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass>
8770 23:46:48.146409 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_65 RESULT=pass
8772 23:46:48.184729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass>
8773 23:46:48.185001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_65 RESULT=pass
8775 23:46:48.222555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass>
8776 23:46:48.222837 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_65 RESULT=pass
8778 23:46:48.255618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass>
8779 23:46:48.255924 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_65 RESULT=pass
8781 23:46:48.288764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass>
8782 23:46:48.289118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_65 RESULT=pass
8784 23:46:48.321820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass>
8785 23:46:48.322201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_64 RESULT=pass
8787 23:46:48.355104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail>
8788 23:46:48.355906 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_64 RESULT=fail
8790 23:46:48.397879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass>
8791 23:46:48.398494 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_64 RESULT=pass
8793 23:46:48.439557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass>
8794 23:46:48.439844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_64 RESULT=pass
8796 23:46:48.483300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass>
8797 23:46:48.483596 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_64 RESULT=pass
8799 23:46:48.528999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass>
8800 23:46:48.529267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_64 RESULT=pass
8802 23:46:48.567314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass>
8803 23:46:48.567602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_64 RESULT=pass
8805 23:46:48.608764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass>
8806 23:46:48.609095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_63 RESULT=pass
8808 23:46:48.648675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail>
8809 23:46:48.649049 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_63 RESULT=fail
8811 23:46:48.697340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass>
8812 23:46:48.697996 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_63 RESULT=pass
8814 23:46:48.747166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass>
8815 23:46:48.747841 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_63 RESULT=pass
8817 23:46:48.788247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass>
8818 23:46:48.788566 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_63 RESULT=pass
8820 23:46:48.828939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass>
8821 23:46:48.829537 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_63 RESULT=pass
8823 23:46:48.870748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass>
8824 23:46:48.871429 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_63 RESULT=pass
8826 23:46:48.917778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass>
8827 23:46:48.918129 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_62 RESULT=pass
8829 23:46:48.959285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail>
8830 23:46:48.959561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_62 RESULT=fail
8832 23:46:49.004404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass>
8833 23:46:49.004714 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_62 RESULT=pass
8835 23:46:49.047559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass>
8836 23:46:49.048159 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_62 RESULT=pass
8838 23:46:49.099680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass>
8839 23:46:49.100285 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_62 RESULT=pass
8841 23:46:49.150961 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass>
8842 23:46:49.151256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_62 RESULT=pass
8844 23:46:49.195755 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass>
8845 23:46:49.196186 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_62 RESULT=pass
8847 23:46:49.242354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass>
8848 23:46:49.242989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_61 RESULT=pass
8850 23:46:49.285247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail>
8851 23:46:49.286089 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_61 RESULT=fail
8853 23:46:49.334588 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass>
8854 23:46:49.335259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_61 RESULT=pass
8856 23:46:49.377283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass>
8857 23:46:49.378145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_61 RESULT=pass
8859 23:46:49.421960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass>
8860 23:46:49.422762 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_61 RESULT=pass
8862 23:46:49.470562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass>
8863 23:46:49.471266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_61 RESULT=pass
8865 23:46:49.511101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass>
8866 23:46:49.511844 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_61 RESULT=pass
8868 23:46:49.560779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass>
8869 23:46:49.561557 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_60 RESULT=pass
8871 23:46:49.596391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail>
8872 23:46:49.597167 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_60 RESULT=fail
8874 23:46:49.646040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass>
8875 23:46:49.646809 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_60 RESULT=pass
8877 23:46:49.699009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass>
8878 23:46:49.699851 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_60 RESULT=pass
8880 23:46:49.752026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass>
8881 23:46:49.752963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_60 RESULT=pass
8883 23:46:49.809427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass>
8884 23:46:49.810140 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_60 RESULT=pass
8886 23:46:49.861985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass>
8887 23:46:49.862728 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_60 RESULT=pass
8889 23:46:49.909689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass>
8890 23:46:49.909958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_59 RESULT=pass
8892 23:46:49.954185 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail>
8893 23:46:49.954816 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_59 RESULT=fail
8895 23:46:50.007049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass>
8896 23:46:50.007869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_59 RESULT=pass
8898 23:46:50.058795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass>
8899 23:46:50.059374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_59 RESULT=pass
8901 23:46:50.104443 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass>
8902 23:46:50.104888 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_59 RESULT=pass
8904 23:46:50.148614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass>
8905 23:46:50.148892 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_59 RESULT=pass
8907 23:46:50.189405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass>
8908 23:46:50.189674 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_59 RESULT=pass
8910 23:46:50.229131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass>
8911 23:46:50.229416 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_58 RESULT=pass
8913 23:46:50.263955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail>
8914 23:46:50.264454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_58 RESULT=fail
8916 23:46:50.311147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass>
8917 23:46:50.311908 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_58 RESULT=pass
8919 23:46:50.349693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass>
8920 23:46:50.350208 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_58 RESULT=pass
8922 23:46:50.393484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass>
8923 23:46:50.394183 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_58 RESULT=pass
8925 23:46:50.440922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass>
8926 23:46:50.441553 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_58 RESULT=pass
8928 23:46:50.488480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass>
8929 23:46:50.489156 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_58 RESULT=pass
8931 23:46:50.533930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass>
8932 23:46:50.534269 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_57 RESULT=pass
8934 23:46:50.573991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail>
8935 23:46:50.574750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_57 RESULT=fail
8937 23:46:50.622154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass>
8938 23:46:50.622840 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_57 RESULT=pass
8940 23:46:50.665676 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass>
8941 23:46:50.666405 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_57 RESULT=pass
8943 23:46:50.709095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass>
8944 23:46:50.709802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_57 RESULT=pass
8946 23:46:50.750782 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass>
8947 23:46:50.751496 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_57 RESULT=pass
8949 23:46:50.799376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass>
8950 23:46:50.800131 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_57 RESULT=pass
8952 23:46:50.847217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass>
8953 23:46:50.848010 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_56 RESULT=pass
8955 23:46:50.886975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail>
8956 23:46:50.887913 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_56 RESULT=fail
8958 23:46:50.937551 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass>
8959 23:46:50.938325 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_56 RESULT=pass
8961 23:46:50.983795 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass>
8962 23:46:50.984474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_56 RESULT=pass
8964 23:46:51.027868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass>
8965 23:46:51.028659 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_56 RESULT=pass
8967 23:46:51.073180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass>
8968 23:46:51.073918 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_56 RESULT=pass
8970 23:46:51.116553 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass>
8971 23:46:51.117232 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_56 RESULT=pass
8973 23:46:51.167448 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass>
8974 23:46:51.168136 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_55 RESULT=pass
8976 23:46:51.208003 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail>
8977 23:46:51.208675 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_55 RESULT=fail
8979 23:46:51.259936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass>
8980 23:46:51.260691 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_55 RESULT=pass
8982 23:46:51.305145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass>
8983 23:46:51.305833 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_55 RESULT=pass
8985 23:46:51.355498 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass>
8986 23:46:51.356368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_55 RESULT=pass
8988 23:46:51.408576 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass>
8989 23:46:51.409329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_55 RESULT=pass
8991 23:46:51.465996 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass>
8992 23:46:51.466682 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_55 RESULT=pass
8994 23:46:51.522541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass>
8995 23:46:51.523242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_54 RESULT=pass
8997 23:46:51.570539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail>
8998 23:46:51.571454 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_54 RESULT=fail
9000 23:46:51.621264 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass>
9001 23:46:51.622012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_54 RESULT=pass
9003 23:46:51.671189 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass>
9004 23:46:51.672038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_54 RESULT=pass
9006 23:46:51.720369 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass>
9007 23:46:51.720637 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_54 RESULT=pass
9009 23:46:51.763539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass>
9010 23:46:51.763811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_54 RESULT=pass
9012 23:46:51.804987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass>
9013 23:46:51.805257 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_54 RESULT=pass
9015 23:46:51.842768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass>
9016 23:46:51.843036 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_53 RESULT=pass
9018 23:46:51.876234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail>
9019 23:46:51.876507 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_53 RESULT=fail
9021 23:46:51.917296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass>
9022 23:46:51.917564 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_53 RESULT=pass
9024 23:46:51.955373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass>
9025 23:46:51.955654 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_53 RESULT=pass
9027 23:46:51.991096 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass>
9028 23:46:51.991363 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_53 RESULT=pass
9030 23:46:52.029480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass>
9031 23:46:52.029749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_53 RESULT=pass
9033 23:46:52.066253 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass>
9034 23:46:52.066518 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_53 RESULT=pass
9036 23:46:52.097954 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass
9038 23:46:52.100902 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_52 RESULT=pass>
9039 23:46:52.133804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail>
9040 23:46:52.134070 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_52 RESULT=fail
9042 23:46:52.174752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass>
9043 23:46:52.175022 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_52 RESULT=pass
9045 23:46:52.212507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass>
9046 23:46:52.212808 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_52 RESULT=pass
9048 23:46:52.256677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass>
9049 23:46:52.256944 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_52 RESULT=pass
9051 23:46:52.293936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass>
9052 23:46:52.294209 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_52 RESULT=pass
9054 23:46:52.337129 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass>
9055 23:46:52.337399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_52 RESULT=pass
9057 23:46:52.380901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass>
9058 23:46:52.381175 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_51 RESULT=pass
9060 23:46:52.418435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail>
9061 23:46:52.418769 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_51 RESULT=fail
9063 23:46:52.459849 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass>
9064 23:46:52.460160 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_51 RESULT=pass
9066 23:46:52.497807 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass>
9067 23:46:52.498217 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_51 RESULT=pass
9069 23:46:52.546131 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass>
9070 23:46:52.547001 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_51 RESULT=pass
9072 23:46:52.592486 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass>
9073 23:46:52.593199 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_51 RESULT=pass
9075 23:46:52.641240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass>
9076 23:46:52.642038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_51 RESULT=pass
9078 23:46:52.689101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass>
9079 23:46:52.689907 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_50 RESULT=pass
9081 23:46:52.734081 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail>
9082 23:46:52.734761 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_50 RESULT=fail
9084 23:46:52.786879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass>
9085 23:46:52.787593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_50 RESULT=pass
9087 23:46:52.834736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass>
9088 23:46:52.835510 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_50 RESULT=pass
9090 23:46:52.881785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass>
9091 23:46:52.882561 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_50 RESULT=pass
9093 23:46:52.924792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass>
9094 23:46:52.925169 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_50 RESULT=pass
9096 23:46:52.958503 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass>
9097 23:46:52.958885 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_50 RESULT=pass
9099 23:46:52.995392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass>
9100 23:46:52.995923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_49 RESULT=pass
9102 23:46:53.032134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail>
9103 23:46:53.032560 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_49 RESULT=fail
9105 23:46:53.077440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass>
9106 23:46:53.077863 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_49 RESULT=pass
9108 23:46:53.115414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass>
9109 23:46:53.115825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_49 RESULT=pass
9111 23:46:53.151048 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass>
9112 23:46:53.151381 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_49 RESULT=pass
9114 23:46:53.188324 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass>
9115 23:46:53.188605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_49 RESULT=pass
9117 23:46:53.229484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass>
9118 23:46:53.229818 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_49 RESULT=pass
9120 23:46:53.277060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass>
9121 23:46:53.277752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_48 RESULT=pass
9123 23:46:53.322062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail>
9124 23:46:53.322803 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_48 RESULT=fail
9126 23:46:53.371462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass>
9127 23:46:53.372201 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_48 RESULT=pass
9129 23:46:53.419509 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass>
9130 23:46:53.419822 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_48 RESULT=pass
9132 23:46:53.463573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass>
9133 23:46:53.463850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_48 RESULT=pass
9135 23:46:53.503860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass>
9136 23:46:53.504145 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_48 RESULT=pass
9138 23:46:53.548333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass>
9139 23:46:53.548605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_48 RESULT=pass
9141 23:46:53.587617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass>
9142 23:46:53.587886 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_47 RESULT=pass
9144 23:46:53.624141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail>
9145 23:46:53.624437 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_47 RESULT=fail
9147 23:46:53.669730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass>
9148 23:46:53.670091 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_47 RESULT=pass
9150 23:46:53.706286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass>
9151 23:46:53.706632 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_47 RESULT=pass
9153 23:46:53.744622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass>
9154 23:46:53.744965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_47 RESULT=pass
9156 23:46:53.778976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass>
9157 23:46:53.779309 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_47 RESULT=pass
9159 23:46:53.812217 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass>
9160 23:46:53.812505 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_47 RESULT=pass
9162 23:46:53.846773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass>
9163 23:46:53.847128 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_46 RESULT=pass
9165 23:46:53.876611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail>
9166 23:46:53.876948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_46 RESULT=fail
9168 23:46:53.920480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass>
9169 23:46:53.920798 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_46 RESULT=pass
9171 23:46:53.957031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass>
9172 23:46:53.957339 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_46 RESULT=pass
9174 23:46:53.988565 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass>
9175 23:46:53.988900 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_46 RESULT=pass
9177 23:46:54.024484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass>
9178 23:46:54.024794 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_46 RESULT=pass
9180 23:46:54.059152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass>
9181 23:46:54.059430 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_46 RESULT=pass
9183 23:46:54.095119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass>
9184 23:46:54.095425 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_45 RESULT=pass
9186 23:46:54.131675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail>
9187 23:46:54.131947 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_45 RESULT=fail
9189 23:46:54.175830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass>
9190 23:46:54.176095 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_45 RESULT=pass
9192 23:46:54.217724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass>
9193 23:46:54.217993 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_45 RESULT=pass
9195 23:46:54.254477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass>
9196 23:46:54.254741 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_45 RESULT=pass
9198 23:46:54.292069 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass>
9199 23:46:54.292338 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_45 RESULT=pass
9201 23:46:54.329936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass>
9202 23:46:54.330206 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_45 RESULT=pass
9204 23:46:54.366536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass>
9205 23:46:54.366802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_44 RESULT=pass
9207 23:46:54.403097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail>
9208 23:46:54.403369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_44 RESULT=fail
9210 23:46:54.448683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass>
9211 23:46:54.448948 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_44 RESULT=pass
9213 23:46:54.487725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass>
9214 23:46:54.487994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_44 RESULT=pass
9216 23:46:54.528060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass>
9217 23:46:54.528354 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_44 RESULT=pass
9219 23:46:54.562713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass>
9220 23:46:54.563000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_44 RESULT=pass
9222 23:46:54.595653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass>
9223 23:46:54.595929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_44 RESULT=pass
9225 23:46:54.635078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass>
9226 23:46:54.635345 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_43 RESULT=pass
9228 23:46:54.672616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail>
9229 23:46:54.672923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_43 RESULT=fail
9231 23:46:54.715493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass>
9232 23:46:54.715786 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_43 RESULT=pass
9234 23:46:54.755374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass>
9235 23:46:54.755655 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_43 RESULT=pass
9237 23:46:54.796450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass>
9238 23:46:54.796725 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_43 RESULT=pass
9240 23:46:54.839205 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass>
9241 23:46:54.839478 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_43 RESULT=pass
9243 23:46:54.879068 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass>
9244 23:46:54.879371 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_43 RESULT=pass
9246 23:46:54.917301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass>
9247 23:46:54.917570 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_42 RESULT=pass
9249 23:46:54.952330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail>
9250 23:46:54.952616 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_42 RESULT=fail
9252 23:46:54.994591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass>
9253 23:46:54.994865 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_42 RESULT=pass
9255 23:46:55.032135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass>
9256 23:46:55.032412 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_42 RESULT=pass
9258 23:46:55.072869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass>
9259 23:46:55.073149 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_42 RESULT=pass
9261 23:46:55.108879 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass>
9262 23:46:55.109155 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_42 RESULT=pass
9264 23:46:55.146319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass>
9265 23:46:55.146597 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_42 RESULT=pass
9267 23:46:55.188386 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass>
9268 23:46:55.188667 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_41 RESULT=pass
9270 23:46:55.219006 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail>
9271 23:46:55.219281 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_41 RESULT=fail
9273 23:46:55.260688 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass>
9274 23:46:55.260963 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_41 RESULT=pass
9276 23:46:55.299882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass>
9277 23:46:55.300163 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_41 RESULT=pass
9279 23:46:55.338024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass>
9280 23:46:55.338320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_41 RESULT=pass
9282 23:46:55.374822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass>
9283 23:46:55.375126 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_41 RESULT=pass
9285 23:46:55.413589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass>
9286 23:46:55.413869 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_41 RESULT=pass
9288 23:46:55.449426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass
9290 23:46:55.452343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_40 RESULT=pass>
9291 23:46:55.483530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail>
9292 23:46:55.483801 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_40 RESULT=fail
9294 23:46:55.527223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass>
9295 23:46:55.527532 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_40 RESULT=pass
9297 23:46:55.563167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass>
9298 23:46:55.563426 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_40 RESULT=pass
9300 23:46:55.602919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass>
9301 23:46:55.603212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_40 RESULT=pass
9303 23:46:55.641696 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass>
9304 23:46:55.641983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_40 RESULT=pass
9306 23:46:55.680119 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass>
9307 23:46:55.680438 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_40 RESULT=pass
9309 23:46:55.720489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass>
9310 23:46:55.720774 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_39 RESULT=pass
9312 23:46:55.756209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail>
9313 23:46:55.756480 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_39 RESULT=fail
9315 23:46:55.798868 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass>
9316 23:46:55.799178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_39 RESULT=pass
9318 23:46:55.838525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass>
9319 23:46:55.838802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_39 RESULT=pass
9321 23:46:55.879629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass>
9322 23:46:55.879914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_39 RESULT=pass
9324 23:46:55.919520 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass>
9325 23:46:55.919825 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_39 RESULT=pass
9327 23:46:55.960734 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass>
9328 23:46:55.961012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_39 RESULT=pass
9330 23:46:56.000760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass>
9331 23:46:56.001035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_38 RESULT=pass
9333 23:46:56.035374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail>
9334 23:46:56.035660 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_38 RESULT=fail
9336 23:46:56.073517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass>
9337 23:46:56.073797 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_38 RESULT=pass
9339 23:46:56.114221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass>
9340 23:46:56.114497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_38 RESULT=pass
9342 23:46:56.166714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass>
9343 23:46:56.167002 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_38 RESULT=pass
9345 23:46:56.220822 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass>
9346 23:46:56.221101 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_38 RESULT=pass
9348 23:46:56.275656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass>
9349 23:46:56.275946 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_38 RESULT=pass
9351 23:46:56.328939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass>
9352 23:46:56.329219 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_37 RESULT=pass
9354 23:46:56.365373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail>
9355 23:46:56.365647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_37 RESULT=fail
9357 23:46:56.406453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass>
9358 23:46:56.406750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_37 RESULT=pass
9360 23:46:56.446480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass>
9361 23:46:56.446752 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_37 RESULT=pass
9363 23:46:56.482701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass>
9364 23:46:56.483018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_37 RESULT=pass
9366 23:46:56.523247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass>
9367 23:46:56.523549 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_37 RESULT=pass
9369 23:46:56.560342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass>
9370 23:46:56.560615 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_37 RESULT=pass
9372 23:46:56.602597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass>
9373 23:46:56.602874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_36 RESULT=pass
9375 23:46:56.639721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail>
9376 23:46:56.640021 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_36 RESULT=fail
9378 23:46:56.690925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass>
9379 23:46:56.691266 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_36 RESULT=pass
9381 23:46:56.730028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass>
9382 23:46:56.730307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_36 RESULT=pass
9384 23:46:56.769580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass>
9385 23:46:56.769882 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_36 RESULT=pass
9387 23:46:56.807990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass>
9388 23:46:56.808271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_36 RESULT=pass
9390 23:46:56.846875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass>
9391 23:46:56.847146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_36 RESULT=pass
9393 23:46:56.885480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass>
9394 23:46:56.885758 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_35 RESULT=pass
9396 23:46:56.918711 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail>
9397 23:46:56.918991 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_35 RESULT=fail
9399 23:46:56.959321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass>
9400 23:46:56.959612 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_35 RESULT=pass
9402 23:46:56.997301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass>
9403 23:46:56.997583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_35 RESULT=pass
9405 23:46:57.039090 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass>
9406 23:46:57.039373 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_35 RESULT=pass
9408 23:46:57.079027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass>
9409 23:46:57.079332 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_35 RESULT=pass
9411 23:46:57.120167 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass>
9412 23:46:57.120445 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_35 RESULT=pass
9414 23:46:57.159100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass>
9415 23:46:57.159374 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_34 RESULT=pass
9417 23:46:57.191303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail>
9418 23:46:57.191614 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_34 RESULT=fail
9420 23:46:57.231584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass>
9421 23:46:57.231862 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_34 RESULT=pass
9423 23:46:57.274009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass>
9424 23:46:57.274293 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_34 RESULT=pass
9426 23:46:57.312513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass>
9427 23:46:57.312783 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_34 RESULT=pass
9429 23:46:57.357683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass>
9430 23:46:57.357955 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_34 RESULT=pass
9432 23:46:57.394706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass>
9433 23:46:57.394983 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_34 RESULT=pass
9435 23:46:57.433769 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass>
9436 23:46:57.434079 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_33 RESULT=pass
9438 23:46:57.469144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail>
9439 23:46:57.469423 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_33 RESULT=fail
9441 23:46:57.510157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass>
9442 23:46:57.510434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_33 RESULT=pass
9444 23:46:57.550495 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass>
9445 23:46:57.550766 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_33 RESULT=pass
9447 23:46:57.590153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass>
9448 23:46:57.590431 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_33 RESULT=pass
9450 23:46:57.632040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass>
9451 23:46:57.632310 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_33 RESULT=pass
9453 23:46:57.670013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass>
9454 23:46:57.670297 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_33 RESULT=pass
9456 23:46:57.705557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass>
9457 23:46:57.705896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_32 RESULT=pass
9459 23:46:57.736421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail>
9460 23:46:57.736694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_32 RESULT=fail
9462 23:46:57.779805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass>
9463 23:46:57.780081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_32 RESULT=pass
9465 23:46:57.818907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass>
9466 23:46:57.819178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_32 RESULT=pass
9468 23:46:57.857044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass>
9469 23:46:57.857313 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_32 RESULT=pass
9471 23:46:57.897987 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass>
9472 23:46:57.898271 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_32 RESULT=pass
9474 23:46:57.940651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass>
9475 23:46:57.940923 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_32 RESULT=pass
9477 23:46:57.979130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass>
9478 23:46:57.979401 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_31 RESULT=pass
9480 23:46:58.018182 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail>
9481 23:46:58.018459 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_31 RESULT=fail
9483 23:46:58.060829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass>
9484 23:46:58.061100 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_31 RESULT=pass
9486 23:46:58.099701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass>
9487 23:46:58.099977 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_31 RESULT=pass
9489 23:46:58.137767 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass>
9490 23:46:58.138040 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_31 RESULT=pass
9492 23:46:58.174215 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass>
9493 23:46:58.174491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_31 RESULT=pass
9495 23:46:58.218365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass>
9496 23:46:58.218647 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_31 RESULT=pass
9498 23:46:58.254859 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass>
9499 23:46:58.255176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_30 RESULT=pass
9501 23:46:58.291447 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail>
9502 23:46:58.291739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_30 RESULT=fail
9504 23:46:58.332589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass>
9505 23:46:58.332867 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_30 RESULT=pass
9507 23:46:58.373919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass>
9508 23:46:58.374188 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_30 RESULT=pass
9510 23:46:58.410890 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass>
9511 23:46:58.411176 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_30 RESULT=pass
9513 23:46:58.447026 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass>
9514 23:46:58.447307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_30 RESULT=pass
9516 23:46:58.481117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass>
9517 23:46:58.481399 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_30 RESULT=pass
9519 23:46:58.517952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass>
9520 23:46:58.518251 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_29 RESULT=pass
9522 23:46:58.553342 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass>
9523 23:46:58.553617 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_29 RESULT=pass
9525 23:46:58.595851 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass>
9526 23:46:58.596139 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_29 RESULT=pass
9528 23:46:58.633699 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass>
9529 23:46:58.633977 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_29 RESULT=pass
9531 23:46:58.675901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass>
9532 23:46:58.676179 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_29 RESULT=pass
9534 23:46:58.715062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass>
9535 23:46:58.715387 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_29 RESULT=pass
9537 23:46:58.755271 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass>
9538 23:46:58.755594 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_29 RESULT=pass
9540 23:46:58.793798 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass>
9541 23:46:58.794081 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_28 RESULT=pass
9543 23:46:58.832309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass>
9544 23:46:58.832586 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_28 RESULT=pass
9546 23:46:58.872008 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass>
9547 23:46:58.872318 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_28 RESULT=pass
9549 23:46:58.907005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass>
9550 23:46:58.907288 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_28 RESULT=pass
9552 23:46:58.944193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass>
9553 23:46:58.944465 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_28 RESULT=pass
9555 23:46:58.980668 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass>
9556 23:46:58.980942 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_28 RESULT=pass
9558 23:46:59.014713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass>
9559 23:46:59.015048 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_28 RESULT=pass
9561 23:46:59.050933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass>
9562 23:46:59.051256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_27 RESULT=pass
9564 23:46:59.084314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass>
9565 23:46:59.084605 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_27 RESULT=pass
9567 23:46:59.126573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass>
9568 23:46:59.126849 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_27 RESULT=pass
9570 23:46:59.168484 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass>
9571 23:46:59.168763 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_27 RESULT=pass
9573 23:46:59.205817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass>
9574 23:46:59.206094 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_27 RESULT=pass
9576 23:46:59.246539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass>
9577 23:46:59.246811 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_27 RESULT=pass
9579 23:46:59.285203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass>
9580 23:46:59.285482 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_27 RESULT=pass
9582 23:46:59.320157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass>
9583 23:46:59.320436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_26 RESULT=pass
9585 23:46:59.353212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass>
9586 23:46:59.353519 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_26 RESULT=pass
9588 23:46:59.391214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass>
9589 23:46:59.391531 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_26 RESULT=pass
9591 23:46:59.430441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass>
9592 23:46:59.430748 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_26 RESULT=pass
9594 23:46:59.464929 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass>
9595 23:46:59.465212 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_26 RESULT=pass
9597 23:46:59.500290 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass>
9598 23:46:59.500606 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_26 RESULT=pass
9600 23:46:59.536977 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass>
9601 23:46:59.537261 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_26 RESULT=pass
9603 23:46:59.571836 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass>
9604 23:46:59.572114 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_25 RESULT=pass
9606 23:46:59.606389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass>
9607 23:46:59.606669 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_25 RESULT=pass
9609 23:46:59.643393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass>
9610 23:46:59.643677 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_25 RESULT=pass
9612 23:46:59.677357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass>
9613 23:46:59.677633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_25 RESULT=pass
9615 23:46:59.712078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass>
9616 23:46:59.712369 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_25 RESULT=pass
9618 23:46:59.749268 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass>
9619 23:46:59.749571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_25 RESULT=pass
9621 23:46:59.784404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass>
9622 23:46:59.784770 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_25 RESULT=pass
9624 23:46:59.820183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass>
9625 23:46:59.820523 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_24 RESULT=pass
9627 23:46:59.850720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass>
9628 23:46:59.850998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_24 RESULT=pass
9630 23:46:59.890469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass>
9631 23:46:59.890788 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_24 RESULT=pass
9633 23:46:59.922957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass>
9634 23:46:59.923264 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_24 RESULT=pass
9636 23:46:59.958815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass>
9637 23:46:59.959088 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_24 RESULT=pass
9639 23:46:59.993678 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass>
9640 23:46:59.993989 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_24 RESULT=pass
9642 23:47:00.029866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass>
9643 23:47:00.030168 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_24 RESULT=pass
9645 23:47:00.066027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass>
9646 23:47:00.066303 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_23 RESULT=pass
9648 23:47:00.095761 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass>
9649 23:47:00.096038 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_23 RESULT=pass
9651 23:47:00.133544 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass>
9652 23:47:00.133853 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_23 RESULT=pass
9654 23:47:00.168469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass>
9655 23:47:00.168749 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_23 RESULT=pass
9657 23:47:00.205726 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass>
9658 23:47:00.206032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_23 RESULT=pass
9660 23:47:00.243166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass>
9661 23:47:00.243433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_23 RESULT=pass
9663 23:47:00.277446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass>
9664 23:47:00.277731 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_23 RESULT=pass
9666 23:47:00.319013 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass>
9667 23:47:00.319286 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_22 RESULT=pass
9669 23:47:00.348322 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass>
9670 23:47:00.348593 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_22 RESULT=pass
9672 23:47:00.388514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass>
9673 23:47:00.388789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_22 RESULT=pass
9675 23:47:00.424025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass>
9676 23:47:00.424295 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_22 RESULT=pass
9678 23:47:00.461837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass>
9679 23:47:00.462146 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_22 RESULT=pass
9681 23:47:00.496389 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass>
9682 23:47:00.496661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_22 RESULT=pass
9684 23:47:00.531037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass>
9685 23:47:00.531307 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_22 RESULT=pass
9687 23:47:00.567922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass>
9688 23:47:00.568197 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_21 RESULT=pass
9690 23:47:00.599364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail>
9691 23:47:00.599673 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_21 RESULT=fail
9693 23:47:00.637005 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass>
9694 23:47:00.637329 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_21 RESULT=pass
9696 23:47:00.669233 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass>
9697 23:47:00.669534 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_21 RESULT=pass
9699 23:47:00.705701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass>
9700 23:47:00.706003 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_21 RESULT=pass
9702 23:47:00.747203 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass>
9703 23:47:00.747481 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_21 RESULT=pass
9705 23:47:00.783830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass>
9706 23:47:00.784108 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_21 RESULT=pass
9708 23:47:00.818403 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass>
9709 23:47:00.818694 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_20 RESULT=pass
9711 23:47:00.852788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail>
9712 23:47:00.853118 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_20 RESULT=fail
9714 23:47:00.891918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass>
9715 23:47:00.892242 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_20 RESULT=pass
9717 23:47:00.928917 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass>
9718 23:47:00.929205 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_20 RESULT=pass
9720 23:47:00.966647 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass>
9721 23:47:00.966929 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_20 RESULT=pass
9723 23:47:01.003002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass>
9724 23:47:01.003316 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_20 RESULT=pass
9726 23:47:01.039411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass>
9727 23:47:01.039696 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_20 RESULT=pass
9729 23:47:01.079091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass>
9730 23:47:01.079394 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_19 RESULT=pass
9732 23:47:01.115376 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail>
9733 23:47:01.115701 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_19 RESULT=fail
9735 23:47:01.156194 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass>
9736 23:47:01.156474 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_19 RESULT=pass
9738 23:47:01.194507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass>
9739 23:47:01.194789 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_19 RESULT=pass
9741 23:47:01.231622 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass>
9742 23:47:01.231896 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_19 RESULT=pass
9744 23:47:01.265066 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass>
9745 23:47:01.265336 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_19 RESULT=pass
9747 23:47:01.300149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass>
9748 23:47:01.300424 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_19 RESULT=pass
9750 23:47:01.339073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass>
9751 23:47:01.339355 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_18 RESULT=pass
9753 23:47:01.375948 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail>
9754 23:47:01.376223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_18 RESULT=fail
9756 23:47:01.421195 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass>
9757 23:47:01.421475 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_18 RESULT=pass
9759 23:47:01.461609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass>
9760 23:47:01.461879 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_18 RESULT=pass
9762 23:47:01.501153 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass>
9763 23:47:01.501458 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_18 RESULT=pass
9765 23:47:01.544864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass>
9766 23:47:01.545171 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_18 RESULT=pass
9768 23:47:01.581866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass>
9769 23:47:01.582177 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_18 RESULT=pass
9771 23:47:01.621899 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass>
9772 23:47:01.622178 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_17 RESULT=pass
9774 23:47:01.659127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail>
9775 23:47:01.659436 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_17 RESULT=fail
9777 23:47:01.699956 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass>
9778 23:47:01.700234 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_17 RESULT=pass
9780 23:47:01.734328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass>
9781 23:47:01.734602 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_17 RESULT=pass
9783 23:47:01.771835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass>
9784 23:47:01.772144 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_17 RESULT=pass
9786 23:47:01.808910 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass>
9787 23:47:01.809223 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_17 RESULT=pass
9789 23:47:01.847165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass>
9790 23:47:01.847434 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_17 RESULT=pass
9792 23:47:01.885960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass>
9793 23:47:01.886256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_16 RESULT=pass
9795 23:47:01.920335 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail>
9796 23:47:01.920608 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_16 RESULT=fail
9798 23:47:01.959314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass>
9799 23:47:01.959644 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_16 RESULT=pass
9801 23:47:01.997063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass>
9802 23:47:01.997375 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_16 RESULT=pass
9804 23:47:02.031437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass>
9805 23:47:02.031709 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_16 RESULT=pass
9807 23:47:02.068792 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass>
9808 23:47:02.069065 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_16 RESULT=pass
9810 23:47:02.103687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass>
9811 23:47:02.103959 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_16 RESULT=pass
9813 23:47:02.138208 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass>
9814 23:47:02.138484 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_15 RESULT=pass
9816 23:47:02.168689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail>
9817 23:47:02.168957 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_15 RESULT=fail
9819 23:47:02.206686 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass>
9820 23:47:02.206999 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_15 RESULT=pass
9822 23:47:02.241074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass>
9823 23:47:02.241383 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_15 RESULT=pass
9825 23:47:02.276547 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass>
9826 23:47:02.276850 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_15 RESULT=pass
9828 23:47:02.311176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass>
9829 23:47:02.311490 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_15 RESULT=pass
9831 23:47:02.348107 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass>
9832 23:47:02.348391 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_15 RESULT=pass
9834 23:47:02.387954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass>
9835 23:47:02.388258 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_14 RESULT=pass
9837 23:47:02.419915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail>
9838 23:47:02.420245 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_14 RESULT=fail
9840 23:47:02.459308 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass>
9841 23:47:02.459624 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_14 RESULT=pass
9843 23:47:02.495925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass>
9844 23:47:02.496193 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_14 RESULT=pass
9846 23:47:02.535617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass>
9847 23:47:02.535919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_14 RESULT=pass
9849 23:47:02.571659 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass>
9850 23:47:02.571958 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_14 RESULT=pass
9852 23:47:02.608508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass>
9853 23:47:02.608819 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_14 RESULT=pass
9855 23:47:02.650391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass>
9856 23:47:02.650699 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_13 RESULT=pass
9858 23:47:02.690440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail>
9859 23:47:02.690743 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_13 RESULT=fail
9861 23:47:02.732594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass>
9862 23:47:02.732895 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_13 RESULT=pass
9864 23:47:02.769329 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass>
9865 23:47:02.769627 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_13 RESULT=pass
9867 23:47:02.805570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass>
9868 23:47:02.805874 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_13 RESULT=pass
9870 23:47:02.843955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass>
9871 23:47:02.844267 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_13 RESULT=pass
9873 23:47:02.882133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass>
9874 23:47:02.882462 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_13 RESULT=pass
9876 23:47:02.915049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass>
9877 23:47:02.915372 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_12 RESULT=pass
9879 23:47:02.947067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail>
9880 23:47:02.947370 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_12 RESULT=fail
9882 23:47:02.984682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass>
9883 23:47:02.984998 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_12 RESULT=pass
9885 23:47:03.022457 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass>
9886 23:47:03.022739 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_12 RESULT=pass
9888 23:47:03.058573 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass>
9889 23:47:03.058861 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_12 RESULT=pass
9891 23:47:03.102685 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass>
9892 23:47:03.102965 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_12 RESULT=pass
9894 23:47:03.138058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass>
9895 23:47:03.138361 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_12 RESULT=pass
9897 23:47:03.172521 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass>
9898 23:47:03.172827 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_11 RESULT=pass
9900 23:47:03.205024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail>
9901 23:47:03.205347 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_11 RESULT=fail
9903 23:47:03.244393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass>
9904 23:47:03.244661 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_11 RESULT=pass
9906 23:47:03.281287 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass>
9907 23:47:03.281601 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_11 RESULT=pass
9909 23:47:03.319468 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass>
9910 23:47:03.319742 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_11 RESULT=pass
9912 23:47:03.357053 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass>
9913 23:47:03.357368 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_11 RESULT=pass
9915 23:47:03.395031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass>
9916 23:47:03.395360 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_11 RESULT=pass
9918 23:47:03.434388 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass>
9919 23:47:03.434663 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_10 RESULT=pass
9921 23:47:03.468538 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail>
9922 23:47:03.468821 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_10 RESULT=fail
9924 23:47:03.509101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass>
9925 23:47:03.509411 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_10 RESULT=pass
9927 23:47:03.546752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass>
9928 23:47:03.547034 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_10 RESULT=pass
9930 23:47:03.581637 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass>
9931 23:47:03.581945 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_10 RESULT=pass
9933 23:47:03.618176 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass>
9934 23:47:03.618491 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_10 RESULT=pass
9936 23:47:03.653828 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass>
9937 23:47:03.654102 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_10 RESULT=pass
9939 23:47:03.686298 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass
9941 23:47:03.688927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_9 RESULT=pass>
9942 23:47:03.720285 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail>
9943 23:47:03.720583 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_9 RESULT=fail
9945 23:47:03.761302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass>
9946 23:47:03.761582 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_9 RESULT=pass
9948 23:47:03.799735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass>
9949 23:47:03.800004 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_9 RESULT=pass
9951 23:47:03.837030 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass>
9952 23:47:03.837308 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_9 RESULT=pass
9954 23:47:03.874662 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass>
9955 23:47:03.874935 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_9 RESULT=pass
9957 23:47:03.908736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass>
9958 23:47:03.909018 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_9 RESULT=pass
9960 23:47:03.947168 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass>
9961 23:47:03.947501 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_8 RESULT=pass
9963 23:47:03.978926 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail>
9964 23:47:03.979256 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_8 RESULT=fail
9966 23:47:04.019031 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass>
9967 23:47:04.019342 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_8 RESULT=pass
9969 23:47:04.056601 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass>
9970 23:47:04.056889 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_8 RESULT=pass
9972 23:47:04.095825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass>
9973 23:47:04.096109 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_8 RESULT=pass
9975 23:47:04.133351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass>
9976 23:47:04.133649 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_8 RESULT=pass
9978 23:47:04.167980 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass>
9979 23:47:04.168319 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_8 RESULT=pass
9981 23:47:04.196497 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass
9983 23:47:04.200040 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_7 RESULT=pass>
9984 23:47:04.229683 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail>
9985 23:47:04.230032 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_7 RESULT=fail
9987 23:47:04.265063 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass>
9988 23:47:04.265350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_7 RESULT=pass
9990 23:47:04.301135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass>
9991 23:47:04.301452 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_7 RESULT=pass
9993 23:47:04.334054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass>
9994 23:47:04.334359 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_7 RESULT=pass
9996 23:47:04.370424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass>
9997 23:47:04.370718 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_7 RESULT=pass
9999 23:47:04.407424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass>
10000 23:47:04.407750 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_7 RESULT=pass
10002 23:47:04.442667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass>
10003 23:47:04.442961 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_6 RESULT=pass
10005 23:47:04.475587 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail>
10006 23:47:04.475884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_6 RESULT=fail
10008 23:47:04.513809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass>
10009 23:47:04.514142 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_6 RESULT=pass
10011 23:47:04.548545 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass>
10012 23:47:04.548823 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_6 RESULT=pass
10014 23:47:04.584525 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass>
10015 23:47:04.584806 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_6 RESULT=pass
10017 23:47:04.621887 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass>
10018 23:47:04.622161 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_6 RESULT=pass
10020 23:47:04.655429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass>
10021 23:47:04.655700 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_6 RESULT=pass
10023 23:47:04.689903 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass
10025 23:47:04.693191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_5 RESULT=pass>
10026 23:47:04.726581 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass>
10027 23:47:04.726855 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_5 RESULT=pass
10029 23:47:04.765364 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass>
10030 23:47:04.765633 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_5 RESULT=pass
10032 23:47:04.800983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass>
10033 23:47:04.801259 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_5 RESULT=pass
10035 23:47:04.837298 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass>
10036 23:47:04.837571 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_5 RESULT=pass
10038 23:47:04.874725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail>
10039 23:47:04.874994 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_5 RESULT=fail
10041 23:47:04.910633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass>
10042 23:47:04.910919 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_5 RESULT=pass
10044 23:47:04.944724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass>
10045 23:47:04.945000 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_4 RESULT=pass
10047 23:47:04.973757 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass>
10048 23:47:04.974026 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_4 RESULT=pass
10050 23:47:05.012027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass>
10051 23:47:05.012320 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_4 RESULT=pass
10053 23:47:05.048857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass>
10054 23:47:05.049185 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_4 RESULT=pass
10056 23:47:05.081062 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass>
10057 23:47:05.081333 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_4 RESULT=pass
10059 23:47:05.114331 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail>
10060 23:47:05.114631 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_4 RESULT=fail
10062 23:47:05.152702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass>
10063 23:47:05.153011 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_4 RESULT=pass
10065 23:47:05.186146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass>
10066 23:47:05.186455 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_3 RESULT=pass
10068 23:47:05.218824 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass>
10069 23:47:05.219141 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_3 RESULT=pass
10071 23:47:05.259163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass>
10072 23:47:05.259433 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_3 RESULT=pass
10074 23:47:05.295344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass>
10075 23:47:05.295702 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_3 RESULT=pass
10077 23:47:05.330689 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass>
10078 23:47:05.330966 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_3 RESULT=pass
10080 23:47:05.367527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail>
10081 23:47:05.367817 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_3 RESULT=fail
10083 23:47:05.408582 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass>
10084 23:47:05.408884 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_3 RESULT=pass
10086 23:47:05.441610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass>
10087 23:47:05.441914 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_2 RESULT=pass
10089 23:47:05.477564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass>
10090 23:47:05.477883 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_2 RESULT=pass
10092 23:47:05.522150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass>
10093 23:47:05.522457 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_2 RESULT=pass
10095 23:47:05.562712 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass>
10096 23:47:05.563035 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_2 RESULT=pass
10098 23:47:05.599732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass>
10099 23:47:05.600005 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_2 RESULT=pass
10101 23:47:05.638897 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail>
10102 23:47:05.639180 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_2 RESULT=fail
10104 23:47:05.676493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass>
10105 23:47:05.676802 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_2 RESULT=pass
10107 23:47:05.713651 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass>
10108 23:47:05.713977 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_1 RESULT=pass
10110 23:47:05.744991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass>
10111 23:47:05.745263 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_1 RESULT=pass
10113 23:47:05.785441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass>
10114 23:47:05.785715 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_1 RESULT=pass
10116 23:47:05.819360 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass>
10117 23:47:05.819651 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_1 RESULT=pass
10119 23:47:05.860740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass>
10120 23:47:05.861012 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_1 RESULT=pass
10122 23:47:05.895473 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail>
10123 23:47:05.895744 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_1 RESULT=fail
10125 23:47:05.931319 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass>
10126 23:47:05.931626 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_1 RESULT=pass
10128 23:47:05.966350 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass
10130 23:47:05.969663 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_get_value_0_0 RESULT=pass>
10131 23:47:06.006077 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass>
10132 23:47:06.006382 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_name_0_0 RESULT=pass
10134 23:47:06.049636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass>
10135 23:47:06.049928 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_default_0_0 RESULT=pass
10137 23:47:06.083684 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass>
10138 23:47:06.083984 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_valid_0_0 RESULT=pass
10140 23:47:06.117616 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass>
10141 23:47:06.117890 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_write_invalid_0_0 RESULT=pass
10143 23:47:06.154458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail>
10144 23:47:06.154729 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_missing_0_0 RESULT=fail
10146 23:47:06.191805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass>
10147 23:47:06.192082 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test_event_spurious_0_0 RESULT=pass
10149 23:47:06.227029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10150 23:47:06.227130 + set +x
10151 23:47:06.227376 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10153 23:47:06.233433 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14172940_1.6.2.3.5>
10154 23:47:06.233703 Received signal: <ENDRUN> 1_kselftest-alsa 14172940_1.6.2.3.5
10155 23:47:06.233787 Ending use of test pattern.
10156 23:47:06.233856 Ending test lava.1_kselftest-alsa (14172940_1.6.2.3.5), duration 38.35
10158 23:47:06.236963 <LAVA_TEST_RUNNER EXIT>
10159 23:47:06.237221 ok: lava_test_shell seems to have completed
10160 23:47:06.241102 alsa_mixer-test: pass
alsa_mixer-test_event_missing_0_0: fail
alsa_mixer-test_event_missing_0_1: fail
alsa_mixer-test_event_missing_0_10: pass
alsa_mixer-test_event_missing_0_11: pass
alsa_mixer-test_event_missing_0_12: pass
alsa_mixer-test_event_missing_0_13: pass
alsa_mixer-test_event_missing_0_14: pass
alsa_mixer-test_event_missing_0_15: pass
alsa_mixer-test_event_missing_0_16: pass
alsa_mixer-test_event_missing_0_17: pass
alsa_mixer-test_event_missing_0_18: pass
alsa_mixer-test_event_missing_0_19: pass
alsa_mixer-test_event_missing_0_2: fail
alsa_mixer-test_event_missing_0_20: pass
alsa_mixer-test_event_missing_0_21: pass
alsa_mixer-test_event_missing_0_22: pass
alsa_mixer-test_event_missing_0_23: pass
alsa_mixer-test_event_missing_0_24: pass
alsa_mixer-test_event_missing_0_25: pass
alsa_mixer-test_event_missing_0_26: pass
alsa_mixer-test_event_missing_0_27: pass
alsa_mixer-test_event_missing_0_28: pass
alsa_mixer-test_event_missing_0_29: pass
alsa_mixer-test_event_missing_0_3: fail
alsa_mixer-test_event_missing_0_30: pass
alsa_mixer-test_event_missing_0_31: pass
alsa_mixer-test_event_missing_0_32: pass
alsa_mixer-test_event_missing_0_33: pass
alsa_mixer-test_event_missing_0_34: pass
alsa_mixer-test_event_missing_0_35: pass
alsa_mixer-test_event_missing_0_36: pass
alsa_mixer-test_event_missing_0_37: pass
alsa_mixer-test_event_missing_0_38: pass
alsa_mixer-test_event_missing_0_39: pass
alsa_mixer-test_event_missing_0_4: fail
alsa_mixer-test_event_missing_0_40: pass
alsa_mixer-test_event_missing_0_41: pass
alsa_mixer-test_event_missing_0_42: pass
alsa_mixer-test_event_missing_0_43: pass
alsa_mixer-test_event_missing_0_44: pass
alsa_mixer-test_event_missing_0_45: pass
alsa_mixer-test_event_missing_0_46: pass
alsa_mixer-test_event_missing_0_47: pass
alsa_mixer-test_event_missing_0_48: pass
alsa_mixer-test_event_missing_0_49: pass
alsa_mixer-test_event_missing_0_5: fail
alsa_mixer-test_event_missing_0_50: pass
alsa_mixer-test_event_missing_0_51: pass
alsa_mixer-test_event_missing_0_52: pass
alsa_mixer-test_event_missing_0_53: pass
alsa_mixer-test_event_missing_0_54: pass
alsa_mixer-test_event_missing_0_55: pass
alsa_mixer-test_event_missing_0_56: pass
alsa_mixer-test_event_missing_0_57: pass
alsa_mixer-test_event_missing_0_58: pass
alsa_mixer-test_event_missing_0_59: pass
alsa_mixer-test_event_missing_0_6: pass
alsa_mixer-test_event_missing_0_60: pass
alsa_mixer-test_event_missing_0_61: pass
alsa_mixer-test_event_missing_0_62: pass
alsa_mixer-test_event_missing_0_63: pass
alsa_mixer-test_event_missing_0_64: pass
alsa_mixer-test_event_missing_0_65: pass
alsa_mixer-test_event_missing_0_66: pass
alsa_mixer-test_event_missing_0_67: pass
alsa_mixer-test_event_missing_0_68: pass
alsa_mixer-test_event_missing_0_69: pass
alsa_mixer-test_event_missing_0_7: pass
alsa_mixer-test_event_missing_0_70: pass
alsa_mixer-test_event_missing_0_71: pass
alsa_mixer-test_event_missing_0_72: pass
alsa_mixer-test_event_missing_0_73: pass
alsa_mixer-test_event_missing_0_74: pass
alsa_mixer-test_event_missing_0_75: pass
alsa_mixer-test_event_missing_0_76: pass
alsa_mixer-test_event_missing_0_77: pass
alsa_mixer-test_event_missing_0_78: pass
alsa_mixer-test_event_missing_0_79: pass
alsa_mixer-test_event_missing_0_8: pass
alsa_mixer-test_event_missing_0_80: pass
alsa_mixer-test_event_missing_0_81: fail
alsa_mixer-test_event_missing_0_82: pass
alsa_mixer-test_event_missing_0_83: pass
alsa_mixer-test_event_missing_0_84: pass
alsa_mixer-test_event_missing_0_85: pass
alsa_mixer-test_event_missing_0_86: pass
alsa_mixer-test_event_missing_0_87: pass
alsa_mixer-test_event_missing_0_88: pass
alsa_mixer-test_event_missing_0_89: pass
alsa_mixer-test_event_missing_0_9: pass
alsa_mixer-test_event_missing_0_90: pass
alsa_mixer-test_event_missing_0_91: pass
alsa_mixer-test_event_missing_0_92: pass
alsa_mixer-test_event_missing_0_93: pass
alsa_mixer-test_event_spurious_0_0: pass
alsa_mixer-test_event_spurious_0_1: pass
alsa_mixer-test_event_spurious_0_10: pass
alsa_mixer-test_event_spurious_0_11: pass
alsa_mixer-test_event_spurious_0_12: pass
alsa_mixer-test_event_spurious_0_13: pass
alsa_mixer-test_event_spurious_0_14: pass
alsa_mixer-test_event_spurious_0_15: pass
alsa_mixer-test_event_spurious_0_16: pass
alsa_mixer-test_event_spurious_0_17: pass
alsa_mixer-test_event_spurious_0_18: pass
alsa_mixer-test_event_spurious_0_19: pass
alsa_mixer-test_event_spurious_0_2: pass
alsa_mixer-test_event_spurious_0_20: pass
alsa_mixer-test_event_spurious_0_21: pass
alsa_mixer-test_event_spurious_0_22: pass
alsa_mixer-test_event_spurious_0_23: pass
alsa_mixer-test_event_spurious_0_24: pass
alsa_mixer-test_event_spurious_0_25: pass
alsa_mixer-test_event_spurious_0_26: pass
alsa_mixer-test_event_spurious_0_27: pass
alsa_mixer-test_event_spurious_0_28: pass
alsa_mixer-test_event_spurious_0_29: pass
alsa_mixer-test_event_spurious_0_3: pass
alsa_mixer-test_event_spurious_0_30: pass
alsa_mixer-test_event_spurious_0_31: pass
alsa_mixer-test_event_spurious_0_32: pass
alsa_mixer-test_event_spurious_0_33: pass
alsa_mixer-test_event_spurious_0_34: pass
alsa_mixer-test_event_spurious_0_35: pass
alsa_mixer-test_event_spurious_0_36: pass
alsa_mixer-test_event_spurious_0_37: pass
alsa_mixer-test_event_spurious_0_38: pass
alsa_mixer-test_event_spurious_0_39: pass
alsa_mixer-test_event_spurious_0_4: pass
alsa_mixer-test_event_spurious_0_40: pass
alsa_mixer-test_event_spurious_0_41: pass
alsa_mixer-test_event_spurious_0_42: pass
alsa_mixer-test_event_spurious_0_43: pass
alsa_mixer-test_event_spurious_0_44: pass
alsa_mixer-test_event_spurious_0_45: pass
alsa_mixer-test_event_spurious_0_46: pass
alsa_mixer-test_event_spurious_0_47: pass
alsa_mixer-test_event_spurious_0_48: pass
alsa_mixer-test_event_spurious_0_49: pass
alsa_mixer-test_event_spurious_0_5: pass
alsa_mixer-test_event_spurious_0_50: pass
alsa_mixer-test_event_spurious_0_51: pass
alsa_mixer-test_event_spurious_0_52: pass
alsa_mixer-test_event_spurious_0_53: pass
alsa_mixer-test_event_spurious_0_54: pass
alsa_mixer-test_event_spurious_0_55: pass
alsa_mixer-test_event_spurious_0_56: pass
alsa_mixer-test_event_spurious_0_57: pass
alsa_mixer-test_event_spurious_0_58: pass
alsa_mixer-test_event_spurious_0_59: pass
alsa_mixer-test_event_spurious_0_6: pass
alsa_mixer-test_event_spurious_0_60: pass
alsa_mixer-test_event_spurious_0_61: pass
alsa_mixer-test_event_spurious_0_62: pass
alsa_mixer-test_event_spurious_0_63: pass
alsa_mixer-test_event_spurious_0_64: pass
alsa_mixer-test_event_spurious_0_65: pass
alsa_mixer-test_event_spurious_0_66: pass
alsa_mixer-test_event_spurious_0_67: pass
alsa_mixer-test_event_spurious_0_68: pass
alsa_mixer-test_event_spurious_0_69: pass
alsa_mixer-test_event_spurious_0_7: pass
alsa_mixer-test_event_spurious_0_70: pass
alsa_mixer-test_event_spurious_0_71: pass
alsa_mixer-test_event_spurious_0_72: pass
alsa_mixer-test_event_spurious_0_73: pass
alsa_mixer-test_event_spurious_0_74: pass
alsa_mixer-test_event_spurious_0_75: pass
alsa_mixer-test_event_spurious_0_76: pass
alsa_mixer-test_event_spurious_0_77: pass
alsa_mixer-test_event_spurious_0_78: pass
alsa_mixer-test_event_spurious_0_79: pass
alsa_mixer-test_event_spurious_0_8: pass
alsa_mixer-test_event_spurious_0_80: pass
alsa_mixer-test_event_spurious_0_81: pass
alsa_mixer-test_event_spurious_0_82: pass
alsa_mixer-test_event_spurious_0_83: pass
alsa_mixer-test_event_spurious_0_84: pass
alsa_mixer-test_event_spurious_0_85: pass
alsa_mixer-test_event_spurious_0_86: pass
alsa_mixer-test_event_spurious_0_87: pass
alsa_mixer-test_event_spurious_0_88: fail
alsa_mixer-test_event_spurious_0_89: pass
alsa_mixer-test_event_spurious_0_9: pass
alsa_mixer-test_event_spurious_0_90: pass
alsa_mixer-test_event_spurious_0_91: pass
alsa_mixer-test_event_spurious_0_92: pass
alsa_mixer-test_event_spurious_0_93: pass
alsa_mixer-test_get_value_0_0: pass
alsa_mixer-test_get_value_0_1: pass
alsa_mixer-test_get_value_0_10: pass
alsa_mixer-test_get_value_0_11: pass
alsa_mixer-test_get_value_0_12: pass
alsa_mixer-test_get_value_0_13: pass
alsa_mixer-test_get_value_0_14: pass
alsa_mixer-test_get_value_0_15: pass
alsa_mixer-test_get_value_0_16: pass
alsa_mixer-test_get_value_0_17: pass
alsa_mixer-test_get_value_0_18: pass
alsa_mixer-test_get_value_0_19: pass
alsa_mixer-test_get_value_0_2: pass
alsa_mixer-test_get_value_0_20: pass
alsa_mixer-test_get_value_0_21: pass
alsa_mixer-test_get_value_0_22: pass
alsa_mixer-test_get_value_0_23: pass
alsa_mixer-test_get_value_0_24: pass
alsa_mixer-test_get_value_0_25: pass
alsa_mixer-test_get_value_0_26: pass
alsa_mixer-test_get_value_0_27: pass
alsa_mixer-test_get_value_0_28: pass
alsa_mixer-test_get_value_0_29: pass
alsa_mixer-test_get_value_0_3: pass
alsa_mixer-test_get_value_0_30: pass
alsa_mixer-test_get_value_0_31: pass
alsa_mixer-test_get_value_0_32: pass
alsa_mixer-test_get_value_0_33: pass
alsa_mixer-test_get_value_0_34: pass
alsa_mixer-test_get_value_0_35: pass
alsa_mixer-test_get_value_0_36: pass
alsa_mixer-test_get_value_0_37: pass
alsa_mixer-test_get_value_0_38: pass
alsa_mixer-test_get_value_0_39: pass
alsa_mixer-test_get_value_0_4: pass
alsa_mixer-test_get_value_0_40: pass
alsa_mixer-test_get_value_0_41: pass
alsa_mixer-test_get_value_0_42: pass
alsa_mixer-test_get_value_0_43: pass
alsa_mixer-test_get_value_0_44: pass
alsa_mixer-test_get_value_0_45: pass
alsa_mixer-test_get_value_0_46: pass
alsa_mixer-test_get_value_0_47: pass
alsa_mixer-test_get_value_0_48: pass
alsa_mixer-test_get_value_0_49: pass
alsa_mixer-test_get_value_0_5: pass
alsa_mixer-test_get_value_0_50: pass
alsa_mixer-test_get_value_0_51: pass
alsa_mixer-test_get_value_0_52: pass
alsa_mixer-test_get_value_0_53: pass
alsa_mixer-test_get_value_0_54: pass
alsa_mixer-test_get_value_0_55: pass
alsa_mixer-test_get_value_0_56: pass
alsa_mixer-test_get_value_0_57: pass
alsa_mixer-test_get_value_0_58: pass
alsa_mixer-test_get_value_0_59: pass
alsa_mixer-test_get_value_0_6: pass
alsa_mixer-test_get_value_0_60: pass
alsa_mixer-test_get_value_0_61: pass
alsa_mixer-test_get_value_0_62: pass
alsa_mixer-test_get_value_0_63: pass
alsa_mixer-test_get_value_0_64: pass
alsa_mixer-test_get_value_0_65: pass
alsa_mixer-test_get_value_0_66: pass
alsa_mixer-test_get_value_0_67: pass
alsa_mixer-test_get_value_0_68: pass
alsa_mixer-test_get_value_0_69: pass
alsa_mixer-test_get_value_0_7: pass
alsa_mixer-test_get_value_0_70: pass
alsa_mixer-test_get_value_0_71: pass
alsa_mixer-test_get_value_0_72: pass
alsa_mixer-test_get_value_0_73: pass
alsa_mixer-test_get_value_0_74: pass
alsa_mixer-test_get_value_0_75: pass
alsa_mixer-test_get_value_0_76: pass
alsa_mixer-test_get_value_0_77: fail
alsa_mixer-test_get_value_0_78: fail
alsa_mixer-test_get_value_0_79: fail
alsa_mixer-test_get_value_0_8: pass
alsa_mixer-test_get_value_0_80: pass
alsa_mixer-test_get_value_0_81: pass
alsa_mixer-test_get_value_0_82: pass
alsa_mixer-test_get_value_0_83: pass
alsa_mixer-test_get_value_0_84: pass
alsa_mixer-test_get_value_0_85: pass
alsa_mixer-test_get_value_0_86: pass
alsa_mixer-test_get_value_0_87: pass
alsa_mixer-test_get_value_0_88: pass
alsa_mixer-test_get_value_0_89: pass
alsa_mixer-test_get_value_0_9: pass
alsa_mixer-test_get_value_0_90: pass
alsa_mixer-test_get_value_0_91: pass
alsa_mixer-test_get_value_0_92: pass
alsa_mixer-test_get_value_0_93: pass
alsa_mixer-test_name_0_0: pass
alsa_mixer-test_name_0_1: pass
alsa_mixer-test_name_0_10: fail
alsa_mixer-test_name_0_11: fail
alsa_mixer-test_name_0_12: fail
alsa_mixer-test_name_0_13: fail
alsa_mixer-test_name_0_14: fail
alsa_mixer-test_name_0_15: fail
alsa_mixer-test_name_0_16: fail
alsa_mixer-test_name_0_17: fail
alsa_mixer-test_name_0_18: fail
alsa_mixer-test_name_0_19: fail
alsa_mixer-test_name_0_2: pass
alsa_mixer-test_name_0_20: fail
alsa_mixer-test_name_0_21: fail
alsa_mixer-test_name_0_22: pass
alsa_mixer-test_name_0_23: pass
alsa_mixer-test_name_0_24: pass
alsa_mixer-test_name_0_25: pass
alsa_mixer-test_name_0_26: pass
alsa_mixer-test_name_0_27: pass
alsa_mixer-test_name_0_28: pass
alsa_mixer-test_name_0_29: pass
alsa_mixer-test_name_0_3: pass
alsa_mixer-test_name_0_30: fail
alsa_mixer-test_name_0_31: fail
alsa_mixer-test_name_0_32: fail
alsa_mixer-test_name_0_33: fail
alsa_mixer-test_name_0_34: fail
alsa_mixer-test_name_0_35: fail
alsa_mixer-test_name_0_36: fail
alsa_mixer-test_name_0_37: fail
alsa_mixer-test_name_0_38: fail
alsa_mixer-test_name_0_39: fail
alsa_mixer-test_name_0_4: pass
alsa_mixer-test_name_0_40: fail
alsa_mixer-test_name_0_41: fail
alsa_mixer-test_name_0_42: fail
alsa_mixer-test_name_0_43: fail
alsa_mixer-test_name_0_44: fail
alsa_mixer-test_name_0_45: fail
alsa_mixer-test_name_0_46: fail
alsa_mixer-test_name_0_47: fail
alsa_mixer-test_name_0_48: fail
alsa_mixer-test_name_0_49: fail
alsa_mixer-test_name_0_5: pass
alsa_mixer-test_name_0_50: fail
alsa_mixer-test_name_0_51: fail
alsa_mixer-test_name_0_52: fail
alsa_mixer-test_name_0_53: fail
alsa_mixer-test_name_0_54: fail
alsa_mixer-test_name_0_55: fail
alsa_mixer-test_name_0_56: fail
alsa_mixer-test_name_0_57: fail
alsa_mixer-test_name_0_58: fail
alsa_mixer-test_name_0_59: fail
alsa_mixer-test_name_0_6: fail
alsa_mixer-test_name_0_60: fail
alsa_mixer-test_name_0_61: fail
alsa_mixer-test_name_0_62: fail
alsa_mixer-test_name_0_63: fail
alsa_mixer-test_name_0_64: fail
alsa_mixer-test_name_0_65: fail
alsa_mixer-test_name_0_66: fail
alsa_mixer-test_name_0_67: fail
alsa_mixer-test_name_0_68: fail
alsa_mixer-test_name_0_69: fail
alsa_mixer-test_name_0_7: fail
alsa_mixer-test_name_0_70: fail
alsa_mixer-test_name_0_71: fail
alsa_mixer-test_name_0_72: fail
alsa_mixer-test_name_0_73: fail
alsa_mixer-test_name_0_74: fail
alsa_mixer-test_name_0_75: fail
alsa_mixer-test_name_0_76: fail
alsa_mixer-test_name_0_77: pass
alsa_mixer-test_name_0_78: pass
alsa_mixer-test_name_0_79: pass
alsa_mixer-test_name_0_8: fail
alsa_mixer-test_name_0_80: pass
alsa_mixer-test_name_0_81: pass
alsa_mixer-test_name_0_82: pass
alsa_mixer-test_name_0_83: pass
alsa_mixer-test_name_0_84: pass
alsa_mixer-test_name_0_85: pass
alsa_mixer-test_name_0_86: pass
alsa_mixer-test_name_0_87: pass
alsa_mixer-test_name_0_88: pass
alsa_mixer-test_name_0_89: pass
alsa_mixer-test_name_0_9: fail
alsa_mixer-test_name_0_90: pass
alsa_mixer-test_name_0_91: pass
alsa_mixer-test_name_0_92: pass
alsa_mixer-test_name_0_93: pass
alsa_mixer-test_write_default_0_0: pass
alsa_mixer-test_write_default_0_1: pass
alsa_mixer-test_write_default_0_10: pass
alsa_mixer-test_write_default_0_11: pass
alsa_mixer-test_write_default_0_12: pass
alsa_mixer-test_write_default_0_13: pass
alsa_mixer-test_write_default_0_14: pass
alsa_mixer-test_write_default_0_15: pass
alsa_mixer-test_write_default_0_16: pass
alsa_mixer-test_write_default_0_17: pass
alsa_mixer-test_write_default_0_18: pass
alsa_mixer-test_write_default_0_19: pass
alsa_mixer-test_write_default_0_2: pass
alsa_mixer-test_write_default_0_20: pass
alsa_mixer-test_write_default_0_21: pass
alsa_mixer-test_write_default_0_22: pass
alsa_mixer-test_write_default_0_23: pass
alsa_mixer-test_write_default_0_24: pass
alsa_mixer-test_write_default_0_25: pass
alsa_mixer-test_write_default_0_26: pass
alsa_mixer-test_write_default_0_27: pass
alsa_mixer-test_write_default_0_28: pass
alsa_mixer-test_write_default_0_29: pass
alsa_mixer-test_write_default_0_3: pass
alsa_mixer-test_write_default_0_30: pass
alsa_mixer-test_write_default_0_31: pass
alsa_mixer-test_write_default_0_32: pass
alsa_mixer-test_write_default_0_33: pass
alsa_mixer-test_write_default_0_34: pass
alsa_mixer-test_write_default_0_35: pass
alsa_mixer-test_write_default_0_36: pass
alsa_mixer-test_write_default_0_37: pass
alsa_mixer-test_write_default_0_38: pass
alsa_mixer-test_write_default_0_39: pass
alsa_mixer-test_write_default_0_4: pass
alsa_mixer-test_write_default_0_40: pass
alsa_mixer-test_write_default_0_41: pass
alsa_mixer-test_write_default_0_42: pass
alsa_mixer-test_write_default_0_43: pass
alsa_mixer-test_write_default_0_44: pass
alsa_mixer-test_write_default_0_45: pass
alsa_mixer-test_write_default_0_46: pass
alsa_mixer-test_write_default_0_47: pass
alsa_mixer-test_write_default_0_48: pass
alsa_mixer-test_write_default_0_49: pass
alsa_mixer-test_write_default_0_5: pass
alsa_mixer-test_write_default_0_50: pass
alsa_mixer-test_write_default_0_51: pass
alsa_mixer-test_write_default_0_52: pass
alsa_mixer-test_write_default_0_53: pass
alsa_mixer-test_write_default_0_54: pass
alsa_mixer-test_write_default_0_55: pass
alsa_mixer-test_write_default_0_56: pass
alsa_mixer-test_write_default_0_57: pass
alsa_mixer-test_write_default_0_58: pass
alsa_mixer-test_write_default_0_59: pass
alsa_mixer-test_write_default_0_6: pass
alsa_mixer-test_write_default_0_60: pass
alsa_mixer-test_write_default_0_61: pass
alsa_mixer-test_write_default_0_62: pass
alsa_mixer-test_write_default_0_63: pass
alsa_mixer-test_write_default_0_64: pass
alsa_mixer-test_write_default_0_65: pass
alsa_mixer-test_write_default_0_66: pass
alsa_mixer-test_write_default_0_67: pass
alsa_mixer-test_write_default_0_68: pass
alsa_mixer-test_write_default_0_69: pass
alsa_mixer-test_write_default_0_7: pass
alsa_mixer-test_write_default_0_70: pass
alsa_mixer-test_write_default_0_71: pass
alsa_mixer-test_write_default_0_72: pass
alsa_mixer-test_write_default_0_73: pass
alsa_mixer-test_write_default_0_74: pass
alsa_mixer-test_write_default_0_75: pass
alsa_mixer-test_write_default_0_76: pass
alsa_mixer-test_write_default_0_77: fail
alsa_mixer-test_write_default_0_78: fail
alsa_mixer-test_write_default_0_79: fail
alsa_mixer-test_write_default_0_8: pass
alsa_mixer-test_write_default_0_80: pass
alsa_mixer-test_write_default_0_81: pass
alsa_mixer-test_write_default_0_82: skip
alsa_mixer-test_write_default_0_83: pass
alsa_mixer-test_write_default_0_84: pass
alsa_mixer-test_write_default_0_85: pass
alsa_mixer-test_write_default_0_86: pass
alsa_mixer-test_write_default_0_87: pass
alsa_mixer-test_write_default_0_88: pass
alsa_mixer-test_write_default_0_89: pass
alsa_mixer-test_write_default_0_9: pass
alsa_mixer-test_write_default_0_90: pass
alsa_mixer-test_write_default_0_91: pass
alsa_mixer-test_write_default_0_92: pass
alsa_mixer-test_write_default_0_93: pass
alsa_mixer-test_write_invalid_0_0: pass
alsa_mixer-test_write_invalid_0_1: pass
alsa_mixer-test_write_invalid_0_10: pass
alsa_mixer-test_write_invalid_0_11: pass
alsa_mixer-test_write_invalid_0_12: pass
alsa_mixer-test_write_invalid_0_13: pass
alsa_mixer-test_write_invalid_0_14: pass
alsa_mixer-test_write_invalid_0_15: pass
alsa_mixer-test_write_invalid_0_16: pass
alsa_mixer-test_write_invalid_0_17: pass
alsa_mixer-test_write_invalid_0_18: pass
alsa_mixer-test_write_invalid_0_19: pass
alsa_mixer-test_write_invalid_0_2: pass
alsa_mixer-test_write_invalid_0_20: pass
alsa_mixer-test_write_invalid_0_21: pass
alsa_mixer-test_write_invalid_0_22: pass
alsa_mixer-test_write_invalid_0_23: pass
alsa_mixer-test_write_invalid_0_24: pass
alsa_mixer-test_write_invalid_0_25: pass
alsa_mixer-test_write_invalid_0_26: pass
alsa_mixer-test_write_invalid_0_27: pass
alsa_mixer-test_write_invalid_0_28: pass
alsa_mixer-test_write_invalid_0_29: pass
alsa_mixer-test_write_invalid_0_3: pass
alsa_mixer-test_write_invalid_0_30: pass
alsa_mixer-test_write_invalid_0_31: pass
alsa_mixer-test_write_invalid_0_32: pass
alsa_mixer-test_write_invalid_0_33: pass
alsa_mixer-test_write_invalid_0_34: pass
alsa_mixer-test_write_invalid_0_35: pass
alsa_mixer-test_write_invalid_0_36: pass
alsa_mixer-test_write_invalid_0_37: pass
alsa_mixer-test_write_invalid_0_38: pass
alsa_mixer-test_write_invalid_0_39: pass
alsa_mixer-test_write_invalid_0_4: pass
alsa_mixer-test_write_invalid_0_40: pass
alsa_mixer-test_write_invalid_0_41: pass
alsa_mixer-test_write_invalid_0_42: pass
alsa_mixer-test_write_invalid_0_43: pass
alsa_mixer-test_write_invalid_0_44: pass
alsa_mixer-test_write_invalid_0_45: pass
alsa_mixer-test_write_invalid_0_46: pass
alsa_mixer-test_write_invalid_0_47: pass
alsa_mixer-test_write_invalid_0_48: pass
alsa_mixer-test_write_invalid_0_49: pass
alsa_mixer-test_write_invalid_0_5: pass
alsa_mixer-test_write_invalid_0_50: pass
alsa_mixer-test_write_invalid_0_51: pass
alsa_mixer-test_write_invalid_0_52: pass
alsa_mixer-test_write_invalid_0_53: pass
alsa_mixer-test_write_invalid_0_54: pass
alsa_mixer-test_write_invalid_0_55: pass
alsa_mixer-test_write_invalid_0_56: pass
alsa_mixer-test_write_invalid_0_57: pass
alsa_mixer-test_write_invalid_0_58: pass
alsa_mixer-test_write_invalid_0_59: pass
alsa_mixer-test_write_invalid_0_6: pass
alsa_mixer-test_write_invalid_0_60: pass
alsa_mixer-test_write_invalid_0_61: pass
alsa_mixer-test_write_invalid_0_62: pass
alsa_mixer-test_write_invalid_0_63: pass
alsa_mixer-test_write_invalid_0_64: pass
alsa_mixer-test_write_invalid_0_65: pass
alsa_mixer-test_write_invalid_0_66: pass
alsa_mixer-test_write_invalid_0_67: pass
alsa_mixer-test_write_invalid_0_68: pass
alsa_mixer-test_write_invalid_0_69: pass
alsa_mixer-test_write_invalid_0_7: pass
alsa_mixer-test_write_invalid_0_70: pass
alsa_mixer-test_write_invalid_0_71: pass
alsa_mixer-test_write_invalid_0_72: pass
alsa_mixer-test_write_invalid_0_73: pass
alsa_mixer-test_write_invalid_0_74: pass
alsa_mixer-test_write_invalid_0_75: pass
alsa_mixer-test_write_invalid_0_76: pass
alsa_mixer-test_write_invalid_0_77: fail
alsa_mixer-test_write_invalid_0_78: fail
alsa_mixer-test_write_invalid_0_79: fail
alsa_mixer-test_write_invalid_0_8: pass
alsa_mixer-test_write_invalid_0_80: pass
alsa_mixer-test_write_invalid_0_81: fail
alsa_mixer-test_write_invalid_0_82: skip
alsa_mixer-test_write_invalid_0_83: pass
alsa_mixer-test_write_invalid_0_84: pass
alsa_mixer-test_write_invalid_0_85: pass
alsa_mixer-test_write_invalid_0_86: pass
alsa_mixer-test_write_invalid_0_87: pass
alsa_mixer-test_write_invalid_0_88: pass
alsa_mixer-test_write_invalid_0_89: pass
alsa_mixer-test_write_invalid_0_9: pass
alsa_mixer-test_write_invalid_0_90: pass
alsa_mixer-test_write_invalid_0_91: pass
alsa_mixer-test_write_invalid_0_92: pass
alsa_mixer-test_write_invalid_0_93: pass
alsa_mixer-test_write_valid_0_0: pass
alsa_mixer-test_write_valid_0_1: pass
alsa_mixer-test_write_valid_0_10: pass
alsa_mixer-test_write_valid_0_11: pass
alsa_mixer-test_write_valid_0_12: pass
alsa_mixer-test_write_valid_0_13: pass
alsa_mixer-test_write_valid_0_14: pass
alsa_mixer-test_write_valid_0_15: pass
alsa_mixer-test_write_valid_0_16: pass
alsa_mixer-test_write_valid_0_17: pass
alsa_mixer-test_write_valid_0_18: pass
alsa_mixer-test_write_valid_0_19: pass
alsa_mixer-test_write_valid_0_2: pass
alsa_mixer-test_write_valid_0_20: pass
alsa_mixer-test_write_valid_0_21: pass
alsa_mixer-test_write_valid_0_22: pass
alsa_mixer-test_write_valid_0_23: pass
alsa_mixer-test_write_valid_0_24: pass
alsa_mixer-test_write_valid_0_25: pass
alsa_mixer-test_write_valid_0_26: pass
alsa_mixer-test_write_valid_0_27: pass
alsa_mixer-test_write_valid_0_28: pass
alsa_mixer-test_write_valid_0_29: pass
alsa_mixer-test_write_valid_0_3: pass
alsa_mixer-test_write_valid_0_30: pass
alsa_mixer-test_write_valid_0_31: pass
alsa_mixer-test_write_valid_0_32: pass
alsa_mixer-test_write_valid_0_33: pass
alsa_mixer-test_write_valid_0_34: pass
alsa_mixer-test_write_valid_0_35: pass
alsa_mixer-test_write_valid_0_36: pass
alsa_mixer-test_write_valid_0_37: pass
alsa_mixer-test_write_valid_0_38: pass
alsa_mixer-test_write_valid_0_39: pass
alsa_mixer-test_write_valid_0_4: pass
alsa_mixer-test_write_valid_0_40: pass
alsa_mixer-test_write_valid_0_41: pass
alsa_mixer-test_write_valid_0_42: pass
alsa_mixer-test_write_valid_0_43: pass
alsa_mixer-test_write_valid_0_44: pass
alsa_mixer-test_write_valid_0_45: pass
alsa_mixer-test_write_valid_0_46: pass
alsa_mixer-test_write_valid_0_47: pass
alsa_mixer-test_write_valid_0_48: pass
alsa_mixer-test_write_valid_0_49: pass
alsa_mixer-test_write_valid_0_5: pass
alsa_mixer-test_write_valid_0_50: pass
alsa_mixer-test_write_valid_0_51: pass
alsa_mixer-test_write_valid_0_52: pass
alsa_mixer-test_write_valid_0_53: pass
alsa_mixer-test_write_valid_0_54: pass
alsa_mixer-test_write_valid_0_55: pass
alsa_mixer-test_write_valid_0_56: pass
alsa_mixer-test_write_valid_0_57: pass
alsa_mixer-test_write_valid_0_58: pass
alsa_mixer-test_write_valid_0_59: pass
alsa_mixer-test_write_valid_0_6: pass
alsa_mixer-test_write_valid_0_60: pass
alsa_mixer-test_write_valid_0_61: pass
alsa_mixer-test_write_valid_0_62: pass
alsa_mixer-test_write_valid_0_63: pass
alsa_mixer-test_write_valid_0_64: pass
alsa_mixer-test_write_valid_0_65: pass
alsa_mixer-test_write_valid_0_66: pass
alsa_mixer-test_write_valid_0_67: pass
alsa_mixer-test_write_valid_0_68: pass
alsa_mixer-test_write_valid_0_69: pass
alsa_mixer-test_write_valid_0_7: pass
alsa_mixer-test_write_valid_0_70: pass
alsa_mixer-test_write_valid_0_71: pass
alsa_mixer-test_write_valid_0_72: pass
alsa_mixer-test_write_valid_0_73: pass
alsa_mixer-test_write_valid_0_74: pass
alsa_mixer-test_write_valid_0_75: pass
alsa_mixer-test_write_valid_0_76: pass
alsa_mixer-test_write_valid_0_77: fail
alsa_mixer-test_write_valid_0_78: fail
alsa_mixer-test_write_valid_0_79: fail
alsa_mixer-test_write_valid_0_8: pass
alsa_mixer-test_write_valid_0_80: pass
alsa_mixer-test_write_valid_0_81: pass
alsa_mixer-test_write_valid_0_82: skip
alsa_mixer-test_write_valid_0_83: pass
alsa_mixer-test_write_valid_0_84: pass
alsa_mixer-test_write_valid_0_85: fail
alsa_mixer-test_write_valid_0_86: fail
alsa_mixer-test_write_valid_0_87: pass
alsa_mixer-test_write_valid_0_88: fail
alsa_mixer-test_write_valid_0_89: pass
alsa_mixer-test_write_valid_0_9: pass
alsa_mixer-test_write_valid_0_90: pass
alsa_mixer-test_write_valid_0_91: pass
alsa_mixer-test_write_valid_0_92: pass
alsa_mixer-test_write_valid_0_93: pass
shardfile-alsa: pass
10161 23:47:06.241481 end: 3.1 lava-test-shell (duration 00:00:39) [common]
10162 23:47:06.241585 end: 3 lava-test-retry (duration 00:00:39) [common]
10163 23:47:06.241688 start: 4 finalize (timeout 00:07:26) [common]
10164 23:47:06.241786 start: 4.1 power-off (timeout 00:00:30) [common]
10165 23:47:06.241980 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8183-kukui-jacuzzi-juniper-sku16-cbg-0', '--port=1', '--command=off']
10166 23:47:07.606711 >> Command sent successfully.
10167 23:47:07.609222 Returned 0 in 1 seconds
10168 23:47:07.709633 end: 4.1 power-off (duration 00:00:01) [common]
10170 23:47:07.710028 start: 4.2 read-feedback (timeout 00:07:24) [common]
10171 23:47:07.710330 Listened to connection for namespace 'common' for up to 1s
10172 23:47:08.711228 Finalising connection for namespace 'common'
10173 23:47:08.711427 Disconnecting from shell: Finalise
10174 23:47:08.711569 / #
10175 23:47:08.811895 end: 4.2 read-feedback (duration 00:00:01) [common]
10176 23:47:08.812081 end: 4 finalize (duration 00:00:03) [common]
10177 23:47:08.812221 Cleaning after the job
10178 23:47:08.812342 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/ramdisk
10179 23:47:08.814837 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/kernel
10180 23:47:08.826411 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/dtb
10181 23:47:08.826610 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/nfsrootfs
10182 23:47:08.894792 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172940/tftp-deploy-j2ocngpm/modules
10183 23:47:08.901090 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14172940
10184 23:47:09.564677 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14172940
10185 23:47:09.564868 Job finished correctly