Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 26
1 23:44:15.396938 lava-dispatcher, installed at version: 2024.03
2 23:44:15.397135 start: 0 validate
3 23:44:15.397266 Start time: 2024-06-04 23:44:15.397258+00:00 (UTC)
4 23:44:15.397424 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:44:15.397548 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:44:15.657755 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:44:15.657918 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:44:15.916499 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:44:15.916659 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:44:16.175137 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:44:16.175316 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:44:16.433614 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:44:16.433785 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:44:16.693385 validate duration: 1.30
16 23:44:16.693694 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:44:16.693831 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:44:16.693930 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:44:16.694060 Not decompressing ramdisk as can be used compressed.
20 23:44:16.694174 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:44:16.694277 saving as /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/ramdisk/initrd.cpio.gz
22 23:44:16.694349 total size: 5628169 (5 MB)
23 23:44:16.695537 progress 0 % (0 MB)
24 23:44:16.697238 progress 5 % (0 MB)
25 23:44:16.698860 progress 10 % (0 MB)
26 23:44:16.700353 progress 15 % (0 MB)
27 23:44:16.701901 progress 20 % (1 MB)
28 23:44:16.703332 progress 25 % (1 MB)
29 23:44:16.704879 progress 30 % (1 MB)
30 23:44:16.706446 progress 35 % (1 MB)
31 23:44:16.707826 progress 40 % (2 MB)
32 23:44:16.709479 progress 45 % (2 MB)
33 23:44:16.710850 progress 50 % (2 MB)
34 23:44:16.712377 progress 55 % (2 MB)
35 23:44:16.714004 progress 60 % (3 MB)
36 23:44:16.715363 progress 65 % (3 MB)
37 23:44:16.716902 progress 70 % (3 MB)
38 23:44:16.718317 progress 75 % (4 MB)
39 23:44:16.719888 progress 80 % (4 MB)
40 23:44:16.721425 progress 85 % (4 MB)
41 23:44:16.723117 progress 90 % (4 MB)
42 23:44:16.724653 progress 95 % (5 MB)
43 23:44:16.726129 progress 100 % (5 MB)
44 23:44:16.726352 5 MB downloaded in 0.03 s (167.71 MB/s)
45 23:44:16.726522 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:44:16.726763 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:44:16.726850 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:44:16.726932 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:44:16.727066 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:44:16.727134 saving as /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/kernel/Image
52 23:44:16.727193 total size: 54682112 (52 MB)
53 23:44:16.727260 No compression specified
54 23:44:16.728359 progress 0 % (0 MB)
55 23:44:16.742406 progress 5 % (2 MB)
56 23:44:16.756299 progress 10 % (5 MB)
57 23:44:16.770366 progress 15 % (7 MB)
58 23:44:16.784220 progress 20 % (10 MB)
59 23:44:16.798449 progress 25 % (13 MB)
60 23:44:16.812767 progress 30 % (15 MB)
61 23:44:16.827054 progress 35 % (18 MB)
62 23:44:16.841083 progress 40 % (20 MB)
63 23:44:16.854993 progress 45 % (23 MB)
64 23:44:16.869107 progress 50 % (26 MB)
65 23:44:16.882924 progress 55 % (28 MB)
66 23:44:16.897089 progress 60 % (31 MB)
67 23:44:16.911091 progress 65 % (33 MB)
68 23:44:16.925240 progress 70 % (36 MB)
69 23:44:16.939263 progress 75 % (39 MB)
70 23:44:16.953534 progress 80 % (41 MB)
71 23:44:16.967389 progress 85 % (44 MB)
72 23:44:16.981211 progress 90 % (46 MB)
73 23:44:16.995098 progress 95 % (49 MB)
74 23:44:17.008899 progress 100 % (52 MB)
75 23:44:17.009159 52 MB downloaded in 0.28 s (184.95 MB/s)
76 23:44:17.009395 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:44:17.009630 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:44:17.009714 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:44:17.009795 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:44:17.009937 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:44:17.010005 saving as /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/dtb/mt8192-asurada-spherion-r0.dtb
83 23:44:17.010067 total size: 47258 (0 MB)
84 23:44:17.010129 No compression specified
85 23:44:17.011240 progress 69 % (0 MB)
86 23:44:17.011531 progress 100 % (0 MB)
87 23:44:17.011688 0 MB downloaded in 0.00 s (27.84 MB/s)
88 23:44:17.011806 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:44:17.012024 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:44:17.012109 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:44:17.012188 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:44:17.012295 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:44:17.012364 saving as /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/nfsrootfs/full.rootfs.tar
95 23:44:17.012436 total size: 120894716 (115 MB)
96 23:44:17.012502 Using unxz to decompress xz
97 23:44:17.016462 progress 0 % (0 MB)
98 23:44:17.360908 progress 5 % (5 MB)
99 23:44:17.715484 progress 10 % (11 MB)
100 23:44:18.067567 progress 15 % (17 MB)
101 23:44:18.393849 progress 20 % (23 MB)
102 23:44:18.685220 progress 25 % (28 MB)
103 23:44:19.043777 progress 30 % (34 MB)
104 23:44:19.384512 progress 35 % (40 MB)
105 23:44:19.549244 progress 40 % (46 MB)
106 23:44:19.726769 progress 45 % (51 MB)
107 23:44:20.035589 progress 50 % (57 MB)
108 23:44:20.408833 progress 55 % (63 MB)
109 23:44:20.752626 progress 60 % (69 MB)
110 23:44:21.105140 progress 65 % (74 MB)
111 23:44:21.460314 progress 70 % (80 MB)
112 23:44:21.833924 progress 75 % (86 MB)
113 23:44:22.173838 progress 80 % (92 MB)
114 23:44:22.507844 progress 85 % (98 MB)
115 23:44:22.860234 progress 90 % (103 MB)
116 23:44:23.183800 progress 95 % (109 MB)
117 23:44:23.534938 progress 100 % (115 MB)
118 23:44:23.540237 115 MB downloaded in 6.53 s (17.66 MB/s)
119 23:44:23.540493 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:44:23.540756 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:44:23.540846 start: 1.5 download-retry (timeout 00:09:53) [common]
123 23:44:23.540932 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 23:44:23.541087 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:44:23.541158 saving as /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/modules/modules.tar
126 23:44:23.541218 total size: 8603924 (8 MB)
127 23:44:23.541281 Using unxz to decompress xz
128 23:44:23.545448 progress 0 % (0 MB)
129 23:44:23.565005 progress 5 % (0 MB)
130 23:44:23.589103 progress 10 % (0 MB)
131 23:44:23.614226 progress 15 % (1 MB)
132 23:44:23.638679 progress 20 % (1 MB)
133 23:44:23.663985 progress 25 % (2 MB)
134 23:44:23.688563 progress 30 % (2 MB)
135 23:44:23.711849 progress 35 % (2 MB)
136 23:44:23.737806 progress 40 % (3 MB)
137 23:44:23.762471 progress 45 % (3 MB)
138 23:44:23.786486 progress 50 % (4 MB)
139 23:44:23.811274 progress 55 % (4 MB)
140 23:44:23.835482 progress 60 % (4 MB)
141 23:44:23.859197 progress 65 % (5 MB)
142 23:44:23.885212 progress 70 % (5 MB)
143 23:44:23.909988 progress 75 % (6 MB)
144 23:44:23.934951 progress 80 % (6 MB)
145 23:44:23.958356 progress 85 % (7 MB)
146 23:44:23.982005 progress 90 % (7 MB)
147 23:44:24.011010 progress 95 % (7 MB)
148 23:44:24.038655 progress 100 % (8 MB)
149 23:44:24.044109 8 MB downloaded in 0.50 s (16.32 MB/s)
150 23:44:24.044368 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:44:24.044742 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:44:24.044836 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 23:44:24.044927 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 23:44:27.540805 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14172964/extract-nfsrootfs-yfsyau3h
156 23:44:27.541003 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 23:44:27.541104 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 23:44:27.541274 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328
159 23:44:27.541539 makedir: /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin
160 23:44:27.541640 makedir: /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/tests
161 23:44:27.541738 makedir: /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/results
162 23:44:27.541837 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-add-keys
163 23:44:27.541979 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-add-sources
164 23:44:27.542113 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-background-process-start
165 23:44:27.542253 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-background-process-stop
166 23:44:27.542380 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-common-functions
167 23:44:27.542508 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-echo-ipv4
168 23:44:27.542636 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-install-packages
169 23:44:27.542761 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-installed-packages
170 23:44:27.542884 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-os-build
171 23:44:27.543007 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-probe-channel
172 23:44:27.543131 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-probe-ip
173 23:44:27.543254 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-target-ip
174 23:44:27.543379 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-target-mac
175 23:44:27.543501 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-target-storage
176 23:44:27.543626 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-test-case
177 23:44:27.543752 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-test-event
178 23:44:27.543877 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-test-feedback
179 23:44:27.544000 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-test-raise
180 23:44:27.544122 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-test-reference
181 23:44:27.544245 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-test-runner
182 23:44:27.544366 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-test-set
183 23:44:27.544491 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-test-shell
184 23:44:27.544616 Updating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-add-keys (debian)
185 23:44:27.544763 Updating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-add-sources (debian)
186 23:44:27.544901 Updating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-install-packages (debian)
187 23:44:27.545089 Updating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-installed-packages (debian)
188 23:44:27.545260 Updating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/bin/lava-os-build (debian)
189 23:44:27.545428 Creating /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/environment
190 23:44:27.545523 LAVA metadata
191 23:44:27.545597 - LAVA_JOB_ID=14172964
192 23:44:27.545659 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:44:27.545758 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 23:44:27.545822 skipped lava-vland-overlay
195 23:44:27.545894 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:44:27.545971 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 23:44:27.546029 skipped lava-multinode-overlay
198 23:44:27.546099 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:44:27.546175 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 23:44:27.546247 Loading test definitions
201 23:44:27.546333 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 23:44:27.546404 Using /lava-14172964 at stage 0
203 23:44:27.546688 uuid=14172964_1.6.2.3.1 testdef=None
204 23:44:27.546773 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:44:27.546855 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 23:44:27.547305 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:44:27.547518 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 23:44:27.548064 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:44:27.548288 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 23:44:27.548815 runner path: /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/0/tests/0_timesync-off test_uuid 14172964_1.6.2.3.1
213 23:44:27.549006 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:44:27.549226 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 23:44:27.549448 Using /lava-14172964 at stage 0
217 23:44:27.549550 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:44:27.549636 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/0/tests/1_kselftest-alsa'
219 23:44:29.552440 Running '/usr/bin/git checkout kernelci.org
220 23:44:29.699409 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 23:44:29.700178 uuid=14172964_1.6.2.3.5 testdef=None
222 23:44:29.700335 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 23:44:29.700581 start: 1.6.2.3.6 test-overlay (timeout 00:09:47) [common]
225 23:44:29.701346 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:44:29.701599 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:47) [common]
228 23:44:29.702574 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:44:29.702813 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:47) [common]
231 23:44:29.703735 runner path: /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/0/tests/1_kselftest-alsa test_uuid 14172964_1.6.2.3.5
232 23:44:29.703827 BOARD='mt8192-asurada-spherion-r0'
233 23:44:29.703891 BRANCH='cip'
234 23:44:29.703949 SKIPFILE='/dev/null'
235 23:44:29.704009 SKIP_INSTALL='True'
236 23:44:29.704064 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:44:29.704123 TST_CASENAME=''
238 23:44:29.704177 TST_CMDFILES='alsa'
239 23:44:29.704318 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:44:29.704519 Creating lava-test-runner.conf files
242 23:44:29.704582 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14172964/lava-overlay-i3uab328/lava-14172964/0 for stage 0
243 23:44:29.704672 - 0_timesync-off
244 23:44:29.704739 - 1_kselftest-alsa
245 23:44:29.704835 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 23:44:29.704922 start: 1.6.2.4 compress-overlay (timeout 00:09:47) [common]
247 23:44:37.275473 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:44:37.275618 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 23:44:37.275709 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:44:37.275807 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 23:44:37.275894 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 23:44:37.442034 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:44:37.442400 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 23:44:37.442514 extracting modules file /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172964/extract-nfsrootfs-yfsyau3h
255 23:44:37.662110 extracting modules file /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172964/extract-overlay-ramdisk-b3v6ofwu/ramdisk
256 23:44:37.890349 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:44:37.890531 start: 1.6.5 apply-overlay-tftp (timeout 00:09:39) [common]
258 23:44:37.890627 [common] Applying overlay to NFS
259 23:44:37.890704 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172964/compress-overlay-c_bxacy8/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14172964/extract-nfsrootfs-yfsyau3h
260 23:44:38.831405 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:44:38.831576 start: 1.6.6 configure-preseed-file (timeout 00:09:38) [common]
262 23:44:38.831666 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:44:38.831754 start: 1.6.7 compress-ramdisk (timeout 00:09:38) [common]
264 23:44:38.831832 Building ramdisk /var/lib/lava/dispatcher/tmp/14172964/extract-overlay-ramdisk-b3v6ofwu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14172964/extract-overlay-ramdisk-b3v6ofwu/ramdisk
265 23:44:39.196463 >> 130337 blocks
266 23:44:41.264363 rename /var/lib/lava/dispatcher/tmp/14172964/extract-overlay-ramdisk-b3v6ofwu/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/ramdisk/ramdisk.cpio.gz
267 23:44:41.264797 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:44:41.264921 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 23:44:41.265023 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 23:44:41.265133 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/kernel/Image']
271 23:44:54.314918 Returned 0 in 13 seconds
272 23:44:54.415548 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/kernel/image.itb
273 23:44:54.771815 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:44:54.772186 output: Created: Wed Jun 5 00:44:54 2024
275 23:44:54.772266 output: Image 0 (kernel-1)
276 23:44:54.772333 output: Description:
277 23:44:54.772397 output: Created: Wed Jun 5 00:44:54 2024
278 23:44:54.772460 output: Type: Kernel Image
279 23:44:54.772520 output: Compression: lzma compressed
280 23:44:54.772578 output: Data Size: 13061430 Bytes = 12755.30 KiB = 12.46 MiB
281 23:44:54.772636 output: Architecture: AArch64
282 23:44:54.772692 output: OS: Linux
283 23:44:54.772745 output: Load Address: 0x00000000
284 23:44:54.772800 output: Entry Point: 0x00000000
285 23:44:54.772854 output: Hash algo: crc32
286 23:44:54.772907 output: Hash value: ecfb5096
287 23:44:54.772960 output: Image 1 (fdt-1)
288 23:44:54.773014 output: Description: mt8192-asurada-spherion-r0
289 23:44:54.773073 output: Created: Wed Jun 5 00:44:54 2024
290 23:44:54.773131 output: Type: Flat Device Tree
291 23:44:54.773185 output: Compression: uncompressed
292 23:44:54.773237 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 23:44:54.773299 output: Architecture: AArch64
294 23:44:54.773353 output: Hash algo: crc32
295 23:44:54.773406 output: Hash value: 0f8e4d2e
296 23:44:54.773458 output: Image 2 (ramdisk-1)
297 23:44:54.773510 output: Description: unavailable
298 23:44:54.773563 output: Created: Wed Jun 5 00:44:54 2024
299 23:44:54.773615 output: Type: RAMDisk Image
300 23:44:54.773668 output: Compression: Unknown Compression
301 23:44:54.773720 output: Data Size: 18731806 Bytes = 18292.78 KiB = 17.86 MiB
302 23:44:54.773772 output: Architecture: AArch64
303 23:44:54.773824 output: OS: Linux
304 23:44:54.773876 output: Load Address: unavailable
305 23:44:54.773928 output: Entry Point: unavailable
306 23:44:54.773979 output: Hash algo: crc32
307 23:44:54.774031 output: Hash value: bc5c559b
308 23:44:54.774083 output: Default Configuration: 'conf-1'
309 23:44:54.774135 output: Configuration 0 (conf-1)
310 23:44:54.774187 output: Description: mt8192-asurada-spherion-r0
311 23:44:54.774239 output: Kernel: kernel-1
312 23:44:54.774291 output: Init Ramdisk: ramdisk-1
313 23:44:54.774343 output: FDT: fdt-1
314 23:44:54.774395 output: Loadables: kernel-1
315 23:44:54.774447 output:
316 23:44:54.774645 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 23:44:54.774742 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 23:44:54.774847 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 23:44:54.774940 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 23:44:54.775052 No LXC device requested
321 23:44:54.775168 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:44:54.775296 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 23:44:54.775404 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:44:54.775479 Checking files for TFTP limit of 4294967296 bytes.
325 23:44:54.775984 end: 1 tftp-deploy (duration 00:00:38) [common]
326 23:44:54.776092 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:44:54.776187 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:44:54.776309 substitutions:
329 23:44:54.776375 - {DTB}: 14172964/tftp-deploy-m7ldps3i/dtb/mt8192-asurada-spherion-r0.dtb
330 23:44:54.776438 - {INITRD}: 14172964/tftp-deploy-m7ldps3i/ramdisk/ramdisk.cpio.gz
331 23:44:54.776496 - {KERNEL}: 14172964/tftp-deploy-m7ldps3i/kernel/Image
332 23:44:54.776553 - {LAVA_MAC}: None
333 23:44:54.776608 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14172964/extract-nfsrootfs-yfsyau3h
334 23:44:54.776663 - {NFS_SERVER_IP}: 192.168.201.1
335 23:44:54.776716 - {PRESEED_CONFIG}: None
336 23:44:54.776770 - {PRESEED_LOCAL}: None
337 23:44:54.776822 - {RAMDISK}: 14172964/tftp-deploy-m7ldps3i/ramdisk/ramdisk.cpio.gz
338 23:44:54.776876 - {ROOT_PART}: None
339 23:44:54.776929 - {ROOT}: None
340 23:44:54.776982 - {SERVER_IP}: 192.168.201.1
341 23:44:54.777034 - {TEE}: None
342 23:44:54.777112 Parsed boot commands:
343 23:44:54.777180 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:44:54.777396 Parsed boot commands: tftpboot 192.168.201.1 14172964/tftp-deploy-m7ldps3i/kernel/image.itb 14172964/tftp-deploy-m7ldps3i/kernel/cmdline
345 23:44:54.777483 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:44:54.777566 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:44:54.777656 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:44:54.777740 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:44:54.777810 Not connected, no need to disconnect.
350 23:44:54.777914 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:44:54.777993 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:44:54.778072 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 23:44:54.782005 Setting prompt string to ['lava-test: # ']
354 23:44:54.782488 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:44:54.782597 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:44:54.782695 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:44:54.782781 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:44:54.783044 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
359 23:44:59.933528 >> Command sent successfully.
360 23:44:59.945374 Returned 0 in 5 seconds
361 23:45:00.046668 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:45:00.048242 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:45:00.048757 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:45:00.049249 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:45:00.049694 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:45:00.050059 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:45:00.052097 [Enter `^Ec?' for help]
369 23:45:00.215915
370 23:45:00.216516
371 23:45:00.216942 F0: 102B 0000
372 23:45:00.217559
373 23:45:00.217987 F3: 1001 0000 [0200]
374 23:45:00.218359
375 23:45:00.219358 F3: 1001 0000
376 23:45:00.219816
377 23:45:00.220192 F7: 102D 0000
378 23:45:00.220533
379 23:45:00.220850 F1: 0000 0000
380 23:45:00.221185
381 23:45:00.223166 V0: 0000 0000 [0001]
382 23:45:00.223635
383 23:45:00.224098 00: 0007 8000
384 23:45:00.224472
385 23:45:00.226761 01: 0000 0000
386 23:45:00.227191
387 23:45:00.227538 BP: 0C00 0209 [0000]
388 23:45:00.227867
389 23:45:00.230614 G0: 1182 0000
390 23:45:00.231079
391 23:45:00.231443 EC: 0000 0021 [4000]
392 23:45:00.231785
393 23:45:00.234291 S7: 0000 0000 [0000]
394 23:45:00.234751
395 23:45:00.235110 CC: 0000 0000 [0001]
396 23:45:00.235449
397 23:45:00.237491 T0: 0000 0040 [010F]
398 23:45:00.237975
399 23:45:00.238343 Jump to BL
400 23:45:00.238680
401 23:45:00.262278
402 23:45:00.262823
403 23:45:00.269669 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 23:45:00.273226 ARM64: Exception handlers installed.
405 23:45:00.277044 ARM64: Testing exception
406 23:45:00.280440 ARM64: Done test exception
407 23:45:00.287443 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 23:45:00.297809 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 23:45:00.304907 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 23:45:00.314855 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 23:45:00.321900 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 23:45:00.328499 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 23:45:00.339218 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 23:45:00.345707 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 23:45:00.365204 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 23:45:00.368276 WDT: Last reset was cold boot
417 23:45:00.371889 SPI1(PAD0) initialized at 2873684 Hz
418 23:45:00.375117 SPI5(PAD0) initialized at 992727 Hz
419 23:45:00.378650 VBOOT: Loading verstage.
420 23:45:00.385161 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 23:45:00.388531 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 23:45:00.391889 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 23:45:00.395191 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 23:45:00.402772 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 23:45:00.409456 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 23:45:00.420697 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
427 23:45:00.421266
428 23:45:00.421687
429 23:45:00.430094 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 23:45:00.433682 ARM64: Exception handlers installed.
431 23:45:00.436920 ARM64: Testing exception
432 23:45:00.437536 ARM64: Done test exception
433 23:45:00.443656 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 23:45:00.446881 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 23:45:00.461245 Probing TPM: . done!
436 23:45:00.461847 TPM ready after 0 ms
437 23:45:00.468376 Connected to device vid:did:rid of 1ae0:0028:00
438 23:45:00.475102 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
439 23:45:00.523709 Initialized TPM device CR50 revision 0
440 23:45:00.527882 tlcl_send_startup: Startup return code is 0
441 23:45:00.536798 TPM: setup succeeded
442 23:45:00.547123 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 23:45:00.556405 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 23:45:00.566020 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 23:45:00.575051 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 23:45:00.578634 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 23:45:00.581553 in-header: 03 07 00 00 08 00 00 00
448 23:45:00.585356 in-data: aa e4 47 04 13 02 00 00
449 23:45:00.588729 Chrome EC: UHEPI supported
450 23:45:00.595049 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 23:45:00.598284 in-header: 03 95 00 00 08 00 00 00
452 23:45:00.602241 in-data: 18 20 20 08 00 00 00 00
453 23:45:00.602673 Phase 1
454 23:45:00.605992 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 23:45:00.613278 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 23:45:00.620673 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 23:45:00.621276 Recovery requested (1009000e)
458 23:45:00.629278 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 23:45:00.635267 tlcl_extend: response is 0
460 23:45:00.644424 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 23:45:00.649959 tlcl_extend: response is 0
462 23:45:00.657084 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 23:45:00.677470 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 23:45:00.685764 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 23:45:00.685849
466 23:45:00.685914
467 23:45:00.692798 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 23:45:00.696405 ARM64: Exception handlers installed.
469 23:45:00.700180 ARM64: Testing exception
470 23:45:00.700268 ARM64: Done test exception
471 23:45:00.722711 pmic_efuse_setting: Set efuses in 11 msecs
472 23:45:00.725766 pmwrap_interface_init: Select PMIF_VLD_RDY
473 23:45:00.732633 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 23:45:00.735736 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 23:45:00.742603 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 23:45:00.746105 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 23:45:00.752714 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 23:45:00.755925 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 23:45:00.759434 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 23:45:00.766106 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 23:45:00.769284 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 23:45:00.775993 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 23:45:00.779373 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 23:45:00.782880 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 23:45:00.789723 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 23:45:00.795659 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 23:45:00.799012 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 23:45:00.806698 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 23:45:00.813383 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 23:45:00.817606 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 23:45:00.825400 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 23:45:00.829079 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 23:45:00.835991 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 23:45:00.839784 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 23:45:00.847471 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 23:45:00.850732 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 23:45:00.858365 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 23:45:00.861488 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 23:45:00.869210 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 23:45:00.872582 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 23:45:00.876220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 23:45:00.883648 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 23:45:00.887276 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 23:45:00.891149 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 23:45:00.898254 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 23:45:00.901899 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 23:45:00.905733 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 23:45:00.912459 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 23:45:00.916167 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 23:45:00.923764 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 23:45:00.927599 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 23:45:00.931175 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 23:45:00.934231 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 23:45:00.937916 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 23:45:00.945431 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 23:45:00.948996 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 23:45:00.952743 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 23:45:00.956280 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 23:45:00.959763 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 23:45:00.966843 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 23:45:00.970762 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 23:45:00.974659 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 23:45:00.978700 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 23:45:00.985328 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 23:45:00.992831 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 23:45:00.999794 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 23:45:01.006837 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 23:45:01.014266 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 23:45:01.021635 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 23:45:01.025132 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 23:45:01.028517 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:45:01.036396 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x26
533 23:45:01.043270 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 23:45:01.047175 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 23:45:01.049878 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 23:45:01.060631 [RTC]rtc_get_frequency_meter,154: input=15, output=763
537 23:45:01.070199 [RTC]rtc_get_frequency_meter,154: input=23, output=949
538 23:45:01.079688 [RTC]rtc_get_frequency_meter,154: input=19, output=857
539 23:45:01.089452 [RTC]rtc_get_frequency_meter,154: input=17, output=810
540 23:45:01.098518 [RTC]rtc_get_frequency_meter,154: input=16, output=788
541 23:45:01.108141 [RTC]rtc_get_frequency_meter,154: input=16, output=788
542 23:45:01.117898 [RTC]rtc_get_frequency_meter,154: input=17, output=810
543 23:45:01.121373 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 23:45:01.128865 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 23:45:01.132025 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 23:45:01.135741 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
547 23:45:01.138848 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 23:45:01.142466 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
549 23:45:01.146523 ADC[4]: Raw value=670800 ID=5
550 23:45:01.149843 ADC[3]: Raw value=212917 ID=1
551 23:45:01.150369 RAM Code: 0x51
552 23:45:01.153973 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 23:45:01.161114 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 23:45:01.168837 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
555 23:45:01.172327 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
556 23:45:01.176199 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 23:45:01.179872 in-header: 03 07 00 00 08 00 00 00
558 23:45:01.183841 in-data: aa e4 47 04 13 02 00 00
559 23:45:01.187653 Chrome EC: UHEPI supported
560 23:45:01.194883 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 23:45:01.198144 in-header: 03 95 00 00 08 00 00 00
562 23:45:01.198630 in-data: 18 20 20 08 00 00 00 00
563 23:45:01.202232 MRC: failed to locate region type 0.
564 23:45:01.209237 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 23:45:01.212841 DRAM-K: Running full calibration
566 23:45:01.220268 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
567 23:45:01.220735 header.status = 0x0
568 23:45:01.224057 header.version = 0x6 (expected: 0x6)
569 23:45:01.227642 header.size = 0xd00 (expected: 0xd00)
570 23:45:01.228208 header.flags = 0x0
571 23:45:01.234488 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 23:45:01.253325 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
573 23:45:01.260393 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 23:45:01.264193 dram_init: ddr_geometry: 0
575 23:45:01.264653 [EMI] MDL number = 0
576 23:45:01.267777 [EMI] Get MDL freq = 0
577 23:45:01.268244 dram_init: ddr_type: 0
578 23:45:01.271685 is_discrete_lpddr4: 1
579 23:45:01.275383 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 23:45:01.275948
581 23:45:01.276373
582 23:45:01.276716 [Bian_co] ETT version 0.0.0.1
583 23:45:01.282577 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
584 23:45:01.283166
585 23:45:01.286404 dramc_set_vcore_voltage set vcore to 650000
586 23:45:01.287006 Read voltage for 800, 4
587 23:45:01.289490 Vio18 = 0
588 23:45:01.289956 Vcore = 650000
589 23:45:01.290376 Vdram = 0
590 23:45:01.293464 Vddq = 0
591 23:45:01.294069 Vmddr = 0
592 23:45:01.294441 dram_init: config_dvfs: 1
593 23:45:01.301439 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 23:45:01.304402 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 23:45:01.307884 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 23:45:01.311678 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 23:45:01.315119 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 23:45:01.318975 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 23:45:01.322793 MEM_TYPE=3, freq_sel=18
600 23:45:01.326269 sv_algorithm_assistance_LP4_1600
601 23:45:01.329798 ============ PULL DRAM RESETB DOWN ============
602 23:45:01.333749 ========== PULL DRAM RESETB DOWN end =========
603 23:45:01.337562 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 23:45:01.340624 ===================================
605 23:45:01.344478 LPDDR4 DRAM CONFIGURATION
606 23:45:01.348348 ===================================
607 23:45:01.348815 EX_ROW_EN[0] = 0x0
608 23:45:01.351731 EX_ROW_EN[1] = 0x0
609 23:45:01.352244 LP4Y_EN = 0x0
610 23:45:01.355368 WORK_FSP = 0x0
611 23:45:01.355868 WL = 0x2
612 23:45:01.359376 RL = 0x2
613 23:45:01.359909 BL = 0x2
614 23:45:01.362728 RPST = 0x0
615 23:45:01.363225 RD_PRE = 0x0
616 23:45:01.366631 WR_PRE = 0x1
617 23:45:01.367092 WR_PST = 0x0
618 23:45:01.369876 DBI_WR = 0x0
619 23:45:01.370387 DBI_RD = 0x0
620 23:45:01.373759 OTF = 0x1
621 23:45:01.378161 ===================================
622 23:45:01.378726 ===================================
623 23:45:01.381278 ANA top config
624 23:45:01.385658 ===================================
625 23:45:01.386217 DLL_ASYNC_EN = 0
626 23:45:01.388960 ALL_SLAVE_EN = 1
627 23:45:01.392198 NEW_RANK_MODE = 1
628 23:45:01.392760 DLL_IDLE_MODE = 1
629 23:45:01.395879 LP45_APHY_COMB_EN = 1
630 23:45:01.399904 TX_ODT_DIS = 1
631 23:45:01.403193 NEW_8X_MODE = 1
632 23:45:01.406371 ===================================
633 23:45:01.409253 ===================================
634 23:45:01.409766 data_rate = 1600
635 23:45:01.413181 CKR = 1
636 23:45:01.416596 DQ_P2S_RATIO = 8
637 23:45:01.419720 ===================================
638 23:45:01.422955 CA_P2S_RATIO = 8
639 23:45:01.426311 DQ_CA_OPEN = 0
640 23:45:01.426785 DQ_SEMI_OPEN = 0
641 23:45:01.430258 CA_SEMI_OPEN = 0
642 23:45:01.433824 CA_FULL_RATE = 0
643 23:45:01.437372 DQ_CKDIV4_EN = 1
644 23:45:01.437894 CA_CKDIV4_EN = 1
645 23:45:01.441228 CA_PREDIV_EN = 0
646 23:45:01.445132 PH8_DLY = 0
647 23:45:01.448358 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 23:45:01.451256 DQ_AAMCK_DIV = 4
649 23:45:01.451727 CA_AAMCK_DIV = 4
650 23:45:01.454539 CA_ADMCK_DIV = 4
651 23:45:01.457912 DQ_TRACK_CA_EN = 0
652 23:45:01.461684 CA_PICK = 800
653 23:45:01.465462 CA_MCKIO = 800
654 23:45:01.465928 MCKIO_SEMI = 0
655 23:45:01.469010 PLL_FREQ = 3068
656 23:45:01.472255 DQ_UI_PI_RATIO = 32
657 23:45:01.475597 CA_UI_PI_RATIO = 0
658 23:45:01.478977 ===================================
659 23:45:01.482454 ===================================
660 23:45:01.485789 memory_type:LPDDR4
661 23:45:01.486261 GP_NUM : 10
662 23:45:01.489521 SRAM_EN : 1
663 23:45:01.489990 MD32_EN : 0
664 23:45:01.493177 ===================================
665 23:45:01.497216 [ANA_INIT] >>>>>>>>>>>>>>
666 23:45:01.500620 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 23:45:01.504584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 23:45:01.507685 ===================================
669 23:45:01.508156 data_rate = 1600,PCW = 0X7600
670 23:45:01.511785 ===================================
671 23:45:01.515450 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 23:45:01.522446 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 23:45:01.525916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:45:01.532960 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 23:45:01.535869 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 23:45:01.539626 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:45:01.540191 [ANA_INIT] flow start
678 23:45:01.542436 [ANA_INIT] PLL >>>>>>>>
679 23:45:01.545629 [ANA_INIT] PLL <<<<<<<<
680 23:45:01.546096 [ANA_INIT] MIDPI >>>>>>>>
681 23:45:01.549443 [ANA_INIT] MIDPI <<<<<<<<
682 23:45:01.552459 [ANA_INIT] DLL >>>>>>>>
683 23:45:01.553018 [ANA_INIT] flow end
684 23:45:01.555943 ============ LP4 DIFF to SE enter ============
685 23:45:01.562322 ============ LP4 DIFF to SE exit ============
686 23:45:01.562902 [ANA_INIT] <<<<<<<<<<<<<
687 23:45:01.566049 [Flow] Enable top DCM control >>>>>
688 23:45:01.569359 [Flow] Enable top DCM control <<<<<
689 23:45:01.572836 Enable DLL master slave shuffle
690 23:45:01.579264 ==============================================================
691 23:45:01.579734 Gating Mode config
692 23:45:01.586038 ==============================================================
693 23:45:01.589872 Config description:
694 23:45:01.599168 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 23:45:01.606163 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 23:45:01.609463 SELPH_MODE 0: By rank 1: By Phase
697 23:45:01.616181 ==============================================================
698 23:45:01.619120 GAT_TRACK_EN = 1
699 23:45:01.619587 RX_GATING_MODE = 2
700 23:45:01.622910 RX_GATING_TRACK_MODE = 2
701 23:45:01.625842 SELPH_MODE = 1
702 23:45:01.629373 PICG_EARLY_EN = 1
703 23:45:01.632971 VALID_LAT_VALUE = 1
704 23:45:01.639388 ==============================================================
705 23:45:01.642922 Enter into Gating configuration >>>>
706 23:45:01.645891 Exit from Gating configuration <<<<
707 23:45:01.649084 Enter into DVFS_PRE_config >>>>>
708 23:45:01.659209 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 23:45:01.662257 Exit from DVFS_PRE_config <<<<<
710 23:45:01.666185 Enter into PICG configuration >>>>
711 23:45:01.669281 Exit from PICG configuration <<<<
712 23:45:01.672537 [RX_INPUT] configuration >>>>>
713 23:45:01.675431 [RX_INPUT] configuration <<<<<
714 23:45:01.679292 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 23:45:01.685706 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 23:45:01.692666 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 23:45:01.695944 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 23:45:01.702342 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 23:45:01.708808 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 23:45:01.711958 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 23:45:01.719364 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 23:45:01.721926 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 23:45:01.726018 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 23:45:01.729236 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 23:45:01.736109 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 23:45:01.739065 ===================================
727 23:45:01.739530 LPDDR4 DRAM CONFIGURATION
728 23:45:01.742130 ===================================
729 23:45:01.745541 EX_ROW_EN[0] = 0x0
730 23:45:01.749040 EX_ROW_EN[1] = 0x0
731 23:45:01.749644 LP4Y_EN = 0x0
732 23:45:01.752287 WORK_FSP = 0x0
733 23:45:01.752843 WL = 0x2
734 23:45:01.755531 RL = 0x2
735 23:45:01.756054 BL = 0x2
736 23:45:01.759075 RPST = 0x0
737 23:45:01.759632 RD_PRE = 0x0
738 23:45:01.762359 WR_PRE = 0x1
739 23:45:01.762888 WR_PST = 0x0
740 23:45:01.765649 DBI_WR = 0x0
741 23:45:01.766113 DBI_RD = 0x0
742 23:45:01.768854 OTF = 0x1
743 23:45:01.772266 ===================================
744 23:45:01.776142 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 23:45:01.778716 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 23:45:01.785912 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 23:45:01.786479 ===================================
748 23:45:01.789074 LPDDR4 DRAM CONFIGURATION
749 23:45:01.792477 ===================================
750 23:45:01.795548 EX_ROW_EN[0] = 0x10
751 23:45:01.796121 EX_ROW_EN[1] = 0x0
752 23:45:01.799131 LP4Y_EN = 0x0
753 23:45:01.799689 WORK_FSP = 0x0
754 23:45:01.802450 WL = 0x2
755 23:45:01.803025 RL = 0x2
756 23:45:01.805504 BL = 0x2
757 23:45:01.809008 RPST = 0x0
758 23:45:01.809682 RD_PRE = 0x0
759 23:45:01.811841 WR_PRE = 0x1
760 23:45:01.812302 WR_PST = 0x0
761 23:45:01.815444 DBI_WR = 0x0
762 23:45:01.815907 DBI_RD = 0x0
763 23:45:01.818734 OTF = 0x1
764 23:45:01.821642 ===================================
765 23:45:01.828273 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 23:45:01.832238 nWR fixed to 40
767 23:45:01.832706 [ModeRegInit_LP4] CH0 RK0
768 23:45:01.835397 [ModeRegInit_LP4] CH0 RK1
769 23:45:01.838470 [ModeRegInit_LP4] CH1 RK0
770 23:45:01.838949 [ModeRegInit_LP4] CH1 RK1
771 23:45:01.841936 match AC timing 12
772 23:45:01.845220 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
773 23:45:01.848733 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 23:45:01.855133 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 23:45:01.858915 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 23:45:01.865365 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 23:45:01.865834 [EMI DOE] emi_dcm 0
778 23:45:01.868582 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 23:45:01.871869 ==
780 23:45:01.872334 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:45:01.878682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 23:45:01.879234 ==
783 23:45:01.881996 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 23:45:01.888535 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 23:45:01.898130 [CA 0] Center 37 (7~68) winsize 62
786 23:45:01.901449 [CA 1] Center 37 (7~68) winsize 62
787 23:45:01.904961 [CA 2] Center 35 (5~66) winsize 62
788 23:45:01.907944 [CA 3] Center 35 (4~66) winsize 63
789 23:45:01.911165 [CA 4] Center 34 (4~65) winsize 62
790 23:45:01.914625 [CA 5] Center 34 (4~64) winsize 61
791 23:45:01.915085
792 23:45:01.917852 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 23:45:01.918587
794 23:45:01.921219 [CATrainingPosCal] consider 1 rank data
795 23:45:01.924759 u2DelayCellTimex100 = 270/100 ps
796 23:45:01.927995 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
797 23:45:01.931293 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
798 23:45:01.937995 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
799 23:45:01.941110 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
800 23:45:01.944400 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
801 23:45:01.947967 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
802 23:45:01.948472
803 23:45:01.951749 CA PerBit enable=1, Macro0, CA PI delay=34
804 23:45:01.952315
805 23:45:01.954990 [CBTSetCACLKResult] CA Dly = 34
806 23:45:01.955512 CS Dly: 6 (0~37)
807 23:45:01.955970 ==
808 23:45:01.957933 Dram Type= 6, Freq= 0, CH_0, rank 1
809 23:45:01.964845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
810 23:45:01.965436 ==
811 23:45:01.967873 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 23:45:01.974461 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 23:45:01.984146 [CA 0] Center 37 (7~68) winsize 62
814 23:45:01.987140 [CA 1] Center 37 (6~68) winsize 63
815 23:45:01.990771 [CA 2] Center 35 (5~66) winsize 62
816 23:45:01.993861 [CA 3] Center 35 (4~66) winsize 63
817 23:45:01.997369 [CA 4] Center 34 (4~64) winsize 61
818 23:45:02.000910 [CA 5] Center 34 (3~65) winsize 63
819 23:45:02.001524
820 23:45:02.004134 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 23:45:02.004696
822 23:45:02.007348 [CATrainingPosCal] consider 2 rank data
823 23:45:02.010907 u2DelayCellTimex100 = 270/100 ps
824 23:45:02.013646 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
825 23:45:02.017450 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
826 23:45:02.023808 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
827 23:45:02.026916 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
828 23:45:02.030294 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
829 23:45:02.033848 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
830 23:45:02.034353
831 23:45:02.037050 CA PerBit enable=1, Macro0, CA PI delay=34
832 23:45:02.037588
833 23:45:02.040529 [CBTSetCACLKResult] CA Dly = 34
834 23:45:02.041093 CS Dly: 6 (0~37)
835 23:45:02.041560
836 23:45:02.043700 ----->DramcWriteLeveling(PI) begin...
837 23:45:02.047032 ==
838 23:45:02.050684 Dram Type= 6, Freq= 0, CH_0, rank 0
839 23:45:02.053775 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
840 23:45:02.054239 ==
841 23:45:02.057467 Write leveling (Byte 0): 30 => 30
842 23:45:02.060466 Write leveling (Byte 1): 30 => 30
843 23:45:02.064366 DramcWriteLeveling(PI) end<-----
844 23:45:02.065190
845 23:45:02.065823 ==
846 23:45:02.067596 Dram Type= 6, Freq= 0, CH_0, rank 0
847 23:45:02.071465 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
848 23:45:02.071934 ==
849 23:45:02.074884 [Gating] SW mode calibration
850 23:45:02.082050 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 23:45:02.085240 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 23:45:02.088991 0 6 0 | B1->B0 | 3333 3232 | 0 0 | (0 0) (1 0)
853 23:45:02.095641 0 6 4 | B1->B0 | 2d2d 2a2a | 1 0 | (1 0) (1 0)
854 23:45:02.099180 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 23:45:02.102423 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:45:02.105750 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:45:02.112285 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:45:02.115766 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:45:02.119147 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:45:02.125521 0 7 0 | B1->B0 | 2c2c 2e2e | 0 0 | (0 0) (0 0)
861 23:45:02.128707 0 7 4 | B1->B0 | 3a3a 3f3f | 0 1 | (0 0) (0 0)
862 23:45:02.132236 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 23:45:02.138903 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 23:45:02.142055 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 23:45:02.145270 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 23:45:02.151882 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 23:45:02.155324 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 23:45:02.158882 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
869 23:45:02.165190 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 23:45:02.168719 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 23:45:02.171788 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 23:45:02.178587 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 23:45:02.182144 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 23:45:02.185435 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 23:45:02.191927 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 23:45:02.195360 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 23:45:02.199004 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 23:45:02.201816 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 23:45:02.208997 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 23:45:02.212008 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 23:45:02.215285 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 23:45:02.222166 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 23:45:02.225280 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
884 23:45:02.228571 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
885 23:45:02.235524 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 23:45:02.238484 Total UI for P1: 0, mck2ui 16
887 23:45:02.241745 best dqsien dly found for B0: ( 0, 10, 0)
888 23:45:02.241829 Total UI for P1: 0, mck2ui 16
889 23:45:02.248662 best dqsien dly found for B1: ( 0, 10, 0)
890 23:45:02.251999 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
891 23:45:02.255276 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
892 23:45:02.255359
893 23:45:02.258479 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
894 23:45:02.261892 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
895 23:45:02.265071 [Gating] SW calibration Done
896 23:45:02.265153 ==
897 23:45:02.268424 Dram Type= 6, Freq= 0, CH_0, rank 0
898 23:45:02.271830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
899 23:45:02.271914 ==
900 23:45:02.275038 RX Vref Scan: 0
901 23:45:02.275121
902 23:45:02.275187 RX Vref 0 -> 0, step: 1
903 23:45:02.275249
904 23:45:02.278509 RX Delay -130 -> 252, step: 16
905 23:45:02.281812 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
906 23:45:02.288227 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
907 23:45:02.291901 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
908 23:45:02.294937 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
909 23:45:02.298245 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
910 23:45:02.301619 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
911 23:45:02.308315 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
912 23:45:02.312303 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
913 23:45:02.314931 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
914 23:45:02.318525 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
915 23:45:02.321469 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
916 23:45:02.328625 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
917 23:45:02.331742 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
918 23:45:02.335267 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
919 23:45:02.338367 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
920 23:45:02.344711 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
921 23:45:02.344798 ==
922 23:45:02.348216 Dram Type= 6, Freq= 0, CH_0, rank 0
923 23:45:02.351772 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
924 23:45:02.351855 ==
925 23:45:02.351920 DQS Delay:
926 23:45:02.354985 DQS0 = 0, DQS1 = 0
927 23:45:02.355067 DQM Delay:
928 23:45:02.358306 DQM0 = 82, DQM1 = 74
929 23:45:02.358387 DQ Delay:
930 23:45:02.361738 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
931 23:45:02.364885 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
932 23:45:02.368116 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
933 23:45:02.371497 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
934 23:45:02.371606
935 23:45:02.371699
936 23:45:02.371787 ==
937 23:45:02.374823 Dram Type= 6, Freq= 0, CH_0, rank 0
938 23:45:02.378456 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
939 23:45:02.378539 ==
940 23:45:02.378605
941 23:45:02.378663
942 23:45:02.381391 TX Vref Scan disable
943 23:45:02.384954 == TX Byte 0 ==
944 23:45:02.388303 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
945 23:45:02.391994 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
946 23:45:02.395257 == TX Byte 1 ==
947 23:45:02.398275 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
948 23:45:02.401698 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
949 23:45:02.401781 ==
950 23:45:02.405232 Dram Type= 6, Freq= 0, CH_0, rank 0
951 23:45:02.408790 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
952 23:45:02.411577 ==
953 23:45:02.422610 TX Vref=22, minBit 4, minWin=27, winSum=445
954 23:45:02.426207 TX Vref=24, minBit 3, minWin=27, winSum=449
955 23:45:02.429665 TX Vref=26, minBit 2, minWin=28, winSum=455
956 23:45:02.432548 TX Vref=28, minBit 0, minWin=28, winSum=456
957 23:45:02.436071 TX Vref=30, minBit 0, minWin=28, winSum=457
958 23:45:02.439797 TX Vref=32, minBit 1, minWin=27, winSum=454
959 23:45:02.445813 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
960 23:45:02.445900
961 23:45:02.449449 Final TX Range 1 Vref 30
962 23:45:02.449532
963 23:45:02.449597 ==
964 23:45:02.452420 Dram Type= 6, Freq= 0, CH_0, rank 0
965 23:45:02.455925 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
966 23:45:02.456009 ==
967 23:45:02.456074
968 23:45:02.459242
969 23:45:02.459331 TX Vref Scan disable
970 23:45:02.462995 == TX Byte 0 ==
971 23:45:02.466574 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
972 23:45:02.469764 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
973 23:45:02.473232 == TX Byte 1 ==
974 23:45:02.476882 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
975 23:45:02.479897 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
976 23:45:02.480014
977 23:45:02.483065 [DATLAT]
978 23:45:02.483147 Freq=800, CH0 RK0
979 23:45:02.483213
980 23:45:02.487209 DATLAT Default: 0xa
981 23:45:02.487374 0, 0xFFFF, sum = 0
982 23:45:02.489873 1, 0xFFFF, sum = 0
983 23:45:02.490040 2, 0xFFFF, sum = 0
984 23:45:02.493932 3, 0xFFFF, sum = 0
985 23:45:02.494098 4, 0xFFFF, sum = 0
986 23:45:02.497062 5, 0xFFFF, sum = 0
987 23:45:02.497228 6, 0xFFFF, sum = 0
988 23:45:02.500044 7, 0xFFFF, sum = 0
989 23:45:02.500218 8, 0x0, sum = 1
990 23:45:02.503280 9, 0x0, sum = 2
991 23:45:02.503369 10, 0x0, sum = 3
992 23:45:02.507380 11, 0x0, sum = 4
993 23:45:02.507949 best_step = 9
994 23:45:02.508316
995 23:45:02.508654 ==
996 23:45:02.510363 Dram Type= 6, Freq= 0, CH_0, rank 0
997 23:45:02.513425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
998 23:45:02.516923 ==
999 23:45:02.517434 RX Vref Scan: 1
1000 23:45:02.517805
1001 23:45:02.520083 Set Vref Range= 32 -> 127
1002 23:45:02.520544
1003 23:45:02.520905 RX Vref 32 -> 127, step: 1
1004 23:45:02.524143
1005 23:45:02.524705 RX Delay -111 -> 252, step: 8
1006 23:45:02.525074
1007 23:45:02.527407 Set Vref, RX VrefLevel [Byte0]: 32
1008 23:45:02.530027 [Byte1]: 32
1009 23:45:02.534216
1010 23:45:02.534778 Set Vref, RX VrefLevel [Byte0]: 33
1011 23:45:02.537393 [Byte1]: 33
1012 23:45:02.542007
1013 23:45:02.542601 Set Vref, RX VrefLevel [Byte0]: 34
1014 23:45:02.545455 [Byte1]: 34
1015 23:45:02.549573
1016 23:45:02.550135 Set Vref, RX VrefLevel [Byte0]: 35
1017 23:45:02.553151 [Byte1]: 35
1018 23:45:02.557101
1019 23:45:02.557728 Set Vref, RX VrefLevel [Byte0]: 36
1020 23:45:02.560389 [Byte1]: 36
1021 23:45:02.564571
1022 23:45:02.565029 Set Vref, RX VrefLevel [Byte0]: 37
1023 23:45:02.568170 [Byte1]: 37
1024 23:45:02.572249
1025 23:45:02.572745 Set Vref, RX VrefLevel [Byte0]: 38
1026 23:45:02.575592 [Byte1]: 38
1027 23:45:02.579818
1028 23:45:02.580363 Set Vref, RX VrefLevel [Byte0]: 39
1029 23:45:02.583081 [Byte1]: 39
1030 23:45:02.587636
1031 23:45:02.588302 Set Vref, RX VrefLevel [Byte0]: 40
1032 23:45:02.591011 [Byte1]: 40
1033 23:45:02.595211
1034 23:45:02.595773 Set Vref, RX VrefLevel [Byte0]: 41
1035 23:45:02.598230 [Byte1]: 41
1036 23:45:02.602894
1037 23:45:02.603442 Set Vref, RX VrefLevel [Byte0]: 42
1038 23:45:02.606321 [Byte1]: 42
1039 23:45:02.610504
1040 23:45:02.611050 Set Vref, RX VrefLevel [Byte0]: 43
1041 23:45:02.613838 [Byte1]: 43
1042 23:45:02.618281
1043 23:45:02.618910 Set Vref, RX VrefLevel [Byte0]: 44
1044 23:45:02.621368 [Byte1]: 44
1045 23:45:02.625878
1046 23:45:02.626428 Set Vref, RX VrefLevel [Byte0]: 45
1047 23:45:02.629244 [Byte1]: 45
1048 23:45:02.633783
1049 23:45:02.634331 Set Vref, RX VrefLevel [Byte0]: 46
1050 23:45:02.636979 [Byte1]: 46
1051 23:45:02.641446
1052 23:45:02.641987 Set Vref, RX VrefLevel [Byte0]: 47
1053 23:45:02.644311 [Byte1]: 47
1054 23:45:02.648817
1055 23:45:02.649396 Set Vref, RX VrefLevel [Byte0]: 48
1056 23:45:02.652090 [Byte1]: 48
1057 23:45:02.656773
1058 23:45:02.657484 Set Vref, RX VrefLevel [Byte0]: 49
1059 23:45:02.659783 [Byte1]: 49
1060 23:45:02.663884
1061 23:45:02.664333 Set Vref, RX VrefLevel [Byte0]: 50
1062 23:45:02.667253 [Byte1]: 50
1063 23:45:02.671843
1064 23:45:02.672384 Set Vref, RX VrefLevel [Byte0]: 51
1065 23:45:02.675109 [Byte1]: 51
1066 23:45:02.679572
1067 23:45:02.680124 Set Vref, RX VrefLevel [Byte0]: 52
1068 23:45:02.682627 [Byte1]: 52
1069 23:45:02.687061
1070 23:45:02.687607 Set Vref, RX VrefLevel [Byte0]: 53
1071 23:45:02.690321 [Byte1]: 53
1072 23:45:02.694921
1073 23:45:02.695468 Set Vref, RX VrefLevel [Byte0]: 54
1074 23:45:02.697642 [Byte1]: 54
1075 23:45:02.702145
1076 23:45:02.702700 Set Vref, RX VrefLevel [Byte0]: 55
1077 23:45:02.705521 [Byte1]: 55
1078 23:45:02.709898
1079 23:45:02.710444 Set Vref, RX VrefLevel [Byte0]: 56
1080 23:45:02.712892 [Byte1]: 56
1081 23:45:02.717448
1082 23:45:02.717905 Set Vref, RX VrefLevel [Byte0]: 57
1083 23:45:02.720903 [Byte1]: 57
1084 23:45:02.725237
1085 23:45:02.725844 Set Vref, RX VrefLevel [Byte0]: 58
1086 23:45:02.728614 [Byte1]: 58
1087 23:45:02.733332
1088 23:45:02.733886 Set Vref, RX VrefLevel [Byte0]: 59
1089 23:45:02.736431 [Byte1]: 59
1090 23:45:02.740900
1091 23:45:02.741486 Set Vref, RX VrefLevel [Byte0]: 60
1092 23:45:02.744344 [Byte1]: 60
1093 23:45:02.747816
1094 23:45:02.751574 Set Vref, RX VrefLevel [Byte0]: 61
1095 23:45:02.752132 [Byte1]: 61
1096 23:45:02.756032
1097 23:45:02.756575 Set Vref, RX VrefLevel [Byte0]: 62
1098 23:45:02.759411 [Byte1]: 62
1099 23:45:02.763589
1100 23:45:02.764062 Set Vref, RX VrefLevel [Byte0]: 63
1101 23:45:02.767276 [Byte1]: 63
1102 23:45:02.770790
1103 23:45:02.771290 Set Vref, RX VrefLevel [Byte0]: 64
1104 23:45:02.774200 [Byte1]: 64
1105 23:45:02.778476
1106 23:45:02.779032 Set Vref, RX VrefLevel [Byte0]: 65
1107 23:45:02.781831 [Byte1]: 65
1108 23:45:02.786192
1109 23:45:02.786749 Set Vref, RX VrefLevel [Byte0]: 66
1110 23:45:02.789737 [Byte1]: 66
1111 23:45:02.794226
1112 23:45:02.794783 Set Vref, RX VrefLevel [Byte0]: 67
1113 23:45:02.797379 [Byte1]: 67
1114 23:45:02.801566
1115 23:45:02.802019 Set Vref, RX VrefLevel [Byte0]: 68
1116 23:45:02.805114 [Byte1]: 68
1117 23:45:02.809538
1118 23:45:02.810094 Set Vref, RX VrefLevel [Byte0]: 69
1119 23:45:02.812297 [Byte1]: 69
1120 23:45:02.816789
1121 23:45:02.817246 Set Vref, RX VrefLevel [Byte0]: 70
1122 23:45:02.819879 [Byte1]: 70
1123 23:45:02.824471
1124 23:45:02.825089 Set Vref, RX VrefLevel [Byte0]: 71
1125 23:45:02.827763 [Byte1]: 71
1126 23:45:02.832113
1127 23:45:02.832665 Set Vref, RX VrefLevel [Byte0]: 72
1128 23:45:02.835558 [Byte1]: 72
1129 23:45:02.840094
1130 23:45:02.840645 Set Vref, RX VrefLevel [Byte0]: 73
1131 23:45:02.843027 [Byte1]: 73
1132 23:45:02.847529
1133 23:45:02.848077 Set Vref, RX VrefLevel [Byte0]: 74
1134 23:45:02.850881 [Byte1]: 74
1135 23:45:02.855250
1136 23:45:02.855797 Set Vref, RX VrefLevel [Byte0]: 75
1137 23:45:02.858681 [Byte1]: 75
1138 23:45:02.862723
1139 23:45:02.863304 Set Vref, RX VrefLevel [Byte0]: 76
1140 23:45:02.866234 [Byte1]: 76
1141 23:45:02.870573
1142 23:45:02.871124 Final RX Vref Byte 0 = 50 to rank0
1143 23:45:02.873970 Final RX Vref Byte 1 = 56 to rank0
1144 23:45:02.877440 Final RX Vref Byte 0 = 50 to rank1
1145 23:45:02.880425 Final RX Vref Byte 1 = 56 to rank1==
1146 23:45:02.883987 Dram Type= 6, Freq= 0, CH_0, rank 0
1147 23:45:02.887187 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1148 23:45:02.890745 ==
1149 23:45:02.891292 DQS Delay:
1150 23:45:02.891659 DQS0 = 0, DQS1 = 0
1151 23:45:02.893902 DQM Delay:
1152 23:45:02.894359 DQM0 = 84, DQM1 = 73
1153 23:45:02.897140 DQ Delay:
1154 23:45:02.900500 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1155 23:45:02.900963 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1156 23:45:02.903878 DQ8 =64, DQ9 =56, DQ10 =76, DQ11 =64
1157 23:45:02.907178 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1158 23:45:02.910617
1159 23:45:02.911109
1160 23:45:02.916888 [DQSOSCAuto] RK0, (LSB)MR18= 0x3535, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
1161 23:45:02.920303 CH0 RK0: MR19=606, MR18=3535
1162 23:45:02.927002 CH0_RK0: MR19=0x606, MR18=0x3535, DQSOSC=396, MR23=63, INC=94, DEC=62
1163 23:45:02.927496
1164 23:45:02.930556 ----->DramcWriteLeveling(PI) begin...
1165 23:45:02.931023 ==
1166 23:45:02.933706 Dram Type= 6, Freq= 0, CH_0, rank 1
1167 23:45:02.937094 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1168 23:45:02.937516 ==
1169 23:45:02.940411 Write leveling (Byte 0): 30 => 30
1170 23:45:02.943455 Write leveling (Byte 1): 26 => 26
1171 23:45:02.946681 DramcWriteLeveling(PI) end<-----
1172 23:45:02.946898
1173 23:45:02.947058 ==
1174 23:45:02.950073 Dram Type= 6, Freq= 0, CH_0, rank 1
1175 23:45:02.953305 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1176 23:45:02.953473 ==
1177 23:45:02.956898 [Gating] SW mode calibration
1178 23:45:02.963354 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1179 23:45:02.970119 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1180 23:45:02.973523 0 6 0 | B1->B0 | 3333 2f2f | 0 0 | (1 0) (1 0)
1181 23:45:02.976782 0 6 4 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
1182 23:45:02.983744 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 23:45:02.986900 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 23:45:02.990454 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:45:02.996952 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:45:03.000403 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 23:45:03.003547 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:45:03.010056 0 7 0 | B1->B0 | 2828 2f2f | 1 0 | (0 0) (0 0)
1189 23:45:03.013237 0 7 4 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)
1190 23:45:03.016686 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 23:45:03.023503 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 23:45:03.026892 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 23:45:03.030244 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 23:45:03.033445 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 23:45:03.040356 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:45:03.044170 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1197 23:45:03.047276 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1198 23:45:03.053662 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 23:45:03.057257 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 23:45:03.060408 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 23:45:03.066839 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 23:45:03.070259 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:45:03.074152 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:45:03.080665 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:45:03.083912 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:45:03.087008 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:45:03.094132 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:45:03.096943 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:45:03.100507 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:45:03.107584 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:45:03.110407 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:45:03.114101 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1213 23:45:03.120168 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1214 23:45:03.123860 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 23:45:03.127315 Total UI for P1: 0, mck2ui 16
1216 23:45:03.130497 best dqsien dly found for B0: ( 0, 10, 2)
1217 23:45:03.133706 Total UI for P1: 0, mck2ui 16
1218 23:45:03.137216 best dqsien dly found for B1: ( 0, 10, 2)
1219 23:45:03.140378 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1220 23:45:03.184756 best DQS1 dly(MCK, UI, PI) = (0, 10, 2)
1221 23:45:03.185382
1222 23:45:03.185869 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1223 23:45:03.186323 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 2)
1224 23:45:03.187143 [Gating] SW calibration Done
1225 23:45:03.187541 ==
1226 23:45:03.187986 Dram Type= 6, Freq= 0, CH_0, rank 1
1227 23:45:03.188416 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1228 23:45:03.188952 ==
1229 23:45:03.189506 RX Vref Scan: 0
1230 23:45:03.189940
1231 23:45:03.190361 RX Vref 0 -> 0, step: 1
1232 23:45:03.190778
1233 23:45:03.191300 RX Delay -130 -> 252, step: 16
1234 23:45:03.191723 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1235 23:45:03.192140 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1236 23:45:03.192665 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1237 23:45:03.193188 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1238 23:45:03.204327 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1239 23:45:03.204898 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1240 23:45:03.205509 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1241 23:45:03.206350 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1242 23:45:03.207758 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1243 23:45:03.208234 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1244 23:45:03.211128 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1245 23:45:03.217473 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1246 23:45:03.221055 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1247 23:45:03.224728 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1248 23:45:03.227798 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1249 23:45:03.231382 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1250 23:45:03.234466 ==
1251 23:45:03.235032 Dram Type= 6, Freq= 0, CH_0, rank 1
1252 23:45:03.241119 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1253 23:45:03.241832 ==
1254 23:45:03.242211 DQS Delay:
1255 23:45:03.244206 DQS0 = 0, DQS1 = 0
1256 23:45:03.244999 DQM Delay:
1257 23:45:03.247613 DQM0 = 83, DQM1 = 73
1258 23:45:03.248071 DQ Delay:
1259 23:45:03.251308 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =69
1260 23:45:03.254458 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1261 23:45:03.257558 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =69
1262 23:45:03.260907 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1263 23:45:03.261527
1264 23:45:03.261898
1265 23:45:03.262231 ==
1266 23:45:03.264543 Dram Type= 6, Freq= 0, CH_0, rank 1
1267 23:45:03.267352 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1268 23:45:03.267816 ==
1269 23:45:03.268182
1270 23:45:03.268519
1271 23:45:03.270848 TX Vref Scan disable
1272 23:45:03.273954 == TX Byte 0 ==
1273 23:45:03.277336 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1274 23:45:03.280680 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1275 23:45:03.284246 == TX Byte 1 ==
1276 23:45:03.287342 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1277 23:45:03.290806 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1278 23:45:03.291266 ==
1279 23:45:03.294352 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 23:45:03.297976 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1281 23:45:03.300981 ==
1282 23:45:03.313018 TX Vref=22, minBit 1, minWin=27, winSum=442
1283 23:45:03.316191 TX Vref=24, minBit 8, minWin=27, winSum=448
1284 23:45:03.320203 TX Vref=26, minBit 13, minWin=27, winSum=453
1285 23:45:03.323447 TX Vref=28, minBit 2, minWin=28, winSum=458
1286 23:45:03.326937 TX Vref=30, minBit 0, minWin=28, winSum=455
1287 23:45:03.330758 TX Vref=32, minBit 2, minWin=28, winSum=455
1288 23:45:03.337534 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 28
1289 23:45:03.338012
1290 23:45:03.340838 Final TX Range 1 Vref 28
1291 23:45:03.341347
1292 23:45:03.341828 ==
1293 23:45:03.344070 Dram Type= 6, Freq= 0, CH_0, rank 1
1294 23:45:03.347294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1295 23:45:03.347715 ==
1296 23:45:03.348041
1297 23:45:03.348341
1298 23:45:03.350663 TX Vref Scan disable
1299 23:45:03.351077 == TX Byte 0 ==
1300 23:45:03.357656 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1301 23:45:03.360667 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1302 23:45:03.361085 == TX Byte 1 ==
1303 23:45:03.367501 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1304 23:45:03.370729 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1305 23:45:03.371165
1306 23:45:03.371525 [DATLAT]
1307 23:45:03.374248 Freq=800, CH0 RK1
1308 23:45:03.374782
1309 23:45:03.375138 DATLAT Default: 0x9
1310 23:45:03.377255 0, 0xFFFF, sum = 0
1311 23:45:03.377740 1, 0xFFFF, sum = 0
1312 23:45:03.380842 2, 0xFFFF, sum = 0
1313 23:45:03.381337 3, 0xFFFF, sum = 0
1314 23:45:03.384221 4, 0xFFFF, sum = 0
1315 23:45:03.387334 5, 0xFFFF, sum = 0
1316 23:45:03.387801 6, 0xFFFF, sum = 0
1317 23:45:03.390971 7, 0xFFFF, sum = 0
1318 23:45:03.391541 8, 0x0, sum = 1
1319 23:45:03.391923 9, 0x0, sum = 2
1320 23:45:03.393945 10, 0x0, sum = 3
1321 23:45:03.394413 11, 0x0, sum = 4
1322 23:45:03.397447 best_step = 9
1323 23:45:03.397906
1324 23:45:03.398302 ==
1325 23:45:03.400597 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 23:45:03.404074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1327 23:45:03.404492 ==
1328 23:45:03.407051 RX Vref Scan: 0
1329 23:45:03.407473
1330 23:45:03.407806 RX Vref 0 -> 0, step: 1
1331 23:45:03.408114
1332 23:45:03.410586 RX Delay -111 -> 252, step: 8
1333 23:45:03.417257 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1334 23:45:03.420394 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1335 23:45:03.423834 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1336 23:45:03.427420 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1337 23:45:03.430720 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1338 23:45:03.437485 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1339 23:45:03.440797 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1340 23:45:03.443963 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1341 23:45:03.447708 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1342 23:45:03.450607 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1343 23:45:03.457502 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1344 23:45:03.460866 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1345 23:45:03.463931 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1346 23:45:03.467397 iDelay=217, Bit 13, Center 80 (-39 ~ 200) 240
1347 23:45:03.474116 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1348 23:45:03.477196 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1349 23:45:03.477788 ==
1350 23:45:03.480574 Dram Type= 6, Freq= 0, CH_0, rank 1
1351 23:45:03.484027 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1352 23:45:03.484591 ==
1353 23:45:03.484956 DQS Delay:
1354 23:45:03.487190 DQS0 = 0, DQS1 = 0
1355 23:45:03.487746 DQM Delay:
1356 23:45:03.491021 DQM0 = 86, DQM1 = 74
1357 23:45:03.491578 DQ Delay:
1358 23:45:03.494203 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1359 23:45:03.496955 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1360 23:45:03.500312 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1361 23:45:03.503736 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1362 23:45:03.504192
1363 23:45:03.504551
1364 23:45:03.513888 [DQSOSCAuto] RK1, (LSB)MR18= 0x4848, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
1365 23:45:03.514346 CH0 RK1: MR19=606, MR18=4848
1366 23:45:03.520213 CH0_RK1: MR19=0x606, MR18=0x4848, DQSOSC=391, MR23=63, INC=96, DEC=64
1367 23:45:03.523615 [RxdqsGatingPostProcess] freq 800
1368 23:45:03.529955 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1369 23:45:03.533364 Pre-setting of DQS Precalculation
1370 23:45:03.536857 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1371 23:45:03.537337 ==
1372 23:45:03.540156 Dram Type= 6, Freq= 0, CH_1, rank 0
1373 23:45:03.543737 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1374 23:45:03.546415 ==
1375 23:45:03.549742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1376 23:45:03.556564 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1377 23:45:03.564866 [CA 0] Center 37 (6~68) winsize 63
1378 23:45:03.568405 [CA 1] Center 37 (6~68) winsize 63
1379 23:45:03.571522 [CA 2] Center 34 (4~65) winsize 62
1380 23:45:03.574920 [CA 3] Center 34 (4~65) winsize 62
1381 23:45:03.578153 [CA 4] Center 33 (3~64) winsize 62
1382 23:45:03.581739 [CA 5] Center 33 (3~64) winsize 62
1383 23:45:03.582056
1384 23:45:03.584933 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1385 23:45:03.585281
1386 23:45:03.588462 [CATrainingPosCal] consider 1 rank data
1387 23:45:03.591656 u2DelayCellTimex100 = 270/100 ps
1388 23:45:03.595013 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1389 23:45:03.598235 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1390 23:45:03.605172 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1391 23:45:03.608120 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1392 23:45:03.611395 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1393 23:45:03.614821 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1394 23:45:03.614976
1395 23:45:03.617967 CA PerBit enable=1, Macro0, CA PI delay=33
1396 23:45:03.618123
1397 23:45:03.621414 [CBTSetCACLKResult] CA Dly = 33
1398 23:45:03.621570 CS Dly: 4 (0~35)
1399 23:45:03.621693 ==
1400 23:45:03.624617 Dram Type= 6, Freq= 0, CH_1, rank 1
1401 23:45:03.631369 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1402 23:45:03.631526 ==
1403 23:45:03.634972 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1404 23:45:03.641552 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1405 23:45:03.650942 [CA 0] Center 37 (6~68) winsize 63
1406 23:45:03.654306 [CA 1] Center 37 (6~68) winsize 63
1407 23:45:03.657717 [CA 2] Center 34 (4~65) winsize 62
1408 23:45:03.660879 [CA 3] Center 34 (4~65) winsize 62
1409 23:45:03.664201 [CA 4] Center 33 (3~64) winsize 62
1410 23:45:03.667798 [CA 5] Center 33 (3~64) winsize 62
1411 23:45:03.668057
1412 23:45:03.670999 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1413 23:45:03.671297
1414 23:45:03.674449 [CATrainingPosCal] consider 2 rank data
1415 23:45:03.677998 u2DelayCellTimex100 = 270/100 ps
1416 23:45:03.681369 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1417 23:45:03.684842 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1418 23:45:03.691207 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1419 23:45:03.694696 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1420 23:45:03.697777 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1421 23:45:03.701561 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1422 23:45:03.702110
1423 23:45:03.704456 CA PerBit enable=1, Macro0, CA PI delay=33
1424 23:45:03.705005
1425 23:45:03.708074 [CBTSetCACLKResult] CA Dly = 33
1426 23:45:03.708620 CS Dly: 5 (0~37)
1427 23:45:03.708976
1428 23:45:03.711172 ----->DramcWriteLeveling(PI) begin...
1429 23:45:03.714545 ==
1430 23:45:03.715090 Dram Type= 6, Freq= 0, CH_1, rank 0
1431 23:45:03.721106 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1432 23:45:03.721694 ==
1433 23:45:03.724390 Write leveling (Byte 0): 26 => 26
1434 23:45:03.727536 Write leveling (Byte 1): 26 => 26
1435 23:45:03.731435 DramcWriteLeveling(PI) end<-----
1436 23:45:03.731980
1437 23:45:03.732340 ==
1438 23:45:03.734320 Dram Type= 6, Freq= 0, CH_1, rank 0
1439 23:45:03.737677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1440 23:45:03.738135 ==
1441 23:45:03.741095 [Gating] SW mode calibration
1442 23:45:03.747605 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1443 23:45:03.751469 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1444 23:45:03.757976 0 6 0 | B1->B0 | 3333 2a2a | 0 0 | (0 0) (1 1)
1445 23:45:03.760892 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 23:45:03.764702 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 23:45:03.771621 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 23:45:03.774393 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 23:45:03.777972 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 23:45:03.784875 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 23:45:03.788004 0 6 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1452 23:45:03.791264 0 7 0 | B1->B0 | 3030 4242 | 0 0 | (0 0) (0 0)
1453 23:45:03.797443 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1454 23:45:03.801032 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1455 23:45:03.804259 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1456 23:45:03.810801 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1457 23:45:03.814020 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1458 23:45:03.817687 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1459 23:45:03.824048 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1460 23:45:03.827451 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1461 23:45:03.830599 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 23:45:03.837435 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 23:45:03.840751 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 23:45:03.844266 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 23:45:03.850578 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 23:45:03.854167 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 23:45:03.857437 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 23:45:03.860844 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 23:45:03.866985 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1470 23:45:03.870613 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1471 23:45:03.874205 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1472 23:45:03.880467 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1473 23:45:03.884537 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1474 23:45:03.887378 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1475 23:45:03.893999 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1476 23:45:03.897492 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1477 23:45:03.900967 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1478 23:45:03.904018 Total UI for P1: 0, mck2ui 16
1479 23:45:03.907511 best dqsien dly found for B0: ( 0, 9, 30)
1480 23:45:03.910766 Total UI for P1: 0, mck2ui 16
1481 23:45:03.914374 best dqsien dly found for B1: ( 0, 9, 30)
1482 23:45:03.917055 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1483 23:45:03.920417 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1484 23:45:03.920880
1485 23:45:03.927769 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1486 23:45:03.930737 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1487 23:45:03.933973 [Gating] SW calibration Done
1488 23:45:03.934519 ==
1489 23:45:03.937549 Dram Type= 6, Freq= 0, CH_1, rank 0
1490 23:45:03.940475 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1491 23:45:03.941026 ==
1492 23:45:03.941453 RX Vref Scan: 0
1493 23:45:03.941808
1494 23:45:03.943649 RX Vref 0 -> 0, step: 1
1495 23:45:03.944106
1496 23:45:03.947104 RX Delay -130 -> 252, step: 16
1497 23:45:03.950628 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1498 23:45:03.953855 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1499 23:45:03.960603 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1500 23:45:03.964084 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1501 23:45:03.967059 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1502 23:45:03.970523 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1503 23:45:03.974334 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1504 23:45:03.977922 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1505 23:45:03.981440 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1506 23:45:03.989165 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1507 23:45:03.991706 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1508 23:45:03.995588 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1509 23:45:03.998793 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1510 23:45:04.003020 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1511 23:45:04.005962 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1512 23:45:04.009794 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1513 23:45:04.010353 ==
1514 23:45:04.013178 Dram Type= 6, Freq= 0, CH_1, rank 0
1515 23:45:04.019721 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1516 23:45:04.020186 ==
1517 23:45:04.020548 DQS Delay:
1518 23:45:04.023149 DQS0 = 0, DQS1 = 0
1519 23:45:04.023611 DQM Delay:
1520 23:45:04.023974 DQM0 = 81, DQM1 = 73
1521 23:45:04.026656 DQ Delay:
1522 23:45:04.029884 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1523 23:45:04.033452 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1524 23:45:04.036459 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1525 23:45:04.040273 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =85
1526 23:45:04.040831
1527 23:45:04.041195
1528 23:45:04.041607 ==
1529 23:45:04.043260 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 23:45:04.046453 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1531 23:45:04.046917 ==
1532 23:45:04.047282
1533 23:45:04.047618
1534 23:45:04.049815 TX Vref Scan disable
1535 23:45:04.050275 == TX Byte 0 ==
1536 23:45:04.056672 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1537 23:45:04.060040 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1538 23:45:04.060593 == TX Byte 1 ==
1539 23:45:04.066539 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1540 23:45:04.069890 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1541 23:45:04.070438 ==
1542 23:45:04.073197 Dram Type= 6, Freq= 0, CH_1, rank 0
1543 23:45:04.076460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1544 23:45:04.076921 ==
1545 23:45:04.090479 TX Vref=22, minBit 8, minWin=27, winSum=446
1546 23:45:04.093888 TX Vref=24, minBit 8, minWin=27, winSum=448
1547 23:45:04.097464 TX Vref=26, minBit 0, minWin=28, winSum=452
1548 23:45:04.100429 TX Vref=28, minBit 0, minWin=28, winSum=458
1549 23:45:04.103364 TX Vref=30, minBit 0, minWin=28, winSum=459
1550 23:45:04.110685 TX Vref=32, minBit 1, minWin=28, winSum=455
1551 23:45:04.113461 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1552 23:45:04.114010
1553 23:45:04.117119 Final TX Range 1 Vref 30
1554 23:45:04.117722
1555 23:45:04.118087 ==
1556 23:45:04.120511 Dram Type= 6, Freq= 0, CH_1, rank 0
1557 23:45:04.123572 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1558 23:45:04.124033 ==
1559 23:45:04.127080
1560 23:45:04.127643
1561 23:45:04.128003 TX Vref Scan disable
1562 23:45:04.129930 == TX Byte 0 ==
1563 23:45:04.133373 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1564 23:45:04.140471 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1565 23:45:04.141024 == TX Byte 1 ==
1566 23:45:04.143668 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1567 23:45:04.146780 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1568 23:45:04.150229
1569 23:45:04.150777 [DATLAT]
1570 23:45:04.151142 Freq=800, CH1 RK0
1571 23:45:04.151483
1572 23:45:04.153554 DATLAT Default: 0xa
1573 23:45:04.154014 0, 0xFFFF, sum = 0
1574 23:45:04.156832 1, 0xFFFF, sum = 0
1575 23:45:04.157334 2, 0xFFFF, sum = 0
1576 23:45:04.160286 3, 0xFFFF, sum = 0
1577 23:45:04.160838 4, 0xFFFF, sum = 0
1578 23:45:04.163812 5, 0xFFFF, sum = 0
1579 23:45:04.166654 6, 0xFFFF, sum = 0
1580 23:45:04.167130 7, 0xFFFF, sum = 0
1581 23:45:04.167506 8, 0x0, sum = 1
1582 23:45:04.170199 9, 0x0, sum = 2
1583 23:45:04.170762 10, 0x0, sum = 3
1584 23:45:04.173414 11, 0x0, sum = 4
1585 23:45:04.173882 best_step = 9
1586 23:45:04.174241
1587 23:45:04.174575 ==
1588 23:45:04.176862 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 23:45:04.184045 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1590 23:45:04.184600 ==
1591 23:45:04.184967 RX Vref Scan: 1
1592 23:45:04.185342
1593 23:45:04.186743 Set Vref Range= 32 -> 127
1594 23:45:04.187199
1595 23:45:04.190329 RX Vref 32 -> 127, step: 1
1596 23:45:04.190787
1597 23:45:04.191152 RX Delay -111 -> 252, step: 8
1598 23:45:04.193402
1599 23:45:04.193862 Set Vref, RX VrefLevel [Byte0]: 32
1600 23:45:04.196995 [Byte1]: 32
1601 23:45:04.201591
1602 23:45:04.202138 Set Vref, RX VrefLevel [Byte0]: 33
1603 23:45:04.204837 [Byte1]: 33
1604 23:45:04.208645
1605 23:45:04.209102 Set Vref, RX VrefLevel [Byte0]: 34
1606 23:45:04.212550 [Byte1]: 34
1607 23:45:04.216481
1608 23:45:04.217035 Set Vref, RX VrefLevel [Byte0]: 35
1609 23:45:04.219936 [Byte1]: 35
1610 23:45:04.224124
1611 23:45:04.224588 Set Vref, RX VrefLevel [Byte0]: 36
1612 23:45:04.227207 [Byte1]: 36
1613 23:45:04.231914
1614 23:45:04.232462 Set Vref, RX VrefLevel [Byte0]: 37
1615 23:45:04.235355 [Byte1]: 37
1616 23:45:04.239637
1617 23:45:04.240359 Set Vref, RX VrefLevel [Byte0]: 38
1618 23:45:04.243024 [Byte1]: 38
1619 23:45:04.247175
1620 23:45:04.247725 Set Vref, RX VrefLevel [Byte0]: 39
1621 23:45:04.250242 [Byte1]: 39
1622 23:45:04.254992
1623 23:45:04.255545 Set Vref, RX VrefLevel [Byte0]: 40
1624 23:45:04.257908 [Byte1]: 40
1625 23:45:04.262287
1626 23:45:04.262744 Set Vref, RX VrefLevel [Byte0]: 41
1627 23:45:04.265598 [Byte1]: 41
1628 23:45:04.270263
1629 23:45:04.270813 Set Vref, RX VrefLevel [Byte0]: 42
1630 23:45:04.273240 [Byte1]: 42
1631 23:45:04.277989
1632 23:45:04.278547 Set Vref, RX VrefLevel [Byte0]: 43
1633 23:45:04.281317 [Byte1]: 43
1634 23:45:04.285442
1635 23:45:04.285986 Set Vref, RX VrefLevel [Byte0]: 44
1636 23:45:04.288654 [Byte1]: 44
1637 23:45:04.293143
1638 23:45:04.293729 Set Vref, RX VrefLevel [Byte0]: 45
1639 23:45:04.296441 [Byte1]: 45
1640 23:45:04.301151
1641 23:45:04.301740 Set Vref, RX VrefLevel [Byte0]: 46
1642 23:45:04.304306 [Byte1]: 46
1643 23:45:04.308447
1644 23:45:04.308993 Set Vref, RX VrefLevel [Byte0]: 47
1645 23:45:04.311604 [Byte1]: 47
1646 23:45:04.316149
1647 23:45:04.316695 Set Vref, RX VrefLevel [Byte0]: 48
1648 23:45:04.319606 [Byte1]: 48
1649 23:45:04.323343
1650 23:45:04.323810 Set Vref, RX VrefLevel [Byte0]: 49
1651 23:45:04.330177 [Byte1]: 49
1652 23:45:04.330726
1653 23:45:04.333698 Set Vref, RX VrefLevel [Byte0]: 50
1654 23:45:04.336638 [Byte1]: 50
1655 23:45:04.337194
1656 23:45:04.340363 Set Vref, RX VrefLevel [Byte0]: 51
1657 23:45:04.343406 [Byte1]: 51
1658 23:45:04.343953
1659 23:45:04.346642 Set Vref, RX VrefLevel [Byte0]: 52
1660 23:45:04.349926 [Byte1]: 52
1661 23:45:04.354265
1662 23:45:04.354820 Set Vref, RX VrefLevel [Byte0]: 53
1663 23:45:04.358027 [Byte1]: 53
1664 23:45:04.361859
1665 23:45:04.362406 Set Vref, RX VrefLevel [Byte0]: 54
1666 23:45:04.365421 [Byte1]: 54
1667 23:45:04.369805
1668 23:45:04.370329 Set Vref, RX VrefLevel [Byte0]: 55
1669 23:45:04.372743 [Byte1]: 55
1670 23:45:04.377335
1671 23:45:04.377891 Set Vref, RX VrefLevel [Byte0]: 56
1672 23:45:04.380154 [Byte1]: 56
1673 23:45:04.384894
1674 23:45:04.385468 Set Vref, RX VrefLevel [Byte0]: 57
1675 23:45:04.388145 [Byte1]: 57
1676 23:45:04.392392
1677 23:45:04.393040 Set Vref, RX VrefLevel [Byte0]: 58
1678 23:45:04.395589 [Byte1]: 58
1679 23:45:04.400279
1680 23:45:04.400834 Set Vref, RX VrefLevel [Byte0]: 59
1681 23:45:04.403490 [Byte1]: 59
1682 23:45:04.407587
1683 23:45:04.408046 Set Vref, RX VrefLevel [Byte0]: 60
1684 23:45:04.410944 [Byte1]: 60
1685 23:45:04.415486
1686 23:45:04.416034 Set Vref, RX VrefLevel [Byte0]: 61
1687 23:45:04.418714 [Byte1]: 61
1688 23:45:04.423081
1689 23:45:04.423543 Set Vref, RX VrefLevel [Byte0]: 62
1690 23:45:04.426093 [Byte1]: 62
1691 23:45:04.430568
1692 23:45:04.431069 Set Vref, RX VrefLevel [Byte0]: 63
1693 23:45:04.434077 [Byte1]: 63
1694 23:45:04.438128
1695 23:45:04.438583 Set Vref, RX VrefLevel [Byte0]: 64
1696 23:45:04.441731 [Byte1]: 64
1697 23:45:04.446232
1698 23:45:04.446689 Set Vref, RX VrefLevel [Byte0]: 65
1699 23:45:04.448995 [Byte1]: 65
1700 23:45:04.453437
1701 23:45:04.453911 Set Vref, RX VrefLevel [Byte0]: 66
1702 23:45:04.456699 [Byte1]: 66
1703 23:45:04.460919
1704 23:45:04.461427 Set Vref, RX VrefLevel [Byte0]: 67
1705 23:45:04.464301 [Byte1]: 67
1706 23:45:04.468696
1707 23:45:04.469195 Set Vref, RX VrefLevel [Byte0]: 68
1708 23:45:04.471892 [Byte1]: 68
1709 23:45:04.476389
1710 23:45:04.476844 Set Vref, RX VrefLevel [Byte0]: 69
1711 23:45:04.480157 [Byte1]: 69
1712 23:45:04.484224
1713 23:45:04.484770 Set Vref, RX VrefLevel [Byte0]: 70
1714 23:45:04.487693 [Byte1]: 70
1715 23:45:04.491846
1716 23:45:04.492389 Set Vref, RX VrefLevel [Byte0]: 71
1717 23:45:04.494894 [Byte1]: 71
1718 23:45:04.499362
1719 23:45:04.499817 Set Vref, RX VrefLevel [Byte0]: 72
1720 23:45:04.502593 [Byte1]: 72
1721 23:45:04.507041
1722 23:45:04.507495 Set Vref, RX VrefLevel [Byte0]: 73
1723 23:45:04.510511 [Byte1]: 73
1724 23:45:04.514605
1725 23:45:04.515211 Set Vref, RX VrefLevel [Byte0]: 74
1726 23:45:04.518064 [Byte1]: 74
1727 23:45:04.522382
1728 23:45:04.522840 Set Vref, RX VrefLevel [Byte0]: 75
1729 23:45:04.525709 [Byte1]: 75
1730 23:45:04.529854
1731 23:45:04.530308 Set Vref, RX VrefLevel [Byte0]: 76
1732 23:45:04.533328 [Byte1]: 76
1733 23:45:04.537602
1734 23:45:04.538059 Set Vref, RX VrefLevel [Byte0]: 77
1735 23:45:04.540738 [Byte1]: 77
1736 23:45:04.545894
1737 23:45:04.546442 Set Vref, RX VrefLevel [Byte0]: 78
1738 23:45:04.548360 [Byte1]: 78
1739 23:45:04.553003
1740 23:45:04.553579 Final RX Vref Byte 0 = 59 to rank0
1741 23:45:04.556617 Final RX Vref Byte 1 = 51 to rank0
1742 23:45:04.559821 Final RX Vref Byte 0 = 59 to rank1
1743 23:45:04.563251 Final RX Vref Byte 1 = 51 to rank1==
1744 23:45:04.566460 Dram Type= 6, Freq= 0, CH_1, rank 0
1745 23:45:04.569816 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1746 23:45:04.573236 ==
1747 23:45:04.573733 DQS Delay:
1748 23:45:04.574092 DQS0 = 0, DQS1 = 0
1749 23:45:04.576436 DQM Delay:
1750 23:45:04.577065 DQM0 = 82, DQM1 = 75
1751 23:45:04.579953 DQ Delay:
1752 23:45:04.580402 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =80
1753 23:45:04.583082 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =80
1754 23:45:04.586889 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =64
1755 23:45:04.589658 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1756 23:45:04.590077
1757 23:45:04.593438
1758 23:45:04.600393 [DQSOSCAuto] RK0, (LSB)MR18= 0x5151, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1759 23:45:04.603569 CH1 RK0: MR19=606, MR18=5151
1760 23:45:04.609960 CH1_RK0: MR19=0x606, MR18=0x5151, DQSOSC=389, MR23=63, INC=97, DEC=65
1761 23:45:04.610492
1762 23:45:04.612904 ----->DramcWriteLeveling(PI) begin...
1763 23:45:04.613395 ==
1764 23:45:04.616663 Dram Type= 6, Freq= 0, CH_1, rank 1
1765 23:45:04.619663 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1766 23:45:04.620128 ==
1767 23:45:04.623272 Write leveling (Byte 0): 26 => 26
1768 23:45:04.626473 Write leveling (Byte 1): 23 => 23
1769 23:45:04.629906 DramcWriteLeveling(PI) end<-----
1770 23:45:04.630362
1771 23:45:04.630723 ==
1772 23:45:04.633514 Dram Type= 6, Freq= 0, CH_1, rank 1
1773 23:45:04.636562 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1774 23:45:04.637024 ==
1775 23:45:04.639670 [Gating] SW mode calibration
1776 23:45:04.646642 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1777 23:45:04.653540 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1778 23:45:04.656536 0 6 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (1 0)
1779 23:45:04.659901 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1780 23:45:04.666447 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1781 23:45:04.669612 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1782 23:45:04.673424 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1783 23:45:04.680062 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1784 23:45:04.683074 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1785 23:45:04.686416 0 6 28 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1786 23:45:04.690086 0 7 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
1787 23:45:04.696792 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1788 23:45:04.699924 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1789 23:45:04.703442 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1790 23:45:04.709952 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1791 23:45:04.713476 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1792 23:45:04.716579 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1793 23:45:04.722942 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1794 23:45:04.726204 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1795 23:45:04.730032 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 23:45:04.736687 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1797 23:45:04.740023 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1798 23:45:04.743310 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1799 23:45:04.749963 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1800 23:45:04.753579 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1801 23:45:04.756407 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1802 23:45:04.762948 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1803 23:45:04.766074 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1804 23:45:04.769668 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1805 23:45:04.776048 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1806 23:45:04.779322 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1807 23:45:04.782924 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1808 23:45:04.789139 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1809 23:45:04.792530 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1810 23:45:04.795847 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1811 23:45:04.799219 Total UI for P1: 0, mck2ui 16
1812 23:45:04.802410 best dqsien dly found for B0: ( 0, 9, 28)
1813 23:45:04.809079 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1814 23:45:04.809527 Total UI for P1: 0, mck2ui 16
1815 23:45:04.812506 best dqsien dly found for B1: ( 0, 9, 30)
1816 23:45:04.819014 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1817 23:45:04.822531 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1818 23:45:04.823000
1819 23:45:04.825610 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1820 23:45:04.829243 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1821 23:45:04.832641 [Gating] SW calibration Done
1822 23:45:04.833165 ==
1823 23:45:04.835752 Dram Type= 6, Freq= 0, CH_1, rank 1
1824 23:45:04.839040 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1825 23:45:04.839500 ==
1826 23:45:04.842516 RX Vref Scan: 0
1827 23:45:04.842970
1828 23:45:04.843325 RX Vref 0 -> 0, step: 1
1829 23:45:04.843660
1830 23:45:04.845791 RX Delay -130 -> 252, step: 16
1831 23:45:04.849608 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1832 23:45:04.855531 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1833 23:45:04.858891 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1834 23:45:04.862040 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1835 23:45:04.865474 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1836 23:45:04.869172 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1837 23:45:04.875258 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1838 23:45:04.878719 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1839 23:45:04.882271 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1840 23:45:04.885740 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1841 23:45:04.888723 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1842 23:45:04.895531 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1843 23:45:04.899083 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1844 23:45:04.902408 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1845 23:45:04.905634 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1846 23:45:04.908949 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1847 23:45:04.912486 ==
1848 23:45:04.915633 Dram Type= 6, Freq= 0, CH_1, rank 1
1849 23:45:04.919035 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1850 23:45:04.919541 ==
1851 23:45:04.919872 DQS Delay:
1852 23:45:04.922227 DQS0 = 0, DQS1 = 0
1853 23:45:04.922675 DQM Delay:
1854 23:45:04.925425 DQM0 = 85, DQM1 = 73
1855 23:45:04.925916 DQ Delay:
1856 23:45:04.928940 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1857 23:45:04.932185 DQ4 =85, DQ5 =101, DQ6 =85, DQ7 =85
1858 23:45:04.935816 DQ8 =53, DQ9 =61, DQ10 =69, DQ11 =61
1859 23:45:04.939037 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1860 23:45:04.939449
1861 23:45:04.939773
1862 23:45:04.940071 ==
1863 23:45:04.942688 Dram Type= 6, Freq= 0, CH_1, rank 1
1864 23:45:04.945807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1865 23:45:04.946223 ==
1866 23:45:04.946549
1867 23:45:04.946848
1868 23:45:04.949173 TX Vref Scan disable
1869 23:45:04.952299 == TX Byte 0 ==
1870 23:45:04.955535 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1871 23:45:04.958774 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1872 23:45:04.962139 == TX Byte 1 ==
1873 23:45:04.965388 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1874 23:45:04.968796 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1875 23:45:04.969311 ==
1876 23:45:04.972219 Dram Type= 6, Freq= 0, CH_1, rank 1
1877 23:45:04.975610 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1878 23:45:04.978543 ==
1879 23:45:04.990221 TX Vref=22, minBit 0, minWin=27, winSum=447
1880 23:45:04.993641 TX Vref=24, minBit 1, minWin=28, winSum=454
1881 23:45:04.997048 TX Vref=26, minBit 0, minWin=28, winSum=456
1882 23:45:05.000281 TX Vref=28, minBit 0, minWin=28, winSum=457
1883 23:45:05.003624 TX Vref=30, minBit 9, minWin=27, winSum=455
1884 23:45:05.010239 TX Vref=32, minBit 9, minWin=27, winSum=455
1885 23:45:05.013398 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 28
1886 23:45:05.013818
1887 23:45:05.016949 Final TX Range 1 Vref 28
1888 23:45:05.017406
1889 23:45:05.017745 ==
1890 23:45:05.020271 Dram Type= 6, Freq= 0, CH_1, rank 1
1891 23:45:05.023997 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1892 23:45:05.024418 ==
1893 23:45:05.024767
1894 23:45:05.027379
1895 23:45:05.027820 TX Vref Scan disable
1896 23:45:05.030386 == TX Byte 0 ==
1897 23:45:05.033725 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1898 23:45:05.037117 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1899 23:45:05.040651 == TX Byte 1 ==
1900 23:45:05.043875 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1901 23:45:05.047105 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1902 23:45:05.050209
1903 23:45:05.050703 [DATLAT]
1904 23:45:05.051066 Freq=800, CH1 RK1
1905 23:45:05.051405
1906 23:45:05.053488 DATLAT Default: 0x9
1907 23:45:05.053948 0, 0xFFFF, sum = 0
1908 23:45:05.056878 1, 0xFFFF, sum = 0
1909 23:45:05.057384 2, 0xFFFF, sum = 0
1910 23:45:05.060620 3, 0xFFFF, sum = 0
1911 23:45:05.063456 4, 0xFFFF, sum = 0
1912 23:45:05.063923 5, 0xFFFF, sum = 0
1913 23:45:05.066723 6, 0xFFFF, sum = 0
1914 23:45:05.067185 7, 0xFFFF, sum = 0
1915 23:45:05.070246 8, 0x0, sum = 1
1916 23:45:05.070706 9, 0x0, sum = 2
1917 23:45:05.071069 10, 0x0, sum = 3
1918 23:45:05.073419 11, 0x0, sum = 4
1919 23:45:05.073885 best_step = 9
1920 23:45:05.074285
1921 23:45:05.074767 ==
1922 23:45:05.076970 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 23:45:05.083398 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1924 23:45:05.083854 ==
1925 23:45:05.084206 RX Vref Scan: 0
1926 23:45:05.084570
1927 23:45:05.086816 RX Vref 0 -> 0, step: 1
1928 23:45:05.087257
1929 23:45:05.090171 RX Delay -111 -> 252, step: 8
1930 23:45:05.093452 iDelay=217, Bit 0, Center 88 (-23 ~ 200) 224
1931 23:45:05.096619 iDelay=217, Bit 1, Center 80 (-39 ~ 200) 240
1932 23:45:05.103315 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1933 23:45:05.106479 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1934 23:45:05.110002 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1935 23:45:05.113342 iDelay=217, Bit 5, Center 100 (-15 ~ 216) 232
1936 23:45:05.116502 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1937 23:45:05.123200 iDelay=217, Bit 7, Center 80 (-39 ~ 200) 240
1938 23:45:05.126619 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1939 23:45:05.129894 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1940 23:45:05.133380 iDelay=217, Bit 10, Center 72 (-47 ~ 192) 240
1941 23:45:05.136389 iDelay=217, Bit 11, Center 64 (-55 ~ 184) 240
1942 23:45:05.143368 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1943 23:45:05.146685 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1944 23:45:05.150434 iDelay=217, Bit 14, Center 80 (-39 ~ 200) 240
1945 23:45:05.153153 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1946 23:45:05.153645 ==
1947 23:45:05.156505 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 23:45:05.163056 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1949 23:45:05.163740 ==
1950 23:45:05.164145 DQS Delay:
1951 23:45:05.166454 DQS0 = 0, DQS1 = 0
1952 23:45:05.166904 DQM Delay:
1953 23:45:05.167264 DQM0 = 85, DQM1 = 73
1954 23:45:05.169804 DQ Delay:
1955 23:45:05.173394 DQ0 =88, DQ1 =80, DQ2 =76, DQ3 =84
1956 23:45:05.176900 DQ4 =84, DQ5 =100, DQ6 =92, DQ7 =80
1957 23:45:05.179563 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =64
1958 23:45:05.182933 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =80
1959 23:45:05.183393
1960 23:45:05.183753
1961 23:45:05.189740 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1962 23:45:05.192920 CH1 RK1: MR19=606, MR18=3F3F
1963 23:45:05.199775 CH1_RK1: MR19=0x606, MR18=0x3F3F, DQSOSC=393, MR23=63, INC=95, DEC=63
1964 23:45:05.203545 [RxdqsGatingPostProcess] freq 800
1965 23:45:05.206354 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1966 23:45:05.209777 Pre-setting of DQS Precalculation
1967 23:45:05.216421 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1968 23:45:05.223279 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1969 23:45:05.229701 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1970 23:45:05.230161
1971 23:45:05.230520
1972 23:45:05.233009 [Calibration Summary] 1600 Mbps
1973 23:45:05.233500 CH 0, Rank 0
1974 23:45:05.236089 SW Impedance : PASS
1975 23:45:05.239580 DUTY Scan : NO K
1976 23:45:05.240039 ZQ Calibration : PASS
1977 23:45:05.243139 Jitter Meter : NO K
1978 23:45:05.246247 CBT Training : PASS
1979 23:45:05.246707 Write leveling : PASS
1980 23:45:05.249857 RX DQS gating : PASS
1981 23:45:05.252986 RX DQ/DQS(RDDQC) : PASS
1982 23:45:05.253492 TX DQ/DQS : PASS
1983 23:45:05.256517 RX DATLAT : PASS
1984 23:45:05.256970 RX DQ/DQS(Engine): PASS
1985 23:45:05.259805 TX OE : NO K
1986 23:45:05.260221 All Pass.
1987 23:45:05.260693
1988 23:45:05.263135 CH 0, Rank 1
1989 23:45:05.263551 SW Impedance : PASS
1990 23:45:05.265765 DUTY Scan : NO K
1991 23:45:05.269029 ZQ Calibration : PASS
1992 23:45:05.269109 Jitter Meter : NO K
1993 23:45:05.272326 CBT Training : PASS
1994 23:45:05.275759 Write leveling : PASS
1995 23:45:05.275840 RX DQS gating : PASS
1996 23:45:05.279061 RX DQ/DQS(RDDQC) : PASS
1997 23:45:05.282721 TX DQ/DQS : PASS
1998 23:45:05.282802 RX DATLAT : PASS
1999 23:45:05.286272 RX DQ/DQS(Engine): PASS
2000 23:45:05.289497 TX OE : NO K
2001 23:45:05.289578 All Pass.
2002 23:45:05.289642
2003 23:45:05.289709 CH 1, Rank 0
2004 23:45:05.292592 SW Impedance : PASS
2005 23:45:05.296603 DUTY Scan : NO K
2006 23:45:05.296774 ZQ Calibration : PASS
2007 23:45:05.299248 Jitter Meter : NO K
2008 23:45:05.299418 CBT Training : PASS
2009 23:45:05.302657 Write leveling : PASS
2010 23:45:05.306097 RX DQS gating : PASS
2011 23:45:05.306284 RX DQ/DQS(RDDQC) : PASS
2012 23:45:05.309575 TX DQ/DQS : PASS
2013 23:45:05.313208 RX DATLAT : PASS
2014 23:45:05.313424 RX DQ/DQS(Engine): PASS
2015 23:45:05.316080 TX OE : NO K
2016 23:45:05.316292 All Pass.
2017 23:45:05.316409
2018 23:45:05.319450 CH 1, Rank 1
2019 23:45:05.319666 SW Impedance : PASS
2020 23:45:05.322734 DUTY Scan : NO K
2021 23:45:05.326018 ZQ Calibration : PASS
2022 23:45:05.326235 Jitter Meter : NO K
2023 23:45:05.329383 CBT Training : PASS
2024 23:45:05.332703 Write leveling : PASS
2025 23:45:05.332902 RX DQS gating : PASS
2026 23:45:05.336021 RX DQ/DQS(RDDQC) : PASS
2027 23:45:05.339483 TX DQ/DQS : PASS
2028 23:45:05.339783 RX DATLAT : PASS
2029 23:45:05.342816 RX DQ/DQS(Engine): PASS
2030 23:45:05.343224 TX OE : NO K
2031 23:45:05.346053 All Pass.
2032 23:45:05.346466
2033 23:45:05.346807 DramC Write-DBI off
2034 23:45:05.349328 PER_BANK_REFRESH: Hybrid Mode
2035 23:45:05.353093 TX_TRACKING: ON
2036 23:45:05.356214 [GetDramInforAfterCalByMRR] Vendor 6.
2037 23:45:05.359506 [GetDramInforAfterCalByMRR] Revision 606.
2038 23:45:05.362896 [GetDramInforAfterCalByMRR] Revision 2 0.
2039 23:45:05.363346 MR0 0x3939
2040 23:45:05.363697 MR8 0x1111
2041 23:45:05.369364 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2042 23:45:05.369832
2043 23:45:05.370212 MR0 0x3939
2044 23:45:05.370550 MR8 0x1111
2045 23:45:05.373037 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2046 23:45:05.373539
2047 23:45:05.382840 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2048 23:45:05.386604 [FAST_K] Save calibration result to emmc
2049 23:45:05.389691 [FAST_K] Save calibration result to emmc
2050 23:45:05.392999 dram_init: config_dvfs: 1
2051 23:45:05.396461 dramc_set_vcore_voltage set vcore to 662500
2052 23:45:05.400089 Read voltage for 1200, 2
2053 23:45:05.400642 Vio18 = 0
2054 23:45:05.401001 Vcore = 662500
2055 23:45:05.403262 Vdram = 0
2056 23:45:05.403808 Vddq = 0
2057 23:45:05.404169 Vmddr = 0
2058 23:45:05.409933 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2059 23:45:05.412924 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2060 23:45:05.416498 MEM_TYPE=3, freq_sel=15
2061 23:45:05.419921 sv_algorithm_assistance_LP4_1600
2062 23:45:05.422777 ============ PULL DRAM RESETB DOWN ============
2063 23:45:05.426536 ========== PULL DRAM RESETB DOWN end =========
2064 23:45:05.432855 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2065 23:45:05.436201 ===================================
2066 23:45:05.439729 LPDDR4 DRAM CONFIGURATION
2067 23:45:05.442953 ===================================
2068 23:45:05.443409 EX_ROW_EN[0] = 0x0
2069 23:45:05.446337 EX_ROW_EN[1] = 0x0
2070 23:45:05.446790 LP4Y_EN = 0x0
2071 23:45:05.449404 WORK_FSP = 0x0
2072 23:45:05.449887 WL = 0x4
2073 23:45:05.453017 RL = 0x4
2074 23:45:05.453583 BL = 0x2
2075 23:45:05.456269 RPST = 0x0
2076 23:45:05.456747 RD_PRE = 0x0
2077 23:45:05.459292 WR_PRE = 0x1
2078 23:45:05.459759 WR_PST = 0x0
2079 23:45:05.462634 DBI_WR = 0x0
2080 23:45:05.463113 DBI_RD = 0x0
2081 23:45:05.466082 OTF = 0x1
2082 23:45:05.469357 ===================================
2083 23:45:05.472788 ===================================
2084 23:45:05.473352 ANA top config
2085 23:45:05.475927 ===================================
2086 23:45:05.479382 DLL_ASYNC_EN = 0
2087 23:45:05.482828 ALL_SLAVE_EN = 0
2088 23:45:05.486378 NEW_RANK_MODE = 1
2089 23:45:05.486937 DLL_IDLE_MODE = 1
2090 23:45:05.489683 LP45_APHY_COMB_EN = 1
2091 23:45:05.492906 TX_ODT_DIS = 1
2092 23:45:05.496471 NEW_8X_MODE = 1
2093 23:45:05.499516 ===================================
2094 23:45:05.503069 ===================================
2095 23:45:05.506482 data_rate = 2400
2096 23:45:05.507046 CKR = 1
2097 23:45:05.509656 DQ_P2S_RATIO = 8
2098 23:45:05.512907 ===================================
2099 23:45:05.516453 CA_P2S_RATIO = 8
2100 23:45:05.519861 DQ_CA_OPEN = 0
2101 23:45:05.522817 DQ_SEMI_OPEN = 0
2102 23:45:05.525912 CA_SEMI_OPEN = 0
2103 23:45:05.526364 CA_FULL_RATE = 0
2104 23:45:05.529936 DQ_CKDIV4_EN = 0
2105 23:45:05.532911 CA_CKDIV4_EN = 0
2106 23:45:05.536431 CA_PREDIV_EN = 0
2107 23:45:05.539845 PH8_DLY = 17
2108 23:45:05.542773 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2109 23:45:05.543245 DQ_AAMCK_DIV = 4
2110 23:45:05.546189 CA_AAMCK_DIV = 4
2111 23:45:05.549570 CA_ADMCK_DIV = 4
2112 23:45:05.552629 DQ_TRACK_CA_EN = 0
2113 23:45:05.555944 CA_PICK = 1200
2114 23:45:05.559247 CA_MCKIO = 1200
2115 23:45:05.559706 MCKIO_SEMI = 0
2116 23:45:05.562907 PLL_FREQ = 2366
2117 23:45:05.566246 DQ_UI_PI_RATIO = 32
2118 23:45:05.569596 CA_UI_PI_RATIO = 0
2119 23:45:05.573104 ===================================
2120 23:45:05.576114 ===================================
2121 23:45:05.579390 memory_type:LPDDR4
2122 23:45:05.579848 GP_NUM : 10
2123 23:45:05.582852 SRAM_EN : 1
2124 23:45:05.586460 MD32_EN : 0
2125 23:45:05.589600 ===================================
2126 23:45:05.590061 [ANA_INIT] >>>>>>>>>>>>>>
2127 23:45:05.593059 <<<<<< [CONFIGURE PHASE]: ANA_TX
2128 23:45:05.596418 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2129 23:45:05.599465 ===================================
2130 23:45:05.602792 data_rate = 2400,PCW = 0X5b00
2131 23:45:05.606079 ===================================
2132 23:45:05.609358 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2133 23:45:05.616181 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2134 23:45:05.619889 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2135 23:45:05.626178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2136 23:45:05.629563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2137 23:45:05.633151 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2138 23:45:05.633676 [ANA_INIT] flow start
2139 23:45:05.636451 [ANA_INIT] PLL >>>>>>>>
2140 23:45:05.639350 [ANA_INIT] PLL <<<<<<<<
2141 23:45:05.639897 [ANA_INIT] MIDPI >>>>>>>>
2142 23:45:05.642790 [ANA_INIT] MIDPI <<<<<<<<
2143 23:45:05.645986 [ANA_INIT] DLL >>>>>>>>
2144 23:45:05.649444 [ANA_INIT] DLL <<<<<<<<
2145 23:45:05.649903 [ANA_INIT] flow end
2146 23:45:05.652812 ============ LP4 DIFF to SE enter ============
2147 23:45:05.659511 ============ LP4 DIFF to SE exit ============
2148 23:45:05.659928 [ANA_INIT] <<<<<<<<<<<<<
2149 23:45:05.662808 [Flow] Enable top DCM control >>>>>
2150 23:45:05.665904 [Flow] Enable top DCM control <<<<<
2151 23:45:05.669202 Enable DLL master slave shuffle
2152 23:45:05.676023 ==============================================================
2153 23:45:05.676441 Gating Mode config
2154 23:45:05.682521 ==============================================================
2155 23:45:05.686006 Config description:
2156 23:45:05.692505 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2157 23:45:05.699462 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2158 23:45:05.705953 SELPH_MODE 0: By rank 1: By Phase
2159 23:45:05.712452 ==============================================================
2160 23:45:05.712868 GAT_TRACK_EN = 1
2161 23:45:05.715799 RX_GATING_MODE = 2
2162 23:45:05.719529 RX_GATING_TRACK_MODE = 2
2163 23:45:05.722598 SELPH_MODE = 1
2164 23:45:05.726098 PICG_EARLY_EN = 1
2165 23:45:05.729099 VALID_LAT_VALUE = 1
2166 23:45:05.735874 ==============================================================
2167 23:45:05.739518 Enter into Gating configuration >>>>
2168 23:45:05.743005 Exit from Gating configuration <<<<
2169 23:45:05.745819 Enter into DVFS_PRE_config >>>>>
2170 23:45:05.755862 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2171 23:45:05.759125 Exit from DVFS_PRE_config <<<<<
2172 23:45:05.762774 Enter into PICG configuration >>>>
2173 23:45:05.766055 Exit from PICG configuration <<<<
2174 23:45:05.769206 [RX_INPUT] configuration >>>>>
2175 23:45:05.769624 [RX_INPUT] configuration <<<<<
2176 23:45:05.775901 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2177 23:45:05.782729 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2178 23:45:05.786083 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2179 23:45:05.792673 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2180 23:45:05.799078 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2181 23:45:05.805914 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2182 23:45:05.809650 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2183 23:45:05.812895 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2184 23:45:05.819217 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2185 23:45:05.822473 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2186 23:45:05.825760 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2187 23:45:05.829211 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2188 23:45:05.832418 ===================================
2189 23:45:05.836088 LPDDR4 DRAM CONFIGURATION
2190 23:45:05.838995 ===================================
2191 23:45:05.842290 EX_ROW_EN[0] = 0x0
2192 23:45:05.842762 EX_ROW_EN[1] = 0x0
2193 23:45:05.845900 LP4Y_EN = 0x0
2194 23:45:05.846378 WORK_FSP = 0x0
2195 23:45:05.849103 WL = 0x4
2196 23:45:05.849621 RL = 0x4
2197 23:45:05.852507 BL = 0x2
2198 23:45:05.852913 RPST = 0x0
2199 23:45:05.855884 RD_PRE = 0x0
2200 23:45:05.856293 WR_PRE = 0x1
2201 23:45:05.859120 WR_PST = 0x0
2202 23:45:05.859529 DBI_WR = 0x0
2203 23:45:05.862630 DBI_RD = 0x0
2204 23:45:05.865875 OTF = 0x1
2205 23:45:05.869197 ===================================
2206 23:45:05.872863 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2207 23:45:05.876009 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2208 23:45:05.879402 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2209 23:45:05.882969 ===================================
2210 23:45:05.886142 LPDDR4 DRAM CONFIGURATION
2211 23:45:05.889740 ===================================
2212 23:45:05.892664 EX_ROW_EN[0] = 0x10
2213 23:45:05.893073 EX_ROW_EN[1] = 0x0
2214 23:45:05.896141 LP4Y_EN = 0x0
2215 23:45:05.896742 WORK_FSP = 0x0
2216 23:45:05.899697 WL = 0x4
2217 23:45:05.900204 RL = 0x4
2218 23:45:05.902494 BL = 0x2
2219 23:45:05.903005 RPST = 0x0
2220 23:45:05.905896 RD_PRE = 0x0
2221 23:45:05.906407 WR_PRE = 0x1
2222 23:45:05.909603 WR_PST = 0x0
2223 23:45:05.910012 DBI_WR = 0x0
2224 23:45:05.912495 DBI_RD = 0x0
2225 23:45:05.912900 OTF = 0x1
2226 23:45:05.916039 ===================================
2227 23:45:05.922555 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2228 23:45:05.923061 ==
2229 23:45:05.925853 Dram Type= 6, Freq= 0, CH_0, rank 0
2230 23:45:05.929140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2231 23:45:05.932635 ==
2232 23:45:05.933050 [Duty_Offset_Calibration]
2233 23:45:05.935889 B0:0 B1:2 CA:1
2234 23:45:05.936300
2235 23:45:05.938996 [DutyScan_Calibration_Flow] k_type=0
2236 23:45:05.947785
2237 23:45:05.948239 ==CLK 0==
2238 23:45:05.951378 Final CLK duty delay cell = 0
2239 23:45:05.954627 [0] MAX Duty = 5093%(X100), DQS PI = 12
2240 23:45:05.957919 [0] MIN Duty = 4938%(X100), DQS PI = 52
2241 23:45:05.958336 [0] AVG Duty = 5015%(X100)
2242 23:45:05.961268
2243 23:45:05.964941 CH0 CLK Duty spec in!! Max-Min= 155%
2244 23:45:05.967657 [DutyScan_Calibration_Flow] ====Done====
2245 23:45:05.968125
2246 23:45:05.970880 [DutyScan_Calibration_Flow] k_type=1
2247 23:45:05.987343
2248 23:45:05.987969 ==DQS 0 ==
2249 23:45:05.990821 Final DQS duty delay cell = 0
2250 23:45:05.993835 [0] MAX Duty = 5124%(X100), DQS PI = 50
2251 23:45:05.997698 [0] MIN Duty = 5000%(X100), DQS PI = 6
2252 23:45:05.998263 [0] AVG Duty = 5062%(X100)
2253 23:45:06.000698
2254 23:45:06.001249 ==DQS 1 ==
2255 23:45:06.004058 Final DQS duty delay cell = 0
2256 23:45:06.007694 [0] MAX Duty = 5031%(X100), DQS PI = 52
2257 23:45:06.010595 [0] MIN Duty = 4906%(X100), DQS PI = 16
2258 23:45:06.011156 [0] AVG Duty = 4968%(X100)
2259 23:45:06.013757
2260 23:45:06.017080 CH0 DQS 0 Duty spec in!! Max-Min= 124%
2261 23:45:06.017601
2262 23:45:06.021023 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2263 23:45:06.023968 [DutyScan_Calibration_Flow] ====Done====
2264 23:45:06.024415
2265 23:45:06.026939 [DutyScan_Calibration_Flow] k_type=3
2266 23:45:06.044859
2267 23:45:06.045506 ==DQM 0 ==
2268 23:45:06.047704 Final DQM duty delay cell = 0
2269 23:45:06.051225 [0] MAX Duty = 5156%(X100), DQS PI = 20
2270 23:45:06.054497 [0] MIN Duty = 4969%(X100), DQS PI = 40
2271 23:45:06.054952 [0] AVG Duty = 5062%(X100)
2272 23:45:06.057860
2273 23:45:06.058308 ==DQM 1 ==
2274 23:45:06.061045 Final DQM duty delay cell = 4
2275 23:45:06.064502 [4] MAX Duty = 5187%(X100), DQS PI = 54
2276 23:45:06.067584 [4] MIN Duty = 5000%(X100), DQS PI = 18
2277 23:45:06.070807 [4] AVG Duty = 5093%(X100)
2278 23:45:06.071257
2279 23:45:06.074319 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2280 23:45:06.074771
2281 23:45:06.077931 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2282 23:45:06.081087 [DutyScan_Calibration_Flow] ====Done====
2283 23:45:06.081668
2284 23:45:06.084092 [DutyScan_Calibration_Flow] k_type=2
2285 23:45:06.099386
2286 23:45:06.099903 ==DQ 0 ==
2287 23:45:06.102654 Final DQ duty delay cell = -4
2288 23:45:06.105984 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2289 23:45:06.109499 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2290 23:45:06.112662 [-4] AVG Duty = 4937%(X100)
2291 23:45:06.113184
2292 23:45:06.113638 ==DQ 1 ==
2293 23:45:06.116129 Final DQ duty delay cell = -4
2294 23:45:06.119257 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2295 23:45:06.122847 [-4] MIN Duty = 4876%(X100), DQS PI = 62
2296 23:45:06.125957 [-4] AVG Duty = 4969%(X100)
2297 23:45:06.126406
2298 23:45:06.129649 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2299 23:45:06.130427
2300 23:45:06.132634 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2301 23:45:06.135945 [DutyScan_Calibration_Flow] ====Done====
2302 23:45:06.136472 ==
2303 23:45:06.139782 Dram Type= 6, Freq= 0, CH_1, rank 0
2304 23:45:06.142933 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2305 23:45:06.143411 ==
2306 23:45:06.145973 [Duty_Offset_Calibration]
2307 23:45:06.146477 B0:0 B1:5 CA:-5
2308 23:45:06.146847
2309 23:45:06.149125 [DutyScan_Calibration_Flow] k_type=0
2310 23:45:06.159946
2311 23:45:06.160514 ==CLK 0==
2312 23:45:06.163507 Final CLK duty delay cell = 0
2313 23:45:06.166896 [0] MAX Duty = 5094%(X100), DQS PI = 24
2314 23:45:06.169797 [0] MIN Duty = 4844%(X100), DQS PI = 46
2315 23:45:06.170270 [0] AVG Duty = 4969%(X100)
2316 23:45:06.173421
2317 23:45:06.176716 CH1 CLK Duty spec in!! Max-Min= 250%
2318 23:45:06.179741 [DutyScan_Calibration_Flow] ====Done====
2319 23:45:06.180203
2320 23:45:06.183052 [DutyScan_Calibration_Flow] k_type=1
2321 23:45:06.198612
2322 23:45:06.199143 ==DQS 0 ==
2323 23:45:06.201888 Final DQS duty delay cell = 0
2324 23:45:06.205516 [0] MAX Duty = 5125%(X100), DQS PI = 16
2325 23:45:06.208876 [0] MIN Duty = 4875%(X100), DQS PI = 40
2326 23:45:06.211814 [0] AVG Duty = 5000%(X100)
2327 23:45:06.212268
2328 23:45:06.212622 ==DQS 1 ==
2329 23:45:06.215105 Final DQS duty delay cell = -4
2330 23:45:06.218481 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2331 23:45:06.221881 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2332 23:45:06.225528 [-4] AVG Duty = 4953%(X100)
2333 23:45:06.225985
2334 23:45:06.228674 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2335 23:45:06.229131
2336 23:45:06.231921 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2337 23:45:06.235128 [DutyScan_Calibration_Flow] ====Done====
2338 23:45:06.235591
2339 23:45:06.238411 [DutyScan_Calibration_Flow] k_type=3
2340 23:45:06.253788
2341 23:45:06.254203 ==DQM 0 ==
2342 23:45:06.257056 Final DQM duty delay cell = -4
2343 23:45:06.260324 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2344 23:45:06.263989 [-4] MIN Duty = 4844%(X100), DQS PI = 38
2345 23:45:06.266956 [-4] AVG Duty = 4953%(X100)
2346 23:45:06.267374
2347 23:45:06.267759 ==DQM 1 ==
2348 23:45:06.270254 Final DQM duty delay cell = -4
2349 23:45:06.273831 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2350 23:45:06.277195 [-4] MIN Duty = 4906%(X100), DQS PI = 42
2351 23:45:06.280354 [-4] AVG Duty = 4984%(X100)
2352 23:45:06.280767
2353 23:45:06.283816 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2354 23:45:06.284324
2355 23:45:06.287439 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2356 23:45:06.290554 [DutyScan_Calibration_Flow] ====Done====
2357 23:45:06.291073
2358 23:45:06.294220 [DutyScan_Calibration_Flow] k_type=2
2359 23:45:06.310534
2360 23:45:06.310946 ==DQ 0 ==
2361 23:45:06.314142 Final DQ duty delay cell = 0
2362 23:45:06.317410 [0] MAX Duty = 5062%(X100), DQS PI = 0
2363 23:45:06.321156 [0] MIN Duty = 4969%(X100), DQS PI = 44
2364 23:45:06.321680 [0] AVG Duty = 5015%(X100)
2365 23:45:06.322005
2366 23:45:06.324545 ==DQ 1 ==
2367 23:45:06.327518 Final DQ duty delay cell = 0
2368 23:45:06.330670 [0] MAX Duty = 5000%(X100), DQS PI = 6
2369 23:45:06.334311 [0] MIN Duty = 4875%(X100), DQS PI = 44
2370 23:45:06.334714 [0] AVG Duty = 4937%(X100)
2371 23:45:06.335032
2372 23:45:06.337507 CH1 DQ 0 Duty spec in!! Max-Min= 93%
2373 23:45:06.337974
2374 23:45:06.341048 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2375 23:45:06.344412 [DutyScan_Calibration_Flow] ====Done====
2376 23:45:06.349677 nWR fixed to 30
2377 23:45:06.352975 [ModeRegInit_LP4] CH0 RK0
2378 23:45:06.353485 [ModeRegInit_LP4] CH0 RK1
2379 23:45:06.356342 [ModeRegInit_LP4] CH1 RK0
2380 23:45:06.359713 [ModeRegInit_LP4] CH1 RK1
2381 23:45:06.360192 match AC timing 6
2382 23:45:06.366258 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2383 23:45:06.369517 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2384 23:45:06.372800 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2385 23:45:06.379752 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2386 23:45:06.382870 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2387 23:45:06.383378 ==
2388 23:45:06.386094 Dram Type= 6, Freq= 0, CH_0, rank 0
2389 23:45:06.389223 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2390 23:45:06.389669 ==
2391 23:45:06.396186 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2392 23:45:06.402835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2393 23:45:06.410627 [CA 0] Center 39 (9~70) winsize 62
2394 23:45:06.413818 [CA 1] Center 39 (8~70) winsize 63
2395 23:45:06.416994 [CA 2] Center 36 (5~67) winsize 63
2396 23:45:06.420345 [CA 3] Center 35 (4~66) winsize 63
2397 23:45:06.423741 [CA 4] Center 34 (3~65) winsize 63
2398 23:45:06.427134 [CA 5] Center 33 (3~64) winsize 62
2399 23:45:06.427560
2400 23:45:06.430379 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2401 23:45:06.430783
2402 23:45:06.433897 [CATrainingPosCal] consider 1 rank data
2403 23:45:06.437017 u2DelayCellTimex100 = 270/100 ps
2404 23:45:06.440464 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2405 23:45:06.443644 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2406 23:45:06.450431 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2407 23:45:06.453923 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2408 23:45:06.457524 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2409 23:45:06.460720 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2410 23:45:06.461277
2411 23:45:06.464221 CA PerBit enable=1, Macro0, CA PI delay=33
2412 23:45:06.464778
2413 23:45:06.467177 [CBTSetCACLKResult] CA Dly = 33
2414 23:45:06.467631 CS Dly: 7 (0~38)
2415 23:45:06.468028 ==
2416 23:45:06.470525 Dram Type= 6, Freq= 0, CH_0, rank 1
2417 23:45:06.477083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2418 23:45:06.477573 ==
2419 23:45:06.480328 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2420 23:45:06.487113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2421 23:45:06.495996 [CA 0] Center 39 (8~70) winsize 63
2422 23:45:06.499236 [CA 1] Center 39 (8~70) winsize 63
2423 23:45:06.502650 [CA 2] Center 36 (5~67) winsize 63
2424 23:45:06.505817 [CA 3] Center 35 (4~66) winsize 63
2425 23:45:06.509256 [CA 4] Center 33 (3~64) winsize 62
2426 23:45:06.512603 [CA 5] Center 34 (3~65) winsize 63
2427 23:45:06.513063
2428 23:45:06.516260 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2429 23:45:06.516811
2430 23:45:06.519309 [CATrainingPosCal] consider 2 rank data
2431 23:45:06.522647 u2DelayCellTimex100 = 270/100 ps
2432 23:45:06.525830 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2433 23:45:06.529431 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2434 23:45:06.535706 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2435 23:45:06.539084 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2436 23:45:06.542441 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2437 23:45:06.546151 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2438 23:45:06.546608
2439 23:45:06.549473 CA PerBit enable=1, Macro0, CA PI delay=33
2440 23:45:06.549935
2441 23:45:06.552594 [CBTSetCACLKResult] CA Dly = 33
2442 23:45:06.553049 CS Dly: 7 (0~39)
2443 23:45:06.553453
2444 23:45:06.555985 ----->DramcWriteLeveling(PI) begin...
2445 23:45:06.559024 ==
2446 23:45:06.562611 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 23:45:06.566141 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2448 23:45:06.566604 ==
2449 23:45:06.569362 Write leveling (Byte 0): 27 => 27
2450 23:45:06.572257 Write leveling (Byte 1): 25 => 25
2451 23:45:06.575542 DramcWriteLeveling(PI) end<-----
2452 23:45:06.575997
2453 23:45:06.576354 ==
2454 23:45:06.579271 Dram Type= 6, Freq= 0, CH_0, rank 0
2455 23:45:06.582189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2456 23:45:06.582652 ==
2457 23:45:06.585644 [Gating] SW mode calibration
2458 23:45:06.592610 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2459 23:45:06.595891 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2460 23:45:06.602249 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2461 23:45:06.606069 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2462 23:45:06.609081 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2463 23:45:06.615730 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2464 23:45:06.618877 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2465 23:45:06.622752 0 11 20 | B1->B0 | 2f2f 2c2c | 1 0 | (1 0) (1 0)
2466 23:45:06.629196 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2467 23:45:06.632440 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2468 23:45:06.635612 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2469 23:45:06.642364 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2470 23:45:06.645596 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2471 23:45:06.649467 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2472 23:45:06.655810 0 12 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2473 23:45:06.658914 0 12 20 | B1->B0 | 3b3b 3f3f | 0 1 | (0 0) (0 0)
2474 23:45:06.662511 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2475 23:45:06.669674 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2476 23:45:06.672211 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2477 23:45:06.675768 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2478 23:45:06.682690 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2479 23:45:06.685594 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2480 23:45:06.689122 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2481 23:45:06.692734 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2482 23:45:06.699105 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 23:45:06.702270 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2484 23:45:06.705670 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2485 23:45:06.712658 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2486 23:45:06.716015 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2487 23:45:06.719034 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2488 23:45:06.725798 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2489 23:45:06.729483 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2490 23:45:06.732400 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2491 23:45:06.739307 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2492 23:45:06.742357 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2493 23:45:06.745671 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2494 23:45:06.752049 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2495 23:45:06.756008 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2496 23:45:06.759249 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2497 23:45:06.765634 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2498 23:45:06.768931 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2499 23:45:06.772281 Total UI for P1: 0, mck2ui 16
2500 23:45:06.775578 best dqsien dly found for B0: ( 0, 15, 20)
2501 23:45:06.778883 Total UI for P1: 0, mck2ui 16
2502 23:45:06.782371 best dqsien dly found for B1: ( 0, 15, 20)
2503 23:45:06.785763 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2504 23:45:06.789010 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2505 23:45:06.789534
2506 23:45:06.792301 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2507 23:45:06.795455 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2508 23:45:06.799419 [Gating] SW calibration Done
2509 23:45:06.799839 ==
2510 23:45:06.802222 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 23:45:06.805412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2512 23:45:06.805834 ==
2513 23:45:06.809026 RX Vref Scan: 0
2514 23:45:06.809474
2515 23:45:06.812181 RX Vref 0 -> 0, step: 1
2516 23:45:06.812726
2517 23:45:06.813195 RX Delay -40 -> 252, step: 8
2518 23:45:06.819097 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2519 23:45:06.822409 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2520 23:45:06.825934 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2521 23:45:06.828982 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2522 23:45:06.832360 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2523 23:45:06.839193 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2524 23:45:06.842164 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2525 23:45:06.845477 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2526 23:45:06.849011 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2527 23:45:06.852325 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2528 23:45:06.858779 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2529 23:45:06.862741 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2530 23:45:06.865700 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2531 23:45:06.868773 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2532 23:45:06.872166 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2533 23:45:06.878836 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2534 23:45:06.879282 ==
2535 23:45:06.882293 Dram Type= 6, Freq= 0, CH_0, rank 0
2536 23:45:06.885752 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2537 23:45:06.886165 ==
2538 23:45:06.886488 DQS Delay:
2539 23:45:06.888902 DQS0 = 0, DQS1 = 0
2540 23:45:06.889346 DQM Delay:
2541 23:45:06.892242 DQM0 = 115, DQM1 = 106
2542 23:45:06.892348 DQ Delay:
2543 23:45:06.895191 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2544 23:45:06.898626 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2545 23:45:06.901722 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2546 23:45:06.905228 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2547 23:45:06.905344
2548 23:45:06.905408
2549 23:45:06.908745 ==
2550 23:45:06.911925 Dram Type= 6, Freq= 0, CH_0, rank 0
2551 23:45:06.915181 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2552 23:45:06.915262 ==
2553 23:45:06.915324
2554 23:45:06.915381
2555 23:45:06.918235 TX Vref Scan disable
2556 23:45:06.918314 == TX Byte 0 ==
2557 23:45:06.921743 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2558 23:45:06.928629 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2559 23:45:06.928712 == TX Byte 1 ==
2560 23:45:06.931519 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2561 23:45:06.938379 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2562 23:45:06.938460 ==
2563 23:45:06.941754 Dram Type= 6, Freq= 0, CH_0, rank 0
2564 23:45:06.945037 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2565 23:45:06.945144 ==
2566 23:45:06.957321 TX Vref=22, minBit 8, minWin=25, winSum=413
2567 23:45:06.960616 TX Vref=24, minBit 9, minWin=25, winSum=418
2568 23:45:06.963906 TX Vref=26, minBit 9, minWin=25, winSum=425
2569 23:45:06.966932 TX Vref=28, minBit 15, minWin=25, winSum=428
2570 23:45:06.970294 TX Vref=30, minBit 8, minWin=26, winSum=430
2571 23:45:06.977582 TX Vref=32, minBit 8, minWin=26, winSum=430
2572 23:45:06.980125 [TxChooseVref] Worse bit 8, Min win 26, Win sum 430, Final Vref 30
2573 23:45:06.980206
2574 23:45:06.983641 Final TX Range 1 Vref 30
2575 23:45:06.983722
2576 23:45:06.983785 ==
2577 23:45:06.987006 Dram Type= 6, Freq= 0, CH_0, rank 0
2578 23:45:06.990434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2579 23:45:06.990515 ==
2580 23:45:06.993870
2581 23:45:06.993950
2582 23:45:06.994012 TX Vref Scan disable
2583 23:45:06.996887 == TX Byte 0 ==
2584 23:45:07.000462 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2585 23:45:07.003960 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2586 23:45:07.007251 == TX Byte 1 ==
2587 23:45:07.010373 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
2588 23:45:07.013650 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
2589 23:45:07.013757
2590 23:45:07.017113 [DATLAT]
2591 23:45:07.017219 Freq=1200, CH0 RK0
2592 23:45:07.017312
2593 23:45:07.020234 DATLAT Default: 0xd
2594 23:45:07.020314 0, 0xFFFF, sum = 0
2595 23:45:07.023637 1, 0xFFFF, sum = 0
2596 23:45:07.023720 2, 0xFFFF, sum = 0
2597 23:45:07.026886 3, 0xFFFF, sum = 0
2598 23:45:07.026968 4, 0xFFFF, sum = 0
2599 23:45:07.030097 5, 0xFFFF, sum = 0
2600 23:45:07.030179 6, 0xFFFF, sum = 0
2601 23:45:07.033693 7, 0xFFFF, sum = 0
2602 23:45:07.033801 8, 0xFFFF, sum = 0
2603 23:45:07.037074 9, 0xFFFF, sum = 0
2604 23:45:07.040116 10, 0xFFFF, sum = 0
2605 23:45:07.040198 11, 0x0, sum = 1
2606 23:45:07.043736 12, 0x0, sum = 2
2607 23:45:07.043818 13, 0x0, sum = 3
2608 23:45:07.043883 14, 0x0, sum = 4
2609 23:45:07.047355 best_step = 12
2610 23:45:07.047435
2611 23:45:07.047499 ==
2612 23:45:07.050470 Dram Type= 6, Freq= 0, CH_0, rank 0
2613 23:45:07.053637 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2614 23:45:07.053801 ==
2615 23:45:07.057097 RX Vref Scan: 1
2616 23:45:07.057302
2617 23:45:07.060431 Set Vref Range= 32 -> 127
2618 23:45:07.060582
2619 23:45:07.060677 RX Vref 32 -> 127, step: 1
2620 23:45:07.060760
2621 23:45:07.063827 RX Delay -21 -> 252, step: 4
2622 23:45:07.064007
2623 23:45:07.067146 Set Vref, RX VrefLevel [Byte0]: 32
2624 23:45:07.070417 [Byte1]: 32
2625 23:45:07.073664
2626 23:45:07.073858 Set Vref, RX VrefLevel [Byte0]: 33
2627 23:45:07.077038 [Byte1]: 33
2628 23:45:07.081424
2629 23:45:07.081575 Set Vref, RX VrefLevel [Byte0]: 34
2630 23:45:07.084717 [Byte1]: 34
2631 23:45:07.089332
2632 23:45:07.089505 Set Vref, RX VrefLevel [Byte0]: 35
2633 23:45:07.092770 [Byte1]: 35
2634 23:45:07.097374
2635 23:45:07.097611 Set Vref, RX VrefLevel [Byte0]: 36
2636 23:45:07.100833 [Byte1]: 36
2637 23:45:07.105726
2638 23:45:07.106111 Set Vref, RX VrefLevel [Byte0]: 37
2639 23:45:07.108939 [Byte1]: 37
2640 23:45:07.113503
2641 23:45:07.113958 Set Vref, RX VrefLevel [Byte0]: 38
2642 23:45:07.117019 [Byte1]: 38
2643 23:45:07.121589
2644 23:45:07.122137 Set Vref, RX VrefLevel [Byte0]: 39
2645 23:45:07.124778 [Byte1]: 39
2646 23:45:07.129423
2647 23:45:07.129881 Set Vref, RX VrefLevel [Byte0]: 40
2648 23:45:07.132824 [Byte1]: 40
2649 23:45:07.137147
2650 23:45:07.137644 Set Vref, RX VrefLevel [Byte0]: 41
2651 23:45:07.140610 [Byte1]: 41
2652 23:45:07.145859
2653 23:45:07.146318 Set Vref, RX VrefLevel [Byte0]: 42
2654 23:45:07.148817 [Byte1]: 42
2655 23:45:07.153201
2656 23:45:07.153701 Set Vref, RX VrefLevel [Byte0]: 43
2657 23:45:07.156520 [Byte1]: 43
2658 23:45:07.160958
2659 23:45:07.161451 Set Vref, RX VrefLevel [Byte0]: 44
2660 23:45:07.164309 [Byte1]: 44
2661 23:45:07.168921
2662 23:45:07.169445 Set Vref, RX VrefLevel [Byte0]: 45
2663 23:45:07.172628 [Byte1]: 45
2664 23:45:07.177276
2665 23:45:07.177875 Set Vref, RX VrefLevel [Byte0]: 46
2666 23:45:07.180449 [Byte1]: 46
2667 23:45:07.184868
2668 23:45:07.185362 Set Vref, RX VrefLevel [Byte0]: 47
2669 23:45:07.188065 [Byte1]: 47
2670 23:45:07.192597
2671 23:45:07.193056 Set Vref, RX VrefLevel [Byte0]: 48
2672 23:45:07.196079 [Byte1]: 48
2673 23:45:07.200710
2674 23:45:07.203923 Set Vref, RX VrefLevel [Byte0]: 49
2675 23:45:07.204381 [Byte1]: 49
2676 23:45:07.208662
2677 23:45:07.209116 Set Vref, RX VrefLevel [Byte0]: 50
2678 23:45:07.212070 [Byte1]: 50
2679 23:45:07.216424
2680 23:45:07.216879 Set Vref, RX VrefLevel [Byte0]: 51
2681 23:45:07.220323 [Byte1]: 51
2682 23:45:07.224761
2683 23:45:07.225362 Set Vref, RX VrefLevel [Byte0]: 52
2684 23:45:07.227578 [Byte1]: 52
2685 23:45:07.232311
2686 23:45:07.232795 Set Vref, RX VrefLevel [Byte0]: 53
2687 23:45:07.235691 [Byte1]: 53
2688 23:45:07.240147
2689 23:45:07.240600 Set Vref, RX VrefLevel [Byte0]: 54
2690 23:45:07.243510 [Byte1]: 54
2691 23:45:07.248077
2692 23:45:07.248530 Set Vref, RX VrefLevel [Byte0]: 55
2693 23:45:07.251387 [Byte1]: 55
2694 23:45:07.256256
2695 23:45:07.256707 Set Vref, RX VrefLevel [Byte0]: 56
2696 23:45:07.259730 [Byte1]: 56
2697 23:45:07.264011
2698 23:45:07.264463 Set Vref, RX VrefLevel [Byte0]: 57
2699 23:45:07.267475 [Byte1]: 57
2700 23:45:07.271775
2701 23:45:07.272388 Set Vref, RX VrefLevel [Byte0]: 58
2702 23:45:07.275394 [Byte1]: 58
2703 23:45:07.279797
2704 23:45:07.280290 Set Vref, RX VrefLevel [Byte0]: 59
2705 23:45:07.283163 [Byte1]: 59
2706 23:45:07.288098
2707 23:45:07.288507 Set Vref, RX VrefLevel [Byte0]: 60
2708 23:45:07.291094 [Byte1]: 60
2709 23:45:07.295824
2710 23:45:07.296263 Set Vref, RX VrefLevel [Byte0]: 61
2711 23:45:07.298972 [Byte1]: 61
2712 23:45:07.303764
2713 23:45:07.304342 Set Vref, RX VrefLevel [Byte0]: 62
2714 23:45:07.307217 [Byte1]: 62
2715 23:45:07.311830
2716 23:45:07.312338 Set Vref, RX VrefLevel [Byte0]: 63
2717 23:45:07.314905 [Byte1]: 63
2718 23:45:07.319547
2719 23:45:07.320087 Set Vref, RX VrefLevel [Byte0]: 64
2720 23:45:07.323236 [Byte1]: 64
2721 23:45:07.327268
2722 23:45:07.327702 Set Vref, RX VrefLevel [Byte0]: 65
2723 23:45:07.330747 [Byte1]: 65
2724 23:45:07.335158
2725 23:45:07.335600 Set Vref, RX VrefLevel [Byte0]: 66
2726 23:45:07.338390 [Byte1]: 66
2727 23:45:07.343265
2728 23:45:07.343687 Set Vref, RX VrefLevel [Byte0]: 67
2729 23:45:07.346785 [Byte1]: 67
2730 23:45:07.351588
2731 23:45:07.352045 Final RX Vref Byte 0 = 46 to rank0
2732 23:45:07.354537 Final RX Vref Byte 1 = 50 to rank0
2733 23:45:07.357768 Final RX Vref Byte 0 = 46 to rank1
2734 23:45:07.361612 Final RX Vref Byte 1 = 50 to rank1==
2735 23:45:07.364677 Dram Type= 6, Freq= 0, CH_0, rank 0
2736 23:45:07.371146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2737 23:45:07.371568 ==
2738 23:45:07.371897 DQS Delay:
2739 23:45:07.372205 DQS0 = 0, DQS1 = 0
2740 23:45:07.374352 DQM Delay:
2741 23:45:07.374769 DQM0 = 113, DQM1 = 105
2742 23:45:07.378015 DQ Delay:
2743 23:45:07.381261 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2744 23:45:07.384502 DQ4 =118, DQ5 =104, DQ6 =124, DQ7 =120
2745 23:45:07.387587 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =96
2746 23:45:07.391232 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2747 23:45:07.391790
2748 23:45:07.392152
2749 23:45:07.397777 [DQSOSCAuto] RK0, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2750 23:45:07.401158 CH0 RK0: MR19=404, MR18=606
2751 23:45:07.407774 CH0_RK0: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
2752 23:45:07.408237
2753 23:45:07.411405 ----->DramcWriteLeveling(PI) begin...
2754 23:45:07.411966 ==
2755 23:45:07.414533 Dram Type= 6, Freq= 0, CH_0, rank 1
2756 23:45:07.418166 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2757 23:45:07.418720 ==
2758 23:45:07.421661 Write leveling (Byte 0): 27 => 27
2759 23:45:07.424831 Write leveling (Byte 1): 24 => 24
2760 23:45:07.427699 DramcWriteLeveling(PI) end<-----
2761 23:45:07.428156
2762 23:45:07.428534 ==
2763 23:45:07.431199 Dram Type= 6, Freq= 0, CH_0, rank 1
2764 23:45:07.437934 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2765 23:45:07.438397 ==
2766 23:45:07.438757 [Gating] SW mode calibration
2767 23:45:07.447794 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2768 23:45:07.450992 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2769 23:45:07.454187 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2770 23:45:07.460968 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2771 23:45:07.464611 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2772 23:45:07.467419 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2773 23:45:07.474265 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2774 23:45:07.477624 0 11 20 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2775 23:45:07.481036 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2776 23:45:07.487356 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2777 23:45:07.490623 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2778 23:45:07.494086 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2779 23:45:07.500556 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2780 23:45:07.504090 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2781 23:45:07.507592 0 12 16 | B1->B0 | 2525 3736 | 0 1 | (0 0) (1 1)
2782 23:45:07.513969 0 12 20 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
2783 23:45:07.517348 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2784 23:45:07.520707 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2785 23:45:07.527312 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2786 23:45:07.530442 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2787 23:45:07.533866 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2788 23:45:07.540760 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2789 23:45:07.544209 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2790 23:45:07.547245 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2791 23:45:07.554003 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2792 23:45:07.557130 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2793 23:45:07.560661 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2794 23:45:07.563683 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2795 23:45:07.570387 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2796 23:45:07.574140 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2797 23:45:07.577281 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2798 23:45:07.584024 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2799 23:45:07.587103 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2800 23:45:07.590941 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2801 23:45:07.597003 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2802 23:45:07.600670 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2803 23:45:07.604210 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2804 23:45:07.611123 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2805 23:45:07.613803 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2806 23:45:07.617375 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2807 23:45:07.620536 Total UI for P1: 0, mck2ui 16
2808 23:45:07.624258 best dqsien dly found for B0: ( 0, 15, 18)
2809 23:45:07.630328 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2810 23:45:07.630790 Total UI for P1: 0, mck2ui 16
2811 23:45:07.637079 best dqsien dly found for B1: ( 0, 15, 20)
2812 23:45:07.640743 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2813 23:45:07.644128 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2814 23:45:07.644684
2815 23:45:07.647451 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2816 23:45:07.650308 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2817 23:45:07.653526 [Gating] SW calibration Done
2818 23:45:07.653985 ==
2819 23:45:07.657378 Dram Type= 6, Freq= 0, CH_0, rank 1
2820 23:45:07.660467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2821 23:45:07.660931 ==
2822 23:45:07.663627 RX Vref Scan: 0
2823 23:45:07.664113
2824 23:45:07.664474 RX Vref 0 -> 0, step: 1
2825 23:45:07.664811
2826 23:45:07.667043 RX Delay -40 -> 252, step: 8
2827 23:45:07.670356 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2828 23:45:07.677365 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2829 23:45:07.680453 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2830 23:45:07.683689 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2831 23:45:07.687067 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2832 23:45:07.690296 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2833 23:45:07.697068 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2834 23:45:07.700509 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2835 23:45:07.703594 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2836 23:45:07.707069 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2837 23:45:07.710559 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2838 23:45:07.717150 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2839 23:45:07.720279 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2840 23:45:07.723616 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2841 23:45:07.726867 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2842 23:45:07.730096 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2843 23:45:07.730555 ==
2844 23:45:07.733698 Dram Type= 6, Freq= 0, CH_0, rank 1
2845 23:45:07.740558 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2846 23:45:07.741126 ==
2847 23:45:07.741561 DQS Delay:
2848 23:45:07.743290 DQS0 = 0, DQS1 = 0
2849 23:45:07.743744 DQM Delay:
2850 23:45:07.747397 DQM0 = 115, DQM1 = 107
2851 23:45:07.747953 DQ Delay:
2852 23:45:07.750127 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2853 23:45:07.753465 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2854 23:45:07.756797 DQ8 =91, DQ9 =95, DQ10 =107, DQ11 =99
2855 23:45:07.760541 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =115
2856 23:45:07.761001
2857 23:45:07.761404
2858 23:45:07.761748 ==
2859 23:45:07.763348 Dram Type= 6, Freq= 0, CH_0, rank 1
2860 23:45:07.766667 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2861 23:45:07.770107 ==
2862 23:45:07.770565
2863 23:45:07.771016
2864 23:45:07.771359 TX Vref Scan disable
2865 23:45:07.773739 == TX Byte 0 ==
2866 23:45:07.776971 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2867 23:45:07.780452 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2868 23:45:07.783527 == TX Byte 1 ==
2869 23:45:07.787057 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2870 23:45:07.789989 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2871 23:45:07.793655 ==
2872 23:45:07.794113 Dram Type= 6, Freq= 0, CH_0, rank 1
2873 23:45:07.800277 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2874 23:45:07.800738 ==
2875 23:45:07.811046 TX Vref=22, minBit 5, minWin=25, winSum=416
2876 23:45:07.814991 TX Vref=24, minBit 8, minWin=25, winSum=422
2877 23:45:07.818136 TX Vref=26, minBit 1, minWin=26, winSum=427
2878 23:45:07.821636 TX Vref=28, minBit 8, minWin=25, winSum=427
2879 23:45:07.824478 TX Vref=30, minBit 8, minWin=25, winSum=428
2880 23:45:07.831668 TX Vref=32, minBit 10, minWin=25, winSum=430
2881 23:45:07.834344 [TxChooseVref] Worse bit 1, Min win 26, Win sum 427, Final Vref 26
2882 23:45:07.834804
2883 23:45:07.837962 Final TX Range 1 Vref 26
2884 23:45:07.838686
2885 23:45:07.839073 ==
2886 23:45:07.841263 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 23:45:07.844688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2888 23:45:07.845238 ==
2889 23:45:07.847670
2890 23:45:07.848121
2891 23:45:07.848474 TX Vref Scan disable
2892 23:45:07.851235 == TX Byte 0 ==
2893 23:45:07.854750 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2894 23:45:07.857911 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2895 23:45:07.861524 == TX Byte 1 ==
2896 23:45:07.864471 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2897 23:45:07.867834 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2898 23:45:07.871164
2899 23:45:07.871622 [DATLAT]
2900 23:45:07.871979 Freq=1200, CH0 RK1
2901 23:45:07.872314
2902 23:45:07.874600 DATLAT Default: 0xc
2903 23:45:07.875057 0, 0xFFFF, sum = 0
2904 23:45:07.877820 1, 0xFFFF, sum = 0
2905 23:45:07.878397 2, 0xFFFF, sum = 0
2906 23:45:07.880994 3, 0xFFFF, sum = 0
2907 23:45:07.881527 4, 0xFFFF, sum = 0
2908 23:45:07.884342 5, 0xFFFF, sum = 0
2909 23:45:07.887559 6, 0xFFFF, sum = 0
2910 23:45:07.888025 7, 0xFFFF, sum = 0
2911 23:45:07.891443 8, 0xFFFF, sum = 0
2912 23:45:07.892062 9, 0xFFFF, sum = 0
2913 23:45:07.894390 10, 0xFFFF, sum = 0
2914 23:45:07.894852 11, 0x0, sum = 1
2915 23:45:07.897847 12, 0x0, sum = 2
2916 23:45:07.898313 13, 0x0, sum = 3
2917 23:45:07.898679 14, 0x0, sum = 4
2918 23:45:07.901098 best_step = 12
2919 23:45:07.901596
2920 23:45:07.901958 ==
2921 23:45:07.904345 Dram Type= 6, Freq= 0, CH_0, rank 1
2922 23:45:07.907795 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2923 23:45:07.908425 ==
2924 23:45:07.911098 RX Vref Scan: 0
2925 23:45:07.911652
2926 23:45:07.912097 RX Vref 0 -> 0, step: 1
2927 23:45:07.914579
2928 23:45:07.915133 RX Delay -21 -> 252, step: 4
2929 23:45:07.921568 iDelay=195, Bit 0, Center 110 (39 ~ 182) 144
2930 23:45:07.925069 iDelay=195, Bit 1, Center 116 (43 ~ 190) 148
2931 23:45:07.928476 iDelay=195, Bit 2, Center 114 (43 ~ 186) 144
2932 23:45:07.931540 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
2933 23:45:07.935216 iDelay=195, Bit 4, Center 118 (47 ~ 190) 144
2934 23:45:07.941780 iDelay=195, Bit 5, Center 108 (39 ~ 178) 140
2935 23:45:07.944890 iDelay=195, Bit 6, Center 124 (55 ~ 194) 140
2936 23:45:07.948176 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
2937 23:45:07.951285 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2938 23:45:07.954915 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2939 23:45:07.961374 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
2940 23:45:07.964737 iDelay=195, Bit 11, Center 96 (35 ~ 158) 124
2941 23:45:07.968051 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
2942 23:45:07.971405 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
2943 23:45:07.974684 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2944 23:45:07.981449 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
2945 23:45:07.981905 ==
2946 23:45:07.984773 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 23:45:07.987995 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2948 23:45:07.988417 ==
2949 23:45:07.988749 DQS Delay:
2950 23:45:07.991403 DQS0 = 0, DQS1 = 0
2951 23:45:07.991815 DQM Delay:
2952 23:45:07.994853 DQM0 = 115, DQM1 = 106
2953 23:45:07.995270 DQ Delay:
2954 23:45:07.998085 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2955 23:45:08.001280 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =122
2956 23:45:08.004671 DQ8 =94, DQ9 =90, DQ10 =108, DQ11 =96
2957 23:45:08.008017 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =116
2958 23:45:08.008435
2959 23:45:08.008759
2960 23:45:08.018071 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2961 23:45:08.021417 CH0 RK1: MR19=404, MR18=E0E
2962 23:45:08.024606 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2963 23:45:08.027925 [RxdqsGatingPostProcess] freq 1200
2964 23:45:08.035006 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2965 23:45:08.038006 Pre-setting of DQS Precalculation
2966 23:45:08.041451 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2967 23:45:08.041866 ==
2968 23:45:08.044568 Dram Type= 6, Freq= 0, CH_1, rank 0
2969 23:45:08.051123 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2970 23:45:08.051537 ==
2971 23:45:08.054660 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2972 23:45:08.061345 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2973 23:45:08.069545 [CA 0] Center 37 (7~68) winsize 62
2974 23:45:08.072921 [CA 1] Center 37 (7~68) winsize 62
2975 23:45:08.076132 [CA 2] Center 34 (4~65) winsize 62
2976 23:45:08.079707 [CA 3] Center 33 (3~64) winsize 62
2977 23:45:08.083188 [CA 4] Center 32 (2~63) winsize 62
2978 23:45:08.086504 [CA 5] Center 32 (1~63) winsize 63
2979 23:45:08.086919
2980 23:45:08.089851 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2981 23:45:08.090268
2982 23:45:08.092995 [CATrainingPosCal] consider 1 rank data
2983 23:45:08.096483 u2DelayCellTimex100 = 270/100 ps
2984 23:45:08.099861 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2985 23:45:08.103079 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2986 23:45:08.110488 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2987 23:45:08.113407 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2988 23:45:08.116401 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2989 23:45:08.119721 CA5 delay=32 (1~63),Diff = 0 PI (0 cell)
2990 23:45:08.120179
2991 23:45:08.123021 CA PerBit enable=1, Macro0, CA PI delay=32
2992 23:45:08.123438
2993 23:45:08.126368 [CBTSetCACLKResult] CA Dly = 32
2994 23:45:08.126943 CS Dly: 5 (0~36)
2995 23:45:08.129692 ==
2996 23:45:08.130119 Dram Type= 6, Freq= 0, CH_1, rank 1
2997 23:45:08.136846 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2998 23:45:08.137457 ==
2999 23:45:08.139593 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3000 23:45:08.146834 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3001 23:45:08.155137 [CA 0] Center 37 (6~68) winsize 63
3002 23:45:08.158762 [CA 1] Center 37 (6~68) winsize 63
3003 23:45:08.162004 [CA 2] Center 34 (3~65) winsize 63
3004 23:45:08.165255 [CA 3] Center 33 (3~64) winsize 62
3005 23:45:08.168800 [CA 4] Center 32 (2~63) winsize 62
3006 23:45:08.171876 [CA 5] Center 31 (1~62) winsize 62
3007 23:45:08.172331
3008 23:45:08.175030 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3009 23:45:08.175492
3010 23:45:08.179025 [CATrainingPosCal] consider 2 rank data
3011 23:45:08.181707 u2DelayCellTimex100 = 270/100 ps
3012 23:45:08.185116 CA0 delay=37 (7~68),Diff = 6 PI (28 cell)
3013 23:45:08.188740 CA1 delay=37 (7~68),Diff = 6 PI (28 cell)
3014 23:45:08.195087 CA2 delay=34 (4~65),Diff = 3 PI (14 cell)
3015 23:45:08.198637 CA3 delay=33 (3~64),Diff = 2 PI (9 cell)
3016 23:45:08.201777 CA4 delay=32 (2~63),Diff = 1 PI (4 cell)
3017 23:45:08.205173 CA5 delay=31 (1~62),Diff = 0 PI (0 cell)
3018 23:45:08.205647
3019 23:45:08.208192 CA PerBit enable=1, Macro0, CA PI delay=31
3020 23:45:08.208601
3021 23:45:08.211743 [CBTSetCACLKResult] CA Dly = 31
3022 23:45:08.212148 CS Dly: 6 (0~38)
3023 23:45:08.212470
3024 23:45:08.215063 ----->DramcWriteLeveling(PI) begin...
3025 23:45:08.218227 ==
3026 23:45:08.221528 Dram Type= 6, Freq= 0, CH_1, rank 0
3027 23:45:08.224810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3028 23:45:08.225173 ==
3029 23:45:08.228703 Write leveling (Byte 0): 22 => 22
3030 23:45:08.231589 Write leveling (Byte 1): 22 => 22
3031 23:45:08.235112 DramcWriteLeveling(PI) end<-----
3032 23:45:08.235518
3033 23:45:08.235838 ==
3034 23:45:08.238538 Dram Type= 6, Freq= 0, CH_1, rank 0
3035 23:45:08.241645 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3036 23:45:08.242057 ==
3037 23:45:08.244813 [Gating] SW mode calibration
3038 23:45:08.251669 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3039 23:45:08.255329 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3040 23:45:08.261807 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3041 23:45:08.265133 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3042 23:45:08.268683 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3043 23:45:08.275014 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3044 23:45:08.278542 0 11 16 | B1->B0 | 3333 2c2c | 0 1 | (0 0) (1 0)
3045 23:45:08.281575 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3046 23:45:08.288667 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3047 23:45:08.292202 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3048 23:45:08.295278 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3049 23:45:08.301922 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3050 23:45:08.304950 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3051 23:45:08.308646 0 12 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3052 23:45:08.314997 0 12 16 | B1->B0 | 3232 4141 | 0 1 | (0 0) (0 0)
3053 23:45:08.318891 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3054 23:45:08.321938 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3055 23:45:08.328947 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3056 23:45:08.331960 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3057 23:45:08.335487 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3058 23:45:08.341825 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3059 23:45:08.345082 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3060 23:45:08.348236 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3061 23:45:08.351919 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3062 23:45:08.358799 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3063 23:45:08.361477 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3064 23:45:08.365117 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3065 23:45:08.371693 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3066 23:45:08.374916 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3067 23:45:08.378411 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3068 23:45:08.384982 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3069 23:45:08.388369 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3070 23:45:08.392306 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3071 23:45:08.398289 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3072 23:45:08.401632 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3073 23:45:08.405177 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3074 23:45:08.411784 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3075 23:45:08.415162 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3076 23:45:08.418397 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3077 23:45:08.425083 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3078 23:45:08.425664 Total UI for P1: 0, mck2ui 16
3079 23:45:08.431462 best dqsien dly found for B0: ( 0, 15, 16)
3080 23:45:08.435107 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3081 23:45:08.438397 Total UI for P1: 0, mck2ui 16
3082 23:45:08.441371 best dqsien dly found for B1: ( 0, 15, 18)
3083 23:45:08.445074 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3084 23:45:08.448810 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3085 23:45:08.449392
3086 23:45:08.451812 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3087 23:45:08.455383 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3088 23:45:08.458989 [Gating] SW calibration Done
3089 23:45:08.459541 ==
3090 23:45:08.461914 Dram Type= 6, Freq= 0, CH_1, rank 0
3091 23:45:08.465386 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3092 23:45:08.465938 ==
3093 23:45:08.468682 RX Vref Scan: 0
3094 23:45:08.469207
3095 23:45:08.471998 RX Vref 0 -> 0, step: 1
3096 23:45:08.472450
3097 23:45:08.472806 RX Delay -40 -> 252, step: 8
3098 23:45:08.478365 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3099 23:45:08.481834 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3100 23:45:08.485259 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3101 23:45:08.488090 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3102 23:45:08.492168 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3103 23:45:08.498251 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3104 23:45:08.502109 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3105 23:45:08.505172 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3106 23:45:08.508923 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3107 23:45:08.511902 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3108 23:45:08.518500 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3109 23:45:08.522088 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3110 23:45:08.525368 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3111 23:45:08.527978 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3112 23:45:08.531646 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3113 23:45:08.538161 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3114 23:45:08.538712 ==
3115 23:45:08.541595 Dram Type= 6, Freq= 0, CH_1, rank 0
3116 23:45:08.544665 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3117 23:45:08.545117 ==
3118 23:45:08.545528 DQS Delay:
3119 23:45:08.548097 DQS0 = 0, DQS1 = 0
3120 23:45:08.548545 DQM Delay:
3121 23:45:08.551728 DQM0 = 116, DQM1 = 108
3122 23:45:08.552278 DQ Delay:
3123 23:45:08.554651 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3124 23:45:08.557855 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3125 23:45:08.561319 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =103
3126 23:45:08.564776 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3127 23:45:08.565226
3128 23:45:08.565610
3129 23:45:08.568534 ==
3130 23:45:08.571261 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 23:45:08.574779 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3132 23:45:08.575235 ==
3133 23:45:08.575591
3134 23:45:08.575917
3135 23:45:08.578084 TX Vref Scan disable
3136 23:45:08.578603 == TX Byte 0 ==
3137 23:45:08.581476 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3138 23:45:08.588361 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3139 23:45:08.588913 == TX Byte 1 ==
3140 23:45:08.591380 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3141 23:45:08.597856 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3142 23:45:08.598391 ==
3143 23:45:08.601454 Dram Type= 6, Freq= 0, CH_1, rank 0
3144 23:45:08.604759 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3145 23:45:08.605354 ==
3146 23:45:08.616576 TX Vref=22, minBit 9, minWin=25, winSum=419
3147 23:45:08.619567 TX Vref=24, minBit 1, minWin=26, winSum=424
3148 23:45:08.623339 TX Vref=26, minBit 0, minWin=26, winSum=426
3149 23:45:08.626113 TX Vref=28, minBit 3, minWin=26, winSum=430
3150 23:45:08.629538 TX Vref=30, minBit 11, minWin=26, winSum=435
3151 23:45:08.636210 TX Vref=32, minBit 9, minWin=26, winSum=433
3152 23:45:08.639934 [TxChooseVref] Worse bit 11, Min win 26, Win sum 435, Final Vref 30
3153 23:45:08.640387
3154 23:45:08.642976 Final TX Range 1 Vref 30
3155 23:45:08.643491
3156 23:45:08.643952 ==
3157 23:45:08.646075 Dram Type= 6, Freq= 0, CH_1, rank 0
3158 23:45:08.649557 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3159 23:45:08.649996 ==
3160 23:45:08.653001
3161 23:45:08.653441
3162 23:45:08.653773 TX Vref Scan disable
3163 23:45:08.655946 == TX Byte 0 ==
3164 23:45:08.659557 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3165 23:45:08.662904 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3166 23:45:08.666565 == TX Byte 1 ==
3167 23:45:08.669672 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3168 23:45:08.673449 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3169 23:45:08.673874
3170 23:45:08.676638 [DATLAT]
3171 23:45:08.677050 Freq=1200, CH1 RK0
3172 23:45:08.677505
3173 23:45:08.679663 DATLAT Default: 0xd
3174 23:45:08.680097 0, 0xFFFF, sum = 0
3175 23:45:08.682810 1, 0xFFFF, sum = 0
3176 23:45:08.683310 2, 0xFFFF, sum = 0
3177 23:45:08.686484 3, 0xFFFF, sum = 0
3178 23:45:08.686964 4, 0xFFFF, sum = 0
3179 23:45:08.689407 5, 0xFFFF, sum = 0
3180 23:45:08.689959 6, 0xFFFF, sum = 0
3181 23:45:08.692582 7, 0xFFFF, sum = 0
3182 23:45:08.696058 8, 0xFFFF, sum = 0
3183 23:45:08.696173 9, 0xFFFF, sum = 0
3184 23:45:08.699294 10, 0xFFFF, sum = 0
3185 23:45:08.699394 11, 0x0, sum = 1
3186 23:45:08.702592 12, 0x0, sum = 2
3187 23:45:08.702689 13, 0x0, sum = 3
3188 23:45:08.702778 14, 0x0, sum = 4
3189 23:45:08.705796 best_step = 12
3190 23:45:08.705877
3191 23:45:08.705939 ==
3192 23:45:08.709036 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 23:45:08.713189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3194 23:45:08.713293 ==
3195 23:45:08.715763 RX Vref Scan: 1
3196 23:45:08.715844
3197 23:45:08.715906 Set Vref Range= 32 -> 127
3198 23:45:08.719225
3199 23:45:08.719306 RX Vref 32 -> 127, step: 1
3200 23:45:08.719370
3201 23:45:08.722659 RX Delay -29 -> 252, step: 4
3202 23:45:08.722758
3203 23:45:08.726265 Set Vref, RX VrefLevel [Byte0]: 32
3204 23:45:08.729170 [Byte1]: 32
3205 23:45:08.732758
3206 23:45:08.732842 Set Vref, RX VrefLevel [Byte0]: 33
3207 23:45:08.736046 [Byte1]: 33
3208 23:45:08.740456
3209 23:45:08.740546 Set Vref, RX VrefLevel [Byte0]: 34
3210 23:45:08.743593 [Byte1]: 34
3211 23:45:08.748461
3212 23:45:08.748552 Set Vref, RX VrefLevel [Byte0]: 35
3213 23:45:08.751648 [Byte1]: 35
3214 23:45:08.756614
3215 23:45:08.756696 Set Vref, RX VrefLevel [Byte0]: 36
3216 23:45:08.759644 [Byte1]: 36
3217 23:45:08.764240
3218 23:45:08.764371 Set Vref, RX VrefLevel [Byte0]: 37
3219 23:45:08.767535 [Byte1]: 37
3220 23:45:08.772096
3221 23:45:08.772180 Set Vref, RX VrefLevel [Byte0]: 38
3222 23:45:08.775643 [Byte1]: 38
3223 23:45:08.780270
3224 23:45:08.780365 Set Vref, RX VrefLevel [Byte0]: 39
3225 23:45:08.783438 [Byte1]: 39
3226 23:45:08.788059
3227 23:45:08.788145 Set Vref, RX VrefLevel [Byte0]: 40
3228 23:45:08.791606 [Byte1]: 40
3229 23:45:08.796290
3230 23:45:08.796391 Set Vref, RX VrefLevel [Byte0]: 41
3231 23:45:08.799384 [Byte1]: 41
3232 23:45:08.804051
3233 23:45:08.804205 Set Vref, RX VrefLevel [Byte0]: 42
3234 23:45:08.807425 [Byte1]: 42
3235 23:45:08.812351
3236 23:45:08.812450 Set Vref, RX VrefLevel [Byte0]: 43
3237 23:45:08.815449 [Byte1]: 43
3238 23:45:08.820237
3239 23:45:08.820341 Set Vref, RX VrefLevel [Byte0]: 44
3240 23:45:08.823472 [Byte1]: 44
3241 23:45:08.827771
3242 23:45:08.827900 Set Vref, RX VrefLevel [Byte0]: 45
3243 23:45:08.831552 [Byte1]: 45
3244 23:45:08.836145
3245 23:45:08.836228 Set Vref, RX VrefLevel [Byte0]: 46
3246 23:45:08.839072 [Byte1]: 46
3247 23:45:08.843686
3248 23:45:08.843769 Set Vref, RX VrefLevel [Byte0]: 47
3249 23:45:08.847317 [Byte1]: 47
3250 23:45:08.851693
3251 23:45:08.851773 Set Vref, RX VrefLevel [Byte0]: 48
3252 23:45:08.855220 [Byte1]: 48
3253 23:45:08.859864
3254 23:45:08.859950 Set Vref, RX VrefLevel [Byte0]: 49
3255 23:45:08.863679 [Byte1]: 49
3256 23:45:08.867831
3257 23:45:08.867941 Set Vref, RX VrefLevel [Byte0]: 50
3258 23:45:08.871148 [Byte1]: 50
3259 23:45:08.875670
3260 23:45:08.875778 Set Vref, RX VrefLevel [Byte0]: 51
3261 23:45:08.878976 [Byte1]: 51
3262 23:45:08.883670
3263 23:45:08.883790 Set Vref, RX VrefLevel [Byte0]: 52
3264 23:45:08.886893 [Byte1]: 52
3265 23:45:08.891681
3266 23:45:08.891829 Set Vref, RX VrefLevel [Byte0]: 53
3267 23:45:08.895045 [Byte1]: 53
3268 23:45:08.899833
3269 23:45:08.900030 Set Vref, RX VrefLevel [Byte0]: 54
3270 23:45:08.903196 [Byte1]: 54
3271 23:45:08.907464
3272 23:45:08.907545 Set Vref, RX VrefLevel [Byte0]: 55
3273 23:45:08.910768 [Byte1]: 55
3274 23:45:08.915689
3275 23:45:08.915775 Set Vref, RX VrefLevel [Byte0]: 56
3276 23:45:08.918956 [Byte1]: 56
3277 23:45:08.923382
3278 23:45:08.923462 Set Vref, RX VrefLevel [Byte0]: 57
3279 23:45:08.926668 [Byte1]: 57
3280 23:45:08.931723
3281 23:45:08.932149 Set Vref, RX VrefLevel [Byte0]: 58
3282 23:45:08.935127 [Byte1]: 58
3283 23:45:08.939900
3284 23:45:08.940311 Set Vref, RX VrefLevel [Byte0]: 59
3285 23:45:08.942823 [Byte1]: 59
3286 23:45:08.947641
3287 23:45:08.948055 Set Vref, RX VrefLevel [Byte0]: 60
3288 23:45:08.950944 [Byte1]: 60
3289 23:45:08.955962
3290 23:45:08.956374 Set Vref, RX VrefLevel [Byte0]: 61
3291 23:45:08.958805 [Byte1]: 61
3292 23:45:08.963588
3293 23:45:08.964004 Set Vref, RX VrefLevel [Byte0]: 62
3294 23:45:08.967282 [Byte1]: 62
3295 23:45:08.971584
3296 23:45:08.971997 Set Vref, RX VrefLevel [Byte0]: 63
3297 23:45:08.974742 [Byte1]: 63
3298 23:45:08.979191
3299 23:45:08.979271 Set Vref, RX VrefLevel [Byte0]: 64
3300 23:45:08.982606 [Byte1]: 64
3301 23:45:08.987381
3302 23:45:08.987795 Set Vref, RX VrefLevel [Byte0]: 65
3303 23:45:08.990742 [Byte1]: 65
3304 23:45:08.995563
3305 23:45:08.995975 Set Vref, RX VrefLevel [Byte0]: 66
3306 23:45:08.998947 [Byte1]: 66
3307 23:45:09.003324
3308 23:45:09.003731 Set Vref, RX VrefLevel [Byte0]: 67
3309 23:45:09.006576 [Byte1]: 67
3310 23:45:09.011590
3311 23:45:09.012128 Final RX Vref Byte 0 = 54 to rank0
3312 23:45:09.014709 Final RX Vref Byte 1 = 49 to rank0
3313 23:45:09.018025 Final RX Vref Byte 0 = 54 to rank1
3314 23:45:09.021273 Final RX Vref Byte 1 = 49 to rank1==
3315 23:45:09.024694 Dram Type= 6, Freq= 0, CH_1, rank 0
3316 23:45:09.031192 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3317 23:45:09.031735 ==
3318 23:45:09.032064 DQS Delay:
3319 23:45:09.032367 DQS0 = 0, DQS1 = 0
3320 23:45:09.034794 DQM Delay:
3321 23:45:09.035245 DQM0 = 115, DQM1 = 105
3322 23:45:09.038057 DQ Delay:
3323 23:45:09.041192 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3324 23:45:09.044886 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3325 23:45:09.047926 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =96
3326 23:45:09.051440 DQ12 =112, DQ13 =114, DQ14 =116, DQ15 =114
3327 23:45:09.051999
3328 23:45:09.052382
3329 23:45:09.057993 [DQSOSCAuto] RK0, (LSB)MR18= 0x1919, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3330 23:45:09.061178 CH1 RK0: MR19=404, MR18=1919
3331 23:45:09.067919 CH1_RK0: MR19=0x404, MR18=0x1919, DQSOSC=400, MR23=63, INC=40, DEC=27
3332 23:45:09.068334
3333 23:45:09.071378 ----->DramcWriteLeveling(PI) begin...
3334 23:45:09.071794 ==
3335 23:45:09.074805 Dram Type= 6, Freq= 0, CH_1, rank 1
3336 23:45:09.077981 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3337 23:45:09.078430 ==
3338 23:45:09.081230 Write leveling (Byte 0): 23 => 23
3339 23:45:09.084544 Write leveling (Byte 1): 20 => 20
3340 23:45:09.088183 DramcWriteLeveling(PI) end<-----
3341 23:45:09.088594
3342 23:45:09.088922 ==
3343 23:45:09.091494 Dram Type= 6, Freq= 0, CH_1, rank 1
3344 23:45:09.097994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3345 23:45:09.098411 ==
3346 23:45:09.098737 [Gating] SW mode calibration
3347 23:45:09.108066 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3348 23:45:09.111515 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3349 23:45:09.114872 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3350 23:45:09.121809 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3351 23:45:09.124557 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3352 23:45:09.128334 0 11 12 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 1)
3353 23:45:09.134546 0 11 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (1 0)
3354 23:45:09.137817 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3355 23:45:09.141702 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3356 23:45:09.148035 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3357 23:45:09.151211 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3358 23:45:09.154503 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3359 23:45:09.161046 0 12 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3360 23:45:09.164370 0 12 12 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
3361 23:45:09.168032 0 12 16 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
3362 23:45:09.174520 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3363 23:45:09.177621 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3364 23:45:09.180851 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3365 23:45:09.187775 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3366 23:45:09.191104 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3367 23:45:09.194403 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3368 23:45:09.200787 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3369 23:45:09.204009 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3370 23:45:09.207044 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3371 23:45:09.213668 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3372 23:45:09.217143 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3373 23:45:09.220514 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3374 23:45:09.227009 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3375 23:45:09.230977 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3376 23:45:09.233952 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3377 23:45:09.240632 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3378 23:45:09.243828 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3379 23:45:09.247255 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3380 23:45:09.251125 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3381 23:45:09.257344 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3382 23:45:09.261106 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3383 23:45:09.264250 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3384 23:45:09.271107 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3385 23:45:09.274027 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3386 23:45:09.277160 Total UI for P1: 0, mck2ui 16
3387 23:45:09.280767 best dqsien dly found for B0: ( 0, 15, 12)
3388 23:45:09.283897 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3389 23:45:09.291021 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3390 23:45:09.291315 Total UI for P1: 0, mck2ui 16
3391 23:45:09.297392 best dqsien dly found for B1: ( 0, 15, 16)
3392 23:45:09.300768 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3393 23:45:09.304192 best DQS1 dly(MCK, UI, PI) = (0, 15, 16)
3394 23:45:09.304608
3395 23:45:09.307671 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3396 23:45:09.311048 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 16)
3397 23:45:09.314294 [Gating] SW calibration Done
3398 23:45:09.314706 ==
3399 23:45:09.317802 Dram Type= 6, Freq= 0, CH_1, rank 1
3400 23:45:09.320869 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3401 23:45:09.321283 ==
3402 23:45:09.323944 RX Vref Scan: 0
3403 23:45:09.324383
3404 23:45:09.324708 RX Vref 0 -> 0, step: 1
3405 23:45:09.325013
3406 23:45:09.327669 RX Delay -40 -> 252, step: 8
3407 23:45:09.330674 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3408 23:45:09.337555 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3409 23:45:09.340653 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3410 23:45:09.344117 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3411 23:45:09.347064 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3412 23:45:09.350346 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3413 23:45:09.356889 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3414 23:45:09.360166 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3415 23:45:09.363822 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3416 23:45:09.367176 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3417 23:45:09.370520 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
3418 23:45:09.376850 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3419 23:45:09.380247 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3420 23:45:09.383586 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3421 23:45:09.387298 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3422 23:45:09.390321 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3423 23:45:09.393619 ==
3424 23:45:09.393701 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 23:45:09.400067 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3426 23:45:09.400148 ==
3427 23:45:09.400212 DQS Delay:
3428 23:45:09.403552 DQS0 = 0, DQS1 = 0
3429 23:45:09.403632 DQM Delay:
3430 23:45:09.406901 DQM0 = 116, DQM1 = 106
3431 23:45:09.406982 DQ Delay:
3432 23:45:09.410021 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3433 23:45:09.413545 DQ4 =119, DQ5 =123, DQ6 =123, DQ7 =115
3434 23:45:09.416770 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
3435 23:45:09.420457 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3436 23:45:09.420538
3437 23:45:09.420600
3438 23:45:09.420659 ==
3439 23:45:09.423692 Dram Type= 6, Freq= 0, CH_1, rank 1
3440 23:45:09.426802 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3441 23:45:09.430162 ==
3442 23:45:09.430242
3443 23:45:09.430305
3444 23:45:09.430364 TX Vref Scan disable
3445 23:45:09.433549 == TX Byte 0 ==
3446 23:45:09.436884 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3447 23:45:09.440585 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3448 23:45:09.443728 == TX Byte 1 ==
3449 23:45:09.446761 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3450 23:45:09.450193 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3451 23:45:09.453411 ==
3452 23:45:09.456859 Dram Type= 6, Freq= 0, CH_1, rank 1
3453 23:45:09.460217 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3454 23:45:09.460327 ==
3455 23:45:09.471374 TX Vref=22, minBit 3, minWin=25, winSum=417
3456 23:45:09.474664 TX Vref=24, minBit 9, minWin=25, winSum=420
3457 23:45:09.477987 TX Vref=26, minBit 11, minWin=25, winSum=425
3458 23:45:09.481337 TX Vref=28, minBit 2, minWin=26, winSum=431
3459 23:45:09.484768 TX Vref=30, minBit 0, minWin=26, winSum=434
3460 23:45:09.487909 TX Vref=32, minBit 9, minWin=26, winSum=432
3461 23:45:09.494799 [TxChooseVref] Worse bit 0, Min win 26, Win sum 434, Final Vref 30
3462 23:45:09.494886
3463 23:45:09.497969 Final TX Range 1 Vref 30
3464 23:45:09.498055
3465 23:45:09.498148 ==
3466 23:45:09.501540 Dram Type= 6, Freq= 0, CH_1, rank 1
3467 23:45:09.504617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3468 23:45:09.504698 ==
3469 23:45:09.504762
3470 23:45:09.508120
3471 23:45:09.508206 TX Vref Scan disable
3472 23:45:09.511233 == TX Byte 0 ==
3473 23:45:09.514700 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3474 23:45:09.518227 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3475 23:45:09.521332 == TX Byte 1 ==
3476 23:45:09.524463 Update DQ dly =836 (3 ,1, 36) DQ OEN =(2 ,6)
3477 23:45:09.527956 Update DQM dly =836 (3 ,1, 36) DQM OEN =(2 ,6)
3478 23:45:09.528037
3479 23:45:09.531432 [DATLAT]
3480 23:45:09.531518 Freq=1200, CH1 RK1
3481 23:45:09.531588
3482 23:45:09.534355 DATLAT Default: 0xc
3483 23:45:09.534447 0, 0xFFFF, sum = 0
3484 23:45:09.537715 1, 0xFFFF, sum = 0
3485 23:45:09.537810 2, 0xFFFF, sum = 0
3486 23:45:09.541114 3, 0xFFFF, sum = 0
3487 23:45:09.541249 4, 0xFFFF, sum = 0
3488 23:45:09.544261 5, 0xFFFF, sum = 0
3489 23:45:09.547587 6, 0xFFFF, sum = 0
3490 23:45:09.547699 7, 0xFFFF, sum = 0
3491 23:45:09.551159 8, 0xFFFF, sum = 0
3492 23:45:09.551241 9, 0xFFFF, sum = 0
3493 23:45:09.554206 10, 0xFFFF, sum = 0
3494 23:45:09.554288 11, 0x0, sum = 1
3495 23:45:09.557568 12, 0x0, sum = 2
3496 23:45:09.557649 13, 0x0, sum = 3
3497 23:45:09.561233 14, 0x0, sum = 4
3498 23:45:09.561343 best_step = 12
3499 23:45:09.561412
3500 23:45:09.561476 ==
3501 23:45:09.564192 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 23:45:09.567311 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3503 23:45:09.567405 ==
3504 23:45:09.571096 RX Vref Scan: 0
3505 23:45:09.571175
3506 23:45:09.574126 RX Vref 0 -> 0, step: 1
3507 23:45:09.574206
3508 23:45:09.574270 RX Delay -29 -> 252, step: 4
3509 23:45:09.581740 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3510 23:45:09.585558 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3511 23:45:09.588139 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3512 23:45:09.591533 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3513 23:45:09.594748 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3514 23:45:09.601498 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3515 23:45:09.605120 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3516 23:45:09.608125 iDelay=199, Bit 7, Center 114 (43 ~ 186) 144
3517 23:45:09.611486 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3518 23:45:09.614697 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3519 23:45:09.621525 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3520 23:45:09.625073 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3521 23:45:09.628309 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3522 23:45:09.631390 iDelay=199, Bit 13, Center 110 (43 ~ 178) 136
3523 23:45:09.635130 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3524 23:45:09.641270 iDelay=199, Bit 15, Center 110 (43 ~ 178) 136
3525 23:45:09.641390 ==
3526 23:45:09.645053 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 23:45:09.648481 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3528 23:45:09.648562 ==
3529 23:45:09.648627 DQS Delay:
3530 23:45:09.651681 DQS0 = 0, DQS1 = 0
3531 23:45:09.651761 DQM Delay:
3532 23:45:09.654739 DQM0 = 115, DQM1 = 103
3533 23:45:09.654820 DQ Delay:
3534 23:45:09.658396 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3535 23:45:09.661621 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =114
3536 23:45:09.664694 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3537 23:45:09.668362 DQ12 =112, DQ13 =110, DQ14 =112, DQ15 =110
3538 23:45:09.668449
3539 23:45:09.668517
3540 23:45:09.678203 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3541 23:45:09.681498 CH1 RK1: MR19=404, MR18=C0C
3542 23:45:09.685016 CH1_RK1: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3543 23:45:09.688422 [RxdqsGatingPostProcess] freq 1200
3544 23:45:09.694856 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3545 23:45:09.698780 Pre-setting of DQS Precalculation
3546 23:45:09.701811 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3547 23:45:09.711678 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3548 23:45:09.718276 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3549 23:45:09.718697
3550 23:45:09.719021
3551 23:45:09.722004 [Calibration Summary] 2400 Mbps
3552 23:45:09.722425 CH 0, Rank 0
3553 23:45:09.724914 SW Impedance : PASS
3554 23:45:09.725357 DUTY Scan : NO K
3555 23:45:09.728362 ZQ Calibration : PASS
3556 23:45:09.731666 Jitter Meter : NO K
3557 23:45:09.732086 CBT Training : PASS
3558 23:45:09.734968 Write leveling : PASS
3559 23:45:09.738255 RX DQS gating : PASS
3560 23:45:09.738672 RX DQ/DQS(RDDQC) : PASS
3561 23:45:09.741797 TX DQ/DQS : PASS
3562 23:45:09.742215 RX DATLAT : PASS
3563 23:45:09.745081 RX DQ/DQS(Engine): PASS
3564 23:45:09.748289 TX OE : NO K
3565 23:45:09.748706 All Pass.
3566 23:45:09.749030
3567 23:45:09.749370 CH 0, Rank 1
3568 23:45:09.751673 SW Impedance : PASS
3569 23:45:09.755271 DUTY Scan : NO K
3570 23:45:09.755690 ZQ Calibration : PASS
3571 23:45:09.758426 Jitter Meter : NO K
3572 23:45:09.761713 CBT Training : PASS
3573 23:45:09.762131 Write leveling : PASS
3574 23:45:09.765085 RX DQS gating : PASS
3575 23:45:09.768357 RX DQ/DQS(RDDQC) : PASS
3576 23:45:09.768770 TX DQ/DQS : PASS
3577 23:45:09.771539 RX DATLAT : PASS
3578 23:45:09.774849 RX DQ/DQS(Engine): PASS
3579 23:45:09.775265 TX OE : NO K
3580 23:45:09.778665 All Pass.
3581 23:45:09.779142
3582 23:45:09.779480 CH 1, Rank 0
3583 23:45:09.781746 SW Impedance : PASS
3584 23:45:09.782161 DUTY Scan : NO K
3585 23:45:09.785078 ZQ Calibration : PASS
3586 23:45:09.785540 Jitter Meter : NO K
3587 23:45:09.788755 CBT Training : PASS
3588 23:45:09.792038 Write leveling : PASS
3589 23:45:09.792461 RX DQS gating : PASS
3590 23:45:09.794950 RX DQ/DQS(RDDQC) : PASS
3591 23:45:09.798515 TX DQ/DQS : PASS
3592 23:45:09.798935 RX DATLAT : PASS
3593 23:45:09.802039 RX DQ/DQS(Engine): PASS
3594 23:45:09.804925 TX OE : NO K
3595 23:45:09.805372 All Pass.
3596 23:45:09.805700
3597 23:45:09.806001 CH 1, Rank 1
3598 23:45:09.808508 SW Impedance : PASS
3599 23:45:09.811689 DUTY Scan : NO K
3600 23:45:09.812106 ZQ Calibration : PASS
3601 23:45:09.815078 Jitter Meter : NO K
3602 23:45:09.818665 CBT Training : PASS
3603 23:45:09.819080 Write leveling : PASS
3604 23:45:09.821885 RX DQS gating : PASS
3605 23:45:09.825491 RX DQ/DQS(RDDQC) : PASS
3606 23:45:09.825905 TX DQ/DQS : PASS
3607 23:45:09.828789 RX DATLAT : PASS
3608 23:45:09.829201 RX DQ/DQS(Engine): PASS
3609 23:45:09.831862 TX OE : NO K
3610 23:45:09.832277 All Pass.
3611 23:45:09.832604
3612 23:45:09.835003 DramC Write-DBI off
3613 23:45:09.838415 PER_BANK_REFRESH: Hybrid Mode
3614 23:45:09.838832 TX_TRACKING: ON
3615 23:45:09.848624 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3616 23:45:09.851955 [FAST_K] Save calibration result to emmc
3617 23:45:09.855280 dramc_set_vcore_voltage set vcore to 650000
3618 23:45:09.858349 Read voltage for 600, 5
3619 23:45:09.858863 Vio18 = 0
3620 23:45:09.859324 Vcore = 650000
3621 23:45:09.861850 Vdram = 0
3622 23:45:09.862265 Vddq = 0
3623 23:45:09.862593 Vmddr = 0
3624 23:45:09.868414 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3625 23:45:09.871768 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3626 23:45:09.875053 MEM_TYPE=3, freq_sel=19
3627 23:45:09.878219 sv_algorithm_assistance_LP4_1600
3628 23:45:09.881555 ============ PULL DRAM RESETB DOWN ============
3629 23:45:09.888869 ========== PULL DRAM RESETB DOWN end =========
3630 23:45:09.891612 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3631 23:45:09.894712 ===================================
3632 23:45:09.898119 LPDDR4 DRAM CONFIGURATION
3633 23:45:09.901662 ===================================
3634 23:45:09.902033 EX_ROW_EN[0] = 0x0
3635 23:45:09.904778 EX_ROW_EN[1] = 0x0
3636 23:45:09.905277 LP4Y_EN = 0x0
3637 23:45:09.907887 WORK_FSP = 0x0
3638 23:45:09.908382 WL = 0x2
3639 23:45:09.911281 RL = 0x2
3640 23:45:09.911760 BL = 0x2
3641 23:45:09.914793 RPST = 0x0
3642 23:45:09.918177 RD_PRE = 0x0
3643 23:45:09.918596 WR_PRE = 0x1
3644 23:45:09.921516 WR_PST = 0x0
3645 23:45:09.921945 DBI_WR = 0x0
3646 23:45:09.924683 DBI_RD = 0x0
3647 23:45:09.925250 OTF = 0x1
3648 23:45:09.927910 ===================================
3649 23:45:09.931330 ===================================
3650 23:45:09.934610 ANA top config
3651 23:45:09.938104 ===================================
3652 23:45:09.938651 DLL_ASYNC_EN = 0
3653 23:45:09.941155 ALL_SLAVE_EN = 1
3654 23:45:09.944801 NEW_RANK_MODE = 1
3655 23:45:09.948076 DLL_IDLE_MODE = 1
3656 23:45:09.948619 LP45_APHY_COMB_EN = 1
3657 23:45:09.951406 TX_ODT_DIS = 1
3658 23:45:09.954813 NEW_8X_MODE = 1
3659 23:45:09.957761 ===================================
3660 23:45:09.961486 ===================================
3661 23:45:09.964401 data_rate = 1200
3662 23:45:09.967766 CKR = 1
3663 23:45:09.968205 DQ_P2S_RATIO = 8
3664 23:45:09.971528 ===================================
3665 23:45:09.974451 CA_P2S_RATIO = 8
3666 23:45:09.977896 DQ_CA_OPEN = 0
3667 23:45:09.981148 DQ_SEMI_OPEN = 0
3668 23:45:09.984569 CA_SEMI_OPEN = 0
3669 23:45:09.987795 CA_FULL_RATE = 0
3670 23:45:09.988208 DQ_CKDIV4_EN = 1
3671 23:45:09.990888 CA_CKDIV4_EN = 1
3672 23:45:09.994371 CA_PREDIV_EN = 0
3673 23:45:09.997424 PH8_DLY = 0
3674 23:45:10.001063 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3675 23:45:10.004375 DQ_AAMCK_DIV = 4
3676 23:45:10.004791 CA_AAMCK_DIV = 4
3677 23:45:10.007769 CA_ADMCK_DIV = 4
3678 23:45:10.011275 DQ_TRACK_CA_EN = 0
3679 23:45:10.014140 CA_PICK = 600
3680 23:45:10.017187 CA_MCKIO = 600
3681 23:45:10.020737 MCKIO_SEMI = 0
3682 23:45:10.023913 PLL_FREQ = 2288
3683 23:45:10.024325 DQ_UI_PI_RATIO = 32
3684 23:45:10.027669 CA_UI_PI_RATIO = 0
3685 23:45:10.030880 ===================================
3686 23:45:10.033920 ===================================
3687 23:45:10.037460 memory_type:LPDDR4
3688 23:45:10.040481 GP_NUM : 10
3689 23:45:10.040910 SRAM_EN : 1
3690 23:45:10.043773 MD32_EN : 0
3691 23:45:10.046924 ===================================
3692 23:45:10.050164 [ANA_INIT] >>>>>>>>>>>>>>
3693 23:45:10.053842 <<<<<< [CONFIGURE PHASE]: ANA_TX
3694 23:45:10.057083 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3695 23:45:10.060466 ===================================
3696 23:45:10.060878 data_rate = 1200,PCW = 0X5800
3697 23:45:10.063732 ===================================
3698 23:45:10.066989 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3699 23:45:10.073708 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3700 23:45:10.080417 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3701 23:45:10.083655 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3702 23:45:10.087048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3703 23:45:10.090378 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3704 23:45:10.093534 [ANA_INIT] flow start
3705 23:45:10.093951 [ANA_INIT] PLL >>>>>>>>
3706 23:45:10.096857 [ANA_INIT] PLL <<<<<<<<
3707 23:45:10.099952 [ANA_INIT] MIDPI >>>>>>>>
3708 23:45:10.103657 [ANA_INIT] MIDPI <<<<<<<<
3709 23:45:10.104082 [ANA_INIT] DLL >>>>>>>>
3710 23:45:10.107032 [ANA_INIT] flow end
3711 23:45:10.110393 ============ LP4 DIFF to SE enter ============
3712 23:45:10.113500 ============ LP4 DIFF to SE exit ============
3713 23:45:10.116634 [ANA_INIT] <<<<<<<<<<<<<
3714 23:45:10.120302 [Flow] Enable top DCM control >>>>>
3715 23:45:10.123437 [Flow] Enable top DCM control <<<<<
3716 23:45:10.126636 Enable DLL master slave shuffle
3717 23:45:10.133271 ==============================================================
3718 23:45:10.133729 Gating Mode config
3719 23:45:10.139869 ==============================================================
3720 23:45:10.140399 Config description:
3721 23:45:10.149656 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3722 23:45:10.156261 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3723 23:45:10.163038 SELPH_MODE 0: By rank 1: By Phase
3724 23:45:10.166134 ==============================================================
3725 23:45:10.169872 GAT_TRACK_EN = 1
3726 23:45:10.172855 RX_GATING_MODE = 2
3727 23:45:10.176449 RX_GATING_TRACK_MODE = 2
3728 23:45:10.179675 SELPH_MODE = 1
3729 23:45:10.183056 PICG_EARLY_EN = 1
3730 23:45:10.186366 VALID_LAT_VALUE = 1
3731 23:45:10.192982 ==============================================================
3732 23:45:10.196354 Enter into Gating configuration >>>>
3733 23:45:10.199623 Exit from Gating configuration <<<<
3734 23:45:10.200193 Enter into DVFS_PRE_config >>>>>
3735 23:45:10.212596 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3736 23:45:10.215979 Exit from DVFS_PRE_config <<<<<
3737 23:45:10.219608 Enter into PICG configuration >>>>
3738 23:45:10.222568 Exit from PICG configuration <<<<
3739 23:45:10.223136 [RX_INPUT] configuration >>>>>
3740 23:45:10.225988 [RX_INPUT] configuration <<<<<
3741 23:45:10.232534 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3742 23:45:10.239021 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3743 23:45:10.242556 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3744 23:45:10.249118 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3745 23:45:10.255921 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3746 23:45:10.262699 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3747 23:45:10.265727 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3748 23:45:10.269006 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3749 23:45:10.275690 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3750 23:45:10.279099 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3751 23:45:10.282293 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3752 23:45:10.288711 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3753 23:45:10.292085 ===================================
3754 23:45:10.292497 LPDDR4 DRAM CONFIGURATION
3755 23:45:10.295792 ===================================
3756 23:45:10.299018 EX_ROW_EN[0] = 0x0
3757 23:45:10.299437 EX_ROW_EN[1] = 0x0
3758 23:45:10.301926 LP4Y_EN = 0x0
3759 23:45:10.302366 WORK_FSP = 0x0
3760 23:45:10.305415 WL = 0x2
3761 23:45:10.305839 RL = 0x2
3762 23:45:10.308848 BL = 0x2
3763 23:45:10.311938 RPST = 0x0
3764 23:45:10.312361 RD_PRE = 0x0
3765 23:45:10.315484 WR_PRE = 0x1
3766 23:45:10.315893 WR_PST = 0x0
3767 23:45:10.318519 DBI_WR = 0x0
3768 23:45:10.318953 DBI_RD = 0x0
3769 23:45:10.322331 OTF = 0x1
3770 23:45:10.325193 ===================================
3771 23:45:10.328486 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3772 23:45:10.332028 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3773 23:45:10.335269 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3774 23:45:10.338471 ===================================
3775 23:45:10.341799 LPDDR4 DRAM CONFIGURATION
3776 23:45:10.345321 ===================================
3777 23:45:10.348678 EX_ROW_EN[0] = 0x10
3778 23:45:10.349091 EX_ROW_EN[1] = 0x0
3779 23:45:10.351884 LP4Y_EN = 0x0
3780 23:45:10.352295 WORK_FSP = 0x0
3781 23:45:10.355293 WL = 0x2
3782 23:45:10.355826 RL = 0x2
3783 23:45:10.358534 BL = 0x2
3784 23:45:10.359010 RPST = 0x0
3785 23:45:10.361613 RD_PRE = 0x0
3786 23:45:10.364935 WR_PRE = 0x1
3787 23:45:10.365499 WR_PST = 0x0
3788 23:45:10.368277 DBI_WR = 0x0
3789 23:45:10.368689 DBI_RD = 0x0
3790 23:45:10.371483 OTF = 0x1
3791 23:45:10.375154 ===================================
3792 23:45:10.378265 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3793 23:45:10.383663 nWR fixed to 30
3794 23:45:10.387022 [ModeRegInit_LP4] CH0 RK0
3795 23:45:10.387565 [ModeRegInit_LP4] CH0 RK1
3796 23:45:10.390284 [ModeRegInit_LP4] CH1 RK0
3797 23:45:10.393722 [ModeRegInit_LP4] CH1 RK1
3798 23:45:10.394135 match AC timing 16
3799 23:45:10.400402 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3800 23:45:10.403745 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3801 23:45:10.407078 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3802 23:45:10.413950 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3803 23:45:10.417213 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3804 23:45:10.417781 ==
3805 23:45:10.420093 Dram Type= 6, Freq= 0, CH_0, rank 0
3806 23:45:10.423836 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3807 23:45:10.424526 ==
3808 23:45:10.429990 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3809 23:45:10.436696 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3810 23:45:10.440360 [CA 0] Center 35 (5~66) winsize 62
3811 23:45:10.443146 [CA 1] Center 35 (5~66) winsize 62
3812 23:45:10.446975 [CA 2] Center 34 (4~65) winsize 62
3813 23:45:10.449884 [CA 3] Center 34 (4~65) winsize 62
3814 23:45:10.453095 [CA 4] Center 33 (3~64) winsize 62
3815 23:45:10.456914 [CA 5] Center 33 (3~64) winsize 62
3816 23:45:10.457518
3817 23:45:10.459560 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3818 23:45:10.460069
3819 23:45:10.463057 [CATrainingPosCal] consider 1 rank data
3820 23:45:10.466584 u2DelayCellTimex100 = 270/100 ps
3821 23:45:10.469672 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3822 23:45:10.473272 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3823 23:45:10.476387 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3824 23:45:10.479501 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3825 23:45:10.483143 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3826 23:45:10.489779 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3827 23:45:10.490212
3828 23:45:10.493097 CA PerBit enable=1, Macro0, CA PI delay=33
3829 23:45:10.493701
3830 23:45:10.496543 [CBTSetCACLKResult] CA Dly = 33
3831 23:45:10.496959 CS Dly: 5 (0~36)
3832 23:45:10.497475 ==
3833 23:45:10.499741 Dram Type= 6, Freq= 0, CH_0, rank 1
3834 23:45:10.503096 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3835 23:45:10.506253 ==
3836 23:45:10.509440 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3837 23:45:10.516196 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3838 23:45:10.519357 [CA 0] Center 35 (5~66) winsize 62
3839 23:45:10.522922 [CA 1] Center 35 (5~66) winsize 62
3840 23:45:10.526008 [CA 2] Center 34 (4~65) winsize 62
3841 23:45:10.529254 [CA 3] Center 34 (4~65) winsize 62
3842 23:45:10.532689 [CA 4] Center 33 (3~64) winsize 62
3843 23:45:10.535951 [CA 5] Center 33 (3~64) winsize 62
3844 23:45:10.536362
3845 23:45:10.539286 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3846 23:45:10.539726
3847 23:45:10.542600 [CATrainingPosCal] consider 2 rank data
3848 23:45:10.545831 u2DelayCellTimex100 = 270/100 ps
3849 23:45:10.549059 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3850 23:45:10.552532 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3851 23:45:10.555666 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3852 23:45:10.562365 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3853 23:45:10.565876 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3854 23:45:10.569340 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3855 23:45:10.569760
3856 23:45:10.572520 CA PerBit enable=1, Macro0, CA PI delay=33
3857 23:45:10.572935
3858 23:45:10.575808 [CBTSetCACLKResult] CA Dly = 33
3859 23:45:10.576272 CS Dly: 5 (0~37)
3860 23:45:10.576612
3861 23:45:10.579114 ----->DramcWriteLeveling(PI) begin...
3862 23:45:10.579534 ==
3863 23:45:10.582470 Dram Type= 6, Freq= 0, CH_0, rank 0
3864 23:45:10.589336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3865 23:45:10.589759 ==
3866 23:45:10.592223 Write leveling (Byte 0): 30 => 30
3867 23:45:10.595514 Write leveling (Byte 1): 29 => 29
3868 23:45:10.598920 DramcWriteLeveling(PI) end<-----
3869 23:45:10.599337
3870 23:45:10.599662 ==
3871 23:45:10.602137 Dram Type= 6, Freq= 0, CH_0, rank 0
3872 23:45:10.605616 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3873 23:45:10.606035 ==
3874 23:45:10.609033 [Gating] SW mode calibration
3875 23:45:10.615303 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3876 23:45:10.618998 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3877 23:45:10.625229 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3878 23:45:10.628744 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3879 23:45:10.632058 0 5 8 | B1->B0 | 3232 2f2f | 1 1 | (1 0) (1 0)
3880 23:45:10.638825 0 5 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3881 23:45:10.642064 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3882 23:45:10.645124 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3883 23:45:10.651717 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3884 23:45:10.655016 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3885 23:45:10.658481 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3886 23:45:10.664902 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3887 23:45:10.668351 0 6 8 | B1->B0 | 2929 2f2f | 1 0 | (0 0) (0 0)
3888 23:45:10.671751 0 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3889 23:45:10.678417 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3890 23:45:10.681485 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3891 23:45:10.684655 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3892 23:45:10.691478 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3893 23:45:10.694801 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3894 23:45:10.698484 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3895 23:45:10.704720 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3896 23:45:10.708763 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3897 23:45:10.711383 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3898 23:45:10.717928 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3899 23:45:10.721218 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3900 23:45:10.724552 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3901 23:45:10.731252 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3902 23:45:10.734443 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3903 23:45:10.737664 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3904 23:45:10.744171 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3905 23:45:10.747484 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3906 23:45:10.751139 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3907 23:45:10.757424 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3908 23:45:10.761362 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3909 23:45:10.764281 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3910 23:45:10.771187 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3911 23:45:10.773990 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3912 23:45:10.777573 Total UI for P1: 0, mck2ui 16
3913 23:45:10.780918 best dqsien dly found for B0: ( 0, 9, 6)
3914 23:45:10.784069 Total UI for P1: 0, mck2ui 16
3915 23:45:10.787239 best dqsien dly found for B1: ( 0, 9, 6)
3916 23:45:10.790837 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
3917 23:45:10.793888 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
3918 23:45:10.794440
3919 23:45:10.797237 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
3920 23:45:10.800451 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
3921 23:45:10.803880 [Gating] SW calibration Done
3922 23:45:10.804442 ==
3923 23:45:10.807280 Dram Type= 6, Freq= 0, CH_0, rank 0
3924 23:45:10.810584 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3925 23:45:10.813801 ==
3926 23:45:10.814215 RX Vref Scan: 0
3927 23:45:10.814537
3928 23:45:10.817277 RX Vref 0 -> 0, step: 1
3929 23:45:10.817838
3930 23:45:10.820288 RX Delay -230 -> 252, step: 16
3931 23:45:10.823642 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3932 23:45:10.826863 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3933 23:45:10.830137 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3934 23:45:10.836986 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3935 23:45:10.840288 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3936 23:45:10.843504 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3937 23:45:10.846908 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3938 23:45:10.850012 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3939 23:45:10.856660 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3940 23:45:10.860230 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3941 23:45:10.863642 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3942 23:45:10.866837 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3943 23:45:10.873428 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3944 23:45:10.876662 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3945 23:45:10.880340 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3946 23:45:10.883073 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3947 23:45:10.883484 ==
3948 23:45:10.886562 Dram Type= 6, Freq= 0, CH_0, rank 0
3949 23:45:10.893100 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3950 23:45:10.893630 ==
3951 23:45:10.894115 DQS Delay:
3952 23:45:10.896418 DQS0 = 0, DQS1 = 0
3953 23:45:10.896988 DQM Delay:
3954 23:45:10.899856 DQM0 = 38, DQM1 = 33
3955 23:45:10.900392 DQ Delay:
3956 23:45:10.903059 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3957 23:45:10.906471 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3958 23:45:10.909844 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3959 23:45:10.913235 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3960 23:45:10.913684
3961 23:45:10.914007
3962 23:45:10.914304 ==
3963 23:45:10.916898 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 23:45:10.919715 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3965 23:45:10.920129 ==
3966 23:45:10.920453
3967 23:45:10.920753
3968 23:45:10.923175 TX Vref Scan disable
3969 23:45:10.926512 == TX Byte 0 ==
3970 23:45:10.929646 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3971 23:45:10.932804 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3972 23:45:10.936594 == TX Byte 1 ==
3973 23:45:10.939926 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3974 23:45:10.942971 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3975 23:45:10.943400 ==
3976 23:45:10.946142 Dram Type= 6, Freq= 0, CH_0, rank 0
3977 23:45:10.949589 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3978 23:45:10.952751 ==
3979 23:45:10.953253
3980 23:45:10.953632
3981 23:45:10.953933 TX Vref Scan disable
3982 23:45:10.956971 == TX Byte 0 ==
3983 23:45:10.959912 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
3984 23:45:10.963356 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
3985 23:45:10.966733 == TX Byte 1 ==
3986 23:45:10.970324 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
3987 23:45:10.976529 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
3988 23:45:10.976958
3989 23:45:10.977430 [DATLAT]
3990 23:45:10.977832 Freq=600, CH0 RK0
3991 23:45:10.978218
3992 23:45:10.979866 DATLAT Default: 0x9
3993 23:45:10.980362 0, 0xFFFF, sum = 0
3994 23:45:10.983435 1, 0xFFFF, sum = 0
3995 23:45:10.983852 2, 0xFFFF, sum = 0
3996 23:45:10.986423 3, 0xFFFF, sum = 0
3997 23:45:10.989800 4, 0xFFFF, sum = 0
3998 23:45:10.990219 5, 0xFFFF, sum = 0
3999 23:45:10.993818 6, 0xFFFF, sum = 0
4000 23:45:10.994233 7, 0x0, sum = 1
4001 23:45:10.994578 8, 0x0, sum = 2
4002 23:45:10.996277 9, 0x0, sum = 3
4003 23:45:10.996690 10, 0x0, sum = 4
4004 23:45:10.999798 best_step = 8
4005 23:45:11.000208
4006 23:45:11.000525 ==
4007 23:45:11.002939 Dram Type= 6, Freq= 0, CH_0, rank 0
4008 23:45:11.006568 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4009 23:45:11.006981 ==
4010 23:45:11.009757 RX Vref Scan: 1
4011 23:45:11.010333
4012 23:45:11.010675 RX Vref 0 -> 0, step: 1
4013 23:45:11.010980
4014 23:45:11.013331 RX Delay -195 -> 252, step: 8
4015 23:45:11.013877
4016 23:45:11.016588 Set Vref, RX VrefLevel [Byte0]: 46
4017 23:45:11.019429 [Byte1]: 50
4018 23:45:11.023676
4019 23:45:11.024218 Final RX Vref Byte 0 = 46 to rank0
4020 23:45:11.027107 Final RX Vref Byte 1 = 50 to rank0
4021 23:45:11.030786 Final RX Vref Byte 0 = 46 to rank1
4022 23:45:11.033853 Final RX Vref Byte 1 = 50 to rank1==
4023 23:45:11.037221 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 23:45:11.040246 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4025 23:45:11.044112 ==
4026 23:45:11.044663 DQS Delay:
4027 23:45:11.045002 DQS0 = 0, DQS1 = 0
4028 23:45:11.047088 DQM Delay:
4029 23:45:11.047498 DQM0 = 40, DQM1 = 30
4030 23:45:11.050369 DQ Delay:
4031 23:45:11.053572 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4032 23:45:11.054004 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4033 23:45:11.056880 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4034 23:45:11.063729 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4035 23:45:11.064138
4036 23:45:11.064456
4037 23:45:11.069901 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f4f, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
4038 23:45:11.073381 CH0 RK0: MR19=808, MR18=4F4F
4039 23:45:11.080192 CH0_RK0: MR19=0x808, MR18=0x4F4F, DQSOSC=394, MR23=63, INC=168, DEC=112
4040 23:45:11.080607
4041 23:45:11.083418 ----->DramcWriteLeveling(PI) begin...
4042 23:45:11.083837 ==
4043 23:45:11.086722 Dram Type= 6, Freq= 0, CH_0, rank 1
4044 23:45:11.090089 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4045 23:45:11.090514 ==
4046 23:45:11.093350 Write leveling (Byte 0): 29 => 29
4047 23:45:11.096598 Write leveling (Byte 1): 30 => 30
4048 23:45:11.100093 DramcWriteLeveling(PI) end<-----
4049 23:45:11.100526
4050 23:45:11.100850 ==
4051 23:45:11.103386 Dram Type= 6, Freq= 0, CH_0, rank 1
4052 23:45:11.106625 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4053 23:45:11.107183 ==
4054 23:45:11.109950 [Gating] SW mode calibration
4055 23:45:11.116442 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4056 23:45:11.122959 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4057 23:45:11.126394 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 23:45:11.132648 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 23:45:11.136066 0 5 8 | B1->B0 | 3232 3333 | 1 0 | (1 1) (1 1)
4060 23:45:11.139556 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
4061 23:45:11.145719 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 23:45:11.149126 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 23:45:11.152556 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 23:45:11.159288 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 23:45:11.162545 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 23:45:11.165968 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 23:45:11.172372 0 6 8 | B1->B0 | 2c2c 3434 | 0 0 | (0 0) (0 0)
4068 23:45:11.175970 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 23:45:11.178937 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 23:45:11.185432 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 23:45:11.189331 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 23:45:11.192244 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 23:45:11.198803 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 23:45:11.202128 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 23:45:11.205815 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4076 23:45:11.212430 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 23:45:11.215636 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 23:45:11.219035 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 23:45:11.225383 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 23:45:11.228671 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 23:45:11.232143 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 23:45:11.238654 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 23:45:11.242419 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 23:45:11.245581 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 23:45:11.251895 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 23:45:11.255345 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 23:45:11.258870 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 23:45:11.265044 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 23:45:11.268154 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 23:45:11.271612 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 23:45:11.278462 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4092 23:45:11.281421 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4093 23:45:11.284826 Total UI for P1: 0, mck2ui 16
4094 23:45:11.288312 best dqsien dly found for B0: ( 0, 9, 8)
4095 23:45:11.291432 Total UI for P1: 0, mck2ui 16
4096 23:45:11.294911 best dqsien dly found for B1: ( 0, 9, 8)
4097 23:45:11.298203 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4098 23:45:11.301194 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4099 23:45:11.301759
4100 23:45:11.305035 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4101 23:45:11.307993 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4102 23:45:11.311447 [Gating] SW calibration Done
4103 23:45:11.311988 ==
4104 23:45:11.314569 Dram Type= 6, Freq= 0, CH_0, rank 1
4105 23:45:11.317916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4106 23:45:11.318331 ==
4107 23:45:11.321133 RX Vref Scan: 0
4108 23:45:11.321572
4109 23:45:11.321931 RX Vref 0 -> 0, step: 1
4110 23:45:11.324439
4111 23:45:11.324944 RX Delay -230 -> 252, step: 16
4112 23:45:11.331231 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4113 23:45:11.334509 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4114 23:45:11.337840 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4115 23:45:11.341104 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4116 23:45:11.347729 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
4117 23:45:11.351462 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4118 23:45:11.354594 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4119 23:45:11.357617 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4120 23:45:11.361091 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4121 23:45:11.367516 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4122 23:45:11.371078 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4123 23:45:11.374298 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4124 23:45:11.377401 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4125 23:45:11.384493 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4126 23:45:11.387757 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4127 23:45:11.390664 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4128 23:45:11.391089 ==
4129 23:45:11.393832 Dram Type= 6, Freq= 0, CH_0, rank 1
4130 23:45:11.400485 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4131 23:45:11.400899 ==
4132 23:45:11.401223 DQS Delay:
4133 23:45:11.401555 DQS0 = 0, DQS1 = 0
4134 23:45:11.404053 DQM Delay:
4135 23:45:11.404457 DQM0 = 39, DQM1 = 29
4136 23:45:11.407245 DQ Delay:
4137 23:45:11.410641 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4138 23:45:11.411050 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4139 23:45:11.413889 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4140 23:45:11.420124 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4141 23:45:11.420209
4142 23:45:11.420275
4143 23:45:11.420337 ==
4144 23:45:11.423315 Dram Type= 6, Freq= 0, CH_0, rank 1
4145 23:45:11.426771 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4146 23:45:11.426863 ==
4147 23:45:11.426935
4148 23:45:11.427001
4149 23:45:11.430029 TX Vref Scan disable
4150 23:45:11.430108 == TX Byte 0 ==
4151 23:45:11.437335 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4152 23:45:11.440191 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4153 23:45:11.440271 == TX Byte 1 ==
4154 23:45:11.446740 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4155 23:45:11.450202 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4156 23:45:11.450282 ==
4157 23:45:11.453171 Dram Type= 6, Freq= 0, CH_0, rank 1
4158 23:45:11.456602 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4159 23:45:11.456689 ==
4160 23:45:11.456756
4161 23:45:11.456817
4162 23:45:11.459981 TX Vref Scan disable
4163 23:45:11.463345 == TX Byte 0 ==
4164 23:45:11.466481 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4165 23:45:11.470127 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4166 23:45:11.473032 == TX Byte 1 ==
4167 23:45:11.476406 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4168 23:45:11.483036 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4169 23:45:11.483112
4170 23:45:11.483174 [DATLAT]
4171 23:45:11.483231 Freq=600, CH0 RK1
4172 23:45:11.483289
4173 23:45:11.487035 DATLAT Default: 0x8
4174 23:45:11.487140 0, 0xFFFF, sum = 0
4175 23:45:11.489731 1, 0xFFFF, sum = 0
4176 23:45:11.489846 2, 0xFFFF, sum = 0
4177 23:45:11.493429 3, 0xFFFF, sum = 0
4178 23:45:11.493516 4, 0xFFFF, sum = 0
4179 23:45:11.496742 5, 0xFFFF, sum = 0
4180 23:45:11.499783 6, 0xFFFF, sum = 0
4181 23:45:11.499904 7, 0x0, sum = 1
4182 23:45:11.500015 8, 0x0, sum = 2
4183 23:45:11.503146 9, 0x0, sum = 3
4184 23:45:11.503269 10, 0x0, sum = 4
4185 23:45:11.506634 best_step = 8
4186 23:45:11.506735
4187 23:45:11.506854 ==
4188 23:45:11.509689 Dram Type= 6, Freq= 0, CH_0, rank 1
4189 23:45:11.513177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4190 23:45:11.513323 ==
4191 23:45:11.516557 RX Vref Scan: 0
4192 23:45:11.516918
4193 23:45:11.517212 RX Vref 0 -> 0, step: 1
4194 23:45:11.517559
4195 23:45:11.520046 RX Delay -195 -> 252, step: 8
4196 23:45:11.526886 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4197 23:45:11.530499 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4198 23:45:11.533889 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4199 23:45:11.536710 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4200 23:45:11.543538 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4201 23:45:11.546772 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4202 23:45:11.550160 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4203 23:45:11.553722 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4204 23:45:11.560599 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4205 23:45:11.563537 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4206 23:45:11.566706 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4207 23:45:11.570254 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4208 23:45:11.573486 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4209 23:45:11.580392 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4210 23:45:11.583303 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4211 23:45:11.586851 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4212 23:45:11.587398 ==
4213 23:45:11.589858 Dram Type= 6, Freq= 0, CH_0, rank 1
4214 23:45:11.596949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4215 23:45:11.597419 ==
4216 23:45:11.597762 DQS Delay:
4217 23:45:11.598062 DQS0 = 0, DQS1 = 0
4218 23:45:11.599802 DQM Delay:
4219 23:45:11.600223 DQM0 = 40, DQM1 = 32
4220 23:45:11.603339 DQ Delay:
4221 23:45:11.606183 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4222 23:45:11.609945 DQ4 =44, DQ5 =32, DQ6 =44, DQ7 =52
4223 23:45:11.613658 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4224 23:45:11.616098 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4225 23:45:11.616629
4226 23:45:11.616959
4227 23:45:11.622738 [DQSOSCAuto] RK1, (LSB)MR18= 0x6464, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4228 23:45:11.626316 CH0 RK1: MR19=808, MR18=6464
4229 23:45:11.632789 CH0_RK1: MR19=0x808, MR18=0x6464, DQSOSC=391, MR23=63, INC=171, DEC=114
4230 23:45:11.636209 [RxdqsGatingPostProcess] freq 600
4231 23:45:11.639498 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4232 23:45:11.642864 Pre-setting of DQS Precalculation
4233 23:45:11.649403 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4234 23:45:11.649816 ==
4235 23:45:11.652911 Dram Type= 6, Freq= 0, CH_1, rank 0
4236 23:45:11.656076 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4237 23:45:11.656642 ==
4238 23:45:11.662765 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4239 23:45:11.666322 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4240 23:45:11.670622 [CA 0] Center 35 (5~66) winsize 62
4241 23:45:11.673823 [CA 1] Center 35 (5~65) winsize 61
4242 23:45:11.677017 [CA 2] Center 33 (3~64) winsize 62
4243 23:45:11.680693 [CA 3] Center 33 (3~64) winsize 62
4244 23:45:11.684018 [CA 4] Center 33 (2~64) winsize 63
4245 23:45:11.687340 [CA 5] Center 33 (2~64) winsize 63
4246 23:45:11.687972
4247 23:45:11.690473 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4248 23:45:11.690896
4249 23:45:11.693752 [CATrainingPosCal] consider 1 rank data
4250 23:45:11.696898 u2DelayCellTimex100 = 270/100 ps
4251 23:45:11.700783 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4252 23:45:11.707116 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4253 23:45:11.710260 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4254 23:45:11.713498 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4255 23:45:11.717129 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4256 23:45:11.720328 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4257 23:45:11.720738
4258 23:45:11.723585 CA PerBit enable=1, Macro0, CA PI delay=33
4259 23:45:11.723998
4260 23:45:11.726783 [CBTSetCACLKResult] CA Dly = 33
4261 23:45:11.727247 CS Dly: 4 (0~35)
4262 23:45:11.730288 ==
4263 23:45:11.733272 Dram Type= 6, Freq= 0, CH_1, rank 1
4264 23:45:11.736486 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4265 23:45:11.737028 ==
4266 23:45:11.743235 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4267 23:45:11.746416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4268 23:45:11.750359 [CA 0] Center 35 (5~66) winsize 62
4269 23:45:11.753769 [CA 1] Center 34 (4~65) winsize 62
4270 23:45:11.757107 [CA 2] Center 33 (3~64) winsize 62
4271 23:45:11.760289 [CA 3] Center 33 (3~64) winsize 62
4272 23:45:11.763718 [CA 4] Center 32 (2~63) winsize 62
4273 23:45:11.767016 [CA 5] Center 32 (2~63) winsize 62
4274 23:45:11.767570
4275 23:45:11.770350 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4276 23:45:11.770915
4277 23:45:11.773830 [CATrainingPosCal] consider 2 rank data
4278 23:45:11.777108 u2DelayCellTimex100 = 270/100 ps
4279 23:45:11.780234 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4280 23:45:11.786759 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4281 23:45:11.790228 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4282 23:45:11.793414 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4283 23:45:11.796928 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4284 23:45:11.799963 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4285 23:45:11.800406
4286 23:45:11.802967 CA PerBit enable=1, Macro0, CA PI delay=32
4287 23:45:11.803467
4288 23:45:11.806320 [CBTSetCACLKResult] CA Dly = 32
4289 23:45:11.809892 CS Dly: 4 (0~35)
4290 23:45:11.810302
4291 23:45:11.813117 ----->DramcWriteLeveling(PI) begin...
4292 23:45:11.813621 ==
4293 23:45:11.816422 Dram Type= 6, Freq= 0, CH_1, rank 0
4294 23:45:11.819837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4295 23:45:11.820269 ==
4296 23:45:11.823089 Write leveling (Byte 0): 28 => 28
4297 23:45:11.826238 Write leveling (Byte 1): 28 => 28
4298 23:45:11.829616 DramcWriteLeveling(PI) end<-----
4299 23:45:11.830025
4300 23:45:11.830349 ==
4301 23:45:11.832815 Dram Type= 6, Freq= 0, CH_1, rank 0
4302 23:45:11.836180 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4303 23:45:11.836659 ==
4304 23:45:11.839826 [Gating] SW mode calibration
4305 23:45:11.846198 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4306 23:45:11.852878 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4307 23:45:11.855769 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4308 23:45:11.859519 0 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4309 23:45:11.865615 0 5 8 | B1->B0 | 2f2f 2828 | 0 0 | (0 0) (0 0)
4310 23:45:11.868970 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4311 23:45:11.872447 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4312 23:45:11.879141 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4313 23:45:11.882489 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4314 23:45:11.885517 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4315 23:45:11.892836 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4316 23:45:11.895633 0 6 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (1 1)
4317 23:45:11.899390 0 6 8 | B1->B0 | 3131 4444 | 0 0 | (1 1) (0 0)
4318 23:45:11.905715 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4319 23:45:11.909185 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4320 23:45:11.912437 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4321 23:45:11.918620 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4322 23:45:11.922259 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4323 23:45:11.925506 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4324 23:45:11.932169 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4325 23:45:11.935491 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4326 23:45:11.938662 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4327 23:45:11.945356 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4328 23:45:11.948599 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4329 23:45:11.951907 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4330 23:45:11.958648 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4331 23:45:11.961892 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4332 23:45:11.965043 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4333 23:45:11.971768 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4334 23:45:11.975371 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4335 23:45:11.978300 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4336 23:45:11.984937 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4337 23:45:11.988106 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4338 23:45:11.991872 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4339 23:45:11.998231 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4340 23:45:12.001712 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4341 23:45:12.004686 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4342 23:45:12.008201 Total UI for P1: 0, mck2ui 16
4343 23:45:12.011022 best dqsien dly found for B0: ( 0, 9, 6)
4344 23:45:12.018083 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4345 23:45:12.018168 Total UI for P1: 0, mck2ui 16
4346 23:45:12.024350 best dqsien dly found for B1: ( 0, 9, 8)
4347 23:45:12.027605 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4348 23:45:12.031379 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4349 23:45:12.031821
4350 23:45:12.034936 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4351 23:45:12.037635 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4352 23:45:12.040906 [Gating] SW calibration Done
4353 23:45:12.040986 ==
4354 23:45:12.044268 Dram Type= 6, Freq= 0, CH_1, rank 0
4355 23:45:12.047620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4356 23:45:12.047700 ==
4357 23:45:12.051058 RX Vref Scan: 0
4358 23:45:12.051161
4359 23:45:12.051251 RX Vref 0 -> 0, step: 1
4360 23:45:12.051336
4361 23:45:12.053907 RX Delay -230 -> 252, step: 16
4362 23:45:12.057237 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4363 23:45:12.063883 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4364 23:45:12.067403 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4365 23:45:12.070899 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4366 23:45:12.073985 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4367 23:45:12.080554 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4368 23:45:12.084099 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4369 23:45:12.087394 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4370 23:45:12.090557 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4371 23:45:12.097284 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4372 23:45:12.100631 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4373 23:45:12.103865 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4374 23:45:12.107313 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4375 23:45:12.113969 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4376 23:45:12.117138 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4377 23:45:12.120275 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4378 23:45:12.120680 ==
4379 23:45:12.123843 Dram Type= 6, Freq= 0, CH_1, rank 0
4380 23:45:12.127088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4381 23:45:12.127555 ==
4382 23:45:12.130583 DQS Delay:
4383 23:45:12.130988 DQS0 = 0, DQS1 = 0
4384 23:45:12.133408 DQM Delay:
4385 23:45:12.133851 DQM0 = 39, DQM1 = 33
4386 23:45:12.134168 DQ Delay:
4387 23:45:12.136840 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4388 23:45:12.140293 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4389 23:45:12.143554 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4390 23:45:12.146798 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =49
4391 23:45:12.147253
4392 23:45:12.147599
4393 23:45:12.150011 ==
4394 23:45:12.153454 Dram Type= 6, Freq= 0, CH_1, rank 0
4395 23:45:12.156895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4396 23:45:12.157467 ==
4397 23:45:12.157800
4398 23:45:12.158119
4399 23:45:12.159885 TX Vref Scan disable
4400 23:45:12.160425 == TX Byte 0 ==
4401 23:45:12.166788 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4402 23:45:12.169790 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4403 23:45:12.170214 == TX Byte 1 ==
4404 23:45:12.176496 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4405 23:45:12.179867 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4406 23:45:12.180424 ==
4407 23:45:12.183150 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 23:45:12.186346 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4409 23:45:12.186836 ==
4410 23:45:12.187330
4411 23:45:12.187655
4412 23:45:12.189953 TX Vref Scan disable
4413 23:45:12.192992 == TX Byte 0 ==
4414 23:45:12.196474 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4415 23:45:12.200014 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4416 23:45:12.203531 == TX Byte 1 ==
4417 23:45:12.206469 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4418 23:45:12.209641 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4419 23:45:12.210075
4420 23:45:12.212822 [DATLAT]
4421 23:45:12.213318 Freq=600, CH1 RK0
4422 23:45:12.213675
4423 23:45:12.216150 DATLAT Default: 0x9
4424 23:45:12.216611 0, 0xFFFF, sum = 0
4425 23:45:12.219502 1, 0xFFFF, sum = 0
4426 23:45:12.219916 2, 0xFFFF, sum = 0
4427 23:45:12.222703 3, 0xFFFF, sum = 0
4428 23:45:12.223266 4, 0xFFFF, sum = 0
4429 23:45:12.226217 5, 0xFFFF, sum = 0
4430 23:45:12.226661 6, 0xFFFF, sum = 0
4431 23:45:12.229368 7, 0x0, sum = 1
4432 23:45:12.229806 8, 0x0, sum = 2
4433 23:45:12.232767 9, 0x0, sum = 3
4434 23:45:12.233353 10, 0x0, sum = 4
4435 23:45:12.235980 best_step = 8
4436 23:45:12.236513
4437 23:45:12.236970 ==
4438 23:45:12.239168 Dram Type= 6, Freq= 0, CH_1, rank 0
4439 23:45:12.242843 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4440 23:45:12.243354 ==
4441 23:45:12.245857 RX Vref Scan: 1
4442 23:45:12.246319
4443 23:45:12.246676 RX Vref 0 -> 0, step: 1
4444 23:45:12.246994
4445 23:45:12.249367 RX Delay -195 -> 252, step: 8
4446 23:45:12.249800
4447 23:45:12.252695 Set Vref, RX VrefLevel [Byte0]: 54
4448 23:45:12.255540 [Byte1]: 49
4449 23:45:12.259510
4450 23:45:12.259931 Final RX Vref Byte 0 = 54 to rank0
4451 23:45:12.262938 Final RX Vref Byte 1 = 49 to rank0
4452 23:45:12.266468 Final RX Vref Byte 0 = 54 to rank1
4453 23:45:12.269768 Final RX Vref Byte 1 = 49 to rank1==
4454 23:45:12.272984 Dram Type= 6, Freq= 0, CH_1, rank 0
4455 23:45:12.279312 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4456 23:45:12.279727 ==
4457 23:45:12.280049 DQS Delay:
4458 23:45:12.282632 DQS0 = 0, DQS1 = 0
4459 23:45:12.283108 DQM Delay:
4460 23:45:12.283526 DQM0 = 38, DQM1 = 31
4461 23:45:12.286164 DQ Delay:
4462 23:45:12.289377 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4463 23:45:12.293086 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4464 23:45:12.296377 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4465 23:45:12.299603 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4466 23:45:12.300098
4467 23:45:12.300457
4468 23:45:12.305400 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f6f, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
4469 23:45:12.308970 CH1 RK0: MR19=808, MR18=6F6F
4470 23:45:12.315521 CH1_RK0: MR19=0x808, MR18=0x6F6F, DQSOSC=389, MR23=63, INC=173, DEC=115
4471 23:45:12.315626
4472 23:45:12.318853 ----->DramcWriteLeveling(PI) begin...
4473 23:45:12.318934 ==
4474 23:45:12.322183 Dram Type= 6, Freq= 0, CH_1, rank 1
4475 23:45:12.325599 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4476 23:45:12.325684 ==
4477 23:45:12.328678 Write leveling (Byte 0): 31 => 31
4478 23:45:12.332088 Write leveling (Byte 1): 26 => 26
4479 23:45:12.335691 DramcWriteLeveling(PI) end<-----
4480 23:45:12.335760
4481 23:45:12.335819 ==
4482 23:45:12.338745 Dram Type= 6, Freq= 0, CH_1, rank 1
4483 23:45:12.342184 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4484 23:45:12.342254 ==
4485 23:45:12.345436 [Gating] SW mode calibration
4486 23:45:12.352266 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4487 23:45:12.358897 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4488 23:45:12.361940 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4489 23:45:12.368650 0 5 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
4490 23:45:12.371960 0 5 8 | B1->B0 | 2f2f 2424 | 1 0 | (0 0) (0 0)
4491 23:45:12.375172 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 23:45:12.381888 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 23:45:12.385303 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 23:45:12.388771 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 23:45:12.395342 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 23:45:12.398566 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 23:45:12.402021 0 6 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4498 23:45:12.408865 0 6 8 | B1->B0 | 3131 4141 | 0 0 | (1 1) (0 0)
4499 23:45:12.412116 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 23:45:12.415322 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 23:45:12.422075 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 23:45:12.425245 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 23:45:12.428686 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 23:45:12.435104 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 23:45:12.438500 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 23:45:12.441674 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4507 23:45:12.445154 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 23:45:12.452019 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 23:45:12.455217 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 23:45:12.458366 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 23:45:12.465228 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 23:45:12.468460 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 23:45:12.471943 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 23:45:12.478493 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 23:45:12.481570 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 23:45:12.484699 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 23:45:12.491796 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 23:45:12.494802 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 23:45:12.498263 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 23:45:12.504701 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 23:45:12.507960 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4522 23:45:12.511284 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4523 23:45:12.514548 Total UI for P1: 0, mck2ui 16
4524 23:45:12.518007 best dqsien dly found for B0: ( 0, 9, 4)
4525 23:45:12.524462 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4526 23:45:12.524942 Total UI for P1: 0, mck2ui 16
4527 23:45:12.531132 best dqsien dly found for B1: ( 0, 9, 8)
4528 23:45:12.535010 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4529 23:45:12.538018 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4530 23:45:12.538453
4531 23:45:12.541168 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4532 23:45:12.544255 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4533 23:45:12.548011 [Gating] SW calibration Done
4534 23:45:12.548516 ==
4535 23:45:12.551068 Dram Type= 6, Freq= 0, CH_1, rank 1
4536 23:45:12.554631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4537 23:45:12.555154 ==
4538 23:45:12.557915 RX Vref Scan: 0
4539 23:45:12.558536
4540 23:45:12.559016 RX Vref 0 -> 0, step: 1
4541 23:45:12.559472
4542 23:45:12.560913 RX Delay -230 -> 252, step: 16
4543 23:45:12.567974 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4544 23:45:12.571012 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4545 23:45:12.574454 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4546 23:45:12.577594 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4547 23:45:12.580725 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4548 23:45:12.587458 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4549 23:45:12.591011 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4550 23:45:12.594110 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4551 23:45:12.597854 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4552 23:45:12.604426 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4553 23:45:12.607965 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4554 23:45:12.610916 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4555 23:45:12.613991 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4556 23:45:12.620746 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4557 23:45:12.623924 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4558 23:45:12.627224 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4559 23:45:12.627638 ==
4560 23:45:12.630756 Dram Type= 6, Freq= 0, CH_1, rank 1
4561 23:45:12.633845 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4562 23:45:12.634292 ==
4563 23:45:12.637316 DQS Delay:
4564 23:45:12.637752 DQS0 = 0, DQS1 = 0
4565 23:45:12.640712 DQM Delay:
4566 23:45:12.641122 DQM0 = 39, DQM1 = 34
4567 23:45:12.641501 DQ Delay:
4568 23:45:12.644140 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4569 23:45:12.646943 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4570 23:45:12.650412 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4571 23:45:12.654083 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4572 23:45:12.654517
4573 23:45:12.654864
4574 23:45:12.657063 ==
4575 23:45:12.660392 Dram Type= 6, Freq= 0, CH_1, rank 1
4576 23:45:12.663763 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4577 23:45:12.664174 ==
4578 23:45:12.664498
4579 23:45:12.664798
4580 23:45:12.666835 TX Vref Scan disable
4581 23:45:12.667276 == TX Byte 0 ==
4582 23:45:12.673576 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4583 23:45:12.676909 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4584 23:45:12.677465 == TX Byte 1 ==
4585 23:45:12.683789 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4586 23:45:12.686602 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4587 23:45:12.687119 ==
4588 23:45:12.690283 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 23:45:12.693709 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4590 23:45:12.694122 ==
4591 23:45:12.694545
4592 23:45:12.694941
4593 23:45:12.696993 TX Vref Scan disable
4594 23:45:12.700052 == TX Byte 0 ==
4595 23:45:12.703449 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4596 23:45:12.706593 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4597 23:45:12.710265 == TX Byte 1 ==
4598 23:45:12.713238 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4599 23:45:12.716762 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4600 23:45:12.717235
4601 23:45:12.720048 [DATLAT]
4602 23:45:12.720615 Freq=600, CH1 RK1
4603 23:45:12.721046
4604 23:45:12.723292 DATLAT Default: 0x8
4605 23:45:12.723824 0, 0xFFFF, sum = 0
4606 23:45:12.726710 1, 0xFFFF, sum = 0
4607 23:45:12.727221 2, 0xFFFF, sum = 0
4608 23:45:12.729902 3, 0xFFFF, sum = 0
4609 23:45:12.730376 4, 0xFFFF, sum = 0
4610 23:45:12.733188 5, 0xFFFF, sum = 0
4611 23:45:12.733656 6, 0xFFFF, sum = 0
4612 23:45:12.736377 7, 0x0, sum = 1
4613 23:45:12.736834 8, 0x0, sum = 2
4614 23:45:12.739842 9, 0x0, sum = 3
4615 23:45:12.740343 10, 0x0, sum = 4
4616 23:45:12.743351 best_step = 8
4617 23:45:12.743798
4618 23:45:12.744218 ==
4619 23:45:12.746386 Dram Type= 6, Freq= 0, CH_1, rank 1
4620 23:45:12.750060 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4621 23:45:12.750558 ==
4622 23:45:12.753411 RX Vref Scan: 0
4623 23:45:12.753890
4624 23:45:12.754273 RX Vref 0 -> 0, step: 1
4625 23:45:12.754596
4626 23:45:12.756346 RX Delay -195 -> 252, step: 8
4627 23:45:12.763464 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4628 23:45:12.766621 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4629 23:45:12.770143 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4630 23:45:12.773238 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4631 23:45:12.779774 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4632 23:45:12.783355 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4633 23:45:12.786250 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4634 23:45:12.789610 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4635 23:45:12.796540 iDelay=205, Bit 8, Center 16 (-139 ~ 172) 312
4636 23:45:12.799660 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4637 23:45:12.802773 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4638 23:45:12.806251 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4639 23:45:12.809523 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4640 23:45:12.815939 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4641 23:45:12.819411 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4642 23:45:12.822969 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4643 23:45:12.823413 ==
4644 23:45:12.826252 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 23:45:12.832889 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4646 23:45:12.833356 ==
4647 23:45:12.833724 DQS Delay:
4648 23:45:12.834026 DQS0 = 0, DQS1 = 0
4649 23:45:12.836220 DQM Delay:
4650 23:45:12.836782 DQM0 = 37, DQM1 = 30
4651 23:45:12.839485 DQ Delay:
4652 23:45:12.842607 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4653 23:45:12.845936 DQ4 =40, DQ5 =48, DQ6 =44, DQ7 =32
4654 23:45:12.849673 DQ8 =16, DQ9 =20, DQ10 =28, DQ11 =20
4655 23:45:12.852765 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4656 23:45:12.853197
4657 23:45:12.853606
4658 23:45:12.859730 [DQSOSCAuto] RK1, (LSB)MR18= 0x5858, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4659 23:45:12.862853 CH1 RK1: MR19=808, MR18=5858
4660 23:45:12.869230 CH1_RK1: MR19=0x808, MR18=0x5858, DQSOSC=393, MR23=63, INC=169, DEC=113
4661 23:45:12.872516 [RxdqsGatingPostProcess] freq 600
4662 23:45:12.876058 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4663 23:45:12.879191 Pre-setting of DQS Precalculation
4664 23:45:12.885757 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4665 23:45:12.892289 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4666 23:45:12.898877 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4667 23:45:12.899403
4668 23:45:12.899735
4669 23:45:12.902111 [Calibration Summary] 1200 Mbps
4670 23:45:12.902524 CH 0, Rank 0
4671 23:45:12.905405 SW Impedance : PASS
4672 23:45:12.909086 DUTY Scan : NO K
4673 23:45:12.909658 ZQ Calibration : PASS
4674 23:45:12.912247 Jitter Meter : NO K
4675 23:45:12.915438 CBT Training : PASS
4676 23:45:12.915843 Write leveling : PASS
4677 23:45:12.919015 RX DQS gating : PASS
4678 23:45:12.921849 RX DQ/DQS(RDDQC) : PASS
4679 23:45:12.922258 TX DQ/DQS : PASS
4680 23:45:12.925325 RX DATLAT : PASS
4681 23:45:12.928787 RX DQ/DQS(Engine): PASS
4682 23:45:12.929192 TX OE : NO K
4683 23:45:12.931965 All Pass.
4684 23:45:12.932385
4685 23:45:12.932736 CH 0, Rank 1
4686 23:45:12.935366 SW Impedance : PASS
4687 23:45:12.935779 DUTY Scan : NO K
4688 23:45:12.938473 ZQ Calibration : PASS
4689 23:45:12.941935 Jitter Meter : NO K
4690 23:45:12.942351 CBT Training : PASS
4691 23:45:12.945237 Write leveling : PASS
4692 23:45:12.945705 RX DQS gating : PASS
4693 23:45:12.948822 RX DQ/DQS(RDDQC) : PASS
4694 23:45:12.952079 TX DQ/DQS : PASS
4695 23:45:12.952531 RX DATLAT : PASS
4696 23:45:12.955214 RX DQ/DQS(Engine): PASS
4697 23:45:12.958561 TX OE : NO K
4698 23:45:12.958979 All Pass.
4699 23:45:12.959551
4700 23:45:12.959884 CH 1, Rank 0
4701 23:45:12.962099 SW Impedance : PASS
4702 23:45:12.965018 DUTY Scan : NO K
4703 23:45:12.965491 ZQ Calibration : PASS
4704 23:45:12.968589 Jitter Meter : NO K
4705 23:45:12.971791 CBT Training : PASS
4706 23:45:12.972203 Write leveling : PASS
4707 23:45:12.975063 RX DQS gating : PASS
4708 23:45:12.978568 RX DQ/DQS(RDDQC) : PASS
4709 23:45:12.978985 TX DQ/DQS : PASS
4710 23:45:12.981835 RX DATLAT : PASS
4711 23:45:12.985274 RX DQ/DQS(Engine): PASS
4712 23:45:12.985730 TX OE : NO K
4713 23:45:12.986058 All Pass.
4714 23:45:12.988577
4715 23:45:12.988988 CH 1, Rank 1
4716 23:45:12.991886 SW Impedance : PASS
4717 23:45:12.992299 DUTY Scan : NO K
4718 23:45:12.995214 ZQ Calibration : PASS
4719 23:45:12.995631 Jitter Meter : NO K
4720 23:45:12.998486 CBT Training : PASS
4721 23:45:13.001726 Write leveling : PASS
4722 23:45:13.002142 RX DQS gating : PASS
4723 23:45:13.005115 RX DQ/DQS(RDDQC) : PASS
4724 23:45:13.008197 TX DQ/DQS : PASS
4725 23:45:13.008613 RX DATLAT : PASS
4726 23:45:13.011805 RX DQ/DQS(Engine): PASS
4727 23:45:13.014974 TX OE : NO K
4728 23:45:13.015452 All Pass.
4729 23:45:13.015786
4730 23:45:13.018239 DramC Write-DBI off
4731 23:45:13.018654 PER_BANK_REFRESH: Hybrid Mode
4732 23:45:13.021603 TX_TRACKING: ON
4733 23:45:13.028370 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4734 23:45:13.035002 [FAST_K] Save calibration result to emmc
4735 23:45:13.038137 dramc_set_vcore_voltage set vcore to 662500
4736 23:45:13.038554 Read voltage for 933, 3
4737 23:45:13.041427 Vio18 = 0
4738 23:45:13.041846 Vcore = 662500
4739 23:45:13.042171 Vdram = 0
4740 23:45:13.044871 Vddq = 0
4741 23:45:13.045284 Vmddr = 0
4742 23:45:13.048097 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4743 23:45:13.054600 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4744 23:45:13.058177 MEM_TYPE=3, freq_sel=17
4745 23:45:13.061131 sv_algorithm_assistance_LP4_1600
4746 23:45:13.064744 ============ PULL DRAM RESETB DOWN ============
4747 23:45:13.067447 ========== PULL DRAM RESETB DOWN end =========
4748 23:45:13.074355 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4749 23:45:13.077819 ===================================
4750 23:45:13.077952 LPDDR4 DRAM CONFIGURATION
4751 23:45:13.080817 ===================================
4752 23:45:13.083961 EX_ROW_EN[0] = 0x0
4753 23:45:13.084087 EX_ROW_EN[1] = 0x0
4754 23:45:13.087366 LP4Y_EN = 0x0
4755 23:45:13.090883 WORK_FSP = 0x0
4756 23:45:13.091048 WL = 0x3
4757 23:45:13.094048 RL = 0x3
4758 23:45:13.094184 BL = 0x2
4759 23:45:13.097312 RPST = 0x0
4760 23:45:13.097406 RD_PRE = 0x0
4761 23:45:13.100594 WR_PRE = 0x1
4762 23:45:13.100681 WR_PST = 0x0
4763 23:45:13.104579 DBI_WR = 0x0
4764 23:45:13.104766 DBI_RD = 0x0
4765 23:45:13.107232 OTF = 0x1
4766 23:45:13.110402 ===================================
4767 23:45:13.114051 ===================================
4768 23:45:13.114238 ANA top config
4769 23:45:13.117074 ===================================
4770 23:45:13.120543 DLL_ASYNC_EN = 0
4771 23:45:13.123812 ALL_SLAVE_EN = 1
4772 23:45:13.123996 NEW_RANK_MODE = 1
4773 23:45:13.126981 DLL_IDLE_MODE = 1
4774 23:45:13.130628 LP45_APHY_COMB_EN = 1
4775 23:45:13.133393 TX_ODT_DIS = 1
4776 23:45:13.137012 NEW_8X_MODE = 1
4777 23:45:13.140042 ===================================
4778 23:45:13.143704 ===================================
4779 23:45:13.146746 data_rate = 1866
4780 23:45:13.146843 CKR = 1
4781 23:45:13.150221 DQ_P2S_RATIO = 8
4782 23:45:13.153411 ===================================
4783 23:45:13.156716 CA_P2S_RATIO = 8
4784 23:45:13.160113 DQ_CA_OPEN = 0
4785 23:45:13.163539 DQ_SEMI_OPEN = 0
4786 23:45:13.166546 CA_SEMI_OPEN = 0
4787 23:45:13.166760 CA_FULL_RATE = 0
4788 23:45:13.170291 DQ_CKDIV4_EN = 1
4789 23:45:13.173163 CA_CKDIV4_EN = 1
4790 23:45:13.176548 CA_PREDIV_EN = 0
4791 23:45:13.180153 PH8_DLY = 0
4792 23:45:13.183315 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4793 23:45:13.183579 DQ_AAMCK_DIV = 4
4794 23:45:13.186631 CA_AAMCK_DIV = 4
4795 23:45:13.190163 CA_ADMCK_DIV = 4
4796 23:45:13.193829 DQ_TRACK_CA_EN = 0
4797 23:45:13.196644 CA_PICK = 933
4798 23:45:13.200055 CA_MCKIO = 933
4799 23:45:13.200530 MCKIO_SEMI = 0
4800 23:45:13.203332 PLL_FREQ = 3732
4801 23:45:13.206755 DQ_UI_PI_RATIO = 32
4802 23:45:13.210167 CA_UI_PI_RATIO = 0
4803 23:45:13.213271 ===================================
4804 23:45:13.216607 ===================================
4805 23:45:13.219794 memory_type:LPDDR4
4806 23:45:13.220209 GP_NUM : 10
4807 23:45:13.222984 SRAM_EN : 1
4808 23:45:13.226370 MD32_EN : 0
4809 23:45:13.229624 ===================================
4810 23:45:13.230041 [ANA_INIT] >>>>>>>>>>>>>>
4811 23:45:13.233335 <<<<<< [CONFIGURE PHASE]: ANA_TX
4812 23:45:13.236871 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4813 23:45:13.239430 ===================================
4814 23:45:13.242675 data_rate = 1866,PCW = 0X8f00
4815 23:45:13.246331 ===================================
4816 23:45:13.249401 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4817 23:45:13.256245 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4818 23:45:13.259396 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4819 23:45:13.266031 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4820 23:45:13.269404 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4821 23:45:13.272823 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4822 23:45:13.276011 [ANA_INIT] flow start
4823 23:45:13.276433 [ANA_INIT] PLL >>>>>>>>
4824 23:45:13.279378 [ANA_INIT] PLL <<<<<<<<
4825 23:45:13.282768 [ANA_INIT] MIDPI >>>>>>>>
4826 23:45:13.283228 [ANA_INIT] MIDPI <<<<<<<<
4827 23:45:13.285859 [ANA_INIT] DLL >>>>>>>>
4828 23:45:13.289519 [ANA_INIT] flow end
4829 23:45:13.292361 ============ LP4 DIFF to SE enter ============
4830 23:45:13.295726 ============ LP4 DIFF to SE exit ============
4831 23:45:13.299027 [ANA_INIT] <<<<<<<<<<<<<
4832 23:45:13.302146 [Flow] Enable top DCM control >>>>>
4833 23:45:13.305565 [Flow] Enable top DCM control <<<<<
4834 23:45:13.309455 Enable DLL master slave shuffle
4835 23:45:13.312335 ==============================================================
4836 23:45:13.315644 Gating Mode config
4837 23:45:13.322229 ==============================================================
4838 23:45:13.322638 Config description:
4839 23:45:13.332221 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4840 23:45:13.338791 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4841 23:45:13.345409 SELPH_MODE 0: By rank 1: By Phase
4842 23:45:13.348973 ==============================================================
4843 23:45:13.352049 GAT_TRACK_EN = 1
4844 23:45:13.355289 RX_GATING_MODE = 2
4845 23:45:13.358745 RX_GATING_TRACK_MODE = 2
4846 23:45:13.361778 SELPH_MODE = 1
4847 23:45:13.365081 PICG_EARLY_EN = 1
4848 23:45:13.368392 VALID_LAT_VALUE = 1
4849 23:45:13.371921 ==============================================================
4850 23:45:13.374941 Enter into Gating configuration >>>>
4851 23:45:13.378101 Exit from Gating configuration <<<<
4852 23:45:13.381886 Enter into DVFS_PRE_config >>>>>
4853 23:45:13.394452 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4854 23:45:13.397899 Exit from DVFS_PRE_config <<<<<
4855 23:45:13.401137 Enter into PICG configuration >>>>
4856 23:45:13.401216 Exit from PICG configuration <<<<
4857 23:45:13.404533 [RX_INPUT] configuration >>>>>
4858 23:45:13.407800 [RX_INPUT] configuration <<<<<
4859 23:45:13.414425 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4860 23:45:13.417978 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4861 23:45:13.424398 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4862 23:45:13.430954 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4863 23:45:13.437643 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4864 23:45:13.444359 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4865 23:45:13.447362 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4866 23:45:13.451247 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4867 23:45:13.457688 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4868 23:45:13.460804 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4869 23:45:13.464157 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4870 23:45:13.467661 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4871 23:45:13.470855 ===================================
4872 23:45:13.474007 LPDDR4 DRAM CONFIGURATION
4873 23:45:13.477728 ===================================
4874 23:45:13.480652 EX_ROW_EN[0] = 0x0
4875 23:45:13.481059 EX_ROW_EN[1] = 0x0
4876 23:45:13.484172 LP4Y_EN = 0x0
4877 23:45:13.484597 WORK_FSP = 0x0
4878 23:45:13.486924 WL = 0x3
4879 23:45:13.487028 RL = 0x3
4880 23:45:13.490168 BL = 0x2
4881 23:45:13.490252 RPST = 0x0
4882 23:45:13.493671 RD_PRE = 0x0
4883 23:45:13.493761 WR_PRE = 0x1
4884 23:45:13.496876 WR_PST = 0x0
4885 23:45:13.500225 DBI_WR = 0x0
4886 23:45:13.500356 DBI_RD = 0x0
4887 23:45:13.503567 OTF = 0x1
4888 23:45:13.506866 ===================================
4889 23:45:13.510258 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4890 23:45:13.513685 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4891 23:45:13.516926 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4892 23:45:13.520478 ===================================
4893 23:45:13.523628 LPDDR4 DRAM CONFIGURATION
4894 23:45:13.526903 ===================================
4895 23:45:13.530005 EX_ROW_EN[0] = 0x10
4896 23:45:13.530205 EX_ROW_EN[1] = 0x0
4897 23:45:13.533337 LP4Y_EN = 0x0
4898 23:45:13.533569 WORK_FSP = 0x0
4899 23:45:13.537035 WL = 0x3
4900 23:45:13.537266 RL = 0x3
4901 23:45:13.540130 BL = 0x2
4902 23:45:13.540418 RPST = 0x0
4903 23:45:13.543501 RD_PRE = 0x0
4904 23:45:13.543879 WR_PRE = 0x1
4905 23:45:13.547133 WR_PST = 0x0
4906 23:45:13.550324 DBI_WR = 0x0
4907 23:45:13.550749 DBI_RD = 0x0
4908 23:45:13.553091 OTF = 0x1
4909 23:45:13.556285 ===================================
4910 23:45:13.559549 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4911 23:45:13.565260 nWR fixed to 30
4912 23:45:13.568524 [ModeRegInit_LP4] CH0 RK0
4913 23:45:13.568981 [ModeRegInit_LP4] CH0 RK1
4914 23:45:13.571971 [ModeRegInit_LP4] CH1 RK0
4915 23:45:13.575326 [ModeRegInit_LP4] CH1 RK1
4916 23:45:13.575731 match AC timing 8
4917 23:45:13.581676 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4918 23:45:13.584989 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4919 23:45:13.588380 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4920 23:45:13.595007 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4921 23:45:13.598620 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4922 23:45:13.599028 ==
4923 23:45:13.601587 Dram Type= 6, Freq= 0, CH_0, rank 0
4924 23:45:13.604491 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4925 23:45:13.604570 ==
4926 23:45:13.611205 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4927 23:45:13.617947 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4928 23:45:13.621129 [CA 0] Center 38 (8~69) winsize 62
4929 23:45:13.624451 [CA 1] Center 38 (8~69) winsize 62
4930 23:45:13.627844 [CA 2] Center 36 (6~67) winsize 62
4931 23:45:13.631124 [CA 3] Center 36 (6~66) winsize 61
4932 23:45:13.634194 [CA 4] Center 34 (4~65) winsize 62
4933 23:45:13.637418 [CA 5] Center 34 (4~65) winsize 62
4934 23:45:13.637537
4935 23:45:13.641263 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4936 23:45:13.641389
4937 23:45:13.644570 [CATrainingPosCal] consider 1 rank data
4938 23:45:13.647626 u2DelayCellTimex100 = 270/100 ps
4939 23:45:13.651214 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4940 23:45:13.654319 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4941 23:45:13.657676 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4942 23:45:13.660831 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4943 23:45:13.667734 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4944 23:45:13.671134 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4945 23:45:13.671514
4946 23:45:13.674273 CA PerBit enable=1, Macro0, CA PI delay=34
4947 23:45:13.674686
4948 23:45:13.677737 [CBTSetCACLKResult] CA Dly = 34
4949 23:45:13.678182 CS Dly: 7 (0~38)
4950 23:45:13.678505 ==
4951 23:45:13.681143 Dram Type= 6, Freq= 0, CH_0, rank 1
4952 23:45:13.687783 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4953 23:45:13.688222 ==
4954 23:45:13.690822 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4955 23:45:13.697602 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4956 23:45:13.700917 [CA 0] Center 38 (8~69) winsize 62
4957 23:45:13.704145 [CA 1] Center 38 (7~69) winsize 63
4958 23:45:13.707389 [CA 2] Center 36 (5~67) winsize 63
4959 23:45:13.710631 [CA 3] Center 35 (5~66) winsize 62
4960 23:45:13.714009 [CA 4] Center 34 (4~64) winsize 61
4961 23:45:13.717602 [CA 5] Center 34 (4~65) winsize 62
4962 23:45:13.718011
4963 23:45:13.720611 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4964 23:45:13.721016
4965 23:45:13.724224 [CATrainingPosCal] consider 2 rank data
4966 23:45:13.726987 u2DelayCellTimex100 = 270/100 ps
4967 23:45:13.730366 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4968 23:45:13.733762 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4969 23:45:13.740318 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4970 23:45:13.743811 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4971 23:45:13.746807 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4972 23:45:13.750401 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4973 23:45:13.750811
4974 23:45:13.753620 CA PerBit enable=1, Macro0, CA PI delay=34
4975 23:45:13.754028
4976 23:45:13.756834 [CBTSetCACLKResult] CA Dly = 34
4977 23:45:13.757260 CS Dly: 7 (0~39)
4978 23:45:13.760451
4979 23:45:13.763529 ----->DramcWriteLeveling(PI) begin...
4980 23:45:13.764052 ==
4981 23:45:13.766822 Dram Type= 6, Freq= 0, CH_0, rank 0
4982 23:45:13.770751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4983 23:45:13.771164 ==
4984 23:45:13.773688 Write leveling (Byte 0): 30 => 30
4985 23:45:13.776713 Write leveling (Byte 1): 28 => 28
4986 23:45:13.780196 DramcWriteLeveling(PI) end<-----
4987 23:45:13.780601
4988 23:45:13.781033 ==
4989 23:45:13.783639 Dram Type= 6, Freq= 0, CH_0, rank 0
4990 23:45:13.787013 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4991 23:45:13.787424 ==
4992 23:45:13.790268 [Gating] SW mode calibration
4993 23:45:13.796695 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4994 23:45:13.803643 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4995 23:45:13.806850 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4996 23:45:13.810779 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4997 23:45:13.816644 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4998 23:45:13.819635 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4999 23:45:13.823006 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5000 23:45:13.829767 0 10 20 | B1->B0 | 3333 3131 | 0 1 | (0 0) (1 1)
5001 23:45:13.832825 0 10 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
5002 23:45:13.836162 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5003 23:45:13.843028 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5004 23:45:13.846070 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5005 23:45:13.849302 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5006 23:45:13.855963 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5007 23:45:13.859219 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5008 23:45:13.862443 0 11 20 | B1->B0 | 2a2a 3333 | 0 0 | (0 0) (0 0)
5009 23:45:13.869250 0 11 24 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
5010 23:45:13.872300 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5011 23:45:13.876785 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5012 23:45:13.883011 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5013 23:45:13.885909 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5014 23:45:13.889494 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5015 23:45:13.895781 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5016 23:45:13.899501 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5017 23:45:13.902676 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5018 23:45:13.905932 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5019 23:45:13.912463 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5020 23:45:13.915981 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5021 23:45:13.919219 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5022 23:45:13.925828 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5023 23:45:13.928805 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5024 23:45:13.932445 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5025 23:45:13.938596 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5026 23:45:13.942117 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5027 23:45:13.945419 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5028 23:45:13.951870 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5029 23:45:13.955147 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5030 23:45:13.958479 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5031 23:45:13.965156 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5032 23:45:13.968370 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5033 23:45:13.971876 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5034 23:45:13.975169 Total UI for P1: 0, mck2ui 16
5035 23:45:13.978194 best dqsien dly found for B0: ( 0, 14, 22)
5036 23:45:13.982036 Total UI for P1: 0, mck2ui 16
5037 23:45:13.984865 best dqsien dly found for B1: ( 0, 14, 20)
5038 23:45:13.988383 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5039 23:45:13.991781 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5040 23:45:13.994975
5041 23:45:13.998228 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5042 23:45:14.001758 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5043 23:45:14.004826 [Gating] SW calibration Done
5044 23:45:14.004908 ==
5045 23:45:14.008140 Dram Type= 6, Freq= 0, CH_0, rank 0
5046 23:45:14.011363 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5047 23:45:14.011446 ==
5048 23:45:14.011530 RX Vref Scan: 0
5049 23:45:14.014692
5050 23:45:14.014775 RX Vref 0 -> 0, step: 1
5051 23:45:14.014859
5052 23:45:14.018290 RX Delay -80 -> 252, step: 8
5053 23:45:14.021433 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5054 23:45:14.024540 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5055 23:45:14.031197 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5056 23:45:14.034929 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5057 23:45:14.038021 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5058 23:45:14.041099 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5059 23:45:14.044532 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5060 23:45:14.048475 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5061 23:45:14.054255 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5062 23:45:14.057565 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5063 23:45:14.061006 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5064 23:45:14.064263 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5065 23:45:14.067727 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5066 23:45:14.074593 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5067 23:45:14.077511 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5068 23:45:14.080943 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5069 23:45:14.081129 ==
5070 23:45:14.084218 Dram Type= 6, Freq= 0, CH_0, rank 0
5071 23:45:14.087683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5072 23:45:14.087880 ==
5073 23:45:14.091522 DQS Delay:
5074 23:45:14.091729 DQS0 = 0, DQS1 = 0
5075 23:45:14.091940 DQM Delay:
5076 23:45:14.094014 DQM0 = 95, DQM1 = 88
5077 23:45:14.094162 DQ Delay:
5078 23:45:14.097526 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5079 23:45:14.100619 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5080 23:45:14.104462 DQ8 =83, DQ9 =71, DQ10 =87, DQ11 =83
5081 23:45:14.107400 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5082 23:45:14.107479
5083 23:45:14.107541
5084 23:45:14.107598 ==
5085 23:45:14.110586 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 23:45:14.117476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5087 23:45:14.117558 ==
5088 23:45:14.117620
5089 23:45:14.117678
5090 23:45:14.120821 TX Vref Scan disable
5091 23:45:14.120905 == TX Byte 0 ==
5092 23:45:14.123784 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5093 23:45:14.130350 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5094 23:45:14.130430 == TX Byte 1 ==
5095 23:45:14.133826 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5096 23:45:14.140685 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5097 23:45:14.140764 ==
5098 23:45:14.143806 Dram Type= 6, Freq= 0, CH_0, rank 0
5099 23:45:14.147137 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5100 23:45:14.147216 ==
5101 23:45:14.147278
5102 23:45:14.147335
5103 23:45:14.150448 TX Vref Scan disable
5104 23:45:14.153961 == TX Byte 0 ==
5105 23:45:14.157243 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5106 23:45:14.160171 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5107 23:45:14.163784 == TX Byte 1 ==
5108 23:45:14.167234 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5109 23:45:14.170331 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5110 23:45:14.170432
5111 23:45:14.170515 [DATLAT]
5112 23:45:14.173996 Freq=933, CH0 RK0
5113 23:45:14.174126
5114 23:45:14.177323 DATLAT Default: 0xd
5115 23:45:14.177447 0, 0xFFFF, sum = 0
5116 23:45:14.180464 1, 0xFFFF, sum = 0
5117 23:45:14.180589 2, 0xFFFF, sum = 0
5118 23:45:14.184063 3, 0xFFFF, sum = 0
5119 23:45:14.184195 4, 0xFFFF, sum = 0
5120 23:45:14.186984 5, 0xFFFF, sum = 0
5121 23:45:14.187134 6, 0xFFFF, sum = 0
5122 23:45:14.190572 7, 0xFFFF, sum = 0
5123 23:45:14.190744 8, 0xFFFF, sum = 0
5124 23:45:14.193703 9, 0xFFFF, sum = 0
5125 23:45:14.193879 10, 0x0, sum = 1
5126 23:45:14.196895 11, 0x0, sum = 2
5127 23:45:14.197073 12, 0x0, sum = 3
5128 23:45:14.200365 13, 0x0, sum = 4
5129 23:45:14.200813 best_step = 11
5130 23:45:14.201117
5131 23:45:14.201556 ==
5132 23:45:14.204247 Dram Type= 6, Freq= 0, CH_0, rank 0
5133 23:45:14.207122 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5134 23:45:14.207700 ==
5135 23:45:14.210404 RX Vref Scan: 1
5136 23:45:14.210978
5137 23:45:14.213591 RX Vref 0 -> 0, step: 1
5138 23:45:14.213997
5139 23:45:14.214341 RX Delay -69 -> 252, step: 4
5140 23:45:14.217093
5141 23:45:14.220409 Set Vref, RX VrefLevel [Byte0]: 46
5142 23:45:14.223685 [Byte1]: 50
5143 23:45:14.224097
5144 23:45:14.226935 Final RX Vref Byte 0 = 46 to rank0
5145 23:45:14.230230 Final RX Vref Byte 1 = 50 to rank0
5146 23:45:14.233559 Final RX Vref Byte 0 = 46 to rank1
5147 23:45:14.236974 Final RX Vref Byte 1 = 50 to rank1==
5148 23:45:14.240286 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 23:45:14.243482 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5150 23:45:14.244028 ==
5151 23:45:14.247153 DQS Delay:
5152 23:45:14.247807 DQS0 = 0, DQS1 = 0
5153 23:45:14.248298 DQM Delay:
5154 23:45:14.250101 DQM0 = 97, DQM1 = 86
5155 23:45:14.250514 DQ Delay:
5156 23:45:14.253561 DQ0 =94, DQ1 =98, DQ2 =96, DQ3 =92
5157 23:45:14.256655 DQ4 =100, DQ5 =90, DQ6 =104, DQ7 =102
5158 23:45:14.260199 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =78
5159 23:45:14.263579 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =98
5160 23:45:14.264197
5161 23:45:14.264667
5162 23:45:14.273181 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
5163 23:45:14.276966 CH0 RK0: MR19=505, MR18=1C1C
5164 23:45:14.279878 CH0_RK0: MR19=0x505, MR18=0x1C1C, DQSOSC=412, MR23=63, INC=63, DEC=42
5165 23:45:14.280288
5166 23:45:14.283296 ----->DramcWriteLeveling(PI) begin...
5167 23:45:14.286668 ==
5168 23:45:14.289714 Dram Type= 6, Freq= 0, CH_0, rank 1
5169 23:45:14.293133 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5170 23:45:14.293657 ==
5171 23:45:14.296425 Write leveling (Byte 0): 30 => 30
5172 23:45:14.299751 Write leveling (Byte 1): 25 => 25
5173 23:45:14.303526 DramcWriteLeveling(PI) end<-----
5174 23:45:14.304029
5175 23:45:14.304376 ==
5176 23:45:14.306266 Dram Type= 6, Freq= 0, CH_0, rank 1
5177 23:45:14.309759 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5178 23:45:14.310172 ==
5179 23:45:14.313042 [Gating] SW mode calibration
5180 23:45:14.319813 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5181 23:45:14.326188 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5182 23:45:14.329960 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5183 23:45:14.333400 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 23:45:14.339332 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 23:45:14.342876 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 23:45:14.345953 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 23:45:14.352618 0 10 20 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 0)
5188 23:45:14.355922 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 23:45:14.359418 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5190 23:45:14.363068 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5191 23:45:14.369407 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 23:45:14.372605 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 23:45:14.375942 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 23:45:14.382613 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 23:45:14.385745 0 11 20 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (0 0)
5196 23:45:14.389055 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 23:45:14.395703 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 23:45:14.399055 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5199 23:45:14.402374 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 23:45:14.409194 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 23:45:14.412184 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 23:45:14.415778 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 23:45:14.422162 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5204 23:45:14.425872 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5205 23:45:14.428846 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 23:45:14.435587 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 23:45:14.438912 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 23:45:14.442122 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 23:45:14.448800 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 23:45:14.452040 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 23:45:14.455524 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 23:45:14.462114 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 23:45:14.465133 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 23:45:14.468692 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 23:45:14.475427 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 23:45:14.479021 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 23:45:14.481853 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 23:45:14.488313 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 23:45:14.491514 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5220 23:45:14.494939 Total UI for P1: 0, mck2ui 16
5221 23:45:14.498234 best dqsien dly found for B0: ( 0, 14, 18)
5222 23:45:14.501173 Total UI for P1: 0, mck2ui 16
5223 23:45:14.504792 best dqsien dly found for B1: ( 0, 14, 18)
5224 23:45:14.508088 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5225 23:45:14.511594 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5226 23:45:14.512120
5227 23:45:14.514629 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5228 23:45:14.521342 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5229 23:45:14.521797 [Gating] SW calibration Done
5230 23:45:14.522144 ==
5231 23:45:14.524733 Dram Type= 6, Freq= 0, CH_0, rank 1
5232 23:45:14.531368 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5233 23:45:14.531885 ==
5234 23:45:14.532270 RX Vref Scan: 0
5235 23:45:14.532577
5236 23:45:14.534405 RX Vref 0 -> 0, step: 1
5237 23:45:14.534835
5238 23:45:14.537578 RX Delay -80 -> 252, step: 8
5239 23:45:14.540774 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5240 23:45:14.544248 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5241 23:45:14.547805 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5242 23:45:14.550818 iDelay=208, Bit 3, Center 87 (-8 ~ 183) 192
5243 23:45:14.557474 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5244 23:45:14.560692 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5245 23:45:14.564234 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5246 23:45:14.567812 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5247 23:45:14.570731 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5248 23:45:14.577345 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5249 23:45:14.580885 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5250 23:45:14.584611 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5251 23:45:14.587158 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5252 23:45:14.590498 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5253 23:45:14.597116 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5254 23:45:14.600618 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5255 23:45:14.601028 ==
5256 23:45:14.603771 Dram Type= 6, Freq= 0, CH_0, rank 1
5257 23:45:14.607391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5258 23:45:14.607803 ==
5259 23:45:14.608129 DQS Delay:
5260 23:45:14.610785 DQS0 = 0, DQS1 = 0
5261 23:45:14.611325 DQM Delay:
5262 23:45:14.613925 DQM0 = 95, DQM1 = 84
5263 23:45:14.614360 DQ Delay:
5264 23:45:14.617043 DQ0 =91, DQ1 =95, DQ2 =95, DQ3 =87
5265 23:45:14.620783 DQ4 =99, DQ5 =91, DQ6 =99, DQ7 =107
5266 23:45:14.624131 DQ8 =75, DQ9 =67, DQ10 =87, DQ11 =79
5267 23:45:14.626945 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5268 23:45:14.627362
5269 23:45:14.627683
5270 23:45:14.628007 ==
5271 23:45:14.630234 Dram Type= 6, Freq= 0, CH_0, rank 1
5272 23:45:14.636713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5273 23:45:14.637282 ==
5274 23:45:14.637827
5275 23:45:14.638242
5276 23:45:14.638540 TX Vref Scan disable
5277 23:45:14.640190 == TX Byte 0 ==
5278 23:45:14.643639 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5279 23:45:14.649933 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5280 23:45:14.650347 == TX Byte 1 ==
5281 23:45:14.653420 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5282 23:45:14.660354 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5283 23:45:14.660818 ==
5284 23:45:14.663218 Dram Type= 6, Freq= 0, CH_0, rank 1
5285 23:45:14.666515 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5286 23:45:14.667020 ==
5287 23:45:14.667516
5288 23:45:14.667994
5289 23:45:14.669807 TX Vref Scan disable
5290 23:45:14.670251 == TX Byte 0 ==
5291 23:45:14.676622 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5292 23:45:14.679689 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5293 23:45:14.683163 == TX Byte 1 ==
5294 23:45:14.686275 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5295 23:45:14.689698 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5296 23:45:14.690130
5297 23:45:14.690476 [DATLAT]
5298 23:45:14.692908 Freq=933, CH0 RK1
5299 23:45:14.693388
5300 23:45:14.693734 DATLAT Default: 0xb
5301 23:45:14.696318 0, 0xFFFF, sum = 0
5302 23:45:14.699654 1, 0xFFFF, sum = 0
5303 23:45:14.700070 2, 0xFFFF, sum = 0
5304 23:45:14.702953 3, 0xFFFF, sum = 0
5305 23:45:14.703372 4, 0xFFFF, sum = 0
5306 23:45:14.706328 5, 0xFFFF, sum = 0
5307 23:45:14.706861 6, 0xFFFF, sum = 0
5308 23:45:14.709543 7, 0xFFFF, sum = 0
5309 23:45:14.709973 8, 0xFFFF, sum = 0
5310 23:45:14.712809 9, 0xFFFF, sum = 0
5311 23:45:14.713262 10, 0x0, sum = 1
5312 23:45:14.715878 11, 0x0, sum = 2
5313 23:45:14.716295 12, 0x0, sum = 3
5314 23:45:14.719186 13, 0x0, sum = 4
5315 23:45:14.719601 best_step = 11
5316 23:45:14.719956
5317 23:45:14.720262 ==
5318 23:45:14.722739 Dram Type= 6, Freq= 0, CH_0, rank 1
5319 23:45:14.726087 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5320 23:45:14.726532 ==
5321 23:45:14.729344 RX Vref Scan: 0
5322 23:45:14.729778
5323 23:45:14.732541 RX Vref 0 -> 0, step: 1
5324 23:45:14.732950
5325 23:45:14.733321 RX Delay -77 -> 252, step: 4
5326 23:45:14.740619 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5327 23:45:14.743972 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5328 23:45:14.747189 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5329 23:45:14.750777 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5330 23:45:14.753987 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5331 23:45:14.757166 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5332 23:45:14.763700 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5333 23:45:14.767026 iDelay=199, Bit 7, Center 108 (19 ~ 198) 180
5334 23:45:14.770429 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5335 23:45:14.773765 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5336 23:45:14.777013 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5337 23:45:14.783666 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5338 23:45:14.787177 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5339 23:45:14.790107 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5340 23:45:14.793438 iDelay=199, Bit 14, Center 96 (3 ~ 190) 188
5341 23:45:14.796943 iDelay=199, Bit 15, Center 94 (3 ~ 186) 184
5342 23:45:14.797512 ==
5343 23:45:14.800053 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 23:45:14.806875 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5345 23:45:14.807310 ==
5346 23:45:14.807634 DQS Delay:
5347 23:45:14.810068 DQS0 = 0, DQS1 = 0
5348 23:45:14.810475 DQM Delay:
5349 23:45:14.810794 DQM0 = 97, DQM1 = 86
5350 23:45:14.813741 DQ Delay:
5351 23:45:14.817087 DQ0 =94, DQ1 =100, DQ2 =94, DQ3 =92
5352 23:45:14.820206 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =108
5353 23:45:14.823373 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5354 23:45:14.826813 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =94
5355 23:45:14.827226
5356 23:45:14.827549
5357 23:45:14.833515 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5358 23:45:14.836773 CH0 RK1: MR19=505, MR18=2929
5359 23:45:14.843242 CH0_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5360 23:45:14.846400 [RxdqsGatingPostProcess] freq 933
5361 23:45:14.853233 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5362 23:45:14.853708 Pre-setting of DQS Precalculation
5363 23:45:14.859828 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5364 23:45:14.860253 ==
5365 23:45:14.863325 Dram Type= 6, Freq= 0, CH_1, rank 0
5366 23:45:14.866538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5367 23:45:14.866986 ==
5368 23:45:14.873184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5369 23:45:14.879736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5370 23:45:14.883069 [CA 0] Center 37 (7~68) winsize 62
5371 23:45:14.886558 [CA 1] Center 37 (6~68) winsize 63
5372 23:45:14.889625 [CA 2] Center 34 (4~65) winsize 62
5373 23:45:14.893107 [CA 3] Center 34 (4~65) winsize 62
5374 23:45:14.896698 [CA 4] Center 33 (3~63) winsize 61
5375 23:45:14.899840 [CA 5] Center 33 (3~64) winsize 62
5376 23:45:14.900266
5377 23:45:14.903208 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5378 23:45:14.903788
5379 23:45:14.906252 [CATrainingPosCal] consider 1 rank data
5380 23:45:14.909924 u2DelayCellTimex100 = 270/100 ps
5381 23:45:14.912975 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5382 23:45:14.916087 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5383 23:45:14.919645 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5384 23:45:14.923123 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5385 23:45:14.926721 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5386 23:45:14.929854 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5387 23:45:14.930263
5388 23:45:14.936178 CA PerBit enable=1, Macro0, CA PI delay=33
5389 23:45:14.936732
5390 23:45:14.939426 [CBTSetCACLKResult] CA Dly = 33
5391 23:45:14.939786 CS Dly: 5 (0~36)
5392 23:45:14.940090 ==
5393 23:45:14.942884 Dram Type= 6, Freq= 0, CH_1, rank 1
5394 23:45:14.946012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5395 23:45:14.946425 ==
5396 23:45:14.952681 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5397 23:45:14.959309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5398 23:45:14.963122 [CA 0] Center 37 (7~68) winsize 62
5399 23:45:14.966008 [CA 1] Center 37 (6~68) winsize 63
5400 23:45:14.969266 [CA 2] Center 34 (4~65) winsize 62
5401 23:45:14.973017 [CA 3] Center 34 (4~64) winsize 61
5402 23:45:14.976281 [CA 4] Center 33 (3~64) winsize 62
5403 23:45:14.979424 [CA 5] Center 32 (2~63) winsize 62
5404 23:45:14.979956
5405 23:45:14.982527 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5406 23:45:14.982937
5407 23:45:14.985913 [CATrainingPosCal] consider 2 rank data
5408 23:45:14.989071 u2DelayCellTimex100 = 270/100 ps
5409 23:45:14.992483 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5410 23:45:14.995807 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5411 23:45:14.999463 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5412 23:45:15.002519 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5413 23:45:15.005854 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5414 23:45:15.012929 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5415 23:45:15.013377
5416 23:45:15.015623 CA PerBit enable=1, Macro0, CA PI delay=33
5417 23:45:15.016030
5418 23:45:15.018908 [CBTSetCACLKResult] CA Dly = 33
5419 23:45:15.019322 CS Dly: 5 (0~37)
5420 23:45:15.019645
5421 23:45:15.022336 ----->DramcWriteLeveling(PI) begin...
5422 23:45:15.022753 ==
5423 23:45:15.025889 Dram Type= 6, Freq= 0, CH_1, rank 0
5424 23:45:15.029221 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5425 23:45:15.032180 ==
5426 23:45:15.032625 Write leveling (Byte 0): 22 => 22
5427 23:45:15.035905 Write leveling (Byte 1): 22 => 22
5428 23:45:15.039068 DramcWriteLeveling(PI) end<-----
5429 23:45:15.039479
5430 23:45:15.039801 ==
5431 23:45:15.042244 Dram Type= 6, Freq= 0, CH_1, rank 0
5432 23:45:15.048746 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5433 23:45:15.049176 ==
5434 23:45:15.052346 [Gating] SW mode calibration
5435 23:45:15.059329 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5436 23:45:15.062240 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5437 23:45:15.068739 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5438 23:45:15.071859 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5439 23:45:15.075506 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5440 23:45:15.081778 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5441 23:45:15.085268 0 10 16 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 0)
5442 23:45:15.088602 0 10 20 | B1->B0 | 3232 2424 | 1 0 | (1 0) (0 0)
5443 23:45:15.095040 0 10 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5444 23:45:15.098693 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5445 23:45:15.101847 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5446 23:45:15.108682 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5447 23:45:15.111796 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5448 23:45:15.115118 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5449 23:45:15.121825 0 11 16 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5450 23:45:15.125047 0 11 20 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
5451 23:45:15.128273 0 11 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5452 23:45:15.134883 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5453 23:45:15.138295 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5454 23:45:15.141398 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5455 23:45:15.147994 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5456 23:45:15.151464 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5457 23:45:15.154636 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5458 23:45:15.158259 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5459 23:45:15.164900 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5460 23:45:15.168577 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5461 23:45:15.171399 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5462 23:45:15.178110 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5463 23:45:15.181145 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5464 23:45:15.184261 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5465 23:45:15.190888 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5466 23:45:15.194239 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5467 23:45:15.197883 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5468 23:45:15.204147 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5469 23:45:15.207586 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5470 23:45:15.211026 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5471 23:45:15.217556 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5472 23:45:15.220853 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5473 23:45:15.224178 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5474 23:45:15.231163 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5475 23:45:15.234471 Total UI for P1: 0, mck2ui 16
5476 23:45:15.237580 best dqsien dly found for B0: ( 0, 14, 16)
5477 23:45:15.240910 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5478 23:45:15.244200 Total UI for P1: 0, mck2ui 16
5479 23:45:15.247509 best dqsien dly found for B1: ( 0, 14, 20)
5480 23:45:15.250908 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5481 23:45:15.253918 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5482 23:45:15.254430
5483 23:45:15.257413 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5484 23:45:15.260748 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5485 23:45:15.264084 [Gating] SW calibration Done
5486 23:45:15.264489 ==
5487 23:45:15.267195 Dram Type= 6, Freq= 0, CH_1, rank 0
5488 23:45:15.274170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5489 23:45:15.274875 ==
5490 23:45:15.275365 RX Vref Scan: 0
5491 23:45:15.275722
5492 23:45:15.277450 RX Vref 0 -> 0, step: 1
5493 23:45:15.277857
5494 23:45:15.280683 RX Delay -80 -> 252, step: 8
5495 23:45:15.283648 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5496 23:45:15.287123 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5497 23:45:15.290516 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5498 23:45:15.294058 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5499 23:45:15.300380 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5500 23:45:15.303790 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5501 23:45:15.307384 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5502 23:45:15.310620 iDelay=208, Bit 7, Center 95 (-8 ~ 199) 208
5503 23:45:15.313764 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5504 23:45:15.316985 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5505 23:45:15.323432 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5506 23:45:15.326850 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5507 23:45:15.330249 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5508 23:45:15.333719 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5509 23:45:15.336750 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5510 23:45:15.343502 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5511 23:45:15.344101 ==
5512 23:45:15.346907 Dram Type= 6, Freq= 0, CH_1, rank 0
5513 23:45:15.349862 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5514 23:45:15.350273 ==
5515 23:45:15.350640 DQS Delay:
5516 23:45:15.353343 DQS0 = 0, DQS1 = 0
5517 23:45:15.353773 DQM Delay:
5518 23:45:15.356685 DQM0 = 94, DQM1 = 87
5519 23:45:15.357091 DQ Delay:
5520 23:45:15.359942 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5521 23:45:15.363280 DQ4 =91, DQ5 =103, DQ6 =99, DQ7 =95
5522 23:45:15.366533 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =79
5523 23:45:15.370469 DQ12 =95, DQ13 =99, DQ14 =91, DQ15 =91
5524 23:45:15.370953
5525 23:45:15.371279
5526 23:45:15.371576 ==
5527 23:45:15.373198 Dram Type= 6, Freq= 0, CH_1, rank 0
5528 23:45:15.376556 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5529 23:45:15.379742 ==
5530 23:45:15.380171
5531 23:45:15.380516
5532 23:45:15.380820 TX Vref Scan disable
5533 23:45:15.383183 == TX Byte 0 ==
5534 23:45:15.386367 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5535 23:45:15.389534 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5536 23:45:15.392909 == TX Byte 1 ==
5537 23:45:15.396145 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5538 23:45:15.399905 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5539 23:45:15.402760 ==
5540 23:45:15.406057 Dram Type= 6, Freq= 0, CH_1, rank 0
5541 23:45:15.409684 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5542 23:45:15.410096 ==
5543 23:45:15.410453
5544 23:45:15.410771
5545 23:45:15.412535 TX Vref Scan disable
5546 23:45:15.412988 == TX Byte 0 ==
5547 23:45:15.419573 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5548 23:45:15.422677 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5549 23:45:15.423271 == TX Byte 1 ==
5550 23:45:15.429588 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5551 23:45:15.432595 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5552 23:45:15.433132
5553 23:45:15.433575 [DATLAT]
5554 23:45:15.436044 Freq=933, CH1 RK0
5555 23:45:15.436450
5556 23:45:15.436910 DATLAT Default: 0xd
5557 23:45:15.439207 0, 0xFFFF, sum = 0
5558 23:45:15.439619 1, 0xFFFF, sum = 0
5559 23:45:15.442647 2, 0xFFFF, sum = 0
5560 23:45:15.443093 3, 0xFFFF, sum = 0
5561 23:45:15.445846 4, 0xFFFF, sum = 0
5562 23:45:15.446261 5, 0xFFFF, sum = 0
5563 23:45:15.449273 6, 0xFFFF, sum = 0
5564 23:45:15.449760 7, 0xFFFF, sum = 0
5565 23:45:15.452618 8, 0xFFFF, sum = 0
5566 23:45:15.455587 9, 0xFFFF, sum = 0
5567 23:45:15.456003 10, 0x0, sum = 1
5568 23:45:15.456358 11, 0x0, sum = 2
5569 23:45:15.459222 12, 0x0, sum = 3
5570 23:45:15.459636 13, 0x0, sum = 4
5571 23:45:15.462282 best_step = 11
5572 23:45:15.462686
5573 23:45:15.463055 ==
5574 23:45:15.465866 Dram Type= 6, Freq= 0, CH_1, rank 0
5575 23:45:15.469012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5576 23:45:15.469551 ==
5577 23:45:15.472289 RX Vref Scan: 1
5578 23:45:15.472799
5579 23:45:15.473346 RX Vref 0 -> 0, step: 1
5580 23:45:15.475387
5581 23:45:15.475926 RX Delay -69 -> 252, step: 4
5582 23:45:15.476386
5583 23:45:15.478972 Set Vref, RX VrefLevel [Byte0]: 54
5584 23:45:15.482010 [Byte1]: 49
5585 23:45:15.486981
5586 23:45:15.487447 Final RX Vref Byte 0 = 54 to rank0
5587 23:45:15.489891 Final RX Vref Byte 1 = 49 to rank0
5588 23:45:15.493366 Final RX Vref Byte 0 = 54 to rank1
5589 23:45:15.496535 Final RX Vref Byte 1 = 49 to rank1==
5590 23:45:15.499868 Dram Type= 6, Freq= 0, CH_1, rank 0
5591 23:45:15.506685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5592 23:45:15.507262 ==
5593 23:45:15.507757 DQS Delay:
5594 23:45:15.509601 DQS0 = 0, DQS1 = 0
5595 23:45:15.510005 DQM Delay:
5596 23:45:15.510322 DQM0 = 93, DQM1 = 88
5597 23:45:15.512821 DQ Delay:
5598 23:45:15.516286 DQ0 =96, DQ1 =90, DQ2 =86, DQ3 =90
5599 23:45:15.519621 DQ4 =92, DQ5 =104, DQ6 =100, DQ7 =92
5600 23:45:15.522738 DQ8 =72, DQ9 =76, DQ10 =90, DQ11 =80
5601 23:45:15.526027 DQ12 =94, DQ13 =100, DQ14 =96, DQ15 =98
5602 23:45:15.526522
5603 23:45:15.526908
5604 23:45:15.532916 [DQSOSCAuto] RK0, (LSB)MR18= 0x3333, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
5605 23:45:15.536467 CH1 RK0: MR19=505, MR18=3333
5606 23:45:15.542629 CH1_RK0: MR19=0x505, MR18=0x3333, DQSOSC=405, MR23=63, INC=66, DEC=44
5607 23:45:15.543043
5608 23:45:15.546065 ----->DramcWriteLeveling(PI) begin...
5609 23:45:15.546512 ==
5610 23:45:15.549241 Dram Type= 6, Freq= 0, CH_1, rank 1
5611 23:45:15.552644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5612 23:45:15.553056 ==
5613 23:45:15.555930 Write leveling (Byte 0): 23 => 23
5614 23:45:15.559346 Write leveling (Byte 1): 23 => 23
5615 23:45:15.562876 DramcWriteLeveling(PI) end<-----
5616 23:45:15.563287
5617 23:45:15.563629 ==
5618 23:45:15.565570 Dram Type= 6, Freq= 0, CH_1, rank 1
5619 23:45:15.569114 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5620 23:45:15.572647 ==
5621 23:45:15.573090 [Gating] SW mode calibration
5622 23:45:15.582361 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5623 23:45:15.585661 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5624 23:45:15.589035 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 23:45:15.595864 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 23:45:15.598869 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5627 23:45:15.602061 0 10 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5628 23:45:15.608649 0 10 16 | B1->B0 | 3434 2626 | 0 0 | (0 0) (0 0)
5629 23:45:15.612367 0 10 20 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5630 23:45:15.615730 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 23:45:15.621943 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 23:45:15.625253 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 23:45:15.628563 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 23:45:15.635442 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5635 23:45:15.638500 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5636 23:45:15.641742 0 11 16 | B1->B0 | 2727 3f3f | 0 0 | (0 0) (0 0)
5637 23:45:15.648534 0 11 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5638 23:45:15.651920 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 23:45:15.654944 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 23:45:15.661350 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 23:45:15.664977 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 23:45:15.668347 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5643 23:45:15.675130 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5644 23:45:15.678477 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 23:45:15.681659 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5646 23:45:15.688018 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 23:45:15.691300 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 23:45:15.694891 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 23:45:15.701693 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 23:45:15.704795 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 23:45:15.708174 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 23:45:15.714525 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 23:45:15.718168 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 23:45:15.721171 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 23:45:15.727897 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 23:45:15.731436 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 23:45:15.734813 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 23:45:15.741432 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 23:45:15.744348 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 23:45:15.747909 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5661 23:45:15.751330 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5662 23:45:15.754786 Total UI for P1: 0, mck2ui 16
5663 23:45:15.758119 best dqsien dly found for B0: ( 0, 14, 16)
5664 23:45:15.764278 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 23:45:15.767817 Total UI for P1: 0, mck2ui 16
5666 23:45:15.771382 best dqsien dly found for B1: ( 0, 14, 18)
5667 23:45:15.774411 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5668 23:45:15.777888 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5669 23:45:15.778368
5670 23:45:15.781023 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5671 23:45:15.784392 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5672 23:45:15.787407 [Gating] SW calibration Done
5673 23:45:15.787491 ==
5674 23:45:15.790676 Dram Type= 6, Freq= 0, CH_1, rank 1
5675 23:45:15.794132 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5676 23:45:15.794212 ==
5677 23:45:15.797174 RX Vref Scan: 0
5678 23:45:15.797276
5679 23:45:15.800422 RX Vref 0 -> 0, step: 1
5680 23:45:15.800510
5681 23:45:15.800587 RX Delay -80 -> 252, step: 8
5682 23:45:15.807526 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5683 23:45:15.810577 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5684 23:45:15.814260 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5685 23:45:15.817402 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5686 23:45:15.820777 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5687 23:45:15.824129 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5688 23:45:15.830343 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5689 23:45:15.833916 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5690 23:45:15.837369 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5691 23:45:15.840416 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5692 23:45:15.843905 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5693 23:45:15.850217 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5694 23:45:15.853856 iDelay=208, Bit 12, Center 95 (-8 ~ 199) 208
5695 23:45:15.857152 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5696 23:45:15.860548 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5697 23:45:15.863602 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5698 23:45:15.866980 ==
5699 23:45:15.867392 Dram Type= 6, Freq= 0, CH_1, rank 1
5700 23:45:15.873886 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5701 23:45:15.874302 ==
5702 23:45:15.874626 DQS Delay:
5703 23:45:15.876910 DQS0 = 0, DQS1 = 0
5704 23:45:15.877341 DQM Delay:
5705 23:45:15.880161 DQM0 = 94, DQM1 = 87
5706 23:45:15.880571 DQ Delay:
5707 23:45:15.883452 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5708 23:45:15.886831 DQ4 =95, DQ5 =107, DQ6 =99, DQ7 =91
5709 23:45:15.890323 DQ8 =79, DQ9 =79, DQ10 =83, DQ11 =79
5710 23:45:15.893463 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =95
5711 23:45:15.893875
5712 23:45:15.894200
5713 23:45:15.894499 ==
5714 23:45:15.896772 Dram Type= 6, Freq= 0, CH_1, rank 1
5715 23:45:15.899921 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5716 23:45:15.900364 ==
5717 23:45:15.900712
5718 23:45:15.901013
5719 23:45:15.903316 TX Vref Scan disable
5720 23:45:15.906518 == TX Byte 0 ==
5721 23:45:15.909617 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5722 23:45:15.912792 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5723 23:45:15.916057 == TX Byte 1 ==
5724 23:45:15.919688 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5725 23:45:15.922656 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5726 23:45:15.922749 ==
5727 23:45:15.926062 Dram Type= 6, Freq= 0, CH_1, rank 1
5728 23:45:15.932784 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5729 23:45:15.932893 ==
5730 23:45:15.932978
5731 23:45:15.933070
5732 23:45:15.933151 TX Vref Scan disable
5733 23:45:15.936735 == TX Byte 0 ==
5734 23:45:15.939850 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5735 23:45:15.946509 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5736 23:45:15.946589 == TX Byte 1 ==
5737 23:45:15.950094 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5738 23:45:15.956418 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5739 23:45:15.956511
5740 23:45:15.956582 [DATLAT]
5741 23:45:15.956648 Freq=933, CH1 RK1
5742 23:45:15.956713
5743 23:45:15.959758 DATLAT Default: 0xb
5744 23:45:15.959857 0, 0xFFFF, sum = 0
5745 23:45:15.962914 1, 0xFFFF, sum = 0
5746 23:45:15.966333 2, 0xFFFF, sum = 0
5747 23:45:15.966442 3, 0xFFFF, sum = 0
5748 23:45:15.969711 4, 0xFFFF, sum = 0
5749 23:45:15.969832 5, 0xFFFF, sum = 0
5750 23:45:15.973140 6, 0xFFFF, sum = 0
5751 23:45:15.973273 7, 0xFFFF, sum = 0
5752 23:45:15.976338 8, 0xFFFF, sum = 0
5753 23:45:15.976471 9, 0xFFFF, sum = 0
5754 23:45:15.979701 10, 0x0, sum = 1
5755 23:45:15.979851 11, 0x0, sum = 2
5756 23:45:15.982836 12, 0x0, sum = 3
5757 23:45:15.982986 13, 0x0, sum = 4
5758 23:45:15.983123 best_step = 11
5759 23:45:15.986585
5760 23:45:15.986755 ==
5761 23:45:15.989761 Dram Type= 6, Freq= 0, CH_1, rank 1
5762 23:45:15.992783 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5763 23:45:15.992988 ==
5764 23:45:15.993171 RX Vref Scan: 0
5765 23:45:15.993371
5766 23:45:15.996704 RX Vref 0 -> 0, step: 1
5767 23:45:15.996942
5768 23:45:15.999813 RX Delay -61 -> 252, step: 4
5769 23:45:16.003151 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5770 23:45:16.009510 iDelay=203, Bit 1, Center 90 (-1 ~ 182) 184
5771 23:45:16.012863 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5772 23:45:16.016246 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5773 23:45:16.019393 iDelay=203, Bit 4, Center 98 (3 ~ 194) 192
5774 23:45:16.022668 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5775 23:45:16.029338 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5776 23:45:16.032516 iDelay=203, Bit 7, Center 94 (3 ~ 186) 184
5777 23:45:16.035987 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5778 23:45:16.039667 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5779 23:45:16.042499 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5780 23:45:16.045988 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5781 23:45:16.052297 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5782 23:45:16.055713 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5783 23:45:16.059031 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5784 23:45:16.062581 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5785 23:45:16.062668 ==
5786 23:45:16.065701 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 23:45:16.072343 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5788 23:45:16.072446 ==
5789 23:45:16.072526 DQS Delay:
5790 23:45:16.072600 DQS0 = 0, DQS1 = 0
5791 23:45:16.075758 DQM Delay:
5792 23:45:16.075867 DQM0 = 96, DQM1 = 87
5793 23:45:16.078945 DQ Delay:
5794 23:45:16.082453 DQ0 =98, DQ1 =90, DQ2 =88, DQ3 =92
5795 23:45:16.085660 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =94
5796 23:45:16.089182 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5797 23:45:16.092374 DQ12 =96, DQ13 =96, DQ14 =94, DQ15 =96
5798 23:45:16.092460
5799 23:45:16.092526
5800 23:45:16.099721 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5801 23:45:16.102360 CH1 RK1: MR19=505, MR18=2323
5802 23:45:16.109353 CH1_RK1: MR19=0x505, MR18=0x2323, DQSOSC=410, MR23=63, INC=64, DEC=42
5803 23:45:16.112284 [RxdqsGatingPostProcess] freq 933
5804 23:45:16.115736 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5805 23:45:16.119318 Pre-setting of DQS Precalculation
5806 23:45:16.125573 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5807 23:45:16.132196 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5808 23:45:16.139113 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5809 23:45:16.139539
5810 23:45:16.139860
5811 23:45:16.142196 [Calibration Summary] 1866 Mbps
5812 23:45:16.142678 CH 0, Rank 0
5813 23:45:16.145520 SW Impedance : PASS
5814 23:45:16.149077 DUTY Scan : NO K
5815 23:45:16.149585 ZQ Calibration : PASS
5816 23:45:16.152286 Jitter Meter : NO K
5817 23:45:16.155854 CBT Training : PASS
5818 23:45:16.156269 Write leveling : PASS
5819 23:45:16.159084 RX DQS gating : PASS
5820 23:45:16.162383 RX DQ/DQS(RDDQC) : PASS
5821 23:45:16.162801 TX DQ/DQS : PASS
5822 23:45:16.165430 RX DATLAT : PASS
5823 23:45:16.165511 RX DQ/DQS(Engine): PASS
5824 23:45:16.168754 TX OE : NO K
5825 23:45:16.168835 All Pass.
5826 23:45:16.168898
5827 23:45:16.172247 CH 0, Rank 1
5828 23:45:16.172328 SW Impedance : PASS
5829 23:45:16.175361 DUTY Scan : NO K
5830 23:45:16.178667 ZQ Calibration : PASS
5831 23:45:16.178760 Jitter Meter : NO K
5832 23:45:16.182617 CBT Training : PASS
5833 23:45:16.185343 Write leveling : PASS
5834 23:45:16.185423 RX DQS gating : PASS
5835 23:45:16.188704 RX DQ/DQS(RDDQC) : PASS
5836 23:45:16.192148 TX DQ/DQS : PASS
5837 23:45:16.192234 RX DATLAT : PASS
5838 23:45:16.195854 RX DQ/DQS(Engine): PASS
5839 23:45:16.198929 TX OE : NO K
5840 23:45:16.199346 All Pass.
5841 23:45:16.199672
5842 23:45:16.199977 CH 1, Rank 0
5843 23:45:16.202497 SW Impedance : PASS
5844 23:45:16.205766 DUTY Scan : NO K
5845 23:45:16.206178 ZQ Calibration : PASS
5846 23:45:16.208896 Jitter Meter : NO K
5847 23:45:16.212583 CBT Training : PASS
5848 23:45:16.212998 Write leveling : PASS
5849 23:45:16.215467 RX DQS gating : PASS
5850 23:45:16.215882 RX DQ/DQS(RDDQC) : PASS
5851 23:45:16.219143 TX DQ/DQS : PASS
5852 23:45:16.222382 RX DATLAT : PASS
5853 23:45:16.222795 RX DQ/DQS(Engine): PASS
5854 23:45:16.225602 TX OE : NO K
5855 23:45:16.226019 All Pass.
5856 23:45:16.226342
5857 23:45:16.229035 CH 1, Rank 1
5858 23:45:16.229491 SW Impedance : PASS
5859 23:45:16.232201 DUTY Scan : NO K
5860 23:45:16.235492 ZQ Calibration : PASS
5861 23:45:16.235907 Jitter Meter : NO K
5862 23:45:16.239086 CBT Training : PASS
5863 23:45:16.241961 Write leveling : PASS
5864 23:45:16.242374 RX DQS gating : PASS
5865 23:45:16.245590 RX DQ/DQS(RDDQC) : PASS
5866 23:45:16.248705 TX DQ/DQS : PASS
5867 23:45:16.249166 RX DATLAT : PASS
5868 23:45:16.251954 RX DQ/DQS(Engine): PASS
5869 23:45:16.255144 TX OE : NO K
5870 23:45:16.255562 All Pass.
5871 23:45:16.255889
5872 23:45:16.258620 DramC Write-DBI off
5873 23:45:16.259032 PER_BANK_REFRESH: Hybrid Mode
5874 23:45:16.261869 TX_TRACKING: ON
5875 23:45:16.268420 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5876 23:45:16.275227 [FAST_K] Save calibration result to emmc
5877 23:45:16.278545 dramc_set_vcore_voltage set vcore to 650000
5878 23:45:16.278956 Read voltage for 400, 6
5879 23:45:16.281782 Vio18 = 0
5880 23:45:16.282194 Vcore = 650000
5881 23:45:16.282518 Vdram = 0
5882 23:45:16.284877 Vddq = 0
5883 23:45:16.285314 Vmddr = 0
5884 23:45:16.288299 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5885 23:45:16.295178 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5886 23:45:16.298260 MEM_TYPE=3, freq_sel=20
5887 23:45:16.301406 sv_algorithm_assistance_LP4_800
5888 23:45:16.304875 ============ PULL DRAM RESETB DOWN ============
5889 23:45:16.308528 ========== PULL DRAM RESETB DOWN end =========
5890 23:45:16.311718 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5891 23:45:16.318135 ===================================
5892 23:45:16.318545 LPDDR4 DRAM CONFIGURATION
5893 23:45:16.321575 ===================================
5894 23:45:16.324796 EX_ROW_EN[0] = 0x0
5895 23:45:16.325204 EX_ROW_EN[1] = 0x0
5896 23:45:16.328258 LP4Y_EN = 0x0
5897 23:45:16.328665 WORK_FSP = 0x0
5898 23:45:16.331451 WL = 0x2
5899 23:45:16.331873 RL = 0x2
5900 23:45:16.334586 BL = 0x2
5901 23:45:16.338100 RPST = 0x0
5902 23:45:16.338517 RD_PRE = 0x0
5903 23:45:16.341026 WR_PRE = 0x1
5904 23:45:16.341484 WR_PST = 0x0
5905 23:45:16.344467 DBI_WR = 0x0
5906 23:45:16.344881 DBI_RD = 0x0
5907 23:45:16.347652 OTF = 0x1
5908 23:45:16.351262 ===================================
5909 23:45:16.354314 ===================================
5910 23:45:16.354734 ANA top config
5911 23:45:16.357976 ===================================
5912 23:45:16.361138 DLL_ASYNC_EN = 0
5913 23:45:16.364819 ALL_SLAVE_EN = 1
5914 23:45:16.365235 NEW_RANK_MODE = 1
5915 23:45:16.367730 DLL_IDLE_MODE = 1
5916 23:45:16.370902 LP45_APHY_COMB_EN = 1
5917 23:45:16.374211 TX_ODT_DIS = 1
5918 23:45:16.377426 NEW_8X_MODE = 1
5919 23:45:16.380796 ===================================
5920 23:45:16.384130 ===================================
5921 23:45:16.384636 data_rate = 800
5922 23:45:16.387530 CKR = 1
5923 23:45:16.390896 DQ_P2S_RATIO = 4
5924 23:45:16.393965 ===================================
5925 23:45:16.397381 CA_P2S_RATIO = 4
5926 23:45:16.400641 DQ_CA_OPEN = 0
5927 23:45:16.404163 DQ_SEMI_OPEN = 1
5928 23:45:16.404652 CA_SEMI_OPEN = 1
5929 23:45:16.407232 CA_FULL_RATE = 0
5930 23:45:16.411075 DQ_CKDIV4_EN = 0
5931 23:45:16.413828 CA_CKDIV4_EN = 1
5932 23:45:16.417097 CA_PREDIV_EN = 0
5933 23:45:16.420818 PH8_DLY = 0
5934 23:45:16.421232 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5935 23:45:16.423681 DQ_AAMCK_DIV = 0
5936 23:45:16.427254 CA_AAMCK_DIV = 0
5937 23:45:16.430708 CA_ADMCK_DIV = 4
5938 23:45:16.434080 DQ_TRACK_CA_EN = 0
5939 23:45:16.437201 CA_PICK = 800
5940 23:45:16.440394 CA_MCKIO = 400
5941 23:45:16.440824 MCKIO_SEMI = 400
5942 23:45:16.443811 PLL_FREQ = 3016
5943 23:45:16.446833 DQ_UI_PI_RATIO = 32
5944 23:45:16.450267 CA_UI_PI_RATIO = 32
5945 23:45:16.453394 ===================================
5946 23:45:16.457039 ===================================
5947 23:45:16.460394 memory_type:LPDDR4
5948 23:45:16.460805 GP_NUM : 10
5949 23:45:16.463312 SRAM_EN : 1
5950 23:45:16.466665 MD32_EN : 0
5951 23:45:16.469959 ===================================
5952 23:45:16.470371 [ANA_INIT] >>>>>>>>>>>>>>
5953 23:45:16.473615 <<<<<< [CONFIGURE PHASE]: ANA_TX
5954 23:45:16.476485 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5955 23:45:16.480217 ===================================
5956 23:45:16.483229 data_rate = 800,PCW = 0X7400
5957 23:45:16.486689 ===================================
5958 23:45:16.489622 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5959 23:45:16.496353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5960 23:45:16.506262 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5961 23:45:16.513054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5962 23:45:16.516170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5963 23:45:16.519443 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5964 23:45:16.519897 [ANA_INIT] flow start
5965 23:45:16.522904 [ANA_INIT] PLL >>>>>>>>
5966 23:45:16.525947 [ANA_INIT] PLL <<<<<<<<
5967 23:45:16.526376 [ANA_INIT] MIDPI >>>>>>>>
5968 23:45:16.529809 [ANA_INIT] MIDPI <<<<<<<<
5969 23:45:16.532776 [ANA_INIT] DLL >>>>>>>>
5970 23:45:16.533216 [ANA_INIT] flow end
5971 23:45:16.539278 ============ LP4 DIFF to SE enter ============
5972 23:45:16.542577 ============ LP4 DIFF to SE exit ============
5973 23:45:16.546090 [ANA_INIT] <<<<<<<<<<<<<
5974 23:45:16.549357 [Flow] Enable top DCM control >>>>>
5975 23:45:16.552794 [Flow] Enable top DCM control <<<<<
5976 23:45:16.553209 Enable DLL master slave shuffle
5977 23:45:16.559216 ==============================================================
5978 23:45:16.562670 Gating Mode config
5979 23:45:16.565835 ==============================================================
5980 23:45:16.569255 Config description:
5981 23:45:16.579224 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5982 23:45:16.585601 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5983 23:45:16.589350 SELPH_MODE 0: By rank 1: By Phase
5984 23:45:16.595677 ==============================================================
5985 23:45:16.599069 GAT_TRACK_EN = 0
5986 23:45:16.602347 RX_GATING_MODE = 2
5987 23:45:16.605978 RX_GATING_TRACK_MODE = 2
5988 23:45:16.609325 SELPH_MODE = 1
5989 23:45:16.609758 PICG_EARLY_EN = 1
5990 23:45:16.612268 VALID_LAT_VALUE = 1
5991 23:45:16.618824 ==============================================================
5992 23:45:16.622345 Enter into Gating configuration >>>>
5993 23:45:16.625624 Exit from Gating configuration <<<<
5994 23:45:16.629024 Enter into DVFS_PRE_config >>>>>
5995 23:45:16.639008 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5996 23:45:16.642035 Exit from DVFS_PRE_config <<<<<
5997 23:45:16.645389 Enter into PICG configuration >>>>
5998 23:45:16.648817 Exit from PICG configuration <<<<
5999 23:45:16.651968 [RX_INPUT] configuration >>>>>
6000 23:45:16.655280 [RX_INPUT] configuration <<<<<
6001 23:45:16.658731 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6002 23:45:16.665158 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6003 23:45:16.671978 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6004 23:45:16.678850 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6005 23:45:16.685418 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6006 23:45:16.691752 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6007 23:45:16.695353 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6008 23:45:16.698680 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6009 23:45:16.701756 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6010 23:45:16.708323 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6011 23:45:16.711653 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6012 23:45:16.714680 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6013 23:45:16.718133 ===================================
6014 23:45:16.721604 LPDDR4 DRAM CONFIGURATION
6015 23:45:16.724592 ===================================
6016 23:45:16.725007 EX_ROW_EN[0] = 0x0
6017 23:45:16.727938 EX_ROW_EN[1] = 0x0
6018 23:45:16.731541 LP4Y_EN = 0x0
6019 23:45:16.731957 WORK_FSP = 0x0
6020 23:45:16.734662 WL = 0x2
6021 23:45:16.735077 RL = 0x2
6022 23:45:16.737905 BL = 0x2
6023 23:45:16.738320 RPST = 0x0
6024 23:45:16.741207 RD_PRE = 0x0
6025 23:45:16.741663 WR_PRE = 0x1
6026 23:45:16.744511 WR_PST = 0x0
6027 23:45:16.744956 DBI_WR = 0x0
6028 23:45:16.747623 DBI_RD = 0x0
6029 23:45:16.748036 OTF = 0x1
6030 23:45:16.751146 ===================================
6031 23:45:16.754413 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6032 23:45:16.761034 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6033 23:45:16.764806 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6034 23:45:16.768210 ===================================
6035 23:45:16.770861 LPDDR4 DRAM CONFIGURATION
6036 23:45:16.774059 ===================================
6037 23:45:16.774494 EX_ROW_EN[0] = 0x10
6038 23:45:16.777694 EX_ROW_EN[1] = 0x0
6039 23:45:16.781272 LP4Y_EN = 0x0
6040 23:45:16.781721 WORK_FSP = 0x0
6041 23:45:16.784289 WL = 0x2
6042 23:45:16.784700 RL = 0x2
6043 23:45:16.787444 BL = 0x2
6044 23:45:16.787858 RPST = 0x0
6045 23:45:16.790880 RD_PRE = 0x0
6046 23:45:16.791294 WR_PRE = 0x1
6047 23:45:16.794082 WR_PST = 0x0
6048 23:45:16.794516 DBI_WR = 0x0
6049 23:45:16.797341 DBI_RD = 0x0
6050 23:45:16.797773 OTF = 0x1
6051 23:45:16.800755 ===================================
6052 23:45:16.807204 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6053 23:45:16.811557 nWR fixed to 30
6054 23:45:16.815258 [ModeRegInit_LP4] CH0 RK0
6055 23:45:16.815685 [ModeRegInit_LP4] CH0 RK1
6056 23:45:16.818086 [ModeRegInit_LP4] CH1 RK0
6057 23:45:16.821514 [ModeRegInit_LP4] CH1 RK1
6058 23:45:16.821944 match AC timing 18
6059 23:45:16.828032 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6060 23:45:16.831179 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6061 23:45:16.834917 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6062 23:45:16.841489 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6063 23:45:16.844531 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6064 23:45:16.845008 ==
6065 23:45:16.847792 Dram Type= 6, Freq= 0, CH_0, rank 0
6066 23:45:16.851140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6067 23:45:16.851571 ==
6068 23:45:16.857865 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6069 23:45:16.864429 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6070 23:45:16.867822 [CA 0] Center 36 (8~64) winsize 57
6071 23:45:16.870861 [CA 1] Center 36 (8~64) winsize 57
6072 23:45:16.874346 [CA 2] Center 36 (8~64) winsize 57
6073 23:45:16.877483 [CA 3] Center 36 (8~64) winsize 57
6074 23:45:16.881392 [CA 4] Center 36 (8~64) winsize 57
6075 23:45:16.881839 [CA 5] Center 36 (8~64) winsize 57
6076 23:45:16.884129
6077 23:45:16.887477 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6078 23:45:16.887907
6079 23:45:16.890784 [CATrainingPosCal] consider 1 rank data
6080 23:45:16.894271 u2DelayCellTimex100 = 270/100 ps
6081 23:45:16.897725 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6082 23:45:16.901098 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6083 23:45:16.904292 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6084 23:45:16.907374 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6085 23:45:16.910606 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6086 23:45:16.914114 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6087 23:45:16.914543
6088 23:45:16.917386 CA PerBit enable=1, Macro0, CA PI delay=36
6089 23:45:16.917821
6090 23:45:16.920643 [CBTSetCACLKResult] CA Dly = 36
6091 23:45:16.923657 CS Dly: 1 (0~32)
6092 23:45:16.923740 ==
6093 23:45:16.926842 Dram Type= 6, Freq= 0, CH_0, rank 1
6094 23:45:16.930529 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6095 23:45:16.930614 ==
6096 23:45:16.937000 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6097 23:45:16.943296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6098 23:45:16.946635 [CA 0] Center 36 (8~64) winsize 57
6099 23:45:16.950271 [CA 1] Center 36 (8~64) winsize 57
6100 23:45:16.950380 [CA 2] Center 36 (8~64) winsize 57
6101 23:45:16.953322 [CA 3] Center 36 (8~64) winsize 57
6102 23:45:16.956863 [CA 4] Center 36 (8~64) winsize 57
6103 23:45:16.960028 [CA 5] Center 36 (8~64) winsize 57
6104 23:45:16.960160
6105 23:45:16.963515 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6106 23:45:16.963664
6107 23:45:16.970088 [CATrainingPosCal] consider 2 rank data
6108 23:45:16.970256 u2DelayCellTimex100 = 270/100 ps
6109 23:45:16.973257 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6110 23:45:16.980050 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6111 23:45:16.983412 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6112 23:45:16.986663 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6113 23:45:16.990232 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6114 23:45:16.993472 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6115 23:45:16.993908
6116 23:45:16.996789 CA PerBit enable=1, Macro0, CA PI delay=36
6117 23:45:16.997220
6118 23:45:16.999994 [CBTSetCACLKResult] CA Dly = 36
6119 23:45:17.003612 CS Dly: 1 (0~32)
6120 23:45:17.004040
6121 23:45:17.006865 ----->DramcWriteLeveling(PI) begin...
6122 23:45:17.007301 ==
6123 23:45:17.010726 Dram Type= 6, Freq= 0, CH_0, rank 0
6124 23:45:17.013602 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6125 23:45:17.014033 ==
6126 23:45:17.016685 Write leveling (Byte 0): 32 => 0
6127 23:45:17.020158 Write leveling (Byte 1): 32 => 0
6128 23:45:17.023192 DramcWriteLeveling(PI) end<-----
6129 23:45:17.023648
6130 23:45:17.023999 ==
6131 23:45:17.027009 Dram Type= 6, Freq= 0, CH_0, rank 0
6132 23:45:17.030369 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6133 23:45:17.030785 ==
6134 23:45:17.033223 [Gating] SW mode calibration
6135 23:45:17.039937 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6136 23:45:17.046531 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6137 23:45:17.050091 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6138 23:45:17.053387 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6139 23:45:17.059993 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6140 23:45:17.063009 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6141 23:45:17.066299 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6142 23:45:17.073160 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6143 23:45:17.076126 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6144 23:45:17.079591 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6145 23:45:17.086452 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6146 23:45:17.086883 Total UI for P1: 0, mck2ui 16
6147 23:45:17.092718 best dqsien dly found for B0: ( 0, 10, 16)
6148 23:45:17.093148 Total UI for P1: 0, mck2ui 16
6149 23:45:17.096628 best dqsien dly found for B1: ( 0, 10, 16)
6150 23:45:17.102713 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6151 23:45:17.106048 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6152 23:45:17.106476
6153 23:45:17.109573 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6154 23:45:17.113188 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6155 23:45:17.116387 [Gating] SW calibration Done
6156 23:45:17.116816 ==
6157 23:45:17.119444 Dram Type= 6, Freq= 0, CH_0, rank 0
6158 23:45:17.122888 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6159 23:45:17.123321 ==
6160 23:45:17.126180 RX Vref Scan: 0
6161 23:45:17.126609
6162 23:45:17.127040 RX Vref 0 -> 0, step: 1
6163 23:45:17.127447
6164 23:45:17.129583 RX Delay -410 -> 252, step: 16
6165 23:45:17.136107 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6166 23:45:17.139475 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6167 23:45:17.142499 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6168 23:45:17.146031 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6169 23:45:17.152458 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6170 23:45:17.155713 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6171 23:45:17.159141 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6172 23:45:17.162302 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6173 23:45:17.168860 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6174 23:45:17.172193 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6175 23:45:17.175474 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6176 23:45:17.179061 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6177 23:45:17.185217 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6178 23:45:17.188521 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6179 23:45:17.191686 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6180 23:45:17.198795 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6181 23:45:17.199211 ==
6182 23:45:17.202265 Dram Type= 6, Freq= 0, CH_0, rank 0
6183 23:45:17.205362 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6184 23:45:17.205785 ==
6185 23:45:17.206113 DQS Delay:
6186 23:45:17.208703 DQS0 = 51, DQS1 = 59
6187 23:45:17.209116 DQM Delay:
6188 23:45:17.212381 DQM0 = 12, DQM1 = 12
6189 23:45:17.212789 DQ Delay:
6190 23:45:17.215241 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6191 23:45:17.218825 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6192 23:45:17.221835 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6193 23:45:17.225213 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6194 23:45:17.225664
6195 23:45:17.225987
6196 23:45:17.226285 ==
6197 23:45:17.228466 Dram Type= 6, Freq= 0, CH_0, rank 0
6198 23:45:17.231877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6199 23:45:17.232328 ==
6200 23:45:17.232660
6201 23:45:17.232960
6202 23:45:17.235223 TX Vref Scan disable
6203 23:45:17.235633 == TX Byte 0 ==
6204 23:45:17.241782 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6205 23:45:17.245156 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6206 23:45:17.245609 == TX Byte 1 ==
6207 23:45:17.251589 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6208 23:45:17.254861 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6209 23:45:17.255275 ==
6210 23:45:17.258488 Dram Type= 6, Freq= 0, CH_0, rank 0
6211 23:45:17.261729 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6212 23:45:17.262148 ==
6213 23:45:17.262475
6214 23:45:17.265125
6215 23:45:17.265560 TX Vref Scan disable
6216 23:45:17.268469 == TX Byte 0 ==
6217 23:45:17.271354 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6218 23:45:17.275036 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6219 23:45:17.278032 == TX Byte 1 ==
6220 23:45:17.281385 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6221 23:45:17.284902 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6222 23:45:17.285391
6223 23:45:17.285728 [DATLAT]
6224 23:45:17.287963 Freq=400, CH0 RK0
6225 23:45:17.288371
6226 23:45:17.291656 DATLAT Default: 0xf
6227 23:45:17.292063 0, 0xFFFF, sum = 0
6228 23:45:17.294839 1, 0xFFFF, sum = 0
6229 23:45:17.295256 2, 0xFFFF, sum = 0
6230 23:45:17.298030 3, 0xFFFF, sum = 0
6231 23:45:17.298448 4, 0xFFFF, sum = 0
6232 23:45:17.301789 5, 0xFFFF, sum = 0
6233 23:45:17.302208 6, 0xFFFF, sum = 0
6234 23:45:17.304702 7, 0xFFFF, sum = 0
6235 23:45:17.305117 8, 0xFFFF, sum = 0
6236 23:45:17.307981 9, 0xFFFF, sum = 0
6237 23:45:17.308404 10, 0xFFFF, sum = 0
6238 23:45:17.311325 11, 0xFFFF, sum = 0
6239 23:45:17.311748 12, 0x0, sum = 1
6240 23:45:17.314776 13, 0x0, sum = 2
6241 23:45:17.315198 14, 0x0, sum = 3
6242 23:45:17.318029 15, 0x0, sum = 4
6243 23:45:17.318450 best_step = 13
6244 23:45:17.318772
6245 23:45:17.319078 ==
6246 23:45:17.321200 Dram Type= 6, Freq= 0, CH_0, rank 0
6247 23:45:17.327766 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6248 23:45:17.328185 ==
6249 23:45:17.328517 RX Vref Scan: 1
6250 23:45:17.328819
6251 23:45:17.331154 RX Vref 0 -> 0, step: 1
6252 23:45:17.331568
6253 23:45:17.334454 RX Delay -359 -> 252, step: 8
6254 23:45:17.334870
6255 23:45:17.337744 Set Vref, RX VrefLevel [Byte0]: 46
6256 23:45:17.340755 [Byte1]: 50
6257 23:45:17.341171
6258 23:45:17.344286 Final RX Vref Byte 0 = 46 to rank0
6259 23:45:17.347613 Final RX Vref Byte 1 = 50 to rank0
6260 23:45:17.351238 Final RX Vref Byte 0 = 46 to rank1
6261 23:45:17.354418 Final RX Vref Byte 1 = 50 to rank1==
6262 23:45:17.357393 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 23:45:17.361414 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6264 23:45:17.364428 ==
6265 23:45:17.364842 DQS Delay:
6266 23:45:17.365167 DQS0 = 52, DQS1 = 68
6267 23:45:17.367623 DQM Delay:
6268 23:45:17.368033 DQM0 = 8, DQM1 = 17
6269 23:45:17.371159 DQ Delay:
6270 23:45:17.371577 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6271 23:45:17.374209 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6272 23:45:17.377558 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6273 23:45:17.381205 DQ12 =28, DQ13 =24, DQ14 =28, DQ15 =28
6274 23:45:17.381655
6275 23:45:17.381974
6276 23:45:17.390933 [DQSOSCAuto] RK0, (LSB)MR18= 0xa1a1, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6277 23:45:17.393862 CH0 RK0: MR19=C0C, MR18=A1A1
6278 23:45:17.397331 CH0_RK0: MR19=0xC0C, MR18=0xA1A1, DQSOSC=389, MR23=63, INC=390, DEC=260
6279 23:45:17.400683 ==
6280 23:45:17.404157 Dram Type= 6, Freq= 0, CH_0, rank 1
6281 23:45:17.407609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6282 23:45:17.408032 ==
6283 23:45:17.410833 [Gating] SW mode calibration
6284 23:45:17.417745 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6285 23:45:17.420854 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6286 23:45:17.427379 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6287 23:45:17.430420 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6288 23:45:17.433831 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 23:45:17.440399 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
6290 23:45:17.443904 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6291 23:45:17.446953 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6292 23:45:17.453748 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6293 23:45:17.456979 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6294 23:45:17.460296 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6295 23:45:17.463900 Total UI for P1: 0, mck2ui 16
6296 23:45:17.467109 best dqsien dly found for B0: ( 0, 10, 16)
6297 23:45:17.469744 Total UI for P1: 0, mck2ui 16
6298 23:45:17.473154 best dqsien dly found for B1: ( 0, 10, 16)
6299 23:45:17.476591 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6300 23:45:17.479594 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6301 23:45:17.483195
6302 23:45:17.486327 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6303 23:45:17.489927 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6304 23:45:17.492781 [Gating] SW calibration Done
6305 23:45:17.492874 ==
6306 23:45:17.496471 Dram Type= 6, Freq= 0, CH_0, rank 1
6307 23:45:17.499698 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6308 23:45:17.499808 ==
6309 23:45:17.503148 RX Vref Scan: 0
6310 23:45:17.503267
6311 23:45:17.503361 RX Vref 0 -> 0, step: 1
6312 23:45:17.503450
6313 23:45:17.506442 RX Delay -410 -> 252, step: 16
6314 23:45:17.509692 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6315 23:45:17.516330 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6316 23:45:17.519574 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6317 23:45:17.522890 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6318 23:45:17.526044 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6319 23:45:17.532689 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6320 23:45:17.536045 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6321 23:45:17.539464 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6322 23:45:17.542746 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6323 23:45:17.549582 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6324 23:45:17.553187 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6325 23:45:17.556183 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6326 23:45:17.559287 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6327 23:45:17.566040 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6328 23:45:17.569452 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6329 23:45:17.572773 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6330 23:45:17.573192 ==
6331 23:45:17.576169 Dram Type= 6, Freq= 0, CH_0, rank 1
6332 23:45:17.582640 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6333 23:45:17.583057 ==
6334 23:45:17.583381 DQS Delay:
6335 23:45:17.586102 DQS0 = 43, DQS1 = 59
6336 23:45:17.586550 DQM Delay:
6337 23:45:17.586875 DQM0 = 7, DQM1 = 15
6338 23:45:17.589485 DQ Delay:
6339 23:45:17.592557 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6340 23:45:17.593033 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6341 23:45:17.596148 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6342 23:45:17.599261 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6343 23:45:17.599673
6344 23:45:17.602874
6345 23:45:17.603285 ==
6346 23:45:17.605892 Dram Type= 6, Freq= 0, CH_0, rank 1
6347 23:45:17.608961 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6348 23:45:17.609409 ==
6349 23:45:17.609762
6350 23:45:17.610106
6351 23:45:17.612385 TX Vref Scan disable
6352 23:45:17.612793 == TX Byte 0 ==
6353 23:45:17.615730 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6354 23:45:17.622295 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6355 23:45:17.622707 == TX Byte 1 ==
6356 23:45:17.625587 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6357 23:45:17.632103 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6358 23:45:17.632544 ==
6359 23:45:17.635254 Dram Type= 6, Freq= 0, CH_0, rank 1
6360 23:45:17.638686 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6361 23:45:17.639097 ==
6362 23:45:17.639415
6363 23:45:17.639710
6364 23:45:17.641942 TX Vref Scan disable
6365 23:45:17.642347 == TX Byte 0 ==
6366 23:45:17.648837 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6367 23:45:17.651792 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6368 23:45:17.652207 == TX Byte 1 ==
6369 23:45:17.655186 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6370 23:45:17.661844 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6371 23:45:17.662137
6372 23:45:17.662366 [DATLAT]
6373 23:45:17.665105 Freq=400, CH0 RK1
6374 23:45:17.665383
6375 23:45:17.665561 DATLAT Default: 0xd
6376 23:45:17.668247 0, 0xFFFF, sum = 0
6377 23:45:17.668437 1, 0xFFFF, sum = 0
6378 23:45:17.671518 2, 0xFFFF, sum = 0
6379 23:45:17.671787 3, 0xFFFF, sum = 0
6380 23:45:17.675240 4, 0xFFFF, sum = 0
6381 23:45:17.675669 5, 0xFFFF, sum = 0
6382 23:45:17.678452 6, 0xFFFF, sum = 0
6383 23:45:17.678938 7, 0xFFFF, sum = 0
6384 23:45:17.681970 8, 0xFFFF, sum = 0
6385 23:45:17.682580 9, 0xFFFF, sum = 0
6386 23:45:17.685185 10, 0xFFFF, sum = 0
6387 23:45:17.685731 11, 0xFFFF, sum = 0
6388 23:45:17.688061 12, 0x0, sum = 1
6389 23:45:17.688515 13, 0x0, sum = 2
6390 23:45:17.691813 14, 0x0, sum = 3
6391 23:45:17.692231 15, 0x0, sum = 4
6392 23:45:17.695346 best_step = 13
6393 23:45:17.695755
6394 23:45:17.696079 ==
6395 23:45:17.698398 Dram Type= 6, Freq= 0, CH_0, rank 1
6396 23:45:17.701361 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6397 23:45:17.701778 ==
6398 23:45:17.704775 RX Vref Scan: 0
6399 23:45:17.705265
6400 23:45:17.705636 RX Vref 0 -> 0, step: 1
6401 23:45:17.705930
6402 23:45:17.707960 RX Delay -359 -> 252, step: 8
6403 23:45:17.716536 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6404 23:45:17.719765 iDelay=217, Bit 1, Center -40 (-295 ~ 216) 512
6405 23:45:17.722927 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6406 23:45:17.729273 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6407 23:45:17.732705 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6408 23:45:17.735980 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6409 23:45:17.739567 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6410 23:45:17.746232 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6411 23:45:17.749633 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6412 23:45:17.752675 iDelay=217, Bit 9, Center -64 (-311 ~ 184) 496
6413 23:45:17.756187 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6414 23:45:17.763042 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6415 23:45:17.766108 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6416 23:45:17.768795 iDelay=217, Bit 13, Center -48 (-295 ~ 200) 496
6417 23:45:17.772761 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6418 23:45:17.779252 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6419 23:45:17.779346 ==
6420 23:45:17.782279 Dram Type= 6, Freq= 0, CH_0, rank 1
6421 23:45:17.785652 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6422 23:45:17.785733 ==
6423 23:45:17.785795 DQS Delay:
6424 23:45:17.789048 DQS0 = 52, DQS1 = 64
6425 23:45:17.789133 DQM Delay:
6426 23:45:17.792568 DQM0 = 10, DQM1 = 13
6427 23:45:17.792666 DQ Delay:
6428 23:45:17.795623 DQ0 =4, DQ1 =12, DQ2 =8, DQ3 =4
6429 23:45:17.799070 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6430 23:45:17.802101 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6431 23:45:17.805412 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =24
6432 23:45:17.805520
6433 23:45:17.805604
6434 23:45:17.812254 [DQSOSCAuto] RK1, (LSB)MR18= 0xbcbc, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6435 23:45:17.815529 CH0 RK1: MR19=C0C, MR18=BCBC
6436 23:45:17.822164 CH0_RK1: MR19=0xC0C, MR18=0xBCBC, DQSOSC=386, MR23=63, INC=396, DEC=264
6437 23:45:17.825282 [RxdqsGatingPostProcess] freq 400
6438 23:45:17.831847 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6439 23:45:17.835200 Pre-setting of DQS Precalculation
6440 23:45:17.838952 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6441 23:45:17.839370 ==
6442 23:45:17.842243 Dram Type= 6, Freq= 0, CH_1, rank 0
6443 23:45:17.845337 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6444 23:45:17.845755 ==
6445 23:45:17.852165 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6446 23:45:17.858720 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6447 23:45:17.861939 [CA 0] Center 36 (8~64) winsize 57
6448 23:45:17.865445 [CA 1] Center 36 (8~64) winsize 57
6449 23:45:17.868776 [CA 2] Center 36 (8~64) winsize 57
6450 23:45:17.871997 [CA 3] Center 36 (8~64) winsize 57
6451 23:45:17.875278 [CA 4] Center 36 (8~64) winsize 57
6452 23:45:17.875694 [CA 5] Center 36 (8~64) winsize 57
6453 23:45:17.878466
6454 23:45:17.881797 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6455 23:45:17.882214
6456 23:45:17.885371 [CATrainingPosCal] consider 1 rank data
6457 23:45:17.888481 u2DelayCellTimex100 = 270/100 ps
6458 23:45:17.891843 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6459 23:45:17.895248 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6460 23:45:17.898625 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6461 23:45:17.901753 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6462 23:45:17.905802 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6463 23:45:17.908700 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6464 23:45:17.909157
6465 23:45:17.911795 CA PerBit enable=1, Macro0, CA PI delay=36
6466 23:45:17.912210
6467 23:45:17.915539 [CBTSetCACLKResult] CA Dly = 36
6468 23:45:17.918480 CS Dly: 1 (0~32)
6469 23:45:17.918896 ==
6470 23:45:17.921630 Dram Type= 6, Freq= 0, CH_1, rank 1
6471 23:45:17.925042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6472 23:45:17.925490 ==
6473 23:45:17.931711 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6474 23:45:17.938180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6475 23:45:17.941247 [CA 0] Center 36 (8~64) winsize 57
6476 23:45:17.944701 [CA 1] Center 36 (8~64) winsize 57
6477 23:45:17.945116 [CA 2] Center 36 (8~64) winsize 57
6478 23:45:17.948302 [CA 3] Center 36 (8~64) winsize 57
6479 23:45:17.951395 [CA 4] Center 36 (8~64) winsize 57
6480 23:45:17.954932 [CA 5] Center 36 (8~64) winsize 57
6481 23:45:17.955348
6482 23:45:17.958051 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6483 23:45:17.958469
6484 23:45:17.964991 [CATrainingPosCal] consider 2 rank data
6485 23:45:17.965438 u2DelayCellTimex100 = 270/100 ps
6486 23:45:17.968241 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6487 23:45:17.974617 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6488 23:45:17.977909 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6489 23:45:17.981567 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6490 23:45:17.984786 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6491 23:45:17.988015 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6492 23:45:17.988432
6493 23:45:17.991015 CA PerBit enable=1, Macro0, CA PI delay=36
6494 23:45:17.991095
6495 23:45:17.994237 [CBTSetCACLKResult] CA Dly = 36
6496 23:45:17.997628 CS Dly: 1 (0~32)
6497 23:45:17.997718
6498 23:45:18.000999 ----->DramcWriteLeveling(PI) begin...
6499 23:45:18.001094 ==
6500 23:45:18.004276 Dram Type= 6, Freq= 0, CH_1, rank 0
6501 23:45:18.007797 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6502 23:45:18.007899 ==
6503 23:45:18.010659 Write leveling (Byte 0): 32 => 0
6504 23:45:18.014319 Write leveling (Byte 1): 32 => 0
6505 23:45:18.017311 DramcWriteLeveling(PI) end<-----
6506 23:45:18.017434
6507 23:45:18.017529 ==
6508 23:45:18.020613 Dram Type= 6, Freq= 0, CH_1, rank 0
6509 23:45:18.024069 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6510 23:45:18.024206 ==
6511 23:45:18.027301 [Gating] SW mode calibration
6512 23:45:18.033785 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6513 23:45:18.040615 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6514 23:45:18.043722 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6515 23:45:18.047254 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6516 23:45:18.054006 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6517 23:45:18.057200 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6518 23:45:18.060402 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6519 23:45:18.067356 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6520 23:45:18.070606 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6521 23:45:18.073876 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6522 23:45:18.080485 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6523 23:45:18.080791 Total UI for P1: 0, mck2ui 16
6524 23:45:18.087184 best dqsien dly found for B0: ( 0, 10, 16)
6525 23:45:18.087423 Total UI for P1: 0, mck2ui 16
6526 23:45:18.090315 best dqsien dly found for B1: ( 0, 10, 16)
6527 23:45:18.097021 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6528 23:45:18.100381 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6529 23:45:18.100767
6530 23:45:18.104174 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6531 23:45:18.107728 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6532 23:45:18.110828 [Gating] SW calibration Done
6533 23:45:18.111305 ==
6534 23:45:18.113746 Dram Type= 6, Freq= 0, CH_1, rank 0
6535 23:45:18.117470 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6536 23:45:18.118044 ==
6537 23:45:18.120722 RX Vref Scan: 0
6538 23:45:18.121266
6539 23:45:18.121688 RX Vref 0 -> 0, step: 1
6540 23:45:18.122026
6541 23:45:18.124287 RX Delay -410 -> 252, step: 16
6542 23:45:18.130533 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6543 23:45:18.133839 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6544 23:45:18.137249 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6545 23:45:18.140573 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6546 23:45:18.147111 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6547 23:45:18.150322 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6548 23:45:18.153778 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6549 23:45:18.157386 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6550 23:45:18.163854 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6551 23:45:18.166765 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6552 23:45:18.170142 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6553 23:45:18.173726 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6554 23:45:18.179847 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6555 23:45:18.183365 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6556 23:45:18.186422 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6557 23:45:18.193447 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6558 23:45:18.193996 ==
6559 23:45:18.196420 Dram Type= 6, Freq= 0, CH_1, rank 0
6560 23:45:18.200086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6561 23:45:18.200639 ==
6562 23:45:18.201006 DQS Delay:
6563 23:45:18.202863 DQS0 = 43, DQS1 = 59
6564 23:45:18.203322 DQM Delay:
6565 23:45:18.206565 DQM0 = 6, DQM1 = 14
6566 23:45:18.207021 DQ Delay:
6567 23:45:18.209645 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6568 23:45:18.213079 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6569 23:45:18.216539 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6570 23:45:18.219832 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =32
6571 23:45:18.220387
6572 23:45:18.220747
6573 23:45:18.221081 ==
6574 23:45:18.222965 Dram Type= 6, Freq= 0, CH_1, rank 0
6575 23:45:18.226214 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6576 23:45:18.226773 ==
6577 23:45:18.227136
6578 23:45:18.227469
6579 23:45:18.229283 TX Vref Scan disable
6580 23:45:18.229773 == TX Byte 0 ==
6581 23:45:18.236803 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6582 23:45:18.239638 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6583 23:45:18.242697 == TX Byte 1 ==
6584 23:45:18.245715 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6585 23:45:18.249333 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6586 23:45:18.249806 ==
6587 23:45:18.252164 Dram Type= 6, Freq= 0, CH_1, rank 0
6588 23:45:18.256201 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6589 23:45:18.256758 ==
6590 23:45:18.258887
6591 23:45:18.259345
6592 23:45:18.259702 TX Vref Scan disable
6593 23:45:18.262340 == TX Byte 0 ==
6594 23:45:18.265660 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6595 23:45:18.269459 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6596 23:45:18.272200 == TX Byte 1 ==
6597 23:45:18.275530 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6598 23:45:18.279350 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6599 23:45:18.279903
6600 23:45:18.282222 [DATLAT]
6601 23:45:18.282678 Freq=400, CH1 RK0
6602 23:45:18.283087
6603 23:45:18.285401 DATLAT Default: 0xf
6604 23:45:18.285859 0, 0xFFFF, sum = 0
6605 23:45:18.288665 1, 0xFFFF, sum = 0
6606 23:45:18.289129 2, 0xFFFF, sum = 0
6607 23:45:18.292160 3, 0xFFFF, sum = 0
6608 23:45:18.292672 4, 0xFFFF, sum = 0
6609 23:45:18.295236 5, 0xFFFF, sum = 0
6610 23:45:18.295701 6, 0xFFFF, sum = 0
6611 23:45:18.298482 7, 0xFFFF, sum = 0
6612 23:45:18.298959 8, 0xFFFF, sum = 0
6613 23:45:18.302016 9, 0xFFFF, sum = 0
6614 23:45:18.302479 10, 0xFFFF, sum = 0
6615 23:45:18.305142 11, 0xFFFF, sum = 0
6616 23:45:18.305636 12, 0x0, sum = 1
6617 23:45:18.308464 13, 0x0, sum = 2
6618 23:45:18.308928 14, 0x0, sum = 3
6619 23:45:18.312374 15, 0x0, sum = 4
6620 23:45:18.312934 best_step = 13
6621 23:45:18.313343
6622 23:45:18.313694 ==
6623 23:45:18.315425 Dram Type= 6, Freq= 0, CH_1, rank 0
6624 23:45:18.322272 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6625 23:45:18.322829 ==
6626 23:45:18.323196 RX Vref Scan: 1
6627 23:45:18.323531
6628 23:45:18.325433 RX Vref 0 -> 0, step: 1
6629 23:45:18.325892
6630 23:45:18.328593 RX Delay -359 -> 252, step: 8
6631 23:45:18.329138
6632 23:45:18.331981 Set Vref, RX VrefLevel [Byte0]: 54
6633 23:45:18.335093 [Byte1]: 49
6634 23:45:18.338637
6635 23:45:18.339189 Final RX Vref Byte 0 = 54 to rank0
6636 23:45:18.341695 Final RX Vref Byte 1 = 49 to rank0
6637 23:45:18.345363 Final RX Vref Byte 0 = 54 to rank1
6638 23:45:18.348378 Final RX Vref Byte 1 = 49 to rank1==
6639 23:45:18.352131 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 23:45:18.358658 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6641 23:45:18.359219 ==
6642 23:45:18.359585 DQS Delay:
6643 23:45:18.361956 DQS0 = 48, DQS1 = 64
6644 23:45:18.362509 DQM Delay:
6645 23:45:18.362873 DQM0 = 8, DQM1 = 16
6646 23:45:18.364750 DQ Delay:
6647 23:45:18.368236 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6648 23:45:18.368786 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6649 23:45:18.371453 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6650 23:45:18.374879 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6651 23:45:18.375430
6652 23:45:18.377901
6653 23:45:18.384530 [DQSOSCAuto] RK0, (LSB)MR18= 0xdada, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6654 23:45:18.387645 CH1 RK0: MR19=C0C, MR18=DADA
6655 23:45:18.394883 CH1_RK0: MR19=0xC0C, MR18=0xDADA, DQSOSC=382, MR23=63, INC=404, DEC=269
6656 23:45:18.395344 ==
6657 23:45:18.397710 Dram Type= 6, Freq= 0, CH_1, rank 1
6658 23:45:18.401121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6659 23:45:18.401624 ==
6660 23:45:18.404839 [Gating] SW mode calibration
6661 23:45:18.411492 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6662 23:45:18.417985 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6663 23:45:18.421468 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 23:45:18.424971 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6665 23:45:18.431198 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 23:45:18.434099 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6667 23:45:18.437410 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 23:45:18.444389 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 23:45:18.447264 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 23:45:18.450862 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6671 23:45:18.457443 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6672 23:45:18.458000 Total UI for P1: 0, mck2ui 16
6673 23:45:18.460855 best dqsien dly found for B0: ( 0, 10, 16)
6674 23:45:18.464080 Total UI for P1: 0, mck2ui 16
6675 23:45:18.467389 best dqsien dly found for B1: ( 0, 10, 16)
6676 23:45:18.473954 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6677 23:45:18.477473 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6678 23:45:18.478022
6679 23:45:18.480879 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6680 23:45:18.483725 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6681 23:45:18.487376 [Gating] SW calibration Done
6682 23:45:18.487929 ==
6683 23:45:18.490325 Dram Type= 6, Freq= 0, CH_1, rank 1
6684 23:45:18.493434 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6685 23:45:18.493895 ==
6686 23:45:18.496811 RX Vref Scan: 0
6687 23:45:18.497319
6688 23:45:18.497694 RX Vref 0 -> 0, step: 1
6689 23:45:18.498038
6690 23:45:18.500543 RX Delay -410 -> 252, step: 16
6691 23:45:18.506852 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6692 23:45:18.510702 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6693 23:45:18.513655 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6694 23:45:18.517100 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6695 23:45:18.523413 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6696 23:45:18.527188 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6697 23:45:18.530207 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6698 23:45:18.533644 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6699 23:45:18.540312 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6700 23:45:18.543742 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6701 23:45:18.546909 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6702 23:45:18.549882 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6703 23:45:18.556552 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6704 23:45:18.560174 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6705 23:45:18.563455 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6706 23:45:18.569886 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6707 23:45:18.570447 ==
6708 23:45:18.573510 Dram Type= 6, Freq= 0, CH_1, rank 1
6709 23:45:18.576900 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6710 23:45:18.577502 ==
6711 23:45:18.577867 DQS Delay:
6712 23:45:18.579884 DQS0 = 43, DQS1 = 59
6713 23:45:18.580443 DQM Delay:
6714 23:45:18.583551 DQM0 = 10, DQM1 = 18
6715 23:45:18.584008 DQ Delay:
6716 23:45:18.586535 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6717 23:45:18.589686 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6718 23:45:18.592823 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6719 23:45:18.596063 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6720 23:45:18.596588
6721 23:45:18.597022
6722 23:45:18.597416 ==
6723 23:45:18.599448 Dram Type= 6, Freq= 0, CH_1, rank 1
6724 23:45:18.603121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6725 23:45:18.603688 ==
6726 23:45:18.604051
6727 23:45:18.604382
6728 23:45:18.606014 TX Vref Scan disable
6729 23:45:18.606471 == TX Byte 0 ==
6730 23:45:18.612611 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6731 23:45:18.616524 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6732 23:45:18.617096 == TX Byte 1 ==
6733 23:45:18.622846 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6734 23:45:18.625870 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6735 23:45:18.626433 ==
6736 23:45:18.629482 Dram Type= 6, Freq= 0, CH_1, rank 1
6737 23:45:18.632766 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6738 23:45:18.633353 ==
6739 23:45:18.633728
6740 23:45:18.634062
6741 23:45:18.635806 TX Vref Scan disable
6742 23:45:18.636262 == TX Byte 0 ==
6743 23:45:18.642390 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6744 23:45:18.645648 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6745 23:45:18.646252 == TX Byte 1 ==
6746 23:45:18.652666 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6747 23:45:18.655558 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6748 23:45:18.656021
6749 23:45:18.656383 [DATLAT]
6750 23:45:18.659404 Freq=400, CH1 RK1
6751 23:45:18.659955
6752 23:45:18.660316 DATLAT Default: 0xd
6753 23:45:18.662458 0, 0xFFFF, sum = 0
6754 23:45:18.663015 1, 0xFFFF, sum = 0
6755 23:45:18.665788 2, 0xFFFF, sum = 0
6756 23:45:18.666352 3, 0xFFFF, sum = 0
6757 23:45:18.669073 4, 0xFFFF, sum = 0
6758 23:45:18.669670 5, 0xFFFF, sum = 0
6759 23:45:18.672652 6, 0xFFFF, sum = 0
6760 23:45:18.675860 7, 0xFFFF, sum = 0
6761 23:45:18.676420 8, 0xFFFF, sum = 0
6762 23:45:18.679230 9, 0xFFFF, sum = 0
6763 23:45:18.679819 10, 0xFFFF, sum = 0
6764 23:45:18.682121 11, 0xFFFF, sum = 0
6765 23:45:18.682585 12, 0x0, sum = 1
6766 23:45:18.685325 13, 0x0, sum = 2
6767 23:45:18.685800 14, 0x0, sum = 3
6768 23:45:18.689036 15, 0x0, sum = 4
6769 23:45:18.689554 best_step = 13
6770 23:45:18.689923
6771 23:45:18.690257 ==
6772 23:45:18.692097 Dram Type= 6, Freq= 0, CH_1, rank 1
6773 23:45:18.695361 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6774 23:45:18.695821 ==
6775 23:45:18.698550 RX Vref Scan: 0
6776 23:45:18.699003
6777 23:45:18.702838 RX Vref 0 -> 0, step: 1
6778 23:45:18.703387
6779 23:45:18.703750 RX Delay -359 -> 252, step: 8
6780 23:45:18.710907 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6781 23:45:18.713878 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6782 23:45:18.717727 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6783 23:45:18.724091 iDelay=225, Bit 3, Center -44 (-287 ~ 200) 488
6784 23:45:18.727073 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6785 23:45:18.730490 iDelay=225, Bit 5, Center -24 (-271 ~ 224) 496
6786 23:45:18.734312 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6787 23:45:18.740644 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6788 23:45:18.744017 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6789 23:45:18.747154 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6790 23:45:18.750302 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6791 23:45:18.756878 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6792 23:45:18.760074 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6793 23:45:18.763828 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6794 23:45:18.766843 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6795 23:45:18.774045 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6796 23:45:18.774602 ==
6797 23:45:18.776854 Dram Type= 6, Freq= 0, CH_1, rank 1
6798 23:45:18.780415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6799 23:45:18.780876 ==
6800 23:45:18.781236 DQS Delay:
6801 23:45:18.783518 DQS0 = 48, DQS1 = 64
6802 23:45:18.784178 DQM Delay:
6803 23:45:18.787082 DQM0 = 9, DQM1 = 15
6804 23:45:18.787536 DQ Delay:
6805 23:45:18.790154 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6806 23:45:18.793821 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6807 23:45:18.796699 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6808 23:45:18.799921 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6809 23:45:18.800379
6810 23:45:18.800852
6811 23:45:18.806730 [DQSOSCAuto] RK1, (LSB)MR18= 0xb8b8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6812 23:45:18.810190 CH1 RK1: MR19=C0C, MR18=B8B8
6813 23:45:18.816986 CH1_RK1: MR19=0xC0C, MR18=0xB8B8, DQSOSC=386, MR23=63, INC=396, DEC=264
6814 23:45:18.819854 [RxdqsGatingPostProcess] freq 400
6815 23:45:18.826645 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6816 23:45:18.827216 Pre-setting of DQS Precalculation
6817 23:45:18.833105 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6818 23:45:18.839860 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6819 23:45:18.846506 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6820 23:45:18.847049
6821 23:45:18.847412
6822 23:45:18.849602 [Calibration Summary] 800 Mbps
6823 23:45:18.852834 CH 0, Rank 0
6824 23:45:18.853617 SW Impedance : PASS
6825 23:45:18.856259 DUTY Scan : NO K
6826 23:45:18.859671 ZQ Calibration : PASS
6827 23:45:18.860129 Jitter Meter : NO K
6828 23:45:18.863100 CBT Training : PASS
6829 23:45:18.866380 Write leveling : PASS
6830 23:45:18.866884 RX DQS gating : PASS
6831 23:45:18.869817 RX DQ/DQS(RDDQC) : PASS
6832 23:45:18.873361 TX DQ/DQS : PASS
6833 23:45:18.873911 RX DATLAT : PASS
6834 23:45:18.876127 RX DQ/DQS(Engine): PASS
6835 23:45:18.876850 TX OE : NO K
6836 23:45:18.879649 All Pass.
6837 23:45:18.880104
6838 23:45:18.880459 CH 0, Rank 1
6839 23:45:18.882783 SW Impedance : PASS
6840 23:45:18.883468 DUTY Scan : NO K
6841 23:45:18.886142 ZQ Calibration : PASS
6842 23:45:18.889338 Jitter Meter : NO K
6843 23:45:18.889801 CBT Training : PASS
6844 23:45:18.892693 Write leveling : NO K
6845 23:45:18.896033 RX DQS gating : PASS
6846 23:45:18.896491 RX DQ/DQS(RDDQC) : PASS
6847 23:45:18.899376 TX DQ/DQS : PASS
6848 23:45:18.902797 RX DATLAT : PASS
6849 23:45:18.903347 RX DQ/DQS(Engine): PASS
6850 23:45:18.906010 TX OE : NO K
6851 23:45:18.906470 All Pass.
6852 23:45:18.906831
6853 23:45:18.909600 CH 1, Rank 0
6854 23:45:18.910057 SW Impedance : PASS
6855 23:45:18.912831 DUTY Scan : NO K
6856 23:45:18.916468 ZQ Calibration : PASS
6857 23:45:18.917017 Jitter Meter : NO K
6858 23:45:18.919417 CBT Training : PASS
6859 23:45:18.922913 Write leveling : PASS
6860 23:45:18.923469 RX DQS gating : PASS
6861 23:45:18.925749 RX DQ/DQS(RDDQC) : PASS
6862 23:45:18.929109 TX DQ/DQS : PASS
6863 23:45:18.929607 RX DATLAT : PASS
6864 23:45:18.932701 RX DQ/DQS(Engine): PASS
6865 23:45:18.933249 TX OE : NO K
6866 23:45:18.935852 All Pass.
6867 23:45:18.936307
6868 23:45:18.936662 CH 1, Rank 1
6869 23:45:18.939048 SW Impedance : PASS
6870 23:45:18.942328 DUTY Scan : NO K
6871 23:45:18.942891 ZQ Calibration : PASS
6872 23:45:18.945895 Jitter Meter : NO K
6873 23:45:18.946355 CBT Training : PASS
6874 23:45:18.949451 Write leveling : NO K
6875 23:45:18.952552 RX DQS gating : PASS
6876 23:45:18.953100 RX DQ/DQS(RDDQC) : PASS
6877 23:45:18.955494 TX DQ/DQS : PASS
6878 23:45:18.959189 RX DATLAT : PASS
6879 23:45:18.959747 RX DQ/DQS(Engine): PASS
6880 23:45:18.962352 TX OE : NO K
6881 23:45:18.962905 All Pass.
6882 23:45:18.963270
6883 23:45:18.965839 DramC Write-DBI off
6884 23:45:18.969004 PER_BANK_REFRESH: Hybrid Mode
6885 23:45:18.969635 TX_TRACKING: ON
6886 23:45:18.978909 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6887 23:45:18.982135 [FAST_K] Save calibration result to emmc
6888 23:45:18.985566 dramc_set_vcore_voltage set vcore to 725000
6889 23:45:18.988811 Read voltage for 1600, 0
6890 23:45:18.989421 Vio18 = 0
6891 23:45:18.989905 Vcore = 725000
6892 23:45:18.992070 Vdram = 0
6893 23:45:18.992537 Vddq = 0
6894 23:45:18.993114 Vmddr = 0
6895 23:45:18.998663 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6896 23:45:19.001943 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6897 23:45:19.005371 MEM_TYPE=3, freq_sel=13
6898 23:45:19.009075 sv_algorithm_assistance_LP4_3733
6899 23:45:19.011985 ============ PULL DRAM RESETB DOWN ============
6900 23:45:19.018626 ========== PULL DRAM RESETB DOWN end =========
6901 23:45:19.022005 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6902 23:45:19.025590 ===================================
6903 23:45:19.028534 LPDDR4 DRAM CONFIGURATION
6904 23:45:19.032340 ===================================
6905 23:45:19.032896 EX_ROW_EN[0] = 0x0
6906 23:45:19.035144 EX_ROW_EN[1] = 0x0
6907 23:45:19.035696 LP4Y_EN = 0x0
6908 23:45:19.038513 WORK_FSP = 0x1
6909 23:45:19.039069 WL = 0x5
6910 23:45:19.041432 RL = 0x5
6911 23:45:19.041893 BL = 0x2
6912 23:45:19.044932 RPST = 0x0
6913 23:45:19.048287 RD_PRE = 0x0
6914 23:45:19.048760 WR_PRE = 0x1
6915 23:45:19.051553 WR_PST = 0x1
6916 23:45:19.052012 DBI_WR = 0x0
6917 23:45:19.054649 DBI_RD = 0x0
6918 23:45:19.055106 OTF = 0x1
6919 23:45:19.058399 ===================================
6920 23:45:19.061663 ===================================
6921 23:45:19.064625 ANA top config
6922 23:45:19.068507 ===================================
6923 23:45:19.069089 DLL_ASYNC_EN = 0
6924 23:45:19.071609 ALL_SLAVE_EN = 0
6925 23:45:19.075163 NEW_RANK_MODE = 1
6926 23:45:19.077927 DLL_IDLE_MODE = 1
6927 23:45:19.078474 LP45_APHY_COMB_EN = 1
6928 23:45:19.081208 TX_ODT_DIS = 0
6929 23:45:19.084449 NEW_8X_MODE = 1
6930 23:45:19.088055 ===================================
6931 23:45:19.091220 ===================================
6932 23:45:19.094331 data_rate = 3200
6933 23:45:19.097563 CKR = 1
6934 23:45:19.101022 DQ_P2S_RATIO = 8
6935 23:45:19.104759 ===================================
6936 23:45:19.105377 CA_P2S_RATIO = 8
6937 23:45:19.108080 DQ_CA_OPEN = 0
6938 23:45:19.111255 DQ_SEMI_OPEN = 0
6939 23:45:19.114894 CA_SEMI_OPEN = 0
6940 23:45:19.117679 CA_FULL_RATE = 0
6941 23:45:19.120896 DQ_CKDIV4_EN = 0
6942 23:45:19.121494 CA_CKDIV4_EN = 0
6943 23:45:19.124311 CA_PREDIV_EN = 0
6944 23:45:19.127547 PH8_DLY = 12
6945 23:45:19.130769 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6946 23:45:19.134216 DQ_AAMCK_DIV = 4
6947 23:45:19.137485 CA_AAMCK_DIV = 4
6948 23:45:19.138035 CA_ADMCK_DIV = 4
6949 23:45:19.141002 DQ_TRACK_CA_EN = 0
6950 23:45:19.144290 CA_PICK = 1600
6951 23:45:19.147590 CA_MCKIO = 1600
6952 23:45:19.150536 MCKIO_SEMI = 0
6953 23:45:19.154013 PLL_FREQ = 3068
6954 23:45:19.157664 DQ_UI_PI_RATIO = 32
6955 23:45:19.160513 CA_UI_PI_RATIO = 0
6956 23:45:19.164337 ===================================
6957 23:45:19.164890 ===================================
6958 23:45:19.167048 memory_type:LPDDR4
6959 23:45:19.170895 GP_NUM : 10
6960 23:45:19.171443 SRAM_EN : 1
6961 23:45:19.174090 MD32_EN : 0
6962 23:45:19.177619 ===================================
6963 23:45:19.180796 [ANA_INIT] >>>>>>>>>>>>>>
6964 23:45:19.184252 <<<<<< [CONFIGURE PHASE]: ANA_TX
6965 23:45:19.187270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6966 23:45:19.190619 ===================================
6967 23:45:19.191170 data_rate = 3200,PCW = 0X7600
6968 23:45:19.193585 ===================================
6969 23:45:19.197601 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6970 23:45:19.203653 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6971 23:45:19.213964 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6972 23:45:19.214517 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6973 23:45:19.217228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6974 23:45:19.220475 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6975 23:45:19.223784 [ANA_INIT] flow start
6976 23:45:19.227160 [ANA_INIT] PLL >>>>>>>>
6977 23:45:19.227709 [ANA_INIT] PLL <<<<<<<<
6978 23:45:19.229982 [ANA_INIT] MIDPI >>>>>>>>
6979 23:45:19.233695 [ANA_INIT] MIDPI <<<<<<<<
6980 23:45:19.234249 [ANA_INIT] DLL >>>>>>>>
6981 23:45:19.237149 [ANA_INIT] DLL <<<<<<<<
6982 23:45:19.240154 [ANA_INIT] flow end
6983 23:45:19.243578 ============ LP4 DIFF to SE enter ============
6984 23:45:19.246598 ============ LP4 DIFF to SE exit ============
6985 23:45:19.250448 [ANA_INIT] <<<<<<<<<<<<<
6986 23:45:19.253352 [Flow] Enable top DCM control >>>>>
6987 23:45:19.256753 [Flow] Enable top DCM control <<<<<
6988 23:45:19.260115 Enable DLL master slave shuffle
6989 23:45:19.263242 ==============================================================
6990 23:45:19.266329 Gating Mode config
6991 23:45:19.273068 ==============================================================
6992 23:45:19.273675 Config description:
6993 23:45:19.282994 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6994 23:45:19.289751 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6995 23:45:19.295964 SELPH_MODE 0: By rank 1: By Phase
6996 23:45:19.299185 ==============================================================
6997 23:45:19.302589 GAT_TRACK_EN = 1
6998 23:45:19.305754 RX_GATING_MODE = 2
6999 23:45:19.309344 RX_GATING_TRACK_MODE = 2
7000 23:45:19.312670 SELPH_MODE = 1
7001 23:45:19.315777 PICG_EARLY_EN = 1
7002 23:45:19.319108 VALID_LAT_VALUE = 1
7003 23:45:19.322286 ==============================================================
7004 23:45:19.328816 Enter into Gating configuration >>>>
7005 23:45:19.329274 Exit from Gating configuration <<<<
7006 23:45:19.332272 Enter into DVFS_PRE_config >>>>>
7007 23:45:19.345522 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7008 23:45:19.348627 Exit from DVFS_PRE_config <<<<<
7009 23:45:19.351759 Enter into PICG configuration >>>>
7010 23:45:19.355268 Exit from PICG configuration <<<<
7011 23:45:19.355427 [RX_INPUT] configuration >>>>>
7012 23:45:19.358595 [RX_INPUT] configuration <<<<<
7013 23:45:19.365141 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7014 23:45:19.368310 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7015 23:45:19.374943 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7016 23:45:19.381733 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7017 23:45:19.388130 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7018 23:45:19.394656 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7019 23:45:19.397860 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7020 23:45:19.401671 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7021 23:45:19.408183 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7022 23:45:19.411333 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7023 23:45:19.414571 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7024 23:45:19.418042 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7025 23:45:19.421162 ===================================
7026 23:45:19.424522 LPDDR4 DRAM CONFIGURATION
7027 23:45:19.428060 ===================================
7028 23:45:19.431358 EX_ROW_EN[0] = 0x0
7029 23:45:19.431442 EX_ROW_EN[1] = 0x0
7030 23:45:19.434432 LP4Y_EN = 0x0
7031 23:45:19.434515 WORK_FSP = 0x1
7032 23:45:19.438078 WL = 0x5
7033 23:45:19.438160 RL = 0x5
7034 23:45:19.440997 BL = 0x2
7035 23:45:19.441078 RPST = 0x0
7036 23:45:19.444321 RD_PRE = 0x0
7037 23:45:19.447470 WR_PRE = 0x1
7038 23:45:19.447551 WR_PST = 0x1
7039 23:45:19.450997 DBI_WR = 0x0
7040 23:45:19.451078 DBI_RD = 0x0
7041 23:45:19.454262 OTF = 0x1
7042 23:45:19.457509 ===================================
7043 23:45:19.461041 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7044 23:45:19.464132 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7045 23:45:19.467656 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7046 23:45:19.470941 ===================================
7047 23:45:19.474177 LPDDR4 DRAM CONFIGURATION
7048 23:45:19.477579 ===================================
7049 23:45:19.480658 EX_ROW_EN[0] = 0x10
7050 23:45:19.480739 EX_ROW_EN[1] = 0x0
7051 23:45:19.484600 LP4Y_EN = 0x0
7052 23:45:19.484682 WORK_FSP = 0x1
7053 23:45:19.487272 WL = 0x5
7054 23:45:19.487354 RL = 0x5
7055 23:45:19.491011 BL = 0x2
7056 23:45:19.491095 RPST = 0x0
7057 23:45:19.493894 RD_PRE = 0x0
7058 23:45:19.497137 WR_PRE = 0x1
7059 23:45:19.497243 WR_PST = 0x1
7060 23:45:19.500390 DBI_WR = 0x0
7061 23:45:19.500470 DBI_RD = 0x0
7062 23:45:19.504049 OTF = 0x1
7063 23:45:19.507225 ===================================
7064 23:45:19.510426 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7065 23:45:19.513702 ==
7066 23:45:19.516877 Dram Type= 6, Freq= 0, CH_0, rank 0
7067 23:45:19.520213 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7068 23:45:19.520294 ==
7069 23:45:19.523481 [Duty_Offset_Calibration]
7070 23:45:19.523560 B0:0 B1:2 CA:1
7071 23:45:19.523622
7072 23:45:19.526707 [DutyScan_Calibration_Flow] k_type=0
7073 23:45:19.537042
7074 23:45:19.537152 ==CLK 0==
7075 23:45:19.540284 Final CLK duty delay cell = 0
7076 23:45:19.543651 [0] MAX Duty = 5187%(X100), DQS PI = 24
7077 23:45:19.547071 [0] MIN Duty = 4938%(X100), DQS PI = 52
7078 23:45:19.547177 [0] AVG Duty = 5062%(X100)
7079 23:45:19.550396
7080 23:45:19.553584 CH0 CLK Duty spec in!! Max-Min= 249%
7081 23:45:19.557073 [DutyScan_Calibration_Flow] ====Done====
7082 23:45:19.557179
7083 23:45:19.559990 [DutyScan_Calibration_Flow] k_type=1
7084 23:45:19.576834
7085 23:45:19.576946 ==DQS 0 ==
7086 23:45:19.580098 Final DQS duty delay cell = 0
7087 23:45:19.583409 [0] MAX Duty = 5156%(X100), DQS PI = 34
7088 23:45:19.586787 [0] MIN Duty = 5031%(X100), DQS PI = 8
7089 23:45:19.586867 [0] AVG Duty = 5093%(X100)
7090 23:45:19.590251
7091 23:45:19.590332 ==DQS 1 ==
7092 23:45:19.593550 Final DQS duty delay cell = 0
7093 23:45:19.596921 [0] MAX Duty = 5031%(X100), DQS PI = 6
7094 23:45:19.600061 [0] MIN Duty = 4876%(X100), DQS PI = 18
7095 23:45:19.600142 [0] AVG Duty = 4953%(X100)
7096 23:45:19.603391
7097 23:45:19.606690 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7098 23:45:19.606797
7099 23:45:19.609959 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7100 23:45:19.613649 [DutyScan_Calibration_Flow] ====Done====
7101 23:45:19.613729
7102 23:45:19.616494 [DutyScan_Calibration_Flow] k_type=3
7103 23:45:19.633920
7104 23:45:19.634011 ==DQM 0 ==
7105 23:45:19.637210 Final DQM duty delay cell = 0
7106 23:45:19.640575 [0] MAX Duty = 5187%(X100), DQS PI = 22
7107 23:45:19.643955 [0] MIN Duty = 4907%(X100), DQS PI = 56
7108 23:45:19.647159 [0] AVG Duty = 5047%(X100)
7109 23:45:19.647239
7110 23:45:19.647302 ==DQM 1 ==
7111 23:45:19.650803 Final DQM duty delay cell = 0
7112 23:45:19.653798 [0] MAX Duty = 5031%(X100), DQS PI = 52
7113 23:45:19.657097 [0] MIN Duty = 4782%(X100), DQS PI = 16
7114 23:45:19.660427 [0] AVG Duty = 4906%(X100)
7115 23:45:19.660505
7116 23:45:19.663606 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7117 23:45:19.663685
7118 23:45:19.667093 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7119 23:45:19.670231 [DutyScan_Calibration_Flow] ====Done====
7120 23:45:19.670311
7121 23:45:19.673803 [DutyScan_Calibration_Flow] k_type=2
7122 23:45:19.690454
7123 23:45:19.690547 ==DQ 0 ==
7124 23:45:19.693667 Final DQ duty delay cell = 0
7125 23:45:19.697078 [0] MAX Duty = 5218%(X100), DQS PI = 18
7126 23:45:19.700317 [0] MIN Duty = 4938%(X100), DQS PI = 56
7127 23:45:19.700397 [0] AVG Duty = 5078%(X100)
7128 23:45:19.703747
7129 23:45:19.703827 ==DQ 1 ==
7130 23:45:19.706799 Final DQ duty delay cell = -4
7131 23:45:19.710224 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7132 23:45:19.713614 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7133 23:45:19.716732 [-4] AVG Duty = 4953%(X100)
7134 23:45:19.716811
7135 23:45:19.720079 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7136 23:45:19.720159
7137 23:45:19.723455 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7138 23:45:19.726788 [DutyScan_Calibration_Flow] ====Done====
7139 23:45:19.726888 ==
7140 23:45:19.730288 Dram Type= 6, Freq= 0, CH_1, rank 0
7141 23:45:19.733626 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7142 23:45:19.733707 ==
7143 23:45:19.736723 [Duty_Offset_Calibration]
7144 23:45:19.736802 B0:0 B1:5 CA:-5
7145 23:45:19.736864
7146 23:45:19.740086 [DutyScan_Calibration_Flow] k_type=0
7147 23:45:19.751104
7148 23:45:19.751185 ==CLK 0==
7149 23:45:19.754457 Final CLK duty delay cell = 0
7150 23:45:19.757615 [0] MAX Duty = 5156%(X100), DQS PI = 18
7151 23:45:19.761019 [0] MIN Duty = 4906%(X100), DQS PI = 50
7152 23:45:19.764208 [0] AVG Duty = 5031%(X100)
7153 23:45:19.764290
7154 23:45:19.767502 CH1 CLK Duty spec in!! Max-Min= 250%
7155 23:45:19.770891 [DutyScan_Calibration_Flow] ====Done====
7156 23:45:19.770980
7157 23:45:19.774243 [DutyScan_Calibration_Flow] k_type=1
7158 23:45:19.790020
7159 23:45:19.790134 ==DQS 0 ==
7160 23:45:19.793200 Final DQS duty delay cell = 0
7161 23:45:19.796447 [0] MAX Duty = 5187%(X100), DQS PI = 20
7162 23:45:19.799983 [0] MIN Duty = 4876%(X100), DQS PI = 44
7163 23:45:19.803534 [0] AVG Duty = 5031%(X100)
7164 23:45:19.803616
7165 23:45:19.803680 ==DQS 1 ==
7166 23:45:19.806429 Final DQS duty delay cell = -4
7167 23:45:19.809919 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7168 23:45:19.813330 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7169 23:45:19.816709 [-4] AVG Duty = 4922%(X100)
7170 23:45:19.816789
7171 23:45:19.819986 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7172 23:45:19.820068
7173 23:45:19.823301 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7174 23:45:19.826555 [DutyScan_Calibration_Flow] ====Done====
7175 23:45:19.826637
7176 23:45:19.829844 [DutyScan_Calibration_Flow] k_type=3
7177 23:45:19.845673
7178 23:45:19.845760 ==DQM 0 ==
7179 23:45:19.849445 Final DQM duty delay cell = -4
7180 23:45:19.852170 [-4] MAX Duty = 5093%(X100), DQS PI = 34
7181 23:45:19.855798 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7182 23:45:19.858839 [-4] AVG Duty = 4953%(X100)
7183 23:45:19.858921
7184 23:45:19.858985 ==DQM 1 ==
7185 23:45:19.862178 Final DQM duty delay cell = -4
7186 23:45:19.865692 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7187 23:45:19.868894 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7188 23:45:19.872142 [-4] AVG Duty = 4984%(X100)
7189 23:45:19.872225
7190 23:45:19.875521 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7191 23:45:19.875603
7192 23:45:19.878842 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7193 23:45:19.882508 [DutyScan_Calibration_Flow] ====Done====
7194 23:45:19.882589
7195 23:45:19.885210 [DutyScan_Calibration_Flow] k_type=2
7196 23:45:19.903268
7197 23:45:19.903393 ==DQ 0 ==
7198 23:45:19.906598 Final DQ duty delay cell = 0
7199 23:45:19.909735 [0] MAX Duty = 5093%(X100), DQS PI = 36
7200 23:45:19.912959 [0] MIN Duty = 4938%(X100), DQS PI = 48
7201 23:45:19.913041 [0] AVG Duty = 5015%(X100)
7202 23:45:19.916372
7203 23:45:19.916453 ==DQ 1 ==
7204 23:45:19.919936 Final DQ duty delay cell = 0
7205 23:45:19.922995 [0] MAX Duty = 5062%(X100), DQS PI = 6
7206 23:45:19.926438 [0] MIN Duty = 4876%(X100), DQS PI = 24
7207 23:45:19.926520 [0] AVG Duty = 4969%(X100)
7208 23:45:19.926583
7209 23:45:19.929872 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7210 23:45:19.932962
7211 23:45:19.936487 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7212 23:45:19.939627 [DutyScan_Calibration_Flow] ====Done====
7213 23:45:19.943274 nWR fixed to 30
7214 23:45:19.943356 [ModeRegInit_LP4] CH0 RK0
7215 23:45:19.946247 [ModeRegInit_LP4] CH0 RK1
7216 23:45:19.949475 [ModeRegInit_LP4] CH1 RK0
7217 23:45:19.952866 [ModeRegInit_LP4] CH1 RK1
7218 23:45:19.952948 match AC timing 4
7219 23:45:19.959591 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7220 23:45:19.963003 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7221 23:45:19.966133 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7222 23:45:19.972963 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7223 23:45:19.975724 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7224 23:45:19.975808 [MiockJmeterHQA]
7225 23:45:19.975872
7226 23:45:19.979227 [DramcMiockJmeter] u1RxGatingPI = 0
7227 23:45:19.982619 0 : 4366, 4139
7228 23:45:19.982708 4 : 4253, 4027
7229 23:45:19.985761 8 : 4363, 4137
7230 23:45:19.985842 12 : 4250, 4027
7231 23:45:19.985906 16 : 4252, 4027
7232 23:45:19.989344 20 : 4363, 4137
7233 23:45:19.989427 24 : 4361, 4137
7234 23:45:19.992756 28 : 4252, 4027
7235 23:45:19.992916 32 : 4250, 4027
7236 23:45:19.995976 36 : 4250, 4027
7237 23:45:19.996135 40 : 4363, 4138
7238 23:45:19.998995 44 : 4250, 4027
7239 23:45:19.999100 48 : 4361, 4138
7240 23:45:19.999165 52 : 4250, 4026
7241 23:45:20.002461 56 : 4250, 4027
7242 23:45:20.002542 60 : 4252, 4027
7243 23:45:20.005659 64 : 4253, 4029
7244 23:45:20.005740 68 : 4250, 4026
7245 23:45:20.009272 72 : 4250, 4027
7246 23:45:20.009478 76 : 4364, 4140
7247 23:45:20.012346 80 : 4252, 4027
7248 23:45:20.012439 84 : 4253, 4029
7249 23:45:20.012505 88 : 4250, 4027
7250 23:45:20.015752 92 : 4360, 4137
7251 23:45:20.015834 96 : 4250, 4027
7252 23:45:20.018935 100 : 4361, 1668
7253 23:45:20.019018 104 : 4360, 0
7254 23:45:20.022434 108 : 4250, 0
7255 23:45:20.022595 112 : 4252, 0
7256 23:45:20.022673 116 : 4250, 0
7257 23:45:20.025655 120 : 4360, 0
7258 23:45:20.025799 124 : 4361, 0
7259 23:45:20.029314 128 : 4250, 0
7260 23:45:20.029483 132 : 4250, 0
7261 23:45:20.029575 136 : 4250, 0
7262 23:45:20.032438 140 : 4252, 0
7263 23:45:20.032566 144 : 4250, 0
7264 23:45:20.032648 148 : 4250, 0
7265 23:45:20.035763 152 : 4253, 0
7266 23:45:20.035924 156 : 4360, 0
7267 23:45:20.039187 160 : 4250, 0
7268 23:45:20.039351 164 : 4250, 0
7269 23:45:20.039450 168 : 4250, 0
7270 23:45:20.042367 172 : 4361, 0
7271 23:45:20.042556 176 : 4250, 0
7272 23:45:20.045580 180 : 4253, 0
7273 23:45:20.045779 184 : 4360, 0
7274 23:45:20.045889 188 : 4250, 0
7275 23:45:20.049045 192 : 4250, 0
7276 23:45:20.049182 196 : 4250, 0
7277 23:45:20.052018 200 : 4250, 0
7278 23:45:20.052100 204 : 4253, 0
7279 23:45:20.052166 208 : 4253, 0
7280 23:45:20.055226 212 : 4250, 0
7281 23:45:20.055306 216 : 4253, 0
7282 23:45:20.058791 220 : 4253, 1005
7283 23:45:20.058879 224 : 4250, 4022
7284 23:45:20.061907 228 : 4250, 4027
7285 23:45:20.062003 232 : 4361, 4138
7286 23:45:20.062077 236 : 4360, 4137
7287 23:45:20.065323 240 : 4250, 4027
7288 23:45:20.065427 244 : 4364, 4140
7289 23:45:20.068541 248 : 4360, 4137
7290 23:45:20.068643 252 : 4252, 4029
7291 23:45:20.071813 256 : 4253, 4029
7292 23:45:20.071925 260 : 4252, 4030
7293 23:45:20.075762 264 : 4250, 4027
7294 23:45:20.076214 268 : 4250, 4027
7295 23:45:20.078858 272 : 4250, 4026
7296 23:45:20.079273 276 : 4250, 4026
7297 23:45:20.082427 280 : 4250, 4027
7298 23:45:20.082843 284 : 4361, 4138
7299 23:45:20.085394 288 : 4360, 4137
7300 23:45:20.086170 292 : 4249, 4027
7301 23:45:20.086806 296 : 4364, 4140
7302 23:45:20.089446 300 : 4250, 4026
7303 23:45:20.089897 304 : 4252, 4029
7304 23:45:20.092433 308 : 4250, 4026
7305 23:45:20.092852 312 : 4253, 4029
7306 23:45:20.095427 316 : 4250, 4026
7307 23:45:20.095855 320 : 4250, 4027
7308 23:45:20.098596 324 : 4250, 4027
7309 23:45:20.099018 328 : 4252, 4029
7310 23:45:20.101988 332 : 4250, 4027
7311 23:45:20.102409 336 : 4360, 3623
7312 23:45:20.105307 340 : 4360, 1840
7313 23:45:20.105741
7314 23:45:20.106087 MIOCK jitter meter ch=0
7315 23:45:20.106574
7316 23:45:20.108628 1T = (340-100) = 240 dly cells
7317 23:45:20.115409 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7318 23:45:20.115821 ==
7319 23:45:20.118778 Dram Type= 6, Freq= 0, CH_0, rank 0
7320 23:45:20.121948 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7321 23:45:20.122368 ==
7322 23:45:20.128460 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7323 23:45:20.131939 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7324 23:45:20.138594 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7325 23:45:20.141757 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7326 23:45:20.150885 [CA 0] Center 42 (12~73) winsize 62
7327 23:45:20.154212 [CA 1] Center 42 (12~73) winsize 62
7328 23:45:20.157541 [CA 2] Center 39 (9~69) winsize 61
7329 23:45:20.160954 [CA 3] Center 38 (9~68) winsize 60
7330 23:45:20.164348 [CA 4] Center 37 (7~67) winsize 61
7331 23:45:20.167748 [CA 5] Center 36 (6~66) winsize 61
7332 23:45:20.168164
7333 23:45:20.171012 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7334 23:45:20.171637
7335 23:45:20.174109 [CATrainingPosCal] consider 1 rank data
7336 23:45:20.177797 u2DelayCellTimex100 = 271/100 ps
7337 23:45:20.181009 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7338 23:45:20.187822 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7339 23:45:20.190696 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7340 23:45:20.194418 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7341 23:45:20.197241 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7342 23:45:20.200568 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7343 23:45:20.200983
7344 23:45:20.205136 CA PerBit enable=1, Macro0, CA PI delay=36
7345 23:45:20.205691
7346 23:45:20.207204 [CBTSetCACLKResult] CA Dly = 36
7347 23:45:20.210659 CS Dly: 10 (0~41)
7348 23:45:20.214028 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7349 23:45:20.217543 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7350 23:45:20.217958 ==
7351 23:45:20.220523 Dram Type= 6, Freq= 0, CH_0, rank 1
7352 23:45:20.223990 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7353 23:45:20.227205 ==
7354 23:45:20.230604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7355 23:45:20.233833 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7356 23:45:20.240718 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7357 23:45:20.247052 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7358 23:45:20.253653 [CA 0] Center 42 (12~73) winsize 62
7359 23:45:20.256923 [CA 1] Center 41 (11~72) winsize 62
7360 23:45:20.260303 [CA 2] Center 38 (8~68) winsize 61
7361 23:45:20.263493 [CA 3] Center 37 (8~67) winsize 60
7362 23:45:20.266703 [CA 4] Center 35 (5~65) winsize 61
7363 23:45:20.270030 [CA 5] Center 35 (5~66) winsize 62
7364 23:45:20.270439
7365 23:45:20.273345 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7366 23:45:20.273755
7367 23:45:20.276827 [CATrainingPosCal] consider 2 rank data
7368 23:45:20.280011 u2DelayCellTimex100 = 271/100 ps
7369 23:45:20.286782 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7370 23:45:20.290543 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7371 23:45:20.293619 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7372 23:45:20.296663 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7373 23:45:20.299672 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7374 23:45:20.303105 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7375 23:45:20.303554
7376 23:45:20.306677 CA PerBit enable=1, Macro0, CA PI delay=36
7377 23:45:20.307238
7378 23:45:20.309692 [CBTSetCACLKResult] CA Dly = 36
7379 23:45:20.312801 CS Dly: 11 (0~43)
7380 23:45:20.316984 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7381 23:45:20.319848 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7382 23:45:20.320298
7383 23:45:20.323103 ----->DramcWriteLeveling(PI) begin...
7384 23:45:20.323554 ==
7385 23:45:20.326359 Dram Type= 6, Freq= 0, CH_0, rank 0
7386 23:45:20.333500 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7387 23:45:20.334042 ==
7388 23:45:20.336089 Write leveling (Byte 0): 30 => 30
7389 23:45:20.339712 Write leveling (Byte 1): 26 => 26
7390 23:45:20.340255 DramcWriteLeveling(PI) end<-----
7391 23:45:20.340610
7392 23:45:20.343019 ==
7393 23:45:20.346230 Dram Type= 6, Freq= 0, CH_0, rank 0
7394 23:45:20.349631 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7395 23:45:20.350171 ==
7396 23:45:20.352655 [Gating] SW mode calibration
7397 23:45:20.359465 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7398 23:45:20.362493 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7399 23:45:20.369236 0 12 0 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
7400 23:45:20.372567 0 12 4 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
7401 23:45:20.375762 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7402 23:45:20.382357 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7403 23:45:20.385608 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7404 23:45:20.389281 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7405 23:45:20.395355 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7406 23:45:20.398903 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7407 23:45:20.402124 0 13 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7408 23:45:20.408503 0 13 4 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7409 23:45:20.411842 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7410 23:45:20.415336 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7411 23:45:20.421600 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7412 23:45:20.425294 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7413 23:45:20.428719 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7414 23:45:20.435435 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7415 23:45:20.438977 0 14 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7416 23:45:20.441783 0 14 4 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7417 23:45:20.448565 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7418 23:45:20.452113 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7419 23:45:20.455205 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7420 23:45:20.461860 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7421 23:45:20.465087 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7422 23:45:20.468615 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7423 23:45:20.475085 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7424 23:45:20.478344 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7425 23:45:20.481663 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7426 23:45:20.488471 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7427 23:45:20.491698 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7428 23:45:20.494874 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7429 23:45:20.501443 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7430 23:45:20.504812 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7431 23:45:20.508362 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7432 23:45:20.515008 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7433 23:45:20.518848 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7434 23:45:20.521906 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7435 23:45:20.525568 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7436 23:45:20.531933 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7437 23:45:20.535073 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7438 23:45:20.538324 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7439 23:45:20.544914 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7440 23:45:20.548425 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7441 23:45:20.551539 Total UI for P1: 0, mck2ui 16
7442 23:45:20.555020 best dqsien dly found for B0: ( 1, 1, 0)
7443 23:45:20.558229 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7444 23:45:20.564740 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7445 23:45:20.568117 Total UI for P1: 0, mck2ui 16
7446 23:45:20.571357 best dqsien dly found for B1: ( 1, 1, 4)
7447 23:45:20.574856 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7448 23:45:20.578192 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7449 23:45:20.578746
7450 23:45:20.581597 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7451 23:45:20.585219 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7452 23:45:20.588035 [Gating] SW calibration Done
7453 23:45:20.588588 ==
7454 23:45:20.591192 Dram Type= 6, Freq= 0, CH_0, rank 0
7455 23:45:20.594530 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7456 23:45:20.594983 ==
7457 23:45:20.597753 RX Vref Scan: 0
7458 23:45:20.598201
7459 23:45:20.598556 RX Vref 0 -> 0, step: 1
7460 23:45:20.598880
7461 23:45:20.601020 RX Delay 0 -> 252, step: 8
7462 23:45:20.604910 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7463 23:45:20.611323 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7464 23:45:20.614726 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7465 23:45:20.617986 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7466 23:45:20.621182 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7467 23:45:20.624460 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
7468 23:45:20.631482 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7469 23:45:20.634698 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7470 23:45:20.637912 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7471 23:45:20.641270 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7472 23:45:20.644630 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7473 23:45:20.651188 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7474 23:45:20.654433 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7475 23:45:20.657879 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7476 23:45:20.660721 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7477 23:45:20.667315 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7478 23:45:20.667857 ==
7479 23:45:20.670679 Dram Type= 6, Freq= 0, CH_0, rank 0
7480 23:45:20.674020 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7481 23:45:20.674476 ==
7482 23:45:20.674831 DQS Delay:
7483 23:45:20.677241 DQS0 = 0, DQS1 = 0
7484 23:45:20.677830 DQM Delay:
7485 23:45:20.680748 DQM0 = 130, DQM1 = 123
7486 23:45:20.681339 DQ Delay:
7487 23:45:20.683952 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =127
7488 23:45:20.687523 DQ4 =135, DQ5 =115, DQ6 =139, DQ7 =139
7489 23:45:20.690575 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
7490 23:45:20.693700 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7491 23:45:20.694158
7492 23:45:20.694508
7493 23:45:20.696991 ==
7494 23:45:20.697530 Dram Type= 6, Freq= 0, CH_0, rank 0
7495 23:45:20.703735 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7496 23:45:20.704196 ==
7497 23:45:20.704552
7498 23:45:20.704881
7499 23:45:20.707422 TX Vref Scan disable
7500 23:45:20.707983 == TX Byte 0 ==
7501 23:45:20.710294 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7502 23:45:20.717453 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7503 23:45:20.718003 == TX Byte 1 ==
7504 23:45:20.720562 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7505 23:45:20.727205 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7506 23:45:20.727834 ==
7507 23:45:20.730392 Dram Type= 6, Freq= 0, CH_0, rank 0
7508 23:45:20.733774 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7509 23:45:20.734329 ==
7510 23:45:20.746903
7511 23:45:20.750168 TX Vref early break, caculate TX vref
7512 23:45:20.753413 TX Vref=16, minBit 8, minWin=21, winSum=369
7513 23:45:20.757038 TX Vref=18, minBit 8, minWin=22, winSum=379
7514 23:45:20.760226 TX Vref=20, minBit 8, minWin=23, winSum=393
7515 23:45:20.763807 TX Vref=22, minBit 8, minWin=23, winSum=395
7516 23:45:20.766494 TX Vref=24, minBit 9, minWin=24, winSum=405
7517 23:45:20.773280 TX Vref=26, minBit 2, minWin=25, winSum=413
7518 23:45:20.776586 TX Vref=28, minBit 8, minWin=25, winSum=417
7519 23:45:20.779956 TX Vref=30, minBit 0, minWin=25, winSum=412
7520 23:45:20.783177 TX Vref=32, minBit 3, minWin=24, winSum=399
7521 23:45:20.786575 TX Vref=34, minBit 3, minWin=23, winSum=391
7522 23:45:20.792932 [TxChooseVref] Worse bit 8, Min win 25, Win sum 417, Final Vref 28
7523 23:45:20.793688
7524 23:45:20.796446 Final TX Range 0 Vref 28
7525 23:45:20.796991
7526 23:45:20.797424 ==
7527 23:45:20.799866 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 23:45:20.803121 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7529 23:45:20.803608 ==
7530 23:45:20.803970
7531 23:45:20.804299
7532 23:45:20.806247 TX Vref Scan disable
7533 23:45:20.812983 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7534 23:45:20.813477 == TX Byte 0 ==
7535 23:45:20.816524 u2DelayCellOfst[0]=10 cells (3 PI)
7536 23:45:20.819864 u2DelayCellOfst[1]=18 cells (5 PI)
7537 23:45:20.823078 u2DelayCellOfst[2]=14 cells (4 PI)
7538 23:45:20.826219 u2DelayCellOfst[3]=14 cells (4 PI)
7539 23:45:20.829812 u2DelayCellOfst[4]=7 cells (2 PI)
7540 23:45:20.833045 u2DelayCellOfst[5]=0 cells (0 PI)
7541 23:45:20.836630 u2DelayCellOfst[6]=21 cells (6 PI)
7542 23:45:20.840010 u2DelayCellOfst[7]=21 cells (6 PI)
7543 23:45:20.842658 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7544 23:45:20.845966 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7545 23:45:20.849757 == TX Byte 1 ==
7546 23:45:20.853056 u2DelayCellOfst[8]=3 cells (1 PI)
7547 23:45:20.853662 u2DelayCellOfst[9]=0 cells (0 PI)
7548 23:45:20.856160 u2DelayCellOfst[10]=10 cells (3 PI)
7549 23:45:20.859428 u2DelayCellOfst[11]=3 cells (1 PI)
7550 23:45:20.862838 u2DelayCellOfst[12]=18 cells (5 PI)
7551 23:45:20.866130 u2DelayCellOfst[13]=14 cells (4 PI)
7552 23:45:20.869986 u2DelayCellOfst[14]=21 cells (6 PI)
7553 23:45:20.872623 u2DelayCellOfst[15]=18 cells (5 PI)
7554 23:45:20.875849 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7555 23:45:20.882411 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7556 23:45:20.882961 DramC Write-DBI on
7557 23:45:20.883321 ==
7558 23:45:20.885805 Dram Type= 6, Freq= 0, CH_0, rank 0
7559 23:45:20.892261 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7560 23:45:20.892829 ==
7561 23:45:20.893196
7562 23:45:20.893768
7563 23:45:20.894401 TX Vref Scan disable
7564 23:45:20.896202 == TX Byte 0 ==
7565 23:45:20.899458 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7566 23:45:20.903043 == TX Byte 1 ==
7567 23:45:20.906199 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7568 23:45:20.906653 DramC Write-DBI off
7569 23:45:20.909707
7570 23:45:20.910289 [DATLAT]
7571 23:45:20.910648 Freq=1600, CH0 RK0
7572 23:45:20.910977
7573 23:45:20.912874 DATLAT Default: 0xf
7574 23:45:20.913358 0, 0xFFFF, sum = 0
7575 23:45:20.916623 1, 0xFFFF, sum = 0
7576 23:45:20.919732 2, 0xFFFF, sum = 0
7577 23:45:20.920310 3, 0xFFFF, sum = 0
7578 23:45:20.922983 4, 0xFFFF, sum = 0
7579 23:45:20.923546 5, 0xFFFF, sum = 0
7580 23:45:20.926039 6, 0xFFFF, sum = 0
7581 23:45:20.926543 7, 0xFFFF, sum = 0
7582 23:45:20.929275 8, 0xFFFF, sum = 0
7583 23:45:20.929773 9, 0xFFFF, sum = 0
7584 23:45:20.933042 10, 0xFFFF, sum = 0
7585 23:45:20.933647 11, 0xFFFF, sum = 0
7586 23:45:20.936095 12, 0xFFF, sum = 0
7587 23:45:20.936650 13, 0x0, sum = 1
7588 23:45:20.939629 14, 0x0, sum = 2
7589 23:45:20.940243 15, 0x0, sum = 3
7590 23:45:20.942573 16, 0x0, sum = 4
7591 23:45:20.943107 best_step = 14
7592 23:45:20.943467
7593 23:45:20.943794 ==
7594 23:45:20.946178 Dram Type= 6, Freq= 0, CH_0, rank 0
7595 23:45:20.949514 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7596 23:45:20.952430 ==
7597 23:45:20.952884 RX Vref Scan: 1
7598 23:45:20.953237
7599 23:45:20.955859 Set Vref Range= 24 -> 127
7600 23:45:20.956309
7601 23:45:20.959178 RX Vref 24 -> 127, step: 1
7602 23:45:20.959628
7603 23:45:20.959973 RX Delay 11 -> 252, step: 4
7604 23:45:20.960297
7605 23:45:20.962688 Set Vref, RX VrefLevel [Byte0]: 24
7606 23:45:20.965946 [Byte1]: 24
7607 23:45:20.969959
7608 23:45:20.972970 Set Vref, RX VrefLevel [Byte0]: 25
7609 23:45:20.973570 [Byte1]: 25
7610 23:45:20.977127
7611 23:45:20.977736 Set Vref, RX VrefLevel [Byte0]: 26
7612 23:45:20.980476 [Byte1]: 26
7613 23:45:20.985476
7614 23:45:20.986013 Set Vref, RX VrefLevel [Byte0]: 27
7615 23:45:20.987860 [Byte1]: 27
7616 23:45:20.992454
7617 23:45:20.993100 Set Vref, RX VrefLevel [Byte0]: 28
7618 23:45:20.995575 [Byte1]: 28
7619 23:45:21.000148
7620 23:45:21.000595 Set Vref, RX VrefLevel [Byte0]: 29
7621 23:45:21.003248 [Byte1]: 29
7622 23:45:21.007646
7623 23:45:21.008196 Set Vref, RX VrefLevel [Byte0]: 30
7624 23:45:21.010899 [Byte1]: 30
7625 23:45:21.015084
7626 23:45:21.015535 Set Vref, RX VrefLevel [Byte0]: 31
7627 23:45:21.018399 [Byte1]: 31
7628 23:45:21.022759
7629 23:45:21.023325 Set Vref, RX VrefLevel [Byte0]: 32
7630 23:45:21.026123 [Byte1]: 32
7631 23:45:21.030483
7632 23:45:21.031064 Set Vref, RX VrefLevel [Byte0]: 33
7633 23:45:21.033750 [Byte1]: 33
7634 23:45:21.038133
7635 23:45:21.038682 Set Vref, RX VrefLevel [Byte0]: 34
7636 23:45:21.041196 [Byte1]: 34
7637 23:45:21.045531
7638 23:45:21.045978 Set Vref, RX VrefLevel [Byte0]: 35
7639 23:45:21.049036 [Byte1]: 35
7640 23:45:21.053624
7641 23:45:21.054178 Set Vref, RX VrefLevel [Byte0]: 36
7642 23:45:21.056552 [Byte1]: 36
7643 23:45:21.061033
7644 23:45:21.061623 Set Vref, RX VrefLevel [Byte0]: 37
7645 23:45:21.064298 [Byte1]: 37
7646 23:45:21.068502
7647 23:45:21.069050 Set Vref, RX VrefLevel [Byte0]: 38
7648 23:45:21.071912 [Byte1]: 38
7649 23:45:21.076358
7650 23:45:21.076906 Set Vref, RX VrefLevel [Byte0]: 39
7651 23:45:21.079601 [Byte1]: 39
7652 23:45:21.083938
7653 23:45:21.084487 Set Vref, RX VrefLevel [Byte0]: 40
7654 23:45:21.087100 [Byte1]: 40
7655 23:45:21.091717
7656 23:45:21.092262 Set Vref, RX VrefLevel [Byte0]: 41
7657 23:45:21.094771 [Byte1]: 41
7658 23:45:21.098942
7659 23:45:21.099393 Set Vref, RX VrefLevel [Byte0]: 42
7660 23:45:21.102367 [Byte1]: 42
7661 23:45:21.106759
7662 23:45:21.107301 Set Vref, RX VrefLevel [Byte0]: 43
7663 23:45:21.109850 [Byte1]: 43
7664 23:45:21.114163
7665 23:45:21.114709 Set Vref, RX VrefLevel [Byte0]: 44
7666 23:45:21.117420 [Byte1]: 44
7667 23:45:21.121824
7668 23:45:21.122403 Set Vref, RX VrefLevel [Byte0]: 45
7669 23:45:21.125187 [Byte1]: 45
7670 23:45:21.129854
7671 23:45:21.130538 Set Vref, RX VrefLevel [Byte0]: 46
7672 23:45:21.132809 [Byte1]: 46
7673 23:45:21.137333
7674 23:45:21.137891 Set Vref, RX VrefLevel [Byte0]: 47
7675 23:45:21.140210 [Byte1]: 47
7676 23:45:21.144648
7677 23:45:21.145200 Set Vref, RX VrefLevel [Byte0]: 48
7678 23:45:21.148339 [Byte1]: 48
7679 23:45:21.152679
7680 23:45:21.153232 Set Vref, RX VrefLevel [Byte0]: 49
7681 23:45:21.155455 [Byte1]: 49
7682 23:45:21.160177
7683 23:45:21.160733 Set Vref, RX VrefLevel [Byte0]: 50
7684 23:45:21.163245 [Byte1]: 50
7685 23:45:21.167979
7686 23:45:21.168531 Set Vref, RX VrefLevel [Byte0]: 51
7687 23:45:21.170619 [Byte1]: 51
7688 23:45:21.175301
7689 23:45:21.175856 Set Vref, RX VrefLevel [Byte0]: 52
7690 23:45:21.178704 [Byte1]: 52
7691 23:45:21.182591
7692 23:45:21.183138 Set Vref, RX VrefLevel [Byte0]: 53
7693 23:45:21.186200 [Byte1]: 53
7694 23:45:21.190429
7695 23:45:21.190984 Set Vref, RX VrefLevel [Byte0]: 54
7696 23:45:21.193750 [Byte1]: 54
7697 23:45:21.197956
7698 23:45:21.198413 Set Vref, RX VrefLevel [Byte0]: 55
7699 23:45:21.201482 [Byte1]: 55
7700 23:45:21.205561
7701 23:45:21.206103 Set Vref, RX VrefLevel [Byte0]: 56
7702 23:45:21.208949 [Byte1]: 56
7703 23:45:21.213545
7704 23:45:21.214081 Set Vref, RX VrefLevel [Byte0]: 57
7705 23:45:21.216278 [Byte1]: 57
7706 23:45:21.220988
7707 23:45:21.221572 Set Vref, RX VrefLevel [Byte0]: 58
7708 23:45:21.224137 [Byte1]: 58
7709 23:45:21.228371
7710 23:45:21.229007 Set Vref, RX VrefLevel [Byte0]: 59
7711 23:45:21.231719 [Byte1]: 59
7712 23:45:21.236082
7713 23:45:21.236634 Set Vref, RX VrefLevel [Byte0]: 60
7714 23:45:21.239262 [Byte1]: 60
7715 23:45:21.243745
7716 23:45:21.244195 Set Vref, RX VrefLevel [Byte0]: 61
7717 23:45:21.246750 [Byte1]: 61
7718 23:45:21.251468
7719 23:45:21.252011 Set Vref, RX VrefLevel [Byte0]: 62
7720 23:45:21.254276 [Byte1]: 62
7721 23:45:21.258545
7722 23:45:21.258996 Set Vref, RX VrefLevel [Byte0]: 63
7723 23:45:21.261971 [Byte1]: 63
7724 23:45:21.266848
7725 23:45:21.267407 Set Vref, RX VrefLevel [Byte0]: 64
7726 23:45:21.269632 [Byte1]: 64
7727 23:45:21.273868
7728 23:45:21.274317 Set Vref, RX VrefLevel [Byte0]: 65
7729 23:45:21.277050 [Byte1]: 65
7730 23:45:21.281330
7731 23:45:21.281738 Set Vref, RX VrefLevel [Byte0]: 66
7732 23:45:21.285093 [Byte1]: 66
7733 23:45:21.289323
7734 23:45:21.289729 Set Vref, RX VrefLevel [Byte0]: 67
7735 23:45:21.292700 [Byte1]: 67
7736 23:45:21.296822
7737 23:45:21.297473 Set Vref, RX VrefLevel [Byte0]: 68
7738 23:45:21.299904 [Byte1]: 68
7739 23:45:21.304275
7740 23:45:21.304679 Final RX Vref Byte 0 = 54 to rank0
7741 23:45:21.307737 Final RX Vref Byte 1 = 56 to rank0
7742 23:45:21.311085 Final RX Vref Byte 0 = 54 to rank1
7743 23:45:21.314311 Final RX Vref Byte 1 = 56 to rank1==
7744 23:45:21.317589 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 23:45:21.324201 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7746 23:45:21.324614 ==
7747 23:45:21.324935 DQS Delay:
7748 23:45:21.327655 DQS0 = 0, DQS1 = 0
7749 23:45:21.328065 DQM Delay:
7750 23:45:21.328383 DQM0 = 126, DQM1 = 120
7751 23:45:21.331065 DQ Delay:
7752 23:45:21.334074 DQ0 =122, DQ1 =128, DQ2 =124, DQ3 =122
7753 23:45:21.337917 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7754 23:45:21.340639 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
7755 23:45:21.344253 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =132
7756 23:45:21.344658
7757 23:45:21.344977
7758 23:45:21.345271
7759 23:45:21.347256 [DramC_TX_OE_Calibration] TA2
7760 23:45:21.350744 Original DQ_B0 (3 6) =30, OEN = 27
7761 23:45:21.353922 Original DQ_B1 (3 6) =30, OEN = 27
7762 23:45:21.357400 24, 0x0, End_B0=24 End_B1=24
7763 23:45:21.357816 25, 0x0, End_B0=25 End_B1=25
7764 23:45:21.360594 26, 0x0, End_B0=26 End_B1=26
7765 23:45:21.363930 27, 0x0, End_B0=27 End_B1=27
7766 23:45:21.367261 28, 0x0, End_B0=28 End_B1=28
7767 23:45:21.370689 29, 0x0, End_B0=29 End_B1=29
7768 23:45:21.371112 30, 0x0, End_B0=30 End_B1=30
7769 23:45:21.373870 31, 0x4141, End_B0=30 End_B1=30
7770 23:45:21.377341 Byte0 end_step=30 best_step=27
7771 23:45:21.380677 Byte1 end_step=30 best_step=27
7772 23:45:21.384028 Byte0 TX OE(2T, 0.5T) = (3, 3)
7773 23:45:21.387124 Byte1 TX OE(2T, 0.5T) = (3, 3)
7774 23:45:21.387539
7775 23:45:21.387866
7776 23:45:21.393886 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
7777 23:45:21.397229 CH0 RK0: MR19=303, MR18=1B1B
7778 23:45:21.403619 CH0_RK0: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
7779 23:45:21.404039
7780 23:45:21.407126 ----->DramcWriteLeveling(PI) begin...
7781 23:45:21.407550 ==
7782 23:45:21.410559 Dram Type= 6, Freq= 0, CH_0, rank 1
7783 23:45:21.413912 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7784 23:45:21.414433 ==
7785 23:45:21.416997 Write leveling (Byte 0): 30 => 30
7786 23:45:21.420645 Write leveling (Byte 1): 27 => 27
7787 23:45:21.423485 DramcWriteLeveling(PI) end<-----
7788 23:45:21.423902
7789 23:45:21.424228 ==
7790 23:45:21.426989 Dram Type= 6, Freq= 0, CH_0, rank 1
7791 23:45:21.430343 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7792 23:45:21.430864 ==
7793 23:45:21.433657 [Gating] SW mode calibration
7794 23:45:21.440194 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7795 23:45:21.446960 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7796 23:45:21.450239 0 12 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7797 23:45:21.456593 0 12 4 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7798 23:45:21.459983 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7799 23:45:21.463430 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7800 23:45:21.469949 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7801 23:45:21.473098 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7802 23:45:21.476467 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7803 23:45:21.482997 0 12 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7804 23:45:21.486183 0 13 0 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
7805 23:45:21.489755 0 13 4 | B1->B0 | 3333 2424 | 1 0 | (1 0) (0 0)
7806 23:45:21.496366 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7807 23:45:21.499715 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7808 23:45:21.502883 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7809 23:45:21.509894 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7810 23:45:21.512918 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7811 23:45:21.516317 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7812 23:45:21.523080 0 14 0 | B1->B0 | 2424 4242 | 0 0 | (0 0) (0 0)
7813 23:45:21.526090 0 14 4 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
7814 23:45:21.529947 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7815 23:45:21.532960 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7816 23:45:21.539652 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7817 23:45:21.542917 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7818 23:45:21.546242 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7819 23:45:21.552728 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7820 23:45:21.555752 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7821 23:45:21.559359 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7822 23:45:21.565972 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7823 23:45:21.569341 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7824 23:45:21.572872 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7825 23:45:21.579284 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7826 23:45:21.582443 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7827 23:45:21.586015 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7828 23:45:21.592527 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7829 23:45:21.595593 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7830 23:45:21.599002 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7831 23:45:21.605755 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7832 23:45:21.609038 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7833 23:45:21.612536 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7834 23:45:21.619175 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7835 23:45:21.622735 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7836 23:45:21.625539 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7837 23:45:21.632371 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7838 23:45:21.635593 Total UI for P1: 0, mck2ui 16
7839 23:45:21.639000 best dqsien dly found for B0: ( 1, 0, 30)
7840 23:45:21.642223 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7841 23:45:21.645520 Total UI for P1: 0, mck2ui 16
7842 23:45:21.648897 best dqsien dly found for B1: ( 1, 1, 4)
7843 23:45:21.651911 best DQS0 dly(MCK, UI, PI) = (1, 0, 30)
7844 23:45:21.655206 best DQS1 dly(MCK, UI, PI) = (1, 1, 4)
7845 23:45:21.655664
7846 23:45:21.658750 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 30)
7847 23:45:21.661947 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 4)
7848 23:45:21.665466 [Gating] SW calibration Done
7849 23:45:21.666164 ==
7850 23:45:21.668809 Dram Type= 6, Freq= 0, CH_0, rank 1
7851 23:45:21.672132 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7852 23:45:21.675136 ==
7853 23:45:21.675700 RX Vref Scan: 0
7854 23:45:21.676062
7855 23:45:21.678556 RX Vref 0 -> 0, step: 1
7856 23:45:21.679116
7857 23:45:21.681719 RX Delay 0 -> 252, step: 8
7858 23:45:21.685160 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7859 23:45:21.688709 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7860 23:45:21.691609 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7861 23:45:21.694827 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
7862 23:45:21.701447 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7863 23:45:21.704704 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7864 23:45:21.708201 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7865 23:45:21.711494 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7866 23:45:21.714537 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7867 23:45:21.721462 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7868 23:45:21.724846 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7869 23:45:21.727713 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7870 23:45:21.731202 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7871 23:45:21.734931 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7872 23:45:21.741434 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
7873 23:45:21.744530 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7874 23:45:21.744991 ==
7875 23:45:21.748088 Dram Type= 6, Freq= 0, CH_0, rank 1
7876 23:45:21.751218 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7877 23:45:21.751841 ==
7878 23:45:21.754332 DQS Delay:
7879 23:45:21.754789 DQS0 = 0, DQS1 = 0
7880 23:45:21.755149 DQM Delay:
7881 23:45:21.757659 DQM0 = 130, DQM1 = 123
7882 23:45:21.758208 DQ Delay:
7883 23:45:21.760875 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =123
7884 23:45:21.764625 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
7885 23:45:21.771121 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7886 23:45:21.774648 DQ12 =131, DQ13 =131, DQ14 =131, DQ15 =131
7887 23:45:21.775195
7888 23:45:21.775551
7889 23:45:21.775886 ==
7890 23:45:21.777438 Dram Type= 6, Freq= 0, CH_0, rank 1
7891 23:45:21.781116 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7892 23:45:21.781715 ==
7893 23:45:21.782077
7894 23:45:21.782404
7895 23:45:21.784274 TX Vref Scan disable
7896 23:45:21.787518 == TX Byte 0 ==
7897 23:45:21.790876 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7898 23:45:21.794127 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7899 23:45:21.797426 == TX Byte 1 ==
7900 23:45:21.800486 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7901 23:45:21.803939 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7902 23:45:21.804399 ==
7903 23:45:21.807295 Dram Type= 6, Freq= 0, CH_0, rank 1
7904 23:45:21.810959 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7905 23:45:21.813705 ==
7906 23:45:21.825138
7907 23:45:21.828466 TX Vref early break, caculate TX vref
7908 23:45:21.831884 TX Vref=16, minBit 11, minWin=22, winSum=374
7909 23:45:21.834902 TX Vref=18, minBit 11, minWin=22, winSum=383
7910 23:45:21.838164 TX Vref=20, minBit 8, minWin=23, winSum=392
7911 23:45:21.841525 TX Vref=22, minBit 8, minWin=23, winSum=396
7912 23:45:21.845166 TX Vref=24, minBit 1, minWin=24, winSum=405
7913 23:45:21.851327 TX Vref=26, minBit 8, minWin=24, winSum=408
7914 23:45:21.854532 TX Vref=28, minBit 3, minWin=25, winSum=415
7915 23:45:21.858109 TX Vref=30, minBit 4, minWin=25, winSum=416
7916 23:45:21.861535 TX Vref=32, minBit 1, minWin=24, winSum=401
7917 23:45:21.864487 TX Vref=34, minBit 1, minWin=23, winSum=394
7918 23:45:21.871559 [TxChooseVref] Worse bit 4, Min win 25, Win sum 416, Final Vref 30
7919 23:45:21.872151
7920 23:45:21.874720 Final TX Range 0 Vref 30
7921 23:45:21.875276
7922 23:45:21.875636 ==
7923 23:45:21.877901 Dram Type= 6, Freq= 0, CH_0, rank 1
7924 23:45:21.881162 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7925 23:45:21.881766 ==
7926 23:45:21.882131
7927 23:45:21.882460
7928 23:45:21.884724 TX Vref Scan disable
7929 23:45:21.891065 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7930 23:45:21.891568 == TX Byte 0 ==
7931 23:45:21.894331 u2DelayCellOfst[0]=10 cells (3 PI)
7932 23:45:21.897606 u2DelayCellOfst[1]=14 cells (4 PI)
7933 23:45:21.900883 u2DelayCellOfst[2]=10 cells (3 PI)
7934 23:45:21.904313 u2DelayCellOfst[3]=10 cells (3 PI)
7935 23:45:21.907777 u2DelayCellOfst[4]=3 cells (1 PI)
7936 23:45:21.911098 u2DelayCellOfst[5]=0 cells (0 PI)
7937 23:45:21.914361 u2DelayCellOfst[6]=14 cells (4 PI)
7938 23:45:21.917673 u2DelayCellOfst[7]=14 cells (4 PI)
7939 23:45:21.921329 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7940 23:45:21.924505 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7941 23:45:21.927856 == TX Byte 1 ==
7942 23:45:21.931007 u2DelayCellOfst[8]=3 cells (1 PI)
7943 23:45:21.931559 u2DelayCellOfst[9]=0 cells (0 PI)
7944 23:45:21.934089 u2DelayCellOfst[10]=14 cells (4 PI)
7945 23:45:21.937782 u2DelayCellOfst[11]=10 cells (3 PI)
7946 23:45:21.940879 u2DelayCellOfst[12]=18 cells (5 PI)
7947 23:45:21.944459 u2DelayCellOfst[13]=18 cells (5 PI)
7948 23:45:21.947774 u2DelayCellOfst[14]=21 cells (6 PI)
7949 23:45:21.950946 u2DelayCellOfst[15]=18 cells (5 PI)
7950 23:45:21.957251 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7951 23:45:21.960586 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7952 23:45:21.961040 DramC Write-DBI on
7953 23:45:21.961424 ==
7954 23:45:21.964182 Dram Type= 6, Freq= 0, CH_0, rank 1
7955 23:45:21.970644 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7956 23:45:21.971249 ==
7957 23:45:21.971615
7958 23:45:21.971946
7959 23:45:21.972263 TX Vref Scan disable
7960 23:45:21.975117 == TX Byte 0 ==
7961 23:45:21.978018 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7962 23:45:21.981558 == TX Byte 1 ==
7963 23:45:21.984801 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7964 23:45:21.988106 DramC Write-DBI off
7965 23:45:21.988670
7966 23:45:21.989031 [DATLAT]
7967 23:45:21.989402 Freq=1600, CH0 RK1
7968 23:45:21.989730
7969 23:45:21.991058 DATLAT Default: 0xe
7970 23:45:21.991511 0, 0xFFFF, sum = 0
7971 23:45:21.994710 1, 0xFFFF, sum = 0
7972 23:45:21.997780 2, 0xFFFF, sum = 0
7973 23:45:21.998248 3, 0xFFFF, sum = 0
7974 23:45:22.001219 4, 0xFFFF, sum = 0
7975 23:45:22.001756 5, 0xFFFF, sum = 0
7976 23:45:22.004239 6, 0xFFFF, sum = 0
7977 23:45:22.004708 7, 0xFFFF, sum = 0
7978 23:45:22.007626 8, 0xFFFF, sum = 0
7979 23:45:22.008087 9, 0xFFFF, sum = 0
7980 23:45:22.011227 10, 0xFFFF, sum = 0
7981 23:45:22.011782 11, 0xFFFF, sum = 0
7982 23:45:22.014496 12, 0x8FFF, sum = 0
7983 23:45:22.015055 13, 0x0, sum = 1
7984 23:45:22.017633 14, 0x0, sum = 2
7985 23:45:22.018093 15, 0x0, sum = 3
7986 23:45:22.021286 16, 0x0, sum = 4
7987 23:45:22.021873 best_step = 14
7988 23:45:22.022233
7989 23:45:22.022567 ==
7990 23:45:22.024131 Dram Type= 6, Freq= 0, CH_0, rank 1
7991 23:45:22.027847 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7992 23:45:22.031105 ==
7993 23:45:22.031660 RX Vref Scan: 0
7994 23:45:22.032020
7995 23:45:22.034105 RX Vref 0 -> 0, step: 1
7996 23:45:22.034564
7997 23:45:22.037972 RX Delay 11 -> 252, step: 4
7998 23:45:22.040840 iDelay=195, Bit 0, Center 122 (67 ~ 178) 112
7999 23:45:22.044224 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8000 23:45:22.047732 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
8001 23:45:22.054073 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8002 23:45:22.057273 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8003 23:45:22.060891 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
8004 23:45:22.064080 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8005 23:45:22.067647 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
8006 23:45:22.074034 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112
8007 23:45:22.077377 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
8008 23:45:22.080810 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8009 23:45:22.084049 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8010 23:45:22.087718 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8011 23:45:22.094174 iDelay=195, Bit 13, Center 126 (71 ~ 182) 112
8012 23:45:22.097244 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8013 23:45:22.100323 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8014 23:45:22.100782 ==
8015 23:45:22.103768 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 23:45:22.107296 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8017 23:45:22.107852 ==
8018 23:45:22.110404 DQS Delay:
8019 23:45:22.110947 DQS0 = 0, DQS1 = 0
8020 23:45:22.113653 DQM Delay:
8021 23:45:22.114111 DQM0 = 127, DQM1 = 120
8022 23:45:22.117651 DQ Delay:
8023 23:45:22.120323 DQ0 =122, DQ1 =130, DQ2 =126, DQ3 =122
8024 23:45:22.123492 DQ4 =130, DQ5 =118, DQ6 =134, DQ7 =138
8025 23:45:22.127545 DQ8 =106, DQ9 =106, DQ10 =122, DQ11 =112
8026 23:45:22.130524 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8027 23:45:22.131076
8028 23:45:22.131436
8029 23:45:22.131768
8030 23:45:22.133495 [DramC_TX_OE_Calibration] TA2
8031 23:45:22.137190 Original DQ_B0 (3 6) =30, OEN = 27
8032 23:45:22.140434 Original DQ_B1 (3 6) =30, OEN = 27
8033 23:45:22.140989 24, 0x0, End_B0=24 End_B1=24
8034 23:45:22.143517 25, 0x0, End_B0=25 End_B1=25
8035 23:45:22.147085 26, 0x0, End_B0=26 End_B1=26
8036 23:45:22.150170 27, 0x0, End_B0=27 End_B1=27
8037 23:45:22.153442 28, 0x0, End_B0=28 End_B1=28
8038 23:45:22.153912 29, 0x0, End_B0=29 End_B1=29
8039 23:45:22.157238 30, 0x0, End_B0=30 End_B1=30
8040 23:45:22.160540 31, 0x4141, End_B0=30 End_B1=30
8041 23:45:22.163636 Byte0 end_step=30 best_step=27
8042 23:45:22.166937 Byte1 end_step=30 best_step=27
8043 23:45:22.170202 Byte0 TX OE(2T, 0.5T) = (3, 3)
8044 23:45:22.170756 Byte1 TX OE(2T, 0.5T) = (3, 3)
8045 23:45:22.171117
8046 23:45:22.173398
8047 23:45:22.180229 [DQSOSCAuto] RK1, (LSB)MR18= 0x2323, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
8048 23:45:22.183254 CH0 RK1: MR19=303, MR18=2323
8049 23:45:22.189899 CH0_RK1: MR19=0x303, MR18=0x2323, DQSOSC=392, MR23=63, INC=24, DEC=16
8050 23:45:22.193485 [RxdqsGatingPostProcess] freq 1600
8051 23:45:22.196630 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8052 23:45:22.199582 Pre-setting of DQS Precalculation
8053 23:45:22.206728 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8054 23:45:22.207281 ==
8055 23:45:22.209534 Dram Type= 6, Freq= 0, CH_1, rank 0
8056 23:45:22.213425 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8057 23:45:22.213981 ==
8058 23:45:22.219978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8059 23:45:22.222750 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8060 23:45:22.226406 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8061 23:45:22.232696 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8062 23:45:22.240900 [CA 0] Center 41 (12~71) winsize 60
8063 23:45:22.243912 [CA 1] Center 41 (11~72) winsize 62
8064 23:45:22.247773 [CA 2] Center 37 (8~67) winsize 60
8065 23:45:22.250570 [CA 3] Center 36 (7~66) winsize 60
8066 23:45:22.254015 [CA 4] Center 34 (4~64) winsize 61
8067 23:45:22.257462 [CA 5] Center 34 (4~64) winsize 61
8068 23:45:22.258008
8069 23:45:22.260623 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8070 23:45:22.261081
8071 23:45:22.264077 [CATrainingPosCal] consider 1 rank data
8072 23:45:22.267278 u2DelayCellTimex100 = 271/100 ps
8073 23:45:22.270533 CA0 delay=41 (12~71),Diff = 7 PI (25 cell)
8074 23:45:22.277276 CA1 delay=41 (11~72),Diff = 7 PI (25 cell)
8075 23:45:22.280556 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8076 23:45:22.283933 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8077 23:45:22.287362 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8078 23:45:22.290570 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
8079 23:45:22.291118
8080 23:45:22.293614 CA PerBit enable=1, Macro0, CA PI delay=34
8081 23:45:22.294071
8082 23:45:22.297067 [CBTSetCACLKResult] CA Dly = 34
8083 23:45:22.300390 CS Dly: 8 (0~39)
8084 23:45:22.303465 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8085 23:45:22.307159 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8086 23:45:22.307708 ==
8087 23:45:22.310085 Dram Type= 6, Freq= 0, CH_1, rank 1
8088 23:45:22.313377 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8089 23:45:22.316762 ==
8090 23:45:22.320043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8091 23:45:22.323578 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8092 23:45:22.330236 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8093 23:45:22.336877 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8094 23:45:22.343187 [CA 0] Center 40 (10~70) winsize 61
8095 23:45:22.346602 [CA 1] Center 39 (9~70) winsize 62
8096 23:45:22.349607 [CA 2] Center 35 (6~65) winsize 60
8097 23:45:22.353064 [CA 3] Center 35 (6~64) winsize 59
8098 23:45:22.356181 [CA 4] Center 32 (3~62) winsize 60
8099 23:45:22.360189 [CA 5] Center 33 (4~63) winsize 60
8100 23:45:22.360739
8101 23:45:22.362742 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8102 23:45:22.363200
8103 23:45:22.366284 [CATrainingPosCal] consider 2 rank data
8104 23:45:22.369772 u2DelayCellTimex100 = 271/100 ps
8105 23:45:22.373145 CA0 delay=41 (12~70),Diff = 8 PI (28 cell)
8106 23:45:22.379671 CA1 delay=40 (11~70),Diff = 7 PI (25 cell)
8107 23:45:22.382907 CA2 delay=36 (8~65),Diff = 3 PI (10 cell)
8108 23:45:22.385965 CA3 delay=35 (7~64),Diff = 2 PI (7 cell)
8109 23:45:22.389595 CA4 delay=33 (4~62),Diff = 0 PI (0 cell)
8110 23:45:22.393076 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8111 23:45:22.393676
8112 23:45:22.395926 CA PerBit enable=1, Macro0, CA PI delay=33
8113 23:45:22.396421
8114 23:45:22.399292 [CBTSetCACLKResult] CA Dly = 33
8115 23:45:22.402341 CS Dly: 9 (0~41)
8116 23:45:22.405729 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8117 23:45:22.409061 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8118 23:45:22.409560
8119 23:45:22.412357 ----->DramcWriteLeveling(PI) begin...
8120 23:45:22.412820 ==
8121 23:45:22.415941 Dram Type= 6, Freq= 0, CH_1, rank 0
8122 23:45:22.422576 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8123 23:45:22.423113 ==
8124 23:45:22.425707 Write leveling (Byte 0): 22 => 22
8125 23:45:22.426165 Write leveling (Byte 1): 20 => 20
8126 23:45:22.429173 DramcWriteLeveling(PI) end<-----
8127 23:45:22.429889
8128 23:45:22.432350 ==
8129 23:45:22.435559 Dram Type= 6, Freq= 0, CH_1, rank 0
8130 23:45:22.438769 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8131 23:45:22.439226 ==
8132 23:45:22.442233 [Gating] SW mode calibration
8133 23:45:22.448789 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8134 23:45:22.452500 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8135 23:45:22.458799 0 12 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8136 23:45:22.461715 0 12 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8137 23:45:22.465160 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8138 23:45:22.472125 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8139 23:45:22.475348 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8140 23:45:22.478591 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8141 23:45:22.485122 0 12 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8142 23:45:22.488497 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8143 23:45:22.491921 0 13 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
8144 23:45:22.498328 0 13 4 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8145 23:45:22.501523 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8146 23:45:22.505084 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8147 23:45:22.511628 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8148 23:45:22.515366 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8149 23:45:22.518452 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8150 23:45:22.524811 0 13 28 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
8151 23:45:22.528450 0 14 0 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
8152 23:45:22.531550 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8153 23:45:22.538177 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8154 23:45:22.541700 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8155 23:45:22.545009 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8156 23:45:22.551638 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8157 23:45:22.554641 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8158 23:45:22.558147 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8159 23:45:22.564831 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8160 23:45:22.568248 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8161 23:45:22.571343 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8162 23:45:22.578184 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8163 23:45:22.581438 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8164 23:45:22.585087 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8165 23:45:22.591599 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8166 23:45:22.594703 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8167 23:45:22.597665 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8168 23:45:22.600982 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8169 23:45:22.607590 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8170 23:45:22.611396 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8171 23:45:22.614566 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8172 23:45:22.621643 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8173 23:45:22.624228 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8174 23:45:22.627981 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8175 23:45:22.634877 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8176 23:45:22.637690 Total UI for P1: 0, mck2ui 16
8177 23:45:22.641036 best dqsien dly found for B0: ( 1, 0, 26)
8178 23:45:22.644388 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8179 23:45:22.647503 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8180 23:45:22.650981 Total UI for P1: 0, mck2ui 16
8181 23:45:22.654137 best dqsien dly found for B1: ( 1, 1, 2)
8182 23:45:22.657481 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8183 23:45:22.661063 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8184 23:45:22.661673
8185 23:45:22.667506 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8186 23:45:22.670796 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8187 23:45:22.671255 [Gating] SW calibration Done
8188 23:45:22.674298 ==
8189 23:45:22.677563 Dram Type= 6, Freq= 0, CH_1, rank 0
8190 23:45:22.681094 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8191 23:45:22.681706 ==
8192 23:45:22.682078 RX Vref Scan: 0
8193 23:45:22.682421
8194 23:45:22.684152 RX Vref 0 -> 0, step: 1
8195 23:45:22.684667
8196 23:45:22.687437 RX Delay 0 -> 252, step: 8
8197 23:45:22.691080 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8198 23:45:22.694113 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8199 23:45:22.697541 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8200 23:45:22.703856 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8201 23:45:22.707327 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8202 23:45:22.710704 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8203 23:45:22.713997 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8204 23:45:22.717120 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8205 23:45:22.724156 iDelay=200, Bit 8, Center 107 (56 ~ 159) 104
8206 23:45:22.727210 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8207 23:45:22.730543 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8208 23:45:22.733853 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8209 23:45:22.737363 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8210 23:45:22.744293 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8211 23:45:22.747504 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8212 23:45:22.750750 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8213 23:45:22.751305 ==
8214 23:45:22.754204 Dram Type= 6, Freq= 0, CH_1, rank 0
8215 23:45:22.757743 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8216 23:45:22.760520 ==
8217 23:45:22.761073 DQS Delay:
8218 23:45:22.761552 DQS0 = 0, DQS1 = 0
8219 23:45:22.763685 DQM Delay:
8220 23:45:22.764232 DQM0 = 131, DQM1 = 126
8221 23:45:22.766955 DQ Delay:
8222 23:45:22.770145 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8223 23:45:22.773798 DQ4 =131, DQ5 =143, DQ6 =135, DQ7 =127
8224 23:45:22.777116 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8225 23:45:22.780329 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8226 23:45:22.780882
8227 23:45:22.781244
8228 23:45:22.781625 ==
8229 23:45:22.783839 Dram Type= 6, Freq= 0, CH_1, rank 0
8230 23:45:22.786654 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8231 23:45:22.787115 ==
8232 23:45:22.787478
8233 23:45:22.790251
8234 23:45:22.790801 TX Vref Scan disable
8235 23:45:22.793807 == TX Byte 0 ==
8236 23:45:22.796745 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8237 23:45:22.800125 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8238 23:45:22.803790 == TX Byte 1 ==
8239 23:45:22.806648 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8240 23:45:22.810044 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8241 23:45:22.810531 ==
8242 23:45:22.813237 Dram Type= 6, Freq= 0, CH_1, rank 0
8243 23:45:22.819931 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8244 23:45:22.820490 ==
8245 23:45:22.831685
8246 23:45:22.834695 TX Vref early break, caculate TX vref
8247 23:45:22.837913 TX Vref=16, minBit 0, minWin=21, winSum=368
8248 23:45:22.840976 TX Vref=18, minBit 3, minWin=21, winSum=379
8249 23:45:22.844360 TX Vref=20, minBit 0, minWin=23, winSum=387
8250 23:45:22.847658 TX Vref=22, minBit 1, minWin=23, winSum=397
8251 23:45:22.851131 TX Vref=24, minBit 1, minWin=24, winSum=406
8252 23:45:22.857839 TX Vref=26, minBit 3, minWin=24, winSum=413
8253 23:45:22.861153 TX Vref=28, minBit 3, minWin=24, winSum=411
8254 23:45:22.864480 TX Vref=30, minBit 0, minWin=24, winSum=405
8255 23:45:22.867703 TX Vref=32, minBit 1, minWin=23, winSum=400
8256 23:45:22.871010 TX Vref=34, minBit 3, minWin=22, winSum=389
8257 23:45:22.877538 [TxChooseVref] Worse bit 3, Min win 24, Win sum 413, Final Vref 26
8258 23:45:22.878102
8259 23:45:22.880773 Final TX Range 0 Vref 26
8260 23:45:22.881373
8261 23:45:22.881743 ==
8262 23:45:22.884183 Dram Type= 6, Freq= 0, CH_1, rank 0
8263 23:45:22.887278 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8264 23:45:22.887838 ==
8265 23:45:22.888202
8266 23:45:22.888533
8267 23:45:22.890558 TX Vref Scan disable
8268 23:45:22.897225 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8269 23:45:22.897824 == TX Byte 0 ==
8270 23:45:22.900387 u2DelayCellOfst[0]=14 cells (4 PI)
8271 23:45:22.904053 u2DelayCellOfst[1]=10 cells (3 PI)
8272 23:45:22.906898 u2DelayCellOfst[2]=0 cells (0 PI)
8273 23:45:22.910755 u2DelayCellOfst[3]=7 cells (2 PI)
8274 23:45:22.913624 u2DelayCellOfst[4]=7 cells (2 PI)
8275 23:45:22.916835 u2DelayCellOfst[5]=14 cells (4 PI)
8276 23:45:22.920738 u2DelayCellOfst[6]=14 cells (4 PI)
8277 23:45:22.923981 u2DelayCellOfst[7]=3 cells (1 PI)
8278 23:45:22.927188 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8279 23:45:22.930177 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8280 23:45:22.933710 == TX Byte 1 ==
8281 23:45:22.937086 u2DelayCellOfst[8]=0 cells (0 PI)
8282 23:45:22.937674 u2DelayCellOfst[9]=3 cells (1 PI)
8283 23:45:22.940367 u2DelayCellOfst[10]=7 cells (2 PI)
8284 23:45:22.943897 u2DelayCellOfst[11]=3 cells (1 PI)
8285 23:45:22.946944 u2DelayCellOfst[12]=14 cells (4 PI)
8286 23:45:22.950113 u2DelayCellOfst[13]=18 cells (5 PI)
8287 23:45:22.953395 u2DelayCellOfst[14]=18 cells (5 PI)
8288 23:45:22.956554 u2DelayCellOfst[15]=14 cells (4 PI)
8289 23:45:22.960070 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8290 23:45:22.966869 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8291 23:45:22.967435 DramC Write-DBI on
8292 23:45:22.967797 ==
8293 23:45:22.969815 Dram Type= 6, Freq= 0, CH_1, rank 0
8294 23:45:22.976573 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8295 23:45:22.977125 ==
8296 23:45:22.977542
8297 23:45:22.977876
8298 23:45:22.978191 TX Vref Scan disable
8299 23:45:22.980339 == TX Byte 0 ==
8300 23:45:22.984076 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8301 23:45:22.986992 == TX Byte 1 ==
8302 23:45:22.990726 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8303 23:45:22.994224 DramC Write-DBI off
8304 23:45:22.994771
8305 23:45:22.995134 [DATLAT]
8306 23:45:22.995468 Freq=1600, CH1 RK0
8307 23:45:22.995790
8308 23:45:22.996763 DATLAT Default: 0xf
8309 23:45:22.997218 0, 0xFFFF, sum = 0
8310 23:45:23.000323 1, 0xFFFF, sum = 0
8311 23:45:23.003409 2, 0xFFFF, sum = 0
8312 23:45:23.003870 3, 0xFFFF, sum = 0
8313 23:45:23.006689 4, 0xFFFF, sum = 0
8314 23:45:23.007436 5, 0xFFFF, sum = 0
8315 23:45:23.009943 6, 0xFFFF, sum = 0
8316 23:45:23.010406 7, 0xFFFF, sum = 0
8317 23:45:23.013600 8, 0xFFFF, sum = 0
8318 23:45:23.014170 9, 0xFFFF, sum = 0
8319 23:45:23.016923 10, 0xFFFF, sum = 0
8320 23:45:23.017544 11, 0xFFFF, sum = 0
8321 23:45:23.020331 12, 0x8F7F, sum = 0
8322 23:45:23.020946 13, 0x0, sum = 1
8323 23:45:23.023808 14, 0x0, sum = 2
8324 23:45:23.024378 15, 0x0, sum = 3
8325 23:45:23.026866 16, 0x0, sum = 4
8326 23:45:23.027432 best_step = 14
8327 23:45:23.027794
8328 23:45:23.028129 ==
8329 23:45:23.029950 Dram Type= 6, Freq= 0, CH_1, rank 0
8330 23:45:23.033845 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8331 23:45:23.037130 ==
8332 23:45:23.037748 RX Vref Scan: 1
8333 23:45:23.038121
8334 23:45:23.040107 Set Vref Range= 24 -> 127
8335 23:45:23.040667
8336 23:45:23.043597 RX Vref 24 -> 127, step: 1
8337 23:45:23.044156
8338 23:45:23.044520 RX Delay 11 -> 252, step: 4
8339 23:45:23.044861
8340 23:45:23.046831 Set Vref, RX VrefLevel [Byte0]: 24
8341 23:45:23.050006 [Byte1]: 24
8342 23:45:23.053633
8343 23:45:23.054093 Set Vref, RX VrefLevel [Byte0]: 25
8344 23:45:23.056989 [Byte1]: 25
8345 23:45:23.061768
8346 23:45:23.062347 Set Vref, RX VrefLevel [Byte0]: 26
8347 23:45:23.064680 [Byte1]: 26
8348 23:45:23.069001
8349 23:45:23.069623 Set Vref, RX VrefLevel [Byte0]: 27
8350 23:45:23.072370 [Byte1]: 27
8351 23:45:23.076647
8352 23:45:23.077195 Set Vref, RX VrefLevel [Byte0]: 28
8353 23:45:23.079992 [Byte1]: 28
8354 23:45:23.084439
8355 23:45:23.085003 Set Vref, RX VrefLevel [Byte0]: 29
8356 23:45:23.087461 [Byte1]: 29
8357 23:45:23.092031
8358 23:45:23.092580 Set Vref, RX VrefLevel [Byte0]: 30
8359 23:45:23.094991 [Byte1]: 30
8360 23:45:23.099711
8361 23:45:23.100160 Set Vref, RX VrefLevel [Byte0]: 31
8362 23:45:23.102548 [Byte1]: 31
8363 23:45:23.107196
8364 23:45:23.107910 Set Vref, RX VrefLevel [Byte0]: 32
8365 23:45:23.110104 [Byte1]: 32
8366 23:45:23.114567
8367 23:45:23.115019 Set Vref, RX VrefLevel [Byte0]: 33
8368 23:45:23.117828 [Byte1]: 33
8369 23:45:23.122396
8370 23:45:23.122944 Set Vref, RX VrefLevel [Byte0]: 34
8371 23:45:23.126022 [Byte1]: 34
8372 23:45:23.129909
8373 23:45:23.130457 Set Vref, RX VrefLevel [Byte0]: 35
8374 23:45:23.133005 [Byte1]: 35
8375 23:45:23.137688
8376 23:45:23.138238 Set Vref, RX VrefLevel [Byte0]: 36
8377 23:45:23.140895 [Byte1]: 36
8378 23:45:23.145259
8379 23:45:23.145852 Set Vref, RX VrefLevel [Byte0]: 37
8380 23:45:23.148615 [Byte1]: 37
8381 23:45:23.152894
8382 23:45:23.153475 Set Vref, RX VrefLevel [Byte0]: 38
8383 23:45:23.155899 [Byte1]: 38
8384 23:45:23.160443
8385 23:45:23.161004 Set Vref, RX VrefLevel [Byte0]: 39
8386 23:45:23.163818 [Byte1]: 39
8387 23:45:23.167693
8388 23:45:23.168294 Set Vref, RX VrefLevel [Byte0]: 40
8389 23:45:23.171342 [Byte1]: 40
8390 23:45:23.175437
8391 23:45:23.175889 Set Vref, RX VrefLevel [Byte0]: 41
8392 23:45:23.178943 [Byte1]: 41
8393 23:45:23.183312
8394 23:45:23.183854 Set Vref, RX VrefLevel [Byte0]: 42
8395 23:45:23.186664 [Byte1]: 42
8396 23:45:23.190955
8397 23:45:23.191506 Set Vref, RX VrefLevel [Byte0]: 43
8398 23:45:23.194031 [Byte1]: 43
8399 23:45:23.198530
8400 23:45:23.199076 Set Vref, RX VrefLevel [Byte0]: 44
8401 23:45:23.201755 [Byte1]: 44
8402 23:45:23.205881
8403 23:45:23.206432 Set Vref, RX VrefLevel [Byte0]: 45
8404 23:45:23.209158 [Byte1]: 45
8405 23:45:23.213510
8406 23:45:23.213961 Set Vref, RX VrefLevel [Byte0]: 46
8407 23:45:23.217217 [Byte1]: 46
8408 23:45:23.221600
8409 23:45:23.222148 Set Vref, RX VrefLevel [Byte0]: 47
8410 23:45:23.224758 [Byte1]: 47
8411 23:45:23.228963
8412 23:45:23.229555 Set Vref, RX VrefLevel [Byte0]: 48
8413 23:45:23.232323 [Byte1]: 48
8414 23:45:23.236707
8415 23:45:23.237251 Set Vref, RX VrefLevel [Byte0]: 49
8416 23:45:23.239914 [Byte1]: 49
8417 23:45:23.244150
8418 23:45:23.244695 Set Vref, RX VrefLevel [Byte0]: 50
8419 23:45:23.247613 [Byte1]: 50
8420 23:45:23.251742
8421 23:45:23.252290 Set Vref, RX VrefLevel [Byte0]: 51
8422 23:45:23.254747 [Byte1]: 51
8423 23:45:23.259160
8424 23:45:23.259610 Set Vref, RX VrefLevel [Byte0]: 52
8425 23:45:23.262536 [Byte1]: 52
8426 23:45:23.266966
8427 23:45:23.267416 Set Vref, RX VrefLevel [Byte0]: 53
8428 23:45:23.270844 [Byte1]: 53
8429 23:45:23.275190
8430 23:45:23.275743 Set Vref, RX VrefLevel [Byte0]: 54
8431 23:45:23.278147 [Byte1]: 54
8432 23:45:23.282135
8433 23:45:23.282695 Set Vref, RX VrefLevel [Byte0]: 55
8434 23:45:23.285363 [Byte1]: 55
8435 23:45:23.289598
8436 23:45:23.290042 Set Vref, RX VrefLevel [Byte0]: 56
8437 23:45:23.293357 [Byte1]: 56
8438 23:45:23.297594
8439 23:45:23.298215 Set Vref, RX VrefLevel [Byte0]: 57
8440 23:45:23.300773 [Byte1]: 57
8441 23:45:23.304726
8442 23:45:23.305176 Set Vref, RX VrefLevel [Byte0]: 58
8443 23:45:23.308108 [Byte1]: 58
8444 23:45:23.312660
8445 23:45:23.313206 Set Vref, RX VrefLevel [Byte0]: 59
8446 23:45:23.316169 [Byte1]: 59
8447 23:45:23.320709
8448 23:45:23.321264 Set Vref, RX VrefLevel [Byte0]: 60
8449 23:45:23.323610 [Byte1]: 60
8450 23:45:23.328051
8451 23:45:23.328596 Set Vref, RX VrefLevel [Byte0]: 61
8452 23:45:23.330903 [Byte1]: 61
8453 23:45:23.335381
8454 23:45:23.335930 Set Vref, RX VrefLevel [Byte0]: 62
8455 23:45:23.338988 [Byte1]: 62
8456 23:45:23.343194
8457 23:45:23.343740 Set Vref, RX VrefLevel [Byte0]: 63
8458 23:45:23.346314 [Byte1]: 63
8459 23:45:23.350859
8460 23:45:23.351635 Set Vref, RX VrefLevel [Byte0]: 64
8461 23:45:23.353898 [Byte1]: 64
8462 23:45:23.358107
8463 23:45:23.358575 Set Vref, RX VrefLevel [Byte0]: 65
8464 23:45:23.361537 [Byte1]: 65
8465 23:45:23.365853
8466 23:45:23.366403 Set Vref, RX VrefLevel [Byte0]: 66
8467 23:45:23.369276 [Byte1]: 66
8468 23:45:23.373683
8469 23:45:23.374233 Set Vref, RX VrefLevel [Byte0]: 67
8470 23:45:23.376748 [Byte1]: 67
8471 23:45:23.381151
8472 23:45:23.381750 Set Vref, RX VrefLevel [Byte0]: 68
8473 23:45:23.384451 [Byte1]: 68
8474 23:45:23.388469
8475 23:45:23.388923 Set Vref, RX VrefLevel [Byte0]: 69
8476 23:45:23.392086 [Byte1]: 69
8477 23:45:23.396218
8478 23:45:23.396767 Set Vref, RX VrefLevel [Byte0]: 70
8479 23:45:23.400078 [Byte1]: 70
8480 23:45:23.403955
8481 23:45:23.404423 Set Vref, RX VrefLevel [Byte0]: 71
8482 23:45:23.407071 [Byte1]: 71
8483 23:45:23.411540
8484 23:45:23.411993 Set Vref, RX VrefLevel [Byte0]: 72
8485 23:45:23.414667 [Byte1]: 72
8486 23:45:23.419178
8487 23:45:23.419630 Set Vref, RX VrefLevel [Byte0]: 73
8488 23:45:23.422360 [Byte1]: 73
8489 23:45:23.426905
8490 23:45:23.427456 Set Vref, RX VrefLevel [Byte0]: 74
8491 23:45:23.429980 [Byte1]: 74
8492 23:45:23.434753
8493 23:45:23.435305 Final RX Vref Byte 0 = 61 to rank0
8494 23:45:23.437459 Final RX Vref Byte 1 = 52 to rank0
8495 23:45:23.440842 Final RX Vref Byte 0 = 61 to rank1
8496 23:45:23.444353 Final RX Vref Byte 1 = 52 to rank1==
8497 23:45:23.447447 Dram Type= 6, Freq= 0, CH_1, rank 0
8498 23:45:23.454293 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8499 23:45:23.454850 ==
8500 23:45:23.455316 DQS Delay:
8501 23:45:23.457342 DQS0 = 0, DQS1 = 0
8502 23:45:23.457798 DQM Delay:
8503 23:45:23.458157 DQM0 = 128, DQM1 = 124
8504 23:45:23.460630 DQ Delay:
8505 23:45:23.464234 DQ0 =134, DQ1 =122, DQ2 =116, DQ3 =128
8506 23:45:23.467443 DQ4 =128, DQ5 =138, DQ6 =138, DQ7 =126
8507 23:45:23.470731 DQ8 =106, DQ9 =114, DQ10 =126, DQ11 =114
8508 23:45:23.473989 DQ12 =130, DQ13 =134, DQ14 =134, DQ15 =134
8509 23:45:23.474543
8510 23:45:23.474901
8511 23:45:23.475231
8512 23:45:23.477915 [DramC_TX_OE_Calibration] TA2
8513 23:45:23.480947 Original DQ_B0 (3 6) =30, OEN = 27
8514 23:45:23.484121 Original DQ_B1 (3 6) =30, OEN = 27
8515 23:45:23.487491 24, 0x0, End_B0=24 End_B1=24
8516 23:45:23.488056 25, 0x0, End_B0=25 End_B1=25
8517 23:45:23.490543 26, 0x0, End_B0=26 End_B1=26
8518 23:45:23.493991 27, 0x0, End_B0=27 End_B1=27
8519 23:45:23.497356 28, 0x0, End_B0=28 End_B1=28
8520 23:45:23.500897 29, 0x0, End_B0=29 End_B1=29
8521 23:45:23.501524 30, 0x0, End_B0=30 End_B1=30
8522 23:45:23.504108 31, 0x4141, End_B0=30 End_B1=30
8523 23:45:23.507205 Byte0 end_step=30 best_step=27
8524 23:45:23.510189 Byte1 end_step=30 best_step=27
8525 23:45:23.513870 Byte0 TX OE(2T, 0.5T) = (3, 3)
8526 23:45:23.517198 Byte1 TX OE(2T, 0.5T) = (3, 3)
8527 23:45:23.517813
8528 23:45:23.518284
8529 23:45:23.523961 [DQSOSCAuto] RK0, (LSB)MR18= 0x2828, (MSB)MR19= 0x303, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
8530 23:45:23.527237 CH1 RK0: MR19=303, MR18=2828
8531 23:45:23.533689 CH1_RK0: MR19=0x303, MR18=0x2828, DQSOSC=389, MR23=63, INC=24, DEC=16
8532 23:45:23.534277
8533 23:45:23.536925 ----->DramcWriteLeveling(PI) begin...
8534 23:45:23.537442 ==
8535 23:45:23.540123 Dram Type= 6, Freq= 0, CH_1, rank 1
8536 23:45:23.543298 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8537 23:45:23.543885 ==
8538 23:45:23.546798 Write leveling (Byte 0): 23 => 23
8539 23:45:23.549862 Write leveling (Byte 1): 20 => 20
8540 23:45:23.553473 DramcWriteLeveling(PI) end<-----
8541 23:45:23.554071
8542 23:45:23.554546 ==
8543 23:45:23.556620 Dram Type= 6, Freq= 0, CH_1, rank 1
8544 23:45:23.559817 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8545 23:45:23.560299 ==
8546 23:45:23.563360 [Gating] SW mode calibration
8547 23:45:23.570499 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8548 23:45:23.576565 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8549 23:45:23.579764 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8550 23:45:23.586323 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8551 23:45:23.589614 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8552 23:45:23.593145 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8553 23:45:23.599596 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8554 23:45:23.602979 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8555 23:45:23.605843 0 12 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8556 23:45:23.612850 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8557 23:45:23.616136 0 13 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8558 23:45:23.619463 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8559 23:45:23.625965 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8560 23:45:23.629403 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8561 23:45:23.632736 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8562 23:45:23.639619 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8563 23:45:23.643033 0 13 24 | B1->B0 | 2323 3434 | 0 1 | (0 0) (0 0)
8564 23:45:23.646150 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8565 23:45:23.653082 0 14 0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8566 23:45:23.655787 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8567 23:45:23.659267 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8568 23:45:23.665559 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8569 23:45:23.668787 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8570 23:45:23.672140 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8571 23:45:23.678812 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8572 23:45:23.682084 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8573 23:45:23.685411 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8574 23:45:23.692305 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8575 23:45:23.695606 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8576 23:45:23.698822 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8577 23:45:23.705344 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8578 23:45:23.708355 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8579 23:45:23.711911 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8580 23:45:23.718664 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8581 23:45:23.721946 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8582 23:45:23.725283 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8583 23:45:23.731962 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8584 23:45:23.735308 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8585 23:45:23.738285 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8586 23:45:23.745487 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8587 23:45:23.748300 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8588 23:45:23.751652 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8589 23:45:23.754642 Total UI for P1: 0, mck2ui 16
8590 23:45:23.758183 best dqsien dly found for B0: ( 1, 0, 24)
8591 23:45:23.761323 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8592 23:45:23.768094 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8593 23:45:23.771354 Total UI for P1: 0, mck2ui 16
8594 23:45:23.774766 best dqsien dly found for B1: ( 1, 0, 30)
8595 23:45:23.778624 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8596 23:45:23.781204 best DQS1 dly(MCK, UI, PI) = (1, 0, 30)
8597 23:45:23.781694
8598 23:45:23.784709 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8599 23:45:23.787982 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 30)
8600 23:45:23.791261 [Gating] SW calibration Done
8601 23:45:23.791814 ==
8602 23:45:23.794685 Dram Type= 6, Freq= 0, CH_1, rank 1
8603 23:45:23.798069 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8604 23:45:23.798626 ==
8605 23:45:23.801263 RX Vref Scan: 0
8606 23:45:23.801847
8607 23:45:23.804315 RX Vref 0 -> 0, step: 1
8608 23:45:23.804763
8609 23:45:23.805116 RX Delay 0 -> 252, step: 8
8610 23:45:23.810968 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8611 23:45:23.814693 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8612 23:45:23.817598 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8613 23:45:23.820721 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8614 23:45:23.824473 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8615 23:45:23.831176 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8616 23:45:23.834580 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8617 23:45:23.837598 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8618 23:45:23.841073 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8619 23:45:23.844556 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8620 23:45:23.850948 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8621 23:45:23.854243 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8622 23:45:23.857365 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8623 23:45:23.860817 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8624 23:45:23.864525 iDelay=200, Bit 14, Center 135 (72 ~ 199) 128
8625 23:45:23.870622 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8626 23:45:23.871177 ==
8627 23:45:23.874099 Dram Type= 6, Freq= 0, CH_1, rank 1
8628 23:45:23.877125 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8629 23:45:23.877732 ==
8630 23:45:23.878093 DQS Delay:
8631 23:45:23.880281 DQS0 = 0, DQS1 = 0
8632 23:45:23.880731 DQM Delay:
8633 23:45:23.883920 DQM0 = 131, DQM1 = 125
8634 23:45:23.884471 DQ Delay:
8635 23:45:23.886881 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8636 23:45:23.890437 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8637 23:45:23.894002 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8638 23:45:23.900714 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8639 23:45:23.901276
8640 23:45:23.901695
8641 23:45:23.902029 ==
8642 23:45:23.903523 Dram Type= 6, Freq= 0, CH_1, rank 1
8643 23:45:23.906900 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8644 23:45:23.907353 ==
8645 23:45:23.907709
8646 23:45:23.908035
8647 23:45:23.910062 TX Vref Scan disable
8648 23:45:23.910514 == TX Byte 0 ==
8649 23:45:23.916787 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8650 23:45:23.920148 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8651 23:45:23.920701 == TX Byte 1 ==
8652 23:45:23.926670 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8653 23:45:23.929764 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8654 23:45:23.930217 ==
8655 23:45:23.933530 Dram Type= 6, Freq= 0, CH_1, rank 1
8656 23:45:23.936685 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8657 23:45:23.937235 ==
8658 23:45:23.951625
8659 23:45:23.954833 TX Vref early break, caculate TX vref
8660 23:45:23.958011 TX Vref=16, minBit 5, minWin=21, winSum=376
8661 23:45:23.961357 TX Vref=18, minBit 0, minWin=22, winSum=385
8662 23:45:23.964727 TX Vref=20, minBit 0, minWin=23, winSum=394
8663 23:45:23.968090 TX Vref=22, minBit 0, minWin=23, winSum=400
8664 23:45:23.971202 TX Vref=24, minBit 0, minWin=24, winSum=407
8665 23:45:23.978100 TX Vref=26, minBit 0, minWin=24, winSum=417
8666 23:45:23.981562 TX Vref=28, minBit 0, minWin=24, winSum=418
8667 23:45:23.984514 TX Vref=30, minBit 0, minWin=23, winSum=416
8668 23:45:23.987911 TX Vref=32, minBit 0, minWin=23, winSum=411
8669 23:45:23.991309 TX Vref=34, minBit 0, minWin=22, winSum=401
8670 23:45:23.994655 TX Vref=36, minBit 0, minWin=21, winSum=388
8671 23:45:24.001204 [TxChooseVref] Worse bit 0, Min win 24, Win sum 418, Final Vref 28
8672 23:45:24.001644
8673 23:45:24.004452 Final TX Range 0 Vref 28
8674 23:45:24.004875
8675 23:45:24.005196 ==
8676 23:45:24.007618 Dram Type= 6, Freq= 0, CH_1, rank 1
8677 23:45:24.010998 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8678 23:45:24.011563 ==
8679 23:45:24.011947
8680 23:45:24.014260
8681 23:45:24.014702 TX Vref Scan disable
8682 23:45:24.020983 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8683 23:45:24.021434 == TX Byte 0 ==
8684 23:45:24.024318 u2DelayCellOfst[0]=18 cells (5 PI)
8685 23:45:24.027455 u2DelayCellOfst[1]=14 cells (4 PI)
8686 23:45:24.030760 u2DelayCellOfst[2]=0 cells (0 PI)
8687 23:45:24.034239 u2DelayCellOfst[3]=7 cells (2 PI)
8688 23:45:24.037520 u2DelayCellOfst[4]=10 cells (3 PI)
8689 23:45:24.041064 u2DelayCellOfst[5]=21 cells (6 PI)
8690 23:45:24.044299 u2DelayCellOfst[6]=18 cells (5 PI)
8691 23:45:24.047402 u2DelayCellOfst[7]=7 cells (2 PI)
8692 23:45:24.050849 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8693 23:45:24.054105 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8694 23:45:24.057503 == TX Byte 1 ==
8695 23:45:24.060655 u2DelayCellOfst[8]=0 cells (0 PI)
8696 23:45:24.064062 u2DelayCellOfst[9]=3 cells (1 PI)
8697 23:45:24.064514 u2DelayCellOfst[10]=7 cells (2 PI)
8698 23:45:24.067499 u2DelayCellOfst[11]=3 cells (1 PI)
8699 23:45:24.070718 u2DelayCellOfst[12]=14 cells (4 PI)
8700 23:45:24.074178 u2DelayCellOfst[13]=18 cells (5 PI)
8701 23:45:24.077507 u2DelayCellOfst[14]=18 cells (5 PI)
8702 23:45:24.080612 u2DelayCellOfst[15]=18 cells (5 PI)
8703 23:45:24.087721 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8704 23:45:24.090651 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8705 23:45:24.091105 DramC Write-DBI on
8706 23:45:24.091512 ==
8707 23:45:24.094094 Dram Type= 6, Freq= 0, CH_1, rank 1
8708 23:45:24.100736 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8709 23:45:24.101324 ==
8710 23:45:24.101700
8711 23:45:24.102027
8712 23:45:24.102338 TX Vref Scan disable
8713 23:45:24.104632 == TX Byte 0 ==
8714 23:45:24.107756 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8715 23:45:24.111155 == TX Byte 1 ==
8716 23:45:24.114313 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8717 23:45:24.118035 DramC Write-DBI off
8718 23:45:24.118485
8719 23:45:24.118838 [DATLAT]
8720 23:45:24.119167 Freq=1600, CH1 RK1
8721 23:45:24.119568
8722 23:45:24.121392 DATLAT Default: 0xe
8723 23:45:24.121844 0, 0xFFFF, sum = 0
8724 23:45:24.124523 1, 0xFFFF, sum = 0
8725 23:45:24.128005 2, 0xFFFF, sum = 0
8726 23:45:24.128559 3, 0xFFFF, sum = 0
8727 23:45:24.131139 4, 0xFFFF, sum = 0
8728 23:45:24.131724 5, 0xFFFF, sum = 0
8729 23:45:24.134475 6, 0xFFFF, sum = 0
8730 23:45:24.135035 7, 0xFFFF, sum = 0
8731 23:45:24.137655 8, 0xFFFF, sum = 0
8732 23:45:24.138117 9, 0xFFFF, sum = 0
8733 23:45:24.140848 10, 0xFFFF, sum = 0
8734 23:45:24.141329 11, 0xFFFF, sum = 0
8735 23:45:24.144751 12, 0xF7F, sum = 0
8736 23:45:24.145337 13, 0x0, sum = 1
8737 23:45:24.147866 14, 0x0, sum = 2
8738 23:45:24.148425 15, 0x0, sum = 3
8739 23:45:24.150911 16, 0x0, sum = 4
8740 23:45:24.151371 best_step = 14
8741 23:45:24.151723
8742 23:45:24.152053 ==
8743 23:45:24.154058 Dram Type= 6, Freq= 0, CH_1, rank 1
8744 23:45:24.157463 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8745 23:45:24.161198 ==
8746 23:45:24.161781 RX Vref Scan: 0
8747 23:45:24.162137
8748 23:45:24.164423 RX Vref 0 -> 0, step: 1
8749 23:45:24.164875
8750 23:45:24.165224 RX Delay 3 -> 252, step: 4
8751 23:45:24.171775 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8752 23:45:24.174801 iDelay=195, Bit 1, Center 122 (67 ~ 178) 112
8753 23:45:24.178169 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8754 23:45:24.181539 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8755 23:45:24.184747 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8756 23:45:24.191416 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8757 23:45:24.194703 iDelay=195, Bit 6, Center 134 (79 ~ 190) 112
8758 23:45:24.198250 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8759 23:45:24.201577 iDelay=195, Bit 8, Center 106 (51 ~ 162) 112
8760 23:45:24.204474 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8761 23:45:24.211371 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8762 23:45:24.214381 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8763 23:45:24.217902 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8764 23:45:24.221173 iDelay=195, Bit 13, Center 130 (79 ~ 182) 104
8765 23:45:24.227843 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8766 23:45:24.231088 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8767 23:45:24.231637 ==
8768 23:45:24.234081 Dram Type= 6, Freq= 0, CH_1, rank 1
8769 23:45:24.237383 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8770 23:45:24.237839 ==
8771 23:45:24.241077 DQS Delay:
8772 23:45:24.241672 DQS0 = 0, DQS1 = 0
8773 23:45:24.242031 DQM Delay:
8774 23:45:24.244298 DQM0 = 126, DQM1 = 122
8775 23:45:24.244845 DQ Delay:
8776 23:45:24.247660 DQ0 =128, DQ1 =122, DQ2 =116, DQ3 =124
8777 23:45:24.250758 DQ4 =126, DQ5 =138, DQ6 =134, DQ7 =126
8778 23:45:24.254319 DQ8 =106, DQ9 =112, DQ10 =122, DQ11 =114
8779 23:45:24.260946 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =132
8780 23:45:24.261533
8781 23:45:24.261888
8782 23:45:24.262211
8783 23:45:24.264250 [DramC_TX_OE_Calibration] TA2
8784 23:45:24.267688 Original DQ_B0 (3 6) =30, OEN = 27
8785 23:45:24.268241 Original DQ_B1 (3 6) =30, OEN = 27
8786 23:45:24.270877 24, 0x0, End_B0=24 End_B1=24
8787 23:45:24.274225 25, 0x0, End_B0=25 End_B1=25
8788 23:45:24.277697 26, 0x0, End_B0=26 End_B1=26
8789 23:45:24.280782 27, 0x0, End_B0=27 End_B1=27
8790 23:45:24.281247 28, 0x0, End_B0=28 End_B1=28
8791 23:45:24.283953 29, 0x0, End_B0=29 End_B1=29
8792 23:45:24.287492 30, 0x0, End_B0=30 End_B1=30
8793 23:45:24.290841 31, 0x5151, End_B0=30 End_B1=30
8794 23:45:24.293825 Byte0 end_step=30 best_step=27
8795 23:45:24.297410 Byte1 end_step=30 best_step=27
8796 23:45:24.297957 Byte0 TX OE(2T, 0.5T) = (3, 3)
8797 23:45:24.300675 Byte1 TX OE(2T, 0.5T) = (3, 3)
8798 23:45:24.301222
8799 23:45:24.301634
8800 23:45:24.310244 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
8801 23:45:24.313819 CH1 RK1: MR19=303, MR18=1B1B
8802 23:45:24.317483 CH1_RK1: MR19=0x303, MR18=0x1B1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8803 23:45:24.320499 [RxdqsGatingPostProcess] freq 1600
8804 23:45:24.327067 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8805 23:45:24.330180 Pre-setting of DQS Precalculation
8806 23:45:24.333621 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8807 23:45:24.343499 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8808 23:45:24.350090 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8809 23:45:24.350630
8810 23:45:24.350986
8811 23:45:24.353533 [Calibration Summary] 3200 Mbps
8812 23:45:24.353982 CH 0, Rank 0
8813 23:45:24.356964 SW Impedance : PASS
8814 23:45:24.357592 DUTY Scan : NO K
8815 23:45:24.360503 ZQ Calibration : PASS
8816 23:45:24.363987 Jitter Meter : NO K
8817 23:45:24.364647 CBT Training : PASS
8818 23:45:24.366939 Write leveling : PASS
8819 23:45:24.370121 RX DQS gating : PASS
8820 23:45:24.370577 RX DQ/DQS(RDDQC) : PASS
8821 23:45:24.373399 TX DQ/DQS : PASS
8822 23:45:24.376776 RX DATLAT : PASS
8823 23:45:24.377363 RX DQ/DQS(Engine): PASS
8824 23:45:24.380341 TX OE : PASS
8825 23:45:24.380890 All Pass.
8826 23:45:24.381247
8827 23:45:24.383321 CH 0, Rank 1
8828 23:45:24.383769 SW Impedance : PASS
8829 23:45:24.386513 DUTY Scan : NO K
8830 23:45:24.390029 ZQ Calibration : PASS
8831 23:45:24.390478 Jitter Meter : NO K
8832 23:45:24.393463 CBT Training : PASS
8833 23:45:24.394012 Write leveling : PASS
8834 23:45:24.396897 RX DQS gating : PASS
8835 23:45:24.400417 RX DQ/DQS(RDDQC) : PASS
8836 23:45:24.400971 TX DQ/DQS : PASS
8837 23:45:24.403097 RX DATLAT : PASS
8838 23:45:24.406390 RX DQ/DQS(Engine): PASS
8839 23:45:24.406842 TX OE : PASS
8840 23:45:24.409803 All Pass.
8841 23:45:24.410255
8842 23:45:24.410609 CH 1, Rank 0
8843 23:45:24.413160 SW Impedance : PASS
8844 23:45:24.413653 DUTY Scan : NO K
8845 23:45:24.416294 ZQ Calibration : PASS
8846 23:45:24.419937 Jitter Meter : NO K
8847 23:45:24.420483 CBT Training : PASS
8848 23:45:24.423308 Write leveling : PASS
8849 23:45:24.426652 RX DQS gating : PASS
8850 23:45:24.427200 RX DQ/DQS(RDDQC) : PASS
8851 23:45:24.429828 TX DQ/DQS : PASS
8852 23:45:24.433182 RX DATLAT : PASS
8853 23:45:24.433776 RX DQ/DQS(Engine): PASS
8854 23:45:24.436301 TX OE : PASS
8855 23:45:24.436752 All Pass.
8856 23:45:24.437102
8857 23:45:24.439635 CH 1, Rank 1
8858 23:45:24.440086 SW Impedance : PASS
8859 23:45:24.443041 DUTY Scan : NO K
8860 23:45:24.446641 ZQ Calibration : PASS
8861 23:45:24.447193 Jitter Meter : NO K
8862 23:45:24.449388 CBT Training : PASS
8863 23:45:24.452890 Write leveling : PASS
8864 23:45:24.453486 RX DQS gating : PASS
8865 23:45:24.456145 RX DQ/DQS(RDDQC) : PASS
8866 23:45:24.456596 TX DQ/DQS : PASS
8867 23:45:24.459229 RX DATLAT : PASS
8868 23:45:24.462624 RX DQ/DQS(Engine): PASS
8869 23:45:24.463076 TX OE : PASS
8870 23:45:24.466567 All Pass.
8871 23:45:24.467116
8872 23:45:24.467470 DramC Write-DBI on
8873 23:45:24.469708 PER_BANK_REFRESH: Hybrid Mode
8874 23:45:24.472879 TX_TRACKING: ON
8875 23:45:24.479288 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8876 23:45:24.489278 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8877 23:45:24.496101 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8878 23:45:24.499159 [FAST_K] Save calibration result to emmc
8879 23:45:24.502690 sync common calibartion params.
8880 23:45:24.503242 sync cbt_mode0:0, 1:0
8881 23:45:24.505646 dram_init: ddr_geometry: 0
8882 23:45:24.509124 dram_init: ddr_geometry: 0
8883 23:45:24.512612 dram_init: ddr_geometry: 0
8884 23:45:24.513152 0:dram_rank_size:80000000
8885 23:45:24.515611 1:dram_rank_size:80000000
8886 23:45:24.522388 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8887 23:45:24.522941 DFS_SHUFFLE_HW_MODE: ON
8888 23:45:24.525862 dramc_set_vcore_voltage set vcore to 725000
8889 23:45:24.529426 Read voltage for 1600, 0
8890 23:45:24.529969 Vio18 = 0
8891 23:45:24.532491 Vcore = 725000
8892 23:45:24.533042 Vdram = 0
8893 23:45:24.533459 Vddq = 0
8894 23:45:24.535781 Vmddr = 0
8895 23:45:24.536234 switch to 3200 Mbps bootup
8896 23:45:24.539426 [DramcRunTimeConfig]
8897 23:45:24.539973 PHYPLL
8898 23:45:24.542454 DPM_CONTROL_AFTERK: ON
8899 23:45:24.543055 PER_BANK_REFRESH: ON
8900 23:45:24.545860 REFRESH_OVERHEAD_REDUCTION: ON
8901 23:45:24.549444 CMD_PICG_NEW_MODE: OFF
8902 23:45:24.550001 XRTWTW_NEW_MODE: ON
8903 23:45:24.552449 XRTRTR_NEW_MODE: ON
8904 23:45:24.552994 TX_TRACKING: ON
8905 23:45:24.555886 RDSEL_TRACKING: OFF
8906 23:45:24.558815 DQS Precalculation for DVFS: ON
8907 23:45:24.559271 RX_TRACKING: OFF
8908 23:45:24.562295 HW_GATING DBG: ON
8909 23:45:24.562755 ZQCS_ENABLE_LP4: ON
8910 23:45:24.565673 RX_PICG_NEW_MODE: ON
8911 23:45:24.566223 TX_PICG_NEW_MODE: ON
8912 23:45:24.569030 ENABLE_RX_DCM_DPHY: ON
8913 23:45:24.572313 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8914 23:45:24.575583 DUMMY_READ_FOR_TRACKING: OFF
8915 23:45:24.576130 !!! SPM_CONTROL_AFTERK: OFF
8916 23:45:24.578935 !!! SPM could not control APHY
8917 23:45:24.582119 IMPEDANCE_TRACKING: ON
8918 23:45:24.582669 TEMP_SENSOR: ON
8919 23:45:24.585571 HW_SAVE_FOR_SR: OFF
8920 23:45:24.588799 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8921 23:45:24.592312 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8922 23:45:24.595472 Read ODT Tracking: ON
8923 23:45:24.596025 Refresh Rate DeBounce: ON
8924 23:45:24.598527 DFS_NO_QUEUE_FLUSH: ON
8925 23:45:24.602081 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8926 23:45:24.605327 ENABLE_DFS_RUNTIME_MRW: OFF
8927 23:45:24.605796 DDR_RESERVE_NEW_MODE: ON
8928 23:45:24.608819 MR_CBT_SWITCH_FREQ: ON
8929 23:45:24.612111 =========================
8930 23:45:24.629328 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8931 23:45:24.632832 dram_init: ddr_geometry: 0
8932 23:45:24.650543 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8933 23:45:24.653779 dram_init: dram init end (result: 0)
8934 23:45:24.660254 DRAM-K: Full calibration passed in 23436 msecs
8935 23:45:24.663790 MRC: failed to locate region type 0.
8936 23:45:24.664348 DRAM rank0 size:0x80000000,
8937 23:45:24.667400 DRAM rank1 size=0x80000000
8938 23:45:24.677081 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8939 23:45:24.683849 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8940 23:45:24.690028 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8941 23:45:24.696821 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8942 23:45:24.699941 DRAM rank0 size:0x80000000,
8943 23:45:24.703437 DRAM rank1 size=0x80000000
8944 23:45:24.703997 CBMEM:
8945 23:45:24.706951 IMD: root @ 0xfffff000 254 entries.
8946 23:45:24.710146 IMD: root @ 0xffffec00 62 entries.
8947 23:45:24.713255 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8948 23:45:24.716438 WARNING: RO_VPD is uninitialized or empty.
8949 23:45:24.723239 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8950 23:45:24.730028 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8951 23:45:24.742874 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
8952 23:45:24.754428 BS: romstage times (exec / console): total (unknown) / 22972 ms
8953 23:45:24.754993
8954 23:45:24.755355
8955 23:45:24.764523 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8956 23:45:24.767668 ARM64: Exception handlers installed.
8957 23:45:24.770816 ARM64: Testing exception
8958 23:45:24.774339 ARM64: Done test exception
8959 23:45:24.774792 Enumerating buses...
8960 23:45:24.777412 Show all devs... Before device enumeration.
8961 23:45:24.780719 Root Device: enabled 1
8962 23:45:24.784024 CPU_CLUSTER: 0: enabled 1
8963 23:45:24.784476 CPU: 00: enabled 1
8964 23:45:24.787497 Compare with tree...
8965 23:45:24.788132 Root Device: enabled 1
8966 23:45:24.790544 CPU_CLUSTER: 0: enabled 1
8967 23:45:24.793882 CPU: 00: enabled 1
8968 23:45:24.794334 Root Device scanning...
8969 23:45:24.797403 scan_static_bus for Root Device
8970 23:45:24.800663 CPU_CLUSTER: 0 enabled
8971 23:45:24.804016 scan_static_bus for Root Device done
8972 23:45:24.807642 scan_bus: bus Root Device finished in 8 msecs
8973 23:45:24.808106 done
8974 23:45:24.813897 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8975 23:45:24.817102 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8976 23:45:24.823822 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8977 23:45:24.827086 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8978 23:45:24.830312 Allocating resources...
8979 23:45:24.833775 Reading resources...
8980 23:45:24.837036 Root Device read_resources bus 0 link: 0
8981 23:45:24.837568 DRAM rank0 size:0x80000000,
8982 23:45:24.840276 DRAM rank1 size=0x80000000
8983 23:45:24.843511 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8984 23:45:24.846951 CPU: 00 missing read_resources
8985 23:45:24.850240 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8986 23:45:24.857139 Root Device read_resources bus 0 link: 0 done
8987 23:45:24.857717 Done reading resources.
8988 23:45:24.863395 Show resources in subtree (Root Device)...After reading.
8989 23:45:24.866754 Root Device child on link 0 CPU_CLUSTER: 0
8990 23:45:24.870027 CPU_CLUSTER: 0 child on link 0 CPU: 00
8991 23:45:24.880162 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8992 23:45:24.880706 CPU: 00
8993 23:45:24.883502 Root Device assign_resources, bus 0 link: 0
8994 23:45:24.886742 CPU_CLUSTER: 0 missing set_resources
8995 23:45:24.893946 Root Device assign_resources, bus 0 link: 0 done
8996 23:45:24.894517 Done setting resources.
8997 23:45:24.900028 Show resources in subtree (Root Device)...After assigning values.
8998 23:45:24.903071 Root Device child on link 0 CPU_CLUSTER: 0
8999 23:45:24.906283 CPU_CLUSTER: 0 child on link 0 CPU: 00
9000 23:45:24.916260 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9001 23:45:24.916998 CPU: 00
9002 23:45:24.919943 Done allocating resources.
9003 23:45:24.923542 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9004 23:45:24.926150 Enabling resources...
9005 23:45:24.926629 done.
9006 23:45:24.933385 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9007 23:45:24.933945 Initializing devices...
9008 23:45:24.936403 Root Device init
9009 23:45:24.936963 init hardware done!
9010 23:45:24.939578 0x00000018: ctrlr->caps
9011 23:45:24.943056 52.000 MHz: ctrlr->f_max
9012 23:45:24.943635 0.400 MHz: ctrlr->f_min
9013 23:45:24.946021 0x40ff8080: ctrlr->voltages
9014 23:45:24.949674 sclk: 390625
9015 23:45:24.950234 Bus Width = 1
9016 23:45:24.950596 sclk: 390625
9017 23:45:24.952823 Bus Width = 1
9018 23:45:24.953436 Early init status = 3
9019 23:45:24.959062 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9020 23:45:24.962481 in-header: 03 fc 00 00 01 00 00 00
9021 23:45:24.965838 in-data: 00
9022 23:45:24.969245 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9023 23:45:24.974956 in-header: 03 fd 00 00 00 00 00 00
9024 23:45:24.978514 in-data:
9025 23:45:24.981541 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9026 23:45:24.986089 in-header: 03 fc 00 00 01 00 00 00
9027 23:45:24.989339 in-data: 00
9028 23:45:24.992688 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9029 23:45:24.998240 in-header: 03 fd 00 00 00 00 00 00
9030 23:45:25.001593 in-data:
9031 23:45:25.005147 [SSUSB] Setting up USB HOST controller...
9032 23:45:25.008143 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9033 23:45:25.011332 [SSUSB] phy power-on done.
9034 23:45:25.014882 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9035 23:45:25.021713 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9036 23:45:25.024582 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9037 23:45:25.031599 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9038 23:45:25.037970 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9039 23:45:25.044633 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9040 23:45:25.051113 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9041 23:45:25.057649 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9042 23:45:25.060654 SPM: binary array size = 0x9dc
9043 23:45:25.064153 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9044 23:45:25.070910 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9045 23:45:25.077672 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9046 23:45:25.084438 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9047 23:45:25.087912 configure_display: Starting display init
9048 23:45:25.121772 anx7625_power_on_init: Init interface.
9049 23:45:25.124979 anx7625_disable_pd_protocol: Disabled PD feature.
9050 23:45:25.128091 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9051 23:45:25.156136 anx7625_start_dp_work: Secure OCM version=00
9052 23:45:25.159040 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9053 23:45:25.174080 sp_tx_get_edid_block: EDID Block = 1
9054 23:45:25.276811 Extracted contents:
9055 23:45:25.279968 header: 00 ff ff ff ff ff ff 00
9056 23:45:25.283239 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9057 23:45:25.286573 version: 01 04
9058 23:45:25.289970 basic params: 95 1f 11 78 0a
9059 23:45:25.293195 chroma info: 76 90 94 55 54 90 27 21 50 54
9060 23:45:25.296673 established: 00 00 00
9061 23:45:25.303240 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9062 23:45:25.306226 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9063 23:45:25.312651 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9064 23:45:25.319191 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9065 23:45:25.326185 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9066 23:45:25.329581 extensions: 00
9067 23:45:25.330136 checksum: fb
9068 23:45:25.330497
9069 23:45:25.335954 Manufacturer: IVO Model 57d Serial Number 0
9070 23:45:25.336517 Made week 0 of 2020
9071 23:45:25.339285 EDID version: 1.4
9072 23:45:25.339902 Digital display
9073 23:45:25.342466 6 bits per primary color channel
9074 23:45:25.342930 DisplayPort interface
9075 23:45:25.345509 Maximum image size: 31 cm x 17 cm
9076 23:45:25.349174 Gamma: 220%
9077 23:45:25.349821 Check DPMS levels
9078 23:45:25.355832 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9079 23:45:25.358770 First detailed timing is preferred timing
9080 23:45:25.359328 Established timings supported:
9081 23:45:25.362089 Standard timings supported:
9082 23:45:25.365480 Detailed timings
9083 23:45:25.368940 Hex of detail: 383680a07038204018303c0035ae10000019
9084 23:45:25.375456 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9085 23:45:25.379020 0780 0798 07c8 0820 hborder 0
9086 23:45:25.382164 0438 043b 0447 0458 vborder 0
9087 23:45:25.385637 -hsync -vsync
9088 23:45:25.386195 Did detailed timing
9089 23:45:25.392054 Hex of detail: 000000000000000000000000000000000000
9090 23:45:25.395067 Manufacturer-specified data, tag 0
9091 23:45:25.398614 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9092 23:45:25.402034 ASCII string: InfoVision
9093 23:45:25.405378 Hex of detail: 000000fe00523134304e574635205248200a
9094 23:45:25.408648 ASCII string: R140NWF5 RH
9095 23:45:25.409133 Checksum
9096 23:45:25.411943 Checksum: 0xfb (valid)
9097 23:45:25.414850 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9098 23:45:25.418087 DSI data_rate: 832800000 bps
9099 23:45:25.424714 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9100 23:45:25.428462 anx7625_parse_edid: pixelclock(138800).
9101 23:45:25.431529 hactive(1920), hsync(48), hfp(24), hbp(88)
9102 23:45:25.434833 vactive(1080), vsync(12), vfp(3), vbp(17)
9103 23:45:25.437838 anx7625_dsi_config: config dsi.
9104 23:45:25.444706 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9105 23:45:25.458714 anx7625_dsi_config: success to config DSI
9106 23:45:25.461686 anx7625_dp_start: MIPI phy setup OK.
9107 23:45:25.465694 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9108 23:45:25.468474 mtk_ddp_mode_set invalid vrefresh 60
9109 23:45:25.471826 main_disp_path_setup
9110 23:45:25.472384 ovl_layer_smi_id_en
9111 23:45:25.475303 ovl_layer_smi_id_en
9112 23:45:25.475864 ccorr_config
9113 23:45:25.476225 aal_config
9114 23:45:25.478408 gamma_config
9115 23:45:25.478864 postmask_config
9116 23:45:25.481830 dither_config
9117 23:45:25.485589 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9118 23:45:25.491964 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9119 23:45:25.495214 Root Device init finished in 555 msecs
9120 23:45:25.498312 CPU_CLUSTER: 0 init
9121 23:45:25.505064 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9122 23:45:25.508213 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9123 23:45:25.511337 APU_MBOX 0x190000b0 = 0x10001
9124 23:45:25.514685 APU_MBOX 0x190001b0 = 0x10001
9125 23:45:25.517935 APU_MBOX 0x190005b0 = 0x10001
9126 23:45:25.521580 APU_MBOX 0x190006b0 = 0x10001
9127 23:45:25.527946 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9128 23:45:25.537674 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9129 23:45:25.549881 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9130 23:45:25.556444 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9131 23:45:25.568375 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9132 23:45:25.577418 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9133 23:45:25.580657 CPU_CLUSTER: 0 init finished in 81 msecs
9134 23:45:25.584069 Devices initialized
9135 23:45:25.587582 Show all devs... After init.
9136 23:45:25.588141 Root Device: enabled 1
9137 23:45:25.590519 CPU_CLUSTER: 0: enabled 1
9138 23:45:25.594023 CPU: 00: enabled 1
9139 23:45:25.596859 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9140 23:45:25.600280 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9141 23:45:25.603661 ELOG: NV offset 0x57f000 size 0x1000
9142 23:45:25.610243 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9143 23:45:25.617150 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9144 23:45:25.620366 ELOG: Event(17) added with size 13 at 2024-06-04 23:45:25 UTC
9145 23:45:25.626829 out: cmd=0x121: 03 db 21 01 00 00 00 00
9146 23:45:25.630229 in-header: 03 e7 00 00 2c 00 00 00
9147 23:45:25.643356 in-data: 7c 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9148 23:45:25.646938 ELOG: Event(A1) added with size 10 at 2024-06-04 23:45:25 UTC
9149 23:45:25.653355 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9150 23:45:25.660245 ELOG: Event(A0) added with size 9 at 2024-06-04 23:45:25 UTC
9151 23:45:25.663263 elog_add_boot_reason: Logged dev mode boot
9152 23:45:25.670026 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9153 23:45:25.670590 Finalize devices...
9154 23:45:25.673125 Devices finalized
9155 23:45:25.676239 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9156 23:45:25.679792 Writing coreboot table at 0xffe64000
9157 23:45:25.686396 0. 000000000010a000-0000000000113fff: RAMSTAGE
9158 23:45:25.689683 1. 0000000040000000-00000000400fffff: RAM
9159 23:45:25.692870 2. 0000000040100000-000000004032afff: RAMSTAGE
9160 23:45:25.696192 3. 000000004032b000-00000000545fffff: RAM
9161 23:45:25.699757 4. 0000000054600000-000000005465ffff: BL31
9162 23:45:25.706222 5. 0000000054660000-00000000ffe63fff: RAM
9163 23:45:25.709576 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9164 23:45:25.712427 7. 0000000100000000-000000013fffffff: RAM
9165 23:45:25.715744 Passing 5 GPIOs to payload:
9166 23:45:25.719072 NAME | PORT | POLARITY | VALUE
9167 23:45:25.725768 EC in RW | 0x000000aa | low | undefined
9168 23:45:25.729050 EC interrupt | 0x00000005 | low | undefined
9169 23:45:25.735735 TPM interrupt | 0x000000ab | high | undefined
9170 23:45:25.739634 SD card detect | 0x00000011 | high | undefined
9171 23:45:25.742146 speaker enable | 0x00000093 | high | undefined
9172 23:45:25.749358 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9173 23:45:25.752099 in-header: 03 f8 00 00 02 00 00 00
9174 23:45:25.752556 in-data: 03 00
9175 23:45:25.755692 ADC[4]: Raw value=668590 ID=5
9176 23:45:25.758717 ADC[3]: Raw value=212549 ID=1
9177 23:45:25.759173 RAM Code: 0x51
9178 23:45:25.761969 ADC[6]: Raw value=74410 ID=0
9179 23:45:25.765226 ADC[5]: Raw value=211812 ID=1
9180 23:45:25.765741 SKU Code: 0x1
9181 23:45:25.772023 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1d21
9182 23:45:25.775399 coreboot table: 964 bytes.
9183 23:45:25.778737 IMD ROOT 0. 0xfffff000 0x00001000
9184 23:45:25.779294 IMD SMALL 1. 0xffffe000 0x00001000
9185 23:45:25.782208 RO MCACHE 2. 0xffffc000 0x00001104
9186 23:45:25.785621 CONSOLE 3. 0xfff7c000 0x00080000
9187 23:45:25.788766 FMAP 4. 0xfff7b000 0x00000452
9188 23:45:25.792060 TIME STAMP 5. 0xfff7a000 0x00000910
9189 23:45:25.795296 VBOOT WORK 6. 0xfff66000 0x00014000
9190 23:45:25.798727 RAMOOPS 7. 0xffe66000 0x00100000
9191 23:45:25.801880 COREBOOT 8. 0xffe64000 0x00002000
9192 23:45:25.805458 IMD small region:
9193 23:45:25.808221 IMD ROOT 0. 0xffffec00 0x00000400
9194 23:45:25.811805 VPD 1. 0xffffeb80 0x0000006c
9195 23:45:25.815062 MMC STATUS 2. 0xffffeb60 0x00000004
9196 23:45:25.821459 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9197 23:45:25.821919 Probing TPM: done!
9198 23:45:25.828730 Connected to device vid:did:rid of 1ae0:0028:00
9199 23:45:25.835436 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9200 23:45:25.838532 Initialized TPM device CR50 revision 0
9201 23:45:25.841908 Checking cr50 for pending updates
9202 23:45:25.847569 Reading cr50 TPM mode
9203 23:45:25.856201 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9204 23:45:25.862218 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9205 23:45:25.902617 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9206 23:45:25.905871 Checking segment from ROM address 0x40100000
9207 23:45:25.909207 Checking segment from ROM address 0x4010001c
9208 23:45:25.915856 Loading segment from ROM address 0x40100000
9209 23:45:25.916320 code (compression=0)
9210 23:45:25.925877 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9211 23:45:25.932385 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9212 23:45:25.932868 it's not compressed!
9213 23:45:25.938895 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9214 23:45:25.945633 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9215 23:45:25.962934 Loading segment from ROM address 0x4010001c
9216 23:45:25.963476 Entry Point 0x80000000
9217 23:45:25.966289 Loaded segments
9218 23:45:25.969838 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9219 23:45:25.976176 Jumping to boot code at 0x80000000(0xffe64000)
9220 23:45:25.983142 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9221 23:45:25.989716 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9222 23:45:25.997435 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9223 23:45:26.001050 Checking segment from ROM address 0x40100000
9224 23:45:26.004264 Checking segment from ROM address 0x4010001c
9225 23:45:26.010986 Loading segment from ROM address 0x40100000
9226 23:45:26.011532 code (compression=1)
9227 23:45:26.017817 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9228 23:45:26.027447 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9229 23:45:26.028010 using LZMA
9230 23:45:26.036380 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9231 23:45:26.042409 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9232 23:45:26.045791 Loading segment from ROM address 0x4010001c
9233 23:45:26.046253 Entry Point 0x54601000
9234 23:45:26.049344 Loaded segments
9235 23:45:26.052412 NOTICE: MT8192 bl31_setup
9236 23:45:26.059344 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9237 23:45:26.062732 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9238 23:45:26.065986 WARNING: region 0:
9239 23:45:26.069471 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9240 23:45:26.070027 WARNING: region 1:
9241 23:45:26.075919 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9242 23:45:26.079570 WARNING: region 2:
9243 23:45:26.082709 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9244 23:45:26.086059 WARNING: region 3:
9245 23:45:26.089550 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9246 23:45:26.092677 WARNING: region 4:
9247 23:45:26.099237 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9248 23:45:26.099729 WARNING: region 5:
9249 23:45:26.102760 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9250 23:45:26.106027 WARNING: region 6:
9251 23:45:26.109484 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9252 23:45:26.112452 WARNING: region 7:
9253 23:45:26.115817 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9254 23:45:26.122678 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9255 23:45:26.125969 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9256 23:45:26.129163 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9257 23:45:26.135941 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9258 23:45:26.139126 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9259 23:45:26.143233 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9260 23:45:26.148888 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9261 23:45:26.152304 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9262 23:45:26.158759 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9263 23:45:26.162430 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9264 23:45:26.165403 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9265 23:45:26.172385 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9266 23:45:26.175769 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9267 23:45:26.182143 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9268 23:45:26.185169 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9269 23:45:26.188748 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9270 23:45:26.195221 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9271 23:45:26.198487 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9272 23:45:26.205359 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9273 23:45:26.208377 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9274 23:45:26.211608 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9275 23:45:26.218498 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9276 23:45:26.221800 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9277 23:45:26.224881 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9278 23:45:26.231953 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9279 23:45:26.235147 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9280 23:45:26.241894 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9281 23:45:26.245156 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9282 23:45:26.251301 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9283 23:45:26.254721 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9284 23:45:26.258311 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9285 23:45:26.264606 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9286 23:45:26.268189 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9287 23:45:26.271495 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9288 23:45:26.275145 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9289 23:45:26.281338 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9290 23:45:26.284686 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9291 23:45:26.288138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9292 23:45:26.291307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9293 23:45:26.298174 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9294 23:45:26.301429 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9295 23:45:26.304721 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9296 23:45:26.307979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9297 23:45:26.314341 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9298 23:45:26.317766 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9299 23:45:26.321563 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9300 23:45:26.327722 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9301 23:45:26.331003 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9302 23:45:26.334481 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9303 23:45:26.341048 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9304 23:45:26.344229 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9305 23:45:26.351338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9306 23:45:26.354397 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9307 23:45:26.357695 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9308 23:45:26.364208 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9309 23:45:26.368077 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9310 23:45:26.374583 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9311 23:45:26.377773 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9312 23:45:26.384262 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9313 23:45:26.387937 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9314 23:45:26.390930 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9315 23:45:26.397249 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9316 23:45:26.401045 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9317 23:45:26.407549 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9318 23:45:26.410660 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9319 23:45:26.417653 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9320 23:45:26.420821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9321 23:45:26.427701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9322 23:45:26.431049 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9323 23:45:26.434067 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9324 23:45:26.440937 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9325 23:45:26.444216 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9326 23:45:26.450763 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9327 23:45:26.454077 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9328 23:45:26.460674 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9329 23:45:26.463871 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9330 23:45:26.467167 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9331 23:45:26.474042 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9332 23:45:26.477198 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9333 23:45:26.484090 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9334 23:45:26.487567 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9335 23:45:26.494261 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9336 23:45:26.497462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9337 23:45:26.501069 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9338 23:45:26.507573 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9339 23:45:26.510486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9340 23:45:26.517439 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9341 23:45:26.520553 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9342 23:45:26.527217 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9343 23:45:26.530840 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9344 23:45:26.534246 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9345 23:45:26.540913 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9346 23:45:26.544500 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9347 23:45:26.550598 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9348 23:45:26.553841 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9349 23:45:26.560422 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9350 23:45:26.563823 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9351 23:45:26.566994 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9352 23:45:26.570581 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9353 23:45:26.577080 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9354 23:45:26.580433 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9355 23:45:26.584183 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9356 23:45:26.590608 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9357 23:45:26.593742 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9358 23:45:26.600314 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9359 23:45:26.603415 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9360 23:45:26.606751 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9361 23:45:26.613197 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9362 23:45:26.616800 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9363 23:45:26.623340 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9364 23:45:26.626645 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9365 23:45:26.630447 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9366 23:45:26.636885 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9367 23:45:26.640448 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9368 23:45:26.647145 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9369 23:45:26.650313 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9370 23:45:26.653348 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9371 23:45:26.656775 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9372 23:45:26.663514 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9373 23:45:26.666771 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9374 23:45:26.670281 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9375 23:45:26.677186 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9376 23:45:26.679947 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9377 23:45:26.683808 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9378 23:45:26.686881 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9379 23:45:26.693492 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9380 23:45:26.696895 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9381 23:45:26.703462 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9382 23:45:26.707127 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9383 23:45:26.710124 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9384 23:45:26.716526 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9385 23:45:26.719922 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9386 23:45:26.726601 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9387 23:45:26.729635 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9388 23:45:26.733471 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9389 23:45:26.740160 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9390 23:45:26.743411 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9391 23:45:26.749877 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9392 23:45:26.753039 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9393 23:45:26.756458 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9394 23:45:26.762873 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9395 23:45:26.766252 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9396 23:45:26.773160 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9397 23:45:26.776936 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9398 23:45:26.779858 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9399 23:45:26.786193 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9400 23:45:26.789786 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9401 23:45:26.793656 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9402 23:45:26.799559 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9403 23:45:26.803018 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9404 23:45:26.809733 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9405 23:45:26.813005 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9406 23:45:26.816146 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9407 23:45:26.822993 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9408 23:45:26.826480 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9409 23:45:26.832925 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9410 23:45:26.836117 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9411 23:45:26.839601 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9412 23:45:26.846235 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9413 23:45:26.849921 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9414 23:45:26.856072 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9415 23:45:26.859197 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9416 23:45:26.862575 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9417 23:45:26.869442 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9418 23:45:26.872604 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9419 23:45:26.879258 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9420 23:45:26.882787 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9421 23:45:26.885906 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9422 23:45:26.892537 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9423 23:45:26.895729 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9424 23:45:26.902341 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9425 23:45:26.905597 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9426 23:45:26.908858 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9427 23:45:26.915193 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9428 23:45:26.919005 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9429 23:45:26.925471 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9430 23:45:26.928420 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9431 23:45:26.932125 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9432 23:45:26.938338 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9433 23:45:26.941687 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9434 23:45:26.948550 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9435 23:45:26.951642 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9436 23:45:26.955108 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9437 23:45:26.961704 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9438 23:45:26.964799 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9439 23:45:26.971703 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9440 23:45:26.974836 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9441 23:45:26.978215 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9442 23:45:26.984899 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9443 23:45:26.988247 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9444 23:45:26.994787 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9445 23:45:26.998050 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9446 23:45:27.001461 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9447 23:45:27.008062 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9448 23:45:27.010931 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9449 23:45:27.018069 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9450 23:45:27.021251 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9451 23:45:27.027739 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9452 23:45:27.031135 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9453 23:45:27.034155 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9454 23:45:27.041351 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9455 23:45:27.044493 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9456 23:45:27.050891 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9457 23:45:27.054651 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9458 23:45:27.060911 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9459 23:45:27.064261 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9460 23:45:27.067451 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9461 23:45:27.074279 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9462 23:45:27.077367 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9463 23:45:27.084008 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9464 23:45:27.087124 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9465 23:45:27.090680 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9466 23:45:27.097377 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9467 23:45:27.100877 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9468 23:45:27.107303 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9469 23:45:27.110626 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9470 23:45:27.116834 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9471 23:45:27.120566 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9472 23:45:27.123799 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9473 23:45:27.130145 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9474 23:45:27.133781 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9475 23:45:27.139998 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9476 23:45:27.143724 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9477 23:45:27.150215 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9478 23:45:27.153155 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9479 23:45:27.157131 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9480 23:45:27.163599 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9481 23:45:27.166669 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9482 23:45:27.173421 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9483 23:45:27.176530 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9484 23:45:27.179877 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9485 23:45:27.183312 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9486 23:45:27.186691 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9487 23:45:27.193539 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9488 23:45:27.196765 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9489 23:45:27.203238 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9490 23:45:27.206603 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9491 23:45:27.209752 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9492 23:45:27.216214 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9493 23:45:27.219707 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9494 23:45:27.223215 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9495 23:45:27.229518 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9496 23:45:27.233160 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9497 23:45:27.236375 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9498 23:45:27.243219 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9499 23:45:27.246006 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9500 23:45:27.252814 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9501 23:45:27.255872 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9502 23:45:27.259346 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9503 23:45:27.265857 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9504 23:45:27.268947 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9505 23:45:27.272415 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9506 23:45:27.279147 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9507 23:45:27.282322 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9508 23:45:27.289202 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9509 23:45:27.292637 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9510 23:45:27.295492 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9511 23:45:27.302115 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9512 23:45:27.305750 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9513 23:45:27.308954 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9514 23:45:27.315326 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9515 23:45:27.318858 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9516 23:45:27.325199 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9517 23:45:27.328523 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9518 23:45:27.332087 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9519 23:45:27.338644 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9520 23:45:27.341644 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9521 23:45:27.345045 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9522 23:45:27.351971 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9523 23:45:27.355387 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9524 23:45:27.358141 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9525 23:45:27.362056 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9526 23:45:27.368043 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9527 23:45:27.371783 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9528 23:45:27.374832 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9529 23:45:27.378421 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9530 23:45:27.384921 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9531 23:45:27.387996 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9532 23:45:27.391103 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9533 23:45:27.394427 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9534 23:45:27.400972 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9535 23:45:27.404667 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9536 23:45:27.407579 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9537 23:45:27.414231 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9538 23:45:27.417648 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9539 23:45:27.424114 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9540 23:45:27.427619 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9541 23:45:27.434001 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9542 23:45:27.437461 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9543 23:45:27.440802 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9544 23:45:27.447199 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9545 23:45:27.450552 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9546 23:45:27.457736 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9547 23:45:27.460840 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9548 23:45:27.467322 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9549 23:45:27.470769 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9550 23:45:27.473799 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9551 23:45:27.480879 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9552 23:45:27.483879 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9553 23:45:27.490855 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9554 23:45:27.493815 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9555 23:45:27.497051 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9556 23:45:27.503689 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9557 23:45:27.506731 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9558 23:45:27.513405 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9559 23:45:27.516558 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9560 23:45:27.520106 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9561 23:45:27.526929 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9562 23:45:27.529830 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9563 23:45:27.536555 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9564 23:45:27.540004 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9565 23:45:27.546588 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9566 23:45:27.549886 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9567 23:45:27.552843 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9568 23:45:27.560193 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9569 23:45:27.562843 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9570 23:45:27.569816 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9571 23:45:27.572658 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9572 23:45:27.579971 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9573 23:45:27.582879 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9574 23:45:27.586316 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9575 23:45:27.592848 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9576 23:45:27.596330 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9577 23:45:27.603013 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9578 23:45:27.605763 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9579 23:45:27.609323 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9580 23:45:27.615819 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9581 23:45:27.618974 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9582 23:45:27.626100 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9583 23:45:27.628950 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9584 23:45:27.632221 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9585 23:45:27.639144 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9586 23:45:27.642441 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9587 23:45:27.648801 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9588 23:45:27.652529 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9589 23:45:27.658609 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9590 23:45:27.662350 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9591 23:45:27.665397 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9592 23:45:27.672207 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9593 23:45:27.675139 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9594 23:45:27.682086 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9595 23:45:27.685131 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9596 23:45:27.688742 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9597 23:45:27.695285 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9598 23:45:27.698279 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9599 23:45:27.705101 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9600 23:45:27.708339 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9601 23:45:27.714728 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9602 23:45:27.717988 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9603 23:45:27.721444 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9604 23:45:27.727918 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9605 23:45:27.731266 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9606 23:45:27.738050 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9607 23:45:27.741168 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9608 23:45:27.745029 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9609 23:45:27.751129 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9610 23:45:27.754636 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9611 23:45:27.761374 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9612 23:45:27.764615 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9613 23:45:27.771228 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9614 23:45:27.774537 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9615 23:45:27.778012 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9616 23:45:27.784601 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9617 23:45:27.787980 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9618 23:45:27.794317 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9619 23:45:27.797774 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9620 23:45:27.804618 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9621 23:45:27.807431 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9622 23:45:27.814230 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9623 23:45:27.817536 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9624 23:45:27.821013 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9625 23:45:27.827487 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9626 23:45:27.830740 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9627 23:45:27.837475 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9628 23:45:27.840674 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9629 23:45:27.847293 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9630 23:45:27.850881 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9631 23:45:27.857520 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9632 23:45:27.860646 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9633 23:45:27.863757 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9634 23:45:27.870323 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9635 23:45:27.873832 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9636 23:45:27.880319 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9637 23:45:27.884115 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9638 23:45:27.890227 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9639 23:45:27.893676 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9640 23:45:27.896732 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9641 23:45:27.903600 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9642 23:45:27.906700 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9643 23:45:27.913375 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9644 23:45:27.916438 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9645 23:45:27.923244 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9646 23:45:27.926687 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9647 23:45:27.932777 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9648 23:45:27.936522 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9649 23:45:27.939610 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9650 23:45:27.946353 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9651 23:45:27.949758 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9652 23:45:27.956601 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9653 23:45:27.959642 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9654 23:45:27.966243 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9655 23:45:27.969555 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9656 23:45:27.973104 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9657 23:45:27.979340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9658 23:45:27.982484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9659 23:45:27.989192 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9660 23:45:27.992394 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9661 23:45:27.999298 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9662 23:45:28.002171 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9663 23:45:28.008681 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9664 23:45:28.012354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9665 23:45:28.018664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9666 23:45:28.022256 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9667 23:45:28.029065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9668 23:45:28.032013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9669 23:45:28.038318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9670 23:45:28.041659 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9671 23:45:28.049015 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9672 23:45:28.051716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9673 23:45:28.058287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9674 23:45:28.061759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9675 23:45:28.068108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9676 23:45:28.071436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9677 23:45:28.078025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9678 23:45:28.081576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9679 23:45:28.088102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9680 23:45:28.091081 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9681 23:45:28.097861 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9682 23:45:28.101373 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9683 23:45:28.108002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9684 23:45:28.111045 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9685 23:45:28.117469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9686 23:45:28.120935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9687 23:45:28.127796 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9688 23:45:28.130573 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9689 23:45:28.133981 INFO: [APUAPC] vio 0
9690 23:45:28.137157 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9691 23:45:28.144025 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9692 23:45:28.147108 INFO: [APUAPC] D0_APC_0: 0x400510
9693 23:45:28.150789 INFO: [APUAPC] D0_APC_1: 0x0
9694 23:45:28.153802 INFO: [APUAPC] D0_APC_2: 0x1540
9695 23:45:28.154254 INFO: [APUAPC] D0_APC_3: 0x0
9696 23:45:28.157149 INFO: [APUAPC] D1_APC_0: 0xffffffff
9697 23:45:28.160314 INFO: [APUAPC] D1_APC_1: 0xffffffff
9698 23:45:28.163830 INFO: [APUAPC] D1_APC_2: 0x3fffff
9699 23:45:28.167346 INFO: [APUAPC] D1_APC_3: 0x0
9700 23:45:28.170377 INFO: [APUAPC] D2_APC_0: 0xffffffff
9701 23:45:28.173673 INFO: [APUAPC] D2_APC_1: 0xffffffff
9702 23:45:28.177043 INFO: [APUAPC] D2_APC_2: 0x3fffff
9703 23:45:28.180224 INFO: [APUAPC] D2_APC_3: 0x0
9704 23:45:28.183629 INFO: [APUAPC] D3_APC_0: 0xffffffff
9705 23:45:28.187320 INFO: [APUAPC] D3_APC_1: 0xffffffff
9706 23:45:28.190170 INFO: [APUAPC] D3_APC_2: 0x3fffff
9707 23:45:28.193844 INFO: [APUAPC] D3_APC_3: 0x0
9708 23:45:28.196938 INFO: [APUAPC] D4_APC_0: 0xffffffff
9709 23:45:28.199885 INFO: [APUAPC] D4_APC_1: 0xffffffff
9710 23:45:28.203552 INFO: [APUAPC] D4_APC_2: 0x3fffff
9711 23:45:28.206739 INFO: [APUAPC] D4_APC_3: 0x0
9712 23:45:28.210526 INFO: [APUAPC] D5_APC_0: 0xffffffff
9713 23:45:28.213338 INFO: [APUAPC] D5_APC_1: 0xffffffff
9714 23:45:28.216777 INFO: [APUAPC] D5_APC_2: 0x3fffff
9715 23:45:28.219806 INFO: [APUAPC] D5_APC_3: 0x0
9716 23:45:28.223317 INFO: [APUAPC] D6_APC_0: 0xffffffff
9717 23:45:28.226716 INFO: [APUAPC] D6_APC_1: 0xffffffff
9718 23:45:28.229888 INFO: [APUAPC] D6_APC_2: 0x3fffff
9719 23:45:28.232825 INFO: [APUAPC] D6_APC_3: 0x0
9720 23:45:28.236202 INFO: [APUAPC] D7_APC_0: 0xffffffff
9721 23:45:28.240244 INFO: [APUAPC] D7_APC_1: 0xffffffff
9722 23:45:28.243007 INFO: [APUAPC] D7_APC_2: 0x3fffff
9723 23:45:28.246300 INFO: [APUAPC] D7_APC_3: 0x0
9724 23:45:28.249615 INFO: [APUAPC] D8_APC_0: 0xffffffff
9725 23:45:28.252624 INFO: [APUAPC] D8_APC_1: 0xffffffff
9726 23:45:28.255985 INFO: [APUAPC] D8_APC_2: 0x3fffff
9727 23:45:28.259366 INFO: [APUAPC] D8_APC_3: 0x0
9728 23:45:28.262903 INFO: [APUAPC] D9_APC_0: 0xffffffff
9729 23:45:28.265963 INFO: [APUAPC] D9_APC_1: 0xffffffff
9730 23:45:28.269462 INFO: [APUAPC] D9_APC_2: 0x3fffff
9731 23:45:28.272713 INFO: [APUAPC] D9_APC_3: 0x0
9732 23:45:28.275928 INFO: [APUAPC] D10_APC_0: 0xffffffff
9733 23:45:28.279257 INFO: [APUAPC] D10_APC_1: 0xffffffff
9734 23:45:28.282480 INFO: [APUAPC] D10_APC_2: 0x3fffff
9735 23:45:28.286072 INFO: [APUAPC] D10_APC_3: 0x0
9736 23:45:28.289203 INFO: [APUAPC] D11_APC_0: 0xffffffff
9737 23:45:28.292557 INFO: [APUAPC] D11_APC_1: 0xffffffff
9738 23:45:28.295911 INFO: [APUAPC] D11_APC_2: 0x3fffff
9739 23:45:28.299127 INFO: [APUAPC] D11_APC_3: 0x0
9740 23:45:28.302255 INFO: [APUAPC] D12_APC_0: 0xffffffff
9741 23:45:28.306383 INFO: [APUAPC] D12_APC_1: 0xffffffff
9742 23:45:28.309015 INFO: [APUAPC] D12_APC_2: 0x3fffff
9743 23:45:28.312027 INFO: [APUAPC] D12_APC_3: 0x0
9744 23:45:28.315385 INFO: [APUAPC] D13_APC_0: 0xffffffff
9745 23:45:28.318915 INFO: [APUAPC] D13_APC_1: 0xffffffff
9746 23:45:28.322046 INFO: [APUAPC] D13_APC_2: 0x3fffff
9747 23:45:28.325356 INFO: [APUAPC] D13_APC_3: 0x0
9748 23:45:28.328596 INFO: [APUAPC] D14_APC_0: 0xffffffff
9749 23:45:28.332137 INFO: [APUAPC] D14_APC_1: 0xffffffff
9750 23:45:28.335492 INFO: [APUAPC] D14_APC_2: 0x3fffff
9751 23:45:28.338825 INFO: [APUAPC] D14_APC_3: 0x0
9752 23:45:28.341831 INFO: [APUAPC] D15_APC_0: 0xffffffff
9753 23:45:28.345346 INFO: [APUAPC] D15_APC_1: 0xffffffff
9754 23:45:28.348606 INFO: [APUAPC] D15_APC_2: 0x3fffff
9755 23:45:28.351918 INFO: [APUAPC] D15_APC_3: 0x0
9756 23:45:28.355357 INFO: [APUAPC] APC_CON: 0x4
9757 23:45:28.358326 INFO: [NOCDAPC] D0_APC_0: 0x0
9758 23:45:28.361751 INFO: [NOCDAPC] D0_APC_1: 0x0
9759 23:45:28.365092 INFO: [NOCDAPC] D1_APC_0: 0x0
9760 23:45:28.368156 INFO: [NOCDAPC] D1_APC_1: 0xfff
9761 23:45:28.371735 INFO: [NOCDAPC] D2_APC_0: 0x0
9762 23:45:28.372287 INFO: [NOCDAPC] D2_APC_1: 0xfff
9763 23:45:28.374972 INFO: [NOCDAPC] D3_APC_0: 0x0
9764 23:45:28.378360 INFO: [NOCDAPC] D3_APC_1: 0xfff
9765 23:45:28.381520 INFO: [NOCDAPC] D4_APC_0: 0x0
9766 23:45:28.385160 INFO: [NOCDAPC] D4_APC_1: 0xfff
9767 23:45:28.388311 INFO: [NOCDAPC] D5_APC_0: 0x0
9768 23:45:28.391607 INFO: [NOCDAPC] D5_APC_1: 0xfff
9769 23:45:28.394909 INFO: [NOCDAPC] D6_APC_0: 0x0
9770 23:45:28.398127 INFO: [NOCDAPC] D6_APC_1: 0xfff
9771 23:45:28.401594 INFO: [NOCDAPC] D7_APC_0: 0x0
9772 23:45:28.404816 INFO: [NOCDAPC] D7_APC_1: 0xfff
9773 23:45:28.405413 INFO: [NOCDAPC] D8_APC_0: 0x0
9774 23:45:28.407761 INFO: [NOCDAPC] D8_APC_1: 0xfff
9775 23:45:28.411223 INFO: [NOCDAPC] D9_APC_0: 0x0
9776 23:45:28.414356 INFO: [NOCDAPC] D9_APC_1: 0xfff
9777 23:45:28.417671 INFO: [NOCDAPC] D10_APC_0: 0x0
9778 23:45:28.421140 INFO: [NOCDAPC] D10_APC_1: 0xfff
9779 23:45:28.424174 INFO: [NOCDAPC] D11_APC_0: 0x0
9780 23:45:28.427766 INFO: [NOCDAPC] D11_APC_1: 0xfff
9781 23:45:28.430779 INFO: [NOCDAPC] D12_APC_0: 0x0
9782 23:45:28.434324 INFO: [NOCDAPC] D12_APC_1: 0xfff
9783 23:45:28.437624 INFO: [NOCDAPC] D13_APC_0: 0x0
9784 23:45:28.440909 INFO: [NOCDAPC] D13_APC_1: 0xfff
9785 23:45:28.444006 INFO: [NOCDAPC] D14_APC_0: 0x0
9786 23:45:28.447448 INFO: [NOCDAPC] D14_APC_1: 0xfff
9787 23:45:28.450760 INFO: [NOCDAPC] D15_APC_0: 0x0
9788 23:45:28.453908 INFO: [NOCDAPC] D15_APC_1: 0xfff
9789 23:45:28.454522 INFO: [NOCDAPC] APC_CON: 0x4
9790 23:45:28.456924 INFO: [APUAPC] set_apusys_apc done
9791 23:45:28.460333 INFO: [DEVAPC] devapc_init done
9792 23:45:28.466963 INFO: GICv3 without legacy support detected.
9793 23:45:28.470369 INFO: ARM GICv3 driver initialized in EL3
9794 23:45:28.473744 INFO: Maximum SPI INTID supported: 639
9795 23:45:28.477324 INFO: BL31: Initializing runtime services
9796 23:45:28.483648 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9797 23:45:28.486914 INFO: SPM: enable CPC mode
9798 23:45:28.490416 INFO: mcdi ready for mcusys-off-idle and system suspend
9799 23:45:28.496783 INFO: BL31: Preparing for EL3 exit to normal world
9800 23:45:28.499883 INFO: Entry point address = 0x80000000
9801 23:45:28.500345 INFO: SPSR = 0x8
9802 23:45:28.507244
9803 23:45:28.507655
9804 23:45:28.507978
9805 23:45:28.510567 Starting depthcharge on Spherion...
9806 23:45:28.511130
9807 23:45:28.511740 Wipe memory regions:
9808 23:45:28.512102
9809 23:45:28.514751 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9810 23:45:28.515315 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9811 23:45:28.515782 Setting prompt string to ['asurada:']
9812 23:45:28.516177 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9813 23:45:28.516814 [0x00000040000000, 0x00000054600000)
9814 23:45:28.636238
9815 23:45:28.636796 [0x00000054660000, 0x00000080000000)
9816 23:45:28.896812
9817 23:45:28.897425 [0x000000821a7280, 0x000000ffe64000)
9818 23:45:29.641544
9819 23:45:29.642125 [0x00000100000000, 0x00000140000000)
9820 23:45:30.022395
9821 23:45:30.025731 Initializing XHCI USB controller at 0x11200000.
9822 23:45:31.064393
9823 23:45:31.067672 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9824 23:45:31.068221
9825 23:45:31.068578
9826 23:45:31.069428 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9828 23:45:31.170789 asurada: tftpboot 192.168.201.1 14172964/tftp-deploy-m7ldps3i/kernel/image.itb 14172964/tftp-deploy-m7ldps3i/kernel/cmdline
9829 23:45:31.171440 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9830 23:45:31.172079 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9831 23:45:31.176465 tftpboot 192.168.201.1 14172964/tftp-deploy-m7ldps3i/kernel/image.itp-deploy-m7ldps3i/kernel/cmdline
9832 23:45:31.177037
9833 23:45:31.177429 Waiting for link
9834 23:45:31.337219
9835 23:45:31.337863 R8152: Initializing
9836 23:45:31.338227
9837 23:45:31.340264 Version 9 (ocp_data = 6010)
9838 23:45:31.340816
9839 23:45:31.343139 R8152: Done initializing
9840 23:45:31.343595
9841 23:45:31.343952 Adding net device
9842 23:45:33.351805
9843 23:45:33.352368 done.
9844 23:45:33.352731
9845 23:45:33.353064 MAC: 00:e0:4c:68:03:bd
9846 23:45:33.353433
9847 23:45:33.355124 Sending DHCP discover... done.
9848 23:45:33.355570
9849 23:45:33.358338 Waiting for reply... done.
9850 23:45:33.358789
9851 23:45:33.361637 Sending DHCP request... done.
9852 23:45:33.362085
9853 23:45:33.364886 Waiting for reply... done.
9854 23:45:33.365391
9855 23:45:33.365757 My ip is 192.168.201.16
9856 23:45:33.366086
9857 23:45:33.368008 The DHCP server ip is 192.168.201.1
9858 23:45:33.368459
9859 23:45:33.374604 TFTP server IP predefined by user: 192.168.201.1
9860 23:45:33.375142
9861 23:45:33.381478 Bootfile predefined by user: 14172964/tftp-deploy-m7ldps3i/kernel/image.itb
9862 23:45:33.381953
9863 23:45:33.382325 Sending tftp read request... done.
9864 23:45:33.384472
9865 23:45:33.390732 Waiting for the transfer...
9866 23:45:33.391193
9867 23:45:33.745218 00000000 ################################################################
9868 23:45:33.745428
9869 23:45:34.032991 00080000 ################################################################
9870 23:45:34.033132
9871 23:45:34.318353 00100000 ################################################################
9872 23:45:34.318491
9873 23:45:34.603611 00180000 ################################################################
9874 23:45:34.603778
9875 23:45:34.887759 00200000 ################################################################
9876 23:45:34.887918
9877 23:45:35.173042 00280000 ################################################################
9878 23:45:35.173201
9879 23:45:35.474001 00300000 ################################################################
9880 23:45:35.474141
9881 23:45:35.767003 00380000 ################################################################
9882 23:45:35.767171
9883 23:45:36.043669 00400000 ################################################################
9884 23:45:36.043808
9885 23:45:36.337091 00480000 ################################################################
9886 23:45:36.337250
9887 23:45:36.613793 00500000 ################################################################
9888 23:45:36.613953
9889 23:45:36.891873 00580000 ################################################################
9890 23:45:36.892039
9891 23:45:37.169090 00600000 ################################################################
9892 23:45:37.169284
9893 23:45:37.445039 00680000 ################################################################
9894 23:45:37.445202
9895 23:45:37.742062 00700000 ################################################################
9896 23:45:37.742199
9897 23:45:38.019688 00780000 ################################################################
9898 23:45:38.019851
9899 23:45:38.283634 00800000 ################################################################
9900 23:45:38.283796
9901 23:45:38.579565 00880000 ################################################################
9902 23:45:38.579730
9903 23:45:38.876045 00900000 ################################################################
9904 23:45:38.876215
9905 23:45:39.134945 00980000 ################################################################
9906 23:45:39.135078
9907 23:45:39.414987 00a00000 ################################################################
9908 23:45:39.415151
9909 23:45:39.670685 00a80000 ################################################################
9910 23:45:39.670827
9911 23:45:39.965984 00b00000 ################################################################
9912 23:45:39.966121
9913 23:45:40.263225 00b80000 ################################################################
9914 23:45:40.263360
9915 23:45:40.550534 00c00000 ################################################################
9916 23:45:40.550702
9917 23:45:40.841285 00c80000 ################################################################
9918 23:45:40.841487
9919 23:45:41.138305 00d00000 ################################################################
9920 23:45:41.138442
9921 23:45:41.434646 00d80000 ################################################################
9922 23:45:41.434806
9923 23:45:41.734059 00e00000 ################################################################
9924 23:45:41.734199
9925 23:45:42.018269 00e80000 ################################################################
9926 23:45:42.018407
9927 23:45:42.317569 00f00000 ################################################################
9928 23:45:42.317704
9929 23:45:42.618088 00f80000 ################################################################
9930 23:45:42.618226
9931 23:45:42.907077 01000000 ################################################################
9932 23:45:42.907242
9933 23:45:43.182560 01080000 ################################################################
9934 23:45:43.182730
9935 23:45:43.470974 01100000 ################################################################
9936 23:45:43.471129
9937 23:45:43.758372 01180000 ################################################################
9938 23:45:43.758505
9939 23:45:44.046147 01200000 ################################################################
9940 23:45:44.046315
9941 23:45:44.305475 01280000 ################################################################
9942 23:45:44.305621
9943 23:45:44.602950 01300000 ################################################################
9944 23:45:44.603115
9945 23:45:44.905234 01380000 ################################################################
9946 23:45:44.905399
9947 23:45:45.206430 01400000 ################################################################
9948 23:45:45.206561
9949 23:45:45.486618 01480000 ################################################################
9950 23:45:45.486756
9951 23:45:45.736840 01500000 ################################################################
9952 23:45:45.736975
9953 23:45:45.986899 01580000 ################################################################
9954 23:45:45.987056
9955 23:45:46.237285 01600000 ################################################################
9956 23:45:46.237450
9957 23:45:46.487323 01680000 ################################################################
9958 23:45:46.487485
9959 23:45:46.748269 01700000 ################################################################
9960 23:45:46.748427
9961 23:45:47.006366 01780000 ################################################################
9962 23:45:47.006505
9963 23:45:47.256889 01800000 ################################################################
9964 23:45:47.257021
9965 23:45:47.542356 01880000 ################################################################
9966 23:45:47.542518
9967 23:45:47.835178 01900000 ################################################################
9968 23:45:47.835351
9969 23:45:48.155291 01980000 ################################################################
9970 23:45:48.155431
9971 23:45:48.484978 01a00000 ################################################################
9972 23:45:48.485579
9973 23:45:48.871343 01a80000 ################################################################
9974 23:45:48.871840
9975 23:45:49.221904 01b00000 ################################################################
9976 23:45:49.222052
9977 23:45:49.518890 01b80000 ################################################################
9978 23:45:49.519051
9979 23:45:49.805829 01c00000 ################################################################
9980 23:45:49.805965
9981 23:45:50.085785 01c80000 ################################################################
9982 23:45:50.085932
9983 23:45:50.343068 01d00000 ################################################################
9984 23:45:50.343217
9985 23:45:50.593311 01d80000 ################################################################
9986 23:45:50.593459
9987 23:45:50.778305 01e00000 ################################################ done.
9988 23:45:50.778835
9989 23:45:50.781338 The bootfile was 31842530 bytes long.
9990 23:45:50.781760
9991 23:45:50.784666 Sending tftp read request... done.
9992 23:45:50.785078
9993 23:45:50.787998 Waiting for the transfer...
9994 23:45:50.788411
9995 23:45:50.788734 00000000 # done.
9996 23:45:50.789043
9997 23:45:50.794833 Command line loaded dynamically from TFTP file: 14172964/tftp-deploy-m7ldps3i/kernel/cmdline
9998 23:45:50.795384
9999 23:45:50.817930 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172964/extract-nfsrootfs-yfsyau3h,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10000 23:45:50.818523
10001 23:45:50.821011 Loading FIT.
10002 23:45:50.821501
10003 23:45:50.824142 Image ramdisk-1 has 18731806 bytes.
10004 23:45:50.824612
10005 23:45:50.824968 Image fdt-1 has 47258 bytes.
10006 23:45:50.825337
10007 23:45:50.827452 Image kernel-1 has 13061430 bytes.
10008 23:45:50.827964
10009 23:45:50.837369 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10010 23:45:50.837918
10011 23:45:50.854218 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10012 23:45:50.854814
10013 23:45:50.860586 Choosing best match conf-1 for compat google,spherion-rev3.
10014 23:45:50.864406
10015 23:45:50.869453 Connected to device vid:did:rid of 1ae0:0028:00
10016 23:45:50.876250
10017 23:45:50.879390 tpm_get_response: command 0x17b, return code 0x0
10018 23:45:50.879952
10019 23:45:50.882601 ec_init: CrosEC protocol v3 supported (256, 248)
10020 23:45:50.886731
10021 23:45:50.890097 tpm_cleanup: add release locality here.
10022 23:45:50.890554
10023 23:45:50.890917 Shutting down all USB controllers.
10024 23:45:50.893504
10025 23:45:50.893959 Removing current net device
10026 23:45:50.894318
10027 23:45:50.900135 Exiting depthcharge with code 4 at timestamp: 50634347
10028 23:45:50.900624
10029 23:45:50.904079 LZMA decompressing kernel-1 to 0x821a6718
10030 23:45:50.904638
10031 23:45:50.906765 LZMA decompressing kernel-1 to 0x40000000
10032 23:45:52.515499
10033 23:45:52.516261 jumping to kernel
10034 23:45:52.518055 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10035 23:45:52.518573 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10036 23:45:52.518983 Setting prompt string to ['Linux version [0-9]']
10037 23:45:52.519587 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10038 23:45:52.520205 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10039 23:45:52.567093
10040 23:45:52.570280 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10041 23:45:52.574408 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10042 23:45:52.574937 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10043 23:45:52.575330 Setting prompt string to []
10044 23:45:52.575774 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10045 23:45:52.576163 Using line separator: #'\n'#
10046 23:45:52.576495 No login prompt set.
10047 23:45:52.576828 Parsing kernel messages
10048 23:45:52.577133 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10049 23:45:52.577742 [login-action] Waiting for messages, (timeout 00:04:02)
10050 23:45:52.578106 Waiting using forced prompt support (timeout 00:02:01)
10051 23:45:52.593463 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j217067-arm64-gcc-10-defconfig-arm64-chromebook-s48tj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024
10052 23:45:52.596648 [ 0.000000] random: crng init done
10053 23:45:52.603368 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10054 23:45:52.606830 [ 0.000000] efi: UEFI not found.
10055 23:45:52.613466 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10056 23:45:52.622952 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10057 23:45:52.629538 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10058 23:45:52.639328 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10059 23:45:52.646006 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10060 23:45:52.652558 [ 0.000000] printk: bootconsole [mtk8250] enabled
10061 23:45:52.659087 [ 0.000000] NUMA: No NUMA configuration found
10062 23:45:52.665867 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10063 23:45:52.672418 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10064 23:45:52.672973 [ 0.000000] Zone ranges:
10065 23:45:52.678678 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10066 23:45:52.681912 [ 0.000000] DMA32 empty
10067 23:45:52.689116 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10068 23:45:52.692459 [ 0.000000] Movable zone start for each node
10069 23:45:52.695596 [ 0.000000] Early memory node ranges
10070 23:45:52.702028 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10071 23:45:52.708706 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10072 23:45:52.715286 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10073 23:45:52.721810 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10074 23:45:52.728404 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10075 23:45:52.735130 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10076 23:45:52.765744 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10077 23:45:52.772519 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10078 23:45:52.779227 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10079 23:45:52.782551 [ 0.000000] psci: probing for conduit method from DT.
10080 23:45:52.789112 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10081 23:45:52.792397 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10082 23:45:52.798931 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10083 23:45:52.802111 [ 0.000000] psci: SMC Calling Convention v1.2
10084 23:45:52.809083 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10085 23:45:52.812228 [ 0.000000] Detected VIPT I-cache on CPU0
10086 23:45:52.818773 [ 0.000000] CPU features: detected: GIC system register CPU interface
10087 23:45:52.825468 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10088 23:45:52.832165 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10089 23:45:52.838447 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10090 23:45:52.848212 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10091 23:45:52.854839 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10092 23:45:52.858108 [ 0.000000] alternatives: applying boot alternatives
10093 23:45:52.865058 [ 0.000000] Fallback order for Node 0: 0
10094 23:45:52.871483 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10095 23:45:52.874820 [ 0.000000] Policy zone: Normal
10096 23:45:52.897871 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172964/extract-nfsrootfs-yfsyau3h,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10097 23:45:52.907610 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10098 23:45:52.917881 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10099 23:45:52.924160 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10100 23:45:52.930861 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10101 23:45:52.937237 <6>[ 0.000000] software IO TLB: area num 8.
10102 23:45:52.992560 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10103 23:45:53.072968 <6>[ 0.000000] Memory: 3831484K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 326980K reserved, 32768K cma-reserved)
10104 23:45:53.079342 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10105 23:45:53.086192 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10106 23:45:53.089741 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10107 23:45:53.095933 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10108 23:45:53.102423 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10109 23:45:53.105485 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10110 23:45:53.115904 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10111 23:45:53.122572 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10112 23:45:53.128672 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10113 23:45:53.135767 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10114 23:45:53.138757 <6>[ 0.000000] GICv3: 608 SPIs implemented
10115 23:45:53.142009 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10116 23:45:53.148699 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10117 23:45:53.152154 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10118 23:45:53.158596 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10119 23:45:53.171564 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10120 23:45:53.185347 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10121 23:45:53.191817 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10122 23:45:53.199478 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10123 23:45:53.212739 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10124 23:45:53.219183 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10125 23:45:53.225955 <6>[ 0.009182] Console: colour dummy device 80x25
10126 23:45:53.235958 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10127 23:45:53.242770 <6>[ 0.024414] pid_max: default: 32768 minimum: 301
10128 23:45:53.245428 <6>[ 0.029315] LSM: Security Framework initializing
10129 23:45:53.252660 <6>[ 0.034229] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10130 23:45:53.262107 <6>[ 0.041837] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10131 23:45:53.268947 <6>[ 0.051070] cblist_init_generic: Setting adjustable number of callback queues.
10132 23:45:53.275600 <6>[ 0.058513] cblist_init_generic: Setting shift to 3 and lim to 1.
10133 23:45:53.285333 <6>[ 0.064852] cblist_init_generic: Setting adjustable number of callback queues.
10134 23:45:53.291831 <6>[ 0.072325] cblist_init_generic: Setting shift to 3 and lim to 1.
10135 23:45:53.295279 <6>[ 0.078766] rcu: Hierarchical SRCU implementation.
10136 23:45:53.301792 <6>[ 0.083781] rcu: Max phase no-delay instances is 1000.
10137 23:45:53.308340 <6>[ 0.090852] EFI services will not be available.
10138 23:45:53.311822 <6>[ 0.095810] smp: Bringing up secondary CPUs ...
10139 23:45:53.319974 <6>[ 0.100858] Detected VIPT I-cache on CPU1
10140 23:45:53.326350 <6>[ 0.100927] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10141 23:45:53.333362 <6>[ 0.100960] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10142 23:45:53.336689 <6>[ 0.101290] Detected VIPT I-cache on CPU2
10143 23:45:53.346575 <6>[ 0.101339] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10144 23:45:53.353054 <6>[ 0.101355] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10145 23:45:53.355998 <6>[ 0.101608] Detected VIPT I-cache on CPU3
10146 23:45:53.362753 <6>[ 0.101655] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10147 23:45:53.369638 <6>[ 0.101668] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10148 23:45:53.375997 <6>[ 0.101971] CPU features: detected: Spectre-v4
10149 23:45:53.379304 <6>[ 0.101977] CPU features: detected: Spectre-BHB
10150 23:45:53.382390 <6>[ 0.101982] Detected PIPT I-cache on CPU4
10151 23:45:53.389424 <6>[ 0.102041] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10152 23:45:53.398977 <6>[ 0.102057] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10153 23:45:53.402242 <6>[ 0.102348] Detected PIPT I-cache on CPU5
10154 23:45:53.408715 <6>[ 0.102412] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10155 23:45:53.415478 <6>[ 0.102428] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10156 23:45:53.418910 <6>[ 0.102710] Detected PIPT I-cache on CPU6
10157 23:45:53.428802 <6>[ 0.102775] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10158 23:45:53.435347 <6>[ 0.102791] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10159 23:45:53.438189 <6>[ 0.103086] Detected PIPT I-cache on CPU7
10160 23:45:53.445195 <6>[ 0.103153] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10161 23:45:53.451868 <6>[ 0.103169] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10162 23:45:53.455034 <6>[ 0.103216] smp: Brought up 1 node, 8 CPUs
10163 23:45:53.461243 <6>[ 0.244554] SMP: Total of 8 processors activated.
10164 23:45:53.468177 <6>[ 0.249475] CPU features: detected: 32-bit EL0 Support
10165 23:45:53.474876 <6>[ 0.254838] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10166 23:45:53.481369 <6>[ 0.263638] CPU features: detected: Common not Private translations
10167 23:45:53.488080 <6>[ 0.270114] CPU features: detected: CRC32 instructions
10168 23:45:53.494606 <6>[ 0.275465] CPU features: detected: RCpc load-acquire (LDAPR)
10169 23:45:53.498044 <6>[ 0.281425] CPU features: detected: LSE atomic instructions
10170 23:45:53.504362 <6>[ 0.287207] CPU features: detected: Privileged Access Never
10171 23:45:53.511295 <6>[ 0.293022] CPU features: detected: RAS Extension Support
10172 23:45:53.517786 <6>[ 0.298666] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10173 23:45:53.520951 <6>[ 0.305883] CPU: All CPU(s) started at EL2
10174 23:45:53.527655 <6>[ 0.310227] alternatives: applying system-wide alternatives
10175 23:45:53.536941 <6>[ 0.320252] devtmpfs: initialized
10176 23:45:53.548697 <6>[ 0.328469] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10177 23:45:53.558535 <6>[ 0.338427] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10178 23:45:53.564896 <6>[ 0.346459] pinctrl core: initialized pinctrl subsystem
10179 23:45:53.568247 <6>[ 0.353265] DMI not present or invalid.
10180 23:45:53.574933 <6>[ 0.357668] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10181 23:45:53.584495 <6>[ 0.364521] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10182 23:45:53.591604 <6>[ 0.371967] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10183 23:45:53.601197 <6>[ 0.380061] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10184 23:45:53.604367 <6>[ 0.388215] audit: initializing netlink subsys (disabled)
10185 23:45:53.614453 <5>[ 0.393910] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10186 23:45:53.621224 <6>[ 0.394658] thermal_sys: Registered thermal governor 'step_wise'
10187 23:45:53.627646 <6>[ 0.401877] thermal_sys: Registered thermal governor 'power_allocator'
10188 23:45:53.630586 <6>[ 0.408134] cpuidle: using governor menu
10189 23:45:53.637164 <6>[ 0.419093] NET: Registered PF_QIPCRTR protocol family
10190 23:45:53.644240 <6>[ 0.424580] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10191 23:45:53.647440 <6>[ 0.431681] ASID allocator initialised with 32768 entries
10192 23:45:53.654949 <6>[ 0.438283] Serial: AMBA PL011 UART driver
10193 23:45:53.663985 <4>[ 0.447473] Trying to register duplicate clock ID: 134
10194 23:45:53.724054 <6>[ 0.510885] KASLR enabled
10195 23:45:53.738350 <6>[ 0.518607] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10196 23:45:53.744972 <6>[ 0.525620] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10197 23:45:53.751637 <6>[ 0.532109] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10198 23:45:53.758250 <6>[ 0.539113] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10199 23:45:53.764742 <6>[ 0.545600] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10200 23:45:53.771328 <6>[ 0.552600] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10201 23:45:53.778078 <6>[ 0.559090] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10202 23:45:53.784392 <6>[ 0.566094] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10203 23:45:53.788087 <6>[ 0.573616] ACPI: Interpreter disabled.
10204 23:45:53.796850 <6>[ 0.580108] iommu: Default domain type: Translated
10205 23:45:53.803137 <6>[ 0.585221] iommu: DMA domain TLB invalidation policy: strict mode
10206 23:45:53.806569 <5>[ 0.591883] SCSI subsystem initialized
10207 23:45:53.813143 <6>[ 0.596044] usbcore: registered new interface driver usbfs
10208 23:45:53.819535 <6>[ 0.601777] usbcore: registered new interface driver hub
10209 23:45:53.823047 <6>[ 0.607331] usbcore: registered new device driver usb
10210 23:45:53.829845 <6>[ 0.613476] pps_core: LinuxPPS API ver. 1 registered
10211 23:45:53.840260 <6>[ 0.618667] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10212 23:45:53.843537 <6>[ 0.628013] PTP clock support registered
10213 23:45:53.846374 <6>[ 0.632256] EDAC MC: Ver: 3.0.0
10214 23:45:53.853985 <6>[ 0.637452] FPGA manager framework
10215 23:45:53.860837 <6>[ 0.641142] Advanced Linux Sound Architecture Driver Initialized.
10216 23:45:53.863685 <6>[ 0.647920] vgaarb: loaded
10217 23:45:53.870416 <6>[ 0.651077] clocksource: Switched to clocksource arch_sys_counter
10218 23:45:53.873923 <5>[ 0.657516] VFS: Disk quotas dquot_6.6.0
10219 23:45:53.880649 <6>[ 0.661700] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10220 23:45:53.883735 <6>[ 0.668886] pnp: PnP ACPI: disabled
10221 23:45:53.892306 <6>[ 0.675566] NET: Registered PF_INET protocol family
10222 23:45:53.898806 <6>[ 0.680951] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10223 23:45:53.910760 <6>[ 0.690961] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10224 23:45:53.920906 <6>[ 0.699742] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10225 23:45:53.927382 <6>[ 0.707707] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10226 23:45:53.934112 <6>[ 0.716110] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10227 23:45:53.944787 <6>[ 0.724767] TCP: Hash tables configured (established 32768 bind 32768)
10228 23:45:53.951507 <6>[ 0.731622] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10229 23:45:53.957895 <6>[ 0.738639] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10230 23:45:53.965007 <6>[ 0.746154] NET: Registered PF_UNIX/PF_LOCAL protocol family
10231 23:45:53.971395 <6>[ 0.752304] RPC: Registered named UNIX socket transport module.
10232 23:45:53.974393 <6>[ 0.758457] RPC: Registered udp transport module.
10233 23:45:53.980868 <6>[ 0.763389] RPC: Registered tcp transport module.
10234 23:45:53.987553 <6>[ 0.768319] RPC: Registered tcp NFSv4.1 backchannel transport module.
10235 23:45:53.990929 <6>[ 0.774983] PCI: CLS 0 bytes, default 64
10236 23:45:53.993962 <6>[ 0.779321] Unpacking initramfs...
10237 23:45:54.019188 <6>[ 0.799177] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10238 23:45:54.029182 <6>[ 0.807839] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10239 23:45:54.032666 <6>[ 0.816704] kvm [1]: IPA Size Limit: 40 bits
10240 23:45:54.038839 <6>[ 0.821231] kvm [1]: GICv3: no GICV resource entry
10241 23:45:54.042259 <6>[ 0.826251] kvm [1]: disabling GICv2 emulation
10242 23:45:54.048937 <6>[ 0.830939] kvm [1]: GIC system register CPU interface enabled
10243 23:45:54.052213 <6>[ 0.837097] kvm [1]: vgic interrupt IRQ18
10244 23:45:54.058896 <6>[ 0.841448] kvm [1]: VHE mode initialized successfully
10245 23:45:54.065359 <5>[ 0.847878] Initialise system trusted keyrings
10246 23:45:54.071989 <6>[ 0.852672] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10247 23:45:54.079393 <6>[ 0.862690] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10248 23:45:54.086012 <5>[ 0.869123] NFS: Registering the id_resolver key type
10249 23:45:54.089209 <5>[ 0.874432] Key type id_resolver registered
10250 23:45:54.095884 <5>[ 0.878846] Key type id_legacy registered
10251 23:45:54.102401 <6>[ 0.883123] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10252 23:45:54.108760 <6>[ 0.890047] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10253 23:45:54.115376 <6>[ 0.897773] 9p: Installing v9fs 9p2000 file system support
10254 23:45:54.152415 <5>[ 0.935741] Key type asymmetric registered
10255 23:45:54.155608 <5>[ 0.940070] Asymmetric key parser 'x509' registered
10256 23:45:54.165269 <6>[ 0.945204] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10257 23:45:54.168870 <6>[ 0.952819] io scheduler mq-deadline registered
10258 23:45:54.172285 <6>[ 0.957598] io scheduler kyber registered
10259 23:45:54.191342 <6>[ 0.974799] EINJ: ACPI disabled.
10260 23:45:54.224305 <4>[ 1.001042] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10261 23:45:54.234052 <4>[ 1.011662] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10262 23:45:54.249239 <6>[ 1.032766] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10263 23:45:54.257383 <6>[ 1.040718] printk: console [ttyS0] disabled
10264 23:45:54.285467 <6>[ 1.065347] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10265 23:45:54.291906 <6>[ 1.074818] printk: console [ttyS0] enabled
10266 23:45:54.295376 <6>[ 1.074818] printk: console [ttyS0] enabled
10267 23:45:54.301908 <6>[ 1.083717] printk: bootconsole [mtk8250] disabled
10268 23:45:54.305000 <6>[ 1.083717] printk: bootconsole [mtk8250] disabled
10269 23:45:54.311736 <6>[ 1.094782] SuperH (H)SCI(F) driver initialized
10270 23:45:54.315029 <6>[ 1.100084] msm_serial: driver initialized
10271 23:45:54.328955 <6>[ 1.109116] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10272 23:45:54.338935 <6>[ 1.117666] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10273 23:45:54.345731 <6>[ 1.126208] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10274 23:45:54.355605 <6>[ 1.134836] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10275 23:45:54.365097 <6>[ 1.143542] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10276 23:45:54.372179 <6>[ 1.152255] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10277 23:45:54.382036 <6>[ 1.160797] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10278 23:45:54.388679 <6>[ 1.169594] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10279 23:45:54.398240 <6>[ 1.178138] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10280 23:45:54.410192 <6>[ 1.193813] loop: module loaded
10281 23:45:54.416843 <6>[ 1.199689] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10282 23:45:54.439497 <4>[ 1.222934] mtk-pmic-keys: Failed to locate of_node [id: -1]
10283 23:45:54.446384 <6>[ 1.229820] megasas: 07.719.03.00-rc1
10284 23:45:54.456600 <6>[ 1.239742] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10285 23:45:54.463258 <6>[ 1.246468] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10286 23:45:54.480099 <6>[ 1.263167] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10287 23:45:54.536075 <6>[ 1.312949] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10288 23:45:54.780208 <6>[ 1.563394] Freeing initrd memory: 18288K
10289 23:45:54.791569 <6>[ 1.574866] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10290 23:45:54.802437 <6>[ 1.585775] tun: Universal TUN/TAP device driver, 1.6
10291 23:45:54.805636 <6>[ 1.591864] thunder_xcv, ver 1.0
10292 23:45:54.808766 <6>[ 1.595371] thunder_bgx, ver 1.0
10293 23:45:54.812017 <6>[ 1.598863] nicpf, ver 1.0
10294 23:45:54.822740 <6>[ 1.602914] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10295 23:45:54.825911 <6>[ 1.610391] hns3: Copyright (c) 2017 Huawei Corporation.
10296 23:45:54.832819 <6>[ 1.615977] hclge is initializing
10297 23:45:54.836072 <6>[ 1.619552] e1000: Intel(R) PRO/1000 Network Driver
10298 23:45:54.842513 <6>[ 1.624680] e1000: Copyright (c) 1999-2006 Intel Corporation.
10299 23:45:54.845699 <6>[ 1.630695] e1000e: Intel(R) PRO/1000 Network Driver
10300 23:45:54.852719 <6>[ 1.635910] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10301 23:45:54.859121 <6>[ 1.642094] igb: Intel(R) Gigabit Ethernet Network Driver
10302 23:45:54.865970 <6>[ 1.647744] igb: Copyright (c) 2007-2014 Intel Corporation.
10303 23:45:54.872687 <6>[ 1.653580] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10304 23:45:54.878884 <6>[ 1.660097] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10305 23:45:54.882194 <6>[ 1.666563] sky2: driver version 1.30
10306 23:45:54.889004 <6>[ 1.671542] usbcore: registered new device driver r8152-cfgselector
10307 23:45:54.896165 <6>[ 1.678079] usbcore: registered new interface driver r8152
10308 23:45:54.901950 <6>[ 1.683900] VFIO - User Level meta-driver version: 0.3
10309 23:45:54.908697 <6>[ 1.692214] usbcore: registered new interface driver usb-storage
10310 23:45:54.915450 <6>[ 1.698666] usbcore: registered new device driver onboard-usb-hub
10311 23:45:54.924474 <6>[ 1.707889] mt6397-rtc mt6359-rtc: registered as rtc0
10312 23:45:54.934482 <6>[ 1.713348] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T23:45:54 UTC (1717544754)
10313 23:45:54.937483 <6>[ 1.722937] i2c_dev: i2c /dev entries driver
10314 23:45:54.955090 <6>[ 1.735104] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10315 23:45:54.961254 <4>[ 1.743839] cpu cpu0: supply cpu not found, using dummy regulator
10316 23:45:54.968357 <4>[ 1.750258] cpu cpu1: supply cpu not found, using dummy regulator
10317 23:45:54.975162 <4>[ 1.756664] cpu cpu2: supply cpu not found, using dummy regulator
10318 23:45:54.981647 <4>[ 1.763072] cpu cpu3: supply cpu not found, using dummy regulator
10319 23:45:54.988225 <4>[ 1.769486] cpu cpu4: supply cpu not found, using dummy regulator
10320 23:45:54.994910 <4>[ 1.775881] cpu cpu5: supply cpu not found, using dummy regulator
10321 23:45:55.001541 <4>[ 1.782282] cpu cpu6: supply cpu not found, using dummy regulator
10322 23:45:55.005059 <4>[ 1.788680] cpu cpu7: supply cpu not found, using dummy regulator
10323 23:45:55.026773 <6>[ 1.810319] cpu cpu0: EM: created perf domain
10324 23:45:55.030009 <6>[ 1.815237] cpu cpu4: EM: created perf domain
10325 23:45:55.037505 <6>[ 1.820800] sdhci: Secure Digital Host Controller Interface driver
10326 23:45:55.044455 <6>[ 1.827235] sdhci: Copyright(c) Pierre Ossman
10327 23:45:55.050457 <6>[ 1.832158] Synopsys Designware Multimedia Card Interface Driver
10328 23:45:55.057155 <6>[ 1.838774] sdhci-pltfm: SDHCI platform and OF driver helper
10329 23:45:55.060272 <6>[ 1.838837] mmc0: CQHCI version 5.10
10330 23:45:55.066997 <6>[ 1.848999] ledtrig-cpu: registered to indicate activity on CPUs
10331 23:45:55.073537 <6>[ 1.856027] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10332 23:45:55.080405 <6>[ 1.863066] usbcore: registered new interface driver usbhid
10333 23:45:55.083596 <6>[ 1.868886] usbhid: USB HID core driver
10334 23:45:55.090080 <6>[ 1.873094] spi_master spi0: will run message pump with realtime priority
10335 23:45:55.138224 <6>[ 1.915191] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10336 23:45:55.157054 <6>[ 1.930773] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10337 23:45:55.160424 <6>[ 1.941302] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17814
10338 23:45:55.167896 <6>[ 1.945605] cros-ec-spi spi0.0: Chrome EC device registered
10339 23:45:55.171312 <6>[ 1.956228] mmc0: Command Queue Engine enabled
10340 23:45:55.177855 <6>[ 1.960959] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10341 23:45:55.184699 <6>[ 1.968111] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10342 23:45:55.194348 <6>[ 1.969029] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10343 23:45:55.201315 <6>[ 1.976412] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10344 23:45:55.204635 <6>[ 1.983180] NET: Registered PF_PACKET protocol family
10345 23:45:55.211018 <6>[ 1.989565] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10346 23:45:55.214481 <6>[ 1.993513] 9pnet: Installing 9P2000 support
10347 23:45:55.221261 <6>[ 1.999291] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10348 23:45:55.224198 <5>[ 2.003228] Key type dns_resolver registered
10349 23:45:55.231043 <6>[ 2.009005] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10350 23:45:55.234513 <6>[ 2.013461] registered taskstats version 1
10351 23:45:55.240912 <5>[ 2.023823] Loading compiled-in X.509 certificates
10352 23:45:55.268226 <4>[ 2.045076] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10353 23:45:55.277731 <4>[ 2.055766] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10354 23:45:55.295081 <6>[ 2.078694] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10355 23:45:55.301679 <6>[ 2.085544] xhci-mtk 11200000.usb: xHCI Host Controller
10356 23:45:55.308114 <6>[ 2.091076] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10357 23:45:55.318425 <6>[ 2.098940] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10358 23:45:55.324979 <6>[ 2.108376] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10359 23:45:55.331479 <6>[ 2.114539] xhci-mtk 11200000.usb: xHCI Host Controller
10360 23:45:55.338089 <6>[ 2.120048] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10361 23:45:55.344738 <6>[ 2.127698] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10362 23:45:55.351389 <6>[ 2.135423] hub 1-0:1.0: USB hub found
10363 23:45:55.354669 <6>[ 2.139440] hub 1-0:1.0: 1 port detected
10364 23:45:55.364965 <6>[ 2.143702] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10365 23:45:55.367999 <6>[ 2.152314] hub 2-0:1.0: USB hub found
10366 23:45:55.371372 <6>[ 2.156342] hub 2-0:1.0: 1 port detected
10367 23:45:55.379584 <6>[ 2.163335] mtk-msdc 11f70000.mmc: Got CD GPIO
10368 23:45:55.390264 <6>[ 2.170952] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10369 23:45:55.396726 <6>[ 2.178971] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10370 23:45:55.406623 <4>[ 2.186882] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10371 23:45:55.416643 <6>[ 2.196403] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10372 23:45:55.423102 <6>[ 2.204483] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10373 23:45:55.429642 <6>[ 2.212510] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10374 23:45:55.439671 <6>[ 2.220444] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10375 23:45:55.446278 <6>[ 2.228261] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10376 23:45:55.456222 <6>[ 2.236077] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10377 23:45:55.465906 <6>[ 2.246449] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10378 23:45:55.472560 <6>[ 2.254811] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10379 23:45:55.482437 <6>[ 2.263166] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10380 23:45:55.489058 <6>[ 2.271509] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10381 23:45:55.498978 <6>[ 2.279847] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10382 23:45:55.508919 <6>[ 2.288184] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10383 23:45:55.515562 <6>[ 2.296521] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10384 23:45:55.525664 <6>[ 2.304858] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10385 23:45:55.532839 <6>[ 2.313195] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10386 23:45:55.542256 <6>[ 2.321532] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10387 23:45:55.548967 <6>[ 2.329869] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10388 23:45:55.558850 <6>[ 2.338209] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10389 23:45:55.565507 <6>[ 2.346547] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10390 23:45:55.575778 <6>[ 2.354885] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10391 23:45:55.581979 <6>[ 2.363223] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10392 23:45:55.588943 <6>[ 2.371968] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10393 23:45:55.595470 <6>[ 2.379109] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10394 23:45:55.602284 <6>[ 2.385858] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10395 23:45:55.612414 <6>[ 2.392599] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10396 23:45:55.618767 <6>[ 2.399505] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10397 23:45:55.625399 <6>[ 2.406352] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10398 23:45:55.635455 <6>[ 2.415487] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10399 23:45:55.645659 <6>[ 2.424606] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10400 23:45:55.655345 <6>[ 2.433900] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10401 23:45:55.665392 <6>[ 2.443367] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10402 23:45:55.671681 <6>[ 2.452832] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10403 23:45:55.681651 <6>[ 2.461952] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10404 23:45:55.691851 <6>[ 2.471418] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10405 23:45:55.701738 <6>[ 2.480535] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10406 23:45:55.711380 <6>[ 2.489828] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10407 23:45:55.721350 <6>[ 2.500006] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10408 23:45:55.731746 <6>[ 2.511664] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10409 23:45:55.737975 <6>[ 2.520977] Trying to probe devices needed for running init ...
10410 23:45:55.763133 <6>[ 2.543615] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10411 23:45:55.791198 <6>[ 2.574620] hub 2-1:1.0: USB hub found
10412 23:45:55.794496 <6>[ 2.579092] hub 2-1:1.0: 3 ports detected
10413 23:45:55.802552 <6>[ 2.586025] hub 2-1:1.0: USB hub found
10414 23:45:55.805566 <6>[ 2.590398] hub 2-1:1.0: 3 ports detected
10415 23:45:55.915004 <6>[ 2.695337] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10416 23:45:56.069563 <6>[ 2.853469] hub 1-1:1.0: USB hub found
10417 23:45:56.073182 <6>[ 2.857906] hub 1-1:1.0: 4 ports detected
10418 23:45:56.082965 <6>[ 2.866384] hub 1-1:1.0: USB hub found
10419 23:45:56.085973 <6>[ 2.870745] hub 1-1:1.0: 4 ports detected
10420 23:45:56.147239 <6>[ 2.927661] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10421 23:45:56.255742 <6>[ 3.036027] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10422 23:45:56.292057 <4>[ 3.072292] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10423 23:45:56.301697 <4>[ 3.081414] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10424 23:45:56.345049 <6>[ 3.129022] r8152 2-1.3:1.0 eth0: v1.12.13
10425 23:45:56.407007 <6>[ 3.187393] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10426 23:45:56.539884 <6>[ 3.323277] hub 1-1.4:1.0: USB hub found
10427 23:45:56.542975 <6>[ 3.327951] hub 1-1.4:1.0: 2 ports detected
10428 23:45:56.552536 <6>[ 3.335964] hub 1-1.4:1.0: USB hub found
10429 23:45:56.555593 <6>[ 3.340628] hub 1-1.4:1.0: 2 ports detected
10430 23:45:56.850184 <6>[ 3.631243] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10431 23:45:57.042208 <6>[ 3.823236] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10432 23:45:57.963809 <6>[ 4.747937] r8152 2-1.3:1.0 eth0: carrier on
10433 23:45:58.006826 <5>[ 4.775157] Sending DHCP requests ., OK
10434 23:45:58.013469 <6>[ 4.795412] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10435 23:45:58.016918 <6>[ 4.803706] IP-Config: Complete:
10436 23:45:58.030083 <6>[ 4.807201] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10437 23:45:58.036730 <6>[ 4.817909] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10438 23:45:58.043449 <6>[ 4.826528] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10439 23:45:58.049849 <6>[ 4.826538] nameserver0=192.168.201.1
10440 23:45:58.053099 <6>[ 4.838660] clk: Disabling unused clocks
10441 23:45:58.056508 <6>[ 4.844145] ALSA device list:
10442 23:45:58.063185 <6>[ 4.847411] No soundcards found.
10443 23:45:58.070312 <6>[ 4.854602] Freeing unused kernel memory: 8512K
10444 23:45:58.073652 <6>[ 4.859572] Run /init as init process
10445 23:45:58.082878 Loading, please wait...
10446 23:45:58.114806 Starting systemd-udevd version 252.22-1~deb12u1
10447 23:45:58.324495 <6>[ 5.105633] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10448 23:45:58.337037 <6>[ 5.121362] remoteproc remoteproc0: scp is available
10449 23:45:58.343777 <6>[ 5.127262] remoteproc remoteproc0: powering up scp
10450 23:45:58.350274 <6>[ 5.132428] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10451 23:45:58.360215 <6>[ 5.134373] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10452 23:45:58.363662 <6>[ 5.142433] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10453 23:45:58.373485 <6>[ 5.148602] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10454 23:45:58.376709 <6>[ 5.160841] mc: Linux media interface: v0.10
10455 23:45:58.386772 <6>[ 5.162936] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10456 23:45:58.396585 <3>[ 5.176943] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10457 23:45:58.403129 <3>[ 5.185603] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10458 23:45:58.413095 <3>[ 5.193837] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10459 23:45:58.420157 <4>[ 5.197096] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10460 23:45:58.426415 <6>[ 5.204833] videodev: Linux video capture interface: v2.00
10461 23:45:58.432911 <4>[ 5.214819] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10462 23:45:58.442742 <3>[ 5.215026] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10463 23:45:58.449481 <3>[ 5.215043] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10464 23:45:58.459417 <3>[ 5.215046] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10465 23:45:58.465972 <3>[ 5.215053] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10466 23:45:58.472528 <3>[ 5.215055] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10467 23:45:58.479203 <6>[ 5.215403] Bluetooth: Core ver 2.22
10468 23:45:58.486014 <3>[ 5.216397] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10469 23:45:58.492512 <6>[ 5.218123] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10470 23:45:58.502302 <3>[ 5.220296] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10471 23:45:58.508936 <3>[ 5.220313] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10472 23:45:58.518883 <3>[ 5.220317] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10473 23:45:58.525575 <3>[ 5.220896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10474 23:45:58.535551 <3>[ 5.220912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10475 23:45:58.542056 <3>[ 5.220916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10476 23:45:58.548631 <3>[ 5.220931] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10477 23:45:58.558672 <3>[ 5.220935] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10478 23:45:58.565463 <3>[ 5.220960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10479 23:45:58.571926 <6>[ 5.300559] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10480 23:45:58.581756 <6>[ 5.307476] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10481 23:45:58.585197 <6>[ 5.307550] NET: Registered PF_BLUETOOTH protocol family
10482 23:45:58.591679 <6>[ 5.307552] Bluetooth: HCI device and connection manager initialized
10483 23:45:58.598405 <6>[ 5.307569] Bluetooth: HCI socket layer initialized
10484 23:45:58.601779 <6>[ 5.307573] Bluetooth: L2CAP socket layer initialized
10485 23:45:58.608491 <6>[ 5.307581] Bluetooth: SCO socket layer initialized
10486 23:45:58.618173 <6>[ 5.315466] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10487 23:45:58.624715 <6>[ 5.315472] remoteproc remoteproc0: remote processor scp is now up
10488 23:45:58.634777 <6>[ 5.332559] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10489 23:45:58.638290 <6>[ 5.339788] pci_bus 0000:00: root bus resource [bus 00-ff]
10490 23:45:58.645273 <6>[ 5.339795] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10491 23:45:58.655098 <6>[ 5.339799] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10492 23:45:58.661835 <6>[ 5.339840] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10493 23:45:58.671809 <6>[ 5.348032] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10494 23:45:58.678168 <6>[ 5.352149] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10495 23:45:58.688157 <6>[ 5.356231] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10496 23:45:58.695049 <4>[ 5.370000] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10497 23:45:58.701498 <4>[ 5.370000] Fallback method does not support PEC.
10498 23:45:58.711444 <6>[ 5.370961] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10499 23:45:58.714547 <6>[ 5.375576] pci 0000:00:00.0: supports D1 D2
10500 23:45:58.721280 <6>[ 5.403183] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10501 23:45:58.728572 <6>[ 5.406200] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10502 23:45:58.738352 <3>[ 5.434820] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10503 23:45:58.745057 <6>[ 5.436459] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10504 23:45:58.751678 <6>[ 5.446769] usbcore: registered new interface driver btusb
10505 23:45:58.761967 <4>[ 5.447258] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10506 23:45:58.768460 <3>[ 5.447268] Bluetooth: hci0: Failed to load firmware file (-2)
10507 23:45:58.774787 <3>[ 5.447272] Bluetooth: hci0: Failed to set up firmware (-2)
10508 23:45:58.784748 <4>[ 5.447276] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10509 23:45:58.791408 <6>[ 5.451866] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10510 23:45:58.797927 <6>[ 5.461194] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10511 23:45:58.804607 <6>[ 5.469321] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10512 23:45:58.817885 <6>[ 5.478040] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10513 23:45:58.824454 <6>[ 5.490424] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10514 23:45:58.834891 <6>[ 5.490439] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10515 23:45:58.837768 <6>[ 5.499750] usbcore: registered new interface driver uvcvideo
10516 23:45:58.844648 <6>[ 5.504095] pci 0000:01:00.0: supports D1 D2
10517 23:45:58.850801 <6>[ 5.504530] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10518 23:45:58.857507 <3>[ 5.516789] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10519 23:45:58.867649 <6>[ 5.519113] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10520 23:45:58.874128 <6>[ 5.535196] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10521 23:45:58.880872 <6>[ 5.662333] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10522 23:45:58.890485 <6>[ 5.670412] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10523 23:45:58.897194 <6>[ 5.678411] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10524 23:45:58.904035 <6>[ 5.686410] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10525 23:45:58.913921 <6>[ 5.694410] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10526 23:45:58.917075 <6>[ 5.702409] pci 0000:00:00.0: PCI bridge to [bus 01]
10527 23:45:58.927171 <6>[ 5.707625] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10528 23:45:58.933498 <6>[ 5.715751] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10529 23:45:58.940130 <6>[ 5.722541] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10530 23:45:58.946737 <6>[ 5.729259] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10531 23:45:58.969378 <5>[ 5.750272] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10532 23:45:58.992676 <5>[ 5.773975] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10533 23:45:58.999369 <5>[ 5.781400] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10534 23:45:59.009418 <4>[ 5.789850] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10535 23:45:59.015704 <6>[ 5.798760] cfg80211: failed to load regulatory.db
10536 23:45:59.069423 <6>[ 5.850157] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10537 23:45:59.075506 <6>[ 5.857685] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10538 23:45:59.100155 <6>[ 5.884644] mt7921e 0000:01:00.0: ASIC revision: 79610010
10539 23:45:59.203458 <6>[ 5.984776] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10540 23:45:59.206707 <6>[ 5.984776]
10541 23:45:59.236100 Begin: Loading essential drivers ... done.
10542 23:45:59.239141 Begin: Running /scripts/init-premount ... done.
10543 23:45:59.245944 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10544 23:45:59.255645 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10545 23:45:59.259047 Device /sys/class/net/eth0 found
10546 23:45:59.259142 done.
10547 23:45:59.265467 Begin: Waiting up to 180 secs for any network device to become available ... done.
10548 23:45:59.318869 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10549 23:45:59.325722 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10550 23:45:59.332082 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10551 23:45:59.338553 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10552 23:45:59.345101 host : mt8192-asurada-spherion-r0-cbg-4
10553 23:45:59.351825 domain : lava-rack
10554 23:45:59.355175 rootserver: 192.168.201.1 rootpath:
10555 23:45:59.355257 filename :
10556 23:45:59.437048 done.
10557 23:45:59.443684 Begin: Running /scripts/nfs-bottom ... done.
10558 23:45:59.457205 Begin: Running /scripts/init-bottom ... done.
10559 23:45:59.474083 <6>[ 6.255350] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10560 23:46:00.771240 <6>[ 7.555920] NET: Registered PF_INET6 protocol family
10561 23:46:00.778554 <6>[ 7.563062] Segment Routing with IPv6
10562 23:46:00.781745 <6>[ 7.567022] In-situ OAM (IOAM) with IPv6
10563 23:46:00.940299 <30>[ 7.698650] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10564 23:46:00.946882 <30>[ 7.731785] systemd[1]: Detected architecture arm64.
10565 23:46:00.954422
10566 23:46:00.957538 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10567 23:46:00.957621
10568 23:46:00.979239 <30>[ 7.764073] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10569 23:46:01.967288 <30>[ 8.748424] systemd[1]: Queued start job for default target graphical.target.
10570 23:46:02.007135 <30>[ 8.788366] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10571 23:46:02.013502 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10572 23:46:02.035828 <30>[ 8.817245] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10573 23:46:02.045660 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10574 23:46:02.063636 <30>[ 8.845123] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10575 23:46:02.073438 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10576 23:46:02.091924 <30>[ 8.873542] systemd[1]: Created slice user.slice - User and Session Slice.
10577 23:46:02.098562 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10578 23:46:02.122370 <30>[ 8.900239] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10579 23:46:02.131815 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10580 23:46:02.149325 <30>[ 8.927650] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10581 23:46:02.156022 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10582 23:46:02.184488 <30>[ 8.955973] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10583 23:46:02.194303 <30>[ 8.975890] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10584 23:46:02.201213 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10585 23:46:02.218716 <30>[ 8.999754] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10586 23:46:02.228071 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10587 23:46:02.245973 <30>[ 9.027549] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10588 23:46:02.256144 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10589 23:46:02.270997 <30>[ 9.055895] systemd[1]: Reached target paths.target - Path Units.
10590 23:46:02.281166 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10591 23:46:02.298233 <30>[ 9.079824] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10592 23:46:02.304970 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10593 23:46:02.318434 <30>[ 9.103400] systemd[1]: Reached target slices.target - Slice Units.
10594 23:46:02.328652 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10595 23:46:02.343275 <30>[ 9.127859] systemd[1]: Reached target swap.target - Swaps.
10596 23:46:02.349584 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10597 23:46:02.370437 <30>[ 9.151890] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10598 23:46:02.380135 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10599 23:46:02.398858 <30>[ 9.180324] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10600 23:46:02.408725 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10601 23:46:02.428637 <30>[ 9.210137] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10602 23:46:02.438541 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10603 23:46:02.455247 <30>[ 9.236765] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10604 23:46:02.465135 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10605 23:46:02.483169 <30>[ 9.264747] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10606 23:46:02.489507 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10607 23:46:02.511244 <30>[ 9.292885] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10608 23:46:02.521061 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10609 23:46:02.540379 <30>[ 9.322031] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10610 23:46:02.550440 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10611 23:46:02.567205 <30>[ 9.348518] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10612 23:46:02.576999 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10613 23:46:02.634086 <30>[ 9.415585] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10614 23:46:02.640487 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10615 23:46:02.662551 <30>[ 9.444040] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10616 23:46:02.668983 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10617 23:46:02.714389 <30>[ 9.495720] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10618 23:46:02.720664 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10619 23:46:02.749124 <30>[ 9.524061] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10620 23:46:02.763884 <30>[ 9.545470] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10621 23:46:02.773791 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10622 23:46:02.793121 <30>[ 9.574693] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10623 23:46:02.799668 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10624 23:46:02.822076 <30>[ 9.603452] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10625 23:46:02.828292 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10626 23:46:02.854282 <30>[ 9.635843] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10627 23:46:02.860781 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10628 23:46:02.870562 <6>[ 9.652274] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10629 23:46:02.884799 <30>[ 9.666147] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10630 23:46:02.894246 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10631 23:46:02.915410 <30>[ 9.697034] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10632 23:46:02.922055 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10633 23:46:02.947436 <30>[ 9.729091] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10634 23:46:02.954112 Startin<6>[ 9.737905] fuse: init (API version 7.37)
10635 23:46:02.960536 g [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10636 23:46:02.988033 <30>[ 9.769364] systemd[1]: Starting systemd-journald.service - Journal Service...
10637 23:46:02.994284 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10638 23:46:03.025651 <30>[ 9.806959] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10639 23:46:03.032144 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10640 23:46:03.058821 <30>[ 9.836868] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10641 23:46:03.065235 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10642 23:46:03.092066 <30>[ 9.873619] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10643 23:46:03.101787 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10644 23:46:03.124591 <30>[ 9.905253] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10645 23:46:03.134526 <3>[ 9.908158] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10646 23:46:03.140911 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10647 23:46:03.164132 <3>[ 9.945604] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10648 23:46:03.170900 <30>[ 9.947619] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10649 23:46:03.180607 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10650 23:46:03.198581 <30>[ 9.980178] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10651 23:46:03.208539 <3>[ 9.980396] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10652 23:46:03.215008 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10653 23:46:03.234186 <30>[ 10.015544] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10654 23:46:03.240941 <3>[ 10.016392] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10655 23:46:03.251055 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10656 23:46:03.270591 <30>[ 10.051927] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10657 23:46:03.280600 <3>[ 10.054855] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10658 23:46:03.286885 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10659 23:46:03.307925 <30>[ 10.088943] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10660 23:46:03.314115 <3>[ 10.094441] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10661 23:46:03.324123 <30>[ 10.097220] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10662 23:46:03.330886 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10663 23:46:03.348491 <3>[ 10.130302] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10664 23:46:03.359691 <30>[ 10.141343] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10665 23:46:03.366318 <30>[ 10.149669] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10666 23:46:03.384216 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Mo<3>[ 10.164665] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10667 23:46:03.384325 dule dm_mod.
10668 23:46:03.404365 <30>[ 10.185769] systemd[1]: modprobe@drm.service: Deactivated successfully.
10669 23:46:03.411530 <30>[ 10.193684] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10670 23:46:03.421002 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10671 23:46:03.443017 <30>[ 10.224546] systemd[1]: Started systemd-journald.service - Journal Service.
10672 23:46:03.449333 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10673 23:46:03.475861 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10674 23:46:03.501172 <4>[ 10.276324] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10675 23:46:03.511160 <3>[ 10.291984] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10676 23:46:03.517614 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10677 23:46:03.541132 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10678 23:46:03.559721 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10679 23:46:03.579070 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10680 23:46:03.599330 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10681 23:46:03.619107 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10682 23:46:03.640569 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10683 23:46:03.686214 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10684 23:46:03.706992 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10685 23:46:03.755138 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10686 23:46:03.780866 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10687 23:46:03.806503 <46>[ 10.588200] systemd-journald[306]: Received client request to flush runtime journal.
10688 23:46:03.813013 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10689 23:46:03.842045 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10690 23:46:04.130477 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10691 23:46:04.150715 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10692 23:46:04.172058 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10693 23:46:04.191155 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10694 23:46:04.943641 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10695 23:46:04.999431 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10696 23:46:05.245196 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10697 23:46:05.343949 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10698 23:46:05.366023 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10699 23:46:05.381974 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10700 23:46:05.438284 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10701 23:46:05.466593 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10702 23:46:05.649471 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10703 23:46:05.716184 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10704 23:46:05.804240 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10705 23:46:06.013666 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10706 23:46:06.058246 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10707 23:46:06.086428 <6>[ 12.871687] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10708 23:46:06.110626 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10709 23:46:06.125457 <4>[ 12.909948] power_supply_show_property: 4 callbacks suppressed
10710 23:46:06.135216 <3>[ 12.910131] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10711 23:46:06.144735 <3>[ 12.926022] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10712 23:46:06.171937 <3>[ 12.954080] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10713 23:46:06.200577 <3>[ 12.982408] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10714 23:46:06.229096 <3>[ 13.011210] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10715 23:46:06.256747 <3>[ 13.038739] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10716 23:46:06.266768 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10717 23:46:06.285616 <3>[ 13.067475] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10718 23:46:06.292007 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10719 23:46:06.316110 [[0;32m OK [<3>[ 13.097624] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10720 23:46:06.322602 0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10721 23:46:06.348693 [[0;32m OK [<3>[ 13.128056] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10722 23:46:06.355395 0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10723 23:46:06.375106 <3>[ 13.156884] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10724 23:46:06.421532 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10725 23:46:06.434712 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10726 23:46:06.454214 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10727 23:46:06.474901 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10728 23:46:06.499607 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10729 23:46:06.526624 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10730 23:46:06.545818 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10731 23:46:06.561907 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10732 23:46:06.587011 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10733 23:46:06.612027 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10734 23:46:06.629748 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10735 23:46:06.648240 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10736 23:46:06.668358 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10737 23:46:06.685736 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10738 23:46:06.703115 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10739 23:46:06.721605 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10740 23:46:06.737298 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10741 23:46:06.787016 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10742 23:46:06.818848 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10743 23:46:06.898621 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10744 23:46:06.924133 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10745 23:46:06.948208 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10746 23:46:07.008110 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10747 23:46:07.032350 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10748 23:46:07.083044 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10749 23:46:07.134657 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10750 23:46:07.154727 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10751 23:46:07.175277 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10752 23:46:07.230666 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10753 23:46:07.260538 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10754 23:46:07.280366 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10755 23:46:07.298744 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10756 23:46:07.351256 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10757 23:46:07.429638 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10758 23:46:07.520168
10759 23:46:07.523435 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10760 23:46:07.523558
10761 23:46:07.526869 debian-bookworm-arm64 login: root (automatic login)
10762 23:46:07.526950
10763 23:46:07.803001 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024 aarch64
10764 23:46:07.803144
10765 23:46:07.809473 The programs included with the Debian GNU/Linux system are free software;
10766 23:46:07.816292 the exact distribution terms for each program are described in the
10767 23:46:07.819444 individual files in /usr/share/doc/*/copyright.
10768 23:46:07.819524
10769 23:46:07.825980 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10770 23:46:07.829469 permitted by applicable law.
10771 23:46:08.806079 Matched prompt #10: / #
10773 23:46:08.806359 Setting prompt string to ['/ #']
10774 23:46:08.806452 end: 2.2.5.1 login-action (duration 00:00:16) [common]
10776 23:46:08.806641 end: 2.2.5 auto-login-action (duration 00:00:16) [common]
10777 23:46:08.806729 start: 2.2.6 expect-shell-connection (timeout 00:03:46) [common]
10778 23:46:08.806798 Setting prompt string to ['/ #']
10779 23:46:08.806857 Forcing a shell prompt, looking for ['/ #']
10781 23:46:08.857081 / #
10782 23:46:08.857252 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10783 23:46:08.857371 Waiting using forced prompt support (timeout 00:02:30)
10784 23:46:08.862085
10785 23:46:08.862361 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10786 23:46:08.862460 start: 2.2.7 export-device-env (timeout 00:03:46) [common]
10788 23:46:08.962789 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172964/extract-nfsrootfs-yfsyau3h'
10789 23:46:08.967492 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172964/extract-nfsrootfs-yfsyau3h'
10791 23:46:09.068039 / # export NFS_SERVER_IP='192.168.201.1'
10792 23:46:09.072965 export NFS_SERVER_IP='192.168.201.1'
10793 23:46:09.073252 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10794 23:46:09.073388 end: 2.2 depthcharge-retry (duration 00:01:14) [common]
10795 23:46:09.073477 end: 2 depthcharge-action (duration 00:01:14) [common]
10796 23:46:09.073566 start: 3 lava-test-retry (timeout 00:08:08) [common]
10797 23:46:09.073651 start: 3.1 lava-test-shell (timeout 00:08:08) [common]
10798 23:46:09.073726 Using namespace: common
10800 23:46:09.174050 / # #
10801 23:46:09.174213 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10802 23:46:09.179180 #
10803 23:46:09.179458 Using /lava-14172964
10805 23:46:09.279816 / # export SHELL=/bin/bash
10806 23:46:09.284752 export SHELL=/bin/bash
10808 23:46:09.385258 / # . /lava-14172964/environment
10809 23:46:09.390330 . /lava-14172964/environment
10811 23:46:09.495918 / # /lava-14172964/bin/lava-test-runner /lava-14172964/0
10812 23:46:09.496156 Test shell timeout: 10s (minimum of the action and connection timeout)
10813 23:46:09.501309 /lava-14172964/bin/lava-test-runner /lava-14172964/0
10814 23:46:09.715633 + export TESTRUN_ID=0_timesync-off
10815 23:46:09.719015 + TESTRUN_ID=0_timesync-off
10816 23:46:09.722107 + cd /lava-14172964/0/tests/0_timesync-off
10817 23:46:09.725524 ++ cat uuid
10818 23:46:09.725607 + UUID=14172964_1.6.2.3.1
10819 23:46:09.729102 + set +x
10820 23:46:09.732667 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14172964_1.6.2.3.1>
10821 23:46:09.732958 Received signal: <STARTRUN> 0_timesync-off 14172964_1.6.2.3.1
10822 23:46:09.733032 Starting test lava.0_timesync-off (14172964_1.6.2.3.1)
10823 23:46:09.733118 Skipping test definition patterns.
10824 23:46:09.735709 + systemctl stop systemd-timesyncd
10825 23:46:09.779907 + set +x
10826 23:46:09.782964 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14172964_1.6.2.3.1>
10827 23:46:09.783239 Received signal: <ENDRUN> 0_timesync-off 14172964_1.6.2.3.1
10828 23:46:09.783327 Ending use of test pattern.
10829 23:46:09.783389 Ending test lava.0_timesync-off (14172964_1.6.2.3.1), duration 0.05
10831 23:46:09.835114 + export TESTRUN_ID=1_kselftest-alsa
10832 23:46:09.838053 + TESTRUN_ID=1_kselftest-alsa
10833 23:46:09.844611 + cd /lava-14172964/0/tests/1_kselftest-alsa
10834 23:46:09.844696 ++ cat uuid
10835 23:46:09.847992 + UUID=14172964_1.6.2.3.5
10836 23:46:09.848108 + set +x
10837 23:46:09.851120 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 14172964_1.6.2.3.5>
10838 23:46:09.851376 Received signal: <STARTRUN> 1_kselftest-alsa 14172964_1.6.2.3.5
10839 23:46:09.851450 Starting test lava.1_kselftest-alsa (14172964_1.6.2.3.5)
10840 23:46:09.851532 Skipping test definition patterns.
10841 23:46:09.854513 + cd ./automated/linux/kselftest/
10842 23:46:09.880873 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10843 23:46:09.905591 INFO: install_deps skipped
10844 23:46:10.397967 --2024-06-04 23:46:10-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10845 23:46:10.404370 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10846 23:46:10.523935 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10847 23:46:10.648769 HTTP request sent, awaiting response... 200 OK
10848 23:46:10.652080 Length: 1642752 (1.6M) [application/octet-stream]
10849 23:46:10.655398 Saving to: 'kselftest_armhf.tar.gz'
10850 23:46:10.655505
10851 23:46:10.655598
10852 23:46:10.898644 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
10853 23:46:11.147743 kselftest_armhf.tar 3%[ ] 49.22K 197KB/s
10854 23:46:11.444735 kselftest_armhf.tar 13%[=> ] 219.84K 441KB/s
10855 23:46:11.571550 kselftest_armhf.tar 50%[=========> ] 804.33K 1011KB/s
10856 23:46:11.578168 kselftest_armhf.tar 100%[===================>] 1.57M 1.70MB/s in 0.9s
10857 23:46:11.578288
10858 23:46:11.721988 2024-06-04 23:46:11 (1.70 MB/s) - 'kselftest_armhf.tar.gz' saved [1642752/1642752]
10859 23:46:11.722172
10860 23:46:15.820205 skiplist:
10861 23:46:15.823404 ========================================
10862 23:46:15.826646 ========================================
10863 23:46:15.867521 alsa:mixer-test
10864 23:46:15.885682 ============== Tests to run ===============
10865 23:46:15.885772 alsa:mixer-test
10866 23:46:15.889025 ===========End Tests to run ===============
10867 23:46:15.893942 shardfile-alsa pass
10868 23:46:15.984435 <12>[ 22.770547] kselftest: Running tests in alsa
10869 23:46:15.992296 TAP version 13
10870 23:46:16.004604 1..1
10871 23:46:16.017214 # selftests: alsa: mixer-test
10872 23:46:16.505877 # TAP version 13
10873 23:46:16.506027 # 1..0
10874 23:46:16.512348 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
10875 23:46:16.515957 ok 1 selftests: alsa: mixer-test
10876 23:46:17.919837 alsa_mixer-test pass
10877 23:46:17.995473 + ../../utils/send-to-lava.sh ./output/result.txt
10878 23:46:18.050669 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
10879 23:46:18.050981 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
10881 23:46:18.089328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
10882 23:46:18.089431 + set +x
10883 23:46:18.089668 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
10885 23:46:18.096208 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 14172964_1.6.2.3.5>
10886 23:46:18.096463 Received signal: <ENDRUN> 1_kselftest-alsa 14172964_1.6.2.3.5
10887 23:46:18.096536 Ending use of test pattern.
10888 23:46:18.096596 Ending test lava.1_kselftest-alsa (14172964_1.6.2.3.5), duration 8.25
10890 23:46:18.099145 <LAVA_TEST_RUNNER EXIT>
10891 23:46:18.099395 ok: lava_test_shell seems to have completed
10892 23:46:18.099500 alsa_mixer-test: pass
shardfile-alsa: pass
10893 23:46:18.099596 end: 3.1 lava-test-shell (duration 00:00:09) [common]
10894 23:46:18.099678 end: 3 lava-test-retry (duration 00:00:09) [common]
10895 23:46:18.099764 start: 4 finalize (timeout 00:07:59) [common]
10896 23:46:18.099851 start: 4.1 power-off (timeout 00:00:30) [common]
10897 23:46:18.099997 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
10898 23:46:18.177219 >> Command sent successfully.
10899 23:46:18.179564 Returned 0 in 0 seconds
10900 23:46:18.279932 end: 4.1 power-off (duration 00:00:00) [common]
10902 23:46:18.280238 start: 4.2 read-feedback (timeout 00:07:58) [common]
10903 23:46:18.280501 Listened to connection for namespace 'common' for up to 1s
10904 23:46:19.281448 Finalising connection for namespace 'common'
10905 23:46:19.281719 Disconnecting from shell: Finalise
10906 23:46:19.281860 / #
10907 23:46:19.382238 end: 4.2 read-feedback (duration 00:00:01) [common]
10908 23:46:19.382460 end: 4 finalize (duration 00:00:01) [common]
10909 23:46:19.382608 Cleaning after the job
10910 23:46:19.382728 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/ramdisk
10911 23:46:19.385591 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/kernel
10912 23:46:19.399579 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/dtb
10913 23:46:19.399782 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/nfsrootfs
10914 23:46:19.466488 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172964/tftp-deploy-m7ldps3i/modules
10915 23:46:19.472087 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14172964
10916 23:46:20.024044 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14172964
10917 23:46:20.024229 Job finished correctly