Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 37
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 23:41:04.355488 lava-dispatcher, installed at version: 2024.03
2 23:41:04.355760 start: 0 validate
3 23:41:04.355902 Start time: 2024-06-04 23:41:04.355895+00:00 (UTC)
4 23:41:04.356028 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:41:04.356152 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:41:04.606873 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:41:04.607051 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:41:27.610505 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:41:27.610681 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:41:27.868512 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:41:27.868671 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:41:28.372529 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:41:28.372702 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:41:30.376324 validate duration: 26.02
16 23:41:30.376596 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:41:30.376698 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:41:30.376785 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:41:30.376940 Not decompressing ramdisk as can be used compressed.
20 23:41:30.377075 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:41:30.377174 saving as /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/ramdisk/initrd.cpio.gz
22 23:41:30.377281 total size: 5628169 (5 MB)
23 23:41:30.637053 progress 0 % (0 MB)
24 23:41:30.638678 progress 5 % (0 MB)
25 23:41:30.640257 progress 10 % (0 MB)
26 23:41:30.641735 progress 15 % (0 MB)
27 23:41:30.643382 progress 20 % (1 MB)
28 23:41:30.645119 progress 25 % (1 MB)
29 23:41:30.646740 progress 30 % (1 MB)
30 23:41:30.648333 progress 35 % (1 MB)
31 23:41:30.649731 progress 40 % (2 MB)
32 23:41:30.651254 progress 45 % (2 MB)
33 23:41:30.652689 progress 50 % (2 MB)
34 23:41:30.654282 progress 55 % (2 MB)
35 23:41:30.655827 progress 60 % (3 MB)
36 23:41:30.657230 progress 65 % (3 MB)
37 23:41:30.658904 progress 70 % (3 MB)
38 23:41:30.660271 progress 75 % (4 MB)
39 23:41:30.661821 progress 80 % (4 MB)
40 23:41:30.663279 progress 85 % (4 MB)
41 23:41:30.664948 progress 90 % (4 MB)
42 23:41:30.666518 progress 95 % (5 MB)
43 23:41:30.667891 progress 100 % (5 MB)
44 23:41:30.668095 5 MB downloaded in 0.29 s (18.46 MB/s)
45 23:41:30.668253 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:41:30.668491 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:41:30.668578 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:41:30.668660 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:41:30.668799 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:41:30.668868 saving as /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/kernel/Image
52 23:41:30.668931 total size: 54682112 (52 MB)
53 23:41:30.668994 No compression specified
54 23:41:30.670295 progress 0 % (0 MB)
55 23:41:30.684819 progress 5 % (2 MB)
56 23:41:30.699238 progress 10 % (5 MB)
57 23:41:30.713516 progress 15 % (7 MB)
58 23:41:30.727548 progress 20 % (10 MB)
59 23:41:30.741940 progress 25 % (13 MB)
60 23:41:30.755996 progress 30 % (15 MB)
61 23:41:30.770190 progress 35 % (18 MB)
62 23:41:30.784380 progress 40 % (20 MB)
63 23:41:30.799709 progress 45 % (23 MB)
64 23:41:30.814261 progress 50 % (26 MB)
65 23:41:30.828365 progress 55 % (28 MB)
66 23:41:30.842647 progress 60 % (31 MB)
67 23:41:30.856737 progress 65 % (33 MB)
68 23:41:30.870921 progress 70 % (36 MB)
69 23:41:30.885020 progress 75 % (39 MB)
70 23:41:30.899418 progress 80 % (41 MB)
71 23:41:30.913421 progress 85 % (44 MB)
72 23:41:30.927395 progress 90 % (46 MB)
73 23:41:30.941541 progress 95 % (49 MB)
74 23:41:30.955256 progress 100 % (52 MB)
75 23:41:30.955527 52 MB downloaded in 0.29 s (181.96 MB/s)
76 23:41:30.955687 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:41:30.955934 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:41:30.956024 start: 1.3 download-retry (timeout 00:09:59) [common]
80 23:41:30.956109 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 23:41:30.956249 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:41:30.956319 saving as /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/dtb/mt8192-asurada-spherion-r0.dtb
83 23:41:30.956381 total size: 47258 (0 MB)
84 23:41:30.956444 No compression specified
85 23:41:30.957622 progress 69 % (0 MB)
86 23:41:30.957924 progress 100 % (0 MB)
87 23:41:30.958083 0 MB downloaded in 0.00 s (26.52 MB/s)
88 23:41:30.958209 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:41:30.958437 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:41:30.958524 start: 1.4 download-retry (timeout 00:09:59) [common]
92 23:41:30.958609 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 23:41:30.958725 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:41:30.958793 saving as /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/nfsrootfs/full.rootfs.tar
95 23:41:30.958855 total size: 120894716 (115 MB)
96 23:41:30.958917 Using unxz to decompress xz
97 23:41:30.962978 progress 0 % (0 MB)
98 23:41:31.325371 progress 5 % (5 MB)
99 23:41:31.699580 progress 10 % (11 MB)
100 23:41:32.059951 progress 15 % (17 MB)
101 23:41:32.392566 progress 20 % (23 MB)
102 23:41:32.692294 progress 25 % (28 MB)
103 23:41:33.054735 progress 30 % (34 MB)
104 23:41:33.399748 progress 35 % (40 MB)
105 23:41:33.567514 progress 40 % (46 MB)
106 23:41:33.747990 progress 45 % (51 MB)
107 23:41:34.065269 progress 50 % (57 MB)
108 23:41:34.441549 progress 55 % (63 MB)
109 23:41:34.790161 progress 60 % (69 MB)
110 23:41:35.137046 progress 65 % (74 MB)
111 23:41:35.484783 progress 70 % (80 MB)
112 23:41:35.850883 progress 75 % (86 MB)
113 23:41:36.201919 progress 80 % (92 MB)
114 23:41:36.551664 progress 85 % (98 MB)
115 23:41:36.921704 progress 90 % (103 MB)
116 23:41:37.261891 progress 95 % (109 MB)
117 23:41:37.633771 progress 100 % (115 MB)
118 23:41:37.639291 115 MB downloaded in 6.68 s (17.26 MB/s)
119 23:41:37.639692 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:41:37.640106 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:41:37.640241 start: 1.5 download-retry (timeout 00:09:53) [common]
123 23:41:37.640370 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 23:41:37.640590 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:41:37.640696 saving as /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/modules/modules.tar
126 23:41:37.640792 total size: 8603924 (8 MB)
127 23:41:37.640890 Using unxz to decompress xz
128 23:41:37.646255 progress 0 % (0 MB)
129 23:41:37.666786 progress 5 % (0 MB)
130 23:41:37.691711 progress 10 % (0 MB)
131 23:41:37.717956 progress 15 % (1 MB)
132 23:41:37.743433 progress 20 % (1 MB)
133 23:41:37.769791 progress 25 % (2 MB)
134 23:41:37.795489 progress 30 % (2 MB)
135 23:41:37.819755 progress 35 % (2 MB)
136 23:41:37.846501 progress 40 % (3 MB)
137 23:41:37.871719 progress 45 % (3 MB)
138 23:41:37.896825 progress 50 % (4 MB)
139 23:41:37.922592 progress 55 % (4 MB)
140 23:41:37.947872 progress 60 % (4 MB)
141 23:41:37.972520 progress 65 % (5 MB)
142 23:41:37.999497 progress 70 % (5 MB)
143 23:41:38.025622 progress 75 % (6 MB)
144 23:41:38.051732 progress 80 % (6 MB)
145 23:41:38.076211 progress 85 % (7 MB)
146 23:41:38.101007 progress 90 % (7 MB)
147 23:41:38.131223 progress 95 % (7 MB)
148 23:41:38.160033 progress 100 % (8 MB)
149 23:41:38.165751 8 MB downloaded in 0.52 s (15.63 MB/s)
150 23:41:38.166160 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:41:38.166567 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:41:38.166709 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 23:41:38.166848 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 23:41:41.722015 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14172919/extract-nfsrootfs-_tc5mk7h
156 23:41:41.722235 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:41:41.722340 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 23:41:41.722530 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri
159 23:41:41.722663 makedir: /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin
160 23:41:41.722767 makedir: /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/tests
161 23:41:41.722866 makedir: /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/results
162 23:41:41.722972 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-add-keys
163 23:41:41.723119 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-add-sources
164 23:41:41.723252 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-background-process-start
165 23:41:41.723382 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-background-process-stop
166 23:41:41.723510 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-common-functions
167 23:41:41.723637 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-echo-ipv4
168 23:41:41.723764 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-install-packages
169 23:41:41.723891 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-installed-packages
170 23:41:41.724016 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-os-build
171 23:41:41.724143 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-probe-channel
172 23:41:41.724271 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-probe-ip
173 23:41:41.724398 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-target-ip
174 23:41:41.724523 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-target-mac
175 23:41:41.724648 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-target-storage
176 23:41:41.724776 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-test-case
177 23:41:41.724903 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-test-event
178 23:41:41.725029 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-test-feedback
179 23:41:41.725155 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-test-raise
180 23:41:41.725288 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-test-reference
181 23:41:41.725414 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-test-runner
182 23:41:41.725540 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-test-set
183 23:41:41.725672 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-test-shell
184 23:41:41.725804 Updating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-add-keys (debian)
185 23:41:41.725962 Updating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-add-sources (debian)
186 23:41:41.726105 Updating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-install-packages (debian)
187 23:41:41.726248 Updating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-installed-packages (debian)
188 23:41:41.726389 Updating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/bin/lava-os-build (debian)
189 23:41:41.726512 Creating /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/environment
190 23:41:41.726611 LAVA metadata
191 23:41:41.726680 - LAVA_JOB_ID=14172919
192 23:41:41.726744 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:41:41.726862 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 23:41:41.726929 skipped lava-vland-overlay
195 23:41:41.727008 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:41:41.727091 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 23:41:41.727153 skipped lava-multinode-overlay
198 23:41:41.727252 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:41:41.727349 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 23:41:41.727429 Loading test definitions
201 23:41:41.727538 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 23:41:41.727624 Using /lava-14172919 at stage 0
203 23:41:41.727951 uuid=14172919_1.6.2.3.1 testdef=None
204 23:41:41.728052 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:41:41.728157 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 23:41:41.728651 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:41:41.728913 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 23:41:41.729548 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:41:41.729814 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 23:41:41.730377 runner path: /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/0/tests/0_timesync-off test_uuid 14172919_1.6.2.3.1
213 23:41:41.730559 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:41:41.730824 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 23:41:41.730914 Using /lava-14172919 at stage 0
217 23:41:41.731051 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:41:41.731185 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/0/tests/1_kselftest-arm64'
219 23:41:44.599037 Running '/usr/bin/git checkout kernelci.org
220 23:41:44.752201 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 23:41:44.753015 uuid=14172919_1.6.2.3.5 testdef=None
222 23:41:44.753191 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 23:41:44.753471 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 23:41:44.754251 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:41:44.754495 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 23:41:44.755522 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:41:44.755774 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 23:41:44.756733 runner path: /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/0/tests/1_kselftest-arm64 test_uuid 14172919_1.6.2.3.5
232 23:41:44.756829 BOARD='mt8192-asurada-spherion-r0'
233 23:41:44.756896 BRANCH='cip'
234 23:41:44.756957 SKIPFILE='/dev/null'
235 23:41:44.757017 SKIP_INSTALL='True'
236 23:41:44.757075 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:41:44.757138 TST_CASENAME=''
238 23:41:44.757195 TST_CMDFILES='arm64'
239 23:41:44.757360 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:41:44.757578 Creating lava-test-runner.conf files
242 23:41:44.757646 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14172919/lava-overlay-uvo6p_ri/lava-14172919/0 for stage 0
243 23:41:44.757744 - 0_timesync-off
244 23:41:44.757815 - 1_kselftest-arm64
245 23:41:44.757916 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 23:41:44.758012 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 23:41:52.446776 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:41:52.446937 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 23:41:52.447026 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:41:52.447122 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 23:41:52.447214 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 23:41:52.614889 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:41:52.615297 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 23:41:52.615429 extracting modules file /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172919/extract-nfsrootfs-_tc5mk7h
255 23:41:52.845611 extracting modules file /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172919/extract-overlay-ramdisk-ts5exngv/ramdisk
256 23:41:53.084832 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:41:53.085027 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 23:41:53.085169 [common] Applying overlay to NFS
259 23:41:53.085345 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172919/compress-overlay-4fv6khpc/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14172919/extract-nfsrootfs-_tc5mk7h
260 23:41:54.022348 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:41:54.022531 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 23:41:54.022625 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:41:54.022716 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 23:41:54.022800 Building ramdisk /var/lib/lava/dispatcher/tmp/14172919/extract-overlay-ramdisk-ts5exngv/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14172919/extract-overlay-ramdisk-ts5exngv/ramdisk
265 23:41:54.347419 >> 130337 blocks
266 23:41:56.395321 rename /var/lib/lava/dispatcher/tmp/14172919/extract-overlay-ramdisk-ts5exngv/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/ramdisk/ramdisk.cpio.gz
267 23:41:56.395811 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:41:56.395934 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 23:41:56.396038 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 23:41:56.396147 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/kernel/Image']
271 23:42:09.626044 Returned 0 in 13 seconds
272 23:42:09.726675 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/kernel/image.itb
273 23:42:10.102891 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:42:10.103291 output: Created: Wed Jun 5 00:42:10 2024
275 23:42:10.103403 output: Image 0 (kernel-1)
276 23:42:10.103504 output: Description:
277 23:42:10.103599 output: Created: Wed Jun 5 00:42:10 2024
278 23:42:10.103692 output: Type: Kernel Image
279 23:42:10.103784 output: Compression: lzma compressed
280 23:42:10.103871 output: Data Size: 13061430 Bytes = 12755.30 KiB = 12.46 MiB
281 23:42:10.103961 output: Architecture: AArch64
282 23:42:10.104050 output: OS: Linux
283 23:42:10.104134 output: Load Address: 0x00000000
284 23:42:10.104219 output: Entry Point: 0x00000000
285 23:42:10.104307 output: Hash algo: crc32
286 23:42:10.104390 output: Hash value: ecfb5096
287 23:42:10.104479 output: Image 1 (fdt-1)
288 23:42:10.104562 output: Description: mt8192-asurada-spherion-r0
289 23:42:10.104647 output: Created: Wed Jun 5 00:42:10 2024
290 23:42:10.104705 output: Type: Flat Device Tree
291 23:42:10.104760 output: Compression: uncompressed
292 23:42:10.104814 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 23:42:10.104867 output: Architecture: AArch64
294 23:42:10.104920 output: Hash algo: crc32
295 23:42:10.104973 output: Hash value: 0f8e4d2e
296 23:42:10.105026 output: Image 2 (ramdisk-1)
297 23:42:10.105078 output: Description: unavailable
298 23:42:10.105131 output: Created: Wed Jun 5 00:42:10 2024
299 23:42:10.105216 output: Type: RAMDisk Image
300 23:42:10.105330 output: Compression: Unknown Compression
301 23:42:10.105386 output: Data Size: 18717593 Bytes = 18278.90 KiB = 17.85 MiB
302 23:42:10.105439 output: Architecture: AArch64
303 23:42:10.105493 output: OS: Linux
304 23:42:10.105545 output: Load Address: unavailable
305 23:42:10.105598 output: Entry Point: unavailable
306 23:42:10.105651 output: Hash algo: crc32
307 23:42:10.105737 output: Hash value: b992763b
308 23:42:10.105823 output: Default Configuration: 'conf-1'
309 23:42:10.105879 output: Configuration 0 (conf-1)
310 23:42:10.105934 output: Description: mt8192-asurada-spherion-r0
311 23:42:10.106022 output: Kernel: kernel-1
312 23:42:10.106104 output: Init Ramdisk: ramdisk-1
313 23:42:10.106192 output: FDT: fdt-1
314 23:42:10.106274 output: Loadables: kernel-1
315 23:42:10.106361 output:
316 23:42:10.106608 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 23:42:10.106737 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 23:42:10.106882 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 23:42:10.107010 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 23:42:10.107122 No LXC device requested
321 23:42:10.107234 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:42:10.107358 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 23:42:10.107471 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:42:10.107571 Checking files for TFTP limit of 4294967296 bytes.
325 23:42:10.108235 end: 1 tftp-deploy (duration 00:00:40) [common]
326 23:42:10.108372 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:42:10.108494 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:42:10.108650 substitutions:
329 23:42:10.108737 - {DTB}: 14172919/tftp-deploy-fqq5gldl/dtb/mt8192-asurada-spherion-r0.dtb
330 23:42:10.108831 - {INITRD}: 14172919/tftp-deploy-fqq5gldl/ramdisk/ramdisk.cpio.gz
331 23:42:10.108919 - {KERNEL}: 14172919/tftp-deploy-fqq5gldl/kernel/Image
332 23:42:10.109005 - {LAVA_MAC}: None
333 23:42:10.109090 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14172919/extract-nfsrootfs-_tc5mk7h
334 23:42:10.109175 - {NFS_SERVER_IP}: 192.168.201.1
335 23:42:10.109267 - {PRESEED_CONFIG}: None
336 23:42:10.109361 - {PRESEED_LOCAL}: None
337 23:42:10.109462 - {RAMDISK}: 14172919/tftp-deploy-fqq5gldl/ramdisk/ramdisk.cpio.gz
338 23:42:10.109560 - {ROOT_PART}: None
339 23:42:10.109663 - {ROOT}: None
340 23:42:10.109757 - {SERVER_IP}: 192.168.201.1
341 23:42:10.109842 - {TEE}: None
342 23:42:10.109926 Parsed boot commands:
343 23:42:10.110011 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:42:10.110235 Parsed boot commands: tftpboot 192.168.201.1 14172919/tftp-deploy-fqq5gldl/kernel/image.itb 14172919/tftp-deploy-fqq5gldl/kernel/cmdline
345 23:42:10.110358 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:42:10.110476 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:42:10.110603 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:42:10.110716 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:42:10.110820 Not connected, no need to disconnect.
350 23:42:10.110926 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:42:10.111038 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:42:10.111150 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 23:42:10.115034 Setting prompt string to ['lava-test: # ']
354 23:42:10.115446 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:42:10.115582 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:42:10.115713 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:42:10.115866 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:42:10.116139 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
359 23:42:24.105083 Returned 0 in 13 seconds
360 23:42:24.205738 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 23:42:24.206163 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 23:42:24.206292 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 23:42:24.206410 Setting prompt string to 'Starting depthcharge on Spherion...'
365 23:42:24.206509 Changing prompt to 'Starting depthcharge on Spherion...'
366 23:42:24.206609 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 23:42:24.207202 [Enter `^Ec?' for help]
368 23:42:24.207324
369 23:42:24.207428
370 23:42:24.207532 F0: 102B 0000
371 23:42:24.207606
372 23:42:24.207667 F3: 1001 0000 [0200]
373 23:42:24.207730
374 23:42:24.207792 F3: 1001 0000
375 23:42:24.207850
376 23:42:24.207906 F7: 102D 0000
377 23:42:24.207972
378 23:42:24.208033 F1: 0000 0000
379 23:42:24.208104
380 23:42:24.208190 V0: 0000 0000 [0001]
381 23:42:24.208276
382 23:42:24.208361 00: 0007 8000
383 23:42:24.208451
384 23:42:24.208536 01: 0000 0000
385 23:42:24.208624
386 23:42:24.208708 BP: 0C00 0209 [0000]
387 23:42:24.208793
388 23:42:24.208877 G0: 1182 0000
389 23:42:24.208962
390 23:42:24.209046 EC: 0000 0021 [4000]
391 23:42:24.209131
392 23:42:24.209216 S7: 0000 0000 [0000]
393 23:42:24.209297
394 23:42:24.209354 CC: 0000 0000 [0001]
395 23:42:24.209410
396 23:42:24.209465 T0: 0000 0040 [010F]
397 23:42:24.209521
398 23:42:24.209576 Jump to BL
399 23:42:24.209631
400 23:42:24.209686
401 23:42:24.209741
402 23:42:24.209795 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 23:42:24.209856 ARM64: Exception handlers installed.
404 23:42:24.209912 ARM64: Testing exception
405 23:42:24.209968 ARM64: Done test exception
406 23:42:24.210023 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 23:42:24.210079 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 23:42:24.210145 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 23:42:24.210211 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 23:42:24.210268 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 23:42:24.210335 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 23:42:24.210397 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 23:42:24.210469 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 23:42:24.210562 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 23:42:24.210659 WDT: Last reset was cold boot
416 23:42:24.210721 SPI1(PAD0) initialized at 2873684 Hz
417 23:42:24.210806 SPI5(PAD0) initialized at 992727 Hz
418 23:42:24.210894 VBOOT: Loading verstage.
419 23:42:24.210982 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 23:42:24.211074 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 23:42:24.211163 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 23:42:24.211228 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 23:42:24.211285 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 23:42:24.211347 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 23:42:24.211435 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 23:42:24.211521
427 23:42:24.211613
428 23:42:24.211700 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 23:42:24.211792 ARM64: Exception handlers installed.
430 23:42:24.211878 ARM64: Testing exception
431 23:42:24.211970 ARM64: Done test exception
432 23:42:24.212056 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 23:42:24.212157 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 23:42:24.212255 Probing TPM: . done!
435 23:42:24.212342 TPM ready after 0 ms
436 23:42:24.212401 Connected to device vid:did:rid of 1ae0:0028:00
437 23:42:24.212458 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
438 23:42:24.212525 Initialized TPM device CR50 revision 0
439 23:42:24.212582 tlcl_send_startup: Startup return code is 0
440 23:42:24.212638 TPM: setup succeeded
441 23:42:24.212701 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 23:42:24.212759 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 23:42:24.212815 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 23:42:24.212882 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:42:24.212970 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 23:42:24.213060 in-header: 03 07 00 00 08 00 00 00
447 23:42:24.213147 in-data: aa e4 47 04 13 02 00 00
448 23:42:24.213235 Chrome EC: UHEPI supported
449 23:42:24.213312 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 23:42:24.213370 in-header: 03 a9 00 00 08 00 00 00
451 23:42:24.213428 in-data: 84 60 60 08 00 00 00 00
452 23:42:24.213492 Phase 1
453 23:42:24.213548 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 23:42:24.213612 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 23:42:24.213700 VB2:vb2_check_recovery() Recovery was requested manually
456 23:42:24.213787 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 23:42:24.213876 Recovery requested (1009000e)
458 23:42:24.213968 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 23:42:24.214062 tlcl_extend: response is 0
460 23:42:24.214151 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 23:42:24.214246 tlcl_extend: response is 0
462 23:42:24.214347 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 23:42:24.214442 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
464 23:42:24.214532 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 23:42:24.214618
466 23:42:24.214704
467 23:42:24.214792 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 23:42:24.214879 ARM64: Exception handlers installed.
469 23:42:24.214972 ARM64: Testing exception
470 23:42:24.215060 ARM64: Done test exception
471 23:42:24.215146 pmic_efuse_setting: Set efuses in 11 msecs
472 23:42:24.215232 pmwrap_interface_init: Select PMIF_VLD_RDY
473 23:42:24.215318 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 23:42:24.215405 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 23:42:24.215686 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 23:42:24.215778 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 23:42:24.215865 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 23:42:24.215957 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 23:42:24.216047 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 23:42:24.216134 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 23:42:24.216220 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 23:42:24.216306 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 23:42:24.216392 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 23:42:24.216478 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 23:42:24.216564 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 23:42:24.216650 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 23:42:24.216737 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 23:42:24.216824 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 23:42:24.216914 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 23:42:24.217010 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 23:42:24.217109 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 23:42:24.217198 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 23:42:24.217293 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 23:42:24.217355 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 23:42:24.217413 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 23:42:24.217470 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 23:42:24.217527 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 23:42:24.217584 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 23:42:24.217641 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 23:42:24.217696 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 23:42:24.217751 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 23:42:24.217815 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 23:42:24.217876 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 23:42:24.217936 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 23:42:24.217992 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 23:42:24.218047 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 23:42:24.218102 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 23:42:24.218157 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 23:42:24.218213 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 23:42:24.218268 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 23:42:24.218324 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 23:42:24.218379 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 23:42:24.218435 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 23:42:24.218492 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 23:42:24.218547 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 23:42:24.218601 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 23:42:24.218656 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 23:42:24.218711 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 23:42:24.218766 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 23:42:24.218821 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 23:42:24.218876 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 23:42:24.218931 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 23:42:24.219018 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 23:42:24.219108 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 23:42:24.219196 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 23:42:24.219283 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 23:42:24.219370 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 23:42:24.219458 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 23:42:24.219544 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 23:42:24.219631 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 23:42:24.219717 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:42:24.219803 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
533 23:42:24.219889 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 23:42:24.219981 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
535 23:42:24.220069 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 23:42:24.220155 [RTC]rtc_get_frequency_meter,154: input=15, output=854
537 23:42:24.220241 [RTC]rtc_get_frequency_meter,154: input=7, output=726
538 23:42:24.220318 [RTC]rtc_get_frequency_meter,154: input=11, output=790
539 23:42:24.220376 [RTC]rtc_get_frequency_meter,154: input=13, output=821
540 23:42:24.220432 [RTC]rtc_get_frequency_meter,154: input=12, output=805
541 23:42:24.220488 [RTC]rtc_get_frequency_meter,154: input=11, output=790
542 23:42:24.220543 [RTC]rtc_get_frequency_meter,154: input=12, output=806
543 23:42:24.220599 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
544 23:42:24.220654 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
545 23:42:24.220898 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 23:42:24.220959 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
547 23:42:24.221016 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 23:42:24.221072 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
549 23:42:24.221166 ADC[4]: Raw value=903325 ID=7
550 23:42:24.221255 ADC[3]: Raw value=213916 ID=1
551 23:42:24.221340 RAM Code: 0x71
552 23:42:24.221398 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 23:42:24.221455 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 23:42:24.221512 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 23:42:24.221569 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 23:42:24.221625 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 23:42:24.221681 in-header: 03 07 00 00 08 00 00 00
558 23:42:24.221735 in-data: aa e4 47 04 13 02 00 00
559 23:42:24.221790 Chrome EC: UHEPI supported
560 23:42:24.221846 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 23:42:24.221902 in-header: 03 a9 00 00 08 00 00 00
562 23:42:24.221957 in-data: 84 60 60 08 00 00 00 00
563 23:42:24.222012 MRC: failed to locate region type 0.
564 23:42:24.222068 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 23:42:24.222125 DRAM-K: Running full calibration
566 23:42:24.222180 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 23:42:24.222235 header.status = 0x0
568 23:42:24.222290 header.version = 0x6 (expected: 0x6)
569 23:42:24.222345 header.size = 0xd00 (expected: 0xd00)
570 23:42:24.222400 header.flags = 0x0
571 23:42:24.222455 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 23:42:24.222511 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
573 23:42:24.222566 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 23:42:24.222622 dram_init: ddr_geometry: 2
575 23:42:24.222676 [EMI] MDL number = 2
576 23:42:24.222731 [EMI] Get MDL freq = 0
577 23:42:24.222786 dram_init: ddr_type: 0
578 23:42:24.222840 is_discrete_lpddr4: 1
579 23:42:24.222895 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 23:42:24.222949
581 23:42:24.223004
582 23:42:24.223058 [Bian_co] ETT version 0.0.0.1
583 23:42:24.223113 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 23:42:24.223168
585 23:42:24.223222 dramc_set_vcore_voltage set vcore to 650000
586 23:42:24.223277 Read voltage for 800, 4
587 23:42:24.223331 Vio18 = 0
588 23:42:24.223386 Vcore = 650000
589 23:42:24.223440 Vdram = 0
590 23:42:24.223494 Vddq = 0
591 23:42:24.223549 Vmddr = 0
592 23:42:24.223603 dram_init: config_dvfs: 1
593 23:42:24.223658 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 23:42:24.223713 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 23:42:24.223769 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 23:42:24.223824 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 23:42:24.223879 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 23:42:24.223933 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 23:42:24.224001 MEM_TYPE=3, freq_sel=18
600 23:42:24.224089 sv_algorithm_assistance_LP4_1600
601 23:42:24.224183 ============ PULL DRAM RESETB DOWN ============
602 23:42:24.224252 ========== PULL DRAM RESETB DOWN end =========
603 23:42:24.224309 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 23:42:24.224365 ===================================
605 23:42:24.224421 LPDDR4 DRAM CONFIGURATION
606 23:42:24.224476 ===================================
607 23:42:24.224531 EX_ROW_EN[0] = 0x0
608 23:42:24.224586 EX_ROW_EN[1] = 0x0
609 23:42:24.224641 LP4Y_EN = 0x0
610 23:42:24.224695 WORK_FSP = 0x0
611 23:42:24.224750 WL = 0x2
612 23:42:24.224804 RL = 0x2
613 23:42:24.224859 BL = 0x2
614 23:42:24.224913 RPST = 0x0
615 23:42:24.224967 RD_PRE = 0x0
616 23:42:24.225022 WR_PRE = 0x1
617 23:42:24.225076 WR_PST = 0x0
618 23:42:24.225130 DBI_WR = 0x0
619 23:42:24.225184 DBI_RD = 0x0
620 23:42:24.225239 OTF = 0x1
621 23:42:24.225303 ===================================
622 23:42:24.225359 ===================================
623 23:42:24.225414 ANA top config
624 23:42:24.225468 ===================================
625 23:42:24.225523 DLL_ASYNC_EN = 0
626 23:42:24.225577 ALL_SLAVE_EN = 1
627 23:42:24.225632 NEW_RANK_MODE = 1
628 23:42:24.225687 DLL_IDLE_MODE = 1
629 23:42:24.225742 LP45_APHY_COMB_EN = 1
630 23:42:24.225796 TX_ODT_DIS = 1
631 23:42:24.225851 NEW_8X_MODE = 1
632 23:42:24.225907 ===================================
633 23:42:24.225961 ===================================
634 23:42:24.226016 data_rate = 1600
635 23:42:24.226071 CKR = 1
636 23:42:24.226125 DQ_P2S_RATIO = 8
637 23:42:24.226180 ===================================
638 23:42:24.226236 CA_P2S_RATIO = 8
639 23:42:24.226290 DQ_CA_OPEN = 0
640 23:42:24.226344 DQ_SEMI_OPEN = 0
641 23:42:24.226399 CA_SEMI_OPEN = 0
642 23:42:24.226453 CA_FULL_RATE = 0
643 23:42:24.226508 DQ_CKDIV4_EN = 1
644 23:42:24.226562 CA_CKDIV4_EN = 1
645 23:42:24.226616 CA_PREDIV_EN = 0
646 23:42:24.226670 PH8_DLY = 0
647 23:42:24.226724 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 23:42:24.226778 DQ_AAMCK_DIV = 4
649 23:42:24.226832 CA_AAMCK_DIV = 4
650 23:42:24.226887 CA_ADMCK_DIV = 4
651 23:42:24.226941 DQ_TRACK_CA_EN = 0
652 23:42:24.226995 CA_PICK = 800
653 23:42:24.227050 CA_MCKIO = 800
654 23:42:24.227105 MCKIO_SEMI = 0
655 23:42:24.227159 PLL_FREQ = 3068
656 23:42:24.227214 DQ_UI_PI_RATIO = 32
657 23:42:24.227268 CA_UI_PI_RATIO = 0
658 23:42:24.227323 ===================================
659 23:42:24.227378 ===================================
660 23:42:24.227433 memory_type:LPDDR4
661 23:42:24.227512 GP_NUM : 10
662 23:42:24.227605 SRAM_EN : 1
663 23:42:24.227695 MD32_EN : 0
664 23:42:24.227999 ===================================
665 23:42:24.228066 [ANA_INIT] >>>>>>>>>>>>>>
666 23:42:24.228125 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 23:42:24.228185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 23:42:24.228242 ===================================
669 23:42:24.228299 data_rate = 1600,PCW = 0X7600
670 23:42:24.228356 ===================================
671 23:42:24.228412 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 23:42:24.228467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 23:42:24.228524 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:42:24.228580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 23:42:24.228635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 23:42:24.228690 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:42:24.228745 [ANA_INIT] flow start
678 23:42:24.228800 [ANA_INIT] PLL >>>>>>>>
679 23:42:24.228855 [ANA_INIT] PLL <<<<<<<<
680 23:42:24.228910 [ANA_INIT] MIDPI >>>>>>>>
681 23:42:24.228965 [ANA_INIT] MIDPI <<<<<<<<
682 23:42:24.229020 [ANA_INIT] DLL >>>>>>>>
683 23:42:24.229074 [ANA_INIT] flow end
684 23:42:24.229129 ============ LP4 DIFF to SE enter ============
685 23:42:24.229185 ============ LP4 DIFF to SE exit ============
686 23:42:24.229240 [ANA_INIT] <<<<<<<<<<<<<
687 23:42:24.229306 [Flow] Enable top DCM control >>>>>
688 23:42:24.229361 [Flow] Enable top DCM control <<<<<
689 23:42:24.229416 Enable DLL master slave shuffle
690 23:42:24.229471 ==============================================================
691 23:42:24.229527 Gating Mode config
692 23:42:24.229582 ==============================================================
693 23:42:24.229637 Config description:
694 23:42:24.229692 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 23:42:24.229749 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 23:42:24.229804 SELPH_MODE 0: By rank 1: By Phase
697 23:42:24.229860 ==============================================================
698 23:42:24.229915 GAT_TRACK_EN = 1
699 23:42:24.229970 RX_GATING_MODE = 2
700 23:42:24.230025 RX_GATING_TRACK_MODE = 2
701 23:42:24.230080 SELPH_MODE = 1
702 23:42:24.230135 PICG_EARLY_EN = 1
703 23:42:24.230190 VALID_LAT_VALUE = 1
704 23:42:24.230245 ==============================================================
705 23:42:24.230300 Enter into Gating configuration >>>>
706 23:42:24.230355 Exit from Gating configuration <<<<
707 23:42:24.230410 Enter into DVFS_PRE_config >>>>>
708 23:42:24.230465 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 23:42:24.230525 Exit from DVFS_PRE_config <<<<<
710 23:42:24.230581 Enter into PICG configuration >>>>
711 23:42:24.230635 Exit from PICG configuration <<<<
712 23:42:24.230690 [RX_INPUT] configuration >>>>>
713 23:42:24.230745 [RX_INPUT] configuration <<<<<
714 23:42:24.230811 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 23:42:24.230904 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 23:42:24.230999 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 23:42:24.231093 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 23:42:24.231163 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 23:42:24.231221 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 23:42:24.231278 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 23:42:24.231334 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 23:42:24.231390 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 23:42:24.231446 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 23:42:24.231502 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 23:42:24.231557 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 23:42:24.231612 ===================================
727 23:42:24.231668 LPDDR4 DRAM CONFIGURATION
728 23:42:24.231723 ===================================
729 23:42:24.231778 EX_ROW_EN[0] = 0x0
730 23:42:24.231834 EX_ROW_EN[1] = 0x0
731 23:42:24.231888 LP4Y_EN = 0x0
732 23:42:24.231943 WORK_FSP = 0x0
733 23:42:24.231998 WL = 0x2
734 23:42:24.232052 RL = 0x2
735 23:42:24.232107 BL = 0x2
736 23:42:24.232160 RPST = 0x0
737 23:42:24.232214 RD_PRE = 0x0
738 23:42:24.232268 WR_PRE = 0x1
739 23:42:24.232323 WR_PST = 0x0
740 23:42:24.232377 DBI_WR = 0x0
741 23:42:24.232431 DBI_RD = 0x0
742 23:42:24.232485 OTF = 0x1
743 23:42:24.232540 ===================================
744 23:42:24.232595 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 23:42:24.232650 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 23:42:24.232705 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 23:42:24.232760 ===================================
748 23:42:24.232815 LPDDR4 DRAM CONFIGURATION
749 23:42:24.232869 ===================================
750 23:42:24.232924 EX_ROW_EN[0] = 0x10
751 23:42:24.232979 EX_ROW_EN[1] = 0x0
752 23:42:24.233033 LP4Y_EN = 0x0
753 23:42:24.233087 WORK_FSP = 0x0
754 23:42:24.233141 WL = 0x2
755 23:42:24.233196 RL = 0x2
756 23:42:24.233250 BL = 0x2
757 23:42:24.233313 RPST = 0x0
758 23:42:24.233367 RD_PRE = 0x0
759 23:42:24.233422 WR_PRE = 0x1
760 23:42:24.233477 WR_PST = 0x0
761 23:42:24.233530 DBI_WR = 0x0
762 23:42:24.233585 DBI_RD = 0x0
763 23:42:24.233639 OTF = 0x1
764 23:42:24.233694 ===================================
765 23:42:24.233749 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 23:42:24.233804 nWR fixed to 40
767 23:42:24.233860 [ModeRegInit_LP4] CH0 RK0
768 23:42:24.233914 [ModeRegInit_LP4] CH0 RK1
769 23:42:24.233968 [ModeRegInit_LP4] CH1 RK0
770 23:42:24.234023 [ModeRegInit_LP4] CH1 RK1
771 23:42:24.234077 match AC timing 13
772 23:42:24.234131 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 23:42:24.234386 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 23:42:24.234449 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 23:42:24.234518 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 23:42:24.234576 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 23:42:24.234632 [EMI DOE] emi_dcm 0
778 23:42:24.234687 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 23:42:24.234743 ==
780 23:42:24.234799 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:42:24.234855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:42:24.234911 ==
783 23:42:24.234966 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 23:42:24.235022 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 23:42:24.235078 [CA 0] Center 38 (7~69) winsize 63
786 23:42:24.235134 [CA 1] Center 37 (6~68) winsize 63
787 23:42:24.235189 [CA 2] Center 34 (4~65) winsize 62
788 23:42:24.235246 [CA 3] Center 34 (4~65) winsize 62
789 23:42:24.235305 [CA 4] Center 33 (3~64) winsize 62
790 23:42:24.235364 [CA 5] Center 33 (3~64) winsize 62
791 23:42:24.235422
792 23:42:24.235489 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 23:42:24.235558
794 23:42:24.235644 [CATrainingPosCal] consider 1 rank data
795 23:42:24.235732 u2DelayCellTimex100 = 270/100 ps
796 23:42:24.235818 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
797 23:42:24.235905 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
798 23:42:24.235991 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 23:42:24.236077 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
800 23:42:24.236168 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
801 23:42:24.236254 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 23:42:24.236325
803 23:42:24.236381 CA PerBit enable=1, Macro0, CA PI delay=33
804 23:42:24.236436
805 23:42:24.236494 [CBTSetCACLKResult] CA Dly = 33
806 23:42:24.236550 CS Dly: 5 (0~36)
807 23:42:24.236605 ==
808 23:42:24.236659 Dram Type= 6, Freq= 0, CH_0, rank 1
809 23:42:24.236718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 23:42:24.236773 ==
811 23:42:24.236828 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 23:42:24.236884 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 23:42:24.236939 [CA 0] Center 38 (7~69) winsize 63
814 23:42:24.236995 [CA 1] Center 37 (7~68) winsize 62
815 23:42:24.237050 [CA 2] Center 35 (5~66) winsize 62
816 23:42:24.237105 [CA 3] Center 35 (4~66) winsize 63
817 23:42:24.237159 [CA 4] Center 34 (3~65) winsize 63
818 23:42:24.237213 [CA 5] Center 33 (3~64) winsize 62
819 23:42:24.237281
820 23:42:24.237338 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 23:42:24.237393
822 23:42:24.237447 [CATrainingPosCal] consider 2 rank data
823 23:42:24.237502 u2DelayCellTimex100 = 270/100 ps
824 23:42:24.237557 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
825 23:42:24.237611 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 23:42:24.237666 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
827 23:42:24.237721 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 23:42:24.237776 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 23:42:24.237830 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 23:42:24.237885
831 23:42:24.237940 CA PerBit enable=1, Macro0, CA PI delay=33
832 23:42:24.237995
833 23:42:24.238049 [CBTSetCACLKResult] CA Dly = 33
834 23:42:24.238104 CS Dly: 6 (0~38)
835 23:42:24.238158
836 23:42:24.238213 ----->DramcWriteLeveling(PI) begin...
837 23:42:24.238272 ==
838 23:42:24.238327 Dram Type= 6, Freq= 0, CH_0, rank 0
839 23:42:24.238382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 23:42:24.238438 ==
841 23:42:24.238493 Write leveling (Byte 0): 30 => 30
842 23:42:24.238547 Write leveling (Byte 1): 27 => 27
843 23:42:24.238602 DramcWriteLeveling(PI) end<-----
844 23:42:24.238657
845 23:42:24.238711 ==
846 23:42:24.238766 Dram Type= 6, Freq= 0, CH_0, rank 0
847 23:42:24.238821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 23:42:24.238877 ==
849 23:42:24.238931 [Gating] SW mode calibration
850 23:42:24.238986 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 23:42:24.239042 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 23:42:24.239098 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 23:42:24.239153 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 23:42:24.239208 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 23:42:24.239263 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:42:24.239318 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:42:24.239372 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:42:24.239428 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:42:24.239483 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:42:24.239538 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:42:24.239593 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:42:24.239648 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:42:24.239703 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:42:24.239758 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:42:24.239812 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:42:24.239867 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:42:24.239922 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:42:24.239976 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
869 23:42:24.240031 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 23:42:24.240086 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
871 23:42:24.240141 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
872 23:42:24.240196 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:42:24.240250 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:42:24.240306 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:42:24.240360 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:42:24.240414 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:42:24.240485 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:42:24.240581 0 9 8 | B1->B0 | 2322 3232 | 1 0 | (0 0) (0 0)
879 23:42:24.240643 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
880 23:42:24.240700 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 23:42:24.240953 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:42:24.241018 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:42:24.241075 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:42:24.241132 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:42:24.241187 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
886 23:42:24.241243 0 10 8 | B1->B0 | 3131 2626 | 0 0 | (0 1) (0 0)
887 23:42:24.241309 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
888 23:42:24.241365 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 23:42:24.241420 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:42:24.241475 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:42:24.241530 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:42:24.241585 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:42:24.241640 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
894 23:42:24.241695 0 11 8 | B1->B0 | 2929 4242 | 0 0 | (0 0) (1 1)
895 23:42:24.241749 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
896 23:42:24.241804 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 23:42:24.241859 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:42:24.241914 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:42:24.241969 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:42:24.242024 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:42:24.242079 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 23:42:24.242134 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
903 23:42:24.242189 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 23:42:24.242244 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:42:24.242298 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:42:24.242353 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:42:24.242407 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:42:24.242462 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:42:24.242517 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:42:24.242572 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:42:24.242627 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:42:24.242685 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:42:24.242741 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:42:24.242796 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:42:24.242851 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:42:24.242905 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
917 23:42:24.242960 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 23:42:24.243015 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 23:42:24.243070 Total UI for P1: 0, mck2ui 16
920 23:42:24.243125 best dqsien dly found for B0: ( 0, 14, 2)
921 23:42:24.243180 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
922 23:42:24.243235 Total UI for P1: 0, mck2ui 16
923 23:42:24.243290 best dqsien dly found for B1: ( 0, 14, 8)
924 23:42:24.243345 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
925 23:42:24.243400 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
926 23:42:24.243455
927 23:42:24.243510 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
928 23:42:24.243564 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 23:42:24.243618 [Gating] SW calibration Done
930 23:42:24.243673 ==
931 23:42:24.243728 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:42:24.243782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 23:42:24.243838 ==
934 23:42:24.243893 RX Vref Scan: 0
935 23:42:24.243947
936 23:42:24.244001 RX Vref 0 -> 0, step: 1
937 23:42:24.244056
938 23:42:24.244110 RX Delay -130 -> 252, step: 16
939 23:42:24.244165 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
940 23:42:24.244220 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
941 23:42:24.244275 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
942 23:42:24.244330 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
943 23:42:24.244384 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
944 23:42:24.244439 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
945 23:42:24.244493 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
946 23:42:24.244548 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
947 23:42:24.244603 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
948 23:42:24.244658 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
949 23:42:24.244712 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
950 23:42:24.244767 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
951 23:42:24.244822 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
952 23:42:24.244877 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
953 23:42:24.244931 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
954 23:42:24.244985 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
955 23:42:24.245040 ==
956 23:42:24.245094 Dram Type= 6, Freq= 0, CH_0, rank 0
957 23:42:24.245149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 23:42:24.245204 ==
959 23:42:24.245265 DQS Delay:
960 23:42:24.245322 DQS0 = 0, DQS1 = 0
961 23:42:24.245376 DQM Delay:
962 23:42:24.245431 DQM0 = 91, DQM1 = 75
963 23:42:24.245485 DQ Delay:
964 23:42:24.245540 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
965 23:42:24.245594 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
966 23:42:24.245649 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
967 23:42:24.245704 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
968 23:42:24.245758
969 23:42:24.245812
970 23:42:24.245866 ==
971 23:42:24.245921 Dram Type= 6, Freq= 0, CH_0, rank 0
972 23:42:24.245976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 23:42:24.246031 ==
974 23:42:24.246086
975 23:42:24.246140
976 23:42:24.246194 TX Vref Scan disable
977 23:42:24.246249 == TX Byte 0 ==
978 23:42:24.246303 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
979 23:42:24.246360 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
980 23:42:24.246415 == TX Byte 1 ==
981 23:42:24.246469 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
982 23:42:24.246524 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
983 23:42:24.246579 ==
984 23:42:24.246633 Dram Type= 6, Freq= 0, CH_0, rank 0
985 23:42:24.246689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 23:42:24.246743 ==
987 23:42:24.246798 TX Vref=22, minBit 5, minWin=26, winSum=438
988 23:42:24.246853 TX Vref=24, minBit 2, minWin=27, winSum=443
989 23:42:24.247101 TX Vref=26, minBit 3, minWin=27, winSum=443
990 23:42:24.247162 TX Vref=28, minBit 1, minWin=27, winSum=452
991 23:42:24.247219 TX Vref=30, minBit 1, minWin=27, winSum=451
992 23:42:24.247274 TX Vref=32, minBit 1, minWin=27, winSum=449
993 23:42:24.247330 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 28
994 23:42:24.247386
995 23:42:24.247442 Final TX Range 1 Vref 28
996 23:42:24.247496
997 23:42:24.247551 ==
998 23:42:24.247606 Dram Type= 6, Freq= 0, CH_0, rank 0
999 23:42:24.247661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 23:42:24.247717 ==
1001 23:42:24.247772
1002 23:42:24.247826
1003 23:42:24.247881 TX Vref Scan disable
1004 23:42:24.247936 == TX Byte 0 ==
1005 23:42:24.247990 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1006 23:42:24.248045 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1007 23:42:24.248100 == TX Byte 1 ==
1008 23:42:24.248155 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1009 23:42:24.248210 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1010 23:42:24.248265
1011 23:42:24.248320 [DATLAT]
1012 23:42:24.248376 Freq=800, CH0 RK0
1013 23:42:24.248431
1014 23:42:24.248485 DATLAT Default: 0xa
1015 23:42:24.248540 0, 0xFFFF, sum = 0
1016 23:42:24.248596 1, 0xFFFF, sum = 0
1017 23:42:24.248651 2, 0xFFFF, sum = 0
1018 23:42:24.248706 3, 0xFFFF, sum = 0
1019 23:42:24.248762 4, 0xFFFF, sum = 0
1020 23:42:24.248817 5, 0xFFFF, sum = 0
1021 23:42:24.248872 6, 0xFFFF, sum = 0
1022 23:42:24.248928 7, 0xFFFF, sum = 0
1023 23:42:24.248983 8, 0xFFFF, sum = 0
1024 23:42:24.249038 9, 0x0, sum = 1
1025 23:42:24.249098 10, 0x0, sum = 2
1026 23:42:24.249159 11, 0x0, sum = 3
1027 23:42:24.249214 12, 0x0, sum = 4
1028 23:42:24.249278 best_step = 10
1029 23:42:24.249334
1030 23:42:24.249388 ==
1031 23:42:24.249441 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 23:42:24.249498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 23:42:24.249553 ==
1034 23:42:24.249607 RX Vref Scan: 1
1035 23:42:24.249661
1036 23:42:24.249714 Set Vref Range= 32 -> 127
1037 23:42:24.249768
1038 23:42:24.249822 RX Vref 32 -> 127, step: 1
1039 23:42:24.249875
1040 23:42:24.249929 RX Delay -111 -> 252, step: 8
1041 23:42:24.249982
1042 23:42:24.250036 Set Vref, RX VrefLevel [Byte0]: 32
1043 23:42:24.250090 [Byte1]: 32
1044 23:42:24.250144
1045 23:42:24.250197 Set Vref, RX VrefLevel [Byte0]: 33
1046 23:42:24.250250 [Byte1]: 33
1047 23:42:24.250303
1048 23:42:24.250357 Set Vref, RX VrefLevel [Byte0]: 34
1049 23:42:24.250411 [Byte1]: 34
1050 23:42:24.250464
1051 23:42:24.250518 Set Vref, RX VrefLevel [Byte0]: 35
1052 23:42:24.250571 [Byte1]: 35
1053 23:42:24.250625
1054 23:42:24.250678 Set Vref, RX VrefLevel [Byte0]: 36
1055 23:42:24.250735 [Byte1]: 36
1056 23:42:24.250790
1057 23:42:24.250843 Set Vref, RX VrefLevel [Byte0]: 37
1058 23:42:24.250897 [Byte1]: 37
1059 23:42:24.250953
1060 23:42:24.251006 Set Vref, RX VrefLevel [Byte0]: 38
1061 23:42:24.251061 [Byte1]: 38
1062 23:42:24.251120
1063 23:42:24.251174 Set Vref, RX VrefLevel [Byte0]: 39
1064 23:42:24.251228 [Byte1]: 39
1065 23:42:24.251282
1066 23:42:24.251340 Set Vref, RX VrefLevel [Byte0]: 40
1067 23:42:24.251393 [Byte1]: 40
1068 23:42:24.251447
1069 23:42:24.251502 Set Vref, RX VrefLevel [Byte0]: 41
1070 23:42:24.251557 [Byte1]: 41
1071 23:42:24.251610
1072 23:42:24.251664 Set Vref, RX VrefLevel [Byte0]: 42
1073 23:42:24.251730 [Byte1]: 42
1074 23:42:24.251785
1075 23:42:24.251839 Set Vref, RX VrefLevel [Byte0]: 43
1076 23:42:24.251899 [Byte1]: 43
1077 23:42:24.251982
1078 23:42:24.252067 Set Vref, RX VrefLevel [Byte0]: 44
1079 23:42:24.252152 [Byte1]: 44
1080 23:42:24.252234
1081 23:42:24.252319 Set Vref, RX VrefLevel [Byte0]: 45
1082 23:42:24.252403 [Byte1]: 45
1083 23:42:24.252485
1084 23:42:24.252569 Set Vref, RX VrefLevel [Byte0]: 46
1085 23:42:24.252652 [Byte1]: 46
1086 23:42:24.252735
1087 23:42:24.252818 Set Vref, RX VrefLevel [Byte0]: 47
1088 23:42:24.252902 [Byte1]: 47
1089 23:42:24.252985
1090 23:42:24.253068 Set Vref, RX VrefLevel [Byte0]: 48
1091 23:42:24.253151 [Byte1]: 48
1092 23:42:24.253234
1093 23:42:24.253308 Set Vref, RX VrefLevel [Byte0]: 49
1094 23:42:24.253363 [Byte1]: 49
1095 23:42:24.253417
1096 23:42:24.253470 Set Vref, RX VrefLevel [Byte0]: 50
1097 23:42:24.253523 [Byte1]: 50
1098 23:42:24.253577
1099 23:42:24.253630 Set Vref, RX VrefLevel [Byte0]: 51
1100 23:42:24.253684 [Byte1]: 51
1101 23:42:24.253737
1102 23:42:24.253791 Set Vref, RX VrefLevel [Byte0]: 52
1103 23:42:24.253845 [Byte1]: 52
1104 23:42:24.253898
1105 23:42:24.253952 Set Vref, RX VrefLevel [Byte0]: 53
1106 23:42:24.254005 [Byte1]: 53
1107 23:42:24.254059
1108 23:42:24.254112 Set Vref, RX VrefLevel [Byte0]: 54
1109 23:42:24.254165 [Byte1]: 54
1110 23:42:24.254219
1111 23:42:24.254272 Set Vref, RX VrefLevel [Byte0]: 55
1112 23:42:24.254325 [Byte1]: 55
1113 23:42:24.254378
1114 23:42:24.254432 Set Vref, RX VrefLevel [Byte0]: 56
1115 23:42:24.254485 [Byte1]: 56
1116 23:42:24.254539
1117 23:42:24.254592 Set Vref, RX VrefLevel [Byte0]: 57
1118 23:42:24.254646 [Byte1]: 57
1119 23:42:24.254699
1120 23:42:24.254752 Set Vref, RX VrefLevel [Byte0]: 58
1121 23:42:24.254805 [Byte1]: 58
1122 23:42:24.254859
1123 23:42:24.254912 Set Vref, RX VrefLevel [Byte0]: 59
1124 23:42:24.254965 [Byte1]: 59
1125 23:42:24.255018
1126 23:42:24.255071 Set Vref, RX VrefLevel [Byte0]: 60
1127 23:42:24.255124 [Byte1]: 60
1128 23:42:24.255177
1129 23:42:24.255229 Set Vref, RX VrefLevel [Byte0]: 61
1130 23:42:24.255282 [Byte1]: 61
1131 23:42:24.255335
1132 23:42:24.255388 Set Vref, RX VrefLevel [Byte0]: 62
1133 23:42:24.255441 [Byte1]: 62
1134 23:42:24.255494
1135 23:42:24.255547 Set Vref, RX VrefLevel [Byte0]: 63
1136 23:42:24.255601 [Byte1]: 63
1137 23:42:24.255656
1138 23:42:24.255710 Set Vref, RX VrefLevel [Byte0]: 64
1139 23:42:24.255763 [Byte1]: 64
1140 23:42:24.255827
1141 23:42:24.255883 Set Vref, RX VrefLevel [Byte0]: 65
1142 23:42:24.255937 [Byte1]: 65
1143 23:42:24.255992
1144 23:42:24.256046 Set Vref, RX VrefLevel [Byte0]: 66
1145 23:42:24.256100 [Byte1]: 66
1146 23:42:24.256153
1147 23:42:24.256213 Set Vref, RX VrefLevel [Byte0]: 67
1148 23:42:24.256267 [Byte1]: 67
1149 23:42:24.256321
1150 23:42:24.256375 Set Vref, RX VrefLevel [Byte0]: 68
1151 23:42:24.256439 [Byte1]: 68
1152 23:42:24.256494
1153 23:42:24.256548 Set Vref, RX VrefLevel [Byte0]: 69
1154 23:42:24.256605 [Byte1]: 69
1155 23:42:24.256659
1156 23:42:24.256712 Set Vref, RX VrefLevel [Byte0]: 70
1157 23:42:24.256961 [Byte1]: 70
1158 23:42:24.257050
1159 23:42:24.257135 Set Vref, RX VrefLevel [Byte0]: 71
1160 23:42:24.257219 [Byte1]: 71
1161 23:42:24.257313
1162 23:42:24.257398 Set Vref, RX VrefLevel [Byte0]: 72
1163 23:42:24.257482 [Byte1]: 72
1164 23:42:24.257565
1165 23:42:24.257649 Set Vref, RX VrefLevel [Byte0]: 73
1166 23:42:24.257733 [Byte1]: 73
1167 23:42:24.257816
1168 23:42:24.257899 Set Vref, RX VrefLevel [Byte0]: 74
1169 23:42:24.257983 [Byte1]: 74
1170 23:42:24.258066
1171 23:42:24.258149 Set Vref, RX VrefLevel [Byte0]: 75
1172 23:42:24.258233 [Byte1]: 75
1173 23:42:24.258316
1174 23:42:24.258399 Set Vref, RX VrefLevel [Byte0]: 76
1175 23:42:24.258483 [Byte1]: 76
1176 23:42:24.258566
1177 23:42:24.258650 Final RX Vref Byte 0 = 56 to rank0
1178 23:42:24.258734 Final RX Vref Byte 1 = 62 to rank0
1179 23:42:24.258818 Final RX Vref Byte 0 = 56 to rank1
1180 23:42:24.258903 Final RX Vref Byte 1 = 62 to rank1==
1181 23:42:24.258992 Dram Type= 6, Freq= 0, CH_0, rank 0
1182 23:42:24.259077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1183 23:42:24.259168 ==
1184 23:42:24.259252 DQS Delay:
1185 23:42:24.259333 DQS0 = 0, DQS1 = 0
1186 23:42:24.259389 DQM Delay:
1187 23:42:24.259444 DQM0 = 88, DQM1 = 76
1188 23:42:24.259499 DQ Delay:
1189 23:42:24.259559 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1190 23:42:24.259614 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1191 23:42:24.259667 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1192 23:42:24.259763 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1193 23:42:24.259848
1194 23:42:24.259938
1195 23:42:24.260024 [DQSOSCAuto] RK0, (LSB)MR18= 0x3731, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
1196 23:42:24.260125 CH0 RK0: MR19=606, MR18=3731
1197 23:42:24.260212 CH0_RK0: MR19=0x606, MR18=0x3731, DQSOSC=395, MR23=63, INC=94, DEC=63
1198 23:42:24.260306
1199 23:42:24.260392 ----->DramcWriteLeveling(PI) begin...
1200 23:42:24.260479 ==
1201 23:42:24.260564 Dram Type= 6, Freq= 0, CH_0, rank 1
1202 23:42:24.260648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1203 23:42:24.260734 ==
1204 23:42:24.260818 Write leveling (Byte 0): 32 => 32
1205 23:42:24.260902 Write leveling (Byte 1): 26 => 26
1206 23:42:24.260985 DramcWriteLeveling(PI) end<-----
1207 23:42:24.261068
1208 23:42:24.261151 ==
1209 23:42:24.261234 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 23:42:24.261309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 23:42:24.261367 ==
1212 23:42:24.261422 [Gating] SW mode calibration
1213 23:42:24.261481 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1214 23:42:24.261541 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1215 23:42:24.261598 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1216 23:42:24.261653 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1217 23:42:24.261708 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1218 23:42:24.261764 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 23:42:24.261826 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 23:42:24.261886 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 23:42:24.261941 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:42:24.261995 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:42:24.262054 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:42:24.262145 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:42:24.262230 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:42:24.262317 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:42:24.262403 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:42:24.262488 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:42:24.262575 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:42:24.262659 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:42:24.262745 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:42:24.262829 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1233 23:42:24.262915 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:42:24.262999 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:42:24.263083 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:42:24.263169 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:42:24.263257 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:42:24.263342 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:42:24.263426 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:42:24.263516 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1241 23:42:24.263603 0 9 8 | B1->B0 | 2323 3333 | 1 1 | (1 1) (1 1)
1242 23:42:24.263688 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1243 23:42:24.263776 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 23:42:24.263867 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 23:42:24.263951 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 23:42:24.264040 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 23:42:24.264124 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 23:42:24.264213 0 10 4 | B1->B0 | 3434 3030 | 1 1 | (1 0) (0 0)
1249 23:42:24.264298 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
1250 23:42:24.264381 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 23:42:24.264438 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 23:42:24.264492 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 23:42:24.264551 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 23:42:24.264608 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 23:42:24.264662 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 23:42:24.264716 0 11 4 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
1257 23:42:24.264792 0 11 8 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
1258 23:42:24.264877 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1259 23:42:24.264966 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 23:42:24.265052 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 23:42:24.265140 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 23:42:24.265225 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 23:42:24.265519 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 23:42:24.265615 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1265 23:42:24.265703 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1266 23:42:24.265790 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 23:42:24.265874 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 23:42:24.265963 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 23:42:24.266048 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 23:42:24.266126 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 23:42:24.266183 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 23:42:24.266238 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 23:42:24.266298 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:42:24.266353 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:42:24.266408 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:42:24.266462 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:42:24.266546 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:42:24.266630 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:42:24.266719 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 23:42:24.266804 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1281 23:42:24.266892 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1282 23:42:24.266977 Total UI for P1: 0, mck2ui 16
1283 23:42:24.267071 best dqsien dly found for B0: ( 0, 14, 4)
1284 23:42:24.267157 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1285 23:42:24.267243 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 23:42:24.267331 Total UI for P1: 0, mck2ui 16
1287 23:42:24.267416 best dqsien dly found for B1: ( 0, 14, 10)
1288 23:42:24.267504 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1289 23:42:24.267589 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1290 23:42:24.267676
1291 23:42:24.267761 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1292 23:42:24.267848 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1293 23:42:24.267932 [Gating] SW calibration Done
1294 23:42:24.268018 ==
1295 23:42:24.268103 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 23:42:24.268187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 23:42:24.268275 ==
1298 23:42:24.268359 RX Vref Scan: 0
1299 23:42:24.268440
1300 23:42:24.268496 RX Vref 0 -> 0, step: 1
1301 23:42:24.268550
1302 23:42:24.268615 RX Delay -130 -> 252, step: 16
1303 23:42:24.268670 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1304 23:42:24.268725 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1305 23:42:24.268779 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1306 23:42:24.268867 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1307 23:42:24.268951 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1308 23:42:24.269041 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1309 23:42:24.269126 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1310 23:42:24.269213 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1311 23:42:24.269319 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1312 23:42:24.269411 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1313 23:42:24.269496 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1314 23:42:24.269584 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1315 23:42:24.269670 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1316 23:42:24.269757 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1317 23:42:24.269843 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1318 23:42:24.269929 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1319 23:42:24.270014 ==
1320 23:42:24.270098 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 23:42:24.270186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 23:42:24.270270 ==
1323 23:42:24.270345 DQS Delay:
1324 23:42:24.270401 DQS0 = 0, DQS1 = 0
1325 23:42:24.270455 DQM Delay:
1326 23:42:24.270509 DQM0 = 86, DQM1 = 77
1327 23:42:24.270570 DQ Delay:
1328 23:42:24.270625 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1329 23:42:24.270679 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1330 23:42:24.270752 DQ8 =69, DQ9 =61, DQ10 =85, DQ11 =69
1331 23:42:24.270837 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1332 23:42:24.270924
1333 23:42:24.271008
1334 23:42:24.271092 ==
1335 23:42:24.271189 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 23:42:24.271277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 23:42:24.271376 ==
1338 23:42:24.271469
1339 23:42:24.271559
1340 23:42:24.271643 TX Vref Scan disable
1341 23:42:24.271730 == TX Byte 0 ==
1342 23:42:24.271815 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1343 23:42:24.271906 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1344 23:42:24.271990 == TX Byte 1 ==
1345 23:42:24.272080 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1346 23:42:24.272166 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1347 23:42:24.272252 ==
1348 23:42:24.272337 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 23:42:24.272424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 23:42:24.272483 ==
1351 23:42:24.272538 TX Vref=22, minBit 1, minWin=27, winSum=439
1352 23:42:24.272592 TX Vref=24, minBit 1, minWin=27, winSum=444
1353 23:42:24.272661 TX Vref=26, minBit 1, minWin=27, winSum=448
1354 23:42:24.272746 TX Vref=28, minBit 2, minWin=27, winSum=451
1355 23:42:24.272834 TX Vref=30, minBit 4, minWin=27, winSum=450
1356 23:42:24.272920 TX Vref=32, minBit 0, minWin=28, winSum=451
1357 23:42:24.273009 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
1358 23:42:24.273093
1359 23:42:24.273176 Final TX Range 1 Vref 32
1360 23:42:24.273270
1361 23:42:24.273327 ==
1362 23:42:24.273387 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 23:42:24.273445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 23:42:24.273500 ==
1365 23:42:24.273553
1366 23:42:24.273621
1367 23:42:24.273704 TX Vref Scan disable
1368 23:42:24.273792 == TX Byte 0 ==
1369 23:42:24.273877 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1370 23:42:24.273961 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1371 23:42:24.274048 == TX Byte 1 ==
1372 23:42:24.274132 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1373 23:42:24.274222 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1374 23:42:24.274305
1375 23:42:24.274392 [DATLAT]
1376 23:42:24.274474 Freq=800, CH0 RK1
1377 23:42:24.274561
1378 23:42:24.274645 DATLAT Default: 0xa
1379 23:42:24.274729 0, 0xFFFF, sum = 0
1380 23:42:24.274816 1, 0xFFFF, sum = 0
1381 23:42:24.274901 2, 0xFFFF, sum = 0
1382 23:42:24.274991 3, 0xFFFF, sum = 0
1383 23:42:24.275076 4, 0xFFFF, sum = 0
1384 23:42:24.275165 5, 0xFFFF, sum = 0
1385 23:42:24.275253 6, 0xFFFF, sum = 0
1386 23:42:24.275343 7, 0xFFFF, sum = 0
1387 23:42:24.275429 8, 0xFFFF, sum = 0
1388 23:42:24.275517 9, 0x0, sum = 1
1389 23:42:24.275603 10, 0x0, sum = 2
1390 23:42:24.275893 11, 0x0, sum = 3
1391 23:42:24.275989 12, 0x0, sum = 4
1392 23:42:24.276075 best_step = 10
1393 23:42:24.276162
1394 23:42:24.276245 ==
1395 23:42:24.276311 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 23:42:24.276366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 23:42:24.276421 ==
1398 23:42:24.276483 RX Vref Scan: 0
1399 23:42:24.276537
1400 23:42:24.276591 RX Vref 0 -> 0, step: 1
1401 23:42:24.276644
1402 23:42:24.276730 RX Delay -95 -> 252, step: 8
1403 23:42:24.276814 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1404 23:42:24.276903 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1405 23:42:24.276987 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1406 23:42:24.277076 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1407 23:42:24.277165 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1408 23:42:24.277267 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1409 23:42:24.277332 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1410 23:42:24.277388 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1411 23:42:24.277442 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1412 23:42:24.277500 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1413 23:42:24.277556 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1414 23:42:24.277610 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1415 23:42:24.277664 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1416 23:42:24.277726 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1417 23:42:24.277781 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1418 23:42:24.277834 iDelay=209, Bit 15, Center 80 (-31 ~ 192) 224
1419 23:42:24.277906 ==
1420 23:42:24.277990 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 23:42:24.278078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 23:42:24.278162 ==
1423 23:42:24.278245 DQS Delay:
1424 23:42:24.278332 DQS0 = 0, DQS1 = 0
1425 23:42:24.278415 DQM Delay:
1426 23:42:24.278504 DQM0 = 86, DQM1 = 76
1427 23:42:24.278587 DQ Delay:
1428 23:42:24.278674 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1429 23:42:24.278758 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1430 23:42:24.278845 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1431 23:42:24.278929 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =80
1432 23:42:24.279012
1433 23:42:24.279098
1434 23:42:24.279182 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d29, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1435 23:42:24.279276 CH0 RK1: MR19=606, MR18=2D29
1436 23:42:24.279361 CH0_RK1: MR19=0x606, MR18=0x2D29, DQSOSC=398, MR23=63, INC=93, DEC=62
1437 23:42:24.279449 [RxdqsGatingPostProcess] freq 800
1438 23:42:24.279534 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 23:42:24.279622 Pre-setting of DQS Precalculation
1440 23:42:24.279707 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 23:42:24.279792 ==
1442 23:42:24.279879 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 23:42:24.279963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 23:42:24.280052 ==
1445 23:42:24.280137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 23:42:24.280227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 23:42:24.280312 [CA 0] Center 37 (6~68) winsize 63
1448 23:42:24.280394 [CA 1] Center 37 (6~68) winsize 63
1449 23:42:24.280450 [CA 2] Center 35 (5~65) winsize 61
1450 23:42:24.280504 [CA 3] Center 34 (4~65) winsize 62
1451 23:42:24.280566 [CA 4] Center 34 (4~65) winsize 62
1452 23:42:24.280623 [CA 5] Center 33 (3~64) winsize 62
1453 23:42:24.280676
1454 23:42:24.280730 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1455 23:42:24.280801
1456 23:42:24.280885 [CATrainingPosCal] consider 1 rank data
1457 23:42:24.280973 u2DelayCellTimex100 = 270/100 ps
1458 23:42:24.281061 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1459 23:42:24.281146 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1460 23:42:24.281233 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1461 23:42:24.281305 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1462 23:42:24.281361 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1463 23:42:24.281422 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1464 23:42:24.281478
1465 23:42:24.281532 CA PerBit enable=1, Macro0, CA PI delay=33
1466 23:42:24.281585
1467 23:42:24.281648 [CBTSetCACLKResult] CA Dly = 33
1468 23:42:24.281702 CS Dly: 4 (0~35)
1469 23:42:24.281755 ==
1470 23:42:24.281814 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 23:42:24.281870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 23:42:24.281924 ==
1473 23:42:24.281977 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 23:42:24.282042 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 23:42:24.282097 [CA 0] Center 36 (6~67) winsize 62
1476 23:42:24.282151 [CA 1] Center 37 (6~68) winsize 63
1477 23:42:24.282224 [CA 2] Center 34 (4~65) winsize 62
1478 23:42:24.282308 [CA 3] Center 33 (3~64) winsize 62
1479 23:42:24.282395 [CA 4] Center 34 (4~65) winsize 62
1480 23:42:24.282478 [CA 5] Center 34 (3~65) winsize 63
1481 23:42:24.282561
1482 23:42:24.282653 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1483 23:42:24.282737
1484 23:42:24.282836 [CATrainingPosCal] consider 2 rank data
1485 23:42:24.282921 u2DelayCellTimex100 = 270/100 ps
1486 23:42:24.283012 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1487 23:42:24.283097 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1488 23:42:24.283195 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1489 23:42:24.283288 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1490 23:42:24.283396 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1491 23:42:24.283482 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1492 23:42:24.283584
1493 23:42:24.283671 CA PerBit enable=1, Macro0, CA PI delay=33
1494 23:42:24.283755
1495 23:42:24.283845 [CBTSetCACLKResult] CA Dly = 33
1496 23:42:24.283929 CS Dly: 5 (0~37)
1497 23:42:24.284027
1498 23:42:24.284112 ----->DramcWriteLeveling(PI) begin...
1499 23:42:24.284213 ==
1500 23:42:24.284298 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 23:42:24.284383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 23:42:24.284441 ==
1503 23:42:24.284494 Write leveling (Byte 0): 25 => 25
1504 23:42:24.284558 Write leveling (Byte 1): 29 => 29
1505 23:42:24.284621 DramcWriteLeveling(PI) end<-----
1506 23:42:24.284675
1507 23:42:24.284728 ==
1508 23:42:24.284826 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 23:42:24.284911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 23:42:24.285013 ==
1511 23:42:24.285099 [Gating] SW mode calibration
1512 23:42:24.285189 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 23:42:24.285290 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 23:42:24.285352 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 23:42:24.285638 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1516 23:42:24.285704 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1517 23:42:24.285790 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 23:42:24.285876 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:42:24.285971 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:42:24.286057 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:42:24.286150 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:42:24.286244 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:42:24.286337 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:42:24.286431 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:42:24.286516 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:42:24.286607 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:42:24.286692 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:42:24.286791 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:42:24.286880 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:42:24.286964 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:42:24.287055 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1532 23:42:24.287140 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:42:24.287239 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:42:24.287325 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:42:24.287415 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:42:24.287500 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:42:24.287591 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:42:24.287682 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:42:24.287770 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1540 23:42:24.287857 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1541 23:42:24.287941 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 23:42:24.288039 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 23:42:24.288124 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 23:42:24.288216 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 23:42:24.288300 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 23:42:24.288398 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 23:42:24.288484 0 10 4 | B1->B0 | 3434 3030 | 0 0 | (0 1) (1 1)
1548 23:42:24.288584 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1549 23:42:24.288670 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 23:42:24.288762 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 23:42:24.288847 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 23:42:24.288945 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 23:42:24.289033 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 23:42:24.289118 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 23:42:24.289211 0 11 4 | B1->B0 | 2828 2f2f | 0 0 | (0 0) (0 0)
1556 23:42:24.289294 0 11 8 | B1->B0 | 3e3e 4444 | 1 0 | (0 0) (0 0)
1557 23:42:24.289355 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 23:42:24.289438 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 23:42:24.289494 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 23:42:24.289548 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 23:42:24.289605 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 23:42:24.289669 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 23:42:24.289723 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1564 23:42:24.289778 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1565 23:42:24.289875 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 23:42:24.289960 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 23:42:24.290059 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 23:42:24.290145 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 23:42:24.290240 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:42:24.290325 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:42:24.290422 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:42:24.290514 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:42:24.290605 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:42:24.290689 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:42:24.290787 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:42:24.290872 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:42:24.290961 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:42:24.291047 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:42:24.291145 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1580 23:42:24.291231 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 23:42:24.291321 Total UI for P1: 0, mck2ui 16
1582 23:42:24.291408 best dqsien dly found for B0: ( 0, 14, 4)
1583 23:42:24.291501 Total UI for P1: 0, mck2ui 16
1584 23:42:24.291592 best dqsien dly found for B1: ( 0, 14, 4)
1585 23:42:24.291678 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1586 23:42:24.291768 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1587 23:42:24.291851
1588 23:42:24.291952 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1589 23:42:24.292039 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1590 23:42:24.292124 [Gating] SW calibration Done
1591 23:42:24.292221 ==
1592 23:42:24.292305 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 23:42:24.292371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 23:42:24.292427 ==
1595 23:42:24.292481 RX Vref Scan: 0
1596 23:42:24.292568
1597 23:42:24.292653 RX Vref 0 -> 0, step: 1
1598 23:42:24.292742
1599 23:42:24.292826 RX Delay -130 -> 252, step: 16
1600 23:42:24.292919 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1601 23:42:24.293010 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1602 23:42:24.293099 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1603 23:42:24.293185 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1604 23:42:24.293274 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1605 23:42:24.293543 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1606 23:42:24.293638 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1607 23:42:24.293739 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1608 23:42:24.293825 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1609 23:42:24.293919 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1610 23:42:24.294004 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1611 23:42:24.294103 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1612 23:42:24.294190 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1613 23:42:24.294283 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1614 23:42:24.294368 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1615 23:42:24.294465 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1616 23:42:24.294554 ==
1617 23:42:24.294642 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 23:42:24.294739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 23:42:24.294825 ==
1620 23:42:24.294915 DQS Delay:
1621 23:42:24.295000 DQS0 = 0, DQS1 = 0
1622 23:42:24.295089 DQM Delay:
1623 23:42:24.295180 DQM0 = 87, DQM1 = 83
1624 23:42:24.295267 DQ Delay:
1625 23:42:24.295354 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =85
1626 23:42:24.295437 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1627 23:42:24.295536 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1628 23:42:24.295622 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1629 23:42:24.295713
1630 23:42:24.295809
1631 23:42:24.295905 ==
1632 23:42:24.295988 Dram Type= 6, Freq= 0, CH_1, rank 0
1633 23:42:24.296071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1634 23:42:24.296166 ==
1635 23:42:24.296248
1636 23:42:24.296321
1637 23:42:24.296375 TX Vref Scan disable
1638 23:42:24.296427 == TX Byte 0 ==
1639 23:42:24.296501 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1640 23:42:24.296558 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1641 23:42:24.296611 == TX Byte 1 ==
1642 23:42:24.296674 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1643 23:42:24.296758 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1644 23:42:24.296840 ==
1645 23:42:24.296937 Dram Type= 6, Freq= 0, CH_1, rank 0
1646 23:42:24.297021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1647 23:42:24.297109 ==
1648 23:42:24.297192 TX Vref=22, minBit 2, minWin=26, winSum=438
1649 23:42:24.297326 TX Vref=24, minBit 0, minWin=27, winSum=444
1650 23:42:24.297384 TX Vref=26, minBit 2, minWin=27, winSum=451
1651 23:42:24.297438 TX Vref=28, minBit 1, minWin=28, winSum=457
1652 23:42:24.297497 TX Vref=30, minBit 6, minWin=27, winSum=453
1653 23:42:24.297557 TX Vref=32, minBit 0, minWin=27, winSum=452
1654 23:42:24.297610 [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 28
1655 23:42:24.297663
1656 23:42:24.297743 Final TX Range 1 Vref 28
1657 23:42:24.297798
1658 23:42:24.297850 ==
1659 23:42:24.297919 Dram Type= 6, Freq= 0, CH_1, rank 0
1660 23:42:24.298003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1661 23:42:24.298097 ==
1662 23:42:24.298182
1663 23:42:24.298268
1664 23:42:24.298351 TX Vref Scan disable
1665 23:42:24.298432 == TX Byte 0 ==
1666 23:42:24.298529 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1667 23:42:24.298614 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1668 23:42:24.298695 == TX Byte 1 ==
1669 23:42:24.298791 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1670 23:42:24.298877 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1671 23:42:24.298965
1672 23:42:24.299053 [DATLAT]
1673 23:42:24.299135 Freq=800, CH1 RK0
1674 23:42:24.299229
1675 23:42:24.299311 DATLAT Default: 0xa
1676 23:42:24.299398 0, 0xFFFF, sum = 0
1677 23:42:24.299482 1, 0xFFFF, sum = 0
1678 23:42:24.299578 2, 0xFFFF, sum = 0
1679 23:42:24.299665 3, 0xFFFF, sum = 0
1680 23:42:24.299752 4, 0xFFFF, sum = 0
1681 23:42:24.299838 5, 0xFFFF, sum = 0
1682 23:42:24.299923 6, 0xFFFF, sum = 0
1683 23:42:24.300021 7, 0xFFFF, sum = 0
1684 23:42:24.300106 8, 0xFFFF, sum = 0
1685 23:42:24.300189 9, 0x0, sum = 1
1686 23:42:24.300287 10, 0x0, sum = 2
1687 23:42:24.300371 11, 0x0, sum = 3
1688 23:42:24.300447 12, 0x0, sum = 4
1689 23:42:24.300527 best_step = 10
1690 23:42:24.300581
1691 23:42:24.300634 ==
1692 23:42:24.300721 Dram Type= 6, Freq= 0, CH_1, rank 0
1693 23:42:24.300804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1694 23:42:24.300902 ==
1695 23:42:24.300985 RX Vref Scan: 1
1696 23:42:24.301074
1697 23:42:24.301156 Set Vref Range= 32 -> 127
1698 23:42:24.301249
1699 23:42:24.301358 RX Vref 32 -> 127, step: 1
1700 23:42:24.301411
1701 23:42:24.301464 RX Delay -95 -> 252, step: 8
1702 23:42:24.301529
1703 23:42:24.301581 Set Vref, RX VrefLevel [Byte0]: 32
1704 23:42:24.301634 [Byte1]: 32
1705 23:42:24.301714
1706 23:42:24.301771 Set Vref, RX VrefLevel [Byte0]: 33
1707 23:42:24.301824 [Byte1]: 33
1708 23:42:24.301885
1709 23:42:24.301938 Set Vref, RX VrefLevel [Byte0]: 34
1710 23:42:24.301991 [Byte1]: 34
1711 23:42:24.302043
1712 23:42:24.302138 Set Vref, RX VrefLevel [Byte0]: 35
1713 23:42:24.302221 [Byte1]: 35
1714 23:42:24.302309
1715 23:42:24.302392 Set Vref, RX VrefLevel [Byte0]: 36
1716 23:42:24.302489 [Byte1]: 36
1717 23:42:24.302572
1718 23:42:24.302658 Set Vref, RX VrefLevel [Byte0]: 37
1719 23:42:24.302755 [Byte1]: 37
1720 23:42:24.302838
1721 23:42:24.302924 Set Vref, RX VrefLevel [Byte0]: 38
1722 23:42:24.303007 [Byte1]: 38
1723 23:42:24.303093
1724 23:42:24.303185 Set Vref, RX VrefLevel [Byte0]: 39
1725 23:42:24.303270 [Byte1]: 39
1726 23:42:24.303354
1727 23:42:24.303435 Set Vref, RX VrefLevel [Byte0]: 40
1728 23:42:24.303532 [Byte1]: 40
1729 23:42:24.303615
1730 23:42:24.303704 Set Vref, RX VrefLevel [Byte0]: 41
1731 23:42:24.303787 [Byte1]: 41
1732 23:42:24.303880
1733 23:42:24.303964 Set Vref, RX VrefLevel [Byte0]: 42
1734 23:42:24.304050 [Byte1]: 42
1735 23:42:24.304136
1736 23:42:24.304218 Set Vref, RX VrefLevel [Byte0]: 43
1737 23:42:24.304300 [Byte1]: 43
1738 23:42:24.304380
1739 23:42:24.304433 Set Vref, RX VrefLevel [Byte0]: 44
1740 23:42:24.304486 [Byte1]: 44
1741 23:42:24.304583
1742 23:42:24.304666 Set Vref, RX VrefLevel [Byte0]: 45
1743 23:42:24.304753 [Byte1]: 45
1744 23:42:24.304836
1745 23:42:24.304918 Set Vref, RX VrefLevel [Byte0]: 46
1746 23:42:24.305018 [Byte1]: 46
1747 23:42:24.305100
1748 23:42:24.305187 Set Vref, RX VrefLevel [Byte0]: 47
1749 23:42:24.305306 [Byte1]: 47
1750 23:42:24.305407
1751 23:42:24.305490 Set Vref, RX VrefLevel [Byte0]: 48
1752 23:42:24.305573 [Byte1]: 48
1753 23:42:24.305668
1754 23:42:24.305751 Set Vref, RX VrefLevel [Byte0]: 49
1755 23:42:24.305841 [Byte1]: 49
1756 23:42:24.305922
1757 23:42:24.306016 Set Vref, RX VrefLevel [Byte0]: 50
1758 23:42:24.306101 [Byte1]: 50
1759 23:42:24.306189
1760 23:42:24.306271 Set Vref, RX VrefLevel [Byte0]: 51
1761 23:42:24.306363 [Byte1]: 51
1762 23:42:24.306422
1763 23:42:24.306475 Set Vref, RX VrefLevel [Byte0]: 52
1764 23:42:24.306734 [Byte1]: 52
1765 23:42:24.306828
1766 23:42:24.306948 Set Vref, RX VrefLevel [Byte0]: 53
1767 23:42:24.307060 [Byte1]: 53
1768 23:42:24.307146
1769 23:42:24.307252 Set Vref, RX VrefLevel [Byte0]: 54
1770 23:42:24.307383 [Byte1]: 54
1771 23:42:24.307478
1772 23:42:24.307561 Set Vref, RX VrefLevel [Byte0]: 55
1773 23:42:24.307650 [Byte1]: 55
1774 23:42:24.307732
1775 23:42:24.307831 Set Vref, RX VrefLevel [Byte0]: 56
1776 23:42:24.307915 [Byte1]: 56
1777 23:42:24.308003
1778 23:42:24.308085 Set Vref, RX VrefLevel [Byte0]: 57
1779 23:42:24.308173 [Byte1]: 57
1780 23:42:24.308264
1781 23:42:24.308347 Set Vref, RX VrefLevel [Byte0]: 58
1782 23:42:24.308433 [Byte1]: 58
1783 23:42:24.308490
1784 23:42:24.308543 Set Vref, RX VrefLevel [Byte0]: 59
1785 23:42:24.308600 [Byte1]: 59
1786 23:42:24.308694
1787 23:42:24.308776 Set Vref, RX VrefLevel [Byte0]: 60
1788 23:42:24.308865 [Byte1]: 60
1789 23:42:24.308954
1790 23:42:24.309036 Set Vref, RX VrefLevel [Byte0]: 61
1791 23:42:24.309127 [Byte1]: 61
1792 23:42:24.309208
1793 23:42:24.309335 Set Vref, RX VrefLevel [Byte0]: 62
1794 23:42:24.309407 [Byte1]: 62
1795 23:42:24.309462
1796 23:42:24.309514 Set Vref, RX VrefLevel [Byte0]: 63
1797 23:42:24.309565 [Byte1]: 63
1798 23:42:24.309648
1799 23:42:24.309702 Set Vref, RX VrefLevel [Byte0]: 64
1800 23:42:24.309755 [Byte1]: 64
1801 23:42:24.309836
1802 23:42:24.309918 Set Vref, RX VrefLevel [Byte0]: 65
1803 23:42:24.310013 [Byte1]: 65
1804 23:42:24.310096
1805 23:42:24.310184 Set Vref, RX VrefLevel [Byte0]: 66
1806 23:42:24.310267 [Byte1]: 66
1807 23:42:24.310354
1808 23:42:24.310445 Set Vref, RX VrefLevel [Byte0]: 67
1809 23:42:24.310527 [Byte1]: 67
1810 23:42:24.310615
1811 23:42:24.310697 Set Vref, RX VrefLevel [Byte0]: 68
1812 23:42:24.310793 [Byte1]: 68
1813 23:42:24.310878
1814 23:42:24.310959 Set Vref, RX VrefLevel [Byte0]: 69
1815 23:42:24.311052 [Byte1]: 69
1816 23:42:24.311136
1817 23:42:24.311222 Set Vref, RX VrefLevel [Byte0]: 70
1818 23:42:24.311311 [Byte1]: 70
1819 23:42:24.311392
1820 23:42:24.311485 Set Vref, RX VrefLevel [Byte0]: 71
1821 23:42:24.311569 [Byte1]: 71
1822 23:42:24.311654
1823 23:42:24.311737 Final RX Vref Byte 0 = 56 to rank0
1824 23:42:24.311819 Final RX Vref Byte 1 = 58 to rank0
1825 23:42:24.311917 Final RX Vref Byte 0 = 56 to rank1
1826 23:42:24.312001 Final RX Vref Byte 1 = 58 to rank1==
1827 23:42:24.312089 Dram Type= 6, Freq= 0, CH_1, rank 0
1828 23:42:24.312172 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1829 23:42:24.312267 ==
1830 23:42:24.312328 DQS Delay:
1831 23:42:24.312380 DQS0 = 0, DQS1 = 0
1832 23:42:24.312432 DQM Delay:
1833 23:42:24.312493 DQM0 = 84, DQM1 = 79
1834 23:42:24.312560 DQ Delay:
1835 23:42:24.312614 DQ0 =88, DQ1 =80, DQ2 =72, DQ3 =84
1836 23:42:24.312667 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1837 23:42:24.312759 DQ8 =68, DQ9 =72, DQ10 =76, DQ11 =72
1838 23:42:24.312841 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =84
1839 23:42:24.312925
1840 23:42:24.313015
1841 23:42:24.313099 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e31, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1842 23:42:24.313191 CH1 RK0: MR19=606, MR18=1E31
1843 23:42:24.313297 CH1_RK0: MR19=0x606, MR18=0x1E31, DQSOSC=397, MR23=63, INC=93, DEC=62
1844 23:42:24.313393
1845 23:42:24.313447 ----->DramcWriteLeveling(PI) begin...
1846 23:42:24.313509 ==
1847 23:42:24.313566 Dram Type= 6, Freq= 0, CH_1, rank 1
1848 23:42:24.313662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1849 23:42:24.313745 ==
1850 23:42:24.313832 Write leveling (Byte 0): 28 => 28
1851 23:42:24.313915 Write leveling (Byte 1): 27 => 27
1852 23:42:24.314010 DramcWriteLeveling(PI) end<-----
1853 23:42:24.314093
1854 23:42:24.314178 ==
1855 23:42:24.314265 Dram Type= 6, Freq= 0, CH_1, rank 1
1856 23:42:24.314349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 23:42:24.314445 ==
1858 23:42:24.314527 [Gating] SW mode calibration
1859 23:42:24.314617 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1860 23:42:24.314701 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1861 23:42:24.314799 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1862 23:42:24.314883 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1863 23:42:24.314971 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1864 23:42:24.315068 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 23:42:24.315156 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 23:42:24.315239 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:42:24.315328 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:42:24.315411 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:42:24.315505 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:42:24.315589 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:42:24.315678 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:42:24.315761 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:42:24.315847 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:42:24.315939 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:42:24.316022 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:42:24.316112 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:42:24.316194 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1878 23:42:24.316286 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1879 23:42:24.316343 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:42:24.316396 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:42:24.316477 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:42:24.316536 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:42:24.316588 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:42:24.316641 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:42:24.316715 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:42:24.316798 0 9 4 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
1887 23:42:24.316886 0 9 8 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
1888 23:42:24.316980 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 23:42:24.317277 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 23:42:24.317383 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 23:42:24.317469 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1892 23:42:24.317561 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 23:42:24.317644 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 23:42:24.317742 0 10 4 | B1->B0 | 3434 2a2a | 0 0 | (0 1) (0 0)
1895 23:42:24.317828 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1896 23:42:24.317910 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:42:24.318008 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:42:24.318092 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 23:42:24.318182 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 23:42:24.318305 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 23:42:24.318396 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 23:42:24.318485 0 11 4 | B1->B0 | 2a2a 4545 | 0 0 | (1 1) (0 0)
1903 23:42:24.318568 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1904 23:42:24.318654 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 23:42:24.318737 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 23:42:24.318826 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 23:42:24.318909 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1908 23:42:24.318995 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 23:42:24.319078 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 23:42:24.319163 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1911 23:42:24.319247 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1912 23:42:24.319329 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 23:42:24.319416 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 23:42:24.319498 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 23:42:24.319568 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 23:42:24.319621 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 23:42:24.319673 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:42:24.319730 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:42:24.319785 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:42:24.319837 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:42:24.319889 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:42:24.319971 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:42:24.320053 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:42:24.320139 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:42:24.320222 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1926 23:42:24.320306 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1927 23:42:24.320392 Total UI for P1: 0, mck2ui 16
1928 23:42:24.320457 best dqsien dly found for B0: ( 0, 14, 0)
1929 23:42:24.320519 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1930 23:42:24.320573 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 23:42:24.320626 Total UI for P1: 0, mck2ui 16
1932 23:42:24.320686 best dqsien dly found for B1: ( 0, 14, 6)
1933 23:42:24.320770 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1934 23:42:24.320852 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1935 23:42:24.320937
1936 23:42:24.321019 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1937 23:42:24.321105 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1938 23:42:24.321187 [Gating] SW calibration Done
1939 23:42:24.321276 ==
1940 23:42:24.321370 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 23:42:24.321423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 23:42:24.321487 ==
1943 23:42:24.321541 RX Vref Scan: 0
1944 23:42:24.321593
1945 23:42:24.321652 RX Vref 0 -> 0, step: 1
1946 23:42:24.321706
1947 23:42:24.321759 RX Delay -130 -> 252, step: 16
1948 23:42:24.321813 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1949 23:42:24.321874 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1950 23:42:24.321927 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1951 23:42:24.321980 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1952 23:42:24.322037 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1953 23:42:24.322122 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1954 23:42:24.322205 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1955 23:42:24.322291 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1956 23:42:24.322373 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1957 23:42:24.322458 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1958 23:42:24.322540 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1959 23:42:24.322629 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1960 23:42:24.322712 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1961 23:42:24.322796 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1962 23:42:24.322880 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1963 23:42:24.322962 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1964 23:42:24.323048 ==
1965 23:42:24.323132 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 23:42:24.323214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 23:42:24.323300 ==
1968 23:42:24.323383 DQS Delay:
1969 23:42:24.323466 DQS0 = 0, DQS1 = 0
1970 23:42:24.323551 DQM Delay:
1971 23:42:24.323632 DQM0 = 84, DQM1 = 84
1972 23:42:24.323717 DQ Delay:
1973 23:42:24.323800 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1974 23:42:24.323882 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1975 23:42:24.323967 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1976 23:42:24.324049 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1977 23:42:24.324170
1978 23:42:24.324251
1979 23:42:24.324321 ==
1980 23:42:24.324375 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 23:42:24.324428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 23:42:24.324489 ==
1983 23:42:24.324543
1984 23:42:24.324620
1985 23:42:24.324701 TX Vref Scan disable
1986 23:42:24.324786 == TX Byte 0 ==
1987 23:42:24.324869 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1988 23:42:24.463421 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1989 23:42:24.463568 == TX Byte 1 ==
1990 23:42:24.463661 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1991 23:42:24.463750 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1992 23:42:24.463841 ==
1993 23:42:24.463928 Dram Type= 6, Freq= 0, CH_1, rank 1
1994 23:42:24.464013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1995 23:42:24.464097 ==
1996 23:42:24.464393 TX Vref=22, minBit 1, minWin=27, winSum=449
1997 23:42:24.464485 TX Vref=24, minBit 5, minWin=27, winSum=451
1998 23:42:24.464570 TX Vref=26, minBit 0, minWin=28, winSum=455
1999 23:42:24.464654 TX Vref=28, minBit 0, minWin=28, winSum=456
2000 23:42:24.464737 TX Vref=30, minBit 0, minWin=28, winSum=454
2001 23:42:24.464821 TX Vref=32, minBit 5, minWin=27, winSum=453
2002 23:42:24.464908 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 28
2003 23:42:24.464995
2004 23:42:24.465080 Final TX Range 1 Vref 28
2005 23:42:24.465175
2006 23:42:24.465288 ==
2007 23:42:24.465424 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 23:42:24.465511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 23:42:24.465603 ==
2010 23:42:24.465686
2011 23:42:24.465767
2012 23:42:24.465849 TX Vref Scan disable
2013 23:42:24.465931 == TX Byte 0 ==
2014 23:42:24.466019 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2015 23:42:24.466106 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2016 23:42:24.466187 == TX Byte 1 ==
2017 23:42:24.466270 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2018 23:42:24.466352 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2019 23:42:24.466433
2020 23:42:24.466513 [DATLAT]
2021 23:42:24.466594 Freq=800, CH1 RK1
2022 23:42:24.466675
2023 23:42:24.466756 DATLAT Default: 0xa
2024 23:42:24.466836 0, 0xFFFF, sum = 0
2025 23:42:24.466920 1, 0xFFFF, sum = 0
2026 23:42:24.467003 2, 0xFFFF, sum = 0
2027 23:42:24.467086 3, 0xFFFF, sum = 0
2028 23:42:24.467169 4, 0xFFFF, sum = 0
2029 23:42:24.467254 5, 0xFFFF, sum = 0
2030 23:42:24.467320 6, 0xFFFF, sum = 0
2031 23:42:24.467375 7, 0xFFFF, sum = 0
2032 23:42:24.467428 8, 0xFFFF, sum = 0
2033 23:42:24.467481 9, 0x0, sum = 1
2034 23:42:24.467534 10, 0x0, sum = 2
2035 23:42:24.467588 11, 0x0, sum = 3
2036 23:42:24.467640 12, 0x0, sum = 4
2037 23:42:24.467693 best_step = 10
2038 23:42:24.467744
2039 23:42:24.467796 ==
2040 23:42:24.467848 Dram Type= 6, Freq= 0, CH_1, rank 1
2041 23:42:24.467900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2042 23:42:24.467953 ==
2043 23:42:24.468005 RX Vref Scan: 0
2044 23:42:24.468057
2045 23:42:24.468109 RX Vref 0 -> 0, step: 1
2046 23:42:24.468160
2047 23:42:24.468212 RX Delay -95 -> 252, step: 8
2048 23:42:24.468264 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2049 23:42:24.468316 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
2050 23:42:24.468368 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2051 23:42:24.468420 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2052 23:42:24.468502 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2053 23:42:24.468593 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2054 23:42:24.468685 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2055 23:42:24.468771 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2056 23:42:24.468847 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2057 23:42:24.468902 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2058 23:42:24.468955 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2059 23:42:24.469008 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2060 23:42:24.469060 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2061 23:42:24.469113 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2062 23:42:24.469165 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2063 23:42:24.469217 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2064 23:42:24.469307 ==
2065 23:42:24.469361 Dram Type= 6, Freq= 0, CH_1, rank 1
2066 23:42:24.469420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2067 23:42:24.469475 ==
2068 23:42:24.469534 DQS Delay:
2069 23:42:24.469591 DQS0 = 0, DQS1 = 0
2070 23:42:24.469644 DQM Delay:
2071 23:42:24.469696 DQM0 = 85, DQM1 = 82
2072 23:42:24.469749 DQ Delay:
2073 23:42:24.469808 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2074 23:42:24.469861 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2075 23:42:24.469914 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
2076 23:42:24.469974 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2077 23:42:24.470058
2078 23:42:24.470139
2079 23:42:24.470225 [DQSOSCAuto] RK1, (LSB)MR18= 0x2541, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2080 23:42:24.470309 CH1 RK1: MR19=606, MR18=2541
2081 23:42:24.470394 CH1_RK1: MR19=0x606, MR18=0x2541, DQSOSC=393, MR23=63, INC=95, DEC=63
2082 23:42:24.470484 [RxdqsGatingPostProcess] freq 800
2083 23:42:24.470568 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2084 23:42:24.470651 Pre-setting of DQS Precalculation
2085 23:42:24.470708 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2086 23:42:24.470762 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2087 23:42:24.470816 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2088 23:42:24.470883
2089 23:42:24.470937
2090 23:42:24.470989 [Calibration Summary] 1600 Mbps
2091 23:42:24.471049 CH 0, Rank 0
2092 23:42:24.471103 SW Impedance : PASS
2093 23:42:24.471155 DUTY Scan : NO K
2094 23:42:24.471210 ZQ Calibration : PASS
2095 23:42:24.471297 Jitter Meter : NO K
2096 23:42:24.471380 CBT Training : PASS
2097 23:42:24.471479 Write leveling : PASS
2098 23:42:24.471571 RX DQS gating : PASS
2099 23:42:24.471667 RX DQ/DQS(RDDQC) : PASS
2100 23:42:24.471753 TX DQ/DQS : PASS
2101 23:42:24.471840 RX DATLAT : PASS
2102 23:42:24.471897 RX DQ/DQS(Engine): PASS
2103 23:42:24.471951 TX OE : NO K
2104 23:42:24.472015 All Pass.
2105 23:42:24.472070
2106 23:42:24.472123 CH 0, Rank 1
2107 23:42:24.472180 SW Impedance : PASS
2108 23:42:24.472235 DUTY Scan : NO K
2109 23:42:24.472288 ZQ Calibration : PASS
2110 23:42:24.472340 Jitter Meter : NO K
2111 23:42:24.472404 CBT Training : PASS
2112 23:42:24.472458 Write leveling : PASS
2113 23:42:24.472510 RX DQS gating : PASS
2114 23:42:24.472568 RX DQ/DQS(RDDQC) : PASS
2115 23:42:24.472622 TX DQ/DQS : PASS
2116 23:42:24.472676 RX DATLAT : PASS
2117 23:42:24.472728 RX DQ/DQS(Engine): PASS
2118 23:42:24.472808 TX OE : NO K
2119 23:42:24.472891 All Pass.
2120 23:42:24.472976
2121 23:42:24.473058 CH 1, Rank 0
2122 23:42:24.473144 SW Impedance : PASS
2123 23:42:24.473252 DUTY Scan : NO K
2124 23:42:24.473359 ZQ Calibration : PASS
2125 23:42:24.473442 Jitter Meter : NO K
2126 23:42:24.473525 CBT Training : PASS
2127 23:42:24.473610 Write leveling : PASS
2128 23:42:24.473691 RX DQS gating : PASS
2129 23:42:24.473777 RX DQ/DQS(RDDQC) : PASS
2130 23:42:24.473859 TX DQ/DQS : PASS
2131 23:42:24.473946 RX DATLAT : PASS
2132 23:42:24.474028 RX DQ/DQS(Engine): PASS
2133 23:42:24.474115 TX OE : NO K
2134 23:42:24.474198 All Pass.
2135 23:42:24.474279
2136 23:42:24.474364 CH 1, Rank 1
2137 23:42:24.474446 SW Impedance : PASS
2138 23:42:24.474533 DUTY Scan : NO K
2139 23:42:24.474616 ZQ Calibration : PASS
2140 23:42:24.474702 Jitter Meter : NO K
2141 23:42:24.474784 CBT Training : PASS
2142 23:42:24.474873 Write leveling : PASS
2143 23:42:24.475009 RX DQS gating : PASS
2144 23:42:24.475103 RX DQ/DQS(RDDQC) : PASS
2145 23:42:24.475189 TX DQ/DQS : PASS
2146 23:42:24.475285 RX DATLAT : PASS
2147 23:42:24.475548 RX DQ/DQS(Engine): PASS
2148 23:42:24.475610 TX OE : NO K
2149 23:42:24.475762 All Pass.
2150 23:42:24.475864
2151 23:42:24.475947 DramC Write-DBI off
2152 23:42:24.476082 PER_BANK_REFRESH: Hybrid Mode
2153 23:42:24.476161 TX_TRACKING: ON
2154 23:42:24.476217 [GetDramInforAfterCalByMRR] Vendor 6.
2155 23:42:24.476271 [GetDramInforAfterCalByMRR] Revision 606.
2156 23:42:24.476347 [GetDramInforAfterCalByMRR] Revision 2 0.
2157 23:42:24.476417 MR0 0x3b3b
2158 23:42:24.476470 MR8 0x5151
2159 23:42:24.476532 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2160 23:42:24.476602
2161 23:42:24.476668 MR0 0x3b3b
2162 23:42:24.476731 MR8 0x5151
2163 23:42:24.476784 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 23:42:24.476837
2165 23:42:24.476896 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2166 23:42:24.476951 [FAST_K] Save calibration result to emmc
2167 23:42:24.477004 [FAST_K] Save calibration result to emmc
2168 23:42:24.477057 dram_init: config_dvfs: 1
2169 23:42:24.477142 dramc_set_vcore_voltage set vcore to 662500
2170 23:42:24.477224 Read voltage for 1200, 2
2171 23:42:24.477335 Vio18 = 0
2172 23:42:24.477390 Vcore = 662500
2173 23:42:24.477442 Vdram = 0
2174 23:42:24.477503 Vddq = 0
2175 23:42:24.477557 Vmddr = 0
2176 23:42:24.477609 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2177 23:42:24.477678 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2178 23:42:24.477761 MEM_TYPE=3, freq_sel=15
2179 23:42:24.477843 sv_algorithm_assistance_LP4_1600
2180 23:42:24.477931 ============ PULL DRAM RESETB DOWN ============
2181 23:42:24.478014 ========== PULL DRAM RESETB DOWN end =========
2182 23:42:24.478078 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2183 23:42:24.478133 ===================================
2184 23:42:24.478186 LPDDR4 DRAM CONFIGURATION
2185 23:42:24.478246 ===================================
2186 23:42:24.478302 EX_ROW_EN[0] = 0x0
2187 23:42:24.478383 EX_ROW_EN[1] = 0x0
2188 23:42:24.478478 LP4Y_EN = 0x0
2189 23:42:24.478571 WORK_FSP = 0x0
2190 23:42:24.478657 WL = 0x4
2191 23:42:24.478736 RL = 0x4
2192 23:42:24.478794 BL = 0x2
2193 23:42:24.478848 RPST = 0x0
2194 23:42:24.478907 RD_PRE = 0x0
2195 23:42:24.478961 WR_PRE = 0x1
2196 23:42:24.479014 WR_PST = 0x0
2197 23:42:24.479067 DBI_WR = 0x0
2198 23:42:24.479119 DBI_RD = 0x0
2199 23:42:24.479171 OTF = 0x1
2200 23:42:24.479224 ===================================
2201 23:42:24.479277 ===================================
2202 23:42:24.479330 ANA top config
2203 23:42:24.479383 ===================================
2204 23:42:24.479446 DLL_ASYNC_EN = 0
2205 23:42:24.479531 ALL_SLAVE_EN = 0
2206 23:42:24.479613 NEW_RANK_MODE = 1
2207 23:42:24.479696 DLL_IDLE_MODE = 1
2208 23:42:24.479777 LP45_APHY_COMB_EN = 1
2209 23:42:24.479859 TX_ODT_DIS = 1
2210 23:42:24.479941 NEW_8X_MODE = 1
2211 23:42:24.480024 ===================================
2212 23:42:24.480107 ===================================
2213 23:42:24.480189 data_rate = 2400
2214 23:42:24.480270 CKR = 1
2215 23:42:24.480352 DQ_P2S_RATIO = 8
2216 23:42:24.480433 ===================================
2217 23:42:24.480515 CA_P2S_RATIO = 8
2218 23:42:24.480597 DQ_CA_OPEN = 0
2219 23:42:24.480681 DQ_SEMI_OPEN = 0
2220 23:42:24.480767 CA_SEMI_OPEN = 0
2221 23:42:24.480881 CA_FULL_RATE = 0
2222 23:42:24.480963 DQ_CKDIV4_EN = 0
2223 23:42:24.481044 CA_CKDIV4_EN = 0
2224 23:42:24.481126 CA_PREDIV_EN = 0
2225 23:42:24.481208 PH8_DLY = 17
2226 23:42:24.481334 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2227 23:42:24.481430 DQ_AAMCK_DIV = 4
2228 23:42:24.481523 CA_AAMCK_DIV = 4
2229 23:42:24.481615 CA_ADMCK_DIV = 4
2230 23:42:24.481705 DQ_TRACK_CA_EN = 0
2231 23:42:24.481799 CA_PICK = 1200
2232 23:42:24.481886 CA_MCKIO = 1200
2233 23:42:24.481970 MCKIO_SEMI = 0
2234 23:42:24.482052 PLL_FREQ = 2366
2235 23:42:24.482134 DQ_UI_PI_RATIO = 32
2236 23:42:24.482216 CA_UI_PI_RATIO = 0
2237 23:42:24.482298 ===================================
2238 23:42:24.482380 ===================================
2239 23:42:24.482463 memory_type:LPDDR4
2240 23:42:24.482545 GP_NUM : 10
2241 23:42:24.482626 SRAM_EN : 1
2242 23:42:24.482708 MD32_EN : 0
2243 23:42:24.482793 ===================================
2244 23:42:24.482885 [ANA_INIT] >>>>>>>>>>>>>>
2245 23:42:24.482977 <<<<<< [CONFIGURE PHASE]: ANA_TX
2246 23:42:24.483063 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2247 23:42:24.483146 ===================================
2248 23:42:24.483229 data_rate = 2400,PCW = 0X5b00
2249 23:42:24.483311 ===================================
2250 23:42:24.483394 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2251 23:42:24.483477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2252 23:42:24.483561 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2253 23:42:24.483644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2254 23:42:24.483757 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2255 23:42:24.483839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2256 23:42:24.483921 [ANA_INIT] flow start
2257 23:42:24.484003 [ANA_INIT] PLL >>>>>>>>
2258 23:42:24.484088 [ANA_INIT] PLL <<<<<<<<
2259 23:42:24.484173 [ANA_INIT] MIDPI >>>>>>>>
2260 23:42:24.484256 [ANA_INIT] MIDPI <<<<<<<<
2261 23:42:24.484338 [ANA_INIT] DLL >>>>>>>>
2262 23:42:24.484419 [ANA_INIT] DLL <<<<<<<<
2263 23:42:24.484500 [ANA_INIT] flow end
2264 23:42:24.484581 ============ LP4 DIFF to SE enter ============
2265 23:42:24.484664 ============ LP4 DIFF to SE exit ============
2266 23:42:24.484769 [ANA_INIT] <<<<<<<<<<<<<
2267 23:42:24.484882 [Flow] Enable top DCM control >>>>>
2268 23:42:24.485032 [Flow] Enable top DCM control <<<<<
2269 23:42:24.485139 Enable DLL master slave shuffle
2270 23:42:24.485254 ==============================================================
2271 23:42:24.485362 Gating Mode config
2272 23:42:24.485446 ==============================================================
2273 23:42:24.485529 Config description:
2274 23:42:24.485613 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2275 23:42:24.485898 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2276 23:42:24.485988 SELPH_MODE 0: By rank 1: By Phase
2277 23:42:24.486072 ==============================================================
2278 23:42:24.486185 GAT_TRACK_EN = 1
2279 23:42:24.486268 RX_GATING_MODE = 2
2280 23:42:24.486349 RX_GATING_TRACK_MODE = 2
2281 23:42:24.486462 SELPH_MODE = 1
2282 23:42:24.486544 PICG_EARLY_EN = 1
2283 23:42:24.486626 VALID_LAT_VALUE = 1
2284 23:42:24.486708 ==============================================================
2285 23:42:24.486791 Enter into Gating configuration >>>>
2286 23:42:24.486872 Exit from Gating configuration <<<<
2287 23:42:24.486954 Enter into DVFS_PRE_config >>>>>
2288 23:42:24.487038 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2289 23:42:24.487121 Exit from DVFS_PRE_config <<<<<
2290 23:42:24.487203 Enter into PICG configuration >>>>
2291 23:42:24.487285 Exit from PICG configuration <<<<
2292 23:42:24.487367 [RX_INPUT] configuration >>>>>
2293 23:42:24.487448 [RX_INPUT] configuration <<<<<
2294 23:42:24.487530 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2295 23:42:24.487613 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2296 23:42:24.487696 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2297 23:42:24.487779 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2298 23:42:24.487862 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2299 23:42:24.487944 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2300 23:42:24.488026 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2301 23:42:24.488108 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2302 23:42:24.488202 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2303 23:42:24.488269 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2304 23:42:24.488360 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2305 23:42:24.488450 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2306 23:42:24.488538 ===================================
2307 23:42:24.488607 LPDDR4 DRAM CONFIGURATION
2308 23:42:24.488662 ===================================
2309 23:42:24.488715 EX_ROW_EN[0] = 0x0
2310 23:42:24.488768 EX_ROW_EN[1] = 0x0
2311 23:42:24.488821 LP4Y_EN = 0x0
2312 23:42:24.488873 WORK_FSP = 0x0
2313 23:42:24.488926 WL = 0x4
2314 23:42:24.488978 RL = 0x4
2315 23:42:24.489031 BL = 0x2
2316 23:42:24.489083 RPST = 0x0
2317 23:42:24.489153 RD_PRE = 0x0
2318 23:42:24.489206 WR_PRE = 0x1
2319 23:42:24.489267 WR_PST = 0x0
2320 23:42:24.489335 DBI_WR = 0x0
2321 23:42:24.489388 DBI_RD = 0x0
2322 23:42:24.489440 OTF = 0x1
2323 23:42:24.489493 ===================================
2324 23:42:24.489546 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2325 23:42:24.489599 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2326 23:42:24.489651 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2327 23:42:24.489704 ===================================
2328 23:42:24.489756 LPDDR4 DRAM CONFIGURATION
2329 23:42:24.489809 ===================================
2330 23:42:24.489861 EX_ROW_EN[0] = 0x10
2331 23:42:24.489913 EX_ROW_EN[1] = 0x0
2332 23:42:24.489966 LP4Y_EN = 0x0
2333 23:42:24.490018 WORK_FSP = 0x0
2334 23:42:24.490070 WL = 0x4
2335 23:42:24.490122 RL = 0x4
2336 23:42:24.490174 BL = 0x2
2337 23:42:24.490226 RPST = 0x0
2338 23:42:24.490278 RD_PRE = 0x0
2339 23:42:24.490329 WR_PRE = 0x1
2340 23:42:24.490381 WR_PST = 0x0
2341 23:42:24.490433 DBI_WR = 0x0
2342 23:42:24.490486 DBI_RD = 0x0
2343 23:42:24.490538 OTF = 0x1
2344 23:42:24.490590 ===================================
2345 23:42:24.490643 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2346 23:42:24.490697 ==
2347 23:42:24.490749 Dram Type= 6, Freq= 0, CH_0, rank 0
2348 23:42:24.490802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2349 23:42:24.490854 ==
2350 23:42:24.490906 [Duty_Offset_Calibration]
2351 23:42:24.490958 B0:2 B1:0 CA:4
2352 23:42:24.491010
2353 23:42:24.491061 [DutyScan_Calibration_Flow] k_type=0
2354 23:42:24.491115
2355 23:42:24.491171 ==CLK 0==
2356 23:42:24.491227 Final CLK duty delay cell = 0
2357 23:42:24.491283 [0] MAX Duty = 5156%(X100), DQS PI = 14
2358 23:42:24.491338 [0] MIN Duty = 5000%(X100), DQS PI = 8
2359 23:42:24.491395 [0] AVG Duty = 5078%(X100)
2360 23:42:24.491479
2361 23:42:24.491573 CH0 CLK Duty spec in!! Max-Min= 156%
2362 23:42:24.491664 [DutyScan_Calibration_Flow] ====Done====
2363 23:42:24.491754
2364 23:42:24.491839 [DutyScan_Calibration_Flow] k_type=1
2365 23:42:24.491929
2366 23:42:24.492016 ==DQS 0 ==
2367 23:42:24.492100 Final DQS duty delay cell = -4
2368 23:42:24.492183 [-4] MAX Duty = 4938%(X100), DQS PI = 6
2369 23:42:24.492265 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2370 23:42:24.492346 [-4] AVG Duty = 4907%(X100)
2371 23:42:24.492431
2372 23:42:24.492487 ==DQS 1 ==
2373 23:42:24.492539 Final DQS duty delay cell = 0
2374 23:42:24.492593 [0] MAX Duty = 5125%(X100), DQS PI = 52
2375 23:42:24.492666 [0] MIN Duty = 4969%(X100), DQS PI = 14
2376 23:42:24.492721 [0] AVG Duty = 5047%(X100)
2377 23:42:24.492773
2378 23:42:24.492828 CH0 DQS 0 Duty spec in!! Max-Min= 62%
2379 23:42:24.492910
2380 23:42:24.492993 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2381 23:42:24.493078 [DutyScan_Calibration_Flow] ====Done====
2382 23:42:24.493166
2383 23:42:24.493251 [DutyScan_Calibration_Flow] k_type=3
2384 23:42:24.493374
2385 23:42:24.493455 ==DQM 0 ==
2386 23:42:24.493536 Final DQM duty delay cell = 0
2387 23:42:24.493619 [0] MAX Duty = 5094%(X100), DQS PI = 20
2388 23:42:24.493700 [0] MIN Duty = 4844%(X100), DQS PI = 44
2389 23:42:24.493781 [0] AVG Duty = 4969%(X100)
2390 23:42:24.493862
2391 23:42:24.493943 ==DQM 1 ==
2392 23:42:24.494024 Final DQM duty delay cell = 0
2393 23:42:24.494106 [0] MAX Duty = 4969%(X100), DQS PI = 2
2394 23:42:24.494187 [0] MIN Duty = 4875%(X100), DQS PI = 20
2395 23:42:24.494268 [0] AVG Duty = 4922%(X100)
2396 23:42:24.494349
2397 23:42:24.494430 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2398 23:42:24.494510
2399 23:42:24.494591 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2400 23:42:24.494672 [DutyScan_Calibration_Flow] ====Done====
2401 23:42:24.494753
2402 23:42:24.494834 [DutyScan_Calibration_Flow] k_type=2
2403 23:42:24.494922
2404 23:42:24.495018 ==DQ 0 ==
2405 23:42:24.495313 Final DQ duty delay cell = 0
2406 23:42:24.495470 [0] MAX Duty = 5125%(X100), DQS PI = 18
2407 23:42:24.495596 [0] MIN Duty = 4938%(X100), DQS PI = 58
2408 23:42:24.495656 [0] AVG Duty = 5031%(X100)
2409 23:42:24.495713
2410 23:42:24.495768 ==DQ 1 ==
2411 23:42:24.495854 Final DQ duty delay cell = 0
2412 23:42:24.495951 [0] MAX Duty = 5125%(X100), DQS PI = 4
2413 23:42:24.496039 [0] MIN Duty = 4938%(X100), DQS PI = 16
2414 23:42:24.496122 [0] AVG Duty = 5031%(X100)
2415 23:42:24.496207
2416 23:42:24.496289 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2417 23:42:24.496371
2418 23:42:24.496427 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2419 23:42:24.496480 [DutyScan_Calibration_Flow] ====Done====
2420 23:42:24.496533 ==
2421 23:42:24.496593 Dram Type= 6, Freq= 0, CH_1, rank 0
2422 23:42:24.496646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2423 23:42:24.496699 ==
2424 23:42:24.496763 [Duty_Offset_Calibration]
2425 23:42:24.496845 B0:0 B1:-1 CA:3
2426 23:42:24.496927
2427 23:42:24.497011 [DutyScan_Calibration_Flow] k_type=0
2428 23:42:24.497092
2429 23:42:24.497179 ==CLK 0==
2430 23:42:24.497304 Final CLK duty delay cell = -4
2431 23:42:24.497368 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2432 23:42:24.497422 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2433 23:42:24.497475 [-4] AVG Duty = 4938%(X100)
2434 23:42:24.497536
2435 23:42:24.497592 CH1 CLK Duty spec in!! Max-Min= 124%
2436 23:42:24.497644 [DutyScan_Calibration_Flow] ====Done====
2437 23:42:24.497703
2438 23:42:24.497758 [DutyScan_Calibration_Flow] k_type=1
2439 23:42:24.497810
2440 23:42:24.497861 ==DQS 0 ==
2441 23:42:24.497921 Final DQS duty delay cell = 0
2442 23:42:24.497975 [0] MAX Duty = 5187%(X100), DQS PI = 28
2443 23:42:24.498028 [0] MIN Duty = 4876%(X100), DQS PI = 38
2444 23:42:24.498092 [0] AVG Duty = 5031%(X100)
2445 23:42:24.498175
2446 23:42:24.498255 ==DQS 1 ==
2447 23:42:24.498342 Final DQS duty delay cell = 0
2448 23:42:24.498425 [0] MAX Duty = 5156%(X100), DQS PI = 6
2449 23:42:24.498511 [0] MIN Duty = 5031%(X100), DQS PI = 20
2450 23:42:24.498595 [0] AVG Duty = 5093%(X100)
2451 23:42:24.498709
2452 23:42:24.498809 CH1 DQS 0 Duty spec in!! Max-Min= 311%
2453 23:42:24.498899
2454 23:42:24.498988 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2455 23:42:24.499085 [DutyScan_Calibration_Flow] ====Done====
2456 23:42:24.499168
2457 23:42:24.499253 [DutyScan_Calibration_Flow] k_type=3
2458 23:42:24.499336
2459 23:42:24.499417 ==DQM 0 ==
2460 23:42:24.499505 Final DQM duty delay cell = 0
2461 23:42:24.499587 [0] MAX Duty = 5031%(X100), DQS PI = 28
2462 23:42:24.499673 [0] MIN Duty = 4782%(X100), DQS PI = 38
2463 23:42:24.499755 [0] AVG Duty = 4906%(X100)
2464 23:42:24.499839
2465 23:42:24.499921 ==DQM 1 ==
2466 23:42:24.500002 Final DQM duty delay cell = 4
2467 23:42:24.500089 [4] MAX Duty = 5187%(X100), DQS PI = 32
2468 23:42:24.500171 [4] MIN Duty = 5062%(X100), DQS PI = 18
2469 23:42:24.500257 [4] AVG Duty = 5124%(X100)
2470 23:42:24.500338
2471 23:42:24.500416 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2472 23:42:24.500471
2473 23:42:24.500523 CH1 DQM 1 Duty spec in!! Max-Min= 125%
2474 23:42:24.500576 [DutyScan_Calibration_Flow] ====Done====
2475 23:42:24.500658
2476 23:42:24.500739 [DutyScan_Calibration_Flow] k_type=2
2477 23:42:24.500825
2478 23:42:24.500905 ==DQ 0 ==
2479 23:42:24.500990 Final DQ duty delay cell = -4
2480 23:42:24.501073 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2481 23:42:24.501156 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2482 23:42:24.501246 [-4] AVG Duty = 4922%(X100)
2483 23:42:24.501371
2484 23:42:24.501455 ==DQ 1 ==
2485 23:42:24.501530 Final DQ duty delay cell = 0
2486 23:42:24.501597 [0] MAX Duty = 5031%(X100), DQS PI = 34
2487 23:42:24.501651 [0] MIN Duty = 4844%(X100), DQS PI = 62
2488 23:42:24.501704 [0] AVG Duty = 4937%(X100)
2489 23:42:24.501765
2490 23:42:24.501819 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2491 23:42:24.501871
2492 23:42:24.501924 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2493 23:42:24.502010 [DutyScan_Calibration_Flow] ====Done====
2494 23:42:24.502092 nWR fixed to 30
2495 23:42:24.502178 [ModeRegInit_LP4] CH0 RK0
2496 23:42:24.502260 [ModeRegInit_LP4] CH0 RK1
2497 23:42:24.502345 [ModeRegInit_LP4] CH1 RK0
2498 23:42:24.502427 [ModeRegInit_LP4] CH1 RK1
2499 23:42:24.502512 match AC timing 7
2500 23:42:24.502595 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2501 23:42:24.502677 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2502 23:42:24.502763 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2503 23:42:24.502845 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2504 23:42:24.502933 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2505 23:42:24.503015 ==
2506 23:42:24.503100 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 23:42:24.503182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 23:42:24.503263 ==
2509 23:42:24.503350 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2510 23:42:24.503433 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2511 23:42:24.503521 [CA 0] Center 39 (9~70) winsize 62
2512 23:42:24.503603 [CA 1] Center 38 (8~69) winsize 62
2513 23:42:24.503693 [CA 2] Center 35 (5~66) winsize 62
2514 23:42:24.503776 [CA 3] Center 35 (4~66) winsize 63
2515 23:42:24.503924 [CA 4] Center 33 (3~64) winsize 62
2516 23:42:24.504049 [CA 5] Center 33 (3~63) winsize 61
2517 23:42:24.504147
2518 23:42:24.504234 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2519 23:42:24.504317
2520 23:42:24.504399 [CATrainingPosCal] consider 1 rank data
2521 23:42:24.504487 u2DelayCellTimex100 = 270/100 ps
2522 23:42:24.504570 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2523 23:42:24.504656 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2524 23:42:24.504739 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2525 23:42:24.504825 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2526 23:42:24.504915 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2527 23:42:24.505005 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2528 23:42:24.505089
2529 23:42:24.505178 CA PerBit enable=1, Macro0, CA PI delay=33
2530 23:42:24.505290
2531 23:42:24.505407 [CBTSetCACLKResult] CA Dly = 33
2532 23:42:24.505544 CS Dly: 7 (0~38)
2533 23:42:24.505662 ==
2534 23:42:24.505744 Dram Type= 6, Freq= 0, CH_0, rank 1
2535 23:42:24.505832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2536 23:42:24.505914 ==
2537 23:42:24.506003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2538 23:42:24.506086 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2539 23:42:24.506173 [CA 0] Center 39 (9~70) winsize 62
2540 23:42:24.506259 [CA 1] Center 39 (9~70) winsize 62
2541 23:42:24.506341 [CA 2] Center 35 (5~66) winsize 62
2542 23:42:24.506426 [CA 3] Center 35 (5~66) winsize 62
2543 23:42:24.506509 [CA 4] Center 34 (3~65) winsize 63
2544 23:42:24.506590 [CA 5] Center 33 (3~63) winsize 61
2545 23:42:24.506654
2546 23:42:24.506707 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2547 23:42:24.506760
2548 23:42:24.506830 [CATrainingPosCal] consider 2 rank data
2549 23:42:24.507199 u2DelayCellTimex100 = 270/100 ps
2550 23:42:24.507311 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2551 23:42:24.507437 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2552 23:42:24.507523 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2553 23:42:24.507634 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2554 23:42:24.507732 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2555 23:42:24.507836 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2556 23:42:24.507919
2557 23:42:24.508007 CA PerBit enable=1, Macro0, CA PI delay=33
2558 23:42:24.508103
2559 23:42:24.508226 [CBTSetCACLKResult] CA Dly = 33
2560 23:42:24.508309 CS Dly: 8 (0~41)
2561 23:42:24.508404
2562 23:42:24.508461 ----->DramcWriteLeveling(PI) begin...
2563 23:42:24.508518 ==
2564 23:42:24.508579 Dram Type= 6, Freq= 0, CH_0, rank 0
2565 23:42:24.508632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2566 23:42:24.508685 ==
2567 23:42:24.508760 Write leveling (Byte 0): 31 => 31
2568 23:42:24.508846 Write leveling (Byte 1): 27 => 27
2569 23:42:24.508940 DramcWriteLeveling(PI) end<-----
2570 23:42:24.509040
2571 23:42:24.509151 ==
2572 23:42:24.509235 Dram Type= 6, Freq= 0, CH_0, rank 0
2573 23:42:24.509351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2574 23:42:24.509414 ==
2575 23:42:24.509470 [Gating] SW mode calibration
2576 23:42:24.509590 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2577 23:42:24.509718 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2578 23:42:24.509818 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2579 23:42:24.509902 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2580 23:42:24.509992 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2581 23:42:24.510075 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2582 23:42:24.510174 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2583 23:42:24.510259 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 23:42:24.510346 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2585 23:42:24.510429 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
2586 23:42:24.510518 1 0 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
2587 23:42:24.510613 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2588 23:42:24.510697 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2589 23:42:24.510784 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2590 23:42:24.510866 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 23:42:24.510961 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 23:42:24.511046 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2593 23:42:24.511128 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2594 23:42:24.511217 1 1 0 | B1->B0 | 2d2c 4646 | 1 0 | (0 0) (0 0)
2595 23:42:24.511305 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 23:42:24.511429 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2597 23:42:24.511522 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2598 23:42:24.511614 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 23:42:24.511748 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 23:42:24.511835 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 23:42:24.511919 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2602 23:42:24.512002 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2603 23:42:24.512084 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 23:42:24.512167 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 23:42:24.512253 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 23:42:24.512328 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 23:42:24.512382 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 23:42:24.512435 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 23:42:24.512487 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 23:42:24.512539 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:42:24.512591 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:42:24.512648 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:42:24.512741 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:42:24.512824 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:42:24.512906 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:42:24.512987 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2617 23:42:24.513069 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2618 23:42:24.513150 Total UI for P1: 0, mck2ui 16
2619 23:42:24.513233 best dqsien dly found for B0: ( 1, 3, 24)
2620 23:42:24.513343 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2621 23:42:24.513396 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2622 23:42:24.513450 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 23:42:24.513502 Total UI for P1: 0, mck2ui 16
2624 23:42:24.513582 best dqsien dly found for B1: ( 1, 4, 2)
2625 23:42:24.513668 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2626 23:42:24.513756 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2627 23:42:24.513841
2628 23:42:24.513971 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2629 23:42:24.514149 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2630 23:42:24.514255 [Gating] SW calibration Done
2631 23:42:24.514343 ==
2632 23:42:24.514435 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 23:42:24.514518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 23:42:24.514607 ==
2635 23:42:24.514692 RX Vref Scan: 0
2636 23:42:24.514780
2637 23:42:24.514862 RX Vref 0 -> 0, step: 1
2638 23:42:24.514956
2639 23:42:24.515043 RX Delay -40 -> 252, step: 8
2640 23:42:24.515131 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2641 23:42:24.515218 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2642 23:42:24.515315 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2643 23:42:24.515411 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2644 23:42:24.515493 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2645 23:42:24.515575 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2646 23:42:24.515656 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2647 23:42:24.515760 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2648 23:42:24.515855 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2649 23:42:24.515937 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2650 23:42:24.516220 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2651 23:42:24.516311 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2652 23:42:24.516395 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2653 23:42:24.516510 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2654 23:42:24.516595 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2655 23:42:24.516677 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2656 23:42:24.516758 ==
2657 23:42:24.516840 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 23:42:24.516922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 23:42:24.517004 ==
2660 23:42:24.517085 DQS Delay:
2661 23:42:24.517166 DQS0 = 0, DQS1 = 0
2662 23:42:24.517248 DQM Delay:
2663 23:42:24.517371 DQM0 = 119, DQM1 = 107
2664 23:42:24.517447 DQ Delay:
2665 23:42:24.517505 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2666 23:42:24.517560 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2667 23:42:24.517613 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2668 23:42:24.517665 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2669 23:42:24.517718
2670 23:42:24.517769
2671 23:42:24.517821 ==
2672 23:42:24.517872 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 23:42:24.517925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 23:42:24.517978 ==
2675 23:42:24.518030
2676 23:42:24.518081
2677 23:42:24.518133 TX Vref Scan disable
2678 23:42:24.518185 == TX Byte 0 ==
2679 23:42:24.518276 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2680 23:42:24.518360 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2681 23:42:24.518442 == TX Byte 1 ==
2682 23:42:24.518524 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2683 23:42:24.518606 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2684 23:42:24.518687 ==
2685 23:42:24.518769 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 23:42:24.518850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 23:42:24.518931 ==
2688 23:42:24.519013 TX Vref=22, minBit 0, minWin=25, winSum=410
2689 23:42:24.519095 TX Vref=24, minBit 8, minWin=25, winSum=419
2690 23:42:24.519176 TX Vref=26, minBit 10, minWin=25, winSum=425
2691 23:42:24.519258 TX Vref=28, minBit 5, minWin=26, winSum=431
2692 23:42:24.519340 TX Vref=30, minBit 5, minWin=26, winSum=432
2693 23:42:24.519422 TX Vref=32, minBit 5, minWin=26, winSum=431
2694 23:42:24.519504 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 30
2695 23:42:24.519586
2696 23:42:24.519666 Final TX Range 1 Vref 30
2697 23:42:24.519747
2698 23:42:24.519817 ==
2699 23:42:24.519871 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 23:42:24.519934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 23:42:24.520016 ==
2702 23:42:24.520097
2703 23:42:24.520181
2704 23:42:24.520263 TX Vref Scan disable
2705 23:42:24.520346 == TX Byte 0 ==
2706 23:42:24.520433 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2707 23:42:24.520516 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2708 23:42:24.520601 == TX Byte 1 ==
2709 23:42:24.520688 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2710 23:42:24.520777 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2711 23:42:24.520859
2712 23:42:24.520940 [DATLAT]
2713 23:42:24.521024 Freq=1200, CH0 RK0
2714 23:42:24.521106
2715 23:42:24.521192 DATLAT Default: 0xd
2716 23:42:24.521309 0, 0xFFFF, sum = 0
2717 23:42:24.521461 1, 0xFFFF, sum = 0
2718 23:42:24.521600 2, 0xFFFF, sum = 0
2719 23:42:24.521708 3, 0xFFFF, sum = 0
2720 23:42:24.521806 4, 0xFFFF, sum = 0
2721 23:42:24.521862 5, 0xFFFF, sum = 0
2722 23:42:24.521948 6, 0xFFFF, sum = 0
2723 23:42:24.522019 7, 0xFFFF, sum = 0
2724 23:42:24.522132 8, 0xFFFF, sum = 0
2725 23:42:24.522190 9, 0xFFFF, sum = 0
2726 23:42:24.522253 10, 0xFFFF, sum = 0
2727 23:42:24.522350 11, 0xFFFF, sum = 0
2728 23:42:24.522434 12, 0x0, sum = 1
2729 23:42:24.522528 13, 0x0, sum = 2
2730 23:42:24.522612 14, 0x0, sum = 3
2731 23:42:24.522710 15, 0x0, sum = 4
2732 23:42:24.522795 best_step = 13
2733 23:42:24.522882
2734 23:42:24.522963 ==
2735 23:42:24.523052 Dram Type= 6, Freq= 0, CH_0, rank 0
2736 23:42:24.523136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2737 23:42:24.523220 ==
2738 23:42:24.523301 RX Vref Scan: 1
2739 23:42:24.523383
2740 23:42:24.523475 Set Vref Range= 32 -> 127
2741 23:42:24.523562
2742 23:42:24.523643 RX Vref 32 -> 127, step: 1
2743 23:42:24.523724
2744 23:42:24.523805 RX Delay -21 -> 252, step: 4
2745 23:42:24.523890
2746 23:42:24.523973 Set Vref, RX VrefLevel [Byte0]: 32
2747 23:42:24.524063 [Byte1]: 32
2748 23:42:24.524144
2749 23:42:24.524227 Set Vref, RX VrefLevel [Byte0]: 33
2750 23:42:24.524305 [Byte1]: 33
2751 23:42:24.524359
2752 23:42:24.524415 Set Vref, RX VrefLevel [Byte0]: 34
2753 23:42:24.524476 [Byte1]: 34
2754 23:42:24.524555
2755 23:42:24.524646 Set Vref, RX VrefLevel [Byte0]: 35
2756 23:42:24.524735 [Byte1]: 35
2757 23:42:24.524848
2758 23:42:24.524936 Set Vref, RX VrefLevel [Byte0]: 36
2759 23:42:24.525017 [Byte1]: 36
2760 23:42:24.525112
2761 23:42:24.525195 Set Vref, RX VrefLevel [Byte0]: 37
2762 23:42:24.525324 [Byte1]: 37
2763 23:42:24.525382
2764 23:42:24.525438 Set Vref, RX VrefLevel [Byte0]: 38
2765 23:42:24.525491 [Byte1]: 38
2766 23:42:24.525542
2767 23:42:24.525595 Set Vref, RX VrefLevel [Byte0]: 39
2768 23:42:24.525652 [Byte1]: 39
2769 23:42:24.525722
2770 23:42:24.525803 Set Vref, RX VrefLevel [Byte0]: 40
2771 23:42:24.525884 [Byte1]: 40
2772 23:42:24.525965
2773 23:42:24.526046 Set Vref, RX VrefLevel [Byte0]: 41
2774 23:42:24.526131 [Byte1]: 41
2775 23:42:24.526212
2776 23:42:24.526293 Set Vref, RX VrefLevel [Byte0]: 42
2777 23:42:24.526374 [Byte1]: 42
2778 23:42:24.526462
2779 23:42:24.526556 Set Vref, RX VrefLevel [Byte0]: 43
2780 23:42:24.526731 [Byte1]: 43
2781 23:42:24.526835
2782 23:42:24.526929 Set Vref, RX VrefLevel [Byte0]: 44
2783 23:42:24.527020 [Byte1]: 44
2784 23:42:24.527103
2785 23:42:24.527185 Set Vref, RX VrefLevel [Byte0]: 45
2786 23:42:24.527266 [Byte1]: 45
2787 23:42:24.527347
2788 23:42:24.527428 Set Vref, RX VrefLevel [Byte0]: 46
2789 23:42:24.527509 [Byte1]: 46
2790 23:42:24.527589
2791 23:42:24.527670 Set Vref, RX VrefLevel [Byte0]: 47
2792 23:42:24.527784 [Byte1]: 47
2793 23:42:24.527865
2794 23:42:24.527958 Set Vref, RX VrefLevel [Byte0]: 48
2795 23:42:24.528050 [Byte1]: 48
2796 23:42:24.528176
2797 23:42:24.528258 Set Vref, RX VrefLevel [Byte0]: 49
2798 23:42:24.528340 [Byte1]: 49
2799 23:42:24.528416
2800 23:42:24.528470 Set Vref, RX VrefLevel [Byte0]: 50
2801 23:42:24.528541 [Byte1]: 50
2802 23:42:24.528627
2803 23:42:24.528709 Set Vref, RX VrefLevel [Byte0]: 51
2804 23:42:24.528790 [Byte1]: 51
2805 23:42:24.528871
2806 23:42:24.528954 Set Vref, RX VrefLevel [Byte0]: 52
2807 23:42:24.529042 [Byte1]: 52
2808 23:42:24.529133
2809 23:42:24.529220 Set Vref, RX VrefLevel [Byte0]: 53
2810 23:42:24.529320 [Byte1]: 53
2811 23:42:24.529402
2812 23:42:24.529484 Set Vref, RX VrefLevel [Byte0]: 54
2813 23:42:24.529565 [Byte1]: 54
2814 23:42:24.529646
2815 23:42:24.529941 Set Vref, RX VrefLevel [Byte0]: 55
2816 23:42:24.530005 [Byte1]: 55
2817 23:42:24.530059
2818 23:42:24.530111 Set Vref, RX VrefLevel [Byte0]: 56
2819 23:42:24.530162 [Byte1]: 56
2820 23:42:24.530214
2821 23:42:24.530266 Set Vref, RX VrefLevel [Byte0]: 57
2822 23:42:24.530381 [Byte1]: 57
2823 23:42:24.530464
2824 23:42:24.530545 Set Vref, RX VrefLevel [Byte0]: 58
2825 23:42:24.530626 [Byte1]: 58
2826 23:42:24.530707
2827 23:42:24.530788 Set Vref, RX VrefLevel [Byte0]: 59
2828 23:42:24.530869 [Byte1]: 59
2829 23:42:24.530949
2830 23:42:24.531030 Set Vref, RX VrefLevel [Byte0]: 60
2831 23:42:24.531111 [Byte1]: 60
2832 23:42:24.531191
2833 23:42:24.531271 Set Vref, RX VrefLevel [Byte0]: 61
2834 23:42:24.531355 [Byte1]: 61
2835 23:42:24.531447
2836 23:42:24.531529 Set Vref, RX VrefLevel [Byte0]: 62
2837 23:42:24.531619 [Byte1]: 62
2838 23:42:24.531707
2839 23:42:24.531788 Set Vref, RX VrefLevel [Byte0]: 63
2840 23:42:24.531869 [Byte1]: 63
2841 23:42:24.531950
2842 23:42:24.532031 Set Vref, RX VrefLevel [Byte0]: 64
2843 23:42:24.532113 [Byte1]: 64
2844 23:42:24.532193
2845 23:42:24.532274 Set Vref, RX VrefLevel [Byte0]: 65
2846 23:42:24.532355 [Byte1]: 65
2847 23:42:24.532435
2848 23:42:24.532515 Set Vref, RX VrefLevel [Byte0]: 66
2849 23:42:24.532597 [Byte1]: 66
2850 23:42:24.532677
2851 23:42:24.532769 Set Vref, RX VrefLevel [Byte0]: 67
2852 23:42:24.532856 [Byte1]: 67
2853 23:42:24.532937
2854 23:42:24.533018 Set Vref, RX VrefLevel [Byte0]: 68
2855 23:42:24.533099 [Byte1]: 68
2856 23:42:24.533179
2857 23:42:24.533266 Final RX Vref Byte 0 = 58 to rank0
2858 23:42:24.533323 Final RX Vref Byte 1 = 49 to rank0
2859 23:42:24.533376 Final RX Vref Byte 0 = 58 to rank1
2860 23:42:24.533427 Final RX Vref Byte 1 = 49 to rank1==
2861 23:42:24.533480 Dram Type= 6, Freq= 0, CH_0, rank 0
2862 23:42:24.533532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2863 23:42:24.533585 ==
2864 23:42:24.533636 DQS Delay:
2865 23:42:24.533688 DQS0 = 0, DQS1 = 0
2866 23:42:24.533752 DQM Delay:
2867 23:42:24.533844 DQM0 = 119, DQM1 = 105
2868 23:42:24.533926 DQ Delay:
2869 23:42:24.534007 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =116
2870 23:42:24.534093 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2871 23:42:24.534175 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =100
2872 23:42:24.534257 DQ12 =114, DQ13 =108, DQ14 =116, DQ15 =114
2873 23:42:24.534338
2874 23:42:24.534419
2875 23:42:24.534501 [DQSOSCAuto] RK0, (LSB)MR18= 0x804, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2876 23:42:24.534583 CH0 RK0: MR19=404, MR18=804
2877 23:42:24.534666 CH0_RK0: MR19=0x404, MR18=0x804, DQSOSC=406, MR23=63, INC=39, DEC=26
2878 23:42:24.534761
2879 23:42:24.534839 ----->DramcWriteLeveling(PI) begin...
2880 23:42:24.534895 ==
2881 23:42:24.534948 Dram Type= 6, Freq= 0, CH_0, rank 1
2882 23:42:24.535000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 23:42:24.535054 ==
2884 23:42:24.535110 Write leveling (Byte 0): 32 => 32
2885 23:42:24.535164 Write leveling (Byte 1): 27 => 27
2886 23:42:24.535266 DramcWriteLeveling(PI) end<-----
2887 23:42:24.535351
2888 23:42:24.535434 ==
2889 23:42:24.535515 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 23:42:24.535599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 23:42:24.535683 ==
2892 23:42:24.535766 [Gating] SW mode calibration
2893 23:42:24.535851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2894 23:42:24.535933 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2895 23:42:24.536016 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2896 23:42:24.536098 0 15 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
2897 23:42:24.536180 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 23:42:24.536261 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 23:42:24.536343 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 23:42:24.536424 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2901 23:42:24.536518 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2902 23:42:24.536602 0 15 28 | B1->B0 | 3434 2626 | 0 0 | (0 0) (1 1)
2903 23:42:24.536684 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
2904 23:42:24.536766 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 23:42:24.536849 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 23:42:24.536930 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 23:42:24.537011 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 23:42:24.537093 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2909 23:42:24.537174 1 0 24 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
2910 23:42:24.537297 1 0 28 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
2911 23:42:24.537370 1 1 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
2912 23:42:24.537424 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 23:42:24.537476 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 23:42:24.537528 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 23:42:24.537621 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 23:42:24.537678 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 23:42:24.537731 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2918 23:42:24.537783 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2919 23:42:24.537835 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2920 23:42:24.537887 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 23:42:24.537939 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 23:42:24.537991 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 23:42:24.538043 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 23:42:24.538109 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 23:42:24.538171 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 23:42:24.538225 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 23:42:24.538277 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 23:42:24.538329 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 23:42:24.538381 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 23:42:24.538433 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 23:42:24.538685 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:42:24.538744 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2933 23:42:24.538803 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2934 23:42:24.538887 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2935 23:42:24.538971 Total UI for P1: 0, mck2ui 16
2936 23:42:24.539054 best dqsien dly found for B0: ( 1, 3, 22)
2937 23:42:24.539137 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 23:42:24.539218 Total UI for P1: 0, mck2ui 16
2939 23:42:24.539300 best dqsien dly found for B1: ( 1, 3, 28)
2940 23:42:24.539381 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2941 23:42:24.539463 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2942 23:42:24.539544
2943 23:42:24.539625 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2944 23:42:24.539706 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2945 23:42:24.539787 [Gating] SW calibration Done
2946 23:42:24.539868 ==
2947 23:42:24.539966 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 23:42:24.540052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 23:42:24.540134 ==
2950 23:42:24.540215 RX Vref Scan: 0
2951 23:42:24.540296
2952 23:42:24.540376 RX Vref 0 -> 0, step: 1
2953 23:42:24.540457
2954 23:42:24.540537 RX Delay -40 -> 252, step: 8
2955 23:42:24.540619 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2956 23:42:24.540701 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2957 23:42:24.540782 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2958 23:42:24.540864 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2959 23:42:24.540945 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2960 23:42:24.541028 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2961 23:42:24.541122 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2962 23:42:24.541206 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2963 23:42:24.541292 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2964 23:42:24.541348 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2965 23:42:24.541401 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2966 23:42:24.541453 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2967 23:42:24.541506 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2968 23:42:24.541558 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2969 23:42:24.541610 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2970 23:42:24.541662 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2971 23:42:24.541740 ==
2972 23:42:24.541795 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 23:42:24.541847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 23:42:24.541899 ==
2975 23:42:24.541952 DQS Delay:
2976 23:42:24.542004 DQS0 = 0, DQS1 = 0
2977 23:42:24.542055 DQM Delay:
2978 23:42:24.542107 DQM0 = 119, DQM1 = 107
2979 23:42:24.542159 DQ Delay:
2980 23:42:24.542210 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2981 23:42:24.542262 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2982 23:42:24.542314 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2983 23:42:24.542366 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =115
2984 23:42:24.542418
2985 23:42:24.542469
2986 23:42:24.542520 ==
2987 23:42:24.542572 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 23:42:24.542623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 23:42:24.542676 ==
2990 23:42:24.542727
2991 23:42:24.542778
2992 23:42:24.542829 TX Vref Scan disable
2993 23:42:24.542881 == TX Byte 0 ==
2994 23:42:24.542932 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2995 23:42:24.542985 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2996 23:42:24.543036 == TX Byte 1 ==
2997 23:42:24.543088 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2998 23:42:24.543140 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2999 23:42:24.543191 ==
3000 23:42:24.543243 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 23:42:24.543294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 23:42:24.543347 ==
3003 23:42:24.543398 TX Vref=22, minBit 14, minWin=25, winSum=420
3004 23:42:24.638039 TX Vref=24, minBit 14, minWin=25, winSum=424
3005 23:42:24.638191 TX Vref=26, minBit 1, minWin=26, winSum=427
3006 23:42:24.638287 TX Vref=28, minBit 12, minWin=26, winSum=430
3007 23:42:24.638392 TX Vref=30, minBit 10, minWin=26, winSum=431
3008 23:42:24.638480 TX Vref=32, minBit 15, minWin=25, winSum=430
3009 23:42:24.638583 [TxChooseVref] Worse bit 10, Min win 26, Win sum 431, Final Vref 30
3010 23:42:24.638677
3011 23:42:24.638762 Final TX Range 1 Vref 30
3012 23:42:24.638849
3013 23:42:24.638935 ==
3014 23:42:24.639020 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 23:42:24.639115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 23:42:24.639199 ==
3017 23:42:24.639289
3018 23:42:24.639371
3019 23:42:24.639468 TX Vref Scan disable
3020 23:42:24.639553 == TX Byte 0 ==
3021 23:42:24.639674 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3022 23:42:24.639759 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3023 23:42:24.639847 == TX Byte 1 ==
3024 23:42:24.639933 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3025 23:42:24.640016 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3026 23:42:24.640101
3027 23:42:24.640182 [DATLAT]
3028 23:42:24.640327 Freq=1200, CH0 RK1
3029 23:42:24.640409
3030 23:42:24.640477 DATLAT Default: 0xd
3031 23:42:24.640532 0, 0xFFFF, sum = 0
3032 23:42:24.640586 1, 0xFFFF, sum = 0
3033 23:42:24.640645 2, 0xFFFF, sum = 0
3034 23:42:24.640700 3, 0xFFFF, sum = 0
3035 23:42:24.640754 4, 0xFFFF, sum = 0
3036 23:42:24.640807 5, 0xFFFF, sum = 0
3037 23:42:24.640888 6, 0xFFFF, sum = 0
3038 23:42:24.640972 7, 0xFFFF, sum = 0
3039 23:42:24.641061 8, 0xFFFF, sum = 0
3040 23:42:24.641145 9, 0xFFFF, sum = 0
3041 23:42:24.641231 10, 0xFFFF, sum = 0
3042 23:42:24.641339 11, 0xFFFF, sum = 0
3043 23:42:24.641393 12, 0x0, sum = 1
3044 23:42:24.641447 13, 0x0, sum = 2
3045 23:42:24.641537 14, 0x0, sum = 3
3046 23:42:24.641594 15, 0x0, sum = 4
3047 23:42:24.641696 best_step = 13
3048 23:42:24.641751
3049 23:42:24.641804 ==
3050 23:42:24.641897 Dram Type= 6, Freq= 0, CH_0, rank 1
3051 23:42:24.641981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3052 23:42:24.642070 ==
3053 23:42:24.642153 RX Vref Scan: 0
3054 23:42:24.642240
3055 23:42:24.642332 RX Vref 0 -> 0, step: 1
3056 23:42:24.642416
3057 23:42:24.642503 RX Delay -21 -> 252, step: 4
3058 23:42:24.642586 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3059 23:42:24.642686 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3060 23:42:24.642770 iDelay=195, Bit 2, Center 112 (51 ~ 174) 124
3061 23:42:24.642855 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3062 23:42:24.642949 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3063 23:42:24.643032 iDelay=195, Bit 5, Center 112 (51 ~ 174) 124
3064 23:42:24.643120 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3065 23:42:24.643202 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3066 23:42:24.643291 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3067 23:42:24.643374 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3068 23:42:24.643464 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3069 23:42:24.643783 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3070 23:42:24.643905 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3071 23:42:24.643992 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3072 23:42:24.644093 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3073 23:42:24.644180 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3074 23:42:24.644279 ==
3075 23:42:24.644342 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 23:42:24.644395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 23:42:24.644452 ==
3078 23:42:24.644533 DQS Delay:
3079 23:42:24.644587 DQS0 = 0, DQS1 = 0
3080 23:42:24.644640 DQM Delay:
3081 23:42:24.644742 DQM0 = 117, DQM1 = 106
3082 23:42:24.644827 DQ Delay:
3083 23:42:24.644914 DQ0 =114, DQ1 =120, DQ2 =112, DQ3 =114
3084 23:42:24.645003 DQ4 =120, DQ5 =112, DQ6 =128, DQ7 =122
3085 23:42:24.645086 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3086 23:42:24.645182 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =112
3087 23:42:24.645292
3088 23:42:24.645363
3089 23:42:24.645432 [DQSOSCAuto] RK1, (LSB)MR18= 0x2ff, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3090 23:42:24.645528 CH0 RK1: MR19=403, MR18=2FF
3091 23:42:24.645586 CH0_RK1: MR19=0x403, MR18=0x2FF, DQSOSC=409, MR23=63, INC=39, DEC=26
3092 23:42:24.645699 [RxdqsGatingPostProcess] freq 1200
3093 23:42:24.645795 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3094 23:42:24.645879 best DQS0 dly(2T, 0.5T) = (0, 11)
3095 23:42:24.645967 best DQS1 dly(2T, 0.5T) = (0, 12)
3096 23:42:24.646050 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3097 23:42:24.646147 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3098 23:42:24.646231 best DQS0 dly(2T, 0.5T) = (0, 11)
3099 23:42:24.646320 best DQS1 dly(2T, 0.5T) = (0, 11)
3100 23:42:24.646404 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3101 23:42:24.646496 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3102 23:42:24.646584 Pre-setting of DQS Precalculation
3103 23:42:24.646672 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3104 23:42:24.646761 ==
3105 23:42:24.646872 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 23:42:24.646972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 23:42:24.647060 ==
3108 23:42:24.647144 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3109 23:42:24.647235 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3110 23:42:24.647318 [CA 0] Center 38 (8~68) winsize 61
3111 23:42:24.647404 [CA 1] Center 37 (7~68) winsize 62
3112 23:42:24.647498 [CA 2] Center 35 (5~65) winsize 61
3113 23:42:24.647585 [CA 3] Center 34 (4~64) winsize 61
3114 23:42:24.647678 [CA 4] Center 34 (4~64) winsize 61
3115 23:42:24.647761 [CA 5] Center 33 (3~63) winsize 61
3116 23:42:24.647850
3117 23:42:24.647933 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3118 23:42:24.648029
3119 23:42:24.648125 [CATrainingPosCal] consider 1 rank data
3120 23:42:24.648216 u2DelayCellTimex100 = 270/100 ps
3121 23:42:24.648306 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3122 23:42:24.648390 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3123 23:42:24.648487 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3124 23:42:24.648571 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3125 23:42:24.648660 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3126 23:42:24.648743 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3127 23:42:24.648837
3128 23:42:24.648921 CA PerBit enable=1, Macro0, CA PI delay=33
3129 23:42:24.649008
3130 23:42:24.649091 [CBTSetCACLKResult] CA Dly = 33
3131 23:42:24.649197 CS Dly: 4 (0~35)
3132 23:42:24.649305 ==
3133 23:42:24.649361 Dram Type= 6, Freq= 0, CH_1, rank 1
3134 23:42:24.649443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 23:42:24.649500 ==
3136 23:42:24.649554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3137 23:42:24.649648 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3138 23:42:24.649746 [CA 0] Center 37 (7~68) winsize 62
3139 23:42:24.649828 [CA 1] Center 38 (8~68) winsize 61
3140 23:42:24.649925 [CA 2] Center 34 (4~65) winsize 62
3141 23:42:24.650008 [CA 3] Center 33 (3~64) winsize 62
3142 23:42:24.650107 [CA 4] Center 34 (4~64) winsize 61
3143 23:42:24.650192 [CA 5] Center 33 (3~64) winsize 62
3144 23:42:24.650278
3145 23:42:24.650381 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3146 23:42:24.650491
3147 23:42:24.650576 [CATrainingPosCal] consider 2 rank data
3148 23:42:24.650663 u2DelayCellTimex100 = 270/100 ps
3149 23:42:24.650748 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3150 23:42:24.650830 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3151 23:42:24.650930 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3152 23:42:24.651017 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3153 23:42:24.651100 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3154 23:42:24.651189 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3155 23:42:24.651271
3156 23:42:24.651368 CA PerBit enable=1, Macro0, CA PI delay=33
3157 23:42:24.651451
3158 23:42:24.651539 [CBTSetCACLKResult] CA Dly = 33
3159 23:42:24.651633 CS Dly: 6 (0~39)
3160 23:42:24.651727
3161 23:42:24.651815 ----->DramcWriteLeveling(PI) begin...
3162 23:42:24.651905 ==
3163 23:42:24.651990 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 23:42:24.652074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 23:42:24.652169 ==
3166 23:42:24.652253 Write leveling (Byte 0): 26 => 26
3167 23:42:24.652322 Write leveling (Byte 1): 26 => 26
3168 23:42:24.652402 DramcWriteLeveling(PI) end<-----
3169 23:42:24.652458
3170 23:42:24.652512 ==
3171 23:42:24.652587 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 23:42:24.652670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 23:42:24.652756 ==
3174 23:42:24.652849 [Gating] SW mode calibration
3175 23:42:24.652933 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3176 23:42:24.653025 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3177 23:42:24.653108 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
3178 23:42:24.653207 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 23:42:24.653331 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 23:42:24.653394 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 23:42:24.653502 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 23:42:24.653643 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 23:42:24.653700 0 15 24 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 0)
3184 23:42:24.653783 0 15 28 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
3185 23:42:24.653872 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 23:42:24.653960 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 23:42:24.654263 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 23:42:24.654403 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 23:42:24.654503 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 23:42:24.654599 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 23:42:24.654691 1 0 24 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
3192 23:42:24.654775 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3193 23:42:24.654873 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 23:42:24.654959 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 23:42:24.655042 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 23:42:24.655133 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 23:42:24.655217 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 23:42:24.655315 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 23:42:24.655401 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3200 23:42:24.655484 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3201 23:42:24.655573 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 23:42:24.655707 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 23:42:24.655827 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 23:42:24.655931 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 23:42:24.656015 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 23:42:24.656111 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 23:42:24.656195 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 23:42:24.656289 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 23:42:24.656351 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 23:42:24.656405 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 23:42:24.656458 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 23:42:24.656520 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:42:24.656606 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:42:24.656689 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 23:42:24.656787 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 23:42:24.656901 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3217 23:42:24.656991 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 23:42:24.657074 Total UI for P1: 0, mck2ui 16
3219 23:42:24.657169 best dqsien dly found for B0: ( 1, 3, 28)
3220 23:42:24.657277 Total UI for P1: 0, mck2ui 16
3221 23:42:24.657359 best dqsien dly found for B1: ( 1, 3, 28)
3222 23:42:24.657416 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3223 23:42:24.657470 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3224 23:42:24.657533
3225 23:42:24.657609 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3226 23:42:24.657692 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3227 23:42:24.657776 [Gating] SW calibration Done
3228 23:42:24.657871 ==
3229 23:42:24.657955 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 23:42:24.658048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 23:42:24.658133 ==
3232 23:42:24.658223 RX Vref Scan: 0
3233 23:42:24.658321
3234 23:42:24.658405 RX Vref 0 -> 0, step: 1
3235 23:42:24.658494
3236 23:42:24.658576 RX Delay -40 -> 252, step: 8
3237 23:42:24.658672 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3238 23:42:24.658756 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3239 23:42:24.658848 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3240 23:42:24.658931 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3241 23:42:24.659026 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3242 23:42:24.659109 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3243 23:42:24.659203 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3244 23:42:24.659294 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3245 23:42:24.659379 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3246 23:42:24.659466 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3247 23:42:24.659551 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3248 23:42:24.659634 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3249 23:42:24.659730 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3250 23:42:24.659813 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3251 23:42:24.659949 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3252 23:42:24.660053 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3253 23:42:24.660140 ==
3254 23:42:24.660232 Dram Type= 6, Freq= 0, CH_1, rank 0
3255 23:42:24.660321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3256 23:42:24.660404 ==
3257 23:42:24.660475 DQS Delay:
3258 23:42:24.660529 DQS0 = 0, DQS1 = 0
3259 23:42:24.660582 DQM Delay:
3260 23:42:24.660676 DQM0 = 115, DQM1 = 112
3261 23:42:24.660810 DQ Delay:
3262 23:42:24.660913 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3263 23:42:24.660998 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3264 23:42:24.661083 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3265 23:42:24.661177 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3266 23:42:24.661288
3267 23:42:24.661365
3268 23:42:24.661418 ==
3269 23:42:24.661480 Dram Type= 6, Freq= 0, CH_1, rank 0
3270 23:42:24.661552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3271 23:42:24.661607 ==
3272 23:42:24.661661
3273 23:42:24.661723
3274 23:42:24.661776 TX Vref Scan disable
3275 23:42:24.661829 == TX Byte 0 ==
3276 23:42:24.661908 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3277 23:42:24.661993 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3278 23:42:24.662076 == TX Byte 1 ==
3279 23:42:24.662169 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3280 23:42:24.662255 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3281 23:42:24.662344 ==
3282 23:42:24.662428 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 23:42:24.662511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 23:42:24.662606 ==
3285 23:42:24.662689 TX Vref=22, minBit 9, minWin=23, winSum=408
3286 23:42:24.662785 TX Vref=24, minBit 9, minWin=23, winSum=414
3287 23:42:24.662869 TX Vref=26, minBit 8, minWin=25, winSum=419
3288 23:42:24.662966 TX Vref=28, minBit 9, minWin=25, winSum=427
3289 23:42:24.663050 TX Vref=30, minBit 9, minWin=25, winSum=427
3290 23:42:24.663141 TX Vref=32, minBit 9, minWin=25, winSum=424
3291 23:42:24.663258 [TxChooseVref] Worse bit 9, Min win 25, Win sum 427, Final Vref 28
3292 23:42:24.663378
3293 23:42:24.663465 Final TX Range 1 Vref 28
3294 23:42:24.663549
3295 23:42:24.663646 ==
3296 23:42:24.663730 Dram Type= 6, Freq= 0, CH_1, rank 0
3297 23:42:24.663817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3298 23:42:24.663900 ==
3299 23:42:24.663987
3300 23:42:24.664078
3301 23:42:24.664368 TX Vref Scan disable
3302 23:42:24.664455 == TX Byte 0 ==
3303 23:42:24.664512 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3304 23:42:24.664568 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3305 23:42:24.664625 == TX Byte 1 ==
3306 23:42:24.664721 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3307 23:42:24.664808 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3308 23:42:24.664895
3309 23:42:24.664977 [DATLAT]
3310 23:42:24.665072 Freq=1200, CH1 RK0
3311 23:42:24.665155
3312 23:42:24.665242 DATLAT Default: 0xd
3313 23:42:24.665371 0, 0xFFFF, sum = 0
3314 23:42:24.665472 1, 0xFFFF, sum = 0
3315 23:42:24.665558 2, 0xFFFF, sum = 0
3316 23:42:24.665648 3, 0xFFFF, sum = 0
3317 23:42:24.665733 4, 0xFFFF, sum = 0
3318 23:42:24.665830 5, 0xFFFF, sum = 0
3319 23:42:24.665921 6, 0xFFFF, sum = 0
3320 23:42:24.666005 7, 0xFFFF, sum = 0
3321 23:42:24.666096 8, 0xFFFF, sum = 0
3322 23:42:24.666180 9, 0xFFFF, sum = 0
3323 23:42:24.666272 10, 0xFFFF, sum = 0
3324 23:42:24.666361 11, 0xFFFF, sum = 0
3325 23:42:24.666453 12, 0x0, sum = 1
3326 23:42:24.666544 13, 0x0, sum = 2
3327 23:42:24.666663 14, 0x0, sum = 3
3328 23:42:24.666751 15, 0x0, sum = 4
3329 23:42:24.666805 best_step = 13
3330 23:42:24.666933
3331 23:42:24.667076 ==
3332 23:42:24.667173 Dram Type= 6, Freq= 0, CH_1, rank 0
3333 23:42:24.667272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3334 23:42:24.667356 ==
3335 23:42:24.667438 RX Vref Scan: 1
3336 23:42:24.667533
3337 23:42:24.667617 Set Vref Range= 32 -> 127
3338 23:42:24.667714
3339 23:42:24.667797 RX Vref 32 -> 127, step: 1
3340 23:42:24.667879
3341 23:42:24.667975 RX Delay -13 -> 252, step: 4
3342 23:42:24.668093
3343 23:42:24.668180 Set Vref, RX VrefLevel [Byte0]: 32
3344 23:42:24.668262 [Byte1]: 32
3345 23:42:24.668351
3346 23:42:24.668424 Set Vref, RX VrefLevel [Byte0]: 33
3347 23:42:24.668502 [Byte1]: 33
3348 23:42:24.668584
3349 23:42:24.668679 Set Vref, RX VrefLevel [Byte0]: 34
3350 23:42:24.668763 [Byte1]: 34
3351 23:42:24.668849
3352 23:42:24.668934 Set Vref, RX VrefLevel [Byte0]: 35
3353 23:42:24.669017 [Byte1]: 35
3354 23:42:24.669111
3355 23:42:24.669195 Set Vref, RX VrefLevel [Byte0]: 36
3356 23:42:24.669326 [Byte1]: 36
3357 23:42:24.669385
3358 23:42:24.669439 Set Vref, RX VrefLevel [Byte0]: 37
3359 23:42:24.669492 [Byte1]: 37
3360 23:42:24.669558
3361 23:42:24.669611 Set Vref, RX VrefLevel [Byte0]: 38
3362 23:42:24.669664 [Byte1]: 38
3363 23:42:24.669736
3364 23:42:24.669797 Set Vref, RX VrefLevel [Byte0]: 39
3365 23:42:24.669904 [Byte1]: 39
3366 23:42:24.669970
3367 23:42:24.670064 Set Vref, RX VrefLevel [Byte0]: 40
3368 23:42:24.670148 [Byte1]: 40
3369 23:42:24.670229
3370 23:42:24.670313 Set Vref, RX VrefLevel [Byte0]: 41
3371 23:42:24.670395 [Byte1]: 41
3372 23:42:24.670476
3373 23:42:24.670561 Set Vref, RX VrefLevel [Byte0]: 42
3374 23:42:24.670643 [Byte1]: 42
3375 23:42:24.670735
3376 23:42:24.670819 Set Vref, RX VrefLevel [Byte0]: 43
3377 23:42:24.670900 [Byte1]: 43
3378 23:42:24.670980
3379 23:42:24.671061 Set Vref, RX VrefLevel [Byte0]: 44
3380 23:42:24.671142 [Byte1]: 44
3381 23:42:24.671222
3382 23:42:24.671303 Set Vref, RX VrefLevel [Byte0]: 45
3383 23:42:24.671422 [Byte1]: 45
3384 23:42:24.671503
3385 23:42:24.671593 Set Vref, RX VrefLevel [Byte0]: 46
3386 23:42:24.671680 [Byte1]: 46
3387 23:42:24.671761
3388 23:42:24.671842 Set Vref, RX VrefLevel [Byte0]: 47
3389 23:42:24.671923 [Byte1]: 47
3390 23:42:24.672035
3391 23:42:24.672116 Set Vref, RX VrefLevel [Byte0]: 48
3392 23:42:24.672197 [Byte1]: 48
3393 23:42:24.672278
3394 23:42:24.672364 Set Vref, RX VrefLevel [Byte0]: 49
3395 23:42:24.672426 [Byte1]: 49
3396 23:42:24.672507
3397 23:42:24.672588 Set Vref, RX VrefLevel [Byte0]: 50
3398 23:42:24.672670 [Byte1]: 50
3399 23:42:24.672750
3400 23:42:24.672831 Set Vref, RX VrefLevel [Byte0]: 51
3401 23:42:24.672912 [Byte1]: 51
3402 23:42:24.672992
3403 23:42:24.673074 Set Vref, RX VrefLevel [Byte0]: 52
3404 23:42:24.673162 [Byte1]: 52
3405 23:42:24.673273
3406 23:42:24.673401 Set Vref, RX VrefLevel [Byte0]: 53
3407 23:42:24.673483 [Byte1]: 53
3408 23:42:24.673564
3409 23:42:24.673645 Set Vref, RX VrefLevel [Byte0]: 54
3410 23:42:24.673726 [Byte1]: 54
3411 23:42:24.673806
3412 23:42:24.673887 Set Vref, RX VrefLevel [Byte0]: 55
3413 23:42:24.673969 [Byte1]: 55
3414 23:42:24.674050
3415 23:42:24.674110 Set Vref, RX VrefLevel [Byte0]: 56
3416 23:42:24.674192 [Byte1]: 56
3417 23:42:24.674272
3418 23:42:24.674353 Set Vref, RX VrefLevel [Byte0]: 57
3419 23:42:24.674435 [Byte1]: 57
3420 23:42:24.674515
3421 23:42:24.674595 Set Vref, RX VrefLevel [Byte0]: 58
3422 23:42:24.674676 [Byte1]: 58
3423 23:42:24.674757
3424 23:42:24.674836 Set Vref, RX VrefLevel [Byte0]: 59
3425 23:42:24.674905 [Byte1]: 59
3426 23:42:24.674986
3427 23:42:24.675067 Set Vref, RX VrefLevel [Byte0]: 60
3428 23:42:24.675148 [Byte1]: 60
3429 23:42:24.675228
3430 23:42:24.675308 Set Vref, RX VrefLevel [Byte0]: 61
3431 23:42:24.675389 [Byte1]: 61
3432 23:42:24.675470
3433 23:42:24.675550 Set Vref, RX VrefLevel [Byte0]: 62
3434 23:42:24.675631 [Byte1]: 62
3435 23:42:24.675725
3436 23:42:24.675808 Set Vref, RX VrefLevel [Byte0]: 63
3437 23:42:24.675890 [Byte1]: 63
3438 23:42:24.675970
3439 23:42:24.676051 Set Vref, RX VrefLevel [Byte0]: 64
3440 23:42:24.676132 [Byte1]: 64
3441 23:42:24.676229
3442 23:42:24.676353 Set Vref, RX VrefLevel [Byte0]: 65
3443 23:42:24.676434 [Byte1]: 65
3444 23:42:24.676523
3445 23:42:24.676618 Final RX Vref Byte 0 = 51 to rank0
3446 23:42:24.676704 Final RX Vref Byte 1 = 52 to rank0
3447 23:42:24.676786 Final RX Vref Byte 0 = 51 to rank1
3448 23:42:24.676868 Final RX Vref Byte 1 = 52 to rank1==
3449 23:42:24.676950 Dram Type= 6, Freq= 0, CH_1, rank 0
3450 23:42:24.677059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3451 23:42:24.677141 ==
3452 23:42:24.677222 DQS Delay:
3453 23:42:24.677333 DQS0 = 0, DQS1 = 0
3454 23:42:24.677420 DQM Delay:
3455 23:42:24.677501 DQM0 = 114, DQM1 = 113
3456 23:42:24.677582 DQ Delay:
3457 23:42:24.677663 DQ0 =120, DQ1 =108, DQ2 =106, DQ3 =114
3458 23:42:24.677745 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3459 23:42:24.677826 DQ8 =98, DQ9 =104, DQ10 =114, DQ11 =106
3460 23:42:24.677908 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =122
3461 23:42:24.677988
3462 23:42:24.678073
3463 23:42:24.678165 [DQSOSCAuto] RK0, (LSB)MR18= 0xf804, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3464 23:42:24.678230 CH1 RK0: MR19=304, MR18=F804
3465 23:42:24.678483 CH1_RK0: MR19=0x304, MR18=0xF804, DQSOSC=408, MR23=63, INC=39, DEC=26
3466 23:42:24.678546
3467 23:42:24.678599 ----->DramcWriteLeveling(PI) begin...
3468 23:42:24.678653 ==
3469 23:42:24.678705 Dram Type= 6, Freq= 0, CH_1, rank 1
3470 23:42:24.678757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3471 23:42:24.678810 ==
3472 23:42:24.678862 Write leveling (Byte 0): 23 => 23
3473 23:42:24.678915 Write leveling (Byte 1): 28 => 28
3474 23:42:24.678966 DramcWriteLeveling(PI) end<-----
3475 23:42:24.679018
3476 23:42:24.679069 ==
3477 23:42:24.679122 Dram Type= 6, Freq= 0, CH_1, rank 1
3478 23:42:24.679174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3479 23:42:24.679226 ==
3480 23:42:24.679278 [Gating] SW mode calibration
3481 23:42:24.679330 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3482 23:42:24.679382 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3483 23:42:24.679434 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3484 23:42:24.679486 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3485 23:42:24.679546 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3486 23:42:24.679638 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3487 23:42:24.679722 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3488 23:42:24.679805 0 15 20 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
3489 23:42:24.679886 0 15 24 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
3490 23:42:24.679968 0 15 28 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
3491 23:42:24.680050 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3492 23:42:24.680131 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3493 23:42:24.680213 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3494 23:42:24.680295 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3495 23:42:24.680377 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3496 23:42:24.680458 1 0 20 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
3497 23:42:24.680540 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3498 23:42:24.680622 1 0 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3499 23:42:24.680703 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3500 23:42:24.680785 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3501 23:42:24.680869 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3502 23:42:24.680967 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3503 23:42:24.681051 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 23:42:24.681133 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 23:42:24.681215 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3506 23:42:24.681309 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3507 23:42:24.681364 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3508 23:42:24.681417 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3509 23:42:24.681469 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3510 23:42:24.681522 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3511 23:42:24.681574 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3512 23:42:24.681626 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3513 23:42:24.681679 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 23:42:24.681730 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 23:42:24.681782 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 23:42:24.681834 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 23:42:24.681886 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 23:42:24.681938 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 23:42:24.681990 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 23:42:24.682042 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 23:42:24.682094 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3522 23:42:24.682147 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3523 23:42:24.682198 Total UI for P1: 0, mck2ui 16
3524 23:42:24.682251 best dqsien dly found for B0: ( 1, 3, 24)
3525 23:42:24.682304 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 23:42:24.682384 Total UI for P1: 0, mck2ui 16
3527 23:42:24.682443 best dqsien dly found for B1: ( 1, 3, 28)
3528 23:42:24.682496 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3529 23:42:24.682549 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3530 23:42:24.682601
3531 23:42:24.682652 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3532 23:42:24.682704 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3533 23:42:24.682756 [Gating] SW calibration Done
3534 23:42:24.682809 ==
3535 23:42:24.682861 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 23:42:24.682913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 23:42:24.682965 ==
3538 23:42:24.683018 RX Vref Scan: 0
3539 23:42:24.683069
3540 23:42:24.683121 RX Vref 0 -> 0, step: 1
3541 23:42:24.683190
3542 23:42:24.683282 RX Delay -40 -> 252, step: 8
3543 23:42:24.683339 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3544 23:42:24.683392 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3545 23:42:24.683445 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3546 23:42:24.683497 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3547 23:42:24.683550 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3548 23:42:24.683602 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3549 23:42:24.683653 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3550 23:42:24.683705 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3551 23:42:24.683757 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3552 23:42:24.683809 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3553 23:42:24.683862 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3554 23:42:24.683914 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3555 23:42:24.683967 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3556 23:42:24.684050 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3557 23:42:24.684103 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3558 23:42:24.684155 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3559 23:42:24.684207 ==
3560 23:42:24.684259 Dram Type= 6, Freq= 0, CH_1, rank 1
3561 23:42:24.684311 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3562 23:42:24.684363 ==
3563 23:42:24.684414 DQS Delay:
3564 23:42:24.684466 DQS0 = 0, DQS1 = 0
3565 23:42:24.684518 DQM Delay:
3566 23:42:24.684569 DQM0 = 114, DQM1 = 111
3567 23:42:24.684621 DQ Delay:
3568 23:42:24.684673 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3569 23:42:24.684921 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =111
3570 23:42:24.684979 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3571 23:42:24.685032 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3572 23:42:24.685085
3573 23:42:24.685136
3574 23:42:24.685188 ==
3575 23:42:24.685240 Dram Type= 6, Freq= 0, CH_1, rank 1
3576 23:42:24.685335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3577 23:42:24.685389 ==
3578 23:42:24.685441
3579 23:42:24.685493
3580 23:42:24.685544 TX Vref Scan disable
3581 23:42:24.685597 == TX Byte 0 ==
3582 23:42:24.685649 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3583 23:42:24.685701 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3584 23:42:24.685753 == TX Byte 1 ==
3585 23:42:24.685805 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3586 23:42:24.685858 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3587 23:42:24.685909 ==
3588 23:42:24.685961 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 23:42:24.686013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 23:42:24.686066 ==
3591 23:42:24.686117 TX Vref=22, minBit 2, minWin=25, winSum=419
3592 23:42:24.686170 TX Vref=24, minBit 9, minWin=25, winSum=425
3593 23:42:24.686221 TX Vref=26, minBit 3, minWin=26, winSum=426
3594 23:42:24.686274 TX Vref=28, minBit 2, minWin=26, winSum=430
3595 23:42:24.686356 TX Vref=30, minBit 3, minWin=26, winSum=435
3596 23:42:24.686408 TX Vref=32, minBit 8, minWin=26, winSum=434
3597 23:42:24.686460 [TxChooseVref] Worse bit 3, Min win 26, Win sum 435, Final Vref 30
3598 23:42:24.686518
3599 23:42:24.686569 Final TX Range 1 Vref 30
3600 23:42:24.686621
3601 23:42:24.686673 ==
3602 23:42:24.686724 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 23:42:24.686777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 23:42:24.686828 ==
3605 23:42:24.686880
3606 23:42:24.686931
3607 23:42:24.686982 TX Vref Scan disable
3608 23:42:24.687034 == TX Byte 0 ==
3609 23:42:24.687086 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3610 23:42:24.687139 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3611 23:42:24.687191 == TX Byte 1 ==
3612 23:42:24.687243 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3613 23:42:24.687294 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3614 23:42:24.687346
3615 23:42:24.687398 [DATLAT]
3616 23:42:24.687449 Freq=1200, CH1 RK1
3617 23:42:24.687500
3618 23:42:24.687551 DATLAT Default: 0xd
3619 23:42:24.687603 0, 0xFFFF, sum = 0
3620 23:42:24.687656 1, 0xFFFF, sum = 0
3621 23:42:24.687709 2, 0xFFFF, sum = 0
3622 23:42:24.687761 3, 0xFFFF, sum = 0
3623 23:42:24.687814 4, 0xFFFF, sum = 0
3624 23:42:24.687866 5, 0xFFFF, sum = 0
3625 23:42:24.687934 6, 0xFFFF, sum = 0
3626 23:42:24.688000 7, 0xFFFF, sum = 0
3627 23:42:24.688053 8, 0xFFFF, sum = 0
3628 23:42:24.688106 9, 0xFFFF, sum = 0
3629 23:42:24.688158 10, 0xFFFF, sum = 0
3630 23:42:24.688211 11, 0xFFFF, sum = 0
3631 23:42:24.688263 12, 0x0, sum = 1
3632 23:42:24.688316 13, 0x0, sum = 2
3633 23:42:24.688368 14, 0x0, sum = 3
3634 23:42:24.688421 15, 0x0, sum = 4
3635 23:42:24.688473 best_step = 13
3636 23:42:24.688525
3637 23:42:24.688577 ==
3638 23:42:24.688628 Dram Type= 6, Freq= 0, CH_1, rank 1
3639 23:42:24.688681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3640 23:42:24.688733 ==
3641 23:42:24.688786 RX Vref Scan: 0
3642 23:42:24.688838
3643 23:42:24.688890 RX Vref 0 -> 0, step: 1
3644 23:42:24.688941
3645 23:42:24.688993 RX Delay -13 -> 252, step: 4
3646 23:42:24.689045 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3647 23:42:24.689097 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3648 23:42:24.689150 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3649 23:42:24.689202 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3650 23:42:24.689254 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3651 23:42:24.689349 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3652 23:42:24.689402 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3653 23:42:24.689454 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3654 23:42:24.689506 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3655 23:42:24.689558 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3656 23:42:24.689610 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3657 23:42:24.689663 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3658 23:42:24.689715 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3659 23:42:24.689767 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3660 23:42:24.689819 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3661 23:42:24.689871 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3662 23:42:24.689924 ==
3663 23:42:24.689975 Dram Type= 6, Freq= 0, CH_1, rank 1
3664 23:42:24.690027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3665 23:42:24.690080 ==
3666 23:42:24.690131 DQS Delay:
3667 23:42:24.690183 DQS0 = 0, DQS1 = 0
3668 23:42:24.690234 DQM Delay:
3669 23:42:24.690286 DQM0 = 115, DQM1 = 112
3670 23:42:24.690338 DQ Delay:
3671 23:42:24.690390 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3672 23:42:24.690442 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3673 23:42:24.690494 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3674 23:42:24.690546 DQ12 =120, DQ13 =118, DQ14 =118, DQ15 =122
3675 23:42:24.690598
3676 23:42:24.690650
3677 23:42:24.690701 [DQSOSCAuto] RK1, (LSB)MR18= 0xf70a, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
3678 23:42:24.690754 CH1 RK1: MR19=304, MR18=F70A
3679 23:42:24.690806 CH1_RK1: MR19=0x304, MR18=0xF70A, DQSOSC=406, MR23=63, INC=39, DEC=26
3680 23:42:24.690859 [RxdqsGatingPostProcess] freq 1200
3681 23:42:24.690912 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3682 23:42:24.690964 best DQS0 dly(2T, 0.5T) = (0, 11)
3683 23:42:24.691016 best DQS1 dly(2T, 0.5T) = (0, 11)
3684 23:42:24.691068 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3685 23:42:24.691120 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3686 23:42:24.691172 best DQS0 dly(2T, 0.5T) = (0, 11)
3687 23:42:24.691224 best DQS1 dly(2T, 0.5T) = (0, 11)
3688 23:42:24.691276 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3689 23:42:24.691328 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3690 23:42:24.691380 Pre-setting of DQS Precalculation
3691 23:42:24.691432 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3692 23:42:24.691485 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3693 23:42:24.691538 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3694 23:42:24.691590
3695 23:42:24.691641
3696 23:42:24.691692 [Calibration Summary] 2400 Mbps
3697 23:42:24.691744 CH 0, Rank 0
3698 23:42:24.691795 SW Impedance : PASS
3699 23:42:24.691885 DUTY Scan : NO K
3700 23:42:24.691937 ZQ Calibration : PASS
3701 23:42:24.691988 Jitter Meter : NO K
3702 23:42:24.692040 CBT Training : PASS
3703 23:42:24.692092 Write leveling : PASS
3704 23:42:24.692144 RX DQS gating : PASS
3705 23:42:24.692196 RX DQ/DQS(RDDQC) : PASS
3706 23:42:24.692247 TX DQ/DQS : PASS
3707 23:42:24.692298 RX DATLAT : PASS
3708 23:42:24.692350 RX DQ/DQS(Engine): PASS
3709 23:42:24.692593 TX OE : NO K
3710 23:42:24.692652 All Pass.
3711 23:42:24.692705
3712 23:42:24.692757 CH 0, Rank 1
3713 23:42:24.692808 SW Impedance : PASS
3714 23:42:24.692860 DUTY Scan : NO K
3715 23:42:24.692911 ZQ Calibration : PASS
3716 23:42:24.692963 Jitter Meter : NO K
3717 23:42:24.693015 CBT Training : PASS
3718 23:42:24.693067 Write leveling : PASS
3719 23:42:24.693118 RX DQS gating : PASS
3720 23:42:24.693170 RX DQ/DQS(RDDQC) : PASS
3721 23:42:24.693239 TX DQ/DQS : PASS
3722 23:42:24.693314 RX DATLAT : PASS
3723 23:42:24.693367 RX DQ/DQS(Engine): PASS
3724 23:42:24.693419 TX OE : NO K
3725 23:42:24.693471 All Pass.
3726 23:42:24.693523
3727 23:42:24.693575 CH 1, Rank 0
3728 23:42:24.693625 SW Impedance : PASS
3729 23:42:24.693677 DUTY Scan : NO K
3730 23:42:24.693729 ZQ Calibration : PASS
3731 23:42:24.693781 Jitter Meter : NO K
3732 23:42:24.693832 CBT Training : PASS
3733 23:42:24.693884 Write leveling : PASS
3734 23:42:24.693935 RX DQS gating : PASS
3735 23:42:24.693987 RX DQ/DQS(RDDQC) : PASS
3736 23:42:24.694039 TX DQ/DQS : PASS
3737 23:42:24.694091 RX DATLAT : PASS
3738 23:42:24.694142 RX DQ/DQS(Engine): PASS
3739 23:42:24.694194 TX OE : NO K
3740 23:42:24.694246 All Pass.
3741 23:42:24.694297
3742 23:42:24.694348 CH 1, Rank 1
3743 23:42:24.694400 SW Impedance : PASS
3744 23:42:24.694451 DUTY Scan : NO K
3745 23:42:24.694502 ZQ Calibration : PASS
3746 23:42:24.694553 Jitter Meter : NO K
3747 23:42:24.694605 CBT Training : PASS
3748 23:42:24.694657 Write leveling : PASS
3749 23:42:24.694709 RX DQS gating : PASS
3750 23:42:24.694760 RX DQ/DQS(RDDQC) : PASS
3751 23:42:24.694812 TX DQ/DQS : PASS
3752 23:42:24.694864 RX DATLAT : PASS
3753 23:42:24.694915 RX DQ/DQS(Engine): PASS
3754 23:42:24.694967 TX OE : NO K
3755 23:42:24.695018 All Pass.
3756 23:42:24.695070
3757 23:42:24.695121 DramC Write-DBI off
3758 23:42:24.695173 PER_BANK_REFRESH: Hybrid Mode
3759 23:42:24.695225 TX_TRACKING: ON
3760 23:42:24.695276 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3761 23:42:24.695329 [FAST_K] Save calibration result to emmc
3762 23:42:24.695381 dramc_set_vcore_voltage set vcore to 650000
3763 23:42:24.695433 Read voltage for 600, 5
3764 23:42:24.695485 Vio18 = 0
3765 23:42:24.695538 Vcore = 650000
3766 23:42:24.695588 Vdram = 0
3767 23:42:24.695640 Vddq = 0
3768 23:42:24.695691 Vmddr = 0
3769 23:42:24.695742 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3770 23:42:24.695795 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3771 23:42:24.695847 MEM_TYPE=3, freq_sel=19
3772 23:42:24.695898 sv_algorithm_assistance_LP4_1600
3773 23:42:24.695950 ============ PULL DRAM RESETB DOWN ============
3774 23:42:24.696003 ========== PULL DRAM RESETB DOWN end =========
3775 23:42:24.696055 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3776 23:42:24.696107 ===================================
3777 23:42:24.696159 LPDDR4 DRAM CONFIGURATION
3778 23:42:24.696212 ===================================
3779 23:42:24.696264 EX_ROW_EN[0] = 0x0
3780 23:42:24.696316 EX_ROW_EN[1] = 0x0
3781 23:42:24.696368 LP4Y_EN = 0x0
3782 23:42:24.696419 WORK_FSP = 0x0
3783 23:42:24.696471 WL = 0x2
3784 23:42:24.696523 RL = 0x2
3785 23:42:24.696574 BL = 0x2
3786 23:42:24.696625 RPST = 0x0
3787 23:42:24.696677 RD_PRE = 0x0
3788 23:42:24.696728 WR_PRE = 0x1
3789 23:42:24.696779 WR_PST = 0x0
3790 23:42:24.696830 DBI_WR = 0x0
3791 23:42:24.696882 DBI_RD = 0x0
3792 23:42:24.696933 OTF = 0x1
3793 23:42:24.696985 ===================================
3794 23:42:24.697037 ===================================
3795 23:42:24.697088 ANA top config
3796 23:42:24.697140 ===================================
3797 23:42:24.697192 DLL_ASYNC_EN = 0
3798 23:42:24.697244 ALL_SLAVE_EN = 1
3799 23:42:24.697350 NEW_RANK_MODE = 1
3800 23:42:24.697404 DLL_IDLE_MODE = 1
3801 23:42:24.697457 LP45_APHY_COMB_EN = 1
3802 23:42:24.697509 TX_ODT_DIS = 1
3803 23:42:24.697560 NEW_8X_MODE = 1
3804 23:42:24.697613 ===================================
3805 23:42:24.697666 ===================================
3806 23:42:24.697719 data_rate = 1200
3807 23:42:24.697771 CKR = 1
3808 23:42:24.697823 DQ_P2S_RATIO = 8
3809 23:42:24.697875 ===================================
3810 23:42:24.697927 CA_P2S_RATIO = 8
3811 23:42:24.697979 DQ_CA_OPEN = 0
3812 23:42:24.698030 DQ_SEMI_OPEN = 0
3813 23:42:24.698082 CA_SEMI_OPEN = 0
3814 23:42:24.698134 CA_FULL_RATE = 0
3815 23:42:24.698186 DQ_CKDIV4_EN = 1
3816 23:42:24.698237 CA_CKDIV4_EN = 1
3817 23:42:24.698289 CA_PREDIV_EN = 0
3818 23:42:24.698341 PH8_DLY = 0
3819 23:42:24.698392 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3820 23:42:24.698444 DQ_AAMCK_DIV = 4
3821 23:42:24.698495 CA_AAMCK_DIV = 4
3822 23:42:24.698547 CA_ADMCK_DIV = 4
3823 23:42:24.698601 DQ_TRACK_CA_EN = 0
3824 23:42:24.698656 CA_PICK = 600
3825 23:42:24.698710 CA_MCKIO = 600
3826 23:42:24.698765 MCKIO_SEMI = 0
3827 23:42:24.698820 PLL_FREQ = 2288
3828 23:42:24.698887 DQ_UI_PI_RATIO = 32
3829 23:42:24.698970 CA_UI_PI_RATIO = 0
3830 23:42:24.699052 ===================================
3831 23:42:24.699135 ===================================
3832 23:42:24.699217 memory_type:LPDDR4
3833 23:42:24.699298 GP_NUM : 10
3834 23:42:24.699382 SRAM_EN : 1
3835 23:42:24.699463 MD32_EN : 0
3836 23:42:24.699541 ===================================
3837 23:42:24.699595 [ANA_INIT] >>>>>>>>>>>>>>
3838 23:42:24.699648 <<<<<< [CONFIGURE PHASE]: ANA_TX
3839 23:42:24.699700 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3840 23:42:24.699755 ===================================
3841 23:42:24.699807 data_rate = 1200,PCW = 0X5800
3842 23:42:24.699860 ===================================
3843 23:42:24.699912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3844 23:42:24.699965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3845 23:42:24.700017 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3846 23:42:24.700070 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3847 23:42:24.700122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3848 23:42:24.700174 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3849 23:42:24.700225 [ANA_INIT] flow start
3850 23:42:24.700277 [ANA_INIT] PLL >>>>>>>>
3851 23:42:24.700329 [ANA_INIT] PLL <<<<<<<<
3852 23:42:24.700570 [ANA_INIT] MIDPI >>>>>>>>
3853 23:42:24.700632 [ANA_INIT] MIDPI <<<<<<<<
3854 23:42:24.700684 [ANA_INIT] DLL >>>>>>>>
3855 23:42:24.700736 [ANA_INIT] flow end
3856 23:42:24.700788 ============ LP4 DIFF to SE enter ============
3857 23:42:24.700840 ============ LP4 DIFF to SE exit ============
3858 23:42:24.700893 [ANA_INIT] <<<<<<<<<<<<<
3859 23:42:24.700945 [Flow] Enable top DCM control >>>>>
3860 23:42:24.700997 [Flow] Enable top DCM control <<<<<
3861 23:42:24.701049 Enable DLL master slave shuffle
3862 23:42:24.701101 ==============================================================
3863 23:42:24.701154 Gating Mode config
3864 23:42:24.703053 ==============================================================
3865 23:42:24.706423 Config description:
3866 23:42:24.716221 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3867 23:42:24.722628 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3868 23:42:24.726164 SELPH_MODE 0: By rank 1: By Phase
3869 23:42:24.732666 ==============================================================
3870 23:42:24.735719 GAT_TRACK_EN = 1
3871 23:42:24.738907 RX_GATING_MODE = 2
3872 23:42:24.739017 RX_GATING_TRACK_MODE = 2
3873 23:42:24.742433 SELPH_MODE = 1
3874 23:42:24.745724 PICG_EARLY_EN = 1
3875 23:42:24.749183 VALID_LAT_VALUE = 1
3876 23:42:24.755345 ==============================================================
3877 23:42:24.759079 Enter into Gating configuration >>>>
3878 23:42:24.762150 Exit from Gating configuration <<<<
3879 23:42:24.765222 Enter into DVFS_PRE_config >>>>>
3880 23:42:24.775074 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3881 23:42:24.778284 Exit from DVFS_PRE_config <<<<<
3882 23:42:24.781712 Enter into PICG configuration >>>>
3883 23:42:24.785714 Exit from PICG configuration <<<<
3884 23:42:24.788344 [RX_INPUT] configuration >>>>>
3885 23:42:24.791538 [RX_INPUT] configuration <<<<<
3886 23:42:24.795228 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3887 23:42:24.801417 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3888 23:42:24.808134 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3889 23:42:24.814723 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3890 23:42:24.820933 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3891 23:42:24.827810 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3892 23:42:24.830931 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3893 23:42:24.834837 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3894 23:42:24.837748 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3895 23:42:24.844589 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3896 23:42:24.848001 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3897 23:42:24.851095 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3898 23:42:24.854198 ===================================
3899 23:42:24.857799 LPDDR4 DRAM CONFIGURATION
3900 23:42:24.861313 ===================================
3901 23:42:24.861398 EX_ROW_EN[0] = 0x0
3902 23:42:24.864280 EX_ROW_EN[1] = 0x0
3903 23:42:24.864361 LP4Y_EN = 0x0
3904 23:42:24.867703 WORK_FSP = 0x0
3905 23:42:24.870757 WL = 0x2
3906 23:42:24.870838 RL = 0x2
3907 23:42:24.873969 BL = 0x2
3908 23:42:24.874049 RPST = 0x0
3909 23:42:24.877706 RD_PRE = 0x0
3910 23:42:24.877806 WR_PRE = 0x1
3911 23:42:24.880712 WR_PST = 0x0
3912 23:42:24.880792 DBI_WR = 0x0
3913 23:42:24.883849 DBI_RD = 0x0
3914 23:42:24.883929 OTF = 0x1
3915 23:42:24.887481 ===================================
3916 23:42:24.890725 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3917 23:42:24.897356 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3918 23:42:24.900517 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3919 23:42:24.904094 ===================================
3920 23:42:24.906931 LPDDR4 DRAM CONFIGURATION
3921 23:42:24.910331 ===================================
3922 23:42:24.910415 EX_ROW_EN[0] = 0x10
3923 23:42:24.913451 EX_ROW_EN[1] = 0x0
3924 23:42:24.916823 LP4Y_EN = 0x0
3925 23:42:24.916905 WORK_FSP = 0x0
3926 23:42:24.919843 WL = 0x2
3927 23:42:24.919926 RL = 0x2
3928 23:42:24.923354 BL = 0x2
3929 23:42:24.923453 RPST = 0x0
3930 23:42:24.927051 RD_PRE = 0x0
3931 23:42:24.927132 WR_PRE = 0x1
3932 23:42:24.929913 WR_PST = 0x0
3933 23:42:24.929994 DBI_WR = 0x0
3934 23:42:24.933365 DBI_RD = 0x0
3935 23:42:24.933446 OTF = 0x1
3936 23:42:24.936691 ===================================
3937 23:42:24.943248 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3938 23:42:24.947404 nWR fixed to 30
3939 23:42:24.950722 [ModeRegInit_LP4] CH0 RK0
3940 23:42:24.950825 [ModeRegInit_LP4] CH0 RK1
3941 23:42:24.954279 [ModeRegInit_LP4] CH1 RK0
3942 23:42:24.957221 [ModeRegInit_LP4] CH1 RK1
3943 23:42:24.957320 match AC timing 17
3944 23:42:24.964058 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3945 23:42:24.967383 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3946 23:42:24.970521 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3947 23:42:24.977157 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3948 23:42:24.980635 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3949 23:42:24.980719 ==
3950 23:42:24.983750 Dram Type= 6, Freq= 0, CH_0, rank 0
3951 23:42:24.987003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3952 23:42:24.987085 ==
3953 23:42:24.993745 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3954 23:42:25.000160 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3955 23:42:25.003648 [CA 0] Center 36 (6~67) winsize 62
3956 23:42:25.006851 [CA 1] Center 36 (6~67) winsize 62
3957 23:42:25.010731 [CA 2] Center 34 (4~65) winsize 62
3958 23:42:25.013507 [CA 3] Center 34 (3~65) winsize 63
3959 23:42:25.016675 [CA 4] Center 33 (3~64) winsize 62
3960 23:42:25.019968 [CA 5] Center 33 (3~64) winsize 62
3961 23:42:25.020050
3962 23:42:25.023870 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3963 23:42:25.023953
3964 23:42:25.026721 [CATrainingPosCal] consider 1 rank data
3965 23:42:25.030325 u2DelayCellTimex100 = 270/100 ps
3966 23:42:25.033577 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3967 23:42:25.036886 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3968 23:42:25.040198 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3969 23:42:25.043622 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3970 23:42:25.050124 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3971 23:42:25.053624 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3972 23:42:25.053707
3973 23:42:25.056784 CA PerBit enable=1, Macro0, CA PI delay=33
3974 23:42:25.056866
3975 23:42:25.059856 [CBTSetCACLKResult] CA Dly = 33
3976 23:42:25.059938 CS Dly: 5 (0~36)
3977 23:42:25.060003 ==
3978 23:42:25.063434 Dram Type= 6, Freq= 0, CH_0, rank 1
3979 23:42:25.069704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3980 23:42:25.069787 ==
3981 23:42:25.073139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3982 23:42:25.079979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3983 23:42:25.083416 [CA 0] Center 36 (6~67) winsize 62
3984 23:42:25.086280 [CA 1] Center 36 (6~67) winsize 62
3985 23:42:25.089620 [CA 2] Center 34 (4~65) winsize 62
3986 23:42:25.092691 [CA 3] Center 34 (4~65) winsize 62
3987 23:42:25.096150 [CA 4] Center 34 (3~65) winsize 63
3988 23:42:25.099583 [CA 5] Center 34 (3~65) winsize 63
3989 23:42:25.099707
3990 23:42:25.102682 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3991 23:42:25.102792
3992 23:42:25.105956 [CATrainingPosCal] consider 2 rank data
3993 23:42:25.109630 u2DelayCellTimex100 = 270/100 ps
3994 23:42:25.112384 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3995 23:42:25.119196 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3996 23:42:25.122429 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3997 23:42:25.125801 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3998 23:42:25.129370 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3999 23:42:25.132361 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4000 23:42:25.132443
4001 23:42:25.136087 CA PerBit enable=1, Macro0, CA PI delay=33
4002 23:42:25.136168
4003 23:42:25.139269 [CBTSetCACLKResult] CA Dly = 33
4004 23:42:25.142524 CS Dly: 6 (0~38)
4005 23:42:25.142605
4006 23:42:25.145678 ----->DramcWriteLeveling(PI) begin...
4007 23:42:25.145760 ==
4008 23:42:25.149191 Dram Type= 6, Freq= 0, CH_0, rank 0
4009 23:42:25.152314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4010 23:42:25.152421 ==
4011 23:42:25.155610 Write leveling (Byte 0): 33 => 33
4012 23:42:25.159022 Write leveling (Byte 1): 29 => 29
4013 23:42:25.162315 DramcWriteLeveling(PI) end<-----
4014 23:42:25.162418
4015 23:42:25.162556 ==
4016 23:42:25.165340 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 23:42:25.168701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 23:42:25.168802 ==
4019 23:42:25.172309 [Gating] SW mode calibration
4020 23:42:25.178850 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4021 23:42:25.185226 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4022 23:42:25.188498 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4023 23:42:25.191853 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4024 23:42:25.198261 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4025 23:42:25.201809 0 9 12 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)
4026 23:42:25.204759 0 9 16 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
4027 23:42:25.211356 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4028 23:42:25.215061 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4029 23:42:25.218195 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4030 23:42:25.224649 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4031 23:42:25.228080 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4032 23:42:25.231548 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4033 23:42:25.238179 0 10 12 | B1->B0 | 2424 2525 | 0 1 | (1 1) (0 0)
4034 23:42:25.241159 0 10 16 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
4035 23:42:25.244704 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4036 23:42:25.251272 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4037 23:42:25.254222 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4038 23:42:25.257753 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 23:42:25.264028 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 23:42:25.267675 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4041 23:42:25.271369 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4042 23:42:25.277781 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4043 23:42:25.280728 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4044 23:42:25.283929 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4045 23:42:25.290945 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4046 23:42:25.294299 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4047 23:42:25.298059 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4048 23:42:25.303969 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4049 23:42:25.307040 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 23:42:25.310416 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 23:42:25.317193 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 23:42:25.320523 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 23:42:25.323452 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 23:42:25.330617 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 23:42:25.333675 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 23:42:25.336392 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 23:42:25.343435 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 23:42:25.346339 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4059 23:42:25.349758 Total UI for P1: 0, mck2ui 16
4060 23:42:25.353100 best dqsien dly found for B0: ( 0, 13, 14)
4061 23:42:25.356332 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 23:42:25.359933 Total UI for P1: 0, mck2ui 16
4063 23:42:25.362819 best dqsien dly found for B1: ( 0, 13, 18)
4064 23:42:25.366451 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4065 23:42:25.372990 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4066 23:42:25.373072
4067 23:42:25.375976 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4068 23:42:25.379462 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4069 23:42:25.383044 [Gating] SW calibration Done
4070 23:42:25.383133 ==
4071 23:42:25.385745 Dram Type= 6, Freq= 0, CH_0, rank 0
4072 23:42:25.389833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4073 23:42:25.389915 ==
4074 23:42:25.392693 RX Vref Scan: 0
4075 23:42:25.392773
4076 23:42:25.392835 RX Vref 0 -> 0, step: 1
4077 23:42:25.392894
4078 23:42:25.396039 RX Delay -230 -> 252, step: 16
4079 23:42:25.399545 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4080 23:42:25.406161 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4081 23:42:25.408930 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4082 23:42:25.412738 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4083 23:42:25.415492 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4084 23:42:25.422399 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4085 23:42:25.425779 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4086 23:42:25.428853 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4087 23:42:25.432218 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4088 23:42:25.438771 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4089 23:42:25.442396 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4090 23:42:25.445032 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4091 23:42:25.448497 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4092 23:42:25.455153 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4093 23:42:25.458679 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4094 23:42:25.461596 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4095 23:42:25.461693 ==
4096 23:42:25.465253 Dram Type= 6, Freq= 0, CH_0, rank 0
4097 23:42:25.468334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4098 23:42:25.471807 ==
4099 23:42:25.471889 DQS Delay:
4100 23:42:25.471953 DQS0 = 0, DQS1 = 0
4101 23:42:25.474657 DQM Delay:
4102 23:42:25.474749 DQM0 = 47, DQM1 = 36
4103 23:42:25.478013 DQ Delay:
4104 23:42:25.478122 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =41
4105 23:42:25.481664 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4106 23:42:25.484626 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4107 23:42:25.488037 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4108 23:42:25.491362
4109 23:42:25.491442
4110 23:42:25.491505 ==
4111 23:42:25.494613 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 23:42:25.498034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 23:42:25.498129 ==
4114 23:42:25.498229
4115 23:42:25.498288
4116 23:42:25.501504 TX Vref Scan disable
4117 23:42:25.501584 == TX Byte 0 ==
4118 23:42:25.508079 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4119 23:42:25.511012 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4120 23:42:25.511121 == TX Byte 1 ==
4121 23:42:25.517677 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4122 23:42:25.521105 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4123 23:42:25.521215 ==
4124 23:42:25.524506 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 23:42:25.527910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 23:42:25.527986 ==
4127 23:42:25.528048
4128 23:42:25.530737
4129 23:42:25.530820 TX Vref Scan disable
4130 23:42:25.534600 == TX Byte 0 ==
4131 23:42:25.537493 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4132 23:42:25.544498 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4133 23:42:25.544599 == TX Byte 1 ==
4134 23:42:25.547487 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4135 23:42:25.553816 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4136 23:42:25.553929
4137 23:42:25.554039 [DATLAT]
4138 23:42:25.554127 Freq=600, CH0 RK0
4139 23:42:25.554229
4140 23:42:25.557305 DATLAT Default: 0x9
4141 23:42:25.560389 0, 0xFFFF, sum = 0
4142 23:42:25.560464 1, 0xFFFF, sum = 0
4143 23:42:25.564114 2, 0xFFFF, sum = 0
4144 23:42:25.564197 3, 0xFFFF, sum = 0
4145 23:42:25.566910 4, 0xFFFF, sum = 0
4146 23:42:25.567030 5, 0xFFFF, sum = 0
4147 23:42:25.570560 6, 0xFFFF, sum = 0
4148 23:42:25.570663 7, 0xFFFF, sum = 0
4149 23:42:25.573540 8, 0x0, sum = 1
4150 23:42:25.573623 9, 0x0, sum = 2
4151 23:42:25.577093 10, 0x0, sum = 3
4152 23:42:25.577176 11, 0x0, sum = 4
4153 23:42:25.577241 best_step = 9
4154 23:42:25.580516
4155 23:42:25.580635 ==
4156 23:42:25.583781 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 23:42:25.586962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 23:42:25.587047 ==
4159 23:42:25.587116 RX Vref Scan: 1
4160 23:42:25.587176
4161 23:42:25.590400 RX Vref 0 -> 0, step: 1
4162 23:42:25.590473
4163 23:42:25.593802 RX Delay -195 -> 252, step: 8
4164 23:42:25.593911
4165 23:42:25.596725 Set Vref, RX VrefLevel [Byte0]: 58
4166 23:42:25.599674 [Byte1]: 49
4167 23:42:25.603227
4168 23:42:25.603300 Final RX Vref Byte 0 = 58 to rank0
4169 23:42:25.606596 Final RX Vref Byte 1 = 49 to rank0
4170 23:42:25.609690 Final RX Vref Byte 0 = 58 to rank1
4171 23:42:25.613012 Final RX Vref Byte 1 = 49 to rank1==
4172 23:42:25.616574 Dram Type= 6, Freq= 0, CH_0, rank 0
4173 23:42:25.623125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4174 23:42:25.623209 ==
4175 23:42:25.623274 DQS Delay:
4176 23:42:25.626542 DQS0 = 0, DQS1 = 0
4177 23:42:25.626624 DQM Delay:
4178 23:42:25.626688 DQM0 = 44, DQM1 = 37
4179 23:42:25.629837 DQ Delay:
4180 23:42:25.632572 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4181 23:42:25.635818 DQ4 =48, DQ5 =36, DQ6 =52, DQ7 =48
4182 23:42:25.639338 DQ8 =28, DQ9 =28, DQ10 =36, DQ11 =32
4183 23:42:25.642545 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4184 23:42:25.642627
4185 23:42:25.642691
4186 23:42:25.649275 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b43, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 395 ps
4187 23:42:25.652808 CH0 RK0: MR19=808, MR18=4B43
4188 23:42:25.659456 CH0_RK0: MR19=0x808, MR18=0x4B43, DQSOSC=395, MR23=63, INC=168, DEC=112
4189 23:42:25.659542
4190 23:42:25.662684 ----->DramcWriteLeveling(PI) begin...
4191 23:42:25.662768 ==
4192 23:42:25.665440 Dram Type= 6, Freq= 0, CH_0, rank 1
4193 23:42:25.669016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4194 23:42:25.669098 ==
4195 23:42:25.672214 Write leveling (Byte 0): 33 => 33
4196 23:42:25.675368 Write leveling (Byte 1): 30 => 30
4197 23:42:25.678473 DramcWriteLeveling(PI) end<-----
4198 23:42:25.678556
4199 23:42:25.678652 ==
4200 23:42:25.681801 Dram Type= 6, Freq= 0, CH_0, rank 1
4201 23:42:25.688906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4202 23:42:25.689038 ==
4203 23:42:25.689121 [Gating] SW mode calibration
4204 23:42:25.698492 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4205 23:42:25.701934 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4206 23:42:25.708149 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4207 23:42:25.711848 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4208 23:42:25.715318 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4209 23:42:25.721592 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
4210 23:42:25.725003 0 9 16 | B1->B0 | 3030 2525 | 0 0 | (0 1) (0 0)
4211 23:42:25.728448 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4212 23:42:25.734843 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4213 23:42:25.738418 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4214 23:42:25.741183 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4215 23:42:25.748035 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4216 23:42:25.751142 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4217 23:42:25.754490 0 10 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
4218 23:42:25.760776 0 10 16 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
4219 23:42:25.764083 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4220 23:42:25.767760 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4221 23:42:25.774449 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4222 23:42:25.777631 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4223 23:42:25.780776 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 23:42:25.787435 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 23:42:25.790738 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 23:42:25.794240 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4227 23:42:25.800728 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4228 23:42:25.803680 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4229 23:42:25.807025 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4230 23:42:25.813723 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4231 23:42:25.816744 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4232 23:42:25.820677 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 23:42:25.827051 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 23:42:25.830167 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 23:42:25.833291 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 23:42:25.839955 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 23:42:25.843552 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 23:42:25.846810 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 23:42:25.853379 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 23:42:25.856871 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 23:42:25.859795 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4242 23:42:25.866513 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 23:42:25.866595 Total UI for P1: 0, mck2ui 16
4244 23:42:25.873104 best dqsien dly found for B0: ( 0, 13, 12)
4245 23:42:25.873218 Total UI for P1: 0, mck2ui 16
4246 23:42:25.876024 best dqsien dly found for B1: ( 0, 13, 12)
4247 23:42:25.883049 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4248 23:42:25.886319 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4249 23:42:25.886429
4250 23:42:25.889820 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4251 23:42:25.892951 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4252 23:42:25.896088 [Gating] SW calibration Done
4253 23:42:25.896171 ==
4254 23:42:25.899485 Dram Type= 6, Freq= 0, CH_0, rank 1
4255 23:42:25.902378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 23:42:25.902460 ==
4257 23:42:25.906145 RX Vref Scan: 0
4258 23:42:25.906255
4259 23:42:25.906366 RX Vref 0 -> 0, step: 1
4260 23:42:25.906472
4261 23:42:25.909243 RX Delay -230 -> 252, step: 16
4262 23:42:25.916138 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4263 23:42:25.919079 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4264 23:42:25.922201 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4265 23:42:25.925947 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4266 23:42:25.929187 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4267 23:42:25.935943 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4268 23:42:25.938968 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4269 23:42:25.941993 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4270 23:42:25.945531 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4271 23:42:25.951984 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4272 23:42:25.955251 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4273 23:42:25.958751 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4274 23:42:25.962217 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4275 23:42:25.968851 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4276 23:42:25.971770 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4277 23:42:25.975110 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4278 23:42:25.975192 ==
4279 23:42:25.978208 Dram Type= 6, Freq= 0, CH_0, rank 1
4280 23:42:25.985180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4281 23:42:25.985317 ==
4282 23:42:25.985384 DQS Delay:
4283 23:42:25.985477 DQS0 = 0, DQS1 = 0
4284 23:42:25.988334 DQM Delay:
4285 23:42:25.988419 DQM0 = 43, DQM1 = 36
4286 23:42:25.991444 DQ Delay:
4287 23:42:25.995323 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4288 23:42:25.998249 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4289 23:42:26.001828 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4290 23:42:26.004838 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4291 23:42:26.004919
4292 23:42:26.004982
4293 23:42:26.005040 ==
4294 23:42:26.007884 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 23:42:26.011677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 23:42:26.011786 ==
4297 23:42:26.011879
4298 23:42:26.011965
4299 23:42:26.014969 TX Vref Scan disable
4300 23:42:26.015077 == TX Byte 0 ==
4301 23:42:26.021229 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4302 23:42:26.024135 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4303 23:42:26.027874 == TX Byte 1 ==
4304 23:42:26.031303 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4305 23:42:26.034233 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4306 23:42:26.034314 ==
4307 23:42:26.037445 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 23:42:26.040828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 23:42:26.044458 ==
4310 23:42:26.044539
4311 23:42:26.044601
4312 23:42:26.044660 TX Vref Scan disable
4313 23:42:26.048006 == TX Byte 0 ==
4314 23:42:26.051488 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4315 23:42:26.057936 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4316 23:42:26.058018 == TX Byte 1 ==
4317 23:42:26.061243 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4318 23:42:26.067898 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4319 23:42:26.068011
4320 23:42:26.068146 [DATLAT]
4321 23:42:26.068206 Freq=600, CH0 RK1
4322 23:42:26.068264
4323 23:42:26.070949 DATLAT Default: 0x9
4324 23:42:26.074520 0, 0xFFFF, sum = 0
4325 23:42:26.074602 1, 0xFFFF, sum = 0
4326 23:42:26.077869 2, 0xFFFF, sum = 0
4327 23:42:26.077951 3, 0xFFFF, sum = 0
4328 23:42:26.080745 4, 0xFFFF, sum = 0
4329 23:42:26.080827 5, 0xFFFF, sum = 0
4330 23:42:26.084369 6, 0xFFFF, sum = 0
4331 23:42:26.084451 7, 0xFFFF, sum = 0
4332 23:42:26.087247 8, 0x0, sum = 1
4333 23:42:26.087329 9, 0x0, sum = 2
4334 23:42:26.090912 10, 0x0, sum = 3
4335 23:42:26.090994 11, 0x0, sum = 4
4336 23:42:26.091059 best_step = 9
4337 23:42:26.091145
4338 23:42:26.094246 ==
4339 23:42:26.097640 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 23:42:26.100626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 23:42:26.100708 ==
4342 23:42:26.100771 RX Vref Scan: 0
4343 23:42:26.100830
4344 23:42:26.103662 RX Vref 0 -> 0, step: 1
4345 23:42:26.103743
4346 23:42:26.107406 RX Delay -179 -> 252, step: 8
4347 23:42:26.113977 iDelay=205, Bit 0, Center 44 (-99 ~ 188) 288
4348 23:42:26.116897 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4349 23:42:26.120566 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4350 23:42:26.123474 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4351 23:42:26.126828 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4352 23:42:26.133156 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4353 23:42:26.136597 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4354 23:42:26.140179 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4355 23:42:26.143206 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4356 23:42:26.150366 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4357 23:42:26.153491 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4358 23:42:26.156379 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4359 23:42:26.160031 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4360 23:42:26.166392 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4361 23:42:26.169910 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4362 23:42:26.173216 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4363 23:42:26.173317 ==
4364 23:42:26.176305 Dram Type= 6, Freq= 0, CH_0, rank 1
4365 23:42:26.179733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4366 23:42:26.182683 ==
4367 23:42:26.182792 DQS Delay:
4368 23:42:26.182928 DQS0 = 0, DQS1 = 0
4369 23:42:26.186070 DQM Delay:
4370 23:42:26.186150 DQM0 = 44, DQM1 = 36
4371 23:42:26.189154 DQ Delay:
4372 23:42:26.192869 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4373 23:42:26.192975 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =48
4374 23:42:26.195958 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4375 23:42:26.199369 DQ12 =36, DQ13 =40, DQ14 =48, DQ15 =44
4376 23:42:26.202702
4377 23:42:26.202799
4378 23:42:26.209200 [DQSOSCAuto] RK1, (LSB)MR18= 0x4945, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 396 ps
4379 23:42:26.212625 CH0 RK1: MR19=808, MR18=4945
4380 23:42:26.220194 CH0_RK1: MR19=0x808, MR18=0x4945, DQSOSC=396, MR23=63, INC=167, DEC=111
4381 23:42:26.222348 [RxdqsGatingPostProcess] freq 600
4382 23:42:26.225644 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4383 23:42:26.228941 Pre-setting of DQS Precalculation
4384 23:42:26.235679 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4385 23:42:26.235762 ==
4386 23:42:26.238508 Dram Type= 6, Freq= 0, CH_1, rank 0
4387 23:42:26.241909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4388 23:42:26.241992 ==
4389 23:42:26.248309 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4390 23:42:26.255227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4391 23:42:26.258725 [CA 0] Center 36 (6~66) winsize 61
4392 23:42:26.261377 [CA 1] Center 35 (5~66) winsize 62
4393 23:42:26.264863 [CA 2] Center 34 (4~65) winsize 62
4394 23:42:26.268099 [CA 3] Center 34 (4~65) winsize 62
4395 23:42:26.271535 [CA 4] Center 34 (4~65) winsize 62
4396 23:42:26.274507 [CA 5] Center 34 (3~65) winsize 63
4397 23:42:26.274624
4398 23:42:26.278040 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4399 23:42:26.278122
4400 23:42:26.281417 [CATrainingPosCal] consider 1 rank data
4401 23:42:26.284431 u2DelayCellTimex100 = 270/100 ps
4402 23:42:26.288067 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4403 23:42:26.291759 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4404 23:42:26.294532 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4405 23:42:26.298077 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4406 23:42:26.300883 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4407 23:42:26.304495 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4408 23:42:26.304581
4409 23:42:26.311349 CA PerBit enable=1, Macro0, CA PI delay=34
4410 23:42:26.311432
4411 23:42:26.314254 [CBTSetCACLKResult] CA Dly = 34
4412 23:42:26.314335 CS Dly: 4 (0~35)
4413 23:42:26.314399 ==
4414 23:42:26.317974 Dram Type= 6, Freq= 0, CH_1, rank 1
4415 23:42:26.321058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 23:42:26.321140 ==
4417 23:42:26.328127 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4418 23:42:26.333789 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4419 23:42:26.336838 [CA 0] Center 35 (5~66) winsize 62
4420 23:42:26.340328 [CA 1] Center 35 (5~66) winsize 62
4421 23:42:26.343672 [CA 2] Center 34 (4~65) winsize 62
4422 23:42:26.347068 [CA 3] Center 34 (3~65) winsize 63
4423 23:42:26.350193 [CA 4] Center 34 (4~65) winsize 62
4424 23:42:26.353565 [CA 5] Center 33 (3~64) winsize 62
4425 23:42:26.353646
4426 23:42:26.356757 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4427 23:42:26.356838
4428 23:42:26.360280 [CATrainingPosCal] consider 2 rank data
4429 23:42:26.363190 u2DelayCellTimex100 = 270/100 ps
4430 23:42:26.366804 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4431 23:42:26.370394 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4432 23:42:26.376598 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 23:42:26.379916 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4434 23:42:26.383250 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4435 23:42:26.387283 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4436 23:42:26.387360
4437 23:42:26.389839 CA PerBit enable=1, Macro0, CA PI delay=33
4438 23:42:26.389923
4439 23:42:26.393211 [CBTSetCACLKResult] CA Dly = 33
4440 23:42:26.393317 CS Dly: 5 (0~37)
4441 23:42:26.393381
4442 23:42:26.396726 ----->DramcWriteLeveling(PI) begin...
4443 23:42:26.399699 ==
4444 23:42:26.403403 Dram Type= 6, Freq= 0, CH_1, rank 0
4445 23:42:26.406306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4446 23:42:26.406388 ==
4447 23:42:26.409583 Write leveling (Byte 0): 28 => 28
4448 23:42:26.413198 Write leveling (Byte 1): 32 => 32
4449 23:42:26.416614 DramcWriteLeveling(PI) end<-----
4450 23:42:26.416694
4451 23:42:26.416757 ==
4452 23:42:26.419801 Dram Type= 6, Freq= 0, CH_1, rank 0
4453 23:42:26.422517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4454 23:42:26.422599 ==
4455 23:42:26.426395 [Gating] SW mode calibration
4456 23:42:26.432379 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4457 23:42:26.439385 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4458 23:42:26.442553 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4459 23:42:26.445593 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4460 23:42:26.452063 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4461 23:42:26.455169 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (1 0)
4462 23:42:26.458516 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4463 23:42:26.465427 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4464 23:42:26.468501 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4465 23:42:26.471556 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4466 23:42:26.478264 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4467 23:42:26.481912 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4468 23:42:26.485223 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4469 23:42:26.491699 0 10 12 | B1->B0 | 3535 3b3b | 0 0 | (0 0) (0 0)
4470 23:42:26.495220 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4471 23:42:26.498140 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4472 23:42:26.504726 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4473 23:42:26.507751 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 23:42:26.511158 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 23:42:26.517761 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4476 23:42:26.521551 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 23:42:26.524229 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 23:42:26.531150 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4479 23:42:26.534693 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4480 23:42:26.537545 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4481 23:42:26.544464 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4482 23:42:26.547361 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4483 23:42:26.550975 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4484 23:42:26.557376 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 23:42:26.560403 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 23:42:26.563916 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 23:42:26.570662 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 23:42:26.574013 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 23:42:26.576806 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 23:42:26.583381 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 23:42:26.586968 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 23:42:26.590100 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 23:42:26.596607 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 23:42:26.599995 Total UI for P1: 0, mck2ui 16
4495 23:42:26.603453 best dqsien dly found for B0: ( 0, 13, 10)
4496 23:42:26.606916 Total UI for P1: 0, mck2ui 16
4497 23:42:26.609782 best dqsien dly found for B1: ( 0, 13, 10)
4498 23:42:26.613300 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4499 23:42:26.616525 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4500 23:42:26.616607
4501 23:42:26.619672 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4502 23:42:26.622969 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4503 23:42:26.626283 [Gating] SW calibration Done
4504 23:42:26.626364 ==
4505 23:42:26.629674 Dram Type= 6, Freq= 0, CH_1, rank 0
4506 23:42:26.633042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4507 23:42:26.636384 ==
4508 23:42:26.636491 RX Vref Scan: 0
4509 23:42:26.636581
4510 23:42:26.639869 RX Vref 0 -> 0, step: 1
4511 23:42:26.639950
4512 23:42:26.642663 RX Delay -230 -> 252, step: 16
4513 23:42:26.646263 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4514 23:42:26.649518 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4515 23:42:26.652657 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4516 23:42:26.659591 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4517 23:42:26.662443 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4518 23:42:26.666349 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4519 23:42:26.669372 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4520 23:42:26.672443 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4521 23:42:26.679221 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4522 23:42:26.682437 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4523 23:42:26.686643 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4524 23:42:26.689197 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4525 23:42:26.695686 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4526 23:42:26.699145 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4527 23:42:26.702123 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4528 23:42:26.705518 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4529 23:42:26.709164 ==
4530 23:42:26.709313 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 23:42:26.715177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 23:42:26.715260 ==
4533 23:42:26.715323 DQS Delay:
4534 23:42:26.718642 DQS0 = 0, DQS1 = 0
4535 23:42:26.718723 DQM Delay:
4536 23:42:26.721956 DQM0 = 42, DQM1 = 38
4537 23:42:26.722037 DQ Delay:
4538 23:42:26.725016 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4539 23:42:26.728226 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4540 23:42:26.731701 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4541 23:42:26.735377 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4542 23:42:26.735459
4543 23:42:26.735522
4544 23:42:26.735580 ==
4545 23:42:26.738539 Dram Type= 6, Freq= 0, CH_1, rank 0
4546 23:42:26.741990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4547 23:42:26.742077 ==
4548 23:42:26.742141
4549 23:42:26.742200
4550 23:42:26.744930 TX Vref Scan disable
4551 23:42:26.748052 == TX Byte 0 ==
4552 23:42:26.751805 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4553 23:42:26.754831 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4554 23:42:26.758307 == TX Byte 1 ==
4555 23:42:26.761111 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4556 23:42:26.764685 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4557 23:42:26.764807 ==
4558 23:42:26.768079 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 23:42:26.774625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 23:42:26.774756 ==
4561 23:42:26.774856
4562 23:42:26.774945
4563 23:42:26.775031 TX Vref Scan disable
4564 23:42:26.779122 == TX Byte 0 ==
4565 23:42:26.782382 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4566 23:42:26.789276 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4567 23:42:26.789377 == TX Byte 1 ==
4568 23:42:26.792496 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4569 23:42:26.799430 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4570 23:42:26.799519
4571 23:42:26.799587 [DATLAT]
4572 23:42:26.799647 Freq=600, CH1 RK0
4573 23:42:26.799704
4574 23:42:26.802230 DATLAT Default: 0x9
4575 23:42:26.802310 0, 0xFFFF, sum = 0
4576 23:42:26.805716 1, 0xFFFF, sum = 0
4577 23:42:26.808929 2, 0xFFFF, sum = 0
4578 23:42:26.809043 3, 0xFFFF, sum = 0
4579 23:42:26.811984 4, 0xFFFF, sum = 0
4580 23:42:26.812112 5, 0xFFFF, sum = 0
4581 23:42:26.815217 6, 0xFFFF, sum = 0
4582 23:42:26.815305 7, 0xFFFF, sum = 0
4583 23:42:26.818576 8, 0x0, sum = 1
4584 23:42:26.818659 9, 0x0, sum = 2
4585 23:42:26.822273 10, 0x0, sum = 3
4586 23:42:26.822356 11, 0x0, sum = 4
4587 23:42:26.822420 best_step = 9
4588 23:42:26.822479
4589 23:42:26.825146 ==
4590 23:42:26.828659 Dram Type= 6, Freq= 0, CH_1, rank 0
4591 23:42:26.832047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 23:42:26.832154 ==
4593 23:42:26.832245 RX Vref Scan: 1
4594 23:42:26.832332
4595 23:42:26.835225 RX Vref 0 -> 0, step: 1
4596 23:42:26.835347
4597 23:42:26.838681 RX Delay -179 -> 252, step: 8
4598 23:42:26.838791
4599 23:42:26.842001 Set Vref, RX VrefLevel [Byte0]: 51
4600 23:42:26.844992 [Byte1]: 52
4601 23:42:26.845211
4602 23:42:26.848323 Final RX Vref Byte 0 = 51 to rank0
4603 23:42:26.851368 Final RX Vref Byte 1 = 52 to rank0
4604 23:42:26.854726 Final RX Vref Byte 0 = 51 to rank1
4605 23:42:26.858268 Final RX Vref Byte 1 = 52 to rank1==
4606 23:42:26.861184 Dram Type= 6, Freq= 0, CH_1, rank 0
4607 23:42:26.867945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 23:42:26.868032 ==
4609 23:42:26.868096 DQS Delay:
4610 23:42:26.868154 DQS0 = 0, DQS1 = 0
4611 23:42:26.871331 DQM Delay:
4612 23:42:26.871439 DQM0 = 41, DQM1 = 33
4613 23:42:26.874435 DQ Delay:
4614 23:42:26.878015 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4615 23:42:26.878096 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4616 23:42:26.881095 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4617 23:42:26.887892 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4618 23:42:26.887977
4619 23:42:26.888043
4620 23:42:26.894281 [DQSOSCAuto] RK0, (LSB)MR18= 0x324b, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4621 23:42:26.897451 CH1 RK0: MR19=808, MR18=324B
4622 23:42:26.904176 CH1_RK0: MR19=0x808, MR18=0x324B, DQSOSC=395, MR23=63, INC=168, DEC=112
4623 23:42:26.904274
4624 23:42:26.907735 ----->DramcWriteLeveling(PI) begin...
4625 23:42:26.907819 ==
4626 23:42:26.910554 Dram Type= 6, Freq= 0, CH_1, rank 1
4627 23:42:26.914287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 23:42:26.914369 ==
4629 23:42:26.917172 Write leveling (Byte 0): 28 => 28
4630 23:42:26.920421 Write leveling (Byte 1): 28 => 28
4631 23:42:26.923901 DramcWriteLeveling(PI) end<-----
4632 23:42:26.923992
4633 23:42:26.924058 ==
4634 23:42:26.927006 Dram Type= 6, Freq= 0, CH_1, rank 1
4635 23:42:26.930615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 23:42:26.934030 ==
4637 23:42:26.934139 [Gating] SW mode calibration
4638 23:42:26.943921 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4639 23:42:26.947333 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4640 23:42:26.950668 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4641 23:42:26.956985 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4642 23:42:26.960258 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4643 23:42:26.963509 0 9 12 | B1->B0 | 3030 2d2d | 1 0 | (1 0) (0 0)
4644 23:42:26.970507 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4645 23:42:26.973295 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4646 23:42:26.976912 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4647 23:42:26.983216 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4648 23:42:26.986579 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4649 23:42:26.989623 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4650 23:42:26.996543 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4651 23:42:26.999544 0 10 12 | B1->B0 | 3535 3c3c | 0 0 | (0 0) (0 0)
4652 23:42:27.002976 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4653 23:42:27.009972 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4654 23:42:27.012961 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4655 23:42:27.015894 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4656 23:42:27.022646 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4657 23:42:27.026099 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4658 23:42:27.029569 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 23:42:27.036068 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4660 23:42:27.039449 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4661 23:42:27.042436 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4662 23:42:27.048880 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4663 23:42:27.052444 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4664 23:42:27.056023 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4665 23:42:27.062823 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4666 23:42:27.065643 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 23:42:27.069121 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 23:42:27.075532 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 23:42:27.078912 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 23:42:27.082388 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 23:42:27.089202 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 23:42:27.092009 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 23:42:27.095128 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 23:42:27.101684 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 23:42:27.105209 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4676 23:42:27.108768 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 23:42:27.111790 Total UI for P1: 0, mck2ui 16
4678 23:42:27.115110 best dqsien dly found for B0: ( 0, 13, 12)
4679 23:42:27.118371 Total UI for P1: 0, mck2ui 16
4680 23:42:27.121983 best dqsien dly found for B1: ( 0, 13, 12)
4681 23:42:27.125170 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4682 23:42:27.128180 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4683 23:42:27.128269
4684 23:42:27.135358 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4685 23:42:27.138646 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4686 23:42:27.141436 [Gating] SW calibration Done
4687 23:42:27.141545 ==
4688 23:42:27.144795 Dram Type= 6, Freq= 0, CH_1, rank 1
4689 23:42:27.148314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4690 23:42:27.148402 ==
4691 23:42:27.148466 RX Vref Scan: 0
4692 23:42:27.148527
4693 23:42:27.151803 RX Vref 0 -> 0, step: 1
4694 23:42:27.151885
4695 23:42:27.154685 RX Delay -230 -> 252, step: 16
4696 23:42:27.158225 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4697 23:42:27.164674 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4698 23:42:27.167752 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4699 23:42:27.171304 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4700 23:42:27.174716 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4701 23:42:27.177736 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4702 23:42:27.184230 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4703 23:42:27.187848 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4704 23:42:27.191487 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4705 23:42:27.194354 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4706 23:42:27.201057 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4707 23:42:27.204110 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4708 23:42:27.207552 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4709 23:42:27.210481 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4710 23:42:27.217564 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4711 23:42:27.220453 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4712 23:42:27.220536 ==
4713 23:42:27.223870 Dram Type= 6, Freq= 0, CH_1, rank 1
4714 23:42:27.226964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4715 23:42:27.227047 ==
4716 23:42:27.230413 DQS Delay:
4717 23:42:27.230495 DQS0 = 0, DQS1 = 0
4718 23:42:27.233602 DQM Delay:
4719 23:42:27.233683 DQM0 = 42, DQM1 = 39
4720 23:42:27.233747 DQ Delay:
4721 23:42:27.236968 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4722 23:42:27.239855 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4723 23:42:27.243479 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4724 23:42:27.246532 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4725 23:42:27.246614
4726 23:42:27.246678
4727 23:42:27.250190 ==
4728 23:42:27.253379 Dram Type= 6, Freq= 0, CH_1, rank 1
4729 23:42:27.256547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4730 23:42:27.256629 ==
4731 23:42:27.256693
4732 23:42:27.256753
4733 23:42:27.260252 TX Vref Scan disable
4734 23:42:27.260333 == TX Byte 0 ==
4735 23:42:27.267065 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4736 23:42:27.269988 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4737 23:42:27.270071 == TX Byte 1 ==
4738 23:42:27.276483 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4739 23:42:27.279681 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4740 23:42:27.279766 ==
4741 23:42:27.283125 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 23:42:27.286113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 23:42:27.286196 ==
4744 23:42:27.286260
4745 23:42:27.286319
4746 23:42:27.289777 TX Vref Scan disable
4747 23:42:27.292669 == TX Byte 0 ==
4748 23:42:27.296243 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4749 23:42:27.299655 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4750 23:42:27.302572 == TX Byte 1 ==
4751 23:42:27.306114 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4752 23:42:27.309549 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4753 23:42:27.309632
4754 23:42:27.312557 [DATLAT]
4755 23:42:27.312638 Freq=600, CH1 RK1
4756 23:42:27.312702
4757 23:42:27.316046 DATLAT Default: 0x9
4758 23:42:27.316127 0, 0xFFFF, sum = 0
4759 23:42:27.319628 1, 0xFFFF, sum = 0
4760 23:42:27.319711 2, 0xFFFF, sum = 0
4761 23:42:27.322786 3, 0xFFFF, sum = 0
4762 23:42:27.322870 4, 0xFFFF, sum = 0
4763 23:42:27.326021 5, 0xFFFF, sum = 0
4764 23:42:27.329292 6, 0xFFFF, sum = 0
4765 23:42:27.329376 7, 0xFFFF, sum = 0
4766 23:42:27.329441 8, 0x0, sum = 1
4767 23:42:27.332770 9, 0x0, sum = 2
4768 23:42:27.332853 10, 0x0, sum = 3
4769 23:42:27.336181 11, 0x0, sum = 4
4770 23:42:27.336264 best_step = 9
4771 23:42:27.336328
4772 23:42:27.336387 ==
4773 23:42:27.339101 Dram Type= 6, Freq= 0, CH_1, rank 1
4774 23:42:27.345523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4775 23:42:27.345606 ==
4776 23:42:27.345669 RX Vref Scan: 0
4777 23:42:27.345728
4778 23:42:27.348967 RX Vref 0 -> 0, step: 1
4779 23:42:27.349047
4780 23:42:27.352242 RX Delay -179 -> 252, step: 8
4781 23:42:27.355406 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4782 23:42:27.362128 iDelay=205, Bit 1, Center 32 (-131 ~ 196) 328
4783 23:42:27.365617 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4784 23:42:27.368635 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4785 23:42:27.371855 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4786 23:42:27.378807 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4787 23:42:27.382204 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4788 23:42:27.385543 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4789 23:42:27.388421 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4790 23:42:27.392122 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4791 23:42:27.398274 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4792 23:42:27.401676 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4793 23:42:27.405264 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4794 23:42:27.408591 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4795 23:42:27.415325 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4796 23:42:27.418238 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4797 23:42:27.418320 ==
4798 23:42:27.421747 Dram Type= 6, Freq= 0, CH_1, rank 1
4799 23:42:27.424915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4800 23:42:27.424998 ==
4801 23:42:27.428322 DQS Delay:
4802 23:42:27.428403 DQS0 = 0, DQS1 = 0
4803 23:42:27.431395 DQM Delay:
4804 23:42:27.431477 DQM0 = 37, DQM1 = 34
4805 23:42:27.431542 DQ Delay:
4806 23:42:27.435255 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4807 23:42:27.438172 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =32
4808 23:42:27.441403 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4809 23:42:27.444415 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4810 23:42:27.444496
4811 23:42:27.444558
4812 23:42:27.454853 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4813 23:42:27.457549 CH1 RK1: MR19=808, MR18=3D61
4814 23:42:27.464118 CH1_RK1: MR19=0x808, MR18=0x3D61, DQSOSC=391, MR23=63, INC=171, DEC=114
4815 23:42:27.467467 [RxdqsGatingPostProcess] freq 600
4816 23:42:27.471152 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4817 23:42:27.474413 Pre-setting of DQS Precalculation
4818 23:42:27.480952 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4819 23:42:27.487350 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4820 23:42:27.493691 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4821 23:42:27.493775
4822 23:42:27.493840
4823 23:42:27.497023 [Calibration Summary] 1200 Mbps
4824 23:42:27.497105 CH 0, Rank 0
4825 23:42:27.500614 SW Impedance : PASS
4826 23:42:27.503588 DUTY Scan : NO K
4827 23:42:27.503669 ZQ Calibration : PASS
4828 23:42:27.507077 Jitter Meter : NO K
4829 23:42:27.510414 CBT Training : PASS
4830 23:42:27.510495 Write leveling : PASS
4831 23:42:27.513721 RX DQS gating : PASS
4832 23:42:27.516734 RX DQ/DQS(RDDQC) : PASS
4833 23:42:27.516816 TX DQ/DQS : PASS
4834 23:42:27.520278 RX DATLAT : PASS
4835 23:42:27.520360 RX DQ/DQS(Engine): PASS
4836 23:42:27.523937 TX OE : NO K
4837 23:42:27.524018 All Pass.
4838 23:42:27.524082
4839 23:42:27.527174 CH 0, Rank 1
4840 23:42:27.530545 SW Impedance : PASS
4841 23:42:27.530628 DUTY Scan : NO K
4842 23:42:27.533697 ZQ Calibration : PASS
4843 23:42:27.533779 Jitter Meter : NO K
4844 23:42:27.536764 CBT Training : PASS
4845 23:42:27.539908 Write leveling : PASS
4846 23:42:27.539989 RX DQS gating : PASS
4847 23:42:27.543771 RX DQ/DQS(RDDQC) : PASS
4848 23:42:27.546838 TX DQ/DQS : PASS
4849 23:42:27.546921 RX DATLAT : PASS
4850 23:42:27.549966 RX DQ/DQS(Engine): PASS
4851 23:42:27.553375 TX OE : NO K
4852 23:42:27.553457 All Pass.
4853 23:42:27.553520
4854 23:42:27.553579 CH 1, Rank 0
4855 23:42:27.556846 SW Impedance : PASS
4856 23:42:27.559737 DUTY Scan : NO K
4857 23:42:27.559819 ZQ Calibration : PASS
4858 23:42:27.562752 Jitter Meter : NO K
4859 23:42:27.566732 CBT Training : PASS
4860 23:42:27.566813 Write leveling : PASS
4861 23:42:27.569543 RX DQS gating : PASS
4862 23:42:27.572705 RX DQ/DQS(RDDQC) : PASS
4863 23:42:27.572786 TX DQ/DQS : PASS
4864 23:42:27.576161 RX DATLAT : PASS
4865 23:42:27.579327 RX DQ/DQS(Engine): PASS
4866 23:42:27.579409 TX OE : NO K
4867 23:42:27.582679 All Pass.
4868 23:42:27.582762
4869 23:42:27.582826 CH 1, Rank 1
4870 23:42:27.585997 SW Impedance : PASS
4871 23:42:27.586079 DUTY Scan : NO K
4872 23:42:27.589426 ZQ Calibration : PASS
4873 23:42:27.592966 Jitter Meter : NO K
4874 23:42:27.593122 CBT Training : PASS
4875 23:42:27.595839 Write leveling : PASS
4876 23:42:27.599300 RX DQS gating : PASS
4877 23:42:27.599405 RX DQ/DQS(RDDQC) : PASS
4878 23:42:27.602566 TX DQ/DQS : PASS
4879 23:42:27.605573 RX DATLAT : PASS
4880 23:42:27.605655 RX DQ/DQS(Engine): PASS
4881 23:42:27.609389 TX OE : NO K
4882 23:42:27.609489 All Pass.
4883 23:42:27.609554
4884 23:42:27.612309 DramC Write-DBI off
4885 23:42:27.615421 PER_BANK_REFRESH: Hybrid Mode
4886 23:42:27.615506 TX_TRACKING: ON
4887 23:42:27.625248 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4888 23:42:27.628477 [FAST_K] Save calibration result to emmc
4889 23:42:27.632275 dramc_set_vcore_voltage set vcore to 662500
4890 23:42:27.635773 Read voltage for 933, 3
4891 23:42:27.635856 Vio18 = 0
4892 23:42:27.635920 Vcore = 662500
4893 23:42:27.638590 Vdram = 0
4894 23:42:27.638672 Vddq = 0
4895 23:42:27.638785 Vmddr = 0
4896 23:42:27.645609 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4897 23:42:27.648425 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4898 23:42:27.651550 MEM_TYPE=3, freq_sel=17
4899 23:42:27.655284 sv_algorithm_assistance_LP4_1600
4900 23:42:27.658251 ============ PULL DRAM RESETB DOWN ============
4901 23:42:27.661682 ========== PULL DRAM RESETB DOWN end =========
4902 23:42:27.668321 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4903 23:42:27.671650 ===================================
4904 23:42:27.674908 LPDDR4 DRAM CONFIGURATION
4905 23:42:27.678115 ===================================
4906 23:42:27.678227 EX_ROW_EN[0] = 0x0
4907 23:42:27.681541 EX_ROW_EN[1] = 0x0
4908 23:42:27.681629 LP4Y_EN = 0x0
4909 23:42:27.684911 WORK_FSP = 0x0
4910 23:42:27.684992 WL = 0x3
4911 23:42:27.688155 RL = 0x3
4912 23:42:27.688237 BL = 0x2
4913 23:42:27.691023 RPST = 0x0
4914 23:42:27.691105 RD_PRE = 0x0
4915 23:42:27.694439 WR_PRE = 0x1
4916 23:42:27.694525 WR_PST = 0x0
4917 23:42:27.698017 DBI_WR = 0x0
4918 23:42:27.700908 DBI_RD = 0x0
4919 23:42:27.700990 OTF = 0x1
4920 23:42:27.704366 ===================================
4921 23:42:27.707718 ===================================
4922 23:42:27.707804 ANA top config
4923 23:42:27.711007 ===================================
4924 23:42:27.714235 DLL_ASYNC_EN = 0
4925 23:42:27.717466 ALL_SLAVE_EN = 1
4926 23:42:27.721005 NEW_RANK_MODE = 1
4927 23:42:27.724451 DLL_IDLE_MODE = 1
4928 23:42:27.724532 LP45_APHY_COMB_EN = 1
4929 23:42:27.727501 TX_ODT_DIS = 1
4930 23:42:27.731544 NEW_8X_MODE = 1
4931 23:42:27.733953 ===================================
4932 23:42:27.737400 ===================================
4933 23:42:27.741072 data_rate = 1866
4934 23:42:27.744027 CKR = 1
4935 23:42:27.747188 DQ_P2S_RATIO = 8
4936 23:42:27.750369 ===================================
4937 23:42:27.750452 CA_P2S_RATIO = 8
4938 23:42:27.753714 DQ_CA_OPEN = 0
4939 23:42:27.756980 DQ_SEMI_OPEN = 0
4940 23:42:27.760420 CA_SEMI_OPEN = 0
4941 23:42:27.763274 CA_FULL_RATE = 0
4942 23:42:27.766664 DQ_CKDIV4_EN = 1
4943 23:42:27.766746 CA_CKDIV4_EN = 1
4944 23:42:27.770579 CA_PREDIV_EN = 0
4945 23:42:27.773434 PH8_DLY = 0
4946 23:42:27.776337 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4947 23:42:27.779692 DQ_AAMCK_DIV = 4
4948 23:42:27.783227 CA_AAMCK_DIV = 4
4949 23:42:27.783308 CA_ADMCK_DIV = 4
4950 23:42:27.786731 DQ_TRACK_CA_EN = 0
4951 23:42:27.790610 CA_PICK = 933
4952 23:42:27.793064 CA_MCKIO = 933
4953 23:42:27.796549 MCKIO_SEMI = 0
4954 23:42:27.799893 PLL_FREQ = 3732
4955 23:42:27.803612 DQ_UI_PI_RATIO = 32
4956 23:42:27.803693 CA_UI_PI_RATIO = 0
4957 23:42:27.806164 ===================================
4958 23:42:27.809494 ===================================
4959 23:42:27.813035 memory_type:LPDDR4
4960 23:42:27.816053 GP_NUM : 10
4961 23:42:27.816138 SRAM_EN : 1
4962 23:42:27.819674 MD32_EN : 0
4963 23:42:27.823017 ===================================
4964 23:42:27.826492 [ANA_INIT] >>>>>>>>>>>>>>
4965 23:42:27.829398 <<<<<< [CONFIGURE PHASE]: ANA_TX
4966 23:42:27.833200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4967 23:42:27.835873 ===================================
4968 23:42:27.839764 data_rate = 1866,PCW = 0X8f00
4969 23:42:27.842642 ===================================
4970 23:42:27.846136 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4971 23:42:27.849699 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4972 23:42:27.856042 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4973 23:42:27.859511 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4974 23:42:27.862635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4975 23:42:27.866072 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4976 23:42:27.868995 [ANA_INIT] flow start
4977 23:42:27.872911 [ANA_INIT] PLL >>>>>>>>
4978 23:42:27.872993 [ANA_INIT] PLL <<<<<<<<
4979 23:42:27.875806 [ANA_INIT] MIDPI >>>>>>>>
4980 23:42:27.879098 [ANA_INIT] MIDPI <<<<<<<<
4981 23:42:27.879180 [ANA_INIT] DLL >>>>>>>>
4982 23:42:27.882210 [ANA_INIT] flow end
4983 23:42:27.885876 ============ LP4 DIFF to SE enter ============
4984 23:42:27.892476 ============ LP4 DIFF to SE exit ============
4985 23:42:27.892582 [ANA_INIT] <<<<<<<<<<<<<
4986 23:42:27.895588 [Flow] Enable top DCM control >>>>>
4987 23:42:27.898421 [Flow] Enable top DCM control <<<<<
4988 23:42:27.902197 Enable DLL master slave shuffle
4989 23:42:27.908680 ==============================================================
4990 23:42:27.908793 Gating Mode config
4991 23:42:27.915245 ==============================================================
4992 23:42:27.918889 Config description:
4993 23:42:27.928242 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4994 23:42:27.935161 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4995 23:42:27.938359 SELPH_MODE 0: By rank 1: By Phase
4996 23:42:27.944835 ==============================================================
4997 23:42:27.947809 GAT_TRACK_EN = 1
4998 23:42:27.951293 RX_GATING_MODE = 2
4999 23:42:27.951374 RX_GATING_TRACK_MODE = 2
5000 23:42:27.954696 SELPH_MODE = 1
5001 23:42:27.958069 PICG_EARLY_EN = 1
5002 23:42:27.961015 VALID_LAT_VALUE = 1
5003 23:42:27.967993 ==============================================================
5004 23:42:27.971065 Enter into Gating configuration >>>>
5005 23:42:27.974308 Exit from Gating configuration <<<<
5006 23:42:27.978090 Enter into DVFS_PRE_config >>>>>
5007 23:42:27.987593 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5008 23:42:27.990935 Exit from DVFS_PRE_config <<<<<
5009 23:42:27.994243 Enter into PICG configuration >>>>
5010 23:42:27.997239 Exit from PICG configuration <<<<
5011 23:42:28.001008 [RX_INPUT] configuration >>>>>
5012 23:42:28.004360 [RX_INPUT] configuration <<<<<
5013 23:42:28.007528 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5014 23:42:28.014519 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5015 23:42:28.020585 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5016 23:42:28.027056 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5017 23:42:28.033583 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5018 23:42:28.040095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5019 23:42:28.043617 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5020 23:42:28.047036 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5021 23:42:28.050627 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5022 23:42:28.056937 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5023 23:42:28.059849 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5024 23:42:28.063512 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5025 23:42:28.066642 ===================================
5026 23:42:28.069745 LPDDR4 DRAM CONFIGURATION
5027 23:42:28.073279 ===================================
5028 23:42:28.073377 EX_ROW_EN[0] = 0x0
5029 23:42:28.076652 EX_ROW_EN[1] = 0x0
5030 23:42:28.076750 LP4Y_EN = 0x0
5031 23:42:28.080023 WORK_FSP = 0x0
5032 23:42:28.083349 WL = 0x3
5033 23:42:28.083430 RL = 0x3
5034 23:42:28.086131 BL = 0x2
5035 23:42:28.086257 RPST = 0x0
5036 23:42:28.089869 RD_PRE = 0x0
5037 23:42:28.089953 WR_PRE = 0x1
5038 23:42:28.092839 WR_PST = 0x0
5039 23:42:28.092947 DBI_WR = 0x0
5040 23:42:28.096208 DBI_RD = 0x0
5041 23:42:28.096314 OTF = 0x1
5042 23:42:28.099584 ===================================
5043 23:42:28.103156 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5044 23:42:28.109582 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5045 23:42:28.112647 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5046 23:42:28.115737 ===================================
5047 23:42:28.119513 LPDDR4 DRAM CONFIGURATION
5048 23:42:28.122652 ===================================
5049 23:42:28.122758 EX_ROW_EN[0] = 0x10
5050 23:42:28.126087 EX_ROW_EN[1] = 0x0
5051 23:42:28.128832 LP4Y_EN = 0x0
5052 23:42:28.128931 WORK_FSP = 0x0
5053 23:42:28.132788 WL = 0x3
5054 23:42:28.132891 RL = 0x3
5055 23:42:28.135774 BL = 0x2
5056 23:42:28.135875 RPST = 0x0
5057 23:42:28.138783 RD_PRE = 0x0
5058 23:42:28.138893 WR_PRE = 0x1
5059 23:42:28.142277 WR_PST = 0x0
5060 23:42:28.142383 DBI_WR = 0x0
5061 23:42:28.145429 DBI_RD = 0x0
5062 23:42:28.145533 OTF = 0x1
5063 23:42:28.148747 ===================================
5064 23:42:28.155213 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5065 23:42:28.160356 nWR fixed to 30
5066 23:42:28.163411 [ModeRegInit_LP4] CH0 RK0
5067 23:42:28.163517 [ModeRegInit_LP4] CH0 RK1
5068 23:42:28.166514 [ModeRegInit_LP4] CH1 RK0
5069 23:42:28.170006 [ModeRegInit_LP4] CH1 RK1
5070 23:42:28.170082 match AC timing 9
5071 23:42:28.176336 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5072 23:42:28.179715 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5073 23:42:28.183130 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5074 23:42:28.189791 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5075 23:42:28.192861 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5076 23:42:28.192966 ==
5077 23:42:28.196150 Dram Type= 6, Freq= 0, CH_0, rank 0
5078 23:42:28.199437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5079 23:42:28.199519 ==
5080 23:42:28.205985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5081 23:42:28.212493 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5082 23:42:28.216085 [CA 0] Center 38 (7~69) winsize 63
5083 23:42:28.219421 [CA 1] Center 37 (7~68) winsize 62
5084 23:42:28.222735 [CA 2] Center 34 (4~65) winsize 62
5085 23:42:28.225699 [CA 3] Center 34 (4~65) winsize 62
5086 23:42:28.229119 [CA 4] Center 33 (3~64) winsize 62
5087 23:42:28.232557 [CA 5] Center 32 (2~63) winsize 62
5088 23:42:28.232640
5089 23:42:28.236165 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5090 23:42:28.236246
5091 23:42:28.238969 [CATrainingPosCal] consider 1 rank data
5092 23:42:28.242290 u2DelayCellTimex100 = 270/100 ps
5093 23:42:28.245743 CA0 delay=38 (7~69),Diff = 6 PI (37 cell)
5094 23:42:28.249147 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5095 23:42:28.252095 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5096 23:42:28.258722 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5097 23:42:28.261857 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5098 23:42:28.265131 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5099 23:42:28.265249
5100 23:42:28.268826 CA PerBit enable=1, Macro0, CA PI delay=32
5101 23:42:28.268925
5102 23:42:28.272099 [CBTSetCACLKResult] CA Dly = 32
5103 23:42:28.272173 CS Dly: 5 (0~36)
5104 23:42:28.272233 ==
5105 23:42:28.275287 Dram Type= 6, Freq= 0, CH_0, rank 1
5106 23:42:28.282132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5107 23:42:28.282223 ==
5108 23:42:28.285067 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5109 23:42:28.291708 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5110 23:42:28.295021 [CA 0] Center 38 (8~69) winsize 62
5111 23:42:28.298641 [CA 1] Center 38 (8~69) winsize 62
5112 23:42:28.301534 [CA 2] Center 35 (5~65) winsize 61
5113 23:42:28.305374 [CA 3] Center 34 (4~65) winsize 62
5114 23:42:28.308143 [CA 4] Center 33 (3~64) winsize 62
5115 23:42:28.311636 [CA 5] Center 33 (3~63) winsize 61
5116 23:42:28.311743
5117 23:42:28.314930 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5118 23:42:28.315008
5119 23:42:28.318026 [CATrainingPosCal] consider 2 rank data
5120 23:42:28.321362 u2DelayCellTimex100 = 270/100 ps
5121 23:42:28.324922 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5122 23:42:28.331509 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5123 23:42:28.334598 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5124 23:42:28.337924 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5125 23:42:28.341380 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5126 23:42:28.344407 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5127 23:42:28.344482
5128 23:42:28.347638 CA PerBit enable=1, Macro0, CA PI delay=33
5129 23:42:28.347740
5130 23:42:28.350907 [CBTSetCACLKResult] CA Dly = 33
5131 23:42:28.354394 CS Dly: 6 (0~39)
5132 23:42:28.354466
5133 23:42:28.357627 ----->DramcWriteLeveling(PI) begin...
5134 23:42:28.357701 ==
5135 23:42:28.361028 Dram Type= 6, Freq= 0, CH_0, rank 0
5136 23:42:28.364246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5137 23:42:28.364358 ==
5138 23:42:28.367451 Write leveling (Byte 0): 32 => 32
5139 23:42:28.371291 Write leveling (Byte 1): 26 => 26
5140 23:42:28.374029 DramcWriteLeveling(PI) end<-----
5141 23:42:28.374101
5142 23:42:28.374169 ==
5143 23:42:28.377380 Dram Type= 6, Freq= 0, CH_0, rank 0
5144 23:42:28.381276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5145 23:42:28.381353 ==
5146 23:42:28.383932 [Gating] SW mode calibration
5147 23:42:28.390461 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5148 23:42:28.397231 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5149 23:42:28.400655 0 14 0 | B1->B0 | 2424 3232 | 0 1 | (0 0) (1 1)
5150 23:42:28.406818 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5151 23:42:28.410108 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5152 23:42:28.413627 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5153 23:42:28.420248 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5154 23:42:28.423296 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5155 23:42:28.426658 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
5156 23:42:28.433540 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 1)
5157 23:42:28.436154 0 15 0 | B1->B0 | 2f2f 2525 | 0 0 | (1 0) (0 0)
5158 23:42:28.439751 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5159 23:42:28.446082 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5160 23:42:28.449364 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5161 23:42:28.452956 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5162 23:42:28.459679 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5163 23:42:28.462697 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5164 23:42:28.466105 0 15 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
5165 23:42:28.473008 1 0 0 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
5166 23:42:28.475952 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5167 23:42:28.479094 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5168 23:42:28.485633 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5169 23:42:28.489240 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5170 23:42:28.492416 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5171 23:42:28.499321 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5172 23:42:28.502648 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5173 23:42:28.505365 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5174 23:42:28.512096 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5175 23:42:28.515368 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5176 23:42:28.518580 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5177 23:42:28.525403 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5178 23:42:28.529022 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5179 23:42:28.532237 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5180 23:42:28.538781 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5181 23:42:28.542051 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 23:42:28.545463 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 23:42:28.551914 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 23:42:28.554845 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 23:42:28.558142 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 23:42:28.564874 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 23:42:28.568238 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 23:42:28.571358 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5189 23:42:28.574912 Total UI for P1: 0, mck2ui 16
5190 23:42:28.577802 best dqsien dly found for B0: ( 1, 2, 26)
5191 23:42:28.584899 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5192 23:42:28.587870 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 23:42:28.591357 Total UI for P1: 0, mck2ui 16
5194 23:42:28.594618 best dqsien dly found for B1: ( 1, 2, 30)
5195 23:42:28.597958 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5196 23:42:28.600741 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5197 23:42:28.600850
5198 23:42:28.604163 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5199 23:42:28.607466 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5200 23:42:28.610701 [Gating] SW calibration Done
5201 23:42:28.610783 ==
5202 23:42:28.614054 Dram Type= 6, Freq= 0, CH_0, rank 0
5203 23:42:28.620990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5204 23:42:28.621094 ==
5205 23:42:28.621185 RX Vref Scan: 0
5206 23:42:28.621296
5207 23:42:28.624210 RX Vref 0 -> 0, step: 1
5208 23:42:28.624285
5209 23:42:28.627561 RX Delay -80 -> 252, step: 8
5210 23:42:28.630896 iDelay=200, Bit 0, Center 103 (8 ~ 199) 192
5211 23:42:28.634144 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5212 23:42:28.637571 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5213 23:42:28.640429 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5214 23:42:28.647325 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5215 23:42:28.650850 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5216 23:42:28.653668 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5217 23:42:28.657192 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5218 23:42:28.660244 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5219 23:42:28.666841 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5220 23:42:28.670348 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5221 23:42:28.673374 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5222 23:42:28.676634 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5223 23:42:28.680176 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5224 23:42:28.683151 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5225 23:42:28.689974 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5226 23:42:28.690082 ==
5227 23:42:28.693408 Dram Type= 6, Freq= 0, CH_0, rank 0
5228 23:42:28.696247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5229 23:42:28.696355 ==
5230 23:42:28.696422 DQS Delay:
5231 23:42:28.699677 DQS0 = 0, DQS1 = 0
5232 23:42:28.699785 DQM Delay:
5233 23:42:28.703017 DQM0 = 101, DQM1 = 87
5234 23:42:28.703091 DQ Delay:
5235 23:42:28.706560 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =99
5236 23:42:28.709632 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5237 23:42:28.713055 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5238 23:42:28.716353 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5239 23:42:28.716454
5240 23:42:28.716519
5241 23:42:28.716592 ==
5242 23:42:28.719684 Dram Type= 6, Freq= 0, CH_0, rank 0
5243 23:42:28.725980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5244 23:42:28.726083 ==
5245 23:42:28.726150
5246 23:42:28.726218
5247 23:42:28.726276 TX Vref Scan disable
5248 23:42:28.729816 == TX Byte 0 ==
5249 23:42:28.732805 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5250 23:42:28.740030 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5251 23:42:28.740135 == TX Byte 1 ==
5252 23:42:28.742747 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5253 23:42:28.749712 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5254 23:42:28.749809 ==
5255 23:42:28.752712 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 23:42:28.755927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 23:42:28.756002 ==
5258 23:42:28.756063
5259 23:42:28.756120
5260 23:42:28.759377 TX Vref Scan disable
5261 23:42:28.762355 == TX Byte 0 ==
5262 23:42:28.766004 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5263 23:42:28.773785 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5264 23:42:28.773896 == TX Byte 1 ==
5265 23:42:28.775862 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5266 23:42:28.778921 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5267 23:42:28.779021
5268 23:42:28.779110 [DATLAT]
5269 23:42:28.782270 Freq=933, CH0 RK0
5270 23:42:28.782370
5271 23:42:28.785651 DATLAT Default: 0xd
5272 23:42:28.785749 0, 0xFFFF, sum = 0
5273 23:42:28.789079 1, 0xFFFF, sum = 0
5274 23:42:28.789178 2, 0xFFFF, sum = 0
5275 23:42:28.792170 3, 0xFFFF, sum = 0
5276 23:42:28.792273 4, 0xFFFF, sum = 0
5277 23:42:28.795392 5, 0xFFFF, sum = 0
5278 23:42:28.795496 6, 0xFFFF, sum = 0
5279 23:42:28.798795 7, 0xFFFF, sum = 0
5280 23:42:28.798897 8, 0xFFFF, sum = 0
5281 23:42:28.802161 9, 0xFFFF, sum = 0
5282 23:42:28.802261 10, 0x0, sum = 1
5283 23:42:28.805176 11, 0x0, sum = 2
5284 23:42:28.805316 12, 0x0, sum = 3
5285 23:42:28.808533 13, 0x0, sum = 4
5286 23:42:28.808637 best_step = 11
5287 23:42:28.808725
5288 23:42:28.808810 ==
5289 23:42:28.812048 Dram Type= 6, Freq= 0, CH_0, rank 0
5290 23:42:28.818858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5291 23:42:28.818937 ==
5292 23:42:28.819025 RX Vref Scan: 1
5293 23:42:28.819110
5294 23:42:28.821830 RX Vref 0 -> 0, step: 1
5295 23:42:28.821905
5296 23:42:28.825706 RX Delay -61 -> 252, step: 4
5297 23:42:28.825779
5298 23:42:28.828319 Set Vref, RX VrefLevel [Byte0]: 58
5299 23:42:28.831635 [Byte1]: 49
5300 23:42:28.831737
5301 23:42:28.834982 Final RX Vref Byte 0 = 58 to rank0
5302 23:42:28.837909 Final RX Vref Byte 1 = 49 to rank0
5303 23:42:28.841655 Final RX Vref Byte 0 = 58 to rank1
5304 23:42:28.844917 Final RX Vref Byte 1 = 49 to rank1==
5305 23:42:28.847921 Dram Type= 6, Freq= 0, CH_0, rank 0
5306 23:42:28.851506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 23:42:28.851583 ==
5308 23:42:28.854960 DQS Delay:
5309 23:42:28.855035 DQS0 = 0, DQS1 = 0
5310 23:42:28.855128 DQM Delay:
5311 23:42:28.857823 DQM0 = 103, DQM1 = 89
5312 23:42:28.857895 DQ Delay:
5313 23:42:28.861055 DQ0 =104, DQ1 =102, DQ2 =100, DQ3 =98
5314 23:42:28.864568 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =108
5315 23:42:28.868173 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =86
5316 23:42:28.874497 DQ12 =98, DQ13 =92, DQ14 =98, DQ15 =96
5317 23:42:28.874573
5318 23:42:28.874633
5319 23:42:28.880799 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5320 23:42:28.884472 CH0 RK0: MR19=505, MR18=1B16
5321 23:42:28.891121 CH0_RK0: MR19=0x505, MR18=0x1B16, DQSOSC=413, MR23=63, INC=63, DEC=42
5322 23:42:28.891214
5323 23:42:28.894318 ----->DramcWriteLeveling(PI) begin...
5324 23:42:28.894389 ==
5325 23:42:28.897115 Dram Type= 6, Freq= 0, CH_0, rank 1
5326 23:42:28.900768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 23:42:28.900864 ==
5328 23:42:28.903952 Write leveling (Byte 0): 32 => 32
5329 23:42:28.907294 Write leveling (Byte 1): 26 => 26
5330 23:42:28.910722 DramcWriteLeveling(PI) end<-----
5331 23:42:28.910804
5332 23:42:28.910868 ==
5333 23:42:28.913746 Dram Type= 6, Freq= 0, CH_0, rank 1
5334 23:42:28.917265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5335 23:42:28.917381 ==
5336 23:42:28.920841 [Gating] SW mode calibration
5337 23:42:28.927328 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5338 23:42:28.933595 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5339 23:42:28.937060 0 14 0 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5340 23:42:28.943815 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5341 23:42:28.946728 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5342 23:42:28.950589 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5343 23:42:28.956875 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5344 23:42:28.959812 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5345 23:42:28.963124 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5346 23:42:28.969850 0 14 28 | B1->B0 | 3333 2727 | 0 0 | (0 1) (0 0)
5347 23:42:28.973448 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5348 23:42:28.976263 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5349 23:42:28.982877 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5350 23:42:28.986560 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5351 23:42:28.990240 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5352 23:42:28.996033 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5353 23:42:28.999649 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5354 23:42:29.003241 0 15 28 | B1->B0 | 2b2b 3939 | 0 0 | (0 0) (0 0)
5355 23:42:29.009801 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5356 23:42:29.012821 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5357 23:42:29.016141 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5358 23:42:29.022847 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5359 23:42:29.025787 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5360 23:42:29.029124 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5361 23:42:29.035612 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5362 23:42:29.038974 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5363 23:42:29.042638 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5364 23:42:29.048895 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 23:42:29.052061 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 23:42:29.055331 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 23:42:29.061754 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5368 23:42:29.065113 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5369 23:42:29.068605 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 23:42:29.075207 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 23:42:29.078608 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 23:42:29.081621 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 23:42:29.088334 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 23:42:29.092011 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 23:42:29.094855 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 23:42:29.101790 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 23:42:29.104848 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 23:42:29.108150 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5379 23:42:29.111785 Total UI for P1: 0, mck2ui 16
5380 23:42:29.114824 best dqsien dly found for B0: ( 1, 2, 26)
5381 23:42:29.121623 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 23:42:29.121713 Total UI for P1: 0, mck2ui 16
5383 23:42:29.127723 best dqsien dly found for B1: ( 1, 2, 28)
5384 23:42:29.131314 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5385 23:42:29.134514 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5386 23:42:29.134595
5387 23:42:29.138004 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5388 23:42:29.141631 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5389 23:42:29.144297 [Gating] SW calibration Done
5390 23:42:29.144385 ==
5391 23:42:29.147739 Dram Type= 6, Freq= 0, CH_0, rank 1
5392 23:42:29.151329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5393 23:42:29.151428 ==
5394 23:42:29.154661 RX Vref Scan: 0
5395 23:42:29.154731
5396 23:42:29.154789 RX Vref 0 -> 0, step: 1
5397 23:42:29.154847
5398 23:42:29.157768 RX Delay -80 -> 252, step: 8
5399 23:42:29.161243 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5400 23:42:29.167566 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5401 23:42:29.170613 iDelay=200, Bit 2, Center 95 (8 ~ 183) 176
5402 23:42:29.173923 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5403 23:42:29.177628 iDelay=200, Bit 4, Center 99 (8 ~ 191) 184
5404 23:42:29.180737 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5405 23:42:29.184091 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5406 23:42:29.190777 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5407 23:42:29.193996 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5408 23:42:29.196992 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5409 23:42:29.200508 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5410 23:42:29.203868 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5411 23:42:29.210561 iDelay=200, Bit 12, Center 91 (0 ~ 183) 184
5412 23:42:29.213507 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5413 23:42:29.216881 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5414 23:42:29.219947 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5415 23:42:29.220027 ==
5416 23:42:29.223514 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 23:42:29.230403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 23:42:29.230485 ==
5419 23:42:29.230548 DQS Delay:
5420 23:42:29.230607 DQS0 = 0, DQS1 = 0
5421 23:42:29.233483 DQM Delay:
5422 23:42:29.233564 DQM0 = 99, DQM1 = 88
5423 23:42:29.236618 DQ Delay:
5424 23:42:29.240458 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5425 23:42:29.243638 DQ4 =99, DQ5 =91, DQ6 =107, DQ7 =107
5426 23:42:29.246523 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5427 23:42:29.249855 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =91
5428 23:42:29.249953
5429 23:42:29.250047
5430 23:42:29.250134 ==
5431 23:42:29.253245 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 23:42:29.256896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 23:42:29.256991 ==
5434 23:42:29.257085
5435 23:42:29.257169
5436 23:42:29.260091 TX Vref Scan disable
5437 23:42:29.260191 == TX Byte 0 ==
5438 23:42:29.266330 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5439 23:42:29.269837 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5440 23:42:29.272934 == TX Byte 1 ==
5441 23:42:29.276420 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5442 23:42:29.279511 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5443 23:42:29.279596 ==
5444 23:42:29.282775 Dram Type= 6, Freq= 0, CH_0, rank 1
5445 23:42:29.286189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5446 23:42:29.289392 ==
5447 23:42:29.289542
5448 23:42:29.289635
5449 23:42:29.289723 TX Vref Scan disable
5450 23:42:29.293156 == TX Byte 0 ==
5451 23:42:29.296284 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5452 23:42:29.302870 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5453 23:42:29.302978 == TX Byte 1 ==
5454 23:42:29.306631 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5455 23:42:29.312833 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5456 23:42:29.312939
5457 23:42:29.313031 [DATLAT]
5458 23:42:29.313119 Freq=933, CH0 RK1
5459 23:42:29.313205
5460 23:42:29.316553 DATLAT Default: 0xb
5461 23:42:29.316631 0, 0xFFFF, sum = 0
5462 23:42:29.319742 1, 0xFFFF, sum = 0
5463 23:42:29.322616 2, 0xFFFF, sum = 0
5464 23:42:29.322718 3, 0xFFFF, sum = 0
5465 23:42:29.326044 4, 0xFFFF, sum = 0
5466 23:42:29.326157 5, 0xFFFF, sum = 0
5467 23:42:29.329019 6, 0xFFFF, sum = 0
5468 23:42:29.329123 7, 0xFFFF, sum = 0
5469 23:42:29.332444 8, 0xFFFF, sum = 0
5470 23:42:29.332519 9, 0xFFFF, sum = 0
5471 23:42:29.335589 10, 0x0, sum = 1
5472 23:42:29.335693 11, 0x0, sum = 2
5473 23:42:29.339135 12, 0x0, sum = 3
5474 23:42:29.339210 13, 0x0, sum = 4
5475 23:42:29.342632 best_step = 11
5476 23:42:29.342710
5477 23:42:29.342771 ==
5478 23:42:29.346214 Dram Type= 6, Freq= 0, CH_0, rank 1
5479 23:42:29.349160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5480 23:42:29.349301 ==
5481 23:42:29.349367 RX Vref Scan: 0
5482 23:42:29.349435
5483 23:42:29.352478 RX Vref 0 -> 0, step: 1
5484 23:42:29.352548
5485 23:42:29.355544 RX Delay -61 -> 252, step: 4
5486 23:42:29.362193 iDelay=195, Bit 0, Center 100 (15 ~ 186) 172
5487 23:42:29.365641 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5488 23:42:29.368918 iDelay=195, Bit 2, Center 94 (11 ~ 178) 168
5489 23:42:29.372186 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5490 23:42:29.375252 iDelay=195, Bit 4, Center 104 (19 ~ 190) 172
5491 23:42:29.382081 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5492 23:42:29.385204 iDelay=195, Bit 6, Center 108 (23 ~ 194) 172
5493 23:42:29.388775 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5494 23:42:29.391575 iDelay=195, Bit 8, Center 82 (-5 ~ 170) 176
5495 23:42:29.394873 iDelay=195, Bit 9, Center 80 (-5 ~ 166) 172
5496 23:42:29.401298 iDelay=195, Bit 10, Center 92 (7 ~ 178) 172
5497 23:42:29.405062 iDelay=195, Bit 11, Center 84 (-1 ~ 170) 172
5498 23:42:29.407881 iDelay=195, Bit 12, Center 94 (11 ~ 178) 168
5499 23:42:29.411490 iDelay=195, Bit 13, Center 94 (11 ~ 178) 168
5500 23:42:29.415194 iDelay=195, Bit 14, Center 100 (15 ~ 186) 172
5501 23:42:29.421355 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5502 23:42:29.421440 ==
5503 23:42:29.424556 Dram Type= 6, Freq= 0, CH_0, rank 1
5504 23:42:29.428107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5505 23:42:29.428210 ==
5506 23:42:29.428300 DQS Delay:
5507 23:42:29.431369 DQS0 = 0, DQS1 = 0
5508 23:42:29.431450 DQM Delay:
5509 23:42:29.434965 DQM0 = 100, DQM1 = 90
5510 23:42:29.435052 DQ Delay:
5511 23:42:29.437733 DQ0 =100, DQ1 =102, DQ2 =94, DQ3 =98
5512 23:42:29.441130 DQ4 =104, DQ5 =92, DQ6 =108, DQ7 =108
5513 23:42:29.444378 DQ8 =82, DQ9 =80, DQ10 =92, DQ11 =84
5514 23:42:29.447694 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =96
5515 23:42:29.447801
5516 23:42:29.447896
5517 23:42:29.457795 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 413 ps
5518 23:42:29.457905 CH0 RK1: MR19=505, MR18=1A16
5519 23:42:29.464404 CH0_RK1: MR19=0x505, MR18=0x1A16, DQSOSC=413, MR23=63, INC=63, DEC=42
5520 23:42:29.467762 [RxdqsGatingPostProcess] freq 933
5521 23:42:29.474081 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5522 23:42:29.477467 best DQS0 dly(2T, 0.5T) = (0, 10)
5523 23:42:29.481232 best DQS1 dly(2T, 0.5T) = (0, 10)
5524 23:42:29.483916 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5525 23:42:29.487228 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5526 23:42:29.490848 best DQS0 dly(2T, 0.5T) = (0, 10)
5527 23:42:29.493811 best DQS1 dly(2T, 0.5T) = (0, 10)
5528 23:42:29.497350 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5529 23:42:29.500728 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5530 23:42:29.500836 Pre-setting of DQS Precalculation
5531 23:42:29.507028 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5532 23:42:29.507108 ==
5533 23:42:29.510334 Dram Type= 6, Freq= 0, CH_1, rank 0
5534 23:42:29.513946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5535 23:42:29.514029 ==
5536 23:42:29.520639 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5537 23:42:29.526948 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5538 23:42:29.530174 [CA 0] Center 36 (6~67) winsize 62
5539 23:42:29.533871 [CA 1] Center 36 (6~67) winsize 62
5540 23:42:29.536873 [CA 2] Center 34 (4~65) winsize 62
5541 23:42:29.539859 [CA 3] Center 33 (3~64) winsize 62
5542 23:42:29.543248 [CA 4] Center 34 (3~65) winsize 63
5543 23:42:29.546781 [CA 5] Center 33 (3~64) winsize 62
5544 23:42:29.546882
5545 23:42:29.550105 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5546 23:42:29.550177
5547 23:42:29.553250 [CATrainingPosCal] consider 1 rank data
5548 23:42:29.556556 u2DelayCellTimex100 = 270/100 ps
5549 23:42:29.559854 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5550 23:42:29.563360 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5551 23:42:29.566759 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5552 23:42:29.569904 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5553 23:42:29.572969 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5554 23:42:29.579635 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5555 23:42:29.579745
5556 23:42:29.582730 CA PerBit enable=1, Macro0, CA PI delay=33
5557 23:42:29.582834
5558 23:42:29.586704 [CBTSetCACLKResult] CA Dly = 33
5559 23:42:29.586784 CS Dly: 5 (0~36)
5560 23:42:29.586846 ==
5561 23:42:29.589460 Dram Type= 6, Freq= 0, CH_1, rank 1
5562 23:42:29.596450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5563 23:42:29.596532 ==
5564 23:42:29.599328 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5565 23:42:29.606056 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5566 23:42:29.609144 [CA 0] Center 36 (6~66) winsize 61
5567 23:42:29.612467 [CA 1] Center 36 (6~67) winsize 62
5568 23:42:29.616002 [CA 2] Center 34 (4~64) winsize 61
5569 23:42:29.619319 [CA 3] Center 33 (3~64) winsize 62
5570 23:42:29.622392 [CA 4] Center 33 (3~64) winsize 62
5571 23:42:29.625923 [CA 5] Center 33 (3~64) winsize 62
5572 23:42:29.626003
5573 23:42:29.629061 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5574 23:42:29.629141
5575 23:42:29.632180 [CATrainingPosCal] consider 2 rank data
5576 23:42:29.635639 u2DelayCellTimex100 = 270/100 ps
5577 23:42:29.639198 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5578 23:42:29.642238 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5579 23:42:29.648542 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5580 23:42:29.652050 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5581 23:42:29.655086 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5582 23:42:29.658450 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5583 23:42:29.658530
5584 23:42:29.661933 CA PerBit enable=1, Macro0, CA PI delay=33
5585 23:42:29.662012
5586 23:42:29.665061 [CBTSetCACLKResult] CA Dly = 33
5587 23:42:29.665142 CS Dly: 6 (0~38)
5588 23:42:29.668829
5589 23:42:29.671642 ----->DramcWriteLeveling(PI) begin...
5590 23:42:29.671724 ==
5591 23:42:29.675133 Dram Type= 6, Freq= 0, CH_1, rank 0
5592 23:42:29.678528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5593 23:42:29.678610 ==
5594 23:42:29.681365 Write leveling (Byte 0): 24 => 24
5595 23:42:29.684855 Write leveling (Byte 1): 25 => 25
5596 23:42:29.688251 DramcWriteLeveling(PI) end<-----
5597 23:42:29.688331
5598 23:42:29.688393 ==
5599 23:42:29.691572 Dram Type= 6, Freq= 0, CH_1, rank 0
5600 23:42:29.694677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 23:42:29.694758 ==
5602 23:42:29.698319 [Gating] SW mode calibration
5603 23:42:29.704603 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5604 23:42:29.711323 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5605 23:42:29.714381 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5606 23:42:29.717759 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5607 23:42:29.724226 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5608 23:42:29.727847 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5609 23:42:29.731207 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5610 23:42:29.737758 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5611 23:42:29.740905 0 14 24 | B1->B0 | 3232 3232 | 0 0 | (0 0) (0 0)
5612 23:42:29.744127 0 14 28 | B1->B0 | 2929 2727 | 0 0 | (0 0) (0 0)
5613 23:42:29.750874 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5614 23:42:29.754421 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5615 23:42:29.757769 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5616 23:42:29.764250 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5617 23:42:29.767318 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5618 23:42:29.770460 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5619 23:42:29.777232 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5620 23:42:29.780560 0 15 28 | B1->B0 | 3e3e 4040 | 0 0 | (0 0) (0 0)
5621 23:42:29.784001 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5622 23:42:29.790549 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5623 23:42:29.793488 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5624 23:42:29.796827 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5625 23:42:29.803388 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5626 23:42:29.806840 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 23:42:29.810163 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 23:42:29.817090 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5629 23:42:29.820089 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5630 23:42:29.823608 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5631 23:42:29.829903 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5632 23:42:29.833094 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5633 23:42:29.836416 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5634 23:42:29.843385 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5635 23:42:29.846759 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 23:42:29.850086 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 23:42:29.856360 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 23:42:29.859603 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 23:42:29.863825 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 23:42:29.869413 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 23:42:29.872798 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 23:42:29.876093 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 23:42:29.882601 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5644 23:42:29.886030 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5645 23:42:29.889918 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 23:42:29.892632 Total UI for P1: 0, mck2ui 16
5647 23:42:29.896142 best dqsien dly found for B0: ( 1, 2, 26)
5648 23:42:29.899044 Total UI for P1: 0, mck2ui 16
5649 23:42:29.902768 best dqsien dly found for B1: ( 1, 2, 26)
5650 23:42:29.905860 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5651 23:42:29.909249 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5652 23:42:29.909355
5653 23:42:29.915988 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5654 23:42:29.919421 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5655 23:42:29.922244 [Gating] SW calibration Done
5656 23:42:29.922331 ==
5657 23:42:29.925804 Dram Type= 6, Freq= 0, CH_1, rank 0
5658 23:42:29.928865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5659 23:42:29.928973 ==
5660 23:42:29.929066 RX Vref Scan: 0
5661 23:42:29.929153
5662 23:42:29.932258 RX Vref 0 -> 0, step: 1
5663 23:42:29.932339
5664 23:42:29.935439 RX Delay -80 -> 252, step: 8
5665 23:42:29.938814 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5666 23:42:29.941910 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5667 23:42:29.948908 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5668 23:42:29.951685 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5669 23:42:29.955404 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5670 23:42:29.958574 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5671 23:42:29.961652 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5672 23:42:29.965028 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5673 23:42:29.971379 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5674 23:42:29.974878 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5675 23:42:29.978375 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5676 23:42:29.981820 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5677 23:42:29.985211 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5678 23:42:29.991455 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5679 23:42:29.995055 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5680 23:42:29.997846 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5681 23:42:29.997926 ==
5682 23:42:30.001238 Dram Type= 6, Freq= 0, CH_1, rank 0
5683 23:42:30.004533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5684 23:42:30.004614 ==
5685 23:42:30.007778 DQS Delay:
5686 23:42:30.007857 DQS0 = 0, DQS1 = 0
5687 23:42:30.011191 DQM Delay:
5688 23:42:30.011270 DQM0 = 101, DQM1 = 96
5689 23:42:30.011332 DQ Delay:
5690 23:42:30.014524 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =103
5691 23:42:30.018055 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5692 23:42:30.020937 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5693 23:42:30.027701 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5694 23:42:30.027805
5695 23:42:30.027898
5696 23:42:30.027984 ==
5697 23:42:30.031174 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 23:42:30.034843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 23:42:30.034942 ==
5700 23:42:30.035033
5701 23:42:30.035118
5702 23:42:30.037416 TX Vref Scan disable
5703 23:42:30.037507 == TX Byte 0 ==
5704 23:42:30.044346 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5705 23:42:30.047694 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5706 23:42:30.047793 == TX Byte 1 ==
5707 23:42:30.054016 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5708 23:42:30.057399 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5709 23:42:30.057476 ==
5710 23:42:30.060412 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 23:42:30.063807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 23:42:30.063887 ==
5713 23:42:30.066813
5714 23:42:30.066891
5715 23:42:30.066953 TX Vref Scan disable
5716 23:42:30.070448 == TX Byte 0 ==
5717 23:42:30.073622 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5718 23:42:30.080181 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5719 23:42:30.080261 == TX Byte 1 ==
5720 23:42:30.083872 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5721 23:42:30.090774 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5722 23:42:30.090855
5723 23:42:30.090917 [DATLAT]
5724 23:42:30.090974 Freq=933, CH1 RK0
5725 23:42:30.091030
5726 23:42:30.093697 DATLAT Default: 0xd
5727 23:42:30.093777 0, 0xFFFF, sum = 0
5728 23:42:30.097106 1, 0xFFFF, sum = 0
5729 23:42:30.100301 2, 0xFFFF, sum = 0
5730 23:42:30.100381 3, 0xFFFF, sum = 0
5731 23:42:30.103257 4, 0xFFFF, sum = 0
5732 23:42:30.103338 5, 0xFFFF, sum = 0
5733 23:42:30.106629 6, 0xFFFF, sum = 0
5734 23:42:30.106710 7, 0xFFFF, sum = 0
5735 23:42:30.109989 8, 0xFFFF, sum = 0
5736 23:42:30.110070 9, 0xFFFF, sum = 0
5737 23:42:30.113601 10, 0x0, sum = 1
5738 23:42:30.113682 11, 0x0, sum = 2
5739 23:42:30.116819 12, 0x0, sum = 3
5740 23:42:30.116904 13, 0x0, sum = 4
5741 23:42:30.119944 best_step = 11
5742 23:42:30.120023
5743 23:42:30.120085 ==
5744 23:42:30.123698 Dram Type= 6, Freq= 0, CH_1, rank 0
5745 23:42:30.126465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 23:42:30.126561 ==
5747 23:42:30.126624 RX Vref Scan: 1
5748 23:42:30.126695
5749 23:42:30.130029 RX Vref 0 -> 0, step: 1
5750 23:42:30.130108
5751 23:42:30.133045 RX Delay -53 -> 252, step: 4
5752 23:42:30.133144
5753 23:42:30.136498 Set Vref, RX VrefLevel [Byte0]: 51
5754 23:42:30.139637 [Byte1]: 52
5755 23:42:30.142997
5756 23:42:30.143101 Final RX Vref Byte 0 = 51 to rank0
5757 23:42:30.146430 Final RX Vref Byte 1 = 52 to rank0
5758 23:42:30.149788 Final RX Vref Byte 0 = 51 to rank1
5759 23:42:30.153389 Final RX Vref Byte 1 = 52 to rank1==
5760 23:42:30.156201 Dram Type= 6, Freq= 0, CH_1, rank 0
5761 23:42:30.162738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5762 23:42:30.162847 ==
5763 23:42:30.162939 DQS Delay:
5764 23:42:30.163032 DQS0 = 0, DQS1 = 0
5765 23:42:30.166167 DQM Delay:
5766 23:42:30.166264 DQM0 = 99, DQM1 = 95
5767 23:42:30.169184 DQ Delay:
5768 23:42:30.172572 DQ0 =106, DQ1 =94, DQ2 =88, DQ3 =100
5769 23:42:30.176289 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5770 23:42:30.179124 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =88
5771 23:42:30.182670 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5772 23:42:30.182772
5773 23:42:30.182862
5774 23:42:30.189377 [DQSOSCAuto] RK0, (LSB)MR18= 0x817, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5775 23:42:30.192746 CH1 RK0: MR19=505, MR18=817
5776 23:42:30.199438 CH1_RK0: MR19=0x505, MR18=0x817, DQSOSC=414, MR23=63, INC=63, DEC=42
5777 23:42:30.199541
5778 23:42:30.202486 ----->DramcWriteLeveling(PI) begin...
5779 23:42:30.202583 ==
5780 23:42:30.205946 Dram Type= 6, Freq= 0, CH_1, rank 1
5781 23:42:30.208806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5782 23:42:30.208903 ==
5783 23:42:30.212335 Write leveling (Byte 0): 28 => 28
5784 23:42:30.215218 Write leveling (Byte 1): 24 => 24
5785 23:42:30.218655 DramcWriteLeveling(PI) end<-----
5786 23:42:30.218758
5787 23:42:30.218832 ==
5788 23:42:30.222258 Dram Type= 6, Freq= 0, CH_1, rank 1
5789 23:42:30.228376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5790 23:42:30.228477 ==
5791 23:42:30.228569 [Gating] SW mode calibration
5792 23:42:30.238610 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5793 23:42:30.241674 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5794 23:42:30.245016 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5795 23:42:30.251624 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5796 23:42:30.255132 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 23:42:30.258750 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 23:42:30.264797 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 23:42:30.268286 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 23:42:30.271435 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5801 23:42:30.277970 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5802 23:42:30.281180 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5803 23:42:30.284853 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5804 23:42:30.291814 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 23:42:30.294480 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 23:42:30.298225 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 23:42:30.304532 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 23:42:30.307775 0 15 24 | B1->B0 | 2727 3131 | 0 0 | (0 0) (0 0)
5809 23:42:30.311418 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5810 23:42:30.317748 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5811 23:42:30.321173 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5812 23:42:30.324072 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 23:42:30.331099 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 23:42:30.333880 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 23:42:30.340894 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 23:42:30.343693 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 23:42:30.346872 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5818 23:42:30.353564 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5819 23:42:30.357169 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5820 23:42:30.360360 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 23:42:30.366694 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 23:42:30.370680 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 23:42:30.373624 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 23:42:30.380329 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 23:42:30.383507 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 23:42:30.386516 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 23:42:30.393626 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 23:42:30.396493 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 23:42:30.400063 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 23:42:30.406756 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 23:42:30.409972 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 23:42:30.412854 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5833 23:42:30.416337 Total UI for P1: 0, mck2ui 16
5834 23:42:30.419877 best dqsien dly found for B0: ( 1, 2, 22)
5835 23:42:30.422958 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5836 23:42:30.429429 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 23:42:30.433090 Total UI for P1: 0, mck2ui 16
5838 23:42:30.435951 best dqsien dly found for B1: ( 1, 2, 26)
5839 23:42:30.439277 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5840 23:42:30.442921 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5841 23:42:30.442999
5842 23:42:30.445944 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5843 23:42:30.449269 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5844 23:42:30.452785 [Gating] SW calibration Done
5845 23:42:30.452884 ==
5846 23:42:30.455793 Dram Type= 6, Freq= 0, CH_1, rank 1
5847 23:42:30.459562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5848 23:42:30.459676 ==
5849 23:42:30.462798 RX Vref Scan: 0
5850 23:42:30.462909
5851 23:42:30.465589 RX Vref 0 -> 0, step: 1
5852 23:42:30.465703
5853 23:42:30.465794 RX Delay -80 -> 252, step: 8
5854 23:42:30.472694 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5855 23:42:30.476368 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5856 23:42:30.479475 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5857 23:42:30.482672 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5858 23:42:30.486172 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5859 23:42:30.488934 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5860 23:42:30.495578 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5861 23:42:30.499055 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5862 23:42:30.502625 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5863 23:42:30.506133 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5864 23:42:30.509066 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5865 23:42:30.512560 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5866 23:42:30.518934 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5867 23:42:30.522152 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5868 23:42:30.525604 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5869 23:42:30.528975 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5870 23:42:30.529116 ==
5871 23:42:30.532494 Dram Type= 6, Freq= 0, CH_1, rank 1
5872 23:42:30.539059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5873 23:42:30.539166 ==
5874 23:42:30.539270 DQS Delay:
5875 23:42:30.539359 DQS0 = 0, DQS1 = 0
5876 23:42:30.542375 DQM Delay:
5877 23:42:30.542473 DQM0 = 97, DQM1 = 94
5878 23:42:30.545873 DQ Delay:
5879 23:42:30.549376 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5880 23:42:30.552152 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5881 23:42:30.555493 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5882 23:42:30.558951 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5883 23:42:30.559060
5884 23:42:30.559151
5885 23:42:30.559243 ==
5886 23:42:30.561900 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 23:42:30.565419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 23:42:30.565525 ==
5889 23:42:30.565616
5890 23:42:30.565706
5891 23:42:30.568585 TX Vref Scan disable
5892 23:42:30.571913 == TX Byte 0 ==
5893 23:42:30.575261 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5894 23:42:30.578651 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5895 23:42:30.581535 == TX Byte 1 ==
5896 23:42:30.585224 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5897 23:42:30.588393 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5898 23:42:30.588491 ==
5899 23:42:30.591843 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 23:42:30.598174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 23:42:30.598278 ==
5902 23:42:30.598369
5903 23:42:30.598462
5904 23:42:30.598548 TX Vref Scan disable
5905 23:42:30.601924 == TX Byte 0 ==
5906 23:42:30.605251 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5907 23:42:30.612132 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5908 23:42:30.612247 == TX Byte 1 ==
5909 23:42:30.615005 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5910 23:42:30.621689 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5911 23:42:30.621824
5912 23:42:30.621916 [DATLAT]
5913 23:42:30.622007 Freq=933, CH1 RK1
5914 23:42:30.622094
5915 23:42:30.625547 DATLAT Default: 0xb
5916 23:42:30.628314 0, 0xFFFF, sum = 0
5917 23:42:30.628418 1, 0xFFFF, sum = 0
5918 23:42:30.631725 2, 0xFFFF, sum = 0
5919 23:42:30.631836 3, 0xFFFF, sum = 0
5920 23:42:30.634830 4, 0xFFFF, sum = 0
5921 23:42:30.634935 5, 0xFFFF, sum = 0
5922 23:42:30.638486 6, 0xFFFF, sum = 0
5923 23:42:30.638575 7, 0xFFFF, sum = 0
5924 23:42:30.641469 8, 0xFFFF, sum = 0
5925 23:42:30.641574 9, 0xFFFF, sum = 0
5926 23:42:30.644951 10, 0x0, sum = 1
5927 23:42:30.645055 11, 0x0, sum = 2
5928 23:42:30.648294 12, 0x0, sum = 3
5929 23:42:30.648432 13, 0x0, sum = 4
5930 23:42:30.651741 best_step = 11
5931 23:42:30.651842
5932 23:42:30.651932 ==
5933 23:42:30.654656 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 23:42:30.657969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 23:42:30.658044 ==
5936 23:42:30.658116 RX Vref Scan: 0
5937 23:42:30.661115
5938 23:42:30.661216 RX Vref 0 -> 0, step: 1
5939 23:42:30.661372
5940 23:42:30.664688 RX Delay -53 -> 252, step: 4
5941 23:42:30.671358 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5942 23:42:30.674768 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5943 23:42:30.677677 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5944 23:42:30.681192 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5945 23:42:30.684704 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5946 23:42:30.687707 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5947 23:42:30.694213 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5948 23:42:30.697703 iDelay=199, Bit 7, Center 92 (-1 ~ 186) 188
5949 23:42:30.700801 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5950 23:42:30.704272 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5951 23:42:30.707422 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5952 23:42:30.714556 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5953 23:42:30.717269 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5954 23:42:30.720906 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5955 23:42:30.724213 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5956 23:42:30.730807 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5957 23:42:30.730923 ==
5958 23:42:30.733916 Dram Type= 6, Freq= 0, CH_1, rank 1
5959 23:42:30.737063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5960 23:42:30.737166 ==
5961 23:42:30.737267 DQS Delay:
5962 23:42:30.740343 DQS0 = 0, DQS1 = 0
5963 23:42:30.740419 DQM Delay:
5964 23:42:30.743897 DQM0 = 96, DQM1 = 92
5965 23:42:30.743973 DQ Delay:
5966 23:42:30.746807 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5967 23:42:30.750165 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5968 23:42:30.753250 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5969 23:42:30.756958 DQ12 =100, DQ13 =102, DQ14 =98, DQ15 =100
5970 23:42:30.757032
5971 23:42:30.757094
5972 23:42:30.766497 [DQSOSCAuto] RK1, (LSB)MR18= 0xb22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5973 23:42:30.766607 CH1 RK1: MR19=505, MR18=B22
5974 23:42:30.773175 CH1_RK1: MR19=0x505, MR18=0xB22, DQSOSC=411, MR23=63, INC=64, DEC=42
5975 23:42:30.776221 [RxdqsGatingPostProcess] freq 933
5976 23:42:30.782963 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5977 23:42:30.786393 best DQS0 dly(2T, 0.5T) = (0, 10)
5978 23:42:30.790002 best DQS1 dly(2T, 0.5T) = (0, 10)
5979 23:42:30.792685 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5980 23:42:30.796299 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5981 23:42:30.799481 best DQS0 dly(2T, 0.5T) = (0, 10)
5982 23:42:30.799582 best DQS1 dly(2T, 0.5T) = (0, 10)
5983 23:42:30.802714 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5984 23:42:30.805802 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5985 23:42:30.809611 Pre-setting of DQS Precalculation
5986 23:42:30.815741 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5987 23:42:30.822633 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5988 23:42:30.829495 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5989 23:42:30.829573
5990 23:42:30.829636
5991 23:42:30.832381 [Calibration Summary] 1866 Mbps
5992 23:42:30.835793 CH 0, Rank 0
5993 23:42:30.835903 SW Impedance : PASS
5994 23:42:30.838823 DUTY Scan : NO K
5995 23:42:30.842339 ZQ Calibration : PASS
5996 23:42:30.842439 Jitter Meter : NO K
5997 23:42:30.845739 CBT Training : PASS
5998 23:42:30.849086 Write leveling : PASS
5999 23:42:30.849184 RX DQS gating : PASS
6000 23:42:30.852434 RX DQ/DQS(RDDQC) : PASS
6001 23:42:30.852509 TX DQ/DQS : PASS
6002 23:42:30.855549 RX DATLAT : PASS
6003 23:42:30.858563 RX DQ/DQS(Engine): PASS
6004 23:42:30.858661 TX OE : NO K
6005 23:42:30.862192 All Pass.
6006 23:42:30.862290
6007 23:42:30.862377 CH 0, Rank 1
6008 23:42:30.865626 SW Impedance : PASS
6009 23:42:30.865726 DUTY Scan : NO K
6010 23:42:30.869210 ZQ Calibration : PASS
6011 23:42:30.872293 Jitter Meter : NO K
6012 23:42:30.872366 CBT Training : PASS
6013 23:42:30.875336 Write leveling : PASS
6014 23:42:30.878571 RX DQS gating : PASS
6015 23:42:30.878643 RX DQ/DQS(RDDQC) : PASS
6016 23:42:30.881778 TX DQ/DQS : PASS
6017 23:42:30.885132 RX DATLAT : PASS
6018 23:42:30.885233 RX DQ/DQS(Engine): PASS
6019 23:42:30.888630 TX OE : NO K
6020 23:42:30.888736 All Pass.
6021 23:42:30.888824
6022 23:42:30.891568 CH 1, Rank 0
6023 23:42:30.891664 SW Impedance : PASS
6024 23:42:30.895074 DUTY Scan : NO K
6025 23:42:30.898599 ZQ Calibration : PASS
6026 23:42:30.898705 Jitter Meter : NO K
6027 23:42:30.902071 CBT Training : PASS
6028 23:42:30.904932 Write leveling : PASS
6029 23:42:30.905035 RX DQS gating : PASS
6030 23:42:30.908509 RX DQ/DQS(RDDQC) : PASS
6031 23:42:30.911254 TX DQ/DQS : PASS
6032 23:42:30.911352 RX DATLAT : PASS
6033 23:42:30.914693 RX DQ/DQS(Engine): PASS
6034 23:42:30.917865 TX OE : NO K
6035 23:42:30.917960 All Pass.
6036 23:42:30.918056
6037 23:42:30.918143 CH 1, Rank 1
6038 23:42:30.921546 SW Impedance : PASS
6039 23:42:30.924976 DUTY Scan : NO K
6040 23:42:30.925082 ZQ Calibration : PASS
6041 23:42:30.928189 Jitter Meter : NO K
6042 23:42:30.928281 CBT Training : PASS
6043 23:42:30.931199 Write leveling : PASS
6044 23:42:30.934454 RX DQS gating : PASS
6045 23:42:30.934530 RX DQ/DQS(RDDQC) : PASS
6046 23:42:30.937923 TX DQ/DQS : PASS
6047 23:42:30.941580 RX DATLAT : PASS
6048 23:42:30.941666 RX DQ/DQS(Engine): PASS
6049 23:42:30.944400 TX OE : NO K
6050 23:42:30.944509 All Pass.
6051 23:42:30.944606
6052 23:42:30.947733 DramC Write-DBI off
6053 23:42:30.951348 PER_BANK_REFRESH: Hybrid Mode
6054 23:42:30.951447 TX_TRACKING: ON
6055 23:42:30.960987 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6056 23:42:30.964436 [FAST_K] Save calibration result to emmc
6057 23:42:30.967804 dramc_set_vcore_voltage set vcore to 650000
6058 23:42:30.970817 Read voltage for 400, 6
6059 23:42:30.970913 Vio18 = 0
6060 23:42:30.974082 Vcore = 650000
6061 23:42:30.974155 Vdram = 0
6062 23:42:30.974215 Vddq = 0
6063 23:42:30.974271 Vmddr = 0
6064 23:42:30.980607 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6065 23:42:30.987167 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6066 23:42:30.987280 MEM_TYPE=3, freq_sel=20
6067 23:42:30.990689 sv_algorithm_assistance_LP4_800
6068 23:42:30.993929 ============ PULL DRAM RESETB DOWN ============
6069 23:42:31.000413 ========== PULL DRAM RESETB DOWN end =========
6070 23:42:31.003433 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6071 23:42:31.006875 ===================================
6072 23:42:31.010313 LPDDR4 DRAM CONFIGURATION
6073 23:42:31.013360 ===================================
6074 23:42:31.013436 EX_ROW_EN[0] = 0x0
6075 23:42:31.016700 EX_ROW_EN[1] = 0x0
6076 23:42:31.019909 LP4Y_EN = 0x0
6077 23:42:31.020016 WORK_FSP = 0x0
6078 23:42:31.023642 WL = 0x2
6079 23:42:31.023746 RL = 0x2
6080 23:42:31.026799 BL = 0x2
6081 23:42:31.026897 RPST = 0x0
6082 23:42:31.029961 RD_PRE = 0x0
6083 23:42:31.030060 WR_PRE = 0x1
6084 23:42:31.033432 WR_PST = 0x0
6085 23:42:31.033533 DBI_WR = 0x0
6086 23:42:31.036612 DBI_RD = 0x0
6087 23:42:31.036685 OTF = 0x1
6088 23:42:31.039823 ===================================
6089 23:42:31.043079 ===================================
6090 23:42:31.046443 ANA top config
6091 23:42:31.049611 ===================================
6092 23:42:31.052706 DLL_ASYNC_EN = 0
6093 23:42:31.052805 ALL_SLAVE_EN = 1
6094 23:42:31.055887 NEW_RANK_MODE = 1
6095 23:42:31.059345 DLL_IDLE_MODE = 1
6096 23:42:31.062640 LP45_APHY_COMB_EN = 1
6097 23:42:31.062746 TX_ODT_DIS = 1
6098 23:42:31.066020 NEW_8X_MODE = 1
6099 23:42:31.069663 ===================================
6100 23:42:31.073080 ===================================
6101 23:42:31.076059 data_rate = 800
6102 23:42:31.079358 CKR = 1
6103 23:42:31.082592 DQ_P2S_RATIO = 4
6104 23:42:31.085769 ===================================
6105 23:42:31.089185 CA_P2S_RATIO = 4
6106 23:42:31.089331 DQ_CA_OPEN = 0
6107 23:42:31.092611 DQ_SEMI_OPEN = 1
6108 23:42:31.096026 CA_SEMI_OPEN = 1
6109 23:42:31.098974 CA_FULL_RATE = 0
6110 23:42:31.102462 DQ_CKDIV4_EN = 0
6111 23:42:31.106180 CA_CKDIV4_EN = 1
6112 23:42:31.106286 CA_PREDIV_EN = 0
6113 23:42:31.108797 PH8_DLY = 0
6114 23:42:31.112488 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6115 23:42:31.115798 DQ_AAMCK_DIV = 0
6116 23:42:31.118614 CA_AAMCK_DIV = 0
6117 23:42:31.122082 CA_ADMCK_DIV = 4
6118 23:42:31.122182 DQ_TRACK_CA_EN = 0
6119 23:42:31.125519 CA_PICK = 800
6120 23:42:31.128787 CA_MCKIO = 400
6121 23:42:31.132149 MCKIO_SEMI = 400
6122 23:42:31.135149 PLL_FREQ = 3016
6123 23:42:31.138730 DQ_UI_PI_RATIO = 32
6124 23:42:31.142028 CA_UI_PI_RATIO = 32
6125 23:42:31.145187 ===================================
6126 23:42:31.148759 ===================================
6127 23:42:31.151764 memory_type:LPDDR4
6128 23:42:31.151939 GP_NUM : 10
6129 23:42:31.155145 SRAM_EN : 1
6130 23:42:31.155247 MD32_EN : 0
6131 23:42:31.158675 ===================================
6132 23:42:31.161475 [ANA_INIT] >>>>>>>>>>>>>>
6133 23:42:31.164817 <<<<<< [CONFIGURE PHASE]: ANA_TX
6134 23:42:31.168530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6135 23:42:31.171799 ===================================
6136 23:42:31.174593 data_rate = 800,PCW = 0X7400
6137 23:42:31.178334 ===================================
6138 23:42:31.181584 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6139 23:42:31.187726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6140 23:42:31.197836 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6141 23:42:31.201407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6142 23:42:31.204290 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6143 23:42:31.207621 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6144 23:42:31.210784 [ANA_INIT] flow start
6145 23:42:31.214335 [ANA_INIT] PLL >>>>>>>>
6146 23:42:31.214432 [ANA_INIT] PLL <<<<<<<<
6147 23:42:31.217858 [ANA_INIT] MIDPI >>>>>>>>
6148 23:42:31.220874 [ANA_INIT] MIDPI <<<<<<<<
6149 23:42:31.224215 [ANA_INIT] DLL >>>>>>>>
6150 23:42:31.224316 [ANA_INIT] flow end
6151 23:42:31.227738 ============ LP4 DIFF to SE enter ============
6152 23:42:31.234141 ============ LP4 DIFF to SE exit ============
6153 23:42:31.234245 [ANA_INIT] <<<<<<<<<<<<<
6154 23:42:31.237535 [Flow] Enable top DCM control >>>>>
6155 23:42:31.240446 [Flow] Enable top DCM control <<<<<
6156 23:42:31.244244 Enable DLL master slave shuffle
6157 23:42:31.250340 ==============================================================
6158 23:42:31.253798 Gating Mode config
6159 23:42:31.257160 ==============================================================
6160 23:42:31.260344 Config description:
6161 23:42:31.270060 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6162 23:42:31.277035 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6163 23:42:31.280488 SELPH_MODE 0: By rank 1: By Phase
6164 23:42:31.286645 ==============================================================
6165 23:42:31.290071 GAT_TRACK_EN = 0
6166 23:42:31.293699 RX_GATING_MODE = 2
6167 23:42:31.296414 RX_GATING_TRACK_MODE = 2
6168 23:42:31.299858 SELPH_MODE = 1
6169 23:42:31.299956 PICG_EARLY_EN = 1
6170 23:42:31.303382 VALID_LAT_VALUE = 1
6171 23:42:31.309548 ==============================================================
6172 23:42:31.313220 Enter into Gating configuration >>>>
6173 23:42:31.316288 Exit from Gating configuration <<<<
6174 23:42:31.319833 Enter into DVFS_PRE_config >>>>>
6175 23:42:31.329464 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6176 23:42:31.332911 Exit from DVFS_PRE_config <<<<<
6177 23:42:31.336299 Enter into PICG configuration >>>>
6178 23:42:31.339066 Exit from PICG configuration <<<<
6179 23:42:31.342537 [RX_INPUT] configuration >>>>>
6180 23:42:31.345766 [RX_INPUT] configuration <<<<<
6181 23:42:31.352449 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6182 23:42:31.355857 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6183 23:42:31.362146 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6184 23:42:31.369169 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6185 23:42:31.375549 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6186 23:42:31.382331 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6187 23:42:31.385711 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6188 23:42:31.388462 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6189 23:42:31.392079 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6190 23:42:31.398702 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6191 23:42:31.402127 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6192 23:42:31.405285 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6193 23:42:31.408915 ===================================
6194 23:42:31.411660 LPDDR4 DRAM CONFIGURATION
6195 23:42:31.415090 ===================================
6196 23:42:31.418209 EX_ROW_EN[0] = 0x0
6197 23:42:31.418281 EX_ROW_EN[1] = 0x0
6198 23:42:31.421603 LP4Y_EN = 0x0
6199 23:42:31.421687 WORK_FSP = 0x0
6200 23:42:31.425103 WL = 0x2
6201 23:42:31.425212 RL = 0x2
6202 23:42:31.428501 BL = 0x2
6203 23:42:31.428570 RPST = 0x0
6204 23:42:31.431395 RD_PRE = 0x0
6205 23:42:31.431488 WR_PRE = 0x1
6206 23:42:31.434841 WR_PST = 0x0
6207 23:42:31.434911 DBI_WR = 0x0
6208 23:42:31.438047 DBI_RD = 0x0
6209 23:42:31.438139 OTF = 0x1
6210 23:42:31.441360 ===================================
6211 23:42:31.447833 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6212 23:42:31.451106 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6213 23:42:31.454695 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6214 23:42:31.458055 ===================================
6215 23:42:31.461366 LPDDR4 DRAM CONFIGURATION
6216 23:42:31.464214 ===================================
6217 23:42:31.467601 EX_ROW_EN[0] = 0x10
6218 23:42:31.467671 EX_ROW_EN[1] = 0x0
6219 23:42:31.471282 LP4Y_EN = 0x0
6220 23:42:31.471378 WORK_FSP = 0x0
6221 23:42:31.474382 WL = 0x2
6222 23:42:31.474451 RL = 0x2
6223 23:42:31.477622 BL = 0x2
6224 23:42:31.477689 RPST = 0x0
6225 23:42:31.480721 RD_PRE = 0x0
6226 23:42:31.480818 WR_PRE = 0x1
6227 23:42:31.484429 WR_PST = 0x0
6228 23:42:31.484523 DBI_WR = 0x0
6229 23:42:31.487714 DBI_RD = 0x0
6230 23:42:31.487812 OTF = 0x1
6231 23:42:31.491019 ===================================
6232 23:42:31.497038 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6233 23:42:31.502587 nWR fixed to 30
6234 23:42:31.505539 [ModeRegInit_LP4] CH0 RK0
6235 23:42:31.505627 [ModeRegInit_LP4] CH0 RK1
6236 23:42:31.508861 [ModeRegInit_LP4] CH1 RK0
6237 23:42:31.512440 [ModeRegInit_LP4] CH1 RK1
6238 23:42:31.512544 match AC timing 19
6239 23:42:31.518556 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6240 23:42:31.522591 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6241 23:42:31.525150 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6242 23:42:31.531767 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6243 23:42:31.535251 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6244 23:42:31.535327 ==
6245 23:42:31.538514 Dram Type= 6, Freq= 0, CH_0, rank 0
6246 23:42:31.541933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6247 23:42:31.542013 ==
6248 23:42:31.548427 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6249 23:42:31.555034 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6250 23:42:31.558001 [CA 0] Center 36 (8~64) winsize 57
6251 23:42:31.561515 [CA 1] Center 36 (8~64) winsize 57
6252 23:42:31.564713 [CA 2] Center 36 (8~64) winsize 57
6253 23:42:31.567887 [CA 3] Center 36 (8~64) winsize 57
6254 23:42:31.571148 [CA 4] Center 36 (8~64) winsize 57
6255 23:42:31.575052 [CA 5] Center 36 (8~64) winsize 57
6256 23:42:31.575161
6257 23:42:31.577892 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6258 23:42:31.577997
6259 23:42:31.581363 [CATrainingPosCal] consider 1 rank data
6260 23:42:31.584618 u2DelayCellTimex100 = 270/100 ps
6261 23:42:31.587859 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6262 23:42:31.591002 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6263 23:42:31.594617 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6264 23:42:31.597882 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6265 23:42:31.600987 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6266 23:42:31.604417 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6267 23:42:31.604499
6268 23:42:31.610936 CA PerBit enable=1, Macro0, CA PI delay=36
6269 23:42:31.611039
6270 23:42:31.611133 [CBTSetCACLKResult] CA Dly = 36
6271 23:42:31.613923 CS Dly: 1 (0~32)
6272 23:42:31.614025 ==
6273 23:42:31.617479 Dram Type= 6, Freq= 0, CH_0, rank 1
6274 23:42:31.620512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6275 23:42:31.620590 ==
6276 23:42:31.627359 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6277 23:42:31.634041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6278 23:42:31.637370 [CA 0] Center 36 (8~64) winsize 57
6279 23:42:31.640738 [CA 1] Center 36 (8~64) winsize 57
6280 23:42:31.644327 [CA 2] Center 36 (8~64) winsize 57
6281 23:42:31.647507 [CA 3] Center 36 (8~64) winsize 57
6282 23:42:31.647614 [CA 4] Center 36 (8~64) winsize 57
6283 23:42:31.650612 [CA 5] Center 36 (8~64) winsize 57
6284 23:42:31.650685
6285 23:42:31.657359 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6286 23:42:31.657435
6287 23:42:31.660423 [CATrainingPosCal] consider 2 rank data
6288 23:42:31.663757 u2DelayCellTimex100 = 270/100 ps
6289 23:42:31.667193 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 23:42:31.670431 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 23:42:31.673428 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 23:42:31.677357 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 23:42:31.680384 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 23:42:31.683778 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 23:42:31.683882
6296 23:42:31.686677 CA PerBit enable=1, Macro0, CA PI delay=36
6297 23:42:31.686782
6298 23:42:31.690402 [CBTSetCACLKResult] CA Dly = 36
6299 23:42:31.693609 CS Dly: 1 (0~32)
6300 23:42:31.693709
6301 23:42:31.697055 ----->DramcWriteLeveling(PI) begin...
6302 23:42:31.697183 ==
6303 23:42:31.700126 Dram Type= 6, Freq= 0, CH_0, rank 0
6304 23:42:31.703021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6305 23:42:31.703125 ==
6306 23:42:31.706615 Write leveling (Byte 0): 40 => 8
6307 23:42:31.709699 Write leveling (Byte 1): 40 => 8
6308 23:42:31.713201 DramcWriteLeveling(PI) end<-----
6309 23:42:31.713326
6310 23:42:31.713423 ==
6311 23:42:31.716734 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 23:42:31.720015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 23:42:31.720120 ==
6314 23:42:31.723531 [Gating] SW mode calibration
6315 23:42:31.729595 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6316 23:42:31.736158 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6317 23:42:31.739633 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6318 23:42:31.746368 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6319 23:42:31.749324 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6320 23:42:31.752732 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6321 23:42:31.759231 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6322 23:42:31.762761 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6323 23:42:31.765705 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6324 23:42:31.772327 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6325 23:42:31.775740 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6326 23:42:31.778935 Total UI for P1: 0, mck2ui 16
6327 23:42:31.782476 best dqsien dly found for B0: ( 0, 14, 24)
6328 23:42:31.785534 Total UI for P1: 0, mck2ui 16
6329 23:42:31.788794 best dqsien dly found for B1: ( 0, 14, 24)
6330 23:42:31.792278 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6331 23:42:31.795930 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6332 23:42:31.796039
6333 23:42:31.798716 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6334 23:42:31.802214 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6335 23:42:31.805189 [Gating] SW calibration Done
6336 23:42:31.805298 ==
6337 23:42:31.808866 Dram Type= 6, Freq= 0, CH_0, rank 0
6338 23:42:31.815485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6339 23:42:31.815592 ==
6340 23:42:31.815696 RX Vref Scan: 0
6341 23:42:31.815786
6342 23:42:31.818830 RX Vref 0 -> 0, step: 1
6343 23:42:31.818933
6344 23:42:31.822145 RX Delay -410 -> 252, step: 16
6345 23:42:31.824984 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6346 23:42:31.828404 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6347 23:42:31.835255 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6348 23:42:31.838173 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6349 23:42:31.841687 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6350 23:42:31.845179 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6351 23:42:31.851352 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6352 23:42:31.854768 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6353 23:42:31.858321 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6354 23:42:31.861242 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6355 23:42:31.868257 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6356 23:42:31.871215 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6357 23:42:31.874628 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6358 23:42:31.877750 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6359 23:42:31.884284 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6360 23:42:31.887915 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6361 23:42:31.888026 ==
6362 23:42:31.891313 Dram Type= 6, Freq= 0, CH_0, rank 0
6363 23:42:31.894240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6364 23:42:31.894344 ==
6365 23:42:31.897787 DQS Delay:
6366 23:42:31.897889 DQS0 = 35, DQS1 = 59
6367 23:42:31.901147 DQM Delay:
6368 23:42:31.901244 DQM0 = 4, DQM1 = 16
6369 23:42:31.904572 DQ Delay:
6370 23:42:31.904679 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6371 23:42:31.907529 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6372 23:42:31.910878 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6373 23:42:31.913926 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6374 23:42:31.914029
6375 23:42:31.914124
6376 23:42:31.914198 ==
6377 23:42:31.917412 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 23:42:31.923745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 23:42:31.923851 ==
6380 23:42:31.923943
6381 23:42:31.924029
6382 23:42:31.924118 TX Vref Scan disable
6383 23:42:31.927487 == TX Byte 0 ==
6384 23:42:31.930540 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6385 23:42:31.934054 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6386 23:42:31.936926 == TX Byte 1 ==
6387 23:42:31.940515 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6388 23:42:31.944136 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6389 23:42:31.947142 ==
6390 23:42:31.947244 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 23:42:31.953507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 23:42:31.953585 ==
6393 23:42:31.953648
6394 23:42:31.953709
6395 23:42:31.956705 TX Vref Scan disable
6396 23:42:31.956802 == TX Byte 0 ==
6397 23:42:31.960105 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6398 23:42:31.966901 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6399 23:42:31.967011 == TX Byte 1 ==
6400 23:42:31.969940 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 23:42:31.976915 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 23:42:31.976990
6403 23:42:31.977064 [DATLAT]
6404 23:42:31.977127 Freq=400, CH0 RK0
6405 23:42:31.977200
6406 23:42:31.979849 DATLAT Default: 0xf
6407 23:42:31.983238 0, 0xFFFF, sum = 0
6408 23:42:31.983312 1, 0xFFFF, sum = 0
6409 23:42:31.986671 2, 0xFFFF, sum = 0
6410 23:42:31.986747 3, 0xFFFF, sum = 0
6411 23:42:31.989983 4, 0xFFFF, sum = 0
6412 23:42:31.990082 5, 0xFFFF, sum = 0
6413 23:42:31.993409 6, 0xFFFF, sum = 0
6414 23:42:31.993484 7, 0xFFFF, sum = 0
6415 23:42:31.996865 8, 0xFFFF, sum = 0
6416 23:42:31.997020 9, 0xFFFF, sum = 0
6417 23:42:31.999932 10, 0xFFFF, sum = 0
6418 23:42:32.000031 11, 0xFFFF, sum = 0
6419 23:42:32.003487 12, 0xFFFF, sum = 0
6420 23:42:32.003584 13, 0x0, sum = 1
6421 23:42:32.006411 14, 0x0, sum = 2
6422 23:42:32.006482 15, 0x0, sum = 3
6423 23:42:32.009843 16, 0x0, sum = 4
6424 23:42:32.009938 best_step = 14
6425 23:42:32.010026
6426 23:42:32.010111 ==
6427 23:42:32.012703 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 23:42:32.019742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 23:42:32.019850 ==
6430 23:42:32.019941 RX Vref Scan: 1
6431 23:42:32.020027
6432 23:42:32.022732 RX Vref 0 -> 0, step: 1
6433 23:42:32.022854
6434 23:42:32.026118 RX Delay -359 -> 252, step: 8
6435 23:42:32.026216
6436 23:42:32.029381 Set Vref, RX VrefLevel [Byte0]: 58
6437 23:42:32.032428 [Byte1]: 49
6438 23:42:32.032501
6439 23:42:32.036100 Final RX Vref Byte 0 = 58 to rank0
6440 23:42:32.039307 Final RX Vref Byte 1 = 49 to rank0
6441 23:42:32.042372 Final RX Vref Byte 0 = 58 to rank1
6442 23:42:32.045866 Final RX Vref Byte 1 = 49 to rank1==
6443 23:42:32.049172 Dram Type= 6, Freq= 0, CH_0, rank 0
6444 23:42:32.055650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 23:42:32.055734 ==
6446 23:42:32.055796 DQS Delay:
6447 23:42:32.058883 DQS0 = 44, DQS1 = 60
6448 23:42:32.058977 DQM Delay:
6449 23:42:32.059067 DQM0 = 10, DQM1 = 17
6450 23:42:32.062634 DQ Delay:
6451 23:42:32.065549 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6452 23:42:32.065631 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6453 23:42:32.068795 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6454 23:42:32.072368 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =24
6455 23:42:32.075780
6456 23:42:32.075875
6457 23:42:32.081812 [DQSOSCAuto] RK0, (LSB)MR18= 0x9689, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6458 23:42:32.085445 CH0 RK0: MR19=C0C, MR18=9689
6459 23:42:32.091599 CH0_RK0: MR19=0xC0C, MR18=0x9689, DQSOSC=391, MR23=63, INC=386, DEC=257
6460 23:42:32.091700 ==
6461 23:42:32.095102 Dram Type= 6, Freq= 0, CH_0, rank 1
6462 23:42:32.098378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 23:42:32.098475 ==
6464 23:42:32.101836 [Gating] SW mode calibration
6465 23:42:32.108154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6466 23:42:32.114750 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6467 23:42:32.118143 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6468 23:42:32.121594 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6469 23:42:32.128138 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6470 23:42:32.131698 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6471 23:42:32.134744 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6472 23:42:32.141130 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6473 23:42:32.144458 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6474 23:42:32.148148 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6475 23:42:32.154589 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6476 23:42:32.157784 Total UI for P1: 0, mck2ui 16
6477 23:42:32.160983 best dqsien dly found for B0: ( 0, 14, 24)
6478 23:42:32.161082 Total UI for P1: 0, mck2ui 16
6479 23:42:32.167595 best dqsien dly found for B1: ( 0, 14, 24)
6480 23:42:32.171001 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6481 23:42:32.174674 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6482 23:42:32.174778
6483 23:42:32.177825 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6484 23:42:32.180954 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6485 23:42:32.184382 [Gating] SW calibration Done
6486 23:42:32.184482 ==
6487 23:42:32.187271 Dram Type= 6, Freq= 0, CH_0, rank 1
6488 23:42:32.191092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6489 23:42:32.191192 ==
6490 23:42:32.193926 RX Vref Scan: 0
6491 23:42:32.194022
6492 23:42:32.197422 RX Vref 0 -> 0, step: 1
6493 23:42:32.197522
6494 23:42:32.197613 RX Delay -410 -> 252, step: 16
6495 23:42:32.204495 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6496 23:42:32.207283 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6497 23:42:32.210776 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6498 23:42:32.217134 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6499 23:42:32.220204 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6500 23:42:32.223607 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6501 23:42:32.227176 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6502 23:42:32.233706 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6503 23:42:32.237154 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6504 23:42:32.240184 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6505 23:42:32.243312 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6506 23:42:32.250334 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6507 23:42:32.253744 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6508 23:42:32.256896 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6509 23:42:32.260183 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6510 23:42:32.266639 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6511 23:42:32.266753 ==
6512 23:42:32.269983 Dram Type= 6, Freq= 0, CH_0, rank 1
6513 23:42:32.273010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 23:42:32.273135 ==
6515 23:42:32.273228 DQS Delay:
6516 23:42:32.276423 DQS0 = 35, DQS1 = 59
6517 23:42:32.276520 DQM Delay:
6518 23:42:32.280274 DQM0 = 6, DQM1 = 17
6519 23:42:32.280382 DQ Delay:
6520 23:42:32.283121 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6521 23:42:32.286189 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6522 23:42:32.289671 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6523 23:42:32.293323 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6524 23:42:32.293435
6525 23:42:32.293523
6526 23:42:32.293607 ==
6527 23:42:32.296352 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 23:42:32.299863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 23:42:32.299972 ==
6530 23:42:32.300064
6531 23:42:32.302885
6532 23:42:32.303011 TX Vref Scan disable
6533 23:42:32.306385 == TX Byte 0 ==
6534 23:42:32.309266 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6535 23:42:32.312535 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6536 23:42:32.315916 == TX Byte 1 ==
6537 23:42:32.319126 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6538 23:42:32.322480 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6539 23:42:32.322579 ==
6540 23:42:32.325871 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 23:42:32.329407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 23:42:32.332813 ==
6543 23:42:32.332911
6544 23:42:32.333009
6545 23:42:32.333096 TX Vref Scan disable
6546 23:42:32.335964 == TX Byte 0 ==
6547 23:42:32.339340 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6548 23:42:32.342301 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6549 23:42:32.346119 == TX Byte 1 ==
6550 23:42:32.349066 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6551 23:42:32.352588 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6552 23:42:32.352686
6553 23:42:32.352774 [DATLAT]
6554 23:42:32.355873 Freq=400, CH0 RK1
6555 23:42:32.355951
6556 23:42:32.359405 DATLAT Default: 0xe
6557 23:42:32.359502 0, 0xFFFF, sum = 0
6558 23:42:32.362163 1, 0xFFFF, sum = 0
6559 23:42:32.362235 2, 0xFFFF, sum = 0
6560 23:42:32.365558 3, 0xFFFF, sum = 0
6561 23:42:32.365667 4, 0xFFFF, sum = 0
6562 23:42:32.368985 5, 0xFFFF, sum = 0
6563 23:42:32.369099 6, 0xFFFF, sum = 0
6564 23:42:32.372527 7, 0xFFFF, sum = 0
6565 23:42:32.372644 8, 0xFFFF, sum = 0
6566 23:42:32.375758 9, 0xFFFF, sum = 0
6567 23:42:32.375873 10, 0xFFFF, sum = 0
6568 23:42:32.379350 11, 0xFFFF, sum = 0
6569 23:42:32.379454 12, 0xFFFF, sum = 0
6570 23:42:32.382169 13, 0x0, sum = 1
6571 23:42:32.382277 14, 0x0, sum = 2
6572 23:42:32.386277 15, 0x0, sum = 3
6573 23:42:32.386364 16, 0x0, sum = 4
6574 23:42:32.389034 best_step = 14
6575 23:42:32.389132
6576 23:42:32.389224 ==
6577 23:42:32.392199 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 23:42:32.395419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 23:42:32.395526 ==
6580 23:42:32.398862 RX Vref Scan: 0
6581 23:42:32.399033
6582 23:42:32.399185 RX Vref 0 -> 0, step: 1
6583 23:42:32.399284
6584 23:42:32.402208 RX Delay -359 -> 252, step: 8
6585 23:42:32.410017 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6586 23:42:32.413081 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6587 23:42:32.416648 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6588 23:42:32.422890 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
6589 23:42:32.426234 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6590 23:42:32.429806 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6591 23:42:32.433116 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6592 23:42:32.439641 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6593 23:42:32.443048 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6594 23:42:32.446568 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6595 23:42:32.449391 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6596 23:42:32.455962 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6597 23:42:32.459117 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6598 23:42:32.462557 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6599 23:42:32.465607 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6600 23:42:32.472654 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6601 23:42:32.472736 ==
6602 23:42:32.475550 Dram Type= 6, Freq= 0, CH_0, rank 1
6603 23:42:32.478927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6604 23:42:32.479025 ==
6605 23:42:32.482226 DQS Delay:
6606 23:42:32.482322 DQS0 = 44, DQS1 = 60
6607 23:42:32.482398 DQM Delay:
6608 23:42:32.485834 DQM0 = 10, DQM1 = 14
6609 23:42:32.485944 DQ Delay:
6610 23:42:32.489178 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6611 23:42:32.492111 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6612 23:42:32.495468 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6613 23:42:32.499049 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6614 23:42:32.499154
6615 23:42:32.499232
6616 23:42:32.508868 [DQSOSCAuto] RK1, (LSB)MR18= 0x9088, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6617 23:42:32.508966 CH0 RK1: MR19=C0C, MR18=9088
6618 23:42:32.515553 CH0_RK1: MR19=0xC0C, MR18=0x9088, DQSOSC=391, MR23=63, INC=386, DEC=257
6619 23:42:32.518455 [RxdqsGatingPostProcess] freq 400
6620 23:42:32.524952 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6621 23:42:32.528204 best DQS0 dly(2T, 0.5T) = (0, 10)
6622 23:42:32.531695 best DQS1 dly(2T, 0.5T) = (0, 10)
6623 23:42:32.535266 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6624 23:42:32.538143 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6625 23:42:32.541710 best DQS0 dly(2T, 0.5T) = (0, 10)
6626 23:42:32.544670 best DQS1 dly(2T, 0.5T) = (0, 10)
6627 23:42:32.548147 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6628 23:42:32.551621 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6629 23:42:32.551717 Pre-setting of DQS Precalculation
6630 23:42:32.557897 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6631 23:42:32.557983 ==
6632 23:42:32.561315 Dram Type= 6, Freq= 0, CH_1, rank 0
6633 23:42:32.564899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6634 23:42:32.565004 ==
6635 23:42:32.571087 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6636 23:42:32.577945 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6637 23:42:32.581077 [CA 0] Center 36 (8~64) winsize 57
6638 23:42:32.584511 [CA 1] Center 36 (8~64) winsize 57
6639 23:42:32.587940 [CA 2] Center 36 (8~64) winsize 57
6640 23:42:32.591039 [CA 3] Center 36 (8~64) winsize 57
6641 23:42:32.591142 [CA 4] Center 36 (8~64) winsize 57
6642 23:42:32.594741 [CA 5] Center 36 (8~64) winsize 57
6643 23:42:32.594843
6644 23:42:32.601022 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6645 23:42:32.601125
6646 23:42:32.604522 [CATrainingPosCal] consider 1 rank data
6647 23:42:32.607553 u2DelayCellTimex100 = 270/100 ps
6648 23:42:32.610970 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6649 23:42:32.613999 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6650 23:42:32.617398 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6651 23:42:32.620857 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6652 23:42:32.623887 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6653 23:42:32.627241 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6654 23:42:32.627366
6655 23:42:32.630846 CA PerBit enable=1, Macro0, CA PI delay=36
6656 23:42:32.630950
6657 23:42:32.634065 [CBTSetCACLKResult] CA Dly = 36
6658 23:42:32.637441 CS Dly: 1 (0~32)
6659 23:42:32.637534 ==
6660 23:42:32.640634 Dram Type= 6, Freq= 0, CH_1, rank 1
6661 23:42:32.644425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6662 23:42:32.644500 ==
6663 23:42:32.650518 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6664 23:42:32.656906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6665 23:42:32.660709 [CA 0] Center 36 (8~64) winsize 57
6666 23:42:32.663604 [CA 1] Center 36 (8~64) winsize 57
6667 23:42:32.663705 [CA 2] Center 36 (8~64) winsize 57
6668 23:42:32.667246 [CA 3] Center 36 (8~64) winsize 57
6669 23:42:32.670704 [CA 4] Center 36 (8~64) winsize 57
6670 23:42:32.673535 [CA 5] Center 36 (8~64) winsize 57
6671 23:42:32.673648
6672 23:42:32.676763 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6673 23:42:32.680634
6674 23:42:32.683664 [CATrainingPosCal] consider 2 rank data
6675 23:42:32.683762 u2DelayCellTimex100 = 270/100 ps
6676 23:42:32.689972 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 23:42:32.693403 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 23:42:32.696720 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 23:42:32.700275 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 23:42:32.703507 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 23:42:32.706439 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 23:42:32.706536
6683 23:42:32.709984 CA PerBit enable=1, Macro0, CA PI delay=36
6684 23:42:32.710054
6685 23:42:32.713117 [CBTSetCACLKResult] CA Dly = 36
6686 23:42:32.716696 CS Dly: 1 (0~32)
6687 23:42:32.716795
6688 23:42:32.719601 ----->DramcWriteLeveling(PI) begin...
6689 23:42:32.719709 ==
6690 23:42:32.723060 Dram Type= 6, Freq= 0, CH_1, rank 0
6691 23:42:32.726666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6692 23:42:32.726776 ==
6693 23:42:32.729967 Write leveling (Byte 0): 40 => 8
6694 23:42:32.733647 Write leveling (Byte 1): 40 => 8
6695 23:42:32.736813 DramcWriteLeveling(PI) end<-----
6696 23:42:32.736925
6697 23:42:32.737012 ==
6698 23:42:32.739785 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 23:42:32.743359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 23:42:32.743485 ==
6701 23:42:32.746623 [Gating] SW mode calibration
6702 23:42:32.752839 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6703 23:42:32.759499 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6704 23:42:32.762928 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6705 23:42:32.766138 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6706 23:42:32.772821 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6707 23:42:32.775744 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6708 23:42:32.779561 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6709 23:42:32.785663 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6710 23:42:32.789092 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6711 23:42:32.792618 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6712 23:42:32.799255 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6713 23:42:32.802357 Total UI for P1: 0, mck2ui 16
6714 23:42:32.805502 best dqsien dly found for B0: ( 0, 14, 24)
6715 23:42:32.808844 Total UI for P1: 0, mck2ui 16
6716 23:42:32.812475 best dqsien dly found for B1: ( 0, 14, 24)
6717 23:42:32.815781 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6718 23:42:32.818837 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6719 23:42:32.818934
6720 23:42:32.822272 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6721 23:42:32.825457 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6722 23:42:32.828634 [Gating] SW calibration Done
6723 23:42:32.828729 ==
6724 23:42:32.832064 Dram Type= 6, Freq= 0, CH_1, rank 0
6725 23:42:32.835680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6726 23:42:32.835749 ==
6727 23:42:32.838562 RX Vref Scan: 0
6728 23:42:32.838633
6729 23:42:32.842141 RX Vref 0 -> 0, step: 1
6730 23:42:32.842219
6731 23:42:32.842284 RX Delay -410 -> 252, step: 16
6732 23:42:32.848571 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6733 23:42:32.852190 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6734 23:42:32.855526 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6735 23:42:32.862125 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6736 23:42:32.865070 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6737 23:42:32.868406 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6738 23:42:32.871947 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6739 23:42:32.878284 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6740 23:42:32.881634 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6741 23:42:32.884995 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6742 23:42:32.888307 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6743 23:42:32.894726 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6744 23:42:32.898307 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6745 23:42:32.901600 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6746 23:42:32.904794 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6747 23:42:32.911505 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6748 23:42:32.911624 ==
6749 23:42:32.914716 Dram Type= 6, Freq= 0, CH_1, rank 0
6750 23:42:32.918403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6751 23:42:32.918509 ==
6752 23:42:32.918605 DQS Delay:
6753 23:42:32.921586 DQS0 = 43, DQS1 = 51
6754 23:42:32.921671 DQM Delay:
6755 23:42:32.924333 DQM0 = 13, DQM1 = 13
6756 23:42:32.924411 DQ Delay:
6757 23:42:32.928072 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6758 23:42:32.931248 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6759 23:42:32.934373 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6760 23:42:32.937936 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6761 23:42:32.938048
6762 23:42:32.938141
6763 23:42:32.938240 ==
6764 23:42:32.941065 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 23:42:32.944567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 23:42:32.944671 ==
6767 23:42:32.948027
6768 23:42:32.948125
6769 23:42:32.948223 TX Vref Scan disable
6770 23:42:32.950936 == TX Byte 0 ==
6771 23:42:32.954567 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 23:42:32.957588 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 23:42:32.960905 == TX Byte 1 ==
6774 23:42:32.964066 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6775 23:42:32.967408 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6776 23:42:32.967518 ==
6777 23:42:32.970658 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 23:42:32.974006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 23:42:32.977176 ==
6780 23:42:32.977301
6781 23:42:32.977396
6782 23:42:32.977496 TX Vref Scan disable
6783 23:42:32.980478 == TX Byte 0 ==
6784 23:42:32.983694 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 23:42:32.987173 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 23:42:32.990494 == TX Byte 1 ==
6787 23:42:32.993940 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 23:42:32.996886 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 23:42:32.996992
6790 23:42:33.000223 [DATLAT]
6791 23:42:33.000316 Freq=400, CH1 RK0
6792 23:42:33.000395
6793 23:42:33.003831 DATLAT Default: 0xf
6794 23:42:33.003937 0, 0xFFFF, sum = 0
6795 23:42:33.007276 1, 0xFFFF, sum = 0
6796 23:42:33.007389 2, 0xFFFF, sum = 0
6797 23:42:33.010456 3, 0xFFFF, sum = 0
6798 23:42:33.010564 4, 0xFFFF, sum = 0
6799 23:42:33.013369 5, 0xFFFF, sum = 0
6800 23:42:33.013465 6, 0xFFFF, sum = 0
6801 23:42:33.016554 7, 0xFFFF, sum = 0
6802 23:42:33.016656 8, 0xFFFF, sum = 0
6803 23:42:33.019844 9, 0xFFFF, sum = 0
6804 23:42:33.019952 10, 0xFFFF, sum = 0
6805 23:42:33.023432 11, 0xFFFF, sum = 0
6806 23:42:33.026436 12, 0xFFFF, sum = 0
6807 23:42:33.026543 13, 0x0, sum = 1
6808 23:42:33.030183 14, 0x0, sum = 2
6809 23:42:33.030290 15, 0x0, sum = 3
6810 23:42:33.030402 16, 0x0, sum = 4
6811 23:42:33.033119 best_step = 14
6812 23:42:33.033235
6813 23:42:33.033346 ==
6814 23:42:33.036483 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 23:42:33.040100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 23:42:33.040204 ==
6817 23:42:33.043214 RX Vref Scan: 1
6818 23:42:33.043335
6819 23:42:33.046519 RX Vref 0 -> 0, step: 1
6820 23:42:33.046629
6821 23:42:33.046723 RX Delay -343 -> 252, step: 8
6822 23:42:33.046812
6823 23:42:33.049501 Set Vref, RX VrefLevel [Byte0]: 51
6824 23:42:33.052896 [Byte1]: 52
6825 23:42:33.058403
6826 23:42:33.058511 Final RX Vref Byte 0 = 51 to rank0
6827 23:42:33.061930 Final RX Vref Byte 1 = 52 to rank0
6828 23:42:33.064774 Final RX Vref Byte 0 = 51 to rank1
6829 23:42:33.068214 Final RX Vref Byte 1 = 52 to rank1==
6830 23:42:33.071483 Dram Type= 6, Freq= 0, CH_1, rank 0
6831 23:42:33.078020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 23:42:33.078134 ==
6833 23:42:33.078237 DQS Delay:
6834 23:42:33.081348 DQS0 = 44, DQS1 = 52
6835 23:42:33.081427 DQM Delay:
6836 23:42:33.081489 DQM0 = 11, DQM1 = 10
6837 23:42:33.085060 DQ Delay:
6838 23:42:33.088239 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6839 23:42:33.091090 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =4
6840 23:42:33.091188 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6841 23:42:33.094329 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6842 23:42:33.097816
6843 23:42:33.097891
6844 23:42:33.104416 [DQSOSCAuto] RK0, (LSB)MR18= 0x7097, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 395 ps
6845 23:42:33.107972 CH1 RK0: MR19=C0C, MR18=7097
6846 23:42:33.114159 CH1_RK0: MR19=0xC0C, MR18=0x7097, DQSOSC=390, MR23=63, INC=388, DEC=258
6847 23:42:33.114265 ==
6848 23:42:33.117521 Dram Type= 6, Freq= 0, CH_1, rank 1
6849 23:42:33.121053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 23:42:33.121153 ==
6851 23:42:33.124446 [Gating] SW mode calibration
6852 23:42:33.131249 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6853 23:42:33.137384 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6854 23:42:33.141035 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6855 23:42:33.144320 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6856 23:42:33.150688 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6857 23:42:33.153990 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6858 23:42:33.157444 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6859 23:42:33.163646 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6860 23:42:33.167019 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6861 23:42:33.170463 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6862 23:42:33.177067 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6863 23:42:33.177180 Total UI for P1: 0, mck2ui 16
6864 23:42:33.183619 best dqsien dly found for B0: ( 0, 14, 24)
6865 23:42:33.183728 Total UI for P1: 0, mck2ui 16
6866 23:42:33.190260 best dqsien dly found for B1: ( 0, 14, 24)
6867 23:42:33.193464 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6868 23:42:33.196794 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6869 23:42:33.196909
6870 23:42:33.200248 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6871 23:42:33.203745 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6872 23:42:33.206501 [Gating] SW calibration Done
6873 23:42:33.206620 ==
6874 23:42:33.210273 Dram Type= 6, Freq= 0, CH_1, rank 1
6875 23:42:33.213292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6876 23:42:33.213372 ==
6877 23:42:33.216525 RX Vref Scan: 0
6878 23:42:33.216619
6879 23:42:33.216710 RX Vref 0 -> 0, step: 1
6880 23:42:33.220057
6881 23:42:33.220159 RX Delay -410 -> 252, step: 16
6882 23:42:33.226872 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6883 23:42:33.229832 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6884 23:42:33.233273 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6885 23:42:33.236666 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6886 23:42:33.243247 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6887 23:42:33.246494 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6888 23:42:33.250158 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6889 23:42:33.252991 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6890 23:42:33.259336 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6891 23:42:33.262609 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6892 23:42:33.266153 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6893 23:42:33.272862 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6894 23:42:33.276050 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6895 23:42:33.279155 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6896 23:42:33.282521 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6897 23:42:33.289203 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6898 23:42:33.289322 ==
6899 23:42:33.292405 Dram Type= 6, Freq= 0, CH_1, rank 1
6900 23:42:33.295687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 23:42:33.295793 ==
6902 23:42:33.295886 DQS Delay:
6903 23:42:33.298935 DQS0 = 43, DQS1 = 51
6904 23:42:33.299006 DQM Delay:
6905 23:42:33.302584 DQM0 = 9, DQM1 = 14
6906 23:42:33.302684 DQ Delay:
6907 23:42:33.305422 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6908 23:42:33.308792 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6909 23:42:33.312201 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6910 23:42:33.315411 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6911 23:42:33.315516
6912 23:42:33.315612
6913 23:42:33.315700 ==
6914 23:42:33.318556 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 23:42:33.321874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 23:42:33.321983 ==
6917 23:42:33.322076
6918 23:42:33.325181
6919 23:42:33.325286 TX Vref Scan disable
6920 23:42:33.328588 == TX Byte 0 ==
6921 23:42:33.332144 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6922 23:42:33.335268 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6923 23:42:33.338563 == TX Byte 1 ==
6924 23:42:33.341493 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6925 23:42:33.345055 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6926 23:42:33.345161 ==
6927 23:42:33.348324 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 23:42:33.351439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 23:42:33.354661 ==
6930 23:42:33.354745
6931 23:42:33.354827
6932 23:42:33.354892 TX Vref Scan disable
6933 23:42:33.358330 == TX Byte 0 ==
6934 23:42:33.361817 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6935 23:42:33.364979 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6936 23:42:33.368000 == TX Byte 1 ==
6937 23:42:33.371488 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6938 23:42:33.374817 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6939 23:42:33.374927
6940 23:42:33.378070 [DATLAT]
6941 23:42:33.378142 Freq=400, CH1 RK1
6942 23:42:33.378202
6943 23:42:33.380965 DATLAT Default: 0xe
6944 23:42:33.381073 0, 0xFFFF, sum = 0
6945 23:42:33.384508 1, 0xFFFF, sum = 0
6946 23:42:33.384612 2, 0xFFFF, sum = 0
6947 23:42:33.387915 3, 0xFFFF, sum = 0
6948 23:42:33.388016 4, 0xFFFF, sum = 0
6949 23:42:33.390919 5, 0xFFFF, sum = 0
6950 23:42:33.391017 6, 0xFFFF, sum = 0
6951 23:42:33.394306 7, 0xFFFF, sum = 0
6952 23:42:33.394416 8, 0xFFFF, sum = 0
6953 23:42:33.397574 9, 0xFFFF, sum = 0
6954 23:42:33.397650 10, 0xFFFF, sum = 0
6955 23:42:33.400926 11, 0xFFFF, sum = 0
6956 23:42:33.401028 12, 0xFFFF, sum = 0
6957 23:42:33.404359 13, 0x0, sum = 1
6958 23:42:33.404456 14, 0x0, sum = 2
6959 23:42:33.407699 15, 0x0, sum = 3
6960 23:42:33.407802 16, 0x0, sum = 4
6961 23:42:33.411044 best_step = 14
6962 23:42:33.411140
6963 23:42:33.411229 ==
6964 23:42:33.414048 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 23:42:33.417275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 23:42:33.417348 ==
6967 23:42:33.420762 RX Vref Scan: 0
6968 23:42:33.420862
6969 23:42:33.420951 RX Vref 0 -> 0, step: 1
6970 23:42:33.421037
6971 23:42:33.424027 RX Delay -343 -> 252, step: 8
6972 23:42:33.432142 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6973 23:42:33.435408 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6974 23:42:33.439076 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6975 23:42:33.445385 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6976 23:42:33.448791 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6977 23:42:33.452428 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6978 23:42:33.455328 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6979 23:42:33.462158 iDelay=217, Bit 7, Center -36 (-279 ~ 208) 488
6980 23:42:33.465122 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6981 23:42:33.468607 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6982 23:42:33.471955 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6983 23:42:33.478186 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6984 23:42:33.481429 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6985 23:42:33.484900 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6986 23:42:33.488373 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6987 23:42:33.494762 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6988 23:42:33.494867 ==
6989 23:42:33.498162 Dram Type= 6, Freq= 0, CH_1, rank 1
6990 23:42:33.501079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6991 23:42:33.501180 ==
6992 23:42:33.504718 DQS Delay:
6993 23:42:33.504818 DQS0 = 48, DQS1 = 52
6994 23:42:33.504908 DQM Delay:
6995 23:42:33.507885 DQM0 = 12, DQM1 = 11
6996 23:42:33.507982 DQ Delay:
6997 23:42:33.511257 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
6998 23:42:33.514226 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =12
6999 23:42:33.517928 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7000 23:42:33.521210 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7001 23:42:33.521321
7002 23:42:33.521411
7003 23:42:33.531207 [DQSOSCAuto] RK1, (LSB)MR18= 0x78af, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7004 23:42:33.531286 CH1 RK1: MR19=C0C, MR18=78AF
7005 23:42:33.537538 CH1_RK1: MR19=0xC0C, MR18=0x78AF, DQSOSC=388, MR23=63, INC=392, DEC=261
7006 23:42:33.541004 [RxdqsGatingPostProcess] freq 400
7007 23:42:33.547409 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7008 23:42:33.550899 best DQS0 dly(2T, 0.5T) = (0, 10)
7009 23:42:33.553811 best DQS1 dly(2T, 0.5T) = (0, 10)
7010 23:42:33.557227 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7011 23:42:33.560836 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7012 23:42:33.563695 best DQS0 dly(2T, 0.5T) = (0, 10)
7013 23:42:33.566989 best DQS1 dly(2T, 0.5T) = (0, 10)
7014 23:42:33.570539 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7015 23:42:33.573627 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7016 23:42:33.577116 Pre-setting of DQS Precalculation
7017 23:42:33.580597 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7018 23:42:33.586935 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7019 23:42:33.593676 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7020 23:42:33.593782
7021 23:42:33.596621
7022 23:42:33.596722 [Calibration Summary] 800 Mbps
7023 23:42:33.600140 CH 0, Rank 0
7024 23:42:33.600237 SW Impedance : PASS
7025 23:42:33.603184 DUTY Scan : NO K
7026 23:42:33.606557 ZQ Calibration : PASS
7027 23:42:33.606663 Jitter Meter : NO K
7028 23:42:33.609766 CBT Training : PASS
7029 23:42:33.612899 Write leveling : PASS
7030 23:42:33.612997 RX DQS gating : PASS
7031 23:42:33.616310 RX DQ/DQS(RDDQC) : PASS
7032 23:42:33.619834 TX DQ/DQS : PASS
7033 23:42:33.619938 RX DATLAT : PASS
7034 23:42:33.622621 RX DQ/DQS(Engine): PASS
7035 23:42:33.626292 TX OE : NO K
7036 23:42:33.626389 All Pass.
7037 23:42:33.626488
7038 23:42:33.626576 CH 0, Rank 1
7039 23:42:33.629495 SW Impedance : PASS
7040 23:42:33.632692 DUTY Scan : NO K
7041 23:42:33.632789 ZQ Calibration : PASS
7042 23:42:33.636295 Jitter Meter : NO K
7043 23:42:33.639173 CBT Training : PASS
7044 23:42:33.639245 Write leveling : NO K
7045 23:42:33.642498 RX DQS gating : PASS
7046 23:42:33.645937 RX DQ/DQS(RDDQC) : PASS
7047 23:42:33.646008 TX DQ/DQS : PASS
7048 23:42:33.649366 RX DATLAT : PASS
7049 23:42:33.652464 RX DQ/DQS(Engine): PASS
7050 23:42:33.652560 TX OE : NO K
7051 23:42:33.652659 All Pass.
7052 23:42:33.656110
7053 23:42:33.656210 CH 1, Rank 0
7054 23:42:33.659294 SW Impedance : PASS
7055 23:42:33.659370 DUTY Scan : NO K
7056 23:42:33.662624 ZQ Calibration : PASS
7057 23:42:33.662694 Jitter Meter : NO K
7058 23:42:33.666021 CBT Training : PASS
7059 23:42:33.669043 Write leveling : PASS
7060 23:42:33.669147 RX DQS gating : PASS
7061 23:42:33.672786 RX DQ/DQS(RDDQC) : PASS
7062 23:42:33.676091 TX DQ/DQS : PASS
7063 23:42:33.676189 RX DATLAT : PASS
7064 23:42:33.679030 RX DQ/DQS(Engine): PASS
7065 23:42:33.682596 TX OE : NO K
7066 23:42:33.682665 All Pass.
7067 23:42:33.682725
7068 23:42:33.682801 CH 1, Rank 1
7069 23:42:33.685522 SW Impedance : PASS
7070 23:42:33.688950 DUTY Scan : NO K
7071 23:42:33.689045 ZQ Calibration : PASS
7072 23:42:33.692265 Jitter Meter : NO K
7073 23:42:33.695555 CBT Training : PASS
7074 23:42:33.695655 Write leveling : NO K
7075 23:42:33.699163 RX DQS gating : PASS
7076 23:42:33.702548 RX DQ/DQS(RDDQC) : PASS
7077 23:42:33.702639 TX DQ/DQS : PASS
7078 23:42:33.705530 RX DATLAT : PASS
7079 23:42:33.709137 RX DQ/DQS(Engine): PASS
7080 23:42:33.709248 TX OE : NO K
7081 23:42:33.712355 All Pass.
7082 23:42:33.712460
7083 23:42:33.712567 DramC Write-DBI off
7084 23:42:33.715358 PER_BANK_REFRESH: Hybrid Mode
7085 23:42:33.715460 TX_TRACKING: ON
7086 23:42:33.725405 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7087 23:42:33.728844 [FAST_K] Save calibration result to emmc
7088 23:42:33.731716 dramc_set_vcore_voltage set vcore to 725000
7089 23:42:33.735142 Read voltage for 1600, 0
7090 23:42:33.735244 Vio18 = 0
7091 23:42:33.738794 Vcore = 725000
7092 23:42:33.738899 Vdram = 0
7093 23:42:33.739001 Vddq = 0
7094 23:42:33.742076 Vmddr = 0
7095 23:42:33.745330 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7096 23:42:33.751491 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7097 23:42:33.751597 MEM_TYPE=3, freq_sel=13
7098 23:42:33.755053 sv_algorithm_assistance_LP4_3733
7099 23:42:33.761549 ============ PULL DRAM RESETB DOWN ============
7100 23:42:33.764736 ========== PULL DRAM RESETB DOWN end =========
7101 23:42:33.768307 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7102 23:42:33.771347 ===================================
7103 23:42:33.774518 LPDDR4 DRAM CONFIGURATION
7104 23:42:33.777895 ===================================
7105 23:42:33.781207 EX_ROW_EN[0] = 0x0
7106 23:42:33.781319 EX_ROW_EN[1] = 0x0
7107 23:42:33.785131 LP4Y_EN = 0x0
7108 23:42:33.785237 WORK_FSP = 0x1
7109 23:42:33.788093 WL = 0x5
7110 23:42:33.788195 RL = 0x5
7111 23:42:33.791063 BL = 0x2
7112 23:42:33.791150 RPST = 0x0
7113 23:42:33.794772 RD_PRE = 0x0
7114 23:42:33.794873 WR_PRE = 0x1
7115 23:42:33.797505 WR_PST = 0x1
7116 23:42:33.797605 DBI_WR = 0x0
7117 23:42:33.801238 DBI_RD = 0x0
7118 23:42:33.801341 OTF = 0x1
7119 23:42:33.804401 ===================================
7120 23:42:33.807939 ===================================
7121 23:42:33.811181 ANA top config
7122 23:42:33.814317 ===================================
7123 23:42:33.817792 DLL_ASYNC_EN = 0
7124 23:42:33.817873 ALL_SLAVE_EN = 0
7125 23:42:33.820716 NEW_RANK_MODE = 1
7126 23:42:33.824536 DLL_IDLE_MODE = 1
7127 23:42:33.827680 LP45_APHY_COMB_EN = 1
7128 23:42:33.827779 TX_ODT_DIS = 0
7129 23:42:33.830684 NEW_8X_MODE = 1
7130 23:42:33.833979 ===================================
7131 23:42:33.837397 ===================================
7132 23:42:33.840811 data_rate = 3200
7133 23:42:33.844442 CKR = 1
7134 23:42:33.847364 DQ_P2S_RATIO = 8
7135 23:42:33.850644 ===================================
7136 23:42:33.853790 CA_P2S_RATIO = 8
7137 23:42:33.853892 DQ_CA_OPEN = 0
7138 23:42:33.857175 DQ_SEMI_OPEN = 0
7139 23:42:33.860837 CA_SEMI_OPEN = 0
7140 23:42:33.863896 CA_FULL_RATE = 0
7141 23:42:33.867187 DQ_CKDIV4_EN = 0
7142 23:42:33.870597 CA_CKDIV4_EN = 0
7143 23:42:33.873727 CA_PREDIV_EN = 0
7144 23:42:33.873831 PH8_DLY = 12
7145 23:42:33.876888 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7146 23:42:33.880351 DQ_AAMCK_DIV = 4
7147 23:42:33.883624 CA_AAMCK_DIV = 4
7148 23:42:33.886731 CA_ADMCK_DIV = 4
7149 23:42:33.890560 DQ_TRACK_CA_EN = 0
7150 23:42:33.890672 CA_PICK = 1600
7151 23:42:33.893554 CA_MCKIO = 1600
7152 23:42:33.896563 MCKIO_SEMI = 0
7153 23:42:33.900028 PLL_FREQ = 3068
7154 23:42:33.903146 DQ_UI_PI_RATIO = 32
7155 23:42:33.906721 CA_UI_PI_RATIO = 0
7156 23:42:33.910240 ===================================
7157 23:42:33.913119 ===================================
7158 23:42:33.917752 memory_type:LPDDR4
7159 23:42:33.917834 GP_NUM : 10
7160 23:42:33.919902 SRAM_EN : 1
7161 23:42:33.919984 MD32_EN : 0
7162 23:42:33.923298 ===================================
7163 23:42:33.926779 [ANA_INIT] >>>>>>>>>>>>>>
7164 23:42:33.930143 <<<<<< [CONFIGURE PHASE]: ANA_TX
7165 23:42:33.932968 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7166 23:42:33.936274 ===================================
7167 23:42:33.939778 data_rate = 3200,PCW = 0X7600
7168 23:42:33.943284 ===================================
7169 23:42:33.946477 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7170 23:42:33.952804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7171 23:42:33.956086 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7172 23:42:33.962995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7173 23:42:33.966066 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7174 23:42:33.969108 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7175 23:42:33.969209 [ANA_INIT] flow start
7176 23:42:33.972452 [ANA_INIT] PLL >>>>>>>>
7177 23:42:33.975867 [ANA_INIT] PLL <<<<<<<<
7178 23:42:33.975939 [ANA_INIT] MIDPI >>>>>>>>
7179 23:42:33.979424 [ANA_INIT] MIDPI <<<<<<<<
7180 23:42:33.982467 [ANA_INIT] DLL >>>>>>>>
7181 23:42:33.985780 [ANA_INIT] DLL <<<<<<<<
7182 23:42:33.985870 [ANA_INIT] flow end
7183 23:42:33.989064 ============ LP4 DIFF to SE enter ============
7184 23:42:33.995858 ============ LP4 DIFF to SE exit ============
7185 23:42:33.995935 [ANA_INIT] <<<<<<<<<<<<<
7186 23:42:33.999144 [Flow] Enable top DCM control >>>>>
7187 23:42:34.002164 [Flow] Enable top DCM control <<<<<
7188 23:42:34.005630 Enable DLL master slave shuffle
7189 23:42:34.012057 ==============================================================
7190 23:42:34.012160 Gating Mode config
7191 23:42:34.018622 ==============================================================
7192 23:42:34.021621 Config description:
7193 23:42:34.031861 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7194 23:42:34.038158 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7195 23:42:34.041718 SELPH_MODE 0: By rank 1: By Phase
7196 23:42:34.048311 ==============================================================
7197 23:42:34.051222 GAT_TRACK_EN = 1
7198 23:42:34.054722 RX_GATING_MODE = 2
7199 23:42:34.057702 RX_GATING_TRACK_MODE = 2
7200 23:42:34.061180 SELPH_MODE = 1
7201 23:42:34.061271 PICG_EARLY_EN = 1
7202 23:42:34.064686 VALID_LAT_VALUE = 1
7203 23:42:34.071102 ==============================================================
7204 23:42:34.074507 Enter into Gating configuration >>>>
7205 23:42:34.077573 Exit from Gating configuration <<<<
7206 23:42:34.080801 Enter into DVFS_PRE_config >>>>>
7207 23:42:34.090861 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7208 23:42:34.093866 Exit from DVFS_PRE_config <<<<<
7209 23:42:34.097522 Enter into PICG configuration >>>>
7210 23:42:34.100453 Exit from PICG configuration <<<<
7211 23:42:34.103790 [RX_INPUT] configuration >>>>>
7212 23:42:34.107155 [RX_INPUT] configuration <<<<<
7213 23:42:34.113973 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7214 23:42:34.117035 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7215 23:42:34.123490 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7216 23:42:34.130344 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7217 23:42:34.136779 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7218 23:42:34.143566 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7219 23:42:34.146994 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7220 23:42:34.150377 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7221 23:42:34.153065 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7222 23:42:34.159666 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7223 23:42:34.163009 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7224 23:42:34.166440 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7225 23:42:34.169885 ===================================
7226 23:42:34.172708 LPDDR4 DRAM CONFIGURATION
7227 23:42:34.176508 ===================================
7228 23:42:34.179723 EX_ROW_EN[0] = 0x0
7229 23:42:34.179820 EX_ROW_EN[1] = 0x0
7230 23:42:34.182555 LP4Y_EN = 0x0
7231 23:42:34.182624 WORK_FSP = 0x1
7232 23:42:34.186229 WL = 0x5
7233 23:42:34.186326 RL = 0x5
7234 23:42:34.189059 BL = 0x2
7235 23:42:34.189155 RPST = 0x0
7236 23:42:34.192703 RD_PRE = 0x0
7237 23:42:34.192834 WR_PRE = 0x1
7238 23:42:34.195774 WR_PST = 0x1
7239 23:42:34.195880 DBI_WR = 0x0
7240 23:42:34.199040 DBI_RD = 0x0
7241 23:42:34.199141 OTF = 0x1
7242 23:42:34.202600 ===================================
7243 23:42:34.209115 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7244 23:42:34.212511 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7245 23:42:34.215868 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7246 23:42:34.218902 ===================================
7247 23:42:34.222482 LPDDR4 DRAM CONFIGURATION
7248 23:42:34.226067 ===================================
7249 23:42:34.228670 EX_ROW_EN[0] = 0x10
7250 23:42:34.228765 EX_ROW_EN[1] = 0x0
7251 23:42:34.231933 LP4Y_EN = 0x0
7252 23:42:34.232033 WORK_FSP = 0x1
7253 23:42:34.235537 WL = 0x5
7254 23:42:34.235607 RL = 0x5
7255 23:42:34.238549 BL = 0x2
7256 23:42:34.238638 RPST = 0x0
7257 23:42:34.241975 RD_PRE = 0x0
7258 23:42:34.242075 WR_PRE = 0x1
7259 23:42:34.245761 WR_PST = 0x1
7260 23:42:34.245837 DBI_WR = 0x0
7261 23:42:34.248655 DBI_RD = 0x0
7262 23:42:34.251573 OTF = 0x1
7263 23:42:34.255364 ===================================
7264 23:42:34.258591 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7265 23:42:34.258688 ==
7266 23:42:34.261843 Dram Type= 6, Freq= 0, CH_0, rank 0
7267 23:42:34.268442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7268 23:42:34.268544 ==
7269 23:42:34.271374 [Duty_Offset_Calibration]
7270 23:42:34.271507 B0:2 B1:0 CA:4
7271 23:42:34.271599
7272 23:42:34.274727 [DutyScan_Calibration_Flow] k_type=0
7273 23:42:34.283955
7274 23:42:34.284056 ==CLK 0==
7275 23:42:34.287139 Final CLK duty delay cell = -4
7276 23:42:34.290351 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7277 23:42:34.293802 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7278 23:42:34.296700 [-4] AVG Duty = 4922%(X100)
7279 23:42:34.296808
7280 23:42:34.300130 CH0 CLK Duty spec in!! Max-Min= 156%
7281 23:42:34.303405 [DutyScan_Calibration_Flow] ====Done====
7282 23:42:34.303508
7283 23:42:34.306713 [DutyScan_Calibration_Flow] k_type=1
7284 23:42:34.323937
7285 23:42:34.324061 ==DQS 0 ==
7286 23:42:34.327559 Final DQS duty delay cell = 0
7287 23:42:34.330580 [0] MAX Duty = 5218%(X100), DQS PI = 38
7288 23:42:34.334299 [0] MIN Duty = 5093%(X100), DQS PI = 14
7289 23:42:34.337595 [0] AVG Duty = 5155%(X100)
7290 23:42:34.337669
7291 23:42:34.337748 ==DQS 1 ==
7292 23:42:34.340547 Final DQS duty delay cell = 0
7293 23:42:34.344080 [0] MAX Duty = 5156%(X100), DQS PI = 2
7294 23:42:34.347052 [0] MIN Duty = 4969%(X100), DQS PI = 10
7295 23:42:34.350541 [0] AVG Duty = 5062%(X100)
7296 23:42:34.350622
7297 23:42:34.354149 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7298 23:42:34.354249
7299 23:42:34.356792 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7300 23:42:34.360146 [DutyScan_Calibration_Flow] ====Done====
7301 23:42:34.360232
7302 23:42:34.363662 [DutyScan_Calibration_Flow] k_type=3
7303 23:42:34.381589
7304 23:42:34.381674 ==DQM 0 ==
7305 23:42:34.384703 Final DQM duty delay cell = 0
7306 23:42:34.387779 [0] MAX Duty = 5124%(X100), DQS PI = 22
7307 23:42:34.391105 [0] MIN Duty = 4844%(X100), DQS PI = 54
7308 23:42:34.394506 [0] AVG Duty = 4984%(X100)
7309 23:42:34.394607
7310 23:42:34.394700 ==DQM 1 ==
7311 23:42:34.397948 Final DQM duty delay cell = 0
7312 23:42:34.400920 [0] MAX Duty = 5000%(X100), DQS PI = 2
7313 23:42:34.404244 [0] MIN Duty = 4813%(X100), DQS PI = 16
7314 23:42:34.407608 [0] AVG Duty = 4906%(X100)
7315 23:42:34.407705
7316 23:42:34.410880 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7317 23:42:34.410975
7318 23:42:34.414087 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7319 23:42:34.418043 [DutyScan_Calibration_Flow] ====Done====
7320 23:42:34.418146
7321 23:42:34.420741 [DutyScan_Calibration_Flow] k_type=2
7322 23:42:34.438656
7323 23:42:34.438760 ==DQ 0 ==
7324 23:42:34.441554 Final DQ duty delay cell = 0
7325 23:42:34.445273 [0] MAX Duty = 5156%(X100), DQS PI = 22
7326 23:42:34.448248 [0] MIN Duty = 4938%(X100), DQS PI = 12
7327 23:42:34.451808 [0] AVG Duty = 5047%(X100)
7328 23:42:34.451913
7329 23:42:34.452004 ==DQ 1 ==
7330 23:42:34.454604 Final DQ duty delay cell = 0
7331 23:42:34.458210 [0] MAX Duty = 5187%(X100), DQS PI = 2
7332 23:42:34.461452 [0] MIN Duty = 4938%(X100), DQS PI = 12
7333 23:42:34.461525 [0] AVG Duty = 5062%(X100)
7334 23:42:34.464504
7335 23:42:34.467948 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7336 23:42:34.468017
7337 23:42:34.471117 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7338 23:42:34.474635 [DutyScan_Calibration_Flow] ====Done====
7339 23:42:34.474734 ==
7340 23:42:34.478055 Dram Type= 6, Freq= 0, CH_1, rank 0
7341 23:42:34.481279 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7342 23:42:34.481351 ==
7343 23:42:34.484390 [Duty_Offset_Calibration]
7344 23:42:34.484458 B0:0 B1:-1 CA:3
7345 23:42:34.484517
7346 23:42:34.487781 [DutyScan_Calibration_Flow] k_type=0
7347 23:42:34.498770
7348 23:42:34.498877 ==CLK 0==
7349 23:42:34.501797 Final CLK duty delay cell = 0
7350 23:42:34.505178 [0] MAX Duty = 5187%(X100), DQS PI = 4
7351 23:42:34.508648 [0] MIN Duty = 5000%(X100), DQS PI = 54
7352 23:42:34.508721 [0] AVG Duty = 5093%(X100)
7353 23:42:34.512045
7354 23:42:34.515041 CH1 CLK Duty spec in!! Max-Min= 187%
7355 23:42:34.518519 [DutyScan_Calibration_Flow] ====Done====
7356 23:42:34.518590
7357 23:42:34.521678 [DutyScan_Calibration_Flow] k_type=1
7358 23:42:34.537382
7359 23:42:34.537470 ==DQS 0 ==
7360 23:42:34.540896 Final DQS duty delay cell = 0
7361 23:42:34.543793 [0] MAX Duty = 5250%(X100), DQS PI = 30
7362 23:42:34.547314 [0] MIN Duty = 4907%(X100), DQS PI = 42
7363 23:42:34.550189 [0] AVG Duty = 5078%(X100)
7364 23:42:34.550280
7365 23:42:34.550343 ==DQS 1 ==
7366 23:42:34.553976 Final DQS duty delay cell = -4
7367 23:42:34.557449 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7368 23:42:34.560470 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7369 23:42:34.563436 [-4] AVG Duty = 4906%(X100)
7370 23:42:34.563513
7371 23:42:34.567002 CH1 DQS 0 Duty spec in!! Max-Min= 343%
7372 23:42:34.567101
7373 23:42:34.570381 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7374 23:42:34.573619 [DutyScan_Calibration_Flow] ====Done====
7375 23:42:34.573722
7376 23:42:34.576506 [DutyScan_Calibration_Flow] k_type=3
7377 23:42:34.594676
7378 23:42:34.594789 ==DQM 0 ==
7379 23:42:34.598234 Final DQM duty delay cell = 0
7380 23:42:34.600942 [0] MAX Duty = 5062%(X100), DQS PI = 30
7381 23:42:34.604722 [0] MIN Duty = 4782%(X100), DQS PI = 38
7382 23:42:34.608023 [0] AVG Duty = 4922%(X100)
7383 23:42:34.608136
7384 23:42:34.608226 ==DQM 1 ==
7385 23:42:34.610919 Final DQM duty delay cell = 0
7386 23:42:34.614149 [0] MAX Duty = 5000%(X100), DQS PI = 34
7387 23:42:34.617695 [0] MIN Duty = 4844%(X100), DQS PI = 0
7388 23:42:34.620850 [0] AVG Duty = 4922%(X100)
7389 23:42:34.620945
7390 23:42:34.624216 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7391 23:42:34.624311
7392 23:42:34.627597 CH1 DQM 1 Duty spec in!! Max-Min= 156%
7393 23:42:34.631027 [DutyScan_Calibration_Flow] ====Done====
7394 23:42:34.631124
7395 23:42:34.633949 [DutyScan_Calibration_Flow] k_type=2
7396 23:42:34.650955
7397 23:42:34.651058 ==DQ 0 ==
7398 23:42:34.654266 Final DQ duty delay cell = -4
7399 23:42:34.657106 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7400 23:42:34.660376 [-4] MIN Duty = 4813%(X100), DQS PI = 22
7401 23:42:34.664225 [-4] AVG Duty = 4891%(X100)
7402 23:42:34.664321
7403 23:42:34.664383 ==DQ 1 ==
7404 23:42:34.667528 Final DQ duty delay cell = 0
7405 23:42:34.670208 [0] MAX Duty = 5031%(X100), DQS PI = 30
7406 23:42:34.673912 [0] MIN Duty = 4875%(X100), DQS PI = 58
7407 23:42:34.676923 [0] AVG Duty = 4953%(X100)
7408 23:42:34.677020
7409 23:42:34.680432 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7410 23:42:34.680529
7411 23:42:34.683613 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7412 23:42:34.687103 [DutyScan_Calibration_Flow] ====Done====
7413 23:42:34.690627 nWR fixed to 30
7414 23:42:34.693415 [ModeRegInit_LP4] CH0 RK0
7415 23:42:34.693485 [ModeRegInit_LP4] CH0 RK1
7416 23:42:34.697009 [ModeRegInit_LP4] CH1 RK0
7417 23:42:34.700080 [ModeRegInit_LP4] CH1 RK1
7418 23:42:34.700179 match AC timing 5
7419 23:42:34.706974 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7420 23:42:34.710412 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7421 23:42:34.713729 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7422 23:42:34.720106 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7423 23:42:34.723260 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7424 23:42:34.723360 [MiockJmeterHQA]
7425 23:42:34.726363
7426 23:42:34.726432 [DramcMiockJmeter] u1RxGatingPI = 0
7427 23:42:34.729912 0 : 4364, 4137
7428 23:42:34.730011 4 : 4253, 4026
7429 23:42:34.733220 8 : 4363, 4137
7430 23:42:34.733347 12 : 4253, 4026
7431 23:42:34.736566 16 : 4252, 4027
7432 23:42:34.736664 20 : 4253, 4026
7433 23:42:34.739535 24 : 4253, 4027
7434 23:42:34.739612 28 : 4252, 4027
7435 23:42:34.739673 32 : 4253, 4027
7436 23:42:34.743507 36 : 4366, 4140
7437 23:42:34.743578 40 : 4365, 4140
7438 23:42:34.746193 44 : 4255, 4030
7439 23:42:34.746270 48 : 4254, 4029
7440 23:42:34.749864 52 : 4366, 4140
7441 23:42:34.749937 56 : 4252, 4027
7442 23:42:34.752818 60 : 4365, 4140
7443 23:42:34.752912 64 : 4250, 4027
7444 23:42:34.753004 68 : 4250, 4027
7445 23:42:34.756350 72 : 4252, 4027
7446 23:42:34.756448 76 : 4253, 4029
7447 23:42:34.759349 80 : 4361, 4137
7448 23:42:34.759420 84 : 4363, 4138
7449 23:42:34.763011 88 : 4247, 4024
7450 23:42:34.763106 92 : 4250, 4026
7451 23:42:34.766508 96 : 4250, 2327
7452 23:42:34.766579 100 : 4252, 0
7453 23:42:34.766639 104 : 4252, 0
7454 23:42:34.769690 108 : 4255, 0
7455 23:42:34.769791 112 : 4250, 0
7456 23:42:34.772755 116 : 4252, 0
7457 23:42:34.772856 120 : 4360, 0
7458 23:42:34.772975 124 : 4361, 0
7459 23:42:34.775887 128 : 4247, 0
7460 23:42:34.775987 132 : 4250, 0
7461 23:42:34.776079 136 : 4250, 0
7462 23:42:34.779453 140 : 4363, 0
7463 23:42:34.779520 144 : 4255, 0
7464 23:42:34.782403 148 : 4250, 0
7465 23:42:34.782469 152 : 4361, 0
7466 23:42:34.782526 156 : 4250, 0
7467 23:42:34.785842 160 : 4250, 0
7468 23:42:34.785927 164 : 4250, 0
7469 23:42:34.789149 168 : 4252, 0
7470 23:42:34.789234 172 : 4360, 0
7471 23:42:34.789348 176 : 4250, 0
7472 23:42:34.792426 180 : 4250, 0
7473 23:42:34.792522 184 : 4252, 0
7474 23:42:34.796067 188 : 4250, 0
7475 23:42:34.796170 192 : 4363, 0
7476 23:42:34.796264 196 : 4250, 0
7477 23:42:34.799476 200 : 4361, 0
7478 23:42:34.799576 204 : 4250, 0
7479 23:42:34.799671 208 : 4250, 0
7480 23:42:34.802318 212 : 4253, 0
7481 23:42:34.802416 216 : 4250, 0
7482 23:42:34.806090 220 : 4250, 807
7483 23:42:34.806190 224 : 4360, 4134
7484 23:42:34.809237 228 : 4250, 4027
7485 23:42:34.809355 232 : 4250, 4027
7486 23:42:34.812209 236 : 4249, 4027
7487 23:42:34.812303 240 : 4250, 4027
7488 23:42:34.815580 244 : 4250, 4026
7489 23:42:34.815677 248 : 4252, 4030
7490 23:42:34.815769 252 : 4252, 4030
7491 23:42:34.819374 256 : 4252, 4029
7492 23:42:34.819476 260 : 4361, 4137
7493 23:42:34.822757 264 : 4255, 4029
7494 23:42:34.822856 268 : 4250, 4027
7495 23:42:34.825692 272 : 4254, 4029
7496 23:42:34.825790 276 : 4361, 4137
7497 23:42:34.829377 280 : 4363, 4137
7498 23:42:34.829473 284 : 4250, 4027
7499 23:42:34.832375 288 : 4363, 4140
7500 23:42:34.832470 292 : 4250, 4026
7501 23:42:34.835675 296 : 4250, 4026
7502 23:42:34.835772 300 : 4252, 4029
7503 23:42:34.838696 304 : 4253, 4030
7504 23:42:34.838767 308 : 4252, 4029
7505 23:42:34.838826 312 : 4361, 4137
7506 23:42:34.841971 316 : 4255, 4029
7507 23:42:34.842042 320 : 4250, 4027
7508 23:42:34.845747 324 : 4255, 4029
7509 23:42:34.845824 328 : 4363, 4140
7510 23:42:34.849174 332 : 4363, 3896
7511 23:42:34.849292 336 : 4250, 1184
7512 23:42:34.849409
7513 23:42:34.852404 MIOCK jitter meter ch=0
7514 23:42:34.852475
7515 23:42:34.855369 1T = (336-100) = 236 dly cells
7516 23:42:34.862182 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7517 23:42:34.862283 ==
7518 23:42:34.865020 Dram Type= 6, Freq= 0, CH_0, rank 0
7519 23:42:34.868606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7520 23:42:34.868700 ==
7521 23:42:34.874934 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7522 23:42:34.878526 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7523 23:42:34.882249 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7524 23:42:34.888269 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7525 23:42:34.897213 [CA 0] Center 44 (14~74) winsize 61
7526 23:42:34.900692 [CA 1] Center 43 (13~74) winsize 62
7527 23:42:34.904145 [CA 2] Center 38 (9~68) winsize 60
7528 23:42:34.907395 [CA 3] Center 38 (9~68) winsize 60
7529 23:42:34.910460 [CA 4] Center 37 (7~67) winsize 61
7530 23:42:34.914043 [CA 5] Center 36 (6~66) winsize 61
7531 23:42:34.914140
7532 23:42:34.916784 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7533 23:42:34.916880
7534 23:42:34.923851 [CATrainingPosCal] consider 1 rank data
7535 23:42:34.923951 u2DelayCellTimex100 = 275/100 ps
7536 23:42:34.930408 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7537 23:42:34.933800 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7538 23:42:34.936653 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7539 23:42:34.940467 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7540 23:42:34.943269 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7541 23:42:34.946488 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7542 23:42:34.946583
7543 23:42:34.950111 CA PerBit enable=1, Macro0, CA PI delay=36
7544 23:42:34.950194
7545 23:42:34.953068 [CBTSetCACLKResult] CA Dly = 36
7546 23:42:34.956389 CS Dly: 10 (0~41)
7547 23:42:34.959939 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7548 23:42:34.963092 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7549 23:42:34.963191 ==
7550 23:42:34.966073 Dram Type= 6, Freq= 0, CH_0, rank 1
7551 23:42:34.972785 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7552 23:42:34.972888 ==
7553 23:42:34.976360 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7554 23:42:34.982598 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7555 23:42:34.985831 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7556 23:42:34.992455 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7557 23:42:35.000777 [CA 0] Center 44 (14~74) winsize 61
7558 23:42:35.003856 [CA 1] Center 44 (14~74) winsize 61
7559 23:42:35.007428 [CA 2] Center 39 (10~69) winsize 60
7560 23:42:35.010409 [CA 3] Center 39 (10~68) winsize 59
7561 23:42:35.014387 [CA 4] Center 37 (7~67) winsize 61
7562 23:42:35.017202 [CA 5] Center 36 (6~66) winsize 61
7563 23:42:35.017300
7564 23:42:35.020698 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7565 23:42:35.020801
7566 23:42:35.026927 [CATrainingPosCal] consider 2 rank data
7567 23:42:35.027028 u2DelayCellTimex100 = 275/100 ps
7568 23:42:35.033407 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7569 23:42:35.036815 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7570 23:42:35.039982 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7571 23:42:35.043647 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7572 23:42:35.047150 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7573 23:42:35.050057 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7574 23:42:35.050154
7575 23:42:35.053286 CA PerBit enable=1, Macro0, CA PI delay=36
7576 23:42:35.053381
7577 23:42:35.056568 [CBTSetCACLKResult] CA Dly = 36
7578 23:42:35.059764 CS Dly: 11 (0~43)
7579 23:42:35.063199 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7580 23:42:35.066895 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7581 23:42:35.066975
7582 23:42:35.069977 ----->DramcWriteLeveling(PI) begin...
7583 23:42:35.073653 ==
7584 23:42:35.076526 Dram Type= 6, Freq= 0, CH_0, rank 0
7585 23:42:35.079835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7586 23:42:35.079932 ==
7587 23:42:35.083427 Write leveling (Byte 0): 33 => 33
7588 23:42:35.086383 Write leveling (Byte 1): 27 => 27
7589 23:42:35.089641 DramcWriteLeveling(PI) end<-----
7590 23:42:35.089742
7591 23:42:35.089832 ==
7592 23:42:35.093221 Dram Type= 6, Freq= 0, CH_0, rank 0
7593 23:42:35.096303 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7594 23:42:35.096387 ==
7595 23:42:35.099771 [Gating] SW mode calibration
7596 23:42:35.106552 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7597 23:42:35.112812 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7598 23:42:35.116411 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 23:42:35.119059 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 23:42:35.125881 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
7601 23:42:35.129342 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7602 23:42:35.132240 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7603 23:42:35.138959 1 4 20 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
7604 23:42:35.142279 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7605 23:42:35.145846 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7606 23:42:35.152276 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7607 23:42:35.155682 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7608 23:42:35.159081 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7609 23:42:35.166002 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
7610 23:42:35.168952 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7611 23:42:35.172273 1 5 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7612 23:42:35.178604 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7613 23:42:35.182085 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 23:42:35.185529 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7615 23:42:35.191590 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7616 23:42:35.195055 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7617 23:42:35.198390 1 6 12 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7618 23:42:35.205063 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7619 23:42:35.208048 1 6 20 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
7620 23:42:35.211632 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7621 23:42:35.218294 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7622 23:42:35.221557 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 23:42:35.224952 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 23:42:35.231121 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7625 23:42:35.234368 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7626 23:42:35.237899 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7627 23:42:35.244206 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7628 23:42:35.247838 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7629 23:42:35.251164 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7630 23:42:35.257970 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 23:42:35.260761 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 23:42:35.264243 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 23:42:35.270612 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 23:42:35.274300 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 23:42:35.277144 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 23:42:35.283915 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 23:42:35.286766 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 23:42:35.290414 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 23:42:35.296956 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 23:42:35.300041 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7641 23:42:35.303687 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7642 23:42:35.309748 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7643 23:42:35.313265 Total UI for P1: 0, mck2ui 16
7644 23:42:35.316786 best dqsien dly found for B0: ( 1, 9, 10)
7645 23:42:35.319935 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7646 23:42:35.323328 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7647 23:42:35.329588 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 23:42:35.333148 Total UI for P1: 0, mck2ui 16
7649 23:42:35.336748 best dqsien dly found for B1: ( 1, 9, 24)
7650 23:42:35.339506 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7651 23:42:35.343331 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7652 23:42:35.343412
7653 23:42:35.346669 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7654 23:42:35.349624 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7655 23:42:35.353050 [Gating] SW calibration Done
7656 23:42:35.353131 ==
7657 23:42:35.356453 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 23:42:35.359381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 23:42:35.359462 ==
7660 23:42:35.362971 RX Vref Scan: 0
7661 23:42:35.363052
7662 23:42:35.366225 RX Vref 0 -> 0, step: 1
7663 23:42:35.366307
7664 23:42:35.366370 RX Delay 0 -> 252, step: 8
7665 23:42:35.372491 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7666 23:42:35.375756 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7667 23:42:35.379396 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7668 23:42:35.382437 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7669 23:42:35.385815 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7670 23:42:35.392319 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7671 23:42:35.395627 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7672 23:42:35.398981 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7673 23:42:35.402266 iDelay=192, Bit 8, Center 115 (64 ~ 167) 104
7674 23:42:35.405811 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7675 23:42:35.412175 iDelay=192, Bit 10, Center 123 (72 ~ 175) 104
7676 23:42:35.415733 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7677 23:42:35.418558 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7678 23:42:35.421811 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7679 23:42:35.428524 iDelay=192, Bit 14, Center 139 (88 ~ 191) 104
7680 23:42:35.432255 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7681 23:42:35.432338 ==
7682 23:42:35.435072 Dram Type= 6, Freq= 0, CH_0, rank 0
7683 23:42:35.438469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7684 23:42:35.438566 ==
7685 23:42:35.441485 DQS Delay:
7686 23:42:35.441608 DQS0 = 0, DQS1 = 0
7687 23:42:35.441699 DQM Delay:
7688 23:42:35.444868 DQM0 = 131, DQM1 = 127
7689 23:42:35.444948 DQ Delay:
7690 23:42:35.448092 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7691 23:42:35.451812 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7692 23:42:35.458097 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =123
7693 23:42:35.461367 DQ12 =135, DQ13 =131, DQ14 =139, DQ15 =135
7694 23:42:35.461449
7695 23:42:35.461512
7696 23:42:35.461571 ==
7697 23:42:35.464978 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 23:42:35.467934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 23:42:35.468042 ==
7700 23:42:35.468133
7701 23:42:35.468227
7702 23:42:35.471289 TX Vref Scan disable
7703 23:42:35.474556 == TX Byte 0 ==
7704 23:42:35.478110 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7705 23:42:35.481057 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7706 23:42:35.484554 == TX Byte 1 ==
7707 23:42:35.487578 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7708 23:42:35.491180 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7709 23:42:35.491262 ==
7710 23:42:35.494063 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 23:42:35.500739 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 23:42:35.500825 ==
7713 23:42:35.512781
7714 23:42:35.515868 TX Vref early break, caculate TX vref
7715 23:42:35.519555 TX Vref=16, minBit 4, minWin=22, winSum=375
7716 23:42:35.522523 TX Vref=18, minBit 8, minWin=22, winSum=380
7717 23:42:35.525676 TX Vref=20, minBit 1, minWin=23, winSum=391
7718 23:42:35.529386 TX Vref=22, minBit 7, minWin=24, winSum=402
7719 23:42:35.532340 TX Vref=24, minBit 0, minWin=25, winSum=411
7720 23:42:35.538808 TX Vref=26, minBit 1, minWin=25, winSum=421
7721 23:42:35.542632 TX Vref=28, minBit 4, minWin=25, winSum=425
7722 23:42:35.545605 TX Vref=30, minBit 2, minWin=25, winSum=422
7723 23:42:35.549154 TX Vref=32, minBit 2, minWin=24, winSum=407
7724 23:42:35.552359 TX Vref=34, minBit 0, minWin=24, winSum=401
7725 23:42:35.559075 [TxChooseVref] Worse bit 4, Min win 25, Win sum 425, Final Vref 28
7726 23:42:35.559173
7727 23:42:35.562655 Final TX Range 0 Vref 28
7728 23:42:35.562736
7729 23:42:35.562799 ==
7730 23:42:35.565175 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 23:42:35.568931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 23:42:35.569012 ==
7733 23:42:35.569076
7734 23:42:35.569133
7735 23:42:35.572219 TX Vref Scan disable
7736 23:42:35.578647 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7737 23:42:35.578746 == TX Byte 0 ==
7738 23:42:35.581794 u2DelayCellOfst[0]=14 cells (4 PI)
7739 23:42:35.584913 u2DelayCellOfst[1]=17 cells (5 PI)
7740 23:42:35.588355 u2DelayCellOfst[2]=14 cells (4 PI)
7741 23:42:35.591964 u2DelayCellOfst[3]=10 cells (3 PI)
7742 23:42:35.594872 u2DelayCellOfst[4]=10 cells (3 PI)
7743 23:42:35.598364 u2DelayCellOfst[5]=0 cells (0 PI)
7744 23:42:35.601235 u2DelayCellOfst[6]=17 cells (5 PI)
7745 23:42:35.604624 u2DelayCellOfst[7]=17 cells (5 PI)
7746 23:42:35.608004 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7747 23:42:35.611736 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7748 23:42:35.614621 == TX Byte 1 ==
7749 23:42:35.618117 u2DelayCellOfst[8]=0 cells (0 PI)
7750 23:42:35.621361 u2DelayCellOfst[9]=0 cells (0 PI)
7751 23:42:35.624684 u2DelayCellOfst[10]=3 cells (1 PI)
7752 23:42:35.627834 u2DelayCellOfst[11]=3 cells (1 PI)
7753 23:42:35.627917 u2DelayCellOfst[12]=10 cells (3 PI)
7754 23:42:35.631457 u2DelayCellOfst[13]=10 cells (3 PI)
7755 23:42:35.634342 u2DelayCellOfst[14]=14 cells (4 PI)
7756 23:42:35.638008 u2DelayCellOfst[15]=10 cells (3 PI)
7757 23:42:35.644549 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7758 23:42:35.647693 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7759 23:42:35.647776 DramC Write-DBI on
7760 23:42:35.651044 ==
7761 23:42:35.654603 Dram Type= 6, Freq= 0, CH_0, rank 0
7762 23:42:35.657669 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7763 23:42:35.657752 ==
7764 23:42:35.657816
7765 23:42:35.657876
7766 23:42:35.660888 TX Vref Scan disable
7767 23:42:35.660970 == TX Byte 0 ==
7768 23:42:35.668230 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7769 23:42:35.668313 == TX Byte 1 ==
7770 23:42:35.671021 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7771 23:42:35.674002 DramC Write-DBI off
7772 23:42:35.674084
7773 23:42:35.674148 [DATLAT]
7774 23:42:35.677478 Freq=1600, CH0 RK0
7775 23:42:35.677560
7776 23:42:35.677624 DATLAT Default: 0xf
7777 23:42:35.680809 0, 0xFFFF, sum = 0
7778 23:42:35.680893 1, 0xFFFF, sum = 0
7779 23:42:35.684215 2, 0xFFFF, sum = 0
7780 23:42:35.684298 3, 0xFFFF, sum = 0
7781 23:42:35.687488 4, 0xFFFF, sum = 0
7782 23:42:35.690542 5, 0xFFFF, sum = 0
7783 23:42:35.690626 6, 0xFFFF, sum = 0
7784 23:42:35.694055 7, 0xFFFF, sum = 0
7785 23:42:35.694172 8, 0xFFFF, sum = 0
7786 23:42:35.697145 9, 0xFFFF, sum = 0
7787 23:42:35.697247 10, 0xFFFF, sum = 0
7788 23:42:35.700505 11, 0xFFFF, sum = 0
7789 23:42:35.700619 12, 0xFFFF, sum = 0
7790 23:42:35.703911 13, 0xFFFF, sum = 0
7791 23:42:35.704016 14, 0x0, sum = 1
7792 23:42:35.706792 15, 0x0, sum = 2
7793 23:42:35.706888 16, 0x0, sum = 3
7794 23:42:35.710222 17, 0x0, sum = 4
7795 23:42:35.710294 best_step = 15
7796 23:42:35.710368
7797 23:42:35.710425 ==
7798 23:42:35.713963 Dram Type= 6, Freq= 0, CH_0, rank 0
7799 23:42:35.716829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7800 23:42:35.720346 ==
7801 23:42:35.720426 RX Vref Scan: 1
7802 23:42:35.720486
7803 23:42:35.723530 Set Vref Range= 24 -> 127
7804 23:42:35.723623
7805 23:42:35.726842 RX Vref 24 -> 127, step: 1
7806 23:42:35.726989
7807 23:42:35.727077 RX Delay 19 -> 252, step: 4
7808 23:42:35.727170
7809 23:42:35.730193 Set Vref, RX VrefLevel [Byte0]: 24
7810 23:42:35.733682 [Byte1]: 24
7811 23:42:35.737169
7812 23:42:35.737275 Set Vref, RX VrefLevel [Byte0]: 25
7813 23:42:35.741232 [Byte1]: 25
7814 23:42:35.745124
7815 23:42:35.745205 Set Vref, RX VrefLevel [Byte0]: 26
7816 23:42:35.747964 [Byte1]: 26
7817 23:42:35.752861
7818 23:42:35.752943 Set Vref, RX VrefLevel [Byte0]: 27
7819 23:42:35.755681 [Byte1]: 27
7820 23:42:35.760290
7821 23:42:35.760367 Set Vref, RX VrefLevel [Byte0]: 28
7822 23:42:35.763302 [Byte1]: 28
7823 23:42:35.767657
7824 23:42:35.767730 Set Vref, RX VrefLevel [Byte0]: 29
7825 23:42:35.770746 [Byte1]: 29
7826 23:42:35.775709
7827 23:42:35.775792 Set Vref, RX VrefLevel [Byte0]: 30
7828 23:42:35.778517 [Byte1]: 30
7829 23:42:35.782704
7830 23:42:35.782779 Set Vref, RX VrefLevel [Byte0]: 31
7831 23:42:35.786214 [Byte1]: 31
7832 23:42:35.790250
7833 23:42:35.790336 Set Vref, RX VrefLevel [Byte0]: 32
7834 23:42:35.793867 [Byte1]: 32
7835 23:42:35.797745
7836 23:42:35.797820 Set Vref, RX VrefLevel [Byte0]: 33
7837 23:42:35.801400 [Byte1]: 33
7838 23:42:35.805541
7839 23:42:35.805622 Set Vref, RX VrefLevel [Byte0]: 34
7840 23:42:35.808667 [Byte1]: 34
7841 23:42:35.812786
7842 23:42:35.812878 Set Vref, RX VrefLevel [Byte0]: 35
7843 23:42:35.816164 [Byte1]: 35
7844 23:42:35.820708
7845 23:42:35.820780 Set Vref, RX VrefLevel [Byte0]: 36
7846 23:42:35.824227 [Byte1]: 36
7847 23:42:35.828415
7848 23:42:35.828502 Set Vref, RX VrefLevel [Byte0]: 37
7849 23:42:35.831798 [Byte1]: 37
7850 23:42:35.835836
7851 23:42:35.835909 Set Vref, RX VrefLevel [Byte0]: 38
7852 23:42:35.839466 [Byte1]: 38
7853 23:42:35.843156
7854 23:42:35.843232 Set Vref, RX VrefLevel [Byte0]: 39
7855 23:42:35.846414 [Byte1]: 39
7856 23:42:35.850919
7857 23:42:35.850994 Set Vref, RX VrefLevel [Byte0]: 40
7858 23:42:35.854018 [Byte1]: 40
7859 23:42:35.858471
7860 23:42:35.858545 Set Vref, RX VrefLevel [Byte0]: 41
7861 23:42:35.861858 [Byte1]: 41
7862 23:42:35.866225
7863 23:42:35.866302 Set Vref, RX VrefLevel [Byte0]: 42
7864 23:42:35.869554 [Byte1]: 42
7865 23:42:35.874233
7866 23:42:35.874307 Set Vref, RX VrefLevel [Byte0]: 43
7867 23:42:35.876708 [Byte1]: 43
7868 23:42:35.881471
7869 23:42:35.881557 Set Vref, RX VrefLevel [Byte0]: 44
7870 23:42:35.884325 [Byte1]: 44
7871 23:42:35.888725
7872 23:42:35.888801 Set Vref, RX VrefLevel [Byte0]: 45
7873 23:42:35.892140 [Byte1]: 45
7874 23:42:35.896458
7875 23:42:35.896542 Set Vref, RX VrefLevel [Byte0]: 46
7876 23:42:35.899840 [Byte1]: 46
7877 23:42:35.903887
7878 23:42:35.903959 Set Vref, RX VrefLevel [Byte0]: 47
7879 23:42:35.907505 [Byte1]: 47
7880 23:42:35.911225
7881 23:42:35.911309 Set Vref, RX VrefLevel [Byte0]: 48
7882 23:42:35.914548 [Byte1]: 48
7883 23:42:35.919158
7884 23:42:35.919238 Set Vref, RX VrefLevel [Byte0]: 49
7885 23:42:35.922225 [Byte1]: 49
7886 23:42:35.926892
7887 23:42:35.926976 Set Vref, RX VrefLevel [Byte0]: 50
7888 23:42:35.929735 [Byte1]: 50
7889 23:42:35.934258
7890 23:42:35.934334 Set Vref, RX VrefLevel [Byte0]: 51
7891 23:42:35.937594 [Byte1]: 51
7892 23:42:35.941642
7893 23:42:35.941722 Set Vref, RX VrefLevel [Byte0]: 52
7894 23:42:35.944745 [Byte1]: 52
7895 23:42:35.949086
7896 23:42:35.949196 Set Vref, RX VrefLevel [Byte0]: 53
7897 23:42:35.952396 [Byte1]: 53
7898 23:42:35.956936
7899 23:42:35.957012 Set Vref, RX VrefLevel [Byte0]: 54
7900 23:42:35.960045 [Byte1]: 54
7901 23:42:35.964800
7902 23:42:35.964877 Set Vref, RX VrefLevel [Byte0]: 55
7903 23:42:35.967607 [Byte1]: 55
7904 23:42:35.972042
7905 23:42:35.972128 Set Vref, RX VrefLevel [Byte0]: 56
7906 23:42:35.975464 [Byte1]: 56
7907 23:42:35.979355
7908 23:42:35.979440 Set Vref, RX VrefLevel [Byte0]: 57
7909 23:42:35.983139 [Byte1]: 57
7910 23:42:35.987052
7911 23:42:35.987135 Set Vref, RX VrefLevel [Byte0]: 58
7912 23:42:35.991014 [Byte1]: 58
7913 23:42:35.994559
7914 23:42:35.994637 Set Vref, RX VrefLevel [Byte0]: 59
7915 23:42:36.001286 [Byte1]: 59
7916 23:42:36.001379
7917 23:42:36.004351 Set Vref, RX VrefLevel [Byte0]: 60
7918 23:42:36.007715 [Byte1]: 60
7919 23:42:36.007790
7920 23:42:36.011166 Set Vref, RX VrefLevel [Byte0]: 61
7921 23:42:36.014248 [Byte1]: 61
7922 23:42:36.014321
7923 23:42:36.017674 Set Vref, RX VrefLevel [Byte0]: 62
7924 23:42:36.021103 [Byte1]: 62
7925 23:42:36.025054
7926 23:42:36.025125 Set Vref, RX VrefLevel [Byte0]: 63
7927 23:42:36.028507 [Byte1]: 63
7928 23:42:36.032567
7929 23:42:36.032640 Set Vref, RX VrefLevel [Byte0]: 64
7930 23:42:36.036241 [Byte1]: 64
7931 23:42:36.040362
7932 23:42:36.040438 Set Vref, RX VrefLevel [Byte0]: 65
7933 23:42:36.043724 [Byte1]: 65
7934 23:42:36.047573
7935 23:42:36.047643 Set Vref, RX VrefLevel [Byte0]: 66
7936 23:42:36.050937 [Byte1]: 66
7937 23:42:36.055606
7938 23:42:36.055721 Set Vref, RX VrefLevel [Byte0]: 67
7939 23:42:36.058836 [Byte1]: 67
7940 23:42:36.062972
7941 23:42:36.063065 Set Vref, RX VrefLevel [Byte0]: 68
7942 23:42:36.066016 [Byte1]: 68
7943 23:42:36.070227
7944 23:42:36.070332 Set Vref, RX VrefLevel [Byte0]: 69
7945 23:42:36.073694 [Byte1]: 69
7946 23:42:36.078246
7947 23:42:36.078324 Set Vref, RX VrefLevel [Byte0]: 70
7948 23:42:36.081329 [Byte1]: 70
7949 23:42:36.085765
7950 23:42:36.085839 Set Vref, RX VrefLevel [Byte0]: 71
7951 23:42:36.089024 [Byte1]: 71
7952 23:42:36.093128
7953 23:42:36.093201 Set Vref, RX VrefLevel [Byte0]: 72
7954 23:42:36.096584 [Byte1]: 72
7955 23:42:36.100609
7956 23:42:36.100687 Set Vref, RX VrefLevel [Byte0]: 73
7957 23:42:36.103931 [Byte1]: 73
7958 23:42:36.108700
7959 23:42:36.108769 Final RX Vref Byte 0 = 54 to rank0
7960 23:42:36.111720 Final RX Vref Byte 1 = 59 to rank0
7961 23:42:36.115260 Final RX Vref Byte 0 = 54 to rank1
7962 23:42:36.118170 Final RX Vref Byte 1 = 59 to rank1==
7963 23:42:36.121729 Dram Type= 6, Freq= 0, CH_0, rank 0
7964 23:42:36.128086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7965 23:42:36.128159 ==
7966 23:42:36.128222 DQS Delay:
7967 23:42:36.131188 DQS0 = 0, DQS1 = 0
7968 23:42:36.131259 DQM Delay:
7969 23:42:36.131323 DQM0 = 128, DQM1 = 123
7970 23:42:36.134777 DQ Delay:
7971 23:42:36.137732 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7972 23:42:36.141027 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =132
7973 23:42:36.144640 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7974 23:42:36.148032 DQ12 =130, DQ13 =128, DQ14 =134, DQ15 =130
7975 23:42:36.148104
7976 23:42:36.148165
7977 23:42:36.148220
7978 23:42:36.151065 [DramC_TX_OE_Calibration] TA2
7979 23:42:36.154711 Original DQ_B0 (3 6) =30, OEN = 27
7980 23:42:36.158187 Original DQ_B1 (3 6) =30, OEN = 27
7981 23:42:36.161123 24, 0x0, End_B0=24 End_B1=24
7982 23:42:36.161200 25, 0x0, End_B0=25 End_B1=25
7983 23:42:36.164537 26, 0x0, End_B0=26 End_B1=26
7984 23:42:36.167581 27, 0x0, End_B0=27 End_B1=27
7985 23:42:36.170947 28, 0x0, End_B0=28 End_B1=28
7986 23:42:36.174430 29, 0x0, End_B0=29 End_B1=29
7987 23:42:36.174499 30, 0x0, End_B0=30 End_B1=30
7988 23:42:36.177518 31, 0x4545, End_B0=30 End_B1=30
7989 23:42:36.180891 Byte0 end_step=30 best_step=27
7990 23:42:36.184153 Byte1 end_step=30 best_step=27
7991 23:42:36.187541 Byte0 TX OE(2T, 0.5T) = (3, 3)
7992 23:42:36.190678 Byte1 TX OE(2T, 0.5T) = (3, 3)
7993 23:42:36.190750
7994 23:42:36.190811
7995 23:42:36.197166 [DQSOSCAuto] RK0, (LSB)MR18= 0x1815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7996 23:42:36.200708 CH0 RK0: MR19=303, MR18=1815
7997 23:42:36.207208 CH0_RK0: MR19=0x303, MR18=0x1815, DQSOSC=397, MR23=63, INC=23, DEC=15
7998 23:42:36.207284
7999 23:42:36.210454 ----->DramcWriteLeveling(PI) begin...
8000 23:42:36.210535 ==
8001 23:42:36.213583 Dram Type= 6, Freq= 0, CH_0, rank 1
8002 23:42:36.217306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8003 23:42:36.217405 ==
8004 23:42:36.220533 Write leveling (Byte 0): 36 => 36
8005 23:42:36.223639 Write leveling (Byte 1): 28 => 28
8006 23:42:36.226896 DramcWriteLeveling(PI) end<-----
8007 23:42:36.226968
8008 23:42:36.227028 ==
8009 23:42:36.230428 Dram Type= 6, Freq= 0, CH_0, rank 1
8010 23:42:36.236727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8011 23:42:36.236803 ==
8012 23:42:36.236865 [Gating] SW mode calibration
8013 23:42:36.246595 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8014 23:42:36.250221 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8015 23:42:36.256497 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8016 23:42:36.259980 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8017 23:42:36.263092 1 4 8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8018 23:42:36.266520 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8019 23:42:36.273220 1 4 16 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8020 23:42:36.276263 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8021 23:42:36.279565 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8022 23:42:36.286021 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8023 23:42:36.289372 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8024 23:42:36.296059 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8025 23:42:36.299672 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
8026 23:42:36.302595 1 5 12 | B1->B0 | 3434 2727 | 1 0 | (1 1) (1 0)
8027 23:42:36.305885 1 5 16 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8028 23:42:36.312586 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8029 23:42:36.316301 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 23:42:36.322369 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 23:42:36.325709 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 23:42:36.329241 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8033 23:42:36.335776 1 6 8 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (1 1)
8034 23:42:36.338785 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8035 23:42:36.342312 1 6 16 | B1->B0 | 3130 4646 | 1 0 | (0 0) (0 0)
8036 23:42:36.348557 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8037 23:42:36.352280 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 23:42:36.355947 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8039 23:42:36.361820 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8040 23:42:36.365192 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8041 23:42:36.368596 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8042 23:42:36.375197 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8043 23:42:36.378045 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8044 23:42:36.381662 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8045 23:42:36.388132 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 23:42:36.391602 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 23:42:36.395091 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 23:42:36.401153 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 23:42:36.404719 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 23:42:36.407860 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8051 23:42:36.414994 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8052 23:42:36.418049 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8053 23:42:36.421450 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8054 23:42:36.428046 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 23:42:36.430973 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 23:42:36.434388 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 23:42:36.440747 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8058 23:42:36.444037 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8059 23:42:36.447623 Total UI for P1: 0, mck2ui 16
8060 23:42:36.450803 best dqsien dly found for B0: ( 1, 9, 8)
8061 23:42:36.454123 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8062 23:42:36.460827 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8063 23:42:36.463926 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8064 23:42:36.467409 Total UI for P1: 0, mck2ui 16
8065 23:42:36.470763 best dqsien dly found for B1: ( 1, 9, 18)
8066 23:42:36.474192 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8067 23:42:36.477175 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8068 23:42:36.477288
8069 23:42:36.480283 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8070 23:42:36.483878 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8071 23:42:36.486738 [Gating] SW calibration Done
8072 23:42:36.486820 ==
8073 23:42:36.490195 Dram Type= 6, Freq= 0, CH_0, rank 1
8074 23:42:36.493726 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8075 23:42:36.497049 ==
8076 23:42:36.497125 RX Vref Scan: 0
8077 23:42:36.497221
8078 23:42:36.500375 RX Vref 0 -> 0, step: 1
8079 23:42:36.500451
8080 23:42:36.500514 RX Delay 0 -> 252, step: 8
8081 23:42:36.506639 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8082 23:42:36.510068 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8083 23:42:36.513733 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8084 23:42:36.517039 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8085 23:42:36.520252 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8086 23:42:36.526380 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8087 23:42:36.530072 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8088 23:42:36.533147 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8089 23:42:36.536618 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8090 23:42:36.543070 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8091 23:42:36.546068 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8092 23:42:36.549615 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8093 23:42:36.552676 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8094 23:42:36.556305 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8095 23:42:36.562605 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8096 23:42:36.566042 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8097 23:42:36.566124 ==
8098 23:42:36.569435 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 23:42:36.572570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 23:42:36.572653 ==
8101 23:42:36.576517 DQS Delay:
8102 23:42:36.576598 DQS0 = 0, DQS1 = 0
8103 23:42:36.579215 DQM Delay:
8104 23:42:36.579299 DQM0 = 131, DQM1 = 126
8105 23:42:36.579363 DQ Delay:
8106 23:42:36.582499 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
8107 23:42:36.588802 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8108 23:42:36.592189 DQ8 =119, DQ9 =111, DQ10 =131, DQ11 =119
8109 23:42:36.595348 DQ12 =127, DQ13 =135, DQ14 =135, DQ15 =135
8110 23:42:36.595431
8111 23:42:36.595497
8112 23:42:36.595566 ==
8113 23:42:36.599148 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 23:42:36.602477 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 23:42:36.602612 ==
8116 23:42:36.602719
8117 23:42:36.602801
8118 23:42:36.605163 TX Vref Scan disable
8119 23:42:36.608613 == TX Byte 0 ==
8120 23:42:36.612095 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8121 23:42:36.615247 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8122 23:42:36.618814 == TX Byte 1 ==
8123 23:42:36.621611 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8124 23:42:36.625068 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8125 23:42:36.625146 ==
8126 23:42:36.628392 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 23:42:36.635079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 23:42:36.635160 ==
8129 23:42:36.648830
8130 23:42:36.652019 TX Vref early break, caculate TX vref
8131 23:42:36.655141 TX Vref=16, minBit 9, minWin=22, winSum=378
8132 23:42:36.658388 TX Vref=18, minBit 9, minWin=23, winSum=391
8133 23:42:36.661679 TX Vref=20, minBit 2, minWin=24, winSum=399
8134 23:42:36.665050 TX Vref=22, minBit 10, minWin=24, winSum=405
8135 23:42:36.668398 TX Vref=24, minBit 1, minWin=25, winSum=413
8136 23:42:36.675052 TX Vref=26, minBit 0, minWin=26, winSum=421
8137 23:42:36.678324 TX Vref=28, minBit 0, minWin=26, winSum=421
8138 23:42:36.681977 TX Vref=30, minBit 1, minWin=25, winSum=418
8139 23:42:36.684686 TX Vref=32, minBit 0, minWin=25, winSum=406
8140 23:42:36.688335 TX Vref=34, minBit 0, minWin=24, winSum=403
8141 23:42:36.694963 TX Vref=36, minBit 0, minWin=24, winSum=395
8142 23:42:36.697917 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 26
8143 23:42:36.698004
8144 23:42:36.701197 Final TX Range 0 Vref 26
8145 23:42:36.701306
8146 23:42:36.701373 ==
8147 23:42:36.704712 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 23:42:36.708357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 23:42:36.711312 ==
8150 23:42:36.711395
8151 23:42:36.711460
8152 23:42:36.711520 TX Vref Scan disable
8153 23:42:36.717770 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8154 23:42:36.717853 == TX Byte 0 ==
8155 23:42:36.721643 u2DelayCellOfst[0]=14 cells (4 PI)
8156 23:42:36.724472 u2DelayCellOfst[1]=17 cells (5 PI)
8157 23:42:36.727922 u2DelayCellOfst[2]=10 cells (3 PI)
8158 23:42:36.731462 u2DelayCellOfst[3]=10 cells (3 PI)
8159 23:42:36.734236 u2DelayCellOfst[4]=10 cells (3 PI)
8160 23:42:36.737481 u2DelayCellOfst[5]=0 cells (0 PI)
8161 23:42:36.740917 u2DelayCellOfst[6]=17 cells (5 PI)
8162 23:42:36.744281 u2DelayCellOfst[7]=17 cells (5 PI)
8163 23:42:36.747847 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8164 23:42:36.751119 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8165 23:42:36.754062 == TX Byte 1 ==
8166 23:42:36.757300 u2DelayCellOfst[8]=0 cells (0 PI)
8167 23:42:36.760815 u2DelayCellOfst[9]=0 cells (0 PI)
8168 23:42:36.764065 u2DelayCellOfst[10]=3 cells (1 PI)
8169 23:42:36.767444 u2DelayCellOfst[11]=3 cells (1 PI)
8170 23:42:36.770769 u2DelayCellOfst[12]=10 cells (3 PI)
8171 23:42:36.774109 u2DelayCellOfst[13]=10 cells (3 PI)
8172 23:42:36.777096 u2DelayCellOfst[14]=14 cells (4 PI)
8173 23:42:36.780773 u2DelayCellOfst[15]=14 cells (4 PI)
8174 23:42:36.783881 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8175 23:42:36.786761 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8176 23:42:36.790039 DramC Write-DBI on
8177 23:42:36.790121 ==
8178 23:42:36.793953 Dram Type= 6, Freq= 0, CH_0, rank 1
8179 23:42:36.797036 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8180 23:42:36.797119 ==
8181 23:42:36.797183
8182 23:42:36.797243
8183 23:42:36.799946 TX Vref Scan disable
8184 23:42:36.803149 == TX Byte 0 ==
8185 23:42:36.806769 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8186 23:42:36.806853 == TX Byte 1 ==
8187 23:42:36.813448 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8188 23:42:36.813526 DramC Write-DBI off
8189 23:42:36.813589
8190 23:42:36.816702 [DATLAT]
8191 23:42:36.816782 Freq=1600, CH0 RK1
8192 23:42:36.816846
8193 23:42:36.819992 DATLAT Default: 0xf
8194 23:42:36.820073 0, 0xFFFF, sum = 0
8195 23:42:36.823123 1, 0xFFFF, sum = 0
8196 23:42:36.823206 2, 0xFFFF, sum = 0
8197 23:42:36.826551 3, 0xFFFF, sum = 0
8198 23:42:36.826634 4, 0xFFFF, sum = 0
8199 23:42:36.830264 5, 0xFFFF, sum = 0
8200 23:42:36.830349 6, 0xFFFF, sum = 0
8201 23:42:36.833213 7, 0xFFFF, sum = 0
8202 23:42:36.833326 8, 0xFFFF, sum = 0
8203 23:42:36.836296 9, 0xFFFF, sum = 0
8204 23:42:36.836405 10, 0xFFFF, sum = 0
8205 23:42:36.839787 11, 0xFFFF, sum = 0
8206 23:42:36.839914 12, 0xFFFF, sum = 0
8207 23:42:36.842717 13, 0xFFFF, sum = 0
8208 23:42:36.846247 14, 0x0, sum = 1
8209 23:42:36.846335 15, 0x0, sum = 2
8210 23:42:36.846407 16, 0x0, sum = 3
8211 23:42:36.849785 17, 0x0, sum = 4
8212 23:42:36.849898 best_step = 15
8213 23:42:36.850005
8214 23:42:36.850105 ==
8215 23:42:36.853051 Dram Type= 6, Freq= 0, CH_0, rank 1
8216 23:42:36.859652 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8217 23:42:36.859734 ==
8218 23:42:36.859799 RX Vref Scan: 0
8219 23:42:36.859859
8220 23:42:36.862526 RX Vref 0 -> 0, step: 1
8221 23:42:36.862595
8222 23:42:36.866029 RX Delay 11 -> 252, step: 4
8223 23:42:36.869468 iDelay=187, Bit 0, Center 126 (79 ~ 174) 96
8224 23:42:36.872489 iDelay=187, Bit 1, Center 130 (79 ~ 182) 104
8225 23:42:36.879054 iDelay=187, Bit 2, Center 122 (71 ~ 174) 104
8226 23:42:36.882631 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8227 23:42:36.885864 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8228 23:42:36.888908 iDelay=187, Bit 5, Center 118 (63 ~ 174) 112
8229 23:42:36.892413 iDelay=187, Bit 6, Center 138 (91 ~ 186) 96
8230 23:42:36.898610 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8231 23:42:36.902394 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8232 23:42:36.905314 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8233 23:42:36.908570 iDelay=187, Bit 10, Center 124 (71 ~ 178) 108
8234 23:42:36.912074 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8235 23:42:36.918568 iDelay=187, Bit 12, Center 128 (75 ~ 182) 108
8236 23:42:36.921615 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8237 23:42:36.925098 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8238 23:42:36.928171 iDelay=187, Bit 15, Center 132 (79 ~ 186) 108
8239 23:42:36.931763 ==
8240 23:42:36.931865 Dram Type= 6, Freq= 0, CH_0, rank 1
8241 23:42:36.938316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 23:42:36.938435 ==
8243 23:42:36.938568 DQS Delay:
8244 23:42:36.941406 DQS0 = 0, DQS1 = 0
8245 23:42:36.941490 DQM Delay:
8246 23:42:36.944634 DQM0 = 128, DQM1 = 123
8247 23:42:36.944734 DQ Delay:
8248 23:42:36.948075 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8249 23:42:36.951523 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
8250 23:42:36.955444 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8251 23:42:36.958191 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =132
8252 23:42:36.958290
8253 23:42:36.958380
8254 23:42:36.958515
8255 23:42:36.961221 [DramC_TX_OE_Calibration] TA2
8256 23:42:36.964825 Original DQ_B0 (3 6) =30, OEN = 27
8257 23:42:36.967818 Original DQ_B1 (3 6) =30, OEN = 27
8258 23:42:36.971680 24, 0x0, End_B0=24 End_B1=24
8259 23:42:36.974777 25, 0x0, End_B0=25 End_B1=25
8260 23:42:36.974853 26, 0x0, End_B0=26 End_B1=26
8261 23:42:36.977618 27, 0x0, End_B0=27 End_B1=27
8262 23:42:36.981063 28, 0x0, End_B0=28 End_B1=28
8263 23:42:36.984604 29, 0x0, End_B0=29 End_B1=29
8264 23:42:36.988125 30, 0x0, End_B0=30 End_B1=30
8265 23:42:36.988208 31, 0x4141, End_B0=30 End_B1=30
8266 23:42:36.990958 Byte0 end_step=30 best_step=27
8267 23:42:36.994080 Byte1 end_step=30 best_step=27
8268 23:42:36.997636 Byte0 TX OE(2T, 0.5T) = (3, 3)
8269 23:42:37.000800 Byte1 TX OE(2T, 0.5T) = (3, 3)
8270 23:42:37.000912
8271 23:42:37.001006
8272 23:42:37.007653 [DQSOSCAuto] RK1, (LSB)MR18= 0x1613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
8273 23:42:37.010786 CH0 RK1: MR19=303, MR18=1613
8274 23:42:37.017466 CH0_RK1: MR19=0x303, MR18=0x1613, DQSOSC=398, MR23=63, INC=23, DEC=15
8275 23:42:37.020862 [RxdqsGatingPostProcess] freq 1600
8276 23:42:37.027288 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8277 23:42:37.030390 best DQS0 dly(2T, 0.5T) = (1, 1)
8278 23:42:37.033490 best DQS1 dly(2T, 0.5T) = (1, 1)
8279 23:42:37.036821 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8280 23:42:37.036897 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8281 23:42:37.040213 best DQS0 dly(2T, 0.5T) = (1, 1)
8282 23:42:37.043470 best DQS1 dly(2T, 0.5T) = (1, 1)
8283 23:42:37.046993 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8284 23:42:37.050529 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8285 23:42:37.053654 Pre-setting of DQS Precalculation
8286 23:42:37.060049 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8287 23:42:37.060159 ==
8288 23:42:37.063370 Dram Type= 6, Freq= 0, CH_1, rank 0
8289 23:42:37.066608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8290 23:42:37.066714 ==
8291 23:42:37.073196 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8292 23:42:37.076390 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8293 23:42:37.079874 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8294 23:42:37.086697 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8295 23:42:37.095070 [CA 0] Center 42 (13~72) winsize 60
8296 23:42:37.098733 [CA 1] Center 43 (13~73) winsize 61
8297 23:42:37.101739 [CA 2] Center 39 (9~69) winsize 61
8298 23:42:37.105358 [CA 3] Center 38 (8~68) winsize 61
8299 23:42:37.108295 [CA 4] Center 38 (8~69) winsize 62
8300 23:42:37.111818 [CA 5] Center 37 (8~67) winsize 60
8301 23:42:37.111901
8302 23:42:37.114697 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8303 23:42:37.114780
8304 23:42:37.121839 [CATrainingPosCal] consider 1 rank data
8305 23:42:37.121923 u2DelayCellTimex100 = 275/100 ps
8306 23:42:37.127904 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8307 23:42:37.131415 CA1 delay=43 (13~73),Diff = 6 PI (21 cell)
8308 23:42:37.134735 CA2 delay=39 (9~69),Diff = 2 PI (7 cell)
8309 23:42:37.137791 CA3 delay=38 (8~68),Diff = 1 PI (3 cell)
8310 23:42:37.140980 CA4 delay=38 (8~69),Diff = 1 PI (3 cell)
8311 23:42:37.144724 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8312 23:42:37.144832
8313 23:42:37.148129 CA PerBit enable=1, Macro0, CA PI delay=37
8314 23:42:37.148229
8315 23:42:37.150865 [CBTSetCACLKResult] CA Dly = 37
8316 23:42:37.154498 CS Dly: 8 (0~39)
8317 23:42:37.157642 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8318 23:42:37.161150 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8319 23:42:37.161228 ==
8320 23:42:37.164124 Dram Type= 6, Freq= 0, CH_1, rank 1
8321 23:42:37.170780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8322 23:42:37.170865 ==
8323 23:42:37.174139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8324 23:42:37.180994 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8325 23:42:37.183955 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8326 23:42:37.190773 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8327 23:42:37.198157 [CA 0] Center 42 (12~72) winsize 61
8328 23:42:37.201253 [CA 1] Center 42 (13~72) winsize 60
8329 23:42:37.205235 [CA 2] Center 38 (9~67) winsize 59
8330 23:42:37.208017 [CA 3] Center 36 (7~66) winsize 60
8331 23:42:37.211444 [CA 4] Center 37 (8~67) winsize 60
8332 23:42:37.214493 [CA 5] Center 36 (7~66) winsize 60
8333 23:42:37.214577
8334 23:42:37.218179 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8335 23:42:37.218263
8336 23:42:37.224568 [CATrainingPosCal] consider 2 rank data
8337 23:42:37.224651 u2DelayCellTimex100 = 275/100 ps
8338 23:42:37.230922 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8339 23:42:37.234527 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8340 23:42:37.237515 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8341 23:42:37.240989 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8342 23:42:37.244526 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8343 23:42:37.247778 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8344 23:42:37.247861
8345 23:42:37.250903 CA PerBit enable=1, Macro0, CA PI delay=37
8346 23:42:37.251013
8347 23:42:37.254209 [CBTSetCACLKResult] CA Dly = 37
8348 23:42:37.257683 CS Dly: 9 (0~42)
8349 23:42:37.260637 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8350 23:42:37.264187 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8351 23:42:37.264270
8352 23:42:37.267105 ----->DramcWriteLeveling(PI) begin...
8353 23:42:37.267190 ==
8354 23:42:37.270432 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 23:42:37.276893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 23:42:37.276979 ==
8357 23:42:37.280475 Write leveling (Byte 0): 26 => 26
8358 23:42:37.284085 Write leveling (Byte 1): 26 => 26
8359 23:42:37.284198 DramcWriteLeveling(PI) end<-----
8360 23:42:37.287315
8361 23:42:37.287397 ==
8362 23:42:37.290804 Dram Type= 6, Freq= 0, CH_1, rank 0
8363 23:42:37.293500 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 23:42:37.293583 ==
8365 23:42:37.297143 [Gating] SW mode calibration
8366 23:42:37.303743 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8367 23:42:37.307301 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8368 23:42:37.313817 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8369 23:42:37.316823 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8370 23:42:37.320443 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8371 23:42:37.326997 1 4 12 | B1->B0 | 2323 3232 | 1 1 | (1 1) (1 1)
8372 23:42:37.330422 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
8373 23:42:37.333463 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8374 23:42:37.340212 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8375 23:42:37.343577 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8376 23:42:37.346535 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8377 23:42:37.353067 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8378 23:42:37.356323 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8379 23:42:37.359471 1 5 12 | B1->B0 | 3333 2626 | 1 0 | (1 0) (1 0)
8380 23:42:37.366341 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8381 23:42:37.369358 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 23:42:37.373237 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 23:42:37.379734 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 23:42:37.383657 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 23:42:37.389590 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 23:42:37.392607 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8387 23:42:37.395993 1 6 12 | B1->B0 | 2828 4343 | 0 0 | (0 0) (0 0)
8388 23:42:37.402677 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 23:42:37.405417 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 23:42:37.409114 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8391 23:42:37.415408 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8392 23:42:37.418887 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8393 23:42:37.421958 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8394 23:42:37.429004 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8395 23:42:37.431673 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8396 23:42:37.435168 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8397 23:42:37.441880 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 23:42:37.445108 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 23:42:37.448297 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 23:42:37.454642 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 23:42:37.458155 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 23:42:37.461341 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 23:42:37.468142 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 23:42:37.471172 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 23:42:37.474544 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 23:42:37.481255 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 23:42:37.484712 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 23:42:37.487933 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 23:42:37.494532 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 23:42:37.497701 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 23:42:37.501169 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8412 23:42:37.507224 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8413 23:42:37.507342 Total UI for P1: 0, mck2ui 16
8414 23:42:37.513827 best dqsien dly found for B0: ( 1, 9, 12)
8415 23:42:37.513909 Total UI for P1: 0, mck2ui 16
8416 23:42:37.520844 best dqsien dly found for B1: ( 1, 9, 12)
8417 23:42:37.523872 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8418 23:42:37.527255 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8419 23:42:37.527337
8420 23:42:37.531216 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8421 23:42:37.533834 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8422 23:42:37.537239 [Gating] SW calibration Done
8423 23:42:37.537344 ==
8424 23:42:37.540244 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 23:42:37.543833 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 23:42:37.543915 ==
8427 23:42:37.546945 RX Vref Scan: 0
8428 23:42:37.547027
8429 23:42:37.547090 RX Vref 0 -> 0, step: 1
8430 23:42:37.547149
8431 23:42:37.550549 RX Delay 0 -> 252, step: 8
8432 23:42:37.553730 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8433 23:42:37.560675 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8434 23:42:37.563245 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8435 23:42:37.566633 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8436 23:42:37.570131 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8437 23:42:37.573551 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8438 23:42:37.580221 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8439 23:42:37.583034 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8440 23:42:37.586614 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8441 23:42:37.590043 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8442 23:42:37.596295 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8443 23:42:37.600138 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8444 23:42:37.602897 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8445 23:42:37.606159 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8446 23:42:37.609763 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8447 23:42:37.616471 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8448 23:42:37.616552 ==
8449 23:42:37.619491 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 23:42:37.622746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 23:42:37.622905 ==
8452 23:42:37.623001 DQS Delay:
8453 23:42:37.626074 DQS0 = 0, DQS1 = 0
8454 23:42:37.626155 DQM Delay:
8455 23:42:37.629881 DQM0 = 135, DQM1 = 130
8456 23:42:37.629963 DQ Delay:
8457 23:42:37.632646 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8458 23:42:37.635953 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =127
8459 23:42:37.639703 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8460 23:42:37.646034 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8461 23:42:37.646147
8462 23:42:37.646238
8463 23:42:37.646323 ==
8464 23:42:37.649226 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 23:42:37.652788 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 23:42:37.652871 ==
8467 23:42:37.652934
8468 23:42:37.652992
8469 23:42:37.655750 TX Vref Scan disable
8470 23:42:37.655831 == TX Byte 0 ==
8471 23:42:37.662411 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8472 23:42:37.665853 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8473 23:42:37.665935 == TX Byte 1 ==
8474 23:42:37.672070 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8475 23:42:37.675894 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8476 23:42:37.675975 ==
8477 23:42:37.678735 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 23:42:37.682058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 23:42:37.682140 ==
8480 23:42:37.696521
8481 23:42:37.700336 TX Vref early break, caculate TX vref
8482 23:42:37.703334 TX Vref=16, minBit 8, minWin=22, winSum=370
8483 23:42:37.706463 TX Vref=18, minBit 8, minWin=21, winSum=378
8484 23:42:37.709774 TX Vref=20, minBit 8, minWin=23, winSum=389
8485 23:42:37.713163 TX Vref=22, minBit 8, minWin=22, winSum=397
8486 23:42:37.716431 TX Vref=24, minBit 8, minWin=23, winSum=408
8487 23:42:37.722860 TX Vref=26, minBit 8, minWin=24, winSum=414
8488 23:42:37.726339 TX Vref=28, minBit 13, minWin=25, winSum=420
8489 23:42:37.729714 TX Vref=30, minBit 8, minWin=25, winSum=414
8490 23:42:37.733028 TX Vref=32, minBit 9, minWin=24, winSum=410
8491 23:42:37.736373 TX Vref=34, minBit 0, minWin=24, winSum=401
8492 23:42:37.742852 TX Vref=36, minBit 8, minWin=23, winSum=389
8493 23:42:37.746424 [TxChooseVref] Worse bit 13, Min win 25, Win sum 420, Final Vref 28
8494 23:42:37.746513
8495 23:42:37.749230 Final TX Range 0 Vref 28
8496 23:42:37.749374
8497 23:42:37.749466 ==
8498 23:42:37.752707 Dram Type= 6, Freq= 0, CH_1, rank 0
8499 23:42:37.756159 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8500 23:42:37.759536 ==
8501 23:42:37.759616
8502 23:42:37.759679
8503 23:42:37.759738 TX Vref Scan disable
8504 23:42:37.765958 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8505 23:42:37.766039 == TX Byte 0 ==
8506 23:42:37.769160 u2DelayCellOfst[0]=17 cells (5 PI)
8507 23:42:37.773087 u2DelayCellOfst[1]=10 cells (3 PI)
8508 23:42:37.775938 u2DelayCellOfst[2]=0 cells (0 PI)
8509 23:42:37.779462 u2DelayCellOfst[3]=7 cells (2 PI)
8510 23:42:37.782740 u2DelayCellOfst[4]=10 cells (3 PI)
8511 23:42:37.786054 u2DelayCellOfst[5]=17 cells (5 PI)
8512 23:42:37.789057 u2DelayCellOfst[6]=14 cells (4 PI)
8513 23:42:37.792404 u2DelayCellOfst[7]=7 cells (2 PI)
8514 23:42:37.795754 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8515 23:42:37.799347 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8516 23:42:37.802556 == TX Byte 1 ==
8517 23:42:37.805483 u2DelayCellOfst[8]=0 cells (0 PI)
8518 23:42:37.809059 u2DelayCellOfst[9]=3 cells (1 PI)
8519 23:42:37.812249 u2DelayCellOfst[10]=10 cells (3 PI)
8520 23:42:37.815947 u2DelayCellOfst[11]=3 cells (1 PI)
8521 23:42:37.818794 u2DelayCellOfst[12]=14 cells (4 PI)
8522 23:42:37.822013 u2DelayCellOfst[13]=17 cells (5 PI)
8523 23:42:37.825430 u2DelayCellOfst[14]=17 cells (5 PI)
8524 23:42:37.825534 u2DelayCellOfst[15]=21 cells (6 PI)
8525 23:42:37.832322 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8526 23:42:37.835560 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8527 23:42:37.838936 DramC Write-DBI on
8528 23:42:37.839065 ==
8529 23:42:37.842145 Dram Type= 6, Freq= 0, CH_1, rank 0
8530 23:42:37.845042 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8531 23:42:37.845152 ==
8532 23:42:37.845247
8533 23:42:37.845431
8534 23:42:37.848691 TX Vref Scan disable
8535 23:42:37.848792 == TX Byte 0 ==
8536 23:42:37.855330 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8537 23:42:37.855436 == TX Byte 1 ==
8538 23:42:37.858733 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8539 23:42:37.861581 DramC Write-DBI off
8540 23:42:37.861683
8541 23:42:37.861781 [DATLAT]
8542 23:42:37.865177 Freq=1600, CH1 RK0
8543 23:42:37.865377
8544 23:42:37.865476 DATLAT Default: 0xf
8545 23:42:37.868577 0, 0xFFFF, sum = 0
8546 23:42:37.871408 1, 0xFFFF, sum = 0
8547 23:42:37.871513 2, 0xFFFF, sum = 0
8548 23:42:37.874818 3, 0xFFFF, sum = 0
8549 23:42:37.874917 4, 0xFFFF, sum = 0
8550 23:42:37.878469 5, 0xFFFF, sum = 0
8551 23:42:37.878570 6, 0xFFFF, sum = 0
8552 23:42:37.881448 7, 0xFFFF, sum = 0
8553 23:42:37.881527 8, 0xFFFF, sum = 0
8554 23:42:37.884808 9, 0xFFFF, sum = 0
8555 23:42:37.884912 10, 0xFFFF, sum = 0
8556 23:42:37.888128 11, 0xFFFF, sum = 0
8557 23:42:37.888235 12, 0xFFFF, sum = 0
8558 23:42:37.891856 13, 0xFFFF, sum = 0
8559 23:42:37.891959 14, 0x0, sum = 1
8560 23:42:37.894628 15, 0x0, sum = 2
8561 23:42:37.894710 16, 0x0, sum = 3
8562 23:42:37.897802 17, 0x0, sum = 4
8563 23:42:37.897889 best_step = 15
8564 23:42:37.897970
8565 23:42:37.898047 ==
8566 23:42:37.901033 Dram Type= 6, Freq= 0, CH_1, rank 0
8567 23:42:37.907990 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8568 23:42:37.908097 ==
8569 23:42:37.908200 RX Vref Scan: 1
8570 23:42:37.908298
8571 23:42:37.911467 Set Vref Range= 24 -> 127
8572 23:42:37.911571
8573 23:42:37.914571 RX Vref 24 -> 127, step: 1
8574 23:42:37.914671
8575 23:42:37.914771 RX Delay 19 -> 252, step: 4
8576 23:42:37.914868
8577 23:42:37.918082 Set Vref, RX VrefLevel [Byte0]: 24
8578 23:42:37.921545 [Byte1]: 24
8579 23:42:37.925089
8580 23:42:37.925195 Set Vref, RX VrefLevel [Byte0]: 25
8581 23:42:37.928362 [Byte1]: 25
8582 23:42:37.932802
8583 23:42:37.932912 Set Vref, RX VrefLevel [Byte0]: 26
8584 23:42:37.935835 [Byte1]: 26
8585 23:42:37.940606
8586 23:42:37.940710 Set Vref, RX VrefLevel [Byte0]: 27
8587 23:42:37.943571 [Byte1]: 27
8588 23:42:37.947941
8589 23:42:37.948044 Set Vref, RX VrefLevel [Byte0]: 28
8590 23:42:37.951248 [Byte1]: 28
8591 23:42:37.955910
8592 23:42:37.956015 Set Vref, RX VrefLevel [Byte0]: 29
8593 23:42:37.958713 [Byte1]: 29
8594 23:42:37.963531
8595 23:42:37.963635 Set Vref, RX VrefLevel [Byte0]: 30
8596 23:42:37.966128 [Byte1]: 30
8597 23:42:37.970684
8598 23:42:37.970760 Set Vref, RX VrefLevel [Byte0]: 31
8599 23:42:37.974245 [Byte1]: 31
8600 23:42:37.978238
8601 23:42:37.978341 Set Vref, RX VrefLevel [Byte0]: 32
8602 23:42:37.981211 [Byte1]: 32
8603 23:42:37.985961
8604 23:42:37.986069 Set Vref, RX VrefLevel [Byte0]: 33
8605 23:42:37.989202 [Byte1]: 33
8606 23:42:37.993465
8607 23:42:37.993554 Set Vref, RX VrefLevel [Byte0]: 34
8608 23:42:37.997198 [Byte1]: 34
8609 23:42:38.001008
8610 23:42:38.001108 Set Vref, RX VrefLevel [Byte0]: 35
8611 23:42:38.004067 [Byte1]: 35
8612 23:42:38.008321
8613 23:42:38.008399 Set Vref, RX VrefLevel [Byte0]: 36
8614 23:42:38.011556 [Byte1]: 36
8615 23:42:38.016176
8616 23:42:38.016277 Set Vref, RX VrefLevel [Byte0]: 37
8617 23:42:38.019266 [Byte1]: 37
8618 23:42:38.023585
8619 23:42:38.023691 Set Vref, RX VrefLevel [Byte0]: 38
8620 23:42:38.027076 [Byte1]: 38
8621 23:42:38.031278
8622 23:42:38.031383 Set Vref, RX VrefLevel [Byte0]: 39
8623 23:42:38.034518 [Byte1]: 39
8624 23:42:38.038991
8625 23:42:38.039140 Set Vref, RX VrefLevel [Byte0]: 40
8626 23:42:38.041986 [Byte1]: 40
8627 23:42:38.046447
8628 23:42:38.046547 Set Vref, RX VrefLevel [Byte0]: 41
8629 23:42:38.049713 [Byte1]: 41
8630 23:42:38.053907
8631 23:42:38.053984 Set Vref, RX VrefLevel [Byte0]: 42
8632 23:42:38.057215 [Byte1]: 42
8633 23:42:38.061605
8634 23:42:38.061683 Set Vref, RX VrefLevel [Byte0]: 43
8635 23:42:38.064925 [Byte1]: 43
8636 23:42:38.069523
8637 23:42:38.069597 Set Vref, RX VrefLevel [Byte0]: 44
8638 23:42:38.072345 [Byte1]: 44
8639 23:42:38.076895
8640 23:42:38.077008 Set Vref, RX VrefLevel [Byte0]: 45
8641 23:42:38.079996 [Byte1]: 45
8642 23:42:38.083963
8643 23:42:38.084060 Set Vref, RX VrefLevel [Byte0]: 46
8644 23:42:38.087407 [Byte1]: 46
8645 23:42:38.091578
8646 23:42:38.091657 Set Vref, RX VrefLevel [Byte0]: 47
8647 23:42:38.094820 [Byte1]: 47
8648 23:42:38.099614
8649 23:42:38.099753 Set Vref, RX VrefLevel [Byte0]: 48
8650 23:42:38.102486 [Byte1]: 48
8651 23:42:38.107056
8652 23:42:38.107184 Set Vref, RX VrefLevel [Byte0]: 49
8653 23:42:38.110144 [Byte1]: 49
8654 23:42:38.114439
8655 23:42:38.114540 Set Vref, RX VrefLevel [Byte0]: 50
8656 23:42:38.117616 [Byte1]: 50
8657 23:42:38.122320
8658 23:42:38.122455 Set Vref, RX VrefLevel [Byte0]: 51
8659 23:42:38.125282 [Byte1]: 51
8660 23:42:38.129823
8661 23:42:38.129901 Set Vref, RX VrefLevel [Byte0]: 52
8662 23:42:38.132809 [Byte1]: 52
8663 23:42:38.136925
8664 23:42:38.137019 Set Vref, RX VrefLevel [Byte0]: 53
8665 23:42:38.140712 [Byte1]: 53
8666 23:42:38.145055
8667 23:42:38.145167 Set Vref, RX VrefLevel [Byte0]: 54
8668 23:42:38.148206 [Byte1]: 54
8669 23:42:38.152833
8670 23:42:38.152916 Set Vref, RX VrefLevel [Byte0]: 55
8671 23:42:38.155725 [Byte1]: 55
8672 23:42:38.160291
8673 23:42:38.160365 Set Vref, RX VrefLevel [Byte0]: 56
8674 23:42:38.163550 [Byte1]: 56
8675 23:42:38.168034
8676 23:42:38.168120 Set Vref, RX VrefLevel [Byte0]: 57
8677 23:42:38.170700 [Byte1]: 57
8678 23:42:38.175129
8679 23:42:38.175209 Set Vref, RX VrefLevel [Byte0]: 58
8680 23:42:38.178479 [Byte1]: 58
8681 23:42:38.182919
8682 23:42:38.182998 Set Vref, RX VrefLevel [Byte0]: 59
8683 23:42:38.186087 [Byte1]: 59
8684 23:42:38.190298
8685 23:42:38.190378 Set Vref, RX VrefLevel [Byte0]: 60
8686 23:42:38.193865 [Byte1]: 60
8687 23:42:38.197933
8688 23:42:38.198016 Set Vref, RX VrefLevel [Byte0]: 61
8689 23:42:38.201027 [Byte1]: 61
8690 23:42:38.205464
8691 23:42:38.205546 Set Vref, RX VrefLevel [Byte0]: 62
8692 23:42:38.208542 [Byte1]: 62
8693 23:42:38.212963
8694 23:42:38.213048 Set Vref, RX VrefLevel [Byte0]: 63
8695 23:42:38.216528 [Byte1]: 63
8696 23:42:38.220452
8697 23:42:38.220534 Set Vref, RX VrefLevel [Byte0]: 64
8698 23:42:38.223869 [Byte1]: 64
8699 23:42:38.227913
8700 23:42:38.227995 Set Vref, RX VrefLevel [Byte0]: 65
8701 23:42:38.231602 [Byte1]: 65
8702 23:42:38.235789
8703 23:42:38.235871 Set Vref, RX VrefLevel [Byte0]: 66
8704 23:42:38.239351 [Byte1]: 66
8705 23:42:38.243562
8706 23:42:38.243644 Set Vref, RX VrefLevel [Byte0]: 67
8707 23:42:38.246407 [Byte1]: 67
8708 23:42:38.251120
8709 23:42:38.251202 Set Vref, RX VrefLevel [Byte0]: 68
8710 23:42:38.254135 [Byte1]: 68
8711 23:42:38.258531
8712 23:42:38.258613 Set Vref, RX VrefLevel [Byte0]: 69
8713 23:42:38.261868 [Byte1]: 69
8714 23:42:38.266346
8715 23:42:38.266428 Set Vref, RX VrefLevel [Byte0]: 70
8716 23:42:38.269530 [Byte1]: 70
8717 23:42:38.273976
8718 23:42:38.274058 Set Vref, RX VrefLevel [Byte0]: 71
8719 23:42:38.276931 [Byte1]: 71
8720 23:42:38.281379
8721 23:42:38.281471 Set Vref, RX VrefLevel [Byte0]: 72
8722 23:42:38.284906 [Byte1]: 72
8723 23:42:38.288636
8724 23:42:38.288719 Set Vref, RX VrefLevel [Byte0]: 73
8725 23:42:38.292067 [Byte1]: 73
8726 23:42:38.296096
8727 23:42:38.296182 Set Vref, RX VrefLevel [Byte0]: 74
8728 23:42:38.299443 [Byte1]: 74
8729 23:42:38.303789
8730 23:42:38.303900 Final RX Vref Byte 0 = 60 to rank0
8731 23:42:38.307183 Final RX Vref Byte 1 = 61 to rank0
8732 23:42:38.310671 Final RX Vref Byte 0 = 60 to rank1
8733 23:42:38.313778 Final RX Vref Byte 1 = 61 to rank1==
8734 23:42:38.317028 Dram Type= 6, Freq= 0, CH_1, rank 0
8735 23:42:38.323933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8736 23:42:38.324019 ==
8737 23:42:38.324084 DQS Delay:
8738 23:42:38.324143 DQS0 = 0, DQS1 = 0
8739 23:42:38.326935 DQM Delay:
8740 23:42:38.327015 DQM0 = 132, DQM1 = 128
8741 23:42:38.330426 DQ Delay:
8742 23:42:38.333631 DQ0 =138, DQ1 =128, DQ2 =118, DQ3 =132
8743 23:42:38.336866 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8744 23:42:38.340232 DQ8 =112, DQ9 =116, DQ10 =128, DQ11 =120
8745 23:42:38.343081 DQ12 =140, DQ13 =138, DQ14 =134, DQ15 =136
8746 23:42:38.343161
8747 23:42:38.343224
8748 23:42:38.343282
8749 23:42:38.346693 [DramC_TX_OE_Calibration] TA2
8750 23:42:38.350422 Original DQ_B0 (3 6) =30, OEN = 27
8751 23:42:38.353413 Original DQ_B1 (3 6) =30, OEN = 27
8752 23:42:38.356724 24, 0x0, End_B0=24 End_B1=24
8753 23:42:38.359659 25, 0x0, End_B0=25 End_B1=25
8754 23:42:38.359741 26, 0x0, End_B0=26 End_B1=26
8755 23:42:38.363684 27, 0x0, End_B0=27 End_B1=27
8756 23:42:38.366473 28, 0x0, End_B0=28 End_B1=28
8757 23:42:38.370044 29, 0x0, End_B0=29 End_B1=29
8758 23:42:38.370125 30, 0x0, End_B0=30 End_B1=30
8759 23:42:38.373448 31, 0x4141, End_B0=30 End_B1=30
8760 23:42:38.376636 Byte0 end_step=30 best_step=27
8761 23:42:38.379729 Byte1 end_step=30 best_step=27
8762 23:42:38.382835 Byte0 TX OE(2T, 0.5T) = (3, 3)
8763 23:42:38.386269 Byte1 TX OE(2T, 0.5T) = (3, 3)
8764 23:42:38.386349
8765 23:42:38.386412
8766 23:42:38.393143 [DQSOSCAuto] RK0, (LSB)MR18= 0x1019, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 401 ps
8767 23:42:38.396269 CH1 RK0: MR19=303, MR18=1019
8768 23:42:38.402479 CH1_RK0: MR19=0x303, MR18=0x1019, DQSOSC=397, MR23=63, INC=23, DEC=15
8769 23:42:38.402561
8770 23:42:38.406116 ----->DramcWriteLeveling(PI) begin...
8771 23:42:38.406208 ==
8772 23:42:38.408961 Dram Type= 6, Freq= 0, CH_1, rank 1
8773 23:42:38.412254 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8774 23:42:38.412335 ==
8775 23:42:38.415751 Write leveling (Byte 0): 22 => 22
8776 23:42:38.419034 Write leveling (Byte 1): 26 => 26
8777 23:42:38.422232 DramcWriteLeveling(PI) end<-----
8778 23:42:38.422327
8779 23:42:38.422389 ==
8780 23:42:38.425466 Dram Type= 6, Freq= 0, CH_1, rank 1
8781 23:42:38.432079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8782 23:42:38.432190 ==
8783 23:42:38.432283 [Gating] SW mode calibration
8784 23:42:38.442283 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8785 23:42:38.445114 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8786 23:42:38.451727 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8787 23:42:38.455183 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 23:42:38.458568 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8789 23:42:38.464831 1 4 12 | B1->B0 | 2b2b 3434 | 0 1 | (1 1) (1 1)
8790 23:42:38.468458 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8791 23:42:38.471598 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 23:42:38.478081 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 23:42:38.481374 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 23:42:38.484819 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 23:42:38.491850 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8796 23:42:38.495156 1 5 8 | B1->B0 | 3434 2828 | 1 0 | (1 0) (1 0)
8797 23:42:38.498207 1 5 12 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
8798 23:42:38.504521 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8799 23:42:38.507968 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 23:42:38.511084 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 23:42:38.518143 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 23:42:38.521127 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 23:42:38.524661 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8804 23:42:38.531011 1 6 8 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
8805 23:42:38.534590 1 6 12 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8806 23:42:38.537403 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8807 23:42:38.544296 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 23:42:38.547308 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 23:42:38.551165 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 23:42:38.557454 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 23:42:38.560340 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8812 23:42:38.563649 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8813 23:42:38.570670 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8814 23:42:38.573509 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 23:42:38.576887 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 23:42:38.583824 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 23:42:38.586825 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 23:42:38.589879 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 23:42:38.596781 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 23:42:38.600160 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 23:42:38.603271 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 23:42:38.609765 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 23:42:38.612870 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 23:42:38.616398 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 23:42:38.623011 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 23:42:38.626306 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 23:42:38.629749 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8828 23:42:38.635952 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8829 23:42:38.639470 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8830 23:42:38.642605 Total UI for P1: 0, mck2ui 16
8831 23:42:38.645920 best dqsien dly found for B0: ( 1, 9, 6)
8832 23:42:38.649181 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8833 23:42:38.655929 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 23:42:38.656011 Total UI for P1: 0, mck2ui 16
8835 23:42:38.662638 best dqsien dly found for B1: ( 1, 9, 14)
8836 23:42:38.665524 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8837 23:42:38.668888 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8838 23:42:38.668969
8839 23:42:38.672651 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8840 23:42:38.675872 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8841 23:42:38.679005 [Gating] SW calibration Done
8842 23:42:38.679088 ==
8843 23:42:38.682560 Dram Type= 6, Freq= 0, CH_1, rank 1
8844 23:42:38.685437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8845 23:42:38.685519 ==
8846 23:42:38.689101 RX Vref Scan: 0
8847 23:42:38.689183
8848 23:42:38.689248 RX Vref 0 -> 0, step: 1
8849 23:42:38.689553
8850 23:42:38.692477 RX Delay 0 -> 252, step: 8
8851 23:42:38.695321 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8852 23:42:38.701770 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8853 23:42:38.705391 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8854 23:42:38.708865 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8855 23:42:38.711727 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8856 23:42:38.715165 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8857 23:42:38.721714 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8858 23:42:38.725104 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8859 23:42:38.728282 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8860 23:42:38.731430 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8861 23:42:38.738008 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8862 23:42:38.741523 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8863 23:42:38.744972 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8864 23:42:38.748000 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8865 23:42:38.751641 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8866 23:42:38.757813 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8867 23:42:38.757897 ==
8868 23:42:38.761279 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 23:42:38.764695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 23:42:38.764778 ==
8871 23:42:38.764843 DQS Delay:
8872 23:42:38.767929 DQS0 = 0, DQS1 = 0
8873 23:42:38.768012 DQM Delay:
8874 23:42:38.770909 DQM0 = 132, DQM1 = 130
8875 23:42:38.770992 DQ Delay:
8876 23:42:38.774645 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8877 23:42:38.777900 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8878 23:42:38.781097 DQ8 =115, DQ9 =119, DQ10 =135, DQ11 =123
8879 23:42:38.787566 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8880 23:42:38.787650
8881 23:42:38.787714
8882 23:42:38.787774 ==
8883 23:42:38.791124 Dram Type= 6, Freq= 0, CH_1, rank 1
8884 23:42:38.793821 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8885 23:42:38.793912 ==
8886 23:42:38.793978
8887 23:42:38.794038
8888 23:42:38.797513 TX Vref Scan disable
8889 23:42:38.797596 == TX Byte 0 ==
8890 23:42:38.803774 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8891 23:42:38.807089 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8892 23:42:38.807172 == TX Byte 1 ==
8893 23:42:38.813418 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8894 23:42:38.816906 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8895 23:42:38.816989 ==
8896 23:42:38.820146 Dram Type= 6, Freq= 0, CH_1, rank 1
8897 23:42:38.823577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8898 23:42:38.823660 ==
8899 23:42:38.838723
8900 23:42:38.842367 TX Vref early break, caculate TX vref
8901 23:42:38.845768 TX Vref=16, minBit 9, minWin=22, winSum=379
8902 23:42:38.848854 TX Vref=18, minBit 9, minWin=22, winSum=393
8903 23:42:38.852018 TX Vref=20, minBit 9, minWin=23, winSum=395
8904 23:42:38.855337 TX Vref=22, minBit 9, minWin=24, winSum=403
8905 23:42:38.858478 TX Vref=24, minBit 9, minWin=24, winSum=414
8906 23:42:38.865196 TX Vref=26, minBit 9, minWin=24, winSum=417
8907 23:42:38.868705 TX Vref=28, minBit 9, minWin=24, winSum=420
8908 23:42:38.871701 TX Vref=30, minBit 8, minWin=25, winSum=419
8909 23:42:38.875187 TX Vref=32, minBit 0, minWin=25, winSum=411
8910 23:42:38.878371 TX Vref=34, minBit 8, minWin=23, winSum=402
8911 23:42:38.884914 TX Vref=36, minBit 9, minWin=23, winSum=397
8912 23:42:38.888601 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 30
8913 23:42:38.888709
8914 23:42:38.891529 Final TX Range 0 Vref 30
8915 23:42:38.891640
8916 23:42:38.891733 ==
8917 23:42:38.894981 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 23:42:38.898285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 23:42:38.901735 ==
8920 23:42:38.901838
8921 23:42:38.901938
8922 23:42:38.902026 TX Vref Scan disable
8923 23:42:38.908186 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8924 23:42:38.908302 == TX Byte 0 ==
8925 23:42:38.911932 u2DelayCellOfst[0]=17 cells (5 PI)
8926 23:42:38.914993 u2DelayCellOfst[1]=10 cells (3 PI)
8927 23:42:38.918030 u2DelayCellOfst[2]=0 cells (0 PI)
8928 23:42:38.921383 u2DelayCellOfst[3]=7 cells (2 PI)
8929 23:42:38.924501 u2DelayCellOfst[4]=10 cells (3 PI)
8930 23:42:38.927917 u2DelayCellOfst[5]=17 cells (5 PI)
8931 23:42:38.931111 u2DelayCellOfst[6]=14 cells (4 PI)
8932 23:42:38.934413 u2DelayCellOfst[7]=3 cells (1 PI)
8933 23:42:38.937978 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8934 23:42:38.941178 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8935 23:42:38.944930 == TX Byte 1 ==
8936 23:42:38.948362 u2DelayCellOfst[8]=0 cells (0 PI)
8937 23:42:38.951188 u2DelayCellOfst[9]=3 cells (1 PI)
8938 23:42:38.954602 u2DelayCellOfst[10]=10 cells (3 PI)
8939 23:42:38.957844 u2DelayCellOfst[11]=3 cells (1 PI)
8940 23:42:38.961084 u2DelayCellOfst[12]=14 cells (4 PI)
8941 23:42:38.964609 u2DelayCellOfst[13]=14 cells (4 PI)
8942 23:42:38.967646 u2DelayCellOfst[14]=17 cells (5 PI)
8943 23:42:38.967722 u2DelayCellOfst[15]=17 cells (5 PI)
8944 23:42:38.974277 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8945 23:42:38.977634 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8946 23:42:38.981127 DramC Write-DBI on
8947 23:42:38.981212 ==
8948 23:42:38.984262 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 23:42:38.987562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 23:42:38.987656 ==
8951 23:42:38.987739
8952 23:42:38.987817
8953 23:42:38.991003 TX Vref Scan disable
8954 23:42:38.991149 == TX Byte 0 ==
8955 23:42:38.997470 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8956 23:42:38.997561 == TX Byte 1 ==
8957 23:42:39.001063 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8958 23:42:39.004340 DramC Write-DBI off
8959 23:42:39.004423
8960 23:42:39.004505 [DATLAT]
8961 23:42:39.007859 Freq=1600, CH1 RK1
8962 23:42:39.007944
8963 23:42:39.008027 DATLAT Default: 0xf
8964 23:42:39.010919 0, 0xFFFF, sum = 0
8965 23:42:39.011003 1, 0xFFFF, sum = 0
8966 23:42:39.014314 2, 0xFFFF, sum = 0
8967 23:42:39.014398 3, 0xFFFF, sum = 0
8968 23:42:39.017782 4, 0xFFFF, sum = 0
8969 23:42:39.017895 5, 0xFFFF, sum = 0
8970 23:42:39.021087 6, 0xFFFF, sum = 0
8971 23:42:39.024125 7, 0xFFFF, sum = 0
8972 23:42:39.024251 8, 0xFFFF, sum = 0
8973 23:42:39.027321 9, 0xFFFF, sum = 0
8974 23:42:39.027405 10, 0xFFFF, sum = 0
8975 23:42:39.030489 11, 0xFFFF, sum = 0
8976 23:42:39.030573 12, 0xFFFF, sum = 0
8977 23:42:39.033676 13, 0xFFFF, sum = 0
8978 23:42:39.033760 14, 0x0, sum = 1
8979 23:42:39.037076 15, 0x0, sum = 2
8980 23:42:39.037160 16, 0x0, sum = 3
8981 23:42:39.040464 17, 0x0, sum = 4
8982 23:42:39.040554 best_step = 15
8983 23:42:39.040694
8984 23:42:39.040818 ==
8985 23:42:39.043708 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 23:42:39.050267 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 23:42:39.050352 ==
8988 23:42:39.050434 RX Vref Scan: 0
8989 23:42:39.050561
8990 23:42:39.053271 RX Vref 0 -> 0, step: 1
8991 23:42:39.053387
8992 23:42:39.056813 RX Delay 11 -> 252, step: 4
8993 23:42:39.059840 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8994 23:42:39.063257 iDelay=195, Bit 1, Center 128 (75 ~ 182) 108
8995 23:42:39.066445 iDelay=195, Bit 2, Center 118 (63 ~ 174) 112
8996 23:42:39.073372 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8997 23:42:39.076583 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8998 23:42:39.080035 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8999 23:42:39.083046 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9000 23:42:39.086464 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9001 23:42:39.092889 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9002 23:42:39.096498 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9003 23:42:39.099375 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9004 23:42:39.102969 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9005 23:42:39.109761 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9006 23:42:39.112896 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9007 23:42:39.116123 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9008 23:42:39.119589 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9009 23:42:39.119675 ==
9010 23:42:39.122712 Dram Type= 6, Freq= 0, CH_1, rank 1
9011 23:42:39.129139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9012 23:42:39.129268 ==
9013 23:42:39.129345 DQS Delay:
9014 23:42:39.132767 DQS0 = 0, DQS1 = 0
9015 23:42:39.132849 DQM Delay:
9016 23:42:39.132931 DQM0 = 130, DQM1 = 127
9017 23:42:39.135521 DQ Delay:
9018 23:42:39.138895 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =128
9019 23:42:39.142202 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =128
9020 23:42:39.145646 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
9021 23:42:39.148652 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =136
9022 23:42:39.148726
9023 23:42:39.148787
9024 23:42:39.148845
9025 23:42:39.152145 [DramC_TX_OE_Calibration] TA2
9026 23:42:39.155732 Original DQ_B0 (3 6) =30, OEN = 27
9027 23:42:39.158527 Original DQ_B1 (3 6) =30, OEN = 27
9028 23:42:39.162039 24, 0x0, End_B0=24 End_B1=24
9029 23:42:39.165785 25, 0x0, End_B0=25 End_B1=25
9030 23:42:39.165866 26, 0x0, End_B0=26 End_B1=26
9031 23:42:39.168381 27, 0x0, End_B0=27 End_B1=27
9032 23:42:39.171669 28, 0x0, End_B0=28 End_B1=28
9033 23:42:39.175076 29, 0x0, End_B0=29 End_B1=29
9034 23:42:39.178117 30, 0x0, End_B0=30 End_B1=30
9035 23:42:39.178243 31, 0x5151, End_B0=30 End_B1=30
9036 23:42:39.181354 Byte0 end_step=30 best_step=27
9037 23:42:39.184753 Byte1 end_step=30 best_step=27
9038 23:42:39.188195 Byte0 TX OE(2T, 0.5T) = (3, 3)
9039 23:42:39.191363 Byte1 TX OE(2T, 0.5T) = (3, 3)
9040 23:42:39.191451
9041 23:42:39.191515
9042 23:42:39.198550 [DQSOSCAuto] RK1, (LSB)MR18= 0x111f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9043 23:42:39.201659 CH1 RK1: MR19=303, MR18=111F
9044 23:42:39.208120 CH1_RK1: MR19=0x303, MR18=0x111F, DQSOSC=394, MR23=63, INC=23, DEC=15
9045 23:42:39.211506 [RxdqsGatingPostProcess] freq 1600
9046 23:42:39.217907 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9047 23:42:39.217996 best DQS0 dly(2T, 0.5T) = (1, 1)
9048 23:42:39.221574 best DQS1 dly(2T, 0.5T) = (1, 1)
9049 23:42:39.224320 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9050 23:42:39.227713 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9051 23:42:39.231284 best DQS0 dly(2T, 0.5T) = (1, 1)
9052 23:42:39.234325 best DQS1 dly(2T, 0.5T) = (1, 1)
9053 23:42:39.237783 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9054 23:42:39.240870 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9055 23:42:39.244293 Pre-setting of DQS Precalculation
9056 23:42:39.247844 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9057 23:42:39.257613 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9058 23:42:39.263992 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9059 23:42:39.264076
9060 23:42:39.264142
9061 23:42:39.267395 [Calibration Summary] 3200 Mbps
9062 23:42:39.267478 CH 0, Rank 0
9063 23:42:39.270448 SW Impedance : PASS
9064 23:42:39.273618 DUTY Scan : NO K
9065 23:42:39.273701 ZQ Calibration : PASS
9066 23:42:39.277242 Jitter Meter : NO K
9067 23:42:39.277325 CBT Training : PASS
9068 23:42:39.280439 Write leveling : PASS
9069 23:42:39.283674 RX DQS gating : PASS
9070 23:42:39.283748 RX DQ/DQS(RDDQC) : PASS
9071 23:42:39.287129 TX DQ/DQS : PASS
9072 23:42:39.290457 RX DATLAT : PASS
9073 23:42:39.290533 RX DQ/DQS(Engine): PASS
9074 23:42:39.293339 TX OE : PASS
9075 23:42:39.293414 All Pass.
9076 23:42:39.293476
9077 23:42:39.296748 CH 0, Rank 1
9078 23:42:39.296820 SW Impedance : PASS
9079 23:42:39.300201 DUTY Scan : NO K
9080 23:42:39.303612 ZQ Calibration : PASS
9081 23:42:39.303696 Jitter Meter : NO K
9082 23:42:39.306604 CBT Training : PASS
9083 23:42:39.309783 Write leveling : PASS
9084 23:42:39.309866 RX DQS gating : PASS
9085 23:42:39.313292 RX DQ/DQS(RDDQC) : PASS
9086 23:42:39.316412 TX DQ/DQS : PASS
9087 23:42:39.316495 RX DATLAT : PASS
9088 23:42:39.319794 RX DQ/DQS(Engine): PASS
9089 23:42:39.323188 TX OE : PASS
9090 23:42:39.323271 All Pass.
9091 23:42:39.323336
9092 23:42:39.323396 CH 1, Rank 0
9093 23:42:39.326483 SW Impedance : PASS
9094 23:42:39.329982 DUTY Scan : NO K
9095 23:42:39.330065 ZQ Calibration : PASS
9096 23:42:39.333254 Jitter Meter : NO K
9097 23:42:39.336204 CBT Training : PASS
9098 23:42:39.336286 Write leveling : PASS
9099 23:42:39.339767 RX DQS gating : PASS
9100 23:42:39.342662 RX DQ/DQS(RDDQC) : PASS
9101 23:42:39.342745 TX DQ/DQS : PASS
9102 23:42:39.346197 RX DATLAT : PASS
9103 23:42:39.349613 RX DQ/DQS(Engine): PASS
9104 23:42:39.349696 TX OE : PASS
9105 23:42:39.349762 All Pass.
9106 23:42:39.353015
9107 23:42:39.353123 CH 1, Rank 1
9108 23:42:39.356045 SW Impedance : PASS
9109 23:42:39.356144 DUTY Scan : NO K
9110 23:42:39.359331 ZQ Calibration : PASS
9111 23:42:39.362881 Jitter Meter : NO K
9112 23:42:39.362957 CBT Training : PASS
9113 23:42:39.366208 Write leveling : PASS
9114 23:42:39.366278 RX DQS gating : PASS
9115 23:42:39.369578 RX DQ/DQS(RDDQC) : PASS
9116 23:42:39.372661 TX DQ/DQS : PASS
9117 23:42:39.372730 RX DATLAT : PASS
9118 23:42:39.376106 RX DQ/DQS(Engine): PASS
9119 23:42:39.379104 TX OE : PASS
9120 23:42:39.379174 All Pass.
9121 23:42:39.379233
9122 23:42:39.382315 DramC Write-DBI on
9123 23:42:39.382383 PER_BANK_REFRESH: Hybrid Mode
9124 23:42:39.385459 TX_TRACKING: ON
9125 23:42:39.395820 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9126 23:42:39.402249 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9127 23:42:39.409094 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9128 23:42:39.411802 [FAST_K] Save calibration result to emmc
9129 23:42:39.415674 sync common calibartion params.
9130 23:42:39.418490 sync cbt_mode0:1, 1:1
9131 23:42:39.421935 dram_init: ddr_geometry: 2
9132 23:42:39.422044 dram_init: ddr_geometry: 2
9133 23:42:39.425434 dram_init: ddr_geometry: 2
9134 23:42:39.428518 0:dram_rank_size:100000000
9135 23:42:39.428602 1:dram_rank_size:100000000
9136 23:42:39.435335 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9137 23:42:39.438413 DFS_SHUFFLE_HW_MODE: ON
9138 23:42:39.441585 dramc_set_vcore_voltage set vcore to 725000
9139 23:42:39.445109 Read voltage for 1600, 0
9140 23:42:39.445189 Vio18 = 0
9141 23:42:39.445254 Vcore = 725000
9142 23:42:39.448509 Vdram = 0
9143 23:42:39.448578 Vddq = 0
9144 23:42:39.448637 Vmddr = 0
9145 23:42:39.451401 switch to 3200 Mbps bootup
9146 23:42:39.454966 [DramcRunTimeConfig]
9147 23:42:39.455052 PHYPLL
9148 23:42:39.455119 DPM_CONTROL_AFTERK: ON
9149 23:42:39.458208 PER_BANK_REFRESH: ON
9150 23:42:39.461446 REFRESH_OVERHEAD_REDUCTION: ON
9151 23:42:39.461529 CMD_PICG_NEW_MODE: OFF
9152 23:42:39.464573 XRTWTW_NEW_MODE: ON
9153 23:42:39.468162 XRTRTR_NEW_MODE: ON
9154 23:42:39.468246 TX_TRACKING: ON
9155 23:42:39.471110 RDSEL_TRACKING: OFF
9156 23:42:39.471193 DQS Precalculation for DVFS: ON
9157 23:42:39.474544 RX_TRACKING: OFF
9158 23:42:39.474627 HW_GATING DBG: ON
9159 23:42:39.477907 ZQCS_ENABLE_LP4: ON
9160 23:42:39.480958 RX_PICG_NEW_MODE: ON
9161 23:42:39.481042 TX_PICG_NEW_MODE: ON
9162 23:42:39.484368 ENABLE_RX_DCM_DPHY: ON
9163 23:42:39.487418 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9164 23:42:39.487491 DUMMY_READ_FOR_TRACKING: OFF
9165 23:42:39.490869 !!! SPM_CONTROL_AFTERK: OFF
9166 23:42:39.494380 !!! SPM could not control APHY
9167 23:42:39.497359 IMPEDANCE_TRACKING: ON
9168 23:42:39.497492 TEMP_SENSOR: ON
9169 23:42:39.500519 HW_SAVE_FOR_SR: OFF
9170 23:42:39.503850 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9171 23:42:39.507404 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9172 23:42:39.507515 Read ODT Tracking: ON
9173 23:42:39.510755 Refresh Rate DeBounce: ON
9174 23:42:39.514363 DFS_NO_QUEUE_FLUSH: ON
9175 23:42:39.517168 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9176 23:42:39.517282 ENABLE_DFS_RUNTIME_MRW: OFF
9177 23:42:39.520292 DDR_RESERVE_NEW_MODE: ON
9178 23:42:39.523709 MR_CBT_SWITCH_FREQ: ON
9179 23:42:39.523826 =========================
9180 23:42:39.543858 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9181 23:42:39.547013 dram_init: ddr_geometry: 2
9182 23:42:39.565266 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9183 23:42:39.568522 dram_init: dram init end (result: 0)
9184 23:42:39.575390 DRAM-K: Full calibration passed in 24428 msecs
9185 23:42:39.578194 MRC: failed to locate region type 0.
9186 23:42:39.578277 DRAM rank0 size:0x100000000,
9187 23:42:39.581526 DRAM rank1 size=0x100000000
9188 23:42:39.591496 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9189 23:42:39.598437 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9190 23:42:39.604677 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9191 23:42:39.614822 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9192 23:42:39.614919 DRAM rank0 size:0x100000000,
9193 23:42:39.618043 DRAM rank1 size=0x100000000
9194 23:42:39.618126 CBMEM:
9195 23:42:39.621080 IMD: root @ 0xfffff000 254 entries.
9196 23:42:39.624505 IMD: root @ 0xffffec00 62 entries.
9197 23:42:39.627916 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9198 23:42:39.634219 WARNING: RO_VPD is uninitialized or empty.
9199 23:42:39.637781 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9200 23:42:39.645401 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9201 23:42:39.657999 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9202 23:42:39.669388 BS: romstage times (exec / console): total (unknown) / 23957 ms
9203 23:42:39.669473
9204 23:42:39.669538
9205 23:42:39.679460 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9206 23:42:39.682443 ARM64: Exception handlers installed.
9207 23:42:39.685963 ARM64: Testing exception
9208 23:42:39.689466 ARM64: Done test exception
9209 23:42:39.689541 Enumerating buses...
9210 23:42:39.692325 Show all devs... Before device enumeration.
9211 23:42:39.695612 Root Device: enabled 1
9212 23:42:39.699400 CPU_CLUSTER: 0: enabled 1
9213 23:42:39.699473 CPU: 00: enabled 1
9214 23:42:39.702151 Compare with tree...
9215 23:42:39.702226 Root Device: enabled 1
9216 23:42:39.705583 CPU_CLUSTER: 0: enabled 1
9217 23:42:39.709064 CPU: 00: enabled 1
9218 23:42:39.709146 Root Device scanning...
9219 23:42:39.712146 scan_static_bus for Root Device
9220 23:42:39.715384 CPU_CLUSTER: 0 enabled
9221 23:42:39.718694 scan_static_bus for Root Device done
9222 23:42:39.721865 scan_bus: bus Root Device finished in 8 msecs
9223 23:42:39.721947 done
9224 23:42:39.728415 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9225 23:42:39.732058 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9226 23:42:39.738266 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9227 23:42:39.745203 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9228 23:42:39.745308 Allocating resources...
9229 23:42:39.748158 Reading resources...
9230 23:42:39.751776 Root Device read_resources bus 0 link: 0
9231 23:42:39.755205 DRAM rank0 size:0x100000000,
9232 23:42:39.755287 DRAM rank1 size=0x100000000
9233 23:42:39.761761 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9234 23:42:39.761845 CPU: 00 missing read_resources
9235 23:42:39.768719 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9236 23:42:39.771419 Root Device read_resources bus 0 link: 0 done
9237 23:42:39.774840 Done reading resources.
9238 23:42:39.778141 Show resources in subtree (Root Device)...After reading.
9239 23:42:39.781550 Root Device child on link 0 CPU_CLUSTER: 0
9240 23:42:39.784740 CPU_CLUSTER: 0 child on link 0 CPU: 00
9241 23:42:39.794908 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9242 23:42:39.795023 CPU: 00
9243 23:42:39.801076 Root Device assign_resources, bus 0 link: 0
9244 23:42:39.805029 CPU_CLUSTER: 0 missing set_resources
9245 23:42:39.808071 Root Device assign_resources, bus 0 link: 0 done
9246 23:42:39.811104 Done setting resources.
9247 23:42:39.814081 Show resources in subtree (Root Device)...After assigning values.
9248 23:42:39.817362 Root Device child on link 0 CPU_CLUSTER: 0
9249 23:42:39.824398 CPU_CLUSTER: 0 child on link 0 CPU: 00
9250 23:42:39.831075 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9251 23:42:39.834008 CPU: 00
9252 23:42:39.834091 Done allocating resources.
9253 23:42:39.841111 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9254 23:42:39.841217 Enabling resources...
9255 23:42:39.844235 done.
9256 23:42:39.847260 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9257 23:42:39.850747 Initializing devices...
9258 23:42:39.850851 Root Device init
9259 23:42:39.854276 init hardware done!
9260 23:42:39.854381 0x00000018: ctrlr->caps
9261 23:42:39.857115 52.000 MHz: ctrlr->f_max
9262 23:42:39.860680 0.400 MHz: ctrlr->f_min
9263 23:42:39.863706 0x40ff8080: ctrlr->voltages
9264 23:42:39.863783 sclk: 390625
9265 23:42:39.863884 Bus Width = 1
9266 23:42:39.866845 sclk: 390625
9267 23:42:39.866944 Bus Width = 1
9268 23:42:39.870177 Early init status = 3
9269 23:42:39.873509 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9270 23:42:39.877146 in-header: 03 fc 00 00 01 00 00 00
9271 23:42:39.880512 in-data: 00
9272 23:42:39.883448 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9273 23:42:39.888139 in-header: 03 fd 00 00 00 00 00 00
9274 23:42:39.891985 in-data:
9275 23:42:39.894962 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9276 23:42:39.898245 in-header: 03 fc 00 00 01 00 00 00
9277 23:42:39.901684 in-data: 00
9278 23:42:39.904609 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9279 23:42:39.909541 in-header: 03 fd 00 00 00 00 00 00
9280 23:42:39.913925 in-data:
9281 23:42:39.916130 [SSUSB] Setting up USB HOST controller...
9282 23:42:39.919506 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9283 23:42:39.923172 [SSUSB] phy power-on done.
9284 23:42:39.926419 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9285 23:42:39.932779 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9286 23:42:39.936340 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9287 23:42:39.942681 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9288 23:42:39.949353 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9289 23:42:39.956028 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9290 23:42:39.962548 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9291 23:42:39.969025 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9292 23:42:39.972350 SPM: binary array size = 0x9dc
9293 23:42:39.975683 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9294 23:42:39.982257 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9295 23:42:39.988547 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9296 23:42:39.994991 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9297 23:42:39.998662 configure_display: Starting display init
9298 23:42:40.032914 anx7625_power_on_init: Init interface.
9299 23:42:40.035979 anx7625_disable_pd_protocol: Disabled PD feature.
9300 23:42:40.039745 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9301 23:42:40.067480 anx7625_start_dp_work: Secure OCM version=00
9302 23:42:40.070437 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9303 23:42:40.085675 sp_tx_get_edid_block: EDID Block = 1
9304 23:42:40.188431 Extracted contents:
9305 23:42:40.191144 header: 00 ff ff ff ff ff ff 00
9306 23:42:40.194812 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9307 23:42:40.197788 version: 01 04
9308 23:42:40.201275 basic params: 95 1f 11 78 0a
9309 23:42:40.204307 chroma info: 76 90 94 55 54 90 27 21 50 54
9310 23:42:40.207526 established: 00 00 00
9311 23:42:40.214072 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9312 23:42:40.220547 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9313 23:42:40.224154 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9314 23:42:40.230778 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9315 23:42:40.237372 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9316 23:42:40.240926 extensions: 00
9317 23:42:40.241033 checksum: fb
9318 23:42:40.241133
9319 23:42:40.247163 Manufacturer: IVO Model 57d Serial Number 0
9320 23:42:40.247274 Made week 0 of 2020
9321 23:42:40.250792 EDID version: 1.4
9322 23:42:40.250873 Digital display
9323 23:42:40.253545 6 bits per primary color channel
9324 23:42:40.257522 DisplayPort interface
9325 23:42:40.257619 Maximum image size: 31 cm x 17 cm
9326 23:42:40.260866 Gamma: 220%
9327 23:42:40.260979 Check DPMS levels
9328 23:42:40.267225 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9329 23:42:40.270302 First detailed timing is preferred timing
9330 23:42:40.273346 Established timings supported:
9331 23:42:40.273428 Standard timings supported:
9332 23:42:40.276713 Detailed timings
9333 23:42:40.279875 Hex of detail: 383680a07038204018303c0035ae10000019
9334 23:42:40.286469 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9335 23:42:40.290075 0780 0798 07c8 0820 hborder 0
9336 23:42:40.293021 0438 043b 0447 0458 vborder 0
9337 23:42:40.296404 -hsync -vsync
9338 23:42:40.296488 Did detailed timing
9339 23:42:40.303355 Hex of detail: 000000000000000000000000000000000000
9340 23:42:40.306745 Manufacturer-specified data, tag 0
9341 23:42:40.309485 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9342 23:42:40.313058 ASCII string: InfoVision
9343 23:42:40.316169 Hex of detail: 000000fe00523134304e574635205248200a
9344 23:42:40.319612 ASCII string: R140NWF5 RH
9345 23:42:40.319724 Checksum
9346 23:42:40.322603 Checksum: 0xfb (valid)
9347 23:42:40.326086 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9348 23:42:40.329550 DSI data_rate: 832800000 bps
9349 23:42:40.335813 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9350 23:42:40.339456 anx7625_parse_edid: pixelclock(138800).
9351 23:42:40.342875 hactive(1920), hsync(48), hfp(24), hbp(88)
9352 23:42:40.345830 vactive(1080), vsync(12), vfp(3), vbp(17)
9353 23:42:40.348975 anx7625_dsi_config: config dsi.
9354 23:42:40.356178 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9355 23:42:40.369993 anx7625_dsi_config: success to config DSI
9356 23:42:40.373340 anx7625_dp_start: MIPI phy setup OK.
9357 23:42:40.376700 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9358 23:42:40.380104 mtk_ddp_mode_set invalid vrefresh 60
9359 23:42:40.383359 main_disp_path_setup
9360 23:42:40.383460 ovl_layer_smi_id_en
9361 23:42:40.386652 ovl_layer_smi_id_en
9362 23:42:40.386757 ccorr_config
9363 23:42:40.386822 aal_config
9364 23:42:40.389983 gamma_config
9365 23:42:40.390090 postmask_config
9366 23:42:40.393062 dither_config
9367 23:42:40.396333 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9368 23:42:40.403039 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9369 23:42:40.406100 Root Device init finished in 551 msecs
9370 23:42:40.409440 CPU_CLUSTER: 0 init
9371 23:42:40.416600 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9372 23:42:40.422881 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9373 23:42:40.422968 APU_MBOX 0x190000b0 = 0x10001
9374 23:42:40.426375 APU_MBOX 0x190001b0 = 0x10001
9375 23:42:40.429230 APU_MBOX 0x190005b0 = 0x10001
9376 23:42:40.432644 APU_MBOX 0x190006b0 = 0x10001
9377 23:42:40.439520 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9378 23:42:40.449291 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9379 23:42:40.461452 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9380 23:42:40.467884 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9381 23:42:40.479950 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9382 23:42:40.488789 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9383 23:42:40.491892 CPU_CLUSTER: 0 init finished in 81 msecs
9384 23:42:40.495483 Devices initialized
9385 23:42:40.498533 Show all devs... After init.
9386 23:42:40.498615 Root Device: enabled 1
9387 23:42:40.502179 CPU_CLUSTER: 0: enabled 1
9388 23:42:40.505061 CPU: 00: enabled 1
9389 23:42:40.508616 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9390 23:42:40.511877 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9391 23:42:40.515025 ELOG: NV offset 0x57f000 size 0x1000
9392 23:42:40.521678 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9393 23:42:40.528288 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9394 23:42:40.531882 ELOG: Event(17) added with size 13 at 2024-06-04 23:42:40 UTC
9395 23:42:40.538832 out: cmd=0x121: 03 db 21 01 00 00 00 00
9396 23:42:40.542105 in-header: 03 eb 00 00 2c 00 00 00
9397 23:42:40.551659 in-data: 52 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9398 23:42:40.558021 ELOG: Event(A1) added with size 10 at 2024-06-04 23:42:40 UTC
9399 23:42:40.564985 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9400 23:42:40.571341 ELOG: Event(A0) added with size 9 at 2024-06-04 23:42:40 UTC
9401 23:42:40.574839 elog_add_boot_reason: Logged dev mode boot
9402 23:42:40.581184 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9403 23:42:40.581308 Finalize devices...
9404 23:42:40.584600 Devices finalized
9405 23:42:40.587628 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9406 23:42:40.591115 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9407 23:42:40.594562 in-header: 03 07 00 00 08 00 00 00
9408 23:42:40.597571 in-data: aa e4 47 04 13 02 00 00
9409 23:42:40.600853 Chrome EC: UHEPI supported
9410 23:42:40.607477 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9411 23:42:40.611165 in-header: 03 a9 00 00 08 00 00 00
9412 23:42:40.614423 in-data: 84 60 60 08 00 00 00 00
9413 23:42:40.620635 ELOG: Event(91) added with size 10 at 2024-06-04 23:42:40 UTC
9414 23:42:40.624438 Chrome EC: clear events_b mask to 0x0000000020004000
9415 23:42:40.630534 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9416 23:42:40.635046 in-header: 03 fd 00 00 00 00 00 00
9417 23:42:40.638096 in-data:
9418 23:42:40.641467 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9419 23:42:40.644909 Writing coreboot table at 0xffe64000
9420 23:42:40.651777 0. 000000000010a000-0000000000113fff: RAMSTAGE
9421 23:42:40.654766 1. 0000000040000000-00000000400fffff: RAM
9422 23:42:40.658139 2. 0000000040100000-000000004032afff: RAMSTAGE
9423 23:42:40.661081 3. 000000004032b000-00000000545fffff: RAM
9424 23:42:40.664445 4. 0000000054600000-000000005465ffff: BL31
9425 23:42:40.667722 5. 0000000054660000-00000000ffe63fff: RAM
9426 23:42:40.674644 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9427 23:42:40.678267 7. 0000000100000000-000000023fffffff: RAM
9428 23:42:40.681113 Passing 5 GPIOs to payload:
9429 23:42:40.684575 NAME | PORT | POLARITY | VALUE
9430 23:42:40.691666 EC in RW | 0x000000aa | low | undefined
9431 23:42:40.694583 EC interrupt | 0x00000005 | low | undefined
9432 23:42:40.700981 TPM interrupt | 0x000000ab | high | undefined
9433 23:42:40.704622 SD card detect | 0x00000011 | high | undefined
9434 23:42:40.707557 speaker enable | 0x00000093 | high | undefined
9435 23:42:40.711134 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9436 23:42:40.714904 in-header: 03 f9 00 00 02 00 00 00
9437 23:42:40.718060 in-data: 02 00
9438 23:42:40.721131 ADC[4]: Raw value=901847 ID=7
9439 23:42:40.724389 ADC[3]: Raw value=213177 ID=1
9440 23:42:40.724464 RAM Code: 0x71
9441 23:42:40.727882 ADC[6]: Raw value=75000 ID=0
9442 23:42:40.731382 ADC[5]: Raw value=213546 ID=1
9443 23:42:40.731464 SKU Code: 0x1
9444 23:42:40.737515 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b970
9445 23:42:40.737640 coreboot table: 964 bytes.
9446 23:42:40.740857 IMD ROOT 0. 0xfffff000 0x00001000
9447 23:42:40.744142 IMD SMALL 1. 0xffffe000 0x00001000
9448 23:42:40.747558 RO MCACHE 2. 0xffffc000 0x00001104
9449 23:42:40.750735 CONSOLE 3. 0xfff7c000 0x00080000
9450 23:42:40.753967 FMAP 4. 0xfff7b000 0x00000452
9451 23:42:40.757705 TIME STAMP 5. 0xfff7a000 0x00000910
9452 23:42:40.760970 VBOOT WORK 6. 0xfff66000 0x00014000
9453 23:42:40.764496 RAMOOPS 7. 0xffe66000 0x00100000
9454 23:42:40.767049 COREBOOT 8. 0xffe64000 0x00002000
9455 23:42:40.770535 IMD small region:
9456 23:42:40.773665 IMD ROOT 0. 0xffffec00 0x00000400
9457 23:42:40.777125 VPD 1. 0xffffeb80 0x0000006c
9458 23:42:40.780362 MMC STATUS 2. 0xffffeb60 0x00000004
9459 23:42:40.787103 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9460 23:42:40.793546 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9461 23:42:40.832187 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9462 23:42:40.835701 Checking segment from ROM address 0x40100000
9463 23:42:40.838769 Checking segment from ROM address 0x4010001c
9464 23:42:40.845839 Loading segment from ROM address 0x40100000
9465 23:42:40.845922 code (compression=0)
9466 23:42:40.855248 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9467 23:42:40.862280 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9468 23:42:40.862360 it's not compressed!
9469 23:42:40.868567 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9470 23:42:40.875394 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9471 23:42:40.892215 Loading segment from ROM address 0x4010001c
9472 23:42:40.892302 Entry Point 0x80000000
9473 23:42:40.895886 Loaded segments
9474 23:42:40.899035 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9475 23:42:40.905661 Jumping to boot code at 0x80000000(0xffe64000)
9476 23:42:40.912227 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9477 23:42:40.918585 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9478 23:42:40.927032 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9479 23:42:40.929945 Checking segment from ROM address 0x40100000
9480 23:42:40.933557 Checking segment from ROM address 0x4010001c
9481 23:42:40.940398 Loading segment from ROM address 0x40100000
9482 23:42:40.940480 code (compression=1)
9483 23:42:40.946514 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9484 23:42:40.956459 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9485 23:42:40.956539 using LZMA
9486 23:42:40.965450 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9487 23:42:40.972118 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9488 23:42:40.974875 Loading segment from ROM address 0x4010001c
9489 23:42:40.978175 Entry Point 0x54601000
9490 23:42:40.978279 Loaded segments
9491 23:42:40.981569 NOTICE: MT8192 bl31_setup
9492 23:42:40.988660 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9493 23:42:40.992235 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9494 23:42:40.995540 WARNING: region 0:
9495 23:42:40.999078 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9496 23:42:40.999185 WARNING: region 1:
9497 23:42:41.005326 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9498 23:42:41.008521 WARNING: region 2:
9499 23:42:41.011974 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9500 23:42:41.015394 WARNING: region 3:
9501 23:42:41.021760 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9502 23:42:41.021842 WARNING: region 4:
9503 23:42:41.028552 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9504 23:42:41.028633 WARNING: region 5:
9505 23:42:41.031825 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 23:42:41.035408 WARNING: region 6:
9507 23:42:41.038222 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 23:42:41.041697 WARNING: region 7:
9509 23:42:41.044423 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9510 23:42:41.051249 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9511 23:42:41.054672 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9512 23:42:41.061150 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9513 23:42:41.064579 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9514 23:42:41.068144 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9515 23:42:41.074569 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9516 23:42:41.078252 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9517 23:42:41.080896 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9518 23:42:41.087590 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9519 23:42:41.091180 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9520 23:42:41.097490 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9521 23:42:41.101065 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9522 23:42:41.104474 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9523 23:42:41.110765 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9524 23:42:41.114303 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9525 23:42:41.117275 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9526 23:42:41.124135 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9527 23:42:41.127815 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9528 23:42:41.133849 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9529 23:42:41.137326 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9530 23:42:41.140896 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9531 23:42:41.147415 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9532 23:42:41.150501 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9533 23:42:41.157170 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9534 23:42:41.160215 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9535 23:42:41.164189 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9536 23:42:41.170543 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9537 23:42:41.173506 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9538 23:42:41.180321 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9539 23:42:41.184132 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9540 23:42:41.189804 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9541 23:42:41.193241 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9542 23:42:41.196771 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9543 23:42:41.200087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9544 23:42:41.206659 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9545 23:42:41.209561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9546 23:42:41.212847 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9547 23:42:41.219515 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9548 23:42:41.223258 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9549 23:42:41.226558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9550 23:42:41.229306 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9551 23:42:41.236106 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9552 23:42:41.239327 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9553 23:42:41.242748 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9554 23:42:41.245850 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9555 23:42:41.252354 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9556 23:42:41.255770 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9557 23:42:41.259026 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9558 23:42:41.266055 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9559 23:42:41.268920 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9560 23:42:41.275862 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9561 23:42:41.278670 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9562 23:42:41.282121 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9563 23:42:41.288968 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9564 23:42:41.291940 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9565 23:42:41.298907 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9566 23:42:41.302369 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9567 23:42:41.308712 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9568 23:42:41.311755 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9569 23:42:41.318502 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9570 23:42:41.321589 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9571 23:42:41.325039 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9572 23:42:41.331691 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9573 23:42:41.335168 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9574 23:42:41.341894 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9575 23:42:41.345336 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9576 23:42:41.351220 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9577 23:42:41.354868 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9578 23:42:41.361569 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9579 23:42:41.364729 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9580 23:42:41.367815 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9581 23:42:41.374546 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9582 23:42:41.377691 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9583 23:42:41.384311 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9584 23:42:41.387554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9585 23:42:41.394046 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9586 23:42:41.397334 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9587 23:42:41.403967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9588 23:42:41.407497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9589 23:42:41.414136 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9590 23:42:41.417125 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9591 23:42:41.420502 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9592 23:42:41.427077 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9593 23:42:41.430232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9594 23:42:41.436771 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9595 23:42:41.440339 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9596 23:42:41.446862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9597 23:42:41.450293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9598 23:42:41.456573 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9599 23:42:41.460528 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9600 23:42:41.463139 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9601 23:42:41.469747 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9602 23:42:41.472985 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9603 23:42:41.479845 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9604 23:42:41.482886 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9605 23:42:41.489629 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9606 23:42:41.493245 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9607 23:42:41.496451 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9608 23:42:41.503234 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9609 23:42:41.506291 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9610 23:42:41.509569 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9611 23:42:41.512879 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9612 23:42:41.519735 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9613 23:42:41.522609 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9614 23:42:41.529614 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9615 23:42:41.532463 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9616 23:42:41.539159 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9617 23:42:41.542274 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9618 23:42:41.545696 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9619 23:42:41.552371 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9620 23:42:41.555880 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9621 23:42:41.562159 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9622 23:42:41.565727 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9623 23:42:41.569133 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9624 23:42:41.575540 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9625 23:42:41.578917 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9626 23:42:41.581734 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9627 23:42:41.588944 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9628 23:42:41.591927 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9629 23:42:41.595200 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9630 23:42:41.601680 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9631 23:42:41.605227 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9632 23:42:41.608069 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9633 23:42:41.611664 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9634 23:42:41.618009 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9635 23:42:41.621752 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9636 23:42:41.628170 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9637 23:42:41.631265 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9638 23:42:41.637697 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9639 23:42:41.641100 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9640 23:42:41.644480 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9641 23:42:41.651295 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9642 23:42:41.654592 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9643 23:42:41.660885 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9644 23:42:41.664339 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9645 23:42:41.667526 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9646 23:42:41.674359 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9647 23:42:41.677457 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9648 23:42:41.683979 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9649 23:42:41.687763 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9650 23:42:41.690432 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9651 23:42:41.697186 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9652 23:42:41.700745 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9653 23:42:41.707166 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9654 23:42:41.710346 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9655 23:42:41.713681 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9656 23:42:41.720238 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9657 23:42:41.723646 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9658 23:42:41.730204 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9659 23:42:41.733749 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9660 23:42:41.736945 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9661 23:42:41.743323 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9662 23:42:41.746827 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9663 23:42:41.753170 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9664 23:42:41.756428 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9665 23:42:41.761934 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9666 23:42:41.766535 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9667 23:42:41.770018 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9668 23:42:41.772827 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9669 23:42:41.780219 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9670 23:42:41.782905 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9671 23:42:41.789662 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9672 23:42:41.792825 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9673 23:42:41.799188 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9674 23:42:41.802628 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9675 23:42:41.805728 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9676 23:42:41.812695 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9677 23:42:41.816004 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9678 23:42:41.822939 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9679 23:42:41.825946 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9680 23:42:41.829166 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9681 23:42:41.835666 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9682 23:42:41.839114 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9683 23:42:41.845560 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9684 23:42:41.849124 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9685 23:42:41.852219 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9686 23:42:41.858645 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9687 23:42:41.861804 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9688 23:42:41.868386 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9689 23:42:41.871973 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9690 23:42:41.875464 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9691 23:42:41.882197 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9692 23:42:41.884979 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9693 23:42:41.891977 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9694 23:42:41.894784 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9695 23:42:41.898778 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9696 23:42:41.904642 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9697 23:42:41.908150 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9698 23:42:41.914515 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9699 23:42:41.917842 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9700 23:42:41.924835 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9701 23:42:41.927541 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9702 23:42:41.931272 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9703 23:42:41.937980 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9704 23:42:41.941116 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9705 23:42:41.947695 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9706 23:42:41.951189 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9707 23:42:41.954165 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9708 23:42:41.961103 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9709 23:42:41.964368 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9710 23:42:41.970596 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9711 23:42:41.974013 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9712 23:42:41.980603 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9713 23:42:41.983855 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9714 23:42:41.990201 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9715 23:42:41.993458 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9716 23:42:41.996785 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9717 23:42:42.003375 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9718 23:42:42.006549 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9719 23:42:42.013396 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9720 23:42:42.016599 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9721 23:42:42.022910 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9722 23:42:42.026337 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9723 23:42:42.029857 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9724 23:42:42.036447 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9725 23:42:42.039588 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9726 23:42:42.046451 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9727 23:42:42.050188 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9728 23:42:42.053340 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9729 23:42:42.059911 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9730 23:42:42.062778 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9731 23:42:42.069392 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9732 23:42:42.073381 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9733 23:42:42.079220 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9734 23:42:42.083008 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9735 23:42:42.085990 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9736 23:42:42.092839 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9737 23:42:42.095650 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9738 23:42:42.102392 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9739 23:42:42.105630 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9740 23:42:42.109177 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9741 23:42:42.112120 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9742 23:42:42.118771 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9743 23:42:42.122390 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9744 23:42:42.125182 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9745 23:42:42.131925 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9746 23:42:42.135215 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9747 23:42:42.138732 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9748 23:42:42.145334 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9749 23:42:42.148362 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9750 23:42:42.155016 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9751 23:42:42.158387 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9752 23:42:42.161773 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9753 23:42:42.168359 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9754 23:42:42.171799 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9755 23:42:42.174674 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9756 23:42:42.181390 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9757 23:42:42.184727 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9758 23:42:42.191545 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9759 23:42:42.194519 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9760 23:42:42.197782 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9761 23:42:42.204227 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9762 23:42:42.207436 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9763 23:42:42.210984 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9764 23:42:42.217418 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9765 23:42:42.221006 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9766 23:42:42.227200 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9767 23:42:42.230533 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9768 23:42:42.233955 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9769 23:42:42.240672 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9770 23:42:42.243660 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9771 23:42:42.250450 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9772 23:42:42.253911 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9773 23:42:42.256703 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9774 23:42:42.263496 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9775 23:42:42.266817 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9776 23:42:42.270516 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9777 23:42:42.276758 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9778 23:42:42.280273 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9779 23:42:42.283629 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9780 23:42:42.290185 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9781 23:42:42.293221 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9782 23:42:42.296660 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9783 23:42:42.300074 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9784 23:42:42.303015 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9785 23:42:42.309595 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9786 23:42:42.313175 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9787 23:42:42.316520 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9788 23:42:42.319824 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9789 23:42:42.326542 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9790 23:42:42.329487 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9791 23:42:42.333063 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9792 23:42:42.339615 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9793 23:42:42.342563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9794 23:42:42.349403 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9795 23:42:42.352742 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9796 23:42:42.359836 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9797 23:42:42.362681 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9798 23:42:42.366331 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9799 23:42:42.372760 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9800 23:42:42.376023 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9801 23:42:42.379356 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9802 23:42:42.385986 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9803 23:42:42.389538 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9804 23:42:42.395945 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9805 23:42:42.399207 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9806 23:42:42.405778 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9807 23:42:42.409092 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9808 23:42:42.412457 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9809 23:42:42.419264 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9810 23:42:42.422439 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9811 23:42:42.428793 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9812 23:42:42.432431 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9813 23:42:42.438836 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9814 23:42:42.442348 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9815 23:42:42.445131 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9816 23:42:42.452082 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9817 23:42:42.455591 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9818 23:42:42.461715 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9819 23:42:42.464990 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9820 23:42:42.468675 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9821 23:42:42.474839 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9822 23:42:42.478400 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9823 23:42:42.485216 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9824 23:42:42.488167 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9825 23:42:42.494974 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9826 23:42:42.498248 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9827 23:42:42.501112 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9828 23:42:42.508004 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9829 23:42:42.511316 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9830 23:42:42.518015 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9831 23:42:42.521115 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9832 23:42:42.524193 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9833 23:42:42.531152 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9834 23:42:42.534530 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9835 23:42:42.541105 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9836 23:42:42.544657 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9837 23:42:42.550868 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9838 23:42:42.554227 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9839 23:42:42.557762 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9840 23:42:42.564135 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9841 23:42:42.567349 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9842 23:42:42.574613 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9843 23:42:42.577199 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9844 23:42:42.580551 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9845 23:42:42.587399 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9846 23:42:42.590491 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9847 23:42:42.597190 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9848 23:42:42.600074 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9849 23:42:42.608177 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9850 23:42:42.610391 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9851 23:42:42.613951 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9852 23:42:42.620139 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9853 23:42:42.623563 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9854 23:42:42.629995 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9855 23:42:42.633162 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9856 23:42:42.636544 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9857 23:42:42.643336 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9858 23:42:42.646598 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9859 23:42:42.653176 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9860 23:42:42.656045 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9861 23:42:42.663035 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9862 23:42:42.666013 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9863 23:42:42.669472 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9864 23:42:42.675923 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9865 23:42:42.679350 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9866 23:42:42.685515 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9867 23:42:42.689126 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9868 23:42:42.695345 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9869 23:42:42.698901 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9870 23:42:42.705228 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9871 23:42:42.708855 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9872 23:42:42.712124 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9873 23:42:42.718752 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9874 23:42:42.721728 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9875 23:42:42.728257 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9876 23:42:42.731906 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9877 23:42:42.738243 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9878 23:42:42.741424 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9879 23:42:42.748365 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9880 23:42:42.751714 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9881 23:42:42.758225 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9882 23:42:42.761082 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9883 23:42:42.767685 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9884 23:42:42.771518 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9885 23:42:42.774972 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9886 23:42:42.781330 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9887 23:42:42.784347 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9888 23:42:42.791443 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9889 23:42:42.794382 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9890 23:42:42.801195 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9891 23:42:42.804075 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9892 23:42:42.807666 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9893 23:42:42.814495 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9894 23:42:42.817571 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9895 23:42:42.823868 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9896 23:42:42.827240 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9897 23:42:42.833838 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9898 23:42:42.837529 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9899 23:42:42.844148 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9900 23:42:42.847027 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9901 23:42:42.853714 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9902 23:42:42.857160 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9903 23:42:42.860088 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9904 23:42:42.867100 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9905 23:42:42.869950 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9906 23:42:42.876848 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9907 23:42:42.880286 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9908 23:42:42.886665 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9909 23:42:42.889950 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9910 23:42:42.896572 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9911 23:42:42.899614 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9912 23:42:42.903040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9913 23:42:42.909526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9914 23:42:42.913033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9915 23:42:42.919396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9916 23:42:42.922868 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9917 23:42:42.929853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9918 23:42:42.932536 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9919 23:42:42.939737 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9920 23:42:42.942911 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9921 23:42:42.949432 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9922 23:42:42.952673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9923 23:42:42.958966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9924 23:42:42.962319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9925 23:42:42.969055 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9926 23:42:42.972158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9927 23:42:42.978715 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9928 23:42:42.982186 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9929 23:42:42.985094 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9930 23:42:42.992272 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9931 23:42:42.995282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9932 23:42:43.002065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9933 23:42:43.008352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9934 23:42:43.011846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9935 23:42:43.018380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9936 23:42:43.022017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9937 23:42:43.028572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9938 23:42:43.031683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9939 23:42:43.038090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9940 23:42:43.041270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9941 23:42:43.048095 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9942 23:42:43.051388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9943 23:42:43.057821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9944 23:42:43.061161 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9945 23:42:43.064472 INFO: [APUAPC] vio 0
9946 23:42:43.067906 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9947 23:42:43.074387 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9948 23:42:43.074475 INFO: [APUAPC] D0_APC_0: 0x400510
9949 23:42:43.077686 INFO: [APUAPC] D0_APC_1: 0x0
9950 23:42:43.081216 INFO: [APUAPC] D0_APC_2: 0x1540
9951 23:42:43.084374 INFO: [APUAPC] D0_APC_3: 0x0
9952 23:42:43.087402 INFO: [APUAPC] D1_APC_0: 0xffffffff
9953 23:42:43.090985 INFO: [APUAPC] D1_APC_1: 0xffffffff
9954 23:42:43.094413 INFO: [APUAPC] D1_APC_2: 0x3fffff
9955 23:42:43.097749 INFO: [APUAPC] D1_APC_3: 0x0
9956 23:42:43.100843 INFO: [APUAPC] D2_APC_0: 0xffffffff
9957 23:42:43.103652 INFO: [APUAPC] D2_APC_1: 0xffffffff
9958 23:42:43.107027 INFO: [APUAPC] D2_APC_2: 0x3fffff
9959 23:42:43.110839 INFO: [APUAPC] D2_APC_3: 0x0
9960 23:42:43.113876 INFO: [APUAPC] D3_APC_0: 0xffffffff
9961 23:42:43.117137 INFO: [APUAPC] D3_APC_1: 0xffffffff
9962 23:42:43.120428 INFO: [APUAPC] D3_APC_2: 0x3fffff
9963 23:42:43.123764 INFO: [APUAPC] D3_APC_3: 0x0
9964 23:42:43.127243 INFO: [APUAPC] D4_APC_0: 0xffffffff
9965 23:42:43.130372 INFO: [APUAPC] D4_APC_1: 0xffffffff
9966 23:42:43.133499 INFO: [APUAPC] D4_APC_2: 0x3fffff
9967 23:42:43.136568 INFO: [APUAPC] D4_APC_3: 0x0
9968 23:42:43.139884 INFO: [APUAPC] D5_APC_0: 0xffffffff
9969 23:42:43.143229 INFO: [APUAPC] D5_APC_1: 0xffffffff
9970 23:42:43.146452 INFO: [APUAPC] D5_APC_2: 0x3fffff
9971 23:42:43.150078 INFO: [APUAPC] D5_APC_3: 0x0
9972 23:42:43.152984 INFO: [APUAPC] D6_APC_0: 0xffffffff
9973 23:42:43.156613 INFO: [APUAPC] D6_APC_1: 0xffffffff
9974 23:42:43.160037 INFO: [APUAPC] D6_APC_2: 0x3fffff
9975 23:42:43.163152 INFO: [APUAPC] D6_APC_3: 0x0
9976 23:42:43.166465 INFO: [APUAPC] D7_APC_0: 0xffffffff
9977 23:42:43.169704 INFO: [APUAPC] D7_APC_1: 0xffffffff
9978 23:42:43.173281 INFO: [APUAPC] D7_APC_2: 0x3fffff
9979 23:42:43.176447 INFO: [APUAPC] D7_APC_3: 0x0
9980 23:42:43.179481 INFO: [APUAPC] D8_APC_0: 0xffffffff
9981 23:42:43.182757 INFO: [APUAPC] D8_APC_1: 0xffffffff
9982 23:42:43.186344 INFO: [APUAPC] D8_APC_2: 0x3fffff
9983 23:42:43.189776 INFO: [APUAPC] D8_APC_3: 0x0
9984 23:42:43.193208 INFO: [APUAPC] D9_APC_0: 0xffffffff
9985 23:42:43.196191 INFO: [APUAPC] D9_APC_1: 0xffffffff
9986 23:42:43.199484 INFO: [APUAPC] D9_APC_2: 0x3fffff
9987 23:42:43.202688 INFO: [APUAPC] D9_APC_3: 0x0
9988 23:42:43.206128 INFO: [APUAPC] D10_APC_0: 0xffffffff
9989 23:42:43.209480 INFO: [APUAPC] D10_APC_1: 0xffffffff
9990 23:42:43.212356 INFO: [APUAPC] D10_APC_2: 0x3fffff
9991 23:42:43.216120 INFO: [APUAPC] D10_APC_3: 0x0
9992 23:42:43.219253 INFO: [APUAPC] D11_APC_0: 0xffffffff
9993 23:42:43.222837 INFO: [APUAPC] D11_APC_1: 0xffffffff
9994 23:42:43.225757 INFO: [APUAPC] D11_APC_2: 0x3fffff
9995 23:42:43.229113 INFO: [APUAPC] D11_APC_3: 0x0
9996 23:42:43.232410 INFO: [APUAPC] D12_APC_0: 0xffffffff
9997 23:42:43.235450 INFO: [APUAPC] D12_APC_1: 0xffffffff
9998 23:42:43.238894 INFO: [APUAPC] D12_APC_2: 0x3fffff
9999 23:42:43.242185 INFO: [APUAPC] D12_APC_3: 0x0
10000 23:42:43.245807 INFO: [APUAPC] D13_APC_0: 0xffffffff
10001 23:42:43.248413 INFO: [APUAPC] D13_APC_1: 0xffffffff
10002 23:42:43.251836 INFO: [APUAPC] D13_APC_2: 0x3fffff
10003 23:42:43.255315 INFO: [APUAPC] D13_APC_3: 0x0
10004 23:42:43.258392 INFO: [APUAPC] D14_APC_0: 0xffffffff
10005 23:42:43.261744 INFO: [APUAPC] D14_APC_1: 0xffffffff
10006 23:42:43.265217 INFO: [APUAPC] D14_APC_2: 0x3fffff
10007 23:42:43.268577 INFO: [APUAPC] D14_APC_3: 0x0
10008 23:42:43.271828 INFO: [APUAPC] D15_APC_0: 0xffffffff
10009 23:42:43.275208 INFO: [APUAPC] D15_APC_1: 0xffffffff
10010 23:42:43.278738 INFO: [APUAPC] D15_APC_2: 0x3fffff
10011 23:42:43.281419 INFO: [APUAPC] D15_APC_3: 0x0
10012 23:42:43.284678 INFO: [APUAPC] APC_CON: 0x4
10013 23:42:43.288079 INFO: [NOCDAPC] D0_APC_0: 0x0
10014 23:42:43.291799 INFO: [NOCDAPC] D0_APC_1: 0x0
10015 23:42:43.294674 INFO: [NOCDAPC] D1_APC_0: 0x0
10016 23:42:43.298113 INFO: [NOCDAPC] D1_APC_1: 0xfff
10017 23:42:43.298191 INFO: [NOCDAPC] D2_APC_0: 0x0
10018 23:42:43.301485 INFO: [NOCDAPC] D2_APC_1: 0xfff
10019 23:42:43.304475 INFO: [NOCDAPC] D3_APC_0: 0x0
10020 23:42:43.308025 INFO: [NOCDAPC] D3_APC_1: 0xfff
10021 23:42:43.311465 INFO: [NOCDAPC] D4_APC_0: 0x0
10022 23:42:43.314707 INFO: [NOCDAPC] D4_APC_1: 0xfff
10023 23:42:43.317836 INFO: [NOCDAPC] D5_APC_0: 0x0
10024 23:42:43.320942 INFO: [NOCDAPC] D5_APC_1: 0xfff
10025 23:42:43.324729 INFO: [NOCDAPC] D6_APC_0: 0x0
10026 23:42:43.327773 INFO: [NOCDAPC] D6_APC_1: 0xfff
10027 23:42:43.331119 INFO: [NOCDAPC] D7_APC_0: 0x0
10028 23:42:43.334339 INFO: [NOCDAPC] D7_APC_1: 0xfff
10029 23:42:43.334416 INFO: [NOCDAPC] D8_APC_0: 0x0
10030 23:42:43.337822 INFO: [NOCDAPC] D8_APC_1: 0xfff
10031 23:42:43.340665 INFO: [NOCDAPC] D9_APC_0: 0x0
10032 23:42:43.344213 INFO: [NOCDAPC] D9_APC_1: 0xfff
10033 23:42:43.347121 INFO: [NOCDAPC] D10_APC_0: 0x0
10034 23:42:43.350838 INFO: [NOCDAPC] D10_APC_1: 0xfff
10035 23:42:43.353849 INFO: [NOCDAPC] D11_APC_0: 0x0
10036 23:42:43.357368 INFO: [NOCDAPC] D11_APC_1: 0xfff
10037 23:42:43.360624 INFO: [NOCDAPC] D12_APC_0: 0x0
10038 23:42:43.363984 INFO: [NOCDAPC] D12_APC_1: 0xfff
10039 23:42:43.367463 INFO: [NOCDAPC] D13_APC_0: 0x0
10040 23:42:43.370751 INFO: [NOCDAPC] D13_APC_1: 0xfff
10041 23:42:43.373844 INFO: [NOCDAPC] D14_APC_0: 0x0
10042 23:42:43.377049 INFO: [NOCDAPC] D14_APC_1: 0xfff
10043 23:42:43.380289 INFO: [NOCDAPC] D15_APC_0: 0x0
10044 23:42:43.383670 INFO: [NOCDAPC] D15_APC_1: 0xfff
10045 23:42:43.383750 INFO: [NOCDAPC] APC_CON: 0x4
10046 23:42:43.386910 INFO: [APUAPC] set_apusys_apc done
10047 23:42:43.390625 INFO: [DEVAPC] devapc_init done
10048 23:42:43.396869 INFO: GICv3 without legacy support detected.
10049 23:42:43.400096 INFO: ARM GICv3 driver initialized in EL3
10050 23:42:43.403268 INFO: Maximum SPI INTID supported: 639
10051 23:42:43.407002 INFO: BL31: Initializing runtime services
10052 23:42:43.413221 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10053 23:42:43.416871 INFO: SPM: enable CPC mode
10054 23:42:43.419519 INFO: mcdi ready for mcusys-off-idle and system suspend
10055 23:42:43.426151 INFO: BL31: Preparing for EL3 exit to normal world
10056 23:42:43.429453 INFO: Entry point address = 0x80000000
10057 23:42:43.429537 INFO: SPSR = 0x8
10058 23:42:43.437170
10059 23:42:43.437254
10060 23:42:43.437372
10061 23:42:43.440311 Starting depthcharge on Spherion...
10062 23:42:43.440411
10063 23:42:43.440508 Wipe memory regions:
10064 23:42:43.440582
10065 23:42:43.441223 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10066 23:42:43.441366 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10067 23:42:43.441450 Setting prompt string to ['asurada:']
10068 23:42:43.441533 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10069 23:42:43.443325 [0x00000040000000, 0x00000054600000)
10070 23:42:43.566200
10071 23:42:43.566335 [0x00000054660000, 0x00000080000000)
10072 23:42:43.826976
10073 23:42:43.827115 [0x000000821a7280, 0x000000ffe64000)
10074 23:42:44.571427
10075 23:42:44.571565 [0x00000100000000, 0x00000240000000)
10076 23:42:46.462292
10077 23:42:46.465458 Initializing XHCI USB controller at 0x11200000.
10078 23:42:47.503936
10079 23:42:47.506944 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10080 23:42:47.507042
10081 23:42:47.507109
10082 23:42:47.507399 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10084 23:42:47.607735 asurada: tftpboot 192.168.201.1 14172919/tftp-deploy-fqq5gldl/kernel/image.itb 14172919/tftp-deploy-fqq5gldl/kernel/cmdline
10085 23:42:47.607927 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10086 23:42:47.608060 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10087 23:42:47.612552 tftpboot 192.168.201.1 14172919/tftp-deploy-fqq5gldl/kernel/image.itp-deploy-fqq5gldl/kernel/cmdline
10088 23:42:47.612640
10089 23:42:47.612706 Waiting for link
10090 23:42:47.770964
10091 23:42:47.771108 R8152: Initializing
10092 23:42:47.771223
10093 23:42:47.774207 Version 6 (ocp_data = 5c30)
10094 23:42:47.774287
10095 23:42:47.777252 R8152: Done initializing
10096 23:42:47.777376
10097 23:42:47.777459 Adding net device
10098 23:42:49.760658
10099 23:42:49.760803 done.
10100 23:42:49.760878
10101 23:42:49.760940 MAC: 00:24:32:30:7c:7b
10102 23:42:49.760999
10103 23:42:49.764055 Sending DHCP discover... done.
10104 23:42:49.764134
10105 23:42:49.767251 Waiting for reply... done.
10106 23:42:49.767330
10107 23:42:49.770386 Sending DHCP request... done.
10108 23:42:49.770466
10109 23:42:49.770529 Waiting for reply... done.
10110 23:42:49.770589
10111 23:42:49.773406 My ip is 192.168.201.14
10112 23:42:49.773476
10113 23:42:49.777198 The DHCP server ip is 192.168.201.1
10114 23:42:49.777319
10115 23:42:49.780246 TFTP server IP predefined by user: 192.168.201.1
10116 23:42:49.780322
10117 23:42:49.786457 Bootfile predefined by user: 14172919/tftp-deploy-fqq5gldl/kernel/image.itb
10118 23:42:49.786542
10119 23:42:49.791015 Sending tftp read request... done.
10120 23:42:49.791097
10121 23:42:49.793499 Waiting for the transfer...
10122 23:42:49.796734
10123 23:42:50.331812 00000000 ################################################################
10124 23:42:50.331976
10125 23:42:50.873166 00080000 ################################################################
10126 23:42:50.873343
10127 23:42:51.409485 00100000 ################################################################
10128 23:42:51.409633
10129 23:42:51.932039 00180000 ################################################################
10130 23:42:51.932180
10131 23:42:52.466308 00200000 ################################################################
10132 23:42:52.466454
10133 23:42:53.001121 00280000 ################################################################
10134 23:42:53.001311
10135 23:42:53.544496 00300000 ################################################################
10136 23:42:53.544643
10137 23:42:54.099125 00380000 ################################################################
10138 23:42:54.099277
10139 23:42:54.644679 00400000 ################################################################
10140 23:42:54.644829
10141 23:42:55.194065 00480000 ################################################################
10142 23:42:55.194208
10143 23:42:55.736774 00500000 ################################################################
10144 23:42:55.736931
10145 23:42:56.256483 00580000 ################################################################
10146 23:42:56.256635
10147 23:42:56.775412 00600000 ################################################################
10148 23:42:56.775548
10149 23:42:57.301130 00680000 ################################################################
10150 23:42:57.301332
10151 23:42:57.826091 00700000 ################################################################
10152 23:42:57.826273
10153 23:42:58.359035 00780000 ################################################################
10154 23:42:58.359166
10155 23:42:58.897146 00800000 ################################################################
10156 23:42:58.897335
10157 23:42:59.427216 00880000 ################################################################
10158 23:42:59.427371
10159 23:42:59.957098 00900000 ################################################################
10160 23:42:59.957229
10161 23:43:00.494300 00980000 ################################################################
10162 23:43:00.494448
10163 23:43:01.034747 00a00000 ################################################################
10164 23:43:01.034885
10165 23:43:01.584611 00a80000 ################################################################
10166 23:43:01.584759
10167 23:43:02.131362 00b00000 ################################################################
10168 23:43:02.131502
10169 23:43:02.688392 00b80000 ################################################################
10170 23:43:02.688534
10171 23:43:03.225237 00c00000 ################################################################
10172 23:43:03.225419
10173 23:43:03.767993 00c80000 ################################################################
10174 23:43:03.768135
10175 23:43:04.305176 00d00000 ################################################################
10176 23:43:04.305350
10177 23:43:04.833075 00d80000 ################################################################
10178 23:43:04.833247
10179 23:43:05.366492 00e00000 ################################################################
10180 23:43:05.366632
10181 23:43:05.896023 00e80000 ################################################################
10182 23:43:05.896158
10183 23:43:06.434974 00f00000 ################################################################
10184 23:43:06.435110
10185 23:43:06.977536 00f80000 ################################################################
10186 23:43:06.977665
10187 23:43:07.518421 01000000 ################################################################
10188 23:43:07.518551
10189 23:43:08.064828 01080000 ################################################################
10190 23:43:08.064958
10191 23:43:08.630345 01100000 ################################################################
10192 23:43:08.630479
10193 23:43:09.187671 01180000 ################################################################
10194 23:43:09.187846
10195 23:43:09.769867 01200000 ################################################################
10196 23:43:09.770475
10197 23:43:10.363527 01280000 ################################################################
10198 23:43:10.363658
10199 23:43:10.935877 01300000 ################################################################
10200 23:43:10.936039
10201 23:43:11.485527 01380000 ################################################################
10202 23:43:11.485695
10203 23:43:12.065725 01400000 ################################################################
10204 23:43:12.065861
10205 23:43:12.651979 01480000 ################################################################
10206 23:43:12.652477
10207 23:43:13.256808 01500000 ################################################################
10208 23:43:13.256940
10209 23:43:13.853328 01580000 ################################################################
10210 23:43:13.853855
10211 23:43:14.437722 01600000 ################################################################
10212 23:43:14.437854
10213 23:43:15.002140 01680000 ################################################################
10214 23:43:15.002302
10215 23:43:15.577095 01700000 ################################################################
10216 23:43:15.577314
10217 23:43:16.156473 01780000 ################################################################
10218 23:43:16.156625
10219 23:43:16.731530 01800000 ################################################################
10220 23:43:16.731678
10221 23:43:17.314154 01880000 ################################################################
10222 23:43:17.314303
10223 23:43:17.897711 01900000 ################################################################
10224 23:43:17.897857
10225 23:43:18.483664 01980000 ################################################################
10226 23:43:18.483813
10227 23:43:19.063448 01a00000 ################################################################
10228 23:43:19.063592
10229 23:43:19.645459 01a80000 ################################################################
10230 23:43:19.645623
10231 23:43:20.233044 01b00000 ################################################################
10232 23:43:20.233180
10233 23:43:20.840078 01b80000 ################################################################
10234 23:43:20.840292
10235 23:43:21.493581 01c00000 ################################################################
10236 23:43:21.494151
10237 23:43:22.176759 01c80000 ################################################################
10238 23:43:22.177283
10239 23:43:22.870443 01d00000 ################################################################
10240 23:43:22.870933
10241 23:43:23.576916 01d80000 ################################################################
10242 23:43:23.577529
10243 23:43:24.032930 01e00000 ############################################## done.
10244 23:43:24.033081
10245 23:43:24.035548 The bootfile was 31828318 bytes long.
10246 23:43:24.035662
10247 23:43:24.039454 Sending tftp read request... done.
10248 23:43:24.039553
10249 23:43:24.042172 Waiting for the transfer...
10250 23:43:24.042259
10251 23:43:24.045806 00000000 # done.
10252 23:43:24.045899
10253 23:43:24.052511 Command line loaded dynamically from TFTP file: 14172919/tftp-deploy-fqq5gldl/kernel/cmdline
10254 23:43:24.052624
10255 23:43:24.075282 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172919/extract-nfsrootfs-_tc5mk7h,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10256 23:43:24.075431
10257 23:43:24.075503 Loading FIT.
10258 23:43:24.075563
10259 23:43:24.078393 Image ramdisk-1 has 18717593 bytes.
10260 23:43:24.078482
10261 23:43:24.082294 Image fdt-1 has 47258 bytes.
10262 23:43:24.082395
10263 23:43:24.084917 Image kernel-1 has 13061430 bytes.
10264 23:43:24.085004
10265 23:43:24.091790 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10266 23:43:24.095107
10267 23:43:24.111988 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10268 23:43:24.112159
10269 23:43:24.114781 Choosing best match conf-1 for compat google,spherion-rev2.
10270 23:43:24.120357
10271 23:43:24.124688 Connected to device vid:did:rid of 1ae0:0028:00
10272 23:43:24.131883
10273 23:43:24.135005 tpm_get_response: command 0x17b, return code 0x0
10274 23:43:24.135090
10275 23:43:24.138473 ec_init: CrosEC protocol v3 supported (256, 248)
10276 23:43:24.142693
10277 23:43:24.146105 tpm_cleanup: add release locality here.
10278 23:43:24.146195
10279 23:43:24.146261 Shutting down all USB controllers.
10280 23:43:24.149071
10281 23:43:24.149191 Removing current net device
10282 23:43:24.149320
10283 23:43:24.156667 Exiting depthcharge with code 4 at timestamp: 69960801
10284 23:43:24.156828
10285 23:43:24.159362 LZMA decompressing kernel-1 to 0x821a6718
10286 23:43:24.159450
10287 23:43:24.162543 LZMA decompressing kernel-1 to 0x40000000
10288 23:43:25.771876
10289 23:43:25.772069 jumping to kernel
10290 23:43:25.772751 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10291 23:43:25.772899 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10292 23:43:25.773015 Setting prompt string to ['Linux version [0-9]']
10293 23:43:25.773123 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10294 23:43:25.773233 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10295 23:43:25.854032
10296 23:43:25.857001 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10297 23:43:25.860267 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10298 23:43:25.860400 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10299 23:43:25.860511 Setting prompt string to []
10300 23:43:25.860627 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10301 23:43:25.860739 Using line separator: #'\n'#
10302 23:43:25.860841 No login prompt set.
10303 23:43:25.860947 Parsing kernel messages
10304 23:43:25.861082 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10305 23:43:25.861286 [login-action] Waiting for messages, (timeout 00:03:44)
10306 23:43:25.861412 Waiting using forced prompt support (timeout 00:01:52)
10307 23:43:25.879954 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j217067-arm64-gcc-10-defconfig-arm64-chromebook-s48tj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024
10308 23:43:25.883630 [ 0.000000] random: crng init done
10309 23:43:25.889823 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10310 23:43:25.893295 [ 0.000000] efi: UEFI not found.
10311 23:43:25.900025 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10312 23:43:25.906303 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10313 23:43:25.916775 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10314 23:43:25.926594 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10315 23:43:25.933210 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10316 23:43:25.939579 [ 0.000000] printk: bootconsole [mtk8250] enabled
10317 23:43:25.945871 [ 0.000000] NUMA: No NUMA configuration found
10318 23:43:25.952799 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10319 23:43:25.955909 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10320 23:43:25.959252 [ 0.000000] Zone ranges:
10321 23:43:25.966377 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10322 23:43:25.969099 [ 0.000000] DMA32 empty
10323 23:43:25.976046 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10324 23:43:25.978970 [ 0.000000] Movable zone start for each node
10325 23:43:25.982543 [ 0.000000] Early memory node ranges
10326 23:43:25.989528 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10327 23:43:25.995635 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10328 23:43:26.002535 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10329 23:43:26.009161 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10330 23:43:26.011927 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10331 23:43:26.021855 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10332 23:43:26.078017 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10333 23:43:26.084714 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10334 23:43:26.091121 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10335 23:43:26.094626 [ 0.000000] psci: probing for conduit method from DT.
10336 23:43:26.101217 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10337 23:43:26.104239 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10338 23:43:26.110932 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10339 23:43:26.114177 [ 0.000000] psci: SMC Calling Convention v1.2
10340 23:43:26.121415 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10341 23:43:26.124275 [ 0.000000] Detected VIPT I-cache on CPU0
10342 23:43:26.130983 [ 0.000000] CPU features: detected: GIC system register CPU interface
10343 23:43:26.137395 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10344 23:43:26.143943 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10345 23:43:26.151168 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10346 23:43:26.157695 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10347 23:43:26.167148 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10348 23:43:26.170401 [ 0.000000] alternatives: applying boot alternatives
10349 23:43:26.177158 [ 0.000000] Fallback order for Node 0: 0
10350 23:43:26.184183 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10351 23:43:26.186918 [ 0.000000] Policy zone: Normal
10352 23:43:26.209952 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172919/extract-nfsrootfs-_tc5mk7h,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10353 23:43:26.219926 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10354 23:43:26.231069 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10355 23:43:26.240887 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10356 23:43:26.247416 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10357 23:43:26.251161 <6>[ 0.000000] software IO TLB: area num 8.
10358 23:43:26.307492 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10359 23:43:26.457263 <6>[ 0.000000] Memory: 7945908K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406860K reserved, 32768K cma-reserved)
10360 23:43:26.463924 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10361 23:43:26.470271 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10362 23:43:26.473779 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10363 23:43:26.480660 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10364 23:43:26.487320 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10365 23:43:26.490916 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10366 23:43:26.500429 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10367 23:43:26.506989 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10368 23:43:26.513377 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10369 23:43:26.520537 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10370 23:43:26.523588 <6>[ 0.000000] GICv3: 608 SPIs implemented
10371 23:43:26.526776 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10372 23:43:26.533496 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10373 23:43:26.536883 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10374 23:43:26.543427 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10375 23:43:26.556450 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10376 23:43:26.569451 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10377 23:43:26.576380 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10378 23:43:26.583934 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10379 23:43:26.597845 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10380 23:43:26.603485 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10381 23:43:26.610543 <6>[ 0.009228] Console: colour dummy device 80x25
10382 23:43:26.620126 <6>[ 0.013955] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10383 23:43:26.626581 <6>[ 0.024397] pid_max: default: 32768 minimum: 301
10384 23:43:26.630327 <6>[ 0.029299] LSM: Security Framework initializing
10385 23:43:26.636726 <6>[ 0.034238] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10386 23:43:26.646688 <6>[ 0.042051] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10387 23:43:26.657264 <6>[ 0.051313] cblist_init_generic: Setting adjustable number of callback queues.
10388 23:43:26.660046 <6>[ 0.058757] cblist_init_generic: Setting shift to 3 and lim to 1.
10389 23:43:26.670165 <6>[ 0.065096] cblist_init_generic: Setting adjustable number of callback queues.
10390 23:43:26.676954 <6>[ 0.072523] cblist_init_generic: Setting shift to 3 and lim to 1.
10391 23:43:26.679345 <6>[ 0.078925] rcu: Hierarchical SRCU implementation.
10392 23:43:26.686222 <6>[ 0.083939] rcu: Max phase no-delay instances is 1000.
10393 23:43:26.692722 <6>[ 0.090979] EFI services will not be available.
10394 23:43:26.696267 <6>[ 0.095937] smp: Bringing up secondary CPUs ...
10395 23:43:26.705004 <6>[ 0.100980] Detected VIPT I-cache on CPU1
10396 23:43:26.711333 <6>[ 0.101041] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10397 23:43:26.717605 <6>[ 0.101069] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10398 23:43:26.720732 <6>[ 0.101407] Detected VIPT I-cache on CPU2
10399 23:43:26.727421 <6>[ 0.101458] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10400 23:43:26.737405 <6>[ 0.101475] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10401 23:43:26.740834 <6>[ 0.101733] Detected VIPT I-cache on CPU3
10402 23:43:26.747887 <6>[ 0.101779] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10403 23:43:26.753901 <6>[ 0.101794] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10404 23:43:26.757321 <6>[ 0.102095] CPU features: detected: Spectre-v4
10405 23:43:26.764363 <6>[ 0.102101] CPU features: detected: Spectre-BHB
10406 23:43:26.767486 <6>[ 0.102106] Detected PIPT I-cache on CPU4
10407 23:43:26.774027 <6>[ 0.102164] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10408 23:43:26.780380 <6>[ 0.102180] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10409 23:43:26.786970 <6>[ 0.102473] Detected PIPT I-cache on CPU5
10410 23:43:26.793874 <6>[ 0.102537] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10411 23:43:26.800245 <6>[ 0.102553] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10412 23:43:26.803553 <6>[ 0.102834] Detected PIPT I-cache on CPU6
10413 23:43:26.810214 <6>[ 0.102900] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10414 23:43:26.816770 <6>[ 0.102916] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10415 23:43:26.823634 <6>[ 0.103212] Detected PIPT I-cache on CPU7
10416 23:43:26.830079 <6>[ 0.103278] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10417 23:43:26.836686 <6>[ 0.103294] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10418 23:43:26.839994 <6>[ 0.103343] smp: Brought up 1 node, 8 CPUs
10419 23:43:26.846381 <6>[ 0.244750] SMP: Total of 8 processors activated.
10420 23:43:26.849855 <6>[ 0.249702] CPU features: detected: 32-bit EL0 Support
10421 23:43:26.859941 <6>[ 0.255097] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10422 23:43:26.866492 <6>[ 0.263952] CPU features: detected: Common not Private translations
10423 23:43:26.872929 <6>[ 0.270428] CPU features: detected: CRC32 instructions
10424 23:43:26.877122 <6>[ 0.275780] CPU features: detected: RCpc load-acquire (LDAPR)
10425 23:43:26.883454 <6>[ 0.281740] CPU features: detected: LSE atomic instructions
10426 23:43:26.889666 <6>[ 0.287557] CPU features: detected: Privileged Access Never
10427 23:43:26.896299 <6>[ 0.293336] CPU features: detected: RAS Extension Support
10428 23:43:26.903270 <6>[ 0.298945] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10429 23:43:26.906742 <6>[ 0.306166] CPU: All CPU(s) started at EL2
10430 23:43:26.912610 <6>[ 0.310483] alternatives: applying system-wide alternatives
10431 23:43:26.922009 <6>[ 0.321304] devtmpfs: initialized
10432 23:43:26.934527 <6>[ 0.330116] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10433 23:43:26.944465 <6>[ 0.340076] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10434 23:43:26.951302 <6>[ 0.348085] pinctrl core: initialized pinctrl subsystem
10435 23:43:26.954877 <6>[ 0.354760] DMI not present or invalid.
10436 23:43:26.961115 <6>[ 0.359169] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10437 23:43:26.970964 <6>[ 0.366024] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10438 23:43:26.977353 <6>[ 0.373612] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10439 23:43:26.987095 <6>[ 0.381827] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10440 23:43:26.990205 <6>[ 0.390069] audit: initializing netlink subsys (disabled)
10441 23:43:27.000349 <5>[ 0.395766] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10442 23:43:27.007042 <6>[ 0.396474] thermal_sys: Registered thermal governor 'step_wise'
10443 23:43:27.013726 <6>[ 0.403730] thermal_sys: Registered thermal governor 'power_allocator'
10444 23:43:27.017907 <6>[ 0.409985] cpuidle: using governor menu
10445 23:43:27.023654 <6>[ 0.420943] NET: Registered PF_QIPCRTR protocol family
10446 23:43:27.030159 <6>[ 0.426434] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10447 23:43:27.036565 <6>[ 0.433537] ASID allocator initialised with 32768 entries
10448 23:43:27.040110 <6>[ 0.440114] Serial: AMBA PL011 UART driver
10449 23:43:27.050102 <4>[ 0.448950] Trying to register duplicate clock ID: 134
10450 23:43:27.108153 <6>[ 0.510188] KASLR enabled
10451 23:43:27.122654 <6>[ 0.517844] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10452 23:43:27.128763 <6>[ 0.524858] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10453 23:43:27.135887 <6>[ 0.531344] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10454 23:43:27.142261 <6>[ 0.538345] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10455 23:43:27.148712 <6>[ 0.544833] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10456 23:43:27.155611 <6>[ 0.551838] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10457 23:43:27.162553 <6>[ 0.558325] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10458 23:43:27.168727 <6>[ 0.565327] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10459 23:43:27.172375 <6>[ 0.572782] ACPI: Interpreter disabled.
10460 23:43:27.180723 <6>[ 0.579212] iommu: Default domain type: Translated
10461 23:43:27.187029 <6>[ 0.584324] iommu: DMA domain TLB invalidation policy: strict mode
10462 23:43:27.190207 <5>[ 0.590987] SCSI subsystem initialized
10463 23:43:27.196792 <6>[ 0.595230] usbcore: registered new interface driver usbfs
10464 23:43:27.203281 <6>[ 0.600961] usbcore: registered new interface driver hub
10465 23:43:27.206646 <6>[ 0.606513] usbcore: registered new device driver usb
10466 23:43:27.213535 <6>[ 0.612630] pps_core: LinuxPPS API ver. 1 registered
10467 23:43:27.223510 <6>[ 0.617821] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10468 23:43:27.226717 <6>[ 0.627164] PTP clock support registered
10469 23:43:27.230007 <6>[ 0.631404] EDAC MC: Ver: 3.0.0
10470 23:43:27.237579 <6>[ 0.636587] FPGA manager framework
10471 23:43:27.244235 <6>[ 0.640264] Advanced Linux Sound Architecture Driver Initialized.
10472 23:43:27.247636 <6>[ 0.647036] vgaarb: loaded
10473 23:43:27.254479 <6>[ 0.650188] clocksource: Switched to clocksource arch_sys_counter
10474 23:43:27.257061 <5>[ 0.656629] VFS: Disk quotas dquot_6.6.0
10475 23:43:27.264299 <6>[ 0.660819] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10476 23:43:27.266925 <6>[ 0.668005] pnp: PnP ACPI: disabled
10477 23:43:27.276022 <6>[ 0.674654] NET: Registered PF_INET protocol family
10478 23:43:27.285225 <6>[ 0.680247] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10479 23:43:27.296996 <6>[ 0.692564] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10480 23:43:27.306596 <6>[ 0.701376] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10481 23:43:27.313134 <6>[ 0.709348] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10482 23:43:27.323183 <6>[ 0.718048] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10483 23:43:27.330069 <6>[ 0.727798] TCP: Hash tables configured (established 65536 bind 65536)
10484 23:43:27.336400 <6>[ 0.734670] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10485 23:43:27.346492 <6>[ 0.741869] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10486 23:43:27.352585 <6>[ 0.749577] NET: Registered PF_UNIX/PF_LOCAL protocol family
10487 23:43:27.359365 <6>[ 0.755722] RPC: Registered named UNIX socket transport module.
10488 23:43:27.362889 <6>[ 0.761876] RPC: Registered udp transport module.
10489 23:43:27.369034 <6>[ 0.766806] RPC: Registered tcp transport module.
10490 23:43:27.375916 <6>[ 0.771737] RPC: Registered tcp NFSv4.1 backchannel transport module.
10491 23:43:27.379343 <6>[ 0.778403] PCI: CLS 0 bytes, default 64
10492 23:43:27.382533 <6>[ 0.782745] Unpacking initramfs...
10493 23:43:27.399200 <6>[ 0.794693] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10494 23:43:27.408955 <6>[ 0.803328] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10495 23:43:27.411995 <6>[ 0.812155] kvm [1]: IPA Size Limit: 40 bits
10496 23:43:27.419031 <6>[ 0.816682] kvm [1]: GICv3: no GICV resource entry
10497 23:43:27.422284 <6>[ 0.821700] kvm [1]: disabling GICv2 emulation
10498 23:43:27.428490 <6>[ 0.826385] kvm [1]: GIC system register CPU interface enabled
10499 23:43:27.431801 <6>[ 0.832549] kvm [1]: vgic interrupt IRQ18
10500 23:43:27.438479 <6>[ 0.836905] kvm [1]: VHE mode initialized successfully
10501 23:43:27.444880 <5>[ 0.843384] Initialise system trusted keyrings
10502 23:43:27.451503 <6>[ 0.848195] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10503 23:43:27.459182 <6>[ 0.858204] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10504 23:43:27.465928 <5>[ 0.864589] NFS: Registering the id_resolver key type
10505 23:43:27.469048 <5>[ 0.869913] Key type id_resolver registered
10506 23:43:27.475721 <5>[ 0.874329] Key type id_legacy registered
10507 23:43:27.482713 <6>[ 0.878609] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10508 23:43:27.488781 <6>[ 0.885529] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10509 23:43:27.495341 <6>[ 0.893245] 9p: Installing v9fs 9p2000 file system support
10510 23:43:27.532431 <5>[ 0.931547] Key type asymmetric registered
10511 23:43:27.535635 <5>[ 0.935877] Asymmetric key parser 'x509' registered
10512 23:43:27.545917 <6>[ 0.941020] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10513 23:43:27.549022 <6>[ 0.948632] io scheduler mq-deadline registered
10514 23:43:27.552104 <6>[ 0.953407] io scheduler kyber registered
10515 23:43:27.571362 <6>[ 0.970528] EINJ: ACPI disabled.
10516 23:43:27.604306 <4>[ 0.996772] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10517 23:43:27.614604 <4>[ 1.007403] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10518 23:43:27.629099 <6>[ 1.028106] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10519 23:43:27.636780 <6>[ 1.036021] printk: console [ttyS0] disabled
10520 23:43:27.665248 <6>[ 1.060649] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10521 23:43:27.671366 <6>[ 1.070119] printk: console [ttyS0] enabled
10522 23:43:27.674736 <6>[ 1.070119] printk: console [ttyS0] enabled
10523 23:43:27.681522 <6>[ 1.079016] printk: bootconsole [mtk8250] disabled
10524 23:43:27.684912 <6>[ 1.079016] printk: bootconsole [mtk8250] disabled
10525 23:43:27.691853 <6>[ 1.089981] SuperH (H)SCI(F) driver initialized
10526 23:43:27.694871 <6>[ 1.095267] msm_serial: driver initialized
10527 23:43:27.708493 <6>[ 1.104128] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10528 23:43:27.718181 <6>[ 1.112674] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10529 23:43:27.725107 <6>[ 1.121217] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10530 23:43:27.734998 <6>[ 1.129845] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10531 23:43:27.744882 <6>[ 1.138552] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10532 23:43:27.751133 <6>[ 1.147273] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10533 23:43:27.761185 <6>[ 1.155814] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10534 23:43:27.767721 <6>[ 1.164610] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10535 23:43:27.777921 <6>[ 1.173153] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10536 23:43:27.790090 <6>[ 1.188754] loop: module loaded
10537 23:43:27.796038 <6>[ 1.194626] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10538 23:43:27.818707 <4>[ 1.217903] mtk-pmic-keys: Failed to locate of_node [id: -1]
10539 23:43:27.825354 <6>[ 1.224667] megasas: 07.719.03.00-rc1
10540 23:43:27.835076 <6>[ 1.234173] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10541 23:43:27.850190 <6>[ 1.245570] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10542 23:43:27.863099 <6>[ 1.262286] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10543 23:43:27.919614 <6>[ 1.312169] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10544 23:43:28.178993 <6>[ 1.577780] Freeing initrd memory: 18276K
10545 23:43:28.190188 <6>[ 1.589275] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10546 23:43:28.201244 <6>[ 1.600265] tun: Universal TUN/TAP device driver, 1.6
10547 23:43:28.204918 <6>[ 1.606345] thunder_xcv, ver 1.0
10548 23:43:28.207959 <6>[ 1.609840] thunder_bgx, ver 1.0
10549 23:43:28.210751 <6>[ 1.613336] nicpf, ver 1.0
10550 23:43:28.221921 <6>[ 1.617353] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10551 23:43:28.225100 <6>[ 1.624829] hns3: Copyright (c) 2017 Huawei Corporation.
10552 23:43:28.231889 <6>[ 1.630416] hclge is initializing
10553 23:43:28.235031 <6>[ 1.633993] e1000: Intel(R) PRO/1000 Network Driver
10554 23:43:28.241403 <6>[ 1.639123] e1000: Copyright (c) 1999-2006 Intel Corporation.
10555 23:43:28.244994 <6>[ 1.645135] e1000e: Intel(R) PRO/1000 Network Driver
10556 23:43:28.251182 <6>[ 1.650350] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10557 23:43:28.257877 <6>[ 1.656538] igb: Intel(R) Gigabit Ethernet Network Driver
10558 23:43:28.264934 <6>[ 1.662188] igb: Copyright (c) 2007-2014 Intel Corporation.
10559 23:43:28.271311 <6>[ 1.668023] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10560 23:43:28.278285 <6>[ 1.674541] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10561 23:43:28.281268 <6>[ 1.681002] sky2: driver version 1.30
10562 23:43:28.287837 <6>[ 1.685924] usbcore: registered new device driver r8152-cfgselector
10563 23:43:28.294091 <6>[ 1.692458] usbcore: registered new interface driver r8152
10564 23:43:28.300834 <6>[ 1.698277] VFIO - User Level meta-driver version: 0.3
10565 23:43:28.307545 <6>[ 1.706514] usbcore: registered new interface driver usb-storage
10566 23:43:28.314148 <6>[ 1.712952] usbcore: registered new device driver onboard-usb-hub
10567 23:43:28.323059 <6>[ 1.722089] mt6397-rtc mt6359-rtc: registered as rtc0
10568 23:43:28.332919 <6>[ 1.727551] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T23:43:28 UTC (1717544608)
10569 23:43:28.336605 <6>[ 1.737113] i2c_dev: i2c /dev entries driver
10570 23:43:28.353245 <6>[ 1.748861] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10571 23:43:28.360060 <4>[ 1.757579] cpu cpu0: supply cpu not found, using dummy regulator
10572 23:43:28.366645 <4>[ 1.764006] cpu cpu1: supply cpu not found, using dummy regulator
10573 23:43:28.372957 <4>[ 1.770424] cpu cpu2: supply cpu not found, using dummy regulator
10574 23:43:28.379435 <4>[ 1.776817] cpu cpu3: supply cpu not found, using dummy regulator
10575 23:43:28.386132 <4>[ 1.783214] cpu cpu4: supply cpu not found, using dummy regulator
10576 23:43:28.392956 <4>[ 1.789612] cpu cpu5: supply cpu not found, using dummy regulator
10577 23:43:28.399228 <4>[ 1.796008] cpu cpu6: supply cpu not found, using dummy regulator
10578 23:43:28.405599 <4>[ 1.802403] cpu cpu7: supply cpu not found, using dummy regulator
10579 23:43:28.423777 <6>[ 1.823061] cpu cpu0: EM: created perf domain
10580 23:43:28.427313 <6>[ 1.828003] cpu cpu4: EM: created perf domain
10581 23:43:28.434624 <6>[ 1.833610] sdhci: Secure Digital Host Controller Interface driver
10582 23:43:28.441723 <6>[ 1.840043] sdhci: Copyright(c) Pierre Ossman
10583 23:43:28.448126 <6>[ 1.844997] Synopsys Designware Multimedia Card Interface Driver
10584 23:43:28.454869 <6>[ 1.851638] sdhci-pltfm: SDHCI platform and OF driver helper
10585 23:43:28.457651 <6>[ 1.851679] mmc0: CQHCI version 5.10
10586 23:43:28.464229 <6>[ 1.861716] ledtrig-cpu: registered to indicate activity on CPUs
10587 23:43:28.471206 <6>[ 1.868839] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10588 23:43:28.477617 <6>[ 1.875911] usbcore: registered new interface driver usbhid
10589 23:43:28.481001 <6>[ 1.881733] usbhid: USB HID core driver
10590 23:43:28.487425 <6>[ 1.885920] spi_master spi0: will run message pump with realtime priority
10591 23:43:28.537338 <6>[ 1.929688] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10592 23:43:28.556834 <6>[ 1.945341] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10593 23:43:28.560112 <6>[ 1.955571] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10594 23:43:28.566803 <6>[ 1.960485] cros-ec-spi spi0.0: Chrome EC device registered
10595 23:43:28.570157 <6>[ 1.970744] mmc0: Command Queue Engine enabled
10596 23:43:28.576674 <6>[ 1.975467] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10597 23:43:28.583917 <6>[ 1.983271] mmcblk0: mmc0:0001 DA4128 116 GiB
10598 23:43:28.594013 <6>[ 1.985021] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10599 23:43:28.600711 <6>[ 1.991751] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10600 23:43:28.604127 <6>[ 1.998475] NET: Registered PF_PACKET protocol family
10601 23:43:28.610929 <6>[ 2.004617] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10602 23:43:28.614142 <6>[ 2.008601] 9pnet: Installing 9P2000 support
10603 23:43:28.620573 <6>[ 2.014341] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10604 23:43:28.623915 <5>[ 2.018293] Key type dns_resolver registered
10605 23:43:28.630574 <6>[ 2.024115] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10606 23:43:28.634078 <6>[ 2.028230] registered taskstats version 1
10607 23:43:28.640421 <5>[ 2.038898] Loading compiled-in X.509 certificates
10608 23:43:28.668868 <4>[ 2.061219] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10609 23:43:28.678899 <4>[ 2.071913] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10610 23:43:28.692732 <6>[ 2.091421] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10611 23:43:28.699408 <6>[ 2.098298] xhci-mtk 11200000.usb: xHCI Host Controller
10612 23:43:28.705573 <6>[ 2.103825] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10613 23:43:28.716082 <6>[ 2.111670] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10614 23:43:28.722277 <6>[ 2.121121] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10615 23:43:28.729208 <6>[ 2.127209] xhci-mtk 11200000.usb: xHCI Host Controller
10616 23:43:28.735770 <6>[ 2.132782] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10617 23:43:28.742205 <6>[ 2.140462] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10618 23:43:28.749487 <6>[ 2.148292] hub 1-0:1.0: USB hub found
10619 23:43:28.752483 <6>[ 2.152319] hub 1-0:1.0: 1 port detected
10620 23:43:28.762645 <6>[ 2.156616] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10621 23:43:28.765807 <6>[ 2.165345] hub 2-0:1.0: USB hub found
10622 23:43:28.769115 <6>[ 2.169370] hub 2-0:1.0: 1 port detected
10623 23:43:28.777363 <6>[ 2.176099] mtk-msdc 11f70000.mmc: Got CD GPIO
10624 23:43:28.789919 <6>[ 2.185954] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10625 23:43:28.796916 <6>[ 2.193988] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10626 23:43:28.806924 <4>[ 2.201919] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10627 23:43:28.816779 <6>[ 2.211458] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10628 23:43:28.823377 <6>[ 2.219535] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10629 23:43:28.830429 <6>[ 2.227543] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10630 23:43:28.840074 <6>[ 2.235463] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10631 23:43:28.847171 <6>[ 2.243281] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10632 23:43:28.856232 <6>[ 2.251098] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10633 23:43:28.866372 <6>[ 2.261503] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10634 23:43:28.873206 <6>[ 2.269859] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10635 23:43:28.882941 <6>[ 2.278205] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10636 23:43:28.889972 <6>[ 2.286545] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10637 23:43:28.899931 <6>[ 2.294883] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10638 23:43:28.905967 <6>[ 2.303221] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10639 23:43:28.916088 <6>[ 2.311559] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10640 23:43:28.922663 <6>[ 2.319897] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10641 23:43:28.932345 <6>[ 2.328235] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10642 23:43:28.942735 <6>[ 2.336573] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10643 23:43:28.948956 <6>[ 2.344911] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10644 23:43:28.958924 <6>[ 2.353248] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10645 23:43:28.965602 <6>[ 2.361588] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10646 23:43:28.975675 <6>[ 2.369927] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10647 23:43:28.981853 <6>[ 2.378265] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10648 23:43:28.988637 <6>[ 2.387001] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10649 23:43:28.995199 <6>[ 2.394164] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10650 23:43:29.001811 <6>[ 2.400943] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10651 23:43:29.011629 <6>[ 2.407707] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10652 23:43:29.018216 <6>[ 2.414633] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10653 23:43:29.025126 <6>[ 2.421485] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10654 23:43:29.034703 <6>[ 2.430616] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10655 23:43:29.052686 <6>[ 2.439737] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10656 23:43:29.054694 <6>[ 2.449030] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10657 23:43:29.064400 <6>[ 2.458496] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10658 23:43:29.074641 <6>[ 2.467963] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10659 23:43:29.081520 <6>[ 2.477082] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10660 23:43:29.091083 <6>[ 2.486549] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10661 23:43:29.101043 <6>[ 2.495668] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10662 23:43:29.110790 <6>[ 2.504962] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10663 23:43:29.120914 <6>[ 2.515125] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10664 23:43:29.131592 <6>[ 2.527031] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10665 23:43:29.138016 <6>[ 2.536543] Trying to probe devices needed for running init ...
10666 23:43:29.178720 <6>[ 2.574469] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10667 23:43:29.332103 <6>[ 2.731117] hub 1-1:1.0: USB hub found
10668 23:43:29.335554 <6>[ 2.735546] hub 1-1:1.0: 4 ports detected
10669 23:43:29.344661 <6>[ 2.743570] hub 1-1:1.0: USB hub found
10670 23:43:29.347521 <6>[ 2.748008] hub 1-1:1.0: 4 ports detected
10671 23:43:29.458858 <6>[ 2.854793] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10672 23:43:29.485413 <6>[ 2.884499] hub 2-1:1.0: USB hub found
10673 23:43:29.488665 <6>[ 2.889032] hub 2-1:1.0: 3 ports detected
10674 23:43:29.498301 <6>[ 2.897181] hub 2-1:1.0: USB hub found
10675 23:43:29.501094 <6>[ 2.901683] hub 2-1:1.0: 3 ports detected
10676 23:43:29.674386 <6>[ 3.070502] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10677 23:43:29.806480 <6>[ 3.205898] hub 1-1.4:1.0: USB hub found
10678 23:43:29.809806 <6>[ 3.210523] hub 1-1.4:1.0: 2 ports detected
10679 23:43:29.818596 <6>[ 3.217811] hub 1-1.4:1.0: USB hub found
10680 23:43:29.821782 <6>[ 3.222369] hub 1-1.4:1.0: 2 ports detected
10681 23:43:29.890369 <6>[ 3.286609] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10682 23:43:29.999264 <6>[ 3.395138] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10683 23:43:30.035820 <4>[ 3.431802] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10684 23:43:30.045321 <4>[ 3.440923] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10685 23:43:30.084788 <6>[ 3.483912] r8152 2-1.3:1.0 eth0: v1.12.13
10686 23:43:30.118380 <6>[ 3.514502] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10687 23:43:30.310691 <6>[ 3.706518] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10688 23:43:31.839457 <6>[ 5.238587] r8152 2-1.3:1.0 eth0: carrier on
10689 23:43:34.182498 <5>[ 5.262243] Sending DHCP requests .., OK
10690 23:43:34.188979 <6>[ 7.586744] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10691 23:43:34.192835 <6>[ 7.595025] IP-Config: Complete:
10692 23:43:34.205769 <6>[ 7.598516] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10693 23:43:34.212746 <6>[ 7.609238] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10694 23:43:34.219102 <6>[ 7.617850] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10695 23:43:34.226007 <6>[ 7.617858] nameserver0=192.168.201.1
10696 23:43:34.229203 <6>[ 7.629947] clk: Disabling unused clocks
10697 23:43:34.232808 <6>[ 7.635105] ALSA device list:
10698 23:43:34.238746 <6>[ 7.638451] No soundcards found.
10699 23:43:34.245734 <6>[ 7.645763] Freeing unused kernel memory: 8512K
10700 23:43:34.249446 <6>[ 7.650777] Run /init as init process
10701 23:43:34.260496 Loading, please wait...
10702 23:43:34.287775 Starting systemd-udevd version 252.22-1~deb12u1
10703 23:43:34.551687 <6>[ 7.947819] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10704 23:43:34.561368 <6>[ 7.956540] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10705 23:43:34.568239 <6>[ 7.962805] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10706 23:43:34.577727 <6>[ 7.966643] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10707 23:43:34.581588 <6>[ 7.977611] remoteproc remoteproc0: scp is available
10708 23:43:34.588084 <6>[ 7.986794] remoteproc remoteproc0: powering up scp
10709 23:43:34.594608 <6>[ 7.991944] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10710 23:43:34.601175 <6>[ 8.000468] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10711 23:43:34.604314 <6>[ 8.000906] mc: Linux media interface: v0.10
10712 23:43:34.614249 <3>[ 8.001019] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10713 23:43:34.621145 <3>[ 8.001034] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10714 23:43:34.630982 <3>[ 8.001042] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 23:43:34.637586 <3>[ 8.001123] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 23:43:34.647280 <3>[ 8.001134] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 23:43:34.653988 <3>[ 8.001142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 23:43:34.664154 <3>[ 8.001153] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 23:43:34.670582 <3>[ 8.001162] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 23:43:34.677192 <3>[ 8.001213] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 23:43:34.687226 <3>[ 8.010495] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 23:43:34.694197 <6>[ 8.039086] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10723 23:43:34.703923 <3>[ 8.043074] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 23:43:34.710987 <3>[ 8.043079] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 23:43:34.717771 <4>[ 8.058413] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10726 23:43:34.724105 <6>[ 8.061790] videodev: Linux video capture interface: v2.00
10727 23:43:34.733432 <3>[ 8.068260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 23:43:34.739969 <4>[ 8.069421] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10729 23:43:34.747145 <4>[ 8.069421] Fallback method does not support PEC.
10730 23:43:34.753519 <4>[ 8.076099] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10731 23:43:34.760132 <3>[ 8.083613] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 23:43:34.769902 <3>[ 8.083625] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 23:43:34.777080 <3>[ 8.083630] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 23:43:34.786628 <3>[ 8.083636] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 23:43:34.793495 <3>[ 8.083700] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10736 23:43:34.802903 <3>[ 8.086386] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10737 23:43:34.809700 <6>[ 8.105715] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10738 23:43:34.816951 <6>[ 8.131308] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10739 23:43:34.823618 <6>[ 8.131372] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10740 23:43:34.829775 <6>[ 8.131380] remoteproc remoteproc0: remote processor scp is now up
10741 23:43:34.836884 <6>[ 8.137091] pci_bus 0000:00: root bus resource [bus 00-ff]
10742 23:43:34.846288 <6>[ 8.159202] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10743 23:43:34.853310 <6>[ 8.165987] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10744 23:43:34.860208 <6>[ 8.177243] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10745 23:43:34.869624 <6>[ 8.182295] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10746 23:43:34.879956 <6>[ 8.190328] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10747 23:43:34.886130 <6>[ 8.198533] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10748 23:43:34.896097 <6>[ 8.202904] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10749 23:43:34.906085 <6>[ 8.207795] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10750 23:43:34.912792 <6>[ 8.214066] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10751 23:43:34.916051 <6>[ 8.214150] pci 0000:00:00.0: supports D1 D2
10752 23:43:34.925442 <3>[ 8.222278] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10753 23:43:34.932332 <6>[ 8.229647] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10754 23:43:34.935650 <6>[ 8.242638] Bluetooth: Core ver 2.22
10755 23:43:34.945688 <6>[ 8.251494] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10756 23:43:34.948852 <6>[ 8.257323] NET: Registered PF_BLUETOOTH protocol family
10757 23:43:34.955138 <6>[ 8.265633] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10758 23:43:34.961777 <6>[ 8.275392] Bluetooth: HCI device and connection manager initialized
10759 23:43:34.971859 <6>[ 8.285473] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10760 23:43:34.978434 <6>[ 8.286709] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10761 23:43:34.991512 <6>[ 8.288564] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10762 23:43:34.995094 <6>[ 8.288673] usbcore: registered new interface driver uvcvideo
10763 23:43:35.001335 <6>[ 8.291804] Bluetooth: HCI socket layer initialized
10764 23:43:35.008072 <6>[ 8.301017] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10765 23:43:35.015002 <6>[ 8.301032] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10766 23:43:35.021472 <6>[ 8.310066] Bluetooth: L2CAP socket layer initialized
10767 23:43:35.024924 <6>[ 8.317644] pci 0000:01:00.0: supports D1 D2
10768 23:43:35.031326 <6>[ 8.322067] Bluetooth: SCO socket layer initialized
10769 23:43:35.037898 <6>[ 8.322596] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10770 23:43:35.044485 <6>[ 8.330827] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10771 23:43:35.051034 <6>[ 8.395572] usbcore: registered new interface driver btusb
10772 23:43:35.060792 <4>[ 8.396478] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10773 23:43:35.067566 <3>[ 8.396490] Bluetooth: hci0: Failed to load firmware file (-2)
10774 23:43:35.073992 <3>[ 8.396494] Bluetooth: hci0: Failed to set up firmware (-2)
10775 23:43:35.084193 <4>[ 8.396499] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10776 23:43:35.090572 <6>[ 8.410336] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10777 23:43:35.097927 <6>[ 8.494953] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10778 23:43:35.107537 <6>[ 8.503037] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10779 23:43:35.113795 <6>[ 8.511033] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10780 23:43:35.120729 <6>[ 8.519034] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10781 23:43:35.130378 <6>[ 8.527036] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10782 23:43:35.134018 <6>[ 8.535040] pci 0000:00:00.0: PCI bridge to [bus 01]
10783 23:43:35.143920 <6>[ 8.540258] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10784 23:43:35.149937 <6>[ 8.548405] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10785 23:43:35.156863 <6>[ 8.555251] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10786 23:43:35.163344 <6>[ 8.561648] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10787 23:43:35.178664 <5>[ 8.575531] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10788 23:43:35.204650 <5>[ 8.601356] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10789 23:43:35.211162 <5>[ 8.608475] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10790 23:43:35.221045 <4>[ 8.616903] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10791 23:43:35.224541 <6>[ 8.625788] cfg80211: failed to load regulatory.db
10792 23:43:35.275156 <6>[ 8.671786] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10793 23:43:35.281514 <6>[ 8.679296] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10794 23:43:35.305816 <6>[ 8.706019] mt7921e 0000:01:00.0: ASIC revision: 79610010
10795 23:43:35.409981 <6>[ 8.806293] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10796 23:43:35.412699 <6>[ 8.806293]
10797 23:43:35.439976 Begin: Loading essential drivers ... done.
10798 23:43:35.442808 Begin: Running /scripts/init-premount ... done.
10799 23:43:35.450068 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10800 23:43:35.459557 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10801 23:43:35.462551 Device /sys/class/net/eth0 found
10802 23:43:35.462639 done.
10803 23:43:35.473146 Begin: Waiting up to 180 secs for any network device to become available ... done.
10804 23:43:35.515094 IP-Config: eth0 hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10805 23:43:35.523491 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10806 23:43:35.530246 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10807 23:43:35.536613 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10808 23:43:35.543382 host : mt8192-asurada-spherion-r0-cbg-2
10809 23:43:35.549701 domain : lava-rack
10810 23:43:35.553064 rootserver: 192.168.201.1 rootpath:
10811 23:43:35.556807 filename :
10812 23:43:35.681040 <6>[ 9.077452] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10813 23:43:35.681226 done.
10814 23:43:35.691201 Begin: Running /scripts/nfs-bottom ... done.
10815 23:43:35.705950 Begin: Running /scripts/init-bottom ... done.
10816 23:43:37.055970 <6>[ 10.456340] NET: Registered PF_INET6 protocol family
10817 23:43:37.063263 <6>[ 10.463411] Segment Routing with IPv6
10818 23:43:37.066545 <6>[ 10.467394] In-situ OAM (IOAM) with IPv6
10819 23:43:37.239628 <30>[ 10.613505] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10820 23:43:37.246507 <30>[ 10.646665] systemd[1]: Detected architecture arm64.
10821 23:43:37.255798
10822 23:43:37.258946 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10823 23:43:37.259031
10824 23:43:37.284003 <30>[ 10.684192] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10825 23:43:38.284022 <30>[ 11.680670] systemd[1]: Queued start job for default target graphical.target.
10826 23:43:38.322643 <30>[ 11.719608] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10827 23:43:38.329031 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10828 23:43:38.351080 <30>[ 11.748283] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10829 23:43:38.361142 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10830 23:43:38.379440 <30>[ 11.776237] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10831 23:43:38.388907 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10832 23:43:38.408032 <30>[ 11.804658] systemd[1]: Created slice user.slice - User and Session Slice.
10833 23:43:38.414155 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10834 23:43:38.437805 <30>[ 11.831260] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10835 23:43:38.447601 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10836 23:43:38.464981 <30>[ 11.858800] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10837 23:43:38.471310 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10838 23:43:38.500199 <30>[ 11.887154] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10839 23:43:38.510463 <30>[ 11.907055] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10840 23:43:38.516867 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10841 23:43:38.533654 <30>[ 11.930864] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10842 23:43:38.540648 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10843 23:43:38.562507 <30>[ 11.958908] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10844 23:43:38.571750 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10845 23:43:38.586715 <30>[ 11.987033] systemd[1]: Reached target paths.target - Path Units.
10846 23:43:38.596803 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10847 23:43:38.614311 <30>[ 12.010956] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10848 23:43:38.620302 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10849 23:43:38.634238 <30>[ 12.034464] systemd[1]: Reached target slices.target - Slice Units.
10850 23:43:38.644115 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10851 23:43:38.658592 <30>[ 12.058971] systemd[1]: Reached target swap.target - Swaps.
10852 23:43:38.665511 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10853 23:43:38.686369 <30>[ 12.082984] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10854 23:43:38.695982 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10855 23:43:38.715104 <30>[ 12.111966] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10856 23:43:38.725202 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10857 23:43:38.744173 <30>[ 12.140971] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10858 23:43:38.753621 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10859 23:43:38.770974 <30>[ 12.167668] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10860 23:43:38.780234 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10861 23:43:38.797714 <30>[ 12.194982] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10862 23:43:38.804283 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10863 23:43:38.823025 <30>[ 12.219741] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10864 23:43:38.832614 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10865 23:43:38.852234 <30>[ 12.249078] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10866 23:43:38.861956 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10867 23:43:38.877840 <30>[ 12.274865] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10868 23:43:38.887365 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10869 23:43:38.938215 <30>[ 12.334981] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10870 23:43:38.944373 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10871 23:43:38.957025 <30>[ 12.354098] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10872 23:43:38.963651 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10873 23:43:38.984861 <30>[ 12.381912] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10874 23:43:38.991725 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10875 23:43:39.016275 <30>[ 12.406876] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10876 23:43:39.066116 <30>[ 12.463394] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10877 23:43:39.075966 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10878 23:43:39.099370 <30>[ 12.496113] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10879 23:43:39.105461 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10880 23:43:39.130927 <30>[ 12.527901] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10881 23:43:39.137305 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10882 23:43:39.163289 <30>[ 12.560121] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10883 23:43:39.172986 Startin<6>[ 12.569571] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10884 23:43:39.179844 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10885 23:43:39.230761 <30>[ 12.627145] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10886 23:43:39.240125 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10887 23:43:39.263197 <30>[ 12.660422] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10888 23:43:39.269583 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10889 23:43:39.294897 <30>[ 12.692225] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10890 23:43:39.301686 Starting [0;1;39mmodpr<6>[ 12.702621] fuse: init (API version 7.37)
10891 23:43:39.308129 obe@loop.ser…e[0m - Load Kernel Module loop...
10892 23:43:39.334786 <30>[ 12.731935] systemd[1]: Starting systemd-journald.service - Journal Service...
10893 23:43:39.341478 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10894 23:43:39.406777 <30>[ 12.803766] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10895 23:43:39.413293 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10896 23:43:39.441295 <30>[ 12.834973] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10897 23:43:39.447799 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10898 23:43:39.472294 <30>[ 12.868700] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10899 23:43:39.482043 <3>[ 12.876879] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 23:43:39.489269 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10901 23:43:39.512955 <30>[ 12.909684] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10902 23:43:39.522483 <3>[ 12.914363] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 23:43:39.529360 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10904 23:43:39.554388 <30>[ 12.951356] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10905 23:43:39.561446 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10906 23:43:39.571976 <3>[ 12.966773] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 23:43:39.577948 <30>[ 12.976401] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10908 23:43:39.588268 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10909 23:43:39.599988 <3>[ 12.997183] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 23:43:39.609843 <30>[ 13.006834] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10911 23:43:39.616238 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10912 23:43:39.634211 <3>[ 13.031259] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 23:43:39.644016 <30>[ 13.031716] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10914 23:43:39.650687 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10915 23:43:39.666607 <3>[ 13.063660] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 23:43:39.677826 <30>[ 13.074894] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10917 23:43:39.687441 <30>[ 13.082999] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10918 23:43:39.701012 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Modu<3>[ 13.098039] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 23:43:39.704240 le configfs.
10920 23:43:39.720103 <30>[ 13.119924] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10921 23:43:39.731450 <30>[ 13.127691] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10922 23:43:39.740973 <3>[ 13.131618] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 23:43:39.746886 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10924 23:43:39.767630 <30>[ 13.164195] systemd[1]: modprobe@drm.service: Deactivated successfully.
10925 23:43:39.773955 <3>[ 13.169349] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 23:43:39.783808 <30>[ 13.172120] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10927 23:43:39.790436 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10928 23:43:39.805810 <3>[ 13.202881] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 23:43:39.816647 <30>[ 13.213691] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10930 23:43:39.826920 <30>[ 13.222115] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10931 23:43:39.840291 [[0;32m OK [0m] Finished [0;1;39mmodprobe@e<3>[ 13.234256] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 23:43:39.843664 fi_psto…m - Load Kernel Module efi_pstore.
10933 23:43:39.867550 <30>[ 13.264898] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10934 23:43:39.877681 <3>[ 13.272663] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 23:43:39.884492 <30>[ 13.273230] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10936 23:43:39.890642 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10937 23:43:39.912575 <3>[ 13.309615] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10938 23:43:39.923424 <30>[ 13.320505] systemd[1]: modprobe@loop.service: Deactivated successfully.
10939 23:43:39.930295 <30>[ 13.328862] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10940 23:43:39.939937 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10941 23:43:39.959798 <3>[ 13.356837] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 23:43:39.971462 <30>[ 13.368618] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10943 23:43:39.981150 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10944 23:43:40.006420 <30>[ 13.400282] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10945 23:43:40.013239 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10946 23:43:40.024688 <3>[ 13.421190] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10947 23:43:40.031098 <3>[ 13.421893] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10948 23:43:40.047373 <4>[ 13.430001] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10949 23:43:40.057301 <30>[ 13.438474] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10950 23:43:40.064032 <3>[ 13.453386] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10951 23:43:40.073847 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10952 23:43:40.094383 <30>[ 13.491435] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10953 23:43:40.104704 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10954 23:43:40.122734 <30>[ 13.519458] systemd[1]: Reached target network-pre.target - Preparation for Network.
10955 23:43:40.129609 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10956 23:43:40.173745 <30>[ 13.570997] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10957 23:43:40.180381 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10958 23:43:40.206138 <30>[ 13.602922] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10959 23:43:40.215487 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10960 23:43:40.240580 <30>[ 13.634664] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10961 23:43:40.257884 <30>[ 13.648312] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10962 23:43:40.294094 <30>[ 13.691155] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10963 23:43:40.300588 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10964 23:43:40.327200 <30>[ 13.721100] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10965 23:43:40.339280 <30>[ 13.736362] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10966 23:43:40.345843 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10967 23:43:40.398398 <30>[ 13.795567] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10968 23:43:40.404841 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10969 23:43:40.433728 <30>[ 13.830688] systemd[1]: Started systemd-journald.service - Journal Service.
10970 23:43:40.440083 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10971 23:43:40.459754 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10972 23:43:40.477928 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10973 23:43:40.494935 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10974 23:43:40.514795 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10975 23:43:40.534841 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10976 23:43:40.586174 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10977 23:43:40.610679 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10978 23:43:40.676209 <46>[ 14.073187] systemd-journald[306]: Received client request to flush runtime journal.
10979 23:43:40.720838 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10980 23:43:40.741601 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10981 23:43:40.757384 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10982 23:43:41.458405 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10983 23:43:42.109878 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10984 23:43:42.137833 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10985 23:43:42.248761 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10986 23:43:42.327347 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10987 23:43:42.399203 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10988 23:43:42.708321 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10989 23:43:42.722047 <6>[ 16.122994] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10990 23:43:42.732975 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10991 23:43:42.786759 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10992 23:43:42.854112 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10993 23:43:42.913782 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10994 23:43:42.935819 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10995 23:43:42.988501 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10996 23:43:43.008069 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10997 23:43:43.029758 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10998 23:43:43.050417 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10999 23:43:43.134481 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11000 23:43:43.156732 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11001 23:43:43.202814 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11002 23:43:43.290897 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11003 23:43:43.314011 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11004 23:43:43.333293 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11005 23:43:43.349277 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11006 23:43:43.373840 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11007 23:43:43.396570 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11008 23:43:43.413312 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11009 23:43:43.433091 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11010 23:43:43.452842 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11011 23:43:43.469323 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11012 23:43:43.487570 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11013 23:43:43.504821 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11014 23:43:43.521185 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11015 23:43:43.582878 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11016 23:43:43.666298 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11017 23:43:43.714710 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11018 23:43:43.739435 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11019 23:43:43.793716 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11020 23:43:43.843329 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11021 23:43:43.886612 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11022 23:43:43.905019 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11023 23:43:43.988981 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11024 23:43:44.060114 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11025 23:43:44.085059 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11026 23:43:44.109613 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11027 23:43:44.129858 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11028 23:43:44.178858 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11029 23:43:44.253756 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11030 23:43:44.321650
11031 23:43:44.325298 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11032 23:43:44.325392
11033 23:43:44.328803 debian-bookworm-arm64 login: root (automatic login)
11034 23:43:44.328883
11035 23:43:44.623664 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024 aarch64
11036 23:43:44.623836
11037 23:43:44.630154 The programs included with the Debian GNU/Linux system are free software;
11038 23:43:44.636867 the exact distribution terms for each program are described in the
11039 23:43:44.640060 individual files in /usr/share/doc/*/copyright.
11040 23:43:44.640171
11041 23:43:44.646699 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11042 23:43:44.649857 permitted by applicable law.
11043 23:43:45.687325 Matched prompt #10: / #
11045 23:43:45.687687 Setting prompt string to ['/ #']
11046 23:43:45.687785 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11048 23:43:45.687991 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11049 23:43:45.688080 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
11050 23:43:45.688152 Setting prompt string to ['/ #']
11051 23:43:45.688252 Forcing a shell prompt, looking for ['/ #']
11053 23:43:45.738519 / #
11054 23:43:45.738737 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11055 23:43:45.738850 Waiting using forced prompt support (timeout 00:02:30)
11056 23:43:45.743635
11057 23:43:45.743945 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11058 23:43:45.744073 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
11060 23:43:45.844389 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172919/extract-nfsrootfs-_tc5mk7h'
11061 23:43:45.849562 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172919/extract-nfsrootfs-_tc5mk7h'
11063 23:43:45.950082 / # export NFS_SERVER_IP='192.168.201.1'
11064 23:43:45.955483 export NFS_SERVER_IP='192.168.201.1'
11065 23:43:45.955810 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11066 23:43:45.955952 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
11067 23:43:45.956073 end: 2 depthcharge-action (duration 00:01:36) [common]
11068 23:43:45.956207 start: 3 lava-test-retry (timeout 00:07:44) [common]
11069 23:43:45.956326 start: 3.1 lava-test-shell (timeout 00:07:44) [common]
11070 23:43:45.956421 Using namespace: common
11072 23:43:46.056723 / # #
11073 23:43:46.056886 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11074 23:43:46.062343 #
11075 23:43:46.062654 Using /lava-14172919
11077 23:43:46.162975 / # export SHELL=/bin/bash
11078 23:43:46.167827 export SHELL=/bin/bash
11080 23:43:46.268394 / # . /lava-14172919/environment
11081 23:43:46.274014 . /lava-14172919/environment
11083 23:43:46.380163 / # /lava-14172919/bin/lava-test-runner /lava-14172919/0
11084 23:43:46.380331 Test shell timeout: 10s (minimum of the action and connection timeout)
11085 23:43:46.385636 /lava-14172919/bin/lava-test-runner /lava-14172919/0
11086 23:43:46.645797 + export TESTRUN_ID=0_timesync-off
11087 23:43:46.649181 + TESTRUN_ID=0_timesync-off
11088 23:43:46.652185 + cd /lava-14172919/0/tests/0_timesync-off
11089 23:43:46.655637 ++ cat uuid
11090 23:43:46.659765 + UUID=14172919_1.6.2.3.1
11091 23:43:46.659877 + set +x
11092 23:43:46.666417 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14172919_1.6.2.3.1>
11093 23:43:46.666694 Received signal: <STARTRUN> 0_timesync-off 14172919_1.6.2.3.1
11094 23:43:46.666773 Starting test lava.0_timesync-off (14172919_1.6.2.3.1)
11095 23:43:46.666871 Skipping test definition patterns.
11096 23:43:46.669134 + systemctl stop systemd-timesyncd
11097 23:43:46.754783 + set +x
11098 23:43:46.757554 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14172919_1.6.2.3.1>
11099 23:43:46.757867 Received signal: <ENDRUN> 0_timesync-off 14172919_1.6.2.3.1
11100 23:43:46.757977 Ending use of test pattern.
11101 23:43:46.758043 Ending test lava.0_timesync-off (14172919_1.6.2.3.1), duration 0.09
11103 23:43:46.835103 + export TESTRUN_ID=1_kselftest-arm64
11104 23:43:46.835281 + TESTRUN_ID=1_kselftest-arm64
11105 23:43:46.841884 + cd /lava-14172919/0/tests/1_kselftest-arm64
11106 23:43:46.842020 ++ cat uuid
11107 23:43:46.848419 + UUID=14172919_1.6.2.3.5
11108 23:43:46.848534 + set +x
11109 23:43:46.855057 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 14172919_1.6.2.3.5>
11110 23:43:46.855378 Received signal: <STARTRUN> 1_kselftest-arm64 14172919_1.6.2.3.5
11111 23:43:46.855486 Starting test lava.1_kselftest-arm64 (14172919_1.6.2.3.5)
11112 23:43:46.855605 Skipping test definition patterns.
11113 23:43:46.858546 + cd ./automated/linux/kselftest/
11114 23:43:46.884829 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11115 23:43:46.931214 INFO: install_deps skipped
11116 23:43:47.433984 --2024-06-04 23:43:47-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11117 23:43:47.440779 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11118 23:43:47.572329 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11119 23:43:47.702426 HTTP request sent, awaiting response... 200 OK
11120 23:43:47.705218 Length: 1642752 (1.6M) [application/octet-stream]
11121 23:43:47.708626 Saving to: 'kselftest_armhf.tar.gz'
11122 23:43:47.708739
11123 23:43:47.708899
11124 23:43:47.960792 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11125 23:43:48.219223 kselftest_armhf.tar 2%[ ] 47.81K 185KB/s
11126 23:43:48.524326 kselftest_armhf.tar 13%[=> ] 217.50K 421KB/s
11127 23:43:48.660618 kselftest_armhf.tar 51%[=========> ] 818.47K 996KB/s
11128 23:43:48.667396 kselftest_armhf.tar 100%[===================>] 1.57M 1.63MB/s in 1.0s
11129 23:43:48.667528
11130 23:43:48.812132 2024-06-04 23:43:48 (1.63 MB/s) - 'kselftest_armhf.tar.gz' saved [1642752/1642752]
11131 23:43:48.812316
11132 23:43:53.118324 skiplist:
11133 23:43:53.121484 ========================================
11134 23:43:53.124711 ========================================
11135 23:43:53.175280 arm64:tags_test
11136 23:43:53.178315 arm64:run_tags_test.sh
11137 23:43:53.178404 arm64:fake_sigreturn_bad_magic
11138 23:43:53.181326 arm64:fake_sigreturn_bad_size
11139 23:43:53.185071 arm64:fake_sigreturn_bad_size_for_magic0
11140 23:43:53.188069 arm64:fake_sigreturn_duplicated_fpsimd
11141 23:43:53.191227 arm64:fake_sigreturn_misaligned_sp
11142 23:43:53.194748 arm64:fake_sigreturn_missing_fpsimd
11143 23:43:53.198157 arm64:fake_sigreturn_sme_change_vl
11144 23:43:53.201192 arm64:fake_sigreturn_sve_change_vl
11145 23:43:53.204721 arm64:mangle_pstate_invalid_compat_toggle
11146 23:43:53.207733 arm64:mangle_pstate_invalid_daif_bits
11147 23:43:53.211279 arm64:mangle_pstate_invalid_mode_el1h
11148 23:43:53.214510 arm64:mangle_pstate_invalid_mode_el1t
11149 23:43:53.218011 arm64:mangle_pstate_invalid_mode_el2h
11150 23:43:53.221281 arm64:mangle_pstate_invalid_mode_el2t
11151 23:43:53.227707 arm64:mangle_pstate_invalid_mode_el3h
11152 23:43:53.231224 arm64:mangle_pstate_invalid_mode_el3t
11153 23:43:53.231339 arm64:sme_trap_no_sm
11154 23:43:53.234400 arm64:sme_trap_non_streaming
11155 23:43:53.234478 arm64:sme_trap_za
11156 23:43:53.237978 arm64:sme_vl
11157 23:43:53.238053 arm64:ssve_regs
11158 23:43:53.240725 arm64:sve_regs
11159 23:43:53.240800 arm64:sve_vl
11160 23:43:53.240861 arm64:za_no_regs
11161 23:43:53.244218 arm64:za_regs
11162 23:43:53.244321 arm64:pac
11163 23:43:53.247731 arm64:fp-stress
11164 23:43:53.247805 arm64:sve-ptrace
11165 23:43:53.251333 arm64:sve-probe-vls
11166 23:43:53.251411 arm64:vec-syscfg
11167 23:43:53.251475 arm64:za-fork
11168 23:43:53.254510 arm64:za-ptrace
11169 23:43:53.257246 arm64:check_buffer_fill
11170 23:43:53.257337 arm64:check_child_memory
11171 23:43:53.260837 arm64:check_gcr_el1_cswitch
11172 23:43:53.263921 arm64:check_ksm_options
11173 23:43:53.264011 arm64:check_mmap_options
11174 23:43:53.267059 arm64:check_prctl
11175 23:43:53.270378 arm64:check_tags_inclusion
11176 23:43:53.270461 arm64:check_user_mem
11177 23:43:53.274041 arm64:btitest
11178 23:43:53.274124 arm64:nobtitest
11179 23:43:53.274188 arm64:hwcap
11180 23:43:53.277024 arm64:ptrace
11181 23:43:53.277107 arm64:syscall-abi
11182 23:43:53.280502 arm64:tpidr2
11183 23:43:53.284179 ============== Tests to run ===============
11184 23:43:53.284268 arm64:tags_test
11185 23:43:53.287071 arm64:run_tags_test.sh
11186 23:43:53.290208 arm64:fake_sigreturn_bad_magic
11187 23:43:53.293732 arm64:fake_sigreturn_bad_size
11188 23:43:53.297079 arm64:fake_sigreturn_bad_size_for_magic0
11189 23:43:53.300467 arm64:fake_sigreturn_duplicated_fpsimd
11190 23:43:53.303304 arm64:fake_sigreturn_misaligned_sp
11191 23:43:53.307049 arm64:fake_sigreturn_missing_fpsimd
11192 23:43:53.309913 arm64:fake_sigreturn_sme_change_vl
11193 23:43:53.313305 arm64:fake_sigreturn_sve_change_vl
11194 23:43:53.316676 arm64:mangle_pstate_invalid_compat_toggle
11195 23:43:53.319746 arm64:mangle_pstate_invalid_daif_bits
11196 23:43:53.323494 arm64:mangle_pstate_invalid_mode_el1h
11197 23:43:53.326484 arm64:mangle_pstate_invalid_mode_el1t
11198 23:43:53.329801 arm64:mangle_pstate_invalid_mode_el2h
11199 23:43:53.333091 arm64:mangle_pstate_invalid_mode_el2t
11200 23:43:53.336227 arm64:mangle_pstate_invalid_mode_el3h
11201 23:43:53.339864 arm64:mangle_pstate_invalid_mode_el3t
11202 23:43:53.339972 arm64:sme_trap_no_sm
11203 23:43:53.343174 arm64:sme_trap_non_streaming
11204 23:43:53.346358 arm64:sme_trap_za
11205 23:43:53.346433 arm64:sme_vl
11206 23:43:53.349434 arm64:ssve_regs
11207 23:43:53.349538 arm64:sve_regs
11208 23:43:53.349628 arm64:sve_vl
11209 23:43:53.352790 arm64:za_no_regs
11210 23:43:53.352865 arm64:za_regs
11211 23:43:53.352928 arm64:pac
11212 23:43:53.356589 arm64:fp-stress
11213 23:43:53.356693 arm64:sve-ptrace
11214 23:43:53.359455 arm64:sve-probe-vls
11215 23:43:53.359556 arm64:vec-syscfg
11216 23:43:53.363246 arm64:za-fork
11217 23:43:53.363350 arm64:za-ptrace
11218 23:43:53.366264 arm64:check_buffer_fill
11219 23:43:53.369848 arm64:check_child_memory
11220 23:43:53.369919 arm64:check_gcr_el1_cswitch
11221 23:43:53.372786 arm64:check_ksm_options
11222 23:43:53.376296 arm64:check_mmap_options
11223 23:43:53.376401 arm64:check_prctl
11224 23:43:53.379170 arm64:check_tags_inclusion
11225 23:43:53.382684 arm64:check_user_mem
11226 23:43:53.382754 arm64:btitest
11227 23:43:53.382814 arm64:nobtitest
11228 23:43:53.386200 arm64:hwcap
11229 23:43:53.386295 arm64:ptrace
11230 23:43:53.389184 arm64:syscall-abi
11231 23:43:53.389284 arm64:tpidr2
11232 23:43:53.393221 ===========End Tests to run ===============
11233 23:43:53.395557 shardfile-arm64 pass
11234 23:43:53.625124 <12>[ 27.026837] kselftest: Running tests in arm64
11235 23:43:53.635718 TAP version 13
11236 23:43:53.649918 1..48
11237 23:43:53.668681 # selftests: arm64: tags_test
11238 23:43:54.128539 ok 1 selftests: arm64: tags_test
11239 23:43:54.150712 # selftests: arm64: run_tags_test.sh
11240 23:43:54.207790 # --------------------
11241 23:43:54.211018 # running tags test
11242 23:43:54.211104 # --------------------
11243 23:43:54.214542 # [PASS]
11244 23:43:54.217643 ok 2 selftests: arm64: run_tags_test.sh
11245 23:43:54.232146 # selftests: arm64: fake_sigreturn_bad_magic
11246 23:43:54.297875 # Registered handlers for all signals.
11247 23:43:54.298026 # Detected MINSTKSIGSZ:4720
11248 23:43:54.300973 # Testcase initialized.
11249 23:43:54.304135 # uc context validated.
11250 23:43:54.307755 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11251 23:43:54.311036 # Handled SIG_COPYCTX
11252 23:43:54.311117 # Available space:3568
11253 23:43:54.317387 # Using badly built context - ERR: BAD MAGIC !
11254 23:43:54.324186 # SIG_OK -- SP:0xFFFFFE79F760 si_addr@:0xfffffe79f760 si_code:2 token@:0xfffffe79e500 offset:-4704
11255 23:43:54.327461 # ==>> completed. PASS(1)
11256 23:43:54.333846 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11257 23:43:54.340431 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFFE79E500
11258 23:43:54.347436 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11259 23:43:54.350321 # selftests: arm64: fake_sigreturn_bad_size
11260 23:43:54.389048 # Registered handlers for all signals.
11261 23:43:54.389157 # Detected MINSTKSIGSZ:4720
11262 23:43:54.392654 # Testcase initialized.
11263 23:43:54.395693 # uc context validated.
11264 23:43:54.399897 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11265 23:43:54.402249 # Handled SIG_COPYCTX
11266 23:43:54.402331 # Available space:3568
11267 23:43:54.406244 # uc context validated.
11268 23:43:54.412227 # Using badly built context - ERR: Bad size for esr_context
11269 23:43:54.419328 # SIG_OK -- SP:0xFFFFECBDBA70 si_addr@:0xffffecbdba70 si_code:2 token@:0xffffecbda810 offset:-4704
11270 23:43:54.422553 # ==>> completed. PASS(1)
11271 23:43:54.428755 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11272 23:43:54.435745 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFECBDA810
11273 23:43:54.438720 ok 4 selftests: arm64: fake_sigreturn_bad_size
11274 23:43:54.445417 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11275 23:43:54.469995 # Registered handlers for all signals.
11276 23:43:54.470093 # Detected MINSTKSIGSZ:4720
11277 23:43:54.473067 # Testcase initialized.
11278 23:43:54.475945 # uc context validated.
11279 23:43:54.479792 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11280 23:43:54.482600 # Handled SIG_COPYCTX
11281 23:43:54.482682 # Available space:3568
11282 23:43:54.489472 # Using badly built context - ERR: Bad size for terminator
11283 23:43:54.499291 # SIG_OK -- SP:0xFFFFCDE625A0 si_addr@:0xffffcde625a0 si_code:2 token@:0xffffcde61340 offset:-4704
11284 23:43:54.499377 # ==>> completed. PASS(1)
11285 23:43:54.509230 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11286 23:43:54.515803 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCDE61340
11287 23:43:54.518822 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11288 23:43:54.525764 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11289 23:43:54.543887 # Registered handlers for all signals.
11290 23:43:54.543980 # Detected MINSTKSIGSZ:4720
11291 23:43:54.547436 # Testcase initialized.
11292 23:43:54.550301 # uc context validated.
11293 23:43:54.553705 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11294 23:43:54.557234 # Handled SIG_COPYCTX
11295 23:43:54.557355 # Available space:3568
11296 23:43:54.563773 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11297 23:43:54.573679 # SIG_OK -- SP:0xFFFFC7B6AA40 si_addr@:0xffffc7b6aa40 si_code:2 token@:0xffffc7b697e0 offset:-4704
11298 23:43:54.573766 # ==>> completed. PASS(1)
11299 23:43:54.583665 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11300 23:43:54.589751 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC7B697E0
11301 23:43:54.593504 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11302 23:43:54.596612 # selftests: arm64: fake_sigreturn_misaligned_sp
11303 23:43:54.615190 # Registered handlers for all signals.
11304 23:43:54.615308 # Detected MINSTKSIGSZ:4720
11305 23:43:54.617897 # Testcase initialized.
11306 23:43:54.621332 # uc context validated.
11307 23:43:54.624796 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11308 23:43:54.628027 # Handled SIG_COPYCTX
11309 23:43:54.634367 # SIG_OK -- SP:0xFFFFF22859B3 si_addr@:0xfffff22859b3 si_code:2 token@:0xfffff22859b3 offset:0
11310 23:43:54.638044 # ==>> completed. PASS(1)
11311 23:43:54.644657 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11312 23:43:54.651476 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF22859B3
11313 23:43:54.658144 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11314 23:43:54.660686 # selftests: arm64: fake_sigreturn_missing_fpsimd
11315 23:43:54.701782 # Registered handlers for all signals.
11316 23:43:54.701874 # Detected MINSTKSIGSZ:4720
11317 23:43:54.704961 # Testcase initialized.
11318 23:43:54.708602 # uc context validated.
11319 23:43:54.711339 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11320 23:43:54.714678 # Handled SIG_COPYCTX
11321 23:43:54.718280 # Mangling template header. Spare space:4096
11322 23:43:54.721600 # Using badly built context - ERR: Missing FPSIMD
11323 23:43:54.731391 # SIG_OK -- SP:0xFFFFD9A64890 si_addr@:0xffffd9a64890 si_code:2 token@:0xffffd9a63630 offset:-4704
11324 23:43:54.734965 # ==>> completed. PASS(1)
11325 23:43:54.741051 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11326 23:43:54.748169 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD9A63630
11327 23:43:54.750900 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11328 23:43:54.757953 # selftests: arm64: fake_sigreturn_sme_change_vl
11329 23:43:54.789516 # Registered handlers for all signals.
11330 23:43:54.789607 # Detected MINSTKSIGSZ:4720
11331 23:43:54.793277 # ==>> completed. SKIP.
11332 23:43:54.799815 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11333 23:43:54.802882 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11334 23:43:54.810860 # selftests: arm64: fake_sigreturn_sve_change_vl
11335 23:43:54.861094 # Registered handlers for all signals.
11336 23:43:54.861233 # Detected MINSTKSIGSZ:4720
11337 23:43:54.864275 # ==>> completed. SKIP.
11338 23:43:54.870997 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11339 23:43:54.873963 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11340 23:43:54.880596 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11341 23:43:54.938969 # Registered handlers for all signals.
11342 23:43:54.939077 # Detected MINSTKSIGSZ:4720
11343 23:43:54.942911 # Testcase initialized.
11344 23:43:54.945545 # uc context validated.
11345 23:43:54.945626 # Handled SIG_TRIG
11346 23:43:54.955534 # SIG_OK -- SP:0xFFFFF3792820 si_addr@:0xfffff3792820 si_code:2 token@:(nil) offset:-281474766546976
11347 23:43:54.959076 # ==>> completed. PASS(1)
11348 23:43:54.965763 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11349 23:43:54.972410 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11350 23:43:54.975145 # selftests: arm64: mangle_pstate_invalid_daif_bits
11351 23:43:55.010203 # Registered handlers for all signals.
11352 23:43:55.010338 # Detected MINSTKSIGSZ:4720
11353 23:43:55.013712 # Testcase initialized.
11354 23:43:55.016642 # uc context validated.
11355 23:43:55.016744 # Handled SIG_TRIG
11356 23:43:55.026362 # SIG_OK -- SP:0xFFFFE4C6E8D0 si_addr@:0xffffe4c6e8d0 si_code:2 token@:(nil) offset:-281474519984336
11357 23:43:55.030013 # ==>> completed. PASS(1)
11358 23:43:55.036555 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11359 23:43:55.040049 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11360 23:43:55.046372 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11361 23:43:55.110093 # Registered handlers for all signals.
11362 23:43:55.110226 # Detected MINSTKSIGSZ:4720
11363 23:43:55.113274 # Testcase initialized.
11364 23:43:55.117068 # uc context validated.
11365 23:43:55.117162 # Handled SIG_TRIG
11366 23:43:55.126632 # SIG_OK -- SP:0xFFFFEB013C60 si_addr@:0xffffeb013c60 si_code:2 token@:(nil) offset:-281474624470112
11367 23:43:55.129981 # ==>> completed. PASS(1)
11368 23:43:55.136646 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11369 23:43:55.140206 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11370 23:43:55.146473 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11371 23:43:55.189195 # Registered handlers for all signals.
11372 23:43:55.189385 # Detected MINSTKSIGSZ:4720
11373 23:43:55.192687 # Testcase initialized.
11374 23:43:55.196034 # uc context validated.
11375 23:43:55.196147 # Handled SIG_TRIG
11376 23:43:55.206192 # SIG_OK -- SP:0xFFFFFD83FA40 si_addr@:0xfffffd83fa40 si_code:2 token@:(nil) offset:-281474935028288
11377 23:43:55.209480 # ==>> completed. PASS(1)
11378 23:43:55.216286 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11379 23:43:55.219353 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11380 23:43:55.225798 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11381 23:43:55.287434 # Registered handlers for all signals.
11382 23:43:55.287572 # Detected MINSTKSIGSZ:4720
11383 23:43:55.291188 # Testcase initialized.
11384 23:43:55.294253 # uc context validated.
11385 23:43:55.294333 # Handled SIG_TRIG
11386 23:43:55.303871 # SIG_OK -- SP:0xFFFFE89C7350 si_addr@:0xffffe89c7350 si_code:2 token@:(nil) offset:-281474584310608
11387 23:43:55.307539 # ==>> completed. PASS(1)
11388 23:43:55.313759 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11389 23:43:55.317308 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11390 23:43:55.323583 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11391 23:43:55.373031 # Registered handlers for all signals.
11392 23:43:55.373187 # Detected MINSTKSIGSZ:4720
11393 23:43:55.375919 # Testcase initialized.
11394 23:43:55.379211 # uc context validated.
11395 23:43:55.379290 # Handled SIG_TRIG
11396 23:43:55.389280 # SIG_OK -- SP:0xFFFFE3CAD2C0 si_addr@:0xffffe3cad2c0 si_code:2 token@:(nil) offset:-281474503463616
11397 23:43:55.392549 # ==>> completed. PASS(1)
11398 23:43:55.398923 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11399 23:43:55.402402 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11400 23:43:55.408811 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11401 23:43:55.443746 # Registered handlers for all signals.
11402 23:43:55.443927 # Detected MINSTKSIGSZ:4720
11403 23:43:55.447066 # Testcase initialized.
11404 23:43:55.450472 # uc context validated.
11405 23:43:55.450561 # Handled SIG_TRIG
11406 23:43:55.460124 # SIG_OK -- SP:0xFFFFCACE04A0 si_addr@:0xffffcace04a0 si_code:2 token@:(nil) offset:-281474084242592
11407 23:43:55.463779 # ==>> completed. PASS(1)
11408 23:43:55.469742 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11409 23:43:55.473712 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11410 23:43:55.480226 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11411 23:43:55.530395 # Registered handlers for all signals.
11412 23:43:55.530529 # Detected MINSTKSIGSZ:4720
11413 23:43:55.533738 # Testcase initialized.
11414 23:43:55.537231 # uc context validated.
11415 23:43:55.537359 # Handled SIG_TRIG
11416 23:43:55.546720 # SIG_OK -- SP:0xFFFFCC918A90 si_addr@:0xffffcc918a90 si_code:2 token@:(nil) offset:-281474113833616
11417 23:43:55.550129 # ==>> completed. PASS(1)
11418 23:43:55.557166 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11419 23:43:55.560271 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11420 23:43:55.563188 # selftests: arm64: sme_trap_no_sm
11421 23:43:55.623271 # Registered handlers for all signals.
11422 23:43:55.623435 # Detected MINSTKSIGSZ:4720
11423 23:43:55.626579 # ==>> completed. SKIP.
11424 23:43:55.636455 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11425 23:43:55.639691 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11426 23:43:55.642652 # selftests: arm64: sme_trap_non_streaming
11427 23:43:55.720129 # Registered handlers for all signals.
11428 23:43:55.720280 # Detected MINSTKSIGSZ:4720
11429 23:43:55.723626 # ==>> completed. SKIP.
11430 23:43:55.733623 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11431 23:43:55.740149 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11432 23:43:55.743335 # selftests: arm64: sme_trap_za
11433 23:43:55.807446 # Registered handlers for all signals.
11434 23:43:55.807584 # Detected MINSTKSIGSZ:4720
11435 23:43:55.810763 # Testcase initialized.
11436 23:43:55.820859 # SIG_OK -- SP:0xFFFFC1241350 si_addr@:0xaaaae8872510 si_code:1 token@:(nil) offset:-187651022333200
11437 23:43:55.820961 # ==>> completed. PASS(1)
11438 23:43:55.830704 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11439 23:43:55.834324 ok 21 selftests: arm64: sme_trap_za
11440 23:43:55.834419 # selftests: arm64: sme_vl
11441 23:43:55.895804 # Registered handlers for all signals.
11442 23:43:55.895961 # Detected MINSTKSIGSZ:4720
11443 23:43:55.899300 # ==>> completed. SKIP.
11444 23:43:55.905612 # # SME VL :: Check that we get the right SME VL reported
11445 23:43:55.909141 ok 22 selftests: arm64: sme_vl # SKIP
11446 23:43:55.914658 # selftests: arm64: ssve_regs
11447 23:43:55.974351 # Registered handlers for all signals.
11448 23:43:55.974487 # Detected MINSTKSIGSZ:4720
11449 23:43:55.977700 # ==>> completed. SKIP.
11450 23:43:55.983984 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11451 23:43:55.990539 ok 23 selftests: arm64: ssve_regs # SKIP
11452 23:43:55.994061 # selftests: arm64: sve_regs
11453 23:43:56.061513 # Registered handlers for all signals.
11454 23:43:56.061666 # Detected MINSTKSIGSZ:4720
11455 23:43:56.064236 # ==>> completed. SKIP.
11456 23:43:56.070851 # # SVE registers :: Check that we get the right SVE registers reported
11457 23:43:56.074346 ok 24 selftests: arm64: sve_regs # SKIP
11458 23:43:56.079160 # selftests: arm64: sve_vl
11459 23:43:56.139008 # Registered handlers for all signals.
11460 23:43:56.139146 # Detected MINSTKSIGSZ:4720
11461 23:43:56.142301 # ==>> completed. SKIP.
11462 23:43:56.148695 # # SVE VL :: Check that we get the right SVE VL reported
11463 23:43:56.152219 ok 25 selftests: arm64: sve_vl # SKIP
11464 23:43:56.156952 # selftests: arm64: za_no_regs
11465 23:43:56.218378 # Registered handlers for all signals.
11466 23:43:56.218515 # Detected MINSTKSIGSZ:4720
11467 23:43:56.221706 # ==>> completed. SKIP.
11468 23:43:56.228328 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11469 23:43:56.231453 ok 26 selftests: arm64: za_no_regs # SKIP
11470 23:43:56.236874 # selftests: arm64: za_regs
11471 23:43:56.309087 # Registered handlers for all signals.
11472 23:43:56.309224 # Detected MINSTKSIGSZ:4720
11473 23:43:56.312636 # ==>> completed. SKIP.
11474 23:43:56.318797 # # ZA register :: Check that we get the right ZA registers reported
11475 23:43:56.322153 ok 27 selftests: arm64: za_regs # SKIP
11476 23:43:56.325167 # selftests: arm64: pac
11477 23:43:56.385458 # TAP version 13
11478 23:43:56.385601 # 1..7
11479 23:43:56.388582 # # Starting 7 tests from 1 test cases.
11480 23:43:56.391950 # # RUN global.corrupt_pac ...
11481 23:43:56.395040 # # SKIP PAUTH not enabled
11482 23:43:56.398560 # # OK global.corrupt_pac
11483 23:43:56.402058 # ok 1 # SKIP PAUTH not enabled
11484 23:43:56.408228 # # RUN global.pac_instructions_not_nop ...
11485 23:43:56.411937 # # SKIP PAUTH not enabled
11486 23:43:56.414735 # # OK global.pac_instructions_not_nop
11487 23:43:56.418333 # ok 2 # SKIP PAUTH not enabled
11488 23:43:56.425213 # # RUN global.pac_instructions_not_nop_generic ...
11489 23:43:56.428062 # # SKIP Generic PAUTH not enabled
11490 23:43:56.431273 # # OK global.pac_instructions_not_nop_generic
11491 23:43:56.438121 # ok 3 # SKIP Generic PAUTH not enabled
11492 23:43:56.441806 # # RUN global.single_thread_different_keys ...
11493 23:43:56.444523 # # SKIP PAUTH not enabled
11494 23:43:56.450986 # # OK global.single_thread_different_keys
11495 23:43:56.451111 # ok 4 # SKIP PAUTH not enabled
11496 23:43:56.457918 # # RUN global.exec_changed_keys ...
11497 23:43:56.461281 # # SKIP PAUTH not enabled
11498 23:43:56.464213 # # OK global.exec_changed_keys
11499 23:43:56.467802 # ok 5 # SKIP PAUTH not enabled
11500 23:43:56.471035 # # RUN global.context_switch_keep_keys ...
11501 23:43:56.474274 # # SKIP PAUTH not enabled
11502 23:43:56.480862 # # OK global.context_switch_keep_keys
11503 23:43:56.484202 # ok 6 # SKIP PAUTH not enabled
11504 23:43:56.487460 # # RUN global.context_switch_keep_keys_generic ...
11505 23:43:56.490934 # # SKIP Generic PAUTH not enabled
11506 23:43:56.497190 # # OK global.context_switch_keep_keys_generic
11507 23:43:56.500945 # ok 7 # SKIP Generic PAUTH not enabled
11508 23:43:56.504396 # # PASSED: 7 / 7 tests passed.
11509 23:43:56.507461 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11510 23:43:56.510585 ok 28 selftests: arm64: pac
11511 23:43:56.513697 # selftests: arm64: fp-stress
11512 23:44:04.560026 <6>[ 37.966422] vpu: disabling
11513 23:44:04.563353 <6>[ 37.969473] vproc2: disabling
11514 23:44:04.566786 <6>[ 37.972750] vproc1: disabling
11515 23:44:04.570110 <6>[ 37.976161] vaud18: disabling
11516 23:44:04.576309 <6>[ 37.979599] vsram_others: disabling
11517 23:44:04.579522 <6>[ 37.983500] va09: disabling
11518 23:44:04.582791 <6>[ 37.986620] vsram_md: disabling
11519 23:44:04.586259 <6>[ 37.990120] Vgpu: disabling
11520 23:44:06.463120 # TAP version 13
11521 23:44:06.463291 # 1..16
11522 23:44:06.466768 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11523 23:44:06.466880 # # Will run for 10s
11524 23:44:06.469959 # # Started FPSIMD-0-0
11525 23:44:06.473412 # # Started FPSIMD-0-1
11526 23:44:06.473521 # # Started FPSIMD-1-0
11527 23:44:06.476302 # # Started FPSIMD-1-1
11528 23:44:06.479811 # # Started FPSIMD-2-0
11529 23:44:06.479919 # # Started FPSIMD-2-1
11530 23:44:06.483347 # # Started FPSIMD-3-0
11531 23:44:06.486225 # # Started FPSIMD-3-1
11532 23:44:06.486334 # # Started FPSIMD-4-0
11533 23:44:06.489327 # # Started FPSIMD-4-1
11534 23:44:06.489435 # # Started FPSIMD-5-0
11535 23:44:06.493059 # # Started FPSIMD-5-1
11536 23:44:06.496342 # # Started FPSIMD-6-0
11537 23:44:06.496459 # # Started FPSIMD-6-1
11538 23:44:06.499536 # # Started FPSIMD-7-0
11539 23:44:06.502744 # # Started FPSIMD-7-1
11540 23:44:06.506154 # # FPSIMD-1-1: Vector length: 128 bits
11541 23:44:06.506269 # # FPSIMD-1-1: PID: 1168
11542 23:44:06.509914 # # FPSIMD-1-0: Vector length: 128 bits
11543 23:44:06.512588 # # FPSIMD-1-0: PID: 1167
11544 23:44:06.516236 # # FPSIMD-2-1: Vector length: 128 bits
11545 23:44:06.519632 # # FPSIMD-2-1: PID: 1170
11546 23:44:06.522778 # # FPSIMD-0-0: Vector length: 128 bits
11547 23:44:06.526222 # # FPSIMD-0-0: PID: 1165
11548 23:44:06.529210 # # FPSIMD-0-1: Vector length: 128 bits
11549 23:44:06.529347 # # FPSIMD-0-1: PID: 1166
11550 23:44:06.536181 # # FPSIMD-3-1: Vector length: 128 bits
11551 23:44:06.536298 # # FPSIMD-3-1: PID: 1172
11552 23:44:06.539001 # # FPSIMD-3-0: Vector length: 128 bits
11553 23:44:06.542616 # # FPSIMD-3-0: PID: 1171
11554 23:44:06.545943 # # FPSIMD-4-0: Vector length: 128 bits
11555 23:44:06.548803 # # FPSIMD-4-0: PID: 1173
11556 23:44:06.552316 # # FPSIMD-5-0: Vector length: 128 bits
11557 23:44:06.555994 # # FPSIMD-5-0: PID: 1175
11558 23:44:06.559029 # # FPSIMD-7-0: Vector length: 128 bits
11559 23:44:06.559147 # # FPSIMD-7-0: PID: 1179
11560 23:44:06.565644 # # FPSIMD-6-0: Vector length: 128 bits
11561 23:44:06.565771 # # FPSIMD-6-0: PID: 1177
11562 23:44:06.568654 # # FPSIMD-4-1: Vector length: 128 bits
11563 23:44:06.572149 # # FPSIMD-4-1: PID: 1174
11564 23:44:06.575654 # # FPSIMD-6-1: Vector length: 128 bits
11565 23:44:06.579131 # # FPSIMD-6-1: PID: 1178
11566 23:44:06.582000 # # FPSIMD-2-0: Vector length: 128 bits
11567 23:44:06.585450 # # FPSIMD-2-0: PID: 1169
11568 23:44:06.588496 # # FPSIMD-7-1: Vector length: 128 bits
11569 23:44:06.588609 # # FPSIMD-7-1: PID: 1180
11570 23:44:06.591874 # # FPSIMD-5-1: Vector length: 128 bits
11571 23:44:06.595188 # # FPSIMD-5-1: PID: 1176
11572 23:44:06.598731 # # Finishing up...
11573 23:44:06.605148 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=1207038, signals=10
11574 23:44:06.611608 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1367192, signals=10
11575 23:44:06.618080 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1063155, signals=10
11576 23:44:06.625093 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=1020775, signals=10
11577 23:44:06.634559 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1725966, signals=10
11578 23:44:06.641159 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1159579, signals=10
11579 23:44:06.647720 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1123860, signals=10
11580 23:44:06.651293 # ok 1 FPSIMD-0-0
11581 23:44:06.651412 # ok 2 FPSIMD-0-1
11582 23:44:06.651521 # ok 3 FPSIMD-1-0
11583 23:44:06.654697 # ok 4 FPSIMD-1-1
11584 23:44:06.654826 # ok 5 FPSIMD-2-0
11585 23:44:06.658249 # ok 6 FPSIMD-2-1
11586 23:44:06.658378 # ok 7 FPSIMD-3-0
11587 23:44:06.661081 # ok 8 FPSIMD-3-1
11588 23:44:06.661191 # ok 9 FPSIMD-4-0
11589 23:44:06.664924 # ok 10 FPSIMD-4-1
11590 23:44:06.667771 # ok 11 FPSIMD-5-0
11591 23:44:06.667882 # ok 12 FPSIMD-5-1
11592 23:44:06.671497 # ok 13 FPSIMD-6-0
11593 23:44:06.671614 # ok 14 FPSIMD-6-1
11594 23:44:06.674777 # ok 15 FPSIMD-7-0
11595 23:44:06.674906 # ok 16 FPSIMD-7-1
11596 23:44:06.681468 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=854424, signals=9
11597 23:44:06.687916 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1039863, signals=10
11598 23:44:06.697462 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=995064, signals=10
11599 23:44:06.704691 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=970208, signals=9
11600 23:44:06.710753 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1238987, signals=10
11601 23:44:06.717184 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=1923684, signals=10
11602 23:44:06.724156 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=1210237, signals=10
11603 23:44:06.730784 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1454609, signals=10
11604 23:44:06.740190 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=887025, signals=9
11605 23:44:06.743806 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11606 23:44:06.747135 ok 29 selftests: arm64: fp-stress
11607 23:44:06.750706 # selftests: arm64: sve-ptrace
11608 23:44:06.750820 # TAP version 13
11609 23:44:06.753500 # 1..4104
11610 23:44:06.756973 # ok 2 # SKIP SVE not available
11611 23:44:06.760230 # # Planned tests != run tests (4104 != 1)
11612 23:44:06.763425 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11613 23:44:06.766709 ok 30 selftests: arm64: sve-ptrace # SKIP
11614 23:44:06.770012 # selftests: arm64: sve-probe-vls
11615 23:44:06.773448 # TAP version 13
11616 23:44:06.773565 # 1..2
11617 23:44:06.776453 # ok 2 # SKIP SVE not available
11618 23:44:06.779966 # # Planned tests != run tests (2 != 1)
11619 23:44:06.786446 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11620 23:44:06.789393 ok 31 selftests: arm64: sve-probe-vls # SKIP
11621 23:44:06.792905 # selftests: arm64: vec-syscfg
11622 23:44:06.793015 # TAP version 13
11623 23:44:06.793116 # 1..20
11624 23:44:06.796034 # ok 1 # SKIP SVE not supported
11625 23:44:06.799509 # ok 2 # SKIP SVE not supported
11626 23:44:06.803374 # ok 3 # SKIP SVE not supported
11627 23:44:06.806267 # ok 4 # SKIP SVE not supported
11628 23:44:06.809250 # ok 5 # SKIP SVE not supported
11629 23:44:06.813147 # ok 6 # SKIP SVE not supported
11630 23:44:06.813270 # ok 7 # SKIP SVE not supported
11631 23:44:06.815764 # ok 8 # SKIP SVE not supported
11632 23:44:06.819480 # ok 9 # SKIP SVE not supported
11633 23:44:06.822350 # ok 10 # SKIP SVE not supported
11634 23:44:06.826198 # ok 11 # SKIP SME not supported
11635 23:44:06.829378 # ok 12 # SKIP SME not supported
11636 23:44:06.832679 # ok 13 # SKIP SME not supported
11637 23:44:06.835759 # ok 14 # SKIP SME not supported
11638 23:44:06.839294 # ok 15 # SKIP SME not supported
11639 23:44:06.839407 # ok 16 # SKIP SME not supported
11640 23:44:06.842259 # ok 17 # SKIP SME not supported
11641 23:44:06.845696 # ok 18 # SKIP SME not supported
11642 23:44:06.849173 # ok 19 # SKIP SME not supported
11643 23:44:06.852210 # ok 20 # SKIP SME not supported
11644 23:44:06.858897 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11645 23:44:06.859003 ok 32 selftests: arm64: vec-syscfg
11646 23:44:06.862129 # selftests: arm64: za-fork
11647 23:44:06.866104 # TAP version 13
11648 23:44:06.866189 # 1..1
11649 23:44:06.866253 # # PID: 1257
11650 23:44:06.868865 # # SME support not present
11651 23:44:06.872545 # ok 0 skipped
11652 23:44:06.875807 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11653 23:44:06.878875 ok 33 selftests: arm64: za-fork
11654 23:44:06.881798 # selftests: arm64: za-ptrace
11655 23:44:06.900381 # TAP version 13
11656 23:44:06.900504 # 1..1
11657 23:44:06.903475 # ok 2 # SKIP SME not available
11658 23:44:06.910090 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11659 23:44:06.913537 ok 34 selftests: arm64: za-ptrace # SKIP
11660 23:44:06.925536 # selftests: arm64: check_buffer_fill
11661 23:44:06.984175 # # SKIP: MTE features unavailable
11662 23:44:06.991812 ok 35 selftests: arm64: check_buffer_fill # SKIP
11663 23:44:07.008722 # selftests: arm64: check_child_memory
11664 23:44:07.066726 # # SKIP: MTE features unavailable
11665 23:44:07.074180 ok 36 selftests: arm64: check_child_memory # SKIP
11666 23:44:07.089710 # selftests: arm64: check_gcr_el1_cswitch
11667 23:44:07.154502 # # SKIP: MTE features unavailable
11668 23:44:07.162045 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11669 23:44:07.176875 # selftests: arm64: check_ksm_options
11670 23:44:07.238328 # # SKIP: MTE features unavailable
11671 23:44:07.244991 ok 38 selftests: arm64: check_ksm_options # SKIP
11672 23:44:07.263322 # selftests: arm64: check_mmap_options
11673 23:44:07.338089 # # SKIP: MTE features unavailable
11674 23:44:07.345195 ok 39 selftests: arm64: check_mmap_options # SKIP
11675 23:44:07.358008 # selftests: arm64: check_prctl
11676 23:44:07.430183 # TAP version 13
11677 23:44:07.430322 # 1..5
11678 23:44:07.433447 # ok 1 check_basic_read
11679 23:44:07.433561 # ok 2 NONE
11680 23:44:07.436709 # ok 3 # SKIP SYNC
11681 23:44:07.436792 # ok 4 # SKIP ASYNC
11682 23:44:07.440005 # ok 5 # SKIP SYNC+ASYNC
11683 23:44:07.443535 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11684 23:44:07.446714 ok 40 selftests: arm64: check_prctl
11685 23:44:07.455772 # selftests: arm64: check_tags_inclusion
11686 23:44:07.507499 # # SKIP: MTE features unavailable
11687 23:44:07.515442 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11688 23:44:07.528400 # selftests: arm64: check_user_mem
11689 23:44:07.570888 # # SKIP: MTE features unavailable
11690 23:44:07.579259 ok 42 selftests: arm64: check_user_mem # SKIP
11691 23:44:07.593998 # selftests: arm64: btitest
11692 23:44:07.667385 # TAP version 13
11693 23:44:07.667528 # 1..18
11694 23:44:07.670718 # # HWCAP_PACA not present
11695 23:44:07.674189 # # HWCAP2_BTI not present
11696 23:44:07.674277 # # Test binary built for BTI
11697 23:44:07.680539 # ok 1 nohint_func/call_using_br_x0 # SKIP
11698 23:44:07.683880 # ok 1 nohint_func/call_using_br_x16 # SKIP
11699 23:44:07.687035 # ok 1 nohint_func/call_using_blr # SKIP
11700 23:44:07.690596 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11701 23:44:07.693594 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11702 23:44:07.700301 # ok 1 bti_none_func/call_using_blr # SKIP
11703 23:44:07.703722 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11704 23:44:07.707019 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11705 23:44:07.710540 # ok 1 bti_c_func/call_using_blr # SKIP
11706 23:44:07.713460 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11707 23:44:07.717115 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11708 23:44:07.719911 # ok 1 bti_j_func/call_using_blr # SKIP
11709 23:44:07.723681 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11710 23:44:07.730121 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11711 23:44:07.733554 # ok 1 bti_jc_func/call_using_blr # SKIP
11712 23:44:07.736518 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11713 23:44:07.739511 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11714 23:44:07.743228 # ok 1 paciasp_func/call_using_blr # SKIP
11715 23:44:07.749620 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11716 23:44:07.752985 # # WARNING - EXPECTED TEST COUNT WRONG
11717 23:44:07.756348 ok 43 selftests: arm64: btitest
11718 23:44:07.759557 # selftests: arm64: nobtitest
11719 23:44:07.759659 # TAP version 13
11720 23:44:07.759725 # 1..18
11721 23:44:07.762958 # # HWCAP_PACA not present
11722 23:44:07.766226 # # HWCAP2_BTI not present
11723 23:44:07.769857 # # Test binary not built for BTI
11724 23:44:07.772916 # ok 1 nohint_func/call_using_br_x0 # SKIP
11725 23:44:07.776137 # ok 1 nohint_func/call_using_br_x16 # SKIP
11726 23:44:07.779448 # ok 1 nohint_func/call_using_blr # SKIP
11727 23:44:07.782704 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11728 23:44:07.789538 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11729 23:44:07.792573 # ok 1 bti_none_func/call_using_blr # SKIP
11730 23:44:07.795678 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11731 23:44:07.799330 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11732 23:44:07.802688 # ok 1 bti_c_func/call_using_blr # SKIP
11733 23:44:07.805731 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11734 23:44:07.809585 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11735 23:44:07.812625 # ok 1 bti_j_func/call_using_blr # SKIP
11736 23:44:07.819106 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11737 23:44:07.822389 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11738 23:44:07.825447 # ok 1 bti_jc_func/call_using_blr # SKIP
11739 23:44:07.828832 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11740 23:44:07.832705 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11741 23:44:07.835348 # ok 1 paciasp_func/call_using_blr # SKIP
11742 23:44:07.842117 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11743 23:44:07.845783 # # WARNING - EXPECTED TEST COUNT WRONG
11744 23:44:07.848988 ok 44 selftests: arm64: nobtitest
11745 23:44:07.851821 # selftests: arm64: hwcap
11746 23:44:07.851942 # TAP version 13
11747 23:44:07.852040 # 1..28
11748 23:44:07.855173 # ok 1 cpuinfo_match_RNG
11749 23:44:07.858496 # # SIGILL reported for RNG
11750 23:44:07.861811 # ok 2 # SKIP sigill_RNG
11751 23:44:07.861931 # ok 3 cpuinfo_match_SME
11752 23:44:07.865035 # ok 4 sigill_SME
11753 23:44:07.865120 # ok 5 cpuinfo_match_SVE
11754 23:44:07.868216 # ok 6 sigill_SVE
11755 23:44:07.872026 # ok 7 cpuinfo_match_SVE 2
11756 23:44:07.872142 # # SIGILL reported for SVE 2
11757 23:44:07.874844 # ok 8 # SKIP sigill_SVE 2
11758 23:44:07.878181 # ok 9 cpuinfo_match_SVE AES
11759 23:44:07.881825 # # SIGILL reported for SVE AES
11760 23:44:07.884935 # ok 10 # SKIP sigill_SVE AES
11761 23:44:07.888112 # ok 11 cpuinfo_match_SVE2 PMULL
11762 23:44:07.891808 # # SIGILL reported for SVE2 PMULL
11763 23:44:07.891902 # ok 12 # SKIP sigill_SVE2 PMULL
11764 23:44:07.895258 # ok 13 cpuinfo_match_SVE2 BITPERM
11765 23:44:07.897905 # # SIGILL reported for SVE2 BITPERM
11766 23:44:07.901475 # ok 14 # SKIP sigill_SVE2 BITPERM
11767 23:44:07.904873 # ok 15 cpuinfo_match_SVE2 SHA3
11768 23:44:07.907891 # # SIGILL reported for SVE2 SHA3
11769 23:44:07.911515 # ok 16 # SKIP sigill_SVE2 SHA3
11770 23:44:07.914728 # ok 17 cpuinfo_match_SVE2 SM4
11771 23:44:07.918215 # # SIGILL reported for SVE2 SM4
11772 23:44:07.920932 # ok 18 # SKIP sigill_SVE2 SM4
11773 23:44:07.921046 # ok 19 cpuinfo_match_SVE2 I8MM
11774 23:44:07.924642 # # SIGILL reported for SVE2 I8MM
11775 23:44:07.927526 # ok 20 # SKIP sigill_SVE2 I8MM
11776 23:44:07.931142 # ok 21 cpuinfo_match_SVE2 F32MM
11777 23:44:07.934129 # # SIGILL reported for SVE2 F32MM
11778 23:44:07.938266 # ok 22 # SKIP sigill_SVE2 F32MM
11779 23:44:07.940876 # ok 23 cpuinfo_match_SVE2 F64MM
11780 23:44:07.944713 # # SIGILL reported for SVE2 F64MM
11781 23:44:07.947412 # ok 24 # SKIP sigill_SVE2 F64MM
11782 23:44:07.950591 # ok 25 cpuinfo_match_SVE2 BF16
11783 23:44:07.950714 # # SIGILL reported for SVE2 BF16
11784 23:44:07.954007 # ok 26 # SKIP sigill_SVE2 BF16
11785 23:44:07.957565 # ok 27 cpuinfo_match_SVE2 EBF16
11786 23:44:07.960975 # ok 28 # SKIP sigill_SVE2 EBF16
11787 23:44:07.967112 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11788 23:44:07.970759 ok 45 selftests: arm64: hwcap
11789 23:44:07.970847 # selftests: arm64: ptrace
11790 23:44:07.974249 # TAP version 13
11791 23:44:07.974337 # 1..7
11792 23:44:07.977120 # # Parent is 1499, child is 1500
11793 23:44:07.977227 # ok 1 read_tpidr_one
11794 23:44:07.980682 # ok 2 write_tpidr_one
11795 23:44:07.983979 # ok 3 verify_tpidr_one
11796 23:44:07.984066 # ok 4 count_tpidrs
11797 23:44:07.987183 # ok 5 tpidr2_write
11798 23:44:07.987268 # ok 6 tpidr2_read
11799 23:44:07.990543 # ok 7 write_tpidr_only
11800 23:44:07.998057 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11801 23:44:07.998161 ok 46 selftests: arm64: ptrace
11802 23:44:08.000423 # selftests: arm64: syscall-abi
11803 23:44:08.003703 # TAP version 13
11804 23:44:08.003796 # 1..2
11805 23:44:08.006773 # ok 1 getpid() FPSIMD
11806 23:44:08.006857 # ok 2 sched_yield() FPSIMD
11807 23:44:08.013681 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11808 23:44:08.017100 ok 47 selftests: arm64: syscall-abi
11809 23:44:08.019892 # selftests: arm64: tpidr2
11810 23:44:08.071805 # TAP version 13
11811 23:44:08.071943 # 1..5
11812 23:44:08.074836 # # PID: 1536
11813 23:44:08.074934 # # SME support not present
11814 23:44:08.078108 # ok 0 skipped, TPIDR2 not supported
11815 23:44:08.081352 # ok 1 skipped, TPIDR2 not supported
11816 23:44:08.085144 # ok 2 skipped, TPIDR2 not supported
11817 23:44:08.088122 # ok 3 skipped, TPIDR2 not supported
11818 23:44:08.091917 # ok 4 skipped, TPIDR2 not supported
11819 23:44:08.098039 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11820 23:44:08.101411 ok 48 selftests: arm64: tpidr2
11821 23:44:09.606233 arm64_tags_test pass
11822 23:44:09.609494 arm64_run_tags_test_sh pass
11823 23:44:09.613007 arm64_fake_sigreturn_bad_magic pass
11824 23:44:09.616062 arm64_fake_sigreturn_bad_size pass
11825 23:44:09.619777 arm64_fake_sigreturn_bad_size_for_magic0 pass
11826 23:44:09.622662 arm64_fake_sigreturn_duplicated_fpsimd pass
11827 23:44:09.625911 arm64_fake_sigreturn_misaligned_sp pass
11828 23:44:09.629535 arm64_fake_sigreturn_missing_fpsimd pass
11829 23:44:09.632792 arm64_fake_sigreturn_sme_change_vl skip
11830 23:44:09.639636 arm64_fake_sigreturn_sve_change_vl skip
11831 23:44:09.642232 arm64_mangle_pstate_invalid_compat_toggle pass
11832 23:44:09.645947 arm64_mangle_pstate_invalid_daif_bits pass
11833 23:44:09.648962 arm64_mangle_pstate_invalid_mode_el1h pass
11834 23:44:09.652180 arm64_mangle_pstate_invalid_mode_el1t pass
11835 23:44:09.655796 arm64_mangle_pstate_invalid_mode_el2h pass
11836 23:44:09.662097 arm64_mangle_pstate_invalid_mode_el2t pass
11837 23:44:09.665924 arm64_mangle_pstate_invalid_mode_el3h pass
11838 23:44:09.668853 arm64_mangle_pstate_invalid_mode_el3t pass
11839 23:44:09.672486 arm64_sme_trap_no_sm skip
11840 23:44:09.675243 arm64_sme_trap_non_streaming skip
11841 23:44:09.675355 arm64_sme_trap_za pass
11842 23:44:09.678983 arm64_sme_vl skip
11843 23:44:09.679095 arm64_ssve_regs skip
11844 23:44:09.682359 arm64_sve_regs skip
11845 23:44:09.682470 arm64_sve_vl skip
11846 23:44:09.685473 arm64_za_no_regs skip
11847 23:44:09.685580 arm64_za_regs skip
11848 23:44:09.689164 arm64_pac_PAUTH_not_enabled skip
11849 23:44:09.691892 arm64_pac_PAUTH_not_enabled_dup2 skip
11850 23:44:09.695636 arm64_pac_Generic_PAUTH_not_enabled skip
11851 23:44:09.698751 arm64_pac_PAUTH_not_enabled_dup3 skip
11852 23:44:09.702254 arm64_pac_PAUTH_not_enabled_dup4 skip
11853 23:44:09.708864 arm64_pac_PAUTH_not_enabled_dup5 skip
11854 23:44:09.712152 arm64_pac_Generic_PAUTH_not_enabled_dup2 skip
11855 23:44:09.712239 arm64_pac pass
11856 23:44:09.715109 arm64_fp-stress_FPSIMD-0-0 pass
11857 23:44:09.718454 arm64_fp-stress_FPSIMD-0-1 pass
11858 23:44:09.721879 arm64_fp-stress_FPSIMD-1-0 pass
11859 23:44:09.725348 arm64_fp-stress_FPSIMD-1-1 pass
11860 23:44:09.728255 arm64_fp-stress_FPSIMD-2-0 pass
11861 23:44:09.728368 arm64_fp-stress_FPSIMD-2-1 pass
11862 23:44:09.731654 arm64_fp-stress_FPSIMD-3-0 pass
11863 23:44:09.734774 arm64_fp-stress_FPSIMD-3-1 pass
11864 23:44:09.738413 arm64_fp-stress_FPSIMD-4-0 pass
11865 23:44:09.741448 arm64_fp-stress_FPSIMD-4-1 pass
11866 23:44:09.745164 arm64_fp-stress_FPSIMD-5-0 pass
11867 23:44:09.747973 arm64_fp-stress_FPSIMD-5-1 pass
11868 23:44:09.748058 arm64_fp-stress_FPSIMD-6-0 pass
11869 23:44:09.751537 arm64_fp-stress_FPSIMD-6-1 pass
11870 23:44:09.754608 arm64_fp-stress_FPSIMD-7-0 pass
11871 23:44:09.758101 arm64_fp-stress_FPSIMD-7-1 pass
11872 23:44:09.761289 arm64_fp-stress pass
11873 23:44:09.764943 arm64_sve-ptrace_SVE_not_available skip
11874 23:44:09.765031 arm64_sve-ptrace skip
11875 23:44:09.767831 arm64_sve-probe-vls_SVE_not_available skip
11876 23:44:09.771415 arm64_sve-probe-vls skip
11877 23:44:09.774612 arm64_vec-syscfg_SVE_not_supported skip
11878 23:44:09.777812 arm64_vec-syscfg_SVE_not_supported_dup2 skip
11879 23:44:09.784683 arm64_vec-syscfg_SVE_not_supported_dup3 skip
11880 23:44:09.787789 arm64_vec-syscfg_SVE_not_supported_dup4 skip
11881 23:44:09.791309 arm64_vec-syscfg_SVE_not_supported_dup5 skip
11882 23:44:09.794271 arm64_vec-syscfg_SVE_not_supported_dup6 skip
11883 23:44:09.801053 arm64_vec-syscfg_SVE_not_supported_dup7 skip
11884 23:44:09.804045 arm64_vec-syscfg_SVE_not_supported_dup8 skip
11885 23:44:09.807780 arm64_vec-syscfg_SVE_not_supported_dup9 skip
11886 23:44:09.810936 arm64_vec-syscfg_SVE_not_supported_dup10 skip
11887 23:44:09.814142 arm64_vec-syscfg_SME_not_supported skip
11888 23:44:09.817627 arm64_vec-syscfg_SME_not_supported_dup2 skip
11889 23:44:09.824401 arm64_vec-syscfg_SME_not_supported_dup3 skip
11890 23:44:09.827648 arm64_vec-syscfg_SME_not_supported_dup4 skip
11891 23:44:09.830602 arm64_vec-syscfg_SME_not_supported_dup5 skip
11892 23:44:09.833706 arm64_vec-syscfg_SME_not_supported_dup6 skip
11893 23:44:09.840327 arm64_vec-syscfg_SME_not_supported_dup7 skip
11894 23:44:09.843734 arm64_vec-syscfg_SME_not_supported_dup8 skip
11895 23:44:09.847171 arm64_vec-syscfg_SME_not_supported_dup9 skip
11896 23:44:09.850443 arm64_vec-syscfg_SME_not_supported_dup10 skip
11897 23:44:09.853477 arm64_vec-syscfg pass
11898 23:44:09.857228 arm64_za-fork_skipped pass
11899 23:44:09.857352 arm64_za-fork pass
11900 23:44:09.860542 arm64_za-ptrace_SME_not_available skip
11901 23:44:09.863629 arm64_za-ptrace skip
11902 23:44:09.863742 arm64_check_buffer_fill skip
11903 23:44:09.866622 arm64_check_child_memory skip
11904 23:44:09.870320 arm64_check_gcr_el1_cswitch skip
11905 23:44:09.873646 arm64_check_ksm_options skip
11906 23:44:09.876872 arm64_check_mmap_options skip
11907 23:44:09.879833 arm64_check_prctl_check_basic_read pass
11908 23:44:09.883258 arm64_check_prctl_NONE pass
11909 23:44:09.883369 arm64_check_prctl_SYNC skip
11910 23:44:09.886767 arm64_check_prctl_ASYNC skip
11911 23:44:09.890031 arm64_check_prctl_SYNC_ASYNC skip
11912 23:44:09.893059 arm64_check_prctl pass
11913 23:44:09.896679 arm64_check_tags_inclusion skip
11914 23:44:09.896791 arm64_check_user_mem skip
11915 23:44:09.903200 arm64_btitest_nohint_func_call_using_br_x0 skip
11916 23:44:09.907062 arm64_btitest_nohint_func_call_using_br_x16 skip
11917 23:44:09.909632 arm64_btitest_nohint_func_call_using_blr skip
11918 23:44:09.913151 arm64_btitest_bti_none_func_call_using_br_x0 skip
11919 23:44:09.919992 arm64_btitest_bti_none_func_call_using_br_x16 skip
11920 23:44:09.922967 arm64_btitest_bti_none_func_call_using_blr skip
11921 23:44:09.926617 arm64_btitest_bti_c_func_call_using_br_x0 skip
11922 23:44:09.933189 arm64_btitest_bti_c_func_call_using_br_x16 skip
11923 23:44:09.936026 arm64_btitest_bti_c_func_call_using_blr skip
11924 23:44:09.939440 arm64_btitest_bti_j_func_call_using_br_x0 skip
11925 23:44:09.943039 arm64_btitest_bti_j_func_call_using_br_x16 skip
11926 23:44:09.949632 arm64_btitest_bti_j_func_call_using_blr skip
11927 23:44:09.952516 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11928 23:44:09.955980 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11929 23:44:09.959399 arm64_btitest_bti_jc_func_call_using_blr skip
11930 23:44:09.966253 arm64_btitest_paciasp_func_call_using_br_x0 skip
11931 23:44:09.969566 arm64_btitest_paciasp_func_call_using_br_x16 skip
11932 23:44:09.972408 arm64_btitest_paciasp_func_call_using_blr skip
11933 23:44:09.975804 arm64_btitest pass
11934 23:44:09.979369 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11935 23:44:09.985876 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11936 23:44:09.989520 arm64_nobtitest_nohint_func_call_using_blr skip
11937 23:44:09.992315 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11938 23:44:09.998755 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11939 23:44:10.002562 arm64_nobtitest_bti_none_func_call_using_blr skip
11940 23:44:10.005772 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11941 23:44:10.012281 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11942 23:44:10.015543 arm64_nobtitest_bti_c_func_call_using_blr skip
11943 23:44:10.018497 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11944 23:44:10.025144 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11945 23:44:10.029087 arm64_nobtitest_bti_j_func_call_using_blr skip
11946 23:44:10.031804 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11947 23:44:10.038827 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11948 23:44:10.041536 arm64_nobtitest_bti_jc_func_call_using_blr skip
11949 23:44:10.045231 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11950 23:44:10.051374 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11951 23:44:10.054928 arm64_nobtitest_paciasp_func_call_using_blr skip
11952 23:44:10.058382 arm64_nobtitest pass
11953 23:44:10.061698 arm64_hwcap_cpuinfo_match_RNG pass
11954 23:44:10.061815 arm64_hwcap_sigill_RNG skip
11955 23:44:10.064619 arm64_hwcap_cpuinfo_match_SME pass
11956 23:44:10.068342 arm64_hwcap_sigill_SME pass
11957 23:44:10.071602 arm64_hwcap_cpuinfo_match_SVE pass
11958 23:44:10.074736 arm64_hwcap_sigill_SVE pass
11959 23:44:10.077714 arm64_hwcap_cpuinfo_match_SVE_2 pass
11960 23:44:10.081127 arm64_hwcap_sigill_SVE_2 skip
11961 23:44:10.084431 arm64_hwcap_cpuinfo_match_SVE_AES pass
11962 23:44:10.084546 arm64_hwcap_sigill_SVE_AES skip
11963 23:44:10.091345 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11964 23:44:10.094394 arm64_hwcap_sigill_SVE2_PMULL skip
11965 23:44:10.097962 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11966 23:44:10.100995 arm64_hwcap_sigill_SVE2_BITPERM skip
11967 23:44:10.104677 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11968 23:44:10.107535 arm64_hwcap_sigill_SVE2_SHA3 skip
11969 23:44:10.111418 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11970 23:44:10.114472 arm64_hwcap_sigill_SVE2_SM4 skip
11971 23:44:10.117620 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11972 23:44:10.121155 arm64_hwcap_sigill_SVE2_I8MM skip
11973 23:44:10.124095 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11974 23:44:10.127590 arm64_hwcap_sigill_SVE2_F32MM skip
11975 23:44:10.130669 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11976 23:44:10.134063 arm64_hwcap_sigill_SVE2_F64MM skip
11977 23:44:10.137505 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11978 23:44:10.140914 arm64_hwcap_sigill_SVE2_BF16 skip
11979 23:44:10.144176 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11980 23:44:10.147009 arm64_hwcap_sigill_SVE2_EBF16 skip
11981 23:44:10.147125 arm64_hwcap pass
11982 23:44:10.150863 arm64_ptrace_read_tpidr_one pass
11983 23:44:10.154027 arm64_ptrace_write_tpidr_one pass
11984 23:44:10.156922 arm64_ptrace_verify_tpidr_one pass
11985 23:44:10.160400 arm64_ptrace_count_tpidrs pass
11986 23:44:10.163895 arm64_ptrace_tpidr2_write pass
11987 23:44:10.167093 arm64_ptrace_tpidr2_read pass
11988 23:44:10.170610 arm64_ptrace_write_tpidr_only pass
11989 23:44:10.170726 arm64_ptrace pass
11990 23:44:10.173958 arm64_syscall-abi_getpid_FPSIMD pass
11991 23:44:10.176713 arm64_syscall-abi_sched_yield_FPSIMD pass
11992 23:44:10.180327 arm64_syscall-abi pass
11993 23:44:10.183331 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11994 23:44:10.190249 arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 pass
11995 23:44:10.193713 arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 pass
11996 23:44:10.196645 arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 pass
11997 23:44:10.203096 arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 pass
11998 23:44:10.203219 arm64_tpidr2 pass
11999 23:44:10.209933 + ../../utils/send-to-lava.sh ./output/result.txt
12000 23:44:10.213417 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
12001 23:44:10.213745 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
12003 23:44:10.219680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
12004 23:44:10.219977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12006 23:44:10.226491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12007 23:44:10.226789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12009 23:44:10.232703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12010 23:44:10.232996 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12012 23:44:10.256615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12013 23:44:10.256950 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12015 23:44:10.317630 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12016 23:44:10.317975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12018 23:44:10.374560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12019 23:44:10.374907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12021 23:44:10.433893 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12022 23:44:10.434239 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12024 23:44:10.491488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12025 23:44:10.491834 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12027 23:44:10.552037 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12028 23:44:10.552388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12030 23:44:10.609998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12031 23:44:10.610361 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12033 23:44:10.669903 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12034 23:44:10.670263 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12036 23:44:10.723505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12037 23:44:10.723876 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12039 23:44:10.783680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12040 23:44:10.784046 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12042 23:44:10.835263 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12043 23:44:10.835639 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12045 23:44:10.886958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12046 23:44:10.887327 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12048 23:44:10.943430 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12049 23:44:10.943800 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12051 23:44:10.996846 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12052 23:44:10.997235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12054 23:44:11.049962 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12055 23:44:11.050319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12057 23:44:11.106358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12058 23:44:11.106713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12060 23:44:11.157288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12062 23:44:11.159939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12063 23:44:11.213552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12064 23:44:11.213970 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12066 23:44:11.270192 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12067 23:44:11.270594 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12069 23:44:11.322283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12070 23:44:11.322661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12072 23:44:11.375649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12073 23:44:11.376038 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12075 23:44:11.427358 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12076 23:44:11.427715 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12078 23:44:11.484905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12079 23:44:11.485288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12081 23:44:11.537614 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12082 23:44:11.537975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12084 23:44:11.589228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12086 23:44:11.591958 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12087 23:44:11.647148 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip>
12088 23:44:11.647525 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup2 RESULT=skip
12090 23:44:11.700979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12091 23:44:11.701325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12093 23:44:11.755805 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip>
12094 23:44:11.756164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup3 RESULT=skip
12096 23:44:11.814539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip>
12097 23:44:11.814919 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup4 RESULT=skip
12099 23:44:11.869612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip>
12100 23:44:11.869968 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled_dup5 RESULT=skip
12102 23:44:11.928537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip>
12103 23:44:11.928909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled_dup2 RESULT=skip
12105 23:44:11.985420 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12106 23:44:11.985785 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12108 23:44:12.039118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12109 23:44:12.039503 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12111 23:44:12.094427 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12112 23:44:12.094802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12114 23:44:12.148150 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12115 23:44:12.148555 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12117 23:44:12.203682 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12118 23:44:12.204040 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12120 23:44:12.259680 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12121 23:44:12.260054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12123 23:44:12.312165 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12124 23:44:12.312519 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12126 23:44:12.368692 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12127 23:44:12.369064 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12129 23:44:12.427407 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12130 23:44:12.427773 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12132 23:44:12.485619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12133 23:44:12.485977 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12135 23:44:12.547487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12136 23:44:12.547848 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12138 23:44:12.601454 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12139 23:44:12.601824 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12141 23:44:12.653778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12142 23:44:12.654156 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12144 23:44:12.712970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12145 23:44:12.713354 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12147 23:44:12.765939 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12148 23:44:12.766349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12150 23:44:12.823779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12151 23:44:12.824135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12153 23:44:12.876472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12154 23:44:12.876789 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12156 23:44:12.929843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12157 23:44:12.930161 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12159 23:44:12.992282 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12160 23:44:12.992600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12162 23:44:13.047374 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12163 23:44:13.047729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12165 23:44:13.110722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12166 23:44:13.111121 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12168 23:44:13.167395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12169 23:44:13.167736 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12171 23:44:13.227724 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12172 23:44:13.228069 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12174 23:44:13.289004 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip>
12175 23:44:13.289293 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup2 RESULT=skip
12177 23:44:13.345373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip>
12178 23:44:13.345690 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup3 RESULT=skip
12180 23:44:13.406552 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip>
12181 23:44:13.406888 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup4 RESULT=skip
12183 23:44:13.468433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip>
12184 23:44:13.468775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup5 RESULT=skip
12186 23:44:13.528752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip>
12187 23:44:13.529083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup6 RESULT=skip
12189 23:44:13.594590 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip>
12190 23:44:13.594909 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup7 RESULT=skip
12192 23:44:13.652281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip>
12193 23:44:13.652617 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup8 RESULT=skip
12195 23:44:13.711541 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip>
12196 23:44:13.711862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup9 RESULT=skip
12198 23:44:13.771516 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip>
12199 23:44:13.771854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported_dup10 RESULT=skip
12201 23:44:13.833687 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12202 23:44:13.834008 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12204 23:44:13.896114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip>
12205 23:44:13.896428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup2 RESULT=skip
12207 23:44:13.959693 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip>
12208 23:44:13.960014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup3 RESULT=skip
12210 23:44:14.024025 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip>
12211 23:44:14.024349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup4 RESULT=skip
12213 23:44:14.085925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip>
12214 23:44:14.086248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup5 RESULT=skip
12216 23:44:14.148991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip>
12217 23:44:14.149316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup6 RESULT=skip
12219 23:44:14.208524 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip>
12220 23:44:14.208843 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup7 RESULT=skip
12222 23:44:14.268121 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip>
12223 23:44:14.268470 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup8 RESULT=skip
12225 23:44:14.329753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip>
12226 23:44:14.330077 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup9 RESULT=skip
12228 23:44:14.391841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip>
12229 23:44:14.392177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported_dup10 RESULT=skip
12231 23:44:14.452534 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12232 23:44:14.452896 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12234 23:44:14.514184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12235 23:44:14.514490 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12237 23:44:14.580655 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12238 23:44:14.580964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12240 23:44:14.643864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12241 23:44:14.644173 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12243 23:44:14.704109 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12244 23:44:14.704417 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12246 23:44:14.766483 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12247 23:44:14.766798 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12249 23:44:14.828550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12250 23:44:14.828870 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12252 23:44:14.888722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12254 23:44:14.891283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12255 23:44:14.947966 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12256 23:44:14.948323 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12258 23:44:15.005224 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12259 23:44:15.005572 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12261 23:44:15.063820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12262 23:44:15.064175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12264 23:44:15.118414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12265 23:44:15.118739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12267 23:44:15.178093 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12268 23:44:15.178419 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12270 23:44:15.236819 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12271 23:44:15.237219 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12273 23:44:15.297312 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12275 23:44:15.300778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12276 23:44:15.359118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12277 23:44:15.359444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12279 23:44:15.417392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12280 23:44:15.417723 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12282 23:44:15.475113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12283 23:44:15.475478 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12285 23:44:15.533928 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12286 23:44:15.534319 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12288 23:44:15.591611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12289 23:44:15.591933 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12291 23:44:15.652101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12292 23:44:15.652429 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12294 23:44:15.717206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12295 23:44:15.717556 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12297 23:44:15.777574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12298 23:44:15.777907 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12300 23:44:15.837151 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12301 23:44:15.837501 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12303 23:44:15.897267 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12304 23:44:15.897611 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12306 23:44:15.960222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12307 23:44:15.960551 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12309 23:44:16.025231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12310 23:44:16.025582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12312 23:44:16.088532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12313 23:44:16.088862 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12315 23:44:16.149652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12316 23:44:16.149983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12318 23:44:16.210985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12319 23:44:16.211309 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12321 23:44:16.266045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12322 23:44:16.266399 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12324 23:44:16.321952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12325 23:44:16.322291 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12327 23:44:16.382812 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12328 23:44:16.383170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12330 23:44:16.441222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12331 23:44:16.441600 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12333 23:44:16.501340 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12334 23:44:16.501667 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12336 23:44:16.564227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12337 23:44:16.564590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12339 23:44:16.618292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12340 23:44:16.618618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12342 23:44:16.678660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12343 23:44:16.678994 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12345 23:44:16.736050 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12346 23:44:16.736407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12348 23:44:16.797446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12349 23:44:16.797775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12351 23:44:16.858835 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12352 23:44:16.859177 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12354 23:44:16.919731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12355 23:44:16.920055 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12357 23:44:16.980675 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12358 23:44:16.981039 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12360 23:44:17.042896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12361 23:44:17.043225 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12363 23:44:17.108179 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12364 23:44:17.108528 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12366 23:44:17.169723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12367 23:44:17.170054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12369 23:44:17.229243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12370 23:44:17.229581 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12372 23:44:17.288236 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12373 23:44:17.288568 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12375 23:44:17.347209 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12376 23:44:17.347539 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12378 23:44:17.405221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12379 23:44:17.405589 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12381 23:44:17.460941 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12382 23:44:17.461288 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12384 23:44:17.516411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12385 23:44:17.516744 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12387 23:44:17.570870 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12388 23:44:17.571228 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12390 23:44:17.625748 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12391 23:44:17.626079 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12393 23:44:17.684347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12394 23:44:17.684702 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12396 23:44:17.738800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12397 23:44:17.739140 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12399 23:44:17.800333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12400 23:44:17.800663 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12402 23:44:17.856772 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12403 23:44:17.857144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12405 23:44:17.917725 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12406 23:44:17.918059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12408 23:44:17.971435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12409 23:44:17.971764 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12411 23:44:18.034950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12412 23:44:18.035273 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12414 23:44:18.088652 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12415 23:44:18.088975 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12417 23:44:18.151178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12418 23:44:18.151497 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12420 23:44:18.208143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12421 23:44:18.208472 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12423 23:44:18.272365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12424 23:44:18.272692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12426 23:44:18.331933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12427 23:44:18.332278 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12429 23:44:18.393196 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12430 23:44:18.393561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12432 23:44:18.450585 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12433 23:44:18.450946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12435 23:44:18.509951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12436 23:44:18.510347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12438 23:44:18.565132 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12439 23:44:18.565561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12441 23:44:18.625415 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12442 23:44:18.625745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12444 23:44:18.684235 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12446 23:44:18.686969 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12447 23:44:18.747620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12448 23:44:18.747952 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12450 23:44:18.808861 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12452 23:44:18.812047 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12453 23:44:18.874404 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12454 23:44:18.874777 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12456 23:44:18.930811 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12458 23:44:18.934401 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12459 23:44:18.993519 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12460 23:44:18.993845 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12462 23:44:19.052488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12463 23:44:19.052822 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12465 23:44:19.113143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12466 23:44:19.113540 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12468 23:44:19.171146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12469 23:44:19.171513 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12471 23:44:19.232809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12472 23:44:19.233135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12474 23:44:19.292296 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12476 23:44:19.295405 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12477 23:44:19.358421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12478 23:44:19.358746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12480 23:44:19.414160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12481 23:44:19.414487 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12483 23:44:19.468775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12484 23:44:19.469100 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12486 23:44:19.527071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12488 23:44:19.530157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12489 23:44:19.586778 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12491 23:44:19.590057 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12492 23:44:19.652487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12493 23:44:19.652812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12495 23:44:19.713777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12496 23:44:19.714102 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12498 23:44:19.777785 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12499 23:44:19.778111 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12501 23:44:19.841314 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12502 23:44:19.841636 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12504 23:44:19.904111 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12505 23:44:19.904434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12507 23:44:19.962201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12508 23:44:19.962523 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12510 23:44:20.025643 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12511 23:44:20.025980 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12513 23:44:20.087598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12514 23:44:20.087917 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12516 23:44:20.142759 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12517 23:44:20.143078 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12519 23:44:20.203586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12520 23:44:20.203943 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12522 23:44:20.262065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass>
12523 23:44:20.262390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup2 RESULT=pass
12525 23:44:20.322626 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass>
12526 23:44:20.322946 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup3 RESULT=pass
12528 23:44:20.381482 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass>
12529 23:44:20.381805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup4 RESULT=pass
12531 23:44:20.440409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass>
12532 23:44:20.440728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported_dup5 RESULT=pass
12534 23:44:20.493831 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12535 23:44:20.493976 + set +x
12536 23:44:20.494220 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12538 23:44:20.500091 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 14172919_1.6.2.3.5>
12539 23:44:20.500393 Received signal: <ENDRUN> 1_kselftest-arm64 14172919_1.6.2.3.5
12540 23:44:20.500482 Ending use of test pattern.
12541 23:44:20.500548 Ending test lava.1_kselftest-arm64 (14172919_1.6.2.3.5), duration 33.65
12543 23:44:20.503271 <LAVA_TEST_RUNNER EXIT>
12544 23:44:20.503526 ok: lava_test_shell seems to have completed
12545 23:44:20.504715 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_Generic_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled_dup2: skip
arm64_pac_PAUTH_not_enabled_dup3: skip
arm64_pac_PAUTH_not_enabled_dup4: skip
arm64_pac_PAUTH_not_enabled_dup5: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup3: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup4: pass
arm64_tpidr2_skipped_TPIDR2_not_supported_dup5: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SME_not_supported_dup10: skip
arm64_vec-syscfg_SME_not_supported_dup2: skip
arm64_vec-syscfg_SME_not_supported_dup3: skip
arm64_vec-syscfg_SME_not_supported_dup4: skip
arm64_vec-syscfg_SME_not_supported_dup5: skip
arm64_vec-syscfg_SME_not_supported_dup6: skip
arm64_vec-syscfg_SME_not_supported_dup7: skip
arm64_vec-syscfg_SME_not_supported_dup8: skip
arm64_vec-syscfg_SME_not_supported_dup9: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_vec-syscfg_SVE_not_supported_dup10: skip
arm64_vec-syscfg_SVE_not_supported_dup2: skip
arm64_vec-syscfg_SVE_not_supported_dup3: skip
arm64_vec-syscfg_SVE_not_supported_dup4: skip
arm64_vec-syscfg_SVE_not_supported_dup5: skip
arm64_vec-syscfg_SVE_not_supported_dup6: skip
arm64_vec-syscfg_SVE_not_supported_dup7: skip
arm64_vec-syscfg_SVE_not_supported_dup8: skip
arm64_vec-syscfg_SVE_not_supported_dup9: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12546 23:44:20.504877 end: 3.1 lava-test-shell (duration 00:00:35) [common]
12547 23:44:20.504968 end: 3 lava-test-retry (duration 00:00:35) [common]
12548 23:44:20.505057 start: 4 finalize (timeout 00:07:10) [common]
12549 23:44:20.505148 start: 4.1 power-off (timeout 00:00:30) [common]
12550 23:44:20.505351 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
12551 23:44:20.704914 >> Command sent successfully.
12552 23:44:20.707485 Returned 0 in 0 seconds
12553 23:44:20.807946 end: 4.1 power-off (duration 00:00:00) [common]
12555 23:44:20.808324 start: 4.2 read-feedback (timeout 00:07:10) [common]
12556 23:44:20.808660 Listened to connection for namespace 'common' for up to 1s
12557 23:44:21.809388 Finalising connection for namespace 'common'
12558 23:44:21.809564 Disconnecting from shell: Finalise
12559 23:44:21.809641 / #
12560 23:44:21.910032 end: 4.2 read-feedback (duration 00:00:01) [common]
12561 23:44:21.910217 end: 4 finalize (duration 00:00:01) [common]
12562 23:44:21.910333 Cleaning after the job
12563 23:44:21.910433 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/ramdisk
12564 23:44:21.912537 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/kernel
12565 23:44:21.922769 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/dtb
12566 23:44:21.922964 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/nfsrootfs
12567 23:44:21.984653 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172919/tftp-deploy-fqq5gldl/modules
12568 23:44:21.990296 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14172919
12569 23:44:22.555491 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14172919
12570 23:44:22.555666 Job finished correctly