Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 35
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 23:45:33.331066 lava-dispatcher, installed at version: 2024.03
2 23:45:33.331282 start: 0 validate
3 23:45:33.331420 Start time: 2024-06-04 23:45:33.331412+00:00 (UTC)
4 23:45:33.331550 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:45:33.331684 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:45:33.582163 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:45:33.582348 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:45:49.583303 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:45:49.583467 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:45:49.842635 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:45:49.842796 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:45:50.097977 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:45:50.098155 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:45:54.101908 validate duration: 20.77
16 23:45:54.102304 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:45:54.102478 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:45:54.102642 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:45:54.102860 Not decompressing ramdisk as can be used compressed.
20 23:45:54.102992 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:45:54.103087 saving as /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/ramdisk/initrd.cpio.gz
22 23:45:54.103199 total size: 5628169 (5 MB)
23 23:45:54.104766 progress 0 % (0 MB)
24 23:45:54.107176 progress 5 % (0 MB)
25 23:45:54.109748 progress 10 % (0 MB)
26 23:45:54.111880 progress 15 % (0 MB)
27 23:45:54.114449 progress 20 % (1 MB)
28 23:45:54.116647 progress 25 % (1 MB)
29 23:45:54.119210 progress 30 % (1 MB)
30 23:45:54.121637 progress 35 % (1 MB)
31 23:45:54.123962 progress 40 % (2 MB)
32 23:45:54.125745 progress 45 % (2 MB)
33 23:45:54.127159 progress 50 % (2 MB)
34 23:45:54.128842 progress 55 % (2 MB)
35 23:45:54.130372 progress 60 % (3 MB)
36 23:45:54.131804 progress 65 % (3 MB)
37 23:45:54.133624 progress 70 % (3 MB)
38 23:45:54.135494 progress 75 % (4 MB)
39 23:45:54.137279 progress 80 % (4 MB)
40 23:45:54.138700 progress 85 % (4 MB)
41 23:45:54.140384 progress 90 % (4 MB)
42 23:45:54.141909 progress 95 % (5 MB)
43 23:45:54.143320 progress 100 % (5 MB)
44 23:45:54.143526 5 MB downloaded in 0.04 s (133.10 MB/s)
45 23:45:54.143684 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:45:54.143958 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:45:54.144045 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:45:54.144131 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:45:54.144292 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:45:54.144375 saving as /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/kernel/Image
52 23:45:54.144441 total size: 54682112 (52 MB)
53 23:45:54.144519 No compression specified
54 23:45:54.145720 progress 0 % (0 MB)
55 23:45:54.160305 progress 5 % (2 MB)
56 23:45:54.174691 progress 10 % (5 MB)
57 23:45:54.189713 progress 15 % (7 MB)
58 23:45:54.204012 progress 20 % (10 MB)
59 23:45:54.218175 progress 25 % (13 MB)
60 23:45:54.232196 progress 30 % (15 MB)
61 23:45:54.246417 progress 35 % (18 MB)
62 23:45:54.260430 progress 40 % (20 MB)
63 23:45:54.274424 progress 45 % (23 MB)
64 23:45:54.288633 progress 50 % (26 MB)
65 23:45:54.302628 progress 55 % (28 MB)
66 23:45:54.316789 progress 60 % (31 MB)
67 23:45:54.330746 progress 65 % (33 MB)
68 23:45:54.345506 progress 70 % (36 MB)
69 23:45:54.360158 progress 75 % (39 MB)
70 23:45:54.374798 progress 80 % (41 MB)
71 23:45:54.389355 progress 85 % (44 MB)
72 23:45:54.404205 progress 90 % (46 MB)
73 23:45:54.418585 progress 95 % (49 MB)
74 23:45:54.432696 progress 100 % (52 MB)
75 23:45:54.432968 52 MB downloaded in 0.29 s (180.74 MB/s)
76 23:45:54.433146 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:45:54.433394 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:45:54.433484 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:45:54.433572 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:45:54.433722 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:45:54.433794 saving as /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/dtb/mt8192-asurada-spherion-r0.dtb
83 23:45:54.433858 total size: 47258 (0 MB)
84 23:45:54.433921 No compression specified
85 23:45:54.435174 progress 69 % (0 MB)
86 23:45:54.435469 progress 100 % (0 MB)
87 23:45:54.435628 0 MB downloaded in 0.00 s (25.50 MB/s)
88 23:45:54.435757 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:45:54.436005 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:45:54.436153 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:45:54.436273 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:45:54.436431 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:45:54.436505 saving as /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/nfsrootfs/full.rootfs.tar
95 23:45:54.436568 total size: 120894716 (115 MB)
96 23:45:54.436633 Using unxz to decompress xz
97 23:45:54.440671 progress 0 % (0 MB)
98 23:45:54.800424 progress 5 % (5 MB)
99 23:45:55.188896 progress 10 % (11 MB)
100 23:45:55.555809 progress 15 % (17 MB)
101 23:45:55.888851 progress 20 % (23 MB)
102 23:45:56.183208 progress 25 % (28 MB)
103 23:45:56.547962 progress 30 % (34 MB)
104 23:45:56.913673 progress 35 % (40 MB)
105 23:45:57.093177 progress 40 % (46 MB)
106 23:45:57.276058 progress 45 % (51 MB)
107 23:45:57.597582 progress 50 % (57 MB)
108 23:45:57.980459 progress 55 % (63 MB)
109 23:45:58.328725 progress 60 % (69 MB)
110 23:45:58.686924 progress 65 % (74 MB)
111 23:45:59.036030 progress 70 % (80 MB)
112 23:45:59.399847 progress 75 % (86 MB)
113 23:45:59.757911 progress 80 % (92 MB)
114 23:46:00.126396 progress 85 % (98 MB)
115 23:46:00.504034 progress 90 % (103 MB)
116 23:46:00.856239 progress 95 % (109 MB)
117 23:46:01.259707 progress 100 % (115 MB)
118 23:46:01.265392 115 MB downloaded in 6.83 s (16.88 MB/s)
119 23:46:01.265744 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:46:01.266203 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:46:01.266358 start: 1.5 download-retry (timeout 00:09:53) [common]
123 23:46:01.266506 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 23:46:01.266729 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:46:01.266831 saving as /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/modules/modules.tar
126 23:46:01.266924 total size: 8603924 (8 MB)
127 23:46:01.267028 Using unxz to decompress xz
128 23:46:01.519504 progress 0 % (0 MB)
129 23:46:01.540711 progress 5 % (0 MB)
130 23:46:01.568053 progress 10 % (0 MB)
131 23:46:01.595583 progress 15 % (1 MB)
132 23:46:01.622389 progress 20 % (1 MB)
133 23:46:01.650606 progress 25 % (2 MB)
134 23:46:01.678078 progress 30 % (2 MB)
135 23:46:01.703134 progress 35 % (2 MB)
136 23:46:01.731908 progress 40 % (3 MB)
137 23:46:01.759466 progress 45 % (3 MB)
138 23:46:01.787013 progress 50 % (4 MB)
139 23:46:01.813889 progress 55 % (4 MB)
140 23:46:01.839017 progress 60 % (4 MB)
141 23:46:01.863371 progress 65 % (5 MB)
142 23:46:01.890301 progress 70 % (5 MB)
143 23:46:01.916281 progress 75 % (6 MB)
144 23:46:01.942277 progress 80 % (6 MB)
145 23:46:01.966684 progress 85 % (7 MB)
146 23:46:01.991306 progress 90 % (7 MB)
147 23:46:02.022462 progress 95 % (7 MB)
148 23:46:02.052295 progress 100 % (8 MB)
149 23:46:02.058086 8 MB downloaded in 0.79 s (10.37 MB/s)
150 23:46:02.058484 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:46:02.058942 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:46:02.059092 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 23:46:02.059250 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 23:46:05.735080 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14172931/extract-nfsrootfs-ivx2x1zz
156 23:46:05.735387 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:46:05.735533 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:46:05.735831 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u
159 23:46:05.736065 makedir: /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin
160 23:46:05.736256 makedir: /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/tests
161 23:46:05.736891 makedir: /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/results
162 23:46:05.737079 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-add-keys
163 23:46:05.737324 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-add-sources
164 23:46:05.737458 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-background-process-start
165 23:46:05.737590 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-background-process-stop
166 23:46:05.737734 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-common-functions
167 23:46:05.737858 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-echo-ipv4
168 23:46:05.737984 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-install-packages
169 23:46:05.738169 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-installed-packages
170 23:46:05.738291 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-os-build
171 23:46:05.738414 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-probe-channel
172 23:46:05.738544 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-probe-ip
173 23:46:05.738669 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-target-ip
174 23:46:05.738792 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-target-mac
175 23:46:05.738915 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-target-storage
176 23:46:05.739099 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-test-case
177 23:46:05.739271 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-test-event
178 23:46:05.739397 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-test-feedback
179 23:46:05.739523 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-test-raise
180 23:46:05.739679 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-test-reference
181 23:46:05.739810 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-test-runner
182 23:46:05.739940 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-test-set
183 23:46:05.740068 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-test-shell
184 23:46:05.740197 Updating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-add-keys (debian)
185 23:46:05.740364 Updating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-add-sources (debian)
186 23:46:05.740516 Updating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-install-packages (debian)
187 23:46:05.740662 Updating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-installed-packages (debian)
188 23:46:05.740806 Updating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/bin/lava-os-build (debian)
189 23:46:05.740933 Creating /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/environment
190 23:46:05.741036 LAVA metadata
191 23:46:05.741105 - LAVA_JOB_ID=14172931
192 23:46:05.741169 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:46:05.741295 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:46:05.741380 skipped lava-vland-overlay
195 23:46:05.741457 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:46:05.741539 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:46:05.741599 skipped lava-multinode-overlay
198 23:46:05.741670 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:46:05.741747 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:46:05.741824 Loading test definitions
201 23:46:05.741915 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:46:05.742004 Using /lava-14172931 at stage 0
203 23:46:05.742460 uuid=14172931_1.6.2.3.1 testdef=None
204 23:46:05.742551 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:46:05.742638 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:46:05.743108 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:46:05.743347 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:46:05.743916 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:46:05.744177 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:46:05.744884 runner path: /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/0/tests/0_timesync-off test_uuid 14172931_1.6.2.3.1
213 23:46:05.745051 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:46:05.745282 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:46:05.745357 Using /lava-14172931 at stage 0
217 23:46:05.745463 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:46:05.745554 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/0/tests/1_kselftest-dt'
219 23:46:08.117895 Running '/usr/bin/git checkout kernelci.org
220 23:46:08.198077 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 23:46:08.199148 uuid=14172931_1.6.2.3.5 testdef=None
222 23:46:08.199379 end: 1.6.2.3.5 git-repo-action (duration 00:00:02) [common]
224 23:46:08.199751 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 23:46:08.201018 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:46:08.201371 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 23:46:08.202928 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:46:08.203308 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 23:46:08.204839 runner path: /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/0/tests/1_kselftest-dt test_uuid 14172931_1.6.2.3.5
232 23:46:08.204972 BOARD='mt8192-asurada-spherion-r0'
233 23:46:08.205069 BRANCH='cip'
234 23:46:08.205162 SKIPFILE='/dev/null'
235 23:46:08.205253 SKIP_INSTALL='True'
236 23:46:08.205343 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:46:08.205439 TST_CASENAME=''
238 23:46:08.205529 TST_CMDFILES='dt'
239 23:46:08.205734 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:46:08.206061 Creating lava-test-runner.conf files
242 23:46:08.206162 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14172931/lava-overlay-7h_p1e0u/lava-14172931/0 for stage 0
243 23:46:08.206299 - 0_timesync-off
244 23:46:08.206408 - 1_kselftest-dt
245 23:46:08.206549 end: 1.6.2.3 test-definition (duration 00:00:02) [common]
246 23:46:08.206678 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 23:46:16.025345 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:46:16.025517 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 23:46:16.025618 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:46:16.025754 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 23:46:16.025881 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 23:46:16.195138 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:46:16.195562 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 23:46:16.195707 extracting modules file /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172931/extract-nfsrootfs-ivx2x1zz
255 23:46:16.416981 extracting modules file /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172931/extract-overlay-ramdisk-943tccs6/ramdisk
256 23:46:16.642921 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:46:16.643118 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 23:46:16.643245 [common] Applying overlay to NFS
259 23:46:16.643352 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172931/compress-overlay-vo7cw7j4/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14172931/extract-nfsrootfs-ivx2x1zz
260 23:46:17.594225 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:46:17.594437 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 23:46:17.594568 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:46:17.594692 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 23:46:17.594811 Building ramdisk /var/lib/lava/dispatcher/tmp/14172931/extract-overlay-ramdisk-943tccs6/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14172931/extract-overlay-ramdisk-943tccs6/ramdisk
265 23:46:17.948081 >> 130337 blocks
266 23:46:20.011577 rename /var/lib/lava/dispatcher/tmp/14172931/extract-overlay-ramdisk-943tccs6/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/ramdisk/ramdisk.cpio.gz
267 23:46:20.012024 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:46:20.012147 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 23:46:20.012253 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 23:46:20.012377 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/kernel/Image']
271 23:46:34.048109 Returned 0 in 14 seconds
272 23:46:34.148886 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/kernel/image.itb
273 23:46:34.508097 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:46:34.508575 output: Created: Wed Jun 5 00:46:34 2024
275 23:46:34.508686 output: Image 0 (kernel-1)
276 23:46:34.508783 output: Description:
277 23:46:34.508881 output: Created: Wed Jun 5 00:46:34 2024
278 23:46:34.508977 output: Type: Kernel Image
279 23:46:34.509075 output: Compression: lzma compressed
280 23:46:34.509164 output: Data Size: 13061430 Bytes = 12755.30 KiB = 12.46 MiB
281 23:46:34.509256 output: Architecture: AArch64
282 23:46:34.509352 output: OS: Linux
283 23:46:34.509444 output: Load Address: 0x00000000
284 23:46:34.509538 output: Entry Point: 0x00000000
285 23:46:34.509630 output: Hash algo: crc32
286 23:46:34.509718 output: Hash value: ecfb5096
287 23:46:34.509816 output: Image 1 (fdt-1)
288 23:46:34.509915 output: Description: mt8192-asurada-spherion-r0
289 23:46:34.510008 output: Created: Wed Jun 5 00:46:34 2024
290 23:46:34.510095 output: Type: Flat Device Tree
291 23:46:34.510193 output: Compression: uncompressed
292 23:46:34.510285 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 23:46:34.510380 output: Architecture: AArch64
294 23:46:34.510473 output: Hash algo: crc32
295 23:46:34.510563 output: Hash value: 0f8e4d2e
296 23:46:34.510652 output: Image 2 (ramdisk-1)
297 23:46:34.510745 output: Description: unavailable
298 23:46:34.510832 output: Created: Wed Jun 5 00:46:34 2024
299 23:46:34.510928 output: Type: RAMDisk Image
300 23:46:34.511016 output: Compression: Unknown Compression
301 23:46:34.511106 output: Data Size: 18731769 Bytes = 18292.74 KiB = 17.86 MiB
302 23:46:34.511200 output: Architecture: AArch64
303 23:46:34.511289 output: OS: Linux
304 23:46:34.511378 output: Load Address: unavailable
305 23:46:34.511478 output: Entry Point: unavailable
306 23:46:34.511564 output: Hash algo: crc32
307 23:46:34.511654 output: Hash value: 0a46777c
308 23:46:34.511739 output: Default Configuration: 'conf-1'
309 23:46:34.511822 output: Configuration 0 (conf-1)
310 23:46:34.511915 output: Description: mt8192-asurada-spherion-r0
311 23:46:34.512002 output: Kernel: kernel-1
312 23:46:34.512086 output: Init Ramdisk: ramdisk-1
313 23:46:34.512175 output: FDT: fdt-1
314 23:46:34.512259 output: Loadables: kernel-1
315 23:46:34.512348 output:
316 23:46:34.512628 end: 1.6.8.1 prepare-fit (duration 00:00:15) [common]
317 23:46:34.512775 end: 1.6.8 prepare-kernel (duration 00:00:15) [common]
318 23:46:34.512928 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 23:46:34.513069 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 23:46:34.513188 No LXC device requested
321 23:46:34.513308 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:46:34.513443 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 23:46:34.513571 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:46:34.513678 Checking files for TFTP limit of 4294967296 bytes.
325 23:46:34.514388 end: 1 tftp-deploy (duration 00:00:40) [common]
326 23:46:34.514544 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:46:34.514679 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:46:34.514852 substitutions:
329 23:46:34.514956 - {DTB}: 14172931/tftp-deploy-gt1vhnjs/dtb/mt8192-asurada-spherion-r0.dtb
330 23:46:34.515055 - {INITRD}: 14172931/tftp-deploy-gt1vhnjs/ramdisk/ramdisk.cpio.gz
331 23:46:34.515145 - {KERNEL}: 14172931/tftp-deploy-gt1vhnjs/kernel/Image
332 23:46:34.515240 - {LAVA_MAC}: None
333 23:46:34.515330 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14172931/extract-nfsrootfs-ivx2x1zz
334 23:46:34.515421 - {NFS_SERVER_IP}: 192.168.201.1
335 23:46:34.515508 - {PRESEED_CONFIG}: None
336 23:46:34.515602 - {PRESEED_LOCAL}: None
337 23:46:34.515691 - {RAMDISK}: 14172931/tftp-deploy-gt1vhnjs/ramdisk/ramdisk.cpio.gz
338 23:46:34.515780 - {ROOT_PART}: None
339 23:46:34.515867 - {ROOT}: None
340 23:46:34.515960 - {SERVER_IP}: 192.168.201.1
341 23:46:34.516049 - {TEE}: None
342 23:46:34.516144 Parsed boot commands:
343 23:46:34.516233 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:46:34.516493 Parsed boot commands: tftpboot 192.168.201.1 14172931/tftp-deploy-gt1vhnjs/kernel/image.itb 14172931/tftp-deploy-gt1vhnjs/kernel/cmdline
345 23:46:34.516631 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:46:34.516764 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:46:34.516900 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:46:34.517032 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:46:34.517148 Not connected, no need to disconnect.
350 23:46:34.517266 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:46:34.517390 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:46:34.517498 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 23:46:34.521757 Setting prompt string to ['lava-test: # ']
354 23:46:34.522253 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:46:34.522418 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:46:34.522558 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:46:34.522713 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:46:34.523024 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=reboot']
359 23:46:39.655380 >> Command sent successfully.
360 23:46:39.657777 Returned 0 in 5 seconds
361 23:46:39.758157 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:46:39.758491 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:46:39.758600 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:46:39.758695 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:46:39.758763 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:46:39.758832 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:46:39.759236 [Enter `^Ec?' for help]
369 23:46:39.931576
370 23:46:39.931762
371 23:46:39.931871 F0: 102B 0000
372 23:46:39.931974
373 23:46:39.932073 F3: 1001 0000 [0200]
374 23:46:39.932170
375 23:46:39.935116 F3: 1001 0000
376 23:46:39.935242
377 23:46:39.935353 F7: 102D 0000
378 23:46:39.935462
379 23:46:39.938008 F1: 0000 0000
380 23:46:39.938116
381 23:46:39.938221 V0: 0000 0000 [0001]
382 23:46:39.938327
383 23:46:39.938431 00: 0007 8000
384 23:46:39.941253
385 23:46:39.941361 01: 0000 0000
386 23:46:39.941472
387 23:46:39.941577 BP: 0C00 0209 [0000]
388 23:46:39.941679
389 23:46:39.944517 G0: 1182 0000
390 23:46:39.944597
391 23:46:39.944668 EC: 0000 0021 [4000]
392 23:46:39.944735
393 23:46:39.948578 S7: 0000 0000 [0000]
394 23:46:39.948653
395 23:46:39.948747 CC: 0000 0000 [0001]
396 23:46:39.951647
397 23:46:39.951756 T0: 0000 0040 [010F]
398 23:46:39.951857
399 23:46:39.951951 Jump to BL
400 23:46:39.952043
401 23:46:39.978132
402 23:46:39.978262
403 23:46:39.984585 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 23:46:39.988553 ARM64: Exception handlers installed.
405 23:46:39.991793 ARM64: Testing exception
406 23:46:39.995233 ARM64: Done test exception
407 23:46:40.001833 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 23:46:40.011916 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 23:46:40.019183 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 23:46:40.029515 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 23:46:40.036056 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 23:46:40.042526 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 23:46:40.054134 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 23:46:40.061047 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 23:46:40.080800 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 23:46:40.084074 WDT: Last reset was cold boot
417 23:46:40.087938 SPI1(PAD0) initialized at 2873684 Hz
418 23:46:40.091258 SPI5(PAD0) initialized at 992727 Hz
419 23:46:40.094434 VBOOT: Loading verstage.
420 23:46:40.101113 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 23:46:40.104360 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 23:46:40.107796 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 23:46:40.111006 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 23:46:40.118016 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 23:46:40.124991 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 23:46:40.135924 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
427 23:46:40.136011
428 23:46:40.136086
429 23:46:40.146104 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 23:46:40.149622 ARM64: Exception handlers installed.
431 23:46:40.153353 ARM64: Testing exception
432 23:46:40.153436 ARM64: Done test exception
433 23:46:40.160049 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 23:46:40.163219 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 23:46:40.176871 Probing TPM: . done!
436 23:46:40.176983 TPM ready after 0 ms
437 23:46:40.184209 Connected to device vid:did:rid of 1ae0:0028:00
438 23:46:40.190625 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
439 23:46:40.261670 Initialized TPM device CR50 revision 0
440 23:46:40.274057 tlcl_send_startup: Startup return code is 0
441 23:46:40.274198 TPM: setup succeeded
442 23:46:40.285613 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 23:46:40.295413 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 23:46:40.306452 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 23:46:40.316444 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 23:46:40.320036 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 23:46:40.323903 in-header: 03 07 00 00 08 00 00 00
448 23:46:40.327951 in-data: aa e4 47 04 13 02 00 00
449 23:46:40.328074 Chrome EC: UHEPI supported
450 23:46:40.334779 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 23:46:40.338866 in-header: 03 95 00 00 08 00 00 00
452 23:46:40.342212 in-data: 18 20 20 08 00 00 00 00
453 23:46:40.342324 Phase 1
454 23:46:40.346715 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 23:46:40.353838 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 23:46:40.361250 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 23:46:40.361374 Recovery requested (1009000e)
458 23:46:40.370951 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 23:46:40.376647 tlcl_extend: response is 0
460 23:46:40.385697 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 23:46:40.391809 tlcl_extend: response is 0
462 23:46:40.399083 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 23:46:40.417811 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
464 23:46:40.424876 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 23:46:40.424965
466 23:46:40.425036
467 23:46:40.435270 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 23:46:40.438676 ARM64: Exception handlers installed.
469 23:46:40.441971 ARM64: Testing exception
470 23:46:40.442085 ARM64: Done test exception
471 23:46:40.463764 pmic_efuse_setting: Set efuses in 11 msecs
472 23:46:40.467637 pmwrap_interface_init: Select PMIF_VLD_RDY
473 23:46:40.474829 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 23:46:40.478684 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 23:46:40.482506 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 23:46:40.485819 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 23:46:40.493324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 23:46:40.497350 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 23:46:40.500699 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 23:46:40.507926 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 23:46:40.511382 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 23:46:40.514696 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 23:46:40.522480 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 23:46:40.526599 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 23:46:40.530086 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 23:46:40.537099 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 23:46:40.541421 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 23:46:40.548615 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 23:46:40.552558 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 23:46:40.560577 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 23:46:40.564521 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 23:46:40.571609 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 23:46:40.575979 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 23:46:40.583209 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 23:46:40.586938 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 23:46:40.590708 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 23:46:40.597654 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 23:46:40.605279 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 23:46:40.609304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 23:46:40.612564 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 23:46:40.616512 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 23:46:40.623691 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 23:46:40.627451 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 23:46:40.631334 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 23:46:40.638522 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 23:46:40.642416 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 23:46:40.646298 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 23:46:40.653421 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 23:46:40.656948 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 23:46:40.664582 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 23:46:40.667708 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 23:46:40.671692 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 23:46:40.675886 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 23:46:40.679625 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 23:46:40.686734 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 23:46:40.689974 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 23:46:40.693803 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 23:46:40.697747 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 23:46:40.701186 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 23:46:40.705015 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 23:46:40.712691 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 23:46:40.716560 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 23:46:40.719942 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 23:46:40.727820 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 23:46:40.734793 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 23:46:40.738115 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 23:46:40.750223 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 23:46:40.757173 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 23:46:40.760819 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 23:46:40.764459 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 23:46:40.768603 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:46:40.777511 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x36
533 23:46:40.780708 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 23:46:40.789284 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 23:46:40.792318 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 23:46:40.801443 [RTC]rtc_get_frequency_meter,154: input=15, output=758
537 23:46:40.811532 [RTC]rtc_get_frequency_meter,154: input=23, output=942
538 23:46:40.820726 [RTC]rtc_get_frequency_meter,154: input=19, output=850
539 23:46:40.829294 [RTC]rtc_get_frequency_meter,154: input=17, output=805
540 23:46:40.839108 [RTC]rtc_get_frequency_meter,154: input=16, output=782
541 23:46:40.849064 [RTC]rtc_get_frequency_meter,154: input=16, output=783
542 23:46:40.859200 [RTC]rtc_get_frequency_meter,154: input=17, output=805
543 23:46:40.863245 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 23:46:40.867143 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 23:46:40.870546 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 23:46:40.874363 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
547 23:46:40.882361 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 23:46:40.886180 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
549 23:46:40.886273 ADC[4]: Raw value=906203 ID=7
550 23:46:40.889605 ADC[3]: Raw value=213441 ID=1
551 23:46:40.889697 RAM Code: 0x71
552 23:46:40.897353 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 23:46:40.901075 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 23:46:40.908724 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 23:46:40.915559 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 23:46:40.919458 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 23:46:40.923175 in-header: 03 07 00 00 08 00 00 00
558 23:46:40.927199 in-data: aa e4 47 04 13 02 00 00
559 23:46:40.930498 Chrome EC: UHEPI supported
560 23:46:40.934450 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 23:46:40.938383 in-header: 03 95 00 00 08 00 00 00
562 23:46:40.941628 in-data: 18 20 20 08 00 00 00 00
563 23:46:40.945780 MRC: failed to locate region type 0.
564 23:46:40.953092 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 23:46:40.957712 DRAM-K: Running full calibration
566 23:46:40.960997 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 23:46:40.964863 header.status = 0x0
568 23:46:40.968714 header.version = 0x6 (expected: 0x6)
569 23:46:40.968826 header.size = 0xd00 (expected: 0xd00)
570 23:46:40.972105 header.flags = 0x0
571 23:46:40.979405 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 23:46:40.996596 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
573 23:46:41.004116 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 23:46:41.004236 dram_init: ddr_geometry: 2
575 23:46:41.007661 [EMI] MDL number = 2
576 23:46:41.011147 [EMI] Get MDL freq = 0
577 23:46:41.011259 dram_init: ddr_type: 0
578 23:46:41.015084 is_discrete_lpddr4: 1
579 23:46:41.018511 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 23:46:41.018607
581 23:46:41.018694
582 23:46:41.018763 [Bian_co] ETT version 0.0.0.1
583 23:46:41.026465 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 23:46:41.026577
585 23:46:41.029830 dramc_set_vcore_voltage set vcore to 650000
586 23:46:41.029938 Read voltage for 800, 4
587 23:46:41.030039 Vio18 = 0
588 23:46:41.033697 Vcore = 650000
589 23:46:41.033806 Vdram = 0
590 23:46:41.033902 Vddq = 0
591 23:46:41.037455 Vmddr = 0
592 23:46:41.037575 dram_init: config_dvfs: 1
593 23:46:41.044540 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 23:46:41.048722 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 23:46:41.052718 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
596 23:46:41.055894 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
597 23:46:41.059722 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
598 23:46:41.063247 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
599 23:46:41.066443 MEM_TYPE=3, freq_sel=18
600 23:46:41.069756 sv_algorithm_assistance_LP4_1600
601 23:46:41.073145 ============ PULL DRAM RESETB DOWN ============
602 23:46:41.076573 ========== PULL DRAM RESETB DOWN end =========
603 23:46:41.080159 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 23:46:41.084167 ===================================
605 23:46:41.087471 LPDDR4 DRAM CONFIGURATION
606 23:46:41.091443 ===================================
607 23:46:41.091552 EX_ROW_EN[0] = 0x0
608 23:46:41.094891 EX_ROW_EN[1] = 0x0
609 23:46:41.095006 LP4Y_EN = 0x0
610 23:46:41.098298 WORK_FSP = 0x0
611 23:46:41.098377 WL = 0x2
612 23:46:41.101708 RL = 0x2
613 23:46:41.101815 BL = 0x2
614 23:46:41.105102 RPST = 0x0
615 23:46:41.105205 RD_PRE = 0x0
616 23:46:41.108622 WR_PRE = 0x1
617 23:46:41.111804 WR_PST = 0x0
618 23:46:41.111922 DBI_WR = 0x0
619 23:46:41.115088 DBI_RD = 0x0
620 23:46:41.115200 OTF = 0x1
621 23:46:41.118491 ===================================
622 23:46:41.122363 ===================================
623 23:46:41.122480 ANA top config
624 23:46:41.125505 ===================================
625 23:46:41.128546 DLL_ASYNC_EN = 0
626 23:46:41.131717 ALL_SLAVE_EN = 1
627 23:46:41.136460 NEW_RANK_MODE = 1
628 23:46:41.136580 DLL_IDLE_MODE = 1
629 23:46:41.139084 LP45_APHY_COMB_EN = 1
630 23:46:41.142894 TX_ODT_DIS = 1
631 23:46:41.145760 NEW_8X_MODE = 1
632 23:46:41.149281 ===================================
633 23:46:41.152597 ===================================
634 23:46:41.152705 data_rate = 1600
635 23:46:41.156163 CKR = 1
636 23:46:41.159241 DQ_P2S_RATIO = 8
637 23:46:41.162595 ===================================
638 23:46:41.166153 CA_P2S_RATIO = 8
639 23:46:41.169154 DQ_CA_OPEN = 0
640 23:46:41.172497 DQ_SEMI_OPEN = 0
641 23:46:41.172616 CA_SEMI_OPEN = 0
642 23:46:41.176215 CA_FULL_RATE = 0
643 23:46:41.179654 DQ_CKDIV4_EN = 1
644 23:46:41.182815 CA_CKDIV4_EN = 1
645 23:46:41.186239 CA_PREDIV_EN = 0
646 23:46:41.189469 PH8_DLY = 0
647 23:46:41.189573 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 23:46:41.192796 DQ_AAMCK_DIV = 4
649 23:46:41.196686 CA_AAMCK_DIV = 4
650 23:46:41.200052 CA_ADMCK_DIV = 4
651 23:46:41.200156 DQ_TRACK_CA_EN = 0
652 23:46:41.203873 CA_PICK = 800
653 23:46:41.207749 CA_MCKIO = 800
654 23:46:41.211723 MCKIO_SEMI = 0
655 23:46:41.215022 PLL_FREQ = 3068
656 23:46:41.215105 DQ_UI_PI_RATIO = 32
657 23:46:41.219133 CA_UI_PI_RATIO = 0
658 23:46:41.222044 ===================================
659 23:46:41.226045 ===================================
660 23:46:41.229945 memory_type:LPDDR4
661 23:46:41.230023 GP_NUM : 10
662 23:46:41.233782 SRAM_EN : 1
663 23:46:41.233888 MD32_EN : 0
664 23:46:41.236752 ===================================
665 23:46:41.240620 [ANA_INIT] >>>>>>>>>>>>>>
666 23:46:41.243711 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 23:46:41.246997 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 23:46:41.250116 ===================================
669 23:46:41.253427 data_rate = 1600,PCW = 0X7600
670 23:46:41.253517 ===================================
671 23:46:41.260073 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 23:46:41.263415 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 23:46:41.270600 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:46:41.273809 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 23:46:41.276828 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 23:46:41.280327 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:46:41.283709 [ANA_INIT] flow start
678 23:46:41.286893 [ANA_INIT] PLL >>>>>>>>
679 23:46:41.286998 [ANA_INIT] PLL <<<<<<<<
680 23:46:41.290811 [ANA_INIT] MIDPI >>>>>>>>
681 23:46:41.293761 [ANA_INIT] MIDPI <<<<<<<<
682 23:46:41.293872 [ANA_INIT] DLL >>>>>>>>
683 23:46:41.297222 [ANA_INIT] flow end
684 23:46:41.300224 ============ LP4 DIFF to SE enter ============
685 23:46:41.303699 ============ LP4 DIFF to SE exit ============
686 23:46:41.307142 [ANA_INIT] <<<<<<<<<<<<<
687 23:46:41.310308 [Flow] Enable top DCM control >>>>>
688 23:46:41.313659 [Flow] Enable top DCM control <<<<<
689 23:46:41.317079 Enable DLL master slave shuffle
690 23:46:41.323524 ==============================================================
691 23:46:41.323660 Gating Mode config
692 23:46:41.330756 ==============================================================
693 23:46:41.330864 Config description:
694 23:46:41.340813 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 23:46:41.346919 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 23:46:41.354117 SELPH_MODE 0: By rank 1: By Phase
697 23:46:41.357119 ==============================================================
698 23:46:41.360462 GAT_TRACK_EN = 1
699 23:46:41.363789 RX_GATING_MODE = 2
700 23:46:41.367255 RX_GATING_TRACK_MODE = 2
701 23:46:41.370783 SELPH_MODE = 1
702 23:46:41.373797 PICG_EARLY_EN = 1
703 23:46:41.377100 VALID_LAT_VALUE = 1
704 23:46:41.380449 ==============================================================
705 23:46:41.383756 Enter into Gating configuration >>>>
706 23:46:41.387081 Exit from Gating configuration <<<<
707 23:46:41.390466 Enter into DVFS_PRE_config >>>>>
708 23:46:41.404195 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 23:46:41.404313 Exit from DVFS_PRE_config <<<<<
710 23:46:41.407514 Enter into PICG configuration >>>>
711 23:46:41.410637 Exit from PICG configuration <<<<
712 23:46:41.414206 [RX_INPUT] configuration >>>>>
713 23:46:41.417219 [RX_INPUT] configuration <<<<<
714 23:46:41.423755 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 23:46:41.427545 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 23:46:41.433989 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 23:46:41.440996 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 23:46:41.447771 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 23:46:41.454401 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 23:46:41.457428 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 23:46:41.461104 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 23:46:41.464113 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 23:46:41.470751 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 23:46:41.474268 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 23:46:41.477625 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 23:46:41.480742 ===================================
727 23:46:41.484031 LPDDR4 DRAM CONFIGURATION
728 23:46:41.487309 ===================================
729 23:46:41.487411 EX_ROW_EN[0] = 0x0
730 23:46:41.491391 EX_ROW_EN[1] = 0x0
731 23:46:41.491475 LP4Y_EN = 0x0
732 23:46:41.494822 WORK_FSP = 0x0
733 23:46:41.494937 WL = 0x2
734 23:46:41.497266 RL = 0x2
735 23:46:41.500597 BL = 0x2
736 23:46:41.500695 RPST = 0x0
737 23:46:41.504754 RD_PRE = 0x0
738 23:46:41.504834 WR_PRE = 0x1
739 23:46:41.507805 WR_PST = 0x0
740 23:46:41.507913 DBI_WR = 0x0
741 23:46:41.510994 DBI_RD = 0x0
742 23:46:41.511074 OTF = 0x1
743 23:46:41.514317 ===================================
744 23:46:41.517944 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 23:46:41.524437 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 23:46:41.527760 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 23:46:41.531010 ===================================
748 23:46:41.534436 LPDDR4 DRAM CONFIGURATION
749 23:46:41.537626 ===================================
750 23:46:41.537715 EX_ROW_EN[0] = 0x10
751 23:46:41.540753 EX_ROW_EN[1] = 0x0
752 23:46:41.540840 LP4Y_EN = 0x0
753 23:46:41.544653 WORK_FSP = 0x0
754 23:46:41.544739 WL = 0x2
755 23:46:41.547533 RL = 0x2
756 23:46:41.547620 BL = 0x2
757 23:46:41.550696 RPST = 0x0
758 23:46:41.550786 RD_PRE = 0x0
759 23:46:41.554286 WR_PRE = 0x1
760 23:46:41.554409 WR_PST = 0x0
761 23:46:41.557461 DBI_WR = 0x0
762 23:46:41.557581 DBI_RD = 0x0
763 23:46:41.560686 OTF = 0x1
764 23:46:41.564269 ===================================
765 23:46:41.571072 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 23:46:41.574299 nWR fixed to 40
767 23:46:41.577411 [ModeRegInit_LP4] CH0 RK0
768 23:46:41.577518 [ModeRegInit_LP4] CH0 RK1
769 23:46:41.580895 [ModeRegInit_LP4] CH1 RK0
770 23:46:41.584772 [ModeRegInit_LP4] CH1 RK1
771 23:46:41.584853 match AC timing 13
772 23:46:41.591173 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 23:46:41.594169 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 23:46:41.597528 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 23:46:41.604173 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 23:46:41.607461 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 23:46:41.607542 [EMI DOE] emi_dcm 0
778 23:46:41.614706 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 23:46:41.614789 ==
780 23:46:41.618276 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:46:41.620904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:46:41.620983 ==
783 23:46:41.627531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 23:46:41.631393 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 23:46:41.641860 [CA 0] Center 36 (6~67) winsize 62
786 23:46:41.644590 [CA 1] Center 36 (6~67) winsize 62
787 23:46:41.647996 [CA 2] Center 34 (4~65) winsize 62
788 23:46:41.651493 [CA 3] Center 33 (3~64) winsize 62
789 23:46:41.655169 [CA 4] Center 33 (2~64) winsize 63
790 23:46:41.658257 [CA 5] Center 32 (2~62) winsize 61
791 23:46:41.658343
792 23:46:41.661524 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 23:46:41.661610
794 23:46:41.665151 [CATrainingPosCal] consider 1 rank data
795 23:46:41.668344 u2DelayCellTimex100 = 270/100 ps
796 23:46:41.671970 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
797 23:46:41.674639 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
798 23:46:41.681585 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
799 23:46:41.685117 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
800 23:46:41.688269 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
801 23:46:41.691642 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
802 23:46:41.691751
803 23:46:41.694798 CA PerBit enable=1, Macro0, CA PI delay=32
804 23:46:41.694903
805 23:46:41.698576 [CBTSetCACLKResult] CA Dly = 32
806 23:46:41.698685 CS Dly: 4 (0~35)
807 23:46:41.698792 ==
808 23:46:41.701760 Dram Type= 6, Freq= 0, CH_0, rank 1
809 23:46:41.708565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 23:46:41.708649 ==
811 23:46:41.711810 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 23:46:41.718385 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 23:46:41.728057 [CA 0] Center 36 (6~67) winsize 62
814 23:46:41.731116 [CA 1] Center 36 (6~67) winsize 62
815 23:46:41.734424 [CA 2] Center 34 (4~65) winsize 62
816 23:46:41.737730 [CA 3] Center 34 (3~65) winsize 63
817 23:46:41.741540 [CA 4] Center 33 (3~63) winsize 61
818 23:46:41.744756 [CA 5] Center 32 (2~63) winsize 62
819 23:46:41.744860
820 23:46:41.747992 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 23:46:41.748101
822 23:46:41.751192 [CATrainingPosCal] consider 2 rank data
823 23:46:41.754582 u2DelayCellTimex100 = 270/100 ps
824 23:46:41.757900 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
825 23:46:41.761200 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
826 23:46:41.767714 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
827 23:46:41.771712 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
828 23:46:41.774909 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
829 23:46:41.778088 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
830 23:46:41.778198
831 23:46:41.781996 CA PerBit enable=1, Macro0, CA PI delay=32
832 23:46:41.782106
833 23:46:41.786122 [CBTSetCACLKResult] CA Dly = 32
834 23:46:41.786238 CS Dly: 5 (0~37)
835 23:46:41.786338
836 23:46:41.789707 ----->DramcWriteLeveling(PI) begin...
837 23:46:41.789815 ==
838 23:46:41.793798 Dram Type= 6, Freq= 0, CH_0, rank 0
839 23:46:41.797151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 23:46:41.797251 ==
841 23:46:41.800577 Write leveling (Byte 0): 32 => 32
842 23:46:41.804035 Write leveling (Byte 1): 29 => 29
843 23:46:41.807453 DramcWriteLeveling(PI) end<-----
844 23:46:41.807557
845 23:46:41.807652 ==
846 23:46:41.810789 Dram Type= 6, Freq= 0, CH_0, rank 0
847 23:46:41.814698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 23:46:41.814815 ==
849 23:46:41.817856 [Gating] SW mode calibration
850 23:46:41.824192 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 23:46:41.827576 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 23:46:41.834131 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 23:46:41.837997 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 23:46:41.841232 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
855 23:46:41.847689 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:46:41.850901 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:46:41.854243 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:46:41.861492 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:46:41.864792 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:46:41.868181 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:46:41.874837 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:46:41.878168 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:46:41.881482 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:46:41.887746 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:46:41.891576 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:46:41.895002 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:46:41.898192 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:46:41.904941 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:46:41.907958 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
870 23:46:41.911545 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
871 23:46:41.917815 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 23:46:41.921505 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:46:41.924751 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:46:41.931196 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:46:41.935087 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:46:41.938329 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:46:41.944969 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:46:41.948250 0 9 8 | B1->B0 | 2322 3030 | 1 0 | (0 0) (1 1)
879 23:46:41.951446 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
880 23:46:41.958158 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 23:46:41.961727 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:46:41.964830 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:46:41.968333 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:46:41.974914 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:46:41.977984 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (1 0)
886 23:46:41.981824 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
887 23:46:41.988410 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
888 23:46:41.991486 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 23:46:41.994947 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:46:42.001247 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:46:42.005139 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:46:42.008380 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:46:42.014823 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
894 23:46:42.018383 0 11 8 | B1->B0 | 2a2a 4444 | 0 0 | (0 0) (0 0)
895 23:46:42.021891 0 11 12 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
896 23:46:42.028595 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 23:46:42.032022 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:46:42.035344 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:46:42.042134 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:46:42.045186 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:46:42.048524 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:46:42.051896 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
903 23:46:42.058200 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 23:46:42.062183 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:46:42.065280 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:46:42.072111 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:46:42.075279 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:46:42.078707 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:46:42.084949 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:46:42.088513 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:46:42.091581 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:46:42.098293 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:46:42.101745 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:46:42.105445 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:46:42.111515 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:46:42.114965 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:46:42.118816 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
918 23:46:42.124913 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
919 23:46:42.128230 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
920 23:46:42.132170 Total UI for P1: 0, mck2ui 16
921 23:46:42.135405 best dqsien dly found for B0: ( 0, 14, 6)
922 23:46:42.135519 Total UI for P1: 0, mck2ui 16
923 23:46:42.142483 best dqsien dly found for B1: ( 0, 14, 8)
924 23:46:42.145755 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
925 23:46:42.149069 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
926 23:46:42.149183
927 23:46:42.152505 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
928 23:46:42.155765 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 23:46:42.159209 [Gating] SW calibration Done
930 23:46:42.159347 ==
931 23:46:42.162309 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:46:42.165673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 23:46:42.165789 ==
934 23:46:42.168928 RX Vref Scan: 0
935 23:46:42.169038
936 23:46:42.169140 RX Vref 0 -> 0, step: 1
937 23:46:42.169243
938 23:46:42.172322 RX Delay -130 -> 252, step: 16
939 23:46:42.175634 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
940 23:46:42.182409 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
941 23:46:42.186232 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
942 23:46:42.188772 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
943 23:46:42.192073 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
944 23:46:42.195537 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
945 23:46:42.199171 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
946 23:46:42.206010 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
947 23:46:42.208840 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
948 23:46:42.212619 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
949 23:46:42.216221 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
950 23:46:42.219907 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
951 23:46:42.226524 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
952 23:46:42.229596 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
953 23:46:42.232866 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
954 23:46:42.236094 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
955 23:46:42.236205 ==
956 23:46:42.239588 Dram Type= 6, Freq= 0, CH_0, rank 0
957 23:46:42.246189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 23:46:42.246306 ==
959 23:46:42.246412 DQS Delay:
960 23:46:42.246488 DQS0 = 0, DQS1 = 0
961 23:46:42.249839 DQM Delay:
962 23:46:42.249939 DQM0 = 90, DQM1 = 84
963 23:46:42.253050 DQ Delay:
964 23:46:42.256449 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
965 23:46:42.259469 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
966 23:46:42.259580 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
967 23:46:42.266179 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
968 23:46:42.266289
969 23:46:42.266385
970 23:46:42.266479 ==
971 23:46:42.269979 Dram Type= 6, Freq= 0, CH_0, rank 0
972 23:46:42.273102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 23:46:42.273213 ==
974 23:46:42.273317
975 23:46:42.273413
976 23:46:42.276506 TX Vref Scan disable
977 23:46:42.276621 == TX Byte 0 ==
978 23:46:42.282678 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
979 23:46:42.286098 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
980 23:46:42.286207 == TX Byte 1 ==
981 23:46:42.292675 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
982 23:46:42.296056 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
983 23:46:42.296161 ==
984 23:46:42.299340 Dram Type= 6, Freq= 0, CH_0, rank 0
985 23:46:42.302621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 23:46:42.302702 ==
987 23:46:42.316965 TX Vref=22, minBit 8, minWin=27, winSum=448
988 23:46:42.320429 TX Vref=24, minBit 8, minWin=27, winSum=449
989 23:46:42.323678 TX Vref=26, minBit 0, minWin=28, winSum=455
990 23:46:42.326909 TX Vref=28, minBit 0, minWin=28, winSum=457
991 23:46:42.330356 TX Vref=30, minBit 5, minWin=28, winSum=459
992 23:46:42.333869 TX Vref=32, minBit 0, minWin=28, winSum=454
993 23:46:42.340194 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30
994 23:46:42.340278
995 23:46:42.344088 Final TX Range 1 Vref 30
996 23:46:42.344194
997 23:46:42.344288 ==
998 23:46:42.347424 Dram Type= 6, Freq= 0, CH_0, rank 0
999 23:46:42.350441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 23:46:42.350548 ==
1001 23:46:42.350642
1002 23:46:42.350742
1003 23:46:42.353594 TX Vref Scan disable
1004 23:46:42.357398 == TX Byte 0 ==
1005 23:46:42.360684 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1006 23:46:42.363669 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1007 23:46:42.367273 == TX Byte 1 ==
1008 23:46:42.370139 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1009 23:46:42.373809 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1010 23:46:42.373893
1011 23:46:42.376931 [DATLAT]
1012 23:46:42.377042 Freq=800, CH0 RK0
1013 23:46:42.377139
1014 23:46:42.380772 DATLAT Default: 0xa
1015 23:46:42.380882 0, 0xFFFF, sum = 0
1016 23:46:42.383999 1, 0xFFFF, sum = 0
1017 23:46:42.384113 2, 0xFFFF, sum = 0
1018 23:46:42.387518 3, 0xFFFF, sum = 0
1019 23:46:42.387613 4, 0xFFFF, sum = 0
1020 23:46:42.390919 5, 0xFFFF, sum = 0
1021 23:46:42.391025 6, 0xFFFF, sum = 0
1022 23:46:42.394100 7, 0xFFFF, sum = 0
1023 23:46:42.394205 8, 0xFFFF, sum = 0
1024 23:46:42.397583 9, 0x0, sum = 1
1025 23:46:42.397671 10, 0x0, sum = 2
1026 23:46:42.400736 11, 0x0, sum = 3
1027 23:46:42.400813 12, 0x0, sum = 4
1028 23:46:42.404024 best_step = 10
1029 23:46:42.404118
1030 23:46:42.404188 ==
1031 23:46:42.407499 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 23:46:42.410692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 23:46:42.410767 ==
1034 23:46:42.414074 RX Vref Scan: 1
1035 23:46:42.414152
1036 23:46:42.414217 Set Vref Range= 32 -> 127
1037 23:46:42.414278
1038 23:46:42.417109 RX Vref 32 -> 127, step: 1
1039 23:46:42.417193
1040 23:46:42.420425 RX Delay -95 -> 252, step: 8
1041 23:46:42.420510
1042 23:46:42.423765 Set Vref, RX VrefLevel [Byte0]: 32
1043 23:46:42.427073 [Byte1]: 32
1044 23:46:42.427157
1045 23:46:42.430927 Set Vref, RX VrefLevel [Byte0]: 33
1046 23:46:42.433606 [Byte1]: 33
1047 23:46:42.437462
1048 23:46:42.437546 Set Vref, RX VrefLevel [Byte0]: 34
1049 23:46:42.440648 [Byte1]: 34
1050 23:46:42.444750
1051 23:46:42.444861 Set Vref, RX VrefLevel [Byte0]: 35
1052 23:46:42.448481 [Byte1]: 35
1053 23:46:42.453100
1054 23:46:42.453185 Set Vref, RX VrefLevel [Byte0]: 36
1055 23:46:42.456345 [Byte1]: 36
1056 23:46:42.460161
1057 23:46:42.460266 Set Vref, RX VrefLevel [Byte0]: 37
1058 23:46:42.463427 [Byte1]: 37
1059 23:46:42.467909
1060 23:46:42.468017 Set Vref, RX VrefLevel [Byte0]: 38
1061 23:46:42.471127 [Byte1]: 38
1062 23:46:42.476137
1063 23:46:42.476253 Set Vref, RX VrefLevel [Byte0]: 39
1064 23:46:42.479007 [Byte1]: 39
1065 23:46:42.482669
1066 23:46:42.482781 Set Vref, RX VrefLevel [Byte0]: 40
1067 23:46:42.486070 [Byte1]: 40
1068 23:46:42.490028
1069 23:46:42.490113 Set Vref, RX VrefLevel [Byte0]: 41
1070 23:46:42.493679 [Byte1]: 41
1071 23:46:42.497695
1072 23:46:42.497802 Set Vref, RX VrefLevel [Byte0]: 42
1073 23:46:42.500860 [Byte1]: 42
1074 23:46:42.505824
1075 23:46:42.505932 Set Vref, RX VrefLevel [Byte0]: 43
1076 23:46:42.509009 [Byte1]: 43
1077 23:46:42.513000
1078 23:46:42.513105 Set Vref, RX VrefLevel [Byte0]: 44
1079 23:46:42.516344 [Byte1]: 44
1080 23:46:42.520847
1081 23:46:42.520951 Set Vref, RX VrefLevel [Byte0]: 45
1082 23:46:42.523968 [Byte1]: 45
1083 23:46:42.528734
1084 23:46:42.528838 Set Vref, RX VrefLevel [Byte0]: 46
1085 23:46:42.531856 [Byte1]: 46
1086 23:46:42.535863
1087 23:46:42.535968 Set Vref, RX VrefLevel [Byte0]: 47
1088 23:46:42.539233 [Byte1]: 47
1089 23:46:42.543715
1090 23:46:42.543833 Set Vref, RX VrefLevel [Byte0]: 48
1091 23:46:42.546611 [Byte1]: 48
1092 23:46:42.551037
1093 23:46:42.551115 Set Vref, RX VrefLevel [Byte0]: 49
1094 23:46:42.554444 [Byte1]: 49
1095 23:46:42.558632
1096 23:46:42.558744 Set Vref, RX VrefLevel [Byte0]: 50
1097 23:46:42.561763 [Byte1]: 50
1098 23:46:42.566506
1099 23:46:42.566596 Set Vref, RX VrefLevel [Byte0]: 51
1100 23:46:42.569723 [Byte1]: 51
1101 23:46:42.573916
1102 23:46:42.573999 Set Vref, RX VrefLevel [Byte0]: 52
1103 23:46:42.577164 [Byte1]: 52
1104 23:46:42.581289
1105 23:46:42.581370 Set Vref, RX VrefLevel [Byte0]: 53
1106 23:46:42.584739 [Byte1]: 53
1107 23:46:42.589189
1108 23:46:42.589269 Set Vref, RX VrefLevel [Byte0]: 54
1109 23:46:42.592540 [Byte1]: 54
1110 23:46:42.596991
1111 23:46:42.597100 Set Vref, RX VrefLevel [Byte0]: 55
1112 23:46:42.599981 [Byte1]: 55
1113 23:46:42.604053
1114 23:46:42.604160 Set Vref, RX VrefLevel [Byte0]: 56
1115 23:46:42.607247 [Byte1]: 56
1116 23:46:42.612086
1117 23:46:42.612205 Set Vref, RX VrefLevel [Byte0]: 57
1118 23:46:42.615060 [Byte1]: 57
1119 23:46:42.619728
1120 23:46:42.619844 Set Vref, RX VrefLevel [Byte0]: 58
1121 23:46:42.622970 [Byte1]: 58
1122 23:46:42.627016
1123 23:46:42.627126 Set Vref, RX VrefLevel [Byte0]: 59
1124 23:46:42.630120 [Byte1]: 59
1125 23:46:42.634712
1126 23:46:42.634819 Set Vref, RX VrefLevel [Byte0]: 60
1127 23:46:42.638095 [Byte1]: 60
1128 23:46:42.642572
1129 23:46:42.642679 Set Vref, RX VrefLevel [Byte0]: 61
1130 23:46:42.645808 [Byte1]: 61
1131 23:46:42.649764
1132 23:46:42.649876 Set Vref, RX VrefLevel [Byte0]: 62
1133 23:46:42.653044 [Byte1]: 62
1134 23:46:42.657789
1135 23:46:42.657902 Set Vref, RX VrefLevel [Byte0]: 63
1136 23:46:42.661069 [Byte1]: 63
1137 23:46:42.665065
1138 23:46:42.665142 Set Vref, RX VrefLevel [Byte0]: 64
1139 23:46:42.668417 [Byte1]: 64
1140 23:46:42.672572
1141 23:46:42.672650 Set Vref, RX VrefLevel [Byte0]: 65
1142 23:46:42.676264 [Byte1]: 65
1143 23:46:42.680171
1144 23:46:42.680278 Set Vref, RX VrefLevel [Byte0]: 66
1145 23:46:42.683481 [Byte1]: 66
1146 23:46:42.687754
1147 23:46:42.687845 Set Vref, RX VrefLevel [Byte0]: 67
1148 23:46:42.690958 [Byte1]: 67
1149 23:46:42.695249
1150 23:46:42.695353 Set Vref, RX VrefLevel [Byte0]: 68
1151 23:46:42.698975 [Byte1]: 68
1152 23:46:42.703375
1153 23:46:42.703454 Set Vref, RX VrefLevel [Byte0]: 69
1154 23:46:42.706330 [Byte1]: 69
1155 23:46:42.710486
1156 23:46:42.710573 Set Vref, RX VrefLevel [Byte0]: 70
1157 23:46:42.714115 [Byte1]: 70
1158 23:46:42.718163
1159 23:46:42.718273 Set Vref, RX VrefLevel [Byte0]: 71
1160 23:46:42.721675 [Byte1]: 71
1161 23:46:42.725632
1162 23:46:42.725711 Set Vref, RX VrefLevel [Byte0]: 72
1163 23:46:42.729064 [Byte1]: 72
1164 23:46:42.733823
1165 23:46:42.733902 Set Vref, RX VrefLevel [Byte0]: 73
1166 23:46:42.736487 [Byte1]: 73
1167 23:46:42.741103
1168 23:46:42.741212 Set Vref, RX VrefLevel [Byte0]: 74
1169 23:46:42.744220 [Byte1]: 74
1170 23:46:42.748897
1171 23:46:42.748994 Set Vref, RX VrefLevel [Byte0]: 75
1172 23:46:42.752173 [Byte1]: 75
1173 23:46:42.756212
1174 23:46:42.756326 Set Vref, RX VrefLevel [Byte0]: 76
1175 23:46:42.759530 [Byte1]: 76
1176 23:46:42.764175
1177 23:46:42.764288 Set Vref, RX VrefLevel [Byte0]: 77
1178 23:46:42.767653 [Byte1]: 77
1179 23:46:42.771672
1180 23:46:42.771785 Set Vref, RX VrefLevel [Byte0]: 78
1181 23:46:42.775062 [Byte1]: 78
1182 23:46:42.779434
1183 23:46:42.779548 Final RX Vref Byte 0 = 52 to rank0
1184 23:46:42.782745 Final RX Vref Byte 1 = 60 to rank0
1185 23:46:42.786001 Final RX Vref Byte 0 = 52 to rank1
1186 23:46:42.789227 Final RX Vref Byte 1 = 60 to rank1==
1187 23:46:42.792530 Dram Type= 6, Freq= 0, CH_0, rank 0
1188 23:46:42.799191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 23:46:42.799312 ==
1190 23:46:42.799410 DQS Delay:
1191 23:46:42.799502 DQS0 = 0, DQS1 = 0
1192 23:46:42.802653 DQM Delay:
1193 23:46:42.802731 DQM0 = 91, DQM1 = 84
1194 23:46:42.805834 DQ Delay:
1195 23:46:42.809690 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1196 23:46:42.809796 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1197 23:46:42.812827 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1198 23:46:42.818876 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1199 23:46:42.818978
1200 23:46:42.819044
1201 23:46:42.825978 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1202 23:46:42.829687 CH0 RK0: MR19=606, MR18=4B41
1203 23:46:42.835773 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1204 23:46:42.835884
1205 23:46:42.838862 ----->DramcWriteLeveling(PI) begin...
1206 23:46:42.838968 ==
1207 23:46:42.842176 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 23:46:42.845883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 23:46:42.845989 ==
1210 23:46:42.849083 Write leveling (Byte 0): 34 => 34
1211 23:46:42.893112 Write leveling (Byte 1): 32 => 32
1212 23:46:42.893214 DramcWriteLeveling(PI) end<-----
1213 23:46:42.893284
1214 23:46:42.893347 ==
1215 23:46:42.893761 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 23:46:42.894044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 23:46:42.894140 ==
1218 23:46:42.894229 [Gating] SW mode calibration
1219 23:46:42.894332 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1220 23:46:42.894424 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1221 23:46:42.894512 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1222 23:46:42.894614 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 23:46:42.894717 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1224 23:46:42.937563 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:46:42.937663 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 23:46:42.937915 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:46:42.937985 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:46:42.938059 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:46:42.938529 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:46:42.938614 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:46:42.938859 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:46:42.938936 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:46:42.939007 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:46:42.942291 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:46:42.942363 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:46:42.949379 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:46:42.952399 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:46:42.955665 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1239 23:46:42.962731 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1240 23:46:42.965658 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:46:42.969047 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 23:46:42.975295 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:46:42.979085 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:46:42.982505 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:46:42.988891 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 23:46:42.992630 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 23:46:42.995943 0 9 8 | B1->B0 | 3030 2d2d | 0 0 | (0 0) (0 0)
1248 23:46:43.002443 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 23:46:43.005796 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 23:46:43.009007 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 23:46:43.015806 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 23:46:43.019000 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 23:46:43.022966 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 23:46:43.026316 0 10 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1255 23:46:43.034199 0 10 8 | B1->B0 | 2727 2525 | 1 0 | (0 0) (0 0)
1256 23:46:43.037500 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 23:46:43.041444 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 23:46:43.044678 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 23:46:43.051466 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 23:46:43.054880 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 23:46:43.058073 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 23:46:43.061823 0 11 4 | B1->B0 | 2a2a 2323 | 1 0 | (0 0) (0 0)
1263 23:46:43.068511 0 11 8 | B1->B0 | 3d3d 3d3d | 0 0 | (0 0) (0 0)
1264 23:46:43.071877 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 23:46:43.074691 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 23:46:43.081910 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 23:46:43.084903 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 23:46:43.088465 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 23:46:43.095276 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 23:46:43.098698 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 23:46:43.101850 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1272 23:46:43.104968 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1273 23:46:43.111593 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 23:46:43.115557 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:46:43.118258 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:46:43.125313 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:46:43.128695 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:46:43.131900 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:46:43.138441 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 23:46:43.141792 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 23:46:43.145048 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:46:43.151815 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:46:43.155719 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:46:43.159217 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 23:46:43.165255 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 23:46:43.169082 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 23:46:43.171878 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1288 23:46:43.175659 Total UI for P1: 0, mck2ui 16
1289 23:46:43.178672 best dqsien dly found for B1: ( 0, 14, 6)
1290 23:46:43.182215 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1291 23:46:43.185691 Total UI for P1: 0, mck2ui 16
1292 23:46:43.189266 best dqsien dly found for B0: ( 0, 14, 8)
1293 23:46:43.192585 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1294 23:46:43.195780 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1295 23:46:43.195876
1296 23:46:43.202176 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1297 23:46:43.205716 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1298 23:46:43.205829 [Gating] SW calibration Done
1299 23:46:43.209120 ==
1300 23:46:43.209201 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 23:46:43.216296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 23:46:43.216399 ==
1303 23:46:43.216468 RX Vref Scan: 0
1304 23:46:43.216535
1305 23:46:43.219372 RX Vref 0 -> 0, step: 1
1306 23:46:43.219479
1307 23:46:43.222545 RX Delay -130 -> 252, step: 16
1308 23:46:43.225853 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1309 23:46:43.229231 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1310 23:46:43.232872 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1311 23:46:43.239764 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1312 23:46:43.242783 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1313 23:46:43.246106 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1314 23:46:43.249503 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1315 23:46:43.252823 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
1316 23:46:43.256131 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1317 23:46:43.262521 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
1318 23:46:43.265870 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1319 23:46:43.269310 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1320 23:46:43.272815 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1321 23:46:43.279509 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1322 23:46:43.282661 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1323 23:46:43.286018 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1324 23:46:43.286134 ==
1325 23:46:43.289661 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 23:46:43.292599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 23:46:43.292708 ==
1328 23:46:43.296122 DQS Delay:
1329 23:46:43.296216 DQS0 = 0, DQS1 = 0
1330 23:46:43.296337 DQM Delay:
1331 23:46:43.299145 DQM0 = 93, DQM1 = 83
1332 23:46:43.299244 DQ Delay:
1333 23:46:43.302838 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1334 23:46:43.306022 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1335 23:46:43.309551 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1336 23:46:43.312550 DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85
1337 23:46:43.312625
1338 23:46:43.312688
1339 23:46:43.312749 ==
1340 23:46:43.315938 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 23:46:43.322861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 23:46:43.322969 ==
1343 23:46:43.323064
1344 23:46:43.323159
1345 23:46:43.323251 TX Vref Scan disable
1346 23:46:43.326854 == TX Byte 0 ==
1347 23:46:43.329929 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1348 23:46:43.336506 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1349 23:46:43.336597 == TX Byte 1 ==
1350 23:46:43.339494 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1351 23:46:43.346739 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1352 23:46:43.346847 ==
1353 23:46:43.350010 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 23:46:43.353290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 23:46:43.353395 ==
1356 23:46:43.365601 TX Vref=22, minBit 8, minWin=27, winSum=450
1357 23:46:43.369121 TX Vref=24, minBit 10, minWin=27, winSum=451
1358 23:46:43.372233 TX Vref=26, minBit 1, minWin=28, winSum=456
1359 23:46:43.376016 TX Vref=28, minBit 1, minWin=28, winSum=455
1360 23:46:43.379238 TX Vref=30, minBit 2, minWin=28, winSum=454
1361 23:46:43.382926 TX Vref=32, minBit 8, minWin=27, winSum=450
1362 23:46:43.389308 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 26
1363 23:46:43.389426
1364 23:46:43.392541 Final TX Range 1 Vref 26
1365 23:46:43.392645
1366 23:46:43.392737 ==
1367 23:46:43.396649 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 23:46:43.399608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 23:46:43.399712 ==
1370 23:46:43.399806
1371 23:46:43.399896
1372 23:46:43.402705 TX Vref Scan disable
1373 23:46:43.405727 == TX Byte 0 ==
1374 23:46:43.409318 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1375 23:46:43.412438 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1376 23:46:43.416237 == TX Byte 1 ==
1377 23:46:43.419246 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1378 23:46:43.422557 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1379 23:46:43.422662
1380 23:46:43.425783 [DATLAT]
1381 23:46:43.425885 Freq=800, CH0 RK1
1382 23:46:43.425978
1383 23:46:43.429621 DATLAT Default: 0xa
1384 23:46:43.429726 0, 0xFFFF, sum = 0
1385 23:46:43.432787 1, 0xFFFF, sum = 0
1386 23:46:43.432862 2, 0xFFFF, sum = 0
1387 23:46:43.435888 3, 0xFFFF, sum = 0
1388 23:46:43.435963 4, 0xFFFF, sum = 0
1389 23:46:43.439384 5, 0xFFFF, sum = 0
1390 23:46:43.439495 6, 0xFFFF, sum = 0
1391 23:46:43.442491 7, 0xFFFF, sum = 0
1392 23:46:43.442598 8, 0xFFFF, sum = 0
1393 23:46:43.446019 9, 0x0, sum = 1
1394 23:46:43.446097 10, 0x0, sum = 2
1395 23:46:43.449499 11, 0x0, sum = 3
1396 23:46:43.449579 12, 0x0, sum = 4
1397 23:46:43.452906 best_step = 10
1398 23:46:43.452980
1399 23:46:43.453076 ==
1400 23:46:43.455774 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 23:46:43.459348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 23:46:43.459453 ==
1403 23:46:43.462809 RX Vref Scan: 0
1404 23:46:43.462912
1405 23:46:43.463008 RX Vref 0 -> 0, step: 1
1406 23:46:43.463098
1407 23:46:43.466264 RX Delay -79 -> 252, step: 8
1408 23:46:43.472818 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1409 23:46:43.475905 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1410 23:46:43.479183 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1411 23:46:43.483017 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1412 23:46:43.486240 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1413 23:46:43.492998 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1414 23:46:43.496117 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1415 23:46:43.499411 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1416 23:46:43.502722 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1417 23:46:43.506060 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1418 23:46:43.509644 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1419 23:46:43.516096 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1420 23:46:43.519618 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1421 23:46:43.522655 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1422 23:46:43.526214 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1423 23:46:43.532488 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1424 23:46:43.532593 ==
1425 23:46:43.536485 Dram Type= 6, Freq= 0, CH_0, rank 1
1426 23:46:43.539773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 23:46:43.539874 ==
1428 23:46:43.539967 DQS Delay:
1429 23:46:43.542944 DQS0 = 0, DQS1 = 0
1430 23:46:43.543041 DQM Delay:
1431 23:46:43.546113 DQM0 = 92, DQM1 = 84
1432 23:46:43.546247 DQ Delay:
1433 23:46:43.549755 DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88
1434 23:46:43.552890 DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100
1435 23:46:43.556303 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1436 23:46:43.559287 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1437 23:46:43.559388
1438 23:46:43.559479
1439 23:46:43.566081 [DQSOSCAuto] RK1, (LSB)MR18= 0x4718, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
1440 23:46:43.569506 CH0 RK1: MR19=606, MR18=4718
1441 23:46:43.576570 CH0_RK1: MR19=0x606, MR18=0x4718, DQSOSC=392, MR23=63, INC=96, DEC=64
1442 23:46:43.579898 [RxdqsGatingPostProcess] freq 800
1443 23:46:43.583371 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1444 23:46:43.586445 Pre-setting of DQS Precalculation
1445 23:46:43.593220 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1446 23:46:43.593324 ==
1447 23:46:43.596244 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 23:46:43.599787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 23:46:43.599888 ==
1450 23:46:43.606058 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 23:46:43.612720 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 23:46:43.620681 [CA 0] Center 36 (6~67) winsize 62
1453 23:46:43.624467 [CA 1] Center 36 (6~67) winsize 62
1454 23:46:43.627499 [CA 2] Center 34 (4~65) winsize 62
1455 23:46:43.631075 [CA 3] Center 34 (4~65) winsize 62
1456 23:46:43.633918 [CA 4] Center 35 (5~65) winsize 61
1457 23:46:43.637698 [CA 5] Center 34 (4~65) winsize 62
1458 23:46:43.637803
1459 23:46:43.641274 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1460 23:46:43.641378
1461 23:46:43.644500 [CATrainingPosCal] consider 1 rank data
1462 23:46:43.647778 u2DelayCellTimex100 = 270/100 ps
1463 23:46:43.651127 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 23:46:43.654267 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1465 23:46:43.657983 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 23:46:43.664220 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 23:46:43.667627 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1468 23:46:43.670863 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1469 23:46:43.670964
1470 23:46:43.674182 CA PerBit enable=1, Macro0, CA PI delay=34
1471 23:46:43.674283
1472 23:46:43.677304 [CBTSetCACLKResult] CA Dly = 34
1473 23:46:43.677377 CS Dly: 6 (0~37)
1474 23:46:43.677440 ==
1475 23:46:43.681020 Dram Type= 6, Freq= 0, CH_1, rank 1
1476 23:46:43.687828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 23:46:43.687934 ==
1478 23:46:43.691522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1479 23:46:43.698820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1480 23:46:43.707547 [CA 0] Center 36 (6~67) winsize 62
1481 23:46:43.711125 [CA 1] Center 37 (6~68) winsize 63
1482 23:46:43.714543 [CA 2] Center 35 (4~66) winsize 63
1483 23:46:43.718521 [CA 3] Center 34 (4~65) winsize 62
1484 23:46:43.722543 [CA 4] Center 35 (5~66) winsize 62
1485 23:46:43.722647 [CA 5] Center 34 (4~65) winsize 62
1486 23:46:43.722738
1487 23:46:43.729063 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1488 23:46:43.729166
1489 23:46:43.732458 [CATrainingPosCal] consider 2 rank data
1490 23:46:43.735737 u2DelayCellTimex100 = 270/100 ps
1491 23:46:43.739528 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1492 23:46:43.742545 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 23:46:43.746044 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 23:46:43.749342 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 23:46:43.752783 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1496 23:46:43.755873 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1497 23:46:43.755980
1498 23:46:43.759732 CA PerBit enable=1, Macro0, CA PI delay=34
1499 23:46:43.759833
1500 23:46:43.762942 [CBTSetCACLKResult] CA Dly = 34
1501 23:46:43.765948 CS Dly: 6 (0~38)
1502 23:46:43.766066
1503 23:46:43.769435 ----->DramcWriteLeveling(PI) begin...
1504 23:46:43.769511 ==
1505 23:46:43.772867 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 23:46:43.776100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 23:46:43.776205 ==
1508 23:46:43.779238 Write leveling (Byte 0): 25 => 25
1509 23:46:43.783183 Write leveling (Byte 1): 28 => 28
1510 23:46:43.786510 DramcWriteLeveling(PI) end<-----
1511 23:46:43.786613
1512 23:46:43.786704 ==
1513 23:46:43.789875 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 23:46:43.793068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 23:46:43.793188 ==
1516 23:46:43.796039 [Gating] SW mode calibration
1517 23:46:43.802970 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1518 23:46:43.809398 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1519 23:46:43.813151 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1520 23:46:43.816185 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:46:43.823239 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1522 23:46:43.825966 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:46:43.829733 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:46:43.836266 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:46:43.839808 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:46:43.843191 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:46:43.849772 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:46:43.852838 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:46:43.856003 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:46:43.860070 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:46:43.866264 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:46:43.869430 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:46:43.872614 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:46:43.879455 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1535 23:46:43.882936 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:46:43.886288 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1537 23:46:43.892707 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:46:43.896146 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:46:43.899334 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:46:43.906458 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:46:43.909513 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:46:43.913156 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 23:46:43.919974 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:46:43.923219 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1545 23:46:43.926915 0 9 8 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1546 23:46:43.932753 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 23:46:43.936101 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 23:46:43.939447 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 23:46:43.943662 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 23:46:43.950118 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 23:46:43.953344 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1552 23:46:43.956508 0 10 4 | B1->B0 | 3131 2e2e | 0 0 | (0 1) (0 1)
1553 23:46:43.963128 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1554 23:46:43.966220 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 23:46:43.969876 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 23:46:43.976505 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 23:46:43.980198 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 23:46:43.983542 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 23:46:43.989830 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1560 23:46:43.993602 0 11 4 | B1->B0 | 2e2e 3a3a | 0 0 | (0 0) (0 0)
1561 23:46:43.996666 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1562 23:46:44.003188 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 23:46:44.007019 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 23:46:44.009709 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 23:46:44.013544 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 23:46:44.019905 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 23:46:44.023856 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 23:46:44.026608 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1569 23:46:44.033397 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 23:46:44.036574 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 23:46:44.039747 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:46:44.046725 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:46:44.050081 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:46:44.053603 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:46:44.060110 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:46:44.063283 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:46:44.066636 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:46:44.072877 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:46:44.076291 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 23:46:44.079546 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:46:44.086212 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 23:46:44.089868 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 23:46:44.093180 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1584 23:46:44.099489 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1585 23:46:44.103105 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1586 23:46:44.106506 Total UI for P1: 0, mck2ui 16
1587 23:46:44.109763 best dqsien dly found for B0: ( 0, 14, 2)
1588 23:46:44.112932 Total UI for P1: 0, mck2ui 16
1589 23:46:44.116298 best dqsien dly found for B1: ( 0, 14, 4)
1590 23:46:44.119441 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1591 23:46:44.122847 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1592 23:46:44.122949
1593 23:46:44.126124 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1594 23:46:44.129450 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1595 23:46:44.132770 [Gating] SW calibration Done
1596 23:46:44.132874 ==
1597 23:46:44.136423 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 23:46:44.139541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 23:46:44.139648 ==
1600 23:46:44.142973 RX Vref Scan: 0
1601 23:46:44.143075
1602 23:46:44.146311 RX Vref 0 -> 0, step: 1
1603 23:46:44.146412
1604 23:46:44.146513 RX Delay -130 -> 252, step: 16
1605 23:46:44.152997 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1606 23:46:44.156431 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1607 23:46:44.159469 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1608 23:46:44.163394 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1609 23:46:44.166499 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1610 23:46:44.173380 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1611 23:46:44.176241 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1612 23:46:44.180103 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1613 23:46:44.183410 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1614 23:46:44.186842 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1615 23:46:44.189853 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1616 23:46:44.196540 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1617 23:46:44.200179 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1618 23:46:44.203458 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1619 23:46:44.206509 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1620 23:46:44.213136 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1621 23:46:44.213215 ==
1622 23:46:44.216599 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 23:46:44.220147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 23:46:44.220266 ==
1625 23:46:44.220365 DQS Delay:
1626 23:46:44.223448 DQS0 = 0, DQS1 = 0
1627 23:46:44.223518 DQM Delay:
1628 23:46:44.226746 DQM0 = 94, DQM1 = 91
1629 23:46:44.226841 DQ Delay:
1630 23:46:44.229935 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1631 23:46:44.233292 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1632 23:46:44.236661 DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85
1633 23:46:44.239982 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1634 23:46:44.240090
1635 23:46:44.240207
1636 23:46:44.240303 ==
1637 23:46:44.243349 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 23:46:44.246415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 23:46:44.246509 ==
1640 23:46:44.246599
1641 23:46:44.249747
1642 23:46:44.249841 TX Vref Scan disable
1643 23:46:44.253291 == TX Byte 0 ==
1644 23:46:44.256284 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1645 23:46:44.260027 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1646 23:46:44.263533 == TX Byte 1 ==
1647 23:46:44.267434 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1648 23:46:44.270876 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1649 23:46:44.270980 ==
1650 23:46:44.273916 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 23:46:44.277582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 23:46:44.277696 ==
1653 23:46:44.291790 TX Vref=22, minBit 1, minWin=26, winSum=438
1654 23:46:44.295120 TX Vref=24, minBit 0, minWin=26, winSum=436
1655 23:46:44.298447 TX Vref=26, minBit 0, minWin=27, winSum=448
1656 23:46:44.301709 TX Vref=28, minBit 1, minWin=27, winSum=450
1657 23:46:44.305250 TX Vref=30, minBit 0, minWin=27, winSum=447
1658 23:46:44.308489 TX Vref=32, minBit 1, minWin=27, winSum=448
1659 23:46:44.315112 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 28
1660 23:46:44.315232
1661 23:46:44.318414 Final TX Range 1 Vref 28
1662 23:46:44.318517
1663 23:46:44.318610 ==
1664 23:46:44.321866 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 23:46:44.325721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 23:46:44.325826 ==
1667 23:46:44.325921
1668 23:46:44.326020
1669 23:46:44.328608 TX Vref Scan disable
1670 23:46:44.331915 == TX Byte 0 ==
1671 23:46:44.335434 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1672 23:46:44.338711 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1673 23:46:44.341989 == TX Byte 1 ==
1674 23:46:44.345563 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1675 23:46:44.348873 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1676 23:46:44.348954
1677 23:46:44.352112 [DATLAT]
1678 23:46:44.352192 Freq=800, CH1 RK0
1679 23:46:44.352285
1680 23:46:44.355348 DATLAT Default: 0xa
1681 23:46:44.355450 0, 0xFFFF, sum = 0
1682 23:46:44.358582 1, 0xFFFF, sum = 0
1683 23:46:44.358683 2, 0xFFFF, sum = 0
1684 23:46:44.362413 3, 0xFFFF, sum = 0
1685 23:46:44.362519 4, 0xFFFF, sum = 0
1686 23:46:44.365739 5, 0xFFFF, sum = 0
1687 23:46:44.365817 6, 0xFFFF, sum = 0
1688 23:46:44.369076 7, 0xFFFF, sum = 0
1689 23:46:44.369179 8, 0xFFFF, sum = 0
1690 23:46:44.372400 9, 0x0, sum = 1
1691 23:46:44.372507 10, 0x0, sum = 2
1692 23:46:44.375575 11, 0x0, sum = 3
1693 23:46:44.375656 12, 0x0, sum = 4
1694 23:46:44.378943 best_step = 10
1695 23:46:44.379020
1696 23:46:44.379083 ==
1697 23:46:44.382244 Dram Type= 6, Freq= 0, CH_1, rank 0
1698 23:46:44.385711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1699 23:46:44.385792 ==
1700 23:46:44.389064 RX Vref Scan: 1
1701 23:46:44.389152
1702 23:46:44.389220 Set Vref Range= 32 -> 127
1703 23:46:44.389285
1704 23:46:44.392053 RX Vref 32 -> 127, step: 1
1705 23:46:44.392125
1706 23:46:44.395677 RX Delay -63 -> 252, step: 8
1707 23:46:44.395762
1708 23:46:44.398684 Set Vref, RX VrefLevel [Byte0]: 32
1709 23:46:44.402070 [Byte1]: 32
1710 23:46:44.402154
1711 23:46:44.405323 Set Vref, RX VrefLevel [Byte0]: 33
1712 23:46:44.408582 [Byte1]: 33
1713 23:46:44.408667
1714 23:46:44.412309 Set Vref, RX VrefLevel [Byte0]: 34
1715 23:46:44.415342 [Byte1]: 34
1716 23:46:44.419603
1717 23:46:44.419687 Set Vref, RX VrefLevel [Byte0]: 35
1718 23:46:44.422487 [Byte1]: 35
1719 23:46:44.426915
1720 23:46:44.426999 Set Vref, RX VrefLevel [Byte0]: 36
1721 23:46:44.429909 [Byte1]: 36
1722 23:46:44.434470
1723 23:46:44.434554 Set Vref, RX VrefLevel [Byte0]: 37
1724 23:46:44.437804 [Byte1]: 37
1725 23:46:44.441981
1726 23:46:44.442065 Set Vref, RX VrefLevel [Byte0]: 38
1727 23:46:44.445204 [Byte1]: 38
1728 23:46:44.449219
1729 23:46:44.449311 Set Vref, RX VrefLevel [Byte0]: 39
1730 23:46:44.452536 [Byte1]: 39
1731 23:46:44.457133
1732 23:46:44.457213 Set Vref, RX VrefLevel [Byte0]: 40
1733 23:46:44.460433 [Byte1]: 40
1734 23:46:44.464308
1735 23:46:44.464400 Set Vref, RX VrefLevel [Byte0]: 41
1736 23:46:44.467427 [Byte1]: 41
1737 23:46:44.472045
1738 23:46:44.472125 Set Vref, RX VrefLevel [Byte0]: 42
1739 23:46:44.475271 [Byte1]: 42
1740 23:46:44.479211
1741 23:46:44.479295 Set Vref, RX VrefLevel [Byte0]: 43
1742 23:46:44.482540 [Byte1]: 43
1743 23:46:44.487175
1744 23:46:44.487260 Set Vref, RX VrefLevel [Byte0]: 44
1745 23:46:44.490280 [Byte1]: 44
1746 23:46:44.494621
1747 23:46:44.494705 Set Vref, RX VrefLevel [Byte0]: 45
1748 23:46:44.497586 [Byte1]: 45
1749 23:46:44.501644
1750 23:46:44.501729 Set Vref, RX VrefLevel [Byte0]: 46
1751 23:46:44.505028 [Byte1]: 46
1752 23:46:44.509304
1753 23:46:44.509382 Set Vref, RX VrefLevel [Byte0]: 47
1754 23:46:44.512791 [Byte1]: 47
1755 23:46:44.516637
1756 23:46:44.516711 Set Vref, RX VrefLevel [Byte0]: 48
1757 23:46:44.520560 [Byte1]: 48
1758 23:46:44.524184
1759 23:46:44.524285 Set Vref, RX VrefLevel [Byte0]: 49
1760 23:46:44.527439 [Byte1]: 49
1761 23:46:44.532124
1762 23:46:44.532224 Set Vref, RX VrefLevel [Byte0]: 50
1763 23:46:44.534848 [Byte1]: 50
1764 23:46:44.539289
1765 23:46:44.539397 Set Vref, RX VrefLevel [Byte0]: 51
1766 23:46:44.542366 [Byte1]: 51
1767 23:46:44.546565
1768 23:46:44.546674 Set Vref, RX VrefLevel [Byte0]: 52
1769 23:46:44.550013 [Byte1]: 52
1770 23:46:44.554181
1771 23:46:44.554257 Set Vref, RX VrefLevel [Byte0]: 53
1772 23:46:44.557673 [Byte1]: 53
1773 23:46:44.562136
1774 23:46:44.562244 Set Vref, RX VrefLevel [Byte0]: 54
1775 23:46:44.565428 [Byte1]: 54
1776 23:46:44.569609
1777 23:46:44.569684 Set Vref, RX VrefLevel [Byte0]: 55
1778 23:46:44.572638 [Byte1]: 55
1779 23:46:44.576522
1780 23:46:44.576608 Set Vref, RX VrefLevel [Byte0]: 56
1781 23:46:44.580369 [Byte1]: 56
1782 23:46:44.584278
1783 23:46:44.584388 Set Vref, RX VrefLevel [Byte0]: 57
1784 23:46:44.587722 [Byte1]: 57
1785 23:46:44.591522
1786 23:46:44.591619 Set Vref, RX VrefLevel [Byte0]: 58
1787 23:46:44.595462 [Byte1]: 58
1788 23:46:44.599433
1789 23:46:44.599518 Set Vref, RX VrefLevel [Byte0]: 59
1790 23:46:44.602684 [Byte1]: 59
1791 23:46:44.607076
1792 23:46:44.607164 Set Vref, RX VrefLevel [Byte0]: 60
1793 23:46:44.610126 [Byte1]: 60
1794 23:46:44.614175
1795 23:46:44.614259 Set Vref, RX VrefLevel [Byte0]: 61
1796 23:46:44.617485 [Byte1]: 61
1797 23:46:44.622144
1798 23:46:44.622230 Set Vref, RX VrefLevel [Byte0]: 62
1799 23:46:44.625165 [Byte1]: 62
1800 23:46:44.629175
1801 23:46:44.629292 Set Vref, RX VrefLevel [Byte0]: 63
1802 23:46:44.632667 [Byte1]: 63
1803 23:46:44.636698
1804 23:46:44.636809 Set Vref, RX VrefLevel [Byte0]: 64
1805 23:46:44.640120 [Byte1]: 64
1806 23:46:44.644604
1807 23:46:44.644710 Set Vref, RX VrefLevel [Byte0]: 65
1808 23:46:44.647740 [Byte1]: 65
1809 23:46:44.651753
1810 23:46:44.651854 Set Vref, RX VrefLevel [Byte0]: 66
1811 23:46:44.654869 [Byte1]: 66
1812 23:46:44.659019
1813 23:46:44.659101 Set Vref, RX VrefLevel [Byte0]: 67
1814 23:46:44.662708 [Byte1]: 67
1815 23:46:44.666489
1816 23:46:44.666595 Set Vref, RX VrefLevel [Byte0]: 68
1817 23:46:44.670164 [Byte1]: 68
1818 23:46:44.674273
1819 23:46:44.674360 Set Vref, RX VrefLevel [Byte0]: 69
1820 23:46:44.677692 [Byte1]: 69
1821 23:46:44.682042
1822 23:46:44.682154 Set Vref, RX VrefLevel [Byte0]: 70
1823 23:46:44.685304 [Byte1]: 70
1824 23:46:44.689517
1825 23:46:44.689604 Set Vref, RX VrefLevel [Byte0]: 71
1826 23:46:44.692489 [Byte1]: 71
1827 23:46:44.697085
1828 23:46:44.697172 Final RX Vref Byte 0 = 57 to rank0
1829 23:46:44.700473 Final RX Vref Byte 1 = 56 to rank0
1830 23:46:44.703759 Final RX Vref Byte 0 = 57 to rank1
1831 23:46:44.706963 Final RX Vref Byte 1 = 56 to rank1==
1832 23:46:44.710116 Dram Type= 6, Freq= 0, CH_1, rank 0
1833 23:46:44.713233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 23:46:44.716491 ==
1835 23:46:44.716578 DQS Delay:
1836 23:46:44.716666 DQS0 = 0, DQS1 = 0
1837 23:46:44.720455 DQM Delay:
1838 23:46:44.720567 DQM0 = 95, DQM1 = 89
1839 23:46:44.723622 DQ Delay:
1840 23:46:44.727052 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1841 23:46:44.727140 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1842 23:46:44.730439 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1843 23:46:44.736854 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1844 23:46:44.736942
1845 23:46:44.737029
1846 23:46:44.743665 [DQSOSCAuto] RK0, (LSB)MR18= 0x304c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1847 23:46:44.746782 CH1 RK0: MR19=606, MR18=304C
1848 23:46:44.753307 CH1_RK0: MR19=0x606, MR18=0x304C, DQSOSC=390, MR23=63, INC=97, DEC=64
1849 23:46:44.753400
1850 23:46:44.756612 ----->DramcWriteLeveling(PI) begin...
1851 23:46:44.756698 ==
1852 23:46:44.759868 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 23:46:44.763655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 23:46:44.763729 ==
1855 23:46:44.766703 Write leveling (Byte 0): 26 => 26
1856 23:46:44.769791 Write leveling (Byte 1): 29 => 29
1857 23:46:44.773666 DramcWriteLeveling(PI) end<-----
1858 23:46:44.773769
1859 23:46:44.773870 ==
1860 23:46:44.776835 Dram Type= 6, Freq= 0, CH_1, rank 1
1861 23:46:44.780650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1862 23:46:44.780729 ==
1863 23:46:44.783882 [Gating] SW mode calibration
1864 23:46:44.789919 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1865 23:46:44.797053 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1866 23:46:44.800396 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1867 23:46:44.803740 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1868 23:46:44.810395 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:46:44.813740 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:46:44.816920 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:46:44.823532 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 23:46:44.826907 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 23:46:44.830071 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:46:44.834039 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:46:44.840301 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:46:44.844012 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:46:44.847165 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:46:44.854073 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:46:44.857027 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:46:44.860427 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:46:44.867022 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:46:44.870250 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:46:44.873829 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:46:44.880177 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:46:44.883485 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:46:44.887146 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:46:44.893810 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 23:46:44.897053 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 23:46:44.900232 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:46:44.906885 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 23:46:44.910771 0 9 4 | B1->B0 | 2f2f 2323 | 1 1 | (1 1) (1 1)
1892 23:46:44.914037 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 1)
1893 23:46:44.920630 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 23:46:44.923952 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 23:46:44.927310 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 23:46:44.930861 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 23:46:44.937253 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1898 23:46:44.940522 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1899 23:46:44.943813 0 10 4 | B1->B0 | 2e2e 2f2f | 0 1 | (0 0) (1 0)
1900 23:46:44.950462 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1901 23:46:44.954091 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 23:46:44.957424 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 23:46:44.963887 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 23:46:44.967298 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 23:46:44.970535 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 23:46:44.977104 0 11 0 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
1907 23:46:44.980777 0 11 4 | B1->B0 | 3b3b 2929 | 0 1 | (1 1) (0 0)
1908 23:46:44.983765 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1909 23:46:44.990914 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 23:46:44.994066 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 23:46:44.997275 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 23:46:45.003701 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 23:46:45.007235 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 23:46:45.010948 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 23:46:45.014058 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1916 23:46:45.020587 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 23:46:45.023819 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 23:46:45.027665 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 23:46:45.034475 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 23:46:45.037456 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 23:46:45.040693 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 23:46:45.047282 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:46:45.050431 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:46:45.054156 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:46:45.060989 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 23:46:45.064249 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 23:46:45.067587 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 23:46:45.074311 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 23:46:45.077182 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 23:46:45.080499 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 23:46:45.087880 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1932 23:46:45.090670 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 23:46:45.093819 Total UI for P1: 0, mck2ui 16
1934 23:46:45.097050 best dqsien dly found for B0: ( 0, 14, 4)
1935 23:46:45.100907 Total UI for P1: 0, mck2ui 16
1936 23:46:45.104098 best dqsien dly found for B1: ( 0, 14, 4)
1937 23:46:45.107152 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1938 23:46:45.111170 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1939 23:46:45.111248
1940 23:46:45.114406 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1941 23:46:45.117672 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1942 23:46:45.120813 [Gating] SW calibration Done
1943 23:46:45.120915 ==
1944 23:46:45.123888 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 23:46:45.127527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 23:46:45.127609 ==
1947 23:46:45.131007 RX Vref Scan: 0
1948 23:46:45.131094
1949 23:46:45.131160 RX Vref 0 -> 0, step: 1
1950 23:46:45.131222
1951 23:46:45.133959 RX Delay -130 -> 252, step: 16
1952 23:46:45.141090 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1953 23:46:45.144334 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1954 23:46:45.147522 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1955 23:46:45.150742 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1956 23:46:45.154010 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1957 23:46:45.157325 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1958 23:46:45.164403 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1959 23:46:45.167479 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1960 23:46:45.171081 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1961 23:46:45.174425 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1962 23:46:45.177577 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1963 23:46:45.184240 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1964 23:46:45.187801 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1965 23:46:45.191040 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1966 23:46:45.194180 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1967 23:46:45.200930 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1968 23:46:45.201007 ==
1969 23:46:45.204177 Dram Type= 6, Freq= 0, CH_1, rank 1
1970 23:46:45.207473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1971 23:46:45.207564 ==
1972 23:46:45.207630 DQS Delay:
1973 23:46:45.210931 DQS0 = 0, DQS1 = 0
1974 23:46:45.211008 DQM Delay:
1975 23:46:45.214061 DQM0 = 92, DQM1 = 88
1976 23:46:45.214141 DQ Delay:
1977 23:46:45.217123 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1978 23:46:45.220662 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1979 23:46:45.223709 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1980 23:46:45.227114 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1981 23:46:45.227189
1982 23:46:45.227255
1983 23:46:45.227318 ==
1984 23:46:45.230439 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 23:46:45.233837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 23:46:45.233916 ==
1987 23:46:45.233977
1988 23:46:45.237611
1989 23:46:45.237692 TX Vref Scan disable
1990 23:46:45.240647 == TX Byte 0 ==
1991 23:46:45.244163 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1992 23:46:45.247485 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1993 23:46:45.250619 == TX Byte 1 ==
1994 23:46:45.254176 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1995 23:46:45.257323 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1996 23:46:45.257413 ==
1997 23:46:45.260741 Dram Type= 6, Freq= 0, CH_1, rank 1
1998 23:46:45.268129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1999 23:46:45.268221 ==
2000 23:46:45.279224 TX Vref=22, minBit 5, minWin=26, winSum=442
2001 23:46:45.282375 TX Vref=24, minBit 0, minWin=27, winSum=446
2002 23:46:45.285729 TX Vref=26, minBit 1, minWin=26, winSum=444
2003 23:46:45.288992 TX Vref=28, minBit 0, minWin=27, winSum=449
2004 23:46:45.292652 TX Vref=30, minBit 0, minWin=27, winSum=448
2005 23:46:45.296108 TX Vref=32, minBit 2, minWin=27, winSum=449
2006 23:46:45.302457 [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 28
2007 23:46:45.302535
2008 23:46:45.306079 Final TX Range 1 Vref 28
2009 23:46:45.306167
2010 23:46:45.306233 ==
2011 23:46:45.309053 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 23:46:45.312264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 23:46:45.312388 ==
2014 23:46:45.312483
2015 23:46:45.316141
2016 23:46:45.316216 TX Vref Scan disable
2017 23:46:45.319310 == TX Byte 0 ==
2018 23:46:45.322482 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2019 23:46:45.325886 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2020 23:46:45.329138 == TX Byte 1 ==
2021 23:46:45.332353 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2022 23:46:45.335789 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2023 23:46:45.339517
2024 23:46:45.339604 [DATLAT]
2025 23:46:45.339677 Freq=800, CH1 RK1
2026 23:46:45.339759
2027 23:46:45.342802 DATLAT Default: 0xa
2028 23:46:45.342883 0, 0xFFFF, sum = 0
2029 23:46:45.345994 1, 0xFFFF, sum = 0
2030 23:46:45.346071 2, 0xFFFF, sum = 0
2031 23:46:45.349515 3, 0xFFFF, sum = 0
2032 23:46:45.349596 4, 0xFFFF, sum = 0
2033 23:46:45.352295 5, 0xFFFF, sum = 0
2034 23:46:45.352421 6, 0xFFFF, sum = 0
2035 23:46:45.355928 7, 0xFFFF, sum = 0
2036 23:46:45.358952 8, 0xFFFF, sum = 0
2037 23:46:45.359062 9, 0x0, sum = 1
2038 23:46:45.359166 10, 0x0, sum = 2
2039 23:46:45.362281 11, 0x0, sum = 3
2040 23:46:45.362382 12, 0x0, sum = 4
2041 23:46:45.365830 best_step = 10
2042 23:46:45.365915
2043 23:46:45.365983 ==
2044 23:46:45.369171 Dram Type= 6, Freq= 0, CH_1, rank 1
2045 23:46:45.372760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2046 23:46:45.372838 ==
2047 23:46:45.376070 RX Vref Scan: 0
2048 23:46:45.376154
2049 23:46:45.376223 RX Vref 0 -> 0, step: 1
2050 23:46:45.376288
2051 23:46:45.379294 RX Delay -79 -> 252, step: 8
2052 23:46:45.386030 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2053 23:46:45.389339 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2054 23:46:45.392683 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2055 23:46:45.396044 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2056 23:46:45.399125 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2057 23:46:45.402883 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2058 23:46:45.409485 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2059 23:46:45.412621 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2060 23:46:45.416261 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2061 23:46:45.419199 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2062 23:46:45.422875 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2063 23:46:45.426034 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2064 23:46:45.432665 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2065 23:46:45.435991 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2066 23:46:45.439306 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2067 23:46:45.442624 iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216
2068 23:46:45.442696 ==
2069 23:46:45.445881 Dram Type= 6, Freq= 0, CH_1, rank 1
2070 23:46:45.452623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2071 23:46:45.452704 ==
2072 23:46:45.452769 DQS Delay:
2073 23:46:45.456261 DQS0 = 0, DQS1 = 0
2074 23:46:45.456377 DQM Delay:
2075 23:46:45.456449 DQM0 = 97, DQM1 = 92
2076 23:46:45.459592 DQ Delay:
2077 23:46:45.462930 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2078 23:46:45.466410 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2079 23:46:45.469417 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2080 23:46:45.472525 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100
2081 23:46:45.472607
2082 23:46:45.472672
2083 23:46:45.479489 [DQSOSCAuto] RK1, (LSB)MR18= 0x4811, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2084 23:46:45.482940 CH1 RK1: MR19=606, MR18=4811
2085 23:46:45.489808 CH1_RK1: MR19=0x606, MR18=0x4811, DQSOSC=391, MR23=63, INC=96, DEC=64
2086 23:46:45.492658 [RxdqsGatingPostProcess] freq 800
2087 23:46:45.496571 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2088 23:46:45.499801 Pre-setting of DQS Precalculation
2089 23:46:45.506347 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2090 23:46:45.512671 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2091 23:46:45.519424 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2092 23:46:45.519511
2093 23:46:45.519582
2094 23:46:45.523049 [Calibration Summary] 1600 Mbps
2095 23:46:45.523159 CH 0, Rank 0
2096 23:46:45.526075 SW Impedance : PASS
2097 23:46:45.529651 DUTY Scan : NO K
2098 23:46:45.529727 ZQ Calibration : PASS
2099 23:46:45.532818 Jitter Meter : NO K
2100 23:46:45.536148 CBT Training : PASS
2101 23:46:45.536264 Write leveling : PASS
2102 23:46:45.539436 RX DQS gating : PASS
2103 23:46:45.542564 RX DQ/DQS(RDDQC) : PASS
2104 23:46:45.542653 TX DQ/DQS : PASS
2105 23:46:45.545780 RX DATLAT : PASS
2106 23:46:45.549293 RX DQ/DQS(Engine): PASS
2107 23:46:45.549370 TX OE : NO K
2108 23:46:45.552323 All Pass.
2109 23:46:45.552401
2110 23:46:45.552464 CH 0, Rank 1
2111 23:46:45.555897 SW Impedance : PASS
2112 23:46:45.555982 DUTY Scan : NO K
2113 23:46:45.559466 ZQ Calibration : PASS
2114 23:46:45.562897 Jitter Meter : NO K
2115 23:46:45.563003 CBT Training : PASS
2116 23:46:45.566170 Write leveling : PASS
2117 23:46:45.566250 RX DQS gating : PASS
2118 23:46:45.569328 RX DQ/DQS(RDDQC) : PASS
2119 23:46:45.572718 TX DQ/DQS : PASS
2120 23:46:45.572809 RX DATLAT : PASS
2121 23:46:45.576060 RX DQ/DQS(Engine): PASS
2122 23:46:45.579293 TX OE : NO K
2123 23:46:45.579379 All Pass.
2124 23:46:45.579443
2125 23:46:45.579505 CH 1, Rank 0
2126 23:46:45.583052 SW Impedance : PASS
2127 23:46:45.586188 DUTY Scan : NO K
2128 23:46:45.586267 ZQ Calibration : PASS
2129 23:46:45.589685 Jitter Meter : NO K
2130 23:46:45.592773 CBT Training : PASS
2131 23:46:45.592858 Write leveling : PASS
2132 23:46:45.596464 RX DQS gating : PASS
2133 23:46:45.596574 RX DQ/DQS(RDDQC) : PASS
2134 23:46:45.599673 TX DQ/DQS : PASS
2135 23:46:45.602875 RX DATLAT : PASS
2136 23:46:45.602952 RX DQ/DQS(Engine): PASS
2137 23:46:45.606217 TX OE : NO K
2138 23:46:45.606328 All Pass.
2139 23:46:45.606424
2140 23:46:45.609680 CH 1, Rank 1
2141 23:46:45.609783 SW Impedance : PASS
2142 23:46:45.612852 DUTY Scan : NO K
2143 23:46:45.616229 ZQ Calibration : PASS
2144 23:46:45.616331 Jitter Meter : NO K
2145 23:46:45.619592 CBT Training : PASS
2146 23:46:45.623231 Write leveling : PASS
2147 23:46:45.623324 RX DQS gating : PASS
2148 23:46:45.626497 RX DQ/DQS(RDDQC) : PASS
2149 23:46:45.629610 TX DQ/DQS : PASS
2150 23:46:45.629688 RX DATLAT : PASS
2151 23:46:45.633238 RX DQ/DQS(Engine): PASS
2152 23:46:45.636400 TX OE : NO K
2153 23:46:45.636478 All Pass.
2154 23:46:45.636551
2155 23:46:45.636613 DramC Write-DBI off
2156 23:46:45.639453 PER_BANK_REFRESH: Hybrid Mode
2157 23:46:45.643022 TX_TRACKING: ON
2158 23:46:45.646480 [GetDramInforAfterCalByMRR] Vendor 6.
2159 23:46:45.650083 [GetDramInforAfterCalByMRR] Revision 606.
2160 23:46:45.653165 [GetDramInforAfterCalByMRR] Revision 2 0.
2161 23:46:45.653250 MR0 0x3b3b
2162 23:46:45.656579 MR8 0x5151
2163 23:46:45.659677 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2164 23:46:45.659762
2165 23:46:45.659829 MR0 0x3b3b
2166 23:46:45.659892 MR8 0x5151
2167 23:46:45.662945 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2168 23:46:45.663031
2169 23:46:45.672733 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2170 23:46:45.676576 [FAST_K] Save calibration result to emmc
2171 23:46:45.679774 [FAST_K] Save calibration result to emmc
2172 23:46:45.683096 dram_init: config_dvfs: 1
2173 23:46:45.686329 dramc_set_vcore_voltage set vcore to 662500
2174 23:46:45.689605 Read voltage for 1200, 2
2175 23:46:45.689692 Vio18 = 0
2176 23:46:45.689758 Vcore = 662500
2177 23:46:45.693409 Vdram = 0
2178 23:46:45.693494 Vddq = 0
2179 23:46:45.693561 Vmddr = 0
2180 23:46:45.700031 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2181 23:46:45.703442 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2182 23:46:45.706736 MEM_TYPE=3, freq_sel=15
2183 23:46:45.709685 sv_algorithm_assistance_LP4_1600
2184 23:46:45.713165 ============ PULL DRAM RESETB DOWN ============
2185 23:46:45.716293 ========== PULL DRAM RESETB DOWN end =========
2186 23:46:45.723511 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2187 23:46:45.726764 ===================================
2188 23:46:45.729768 LPDDR4 DRAM CONFIGURATION
2189 23:46:45.729852 ===================================
2190 23:46:45.733557 EX_ROW_EN[0] = 0x0
2191 23:46:45.736575 EX_ROW_EN[1] = 0x0
2192 23:46:45.736659 LP4Y_EN = 0x0
2193 23:46:45.739586 WORK_FSP = 0x0
2194 23:46:45.739669 WL = 0x4
2195 23:46:45.743482 RL = 0x4
2196 23:46:45.743615 BL = 0x2
2197 23:46:45.746838 RPST = 0x0
2198 23:46:45.746922 RD_PRE = 0x0
2199 23:46:45.750060 WR_PRE = 0x1
2200 23:46:45.750143 WR_PST = 0x0
2201 23:46:45.753204 DBI_WR = 0x0
2202 23:46:45.753302 DBI_RD = 0x0
2203 23:46:45.757000 OTF = 0x1
2204 23:46:45.759745 ===================================
2205 23:46:45.763670 ===================================
2206 23:46:45.763756 ANA top config
2207 23:46:45.766697 ===================================
2208 23:46:45.770087 DLL_ASYNC_EN = 0
2209 23:46:45.773427 ALL_SLAVE_EN = 0
2210 23:46:45.773512 NEW_RANK_MODE = 1
2211 23:46:45.776784 DLL_IDLE_MODE = 1
2212 23:46:45.780196 LP45_APHY_COMB_EN = 1
2213 23:46:45.783487 TX_ODT_DIS = 1
2214 23:46:45.786765 NEW_8X_MODE = 1
2215 23:46:45.789998 ===================================
2216 23:46:45.793769 ===================================
2217 23:46:45.793846 data_rate = 2400
2218 23:46:45.796902 CKR = 1
2219 23:46:45.800262 DQ_P2S_RATIO = 8
2220 23:46:45.803409 ===================================
2221 23:46:45.806669 CA_P2S_RATIO = 8
2222 23:46:45.810044 DQ_CA_OPEN = 0
2223 23:46:45.813233 DQ_SEMI_OPEN = 0
2224 23:46:45.813320 CA_SEMI_OPEN = 0
2225 23:46:45.817229 CA_FULL_RATE = 0
2226 23:46:45.820585 DQ_CKDIV4_EN = 0
2227 23:46:45.823521 CA_CKDIV4_EN = 0
2228 23:46:45.827096 CA_PREDIV_EN = 0
2229 23:46:45.830436 PH8_DLY = 17
2230 23:46:45.830541 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2231 23:46:45.833622 DQ_AAMCK_DIV = 4
2232 23:46:45.836770 CA_AAMCK_DIV = 4
2233 23:46:45.840387 CA_ADMCK_DIV = 4
2234 23:46:45.843660 DQ_TRACK_CA_EN = 0
2235 23:46:45.846972 CA_PICK = 1200
2236 23:46:45.847059 CA_MCKIO = 1200
2237 23:46:45.850341 MCKIO_SEMI = 0
2238 23:46:45.853350 PLL_FREQ = 2366
2239 23:46:45.856646 DQ_UI_PI_RATIO = 32
2240 23:46:45.860568 CA_UI_PI_RATIO = 0
2241 23:46:45.863656 ===================================
2242 23:46:45.866784 ===================================
2243 23:46:45.870400 memory_type:LPDDR4
2244 23:46:45.870486 GP_NUM : 10
2245 23:46:45.873991 SRAM_EN : 1
2246 23:46:45.874077 MD32_EN : 0
2247 23:46:45.877195 ===================================
2248 23:46:45.880358 [ANA_INIT] >>>>>>>>>>>>>>
2249 23:46:45.883765 <<<<<< [CONFIGURE PHASE]: ANA_TX
2250 23:46:45.886739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2251 23:46:45.890078 ===================================
2252 23:46:45.893943 data_rate = 2400,PCW = 0X5b00
2253 23:46:45.897123 ===================================
2254 23:46:45.900307 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2255 23:46:45.903664 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2256 23:46:45.910334 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2257 23:46:45.913468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2258 23:46:45.916793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2259 23:46:45.924104 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2260 23:46:45.924191 [ANA_INIT] flow start
2261 23:46:45.927339 [ANA_INIT] PLL >>>>>>>>
2262 23:46:45.927425 [ANA_INIT] PLL <<<<<<<<
2263 23:46:45.930744 [ANA_INIT] MIDPI >>>>>>>>
2264 23:46:45.934059 [ANA_INIT] MIDPI <<<<<<<<
2265 23:46:45.937322 [ANA_INIT] DLL >>>>>>>>
2266 23:46:45.937407 [ANA_INIT] DLL <<<<<<<<
2267 23:46:45.940416 [ANA_INIT] flow end
2268 23:46:45.943761 ============ LP4 DIFF to SE enter ============
2269 23:46:45.947294 ============ LP4 DIFF to SE exit ============
2270 23:46:45.950505 [ANA_INIT] <<<<<<<<<<<<<
2271 23:46:45.953970 [Flow] Enable top DCM control >>>>>
2272 23:46:45.957600 [Flow] Enable top DCM control <<<<<
2273 23:46:45.960497 Enable DLL master slave shuffle
2274 23:46:45.963879 ==============================================================
2275 23:46:45.967064 Gating Mode config
2276 23:46:45.974372 ==============================================================
2277 23:46:45.974459 Config description:
2278 23:46:45.984134 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2279 23:46:45.990498 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2280 23:46:45.993871 SELPH_MODE 0: By rank 1: By Phase
2281 23:46:46.001183 ==============================================================
2282 23:46:46.004238 GAT_TRACK_EN = 1
2283 23:46:46.007504 RX_GATING_MODE = 2
2284 23:46:46.010806 RX_GATING_TRACK_MODE = 2
2285 23:46:46.014074 SELPH_MODE = 1
2286 23:46:46.017372 PICG_EARLY_EN = 1
2287 23:46:46.020696 VALID_LAT_VALUE = 1
2288 23:46:46.023950 ==============================================================
2289 23:46:46.027234 Enter into Gating configuration >>>>
2290 23:46:46.030571 Exit from Gating configuration <<<<
2291 23:46:46.033854 Enter into DVFS_PRE_config >>>>>
2292 23:46:46.044335 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2293 23:46:46.047833 Exit from DVFS_PRE_config <<<<<
2294 23:46:46.051060 Enter into PICG configuration >>>>
2295 23:46:46.054276 Exit from PICG configuration <<<<
2296 23:46:46.057863 [RX_INPUT] configuration >>>>>
2297 23:46:46.060896 [RX_INPUT] configuration <<<<<
2298 23:46:46.067764 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2299 23:46:46.071061 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2300 23:46:46.077755 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2301 23:46:46.084452 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2302 23:46:46.090732 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 23:46:46.097309 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 23:46:46.100860 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2305 23:46:46.104227 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2306 23:46:46.108018 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2307 23:46:46.111074 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2308 23:46:46.117530 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2309 23:46:46.120800 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2310 23:46:46.124088 ===================================
2311 23:46:46.127337 LPDDR4 DRAM CONFIGURATION
2312 23:46:46.130694 ===================================
2313 23:46:46.130814 EX_ROW_EN[0] = 0x0
2314 23:46:46.134617 EX_ROW_EN[1] = 0x0
2315 23:46:46.134731 LP4Y_EN = 0x0
2316 23:46:46.138027 WORK_FSP = 0x0
2317 23:46:46.138106 WL = 0x4
2318 23:46:46.141582 RL = 0x4
2319 23:46:46.141659 BL = 0x2
2320 23:46:46.144615 RPST = 0x0
2321 23:46:46.144714 RD_PRE = 0x0
2322 23:46:46.148039 WR_PRE = 0x1
2323 23:46:46.148144 WR_PST = 0x0
2324 23:46:46.151440 DBI_WR = 0x0
2325 23:46:46.154545 DBI_RD = 0x0
2326 23:46:46.154660 OTF = 0x1
2327 23:46:46.157769 ===================================
2328 23:46:46.161039 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2329 23:46:46.164214 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2330 23:46:46.171132 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2331 23:46:46.174447 ===================================
2332 23:46:46.174534 LPDDR4 DRAM CONFIGURATION
2333 23:46:46.178183 ===================================
2334 23:46:46.181504 EX_ROW_EN[0] = 0x10
2335 23:46:46.184738 EX_ROW_EN[1] = 0x0
2336 23:46:46.184816 LP4Y_EN = 0x0
2337 23:46:46.188109 WORK_FSP = 0x0
2338 23:46:46.188216 WL = 0x4
2339 23:46:46.191417 RL = 0x4
2340 23:46:46.191500 BL = 0x2
2341 23:46:46.194732 RPST = 0x0
2342 23:46:46.194816 RD_PRE = 0x0
2343 23:46:46.197929 WR_PRE = 0x1
2344 23:46:46.198013 WR_PST = 0x0
2345 23:46:46.201121 DBI_WR = 0x0
2346 23:46:46.201208 DBI_RD = 0x0
2347 23:46:46.204771 OTF = 0x1
2348 23:46:46.208315 ===================================
2349 23:46:46.214646 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2350 23:46:46.214728 ==
2351 23:46:46.218197 Dram Type= 6, Freq= 0, CH_0, rank 0
2352 23:46:46.221520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2353 23:46:46.221604 ==
2354 23:46:46.224942 [Duty_Offset_Calibration]
2355 23:46:46.225020 B0:2 B1:1 CA:1
2356 23:46:46.225091
2357 23:46:46.227856 [DutyScan_Calibration_Flow] k_type=0
2358 23:46:46.237686
2359 23:46:46.237769 ==CLK 0==
2360 23:46:46.241414 Final CLK duty delay cell = 0
2361 23:46:46.244774 [0] MAX Duty = 5187%(X100), DQS PI = 24
2362 23:46:46.247847 [0] MIN Duty = 4844%(X100), DQS PI = 48
2363 23:46:46.251187 [0] AVG Duty = 5015%(X100)
2364 23:46:46.251300
2365 23:46:46.254444 CH0 CLK Duty spec in!! Max-Min= 343%
2366 23:46:46.257741 [DutyScan_Calibration_Flow] ====Done====
2367 23:46:46.257826
2368 23:46:46.261054 [DutyScan_Calibration_Flow] k_type=1
2369 23:46:46.276903
2370 23:46:46.276987 ==DQS 0 ==
2371 23:46:46.279984 Final DQS duty delay cell = -4
2372 23:46:46.283741 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2373 23:46:46.286496 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2374 23:46:46.289944 [-4] AVG Duty = 4953%(X100)
2375 23:46:46.290032
2376 23:46:46.290099 ==DQS 1 ==
2377 23:46:46.293065 Final DQS duty delay cell = 0
2378 23:46:46.296459 [0] MAX Duty = 5156%(X100), DQS PI = 62
2379 23:46:46.299751 [0] MIN Duty = 5000%(X100), DQS PI = 32
2380 23:46:46.303161 [0] AVG Duty = 5078%(X100)
2381 23:46:46.303264
2382 23:46:46.306619 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2383 23:46:46.306706
2384 23:46:46.309715 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2385 23:46:46.313027 [DutyScan_Calibration_Flow] ====Done====
2386 23:46:46.313115
2387 23:46:46.316371 [DutyScan_Calibration_Flow] k_type=3
2388 23:46:46.333508
2389 23:46:46.333590 ==DQM 0 ==
2390 23:46:46.336587 Final DQM duty delay cell = 0
2391 23:46:46.340089 [0] MAX Duty = 5156%(X100), DQS PI = 28
2392 23:46:46.343710 [0] MIN Duty = 4875%(X100), DQS PI = 58
2393 23:46:46.346719 [0] AVG Duty = 5015%(X100)
2394 23:46:46.346806
2395 23:46:46.346874 ==DQM 1 ==
2396 23:46:46.350145 Final DQM duty delay cell = 0
2397 23:46:46.353452 [0] MAX Duty = 5124%(X100), DQS PI = 6
2398 23:46:46.356653 [0] MIN Duty = 5031%(X100), DQS PI = 36
2399 23:46:46.356738 [0] AVG Duty = 5077%(X100)
2400 23:46:46.360100
2401 23:46:46.363591 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2402 23:46:46.363677
2403 23:46:46.366983 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2404 23:46:46.370487 [DutyScan_Calibration_Flow] ====Done====
2405 23:46:46.370578
2406 23:46:46.373722 [DutyScan_Calibration_Flow] k_type=2
2407 23:46:46.389653
2408 23:46:46.389768 ==DQ 0 ==
2409 23:46:46.393276 Final DQ duty delay cell = 0
2410 23:46:46.396555 [0] MAX Duty = 5062%(X100), DQS PI = 32
2411 23:46:46.399992 [0] MIN Duty = 4844%(X100), DQS PI = 62
2412 23:46:46.400098 [0] AVG Duty = 4953%(X100)
2413 23:46:46.403180
2414 23:46:46.403254 ==DQ 1 ==
2415 23:46:46.406268 Final DQ duty delay cell = 0
2416 23:46:46.410181 [0] MAX Duty = 5093%(X100), DQS PI = 10
2417 23:46:46.413607 [0] MIN Duty = 4969%(X100), DQS PI = 14
2418 23:46:46.413689 [0] AVG Duty = 5031%(X100)
2419 23:46:46.413755
2420 23:46:46.416821 CH0 DQ 0 Duty spec in!! Max-Min= 218%
2421 23:46:46.420086
2422 23:46:46.423470 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2423 23:46:46.426560 [DutyScan_Calibration_Flow] ====Done====
2424 23:46:46.426645 ==
2425 23:46:46.429910 Dram Type= 6, Freq= 0, CH_1, rank 0
2426 23:46:46.432823 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2427 23:46:46.432906 ==
2428 23:46:46.436566 [Duty_Offset_Calibration]
2429 23:46:46.436646 B0:1 B1:0 CA:0
2430 23:46:46.436716
2431 23:46:46.439834 [DutyScan_Calibration_Flow] k_type=0
2432 23:46:46.449032
2433 23:46:46.449115 ==CLK 0==
2434 23:46:46.452149 Final CLK duty delay cell = -4
2435 23:46:46.455957 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2436 23:46:46.459209 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2437 23:46:46.462530 [-4] AVG Duty = 4969%(X100)
2438 23:46:46.462615
2439 23:46:46.465653 CH1 CLK Duty spec in!! Max-Min= 124%
2440 23:46:46.468825 [DutyScan_Calibration_Flow] ====Done====
2441 23:46:46.468919
2442 23:46:46.472405 [DutyScan_Calibration_Flow] k_type=1
2443 23:46:46.488977
2444 23:46:46.489065 ==DQS 0 ==
2445 23:46:46.492719 Final DQS duty delay cell = 0
2446 23:46:46.495538 [0] MAX Duty = 5062%(X100), DQS PI = 10
2447 23:46:46.498718 [0] MIN Duty = 4844%(X100), DQS PI = 0
2448 23:46:46.498828 [0] AVG Duty = 4953%(X100)
2449 23:46:46.501979
2450 23:46:46.502085 ==DQS 1 ==
2451 23:46:46.505991 Final DQS duty delay cell = 0
2452 23:46:46.508950 [0] MAX Duty = 5187%(X100), DQS PI = 18
2453 23:46:46.512393 [0] MIN Duty = 4969%(X100), DQS PI = 8
2454 23:46:46.512475 [0] AVG Duty = 5078%(X100)
2455 23:46:46.512580
2456 23:46:46.518800 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2457 23:46:46.518888
2458 23:46:46.522715 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2459 23:46:46.526146 [DutyScan_Calibration_Flow] ====Done====
2460 23:46:46.526226
2461 23:46:46.528633 [DutyScan_Calibration_Flow] k_type=3
2462 23:46:46.545288
2463 23:46:46.545372 ==DQM 0 ==
2464 23:46:46.548679 Final DQM duty delay cell = 0
2465 23:46:46.552084 [0] MAX Duty = 5156%(X100), DQS PI = 6
2466 23:46:46.555254 [0] MIN Duty = 5031%(X100), DQS PI = 0
2467 23:46:46.555329 [0] AVG Duty = 5093%(X100)
2468 23:46:46.559020
2469 23:46:46.559094 ==DQM 1 ==
2470 23:46:46.561829 Final DQM duty delay cell = 0
2471 23:46:46.565181 [0] MAX Duty = 5031%(X100), DQS PI = 16
2472 23:46:46.568399 [0] MIN Duty = 4875%(X100), DQS PI = 52
2473 23:46:46.568476 [0] AVG Duty = 4953%(X100)
2474 23:46:46.572229
2475 23:46:46.575531 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2476 23:46:46.575615
2477 23:46:46.578742 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2478 23:46:46.582032 [DutyScan_Calibration_Flow] ====Done====
2479 23:46:46.582113
2480 23:46:46.585408 [DutyScan_Calibration_Flow] k_type=2
2481 23:46:46.601129
2482 23:46:46.601219 ==DQ 0 ==
2483 23:46:46.604440 Final DQ duty delay cell = -4
2484 23:46:46.607977 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2485 23:46:46.611092 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2486 23:46:46.614817 [-4] AVG Duty = 4984%(X100)
2487 23:46:46.614911
2488 23:46:46.614977 ==DQ 1 ==
2489 23:46:46.617966 Final DQ duty delay cell = 0
2490 23:46:46.620773 [0] MAX Duty = 5125%(X100), DQS PI = 20
2491 23:46:46.624170 [0] MIN Duty = 4969%(X100), DQS PI = 32
2492 23:46:46.624270 [0] AVG Duty = 5047%(X100)
2493 23:46:46.627882
2494 23:46:46.631011 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2495 23:46:46.631086
2496 23:46:46.634519 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2497 23:46:46.637495 [DutyScan_Calibration_Flow] ====Done====
2498 23:46:46.641152 nWR fixed to 30
2499 23:46:46.641260 [ModeRegInit_LP4] CH0 RK0
2500 23:46:46.644170 [ModeRegInit_LP4] CH0 RK1
2501 23:46:46.647545 [ModeRegInit_LP4] CH1 RK0
2502 23:46:46.651007 [ModeRegInit_LP4] CH1 RK1
2503 23:46:46.651082 match AC timing 7
2504 23:46:46.654221 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2505 23:46:46.661404 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2506 23:46:46.664751 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2507 23:46:46.667822 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2508 23:46:46.674788 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2509 23:46:46.674869 ==
2510 23:46:46.678151 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 23:46:46.681532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 23:46:46.681607 ==
2513 23:46:46.688140 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2514 23:46:46.691529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2515 23:46:46.701312 [CA 0] Center 39 (8~70) winsize 63
2516 23:46:46.704771 [CA 1] Center 39 (8~70) winsize 63
2517 23:46:46.708021 [CA 2] Center 35 (5~66) winsize 62
2518 23:46:46.711497 [CA 3] Center 34 (4~65) winsize 62
2519 23:46:46.714609 [CA 4] Center 33 (3~64) winsize 62
2520 23:46:46.717705 [CA 5] Center 32 (3~62) winsize 60
2521 23:46:46.717782
2522 23:46:46.721487 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2523 23:46:46.721575
2524 23:46:46.724686 [CATrainingPosCal] consider 1 rank data
2525 23:46:46.728025 u2DelayCellTimex100 = 270/100 ps
2526 23:46:46.731406 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2527 23:46:46.734563 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2528 23:46:46.741305 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2529 23:46:46.744619 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2530 23:46:46.747704 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2531 23:46:46.751196 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2532 23:46:46.751270
2533 23:46:46.754690 CA PerBit enable=1, Macro0, CA PI delay=32
2534 23:46:46.754763
2535 23:46:46.757983 [CBTSetCACLKResult] CA Dly = 32
2536 23:46:46.758059 CS Dly: 6 (0~37)
2537 23:46:46.761328 ==
2538 23:46:46.761408 Dram Type= 6, Freq= 0, CH_0, rank 1
2539 23:46:46.767836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2540 23:46:46.767950 ==
2541 23:46:46.771346 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2542 23:46:46.777836 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2543 23:46:46.786971 [CA 0] Center 38 (8~69) winsize 62
2544 23:46:46.790849 [CA 1] Center 38 (8~69) winsize 62
2545 23:46:46.794191 [CA 2] Center 35 (5~66) winsize 62
2546 23:46:46.797480 [CA 3] Center 34 (4~65) winsize 62
2547 23:46:46.800646 [CA 4] Center 33 (3~64) winsize 62
2548 23:46:46.803848 [CA 5] Center 32 (2~62) winsize 61
2549 23:46:46.803926
2550 23:46:46.807169 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2551 23:46:46.807242
2552 23:46:46.810488 [CATrainingPosCal] consider 2 rank data
2553 23:46:46.813969 u2DelayCellTimex100 = 270/100 ps
2554 23:46:46.817093 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2555 23:46:46.820814 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2556 23:46:46.827440 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2557 23:46:46.830602 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2558 23:46:46.833845 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2559 23:46:46.837114 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2560 23:46:46.837197
2561 23:46:46.840442 CA PerBit enable=1, Macro0, CA PI delay=32
2562 23:46:46.840542
2563 23:46:46.843906 [CBTSetCACLKResult] CA Dly = 32
2564 23:46:46.844012 CS Dly: 6 (0~38)
2565 23:46:46.844110
2566 23:46:46.847299 ----->DramcWriteLeveling(PI) begin...
2567 23:46:46.847401 ==
2568 23:46:46.850587 Dram Type= 6, Freq= 0, CH_0, rank 0
2569 23:46:46.857720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2570 23:46:46.857800 ==
2571 23:46:46.860907 Write leveling (Byte 0): 34 => 34
2572 23:46:46.864094 Write leveling (Byte 1): 31 => 31
2573 23:46:46.864168 DramcWriteLeveling(PI) end<-----
2574 23:46:46.864231
2575 23:46:46.867617 ==
2576 23:46:46.870662 Dram Type= 6, Freq= 0, CH_0, rank 0
2577 23:46:46.874192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2578 23:46:46.874268 ==
2579 23:46:46.877297 [Gating] SW mode calibration
2580 23:46:46.883758 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2581 23:46:46.887617 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2582 23:46:46.894222 0 15 0 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
2583 23:46:46.897433 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2584 23:46:46.900708 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 23:46:46.907468 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 23:46:46.910672 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 23:46:46.914504 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 23:46:46.921032 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2589 23:46:46.924234 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
2590 23:46:46.927178 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
2591 23:46:46.934118 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 23:46:46.937167 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 23:46:46.940953 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 23:46:46.944068 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 23:46:46.950747 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 23:46:46.954298 1 0 24 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
2597 23:46:46.957334 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
2598 23:46:46.964082 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2599 23:46:46.967949 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 23:46:46.971208 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 23:46:46.977444 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 23:46:46.980662 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 23:46:46.984752 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 23:46:46.991312 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2605 23:46:46.994494 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2606 23:46:46.997623 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2607 23:46:47.004465 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 23:46:47.007850 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 23:46:47.010936 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 23:46:47.014319 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 23:46:47.020753 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 23:46:47.024708 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:46:47.027605 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:46:47.034517 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:46:47.037840 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:46:47.041110 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 23:46:47.047847 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 23:46:47.051092 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 23:46:47.054527 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 23:46:47.061030 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2621 23:46:47.064155 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2622 23:46:47.067632 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 23:46:47.070970 Total UI for P1: 0, mck2ui 16
2624 23:46:47.074463 best dqsien dly found for B0: ( 1, 3, 26)
2625 23:46:47.077900 Total UI for P1: 0, mck2ui 16
2626 23:46:47.080802 best dqsien dly found for B1: ( 1, 3, 28)
2627 23:46:47.084653 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2628 23:46:47.087846 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2629 23:46:47.087949
2630 23:46:47.094329 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2631 23:46:47.097856 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2632 23:46:47.097962 [Gating] SW calibration Done
2633 23:46:47.098068 ==
2634 23:46:47.101085 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 23:46:47.108297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 23:46:47.108423 ==
2637 23:46:47.108521 RX Vref Scan: 0
2638 23:46:47.108615
2639 23:46:47.111304 RX Vref 0 -> 0, step: 1
2640 23:46:47.111379
2641 23:46:47.114284 RX Delay -40 -> 252, step: 8
2642 23:46:47.118118 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2643 23:46:47.121266 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2644 23:46:47.124592 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2645 23:46:47.131479 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2646 23:46:47.134806 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2647 23:46:47.138119 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2648 23:46:47.141252 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2649 23:46:47.144237 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2650 23:46:47.147874 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2651 23:46:47.154684 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2652 23:46:47.157854 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2653 23:46:47.161107 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2654 23:46:47.164610 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2655 23:46:47.168482 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2656 23:46:47.175085 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2657 23:46:47.178319 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2658 23:46:47.178423 ==
2659 23:46:47.181440 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 23:46:47.184972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 23:46:47.185048 ==
2662 23:46:47.188593 DQS Delay:
2663 23:46:47.188671 DQS0 = 0, DQS1 = 0
2664 23:46:47.188734 DQM Delay:
2665 23:46:47.191736 DQM0 = 121, DQM1 = 112
2666 23:46:47.191806 DQ Delay:
2667 23:46:47.194939 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2668 23:46:47.198269 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2669 23:46:47.201642 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2670 23:46:47.208091 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119
2671 23:46:47.208175
2672 23:46:47.208242
2673 23:46:47.208302 ==
2674 23:46:47.211404 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 23:46:47.214737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 23:46:47.214821 ==
2677 23:46:47.214888
2678 23:46:47.214949
2679 23:46:47.218469 TX Vref Scan disable
2680 23:46:47.218553 == TX Byte 0 ==
2681 23:46:47.225000 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2682 23:46:47.228423 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2683 23:46:47.228502 == TX Byte 1 ==
2684 23:46:47.234911 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2685 23:46:47.238185 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2686 23:46:47.238260 ==
2687 23:46:47.241428 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 23:46:47.244702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 23:46:47.244804 ==
2690 23:46:47.257890 TX Vref=22, minBit 4, minWin=24, winSum=403
2691 23:46:47.261126 TX Vref=24, minBit 4, minWin=24, winSum=410
2692 23:46:47.264255 TX Vref=26, minBit 10, minWin=25, winSum=417
2693 23:46:47.267535 TX Vref=28, minBit 7, minWin=25, winSum=416
2694 23:46:47.271008 TX Vref=30, minBit 0, minWin=26, winSum=421
2695 23:46:47.273958 TX Vref=32, minBit 1, minWin=26, winSum=422
2696 23:46:47.280886 [TxChooseVref] Worse bit 1, Min win 26, Win sum 422, Final Vref 32
2697 23:46:47.280966
2698 23:46:47.284009 Final TX Range 1 Vref 32
2699 23:46:47.284125
2700 23:46:47.284256 ==
2701 23:46:47.287700 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 23:46:47.290915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 23:46:47.291016 ==
2704 23:46:47.291106
2705 23:46:47.294048
2706 23:46:47.294145 TX Vref Scan disable
2707 23:46:47.297842 == TX Byte 0 ==
2708 23:46:47.301388 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2709 23:46:47.304507 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2710 23:46:47.307813 == TX Byte 1 ==
2711 23:46:47.311080 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2712 23:46:47.314374 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2713 23:46:47.314448
2714 23:46:47.317717 [DATLAT]
2715 23:46:47.317817 Freq=1200, CH0 RK0
2716 23:46:47.317915
2717 23:46:47.321053 DATLAT Default: 0xd
2718 23:46:47.321141 0, 0xFFFF, sum = 0
2719 23:46:47.324463 1, 0xFFFF, sum = 0
2720 23:46:47.324538 2, 0xFFFF, sum = 0
2721 23:46:47.327603 3, 0xFFFF, sum = 0
2722 23:46:47.327703 4, 0xFFFF, sum = 0
2723 23:46:47.330669 5, 0xFFFF, sum = 0
2724 23:46:47.330777 6, 0xFFFF, sum = 0
2725 23:46:47.334400 7, 0xFFFF, sum = 0
2726 23:46:47.334477 8, 0xFFFF, sum = 0
2727 23:46:47.337725 9, 0xFFFF, sum = 0
2728 23:46:47.340933 10, 0xFFFF, sum = 0
2729 23:46:47.341042 11, 0xFFFF, sum = 0
2730 23:46:47.344242 12, 0x0, sum = 1
2731 23:46:47.344352 13, 0x0, sum = 2
2732 23:46:47.344454 14, 0x0, sum = 3
2733 23:46:47.347464 15, 0x0, sum = 4
2734 23:46:47.347561 best_step = 13
2735 23:46:47.347660
2736 23:46:47.350777 ==
2737 23:46:47.350947 Dram Type= 6, Freq= 0, CH_0, rank 0
2738 23:46:47.357284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2739 23:46:47.357358 ==
2740 23:46:47.357420 RX Vref Scan: 1
2741 23:46:47.357482
2742 23:46:47.361215 Set Vref Range= 32 -> 127
2743 23:46:47.361284
2744 23:46:47.363860 RX Vref 32 -> 127, step: 1
2745 23:46:47.363969
2746 23:46:47.367618 RX Delay -13 -> 252, step: 4
2747 23:46:47.367718
2748 23:46:47.370796 Set Vref, RX VrefLevel [Byte0]: 32
2749 23:46:47.374048 [Byte1]: 32
2750 23:46:47.374124
2751 23:46:47.377915 Set Vref, RX VrefLevel [Byte0]: 33
2752 23:46:47.381013 [Byte1]: 33
2753 23:46:47.381087
2754 23:46:47.384104 Set Vref, RX VrefLevel [Byte0]: 34
2755 23:46:47.387151 [Byte1]: 34
2756 23:46:47.391822
2757 23:46:47.391897 Set Vref, RX VrefLevel [Byte0]: 35
2758 23:46:47.394799 [Byte1]: 35
2759 23:46:47.399646
2760 23:46:47.399729 Set Vref, RX VrefLevel [Byte0]: 36
2761 23:46:47.402643 [Byte1]: 36
2762 23:46:47.407152
2763 23:46:47.407235 Set Vref, RX VrefLevel [Byte0]: 37
2764 23:46:47.410724 [Byte1]: 37
2765 23:46:47.415279
2766 23:46:47.415377 Set Vref, RX VrefLevel [Byte0]: 38
2767 23:46:47.418795 [Byte1]: 38
2768 23:46:47.423153
2769 23:46:47.423262 Set Vref, RX VrefLevel [Byte0]: 39
2770 23:46:47.426503 [Byte1]: 39
2771 23:46:47.431054
2772 23:46:47.431157 Set Vref, RX VrefLevel [Byte0]: 40
2773 23:46:47.434383 [Byte1]: 40
2774 23:46:47.438663
2775 23:46:47.438779 Set Vref, RX VrefLevel [Byte0]: 41
2776 23:46:47.442492 [Byte1]: 41
2777 23:46:47.446596
2778 23:46:47.446693 Set Vref, RX VrefLevel [Byte0]: 42
2779 23:46:47.449966 [Byte1]: 42
2780 23:46:47.454445
2781 23:46:47.454527 Set Vref, RX VrefLevel [Byte0]: 43
2782 23:46:47.461036 [Byte1]: 43
2783 23:46:47.461119
2784 23:46:47.464462 Set Vref, RX VrefLevel [Byte0]: 44
2785 23:46:47.467741 [Byte1]: 44
2786 23:46:47.467860
2787 23:46:47.471194 Set Vref, RX VrefLevel [Byte0]: 45
2788 23:46:47.474471 [Byte1]: 45
2789 23:46:47.478291
2790 23:46:47.478447 Set Vref, RX VrefLevel [Byte0]: 46
2791 23:46:47.481996 [Byte1]: 46
2792 23:46:47.486026
2793 23:46:47.486137 Set Vref, RX VrefLevel [Byte0]: 47
2794 23:46:47.489805 [Byte1]: 47
2795 23:46:47.494454
2796 23:46:47.494575 Set Vref, RX VrefLevel [Byte0]: 48
2797 23:46:47.497570 [Byte1]: 48
2798 23:46:47.502200
2799 23:46:47.502325 Set Vref, RX VrefLevel [Byte0]: 49
2800 23:46:47.505384 [Byte1]: 49
2801 23:46:47.509966
2802 23:46:47.510077 Set Vref, RX VrefLevel [Byte0]: 50
2803 23:46:47.513295 [Byte1]: 50
2804 23:46:47.517765
2805 23:46:47.517879 Set Vref, RX VrefLevel [Byte0]: 51
2806 23:46:47.520967 [Byte1]: 51
2807 23:46:47.525507
2808 23:46:47.525585 Set Vref, RX VrefLevel [Byte0]: 52
2809 23:46:47.529053 [Byte1]: 52
2810 23:46:47.533543
2811 23:46:47.533628 Set Vref, RX VrefLevel [Byte0]: 53
2812 23:46:47.536794 [Byte1]: 53
2813 23:46:47.541557
2814 23:46:47.541642 Set Vref, RX VrefLevel [Byte0]: 54
2815 23:46:47.544674 [Byte1]: 54
2816 23:46:47.549322
2817 23:46:47.549406 Set Vref, RX VrefLevel [Byte0]: 55
2818 23:46:47.552673 [Byte1]: 55
2819 23:46:47.557276
2820 23:46:47.557360 Set Vref, RX VrefLevel [Byte0]: 56
2821 23:46:47.561057 [Byte1]: 56
2822 23:46:47.565253
2823 23:46:47.565366 Set Vref, RX VrefLevel [Byte0]: 57
2824 23:46:47.568498 [Byte1]: 57
2825 23:46:47.573142
2826 23:46:47.573226 Set Vref, RX VrefLevel [Byte0]: 58
2827 23:46:47.576343 [Byte1]: 58
2828 23:46:47.580850
2829 23:46:47.580935 Set Vref, RX VrefLevel [Byte0]: 59
2830 23:46:47.584563 [Byte1]: 59
2831 23:46:47.588845
2832 23:46:47.588930 Set Vref, RX VrefLevel [Byte0]: 60
2833 23:46:47.592029 [Byte1]: 60
2834 23:46:47.596628
2835 23:46:47.596712 Set Vref, RX VrefLevel [Byte0]: 61
2836 23:46:47.599869 [Byte1]: 61
2837 23:46:47.604335
2838 23:46:47.604426 Set Vref, RX VrefLevel [Byte0]: 62
2839 23:46:47.607702 [Byte1]: 62
2840 23:46:47.612493
2841 23:46:47.612578 Set Vref, RX VrefLevel [Byte0]: 63
2842 23:46:47.615886 [Byte1]: 63
2843 23:46:47.620411
2844 23:46:47.620528 Set Vref, RX VrefLevel [Byte0]: 64
2845 23:46:47.623819 [Byte1]: 64
2846 23:46:47.628256
2847 23:46:47.628374 Set Vref, RX VrefLevel [Byte0]: 65
2848 23:46:47.631792 [Byte1]: 65
2849 23:46:47.636499
2850 23:46:47.636605 Set Vref, RX VrefLevel [Byte0]: 66
2851 23:46:47.639739 [Byte1]: 66
2852 23:46:47.644113
2853 23:46:47.644198 Set Vref, RX VrefLevel [Byte0]: 67
2854 23:46:47.647413 [Byte1]: 67
2855 23:46:47.651875
2856 23:46:47.651987 Set Vref, RX VrefLevel [Byte0]: 68
2857 23:46:47.655593 [Byte1]: 68
2858 23:46:47.659940
2859 23:46:47.660046 Set Vref, RX VrefLevel [Byte0]: 69
2860 23:46:47.663386 [Byte1]: 69
2861 23:46:47.667493
2862 23:46:47.667574 Set Vref, RX VrefLevel [Byte0]: 70
2863 23:46:47.670892 [Byte1]: 70
2864 23:46:47.675610
2865 23:46:47.675715 Final RX Vref Byte 0 = 56 to rank0
2866 23:46:47.678888 Final RX Vref Byte 1 = 54 to rank0
2867 23:46:47.682312 Final RX Vref Byte 0 = 56 to rank1
2868 23:46:47.685999 Final RX Vref Byte 1 = 54 to rank1==
2869 23:46:47.689233 Dram Type= 6, Freq= 0, CH_0, rank 0
2870 23:46:47.695941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 23:46:47.696028 ==
2872 23:46:47.696095 DQS Delay:
2873 23:46:47.696157 DQS0 = 0, DQS1 = 0
2874 23:46:47.699057 DQM Delay:
2875 23:46:47.699142 DQM0 = 121, DQM1 = 112
2876 23:46:47.702690 DQ Delay:
2877 23:46:47.705779 DQ0 =120, DQ1 =124, DQ2 =118, DQ3 =120
2878 23:46:47.708994 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2879 23:46:47.712227 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
2880 23:46:47.715496 DQ12 =118, DQ13 =118, DQ14 =124, DQ15 =120
2881 23:46:47.715581
2882 23:46:47.715648
2883 23:46:47.722120 [DQSOSCAuto] RK0, (LSB)MR18= 0x150e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2884 23:46:47.726026 CH0 RK0: MR19=404, MR18=150E
2885 23:46:47.732588 CH0_RK0: MR19=0x404, MR18=0x150E, DQSOSC=401, MR23=63, INC=40, DEC=27
2886 23:46:47.732673
2887 23:46:47.735833 ----->DramcWriteLeveling(PI) begin...
2888 23:46:47.735919 ==
2889 23:46:47.739113 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 23:46:47.742440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 23:46:47.745700 ==
2892 23:46:47.745785 Write leveling (Byte 0): 34 => 34
2893 23:46:47.749000 Write leveling (Byte 1): 29 => 29
2894 23:46:47.752204 DramcWriteLeveling(PI) end<-----
2895 23:46:47.752314
2896 23:46:47.752398 ==
2897 23:46:47.755516 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 23:46:47.762342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 23:46:47.762426 ==
2900 23:46:47.762493 [Gating] SW mode calibration
2901 23:46:47.772794 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2902 23:46:47.775907 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2903 23:46:47.779189 0 15 0 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
2904 23:46:47.785912 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 23:46:47.788959 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 23:46:47.792428 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 23:46:47.798921 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 23:46:47.802315 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 23:46:47.805695 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 23:46:47.812501 0 15 28 | B1->B0 | 2d2d 2e2e | 0 0 | (0 0) (0 0)
2911 23:46:47.815766 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2912 23:46:47.819106 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 23:46:47.825619 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 23:46:47.828826 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 23:46:47.832715 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 23:46:47.839364 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 23:46:47.842687 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2918 23:46:47.845937 1 0 28 | B1->B0 | 4141 4141 | 0 1 | (0 0) (0 0)
2919 23:46:47.852450 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 23:46:47.855849 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 23:46:47.859094 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 23:46:47.862329 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 23:46:47.869506 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 23:46:47.872526 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 23:46:47.875468 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 23:46:47.882854 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2927 23:46:47.885950 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 23:46:47.889003 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 23:46:47.895619 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 23:46:47.898816 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 23:46:47.902661 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:46:47.909453 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 23:46:47.912272 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 23:46:47.915656 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 23:46:47.922544 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 23:46:47.926037 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 23:46:47.929077 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 23:46:47.935553 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 23:46:47.939611 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 23:46:47.942903 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 23:46:47.949453 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2942 23:46:47.952890 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2943 23:46:47.956094 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2944 23:46:47.959681 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 23:46:47.962763 Total UI for P1: 0, mck2ui 16
2946 23:46:47.965981 best dqsien dly found for B0: ( 1, 3, 30)
2947 23:46:47.969209 Total UI for P1: 0, mck2ui 16
2948 23:46:47.972374 best dqsien dly found for B1: ( 1, 3, 28)
2949 23:46:47.975670 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2950 23:46:47.979515 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2951 23:46:47.982462
2952 23:46:47.985851 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2953 23:46:47.988929 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2954 23:46:47.992752 [Gating] SW calibration Done
2955 23:46:47.992835 ==
2956 23:46:47.996027 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 23:46:47.999279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 23:46:47.999362 ==
2959 23:46:47.999427 RX Vref Scan: 0
2960 23:46:47.999489
2961 23:46:48.002487 RX Vref 0 -> 0, step: 1
2962 23:46:48.002570
2963 23:46:48.006272 RX Delay -40 -> 252, step: 8
2964 23:46:48.009394 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2965 23:46:48.012748 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2966 23:46:48.019442 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2967 23:46:48.022634 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2968 23:46:48.025846 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2969 23:46:48.029561 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2970 23:46:48.032544 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2971 23:46:48.036054 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2972 23:46:48.042594 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2973 23:46:48.046176 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2974 23:46:48.049653 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2975 23:46:48.052507 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2976 23:46:48.056125 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2977 23:46:48.062913 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2978 23:46:48.066191 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2979 23:46:48.069514 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2980 23:46:48.069630 ==
2981 23:46:48.073022 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 23:46:48.076350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 23:46:48.079537 ==
2984 23:46:48.079620 DQS Delay:
2985 23:46:48.079684 DQS0 = 0, DQS1 = 0
2986 23:46:48.082774 DQM Delay:
2987 23:46:48.082857 DQM0 = 122, DQM1 = 113
2988 23:46:48.085877 DQ Delay:
2989 23:46:48.089208 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2990 23:46:48.092883 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2991 23:46:48.096178 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
2992 23:46:48.099716 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2993 23:46:48.099798
2994 23:46:48.099863
2995 23:46:48.099923 ==
2996 23:46:48.102769 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 23:46:48.106123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 23:46:48.106206 ==
2999 23:46:48.106272
3000 23:46:48.106333
3001 23:46:48.109685 TX Vref Scan disable
3002 23:46:48.112744 == TX Byte 0 ==
3003 23:46:48.116465 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3004 23:46:48.119956 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3005 23:46:48.123298 == TX Byte 1 ==
3006 23:46:48.126453 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3007 23:46:48.129752 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3008 23:46:48.129834 ==
3009 23:46:48.133063 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 23:46:48.136207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 23:46:48.136290 ==
3012 23:46:48.150024 TX Vref=22, minBit 2, minWin=25, winSum=415
3013 23:46:48.153151 TX Vref=24, minBit 3, minWin=25, winSum=419
3014 23:46:48.156276 TX Vref=26, minBit 0, minWin=26, winSum=424
3015 23:46:48.160093 TX Vref=28, minBit 1, minWin=26, winSum=430
3016 23:46:48.163641 TX Vref=30, minBit 1, minWin=26, winSum=427
3017 23:46:48.170090 TX Vref=32, minBit 0, minWin=26, winSum=426
3018 23:46:48.173167 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 28
3019 23:46:48.173290
3020 23:46:48.176214 Final TX Range 1 Vref 28
3021 23:46:48.176326
3022 23:46:48.176406 ==
3023 23:46:48.179926 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 23:46:48.183034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 23:46:48.183117 ==
3026 23:46:48.186310
3027 23:46:48.186393
3028 23:46:48.186458 TX Vref Scan disable
3029 23:46:48.189998 == TX Byte 0 ==
3030 23:46:48.193290 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3031 23:46:48.196725 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3032 23:46:48.199786 == TX Byte 1 ==
3033 23:46:48.203131 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3034 23:46:48.206262 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3035 23:46:48.209983
3036 23:46:48.210065 [DATLAT]
3037 23:46:48.210130 Freq=1200, CH0 RK1
3038 23:46:48.210192
3039 23:46:48.213165 DATLAT Default: 0xd
3040 23:46:48.213248 0, 0xFFFF, sum = 0
3041 23:46:48.216375 1, 0xFFFF, sum = 0
3042 23:46:48.216518 2, 0xFFFF, sum = 0
3043 23:46:48.219628 3, 0xFFFF, sum = 0
3044 23:46:48.219712 4, 0xFFFF, sum = 0
3045 23:46:48.223392 5, 0xFFFF, sum = 0
3046 23:46:48.226877 6, 0xFFFF, sum = 0
3047 23:46:48.226963 7, 0xFFFF, sum = 0
3048 23:46:48.229985 8, 0xFFFF, sum = 0
3049 23:46:48.230070 9, 0xFFFF, sum = 0
3050 23:46:48.233313 10, 0xFFFF, sum = 0
3051 23:46:48.233398 11, 0xFFFF, sum = 0
3052 23:46:48.236306 12, 0x0, sum = 1
3053 23:46:48.236413 13, 0x0, sum = 2
3054 23:46:48.239588 14, 0x0, sum = 3
3055 23:46:48.239674 15, 0x0, sum = 4
3056 23:46:48.239741 best_step = 13
3057 23:46:48.239803
3058 23:46:48.243577 ==
3059 23:46:48.246824 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 23:46:48.250065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 23:46:48.250150 ==
3062 23:46:48.250217 RX Vref Scan: 0
3063 23:46:48.250279
3064 23:46:48.253477 RX Vref 0 -> 0, step: 1
3065 23:46:48.253561
3066 23:46:48.256810 RX Delay -13 -> 252, step: 4
3067 23:46:48.260043 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3068 23:46:48.263060 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3069 23:46:48.270276 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3070 23:46:48.273351 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3071 23:46:48.276585 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3072 23:46:48.280435 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3073 23:46:48.283496 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3074 23:46:48.290262 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3075 23:46:48.293466 iDelay=195, Bit 8, Center 102 (35 ~ 170) 136
3076 23:46:48.296842 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3077 23:46:48.299844 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3078 23:46:48.303228 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3079 23:46:48.310065 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3080 23:46:48.313185 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3081 23:46:48.316686 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3082 23:46:48.319587 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3083 23:46:48.319672 ==
3084 23:46:48.323177 Dram Type= 6, Freq= 0, CH_0, rank 1
3085 23:46:48.330168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 23:46:48.330255 ==
3087 23:46:48.330322 DQS Delay:
3088 23:46:48.333023 DQS0 = 0, DQS1 = 0
3089 23:46:48.333108 DQM Delay:
3090 23:46:48.333176 DQM0 = 120, DQM1 = 111
3091 23:46:48.336637 DQ Delay:
3092 23:46:48.339723 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3093 23:46:48.342993 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3094 23:46:48.346328 DQ8 =102, DQ9 =100, DQ10 =110, DQ11 =104
3095 23:46:48.349660 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3096 23:46:48.349738
3097 23:46:48.349808
3098 23:46:48.360113 [DQSOSCAuto] RK1, (LSB)MR18= 0xeef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3099 23:46:48.360200 CH0 RK1: MR19=403, MR18=EEF
3100 23:46:48.366772 CH0_RK1: MR19=0x403, MR18=0xEEF, DQSOSC=404, MR23=63, INC=40, DEC=26
3101 23:46:48.369759 [RxdqsGatingPostProcess] freq 1200
3102 23:46:48.376462 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3103 23:46:48.379824 best DQS0 dly(2T, 0.5T) = (0, 11)
3104 23:46:48.379910 best DQS1 dly(2T, 0.5T) = (0, 11)
3105 23:46:48.383182 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3106 23:46:48.386458 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3107 23:46:48.390040 best DQS0 dly(2T, 0.5T) = (0, 11)
3108 23:46:48.393454 best DQS1 dly(2T, 0.5T) = (0, 11)
3109 23:46:48.396842 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3110 23:46:48.400036 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3111 23:46:48.403336 Pre-setting of DQS Precalculation
3112 23:46:48.410465 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3113 23:46:48.410552 ==
3114 23:46:48.413708 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 23:46:48.416934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 23:46:48.417019 ==
3117 23:46:48.423329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3118 23:46:48.426533 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3119 23:46:48.436356 [CA 0] Center 37 (7~68) winsize 62
3120 23:46:48.439708 [CA 1] Center 37 (7~68) winsize 62
3121 23:46:48.443199 [CA 2] Center 35 (5~65) winsize 61
3122 23:46:48.446240 [CA 3] Center 34 (5~64) winsize 60
3123 23:46:48.449522 [CA 4] Center 34 (4~64) winsize 61
3124 23:46:48.453234 [CA 5] Center 33 (3~63) winsize 61
3125 23:46:48.453320
3126 23:46:48.456230 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3127 23:46:48.456315
3128 23:46:48.459610 [CATrainingPosCal] consider 1 rank data
3129 23:46:48.463150 u2DelayCellTimex100 = 270/100 ps
3130 23:46:48.466386 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3131 23:46:48.469519 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3132 23:46:48.476414 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3133 23:46:48.479772 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3134 23:46:48.483033 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3135 23:46:48.486595 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3136 23:46:48.486697
3137 23:46:48.489662 CA PerBit enable=1, Macro0, CA PI delay=33
3138 23:46:48.489768
3139 23:46:48.492918 [CBTSetCACLKResult] CA Dly = 33
3140 23:46:48.493023 CS Dly: 7 (0~38)
3141 23:46:48.493115 ==
3142 23:46:48.496640 Dram Type= 6, Freq= 0, CH_1, rank 1
3143 23:46:48.503414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 23:46:48.503511 ==
3145 23:46:48.506663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3146 23:46:48.513156 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3147 23:46:48.522103 [CA 0] Center 37 (7~68) winsize 62
3148 23:46:48.525228 [CA 1] Center 37 (7~68) winsize 62
3149 23:46:48.528463 [CA 2] Center 35 (5~65) winsize 61
3150 23:46:48.531723 [CA 3] Center 34 (4~65) winsize 62
3151 23:46:48.535021 [CA 4] Center 34 (4~65) winsize 62
3152 23:46:48.538863 [CA 5] Center 34 (4~64) winsize 61
3153 23:46:48.538943
3154 23:46:48.542116 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3155 23:46:48.542196
3156 23:46:48.545621 [CATrainingPosCal] consider 2 rank data
3157 23:46:48.548780 u2DelayCellTimex100 = 270/100 ps
3158 23:46:48.551978 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3159 23:46:48.555174 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3160 23:46:48.559064 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3161 23:46:48.565284 CA3 delay=34 (5~64),Diff = 1 PI (4 cell)
3162 23:46:48.568512 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3163 23:46:48.572096 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3164 23:46:48.572206
3165 23:46:48.575309 CA PerBit enable=1, Macro0, CA PI delay=33
3166 23:46:48.575415
3167 23:46:48.579051 [CBTSetCACLKResult] CA Dly = 33
3168 23:46:48.579160 CS Dly: 8 (0~41)
3169 23:46:48.579255
3170 23:46:48.582054 ----->DramcWriteLeveling(PI) begin...
3171 23:46:48.582165 ==
3172 23:46:48.585522 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 23:46:48.592275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 23:46:48.592402 ==
3175 23:46:48.595709 Write leveling (Byte 0): 27 => 27
3176 23:46:48.595813 Write leveling (Byte 1): 27 => 27
3177 23:46:48.599030 DramcWriteLeveling(PI) end<-----
3178 23:46:48.599136
3179 23:46:48.602533 ==
3180 23:46:48.605719 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 23:46:48.609096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 23:46:48.609200 ==
3183 23:46:48.612208 [Gating] SW mode calibration
3184 23:46:48.618784 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3185 23:46:48.622568 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3186 23:46:48.629021 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3187 23:46:48.632236 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 23:46:48.635501 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 23:46:48.642141 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 23:46:48.645401 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 23:46:48.648732 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 23:46:48.655401 0 15 24 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (0 0)
3193 23:46:48.658753 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3194 23:46:48.662029 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 23:46:48.665913 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 23:46:48.672505 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 23:46:48.675783 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 23:46:48.679087 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 23:46:48.685673 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3200 23:46:48.688972 1 0 24 | B1->B0 | 2f2f 3b3b | 1 1 | (0 0) (0 0)
3201 23:46:48.692132 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 23:46:48.698893 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 23:46:48.702416 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 23:46:48.706084 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 23:46:48.712411 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 23:46:48.715735 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 23:46:48.718983 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 23:46:48.725843 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3209 23:46:48.729049 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3210 23:46:48.732408 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 23:46:48.739054 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 23:46:48.742423 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:46:48.745865 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:46:48.749152 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 23:46:48.755899 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 23:46:48.759018 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 23:46:48.762764 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 23:46:48.769215 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 23:46:48.772476 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 23:46:48.775824 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 23:46:48.782361 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 23:46:48.785628 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 23:46:48.789519 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 23:46:48.796133 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3225 23:46:48.799646 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3226 23:46:48.802691 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 23:46:48.806091 Total UI for P1: 0, mck2ui 16
3228 23:46:48.809303 best dqsien dly found for B0: ( 1, 3, 26)
3229 23:46:48.812603 Total UI for P1: 0, mck2ui 16
3230 23:46:48.816295 best dqsien dly found for B1: ( 1, 3, 26)
3231 23:46:48.819106 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3232 23:46:48.822914 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3233 23:46:48.823028
3234 23:46:48.826140 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3235 23:46:48.832483 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3236 23:46:48.832566 [Gating] SW calibration Done
3237 23:46:48.832633 ==
3238 23:46:48.836117 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 23:46:48.842712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 23:46:48.842815 ==
3241 23:46:48.842886 RX Vref Scan: 0
3242 23:46:48.842950
3243 23:46:48.845953 RX Vref 0 -> 0, step: 1
3244 23:46:48.846045
3245 23:46:48.848996 RX Delay -40 -> 252, step: 8
3246 23:46:48.852475 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3247 23:46:48.855909 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3248 23:46:48.859590 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3249 23:46:48.862530 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3250 23:46:48.869525 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3251 23:46:48.872754 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3252 23:46:48.876257 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3253 23:46:48.879707 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3254 23:46:48.883249 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3255 23:46:48.889704 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3256 23:46:48.893181 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3257 23:46:48.896478 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3258 23:46:48.899715 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3259 23:46:48.903073 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3260 23:46:48.909858 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3261 23:46:48.913073 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3262 23:46:48.913156 ==
3263 23:46:48.916295 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 23:46:48.919725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 23:46:48.919831 ==
3266 23:46:48.923000 DQS Delay:
3267 23:46:48.923117 DQS0 = 0, DQS1 = 0
3268 23:46:48.923210 DQM Delay:
3269 23:46:48.926236 DQM0 = 120, DQM1 = 116
3270 23:46:48.926343 DQ Delay:
3271 23:46:48.929646 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3272 23:46:48.932845 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3273 23:46:48.936163 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3274 23:46:48.943571 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3275 23:46:48.943684
3276 23:46:48.943782
3277 23:46:48.943882 ==
3278 23:46:48.946270 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 23:46:48.949812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 23:46:48.949896 ==
3281 23:46:48.949962
3282 23:46:48.950024
3283 23:46:48.952985 TX Vref Scan disable
3284 23:46:48.953057 == TX Byte 0 ==
3285 23:46:48.959555 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3286 23:46:48.962934 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3287 23:46:48.963039 == TX Byte 1 ==
3288 23:46:48.969611 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3289 23:46:48.973329 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3290 23:46:48.973415 ==
3291 23:46:48.976438 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 23:46:48.979427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 23:46:48.979504 ==
3294 23:46:48.991678 TX Vref=22, minBit 9, minWin=24, winSum=409
3295 23:46:48.995141 TX Vref=24, minBit 9, minWin=24, winSum=414
3296 23:46:48.998580 TX Vref=26, minBit 9, minWin=25, winSum=424
3297 23:46:49.002040 TX Vref=28, minBit 9, minWin=25, winSum=423
3298 23:46:49.005664 TX Vref=30, minBit 1, minWin=26, winSum=429
3299 23:46:49.009263 TX Vref=32, minBit 9, minWin=26, winSum=430
3300 23:46:49.015756 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 32
3301 23:46:49.015866
3302 23:46:49.019169 Final TX Range 1 Vref 32
3303 23:46:49.019275
3304 23:46:49.019368 ==
3305 23:46:49.022135 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 23:46:49.025610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 23:46:49.025716 ==
3308 23:46:49.025809
3309 23:46:49.025908
3310 23:46:49.028673 TX Vref Scan disable
3311 23:46:49.031938 == TX Byte 0 ==
3312 23:46:49.035269 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3313 23:46:49.038644 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3314 23:46:49.042075 == TX Byte 1 ==
3315 23:46:49.045456 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3316 23:46:49.048666 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3317 23:46:49.048749
3318 23:46:49.051933 [DATLAT]
3319 23:46:49.052019 Freq=1200, CH1 RK0
3320 23:46:49.052094
3321 23:46:49.055540 DATLAT Default: 0xd
3322 23:46:49.055622 0, 0xFFFF, sum = 0
3323 23:46:49.058998 1, 0xFFFF, sum = 0
3324 23:46:49.059079 2, 0xFFFF, sum = 0
3325 23:46:49.062140 3, 0xFFFF, sum = 0
3326 23:46:49.062224 4, 0xFFFF, sum = 0
3327 23:46:49.065510 5, 0xFFFF, sum = 0
3328 23:46:49.065590 6, 0xFFFF, sum = 0
3329 23:46:49.068722 7, 0xFFFF, sum = 0
3330 23:46:49.068826 8, 0xFFFF, sum = 0
3331 23:46:49.071993 9, 0xFFFF, sum = 0
3332 23:46:49.072071 10, 0xFFFF, sum = 0
3333 23:46:49.075268 11, 0xFFFF, sum = 0
3334 23:46:49.075344 12, 0x0, sum = 1
3335 23:46:49.078966 13, 0x0, sum = 2
3336 23:46:49.079048 14, 0x0, sum = 3
3337 23:46:49.082091 15, 0x0, sum = 4
3338 23:46:49.082171 best_step = 13
3339 23:46:49.082241
3340 23:46:49.082302 ==
3341 23:46:49.085420 Dram Type= 6, Freq= 0, CH_1, rank 0
3342 23:46:49.092614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3343 23:46:49.092701 ==
3344 23:46:49.092771 RX Vref Scan: 1
3345 23:46:49.092840
3346 23:46:49.095896 Set Vref Range= 32 -> 127
3347 23:46:49.095974
3348 23:46:49.099133 RX Vref 32 -> 127, step: 1
3349 23:46:49.099214
3350 23:46:49.099278 RX Delay -5 -> 252, step: 4
3351 23:46:49.102281
3352 23:46:49.102356 Set Vref, RX VrefLevel [Byte0]: 32
3353 23:46:49.105420 [Byte1]: 32
3354 23:46:49.110273
3355 23:46:49.110360 Set Vref, RX VrefLevel [Byte0]: 33
3356 23:46:49.113345 [Byte1]: 33
3357 23:46:49.117867
3358 23:46:49.117945 Set Vref, RX VrefLevel [Byte0]: 34
3359 23:46:49.121038 [Byte1]: 34
3360 23:46:49.125522
3361 23:46:49.125600 Set Vref, RX VrefLevel [Byte0]: 35
3362 23:46:49.129236 [Byte1]: 35
3363 23:46:49.133589
3364 23:46:49.133668 Set Vref, RX VrefLevel [Byte0]: 36
3365 23:46:49.137034 [Byte1]: 36
3366 23:46:49.141749
3367 23:46:49.141829 Set Vref, RX VrefLevel [Byte0]: 37
3368 23:46:49.144812 [Byte1]: 37
3369 23:46:49.149491
3370 23:46:49.149571 Set Vref, RX VrefLevel [Byte0]: 38
3371 23:46:49.152846 [Byte1]: 38
3372 23:46:49.156738
3373 23:46:49.156827 Set Vref, RX VrefLevel [Byte0]: 39
3374 23:46:49.160687 [Byte1]: 39
3375 23:46:49.165048
3376 23:46:49.165137 Set Vref, RX VrefLevel [Byte0]: 40
3377 23:46:49.167984 [Byte1]: 40
3378 23:46:49.173058
3379 23:46:49.173139 Set Vref, RX VrefLevel [Byte0]: 41
3380 23:46:49.175756 [Byte1]: 41
3381 23:46:49.180286
3382 23:46:49.180390 Set Vref, RX VrefLevel [Byte0]: 42
3383 23:46:49.184139 [Byte1]: 42
3384 23:46:49.188136
3385 23:46:49.188222 Set Vref, RX VrefLevel [Byte0]: 43
3386 23:46:49.191501 [Byte1]: 43
3387 23:46:49.196781
3388 23:46:49.196866 Set Vref, RX VrefLevel [Byte0]: 44
3389 23:46:49.199854 [Byte1]: 44
3390 23:46:49.204004
3391 23:46:49.204084 Set Vref, RX VrefLevel [Byte0]: 45
3392 23:46:49.207645 [Byte1]: 45
3393 23:46:49.212284
3394 23:46:49.212390 Set Vref, RX VrefLevel [Byte0]: 46
3395 23:46:49.215184 [Byte1]: 46
3396 23:46:49.220075
3397 23:46:49.220184 Set Vref, RX VrefLevel [Byte0]: 47
3398 23:46:49.223175 [Byte1]: 47
3399 23:46:49.227425
3400 23:46:49.227505 Set Vref, RX VrefLevel [Byte0]: 48
3401 23:46:49.231147 [Byte1]: 48
3402 23:46:49.235761
3403 23:46:49.235856 Set Vref, RX VrefLevel [Byte0]: 49
3404 23:46:49.239228 [Byte1]: 49
3405 23:46:49.243641
3406 23:46:49.243725 Set Vref, RX VrefLevel [Byte0]: 50
3407 23:46:49.246756 [Byte1]: 50
3408 23:46:49.251041
3409 23:46:49.251119 Set Vref, RX VrefLevel [Byte0]: 51
3410 23:46:49.254480 [Byte1]: 51
3411 23:46:49.259239
3412 23:46:49.259320 Set Vref, RX VrefLevel [Byte0]: 52
3413 23:46:49.262536 [Byte1]: 52
3414 23:46:49.267142
3415 23:46:49.267225 Set Vref, RX VrefLevel [Byte0]: 53
3416 23:46:49.269994 [Byte1]: 53
3417 23:46:49.274755
3418 23:46:49.274842 Set Vref, RX VrefLevel [Byte0]: 54
3419 23:46:49.278235 [Byte1]: 54
3420 23:46:49.282828
3421 23:46:49.282907 Set Vref, RX VrefLevel [Byte0]: 55
3422 23:46:49.285604 [Byte1]: 55
3423 23:46:49.290653
3424 23:46:49.290738 Set Vref, RX VrefLevel [Byte0]: 56
3425 23:46:49.294006 [Byte1]: 56
3426 23:46:49.298163
3427 23:46:49.298239 Set Vref, RX VrefLevel [Byte0]: 57
3428 23:46:49.301746 [Byte1]: 57
3429 23:46:49.306294
3430 23:46:49.306371 Set Vref, RX VrefLevel [Byte0]: 58
3431 23:46:49.309604 [Byte1]: 58
3432 23:46:49.314416
3433 23:46:49.314493 Set Vref, RX VrefLevel [Byte0]: 59
3434 23:46:49.317322 [Byte1]: 59
3435 23:46:49.322194
3436 23:46:49.322271 Set Vref, RX VrefLevel [Byte0]: 60
3437 23:46:49.325432 [Byte1]: 60
3438 23:46:49.330503
3439 23:46:49.330579 Set Vref, RX VrefLevel [Byte0]: 61
3440 23:46:49.333122 [Byte1]: 61
3441 23:46:49.337763
3442 23:46:49.337846 Set Vref, RX VrefLevel [Byte0]: 62
3443 23:46:49.341077 [Byte1]: 62
3444 23:46:49.345802
3445 23:46:49.345915 Set Vref, RX VrefLevel [Byte0]: 63
3446 23:46:49.349109 [Byte1]: 63
3447 23:46:49.353220
3448 23:46:49.353296 Set Vref, RX VrefLevel [Byte0]: 64
3449 23:46:49.356374 [Byte1]: 64
3450 23:46:49.361099
3451 23:46:49.361203 Set Vref, RX VrefLevel [Byte0]: 65
3452 23:46:49.364182 [Byte1]: 65
3453 23:46:49.369257
3454 23:46:49.369367 Set Vref, RX VrefLevel [Byte0]: 66
3455 23:46:49.372309 [Byte1]: 66
3456 23:46:49.376855
3457 23:46:49.376960 Set Vref, RX VrefLevel [Byte0]: 67
3458 23:46:49.379914 [Byte1]: 67
3459 23:46:49.384501
3460 23:46:49.384605 Set Vref, RX VrefLevel [Byte0]: 68
3461 23:46:49.387943 [Byte1]: 68
3462 23:46:49.392529
3463 23:46:49.392635 Set Vref, RX VrefLevel [Byte0]: 69
3464 23:46:49.395708 [Byte1]: 69
3465 23:46:49.400309
3466 23:46:49.400441 Set Vref, RX VrefLevel [Byte0]: 70
3467 23:46:49.403676 [Byte1]: 70
3468 23:46:49.408266
3469 23:46:49.408377 Final RX Vref Byte 0 = 50 to rank0
3470 23:46:49.411489 Final RX Vref Byte 1 = 48 to rank0
3471 23:46:49.414777 Final RX Vref Byte 0 = 50 to rank1
3472 23:46:49.418137 Final RX Vref Byte 1 = 48 to rank1==
3473 23:46:49.421378 Dram Type= 6, Freq= 0, CH_1, rank 0
3474 23:46:49.428003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 23:46:49.428083 ==
3476 23:46:49.428150 DQS Delay:
3477 23:46:49.428251 DQS0 = 0, DQS1 = 0
3478 23:46:49.431208 DQM Delay:
3479 23:46:49.431285 DQM0 = 119, DQM1 = 116
3480 23:46:49.435051 DQ Delay:
3481 23:46:49.438152 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =114
3482 23:46:49.441634 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =120
3483 23:46:49.444748 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3484 23:46:49.448838 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3485 23:46:49.448947
3486 23:46:49.449043
3487 23:46:49.455329 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3488 23:46:49.458698 CH1 RK0: MR19=404, MR18=316
3489 23:46:49.465191 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3490 23:46:49.465278
3491 23:46:49.468430 ----->DramcWriteLeveling(PI) begin...
3492 23:46:49.468509 ==
3493 23:46:49.471734 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 23:46:49.475617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 23:46:49.475702 ==
3496 23:46:49.479051 Write leveling (Byte 0): 27 => 27
3497 23:46:49.482067 Write leveling (Byte 1): 29 => 29
3498 23:46:49.485440 DramcWriteLeveling(PI) end<-----
3499 23:46:49.485524
3500 23:46:49.485590 ==
3501 23:46:49.488712 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 23:46:49.491981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 23:46:49.492062 ==
3504 23:46:49.495343 [Gating] SW mode calibration
3505 23:46:49.502296 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3506 23:46:49.508645 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3507 23:46:49.512301 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 23:46:49.518775 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 23:46:49.522205 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 23:46:49.525813 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 23:46:49.532193 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 23:46:49.535602 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3513 23:46:49.538977 0 15 24 | B1->B0 | 2e2e 3434 | 0 1 | (1 0) (1 0)
3514 23:46:49.542148 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3515 23:46:49.548879 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 23:46:49.552656 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 23:46:49.555452 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 23:46:49.562183 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 23:46:49.565398 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 23:46:49.568779 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
3521 23:46:49.575328 1 0 24 | B1->B0 | 4545 3535 | 1 0 | (0 0) (0 0)
3522 23:46:49.578719 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 23:46:49.582486 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 23:46:49.588916 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 23:46:49.592315 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 23:46:49.595376 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 23:46:49.602116 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 23:46:49.605442 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3529 23:46:49.608737 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3530 23:46:49.615270 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3531 23:46:49.619028 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 23:46:49.622199 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 23:46:49.628816 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 23:46:49.631932 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 23:46:49.635422 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 23:46:49.642364 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 23:46:49.645595 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 23:46:49.648908 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 23:46:49.652090 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 23:46:49.658963 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 23:46:49.661976 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 23:46:49.665182 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 23:46:49.671863 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 23:46:49.675128 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3545 23:46:49.678315 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3546 23:46:49.685486 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3547 23:46:49.688681 Total UI for P1: 0, mck2ui 16
3548 23:46:49.692111 best dqsien dly found for B1: ( 1, 3, 22)
3549 23:46:49.695480 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 23:46:49.698428 Total UI for P1: 0, mck2ui 16
3551 23:46:49.702009 best dqsien dly found for B0: ( 1, 3, 28)
3552 23:46:49.704915 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3553 23:46:49.708147 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3554 23:46:49.708264
3555 23:46:49.712067 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3556 23:46:49.715379 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3557 23:46:49.718650 [Gating] SW calibration Done
3558 23:46:49.718735 ==
3559 23:46:49.721970 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 23:46:49.725091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 23:46:49.728414 ==
3562 23:46:49.728532 RX Vref Scan: 0
3563 23:46:49.728603
3564 23:46:49.731549 RX Vref 0 -> 0, step: 1
3565 23:46:49.731638
3566 23:46:49.735124 RX Delay -40 -> 252, step: 8
3567 23:46:49.738686 iDelay=200, Bit 0, Center 127 (64 ~ 191) 128
3568 23:46:49.742021 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3569 23:46:49.745127 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3570 23:46:49.748093 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3571 23:46:49.754845 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3572 23:46:49.758234 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3573 23:46:49.761628 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3574 23:46:49.765069 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3575 23:46:49.768287 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3576 23:46:49.774781 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3577 23:46:49.778037 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3578 23:46:49.781917 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3579 23:46:49.785071 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3580 23:46:49.788407 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3581 23:46:49.794963 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3582 23:46:49.798139 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3583 23:46:49.798255 ==
3584 23:46:49.801501 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 23:46:49.805092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 23:46:49.805171 ==
3587 23:46:49.808014 DQS Delay:
3588 23:46:49.808120 DQS0 = 0, DQS1 = 0
3589 23:46:49.808213 DQM Delay:
3590 23:46:49.811554 DQM0 = 120, DQM1 = 118
3591 23:46:49.811661 DQ Delay:
3592 23:46:49.814600 DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =115
3593 23:46:49.818223 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3594 23:46:49.821506 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3595 23:46:49.828247 DQ12 =127, DQ13 =123, DQ14 =123, DQ15 =123
3596 23:46:49.828388
3597 23:46:49.828475
3598 23:46:49.828540 ==
3599 23:46:49.831496 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 23:46:49.834869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 23:46:49.834991 ==
3602 23:46:49.835088
3603 23:46:49.835189
3604 23:46:49.838199 TX Vref Scan disable
3605 23:46:49.838307 == TX Byte 0 ==
3606 23:46:49.844478 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3607 23:46:49.847913 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3608 23:46:49.848028 == TX Byte 1 ==
3609 23:46:49.854515 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3610 23:46:49.857988 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3611 23:46:49.858075 ==
3612 23:46:49.861527 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 23:46:49.864729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 23:46:49.864849 ==
3615 23:46:49.877141 TX Vref=22, minBit 9, minWin=25, winSum=419
3616 23:46:49.880547 TX Vref=24, minBit 10, minWin=25, winSum=424
3617 23:46:49.883857 TX Vref=26, minBit 2, minWin=26, winSum=429
3618 23:46:49.887085 TX Vref=28, minBit 2, minWin=26, winSum=431
3619 23:46:49.890830 TX Vref=30, minBit 9, minWin=26, winSum=435
3620 23:46:49.897275 TX Vref=32, minBit 6, minWin=26, winSum=434
3621 23:46:49.900626 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3622 23:46:49.900734
3623 23:46:49.903835 Final TX Range 1 Vref 30
3624 23:46:49.903921
3625 23:46:49.903988 ==
3626 23:46:49.907142 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 23:46:49.910653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 23:46:49.910740 ==
3629 23:46:49.913809
3630 23:46:49.913893
3631 23:46:49.913980 TX Vref Scan disable
3632 23:46:49.917002 == TX Byte 0 ==
3633 23:46:49.920809 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3634 23:46:49.923867 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3635 23:46:49.927713 == TX Byte 1 ==
3636 23:46:49.930756 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3637 23:46:49.933785 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3638 23:46:49.937138
3639 23:46:49.937222 [DATLAT]
3640 23:46:49.937288 Freq=1200, CH1 RK1
3641 23:46:49.937368
3642 23:46:49.940500 DATLAT Default: 0xd
3643 23:46:49.940577 0, 0xFFFF, sum = 0
3644 23:46:49.943857 1, 0xFFFF, sum = 0
3645 23:46:49.943940 2, 0xFFFF, sum = 0
3646 23:46:49.946987 3, 0xFFFF, sum = 0
3647 23:46:49.947120 4, 0xFFFF, sum = 0
3648 23:46:49.950432 5, 0xFFFF, sum = 0
3649 23:46:49.953663 6, 0xFFFF, sum = 0
3650 23:46:49.953793 7, 0xFFFF, sum = 0
3651 23:46:49.956962 8, 0xFFFF, sum = 0
3652 23:46:49.957155 9, 0xFFFF, sum = 0
3653 23:46:49.960783 10, 0xFFFF, sum = 0
3654 23:46:49.960897 11, 0xFFFF, sum = 0
3655 23:46:49.963977 12, 0x0, sum = 1
3656 23:46:49.964054 13, 0x0, sum = 2
3657 23:46:49.966932 14, 0x0, sum = 3
3658 23:46:49.967022 15, 0x0, sum = 4
3659 23:46:49.967093 best_step = 13
3660 23:46:49.970422
3661 23:46:49.970503 ==
3662 23:46:49.973811 Dram Type= 6, Freq= 0, CH_1, rank 1
3663 23:46:49.977380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3664 23:46:49.977470 ==
3665 23:46:49.977547 RX Vref Scan: 0
3666 23:46:49.977613
3667 23:46:49.980131 RX Vref 0 -> 0, step: 1
3668 23:46:49.980205
3669 23:46:49.983711 RX Delay -5 -> 252, step: 4
3670 23:46:49.987003 iDelay=195, Bit 0, Center 124 (63 ~ 186) 124
3671 23:46:49.993928 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3672 23:46:49.997059 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3673 23:46:50.000270 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3674 23:46:50.003516 iDelay=195, Bit 4, Center 114 (55 ~ 174) 120
3675 23:46:50.006943 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3676 23:46:50.010049 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3677 23:46:50.017199 iDelay=195, Bit 7, Center 118 (59 ~ 178) 120
3678 23:46:50.020489 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3679 23:46:50.023761 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3680 23:46:50.027097 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3681 23:46:50.033251 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3682 23:46:50.036761 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3683 23:46:50.040289 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3684 23:46:50.043506 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3685 23:46:50.046731 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3686 23:46:50.050254 ==
3687 23:46:50.050341 Dram Type= 6, Freq= 0, CH_1, rank 1
3688 23:46:50.056589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3689 23:46:50.056675 ==
3690 23:46:50.056756 DQS Delay:
3691 23:46:50.059850 DQS0 = 0, DQS1 = 0
3692 23:46:50.059936 DQM Delay:
3693 23:46:50.063635 DQM0 = 120, DQM1 = 116
3694 23:46:50.063739 DQ Delay:
3695 23:46:50.067073 DQ0 =124, DQ1 =116, DQ2 =110, DQ3 =116
3696 23:46:50.070487 DQ4 =114, DQ5 =132, DQ6 =130, DQ7 =118
3697 23:46:50.073699 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3698 23:46:50.077049 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =126
3699 23:46:50.077126
3700 23:46:50.077195
3701 23:46:50.086902 [DQSOSCAuto] RK1, (LSB)MR18= 0x14f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 402 ps
3702 23:46:50.089741 CH1 RK1: MR19=403, MR18=14F2
3703 23:46:50.093137 CH1_RK1: MR19=0x403, MR18=0x14F2, DQSOSC=402, MR23=63, INC=40, DEC=27
3704 23:46:50.096593 [RxdqsGatingPostProcess] freq 1200
3705 23:46:50.103138 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3706 23:46:50.106273 best DQS0 dly(2T, 0.5T) = (0, 11)
3707 23:46:50.109994 best DQS1 dly(2T, 0.5T) = (0, 11)
3708 23:46:50.113339 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3709 23:46:50.116833 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3710 23:46:50.119936 best DQS0 dly(2T, 0.5T) = (0, 11)
3711 23:46:50.123032 best DQS1 dly(2T, 0.5T) = (0, 11)
3712 23:46:50.127018 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3713 23:46:50.127096 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3714 23:46:50.130266 Pre-setting of DQS Precalculation
3715 23:46:50.136533 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3716 23:46:50.143099 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3717 23:46:50.150043 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3718 23:46:50.150131
3719 23:46:50.150200
3720 23:46:50.153343 [Calibration Summary] 2400 Mbps
3721 23:46:50.156806 CH 0, Rank 0
3722 23:46:50.156892 SW Impedance : PASS
3723 23:46:50.160114 DUTY Scan : NO K
3724 23:46:50.160199 ZQ Calibration : PASS
3725 23:46:50.163145 Jitter Meter : NO K
3726 23:46:50.166606 CBT Training : PASS
3727 23:46:50.166692 Write leveling : PASS
3728 23:46:50.169739 RX DQS gating : PASS
3729 23:46:50.173072 RX DQ/DQS(RDDQC) : PASS
3730 23:46:50.173188 TX DQ/DQS : PASS
3731 23:46:50.176460 RX DATLAT : PASS
3732 23:46:50.179758 RX DQ/DQS(Engine): PASS
3733 23:46:50.179882 TX OE : NO K
3734 23:46:50.183543 All Pass.
3735 23:46:50.183628
3736 23:46:50.183696 CH 0, Rank 1
3737 23:46:50.187064 SW Impedance : PASS
3738 23:46:50.187139 DUTY Scan : NO K
3739 23:46:50.190021 ZQ Calibration : PASS
3740 23:46:50.193306 Jitter Meter : NO K
3741 23:46:50.193391 CBT Training : PASS
3742 23:46:50.196501 Write leveling : PASS
3743 23:46:50.200192 RX DQS gating : PASS
3744 23:46:50.200278 RX DQ/DQS(RDDQC) : PASS
3745 23:46:50.203280 TX DQ/DQS : PASS
3746 23:46:50.203367 RX DATLAT : PASS
3747 23:46:50.206464 RX DQ/DQS(Engine): PASS
3748 23:46:50.209970 TX OE : NO K
3749 23:46:50.210055 All Pass.
3750 23:46:50.210125
3751 23:46:50.210193 CH 1, Rank 0
3752 23:46:50.213401 SW Impedance : PASS
3753 23:46:50.216685 DUTY Scan : NO K
3754 23:46:50.216767 ZQ Calibration : PASS
3755 23:46:50.220106 Jitter Meter : NO K
3756 23:46:50.223727 CBT Training : PASS
3757 23:46:50.223808 Write leveling : PASS
3758 23:46:50.226835 RX DQS gating : PASS
3759 23:46:50.230268 RX DQ/DQS(RDDQC) : PASS
3760 23:46:50.230355 TX DQ/DQS : PASS
3761 23:46:50.233368 RX DATLAT : PASS
3762 23:46:50.236464 RX DQ/DQS(Engine): PASS
3763 23:46:50.236568 TX OE : NO K
3764 23:46:50.236637 All Pass.
3765 23:46:50.240543
3766 23:46:50.240649 CH 1, Rank 1
3767 23:46:50.243091 SW Impedance : PASS
3768 23:46:50.243167 DUTY Scan : NO K
3769 23:46:50.246822 ZQ Calibration : PASS
3770 23:46:50.246899 Jitter Meter : NO K
3771 23:46:50.250238 CBT Training : PASS
3772 23:46:50.253245 Write leveling : PASS
3773 23:46:50.253359 RX DQS gating : PASS
3774 23:46:50.256405 RX DQ/DQS(RDDQC) : PASS
3775 23:46:50.260087 TX DQ/DQS : PASS
3776 23:46:50.260173 RX DATLAT : PASS
3777 23:46:50.263252 RX DQ/DQS(Engine): PASS
3778 23:46:50.266597 TX OE : NO K
3779 23:46:50.266707 All Pass.
3780 23:46:50.266812
3781 23:46:50.269873 DramC Write-DBI off
3782 23:46:50.269992 PER_BANK_REFRESH: Hybrid Mode
3783 23:46:50.273192 TX_TRACKING: ON
3784 23:46:50.279701 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3785 23:46:50.286239 [FAST_K] Save calibration result to emmc
3786 23:46:50.289988 dramc_set_vcore_voltage set vcore to 650000
3787 23:46:50.290073 Read voltage for 600, 5
3788 23:46:50.293163 Vio18 = 0
3789 23:46:50.293248 Vcore = 650000
3790 23:46:50.293326 Vdram = 0
3791 23:46:50.296380 Vddq = 0
3792 23:46:50.296463 Vmddr = 0
3793 23:46:50.299740 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3794 23:46:50.306293 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3795 23:46:50.310020 MEM_TYPE=3, freq_sel=19
3796 23:46:50.313119 sv_algorithm_assistance_LP4_1600
3797 23:46:50.316318 ============ PULL DRAM RESETB DOWN ============
3798 23:46:50.319523 ========== PULL DRAM RESETB DOWN end =========
3799 23:46:50.326743 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3800 23:46:50.326825 ===================================
3801 23:46:50.329642 LPDDR4 DRAM CONFIGURATION
3802 23:46:50.333126 ===================================
3803 23:46:50.336602 EX_ROW_EN[0] = 0x0
3804 23:46:50.336707 EX_ROW_EN[1] = 0x0
3805 23:46:50.339589 LP4Y_EN = 0x0
3806 23:46:50.339687 WORK_FSP = 0x0
3807 23:46:50.343084 WL = 0x2
3808 23:46:50.343219 RL = 0x2
3809 23:46:50.346868 BL = 0x2
3810 23:46:50.346987 RPST = 0x0
3811 23:46:50.349608 RD_PRE = 0x0
3812 23:46:50.353581 WR_PRE = 0x1
3813 23:46:50.353670 WR_PST = 0x0
3814 23:46:50.356685 DBI_WR = 0x0
3815 23:46:50.356777 DBI_RD = 0x0
3816 23:46:50.360016 OTF = 0x1
3817 23:46:50.363058 ===================================
3818 23:46:50.366279 ===================================
3819 23:46:50.366351 ANA top config
3820 23:46:50.369937 ===================================
3821 23:46:50.373067 DLL_ASYNC_EN = 0
3822 23:46:50.376720 ALL_SLAVE_EN = 1
3823 23:46:50.376804 NEW_RANK_MODE = 1
3824 23:46:50.379496 DLL_IDLE_MODE = 1
3825 23:46:50.383273 LP45_APHY_COMB_EN = 1
3826 23:46:50.386601 TX_ODT_DIS = 1
3827 23:46:50.386687 NEW_8X_MODE = 1
3828 23:46:50.389960 ===================================
3829 23:46:50.393099 ===================================
3830 23:46:50.396616 data_rate = 1200
3831 23:46:50.399647 CKR = 1
3832 23:46:50.402980 DQ_P2S_RATIO = 8
3833 23:46:50.406185 ===================================
3834 23:46:50.409527 CA_P2S_RATIO = 8
3835 23:46:50.413296 DQ_CA_OPEN = 0
3836 23:46:50.413384 DQ_SEMI_OPEN = 0
3837 23:46:50.416277 CA_SEMI_OPEN = 0
3838 23:46:50.419561 CA_FULL_RATE = 0
3839 23:46:50.422772 DQ_CKDIV4_EN = 1
3840 23:46:50.425900 CA_CKDIV4_EN = 1
3841 23:46:50.429223 CA_PREDIV_EN = 0
3842 23:46:50.429309 PH8_DLY = 0
3843 23:46:50.433160 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3844 23:46:50.436448 DQ_AAMCK_DIV = 4
3845 23:46:50.439502 CA_AAMCK_DIV = 4
3846 23:46:50.442513 CA_ADMCK_DIV = 4
3847 23:46:50.445948 DQ_TRACK_CA_EN = 0
3848 23:46:50.446031 CA_PICK = 600
3849 23:46:50.449399 CA_MCKIO = 600
3850 23:46:50.452570 MCKIO_SEMI = 0
3851 23:46:50.456314 PLL_FREQ = 2288
3852 23:46:50.459271 DQ_UI_PI_RATIO = 32
3853 23:46:50.462735 CA_UI_PI_RATIO = 0
3854 23:46:50.466094 ===================================
3855 23:46:50.469549 ===================================
3856 23:46:50.469629 memory_type:LPDDR4
3857 23:46:50.472637 GP_NUM : 10
3858 23:46:50.475751 SRAM_EN : 1
3859 23:46:50.475836 MD32_EN : 0
3860 23:46:50.479035 ===================================
3861 23:46:50.482804 [ANA_INIT] >>>>>>>>>>>>>>
3862 23:46:50.486165 <<<<<< [CONFIGURE PHASE]: ANA_TX
3863 23:46:50.489406 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3864 23:46:50.492735 ===================================
3865 23:46:50.495956 data_rate = 1200,PCW = 0X5800
3866 23:46:50.499000 ===================================
3867 23:46:50.502194 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3868 23:46:50.505506 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 23:46:50.512686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3870 23:46:50.515897 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3871 23:46:50.518922 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3872 23:46:50.525516 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3873 23:46:50.525598 [ANA_INIT] flow start
3874 23:46:50.528727 [ANA_INIT] PLL >>>>>>>>
3875 23:46:50.532041 [ANA_INIT] PLL <<<<<<<<
3876 23:46:50.532142 [ANA_INIT] MIDPI >>>>>>>>
3877 23:46:50.535597 [ANA_INIT] MIDPI <<<<<<<<
3878 23:46:50.538840 [ANA_INIT] DLL >>>>>>>>
3879 23:46:50.538948 [ANA_INIT] flow end
3880 23:46:50.542052 ============ LP4 DIFF to SE enter ============
3881 23:46:50.548527 ============ LP4 DIFF to SE exit ============
3882 23:46:50.548613 [ANA_INIT] <<<<<<<<<<<<<
3883 23:46:50.552165 [Flow] Enable top DCM control >>>>>
3884 23:46:50.555271 [Flow] Enable top DCM control <<<<<
3885 23:46:50.558914 Enable DLL master slave shuffle
3886 23:46:50.565384 ==============================================================
3887 23:46:50.568626 Gating Mode config
3888 23:46:50.572025 ==============================================================
3889 23:46:50.574912 Config description:
3890 23:46:50.584980 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3891 23:46:50.591715 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3892 23:46:50.595019 SELPH_MODE 0: By rank 1: By Phase
3893 23:46:50.601509 ==============================================================
3894 23:46:50.605184 GAT_TRACK_EN = 1
3895 23:46:50.608472 RX_GATING_MODE = 2
3896 23:46:50.611731 RX_GATING_TRACK_MODE = 2
3897 23:46:50.611841 SELPH_MODE = 1
3898 23:46:50.615303 PICG_EARLY_EN = 1
3899 23:46:50.618487 VALID_LAT_VALUE = 1
3900 23:46:50.624848 ==============================================================
3901 23:46:50.628504 Enter into Gating configuration >>>>
3902 23:46:50.631720 Exit from Gating configuration <<<<
3903 23:46:50.634992 Enter into DVFS_PRE_config >>>>>
3904 23:46:50.645124 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3905 23:46:50.648413 Exit from DVFS_PRE_config <<<<<
3906 23:46:50.651836 Enter into PICG configuration >>>>
3907 23:46:50.654926 Exit from PICG configuration <<<<
3908 23:46:50.658036 [RX_INPUT] configuration >>>>>
3909 23:46:50.661804 [RX_INPUT] configuration <<<<<
3910 23:46:50.664816 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3911 23:46:50.671638 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3912 23:46:50.678142 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3913 23:46:50.685081 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3914 23:46:50.688445 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3915 23:46:50.694790 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3916 23:46:50.698585 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3917 23:46:50.705002 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3918 23:46:50.707871 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3919 23:46:50.711196 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3920 23:46:50.715113 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3921 23:46:50.721673 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3922 23:46:50.724906 ===================================
3923 23:46:50.724992 LPDDR4 DRAM CONFIGURATION
3924 23:46:50.728260 ===================================
3925 23:46:50.731286 EX_ROW_EN[0] = 0x0
3926 23:46:50.734969 EX_ROW_EN[1] = 0x0
3927 23:46:50.735049 LP4Y_EN = 0x0
3928 23:46:50.738013 WORK_FSP = 0x0
3929 23:46:50.738096 WL = 0x2
3930 23:46:50.741200 RL = 0x2
3931 23:46:50.741286 BL = 0x2
3932 23:46:50.744421 RPST = 0x0
3933 23:46:50.744501 RD_PRE = 0x0
3934 23:46:50.747685 WR_PRE = 0x1
3935 23:46:50.747769 WR_PST = 0x0
3936 23:46:50.750950 DBI_WR = 0x0
3937 23:46:50.751025 DBI_RD = 0x0
3938 23:46:50.754400 OTF = 0x1
3939 23:46:50.758133 ===================================
3940 23:46:50.761354 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3941 23:46:50.764480 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3942 23:46:50.771536 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3943 23:46:50.774574 ===================================
3944 23:46:50.774665 LPDDR4 DRAM CONFIGURATION
3945 23:46:50.777613 ===================================
3946 23:46:50.781104 EX_ROW_EN[0] = 0x10
3947 23:46:50.784277 EX_ROW_EN[1] = 0x0
3948 23:46:50.784385 LP4Y_EN = 0x0
3949 23:46:50.787905 WORK_FSP = 0x0
3950 23:46:50.788016 WL = 0x2
3951 23:46:50.791104 RL = 0x2
3952 23:46:50.791185 BL = 0x2
3953 23:46:50.794378 RPST = 0x0
3954 23:46:50.794457 RD_PRE = 0x0
3955 23:46:50.797683 WR_PRE = 0x1
3956 23:46:50.797772 WR_PST = 0x0
3957 23:46:50.800949 DBI_WR = 0x0
3958 23:46:50.801034 DBI_RD = 0x0
3959 23:46:50.804148 OTF = 0x1
3960 23:46:50.807916 ===================================
3961 23:46:50.814518 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3962 23:46:50.817665 nWR fixed to 30
3963 23:46:50.817753 [ModeRegInit_LP4] CH0 RK0
3964 23:46:50.820794 [ModeRegInit_LP4] CH0 RK1
3965 23:46:50.824194 [ModeRegInit_LP4] CH1 RK0
3966 23:46:50.827742 [ModeRegInit_LP4] CH1 RK1
3967 23:46:50.827828 match AC timing 17
3968 23:46:50.831266 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3969 23:46:50.837792 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3970 23:46:50.841292 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3971 23:46:50.844485 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3972 23:46:50.850699 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3973 23:46:50.850827 ==
3974 23:46:50.854022 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 23:46:50.857569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 23:46:50.857651 ==
3977 23:46:50.863916 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3978 23:46:50.871089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3979 23:46:50.874272 [CA 0] Center 35 (5~66) winsize 62
3980 23:46:50.877555 [CA 1] Center 35 (5~66) winsize 62
3981 23:46:50.880732 [CA 2] Center 33 (3~64) winsize 62
3982 23:46:50.883865 [CA 3] Center 33 (2~64) winsize 63
3983 23:46:50.887552 [CA 4] Center 33 (2~64) winsize 63
3984 23:46:50.890710 [CA 5] Center 32 (2~63) winsize 62
3985 23:46:50.890843
3986 23:46:50.894041 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3987 23:46:50.894138
3988 23:46:50.897770 [CATrainingPosCal] consider 1 rank data
3989 23:46:50.900532 u2DelayCellTimex100 = 270/100 ps
3990 23:46:50.904308 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3991 23:46:50.907442 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3992 23:46:50.910694 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3993 23:46:50.913947 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3994 23:46:50.917432 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3995 23:46:50.920852 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3996 23:46:50.920939
3997 23:46:50.924277 CA PerBit enable=1, Macro0, CA PI delay=32
3998 23:46:50.924387
3999 23:46:50.927404 [CBTSetCACLKResult] CA Dly = 32
4000 23:46:50.930717 CS Dly: 4 (0~35)
4001 23:46:50.930813 ==
4002 23:46:50.933899 Dram Type= 6, Freq= 0, CH_0, rank 1
4003 23:46:50.937725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 23:46:50.937813 ==
4005 23:46:50.943901 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4006 23:46:50.950895 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4007 23:46:50.953789 [CA 0] Center 35 (5~66) winsize 62
4008 23:46:50.957229 [CA 1] Center 35 (5~66) winsize 62
4009 23:46:50.960684 [CA 2] Center 34 (3~65) winsize 63
4010 23:46:50.964216 [CA 3] Center 33 (2~65) winsize 64
4011 23:46:50.967490 [CA 4] Center 32 (2~63) winsize 62
4012 23:46:50.970475 [CA 5] Center 32 (2~63) winsize 62
4013 23:46:50.970568
4014 23:46:50.973757 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4015 23:46:50.973862
4016 23:46:50.977710 [CATrainingPosCal] consider 2 rank data
4017 23:46:50.980898 u2DelayCellTimex100 = 270/100 ps
4018 23:46:50.984174 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4019 23:46:50.987452 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4020 23:46:50.990884 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4021 23:46:50.994008 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
4022 23:46:50.997208 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4023 23:46:51.000705 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4024 23:46:51.000793
4025 23:46:51.007406 CA PerBit enable=1, Macro0, CA PI delay=32
4026 23:46:51.007495
4027 23:46:51.007581 [CBTSetCACLKResult] CA Dly = 32
4028 23:46:51.010428 CS Dly: 4 (0~35)
4029 23:46:51.010523
4030 23:46:51.014075 ----->DramcWriteLeveling(PI) begin...
4031 23:46:51.014163 ==
4032 23:46:51.017059 Dram Type= 6, Freq= 0, CH_0, rank 0
4033 23:46:51.020526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4034 23:46:51.020614 ==
4035 23:46:51.023614 Write leveling (Byte 0): 35 => 35
4036 23:46:51.026954 Write leveling (Byte 1): 31 => 31
4037 23:46:51.030925 DramcWriteLeveling(PI) end<-----
4038 23:46:51.031036
4039 23:46:51.031120 ==
4040 23:46:51.034132 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 23:46:51.037432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 23:46:51.037507 ==
4043 23:46:51.040638 [Gating] SW mode calibration
4044 23:46:51.047194 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4045 23:46:51.053661 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4046 23:46:51.057748 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 23:46:51.063632 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 23:46:51.067242 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 23:46:51.070327 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
4050 23:46:51.076983 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4051 23:46:51.080255 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 23:46:51.083935 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 23:46:51.090737 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 23:46:51.094015 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 23:46:51.097150 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 23:46:51.100308 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4057 23:46:51.106873 0 10 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
4058 23:46:51.110882 0 10 16 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
4059 23:46:51.113645 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 23:46:51.120497 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 23:46:51.123631 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 23:46:51.127362 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 23:46:51.133999 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 23:46:51.137116 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 23:46:51.140311 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 23:46:51.147252 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 23:46:51.150570 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4068 23:46:51.153774 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 23:46:51.160476 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 23:46:51.163486 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 23:46:51.166626 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 23:46:51.173789 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 23:46:51.177032 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 23:46:51.180126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 23:46:51.186689 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 23:46:51.190062 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 23:46:51.193206 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 23:46:51.200363 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 23:46:51.203533 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 23:46:51.206987 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 23:46:51.213390 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4082 23:46:51.213472 Total UI for P1: 0, mck2ui 16
4083 23:46:51.220063 best dqsien dly found for B0: ( 0, 13, 10)
4084 23:46:51.223439 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4085 23:46:51.226493 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4086 23:46:51.230261 Total UI for P1: 0, mck2ui 16
4087 23:46:51.233463 best dqsien dly found for B1: ( 0, 13, 16)
4088 23:46:51.236712 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4089 23:46:51.239842 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4090 23:46:51.239941
4091 23:46:51.243520 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4092 23:46:51.249707 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4093 23:46:51.249789 [Gating] SW calibration Done
4094 23:46:51.249855 ==
4095 23:46:51.253637 Dram Type= 6, Freq= 0, CH_0, rank 0
4096 23:46:51.260164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4097 23:46:51.260271 ==
4098 23:46:51.260368 RX Vref Scan: 0
4099 23:46:51.260432
4100 23:46:51.263433 RX Vref 0 -> 0, step: 1
4101 23:46:51.263504
4102 23:46:51.266665 RX Delay -230 -> 252, step: 16
4103 23:46:51.269899 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4104 23:46:51.273095 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4105 23:46:51.279634 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4106 23:46:51.282965 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4107 23:46:51.286237 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4108 23:46:51.289487 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4109 23:46:51.293377 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4110 23:46:51.299839 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4111 23:46:51.302731 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4112 23:46:51.306166 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4113 23:46:51.309583 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4114 23:46:51.316285 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4115 23:46:51.319594 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4116 23:46:51.323097 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4117 23:46:51.326569 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4118 23:46:51.329730 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4119 23:46:51.332884 ==
4120 23:46:51.335912 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 23:46:51.339168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 23:46:51.339281 ==
4123 23:46:51.339381 DQS Delay:
4124 23:46:51.342523 DQS0 = 0, DQS1 = 0
4125 23:46:51.342624 DQM Delay:
4126 23:46:51.345740 DQM0 = 52, DQM1 = 45
4127 23:46:51.345812 DQ Delay:
4128 23:46:51.349134 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4129 23:46:51.352569 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4130 23:46:51.356050 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4131 23:46:51.359483 DQ12 =49, DQ13 =49, DQ14 =65, DQ15 =49
4132 23:46:51.359568
4133 23:46:51.359633
4134 23:46:51.359698 ==
4135 23:46:51.362299 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 23:46:51.366143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 23:46:51.366224 ==
4138 23:46:51.366296
4139 23:46:51.366356
4140 23:46:51.369416 TX Vref Scan disable
4141 23:46:51.372487 == TX Byte 0 ==
4142 23:46:51.375623 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4143 23:46:51.379024 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4144 23:46:51.382946 == TX Byte 1 ==
4145 23:46:51.386144 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4146 23:46:51.388959 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4147 23:46:51.389062 ==
4148 23:46:51.392268 Dram Type= 6, Freq= 0, CH_0, rank 0
4149 23:46:51.398796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 23:46:51.398875 ==
4151 23:46:51.398939
4152 23:46:51.399004
4153 23:46:51.399064 TX Vref Scan disable
4154 23:46:51.403437 == TX Byte 0 ==
4155 23:46:51.406829 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4156 23:46:51.413403 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4157 23:46:51.413482 == TX Byte 1 ==
4158 23:46:51.416642 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4159 23:46:51.423585 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4160 23:46:51.423670
4161 23:46:51.423735 [DATLAT]
4162 23:46:51.423796 Freq=600, CH0 RK0
4163 23:46:51.423854
4164 23:46:51.426665 DATLAT Default: 0x9
4165 23:46:51.426735 0, 0xFFFF, sum = 0
4166 23:46:51.430152 1, 0xFFFF, sum = 0
4167 23:46:51.430229 2, 0xFFFF, sum = 0
4168 23:46:51.433540 3, 0xFFFF, sum = 0
4169 23:46:51.433613 4, 0xFFFF, sum = 0
4170 23:46:51.436769 5, 0xFFFF, sum = 0
4171 23:46:51.439909 6, 0xFFFF, sum = 0
4172 23:46:51.440011 7, 0xFFFF, sum = 0
4173 23:46:51.440104 8, 0x0, sum = 1
4174 23:46:51.443661 9, 0x0, sum = 2
4175 23:46:51.443739 10, 0x0, sum = 3
4176 23:46:51.447154 11, 0x0, sum = 4
4177 23:46:51.447232 best_step = 9
4178 23:46:51.447296
4179 23:46:51.447360 ==
4180 23:46:51.449813 Dram Type= 6, Freq= 0, CH_0, rank 0
4181 23:46:51.456401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4182 23:46:51.456477 ==
4183 23:46:51.456540 RX Vref Scan: 1
4184 23:46:51.456600
4185 23:46:51.459721 RX Vref 0 -> 0, step: 1
4186 23:46:51.459802
4187 23:46:51.463442 RX Delay -163 -> 252, step: 8
4188 23:46:51.463524
4189 23:46:51.466521 Set Vref, RX VrefLevel [Byte0]: 56
4190 23:46:51.469616 [Byte1]: 54
4191 23:46:51.469695
4192 23:46:51.473258 Final RX Vref Byte 0 = 56 to rank0
4193 23:46:51.476607 Final RX Vref Byte 1 = 54 to rank0
4194 23:46:51.479639 Final RX Vref Byte 0 = 56 to rank1
4195 23:46:51.482763 Final RX Vref Byte 1 = 54 to rank1==
4196 23:46:51.486453 Dram Type= 6, Freq= 0, CH_0, rank 0
4197 23:46:51.489645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4198 23:46:51.489726 ==
4199 23:46:51.492912 DQS Delay:
4200 23:46:51.492985 DQS0 = 0, DQS1 = 0
4201 23:46:51.496298 DQM Delay:
4202 23:46:51.496408 DQM0 = 53, DQM1 = 46
4203 23:46:51.496506 DQ Delay:
4204 23:46:51.499635 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52
4205 23:46:51.503159 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4206 23:46:51.506219 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =40
4207 23:46:51.509491 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4208 23:46:51.509597
4209 23:46:51.509688
4210 23:46:51.519249 [DQSOSCAuto] RK0, (LSB)MR18= 0x7266, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4211 23:46:51.522778 CH0 RK0: MR19=808, MR18=7266
4212 23:46:51.526014 CH0_RK0: MR19=0x808, MR18=0x7266, DQSOSC=388, MR23=63, INC=174, DEC=116
4213 23:46:51.529264
4214 23:46:51.532638 ----->DramcWriteLeveling(PI) begin...
4215 23:46:51.532717 ==
4216 23:46:51.536019 Dram Type= 6, Freq= 0, CH_0, rank 1
4217 23:46:51.539849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4218 23:46:51.539938 ==
4219 23:46:51.542996 Write leveling (Byte 0): 34 => 34
4220 23:46:51.546188 Write leveling (Byte 1): 31 => 31
4221 23:46:51.549408 DramcWriteLeveling(PI) end<-----
4222 23:46:51.549482
4223 23:46:51.549544 ==
4224 23:46:51.552638 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 23:46:51.556007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 23:46:51.556081 ==
4227 23:46:51.559196 [Gating] SW mode calibration
4228 23:46:51.566222 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4229 23:46:51.572720 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4230 23:46:51.575970 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 23:46:51.579687 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 23:46:51.582776 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4233 23:46:51.589356 0 9 12 | B1->B0 | 3333 3434 | 0 0 | (0 1) (0 0)
4234 23:46:51.592881 0 9 16 | B1->B0 | 2c2c 2525 | 0 0 | (0 0) (0 0)
4235 23:46:51.596041 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 23:46:51.603018 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 23:46:51.606374 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 23:46:51.609789 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 23:46:51.616391 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 23:46:51.619613 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4241 23:46:51.622786 0 10 12 | B1->B0 | 2a2a 2626 | 0 0 | (0 0) (0 0)
4242 23:46:51.629367 0 10 16 | B1->B0 | 4141 3f3f | 0 0 | (0 0) (1 1)
4243 23:46:51.632505 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 23:46:51.636499 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 23:46:51.643010 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 23:46:51.646332 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 23:46:51.649545 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 23:46:51.656301 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 23:46:51.659747 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4250 23:46:51.662965 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:46:51.669482 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:46:51.672810 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:46:51.675981 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:46:51.682828 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 23:46:51.686143 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 23:46:51.689241 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 23:46:51.695839 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 23:46:51.699142 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 23:46:51.702426 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 23:46:51.709065 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 23:46:51.712415 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 23:46:51.715585 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 23:46:51.719223 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 23:46:51.725806 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 23:46:51.729134 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4266 23:46:51.732773 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4267 23:46:51.736029 Total UI for P1: 0, mck2ui 16
4268 23:46:51.739477 best dqsien dly found for B0: ( 0, 13, 14)
4269 23:46:51.742774 Total UI for P1: 0, mck2ui 16
4270 23:46:51.746096 best dqsien dly found for B1: ( 0, 13, 12)
4271 23:46:51.749224 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4272 23:46:51.752393 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4273 23:46:51.755690
4274 23:46:51.758930 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4275 23:46:51.762256 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4276 23:46:51.765638 [Gating] SW calibration Done
4277 23:46:51.765715 ==
4278 23:46:51.769021 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 23:46:51.772426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 23:46:51.772509 ==
4281 23:46:51.772575 RX Vref Scan: 0
4282 23:46:51.772635
4283 23:46:51.775770 RX Vref 0 -> 0, step: 1
4284 23:46:51.775844
4285 23:46:51.778990 RX Delay -230 -> 252, step: 16
4286 23:46:51.782746 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4287 23:46:51.788931 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4288 23:46:51.792240 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4289 23:46:51.795529 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4290 23:46:51.798762 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4291 23:46:51.802272 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4292 23:46:51.808748 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4293 23:46:51.812061 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4294 23:46:51.815376 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4295 23:46:51.818686 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4296 23:46:51.825261 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4297 23:46:51.828557 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4298 23:46:51.831921 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4299 23:46:51.835762 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4300 23:46:51.842196 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4301 23:46:51.845775 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4302 23:46:51.845851 ==
4303 23:46:51.848632 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 23:46:51.851825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 23:46:51.851906 ==
4306 23:46:51.855037 DQS Delay:
4307 23:46:51.855111 DQS0 = 0, DQS1 = 0
4308 23:46:51.855181 DQM Delay:
4309 23:46:51.858421 DQM0 = 51, DQM1 = 41
4310 23:46:51.858527 DQ Delay:
4311 23:46:51.861999 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4312 23:46:51.865273 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4313 23:46:51.868497 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4314 23:46:51.871849 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4315 23:46:51.871960
4316 23:46:51.872054
4317 23:46:51.872148 ==
4318 23:46:51.875394 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 23:46:51.878416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 23:46:51.881963 ==
4321 23:46:51.882062
4322 23:46:51.882160
4323 23:46:51.882250 TX Vref Scan disable
4324 23:46:51.885151 == TX Byte 0 ==
4325 23:46:51.888495 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4326 23:46:51.891758 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4327 23:46:51.895012 == TX Byte 1 ==
4328 23:46:51.899122 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4329 23:46:51.902118 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4330 23:46:51.905559 ==
4331 23:46:51.908787 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 23:46:51.912128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 23:46:51.912217 ==
4334 23:46:51.912325
4335 23:46:51.912414
4336 23:46:51.915410 TX Vref Scan disable
4337 23:46:51.915491 == TX Byte 0 ==
4338 23:46:51.921753 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4339 23:46:51.925037 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4340 23:46:51.925119 == TX Byte 1 ==
4341 23:46:51.932164 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4342 23:46:51.935469 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4343 23:46:51.935549
4344 23:46:51.935634 [DATLAT]
4345 23:46:51.938676 Freq=600, CH0 RK1
4346 23:46:51.938754
4347 23:46:51.938841 DATLAT Default: 0x9
4348 23:46:51.942012 0, 0xFFFF, sum = 0
4349 23:46:51.942095 1, 0xFFFF, sum = 0
4350 23:46:51.945528 2, 0xFFFF, sum = 0
4351 23:46:51.945609 3, 0xFFFF, sum = 0
4352 23:46:51.949031 4, 0xFFFF, sum = 0
4353 23:46:51.949122 5, 0xFFFF, sum = 0
4354 23:46:51.952600 6, 0xFFFF, sum = 0
4355 23:46:51.952679 7, 0xFFFF, sum = 0
4356 23:46:51.955516 8, 0x0, sum = 1
4357 23:46:51.955613 9, 0x0, sum = 2
4358 23:46:51.958740 10, 0x0, sum = 3
4359 23:46:51.958854 11, 0x0, sum = 4
4360 23:46:51.962055 best_step = 9
4361 23:46:51.962165
4362 23:46:51.962259 ==
4363 23:46:51.965638 Dram Type= 6, Freq= 0, CH_0, rank 1
4364 23:46:51.968538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 23:46:51.968626 ==
4366 23:46:51.972042 RX Vref Scan: 0
4367 23:46:51.972151
4368 23:46:51.972254 RX Vref 0 -> 0, step: 1
4369 23:46:51.972359
4370 23:46:51.975109 RX Delay -179 -> 252, step: 8
4371 23:46:51.982285 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4372 23:46:51.985706 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4373 23:46:51.989019 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4374 23:46:51.992286 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4375 23:46:51.995444 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4376 23:46:52.002174 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4377 23:46:52.005276 iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280
4378 23:46:52.008840 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4379 23:46:52.012299 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4380 23:46:52.015452 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4381 23:46:52.021959 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4382 23:46:52.025651 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4383 23:46:52.028795 iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288
4384 23:46:52.031950 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4385 23:46:52.038365 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4386 23:46:52.042263 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4387 23:46:52.042345 ==
4388 23:46:52.045587 Dram Type= 6, Freq= 0, CH_0, rank 1
4389 23:46:52.048885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 23:46:52.048961 ==
4391 23:46:52.052070 DQS Delay:
4392 23:46:52.052173 DQS0 = 0, DQS1 = 0
4393 23:46:52.052264 DQM Delay:
4394 23:46:52.055628 DQM0 = 53, DQM1 = 46
4395 23:46:52.055728 DQ Delay:
4396 23:46:52.058556 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4397 23:46:52.061767 DQ4 =56, DQ5 =44, DQ6 =56, DQ7 =60
4398 23:46:52.064974 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4399 23:46:52.068900 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4400 23:46:52.068977
4401 23:46:52.069040
4402 23:46:52.078801 [DQSOSCAuto] RK1, (LSB)MR18= 0x6828, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4403 23:46:52.078889 CH0 RK1: MR19=808, MR18=6828
4404 23:46:52.085432 CH0_RK1: MR19=0x808, MR18=0x6828, DQSOSC=390, MR23=63, INC=172, DEC=114
4405 23:46:52.088447 [RxdqsGatingPostProcess] freq 600
4406 23:46:52.095239 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4407 23:46:52.098595 Pre-setting of DQS Precalculation
4408 23:46:52.102504 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4409 23:46:52.102586 ==
4410 23:46:52.105567 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 23:46:52.108714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 23:46:52.112052 ==
4413 23:46:52.115361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4414 23:46:52.121724 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4415 23:46:52.125105 [CA 0] Center 36 (5~67) winsize 63
4416 23:46:52.128903 [CA 1] Center 36 (5~67) winsize 63
4417 23:46:52.131995 [CA 2] Center 34 (4~65) winsize 62
4418 23:46:52.135303 [CA 3] Center 34 (4~65) winsize 62
4419 23:46:52.138639 [CA 4] Center 34 (4~65) winsize 62
4420 23:46:52.141896 [CA 5] Center 33 (3~64) winsize 62
4421 23:46:52.141972
4422 23:46:52.144753 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4423 23:46:52.144831
4424 23:46:52.148677 [CATrainingPosCal] consider 1 rank data
4425 23:46:52.152087 u2DelayCellTimex100 = 270/100 ps
4426 23:46:52.155231 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4427 23:46:52.158401 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4428 23:46:52.161644 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4429 23:46:52.168017 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 23:46:52.171874 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4431 23:46:52.175200 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 23:46:52.175276
4433 23:46:52.178526 CA PerBit enable=1, Macro0, CA PI delay=33
4434 23:46:52.178604
4435 23:46:52.181719 [CBTSetCACLKResult] CA Dly = 33
4436 23:46:52.181792 CS Dly: 6 (0~37)
4437 23:46:52.181853 ==
4438 23:46:52.185069 Dram Type= 6, Freq= 0, CH_1, rank 1
4439 23:46:52.191977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 23:46:52.192063 ==
4441 23:46:52.195122 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4442 23:46:52.201451 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4443 23:46:52.205161 [CA 0] Center 36 (5~67) winsize 63
4444 23:46:52.208121 [CA 1] Center 36 (5~67) winsize 63
4445 23:46:52.211964 [CA 2] Center 34 (4~65) winsize 62
4446 23:46:52.215197 [CA 3] Center 34 (4~65) winsize 62
4447 23:46:52.218288 [CA 4] Center 35 (4~66) winsize 63
4448 23:46:52.221671 [CA 5] Center 34 (3~65) winsize 63
4449 23:46:52.221774
4450 23:46:52.224792 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4451 23:46:52.224896
4452 23:46:52.228635 [CATrainingPosCal] consider 2 rank data
4453 23:46:52.231800 u2DelayCellTimex100 = 270/100 ps
4454 23:46:52.235041 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4455 23:46:52.238388 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4456 23:46:52.241692 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4457 23:46:52.248534 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4458 23:46:52.251822 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4459 23:46:52.255220 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4460 23:46:52.255297
4461 23:46:52.258168 CA PerBit enable=1, Macro0, CA PI delay=33
4462 23:46:52.258286
4463 23:46:52.261480 [CBTSetCACLKResult] CA Dly = 33
4464 23:46:52.261566 CS Dly: 6 (0~37)
4465 23:46:52.261658
4466 23:46:52.265043 ----->DramcWriteLeveling(PI) begin...
4467 23:46:52.265129 ==
4468 23:46:52.268388 Dram Type= 6, Freq= 0, CH_1, rank 0
4469 23:46:52.274801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 23:46:52.274891 ==
4471 23:46:52.278072 Write leveling (Byte 0): 29 => 29
4472 23:46:52.281374 Write leveling (Byte 1): 29 => 29
4473 23:46:52.284666 DramcWriteLeveling(PI) end<-----
4474 23:46:52.284747
4475 23:46:52.284834 ==
4476 23:46:52.288008 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 23:46:52.291356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 23:46:52.291439 ==
4479 23:46:52.294668 [Gating] SW mode calibration
4480 23:46:52.301699 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4481 23:46:52.304863 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4482 23:46:52.311086 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4483 23:46:52.314404 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4484 23:46:52.318428 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4485 23:46:52.324904 0 9 12 | B1->B0 | 2e2e 2e2e | 0 0 | (0 0) (0 0)
4486 23:46:52.328004 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 23:46:52.331116 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 23:46:52.338004 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 23:46:52.341143 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 23:46:52.344622 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 23:46:52.351187 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 23:46:52.354510 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 23:46:52.357615 0 10 12 | B1->B0 | 3535 3b3b | 0 0 | (0 0) (0 0)
4494 23:46:52.364511 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 23:46:52.367816 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 23:46:52.371265 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 23:46:52.377877 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 23:46:52.381019 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 23:46:52.384300 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 23:46:52.390845 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4501 23:46:52.394087 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4502 23:46:52.397448 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 23:46:52.403954 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 23:46:52.407188 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 23:46:52.410888 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 23:46:52.417645 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 23:46:52.420972 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 23:46:52.424343 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 23:46:52.431011 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 23:46:52.434203 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 23:46:52.437615 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 23:46:52.443818 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 23:46:52.447271 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 23:46:52.450700 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 23:46:52.457494 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 23:46:52.460569 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 23:46:52.463695 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 23:46:52.467050 Total UI for P1: 0, mck2ui 16
4519 23:46:52.470338 best dqsien dly found for B0: ( 0, 13, 10)
4520 23:46:52.473941 Total UI for P1: 0, mck2ui 16
4521 23:46:52.477483 best dqsien dly found for B1: ( 0, 13, 10)
4522 23:46:52.480803 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4523 23:46:52.483898 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4524 23:46:52.484049
4525 23:46:52.487337 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4526 23:46:52.493990 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4527 23:46:52.494133 [Gating] SW calibration Done
4528 23:46:52.494203 ==
4529 23:46:52.496785 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 23:46:52.503421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 23:46:52.503518 ==
4532 23:46:52.503586 RX Vref Scan: 0
4533 23:46:52.503649
4534 23:46:52.506793 RX Vref 0 -> 0, step: 1
4535 23:46:52.506879
4536 23:46:52.510274 RX Delay -230 -> 252, step: 16
4537 23:46:52.513431 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4538 23:46:52.516723 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4539 23:46:52.523468 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4540 23:46:52.526940 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4541 23:46:52.530178 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4542 23:46:52.533442 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4543 23:46:52.536737 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4544 23:46:52.543843 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4545 23:46:52.547142 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4546 23:46:52.550324 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4547 23:46:52.553597 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4548 23:46:52.559965 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4549 23:46:52.563540 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4550 23:46:52.566938 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4551 23:46:52.570378 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4552 23:46:52.576734 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4553 23:46:52.576905 ==
4554 23:46:52.580092 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 23:46:52.583565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 23:46:52.583657 ==
4557 23:46:52.583734 DQS Delay:
4558 23:46:52.586653 DQS0 = 0, DQS1 = 0
4559 23:46:52.586767 DQM Delay:
4560 23:46:52.589959 DQM0 = 51, DQM1 = 48
4561 23:46:52.590071 DQ Delay:
4562 23:46:52.593280 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4563 23:46:52.596688 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4564 23:46:52.600411 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4565 23:46:52.603593 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4566 23:46:52.603724
4567 23:46:52.603835
4568 23:46:52.603951 ==
4569 23:46:52.606988 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 23:46:52.609771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 23:46:52.609865 ==
4572 23:46:52.609935
4573 23:46:52.609999
4574 23:46:52.613182 TX Vref Scan disable
4575 23:46:52.616613 == TX Byte 0 ==
4576 23:46:52.620432 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4577 23:46:52.623567 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4578 23:46:52.627066 == TX Byte 1 ==
4579 23:46:52.629951 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4580 23:46:52.633415 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4581 23:46:52.633508 ==
4582 23:46:52.636522 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 23:46:52.643160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 23:46:52.643252 ==
4585 23:46:52.643345
4586 23:46:52.643434
4587 23:46:52.643514 TX Vref Scan disable
4588 23:46:52.647102 == TX Byte 0 ==
4589 23:46:52.650976 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4590 23:46:52.654412 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4591 23:46:52.657107 == TX Byte 1 ==
4592 23:46:52.666587 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4593 23:46:52.667093 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4594 23:46:52.667211
4595 23:46:52.667308 [DATLAT]
4596 23:46:52.667400 Freq=600, CH1 RK0
4597 23:46:52.667491
4598 23:46:52.670388 DATLAT Default: 0x9
4599 23:46:52.670492 0, 0xFFFF, sum = 0
4600 23:46:52.674419 1, 0xFFFF, sum = 0
4601 23:46:52.674538 2, 0xFFFF, sum = 0
4602 23:46:52.677568 3, 0xFFFF, sum = 0
4603 23:46:52.677677 4, 0xFFFF, sum = 0
4604 23:46:52.680596 5, 0xFFFF, sum = 0
4605 23:46:52.684197 6, 0xFFFF, sum = 0
4606 23:46:52.684309 7, 0xFFFF, sum = 0
4607 23:46:52.684408 8, 0x0, sum = 1
4608 23:46:52.687245 9, 0x0, sum = 2
4609 23:46:52.687353 10, 0x0, sum = 3
4610 23:46:52.690252 11, 0x0, sum = 4
4611 23:46:52.690363 best_step = 9
4612 23:46:52.690459
4613 23:46:52.690554 ==
4614 23:46:52.693745 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 23:46:52.700780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 23:46:52.700906 ==
4617 23:46:52.701005 RX Vref Scan: 1
4618 23:46:52.701104
4619 23:46:52.704064 RX Vref 0 -> 0, step: 1
4620 23:46:52.704168
4621 23:46:52.707480 RX Delay -163 -> 252, step: 8
4622 23:46:52.707588
4623 23:46:52.710375 Set Vref, RX VrefLevel [Byte0]: 50
4624 23:46:52.714042 [Byte1]: 48
4625 23:46:52.714153
4626 23:46:52.717334 Final RX Vref Byte 0 = 50 to rank0
4627 23:46:52.720493 Final RX Vref Byte 1 = 48 to rank0
4628 23:46:52.723911 Final RX Vref Byte 0 = 50 to rank1
4629 23:46:52.727259 Final RX Vref Byte 1 = 48 to rank1==
4630 23:46:52.729994 Dram Type= 6, Freq= 0, CH_1, rank 0
4631 23:46:52.733900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 23:46:52.734018 ==
4633 23:46:52.737038 DQS Delay:
4634 23:46:52.737152 DQS0 = 0, DQS1 = 0
4635 23:46:52.737258 DQM Delay:
4636 23:46:52.740072 DQM0 = 48, DQM1 = 45
4637 23:46:52.740192 DQ Delay:
4638 23:46:52.743675 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4639 23:46:52.746904 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4640 23:46:52.750104 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4641 23:46:52.753420 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4642 23:46:52.753534
4643 23:46:52.753630
4644 23:46:52.764022 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c72, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4645 23:46:52.766787 CH1 RK0: MR19=808, MR18=4C72
4646 23:46:52.770599 CH1_RK0: MR19=0x808, MR18=0x4C72, DQSOSC=388, MR23=63, INC=174, DEC=116
4647 23:46:52.770745
4648 23:46:52.773290 ----->DramcWriteLeveling(PI) begin...
4649 23:46:52.777193 ==
4650 23:46:52.780487 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 23:46:52.783494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 23:46:52.783626 ==
4653 23:46:52.786713 Write leveling (Byte 0): 29 => 29
4654 23:46:52.790000 Write leveling (Byte 1): 32 => 32
4655 23:46:52.793258 DramcWriteLeveling(PI) end<-----
4656 23:46:52.793371
4657 23:46:52.793468 ==
4658 23:46:52.797123 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 23:46:52.800281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 23:46:52.800445 ==
4661 23:46:52.803790 [Gating] SW mode calibration
4662 23:46:52.810535 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4663 23:46:52.813292 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4664 23:46:52.820212 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4665 23:46:52.823326 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4666 23:46:52.826682 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 23:46:52.833102 0 9 12 | B1->B0 | 2e2e 2e2e | 0 0 | (1 1) (0 0)
4668 23:46:52.836567 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4669 23:46:52.839961 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 23:46:52.846444 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 23:46:52.850007 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 23:46:52.853015 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 23:46:52.860010 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 23:46:52.863379 0 10 8 | B1->B0 | 2424 2626 | 0 0 | (0 0) (0 0)
4675 23:46:52.866672 0 10 12 | B1->B0 | 4242 3535 | 0 1 | (0 0) (0 0)
4676 23:46:52.873288 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 23:46:52.876661 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 23:46:52.880033 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 23:46:52.886727 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 23:46:52.889990 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 23:46:52.893066 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 23:46:52.900081 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 23:46:52.903594 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 23:46:52.906647 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 23:46:52.913068 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 23:46:52.916894 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 23:46:52.919572 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 23:46:52.926236 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 23:46:52.929873 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 23:46:52.933258 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 23:46:52.939819 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 23:46:52.943101 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 23:46:52.946137 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 23:46:52.952995 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 23:46:52.956385 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 23:46:52.959398 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 23:46:52.963095 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 23:46:52.969450 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 23:46:52.973143 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4700 23:46:52.976611 Total UI for P1: 0, mck2ui 16
4701 23:46:52.979698 best dqsien dly found for B0: ( 0, 13, 10)
4702 23:46:52.983063 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 23:46:52.985729 Total UI for P1: 0, mck2ui 16
4704 23:46:52.989633 best dqsien dly found for B1: ( 0, 13, 12)
4705 23:46:52.992741 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4706 23:46:52.999244 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4707 23:46:52.999352
4708 23:46:53.002418 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4709 23:46:53.005713 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4710 23:46:53.008994 [Gating] SW calibration Done
4711 23:46:53.009098 ==
4712 23:46:53.012298 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 23:46:53.016113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 23:46:53.016220 ==
4715 23:46:53.019302 RX Vref Scan: 0
4716 23:46:53.019391
4717 23:46:53.019482 RX Vref 0 -> 0, step: 1
4718 23:46:53.019570
4719 23:46:53.022619 RX Delay -230 -> 252, step: 16
4720 23:46:53.025894 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4721 23:46:53.032938 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4722 23:46:53.036179 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4723 23:46:53.038982 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4724 23:46:53.042719 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4725 23:46:53.046042 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4726 23:46:53.052597 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4727 23:46:53.055902 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4728 23:46:53.059153 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4729 23:46:53.062505 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4730 23:46:53.065690 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4731 23:46:53.072815 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4732 23:46:53.075695 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4733 23:46:53.079225 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4734 23:46:53.082238 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4735 23:46:53.089187 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4736 23:46:53.089273 ==
4737 23:46:53.092753 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 23:46:53.096051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 23:46:53.096189 ==
4740 23:46:53.096284 DQS Delay:
4741 23:46:53.099281 DQS0 = 0, DQS1 = 0
4742 23:46:53.099360 DQM Delay:
4743 23:46:53.102428 DQM0 = 52, DQM1 = 48
4744 23:46:53.102539 DQ Delay:
4745 23:46:53.105842 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4746 23:46:53.109034 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4747 23:46:53.112422 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4748 23:46:53.115921 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =65
4749 23:46:53.116030
4750 23:46:53.116124
4751 23:46:53.116213 ==
4752 23:46:53.119066 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 23:46:53.122566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 23:46:53.122646 ==
4755 23:46:53.125670
4756 23:46:53.125746
4757 23:46:53.125812 TX Vref Scan disable
4758 23:46:53.129211 == TX Byte 0 ==
4759 23:46:53.132249 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4760 23:46:53.136102 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4761 23:46:53.139629 == TX Byte 1 ==
4762 23:46:53.142403 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4763 23:46:53.145848 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4764 23:46:53.145955 ==
4765 23:46:53.148856 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 23:46:53.155567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 23:46:53.155648 ==
4768 23:46:53.155715
4769 23:46:53.155776
4770 23:46:53.155836 TX Vref Scan disable
4771 23:46:53.160052 == TX Byte 0 ==
4772 23:46:53.163690 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4773 23:46:53.167161 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4774 23:46:53.170218 == TX Byte 1 ==
4775 23:46:53.173586 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4776 23:46:53.177365 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4777 23:46:53.180190
4778 23:46:53.180294 [DATLAT]
4779 23:46:53.180406 Freq=600, CH1 RK1
4780 23:46:53.180498
4781 23:46:53.184005 DATLAT Default: 0x9
4782 23:46:53.184113 0, 0xFFFF, sum = 0
4783 23:46:53.187039 1, 0xFFFF, sum = 0
4784 23:46:53.187119 2, 0xFFFF, sum = 0
4785 23:46:53.190526 3, 0xFFFF, sum = 0
4786 23:46:53.190604 4, 0xFFFF, sum = 0
4787 23:46:53.194243 5, 0xFFFF, sum = 0
4788 23:46:53.194349 6, 0xFFFF, sum = 0
4789 23:46:53.197123 7, 0xFFFF, sum = 0
4790 23:46:53.197236 8, 0x0, sum = 1
4791 23:46:53.200061 9, 0x0, sum = 2
4792 23:46:53.200169 10, 0x0, sum = 3
4793 23:46:53.203725 11, 0x0, sum = 4
4794 23:46:53.203832 best_step = 9
4795 23:46:53.203924
4796 23:46:53.204016 ==
4797 23:46:53.206969 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 23:46:53.213728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 23:46:53.213835 ==
4800 23:46:53.213930 RX Vref Scan: 0
4801 23:46:53.214020
4802 23:46:53.217105 RX Vref 0 -> 0, step: 1
4803 23:46:53.217211
4804 23:46:53.219946 RX Delay -163 -> 252, step: 8
4805 23:46:53.223736 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4806 23:46:53.230112 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4807 23:46:53.233424 iDelay=205, Bit 2, Center 40 (-99 ~ 180) 280
4808 23:46:53.236839 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4809 23:46:53.240011 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4810 23:46:53.243274 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4811 23:46:53.249946 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4812 23:46:53.253272 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4813 23:46:53.256581 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4814 23:46:53.259872 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4815 23:46:53.263674 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4816 23:46:53.270414 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4817 23:46:53.273447 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4818 23:46:53.276921 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4819 23:46:53.280239 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4820 23:46:53.283562 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4821 23:46:53.286880 ==
4822 23:46:53.286984 Dram Type= 6, Freq= 0, CH_1, rank 1
4823 23:46:53.293377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4824 23:46:53.293480 ==
4825 23:46:53.293575 DQS Delay:
4826 23:46:53.296745 DQS0 = 0, DQS1 = 0
4827 23:46:53.296846 DQM Delay:
4828 23:46:53.299814 DQM0 = 49, DQM1 = 44
4829 23:46:53.299918 DQ Delay:
4830 23:46:53.303131 DQ0 =52, DQ1 =44, DQ2 =40, DQ3 =44
4831 23:46:53.306367 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =44
4832 23:46:53.309896 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4833 23:46:53.312942 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =52
4834 23:46:53.313047
4835 23:46:53.313146
4836 23:46:53.319701 [DQSOSCAuto] RK1, (LSB)MR18= 0x681e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4837 23:46:53.323389 CH1 RK1: MR19=808, MR18=681E
4838 23:46:53.330194 CH1_RK1: MR19=0x808, MR18=0x681E, DQSOSC=390, MR23=63, INC=172, DEC=114
4839 23:46:53.333284 [RxdqsGatingPostProcess] freq 600
4840 23:46:53.339719 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4841 23:46:53.339805 Pre-setting of DQS Precalculation
4842 23:46:53.346656 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4843 23:46:53.353780 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4844 23:46:53.360211 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4845 23:46:53.360321
4846 23:46:53.360406
4847 23:46:53.363369 [Calibration Summary] 1200 Mbps
4848 23:46:53.363443 CH 0, Rank 0
4849 23:46:53.366653 SW Impedance : PASS
4850 23:46:53.370014 DUTY Scan : NO K
4851 23:46:53.370091 ZQ Calibration : PASS
4852 23:46:53.373398 Jitter Meter : NO K
4853 23:46:53.376558 CBT Training : PASS
4854 23:46:53.376648 Write leveling : PASS
4855 23:46:53.379765 RX DQS gating : PASS
4856 23:46:53.383010 RX DQ/DQS(RDDQC) : PASS
4857 23:46:53.383114 TX DQ/DQS : PASS
4858 23:46:53.386500 RX DATLAT : PASS
4859 23:46:53.390050 RX DQ/DQS(Engine): PASS
4860 23:46:53.390132 TX OE : NO K
4861 23:46:53.393558 All Pass.
4862 23:46:53.393644
4863 23:46:53.393708 CH 0, Rank 1
4864 23:46:53.396643 SW Impedance : PASS
4865 23:46:53.396724 DUTY Scan : NO K
4866 23:46:53.400118 ZQ Calibration : PASS
4867 23:46:53.403066 Jitter Meter : NO K
4868 23:46:53.403150 CBT Training : PASS
4869 23:46:53.406286 Write leveling : PASS
4870 23:46:53.409643 RX DQS gating : PASS
4871 23:46:53.409725 RX DQ/DQS(RDDQC) : PASS
4872 23:46:53.413022 TX DQ/DQS : PASS
4873 23:46:53.413098 RX DATLAT : PASS
4874 23:46:53.416188 RX DQ/DQS(Engine): PASS
4875 23:46:53.419316 TX OE : NO K
4876 23:46:53.419397 All Pass.
4877 23:46:53.419460
4878 23:46:53.419521 CH 1, Rank 0
4879 23:46:53.423165 SW Impedance : PASS
4880 23:46:53.426420 DUTY Scan : NO K
4881 23:46:53.426498 ZQ Calibration : PASS
4882 23:46:53.429423 Jitter Meter : NO K
4883 23:46:53.432698 CBT Training : PASS
4884 23:46:53.432778 Write leveling : PASS
4885 23:46:53.436188 RX DQS gating : PASS
4886 23:46:53.439398 RX DQ/DQS(RDDQC) : PASS
4887 23:46:53.439475 TX DQ/DQS : PASS
4888 23:46:53.442610 RX DATLAT : PASS
4889 23:46:53.446499 RX DQ/DQS(Engine): PASS
4890 23:46:53.446600 TX OE : NO K
4891 23:46:53.449383 All Pass.
4892 23:46:53.449456
4893 23:46:53.449521 CH 1, Rank 1
4894 23:46:53.453165 SW Impedance : PASS
4895 23:46:53.453238 DUTY Scan : NO K
4896 23:46:53.456095 ZQ Calibration : PASS
4897 23:46:53.459419 Jitter Meter : NO K
4898 23:46:53.459494 CBT Training : PASS
4899 23:46:53.462675 Write leveling : PASS
4900 23:46:53.462758 RX DQS gating : PASS
4901 23:46:53.465822 RX DQ/DQS(RDDQC) : PASS
4902 23:46:53.469772 TX DQ/DQS : PASS
4903 23:46:53.469854 RX DATLAT : PASS
4904 23:46:53.472602 RX DQ/DQS(Engine): PASS
4905 23:46:53.476482 TX OE : NO K
4906 23:46:53.476589 All Pass.
4907 23:46:53.476688
4908 23:46:53.479674 DramC Write-DBI off
4909 23:46:53.479751 PER_BANK_REFRESH: Hybrid Mode
4910 23:46:53.483053 TX_TRACKING: ON
4911 23:46:53.489693 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4912 23:46:53.495732 [FAST_K] Save calibration result to emmc
4913 23:46:53.499373 dramc_set_vcore_voltage set vcore to 662500
4914 23:46:53.499455 Read voltage for 933, 3
4915 23:46:53.503047 Vio18 = 0
4916 23:46:53.503128 Vcore = 662500
4917 23:46:53.503195 Vdram = 0
4918 23:46:53.506432 Vddq = 0
4919 23:46:53.506509 Vmddr = 0
4920 23:46:53.509225 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4921 23:46:53.515786 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4922 23:46:53.519005 MEM_TYPE=3, freq_sel=17
4923 23:46:53.522387 sv_algorithm_assistance_LP4_1600
4924 23:46:53.525760 ============ PULL DRAM RESETB DOWN ============
4925 23:46:53.528994 ========== PULL DRAM RESETB DOWN end =========
4926 23:46:53.535939 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4927 23:46:53.539215 ===================================
4928 23:46:53.539294 LPDDR4 DRAM CONFIGURATION
4929 23:46:53.542566 ===================================
4930 23:46:53.545967 EX_ROW_EN[0] = 0x0
4931 23:46:53.546044 EX_ROW_EN[1] = 0x0
4932 23:46:53.549144 LP4Y_EN = 0x0
4933 23:46:53.549219 WORK_FSP = 0x0
4934 23:46:53.552416 WL = 0x3
4935 23:46:53.555686 RL = 0x3
4936 23:46:53.555761 BL = 0x2
4937 23:46:53.559015 RPST = 0x0
4938 23:46:53.559092 RD_PRE = 0x0
4939 23:46:53.562374 WR_PRE = 0x1
4940 23:46:53.562447 WR_PST = 0x0
4941 23:46:53.565450 DBI_WR = 0x0
4942 23:46:53.565530 DBI_RD = 0x0
4943 23:46:53.568974 OTF = 0x1
4944 23:46:53.572572 ===================================
4945 23:46:53.575365 ===================================
4946 23:46:53.575449 ANA top config
4947 23:46:53.578979 ===================================
4948 23:46:53.582320 DLL_ASYNC_EN = 0
4949 23:46:53.585611 ALL_SLAVE_EN = 1
4950 23:46:53.585692 NEW_RANK_MODE = 1
4951 23:46:53.589037 DLL_IDLE_MODE = 1
4952 23:46:53.592164 LP45_APHY_COMB_EN = 1
4953 23:46:53.595544 TX_ODT_DIS = 1
4954 23:46:53.595624 NEW_8X_MODE = 1
4955 23:46:53.598718 ===================================
4956 23:46:53.602104 ===================================
4957 23:46:53.605522 data_rate = 1866
4958 23:46:53.608661 CKR = 1
4959 23:46:53.612079 DQ_P2S_RATIO = 8
4960 23:46:53.615035 ===================================
4961 23:46:53.618444 CA_P2S_RATIO = 8
4962 23:46:53.622304 DQ_CA_OPEN = 0
4963 23:46:53.625507 DQ_SEMI_OPEN = 0
4964 23:46:53.625590 CA_SEMI_OPEN = 0
4965 23:46:53.628748 CA_FULL_RATE = 0
4966 23:46:53.632093 DQ_CKDIV4_EN = 1
4967 23:46:53.635363 CA_CKDIV4_EN = 1
4968 23:46:53.638523 CA_PREDIV_EN = 0
4969 23:46:53.641651 PH8_DLY = 0
4970 23:46:53.641727 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4971 23:46:53.645349 DQ_AAMCK_DIV = 4
4972 23:46:53.648718 CA_AAMCK_DIV = 4
4973 23:46:53.652029 CA_ADMCK_DIV = 4
4974 23:46:53.655322 DQ_TRACK_CA_EN = 0
4975 23:46:53.658508 CA_PICK = 933
4976 23:46:53.658588 CA_MCKIO = 933
4977 23:46:53.661914 MCKIO_SEMI = 0
4978 23:46:53.665071 PLL_FREQ = 3732
4979 23:46:53.668645 DQ_UI_PI_RATIO = 32
4980 23:46:53.671632 CA_UI_PI_RATIO = 0
4981 23:46:53.674842 ===================================
4982 23:46:53.678649 ===================================
4983 23:46:53.681862 memory_type:LPDDR4
4984 23:46:53.681944 GP_NUM : 10
4985 23:46:53.685120 SRAM_EN : 1
4986 23:46:53.685197 MD32_EN : 0
4987 23:46:53.688260 ===================================
4988 23:46:53.692076 [ANA_INIT] >>>>>>>>>>>>>>
4989 23:46:53.695298 <<<<<< [CONFIGURE PHASE]: ANA_TX
4990 23:46:53.698314 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4991 23:46:53.701790 ===================================
4992 23:46:53.705394 data_rate = 1866,PCW = 0X8f00
4993 23:46:53.708474 ===================================
4994 23:46:53.711887 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4995 23:46:53.715351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4996 23:46:53.721904 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4997 23:46:53.725024 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4998 23:46:53.731819 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4999 23:46:53.735370 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5000 23:46:53.735454 [ANA_INIT] flow start
5001 23:46:53.738245 [ANA_INIT] PLL >>>>>>>>
5002 23:46:53.742178 [ANA_INIT] PLL <<<<<<<<
5003 23:46:53.742258 [ANA_INIT] MIDPI >>>>>>>>
5004 23:46:53.745358 [ANA_INIT] MIDPI <<<<<<<<
5005 23:46:53.748435 [ANA_INIT] DLL >>>>>>>>
5006 23:46:53.748516 [ANA_INIT] flow end
5007 23:46:53.751563 ============ LP4 DIFF to SE enter ============
5008 23:46:53.758219 ============ LP4 DIFF to SE exit ============
5009 23:46:53.758299 [ANA_INIT] <<<<<<<<<<<<<
5010 23:46:53.761714 [Flow] Enable top DCM control >>>>>
5011 23:46:53.764886 [Flow] Enable top DCM control <<<<<
5012 23:46:53.768115 Enable DLL master slave shuffle
5013 23:46:53.775395 ==============================================================
5014 23:46:53.775477 Gating Mode config
5015 23:46:53.781939 ==============================================================
5016 23:46:53.785106 Config description:
5017 23:46:53.794890 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5018 23:46:53.801431 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5019 23:46:53.804784 SELPH_MODE 0: By rank 1: By Phase
5020 23:46:53.811765 ==============================================================
5021 23:46:53.814968 GAT_TRACK_EN = 1
5022 23:46:53.818362 RX_GATING_MODE = 2
5023 23:46:53.818487 RX_GATING_TRACK_MODE = 2
5024 23:46:53.821207 SELPH_MODE = 1
5025 23:46:53.824858 PICG_EARLY_EN = 1
5026 23:46:53.828157 VALID_LAT_VALUE = 1
5027 23:46:53.834460 ==============================================================
5028 23:46:53.838078 Enter into Gating configuration >>>>
5029 23:46:53.841635 Exit from Gating configuration <<<<
5030 23:46:53.844693 Enter into DVFS_PRE_config >>>>>
5031 23:46:53.854835 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5032 23:46:53.858165 Exit from DVFS_PRE_config <<<<<
5033 23:46:53.861275 Enter into PICG configuration >>>>
5034 23:46:53.864379 Exit from PICG configuration <<<<
5035 23:46:53.867787 [RX_INPUT] configuration >>>>>
5036 23:46:53.871081 [RX_INPUT] configuration <<<<<
5037 23:46:53.874480 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5038 23:46:53.881113 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5039 23:46:53.888189 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5040 23:46:53.894874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5041 23:46:53.897968 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5042 23:46:53.904525 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5043 23:46:53.907750 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5044 23:46:53.914652 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5045 23:46:53.917785 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5046 23:46:53.921040 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5047 23:46:53.924298 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5048 23:46:53.930994 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5049 23:46:53.934312 ===================================
5050 23:46:53.934397 LPDDR4 DRAM CONFIGURATION
5051 23:46:53.937792 ===================================
5052 23:46:53.941039 EX_ROW_EN[0] = 0x0
5053 23:46:53.944287 EX_ROW_EN[1] = 0x0
5054 23:46:53.944392 LP4Y_EN = 0x0
5055 23:46:53.947580 WORK_FSP = 0x0
5056 23:46:53.947689 WL = 0x3
5057 23:46:53.950773 RL = 0x3
5058 23:46:53.950884 BL = 0x2
5059 23:46:53.954098 RPST = 0x0
5060 23:46:53.954202 RD_PRE = 0x0
5061 23:46:53.957325 WR_PRE = 0x1
5062 23:46:53.957420 WR_PST = 0x0
5063 23:46:53.960559 DBI_WR = 0x0
5064 23:46:53.960664 DBI_RD = 0x0
5065 23:46:53.964209 OTF = 0x1
5066 23:46:53.967730 ===================================
5067 23:46:53.970542 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5068 23:46:53.974161 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5069 23:46:53.980768 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5070 23:46:53.984261 ===================================
5071 23:46:53.984369 LPDDR4 DRAM CONFIGURATION
5072 23:46:53.987450 ===================================
5073 23:46:53.990804 EX_ROW_EN[0] = 0x10
5074 23:46:53.994090 EX_ROW_EN[1] = 0x0
5075 23:46:53.994201 LP4Y_EN = 0x0
5076 23:46:53.997476 WORK_FSP = 0x0
5077 23:46:53.997597 WL = 0x3
5078 23:46:54.000682 RL = 0x3
5079 23:46:54.000796 BL = 0x2
5080 23:46:54.004054 RPST = 0x0
5081 23:46:54.004166 RD_PRE = 0x0
5082 23:46:54.007729 WR_PRE = 0x1
5083 23:46:54.007832 WR_PST = 0x0
5084 23:46:54.010921 DBI_WR = 0x0
5085 23:46:54.011032 DBI_RD = 0x0
5086 23:46:54.014419 OTF = 0x1
5087 23:46:54.017687 ===================================
5088 23:46:54.023667 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5089 23:46:54.027471 nWR fixed to 30
5090 23:46:54.027556 [ModeRegInit_LP4] CH0 RK0
5091 23:46:54.030762 [ModeRegInit_LP4] CH0 RK1
5092 23:46:54.034075 [ModeRegInit_LP4] CH1 RK0
5093 23:46:54.034150 [ModeRegInit_LP4] CH1 RK1
5094 23:46:54.037447 match AC timing 9
5095 23:46:54.040637 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5096 23:46:54.043987 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5097 23:46:54.050897 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5098 23:46:54.053819 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5099 23:46:54.061054 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5100 23:46:54.061162 ==
5101 23:46:54.064216 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 23:46:54.067300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 23:46:54.067403 ==
5104 23:46:54.074210 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5105 23:46:54.077322 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5106 23:46:54.081883 [CA 0] Center 37 (6~68) winsize 63
5107 23:46:54.085197 [CA 1] Center 37 (6~68) winsize 63
5108 23:46:54.088100 [CA 2] Center 34 (4~65) winsize 62
5109 23:46:54.091662 [CA 3] Center 34 (3~65) winsize 63
5110 23:46:54.094770 [CA 4] Center 33 (3~64) winsize 62
5111 23:46:54.098603 [CA 5] Center 32 (2~62) winsize 61
5112 23:46:54.098688
5113 23:46:54.101882 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5114 23:46:54.101958
5115 23:46:54.104731 [CATrainingPosCal] consider 1 rank data
5116 23:46:54.108217 u2DelayCellTimex100 = 270/100 ps
5117 23:46:54.111458 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5118 23:46:54.118421 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5119 23:46:54.121529 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5120 23:46:54.124736 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5121 23:46:54.127945 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5122 23:46:54.131642 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5123 23:46:54.131721
5124 23:46:54.134850 CA PerBit enable=1, Macro0, CA PI delay=32
5125 23:46:54.134933
5126 23:46:54.138066 [CBTSetCACLKResult] CA Dly = 32
5127 23:46:54.141410 CS Dly: 5 (0~36)
5128 23:46:54.141481 ==
5129 23:46:54.144719 Dram Type= 6, Freq= 0, CH_0, rank 1
5130 23:46:54.148013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 23:46:54.148084 ==
5132 23:46:54.151130 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5133 23:46:54.157862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5134 23:46:54.161556 [CA 0] Center 37 (6~68) winsize 63
5135 23:46:54.165067 [CA 1] Center 37 (6~68) winsize 63
5136 23:46:54.168275 [CA 2] Center 34 (4~65) winsize 62
5137 23:46:54.171865 [CA 3] Center 34 (3~65) winsize 63
5138 23:46:54.175189 [CA 4] Center 32 (2~63) winsize 62
5139 23:46:54.178669 [CA 5] Center 32 (2~62) winsize 61
5140 23:46:54.178750
5141 23:46:54.181665 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5142 23:46:54.181777
5143 23:46:54.184943 [CATrainingPosCal] consider 2 rank data
5144 23:46:54.188675 u2DelayCellTimex100 = 270/100 ps
5145 23:46:54.191573 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5146 23:46:54.194793 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5147 23:46:54.201565 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5148 23:46:54.205094 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5149 23:46:54.208384 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5150 23:46:54.211846 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5151 23:46:54.211956
5152 23:46:54.214899 CA PerBit enable=1, Macro0, CA PI delay=32
5153 23:46:54.214979
5154 23:46:54.218087 [CBTSetCACLKResult] CA Dly = 32
5155 23:46:54.218168 CS Dly: 5 (0~37)
5156 23:46:54.221693
5157 23:46:54.224999 ----->DramcWriteLeveling(PI) begin...
5158 23:46:54.225094 ==
5159 23:46:54.228222 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 23:46:54.231337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 23:46:54.231411 ==
5162 23:46:54.235101 Write leveling (Byte 0): 31 => 31
5163 23:46:54.238270 Write leveling (Byte 1): 30 => 30
5164 23:46:54.241249 DramcWriteLeveling(PI) end<-----
5165 23:46:54.241329
5166 23:46:54.241393 ==
5167 23:46:54.244565 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 23:46:54.248028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 23:46:54.248137 ==
5170 23:46:54.251111 [Gating] SW mode calibration
5171 23:46:54.257716 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5172 23:46:54.264915 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5173 23:46:54.267895 0 14 0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5174 23:46:54.271509 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 23:46:54.278279 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 23:46:54.281602 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 23:46:54.285015 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 23:46:54.291598 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 23:46:54.294950 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5180 23:46:54.297686 0 14 28 | B1->B0 | 3333 2828 | 1 0 | (1 1) (1 0)
5181 23:46:54.301532 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
5182 23:46:54.308016 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 23:46:54.311250 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 23:46:54.314507 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 23:46:54.321042 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 23:46:54.324450 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 23:46:54.327837 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 23:46:54.334380 0 15 28 | B1->B0 | 2323 3b3b | 0 1 | (0 0) (0 0)
5189 23:46:54.337771 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5190 23:46:54.340860 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 23:46:54.347580 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 23:46:54.351106 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 23:46:54.354649 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 23:46:54.360962 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 23:46:54.364389 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 23:46:54.368010 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5197 23:46:54.374693 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5198 23:46:54.377734 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 23:46:54.380918 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 23:46:54.387674 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 23:46:54.390607 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 23:46:54.393977 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 23:46:54.400590 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 23:46:54.403884 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 23:46:54.407220 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 23:46:54.413776 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 23:46:54.417131 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 23:46:54.420500 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 23:46:54.427048 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 23:46:54.430967 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 23:46:54.434053 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5212 23:46:54.440587 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5213 23:46:54.443985 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 23:46:54.447469 Total UI for P1: 0, mck2ui 16
5215 23:46:54.450172 best dqsien dly found for B0: ( 1, 2, 26)
5216 23:46:54.453559 Total UI for P1: 0, mck2ui 16
5217 23:46:54.456851 best dqsien dly found for B1: ( 1, 2, 30)
5218 23:46:54.460273 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5219 23:46:54.463857 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5220 23:46:54.463966
5221 23:46:54.467173 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5222 23:46:54.470691 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5223 23:46:54.474181 [Gating] SW calibration Done
5224 23:46:54.474265 ==
5225 23:46:54.476825 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 23:46:54.480462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 23:46:54.480550 ==
5228 23:46:54.483416 RX Vref Scan: 0
5229 23:46:54.483500
5230 23:46:54.486663 RX Vref 0 -> 0, step: 1
5231 23:46:54.486747
5232 23:46:54.486832 RX Delay -80 -> 252, step: 8
5233 23:46:54.493657 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5234 23:46:54.496859 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5235 23:46:54.500149 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5236 23:46:54.503613 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5237 23:46:54.506860 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5238 23:46:54.514002 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5239 23:46:54.517352 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5240 23:46:54.520531 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5241 23:46:54.523745 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5242 23:46:54.527028 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5243 23:46:54.530286 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5244 23:46:54.537040 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5245 23:46:54.540108 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5246 23:46:54.543837 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5247 23:46:54.547032 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5248 23:46:54.550327 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5249 23:46:54.553672 ==
5250 23:46:54.553767 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 23:46:54.559825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 23:46:54.559912 ==
5253 23:46:54.559987 DQS Delay:
5254 23:46:54.563439 DQS0 = 0, DQS1 = 0
5255 23:46:54.563527 DQM Delay:
5256 23:46:54.566345 DQM0 = 106, DQM1 = 95
5257 23:46:54.566431 DQ Delay:
5258 23:46:54.569964 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5259 23:46:54.573076 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =115
5260 23:46:54.576819 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5261 23:46:54.579748 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5262 23:46:54.579833
5263 23:46:54.579900
5264 23:46:54.579962 ==
5265 23:46:54.583437 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 23:46:54.587185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 23:46:54.587270 ==
5268 23:46:54.590125
5269 23:46:54.590209
5270 23:46:54.590275 TX Vref Scan disable
5271 23:46:54.593420 == TX Byte 0 ==
5272 23:46:54.596720 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5273 23:46:54.599830 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5274 23:46:54.603545 == TX Byte 1 ==
5275 23:46:54.606707 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5276 23:46:54.610504 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5277 23:46:54.610589 ==
5278 23:46:54.613548 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 23:46:54.620087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 23:46:54.620173 ==
5281 23:46:54.620240
5282 23:46:54.620302
5283 23:46:54.620368 TX Vref Scan disable
5284 23:46:54.623949 == TX Byte 0 ==
5285 23:46:54.627345 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5286 23:46:54.630814 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5287 23:46:54.634060 == TX Byte 1 ==
5288 23:46:54.637344 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5289 23:46:54.640814 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5290 23:46:54.643914
5291 23:46:54.643998 [DATLAT]
5292 23:46:54.644064 Freq=933, CH0 RK0
5293 23:46:54.644141
5294 23:46:54.647731 DATLAT Default: 0xd
5295 23:46:54.647815 0, 0xFFFF, sum = 0
5296 23:46:54.651026 1, 0xFFFF, sum = 0
5297 23:46:54.651111 2, 0xFFFF, sum = 0
5298 23:46:54.654152 3, 0xFFFF, sum = 0
5299 23:46:54.654238 4, 0xFFFF, sum = 0
5300 23:46:54.657599 5, 0xFFFF, sum = 0
5301 23:46:54.657688 6, 0xFFFF, sum = 0
5302 23:46:54.660586 7, 0xFFFF, sum = 0
5303 23:46:54.663814 8, 0xFFFF, sum = 0
5304 23:46:54.663923 9, 0xFFFF, sum = 0
5305 23:46:54.667701 10, 0x0, sum = 1
5306 23:46:54.667811 11, 0x0, sum = 2
5307 23:46:54.667908 12, 0x0, sum = 3
5308 23:46:54.670757 13, 0x0, sum = 4
5309 23:46:54.670861 best_step = 11
5310 23:46:54.670955
5311 23:46:54.671052 ==
5312 23:46:54.673790 Dram Type= 6, Freq= 0, CH_0, rank 0
5313 23:46:54.680808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 23:46:54.680899 ==
5315 23:46:54.680986 RX Vref Scan: 1
5316 23:46:54.681069
5317 23:46:54.683965 RX Vref 0 -> 0, step: 1
5318 23:46:54.684047
5319 23:46:54.687699 RX Delay -45 -> 252, step: 4
5320 23:46:54.687784
5321 23:46:54.690712 Set Vref, RX VrefLevel [Byte0]: 56
5322 23:46:54.694035 [Byte1]: 54
5323 23:46:54.694153
5324 23:46:54.697332 Final RX Vref Byte 0 = 56 to rank0
5325 23:46:54.700707 Final RX Vref Byte 1 = 54 to rank0
5326 23:46:54.704310 Final RX Vref Byte 0 = 56 to rank1
5327 23:46:54.707394 Final RX Vref Byte 1 = 54 to rank1==
5328 23:46:54.710605 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 23:46:54.713911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 23:46:54.714021 ==
5331 23:46:54.717262 DQS Delay:
5332 23:46:54.717341 DQS0 = 0, DQS1 = 0
5333 23:46:54.721029 DQM Delay:
5334 23:46:54.721105 DQM0 = 105, DQM1 = 96
5335 23:46:54.721168 DQ Delay:
5336 23:46:54.723669 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5337 23:46:54.730215 DQ4 =106, DQ5 =96, DQ6 =114, DQ7 =110
5338 23:46:54.730302 DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =92
5339 23:46:54.736959 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =106
5340 23:46:54.737052
5341 23:46:54.737120
5342 23:46:54.743538 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5343 23:46:54.746757 CH0 RK0: MR19=505, MR18=2E26
5344 23:46:54.753271 CH0_RK0: MR19=0x505, MR18=0x2E26, DQSOSC=407, MR23=63, INC=65, DEC=43
5345 23:46:54.753373
5346 23:46:54.756995 ----->DramcWriteLeveling(PI) begin...
5347 23:46:54.757077 ==
5348 23:46:54.760172 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 23:46:54.763704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 23:46:54.763808 ==
5351 23:46:54.767093 Write leveling (Byte 0): 33 => 33
5352 23:46:54.770316 Write leveling (Byte 1): 28 => 28
5353 23:46:54.772925 DramcWriteLeveling(PI) end<-----
5354 23:46:54.773033
5355 23:46:54.773125 ==
5356 23:46:54.776249 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 23:46:54.779525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 23:46:54.783230 ==
5359 23:46:54.783332 [Gating] SW mode calibration
5360 23:46:54.789882 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5361 23:46:54.796488 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5362 23:46:54.800150 0 14 0 | B1->B0 | 3434 3232 | 0 0 | (0 0) (0 0)
5363 23:46:54.806596 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 23:46:54.809906 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 23:46:54.813334 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 23:46:54.819655 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 23:46:54.822674 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 23:46:54.826691 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5369 23:46:54.833213 0 14 28 | B1->B0 | 2b2b 2d2d | 0 0 | (0 0) (0 0)
5370 23:46:54.836555 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5371 23:46:54.839238 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 23:46:54.846351 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 23:46:54.849662 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 23:46:54.853015 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 23:46:54.859723 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 23:46:54.862911 0 15 24 | B1->B0 | 2727 2525 | 0 0 | (0 0) (0 0)
5377 23:46:54.866097 0 15 28 | B1->B0 | 3e3e 3a3a | 0 0 | (0 0) (0 0)
5378 23:46:54.872684 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 23:46:54.875921 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 23:46:54.879230 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 23:46:54.885942 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 23:46:54.889155 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 23:46:54.893009 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 23:46:54.899211 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 23:46:54.902273 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5386 23:46:54.906019 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5387 23:46:54.909032 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 23:46:54.916194 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 23:46:54.919584 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 23:46:54.922821 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 23:46:54.929106 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 23:46:54.932593 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 23:46:54.935862 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 23:46:54.942627 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 23:46:54.945702 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 23:46:54.949451 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 23:46:54.955518 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 23:46:54.959583 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 23:46:54.962654 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 23:46:54.969037 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5401 23:46:54.972310 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5402 23:46:54.979201 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 23:46:54.979475 Total UI for P1: 0, mck2ui 16
5404 23:46:54.982322 best dqsien dly found for B0: ( 1, 2, 26)
5405 23:46:54.985598 Total UI for P1: 0, mck2ui 16
5406 23:46:54.988934 best dqsien dly found for B1: ( 1, 2, 30)
5407 23:46:54.992066 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5408 23:46:54.995867 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5409 23:46:54.995981
5410 23:46:55.002383 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5411 23:46:55.005626 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5412 23:46:55.005740 [Gating] SW calibration Done
5413 23:46:55.008934 ==
5414 23:46:55.012542 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 23:46:55.015633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 23:46:55.015747 ==
5417 23:46:55.015849 RX Vref Scan: 0
5418 23:46:55.015944
5419 23:46:55.018640 RX Vref 0 -> 0, step: 1
5420 23:46:55.018755
5421 23:46:55.022132 RX Delay -80 -> 252, step: 8
5422 23:46:55.025733 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5423 23:46:55.028763 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5424 23:46:55.031834 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5425 23:46:55.038681 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5426 23:46:55.041616 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5427 23:46:55.045541 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5428 23:46:55.048272 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5429 23:46:55.052144 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5430 23:46:55.055580 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5431 23:46:55.062116 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5432 23:46:55.065119 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5433 23:46:55.068690 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5434 23:46:55.071768 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5435 23:46:55.074978 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5436 23:46:55.082159 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5437 23:46:55.085293 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5438 23:46:55.085422 ==
5439 23:46:55.088514 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 23:46:55.091723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 23:46:55.091832 ==
5442 23:46:55.091942 DQS Delay:
5443 23:46:55.095141 DQS0 = 0, DQS1 = 0
5444 23:46:55.095251 DQM Delay:
5445 23:46:55.098781 DQM0 = 105, DQM1 = 93
5446 23:46:55.098895 DQ Delay:
5447 23:46:55.101997 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5448 23:46:55.105175 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5449 23:46:55.108115 DQ8 =87, DQ9 =83, DQ10 =91, DQ11 =87
5450 23:46:55.111813 DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99
5451 23:46:55.111935
5452 23:46:55.112037
5453 23:46:55.112133 ==
5454 23:46:55.115245 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 23:46:55.121617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 23:46:55.121735 ==
5457 23:46:55.121838
5458 23:46:55.121938
5459 23:46:55.122028 TX Vref Scan disable
5460 23:46:55.125268 == TX Byte 0 ==
5461 23:46:55.128382 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5462 23:46:55.132129 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5463 23:46:55.135798 == TX Byte 1 ==
5464 23:46:55.138989 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5465 23:46:55.142149 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5466 23:46:55.145289 ==
5467 23:46:55.148727 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 23:46:55.152014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 23:46:55.152127 ==
5470 23:46:55.152225
5471 23:46:55.152319
5472 23:46:55.155359 TX Vref Scan disable
5473 23:46:55.155465 == TX Byte 0 ==
5474 23:46:55.161971 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5475 23:46:55.165542 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5476 23:46:55.165654 == TX Byte 1 ==
5477 23:46:55.171902 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5478 23:46:55.175251 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5479 23:46:55.175365
5480 23:46:55.175467 [DATLAT]
5481 23:46:55.178699 Freq=933, CH0 RK1
5482 23:46:55.178789
5483 23:46:55.178857 DATLAT Default: 0xb
5484 23:46:55.181763 0, 0xFFFF, sum = 0
5485 23:46:55.181851 1, 0xFFFF, sum = 0
5486 23:46:55.185367 2, 0xFFFF, sum = 0
5487 23:46:55.185487 3, 0xFFFF, sum = 0
5488 23:46:55.188454 4, 0xFFFF, sum = 0
5489 23:46:55.191859 5, 0xFFFF, sum = 0
5490 23:46:55.191971 6, 0xFFFF, sum = 0
5491 23:46:55.194878 7, 0xFFFF, sum = 0
5492 23:46:55.194994 8, 0xFFFF, sum = 0
5493 23:46:55.198115 9, 0xFFFF, sum = 0
5494 23:46:55.198224 10, 0x0, sum = 1
5495 23:46:55.201324 11, 0x0, sum = 2
5496 23:46:55.201436 12, 0x0, sum = 3
5497 23:46:55.201536 13, 0x0, sum = 4
5498 23:46:55.205108 best_step = 11
5499 23:46:55.205220
5500 23:46:55.205322 ==
5501 23:46:55.208482 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 23:46:55.211573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 23:46:55.211689 ==
5504 23:46:55.214602 RX Vref Scan: 0
5505 23:46:55.214710
5506 23:46:55.218316 RX Vref 0 -> 0, step: 1
5507 23:46:55.218426
5508 23:46:55.218535 RX Delay -53 -> 252, step: 4
5509 23:46:55.225956 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5510 23:46:55.229354 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5511 23:46:55.232256 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5512 23:46:55.235986 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5513 23:46:55.239060 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5514 23:46:55.246013 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5515 23:46:55.249296 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5516 23:46:55.252277 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5517 23:46:55.256002 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5518 23:46:55.259134 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5519 23:46:55.262298 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5520 23:46:55.269285 iDelay=199, Bit 11, Center 90 (7 ~ 174) 168
5521 23:46:55.272651 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5522 23:46:55.275673 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5523 23:46:55.279041 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5524 23:46:55.285808 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5525 23:46:55.285903 ==
5526 23:46:55.289208 Dram Type= 6, Freq= 0, CH_0, rank 1
5527 23:46:55.292552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 23:46:55.292635 ==
5529 23:46:55.292713 DQS Delay:
5530 23:46:55.295624 DQS0 = 0, DQS1 = 0
5531 23:46:55.295736 DQM Delay:
5532 23:46:55.299147 DQM0 = 104, DQM1 = 95
5533 23:46:55.299268 DQ Delay:
5534 23:46:55.302200 DQ0 =102, DQ1 =104, DQ2 =102, DQ3 =102
5535 23:46:55.305245 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5536 23:46:55.309349 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =90
5537 23:46:55.312373 DQ12 =100, DQ13 =100, DQ14 =104, DQ15 =102
5538 23:46:55.312460
5539 23:46:55.312559
5540 23:46:55.322427 [DQSOSCAuto] RK1, (LSB)MR18= 0x2801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps
5541 23:46:55.322553 CH0 RK1: MR19=505, MR18=2801
5542 23:46:55.329040 CH0_RK1: MR19=0x505, MR18=0x2801, DQSOSC=409, MR23=63, INC=64, DEC=43
5543 23:46:55.332217 [RxdqsGatingPostProcess] freq 933
5544 23:46:55.338718 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5545 23:46:55.342382 best DQS0 dly(2T, 0.5T) = (0, 10)
5546 23:46:55.345431 best DQS1 dly(2T, 0.5T) = (0, 10)
5547 23:46:55.348680 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5548 23:46:55.352690 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5549 23:46:55.355769 best DQS0 dly(2T, 0.5T) = (0, 10)
5550 23:46:55.355875 best DQS1 dly(2T, 0.5T) = (0, 10)
5551 23:46:55.358935 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5552 23:46:55.361968 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5553 23:46:55.365535 Pre-setting of DQS Precalculation
5554 23:46:55.372182 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5555 23:46:55.372312 ==
5556 23:46:55.375640 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 23:46:55.378560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 23:46:55.378672 ==
5559 23:46:55.385278 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5560 23:46:55.392180 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5561 23:46:55.395082 [CA 0] Center 37 (6~68) winsize 63
5562 23:46:55.398937 [CA 1] Center 37 (6~68) winsize 63
5563 23:46:55.401867 [CA 2] Center 35 (5~65) winsize 61
5564 23:46:55.405575 [CA 3] Center 34 (4~65) winsize 62
5565 23:46:55.408914 [CA 4] Center 34 (4~64) winsize 61
5566 23:46:55.412186 [CA 5] Center 33 (3~64) winsize 62
5567 23:46:55.412303
5568 23:46:55.415086 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5569 23:46:55.415199
5570 23:46:55.418972 [CATrainingPosCal] consider 1 rank data
5571 23:46:55.422210 u2DelayCellTimex100 = 270/100 ps
5572 23:46:55.425330 CA0 delay=37 (6~68),Diff = 4 PI (24 cell)
5573 23:46:55.428448 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5574 23:46:55.431960 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5575 23:46:55.435230 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5576 23:46:55.439048 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5577 23:46:55.442176 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5578 23:46:55.442270
5579 23:46:55.445364 CA PerBit enable=1, Macro0, CA PI delay=33
5580 23:46:55.445451
5581 23:46:55.449063 [CBTSetCACLKResult] CA Dly = 33
5582 23:46:55.452175 CS Dly: 6 (0~37)
5583 23:46:55.452262 ==
5584 23:46:55.455522 Dram Type= 6, Freq= 0, CH_1, rank 1
5585 23:46:55.458824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 23:46:55.458914 ==
5587 23:46:55.465596 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5588 23:46:55.472259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5589 23:46:55.475513 [CA 0] Center 36 (6~67) winsize 62
5590 23:46:55.478668 [CA 1] Center 37 (6~68) winsize 63
5591 23:46:55.481937 [CA 2] Center 35 (4~66) winsize 63
5592 23:46:55.485058 [CA 3] Center 34 (4~65) winsize 62
5593 23:46:55.488996 [CA 4] Center 34 (4~65) winsize 62
5594 23:46:55.491888 [CA 5] Center 34 (4~64) winsize 61
5595 23:46:55.491975
5596 23:46:55.495387 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5597 23:46:55.495475
5598 23:46:55.498462 [CATrainingPosCal] consider 2 rank data
5599 23:46:55.502063 u2DelayCellTimex100 = 270/100 ps
5600 23:46:55.505187 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5601 23:46:55.508324 CA1 delay=37 (6~68),Diff = 3 PI (18 cell)
5602 23:46:55.512208 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5603 23:46:55.515080 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5604 23:46:55.518319 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5605 23:46:55.521440 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5606 23:46:55.521555
5607 23:46:55.528614 CA PerBit enable=1, Macro0, CA PI delay=34
5608 23:46:55.528703
5609 23:46:55.528771 [CBTSetCACLKResult] CA Dly = 34
5610 23:46:55.531706 CS Dly: 7 (0~40)
5611 23:46:55.531792
5612 23:46:55.535095 ----->DramcWriteLeveling(PI) begin...
5613 23:46:55.535195 ==
5614 23:46:55.538179 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 23:46:55.541256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 23:46:55.541363 ==
5617 23:46:55.544695 Write leveling (Byte 0): 27 => 27
5618 23:46:55.547887 Write leveling (Byte 1): 29 => 29
5619 23:46:55.551375 DramcWriteLeveling(PI) end<-----
5620 23:46:55.551486
5621 23:46:55.551583 ==
5622 23:46:55.554557 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 23:46:55.561442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 23:46:55.561560 ==
5625 23:46:55.561666 [Gating] SW mode calibration
5626 23:46:55.571139 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5627 23:46:55.574976 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5628 23:46:55.577899 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 23:46:55.584919 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 23:46:55.588131 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 23:46:55.591446 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 23:46:55.597893 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 23:46:55.601264 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 23:46:55.604882 0 14 24 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
5635 23:46:55.611157 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (1 0)
5636 23:46:55.614617 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 23:46:55.617976 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 23:46:55.624786 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 23:46:55.628076 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 23:46:55.631170 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 23:46:55.638119 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 23:46:55.641416 0 15 24 | B1->B0 | 2424 3232 | 0 0 | (0 0) (0 0)
5643 23:46:55.644889 0 15 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5644 23:46:55.651259 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 23:46:55.654360 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 23:46:55.657908 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 23:46:55.664390 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 23:46:55.667922 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 23:46:55.671047 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 23:46:55.674219 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5651 23:46:55.681295 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 23:46:55.684633 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 23:46:55.687716 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 23:46:55.694342 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 23:46:55.697398 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 23:46:55.701215 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 23:46:55.707844 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 23:46:55.711158 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 23:46:55.714543 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 23:46:55.721000 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 23:46:55.724589 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 23:46:55.727380 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 23:46:55.734074 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 23:46:55.737773 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 23:46:55.740951 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 23:46:55.747520 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5667 23:46:55.751112 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5668 23:46:55.754185 Total UI for P1: 0, mck2ui 16
5669 23:46:55.757991 best dqsien dly found for B0: ( 1, 2, 24)
5670 23:46:55.761168 Total UI for P1: 0, mck2ui 16
5671 23:46:55.764436 best dqsien dly found for B1: ( 1, 2, 24)
5672 23:46:55.767471 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5673 23:46:55.771060 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5674 23:46:55.771171
5675 23:46:55.774074 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5676 23:46:55.777386 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5677 23:46:55.781014 [Gating] SW calibration Done
5678 23:46:55.781129 ==
5679 23:46:55.784269 Dram Type= 6, Freq= 0, CH_1, rank 0
5680 23:46:55.787521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5681 23:46:55.787637 ==
5682 23:46:55.790843 RX Vref Scan: 0
5683 23:46:55.790954
5684 23:46:55.794128 RX Vref 0 -> 0, step: 1
5685 23:46:55.794238
5686 23:46:55.794342 RX Delay -80 -> 252, step: 8
5687 23:46:55.800655 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5688 23:46:55.804458 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5689 23:46:55.807639 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5690 23:46:55.810964 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5691 23:46:55.814127 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5692 23:46:55.817400 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5693 23:46:55.823741 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5694 23:46:55.827465 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5695 23:46:55.830665 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5696 23:46:55.833842 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5697 23:46:55.837026 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5698 23:46:55.840963 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5699 23:46:55.847231 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5700 23:46:55.850963 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5701 23:46:55.854118 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5702 23:46:55.857163 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5703 23:46:55.857250 ==
5704 23:46:55.860564 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 23:46:55.867479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 23:46:55.867596 ==
5707 23:46:55.867705 DQS Delay:
5708 23:46:55.870678 DQS0 = 0, DQS1 = 0
5709 23:46:55.870793 DQM Delay:
5710 23:46:55.870899 DQM0 = 103, DQM1 = 98
5711 23:46:55.874003 DQ Delay:
5712 23:46:55.877195 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5713 23:46:55.880904 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5714 23:46:55.883855 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5715 23:46:55.887383 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5716 23:46:55.887494
5717 23:46:55.887601
5718 23:46:55.887703 ==
5719 23:46:55.890642 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 23:46:55.893718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 23:46:55.893829 ==
5722 23:46:55.893933
5723 23:46:55.894035
5724 23:46:55.897023 TX Vref Scan disable
5725 23:46:55.900191 == TX Byte 0 ==
5726 23:46:55.903909 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5727 23:46:55.906928 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5728 23:46:55.910515 == TX Byte 1 ==
5729 23:46:55.913721 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5730 23:46:55.917359 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5731 23:46:55.917470 ==
5732 23:46:55.920542 Dram Type= 6, Freq= 0, CH_1, rank 0
5733 23:46:55.926833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 23:46:55.926949 ==
5735 23:46:55.927056
5736 23:46:55.927168
5737 23:46:55.927267 TX Vref Scan disable
5738 23:46:55.931269 == TX Byte 0 ==
5739 23:46:55.934069 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5740 23:46:55.941128 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5741 23:46:55.941251 == TX Byte 1 ==
5742 23:46:55.944260 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5743 23:46:55.947497 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5744 23:46:55.951291
5745 23:46:55.951403 [DATLAT]
5746 23:46:55.951499 Freq=933, CH1 RK0
5747 23:46:55.951595
5748 23:46:55.954197 DATLAT Default: 0xd
5749 23:46:55.954311 0, 0xFFFF, sum = 0
5750 23:46:55.957853 1, 0xFFFF, sum = 0
5751 23:46:55.957967 2, 0xFFFF, sum = 0
5752 23:46:55.961160 3, 0xFFFF, sum = 0
5753 23:46:55.961314 4, 0xFFFF, sum = 0
5754 23:46:55.963995 5, 0xFFFF, sum = 0
5755 23:46:55.967667 6, 0xFFFF, sum = 0
5756 23:46:55.967805 7, 0xFFFF, sum = 0
5757 23:46:55.970847 8, 0xFFFF, sum = 0
5758 23:46:55.970959 9, 0xFFFF, sum = 0
5759 23:46:55.974118 10, 0x0, sum = 1
5760 23:46:55.974229 11, 0x0, sum = 2
5761 23:46:55.974326 12, 0x0, sum = 3
5762 23:46:55.977866 13, 0x0, sum = 4
5763 23:46:55.977978 best_step = 11
5764 23:46:55.978071
5765 23:46:55.978165 ==
5766 23:46:55.981025 Dram Type= 6, Freq= 0, CH_1, rank 0
5767 23:46:55.987529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 23:46:55.987642 ==
5769 23:46:55.987751 RX Vref Scan: 1
5770 23:46:55.987855
5771 23:46:55.990702 RX Vref 0 -> 0, step: 1
5772 23:46:55.990811
5773 23:46:55.994376 RX Delay -45 -> 252, step: 4
5774 23:46:55.994486
5775 23:46:55.997630 Set Vref, RX VrefLevel [Byte0]: 50
5776 23:46:56.000850 [Byte1]: 48
5777 23:46:56.000963
5778 23:46:56.004073 Final RX Vref Byte 0 = 50 to rank0
5779 23:46:56.007441 Final RX Vref Byte 1 = 48 to rank0
5780 23:46:56.011011 Final RX Vref Byte 0 = 50 to rank1
5781 23:46:56.014130 Final RX Vref Byte 1 = 48 to rank1==
5782 23:46:56.017100 Dram Type= 6, Freq= 0, CH_1, rank 0
5783 23:46:56.021000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 23:46:56.021125 ==
5785 23:46:56.024051 DQS Delay:
5786 23:46:56.024164 DQS0 = 0, DQS1 = 0
5787 23:46:56.027180 DQM Delay:
5788 23:46:56.027288 DQM0 = 103, DQM1 = 100
5789 23:46:56.027403 DQ Delay:
5790 23:46:56.030408 DQ0 =108, DQ1 =96, DQ2 =92, DQ3 =100
5791 23:46:56.034156 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =100
5792 23:46:56.040624 DQ8 =90, DQ9 =90, DQ10 =100, DQ11 =90
5793 23:46:56.043934 DQ12 =108, DQ13 =106, DQ14 =106, DQ15 =110
5794 23:46:56.044047
5795 23:46:56.044152
5796 23:46:56.050488 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5797 23:46:56.054106 CH1 RK0: MR19=505, MR18=1B33
5798 23:46:56.060397 CH1_RK0: MR19=0x505, MR18=0x1B33, DQSOSC=405, MR23=63, INC=66, DEC=44
5799 23:46:56.060517
5800 23:46:56.064170 ----->DramcWriteLeveling(PI) begin...
5801 23:46:56.064281 ==
5802 23:46:56.067049 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 23:46:56.070471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 23:46:56.070587 ==
5805 23:46:56.074385 Write leveling (Byte 0): 26 => 26
5806 23:46:56.077374 Write leveling (Byte 1): 28 => 28
5807 23:46:56.080789 DramcWriteLeveling(PI) end<-----
5808 23:46:56.080907
5809 23:46:56.081009 ==
5810 23:46:56.083991 Dram Type= 6, Freq= 0, CH_1, rank 1
5811 23:46:56.087195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 23:46:56.087303 ==
5813 23:46:56.090390 [Gating] SW mode calibration
5814 23:46:56.096749 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5815 23:46:56.103618 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5816 23:46:56.107110 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5817 23:46:56.114043 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 23:46:56.117118 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 23:46:56.120290 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 23:46:56.127047 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 23:46:56.130140 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 23:46:56.133444 0 14 24 | B1->B0 | 2f2f 3131 | 0 1 | (0 0) (1 0)
5823 23:46:56.140490 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5824 23:46:56.143504 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 23:46:56.146567 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 23:46:56.153647 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 23:46:56.156797 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 23:46:56.159773 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 23:46:56.166770 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5830 23:46:56.170269 0 15 24 | B1->B0 | 2f2f 2a2a | 1 0 | (0 0) (0 0)
5831 23:46:56.173272 0 15 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)
5832 23:46:56.176484 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5833 23:46:56.183035 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 23:46:56.186457 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 23:46:56.189797 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 23:46:56.196336 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 23:46:56.200231 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 23:46:56.203506 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5839 23:46:56.210289 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5840 23:46:56.213061 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 23:46:56.216698 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 23:46:56.223287 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 23:46:56.226648 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 23:46:56.229661 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 23:46:56.236437 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 23:46:56.240041 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 23:46:56.243404 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 23:46:56.249495 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 23:46:56.252661 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 23:46:56.255941 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 23:46:56.262986 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 23:46:56.266395 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 23:46:56.269565 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5854 23:46:56.275902 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5855 23:46:56.279225 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5856 23:46:56.282534 Total UI for P1: 0, mck2ui 16
5857 23:46:56.285775 best dqsien dly found for B0: ( 1, 2, 22)
5858 23:46:56.289699 Total UI for P1: 0, mck2ui 16
5859 23:46:56.292591 best dqsien dly found for B1: ( 1, 2, 22)
5860 23:46:56.296017 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5861 23:46:56.299321 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5862 23:46:56.299436
5863 23:46:56.302676 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5864 23:46:56.305953 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5865 23:46:56.309031 [Gating] SW calibration Done
5866 23:46:56.309140 ==
5867 23:46:56.312331 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 23:46:56.316107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 23:46:56.319336 ==
5870 23:46:56.319441 RX Vref Scan: 0
5871 23:46:56.319543
5872 23:46:56.322423 RX Vref 0 -> 0, step: 1
5873 23:46:56.322533
5874 23:46:56.325519 RX Delay -80 -> 252, step: 8
5875 23:46:56.329024 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5876 23:46:56.332720 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5877 23:46:56.335558 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5878 23:46:56.338975 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5879 23:46:56.342084 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5880 23:46:56.348846 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5881 23:46:56.352552 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5882 23:46:56.355778 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5883 23:46:56.358850 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5884 23:46:56.362173 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5885 23:46:56.365362 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5886 23:46:56.372435 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5887 23:46:56.375675 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5888 23:46:56.378897 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5889 23:46:56.382185 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5890 23:46:56.385256 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5891 23:46:56.385345 ==
5892 23:46:56.388780 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 23:46:56.395785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 23:46:56.395883 ==
5895 23:46:56.395952 DQS Delay:
5896 23:46:56.399073 DQS0 = 0, DQS1 = 0
5897 23:46:56.399159 DQM Delay:
5898 23:46:56.402371 DQM0 = 102, DQM1 = 98
5899 23:46:56.402460 DQ Delay:
5900 23:46:56.405451 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5901 23:46:56.408862 DQ4 =95, DQ5 =119, DQ6 =111, DQ7 =99
5902 23:46:56.411659 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5903 23:46:56.415022 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5904 23:46:56.415144
5905 23:46:56.415240
5906 23:46:56.415341 ==
5907 23:46:56.418797 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 23:46:56.421775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 23:46:56.421859 ==
5910 23:46:56.421925
5911 23:46:56.425525
5912 23:46:56.425622 TX Vref Scan disable
5913 23:46:56.428703 == TX Byte 0 ==
5914 23:46:56.431987 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5915 23:46:56.435115 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5916 23:46:56.438887 == TX Byte 1 ==
5917 23:46:56.441839 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5918 23:46:56.445044 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5919 23:46:56.445160 ==
5920 23:46:56.448936 Dram Type= 6, Freq= 0, CH_1, rank 1
5921 23:46:56.455466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5922 23:46:56.455560 ==
5923 23:46:56.455629
5924 23:46:56.455693
5925 23:46:56.455753 TX Vref Scan disable
5926 23:46:56.458955 == TX Byte 0 ==
5927 23:46:56.462851 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5928 23:46:56.466104 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5929 23:46:56.469183 == TX Byte 1 ==
5930 23:46:56.472442 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5931 23:46:56.475684 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5932 23:46:56.479390
5933 23:46:56.479476 [DATLAT]
5934 23:46:56.479549 Freq=933, CH1 RK1
5935 23:46:56.479613
5936 23:46:56.482783 DATLAT Default: 0xb
5937 23:46:56.482873 0, 0xFFFF, sum = 0
5938 23:46:56.485739 1, 0xFFFF, sum = 0
5939 23:46:56.485822 2, 0xFFFF, sum = 0
5940 23:46:56.489002 3, 0xFFFF, sum = 0
5941 23:46:56.492269 4, 0xFFFF, sum = 0
5942 23:46:56.492384 5, 0xFFFF, sum = 0
5943 23:46:56.495437 6, 0xFFFF, sum = 0
5944 23:46:56.495527 7, 0xFFFF, sum = 0
5945 23:46:56.499159 8, 0xFFFF, sum = 0
5946 23:46:56.499238 9, 0xFFFF, sum = 0
5947 23:46:56.502113 10, 0x0, sum = 1
5948 23:46:56.502205 11, 0x0, sum = 2
5949 23:46:56.505446 12, 0x0, sum = 3
5950 23:46:56.505534 13, 0x0, sum = 4
5951 23:46:56.505601 best_step = 11
5952 23:46:56.505668
5953 23:46:56.509170 ==
5954 23:46:56.512385 Dram Type= 6, Freq= 0, CH_1, rank 1
5955 23:46:56.515638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5956 23:46:56.515719 ==
5957 23:46:56.515796 RX Vref Scan: 0
5958 23:46:56.515864
5959 23:46:56.518792 RX Vref 0 -> 0, step: 1
5960 23:46:56.518879
5961 23:46:56.522260 RX Delay -45 -> 252, step: 4
5962 23:46:56.525226 iDelay=199, Bit 0, Center 108 (27 ~ 190) 164
5963 23:46:56.532235 iDelay=199, Bit 1, Center 100 (19 ~ 182) 164
5964 23:46:56.535938 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5965 23:46:56.538970 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5966 23:46:56.542293 iDelay=199, Bit 4, Center 100 (19 ~ 182) 164
5967 23:46:56.545451 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5968 23:46:56.552186 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5969 23:46:56.555583 iDelay=199, Bit 7, Center 102 (19 ~ 186) 168
5970 23:46:56.559077 iDelay=199, Bit 8, Center 90 (7 ~ 174) 168
5971 23:46:56.562513 iDelay=199, Bit 9, Center 88 (-1 ~ 178) 180
5972 23:46:56.565364 iDelay=199, Bit 10, Center 100 (15 ~ 186) 172
5973 23:46:56.569004 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5974 23:46:56.575721 iDelay=199, Bit 12, Center 112 (27 ~ 198) 172
5975 23:46:56.579279 iDelay=199, Bit 13, Center 104 (23 ~ 186) 164
5976 23:46:56.582540 iDelay=199, Bit 14, Center 106 (27 ~ 186) 160
5977 23:46:56.585872 iDelay=199, Bit 15, Center 110 (27 ~ 194) 168
5978 23:46:56.585985 ==
5979 23:46:56.588944 Dram Type= 6, Freq= 0, CH_1, rank 1
5980 23:46:56.595785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5981 23:46:56.595870 ==
5982 23:46:56.595941 DQS Delay:
5983 23:46:56.596006 DQS0 = 0, DQS1 = 0
5984 23:46:56.599081 DQM Delay:
5985 23:46:56.599161 DQM0 = 104, DQM1 = 100
5986 23:46:56.602284 DQ Delay:
5987 23:46:56.605537 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5988 23:46:56.608776 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =102
5989 23:46:56.612481 DQ8 =90, DQ9 =88, DQ10 =100, DQ11 =94
5990 23:46:56.615898 DQ12 =112, DQ13 =104, DQ14 =106, DQ15 =110
5991 23:46:56.615981
5992 23:46:56.616046
5993 23:46:56.622406 [DQSOSCAuto] RK1, (LSB)MR18= 0x3105, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 406 ps
5994 23:46:56.625503 CH1 RK1: MR19=505, MR18=3105
5995 23:46:56.632404 CH1_RK1: MR19=0x505, MR18=0x3105, DQSOSC=406, MR23=63, INC=65, DEC=43
5996 23:46:56.635604 [RxdqsGatingPostProcess] freq 933
5997 23:46:56.642280 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5998 23:46:56.645207 best DQS0 dly(2T, 0.5T) = (0, 10)
5999 23:46:56.645294 best DQS1 dly(2T, 0.5T) = (0, 10)
6000 23:46:56.648717 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6001 23:46:56.651988 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6002 23:46:56.655229 best DQS0 dly(2T, 0.5T) = (0, 10)
6003 23:46:56.659037 best DQS1 dly(2T, 0.5T) = (0, 10)
6004 23:46:56.662199 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6005 23:46:56.665319 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6006 23:46:56.668686 Pre-setting of DQS Precalculation
6007 23:46:56.675142 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6008 23:46:56.682216 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6009 23:46:56.688589 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6010 23:46:56.688728
6011 23:46:56.688833
6012 23:46:56.691992 [Calibration Summary] 1866 Mbps
6013 23:46:56.692103 CH 0, Rank 0
6014 23:46:56.695206 SW Impedance : PASS
6015 23:46:56.698382 DUTY Scan : NO K
6016 23:46:56.698465 ZQ Calibration : PASS
6017 23:46:56.701922 Jitter Meter : NO K
6018 23:46:56.704922 CBT Training : PASS
6019 23:46:56.705003 Write leveling : PASS
6020 23:46:56.708714 RX DQS gating : PASS
6021 23:46:56.711988 RX DQ/DQS(RDDQC) : PASS
6022 23:46:56.712071 TX DQ/DQS : PASS
6023 23:46:56.715193 RX DATLAT : PASS
6024 23:46:56.715309 RX DQ/DQS(Engine): PASS
6025 23:46:56.718451 TX OE : NO K
6026 23:46:56.718530 All Pass.
6027 23:46:56.718606
6028 23:46:56.721462 CH 0, Rank 1
6029 23:46:56.721545 SW Impedance : PASS
6030 23:46:56.725120 DUTY Scan : NO K
6031 23:46:56.728574 ZQ Calibration : PASS
6032 23:46:56.728662 Jitter Meter : NO K
6033 23:46:56.731902 CBT Training : PASS
6034 23:46:56.734787 Write leveling : PASS
6035 23:46:56.734876 RX DQS gating : PASS
6036 23:46:56.738462 RX DQ/DQS(RDDQC) : PASS
6037 23:46:56.741716 TX DQ/DQS : PASS
6038 23:46:56.741834 RX DATLAT : PASS
6039 23:46:56.744947 RX DQ/DQS(Engine): PASS
6040 23:46:56.748190 TX OE : NO K
6041 23:46:56.748303 All Pass.
6042 23:46:56.748398
6043 23:46:56.748509 CH 1, Rank 0
6044 23:46:56.751811 SW Impedance : PASS
6045 23:46:56.754806 DUTY Scan : NO K
6046 23:46:56.754895 ZQ Calibration : PASS
6047 23:46:56.758188 Jitter Meter : NO K
6048 23:46:56.761426 CBT Training : PASS
6049 23:46:56.761516 Write leveling : PASS
6050 23:46:56.764680 RX DQS gating : PASS
6051 23:46:56.768509 RX DQ/DQS(RDDQC) : PASS
6052 23:46:56.768609 TX DQ/DQS : PASS
6053 23:46:56.771858 RX DATLAT : PASS
6054 23:46:56.771948 RX DQ/DQS(Engine): PASS
6055 23:46:56.774749 TX OE : NO K
6056 23:46:56.774834 All Pass.
6057 23:46:56.774900
6058 23:46:56.778285 CH 1, Rank 1
6059 23:46:56.778364 SW Impedance : PASS
6060 23:46:56.781293 DUTY Scan : NO K
6061 23:46:56.785030 ZQ Calibration : PASS
6062 23:46:56.785143 Jitter Meter : NO K
6063 23:46:56.788147 CBT Training : PASS
6064 23:46:56.791642 Write leveling : PASS
6065 23:46:56.791757 RX DQS gating : PASS
6066 23:46:56.794597 RX DQ/DQS(RDDQC) : PASS
6067 23:46:56.798161 TX DQ/DQS : PASS
6068 23:46:56.798239 RX DATLAT : PASS
6069 23:46:56.801375 RX DQ/DQS(Engine): PASS
6070 23:46:56.804604 TX OE : NO K
6071 23:46:56.804692 All Pass.
6072 23:46:56.804765
6073 23:46:56.804850 DramC Write-DBI off
6074 23:46:56.807858 PER_BANK_REFRESH: Hybrid Mode
6075 23:46:56.811071 TX_TRACKING: ON
6076 23:46:56.818263 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6077 23:46:56.821330 [FAST_K] Save calibration result to emmc
6078 23:46:56.828264 dramc_set_vcore_voltage set vcore to 650000
6079 23:46:56.828389 Read voltage for 400, 6
6080 23:46:56.831442 Vio18 = 0
6081 23:46:56.831530 Vcore = 650000
6082 23:46:56.831601 Vdram = 0
6083 23:46:56.834512 Vddq = 0
6084 23:46:56.834591 Vmddr = 0
6085 23:46:56.838163 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6086 23:46:56.844678 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6087 23:46:56.848522 MEM_TYPE=3, freq_sel=20
6088 23:46:56.848607 sv_algorithm_assistance_LP4_800
6089 23:46:56.854495 ============ PULL DRAM RESETB DOWN ============
6090 23:46:56.858188 ========== PULL DRAM RESETB DOWN end =========
6091 23:46:56.861191 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6092 23:46:56.864740 ===================================
6093 23:46:56.867687 LPDDR4 DRAM CONFIGURATION
6094 23:46:56.871206 ===================================
6095 23:46:56.874378 EX_ROW_EN[0] = 0x0
6096 23:46:56.874487 EX_ROW_EN[1] = 0x0
6097 23:46:56.877577 LP4Y_EN = 0x0
6098 23:46:56.877670 WORK_FSP = 0x0
6099 23:46:56.881414 WL = 0x2
6100 23:46:56.881497 RL = 0x2
6101 23:46:56.884637 BL = 0x2
6102 23:46:56.884718 RPST = 0x0
6103 23:46:56.887666 RD_PRE = 0x0
6104 23:46:56.887744 WR_PRE = 0x1
6105 23:46:56.891272 WR_PST = 0x0
6106 23:46:56.891369 DBI_WR = 0x0
6107 23:46:56.894237 DBI_RD = 0x0
6108 23:46:56.894347 OTF = 0x1
6109 23:46:56.897639 ===================================
6110 23:46:56.900812 ===================================
6111 23:46:56.904662 ANA top config
6112 23:46:56.907960 ===================================
6113 23:46:56.911325 DLL_ASYNC_EN = 0
6114 23:46:56.911407 ALL_SLAVE_EN = 1
6115 23:46:56.914693 NEW_RANK_MODE = 1
6116 23:46:56.917935 DLL_IDLE_MODE = 1
6117 23:46:56.921181 LP45_APHY_COMB_EN = 1
6118 23:46:56.924402 TX_ODT_DIS = 1
6119 23:46:56.924484 NEW_8X_MODE = 1
6120 23:46:56.927609 ===================================
6121 23:46:56.930919 ===================================
6122 23:46:56.934009 data_rate = 800
6123 23:46:56.937280 CKR = 1
6124 23:46:56.940974 DQ_P2S_RATIO = 4
6125 23:46:56.944164 ===================================
6126 23:46:56.947637 CA_P2S_RATIO = 4
6127 23:46:56.950659 DQ_CA_OPEN = 0
6128 23:46:56.950743 DQ_SEMI_OPEN = 1
6129 23:46:56.954257 CA_SEMI_OPEN = 1
6130 23:46:56.957243 CA_FULL_RATE = 0
6131 23:46:56.961168 DQ_CKDIV4_EN = 0
6132 23:46:56.964021 CA_CKDIV4_EN = 1
6133 23:46:56.967158 CA_PREDIV_EN = 0
6134 23:46:56.967251 PH8_DLY = 0
6135 23:46:56.970867 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6136 23:46:56.973718 DQ_AAMCK_DIV = 0
6137 23:46:56.977187 CA_AAMCK_DIV = 0
6138 23:46:56.980824 CA_ADMCK_DIV = 4
6139 23:46:56.983816 DQ_TRACK_CA_EN = 0
6140 23:46:56.983909 CA_PICK = 800
6141 23:46:56.986998 CA_MCKIO = 400
6142 23:46:56.990824 MCKIO_SEMI = 400
6143 23:46:56.994013 PLL_FREQ = 3016
6144 23:46:56.997246 DQ_UI_PI_RATIO = 32
6145 23:46:57.000712 CA_UI_PI_RATIO = 32
6146 23:46:57.003968 ===================================
6147 23:46:57.007655 ===================================
6148 23:46:57.010667 memory_type:LPDDR4
6149 23:46:57.010801 GP_NUM : 10
6150 23:46:57.014321 SRAM_EN : 1
6151 23:46:57.014416 MD32_EN : 0
6152 23:46:57.016892 ===================================
6153 23:46:57.020610 [ANA_INIT] >>>>>>>>>>>>>>
6154 23:46:57.024029 <<<<<< [CONFIGURE PHASE]: ANA_TX
6155 23:46:57.026807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6156 23:46:57.030701 ===================================
6157 23:46:57.033875 data_rate = 800,PCW = 0X7400
6158 23:46:57.037166 ===================================
6159 23:46:57.040641 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6160 23:46:57.043502 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6161 23:46:57.056875 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6162 23:46:57.060449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6163 23:46:57.063633 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6164 23:46:57.066717 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6165 23:46:57.070314 [ANA_INIT] flow start
6166 23:46:57.073425 [ANA_INIT] PLL >>>>>>>>
6167 23:46:57.073628 [ANA_INIT] PLL <<<<<<<<
6168 23:46:57.076683 [ANA_INIT] MIDPI >>>>>>>>
6169 23:46:57.080254 [ANA_INIT] MIDPI <<<<<<<<
6170 23:46:57.080444 [ANA_INIT] DLL >>>>>>>>
6171 23:46:57.083254 [ANA_INIT] flow end
6172 23:46:57.086776 ============ LP4 DIFF to SE enter ============
6173 23:46:57.093200 ============ LP4 DIFF to SE exit ============
6174 23:46:57.093348 [ANA_INIT] <<<<<<<<<<<<<
6175 23:46:57.096776 [Flow] Enable top DCM control >>>>>
6176 23:46:57.099836 [Flow] Enable top DCM control <<<<<
6177 23:46:57.103100 Enable DLL master slave shuffle
6178 23:46:57.109976 ==============================================================
6179 23:46:57.110066 Gating Mode config
6180 23:46:57.116704 ==============================================================
6181 23:46:57.119780 Config description:
6182 23:46:57.126968 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6183 23:46:57.133221 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6184 23:46:57.139592 SELPH_MODE 0: By rank 1: By Phase
6185 23:46:57.146642 ==============================================================
6186 23:46:57.146727 GAT_TRACK_EN = 0
6187 23:46:57.149702 RX_GATING_MODE = 2
6188 23:46:57.152859 RX_GATING_TRACK_MODE = 2
6189 23:46:57.156732 SELPH_MODE = 1
6190 23:46:57.159897 PICG_EARLY_EN = 1
6191 23:46:57.162922 VALID_LAT_VALUE = 1
6192 23:46:57.169399 ==============================================================
6193 23:46:57.173225 Enter into Gating configuration >>>>
6194 23:46:57.176396 Exit from Gating configuration <<<<
6195 23:46:57.179695 Enter into DVFS_PRE_config >>>>>
6196 23:46:57.189448 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6197 23:46:57.193041 Exit from DVFS_PRE_config <<<<<
6198 23:46:57.196317 Enter into PICG configuration >>>>
6199 23:46:57.199315 Exit from PICG configuration <<<<
6200 23:46:57.203005 [RX_INPUT] configuration >>>>>
6201 23:46:57.203091 [RX_INPUT] configuration <<<<<
6202 23:46:57.209646 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6203 23:46:57.216239 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6204 23:46:57.222770 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6205 23:46:57.226192 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6206 23:46:57.232492 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6207 23:46:57.239523 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6208 23:46:57.242876 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6209 23:46:57.245666 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6210 23:46:57.252355 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6211 23:46:57.255497 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6212 23:46:57.259043 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6213 23:46:57.265545 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6214 23:46:57.269091 ===================================
6215 23:46:57.269177 LPDDR4 DRAM CONFIGURATION
6216 23:46:57.272374 ===================================
6217 23:46:57.275540 EX_ROW_EN[0] = 0x0
6218 23:46:57.278738 EX_ROW_EN[1] = 0x0
6219 23:46:57.278827 LP4Y_EN = 0x0
6220 23:46:57.282057 WORK_FSP = 0x0
6221 23:46:57.282136 WL = 0x2
6222 23:46:57.285829 RL = 0x2
6223 23:46:57.285937 BL = 0x2
6224 23:46:57.288929 RPST = 0x0
6225 23:46:57.289051 RD_PRE = 0x0
6226 23:46:57.292461 WR_PRE = 0x1
6227 23:46:57.292572 WR_PST = 0x0
6228 23:46:57.295572 DBI_WR = 0x0
6229 23:46:57.295671 DBI_RD = 0x0
6230 23:46:57.299234 OTF = 0x1
6231 23:46:57.302379 ===================================
6232 23:46:57.305616 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6233 23:46:57.308822 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6234 23:46:57.315815 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6235 23:46:57.318807 ===================================
6236 23:46:57.318915 LPDDR4 DRAM CONFIGURATION
6237 23:46:57.322267 ===================================
6238 23:46:57.325837 EX_ROW_EN[0] = 0x10
6239 23:46:57.325918 EX_ROW_EN[1] = 0x0
6240 23:46:57.329056 LP4Y_EN = 0x0
6241 23:46:57.331907 WORK_FSP = 0x0
6242 23:46:57.331991 WL = 0x2
6243 23:46:57.335103 RL = 0x2
6244 23:46:57.335184 BL = 0x2
6245 23:46:57.338932 RPST = 0x0
6246 23:46:57.339016 RD_PRE = 0x0
6247 23:46:57.342098 WR_PRE = 0x1
6248 23:46:57.342180 WR_PST = 0x0
6249 23:46:57.345387 DBI_WR = 0x0
6250 23:46:57.345472 DBI_RD = 0x0
6251 23:46:57.348608 OTF = 0x1
6252 23:46:57.352592 ===================================
6253 23:46:57.355828 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6254 23:46:57.360950 nWR fixed to 30
6255 23:46:57.364027 [ModeRegInit_LP4] CH0 RK0
6256 23:46:57.364106 [ModeRegInit_LP4] CH0 RK1
6257 23:46:57.367751 [ModeRegInit_LP4] CH1 RK0
6258 23:46:57.370695 [ModeRegInit_LP4] CH1 RK1
6259 23:46:57.370780 match AC timing 19
6260 23:46:57.377485 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6261 23:46:57.380672 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6262 23:46:57.383830 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6263 23:46:57.390930 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6264 23:46:57.394261 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6265 23:46:57.394346 ==
6266 23:46:57.397413 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 23:46:57.400987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 23:46:57.401069 ==
6269 23:46:57.407665 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6270 23:46:57.414082 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6271 23:46:57.417360 [CA 0] Center 36 (8~64) winsize 57
6272 23:46:57.420722 [CA 1] Center 36 (8~64) winsize 57
6273 23:46:57.423812 [CA 2] Center 36 (8~64) winsize 57
6274 23:46:57.423896 [CA 3] Center 36 (8~64) winsize 57
6275 23:46:57.427605 [CA 4] Center 36 (8~64) winsize 57
6276 23:46:57.431000 [CA 5] Center 36 (8~64) winsize 57
6277 23:46:57.431087
6278 23:46:57.437450 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6279 23:46:57.437533
6280 23:46:57.440435 [CATrainingPosCal] consider 1 rank data
6281 23:46:57.444153 u2DelayCellTimex100 = 270/100 ps
6282 23:46:57.446939 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6283 23:46:57.450278 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6284 23:46:57.454002 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 23:46:57.457340 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 23:46:57.460685 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 23:46:57.464011 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 23:46:57.464095
6289 23:46:57.467237 CA PerBit enable=1, Macro0, CA PI delay=36
6290 23:46:57.467315
6291 23:46:57.470944 [CBTSetCACLKResult] CA Dly = 36
6292 23:46:57.473851 CS Dly: 1 (0~32)
6293 23:46:57.473964 ==
6294 23:46:57.477237 Dram Type= 6, Freq= 0, CH_0, rank 1
6295 23:46:57.480863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6296 23:46:57.480946 ==
6297 23:46:57.487205 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6298 23:46:57.490881 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6299 23:46:57.493758 [CA 0] Center 36 (8~64) winsize 57
6300 23:46:57.497609 [CA 1] Center 36 (8~64) winsize 57
6301 23:46:57.500871 [CA 2] Center 36 (8~64) winsize 57
6302 23:46:57.504094 [CA 3] Center 36 (8~64) winsize 57
6303 23:46:57.507152 [CA 4] Center 36 (8~64) winsize 57
6304 23:46:57.510715 [CA 5] Center 36 (8~64) winsize 57
6305 23:46:57.510794
6306 23:46:57.513766 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6307 23:46:57.513853
6308 23:46:57.517520 [CATrainingPosCal] consider 2 rank data
6309 23:46:57.520740 u2DelayCellTimex100 = 270/100 ps
6310 23:46:57.523889 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 23:46:57.527026 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 23:46:57.530227 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 23:46:57.537247 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 23:46:57.540316 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 23:46:57.543834 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 23:46:57.543916
6317 23:46:57.547023 CA PerBit enable=1, Macro0, CA PI delay=36
6318 23:46:57.547104
6319 23:46:57.550434 [CBTSetCACLKResult] CA Dly = 36
6320 23:46:57.550514 CS Dly: 1 (0~32)
6321 23:46:57.550579
6322 23:46:57.553520 ----->DramcWriteLeveling(PI) begin...
6323 23:46:57.553598 ==
6324 23:46:57.557218 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 23:46:57.563705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 23:46:57.563794 ==
6327 23:46:57.566922 Write leveling (Byte 0): 40 => 8
6328 23:46:57.570243 Write leveling (Byte 1): 40 => 8
6329 23:46:57.570334 DramcWriteLeveling(PI) end<-----
6330 23:46:57.570402
6331 23:46:57.573833 ==
6332 23:46:57.577317 Dram Type= 6, Freq= 0, CH_0, rank 0
6333 23:46:57.580313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6334 23:46:57.580432 ==
6335 23:46:57.583660 [Gating] SW mode calibration
6336 23:46:57.590106 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6337 23:46:57.593688 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6338 23:46:57.600481 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6339 23:46:57.603615 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6340 23:46:57.606756 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 23:46:57.613601 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6342 23:46:57.616912 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6343 23:46:57.620323 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6344 23:46:57.627119 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 23:46:57.630377 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 23:46:57.633629 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 23:46:57.636884 Total UI for P1: 0, mck2ui 16
6348 23:46:57.640118 best dqsien dly found for B0: ( 0, 14, 24)
6349 23:46:57.643530 Total UI for P1: 0, mck2ui 16
6350 23:46:57.646760 best dqsien dly found for B1: ( 0, 14, 24)
6351 23:46:57.650260 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6352 23:46:57.653180 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6353 23:46:57.653265
6354 23:46:57.660253 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6355 23:46:57.663421 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6356 23:46:57.663502 [Gating] SW calibration Done
6357 23:46:57.666643 ==
6358 23:46:57.669811 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 23:46:57.673395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 23:46:57.673504 ==
6361 23:46:57.673579 RX Vref Scan: 0
6362 23:46:57.673652
6363 23:46:57.676543 RX Vref 0 -> 0, step: 1
6364 23:46:57.676621
6365 23:46:57.679756 RX Delay -410 -> 252, step: 16
6366 23:46:57.683194 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6367 23:46:57.686685 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6368 23:46:57.693286 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6369 23:46:57.696671 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6370 23:46:57.699752 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6371 23:46:57.703004 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6372 23:46:57.710233 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6373 23:46:57.713072 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6374 23:46:57.716608 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6375 23:46:57.720056 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6376 23:46:57.730494 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6377 23:46:57.730600 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6378 23:46:57.733044 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6379 23:46:57.736749 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6380 23:46:57.743266 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6381 23:46:57.746531 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6382 23:46:57.746615 ==
6383 23:46:57.749786 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 23:46:57.752943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 23:46:57.753023 ==
6386 23:46:57.756709 DQS Delay:
6387 23:46:57.756815 DQS0 = 27, DQS1 = 35
6388 23:46:57.759789 DQM Delay:
6389 23:46:57.759874 DQM0 = 9, DQM1 = 11
6390 23:46:57.759940 DQ Delay:
6391 23:46:57.763413 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6392 23:46:57.766656 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24
6393 23:46:57.769908 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6394 23:46:57.773013 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6395 23:46:57.773092
6396 23:46:57.773156
6397 23:46:57.773224 ==
6398 23:46:57.776310 Dram Type= 6, Freq= 0, CH_0, rank 0
6399 23:46:57.780131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6400 23:46:57.783466 ==
6401 23:46:57.783558
6402 23:46:57.783624
6403 23:46:57.783712 TX Vref Scan disable
6404 23:46:57.786480 == TX Byte 0 ==
6405 23:46:57.790091 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6406 23:46:57.793023 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6407 23:46:57.796408 == TX Byte 1 ==
6408 23:46:57.799855 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6409 23:46:57.803068 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6410 23:46:57.803181 ==
6411 23:46:57.806656 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 23:46:57.809928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 23:46:57.812885 ==
6414 23:46:57.812992
6415 23:46:57.813084
6416 23:46:57.813183 TX Vref Scan disable
6417 23:46:57.816201 == TX Byte 0 ==
6418 23:46:57.819827 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6419 23:46:57.822780 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6420 23:46:57.826209 == TX Byte 1 ==
6421 23:46:57.829732 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6422 23:46:57.833200 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6423 23:46:57.833312
6424 23:46:57.836248 [DATLAT]
6425 23:46:57.836360 Freq=400, CH0 RK0
6426 23:46:57.836427
6427 23:46:57.840014 DATLAT Default: 0xf
6428 23:46:57.840117 0, 0xFFFF, sum = 0
6429 23:46:57.842866 1, 0xFFFF, sum = 0
6430 23:46:57.842946 2, 0xFFFF, sum = 0
6431 23:46:57.846093 3, 0xFFFF, sum = 0
6432 23:46:57.846176 4, 0xFFFF, sum = 0
6433 23:46:57.849402 5, 0xFFFF, sum = 0
6434 23:46:57.849476 6, 0xFFFF, sum = 0
6435 23:46:57.853058 7, 0xFFFF, sum = 0
6436 23:46:57.853129 8, 0xFFFF, sum = 0
6437 23:46:57.856182 9, 0xFFFF, sum = 0
6438 23:46:57.856286 10, 0xFFFF, sum = 0
6439 23:46:57.859454 11, 0xFFFF, sum = 0
6440 23:46:57.862883 12, 0xFFFF, sum = 0
6441 23:46:57.862970 13, 0x0, sum = 1
6442 23:46:57.863038 14, 0x0, sum = 2
6443 23:46:57.866426 15, 0x0, sum = 3
6444 23:46:57.866505 16, 0x0, sum = 4
6445 23:46:57.869420 best_step = 14
6446 23:46:57.869494
6447 23:46:57.869557 ==
6448 23:46:57.872581 Dram Type= 6, Freq= 0, CH_0, rank 0
6449 23:46:57.875808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6450 23:46:57.875920 ==
6451 23:46:57.879727 RX Vref Scan: 1
6452 23:46:57.879832
6453 23:46:57.879927 RX Vref 0 -> 0, step: 1
6454 23:46:57.880022
6455 23:46:57.882856 RX Delay -311 -> 252, step: 8
6456 23:46:57.882970
6457 23:46:57.885984 Set Vref, RX VrefLevel [Byte0]: 56
6458 23:46:57.889181 [Byte1]: 54
6459 23:46:57.894139
6460 23:46:57.894221 Final RX Vref Byte 0 = 56 to rank0
6461 23:46:57.897488 Final RX Vref Byte 1 = 54 to rank0
6462 23:46:57.900677 Final RX Vref Byte 0 = 56 to rank1
6463 23:46:57.904590 Final RX Vref Byte 1 = 54 to rank1==
6464 23:46:57.907590 Dram Type= 6, Freq= 0, CH_0, rank 0
6465 23:46:57.911195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 23:46:57.914056 ==
6467 23:46:57.914137 DQS Delay:
6468 23:46:57.914208 DQS0 = 28, DQS1 = 36
6469 23:46:57.917561 DQM Delay:
6470 23:46:57.917641 DQM0 = 10, DQM1 = 13
6471 23:46:57.920858 DQ Delay:
6472 23:46:57.924156 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6473 23:46:57.924244 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6474 23:46:57.927413 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6475 23:46:57.930984 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6476 23:46:57.931068
6477 23:46:57.931133
6478 23:46:57.940813 [DQSOSCAuto] RK0, (LSB)MR18= 0xccb9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6479 23:46:57.944168 CH0 RK0: MR19=C0C, MR18=CCB9
6480 23:46:57.950699 CH0_RK0: MR19=0xC0C, MR18=0xCCB9, DQSOSC=384, MR23=63, INC=400, DEC=267
6481 23:46:57.950779 ==
6482 23:46:57.953862 Dram Type= 6, Freq= 0, CH_0, rank 1
6483 23:46:57.957604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6484 23:46:57.957691 ==
6485 23:46:57.960377 [Gating] SW mode calibration
6486 23:46:57.966781 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6487 23:46:57.973889 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6488 23:46:57.976941 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6489 23:46:57.980561 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6490 23:46:57.986914 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 23:46:57.990184 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6492 23:46:57.993465 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6493 23:46:58.000227 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6494 23:46:58.003304 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 23:46:58.007083 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 23:46:58.010287 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 23:46:58.013571 Total UI for P1: 0, mck2ui 16
6498 23:46:58.016825 best dqsien dly found for B0: ( 0, 14, 24)
6499 23:46:58.020280 Total UI for P1: 0, mck2ui 16
6500 23:46:58.023304 best dqsien dly found for B1: ( 0, 14, 24)
6501 23:46:58.027134 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6502 23:46:58.033984 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6503 23:46:58.034082
6504 23:46:58.036552 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6505 23:46:58.040220 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6506 23:46:58.043590 [Gating] SW calibration Done
6507 23:46:58.043703 ==
6508 23:46:58.046839 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 23:46:58.050218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 23:46:58.050330 ==
6511 23:46:58.053571 RX Vref Scan: 0
6512 23:46:58.053671
6513 23:46:58.053766 RX Vref 0 -> 0, step: 1
6514 23:46:58.053860
6515 23:46:58.056577 RX Delay -410 -> 252, step: 16
6516 23:46:58.060164 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6517 23:46:58.066578 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6518 23:46:58.070122 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6519 23:46:58.073467 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6520 23:46:58.076671 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6521 23:46:58.083161 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6522 23:46:58.086721 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6523 23:46:58.090262 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6524 23:46:58.093132 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6525 23:46:58.100256 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6526 23:46:58.103479 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6527 23:46:58.106690 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6528 23:46:58.110112 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6529 23:46:58.116947 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6530 23:46:58.120202 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6531 23:46:58.123350 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6532 23:46:58.123445 ==
6533 23:46:58.126620 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 23:46:58.129779 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 23:46:58.133055 ==
6536 23:46:58.133157 DQS Delay:
6537 23:46:58.133225 DQS0 = 19, DQS1 = 35
6538 23:46:58.137116 DQM Delay:
6539 23:46:58.137227 DQM0 = 6, DQM1 = 11
6540 23:46:58.140032 DQ Delay:
6541 23:46:58.140136 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6542 23:46:58.143201 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6543 23:46:58.146433 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6544 23:46:58.149711 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6545 23:46:58.149788
6546 23:46:58.149852
6547 23:46:58.149932 ==
6548 23:46:58.153392 Dram Type= 6, Freq= 0, CH_0, rank 1
6549 23:46:58.159735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6550 23:46:58.159813 ==
6551 23:46:58.159877
6552 23:46:58.159950
6553 23:46:58.163043 TX Vref Scan disable
6554 23:46:58.163118 == TX Byte 0 ==
6555 23:46:58.166262 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6556 23:46:58.169635 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6557 23:46:58.172819 == TX Byte 1 ==
6558 23:46:58.176270 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6559 23:46:58.179514 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6560 23:46:58.182961 ==
6561 23:46:58.183069 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 23:46:58.189283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 23:46:58.189364 ==
6564 23:46:58.189430
6565 23:46:58.189490
6566 23:46:58.192774 TX Vref Scan disable
6567 23:46:58.192860 == TX Byte 0 ==
6568 23:46:58.196173 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6569 23:46:58.199681 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6570 23:46:58.202916 == TX Byte 1 ==
6571 23:46:58.205995 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6572 23:46:58.209767 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6573 23:46:58.213037
6574 23:46:58.213122 [DATLAT]
6575 23:46:58.213189 Freq=400, CH0 RK1
6576 23:46:58.213252
6577 23:46:58.215991 DATLAT Default: 0xe
6578 23:46:58.216075 0, 0xFFFF, sum = 0
6579 23:46:58.219887 1, 0xFFFF, sum = 0
6580 23:46:58.219974 2, 0xFFFF, sum = 0
6581 23:46:58.223060 3, 0xFFFF, sum = 0
6582 23:46:58.223147 4, 0xFFFF, sum = 0
6583 23:46:58.226270 5, 0xFFFF, sum = 0
6584 23:46:58.226357 6, 0xFFFF, sum = 0
6585 23:46:58.229546 7, 0xFFFF, sum = 0
6586 23:46:58.232588 8, 0xFFFF, sum = 0
6587 23:46:58.232679 9, 0xFFFF, sum = 0
6588 23:46:58.236017 10, 0xFFFF, sum = 0
6589 23:46:58.236103 11, 0xFFFF, sum = 0
6590 23:46:58.239647 12, 0xFFFF, sum = 0
6591 23:46:58.239733 13, 0x0, sum = 1
6592 23:46:58.242989 14, 0x0, sum = 2
6593 23:46:58.243076 15, 0x0, sum = 3
6594 23:46:58.246130 16, 0x0, sum = 4
6595 23:46:58.246216 best_step = 14
6596 23:46:58.246295
6597 23:46:58.246399 ==
6598 23:46:58.249305 Dram Type= 6, Freq= 0, CH_0, rank 1
6599 23:46:58.252558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6600 23:46:58.252644 ==
6601 23:46:58.256460 RX Vref Scan: 0
6602 23:46:58.256544
6603 23:46:58.259615 RX Vref 0 -> 0, step: 1
6604 23:46:58.259700
6605 23:46:58.259766 RX Delay -311 -> 252, step: 8
6606 23:46:58.267837 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6607 23:46:58.271110 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6608 23:46:58.274933 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6609 23:46:58.278186 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6610 23:46:58.284573 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6611 23:46:58.288244 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6612 23:46:58.291467 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6613 23:46:58.294654 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6614 23:46:58.301114 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6615 23:46:58.304459 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6616 23:46:58.308222 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6617 23:46:58.311283 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6618 23:46:58.317904 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6619 23:46:58.321386 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6620 23:46:58.325013 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6621 23:46:58.327983 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6622 23:46:58.331819 ==
6623 23:46:58.334612 Dram Type= 6, Freq= 0, CH_0, rank 1
6624 23:46:58.337746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 23:46:58.337832 ==
6626 23:46:58.337901 DQS Delay:
6627 23:46:58.341084 DQS0 = 24, DQS1 = 32
6628 23:46:58.341169 DQM Delay:
6629 23:46:58.344323 DQM0 = 8, DQM1 = 9
6630 23:46:58.344415 DQ Delay:
6631 23:46:58.348627 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6632 23:46:58.351495 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6633 23:46:58.354787 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6634 23:46:58.357990 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
6635 23:46:58.358075
6636 23:46:58.358142
6637 23:46:58.364305 [DQSOSCAuto] RK1, (LSB)MR18= 0xb959, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6638 23:46:58.367540 CH0 RK1: MR19=C0C, MR18=B959
6639 23:46:58.374818 CH0_RK1: MR19=0xC0C, MR18=0xB959, DQSOSC=386, MR23=63, INC=396, DEC=264
6640 23:46:58.377910 [RxdqsGatingPostProcess] freq 400
6641 23:46:58.381327 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6642 23:46:58.384359 best DQS0 dly(2T, 0.5T) = (0, 10)
6643 23:46:58.387425 best DQS1 dly(2T, 0.5T) = (0, 10)
6644 23:46:58.390775 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6645 23:46:58.394105 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6646 23:46:58.397350 best DQS0 dly(2T, 0.5T) = (0, 10)
6647 23:46:58.401116 best DQS1 dly(2T, 0.5T) = (0, 10)
6648 23:46:58.404259 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6649 23:46:58.407443 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6650 23:46:58.411019 Pre-setting of DQS Precalculation
6651 23:46:58.414446 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6652 23:46:58.414531 ==
6653 23:46:58.417562 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 23:46:58.424517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 23:46:58.424603 ==
6656 23:46:58.427710 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6657 23:46:58.434495 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6658 23:46:58.437459 [CA 0] Center 36 (8~64) winsize 57
6659 23:46:58.440863 [CA 1] Center 36 (8~64) winsize 57
6660 23:46:58.444467 [CA 2] Center 36 (8~64) winsize 57
6661 23:46:58.447802 [CA 3] Center 36 (8~64) winsize 57
6662 23:46:58.451226 [CA 4] Center 36 (8~64) winsize 57
6663 23:46:58.454237 [CA 5] Center 36 (8~64) winsize 57
6664 23:46:58.454361
6665 23:46:58.457456 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6666 23:46:58.457578
6667 23:46:58.461091 [CATrainingPosCal] consider 1 rank data
6668 23:46:58.464236 u2DelayCellTimex100 = 270/100 ps
6669 23:46:58.467408 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6670 23:46:58.470835 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6671 23:46:58.473844 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 23:46:58.477175 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 23:46:58.480426 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 23:46:58.484289 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 23:46:58.487459
6676 23:46:58.490540 CA PerBit enable=1, Macro0, CA PI delay=36
6677 23:46:58.490625
6678 23:46:58.493925 [CBTSetCACLKResult] CA Dly = 36
6679 23:46:58.494010 CS Dly: 1 (0~32)
6680 23:46:58.494078 ==
6681 23:46:58.497208 Dram Type= 6, Freq= 0, CH_1, rank 1
6682 23:46:58.500975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 23:46:58.501061 ==
6684 23:46:58.507327 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6685 23:46:58.514323 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6686 23:46:58.517682 [CA 0] Center 36 (8~64) winsize 57
6687 23:46:58.520708 [CA 1] Center 36 (8~64) winsize 57
6688 23:46:58.524211 [CA 2] Center 36 (8~64) winsize 57
6689 23:46:58.527594 [CA 3] Center 36 (8~64) winsize 57
6690 23:46:58.530660 [CA 4] Center 36 (8~64) winsize 57
6691 23:46:58.530746 [CA 5] Center 36 (8~64) winsize 57
6692 23:46:58.533651
6693 23:46:58.537294 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6694 23:46:58.537379
6695 23:46:58.540473 [CATrainingPosCal] consider 2 rank data
6696 23:46:58.543690 u2DelayCellTimex100 = 270/100 ps
6697 23:46:58.546904 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 23:46:58.550669 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 23:46:58.553735 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 23:46:58.557108 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 23:46:58.560067 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 23:46:58.563747 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 23:46:58.563833
6704 23:46:58.567163 CA PerBit enable=1, Macro0, CA PI delay=36
6705 23:46:58.567274
6706 23:46:58.570795 [CBTSetCACLKResult] CA Dly = 36
6707 23:46:58.573451 CS Dly: 1 (0~32)
6708 23:46:58.573536
6709 23:46:58.577098 ----->DramcWriteLeveling(PI) begin...
6710 23:46:58.577211 ==
6711 23:46:58.579953 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 23:46:58.583881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 23:46:58.583993 ==
6714 23:46:58.587133 Write leveling (Byte 0): 40 => 8
6715 23:46:58.590375 Write leveling (Byte 1): 40 => 8
6716 23:46:58.593861 DramcWriteLeveling(PI) end<-----
6717 23:46:58.593946
6718 23:46:58.594015 ==
6719 23:46:58.597144 Dram Type= 6, Freq= 0, CH_1, rank 0
6720 23:46:58.599864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6721 23:46:58.599949 ==
6722 23:46:58.603563 [Gating] SW mode calibration
6723 23:46:58.610572 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6724 23:46:58.617021 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6725 23:46:58.620510 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6726 23:46:58.623751 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6727 23:46:58.630164 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 23:46:58.633289 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6729 23:46:58.636987 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6730 23:46:58.643338 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6731 23:46:58.646660 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 23:46:58.650007 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 23:46:58.656826 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 23:46:58.659972 Total UI for P1: 0, mck2ui 16
6735 23:46:58.663381 best dqsien dly found for B0: ( 0, 14, 24)
6736 23:46:58.666576 Total UI for P1: 0, mck2ui 16
6737 23:46:58.669697 best dqsien dly found for B1: ( 0, 14, 24)
6738 23:46:58.673005 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6739 23:46:58.676721 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6740 23:46:58.676808
6741 23:46:58.679859 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6742 23:46:58.683024 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6743 23:46:58.686839 [Gating] SW calibration Done
6744 23:46:58.686935 ==
6745 23:46:58.690211 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 23:46:58.692832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 23:46:58.692918 ==
6748 23:46:58.696631 RX Vref Scan: 0
6749 23:46:58.696716
6750 23:46:58.699870 RX Vref 0 -> 0, step: 1
6751 23:46:58.699954
6752 23:46:58.700022 RX Delay -410 -> 252, step: 16
6753 23:46:58.706376 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6754 23:46:58.709812 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6755 23:46:58.713219 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6756 23:46:58.716415 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6757 23:46:58.723177 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6758 23:46:58.726414 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6759 23:46:58.729810 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6760 23:46:58.732951 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6761 23:46:58.739436 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6762 23:46:58.743156 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6763 23:46:58.746283 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6764 23:46:58.749954 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6765 23:46:58.756506 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6766 23:46:58.760018 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6767 23:46:58.762746 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6768 23:46:58.769638 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6769 23:46:58.769725 ==
6770 23:46:58.772686 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 23:46:58.776625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 23:46:58.776717 ==
6773 23:46:58.776784 DQS Delay:
6774 23:46:58.779689 DQS0 = 27, DQS1 = 35
6775 23:46:58.779803 DQM Delay:
6776 23:46:58.783187 DQM0 = 11, DQM1 = 13
6777 23:46:58.783272 DQ Delay:
6778 23:46:58.786141 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6779 23:46:58.789487 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6780 23:46:58.793001 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6781 23:46:58.796165 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6782 23:46:58.796268
6783 23:46:58.796394
6784 23:46:58.796469 ==
6785 23:46:58.799810 Dram Type= 6, Freq= 0, CH_1, rank 0
6786 23:46:58.802839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6787 23:46:58.802926 ==
6788 23:46:58.802993
6789 23:46:58.803056
6790 23:46:58.806128 TX Vref Scan disable
6791 23:46:58.806214 == TX Byte 0 ==
6792 23:46:58.813232 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6793 23:46:58.816076 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6794 23:46:58.816190 == TX Byte 1 ==
6795 23:46:58.822693 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6796 23:46:58.825810 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6797 23:46:58.825896 ==
6798 23:46:58.829435 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 23:46:58.832476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 23:46:58.832589 ==
6801 23:46:58.832685
6802 23:46:58.832776
6803 23:46:58.835790 TX Vref Scan disable
6804 23:46:58.835902 == TX Byte 0 ==
6805 23:46:58.842843 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6806 23:46:58.845989 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6807 23:46:58.846101 == TX Byte 1 ==
6808 23:46:58.852795 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6809 23:46:58.856049 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6810 23:46:58.856134
6811 23:46:58.856201 [DATLAT]
6812 23:46:58.859190 Freq=400, CH1 RK0
6813 23:46:58.859275
6814 23:46:58.859343 DATLAT Default: 0xf
6815 23:46:58.862950 0, 0xFFFF, sum = 0
6816 23:46:58.863037 1, 0xFFFF, sum = 0
6817 23:46:58.865652 2, 0xFFFF, sum = 0
6818 23:46:58.865738 3, 0xFFFF, sum = 0
6819 23:46:58.868984 4, 0xFFFF, sum = 0
6820 23:46:58.869071 5, 0xFFFF, sum = 0
6821 23:46:58.872490 6, 0xFFFF, sum = 0
6822 23:46:58.872577 7, 0xFFFF, sum = 0
6823 23:46:58.876183 8, 0xFFFF, sum = 0
6824 23:46:58.876270 9, 0xFFFF, sum = 0
6825 23:46:58.879071 10, 0xFFFF, sum = 0
6826 23:46:58.882564 11, 0xFFFF, sum = 0
6827 23:46:58.882651 12, 0xFFFF, sum = 0
6828 23:46:58.885781 13, 0x0, sum = 1
6829 23:46:58.885868 14, 0x0, sum = 2
6830 23:46:58.888998 15, 0x0, sum = 3
6831 23:46:58.889085 16, 0x0, sum = 4
6832 23:46:58.889153 best_step = 14
6833 23:46:58.889216
6834 23:46:58.892246 ==
6835 23:46:58.892331 Dram Type= 6, Freq= 0, CH_1, rank 0
6836 23:46:58.899165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6837 23:46:58.899255 ==
6838 23:46:58.899322 RX Vref Scan: 1
6839 23:46:58.899385
6840 23:46:58.902424 RX Vref 0 -> 0, step: 1
6841 23:46:58.902509
6842 23:46:58.905714 RX Delay -311 -> 252, step: 8
6843 23:46:58.905802
6844 23:46:58.908920 Set Vref, RX VrefLevel [Byte0]: 50
6845 23:46:58.912083 [Byte1]: 48
6846 23:46:58.915790
6847 23:46:58.915875 Final RX Vref Byte 0 = 50 to rank0
6848 23:46:58.918859 Final RX Vref Byte 1 = 48 to rank0
6849 23:46:58.922246 Final RX Vref Byte 0 = 50 to rank1
6850 23:46:58.925578 Final RX Vref Byte 1 = 48 to rank1==
6851 23:46:58.928865 Dram Type= 6, Freq= 0, CH_1, rank 0
6852 23:46:58.935416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 23:46:58.935502 ==
6854 23:46:58.935570 DQS Delay:
6855 23:46:58.939036 DQS0 = 32, DQS1 = 32
6856 23:46:58.939146 DQM Delay:
6857 23:46:58.939243 DQM0 = 14, DQM1 = 12
6858 23:46:58.942244 DQ Delay:
6859 23:46:58.945414 DQ0 =16, DQ1 =12, DQ2 =0, DQ3 =12
6860 23:46:58.949201 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6861 23:46:58.949286 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6862 23:46:58.952320 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6863 23:46:58.955429
6864 23:46:58.955513
6865 23:46:58.962038 [DQSOSCAuto] RK0, (LSB)MR18= 0x90c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6866 23:46:58.965571 CH1 RK0: MR19=C0C, MR18=90C9
6867 23:46:58.972119 CH1_RK0: MR19=0xC0C, MR18=0x90C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6868 23:46:58.972205 ==
6869 23:46:58.975569 Dram Type= 6, Freq= 0, CH_1, rank 1
6870 23:46:58.978582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6871 23:46:58.978668 ==
6872 23:46:58.982286 [Gating] SW mode calibration
6873 23:46:58.988806 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6874 23:46:58.995299 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6875 23:46:58.998518 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6876 23:46:59.001658 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6877 23:46:59.008595 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 23:46:59.011890 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6879 23:46:59.015052 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6880 23:46:59.021515 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6881 23:46:59.025209 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 23:46:59.028447 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 23:46:59.034672 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 23:46:59.034757 Total UI for P1: 0, mck2ui 16
6885 23:46:59.041975 best dqsien dly found for B0: ( 0, 14, 24)
6886 23:46:59.042061 Total UI for P1: 0, mck2ui 16
6887 23:46:59.044712 best dqsien dly found for B1: ( 0, 14, 24)
6888 23:46:59.051498 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6889 23:46:59.054981 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6890 23:46:59.055067
6891 23:46:59.058210 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6892 23:46:59.061598 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6893 23:46:59.064812 [Gating] SW calibration Done
6894 23:46:59.064897 ==
6895 23:46:59.068200 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 23:46:59.071480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 23:46:59.071565 ==
6898 23:46:59.075009 RX Vref Scan: 0
6899 23:46:59.075094
6900 23:46:59.075161 RX Vref 0 -> 0, step: 1
6901 23:46:59.075223
6902 23:46:59.078078 RX Delay -410 -> 252, step: 16
6903 23:46:59.081977 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6904 23:46:59.088429 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6905 23:46:59.091630 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6906 23:46:59.094665 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6907 23:46:59.101648 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6908 23:46:59.104635 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6909 23:46:59.108185 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6910 23:46:59.111434 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6911 23:46:59.114672 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6912 23:46:59.121163 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6913 23:46:59.124453 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6914 23:46:59.128442 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6915 23:46:59.131406 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6916 23:46:59.137832 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6917 23:46:59.141036 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6918 23:46:59.144312 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6919 23:46:59.144405 ==
6920 23:46:59.148041 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 23:46:59.154542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 23:46:59.154649 ==
6923 23:46:59.154745 DQS Delay:
6924 23:46:59.158059 DQS0 = 27, DQS1 = 35
6925 23:46:59.158168 DQM Delay:
6926 23:46:59.161503 DQM0 = 12, DQM1 = 13
6927 23:46:59.161610 DQ Delay:
6928 23:46:59.164298 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6929 23:46:59.167525 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6930 23:46:59.167609 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6931 23:46:59.171279 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6932 23:46:59.174317
6933 23:46:59.174394
6934 23:46:59.174459 ==
6935 23:46:59.177463 Dram Type= 6, Freq= 0, CH_1, rank 1
6936 23:46:59.180883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6937 23:46:59.180969 ==
6938 23:46:59.181035
6939 23:46:59.181096
6940 23:46:59.184517 TX Vref Scan disable
6941 23:46:59.184601 == TX Byte 0 ==
6942 23:46:59.187919 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6943 23:46:59.194406 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6944 23:46:59.194500 == TX Byte 1 ==
6945 23:46:59.197602 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6946 23:46:59.204630 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6947 23:46:59.204758 ==
6948 23:46:59.207559 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 23:46:59.211463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 23:46:59.211550 ==
6951 23:46:59.211618
6952 23:46:59.211680
6953 23:46:59.214448 TX Vref Scan disable
6954 23:46:59.214533 == TX Byte 0 ==
6955 23:46:59.217480 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6956 23:46:59.224333 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6957 23:46:59.224426 == TX Byte 1 ==
6958 23:46:59.227581 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6959 23:46:59.234680 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6960 23:46:59.234766
6961 23:46:59.234833 [DATLAT]
6962 23:46:59.234896 Freq=400, CH1 RK1
6963 23:46:59.234956
6964 23:46:59.237546 DATLAT Default: 0xe
6965 23:46:59.237630 0, 0xFFFF, sum = 0
6966 23:46:59.241293 1, 0xFFFF, sum = 0
6967 23:46:59.244559 2, 0xFFFF, sum = 0
6968 23:46:59.244645 3, 0xFFFF, sum = 0
6969 23:46:59.247740 4, 0xFFFF, sum = 0
6970 23:46:59.247853 5, 0xFFFF, sum = 0
6971 23:46:59.250914 6, 0xFFFF, sum = 0
6972 23:46:59.251020 7, 0xFFFF, sum = 0
6973 23:46:59.254206 8, 0xFFFF, sum = 0
6974 23:46:59.254314 9, 0xFFFF, sum = 0
6975 23:46:59.258050 10, 0xFFFF, sum = 0
6976 23:46:59.258159 11, 0xFFFF, sum = 0
6977 23:46:59.260934 12, 0xFFFF, sum = 0
6978 23:46:59.261048 13, 0x0, sum = 1
6979 23:46:59.264182 14, 0x0, sum = 2
6980 23:46:59.264292 15, 0x0, sum = 3
6981 23:46:59.267889 16, 0x0, sum = 4
6982 23:46:59.268009 best_step = 14
6983 23:46:59.268106
6984 23:46:59.268197 ==
6985 23:46:59.271275 Dram Type= 6, Freq= 0, CH_1, rank 1
6986 23:46:59.274445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6987 23:46:59.277691 ==
6988 23:46:59.277777 RX Vref Scan: 0
6989 23:46:59.277844
6990 23:46:59.280860 RX Vref 0 -> 0, step: 1
6991 23:46:59.280945
6992 23:46:59.284576 RX Delay -311 -> 252, step: 8
6993 23:46:59.287353 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6994 23:46:59.294101 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6995 23:46:59.297683 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6996 23:46:59.300948 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6997 23:46:59.304229 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6998 23:46:59.310837 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6999 23:46:59.313891 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
7000 23:46:59.317537 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7001 23:46:59.320509 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
7002 23:46:59.327062 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7003 23:46:59.330912 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7004 23:46:59.334081 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7005 23:46:59.337310 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7006 23:46:59.344029 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7007 23:46:59.347196 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7008 23:46:59.350474 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
7009 23:46:59.350562 ==
7010 23:46:59.353920 Dram Type= 6, Freq= 0, CH_1, rank 1
7011 23:46:59.360808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7012 23:46:59.360921 ==
7013 23:46:59.361016 DQS Delay:
7014 23:46:59.364124 DQS0 = 28, DQS1 = 32
7015 23:46:59.364200 DQM Delay:
7016 23:46:59.364263 DQM0 = 11, DQM1 = 11
7017 23:46:59.367316 DQ Delay:
7018 23:46:59.370895 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7019 23:46:59.370996 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7020 23:46:59.373821 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
7021 23:46:59.377615 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
7022 23:46:59.377693
7023 23:46:59.377756
7024 23:46:59.387100 [DQSOSCAuto] RK1, (LSB)MR18= 0xc657, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
7025 23:46:59.390408 CH1 RK1: MR19=C0C, MR18=C657
7026 23:46:59.397257 CH1_RK1: MR19=0xC0C, MR18=0xC657, DQSOSC=385, MR23=63, INC=398, DEC=265
7027 23:46:59.400136 [RxdqsGatingPostProcess] freq 400
7028 23:46:59.403685 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7029 23:46:59.407483 best DQS0 dly(2T, 0.5T) = (0, 10)
7030 23:46:59.410540 best DQS1 dly(2T, 0.5T) = (0, 10)
7031 23:46:59.413698 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7032 23:46:59.417032 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7033 23:46:59.420492 best DQS0 dly(2T, 0.5T) = (0, 10)
7034 23:46:59.423861 best DQS1 dly(2T, 0.5T) = (0, 10)
7035 23:46:59.427159 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7036 23:46:59.430283 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7037 23:46:59.433939 Pre-setting of DQS Precalculation
7038 23:46:59.436904 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7039 23:46:59.443728 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7040 23:46:59.450620 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7041 23:46:59.453874
7042 23:46:59.453979
7043 23:46:59.454076 [Calibration Summary] 800 Mbps
7044 23:46:59.457138 CH 0, Rank 0
7045 23:46:59.457245 SW Impedance : PASS
7046 23:46:59.460376 DUTY Scan : NO K
7047 23:46:59.463534 ZQ Calibration : PASS
7048 23:46:59.463613 Jitter Meter : NO K
7049 23:46:59.466760 CBT Training : PASS
7050 23:46:59.469979 Write leveling : PASS
7051 23:46:59.470093 RX DQS gating : PASS
7052 23:46:59.473262 RX DQ/DQS(RDDQC) : PASS
7053 23:46:59.476613 TX DQ/DQS : PASS
7054 23:46:59.476717 RX DATLAT : PASS
7055 23:46:59.480413 RX DQ/DQS(Engine): PASS
7056 23:46:59.483352 TX OE : NO K
7057 23:46:59.483457 All Pass.
7058 23:46:59.483552
7059 23:46:59.483645 CH 0, Rank 1
7060 23:46:59.487223 SW Impedance : PASS
7061 23:46:59.490132 DUTY Scan : NO K
7062 23:46:59.490238 ZQ Calibration : PASS
7063 23:46:59.493420 Jitter Meter : NO K
7064 23:46:59.496751 CBT Training : PASS
7065 23:46:59.496838 Write leveling : NO K
7066 23:46:59.499871 RX DQS gating : PASS
7067 23:46:59.499974 RX DQ/DQS(RDDQC) : PASS
7068 23:46:59.503346 TX DQ/DQS : PASS
7069 23:46:59.506812 RX DATLAT : PASS
7070 23:46:59.506918 RX DQ/DQS(Engine): PASS
7071 23:46:59.510236 TX OE : NO K
7072 23:46:59.510339 All Pass.
7073 23:46:59.510437
7074 23:46:59.513194 CH 1, Rank 0
7075 23:46:59.513298 SW Impedance : PASS
7076 23:46:59.516628 DUTY Scan : NO K
7077 23:46:59.519649 ZQ Calibration : PASS
7078 23:46:59.519752 Jitter Meter : NO K
7079 23:46:59.523383 CBT Training : PASS
7080 23:46:59.526459 Write leveling : PASS
7081 23:46:59.526563 RX DQS gating : PASS
7082 23:46:59.530084 RX DQ/DQS(RDDQC) : PASS
7083 23:46:59.533232 TX DQ/DQS : PASS
7084 23:46:59.533310 RX DATLAT : PASS
7085 23:46:59.536669 RX DQ/DQS(Engine): PASS
7086 23:46:59.539745 TX OE : NO K
7087 23:46:59.539850 All Pass.
7088 23:46:59.539957
7089 23:46:59.540052 CH 1, Rank 1
7090 23:46:59.542939 SW Impedance : PASS
7091 23:46:59.546348 DUTY Scan : NO K
7092 23:46:59.546442 ZQ Calibration : PASS
7093 23:46:59.549870 Jitter Meter : NO K
7094 23:46:59.552916 CBT Training : PASS
7095 23:46:59.552991 Write leveling : NO K
7096 23:46:59.556236 RX DQS gating : PASS
7097 23:46:59.556354 RX DQ/DQS(RDDQC) : PASS
7098 23:46:59.559790 TX DQ/DQS : PASS
7099 23:46:59.563236 RX DATLAT : PASS
7100 23:46:59.563340 RX DQ/DQS(Engine): PASS
7101 23:46:59.566243 TX OE : NO K
7102 23:46:59.566328 All Pass.
7103 23:46:59.566395
7104 23:46:59.569549 DramC Write-DBI off
7105 23:46:59.572751 PER_BANK_REFRESH: Hybrid Mode
7106 23:46:59.572843 TX_TRACKING: ON
7107 23:46:59.582997 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7108 23:46:59.586202 [FAST_K] Save calibration result to emmc
7109 23:46:59.589301 dramc_set_vcore_voltage set vcore to 725000
7110 23:46:59.593013 Read voltage for 1600, 0
7111 23:46:59.593095 Vio18 = 0
7112 23:46:59.596295 Vcore = 725000
7113 23:46:59.596393 Vdram = 0
7114 23:46:59.596459 Vddq = 0
7115 23:46:59.596520 Vmddr = 0
7116 23:46:59.602714 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7117 23:46:59.609788 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7118 23:46:59.609875 MEM_TYPE=3, freq_sel=13
7119 23:46:59.612838 sv_algorithm_assistance_LP4_3733
7120 23:46:59.616132 ============ PULL DRAM RESETB DOWN ============
7121 23:46:59.622424 ========== PULL DRAM RESETB DOWN end =========
7122 23:46:59.625952 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7123 23:46:59.629491 ===================================
7124 23:46:59.632818 LPDDR4 DRAM CONFIGURATION
7125 23:46:59.636154 ===================================
7126 23:46:59.636243 EX_ROW_EN[0] = 0x0
7127 23:46:59.639280 EX_ROW_EN[1] = 0x0
7128 23:46:59.639386 LP4Y_EN = 0x0
7129 23:46:59.642659 WORK_FSP = 0x1
7130 23:46:59.642775 WL = 0x5
7131 23:46:59.646126 RL = 0x5
7132 23:46:59.646206 BL = 0x2
7133 23:46:59.649099 RPST = 0x0
7134 23:46:59.649179 RD_PRE = 0x0
7135 23:46:59.652617 WR_PRE = 0x1
7136 23:46:59.655832 WR_PST = 0x1
7137 23:46:59.655915 DBI_WR = 0x0
7138 23:46:59.659196 DBI_RD = 0x0
7139 23:46:59.659275 OTF = 0x1
7140 23:46:59.662405 ===================================
7141 23:46:59.666025 ===================================
7142 23:46:59.666109 ANA top config
7143 23:46:59.669756 ===================================
7144 23:46:59.672463 DLL_ASYNC_EN = 0
7145 23:46:59.675734 ALL_SLAVE_EN = 0
7146 23:46:59.679061 NEW_RANK_MODE = 1
7147 23:46:59.682767 DLL_IDLE_MODE = 1
7148 23:46:59.682893 LP45_APHY_COMB_EN = 1
7149 23:46:59.685936 TX_ODT_DIS = 0
7150 23:46:59.689139 NEW_8X_MODE = 1
7151 23:46:59.692357 ===================================
7152 23:46:59.695632 ===================================
7153 23:46:59.698794 data_rate = 3200
7154 23:46:59.702419 CKR = 1
7155 23:46:59.702537 DQ_P2S_RATIO = 8
7156 23:46:59.705412 ===================================
7157 23:46:59.709071 CA_P2S_RATIO = 8
7158 23:46:59.712212 DQ_CA_OPEN = 0
7159 23:46:59.715474 DQ_SEMI_OPEN = 0
7160 23:46:59.718742 CA_SEMI_OPEN = 0
7161 23:46:59.722767 CA_FULL_RATE = 0
7162 23:46:59.722879 DQ_CKDIV4_EN = 0
7163 23:46:59.725717 CA_CKDIV4_EN = 0
7164 23:46:59.729007 CA_PREDIV_EN = 0
7165 23:46:59.732413 PH8_DLY = 12
7166 23:46:59.735651 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7167 23:46:59.739338 DQ_AAMCK_DIV = 4
7168 23:46:59.739425 CA_AAMCK_DIV = 4
7169 23:46:59.742179 CA_ADMCK_DIV = 4
7170 23:46:59.745705 DQ_TRACK_CA_EN = 0
7171 23:46:59.748962 CA_PICK = 1600
7172 23:46:59.752191 CA_MCKIO = 1600
7173 23:46:59.755831 MCKIO_SEMI = 0
7174 23:46:59.759030 PLL_FREQ = 3068
7175 23:46:59.759107 DQ_UI_PI_RATIO = 32
7176 23:46:59.762160 CA_UI_PI_RATIO = 0
7177 23:46:59.765886 ===================================
7178 23:46:59.769175 ===================================
7179 23:46:59.772091 memory_type:LPDDR4
7180 23:46:59.775254 GP_NUM : 10
7181 23:46:59.775341 SRAM_EN : 1
7182 23:46:59.778893 MD32_EN : 0
7183 23:46:59.782040 ===================================
7184 23:46:59.785318 [ANA_INIT] >>>>>>>>>>>>>>
7185 23:46:59.785407 <<<<<< [CONFIGURE PHASE]: ANA_TX
7186 23:46:59.789124 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7187 23:46:59.792390 ===================================
7188 23:46:59.795562 data_rate = 3200,PCW = 0X7600
7189 23:46:59.798796 ===================================
7190 23:46:59.802146 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7191 23:46:59.809019 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7192 23:46:59.815492 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7193 23:46:59.819108 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7194 23:46:59.822259 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7195 23:46:59.825447 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7196 23:46:59.828695 [ANA_INIT] flow start
7197 23:46:59.828786 [ANA_INIT] PLL >>>>>>>>
7198 23:46:59.832028 [ANA_INIT] PLL <<<<<<<<
7199 23:46:59.835503 [ANA_INIT] MIDPI >>>>>>>>
7200 23:46:59.835611 [ANA_INIT] MIDPI <<<<<<<<
7201 23:46:59.839304 [ANA_INIT] DLL >>>>>>>>
7202 23:46:59.841874 [ANA_INIT] DLL <<<<<<<<
7203 23:46:59.841987 [ANA_INIT] flow end
7204 23:46:59.848726 ============ LP4 DIFF to SE enter ============
7205 23:46:59.852121 ============ LP4 DIFF to SE exit ============
7206 23:46:59.855104 [ANA_INIT] <<<<<<<<<<<<<
7207 23:46:59.858794 [Flow] Enable top DCM control >>>>>
7208 23:46:59.861805 [Flow] Enable top DCM control <<<<<
7209 23:46:59.861884 Enable DLL master slave shuffle
7210 23:46:59.868372 ==============================================================
7211 23:46:59.872079 Gating Mode config
7212 23:46:59.875085 ==============================================================
7213 23:46:59.878786 Config description:
7214 23:46:59.889025 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7215 23:46:59.895592 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7216 23:46:59.898751 SELPH_MODE 0: By rank 1: By Phase
7217 23:46:59.905338 ==============================================================
7218 23:46:59.908443 GAT_TRACK_EN = 1
7219 23:46:59.912388 RX_GATING_MODE = 2
7220 23:46:59.915055 RX_GATING_TRACK_MODE = 2
7221 23:46:59.915157 SELPH_MODE = 1
7222 23:46:59.918764 PICG_EARLY_EN = 1
7223 23:46:59.921916 VALID_LAT_VALUE = 1
7224 23:46:59.928394 ==============================================================
7225 23:46:59.931854 Enter into Gating configuration >>>>
7226 23:46:59.935424 Exit from Gating configuration <<<<
7227 23:46:59.938602 Enter into DVFS_PRE_config >>>>>
7228 23:46:59.948579 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7229 23:46:59.951871 Exit from DVFS_PRE_config <<<<<
7230 23:46:59.955161 Enter into PICG configuration >>>>
7231 23:46:59.958087 Exit from PICG configuration <<<<
7232 23:46:59.961360 [RX_INPUT] configuration >>>>>
7233 23:46:59.964872 [RX_INPUT] configuration <<<<<
7234 23:46:59.968210 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7235 23:46:59.975021 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7236 23:46:59.981438 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7237 23:46:59.988069 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7238 23:46:59.994754 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7239 23:46:59.998282 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7240 23:47:00.005091 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7241 23:47:00.008255 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7242 23:47:00.011461 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7243 23:47:00.014684 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7244 23:47:00.017888 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7245 23:47:00.024900 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7246 23:47:00.028019 ===================================
7247 23:47:00.031038 LPDDR4 DRAM CONFIGURATION
7248 23:47:00.034700 ===================================
7249 23:47:00.034782 EX_ROW_EN[0] = 0x0
7250 23:47:00.038238 EX_ROW_EN[1] = 0x0
7251 23:47:00.038349 LP4Y_EN = 0x0
7252 23:47:00.041486 WORK_FSP = 0x1
7253 23:47:00.041603 WL = 0x5
7254 23:47:00.044727 RL = 0x5
7255 23:47:00.044812 BL = 0x2
7256 23:47:00.048061 RPST = 0x0
7257 23:47:00.048168 RD_PRE = 0x0
7258 23:47:00.051590 WR_PRE = 0x1
7259 23:47:00.051667 WR_PST = 0x1
7260 23:47:00.054454 DBI_WR = 0x0
7261 23:47:00.054541 DBI_RD = 0x0
7262 23:47:00.057721 OTF = 0x1
7263 23:47:00.061535 ===================================
7264 23:47:00.064272 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7265 23:47:00.067878 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7266 23:47:00.074597 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7267 23:47:00.077969 ===================================
7268 23:47:00.078044 LPDDR4 DRAM CONFIGURATION
7269 23:47:00.081224 ===================================
7270 23:47:00.084607 EX_ROW_EN[0] = 0x10
7271 23:47:00.088235 EX_ROW_EN[1] = 0x0
7272 23:47:00.088360 LP4Y_EN = 0x0
7273 23:47:00.091573 WORK_FSP = 0x1
7274 23:47:00.091677 WL = 0x5
7275 23:47:00.094627 RL = 0x5
7276 23:47:00.094707 BL = 0x2
7277 23:47:00.097861 RPST = 0x0
7278 23:47:00.097940 RD_PRE = 0x0
7279 23:47:00.100869 WR_PRE = 0x1
7280 23:47:00.100985 WR_PST = 0x1
7281 23:47:00.104559 DBI_WR = 0x0
7282 23:47:00.104644 DBI_RD = 0x0
7283 23:47:00.107627 OTF = 0x1
7284 23:47:00.111428 ===================================
7285 23:47:00.117705 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7286 23:47:00.117793 ==
7287 23:47:00.120894 Dram Type= 6, Freq= 0, CH_0, rank 0
7288 23:47:00.124711 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7289 23:47:00.124798 ==
7290 23:47:00.128068 [Duty_Offset_Calibration]
7291 23:47:00.128152 B0:2 B1:1 CA:1
7292 23:47:00.128219
7293 23:47:00.131343 [DutyScan_Calibration_Flow] k_type=0
7294 23:47:00.141882
7295 23:47:00.141985 ==CLK 0==
7296 23:47:00.145304 Final CLK duty delay cell = 0
7297 23:47:00.148298 [0] MAX Duty = 5156%(X100), DQS PI = 22
7298 23:47:00.151692 [0] MIN Duty = 4907%(X100), DQS PI = 0
7299 23:47:00.151783 [0] AVG Duty = 5031%(X100)
7300 23:47:00.155561
7301 23:47:00.158600 CH0 CLK Duty spec in!! Max-Min= 249%
7302 23:47:00.161975 [DutyScan_Calibration_Flow] ====Done====
7303 23:47:00.162057
7304 23:47:00.165249 [DutyScan_Calibration_Flow] k_type=1
7305 23:47:00.180635
7306 23:47:00.180755 ==DQS 0 ==
7307 23:47:00.184415 Final DQS duty delay cell = -4
7308 23:47:00.187470 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7309 23:47:00.190940 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7310 23:47:00.194200 [-4] AVG Duty = 4891%(X100)
7311 23:47:00.194280
7312 23:47:00.194346 ==DQS 1 ==
7313 23:47:00.197316 Final DQS duty delay cell = 0
7314 23:47:00.200983 [0] MAX Duty = 5187%(X100), DQS PI = 20
7315 23:47:00.204228 [0] MIN Duty = 5031%(X100), DQS PI = 32
7316 23:47:00.207636 [0] AVG Duty = 5109%(X100)
7317 23:47:00.207747
7318 23:47:00.211303 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7319 23:47:00.211424
7320 23:47:00.214162 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7321 23:47:00.217702 [DutyScan_Calibration_Flow] ====Done====
7322 23:47:00.217782
7323 23:47:00.220481 [DutyScan_Calibration_Flow] k_type=3
7324 23:47:00.238525
7325 23:47:00.238613 ==DQM 0 ==
7326 23:47:00.241723 Final DQM duty delay cell = 0
7327 23:47:00.244977 [0] MAX Duty = 5187%(X100), DQS PI = 26
7328 23:47:00.248109 [0] MIN Duty = 4907%(X100), DQS PI = 56
7329 23:47:00.251872 [0] AVG Duty = 5047%(X100)
7330 23:47:00.251958
7331 23:47:00.252025 ==DQM 1 ==
7332 23:47:00.254884 Final DQM duty delay cell = 0
7333 23:47:00.258160 [0] MAX Duty = 5187%(X100), DQS PI = 2
7334 23:47:00.261351 [0] MIN Duty = 5031%(X100), DQS PI = 48
7335 23:47:00.265142 [0] AVG Duty = 5109%(X100)
7336 23:47:00.265233
7337 23:47:00.268163 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7338 23:47:00.268243
7339 23:47:00.271767 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7340 23:47:00.275065 [DutyScan_Calibration_Flow] ====Done====
7341 23:47:00.275150
7342 23:47:00.278277 [DutyScan_Calibration_Flow] k_type=2
7343 23:47:00.296101
7344 23:47:00.296213 ==DQ 0 ==
7345 23:47:00.299084 Final DQ duty delay cell = 0
7346 23:47:00.302260 [0] MAX Duty = 5062%(X100), DQS PI = 26
7347 23:47:00.305646 [0] MIN Duty = 4907%(X100), DQS PI = 0
7348 23:47:00.305733 [0] AVG Duty = 4984%(X100)
7349 23:47:00.305806
7350 23:47:00.308535 ==DQ 1 ==
7351 23:47:00.312009 Final DQ duty delay cell = 0
7352 23:47:00.315561 [0] MAX Duty = 5156%(X100), DQS PI = 22
7353 23:47:00.318939 [0] MIN Duty = 4907%(X100), DQS PI = 34
7354 23:47:00.319032 [0] AVG Duty = 5031%(X100)
7355 23:47:00.319099
7356 23:47:00.321776 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7357 23:47:00.325226
7358 23:47:00.328879 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7359 23:47:00.332152 [DutyScan_Calibration_Flow] ====Done====
7360 23:47:00.332291 ==
7361 23:47:00.335307 Dram Type= 6, Freq= 0, CH_1, rank 0
7362 23:47:00.338387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7363 23:47:00.338475 ==
7364 23:47:00.342325 [Duty_Offset_Calibration]
7365 23:47:00.342487 B0:1 B1:0 CA:0
7366 23:47:00.342601
7367 23:47:00.345639 [DutyScan_Calibration_Flow] k_type=0
7368 23:47:00.354627
7369 23:47:00.354730 ==CLK 0==
7370 23:47:00.358587 Final CLK duty delay cell = -4
7371 23:47:00.361808 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7372 23:47:00.364919 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7373 23:47:00.368446 [-4] AVG Duty = 4922%(X100)
7374 23:47:00.368538
7375 23:47:00.371779 CH1 CLK Duty spec in!! Max-Min= 156%
7376 23:47:00.374952 [DutyScan_Calibration_Flow] ====Done====
7377 23:47:00.375061
7378 23:47:00.377936 [DutyScan_Calibration_Flow] k_type=1
7379 23:47:00.395419
7380 23:47:00.395525 ==DQS 0 ==
7381 23:47:00.398688 Final DQS duty delay cell = 0
7382 23:47:00.401962 [0] MAX Duty = 5094%(X100), DQS PI = 16
7383 23:47:00.405219 [0] MIN Duty = 4844%(X100), DQS PI = 0
7384 23:47:00.405320 [0] AVG Duty = 4969%(X100)
7385 23:47:00.408426
7386 23:47:00.408533 ==DQS 1 ==
7387 23:47:00.411554 Final DQS duty delay cell = 0
7388 23:47:00.415184 [0] MAX Duty = 5249%(X100), DQS PI = 16
7389 23:47:00.418210 [0] MIN Duty = 4969%(X100), DQS PI = 8
7390 23:47:00.418324 [0] AVG Duty = 5109%(X100)
7391 23:47:00.421434
7392 23:47:00.425088 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7393 23:47:00.425173
7394 23:47:00.428081 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7395 23:47:00.431721 [DutyScan_Calibration_Flow] ====Done====
7396 23:47:00.431805
7397 23:47:00.434740 [DutyScan_Calibration_Flow] k_type=3
7398 23:47:00.452064
7399 23:47:00.452149 ==DQM 0 ==
7400 23:47:00.455350 Final DQM duty delay cell = 0
7401 23:47:00.458618 [0] MAX Duty = 5187%(X100), DQS PI = 8
7402 23:47:00.461782 [0] MIN Duty = 4969%(X100), DQS PI = 48
7403 23:47:00.465006 [0] AVG Duty = 5078%(X100)
7404 23:47:00.465090
7405 23:47:00.465156 ==DQM 1 ==
7406 23:47:00.468269 Final DQM duty delay cell = 0
7407 23:47:00.471516 [0] MAX Duty = 5093%(X100), DQS PI = 16
7408 23:47:00.474707 [0] MIN Duty = 4907%(X100), DQS PI = 32
7409 23:47:00.478599 [0] AVG Duty = 5000%(X100)
7410 23:47:00.478722
7411 23:47:00.481672 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7412 23:47:00.481773
7413 23:47:00.484489 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7414 23:47:00.488216 [DutyScan_Calibration_Flow] ====Done====
7415 23:47:00.488334
7416 23:47:00.491309 [DutyScan_Calibration_Flow] k_type=2
7417 23:47:00.507988
7418 23:47:00.508081 ==DQ 0 ==
7419 23:47:00.511187 Final DQ duty delay cell = -4
7420 23:47:00.514441 [-4] MAX Duty = 5031%(X100), DQS PI = 8
7421 23:47:00.517980 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7422 23:47:00.518060 [-4] AVG Duty = 4953%(X100)
7423 23:47:00.521117
7424 23:47:00.521198 ==DQ 1 ==
7425 23:47:00.524960 Final DQ duty delay cell = 0
7426 23:47:00.528124 [0] MAX Duty = 5156%(X100), DQS PI = 18
7427 23:47:00.531454 [0] MIN Duty = 4938%(X100), DQS PI = 8
7428 23:47:00.531555 [0] AVG Duty = 5047%(X100)
7429 23:47:00.531620
7430 23:47:00.538249 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7431 23:47:00.538329
7432 23:47:00.541576 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7433 23:47:00.544423 [DutyScan_Calibration_Flow] ====Done====
7434 23:47:00.547737 nWR fixed to 30
7435 23:47:00.547875 [ModeRegInit_LP4] CH0 RK0
7436 23:47:00.550831 [ModeRegInit_LP4] CH0 RK1
7437 23:47:00.554509 [ModeRegInit_LP4] CH1 RK0
7438 23:47:00.557866 [ModeRegInit_LP4] CH1 RK1
7439 23:47:00.557963 match AC timing 5
7440 23:47:00.564428 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7441 23:47:00.567790 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7442 23:47:00.571020 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7443 23:47:00.577486 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7444 23:47:00.580710 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7445 23:47:00.580793 [MiockJmeterHQA]
7446 23:47:00.580880
7447 23:47:00.584185 [DramcMiockJmeter] u1RxGatingPI = 0
7448 23:47:00.587770 0 : 4258, 4029
7449 23:47:00.587864 4 : 4253, 4026
7450 23:47:00.590971 8 : 4252, 4027
7451 23:47:00.591095 12 : 4252, 4027
7452 23:47:00.591176 16 : 4363, 4138
7453 23:47:00.594129 20 : 4363, 4137
7454 23:47:00.594220 24 : 4252, 4027
7455 23:47:00.597446 28 : 4252, 4027
7456 23:47:00.597522 32 : 4252, 4027
7457 23:47:00.600791 36 : 4360, 4138
7458 23:47:00.600881 40 : 4252, 4027
7459 23:47:00.604072 44 : 4363, 4138
7460 23:47:00.604146 48 : 4252, 4026
7461 23:47:00.604249 52 : 4250, 4027
7462 23:47:00.607158 56 : 4250, 4027
7463 23:47:00.607241 60 : 4252, 4029
7464 23:47:00.610428 64 : 4360, 4138
7465 23:47:00.610508 68 : 4252, 4027
7466 23:47:00.614058 72 : 4360, 4138
7467 23:47:00.614169 76 : 4250, 4027
7468 23:47:00.617015 80 : 4250, 4027
7469 23:47:00.617092 84 : 4250, 4027
7470 23:47:00.617155 88 : 4360, 139
7471 23:47:00.620304 92 : 4252, 0
7472 23:47:00.620412 96 : 4252, 0
7473 23:47:00.623885 100 : 4252, 0
7474 23:47:00.623996 104 : 4250, 0
7475 23:47:00.624095 108 : 4250, 0
7476 23:47:00.626838 112 : 4253, 0
7477 23:47:00.626914 116 : 4360, 0
7478 23:47:00.626977 120 : 4360, 0
7479 23:47:00.630454 124 : 4248, 0
7480 23:47:00.630533 128 : 4249, 0
7481 23:47:00.633578 132 : 4360, 0
7482 23:47:00.633654 136 : 4361, 0
7483 23:47:00.633719 140 : 4249, 0
7484 23:47:00.637413 144 : 4250, 0
7485 23:47:00.637490 148 : 4360, 0
7486 23:47:00.640111 152 : 4250, 0
7487 23:47:00.640189 156 : 4250, 0
7488 23:47:00.640255 160 : 4250, 0
7489 23:47:00.643946 164 : 4250, 0
7490 23:47:00.644027 168 : 4360, 0
7491 23:47:00.647086 172 : 4250, 0
7492 23:47:00.647160 176 : 4250, 0
7493 23:47:00.647223 180 : 4360, 0
7494 23:47:00.650204 184 : 4361, 0
7495 23:47:00.650283 188 : 4361, 0
7496 23:47:00.650368 192 : 4249, 0
7497 23:47:00.653823 196 : 4360, 0
7498 23:47:00.653937 200 : 4250, 0
7499 23:47:00.657080 204 : 4250, 1302
7500 23:47:00.657156 208 : 4361, 4077
7501 23:47:00.660386 212 : 4250, 4026
7502 23:47:00.660465 216 : 4250, 4027
7503 23:47:00.663766 220 : 4249, 4027
7504 23:47:00.663840 224 : 4250, 4026
7505 23:47:00.667132 228 : 4250, 4027
7506 23:47:00.667207 232 : 4250, 4027
7507 23:47:00.667294 236 : 4249, 4027
7508 23:47:00.670097 240 : 4250, 4027
7509 23:47:00.670174 244 : 4250, 4027
7510 23:47:00.673783 248 : 4360, 4138
7511 23:47:00.673863 252 : 4360, 4138
7512 23:47:00.677287 256 : 4250, 4027
7513 23:47:00.677366 260 : 4361, 4137
7514 23:47:00.680509 264 : 4360, 4138
7515 23:47:00.680589 268 : 4250, 4027
7516 23:47:00.684039 272 : 4249, 4027
7517 23:47:00.684118 276 : 4250, 4027
7518 23:47:00.687102 280 : 4250, 4027
7519 23:47:00.687207 284 : 4250, 4027
7520 23:47:00.690370 288 : 4249, 4027
7521 23:47:00.690469 292 : 4250, 4026
7522 23:47:00.690564 296 : 4250, 4027
7523 23:47:00.693744 300 : 4360, 4138
7524 23:47:00.693842 304 : 4360, 4138
7525 23:47:00.696905 308 : 4250, 3986
7526 23:47:00.697003 312 : 4361, 2182
7527 23:47:00.700127 316 : 4360, 2
7528 23:47:00.700224
7529 23:47:00.700313 MIOCK jitter meter ch=0
7530 23:47:00.703426
7531 23:47:00.703524 1T = (316-88) = 228 dly cells
7532 23:47:00.710161 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7533 23:47:00.710269 ==
7534 23:47:00.713188 Dram Type= 6, Freq= 0, CH_0, rank 0
7535 23:47:00.716437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 23:47:00.716540 ==
7537 23:47:00.723379 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7538 23:47:00.726689 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7539 23:47:00.733253 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7540 23:47:00.736935 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7541 23:47:00.746793 [CA 0] Center 43 (13~74) winsize 62
7542 23:47:00.749957 [CA 1] Center 43 (13~74) winsize 62
7543 23:47:00.753226 [CA 2] Center 38 (9~68) winsize 60
7544 23:47:00.756456 [CA 3] Center 38 (8~68) winsize 61
7545 23:47:00.759955 [CA 4] Center 36 (7~66) winsize 60
7546 23:47:00.763395 [CA 5] Center 36 (7~65) winsize 59
7547 23:47:00.763476
7548 23:47:00.766500 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7549 23:47:00.766580
7550 23:47:00.770487 [CATrainingPosCal] consider 1 rank data
7551 23:47:00.773398 u2DelayCellTimex100 = 285/100 ps
7552 23:47:00.776610 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7553 23:47:00.782994 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7554 23:47:00.786401 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7555 23:47:00.789609 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7556 23:47:00.793632 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7557 23:47:00.796686 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7558 23:47:00.796765
7559 23:47:00.800014 CA PerBit enable=1, Macro0, CA PI delay=36
7560 23:47:00.800097
7561 23:47:00.803214 [CBTSetCACLKResult] CA Dly = 36
7562 23:47:00.806578 CS Dly: 9 (0~40)
7563 23:47:00.809880 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7564 23:47:00.813246 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7565 23:47:00.813324 ==
7566 23:47:00.816146 Dram Type= 6, Freq= 0, CH_0, rank 1
7567 23:47:00.819831 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7568 23:47:00.819911 ==
7569 23:47:00.826581 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7570 23:47:00.829542 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7571 23:47:00.836022 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7572 23:47:00.839769 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7573 23:47:00.850089 [CA 0] Center 42 (12~73) winsize 62
7574 23:47:00.853414 [CA 1] Center 42 (12~73) winsize 62
7575 23:47:00.856501 [CA 2] Center 38 (8~68) winsize 61
7576 23:47:00.859711 [CA 3] Center 37 (8~67) winsize 60
7577 23:47:00.863220 [CA 4] Center 36 (6~66) winsize 61
7578 23:47:00.866357 [CA 5] Center 35 (5~65) winsize 61
7579 23:47:00.866445
7580 23:47:00.869888 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7581 23:47:00.869973
7582 23:47:00.873005 [CATrainingPosCal] consider 2 rank data
7583 23:47:00.876719 u2DelayCellTimex100 = 285/100 ps
7584 23:47:00.879839 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7585 23:47:00.886652 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7586 23:47:00.889823 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7587 23:47:00.893238 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
7588 23:47:00.896662 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7589 23:47:00.899599 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7590 23:47:00.899684
7591 23:47:00.902802 CA PerBit enable=1, Macro0, CA PI delay=36
7592 23:47:00.902887
7593 23:47:00.906694 [CBTSetCACLKResult] CA Dly = 36
7594 23:47:00.909863 CS Dly: 10 (0~42)
7595 23:47:00.913073 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7596 23:47:00.916310 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7597 23:47:00.916404
7598 23:47:00.919515 ----->DramcWriteLeveling(PI) begin...
7599 23:47:00.919601 ==
7600 23:47:00.923031 Dram Type= 6, Freq= 0, CH_0, rank 0
7601 23:47:00.926261 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7602 23:47:00.929507 ==
7603 23:47:00.932926 Write leveling (Byte 0): 39 => 39
7604 23:47:00.933011 Write leveling (Byte 1): 28 => 28
7605 23:47:00.935965 DramcWriteLeveling(PI) end<-----
7606 23:47:00.936078
7607 23:47:00.936171 ==
7608 23:47:00.939162 Dram Type= 6, Freq= 0, CH_0, rank 0
7609 23:47:00.946322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 23:47:00.946407 ==
7611 23:47:00.949574 [Gating] SW mode calibration
7612 23:47:00.955890 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7613 23:47:00.959682 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7614 23:47:00.966116 1 4 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7615 23:47:00.969228 1 4 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7616 23:47:00.973024 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7617 23:47:00.979356 1 4 12 | B1->B0 | 2323 3938 | 0 1 | (0 0) (0 0)
7618 23:47:00.982859 1 4 16 | B1->B0 | 2525 3636 | 0 0 | (0 0) (1 1)
7619 23:47:00.985841 1 4 20 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
7620 23:47:00.992556 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7621 23:47:00.996404 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7622 23:47:00.999268 1 5 0 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7623 23:47:01.003095 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7624 23:47:01.009359 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7625 23:47:01.013587 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (1 0)
7626 23:47:01.015960 1 5 16 | B1->B0 | 3434 2c2b | 0 1 | (0 0) (0 0)
7627 23:47:01.022320 1 5 20 | B1->B0 | 2727 2928 | 0 1 | (1 0) (1 1)
7628 23:47:01.025530 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7629 23:47:01.029387 1 5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7630 23:47:01.035953 1 6 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7631 23:47:01.039509 1 6 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7632 23:47:01.042681 1 6 8 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (1 1)
7633 23:47:01.048962 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7634 23:47:01.052279 1 6 16 | B1->B0 | 2a2a 4545 | 0 1 | (0 0) (0 0)
7635 23:47:01.055902 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7636 23:47:01.062290 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7637 23:47:01.065441 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 23:47:01.068783 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 23:47:01.075430 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 23:47:01.078470 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 23:47:01.082270 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7642 23:47:01.088738 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7643 23:47:01.092120 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7644 23:47:01.095172 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 23:47:01.102113 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 23:47:01.105169 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 23:47:01.108448 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 23:47:01.115276 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 23:47:01.118470 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 23:47:01.121738 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 23:47:01.128720 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 23:47:01.131742 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 23:47:01.135448 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 23:47:01.142207 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 23:47:01.144969 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 23:47:01.148604 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7657 23:47:01.155064 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7658 23:47:01.158120 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7659 23:47:01.161715 Total UI for P1: 0, mck2ui 16
7660 23:47:01.165118 best dqsien dly found for B0: ( 1, 9, 10)
7661 23:47:01.167999 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7662 23:47:01.174531 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 23:47:01.174616 Total UI for P1: 0, mck2ui 16
7664 23:47:01.178121 best dqsien dly found for B1: ( 1, 9, 18)
7665 23:47:01.184710 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7666 23:47:01.188249 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7667 23:47:01.188348
7668 23:47:01.191457 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7669 23:47:01.194680 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7670 23:47:01.198067 [Gating] SW calibration Done
7671 23:47:01.198150 ==
7672 23:47:01.201391 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 23:47:01.204916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 23:47:01.205001 ==
7675 23:47:01.207952 RX Vref Scan: 0
7676 23:47:01.208041
7677 23:47:01.208121 RX Vref 0 -> 0, step: 1
7678 23:47:01.208183
7679 23:47:01.211185 RX Delay 0 -> 252, step: 8
7680 23:47:01.214941 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7681 23:47:01.221279 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7682 23:47:01.224909 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7683 23:47:01.228200 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7684 23:47:01.231404 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7685 23:47:01.234611 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7686 23:47:01.241092 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7687 23:47:01.244227 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7688 23:47:01.247500 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7689 23:47:01.250728 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7690 23:47:01.254565 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7691 23:47:01.260777 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7692 23:47:01.264433 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7693 23:47:01.267827 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7694 23:47:01.270937 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7695 23:47:01.274598 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7696 23:47:01.274683 ==
7697 23:47:01.277836 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 23:47:01.284437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 23:47:01.284551 ==
7700 23:47:01.284649 DQS Delay:
7701 23:47:01.287662 DQS0 = 0, DQS1 = 0
7702 23:47:01.287775 DQM Delay:
7703 23:47:01.290900 DQM0 = 137, DQM1 = 130
7704 23:47:01.290984 DQ Delay:
7705 23:47:01.294330 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7706 23:47:01.297755 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7707 23:47:01.301165 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7708 23:47:01.304463 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7709 23:47:01.304574
7710 23:47:01.304671
7711 23:47:01.304760 ==
7712 23:47:01.307515 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 23:47:01.314345 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 23:47:01.314435 ==
7715 23:47:01.314504
7716 23:47:01.314567
7717 23:47:01.314632 TX Vref Scan disable
7718 23:47:01.317764 == TX Byte 0 ==
7719 23:47:01.320650 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7720 23:47:01.324483 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7721 23:47:01.327636 == TX Byte 1 ==
7722 23:47:01.330994 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7723 23:47:01.337553 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7724 23:47:01.337659 ==
7725 23:47:01.340755 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 23:47:01.343948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 23:47:01.344028 ==
7728 23:47:01.357829
7729 23:47:01.360730 TX Vref early break, caculate TX vref
7730 23:47:01.363924 TX Vref=16, minBit 3, minWin=22, winSum=378
7731 23:47:01.367789 TX Vref=18, minBit 0, minWin=22, winSum=381
7732 23:47:01.371070 TX Vref=20, minBit 3, minWin=23, winSum=400
7733 23:47:01.374214 TX Vref=22, minBit 4, minWin=23, winSum=403
7734 23:47:01.377357 TX Vref=24, minBit 0, minWin=25, winSum=414
7735 23:47:01.383962 TX Vref=26, minBit 2, minWin=24, winSum=421
7736 23:47:01.387713 TX Vref=28, minBit 1, minWin=25, winSum=423
7737 23:47:01.391111 TX Vref=30, minBit 8, minWin=24, winSum=412
7738 23:47:01.394507 TX Vref=32, minBit 5, minWin=24, winSum=403
7739 23:47:01.397290 TX Vref=34, minBit 0, minWin=23, winSum=394
7740 23:47:01.403913 [TxChooseVref] Worse bit 1, Min win 25, Win sum 423, Final Vref 28
7741 23:47:01.404026
7742 23:47:01.407439 Final TX Range 0 Vref 28
7743 23:47:01.407547
7744 23:47:01.407640 ==
7745 23:47:01.410834 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 23:47:01.414362 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 23:47:01.414464 ==
7748 23:47:01.414557
7749 23:47:01.414656
7750 23:47:01.417303 TX Vref Scan disable
7751 23:47:01.423991 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7752 23:47:01.424095 == TX Byte 0 ==
7753 23:47:01.427258 u2DelayCellOfst[0]=13 cells (4 PI)
7754 23:47:01.430268 u2DelayCellOfst[1]=17 cells (5 PI)
7755 23:47:01.433920 u2DelayCellOfst[2]=13 cells (4 PI)
7756 23:47:01.437261 u2DelayCellOfst[3]=10 cells (3 PI)
7757 23:47:01.440621 u2DelayCellOfst[4]=10 cells (3 PI)
7758 23:47:01.443668 u2DelayCellOfst[5]=0 cells (0 PI)
7759 23:47:01.447276 u2DelayCellOfst[6]=17 cells (5 PI)
7760 23:47:01.450622 u2DelayCellOfst[7]=17 cells (5 PI)
7761 23:47:01.453531 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7762 23:47:01.457437 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7763 23:47:01.460667 == TX Byte 1 ==
7764 23:47:01.460751 u2DelayCellOfst[8]=0 cells (0 PI)
7765 23:47:01.463850 u2DelayCellOfst[9]=3 cells (1 PI)
7766 23:47:01.467089 u2DelayCellOfst[10]=10 cells (3 PI)
7767 23:47:01.470252 u2DelayCellOfst[11]=3 cells (1 PI)
7768 23:47:01.473734 u2DelayCellOfst[12]=10 cells (3 PI)
7769 23:47:01.476856 u2DelayCellOfst[13]=10 cells (3 PI)
7770 23:47:01.480649 u2DelayCellOfst[14]=13 cells (4 PI)
7771 23:47:01.484234 u2DelayCellOfst[15]=10 cells (3 PI)
7772 23:47:01.487285 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7773 23:47:01.493522 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7774 23:47:01.493633 DramC Write-DBI on
7775 23:47:01.493733 ==
7776 23:47:01.496694 Dram Type= 6, Freq= 0, CH_0, rank 0
7777 23:47:01.503752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7778 23:47:01.503837 ==
7779 23:47:01.503903
7780 23:47:01.503964
7781 23:47:01.504023 TX Vref Scan disable
7782 23:47:01.507193 == TX Byte 0 ==
7783 23:47:01.510745 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7784 23:47:01.513979 == TX Byte 1 ==
7785 23:47:01.517216 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7786 23:47:01.520723 DramC Write-DBI off
7787 23:47:01.520808
7788 23:47:01.520875 [DATLAT]
7789 23:47:01.520936 Freq=1600, CH0 RK0
7790 23:47:01.520996
7791 23:47:01.523730 DATLAT Default: 0xf
7792 23:47:01.526943 0, 0xFFFF, sum = 0
7793 23:47:01.527029 1, 0xFFFF, sum = 0
7794 23:47:01.530073 2, 0xFFFF, sum = 0
7795 23:47:01.530160 3, 0xFFFF, sum = 0
7796 23:47:01.533258 4, 0xFFFF, sum = 0
7797 23:47:01.533343 5, 0xFFFF, sum = 0
7798 23:47:01.536715 6, 0xFFFF, sum = 0
7799 23:47:01.536829 7, 0xFFFF, sum = 0
7800 23:47:01.540425 8, 0xFFFF, sum = 0
7801 23:47:01.540535 9, 0xFFFF, sum = 0
7802 23:47:01.543374 10, 0xFFFF, sum = 0
7803 23:47:01.543459 11, 0xFFFF, sum = 0
7804 23:47:01.546917 12, 0xFFFF, sum = 0
7805 23:47:01.547001 13, 0xFFFF, sum = 0
7806 23:47:01.550362 14, 0x0, sum = 1
7807 23:47:01.550447 15, 0x0, sum = 2
7808 23:47:01.553068 16, 0x0, sum = 3
7809 23:47:01.553154 17, 0x0, sum = 4
7810 23:47:01.556596 best_step = 15
7811 23:47:01.556706
7812 23:47:01.556804 ==
7813 23:47:01.559686 Dram Type= 6, Freq= 0, CH_0, rank 0
7814 23:47:01.563256 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7815 23:47:01.563341 ==
7816 23:47:01.566550 RX Vref Scan: 1
7817 23:47:01.566634
7818 23:47:01.566701 Set Vref Range= 24 -> 127
7819 23:47:01.566764
7820 23:47:01.570007 RX Vref 24 -> 127, step: 1
7821 23:47:01.570091
7822 23:47:01.573305 RX Delay 19 -> 252, step: 4
7823 23:47:01.573390
7824 23:47:01.576791 Set Vref, RX VrefLevel [Byte0]: 24
7825 23:47:01.580034 [Byte1]: 24
7826 23:47:01.580119
7827 23:47:01.583222 Set Vref, RX VrefLevel [Byte0]: 25
7828 23:47:01.586415 [Byte1]: 25
7829 23:47:01.590179
7830 23:47:01.590263 Set Vref, RX VrefLevel [Byte0]: 26
7831 23:47:01.593622 [Byte1]: 26
7832 23:47:01.597307
7833 23:47:01.597391 Set Vref, RX VrefLevel [Byte0]: 27
7834 23:47:01.600593 [Byte1]: 27
7835 23:47:01.605078
7836 23:47:01.605162 Set Vref, RX VrefLevel [Byte0]: 28
7837 23:47:01.608283 [Byte1]: 28
7838 23:47:01.612782
7839 23:47:01.612861 Set Vref, RX VrefLevel [Byte0]: 29
7840 23:47:01.615874 [Byte1]: 29
7841 23:47:01.620025
7842 23:47:01.620107 Set Vref, RX VrefLevel [Byte0]: 30
7843 23:47:01.623831 [Byte1]: 30
7844 23:47:01.627656
7845 23:47:01.627733 Set Vref, RX VrefLevel [Byte0]: 31
7846 23:47:01.630948 [Byte1]: 31
7847 23:47:01.635361
7848 23:47:01.635437 Set Vref, RX VrefLevel [Byte0]: 32
7849 23:47:01.638585 [Byte1]: 32
7850 23:47:01.642644
7851 23:47:01.642725 Set Vref, RX VrefLevel [Byte0]: 33
7852 23:47:01.646664 [Byte1]: 33
7853 23:47:01.650232
7854 23:47:01.650312 Set Vref, RX VrefLevel [Byte0]: 34
7855 23:47:01.653888 [Byte1]: 34
7856 23:47:01.657933
7857 23:47:01.658009 Set Vref, RX VrefLevel [Byte0]: 35
7858 23:47:01.661625 [Byte1]: 35
7859 23:47:01.665452
7860 23:47:01.665536 Set Vref, RX VrefLevel [Byte0]: 36
7861 23:47:01.668659 [Byte1]: 36
7862 23:47:01.673319
7863 23:47:01.673401 Set Vref, RX VrefLevel [Byte0]: 37
7864 23:47:01.676292 [Byte1]: 37
7865 23:47:01.680641
7866 23:47:01.680723 Set Vref, RX VrefLevel [Byte0]: 38
7867 23:47:01.684177 [Byte1]: 38
7868 23:47:01.688598
7869 23:47:01.688680 Set Vref, RX VrefLevel [Byte0]: 39
7870 23:47:01.691516 [Byte1]: 39
7871 23:47:01.696125
7872 23:47:01.696207 Set Vref, RX VrefLevel [Byte0]: 40
7873 23:47:01.699129 [Byte1]: 40
7874 23:47:01.703276
7875 23:47:01.703357 Set Vref, RX VrefLevel [Byte0]: 41
7876 23:47:01.706678 [Byte1]: 41
7877 23:47:01.710951
7878 23:47:01.711052 Set Vref, RX VrefLevel [Byte0]: 42
7879 23:47:01.714403 [Byte1]: 42
7880 23:47:01.718777
7881 23:47:01.718885 Set Vref, RX VrefLevel [Byte0]: 43
7882 23:47:01.721867 [Byte1]: 43
7883 23:47:01.726305
7884 23:47:01.726429 Set Vref, RX VrefLevel [Byte0]: 44
7885 23:47:01.729417 [Byte1]: 44
7886 23:47:01.733972
7887 23:47:01.734097 Set Vref, RX VrefLevel [Byte0]: 45
7888 23:47:01.737155 [Byte1]: 45
7889 23:47:01.741562
7890 23:47:01.741668 Set Vref, RX VrefLevel [Byte0]: 46
7891 23:47:01.744603 [Byte1]: 46
7892 23:47:01.749164
7893 23:47:01.749239 Set Vref, RX VrefLevel [Byte0]: 47
7894 23:47:01.752766 [Byte1]: 47
7895 23:47:01.756779
7896 23:47:01.756885 Set Vref, RX VrefLevel [Byte0]: 48
7897 23:47:01.759976 [Byte1]: 48
7898 23:47:01.764603
7899 23:47:01.764707 Set Vref, RX VrefLevel [Byte0]: 49
7900 23:47:01.767514 [Byte1]: 49
7901 23:47:01.772026
7902 23:47:01.772102 Set Vref, RX VrefLevel [Byte0]: 50
7903 23:47:01.775218 [Byte1]: 50
7904 23:47:01.779033
7905 23:47:01.779117 Set Vref, RX VrefLevel [Byte0]: 51
7906 23:47:01.782428 [Byte1]: 51
7907 23:47:01.786772
7908 23:47:01.786870 Set Vref, RX VrefLevel [Byte0]: 52
7909 23:47:01.790034 [Byte1]: 52
7910 23:47:01.794692
7911 23:47:01.794775 Set Vref, RX VrefLevel [Byte0]: 53
7912 23:47:01.797617 [Byte1]: 53
7913 23:47:01.801936
7914 23:47:01.802033 Set Vref, RX VrefLevel [Byte0]: 54
7915 23:47:01.805162 [Byte1]: 54
7916 23:47:01.809495
7917 23:47:01.809607 Set Vref, RX VrefLevel [Byte0]: 55
7918 23:47:01.812814 [Byte1]: 55
7919 23:47:01.817017
7920 23:47:01.817101 Set Vref, RX VrefLevel [Byte0]: 56
7921 23:47:01.820317 [Byte1]: 56
7922 23:47:01.824606
7923 23:47:01.824689 Set Vref, RX VrefLevel [Byte0]: 57
7924 23:47:01.827702 [Byte1]: 57
7925 23:47:01.832354
7926 23:47:01.832439 Set Vref, RX VrefLevel [Byte0]: 58
7927 23:47:01.835393 [Byte1]: 58
7928 23:47:01.839880
7929 23:47:01.839968 Set Vref, RX VrefLevel [Byte0]: 59
7930 23:47:01.843166 [Byte1]: 59
7931 23:47:01.847266
7932 23:47:01.847346 Set Vref, RX VrefLevel [Byte0]: 60
7933 23:47:01.850849 [Byte1]: 60
7934 23:47:01.855384
7935 23:47:01.855468 Set Vref, RX VrefLevel [Byte0]: 61
7936 23:47:01.858248 [Byte1]: 61
7937 23:47:01.862581
7938 23:47:01.862665 Set Vref, RX VrefLevel [Byte0]: 62
7939 23:47:01.865813 [Byte1]: 62
7940 23:47:01.870279
7941 23:47:01.870363 Set Vref, RX VrefLevel [Byte0]: 63
7942 23:47:01.873541 [Byte1]: 63
7943 23:47:01.877951
7944 23:47:01.878035 Set Vref, RX VrefLevel [Byte0]: 64
7945 23:47:01.881140 [Byte1]: 64
7946 23:47:01.885562
7947 23:47:01.885646 Set Vref, RX VrefLevel [Byte0]: 65
7948 23:47:01.888871 [Byte1]: 65
7949 23:47:01.893052
7950 23:47:01.893140 Set Vref, RX VrefLevel [Byte0]: 66
7951 23:47:01.896118 [Byte1]: 66
7952 23:47:01.900709
7953 23:47:01.900793 Set Vref, RX VrefLevel [Byte0]: 67
7954 23:47:01.904084 [Byte1]: 67
7955 23:47:01.907790
7956 23:47:01.907873 Set Vref, RX VrefLevel [Byte0]: 68
7957 23:47:01.911090 [Byte1]: 68
7958 23:47:01.915457
7959 23:47:01.915554 Set Vref, RX VrefLevel [Byte0]: 69
7960 23:47:01.918989 [Byte1]: 69
7961 23:47:01.923554
7962 23:47:01.923632 Set Vref, RX VrefLevel [Byte0]: 70
7963 23:47:01.926612 [Byte1]: 70
7964 23:47:01.930941
7965 23:47:01.931042 Set Vref, RX VrefLevel [Byte0]: 71
7966 23:47:01.934006 [Byte1]: 71
7967 23:47:01.938229
7968 23:47:01.938337 Set Vref, RX VrefLevel [Byte0]: 72
7969 23:47:01.942062 [Byte1]: 72
7970 23:47:01.945681
7971 23:47:01.945755 Set Vref, RX VrefLevel [Byte0]: 73
7972 23:47:01.949371 [Byte1]: 73
7973 23:47:01.953375
7974 23:47:01.953480 Set Vref, RX VrefLevel [Byte0]: 74
7975 23:47:01.956652 [Byte1]: 74
7976 23:47:01.960865
7977 23:47:01.960980 Final RX Vref Byte 0 = 54 to rank0
7978 23:47:01.964504 Final RX Vref Byte 1 = 60 to rank0
7979 23:47:01.967416 Final RX Vref Byte 0 = 54 to rank1
7980 23:47:01.971057 Final RX Vref Byte 1 = 60 to rank1==
7981 23:47:01.974270 Dram Type= 6, Freq= 0, CH_0, rank 0
7982 23:47:01.981174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 23:47:01.981281 ==
7984 23:47:01.981392 DQS Delay:
7985 23:47:01.981485 DQS0 = 0, DQS1 = 0
7986 23:47:01.984003 DQM Delay:
7987 23:47:01.984109 DQM0 = 133, DQM1 = 127
7988 23:47:01.987388 DQ Delay:
7989 23:47:01.990969 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7990 23:47:01.993956 DQ4 =132, DQ5 =122, DQ6 =142, DQ7 =138
7991 23:47:01.997805 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
7992 23:47:02.001070 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
7993 23:47:02.001171
7994 23:47:02.001269
7995 23:47:02.001361
7996 23:47:02.004368 [DramC_TX_OE_Calibration] TA2
7997 23:47:02.007559 Original DQ_B0 (3 6) =30, OEN = 27
7998 23:47:02.010846 Original DQ_B1 (3 6) =30, OEN = 27
7999 23:47:02.014022 24, 0x0, End_B0=24 End_B1=24
8000 23:47:02.014135 25, 0x0, End_B0=25 End_B1=25
8001 23:47:02.017262 26, 0x0, End_B0=26 End_B1=26
8002 23:47:02.020445 27, 0x0, End_B0=27 End_B1=27
8003 23:47:02.024223 28, 0x0, End_B0=28 End_B1=28
8004 23:47:02.027329 29, 0x0, End_B0=29 End_B1=29
8005 23:47:02.027429 30, 0x0, End_B0=30 End_B1=30
8006 23:47:02.030751 31, 0x4141, End_B0=30 End_B1=30
8007 23:47:02.034002 Byte0 end_step=30 best_step=27
8008 23:47:02.037133 Byte1 end_step=30 best_step=27
8009 23:47:02.041004 Byte0 TX OE(2T, 0.5T) = (3, 3)
8010 23:47:02.043953 Byte1 TX OE(2T, 0.5T) = (3, 3)
8011 23:47:02.044056
8012 23:47:02.044155
8013 23:47:02.050468 [DQSOSCAuto] RK0, (LSB)MR18= 0x2824, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
8014 23:47:02.053656 CH0 RK0: MR19=303, MR18=2824
8015 23:47:02.060783 CH0_RK0: MR19=0x303, MR18=0x2824, DQSOSC=389, MR23=63, INC=24, DEC=16
8016 23:47:02.060896
8017 23:47:02.063974 ----->DramcWriteLeveling(PI) begin...
8018 23:47:02.064072 ==
8019 23:47:02.067059 Dram Type= 6, Freq= 0, CH_0, rank 1
8020 23:47:02.070951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8021 23:47:02.071050 ==
8022 23:47:02.074407 Write leveling (Byte 0): 35 => 35
8023 23:47:02.077477 Write leveling (Byte 1): 28 => 28
8024 23:47:02.080617 DramcWriteLeveling(PI) end<-----
8025 23:47:02.080697
8026 23:47:02.080763 ==
8027 23:47:02.084023 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 23:47:02.087580 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 23:47:02.087680 ==
8030 23:47:02.090964 [Gating] SW mode calibration
8031 23:47:02.097838 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8032 23:47:02.104539 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8033 23:47:02.107899 1 4 0 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8034 23:47:02.110734 1 4 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8035 23:47:02.117274 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8036 23:47:02.121168 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8037 23:47:02.124197 1 4 16 | B1->B0 | 3232 3e3d | 1 1 | (1 1) (1 1)
8038 23:47:02.130733 1 4 20 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)
8039 23:47:02.134313 1 4 24 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
8040 23:47:02.137261 1 4 28 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
8041 23:47:02.144164 1 5 0 | B1->B0 | 3434 3a3a | 1 1 | (1 1) (1 1)
8042 23:47:02.147406 1 5 4 | B1->B0 | 3434 3b3a | 1 1 | (1 1) (1 1)
8043 23:47:02.150525 1 5 8 | B1->B0 | 3434 3b3b | 1 1 | (1 1) (1 1)
8044 23:47:02.157226 1 5 12 | B1->B0 | 3434 3534 | 1 1 | (1 0) (0 1)
8045 23:47:02.160912 1 5 16 | B1->B0 | 2d2d 2d2c | 0 1 | (0 0) (1 1)
8046 23:47:02.164167 1 5 20 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
8047 23:47:02.167466 1 5 24 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (1 1)
8048 23:47:02.174260 1 5 28 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8049 23:47:02.177842 1 6 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
8050 23:47:02.180796 1 6 4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
8051 23:47:02.187184 1 6 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8052 23:47:02.190454 1 6 12 | B1->B0 | 2323 3130 | 0 1 | (0 0) (1 1)
8053 23:47:02.194194 1 6 16 | B1->B0 | 3636 4544 | 1 1 | (0 0) (0 0)
8054 23:47:02.200312 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8055 23:47:02.203639 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 23:47:02.206966 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8057 23:47:02.213537 1 7 0 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8058 23:47:02.217234 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 23:47:02.220233 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 23:47:02.227548 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8061 23:47:02.230342 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8062 23:47:02.233951 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 23:47:02.240575 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 23:47:02.243457 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 23:47:02.246943 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 23:47:02.253445 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 23:47:02.257343 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 23:47:02.260252 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 23:47:02.267263 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 23:47:02.270283 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 23:47:02.273371 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 23:47:02.280456 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 23:47:02.283698 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 23:47:02.286956 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 23:47:02.293389 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 23:47:02.296886 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8077 23:47:02.300469 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8078 23:47:02.303405 Total UI for P1: 0, mck2ui 16
8079 23:47:02.306692 best dqsien dly found for B0: ( 1, 9, 12)
8080 23:47:02.310265 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 23:47:02.313422 Total UI for P1: 0, mck2ui 16
8082 23:47:02.316647 best dqsien dly found for B1: ( 1, 9, 14)
8083 23:47:02.323123 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8084 23:47:02.326683 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8085 23:47:02.326766
8086 23:47:02.329933 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8087 23:47:02.333124 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8088 23:47:02.336512 [Gating] SW calibration Done
8089 23:47:02.336592 ==
8090 23:47:02.339714 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 23:47:02.343522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 23:47:02.343601 ==
8093 23:47:02.346349 RX Vref Scan: 0
8094 23:47:02.346464
8095 23:47:02.346568 RX Vref 0 -> 0, step: 1
8096 23:47:02.346655
8097 23:47:02.350108 RX Delay 0 -> 252, step: 8
8098 23:47:02.353030 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8099 23:47:02.356839 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8100 23:47:02.363171 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8101 23:47:02.366505 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8102 23:47:02.369608 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8103 23:47:02.373126 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8104 23:47:02.376912 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8105 23:47:02.382923 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8106 23:47:02.386552 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8107 23:47:02.389932 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8108 23:47:02.392961 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8109 23:47:02.396125 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8110 23:47:02.403359 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8111 23:47:02.406538 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8112 23:47:02.409390 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8113 23:47:02.413171 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8114 23:47:02.413249 ==
8115 23:47:02.416463 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 23:47:02.422912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 23:47:02.422998 ==
8118 23:47:02.423065 DQS Delay:
8119 23:47:02.426109 DQS0 = 0, DQS1 = 0
8120 23:47:02.426194 DQM Delay:
8121 23:47:02.429209 DQM0 = 136, DQM1 = 128
8122 23:47:02.429327 DQ Delay:
8123 23:47:02.433092 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8124 23:47:02.436157 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8125 23:47:02.439338 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8126 23:47:02.442484 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8127 23:47:02.442592
8128 23:47:02.442684
8129 23:47:02.442774 ==
8130 23:47:02.446026 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 23:47:02.452588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 23:47:02.452666 ==
8133 23:47:02.452729
8134 23:47:02.452790
8135 23:47:02.452861 TX Vref Scan disable
8136 23:47:02.456234 == TX Byte 0 ==
8137 23:47:02.459516 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8138 23:47:02.465950 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8139 23:47:02.466051 == TX Byte 1 ==
8140 23:47:02.469293 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8141 23:47:02.476097 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8142 23:47:02.476199 ==
8143 23:47:02.479457 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 23:47:02.482431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 23:47:02.482530 ==
8146 23:47:02.495765
8147 23:47:02.499173 TX Vref early break, caculate TX vref
8148 23:47:02.502514 TX Vref=16, minBit 0, minWin=23, winSum=384
8149 23:47:02.505946 TX Vref=18, minBit 1, minWin=23, winSum=397
8150 23:47:02.509150 TX Vref=20, minBit 1, minWin=24, winSum=408
8151 23:47:02.512544 TX Vref=22, minBit 1, minWin=24, winSum=411
8152 23:47:02.515753 TX Vref=24, minBit 1, minWin=24, winSum=424
8153 23:47:02.522162 TX Vref=26, minBit 1, minWin=24, winSum=423
8154 23:47:02.525646 TX Vref=28, minBit 0, minWin=25, winSum=420
8155 23:47:02.528889 TX Vref=30, minBit 0, minWin=25, winSum=416
8156 23:47:02.532636 TX Vref=32, minBit 0, minWin=24, winSum=411
8157 23:47:02.535777 TX Vref=34, minBit 0, minWin=23, winSum=400
8158 23:47:02.542209 [TxChooseVref] Worse bit 0, Min win 25, Win sum 420, Final Vref 28
8159 23:47:02.542295
8160 23:47:02.545483 Final TX Range 0 Vref 28
8161 23:47:02.545568
8162 23:47:02.545635 ==
8163 23:47:02.549509 Dram Type= 6, Freq= 0, CH_0, rank 1
8164 23:47:02.552662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8165 23:47:02.552747 ==
8166 23:47:02.552814
8167 23:47:02.552876
8168 23:47:02.555919 TX Vref Scan disable
8169 23:47:02.562002 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8170 23:47:02.562087 == TX Byte 0 ==
8171 23:47:02.565850 u2DelayCellOfst[0]=13 cells (4 PI)
8172 23:47:02.569185 u2DelayCellOfst[1]=13 cells (4 PI)
8173 23:47:02.572260 u2DelayCellOfst[2]=10 cells (3 PI)
8174 23:47:02.575729 u2DelayCellOfst[3]=6 cells (2 PI)
8175 23:47:02.579335 u2DelayCellOfst[4]=6 cells (2 PI)
8176 23:47:02.582487 u2DelayCellOfst[5]=0 cells (0 PI)
8177 23:47:02.585445 u2DelayCellOfst[6]=13 cells (4 PI)
8178 23:47:02.585529 u2DelayCellOfst[7]=13 cells (4 PI)
8179 23:47:02.592556 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8180 23:47:02.595826 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8181 23:47:02.595911 == TX Byte 1 ==
8182 23:47:02.599014 u2DelayCellOfst[8]=0 cells (0 PI)
8183 23:47:02.602240 u2DelayCellOfst[9]=0 cells (0 PI)
8184 23:47:02.605330 u2DelayCellOfst[10]=6 cells (2 PI)
8185 23:47:02.608691 u2DelayCellOfst[11]=3 cells (1 PI)
8186 23:47:02.612489 u2DelayCellOfst[12]=10 cells (3 PI)
8187 23:47:02.615489 u2DelayCellOfst[13]=10 cells (3 PI)
8188 23:47:02.619147 u2DelayCellOfst[14]=13 cells (4 PI)
8189 23:47:02.622054 u2DelayCellOfst[15]=10 cells (3 PI)
8190 23:47:02.625438 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8191 23:47:02.628773 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8192 23:47:02.632112 DramC Write-DBI on
8193 23:47:02.632196 ==
8194 23:47:02.635787 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 23:47:02.638905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 23:47:02.638991 ==
8197 23:47:02.639058
8198 23:47:02.639150
8199 23:47:02.642122 TX Vref Scan disable
8200 23:47:02.645862 == TX Byte 0 ==
8201 23:47:02.648801 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8202 23:47:02.652522 == TX Byte 1 ==
8203 23:47:02.655713 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8204 23:47:02.655791 DramC Write-DBI off
8205 23:47:02.655857
8206 23:47:02.659067 [DATLAT]
8207 23:47:02.659149 Freq=1600, CH0 RK1
8208 23:47:02.659214
8209 23:47:02.662247 DATLAT Default: 0xf
8210 23:47:02.662326 0, 0xFFFF, sum = 0
8211 23:47:02.665423 1, 0xFFFF, sum = 0
8212 23:47:02.665510 2, 0xFFFF, sum = 0
8213 23:47:02.669143 3, 0xFFFF, sum = 0
8214 23:47:02.669224 4, 0xFFFF, sum = 0
8215 23:47:02.672253 5, 0xFFFF, sum = 0
8216 23:47:02.672374 6, 0xFFFF, sum = 0
8217 23:47:02.675503 7, 0xFFFF, sum = 0
8218 23:47:02.678719 8, 0xFFFF, sum = 0
8219 23:47:02.678801 9, 0xFFFF, sum = 0
8220 23:47:02.682317 10, 0xFFFF, sum = 0
8221 23:47:02.682402 11, 0xFFFF, sum = 0
8222 23:47:02.685257 12, 0xFFFF, sum = 0
8223 23:47:02.685340 13, 0xFFFF, sum = 0
8224 23:47:02.688536 14, 0x0, sum = 1
8225 23:47:02.688622 15, 0x0, sum = 2
8226 23:47:02.691740 16, 0x0, sum = 3
8227 23:47:02.691855 17, 0x0, sum = 4
8228 23:47:02.695464 best_step = 15
8229 23:47:02.695547
8230 23:47:02.695613 ==
8231 23:47:02.698499 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 23:47:02.702135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 23:47:02.702227 ==
8234 23:47:02.702294 RX Vref Scan: 0
8235 23:47:02.702356
8236 23:47:02.705297 RX Vref 0 -> 0, step: 1
8237 23:47:02.705379
8238 23:47:02.708437 RX Delay 19 -> 252, step: 4
8239 23:47:02.712145 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8240 23:47:02.718538 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8241 23:47:02.721599 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8242 23:47:02.725008 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8243 23:47:02.729052 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8244 23:47:02.731716 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8245 23:47:02.735492 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8246 23:47:02.741754 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8247 23:47:02.745522 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8248 23:47:02.748623 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8249 23:47:02.751775 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8250 23:47:02.754915 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8251 23:47:02.761937 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8252 23:47:02.765201 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8253 23:47:02.768258 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8254 23:47:02.771665 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8255 23:47:02.771755 ==
8256 23:47:02.774890 Dram Type= 6, Freq= 0, CH_0, rank 1
8257 23:47:02.781695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 23:47:02.781785 ==
8259 23:47:02.781855 DQS Delay:
8260 23:47:02.784681 DQS0 = 0, DQS1 = 0
8261 23:47:02.784756 DQM Delay:
8262 23:47:02.787958 DQM0 = 134, DQM1 = 127
8263 23:47:02.788036 DQ Delay:
8264 23:47:02.791800 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8265 23:47:02.795048 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =142
8266 23:47:02.798176 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8267 23:47:02.801490 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8268 23:47:02.801568
8269 23:47:02.801638
8270 23:47:02.801701
8271 23:47:02.804926 [DramC_TX_OE_Calibration] TA2
8272 23:47:02.807938 Original DQ_B0 (3 6) =30, OEN = 27
8273 23:47:02.811158 Original DQ_B1 (3 6) =30, OEN = 27
8274 23:47:02.814354 24, 0x0, End_B0=24 End_B1=24
8275 23:47:02.818256 25, 0x0, End_B0=25 End_B1=25
8276 23:47:02.818337 26, 0x0, End_B0=26 End_B1=26
8277 23:47:02.821182 27, 0x0, End_B0=27 End_B1=27
8278 23:47:02.824675 28, 0x0, End_B0=28 End_B1=28
8279 23:47:02.827678 29, 0x0, End_B0=29 End_B1=29
8280 23:47:02.827758 30, 0x0, End_B0=30 End_B1=30
8281 23:47:02.831245 31, 0x4141, End_B0=30 End_B1=30
8282 23:47:02.834496 Byte0 end_step=30 best_step=27
8283 23:47:02.838118 Byte1 end_step=30 best_step=27
8284 23:47:02.841396 Byte0 TX OE(2T, 0.5T) = (3, 3)
8285 23:47:02.844533 Byte1 TX OE(2T, 0.5T) = (3, 3)
8286 23:47:02.844614
8287 23:47:02.844682
8288 23:47:02.850870 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8289 23:47:02.854537 CH0 RK1: MR19=303, MR18=2008
8290 23:47:02.861088 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8291 23:47:02.864327 [RxdqsGatingPostProcess] freq 1600
8292 23:47:02.867690 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8293 23:47:02.871292 best DQS0 dly(2T, 0.5T) = (1, 1)
8294 23:47:02.874268 best DQS1 dly(2T, 0.5T) = (1, 1)
8295 23:47:02.877455 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8296 23:47:02.881130 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8297 23:47:02.884227 best DQS0 dly(2T, 0.5T) = (1, 1)
8298 23:47:02.887841 best DQS1 dly(2T, 0.5T) = (1, 1)
8299 23:47:02.891325 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8300 23:47:02.894375 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8301 23:47:02.897855 Pre-setting of DQS Precalculation
8302 23:47:02.900888 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8303 23:47:02.900985 ==
8304 23:47:02.904271 Dram Type= 6, Freq= 0, CH_1, rank 0
8305 23:47:02.910965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8306 23:47:02.911082 ==
8307 23:47:02.914043 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8308 23:47:02.917778 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8309 23:47:02.924287 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8310 23:47:02.930466 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8311 23:47:02.938141 [CA 0] Center 42 (13~72) winsize 60
8312 23:47:02.941638 [CA 1] Center 42 (13~72) winsize 60
8313 23:47:02.944804 [CA 2] Center 39 (9~69) winsize 61
8314 23:47:02.947932 [CA 3] Center 38 (9~67) winsize 59
8315 23:47:02.951743 [CA 4] Center 39 (10~68) winsize 59
8316 23:47:02.954855 [CA 5] Center 37 (8~67) winsize 60
8317 23:47:02.954937
8318 23:47:02.957990 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8319 23:47:02.958071
8320 23:47:02.961901 [CATrainingPosCal] consider 1 rank data
8321 23:47:02.964897 u2DelayCellTimex100 = 285/100 ps
8322 23:47:02.968225 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8323 23:47:02.974803 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8324 23:47:02.978230 CA2 delay=39 (9~69),Diff = 2 PI (6 cell)
8325 23:47:02.981677 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8326 23:47:02.984656 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8327 23:47:02.987914 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8328 23:47:02.987993
8329 23:47:02.991145 CA PerBit enable=1, Macro0, CA PI delay=37
8330 23:47:02.991250
8331 23:47:02.994366 [CBTSetCACLKResult] CA Dly = 37
8332 23:47:02.997876 CS Dly: 11 (0~42)
8333 23:47:03.001467 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8334 23:47:03.004425 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8335 23:47:03.004495 ==
8336 23:47:03.008152 Dram Type= 6, Freq= 0, CH_1, rank 1
8337 23:47:03.011182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 23:47:03.015030 ==
8339 23:47:03.018031 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8340 23:47:03.021780 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8341 23:47:03.028135 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8342 23:47:03.031480 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8343 23:47:03.041374 [CA 0] Center 42 (12~72) winsize 61
8344 23:47:03.045250 [CA 1] Center 42 (12~72) winsize 61
8345 23:47:03.048101 [CA 2] Center 38 (9~68) winsize 60
8346 23:47:03.051563 [CA 3] Center 38 (8~68) winsize 61
8347 23:47:03.055410 [CA 4] Center 38 (8~68) winsize 61
8348 23:47:03.058419 [CA 5] Center 36 (7~66) winsize 60
8349 23:47:03.058528
8350 23:47:03.061517 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8351 23:47:03.061600
8352 23:47:03.064748 [CATrainingPosCal] consider 2 rank data
8353 23:47:03.068264 u2DelayCellTimex100 = 285/100 ps
8354 23:47:03.071448 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8355 23:47:03.078638 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8356 23:47:03.081835 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8357 23:47:03.085084 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8358 23:47:03.088665 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8359 23:47:03.091642 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8360 23:47:03.091728
8361 23:47:03.094973 CA PerBit enable=1, Macro0, CA PI delay=37
8362 23:47:03.095058
8363 23:47:03.098275 [CBTSetCACLKResult] CA Dly = 37
8364 23:47:03.098361 CS Dly: 12 (0~45)
8365 23:47:03.104973 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8366 23:47:03.108153 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8367 23:47:03.108262
8368 23:47:03.111488 ----->DramcWriteLeveling(PI) begin...
8369 23:47:03.111571 ==
8370 23:47:03.114810 Dram Type= 6, Freq= 0, CH_1, rank 0
8371 23:47:03.117905 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8372 23:47:03.121637 ==
8373 23:47:03.121717 Write leveling (Byte 0): 27 => 27
8374 23:47:03.124981 Write leveling (Byte 1): 27 => 27
8375 23:47:03.128241 DramcWriteLeveling(PI) end<-----
8376 23:47:03.128361
8377 23:47:03.128456 ==
8378 23:47:03.131592 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 23:47:03.138125 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 23:47:03.138211 ==
8381 23:47:03.141383 [Gating] SW mode calibration
8382 23:47:03.148259 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8383 23:47:03.151423 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8384 23:47:03.157628 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8385 23:47:03.161105 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 23:47:03.164289 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8387 23:47:03.171125 1 4 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
8388 23:47:03.174404 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 23:47:03.177519 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 23:47:03.184439 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 23:47:03.187851 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 23:47:03.191057 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 23:47:03.197547 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 23:47:03.200722 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8395 23:47:03.204519 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8396 23:47:03.207667 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 23:47:03.214015 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 23:47:03.217917 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 23:47:03.220573 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 23:47:03.227638 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 23:47:03.231040 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 23:47:03.234223 1 6 8 | B1->B0 | 2525 3635 | 0 1 | (0 0) (0 0)
8403 23:47:03.240814 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8404 23:47:03.244280 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 23:47:03.247208 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 23:47:03.253991 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 23:47:03.257389 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 23:47:03.260447 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 23:47:03.267372 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 23:47:03.270275 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8411 23:47:03.273977 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8412 23:47:03.280513 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 23:47:03.283876 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 23:47:03.287057 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 23:47:03.293734 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 23:47:03.296914 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 23:47:03.300442 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 23:47:03.306691 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 23:47:03.310607 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 23:47:03.313784 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 23:47:03.320416 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 23:47:03.323715 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 23:47:03.327245 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 23:47:03.333842 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 23:47:03.336997 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 23:47:03.340182 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8427 23:47:03.347357 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8428 23:47:03.350301 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 23:47:03.353776 Total UI for P1: 0, mck2ui 16
8430 23:47:03.356863 best dqsien dly found for B0: ( 1, 9, 10)
8431 23:47:03.359995 Total UI for P1: 0, mck2ui 16
8432 23:47:03.363877 best dqsien dly found for B1: ( 1, 9, 10)
8433 23:47:03.367035 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8434 23:47:03.370151 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8435 23:47:03.370299
8436 23:47:03.373913 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8437 23:47:03.376638 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8438 23:47:03.380059 [Gating] SW calibration Done
8439 23:47:03.380200 ==
8440 23:47:03.383640 Dram Type= 6, Freq= 0, CH_1, rank 0
8441 23:47:03.386762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8442 23:47:03.386869 ==
8443 23:47:03.390045 RX Vref Scan: 0
8444 23:47:03.390146
8445 23:47:03.393677 RX Vref 0 -> 0, step: 1
8446 23:47:03.393820
8447 23:47:03.393903 RX Delay 0 -> 252, step: 8
8448 23:47:03.400322 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8449 23:47:03.403243 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8450 23:47:03.406458 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8451 23:47:03.409880 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8452 23:47:03.413508 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8453 23:47:03.420306 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8454 23:47:03.423112 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8455 23:47:03.427158 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8456 23:47:03.430173 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8457 23:47:03.433386 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8458 23:47:03.436976 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8459 23:47:03.443291 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8460 23:47:03.446513 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8461 23:47:03.449955 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8462 23:47:03.453169 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8463 23:47:03.459924 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8464 23:47:03.460010 ==
8465 23:47:03.463142 Dram Type= 6, Freq= 0, CH_1, rank 0
8466 23:47:03.466291 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8467 23:47:03.466377 ==
8468 23:47:03.466444 DQS Delay:
8469 23:47:03.469565 DQS0 = 0, DQS1 = 0
8470 23:47:03.469650 DQM Delay:
8471 23:47:03.473454 DQM0 = 136, DQM1 = 133
8472 23:47:03.473538 DQ Delay:
8473 23:47:03.476461 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8474 23:47:03.479951 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8475 23:47:03.483003 DQ8 =123, DQ9 =123, DQ10 =131, DQ11 =127
8476 23:47:03.486257 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8477 23:47:03.486361
8478 23:47:03.486465
8479 23:47:03.489553 ==
8480 23:47:03.493162 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 23:47:03.495944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 23:47:03.496045 ==
8483 23:47:03.496140
8484 23:47:03.496228
8485 23:47:03.499767 TX Vref Scan disable
8486 23:47:03.499865 == TX Byte 0 ==
8487 23:47:03.502969 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8488 23:47:03.509187 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8489 23:47:03.509293 == TX Byte 1 ==
8490 23:47:03.512665 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8491 23:47:03.519545 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8492 23:47:03.519657 ==
8493 23:47:03.522626 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 23:47:03.526169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 23:47:03.526281 ==
8496 23:47:03.538532
8497 23:47:03.541798 TX Vref early break, caculate TX vref
8498 23:47:03.545678 TX Vref=16, minBit 1, minWin=22, winSum=378
8499 23:47:03.548911 TX Vref=18, minBit 1, minWin=23, winSum=385
8500 23:47:03.551740 TX Vref=20, minBit 1, minWin=23, winSum=397
8501 23:47:03.555881 TX Vref=22, minBit 0, minWin=24, winSum=407
8502 23:47:03.558374 TX Vref=24, minBit 1, minWin=25, winSum=415
8503 23:47:03.565465 TX Vref=26, minBit 1, minWin=25, winSum=424
8504 23:47:03.568666 TX Vref=28, minBit 2, minWin=25, winSum=425
8505 23:47:03.571993 TX Vref=30, minBit 0, minWin=25, winSum=419
8506 23:47:03.575183 TX Vref=32, minBit 0, minWin=25, winSum=413
8507 23:47:03.578474 TX Vref=34, minBit 0, minWin=24, winSum=400
8508 23:47:03.585337 [TxChooseVref] Worse bit 2, Min win 25, Win sum 425, Final Vref 28
8509 23:47:03.585414
8510 23:47:03.589024 Final TX Range 0 Vref 28
8511 23:47:03.589102
8512 23:47:03.589164 ==
8513 23:47:03.592033 Dram Type= 6, Freq= 0, CH_1, rank 0
8514 23:47:03.595610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8515 23:47:03.595686 ==
8516 23:47:03.595752
8517 23:47:03.595814
8518 23:47:03.598588 TX Vref Scan disable
8519 23:47:03.605431 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8520 23:47:03.605534 == TX Byte 0 ==
8521 23:47:03.609170 u2DelayCellOfst[0]=20 cells (6 PI)
8522 23:47:03.612440 u2DelayCellOfst[1]=13 cells (4 PI)
8523 23:47:03.615120 u2DelayCellOfst[2]=0 cells (0 PI)
8524 23:47:03.618867 u2DelayCellOfst[3]=10 cells (3 PI)
8525 23:47:03.622040 u2DelayCellOfst[4]=13 cells (4 PI)
8526 23:47:03.625094 u2DelayCellOfst[5]=20 cells (6 PI)
8527 23:47:03.628528 u2DelayCellOfst[6]=20 cells (6 PI)
8528 23:47:03.628620 u2DelayCellOfst[7]=6 cells (2 PI)
8529 23:47:03.635070 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8530 23:47:03.638174 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8531 23:47:03.638272 == TX Byte 1 ==
8532 23:47:03.641830 u2DelayCellOfst[8]=0 cells (0 PI)
8533 23:47:03.645373 u2DelayCellOfst[9]=3 cells (1 PI)
8534 23:47:03.648822 u2DelayCellOfst[10]=13 cells (4 PI)
8535 23:47:03.651570 u2DelayCellOfst[11]=3 cells (1 PI)
8536 23:47:03.655403 u2DelayCellOfst[12]=17 cells (5 PI)
8537 23:47:03.658711 u2DelayCellOfst[13]=17 cells (5 PI)
8538 23:47:03.661895 u2DelayCellOfst[14]=17 cells (5 PI)
8539 23:47:03.665030 u2DelayCellOfst[15]=17 cells (5 PI)
8540 23:47:03.668281 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8541 23:47:03.675395 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8542 23:47:03.675478 DramC Write-DBI on
8543 23:47:03.675544 ==
8544 23:47:03.678677 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 23:47:03.681867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 23:47:03.681950 ==
8547 23:47:03.682016
8548 23:47:03.685042
8549 23:47:03.685124 TX Vref Scan disable
8550 23:47:03.688208 == TX Byte 0 ==
8551 23:47:03.691417 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8552 23:47:03.695093 == TX Byte 1 ==
8553 23:47:03.698130 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8554 23:47:03.698213 DramC Write-DBI off
8555 23:47:03.698293
8556 23:47:03.701728 [DATLAT]
8557 23:47:03.701840 Freq=1600, CH1 RK0
8558 23:47:03.701905
8559 23:47:03.704884 DATLAT Default: 0xf
8560 23:47:03.704966 0, 0xFFFF, sum = 0
8561 23:47:03.708677 1, 0xFFFF, sum = 0
8562 23:47:03.708776 2, 0xFFFF, sum = 0
8563 23:47:03.711589 3, 0xFFFF, sum = 0
8564 23:47:03.711712 4, 0xFFFF, sum = 0
8565 23:47:03.715108 5, 0xFFFF, sum = 0
8566 23:47:03.715236 6, 0xFFFF, sum = 0
8567 23:47:03.718228 7, 0xFFFF, sum = 0
8568 23:47:03.721325 8, 0xFFFF, sum = 0
8569 23:47:03.721411 9, 0xFFFF, sum = 0
8570 23:47:03.725018 10, 0xFFFF, sum = 0
8571 23:47:03.725093 11, 0xFFFF, sum = 0
8572 23:47:03.728173 12, 0xFFFF, sum = 0
8573 23:47:03.728250 13, 0xFFFF, sum = 0
8574 23:47:03.731345 14, 0x0, sum = 1
8575 23:47:03.731420 15, 0x0, sum = 2
8576 23:47:03.735022 16, 0x0, sum = 3
8577 23:47:03.735098 17, 0x0, sum = 4
8578 23:47:03.737877 best_step = 15
8579 23:47:03.737970
8580 23:47:03.738033 ==
8581 23:47:03.741763 Dram Type= 6, Freq= 0, CH_1, rank 0
8582 23:47:03.744752 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8583 23:47:03.744844 ==
8584 23:47:03.744962 RX Vref Scan: 1
8585 23:47:03.745072
8586 23:47:03.748258 Set Vref Range= 24 -> 127
8587 23:47:03.748335
8588 23:47:03.751516 RX Vref 24 -> 127, step: 1
8589 23:47:03.751623
8590 23:47:03.754585 RX Delay 27 -> 252, step: 4
8591 23:47:03.754666
8592 23:47:03.758248 Set Vref, RX VrefLevel [Byte0]: 24
8593 23:47:03.761567 [Byte1]: 24
8594 23:47:03.761640
8595 23:47:03.764659 Set Vref, RX VrefLevel [Byte0]: 25
8596 23:47:03.768064 [Byte1]: 25
8597 23:47:03.768144
8598 23:47:03.771268 Set Vref, RX VrefLevel [Byte0]: 26
8599 23:47:03.774484 [Byte1]: 26
8600 23:47:03.778524
8601 23:47:03.778630 Set Vref, RX VrefLevel [Byte0]: 27
8602 23:47:03.781623 [Byte1]: 27
8603 23:47:03.785587
8604 23:47:03.785681 Set Vref, RX VrefLevel [Byte0]: 28
8605 23:47:03.788774 [Byte1]: 28
8606 23:47:03.793224
8607 23:47:03.793307 Set Vref, RX VrefLevel [Byte0]: 29
8608 23:47:03.796505 [Byte1]: 29
8609 23:47:03.800617
8610 23:47:03.800697 Set Vref, RX VrefLevel [Byte0]: 30
8611 23:47:03.804294 [Byte1]: 30
8612 23:47:03.808553
8613 23:47:03.808631 Set Vref, RX VrefLevel [Byte0]: 31
8614 23:47:03.811729 [Byte1]: 31
8615 23:47:03.815591
8616 23:47:03.815713 Set Vref, RX VrefLevel [Byte0]: 32
8617 23:47:03.819336 [Byte1]: 32
8618 23:47:03.823046
8619 23:47:03.823155 Set Vref, RX VrefLevel [Byte0]: 33
8620 23:47:03.826929 [Byte1]: 33
8621 23:47:03.830986
8622 23:47:03.831091 Set Vref, RX VrefLevel [Byte0]: 34
8623 23:47:03.834139 [Byte1]: 34
8624 23:47:03.838629
8625 23:47:03.838707 Set Vref, RX VrefLevel [Byte0]: 35
8626 23:47:03.841730 [Byte1]: 35
8627 23:47:03.845993
8628 23:47:03.846077 Set Vref, RX VrefLevel [Byte0]: 36
8629 23:47:03.849481 [Byte1]: 36
8630 23:47:03.853364
8631 23:47:03.853446 Set Vref, RX VrefLevel [Byte0]: 37
8632 23:47:03.856770 [Byte1]: 37
8633 23:47:03.860823
8634 23:47:03.860903 Set Vref, RX VrefLevel [Byte0]: 38
8635 23:47:03.864763 [Byte1]: 38
8636 23:47:03.868492
8637 23:47:03.868601 Set Vref, RX VrefLevel [Byte0]: 39
8638 23:47:03.872449 [Byte1]: 39
8639 23:47:03.876409
8640 23:47:03.876486 Set Vref, RX VrefLevel [Byte0]: 40
8641 23:47:03.879689 [Byte1]: 40
8642 23:47:03.883592
8643 23:47:03.883679 Set Vref, RX VrefLevel [Byte0]: 41
8644 23:47:03.886679 [Byte1]: 41
8645 23:47:03.891212
8646 23:47:03.891298 Set Vref, RX VrefLevel [Byte0]: 42
8647 23:47:03.894425 [Byte1]: 42
8648 23:47:03.898344
8649 23:47:03.898428 Set Vref, RX VrefLevel [Byte0]: 43
8650 23:47:03.902195 [Byte1]: 43
8651 23:47:03.906444
8652 23:47:03.906555 Set Vref, RX VrefLevel [Byte0]: 44
8653 23:47:03.909724 [Byte1]: 44
8654 23:47:03.914039
8655 23:47:03.914118 Set Vref, RX VrefLevel [Byte0]: 45
8656 23:47:03.917087 [Byte1]: 45
8657 23:47:03.921054
8658 23:47:03.921130 Set Vref, RX VrefLevel [Byte0]: 46
8659 23:47:03.924373 [Byte1]: 46
8660 23:47:03.928925
8661 23:47:03.929003 Set Vref, RX VrefLevel [Byte0]: 47
8662 23:47:03.932056 [Byte1]: 47
8663 23:47:03.936447
8664 23:47:03.936523 Set Vref, RX VrefLevel [Byte0]: 48
8665 23:47:03.939883 [Byte1]: 48
8666 23:47:03.943867
8667 23:47:03.943941 Set Vref, RX VrefLevel [Byte0]: 49
8668 23:47:03.947240 [Byte1]: 49
8669 23:47:03.951653
8670 23:47:03.951728 Set Vref, RX VrefLevel [Byte0]: 50
8671 23:47:03.954849 [Byte1]: 50
8672 23:47:03.959376
8673 23:47:03.959487 Set Vref, RX VrefLevel [Byte0]: 51
8674 23:47:03.962368 [Byte1]: 51
8675 23:47:03.966513
8676 23:47:03.966589 Set Vref, RX VrefLevel [Byte0]: 52
8677 23:47:03.969945 [Byte1]: 52
8678 23:47:03.974049
8679 23:47:03.974128 Set Vref, RX VrefLevel [Byte0]: 53
8680 23:47:03.977387 [Byte1]: 53
8681 23:47:03.981394
8682 23:47:03.981469 Set Vref, RX VrefLevel [Byte0]: 54
8683 23:47:03.985151 [Byte1]: 54
8684 23:47:03.989348
8685 23:47:03.989424 Set Vref, RX VrefLevel [Byte0]: 55
8686 23:47:03.992125 [Byte1]: 55
8687 23:47:03.996720
8688 23:47:03.996802 Set Vref, RX VrefLevel [Byte0]: 56
8689 23:47:04.000066 [Byte1]: 56
8690 23:47:04.003864
8691 23:47:04.003940 Set Vref, RX VrefLevel [Byte0]: 57
8692 23:47:04.007932 [Byte1]: 57
8693 23:47:04.011472
8694 23:47:04.011551 Set Vref, RX VrefLevel [Byte0]: 58
8695 23:47:04.014689 [Byte1]: 58
8696 23:47:04.019202
8697 23:47:04.019335 Set Vref, RX VrefLevel [Byte0]: 59
8698 23:47:04.022743 [Byte1]: 59
8699 23:47:04.026474
8700 23:47:04.026575 Set Vref, RX VrefLevel [Byte0]: 60
8701 23:47:04.030192 [Byte1]: 60
8702 23:47:04.034155
8703 23:47:04.034237 Set Vref, RX VrefLevel [Byte0]: 61
8704 23:47:04.037934 [Byte1]: 61
8705 23:47:04.041780
8706 23:47:04.041856 Set Vref, RX VrefLevel [Byte0]: 62
8707 23:47:04.045231 [Byte1]: 62
8708 23:47:04.049480
8709 23:47:04.049563 Set Vref, RX VrefLevel [Byte0]: 63
8710 23:47:04.052724 [Byte1]: 63
8711 23:47:04.056862
8712 23:47:04.056942 Set Vref, RX VrefLevel [Byte0]: 64
8713 23:47:04.060180 [Byte1]: 64
8714 23:47:04.064437
8715 23:47:04.064513 Set Vref, RX VrefLevel [Byte0]: 65
8716 23:47:04.067865 [Byte1]: 65
8717 23:47:04.071639
8718 23:47:04.071724 Set Vref, RX VrefLevel [Byte0]: 66
8719 23:47:04.075270 [Byte1]: 66
8720 23:47:04.079208
8721 23:47:04.079291 Set Vref, RX VrefLevel [Byte0]: 67
8722 23:47:04.082985 [Byte1]: 67
8723 23:47:04.086834
8724 23:47:04.086921 Set Vref, RX VrefLevel [Byte0]: 68
8725 23:47:04.090453 [Byte1]: 68
8726 23:47:04.094948
8727 23:47:04.095056 Set Vref, RX VrefLevel [Byte0]: 69
8728 23:47:04.098024 [Byte1]: 69
8729 23:47:04.102330
8730 23:47:04.102442 Set Vref, RX VrefLevel [Byte0]: 70
8731 23:47:04.105477 [Byte1]: 70
8732 23:47:04.109593
8733 23:47:04.109668 Set Vref, RX VrefLevel [Byte0]: 71
8734 23:47:04.112859 [Byte1]: 71
8735 23:47:04.117629
8736 23:47:04.117735 Final RX Vref Byte 0 = 58 to rank0
8737 23:47:04.120618 Final RX Vref Byte 1 = 56 to rank0
8738 23:47:04.123670 Final RX Vref Byte 0 = 58 to rank1
8739 23:47:04.127448 Final RX Vref Byte 1 = 56 to rank1==
8740 23:47:04.130431 Dram Type= 6, Freq= 0, CH_1, rank 0
8741 23:47:04.137275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8742 23:47:04.137382 ==
8743 23:47:04.137477 DQS Delay:
8744 23:47:04.137549 DQS0 = 0, DQS1 = 0
8745 23:47:04.140646 DQM Delay:
8746 23:47:04.140719 DQM0 = 134, DQM1 = 131
8747 23:47:04.143809 DQ Delay:
8748 23:47:04.146994 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8749 23:47:04.150380 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8750 23:47:04.153613 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8751 23:47:04.157628 DQ12 =140, DQ13 =138, DQ14 =140, DQ15 =140
8752 23:47:04.157703
8753 23:47:04.157766
8754 23:47:04.157833
8755 23:47:04.160874 [DramC_TX_OE_Calibration] TA2
8756 23:47:04.163974 Original DQ_B0 (3 6) =30, OEN = 27
8757 23:47:04.167030 Original DQ_B1 (3 6) =30, OEN = 27
8758 23:47:04.170534 24, 0x0, End_B0=24 End_B1=24
8759 23:47:04.170644 25, 0x0, End_B0=25 End_B1=25
8760 23:47:04.173559 26, 0x0, End_B0=26 End_B1=26
8761 23:47:04.176935 27, 0x0, End_B0=27 End_B1=27
8762 23:47:04.180551 28, 0x0, End_B0=28 End_B1=28
8763 23:47:04.180665 29, 0x0, End_B0=29 End_B1=29
8764 23:47:04.183590 30, 0x0, End_B0=30 End_B1=30
8765 23:47:04.186781 31, 0x4141, End_B0=30 End_B1=30
8766 23:47:04.190379 Byte0 end_step=30 best_step=27
8767 23:47:04.193505 Byte1 end_step=30 best_step=27
8768 23:47:04.197183 Byte0 TX OE(2T, 0.5T) = (3, 3)
8769 23:47:04.197300 Byte1 TX OE(2T, 0.5T) = (3, 3)
8770 23:47:04.197405
8771 23:47:04.200092
8772 23:47:04.207158 [DQSOSCAuto] RK0, (LSB)MR18= 0x1927, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8773 23:47:04.210352 CH1 RK0: MR19=303, MR18=1927
8774 23:47:04.217162 CH1_RK0: MR19=0x303, MR18=0x1927, DQSOSC=390, MR23=63, INC=24, DEC=16
8775 23:47:04.217246
8776 23:47:04.220049 ----->DramcWriteLeveling(PI) begin...
8777 23:47:04.220160 ==
8778 23:47:04.223387 Dram Type= 6, Freq= 0, CH_1, rank 1
8779 23:47:04.226610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8780 23:47:04.226721 ==
8781 23:47:04.230350 Write leveling (Byte 0): 25 => 25
8782 23:47:04.233569 Write leveling (Byte 1): 28 => 28
8783 23:47:04.236706 DramcWriteLeveling(PI) end<-----
8784 23:47:04.236811
8785 23:47:04.236919 ==
8786 23:47:04.240250 Dram Type= 6, Freq= 0, CH_1, rank 1
8787 23:47:04.243426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 23:47:04.243510 ==
8789 23:47:04.246707 [Gating] SW mode calibration
8790 23:47:04.253373 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8791 23:47:04.260425 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8792 23:47:04.263672 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 23:47:04.266940 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 23:47:04.273567 1 4 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8795 23:47:04.276693 1 4 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8796 23:47:04.279925 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 23:47:04.286535 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 23:47:04.289995 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 23:47:04.293463 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 23:47:04.300149 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8801 23:47:04.303249 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8802 23:47:04.306594 1 5 8 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 0)
8803 23:47:04.313133 1 5 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8804 23:47:04.316860 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8805 23:47:04.319659 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 23:47:04.326764 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 23:47:04.329758 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 23:47:04.333226 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 23:47:04.340042 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 23:47:04.343025 1 6 8 | B1->B0 | 3838 2323 | 0 0 | (0 0) (0 0)
8811 23:47:04.346383 1 6 12 | B1->B0 | 4646 4242 | 0 1 | (0 0) (0 0)
8812 23:47:04.353336 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 23:47:04.356655 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 23:47:04.359967 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 23:47:04.363217 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 23:47:04.370133 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 23:47:04.373385 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8818 23:47:04.376470 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8819 23:47:04.383005 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8820 23:47:04.386325 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 23:47:04.389546 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 23:47:04.396484 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 23:47:04.399855 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 23:47:04.403157 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 23:47:04.409623 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 23:47:04.412928 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 23:47:04.416400 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 23:47:04.422882 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 23:47:04.426467 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 23:47:04.429784 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 23:47:04.436451 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 23:47:04.439341 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 23:47:04.443008 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8834 23:47:04.449775 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8835 23:47:04.452683 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8836 23:47:04.456300 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 23:47:04.459604 Total UI for P1: 0, mck2ui 16
8838 23:47:04.462973 best dqsien dly found for B0: ( 1, 9, 12)
8839 23:47:04.466254 Total UI for P1: 0, mck2ui 16
8840 23:47:04.469430 best dqsien dly found for B1: ( 1, 9, 8)
8841 23:47:04.472674 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8842 23:47:04.475936 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8843 23:47:04.476009
8844 23:47:04.479152 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8845 23:47:04.486260 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8846 23:47:04.486337 [Gating] SW calibration Done
8847 23:47:04.486412 ==
8848 23:47:04.489518 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 23:47:04.496391 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 23:47:04.496474 ==
8851 23:47:04.496539 RX Vref Scan: 0
8852 23:47:04.496601
8853 23:47:04.499634 RX Vref 0 -> 0, step: 1
8854 23:47:04.499709
8855 23:47:04.502875 RX Delay 0 -> 252, step: 8
8856 23:47:04.506107 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8857 23:47:04.509716 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8858 23:47:04.512453 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8859 23:47:04.516036 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8860 23:47:04.522709 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8861 23:47:04.526440 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8862 23:47:04.529675 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8863 23:47:04.532875 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8864 23:47:04.535979 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8865 23:47:04.542487 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8866 23:47:04.546089 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8867 23:47:04.549275 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8868 23:47:04.552727 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8869 23:47:04.559437 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8870 23:47:04.563171 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8871 23:47:04.565970 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8872 23:47:04.566046 ==
8873 23:47:04.569514 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 23:47:04.572786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 23:47:04.572895 ==
8876 23:47:04.575958 DQS Delay:
8877 23:47:04.576065 DQS0 = 0, DQS1 = 0
8878 23:47:04.579310 DQM Delay:
8879 23:47:04.579403 DQM0 = 136, DQM1 = 133
8880 23:47:04.579511 DQ Delay:
8881 23:47:04.582555 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8882 23:47:04.589056 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8883 23:47:04.592613 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8884 23:47:04.595627 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8885 23:47:04.595707
8886 23:47:04.595778
8887 23:47:04.595839 ==
8888 23:47:04.599279 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 23:47:04.602505 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 23:47:04.602581 ==
8891 23:47:04.602650
8892 23:47:04.602710
8893 23:47:04.605680 TX Vref Scan disable
8894 23:47:04.608996 == TX Byte 0 ==
8895 23:47:04.612114 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8896 23:47:04.615368 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8897 23:47:04.619052 == TX Byte 1 ==
8898 23:47:04.622203 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8899 23:47:04.625227 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8900 23:47:04.625308 ==
8901 23:47:04.628619 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 23:47:04.632001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 23:47:04.635060 ==
8904 23:47:04.646739
8905 23:47:04.650002 TX Vref early break, caculate TX vref
8906 23:47:04.653039 TX Vref=16, minBit 0, minWin=23, winSum=385
8907 23:47:04.656231 TX Vref=18, minBit 0, minWin=23, winSum=389
8908 23:47:04.659736 TX Vref=20, minBit 0, minWin=24, winSum=402
8909 23:47:04.662931 TX Vref=22, minBit 0, minWin=24, winSum=407
8910 23:47:04.666526 TX Vref=24, minBit 0, minWin=25, winSum=417
8911 23:47:04.673496 TX Vref=26, minBit 0, minWin=26, winSum=427
8912 23:47:04.676649 TX Vref=28, minBit 0, minWin=26, winSum=425
8913 23:47:04.679788 TX Vref=30, minBit 0, minWin=25, winSum=420
8914 23:47:04.682817 TX Vref=32, minBit 0, minWin=25, winSum=415
8915 23:47:04.686410 TX Vref=34, minBit 0, minWin=24, winSum=402
8916 23:47:04.693148 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
8917 23:47:04.693233
8918 23:47:04.696128 Final TX Range 0 Vref 26
8919 23:47:04.696213
8920 23:47:04.696281 ==
8921 23:47:04.699290 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 23:47:04.702917 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 23:47:04.703002 ==
8924 23:47:04.703069
8925 23:47:04.703130
8926 23:47:04.705833 TX Vref Scan disable
8927 23:47:04.713140 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8928 23:47:04.713226 == TX Byte 0 ==
8929 23:47:04.716310 u2DelayCellOfst[0]=17 cells (5 PI)
8930 23:47:04.719543 u2DelayCellOfst[1]=10 cells (3 PI)
8931 23:47:04.722710 u2DelayCellOfst[2]=0 cells (0 PI)
8932 23:47:04.726150 u2DelayCellOfst[3]=6 cells (2 PI)
8933 23:47:04.729254 u2DelayCellOfst[4]=6 cells (2 PI)
8934 23:47:04.732747 u2DelayCellOfst[5]=17 cells (5 PI)
8935 23:47:04.735666 u2DelayCellOfst[6]=17 cells (5 PI)
8936 23:47:04.739224 u2DelayCellOfst[7]=6 cells (2 PI)
8937 23:47:04.742561 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8938 23:47:04.746061 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8939 23:47:04.749303 == TX Byte 1 ==
8940 23:47:04.749388 u2DelayCellOfst[8]=0 cells (0 PI)
8941 23:47:04.752834 u2DelayCellOfst[9]=3 cells (1 PI)
8942 23:47:04.755820 u2DelayCellOfst[10]=10 cells (3 PI)
8943 23:47:04.759529 u2DelayCellOfst[11]=6 cells (2 PI)
8944 23:47:04.762401 u2DelayCellOfst[12]=13 cells (4 PI)
8945 23:47:04.765450 u2DelayCellOfst[13]=13 cells (4 PI)
8946 23:47:04.769091 u2DelayCellOfst[14]=17 cells (5 PI)
8947 23:47:04.772155 u2DelayCellOfst[15]=17 cells (5 PI)
8948 23:47:04.776013 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8949 23:47:04.782550 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8950 23:47:04.782633 DramC Write-DBI on
8951 23:47:04.782700 ==
8952 23:47:04.785375 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 23:47:04.789075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 23:47:04.792190 ==
8955 23:47:04.792319
8956 23:47:04.792438
8957 23:47:04.792534 TX Vref Scan disable
8958 23:47:04.796189 == TX Byte 0 ==
8959 23:47:04.799157 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8960 23:47:04.802640 == TX Byte 1 ==
8961 23:47:04.805709 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8962 23:47:04.808898 DramC Write-DBI off
8963 23:47:04.809000
8964 23:47:04.809115 [DATLAT]
8965 23:47:04.809219 Freq=1600, CH1 RK1
8966 23:47:04.809342
8967 23:47:04.812400 DATLAT Default: 0xf
8968 23:47:04.812475 0, 0xFFFF, sum = 0
8969 23:47:04.816050 1, 0xFFFF, sum = 0
8970 23:47:04.816165 2, 0xFFFF, sum = 0
8971 23:47:04.818900 3, 0xFFFF, sum = 0
8972 23:47:04.822426 4, 0xFFFF, sum = 0
8973 23:47:04.822506 5, 0xFFFF, sum = 0
8974 23:47:04.825812 6, 0xFFFF, sum = 0
8975 23:47:04.825897 7, 0xFFFF, sum = 0
8976 23:47:04.829021 8, 0xFFFF, sum = 0
8977 23:47:04.829100 9, 0xFFFF, sum = 0
8978 23:47:04.832258 10, 0xFFFF, sum = 0
8979 23:47:04.832372 11, 0xFFFF, sum = 0
8980 23:47:04.835577 12, 0xFFFF, sum = 0
8981 23:47:04.835680 13, 0xFFFF, sum = 0
8982 23:47:04.838926 14, 0x0, sum = 1
8983 23:47:04.839040 15, 0x0, sum = 2
8984 23:47:04.842569 16, 0x0, sum = 3
8985 23:47:04.842648 17, 0x0, sum = 4
8986 23:47:04.845679 best_step = 15
8987 23:47:04.845756
8988 23:47:04.845821 ==
8989 23:47:04.848918 Dram Type= 6, Freq= 0, CH_1, rank 1
8990 23:47:04.852308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8991 23:47:04.852411 ==
8992 23:47:04.852496 RX Vref Scan: 0
8993 23:47:04.855511
8994 23:47:04.855592 RX Vref 0 -> 0, step: 1
8995 23:47:04.855675
8996 23:47:04.858678 RX Delay 19 -> 252, step: 4
8997 23:47:04.861924 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8998 23:47:04.868547 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8999 23:47:04.872203 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9000 23:47:04.875314 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9001 23:47:04.879015 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9002 23:47:04.882092 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9003 23:47:04.885400 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9004 23:47:04.891813 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9005 23:47:04.895764 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
9006 23:47:04.898746 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9007 23:47:04.901762 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9008 23:47:04.905563 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9009 23:47:04.912148 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9010 23:47:04.915104 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9011 23:47:04.918826 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9012 23:47:04.922087 iDelay=195, Bit 15, Center 142 (91 ~ 194) 104
9013 23:47:04.922172 ==
9014 23:47:04.925408 Dram Type= 6, Freq= 0, CH_1, rank 1
9015 23:47:04.931939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9016 23:47:04.932046 ==
9017 23:47:04.932148 DQS Delay:
9018 23:47:04.934955 DQS0 = 0, DQS1 = 0
9019 23:47:04.935038 DQM Delay:
9020 23:47:04.938471 DQM0 = 134, DQM1 = 131
9021 23:47:04.938547 DQ Delay:
9022 23:47:04.941605 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9023 23:47:04.945163 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9024 23:47:04.948364 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9025 23:47:04.951561 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =142
9026 23:47:04.951634
9027 23:47:04.951698
9028 23:47:04.951763
9029 23:47:04.954881 [DramC_TX_OE_Calibration] TA2
9030 23:47:04.958013 Original DQ_B0 (3 6) =30, OEN = 27
9031 23:47:04.961654 Original DQ_B1 (3 6) =30, OEN = 27
9032 23:47:04.965129 24, 0x0, End_B0=24 End_B1=24
9033 23:47:04.968443 25, 0x0, End_B0=25 End_B1=25
9034 23:47:04.968531 26, 0x0, End_B0=26 End_B1=26
9035 23:47:04.971685 27, 0x0, End_B0=27 End_B1=27
9036 23:47:04.974946 28, 0x0, End_B0=28 End_B1=28
9037 23:47:04.978165 29, 0x0, End_B0=29 End_B1=29
9038 23:47:04.978244 30, 0x0, End_B0=30 End_B1=30
9039 23:47:04.981824 31, 0x4141, End_B0=30 End_B1=30
9040 23:47:04.984953 Byte0 end_step=30 best_step=27
9041 23:47:04.988193 Byte1 end_step=30 best_step=27
9042 23:47:04.991813 Byte0 TX OE(2T, 0.5T) = (3, 3)
9043 23:47:04.995184 Byte1 TX OE(2T, 0.5T) = (3, 3)
9044 23:47:04.995269
9045 23:47:04.995336
9046 23:47:05.001607 [DQSOSCAuto] RK1, (LSB)MR18= 0x2409, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
9047 23:47:05.004912 CH1 RK1: MR19=303, MR18=2409
9048 23:47:05.011194 CH1_RK1: MR19=0x303, MR18=0x2409, DQSOSC=391, MR23=63, INC=24, DEC=16
9049 23:47:05.014761 [RxdqsGatingPostProcess] freq 1600
9050 23:47:05.018147 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9051 23:47:05.021276 best DQS0 dly(2T, 0.5T) = (1, 1)
9052 23:47:05.024604 best DQS1 dly(2T, 0.5T) = (1, 1)
9053 23:47:05.027774 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9054 23:47:05.031241 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9055 23:47:05.035002 best DQS0 dly(2T, 0.5T) = (1, 1)
9056 23:47:05.038102 best DQS1 dly(2T, 0.5T) = (1, 1)
9057 23:47:05.041274 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9058 23:47:05.044608 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9059 23:47:05.047873 Pre-setting of DQS Precalculation
9060 23:47:05.051545 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9061 23:47:05.057837 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9062 23:47:05.068236 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9063 23:47:05.068322
9064 23:47:05.068408
9065 23:47:05.071444 [Calibration Summary] 3200 Mbps
9066 23:47:05.071529 CH 0, Rank 0
9067 23:47:05.074456 SW Impedance : PASS
9068 23:47:05.074540 DUTY Scan : NO K
9069 23:47:05.077909 ZQ Calibration : PASS
9070 23:47:05.081397 Jitter Meter : NO K
9071 23:47:05.081481 CBT Training : PASS
9072 23:47:05.084556 Write leveling : PASS
9073 23:47:05.084642 RX DQS gating : PASS
9074 23:47:05.087691 RX DQ/DQS(RDDQC) : PASS
9075 23:47:05.091121 TX DQ/DQS : PASS
9076 23:47:05.091232 RX DATLAT : PASS
9077 23:47:05.094219 RX DQ/DQS(Engine): PASS
9078 23:47:05.097985 TX OE : PASS
9079 23:47:05.098070 All Pass.
9080 23:47:05.098138
9081 23:47:05.098200 CH 0, Rank 1
9082 23:47:05.101366 SW Impedance : PASS
9083 23:47:05.104541 DUTY Scan : NO K
9084 23:47:05.104626 ZQ Calibration : PASS
9085 23:47:05.107687 Jitter Meter : NO K
9086 23:47:05.111067 CBT Training : PASS
9087 23:47:05.111152 Write leveling : PASS
9088 23:47:05.114133 RX DQS gating : PASS
9089 23:47:05.118063 RX DQ/DQS(RDDQC) : PASS
9090 23:47:05.118148 TX DQ/DQS : PASS
9091 23:47:05.121032 RX DATLAT : PASS
9092 23:47:05.124651 RX DQ/DQS(Engine): PASS
9093 23:47:05.124736 TX OE : PASS
9094 23:47:05.124804 All Pass.
9095 23:47:05.127820
9096 23:47:05.127904 CH 1, Rank 0
9097 23:47:05.131022 SW Impedance : PASS
9098 23:47:05.131107 DUTY Scan : NO K
9099 23:47:05.134077 ZQ Calibration : PASS
9100 23:47:05.134162 Jitter Meter : NO K
9101 23:47:05.137442 CBT Training : PASS
9102 23:47:05.140876 Write leveling : PASS
9103 23:47:05.140961 RX DQS gating : PASS
9104 23:47:05.144183 RX DQ/DQS(RDDQC) : PASS
9105 23:47:05.147532 TX DQ/DQS : PASS
9106 23:47:05.147617 RX DATLAT : PASS
9107 23:47:05.151084 RX DQ/DQS(Engine): PASS
9108 23:47:05.154294 TX OE : PASS
9109 23:47:05.154388 All Pass.
9110 23:47:05.154459
9111 23:47:05.154560 CH 1, Rank 1
9112 23:47:05.157731 SW Impedance : PASS
9113 23:47:05.160773 DUTY Scan : NO K
9114 23:47:05.160860 ZQ Calibration : PASS
9115 23:47:05.163949 Jitter Meter : NO K
9116 23:47:05.167797 CBT Training : PASS
9117 23:47:05.167885 Write leveling : PASS
9118 23:47:05.170853 RX DQS gating : PASS
9119 23:47:05.174470 RX DQ/DQS(RDDQC) : PASS
9120 23:47:05.174577 TX DQ/DQS : PASS
9121 23:47:05.177283 RX DATLAT : PASS
9122 23:47:05.180596 RX DQ/DQS(Engine): PASS
9123 23:47:05.180679 TX OE : PASS
9124 23:47:05.180789 All Pass.
9125 23:47:05.180877
9126 23:47:05.184535 DramC Write-DBI on
9127 23:47:05.187498 PER_BANK_REFRESH: Hybrid Mode
9128 23:47:05.187582 TX_TRACKING: ON
9129 23:47:05.197493 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9130 23:47:05.204084 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9131 23:47:05.213586 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9132 23:47:05.217481 [FAST_K] Save calibration result to emmc
9133 23:47:05.220776 sync common calibartion params.
9134 23:47:05.220862 sync cbt_mode0:1, 1:1
9135 23:47:05.224055 dram_init: ddr_geometry: 2
9136 23:47:05.227286 dram_init: ddr_geometry: 2
9137 23:47:05.227371 dram_init: ddr_geometry: 2
9138 23:47:05.230297 0:dram_rank_size:100000000
9139 23:47:05.233879 1:dram_rank_size:100000000
9140 23:47:05.236999 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9141 23:47:05.240232 DFS_SHUFFLE_HW_MODE: ON
9142 23:47:05.243398 dramc_set_vcore_voltage set vcore to 725000
9143 23:47:05.246947 Read voltage for 1600, 0
9144 23:47:05.247055 Vio18 = 0
9145 23:47:05.250717 Vcore = 725000
9146 23:47:05.250793 Vdram = 0
9147 23:47:05.250863 Vddq = 0
9148 23:47:05.250926 Vmddr = 0
9149 23:47:05.253540 switch to 3200 Mbps bootup
9150 23:47:05.257179 [DramcRunTimeConfig]
9151 23:47:05.257261 PHYPLL
9152 23:47:05.260391 DPM_CONTROL_AFTERK: ON
9153 23:47:05.260501 PER_BANK_REFRESH: ON
9154 23:47:05.263912 REFRESH_OVERHEAD_REDUCTION: ON
9155 23:47:05.266870 CMD_PICG_NEW_MODE: OFF
9156 23:47:05.266947 XRTWTW_NEW_MODE: ON
9157 23:47:05.270104 XRTRTR_NEW_MODE: ON
9158 23:47:05.270177 TX_TRACKING: ON
9159 23:47:05.273339 RDSEL_TRACKING: OFF
9160 23:47:05.277159 DQS Precalculation for DVFS: ON
9161 23:47:05.277235 RX_TRACKING: OFF
9162 23:47:05.280218 HW_GATING DBG: ON
9163 23:47:05.280328 ZQCS_ENABLE_LP4: ON
9164 23:47:05.283844 RX_PICG_NEW_MODE: ON
9165 23:47:05.283917 TX_PICG_NEW_MODE: ON
9166 23:47:05.286911 ENABLE_RX_DCM_DPHY: ON
9167 23:47:05.290342 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9168 23:47:05.293744 DUMMY_READ_FOR_TRACKING: OFF
9169 23:47:05.293829 !!! SPM_CONTROL_AFTERK: OFF
9170 23:47:05.296857 !!! SPM could not control APHY
9171 23:47:05.300511 IMPEDANCE_TRACKING: ON
9172 23:47:05.300586 TEMP_SENSOR: ON
9173 23:47:05.303809 HW_SAVE_FOR_SR: OFF
9174 23:47:05.307019 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9175 23:47:05.310207 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9176 23:47:05.310283 Read ODT Tracking: ON
9177 23:47:05.313402 Refresh Rate DeBounce: ON
9178 23:47:05.316481 DFS_NO_QUEUE_FLUSH: ON
9179 23:47:05.320358 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9180 23:47:05.320433 ENABLE_DFS_RUNTIME_MRW: OFF
9181 23:47:05.323555 DDR_RESERVE_NEW_MODE: ON
9182 23:47:05.327052 MR_CBT_SWITCH_FREQ: ON
9183 23:47:05.327134 =========================
9184 23:47:05.347101 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9185 23:47:05.350208 dram_init: ddr_geometry: 2
9186 23:47:05.368395 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9187 23:47:05.371798 dram_init: dram init end (result: 0)
9188 23:47:05.378514 DRAM-K: Full calibration passed in 24410 msecs
9189 23:47:05.381563 MRC: failed to locate region type 0.
9190 23:47:05.381650 DRAM rank0 size:0x100000000,
9191 23:47:05.384746 DRAM rank1 size=0x100000000
9192 23:47:05.394908 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9193 23:47:05.401551 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9194 23:47:05.408200 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9195 23:47:05.414460 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9196 23:47:05.417794 DRAM rank0 size:0x100000000,
9197 23:47:05.421461 DRAM rank1 size=0x100000000
9198 23:47:05.421545 CBMEM:
9199 23:47:05.424660 IMD: root @ 0xfffff000 254 entries.
9200 23:47:05.428145 IMD: root @ 0xffffec00 62 entries.
9201 23:47:05.431465 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9202 23:47:05.437911 WARNING: RO_VPD is uninitialized or empty.
9203 23:47:05.441064 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9204 23:47:05.448840 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9205 23:47:05.461385 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9206 23:47:05.472484 BS: romstage times (exec / console): total (unknown) / 23946 ms
9207 23:47:05.472609
9208 23:47:05.472683
9209 23:47:05.482364 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9210 23:47:05.485968 ARM64: Exception handlers installed.
9211 23:47:05.489127 ARM64: Testing exception
9212 23:47:05.493020 ARM64: Done test exception
9213 23:47:05.493135 Enumerating buses...
9214 23:47:05.496160 Show all devs... Before device enumeration.
9215 23:47:05.498971 Root Device: enabled 1
9216 23:47:05.502876 CPU_CLUSTER: 0: enabled 1
9217 23:47:05.502955 CPU: 00: enabled 1
9218 23:47:05.505654 Compare with tree...
9219 23:47:05.505728 Root Device: enabled 1
9220 23:47:05.508827 CPU_CLUSTER: 0: enabled 1
9221 23:47:05.512821 CPU: 00: enabled 1
9222 23:47:05.512924 Root Device scanning...
9223 23:47:05.515667 scan_static_bus for Root Device
9224 23:47:05.519158 CPU_CLUSTER: 0 enabled
9225 23:47:05.522767 scan_static_bus for Root Device done
9226 23:47:05.525753 scan_bus: bus Root Device finished in 8 msecs
9227 23:47:05.525864 done
9228 23:47:05.532464 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9229 23:47:05.535411 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9230 23:47:05.542172 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9231 23:47:05.545291 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9232 23:47:05.548890 Allocating resources...
9233 23:47:05.551862 Reading resources...
9234 23:47:05.555232 Root Device read_resources bus 0 link: 0
9235 23:47:05.555317 DRAM rank0 size:0x100000000,
9236 23:47:05.558459 DRAM rank1 size=0x100000000
9237 23:47:05.562215 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9238 23:47:05.565630 CPU: 00 missing read_resources
9239 23:47:05.568869 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9240 23:47:05.575371 Root Device read_resources bus 0 link: 0 done
9241 23:47:05.575456 Done reading resources.
9242 23:47:05.582528 Show resources in subtree (Root Device)...After reading.
9243 23:47:05.585693 Root Device child on link 0 CPU_CLUSTER: 0
9244 23:47:05.588739 CPU_CLUSTER: 0 child on link 0 CPU: 00
9245 23:47:05.598897 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9246 23:47:05.598985 CPU: 00
9247 23:47:05.602329 Root Device assign_resources, bus 0 link: 0
9248 23:47:05.605366 CPU_CLUSTER: 0 missing set_resources
9249 23:47:05.609010 Root Device assign_resources, bus 0 link: 0 done
9250 23:47:05.612277 Done setting resources.
9251 23:47:05.618896 Show resources in subtree (Root Device)...After assigning values.
9252 23:47:05.622124 Root Device child on link 0 CPU_CLUSTER: 0
9253 23:47:05.625340 CPU_CLUSTER: 0 child on link 0 CPU: 00
9254 23:47:05.635566 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9255 23:47:05.635651 CPU: 00
9256 23:47:05.638890 Done allocating resources.
9257 23:47:05.642767 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9258 23:47:05.645705 Enabling resources...
9259 23:47:05.645788 done.
9260 23:47:05.652310 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9261 23:47:05.652414 Initializing devices...
9262 23:47:05.655132 Root Device init
9263 23:47:05.655208 init hardware done!
9264 23:47:05.658999 0x00000018: ctrlr->caps
9265 23:47:05.662285 52.000 MHz: ctrlr->f_max
9266 23:47:05.662370 0.400 MHz: ctrlr->f_min
9267 23:47:05.665270 0x40ff8080: ctrlr->voltages
9268 23:47:05.665354 sclk: 390625
9269 23:47:05.668523 Bus Width = 1
9270 23:47:05.668605 sclk: 390625
9271 23:47:05.671697 Bus Width = 1
9272 23:47:05.671794 Early init status = 3
9273 23:47:05.678337 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9274 23:47:05.681565 in-header: 03 fc 00 00 01 00 00 00
9275 23:47:05.684786 in-data: 00
9276 23:47:05.688015 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9277 23:47:05.693503 in-header: 03 fd 00 00 00 00 00 00
9278 23:47:05.696723 in-data:
9279 23:47:05.700199 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9280 23:47:05.704033 in-header: 03 fc 00 00 01 00 00 00
9281 23:47:05.707950 in-data: 00
9282 23:47:05.710996 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9283 23:47:05.716296 in-header: 03 fd 00 00 00 00 00 00
9284 23:47:05.719718 in-data:
9285 23:47:05.723085 [SSUSB] Setting up USB HOST controller...
9286 23:47:05.726187 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9287 23:47:05.730041 [SSUSB] phy power-on done.
9288 23:47:05.733309 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9289 23:47:05.739959 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9290 23:47:05.743028 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9291 23:47:05.749782 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9292 23:47:05.756236 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9293 23:47:05.763065 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9294 23:47:05.769816 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9295 23:47:05.776171 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9296 23:47:05.779483 SPM: binary array size = 0x9dc
9297 23:47:05.782748 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9298 23:47:05.789717 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9299 23:47:05.796315 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9300 23:47:05.799403 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9301 23:47:05.806267 configure_display: Starting display init
9302 23:47:05.839667 anx7625_power_on_init: Init interface.
9303 23:47:05.843392 anx7625_disable_pd_protocol: Disabled PD feature.
9304 23:47:05.846996 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9305 23:47:05.874535 anx7625_start_dp_work: Secure OCM version=00
9306 23:47:05.877559 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9307 23:47:05.892224 sp_tx_get_edid_block: EDID Block = 1
9308 23:47:05.994878 Extracted contents:
9309 23:47:05.998243 header: 00 ff ff ff ff ff ff 00
9310 23:47:06.001706 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9311 23:47:06.005084 version: 01 04
9312 23:47:06.008148 basic params: 95 1f 11 78 0a
9313 23:47:06.011489 chroma info: 76 90 94 55 54 90 27 21 50 54
9314 23:47:06.014546 established: 00 00 00
9315 23:47:06.021644 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9316 23:47:06.024782 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9317 23:47:06.031352 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9318 23:47:06.037897 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9319 23:47:06.045058 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9320 23:47:06.048181 extensions: 00
9321 23:47:06.048292 checksum: fb
9322 23:47:06.048416
9323 23:47:06.051362 Manufacturer: IVO Model 57d Serial Number 0
9324 23:47:06.054406 Made week 0 of 2020
9325 23:47:06.054496 EDID version: 1.4
9326 23:47:06.058516 Digital display
9327 23:47:06.061222 6 bits per primary color channel
9328 23:47:06.061340 DisplayPort interface
9329 23:47:06.064523 Maximum image size: 31 cm x 17 cm
9330 23:47:06.067910 Gamma: 220%
9331 23:47:06.068018 Check DPMS levels
9332 23:47:06.071260 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9333 23:47:06.074815 First detailed timing is preferred timing
9334 23:47:06.077906 Established timings supported:
9335 23:47:06.081221 Standard timings supported:
9336 23:47:06.081305 Detailed timings
9337 23:47:06.087817 Hex of detail: 383680a07038204018303c0035ae10000019
9338 23:47:06.091549 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9339 23:47:06.097694 0780 0798 07c8 0820 hborder 0
9340 23:47:06.101433 0438 043b 0447 0458 vborder 0
9341 23:47:06.104285 -hsync -vsync
9342 23:47:06.104419 Did detailed timing
9343 23:47:06.107663 Hex of detail: 000000000000000000000000000000000000
9344 23:47:06.111137 Manufacturer-specified data, tag 0
9345 23:47:06.117585 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9346 23:47:06.117673 ASCII string: InfoVision
9347 23:47:06.124294 Hex of detail: 000000fe00523134304e574635205248200a
9348 23:47:06.127540 ASCII string: R140NWF5 RH
9349 23:47:06.127624 Checksum
9350 23:47:06.127689 Checksum: 0xfb (valid)
9351 23:47:06.134424 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9352 23:47:06.137467 DSI data_rate: 832800000 bps
9353 23:47:06.140888 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9354 23:47:06.147557 anx7625_parse_edid: pixelclock(138800).
9355 23:47:06.151242 hactive(1920), hsync(48), hfp(24), hbp(88)
9356 23:47:06.154786 vactive(1080), vsync(12), vfp(3), vbp(17)
9357 23:47:06.157762 anx7625_dsi_config: config dsi.
9358 23:47:06.164390 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9359 23:47:06.176849 anx7625_dsi_config: success to config DSI
9360 23:47:06.180105 anx7625_dp_start: MIPI phy setup OK.
9361 23:47:06.183291 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9362 23:47:06.186599 mtk_ddp_mode_set invalid vrefresh 60
9363 23:47:06.190058 main_disp_path_setup
9364 23:47:06.190141 ovl_layer_smi_id_en
9365 23:47:06.193733 ovl_layer_smi_id_en
9366 23:47:06.193816 ccorr_config
9367 23:47:06.193881 aal_config
9368 23:47:06.196977 gamma_config
9369 23:47:06.197060 postmask_config
9370 23:47:06.200188 dither_config
9371 23:47:06.203147 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9372 23:47:06.210329 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9373 23:47:06.213310 Root Device init finished in 555 msecs
9374 23:47:06.213393 CPU_CLUSTER: 0 init
9375 23:47:06.223537 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9376 23:47:06.226795 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9377 23:47:06.229913 APU_MBOX 0x190000b0 = 0x10001
9378 23:47:06.233681 APU_MBOX 0x190001b0 = 0x10001
9379 23:47:06.236583 APU_MBOX 0x190005b0 = 0x10001
9380 23:47:06.240056 APU_MBOX 0x190006b0 = 0x10001
9381 23:47:06.243607 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9382 23:47:06.255686 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9383 23:47:06.268387 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9384 23:47:06.275286 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9385 23:47:06.286919 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9386 23:47:06.296181 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9387 23:47:06.299394 CPU_CLUSTER: 0 init finished in 81 msecs
9388 23:47:06.302681 Devices initialized
9389 23:47:06.306105 Show all devs... After init.
9390 23:47:06.306407 Root Device: enabled 1
9391 23:47:06.309126 CPU_CLUSTER: 0: enabled 1
9392 23:47:06.312241 CPU: 00: enabled 1
9393 23:47:06.315613 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9394 23:47:06.318927 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9395 23:47:06.322061 ELOG: NV offset 0x57f000 size 0x1000
9396 23:47:06.329203 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9397 23:47:06.335739 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9398 23:47:06.338863 ELOG: Event(17) added with size 13 at 2024-06-04 23:42:25 UTC
9399 23:47:06.345650 out: cmd=0x121: 03 db 21 01 00 00 00 00
9400 23:47:06.348725 in-header: 03 01 00 00 2c 00 00 00
9401 23:47:06.359006 in-data: 5e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9402 23:47:06.365998 ELOG: Event(A1) added with size 10 at 2024-06-04 23:42:25 UTC
9403 23:47:06.372128 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9404 23:47:06.378510 ELOG: Event(A0) added with size 9 at 2024-06-04 23:42:25 UTC
9405 23:47:06.382344 elog_add_boot_reason: Logged dev mode boot
9406 23:47:06.385464 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9407 23:47:06.388630 Finalize devices...
9408 23:47:06.389071 Devices finalized
9409 23:47:06.395779 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9410 23:47:06.399176 Writing coreboot table at 0xffe64000
9411 23:47:06.402220 0. 000000000010a000-0000000000113fff: RAMSTAGE
9412 23:47:06.405453 1. 0000000040000000-00000000400fffff: RAM
9413 23:47:06.412064 2. 0000000040100000-000000004032afff: RAMSTAGE
9414 23:47:06.415304 3. 000000004032b000-00000000545fffff: RAM
9415 23:47:06.418956 4. 0000000054600000-000000005465ffff: BL31
9416 23:47:06.421636 5. 0000000054660000-00000000ffe63fff: RAM
9417 23:47:06.428687 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9418 23:47:06.432123 7. 0000000100000000-000000023fffffff: RAM
9419 23:47:06.435456 Passing 5 GPIOs to payload:
9420 23:47:06.438743 NAME | PORT | POLARITY | VALUE
9421 23:47:06.442117 EC in RW | 0x000000aa | low | undefined
9422 23:47:06.448372 EC interrupt | 0x00000005 | low | undefined
9423 23:47:06.451844 TPM interrupt | 0x000000ab | high | undefined
9424 23:47:06.458262 SD card detect | 0x00000011 | high | undefined
9425 23:47:06.461629 speaker enable | 0x00000093 | high | undefined
9426 23:47:06.465390 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9427 23:47:06.468372 in-header: 03 f9 00 00 02 00 00 00
9428 23:47:06.472079 in-data: 02 00
9429 23:47:06.472406 ADC[4]: Raw value=905096 ID=7
9430 23:47:06.475190 ADC[3]: Raw value=213441 ID=1
9431 23:47:06.478103 RAM Code: 0x71
9432 23:47:06.478494 ADC[6]: Raw value=75332 ID=0
9433 23:47:06.481745 ADC[5]: Raw value=213072 ID=1
9434 23:47:06.484923 SKU Code: 0x1
9435 23:47:06.488511 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 3b2d
9436 23:47:06.491712 coreboot table: 964 bytes.
9437 23:47:06.494767 IMD ROOT 0. 0xfffff000 0x00001000
9438 23:47:06.498025 IMD SMALL 1. 0xffffe000 0x00001000
9439 23:47:06.501182 RO MCACHE 2. 0xffffc000 0x00001104
9440 23:47:06.505065 CONSOLE 3. 0xfff7c000 0x00080000
9441 23:47:06.508231 FMAP 4. 0xfff7b000 0x00000452
9442 23:47:06.511616 TIME STAMP 5. 0xfff7a000 0x00000910
9443 23:47:06.514588 VBOOT WORK 6. 0xfff66000 0x00014000
9444 23:47:06.517862 RAMOOPS 7. 0xffe66000 0x00100000
9445 23:47:06.521960 COREBOOT 8. 0xffe64000 0x00002000
9446 23:47:06.522192 IMD small region:
9447 23:47:06.525142 IMD ROOT 0. 0xffffec00 0x00000400
9448 23:47:06.528075 VPD 1. 0xffffeb80 0x0000006c
9449 23:47:06.535093 MMC STATUS 2. 0xffffeb60 0x00000004
9450 23:47:06.538344 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9451 23:47:06.541675 Probing TPM: done!
9452 23:47:06.544866 Connected to device vid:did:rid of 1ae0:0028:00
9453 23:47:06.555088 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9454 23:47:06.558362 Initialized TPM device CR50 revision 0
9455 23:47:06.561793 Checking cr50 for pending updates
9456 23:47:06.565353 Reading cr50 TPM mode
9457 23:47:06.574055 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9458 23:47:06.580929 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9459 23:47:06.620800 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9460 23:47:06.624127 Checking segment from ROM address 0x40100000
9461 23:47:06.627871 Checking segment from ROM address 0x4010001c
9462 23:47:06.634434 Loading segment from ROM address 0x40100000
9463 23:47:06.634675 code (compression=0)
9464 23:47:06.644377 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9465 23:47:06.651042 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9466 23:47:06.651276 it's not compressed!
9467 23:47:06.657668 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9468 23:47:06.660905 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9469 23:47:06.681752 Loading segment from ROM address 0x4010001c
9470 23:47:06.682058 Entry Point 0x80000000
9471 23:47:06.684655 Loaded segments
9472 23:47:06.688038 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9473 23:47:06.694617 Jumping to boot code at 0x80000000(0xffe64000)
9474 23:47:06.701248 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9475 23:47:06.708063 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9476 23:47:06.715539 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9477 23:47:06.719054 Checking segment from ROM address 0x40100000
9478 23:47:06.722242 Checking segment from ROM address 0x4010001c
9479 23:47:06.729223 Loading segment from ROM address 0x40100000
9480 23:47:06.729307 code (compression=1)
9481 23:47:06.735716 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9482 23:47:06.745648 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9483 23:47:06.745758 using LZMA
9484 23:47:06.753944 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9485 23:47:06.761202 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9486 23:47:06.764481 Loading segment from ROM address 0x4010001c
9487 23:47:06.764564 Entry Point 0x54601000
9488 23:47:06.767906 Loaded segments
9489 23:47:06.770901 NOTICE: MT8192 bl31_setup
9490 23:47:06.777769 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9491 23:47:06.780823 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9492 23:47:06.784553 WARNING: region 0:
9493 23:47:06.787596 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9494 23:47:06.787708 WARNING: region 1:
9495 23:47:06.794304 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9496 23:47:06.797672 WARNING: region 2:
9497 23:47:06.800876 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9498 23:47:06.804654 WARNING: region 3:
9499 23:47:06.807903 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9500 23:47:06.811241 WARNING: region 4:
9501 23:47:06.817847 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9502 23:47:06.817961 WARNING: region 5:
9503 23:47:06.821320 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 23:47:06.824594 WARNING: region 6:
9505 23:47:06.827949 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 23:47:06.831361 WARNING: region 7:
9507 23:47:06.834330 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9508 23:47:06.840918 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9509 23:47:06.844088 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9510 23:47:06.847293 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9511 23:47:06.853906 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9512 23:47:06.857829 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9513 23:47:06.860983 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9514 23:47:06.867459 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9515 23:47:06.870691 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9516 23:47:06.877166 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9517 23:47:06.881018 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9518 23:47:06.884230 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9519 23:47:06.891171 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9520 23:47:06.894578 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9521 23:47:06.897626 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9522 23:47:06.904639 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9523 23:47:06.907915 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9524 23:47:06.914320 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9525 23:47:06.917881 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9526 23:47:06.920890 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9527 23:47:06.927933 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9528 23:47:06.930840 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9529 23:47:06.934449 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9530 23:47:06.941372 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9531 23:47:06.944216 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9532 23:47:06.951466 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9533 23:47:06.954542 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9534 23:47:06.957928 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9535 23:47:06.964298 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9536 23:47:06.967841 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9537 23:47:06.974209 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9538 23:47:06.978083 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9539 23:47:06.981297 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9540 23:47:06.987718 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9541 23:47:06.991067 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9542 23:47:06.994280 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9543 23:47:06.997402 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9544 23:47:07.004113 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9545 23:47:07.007593 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9546 23:47:07.011070 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9547 23:47:07.014360 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9548 23:47:07.020890 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9549 23:47:07.024489 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9550 23:47:07.027667 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9551 23:47:07.030769 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9552 23:47:07.037453 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9553 23:47:07.040965 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9554 23:47:07.044150 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9555 23:47:07.047924 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9556 23:47:07.054206 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9557 23:47:07.058109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9558 23:47:07.064061 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9559 23:47:07.067509 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9560 23:47:07.070825 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9561 23:47:07.077819 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9562 23:47:07.081022 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9563 23:47:07.088082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9564 23:47:07.091366 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9565 23:47:07.098012 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9566 23:47:07.101648 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9567 23:47:07.104637 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9568 23:47:07.111067 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9569 23:47:07.115299 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9570 23:47:07.121384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9571 23:47:07.125099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9572 23:47:07.131766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9573 23:47:07.134861 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9574 23:47:07.138432 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9575 23:47:07.144625 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9576 23:47:07.148618 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9577 23:47:07.154870 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9578 23:47:07.158309 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9579 23:47:07.164920 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9580 23:47:07.168323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9581 23:47:07.171164 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9582 23:47:07.177943 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9583 23:47:07.181773 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9584 23:47:07.188372 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9585 23:47:07.191401 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9586 23:47:07.198203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9587 23:47:07.201573 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9588 23:47:07.208232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9589 23:47:07.211489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9590 23:47:07.214636 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9591 23:47:07.221166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9592 23:47:07.225071 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9593 23:47:07.231614 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9594 23:47:07.234817 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9595 23:47:07.238455 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9596 23:47:07.244925 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9597 23:47:07.247865 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9598 23:47:07.254779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9599 23:47:07.258497 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9600 23:47:07.264948 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9601 23:47:07.268028 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9602 23:47:07.275027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9603 23:47:07.278297 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9604 23:47:07.281824 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9605 23:47:07.288027 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9606 23:47:07.291416 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9607 23:47:07.294604 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9608 23:47:07.297832 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9609 23:47:07.304430 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9610 23:47:07.308329 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9611 23:47:07.311623 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9612 23:47:07.318148 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9613 23:47:07.321341 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9614 23:47:07.328299 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9615 23:47:07.331179 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9616 23:47:07.334580 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9617 23:47:07.341065 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9618 23:47:07.344915 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9619 23:47:07.351103 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9620 23:47:07.354355 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9621 23:47:07.357870 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9622 23:47:07.365140 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9623 23:47:07.368402 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9624 23:47:07.371927 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9625 23:47:07.378085 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9626 23:47:07.381064 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9627 23:47:07.384522 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9628 23:47:07.387910 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9629 23:47:07.394717 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9630 23:47:07.397847 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9631 23:47:07.401014 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9632 23:47:07.407797 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9633 23:47:07.410980 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9634 23:47:07.414656 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9635 23:47:07.421263 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9636 23:47:07.424310 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9637 23:47:07.431557 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9638 23:47:07.434321 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9639 23:47:07.437686 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9640 23:47:07.444738 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9641 23:47:07.447765 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9642 23:47:07.451033 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9643 23:47:07.458100 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9644 23:47:07.461531 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9645 23:47:07.467995 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9646 23:47:07.471893 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9647 23:47:07.475168 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9648 23:47:07.481757 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9649 23:47:07.484885 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9650 23:47:07.488357 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9651 23:47:07.494969 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9652 23:47:07.498393 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9653 23:47:07.504827 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9654 23:47:07.507825 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9655 23:47:07.511608 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9656 23:47:07.518033 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9657 23:47:07.521219 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9658 23:47:07.528300 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9659 23:47:07.531837 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9660 23:47:07.534910 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9661 23:47:07.541581 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9662 23:47:07.545209 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9663 23:47:07.548156 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9664 23:47:07.555060 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9665 23:47:07.558654 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9666 23:47:07.565370 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9667 23:47:07.568629 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9668 23:47:07.572120 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9669 23:47:07.578589 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9670 23:47:07.582027 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9671 23:47:07.585693 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9672 23:47:07.592308 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9673 23:47:07.595498 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9674 23:47:07.602198 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9675 23:47:07.605495 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9676 23:47:07.608452 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9677 23:47:07.614917 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9678 23:47:07.618659 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9679 23:47:07.625063 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9680 23:47:07.628149 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9681 23:47:07.631872 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9682 23:47:07.638604 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9683 23:47:07.642097 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9684 23:47:07.648495 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9685 23:47:07.651919 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9686 23:47:07.654866 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9687 23:47:07.661879 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9688 23:47:07.665362 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9689 23:47:07.668168 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9690 23:47:07.674720 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9691 23:47:07.678204 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9692 23:47:07.685037 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9693 23:47:07.688042 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9694 23:47:07.691374 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9695 23:47:07.698383 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9696 23:47:07.701302 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9697 23:47:07.708047 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9698 23:47:07.711207 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9699 23:47:07.717999 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9700 23:47:07.721520 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9701 23:47:07.724564 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9702 23:47:07.731097 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9703 23:47:07.734555 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9704 23:47:07.740951 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9705 23:47:07.744494 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9706 23:47:07.747994 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9707 23:47:07.754572 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9708 23:47:07.757663 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9709 23:47:07.764788 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9710 23:47:07.768023 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9711 23:47:07.771274 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9712 23:47:07.778222 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9713 23:47:07.781377 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9714 23:47:07.787799 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9715 23:47:07.790902 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9716 23:47:07.794309 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9717 23:47:07.801158 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9718 23:47:07.804545 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9719 23:47:07.811475 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9720 23:47:07.814587 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9721 23:47:07.821041 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9722 23:47:07.824253 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9723 23:47:07.828101 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9724 23:47:07.834512 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9725 23:47:07.837653 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9726 23:47:07.844692 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9727 23:47:07.848201 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9728 23:47:07.854723 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9729 23:47:07.858292 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9730 23:47:07.861349 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9731 23:47:07.868303 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9732 23:47:07.871557 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9733 23:47:07.878098 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9734 23:47:07.881252 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9735 23:47:07.884540 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9736 23:47:07.891302 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9737 23:47:07.894458 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9738 23:47:07.897623 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9739 23:47:07.900859 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9740 23:47:07.907348 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9741 23:47:07.911066 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9742 23:47:07.913953 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9743 23:47:07.920777 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9744 23:47:07.924571 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9745 23:47:07.931021 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9746 23:47:07.934400 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9747 23:47:07.937239 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9748 23:47:07.944130 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9749 23:47:07.947395 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9750 23:47:07.950595 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9751 23:47:07.957148 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9752 23:47:07.960705 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9753 23:47:07.963727 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9754 23:47:07.970895 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9755 23:47:07.974134 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9756 23:47:07.976911 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9757 23:47:07.984062 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9758 23:47:07.987110 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9759 23:47:07.993938 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9760 23:47:07.997316 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9761 23:47:08.000529 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9762 23:47:08.007692 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9763 23:47:08.010920 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9764 23:47:08.013896 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9765 23:47:08.020694 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9766 23:47:08.024166 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9767 23:47:08.027282 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9768 23:47:08.033646 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9769 23:47:08.036937 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9770 23:47:08.043886 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9771 23:47:08.047277 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9772 23:47:08.050484 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9773 23:47:08.056953 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9774 23:47:08.060469 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9775 23:47:08.066687 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9776 23:47:08.070025 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9777 23:47:08.073184 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9778 23:47:08.076318 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9779 23:47:08.080191 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9780 23:47:08.086502 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9781 23:47:08.089742 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9782 23:47:08.093284 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9783 23:47:08.096913 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9784 23:47:08.103176 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9785 23:47:08.107024 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9786 23:47:08.110355 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9787 23:47:08.113390 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9788 23:47:08.120109 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9789 23:47:08.123146 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9790 23:47:08.126410 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9791 23:47:08.132823 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9792 23:47:08.136598 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9793 23:47:08.143356 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9794 23:47:08.146271 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9795 23:47:08.153001 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9796 23:47:08.155957 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9797 23:47:08.159432 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9798 23:47:08.165881 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9799 23:47:08.169325 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9800 23:47:08.175739 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9801 23:47:08.179149 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9802 23:47:08.182273 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9803 23:47:08.189457 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9804 23:47:08.192800 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9805 23:47:08.199232 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9806 23:47:08.202207 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9807 23:47:08.206039 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9808 23:47:08.212409 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9809 23:47:08.215641 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9810 23:47:08.222099 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9811 23:47:08.225434 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9812 23:47:08.232948 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9813 23:47:08.236194 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9814 23:47:08.239002 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9815 23:47:08.245576 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9816 23:47:08.248803 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9817 23:47:08.256008 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9818 23:47:08.258818 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9819 23:47:08.261979 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9820 23:47:08.269077 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9821 23:47:08.272161 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9822 23:47:08.278798 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9823 23:47:08.281884 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9824 23:47:08.285541 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9825 23:47:08.292133 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9826 23:47:08.295291 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9827 23:47:08.301965 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9828 23:47:08.304989 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9829 23:47:08.308767 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9830 23:47:08.315225 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9831 23:47:08.318566 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9832 23:47:08.324863 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9833 23:47:08.328277 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9834 23:47:08.334814 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9835 23:47:08.338691 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9836 23:47:08.341398 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9837 23:47:08.348487 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9838 23:47:08.351810 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9839 23:47:08.358339 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9840 23:47:08.361772 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9841 23:47:08.365089 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9842 23:47:08.371564 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9843 23:47:08.375012 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9844 23:47:08.381737 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9845 23:47:08.384936 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9846 23:47:08.388033 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9847 23:47:08.394971 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9848 23:47:08.398136 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9849 23:47:08.405194 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9850 23:47:08.408802 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9851 23:47:08.411473 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9852 23:47:08.418144 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9853 23:47:08.421225 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9854 23:47:08.428151 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9855 23:47:08.431349 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9856 23:47:08.435077 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9857 23:47:08.441743 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9858 23:47:08.444513 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9859 23:47:08.451373 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9860 23:47:08.454664 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9861 23:47:08.457960 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9862 23:47:08.464911 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9863 23:47:08.467709 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9864 23:47:08.474869 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9865 23:47:08.478135 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9866 23:47:08.484311 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9867 23:47:08.487753 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9868 23:47:08.494389 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9869 23:47:08.498017 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9870 23:47:08.501351 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9871 23:47:08.507792 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9872 23:47:08.511237 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9873 23:47:08.517761 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9874 23:47:08.521141 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9875 23:47:08.527763 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9876 23:47:08.530811 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9877 23:47:08.534045 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9878 23:47:08.540826 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9879 23:47:08.544202 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9880 23:47:08.551095 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9881 23:47:08.554122 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9882 23:47:08.560967 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9883 23:47:08.564277 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9884 23:47:08.570807 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9885 23:47:08.574153 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9886 23:47:08.577298 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9887 23:47:08.584105 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9888 23:47:08.587062 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9889 23:47:08.593925 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9890 23:47:08.597341 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9891 23:47:08.603683 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9892 23:47:08.607249 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9893 23:47:08.610519 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9894 23:47:08.617117 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9895 23:47:08.620460 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9896 23:47:08.627273 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9897 23:47:08.630557 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9898 23:47:08.637008 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9899 23:47:08.640245 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9900 23:47:08.646640 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9901 23:47:08.650742 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9902 23:47:08.653809 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9903 23:47:08.660303 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9904 23:47:08.663467 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9905 23:47:08.670329 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9906 23:47:08.673621 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9907 23:47:08.680405 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9908 23:47:08.683689 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9909 23:47:08.686960 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9910 23:47:08.693882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9911 23:47:08.697244 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9912 23:47:08.703866 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9913 23:47:08.707206 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9914 23:47:08.713390 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9915 23:47:08.716771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9916 23:47:08.719998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9917 23:47:08.727177 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9918 23:47:08.730106 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9919 23:47:08.736765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9920 23:47:08.740050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9921 23:47:08.746510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9922 23:47:08.749765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9923 23:47:08.756609 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9924 23:47:08.759876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9925 23:47:08.766289 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9926 23:47:08.769699 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9927 23:47:08.776464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9928 23:47:08.779688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9929 23:47:08.786383 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9930 23:47:08.789698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9931 23:47:08.796402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9932 23:47:08.799309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9933 23:47:08.806068 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9934 23:47:08.810128 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9935 23:47:08.816321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9936 23:47:08.819469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9937 23:47:08.826444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9938 23:47:08.829669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9939 23:47:08.836000 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9940 23:47:08.839511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9941 23:47:08.846180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9942 23:47:08.849534 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9943 23:47:08.852866 INFO: [APUAPC] vio 0
9944 23:47:08.856293 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9945 23:47:08.862933 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9946 23:47:08.866196 INFO: [APUAPC] D0_APC_0: 0x400510
9947 23:47:08.866279 INFO: [APUAPC] D0_APC_1: 0x0
9948 23:47:08.869303 INFO: [APUAPC] D0_APC_2: 0x1540
9949 23:47:08.872539 INFO: [APUAPC] D0_APC_3: 0x0
9950 23:47:08.875943 INFO: [APUAPC] D1_APC_0: 0xffffffff
9951 23:47:08.879604 INFO: [APUAPC] D1_APC_1: 0xffffffff
9952 23:47:08.882645 INFO: [APUAPC] D1_APC_2: 0x3fffff
9953 23:47:08.885992 INFO: [APUAPC] D1_APC_3: 0x0
9954 23:47:08.889706 INFO: [APUAPC] D2_APC_0: 0xffffffff
9955 23:47:08.892597 INFO: [APUAPC] D2_APC_1: 0xffffffff
9956 23:47:08.896125 INFO: [APUAPC] D2_APC_2: 0x3fffff
9957 23:47:08.899131 INFO: [APUAPC] D2_APC_3: 0x0
9958 23:47:08.902316 INFO: [APUAPC] D3_APC_0: 0xffffffff
9959 23:47:08.905676 INFO: [APUAPC] D3_APC_1: 0xffffffff
9960 23:47:08.908946 INFO: [APUAPC] D3_APC_2: 0x3fffff
9961 23:47:08.912464 INFO: [APUAPC] D3_APC_3: 0x0
9962 23:47:08.915474 INFO: [APUAPC] D4_APC_0: 0xffffffff
9963 23:47:08.919165 INFO: [APUAPC] D4_APC_1: 0xffffffff
9964 23:47:08.922179 INFO: [APUAPC] D4_APC_2: 0x3fffff
9965 23:47:08.925490 INFO: [APUAPC] D4_APC_3: 0x0
9966 23:47:08.929077 INFO: [APUAPC] D5_APC_0: 0xffffffff
9967 23:47:08.931888 INFO: [APUAPC] D5_APC_1: 0xffffffff
9968 23:47:08.935841 INFO: [APUAPC] D5_APC_2: 0x3fffff
9969 23:47:08.938983 INFO: [APUAPC] D5_APC_3: 0x0
9970 23:47:08.942403 INFO: [APUAPC] D6_APC_0: 0xffffffff
9971 23:47:08.945731 INFO: [APUAPC] D6_APC_1: 0xffffffff
9972 23:47:08.949100 INFO: [APUAPC] D6_APC_2: 0x3fffff
9973 23:47:08.952479 INFO: [APUAPC] D6_APC_3: 0x0
9974 23:47:08.955246 INFO: [APUAPC] D7_APC_0: 0xffffffff
9975 23:47:08.958932 INFO: [APUAPC] D7_APC_1: 0xffffffff
9976 23:47:08.962154 INFO: [APUAPC] D7_APC_2: 0x3fffff
9977 23:47:08.965546 INFO: [APUAPC] D7_APC_3: 0x0
9978 23:47:08.968875 INFO: [APUAPC] D8_APC_0: 0xffffffff
9979 23:47:08.972510 INFO: [APUAPC] D8_APC_1: 0xffffffff
9980 23:47:08.975952 INFO: [APUAPC] D8_APC_2: 0x3fffff
9981 23:47:08.978947 INFO: [APUAPC] D8_APC_3: 0x0
9982 23:47:08.982150 INFO: [APUAPC] D9_APC_0: 0xffffffff
9983 23:47:08.985636 INFO: [APUAPC] D9_APC_1: 0xffffffff
9984 23:47:08.988873 INFO: [APUAPC] D9_APC_2: 0x3fffff
9985 23:47:08.992255 INFO: [APUAPC] D9_APC_3: 0x0
9986 23:47:08.995721 INFO: [APUAPC] D10_APC_0: 0xffffffff
9987 23:47:08.998823 INFO: [APUAPC] D10_APC_1: 0xffffffff
9988 23:47:09.002557 INFO: [APUAPC] D10_APC_2: 0x3fffff
9989 23:47:09.005328 INFO: [APUAPC] D10_APC_3: 0x0
9990 23:47:09.009235 INFO: [APUAPC] D11_APC_0: 0xffffffff
9991 23:47:09.011923 INFO: [APUAPC] D11_APC_1: 0xffffffff
9992 23:47:09.015496 INFO: [APUAPC] D11_APC_2: 0x3fffff
9993 23:47:09.019176 INFO: [APUAPC] D11_APC_3: 0x0
9994 23:47:09.022182 INFO: [APUAPC] D12_APC_0: 0xffffffff
9995 23:47:09.025349 INFO: [APUAPC] D12_APC_1: 0xffffffff
9996 23:47:09.029115 INFO: [APUAPC] D12_APC_2: 0x3fffff
9997 23:47:09.032307 INFO: [APUAPC] D12_APC_3: 0x0
9998 23:47:09.035180 INFO: [APUAPC] D13_APC_0: 0xffffffff
9999 23:47:09.038505 INFO: [APUAPC] D13_APC_1: 0xffffffff
10000 23:47:09.042075 INFO: [APUAPC] D13_APC_2: 0x3fffff
10001 23:47:09.045015 INFO: [APUAPC] D13_APC_3: 0x0
10002 23:47:09.048387 INFO: [APUAPC] D14_APC_0: 0xffffffff
10003 23:47:09.051595 INFO: [APUAPC] D14_APC_1: 0xffffffff
10004 23:47:09.055181 INFO: [APUAPC] D14_APC_2: 0x3fffff
10005 23:47:09.058212 INFO: [APUAPC] D14_APC_3: 0x0
10006 23:47:09.061655 INFO: [APUAPC] D15_APC_0: 0xffffffff
10007 23:47:09.064985 INFO: [APUAPC] D15_APC_1: 0xffffffff
10008 23:47:09.068250 INFO: [APUAPC] D15_APC_2: 0x3fffff
10009 23:47:09.071944 INFO: [APUAPC] D15_APC_3: 0x0
10010 23:47:09.072148 INFO: [APUAPC] APC_CON: 0x4
10011 23:47:09.075794 INFO: [NOCDAPC] D0_APC_0: 0x0
10012 23:47:09.079134 INFO: [NOCDAPC] D0_APC_1: 0x0
10013 23:47:09.081579 INFO: [NOCDAPC] D1_APC_0: 0x0
10014 23:47:09.085025 INFO: [NOCDAPC] D1_APC_1: 0xfff
10015 23:47:09.088275 INFO: [NOCDAPC] D2_APC_0: 0x0
10016 23:47:09.091275 INFO: [NOCDAPC] D2_APC_1: 0xfff
10017 23:47:09.095052 INFO: [NOCDAPC] D3_APC_0: 0x0
10018 23:47:09.098330 INFO: [NOCDAPC] D3_APC_1: 0xfff
10019 23:47:09.101501 INFO: [NOCDAPC] D4_APC_0: 0x0
10020 23:47:09.101584 INFO: [NOCDAPC] D4_APC_1: 0xfff
10021 23:47:09.104919 INFO: [NOCDAPC] D5_APC_0: 0x0
10022 23:47:09.107955 INFO: [NOCDAPC] D5_APC_1: 0xfff
10023 23:47:09.111649 INFO: [NOCDAPC] D6_APC_0: 0x0
10024 23:47:09.114762 INFO: [NOCDAPC] D6_APC_1: 0xfff
10025 23:47:09.118049 INFO: [NOCDAPC] D7_APC_0: 0x0
10026 23:47:09.121834 INFO: [NOCDAPC] D7_APC_1: 0xfff
10027 23:47:09.124521 INFO: [NOCDAPC] D8_APC_0: 0x0
10028 23:47:09.128781 INFO: [NOCDAPC] D8_APC_1: 0xfff
10029 23:47:09.131879 INFO: [NOCDAPC] D9_APC_0: 0x0
10030 23:47:09.134669 INFO: [NOCDAPC] D9_APC_1: 0xfff
10031 23:47:09.134807 INFO: [NOCDAPC] D10_APC_0: 0x0
10032 23:47:09.138503 INFO: [NOCDAPC] D10_APC_1: 0xfff
10033 23:47:09.141511 INFO: [NOCDAPC] D11_APC_0: 0x0
10034 23:47:09.145184 INFO: [NOCDAPC] D11_APC_1: 0xfff
10035 23:47:09.147937 INFO: [NOCDAPC] D12_APC_0: 0x0
10036 23:47:09.151628 INFO: [NOCDAPC] D12_APC_1: 0xfff
10037 23:47:09.154555 INFO: [NOCDAPC] D13_APC_0: 0x0
10038 23:47:09.158438 INFO: [NOCDAPC] D13_APC_1: 0xfff
10039 23:47:09.161467 INFO: [NOCDAPC] D14_APC_0: 0x0
10040 23:47:09.164686 INFO: [NOCDAPC] D14_APC_1: 0xfff
10041 23:47:09.168067 INFO: [NOCDAPC] D15_APC_0: 0x0
10042 23:47:09.171332 INFO: [NOCDAPC] D15_APC_1: 0xfff
10043 23:47:09.174617 INFO: [NOCDAPC] APC_CON: 0x4
10044 23:47:09.177904 INFO: [APUAPC] set_apusys_apc done
10045 23:47:09.181564 INFO: [DEVAPC] devapc_init done
10046 23:47:09.184526 INFO: GICv3 without legacy support detected.
10047 23:47:09.187776 INFO: ARM GICv3 driver initialized in EL3
10048 23:47:09.191644 INFO: Maximum SPI INTID supported: 639
10049 23:47:09.194991 INFO: BL31: Initializing runtime services
10050 23:47:09.201175 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10051 23:47:09.204767 INFO: SPM: enable CPC mode
10052 23:47:09.208307 INFO: mcdi ready for mcusys-off-idle and system suspend
10053 23:47:09.214695 INFO: BL31: Preparing for EL3 exit to normal world
10054 23:47:09.218104 INFO: Entry point address = 0x80000000
10055 23:47:09.221217 INFO: SPSR = 0x8
10056 23:47:09.225831
10057 23:47:09.225912
10058 23:47:09.226001
10059 23:47:09.226789 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10060 23:47:09.226910 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10061 23:47:09.227042 Setting prompt string to ['asurada:']
10062 23:47:09.227128 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10063 23:47:09.228736 Starting depthcharge on Spherion...
10064 23:47:09.228815
10065 23:47:09.228880 Wipe memory regions:
10066 23:47:09.228940
10067 23:47:09.232070 [0x00000040000000, 0x00000054600000)
10068 23:47:09.354374
10069 23:47:09.354641 [0x00000054660000, 0x00000080000000)
10070 23:47:09.615322
10071 23:47:09.615565 [0x000000821a7280, 0x000000ffe64000)
10072 23:47:10.360414
10073 23:47:10.361012 [0x00000100000000, 0x00000240000000)
10074 23:47:12.250824
10075 23:47:12.254025 Initializing XHCI USB controller at 0x11200000.
10076 23:47:13.292041
10077 23:47:13.295625 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10078 23:47:13.296185
10079 23:47:13.296618
10080 23:47:13.297462 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10082 23:47:13.398829 asurada: tftpboot 192.168.201.1 14172931/tftp-deploy-gt1vhnjs/kernel/image.itb 14172931/tftp-deploy-gt1vhnjs/kernel/cmdline
10083 23:47:13.399482 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10084 23:47:13.399928 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10085 23:47:13.404767 tftpboot 192.168.201.1 14172931/tftp-deploy-gt1vhnjs/kernel/image.itp-deploy-gt1vhnjs/kernel/cmdline
10086 23:47:13.405343
10087 23:47:13.405717 Waiting for link
10088 23:47:13.564718
10089 23:47:13.565346 R8152: Initializing
10090 23:47:13.565739
10091 23:47:13.568025 Version 9 (ocp_data = 6010)
10092 23:47:13.568534
10093 23:47:13.571808 R8152: Done initializing
10094 23:47:13.572437
10095 23:47:13.572847 Adding net device
10096 23:47:15.450982
10097 23:47:15.451573 done.
10098 23:47:15.452091
10099 23:47:15.452613 MAC: 00:e0:4c:78:7a:aa
10100 23:47:15.452974
10101 23:47:15.453651 Sending DHCP discover... done.
10102 23:47:15.454031
10103 23:47:15.456747 Waiting for reply... done.
10104 23:47:15.457364
10105 23:47:15.460049 Sending DHCP request... done.
10106 23:47:15.460556
10107 23:47:15.463917 Waiting for reply... done.
10108 23:47:15.464426
10109 23:47:15.464805 My ip is 192.168.201.12
10110 23:47:15.465143
10111 23:47:15.467062 The DHCP server ip is 192.168.201.1
10112 23:47:15.467537
10113 23:47:15.473582 TFTP server IP predefined by user: 192.168.201.1
10114 23:47:15.474121
10115 23:47:15.480693 Bootfile predefined by user: 14172931/tftp-deploy-gt1vhnjs/kernel/image.itb
10116 23:47:15.481169
10117 23:47:15.483359 Sending tftp read request... done.
10118 23:47:15.483836
10119 23:47:15.489701 Waiting for the transfer...
10120 23:47:15.490233
10121 23:47:15.774784 00000000 ################################################################
10122 23:47:15.774920
10123 23:47:16.027254 00080000 ################################################################
10124 23:47:16.027423
10125 23:47:16.283877 00100000 ################################################################
10126 23:47:16.284021
10127 23:47:16.537875 00180000 ################################################################
10128 23:47:16.538010
10129 23:47:16.799945 00200000 ################################################################
10130 23:47:16.800094
10131 23:47:17.052040 00280000 ################################################################
10132 23:47:17.052181
10133 23:47:17.303211 00300000 ################################################################
10134 23:47:17.303351
10135 23:47:17.579130 00380000 ################################################################
10136 23:47:17.579263
10137 23:47:17.863457 00400000 ################################################################
10138 23:47:17.863621
10139 23:47:18.121115 00480000 ################################################################
10140 23:47:18.121250
10141 23:47:18.378910 00500000 ################################################################
10142 23:47:18.379044
10143 23:47:18.629151 00580000 ################################################################
10144 23:47:18.629286
10145 23:47:18.881701 00600000 ################################################################
10146 23:47:18.881828
10147 23:47:19.133178 00680000 ################################################################
10148 23:47:19.133307
10149 23:47:19.386899 00700000 ################################################################
10150 23:47:19.387031
10151 23:47:19.639278 00780000 ################################################################
10152 23:47:19.639413
10153 23:47:19.893942 00800000 ################################################################
10154 23:47:19.894077
10155 23:47:20.142635 00880000 ################################################################
10156 23:47:20.142776
10157 23:47:20.392037 00900000 ################################################################
10158 23:47:20.392170
10159 23:47:20.651060 00980000 ################################################################
10160 23:47:20.651196
10161 23:47:20.900423 00a00000 ################################################################
10162 23:47:20.900552
10163 23:47:21.151230 00a80000 ################################################################
10164 23:47:21.151365
10165 23:47:21.400208 00b00000 ################################################################
10166 23:47:21.400402
10167 23:47:21.652948 00b80000 ################################################################
10168 23:47:21.653078
10169 23:47:21.903121 00c00000 ################################################################
10170 23:47:21.903253
10171 23:47:22.182081 00c80000 ################################################################
10172 23:47:22.182216
10173 23:47:22.459695 00d00000 ################################################################
10174 23:47:22.459826
10175 23:47:22.711414 00d80000 ################################################################
10176 23:47:22.711545
10177 23:47:22.966224 00e00000 ################################################################
10178 23:47:22.966359
10179 23:47:23.223118 00e80000 ################################################################
10180 23:47:23.223256
10181 23:47:23.468238 00f00000 ################################################################
10182 23:47:23.468421
10183 23:47:23.716569 00f80000 ################################################################
10184 23:47:23.716703
10185 23:47:23.968929 01000000 ################################################################
10186 23:47:23.969065
10187 23:47:24.217843 01080000 ################################################################
10188 23:47:24.218074
10189 23:47:24.470741 01100000 ################################################################
10190 23:47:24.470895
10191 23:47:24.728549 01180000 ################################################################
10192 23:47:24.728702
10193 23:47:24.975406 01200000 ################################################################
10194 23:47:24.975564
10195 23:47:25.226276 01280000 ################################################################
10196 23:47:25.226412
10197 23:47:25.506158 01300000 ################################################################
10198 23:47:25.506300
10199 23:47:25.770443 01380000 ################################################################
10200 23:47:25.770577
10201 23:47:26.021904 01400000 ################################################################
10202 23:47:26.022044
10203 23:47:26.273971 01480000 ################################################################
10204 23:47:26.274106
10205 23:47:26.543796 01500000 ################################################################
10206 23:47:26.543939
10207 23:47:26.813139 01580000 ################################################################
10208 23:47:26.813270
10209 23:47:27.073807 01600000 ################################################################
10210 23:47:27.073941
10211 23:47:27.336162 01680000 ################################################################
10212 23:47:27.336315
10213 23:47:27.592684 01700000 ################################################################
10214 23:47:27.592821
10215 23:47:27.861679 01780000 ################################################################
10216 23:47:27.861817
10217 23:47:28.126141 01800000 ################################################################
10218 23:47:28.126288
10219 23:47:28.377290 01880000 ################################################################
10220 23:47:28.377431
10221 23:47:28.630287 01900000 ################################################################
10222 23:47:28.630424
10223 23:47:28.912227 01980000 ################################################################
10224 23:47:28.912379
10225 23:47:29.189296 01a00000 ################################################################
10226 23:47:29.189428
10227 23:47:29.448322 01a80000 ################################################################
10228 23:47:29.448467
10229 23:47:29.699836 01b00000 ################################################################
10230 23:47:29.700006
10231 23:47:29.953558 01b80000 ################################################################
10232 23:47:29.953689
10233 23:47:30.211080 01c00000 ################################################################
10234 23:47:30.211207
10235 23:47:30.469292 01c80000 ################################################################
10236 23:47:30.469425
10237 23:47:30.759120 01d00000 ################################################################
10238 23:47:30.759292
10239 23:47:31.016060 01d80000 ################################################################
10240 23:47:31.016199
10241 23:47:31.202227 01e00000 ################################################ done.
10242 23:47:31.202399
10243 23:47:31.205888 The bootfile was 31842494 bytes long.
10244 23:47:31.205975
10245 23:47:31.208941 Sending tftp read request... done.
10246 23:47:31.209017
10247 23:47:31.209097 Waiting for the transfer...
10248 23:47:31.209158
10249 23:47:31.212493 00000000 # done.
10250 23:47:31.212587
10251 23:47:31.219105 Command line loaded dynamically from TFTP file: 14172931/tftp-deploy-gt1vhnjs/kernel/cmdline
10252 23:47:31.219190
10253 23:47:31.242200 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172931/extract-nfsrootfs-ivx2x1zz,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10254 23:47:31.242378
10255 23:47:31.242489 Loading FIT.
10256 23:47:31.242592
10257 23:47:31.245952 Image ramdisk-1 has 18731769 bytes.
10258 23:47:31.246089
10259 23:47:31.248981 Image fdt-1 has 47258 bytes.
10260 23:47:31.249084
10261 23:47:31.252252 Image kernel-1 has 13061430 bytes.
10262 23:47:31.252902
10263 23:47:31.262100 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10264 23:47:31.262616
10265 23:47:31.279086 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10266 23:47:31.279655
10267 23:47:31.285528 Choosing best match conf-1 for compat google,spherion-rev2.
10268 23:47:31.288743
10269 23:47:31.293514 Connected to device vid:did:rid of 1ae0:0028:00
10270 23:47:31.301372
10271 23:47:31.305204 tpm_get_response: command 0x17b, return code 0x0
10272 23:47:31.305664
10273 23:47:31.308192 ec_init: CrosEC protocol v3 supported (256, 248)
10274 23:47:31.313400
10275 23:47:31.316932 tpm_cleanup: add release locality here.
10276 23:47:31.317481
10277 23:47:31.317837 Shutting down all USB controllers.
10278 23:47:31.320236
10279 23:47:31.320872 Removing current net device
10280 23:47:31.321361
10281 23:47:31.326889 Exiting depthcharge with code 4 at timestamp: 51344325
10282 23:47:31.327191
10283 23:47:31.329937 LZMA decompressing kernel-1 to 0x821a6718
10284 23:47:31.330283
10285 23:47:31.332895 LZMA decompressing kernel-1 to 0x40000000
10286 23:47:32.943186
10287 23:47:32.943690 jumping to kernel
10288 23:47:32.945395 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10289 23:47:32.945964 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10290 23:47:32.946355 Setting prompt string to ['Linux version [0-9]']
10291 23:47:32.946698 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10292 23:47:32.947034 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10293 23:47:33.024970
10294 23:47:33.028386 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10295 23:47:33.031454 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10296 23:47:33.031679 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10297 23:47:33.031864 Setting prompt string to []
10298 23:47:33.032119 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10299 23:47:33.032383 Using line separator: #'\n'#
10300 23:47:33.032550 No login prompt set.
10301 23:47:33.032735 Parsing kernel messages
10302 23:47:33.032900 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10303 23:47:33.033175 [login-action] Waiting for messages, (timeout 00:04:01)
10304 23:47:33.033409 Waiting using forced prompt support (timeout 00:02:01)
10305 23:47:33.051263 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j217067-arm64-gcc-10-defconfig-arm64-chromebook-s48tj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024
10306 23:47:33.054116 [ 0.000000] random: crng init done
10307 23:47:33.061143 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10308 23:47:33.064436 [ 0.000000] efi: UEFI not found.
10309 23:47:33.070907 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10310 23:47:33.077694 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10311 23:47:33.087666 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10312 23:47:33.097429 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10313 23:47:33.104427 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10314 23:47:33.110642 [ 0.000000] printk: bootconsole [mtk8250] enabled
10315 23:47:33.117453 [ 0.000000] NUMA: No NUMA configuration found
10316 23:47:33.124277 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10317 23:47:33.127406 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10318 23:47:33.130498 [ 0.000000] Zone ranges:
10319 23:47:33.137253 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10320 23:47:33.140846 [ 0.000000] DMA32 empty
10321 23:47:33.147786 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10322 23:47:33.150514 [ 0.000000] Movable zone start for each node
10323 23:47:33.153614 [ 0.000000] Early memory node ranges
10324 23:47:33.160787 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10325 23:47:33.167316 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10326 23:47:33.174001 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10327 23:47:33.177254 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10328 23:47:33.183971 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10329 23:47:33.190218 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10330 23:47:33.249621 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10331 23:47:33.255999 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10332 23:47:33.262335 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10333 23:47:33.266109 [ 0.000000] psci: probing for conduit method from DT.
10334 23:47:33.272460 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10335 23:47:33.276108 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10336 23:47:33.282465 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10337 23:47:33.286022 [ 0.000000] psci: SMC Calling Convention v1.2
10338 23:47:33.292677 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10339 23:47:33.295860 [ 0.000000] Detected VIPT I-cache on CPU0
10340 23:47:33.302093 [ 0.000000] CPU features: detected: GIC system register CPU interface
10341 23:47:33.308809 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10342 23:47:33.315765 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10343 23:47:33.322010 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10344 23:47:33.329113 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10345 23:47:33.335681 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10346 23:47:33.342252 [ 0.000000] alternatives: applying boot alternatives
10347 23:47:33.349063 [ 0.000000] Fallback order for Node 0: 0
10348 23:47:33.355644 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10349 23:47:33.358627 [ 0.000000] Policy zone: Normal
10350 23:47:33.382293 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172931/extract-nfsrootfs-ivx2x1zz,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10351 23:47:33.391818 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10352 23:47:33.402660 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10353 23:47:33.412460 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10354 23:47:33.419131 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10355 23:47:33.422894 <6>[ 0.000000] software IO TLB: area num 8.
10356 23:47:33.478829 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10357 23:47:33.628546 <6>[ 0.000000] Memory: 7945896K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406872K reserved, 32768K cma-reserved)
10358 23:47:33.635325 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10359 23:47:33.641752 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10360 23:47:33.645682 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10361 23:47:33.652484 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10362 23:47:33.658962 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10363 23:47:33.662012 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10364 23:47:33.672163 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10365 23:47:33.678572 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10366 23:47:33.685402 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10367 23:47:33.691993 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10368 23:47:33.695485 <6>[ 0.000000] GICv3: 608 SPIs implemented
10369 23:47:33.698920 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10370 23:47:33.705022 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10371 23:47:33.708501 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10372 23:47:33.715278 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10373 23:47:33.728535 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10374 23:47:33.738576 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10375 23:47:33.747717 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10376 23:47:33.755148 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10377 23:47:33.768623 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10378 23:47:33.775672 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10379 23:47:33.781966 <6>[ 0.009179] Console: colour dummy device 80x25
10380 23:47:33.792045 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10381 23:47:33.798207 <6>[ 0.024411] pid_max: default: 32768 minimum: 301
10382 23:47:33.801915 <6>[ 0.029282] LSM: Security Framework initializing
10383 23:47:33.808532 <6>[ 0.034219] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10384 23:47:33.818404 <6>[ 0.042081] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10385 23:47:33.824883 <6>[ 0.051502] cblist_init_generic: Setting adjustable number of callback queues.
10386 23:47:33.831418 <6>[ 0.058944] cblist_init_generic: Setting shift to 3 and lim to 1.
10387 23:47:33.841744 <6>[ 0.065282] cblist_init_generic: Setting adjustable number of callback queues.
10388 23:47:33.848364 <6>[ 0.072709] cblist_init_generic: Setting shift to 3 and lim to 1.
10389 23:47:33.851336 <6>[ 0.079108] rcu: Hierarchical SRCU implementation.
10390 23:47:33.858288 <6>[ 0.084123] rcu: Max phase no-delay instances is 1000.
10391 23:47:33.864961 <6>[ 0.091192] EFI services will not be available.
10392 23:47:33.868192 <6>[ 0.096144] smp: Bringing up secondary CPUs ...
10393 23:47:33.876274 <6>[ 0.101223] Detected VIPT I-cache on CPU1
10394 23:47:33.882926 <6>[ 0.101295] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10395 23:47:33.889945 <6>[ 0.101328] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10396 23:47:33.893220 <6>[ 0.101665] Detected VIPT I-cache on CPU2
10397 23:47:33.899983 <6>[ 0.101719] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10398 23:47:33.907061 <6>[ 0.101736] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10399 23:47:33.913388 <6>[ 0.101997] Detected VIPT I-cache on CPU3
10400 23:47:33.920132 <6>[ 0.102047] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10401 23:47:33.926345 <6>[ 0.102061] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10402 23:47:33.929790 <6>[ 0.102368] CPU features: detected: Spectre-v4
10403 23:47:33.935866 <6>[ 0.102374] CPU features: detected: Spectre-BHB
10404 23:47:33.939175 <6>[ 0.102379] Detected PIPT I-cache on CPU4
10405 23:47:33.945715 <6>[ 0.102438] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10406 23:47:33.952411 <6>[ 0.102453] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10407 23:47:33.958752 <6>[ 0.102730] Detected PIPT I-cache on CPU5
10408 23:47:33.965682 <6>[ 0.102785] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10409 23:47:33.972798 <6>[ 0.102801] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10410 23:47:33.975708 <6>[ 0.103076] Detected PIPT I-cache on CPU6
10411 23:47:33.982293 <6>[ 0.103141] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10412 23:47:33.988964 <6>[ 0.103157] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10413 23:47:33.995874 <6>[ 0.103451] Detected PIPT I-cache on CPU7
10414 23:47:34.002270 <6>[ 0.103517] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10415 23:47:34.009274 <6>[ 0.103532] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10416 23:47:34.012267 <6>[ 0.103579] smp: Brought up 1 node, 8 CPUs
10417 23:47:34.019055 <6>[ 0.245124] SMP: Total of 8 processors activated.
10418 23:47:34.022033 <6>[ 0.250075] CPU features: detected: 32-bit EL0 Support
10419 23:47:34.032109 <6>[ 0.255460] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10420 23:47:34.039046 <6>[ 0.264315] CPU features: detected: Common not Private translations
10421 23:47:34.045616 <6>[ 0.270831] CPU features: detected: CRC32 instructions
10422 23:47:34.048865 <6>[ 0.276182] CPU features: detected: RCpc load-acquire (LDAPR)
10423 23:47:34.055857 <6>[ 0.282180] CPU features: detected: LSE atomic instructions
10424 23:47:34.062643 <6>[ 0.287961] CPU features: detected: Privileged Access Never
10425 23:47:34.068874 <6>[ 0.293741] CPU features: detected: RAS Extension Support
10426 23:47:34.075564 <6>[ 0.299384] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10427 23:47:34.078898 <6>[ 0.306605] CPU: All CPU(s) started at EL2
10428 23:47:34.085402 <6>[ 0.310922] alternatives: applying system-wide alternatives
10429 23:47:34.094383 <6>[ 0.321757] devtmpfs: initialized
10430 23:47:34.106891 <6>[ 0.330713] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10431 23:47:34.117041 <6>[ 0.340672] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10432 23:47:34.123550 <6>[ 0.348689] pinctrl core: initialized pinctrl subsystem
10433 23:47:34.127340 <6>[ 0.355362] DMI not present or invalid.
10434 23:47:34.133479 <6>[ 0.359778] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10435 23:47:34.144095 <6>[ 0.366640] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10436 23:47:34.150785 <6>[ 0.374234] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10437 23:47:34.160424 <6>[ 0.382453] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10438 23:47:34.163318 <6>[ 0.390698] audit: initializing netlink subsys (disabled)
10439 23:47:34.173666 <5>[ 0.396386] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10440 23:47:34.179806 <6>[ 0.397110] thermal_sys: Registered thermal governor 'step_wise'
10441 23:47:34.186693 <6>[ 0.404351] thermal_sys: Registered thermal governor 'power_allocator'
10442 23:47:34.190139 <6>[ 0.410607] cpuidle: using governor menu
10443 23:47:34.193389 <6>[ 0.421567] NET: Registered PF_QIPCRTR protocol family
10444 23:47:34.203429 <6>[ 0.427051] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10445 23:47:34.206917 <6>[ 0.434153] ASID allocator initialised with 32768 entries
10446 23:47:34.213598 <6>[ 0.440740] Serial: AMBA PL011 UART driver
10447 23:47:34.222667 <4>[ 0.449615] Trying to register duplicate clock ID: 134
10448 23:47:34.282060 <6>[ 0.512638] KASLR enabled
10449 23:47:34.296278 <6>[ 0.520400] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10450 23:47:34.302878 <6>[ 0.527416] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10451 23:47:34.309659 <6>[ 0.533902] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10452 23:47:34.316391 <6>[ 0.540907] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10453 23:47:34.323190 <6>[ 0.547395] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10454 23:47:34.329251 <6>[ 0.554402] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10455 23:47:34.336198 <6>[ 0.560891] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10456 23:47:34.342672 <6>[ 0.567894] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10457 23:47:34.346306 <6>[ 0.575417] ACPI: Interpreter disabled.
10458 23:47:34.354746 <6>[ 0.581862] iommu: Default domain type: Translated
10459 23:47:34.361405 <6>[ 0.586972] iommu: DMA domain TLB invalidation policy: strict mode
10460 23:47:34.364822 <5>[ 0.593632] SCSI subsystem initialized
10461 23:47:34.371365 <6>[ 0.597798] usbcore: registered new interface driver usbfs
10462 23:47:34.378031 <6>[ 0.603530] usbcore: registered new interface driver hub
10463 23:47:34.381509 <6>[ 0.609080] usbcore: registered new device driver usb
10464 23:47:34.388197 <6>[ 0.615182] pps_core: LinuxPPS API ver. 1 registered
10465 23:47:34.398190 <6>[ 0.620376] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10466 23:47:34.400970 <6>[ 0.629726] PTP clock support registered
10467 23:47:34.404440 <6>[ 0.633969] EDAC MC: Ver: 3.0.0
10468 23:47:34.411926 <6>[ 0.639117] FPGA manager framework
10469 23:47:34.418952 <6>[ 0.642808] Advanced Linux Sound Architecture Driver Initialized.
10470 23:47:34.421878 <6>[ 0.649596] vgaarb: loaded
10471 23:47:34.428713 <6>[ 0.652753] clocksource: Switched to clocksource arch_sys_counter
10472 23:47:34.431616 <5>[ 0.659194] VFS: Disk quotas dquot_6.6.0
10473 23:47:34.438398 <6>[ 0.663382] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10474 23:47:34.441463 <6>[ 0.670571] pnp: PnP ACPI: disabled
10475 23:47:34.450070 <6>[ 0.677269] NET: Registered PF_INET protocol family
10476 23:47:34.459997 <6>[ 0.682863] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10477 23:47:34.471432 <6>[ 0.695198] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10478 23:47:34.481710 <6>[ 0.704013] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10479 23:47:34.488135 <6>[ 0.711978] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10480 23:47:34.494584 <6>[ 0.720682] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10481 23:47:34.506605 <6>[ 0.730437] TCP: Hash tables configured (established 65536 bind 65536)
10482 23:47:34.513375 <6>[ 0.737300] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10483 23:47:34.519470 <6>[ 0.744499] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10484 23:47:34.526594 <6>[ 0.752201] NET: Registered PF_UNIX/PF_LOCAL protocol family
10485 23:47:34.533192 <6>[ 0.758357] RPC: Registered named UNIX socket transport module.
10486 23:47:34.536108 <6>[ 0.764511] RPC: Registered udp transport module.
10487 23:47:34.543094 <6>[ 0.769446] RPC: Registered tcp transport module.
10488 23:47:34.549670 <6>[ 0.774378] RPC: Registered tcp NFSv4.1 backchannel transport module.
10489 23:47:34.552654 <6>[ 0.781042] PCI: CLS 0 bytes, default 64
10490 23:47:34.556506 <6>[ 0.785348] Unpacking initramfs...
10491 23:47:34.566057 <6>[ 0.789414] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10492 23:47:34.572980 <6>[ 0.798091] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10493 23:47:34.579465 <6>[ 0.806895] kvm [1]: IPA Size Limit: 40 bits
10494 23:47:34.582683 <6>[ 0.811422] kvm [1]: GICv3: no GICV resource entry
10495 23:47:34.589435 <6>[ 0.816444] kvm [1]: disabling GICv2 emulation
10496 23:47:34.596061 <6>[ 0.821134] kvm [1]: GIC system register CPU interface enabled
10497 23:47:34.599821 <6>[ 0.827290] kvm [1]: vgic interrupt IRQ18
10498 23:47:34.606185 <6>[ 0.831644] kvm [1]: VHE mode initialized successfully
10499 23:47:34.609402 <5>[ 0.838088] Initialise system trusted keyrings
10500 23:47:34.616025 <6>[ 0.842877] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10501 23:47:34.625972 <6>[ 0.852977] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10502 23:47:34.632099 <5>[ 0.859421] NFS: Registering the id_resolver key type
10503 23:47:34.635392 <5>[ 0.864738] Key type id_resolver registered
10504 23:47:34.642323 <5>[ 0.869158] Key type id_legacy registered
10505 23:47:34.648834 <6>[ 0.873433] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10506 23:47:34.655564 <6>[ 0.880354] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10507 23:47:34.662048 <6>[ 0.888110] 9p: Installing v9fs 9p2000 file system support
10508 23:47:34.698601 <5>[ 0.925657] Key type asymmetric registered
10509 23:47:34.702022 <5>[ 0.929984] Asymmetric key parser 'x509' registered
10510 23:47:34.712146 <6>[ 0.935130] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10511 23:47:34.715135 <6>[ 0.942741] io scheduler mq-deadline registered
10512 23:47:34.718823 <6>[ 0.947502] io scheduler kyber registered
10513 23:47:34.737524 <6>[ 0.964593] EINJ: ACPI disabled.
10514 23:47:34.770483 <4>[ 0.990932] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10515 23:47:34.780020 <4>[ 1.001564] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10516 23:47:34.795132 <6>[ 1.022639] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10517 23:47:34.803284 <6>[ 1.030646] printk: console [ttyS0] disabled
10518 23:47:34.831322 <6>[ 1.055278] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10519 23:47:34.838078 <6>[ 1.064773] printk: console [ttyS0] enabled
10520 23:47:34.841242 <6>[ 1.064773] printk: console [ttyS0] enabled
10521 23:47:34.847660 <6>[ 1.073666] printk: bootconsole [mtk8250] disabled
10522 23:47:34.851295 <6>[ 1.073666] printk: bootconsole [mtk8250] disabled
10523 23:47:34.857498 <6>[ 1.084977] SuperH (H)SCI(F) driver initialized
10524 23:47:34.861331 <6>[ 1.090262] msm_serial: driver initialized
10525 23:47:34.875142 <6>[ 1.099249] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10526 23:47:34.885336 <6>[ 1.107800] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10527 23:47:34.891819 <6>[ 1.116342] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10528 23:47:34.901766 <6>[ 1.124973] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10529 23:47:34.908636 <6>[ 1.133679] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10530 23:47:34.918388 <6>[ 1.142401] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10531 23:47:34.928181 <6>[ 1.150944] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10532 23:47:34.934739 <6>[ 1.159751] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10533 23:47:34.945063 <6>[ 1.168299] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10534 23:47:34.956756 <6>[ 1.184232] loop: module loaded
10535 23:47:34.963093 <6>[ 1.190241] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10536 23:47:34.985981 <4>[ 1.213744] mtk-pmic-keys: Failed to locate of_node [id: -1]
10537 23:47:34.992982 <6>[ 1.220579] megasas: 07.719.03.00-rc1
10538 23:47:35.002602 <6>[ 1.230179] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10539 23:47:35.013248 <6>[ 1.240132] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10540 23:47:35.029638 <6>[ 1.256895] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10541 23:47:35.086256 <6>[ 1.306882] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10542 23:47:35.390010 <6>[ 1.617358] Freeing initrd memory: 18288K
10543 23:47:35.401515 <6>[ 1.629080] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10544 23:47:35.412735 <6>[ 1.640166] tun: Universal TUN/TAP device driver, 1.6
10545 23:47:35.415751 <6>[ 1.646248] thunder_xcv, ver 1.0
10546 23:47:35.419390 <6>[ 1.649758] thunder_bgx, ver 1.0
10547 23:47:35.422617 <6>[ 1.653252] nicpf, ver 1.0
10548 23:47:35.433300 <6>[ 1.657298] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10549 23:47:35.436662 <6>[ 1.664774] hns3: Copyright (c) 2017 Huawei Corporation.
10550 23:47:35.442878 <6>[ 1.670367] hclge is initializing
10551 23:47:35.446495 <6>[ 1.673950] e1000: Intel(R) PRO/1000 Network Driver
10552 23:47:35.453101 <6>[ 1.679079] e1000: Copyright (c) 1999-2006 Intel Corporation.
10553 23:47:35.456218 <6>[ 1.685091] e1000e: Intel(R) PRO/1000 Network Driver
10554 23:47:35.462772 <6>[ 1.690306] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10555 23:47:35.469670 <6>[ 1.696491] igb: Intel(R) Gigabit Ethernet Network Driver
10556 23:47:35.476782 <6>[ 1.702141] igb: Copyright (c) 2007-2014 Intel Corporation.
10557 23:47:35.483699 <6>[ 1.707976] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10558 23:47:35.489900 <6>[ 1.714494] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10559 23:47:35.493426 <6>[ 1.720971] sky2: driver version 1.30
10560 23:47:35.499843 <6>[ 1.725930] usbcore: registered new device driver r8152-cfgselector
10561 23:47:35.506740 <6>[ 1.732465] usbcore: registered new interface driver r8152
10562 23:47:35.509784 <6>[ 1.738286] VFIO - User Level meta-driver version: 0.3
10563 23:47:35.519521 <6>[ 1.746500] usbcore: registered new interface driver usb-storage
10564 23:47:35.525916 <6>[ 1.752944] usbcore: registered new device driver onboard-usb-hub
10565 23:47:35.534499 <6>[ 1.762135] mt6397-rtc mt6359-rtc: registered as rtc0
10566 23:47:35.544912 <6>[ 1.767604] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T23:42:54 UTC (1717544574)
10567 23:47:35.547810 <6>[ 1.777205] i2c_dev: i2c /dev entries driver
10568 23:47:35.564688 <6>[ 1.788952] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10569 23:47:35.571840 <4>[ 1.797676] cpu cpu0: supply cpu not found, using dummy regulator
10570 23:47:35.578525 <4>[ 1.804102] cpu cpu1: supply cpu not found, using dummy regulator
10571 23:47:35.584619 <4>[ 1.810512] cpu cpu2: supply cpu not found, using dummy regulator
10572 23:47:35.591336 <4>[ 1.816927] cpu cpu3: supply cpu not found, using dummy regulator
10573 23:47:35.598154 <4>[ 1.823325] cpu cpu4: supply cpu not found, using dummy regulator
10574 23:47:35.605392 <4>[ 1.829723] cpu cpu5: supply cpu not found, using dummy regulator
10575 23:47:35.608389 <4>[ 1.836123] cpu cpu6: supply cpu not found, using dummy regulator
10576 23:47:35.615012 <4>[ 1.842519] cpu cpu7: supply cpu not found, using dummy regulator
10577 23:47:35.636681 <6>[ 1.864177] cpu cpu0: EM: created perf domain
10578 23:47:35.639897 <6>[ 1.869114] cpu cpu4: EM: created perf domain
10579 23:47:35.646964 <6>[ 1.874680] sdhci: Secure Digital Host Controller Interface driver
10580 23:47:35.654533 <6>[ 1.881116] sdhci: Copyright(c) Pierre Ossman
10581 23:47:35.660421 <6>[ 1.886073] Synopsys Designware Multimedia Card Interface Driver
10582 23:47:35.667148 <6>[ 1.892716] sdhci-pltfm: SDHCI platform and OF driver helper
10583 23:47:35.670388 <6>[ 1.892767] mmc0: CQHCI version 5.10
10584 23:47:35.676898 <6>[ 1.903412] ledtrig-cpu: registered to indicate activity on CPUs
10585 23:47:35.683838 <6>[ 1.910509] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10586 23:47:35.690900 <6>[ 1.917568] usbcore: registered new interface driver usbhid
10587 23:47:35.694183 <6>[ 1.923390] usbhid: USB HID core driver
10588 23:47:35.700378 <6>[ 1.927581] spi_master spi0: will run message pump with realtime priority
10589 23:47:35.742697 <6>[ 1.963527] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10590 23:47:35.760942 <6>[ 1.978635] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10591 23:47:35.764637 <6>[ 1.989680] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10592 23:47:35.772172 <6>[ 1.999922] cros-ec-spi spi0.0: Chrome EC device registered
10593 23:47:35.779146 <6>[ 2.005954] mmc0: Command Queue Engine enabled
10594 23:47:35.785614 <6>[ 2.010704] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10595 23:47:35.792196 <6>[ 2.018445] mmcblk0: mmc0:0001 DA4128 116 GiB
10596 23:47:35.799830 <6>[ 2.027307] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10597 23:47:35.807202 <6>[ 2.034808] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10598 23:47:35.817366 <6>[ 2.039315] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10599 23:47:35.820992 <6>[ 2.040706] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10600 23:47:35.827090 <6>[ 2.050676] NET: Registered PF_PACKET protocol family
10601 23:47:35.833742 <6>[ 2.055258] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10602 23:47:35.837529 <6>[ 2.060008] 9pnet: Installing 9P2000 support
10603 23:47:35.843662 <5>[ 2.070975] Key type dns_resolver registered
10604 23:47:35.847325 <6>[ 2.076032] registered taskstats version 1
10605 23:47:35.853682 <5>[ 2.080400] Loading compiled-in X.509 certificates
10606 23:47:35.882696 <4>[ 2.103629] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10607 23:47:35.892594 <4>[ 2.114347] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10608 23:47:35.907153 <6>[ 2.134625] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10609 23:47:35.914090 <6>[ 2.141550] xhci-mtk 11200000.usb: xHCI Host Controller
10610 23:47:35.920211 <6>[ 2.147053] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10611 23:47:35.930950 <6>[ 2.154906] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10612 23:47:35.937080 <6>[ 2.164345] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10613 23:47:35.943769 <6>[ 2.170434] xhci-mtk 11200000.usb: xHCI Host Controller
10614 23:47:35.950646 <6>[ 2.175913] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10615 23:47:35.957539 <6>[ 2.183569] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10616 23:47:35.963464 <6>[ 2.191224] hub 1-0:1.0: USB hub found
10617 23:47:35.966876 <6>[ 2.195253] hub 1-0:1.0: 1 port detected
10618 23:47:35.973788 <6>[ 2.199541] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10619 23:47:35.980836 <6>[ 2.208082] hub 2-0:1.0: USB hub found
10620 23:47:35.983920 <6>[ 2.212101] hub 2-0:1.0: 1 port detected
10621 23:47:35.991348 <6>[ 2.219166] mtk-msdc 11f70000.mmc: Got CD GPIO
10622 23:47:36.005626 <6>[ 2.229760] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10623 23:47:36.012393 <6>[ 2.237789] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10624 23:47:36.022144 <4>[ 2.245711] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10625 23:47:36.032206 <6>[ 2.255274] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10626 23:47:36.038971 <6>[ 2.263358] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10627 23:47:36.045692 <6>[ 2.271374] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10628 23:47:36.055899 <6>[ 2.279307] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10629 23:47:36.062248 <6>[ 2.287129] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10630 23:47:36.072096 <6>[ 2.294947] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10631 23:47:36.081894 <6>[ 2.305418] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10632 23:47:36.088956 <6>[ 2.313795] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10633 23:47:36.098385 <6>[ 2.322141] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10634 23:47:36.105373 <6>[ 2.330480] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10635 23:47:36.115356 <6>[ 2.338818] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10636 23:47:36.121546 <6>[ 2.347157] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10637 23:47:36.131807 <6>[ 2.355495] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10638 23:47:36.138497 <6>[ 2.363833] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10639 23:47:36.148285 <6>[ 2.372170] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10640 23:47:36.155274 <6>[ 2.380507] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10641 23:47:36.165062 <6>[ 2.388845] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10642 23:47:36.171523 <6>[ 2.397182] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10643 23:47:36.182363 <6>[ 2.405520] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10644 23:47:36.188204 <6>[ 2.413857] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10645 23:47:36.198418 <6>[ 2.422196] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10646 23:47:36.205138 <6>[ 2.430928] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10647 23:47:36.211510 <6>[ 2.438075] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10648 23:47:36.218526 <6>[ 2.444843] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10649 23:47:36.224865 <6>[ 2.451611] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10650 23:47:36.231308 <6>[ 2.458533] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10651 23:47:36.241608 <6>[ 2.465386] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10652 23:47:36.251902 <6>[ 2.474521] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10653 23:47:36.261620 <6>[ 2.483640] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10654 23:47:36.271303 <6>[ 2.492934] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10655 23:47:36.278045 <6>[ 2.502400] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10656 23:47:36.287730 <6>[ 2.511867] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10657 23:47:36.297815 <6>[ 2.520987] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10658 23:47:36.307817 <6>[ 2.530456] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10659 23:47:36.317699 <6>[ 2.539575] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10660 23:47:36.327817 <6>[ 2.548869] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10661 23:47:36.338102 <6>[ 2.559030] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10662 23:47:36.347918 <6>[ 2.570492] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10663 23:47:36.354035 <6>[ 2.580189] Trying to probe devices needed for running init ...
10664 23:47:36.393065 <6>[ 2.617038] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10665 23:47:36.547804 <6>[ 2.774903] hub 1-1:1.0: USB hub found
10666 23:47:36.550895 <6>[ 2.779411] hub 1-1:1.0: 4 ports detected
10667 23:47:36.560986 <6>[ 2.788124] hub 1-1:1.0: USB hub found
10668 23:47:36.564213 <6>[ 2.792496] hub 1-1:1.0: 4 ports detected
10669 23:47:36.673414 <6>[ 2.897363] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10670 23:47:36.699979 <6>[ 2.926795] hub 2-1:1.0: USB hub found
10671 23:47:36.702773 <6>[ 2.931293] hub 2-1:1.0: 3 ports detected
10672 23:47:36.712251 <6>[ 2.939431] hub 2-1:1.0: USB hub found
10673 23:47:36.715514 <6>[ 2.943902] hub 2-1:1.0: 3 ports detected
10674 23:47:36.888741 <6>[ 3.113052] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10675 23:47:37.021190 <6>[ 3.248430] hub 1-1.4:1.0: USB hub found
10676 23:47:37.024281 <6>[ 3.253023] hub 1-1.4:1.0: 2 ports detected
10677 23:47:37.032833 <6>[ 3.260539] hub 1-1.4:1.0: USB hub found
10678 23:47:37.036704 <6>[ 3.265191] hub 1-1.4:1.0: 2 ports detected
10679 23:47:37.101206 <6>[ 3.325225] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10680 23:47:37.209840 <6>[ 3.433716] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10681 23:47:37.245501 <4>[ 3.469507] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10682 23:47:37.255393 <4>[ 3.478600] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10683 23:47:37.299205 <6>[ 3.526676] r8152 2-1.3:1.0 eth0: v1.12.13
10684 23:47:37.333042 <6>[ 3.557071] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10685 23:47:37.524652 <6>[ 3.749071] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10686 23:47:38.944459 <6>[ 5.171938] r8152 2-1.3:1.0 eth0: carrier on
10687 23:47:41.013146 <5>[ 5.200878] Sending DHCP requests .., OK
10688 23:47:41.020215 <6>[ 7.245270] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12
10689 23:47:41.023212 <6>[ 7.253558] IP-Config: Complete:
10690 23:47:41.036528 <6>[ 7.257044] device=eth0, hwaddr=00:e0:4c:78:7a:aa, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1
10691 23:47:41.042959 <6>[ 7.267749] host=mt8192-asurada-spherion-r0-cbg-0, domain=lava-rack, nis-domain=(none)
10692 23:47:41.049728 <6>[ 7.276359] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10693 23:47:41.056122 <6>[ 7.276367] nameserver0=192.168.201.1
10694 23:47:41.059317 <6>[ 7.288482] clk: Disabling unused clocks
10695 23:47:41.062839 <6>[ 7.293889] ALSA device list:
10696 23:47:41.066521 <6>[ 7.297192] No soundcards found.
10697 23:47:41.076770 <6>[ 7.304793] Freeing unused kernel memory: 8512K
10698 23:47:41.079848 <6>[ 7.309684] Run /init as init process
10699 23:47:41.089599 Loading, please wait...
10700 23:47:41.116379 Starting systemd-udevd version 252.22-1~deb12u1
10701 23:47:41.357759 <6>[ 7.582184] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10702 23:47:41.367379 <6>[ 7.591615] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10703 23:47:41.374511 <6>[ 7.593282] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10704 23:47:41.384310 <6>[ 7.600412] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10705 23:47:41.390710 <3>[ 7.614512] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 23:47:41.397257 <6>[ 7.623095] remoteproc remoteproc0: scp is available
10707 23:47:41.404084 <3>[ 7.626561] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 23:47:41.410670 <6>[ 7.629947] remoteproc remoteproc0: powering up scp
10709 23:47:41.417441 <3>[ 7.638263] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10710 23:47:41.423496 <4>[ 7.639119] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10711 23:47:41.433575 <4>[ 7.639433] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10712 23:47:41.440328 <6>[ 7.639932] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10713 23:47:41.450280 <6>[ 7.643486] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10714 23:47:41.454053 <6>[ 7.643670] mc: Linux media interface: v0.10
10715 23:47:41.460746 <3>[ 7.651331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 23:47:41.467784 <6>[ 7.658572] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10717 23:47:41.474627 <3>[ 7.665847] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 23:47:41.484689 <4>[ 7.670756] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10719 23:47:41.487600 <4>[ 7.670756] Fallback method does not support PEC.
10720 23:47:41.494769 <6>[ 7.684935] videodev: Linux video capture interface: v2.00
10721 23:47:41.502182 <3>[ 7.686457] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 23:47:41.512015 <3>[ 7.696072] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10723 23:47:41.518627 <3>[ 7.700246] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 23:47:41.528479 <3>[ 7.700253] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10725 23:47:41.535579 <3>[ 7.700324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10726 23:47:41.544872 <3>[ 7.700363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 23:47:41.552438 <6>[ 7.721892] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10728 23:47:41.558517 <3>[ 7.722066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 23:47:41.565449 <6>[ 7.727803] pci_bus 0000:00: root bus resource [bus 00-ff]
10730 23:47:41.575172 <3>[ 7.732153] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10731 23:47:41.581871 <3>[ 7.735874] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10732 23:47:41.588598 <6>[ 7.744643] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10733 23:47:41.598409 <3>[ 7.752764] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10734 23:47:41.604826 <6>[ 7.757329] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10735 23:47:41.614783 <6>[ 7.761031] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10736 23:47:41.624426 <3>[ 7.768873] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10737 23:47:41.631048 <3>[ 7.768878] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10738 23:47:41.641499 <3>[ 7.768882] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 23:47:41.647726 <6>[ 7.776989] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10740 23:47:41.658145 <6>[ 7.777580] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10741 23:47:41.664098 <6>[ 7.777984] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10742 23:47:41.674403 <3>[ 7.783826] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 23:47:41.681305 <6>[ 7.791913] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10744 23:47:41.691069 <3>[ 7.797655] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 23:47:41.697951 <6>[ 7.799125] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10746 23:47:41.704525 <6>[ 7.799183] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10747 23:47:41.710875 <6>[ 7.799191] remoteproc remoteproc0: remote processor scp is now up
10748 23:47:41.717787 <6>[ 7.806492] pci 0000:00:00.0: supports D1 D2
10749 23:47:41.725155 <6>[ 7.810918] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10750 23:47:41.734498 <6>[ 7.816965] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10751 23:47:41.741077 <6>[ 7.821838] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10752 23:47:41.744456 <6>[ 7.822468] Bluetooth: Core ver 2.22
10753 23:47:41.747413 <6>[ 7.822679] NET: Registered PF_BLUETOOTH protocol family
10754 23:47:41.753727 <6>[ 7.822683] Bluetooth: HCI device and connection manager initialized
10755 23:47:41.760760 <6>[ 7.822729] Bluetooth: HCI socket layer initialized
10756 23:47:41.767761 <6>[ 7.822742] Bluetooth: L2CAP socket layer initialized
10757 23:47:41.770921 <6>[ 7.822769] Bluetooth: SCO socket layer initialized
10758 23:47:41.777631 <6>[ 7.840551] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10759 23:47:41.787494 <6>[ 7.850392] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10760 23:47:41.797611 <6>[ 7.858658] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10761 23:47:41.803744 <6>[ 7.865302] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10762 23:47:41.810024 <6>[ 7.866073] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10763 23:47:41.816927 <6>[ 7.873495] usbcore: registered new interface driver uvcvideo
10764 23:47:41.824029 <6>[ 7.873863] usbcore: registered new interface driver btusb
10765 23:47:41.834133 <4>[ 7.874817] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10766 23:47:41.839948 <3>[ 7.874826] Bluetooth: hci0: Failed to load firmware file (-2)
10767 23:47:41.847129 <3>[ 7.874830] Bluetooth: hci0: Failed to set up firmware (-2)
10768 23:47:41.856647 <4>[ 7.874834] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10769 23:47:41.863453 <6>[ 7.879650] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10770 23:47:41.869661 <6>[ 8.096189] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10771 23:47:41.880258 <6>[ 8.103674] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10772 23:47:41.883353 <6>[ 8.111251] pci 0000:01:00.0: supports D1 D2
10773 23:47:41.889593 <6>[ 8.115770] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10774 23:47:41.912880 <6>[ 8.136997] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10775 23:47:41.919122 <6>[ 8.143895] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10776 23:47:41.925723 <6>[ 8.151975] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10777 23:47:41.935599 <6>[ 8.159973] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10778 23:47:41.942302 <6>[ 8.167974] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10779 23:47:41.952457 <6>[ 8.175975] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10780 23:47:41.955870 <6>[ 8.183974] pci 0000:00:00.0: PCI bridge to [bus 01]
10781 23:47:41.965887 <6>[ 8.189190] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10782 23:47:41.971826 <6>[ 8.197320] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10783 23:47:41.978503 <6>[ 8.204169] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10784 23:47:41.984942 <6>[ 8.210891] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10785 23:47:41.999511 <5>[ 8.224558] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10786 23:47:42.025193 <5>[ 8.249931] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10787 23:47:42.031838 <5>[ 8.257050] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10788 23:47:42.041572 <4>[ 8.265461] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10789 23:47:42.044736 <6>[ 8.274334] cfg80211: failed to load regulatory.db
10790 23:47:42.095699 <6>[ 8.320258] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10791 23:47:42.102222 <6>[ 8.327830] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10792 23:47:42.126677 <6>[ 8.354780] mt7921e 0000:01:00.0: ASIC revision: 79610010
10793 23:47:42.228474 <6>[ 8.453157] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10794 23:47:42.231526 <6>[ 8.453157]
10795 23:47:42.253505 Begin: Loading essential drivers ... done.
10796 23:47:42.257091 Begin: Running /scripts/init-premount ... done.
10797 23:47:42.263744 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10798 23:47:42.273630 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10799 23:47:42.276544 Device /sys/class/net/eth0 found
10800 23:47:42.276668 done.
10801 23:47:42.300990 Begin: Waiting up to 180 secs for any network device to become available ... done.
10802 23:47:42.384871 IP-Config: eth0 hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10803 23:47:42.391128 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10804 23:47:42.397958 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10805 23:47:42.404625 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10806 23:47:42.411778 host : mt8192-asurada-spherion-r0-cbg-0
10807 23:47:42.418105 domain : lava-rack
10808 23:47:42.421330 rootserver: 192.168.201.1 rootpath:
10809 23:47:42.421513 filename :
10810 23:47:42.497813 <6>[ 8.722591] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10811 23:47:42.635276 done.
10812 23:47:42.638669 Begin: Running /scripts/nfs-bottom ... done.
10813 23:47:42.658423 Begin: Running /scripts/init-bottom ... done.
10814 23:47:43.946431 <6>[ 10.175114] NET: Registered PF_INET6 protocol family
10815 23:47:43.954093 <6>[ 10.182258] Segment Routing with IPv6
10816 23:47:43.957213 <6>[ 10.186240] In-situ OAM (IOAM) with IPv6
10817 23:47:44.115392 <30>[ 10.316924] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10818 23:47:44.122413 <30>[ 10.350075] systemd[1]: Detected architecture arm64.
10819 23:47:44.128442
10820 23:47:44.131259 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10821 23:47:44.131364
10822 23:47:44.153286 <30>[ 10.381615] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10823 23:47:45.071283 <30>[ 11.296796] systemd[1]: Queued start job for default target graphical.target.
10824 23:47:45.108576 <30>[ 11.334082] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10825 23:47:45.115468 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10826 23:47:45.137718 <30>[ 11.362818] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10827 23:47:45.147178 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10828 23:47:45.165954 <30>[ 11.390780] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10829 23:47:45.175346 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10830 23:47:45.193542 <30>[ 11.418404] systemd[1]: Created slice user.slice - User and Session Slice.
10831 23:47:45.199657 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10832 23:47:45.223252 <30>[ 11.445345] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10833 23:47:45.230331 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10834 23:47:45.251694 <30>[ 11.473282] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10835 23:47:45.257677 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10836 23:47:45.286471 <30>[ 11.501685] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10837 23:47:45.296224 <30>[ 11.521582] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10838 23:47:45.302629 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10839 23:47:45.319961 <30>[ 11.545060] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10840 23:47:45.326782 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10841 23:47:45.343766 <30>[ 11.569109] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10842 23:47:45.353654 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10843 23:47:45.368358 <30>[ 11.597156] systemd[1]: Reached target paths.target - Path Units.
10844 23:47:45.378519 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10845 23:47:45.396285 <30>[ 11.621505] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10846 23:47:45.402932 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10847 23:47:45.416640 <30>[ 11.645052] systemd[1]: Reached target slices.target - Slice Units.
10848 23:47:45.426591 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10849 23:47:45.441647 <30>[ 11.669562] systemd[1]: Reached target swap.target - Swaps.
10850 23:47:45.447848 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10851 23:47:45.467972 <30>[ 11.693541] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10852 23:47:45.477965 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10853 23:47:45.495980 <30>[ 11.721522] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10854 23:47:45.506194 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10855 23:47:45.526516 <30>[ 11.751805] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10856 23:47:45.536324 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10857 23:47:45.552987 <30>[ 11.778389] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10858 23:47:45.563073 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10859 23:47:45.580328 <30>[ 11.805733] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10860 23:47:45.586874 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10861 23:47:45.604959 <30>[ 11.830432] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10862 23:47:45.615033 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10863 23:47:45.634317 <30>[ 11.859709] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10864 23:47:45.644603 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10865 23:47:45.660326 <30>[ 11.885529] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10866 23:47:45.670002 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10867 23:47:45.720206 <30>[ 11.945237] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10868 23:47:45.726783 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10869 23:47:45.748226 <30>[ 11.973669] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10870 23:47:45.755265 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10871 23:47:45.816113 <30>[ 12.041461] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10872 23:47:45.823061 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10873 23:47:45.850702 <30>[ 12.069508] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10874 23:47:45.866232 <30>[ 12.091143] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10875 23:47:45.875703 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10876 23:47:45.897357 <30>[ 12.122403] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10877 23:47:45.903787 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10878 23:47:45.944643 <30>[ 12.169705] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10879 23:47:45.951282 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10880 23:47:45.977107 <30>[ 12.202556] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10881 23:47:45.987215 Startin<6>[ 12.211906] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10882 23:47:45.993633 g [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10883 23:47:46.017299 <30>[ 12.242509] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10884 23:47:46.027255 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10885 23:47:46.049436 <30>[ 12.274485] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10886 23:47:46.055691 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10887 23:47:46.083231 <6>[ 12.312139] fuse: init (API version 7.37)
10888 23:47:46.112231 <30>[ 12.337900] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10889 23:47:46.119219 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10890 23:47:46.149257 <30>[ 12.374840] systemd[1]: Starting systemd-journald.service - Journal Service...
10891 23:47:46.155752 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10892 23:47:46.177319 <30>[ 12.402475] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10893 23:47:46.186436 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10894 23:47:46.244130 <30>[ 12.465899] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10895 23:47:46.250525 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10896 23:47:46.273776 <30>[ 12.498959] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10897 23:47:46.283639 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10898 23:47:46.309636 <3>[ 12.535205] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10899 23:47:46.319817 <30>[ 12.535238] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10900 23:47:46.326052 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10901 23:47:46.347994 <3>[ 12.573061] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 23:47:46.354117 <30>[ 12.579144] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10903 23:47:46.370798 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10904 23:47:46.392807 <30>[ 12.617354] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10905 23:47:46.402881 [[0;32m OK [0m] Mounted [0;<3>[ 12.627301] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 23:47:46.409044 1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10907 23:47:46.432188 <30>[ 12.657267] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10908 23:47:46.441646 <3>[ 12.657646] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 23:47:46.448708 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10910 23:47:46.469654 <3>[ 12.694962] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 23:47:46.479308 <30>[ 12.695207] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10912 23:47:46.495813 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10913 23:47:46.514687 <3>[ 12.733734] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 23:47:46.519102 <30>[ 12.744576] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10915 23:47:46.530771 <30>[ 12.753310] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10916 23:47:46.540501 [[0;32m OK [0m] Finished [0<3>[ 12.764391] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 23:47:46.546807 ;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10918 23:47:46.562016 <30>[ 12.790058] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10919 23:47:46.572258 <3>[ 12.797571] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 23:47:46.582360 <30>[ 12.798240] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10921 23:47:46.588731 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10922 23:47:46.604363 <3>[ 12.829739] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 23:47:46.615350 <30>[ 12.841050] systemd[1]: modprobe@drm.service: Deactivated successfully.
10924 23:47:46.622844 <30>[ 12.848589] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10925 23:47:46.639570 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Mod<3>[ 12.862984] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 23:47:46.639735 ule drm.
10927 23:47:46.658315 <30>[ 12.882913] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10928 23:47:46.665262 <30>[ 12.891083] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10929 23:47:46.675208 <3>[ 12.895210] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 23:47:46.684835 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10931 23:47:46.697931 <30>[ 12.926268] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10932 23:47:46.709229 <30>[ 12.934341] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10933 23:47:46.719108 <3>[ 12.935271] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10934 23:47:46.726210 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10935 23:47:46.737355 <3>[ 12.963123] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 23:47:46.747804 <3>[ 12.963898] power_supply sbs-5-000b: driver failed to report `status' property: -6
10937 23:47:46.760821 <4>[ 12.971937] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10938 23:47:46.771093 <3>[ 12.971942] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10939 23:47:46.777758 <30>[ 12.981531] systemd[1]: modprobe@loop.service: Deactivated successfully.
10940 23:47:46.784552 <30>[ 13.010710] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10941 23:47:46.794673 <3>[ 13.018402] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 23:47:46.801978 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10943 23:47:46.825728 <30>[ 13.050992] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10944 23:47:46.835167 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10945 23:47:46.856847 <30>[ 13.078311] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10946 23:47:46.863242 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10947 23:47:46.880898 <30>[ 13.106485] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10948 23:47:46.890770 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10949 23:47:46.909585 <30>[ 13.134327] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10950 23:47:46.916267 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10951 23:47:46.936033 <30>[ 13.161700] systemd[1]: Started systemd-journald.service - Journal Service.
10952 23:47:46.942962 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10953 23:47:46.965704 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10954 23:47:47.016357 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10955 23:47:47.036263 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10956 23:47:47.059195 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10957 23:47:47.079863 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10958 23:47:47.105175 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10959 23:47:47.130623 <46>[ 13.355806] systemd-journald[311]: Received client request to flush runtime journal.
10960 23:47:47.136797 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10961 23:47:47.175277 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10962 23:47:47.192653 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10963 23:47:47.213553 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10964 23:47:47.233306 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10965 23:47:47.913074 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10966 23:47:47.948062 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10967 23:47:48.534003 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10968 23:47:48.577480 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10969 23:47:48.596003 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10970 23:47:48.615784 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10971 23:47:48.660253 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10972 23:47:48.680769 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10973 23:47:48.900446 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10974 23:47:48.963119 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10975 23:47:49.005195 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10976 23:47:49.041420 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10977 23:47:49.213539 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10978 23:47:49.244189 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10979 23:47:49.328506 <6>[ 15.557647] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10980 23:47:49.410334 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10981 23:47:49.470560 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10982 23:47:49.492523 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10983 23:47:49.533948 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10984 23:47:49.578033 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10985 23:47:49.596121 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10986 23:47:49.619046 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10987 23:47:49.636234 <46>[ 15.865193] systemd-journald[311]: Time jumped backwards, rotating.
10988 23:47:49.643038 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10989 23:47:49.667429 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10990 23:47:49.683919 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10991 23:47:49.699470 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10992 23:47:50.416216 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10993 23:47:50.746440 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10994 23:47:50.763566 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10995 23:47:51.114472 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10996 23:47:51.134916 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10997 23:47:51.155310 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10998 23:47:51.174621 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10999 23:47:51.190920 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11000 23:47:51.207657 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11001 23:47:51.223478 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11002 23:47:51.268824 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11003 23:47:51.300282 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11004 23:47:51.339646 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11005 23:47:51.359778 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11006 23:47:51.391737 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11007 23:47:51.602225 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11008 23:47:51.668352 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11009 23:47:51.739670 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11010 23:47:51.755629 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11011 23:47:51.772318 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11012 23:47:51.791232 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11013 23:47:51.823701 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11014 23:47:51.846920 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11015 23:47:51.866087 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11016 23:47:51.885034 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11017 23:47:51.953870 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11018 23:47:51.993377 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11019 23:47:52.076221
11020 23:47:52.079859 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11021 23:47:52.080008
11022 23:47:52.083019 debian-bookworm-arm64 login: root (automatic login)
11023 23:47:52.083154
11024 23:47:52.349154 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024 aarch64
11025 23:47:52.349299
11026 23:47:52.356026 The programs included with the Debian GNU/Linux system are free software;
11027 23:47:52.362543 the exact distribution terms for each program are described in the
11028 23:47:52.366427 individual files in /usr/share/doc/*/copyright.
11029 23:47:52.366508
11030 23:47:52.372576 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11031 23:47:52.375703 permitted by applicable law.
11032 23:47:53.340670 Matched prompt #10: / #
11034 23:47:53.341078 Setting prompt string to ['/ #']
11035 23:47:53.341221 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11037 23:47:53.341543 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11038 23:47:53.341682 start: 2.2.6 expect-shell-connection (timeout 00:03:41) [common]
11039 23:47:53.341792 Setting prompt string to ['/ #']
11040 23:47:53.341896 Forcing a shell prompt, looking for ['/ #']
11042 23:47:53.392200 / #
11043 23:47:53.392430 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11044 23:47:53.392547 Waiting using forced prompt support (timeout 00:02:30)
11045 23:47:53.397025
11046 23:47:53.397342 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11047 23:47:53.397442 start: 2.2.7 export-device-env (timeout 00:03:41) [common]
11049 23:47:53.497805 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172931/extract-nfsrootfs-ivx2x1zz'
11050 23:47:53.502636 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172931/extract-nfsrootfs-ivx2x1zz'
11052 23:47:53.603163 / # export NFS_SERVER_IP='192.168.201.1'
11053 23:47:53.608546 export NFS_SERVER_IP='192.168.201.1'
11054 23:47:53.608831 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11055 23:47:53.608930 end: 2.2 depthcharge-retry (duration 00:01:19) [common]
11056 23:47:53.609017 end: 2 depthcharge-action (duration 00:01:19) [common]
11057 23:47:53.609105 start: 3 lava-test-retry (timeout 00:08:00) [common]
11058 23:47:53.609191 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
11059 23:47:53.609265 Using namespace: common
11061 23:47:53.709644 / # #
11062 23:47:53.710013 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11063 23:47:53.715361 #
11064 23:47:53.715883 Using /lava-14172931
11066 23:47:53.816501 / # export SHELL=/bin/bash
11067 23:47:53.821171 export SHELL=/bin/bash
11069 23:47:53.921683 / # . /lava-14172931/environment
11070 23:47:53.927002 . /lava-14172931/environment
11072 23:47:54.032622 / # /lava-14172931/bin/lava-test-runner /lava-14172931/0
11073 23:47:54.032826 Test shell timeout: 10s (minimum of the action and connection timeout)
11074 23:47:54.037905 /lava-14172931/bin/lava-test-runner /lava-14172931/0
11075 23:47:54.226772 + export TESTRUN_ID=0_timesync-off
11076 23:47:54.230431 + TESTRUN_ID=0_timesync-off
11077 23:47:54.233671 + cd /lava-14172931/0/tests/0_timesync-off
11078 23:47:54.236758 ++ cat uuid
11079 23:47:54.236845 + UUID=14172931_1.6.2.3.1
11080 23:47:54.240321 + set +x
11081 23:47:54.243426 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14172931_1.6.2.3.1>
11082 23:47:54.243694 Received signal: <STARTRUN> 0_timesync-off 14172931_1.6.2.3.1
11083 23:47:54.243771 Starting test lava.0_timesync-off (14172931_1.6.2.3.1)
11084 23:47:54.243858 Skipping test definition patterns.
11085 23:47:54.246402 + systemctl stop systemd-timesyncd
11086 23:47:54.323223 + set +x
11087 23:47:54.326379 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14172931_1.6.2.3.1>
11088 23:47:54.326650 Received signal: <ENDRUN> 0_timesync-off 14172931_1.6.2.3.1
11089 23:47:54.326791 Ending use of test pattern.
11090 23:47:54.326892 Ending test lava.0_timesync-off (14172931_1.6.2.3.1), duration 0.08
11092 23:47:54.376164 + export TESTRUN_ID=1_kselftest-dt
11093 23:47:54.380026 + TESTRUN_ID=1_kselftest-dt
11094 23:47:54.383193 + cd /lava-14172931/0/tests/1_kselftest-dt
11095 23:47:54.386135 ++ cat uuid
11096 23:47:54.386222 + UUID=14172931_1.6.2.3.5
11097 23:47:54.389524 + set +x
11098 23:47:54.393276 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 14172931_1.6.2.3.5>
11099 23:47:54.393541 Received signal: <STARTRUN> 1_kselftest-dt 14172931_1.6.2.3.5
11100 23:47:54.393614 Starting test lava.1_kselftest-dt (14172931_1.6.2.3.5)
11101 23:47:54.393698 Skipping test definition patterns.
11102 23:47:54.396485 + cd ./automated/linux/kselftest/
11103 23:47:54.422849 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11104 23:47:54.444066 INFO: install_deps skipped
11105 23:47:54.923434 --2024-06-04 23:43:13-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11106 23:47:54.933739 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11107 23:47:55.062756 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11108 23:47:55.192120 HTTP request sent, awaiting response... 200 OK
11109 23:47:55.195423 Length: 1642752 (1.6M) [application/octet-stream]
11110 23:47:55.198787 Saving to: 'kselftest_armhf.tar.gz'
11111 23:47:55.198923
11112 23:47:55.199022
11113 23:47:55.449598 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11114 23:47:55.706043 kselftest_armhf.tar 2%[ ] 47.81K 186KB/s
11115 23:47:56.009672 kselftest_armhf.tar 13%[=> ] 216.08K 421KB/s
11116 23:47:56.140545 kselftest_armhf.tar 51%[=========> ] 829.78K 1015KB/s
11117 23:47:56.147115 kselftest_armhf.tar 100%[===================>] 1.57M 1.65MB/s in 0.9s
11118 23:47:56.147247
11119 23:47:56.291722 2024-06-04 23:43:14 (1.65 MB/s) - 'kselftest_armhf.tar.gz' saved [1642752/1642752]
11120 23:47:56.291857
11121 23:47:59.953062 skiplist:
11122 23:47:59.956725 ========================================
11123 23:47:59.959612 ========================================
11124 23:48:00.014436 ============== Tests to run ===============
11125 23:48:00.017902 ===========End Tests to run ===============
11126 23:48:00.017996 shardfile-dt fail
11127 23:48:00.039085 ./kselftest.sh: 131: cannot open /lava-14172931/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11128 23:48:00.042321 + ../../utils/send-to-lava.sh ./output/result.txt
11129 23:48:00.084866 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11130 23:48:00.085001 + set +x
11131 23:48:00.085252 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11133 23:48:00.091310 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 14172931_1.6.2.3.5>
11134 23:48:00.091621 Received signal: <ENDRUN> 1_kselftest-dt 14172931_1.6.2.3.5
11135 23:48:00.091731 Ending use of test pattern.
11136 23:48:00.091829 Ending test lava.1_kselftest-dt (14172931_1.6.2.3.5), duration 5.70
11138 23:48:00.092091 ok: lava_test_shell seems to have completed
11139 23:48:00.092186 shardfile-dt: fail
11140 23:48:00.092275 end: 3.1 lava-test-shell (duration 00:00:06) [common]
11141 23:48:00.092372 end: 3 lava-test-retry (duration 00:00:06) [common]
11142 23:48:00.092463 start: 4 finalize (timeout 00:07:54) [common]
11143 23:48:00.092553 start: 4.1 power-off (timeout 00:00:30) [common]
11144 23:48:00.092708 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-0', '--port=1', '--command=off']
11145 23:48:00.172321 >> Command sent successfully.
11146 23:48:00.175111 Returned 0 in 0 seconds
11147 23:48:00.275517 end: 4.1 power-off (duration 00:00:00) [common]
11149 23:48:00.275837 start: 4.2 read-feedback (timeout 00:07:54) [common]
11151 23:48:00.276444 Listened to connection for namespace 'common' for up to 1s
11152 23:48:01.276436 Finalising connection for namespace 'common'
11153 23:48:01.276605 Disconnecting from shell: Finalise
11154 23:48:01.276700 / #
11155 23:48:01.377030 end: 4.2 read-feedback (duration 00:00:01) [common]
11156 23:48:01.377200 end: 4 finalize (duration 00:00:01) [common]
11157 23:48:01.377316 Cleaning after the job
11158 23:48:01.377428 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/ramdisk
11159 23:48:01.379632 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/kernel
11160 23:48:01.390489 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/dtb
11161 23:48:01.390708 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/nfsrootfs
11162 23:48:01.454683 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172931/tftp-deploy-gt1vhnjs/modules
11163 23:48:01.460503 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14172931
11164 23:48:02.044629 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14172931
11165 23:48:02.044794 Job finished correctly