Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 36
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 23:45:04.189748 lava-dispatcher, installed at version: 2024.03
2 23:45:04.189947 start: 0 validate
3 23:45:04.190090 Start time: 2024-06-04 23:45:04.190079+00:00 (UTC)
4 23:45:04.190208 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:45:04.190334 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:45:04.449161 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:45:04.449369 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:45:04.707490 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:45:04.707713 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:45:04.967794 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:45:04.968421 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:45:05.230456 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:45:05.231251 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:45:05.507426 validate duration: 1.32
16 23:45:05.508790 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:45:05.509419 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:45:05.509879 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:45:05.510450 Not decompressing ramdisk as can be used compressed.
20 23:45:05.510885 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:45:05.511236 saving as /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/ramdisk/initrd.cpio.gz
22 23:45:05.511570 total size: 5628169 (5 MB)
23 23:45:05.516682 progress 0 % (0 MB)
24 23:45:05.524931 progress 5 % (0 MB)
25 23:45:05.530065 progress 10 % (0 MB)
26 23:45:05.533735 progress 15 % (0 MB)
27 23:45:05.537236 progress 20 % (1 MB)
28 23:45:05.540074 progress 25 % (1 MB)
29 23:45:05.542976 progress 30 % (1 MB)
30 23:45:05.545498 progress 35 % (1 MB)
31 23:45:05.547670 progress 40 % (2 MB)
32 23:45:05.549891 progress 45 % (2 MB)
33 23:45:05.551826 progress 50 % (2 MB)
34 23:45:05.553866 progress 55 % (2 MB)
35 23:45:05.555743 progress 60 % (3 MB)
36 23:45:05.557492 progress 65 % (3 MB)
37 23:45:05.559278 progress 70 % (3 MB)
38 23:45:05.560793 progress 75 % (4 MB)
39 23:45:05.562556 progress 80 % (4 MB)
40 23:45:05.564001 progress 85 % (4 MB)
41 23:45:05.565562 progress 90 % (4 MB)
42 23:45:05.567169 progress 95 % (5 MB)
43 23:45:05.568592 progress 100 % (5 MB)
44 23:45:05.568802 5 MB downloaded in 0.06 s (93.75 MB/s)
45 23:45:05.568955 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:45:05.569195 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:45:05.569326 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:45:05.569412 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:45:05.569534 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:45:05.569604 saving as /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/kernel/Image
52 23:45:05.569666 total size: 54682112 (52 MB)
53 23:45:05.569729 No compression specified
54 23:45:05.570815 progress 0 % (0 MB)
55 23:45:05.584665 progress 5 % (2 MB)
56 23:45:05.598553 progress 10 % (5 MB)
57 23:45:05.612840 progress 15 % (7 MB)
58 23:45:05.627673 progress 20 % (10 MB)
59 23:45:05.642005 progress 25 % (13 MB)
60 23:45:05.656303 progress 30 % (15 MB)
61 23:45:05.670803 progress 35 % (18 MB)
62 23:45:05.684714 progress 40 % (20 MB)
63 23:45:05.698659 progress 45 % (23 MB)
64 23:45:05.712824 progress 50 % (26 MB)
65 23:45:05.726789 progress 55 % (28 MB)
66 23:45:05.740801 progress 60 % (31 MB)
67 23:45:05.754724 progress 65 % (33 MB)
68 23:45:05.768724 progress 70 % (36 MB)
69 23:45:05.782510 progress 75 % (39 MB)
70 23:45:05.796576 progress 80 % (41 MB)
71 23:45:05.810357 progress 85 % (44 MB)
72 23:45:05.824072 progress 90 % (46 MB)
73 23:45:05.838238 progress 95 % (49 MB)
74 23:45:05.852226 progress 100 % (52 MB)
75 23:45:05.852465 52 MB downloaded in 0.28 s (184.41 MB/s)
76 23:45:05.852618 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:45:05.852877 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:45:05.852967 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:45:05.853062 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:45:05.853267 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:45:05.853356 saving as /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/dtb/mt8192-asurada-spherion-r0.dtb
83 23:45:05.853420 total size: 47258 (0 MB)
84 23:45:05.853483 No compression specified
85 23:45:05.854659 progress 69 % (0 MB)
86 23:45:05.854981 progress 100 % (0 MB)
87 23:45:05.855140 0 MB downloaded in 0.00 s (26.24 MB/s)
88 23:45:05.855273 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:45:05.855497 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:45:05.855584 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:45:05.855668 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:45:05.855781 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:45:05.855864 saving as /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/nfsrootfs/full.rootfs.tar
95 23:45:05.855929 total size: 120894716 (115 MB)
96 23:45:05.855992 Using unxz to decompress xz
97 23:45:05.860002 progress 0 % (0 MB)
98 23:45:06.205664 progress 5 % (5 MB)
99 23:45:06.560350 progress 10 % (11 MB)
100 23:45:06.915062 progress 15 % (17 MB)
101 23:45:07.255292 progress 20 % (23 MB)
102 23:45:07.547167 progress 25 % (28 MB)
103 23:45:07.901561 progress 30 % (34 MB)
104 23:45:08.237963 progress 35 % (40 MB)
105 23:45:08.401536 progress 40 % (46 MB)
106 23:45:08.577048 progress 45 % (51 MB)
107 23:45:08.884882 progress 50 % (57 MB)
108 23:45:09.254807 progress 55 % (63 MB)
109 23:45:09.597768 progress 60 % (69 MB)
110 23:45:09.936222 progress 65 % (74 MB)
111 23:45:10.278631 progress 70 % (80 MB)
112 23:45:10.634581 progress 75 % (86 MB)
113 23:45:10.976543 progress 80 % (92 MB)
114 23:45:11.312845 progress 85 % (98 MB)
115 23:45:11.665866 progress 90 % (103 MB)
116 23:45:11.991030 progress 95 % (109 MB)
117 23:45:12.349140 progress 100 % (115 MB)
118 23:45:12.354636 115 MB downloaded in 6.50 s (17.74 MB/s)
119 23:45:12.354897 end: 1.4.1 http-download (duration 00:00:06) [common]
121 23:45:12.355163 end: 1.4 download-retry (duration 00:00:06) [common]
122 23:45:12.355258 start: 1.5 download-retry (timeout 00:09:53) [common]
123 23:45:12.355344 start: 1.5.1 http-download (timeout 00:09:53) [common]
124 23:45:12.355491 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:45:12.355560 saving as /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/modules/modules.tar
126 23:45:12.355620 total size: 8603924 (8 MB)
127 23:45:12.355682 Using unxz to decompress xz
128 23:45:12.359676 progress 0 % (0 MB)
129 23:45:12.379755 progress 5 % (0 MB)
130 23:45:12.404294 progress 10 % (0 MB)
131 23:45:12.430213 progress 15 % (1 MB)
132 23:45:12.455233 progress 20 % (1 MB)
133 23:45:12.481232 progress 25 % (2 MB)
134 23:45:12.506519 progress 30 % (2 MB)
135 23:45:12.529914 progress 35 % (2 MB)
136 23:45:12.556058 progress 40 % (3 MB)
137 23:45:12.580584 progress 45 % (3 MB)
138 23:45:12.604653 progress 50 % (4 MB)
139 23:45:12.629509 progress 55 % (4 MB)
140 23:45:12.654818 progress 60 % (4 MB)
141 23:45:12.679093 progress 65 % (5 MB)
142 23:45:12.705728 progress 70 % (5 MB)
143 23:45:12.731929 progress 75 % (6 MB)
144 23:45:12.759073 progress 80 % (6 MB)
145 23:45:12.786481 progress 85 % (7 MB)
146 23:45:12.811149 progress 90 % (7 MB)
147 23:45:12.841018 progress 95 % (7 MB)
148 23:45:12.869586 progress 100 % (8 MB)
149 23:45:12.875236 8 MB downloaded in 0.52 s (15.79 MB/s)
150 23:45:12.875531 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:45:12.875812 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:45:12.875925 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 23:45:12.876030 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 23:45:16.373201 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14172986/extract-nfsrootfs-gk86ljjv
156 23:45:16.373442 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 23:45:16.373542 start: 1.6.2 lava-overlay (timeout 00:09:49) [common]
158 23:45:16.373711 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f
159 23:45:16.373842 makedir: /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin
160 23:45:16.373942 makedir: /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/tests
161 23:45:16.374039 makedir: /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/results
162 23:45:16.374138 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-add-keys
163 23:45:16.374276 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-add-sources
164 23:45:16.374403 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-background-process-start
165 23:45:16.374546 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-background-process-stop
166 23:45:16.374675 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-common-functions
167 23:45:16.374799 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-echo-ipv4
168 23:45:16.374922 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-install-packages
169 23:45:16.375045 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-installed-packages
170 23:45:16.375166 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-os-build
171 23:45:16.375292 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-probe-channel
172 23:45:16.375415 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-probe-ip
173 23:45:16.375536 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-target-ip
174 23:45:16.375656 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-target-mac
175 23:45:16.375775 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-target-storage
176 23:45:16.375897 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-test-case
177 23:45:16.376018 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-test-event
178 23:45:16.376167 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-test-feedback
179 23:45:16.376290 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-test-raise
180 23:45:16.376415 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-test-reference
181 23:45:16.376541 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-test-runner
182 23:45:16.376661 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-test-set
183 23:45:16.376784 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-test-shell
184 23:45:16.376908 Updating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-add-keys (debian)
185 23:45:16.377055 Updating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-add-sources (debian)
186 23:45:16.377200 Updating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-install-packages (debian)
187 23:45:16.377537 Updating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-installed-packages (debian)
188 23:45:16.377679 Updating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/bin/lava-os-build (debian)
189 23:45:16.377798 Creating /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/environment
190 23:45:16.377899 LAVA metadata
191 23:45:16.377965 - LAVA_JOB_ID=14172986
192 23:45:16.378026 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:45:16.378126 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:49) [common]
194 23:45:16.378190 skipped lava-vland-overlay
195 23:45:16.378263 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:45:16.378342 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:49) [common]
197 23:45:16.378401 skipped lava-multinode-overlay
198 23:45:16.378471 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:45:16.378546 start: 1.6.2.3 test-definition (timeout 00:09:49) [common]
200 23:45:16.378618 Loading test definitions
201 23:45:16.378705 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:49) [common]
202 23:45:16.378773 Using /lava-14172986 at stage 0
203 23:45:16.379049 uuid=14172986_1.6.2.3.1 testdef=None
204 23:45:16.379134 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:45:16.379217 start: 1.6.2.3.2 test-overlay (timeout 00:09:49) [common]
206 23:45:16.379665 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:45:16.379881 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:49) [common]
209 23:45:16.380422 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:45:16.380647 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:49) [common]
212 23:45:16.381175 runner path: /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/0/tests/0_timesync-off test_uuid 14172986_1.6.2.3.1
213 23:45:16.381366 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:45:16.381589 start: 1.6.2.3.5 git-repo-action (timeout 00:09:49) [common]
216 23:45:16.381660 Using /lava-14172986 at stage 0
217 23:45:16.381756 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:45:16.381841 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/0/tests/1_kselftest-rtc'
219 23:45:19.027450 Running '/usr/bin/git checkout kernelci.org
220 23:45:19.066595 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 23:45:19.067556 uuid=14172986_1.6.2.3.5 testdef=None
222 23:45:19.067732 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 23:45:19.067996 start: 1.6.2.3.6 test-overlay (timeout 00:09:46) [common]
225 23:45:19.068751 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:45:19.068996 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:46) [common]
228 23:45:19.070039 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:45:19.070278 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:46) [common]
231 23:45:19.071515 runner path: /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/0/tests/1_kselftest-rtc test_uuid 14172986_1.6.2.3.5
232 23:45:19.071637 BOARD='mt8192-asurada-spherion-r0'
233 23:45:19.071729 BRANCH='cip'
234 23:45:19.071817 SKIPFILE='/dev/null'
235 23:45:19.071906 SKIP_INSTALL='True'
236 23:45:19.071990 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:45:19.072077 TST_CASENAME=''
238 23:45:19.072161 TST_CMDFILES='rtc'
239 23:45:19.072352 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:45:19.072699 Creating lava-test-runner.conf files
242 23:45:19.072790 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14172986/lava-overlay-fum3sj9f/lava-14172986/0 for stage 0
243 23:45:19.072910 - 0_timesync-off
244 23:45:19.073011 - 1_kselftest-rtc
245 23:45:19.073165 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 23:45:19.073311 start: 1.6.2.4 compress-overlay (timeout 00:09:46) [common]
247 23:45:26.770004 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 23:45:26.770154 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:39) [common]
249 23:45:26.770247 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:45:26.770348 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 23:45:26.770443 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:39) [common]
252 23:45:26.937727 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:45:26.938168 start: 1.6.4 extract-modules (timeout 00:09:39) [common]
254 23:45:26.938318 extracting modules file /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172986/extract-nfsrootfs-gk86ljjv
255 23:45:27.177516 extracting modules file /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172986/extract-overlay-ramdisk-pr65fxaw/ramdisk
256 23:45:27.416797 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:45:27.416967 start: 1.6.5 apply-overlay-tftp (timeout 00:09:38) [common]
258 23:45:27.417062 [common] Applying overlay to NFS
259 23:45:27.417136 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172986/compress-overlay-vmthvbr0/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14172986/extract-nfsrootfs-gk86ljjv
260 23:45:28.370592 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:45:28.370755 start: 1.6.6 configure-preseed-file (timeout 00:09:37) [common]
262 23:45:28.370849 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:45:28.370942 start: 1.6.7 compress-ramdisk (timeout 00:09:37) [common]
264 23:45:28.371026 Building ramdisk /var/lib/lava/dispatcher/tmp/14172986/extract-overlay-ramdisk-pr65fxaw/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14172986/extract-overlay-ramdisk-pr65fxaw/ramdisk
265 23:45:28.738567 >> 130337 blocks
266 23:45:30.763986 rename /var/lib/lava/dispatcher/tmp/14172986/extract-overlay-ramdisk-pr65fxaw/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/ramdisk/ramdisk.cpio.gz
267 23:45:30.764415 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:45:30.764539 start: 1.6.8 prepare-kernel (timeout 00:09:35) [common]
269 23:45:30.764644 start: 1.6.8.1 prepare-fit (timeout 00:09:35) [common]
270 23:45:30.764746 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/kernel/Image']
271 23:45:44.259737 Returned 0 in 13 seconds
272 23:45:44.360368 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/kernel/image.itb
273 23:45:44.725250 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:45:44.725632 output: Created: Wed Jun 5 00:45:44 2024
275 23:45:44.725712 output: Image 0 (kernel-1)
276 23:45:44.725780 output: Description:
277 23:45:44.725846 output: Created: Wed Jun 5 00:45:44 2024
278 23:45:44.725910 output: Type: Kernel Image
279 23:45:44.725974 output: Compression: lzma compressed
280 23:45:44.726031 output: Data Size: 13061430 Bytes = 12755.30 KiB = 12.46 MiB
281 23:45:44.726092 output: Architecture: AArch64
282 23:45:44.726151 output: OS: Linux
283 23:45:44.726205 output: Load Address: 0x00000000
284 23:45:44.726259 output: Entry Point: 0x00000000
285 23:45:44.726316 output: Hash algo: crc32
286 23:45:44.726370 output: Hash value: ecfb5096
287 23:45:44.726426 output: Image 1 (fdt-1)
288 23:45:44.726480 output: Description: mt8192-asurada-spherion-r0
289 23:45:44.726536 output: Created: Wed Jun 5 00:45:44 2024
290 23:45:44.726589 output: Type: Flat Device Tree
291 23:45:44.726644 output: Compression: uncompressed
292 23:45:44.726697 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 23:45:44.726751 output: Architecture: AArch64
294 23:45:44.726803 output: Hash algo: crc32
295 23:45:44.726856 output: Hash value: 0f8e4d2e
296 23:45:44.726908 output: Image 2 (ramdisk-1)
297 23:45:44.726961 output: Description: unavailable
298 23:45:44.727014 output: Created: Wed Jun 5 00:45:44 2024
299 23:45:44.727067 output: Type: RAMDisk Image
300 23:45:44.727119 output: Compression: Unknown Compression
301 23:45:44.727171 output: Data Size: 18718513 Bytes = 18279.80 KiB = 17.85 MiB
302 23:45:44.727224 output: Architecture: AArch64
303 23:45:44.727277 output: OS: Linux
304 23:45:44.727329 output: Load Address: unavailable
305 23:45:44.727382 output: Entry Point: unavailable
306 23:45:44.727434 output: Hash algo: crc32
307 23:45:44.727486 output: Hash value: 5dcc6a23
308 23:45:44.727539 output: Default Configuration: 'conf-1'
309 23:45:44.727591 output: Configuration 0 (conf-1)
310 23:45:44.727644 output: Description: mt8192-asurada-spherion-r0
311 23:45:44.727696 output: Kernel: kernel-1
312 23:45:44.727749 output: Init Ramdisk: ramdisk-1
313 23:45:44.727801 output: FDT: fdt-1
314 23:45:44.727853 output: Loadables: kernel-1
315 23:45:44.727905 output:
316 23:45:44.728112 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 23:45:44.728214 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 23:45:44.728323 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 23:45:44.728416 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 23:45:44.728494 No LXC device requested
321 23:45:44.728573 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:45:44.728662 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 23:45:44.728739 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:45:44.728842 Checking files for TFTP limit of 4294967296 bytes.
325 23:45:44.729363 end: 1 tftp-deploy (duration 00:00:39) [common]
326 23:45:44.729471 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:45:44.729561 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:45:44.729730 substitutions:
329 23:45:44.729832 - {DTB}: 14172986/tftp-deploy-6o449hfs/dtb/mt8192-asurada-spherion-r0.dtb
330 23:45:44.729898 - {INITRD}: 14172986/tftp-deploy-6o449hfs/ramdisk/ramdisk.cpio.gz
331 23:45:44.729958 - {KERNEL}: 14172986/tftp-deploy-6o449hfs/kernel/Image
332 23:45:44.730015 - {LAVA_MAC}: None
333 23:45:44.730072 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14172986/extract-nfsrootfs-gk86ljjv
334 23:45:44.730128 - {NFS_SERVER_IP}: 192.168.201.1
335 23:45:44.730183 - {PRESEED_CONFIG}: None
336 23:45:44.730237 - {PRESEED_LOCAL}: None
337 23:45:44.730292 - {RAMDISK}: 14172986/tftp-deploy-6o449hfs/ramdisk/ramdisk.cpio.gz
338 23:45:44.730348 - {ROOT_PART}: None
339 23:45:44.730402 - {ROOT}: None
340 23:45:44.730456 - {SERVER_IP}: 192.168.201.1
341 23:45:44.730510 - {TEE}: None
342 23:45:44.730566 Parsed boot commands:
343 23:45:44.730621 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:45:44.730804 Parsed boot commands: tftpboot 192.168.201.1 14172986/tftp-deploy-6o449hfs/kernel/image.itb 14172986/tftp-deploy-6o449hfs/kernel/cmdline
345 23:45:44.730894 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:45:44.730978 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:45:44.731069 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:45:44.731153 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:45:44.731225 Not connected, no need to disconnect.
350 23:45:44.731299 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:45:44.731380 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:45:44.731451 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 23:45:44.735052 Setting prompt string to ['lava-test: # ']
354 23:45:44.735420 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:45:44.735527 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:45:44.735630 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:45:44.735720 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:45:44.735930 Calling: ['/usr/local/bin/chromebook-reboot.sh', 'mt8192-asurada-spherion-r0-cbg-2']
359 23:45:58.717383 Returned 0 in 13 seconds
360 23:45:58.818015 end: 2.2.2.1 pdu-reboot (duration 00:00:14) [common]
362 23:45:58.818466 end: 2.2.2 reset-device (duration 00:00:14) [common]
363 23:45:58.818599 start: 2.2.3 depthcharge-start (timeout 00:04:46) [common]
364 23:45:58.818724 Setting prompt string to 'Starting depthcharge on Spherion...'
365 23:45:58.818829 Changing prompt to 'Starting depthcharge on Spherion...'
366 23:45:58.818934 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
367 23:45:58.819529 [Enter `^Ec?' for help]
368 23:45:58.819645
369 23:45:58.819745
370 23:45:58.819843 F0: 102B 0000
371 23:45:58.819941
372 23:45:58.820031 F3: 1001 0000 [0200]
373 23:45:58.820127
374 23:45:58.820213 F3: 1001 0000
375 23:45:58.820302
376 23:45:58.820373 F7: 102D 0000
377 23:45:58.820430
378 23:45:58.820485 F1: 0000 0000
379 23:45:58.820550
380 23:45:58.820607 V0: 0000 0000 [0001]
381 23:45:58.820661
382 23:45:58.820724 00: 0007 8000
383 23:45:58.820815
384 23:45:58.820899 01: 0000 0000
385 23:45:58.820990
386 23:45:58.821075 BP: 0C00 0209 [0000]
387 23:45:58.821165
388 23:45:58.821254 G0: 1182 0000
389 23:45:58.821322
390 23:45:58.821377 EC: 0000 0021 [4000]
391 23:45:58.821431
392 23:45:58.821503 S7: 0000 0000 [0000]
393 23:45:58.821558
394 23:45:58.821612 CC: 0000 0000 [0001]
395 23:45:58.821666
396 23:45:58.821755 T0: 0000 0040 [010F]
397 23:45:58.821842
398 23:45:58.821934 Jump to BL
399 23:45:58.822018
400 23:45:58.822100
401 23:45:58.822192
402 23:45:58.822278 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
403 23:45:58.822379 ARM64: Exception handlers installed.
404 23:45:58.822464 ARM64: Testing exception
405 23:45:58.822548 ARM64: Done test exception
406 23:45:58.822643 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
407 23:45:58.822730 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
408 23:45:58.822822 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
409 23:45:58.822910 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
410 23:45:58.822996 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
411 23:45:58.823092 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
412 23:45:58.823178 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
413 23:45:58.823267 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
414 23:45:58.823359 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
415 23:45:58.823444 WDT: Last reset was cold boot
416 23:45:58.823534 SPI1(PAD0) initialized at 2873684 Hz
417 23:45:58.823620 SPI5(PAD0) initialized at 992727 Hz
418 23:45:58.823677 VBOOT: Loading verstage.
419 23:45:58.823732 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
420 23:45:58.823796 FMAP: Found "FLASH" version 1.1 at 0x20000.
421 23:45:58.823856 FMAP: base = 0x0 size = 0x800000 #areas = 25
422 23:45:58.823945 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
423 23:45:58.824033 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
424 23:45:58.824125 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
425 23:45:58.824210 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
426 23:45:58.824303
427 23:45:58.824388
428 23:45:58.824474 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
429 23:45:58.824567 ARM64: Exception handlers installed.
430 23:45:58.824631 ARM64: Testing exception
431 23:45:58.824685 ARM64: Done test exception
432 23:45:58.824739 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
433 23:45:58.824808 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
434 23:45:58.824863 Probing TPM: . done!
435 23:45:58.824917 TPM ready after 0 ms
436 23:45:58.824985 Connected to device vid:did:rid of 1ae0:0028:00
437 23:45:58.825054 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
438 23:45:58.825109 Initialized TPM device CR50 revision 0
439 23:45:58.825164 tlcl_send_startup: Startup return code is 0
440 23:45:58.825229 TPM: setup succeeded
441 23:45:58.825334 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
442 23:45:58.825396 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
443 23:45:58.825458 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
444 23:45:58.825513 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:45:58.825567 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
446 23:45:58.825621 in-header: 03 07 00 00 08 00 00 00
447 23:45:58.825691 in-data: aa e4 47 04 13 02 00 00
448 23:45:58.825753 Chrome EC: UHEPI supported
449 23:45:58.825812 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
450 23:45:58.825867 in-header: 03 a9 00 00 08 00 00 00
451 23:45:58.825932 in-data: 84 60 60 08 00 00 00 00
452 23:45:58.825986 Phase 1
453 23:45:58.826039 FMAP: area GBB found @ 3f5000 (12032 bytes)
454 23:45:58.826103 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
455 23:45:58.826176 VB2:vb2_check_recovery() Recovery was requested manually
456 23:45:58.826246 VB2:vb2_check_recovery() We have a recovery request: 0x2 / 0x7
457 23:45:58.826319 Recovery requested (1009000e)
458 23:45:58.826375 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 23:45:58.826429 tlcl_extend: response is 0
460 23:45:58.826494 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 23:45:58.826564 tlcl_extend: response is 0
462 23:45:58.826619 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 23:45:58.826674 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 23:45:58.826740 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 23:45:58.826804
466 23:45:58.826860
467 23:45:58.826915 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 23:45:58.826969 ARM64: Exception handlers installed.
469 23:45:58.827037 ARM64: Testing exception
470 23:45:58.827092 ARM64: Done test exception
471 23:45:58.827145 pmic_efuse_setting: Set efuses in 11 msecs
472 23:45:58.827214 pmwrap_interface_init: Select PMIF_VLD_RDY
473 23:45:58.827270 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 23:45:58.827324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 23:45:58.827572 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 23:45:58.827698 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 23:45:58.827757 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 23:45:58.827829 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 23:45:58.827886 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 23:45:58.827941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 23:45:58.828011 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 23:45:58.828068 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 23:45:58.828135 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 23:45:58.828212 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 23:45:58.828273 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 23:45:58.828360 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 23:45:58.828424 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 23:45:58.828481 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 23:45:58.828550 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 23:45:58.828606 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 23:45:58.828660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 23:45:58.828728 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 23:45:58.828797 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 23:45:58.828852 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 23:45:58.828907 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 23:45:58.828975 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 23:45:58.829039 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 23:45:58.829096 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 23:45:58.829151 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 23:45:58.829215 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 23:45:58.829322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 23:45:58.829378 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 23:45:58.829470 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 23:45:58.829545 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 23:45:58.829600 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 23:45:58.829661 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 23:45:58.829721 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 23:45:58.829789 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 23:45:58.829844 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 23:45:58.829898 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 23:45:58.829967 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 23:45:58.830022 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 23:45:58.830076 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 23:45:58.830141 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 23:45:58.830206 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 23:45:58.830262 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 23:45:58.830315 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 23:45:58.830374 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 23:45:58.830439 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 23:45:58.830493 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 23:45:58.830548 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 23:45:58.830617 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 23:45:58.830672 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 23:45:58.830725 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x6b6d 0x5bf0 0x8100 0x4c 0xf0f 0x9248
525 23:45:58.830780 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 23:45:58.830847 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 23:45:58.830904 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 23:45:58.830969 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 23:45:58.831026 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 23:45:58.831096 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 23:45:58.831152 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:45:58.831206 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
533 23:45:58.831259 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 23:45:58.831332 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
535 23:45:58.831389 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 23:45:58.831443 [RTC]rtc_get_frequency_meter,154: input=15, output=852
537 23:45:58.831497 [RTC]rtc_get_frequency_meter,154: input=7, output=725
538 23:45:58.831567 [RTC]rtc_get_frequency_meter,154: input=11, output=789
539 23:45:58.831622 [RTC]rtc_get_frequency_meter,154: input=13, output=821
540 23:45:58.831676 [RTC]rtc_get_frequency_meter,154: input=12, output=804
541 23:45:58.831736 [RTC]rtc_get_frequency_meter,154: input=11, output=788
542 23:45:58.831799 [RTC]rtc_get_frequency_meter,154: input=12, output=805
543 23:45:58.831853 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
544 23:45:58.831907 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
545 23:45:58.832157 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 23:45:58.832257 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
547 23:45:58.832417 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 23:45:58.832511 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
549 23:45:58.832596 ADC[4]: Raw value=903325 ID=7
550 23:45:58.832690 ADC[3]: Raw value=213916 ID=1
551 23:45:58.832774 RAM Code: 0x71
552 23:45:58.832860 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 23:45:58.832986 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 23:45:58.833072 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
555 23:45:58.833165 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
556 23:45:58.833278 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 23:45:58.833350 in-header: 03 07 00 00 08 00 00 00
558 23:45:58.833420 in-data: aa e4 47 04 13 02 00 00
559 23:45:58.833475 Chrome EC: UHEPI supported
560 23:45:58.833529 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 23:45:58.833598 in-header: 03 a9 00 00 08 00 00 00
562 23:45:58.833671 in-data: 84 60 60 08 00 00 00 00
563 23:45:58.833726 MRC: failed to locate region type 0.
564 23:45:58.833780 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 23:45:58.833844 DRAM-K: Running full calibration
566 23:45:58.833900 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
567 23:45:58.833971 header.status = 0x0
568 23:45:58.834025 header.version = 0x6 (expected: 0x6)
569 23:45:58.834078 header.size = 0xd00 (expected: 0xd00)
570 23:45:58.834149 header.flags = 0x0
571 23:45:58.834203 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 23:45:58.834258 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
573 23:45:58.834326 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 23:45:58.834448 dram_init: ddr_geometry: 2
575 23:45:58.834524 [EMI] MDL number = 2
576 23:45:58.834652 [EMI] Get MDL freq = 0
577 23:45:58.834736 dram_init: ddr_type: 0
578 23:45:58.834820 is_discrete_lpddr4: 1
579 23:45:58.834911 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 23:45:58.834994
581 23:45:58.835087
582 23:45:58.835170 [Bian_co] ETT version 0.0.0.1
583 23:45:58.835255 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
584 23:45:58.835348
585 23:45:58.835440 dramc_set_vcore_voltage set vcore to 650000
586 23:45:58.835531 Read voltage for 800, 4
587 23:45:58.835615 Vio18 = 0
588 23:45:58.835699 Vcore = 650000
589 23:45:58.835788 Vdram = 0
590 23:45:58.835871 Vddq = 0
591 23:45:58.835961 Vmddr = 0
592 23:45:58.836044 dram_init: config_dvfs: 1
593 23:45:58.836141 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 23:45:58.836230 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 23:45:58.836315 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 23:45:58.836406 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 23:45:58.836499 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 23:45:58.836583 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 23:45:58.836674 MEM_TYPE=3, freq_sel=18
600 23:45:58.836758 sv_algorithm_assistance_LP4_1600
601 23:45:58.836851 ============ PULL DRAM RESETB DOWN ============
602 23:45:58.836947 ========== PULL DRAM RESETB DOWN end =========
603 23:45:58.837032 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 23:45:58.837124 ===================================
605 23:45:58.837216 LPDDR4 DRAM CONFIGURATION
606 23:45:58.837338 ===================================
607 23:45:58.837429 EX_ROW_EN[0] = 0x0
608 23:45:58.837513 EX_ROW_EN[1] = 0x0
609 23:45:58.837600 LP4Y_EN = 0x0
610 23:45:58.837689 WORK_FSP = 0x0
611 23:45:58.837773 WL = 0x2
612 23:45:58.837864 RL = 0x2
613 23:45:58.837955 BL = 0x2
614 23:45:58.838038 RPST = 0x0
615 23:45:58.838129 RD_PRE = 0x0
616 23:45:58.838220 WR_PRE = 0x1
617 23:45:58.838304 WR_PST = 0x0
618 23:45:58.838398 DBI_WR = 0x0
619 23:45:58.838488 DBI_RD = 0x0
620 23:45:58.838580 OTF = 0x1
621 23:45:58.838673 ===================================
622 23:45:58.838757 ===================================
623 23:45:58.838849 ANA top config
624 23:45:58.838940 ===================================
625 23:45:58.839024 DLL_ASYNC_EN = 0
626 23:45:58.839115 ALL_SLAVE_EN = 1
627 23:45:58.839199 NEW_RANK_MODE = 1
628 23:45:58.839291 DLL_IDLE_MODE = 1
629 23:45:58.839385 LP45_APHY_COMB_EN = 1
630 23:45:58.839469 TX_ODT_DIS = 1
631 23:45:58.839550 NEW_8X_MODE = 1
632 23:45:58.839605 ===================================
633 23:45:58.839659 ===================================
634 23:45:58.839741 data_rate = 1600
635 23:45:58.839833 CKR = 1
636 23:45:58.839917 DQ_P2S_RATIO = 8
637 23:45:58.840009 ===================================
638 23:45:58.840101 CA_P2S_RATIO = 8
639 23:45:58.840185 DQ_CA_OPEN = 0
640 23:45:58.840275 DQ_SEMI_OPEN = 0
641 23:45:58.840373 CA_SEMI_OPEN = 0
642 23:45:58.840458 CA_FULL_RATE = 0
643 23:45:58.840551 DQ_CKDIV4_EN = 1
644 23:45:58.840634 CA_CKDIV4_EN = 1
645 23:45:58.840724 CA_PREDIV_EN = 0
646 23:45:58.840817 PH8_DLY = 0
647 23:45:58.840901 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 23:45:58.840993 DQ_AAMCK_DIV = 4
649 23:45:58.841079 CA_AAMCK_DIV = 4
650 23:45:58.841171 CA_ADMCK_DIV = 4
651 23:45:58.841281 DQ_TRACK_CA_EN = 0
652 23:45:58.841380 CA_PICK = 800
653 23:45:58.841475 CA_MCKIO = 800
654 23:45:58.841564 MCKIO_SEMI = 0
655 23:45:58.841657 PLL_FREQ = 3068
656 23:45:58.841741 DQ_UI_PI_RATIO = 32
657 23:45:58.841825 CA_UI_PI_RATIO = 0
658 23:45:58.841919 ===================================
659 23:45:58.842004 ===================================
660 23:45:58.842088 memory_type:LPDDR4
661 23:45:58.842171 GP_NUM : 10
662 23:45:58.842255 SRAM_EN : 1
663 23:45:58.842349 MD32_EN : 0
664 23:45:58.842656 ===================================
665 23:45:58.842722 [ANA_INIT] >>>>>>>>>>>>>>
666 23:45:58.842800 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 23:45:58.842859 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 23:45:58.842914 ===================================
669 23:45:58.843000 data_rate = 1600,PCW = 0X7600
670 23:45:58.843058 ===================================
671 23:45:58.843112 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 23:45:58.843167 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 23:45:58.843246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:45:58.843310 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 23:45:58.843366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 23:45:58.843419 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:45:58.843493 [ANA_INIT] flow start
678 23:45:58.843548 [ANA_INIT] PLL >>>>>>>>
679 23:45:58.843602 [ANA_INIT] PLL <<<<<<<<
680 23:45:58.843679 [ANA_INIT] MIDPI >>>>>>>>
681 23:45:58.843735 [ANA_INIT] MIDPI <<<<<<<<
682 23:45:58.843789 [ANA_INIT] DLL >>>>>>>>
683 23:45:58.843843 [ANA_INIT] flow end
684 23:45:58.843917 ============ LP4 DIFF to SE enter ============
685 23:45:58.843986 ============ LP4 DIFF to SE exit ============
686 23:45:58.844044 [ANA_INIT] <<<<<<<<<<<<<
687 23:45:58.844098 [Flow] Enable top DCM control >>>>>
688 23:45:58.844169 [Flow] Enable top DCM control <<<<<
689 23:45:58.844223 Enable DLL master slave shuffle
690 23:45:58.844277 ==============================================================
691 23:45:58.844349 Gating Mode config
692 23:45:58.844405 ==============================================================
693 23:45:58.844459 Config description:
694 23:45:58.844534 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 23:45:58.844592 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 23:45:58.844646 SELPH_MODE 0: By rank 1: By Phase
697 23:45:58.844713 ==============================================================
698 23:45:58.844808 GAT_TRACK_EN = 1
699 23:45:58.844892 RX_GATING_MODE = 2
700 23:45:58.844985 RX_GATING_TRACK_MODE = 2
701 23:45:58.845078 SELPH_MODE = 1
702 23:45:58.845162 PICG_EARLY_EN = 1
703 23:45:58.845264 VALID_LAT_VALUE = 1
704 23:45:58.845355 ==============================================================
705 23:45:58.845420 Enter into Gating configuration >>>>
706 23:45:58.845495 Exit from Gating configuration <<<<
707 23:45:58.845552 Enter into DVFS_PRE_config >>>>>
708 23:45:58.845606 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 23:45:58.845677 Exit from DVFS_PRE_config <<<<<
710 23:45:58.845743 Enter into PICG configuration >>>>
711 23:45:58.845802 Exit from PICG configuration <<<<
712 23:45:58.845856 [RX_INPUT] configuration >>>>>
713 23:45:58.845909 [RX_INPUT] configuration <<<<<
714 23:45:58.845982 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 23:45:58.846037 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 23:45:58.846091 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 23:45:58.846166 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 23:45:58.846240 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 23:45:58.846295 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 23:45:58.846350 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 23:45:58.846427 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 23:45:58.846483 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 23:45:58.846537 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 23:45:58.846615 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 23:45:58.846670 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 23:45:58.846724 ===================================
727 23:45:58.846778 LPDDR4 DRAM CONFIGURATION
728 23:45:58.846848 ===================================
729 23:45:58.846904 EX_ROW_EN[0] = 0x0
730 23:45:58.846972 EX_ROW_EN[1] = 0x0
731 23:45:58.847028 LP4Y_EN = 0x0
732 23:45:58.847101 WORK_FSP = 0x0
733 23:45:58.847155 WL = 0x2
734 23:45:58.847209 RL = 0x2
735 23:45:58.847262 BL = 0x2
736 23:45:58.847340 RPST = 0x0
737 23:45:58.847395 RD_PRE = 0x0
738 23:45:58.847448 WR_PRE = 0x1
739 23:45:58.847501 WR_PST = 0x0
740 23:45:58.847580 DBI_WR = 0x0
741 23:45:58.847635 DBI_RD = 0x0
742 23:45:58.847689 OTF = 0x1
743 23:45:58.847757 ===================================
744 23:45:58.847813 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 23:45:58.847868 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 23:45:58.847922 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 23:45:58.847988 ===================================
748 23:45:58.848049 LPDDR4 DRAM CONFIGURATION
749 23:45:58.848103 ===================================
750 23:45:58.848167 EX_ROW_EN[0] = 0x10
751 23:45:58.848245 EX_ROW_EN[1] = 0x0
752 23:45:58.848300 LP4Y_EN = 0x0
753 23:45:58.848354 WORK_FSP = 0x0
754 23:45:58.848422 WL = 0x2
755 23:45:58.848487 RL = 0x2
756 23:45:58.848546 BL = 0x2
757 23:45:58.848599 RPST = 0x0
758 23:45:58.848664 RD_PRE = 0x0
759 23:45:58.848725 WR_PRE = 0x1
760 23:45:58.848779 WR_PST = 0x0
761 23:45:58.848833 DBI_WR = 0x0
762 23:45:58.848910 DBI_RD = 0x0
763 23:45:58.848976 OTF = 0x1
764 23:45:58.849031 ===================================
765 23:45:58.849085 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 23:45:58.849183 nWR fixed to 40
767 23:45:58.849295 [ModeRegInit_LP4] CH0 RK0
768 23:45:58.849373 [ModeRegInit_LP4] CH0 RK1
769 23:45:58.849445 [ModeRegInit_LP4] CH1 RK0
770 23:45:58.849504 [ModeRegInit_LP4] CH1 RK1
771 23:45:58.849558 match AC timing 13
772 23:45:58.849612 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
773 23:45:58.849888 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 23:45:58.850011 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 23:45:58.850069 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 23:45:58.850173 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 23:45:58.850231 [EMI DOE] emi_dcm 0
778 23:45:58.850285 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 23:45:58.850350 ==
780 23:45:58.850422 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:45:58.850480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:45:58.850535 ==
783 23:45:58.850589 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 23:45:58.850664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 23:45:58.850719 [CA 0] Center 37 (7~68) winsize 62
786 23:45:58.850774 [CA 1] Center 37 (6~68) winsize 63
787 23:45:58.850857 [CA 2] Center 34 (4~65) winsize 62
788 23:45:58.850920 [CA 3] Center 35 (4~66) winsize 63
789 23:45:58.850974 [CA 4] Center 33 (3~64) winsize 62
790 23:45:58.851028 [CA 5] Center 33 (3~64) winsize 62
791 23:45:58.851108
792 23:45:58.851163 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 23:45:58.851218
794 23:45:58.851295 [CATrainingPosCal] consider 1 rank data
795 23:45:58.851350 u2DelayCellTimex100 = 270/100 ps
796 23:45:58.851404 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
797 23:45:58.851458 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
798 23:45:58.851532 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
799 23:45:58.851595 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
800 23:45:58.851659 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
801 23:45:58.851717 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 23:45:58.851783
803 23:45:58.851838 CA PerBit enable=1, Macro0, CA PI delay=33
804 23:45:58.851892
805 23:45:58.851965 [CBTSetCACLKResult] CA Dly = 33
806 23:45:58.852021 CS Dly: 5 (0~36)
807 23:45:58.852107 ==
808 23:45:58.852179 Dram Type= 6, Freq= 0, CH_0, rank 1
809 23:45:58.852233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
810 23:45:58.852288 ==
811 23:45:58.852412 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 23:45:58.852468 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 23:45:58.852523 [CA 0] Center 38 (7~69) winsize 63
814 23:45:58.852598 [CA 1] Center 37 (7~68) winsize 62
815 23:45:58.852672 [CA 2] Center 35 (4~66) winsize 63
816 23:45:58.852728 [CA 3] Center 34 (4~65) winsize 62
817 23:45:58.852781 [CA 4] Center 34 (3~65) winsize 63
818 23:45:58.852849 [CA 5] Center 33 (3~64) winsize 62
819 23:45:58.852934
820 23:45:58.853020 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 23:45:58.853121
822 23:45:58.853205 [CATrainingPosCal] consider 2 rank data
823 23:45:58.853334 u2DelayCellTimex100 = 270/100 ps
824 23:45:58.853392 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
825 23:45:58.853446 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 23:45:58.853522 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
827 23:45:58.853577 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
828 23:45:58.853631 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
829 23:45:58.853685 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 23:45:58.853738
831 23:45:58.853817 CA PerBit enable=1, Macro0, CA PI delay=33
832 23:45:58.853890
833 23:45:58.853945 [CBTSetCACLKResult] CA Dly = 33
834 23:45:58.854021 CS Dly: 6 (0~38)
835 23:45:58.854077
836 23:45:58.854131 ----->DramcWriteLeveling(PI) begin...
837 23:45:58.854208 ==
838 23:45:58.854264 Dram Type= 6, Freq= 0, CH_0, rank 0
839 23:45:58.854319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
840 23:45:58.854399 ==
841 23:45:58.854454 Write leveling (Byte 0): 32 => 32
842 23:45:58.854508 Write leveling (Byte 1): 28 => 28
843 23:45:58.854576 DramcWriteLeveling(PI) end<-----
844 23:45:58.854654
845 23:45:58.854709 ==
846 23:45:58.854762 Dram Type= 6, Freq= 0, CH_0, rank 0
847 23:45:58.854837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
848 23:45:58.854913 ==
849 23:45:58.854970 [Gating] SW mode calibration
850 23:45:58.855024 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 23:45:58.855104 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 23:45:58.855159 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
853 23:45:58.855214 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
854 23:45:58.855284 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 23:45:58.855362 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:45:58.855418 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:45:58.855472 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:45:58.855549 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:45:58.855655 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:45:58.855711 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:45:58.855766 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:45:58.855841 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:45:58.855896 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:45:58.855950 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:45:58.856036 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:45:58.856100 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:45:58.856154 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:45:58.856208 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:45:58.856285 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 23:45:58.856340 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
871 23:45:58.856394 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 23:45:58.856475 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:45:58.856531 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:45:58.856584 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:45:58.856637 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:45:58.856692 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:45:58.856776 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:45:58.856842 0 9 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
879 23:45:58.856897 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
880 23:45:58.856990 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 23:45:58.857299 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:45:58.857399 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:45:58.857457 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:45:58.857527 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:45:58.857608 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
886 23:45:58.857664 0 10 8 | B1->B0 | 3232 2626 | 1 0 | (1 0) (1 1)
887 23:45:58.857719 0 10 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
888 23:45:58.857840 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 23:45:58.857900 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:45:58.857955 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:45:58.858023 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:45:58.858084 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:45:58.858138 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
894 23:45:58.858192 0 11 8 | B1->B0 | 2929 4040 | 1 0 | (0 0) (1 1)
895 23:45:58.858277 0 11 12 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
896 23:45:58.858339 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 23:45:58.858394 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:45:58.858452 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:45:58.858520 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:45:58.858596 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:45:58.858651 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
902 23:45:58.858705 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 23:45:58.858783 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 23:45:58.858838 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:45:58.858892 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:45:58.858979 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:45:58.859045 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:45:58.859099 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:45:58.859153 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:45:58.859232 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:45:58.859288 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:45:58.859348 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:45:58.859425 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:45:58.859480 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:45:58.859534 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:45:58.859587 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:45:58.859644 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:45:58.859725 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
919 23:45:58.859791 Total UI for P1: 0, mck2ui 16
920 23:45:58.859847 best dqsien dly found for B0: ( 0, 14, 6)
921 23:45:58.859923 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
922 23:45:58.859978 Total UI for P1: 0, mck2ui 16
923 23:45:58.860032 best dqsien dly found for B1: ( 0, 14, 8)
924 23:45:58.860108 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
925 23:45:58.860164 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
926 23:45:58.860219
927 23:45:58.860296 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
928 23:45:58.860352 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 23:45:58.860406 [Gating] SW calibration Done
930 23:45:58.860476 ==
931 23:45:58.860555 Dram Type= 6, Freq= 0, CH_0, rank 0
932 23:45:58.860610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
933 23:45:58.860665 ==
934 23:45:58.860754 RX Vref Scan: 0
935 23:45:58.860848
936 23:45:58.860940 RX Vref 0 -> 0, step: 1
937 23:45:58.861035
938 23:45:58.861119 RX Delay -130 -> 252, step: 16
939 23:45:58.861219 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
940 23:45:58.861335 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
941 23:45:58.861391 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
942 23:45:58.861468 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
943 23:45:58.861546 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
944 23:45:58.861600 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
945 23:45:58.861654 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
946 23:45:58.861732 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
947 23:45:58.861787 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
948 23:45:58.861840 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
949 23:45:58.861919 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
950 23:45:58.861997 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
951 23:45:58.862053 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
952 23:45:58.862106 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
953 23:45:58.862188 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
954 23:45:58.862244 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
955 23:45:58.862300 ==
956 23:45:58.862375 Dram Type= 6, Freq= 0, CH_0, rank 0
957 23:45:58.862430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
958 23:45:58.862484 ==
959 23:45:58.862538 DQS Delay:
960 23:45:58.862618 DQS0 = 0, DQS1 = 0
961 23:45:58.862674 DQM Delay:
962 23:45:58.862751 DQM0 = 88, DQM1 = 76
963 23:45:58.862825 DQ Delay:
964 23:45:58.862880 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
965 23:45:58.862935 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
966 23:45:58.862989 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
967 23:45:58.863053 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
968 23:45:58.863118
969 23:45:58.863172
970 23:45:58.863225 ==
971 23:45:58.863278 Dram Type= 6, Freq= 0, CH_0, rank 0
972 23:45:58.863332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
973 23:45:58.863386 ==
974 23:45:58.863439
975 23:45:58.863507
976 23:45:58.863573 TX Vref Scan disable
977 23:45:58.863640 == TX Byte 0 ==
978 23:45:58.863694 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
979 23:45:58.863749 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
980 23:45:58.863842 == TX Byte 1 ==
981 23:45:58.863899 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
982 23:45:58.863953 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
983 23:45:58.864010 ==
984 23:45:58.864089 Dram Type= 6, Freq= 0, CH_0, rank 0
985 23:45:58.864153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 23:45:58.864208 ==
987 23:45:58.864265 TX Vref=22, minBit 5, minWin=26, winSum=437
988 23:45:58.864339 TX Vref=24, minBit 1, minWin=27, winSum=445
989 23:45:58.864619 TX Vref=26, minBit 1, minWin=27, winSum=446
990 23:45:58.864682 TX Vref=28, minBit 1, minWin=27, winSum=452
991 23:45:58.864774 TX Vref=30, minBit 5, minWin=27, winSum=453
992 23:45:58.864872 TX Vref=32, minBit 1, minWin=27, winSum=449
993 23:45:58.864958 [TxChooseVref] Worse bit 5, Min win 27, Win sum 453, Final Vref 30
994 23:45:58.865054
995 23:45:58.865149 Final TX Range 1 Vref 30
996 23:45:58.865233
997 23:45:58.865367 ==
998 23:45:58.865456 Dram Type= 6, Freq= 0, CH_0, rank 0
999 23:45:58.865560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1000 23:45:58.865645 ==
1001 23:45:58.865737
1002 23:45:58.865821
1003 23:45:58.865910 TX Vref Scan disable
1004 23:45:58.866000 == TX Byte 0 ==
1005 23:45:58.866083 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1006 23:45:58.866167 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1007 23:45:58.866270 == TX Byte 1 ==
1008 23:45:58.866358 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1009 23:45:58.866453 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1010 23:45:58.866536
1011 23:45:58.866629 [DATLAT]
1012 23:45:58.866714 Freq=800, CH0 RK0
1013 23:45:58.866805
1014 23:45:58.866894 DATLAT Default: 0xa
1015 23:45:58.866981 0, 0xFFFF, sum = 0
1016 23:45:58.867084 1, 0xFFFF, sum = 0
1017 23:45:58.867170 2, 0xFFFF, sum = 0
1018 23:45:58.867266 3, 0xFFFF, sum = 0
1019 23:45:58.867363 4, 0xFFFF, sum = 0
1020 23:45:58.867448 5, 0xFFFF, sum = 0
1021 23:45:58.867546 6, 0xFFFF, sum = 0
1022 23:45:58.867632 7, 0xFFFF, sum = 0
1023 23:45:58.867728 8, 0xFFFF, sum = 0
1024 23:45:58.867825 9, 0x0, sum = 1
1025 23:45:58.867917 10, 0x0, sum = 2
1026 23:45:58.868017 11, 0x0, sum = 3
1027 23:45:58.868110 12, 0x0, sum = 4
1028 23:45:58.868195 best_step = 10
1029 23:45:58.868289
1030 23:45:58.868374 ==
1031 23:45:58.868475 Dram Type= 6, Freq= 0, CH_0, rank 0
1032 23:45:58.868563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1033 23:45:58.868646 ==
1034 23:45:58.868739 RX Vref Scan: 1
1035 23:45:58.868820
1036 23:45:58.868961 Set Vref Range= 32 -> 127
1037 23:45:58.869045
1038 23:45:58.869129 RX Vref 32 -> 127, step: 1
1039 23:45:58.869226
1040 23:45:58.869336 RX Delay -95 -> 252, step: 8
1041 23:45:58.869391
1042 23:45:58.869471 Set Vref, RX VrefLevel [Byte0]: 32
1043 23:45:58.869525 [Byte1]: 32
1044 23:45:58.869579
1045 23:45:58.869663 Set Vref, RX VrefLevel [Byte0]: 33
1046 23:45:58.869717 [Byte1]: 33
1047 23:45:58.869769
1048 23:45:58.869822 Set Vref, RX VrefLevel [Byte0]: 34
1049 23:45:58.869902 [Byte1]: 34
1050 23:45:58.869980
1051 23:45:58.870036 Set Vref, RX VrefLevel [Byte0]: 35
1052 23:45:58.870110 [Byte1]: 35
1053 23:45:58.870165
1054 23:45:58.870219 Set Vref, RX VrefLevel [Byte0]: 36
1055 23:45:58.870276 [Byte1]: 36
1056 23:45:58.870348
1057 23:45:58.870402 Set Vref, RX VrefLevel [Byte0]: 37
1058 23:45:58.870455 [Byte1]: 37
1059 23:45:58.870537
1060 23:45:58.870591 Set Vref, RX VrefLevel [Byte0]: 38
1061 23:45:58.870644 [Byte1]: 38
1062 23:45:58.870745
1063 23:45:58.870802 Set Vref, RX VrefLevel [Byte0]: 39
1064 23:45:58.870855 [Byte1]: 39
1065 23:45:58.870911
1066 23:45:58.870990 Set Vref, RX VrefLevel [Byte0]: 40
1067 23:45:58.871058 [Byte1]: 40
1068 23:45:58.871112
1069 23:45:58.871173 Set Vref, RX VrefLevel [Byte0]: 41
1070 23:45:58.871242 [Byte1]: 41
1071 23:45:58.871296
1072 23:45:58.871348 Set Vref, RX VrefLevel [Byte0]: 42
1073 23:45:58.871437 [Byte1]: 42
1074 23:45:58.871503
1075 23:45:58.871556 Set Vref, RX VrefLevel [Byte0]: 43
1076 23:45:58.871610 [Byte1]: 43
1077 23:45:58.871688
1078 23:45:58.871764 Set Vref, RX VrefLevel [Byte0]: 44
1079 23:45:58.871818 [Byte1]: 44
1080 23:45:58.871872
1081 23:45:58.871965 Set Vref, RX VrefLevel [Byte0]: 45
1082 23:45:58.872048 [Byte1]: 45
1083 23:45:58.872137
1084 23:45:58.872214 Set Vref, RX VrefLevel [Byte0]: 46
1085 23:45:58.872268 [Byte1]: 46
1086 23:45:58.872321
1087 23:45:58.872403 Set Vref, RX VrefLevel [Byte0]: 47
1088 23:45:58.872457 [Byte1]: 47
1089 23:45:58.872511
1090 23:45:58.872591 Set Vref, RX VrefLevel [Byte0]: 48
1091 23:45:58.872645 [Byte1]: 48
1092 23:45:58.872698
1093 23:45:58.872750 Set Vref, RX VrefLevel [Byte0]: 49
1094 23:45:58.872830 [Byte1]: 49
1095 23:45:58.872886
1096 23:45:58.872956 Set Vref, RX VrefLevel [Byte0]: 50
1097 23:45:58.873025 [Byte1]: 50
1098 23:45:58.873086
1099 23:45:58.873139 Set Vref, RX VrefLevel [Byte0]: 51
1100 23:45:58.873191 [Byte1]: 51
1101 23:45:58.873246
1102 23:45:58.873362 Set Vref, RX VrefLevel [Byte0]: 52
1103 23:45:58.873417 [Byte1]: 52
1104 23:45:58.873470
1105 23:45:58.873522 Set Vref, RX VrefLevel [Byte0]: 53
1106 23:45:58.873575 [Byte1]: 53
1107 23:45:58.873628
1108 23:45:58.873680 Set Vref, RX VrefLevel [Byte0]: 54
1109 23:45:58.873764 [Byte1]: 54
1110 23:45:58.873845
1111 23:45:58.873898 Set Vref, RX VrefLevel [Byte0]: 55
1112 23:45:58.873951 [Byte1]: 55
1113 23:45:58.874042
1114 23:45:58.874104 Set Vref, RX VrefLevel [Byte0]: 56
1115 23:45:58.874157 [Byte1]: 56
1116 23:45:58.874216
1117 23:45:58.874318 Set Vref, RX VrefLevel [Byte0]: 57
1118 23:45:58.874402 [Byte1]: 57
1119 23:45:58.874489
1120 23:45:58.874590 Set Vref, RX VrefLevel [Byte0]: 58
1121 23:45:58.874673 [Byte1]: 58
1122 23:45:58.874767
1123 23:45:58.874851 Set Vref, RX VrefLevel [Byte0]: 59
1124 23:45:58.874935 [Byte1]: 59
1125 23:45:58.875105
1126 23:45:58.875193 Set Vref, RX VrefLevel [Byte0]: 60
1127 23:45:58.875291 [Byte1]: 60
1128 23:45:58.875374
1129 23:45:58.875460 Set Vref, RX VrefLevel [Byte0]: 61
1130 23:45:58.875550 [Byte1]: 61
1131 23:45:58.875633
1132 23:45:58.875732 Set Vref, RX VrefLevel [Byte0]: 62
1133 23:45:58.875819 [Byte1]: 62
1134 23:45:58.875902
1135 23:45:58.875995 Set Vref, RX VrefLevel [Byte0]: 63
1136 23:45:58.876079 [Byte1]: 63
1137 23:45:58.876173
1138 23:45:58.876255 Set Vref, RX VrefLevel [Byte0]: 64
1139 23:45:58.876340 [Byte1]: 64
1140 23:45:58.876433
1141 23:45:58.876526 Set Vref, RX VrefLevel [Byte0]: 65
1142 23:45:58.876622 [Byte1]: 65
1143 23:45:58.876704
1144 23:45:58.876786 Set Vref, RX VrefLevel [Byte0]: 66
1145 23:45:58.876882 [Byte1]: 66
1146 23:45:58.876977
1147 23:45:58.877060 Set Vref, RX VrefLevel [Byte0]: 67
1148 23:45:58.877146 [Byte1]: 67
1149 23:45:58.877246
1150 23:45:58.877345 Set Vref, RX VrefLevel [Byte0]: 68
1151 23:45:58.877429 [Byte1]: 68
1152 23:45:58.877505
1153 23:45:58.877559 Set Vref, RX VrefLevel [Byte0]: 69
1154 23:45:58.877613 [Byte1]: 69
1155 23:45:58.877694
1156 23:45:58.877768 Set Vref, RX VrefLevel [Byte0]: 70
1157 23:45:58.878017 [Byte1]: 70
1158 23:45:58.878081
1159 23:45:58.878162 Set Vref, RX VrefLevel [Byte0]: 71
1160 23:45:58.878233 [Byte1]: 71
1161 23:45:58.878288
1162 23:45:58.878347 Final RX Vref Byte 0 = 55 to rank0
1163 23:45:58.878441 Final RX Vref Byte 1 = 60 to rank0
1164 23:45:58.878566 Final RX Vref Byte 0 = 55 to rank1
1165 23:45:58.878675 Final RX Vref Byte 1 = 60 to rank1==
1166 23:45:58.878758 Dram Type= 6, Freq= 0, CH_0, rank 0
1167 23:45:58.878854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1168 23:45:58.878950 ==
1169 23:45:58.879033 DQS Delay:
1170 23:45:58.879130 DQS0 = 0, DQS1 = 0
1171 23:45:58.879212 DQM Delay:
1172 23:45:58.879309 DQM0 = 88, DQM1 = 76
1173 23:45:58.879401 DQ Delay:
1174 23:45:58.879483 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1175 23:45:58.879581 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1176 23:45:58.879672 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1177 23:45:58.879755 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1178 23:45:58.879849
1179 23:45:58.879930
1180 23:45:58.880034 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e27, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
1181 23:45:58.880124 CH0 RK0: MR19=606, MR18=2E27
1182 23:45:58.880208 CH0_RK0: MR19=0x606, MR18=0x2E27, DQSOSC=398, MR23=63, INC=93, DEC=62
1183 23:45:58.880301
1184 23:45:58.880384 ----->DramcWriteLeveling(PI) begin...
1185 23:45:58.880482 ==
1186 23:45:58.880565 Dram Type= 6, Freq= 0, CH_0, rank 1
1187 23:45:58.880648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1188 23:45:58.880745 ==
1189 23:45:58.880841 Write leveling (Byte 0): 32 => 32
1190 23:45:58.880936 Write leveling (Byte 1): 26 => 26
1191 23:45:58.881019 DramcWriteLeveling(PI) end<-----
1192 23:45:58.881102
1193 23:45:58.881194 ==
1194 23:45:58.881306 Dram Type= 6, Freq= 0, CH_0, rank 1
1195 23:45:58.881415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1196 23:45:58.881502 ==
1197 23:45:58.881605 [Gating] SW mode calibration
1198 23:45:58.881689 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1199 23:45:58.881786 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1200 23:45:58.881883 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1201 23:45:58.881967 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1202 23:45:58.882066 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1203 23:45:58.882153 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 23:45:58.882252 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 23:45:58.882347 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 23:45:58.882430 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 23:45:58.882513 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 23:45:58.882610 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 23:45:58.882693 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1210 23:45:58.882790 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 23:45:58.882872 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 23:45:58.882970 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 23:45:58.883063 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 23:45:58.883146 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 23:45:58.883245 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 23:45:58.883328 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1217 23:45:58.883428 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1218 23:45:58.883487 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 23:45:58.883541 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 23:45:58.883595 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 23:45:58.883683 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 23:45:58.883738 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 23:45:58.883821 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 23:45:58.883903 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 23:45:58.883957 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
1226 23:45:58.884011 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
1227 23:45:58.884064 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1228 23:45:58.884151 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1229 23:45:58.884206 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1230 23:45:58.884259 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1231 23:45:58.884316 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1232 23:45:58.884396 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1233 23:45:58.884450 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
1234 23:45:58.884503 0 10 8 | B1->B0 | 3131 2323 | 1 0 | (1 0) (0 0)
1235 23:45:58.884587 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1236 23:45:58.884642 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:45:58.884695 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:45:58.884748 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:45:58.884832 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:45:58.884889 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 23:45:58.884948 0 11 4 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
1242 23:45:58.885053 0 11 8 | B1->B0 | 3030 4545 | 0 1 | (0 0) (0 0)
1243 23:45:58.885137 0 11 12 | B1->B0 | 4443 4646 | 1 0 | (0 0) (0 0)
1244 23:45:58.885234 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1245 23:45:58.885336 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1246 23:45:58.885420 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1247 23:45:58.885520 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1248 23:45:58.885603 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1249 23:45:58.885703 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1250 23:45:58.885797 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1251 23:45:58.885881 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 23:45:58.885985 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 23:45:58.886072 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 23:45:58.886158 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 23:45:58.886468 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 23:45:58.886571 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 23:45:58.886656 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1258 23:45:58.886756 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1259 23:45:58.886840 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1260 23:45:58.886941 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1261 23:45:58.887033 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 23:45:58.887117 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 23:45:58.887218 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 23:45:58.887307 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 23:45:58.887391 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1266 23:45:58.887485 Total UI for P1: 0, mck2ui 16
1267 23:45:58.887568 best dqsien dly found for B0: ( 0, 14, 2)
1268 23:45:58.887672 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1269 23:45:58.887760 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 23:45:58.887845 Total UI for P1: 0, mck2ui 16
1271 23:45:58.887941 best dqsien dly found for B1: ( 0, 14, 6)
1272 23:45:58.888027 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1273 23:45:58.888121 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1274 23:45:58.888203
1275 23:45:58.888287 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1276 23:45:58.888421 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1277 23:45:58.888511 [Gating] SW calibration Done
1278 23:45:58.888603 ==
1279 23:45:58.888686 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 23:45:58.888783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 23:45:58.888866 ==
1282 23:45:58.888963 RX Vref Scan: 0
1283 23:45:58.889056
1284 23:45:58.889138 RX Vref 0 -> 0, step: 1
1285 23:45:58.889236
1286 23:45:58.889362 RX Delay -130 -> 252, step: 16
1287 23:45:58.889457 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1288 23:45:58.889575 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1289 23:45:58.889693 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1290 23:45:58.889810 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1291 23:45:58.889925 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1292 23:45:58.890040 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1293 23:45:58.890133 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1294 23:45:58.890217 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1295 23:45:58.890307 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1296 23:45:58.890430 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1297 23:45:58.890516 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1298 23:45:58.890603 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1299 23:45:58.890686 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1300 23:45:58.890771 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1301 23:45:58.890854 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1302 23:45:58.890936 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1303 23:45:58.891025 ==
1304 23:45:58.891108 Dram Type= 6, Freq= 0, CH_0, rank 1
1305 23:45:58.891191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1306 23:45:58.891276 ==
1307 23:45:58.891361 DQS Delay:
1308 23:45:58.891443 DQS0 = 0, DQS1 = 0
1309 23:45:58.891528 DQM Delay:
1310 23:45:58.891613 DQM0 = 85, DQM1 = 75
1311 23:45:58.891695 DQ Delay:
1312 23:45:58.891782 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1313 23:45:58.891865 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1314 23:45:58.891950 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1315 23:45:58.892036 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1316 23:45:58.892117
1317 23:45:58.892198
1318 23:45:58.892282 ==
1319 23:45:58.892375 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 23:45:58.892430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 23:45:58.892515 ==
1322 23:45:58.892600
1323 23:45:58.892682
1324 23:45:58.892763 TX Vref Scan disable
1325 23:45:58.892851 == TX Byte 0 ==
1326 23:45:58.892934 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1327 23:45:58.893017 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1328 23:45:58.893105 == TX Byte 1 ==
1329 23:45:58.893193 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1330 23:45:58.893317 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1331 23:45:58.893381 ==
1332 23:45:58.893435 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 23:45:58.893488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 23:45:58.893544 ==
1335 23:45:58.893600 TX Vref=22, minBit 1, minWin=27, winSum=442
1336 23:45:58.893686 TX Vref=24, minBit 1, minWin=27, winSum=445
1337 23:45:58.893769 TX Vref=26, minBit 1, minWin=27, winSum=447
1338 23:45:58.893855 TX Vref=28, minBit 1, minWin=27, winSum=450
1339 23:45:58.893939 TX Vref=30, minBit 1, minWin=27, winSum=451
1340 23:45:58.894026 TX Vref=32, minBit 0, minWin=28, winSum=451
1341 23:45:58.894113 [TxChooseVref] Worse bit 0, Min win 28, Win sum 451, Final Vref 32
1342 23:45:58.894195
1343 23:45:58.894280 Final TX Range 1 Vref 32
1344 23:45:58.894363
1345 23:45:58.894447 ==
1346 23:45:58.894533 Dram Type= 6, Freq= 0, CH_0, rank 1
1347 23:45:58.894617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1348 23:45:58.894699 ==
1349 23:45:58.894785
1350 23:45:58.894870
1351 23:45:58.894952 TX Vref Scan disable
1352 23:45:58.895037 == TX Byte 0 ==
1353 23:45:58.895124 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1354 23:45:58.895207 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1355 23:45:58.895292 == TX Byte 1 ==
1356 23:45:58.895375 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1357 23:45:58.895460 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1358 23:45:58.895545
1359 23:45:58.895627 [DATLAT]
1360 23:45:58.895708 Freq=800, CH0 RK1
1361 23:45:58.895796
1362 23:45:58.895877 DATLAT Default: 0xa
1363 23:45:58.895963 0, 0xFFFF, sum = 0
1364 23:45:58.896047 1, 0xFFFF, sum = 0
1365 23:45:58.896130 2, 0xFFFF, sum = 0
1366 23:45:58.896219 3, 0xFFFF, sum = 0
1367 23:45:58.896304 4, 0xFFFF, sum = 0
1368 23:45:58.896378 5, 0xFFFF, sum = 0
1369 23:45:58.896452 6, 0xFFFF, sum = 0
1370 23:45:58.896505 7, 0xFFFF, sum = 0
1371 23:45:58.896558 8, 0xFFFF, sum = 0
1372 23:45:58.896611 9, 0x0, sum = 1
1373 23:45:58.896697 10, 0x0, sum = 2
1374 23:45:58.896785 11, 0x0, sum = 3
1375 23:45:58.896868 12, 0x0, sum = 4
1376 23:45:58.896955 best_step = 10
1377 23:45:58.897040
1378 23:45:58.897121 ==
1379 23:45:58.897206 Dram Type= 6, Freq= 0, CH_0, rank 1
1380 23:45:58.897329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 23:45:58.897385 ==
1382 23:45:58.897441 RX Vref Scan: 0
1383 23:45:58.897496
1384 23:45:58.897555 RX Vref 0 -> 0, step: 1
1385 23:45:58.897608
1386 23:45:58.897659 RX Delay -95 -> 252, step: 8
1387 23:45:58.897717 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1388 23:45:58.897771 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1389 23:45:58.897824 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1390 23:45:58.897877 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1391 23:45:58.898168 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1392 23:45:58.898256 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1393 23:45:58.898340 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1394 23:45:58.898429 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1395 23:45:58.898512 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1396 23:45:58.898594 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1397 23:45:58.898682 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1398 23:45:58.898765 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1399 23:45:58.898848 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1400 23:45:58.898936 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1401 23:45:58.899018 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1402 23:45:58.899105 iDelay=209, Bit 15, Center 80 (-31 ~ 192) 224
1403 23:45:58.899191 ==
1404 23:45:58.899273 Dram Type= 6, Freq= 0, CH_0, rank 1
1405 23:45:58.899359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1406 23:45:58.899446 ==
1407 23:45:58.899528 DQS Delay:
1408 23:45:58.899614 DQS0 = 0, DQS1 = 0
1409 23:45:58.899695 DQM Delay:
1410 23:45:58.899780 DQM0 = 86, DQM1 = 75
1411 23:45:58.899868 DQ Delay:
1412 23:45:58.899950 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1413 23:45:58.900035 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1414 23:45:58.900118 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
1415 23:45:58.900200 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =80
1416 23:45:58.900286
1417 23:45:58.900396
1418 23:45:58.900479 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1419 23:45:58.900552 CH0 RK1: MR19=606, MR18=2F2B
1420 23:45:58.900629 CH0_RK1: MR19=0x606, MR18=0x2F2B, DQSOSC=397, MR23=63, INC=93, DEC=62
1421 23:45:58.900715 [RxdqsGatingPostProcess] freq 800
1422 23:45:58.900799 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1423 23:45:58.900881 Pre-setting of DQS Precalculation
1424 23:45:58.900968 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1425 23:45:58.901049 ==
1426 23:45:58.901138 Dram Type= 6, Freq= 0, CH_1, rank 0
1427 23:45:58.901238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1428 23:45:58.901350 ==
1429 23:45:58.901436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1430 23:45:58.901520 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1431 23:45:58.901607 [CA 0] Center 36 (6~67) winsize 62
1432 23:45:58.901693 [CA 1] Center 37 (6~68) winsize 63
1433 23:45:58.901775 [CA 2] Center 35 (5~65) winsize 61
1434 23:45:58.901858 [CA 3] Center 34 (4~65) winsize 62
1435 23:45:58.901913 [CA 4] Center 34 (4~65) winsize 62
1436 23:45:58.901965 [CA 5] Center 33 (3~64) winsize 62
1437 23:45:58.902025
1438 23:45:58.902085 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1439 23:45:58.902140
1440 23:45:58.902192 [CATrainingPosCal] consider 1 rank data
1441 23:45:58.902246 u2DelayCellTimex100 = 270/100 ps
1442 23:45:58.902332 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1443 23:45:58.902447 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1444 23:45:58.902532 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1445 23:45:58.902615 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1446 23:45:58.902697 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1447 23:45:58.902786 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1448 23:45:58.902869
1449 23:45:58.902950 CA PerBit enable=1, Macro0, CA PI delay=33
1450 23:45:58.903038
1451 23:45:58.903120 [CBTSetCACLKResult] CA Dly = 33
1452 23:45:58.903208 CS Dly: 4 (0~35)
1453 23:45:58.903289 ==
1454 23:45:58.903370 Dram Type= 6, Freq= 0, CH_1, rank 1
1455 23:45:58.903460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1456 23:45:58.903547 ==
1457 23:45:58.903629 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1458 23:45:58.903717 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1459 23:45:58.903799 [CA 0] Center 36 (6~67) winsize 62
1460 23:45:58.903886 [CA 1] Center 36 (6~67) winsize 62
1461 23:45:58.903968 [CA 2] Center 34 (4~65) winsize 62
1462 23:45:58.904053 [CA 3] Center 34 (3~65) winsize 63
1463 23:45:58.904108 [CA 4] Center 34 (4~65) winsize 62
1464 23:45:58.904161 [CA 5] Center 34 (3~65) winsize 63
1465 23:45:58.904213
1466 23:45:58.904277 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1467 23:45:58.904405
1468 23:45:58.904491 [CATrainingPosCal] consider 2 rank data
1469 23:45:58.904578 u2DelayCellTimex100 = 270/100 ps
1470 23:45:58.904660 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1471 23:45:58.904742 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1472 23:45:58.904829 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1473 23:45:58.904910 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1474 23:45:58.904999 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1475 23:45:58.905086 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1476 23:45:58.905167
1477 23:45:58.905253 CA PerBit enable=1, Macro0, CA PI delay=33
1478 23:45:58.905372
1479 23:45:58.905461 [CBTSetCACLKResult] CA Dly = 33
1480 23:45:58.905546 CS Dly: 5 (0~37)
1481 23:45:58.905610
1482 23:45:58.905663 ----->DramcWriteLeveling(PI) begin...
1483 23:45:58.905731 ==
1484 23:45:58.905795 Dram Type= 6, Freq= 0, CH_1, rank 0
1485 23:45:58.905849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1486 23:45:58.905911 ==
1487 23:45:58.905994 Write leveling (Byte 0): 24 => 24
1488 23:45:58.906076 Write leveling (Byte 1): 29 => 29
1489 23:45:58.906162 DramcWriteLeveling(PI) end<-----
1490 23:45:58.906244
1491 23:45:58.906330 ==
1492 23:45:58.906411 Dram Type= 6, Freq= 0, CH_1, rank 0
1493 23:45:58.906498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1494 23:45:58.906585 ==
1495 23:45:58.906667 [Gating] SW mode calibration
1496 23:45:58.906755 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1497 23:45:58.906844 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1498 23:45:58.906927 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1499 23:45:58.907016 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1500 23:45:58.907100 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1501 23:45:58.907188 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 23:45:58.907277 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 23:45:58.907360 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 23:45:58.907446 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 23:45:58.907533 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 23:45:58.907616 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 23:45:58.907699 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 23:45:58.907988 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 23:45:58.908075 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 23:45:58.908162 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 23:45:58.908218 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 23:45:58.908271 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 23:45:58.908324 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 23:45:58.908436 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1515 23:45:58.908521 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1516 23:45:58.908603 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1517 23:45:58.908692 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 23:45:58.908779 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 23:45:58.908862 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 23:45:58.908949 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 23:45:58.909039 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 23:45:58.909122 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 23:45:58.909210 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1524 23:45:58.909332 0 9 8 | B1->B0 | 3030 3232 | 0 1 | (1 1) (1 1)
1525 23:45:58.909423 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1526 23:45:58.909508 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1527 23:45:58.909590 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1528 23:45:58.909680 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1529 23:45:58.909763 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1530 23:45:58.909850 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1531 23:45:58.909938 0 10 4 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 0)
1532 23:45:58.910020 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1533 23:45:58.910108 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:45:58.910195 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:45:58.910278 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:45:58.910367 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:45:58.910450 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 23:45:58.910536 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 23:45:58.910624 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1540 23:45:58.910707 0 11 8 | B1->B0 | 3b3b 4141 | 0 0 | (0 0) (0 0)
1541 23:45:58.910795 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1542 23:45:58.910874 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1543 23:45:58.910928 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1544 23:45:58.910981 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1545 23:45:58.911042 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1546 23:45:58.911096 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1547 23:45:58.911149 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1548 23:45:58.911201 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 23:45:58.911285 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 23:45:58.911374 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 23:45:58.911457 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 23:45:58.911545 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 23:45:58.911627 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 23:45:58.911715 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 23:45:58.911807 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1556 23:45:58.911893 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1557 23:45:58.911981 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1558 23:45:58.912070 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1559 23:45:58.912152 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 23:45:58.912239 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 23:45:58.912319 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 23:45:58.912404 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1563 23:45:58.912479 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1564 23:45:58.912604 Total UI for P1: 0, mck2ui 16
1565 23:45:58.912691 best dqsien dly found for B0: ( 0, 14, 0)
1566 23:45:58.912774 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1567 23:45:58.912856 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 23:45:58.912938 Total UI for P1: 0, mck2ui 16
1569 23:45:58.913020 best dqsien dly found for B1: ( 0, 14, 6)
1570 23:45:58.913102 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1571 23:45:58.913184 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1572 23:45:58.913287
1573 23:45:58.913356 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1574 23:45:58.913409 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1575 23:45:58.913461 [Gating] SW calibration Done
1576 23:45:58.913513 ==
1577 23:45:58.913565 Dram Type= 6, Freq= 0, CH_1, rank 0
1578 23:45:58.913618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1579 23:45:58.913670 ==
1580 23:45:58.913722 RX Vref Scan: 0
1581 23:45:58.913774
1582 23:45:58.913826 RX Vref 0 -> 0, step: 1
1583 23:45:58.913877
1584 23:45:58.913928 RX Delay -130 -> 252, step: 16
1585 23:45:58.913981 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1586 23:45:58.914033 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1587 23:45:58.914087 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1588 23:45:58.914139 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1589 23:45:58.914191 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1590 23:45:58.914244 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1591 23:45:58.914296 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1592 23:45:58.914348 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1593 23:45:58.914400 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1594 23:45:58.914451 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1595 23:45:58.914503 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1596 23:45:58.914554 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1597 23:45:58.914607 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1598 23:45:58.914853 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1599 23:45:58.914912 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1600 23:45:58.914965 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1601 23:45:58.915018 ==
1602 23:45:58.915070 Dram Type= 6, Freq= 0, CH_1, rank 0
1603 23:45:58.915121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1604 23:45:58.915173 ==
1605 23:45:58.915225 DQS Delay:
1606 23:45:58.915277 DQS0 = 0, DQS1 = 0
1607 23:45:58.915329 DQM Delay:
1608 23:45:58.915380 DQM0 = 85, DQM1 = 79
1609 23:45:58.915432 DQ Delay:
1610 23:45:58.915484 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1611 23:45:58.915536 DQ4 =85, DQ5 =101, DQ6 =93, DQ7 =85
1612 23:45:58.915588 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1613 23:45:58.915640 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1614 23:45:58.915691
1615 23:45:58.915743
1616 23:45:58.915794 ==
1617 23:45:58.915845 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 23:45:58.915897 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 23:45:58.915950 ==
1620 23:45:58.916002
1621 23:45:58.916053
1622 23:45:58.916104 TX Vref Scan disable
1623 23:45:58.916156 == TX Byte 0 ==
1624 23:45:58.916208 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1625 23:45:58.916260 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1626 23:45:58.916312 == TX Byte 1 ==
1627 23:45:58.916365 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1628 23:45:58.916417 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1629 23:45:58.916469 ==
1630 23:45:58.916521 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 23:45:58.916573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 23:45:58.916625 ==
1633 23:45:58.916676 TX Vref=22, minBit 2, minWin=26, winSum=440
1634 23:45:58.916729 TX Vref=24, minBit 2, minWin=26, winSum=444
1635 23:45:58.916781 TX Vref=26, minBit 2, minWin=27, winSum=452
1636 23:45:58.916833 TX Vref=28, minBit 2, minWin=27, winSum=454
1637 23:45:58.916885 TX Vref=30, minBit 1, minWin=27, winSum=455
1638 23:45:58.916937 TX Vref=32, minBit 1, minWin=27, winSum=451
1639 23:45:58.916989 [TxChooseVref] Worse bit 1, Min win 27, Win sum 455, Final Vref 30
1640 23:45:58.917042
1641 23:45:58.917094 Final TX Range 1 Vref 30
1642 23:45:58.917145
1643 23:45:58.917197 ==
1644 23:45:58.917248 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 23:45:58.917309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 23:45:58.917362 ==
1647 23:45:58.917414
1648 23:45:58.917466
1649 23:45:58.917517 TX Vref Scan disable
1650 23:45:58.917570 == TX Byte 0 ==
1651 23:45:58.917622 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1652 23:45:58.917674 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1653 23:45:58.917726 == TX Byte 1 ==
1654 23:45:58.917777 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1655 23:45:58.917829 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1656 23:45:58.917880
1657 23:45:58.917932 [DATLAT]
1658 23:45:58.917984 Freq=800, CH1 RK0
1659 23:45:58.918036
1660 23:45:58.918088 DATLAT Default: 0xa
1661 23:45:58.918140 0, 0xFFFF, sum = 0
1662 23:45:58.918193 1, 0xFFFF, sum = 0
1663 23:45:58.918258 2, 0xFFFF, sum = 0
1664 23:45:58.918312 3, 0xFFFF, sum = 0
1665 23:45:58.918365 4, 0xFFFF, sum = 0
1666 23:45:58.918418 5, 0xFFFF, sum = 0
1667 23:45:58.918471 6, 0xFFFF, sum = 0
1668 23:45:58.918523 7, 0xFFFF, sum = 0
1669 23:45:58.918577 8, 0xFFFF, sum = 0
1670 23:45:58.918630 9, 0x0, sum = 1
1671 23:45:58.918682 10, 0x0, sum = 2
1672 23:45:58.918735 11, 0x0, sum = 3
1673 23:45:58.918788 12, 0x0, sum = 4
1674 23:45:58.918841 best_step = 10
1675 23:45:58.918892
1676 23:45:58.918943 ==
1677 23:45:58.918995 Dram Type= 6, Freq= 0, CH_1, rank 0
1678 23:45:58.919048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1679 23:45:58.919100 ==
1680 23:45:58.919153 RX Vref Scan: 1
1681 23:45:58.919204
1682 23:45:58.919256 Set Vref Range= 32 -> 127
1683 23:45:58.919307
1684 23:45:58.919359 RX Vref 32 -> 127, step: 1
1685 23:45:58.919410
1686 23:45:58.919462 RX Delay -95 -> 252, step: 8
1687 23:45:58.919514
1688 23:45:58.919565 Set Vref, RX VrefLevel [Byte0]: 32
1689 23:45:58.919618 [Byte1]: 32
1690 23:45:58.919669
1691 23:45:58.919721 Set Vref, RX VrefLevel [Byte0]: 33
1692 23:45:58.919773 [Byte1]: 33
1693 23:45:58.919824
1694 23:45:58.919875 Set Vref, RX VrefLevel [Byte0]: 34
1695 23:45:58.919927 [Byte1]: 34
1696 23:45:58.919979
1697 23:45:58.920030 Set Vref, RX VrefLevel [Byte0]: 35
1698 23:45:58.920082 [Byte1]: 35
1699 23:45:58.920134
1700 23:45:58.920185 Set Vref, RX VrefLevel [Byte0]: 36
1701 23:45:58.920237 [Byte1]: 36
1702 23:45:58.920289
1703 23:45:58.920340 Set Vref, RX VrefLevel [Byte0]: 37
1704 23:45:58.920392 [Byte1]: 37
1705 23:45:58.920444
1706 23:45:58.920495 Set Vref, RX VrefLevel [Byte0]: 38
1707 23:45:58.920548 [Byte1]: 38
1708 23:45:58.920600
1709 23:45:58.920651 Set Vref, RX VrefLevel [Byte0]: 39
1710 23:45:58.920703 [Byte1]: 39
1711 23:45:58.920756
1712 23:45:58.920807 Set Vref, RX VrefLevel [Byte0]: 40
1713 23:45:58.920860 [Byte1]: 40
1714 23:45:58.920911
1715 23:45:58.920963 Set Vref, RX VrefLevel [Byte0]: 41
1716 23:45:58.921015 [Byte1]: 41
1717 23:45:58.921067
1718 23:45:58.921118 Set Vref, RX VrefLevel [Byte0]: 42
1719 23:45:58.921170 [Byte1]: 42
1720 23:45:58.921222
1721 23:45:58.921282 Set Vref, RX VrefLevel [Byte0]: 43
1722 23:45:58.921336 [Byte1]: 43
1723 23:45:58.921387
1724 23:45:58.921439 Set Vref, RX VrefLevel [Byte0]: 44
1725 23:45:58.921491 [Byte1]: 44
1726 23:45:58.921542
1727 23:45:58.921594 Set Vref, RX VrefLevel [Byte0]: 45
1728 23:45:58.921646 [Byte1]: 45
1729 23:45:58.921697
1730 23:45:58.921749 Set Vref, RX VrefLevel [Byte0]: 46
1731 23:45:58.921801 [Byte1]: 46
1732 23:45:58.921853
1733 23:45:58.921905 Set Vref, RX VrefLevel [Byte0]: 47
1734 23:45:58.921957 [Byte1]: 47
1735 23:45:58.922008
1736 23:45:58.922059 Set Vref, RX VrefLevel [Byte0]: 48
1737 23:45:58.922111 [Byte1]: 48
1738 23:45:58.922164
1739 23:45:58.922215 Set Vref, RX VrefLevel [Byte0]: 49
1740 23:45:58.922289 [Byte1]: 49
1741 23:45:58.922378
1742 23:45:58.922435 Set Vref, RX VrefLevel [Byte0]: 50
1743 23:45:58.922487 [Byte1]: 50
1744 23:45:58.922540
1745 23:45:58.922591 Set Vref, RX VrefLevel [Byte0]: 51
1746 23:45:58.922644 [Byte1]: 51
1747 23:45:58.922696
1748 23:45:58.922748 Set Vref, RX VrefLevel [Byte0]: 52
1749 23:45:58.922800 [Byte1]: 52
1750 23:45:58.922853
1751 23:45:58.922905 Set Vref, RX VrefLevel [Byte0]: 53
1752 23:45:58.922956 [Byte1]: 53
1753 23:45:58.923008
1754 23:45:58.923060 Set Vref, RX VrefLevel [Byte0]: 54
1755 23:45:58.923113 [Byte1]: 54
1756 23:45:58.923165
1757 23:45:58.923216 Set Vref, RX VrefLevel [Byte0]: 55
1758 23:45:58.923268 [Byte1]: 55
1759 23:45:58.923321
1760 23:45:58.923372 Set Vref, RX VrefLevel [Byte0]: 56
1761 23:45:58.923424 [Byte1]: 56
1762 23:45:58.923476
1763 23:45:58.923527 Set Vref, RX VrefLevel [Byte0]: 57
1764 23:45:58.923773 [Byte1]: 57
1765 23:45:58.923830
1766 23:45:58.923882 Set Vref, RX VrefLevel [Byte0]: 58
1767 23:45:58.923935 [Byte1]: 58
1768 23:45:58.923986
1769 23:45:58.924038 Set Vref, RX VrefLevel [Byte0]: 59
1770 23:45:58.924090 [Byte1]: 59
1771 23:45:58.924142
1772 23:45:58.924193 Set Vref, RX VrefLevel [Byte0]: 60
1773 23:45:58.924244 [Byte1]: 60
1774 23:45:58.924296
1775 23:45:58.924348 Set Vref, RX VrefLevel [Byte0]: 61
1776 23:45:58.924400 [Byte1]: 61
1777 23:45:58.924452
1778 23:45:58.924503 Set Vref, RX VrefLevel [Byte0]: 62
1779 23:45:58.924555 [Byte1]: 62
1780 23:45:58.924607
1781 23:45:58.924658 Set Vref, RX VrefLevel [Byte0]: 63
1782 23:45:58.924710 [Byte1]: 63
1783 23:45:58.924762
1784 23:45:58.924814 Set Vref, RX VrefLevel [Byte0]: 64
1785 23:45:58.924865 [Byte1]: 64
1786 23:45:58.924917
1787 23:45:58.924969 Set Vref, RX VrefLevel [Byte0]: 65
1788 23:45:58.925021 [Byte1]: 65
1789 23:45:58.925073
1790 23:45:58.925124 Set Vref, RX VrefLevel [Byte0]: 66
1791 23:45:58.925176 [Byte1]: 66
1792 23:45:58.925227
1793 23:45:58.925307 Set Vref, RX VrefLevel [Byte0]: 67
1794 23:45:58.925373 [Byte1]: 67
1795 23:45:58.925425
1796 23:45:58.925476 Set Vref, RX VrefLevel [Byte0]: 68
1797 23:45:58.925529 [Byte1]: 68
1798 23:45:58.925581
1799 23:45:58.925632 Set Vref, RX VrefLevel [Byte0]: 69
1800 23:45:58.925685 [Byte1]: 69
1801 23:45:58.925737
1802 23:45:58.925789 Set Vref, RX VrefLevel [Byte0]: 70
1803 23:45:58.925839 [Byte1]: 70
1804 23:45:58.925891
1805 23:45:58.925943 Set Vref, RX VrefLevel [Byte0]: 71
1806 23:45:58.925994 [Byte1]: 71
1807 23:45:58.926045
1808 23:45:58.926097 Final RX Vref Byte 0 = 59 to rank0
1809 23:45:58.926150 Final RX Vref Byte 1 = 56 to rank0
1810 23:45:58.926202 Final RX Vref Byte 0 = 59 to rank1
1811 23:45:58.926254 Final RX Vref Byte 1 = 56 to rank1==
1812 23:45:58.926306 Dram Type= 6, Freq= 0, CH_1, rank 0
1813 23:45:58.926358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 23:45:58.926411 ==
1815 23:45:58.926463 DQS Delay:
1816 23:45:58.926515 DQS0 = 0, DQS1 = 0
1817 23:45:58.926567 DQM Delay:
1818 23:45:58.926619 DQM0 = 85, DQM1 = 80
1819 23:45:58.926671 DQ Delay:
1820 23:45:58.926722 DQ0 =92, DQ1 =80, DQ2 =72, DQ3 =84
1821 23:45:58.926774 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1822 23:45:58.926826 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1823 23:45:58.926878 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1824 23:45:58.926930
1825 23:45:58.926981
1826 23:45:58.927033 [DQSOSCAuto] RK0, (LSB)MR18= 0x2033, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
1827 23:45:58.927086 CH1 RK0: MR19=606, MR18=2033
1828 23:45:58.927138 CH1_RK0: MR19=0x606, MR18=0x2033, DQSOSC=396, MR23=63, INC=94, DEC=62
1829 23:45:58.927190
1830 23:45:58.927242 ----->DramcWriteLeveling(PI) begin...
1831 23:45:58.927295 ==
1832 23:45:58.927347 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 23:45:58.927399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 23:45:58.927451 ==
1835 23:45:58.927503 Write leveling (Byte 0): 28 => 28
1836 23:45:58.927555 Write leveling (Byte 1): 29 => 29
1837 23:45:58.927606 DramcWriteLeveling(PI) end<-----
1838 23:45:58.927658
1839 23:45:58.927710 ==
1840 23:45:58.927762 Dram Type= 6, Freq= 0, CH_1, rank 1
1841 23:45:58.927814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1842 23:45:58.927867 ==
1843 23:45:58.927919 [Gating] SW mode calibration
1844 23:45:58.927971 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1845 23:45:58.928024 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1846 23:45:58.928076 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1847 23:45:58.928128 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1848 23:45:58.928180 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 23:45:58.928232 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 23:45:58.928284 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 23:45:58.928336 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:45:58.928388 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:45:58.928439 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 23:45:58.928490 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 23:45:58.928542 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 23:45:58.928593 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 23:45:58.928645 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 23:45:58.928697 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 23:45:58.928749 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 23:45:58.928802 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 23:45:58.928853 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 23:45:58.928905 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1863 23:45:58.928956 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1864 23:45:58.929008 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1865 23:45:58.929060 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 23:45:58.929111 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 23:45:58.929163 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 23:45:58.929215 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 23:45:58.929311 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 23:45:58.929365 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 23:45:58.929416 0 9 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
1872 23:45:58.929469 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1873 23:45:58.929521 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 23:45:58.929574 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 23:45:58.929626 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 23:45:58.929678 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 23:45:58.929730 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 23:45:58.929782 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1879 23:45:58.929834 0 10 4 | B1->B0 | 3232 2b2b | 0 0 | (0 0) (0 0)
1880 23:45:58.929886 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1881 23:45:58.930130 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:45:58.930190 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:45:58.930243 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:45:58.930296 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:45:58.930348 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:45:58.930400 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:45:58.930453 0 11 4 | B1->B0 | 2a2a 3d3d | 0 0 | (1 1) (0 0)
1888 23:45:58.930505 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1889 23:45:58.930557 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 23:45:58.930627 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 23:45:58.930681 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 23:45:58.930734 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 23:45:58.930788 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 23:45:58.930841 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1895 23:45:58.930894 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1896 23:45:58.930948 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1897 23:45:58.931015 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 23:45:58.931067 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 23:45:58.931119 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 23:45:58.931171 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 23:45:58.931223 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 23:45:58.931275 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 23:45:58.931327 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 23:45:58.931379 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 23:45:58.931431 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 23:45:58.931484 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 23:45:58.931536 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 23:45:58.931588 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 23:45:58.931641 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 23:45:58.931693 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1911 23:45:58.931745 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1912 23:45:58.931796 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1913 23:45:58.931848 Total UI for P1: 0, mck2ui 16
1914 23:45:58.931901 best dqsien dly found for B0: ( 0, 14, 2)
1915 23:45:58.931953 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 23:45:58.932005 Total UI for P1: 0, mck2ui 16
1917 23:45:58.932057 best dqsien dly found for B1: ( 0, 14, 6)
1918 23:45:58.932110 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1919 23:45:58.932162 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1920 23:45:58.932214
1921 23:45:58.932265 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1922 23:45:58.932317 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1923 23:45:58.932369 [Gating] SW calibration Done
1924 23:45:58.932421 ==
1925 23:45:58.932491 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 23:45:58.932557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 23:45:58.932609 ==
1928 23:45:58.932661 RX Vref Scan: 0
1929 23:45:58.932712
1930 23:45:58.932764 RX Vref 0 -> 0, step: 1
1931 23:45:58.932815
1932 23:45:58.932884 RX Delay -130 -> 252, step: 16
1933 23:45:58.932951 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1934 23:45:58.933003 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1935 23:45:58.933055 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1936 23:45:58.933107 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1937 23:45:58.933159 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1938 23:45:58.933211 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1939 23:45:58.933288 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1940 23:45:58.933356 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1941 23:45:58.933408 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1942 23:45:58.933459 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1943 23:45:58.933512 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1944 23:45:58.933564 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1945 23:45:58.933615 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1946 23:45:58.933667 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1947 23:45:58.933719 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1948 23:45:58.933771 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1949 23:45:58.933823 ==
1950 23:45:58.933874 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 23:45:58.933927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 23:45:58.933979 ==
1953 23:45:58.934030 DQS Delay:
1954 23:45:58.934082 DQS0 = 0, DQS1 = 0
1955 23:45:58.934134 DQM Delay:
1956 23:45:58.934185 DQM0 = 79, DQM1 = 78
1957 23:45:58.934237 DQ Delay:
1958 23:45:58.934288 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =69
1959 23:45:58.934340 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1960 23:45:58.934392 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1961 23:45:58.934444 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1962 23:45:58.934496
1963 23:45:58.934547
1964 23:45:58.934599 ==
1965 23:45:58.934651 Dram Type= 6, Freq= 0, CH_1, rank 1
1966 23:45:58.934702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1967 23:45:58.934755 ==
1968 23:45:58.934806
1969 23:45:58.934857
1970 23:45:58.934909 TX Vref Scan disable
1971 23:45:58.934960 == TX Byte 0 ==
1972 23:45:58.935012 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1973 23:45:58.935064 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1974 23:45:58.935116 == TX Byte 1 ==
1975 23:45:58.935168 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1976 23:45:58.935220 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1977 23:45:58.935272 ==
1978 23:45:58.935324 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 23:45:58.935376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 23:45:58.935428 ==
1981 23:45:58.935480 TX Vref=22, minBit 1, minWin=27, winSum=451
1982 23:45:58.935532 TX Vref=24, minBit 0, minWin=27, winSum=450
1983 23:45:58.935585 TX Vref=26, minBit 0, minWin=28, winSum=456
1984 23:45:59.070001 TX Vref=28, minBit 0, minWin=28, winSum=455
1985 23:45:59.070163 TX Vref=30, minBit 7, minWin=27, winSum=453
1986 23:45:59.070257 TX Vref=32, minBit 3, minWin=27, winSum=452
1987 23:45:59.070347 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 26
1988 23:45:59.070433
1989 23:45:59.070518 Final TX Range 1 Vref 26
1990 23:45:59.070603
1991 23:45:59.070685 ==
1992 23:45:59.070768 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 23:45:59.071064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 23:45:59.071152 ==
1995 23:45:59.071235
1996 23:45:59.071317
1997 23:45:59.071399 TX Vref Scan disable
1998 23:45:59.071480 == TX Byte 0 ==
1999 23:45:59.071563 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2000 23:45:59.071647 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2001 23:45:59.071729 == TX Byte 1 ==
2002 23:45:59.071811 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2003 23:45:59.071893 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2004 23:45:59.071974
2005 23:45:59.072054 [DATLAT]
2006 23:45:59.072135 Freq=800, CH1 RK1
2007 23:45:59.072216
2008 23:45:59.072297 DATLAT Default: 0xa
2009 23:45:59.072378 0, 0xFFFF, sum = 0
2010 23:45:59.072462 1, 0xFFFF, sum = 0
2011 23:45:59.072545 2, 0xFFFF, sum = 0
2012 23:45:59.072628 3, 0xFFFF, sum = 0
2013 23:45:59.072711 4, 0xFFFF, sum = 0
2014 23:45:59.072794 5, 0xFFFF, sum = 0
2015 23:45:59.072876 6, 0xFFFF, sum = 0
2016 23:45:59.072959 7, 0xFFFF, sum = 0
2017 23:45:59.073042 8, 0xFFFF, sum = 0
2018 23:45:59.073155 9, 0x0, sum = 1
2019 23:45:59.073238 10, 0x0, sum = 2
2020 23:45:59.073340 11, 0x0, sum = 3
2021 23:45:59.073395 12, 0x0, sum = 4
2022 23:45:59.073448 best_step = 10
2023 23:45:59.073500
2024 23:45:59.073552 ==
2025 23:45:59.073604 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 23:45:59.073656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 23:45:59.073709 ==
2028 23:45:59.073761 RX Vref Scan: 0
2029 23:45:59.073813
2030 23:45:59.073865 RX Vref 0 -> 0, step: 1
2031 23:45:59.073917
2032 23:45:59.073969 RX Delay -95 -> 252, step: 8
2033 23:45:59.074020 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2034 23:45:59.074073 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2035 23:45:59.074125 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2036 23:45:59.074178 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2037 23:45:59.074229 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2038 23:45:59.074281 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2039 23:45:59.074333 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2040 23:45:59.074386 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2041 23:45:59.074438 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2042 23:45:59.074490 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2043 23:45:59.074542 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2044 23:45:59.074595 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2045 23:45:59.074647 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2046 23:45:59.074699 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2047 23:45:59.074751 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2048 23:45:59.074803 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2049 23:45:59.074856 ==
2050 23:45:59.074908 Dram Type= 6, Freq= 0, CH_1, rank 1
2051 23:45:59.074961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2052 23:45:59.075013 ==
2053 23:45:59.075065 DQS Delay:
2054 23:45:59.075117 DQS0 = 0, DQS1 = 0
2055 23:45:59.075169 DQM Delay:
2056 23:45:59.075220 DQM0 = 86, DQM1 = 81
2057 23:45:59.075273 DQ Delay:
2058 23:45:59.075324 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2059 23:45:59.075378 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2060 23:45:59.075431 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
2061 23:45:59.075483 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2062 23:45:59.075535
2063 23:45:59.075587
2064 23:45:59.075639 [DQSOSCAuto] RK1, (LSB)MR18= 0x2541, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
2065 23:45:59.075692 CH1 RK1: MR19=606, MR18=2541
2066 23:45:59.075744 CH1_RK1: MR19=0x606, MR18=0x2541, DQSOSC=393, MR23=63, INC=95, DEC=63
2067 23:45:59.075797 [RxdqsGatingPostProcess] freq 800
2068 23:45:59.075850 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2069 23:45:59.075903 Pre-setting of DQS Precalculation
2070 23:45:59.075956 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2071 23:45:59.076008 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2072 23:45:59.076062 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2073 23:45:59.076115
2074 23:45:59.076167
2075 23:45:59.076218 [Calibration Summary] 1600 Mbps
2076 23:45:59.076271 CH 0, Rank 0
2077 23:45:59.076323 SW Impedance : PASS
2078 23:45:59.076375 DUTY Scan : NO K
2079 23:45:59.076427 ZQ Calibration : PASS
2080 23:45:59.076480 Jitter Meter : NO K
2081 23:45:59.076532 CBT Training : PASS
2082 23:45:59.076585 Write leveling : PASS
2083 23:45:59.076637 RX DQS gating : PASS
2084 23:45:59.076689 RX DQ/DQS(RDDQC) : PASS
2085 23:45:59.076741 TX DQ/DQS : PASS
2086 23:45:59.076794 RX DATLAT : PASS
2087 23:45:59.076846 RX DQ/DQS(Engine): PASS
2088 23:45:59.076898 TX OE : NO K
2089 23:45:59.076951 All Pass.
2090 23:45:59.077004
2091 23:45:59.077056 CH 0, Rank 1
2092 23:45:59.077108 SW Impedance : PASS
2093 23:45:59.077160 DUTY Scan : NO K
2094 23:45:59.077213 ZQ Calibration : PASS
2095 23:45:59.077289 Jitter Meter : NO K
2096 23:45:59.077356 CBT Training : PASS
2097 23:45:59.077408 Write leveling : PASS
2098 23:45:59.077461 RX DQS gating : PASS
2099 23:45:59.077513 RX DQ/DQS(RDDQC) : PASS
2100 23:45:59.077567 TX DQ/DQS : PASS
2101 23:45:59.077619 RX DATLAT : PASS
2102 23:45:59.077671 RX DQ/DQS(Engine): PASS
2103 23:45:59.077724 TX OE : NO K
2104 23:45:59.077776 All Pass.
2105 23:45:59.077828
2106 23:45:59.077879 CH 1, Rank 0
2107 23:45:59.077931 SW Impedance : PASS
2108 23:45:59.077984 DUTY Scan : NO K
2109 23:45:59.078036 ZQ Calibration : PASS
2110 23:45:59.078089 Jitter Meter : NO K
2111 23:45:59.078141 CBT Training : PASS
2112 23:45:59.078194 Write leveling : PASS
2113 23:45:59.078246 RX DQS gating : PASS
2114 23:45:59.078299 RX DQ/DQS(RDDQC) : PASS
2115 23:45:59.078351 TX DQ/DQS : PASS
2116 23:45:59.078403 RX DATLAT : PASS
2117 23:45:59.078456 RX DQ/DQS(Engine): PASS
2118 23:45:59.078509 TX OE : NO K
2119 23:45:59.078562 All Pass.
2120 23:45:59.078614
2121 23:45:59.078667 CH 1, Rank 1
2122 23:45:59.078718 SW Impedance : PASS
2123 23:45:59.078770 DUTY Scan : NO K
2124 23:45:59.078823 ZQ Calibration : PASS
2125 23:45:59.078875 Jitter Meter : NO K
2126 23:45:59.078927 CBT Training : PASS
2127 23:45:59.078979 Write leveling : PASS
2128 23:45:59.079031 RX DQS gating : PASS
2129 23:45:59.079084 RX DQ/DQS(RDDQC) : PASS
2130 23:45:59.079136 TX DQ/DQS : PASS
2131 23:45:59.079189 RX DATLAT : PASS
2132 23:45:59.079241 RX DQ/DQS(Engine): PASS
2133 23:45:59.079292 TX OE : NO K
2134 23:45:59.079345 All Pass.
2135 23:45:59.079397
2136 23:45:59.079448 DramC Write-DBI off
2137 23:45:59.079501 PER_BANK_REFRESH: Hybrid Mode
2138 23:45:59.079553 TX_TRACKING: ON
2139 23:45:59.079605 [GetDramInforAfterCalByMRR] Vendor 6.
2140 23:45:59.079658 [GetDramInforAfterCalByMRR] Revision 606.
2141 23:45:59.079711 [GetDramInforAfterCalByMRR] Revision 2 0.
2142 23:45:59.079763 MR0 0x3b3b
2143 23:45:59.079816 MR8 0x5151
2144 23:45:59.079868 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2145 23:45:59.079920
2146 23:45:59.079973 MR0 0x3b3b
2147 23:45:59.080025 MR8 0x5151
2148 23:45:59.080077 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2149 23:45:59.080129
2150 23:45:59.080376 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2151 23:45:59.080436 [FAST_K] Save calibration result to emmc
2152 23:45:59.080490 [FAST_K] Save calibration result to emmc
2153 23:45:59.080543 dram_init: config_dvfs: 1
2154 23:45:59.080597 dramc_set_vcore_voltage set vcore to 662500
2155 23:45:59.080650 Read voltage for 1200, 2
2156 23:45:59.080702 Vio18 = 0
2157 23:45:59.080755 Vcore = 662500
2158 23:45:59.080807 Vdram = 0
2159 23:45:59.080860 Vddq = 0
2160 23:45:59.080912 Vmddr = 0
2161 23:45:59.080965 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2162 23:45:59.081017 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2163 23:45:59.081070 MEM_TYPE=3, freq_sel=15
2164 23:45:59.081122 sv_algorithm_assistance_LP4_1600
2165 23:45:59.081174 ============ PULL DRAM RESETB DOWN ============
2166 23:45:59.081227 ========== PULL DRAM RESETB DOWN end =========
2167 23:45:59.081303 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2168 23:45:59.081371 ===================================
2169 23:45:59.081423 LPDDR4 DRAM CONFIGURATION
2170 23:45:59.081476 ===================================
2171 23:45:59.081529 EX_ROW_EN[0] = 0x0
2172 23:45:59.081582 EX_ROW_EN[1] = 0x0
2173 23:45:59.081634 LP4Y_EN = 0x0
2174 23:45:59.081686 WORK_FSP = 0x0
2175 23:45:59.081738 WL = 0x4
2176 23:45:59.081791 RL = 0x4
2177 23:45:59.081843 BL = 0x2
2178 23:45:59.081895 RPST = 0x0
2179 23:45:59.081947 RD_PRE = 0x0
2180 23:45:59.081999 WR_PRE = 0x1
2181 23:45:59.082051 WR_PST = 0x0
2182 23:45:59.082103 DBI_WR = 0x0
2183 23:45:59.082155 DBI_RD = 0x0
2184 23:45:59.082207 OTF = 0x1
2185 23:45:59.082260 ===================================
2186 23:45:59.082312 ===================================
2187 23:45:59.082365 ANA top config
2188 23:45:59.082439 ===================================
2189 23:45:59.082494 DLL_ASYNC_EN = 0
2190 23:45:59.082547 ALL_SLAVE_EN = 0
2191 23:45:59.082600 NEW_RANK_MODE = 1
2192 23:45:59.082653 DLL_IDLE_MODE = 1
2193 23:45:59.082706 LP45_APHY_COMB_EN = 1
2194 23:45:59.082758 TX_ODT_DIS = 1
2195 23:45:59.082810 NEW_8X_MODE = 1
2196 23:45:59.082863 ===================================
2197 23:45:59.082916 ===================================
2198 23:45:59.082969 data_rate = 2400
2199 23:45:59.083021 CKR = 1
2200 23:45:59.083074 DQ_P2S_RATIO = 8
2201 23:45:59.083126 ===================================
2202 23:45:59.083178 CA_P2S_RATIO = 8
2203 23:45:59.083231 DQ_CA_OPEN = 0
2204 23:45:59.083283 DQ_SEMI_OPEN = 0
2205 23:45:59.083335 CA_SEMI_OPEN = 0
2206 23:45:59.083387 CA_FULL_RATE = 0
2207 23:45:59.083439 DQ_CKDIV4_EN = 0
2208 23:45:59.083492 CA_CKDIV4_EN = 0
2209 23:45:59.083544 CA_PREDIV_EN = 0
2210 23:45:59.083596 PH8_DLY = 17
2211 23:45:59.083648 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2212 23:45:59.083712 DQ_AAMCK_DIV = 4
2213 23:45:59.083767 CA_AAMCK_DIV = 4
2214 23:45:59.083820 CA_ADMCK_DIV = 4
2215 23:45:59.083872 DQ_TRACK_CA_EN = 0
2216 23:45:59.083924 CA_PICK = 1200
2217 23:45:59.083977 CA_MCKIO = 1200
2218 23:45:59.084030 MCKIO_SEMI = 0
2219 23:45:59.084083 PLL_FREQ = 2366
2220 23:45:59.084136 DQ_UI_PI_RATIO = 32
2221 23:45:59.084189 CA_UI_PI_RATIO = 0
2222 23:45:59.084241 ===================================
2223 23:45:59.084293 ===================================
2224 23:45:59.084346 memory_type:LPDDR4
2225 23:45:59.084399 GP_NUM : 10
2226 23:45:59.084451 SRAM_EN : 1
2227 23:45:59.084503 MD32_EN : 0
2228 23:45:59.084556 ===================================
2229 23:45:59.084609 [ANA_INIT] >>>>>>>>>>>>>>
2230 23:45:59.084662 <<<<<< [CONFIGURE PHASE]: ANA_TX
2231 23:45:59.084715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2232 23:45:59.084803 ===================================
2233 23:45:59.084855 data_rate = 2400,PCW = 0X5b00
2234 23:45:59.084908 ===================================
2235 23:45:59.084960 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2236 23:45:59.085013 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2237 23:45:59.085067 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2238 23:45:59.085120 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2239 23:45:59.085173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2240 23:45:59.085226 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2241 23:45:59.085300 [ANA_INIT] flow start
2242 23:45:59.085398 [ANA_INIT] PLL >>>>>>>>
2243 23:45:59.085450 [ANA_INIT] PLL <<<<<<<<
2244 23:45:59.085503 [ANA_INIT] MIDPI >>>>>>>>
2245 23:45:59.085555 [ANA_INIT] MIDPI <<<<<<<<
2246 23:45:59.085607 [ANA_INIT] DLL >>>>>>>>
2247 23:45:59.085660 [ANA_INIT] DLL <<<<<<<<
2248 23:45:59.085711 [ANA_INIT] flow end
2249 23:45:59.085764 ============ LP4 DIFF to SE enter ============
2250 23:45:59.085818 ============ LP4 DIFF to SE exit ============
2251 23:45:59.085871 [ANA_INIT] <<<<<<<<<<<<<
2252 23:45:59.085923 [Flow] Enable top DCM control >>>>>
2253 23:45:59.085975 [Flow] Enable top DCM control <<<<<
2254 23:45:59.086028 Enable DLL master slave shuffle
2255 23:45:59.086080 ==============================================================
2256 23:45:59.086132 Gating Mode config
2257 23:45:59.086184 ==============================================================
2258 23:45:59.086237 Config description:
2259 23:45:59.086290 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2260 23:45:59.086344 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2261 23:45:59.086398 SELPH_MODE 0: By rank 1: By Phase
2262 23:45:59.086450 ==============================================================
2263 23:45:59.086503 GAT_TRACK_EN = 1
2264 23:45:59.086555 RX_GATING_MODE = 2
2265 23:45:59.086607 RX_GATING_TRACK_MODE = 2
2266 23:45:59.086659 SELPH_MODE = 1
2267 23:45:59.086712 PICG_EARLY_EN = 1
2268 23:45:59.086995 VALID_LAT_VALUE = 1
2269 23:45:59.087053 ==============================================================
2270 23:45:59.087108 Enter into Gating configuration >>>>
2271 23:45:59.087161 Exit from Gating configuration <<<<
2272 23:45:59.087214 Enter into DVFS_PRE_config >>>>>
2273 23:45:59.087267 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2274 23:45:59.087322 Exit from DVFS_PRE_config <<<<<
2275 23:45:59.087374 Enter into PICG configuration >>>>
2276 23:45:59.087426 Exit from PICG configuration <<<<
2277 23:45:59.087479 [RX_INPUT] configuration >>>>>
2278 23:45:59.087531 [RX_INPUT] configuration <<<<<
2279 23:45:59.087584 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2280 23:45:59.087637 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2281 23:45:59.087690 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2282 23:45:59.087743 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2283 23:45:59.087796 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2284 23:45:59.087848 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2285 23:45:59.087901 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2286 23:45:59.087971 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2287 23:45:59.088025 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2288 23:45:59.088111 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2289 23:45:59.088195 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2290 23:45:59.088263 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2291 23:45:59.088333 ===================================
2292 23:45:59.088387 LPDDR4 DRAM CONFIGURATION
2293 23:45:59.088441 ===================================
2294 23:45:59.088495 EX_ROW_EN[0] = 0x0
2295 23:45:59.088548 EX_ROW_EN[1] = 0x0
2296 23:45:59.088601 LP4Y_EN = 0x0
2297 23:45:59.088655 WORK_FSP = 0x0
2298 23:45:59.088709 WL = 0x4
2299 23:45:59.088762 RL = 0x4
2300 23:45:59.088816 BL = 0x2
2301 23:45:59.088869 RPST = 0x0
2302 23:45:59.088923 RD_PRE = 0x0
2303 23:45:59.088976 WR_PRE = 0x1
2304 23:45:59.089030 WR_PST = 0x0
2305 23:45:59.089097 DBI_WR = 0x0
2306 23:45:59.089149 DBI_RD = 0x0
2307 23:45:59.089201 OTF = 0x1
2308 23:45:59.089255 ===================================
2309 23:45:59.089353 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2310 23:45:59.089407 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2311 23:45:59.089460 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 23:45:59.089513 ===================================
2313 23:45:59.089566 LPDDR4 DRAM CONFIGURATION
2314 23:45:59.089618 ===================================
2315 23:45:59.089671 EX_ROW_EN[0] = 0x10
2316 23:45:59.089724 EX_ROW_EN[1] = 0x0
2317 23:45:59.089776 LP4Y_EN = 0x0
2318 23:45:59.089828 WORK_FSP = 0x0
2319 23:45:59.089880 WL = 0x4
2320 23:45:59.089933 RL = 0x4
2321 23:45:59.089985 BL = 0x2
2322 23:45:59.090037 RPST = 0x0
2323 23:45:59.090088 RD_PRE = 0x0
2324 23:45:59.090141 WR_PRE = 0x1
2325 23:45:59.090193 WR_PST = 0x0
2326 23:45:59.090244 DBI_WR = 0x0
2327 23:45:59.090296 DBI_RD = 0x0
2328 23:45:59.090348 OTF = 0x1
2329 23:45:59.090401 ===================================
2330 23:45:59.090453 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2331 23:45:59.090507 ==
2332 23:45:59.090559 Dram Type= 6, Freq= 0, CH_0, rank 0
2333 23:45:59.090611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2334 23:45:59.090665 ==
2335 23:45:59.090717 [Duty_Offset_Calibration]
2336 23:45:59.090769 B0:2 B1:0 CA:4
2337 23:45:59.090821
2338 23:45:59.090874 [DutyScan_Calibration_Flow] k_type=0
2339 23:45:59.090926
2340 23:45:59.090978 ==CLK 0==
2341 23:45:59.091031 Final CLK duty delay cell = 0
2342 23:45:59.091083 [0] MAX Duty = 5156%(X100), DQS PI = 14
2343 23:45:59.091135 [0] MIN Duty = 5000%(X100), DQS PI = 8
2344 23:45:59.091188 [0] AVG Duty = 5078%(X100)
2345 23:45:59.091240
2346 23:45:59.091293 CH0 CLK Duty spec in!! Max-Min= 156%
2347 23:45:59.091345 [DutyScan_Calibration_Flow] ====Done====
2348 23:45:59.091398
2349 23:45:59.091450 [DutyScan_Calibration_Flow] k_type=1
2350 23:45:59.091503
2351 23:45:59.091555 ==DQS 0 ==
2352 23:45:59.091607 Final DQS duty delay cell = 0
2353 23:45:59.091689 [0] MAX Duty = 5156%(X100), DQS PI = 18
2354 23:45:59.091742 [0] MIN Duty = 5093%(X100), DQS PI = 0
2355 23:45:59.091795 [0] AVG Duty = 5124%(X100)
2356 23:45:59.091846
2357 23:45:59.091899 ==DQS 1 ==
2358 23:45:59.091952 Final DQS duty delay cell = 0
2359 23:45:59.092064 [0] MAX Duty = 5125%(X100), DQS PI = 50
2360 23:45:59.092120 [0] MIN Duty = 4938%(X100), DQS PI = 14
2361 23:45:59.092174 [0] AVG Duty = 5031%(X100)
2362 23:45:59.092226
2363 23:45:59.092277 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2364 23:45:59.092329
2365 23:45:59.092381 CH0 DQS 1 Duty spec in!! Max-Min= 187%
2366 23:45:59.092433 [DutyScan_Calibration_Flow] ====Done====
2367 23:45:59.092485
2368 23:45:59.092537 [DutyScan_Calibration_Flow] k_type=3
2369 23:45:59.092589
2370 23:45:59.092640 ==DQM 0 ==
2371 23:45:59.092692 Final DQM duty delay cell = 0
2372 23:45:59.092745 [0] MAX Duty = 5094%(X100), DQS PI = 20
2373 23:45:59.092797 [0] MIN Duty = 4844%(X100), DQS PI = 52
2374 23:45:59.092848 [0] AVG Duty = 4969%(X100)
2375 23:45:59.092900
2376 23:45:59.092951 ==DQM 1 ==
2377 23:45:59.093003 Final DQM duty delay cell = 0
2378 23:45:59.093055 [0] MAX Duty = 4969%(X100), DQS PI = 2
2379 23:45:59.093108 [0] MIN Duty = 4875%(X100), DQS PI = 12
2380 23:45:59.093160 [0] AVG Duty = 4922%(X100)
2381 23:45:59.093212
2382 23:45:59.093290 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2383 23:45:59.093387
2384 23:45:59.093468 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2385 23:45:59.093524 [DutyScan_Calibration_Flow] ====Done====
2386 23:45:59.093576
2387 23:45:59.093628 [DutyScan_Calibration_Flow] k_type=2
2388 23:45:59.093680
2389 23:45:59.093733 ==DQ 0 ==
2390 23:45:59.093785 Final DQ duty delay cell = 0
2391 23:45:59.093838 [0] MAX Duty = 5156%(X100), DQS PI = 18
2392 23:45:59.093889 [0] MIN Duty = 4969%(X100), DQS PI = 52
2393 23:45:59.093941 [0] AVG Duty = 5062%(X100)
2394 23:45:59.093993
2395 23:45:59.094045 ==DQ 1 ==
2396 23:45:59.094096 Final DQ duty delay cell = 0
2397 23:45:59.094149 [0] MAX Duty = 5156%(X100), DQS PI = 4
2398 23:45:59.094201 [0] MIN Duty = 4938%(X100), DQS PI = 14
2399 23:45:59.094254 [0] AVG Duty = 5047%(X100)
2400 23:45:59.094305
2401 23:45:59.094357 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2402 23:45:59.094409
2403 23:45:59.094460 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2404 23:45:59.094711 [DutyScan_Calibration_Flow] ====Done====
2405 23:45:59.094824 ==
2406 23:45:59.094878 Dram Type= 6, Freq= 0, CH_1, rank 0
2407 23:45:59.094932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2408 23:45:59.094987 ==
2409 23:45:59.095040 [Duty_Offset_Calibration]
2410 23:45:59.095094 B0:0 B1:-1 CA:3
2411 23:45:59.095147
2412 23:45:59.095200 [DutyScan_Calibration_Flow] k_type=0
2413 23:45:59.095267
2414 23:45:59.095319 ==CLK 0==
2415 23:45:59.095370 Final CLK duty delay cell = -4
2416 23:45:59.095423 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2417 23:45:59.095475 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2418 23:45:59.095528 [-4] AVG Duty = 4938%(X100)
2419 23:45:59.095580
2420 23:45:59.095632 CH1 CLK Duty spec in!! Max-Min= 124%
2421 23:45:59.095684 [DutyScan_Calibration_Flow] ====Done====
2422 23:45:59.095736
2423 23:45:59.095788 [DutyScan_Calibration_Flow] k_type=1
2424 23:45:59.095839
2425 23:45:59.095891 ==DQS 0 ==
2426 23:45:59.095943 Final DQS duty delay cell = 0
2427 23:45:59.095995 [0] MAX Duty = 5156%(X100), DQS PI = 18
2428 23:45:59.096047 [0] MIN Duty = 4907%(X100), DQS PI = 38
2429 23:45:59.096099 [0] AVG Duty = 5031%(X100)
2430 23:45:59.096203
2431 23:45:59.096259 ==DQS 1 ==
2432 23:45:59.096312 Final DQS duty delay cell = -4
2433 23:45:59.096364 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2434 23:45:59.096416 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2435 23:45:59.096468 [-4] AVG Duty = 4937%(X100)
2436 23:45:59.096538
2437 23:45:59.096604 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2438 23:45:59.096656
2439 23:45:59.096708 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2440 23:45:59.096760 [DutyScan_Calibration_Flow] ====Done====
2441 23:45:59.096813
2442 23:45:59.096865 [DutyScan_Calibration_Flow] k_type=3
2443 23:45:59.096917
2444 23:45:59.096969 ==DQM 0 ==
2445 23:45:59.097021 Final DQM duty delay cell = 0
2446 23:45:59.097074 [0] MAX Duty = 5031%(X100), DQS PI = 28
2447 23:45:59.097127 [0] MIN Duty = 4813%(X100), DQS PI = 36
2448 23:45:59.097180 [0] AVG Duty = 4922%(X100)
2449 23:45:59.097232
2450 23:45:59.097331 ==DQM 1 ==
2451 23:45:59.097385 Final DQM duty delay cell = 0
2452 23:45:59.097437 [0] MAX Duty = 5000%(X100), DQS PI = 34
2453 23:45:59.097489 [0] MIN Duty = 4813%(X100), DQS PI = 0
2454 23:45:59.097541 [0] AVG Duty = 4906%(X100)
2455 23:45:59.097593
2456 23:45:59.097645 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2457 23:45:59.097697
2458 23:45:59.097749 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2459 23:45:59.097801 [DutyScan_Calibration_Flow] ====Done====
2460 23:45:59.097854
2461 23:45:59.097905 [DutyScan_Calibration_Flow] k_type=2
2462 23:45:59.097957
2463 23:45:59.098008 ==DQ 0 ==
2464 23:45:59.098060 Final DQ duty delay cell = -4
2465 23:45:59.098112 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2466 23:45:59.098164 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2467 23:45:59.098216 [-4] AVG Duty = 4922%(X100)
2468 23:45:59.098268
2469 23:45:59.098319 ==DQ 1 ==
2470 23:45:59.098371 Final DQ duty delay cell = 0
2471 23:45:59.098423 [0] MAX Duty = 5031%(X100), DQS PI = 32
2472 23:45:59.098476 [0] MIN Duty = 4844%(X100), DQS PI = 0
2473 23:45:59.098528 [0] AVG Duty = 4937%(X100)
2474 23:45:59.098579
2475 23:45:59.098670 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2476 23:45:59.098732
2477 23:45:59.098785 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2478 23:45:59.098837 [DutyScan_Calibration_Flow] ====Done====
2479 23:45:59.098889 nWR fixed to 30
2480 23:45:59.098942 [ModeRegInit_LP4] CH0 RK0
2481 23:45:59.098995 [ModeRegInit_LP4] CH0 RK1
2482 23:45:59.099047 [ModeRegInit_LP4] CH1 RK0
2483 23:45:59.099099 [ModeRegInit_LP4] CH1 RK1
2484 23:45:59.099151 match AC timing 7
2485 23:45:59.099203 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2486 23:45:59.099255 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2487 23:45:59.099307 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2488 23:45:59.099361 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2489 23:45:59.099414 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2490 23:45:59.099466 ==
2491 23:45:59.099518 Dram Type= 6, Freq= 0, CH_0, rank 0
2492 23:45:59.099570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2493 23:45:59.099623 ==
2494 23:45:59.099674 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2495 23:45:59.099727 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2496 23:45:59.099779 [CA 0] Center 39 (9~70) winsize 62
2497 23:45:59.099831 [CA 1] Center 38 (8~69) winsize 62
2498 23:45:59.099882 [CA 2] Center 35 (5~66) winsize 62
2499 23:45:59.099933 [CA 3] Center 35 (5~66) winsize 62
2500 23:45:59.099985 [CA 4] Center 33 (3~64) winsize 62
2501 23:45:59.100037 [CA 5] Center 33 (3~63) winsize 61
2502 23:45:59.100089
2503 23:45:59.100140 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2504 23:45:59.100192
2505 23:45:59.100244 [CATrainingPosCal] consider 1 rank data
2506 23:45:59.100295 u2DelayCellTimex100 = 270/100 ps
2507 23:45:59.100348 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2508 23:45:59.100399 CA1 delay=38 (8~69),Diff = 5 PI (24 cell)
2509 23:45:59.100452 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2510 23:45:59.100504 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2511 23:45:59.100556 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2512 23:45:59.100608 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2513 23:45:59.100660
2514 23:45:59.100712 CA PerBit enable=1, Macro0, CA PI delay=33
2515 23:45:59.100764
2516 23:45:59.100816 [CBTSetCACLKResult] CA Dly = 33
2517 23:45:59.100868 CS Dly: 6 (0~37)
2518 23:45:59.100920 ==
2519 23:45:59.100972 Dram Type= 6, Freq= 0, CH_0, rank 1
2520 23:45:59.101024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2521 23:45:59.101076 ==
2522 23:45:59.101129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2523 23:45:59.101181 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2524 23:45:59.101233 [CA 0] Center 39 (9~70) winsize 62
2525 23:45:59.101326 [CA 1] Center 39 (9~70) winsize 62
2526 23:45:59.101380 [CA 2] Center 35 (5~66) winsize 62
2527 23:45:59.101464 [CA 3] Center 35 (5~66) winsize 62
2528 23:45:59.101516 [CA 4] Center 34 (4~65) winsize 62
2529 23:45:59.101568 [CA 5] Center 33 (3~64) winsize 62
2530 23:45:59.101620
2531 23:45:59.101672 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2532 23:45:59.101724
2533 23:45:59.101796 [CATrainingPosCal] consider 2 rank data
2534 23:45:59.101901 u2DelayCellTimex100 = 270/100 ps
2535 23:45:59.101983 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2536 23:45:59.102065 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2537 23:45:59.102131 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2538 23:45:59.102185 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2539 23:45:59.102238 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2540 23:45:59.102290 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2541 23:45:59.102343
2542 23:45:59.102395 CA PerBit enable=1, Macro0, CA PI delay=33
2543 23:45:59.102447
2544 23:45:59.102500 [CBTSetCACLKResult] CA Dly = 33
2545 23:45:59.102552 CS Dly: 8 (0~41)
2546 23:45:59.102604
2547 23:45:59.102849 ----->DramcWriteLeveling(PI) begin...
2548 23:45:59.102908 ==
2549 23:45:59.102961 Dram Type= 6, Freq= 0, CH_0, rank 0
2550 23:45:59.103014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2551 23:45:59.103067 ==
2552 23:45:59.103119 Write leveling (Byte 0): 33 => 33
2553 23:45:59.103171 Write leveling (Byte 1): 28 => 28
2554 23:45:59.103223 DramcWriteLeveling(PI) end<-----
2555 23:45:59.103275
2556 23:45:59.103326 ==
2557 23:45:59.103377 Dram Type= 6, Freq= 0, CH_0, rank 0
2558 23:45:59.103430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2559 23:45:59.103482 ==
2560 23:45:59.103534 [Gating] SW mode calibration
2561 23:45:59.103586 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2562 23:45:59.103639 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2563 23:45:59.103691 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2564 23:45:59.103744 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (1 1)
2565 23:45:59.103796 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 23:45:59.103848 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 23:45:59.103901 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 23:45:59.103953 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2569 23:45:59.104005 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2570 23:45:59.104057 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
2571 23:45:59.104109 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
2572 23:45:59.104161 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 23:45:59.104213 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 23:45:59.104265 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 23:45:59.104316 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 23:45:59.104368 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 23:45:59.104420 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
2578 23:45:59.104471 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2579 23:45:59.104523 1 1 0 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)
2580 23:45:59.104575 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2581 23:45:59.104628 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 23:45:59.104679 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 23:45:59.104731 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 23:45:59.104783 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 23:45:59.104835 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2586 23:45:59.104887 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2587 23:45:59.104938 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2588 23:45:59.104990 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 23:45:59.105042 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 23:45:59.105094 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 23:45:59.105145 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 23:45:59.105206 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 23:45:59.105323 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 23:45:59.105377 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 23:45:59.105430 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 23:45:59.105482 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 23:45:59.105534 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 23:45:59.105586 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 23:45:59.105639 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 23:45:59.105692 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 23:45:59.105744 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2602 23:45:59.105795 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2603 23:45:59.105864 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2604 23:45:59.105918 Total UI for P1: 0, mck2ui 16
2605 23:45:59.105971 best dqsien dly found for B0: ( 1, 3, 26)
2606 23:45:59.106023 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 23:45:59.106075 Total UI for P1: 0, mck2ui 16
2608 23:45:59.106128 best dqsien dly found for B1: ( 1, 4, 0)
2609 23:45:59.106180 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2610 23:45:59.106232 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2611 23:45:59.106284
2612 23:45:59.106335 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2613 23:45:59.106387 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2614 23:45:59.106439 [Gating] SW calibration Done
2615 23:45:59.106491 ==
2616 23:45:59.106544 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 23:45:59.106596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 23:45:59.106648 ==
2619 23:45:59.106699 RX Vref Scan: 0
2620 23:45:59.106751
2621 23:45:59.106802 RX Vref 0 -> 0, step: 1
2622 23:45:59.106854
2623 23:45:59.106905 RX Delay -40 -> 252, step: 8
2624 23:45:59.106957 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2625 23:45:59.107009 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2626 23:45:59.107061 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2627 23:45:59.107112 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2628 23:45:59.107164 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2629 23:45:59.107216 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2630 23:45:59.107268 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2631 23:45:59.107320 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2632 23:45:59.107371 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2633 23:45:59.107423 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2634 23:45:59.107475 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2635 23:45:59.107527 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2636 23:45:59.107578 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2637 23:45:59.107631 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2638 23:45:59.107683 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2639 23:45:59.107735 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2640 23:45:59.107786 ==
2641 23:45:59.107838 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 23:45:59.107890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 23:45:59.107942 ==
2644 23:45:59.107993 DQS Delay:
2645 23:45:59.108045 DQS0 = 0, DQS1 = 0
2646 23:45:59.108096 DQM Delay:
2647 23:45:59.108148 DQM0 = 119, DQM1 = 107
2648 23:45:59.108200 DQ Delay:
2649 23:45:59.108452 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2650 23:45:59.108513 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2651 23:45:59.108567 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2652 23:45:59.108620 DQ12 =119, DQ13 =111, DQ14 =115, DQ15 =111
2653 23:45:59.108673
2654 23:45:59.108725
2655 23:45:59.108777 ==
2656 23:45:59.108828 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 23:45:59.108881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 23:45:59.108934 ==
2659 23:45:59.108986
2660 23:45:59.109038
2661 23:45:59.109089 TX Vref Scan disable
2662 23:45:59.109142 == TX Byte 0 ==
2663 23:45:59.109194 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2664 23:45:59.109248 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2665 23:45:59.109349 == TX Byte 1 ==
2666 23:45:59.109402 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2667 23:45:59.109454 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2668 23:45:59.109506 ==
2669 23:45:59.109558 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 23:45:59.109610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 23:45:59.109663 ==
2672 23:45:59.109715 TX Vref=22, minBit 14, minWin=25, winSum=420
2673 23:45:59.109767 TX Vref=24, minBit 13, minWin=25, winSum=421
2674 23:45:59.109820 TX Vref=26, minBit 13, minWin=25, winSum=426
2675 23:45:59.109873 TX Vref=28, minBit 5, minWin=26, winSum=432
2676 23:45:59.109925 TX Vref=30, minBit 5, minWin=26, winSum=432
2677 23:45:59.109976 TX Vref=32, minBit 4, minWin=26, winSum=429
2678 23:45:59.110030 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 28
2679 23:45:59.110083
2680 23:45:59.110134 Final TX Range 1 Vref 28
2681 23:45:59.110187
2682 23:45:59.110238 ==
2683 23:45:59.110290 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 23:45:59.110342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 23:45:59.110394 ==
2686 23:45:59.110446
2687 23:45:59.110497
2688 23:45:59.110549 TX Vref Scan disable
2689 23:45:59.110601 == TX Byte 0 ==
2690 23:45:59.110653 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2691 23:45:59.110705 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2692 23:45:59.110758 == TX Byte 1 ==
2693 23:45:59.110809 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2694 23:45:59.110861 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2695 23:45:59.110913
2696 23:45:59.110964 [DATLAT]
2697 23:45:59.111016 Freq=1200, CH0 RK0
2698 23:45:59.111068
2699 23:45:59.111119 DATLAT Default: 0xd
2700 23:45:59.111171 0, 0xFFFF, sum = 0
2701 23:45:59.111224 1, 0xFFFF, sum = 0
2702 23:45:59.111278 2, 0xFFFF, sum = 0
2703 23:45:59.111330 3, 0xFFFF, sum = 0
2704 23:45:59.111383 4, 0xFFFF, sum = 0
2705 23:45:59.111436 5, 0xFFFF, sum = 0
2706 23:45:59.111489 6, 0xFFFF, sum = 0
2707 23:45:59.111541 7, 0xFFFF, sum = 0
2708 23:45:59.111594 8, 0xFFFF, sum = 0
2709 23:45:59.111647 9, 0xFFFF, sum = 0
2710 23:45:59.111700 10, 0xFFFF, sum = 0
2711 23:45:59.111753 11, 0xFFFF, sum = 0
2712 23:45:59.111819 12, 0x0, sum = 1
2713 23:45:59.111907 13, 0x0, sum = 2
2714 23:45:59.111990 14, 0x0, sum = 3
2715 23:45:59.112077 15, 0x0, sum = 4
2716 23:45:59.112139 best_step = 13
2717 23:45:59.112192
2718 23:45:59.112244 ==
2719 23:45:59.112296 Dram Type= 6, Freq= 0, CH_0, rank 0
2720 23:45:59.112349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2721 23:45:59.112401 ==
2722 23:45:59.112454 RX Vref Scan: 1
2723 23:45:59.112506
2724 23:45:59.112558 Set Vref Range= 32 -> 127
2725 23:45:59.112611
2726 23:45:59.112662 RX Vref 32 -> 127, step: 1
2727 23:45:59.112714
2728 23:45:59.112766 RX Delay -21 -> 252, step: 4
2729 23:45:59.112818
2730 23:45:59.112869 Set Vref, RX VrefLevel [Byte0]: 32
2731 23:45:59.112921 [Byte1]: 32
2732 23:45:59.112973
2733 23:45:59.113025 Set Vref, RX VrefLevel [Byte0]: 33
2734 23:45:59.113076 [Byte1]: 33
2735 23:45:59.113128
2736 23:45:59.113179 Set Vref, RX VrefLevel [Byte0]: 34
2737 23:45:59.113231 [Byte1]: 34
2738 23:45:59.113329
2739 23:45:59.113381 Set Vref, RX VrefLevel [Byte0]: 35
2740 23:45:59.113434 [Byte1]: 35
2741 23:45:59.113486
2742 23:45:59.113537 Set Vref, RX VrefLevel [Byte0]: 36
2743 23:45:59.113589 [Byte1]: 36
2744 23:45:59.113641
2745 23:45:59.113692 Set Vref, RX VrefLevel [Byte0]: 37
2746 23:45:59.113744 [Byte1]: 37
2747 23:45:59.113795
2748 23:45:59.113847 Set Vref, RX VrefLevel [Byte0]: 38
2749 23:45:59.113899 [Byte1]: 38
2750 23:45:59.113950
2751 23:45:59.114002 Set Vref, RX VrefLevel [Byte0]: 39
2752 23:45:59.114053 [Byte1]: 39
2753 23:45:59.114105
2754 23:45:59.114156 Set Vref, RX VrefLevel [Byte0]: 40
2755 23:45:59.114208 [Byte1]: 40
2756 23:45:59.114259
2757 23:45:59.114311 Set Vref, RX VrefLevel [Byte0]: 41
2758 23:45:59.114363 [Byte1]: 41
2759 23:45:59.114415
2760 23:45:59.114466 Set Vref, RX VrefLevel [Byte0]: 42
2761 23:45:59.114518 [Byte1]: 42
2762 23:45:59.114570
2763 23:45:59.114652 Set Vref, RX VrefLevel [Byte0]: 43
2764 23:45:59.114704 [Byte1]: 43
2765 23:45:59.114756
2766 23:45:59.114808 Set Vref, RX VrefLevel [Byte0]: 44
2767 23:45:59.114860 [Byte1]: 44
2768 23:45:59.114912
2769 23:45:59.114963 Set Vref, RX VrefLevel [Byte0]: 45
2770 23:45:59.115015 [Byte1]: 45
2771 23:45:59.115067
2772 23:45:59.115118 Set Vref, RX VrefLevel [Byte0]: 46
2773 23:45:59.115170 [Byte1]: 46
2774 23:45:59.115244
2775 23:45:59.115298 Set Vref, RX VrefLevel [Byte0]: 47
2776 23:45:59.115350 [Byte1]: 47
2777 23:45:59.115402
2778 23:45:59.115454 Set Vref, RX VrefLevel [Byte0]: 48
2779 23:45:59.115506 [Byte1]: 48
2780 23:45:59.115558
2781 23:45:59.115610 Set Vref, RX VrefLevel [Byte0]: 49
2782 23:45:59.115661 [Byte1]: 49
2783 23:45:59.115713
2784 23:45:59.115764 Set Vref, RX VrefLevel [Byte0]: 50
2785 23:45:59.115816 [Byte1]: 50
2786 23:45:59.115867
2787 23:45:59.115918 Set Vref, RX VrefLevel [Byte0]: 51
2788 23:45:59.115970 [Byte1]: 51
2789 23:45:59.116022
2790 23:45:59.116073 Set Vref, RX VrefLevel [Byte0]: 52
2791 23:45:59.116124 [Byte1]: 52
2792 23:45:59.116176
2793 23:45:59.116227 Set Vref, RX VrefLevel [Byte0]: 53
2794 23:45:59.116280 [Byte1]: 53
2795 23:45:59.116331
2796 23:45:59.116383 Set Vref, RX VrefLevel [Byte0]: 54
2797 23:45:59.116435 [Byte1]: 54
2798 23:45:59.116486
2799 23:45:59.116538 Set Vref, RX VrefLevel [Byte0]: 55
2800 23:45:59.116590 [Byte1]: 55
2801 23:45:59.116671
2802 23:45:59.116723 Set Vref, RX VrefLevel [Byte0]: 56
2803 23:45:59.116774 [Byte1]: 56
2804 23:45:59.116826
2805 23:45:59.116877 Set Vref, RX VrefLevel [Byte0]: 57
2806 23:45:59.116928 [Byte1]: 57
2807 23:45:59.116981
2808 23:45:59.117032 Set Vref, RX VrefLevel [Byte0]: 58
2809 23:45:59.117084 [Byte1]: 58
2810 23:45:59.117136
2811 23:45:59.117188 Set Vref, RX VrefLevel [Byte0]: 59
2812 23:45:59.117239 [Byte1]: 59
2813 23:45:59.117301
2814 23:45:59.117353 Set Vref, RX VrefLevel [Byte0]: 60
2815 23:45:59.117596 [Byte1]: 60
2816 23:45:59.117653
2817 23:45:59.117706 Set Vref, RX VrefLevel [Byte0]: 61
2818 23:45:59.117758 [Byte1]: 61
2819 23:45:59.117810
2820 23:45:59.117862 Set Vref, RX VrefLevel [Byte0]: 62
2821 23:45:59.117914 [Byte1]: 62
2822 23:45:59.117966
2823 23:45:59.118017 Set Vref, RX VrefLevel [Byte0]: 63
2824 23:45:59.118069 [Byte1]: 63
2825 23:45:59.118121
2826 23:45:59.118172 Set Vref, RX VrefLevel [Byte0]: 64
2827 23:45:59.118224 [Byte1]: 64
2828 23:45:59.118276
2829 23:45:59.118328 Set Vref, RX VrefLevel [Byte0]: 65
2830 23:45:59.118380 [Byte1]: 65
2831 23:45:59.118432
2832 23:45:59.118483 Set Vref, RX VrefLevel [Byte0]: 66
2833 23:45:59.118535 [Byte1]: 66
2834 23:45:59.118586
2835 23:45:59.118638 Set Vref, RX VrefLevel [Byte0]: 67
2836 23:45:59.118690 [Byte1]: 67
2837 23:45:59.118741
2838 23:45:59.118793 Final RX Vref Byte 0 = 57 to rank0
2839 23:45:59.118845 Final RX Vref Byte 1 = 51 to rank0
2840 23:45:59.118910 Final RX Vref Byte 0 = 57 to rank1
2841 23:45:59.118970 Final RX Vref Byte 1 = 51 to rank1==
2842 23:45:59.119022 Dram Type= 6, Freq= 0, CH_0, rank 0
2843 23:45:59.119074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2844 23:45:59.119127 ==
2845 23:45:59.119179 DQS Delay:
2846 23:45:59.119230 DQS0 = 0, DQS1 = 0
2847 23:45:59.119282 DQM Delay:
2848 23:45:59.119334 DQM0 = 119, DQM1 = 105
2849 23:45:59.119387 DQ Delay:
2850 23:45:59.119439 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =116
2851 23:45:59.119491 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =122
2852 23:45:59.119543 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2853 23:45:59.119595 DQ12 =116, DQ13 =110, DQ14 =116, DQ15 =114
2854 23:45:59.119647
2855 23:45:59.119698
2856 23:45:59.119749 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2857 23:45:59.119803 CH0 RK0: MR19=403, MR18=1FC
2858 23:45:59.119855 CH0_RK0: MR19=0x403, MR18=0x1FC, DQSOSC=409, MR23=63, INC=39, DEC=26
2859 23:45:59.119908
2860 23:45:59.119960 ----->DramcWriteLeveling(PI) begin...
2861 23:45:59.120013 ==
2862 23:45:59.120065 Dram Type= 6, Freq= 0, CH_0, rank 1
2863 23:45:59.120117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2864 23:45:59.120169 ==
2865 23:45:59.120221 Write leveling (Byte 0): 33 => 33
2866 23:45:59.120274 Write leveling (Byte 1): 25 => 25
2867 23:45:59.120326 DramcWriteLeveling(PI) end<-----
2868 23:45:59.120378
2869 23:45:59.120430 ==
2870 23:45:59.120482 Dram Type= 6, Freq= 0, CH_0, rank 1
2871 23:45:59.120534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2872 23:45:59.120586 ==
2873 23:45:59.120638 [Gating] SW mode calibration
2874 23:45:59.120691 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2875 23:45:59.120743 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2876 23:45:59.120796 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2877 23:45:59.120849 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2878 23:45:59.120901 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2879 23:45:59.120953 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2880 23:45:59.121006 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2881 23:45:59.121057 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2882 23:45:59.121109 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2883 23:45:59.121162 0 15 28 | B1->B0 | 3434 2727 | 1 1 | (1 1) (1 0)
2884 23:45:59.121214 1 0 0 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
2885 23:45:59.121291 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2886 23:45:59.121358 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2887 23:45:59.121412 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2888 23:45:59.121464 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2889 23:45:59.121516 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2890 23:45:59.121568 1 0 24 | B1->B0 | 2323 3737 | 0 1 | (0 0) (1 1)
2891 23:45:59.121621 1 0 28 | B1->B0 | 2b2b 4646 | 1 0 | (0 0) (0 0)
2892 23:45:59.121673 1 1 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
2893 23:45:59.121724 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2894 23:45:59.121777 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 23:45:59.121829 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2896 23:45:59.121880 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2897 23:45:59.121932 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 23:45:59.121997 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2899 23:45:59.122056 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2900 23:45:59.122109 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2901 23:45:59.122161 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2902 23:45:59.122213 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2903 23:45:59.122265 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2904 23:45:59.122318 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2905 23:45:59.122370 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2906 23:45:59.122422 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2907 23:45:59.122474 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2908 23:45:59.122527 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2909 23:45:59.122578 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2910 23:45:59.122631 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 23:45:59.122683 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 23:45:59.122735 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 23:45:59.122787 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2914 23:45:59.122839 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2915 23:45:59.122891 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2916 23:45:59.122944 Total UI for P1: 0, mck2ui 16
2917 23:45:59.122996 best dqsien dly found for B0: ( 1, 3, 22)
2918 23:45:59.123049 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 23:45:59.123101 Total UI for P1: 0, mck2ui 16
2920 23:45:59.123154 best dqsien dly found for B1: ( 1, 3, 28)
2921 23:45:59.123207 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2922 23:45:59.123259 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2923 23:45:59.123311
2924 23:45:59.123560 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2925 23:45:59.123620 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2926 23:45:59.123673 [Gating] SW calibration Done
2927 23:45:59.123726 ==
2928 23:45:59.123778 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 23:45:59.123831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 23:45:59.123884 ==
2931 23:45:59.123936 RX Vref Scan: 0
2932 23:45:59.123987
2933 23:45:59.124038 RX Vref 0 -> 0, step: 1
2934 23:45:59.124090
2935 23:45:59.124141 RX Delay -40 -> 252, step: 8
2936 23:45:59.124192 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2937 23:45:59.124245 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2938 23:45:59.124297 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2939 23:45:59.124349 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2940 23:45:59.124402 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2941 23:45:59.124454 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2942 23:45:59.124505 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2943 23:45:59.124557 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2944 23:45:59.124609 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2945 23:45:59.124661 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2946 23:45:59.124713 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2947 23:45:59.124764 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2948 23:45:59.124816 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2949 23:45:59.124869 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2950 23:45:59.124921 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2951 23:45:59.124972 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2952 23:45:59.125024 ==
2953 23:45:59.125076 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 23:45:59.125127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 23:45:59.125180 ==
2956 23:45:59.125231 DQS Delay:
2957 23:45:59.125317 DQS0 = 0, DQS1 = 0
2958 23:45:59.125400 DQM Delay:
2959 23:45:59.125454 DQM0 = 119, DQM1 = 107
2960 23:45:59.125541 DQ Delay:
2961 23:45:59.125593 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2962 23:45:59.125645 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2963 23:45:59.125698 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2964 23:45:59.125750 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2965 23:45:59.125819
2966 23:45:59.125886
2967 23:45:59.125937 ==
2968 23:45:59.125989 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 23:45:59.126042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 23:45:59.126095 ==
2971 23:45:59.126146
2972 23:45:59.126197
2973 23:45:59.126249 TX Vref Scan disable
2974 23:45:59.126301 == TX Byte 0 ==
2975 23:45:59.126352 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2976 23:45:59.126404 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2977 23:45:59.126456 == TX Byte 1 ==
2978 23:45:59.126507 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2979 23:45:59.126560 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2980 23:45:59.126612 ==
2981 23:45:59.126664 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 23:45:59.126716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 23:45:59.126768 ==
2984 23:45:59.126820 TX Vref=22, minBit 8, minWin=25, winSum=416
2985 23:45:59.126872 TX Vref=24, minBit 3, minWin=26, winSum=423
2986 23:45:59.126924 TX Vref=26, minBit 2, minWin=26, winSum=428
2987 23:45:59.126976 TX Vref=28, minBit 10, minWin=26, winSum=432
2988 23:45:59.127028 TX Vref=30, minBit 10, minWin=26, winSum=431
2989 23:45:59.127081 TX Vref=32, minBit 12, minWin=26, winSum=434
2990 23:45:59.127134 [TxChooseVref] Worse bit 12, Min win 26, Win sum 434, Final Vref 32
2991 23:45:59.127186
2992 23:45:59.127237 Final TX Range 1 Vref 32
2993 23:45:59.127289
2994 23:45:59.127341 ==
2995 23:45:59.127393 Dram Type= 6, Freq= 0, CH_0, rank 1
2996 23:45:59.127445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2997 23:45:59.127497 ==
2998 23:45:59.127549
2999 23:45:59.127600
3000 23:45:59.127651 TX Vref Scan disable
3001 23:45:59.127702 == TX Byte 0 ==
3002 23:45:59.329428 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3003 23:45:59.329566 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3004 23:45:59.329632 == TX Byte 1 ==
3005 23:45:59.329692 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3006 23:45:59.329749 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3007 23:45:59.329805
3008 23:45:59.329860 [DATLAT]
3009 23:45:59.329914 Freq=1200, CH0 RK1
3010 23:45:59.329969
3011 23:45:59.330023 DATLAT Default: 0xd
3012 23:45:59.330076 0, 0xFFFF, sum = 0
3013 23:45:59.330130 1, 0xFFFF, sum = 0
3014 23:45:59.330184 2, 0xFFFF, sum = 0
3015 23:45:59.330237 3, 0xFFFF, sum = 0
3016 23:45:59.330290 4, 0xFFFF, sum = 0
3017 23:45:59.330344 5, 0xFFFF, sum = 0
3018 23:45:59.330397 6, 0xFFFF, sum = 0
3019 23:45:59.330450 7, 0xFFFF, sum = 0
3020 23:45:59.330503 8, 0xFFFF, sum = 0
3021 23:45:59.330556 9, 0xFFFF, sum = 0
3022 23:45:59.330609 10, 0xFFFF, sum = 0
3023 23:45:59.330661 11, 0xFFFF, sum = 0
3024 23:45:59.330714 12, 0x0, sum = 1
3025 23:45:59.330767 13, 0x0, sum = 2
3026 23:45:59.330819 14, 0x0, sum = 3
3027 23:45:59.330872 15, 0x0, sum = 4
3028 23:45:59.330924 best_step = 13
3029 23:45:59.330976
3030 23:45:59.331027 ==
3031 23:45:59.331079 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 23:45:59.331132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 23:45:59.331184 ==
3034 23:45:59.331236 RX Vref Scan: 0
3035 23:45:59.331288
3036 23:45:59.331339 RX Vref 0 -> 0, step: 1
3037 23:45:59.331391
3038 23:45:59.331442 RX Delay -21 -> 252, step: 4
3039 23:45:59.331494 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3040 23:45:59.331546 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3041 23:45:59.331598 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3042 23:45:59.331650 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3043 23:45:59.331702 iDelay=195, Bit 4, Center 122 (59 ~ 186) 128
3044 23:45:59.331754 iDelay=195, Bit 5, Center 112 (47 ~ 178) 132
3045 23:45:59.331806 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3046 23:45:59.331858 iDelay=195, Bit 7, Center 124 (59 ~ 190) 132
3047 23:45:59.331909 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3048 23:45:59.331961 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3049 23:45:59.332013 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3050 23:45:59.332065 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3051 23:45:59.332117 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3052 23:45:59.332169 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3053 23:45:59.332221 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3054 23:45:59.332273 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3055 23:45:59.332325 ==
3056 23:45:59.332377 Dram Type= 6, Freq= 0, CH_0, rank 1
3057 23:45:59.332429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 23:45:59.332481 ==
3059 23:45:59.332533 DQS Delay:
3060 23:45:59.332585 DQS0 = 0, DQS1 = 0
3061 23:45:59.332636 DQM Delay:
3062 23:45:59.332687 DQM0 = 118, DQM1 = 106
3063 23:45:59.332739 DQ Delay:
3064 23:45:59.332790 DQ0 =114, DQ1 =118, DQ2 =114, DQ3 =116
3065 23:45:59.332842 DQ4 =122, DQ5 =112, DQ6 =128, DQ7 =124
3066 23:45:59.332894 DQ8 =94, DQ9 =94, DQ10 =108, DQ11 =98
3067 23:45:59.333159 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =116
3068 23:45:59.333253
3069 23:45:59.333401
3070 23:45:59.333507 [DQSOSCAuto] RK1, (LSB)MR18= 0xfefc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3071 23:45:59.333614 CH0 RK1: MR19=303, MR18=FEFC
3072 23:45:59.333720 CH0_RK1: MR19=0x303, MR18=0xFEFC, DQSOSC=410, MR23=63, INC=39, DEC=26
3073 23:45:59.333826 [RxdqsGatingPostProcess] freq 1200
3074 23:45:59.333932 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3075 23:45:59.334035 best DQS0 dly(2T, 0.5T) = (0, 11)
3076 23:45:59.334126 best DQS1 dly(2T, 0.5T) = (0, 12)
3077 23:45:59.334209 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3078 23:45:59.334264 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3079 23:45:59.334318 best DQS0 dly(2T, 0.5T) = (0, 11)
3080 23:45:59.334380 best DQS1 dly(2T, 0.5T) = (0, 11)
3081 23:45:59.334439 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3082 23:45:59.334491 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3083 23:45:59.334544 Pre-setting of DQS Precalculation
3084 23:45:59.334596 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3085 23:45:59.334649 ==
3086 23:45:59.334701 Dram Type= 6, Freq= 0, CH_1, rank 0
3087 23:45:59.334754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 23:45:59.334807 ==
3089 23:45:59.334859 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3090 23:45:59.334912 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3091 23:45:59.334965 [CA 0] Center 38 (8~68) winsize 61
3092 23:45:59.335017 [CA 1] Center 37 (7~68) winsize 62
3093 23:45:59.335069 [CA 2] Center 35 (5~65) winsize 61
3094 23:45:59.335121 [CA 3] Center 34 (4~64) winsize 61
3095 23:45:59.335172 [CA 4] Center 34 (4~65) winsize 62
3096 23:45:59.335224 [CA 5] Center 33 (4~63) winsize 60
3097 23:45:59.335276
3098 23:45:59.335328 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3099 23:45:59.335384
3100 23:45:59.335437 [CATrainingPosCal] consider 1 rank data
3101 23:45:59.335490 u2DelayCellTimex100 = 270/100 ps
3102 23:45:59.335542 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3103 23:45:59.335595 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3104 23:45:59.335647 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3105 23:45:59.335700 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3106 23:45:59.335752 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3107 23:45:59.335804 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3108 23:45:59.335857
3109 23:45:59.335909 CA PerBit enable=1, Macro0, CA PI delay=33
3110 23:45:59.335962
3111 23:45:59.336014 [CBTSetCACLKResult] CA Dly = 33
3112 23:45:59.336067 CS Dly: 5 (0~36)
3113 23:45:59.336119 ==
3114 23:45:59.336171 Dram Type= 6, Freq= 0, CH_1, rank 1
3115 23:45:59.336224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 23:45:59.336277 ==
3117 23:45:59.336329 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3118 23:45:59.336382 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3119 23:45:59.336435 [CA 0] Center 37 (7~68) winsize 62
3120 23:45:59.336488 [CA 1] Center 38 (8~68) winsize 61
3121 23:45:59.336540 [CA 2] Center 35 (5~65) winsize 61
3122 23:45:59.336593 [CA 3] Center 33 (3~64) winsize 62
3123 23:45:59.336645 [CA 4] Center 34 (4~64) winsize 61
3124 23:45:59.336698 [CA 5] Center 33 (3~64) winsize 62
3125 23:45:59.336750
3126 23:45:59.336802 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3127 23:45:59.336855
3128 23:45:59.336907 [CATrainingPosCal] consider 2 rank data
3129 23:45:59.336960 u2DelayCellTimex100 = 270/100 ps
3130 23:45:59.337012 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3131 23:45:59.337064 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3132 23:45:59.337117 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3133 23:45:59.337169 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 23:45:59.337221 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3135 23:45:59.337299 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3136 23:45:59.337366
3137 23:45:59.337419 CA PerBit enable=1, Macro0, CA PI delay=33
3138 23:45:59.337472
3139 23:45:59.337525 [CBTSetCACLKResult] CA Dly = 33
3140 23:45:59.337578 CS Dly: 6 (0~39)
3141 23:45:59.337630
3142 23:45:59.337682 ----->DramcWriteLeveling(PI) begin...
3143 23:45:59.337736 ==
3144 23:45:59.337788 Dram Type= 6, Freq= 0, CH_1, rank 0
3145 23:45:59.337841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 23:45:59.337894 ==
3147 23:45:59.337946 Write leveling (Byte 0): 27 => 27
3148 23:45:59.337998 Write leveling (Byte 1): 26 => 26
3149 23:45:59.338051 DramcWriteLeveling(PI) end<-----
3150 23:45:59.338103
3151 23:45:59.338155 ==
3152 23:45:59.338208 Dram Type= 6, Freq= 0, CH_1, rank 0
3153 23:45:59.338260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3154 23:45:59.338313 ==
3155 23:45:59.338365 [Gating] SW mode calibration
3156 23:45:59.338418 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3157 23:45:59.338471 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3158 23:45:59.338524 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3159 23:45:59.338577 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3160 23:45:59.338630 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3161 23:45:59.338683 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3162 23:45:59.338735 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3163 23:45:59.338791 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3164 23:45:59.338846 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
3165 23:45:59.338898 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
3166 23:45:59.338951 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3167 23:45:59.339003 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3168 23:45:59.339056 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3169 23:45:59.339108 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3170 23:45:59.339179 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3171 23:45:59.339233 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3172 23:45:59.339286 1 0 24 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
3173 23:45:59.339339 1 0 28 | B1->B0 | 3737 4444 | 0 0 | (0 0) (0 0)
3174 23:45:59.339392 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 23:45:59.339444 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3176 23:45:59.339497 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3177 23:45:59.339550 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3178 23:45:59.339800 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3179 23:45:59.339889 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3180 23:45:59.339987 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3181 23:45:59.340073 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3182 23:45:59.340159 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 23:45:59.340242 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3184 23:45:59.340325 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3185 23:45:59.340408 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3186 23:45:59.340490 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3187 23:45:59.340572 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3188 23:45:59.340654 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3189 23:45:59.340737 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3190 23:45:59.340819 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3191 23:45:59.340902 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3192 23:45:59.340983 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3193 23:45:59.341071 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3194 23:45:59.341154 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3195 23:45:59.341236 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3196 23:45:59.341358 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3197 23:45:59.341441 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3198 23:45:59.341523 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 23:45:59.341605 Total UI for P1: 0, mck2ui 16
3200 23:45:59.341689 best dqsien dly found for B0: ( 1, 3, 26)
3201 23:45:59.341771 Total UI for P1: 0, mck2ui 16
3202 23:45:59.341853 best dqsien dly found for B1: ( 1, 3, 26)
3203 23:45:59.341937 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3204 23:45:59.342022 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3205 23:45:59.342104
3206 23:45:59.342186 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3207 23:45:59.342269 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3208 23:45:59.342351 [Gating] SW calibration Done
3209 23:45:59.342432 ==
3210 23:45:59.342515 Dram Type= 6, Freq= 0, CH_1, rank 0
3211 23:45:59.342597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3212 23:45:59.342679 ==
3213 23:45:59.342761 RX Vref Scan: 0
3214 23:45:59.342842
3215 23:45:59.342923 RX Vref 0 -> 0, step: 1
3216 23:45:59.343004
3217 23:45:59.343086 RX Delay -40 -> 252, step: 8
3218 23:45:59.343168 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3219 23:45:59.343252 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3220 23:45:59.343309 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3221 23:45:59.343362 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3222 23:45:59.343415 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3223 23:45:59.343467 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3224 23:45:59.343520 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3225 23:45:59.343573 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3226 23:45:59.343625 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3227 23:45:59.343678 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3228 23:45:59.343730 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3229 23:45:59.343783 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3230 23:45:59.343836 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3231 23:45:59.343888 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3232 23:45:59.343940 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3233 23:45:59.343993 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3234 23:45:59.344046 ==
3235 23:45:59.344099 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 23:45:59.344150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 23:45:59.344203 ==
3238 23:45:59.344256 DQS Delay:
3239 23:45:59.344309 DQS0 = 0, DQS1 = 0
3240 23:45:59.344361 DQM Delay:
3241 23:45:59.344413 DQM0 = 115, DQM1 = 112
3242 23:45:59.344465 DQ Delay:
3243 23:45:59.344517 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3244 23:45:59.344570 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3245 23:45:59.344622 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3246 23:45:59.344675 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3247 23:45:59.344727
3248 23:45:59.344779
3249 23:45:59.344831 ==
3250 23:45:59.344883 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 23:45:59.344936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 23:45:59.344989 ==
3253 23:45:59.345040
3254 23:45:59.345092
3255 23:45:59.345144 TX Vref Scan disable
3256 23:45:59.345196 == TX Byte 0 ==
3257 23:45:59.345249 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3258 23:45:59.345350 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3259 23:45:59.345410 == TX Byte 1 ==
3260 23:45:59.345467 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3261 23:45:59.345521 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3262 23:45:59.345573 ==
3263 23:45:59.345629 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 23:45:59.345688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 23:45:59.345741 ==
3266 23:45:59.345794 TX Vref=22, minBit 8, minWin=24, winSum=408
3267 23:45:59.345848 TX Vref=24, minBit 8, minWin=24, winSum=413
3268 23:45:59.345901 TX Vref=26, minBit 8, minWin=25, winSum=414
3269 23:45:59.345954 TX Vref=28, minBit 9, minWin=25, winSum=422
3270 23:45:59.346007 TX Vref=30, minBit 11, minWin=25, winSum=424
3271 23:45:59.346060 TX Vref=32, minBit 9, minWin=25, winSum=421
3272 23:45:59.346113 [TxChooseVref] Worse bit 11, Min win 25, Win sum 424, Final Vref 30
3273 23:45:59.346166
3274 23:45:59.346218 Final TX Range 1 Vref 30
3275 23:45:59.346270
3276 23:45:59.346322 ==
3277 23:45:59.346375 Dram Type= 6, Freq= 0, CH_1, rank 0
3278 23:45:59.346428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3279 23:45:59.346481 ==
3280 23:45:59.346533
3281 23:45:59.346585
3282 23:45:59.346637 TX Vref Scan disable
3283 23:45:59.346689 == TX Byte 0 ==
3284 23:45:59.346742 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3285 23:45:59.346795 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3286 23:45:59.346847 == TX Byte 1 ==
3287 23:45:59.346899 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3288 23:45:59.346952 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3289 23:45:59.347004
3290 23:45:59.347057 [DATLAT]
3291 23:45:59.347109 Freq=1200, CH1 RK0
3292 23:45:59.347161
3293 23:45:59.347213 DATLAT Default: 0xd
3294 23:45:59.347265 0, 0xFFFF, sum = 0
3295 23:45:59.347319 1, 0xFFFF, sum = 0
3296 23:45:59.347372 2, 0xFFFF, sum = 0
3297 23:45:59.347425 3, 0xFFFF, sum = 0
3298 23:45:59.347479 4, 0xFFFF, sum = 0
3299 23:45:59.347532 5, 0xFFFF, sum = 0
3300 23:45:59.347585 6, 0xFFFF, sum = 0
3301 23:45:59.347639 7, 0xFFFF, sum = 0
3302 23:45:59.347692 8, 0xFFFF, sum = 0
3303 23:45:59.347745 9, 0xFFFF, sum = 0
3304 23:45:59.347993 10, 0xFFFF, sum = 0
3305 23:45:59.348053 11, 0xFFFF, sum = 0
3306 23:45:59.348108 12, 0x0, sum = 1
3307 23:45:59.348162 13, 0x0, sum = 2
3308 23:45:59.348215 14, 0x0, sum = 3
3309 23:45:59.348269 15, 0x0, sum = 4
3310 23:45:59.348323 best_step = 13
3311 23:45:59.348375
3312 23:45:59.348428 ==
3313 23:45:59.348480 Dram Type= 6, Freq= 0, CH_1, rank 0
3314 23:45:59.348533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3315 23:45:59.348586 ==
3316 23:45:59.348644 RX Vref Scan: 1
3317 23:45:59.348702
3318 23:45:59.348755 Set Vref Range= 32 -> 127
3319 23:45:59.348807
3320 23:45:59.348860 RX Vref 32 -> 127, step: 1
3321 23:45:59.348912
3322 23:45:59.348964 RX Delay -13 -> 252, step: 4
3323 23:45:59.349016
3324 23:45:59.349069 Set Vref, RX VrefLevel [Byte0]: 32
3325 23:45:59.349121 [Byte1]: 32
3326 23:45:59.349173
3327 23:45:59.349225 Set Vref, RX VrefLevel [Byte0]: 33
3328 23:45:59.349301 [Byte1]: 33
3329 23:45:59.349370
3330 23:45:59.349422 Set Vref, RX VrefLevel [Byte0]: 34
3331 23:45:59.349474 [Byte1]: 34
3332 23:45:59.349527
3333 23:45:59.349578 Set Vref, RX VrefLevel [Byte0]: 35
3334 23:45:59.349631 [Byte1]: 35
3335 23:45:59.349683
3336 23:45:59.349735 Set Vref, RX VrefLevel [Byte0]: 36
3337 23:45:59.349788 [Byte1]: 36
3338 23:45:59.349840
3339 23:45:59.349893 Set Vref, RX VrefLevel [Byte0]: 37
3340 23:45:59.349946 [Byte1]: 37
3341 23:45:59.349998
3342 23:45:59.350050 Set Vref, RX VrefLevel [Byte0]: 38
3343 23:45:59.350103 [Byte1]: 38
3344 23:45:59.350155
3345 23:45:59.350207 Set Vref, RX VrefLevel [Byte0]: 39
3346 23:45:59.350259 [Byte1]: 39
3347 23:45:59.350312
3348 23:45:59.350364 Set Vref, RX VrefLevel [Byte0]: 40
3349 23:45:59.350416 [Byte1]: 40
3350 23:45:59.350468
3351 23:45:59.350520 Set Vref, RX VrefLevel [Byte0]: 41
3352 23:45:59.350572 [Byte1]: 41
3353 23:45:59.350623
3354 23:45:59.350676 Set Vref, RX VrefLevel [Byte0]: 42
3355 23:45:59.350728 [Byte1]: 42
3356 23:45:59.350780
3357 23:45:59.350832 Set Vref, RX VrefLevel [Byte0]: 43
3358 23:45:59.350884 [Byte1]: 43
3359 23:45:59.350936
3360 23:45:59.350988 Set Vref, RX VrefLevel [Byte0]: 44
3361 23:45:59.351040 [Byte1]: 44
3362 23:45:59.351092
3363 23:45:59.351143 Set Vref, RX VrefLevel [Byte0]: 45
3364 23:45:59.351195 [Byte1]: 45
3365 23:45:59.351246
3366 23:45:59.351297 Set Vref, RX VrefLevel [Byte0]: 46
3367 23:45:59.351349 [Byte1]: 46
3368 23:45:59.351400
3369 23:45:59.351452 Set Vref, RX VrefLevel [Byte0]: 47
3370 23:45:59.351504 [Byte1]: 47
3371 23:45:59.351556
3372 23:45:59.351608 Set Vref, RX VrefLevel [Byte0]: 48
3373 23:45:59.351671 [Byte1]: 48
3374 23:45:59.351753
3375 23:45:59.351834 Set Vref, RX VrefLevel [Byte0]: 49
3376 23:45:59.351915 [Byte1]: 49
3377 23:45:59.351998
3378 23:45:59.352055 Set Vref, RX VrefLevel [Byte0]: 50
3379 23:45:59.352110 [Byte1]: 50
3380 23:45:59.352162
3381 23:45:59.352214 Set Vref, RX VrefLevel [Byte0]: 51
3382 23:45:59.352266 [Byte1]: 51
3383 23:45:59.352318
3384 23:45:59.352369 Set Vref, RX VrefLevel [Byte0]: 52
3385 23:45:59.352421 [Byte1]: 52
3386 23:45:59.352472
3387 23:45:59.352523 Set Vref, RX VrefLevel [Byte0]: 53
3388 23:45:59.352575 [Byte1]: 53
3389 23:45:59.352627
3390 23:45:59.352679 Set Vref, RX VrefLevel [Byte0]: 54
3391 23:45:59.352731 [Byte1]: 54
3392 23:45:59.352782
3393 23:45:59.352833 Set Vref, RX VrefLevel [Byte0]: 55
3394 23:45:59.352886 [Byte1]: 55
3395 23:45:59.352937
3396 23:45:59.352989 Set Vref, RX VrefLevel [Byte0]: 56
3397 23:45:59.353040 [Byte1]: 56
3398 23:45:59.353092
3399 23:45:59.353144 Set Vref, RX VrefLevel [Byte0]: 57
3400 23:45:59.353196 [Byte1]: 57
3401 23:45:59.353247
3402 23:45:59.353337 Set Vref, RX VrefLevel [Byte0]: 58
3403 23:45:59.353391 [Byte1]: 58
3404 23:45:59.353443
3405 23:45:59.353494 Set Vref, RX VrefLevel [Byte0]: 59
3406 23:45:59.353546 [Byte1]: 59
3407 23:45:59.353598
3408 23:45:59.353649 Set Vref, RX VrefLevel [Byte0]: 60
3409 23:45:59.353702 [Byte1]: 60
3410 23:45:59.353754
3411 23:45:59.353805 Set Vref, RX VrefLevel [Byte0]: 61
3412 23:45:59.353856 [Byte1]: 61
3413 23:45:59.353908
3414 23:45:59.353960 Set Vref, RX VrefLevel [Byte0]: 62
3415 23:45:59.354011 [Byte1]: 62
3416 23:45:59.354063
3417 23:45:59.354114 Set Vref, RX VrefLevel [Byte0]: 63
3418 23:45:59.354166 [Byte1]: 63
3419 23:45:59.354218
3420 23:45:59.354270 Set Vref, RX VrefLevel [Byte0]: 64
3421 23:45:59.354322 [Byte1]: 64
3422 23:45:59.354373
3423 23:45:59.354424 Final RX Vref Byte 0 = 51 to rank0
3424 23:45:59.354476 Final RX Vref Byte 1 = 51 to rank0
3425 23:45:59.354528 Final RX Vref Byte 0 = 51 to rank1
3426 23:45:59.354581 Final RX Vref Byte 1 = 51 to rank1==
3427 23:45:59.354633 Dram Type= 6, Freq= 0, CH_1, rank 0
3428 23:45:59.354686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 23:45:59.354738 ==
3430 23:45:59.354790 DQS Delay:
3431 23:45:59.354842 DQS0 = 0, DQS1 = 0
3432 23:45:59.354894 DQM Delay:
3433 23:45:59.354946 DQM0 = 114, DQM1 = 112
3434 23:45:59.354998 DQ Delay:
3435 23:45:59.355050 DQ0 =120, DQ1 =110, DQ2 =104, DQ3 =114
3436 23:45:59.355102 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3437 23:45:59.355154 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3438 23:45:59.355206 DQ12 =122, DQ13 =120, DQ14 =118, DQ15 =122
3439 23:45:59.355258
3440 23:45:59.355313
3441 23:45:59.355367 [DQSOSCAuto] RK0, (LSB)MR18= 0xf400, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3442 23:45:59.355426 CH1 RK0: MR19=304, MR18=F400
3443 23:45:59.355478 CH1_RK0: MR19=0x304, MR18=0xF400, DQSOSC=410, MR23=63, INC=39, DEC=26
3444 23:45:59.355532
3445 23:45:59.355584 ----->DramcWriteLeveling(PI) begin...
3446 23:45:59.355638 ==
3447 23:45:59.355690 Dram Type= 6, Freq= 0, CH_1, rank 1
3448 23:45:59.355742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3449 23:45:59.355795 ==
3450 23:45:59.355847 Write leveling (Byte 0): 26 => 26
3451 23:45:59.355899 Write leveling (Byte 1): 30 => 30
3452 23:45:59.355951 DramcWriteLeveling(PI) end<-----
3453 23:45:59.356003
3454 23:45:59.356055 ==
3455 23:45:59.356106 Dram Type= 6, Freq= 0, CH_1, rank 1
3456 23:45:59.356158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3457 23:45:59.356211 ==
3458 23:45:59.356263 [Gating] SW mode calibration
3459 23:45:59.356315 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3460 23:45:59.356368 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3461 23:45:59.356420 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3462 23:45:59.356711 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3463 23:45:59.356773 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 23:45:59.356856 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 23:45:59.356957 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 23:45:59.357025 0 15 20 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
3467 23:45:59.357079 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
3468 23:45:59.357133 0 15 28 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (0 0)
3469 23:45:59.357187 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3470 23:45:59.357240 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 23:45:59.357318 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 23:45:59.357371 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 23:45:59.357423 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 23:45:59.357475 1 0 20 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
3475 23:45:59.357526 1 0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
3476 23:45:59.357579 1 0 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
3477 23:45:59.357631 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3478 23:45:59.357683 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 23:45:59.357736 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 23:45:59.357789 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 23:45:59.357842 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 23:45:59.357894 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 23:45:59.357946 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3484 23:45:59.357998 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3485 23:45:59.358050 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 23:45:59.358102 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 23:45:59.358153 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 23:45:59.358205 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 23:45:59.358258 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 23:45:59.358310 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 23:45:59.358362 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 23:45:59.358414 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 23:45:59.358486 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 23:45:59.358574 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 23:45:59.358642 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 23:45:59.358695 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 23:45:59.358747 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 23:45:59.358816 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3499 23:45:59.358882 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3500 23:45:59.358934 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3501 23:45:59.358986 Total UI for P1: 0, mck2ui 16
3502 23:45:59.359039 best dqsien dly found for B0: ( 1, 3, 22)
3503 23:45:59.359091 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3504 23:45:59.359143 Total UI for P1: 0, mck2ui 16
3505 23:45:59.359196 best dqsien dly found for B1: ( 1, 3, 28)
3506 23:45:59.359248 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3507 23:45:59.359300 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3508 23:45:59.359352
3509 23:45:59.359404 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3510 23:45:59.359457 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3511 23:45:59.359509 [Gating] SW calibration Done
3512 23:45:59.359561 ==
3513 23:45:59.359613 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 23:45:59.359665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 23:45:59.359719 ==
3516 23:45:59.359771 RX Vref Scan: 0
3517 23:45:59.359822
3518 23:45:59.359873 RX Vref 0 -> 0, step: 1
3519 23:45:59.359925
3520 23:45:59.359977 RX Delay -40 -> 252, step: 8
3521 23:45:59.360030 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3522 23:45:59.360083 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3523 23:45:59.360135 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3524 23:45:59.360187 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3525 23:45:59.360239 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3526 23:45:59.360291 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3527 23:45:59.360343 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3528 23:45:59.360395 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3529 23:45:59.360447 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3530 23:45:59.360499 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3531 23:45:59.360551 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3532 23:45:59.360603 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3533 23:45:59.360654 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3534 23:45:59.360706 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3535 23:45:59.360758 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3536 23:45:59.360810 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3537 23:45:59.360923 ==
3538 23:45:59.361043 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 23:45:59.361136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 23:45:59.361219 ==
3541 23:45:59.361326 DQS Delay:
3542 23:45:59.361380 DQS0 = 0, DQS1 = 0
3543 23:45:59.361432 DQM Delay:
3544 23:45:59.361484 DQM0 = 114, DQM1 = 111
3545 23:45:59.361536 DQ Delay:
3546 23:45:59.361587 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3547 23:45:59.361640 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3548 23:45:59.361691 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3549 23:45:59.361743 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3550 23:45:59.361795
3551 23:45:59.361848
3552 23:45:59.361907 ==
3553 23:45:59.361961 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 23:45:59.362013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 23:45:59.362066 ==
3556 23:45:59.362118
3557 23:45:59.362170
3558 23:45:59.362228 TX Vref Scan disable
3559 23:45:59.362284 == TX Byte 0 ==
3560 23:45:59.362337 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3561 23:45:59.362390 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3562 23:45:59.362442 == TX Byte 1 ==
3563 23:45:59.362494 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3564 23:45:59.362547 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3565 23:45:59.362598 ==
3566 23:45:59.362650 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 23:45:59.362702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 23:45:59.362755 ==
3569 23:45:59.363004 TX Vref=22, minBit 1, minWin=25, winSum=420
3570 23:45:59.363063 TX Vref=24, minBit 1, minWin=26, winSum=427
3571 23:45:59.363117 TX Vref=26, minBit 1, minWin=26, winSum=428
3572 23:45:59.363170 TX Vref=28, minBit 1, minWin=26, winSum=432
3573 23:45:59.363222 TX Vref=30, minBit 9, minWin=26, winSum=432
3574 23:45:59.363275 TX Vref=32, minBit 2, minWin=26, winSum=434
3575 23:45:59.363327 [TxChooseVref] Worse bit 2, Min win 26, Win sum 434, Final Vref 32
3576 23:45:59.363380
3577 23:45:59.363432 Final TX Range 1 Vref 32
3578 23:45:59.363484
3579 23:45:59.363536 ==
3580 23:45:59.363589 Dram Type= 6, Freq= 0, CH_1, rank 1
3581 23:45:59.363641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3582 23:45:59.363693 ==
3583 23:45:59.363744
3584 23:45:59.363796
3585 23:45:59.363847 TX Vref Scan disable
3586 23:45:59.363898 == TX Byte 0 ==
3587 23:45:59.363950 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3588 23:45:59.364003 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3589 23:45:59.364055 == TX Byte 1 ==
3590 23:45:59.364107 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3591 23:45:59.364159 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3592 23:45:59.364210
3593 23:45:59.364261 [DATLAT]
3594 23:45:59.364313 Freq=1200, CH1 RK1
3595 23:45:59.364364
3596 23:45:59.364417 DATLAT Default: 0xd
3597 23:45:59.364469 0, 0xFFFF, sum = 0
3598 23:45:59.364522 1, 0xFFFF, sum = 0
3599 23:45:59.364575 2, 0xFFFF, sum = 0
3600 23:45:59.364628 3, 0xFFFF, sum = 0
3601 23:45:59.364681 4, 0xFFFF, sum = 0
3602 23:45:59.364733 5, 0xFFFF, sum = 0
3603 23:45:59.364786 6, 0xFFFF, sum = 0
3604 23:45:59.364838 7, 0xFFFF, sum = 0
3605 23:45:59.364891 8, 0xFFFF, sum = 0
3606 23:45:59.364949 9, 0xFFFF, sum = 0
3607 23:45:59.365004 10, 0xFFFF, sum = 0
3608 23:45:59.365061 11, 0xFFFF, sum = 0
3609 23:45:59.365114 12, 0x0, sum = 1
3610 23:45:59.365168 13, 0x0, sum = 2
3611 23:45:59.365221 14, 0x0, sum = 3
3612 23:45:59.365312 15, 0x0, sum = 4
3613 23:45:59.365366 best_step = 13
3614 23:45:59.365418
3615 23:45:59.365470 ==
3616 23:45:59.365522 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 23:45:59.365574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 23:45:59.365626 ==
3619 23:45:59.365678 RX Vref Scan: 0
3620 23:45:59.365730
3621 23:45:59.365782 RX Vref 0 -> 0, step: 1
3622 23:45:59.365834
3623 23:45:59.365885 RX Delay -13 -> 252, step: 4
3624 23:45:59.365938 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3625 23:45:59.365990 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3626 23:45:59.366042 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3627 23:45:59.366093 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3628 23:45:59.366145 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3629 23:45:59.366197 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3630 23:45:59.366249 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3631 23:45:59.366301 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3632 23:45:59.366353 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3633 23:45:59.366405 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3634 23:45:59.366457 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3635 23:45:59.366509 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3636 23:45:59.366561 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3637 23:45:59.366613 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3638 23:45:59.366666 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3639 23:45:59.366718 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3640 23:45:59.366770 ==
3641 23:45:59.366822 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 23:45:59.366874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 23:45:59.366926 ==
3644 23:45:59.366978 DQS Delay:
3645 23:45:59.367029 DQS0 = 0, DQS1 = 0
3646 23:45:59.367080 DQM Delay:
3647 23:45:59.367132 DQM0 = 115, DQM1 = 112
3648 23:45:59.367184 DQ Delay:
3649 23:45:59.367236 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =114
3650 23:45:59.367288 DQ4 =112, DQ5 =124, DQ6 =122, DQ7 =112
3651 23:45:59.367340 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3652 23:45:59.367391 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3653 23:45:59.367443
3654 23:45:59.367494
3655 23:45:59.367546 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc0e, (MSB)MR19= 0x304, tDQSOscB0 = 404 ps tDQSOscB1 = 411 ps
3656 23:45:59.367605 CH1 RK1: MR19=304, MR18=FC0E
3657 23:45:59.367662 CH1_RK1: MR19=0x304, MR18=0xFC0E, DQSOSC=404, MR23=63, INC=40, DEC=26
3658 23:45:59.367715 [RxdqsGatingPostProcess] freq 1200
3659 23:45:59.367768 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3660 23:45:59.367820 best DQS0 dly(2T, 0.5T) = (0, 11)
3661 23:45:59.367873 best DQS1 dly(2T, 0.5T) = (0, 11)
3662 23:45:59.367925 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3663 23:45:59.367977 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3664 23:45:59.368028 best DQS0 dly(2T, 0.5T) = (0, 11)
3665 23:45:59.368081 best DQS1 dly(2T, 0.5T) = (0, 11)
3666 23:45:59.368132 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3667 23:45:59.368184 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3668 23:45:59.368236 Pre-setting of DQS Precalculation
3669 23:45:59.368289 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3670 23:45:59.368341 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3671 23:45:59.368398 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3672 23:45:59.368451
3673 23:45:59.368506
3674 23:45:59.368558 [Calibration Summary] 2400 Mbps
3675 23:45:59.368611 CH 0, Rank 0
3676 23:45:59.368663 SW Impedance : PASS
3677 23:45:59.368715 DUTY Scan : NO K
3678 23:45:59.368767 ZQ Calibration : PASS
3679 23:45:59.368819 Jitter Meter : NO K
3680 23:45:59.368872 CBT Training : PASS
3681 23:45:59.368924 Write leveling : PASS
3682 23:45:59.368976 RX DQS gating : PASS
3683 23:45:59.369027 RX DQ/DQS(RDDQC) : PASS
3684 23:45:59.369079 TX DQ/DQS : PASS
3685 23:45:59.369131 RX DATLAT : PASS
3686 23:45:59.369182 RX DQ/DQS(Engine): PASS
3687 23:45:59.369234 TX OE : NO K
3688 23:45:59.369317 All Pass.
3689 23:45:59.369383
3690 23:45:59.369435 CH 0, Rank 1
3691 23:45:59.369487 SW Impedance : PASS
3692 23:45:59.369539 DUTY Scan : NO K
3693 23:45:59.369591 ZQ Calibration : PASS
3694 23:45:59.369643 Jitter Meter : NO K
3695 23:45:59.369695 CBT Training : PASS
3696 23:45:59.369746 Write leveling : PASS
3697 23:45:59.369798 RX DQS gating : PASS
3698 23:45:59.369850 RX DQ/DQS(RDDQC) : PASS
3699 23:45:59.369902 TX DQ/DQS : PASS
3700 23:45:59.369953 RX DATLAT : PASS
3701 23:45:59.370005 RX DQ/DQS(Engine): PASS
3702 23:45:59.370056 TX OE : NO K
3703 23:45:59.370108 All Pass.
3704 23:45:59.370159
3705 23:45:59.370210 CH 1, Rank 0
3706 23:45:59.370262 SW Impedance : PASS
3707 23:45:59.370314 DUTY Scan : NO K
3708 23:45:59.370365 ZQ Calibration : PASS
3709 23:45:59.370417 Jitter Meter : NO K
3710 23:45:59.370469 CBT Training : PASS
3711 23:45:59.370520 Write leveling : PASS
3712 23:45:59.370572 RX DQS gating : PASS
3713 23:45:59.370623 RX DQ/DQS(RDDQC) : PASS
3714 23:45:59.370876 TX DQ/DQS : PASS
3715 23:45:59.370935 RX DATLAT : PASS
3716 23:45:59.370988 RX DQ/DQS(Engine): PASS
3717 23:45:59.371041 TX OE : NO K
3718 23:45:59.371093 All Pass.
3719 23:45:59.371145
3720 23:45:59.371198 CH 1, Rank 1
3721 23:45:59.371250 SW Impedance : PASS
3722 23:45:59.371301 DUTY Scan : NO K
3723 23:45:59.371353 ZQ Calibration : PASS
3724 23:45:59.371404 Jitter Meter : NO K
3725 23:45:59.371456 CBT Training : PASS
3726 23:45:59.371508 Write leveling : PASS
3727 23:45:59.371560 RX DQS gating : PASS
3728 23:45:59.371612 RX DQ/DQS(RDDQC) : PASS
3729 23:45:59.371664 TX DQ/DQS : PASS
3730 23:45:59.371717 RX DATLAT : PASS
3731 23:45:59.371769 RX DQ/DQS(Engine): PASS
3732 23:45:59.371827 TX OE : NO K
3733 23:45:59.371880 All Pass.
3734 23:45:59.371937
3735 23:45:59.371989 DramC Write-DBI off
3736 23:45:59.372041 PER_BANK_REFRESH: Hybrid Mode
3737 23:45:59.372093 TX_TRACKING: ON
3738 23:45:59.372145 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3739 23:45:59.372199 [FAST_K] Save calibration result to emmc
3740 23:45:59.372251 dramc_set_vcore_voltage set vcore to 650000
3741 23:45:59.372303 Read voltage for 600, 5
3742 23:45:59.372356 Vio18 = 0
3743 23:45:59.372407 Vcore = 650000
3744 23:45:59.372459 Vdram = 0
3745 23:45:59.372510 Vddq = 0
3746 23:45:59.372562 Vmddr = 0
3747 23:45:59.372614 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3748 23:45:59.372667 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3749 23:45:59.372719 MEM_TYPE=3, freq_sel=19
3750 23:45:59.372771 sv_algorithm_assistance_LP4_1600
3751 23:45:59.372823 ============ PULL DRAM RESETB DOWN ============
3752 23:45:59.372875 ========== PULL DRAM RESETB DOWN end =========
3753 23:45:59.372927 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3754 23:45:59.372979 ===================================
3755 23:45:59.373031 LPDDR4 DRAM CONFIGURATION
3756 23:45:59.373083 ===================================
3757 23:45:59.373135 EX_ROW_EN[0] = 0x0
3758 23:45:59.373187 EX_ROW_EN[1] = 0x0
3759 23:45:59.373239 LP4Y_EN = 0x0
3760 23:45:59.373337 WORK_FSP = 0x0
3761 23:45:59.373390 WL = 0x2
3762 23:45:59.373442 RL = 0x2
3763 23:45:59.373494 BL = 0x2
3764 23:45:59.373546 RPST = 0x0
3765 23:45:59.373597 RD_PRE = 0x0
3766 23:45:59.373649 WR_PRE = 0x1
3767 23:45:59.373708 WR_PST = 0x0
3768 23:45:59.373763 DBI_WR = 0x0
3769 23:45:59.373816 DBI_RD = 0x0
3770 23:45:59.373868 OTF = 0x1
3771 23:45:59.373920 ===================================
3772 23:45:59.373973 ===================================
3773 23:45:59.374025 ANA top config
3774 23:45:59.374077 ===================================
3775 23:45:59.374129 DLL_ASYNC_EN = 0
3776 23:45:59.374181 ALL_SLAVE_EN = 1
3777 23:45:59.374233 NEW_RANK_MODE = 1
3778 23:45:59.374286 DLL_IDLE_MODE = 1
3779 23:45:59.374338 LP45_APHY_COMB_EN = 1
3780 23:45:59.374390 TX_ODT_DIS = 1
3781 23:45:59.374442 NEW_8X_MODE = 1
3782 23:45:59.374494 ===================================
3783 23:45:59.374545 ===================================
3784 23:45:59.374598 data_rate = 1200
3785 23:45:59.374650 CKR = 1
3786 23:45:59.374701 DQ_P2S_RATIO = 8
3787 23:45:59.374753 ===================================
3788 23:45:59.374805 CA_P2S_RATIO = 8
3789 23:45:59.374877 DQ_CA_OPEN = 0
3790 23:45:59.374932 DQ_SEMI_OPEN = 0
3791 23:45:59.374984 CA_SEMI_OPEN = 0
3792 23:45:59.375037 CA_FULL_RATE = 0
3793 23:45:59.375089 DQ_CKDIV4_EN = 1
3794 23:45:59.375141 CA_CKDIV4_EN = 1
3795 23:45:59.375193 CA_PREDIV_EN = 0
3796 23:45:59.375244 PH8_DLY = 0
3797 23:45:59.375297 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3798 23:45:59.375355 DQ_AAMCK_DIV = 4
3799 23:45:59.375409 CA_AAMCK_DIV = 4
3800 23:45:59.375465 CA_ADMCK_DIV = 4
3801 23:45:59.375518 DQ_TRACK_CA_EN = 0
3802 23:45:59.375571 CA_PICK = 600
3803 23:45:59.375623 CA_MCKIO = 600
3804 23:45:59.375675 MCKIO_SEMI = 0
3805 23:45:59.375727 PLL_FREQ = 2288
3806 23:45:59.375779 DQ_UI_PI_RATIO = 32
3807 23:45:59.375830 CA_UI_PI_RATIO = 0
3808 23:45:59.375882 ===================================
3809 23:45:59.375934 ===================================
3810 23:45:59.375986 memory_type:LPDDR4
3811 23:45:59.376038 GP_NUM : 10
3812 23:45:59.376089 SRAM_EN : 1
3813 23:45:59.376141 MD32_EN : 0
3814 23:45:59.376193 ===================================
3815 23:45:59.376245 [ANA_INIT] >>>>>>>>>>>>>>
3816 23:45:59.376297 <<<<<< [CONFIGURE PHASE]: ANA_TX
3817 23:45:59.376349 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3818 23:45:59.376401 ===================================
3819 23:45:59.376454 data_rate = 1200,PCW = 0X5800
3820 23:45:59.376506 ===================================
3821 23:45:59.376558 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3822 23:45:59.376610 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3823 23:45:59.376663 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3824 23:45:59.376715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3825 23:45:59.376767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3826 23:45:59.376819 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3827 23:45:59.376872 [ANA_INIT] flow start
3828 23:45:59.376924 [ANA_INIT] PLL >>>>>>>>
3829 23:45:59.376975 [ANA_INIT] PLL <<<<<<<<
3830 23:45:59.377027 [ANA_INIT] MIDPI >>>>>>>>
3831 23:45:59.377079 [ANA_INIT] MIDPI <<<<<<<<
3832 23:45:59.377130 [ANA_INIT] DLL >>>>>>>>
3833 23:45:59.377181 [ANA_INIT] flow end
3834 23:45:59.377233 ============ LP4 DIFF to SE enter ============
3835 23:45:59.377335 ============ LP4 DIFF to SE exit ============
3836 23:45:59.377388 [ANA_INIT] <<<<<<<<<<<<<
3837 23:45:59.377440 [Flow] Enable top DCM control >>>>>
3838 23:45:59.377492 [Flow] Enable top DCM control <<<<<
3839 23:45:59.377545 Enable DLL master slave shuffle
3840 23:45:59.377597 ==============================================================
3841 23:45:59.377650 Gating Mode config
3842 23:45:59.377701 ==============================================================
3843 23:45:59.377753 Config description:
3844 23:45:59.378002 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3845 23:45:59.378065 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3846 23:45:59.378127 SELPH_MODE 0: By rank 1: By Phase
3847 23:45:59.378182 ==============================================================
3848 23:45:59.378239 GAT_TRACK_EN = 1
3849 23:45:59.378292 RX_GATING_MODE = 2
3850 23:45:59.378345 RX_GATING_TRACK_MODE = 2
3851 23:45:59.378397 SELPH_MODE = 1
3852 23:45:59.378449 PICG_EARLY_EN = 1
3853 23:45:59.378501 VALID_LAT_VALUE = 1
3854 23:45:59.378554 ==============================================================
3855 23:45:59.378606 Enter into Gating configuration >>>>
3856 23:45:59.378659 Exit from Gating configuration <<<<
3857 23:45:59.378711 Enter into DVFS_PRE_config >>>>>
3858 23:45:59.378772 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3859 23:45:59.378830 Exit from DVFS_PRE_config <<<<<
3860 23:45:59.378915 Enter into PICG configuration >>>>
3861 23:45:59.379007 Exit from PICG configuration <<<<
3862 23:45:59.379090 [RX_INPUT] configuration >>>>>
3863 23:45:59.379172 [RX_INPUT] configuration <<<<<
3864 23:45:59.379255 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3865 23:45:59.379338 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3866 23:45:59.379421 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3867 23:45:59.379504 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3868 23:45:59.379603 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3869 23:45:59.384889 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3870 23:45:59.388285 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3871 23:45:59.391815 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3872 23:45:59.394662 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3873 23:45:59.401061 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3874 23:45:59.405000 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3875 23:45:59.407803 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3876 23:45:59.410962 ===================================
3877 23:45:59.414415 LPDDR4 DRAM CONFIGURATION
3878 23:45:59.417777 ===================================
3879 23:45:59.417860 EX_ROW_EN[0] = 0x0
3880 23:45:59.421250 EX_ROW_EN[1] = 0x0
3881 23:45:59.424669 LP4Y_EN = 0x0
3882 23:45:59.424749 WORK_FSP = 0x0
3883 23:45:59.427976 WL = 0x2
3884 23:45:59.428057 RL = 0x2
3885 23:45:59.431173 BL = 0x2
3886 23:45:59.431254 RPST = 0x0
3887 23:45:59.434134 RD_PRE = 0x0
3888 23:45:59.434215 WR_PRE = 0x1
3889 23:45:59.437584 WR_PST = 0x0
3890 23:45:59.437665 DBI_WR = 0x0
3891 23:45:59.440724 DBI_RD = 0x0
3892 23:45:59.440805 OTF = 0x1
3893 23:45:59.443942 ===================================
3894 23:45:59.447732 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3895 23:45:59.453972 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3896 23:45:59.457570 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3897 23:45:59.460941 ===================================
3898 23:45:59.464262 LPDDR4 DRAM CONFIGURATION
3899 23:45:59.467353 ===================================
3900 23:45:59.467435 EX_ROW_EN[0] = 0x10
3901 23:45:59.471128 EX_ROW_EN[1] = 0x0
3902 23:45:59.473960 LP4Y_EN = 0x0
3903 23:45:59.474041 WORK_FSP = 0x0
3904 23:45:59.477823 WL = 0x2
3905 23:45:59.477903 RL = 0x2
3906 23:45:59.480709 BL = 0x2
3907 23:45:59.480789 RPST = 0x0
3908 23:45:59.483839 RD_PRE = 0x0
3909 23:45:59.483949 WR_PRE = 0x1
3910 23:45:59.486910 WR_PST = 0x0
3911 23:45:59.487009 DBI_WR = 0x0
3912 23:45:59.490386 DBI_RD = 0x0
3913 23:45:59.490466 OTF = 0x1
3914 23:45:59.494333 ===================================
3915 23:45:59.499999 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3916 23:45:59.504515 nWR fixed to 30
3917 23:45:59.507756 [ModeRegInit_LP4] CH0 RK0
3918 23:45:59.507842 [ModeRegInit_LP4] CH0 RK1
3919 23:45:59.511057 [ModeRegInit_LP4] CH1 RK0
3920 23:45:59.514790 [ModeRegInit_LP4] CH1 RK1
3921 23:45:59.514870 match AC timing 17
3922 23:45:59.520750 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3923 23:45:59.524482 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3924 23:45:59.527427 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3925 23:45:59.534222 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3926 23:45:59.537229 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3927 23:45:59.537353 ==
3928 23:45:59.540811 Dram Type= 6, Freq= 0, CH_0, rank 0
3929 23:45:59.543904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3930 23:45:59.543986 ==
3931 23:45:59.550751 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3932 23:45:59.557002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3933 23:45:59.560197 [CA 0] Center 36 (6~67) winsize 62
3934 23:45:59.563696 [CA 1] Center 36 (6~66) winsize 61
3935 23:45:59.567131 [CA 2] Center 34 (3~65) winsize 63
3936 23:45:59.570257 [CA 3] Center 34 (3~65) winsize 63
3937 23:45:59.573213 [CA 4] Center 33 (3~64) winsize 62
3938 23:45:59.576992 [CA 5] Center 33 (3~64) winsize 62
3939 23:45:59.577108
3940 23:45:59.580213 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3941 23:45:59.580320
3942 23:45:59.583398 [CATrainingPosCal] consider 1 rank data
3943 23:45:59.586596 u2DelayCellTimex100 = 270/100 ps
3944 23:45:59.589709 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3945 23:45:59.593601 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3946 23:45:59.599951 CA2 delay=34 (3~65),Diff = 1 PI (9 cell)
3947 23:45:59.603111 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3948 23:45:59.606703 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3949 23:45:59.609971 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3950 23:45:59.610043
3951 23:45:59.613459 CA PerBit enable=1, Macro0, CA PI delay=33
3952 23:45:59.613540
3953 23:45:59.616027 [CBTSetCACLKResult] CA Dly = 33
3954 23:45:59.616108 CS Dly: 5 (0~36)
3955 23:45:59.619596 ==
3956 23:45:59.623433 Dram Type= 6, Freq= 0, CH_0, rank 1
3957 23:45:59.626561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 23:45:59.626643 ==
3959 23:45:59.629248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3960 23:45:59.635998 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3961 23:45:59.639773 [CA 0] Center 36 (6~67) winsize 62
3962 23:45:59.643902 [CA 1] Center 36 (6~67) winsize 62
3963 23:45:59.646570 [CA 2] Center 34 (4~65) winsize 62
3964 23:45:59.650050 [CA 3] Center 34 (4~65) winsize 62
3965 23:45:59.652992 [CA 4] Center 34 (3~65) winsize 63
3966 23:45:59.656474 [CA 5] Center 33 (3~64) winsize 62
3967 23:45:59.656554
3968 23:45:59.659816 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3969 23:45:59.659898
3970 23:45:59.664044 [CATrainingPosCal] consider 2 rank data
3971 23:45:59.666196 u2DelayCellTimex100 = 270/100 ps
3972 23:45:59.669475 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3973 23:45:59.676023 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3974 23:45:59.679463 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3975 23:45:59.682657 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3976 23:45:59.686540 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3977 23:45:59.689207 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 23:45:59.689324
3979 23:45:59.692462 CA PerBit enable=1, Macro0, CA PI delay=33
3980 23:45:59.692544
3981 23:45:59.695900 [CBTSetCACLKResult] CA Dly = 33
3982 23:45:59.699353 CS Dly: 5 (0~37)
3983 23:45:59.699434
3984 23:45:59.702702 ----->DramcWriteLeveling(PI) begin...
3985 23:45:59.702785 ==
3986 23:45:59.705938 Dram Type= 6, Freq= 0, CH_0, rank 0
3987 23:45:59.709639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3988 23:45:59.709722 ==
3989 23:45:59.712456 Write leveling (Byte 0): 32 => 32
3990 23:45:59.715479 Write leveling (Byte 1): 29 => 29
3991 23:45:59.719026 DramcWriteLeveling(PI) end<-----
3992 23:45:59.719108
3993 23:45:59.719173 ==
3994 23:45:59.722212 Dram Type= 6, Freq= 0, CH_0, rank 0
3995 23:45:59.726159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3996 23:45:59.726242 ==
3997 23:45:59.728882 [Gating] SW mode calibration
3998 23:45:59.735428 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3999 23:45:59.742279 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4000 23:45:59.745597 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4001 23:45:59.748834 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 23:45:59.756012 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 23:45:59.758402 0 9 12 | B1->B0 | 3333 3131 | 1 0 | (1 1) (0 1)
4004 23:45:59.761984 0 9 16 | B1->B0 | 2f2f 2a2a | 0 0 | (1 0) (0 0)
4005 23:45:59.768580 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4006 23:45:59.771542 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4007 23:45:59.774832 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 23:45:59.781805 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 23:45:59.785874 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 23:45:59.788255 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 23:45:59.794593 0 10 12 | B1->B0 | 2525 2828 | 1 0 | (0 0) (1 1)
4012 23:45:59.798847 0 10 16 | B1->B0 | 3939 4141 | 0 0 | (0 0) (0 0)
4013 23:45:59.801682 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 23:45:59.807845 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 23:45:59.811577 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 23:45:59.814611 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 23:45:59.821123 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 23:45:59.824480 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 23:45:59.827908 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 23:45:59.834282 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4021 23:45:59.837632 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 23:45:59.840771 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 23:45:59.848494 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 23:45:59.850858 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 23:45:59.857177 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 23:45:59.860607 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 23:45:59.863775 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 23:45:59.870606 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 23:45:59.873447 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 23:45:59.877156 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 23:45:59.883630 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 23:45:59.887081 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 23:45:59.890163 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 23:45:59.896434 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 23:45:59.899939 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4036 23:45:59.903037 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4037 23:45:59.906536 Total UI for P1: 0, mck2ui 16
4038 23:45:59.910042 best dqsien dly found for B0: ( 0, 13, 12)
4039 23:45:59.913311 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4040 23:45:59.916138 Total UI for P1: 0, mck2ui 16
4041 23:45:59.919629 best dqsien dly found for B1: ( 0, 13, 14)
4042 23:45:59.926618 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4043 23:45:59.929425 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4044 23:45:59.929507
4045 23:45:59.932935 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4046 23:45:59.936228 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4047 23:45:59.940067 [Gating] SW calibration Done
4048 23:45:59.940149 ==
4049 23:45:59.942690 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 23:45:59.946649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 23:45:59.946732 ==
4052 23:45:59.949145 RX Vref Scan: 0
4053 23:45:59.949227
4054 23:45:59.949312 RX Vref 0 -> 0, step: 1
4055 23:45:59.949374
4056 23:45:59.953203 RX Delay -230 -> 252, step: 16
4057 23:45:59.959270 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4058 23:45:59.962665 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4059 23:45:59.965925 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4060 23:45:59.969501 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4061 23:45:59.972469 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4062 23:45:59.979147 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4063 23:45:59.982445 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4064 23:45:59.985533 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4065 23:45:59.988791 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4066 23:45:59.995395 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4067 23:45:59.998897 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4068 23:46:00.001664 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4069 23:46:00.005290 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4070 23:46:00.011485 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4071 23:46:00.015374 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4072 23:46:00.018264 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4073 23:46:00.018345 ==
4074 23:46:00.021680 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 23:46:00.028143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 23:46:00.028227 ==
4077 23:46:00.028292 DQS Delay:
4078 23:46:00.028352 DQS0 = 0, DQS1 = 0
4079 23:46:00.031384 DQM Delay:
4080 23:46:00.031465 DQM0 = 45, DQM1 = 36
4081 23:46:00.034993 DQ Delay:
4082 23:46:00.037849 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4083 23:46:00.041297 DQ4 =41, DQ5 =41, DQ6 =57, DQ7 =57
4084 23:46:00.044695 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =41
4085 23:46:00.047781 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4086 23:46:00.047862
4087 23:46:00.047926
4088 23:46:00.047986 ==
4089 23:46:00.051729 Dram Type= 6, Freq= 0, CH_0, rank 0
4090 23:46:00.054282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4091 23:46:00.054364 ==
4092 23:46:00.054428
4093 23:46:00.054486
4094 23:46:00.057663 TX Vref Scan disable
4095 23:46:00.060945 == TX Byte 0 ==
4096 23:46:00.064356 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4097 23:46:00.067613 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4098 23:46:00.071225 == TX Byte 1 ==
4099 23:46:00.074971 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4100 23:46:00.077508 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4101 23:46:00.077589 ==
4102 23:46:00.080879 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 23:46:00.084351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 23:46:00.087472 ==
4105 23:46:00.087554
4106 23:46:00.087617
4107 23:46:00.087677 TX Vref Scan disable
4108 23:46:00.091399 == TX Byte 0 ==
4109 23:46:00.094563 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4110 23:46:00.100908 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4111 23:46:00.100990 == TX Byte 1 ==
4112 23:46:00.104529 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4113 23:46:00.111304 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4114 23:46:00.111386
4115 23:46:00.111451 [DATLAT]
4116 23:46:00.111510 Freq=600, CH0 RK0
4117 23:46:00.111568
4118 23:46:00.114402 DATLAT Default: 0x9
4119 23:46:00.117439 0, 0xFFFF, sum = 0
4120 23:46:00.117521 1, 0xFFFF, sum = 0
4121 23:46:00.120821 2, 0xFFFF, sum = 0
4122 23:46:00.120903 3, 0xFFFF, sum = 0
4123 23:46:00.123940 4, 0xFFFF, sum = 0
4124 23:46:00.124023 5, 0xFFFF, sum = 0
4125 23:46:00.127318 6, 0xFFFF, sum = 0
4126 23:46:00.127400 7, 0xFFFF, sum = 0
4127 23:46:00.130722 8, 0x0, sum = 1
4128 23:46:00.130805 9, 0x0, sum = 2
4129 23:46:00.134005 10, 0x0, sum = 3
4130 23:46:00.134088 11, 0x0, sum = 4
4131 23:46:00.134153 best_step = 9
4132 23:46:00.134213
4133 23:46:00.137445 ==
4134 23:46:00.140470 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 23:46:00.143656 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 23:46:00.143737 ==
4137 23:46:00.143801 RX Vref Scan: 1
4138 23:46:00.143862
4139 23:46:00.147353 RX Vref 0 -> 0, step: 1
4140 23:46:00.147435
4141 23:46:00.150480 RX Delay -195 -> 252, step: 8
4142 23:46:00.150561
4143 23:46:00.153770 Set Vref, RX VrefLevel [Byte0]: 57
4144 23:46:00.156873 [Byte1]: 51
4145 23:46:00.156954
4146 23:46:00.160367 Final RX Vref Byte 0 = 57 to rank0
4147 23:46:00.163431 Final RX Vref Byte 1 = 51 to rank0
4148 23:46:00.167370 Final RX Vref Byte 0 = 57 to rank1
4149 23:46:00.169981 Final RX Vref Byte 1 = 51 to rank1==
4150 23:46:00.173614 Dram Type= 6, Freq= 0, CH_0, rank 0
4151 23:46:00.180170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4152 23:46:00.180252 ==
4153 23:46:00.180315 DQS Delay:
4154 23:46:00.180375 DQS0 = 0, DQS1 = 0
4155 23:46:00.183172 DQM Delay:
4156 23:46:00.183253 DQM0 = 44, DQM1 = 36
4157 23:46:00.186638 DQ Delay:
4158 23:46:00.190104 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4159 23:46:00.193204 DQ4 =48, DQ5 =36, DQ6 =56, DQ7 =48
4160 23:46:00.197081 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =32
4161 23:46:00.199703 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4162 23:46:00.199784
4163 23:46:00.199848
4164 23:46:00.206579 [DQSOSCAuto] RK0, (LSB)MR18= 0x5148, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4165 23:46:00.209466 CH0 RK0: MR19=808, MR18=5148
4166 23:46:00.216262 CH0_RK0: MR19=0x808, MR18=0x5148, DQSOSC=394, MR23=63, INC=168, DEC=112
4167 23:46:00.216348
4168 23:46:00.219531 ----->DramcWriteLeveling(PI) begin...
4169 23:46:00.219615 ==
4170 23:46:00.222814 Dram Type= 6, Freq= 0, CH_0, rank 1
4171 23:46:00.226357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4172 23:46:00.226438 ==
4173 23:46:00.229573 Write leveling (Byte 0): 31 => 31
4174 23:46:00.232697 Write leveling (Byte 1): 31 => 31
4175 23:46:00.236195 DramcWriteLeveling(PI) end<-----
4176 23:46:00.236275
4177 23:46:00.236340 ==
4178 23:46:00.239363 Dram Type= 6, Freq= 0, CH_0, rank 1
4179 23:46:00.242929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 23:46:00.246109 ==
4181 23:46:00.246190 [Gating] SW mode calibration
4182 23:46:00.255821 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4183 23:46:00.259295 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4184 23:46:00.262173 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4185 23:46:00.268851 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4186 23:46:00.272126 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4187 23:46:00.275325 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
4188 23:46:00.281818 0 9 16 | B1->B0 | 2f2f 2525 | 1 1 | (1 0) (0 0)
4189 23:46:00.285364 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4190 23:46:00.288425 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 23:46:00.295146 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 23:46:00.298255 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 23:46:00.301771 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 23:46:00.308127 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4195 23:46:00.311689 0 10 12 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
4196 23:46:00.318090 0 10 16 | B1->B0 | 3a3a 4444 | 0 0 | (0 0) (0 0)
4197 23:46:00.321173 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 23:46:00.324456 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 23:46:00.331657 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 23:46:00.334355 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 23:46:00.338165 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 23:46:00.344560 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 23:46:00.347712 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4204 23:46:00.350800 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 23:46:00.357162 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 23:46:00.360495 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 23:46:00.363778 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 23:46:00.370786 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 23:46:00.373848 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 23:46:00.376961 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 23:46:00.383694 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 23:46:00.387304 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 23:46:00.390169 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 23:46:00.396892 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 23:46:00.400045 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 23:46:00.403675 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 23:46:00.409820 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 23:46:00.413267 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 23:46:00.416421 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4220 23:46:00.423092 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4221 23:46:00.423175 Total UI for P1: 0, mck2ui 16
4222 23:46:00.429585 best dqsien dly found for B0: ( 0, 13, 12)
4223 23:46:00.433174 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4224 23:46:00.436239 Total UI for P1: 0, mck2ui 16
4225 23:46:00.439722 best dqsien dly found for B1: ( 0, 13, 14)
4226 23:46:00.443208 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4227 23:46:00.446565 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4228 23:46:00.446646
4229 23:46:00.449254 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4230 23:46:00.452725 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4231 23:46:00.455949 [Gating] SW calibration Done
4232 23:46:00.456030 ==
4233 23:46:00.459689 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 23:46:00.466112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 23:46:00.466220 ==
4236 23:46:00.466313 RX Vref Scan: 0
4237 23:46:00.466401
4238 23:46:00.469476 RX Vref 0 -> 0, step: 1
4239 23:46:00.469557
4240 23:46:00.472697 RX Delay -230 -> 252, step: 16
4241 23:46:00.476496 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4242 23:46:00.479231 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4243 23:46:00.482559 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4244 23:46:00.489216 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4245 23:46:00.492600 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4246 23:46:00.495885 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4247 23:46:00.499218 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4248 23:46:00.505754 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4249 23:46:00.508927 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4250 23:46:00.512175 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4251 23:46:00.515272 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4252 23:46:00.521834 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4253 23:46:00.525624 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4254 23:46:00.528423 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4255 23:46:00.532009 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4256 23:46:00.538550 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4257 23:46:00.538631 ==
4258 23:46:00.541607 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 23:46:00.544904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 23:46:00.544987 ==
4261 23:46:00.545052 DQS Delay:
4262 23:46:00.548319 DQS0 = 0, DQS1 = 0
4263 23:46:00.548400 DQM Delay:
4264 23:46:00.551539 DQM0 = 46, DQM1 = 37
4265 23:46:00.551620 DQ Delay:
4266 23:46:00.554687 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4267 23:46:00.558382 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4268 23:46:00.561131 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4269 23:46:00.564799 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4270 23:46:00.564880
4271 23:46:00.564944
4272 23:46:00.565003 ==
4273 23:46:00.567935 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 23:46:00.571121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 23:46:00.571202 ==
4276 23:46:00.574409
4277 23:46:00.574489
4278 23:46:00.574553 TX Vref Scan disable
4279 23:46:00.577895 == TX Byte 0 ==
4280 23:46:00.581196 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4281 23:46:00.584676 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4282 23:46:00.588352 == TX Byte 1 ==
4283 23:46:00.591121 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4284 23:46:00.594872 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4285 23:46:00.598197 ==
4286 23:46:00.601080 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 23:46:00.604230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 23:46:00.604312 ==
4289 23:46:00.604376
4290 23:46:00.604436
4291 23:46:00.607700 TX Vref Scan disable
4292 23:46:00.607781 == TX Byte 0 ==
4293 23:46:00.614460 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4294 23:46:00.617371 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4295 23:46:00.617453 == TX Byte 1 ==
4296 23:46:00.624021 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4297 23:46:00.627379 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4298 23:46:00.627461
4299 23:46:00.627525 [DATLAT]
4300 23:46:00.630679 Freq=600, CH0 RK1
4301 23:46:00.630761
4302 23:46:00.630825 DATLAT Default: 0x9
4303 23:46:00.634087 0, 0xFFFF, sum = 0
4304 23:46:00.634211 1, 0xFFFF, sum = 0
4305 23:46:00.637044 2, 0xFFFF, sum = 0
4306 23:46:00.640509 3, 0xFFFF, sum = 0
4307 23:46:00.640591 4, 0xFFFF, sum = 0
4308 23:46:00.644268 5, 0xFFFF, sum = 0
4309 23:46:00.644350 6, 0xFFFF, sum = 0
4310 23:46:00.647186 7, 0xFFFF, sum = 0
4311 23:46:00.647268 8, 0x0, sum = 1
4312 23:46:00.647334 9, 0x0, sum = 2
4313 23:46:00.651164 10, 0x0, sum = 3
4314 23:46:00.651247 11, 0x0, sum = 4
4315 23:46:00.653571 best_step = 9
4316 23:46:00.653651
4317 23:46:00.653729 ==
4318 23:46:00.657192 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 23:46:00.660446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 23:46:00.660528 ==
4321 23:46:00.663587 RX Vref Scan: 0
4322 23:46:00.663669
4323 23:46:00.663732 RX Vref 0 -> 0, step: 1
4324 23:46:00.666792
4325 23:46:00.666873 RX Delay -179 -> 252, step: 8
4326 23:46:00.674578 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4327 23:46:00.677675 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4328 23:46:00.681007 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4329 23:46:00.684580 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4330 23:46:00.691146 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4331 23:46:00.694350 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4332 23:46:00.697827 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4333 23:46:00.700669 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4334 23:46:00.704188 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4335 23:46:00.710484 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4336 23:46:00.713885 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4337 23:46:00.717003 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4338 23:46:00.723714 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4339 23:46:00.727138 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4340 23:46:00.730444 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4341 23:46:00.733938 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4342 23:46:00.734064 ==
4343 23:46:00.737103 Dram Type= 6, Freq= 0, CH_0, rank 1
4344 23:46:00.744050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 23:46:00.744133 ==
4346 23:46:00.744198 DQS Delay:
4347 23:46:00.744258 DQS0 = 0, DQS1 = 0
4348 23:46:00.747330 DQM Delay:
4349 23:46:00.747412 DQM0 = 43, DQM1 = 37
4350 23:46:00.750253 DQ Delay:
4351 23:46:00.753463 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4352 23:46:00.756848 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =48
4353 23:46:00.759935 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =32
4354 23:46:00.763595 DQ12 =40, DQ13 =44, DQ14 =48, DQ15 =44
4355 23:46:00.763676
4356 23:46:00.763740
4357 23:46:00.770653 [DQSOSCAuto] RK1, (LSB)MR18= 0x403c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4358 23:46:00.773164 CH0 RK1: MR19=808, MR18=403C
4359 23:46:00.779702 CH0_RK1: MR19=0x808, MR18=0x403C, DQSOSC=397, MR23=63, INC=166, DEC=110
4360 23:46:00.783211 [RxdqsGatingPostProcess] freq 600
4361 23:46:00.786555 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4362 23:46:00.789490 Pre-setting of DQS Precalculation
4363 23:46:00.796674 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4364 23:46:00.796757 ==
4365 23:46:00.799882 Dram Type= 6, Freq= 0, CH_1, rank 0
4366 23:46:00.803444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 23:46:00.803526 ==
4368 23:46:00.809998 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 23:46:00.816048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4370 23:46:00.819069 [CA 0] Center 35 (5~66) winsize 62
4371 23:46:00.823144 [CA 1] Center 36 (6~66) winsize 61
4372 23:46:00.826097 [CA 2] Center 34 (4~65) winsize 62
4373 23:46:00.828966 [CA 3] Center 34 (3~65) winsize 63
4374 23:46:00.832796 [CA 4] Center 34 (4~65) winsize 62
4375 23:46:00.835822 [CA 5] Center 34 (3~65) winsize 63
4376 23:46:00.835903
4377 23:46:00.839054 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4378 23:46:00.839136
4379 23:46:00.842610 [CATrainingPosCal] consider 1 rank data
4380 23:46:00.846226 u2DelayCellTimex100 = 270/100 ps
4381 23:46:00.848809 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4382 23:46:00.852369 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4383 23:46:00.855534 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4384 23:46:00.858839 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4385 23:46:00.862317 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4386 23:46:00.868633 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4387 23:46:00.868715
4388 23:46:00.871821 CA PerBit enable=1, Macro0, CA PI delay=34
4389 23:46:00.871903
4390 23:46:00.875051 [CBTSetCACLKResult] CA Dly = 34
4391 23:46:00.875132 CS Dly: 5 (0~36)
4392 23:46:00.875196 ==
4393 23:46:00.878581 Dram Type= 6, Freq= 0, CH_1, rank 1
4394 23:46:00.881630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 23:46:00.885674 ==
4396 23:46:00.888381 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4397 23:46:00.895093 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4398 23:46:00.898038 [CA 0] Center 35 (5~66) winsize 62
4399 23:46:00.901430 [CA 1] Center 35 (5~66) winsize 62
4400 23:46:00.904689 [CA 2] Center 34 (4~65) winsize 62
4401 23:46:00.908016 [CA 3] Center 34 (3~65) winsize 63
4402 23:46:00.911132 [CA 4] Center 34 (3~65) winsize 63
4403 23:46:00.914500 [CA 5] Center 34 (3~65) winsize 63
4404 23:46:00.914582
4405 23:46:00.917862 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4406 23:46:00.917943
4407 23:46:00.921039 [CATrainingPosCal] consider 2 rank data
4408 23:46:00.924828 u2DelayCellTimex100 = 270/100 ps
4409 23:46:00.927910 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4410 23:46:00.931392 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4411 23:46:00.937591 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4412 23:46:00.941315 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4413 23:46:00.944263 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4414 23:46:00.947810 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4415 23:46:00.947892
4416 23:46:00.950886 CA PerBit enable=1, Macro0, CA PI delay=34
4417 23:46:00.950968
4418 23:46:00.953955 [CBTSetCACLKResult] CA Dly = 34
4419 23:46:00.954063 CS Dly: 5 (0~37)
4420 23:46:00.954159
4421 23:46:00.960834 ----->DramcWriteLeveling(PI) begin...
4422 23:46:00.960918 ==
4423 23:46:00.964162 Dram Type= 6, Freq= 0, CH_1, rank 0
4424 23:46:00.967393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 23:46:00.967484 ==
4426 23:46:00.970732 Write leveling (Byte 0): 29 => 29
4427 23:46:00.973704 Write leveling (Byte 1): 30 => 30
4428 23:46:00.976982 DramcWriteLeveling(PI) end<-----
4429 23:46:00.977079
4430 23:46:00.977158 ==
4431 23:46:00.980282 Dram Type= 6, Freq= 0, CH_1, rank 0
4432 23:46:00.983934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4433 23:46:00.984016 ==
4434 23:46:00.987328 [Gating] SW mode calibration
4435 23:46:00.993655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4436 23:46:01.000108 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4437 23:46:01.003780 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4438 23:46:01.007368 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 23:46:01.013651 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4440 23:46:01.016736 0 9 12 | B1->B0 | 3030 2f2f | 0 1 | (0 0) (1 0)
4441 23:46:01.020050 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
4442 23:46:01.026686 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4443 23:46:01.029929 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4444 23:46:01.033384 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 23:46:01.039425 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 23:46:01.042924 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 23:46:01.046161 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4448 23:46:01.053557 0 10 12 | B1->B0 | 3535 3636 | 0 0 | (1 1) (0 0)
4449 23:46:01.056373 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 23:46:01.059647 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4451 23:46:01.065817 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 23:46:01.069153 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 23:46:01.072504 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 23:46:01.078921 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 23:46:01.082339 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 23:46:01.085237 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 23:46:01.092512 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 23:46:01.095116 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 23:46:01.099278 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 23:46:01.105687 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 23:46:01.108676 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 23:46:01.111655 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 23:46:01.118159 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 23:46:01.121537 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 23:46:01.125077 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 23:46:01.131613 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 23:46:01.135115 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 23:46:01.138212 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 23:46:01.145460 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 23:46:01.148342 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 23:46:01.151615 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 23:46:01.157934 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 23:46:01.161050 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4474 23:46:01.164972 Total UI for P1: 0, mck2ui 16
4475 23:46:01.167801 best dqsien dly found for B0: ( 0, 13, 14)
4476 23:46:01.171223 Total UI for P1: 0, mck2ui 16
4477 23:46:01.174432 best dqsien dly found for B1: ( 0, 13, 14)
4478 23:46:01.177907 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4479 23:46:01.181102 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4480 23:46:01.181184
4481 23:46:01.184423 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4482 23:46:01.191392 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4483 23:46:01.191513 [Gating] SW calibration Done
4484 23:46:01.191606 ==
4485 23:46:01.194156 Dram Type= 6, Freq= 0, CH_1, rank 0
4486 23:46:01.200900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4487 23:46:01.201008 ==
4488 23:46:01.201101 RX Vref Scan: 0
4489 23:46:01.201192
4490 23:46:01.204205 RX Vref 0 -> 0, step: 1
4491 23:46:01.204285
4492 23:46:01.207457 RX Delay -230 -> 252, step: 16
4493 23:46:01.211417 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4494 23:46:01.214027 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4495 23:46:01.220901 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4496 23:46:01.223973 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4497 23:46:01.227211 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4498 23:46:01.230412 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4499 23:46:01.234237 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4500 23:46:01.240408 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4501 23:46:01.243849 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4502 23:46:01.247242 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4503 23:46:01.250469 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4504 23:46:01.256955 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4505 23:46:01.260324 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4506 23:46:01.263667 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4507 23:46:01.267064 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4508 23:46:01.273267 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4509 23:46:01.273363 ==
4510 23:46:01.276561 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 23:46:01.279934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 23:46:01.280041 ==
4513 23:46:01.280133 DQS Delay:
4514 23:46:01.283189 DQS0 = 0, DQS1 = 0
4515 23:46:01.283274 DQM Delay:
4516 23:46:01.286575 DQM0 = 43, DQM1 = 39
4517 23:46:01.286678 DQ Delay:
4518 23:46:01.290059 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4519 23:46:01.293071 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4520 23:46:01.296767 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4521 23:46:01.300124 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4522 23:46:01.300205
4523 23:46:01.300268
4524 23:46:01.300328 ==
4525 23:46:01.303207 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 23:46:01.306497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 23:46:01.309755 ==
4528 23:46:01.309836
4529 23:46:01.309900
4530 23:46:01.309960 TX Vref Scan disable
4531 23:46:01.312929 == TX Byte 0 ==
4532 23:46:01.316673 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4533 23:46:01.322735 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4534 23:46:01.322869 == TX Byte 1 ==
4535 23:46:01.326195 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4536 23:46:01.332930 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4537 23:46:01.333012 ==
4538 23:46:01.336066 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 23:46:01.339408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 23:46:01.339490 ==
4541 23:46:01.339555
4542 23:46:01.339614
4543 23:46:01.342399 TX Vref Scan disable
4544 23:46:01.346072 == TX Byte 0 ==
4545 23:46:01.349512 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4546 23:46:01.352502 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4547 23:46:01.355653 == TX Byte 1 ==
4548 23:46:01.359441 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4549 23:46:01.362804 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4550 23:46:01.362886
4551 23:46:01.362954 [DATLAT]
4552 23:46:01.365995 Freq=600, CH1 RK0
4553 23:46:01.366076
4554 23:46:01.369440 DATLAT Default: 0x9
4555 23:46:01.369521 0, 0xFFFF, sum = 0
4556 23:46:01.372388 1, 0xFFFF, sum = 0
4557 23:46:01.372470 2, 0xFFFF, sum = 0
4558 23:46:01.375588 3, 0xFFFF, sum = 0
4559 23:46:01.375671 4, 0xFFFF, sum = 0
4560 23:46:01.378762 5, 0xFFFF, sum = 0
4561 23:46:01.378844 6, 0xFFFF, sum = 0
4562 23:46:01.381973 7, 0xFFFF, sum = 0
4563 23:46:01.382055 8, 0x0, sum = 1
4564 23:46:01.385116 9, 0x0, sum = 2
4565 23:46:01.385197 10, 0x0, sum = 3
4566 23:46:01.388617 11, 0x0, sum = 4
4567 23:46:01.388699 best_step = 9
4568 23:46:01.388764
4569 23:46:01.388824 ==
4570 23:46:01.391911 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 23:46:01.395708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 23:46:01.395790 ==
4573 23:46:01.398590 RX Vref Scan: 1
4574 23:46:01.398670
4575 23:46:01.401649 RX Vref 0 -> 0, step: 1
4576 23:46:01.401730
4577 23:46:01.401794 RX Delay -179 -> 252, step: 8
4578 23:46:01.405179
4579 23:46:01.405293 Set Vref, RX VrefLevel [Byte0]: 51
4580 23:46:01.408287 [Byte1]: 51
4581 23:46:01.413374
4582 23:46:01.413455 Final RX Vref Byte 0 = 51 to rank0
4583 23:46:01.416846 Final RX Vref Byte 1 = 51 to rank0
4584 23:46:01.419918 Final RX Vref Byte 0 = 51 to rank1
4585 23:46:01.423440 Final RX Vref Byte 1 = 51 to rank1==
4586 23:46:01.426406 Dram Type= 6, Freq= 0, CH_1, rank 0
4587 23:46:01.433123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 23:46:01.433205 ==
4589 23:46:01.433290 DQS Delay:
4590 23:46:01.433365 DQS0 = 0, DQS1 = 0
4591 23:46:01.436370 DQM Delay:
4592 23:46:01.436450 DQM0 = 42, DQM1 = 34
4593 23:46:01.440063 DQ Delay:
4594 23:46:01.443129 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4595 23:46:01.446244 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4596 23:46:01.449956 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4597 23:46:01.452889 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4598 23:46:01.452971
4599 23:46:01.453062
4600 23:46:01.459797 [DQSOSCAuto] RK0, (LSB)MR18= 0x354f, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
4601 23:46:01.462950 CH1 RK0: MR19=808, MR18=354F
4602 23:46:01.469546 CH1_RK0: MR19=0x808, MR18=0x354F, DQSOSC=394, MR23=63, INC=168, DEC=112
4603 23:46:01.469627
4604 23:46:01.473246 ----->DramcWriteLeveling(PI) begin...
4605 23:46:01.473364 ==
4606 23:46:01.476220 Dram Type= 6, Freq= 0, CH_1, rank 1
4607 23:46:01.479399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4608 23:46:01.479498 ==
4609 23:46:01.483098 Write leveling (Byte 0): 29 => 29
4610 23:46:01.486165 Write leveling (Byte 1): 29 => 29
4611 23:46:01.489809 DramcWriteLeveling(PI) end<-----
4612 23:46:01.489890
4613 23:46:01.489954 ==
4614 23:46:01.492720 Dram Type= 6, Freq= 0, CH_1, rank 1
4615 23:46:01.495783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 23:46:01.499157 ==
4617 23:46:01.499236 [Gating] SW mode calibration
4618 23:46:01.505742 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4619 23:46:01.512573 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4620 23:46:01.515640 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4621 23:46:01.522252 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4622 23:46:01.525574 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
4623 23:46:01.529145 0 9 12 | B1->B0 | 3131 2a2a | 0 0 | (0 1) (1 0)
4624 23:46:01.535718 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4625 23:46:01.538713 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4626 23:46:01.542241 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 23:46:01.548657 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 23:46:01.552646 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 23:46:01.555110 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 23:46:01.561663 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4631 23:46:01.565178 0 10 12 | B1->B0 | 2f2f 3939 | 0 0 | (1 1) (0 0)
4632 23:46:01.568279 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 23:46:01.575181 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4634 23:46:01.578251 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 23:46:01.581604 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 23:46:01.587911 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 23:46:01.591253 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 23:46:01.595040 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4639 23:46:01.601173 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4640 23:46:01.604481 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4641 23:46:01.607671 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4642 23:46:01.614362 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 23:46:01.617449 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 23:46:01.620684 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 23:46:01.627815 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 23:46:01.630701 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 23:46:01.634390 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 23:46:01.641153 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 23:46:01.644149 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 23:46:01.647641 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 23:46:01.654349 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 23:46:01.657474 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 23:46:01.660376 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 23:46:01.667323 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 23:46:01.670518 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4656 23:46:01.673911 Total UI for P1: 0, mck2ui 16
4657 23:46:01.676835 best dqsien dly found for B0: ( 0, 13, 10)
4658 23:46:01.680417 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 23:46:01.684453 Total UI for P1: 0, mck2ui 16
4660 23:46:01.686636 best dqsien dly found for B1: ( 0, 13, 12)
4661 23:46:01.690496 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4662 23:46:01.696637 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4663 23:46:01.696712
4664 23:46:01.700088 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4665 23:46:01.703482 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4666 23:46:01.706779 [Gating] SW calibration Done
4667 23:46:01.706857 ==
4668 23:46:01.710211 Dram Type= 6, Freq= 0, CH_1, rank 1
4669 23:46:01.713220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4670 23:46:01.713351 ==
4671 23:46:01.716572 RX Vref Scan: 0
4672 23:46:01.716653
4673 23:46:01.716721 RX Vref 0 -> 0, step: 1
4674 23:46:01.716786
4675 23:46:01.719592 RX Delay -230 -> 252, step: 16
4676 23:46:01.723203 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4677 23:46:01.729730 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4678 23:46:01.732753 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4679 23:46:01.736381 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4680 23:46:01.739732 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4681 23:46:01.746227 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4682 23:46:01.749963 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4683 23:46:01.752985 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4684 23:46:01.756273 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4685 23:46:01.763158 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4686 23:46:01.765677 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4687 23:46:01.769054 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4688 23:46:01.772406 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4689 23:46:01.778887 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4690 23:46:01.782048 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4691 23:46:01.785764 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4692 23:46:01.785844 ==
4693 23:46:01.788735 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 23:46:01.792033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 23:46:01.792114 ==
4696 23:46:01.795400 DQS Delay:
4697 23:46:01.795530 DQS0 = 0, DQS1 = 0
4698 23:46:01.798543 DQM Delay:
4699 23:46:01.798624 DQM0 = 42, DQM1 = 39
4700 23:46:01.802301 DQ Delay:
4701 23:46:01.802381 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4702 23:46:01.805576 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4703 23:46:01.808598 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4704 23:46:01.811998 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4705 23:46:01.812101
4706 23:46:01.815750
4707 23:46:01.815856 ==
4708 23:46:01.818245 Dram Type= 6, Freq= 0, CH_1, rank 1
4709 23:46:01.821926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4710 23:46:01.822008 ==
4711 23:46:01.822072
4712 23:46:01.822131
4713 23:46:01.824810 TX Vref Scan disable
4714 23:46:01.824891 == TX Byte 0 ==
4715 23:46:01.831448 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4716 23:46:01.834766 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4717 23:46:01.834851 == TX Byte 1 ==
4718 23:46:01.841875 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4719 23:46:01.844796 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4720 23:46:01.844900 ==
4721 23:46:01.848545 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 23:46:01.851366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 23:46:01.851440 ==
4724 23:46:01.851502
4725 23:46:01.854649
4726 23:46:01.854730 TX Vref Scan disable
4727 23:46:01.857957 == TX Byte 0 ==
4728 23:46:01.861381 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4729 23:46:01.868092 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4730 23:46:01.868174 == TX Byte 1 ==
4731 23:46:01.871306 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4732 23:46:01.877873 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4733 23:46:01.877954
4734 23:46:01.878018 [DATLAT]
4735 23:46:01.878099 Freq=600, CH1 RK1
4736 23:46:01.878160
4737 23:46:01.881135 DATLAT Default: 0x9
4738 23:46:01.884808 0, 0xFFFF, sum = 0
4739 23:46:01.884884 1, 0xFFFF, sum = 0
4740 23:46:01.887711 2, 0xFFFF, sum = 0
4741 23:46:01.887783 3, 0xFFFF, sum = 0
4742 23:46:01.890715 4, 0xFFFF, sum = 0
4743 23:46:01.890797 5, 0xFFFF, sum = 0
4744 23:46:01.894150 6, 0xFFFF, sum = 0
4745 23:46:01.894232 7, 0xFFFF, sum = 0
4746 23:46:01.898013 8, 0x0, sum = 1
4747 23:46:01.898095 9, 0x0, sum = 2
4748 23:46:01.900590 10, 0x0, sum = 3
4749 23:46:01.900704 11, 0x0, sum = 4
4750 23:46:01.900773 best_step = 9
4751 23:46:01.900833
4752 23:46:01.903962 ==
4753 23:46:01.907335 Dram Type= 6, Freq= 0, CH_1, rank 1
4754 23:46:01.910606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4755 23:46:01.910688 ==
4756 23:46:01.910752 RX Vref Scan: 0
4757 23:46:01.910814
4758 23:46:01.913966 RX Vref 0 -> 0, step: 1
4759 23:46:01.914062
4760 23:46:01.917333 RX Delay -179 -> 252, step: 8
4761 23:46:01.923852 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4762 23:46:01.927158 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4763 23:46:01.930586 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4764 23:46:01.933473 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4765 23:46:01.940042 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4766 23:46:01.943546 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4767 23:46:01.947196 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4768 23:46:01.950231 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4769 23:46:01.953678 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4770 23:46:01.959921 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4771 23:46:01.963736 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4772 23:46:01.966464 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4773 23:46:01.969941 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4774 23:46:01.977117 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4775 23:46:01.980060 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4776 23:46:01.983125 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4777 23:46:01.983207 ==
4778 23:46:01.986352 Dram Type= 6, Freq= 0, CH_1, rank 1
4779 23:46:01.989681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4780 23:46:01.993061 ==
4781 23:46:01.993149 DQS Delay:
4782 23:46:01.993214 DQS0 = 0, DQS1 = 0
4783 23:46:01.996316 DQM Delay:
4784 23:46:01.996423 DQM0 = 37, DQM1 = 35
4785 23:46:01.999803 DQ Delay:
4786 23:46:02.002890 DQ0 =40, DQ1 =36, DQ2 =24, DQ3 =36
4787 23:46:02.002976 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4788 23:46:02.006072 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4789 23:46:02.012906 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4790 23:46:02.013014
4791 23:46:02.013106
4792 23:46:02.019096 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4793 23:46:02.022760 CH1 RK1: MR19=808, MR18=3C61
4794 23:46:02.028937 CH1_RK1: MR19=0x808, MR18=0x3C61, DQSOSC=391, MR23=63, INC=171, DEC=114
4795 23:46:02.032275 [RxdqsGatingPostProcess] freq 600
4796 23:46:02.035720 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4797 23:46:02.038981 Pre-setting of DQS Precalculation
4798 23:46:02.045928 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4799 23:46:02.052708 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4800 23:46:02.058872 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4801 23:46:02.058968
4802 23:46:02.059032
4803 23:46:02.061774 [Calibration Summary] 1200 Mbps
4804 23:46:02.061909 CH 0, Rank 0
4805 23:46:02.066066 SW Impedance : PASS
4806 23:46:02.068344 DUTY Scan : NO K
4807 23:46:02.068425 ZQ Calibration : PASS
4808 23:46:02.071596 Jitter Meter : NO K
4809 23:46:02.075071 CBT Training : PASS
4810 23:46:02.075183 Write leveling : PASS
4811 23:46:02.078164 RX DQS gating : PASS
4812 23:46:02.081431 RX DQ/DQS(RDDQC) : PASS
4813 23:46:02.081533 TX DQ/DQS : PASS
4814 23:46:02.084846 RX DATLAT : PASS
4815 23:46:02.087918 RX DQ/DQS(Engine): PASS
4816 23:46:02.088021 TX OE : NO K
4817 23:46:02.091323 All Pass.
4818 23:46:02.091425
4819 23:46:02.091519 CH 0, Rank 1
4820 23:46:02.095004 SW Impedance : PASS
4821 23:46:02.095112 DUTY Scan : NO K
4822 23:46:02.098083 ZQ Calibration : PASS
4823 23:46:02.101381 Jitter Meter : NO K
4824 23:46:02.101490 CBT Training : PASS
4825 23:46:02.105117 Write leveling : PASS
4826 23:46:02.108285 RX DQS gating : PASS
4827 23:46:02.108372 RX DQ/DQS(RDDQC) : PASS
4828 23:46:02.111576 TX DQ/DQS : PASS
4829 23:46:02.114972 RX DATLAT : PASS
4830 23:46:02.115052 RX DQ/DQS(Engine): PASS
4831 23:46:02.117687 TX OE : NO K
4832 23:46:02.117790 All Pass.
4833 23:46:02.117884
4834 23:46:02.121138 CH 1, Rank 0
4835 23:46:02.121249 SW Impedance : PASS
4836 23:46:02.124392 DUTY Scan : NO K
4837 23:46:02.127654 ZQ Calibration : PASS
4838 23:46:02.127796 Jitter Meter : NO K
4839 23:46:02.130707 CBT Training : PASS
4840 23:46:02.134376 Write leveling : PASS
4841 23:46:02.134492 RX DQS gating : PASS
4842 23:46:02.137929 RX DQ/DQS(RDDQC) : PASS
4843 23:46:02.141032 TX DQ/DQS : PASS
4844 23:46:02.141144 RX DATLAT : PASS
4845 23:46:02.144606 RX DQ/DQS(Engine): PASS
4846 23:46:02.144712 TX OE : NO K
4847 23:46:02.147504 All Pass.
4848 23:46:02.147614
4849 23:46:02.147706 CH 1, Rank 1
4850 23:46:02.150692 SW Impedance : PASS
4851 23:46:02.150802 DUTY Scan : NO K
4852 23:46:02.154423 ZQ Calibration : PASS
4853 23:46:02.157381 Jitter Meter : NO K
4854 23:46:02.157492 CBT Training : PASS
4855 23:46:02.160738 Write leveling : PASS
4856 23:46:02.164344 RX DQS gating : PASS
4857 23:46:02.164436 RX DQ/DQS(RDDQC) : PASS
4858 23:46:02.167148 TX DQ/DQS : PASS
4859 23:46:02.170840 RX DATLAT : PASS
4860 23:46:02.170948 RX DQ/DQS(Engine): PASS
4861 23:46:02.173720 TX OE : NO K
4862 23:46:02.173821 All Pass.
4863 23:46:02.173910
4864 23:46:02.177154 DramC Write-DBI off
4865 23:46:02.180542 PER_BANK_REFRESH: Hybrid Mode
4866 23:46:02.180641 TX_TRACKING: ON
4867 23:46:02.190238 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4868 23:46:02.193524 [FAST_K] Save calibration result to emmc
4869 23:46:02.197588 dramc_set_vcore_voltage set vcore to 662500
4870 23:46:02.200249 Read voltage for 933, 3
4871 23:46:02.200345 Vio18 = 0
4872 23:46:02.200439 Vcore = 662500
4873 23:46:02.203626 Vdram = 0
4874 23:46:02.203730 Vddq = 0
4875 23:46:02.203835 Vmddr = 0
4876 23:46:02.210318 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4877 23:46:02.214072 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4878 23:46:02.217014 MEM_TYPE=3, freq_sel=17
4879 23:46:02.220113 sv_algorithm_assistance_LP4_1600
4880 23:46:02.223410 ============ PULL DRAM RESETB DOWN ============
4881 23:46:02.229814 ========== PULL DRAM RESETB DOWN end =========
4882 23:46:02.233153 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4883 23:46:02.236826 ===================================
4884 23:46:02.239782 LPDDR4 DRAM CONFIGURATION
4885 23:46:02.243092 ===================================
4886 23:46:02.243201 EX_ROW_EN[0] = 0x0
4887 23:46:02.246340 EX_ROW_EN[1] = 0x0
4888 23:46:02.246439 LP4Y_EN = 0x0
4889 23:46:02.249779 WORK_FSP = 0x0
4890 23:46:02.249932 WL = 0x3
4891 23:46:02.253607 RL = 0x3
4892 23:46:02.253726 BL = 0x2
4893 23:46:02.256965 RPST = 0x0
4894 23:46:02.257065 RD_PRE = 0x0
4895 23:46:02.259766 WR_PRE = 0x1
4896 23:46:02.262923 WR_PST = 0x0
4897 23:46:02.263029 DBI_WR = 0x0
4898 23:46:02.266903 DBI_RD = 0x0
4899 23:46:02.267007 OTF = 0x1
4900 23:46:02.270077 ===================================
4901 23:46:02.273481 ===================================
4902 23:46:02.276169 ANA top config
4903 23:46:02.279615 ===================================
4904 23:46:02.279722 DLL_ASYNC_EN = 0
4905 23:46:02.283098 ALL_SLAVE_EN = 1
4906 23:46:02.286138 NEW_RANK_MODE = 1
4907 23:46:02.289347 DLL_IDLE_MODE = 1
4908 23:46:02.289452 LP45_APHY_COMB_EN = 1
4909 23:46:02.292694 TX_ODT_DIS = 1
4910 23:46:02.296150 NEW_8X_MODE = 1
4911 23:46:02.299302 ===================================
4912 23:46:02.302198 ===================================
4913 23:46:02.305895 data_rate = 1866
4914 23:46:02.309014 CKR = 1
4915 23:46:02.312415 DQ_P2S_RATIO = 8
4916 23:46:02.316057 ===================================
4917 23:46:02.316166 CA_P2S_RATIO = 8
4918 23:46:02.318776 DQ_CA_OPEN = 0
4919 23:46:02.321967 DQ_SEMI_OPEN = 0
4920 23:46:02.325226 CA_SEMI_OPEN = 0
4921 23:46:02.328533 CA_FULL_RATE = 0
4922 23:46:02.331927 DQ_CKDIV4_EN = 1
4923 23:46:02.332032 CA_CKDIV4_EN = 1
4924 23:46:02.335840 CA_PREDIV_EN = 0
4925 23:46:02.338877 PH8_DLY = 0
4926 23:46:02.342334 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4927 23:46:02.345122 DQ_AAMCK_DIV = 4
4928 23:46:02.348213 CA_AAMCK_DIV = 4
4929 23:46:02.351471 CA_ADMCK_DIV = 4
4930 23:46:02.351577 DQ_TRACK_CA_EN = 0
4931 23:46:02.354734 CA_PICK = 933
4932 23:46:02.357965 CA_MCKIO = 933
4933 23:46:02.361698 MCKIO_SEMI = 0
4934 23:46:02.364703 PLL_FREQ = 3732
4935 23:46:02.368010 DQ_UI_PI_RATIO = 32
4936 23:46:02.371566 CA_UI_PI_RATIO = 0
4937 23:46:02.374845 ===================================
4938 23:46:02.377857 ===================================
4939 23:46:02.377971 memory_type:LPDDR4
4940 23:46:02.381149 GP_NUM : 10
4941 23:46:02.384616 SRAM_EN : 1
4942 23:46:02.384722 MD32_EN : 0
4943 23:46:02.388137 ===================================
4944 23:46:02.391336 [ANA_INIT] >>>>>>>>>>>>>>
4945 23:46:02.394765 <<<<<< [CONFIGURE PHASE]: ANA_TX
4946 23:46:02.397812 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4947 23:46:02.401020 ===================================
4948 23:46:02.404118 data_rate = 1866,PCW = 0X8f00
4949 23:46:02.407728 ===================================
4950 23:46:02.411431 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4951 23:46:02.414036 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4952 23:46:02.420623 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4953 23:46:02.423950 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4954 23:46:02.430928 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4955 23:46:02.434096 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4956 23:46:02.434177 [ANA_INIT] flow start
4957 23:46:02.437660 [ANA_INIT] PLL >>>>>>>>
4958 23:46:02.440516 [ANA_INIT] PLL <<<<<<<<
4959 23:46:02.440597 [ANA_INIT] MIDPI >>>>>>>>
4960 23:46:02.443734 [ANA_INIT] MIDPI <<<<<<<<
4961 23:46:02.447349 [ANA_INIT] DLL >>>>>>>>
4962 23:46:02.447429 [ANA_INIT] flow end
4963 23:46:02.450441 ============ LP4 DIFF to SE enter ============
4964 23:46:02.457147 ============ LP4 DIFF to SE exit ============
4965 23:46:02.457243 [ANA_INIT] <<<<<<<<<<<<<
4966 23:46:02.460406 [Flow] Enable top DCM control >>>>>
4967 23:46:02.463892 [Flow] Enable top DCM control <<<<<
4968 23:46:02.466856 Enable DLL master slave shuffle
4969 23:46:02.473434 ==============================================================
4970 23:46:02.477002 Gating Mode config
4971 23:46:02.479864 ==============================================================
4972 23:46:02.483163 Config description:
4973 23:46:02.492829 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4974 23:46:02.499377 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4975 23:46:02.502783 SELPH_MODE 0: By rank 1: By Phase
4976 23:46:02.509192 ==============================================================
4977 23:46:02.512923 GAT_TRACK_EN = 1
4978 23:46:02.516231 RX_GATING_MODE = 2
4979 23:46:02.519241 RX_GATING_TRACK_MODE = 2
4980 23:46:02.522660 SELPH_MODE = 1
4981 23:46:02.525602 PICG_EARLY_EN = 1
4982 23:46:02.528958 VALID_LAT_VALUE = 1
4983 23:46:02.532424 ==============================================================
4984 23:46:02.535338 Enter into Gating configuration >>>>
4985 23:46:02.539074 Exit from Gating configuration <<<<
4986 23:46:02.542437 Enter into DVFS_PRE_config >>>>>
4987 23:46:02.555379 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4988 23:46:02.555490 Exit from DVFS_PRE_config <<<<<
4989 23:46:02.558624 Enter into PICG configuration >>>>
4990 23:46:02.562276 Exit from PICG configuration <<<<
4991 23:46:02.565443 [RX_INPUT] configuration >>>>>
4992 23:46:02.569185 [RX_INPUT] configuration <<<<<
4993 23:46:02.574875 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4994 23:46:02.578866 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4995 23:46:02.585266 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4996 23:46:02.591600 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4997 23:46:02.598585 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4998 23:46:02.604907 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4999 23:46:02.608021 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5000 23:46:02.611186 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5001 23:46:02.615271 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5002 23:46:02.621173 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5003 23:46:02.624499 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5004 23:46:02.628027 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5005 23:46:02.631576 ===================================
5006 23:46:02.634151 LPDDR4 DRAM CONFIGURATION
5007 23:46:02.637950 ===================================
5008 23:46:02.641123 EX_ROW_EN[0] = 0x0
5009 23:46:02.641225 EX_ROW_EN[1] = 0x0
5010 23:46:02.643972 LP4Y_EN = 0x0
5011 23:46:02.644078 WORK_FSP = 0x0
5012 23:46:02.647867 WL = 0x3
5013 23:46:02.647942 RL = 0x3
5014 23:46:02.651101 BL = 0x2
5015 23:46:02.651198 RPST = 0x0
5016 23:46:02.654283 RD_PRE = 0x0
5017 23:46:02.654390 WR_PRE = 0x1
5018 23:46:02.657733 WR_PST = 0x0
5019 23:46:02.657806 DBI_WR = 0x0
5020 23:46:02.660896 DBI_RD = 0x0
5021 23:46:02.664278 OTF = 0x1
5022 23:46:02.667214 ===================================
5023 23:46:02.670583 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5024 23:46:02.674066 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5025 23:46:02.677644 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5026 23:46:02.680938 ===================================
5027 23:46:02.683943 LPDDR4 DRAM CONFIGURATION
5028 23:46:02.687160 ===================================
5029 23:46:02.690421 EX_ROW_EN[0] = 0x10
5030 23:46:02.690527 EX_ROW_EN[1] = 0x0
5031 23:46:02.693828 LP4Y_EN = 0x0
5032 23:46:02.693900 WORK_FSP = 0x0
5033 23:46:02.696774 WL = 0x3
5034 23:46:02.696846 RL = 0x3
5035 23:46:02.700799 BL = 0x2
5036 23:46:02.700906 RPST = 0x0
5037 23:46:02.703666 RD_PRE = 0x0
5038 23:46:02.703764 WR_PRE = 0x1
5039 23:46:02.707068 WR_PST = 0x0
5040 23:46:02.710702 DBI_WR = 0x0
5041 23:46:02.710802 DBI_RD = 0x0
5042 23:46:02.713561 OTF = 0x1
5043 23:46:02.716955 ===================================
5044 23:46:02.720040 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5045 23:46:02.725613 nWR fixed to 30
5046 23:46:02.728927 [ModeRegInit_LP4] CH0 RK0
5047 23:46:02.729026 [ModeRegInit_LP4] CH0 RK1
5048 23:46:02.732218 [ModeRegInit_LP4] CH1 RK0
5049 23:46:02.735326 [ModeRegInit_LP4] CH1 RK1
5050 23:46:02.735431 match AC timing 9
5051 23:46:02.741765 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5052 23:46:02.745369 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5053 23:46:02.748364 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5054 23:46:02.755311 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5055 23:46:02.758899 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5056 23:46:02.759005 ==
5057 23:46:02.761665 Dram Type= 6, Freq= 0, CH_0, rank 0
5058 23:46:02.765057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 23:46:02.765158 ==
5060 23:46:02.771688 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 23:46:02.778459 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5062 23:46:02.781490 [CA 0] Center 38 (7~69) winsize 63
5063 23:46:02.784807 [CA 1] Center 37 (7~68) winsize 62
5064 23:46:02.787946 [CA 2] Center 34 (4~65) winsize 62
5065 23:46:02.791274 [CA 3] Center 34 (4~65) winsize 62
5066 23:46:02.794480 [CA 4] Center 33 (3~64) winsize 62
5067 23:46:02.797995 [CA 5] Center 32 (2~63) winsize 62
5068 23:46:02.798077
5069 23:46:02.801411 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5070 23:46:02.801492
5071 23:46:02.804910 [CATrainingPosCal] consider 1 rank data
5072 23:46:02.807882 u2DelayCellTimex100 = 270/100 ps
5073 23:46:02.811095 CA0 delay=38 (7~69),Diff = 6 PI (37 cell)
5074 23:46:02.814381 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5075 23:46:02.817470 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5076 23:46:02.824693 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5077 23:46:02.827511 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5078 23:46:02.831181 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5079 23:46:02.831262
5080 23:46:02.834097 CA PerBit enable=1, Macro0, CA PI delay=32
5081 23:46:02.834177
5082 23:46:02.837553 [CBTSetCACLKResult] CA Dly = 32
5083 23:46:02.837634 CS Dly: 6 (0~37)
5084 23:46:02.837699 ==
5085 23:46:02.841452 Dram Type= 6, Freq= 0, CH_0, rank 1
5086 23:46:02.847191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 23:46:02.847276 ==
5088 23:46:02.850511 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5089 23:46:02.856993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5090 23:46:02.860406 [CA 0] Center 38 (8~68) winsize 61
5091 23:46:02.863953 [CA 1] Center 37 (7~68) winsize 62
5092 23:46:02.866862 [CA 2] Center 34 (4~65) winsize 62
5093 23:46:02.870160 [CA 3] Center 34 (4~65) winsize 62
5094 23:46:02.874146 [CA 4] Center 33 (3~64) winsize 62
5095 23:46:02.877143 [CA 5] Center 32 (2~63) winsize 62
5096 23:46:02.877249
5097 23:46:02.880115 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5098 23:46:02.880219
5099 23:46:02.883409 [CATrainingPosCal] consider 2 rank data
5100 23:46:02.887064 u2DelayCellTimex100 = 270/100 ps
5101 23:46:02.890301 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5102 23:46:02.896785 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5103 23:46:02.900002 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5104 23:46:02.903456 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5105 23:46:02.906913 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5106 23:46:02.910106 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5107 23:46:02.910213
5108 23:46:02.913103 CA PerBit enable=1, Macro0, CA PI delay=32
5109 23:46:02.913208
5110 23:46:02.916630 [CBTSetCACLKResult] CA Dly = 32
5111 23:46:02.919830 CS Dly: 7 (0~39)
5112 23:46:02.919932
5113 23:46:02.923357 ----->DramcWriteLeveling(PI) begin...
5114 23:46:02.923461 ==
5115 23:46:02.926282 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 23:46:02.929703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 23:46:02.929801 ==
5118 23:46:02.932869 Write leveling (Byte 0): 28 => 28
5119 23:46:02.936129 Write leveling (Byte 1): 26 => 26
5120 23:46:02.939833 DramcWriteLeveling(PI) end<-----
5121 23:46:02.939931
5122 23:46:02.940026 ==
5123 23:46:02.942859 Dram Type= 6, Freq= 0, CH_0, rank 0
5124 23:46:02.946368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5125 23:46:02.946474 ==
5126 23:46:02.949672 [Gating] SW mode calibration
5127 23:46:02.955853 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5128 23:46:02.963190 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5129 23:46:02.966040 0 14 0 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
5130 23:46:02.969636 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5131 23:46:02.975854 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5132 23:46:02.979177 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5133 23:46:02.983164 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 23:46:02.989250 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 23:46:02.992710 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
5136 23:46:02.995724 0 14 28 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
5137 23:46:03.002253 0 15 0 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (0 0)
5138 23:46:03.005869 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5139 23:46:03.009088 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5140 23:46:03.015352 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5141 23:46:03.018741 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 23:46:03.022180 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 23:46:03.028664 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 23:46:03.031845 0 15 28 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
5145 23:46:03.036220 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5146 23:46:03.042001 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 23:46:03.045557 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 23:46:03.048808 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5149 23:46:03.054883 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 23:46:03.058188 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 23:46:03.061628 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 23:46:03.068366 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5153 23:46:03.071724 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5154 23:46:03.074818 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5155 23:46:03.081729 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5156 23:46:03.084897 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 23:46:03.088432 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 23:46:03.094730 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 23:46:03.097788 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 23:46:03.104339 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 23:46:03.108329 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 23:46:03.110879 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 23:46:03.117769 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 23:46:03.120794 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 23:46:03.124703 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 23:46:03.127624 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 23:46:03.134130 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 23:46:03.137482 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5169 23:46:03.144114 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5170 23:46:03.144220 Total UI for P1: 0, mck2ui 16
5171 23:46:03.147702 best dqsien dly found for B0: ( 1, 2, 28)
5172 23:46:03.153633 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 23:46:03.157105 Total UI for P1: 0, mck2ui 16
5174 23:46:03.160611 best dqsien dly found for B1: ( 1, 3, 0)
5175 23:46:03.163614 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5176 23:46:03.166892 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5177 23:46:03.166963
5178 23:46:03.170328 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5179 23:46:03.173579 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5180 23:46:03.177413 [Gating] SW calibration Done
5181 23:46:03.177484 ==
5182 23:46:03.180631 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 23:46:03.183598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 23:46:03.183669 ==
5185 23:46:03.187024 RX Vref Scan: 0
5186 23:46:03.187094
5187 23:46:03.190185 RX Vref 0 -> 0, step: 1
5188 23:46:03.190254
5189 23:46:03.190312 RX Delay -80 -> 252, step: 8
5190 23:46:03.196669 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5191 23:46:03.200341 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5192 23:46:03.203381 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5193 23:46:03.206723 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5194 23:46:03.209694 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5195 23:46:03.213398 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5196 23:46:03.219804 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5197 23:46:03.223430 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5198 23:46:03.226265 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5199 23:46:03.229693 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5200 23:46:03.233141 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5201 23:46:03.239533 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5202 23:46:03.242637 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5203 23:46:03.245999 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5204 23:46:03.249528 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5205 23:46:03.252907 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5206 23:46:03.256059 ==
5207 23:46:03.259470 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 23:46:03.262646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 23:46:03.262747 ==
5210 23:46:03.262837 DQS Delay:
5211 23:46:03.266030 DQS0 = 0, DQS1 = 0
5212 23:46:03.266116 DQM Delay:
5213 23:46:03.269373 DQM0 = 101, DQM1 = 87
5214 23:46:03.269469 DQ Delay:
5215 23:46:03.272679 DQ0 =103, DQ1 =103, DQ2 =95, DQ3 =99
5216 23:46:03.275627 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =107
5217 23:46:03.279401 DQ8 =79, DQ9 =71, DQ10 =87, DQ11 =83
5218 23:46:03.282289 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5219 23:46:03.282384
5220 23:46:03.282472
5221 23:46:03.282560 ==
5222 23:46:03.285643 Dram Type= 6, Freq= 0, CH_0, rank 0
5223 23:46:03.288996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5224 23:46:03.292189 ==
5225 23:46:03.292269
5226 23:46:03.292331
5227 23:46:03.292389 TX Vref Scan disable
5228 23:46:03.295829 == TX Byte 0 ==
5229 23:46:03.299155 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5230 23:46:03.302109 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5231 23:46:03.305554 == TX Byte 1 ==
5232 23:46:03.308697 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5233 23:46:03.312207 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5234 23:46:03.315341 ==
5235 23:46:03.318688 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 23:46:03.321904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 23:46:03.322051 ==
5238 23:46:03.322149
5239 23:46:03.322239
5240 23:46:03.325289 TX Vref Scan disable
5241 23:46:03.325396 == TX Byte 0 ==
5242 23:46:03.331579 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5243 23:46:03.335077 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5244 23:46:03.335185 == TX Byte 1 ==
5245 23:46:03.341535 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5246 23:46:03.345168 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5247 23:46:03.345297
5248 23:46:03.345405 [DATLAT]
5249 23:46:03.348066 Freq=933, CH0 RK0
5250 23:46:03.348141
5251 23:46:03.348204 DATLAT Default: 0xd
5252 23:46:03.351486 0, 0xFFFF, sum = 0
5253 23:46:03.351587 1, 0xFFFF, sum = 0
5254 23:46:03.354985 2, 0xFFFF, sum = 0
5255 23:46:03.355057 3, 0xFFFF, sum = 0
5256 23:46:03.358206 4, 0xFFFF, sum = 0
5257 23:46:03.361369 5, 0xFFFF, sum = 0
5258 23:46:03.361476 6, 0xFFFF, sum = 0
5259 23:46:03.364628 7, 0xFFFF, sum = 0
5260 23:46:03.364734 8, 0xFFFF, sum = 0
5261 23:46:03.368128 9, 0xFFFF, sum = 0
5262 23:46:03.368232 10, 0x0, sum = 1
5263 23:46:03.371045 11, 0x0, sum = 2
5264 23:46:03.371136 12, 0x0, sum = 3
5265 23:46:03.374281 13, 0x0, sum = 4
5266 23:46:03.374354 best_step = 11
5267 23:46:03.374434
5268 23:46:03.374495 ==
5269 23:46:03.377679 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 23:46:03.380981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 23:46:03.381078 ==
5272 23:46:03.384295 RX Vref Scan: 1
5273 23:46:03.384396
5274 23:46:03.387416 RX Vref 0 -> 0, step: 1
5275 23:46:03.387520
5276 23:46:03.387611 RX Delay -69 -> 252, step: 4
5277 23:46:03.387704
5278 23:46:03.390966 Set Vref, RX VrefLevel [Byte0]: 57
5279 23:46:03.393909 [Byte1]: 51
5280 23:46:03.399294
5281 23:46:03.399394 Final RX Vref Byte 0 = 57 to rank0
5282 23:46:03.402433 Final RX Vref Byte 1 = 51 to rank0
5283 23:46:03.405571 Final RX Vref Byte 0 = 57 to rank1
5284 23:46:03.409439 Final RX Vref Byte 1 = 51 to rank1==
5285 23:46:03.412065 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 23:46:03.418703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 23:46:03.418781 ==
5288 23:46:03.418845 DQS Delay:
5289 23:46:03.422287 DQS0 = 0, DQS1 = 0
5290 23:46:03.422359 DQM Delay:
5291 23:46:03.422426 DQM0 = 102, DQM1 = 90
5292 23:46:03.425115 DQ Delay:
5293 23:46:03.428974 DQ0 =104, DQ1 =102, DQ2 =98, DQ3 =100
5294 23:46:03.432212 DQ4 =102, DQ5 =96, DQ6 =112, DQ7 =108
5295 23:46:03.435301 DQ8 =80, DQ9 =76, DQ10 =92, DQ11 =86
5296 23:46:03.438950 DQ12 =98, DQ13 =92, DQ14 =100, DQ15 =98
5297 23:46:03.439131
5298 23:46:03.439248
5299 23:46:03.445270 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5300 23:46:03.448124 CH0 RK0: MR19=505, MR18=1B15
5301 23:46:03.454748 CH0_RK0: MR19=0x505, MR18=0x1B15, DQSOSC=413, MR23=63, INC=63, DEC=42
5302 23:46:03.454864
5303 23:46:03.458763 ----->DramcWriteLeveling(PI) begin...
5304 23:46:03.458878 ==
5305 23:46:03.461397 Dram Type= 6, Freq= 0, CH_0, rank 1
5306 23:46:03.467946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5307 23:46:03.468057 ==
5308 23:46:03.471629 Write leveling (Byte 0): 32 => 32
5309 23:46:03.471738 Write leveling (Byte 1): 27 => 27
5310 23:46:03.474669 DramcWriteLeveling(PI) end<-----
5311 23:46:03.474781
5312 23:46:03.474889 ==
5313 23:46:03.477899 Dram Type= 6, Freq= 0, CH_0, rank 1
5314 23:46:03.484281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5315 23:46:03.484398 ==
5316 23:46:03.487991 [Gating] SW mode calibration
5317 23:46:03.494301 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5318 23:46:03.497989 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5319 23:46:03.505490 0 14 0 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
5320 23:46:03.507839 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5321 23:46:03.510720 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5322 23:46:03.517685 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5323 23:46:03.521092 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 23:46:03.523891 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 23:46:03.530566 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5326 23:46:03.533954 0 14 28 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
5327 23:46:03.537096 0 15 0 | B1->B0 | 3131 2424 | 0 0 | (0 0) (0 0)
5328 23:46:03.544604 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5329 23:46:03.547062 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5330 23:46:03.550251 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 23:46:03.557227 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 23:46:03.560698 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 23:46:03.563923 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5334 23:46:03.570427 0 15 28 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
5335 23:46:03.573477 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5336 23:46:03.576736 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5337 23:46:03.583303 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 23:46:03.587155 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5339 23:46:03.589874 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 23:46:03.596327 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 23:46:03.599702 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 23:46:03.603362 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5343 23:46:03.610004 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5344 23:46:03.613001 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5345 23:46:03.616365 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5346 23:46:03.623285 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 23:46:03.626213 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 23:46:03.629312 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 23:46:03.636020 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 23:46:03.639568 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 23:46:03.642562 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 23:46:03.649648 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 23:46:03.652541 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 23:46:03.655947 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 23:46:03.662851 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 23:46:03.665522 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 23:46:03.669602 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5358 23:46:03.675655 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5359 23:46:03.675738 Total UI for P1: 0, mck2ui 16
5360 23:46:03.682631 best dqsien dly found for B0: ( 1, 2, 24)
5361 23:46:03.686138 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5362 23:46:03.688779 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 23:46:03.692185 Total UI for P1: 0, mck2ui 16
5364 23:46:03.695620 best dqsien dly found for B1: ( 1, 3, 0)
5365 23:46:03.698558 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5366 23:46:03.702282 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5367 23:46:03.702356
5368 23:46:03.709195 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5369 23:46:03.712325 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5370 23:46:03.712404 [Gating] SW calibration Done
5371 23:46:03.715399 ==
5372 23:46:03.718915 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 23:46:03.721821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 23:46:03.721892 ==
5375 23:46:03.721956 RX Vref Scan: 0
5376 23:46:03.722016
5377 23:46:03.725221 RX Vref 0 -> 0, step: 1
5378 23:46:03.725339
5379 23:46:03.728640 RX Delay -80 -> 252, step: 8
5380 23:46:03.731773 iDelay=200, Bit 0, Center 103 (16 ~ 191) 176
5381 23:46:03.735021 iDelay=200, Bit 1, Center 107 (16 ~ 199) 184
5382 23:46:03.741963 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5383 23:46:03.744884 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5384 23:46:03.748267 iDelay=200, Bit 4, Center 107 (16 ~ 199) 184
5385 23:46:03.751827 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5386 23:46:03.754845 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5387 23:46:03.758492 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5388 23:46:03.764751 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5389 23:46:03.768044 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5390 23:46:03.771170 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5391 23:46:03.774565 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5392 23:46:03.778087 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5393 23:46:03.784999 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5394 23:46:03.787538 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5395 23:46:03.791255 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5396 23:46:03.791359 ==
5397 23:46:03.794838 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 23:46:03.797310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 23:46:03.797380 ==
5400 23:46:03.800782 DQS Delay:
5401 23:46:03.800850 DQS0 = 0, DQS1 = 0
5402 23:46:03.804026 DQM Delay:
5403 23:46:03.804092 DQM0 = 101, DQM1 = 88
5404 23:46:03.804150 DQ Delay:
5405 23:46:03.807429 DQ0 =103, DQ1 =107, DQ2 =95, DQ3 =95
5406 23:46:03.813608 DQ4 =107, DQ5 =91, DQ6 =107, DQ7 =107
5407 23:46:03.813690 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5408 23:46:03.821010 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5409 23:46:03.821080
5410 23:46:03.821145
5411 23:46:03.821232 ==
5412 23:46:03.823588 Dram Type= 6, Freq= 0, CH_0, rank 1
5413 23:46:03.827156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5414 23:46:03.827225 ==
5415 23:46:03.827285
5416 23:46:03.827341
5417 23:46:03.830545 TX Vref Scan disable
5418 23:46:03.830642 == TX Byte 0 ==
5419 23:46:03.836731 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5420 23:46:03.840075 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5421 23:46:03.840181 == TX Byte 1 ==
5422 23:46:03.846848 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5423 23:46:03.850533 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5424 23:46:03.850611 ==
5425 23:46:03.853351 Dram Type= 6, Freq= 0, CH_0, rank 1
5426 23:46:03.856746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5427 23:46:03.856820 ==
5428 23:46:03.856908
5429 23:46:03.859713
5430 23:46:03.859808 TX Vref Scan disable
5431 23:46:03.863594 == TX Byte 0 ==
5432 23:46:03.866728 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5433 23:46:03.873283 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5434 23:46:03.873372 == TX Byte 1 ==
5435 23:46:03.876814 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5436 23:46:03.883241 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5437 23:46:03.883336
5438 23:46:03.883424 [DATLAT]
5439 23:46:03.883513 Freq=933, CH0 RK1
5440 23:46:03.883598
5441 23:46:03.886626 DATLAT Default: 0xb
5442 23:46:03.886721 0, 0xFFFF, sum = 0
5443 23:46:03.890150 1, 0xFFFF, sum = 0
5444 23:46:03.893197 2, 0xFFFF, sum = 0
5445 23:46:03.893339 3, 0xFFFF, sum = 0
5446 23:46:03.896429 4, 0xFFFF, sum = 0
5447 23:46:03.896511 5, 0xFFFF, sum = 0
5448 23:46:03.899790 6, 0xFFFF, sum = 0
5449 23:46:03.899889 7, 0xFFFF, sum = 0
5450 23:46:03.902525 8, 0xFFFF, sum = 0
5451 23:46:03.902594 9, 0xFFFF, sum = 0
5452 23:46:03.905924 10, 0x0, sum = 1
5453 23:46:03.906029 11, 0x0, sum = 2
5454 23:46:03.909881 12, 0x0, sum = 3
5455 23:46:03.909955 13, 0x0, sum = 4
5456 23:46:03.912964 best_step = 11
5457 23:46:03.913032
5458 23:46:03.913103 ==
5459 23:46:03.915961 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 23:46:03.919097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 23:46:03.919175 ==
5462 23:46:03.919236 RX Vref Scan: 0
5463 23:46:03.922459
5464 23:46:03.922524 RX Vref 0 -> 0, step: 1
5465 23:46:03.922584
5466 23:46:03.925542 RX Delay -61 -> 252, step: 4
5467 23:46:03.932413 iDelay=195, Bit 0, Center 100 (15 ~ 186) 172
5468 23:46:03.935387 iDelay=195, Bit 1, Center 102 (15 ~ 190) 176
5469 23:46:03.938908 iDelay=195, Bit 2, Center 96 (11 ~ 182) 172
5470 23:46:03.942300 iDelay=195, Bit 3, Center 98 (11 ~ 186) 176
5471 23:46:03.945482 iDelay=195, Bit 4, Center 104 (19 ~ 190) 172
5472 23:46:03.952305 iDelay=195, Bit 5, Center 92 (7 ~ 178) 172
5473 23:46:03.955604 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5474 23:46:03.958913 iDelay=195, Bit 7, Center 108 (23 ~ 194) 172
5475 23:46:03.961781 iDelay=195, Bit 8, Center 82 (-5 ~ 170) 176
5476 23:46:03.965205 iDelay=195, Bit 9, Center 80 (-5 ~ 166) 172
5477 23:46:03.971640 iDelay=195, Bit 10, Center 90 (3 ~ 178) 176
5478 23:46:03.975096 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5479 23:46:03.978370 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5480 23:46:03.982186 iDelay=195, Bit 13, Center 96 (11 ~ 182) 172
5481 23:46:03.984918 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5482 23:46:03.992002 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5483 23:46:03.992103 ==
5484 23:46:03.995229 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 23:46:03.998650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 23:46:03.998721 ==
5487 23:46:03.998782 DQS Delay:
5488 23:46:04.001720 DQS0 = 0, DQS1 = 0
5489 23:46:04.001793 DQM Delay:
5490 23:46:04.004763 DQM0 = 101, DQM1 = 90
5491 23:46:04.004855 DQ Delay:
5492 23:46:04.008745 DQ0 =100, DQ1 =102, DQ2 =96, DQ3 =98
5493 23:46:04.011265 DQ4 =104, DQ5 =92, DQ6 =110, DQ7 =108
5494 23:46:04.015635 DQ8 =82, DQ9 =80, DQ10 =90, DQ11 =82
5495 23:46:04.017830 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =96
5496 23:46:04.017911
5497 23:46:04.017975
5498 23:46:04.027605 [DQSOSCAuto] RK1, (LSB)MR18= 0x1411, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5499 23:46:04.027688 CH0 RK1: MR19=505, MR18=1411
5500 23:46:04.034323 CH0_RK1: MR19=0x505, MR18=0x1411, DQSOSC=415, MR23=63, INC=62, DEC=41
5501 23:46:04.037655 [RxdqsGatingPostProcess] freq 933
5502 23:46:04.044355 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5503 23:46:04.047661 best DQS0 dly(2T, 0.5T) = (0, 10)
5504 23:46:04.050540 best DQS1 dly(2T, 0.5T) = (0, 11)
5505 23:46:04.053773 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5506 23:46:04.057709 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5507 23:46:04.060297 best DQS0 dly(2T, 0.5T) = (0, 10)
5508 23:46:04.063653 best DQS1 dly(2T, 0.5T) = (0, 11)
5509 23:46:04.067005 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5510 23:46:04.070563 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5511 23:46:04.074531 Pre-setting of DQS Precalculation
5512 23:46:04.077293 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5513 23:46:04.077375 ==
5514 23:46:04.080179 Dram Type= 6, Freq= 0, CH_1, rank 0
5515 23:46:04.083765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 23:46:04.083846 ==
5517 23:46:04.090259 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5518 23:46:04.097009 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5519 23:46:04.099929 [CA 0] Center 36 (6~67) winsize 62
5520 23:46:04.103452 [CA 1] Center 36 (6~67) winsize 62
5521 23:46:04.106655 [CA 2] Center 34 (4~65) winsize 62
5522 23:46:04.109859 [CA 3] Center 34 (3~65) winsize 63
5523 23:46:04.113046 [CA 4] Center 34 (3~65) winsize 63
5524 23:46:04.116434 [CA 5] Center 33 (3~64) winsize 62
5525 23:46:04.116515
5526 23:46:04.120685 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5527 23:46:04.120766
5528 23:46:04.123047 [CATrainingPosCal] consider 1 rank data
5529 23:46:04.126714 u2DelayCellTimex100 = 270/100 ps
5530 23:46:04.129479 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5531 23:46:04.133166 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5532 23:46:04.136746 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5533 23:46:04.142737 CA3 delay=34 (3~65),Diff = 1 PI (6 cell)
5534 23:46:04.146110 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5535 23:46:04.149677 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5536 23:46:04.149758
5537 23:46:04.152821 CA PerBit enable=1, Macro0, CA PI delay=33
5538 23:46:04.152902
5539 23:46:04.156531 [CBTSetCACLKResult] CA Dly = 33
5540 23:46:04.156611 CS Dly: 4 (0~35)
5541 23:46:04.156676 ==
5542 23:46:04.159144 Dram Type= 6, Freq= 0, CH_1, rank 1
5543 23:46:04.165746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5544 23:46:04.165873 ==
5545 23:46:04.169428 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5546 23:46:04.175610 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5547 23:46:04.178837 [CA 0] Center 36 (6~67) winsize 62
5548 23:46:04.182482 [CA 1] Center 36 (6~67) winsize 62
5549 23:46:04.185466 [CA 2] Center 34 (4~65) winsize 62
5550 23:46:04.189099 [CA 3] Center 33 (3~64) winsize 62
5551 23:46:04.192288 [CA 4] Center 33 (3~64) winsize 62
5552 23:46:04.195450 [CA 5] Center 33 (3~64) winsize 62
5553 23:46:04.195532
5554 23:46:04.199012 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5555 23:46:04.199085
5556 23:46:04.201991 [CATrainingPosCal] consider 2 rank data
5557 23:46:04.205379 u2DelayCellTimex100 = 270/100 ps
5558 23:46:04.208812 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5559 23:46:04.215169 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 23:46:04.218388 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5561 23:46:04.222109 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5562 23:46:04.225364 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5563 23:46:04.228489 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 23:46:04.228558
5565 23:46:04.231797 CA PerBit enable=1, Macro0, CA PI delay=33
5566 23:46:04.231891
5567 23:46:04.235099 [CBTSetCACLKResult] CA Dly = 33
5568 23:46:04.239635 CS Dly: 5 (0~38)
5569 23:46:04.239731
5570 23:46:04.241939 ----->DramcWriteLeveling(PI) begin...
5571 23:46:04.242012 ==
5572 23:46:04.244899 Dram Type= 6, Freq= 0, CH_1, rank 0
5573 23:46:04.248471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 23:46:04.248554 ==
5575 23:46:04.251350 Write leveling (Byte 0): 27 => 27
5576 23:46:04.254801 Write leveling (Byte 1): 28 => 28
5577 23:46:04.258475 DramcWriteLeveling(PI) end<-----
5578 23:46:04.258556
5579 23:46:04.258620 ==
5580 23:46:04.261471 Dram Type= 6, Freq= 0, CH_1, rank 0
5581 23:46:04.264452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5582 23:46:04.264534 ==
5583 23:46:04.267761 [Gating] SW mode calibration
5584 23:46:04.275039 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5585 23:46:04.281608 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5586 23:46:04.284618 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5587 23:46:04.288406 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5588 23:46:04.294346 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5589 23:46:04.297898 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 23:46:04.303993 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 23:46:04.307433 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 23:46:04.310876 0 14 24 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
5593 23:46:04.317662 0 14 28 | B1->B0 | 2f2f 2424 | 0 0 | (1 1) (0 0)
5594 23:46:04.320798 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5595 23:46:04.323775 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5596 23:46:04.330194 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5597 23:46:04.334008 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 23:46:04.337668 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 23:46:04.343450 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5600 23:46:04.346805 0 15 24 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
5601 23:46:04.349875 0 15 28 | B1->B0 | 3939 4242 | 0 0 | (0 0) (0 0)
5602 23:46:04.356617 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5603 23:46:04.359835 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5604 23:46:04.363066 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 23:46:04.370309 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5606 23:46:04.373483 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 23:46:04.376453 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 23:46:04.382999 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5609 23:46:04.386676 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5610 23:46:04.390266 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5611 23:46:04.396397 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5612 23:46:04.399427 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 23:46:04.403495 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 23:46:04.409255 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 23:46:04.412937 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 23:46:04.416634 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 23:46:04.422320 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 23:46:04.426005 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 23:46:04.429349 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 23:46:04.435580 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 23:46:04.438788 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 23:46:04.442638 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 23:46:04.448903 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 23:46:04.452269 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 23:46:04.455563 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5626 23:46:04.461904 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5627 23:46:04.461979 Total UI for P1: 0, mck2ui 16
5628 23:46:04.468921 best dqsien dly found for B0: ( 1, 2, 28)
5629 23:46:04.469000 Total UI for P1: 0, mck2ui 16
5630 23:46:04.475055 best dqsien dly found for B1: ( 1, 2, 28)
5631 23:46:04.478103 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5632 23:46:04.481542 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5633 23:46:04.481611
5634 23:46:04.485578 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5635 23:46:04.488143 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5636 23:46:04.492003 [Gating] SW calibration Done
5637 23:46:04.492104 ==
5638 23:46:04.494562 Dram Type= 6, Freq= 0, CH_1, rank 0
5639 23:46:04.498466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5640 23:46:04.498563 ==
5641 23:46:04.501427 RX Vref Scan: 0
5642 23:46:04.501523
5643 23:46:04.501612 RX Vref 0 -> 0, step: 1
5644 23:46:04.501698
5645 23:46:04.504764 RX Delay -80 -> 252, step: 8
5646 23:46:04.508781 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5647 23:46:04.514575 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5648 23:46:04.517847 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5649 23:46:04.521183 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5650 23:46:04.525164 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5651 23:46:04.527757 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5652 23:46:04.534514 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5653 23:46:04.537750 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5654 23:46:04.541469 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5655 23:46:04.544601 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5656 23:46:04.547736 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5657 23:46:04.551299 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5658 23:46:04.557581 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5659 23:46:04.561430 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5660 23:46:04.564159 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5661 23:46:04.567360 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5662 23:46:04.567458 ==
5663 23:46:04.570613 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 23:46:04.577128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 23:46:04.577230 ==
5666 23:46:04.577359 DQS Delay:
5667 23:46:04.577435 DQS0 = 0, DQS1 = 0
5668 23:46:04.580763 DQM Delay:
5669 23:46:04.580864 DQM0 = 100, DQM1 = 96
5670 23:46:04.583753 DQ Delay:
5671 23:46:04.587096 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =103
5672 23:46:04.590816 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5673 23:46:04.594012 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5674 23:46:04.597049 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5675 23:46:04.597146
5676 23:46:04.597236
5677 23:46:04.597343 ==
5678 23:46:04.600384 Dram Type= 6, Freq= 0, CH_1, rank 0
5679 23:46:04.604269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5680 23:46:04.604368 ==
5681 23:46:04.604435
5682 23:46:04.604496
5683 23:46:04.607077 TX Vref Scan disable
5684 23:46:04.610800 == TX Byte 0 ==
5685 23:46:04.613517 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5686 23:46:04.616707 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5687 23:46:04.620188 == TX Byte 1 ==
5688 23:46:04.623335 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5689 23:46:04.626498 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5690 23:46:04.626606 ==
5691 23:46:04.629984 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 23:46:04.636866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 23:46:04.636966 ==
5694 23:46:04.637075
5695 23:46:04.637164
5696 23:46:04.637252 TX Vref Scan disable
5697 23:46:04.640891 == TX Byte 0 ==
5698 23:46:04.643839 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5699 23:46:04.650236 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5700 23:46:04.650345 == TX Byte 1 ==
5701 23:46:04.653980 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5702 23:46:04.660507 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5703 23:46:04.660629
5704 23:46:04.660738 [DATLAT]
5705 23:46:04.660828 Freq=933, CH1 RK0
5706 23:46:04.660915
5707 23:46:04.663697 DATLAT Default: 0xd
5708 23:46:04.663797 0, 0xFFFF, sum = 0
5709 23:46:04.666932 1, 0xFFFF, sum = 0
5710 23:46:04.670201 2, 0xFFFF, sum = 0
5711 23:46:04.670365 3, 0xFFFF, sum = 0
5712 23:46:04.673915 4, 0xFFFF, sum = 0
5713 23:46:04.673993 5, 0xFFFF, sum = 0
5714 23:46:04.676738 6, 0xFFFF, sum = 0
5715 23:46:04.676816 7, 0xFFFF, sum = 0
5716 23:46:04.680009 8, 0xFFFF, sum = 0
5717 23:46:04.680111 9, 0xFFFF, sum = 0
5718 23:46:04.683528 10, 0x0, sum = 1
5719 23:46:04.683628 11, 0x0, sum = 2
5720 23:46:04.686890 12, 0x0, sum = 3
5721 23:46:04.686988 13, 0x0, sum = 4
5722 23:46:04.687081 best_step = 11
5723 23:46:04.689839
5724 23:46:04.689914 ==
5725 23:46:04.693199 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 23:46:04.696670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 23:46:04.696744 ==
5728 23:46:04.696808 RX Vref Scan: 1
5729 23:46:04.696885
5730 23:46:04.699774 RX Vref 0 -> 0, step: 1
5731 23:46:04.699875
5732 23:46:04.703420 RX Delay -53 -> 252, step: 4
5733 23:46:04.703519
5734 23:46:04.706641 Set Vref, RX VrefLevel [Byte0]: 51
5735 23:46:04.710339 [Byte1]: 51
5736 23:46:04.713032
5737 23:46:04.713133 Final RX Vref Byte 0 = 51 to rank0
5738 23:46:04.716421 Final RX Vref Byte 1 = 51 to rank0
5739 23:46:04.719595 Final RX Vref Byte 0 = 51 to rank1
5740 23:46:04.722827 Final RX Vref Byte 1 = 51 to rank1==
5741 23:46:04.726404 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 23:46:04.733028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 23:46:04.733137 ==
5744 23:46:04.733233 DQS Delay:
5745 23:46:04.736412 DQS0 = 0, DQS1 = 0
5746 23:46:04.736486 DQM Delay:
5747 23:46:04.736548 DQM0 = 98, DQM1 = 94
5748 23:46:04.739730 DQ Delay:
5749 23:46:04.742752 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =100
5750 23:46:04.746136 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5751 23:46:04.749134 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5752 23:46:04.752803 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =104
5753 23:46:04.752886
5754 23:46:04.752951
5755 23:46:04.759168 [DQSOSCAuto] RK0, (LSB)MR18= 0x515, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 420 ps
5756 23:46:04.762883 CH1 RK0: MR19=505, MR18=515
5757 23:46:04.769149 CH1_RK0: MR19=0x505, MR18=0x515, DQSOSC=415, MR23=63, INC=62, DEC=41
5758 23:46:04.769264
5759 23:46:04.772598 ----->DramcWriteLeveling(PI) begin...
5760 23:46:04.772672 ==
5761 23:46:04.776370 Dram Type= 6, Freq= 0, CH_1, rank 1
5762 23:46:04.778933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5763 23:46:04.779031 ==
5764 23:46:04.782221 Write leveling (Byte 0): 28 => 28
5765 23:46:04.785620 Write leveling (Byte 1): 29 => 29
5766 23:46:04.789226 DramcWriteLeveling(PI) end<-----
5767 23:46:04.789335
5768 23:46:04.789427 ==
5769 23:46:04.792607 Dram Type= 6, Freq= 0, CH_1, rank 1
5770 23:46:04.799327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 23:46:04.799432 ==
5772 23:46:04.799528 [Gating] SW mode calibration
5773 23:46:04.808705 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5774 23:46:04.812242 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5775 23:46:04.818814 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5776 23:46:04.822156 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5777 23:46:04.825414 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5778 23:46:04.831910 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 23:46:04.835138 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 23:46:04.838529 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 23:46:04.842020 0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (1 0)
5782 23:46:04.848387 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
5783 23:46:04.851883 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5784 23:46:04.858468 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5785 23:46:04.862625 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5786 23:46:04.864944 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 23:46:04.871583 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5788 23:46:04.874738 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 23:46:04.877875 0 15 24 | B1->B0 | 2423 3838 | 1 0 | (0 0) (0 0)
5790 23:46:04.884671 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5791 23:46:04.888275 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5792 23:46:04.891064 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 23:46:04.897693 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 23:46:04.900944 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 23:46:04.904059 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 23:46:04.910769 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 23:46:04.914003 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5798 23:46:04.917883 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5799 23:46:04.924121 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5800 23:46:04.927657 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5801 23:46:04.930937 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5802 23:46:04.937103 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 23:46:04.940495 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 23:46:04.943550 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 23:46:04.950903 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 23:46:04.953692 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 23:46:04.956907 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 23:46:04.963958 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 23:46:04.966525 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 23:46:04.969906 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 23:46:04.976824 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 23:46:04.979824 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 23:46:04.983241 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 23:46:04.989858 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5815 23:46:04.993101 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 23:46:04.996438 Total UI for P1: 0, mck2ui 16
5817 23:46:04.999538 best dqsien dly found for B0: ( 1, 2, 28)
5818 23:46:05.002691 Total UI for P1: 0, mck2ui 16
5819 23:46:05.006463 best dqsien dly found for B1: ( 1, 2, 28)
5820 23:46:05.009529 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5821 23:46:05.012950 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5822 23:46:05.013047
5823 23:46:05.016238 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5824 23:46:05.019270 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5825 23:46:05.022866 [Gating] SW calibration Done
5826 23:46:05.022950 ==
5827 23:46:05.026374 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 23:46:05.029457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 23:46:05.032777 ==
5830 23:46:05.032881 RX Vref Scan: 0
5831 23:46:05.032970
5832 23:46:05.035943 RX Vref 0 -> 0, step: 1
5833 23:46:05.036039
5834 23:46:05.039069 RX Delay -80 -> 252, step: 8
5835 23:46:05.042549 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5836 23:46:05.046002 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5837 23:46:05.048867 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5838 23:46:05.052558 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5839 23:46:05.056065 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5840 23:46:05.062322 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5841 23:46:05.065450 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5842 23:46:05.069022 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5843 23:46:05.072021 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5844 23:46:05.075618 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5845 23:46:05.082202 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5846 23:46:05.085147 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5847 23:46:05.088992 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5848 23:46:05.091959 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5849 23:46:05.095363 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5850 23:46:05.101925 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5851 23:46:05.102001 ==
5852 23:46:05.105148 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 23:46:05.108086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 23:46:05.108168 ==
5855 23:46:05.108233 DQS Delay:
5856 23:46:05.111543 DQS0 = 0, DQS1 = 0
5857 23:46:05.111651 DQM Delay:
5858 23:46:05.114956 DQM0 = 97, DQM1 = 94
5859 23:46:05.115045 DQ Delay:
5860 23:46:05.118784 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5861 23:46:05.121583 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5862 23:46:05.124553 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5863 23:46:05.127970 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5864 23:46:05.128069
5865 23:46:05.128158
5866 23:46:05.128253 ==
5867 23:46:05.131354 Dram Type= 6, Freq= 0, CH_1, rank 1
5868 23:46:05.137586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5869 23:46:05.137696 ==
5870 23:46:05.137787
5871 23:46:05.137873
5872 23:46:05.137966 TX Vref Scan disable
5873 23:46:05.141035 == TX Byte 0 ==
5874 23:46:05.144609 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5875 23:46:05.150845 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5876 23:46:05.150921 == TX Byte 1 ==
5877 23:46:05.154216 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5878 23:46:05.160974 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5879 23:46:05.161076 ==
5880 23:46:05.164353 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 23:46:05.167359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 23:46:05.167463 ==
5883 23:46:05.167554
5884 23:46:05.167640
5885 23:46:05.170762 TX Vref Scan disable
5886 23:46:05.170865 == TX Byte 0 ==
5887 23:46:05.177740 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5888 23:46:05.180570 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5889 23:46:05.183533 == TX Byte 1 ==
5890 23:46:05.186911 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5891 23:46:05.190634 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5892 23:46:05.190708
5893 23:46:05.190769 [DATLAT]
5894 23:46:05.193449 Freq=933, CH1 RK1
5895 23:46:05.193520
5896 23:46:05.196772 DATLAT Default: 0xb
5897 23:46:05.196842 0, 0xFFFF, sum = 0
5898 23:46:05.200641 1, 0xFFFF, sum = 0
5899 23:46:05.200711 2, 0xFFFF, sum = 0
5900 23:46:05.203714 3, 0xFFFF, sum = 0
5901 23:46:05.203809 4, 0xFFFF, sum = 0
5902 23:46:05.206818 5, 0xFFFF, sum = 0
5903 23:46:05.206919 6, 0xFFFF, sum = 0
5904 23:46:05.209913 7, 0xFFFF, sum = 0
5905 23:46:05.209989 8, 0xFFFF, sum = 0
5906 23:46:05.213283 9, 0xFFFF, sum = 0
5907 23:46:05.213396 10, 0x0, sum = 1
5908 23:46:05.217029 11, 0x0, sum = 2
5909 23:46:05.217128 12, 0x0, sum = 3
5910 23:46:05.220125 13, 0x0, sum = 4
5911 23:46:05.220224 best_step = 11
5912 23:46:05.220311
5913 23:46:05.220402 ==
5914 23:46:05.223442 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 23:46:05.226601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 23:46:05.229921 ==
5917 23:46:05.229992 RX Vref Scan: 0
5918 23:46:05.230052
5919 23:46:05.232866 RX Vref 0 -> 0, step: 1
5920 23:46:05.232961
5921 23:46:05.236191 RX Delay -53 -> 252, step: 4
5922 23:46:05.239819 iDelay=203, Bit 0, Center 102 (11 ~ 194) 184
5923 23:46:05.243463 iDelay=203, Bit 1, Center 94 (-1 ~ 190) 192
5924 23:46:05.249621 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5925 23:46:05.252734 iDelay=203, Bit 3, Center 96 (3 ~ 190) 188
5926 23:46:05.256024 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5927 23:46:05.259351 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5928 23:46:05.262703 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5929 23:46:05.266198 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5930 23:46:05.272493 iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180
5931 23:46:05.276554 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5932 23:46:05.279237 iDelay=203, Bit 10, Center 94 (3 ~ 186) 184
5933 23:46:05.282595 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5934 23:46:05.285800 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5935 23:46:05.292434 iDelay=203, Bit 13, Center 100 (11 ~ 190) 180
5936 23:46:05.295381 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5937 23:46:05.299029 iDelay=203, Bit 15, Center 100 (7 ~ 194) 188
5938 23:46:05.299135 ==
5939 23:46:05.302133 Dram Type= 6, Freq= 0, CH_1, rank 1
5940 23:46:05.305378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5941 23:46:05.305459 ==
5942 23:46:05.309191 DQS Delay:
5943 23:46:05.309308 DQS0 = 0, DQS1 = 0
5944 23:46:05.311951 DQM Delay:
5945 23:46:05.312032 DQM0 = 97, DQM1 = 92
5946 23:46:05.315463 DQ Delay:
5947 23:46:05.315543 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =96
5948 23:46:05.318527 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
5949 23:46:05.321781 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =84
5950 23:46:05.328616 DQ12 =100, DQ13 =100, DQ14 =96, DQ15 =100
5951 23:46:05.328696
5952 23:46:05.328761
5953 23:46:05.335652 [DQSOSCAuto] RK1, (LSB)MR18= 0xe24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5954 23:46:05.338705 CH1 RK1: MR19=505, MR18=E24
5955 23:46:05.344790 CH1_RK1: MR19=0x505, MR18=0xE24, DQSOSC=410, MR23=63, INC=64, DEC=42
5956 23:46:05.348114 [RxdqsGatingPostProcess] freq 933
5957 23:46:05.351629 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5958 23:46:05.354702 best DQS0 dly(2T, 0.5T) = (0, 10)
5959 23:46:05.358494 best DQS1 dly(2T, 0.5T) = (0, 10)
5960 23:46:05.361421 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5961 23:46:05.364949 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5962 23:46:05.368364 best DQS0 dly(2T, 0.5T) = (0, 10)
5963 23:46:05.371095 best DQS1 dly(2T, 0.5T) = (0, 10)
5964 23:46:05.374600 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5965 23:46:05.377947 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5966 23:46:05.381196 Pre-setting of DQS Precalculation
5967 23:46:05.384972 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5968 23:46:05.394473 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5969 23:46:05.400824 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5970 23:46:05.400910
5971 23:46:05.401001
5972 23:46:05.404034 [Calibration Summary] 1866 Mbps
5973 23:46:05.404135 CH 0, Rank 0
5974 23:46:05.407492 SW Impedance : PASS
5975 23:46:05.407588 DUTY Scan : NO K
5976 23:46:05.410687 ZQ Calibration : PASS
5977 23:46:05.414058 Jitter Meter : NO K
5978 23:46:05.414129 CBT Training : PASS
5979 23:46:05.417369 Write leveling : PASS
5980 23:46:05.420687 RX DQS gating : PASS
5981 23:46:05.420791 RX DQ/DQS(RDDQC) : PASS
5982 23:46:05.423783 TX DQ/DQS : PASS
5983 23:46:05.427270 RX DATLAT : PASS
5984 23:46:05.427367 RX DQ/DQS(Engine): PASS
5985 23:46:05.430603 TX OE : NO K
5986 23:46:05.430675 All Pass.
5987 23:46:05.430744
5988 23:46:05.433457 CH 0, Rank 1
5989 23:46:05.433554 SW Impedance : PASS
5990 23:46:05.437209 DUTY Scan : NO K
5991 23:46:05.440101 ZQ Calibration : PASS
5992 23:46:05.440200 Jitter Meter : NO K
5993 23:46:05.443791 CBT Training : PASS
5994 23:46:05.447013 Write leveling : PASS
5995 23:46:05.447085 RX DQS gating : PASS
5996 23:46:05.450238 RX DQ/DQS(RDDQC) : PASS
5997 23:46:05.454123 TX DQ/DQS : PASS
5998 23:46:05.454205 RX DATLAT : PASS
5999 23:46:05.456696 RX DQ/DQS(Engine): PASS
6000 23:46:05.460033 TX OE : NO K
6001 23:46:05.460129 All Pass.
6002 23:46:05.460204
6003 23:46:05.460274 CH 1, Rank 0
6004 23:46:05.463471 SW Impedance : PASS
6005 23:46:05.466710 DUTY Scan : NO K
6006 23:46:05.466803 ZQ Calibration : PASS
6007 23:46:05.470125 Jitter Meter : NO K
6008 23:46:05.473552 CBT Training : PASS
6009 23:46:05.473670 Write leveling : PASS
6010 23:46:05.476704 RX DQS gating : PASS
6011 23:46:05.479926 RX DQ/DQS(RDDQC) : PASS
6012 23:46:05.480073 TX DQ/DQS : PASS
6013 23:46:05.483593 RX DATLAT : PASS
6014 23:46:05.483740 RX DQ/DQS(Engine): PASS
6015 23:46:05.486230 TX OE : NO K
6016 23:46:05.486375 All Pass.
6017 23:46:05.486500
6018 23:46:05.489884 CH 1, Rank 1
6019 23:46:05.492899 SW Impedance : PASS
6020 23:46:05.493236 DUTY Scan : NO K
6021 23:46:05.496353 ZQ Calibration : PASS
6022 23:46:05.496620 Jitter Meter : NO K
6023 23:46:05.499976 CBT Training : PASS
6024 23:46:05.502864 Write leveling : PASS
6025 23:46:05.503290 RX DQS gating : PASS
6026 23:46:05.506785 RX DQ/DQS(RDDQC) : PASS
6027 23:46:05.510284 TX DQ/DQS : PASS
6028 23:46:05.510764 RX DATLAT : PASS
6029 23:46:05.513164 RX DQ/DQS(Engine): PASS
6030 23:46:05.516236 TX OE : NO K
6031 23:46:05.516728 All Pass.
6032 23:46:05.517287
6033 23:46:05.519600 DramC Write-DBI off
6034 23:46:05.520188 PER_BANK_REFRESH: Hybrid Mode
6035 23:46:05.522803 TX_TRACKING: ON
6036 23:46:05.532742 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6037 23:46:05.536158 [FAST_K] Save calibration result to emmc
6038 23:46:05.539376 dramc_set_vcore_voltage set vcore to 650000
6039 23:46:05.543011 Read voltage for 400, 6
6040 23:46:05.543602 Vio18 = 0
6041 23:46:05.544118 Vcore = 650000
6042 23:46:05.544574 Vdram = 0
6043 23:46:05.546162 Vddq = 0
6044 23:46:05.546577 Vmddr = 0
6045 23:46:05.552112 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6046 23:46:05.555496 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6047 23:46:05.559085 MEM_TYPE=3, freq_sel=20
6048 23:46:05.562153 sv_algorithm_assistance_LP4_800
6049 23:46:05.565218 ============ PULL DRAM RESETB DOWN ============
6050 23:46:05.568494 ========== PULL DRAM RESETB DOWN end =========
6051 23:46:05.575209 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6052 23:46:05.578300 ===================================
6053 23:46:05.578381 LPDDR4 DRAM CONFIGURATION
6054 23:46:05.582086 ===================================
6055 23:46:05.585000 EX_ROW_EN[0] = 0x0
6056 23:46:05.588300 EX_ROW_EN[1] = 0x0
6057 23:46:05.588411 LP4Y_EN = 0x0
6058 23:46:05.591935 WORK_FSP = 0x0
6059 23:46:05.592016 WL = 0x2
6060 23:46:05.595301 RL = 0x2
6061 23:46:05.595381 BL = 0x2
6062 23:46:05.598115 RPST = 0x0
6063 23:46:05.598195 RD_PRE = 0x0
6064 23:46:05.601501 WR_PRE = 0x1
6065 23:46:05.601608 WR_PST = 0x0
6066 23:46:05.605072 DBI_WR = 0x0
6067 23:46:05.605153 DBI_RD = 0x0
6068 23:46:05.608245 OTF = 0x1
6069 23:46:05.611550 ===================================
6070 23:46:05.614810 ===================================
6071 23:46:05.614890 ANA top config
6072 23:46:05.617720 ===================================
6073 23:46:05.621147 DLL_ASYNC_EN = 0
6074 23:46:05.624324 ALL_SLAVE_EN = 1
6075 23:46:05.628013 NEW_RANK_MODE = 1
6076 23:46:05.628095 DLL_IDLE_MODE = 1
6077 23:46:05.631402 LP45_APHY_COMB_EN = 1
6078 23:46:05.634326 TX_ODT_DIS = 1
6079 23:46:05.637513 NEW_8X_MODE = 1
6080 23:46:05.640640 ===================================
6081 23:46:05.644391 ===================================
6082 23:46:05.647697 data_rate = 800
6083 23:46:05.650811 CKR = 1
6084 23:46:05.650891 DQ_P2S_RATIO = 4
6085 23:46:05.653848 ===================================
6086 23:46:05.657129 CA_P2S_RATIO = 4
6087 23:46:05.661460 DQ_CA_OPEN = 0
6088 23:46:05.663778 DQ_SEMI_OPEN = 1
6089 23:46:05.667284 CA_SEMI_OPEN = 1
6090 23:46:05.670622 CA_FULL_RATE = 0
6091 23:46:05.670704 DQ_CKDIV4_EN = 0
6092 23:46:05.674349 CA_CKDIV4_EN = 1
6093 23:46:05.676971 CA_PREDIV_EN = 0
6094 23:46:05.680521 PH8_DLY = 0
6095 23:46:05.684066 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6096 23:46:05.687166 DQ_AAMCK_DIV = 0
6097 23:46:05.687248 CA_AAMCK_DIV = 0
6098 23:46:05.690572 CA_ADMCK_DIV = 4
6099 23:46:05.693610 DQ_TRACK_CA_EN = 0
6100 23:46:05.696988 CA_PICK = 800
6101 23:46:05.700322 CA_MCKIO = 400
6102 23:46:05.703510 MCKIO_SEMI = 400
6103 23:46:05.706751 PLL_FREQ = 3016
6104 23:46:05.710487 DQ_UI_PI_RATIO = 32
6105 23:46:05.710568 CA_UI_PI_RATIO = 32
6106 23:46:05.713189 ===================================
6107 23:46:05.716429 ===================================
6108 23:46:05.720017 memory_type:LPDDR4
6109 23:46:05.723148 GP_NUM : 10
6110 23:46:05.723228 SRAM_EN : 1
6111 23:46:05.726917 MD32_EN : 0
6112 23:46:05.730061 ===================================
6113 23:46:05.733237 [ANA_INIT] >>>>>>>>>>>>>>
6114 23:46:05.736320 <<<<<< [CONFIGURE PHASE]: ANA_TX
6115 23:46:05.739692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6116 23:46:05.742562 ===================================
6117 23:46:05.742643 data_rate = 800,PCW = 0X7400
6118 23:46:05.746517 ===================================
6119 23:46:05.752502 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6120 23:46:05.755927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6121 23:46:05.769424 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6122 23:46:05.772693 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6123 23:46:05.775881 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6124 23:46:05.779279 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6125 23:46:05.782390 [ANA_INIT] flow start
6126 23:46:05.782471 [ANA_INIT] PLL >>>>>>>>
6127 23:46:05.785954 [ANA_INIT] PLL <<<<<<<<
6128 23:46:05.788740 [ANA_INIT] MIDPI >>>>>>>>
6129 23:46:05.792618 [ANA_INIT] MIDPI <<<<<<<<
6130 23:46:05.792702 [ANA_INIT] DLL >>>>>>>>
6131 23:46:05.795917 [ANA_INIT] flow end
6132 23:46:05.798684 ============ LP4 DIFF to SE enter ============
6133 23:46:05.802173 ============ LP4 DIFF to SE exit ============
6134 23:46:05.805539 [ANA_INIT] <<<<<<<<<<<<<
6135 23:46:05.808596 [Flow] Enable top DCM control >>>>>
6136 23:46:05.812077 [Flow] Enable top DCM control <<<<<
6137 23:46:05.815216 Enable DLL master slave shuffle
6138 23:46:05.821645 ==============================================================
6139 23:46:05.821756 Gating Mode config
6140 23:46:05.828197 ==============================================================
6141 23:46:05.828279 Config description:
6142 23:46:05.838333 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6143 23:46:05.844445 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6144 23:46:05.851475 SELPH_MODE 0: By rank 1: By Phase
6145 23:46:05.858352 ==============================================================
6146 23:46:05.858435 GAT_TRACK_EN = 0
6147 23:46:05.860985 RX_GATING_MODE = 2
6148 23:46:05.864404 RX_GATING_TRACK_MODE = 2
6149 23:46:05.868029 SELPH_MODE = 1
6150 23:46:05.871198 PICG_EARLY_EN = 1
6151 23:46:05.874492 VALID_LAT_VALUE = 1
6152 23:46:05.880770 ==============================================================
6153 23:46:05.883949 Enter into Gating configuration >>>>
6154 23:46:05.887829 Exit from Gating configuration <<<<
6155 23:46:05.890793 Enter into DVFS_PRE_config >>>>>
6156 23:46:05.900667 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6157 23:46:05.904101 Exit from DVFS_PRE_config <<<<<
6158 23:46:05.907181 Enter into PICG configuration >>>>
6159 23:46:05.910733 Exit from PICG configuration <<<<
6160 23:46:05.914174 [RX_INPUT] configuration >>>>>
6161 23:46:05.917525 [RX_INPUT] configuration <<<<<
6162 23:46:05.920787 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6163 23:46:05.927496 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6164 23:46:05.933926 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6165 23:46:05.940434 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6166 23:46:05.943816 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6167 23:46:05.950136 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6168 23:46:05.953402 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6169 23:46:05.960030 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6170 23:46:05.963398 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6171 23:46:05.966520 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6172 23:46:05.970153 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6173 23:46:05.976465 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6174 23:46:05.979912 ===================================
6175 23:46:05.983142 LPDDR4 DRAM CONFIGURATION
6176 23:46:05.986351 ===================================
6177 23:46:05.986432 EX_ROW_EN[0] = 0x0
6178 23:46:05.989953 EX_ROW_EN[1] = 0x0
6179 23:46:05.990034 LP4Y_EN = 0x0
6180 23:46:05.993145 WORK_FSP = 0x0
6181 23:46:05.993225 WL = 0x2
6182 23:46:05.996430 RL = 0x2
6183 23:46:05.996510 BL = 0x2
6184 23:46:05.999244 RPST = 0x0
6185 23:46:05.999324 RD_PRE = 0x0
6186 23:46:06.002832 WR_PRE = 0x1
6187 23:46:06.006163 WR_PST = 0x0
6188 23:46:06.006244 DBI_WR = 0x0
6189 23:46:06.009862 DBI_RD = 0x0
6190 23:46:06.009942 OTF = 0x1
6191 23:46:06.012523 ===================================
6192 23:46:06.015815 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6193 23:46:06.022694 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6194 23:46:06.025547 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6195 23:46:06.029582 ===================================
6196 23:46:06.032349 LPDDR4 DRAM CONFIGURATION
6197 23:46:06.035483 ===================================
6198 23:46:06.035573 EX_ROW_EN[0] = 0x10
6199 23:46:06.039356 EX_ROW_EN[1] = 0x0
6200 23:46:06.039436 LP4Y_EN = 0x0
6201 23:46:06.042494 WORK_FSP = 0x0
6202 23:46:06.042574 WL = 0x2
6203 23:46:06.045836 RL = 0x2
6204 23:46:06.045917 BL = 0x2
6205 23:46:06.048637 RPST = 0x0
6206 23:46:06.052808 RD_PRE = 0x0
6207 23:46:06.052888 WR_PRE = 0x1
6208 23:46:06.055356 WR_PST = 0x0
6209 23:46:06.055436 DBI_WR = 0x0
6210 23:46:06.058641 DBI_RD = 0x0
6211 23:46:06.058747 OTF = 0x1
6212 23:46:06.061900 ===================================
6213 23:46:06.068855 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6214 23:46:06.072733 nWR fixed to 30
6215 23:46:06.075629 [ModeRegInit_LP4] CH0 RK0
6216 23:46:06.075710 [ModeRegInit_LP4] CH0 RK1
6217 23:46:06.079215 [ModeRegInit_LP4] CH1 RK0
6218 23:46:06.082114 [ModeRegInit_LP4] CH1 RK1
6219 23:46:06.082195 match AC timing 19
6220 23:46:06.088983 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6221 23:46:06.092780 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6222 23:46:06.096044 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6223 23:46:06.102289 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6224 23:46:06.105482 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6225 23:46:06.105563 ==
6226 23:46:06.109233 Dram Type= 6, Freq= 0, CH_0, rank 0
6227 23:46:06.111888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6228 23:46:06.111970 ==
6229 23:46:06.118497 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6230 23:46:06.125539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6231 23:46:06.128507 [CA 0] Center 36 (8~64) winsize 57
6232 23:46:06.131519 [CA 1] Center 36 (8~64) winsize 57
6233 23:46:06.135045 [CA 2] Center 36 (8~64) winsize 57
6234 23:46:06.138546 [CA 3] Center 36 (8~64) winsize 57
6235 23:46:06.141694 [CA 4] Center 36 (8~64) winsize 57
6236 23:46:06.144944 [CA 5] Center 36 (8~64) winsize 57
6237 23:46:06.145024
6238 23:46:06.148234 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6239 23:46:06.148314
6240 23:46:06.151620 [CATrainingPosCal] consider 1 rank data
6241 23:46:06.154827 u2DelayCellTimex100 = 270/100 ps
6242 23:46:06.158635 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 23:46:06.161249 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 23:46:06.166503 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 23:46:06.168410 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 23:46:06.171291 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 23:46:06.174483 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 23:46:06.174564
6249 23:46:06.181227 CA PerBit enable=1, Macro0, CA PI delay=36
6250 23:46:06.181354
6251 23:46:06.181449 [CBTSetCACLKResult] CA Dly = 36
6252 23:46:06.184825 CS Dly: 1 (0~32)
6253 23:46:06.184905 ==
6254 23:46:06.188134 Dram Type= 6, Freq= 0, CH_0, rank 1
6255 23:46:06.191118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 23:46:06.191200 ==
6257 23:46:06.197988 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6258 23:46:06.204173 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6259 23:46:06.207636 [CA 0] Center 36 (8~64) winsize 57
6260 23:46:06.210997 [CA 1] Center 36 (8~64) winsize 57
6261 23:46:06.214171 [CA 2] Center 36 (8~64) winsize 57
6262 23:46:06.217663 [CA 3] Center 36 (8~64) winsize 57
6263 23:46:06.217744 [CA 4] Center 36 (8~64) winsize 57
6264 23:46:06.220838 [CA 5] Center 36 (8~64) winsize 57
6265 23:46:06.220919
6266 23:46:06.227456 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6267 23:46:06.227537
6268 23:46:06.230832 [CATrainingPosCal] consider 2 rank data
6269 23:46:06.233807 u2DelayCellTimex100 = 270/100 ps
6270 23:46:06.237149 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 23:46:06.240539 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 23:46:06.243790 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 23:46:06.246770 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 23:46:06.250187 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 23:46:06.253487 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 23:46:06.253568
6277 23:46:06.256667 CA PerBit enable=1, Macro0, CA PI delay=36
6278 23:46:06.256778
6279 23:46:06.260120 [CBTSetCACLKResult] CA Dly = 36
6280 23:46:06.263568 CS Dly: 1 (0~32)
6281 23:46:06.263649
6282 23:46:06.266597 ----->DramcWriteLeveling(PI) begin...
6283 23:46:06.266678 ==
6284 23:46:06.270168 Dram Type= 6, Freq= 0, CH_0, rank 0
6285 23:46:06.273481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6286 23:46:06.273583 ==
6287 23:46:06.276564 Write leveling (Byte 0): 40 => 8
6288 23:46:06.280059 Write leveling (Byte 1): 40 => 8
6289 23:46:06.283459 DramcWriteLeveling(PI) end<-----
6290 23:46:06.283540
6291 23:46:06.283603 ==
6292 23:46:06.287150 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 23:46:06.290084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 23:46:06.290166 ==
6295 23:46:06.293214 [Gating] SW mode calibration
6296 23:46:06.299741 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6297 23:46:06.306169 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6298 23:46:06.309976 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6299 23:46:06.316667 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6300 23:46:06.319419 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6301 23:46:06.322795 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6302 23:46:06.329377 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6303 23:46:06.332809 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6304 23:46:06.335718 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6305 23:46:06.342377 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 23:46:06.345960 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6307 23:46:06.349043 Total UI for P1: 0, mck2ui 16
6308 23:46:06.352397 best dqsien dly found for B0: ( 0, 14, 24)
6309 23:46:06.355475 Total UI for P1: 0, mck2ui 16
6310 23:46:06.358970 best dqsien dly found for B1: ( 0, 14, 24)
6311 23:46:06.362080 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6312 23:46:06.365401 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6313 23:46:06.365492
6314 23:46:06.368975 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6315 23:46:06.375435 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6316 23:46:06.375544 [Gating] SW calibration Done
6317 23:46:06.375636 ==
6318 23:46:06.378892 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 23:46:06.385202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 23:46:06.385344 ==
6321 23:46:06.385435 RX Vref Scan: 0
6322 23:46:06.385523
6323 23:46:06.388961 RX Vref 0 -> 0, step: 1
6324 23:46:06.389031
6325 23:46:06.391809 RX Delay -410 -> 252, step: 16
6326 23:46:06.394895 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6327 23:46:06.398518 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6328 23:46:06.405135 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6329 23:46:06.407973 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6330 23:46:06.411347 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6331 23:46:06.414634 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6332 23:46:06.421514 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6333 23:46:06.424546 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6334 23:46:06.428106 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6335 23:46:06.430980 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6336 23:46:06.437596 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6337 23:46:06.441152 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6338 23:46:06.444276 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6339 23:46:06.450931 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6340 23:46:06.454017 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6341 23:46:06.457669 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6342 23:46:06.457740 ==
6343 23:46:06.460833 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 23:46:06.464349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 23:46:06.467597 ==
6346 23:46:06.467696 DQS Delay:
6347 23:46:06.467788 DQS0 = 35, DQS1 = 51
6348 23:46:06.470577 DQM Delay:
6349 23:46:06.470672 DQM0 = 4, DQM1 = 10
6350 23:46:06.474211 DQ Delay:
6351 23:46:06.474307 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6352 23:46:06.477246 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6353 23:46:06.480310 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6354 23:46:06.484627 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6355 23:46:06.484703
6356 23:46:06.484770
6357 23:46:06.484829 ==
6358 23:46:06.487305 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 23:46:06.493628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 23:46:06.493702 ==
6361 23:46:06.493769
6362 23:46:06.493828
6363 23:46:06.496984 TX Vref Scan disable
6364 23:46:06.497090 == TX Byte 0 ==
6365 23:46:06.500182 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6366 23:46:06.507107 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6367 23:46:06.507188 == TX Byte 1 ==
6368 23:46:06.510006 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 23:46:06.517044 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 23:46:06.517124 ==
6371 23:46:06.519911 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 23:46:06.523743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 23:46:06.523849 ==
6374 23:46:06.523941
6375 23:46:06.524027
6376 23:46:06.526505 TX Vref Scan disable
6377 23:46:06.526585 == TX Byte 0 ==
6378 23:46:06.530830 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6379 23:46:06.536536 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6380 23:46:06.536645 == TX Byte 1 ==
6381 23:46:06.539736 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 23:46:06.546240 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 23:46:06.546320
6384 23:46:06.546384 [DATLAT]
6385 23:46:06.549947 Freq=400, CH0 RK0
6386 23:46:06.550052
6387 23:46:06.550140 DATLAT Default: 0xf
6388 23:46:06.552802 0, 0xFFFF, sum = 0
6389 23:46:06.552884 1, 0xFFFF, sum = 0
6390 23:46:06.556004 2, 0xFFFF, sum = 0
6391 23:46:06.556086 3, 0xFFFF, sum = 0
6392 23:46:06.559358 4, 0xFFFF, sum = 0
6393 23:46:06.559439 5, 0xFFFF, sum = 0
6394 23:46:06.562935 6, 0xFFFF, sum = 0
6395 23:46:06.563084 7, 0xFFFF, sum = 0
6396 23:46:06.566300 8, 0xFFFF, sum = 0
6397 23:46:06.566381 9, 0xFFFF, sum = 0
6398 23:46:06.569144 10, 0xFFFF, sum = 0
6399 23:46:06.569226 11, 0xFFFF, sum = 0
6400 23:46:06.572655 12, 0xFFFF, sum = 0
6401 23:46:06.572735 13, 0x0, sum = 1
6402 23:46:06.575868 14, 0x0, sum = 2
6403 23:46:06.575960 15, 0x0, sum = 3
6404 23:46:06.579100 16, 0x0, sum = 4
6405 23:46:06.579182 best_step = 14
6406 23:46:06.579246
6407 23:46:06.579305 ==
6408 23:46:06.582673 Dram Type= 6, Freq= 0, CH_0, rank 0
6409 23:46:06.588977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6410 23:46:06.589118 ==
6411 23:46:06.589212 RX Vref Scan: 1
6412 23:46:06.589331
6413 23:46:06.592209 RX Vref 0 -> 0, step: 1
6414 23:46:06.592290
6415 23:46:06.595745 RX Delay -343 -> 252, step: 8
6416 23:46:06.595826
6417 23:46:06.599120 Set Vref, RX VrefLevel [Byte0]: 57
6418 23:46:06.602205 [Byte1]: 51
6419 23:46:06.605946
6420 23:46:06.606026 Final RX Vref Byte 0 = 57 to rank0
6421 23:46:06.608904 Final RX Vref Byte 1 = 51 to rank0
6422 23:46:06.612360 Final RX Vref Byte 0 = 57 to rank1
6423 23:46:06.615678 Final RX Vref Byte 1 = 51 to rank1==
6424 23:46:06.618760 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 23:46:06.625263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 23:46:06.625344 ==
6427 23:46:06.625407 DQS Delay:
6428 23:46:06.628787 DQS0 = 44, DQS1 = 56
6429 23:46:06.628867 DQM Delay:
6430 23:46:06.628930 DQM0 = 10, DQM1 = 14
6431 23:46:06.632106 DQ Delay:
6432 23:46:06.635205 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6433 23:46:06.638562 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6434 23:46:06.638643 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6435 23:46:06.645140 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6436 23:46:06.645221
6437 23:46:06.645326
6438 23:46:06.651775 [DQSOSCAuto] RK0, (LSB)MR18= 0x9488, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6439 23:46:06.654992 CH0 RK0: MR19=C0C, MR18=9488
6440 23:46:06.661921 CH0_RK0: MR19=0xC0C, MR18=0x9488, DQSOSC=391, MR23=63, INC=386, DEC=257
6441 23:46:06.662003 ==
6442 23:46:06.664984 Dram Type= 6, Freq= 0, CH_0, rank 1
6443 23:46:06.668479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 23:46:06.668561 ==
6445 23:46:06.671815 [Gating] SW mode calibration
6446 23:46:06.678218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6447 23:46:06.684699 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6448 23:46:06.688254 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6449 23:46:06.691385 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6450 23:46:06.697872 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6451 23:46:06.701132 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6452 23:46:06.704355 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6453 23:46:06.710957 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6454 23:46:06.714298 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6455 23:46:06.717890 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 23:46:06.724478 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6457 23:46:06.727870 Total UI for P1: 0, mck2ui 16
6458 23:46:06.730915 best dqsien dly found for B0: ( 0, 14, 24)
6459 23:46:06.730996 Total UI for P1: 0, mck2ui 16
6460 23:46:06.737779 best dqsien dly found for B1: ( 0, 14, 24)
6461 23:46:06.741047 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6462 23:46:06.743998 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6463 23:46:06.744078
6464 23:46:06.747253 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6465 23:46:06.750675 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6466 23:46:06.754178 [Gating] SW calibration Done
6467 23:46:06.754258 ==
6468 23:46:06.757391 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 23:46:06.760624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 23:46:06.760705 ==
6471 23:46:06.763797 RX Vref Scan: 0
6472 23:46:06.763877
6473 23:46:06.767026 RX Vref 0 -> 0, step: 1
6474 23:46:06.767107
6475 23:46:06.767172 RX Delay -410 -> 252, step: 16
6476 23:46:06.773811 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6477 23:46:06.776861 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6478 23:46:06.780293 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6479 23:46:06.787070 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6480 23:46:06.790518 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6481 23:46:06.793621 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6482 23:46:06.796990 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6483 23:46:06.803365 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6484 23:46:06.807172 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6485 23:46:06.809908 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6486 23:46:06.813419 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6487 23:46:06.819831 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6488 23:46:06.823324 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6489 23:46:06.826634 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6490 23:46:06.829716 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6491 23:46:06.836468 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6492 23:46:06.836549 ==
6493 23:46:06.839898 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 23:46:06.843607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 23:46:06.843689 ==
6496 23:46:06.843752 DQS Delay:
6497 23:46:06.847105 DQS0 = 35, DQS1 = 59
6498 23:46:06.847185 DQM Delay:
6499 23:46:06.849816 DQM0 = 5, DQM1 = 17
6500 23:46:06.849897 DQ Delay:
6501 23:46:06.853345 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6502 23:46:06.856659 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6503 23:46:06.859962 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6504 23:46:06.862974 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6505 23:46:06.863055
6506 23:46:06.863119
6507 23:46:06.863209 ==
6508 23:46:06.866283 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 23:46:06.869768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 23:46:06.869850 ==
6511 23:46:06.869914
6512 23:46:06.872886
6513 23:46:06.872966 TX Vref Scan disable
6514 23:46:06.876252 == TX Byte 0 ==
6515 23:46:06.879462 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6516 23:46:06.882704 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6517 23:46:06.885876 == TX Byte 1 ==
6518 23:46:06.889394 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6519 23:46:06.892156 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6520 23:46:06.892266 ==
6521 23:46:06.895894 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 23:46:06.899133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 23:46:06.902128 ==
6524 23:46:06.902210
6525 23:46:06.902274
6526 23:46:06.902335 TX Vref Scan disable
6527 23:46:06.906032 == TX Byte 0 ==
6528 23:46:06.908992 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6529 23:46:06.912296 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6530 23:46:06.915585 == TX Byte 1 ==
6531 23:46:06.918535 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6532 23:46:06.922152 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6533 23:46:06.922234
6534 23:46:06.925297 [DATLAT]
6535 23:46:06.925380 Freq=400, CH0 RK1
6536 23:46:06.925445
6537 23:46:06.928906 DATLAT Default: 0xe
6538 23:46:06.928987 0, 0xFFFF, sum = 0
6539 23:46:06.932066 1, 0xFFFF, sum = 0
6540 23:46:06.932149 2, 0xFFFF, sum = 0
6541 23:46:06.935346 3, 0xFFFF, sum = 0
6542 23:46:06.935429 4, 0xFFFF, sum = 0
6543 23:46:06.938733 5, 0xFFFF, sum = 0
6544 23:46:06.938816 6, 0xFFFF, sum = 0
6545 23:46:06.942232 7, 0xFFFF, sum = 0
6546 23:46:06.942315 8, 0xFFFF, sum = 0
6547 23:46:06.944921 9, 0xFFFF, sum = 0
6548 23:46:06.945004 10, 0xFFFF, sum = 0
6549 23:46:06.948709 11, 0xFFFF, sum = 0
6550 23:46:06.952233 12, 0xFFFF, sum = 0
6551 23:46:06.952316 13, 0x0, sum = 1
6552 23:46:06.952383 14, 0x0, sum = 2
6553 23:46:06.955018 15, 0x0, sum = 3
6554 23:46:06.955101 16, 0x0, sum = 4
6555 23:46:06.958132 best_step = 14
6556 23:46:06.958213
6557 23:46:06.958277 ==
6558 23:46:06.961973 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 23:46:06.964941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 23:46:06.965023 ==
6561 23:46:06.968386 RX Vref Scan: 0
6562 23:46:06.968468
6563 23:46:06.968532 RX Vref 0 -> 0, step: 1
6564 23:46:06.968594
6565 23:46:06.971666 RX Delay -359 -> 252, step: 8
6566 23:46:06.980111 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6567 23:46:06.983306 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6568 23:46:06.986367 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6569 23:46:06.992966 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
6570 23:46:06.996395 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6571 23:46:06.999588 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6572 23:46:07.002880 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6573 23:46:07.009233 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6574 23:46:07.013059 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6575 23:46:07.015947 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6576 23:46:07.019204 iDelay=217, Bit 10, Center -40 (-279 ~ 200) 480
6577 23:46:07.025927 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6578 23:46:07.029142 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6579 23:46:07.032230 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6580 23:46:07.039155 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6581 23:46:07.042349 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6582 23:46:07.042431 ==
6583 23:46:07.045970 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 23:46:07.048942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 23:46:07.049025 ==
6586 23:46:07.052151 DQS Delay:
6587 23:46:07.052233 DQS0 = 40, DQS1 = 60
6588 23:46:07.052297 DQM Delay:
6589 23:46:07.055339 DQM0 = 7, DQM1 = 14
6590 23:46:07.055420 DQ Delay:
6591 23:46:07.058658 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6592 23:46:07.062027 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6593 23:46:07.065209 DQ8 =4, DQ9 =0, DQ10 =20, DQ11 =8
6594 23:46:07.068905 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6595 23:46:07.068986
6596 23:46:07.069050
6597 23:46:07.078455 [DQSOSCAuto] RK1, (LSB)MR18= 0x8e86, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6598 23:46:07.078539 CH0 RK1: MR19=C0C, MR18=8E86
6599 23:46:07.084673 CH0_RK1: MR19=0xC0C, MR18=0x8E86, DQSOSC=392, MR23=63, INC=384, DEC=256
6600 23:46:07.088225 [RxdqsGatingPostProcess] freq 400
6601 23:46:07.094675 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6602 23:46:07.097683 best DQS0 dly(2T, 0.5T) = (0, 10)
6603 23:46:07.101150 best DQS1 dly(2T, 0.5T) = (0, 10)
6604 23:46:07.104622 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6605 23:46:07.107908 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6606 23:46:07.111294 best DQS0 dly(2T, 0.5T) = (0, 10)
6607 23:46:07.114693 best DQS1 dly(2T, 0.5T) = (0, 10)
6608 23:46:07.117825 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6609 23:46:07.120850 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6610 23:46:07.120932 Pre-setting of DQS Precalculation
6611 23:46:07.127775 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6612 23:46:07.127857 ==
6613 23:46:07.130752 Dram Type= 6, Freq= 0, CH_1, rank 0
6614 23:46:07.134163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 23:46:07.134278 ==
6616 23:46:07.140743 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6617 23:46:07.147075 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6618 23:46:07.150507 [CA 0] Center 36 (8~64) winsize 57
6619 23:46:07.154202 [CA 1] Center 36 (8~64) winsize 57
6620 23:46:07.157651 [CA 2] Center 36 (8~64) winsize 57
6621 23:46:07.160414 [CA 3] Center 36 (8~64) winsize 57
6622 23:46:07.163750 [CA 4] Center 36 (8~64) winsize 57
6623 23:46:07.167409 [CA 5] Center 36 (8~64) winsize 57
6624 23:46:07.167512
6625 23:46:07.170580 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6626 23:46:07.170680
6627 23:46:07.173764 [CATrainingPosCal] consider 1 rank data
6628 23:46:07.176645 u2DelayCellTimex100 = 270/100 ps
6629 23:46:07.180033 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 23:46:07.183389 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 23:46:07.186954 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 23:46:07.190460 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 23:46:07.193169 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 23:46:07.196879 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 23:46:07.196986
6636 23:46:07.203695 CA PerBit enable=1, Macro0, CA PI delay=36
6637 23:46:07.203776
6638 23:46:07.203840 [CBTSetCACLKResult] CA Dly = 36
6639 23:46:07.206941 CS Dly: 1 (0~32)
6640 23:46:07.207033 ==
6641 23:46:07.209956 Dram Type= 6, Freq= 0, CH_1, rank 1
6642 23:46:07.212942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 23:46:07.213049 ==
6644 23:46:07.219804 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6645 23:46:07.226469 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6646 23:46:07.229426 [CA 0] Center 36 (8~64) winsize 57
6647 23:46:07.233023 [CA 1] Center 36 (8~64) winsize 57
6648 23:46:07.236301 [CA 2] Center 36 (8~64) winsize 57
6649 23:46:07.239655 [CA 3] Center 36 (8~64) winsize 57
6650 23:46:07.239742 [CA 4] Center 36 (8~64) winsize 57
6651 23:46:07.242898 [CA 5] Center 36 (8~64) winsize 57
6652 23:46:07.242980
6653 23:46:07.249185 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6654 23:46:07.249301
6655 23:46:07.252860 [CATrainingPosCal] consider 2 rank data
6656 23:46:07.256544 u2DelayCellTimex100 = 270/100 ps
6657 23:46:07.259275 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 23:46:07.262484 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 23:46:07.265946 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 23:46:07.269553 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 23:46:07.272281 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 23:46:07.275528 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 23:46:07.275609
6664 23:46:07.279016 CA PerBit enable=1, Macro0, CA PI delay=36
6665 23:46:07.279097
6666 23:46:07.282568 [CBTSetCACLKResult] CA Dly = 36
6667 23:46:07.285623 CS Dly: 1 (0~32)
6668 23:46:07.285703
6669 23:46:07.288618 ----->DramcWriteLeveling(PI) begin...
6670 23:46:07.288700 ==
6671 23:46:07.292103 Dram Type= 6, Freq= 0, CH_1, rank 0
6672 23:46:07.295822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 23:46:07.295903 ==
6674 23:46:07.298718 Write leveling (Byte 0): 40 => 8
6675 23:46:07.302225 Write leveling (Byte 1): 40 => 8
6676 23:46:07.305508 DramcWriteLeveling(PI) end<-----
6677 23:46:07.305588
6678 23:46:07.305653 ==
6679 23:46:07.308769 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 23:46:07.311749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 23:46:07.311830 ==
6682 23:46:07.315250 [Gating] SW mode calibration
6683 23:46:07.321701 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6684 23:46:07.328475 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6685 23:46:07.331539 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6686 23:46:07.338268 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6687 23:46:07.341398 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6688 23:46:07.344973 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6689 23:46:07.351201 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6690 23:46:07.355048 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6691 23:46:07.357778 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6692 23:46:07.364449 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 23:46:07.368888 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6694 23:46:07.371190 Total UI for P1: 0, mck2ui 16
6695 23:46:07.374707 best dqsien dly found for B0: ( 0, 14, 24)
6696 23:46:07.377614 Total UI for P1: 0, mck2ui 16
6697 23:46:07.380718 best dqsien dly found for B1: ( 0, 14, 24)
6698 23:46:07.384106 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6699 23:46:07.387412 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6700 23:46:07.387517
6701 23:46:07.390969 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6702 23:46:07.397513 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6703 23:46:07.397615 [Gating] SW calibration Done
6704 23:46:07.397705 ==
6705 23:46:07.400964 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 23:46:07.407289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 23:46:07.407397 ==
6708 23:46:07.407491 RX Vref Scan: 0
6709 23:46:07.407578
6710 23:46:07.410608 RX Vref 0 -> 0, step: 1
6711 23:46:07.410679
6712 23:46:07.413977 RX Delay -410 -> 252, step: 16
6713 23:46:07.417359 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6714 23:46:07.420657 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6715 23:46:07.427222 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6716 23:46:07.430207 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6717 23:46:07.434062 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6718 23:46:07.437033 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6719 23:46:07.443278 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6720 23:46:07.446831 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6721 23:46:07.449956 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6722 23:46:07.453014 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6723 23:46:07.459892 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6724 23:46:07.463033 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6725 23:46:07.466545 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6726 23:46:07.473163 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6727 23:46:07.476384 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6728 23:46:07.479512 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6729 23:46:07.479594 ==
6730 23:46:07.483173 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 23:46:07.486192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 23:46:07.489513 ==
6733 23:46:07.489594 DQS Delay:
6734 23:46:07.489659 DQS0 = 35, DQS1 = 51
6735 23:46:07.492580 DQM Delay:
6736 23:46:07.492661 DQM0 = 6, DQM1 = 13
6737 23:46:07.496244 DQ Delay:
6738 23:46:07.496325 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6739 23:46:07.499487 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6740 23:46:07.502385 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6741 23:46:07.505797 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6742 23:46:07.505878
6743 23:46:07.505941
6744 23:46:07.509384 ==
6745 23:46:07.512544 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 23:46:07.516108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 23:46:07.516190 ==
6748 23:46:07.516254
6749 23:46:07.516312
6750 23:46:07.519124 TX Vref Scan disable
6751 23:46:07.519205 == TX Byte 0 ==
6752 23:46:07.522566 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6753 23:46:07.529093 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6754 23:46:07.529175 == TX Byte 1 ==
6755 23:46:07.532042 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 23:46:07.538844 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 23:46:07.538925 ==
6758 23:46:07.541978 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 23:46:07.545563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 23:46:07.545644 ==
6761 23:46:07.545707
6762 23:46:07.545766
6763 23:46:07.548639 TX Vref Scan disable
6764 23:46:07.548720 == TX Byte 0 ==
6765 23:46:07.551884 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6766 23:46:07.558411 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6767 23:46:07.558492 == TX Byte 1 ==
6768 23:46:07.561877 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 23:46:07.568498 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 23:46:07.568579
6771 23:46:07.568643 [DATLAT]
6772 23:46:07.571786 Freq=400, CH1 RK0
6773 23:46:07.571867
6774 23:46:07.571932 DATLAT Default: 0xf
6775 23:46:07.575516 0, 0xFFFF, sum = 0
6776 23:46:07.575599 1, 0xFFFF, sum = 0
6777 23:46:07.578709 2, 0xFFFF, sum = 0
6778 23:46:07.578791 3, 0xFFFF, sum = 0
6779 23:46:07.582011 4, 0xFFFF, sum = 0
6780 23:46:07.582093 5, 0xFFFF, sum = 0
6781 23:46:07.585033 6, 0xFFFF, sum = 0
6782 23:46:07.585115 7, 0xFFFF, sum = 0
6783 23:46:07.588423 8, 0xFFFF, sum = 0
6784 23:46:07.588505 9, 0xFFFF, sum = 0
6785 23:46:07.591371 10, 0xFFFF, sum = 0
6786 23:46:07.591453 11, 0xFFFF, sum = 0
6787 23:46:07.594948 12, 0xFFFF, sum = 0
6788 23:46:07.595030 13, 0x0, sum = 1
6789 23:46:07.597968 14, 0x0, sum = 2
6790 23:46:07.598050 15, 0x0, sum = 3
6791 23:46:07.601637 16, 0x0, sum = 4
6792 23:46:07.601719 best_step = 14
6793 23:46:07.601783
6794 23:46:07.601843 ==
6795 23:46:07.604700 Dram Type= 6, Freq= 0, CH_1, rank 0
6796 23:46:07.611644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6797 23:46:07.611725 ==
6798 23:46:07.611790 RX Vref Scan: 1
6799 23:46:07.611849
6800 23:46:07.614857 RX Vref 0 -> 0, step: 1
6801 23:46:07.614937
6802 23:46:07.618085 RX Delay -343 -> 252, step: 8
6803 23:46:07.618166
6804 23:46:07.621004 Set Vref, RX VrefLevel [Byte0]: 51
6805 23:46:07.624276 [Byte1]: 51
6806 23:46:07.628364
6807 23:46:07.628444 Final RX Vref Byte 0 = 51 to rank0
6808 23:46:07.631431 Final RX Vref Byte 1 = 51 to rank0
6809 23:46:07.634703 Final RX Vref Byte 0 = 51 to rank1
6810 23:46:07.638046 Final RX Vref Byte 1 = 51 to rank1==
6811 23:46:07.641208 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 23:46:07.647538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 23:46:07.647621 ==
6814 23:46:07.647686 DQS Delay:
6815 23:46:07.650862 DQS0 = 44, DQS1 = 52
6816 23:46:07.650932 DQM Delay:
6817 23:46:07.651031 DQM0 = 10, DQM1 = 11
6818 23:46:07.654273 DQ Delay:
6819 23:46:07.657695 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6820 23:46:07.660714 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6821 23:46:07.660795 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6822 23:46:07.664102 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6823 23:46:07.667632
6824 23:46:07.667714
6825 23:46:07.674104 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a90, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6826 23:46:07.677487 CH1 RK0: MR19=C0C, MR18=6A90
6827 23:46:07.683874 CH1_RK0: MR19=0xC0C, MR18=0x6A90, DQSOSC=391, MR23=63, INC=386, DEC=257
6828 23:46:07.683957 ==
6829 23:46:07.686942 Dram Type= 6, Freq= 0, CH_1, rank 1
6830 23:46:07.690720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 23:46:07.690802 ==
6832 23:46:07.693602 [Gating] SW mode calibration
6833 23:46:07.700188 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6834 23:46:07.706877 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6835 23:46:07.710169 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6836 23:46:07.713080 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6837 23:46:07.720149 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6838 23:46:07.723105 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6839 23:46:07.726440 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6840 23:46:07.734390 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6841 23:46:07.736651 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6842 23:46:07.739784 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 23:46:07.745974 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6844 23:46:07.749252 Total UI for P1: 0, mck2ui 16
6845 23:46:07.752536 best dqsien dly found for B0: ( 0, 14, 24)
6846 23:46:07.756302 Total UI for P1: 0, mck2ui 16
6847 23:46:07.759471 best dqsien dly found for B1: ( 0, 14, 24)
6848 23:46:07.762619 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6849 23:46:07.765664 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6850 23:46:07.765746
6851 23:46:07.769075 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6852 23:46:07.772804 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6853 23:46:07.776401 [Gating] SW calibration Done
6854 23:46:07.776482 ==
6855 23:46:07.778860 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 23:46:07.782271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 23:46:07.782353 ==
6858 23:46:07.785598 RX Vref Scan: 0
6859 23:46:07.785680
6860 23:46:07.788810 RX Vref 0 -> 0, step: 1
6861 23:46:07.788892
6862 23:46:07.792346 RX Delay -410 -> 252, step: 16
6863 23:46:07.795653 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6864 23:46:07.798962 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6865 23:46:07.802167 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6866 23:46:07.809304 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6867 23:46:07.812358 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6868 23:46:07.815685 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6869 23:46:07.818875 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6870 23:46:07.825346 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6871 23:46:07.829025 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6872 23:46:07.832013 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6873 23:46:07.835363 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6874 23:46:07.842099 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6875 23:46:07.845152 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6876 23:46:07.848556 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6877 23:46:07.854792 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6878 23:46:07.858137 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6879 23:46:07.858219 ==
6880 23:46:07.861500 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 23:46:07.865125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 23:46:07.865207 ==
6883 23:46:07.867840 DQS Delay:
6884 23:46:07.867921 DQS0 = 43, DQS1 = 51
6885 23:46:07.868006 DQM Delay:
6886 23:46:07.871477 DQM0 = 9, DQM1 = 14
6887 23:46:07.871559 DQ Delay:
6888 23:46:07.874827 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6889 23:46:07.877853 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6890 23:46:07.881243 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6891 23:46:07.885154 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6892 23:46:07.885235
6893 23:46:07.885350
6894 23:46:07.885415 ==
6895 23:46:07.887771 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 23:46:07.891239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 23:46:07.894301 ==
6898 23:46:07.894382
6899 23:46:07.894446
6900 23:46:07.894505 TX Vref Scan disable
6901 23:46:07.897867 == TX Byte 0 ==
6902 23:46:07.900825 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6903 23:46:07.904451 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6904 23:46:07.907484 == TX Byte 1 ==
6905 23:46:07.910733 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6906 23:46:07.914100 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6907 23:46:07.914182 ==
6908 23:46:07.917850 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 23:46:07.923474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 23:46:07.923556 ==
6911 23:46:07.923620
6912 23:46:07.923680
6913 23:46:07.923737 TX Vref Scan disable
6914 23:46:07.926863 == TX Byte 0 ==
6915 23:46:07.930258 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6916 23:46:07.933402 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6917 23:46:07.937073 == TX Byte 1 ==
6918 23:46:07.940249 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6919 23:46:07.943459 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6920 23:46:07.946394
6921 23:46:07.946475 [DATLAT]
6922 23:46:07.946538 Freq=400, CH1 RK1
6923 23:46:07.946620
6924 23:46:07.949854 DATLAT Default: 0xe
6925 23:46:07.949935 0, 0xFFFF, sum = 0
6926 23:46:07.953379 1, 0xFFFF, sum = 0
6927 23:46:07.953462 2, 0xFFFF, sum = 0
6928 23:46:07.956799 3, 0xFFFF, sum = 0
6929 23:46:07.956881 4, 0xFFFF, sum = 0
6930 23:46:07.959706 5, 0xFFFF, sum = 0
6931 23:46:07.963194 6, 0xFFFF, sum = 0
6932 23:46:07.963277 7, 0xFFFF, sum = 0
6933 23:46:07.966689 8, 0xFFFF, sum = 0
6934 23:46:07.966771 9, 0xFFFF, sum = 0
6935 23:46:07.970066 10, 0xFFFF, sum = 0
6936 23:46:07.970149 11, 0xFFFF, sum = 0
6937 23:46:07.972856 12, 0xFFFF, sum = 0
6938 23:46:07.972939 13, 0x0, sum = 1
6939 23:46:07.976389 14, 0x0, sum = 2
6940 23:46:07.976472 15, 0x0, sum = 3
6941 23:46:07.979702 16, 0x0, sum = 4
6942 23:46:07.979785 best_step = 14
6943 23:46:07.979850
6944 23:46:07.979910 ==
6945 23:46:07.982973 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 23:46:07.986529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 23:46:07.989712 ==
6948 23:46:07.989793 RX Vref Scan: 0
6949 23:46:07.989858
6950 23:46:07.992510 RX Vref 0 -> 0, step: 1
6951 23:46:07.992591
6952 23:46:07.996261 RX Delay -343 -> 252, step: 8
6953 23:46:08.002578 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6954 23:46:08.006174 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6955 23:46:08.009123 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6956 23:46:08.012937 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6957 23:46:08.019476 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6958 23:46:08.022391 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6959 23:46:08.025633 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6960 23:46:08.029198 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6961 23:46:08.035824 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6962 23:46:08.038637 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6963 23:46:08.042257 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6964 23:46:08.045313 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6965 23:46:08.051895 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6966 23:46:08.054974 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6967 23:46:08.058503 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6968 23:46:08.065122 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6969 23:46:08.065203 ==
6970 23:46:08.068148 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 23:46:08.071327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 23:46:08.071408 ==
6973 23:46:08.071492 DQS Delay:
6974 23:46:08.075131 DQS0 = 48, DQS1 = 52
6975 23:46:08.075212 DQM Delay:
6976 23:46:08.078311 DQM0 = 10, DQM1 = 10
6977 23:46:08.078391 DQ Delay:
6978 23:46:08.081703 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6979 23:46:08.084701 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
6980 23:46:08.087837 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6981 23:46:08.091247 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6982 23:46:08.091328
6983 23:46:08.091392
6984 23:46:08.097888 [DQSOSCAuto] RK1, (LSB)MR18= 0x7ab2, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
6985 23:46:08.101136 CH1 RK1: MR19=C0C, MR18=7AB2
6986 23:46:08.107809 CH1_RK1: MR19=0xC0C, MR18=0x7AB2, DQSOSC=387, MR23=63, INC=394, DEC=262
6987 23:46:08.111191 [RxdqsGatingPostProcess] freq 400
6988 23:46:08.117891 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6989 23:46:08.120751 best DQS0 dly(2T, 0.5T) = (0, 10)
6990 23:46:08.124461 best DQS1 dly(2T, 0.5T) = (0, 10)
6991 23:46:08.128106 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6992 23:46:08.130736 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6993 23:46:08.130817 best DQS0 dly(2T, 0.5T) = (0, 10)
6994 23:46:08.134106 best DQS1 dly(2T, 0.5T) = (0, 10)
6995 23:46:08.137259 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6996 23:46:08.140544 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6997 23:46:08.144072 Pre-setting of DQS Precalculation
6998 23:46:08.150267 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6999 23:46:08.156914 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7000 23:46:08.163380 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7001 23:46:08.163461
7002 23:46:08.163525
7003 23:46:08.166927 [Calibration Summary] 800 Mbps
7004 23:46:08.167008 CH 0, Rank 0
7005 23:46:08.170267 SW Impedance : PASS
7006 23:46:08.173504 DUTY Scan : NO K
7007 23:46:08.173585 ZQ Calibration : PASS
7008 23:46:08.176524 Jitter Meter : NO K
7009 23:46:08.180327 CBT Training : PASS
7010 23:46:08.180407 Write leveling : PASS
7011 23:46:08.183542 RX DQS gating : PASS
7012 23:46:08.186921 RX DQ/DQS(RDDQC) : PASS
7013 23:46:08.187002 TX DQ/DQS : PASS
7014 23:46:08.190036 RX DATLAT : PASS
7015 23:46:08.193186 RX DQ/DQS(Engine): PASS
7016 23:46:08.193272 TX OE : NO K
7017 23:46:08.196534 All Pass.
7018 23:46:08.196670
7019 23:46:08.196757 CH 0, Rank 1
7020 23:46:08.200120 SW Impedance : PASS
7021 23:46:08.200201 DUTY Scan : NO K
7022 23:46:08.203048 ZQ Calibration : PASS
7023 23:46:08.206290 Jitter Meter : NO K
7024 23:46:08.206370 CBT Training : PASS
7025 23:46:08.209525 Write leveling : NO K
7026 23:46:08.212967 RX DQS gating : PASS
7027 23:46:08.213047 RX DQ/DQS(RDDQC) : PASS
7028 23:46:08.216018 TX DQ/DQS : PASS
7029 23:46:08.219475 RX DATLAT : PASS
7030 23:46:08.219557 RX DQ/DQS(Engine): PASS
7031 23:46:08.222717 TX OE : NO K
7032 23:46:08.222798 All Pass.
7033 23:46:08.222862
7034 23:46:08.225784 CH 1, Rank 0
7035 23:46:08.225868 SW Impedance : PASS
7036 23:46:08.229690 DUTY Scan : NO K
7037 23:46:08.232625 ZQ Calibration : PASS
7038 23:46:08.232707 Jitter Meter : NO K
7039 23:46:08.235797 CBT Training : PASS
7040 23:46:08.239697 Write leveling : PASS
7041 23:46:08.239779 RX DQS gating : PASS
7042 23:46:08.242340 RX DQ/DQS(RDDQC) : PASS
7043 23:46:08.246359 TX DQ/DQS : PASS
7044 23:46:08.246473 RX DATLAT : PASS
7045 23:46:08.248917 RX DQ/DQS(Engine): PASS
7046 23:46:08.249015 TX OE : NO K
7047 23:46:08.252221 All Pass.
7048 23:46:08.252302
7049 23:46:08.252366 CH 1, Rank 1
7050 23:46:08.255346 SW Impedance : PASS
7051 23:46:08.258808 DUTY Scan : NO K
7052 23:46:08.258889 ZQ Calibration : PASS
7053 23:46:08.262314 Jitter Meter : NO K
7054 23:46:08.262394 CBT Training : PASS
7055 23:46:08.265606 Write leveling : NO K
7056 23:46:08.269065 RX DQS gating : PASS
7057 23:46:08.269191 RX DQ/DQS(RDDQC) : PASS
7058 23:46:08.272098 TX DQ/DQS : PASS
7059 23:46:08.275627 RX DATLAT : PASS
7060 23:46:08.275708 RX DQ/DQS(Engine): PASS
7061 23:46:08.279057 TX OE : NO K
7062 23:46:08.279138 All Pass.
7063 23:46:08.279202
7064 23:46:08.281877 DramC Write-DBI off
7065 23:46:08.285254 PER_BANK_REFRESH: Hybrid Mode
7066 23:46:08.285373 TX_TRACKING: ON
7067 23:46:08.295223 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7068 23:46:08.298556 [FAST_K] Save calibration result to emmc
7069 23:46:08.301852 dramc_set_vcore_voltage set vcore to 725000
7070 23:46:08.305132 Read voltage for 1600, 0
7071 23:46:08.305213 Vio18 = 0
7072 23:46:08.308076 Vcore = 725000
7073 23:46:08.308156 Vdram = 0
7074 23:46:08.308220 Vddq = 0
7075 23:46:08.308282 Vmddr = 0
7076 23:46:08.315118 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7077 23:46:08.321412 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7078 23:46:08.321568 MEM_TYPE=3, freq_sel=13
7079 23:46:08.324598 sv_algorithm_assistance_LP4_3733
7080 23:46:08.327755 ============ PULL DRAM RESETB DOWN ============
7081 23:46:08.334371 ========== PULL DRAM RESETB DOWN end =========
7082 23:46:08.337754 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7083 23:46:08.340790 ===================================
7084 23:46:08.344152 LPDDR4 DRAM CONFIGURATION
7085 23:46:08.347744 ===================================
7086 23:46:08.347825 EX_ROW_EN[0] = 0x0
7087 23:46:08.351625 EX_ROW_EN[1] = 0x0
7088 23:46:08.355066 LP4Y_EN = 0x0
7089 23:46:08.355147 WORK_FSP = 0x1
7090 23:46:08.357894 WL = 0x5
7091 23:46:08.357974 RL = 0x5
7092 23:46:08.360776 BL = 0x2
7093 23:46:08.360857 RPST = 0x0
7094 23:46:08.363920 RD_PRE = 0x0
7095 23:46:08.364001 WR_PRE = 0x1
7096 23:46:08.367368 WR_PST = 0x1
7097 23:46:08.367449 DBI_WR = 0x0
7098 23:46:08.370972 DBI_RD = 0x0
7099 23:46:08.371053 OTF = 0x1
7100 23:46:08.373851 ===================================
7101 23:46:08.377223 ===================================
7102 23:46:08.380748 ANA top config
7103 23:46:08.384255 ===================================
7104 23:46:08.387288 DLL_ASYNC_EN = 0
7105 23:46:08.387362 ALL_SLAVE_EN = 0
7106 23:46:08.390440 NEW_RANK_MODE = 1
7107 23:46:08.393992 DLL_IDLE_MODE = 1
7108 23:46:08.397025 LP45_APHY_COMB_EN = 1
7109 23:46:08.397097 TX_ODT_DIS = 0
7110 23:46:08.400301 NEW_8X_MODE = 1
7111 23:46:08.403719 ===================================
7112 23:46:08.407358 ===================================
7113 23:46:08.410560 data_rate = 3200
7114 23:46:08.414176 CKR = 1
7115 23:46:08.416912 DQ_P2S_RATIO = 8
7116 23:46:08.420458 ===================================
7117 23:46:08.423631 CA_P2S_RATIO = 8
7118 23:46:08.423704 DQ_CA_OPEN = 0
7119 23:46:08.426880 DQ_SEMI_OPEN = 0
7120 23:46:08.430143 CA_SEMI_OPEN = 0
7121 23:46:08.433777 CA_FULL_RATE = 0
7122 23:46:08.436709 DQ_CKDIV4_EN = 0
7123 23:46:08.440055 CA_CKDIV4_EN = 0
7124 23:46:08.440136 CA_PREDIV_EN = 0
7125 23:46:08.443653 PH8_DLY = 12
7126 23:46:08.446521 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7127 23:46:08.449991 DQ_AAMCK_DIV = 4
7128 23:46:08.453098 CA_AAMCK_DIV = 4
7129 23:46:08.456242 CA_ADMCK_DIV = 4
7130 23:46:08.456322 DQ_TRACK_CA_EN = 0
7131 23:46:08.460353 CA_PICK = 1600
7132 23:46:08.463320 CA_MCKIO = 1600
7133 23:46:08.466229 MCKIO_SEMI = 0
7134 23:46:08.469282 PLL_FREQ = 3068
7135 23:46:08.472809 DQ_UI_PI_RATIO = 32
7136 23:46:08.476099 CA_UI_PI_RATIO = 0
7137 23:46:08.479613 ===================================
7138 23:46:08.482776 ===================================
7139 23:46:08.486500 memory_type:LPDDR4
7140 23:46:08.486580 GP_NUM : 10
7141 23:46:08.489448 SRAM_EN : 1
7142 23:46:08.489528 MD32_EN : 0
7143 23:46:08.492775 ===================================
7144 23:46:08.496018 [ANA_INIT] >>>>>>>>>>>>>>
7145 23:46:08.499870 <<<<<< [CONFIGURE PHASE]: ANA_TX
7146 23:46:08.502931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7147 23:46:08.505770 ===================================
7148 23:46:08.509187 data_rate = 3200,PCW = 0X7600
7149 23:46:08.512553 ===================================
7150 23:46:08.516045 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7151 23:46:08.522352 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7152 23:46:08.525354 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7153 23:46:08.532308 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7154 23:46:08.535919 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7155 23:46:08.538724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7156 23:46:08.538798 [ANA_INIT] flow start
7157 23:46:08.541912 [ANA_INIT] PLL >>>>>>>>
7158 23:46:08.545531 [ANA_INIT] PLL <<<<<<<<
7159 23:46:08.545603 [ANA_INIT] MIDPI >>>>>>>>
7160 23:46:08.548467 [ANA_INIT] MIDPI <<<<<<<<
7161 23:46:08.552314 [ANA_INIT] DLL >>>>>>>>
7162 23:46:08.552397 [ANA_INIT] DLL <<<<<<<<
7163 23:46:08.555178 [ANA_INIT] flow end
7164 23:46:08.558402 ============ LP4 DIFF to SE enter ============
7165 23:46:08.565429 ============ LP4 DIFF to SE exit ============
7166 23:46:08.565513 [ANA_INIT] <<<<<<<<<<<<<
7167 23:46:08.568293 [Flow] Enable top DCM control >>>>>
7168 23:46:08.571519 [Flow] Enable top DCM control <<<<<
7169 23:46:08.574802 Enable DLL master slave shuffle
7170 23:46:08.582082 ==============================================================
7171 23:46:08.582166 Gating Mode config
7172 23:46:08.588011 ==============================================================
7173 23:46:08.591558 Config description:
7174 23:46:08.601132 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7175 23:46:08.608195 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7176 23:46:08.611338 SELPH_MODE 0: By rank 1: By Phase
7177 23:46:08.618117 ==============================================================
7178 23:46:08.621058 GAT_TRACK_EN = 1
7179 23:46:08.624323 RX_GATING_MODE = 2
7180 23:46:08.624427 RX_GATING_TRACK_MODE = 2
7181 23:46:08.628016 SELPH_MODE = 1
7182 23:46:08.630837 PICG_EARLY_EN = 1
7183 23:46:08.634134 VALID_LAT_VALUE = 1
7184 23:46:08.640609 ==============================================================
7185 23:46:08.644247 Enter into Gating configuration >>>>
7186 23:46:08.647345 Exit from Gating configuration <<<<
7187 23:46:08.650441 Enter into DVFS_PRE_config >>>>>
7188 23:46:08.660578 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7189 23:46:08.664526 Exit from DVFS_PRE_config <<<<<
7190 23:46:08.667218 Enter into PICG configuration >>>>
7191 23:46:08.670285 Exit from PICG configuration <<<<
7192 23:46:08.673503 [RX_INPUT] configuration >>>>>
7193 23:46:08.677218 [RX_INPUT] configuration <<<<<
7194 23:46:08.680576 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7195 23:46:08.687212 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7196 23:46:08.693875 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7197 23:46:08.700768 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7198 23:46:08.706528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7199 23:46:08.713327 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7200 23:46:08.716901 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7201 23:46:08.719789 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7202 23:46:08.723052 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7203 23:46:08.729762 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7204 23:46:08.732981 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7205 23:46:08.736334 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7206 23:46:08.739611 ===================================
7207 23:46:08.743034 LPDDR4 DRAM CONFIGURATION
7208 23:46:08.746819 ===================================
7209 23:46:08.747259 EX_ROW_EN[0] = 0x0
7210 23:46:08.749490 EX_ROW_EN[1] = 0x0
7211 23:46:08.753163 LP4Y_EN = 0x0
7212 23:46:08.753615 WORK_FSP = 0x1
7213 23:46:08.756058 WL = 0x5
7214 23:46:08.756473 RL = 0x5
7215 23:46:08.759650 BL = 0x2
7216 23:46:08.760063 RPST = 0x0
7217 23:46:08.762820 RD_PRE = 0x0
7218 23:46:08.763237 WR_PRE = 0x1
7219 23:46:08.766626 WR_PST = 0x1
7220 23:46:08.767145 DBI_WR = 0x0
7221 23:46:08.769742 DBI_RD = 0x0
7222 23:46:08.770155 OTF = 0x1
7223 23:46:08.772817 ===================================
7224 23:46:08.775852 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7225 23:46:08.782821 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7226 23:46:08.785734 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7227 23:46:08.789410 ===================================
7228 23:46:08.792606 LPDDR4 DRAM CONFIGURATION
7229 23:46:08.796107 ===================================
7230 23:46:08.796590 EX_ROW_EN[0] = 0x10
7231 23:46:08.799132 EX_ROW_EN[1] = 0x0
7232 23:46:08.802300 LP4Y_EN = 0x0
7233 23:46:08.802776 WORK_FSP = 0x1
7234 23:46:08.805832 WL = 0x5
7235 23:46:08.806431 RL = 0x5
7236 23:46:08.808784 BL = 0x2
7237 23:46:08.809221 RPST = 0x0
7238 23:46:08.812362 RD_PRE = 0x0
7239 23:46:08.812842 WR_PRE = 0x1
7240 23:46:08.815914 WR_PST = 0x1
7241 23:46:08.816378 DBI_WR = 0x0
7242 23:46:08.819717 DBI_RD = 0x0
7243 23:46:08.820220 OTF = 0x1
7244 23:46:08.822373 ===================================
7245 23:46:08.828756 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7246 23:46:08.829239 ==
7247 23:46:08.831985 Dram Type= 6, Freq= 0, CH_0, rank 0
7248 23:46:08.835343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7249 23:46:08.838439 ==
7250 23:46:08.838925 [Duty_Offset_Calibration]
7251 23:46:08.842273 B0:2 B1:0 CA:4
7252 23:46:08.842824
7253 23:46:08.845048 [DutyScan_Calibration_Flow] k_type=0
7254 23:46:08.853661
7255 23:46:08.854075 ==CLK 0==
7256 23:46:08.856769 Final CLK duty delay cell = -4
7257 23:46:08.859875 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7258 23:46:08.863453 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7259 23:46:08.866999 [-4] AVG Duty = 4937%(X100)
7260 23:46:08.867564
7261 23:46:08.870560 CH0 CLK Duty spec in!! Max-Min= 187%
7262 23:46:08.874034 [DutyScan_Calibration_Flow] ====Done====
7263 23:46:08.874641
7264 23:46:08.876926 [DutyScan_Calibration_Flow] k_type=1
7265 23:46:08.893626
7266 23:46:08.894216 ==DQS 0 ==
7267 23:46:08.897107 Final DQS duty delay cell = 0
7268 23:46:08.900270 [0] MAX Duty = 5218%(X100), DQS PI = 38
7269 23:46:08.903548 [0] MIN Duty = 5093%(X100), DQS PI = 12
7270 23:46:08.906544 [0] AVG Duty = 5155%(X100)
7271 23:46:08.907029
7272 23:46:08.907549 ==DQS 1 ==
7273 23:46:08.910569 Final DQS duty delay cell = 0
7274 23:46:08.913358 [0] MAX Duty = 5156%(X100), DQS PI = 0
7275 23:46:08.916456 [0] MIN Duty = 4969%(X100), DQS PI = 10
7276 23:46:08.920346 [0] AVG Duty = 5062%(X100)
7277 23:46:08.920829
7278 23:46:08.923364 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7279 23:46:08.923853
7280 23:46:08.926514 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7281 23:46:08.929933 [DutyScan_Calibration_Flow] ====Done====
7282 23:46:08.930450
7283 23:46:08.933180 [DutyScan_Calibration_Flow] k_type=3
7284 23:46:08.951292
7285 23:46:08.951706 ==DQM 0 ==
7286 23:46:08.954281 Final DQM duty delay cell = 0
7287 23:46:08.957595 [0] MAX Duty = 5124%(X100), DQS PI = 22
7288 23:46:08.960608 [0] MIN Duty = 4844%(X100), DQS PI = 54
7289 23:46:08.964470 [0] AVG Duty = 4984%(X100)
7290 23:46:08.964884
7291 23:46:08.965235 ==DQM 1 ==
7292 23:46:08.967400 Final DQM duty delay cell = 0
7293 23:46:08.970915 [0] MAX Duty = 5000%(X100), DQS PI = 2
7294 23:46:08.974156 [0] MIN Duty = 4844%(X100), DQS PI = 14
7295 23:46:08.977146 [0] AVG Duty = 4922%(X100)
7296 23:46:08.977620
7297 23:46:08.980452 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7298 23:46:08.980870
7299 23:46:08.983802 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7300 23:46:08.987309 [DutyScan_Calibration_Flow] ====Done====
7301 23:46:08.987727
7302 23:46:08.990000 [DutyScan_Calibration_Flow] k_type=2
7303 23:46:09.008317
7304 23:46:09.008933 ==DQ 0 ==
7305 23:46:09.011424 Final DQ duty delay cell = 0
7306 23:46:09.014424 [0] MAX Duty = 5156%(X100), DQS PI = 22
7307 23:46:09.018120 [0] MIN Duty = 4938%(X100), DQS PI = 12
7308 23:46:09.020978 [0] AVG Duty = 5047%(X100)
7309 23:46:09.021598
7310 23:46:09.022150 ==DQ 1 ==
7311 23:46:09.025561 Final DQ duty delay cell = 0
7312 23:46:09.027620 [0] MAX Duty = 5187%(X100), DQS PI = 2
7313 23:46:09.031099 [0] MIN Duty = 4907%(X100), DQS PI = 32
7314 23:46:09.031571 [0] AVG Duty = 5047%(X100)
7315 23:46:09.034545
7316 23:46:09.037715 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7317 23:46:09.038206
7318 23:46:09.041317 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7319 23:46:09.044222 [DutyScan_Calibration_Flow] ====Done====
7320 23:46:09.044804 ==
7321 23:46:09.048948 Dram Type= 6, Freq= 0, CH_1, rank 0
7322 23:46:09.050577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7323 23:46:09.051010 ==
7324 23:46:09.054692 [Duty_Offset_Calibration]
7325 23:46:09.055186 B0:0 B1:-1 CA:3
7326 23:46:09.055585
7327 23:46:09.057502 [DutyScan_Calibration_Flow] k_type=0
7328 23:46:09.067893
7329 23:46:09.068440 ==CLK 0==
7330 23:46:09.070600 Final CLK duty delay cell = -4
7331 23:46:09.074200 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7332 23:46:09.077170 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7333 23:46:09.080506 [-4] AVG Duty = 4922%(X100)
7334 23:46:09.080979
7335 23:46:09.083722 CH1 CLK Duty spec in!! Max-Min= 156%
7336 23:46:09.087011 [DutyScan_Calibration_Flow] ====Done====
7337 23:46:09.087625
7338 23:46:09.090636 [DutyScan_Calibration_Flow] k_type=1
7339 23:46:09.106656
7340 23:46:09.107157 ==DQS 0 ==
7341 23:46:09.110028 Final DQS duty delay cell = 0
7342 23:46:09.112978 [0] MAX Duty = 5218%(X100), DQS PI = 30
7343 23:46:09.116743 [0] MIN Duty = 4907%(X100), DQS PI = 40
7344 23:46:09.120298 [0] AVG Duty = 5062%(X100)
7345 23:46:09.120892
7346 23:46:09.121473 ==DQS 1 ==
7347 23:46:09.122924 Final DQS duty delay cell = -4
7348 23:46:09.126246 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7349 23:46:09.129648 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7350 23:46:09.132810 [-4] AVG Duty = 4922%(X100)
7351 23:46:09.133339
7352 23:46:09.136383 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7353 23:46:09.136973
7354 23:46:09.139499 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7355 23:46:09.142779 [DutyScan_Calibration_Flow] ====Done====
7356 23:46:09.143271
7357 23:46:09.146181 [DutyScan_Calibration_Flow] k_type=3
7358 23:46:09.163893
7359 23:46:09.164386 ==DQM 0 ==
7360 23:46:09.167023 Final DQM duty delay cell = 0
7361 23:46:09.170778 [0] MAX Duty = 5031%(X100), DQS PI = 30
7362 23:46:09.174150 [0] MIN Duty = 4782%(X100), DQS PI = 38
7363 23:46:09.177127 [0] AVG Duty = 4906%(X100)
7364 23:46:09.177583
7365 23:46:09.178016 ==DQM 1 ==
7366 23:46:09.180808 Final DQM duty delay cell = 0
7367 23:46:09.183931 [0] MAX Duty = 4969%(X100), DQS PI = 30
7368 23:46:09.187162 [0] MIN Duty = 4844%(X100), DQS PI = 0
7369 23:46:09.190481 [0] AVG Duty = 4906%(X100)
7370 23:46:09.190898
7371 23:46:09.193565 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7372 23:46:09.193986
7373 23:46:09.196647 CH1 DQM 1 Duty spec in!! Max-Min= 125%
7374 23:46:09.200120 [DutyScan_Calibration_Flow] ====Done====
7375 23:46:09.200539
7376 23:46:09.203330 [DutyScan_Calibration_Flow] k_type=2
7377 23:46:09.219884
7378 23:46:09.220476 ==DQ 0 ==
7379 23:46:09.223711 Final DQ duty delay cell = -4
7380 23:46:09.226602 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7381 23:46:09.230196 [-4] MIN Duty = 4813%(X100), DQS PI = 20
7382 23:46:09.232872 [-4] AVG Duty = 4891%(X100)
7383 23:46:09.233406
7384 23:46:09.233845 ==DQ 1 ==
7385 23:46:09.236535 Final DQ duty delay cell = 0
7386 23:46:09.239909 [0] MAX Duty = 5031%(X100), DQS PI = 32
7387 23:46:09.243451 [0] MIN Duty = 4875%(X100), DQS PI = 58
7388 23:46:09.246136 [0] AVG Duty = 4953%(X100)
7389 23:46:09.246620
7390 23:46:09.249512 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7391 23:46:09.250000
7392 23:46:09.253050 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7393 23:46:09.256876 [DutyScan_Calibration_Flow] ====Done====
7394 23:46:09.259266 nWR fixed to 30
7395 23:46:09.263314 [ModeRegInit_LP4] CH0 RK0
7396 23:46:09.263822 [ModeRegInit_LP4] CH0 RK1
7397 23:46:09.266465 [ModeRegInit_LP4] CH1 RK0
7398 23:46:09.269699 [ModeRegInit_LP4] CH1 RK1
7399 23:46:09.270112 match AC timing 5
7400 23:46:09.275816 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7401 23:46:09.279473 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7402 23:46:09.282701 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7403 23:46:09.289574 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7404 23:46:09.293047 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7405 23:46:09.293634 [MiockJmeterHQA]
7406 23:46:09.295688
7407 23:46:09.299044 [DramcMiockJmeter] u1RxGatingPI = 0
7408 23:46:09.299508 0 : 4258, 4029
7409 23:46:09.299934 4 : 4365, 4140
7410 23:46:09.302140 8 : 4252, 4027
7411 23:46:09.302721 12 : 4253, 4027
7412 23:46:09.305648 16 : 4253, 4026
7413 23:46:09.306162 20 : 4252, 4027
7414 23:46:09.309058 24 : 4255, 4029
7415 23:46:09.309639 28 : 4253, 4026
7416 23:46:09.310172 32 : 4253, 4027
7417 23:46:09.312563 36 : 4365, 4140
7418 23:46:09.312999 40 : 4252, 4027
7419 23:46:09.315492 44 : 4255, 4029
7420 23:46:09.316099 48 : 4252, 4027
7421 23:46:09.319665 52 : 4360, 4138
7422 23:46:09.320173 56 : 4250, 4027
7423 23:46:09.322453 60 : 4361, 4137
7424 23:46:09.322956 64 : 4249, 4027
7425 23:46:09.323353 68 : 4250, 4026
7426 23:46:09.325201 72 : 4250, 4027
7427 23:46:09.325704 76 : 4252, 4029
7428 23:46:09.328995 80 : 4360, 4138
7429 23:46:09.329601 84 : 4249, 4027
7430 23:46:09.332068 88 : 4361, 4137
7431 23:46:09.332484 92 : 4250, 4027
7432 23:46:09.335853 96 : 4250, 2701
7433 23:46:09.336531 100 : 4250, 0
7434 23:46:09.337077 104 : 4253, 0
7435 23:46:09.338456 108 : 4255, 0
7436 23:46:09.339144 112 : 4252, 0
7437 23:46:09.339647 116 : 4250, 0
7438 23:46:09.341734 120 : 4253, 0
7439 23:46:09.342198 124 : 4360, 0
7440 23:46:09.345163 128 : 4250, 0
7441 23:46:09.345698 132 : 4249, 0
7442 23:46:09.346113 136 : 4363, 0
7443 23:46:09.348302 140 : 4250, 0
7444 23:46:09.348925 144 : 4361, 0
7445 23:46:09.351946 148 : 4250, 0
7446 23:46:09.352597 152 : 4250, 0
7447 23:46:09.352938 156 : 4249, 0
7448 23:46:09.355006 160 : 4360, 0
7449 23:46:09.355409 164 : 4250, 0
7450 23:46:09.358775 168 : 4251, 0
7451 23:46:09.359071 172 : 4252, 0
7452 23:46:09.359309 176 : 4361, 0
7453 23:46:09.361408 180 : 4360, 0
7454 23:46:09.361709 184 : 4253, 0
7455 23:46:09.364450 188 : 4361, 0
7456 23:46:09.364751 192 : 4361, 0
7457 23:46:09.364988 196 : 4250, 0
7458 23:46:09.368208 200 : 4250, 0
7459 23:46:09.368506 204 : 4250, 0
7460 23:46:09.371666 208 : 4250, 0
7461 23:46:09.371950 212 : 4363, 0
7462 23:46:09.372016 216 : 4250, 0
7463 23:46:09.374795 220 : 4250, 380
7464 23:46:09.374877 224 : 4361, 4118
7465 23:46:09.377841 228 : 4360, 4138
7466 23:46:09.377923 232 : 4250, 4027
7467 23:46:09.380872 236 : 4360, 4137
7468 23:46:09.380954 240 : 4360, 4138
7469 23:46:09.384776 244 : 4250, 4027
7470 23:46:09.384858 248 : 4250, 4027
7471 23:46:09.387466 252 : 4250, 4027
7472 23:46:09.387549 256 : 4250, 4027
7473 23:46:09.387614 260 : 4250, 4027
7474 23:46:09.390759 264 : 4250, 4027
7475 23:46:09.390842 268 : 4250, 4027
7476 23:46:09.394377 272 : 4250, 4026
7477 23:46:09.394459 276 : 4360, 4138
7478 23:46:09.397616 280 : 4360, 4138
7479 23:46:09.397699 284 : 4250, 4026
7480 23:46:09.400743 288 : 4361, 4137
7481 23:46:09.400852 292 : 4360, 4138
7482 23:46:09.404264 296 : 4250, 4027
7483 23:46:09.404369 300 : 4250, 4027
7484 23:46:09.407462 304 : 4250, 4026
7485 23:46:09.407550 308 : 4250, 4027
7486 23:46:09.411003 312 : 4250, 4027
7487 23:46:09.411107 316 : 4249, 4027
7488 23:46:09.413810 320 : 4250, 4027
7489 23:46:09.413892 324 : 4250, 4027
7490 23:46:09.413956 328 : 4360, 4138
7491 23:46:09.417245 332 : 4361, 4050
7492 23:46:09.417365 336 : 4250, 1712
7493 23:46:09.417430
7494 23:46:09.420388 MIOCK jitter meter ch=0
7495 23:46:09.420469
7496 23:46:09.423814 1T = (336-100) = 236 dly cells
7497 23:46:09.430832 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7498 23:46:09.430947 ==
7499 23:46:09.433889 Dram Type= 6, Freq= 0, CH_0, rank 0
7500 23:46:09.437145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7501 23:46:09.437245 ==
7502 23:46:09.444195 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7503 23:46:09.447088 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7504 23:46:09.450208 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7505 23:46:09.456750 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7506 23:46:09.466177 [CA 0] Center 44 (14~74) winsize 61
7507 23:46:09.469826 [CA 1] Center 43 (13~74) winsize 62
7508 23:46:09.472528 [CA 2] Center 38 (9~68) winsize 60
7509 23:46:09.476097 [CA 3] Center 38 (9~68) winsize 60
7510 23:46:09.479291 [CA 4] Center 36 (7~66) winsize 60
7511 23:46:09.482909 [CA 5] Center 36 (6~66) winsize 61
7512 23:46:09.482990
7513 23:46:09.485987 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7514 23:46:09.486069
7515 23:46:09.492360 [CATrainingPosCal] consider 1 rank data
7516 23:46:09.492441 u2DelayCellTimex100 = 275/100 ps
7517 23:46:09.499101 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7518 23:46:09.502170 CA1 delay=43 (13~74),Diff = 7 PI (24 cell)
7519 23:46:09.505692 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7520 23:46:09.509157 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7521 23:46:09.512058 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7522 23:46:09.515538 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7523 23:46:09.515619
7524 23:46:09.518644 CA PerBit enable=1, Macro0, CA PI delay=36
7525 23:46:09.518726
7526 23:46:09.522223 [CBTSetCACLKResult] CA Dly = 36
7527 23:46:09.525336 CS Dly: 11 (0~42)
7528 23:46:09.528609 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7529 23:46:09.532114 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7530 23:46:09.532200 ==
7531 23:46:09.535310 Dram Type= 6, Freq= 0, CH_0, rank 1
7532 23:46:09.541808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7533 23:46:09.541890 ==
7534 23:46:09.545014 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7535 23:46:09.552304 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7536 23:46:09.554654 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7537 23:46:09.561154 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7538 23:46:09.569946 [CA 0] Center 44 (14~75) winsize 62
7539 23:46:09.572720 [CA 1] Center 44 (14~74) winsize 61
7540 23:46:09.576271 [CA 2] Center 39 (10~69) winsize 60
7541 23:46:09.579442 [CA 3] Center 39 (10~68) winsize 59
7542 23:46:09.582608 [CA 4] Center 37 (7~67) winsize 61
7543 23:46:09.585927 [CA 5] Center 36 (7~66) winsize 60
7544 23:46:09.586008
7545 23:46:09.589552 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7546 23:46:09.589634
7547 23:46:09.596474 [CATrainingPosCal] consider 2 rank data
7548 23:46:09.596555 u2DelayCellTimex100 = 275/100 ps
7549 23:46:09.602278 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7550 23:46:09.606309 CA1 delay=44 (14~74),Diff = 8 PI (28 cell)
7551 23:46:09.608837 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7552 23:46:09.612537 CA3 delay=39 (10~68),Diff = 3 PI (10 cell)
7553 23:46:09.615636 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7554 23:46:09.619347 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7555 23:46:09.619467
7556 23:46:09.622642 CA PerBit enable=1, Macro0, CA PI delay=36
7557 23:46:09.625249
7558 23:46:09.625353 [CBTSetCACLKResult] CA Dly = 36
7559 23:46:09.629505 CS Dly: 11 (0~43)
7560 23:46:09.632010 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7561 23:46:09.635746 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7562 23:46:09.635828
7563 23:46:09.642152 ----->DramcWriteLeveling(PI) begin...
7564 23:46:09.642234 ==
7565 23:46:09.645639 Dram Type= 6, Freq= 0, CH_0, rank 0
7566 23:46:09.648584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7567 23:46:09.648666 ==
7568 23:46:09.651930 Write leveling (Byte 0): 33 => 33
7569 23:46:09.655693 Write leveling (Byte 1): 28 => 28
7570 23:46:09.658571 DramcWriteLeveling(PI) end<-----
7571 23:46:09.658652
7572 23:46:09.658715 ==
7573 23:46:09.661834 Dram Type= 6, Freq= 0, CH_0, rank 0
7574 23:46:09.665489 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7575 23:46:09.665571 ==
7576 23:46:09.668593 [Gating] SW mode calibration
7577 23:46:09.675063 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7578 23:46:09.681900 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7579 23:46:09.684735 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 23:46:09.687757 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 23:46:09.694943 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7582 23:46:09.697596 1 4 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
7583 23:46:09.701066 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7584 23:46:09.707805 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7585 23:46:09.711282 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7586 23:46:09.714535 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7587 23:46:09.720996 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7588 23:46:09.724407 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7589 23:46:09.728072 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7590 23:46:09.733696 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
7591 23:46:09.737498 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7592 23:46:09.740534 1 5 20 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
7593 23:46:09.746744 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7594 23:46:09.750456 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7595 23:46:09.753540 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7596 23:46:09.760227 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7597 23:46:09.763492 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7598 23:46:09.766854 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7599 23:46:09.773221 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7600 23:46:09.776918 1 6 20 | B1->B0 | 3938 4646 | 1 0 | (1 1) (0 0)
7601 23:46:09.783135 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7602 23:46:09.786767 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 23:46:09.790110 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 23:46:09.796510 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7605 23:46:09.800049 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7606 23:46:09.803220 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7607 23:46:09.809403 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7608 23:46:09.812524 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7609 23:46:09.815964 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7610 23:46:09.822473 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7611 23:46:09.826038 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7612 23:46:09.829190 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 23:46:09.836074 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 23:46:09.839056 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 23:46:09.842224 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 23:46:09.849139 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 23:46:09.852117 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 23:46:09.855591 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 23:46:09.862286 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 23:46:09.865641 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 23:46:09.868940 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7622 23:46:09.875095 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7623 23:46:09.878296 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7624 23:46:09.881680 Total UI for P1: 0, mck2ui 16
7625 23:46:09.885242 best dqsien dly found for B0: ( 1, 9, 10)
7626 23:46:09.888244 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7627 23:46:09.894732 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 23:46:09.894834 Total UI for P1: 0, mck2ui 16
7629 23:46:09.901556 best dqsien dly found for B1: ( 1, 9, 20)
7630 23:46:09.904688 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7631 23:46:09.908010 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7632 23:46:09.908091
7633 23:46:09.911683 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7634 23:46:09.914630 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7635 23:46:09.918188 [Gating] SW calibration Done
7636 23:46:09.918269 ==
7637 23:46:09.921653 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 23:46:09.924599 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 23:46:09.924681 ==
7640 23:46:09.928028 RX Vref Scan: 0
7641 23:46:09.928109
7642 23:46:09.928173 RX Vref 0 -> 0, step: 1
7643 23:46:09.931209
7644 23:46:09.931290 RX Delay 0 -> 252, step: 8
7645 23:46:09.934458 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7646 23:46:09.940909 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7647 23:46:09.944140 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7648 23:46:09.947765 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7649 23:46:09.950693 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7650 23:46:09.954485 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7651 23:46:09.960613 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7652 23:46:09.964043 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7653 23:46:09.967491 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7654 23:46:09.971168 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7655 23:46:09.976948 iDelay=192, Bit 10, Center 123 (72 ~ 175) 104
7656 23:46:09.980754 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7657 23:46:09.983602 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7658 23:46:09.986944 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7659 23:46:09.990189 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7660 23:46:09.996804 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7661 23:46:09.996885 ==
7662 23:46:10.000411 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 23:46:10.003567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 23:46:10.003649 ==
7665 23:46:10.003713 DQS Delay:
7666 23:46:10.006811 DQS0 = 0, DQS1 = 0
7667 23:46:10.006892 DQM Delay:
7668 23:46:10.010213 DQM0 = 131, DQM1 = 126
7669 23:46:10.010294 DQ Delay:
7670 23:46:10.013310 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7671 23:46:10.016587 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7672 23:46:10.019798 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
7673 23:46:10.026613 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7674 23:46:10.026694
7675 23:46:10.026757
7676 23:46:10.026817 ==
7677 23:46:10.029684 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 23:46:10.033022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 23:46:10.033103 ==
7680 23:46:10.033167
7681 23:46:10.033227
7682 23:46:10.036180 TX Vref Scan disable
7683 23:46:10.036260 == TX Byte 0 ==
7684 23:46:10.042978 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7685 23:46:10.046021 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7686 23:46:10.046102 == TX Byte 1 ==
7687 23:46:10.052896 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7688 23:46:10.056195 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7689 23:46:10.056309 ==
7690 23:46:10.059384 Dram Type= 6, Freq= 0, CH_0, rank 0
7691 23:46:10.062556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7692 23:46:10.062638 ==
7693 23:46:10.077077
7694 23:46:10.080230 TX Vref early break, caculate TX vref
7695 23:46:10.083942 TX Vref=16, minBit 8, minWin=21, winSum=372
7696 23:46:10.087566 TX Vref=18, minBit 8, minWin=22, winSum=384
7697 23:46:10.090276 TX Vref=20, minBit 1, minWin=23, winSum=390
7698 23:46:10.093247 TX Vref=22, minBit 4, minWin=24, winSum=401
7699 23:46:10.097155 TX Vref=24, minBit 1, minWin=25, winSum=414
7700 23:46:10.103296 TX Vref=26, minBit 1, minWin=25, winSum=420
7701 23:46:10.106849 TX Vref=28, minBit 7, minWin=25, winSum=425
7702 23:46:10.109953 TX Vref=30, minBit 4, minWin=24, winSum=420
7703 23:46:10.113192 TX Vref=32, minBit 4, minWin=24, winSum=408
7704 23:46:10.116747 TX Vref=34, minBit 0, minWin=24, winSum=398
7705 23:46:10.122801 [TxChooseVref] Worse bit 7, Min win 25, Win sum 425, Final Vref 28
7706 23:46:10.122882
7707 23:46:10.126090 Final TX Range 0 Vref 28
7708 23:46:10.126172
7709 23:46:10.126236 ==
7710 23:46:10.129552 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 23:46:10.132804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 23:46:10.132885 ==
7713 23:46:10.132949
7714 23:46:10.133008
7715 23:46:10.136479 TX Vref Scan disable
7716 23:46:10.143302 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7717 23:46:10.143383 == TX Byte 0 ==
7718 23:46:10.145942 u2DelayCellOfst[0]=10 cells (3 PI)
7719 23:46:10.149206 u2DelayCellOfst[1]=14 cells (4 PI)
7720 23:46:10.152467 u2DelayCellOfst[2]=7 cells (2 PI)
7721 23:46:10.156803 u2DelayCellOfst[3]=10 cells (3 PI)
7722 23:46:10.159481 u2DelayCellOfst[4]=7 cells (2 PI)
7723 23:46:10.162797 u2DelayCellOfst[5]=0 cells (0 PI)
7724 23:46:10.166373 u2DelayCellOfst[6]=14 cells (4 PI)
7725 23:46:10.169359 u2DelayCellOfst[7]=14 cells (4 PI)
7726 23:46:10.172507 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7727 23:46:10.175829 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7728 23:46:10.179460 == TX Byte 1 ==
7729 23:46:10.182330 u2DelayCellOfst[8]=0 cells (0 PI)
7730 23:46:10.185871 u2DelayCellOfst[9]=0 cells (0 PI)
7731 23:46:10.185952 u2DelayCellOfst[10]=7 cells (2 PI)
7732 23:46:10.189219 u2DelayCellOfst[11]=3 cells (1 PI)
7733 23:46:10.192076 u2DelayCellOfst[12]=10 cells (3 PI)
7734 23:46:10.195851 u2DelayCellOfst[13]=10 cells (3 PI)
7735 23:46:10.198995 u2DelayCellOfst[14]=14 cells (4 PI)
7736 23:46:10.202421 u2DelayCellOfst[15]=10 cells (3 PI)
7737 23:46:10.208944 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7738 23:46:10.212003 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7739 23:46:10.212090 DramC Write-DBI on
7740 23:46:10.212154 ==
7741 23:46:10.215667 Dram Type= 6, Freq= 0, CH_0, rank 0
7742 23:46:10.222240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7743 23:46:10.222347 ==
7744 23:46:10.222439
7745 23:46:10.222526
7746 23:46:10.225188 TX Vref Scan disable
7747 23:46:10.225314 == TX Byte 0 ==
7748 23:46:10.231959 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7749 23:46:10.232031 == TX Byte 1 ==
7750 23:46:10.235136 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7751 23:46:10.238839 DramC Write-DBI off
7752 23:46:10.238908
7753 23:46:10.238967 [DATLAT]
7754 23:46:10.242020 Freq=1600, CH0 RK0
7755 23:46:10.242088
7756 23:46:10.242146 DATLAT Default: 0xf
7757 23:46:10.245179 0, 0xFFFF, sum = 0
7758 23:46:10.245297 1, 0xFFFF, sum = 0
7759 23:46:10.248384 2, 0xFFFF, sum = 0
7760 23:46:10.248480 3, 0xFFFF, sum = 0
7761 23:46:10.251670 4, 0xFFFF, sum = 0
7762 23:46:10.251739 5, 0xFFFF, sum = 0
7763 23:46:10.254700 6, 0xFFFF, sum = 0
7764 23:46:10.257918 7, 0xFFFF, sum = 0
7765 23:46:10.257998 8, 0xFFFF, sum = 0
7766 23:46:10.261729 9, 0xFFFF, sum = 0
7767 23:46:10.261804 10, 0xFFFF, sum = 0
7768 23:46:10.264895 11, 0xFFFF, sum = 0
7769 23:46:10.264993 12, 0xFFFF, sum = 0
7770 23:46:10.268165 13, 0xFFFF, sum = 0
7771 23:46:10.268261 14, 0x0, sum = 1
7772 23:46:10.272090 15, 0x0, sum = 2
7773 23:46:10.272192 16, 0x0, sum = 3
7774 23:46:10.274327 17, 0x0, sum = 4
7775 23:46:10.274407 best_step = 15
7776 23:46:10.274467
7777 23:46:10.274523 ==
7778 23:46:10.278097 Dram Type= 6, Freq= 0, CH_0, rank 0
7779 23:46:10.281353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7780 23:46:10.284725 ==
7781 23:46:10.284793 RX Vref Scan: 1
7782 23:46:10.284852
7783 23:46:10.287995 Set Vref Range= 24 -> 127
7784 23:46:10.288096
7785 23:46:10.290811 RX Vref 24 -> 127, step: 1
7786 23:46:10.290879
7787 23:46:10.290955 RX Delay 11 -> 252, step: 4
7788 23:46:10.291013
7789 23:46:10.294684 Set Vref, RX VrefLevel [Byte0]: 24
7790 23:46:10.297273 [Byte1]: 24
7791 23:46:10.301366
7792 23:46:10.301436 Set Vref, RX VrefLevel [Byte0]: 25
7793 23:46:10.304622 [Byte1]: 25
7794 23:46:10.309231
7795 23:46:10.309331 Set Vref, RX VrefLevel [Byte0]: 26
7796 23:46:10.312743 [Byte1]: 26
7797 23:46:10.316592
7798 23:46:10.316694 Set Vref, RX VrefLevel [Byte0]: 27
7799 23:46:10.320310 [Byte1]: 27
7800 23:46:10.324249
7801 23:46:10.324351 Set Vref, RX VrefLevel [Byte0]: 28
7802 23:46:10.327954 [Byte1]: 28
7803 23:46:10.331953
7804 23:46:10.332048 Set Vref, RX VrefLevel [Byte0]: 29
7805 23:46:10.335848 [Byte1]: 29
7806 23:46:10.339422
7807 23:46:10.339493 Set Vref, RX VrefLevel [Byte0]: 30
7808 23:46:10.342745 [Byte1]: 30
7809 23:46:10.347593
7810 23:46:10.347698 Set Vref, RX VrefLevel [Byte0]: 31
7811 23:46:10.350273 [Byte1]: 31
7812 23:46:10.354767
7813 23:46:10.354845 Set Vref, RX VrefLevel [Byte0]: 32
7814 23:46:10.358698 [Byte1]: 32
7815 23:46:10.362725
7816 23:46:10.362796 Set Vref, RX VrefLevel [Byte0]: 33
7817 23:46:10.365496 [Byte1]: 33
7818 23:46:10.370012
7819 23:46:10.370117 Set Vref, RX VrefLevel [Byte0]: 34
7820 23:46:10.373527 [Byte1]: 34
7821 23:46:10.377848
7822 23:46:10.377945 Set Vref, RX VrefLevel [Byte0]: 35
7823 23:46:10.382146 [Byte1]: 35
7824 23:46:10.385292
7825 23:46:10.385381 Set Vref, RX VrefLevel [Byte0]: 36
7826 23:46:10.388512 [Byte1]: 36
7827 23:46:10.393022
7828 23:46:10.393119 Set Vref, RX VrefLevel [Byte0]: 37
7829 23:46:10.396428 [Byte1]: 37
7830 23:46:10.401120
7831 23:46:10.401217 Set Vref, RX VrefLevel [Byte0]: 38
7832 23:46:10.403683 [Byte1]: 38
7833 23:46:10.408166
7834 23:46:10.408263 Set Vref, RX VrefLevel [Byte0]: 39
7835 23:46:10.411336 [Byte1]: 39
7836 23:46:10.415732
7837 23:46:10.415802 Set Vref, RX VrefLevel [Byte0]: 40
7838 23:46:10.418843 [Byte1]: 40
7839 23:46:10.423124
7840 23:46:10.423218 Set Vref, RX VrefLevel [Byte0]: 41
7841 23:46:10.426346 [Byte1]: 41
7842 23:46:10.430695
7843 23:46:10.430766 Set Vref, RX VrefLevel [Byte0]: 42
7844 23:46:10.434403 [Byte1]: 42
7845 23:46:10.438655
7846 23:46:10.438725 Set Vref, RX VrefLevel [Byte0]: 43
7847 23:46:10.442088 [Byte1]: 43
7848 23:46:10.446116
7849 23:46:10.446196 Set Vref, RX VrefLevel [Byte0]: 44
7850 23:46:10.449587 [Byte1]: 44
7851 23:46:10.453972
7852 23:46:10.454052 Set Vref, RX VrefLevel [Byte0]: 45
7853 23:46:10.457038 [Byte1]: 45
7854 23:46:10.461727
7855 23:46:10.461807 Set Vref, RX VrefLevel [Byte0]: 46
7856 23:46:10.464477 [Byte1]: 46
7857 23:46:10.469558
7858 23:46:10.469717 Set Vref, RX VrefLevel [Byte0]: 47
7859 23:46:10.472683 [Byte1]: 47
7860 23:46:10.476692
7861 23:46:10.476773 Set Vref, RX VrefLevel [Byte0]: 48
7862 23:46:10.479695 [Byte1]: 48
7863 23:46:10.484208
7864 23:46:10.484289 Set Vref, RX VrefLevel [Byte0]: 49
7865 23:46:10.487753 [Byte1]: 49
7866 23:46:10.491954
7867 23:46:10.492034 Set Vref, RX VrefLevel [Byte0]: 50
7868 23:46:10.494897 [Byte1]: 50
7869 23:46:10.499368
7870 23:46:10.499449 Set Vref, RX VrefLevel [Byte0]: 51
7871 23:46:10.502482 [Byte1]: 51
7872 23:46:10.507119
7873 23:46:10.507200 Set Vref, RX VrefLevel [Byte0]: 52
7874 23:46:10.510159 [Byte1]: 52
7875 23:46:10.514474
7876 23:46:10.514555 Set Vref, RX VrefLevel [Byte0]: 53
7877 23:46:10.518303 [Byte1]: 53
7878 23:46:10.522371
7879 23:46:10.522452 Set Vref, RX VrefLevel [Byte0]: 54
7880 23:46:10.525770 [Byte1]: 54
7881 23:46:10.529972
7882 23:46:10.530052 Set Vref, RX VrefLevel [Byte0]: 55
7883 23:46:10.533174 [Byte1]: 55
7884 23:46:10.537472
7885 23:46:10.537553 Set Vref, RX VrefLevel [Byte0]: 56
7886 23:46:10.541457 [Byte1]: 56
7887 23:46:10.545107
7888 23:46:10.545187 Set Vref, RX VrefLevel [Byte0]: 57
7889 23:46:10.548494 [Byte1]: 57
7890 23:46:10.552802
7891 23:46:10.552882 Set Vref, RX VrefLevel [Byte0]: 58
7892 23:46:10.556159 [Byte1]: 58
7893 23:46:10.560630
7894 23:46:10.560712 Set Vref, RX VrefLevel [Byte0]: 59
7895 23:46:10.563489 [Byte1]: 59
7896 23:46:10.567733
7897 23:46:10.567813 Set Vref, RX VrefLevel [Byte0]: 60
7898 23:46:10.571371 [Byte1]: 60
7899 23:46:10.575746
7900 23:46:10.575827 Set Vref, RX VrefLevel [Byte0]: 61
7901 23:46:10.579272 [Byte1]: 61
7902 23:46:10.583266
7903 23:46:10.583346 Set Vref, RX VrefLevel [Byte0]: 62
7904 23:46:10.586240 [Byte1]: 62
7905 23:46:10.590894
7906 23:46:10.590975 Set Vref, RX VrefLevel [Byte0]: 63
7907 23:46:10.593923 [Byte1]: 63
7908 23:46:10.598426
7909 23:46:10.598507 Set Vref, RX VrefLevel [Byte0]: 64
7910 23:46:10.602095 [Byte1]: 64
7911 23:46:10.606411
7912 23:46:10.606491 Set Vref, RX VrefLevel [Byte0]: 65
7913 23:46:10.609492 [Byte1]: 65
7914 23:46:10.613690
7915 23:46:10.613770 Set Vref, RX VrefLevel [Byte0]: 66
7916 23:46:10.617523 [Byte1]: 66
7917 23:46:10.621179
7918 23:46:10.621283 Set Vref, RX VrefLevel [Byte0]: 67
7919 23:46:10.624277 [Byte1]: 67
7920 23:46:10.628739
7921 23:46:10.628823 Set Vref, RX VrefLevel [Byte0]: 68
7922 23:46:10.631998 [Byte1]: 68
7923 23:46:10.636584
7924 23:46:10.636679 Set Vref, RX VrefLevel [Byte0]: 69
7925 23:46:10.639796 [Byte1]: 69
7926 23:46:10.644332
7927 23:46:10.644412 Set Vref, RX VrefLevel [Byte0]: 70
7928 23:46:10.647258 [Byte1]: 70
7929 23:46:10.651875
7930 23:46:10.651956 Set Vref, RX VrefLevel [Byte0]: 71
7931 23:46:10.655190 [Byte1]: 71
7932 23:46:10.659237
7933 23:46:10.659317 Set Vref, RX VrefLevel [Byte0]: 72
7934 23:46:10.663003 [Byte1]: 72
7935 23:46:10.667210
7936 23:46:10.667290 Set Vref, RX VrefLevel [Byte0]: 73
7937 23:46:10.670174 [Byte1]: 73
7938 23:46:10.674473
7939 23:46:10.674554 Final RX Vref Byte 0 = 55 to rank0
7940 23:46:10.677877 Final RX Vref Byte 1 = 55 to rank0
7941 23:46:10.680980 Final RX Vref Byte 0 = 55 to rank1
7942 23:46:10.684643 Final RX Vref Byte 1 = 55 to rank1==
7943 23:46:10.687819 Dram Type= 6, Freq= 0, CH_0, rank 0
7944 23:46:10.694708 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7945 23:46:10.694789 ==
7946 23:46:10.694854 DQS Delay:
7947 23:46:10.697612 DQS0 = 0, DQS1 = 0
7948 23:46:10.697692 DQM Delay:
7949 23:46:10.697756 DQM0 = 129, DQM1 = 124
7950 23:46:10.700891 DQ Delay:
7951 23:46:10.704250 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7952 23:46:10.707506 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7953 23:46:10.710785 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7954 23:46:10.714230 DQ12 =130, DQ13 =130, DQ14 =134, DQ15 =132
7955 23:46:10.714311
7956 23:46:10.714375
7957 23:46:10.714435
7958 23:46:10.717280 [DramC_TX_OE_Calibration] TA2
7959 23:46:10.720465 Original DQ_B0 (3 6) =30, OEN = 27
7960 23:46:10.724424 Original DQ_B1 (3 6) =30, OEN = 27
7961 23:46:10.727260 24, 0x0, End_B0=24 End_B1=24
7962 23:46:10.730615 25, 0x0, End_B0=25 End_B1=25
7963 23:46:10.730696 26, 0x0, End_B0=26 End_B1=26
7964 23:46:10.734058 27, 0x0, End_B0=27 End_B1=27
7965 23:46:10.736825 28, 0x0, End_B0=28 End_B1=28
7966 23:46:10.740285 29, 0x0, End_B0=29 End_B1=29
7967 23:46:10.740368 30, 0x0, End_B0=30 End_B1=30
7968 23:46:10.743555 31, 0x4141, End_B0=30 End_B1=30
7969 23:46:10.746954 Byte0 end_step=30 best_step=27
7970 23:46:10.750090 Byte1 end_step=30 best_step=27
7971 23:46:10.754295 Byte0 TX OE(2T, 0.5T) = (3, 3)
7972 23:46:10.756682 Byte1 TX OE(2T, 0.5T) = (3, 3)
7973 23:46:10.756763
7974 23:46:10.756826
7975 23:46:10.763306 [DQSOSCAuto] RK0, (LSB)MR18= 0x1613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
7976 23:46:10.766574 CH0 RK0: MR19=303, MR18=1613
7977 23:46:10.773214 CH0_RK0: MR19=0x303, MR18=0x1613, DQSOSC=398, MR23=63, INC=23, DEC=15
7978 23:46:10.773347
7979 23:46:10.776417 ----->DramcWriteLeveling(PI) begin...
7980 23:46:10.776499 ==
7981 23:46:10.780227 Dram Type= 6, Freq= 0, CH_0, rank 1
7982 23:46:10.783229 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 23:46:10.783310 ==
7984 23:46:10.786637 Write leveling (Byte 0): 36 => 36
7985 23:46:10.789886 Write leveling (Byte 1): 28 => 28
7986 23:46:10.792896 DramcWriteLeveling(PI) end<-----
7987 23:46:10.792976
7988 23:46:10.793040 ==
7989 23:46:10.796351 Dram Type= 6, Freq= 0, CH_0, rank 1
7990 23:46:10.802799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7991 23:46:10.802891 ==
7992 23:46:10.802959 [Gating] SW mode calibration
7993 23:46:10.813387 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7994 23:46:10.816285 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7995 23:46:10.819564 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 23:46:10.826460 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 23:46:10.829392 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7998 23:46:10.832789 1 4 12 | B1->B0 | 2323 3130 | 0 1 | (0 0) (1 1)
7999 23:46:10.839637 1 4 16 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
8000 23:46:10.842873 1 4 20 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
8001 23:46:10.845868 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8002 23:46:10.853199 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8003 23:46:10.855472 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8004 23:46:10.858983 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8005 23:46:10.865444 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8006 23:46:10.868847 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
8007 23:46:10.872117 1 5 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8008 23:46:10.879141 1 5 20 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
8009 23:46:10.882406 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 23:46:10.885668 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8011 23:46:10.892465 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8012 23:46:10.895356 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8013 23:46:10.898854 1 6 8 | B1->B0 | 2323 3e3e | 0 1 | (0 0) (0 0)
8014 23:46:10.904948 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8015 23:46:10.908191 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
8016 23:46:10.911684 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8017 23:46:10.918462 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 23:46:10.922089 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8019 23:46:10.927929 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8020 23:46:10.931468 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8021 23:46:10.934985 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8022 23:46:10.941586 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8023 23:46:10.944438 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8024 23:46:10.947722 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8025 23:46:10.954357 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 23:46:10.957951 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 23:46:10.960947 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 23:46:10.967470 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 23:46:10.970816 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 23:46:10.974397 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 23:46:10.980840 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8032 23:46:10.984348 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8033 23:46:10.987777 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8034 23:46:10.994209 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8035 23:46:10.997281 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8036 23:46:11.000418 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8037 23:46:11.007317 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8038 23:46:11.010549 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8039 23:46:11.014119 Total UI for P1: 0, mck2ui 16
8040 23:46:11.017975 best dqsien dly found for B0: ( 1, 9, 8)
8041 23:46:11.020355 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8042 23:46:11.024227 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8043 23:46:11.030472 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8044 23:46:11.033708 Total UI for P1: 0, mck2ui 16
8045 23:46:11.036998 best dqsien dly found for B1: ( 1, 9, 18)
8046 23:46:11.040525 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8047 23:46:11.044109 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8048 23:46:11.044199
8049 23:46:11.047260 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8050 23:46:11.050099 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8051 23:46:11.053754 [Gating] SW calibration Done
8052 23:46:11.053827 ==
8053 23:46:11.056991 Dram Type= 6, Freq= 0, CH_0, rank 1
8054 23:46:11.060326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8055 23:46:11.060398 ==
8056 23:46:11.063364 RX Vref Scan: 0
8057 23:46:11.063442
8058 23:46:11.066869 RX Vref 0 -> 0, step: 1
8059 23:46:11.066953
8060 23:46:11.067014 RX Delay 0 -> 252, step: 8
8061 23:46:11.073126 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8062 23:46:11.077017 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8063 23:46:11.080639 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8064 23:46:11.083020 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8065 23:46:11.086372 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8066 23:46:11.093035 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8067 23:46:11.096489 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8068 23:46:11.099743 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8069 23:46:11.102964 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8070 23:46:11.106257 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8071 23:46:11.113075 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8072 23:46:11.116349 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8073 23:46:11.119440 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8074 23:46:11.122856 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8075 23:46:11.129724 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
8076 23:46:11.133058 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8077 23:46:11.133138 ==
8078 23:46:11.136550 Dram Type= 6, Freq= 0, CH_0, rank 1
8079 23:46:11.139305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8080 23:46:11.139402 ==
8081 23:46:11.143157 DQS Delay:
8082 23:46:11.143254 DQS0 = 0, DQS1 = 0
8083 23:46:11.143341 DQM Delay:
8084 23:46:11.145910 DQM0 = 131, DQM1 = 127
8085 23:46:11.145979 DQ Delay:
8086 23:46:11.149048 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8087 23:46:11.152665 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8088 23:46:11.155876 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
8089 23:46:11.162298 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =135
8090 23:46:11.162372
8091 23:46:11.162433
8092 23:46:11.162502 ==
8093 23:46:11.165544 Dram Type= 6, Freq= 0, CH_0, rank 1
8094 23:46:11.169144 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8095 23:46:11.169255 ==
8096 23:46:11.169364
8097 23:46:11.169443
8098 23:46:11.172210 TX Vref Scan disable
8099 23:46:11.172312 == TX Byte 0 ==
8100 23:46:11.178905 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8101 23:46:11.182718 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8102 23:46:11.182808 == TX Byte 1 ==
8103 23:46:11.189546 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8104 23:46:11.192132 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8105 23:46:11.192230 ==
8106 23:46:11.195335 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 23:46:11.198566 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 23:46:11.201988 ==
8109 23:46:11.214095
8110 23:46:11.217085 TX Vref early break, caculate TX vref
8111 23:46:11.220716 TX Vref=16, minBit 1, minWin=23, winSum=382
8112 23:46:11.223590 TX Vref=18, minBit 2, minWin=23, winSum=390
8113 23:46:11.226971 TX Vref=20, minBit 2, minWin=24, winSum=399
8114 23:46:11.229839 TX Vref=22, minBit 2, minWin=24, winSum=406
8115 23:46:11.233442 TX Vref=24, minBit 2, minWin=25, winSum=413
8116 23:46:11.239683 TX Vref=26, minBit 4, minWin=25, winSum=423
8117 23:46:11.242900 TX Vref=28, minBit 4, minWin=25, winSum=423
8118 23:46:11.246571 TX Vref=30, minBit 1, minWin=25, winSum=416
8119 23:46:11.249888 TX Vref=32, minBit 13, minWin=24, winSum=407
8120 23:46:11.252800 TX Vref=34, minBit 0, minWin=24, winSum=400
8121 23:46:11.259538 [TxChooseVref] Worse bit 4, Min win 25, Win sum 423, Final Vref 26
8122 23:46:11.259637
8123 23:46:11.262717 Final TX Range 0 Vref 26
8124 23:46:11.262814
8125 23:46:11.262909 ==
8126 23:46:11.266597 Dram Type= 6, Freq= 0, CH_0, rank 1
8127 23:46:11.269386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8128 23:46:11.269458 ==
8129 23:46:11.269518
8130 23:46:11.272909
8131 23:46:11.273011 TX Vref Scan disable
8132 23:46:11.279588 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8133 23:46:11.279677 == TX Byte 0 ==
8134 23:46:11.282770 u2DelayCellOfst[0]=14 cells (4 PI)
8135 23:46:11.286281 u2DelayCellOfst[1]=17 cells (5 PI)
8136 23:46:11.289421 u2DelayCellOfst[2]=10 cells (3 PI)
8137 23:46:11.292921 u2DelayCellOfst[3]=10 cells (3 PI)
8138 23:46:11.295839 u2DelayCellOfst[4]=7 cells (2 PI)
8139 23:46:11.299678 u2DelayCellOfst[5]=0 cells (0 PI)
8140 23:46:11.302567 u2DelayCellOfst[6]=21 cells (6 PI)
8141 23:46:11.306013 u2DelayCellOfst[7]=17 cells (5 PI)
8142 23:46:11.309243 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8143 23:46:11.312306 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8144 23:46:11.315474 == TX Byte 1 ==
8145 23:46:11.319277 u2DelayCellOfst[8]=0 cells (0 PI)
8146 23:46:11.322338 u2DelayCellOfst[9]=0 cells (0 PI)
8147 23:46:11.325306 u2DelayCellOfst[10]=3 cells (1 PI)
8148 23:46:11.328758 u2DelayCellOfst[11]=3 cells (1 PI)
8149 23:46:11.331858 u2DelayCellOfst[12]=10 cells (3 PI)
8150 23:46:11.335444 u2DelayCellOfst[13]=10 cells (3 PI)
8151 23:46:11.335515 u2DelayCellOfst[14]=14 cells (4 PI)
8152 23:46:11.338629 u2DelayCellOfst[15]=10 cells (3 PI)
8153 23:46:11.345543 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8154 23:46:11.348562 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8155 23:46:11.352032 DramC Write-DBI on
8156 23:46:11.352113 ==
8157 23:46:11.355428 Dram Type= 6, Freq= 0, CH_0, rank 1
8158 23:46:11.358959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8159 23:46:11.359041 ==
8160 23:46:11.359105
8161 23:46:11.359163
8162 23:46:11.361894 TX Vref Scan disable
8163 23:46:11.361975 == TX Byte 0 ==
8164 23:46:11.368638 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8165 23:46:11.368720 == TX Byte 1 ==
8166 23:46:11.371612 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8167 23:46:11.375253 DramC Write-DBI off
8168 23:46:11.375334
8169 23:46:11.375409 [DATLAT]
8170 23:46:11.378514 Freq=1600, CH0 RK1
8171 23:46:11.378595
8172 23:46:11.378659 DATLAT Default: 0xf
8173 23:46:11.381640 0, 0xFFFF, sum = 0
8174 23:46:11.381723 1, 0xFFFF, sum = 0
8175 23:46:11.384769 2, 0xFFFF, sum = 0
8176 23:46:11.388229 3, 0xFFFF, sum = 0
8177 23:46:11.388311 4, 0xFFFF, sum = 0
8178 23:46:11.391567 5, 0xFFFF, sum = 0
8179 23:46:11.391649 6, 0xFFFF, sum = 0
8180 23:46:11.394807 7, 0xFFFF, sum = 0
8181 23:46:11.394889 8, 0xFFFF, sum = 0
8182 23:46:11.398086 9, 0xFFFF, sum = 0
8183 23:46:11.398168 10, 0xFFFF, sum = 0
8184 23:46:11.401554 11, 0xFFFF, sum = 0
8185 23:46:11.401636 12, 0xFFFF, sum = 0
8186 23:46:11.404824 13, 0xFFFF, sum = 0
8187 23:46:11.404905 14, 0x0, sum = 1
8188 23:46:11.407963 15, 0x0, sum = 2
8189 23:46:11.408044 16, 0x0, sum = 3
8190 23:46:11.411321 17, 0x0, sum = 4
8191 23:46:11.411402 best_step = 15
8192 23:46:11.411466
8193 23:46:11.411525 ==
8194 23:46:11.414979 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 23:46:11.418202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 23:46:11.421160 ==
8197 23:46:11.421291 RX Vref Scan: 0
8198 23:46:11.421372
8199 23:46:11.424728 RX Vref 0 -> 0, step: 1
8200 23:46:11.424799
8201 23:46:11.428111 RX Delay 11 -> 252, step: 4
8202 23:46:11.431420 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8203 23:46:11.434784 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8204 23:46:11.437704 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8205 23:46:11.444626 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8206 23:46:11.448384 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8207 23:46:11.451161 iDelay=191, Bit 5, Center 118 (63 ~ 174) 112
8208 23:46:11.455197 iDelay=191, Bit 6, Center 136 (87 ~ 186) 100
8209 23:46:11.457496 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8210 23:46:11.464210 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8211 23:46:11.467299 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8212 23:46:11.470866 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8213 23:46:11.473994 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8214 23:46:11.477149 iDelay=191, Bit 12, Center 126 (71 ~ 182) 112
8215 23:46:11.483882 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8216 23:46:11.487136 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8217 23:46:11.490186 iDelay=191, Bit 15, Center 130 (79 ~ 182) 104
8218 23:46:11.490267 ==
8219 23:46:11.494110 Dram Type= 6, Freq= 0, CH_0, rank 1
8220 23:46:11.497020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8221 23:46:11.500351 ==
8222 23:46:11.500431 DQS Delay:
8223 23:46:11.500494 DQS0 = 0, DQS1 = 0
8224 23:46:11.503874 DQM Delay:
8225 23:46:11.503955 DQM0 = 128, DQM1 = 123
8226 23:46:11.507110 DQ Delay:
8227 23:46:11.510463 DQ0 =126, DQ1 =132, DQ2 =122, DQ3 =126
8228 23:46:11.513284 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
8229 23:46:11.516976 DQ8 =112, DQ9 =110, DQ10 =126, DQ11 =118
8230 23:46:11.520241 DQ12 =126, DQ13 =128, DQ14 =136, DQ15 =130
8231 23:46:11.520322
8232 23:46:11.520386
8233 23:46:11.520444
8234 23:46:11.523807 [DramC_TX_OE_Calibration] TA2
8235 23:46:11.526561 Original DQ_B0 (3 6) =30, OEN = 27
8236 23:46:11.530001 Original DQ_B1 (3 6) =30, OEN = 27
8237 23:46:11.533535 24, 0x0, End_B0=24 End_B1=24
8238 23:46:11.533617 25, 0x0, End_B0=25 End_B1=25
8239 23:46:11.536326 26, 0x0, End_B0=26 End_B1=26
8240 23:46:11.539748 27, 0x0, End_B0=27 End_B1=27
8241 23:46:11.543485 28, 0x0, End_B0=28 End_B1=28
8242 23:46:11.546273 29, 0x0, End_B0=29 End_B1=29
8243 23:46:11.546355 30, 0x0, End_B0=30 End_B1=30
8244 23:46:11.549807 31, 0x4141, End_B0=30 End_B1=30
8245 23:46:11.553172 Byte0 end_step=30 best_step=27
8246 23:46:11.556394 Byte1 end_step=30 best_step=27
8247 23:46:11.560134 Byte0 TX OE(2T, 0.5T) = (3, 3)
8248 23:46:11.563145 Byte1 TX OE(2T, 0.5T) = (3, 3)
8249 23:46:11.563225
8250 23:46:11.563289
8251 23:46:11.569409 [DQSOSCAuto] RK1, (LSB)MR18= 0x1513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8252 23:46:11.572799 CH0 RK1: MR19=303, MR18=1513
8253 23:46:11.579184 CH0_RK1: MR19=0x303, MR18=0x1513, DQSOSC=399, MR23=63, INC=23, DEC=15
8254 23:46:11.582567 [RxdqsGatingPostProcess] freq 1600
8255 23:46:11.589096 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8256 23:46:11.589218 best DQS0 dly(2T, 0.5T) = (1, 1)
8257 23:46:11.592518 best DQS1 dly(2T, 0.5T) = (1, 1)
8258 23:46:11.595851 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8259 23:46:11.599014 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8260 23:46:11.602108 best DQS0 dly(2T, 0.5T) = (1, 1)
8261 23:46:11.605242 best DQS1 dly(2T, 0.5T) = (1, 1)
8262 23:46:11.608868 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8263 23:46:11.612886 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8264 23:46:11.615158 Pre-setting of DQS Precalculation
8265 23:46:11.619426 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8266 23:46:11.619508 ==
8267 23:46:11.621996 Dram Type= 6, Freq= 0, CH_1, rank 0
8268 23:46:11.628680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 23:46:11.628762 ==
8270 23:46:11.631860 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8271 23:46:11.639098 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8272 23:46:11.642075 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8273 23:46:11.649082 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8274 23:46:11.656217 [CA 0] Center 42 (12~72) winsize 61
8275 23:46:11.659494 [CA 1] Center 42 (12~72) winsize 61
8276 23:46:11.663015 [CA 2] Center 38 (9~67) winsize 59
8277 23:46:11.666329 [CA 3] Center 37 (8~66) winsize 59
8278 23:46:11.669725 [CA 4] Center 37 (7~67) winsize 61
8279 23:46:11.672504 [CA 5] Center 36 (7~66) winsize 60
8280 23:46:11.672595
8281 23:46:11.675887 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8282 23:46:11.675967
8283 23:46:11.682682 [CATrainingPosCal] consider 1 rank data
8284 23:46:11.682764 u2DelayCellTimex100 = 275/100 ps
8285 23:46:11.689639 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8286 23:46:11.693286 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8287 23:46:11.696096 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8288 23:46:11.699443 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8289 23:46:11.702197 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8290 23:46:11.705491 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8291 23:46:11.705572
8292 23:46:11.709517 CA PerBit enable=1, Macro0, CA PI delay=36
8293 23:46:11.709624
8294 23:46:11.712263 [CBTSetCACLKResult] CA Dly = 36
8295 23:46:11.715652 CS Dly: 8 (0~39)
8296 23:46:11.719522 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8297 23:46:11.722506 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8298 23:46:11.722588 ==
8299 23:46:11.725639 Dram Type= 6, Freq= 0, CH_1, rank 1
8300 23:46:11.731947 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 23:46:11.732028 ==
8302 23:46:11.735261 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8303 23:46:11.741643 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8304 23:46:11.744844 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8305 23:46:11.751568 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8306 23:46:11.759642 [CA 0] Center 41 (11~72) winsize 62
8307 23:46:11.762748 [CA 1] Center 43 (14~72) winsize 59
8308 23:46:11.765951 [CA 2] Center 38 (9~68) winsize 60
8309 23:46:11.768998 [CA 3] Center 37 (8~66) winsize 59
8310 23:46:11.772504 [CA 4] Center 38 (8~68) winsize 61
8311 23:46:11.775657 [CA 5] Center 37 (7~67) winsize 61
8312 23:46:11.775738
8313 23:46:11.778984 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8314 23:46:11.779065
8315 23:46:11.785736 [CATrainingPosCal] consider 2 rank data
8316 23:46:11.785816 u2DelayCellTimex100 = 275/100 ps
8317 23:46:11.792947 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8318 23:46:11.795442 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8319 23:46:11.798807 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8320 23:46:11.802358 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8321 23:46:11.805205 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8322 23:46:11.808985 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8323 23:46:11.809066
8324 23:46:11.812298 CA PerBit enable=1, Macro0, CA PI delay=36
8325 23:46:11.812379
8326 23:46:11.815183 [CBTSetCACLKResult] CA Dly = 36
8327 23:46:11.818399 CS Dly: 9 (0~42)
8328 23:46:11.821661 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8329 23:46:11.825286 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8330 23:46:11.825380
8331 23:46:11.828215 ----->DramcWriteLeveling(PI) begin...
8332 23:46:11.831662 ==
8333 23:46:11.831744 Dram Type= 6, Freq= 0, CH_1, rank 0
8334 23:46:11.838233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 23:46:11.838315 ==
8336 23:46:11.841300 Write leveling (Byte 0): 26 => 26
8337 23:46:11.844592 Write leveling (Byte 1): 26 => 26
8338 23:46:11.848546 DramcWriteLeveling(PI) end<-----
8339 23:46:11.848626
8340 23:46:11.848690 ==
8341 23:46:11.851727 Dram Type= 6, Freq= 0, CH_1, rank 0
8342 23:46:11.854356 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8343 23:46:11.854438 ==
8344 23:46:11.858465 [Gating] SW mode calibration
8345 23:46:11.864169 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8346 23:46:11.871077 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8347 23:46:11.874179 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 23:46:11.878100 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 23:46:11.884455 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 23:46:11.887270 1 4 12 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (0 0)
8351 23:46:11.890748 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 23:46:11.897291 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 23:46:11.900502 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8354 23:46:11.903822 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8355 23:46:11.911195 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8356 23:46:11.913916 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8357 23:46:11.917484 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8358 23:46:11.923888 1 5 12 | B1->B0 | 3232 2323 | 0 0 | (0 1) (1 0)
8359 23:46:11.926875 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8360 23:46:11.930190 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 23:46:11.936976 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 23:46:11.940740 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 23:46:11.943728 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 23:46:11.950010 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 23:46:11.953854 1 6 8 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8366 23:46:11.956860 1 6 12 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
8367 23:46:11.963732 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 23:46:11.966639 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 23:46:11.970371 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 23:46:11.976338 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8371 23:46:11.979587 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8372 23:46:11.983393 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8373 23:46:11.989518 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8374 23:46:11.993131 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8375 23:46:11.996145 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8376 23:46:12.002514 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 23:46:12.005973 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 23:46:12.009197 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 23:46:12.015954 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 23:46:12.018937 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 23:46:12.022794 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 23:46:12.028872 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 23:46:12.032413 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 23:46:12.035467 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 23:46:12.042054 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8386 23:46:12.045504 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8387 23:46:12.048870 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8388 23:46:12.055093 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8389 23:46:12.058553 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8390 23:46:12.061858 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8391 23:46:12.068474 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8392 23:46:12.068555 Total UI for P1: 0, mck2ui 16
8393 23:46:12.075495 best dqsien dly found for B0: ( 1, 9, 10)
8394 23:46:12.078766 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8395 23:46:12.081835 Total UI for P1: 0, mck2ui 16
8396 23:46:12.084828 best dqsien dly found for B1: ( 1, 9, 14)
8397 23:46:12.088357 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8398 23:46:12.091731 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8399 23:46:12.091812
8400 23:46:12.094736 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8401 23:46:12.098091 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8402 23:46:12.101722 [Gating] SW calibration Done
8403 23:46:12.101803 ==
8404 23:46:12.104781 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 23:46:12.111941 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 23:46:12.112024 ==
8407 23:46:12.112088 RX Vref Scan: 0
8408 23:46:12.112148
8409 23:46:12.114567 RX Vref 0 -> 0, step: 1
8410 23:46:12.114647
8411 23:46:12.117795 RX Delay 0 -> 252, step: 8
8412 23:46:12.121138 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8413 23:46:12.124452 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8414 23:46:12.127848 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8415 23:46:12.131212 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8416 23:46:12.137732 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8417 23:46:12.140839 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8418 23:46:12.144584 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8419 23:46:12.147390 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8420 23:46:12.153775 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8421 23:46:12.157118 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8422 23:46:12.160443 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8423 23:46:12.163863 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8424 23:46:12.167164 iDelay=200, Bit 12, Center 143 (96 ~ 191) 96
8425 23:46:12.173425 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8426 23:46:12.176849 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8427 23:46:12.180240 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8428 23:46:12.180334 ==
8429 23:46:12.183445 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 23:46:12.187059 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 23:46:12.190105 ==
8432 23:46:12.190185 DQS Delay:
8433 23:46:12.190250 DQS0 = 0, DQS1 = 0
8434 23:46:12.193502 DQM Delay:
8435 23:46:12.193584 DQM0 = 135, DQM1 = 132
8436 23:46:12.196828 DQ Delay:
8437 23:46:12.200223 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8438 23:46:12.203162 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =127
8439 23:46:12.207020 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8440 23:46:12.210142 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =139
8441 23:46:12.210223
8442 23:46:12.210286
8443 23:46:12.210345 ==
8444 23:46:12.213296 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 23:46:12.216332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 23:46:12.216414 ==
8447 23:46:12.219914
8448 23:46:12.220020
8449 23:46:12.220112 TX Vref Scan disable
8450 23:46:12.223479 == TX Byte 0 ==
8451 23:46:12.226107 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8452 23:46:12.230234 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8453 23:46:12.233107 == TX Byte 1 ==
8454 23:46:12.236438 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8455 23:46:12.239443 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8456 23:46:12.239524 ==
8457 23:46:12.242871 Dram Type= 6, Freq= 0, CH_1, rank 0
8458 23:46:12.249451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8459 23:46:12.249532 ==
8460 23:46:12.262193
8461 23:46:12.265674 TX Vref early break, caculate TX vref
8462 23:46:12.268735 TX Vref=16, minBit 8, minWin=21, winSum=370
8463 23:46:12.271940 TX Vref=18, minBit 9, minWin=21, winSum=375
8464 23:46:12.275126 TX Vref=20, minBit 3, minWin=23, winSum=382
8465 23:46:12.278390 TX Vref=22, minBit 8, minWin=23, winSum=391
8466 23:46:12.281675 TX Vref=24, minBit 9, minWin=24, winSum=406
8467 23:46:12.288789 TX Vref=26, minBit 8, minWin=24, winSum=413
8468 23:46:12.291877 TX Vref=28, minBit 3, minWin=25, winSum=415
8469 23:46:12.295318 TX Vref=30, minBit 0, minWin=25, winSum=416
8470 23:46:12.298442 TX Vref=32, minBit 0, minWin=24, winSum=405
8471 23:46:12.301811 TX Vref=34, minBit 0, minWin=24, winSum=400
8472 23:46:12.305100 TX Vref=36, minBit 0, minWin=23, winSum=385
8473 23:46:12.311868 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 30
8474 23:46:12.311947
8475 23:46:12.315425 Final TX Range 0 Vref 30
8476 23:46:12.315506
8477 23:46:12.315570 ==
8478 23:46:12.318185 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 23:46:12.322049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 23:46:12.324419 ==
8481 23:46:12.324499
8482 23:46:12.324562
8483 23:46:12.324621 TX Vref Scan disable
8484 23:46:12.331985 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8485 23:46:12.332092 == TX Byte 0 ==
8486 23:46:12.334585 u2DelayCellOfst[0]=14 cells (4 PI)
8487 23:46:12.338116 u2DelayCellOfst[1]=10 cells (3 PI)
8488 23:46:12.340950 u2DelayCellOfst[2]=0 cells (0 PI)
8489 23:46:12.344507 u2DelayCellOfst[3]=7 cells (2 PI)
8490 23:46:12.347700 u2DelayCellOfst[4]=7 cells (2 PI)
8491 23:46:12.350927 u2DelayCellOfst[5]=17 cells (5 PI)
8492 23:46:12.354109 u2DelayCellOfst[6]=17 cells (5 PI)
8493 23:46:12.357474 u2DelayCellOfst[7]=7 cells (2 PI)
8494 23:46:12.360984 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8495 23:46:12.364388 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8496 23:46:12.367785 == TX Byte 1 ==
8497 23:46:12.370826 u2DelayCellOfst[8]=0 cells (0 PI)
8498 23:46:12.374212 u2DelayCellOfst[9]=3 cells (1 PI)
8499 23:46:12.377556 u2DelayCellOfst[10]=10 cells (3 PI)
8500 23:46:12.380783 u2DelayCellOfst[11]=7 cells (2 PI)
8501 23:46:12.383708 u2DelayCellOfst[12]=14 cells (4 PI)
8502 23:46:12.387360 u2DelayCellOfst[13]=17 cells (5 PI)
8503 23:46:12.390464 u2DelayCellOfst[14]=17 cells (5 PI)
8504 23:46:12.393624 u2DelayCellOfst[15]=17 cells (5 PI)
8505 23:46:12.396977 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8506 23:46:12.400477 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8507 23:46:12.403660 DramC Write-DBI on
8508 23:46:12.403733 ==
8509 23:46:12.406922 Dram Type= 6, Freq= 0, CH_1, rank 0
8510 23:46:12.410442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8511 23:46:12.410523 ==
8512 23:46:12.410586
8513 23:46:12.410645
8514 23:46:12.413869 TX Vref Scan disable
8515 23:46:12.413949 == TX Byte 0 ==
8516 23:46:12.420178 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8517 23:46:12.420259 == TX Byte 1 ==
8518 23:46:12.426393 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8519 23:46:12.426474 DramC Write-DBI off
8520 23:46:12.426537
8521 23:46:12.426596 [DATLAT]
8522 23:46:12.429989 Freq=1600, CH1 RK0
8523 23:46:12.430070
8524 23:46:12.433679 DATLAT Default: 0xf
8525 23:46:12.433759 0, 0xFFFF, sum = 0
8526 23:46:12.436987 1, 0xFFFF, sum = 0
8527 23:46:12.437069 2, 0xFFFF, sum = 0
8528 23:46:12.440364 3, 0xFFFF, sum = 0
8529 23:46:12.440446 4, 0xFFFF, sum = 0
8530 23:46:12.443009 5, 0xFFFF, sum = 0
8531 23:46:12.443091 6, 0xFFFF, sum = 0
8532 23:46:12.446548 7, 0xFFFF, sum = 0
8533 23:46:12.446630 8, 0xFFFF, sum = 0
8534 23:46:12.449880 9, 0xFFFF, sum = 0
8535 23:46:12.449963 10, 0xFFFF, sum = 0
8536 23:46:12.453190 11, 0xFFFF, sum = 0
8537 23:46:12.453312 12, 0xFFFF, sum = 0
8538 23:46:12.456556 13, 0xFFFF, sum = 0
8539 23:46:12.456638 14, 0x0, sum = 1
8540 23:46:12.459371 15, 0x0, sum = 2
8541 23:46:12.459452 16, 0x0, sum = 3
8542 23:46:12.463077 17, 0x0, sum = 4
8543 23:46:12.463158 best_step = 15
8544 23:46:12.463222
8545 23:46:12.463282 ==
8546 23:46:12.466240 Dram Type= 6, Freq= 0, CH_1, rank 0
8547 23:46:12.472801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8548 23:46:12.472883 ==
8549 23:46:12.472946 RX Vref Scan: 1
8550 23:46:12.473005
8551 23:46:12.476239 Set Vref Range= 24 -> 127
8552 23:46:12.476320
8553 23:46:12.479205 RX Vref 24 -> 127, step: 1
8554 23:46:12.479285
8555 23:46:12.482921 RX Delay 19 -> 252, step: 4
8556 23:46:12.483007
8557 23:46:12.485664 Set Vref, RX VrefLevel [Byte0]: 24
8558 23:46:12.489729 [Byte1]: 24
8559 23:46:12.489816
8560 23:46:12.492519 Set Vref, RX VrefLevel [Byte0]: 25
8561 23:46:12.495953 [Byte1]: 25
8562 23:46:12.496073
8563 23:46:12.498873 Set Vref, RX VrefLevel [Byte0]: 26
8564 23:46:12.502164 [Byte1]: 26
8565 23:46:12.505637
8566 23:46:12.505738 Set Vref, RX VrefLevel [Byte0]: 27
8567 23:46:12.508827 [Byte1]: 27
8568 23:46:12.513267
8569 23:46:12.513418 Set Vref, RX VrefLevel [Byte0]: 28
8570 23:46:12.516232 [Byte1]: 28
8571 23:46:12.521254
8572 23:46:12.521402 Set Vref, RX VrefLevel [Byte0]: 29
8573 23:46:12.524249 [Byte1]: 29
8574 23:46:12.528552
8575 23:46:12.528811 Set Vref, RX VrefLevel [Byte0]: 30
8576 23:46:12.531995 [Byte1]: 30
8577 23:46:12.536219
8578 23:46:12.536525 Set Vref, RX VrefLevel [Byte0]: 31
8579 23:46:12.539306 [Byte1]: 31
8580 23:46:12.543794
8581 23:46:12.544196 Set Vref, RX VrefLevel [Byte0]: 32
8582 23:46:12.547009 [Byte1]: 32
8583 23:46:12.551144
8584 23:46:12.551563 Set Vref, RX VrefLevel [Byte0]: 33
8585 23:46:12.554522 [Byte1]: 33
8586 23:46:12.558963
8587 23:46:12.559383 Set Vref, RX VrefLevel [Byte0]: 34
8588 23:46:12.562324 [Byte1]: 34
8589 23:46:12.566599
8590 23:46:12.567106 Set Vref, RX VrefLevel [Byte0]: 35
8591 23:46:12.570124 [Byte1]: 35
8592 23:46:12.574024
8593 23:46:12.574548 Set Vref, RX VrefLevel [Byte0]: 36
8594 23:46:12.577187 [Byte1]: 36
8595 23:46:12.581803
8596 23:46:12.582299 Set Vref, RX VrefLevel [Byte0]: 37
8597 23:46:12.584608 [Byte1]: 37
8598 23:46:12.589422
8599 23:46:12.589833 Set Vref, RX VrefLevel [Byte0]: 38
8600 23:46:12.592317 [Byte1]: 38
8601 23:46:12.597186
8602 23:46:12.597636 Set Vref, RX VrefLevel [Byte0]: 39
8603 23:46:12.600255 [Byte1]: 39
8604 23:46:12.604234
8605 23:46:12.604847 Set Vref, RX VrefLevel [Byte0]: 40
8606 23:46:12.607621 [Byte1]: 40
8607 23:46:12.611778
8608 23:46:12.612270 Set Vref, RX VrefLevel [Byte0]: 41
8609 23:46:12.614998 [Byte1]: 41
8610 23:46:12.619246
8611 23:46:12.619846 Set Vref, RX VrefLevel [Byte0]: 42
8612 23:46:12.622887 [Byte1]: 42
8613 23:46:12.626764
8614 23:46:12.627205 Set Vref, RX VrefLevel [Byte0]: 43
8615 23:46:12.630542 [Byte1]: 43
8616 23:46:12.634568
8617 23:46:12.634990 Set Vref, RX VrefLevel [Byte0]: 44
8618 23:46:12.638208 [Byte1]: 44
8619 23:46:12.641833
8620 23:46:12.642379 Set Vref, RX VrefLevel [Byte0]: 45
8621 23:46:12.645765 [Byte1]: 45
8622 23:46:12.649800
8623 23:46:12.650219 Set Vref, RX VrefLevel [Byte0]: 46
8624 23:46:12.653160 [Byte1]: 46
8625 23:46:12.657151
8626 23:46:12.657631 Set Vref, RX VrefLevel [Byte0]: 47
8627 23:46:12.660522 [Byte1]: 47
8628 23:46:12.664826
8629 23:46:12.665413 Set Vref, RX VrefLevel [Byte0]: 48
8630 23:46:12.668235 [Byte1]: 48
8631 23:46:12.672404
8632 23:46:12.672956 Set Vref, RX VrefLevel [Byte0]: 49
8633 23:46:12.675890 [Byte1]: 49
8634 23:46:12.680015
8635 23:46:12.680612 Set Vref, RX VrefLevel [Byte0]: 50
8636 23:46:12.683106 [Byte1]: 50
8637 23:46:12.687807
8638 23:46:12.688234 Set Vref, RX VrefLevel [Byte0]: 51
8639 23:46:12.691450 [Byte1]: 51
8640 23:46:12.695090
8641 23:46:12.695539 Set Vref, RX VrefLevel [Byte0]: 52
8642 23:46:12.698321 [Byte1]: 52
8643 23:46:12.702492
8644 23:46:12.703047 Set Vref, RX VrefLevel [Byte0]: 53
8645 23:46:12.706185 [Byte1]: 53
8646 23:46:12.710348
8647 23:46:12.710980 Set Vref, RX VrefLevel [Byte0]: 54
8648 23:46:12.713355 [Byte1]: 54
8649 23:46:12.717605
8650 23:46:12.718093 Set Vref, RX VrefLevel [Byte0]: 55
8651 23:46:12.720921 [Byte1]: 55
8652 23:46:12.725282
8653 23:46:12.725832 Set Vref, RX VrefLevel [Byte0]: 56
8654 23:46:12.728592 [Byte1]: 56
8655 23:46:12.733299
8656 23:46:12.733853 Set Vref, RX VrefLevel [Byte0]: 57
8657 23:46:12.736150 [Byte1]: 57
8658 23:46:12.740333
8659 23:46:12.740797 Set Vref, RX VrefLevel [Byte0]: 58
8660 23:46:12.743918 [Byte1]: 58
8661 23:46:12.748381
8662 23:46:12.748909 Set Vref, RX VrefLevel [Byte0]: 59
8663 23:46:12.751938 [Byte1]: 59
8664 23:46:12.755455
8665 23:46:12.755914 Set Vref, RX VrefLevel [Byte0]: 60
8666 23:46:12.759687 [Byte1]: 60
8667 23:46:12.763515
8668 23:46:12.763986 Set Vref, RX VrefLevel [Byte0]: 61
8669 23:46:12.766733 [Byte1]: 61
8670 23:46:12.770720
8671 23:46:12.771135 Set Vref, RX VrefLevel [Byte0]: 62
8672 23:46:12.774179 [Byte1]: 62
8673 23:46:12.778395
8674 23:46:12.778812 Set Vref, RX VrefLevel [Byte0]: 63
8675 23:46:12.782210 [Byte1]: 63
8676 23:46:12.786169
8677 23:46:12.786585 Set Vref, RX VrefLevel [Byte0]: 64
8678 23:46:12.789553 [Byte1]: 64
8679 23:46:12.793517
8680 23:46:12.793931 Set Vref, RX VrefLevel [Byte0]: 65
8681 23:46:12.796933 [Byte1]: 65
8682 23:46:12.801359
8683 23:46:12.801776 Set Vref, RX VrefLevel [Byte0]: 66
8684 23:46:12.804874 [Byte1]: 66
8685 23:46:12.809144
8686 23:46:12.809625 Set Vref, RX VrefLevel [Byte0]: 67
8687 23:46:12.811841 [Byte1]: 67
8688 23:46:12.816552
8689 23:46:12.817001 Set Vref, RX VrefLevel [Byte0]: 68
8690 23:46:12.819534 [Byte1]: 68
8691 23:46:12.824212
8692 23:46:12.824627 Set Vref, RX VrefLevel [Byte0]: 69
8693 23:46:12.827044 [Byte1]: 69
8694 23:46:12.831677
8695 23:46:12.832095 Set Vref, RX VrefLevel [Byte0]: 70
8696 23:46:12.834787 [Byte1]: 70
8697 23:46:12.839152
8698 23:46:12.839572 Set Vref, RX VrefLevel [Byte0]: 71
8699 23:46:12.842351 [Byte1]: 71
8700 23:46:12.846929
8701 23:46:12.847354 Final RX Vref Byte 0 = 58 to rank0
8702 23:46:12.849838 Final RX Vref Byte 1 = 59 to rank0
8703 23:46:12.852807 Final RX Vref Byte 0 = 58 to rank1
8704 23:46:12.856408 Final RX Vref Byte 1 = 59 to rank1==
8705 23:46:12.859645 Dram Type= 6, Freq= 0, CH_1, rank 0
8706 23:46:12.865922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8707 23:46:12.866006 ==
8708 23:46:12.866072 DQS Delay:
8709 23:46:12.869278 DQS0 = 0, DQS1 = 0
8710 23:46:12.869362 DQM Delay:
8711 23:46:12.869427 DQM0 = 133, DQM1 = 129
8712 23:46:12.872298 DQ Delay:
8713 23:46:12.875916 DQ0 =142, DQ1 =130, DQ2 =118, DQ3 =130
8714 23:46:12.879194 DQ4 =130, DQ5 =142, DQ6 =146, DQ7 =128
8715 23:46:12.882576 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
8716 23:46:12.885909 DQ12 =142, DQ13 =138, DQ14 =136, DQ15 =138
8717 23:46:12.885991
8718 23:46:12.886058
8719 23:46:12.886118
8720 23:46:12.888942 [DramC_TX_OE_Calibration] TA2
8721 23:46:12.892094 Original DQ_B0 (3 6) =30, OEN = 27
8722 23:46:12.896044 Original DQ_B1 (3 6) =30, OEN = 27
8723 23:46:12.899239 24, 0x0, End_B0=24 End_B1=24
8724 23:46:12.902511 25, 0x0, End_B0=25 End_B1=25
8725 23:46:12.902593 26, 0x0, End_B0=26 End_B1=26
8726 23:46:12.905759 27, 0x0, End_B0=27 End_B1=27
8727 23:46:12.908518 28, 0x0, End_B0=28 End_B1=28
8728 23:46:12.912053 29, 0x0, End_B0=29 End_B1=29
8729 23:46:12.912159 30, 0x0, End_B0=30 End_B1=30
8730 23:46:12.915420 31, 0x4141, End_B0=30 End_B1=30
8731 23:46:12.919035 Byte0 end_step=30 best_step=27
8732 23:46:12.921950 Byte1 end_step=30 best_step=27
8733 23:46:12.925651 Byte0 TX OE(2T, 0.5T) = (3, 3)
8734 23:46:12.928599 Byte1 TX OE(2T, 0.5T) = (3, 3)
8735 23:46:12.928679
8736 23:46:12.928743
8737 23:46:12.935175 [DQSOSCAuto] RK0, (LSB)MR18= 0xc16, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8738 23:46:12.938692 CH1 RK0: MR19=303, MR18=C16
8739 23:46:12.945143 CH1_RK0: MR19=0x303, MR18=0xC16, DQSOSC=398, MR23=63, INC=23, DEC=15
8740 23:46:12.945225
8741 23:46:12.948447 ----->DramcWriteLeveling(PI) begin...
8742 23:46:12.948530 ==
8743 23:46:12.951712 Dram Type= 6, Freq= 0, CH_1, rank 1
8744 23:46:12.955372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8745 23:46:12.955454 ==
8746 23:46:12.958221 Write leveling (Byte 0): 25 => 25
8747 23:46:12.961496 Write leveling (Byte 1): 27 => 27
8748 23:46:12.965621 DramcWriteLeveling(PI) end<-----
8749 23:46:12.965702
8750 23:46:12.965766 ==
8751 23:46:12.968145 Dram Type= 6, Freq= 0, CH_1, rank 1
8752 23:46:12.971546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8753 23:46:12.971628 ==
8754 23:46:12.975052 [Gating] SW mode calibration
8755 23:46:12.984981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8756 23:46:12.987984 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8757 23:46:12.991418 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 23:46:12.998164 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8759 23:46:13.000978 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8760 23:46:13.004493 1 4 12 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
8761 23:46:13.010904 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 23:46:13.014248 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8763 23:46:13.017717 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8764 23:46:13.024465 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8765 23:46:13.027518 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8766 23:46:13.030292 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8767 23:46:13.037063 1 5 8 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8768 23:46:13.040320 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8769 23:46:13.043678 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8770 23:46:13.050192 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8771 23:46:13.053541 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8772 23:46:13.056994 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8773 23:46:13.064103 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8774 23:46:13.066815 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8775 23:46:13.070240 1 6 8 | B1->B0 | 2323 4444 | 0 0 | (0 0) (1 1)
8776 23:46:13.076404 1 6 12 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
8777 23:46:13.080402 1 6 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8778 23:46:13.083782 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8779 23:46:13.090082 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8780 23:46:13.093180 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8781 23:46:13.096196 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8782 23:46:13.103038 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8783 23:46:13.106359 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8784 23:46:13.109601 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8785 23:46:13.116177 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8786 23:46:13.119472 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 23:46:13.125802 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 23:46:13.129176 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 23:46:13.132292 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 23:46:13.139102 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 23:46:13.142194 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 23:46:13.145483 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 23:46:13.152522 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 23:46:13.155652 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8795 23:46:13.159117 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8796 23:46:13.165225 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8797 23:46:13.168812 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8798 23:46:13.172008 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8799 23:46:13.178549 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8800 23:46:13.182602 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8801 23:46:13.185079 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8802 23:46:13.188516 Total UI for P1: 0, mck2ui 16
8803 23:46:13.191836 best dqsien dly found for B0: ( 1, 9, 8)
8804 23:46:13.195158 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8805 23:46:13.198262 Total UI for P1: 0, mck2ui 16
8806 23:46:13.201915 best dqsien dly found for B1: ( 1, 9, 12)
8807 23:46:13.208421 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8808 23:46:13.211782 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8809 23:46:13.211879
8810 23:46:13.215100 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8811 23:46:13.218315 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8812 23:46:13.221607 [Gating] SW calibration Done
8813 23:46:13.221688 ==
8814 23:46:13.224955 Dram Type= 6, Freq= 0, CH_1, rank 1
8815 23:46:13.228127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 23:46:13.228209 ==
8817 23:46:13.231283 RX Vref Scan: 0
8818 23:46:13.231364
8819 23:46:13.231428 RX Vref 0 -> 0, step: 1
8820 23:46:13.231487
8821 23:46:13.234696 RX Delay 0 -> 252, step: 8
8822 23:46:13.237801 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8823 23:46:13.244380 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8824 23:46:13.247654 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8825 23:46:13.251877 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8826 23:46:13.254241 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8827 23:46:13.257690 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8828 23:46:13.264624 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8829 23:46:13.267485 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8830 23:46:13.271391 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8831 23:46:13.273908 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8832 23:46:13.277414 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8833 23:46:13.284110 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8834 23:46:13.287008 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8835 23:46:13.290470 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8836 23:46:13.293695 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8837 23:46:13.300290 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8838 23:46:13.300372 ==
8839 23:46:13.303384 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 23:46:13.307381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 23:46:13.307462 ==
8842 23:46:13.307527 DQS Delay:
8843 23:46:13.310545 DQS0 = 0, DQS1 = 0
8844 23:46:13.310626 DQM Delay:
8845 23:46:13.313392 DQM0 = 135, DQM1 = 130
8846 23:46:13.313473 DQ Delay:
8847 23:46:13.316718 DQ0 =143, DQ1 =135, DQ2 =119, DQ3 =127
8848 23:46:13.320202 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135
8849 23:46:13.323641 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8850 23:46:13.326827 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8851 23:46:13.326908
8852 23:46:13.329809
8853 23:46:13.329889 ==
8854 23:46:13.333438 Dram Type= 6, Freq= 0, CH_1, rank 1
8855 23:46:13.336730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8856 23:46:13.336812 ==
8857 23:46:13.336877
8858 23:46:13.336952
8859 23:46:13.339795 TX Vref Scan disable
8860 23:46:13.339875 == TX Byte 0 ==
8861 23:46:13.346506 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8862 23:46:13.349670 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8863 23:46:13.349751 == TX Byte 1 ==
8864 23:46:13.356574 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8865 23:46:13.359561 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8866 23:46:13.359661 ==
8867 23:46:13.363099 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 23:46:13.365951 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 23:46:13.366032 ==
8870 23:46:13.380813
8871 23:46:13.384167 TX Vref early break, caculate TX vref
8872 23:46:13.387455 TX Vref=16, minBit 9, minWin=21, winSum=378
8873 23:46:13.390760 TX Vref=18, minBit 9, minWin=22, winSum=383
8874 23:46:13.394070 TX Vref=20, minBit 9, minWin=23, winSum=395
8875 23:46:13.397713 TX Vref=22, minBit 9, minWin=23, winSum=404
8876 23:46:13.400707 TX Vref=24, minBit 9, minWin=23, winSum=406
8877 23:46:13.407207 TX Vref=26, minBit 9, minWin=24, winSum=415
8878 23:46:13.410658 TX Vref=28, minBit 9, minWin=25, winSum=418
8879 23:46:13.413518 TX Vref=30, minBit 0, minWin=25, winSum=416
8880 23:46:13.416814 TX Vref=32, minBit 0, minWin=24, winSum=407
8881 23:46:13.420802 TX Vref=34, minBit 9, minWin=23, winSum=403
8882 23:46:13.423817 TX Vref=36, minBit 8, minWin=23, winSum=394
8883 23:46:13.431032 [TxChooseVref] Worse bit 9, Min win 25, Win sum 418, Final Vref 28
8884 23:46:13.431118
8885 23:46:13.433909 Final TX Range 0 Vref 28
8886 23:46:13.433989
8887 23:46:13.434052 ==
8888 23:46:13.437133 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 23:46:13.440548 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 23:46:13.440629 ==
8891 23:46:13.443798
8892 23:46:13.443877
8893 23:46:13.443940 TX Vref Scan disable
8894 23:46:13.450635 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8895 23:46:13.450715 == TX Byte 0 ==
8896 23:46:13.453555 u2DelayCellOfst[0]=14 cells (4 PI)
8897 23:46:13.457056 u2DelayCellOfst[1]=10 cells (3 PI)
8898 23:46:13.459950 u2DelayCellOfst[2]=0 cells (0 PI)
8899 23:46:13.464017 u2DelayCellOfst[3]=3 cells (1 PI)
8900 23:46:13.466486 u2DelayCellOfst[4]=7 cells (2 PI)
8901 23:46:13.470031 u2DelayCellOfst[5]=14 cells (4 PI)
8902 23:46:13.472958 u2DelayCellOfst[6]=14 cells (4 PI)
8903 23:46:13.476377 u2DelayCellOfst[7]=3 cells (1 PI)
8904 23:46:13.479378 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8905 23:46:13.482921 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8906 23:46:13.486100 == TX Byte 1 ==
8907 23:46:13.489211 u2DelayCellOfst[8]=0 cells (0 PI)
8908 23:46:13.492531 u2DelayCellOfst[9]=3 cells (1 PI)
8909 23:46:13.496013 u2DelayCellOfst[10]=14 cells (4 PI)
8910 23:46:13.499277 u2DelayCellOfst[11]=3 cells (1 PI)
8911 23:46:13.502832 u2DelayCellOfst[12]=14 cells (4 PI)
8912 23:46:13.505791 u2DelayCellOfst[13]=14 cells (4 PI)
8913 23:46:13.509436 u2DelayCellOfst[14]=14 cells (4 PI)
8914 23:46:13.509517 u2DelayCellOfst[15]=17 cells (5 PI)
8915 23:46:13.515918 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8916 23:46:13.519126 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8917 23:46:13.522996 DramC Write-DBI on
8918 23:46:13.523078 ==
8919 23:46:13.525885 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 23:46:13.528914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 23:46:13.528995 ==
8922 23:46:13.529059
8923 23:46:13.529117
8924 23:46:13.532328 TX Vref Scan disable
8925 23:46:13.532409 == TX Byte 0 ==
8926 23:46:13.539089 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8927 23:46:13.539170 == TX Byte 1 ==
8928 23:46:13.542119 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8929 23:46:13.545874 DramC Write-DBI off
8930 23:46:13.545955
8931 23:46:13.546018 [DATLAT]
8932 23:46:13.549532 Freq=1600, CH1 RK1
8933 23:46:13.549613
8934 23:46:13.549677 DATLAT Default: 0xf
8935 23:46:13.552326 0, 0xFFFF, sum = 0
8936 23:46:13.552407 1, 0xFFFF, sum = 0
8937 23:46:13.555221 2, 0xFFFF, sum = 0
8938 23:46:13.559121 3, 0xFFFF, sum = 0
8939 23:46:13.559204 4, 0xFFFF, sum = 0
8940 23:46:13.561886 5, 0xFFFF, sum = 0
8941 23:46:13.561968 6, 0xFFFF, sum = 0
8942 23:46:13.565505 7, 0xFFFF, sum = 0
8943 23:46:13.565587 8, 0xFFFF, sum = 0
8944 23:46:13.568700 9, 0xFFFF, sum = 0
8945 23:46:13.568782 10, 0xFFFF, sum = 0
8946 23:46:13.571996 11, 0xFFFF, sum = 0
8947 23:46:13.572077 12, 0xFFFF, sum = 0
8948 23:46:13.575125 13, 0xFFFF, sum = 0
8949 23:46:13.575207 14, 0x0, sum = 1
8950 23:46:13.578287 15, 0x0, sum = 2
8951 23:46:13.578369 16, 0x0, sum = 3
8952 23:46:13.581779 17, 0x0, sum = 4
8953 23:46:13.581861 best_step = 15
8954 23:46:13.581925
8955 23:46:13.581984 ==
8956 23:46:13.585127 Dram Type= 6, Freq= 0, CH_1, rank 1
8957 23:46:13.591506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8958 23:46:13.591588 ==
8959 23:46:13.591652 RX Vref Scan: 0
8960 23:46:13.591712
8961 23:46:13.595312 RX Vref 0 -> 0, step: 1
8962 23:46:13.595392
8963 23:46:13.598750 RX Delay 11 -> 252, step: 4
8964 23:46:13.601848 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8965 23:46:13.604875 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8966 23:46:13.608369 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8967 23:46:13.614647 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8968 23:46:13.618021 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8969 23:46:13.620995 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8970 23:46:13.624535 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8971 23:46:13.631127 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8972 23:46:13.634579 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8973 23:46:13.637964 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8974 23:46:13.640756 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8975 23:46:13.644064 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8976 23:46:13.650656 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8977 23:46:13.653854 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8978 23:46:13.657450 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8979 23:46:13.660554 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8980 23:46:13.660636 ==
8981 23:46:13.664175 Dram Type= 6, Freq= 0, CH_1, rank 1
8982 23:46:13.670787 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8983 23:46:13.670871 ==
8984 23:46:13.670956 DQS Delay:
8985 23:46:13.673788 DQS0 = 0, DQS1 = 0
8986 23:46:13.673872 DQM Delay:
8987 23:46:13.673992 DQM0 = 132, DQM1 = 127
8988 23:46:13.677702 DQ Delay:
8989 23:46:13.681163 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
8990 23:46:13.683518 DQ4 =130, DQ5 =144, DQ6 =142, DQ7 =130
8991 23:46:13.687577 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8992 23:46:13.690117 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8993 23:46:13.690201
8994 23:46:13.690285
8995 23:46:13.690364
8996 23:46:13.693842 [DramC_TX_OE_Calibration] TA2
8997 23:46:13.697003 Original DQ_B0 (3 6) =30, OEN = 27
8998 23:46:13.700430 Original DQ_B1 (3 6) =30, OEN = 27
8999 23:46:13.703590 24, 0x0, End_B0=24 End_B1=24
9000 23:46:13.706944 25, 0x0, End_B0=25 End_B1=25
9001 23:46:13.707029 26, 0x0, End_B0=26 End_B1=26
9002 23:46:13.710227 27, 0x0, End_B0=27 End_B1=27
9003 23:46:13.713546 28, 0x0, End_B0=28 End_B1=28
9004 23:46:13.717158 29, 0x0, End_B0=29 End_B1=29
9005 23:46:13.717243 30, 0x0, End_B0=30 End_B1=30
9006 23:46:13.719790 31, 0x5151, End_B0=30 End_B1=30
9007 23:46:13.723214 Byte0 end_step=30 best_step=27
9008 23:46:13.726650 Byte1 end_step=30 best_step=27
9009 23:46:13.729777 Byte0 TX OE(2T, 0.5T) = (3, 3)
9010 23:46:13.732919 Byte1 TX OE(2T, 0.5T) = (3, 3)
9011 23:46:13.733003
9012 23:46:13.733086
9013 23:46:13.739627 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
9014 23:46:13.743905 CH1 RK1: MR19=303, MR18=F1D
9015 23:46:13.749622 CH1_RK1: MR19=0x303, MR18=0xF1D, DQSOSC=395, MR23=63, INC=23, DEC=15
9016 23:46:13.752625 [RxdqsGatingPostProcess] freq 1600
9017 23:46:13.759692 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9018 23:46:13.759793 best DQS0 dly(2T, 0.5T) = (1, 1)
9019 23:46:13.762667 best DQS1 dly(2T, 0.5T) = (1, 1)
9020 23:46:13.765754 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9021 23:46:13.769097 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9022 23:46:13.772359 best DQS0 dly(2T, 0.5T) = (1, 1)
9023 23:46:13.776011 best DQS1 dly(2T, 0.5T) = (1, 1)
9024 23:46:13.778889 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9025 23:46:13.782507 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9026 23:46:13.785624 Pre-setting of DQS Precalculation
9027 23:46:13.788758 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9028 23:46:13.798675 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9029 23:46:13.806029 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9030 23:46:13.806113
9031 23:46:13.806197
9032 23:46:13.808979 [Calibration Summary] 3200 Mbps
9033 23:46:13.809063 CH 0, Rank 0
9034 23:46:13.811910 SW Impedance : PASS
9035 23:46:13.811995 DUTY Scan : NO K
9036 23:46:13.815090 ZQ Calibration : PASS
9037 23:46:13.818778 Jitter Meter : NO K
9038 23:46:13.818861 CBT Training : PASS
9039 23:46:13.822052 Write leveling : PASS
9040 23:46:13.824904 RX DQS gating : PASS
9041 23:46:13.824987 RX DQ/DQS(RDDQC) : PASS
9042 23:46:13.828829 TX DQ/DQS : PASS
9043 23:46:13.831822 RX DATLAT : PASS
9044 23:46:13.831906 RX DQ/DQS(Engine): PASS
9045 23:46:13.835187 TX OE : PASS
9046 23:46:13.835271 All Pass.
9047 23:46:13.835355
9048 23:46:13.838638 CH 0, Rank 1
9049 23:46:13.838722 SW Impedance : PASS
9050 23:46:13.841453 DUTY Scan : NO K
9051 23:46:13.846052 ZQ Calibration : PASS
9052 23:46:13.846135 Jitter Meter : NO K
9053 23:46:13.848137 CBT Training : PASS
9054 23:46:13.851303 Write leveling : PASS
9055 23:46:13.851387 RX DQS gating : PASS
9056 23:46:13.855003 RX DQ/DQS(RDDQC) : PASS
9057 23:46:13.857897 TX DQ/DQS : PASS
9058 23:46:13.857981 RX DATLAT : PASS
9059 23:46:13.861279 RX DQ/DQS(Engine): PASS
9060 23:46:13.864651 TX OE : PASS
9061 23:46:13.864735 All Pass.
9062 23:46:13.864819
9063 23:46:13.864899 CH 1, Rank 0
9064 23:46:13.867649 SW Impedance : PASS
9065 23:46:13.871202 DUTY Scan : NO K
9066 23:46:13.871286 ZQ Calibration : PASS
9067 23:46:13.874734 Jitter Meter : NO K
9068 23:46:13.877590 CBT Training : PASS
9069 23:46:13.877674 Write leveling : PASS
9070 23:46:13.881181 RX DQS gating : PASS
9071 23:46:13.884794 RX DQ/DQS(RDDQC) : PASS
9072 23:46:13.884879 TX DQ/DQS : PASS
9073 23:46:13.887976 RX DATLAT : PASS
9074 23:46:13.888061 RX DQ/DQS(Engine): PASS
9075 23:46:13.891119 TX OE : PASS
9076 23:46:13.891204 All Pass.
9077 23:46:13.891289
9078 23:46:13.894364 CH 1, Rank 1
9079 23:46:13.897591 SW Impedance : PASS
9080 23:46:13.897675 DUTY Scan : NO K
9081 23:46:13.900796 ZQ Calibration : PASS
9082 23:46:13.900879 Jitter Meter : NO K
9083 23:46:13.904646 CBT Training : PASS
9084 23:46:13.907687 Write leveling : PASS
9085 23:46:13.907771 RX DQS gating : PASS
9086 23:46:13.910851 RX DQ/DQS(RDDQC) : PASS
9087 23:46:13.914405 TX DQ/DQS : PASS
9088 23:46:13.914492 RX DATLAT : PASS
9089 23:46:13.917554 RX DQ/DQS(Engine): PASS
9090 23:46:13.920363 TX OE : PASS
9091 23:46:13.920447 All Pass.
9092 23:46:13.920548
9093 23:46:13.923642 DramC Write-DBI on
9094 23:46:13.923739 PER_BANK_REFRESH: Hybrid Mode
9095 23:46:13.926737 TX_TRACKING: ON
9096 23:46:13.936539 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9097 23:46:13.943507 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9098 23:46:13.951399 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9099 23:46:13.953370 [FAST_K] Save calibration result to emmc
9100 23:46:13.956605 sync common calibartion params.
9101 23:46:13.959848 sync cbt_mode0:1, 1:1
9102 23:46:13.963430 dram_init: ddr_geometry: 2
9103 23:46:13.963514 dram_init: ddr_geometry: 2
9104 23:46:13.966589 dram_init: ddr_geometry: 2
9105 23:46:13.969634 0:dram_rank_size:100000000
9106 23:46:13.969750 1:dram_rank_size:100000000
9107 23:46:13.976450 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9108 23:46:13.980433 DFS_SHUFFLE_HW_MODE: ON
9109 23:46:13.982678 dramc_set_vcore_voltage set vcore to 725000
9110 23:46:13.986233 Read voltage for 1600, 0
9111 23:46:13.986317 Vio18 = 0
9112 23:46:13.986401 Vcore = 725000
9113 23:46:13.989820 Vdram = 0
9114 23:46:13.989904 Vddq = 0
9115 23:46:13.989988 Vmddr = 0
9116 23:46:13.992854 switch to 3200 Mbps bootup
9117 23:46:13.996453 [DramcRunTimeConfig]
9118 23:46:13.996537 PHYPLL
9119 23:46:13.996622 DPM_CONTROL_AFTERK: ON
9120 23:46:13.999000 PER_BANK_REFRESH: ON
9121 23:46:14.002729 REFRESH_OVERHEAD_REDUCTION: ON
9122 23:46:14.002813 CMD_PICG_NEW_MODE: OFF
9123 23:46:14.005900 XRTWTW_NEW_MODE: ON
9124 23:46:14.009401 XRTRTR_NEW_MODE: ON
9125 23:46:14.009484 TX_TRACKING: ON
9126 23:46:14.012688 RDSEL_TRACKING: OFF
9127 23:46:14.012772 DQS Precalculation for DVFS: ON
9128 23:46:14.015641 RX_TRACKING: OFF
9129 23:46:14.015724 HW_GATING DBG: ON
9130 23:46:14.018999 ZQCS_ENABLE_LP4: ON
9131 23:46:14.019083 RX_PICG_NEW_MODE: ON
9132 23:46:14.022251 TX_PICG_NEW_MODE: ON
9133 23:46:14.025437 ENABLE_RX_DCM_DPHY: ON
9134 23:46:14.028777 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9135 23:46:14.028862 DUMMY_READ_FOR_TRACKING: OFF
9136 23:46:14.032432 !!! SPM_CONTROL_AFTERK: OFF
9137 23:46:14.035341 !!! SPM could not control APHY
9138 23:46:14.039171 IMPEDANCE_TRACKING: ON
9139 23:46:14.039254 TEMP_SENSOR: ON
9140 23:46:14.042392 HW_SAVE_FOR_SR: OFF
9141 23:46:14.045394 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9142 23:46:14.049008 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9143 23:46:14.049091 Read ODT Tracking: ON
9144 23:46:14.052048 Refresh Rate DeBounce: ON
9145 23:46:14.055407 DFS_NO_QUEUE_FLUSH: ON
9146 23:46:14.058592 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9147 23:46:14.058676 ENABLE_DFS_RUNTIME_MRW: OFF
9148 23:46:14.061713 DDR_RESERVE_NEW_MODE: ON
9149 23:46:14.065053 MR_CBT_SWITCH_FREQ: ON
9150 23:46:14.065136 =========================
9151 23:46:14.085177 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9152 23:46:14.088371 dram_init: ddr_geometry: 2
9153 23:46:14.106568 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9154 23:46:14.109834 dram_init: dram init end (result: 0)
9155 23:46:14.116143 DRAM-K: Full calibration passed in 24352 msecs
9156 23:46:14.119516 MRC: failed to locate region type 0.
9157 23:46:14.119600 DRAM rank0 size:0x100000000,
9158 23:46:14.122869 DRAM rank1 size=0x100000000
9159 23:46:14.132631 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9160 23:46:14.139356 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9161 23:46:14.149370 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9162 23:46:14.155955 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9163 23:46:14.156060 DRAM rank0 size:0x100000000,
9164 23:46:14.159157 DRAM rank1 size=0x100000000
9165 23:46:14.159242 CBMEM:
9166 23:46:14.162128 IMD: root @ 0xfffff000 254 entries.
9167 23:46:14.165968 IMD: root @ 0xffffec00 62 entries.
9168 23:46:14.172685 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9169 23:46:14.175592 WARNING: RO_VPD is uninitialized or empty.
9170 23:46:14.178829 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9171 23:46:14.186660 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9172 23:46:14.199708 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9173 23:46:14.211260 BS: romstage times (exec / console): total (unknown) / 23897 ms
9174 23:46:14.211346
9175 23:46:14.211431
9176 23:46:14.220740 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9177 23:46:14.224057 ARM64: Exception handlers installed.
9178 23:46:14.227590 ARM64: Testing exception
9179 23:46:14.230973 ARM64: Done test exception
9180 23:46:14.231057 Enumerating buses...
9181 23:46:14.234182 Show all devs... Before device enumeration.
9182 23:46:14.237183 Root Device: enabled 1
9183 23:46:14.240576 CPU_CLUSTER: 0: enabled 1
9184 23:46:14.240660 CPU: 00: enabled 1
9185 23:46:14.243581 Compare with tree...
9186 23:46:14.243665 Root Device: enabled 1
9187 23:46:14.247297 CPU_CLUSTER: 0: enabled 1
9188 23:46:14.250621 CPU: 00: enabled 1
9189 23:46:14.250710 Root Device scanning...
9190 23:46:14.253745 scan_static_bus for Root Device
9191 23:46:14.256588 CPU_CLUSTER: 0 enabled
9192 23:46:14.260096 scan_static_bus for Root Device done
9193 23:46:14.263228 scan_bus: bus Root Device finished in 8 msecs
9194 23:46:14.263312 done
9195 23:46:14.270079 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9196 23:46:14.273566 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9197 23:46:14.280495 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9198 23:46:14.286613 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9199 23:46:14.286698 Allocating resources...
9200 23:46:14.290029 Reading resources...
9201 23:46:14.292920 Root Device read_resources bus 0 link: 0
9202 23:46:14.296470 DRAM rank0 size:0x100000000,
9203 23:46:14.296553 DRAM rank1 size=0x100000000
9204 23:46:14.302967 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9205 23:46:14.303051 CPU: 00 missing read_resources
9206 23:46:14.309476 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9207 23:46:14.312815 Root Device read_resources bus 0 link: 0 done
9208 23:46:14.316220 Done reading resources.
9209 23:46:14.320048 Show resources in subtree (Root Device)...After reading.
9210 23:46:14.322843 Root Device child on link 0 CPU_CLUSTER: 0
9211 23:46:14.327153 CPU_CLUSTER: 0 child on link 0 CPU: 00
9212 23:46:14.335983 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9213 23:46:14.336065 CPU: 00
9214 23:46:14.342252 Root Device assign_resources, bus 0 link: 0
9215 23:46:14.345548 CPU_CLUSTER: 0 missing set_resources
9216 23:46:14.349094 Root Device assign_resources, bus 0 link: 0 done
9217 23:46:14.352173 Done setting resources.
9218 23:46:14.355612 Show resources in subtree (Root Device)...After assigning values.
9219 23:46:14.362066 Root Device child on link 0 CPU_CLUSTER: 0
9220 23:46:14.365213 CPU_CLUSTER: 0 child on link 0 CPU: 00
9221 23:46:14.371732 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9222 23:46:14.374996 CPU: 00
9223 23:46:14.375077 Done allocating resources.
9224 23:46:14.381943 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9225 23:46:14.385056 Enabling resources...
9226 23:46:14.385136 done.
9227 23:46:14.388308 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9228 23:46:14.391626 Initializing devices...
9229 23:46:14.391714 Root Device init
9230 23:46:14.394770 init hardware done!
9231 23:46:14.398377 0x00000018: ctrlr->caps
9232 23:46:14.398460 52.000 MHz: ctrlr->f_max
9233 23:46:14.402133 0.400 MHz: ctrlr->f_min
9234 23:46:14.404641 0x40ff8080: ctrlr->voltages
9235 23:46:14.404724 sclk: 390625
9236 23:46:14.404789 Bus Width = 1
9237 23:46:14.407947 sclk: 390625
9238 23:46:14.408029 Bus Width = 1
9239 23:46:14.411438 Early init status = 3
9240 23:46:14.415285 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9241 23:46:14.418694 in-header: 03 fc 00 00 01 00 00 00
9242 23:46:14.421753 in-data: 00
9243 23:46:14.424793 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9244 23:46:14.429805 in-header: 03 fd 00 00 00 00 00 00
9245 23:46:14.433554 in-data:
9246 23:46:14.436332 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9247 23:46:14.440076 in-header: 03 fc 00 00 01 00 00 00
9248 23:46:14.442845 in-data: 00
9249 23:46:14.446340 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9250 23:46:14.451697 in-header: 03 fd 00 00 00 00 00 00
9251 23:46:14.454572 in-data:
9252 23:46:14.457831 [SSUSB] Setting up USB HOST controller...
9253 23:46:14.461006 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9254 23:46:14.464658 [SSUSB] phy power-on done.
9255 23:46:14.467702 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9256 23:46:14.474736 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9257 23:46:14.477699 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9258 23:46:14.484279 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9259 23:46:14.490678 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9260 23:46:14.497440 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9261 23:46:14.504247 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9262 23:46:14.510569 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9263 23:46:14.514091 SPM: binary array size = 0x9dc
9264 23:46:14.516876 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9265 23:46:14.523678 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9266 23:46:14.531251 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9267 23:46:14.537146 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9268 23:46:14.540535 configure_display: Starting display init
9269 23:46:14.575010 anx7625_power_on_init: Init interface.
9270 23:46:14.577606 anx7625_disable_pd_protocol: Disabled PD feature.
9271 23:46:14.581138 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9272 23:46:14.608929 anx7625_start_dp_work: Secure OCM version=00
9273 23:46:14.612009 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9274 23:46:14.626892 sp_tx_get_edid_block: EDID Block = 1
9275 23:46:14.729397 Extracted contents:
9276 23:46:14.733270 header: 00 ff ff ff ff ff ff 00
9277 23:46:14.736356 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9278 23:46:14.739566 version: 01 04
9279 23:46:14.743132 basic params: 95 1f 11 78 0a
9280 23:46:14.746206 chroma info: 76 90 94 55 54 90 27 21 50 54
9281 23:46:14.749409 established: 00 00 00
9282 23:46:14.756261 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9283 23:46:14.763040 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9284 23:46:14.765787 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9285 23:46:14.772409 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9286 23:46:14.778796 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9287 23:46:14.782483 extensions: 00
9288 23:46:14.782569 checksum: fb
9289 23:46:14.782655
9290 23:46:14.788803 Manufacturer: IVO Model 57d Serial Number 0
9291 23:46:14.788890 Made week 0 of 2020
9292 23:46:14.791904 EDID version: 1.4
9293 23:46:14.791990 Digital display
9294 23:46:14.795403 6 bits per primary color channel
9295 23:46:14.798852 DisplayPort interface
9296 23:46:14.798936 Maximum image size: 31 cm x 17 cm
9297 23:46:14.802022 Gamma: 220%
9298 23:46:14.802105 Check DPMS levels
9299 23:46:14.808764 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9300 23:46:14.812203 First detailed timing is preferred timing
9301 23:46:14.812288 Established timings supported:
9302 23:46:14.815060 Standard timings supported:
9303 23:46:14.818655 Detailed timings
9304 23:46:14.821678 Hex of detail: 383680a07038204018303c0035ae10000019
9305 23:46:14.828506 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9306 23:46:14.831921 0780 0798 07c8 0820 hborder 0
9307 23:46:14.835141 0438 043b 0447 0458 vborder 0
9308 23:46:14.838516 -hsync -vsync
9309 23:46:14.838600 Did detailed timing
9310 23:46:14.844950 Hex of detail: 000000000000000000000000000000000000
9311 23:46:14.848183 Manufacturer-specified data, tag 0
9312 23:46:14.851250 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9313 23:46:14.854736 ASCII string: InfoVision
9314 23:46:14.857892 Hex of detail: 000000fe00523134304e574635205248200a
9315 23:46:14.861222 ASCII string: R140NWF5 RH
9316 23:46:14.861338 Checksum
9317 23:46:14.864368 Checksum: 0xfb (valid)
9318 23:46:14.868221 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9319 23:46:14.871321 DSI data_rate: 832800000 bps
9320 23:46:14.878037 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9321 23:46:14.881293 anx7625_parse_edid: pixelclock(138800).
9322 23:46:14.884788 hactive(1920), hsync(48), hfp(24), hbp(88)
9323 23:46:14.887910 vactive(1080), vsync(12), vfp(3), vbp(17)
9324 23:46:14.891616 anx7625_dsi_config: config dsi.
9325 23:46:14.897355 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9326 23:46:14.911672 anx7625_dsi_config: success to config DSI
9327 23:46:14.914722 anx7625_dp_start: MIPI phy setup OK.
9328 23:46:14.918058 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9329 23:46:14.921239 mtk_ddp_mode_set invalid vrefresh 60
9330 23:46:14.924500 main_disp_path_setup
9331 23:46:14.924584 ovl_layer_smi_id_en
9332 23:46:14.927687 ovl_layer_smi_id_en
9333 23:46:14.927858 ccorr_config
9334 23:46:14.927964 aal_config
9335 23:46:14.931283 gamma_config
9336 23:46:14.931366 postmask_config
9337 23:46:14.934704 dither_config
9338 23:46:14.938124 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9339 23:46:14.944062 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9340 23:46:14.947688 Root Device init finished in 551 msecs
9341 23:46:14.950787 CPU_CLUSTER: 0 init
9342 23:46:14.957416 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9343 23:46:14.963956 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9344 23:46:14.964036 APU_MBOX 0x190000b0 = 0x10001
9345 23:46:14.967515 APU_MBOX 0x190001b0 = 0x10001
9346 23:46:14.970623 APU_MBOX 0x190005b0 = 0x10001
9347 23:46:14.974115 APU_MBOX 0x190006b0 = 0x10001
9348 23:46:14.980186 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9349 23:46:14.990647 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9350 23:46:15.002932 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9351 23:46:15.010094 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9352 23:46:15.021243 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9353 23:46:15.030147 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9354 23:46:15.033478 CPU_CLUSTER: 0 init finished in 81 msecs
9355 23:46:15.037186 Devices initialized
9356 23:46:15.040257 Show all devs... After init.
9357 23:46:15.040352 Root Device: enabled 1
9358 23:46:15.043465 CPU_CLUSTER: 0: enabled 1
9359 23:46:15.046634 CPU: 00: enabled 1
9360 23:46:15.050238 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9361 23:46:15.053428 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9362 23:46:15.056950 ELOG: NV offset 0x57f000 size 0x1000
9363 23:46:15.063680 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9364 23:46:15.070491 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9365 23:46:15.073675 ELOG: Event(17) added with size 13 at 2024-06-04 23:46:15 UTC
9366 23:46:15.080100 out: cmd=0x121: 03 db 21 01 00 00 00 00
9367 23:46:15.083189 in-header: 03 3b 00 00 2c 00 00 00
9368 23:46:15.092995 in-data: 02 72 00 00 00 00 00 00 0a 18 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9369 23:46:15.099696 ELOG: Event(A1) added with size 10 at 2024-06-04 23:46:15 UTC
9370 23:46:15.107100 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x02
9371 23:46:15.113651 ELOG: Event(A0) added with size 9 at 2024-06-04 23:46:15 UTC
9372 23:46:15.116727 elog_add_boot_reason: Logged dev mode boot
9373 23:46:15.123128 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9374 23:46:15.123209 Finalize devices...
9375 23:46:15.126279 Devices finalized
9376 23:46:15.129873 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9377 23:46:15.133160 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
9378 23:46:15.136339 in-header: 03 07 00 00 08 00 00 00
9379 23:46:15.139537 in-data: aa e4 47 04 13 02 00 00
9380 23:46:15.143075 Chrome EC: UHEPI supported
9381 23:46:15.149424 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
9382 23:46:15.152900 in-header: 03 a9 00 00 08 00 00 00
9383 23:46:15.155900 in-data: 84 60 60 08 00 00 00 00
9384 23:46:15.162874 ELOG: Event(91) added with size 10 at 2024-06-04 23:46:15 UTC
9385 23:46:15.165657 Chrome EC: clear events_b mask to 0x0000000020004000
9386 23:46:15.172091 out: cmd=0xa4: 03 ea a4 00 00 00 0c 00 02 01 00 00 00 40 00 20 00 00 00 00
9387 23:46:15.177105 in-header: 03 fd 00 00 00 00 00 00
9388 23:46:15.180093 in-data:
9389 23:46:15.183277 BS: BS_WRITE_TABLES entry times (exec / console): 3 / 46 ms
9390 23:46:15.186383 Writing coreboot table at 0xffe64000
9391 23:46:15.193445 0. 000000000010a000-0000000000113fff: RAMSTAGE
9392 23:46:15.196382 1. 0000000040000000-00000000400fffff: RAM
9393 23:46:15.199609 2. 0000000040100000-000000004032afff: RAMSTAGE
9394 23:46:15.203257 3. 000000004032b000-00000000545fffff: RAM
9395 23:46:15.206520 4. 0000000054600000-000000005465ffff: BL31
9396 23:46:15.209645 5. 0000000054660000-00000000ffe63fff: RAM
9397 23:46:15.216285 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9398 23:46:15.219488 7. 0000000100000000-000000023fffffff: RAM
9399 23:46:15.223162 Passing 5 GPIOs to payload:
9400 23:46:15.225783 NAME | PORT | POLARITY | VALUE
9401 23:46:15.232736 EC in RW | 0x000000aa | low | undefined
9402 23:46:15.236502 EC interrupt | 0x00000005 | low | undefined
9403 23:46:15.242289 TPM interrupt | 0x000000ab | high | undefined
9404 23:46:15.246440 SD card detect | 0x00000011 | high | undefined
9405 23:46:15.249431 speaker enable | 0x00000093 | high | undefined
9406 23:46:15.255509 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9407 23:46:15.258869 in-header: 03 f9 00 00 02 00 00 00
9408 23:46:15.258953 in-data: 02 00
9409 23:46:15.262191 ADC[4]: Raw value=901847 ID=7
9410 23:46:15.265402 ADC[3]: Raw value=213546 ID=1
9411 23:46:15.265486 RAM Code: 0x71
9412 23:46:15.269066 ADC[6]: Raw value=74630 ID=0
9413 23:46:15.272266 ADC[5]: Raw value=213546 ID=1
9414 23:46:15.272350 SKU Code: 0x1
9415 23:46:15.279077 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a354
9416 23:46:15.281972 coreboot table: 964 bytes.
9417 23:46:15.285753 IMD ROOT 0. 0xfffff000 0x00001000
9418 23:46:15.288578 IMD SMALL 1. 0xffffe000 0x00001000
9419 23:46:15.291812 RO MCACHE 2. 0xffffc000 0x00001104
9420 23:46:15.295345 CONSOLE 3. 0xfff7c000 0x00080000
9421 23:46:15.298648 FMAP 4. 0xfff7b000 0x00000452
9422 23:46:15.301744 TIME STAMP 5. 0xfff7a000 0x00000910
9423 23:46:15.305002 VBOOT WORK 6. 0xfff66000 0x00014000
9424 23:46:15.308335 RAMOOPS 7. 0xffe66000 0x00100000
9425 23:46:15.312012 COREBOOT 8. 0xffe64000 0x00002000
9426 23:46:15.312103 IMD small region:
9427 23:46:15.315169 IMD ROOT 0. 0xffffec00 0x00000400
9428 23:46:15.318253 VPD 1. 0xffffeb80 0x0000006c
9429 23:46:15.321321 MMC STATUS 2. 0xffffeb60 0x00000004
9430 23:46:15.327902 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9431 23:46:15.334865 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9432 23:46:15.373836 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9433 23:46:15.377232 Checking segment from ROM address 0x40100000
9434 23:46:15.384496 Checking segment from ROM address 0x4010001c
9435 23:46:15.386641 Loading segment from ROM address 0x40100000
9436 23:46:15.386725 code (compression=0)
9437 23:46:15.396916 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9438 23:46:15.403107 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9439 23:46:15.406435 it's not compressed!
9440 23:46:15.409814 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9441 23:46:15.416343 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9442 23:46:15.434119 Loading segment from ROM address 0x4010001c
9443 23:46:15.434208 Entry Point 0x80000000
9444 23:46:15.437233 Loaded segments
9445 23:46:15.440597 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9446 23:46:15.447166 Jumping to boot code at 0x80000000(0xffe64000)
9447 23:46:15.453792 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9448 23:46:15.460321 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9449 23:46:15.468548 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9450 23:46:15.472216 Checking segment from ROM address 0x40100000
9451 23:46:15.475657 Checking segment from ROM address 0x4010001c
9452 23:46:15.481815 Loading segment from ROM address 0x40100000
9453 23:46:15.481900 code (compression=1)
9454 23:46:15.488916 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9455 23:46:15.498624 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9456 23:46:15.498710 using LZMA
9457 23:46:15.507144 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9458 23:46:15.513731 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9459 23:46:15.517177 Loading segment from ROM address 0x4010001c
9460 23:46:15.520404 Entry Point 0x54601000
9461 23:46:15.520488 Loaded segments
9462 23:46:15.523489 NOTICE: MT8192 bl31_setup
9463 23:46:15.530481 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9464 23:46:15.534335 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9465 23:46:15.537678 WARNING: region 0:
9466 23:46:15.540312 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9467 23:46:15.540395 WARNING: region 1:
9468 23:46:15.547268 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9469 23:46:15.550253 WARNING: region 2:
9470 23:46:15.553560 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9471 23:46:15.557039 WARNING: region 3:
9472 23:46:15.563367 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9473 23:46:15.563478 WARNING: region 4:
9474 23:46:15.569792 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9475 23:46:15.569866 WARNING: region 5:
9476 23:46:15.573142 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9477 23:46:15.576412 WARNING: region 6:
9478 23:46:15.579637 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9479 23:46:15.583154 WARNING: region 7:
9480 23:46:15.586203 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 23:46:15.593316 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9482 23:46:15.597379 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9483 23:46:15.602986 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9484 23:46:15.606303 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9485 23:46:15.609845 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9486 23:46:15.616508 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9487 23:46:15.619769 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9488 23:46:15.622705 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9489 23:46:15.629421 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9490 23:46:15.632766 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9491 23:46:15.638958 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9492 23:46:15.642468 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9493 23:46:15.645879 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9494 23:46:15.652452 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9495 23:46:15.655510 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9496 23:46:15.662028 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9497 23:46:15.665208 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9498 23:46:15.668425 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9499 23:46:15.675258 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9500 23:46:15.678426 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9501 23:46:15.684774 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9502 23:46:15.688580 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9503 23:46:15.692233 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9504 23:46:15.698457 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9505 23:46:15.701494 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9506 23:46:15.708667 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9507 23:46:15.711418 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9508 23:46:15.714724 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9509 23:46:15.721322 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9510 23:46:15.724594 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9511 23:46:15.731898 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9512 23:46:15.735066 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9513 23:46:15.738239 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9514 23:46:15.744982 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9515 23:46:15.747862 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9516 23:46:15.751155 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9517 23:46:15.754341 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9518 23:46:15.761164 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9519 23:46:15.764320 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9520 23:46:15.767975 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9521 23:46:15.770959 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9522 23:46:15.778005 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9523 23:46:15.780782 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9524 23:46:15.784243 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9525 23:46:15.787301 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9526 23:46:15.793686 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9527 23:46:15.798085 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9528 23:46:15.800536 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9529 23:46:15.807225 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9530 23:46:15.810376 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9531 23:46:15.816947 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9532 23:46:15.820227 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9533 23:46:15.826954 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9534 23:46:15.830138 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9535 23:46:15.833667 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9536 23:46:15.840508 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9537 23:46:15.843751 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9538 23:46:15.850135 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9539 23:46:15.853751 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9540 23:46:15.859896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9541 23:46:15.863307 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9542 23:46:15.869835 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9543 23:46:15.872784 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9544 23:46:15.876842 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9545 23:46:15.883514 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9546 23:46:15.886306 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9547 23:46:15.892801 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9548 23:46:15.896473 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9549 23:46:15.902720 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9550 23:46:15.905963 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9551 23:46:15.912420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9552 23:46:15.915708 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9553 23:46:15.918936 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9554 23:46:15.925660 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9555 23:46:15.929051 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9556 23:46:15.935745 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9557 23:46:15.939151 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9558 23:46:15.945783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9559 23:46:15.949118 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9560 23:46:15.955444 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9561 23:46:15.958826 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9562 23:46:15.965579 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9563 23:46:15.969110 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9564 23:46:15.972115 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9565 23:46:15.978410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9566 23:46:15.982166 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9567 23:46:15.988655 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9568 23:46:15.992512 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9569 23:46:15.998662 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9570 23:46:16.001432 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9571 23:46:16.004937 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9572 23:46:16.011490 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9573 23:46:16.015146 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9574 23:46:16.021525 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9575 23:46:16.024864 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9576 23:46:16.031419 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9577 23:46:16.034402 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9578 23:46:16.037976 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9579 23:46:16.045036 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9580 23:46:16.047603 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9581 23:46:16.050985 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9582 23:46:16.057987 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9583 23:46:16.061022 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9584 23:46:16.064160 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9585 23:46:16.071563 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9586 23:46:16.074193 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9587 23:46:16.080813 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9588 23:46:16.084355 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9589 23:46:16.088027 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9590 23:46:16.094088 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9591 23:46:16.097147 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9592 23:46:16.103841 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9593 23:46:16.107861 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9594 23:46:16.113886 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9595 23:46:16.116868 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9596 23:46:16.121696 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9597 23:46:16.123388 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9598 23:46:16.129777 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9599 23:46:16.133169 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9600 23:46:16.139998 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9601 23:46:16.143092 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9602 23:46:16.146545 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9603 23:46:16.150080 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9604 23:46:16.156586 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9605 23:46:16.159414 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9606 23:46:16.162785 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9607 23:46:16.169530 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9608 23:46:16.173138 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9609 23:46:16.179841 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9610 23:46:16.183411 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9611 23:46:16.186155 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9612 23:46:16.192651 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9613 23:46:16.195925 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9614 23:46:16.202807 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9615 23:46:16.205925 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9616 23:46:16.208879 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9617 23:46:16.215519 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9618 23:46:16.219279 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9619 23:46:16.225501 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9620 23:46:16.229049 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9621 23:46:16.232340 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9622 23:46:16.238726 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9623 23:46:16.242361 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9624 23:46:16.248507 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9625 23:46:16.252612 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9626 23:46:16.255226 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9627 23:46:16.262018 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9628 23:46:16.265106 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9629 23:46:16.272098 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9630 23:46:16.275145 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9631 23:46:16.278789 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9632 23:46:16.285434 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9633 23:46:16.288117 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9634 23:46:16.294747 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9635 23:46:16.298745 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9636 23:46:16.302313 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9637 23:46:16.307871 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9638 23:46:16.311875 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9639 23:46:16.318846 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9640 23:46:16.321476 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9641 23:46:16.324740 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9642 23:46:16.331474 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9643 23:46:16.334675 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9644 23:46:16.341221 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9645 23:46:16.344339 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9646 23:46:16.347792 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9647 23:46:16.354452 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9648 23:46:16.358449 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9649 23:46:16.360973 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9650 23:46:16.367492 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9651 23:46:16.371167 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9652 23:46:16.377629 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9653 23:46:16.381169 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9654 23:46:16.384208 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9655 23:46:16.390636 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9656 23:46:16.394315 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9657 23:46:16.400578 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9658 23:46:16.404074 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9659 23:46:16.410239 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9660 23:46:16.413907 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9661 23:46:16.417013 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9662 23:46:16.423408 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9663 23:46:16.426816 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9664 23:46:16.433151 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9665 23:46:16.436787 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9666 23:46:16.439891 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9667 23:46:16.447082 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9668 23:46:16.450008 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9669 23:46:16.457213 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9670 23:46:16.459960 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9671 23:46:16.462875 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9672 23:46:16.469680 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9673 23:46:16.473279 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9674 23:46:16.479447 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9675 23:46:16.482875 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9676 23:46:16.489289 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9677 23:46:16.492503 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9678 23:46:16.496092 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9679 23:46:16.502713 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9680 23:46:16.506013 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9681 23:46:16.513376 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9682 23:46:16.516082 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9683 23:46:16.522580 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9684 23:46:16.525656 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9685 23:46:16.528960 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9686 23:46:16.535761 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9687 23:46:16.539221 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9688 23:46:16.544970 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9689 23:46:16.548788 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9690 23:46:16.555018 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9691 23:46:16.558516 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9692 23:46:16.561495 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9693 23:46:16.568046 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9694 23:46:16.571591 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9695 23:46:16.578278 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9696 23:46:16.581192 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9697 23:46:16.587919 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9698 23:46:16.591208 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9699 23:46:16.597763 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9700 23:46:16.601518 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9701 23:46:16.605373 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9702 23:46:16.610774 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9703 23:46:16.614275 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9704 23:46:16.620619 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9705 23:46:16.624213 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9706 23:46:16.630925 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9707 23:46:16.634023 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9708 23:46:16.637056 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9709 23:46:16.643882 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9710 23:46:16.647046 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9711 23:46:16.650402 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9712 23:46:16.654046 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9713 23:46:16.660768 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9714 23:46:16.663784 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9715 23:46:16.667165 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9716 23:46:16.673356 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9717 23:46:16.676736 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9718 23:46:16.683241 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9719 23:46:16.686801 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9720 23:46:16.690409 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9721 23:46:16.696405 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9722 23:46:16.700308 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9723 23:46:16.703342 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9724 23:46:16.709641 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9725 23:46:16.713137 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9726 23:46:16.716424 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9727 23:46:16.723533 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9728 23:46:16.726238 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9729 23:46:16.732827 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9730 23:46:16.736446 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9731 23:46:16.739445 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9732 23:46:16.745911 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9733 23:46:16.749535 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9734 23:46:16.752609 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9735 23:46:16.759647 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9736 23:46:16.762800 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9737 23:46:16.769437 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9738 23:46:16.772600 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9739 23:46:16.776372 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9740 23:46:16.782998 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9741 23:46:16.785769 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9742 23:46:16.789111 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9743 23:46:16.795556 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9744 23:46:16.798866 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9745 23:46:16.805846 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9746 23:46:16.808935 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9747 23:46:16.811965 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9748 23:46:16.818509 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9749 23:46:16.822391 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9750 23:46:16.825421 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9751 23:46:16.828320 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9752 23:46:16.835188 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9753 23:46:16.838169 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9754 23:46:16.841951 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9755 23:46:16.845210 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9756 23:46:16.851779 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9757 23:46:16.854825 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9758 23:46:16.858348 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9759 23:46:16.861967 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9760 23:46:16.868361 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9761 23:46:16.871597 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9762 23:46:16.874608 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9763 23:46:16.881218 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9764 23:46:16.884952 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9765 23:46:16.891509 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9766 23:46:16.894691 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9767 23:46:16.898049 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9768 23:46:16.904758 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9769 23:46:16.907898 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9770 23:46:16.914429 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9771 23:46:16.917444 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9772 23:46:16.924512 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9773 23:46:16.927553 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9774 23:46:16.930676 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9775 23:46:16.937199 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9776 23:46:16.940641 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9777 23:46:16.947340 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9778 23:46:16.950586 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9779 23:46:16.953583 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9780 23:46:16.960765 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9781 23:46:16.963477 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9782 23:46:16.970803 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9783 23:46:16.973413 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9784 23:46:16.980114 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9785 23:46:16.983525 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9786 23:46:16.987047 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9787 23:46:16.993531 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9788 23:46:16.996969 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9789 23:46:17.003351 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9790 23:46:17.006759 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9791 23:46:17.013202 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9792 23:46:17.016672 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9793 23:46:17.019657 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9794 23:46:17.026643 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9795 23:46:17.029354 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9796 23:46:17.036797 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9797 23:46:17.039294 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9798 23:46:17.042963 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9799 23:46:17.049453 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9800 23:46:17.052918 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9801 23:46:17.059298 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9802 23:46:17.062586 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9803 23:46:17.065989 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9804 23:46:17.072986 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9805 23:46:17.076179 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9806 23:46:17.082981 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9807 23:46:17.086469 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9808 23:46:17.092459 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9809 23:46:17.095697 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9810 23:46:17.099236 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9811 23:46:17.105763 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9812 23:46:17.109265 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9813 23:46:17.115731 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9814 23:46:17.119414 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9815 23:46:17.122059 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9816 23:46:17.128750 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9817 23:46:17.132198 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9818 23:46:17.138890 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9819 23:46:17.142278 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9820 23:46:17.148539 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9821 23:46:17.151782 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9822 23:46:17.155369 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9823 23:46:17.161774 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9824 23:46:17.165534 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9825 23:46:17.171852 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9826 23:46:17.174793 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9827 23:46:17.178269 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9828 23:46:17.184832 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9829 23:46:17.187947 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9830 23:46:17.194622 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9831 23:46:17.198055 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9832 23:46:17.204878 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9833 23:46:17.207777 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9834 23:46:17.211112 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9835 23:46:17.218118 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9836 23:46:17.221241 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9837 23:46:17.227534 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9838 23:46:17.230977 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9839 23:46:17.237787 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9840 23:46:17.240874 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9841 23:46:17.247256 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9842 23:46:17.250848 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9843 23:46:17.254163 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9844 23:46:17.260622 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9845 23:46:17.264268 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9846 23:46:17.270512 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9847 23:46:17.274016 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9848 23:46:17.280665 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9849 23:46:17.283402 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9850 23:46:17.286633 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9851 23:46:17.293557 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9852 23:46:17.296728 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9853 23:46:17.303496 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9854 23:46:17.306691 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9855 23:46:17.313104 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9856 23:46:17.316309 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9857 23:46:17.323143 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9858 23:46:17.326560 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9859 23:46:17.332878 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9860 23:46:17.336540 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9861 23:46:17.339768 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9862 23:46:17.346150 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9863 23:46:17.349634 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9864 23:46:17.356224 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9865 23:46:17.359635 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9866 23:46:17.365695 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9867 23:46:17.369359 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9868 23:46:17.375609 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9869 23:46:17.379118 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9870 23:46:17.382409 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9871 23:46:17.389120 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9872 23:46:17.392415 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9873 23:46:17.399242 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9874 23:46:17.402466 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9875 23:46:17.409554 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9876 23:46:17.412611 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9877 23:46:17.415713 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9878 23:46:17.422812 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9879 23:46:17.425186 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9880 23:46:17.432241 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9881 23:46:17.435278 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9882 23:46:17.441831 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9883 23:46:17.444963 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9884 23:46:17.448604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9885 23:46:17.455591 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9886 23:46:17.458458 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9887 23:46:17.465159 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9888 23:46:17.468114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9889 23:46:17.474831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9890 23:46:17.478354 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9891 23:46:17.484885 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9892 23:46:17.488147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9893 23:46:17.494493 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9894 23:46:17.497906 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9895 23:46:17.505094 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9896 23:46:17.507678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9897 23:46:17.514210 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9898 23:46:17.518005 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9899 23:46:17.524086 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9900 23:46:17.527660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9901 23:46:17.534248 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9902 23:46:17.537683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9903 23:46:17.544203 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9904 23:46:17.547666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9905 23:46:17.554026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9906 23:46:17.557142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9907 23:46:17.564035 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9908 23:46:17.567406 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9909 23:46:17.574115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9910 23:46:17.576725 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9911 23:46:17.583522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9912 23:46:17.587444 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9913 23:46:17.593674 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9914 23:46:17.596797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9915 23:46:17.602928 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9916 23:46:17.603037 INFO: [APUAPC] vio 0
9917 23:46:17.610995 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9918 23:46:17.613961 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9919 23:46:17.616814 INFO: [APUAPC] D0_APC_0: 0x400510
9920 23:46:17.620417 INFO: [APUAPC] D0_APC_1: 0x0
9921 23:46:17.623609 INFO: [APUAPC] D0_APC_2: 0x1540
9922 23:46:17.626760 INFO: [APUAPC] D0_APC_3: 0x0
9923 23:46:17.630146 INFO: [APUAPC] D1_APC_0: 0xffffffff
9924 23:46:17.633401 INFO: [APUAPC] D1_APC_1: 0xffffffff
9925 23:46:17.636652 INFO: [APUAPC] D1_APC_2: 0x3fffff
9926 23:46:17.640541 INFO: [APUAPC] D1_APC_3: 0x0
9927 23:46:17.643697 INFO: [APUAPC] D2_APC_0: 0xffffffff
9928 23:46:17.646446 INFO: [APUAPC] D2_APC_1: 0xffffffff
9929 23:46:17.650219 INFO: [APUAPC] D2_APC_2: 0x3fffff
9930 23:46:17.653155 INFO: [APUAPC] D2_APC_3: 0x0
9931 23:46:17.657084 INFO: [APUAPC] D3_APC_0: 0xffffffff
9932 23:46:17.659950 INFO: [APUAPC] D3_APC_1: 0xffffffff
9933 23:46:17.663099 INFO: [APUAPC] D3_APC_2: 0x3fffff
9934 23:46:17.666658 INFO: [APUAPC] D3_APC_3: 0x0
9935 23:46:17.669964 INFO: [APUAPC] D4_APC_0: 0xffffffff
9936 23:46:17.673399 INFO: [APUAPC] D4_APC_1: 0xffffffff
9937 23:46:17.676793 INFO: [APUAPC] D4_APC_2: 0x3fffff
9938 23:46:17.679952 INFO: [APUAPC] D4_APC_3: 0x0
9939 23:46:17.683435 INFO: [APUAPC] D5_APC_0: 0xffffffff
9940 23:46:17.686361 INFO: [APUAPC] D5_APC_1: 0xffffffff
9941 23:46:17.689544 INFO: [APUAPC] D5_APC_2: 0x3fffff
9942 23:46:17.693071 INFO: [APUAPC] D5_APC_3: 0x0
9943 23:46:17.696380 INFO: [APUAPC] D6_APC_0: 0xffffffff
9944 23:46:17.699715 INFO: [APUAPC] D6_APC_1: 0xffffffff
9945 23:46:17.702601 INFO: [APUAPC] D6_APC_2: 0x3fffff
9946 23:46:17.702682 INFO: [APUAPC] D6_APC_3: 0x0
9947 23:46:17.709564 INFO: [APUAPC] D7_APC_0: 0xffffffff
9948 23:46:17.712894 INFO: [APUAPC] D7_APC_1: 0xffffffff
9949 23:46:17.716012 INFO: [APUAPC] D7_APC_2: 0x3fffff
9950 23:46:17.716093 INFO: [APUAPC] D7_APC_3: 0x0
9951 23:46:17.719380 INFO: [APUAPC] D8_APC_0: 0xffffffff
9952 23:46:17.726080 INFO: [APUAPC] D8_APC_1: 0xffffffff
9953 23:46:17.726161 INFO: [APUAPC] D8_APC_2: 0x3fffff
9954 23:46:17.729067 INFO: [APUAPC] D8_APC_3: 0x0
9955 23:46:17.732698 INFO: [APUAPC] D9_APC_0: 0xffffffff
9956 23:46:17.735860 INFO: [APUAPC] D9_APC_1: 0xffffffff
9957 23:46:17.739309 INFO: [APUAPC] D9_APC_2: 0x3fffff
9958 23:46:17.742550 INFO: [APUAPC] D9_APC_3: 0x0
9959 23:46:17.746171 INFO: [APUAPC] D10_APC_0: 0xffffffff
9960 23:46:17.749080 INFO: [APUAPC] D10_APC_1: 0xffffffff
9961 23:46:17.752168 INFO: [APUAPC] D10_APC_2: 0x3fffff
9962 23:46:17.755529 INFO: [APUAPC] D10_APC_3: 0x0
9963 23:46:17.758788 INFO: [APUAPC] D11_APC_0: 0xffffffff
9964 23:46:17.762201 INFO: [APUAPC] D11_APC_1: 0xffffffff
9965 23:46:17.769074 INFO: [APUAPC] D11_APC_2: 0x3fffff
9966 23:46:17.769155 INFO: [APUAPC] D11_APC_3: 0x0
9967 23:46:17.771978 INFO: [APUAPC] D12_APC_0: 0xffffffff
9968 23:46:17.778743 INFO: [APUAPC] D12_APC_1: 0xffffffff
9969 23:46:17.782294 INFO: [APUAPC] D12_APC_2: 0x3fffff
9970 23:46:17.782376 INFO: [APUAPC] D12_APC_3: 0x0
9971 23:46:17.788496 INFO: [APUAPC] D13_APC_0: 0xffffffff
9972 23:46:17.792168 INFO: [APUAPC] D13_APC_1: 0xffffffff
9973 23:46:17.795413 INFO: [APUAPC] D13_APC_2: 0x3fffff
9974 23:46:17.795494 INFO: [APUAPC] D13_APC_3: 0x0
9975 23:46:17.801733 INFO: [APUAPC] D14_APC_0: 0xffffffff
9976 23:46:17.805174 INFO: [APUAPC] D14_APC_1: 0xffffffff
9977 23:46:17.808229 INFO: [APUAPC] D14_APC_2: 0x3fffff
9978 23:46:17.811841 INFO: [APUAPC] D14_APC_3: 0x0
9979 23:46:17.814788 INFO: [APUAPC] D15_APC_0: 0xffffffff
9980 23:46:17.818780 INFO: [APUAPC] D15_APC_1: 0xffffffff
9981 23:46:17.822188 INFO: [APUAPC] D15_APC_2: 0x3fffff
9982 23:46:17.825577 INFO: [APUAPC] D15_APC_3: 0x0
9983 23:46:17.825658 INFO: [APUAPC] APC_CON: 0x4
9984 23:46:17.828124 INFO: [NOCDAPC] D0_APC_0: 0x0
9985 23:46:17.831753 INFO: [NOCDAPC] D0_APC_1: 0x0
9986 23:46:17.834822 INFO: [NOCDAPC] D1_APC_0: 0x0
9987 23:46:17.838000 INFO: [NOCDAPC] D1_APC_1: 0xfff
9988 23:46:17.841169 INFO: [NOCDAPC] D2_APC_0: 0x0
9989 23:46:17.844822 INFO: [NOCDAPC] D2_APC_1: 0xfff
9990 23:46:17.847971 INFO: [NOCDAPC] D3_APC_0: 0x0
9991 23:46:17.852130 INFO: [NOCDAPC] D3_APC_1: 0xfff
9992 23:46:17.854323 INFO: [NOCDAPC] D4_APC_0: 0x0
9993 23:46:17.857490 INFO: [NOCDAPC] D4_APC_1: 0xfff
9994 23:46:17.857568 INFO: [NOCDAPC] D5_APC_0: 0x0
9995 23:46:17.861169 INFO: [NOCDAPC] D5_APC_1: 0xfff
9996 23:46:17.864632 INFO: [NOCDAPC] D6_APC_0: 0x0
9997 23:46:17.867837 INFO: [NOCDAPC] D6_APC_1: 0xfff
9998 23:46:17.871107 INFO: [NOCDAPC] D7_APC_0: 0x0
9999 23:46:17.874084 INFO: [NOCDAPC] D7_APC_1: 0xfff
10000 23:46:17.878716 INFO: [NOCDAPC] D8_APC_0: 0x0
10001 23:46:17.880840 INFO: [NOCDAPC] D8_APC_1: 0xfff
10002 23:46:17.884314 INFO: [NOCDAPC] D9_APC_0: 0x0
10003 23:46:17.887710 INFO: [NOCDAPC] D9_APC_1: 0xfff
10004 23:46:17.890522 INFO: [NOCDAPC] D10_APC_0: 0x0
10005 23:46:17.894408 INFO: [NOCDAPC] D10_APC_1: 0xfff
10006 23:46:17.894482 INFO: [NOCDAPC] D11_APC_0: 0x0
10007 23:46:17.897170 INFO: [NOCDAPC] D11_APC_1: 0xfff
10008 23:46:17.900436 INFO: [NOCDAPC] D12_APC_0: 0x0
10009 23:46:17.903637 INFO: [NOCDAPC] D12_APC_1: 0xfff
10010 23:46:17.907030 INFO: [NOCDAPC] D13_APC_0: 0x0
10011 23:46:17.910472 INFO: [NOCDAPC] D13_APC_1: 0xfff
10012 23:46:17.913780 INFO: [NOCDAPC] D14_APC_0: 0x0
10013 23:46:17.917221 INFO: [NOCDAPC] D14_APC_1: 0xfff
10014 23:46:17.920166 INFO: [NOCDAPC] D15_APC_0: 0x0
10015 23:46:17.923752 INFO: [NOCDAPC] D15_APC_1: 0xfff
10016 23:46:17.927126 INFO: [NOCDAPC] APC_CON: 0x4
10017 23:46:17.930455 INFO: [APUAPC] set_apusys_apc done
10018 23:46:17.933658 INFO: [DEVAPC] devapc_init done
10019 23:46:17.937483 INFO: GICv3 without legacy support detected.
10020 23:46:17.939957 INFO: ARM GICv3 driver initialized in EL3
10021 23:46:17.943859 INFO: Maximum SPI INTID supported: 639
10022 23:46:17.950059 INFO: BL31: Initializing runtime services
10023 23:46:17.953662 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10024 23:46:17.956508 INFO: SPM: enable CPC mode
10025 23:46:17.963324 INFO: mcdi ready for mcusys-off-idle and system suspend
10026 23:46:17.966978 INFO: BL31: Preparing for EL3 exit to normal world
10027 23:46:17.969662 INFO: Entry point address = 0x80000000
10028 23:46:17.973184 INFO: SPSR = 0x8
10029 23:46:17.978514
10030 23:46:17.978593
10031 23:46:17.978657
10032 23:46:17.982153 Starting depthcharge on Spherion...
10033 23:46:17.982234
10034 23:46:17.982298 Wipe memory regions:
10035 23:46:17.982358
10036 23:46:17.982959 end: 2.2.3 depthcharge-start (duration 00:00:19) [common]
10037 23:46:17.983057 start: 2.2.4 bootloader-commands (timeout 00:04:27) [common]
10038 23:46:17.983142 Setting prompt string to ['asurada:']
10039 23:46:17.983223 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:27)
10040 23:46:17.985352 [0x00000040000000, 0x00000054600000)
10041 23:46:18.107438
10042 23:46:18.107551 [0x00000054660000, 0x00000080000000)
10043 23:46:18.368056
10044 23:46:18.368201 [0x000000821a7280, 0x000000ffe64000)
10045 23:46:19.112627
10046 23:46:19.112834 [0x00000100000000, 0x00000240000000)
10047 23:46:21.003035
10048 23:46:21.006550 Initializing XHCI USB controller at 0x11200000.
10049 23:46:22.045728
10050 23:46:22.049313 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10051 23:46:22.049392
10052 23:46:22.049455
10053 23:46:22.049738 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10055 23:46:22.150038 asurada: tftpboot 192.168.201.1 14172986/tftp-deploy-6o449hfs/kernel/image.itb 14172986/tftp-deploy-6o449hfs/kernel/cmdline
10056 23:46:22.150164 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10057 23:46:22.150259 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:23)
10058 23:46:22.154554 tftpboot 192.168.201.1 14172986/tftp-deploy-6o449hfs/kernel/image.itp-deploy-6o449hfs/kernel/cmdline
10059 23:46:22.154635
10060 23:46:22.154701 Waiting for link
10061 23:46:22.312846
10062 23:46:22.312963 R8152: Initializing
10063 23:46:22.313034
10064 23:46:22.315930 Version 6 (ocp_data = 5c30)
10065 23:46:22.316000
10066 23:46:22.319530 R8152: Done initializing
10067 23:46:22.319598
10068 23:46:22.319661 Adding net device
10069 23:46:24.192216
10070 23:46:24.192360 done.
10071 23:46:24.192425
10072 23:46:24.192485 MAC: 00:24:32:30:7c:7b
10073 23:46:24.192547
10074 23:46:24.196107 Sending DHCP discover... done.
10075 23:46:24.196177
10076 23:46:34.215738 Waiting for reply... R8152: Bulk read error 0xffffffbf
10077 23:46:34.215892
10078 23:46:34.218000 Receive failed.
10079 23:46:34.218085
10080 23:46:34.218149 done.
10081 23:46:34.218209
10082 23:46:34.221534 Sending DHCP request... done.
10083 23:46:34.221641
10084 23:46:34.227892 Waiting for reply... done.
10085 23:46:34.227974
10086 23:46:34.228037 My ip is 192.168.201.14
10087 23:46:34.228113
10088 23:46:34.231796 The DHCP server ip is 192.168.201.1
10089 23:46:34.231878
10090 23:46:34.234529 TFTP server IP predefined by user: 192.168.201.1
10091 23:46:34.238066
10092 23:46:34.241180 Bootfile predefined by user: 14172986/tftp-deploy-6o449hfs/kernel/image.itb
10093 23:46:34.244530
10094 23:46:34.244606 Sending tftp read request... done.
10095 23:46:34.244671
10096 23:46:34.251401 Waiting for the transfer...
10097 23:46:34.251486
10098 23:46:34.829508 00000000 ################################################################
10099 23:46:34.829654
10100 23:46:35.385092 00080000 ################################################################
10101 23:46:35.385292
10102 23:46:35.959574 00100000 ################################################################
10103 23:46:35.959726
10104 23:46:36.532146 00180000 ################################################################
10105 23:46:36.532282
10106 23:46:37.096906 00200000 ################################################################
10107 23:46:37.097042
10108 23:46:37.665792 00280000 ################################################################
10109 23:46:37.665933
10110 23:46:38.223868 00300000 ################################################################
10111 23:46:38.224051
10112 23:46:38.772768 00380000 ################################################################
10113 23:46:38.772918
10114 23:46:39.333120 00400000 ################################################################
10115 23:46:39.333296
10116 23:46:39.892268 00480000 ################################################################
10117 23:46:39.892401
10118 23:46:40.531378 00500000 ################################################################
10119 23:46:40.531894
10120 23:46:41.241946 00580000 ################################################################
10121 23:46:41.242455
10122 23:46:41.943584 00600000 ################################################################
10123 23:46:41.944239
10124 23:46:42.640454 00680000 ################################################################
10125 23:46:42.640949
10126 23:46:43.335531 00700000 ################################################################
10127 23:46:43.336029
10128 23:46:44.026854 00780000 ################################################################
10129 23:46:44.027375
10130 23:46:44.702571 00800000 ################################################################
10131 23:46:44.703118
10132 23:46:45.381949 00880000 ################################################################
10133 23:46:45.382087
10134 23:46:45.975643 00900000 ################################################################
10135 23:46:45.975783
10136 23:46:46.546567 00980000 ################################################################
10137 23:46:46.546717
10138 23:46:47.132762 00a00000 ################################################################
10139 23:46:47.132901
10140 23:46:47.704589 00a80000 ################################################################
10141 23:46:47.704734
10142 23:46:48.281532 00b00000 ################################################################
10143 23:46:48.281670
10144 23:46:48.863709 00b80000 ################################################################
10145 23:46:48.863857
10146 23:46:49.458361 00c00000 ################################################################
10147 23:46:49.458512
10148 23:46:50.033514 00c80000 ################################################################
10149 23:46:50.033664
10150 23:46:50.605210 00d00000 ################################################################
10151 23:46:50.605390
10152 23:46:51.162730 00d80000 ################################################################
10153 23:46:51.162882
10154 23:46:51.731781 00e00000 ################################################################
10155 23:46:51.731934
10156 23:46:52.271369 00e80000 ################################################################
10157 23:46:52.271518
10158 23:46:52.820384 00f00000 ################################################################
10159 23:46:52.820537
10160 23:46:53.371266 00f80000 ################################################################
10161 23:46:53.371401
10162 23:46:53.909366 01000000 ################################################################
10163 23:46:53.909498
10164 23:46:54.458354 01080000 ################################################################
10165 23:46:54.458491
10166 23:46:54.999333 01100000 ################################################################
10167 23:46:54.999469
10168 23:46:55.530676 01180000 ################################################################
10169 23:46:55.530811
10170 23:46:56.082529 01200000 ################################################################
10171 23:46:56.082665
10172 23:46:56.671060 01280000 ################################################################
10173 23:46:56.671209
10174 23:46:57.253496 01300000 ################################################################
10175 23:46:57.253643
10176 23:46:57.837201 01380000 ################################################################
10177 23:46:57.837398
10178 23:46:58.413180 01400000 ################################################################
10179 23:46:58.413361
10180 23:46:59.003853 01480000 ################################################################
10181 23:46:59.004015
10182 23:46:59.581021 01500000 ################################################################
10183 23:46:59.581178
10184 23:47:00.152009 01580000 ################################################################
10185 23:47:00.152168
10186 23:47:00.729981 01600000 ################################################################
10187 23:47:00.730138
10188 23:47:01.325761 01680000 ################################################################
10189 23:47:01.325920
10190 23:47:01.925801 01700000 ################################################################
10191 23:47:01.925955
10192 23:47:02.529893 01780000 ################################################################
10193 23:47:02.530053
10194 23:47:03.109420 01800000 ################################################################
10195 23:47:03.109578
10196 23:47:03.706391 01880000 ################################################################
10197 23:47:03.706542
10198 23:47:04.291479 01900000 ################################################################
10199 23:47:04.291630
10200 23:47:04.878132 01980000 ################################################################
10201 23:47:04.878280
10202 23:47:05.455303 01a00000 ################################################################
10203 23:47:05.455465
10204 23:47:06.037308 01a80000 ################################################################
10205 23:47:06.037456
10206 23:47:06.624677 01b00000 ################################################################
10207 23:47:06.624825
10208 23:47:07.204030 01b80000 ################################################################
10209 23:47:07.204183
10210 23:47:07.775008 01c00000 ################################################################
10211 23:47:07.775159
10212 23:47:08.342723 01c80000 ################################################################
10213 23:47:08.342866
10214 23:47:08.914369 01d00000 ################################################################
10215 23:47:08.914505
10216 23:47:09.503227 01d80000 ################################################################
10217 23:47:09.503408
10218 23:47:09.920054 01e00000 ############################################## done.
10219 23:47:09.920208
10220 23:47:09.923439 The bootfile was 31829238 bytes long.
10221 23:47:09.923534
10222 23:47:09.926463 Sending tftp read request... done.
10223 23:47:09.926551
10224 23:47:09.926616 Waiting for the transfer...
10225 23:47:09.926677
10226 23:47:09.929796 00000000 # done.
10227 23:47:09.929883
10228 23:47:09.936383 Command line loaded dynamically from TFTP file: 14172986/tftp-deploy-6o449hfs/kernel/cmdline
10229 23:47:09.936468
10230 23:47:09.960036 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172986/extract-nfsrootfs-gk86ljjv,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10231 23:47:09.960164
10232 23:47:09.960231 Loading FIT.
10233 23:47:09.960293
10234 23:47:09.962968 Image ramdisk-1 has 18718513 bytes.
10235 23:47:09.963050
10236 23:47:09.966011 Image fdt-1 has 47258 bytes.
10237 23:47:09.966093
10238 23:47:09.969818 Image kernel-1 has 13061430 bytes.
10239 23:47:09.969900
10240 23:47:09.979204 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10241 23:47:09.979316
10242 23:47:09.996036 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10243 23:47:09.996142
10244 23:47:10.002956 Choosing best match conf-1 for compat google,spherion-rev2.
10245 23:47:10.003068
10246 23:47:10.010266 Connected to device vid:did:rid of 1ae0:0028:00
10247 23:47:10.018390
10248 23:47:10.021503 tpm_get_response: command 0x17b, return code 0x0
10249 23:47:10.021586
10250 23:47:10.024649 ec_init: CrosEC protocol v3 supported (256, 248)
10251 23:47:10.030211
10252 23:47:10.033408 tpm_cleanup: add release locality here.
10253 23:47:10.033491
10254 23:47:10.033556 Shutting down all USB controllers.
10255 23:47:10.036952
10256 23:47:10.037033 Removing current net device
10257 23:47:10.037098
10258 23:47:10.043304 Exiting depthcharge with code 4 at timestamp: 81230331
10259 23:47:10.043502
10260 23:47:10.046422 LZMA decompressing kernel-1 to 0x821a6718
10261 23:47:10.046504
10262 23:47:10.049456 LZMA decompressing kernel-1 to 0x40000000
10263 23:47:11.659225
10264 23:47:11.659375 jumping to kernel
10265 23:47:11.659920 end: 2.2.4 bootloader-commands (duration 00:00:54) [common]
10266 23:47:11.660016 start: 2.2.5 auto-login-action (timeout 00:03:33) [common]
10267 23:47:11.660090 Setting prompt string to ['Linux version [0-9]']
10268 23:47:11.660158 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10269 23:47:11.660224 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10270 23:47:11.741827
10271 23:47:11.745424 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10272 23:47:11.748665 start: 2.2.5.1 login-action (timeout 00:03:33) [common]
10273 23:47:11.748764 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10274 23:47:11.748837 Setting prompt string to []
10275 23:47:11.748912 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10276 23:47:11.748990 Using line separator: #'\n'#
10277 23:47:11.749051 No login prompt set.
10278 23:47:11.749112 Parsing kernel messages
10279 23:47:11.749167 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10280 23:47:11.749312 [login-action] Waiting for messages, (timeout 00:03:33)
10281 23:47:11.749379 Waiting using forced prompt support (timeout 00:01:46)
10282 23:47:11.768318 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j217067-arm64-gcc-10-defconfig-arm64-chromebook-s48tj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024
10283 23:47:11.771691 [ 0.000000] random: crng init done
10284 23:47:11.778442 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10285 23:47:11.781758 [ 0.000000] efi: UEFI not found.
10286 23:47:11.788387 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10287 23:47:11.795356 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10288 23:47:11.804604 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10289 23:47:11.815010 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10290 23:47:11.821373 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10291 23:47:11.827926 [ 0.000000] printk: bootconsole [mtk8250] enabled
10292 23:47:11.834884 [ 0.000000] NUMA: No NUMA configuration found
10293 23:47:11.841162 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10294 23:47:11.844553 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd1a00-0x23efd3fff]
10295 23:47:11.847815 [ 0.000000] Zone ranges:
10296 23:47:11.854363 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10297 23:47:11.857890 [ 0.000000] DMA32 empty
10298 23:47:11.864665 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10299 23:47:11.868046 [ 0.000000] Movable zone start for each node
10300 23:47:11.871551 [ 0.000000] Early memory node ranges
10301 23:47:11.877994 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10302 23:47:11.884550 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10303 23:47:11.891647 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10304 23:47:11.898071 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10305 23:47:11.901041 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10306 23:47:11.908144 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10307 23:47:11.966223 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10308 23:47:11.973132 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10309 23:47:11.980085 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10310 23:47:11.982751 [ 0.000000] psci: probing for conduit method from DT.
10311 23:47:11.989514 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10312 23:47:11.992641 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10313 23:47:11.999355 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10314 23:47:12.002607 [ 0.000000] psci: SMC Calling Convention v1.2
10315 23:47:12.009654 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10316 23:47:12.012707 [ 0.000000] Detected VIPT I-cache on CPU0
10317 23:47:12.019282 [ 0.000000] CPU features: detected: GIC system register CPU interface
10318 23:47:12.026443 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10319 23:47:12.032807 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10320 23:47:12.038972 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10321 23:47:12.045928 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10322 23:47:12.055526 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10323 23:47:12.059403 [ 0.000000] alternatives: applying boot alternatives
10324 23:47:12.065633 [ 0.000000] Fallback order for Node 0: 0
10325 23:47:12.072346 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10326 23:47:12.075897 [ 0.000000] Policy zone: Normal
10327 23:47:12.098799 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172986/extract-nfsrootfs-gk86ljjv,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10328 23:47:12.108452 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10329 23:47:12.119772 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10330 23:47:12.129862 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10331 23:47:12.135866 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10332 23:47:12.139311 <6>[ 0.000000] software IO TLB: area num 8.
10333 23:47:12.196427 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10334 23:47:12.346491 <6>[ 0.000000] Memory: 7945908K/8385536K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 406860K reserved, 32768K cma-reserved)
10335 23:47:12.353168 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10336 23:47:12.359506 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10337 23:47:12.362585 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10338 23:47:12.369373 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10339 23:47:12.375780 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10340 23:47:12.379282 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10341 23:47:12.389498 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10342 23:47:12.396063 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10343 23:47:12.402386 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10344 23:47:12.409095 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10345 23:47:12.412451 <6>[ 0.000000] GICv3: 608 SPIs implemented
10346 23:47:12.415668 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10347 23:47:12.422430 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10348 23:47:12.425594 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10349 23:47:12.432136 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10350 23:47:12.445472 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10351 23:47:12.455565 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10352 23:47:12.465652 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10353 23:47:12.472447 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10354 23:47:12.485733 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10355 23:47:12.492552 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10356 23:47:12.498943 <6>[ 0.009184] Console: colour dummy device 80x25
10357 23:47:12.509081 <6>[ 0.013903] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10358 23:47:12.515869 <6>[ 0.024345] pid_max: default: 32768 minimum: 301
10359 23:47:12.518918 <6>[ 0.029217] LSM: Security Framework initializing
10360 23:47:12.526249 <6>[ 0.034155] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10361 23:47:12.535633 <6>[ 0.041968] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10362 23:47:12.545113 <6>[ 0.051393] cblist_init_generic: Setting adjustable number of callback queues.
10363 23:47:12.548600 <6>[ 0.058839] cblist_init_generic: Setting shift to 3 and lim to 1.
10364 23:47:12.558267 <6>[ 0.065178] cblist_init_generic: Setting adjustable number of callback queues.
10365 23:47:12.565369 <6>[ 0.072605] cblist_init_generic: Setting shift to 3 and lim to 1.
10366 23:47:12.568487 <6>[ 0.079005] rcu: Hierarchical SRCU implementation.
10367 23:47:12.575085 <6>[ 0.084021] rcu: Max phase no-delay instances is 1000.
10368 23:47:12.581892 <6>[ 0.091065] EFI services will not be available.
10369 23:47:12.584988 <6>[ 0.096024] smp: Bringing up secondary CPUs ...
10370 23:47:12.593611 <6>[ 0.101073] Detected VIPT I-cache on CPU1
10371 23:47:12.600274 <6>[ 0.101144] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10372 23:47:12.606700 <6>[ 0.101176] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10373 23:47:12.610288 <6>[ 0.101516] Detected VIPT I-cache on CPU2
10374 23:47:12.617166 <6>[ 0.101568] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10375 23:47:12.623684 <6>[ 0.101587] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10376 23:47:12.629840 <6>[ 0.101845] Detected VIPT I-cache on CPU3
10377 23:47:12.636469 <6>[ 0.101891] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10378 23:47:12.643161 <6>[ 0.101906] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10379 23:47:12.646572 <6>[ 0.102211] CPU features: detected: Spectre-v4
10380 23:47:12.653204 <6>[ 0.102218] CPU features: detected: Spectre-BHB
10381 23:47:12.656439 <6>[ 0.102223] Detected PIPT I-cache on CPU4
10382 23:47:12.662869 <6>[ 0.102282] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10383 23:47:12.669271 <6>[ 0.102298] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10384 23:47:12.676189 <6>[ 0.102588] Detected PIPT I-cache on CPU5
10385 23:47:12.683110 <6>[ 0.102651] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10386 23:47:12.689118 <6>[ 0.102667] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10387 23:47:12.692922 <6>[ 0.102950] Detected PIPT I-cache on CPU6
10388 23:47:12.699611 <6>[ 0.103014] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10389 23:47:12.705791 <6>[ 0.103030] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10390 23:47:12.712458 <6>[ 0.103329] Detected PIPT I-cache on CPU7
10391 23:47:12.719450 <6>[ 0.103393] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10392 23:47:12.725992 <6>[ 0.103409] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10393 23:47:12.729179 <6>[ 0.103456] smp: Brought up 1 node, 8 CPUs
10394 23:47:12.735936 <6>[ 0.244787] SMP: Total of 8 processors activated.
10395 23:47:12.738800 <6>[ 0.249707] CPU features: detected: 32-bit EL0 Support
10396 23:47:12.748728 <6>[ 0.255070] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10397 23:47:12.755748 <6>[ 0.263925] CPU features: detected: Common not Private translations
10398 23:47:12.762078 <6>[ 0.270441] CPU features: detected: CRC32 instructions
10399 23:47:12.765210 <6>[ 0.275792] CPU features: detected: RCpc load-acquire (LDAPR)
10400 23:47:12.772256 <6>[ 0.281752] CPU features: detected: LSE atomic instructions
10401 23:47:12.778966 <6>[ 0.287534] CPU features: detected: Privileged Access Never
10402 23:47:12.785466 <6>[ 0.293349] CPU features: detected: RAS Extension Support
10403 23:47:12.791644 <6>[ 0.298958] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10404 23:47:12.795078 <6>[ 0.306178] CPU: All CPU(s) started at EL2
10405 23:47:12.801917 <6>[ 0.310495] alternatives: applying system-wide alternatives
10406 23:47:12.811515 <6>[ 0.321333] devtmpfs: initialized
10407 23:47:12.826868 <6>[ 0.330274] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10408 23:47:12.833376 <6>[ 0.340231] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10409 23:47:12.840018 <6>[ 0.348249] pinctrl core: initialized pinctrl subsystem
10410 23:47:12.843421 <6>[ 0.354934] DMI not present or invalid.
10411 23:47:12.849714 <6>[ 0.359345] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10412 23:47:12.859930 <6>[ 0.366134] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10413 23:47:12.866527 <6>[ 0.373723] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10414 23:47:12.876544 <6>[ 0.381940] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10415 23:47:12.879566 <6>[ 0.390181] audit: initializing netlink subsys (disabled)
10416 23:47:12.889725 <5>[ 0.395870] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10417 23:47:12.896472 <6>[ 0.396592] thermal_sys: Registered thermal governor 'step_wise'
10418 23:47:12.903191 <6>[ 0.403836] thermal_sys: Registered thermal governor 'power_allocator'
10419 23:47:12.906459 <6>[ 0.410093] cpuidle: using governor menu
10420 23:47:12.909817 <6>[ 0.421048] NET: Registered PF_QIPCRTR protocol family
10421 23:47:12.919950 <6>[ 0.426536] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10422 23:47:12.923228 <6>[ 0.433640] ASID allocator initialised with 32768 entries
10423 23:47:12.930228 <6>[ 0.440226] Serial: AMBA PL011 UART driver
10424 23:47:12.939098 <4>[ 0.449106] Trying to register duplicate clock ID: 134
10425 23:47:12.998809 <6>[ 0.512243] KASLR enabled
10426 23:47:13.013353 <6>[ 0.519949] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10427 23:47:13.019680 <6>[ 0.526962] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10428 23:47:13.026217 <6>[ 0.533450] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10429 23:47:13.033166 <6>[ 0.540453] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10430 23:47:13.039583 <6>[ 0.546938] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10431 23:47:13.046399 <6>[ 0.553941] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10432 23:47:13.052658 <6>[ 0.560426] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10433 23:47:13.059739 <6>[ 0.567429] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10434 23:47:13.062472 <6>[ 0.574876] ACPI: Interpreter disabled.
10435 23:47:13.071231 <6>[ 0.581311] iommu: Default domain type: Translated
10436 23:47:13.077728 <6>[ 0.586464] iommu: DMA domain TLB invalidation policy: strict mode
10437 23:47:13.081537 <5>[ 0.593122] SCSI subsystem initialized
10438 23:47:13.087744 <6>[ 0.597371] usbcore: registered new interface driver usbfs
10439 23:47:13.094148 <6>[ 0.603103] usbcore: registered new interface driver hub
10440 23:47:13.097689 <6>[ 0.608652] usbcore: registered new device driver usb
10441 23:47:13.104481 <6>[ 0.614771] pps_core: LinuxPPS API ver. 1 registered
10442 23:47:13.114236 <6>[ 0.619965] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10443 23:47:13.117954 <6>[ 0.629307] PTP clock support registered
10444 23:47:13.120850 <6>[ 0.633549] EDAC MC: Ver: 3.0.0
10445 23:47:13.128912 <6>[ 0.638745] FPGA manager framework
10446 23:47:13.135023 <6>[ 0.642423] Advanced Linux Sound Architecture Driver Initialized.
10447 23:47:13.138344 <6>[ 0.649205] vgaarb: loaded
10448 23:47:13.145043 <6>[ 0.652366] clocksource: Switched to clocksource arch_sys_counter
10449 23:47:13.148223 <5>[ 0.658818] VFS: Disk quotas dquot_6.6.0
10450 23:47:13.154806 <6>[ 0.663003] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10451 23:47:13.158133 <6>[ 0.670196] pnp: PnP ACPI: disabled
10452 23:47:13.166993 <6>[ 0.676867] NET: Registered PF_INET protocol family
10453 23:47:13.176672 <6>[ 0.682460] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10454 23:47:13.188201 <6>[ 0.694765] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10455 23:47:13.197984 <6>[ 0.703579] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10456 23:47:13.204565 <6>[ 0.711549] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10457 23:47:13.214111 <6>[ 0.720246] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10458 23:47:13.220837 <6>[ 0.729994] TCP: Hash tables configured (established 65536 bind 65536)
10459 23:47:13.227623 <6>[ 0.736862] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10460 23:47:13.237692 <6>[ 0.744063] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10461 23:47:13.243863 <6>[ 0.751767] NET: Registered PF_UNIX/PF_LOCAL protocol family
10462 23:47:13.250539 <6>[ 0.757914] RPC: Registered named UNIX socket transport module.
10463 23:47:13.253885 <6>[ 0.764069] RPC: Registered udp transport module.
10464 23:47:13.260177 <6>[ 0.768999] RPC: Registered tcp transport module.
10465 23:47:13.267346 <6>[ 0.773932] RPC: Registered tcp NFSv4.1 backchannel transport module.
10466 23:47:13.270187 <6>[ 0.780599] PCI: CLS 0 bytes, default 64
10467 23:47:13.273569 <6>[ 0.784858] Unpacking initramfs...
10468 23:47:13.283365 <6>[ 0.789045] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10469 23:47:13.290027 <6>[ 0.797667] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10470 23:47:13.296746 <6>[ 0.806479] kvm [1]: IPA Size Limit: 40 bits
10471 23:47:13.300146 <6>[ 0.811008] kvm [1]: GICv3: no GICV resource entry
10472 23:47:13.306292 <6>[ 0.816028] kvm [1]: disabling GICv2 emulation
10473 23:47:13.312905 <6>[ 0.820713] kvm [1]: GIC system register CPU interface enabled
10474 23:47:13.316683 <6>[ 0.826879] kvm [1]: vgic interrupt IRQ18
10475 23:47:13.322996 <6>[ 0.832437] kvm [1]: VHE mode initialized successfully
10476 23:47:13.329744 <5>[ 0.838845] Initialise system trusted keyrings
10477 23:47:13.335892 <6>[ 0.843647] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10478 23:47:13.344039 <6>[ 0.853788] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10479 23:47:13.350541 <5>[ 0.860206] NFS: Registering the id_resolver key type
10480 23:47:13.353695 <5>[ 0.865517] Key type id_resolver registered
10481 23:47:13.360102 <5>[ 0.869930] Key type id_legacy registered
10482 23:47:13.367061 <6>[ 0.874209] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10483 23:47:13.373194 <6>[ 0.881130] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10484 23:47:13.380130 <6>[ 0.888850] 9p: Installing v9fs 9p2000 file system support
10485 23:47:13.416727 <5>[ 0.926875] Key type asymmetric registered
10486 23:47:13.419954 <5>[ 0.931203] Asymmetric key parser 'x509' registered
10487 23:47:13.429882 <6>[ 0.936344] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10488 23:47:13.433041 <6>[ 0.943964] io scheduler mq-deadline registered
10489 23:47:13.436768 <6>[ 0.948729] io scheduler kyber registered
10490 23:47:13.455601 <6>[ 0.965774] EINJ: ACPI disabled.
10491 23:47:13.489002 <4>[ 0.992052] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10492 23:47:13.498214 <4>[ 1.002650] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10493 23:47:13.513571 <6>[ 1.023592] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10494 23:47:13.521455 <6>[ 1.031589] printk: console [ttyS0] disabled
10495 23:47:13.549509 <6>[ 1.056212] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10496 23:47:13.556495 <6>[ 1.065694] printk: console [ttyS0] enabled
10497 23:47:13.559003 <6>[ 1.065694] printk: console [ttyS0] enabled
10498 23:47:13.566272 <6>[ 1.074605] printk: bootconsole [mtk8250] disabled
10499 23:47:13.569190 <6>[ 1.074605] printk: bootconsole [mtk8250] disabled
10500 23:47:13.575703 <6>[ 1.085675] SuperH (H)SCI(F) driver initialized
10501 23:47:13.579134 <6>[ 1.090938] msm_serial: driver initialized
10502 23:47:13.592912 <6>[ 1.099849] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10503 23:47:13.602818 <6>[ 1.108397] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10504 23:47:13.609482 <6>[ 1.116939] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10505 23:47:13.619307 <6>[ 1.125568] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10506 23:47:13.629436 <6>[ 1.134274] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10507 23:47:13.636032 <6>[ 1.142988] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10508 23:47:13.645676 <6>[ 1.151528] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10509 23:47:13.652545 <6>[ 1.160327] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10510 23:47:13.662450 <6>[ 1.168870] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10511 23:47:13.674142 <6>[ 1.184504] loop: module loaded
10512 23:47:13.680689 <6>[ 1.190451] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10513 23:47:13.703165 <4>[ 1.213652] mtk-pmic-keys: Failed to locate of_node [id: -1]
10514 23:47:13.710132 <6>[ 1.220410] megasas: 07.719.03.00-rc1
10515 23:47:13.720088 <6>[ 1.230106] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10516 23:47:13.729748 <6>[ 1.239745] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10517 23:47:13.746300 <6>[ 1.256111] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10518 23:47:13.801698 <6>[ 1.305328] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10519 23:47:14.065658 <6>[ 1.575501] Freeing initrd memory: 18276K
10520 23:47:14.076444 <6>[ 1.586899] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10521 23:47:14.087768 <6>[ 1.597862] tun: Universal TUN/TAP device driver, 1.6
10522 23:47:14.091087 <6>[ 1.603912] thunder_xcv, ver 1.0
10523 23:47:14.094284 <6>[ 1.607420] thunder_bgx, ver 1.0
10524 23:47:14.097795 <6>[ 1.610919] nicpf, ver 1.0
10525 23:47:14.108045 <6>[ 1.614939] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10526 23:47:14.111504 <6>[ 1.622414] hns3: Copyright (c) 2017 Huawei Corporation.
10527 23:47:14.115000 <6>[ 1.628007] hclge is initializing
10528 23:47:14.121414 <6>[ 1.631583] e1000: Intel(R) PRO/1000 Network Driver
10529 23:47:14.128187 <6>[ 1.636713] e1000: Copyright (c) 1999-2006 Intel Corporation.
10530 23:47:14.131302 <6>[ 1.642726] e1000e: Intel(R) PRO/1000 Network Driver
10531 23:47:14.138036 <6>[ 1.647941] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10532 23:47:14.144686 <6>[ 1.654127] igb: Intel(R) Gigabit Ethernet Network Driver
10533 23:47:14.150856 <6>[ 1.659777] igb: Copyright (c) 2007-2014 Intel Corporation.
10534 23:47:14.157913 <6>[ 1.665617] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10535 23:47:14.164313 <6>[ 1.672135] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10536 23:47:14.167811 <6>[ 1.678597] sky2: driver version 1.30
10537 23:47:14.173957 <6>[ 1.683532] usbcore: registered new device driver r8152-cfgselector
10538 23:47:14.180949 <6>[ 1.690068] usbcore: registered new interface driver r8152
10539 23:47:14.187348 <6>[ 1.695890] VFIO - User Level meta-driver version: 0.3
10540 23:47:14.193856 <6>[ 1.704104] usbcore: registered new interface driver usb-storage
10541 23:47:14.200491 <6>[ 1.710551] usbcore: registered new device driver onboard-usb-hub
10542 23:47:14.209607 <6>[ 1.719731] mt6397-rtc mt6359-rtc: registered as rtc0
10543 23:47:14.219362 <6>[ 1.725195] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T23:47:14 UTC (1717544834)
10544 23:47:14.222922 <6>[ 1.734764] i2c_dev: i2c /dev entries driver
10545 23:47:14.239820 <6>[ 1.746604] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10546 23:47:14.245994 <4>[ 1.755333] cpu cpu0: supply cpu not found, using dummy regulator
10547 23:47:14.253155 <4>[ 1.761759] cpu cpu1: supply cpu not found, using dummy regulator
10548 23:47:14.259169 <4>[ 1.768164] cpu cpu2: supply cpu not found, using dummy regulator
10549 23:47:14.266200 <4>[ 1.774570] cpu cpu3: supply cpu not found, using dummy regulator
10550 23:47:14.272276 <4>[ 1.780987] cpu cpu4: supply cpu not found, using dummy regulator
10551 23:47:14.278759 <4>[ 1.787382] cpu cpu5: supply cpu not found, using dummy regulator
10552 23:47:14.285691 <4>[ 1.793776] cpu cpu6: supply cpu not found, using dummy regulator
10553 23:47:14.292168 <4>[ 1.800175] cpu cpu7: supply cpu not found, using dummy regulator
10554 23:47:14.310630 <6>[ 1.820830] cpu cpu0: EM: created perf domain
10555 23:47:14.313841 <6>[ 1.825772] cpu cpu4: EM: created perf domain
10556 23:47:14.321146 <6>[ 1.831398] sdhci: Secure Digital Host Controller Interface driver
10557 23:47:14.328110 <6>[ 1.837828] sdhci: Copyright(c) Pierre Ossman
10558 23:47:14.334294 <6>[ 1.842798] Synopsys Designware Multimedia Card Interface Driver
10559 23:47:14.341097 <6>[ 1.849453] sdhci-pltfm: SDHCI platform and OF driver helper
10560 23:47:14.344386 <6>[ 1.849664] mmc0: CQHCI version 5.10
10561 23:47:14.351463 <6>[ 1.859433] ledtrig-cpu: registered to indicate activity on CPUs
10562 23:47:14.357762 <6>[ 1.866428] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10563 23:47:14.364125 <6>[ 1.873475] usbcore: registered new interface driver usbhid
10564 23:47:14.368109 <6>[ 1.879297] usbhid: USB HID core driver
10565 23:47:14.374117 <6>[ 1.883490] spi_master spi0: will run message pump with realtime priority
10566 23:47:14.418860 <6>[ 1.922512] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10567 23:47:14.437162 <6>[ 1.937331] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10568 23:47:14.440373 <6>[ 1.945485] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x17414
10569 23:47:14.448456 <6>[ 1.958367] cros-ec-spi spi0.0: Chrome EC device registered
10570 23:47:14.455245 <6>[ 1.964391] mmc0: Command Queue Engine enabled
10571 23:47:14.461494 <6>[ 1.969109] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10572 23:47:14.464701 <6>[ 1.976607] mmcblk0: mmc0:0001 DA4128 116 GiB
10573 23:47:14.474594 <6>[ 1.984985] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10574 23:47:14.482205 <6>[ 1.992289] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10575 23:47:14.488356 <6>[ 1.998243] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10576 23:47:14.495683 <6>[ 2.004162] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10577 23:47:14.505082 <6>[ 2.004392] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10578 23:47:14.511764 <6>[ 2.021310] NET: Registered PF_PACKET protocol family
10579 23:47:14.515205 <6>[ 2.026763] 9pnet: Installing 9P2000 support
10580 23:47:14.521418 <5>[ 2.031332] Key type dns_resolver registered
10581 23:47:14.524733 <6>[ 2.036303] registered taskstats version 1
10582 23:47:14.532072 <5>[ 2.040689] Loading compiled-in X.509 certificates
10583 23:47:14.559582 <4>[ 2.063364] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10584 23:47:14.569845 <4>[ 2.074184] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 23:47:14.584977 <6>[ 2.095320] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10586 23:47:14.592180 <6>[ 2.102233] xhci-mtk 11200000.usb: xHCI Host Controller
10587 23:47:14.598759 <6>[ 2.107751] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10588 23:47:14.608847 <6>[ 2.115652] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10589 23:47:14.615592 <6>[ 2.125086] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10590 23:47:14.622014 <6>[ 2.131191] xhci-mtk 11200000.usb: xHCI Host Controller
10591 23:47:14.628674 <6>[ 2.136679] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10592 23:47:14.635303 <6>[ 2.144435] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10593 23:47:14.641797 <6>[ 2.152296] hub 1-0:1.0: USB hub found
10594 23:47:14.645333 <6>[ 2.156336] hub 1-0:1.0: 1 port detected
10595 23:47:14.655434 <6>[ 2.160653] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10596 23:47:14.658878 <6>[ 2.169406] hub 2-0:1.0: USB hub found
10597 23:47:14.661633 <6>[ 2.173449] hub 2-0:1.0: 1 port detected
10598 23:47:14.669717 <6>[ 2.180156] mtk-msdc 11f70000.mmc: Got CD GPIO
10599 23:47:14.683587 <6>[ 2.190715] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10600 23:47:14.690680 <6>[ 2.198743] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10601 23:47:14.700165 <4>[ 2.206681] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10602 23:47:14.710172 <6>[ 2.216249] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10603 23:47:14.717569 <6>[ 2.224327] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10604 23:47:14.723322 <6>[ 2.232368] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10605 23:47:14.733668 <6>[ 2.240281] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10606 23:47:14.740164 <6>[ 2.248098] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10607 23:47:14.749788 <6>[ 2.255916] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10608 23:47:14.759553 <6>[ 2.266330] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10609 23:47:14.766718 <6>[ 2.274688] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10610 23:47:14.776377 <6>[ 2.283043] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10611 23:47:14.783108 <6>[ 2.291381] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10612 23:47:14.792857 <6>[ 2.299718] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10613 23:47:14.799506 <6>[ 2.308056] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10614 23:47:14.809439 <6>[ 2.316393] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10615 23:47:14.819490 <6>[ 2.324731] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10616 23:47:14.826022 <6>[ 2.333069] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10617 23:47:14.835881 <6>[ 2.341407] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10618 23:47:14.842326 <6>[ 2.349745] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10619 23:47:14.852376 <6>[ 2.358082] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10620 23:47:14.859206 <6>[ 2.366419] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10621 23:47:14.869048 <6>[ 2.374756] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10622 23:47:14.875415 <6>[ 2.383094] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10623 23:47:14.881876 <6>[ 2.391822] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10624 23:47:14.888665 <6>[ 2.398970] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10625 23:47:14.895703 <6>[ 2.405737] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10626 23:47:14.905420 <6>[ 2.412541] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10627 23:47:14.912538 <6>[ 2.419510] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10628 23:47:14.919294 <6>[ 2.426363] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10629 23:47:14.928821 <6>[ 2.435511] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10630 23:47:14.939006 <6>[ 2.444630] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10631 23:47:14.948933 <6>[ 2.453924] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10632 23:47:14.958481 <6>[ 2.463394] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10633 23:47:14.964828 <6>[ 2.472863] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10634 23:47:14.975100 <6>[ 2.481982] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10635 23:47:14.985101 <6>[ 2.491448] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10636 23:47:14.995360 <6>[ 2.500567] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10637 23:47:15.004725 <6>[ 2.509862] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10638 23:47:15.014802 <6>[ 2.520023] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10639 23:47:15.025137 <6>[ 2.531920] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10640 23:47:15.031279 <6>[ 2.541477] Trying to probe devices needed for running init ...
10641 23:47:15.077344 <6>[ 2.584485] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10642 23:47:15.230949 <6>[ 2.740701] hub 1-1:1.0: USB hub found
10643 23:47:15.233703 <6>[ 2.745107] hub 1-1:1.0: 4 ports detected
10644 23:47:15.242304 <6>[ 2.752202] hub 1-1:1.0: USB hub found
10645 23:47:15.245597 <6>[ 2.756586] hub 1-1:1.0: 4 ports detected
10646 23:47:15.358593 <6>[ 2.865059] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10647 23:47:15.385861 <6>[ 2.895885] hub 2-1:1.0: USB hub found
10648 23:47:15.389611 <6>[ 2.900455] hub 2-1:1.0: 3 ports detected
10649 23:47:15.399742 <6>[ 2.909134] hub 2-1:1.0: USB hub found
10650 23:47:15.402774 <6>[ 2.913587] hub 2-1:1.0: 3 ports detected
10651 23:47:15.565763 <6>[ 3.072686] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10652 23:47:15.697590 <6>[ 3.208079] hub 1-1.4:1.0: USB hub found
10653 23:47:15.701023 <6>[ 3.212714] hub 1-1.4:1.0: 2 ports detected
10654 23:47:15.708908 <6>[ 3.219551] hub 1-1.4:1.0: USB hub found
10655 23:47:15.712391 <6>[ 3.224119] hub 1-1.4:1.0: 2 ports detected
10656 23:47:15.777518 <6>[ 3.284748] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10657 23:47:15.885655 <6>[ 3.393062] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10658 23:47:15.918257 <4>[ 3.425542] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10659 23:47:15.928036 <4>[ 3.434715] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10660 23:47:15.963185 <6>[ 3.473602] r8152 2-1.3:1.0 eth0: v1.12.13
10661 23:47:16.013993 <6>[ 3.520687] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10662 23:47:16.205570 <6>[ 3.712697] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10663 23:47:17.571740 <6>[ 5.082478] r8152 2-1.3:1.0 eth0: carrier on
10664 23:47:20.453712 <5>[ 5.112492] Sending DHCP requests .., OK
10665 23:47:20.460057 <6>[ 7.968829] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.14
10666 23:47:20.463618 <6>[ 7.977123] IP-Config: Complete:
10667 23:47:20.476697 <6>[ 7.980622] device=eth0, hwaddr=00:24:32:30:7c:7b, ipaddr=192.168.201.14, mask=255.255.255.0, gw=192.168.201.1
10668 23:47:20.483337 <6>[ 7.991341] host=mt8192-asurada-spherion-r0-cbg-2, domain=lava-rack, nis-domain=(none)
10669 23:47:20.490045 <6>[ 7.999960] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10670 23:47:20.496498 <6>[ 7.999969] nameserver0=192.168.201.1
10671 23:47:20.499849 <6>[ 8.012138] clk: Disabling unused clocks
10672 23:47:20.503407 <6>[ 8.017621] ALSA device list:
10673 23:47:20.509804 <6>[ 8.020877] No soundcards found.
10674 23:47:20.517478 <6>[ 8.028498] Freeing unused kernel memory: 8512K
10675 23:47:20.521160 <6>[ 8.033472] Run /init as init process
10676 23:47:20.531025 Loading, please wait...
10677 23:47:20.557561 Starting systemd-udevd version 252.22-1~deb12u1
10678 23:47:20.814623 <6>[ 8.321996] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10679 23:47:20.824074 <6>[ 8.331046] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10680 23:47:20.827668 <6>[ 8.339525] remoteproc remoteproc0: scp is available
10681 23:47:20.833914 <6>[ 8.345095] remoteproc remoteproc0: powering up scp
10682 23:47:20.843879 <6>[ 8.350342] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10683 23:47:20.850959 <6>[ 8.354876] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10684 23:47:20.857138 <6>[ 8.359851] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10685 23:47:20.867236 <6>[ 8.367587] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10686 23:47:20.877480 <6>[ 8.388260] mc: Linux media interface: v0.10
10687 23:47:20.887748 <3>[ 8.395214] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 23:47:20.894134 <4>[ 8.396986] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10689 23:47:20.904100 <3>[ 8.403546] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 23:47:20.911196 <3>[ 8.419126] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 23:47:20.917439 <4>[ 8.423114] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10692 23:47:20.927023 <3>[ 8.430634] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 23:47:20.933979 <3>[ 8.442859] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 23:47:20.940292 <6>[ 8.443760] videodev: Linux video capture interface: v2.00
10695 23:47:20.947033 <6>[ 8.444146] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10696 23:47:20.957070 <3>[ 8.450964] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 23:47:20.963621 <3>[ 8.450976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10698 23:47:20.973212 <3>[ 8.450982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 23:47:20.981090 <3>[ 8.451081] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10700 23:47:20.990430 <4>[ 8.466632] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10701 23:47:20.993696 <4>[ 8.466632] Fallback method does not support PEC.
10702 23:47:21.004060 <3>[ 8.472536] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10703 23:47:21.010469 <3>[ 8.497164] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10704 23:47:21.016793 <6>[ 8.498586] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10705 23:47:21.023983 <6>[ 8.501784] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10706 23:47:21.030883 <6>[ 8.501794] pci_bus 0000:00: root bus resource [bus 00-ff]
10707 23:47:21.037508 <6>[ 8.501801] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10708 23:47:21.046942 <6>[ 8.501806] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10709 23:47:21.053949 <6>[ 8.501841] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10710 23:47:21.060493 <6>[ 8.501861] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10711 23:47:21.067541 <6>[ 8.502025] pci 0000:00:00.0: supports D1 D2
10712 23:47:21.073576 <6>[ 8.502032] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10713 23:47:21.080349 <6>[ 8.504338] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10714 23:47:21.086779 <6>[ 8.504514] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10715 23:47:21.096592 <6>[ 8.504550] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10716 23:47:21.103635 <6>[ 8.504574] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10717 23:47:21.110154 <6>[ 8.504595] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10718 23:47:21.113683 <6>[ 8.504729] pci 0000:01:00.0: supports D1 D2
10719 23:47:21.119962 <6>[ 8.504733] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10720 23:47:21.129736 <6>[ 8.510394] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10721 23:47:21.139535 <3>[ 8.510891] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10722 23:47:21.146261 <3>[ 8.510902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10723 23:47:21.153073 <3>[ 8.510960] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10724 23:47:21.162953 <3>[ 8.510968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 23:47:21.169494 <3>[ 8.510976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10726 23:47:21.179621 <3>[ 8.510983] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 23:47:21.186297 <3>[ 8.510990] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10728 23:47:21.195874 <3>[ 8.511025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10729 23:47:21.202659 <6>[ 8.511905] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10730 23:47:21.212202 <6>[ 8.514144] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10731 23:47:21.218871 <6>[ 8.516440] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10732 23:47:21.225733 <6>[ 8.516473] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10733 23:47:21.235667 <6>[ 8.516478] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10734 23:47:21.242188 <6>[ 8.516487] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10735 23:47:21.248885 <6>[ 8.516500] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10736 23:47:21.259061 <6>[ 8.516514] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10737 23:47:21.261757 <6>[ 8.516526] pci 0000:00:00.0: PCI bridge to [bus 01]
10738 23:47:21.271785 <6>[ 8.516531] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10739 23:47:21.278322 <6>[ 8.516655] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10740 23:47:21.285021 <6>[ 8.517154] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10741 23:47:21.288124 <6>[ 8.517594] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10742 23:47:21.298310 <3>[ 8.542603] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10743 23:47:21.305161 <6>[ 8.546866] remoteproc remoteproc0: remote processor scp is now up
10744 23:47:21.315162 <6>[ 8.551024] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10745 23:47:21.325128 <6>[ 8.678519] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10746 23:47:21.335071 <6>[ 8.841440] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10747 23:47:21.361591 <6>[ 8.869029] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10748 23:47:21.378705 <6>[ 8.889835] Bluetooth: Core ver 2.22
10749 23:47:21.385174 <6>[ 8.894271] NET: Registered PF_BLUETOOTH protocol family
10750 23:47:21.395287 <6>[ 8.900263] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10751 23:47:21.402030 <6>[ 8.900565] Bluetooth: HCI device and connection manager initialized
10752 23:47:21.409241 <6>[ 8.920167] Bluetooth: HCI socket layer initialized
10753 23:47:21.415830 <6>[ 8.920635] usbcore: registered new interface driver uvcvideo
10754 23:47:21.422355 <6>[ 8.920783] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10755 23:47:21.425588 <6>[ 8.925389] Bluetooth: L2CAP socket layer initialized
10756 23:47:21.435855 <5>[ 8.933769] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10757 23:47:21.438864 <6>[ 8.937905] Bluetooth: SCO socket layer initialized
10758 23:47:21.450760 <5>[ 8.958526] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10759 23:47:21.457365 <5>[ 8.965898] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10760 23:47:21.467190 <4>[ 8.974419] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10761 23:47:21.474015 <6>[ 8.983312] cfg80211: failed to load regulatory.db
10762 23:47:21.480970 <6>[ 8.989263] usbcore: registered new interface driver btusb
10763 23:47:21.490310 <4>[ 8.990356] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10764 23:47:21.497050 <3>[ 9.005564] Bluetooth: hci0: Failed to load firmware file (-2)
10765 23:47:21.500587 <3>[ 9.011651] Bluetooth: hci0: Failed to set up firmware (-2)
10766 23:47:21.513877 <4>[ 9.017514] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10767 23:47:21.555088 <6>[ 9.062818] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10768 23:47:21.561761 <6>[ 9.070356] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10769 23:47:21.586222 <6>[ 9.097181] mt7921e 0000:01:00.0: ASIC revision: 79610010
10770 23:47:21.688383 <6>[ 9.196268] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10771 23:47:21.691869 <6>[ 9.196268]
10772 23:47:21.694954 Begin: Loading essential drivers ... done.
10773 23:47:21.698602 Begin: Running /scripts/init-premount ... done.
10774 23:47:21.705030 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10775 23:47:21.714940 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10776 23:47:21.718002 Device /sys/class/net/eth0 found
10777 23:47:21.718097 done.
10778 23:47:21.725472 Begin: Waiting up to 180 secs for any network device to become available ... done.
10779 23:47:21.773830 IP-Config: eth0 hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10780 23:47:21.781164 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10781 23:47:21.788086 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10782 23:47:21.794365 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10783 23:47:21.801551 host : mt8192-asurada-spherion-r0-cbg-2
10784 23:47:21.807475 domain : lava-rack
10785 23:47:21.811321 rootserver: 192.168.201.1 rootpath:
10786 23:47:21.814067 filename :
10787 23:47:21.915572 done.
10788 23:47:21.922768 Begin: Running /scripts/nfs-bottom ... done.
10789 23:47:21.936289 Begin: Running /scripts/init-bottom ... done.
10790 23:47:21.958585 <6>[ 9.465999] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10791 23:47:23.315486 <6>[ 10.826871] NET: Registered PF_INET6 protocol family
10792 23:47:23.322642 <6>[ 10.833904] Segment Routing with IPv6
10793 23:47:23.325874 <6>[ 10.837905] In-situ OAM (IOAM) with IPv6
10794 23:47:23.502756 <30>[ 10.987720] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10795 23:47:23.509597 <30>[ 11.020838] systemd[1]: Detected architecture arm64.
10796 23:47:23.519042
10797 23:47:23.522580 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10798 23:47:23.522662
10799 23:47:23.547368 <30>[ 11.058785] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10800 23:47:24.640175 <30>[ 12.148308] systemd[1]: Queued start job for default target graphical.target.
10801 23:47:24.689124 <30>[ 12.197299] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10802 23:47:24.695955 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10803 23:47:24.718662 <30>[ 12.226489] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10804 23:47:24.728039 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10805 23:47:24.746571 <30>[ 12.254470] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10806 23:47:24.756242 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10807 23:47:24.774982 <30>[ 12.282866] systemd[1]: Created slice user.slice - User and Session Slice.
10808 23:47:24.781471 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10809 23:47:24.804850 <30>[ 12.309579] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10810 23:47:24.814695 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10811 23:47:24.835950 <30>[ 12.340974] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10812 23:47:24.842905 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10813 23:47:24.871181 <30>[ 12.368848] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10814 23:47:24.880581 <30>[ 12.388674] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10815 23:47:24.887040 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10816 23:47:24.904955 <30>[ 12.412972] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10817 23:47:24.914542 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10818 23:47:24.933254 <30>[ 12.441214] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10819 23:47:24.942911 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10820 23:47:24.957735 <30>[ 12.469242] systemd[1]: Reached target paths.target - Path Units.
10821 23:47:24.964498 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10822 23:47:24.985140 <30>[ 12.493114] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10823 23:47:24.991512 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10824 23:47:25.005038 <30>[ 12.516661] systemd[1]: Reached target slices.target - Slice Units.
10825 23:47:25.015249 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10826 23:47:25.029485 <30>[ 12.541064] systemd[1]: Reached target swap.target - Swaps.
10827 23:47:25.036398 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10828 23:47:25.057416 <30>[ 12.565213] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10829 23:47:25.066897 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10830 23:47:25.085858 <30>[ 12.593643] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10831 23:47:25.095346 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10832 23:47:25.115604 <30>[ 12.623659] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10833 23:47:25.125553 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10834 23:47:25.142051 <30>[ 12.650245] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10835 23:47:25.151855 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10836 23:47:25.169271 <30>[ 12.677362] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10837 23:47:25.175575 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10838 23:47:25.194342 <30>[ 12.702273] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10839 23:47:25.203837 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10840 23:47:25.223971 <30>[ 12.731904] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10841 23:47:25.233888 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10842 23:47:25.248978 <30>[ 12.757146] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10843 23:47:25.258670 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10844 23:47:25.308730 <30>[ 12.817124] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10845 23:47:25.315291 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10846 23:47:25.335068 <30>[ 12.843073] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10847 23:47:25.341444 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10848 23:47:25.364043 <30>[ 12.872498] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10849 23:47:25.370865 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10850 23:47:25.395365 <30>[ 12.897157] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10851 23:47:25.410860 <30>[ 12.919162] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10852 23:47:25.421205 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10853 23:47:25.446198 <30>[ 12.954226] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10854 23:47:25.455644 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10855 23:47:25.478056 <30>[ 12.986300] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10856 23:47:25.484588 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10857 23:47:25.510260 <30>[ 13.018285] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10858 23:47:25.523561 Starting [0;1;39mmodprobe@drm.service[0m - Load Kerne<6>[ 13.031264] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10859 23:47:25.526656 l Module drm...
10860 23:47:25.550056 <30>[ 13.058300] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10861 23:47:25.559929 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10862 23:47:25.582220 <30>[ 13.090036] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10863 23:47:25.588680 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10864 23:47:25.614321 <30>[ 13.122340] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10865 23:47:25.624253 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kern<6>[ 13.135703] fuse: init (API version 7.37)
10866 23:47:25.627533 el Module loop...
10867 23:47:25.654213 <30>[ 13.162476] systemd[1]: Starting systemd-journald.service - Journal Service...
10868 23:47:25.661149 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10869 23:47:25.693533 <30>[ 13.201996] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10870 23:47:25.700040 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10871 23:47:25.731896 <30>[ 13.236246] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10872 23:47:25.738065 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10873 23:47:25.761985 <30>[ 13.270457] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10874 23:47:25.771890 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10875 23:47:25.793405 <30>[ 13.301340] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10876 23:47:25.800224 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10877 23:47:25.813871 <3>[ 13.322221] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 23:47:25.828093 <30>[ 13.336521] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10879 23:47:25.835101 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10880 23:47:25.852776 <30>[ 13.360967] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10881 23:47:25.863095 <3>[ 13.364521] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 23:47:25.869940 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10883 23:47:25.889288 <30>[ 13.397014] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10884 23:47:25.899249 [[0;32m OK [<3>[ 13.405361] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 23:47:25.905846 0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10886 23:47:25.925118 <30>[ 13.433139] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10887 23:47:25.935674 <3>[ 13.437979] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10888 23:47:25.942590 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10889 23:47:25.961795 <30>[ 13.469568] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10890 23:47:25.968611 <3>[ 13.470992] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 23:47:25.978413 <30>[ 13.477366] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10892 23:47:25.985421 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10893 23:47:25.999635 <3>[ 13.508084] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 23:47:26.010078 <30>[ 13.518068] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10895 23:47:26.016464 <30>[ 13.525835] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10896 23:47:26.033401 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m <3>[ 13.539441] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 23:47:26.033492 - Load Kernel Module dm_mod.
10898 23:47:26.054002 <30>[ 13.561616] systemd[1]: modprobe@drm.service: Deactivated successfully.
10899 23:47:26.060261 <30>[ 13.569088] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10900 23:47:26.070123 <3>[ 13.569896] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10901 23:47:26.076519 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10902 23:47:26.099126 <30>[ 13.606550] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10903 23:47:26.106254 <3>[ 13.613352] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10904 23:47:26.115226 <30>[ 13.614624] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10905 23:47:26.125212 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10906 23:47:26.140390 <3>[ 13.648630] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 23:47:26.146875 <30>[ 13.650315] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10908 23:47:26.157758 <30>[ 13.665404] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10909 23:47:26.164583 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10910 23:47:26.174082 <3>[ 13.681158] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 23:47:26.185692 <30>[ 13.693646] systemd[1]: modprobe@loop.service: Deactivated successfully.
10912 23:47:26.193110 <30>[ 13.701390] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10913 23:47:26.203344 <3>[ 13.709123] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 23:47:26.216524 <4>[ 13.718011] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10915 23:47:26.226536 <3>[ 13.718015] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10916 23:47:26.233116 <3>[ 13.726815] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10917 23:47:26.243311 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10918 23:47:26.261757 <30>[ 13.769866] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10919 23:47:26.271987 <3>[ 13.773753] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10920 23:47:26.278288 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10921 23:47:26.300850 <30>[ 13.805137] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10922 23:47:26.307413 <3>[ 13.810729] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 23:47:26.317998 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10924 23:47:26.334120 <30>[ 13.841902] systemd[1]: Finished systemd-remount-fs.service - Remount Root and Kernel File Systems.
10925 23:47:26.344008 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10926 23:47:26.361154 <30>[ 13.869143] systemd[1]: Finished systemd-udev-trigger.service - Coldplug All udev Devices.
10927 23:47:26.371066 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10928 23:47:26.389279 <30>[ 13.897289] systemd[1]: Reached target network-pre.target - Preparation for Network.
10929 23:47:26.395594 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10930 23:47:26.444953 <30>[ 13.953134] systemd[1]: Mounting sys-fs-fuse-connections.mount - FUSE Control File System...
10931 23:47:26.451759 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10932 23:47:26.477333 <30>[ 13.985888] systemd[1]: Mounting sys-kernel-config.mount - Kernel Configuration File System...
10933 23:47:26.487341 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10934 23:47:26.508133 <30>[ 14.012844] systemd[1]: systemd-firstboot.service - First Boot Wizard was skipped because of an unmet condition check (ConditionFirstBoot=yes).
10935 23:47:26.525041 <30>[ 14.026477] systemd[1]: systemd-pstore.service - Platform Persistent Storage Archival was skipped because of an unmet condition check (ConditionDirectoryNotEmpty=/sys/fs/pstore).
10936 23:47:26.539362 <30>[ 14.047511] systemd[1]: Starting systemd-random-seed.service - Load/Save Random Seed...
10937 23:47:26.545874 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10938 23:47:26.570653 <30>[ 14.075219] systemd[1]: systemd-repart.service - Repartition Root Disk was skipped because no trigger condition checks were met.
10939 23:47:26.608974 <30>[ 14.117458] systemd[1]: Starting systemd-sysctl.service - Apply Kernel Variables...
10940 23:47:26.615500 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10941 23:47:26.640479 <30>[ 14.148733] systemd[1]: Starting systemd-sysusers.service - Create System Users...
10942 23:47:26.646997 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10943 23:47:26.670991 <30>[ 14.179072] systemd[1]: Started systemd-journald.service - Journal Service.
10944 23:47:26.677505 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10945 23:47:26.702103 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10946 23:47:26.720561 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10947 23:47:26.737613 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10948 23:47:26.757928 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10949 23:47:26.777913 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10950 23:47:26.833184 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10951 23:47:26.857584 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10952 23:47:26.921234 <46>[ 14.429577] systemd-journald[308]: Received client request to flush runtime journal.
10953 23:47:26.962691 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10954 23:47:26.984593 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10955 23:47:27.004475 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10956 23:47:27.709847 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10957 23:47:28.332834 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10958 23:47:28.365100 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10959 23:47:28.440239 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10960 23:47:28.507384 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10961 23:47:28.587251 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10962 23:47:28.916638 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slic<6>[ 16.426255] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10963 23:47:28.919719 e /system/systemd-backlight.
10964 23:47:28.970363 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10965 23:47:29.077396 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10966 23:47:29.096621 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10967 23:47:29.113132 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10968 23:47:29.134870 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10969 23:47:29.163979 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10970 23:47:29.213248 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10971 23:47:29.258855 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10972 23:47:29.309270 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10973 23:47:29.334848 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10974 23:47:29.358262 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10975 23:47:29.398283 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10976 23:47:29.469566 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10977 23:47:29.488985 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10978 23:47:29.508814 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10979 23:47:29.528563 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10980 23:47:29.557046 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10981 23:47:29.579649 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10982 23:47:29.596655 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10983 23:47:29.620209 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10984 23:47:29.640339 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10985 23:47:29.656489 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10986 23:47:29.675031 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10987 23:47:29.692722 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10988 23:47:29.709398 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10989 23:47:29.768217 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10990 23:47:29.872957 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10991 23:47:29.958823 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10992 23:47:29.986339 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10993 23:47:30.126419 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10994 23:47:30.173487 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10995 23:47:30.195068 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10996 23:47:30.214143 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10997 23:47:30.232479 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10998 23:47:30.253777 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10999 23:47:30.279624 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11000 23:47:30.299987 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11001 23:47:30.319704 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11002 23:47:30.383073 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11003 23:47:30.427085 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11004 23:47:30.537112
11005 23:47:30.540537 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11006 23:47:30.540679
11007 23:47:30.543814 debian-bookworm-arm64 login: root (automatic login)
11008 23:47:30.543932
11009 23:47:30.835076 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024 aarch64
11010 23:47:30.835327
11011 23:47:30.841922 The programs included with the Debian GNU/Linux system are free software;
11012 23:47:30.848305 the exact distribution terms for each program are described in the
11013 23:47:30.851292 individual files in /usr/share/doc/*/copyright.
11014 23:47:30.851410
11015 23:47:30.858256 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11016 23:47:30.861194 permitted by applicable law.
11017 23:47:31.881438 Matched prompt #10: / #
11019 23:47:31.881727 Setting prompt string to ['/ #']
11020 23:47:31.881823 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11022 23:47:31.882029 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
11023 23:47:31.882121 start: 2.2.6 expect-shell-connection (timeout 00:03:13) [common]
11024 23:47:31.882194 Setting prompt string to ['/ #']
11025 23:47:31.882255 Forcing a shell prompt, looking for ['/ #']
11027 23:47:31.932458 / #
11028 23:47:31.932663 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11029 23:47:31.932746 Waiting using forced prompt support (timeout 00:02:30)
11030 23:47:31.937642
11031 23:47:31.937935 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11032 23:47:31.938036 start: 2.2.7 export-device-env (timeout 00:03:13) [common]
11034 23:47:32.038373 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172986/extract-nfsrootfs-gk86ljjv'
11035 23:47:32.043343 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172986/extract-nfsrootfs-gk86ljjv'
11037 23:47:32.143932 / # export NFS_SERVER_IP='192.168.201.1'
11038 23:47:32.149184 export NFS_SERVER_IP='192.168.201.1'
11039 23:47:32.149553 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11040 23:47:32.149662 end: 2.2 depthcharge-retry (duration 00:01:47) [common]
11041 23:47:32.149757 end: 2 depthcharge-action (duration 00:01:47) [common]
11042 23:47:32.149850 start: 3 lava-test-retry (timeout 00:07:33) [common]
11043 23:47:32.149941 start: 3.1 lava-test-shell (timeout 00:07:33) [common]
11044 23:47:32.150019 Using namespace: common
11046 23:47:32.250355 / # #
11047 23:47:32.250553 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11048 23:47:32.255297 #
11049 23:47:32.255598 Using /lava-14172986
11051 23:47:32.355965 / # export SHELL=/bin/bash
11052 23:47:32.360904 export SHELL=/bin/bash
11054 23:47:32.461496 / # . /lava-14172986/environment
11055 23:47:32.466454 . /lava-14172986/environment
11057 23:47:32.573566 / # /lava-14172986/bin/lava-test-runner /lava-14172986/0
11058 23:47:32.573764 Test shell timeout: 10s (minimum of the action and connection timeout)
11059 23:47:32.578798 /lava-14172986/bin/lava-test-runner /lava-14172986/0
11060 23:47:32.872011 + export TESTRUN_ID=0_timesync-off
11061 23:47:32.875252 + TESTRUN_ID=0_timesync-off
11062 23:47:32.878734 + cd /lava-14172986/0/tests/0_timesync-off
11063 23:47:32.881822 ++ cat uuid
11064 23:47:32.888563 + UUID=14172986_1.6.2.3.1
11065 23:47:32.888677 + set +x
11066 23:47:32.894931 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14172986_1.6.2.3.1>
11067 23:47:32.895219 Received signal: <STARTRUN> 0_timesync-off 14172986_1.6.2.3.1
11068 23:47:32.895303 Starting test lava.0_timesync-off (14172986_1.6.2.3.1)
11069 23:47:32.895392 Skipping test definition patterns.
11070 23:47:32.898062 + systemctl stop systemd-timesyncd
11071 23:47:32.960799 + set +x
11072 23:47:32.963782 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14172986_1.6.2.3.1>
11073 23:47:32.964056 Received signal: <ENDRUN> 0_timesync-off 14172986_1.6.2.3.1
11074 23:47:32.964144 Ending use of test pattern.
11075 23:47:32.964208 Ending test lava.0_timesync-off (14172986_1.6.2.3.1), duration 0.07
11077 23:47:33.045461 + export TESTRUN_ID=1_kselftest-rtc
11078 23:47:33.048272 + TESTRUN_ID=1_kselftest-rtc
11079 23:47:33.051951 + cd /lava-14172986/0/tests/1_kselftest-rtc
11080 23:47:33.055742 ++ cat uuid
11081 23:47:33.060425 + UUID=14172986_1.6.2.3.5
11082 23:47:33.060563 + set +x
11083 23:47:33.067755 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 14172986_1.6.2.3.5>
11084 23:47:33.068052 Received signal: <STARTRUN> 1_kselftest-rtc 14172986_1.6.2.3.5
11085 23:47:33.068128 Starting test lava.1_kselftest-rtc (14172986_1.6.2.3.5)
11086 23:47:33.068212 Skipping test definition patterns.
11087 23:47:33.070337 + cd ./automated/linux/kselftest/
11088 23:47:33.096699 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11089 23:47:33.139917 INFO: install_deps skipped
11090 23:47:33.642875 --2024-06-04 23:47:33-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11091 23:47:33.656205 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11092 23:47:33.782639 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11093 23:47:33.907188 HTTP request sent, awaiting response... 200 OK
11094 23:47:33.910413 Length: 1642752 (1.6M) [application/octet-stream]
11095 23:47:33.913733 Saving to: 'kselftest_armhf.tar.gz'
11096 23:47:33.913823
11097 23:47:33.913926
11098 23:47:34.157835 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
11099 23:47:34.407525 kselftest_armhf.tar 3%[ ] 50.15K 205KB/s
11100 23:47:34.704449 kselftest_armhf.tar 13%[=> ] 217.50K 445KB/s
11101 23:47:34.831632 kselftest_armhf.tar 51%[=========> ] 822.71K 1.03MB/s
11102 23:47:34.838071 kselftest_armhf.tar 100%[===================>] 1.57M 1.73MB/s in 0.9s
11103 23:47:34.838225
11104 23:47:34.988158 2024-06-04 23:47:34 (1.73 MB/s) - 'kselftest_armhf.tar.gz' saved [1642752/1642752]
11105 23:47:34.988335
11106 23:47:39.942073 skiplist:
11107 23:47:39.945183 ========================================
11108 23:47:39.948700 ========================================
11109 23:47:40.000508 rtc:rtctest
11110 23:47:40.022414 ============== Tests to run ===============
11111 23:47:40.025635 rtc:rtctest
11112 23:47:40.029132 ===========End Tests to run ===============
11113 23:47:40.032084 shardfile-rtc pass
11114 23:47:40.144259 <12>[ 27.657522] kselftest: Running tests in rtc
11115 23:47:40.154867 TAP version 13
11116 23:47:40.170062 1..1
11117 23:47:40.202140 # selftests: rtc: rtctest
11118 23:47:40.673496 # TAP version 13
11119 23:47:40.673700 # 1..8
11120 23:47:40.676764 # # Starting 8 tests from 2 test cases.
11121 23:47:40.679874 # # RUN rtc.date_read ...
11122 23:47:40.686800 # # rtctest.c:49:date_read:Current RTC date/time is 04/06/2024 23:47:40.
11123 23:47:40.689953 # # OK rtc.date_read
11124 23:47:40.693112 # ok 1 rtc.date_read
11125 23:47:40.696447 # # RUN rtc.date_read_loop ...
11126 23:47:40.706228 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11127 23:47:52.786453 <6>[ 40.304575] vpu: disabling
11128 23:47:52.789754 <6>[ 40.307681] vproc2: disabling
11129 23:47:52.793594 <6>[ 40.311538] vproc1: disabling
11130 23:47:52.797889 <6>[ 40.315554] vaud18: disabling
11131 23:47:52.804473 <6>[ 40.319316] vsram_others: disabling
11132 23:47:52.807997 <6>[ 40.323499] va09: disabling
11133 23:47:52.811069 <6>[ 40.326904] vsram_md: disabling
11134 23:47:52.814403 <6>[ 40.330680] Vgpu: disabling
11135 23:48:10.753710 # # rtctest.c:115:date_read_loop:Performed 2614 RTC time reads.
11136 23:48:10.756860 # # OK rtc.date_read_loop
11137 23:48:10.760437 # ok 2 rtc.date_read_loop
11138 23:48:10.763551 # # RUN rtc.uie_read ...
11139 23:48:13.740105 # # OK rtc.uie_read
11140 23:48:13.743354 # ok 3 rtc.uie_read
11141 23:48:13.746483 # # RUN rtc.uie_select ...
11142 23:48:16.739510 # # OK rtc.uie_select
11143 23:48:16.742950 # ok 4 rtc.uie_select
11144 23:48:16.745881 # # RUN rtc.alarm_alm_set ...
11145 23:48:16.752895 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 23:48:20.
11146 23:48:16.755927 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11147 23:48:16.762777 # # alarm_alm_set: Test terminated by assertion
11148 23:48:16.765667 # # FAIL rtc.alarm_alm_set
11149 23:48:16.769286 # not ok 5 rtc.alarm_alm_set
11150 23:48:16.772441 # # RUN rtc.alarm_wkalm_set ...
11151 23:48:16.778738 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 04/06/2024 23:48:20.
11152 23:48:19.742202 # # OK rtc.alarm_wkalm_set
11153 23:48:19.742339 # ok 6 rtc.alarm_wkalm_set
11154 23:48:19.748575 # # RUN rtc.alarm_alm_set_minute ...
11155 23:48:19.751864 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 23:49:00.
11156 23:48:19.758335 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11157 23:48:19.765253 # # alarm_alm_set_minute: Test terminated by assertion
11158 23:48:19.768407 # # FAIL rtc.alarm_alm_set_minute
11159 23:48:19.772154 # not ok 7 rtc.alarm_alm_set_minute
11160 23:48:19.774999 # # RUN rtc.alarm_wkalm_set_minute ...
11161 23:48:19.782080 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 04/06/2024 23:49:00.
11162 23:48:59.738109 # # OK rtc.alarm_wkalm_set_minute
11163 23:48:59.741689 # ok 8 rtc.alarm_wkalm_set_minute
11164 23:48:59.744209 # # FAILED: 6 / 8 tests passed.
11165 23:48:59.747397 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11166 23:48:59.751340 not ok 1 selftests: rtc: rtctest # exit=1
11167 23:49:01.344145 rtc_rtctest_rtc_date_read pass
11168 23:49:01.347317 rtc_rtctest_rtc_date_read_loop pass
11169 23:49:01.351031 rtc_rtctest_rtc_uie_read pass
11170 23:49:01.353835 rtc_rtctest_rtc_uie_select pass
11171 23:49:01.357649 rtc_rtctest_rtc_alarm_alm_set fail
11172 23:49:01.360593 rtc_rtctest_rtc_alarm_wkalm_set pass
11173 23:49:01.363760 rtc_rtctest_rtc_alarm_alm_set_minute fail
11174 23:49:01.367367 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11175 23:49:01.370529 rtc_rtctest fail
11176 23:49:01.420854 + ../../utils/send-to-lava.sh ./output/result.txt
11177 23:49:01.514046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11178 23:49:01.514879 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11180 23:49:01.577841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11181 23:49:01.578530 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11183 23:49:01.642206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11184 23:49:01.642979 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11186 23:49:01.707615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11187 23:49:01.708545 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11189 23:49:01.773353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11190 23:49:01.774058 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11192 23:49:01.836252 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11193 23:49:01.836935 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11195 23:49:01.905046 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11196 23:49:01.905781 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11198 23:49:01.974665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11199 23:49:01.975341 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11201 23:49:02.042618 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11202 23:49:02.043312 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11204 23:49:02.096574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11205 23:49:02.097086 + set +x
11206 23:49:02.097761 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11208 23:49:02.103178 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 14172986_1.6.2.3.5>
11209 23:49:02.103875 Received signal: <ENDRUN> 1_kselftest-rtc 14172986_1.6.2.3.5
11210 23:49:02.104256 Ending use of test pattern.
11211 23:49:02.104574 Ending test lava.1_kselftest-rtc (14172986_1.6.2.3.5), duration 89.04
11213 23:49:02.105759 ok: lava_test_shell seems to have completed
11214 23:49:02.106504 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11215 23:49:02.106947 end: 3.1 lava-test-shell (duration 00:01:30) [common]
11216 23:49:02.107364 end: 3 lava-test-retry (duration 00:01:30) [common]
11217 23:49:02.107858 start: 4 finalize (timeout 00:06:03) [common]
11218 23:49:02.108315 start: 4.1 power-off (timeout 00:00:30) [common]
11219 23:49:02.109037 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-2', '--port=1', '--command=off']
11220 23:49:02.370759 >> Command sent successfully.
11221 23:49:02.381062 Returned 0 in 0 seconds
11222 23:49:02.482277 end: 4.1 power-off (duration 00:00:00) [common]
11224 23:49:02.483806 start: 4.2 read-feedback (timeout 00:06:03) [common]
11226 23:49:02.486022 Listened to connection for namespace 'common' for up to 1s
11227 23:49:03.485575 Finalising connection for namespace 'common'
11228 23:49:03.486244 Disconnecting from shell: Finalise
11229 23:49:03.486636 / #
11230 23:49:03.588015 end: 4.2 read-feedback (duration 00:00:01) [common]
11231 23:49:03.588725 end: 4 finalize (duration 00:00:01) [common]
11232 23:49:03.589392 Cleaning after the job
11233 23:49:03.589897 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/ramdisk
11234 23:49:03.594456 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/kernel
11235 23:49:03.604575 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/dtb
11236 23:49:03.604744 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/nfsrootfs
11237 23:49:03.665527 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172986/tftp-deploy-6o449hfs/modules
11238 23:49:03.670948 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14172986
11239 23:49:04.212955 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14172986
11240 23:49:04.213133 Job finished correctly