Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 46
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 23:40:55.321159 lava-dispatcher, installed at version: 2024.03
2 23:40:55.321366 start: 0 validate
3 23:40:55.321503 Start time: 2024-06-04 23:40:55.321493+00:00 (UTC)
4 23:40:55.321616 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:40:55.321741 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Finitrd.cpio.gz exists
6 23:40:55.583834 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:40:55.584579 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:40:55.838092 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:40:55.838327 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:41:27.745410 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:41:27.746058 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20240313.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:41:28.259234 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:41:28.259983 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.92-cip22%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:41:28.518652 validate duration: 33.20
16 23:41:28.518918 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:41:28.519017 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:41:28.519101 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:41:28.519218 Not decompressing ramdisk as can be used compressed.
20 23:41:28.519299 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/initrd.cpio.gz
21 23:41:28.519364 saving as /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/ramdisk/initrd.cpio.gz
22 23:41:28.519426 total size: 5628169 (5 MB)
23 23:41:30.723273 progress 0 % (0 MB)
24 23:41:30.727751 progress 5 % (0 MB)
25 23:41:30.729498 progress 10 % (0 MB)
26 23:41:30.730933 progress 15 % (0 MB)
27 23:41:30.732591 progress 20 % (1 MB)
28 23:41:30.734025 progress 25 % (1 MB)
29 23:41:30.735622 progress 30 % (1 MB)
30 23:41:30.737976 progress 35 % (1 MB)
31 23:41:30.740040 progress 40 % (2 MB)
32 23:41:30.741632 progress 45 % (2 MB)
33 23:41:30.742962 progress 50 % (2 MB)
34 23:41:30.744440 progress 55 % (2 MB)
35 23:41:30.745955 progress 60 % (3 MB)
36 23:41:30.747279 progress 65 % (3 MB)
37 23:41:30.748752 progress 70 % (3 MB)
38 23:41:30.750117 progress 75 % (4 MB)
39 23:41:30.751592 progress 80 % (4 MB)
40 23:41:30.752909 progress 85 % (4 MB)
41 23:41:30.754460 progress 90 % (4 MB)
42 23:41:30.755932 progress 95 % (5 MB)
43 23:41:30.757266 progress 100 % (5 MB)
44 23:41:30.757513 5 MB downloaded in 2.24 s (2.40 MB/s)
45 23:41:30.757662 end: 1.1.1 http-download (duration 00:00:02) [common]
47 23:41:30.757895 end: 1.1 download-retry (duration 00:00:02) [common]
48 23:41:30.757977 start: 1.2 download-retry (timeout 00:09:58) [common]
49 23:41:30.758058 start: 1.2.1 http-download (timeout 00:09:58) [common]
50 23:41:30.758178 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:41:30.758261 saving as /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/kernel/Image
52 23:41:30.758322 total size: 54682112 (52 MB)
53 23:41:30.758396 No compression specified
54 23:41:30.759453 progress 0 % (0 MB)
55 23:41:30.772839 progress 5 % (2 MB)
56 23:41:30.786383 progress 10 % (5 MB)
57 23:41:30.800057 progress 15 % (7 MB)
58 23:41:30.813565 progress 20 % (10 MB)
59 23:41:30.827556 progress 25 % (13 MB)
60 23:41:30.841070 progress 30 % (15 MB)
61 23:41:30.854629 progress 35 % (18 MB)
62 23:41:30.868112 progress 40 % (20 MB)
63 23:41:30.881601 progress 45 % (23 MB)
64 23:41:30.895452 progress 50 % (26 MB)
65 23:41:30.909111 progress 55 % (28 MB)
66 23:41:30.922949 progress 60 % (31 MB)
67 23:41:30.936595 progress 65 % (33 MB)
68 23:41:30.950294 progress 70 % (36 MB)
69 23:41:30.963616 progress 75 % (39 MB)
70 23:41:30.977148 progress 80 % (41 MB)
71 23:41:30.990577 progress 85 % (44 MB)
72 23:41:31.004013 progress 90 % (46 MB)
73 23:41:31.017644 progress 95 % (49 MB)
74 23:41:31.031157 progress 100 % (52 MB)
75 23:41:31.031414 52 MB downloaded in 0.27 s (190.96 MB/s)
76 23:41:31.031560 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:41:31.031793 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:41:31.031877 start: 1.3 download-retry (timeout 00:09:57) [common]
80 23:41:31.031960 start: 1.3.1 http-download (timeout 00:09:57) [common]
81 23:41:31.032081 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:41:31.032149 saving as /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/dtb/mt8192-asurada-spherion-r0.dtb
83 23:41:31.032209 total size: 47258 (0 MB)
84 23:41:31.032268 No compression specified
85 23:41:31.033406 progress 69 % (0 MB)
86 23:41:31.033675 progress 100 % (0 MB)
87 23:41:31.033824 0 MB downloaded in 0.00 s (27.94 MB/s)
88 23:41:31.033942 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:41:31.034159 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:41:31.034242 start: 1.4 download-retry (timeout 00:09:57) [common]
92 23:41:31.034323 start: 1.4.1 http-download (timeout 00:09:57) [common]
93 23:41:31.034432 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20240313.0/arm64/full.rootfs.tar.xz
94 23:41:31.034497 saving as /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/nfsrootfs/full.rootfs.tar
95 23:41:31.034556 total size: 120894716 (115 MB)
96 23:41:31.034616 Using unxz to decompress xz
97 23:41:31.038614 progress 0 % (0 MB)
98 23:41:31.382283 progress 5 % (5 MB)
99 23:41:31.734582 progress 10 % (11 MB)
100 23:41:32.080332 progress 15 % (17 MB)
101 23:41:32.404405 progress 20 % (23 MB)
102 23:41:32.694789 progress 25 % (28 MB)
103 23:41:33.047511 progress 30 % (34 MB)
104 23:41:33.380967 progress 35 % (40 MB)
105 23:41:33.544178 progress 40 % (46 MB)
106 23:41:33.720918 progress 45 % (51 MB)
107 23:41:34.027008 progress 50 % (57 MB)
108 23:41:34.395373 progress 55 % (63 MB)
109 23:41:34.739354 progress 60 % (69 MB)
110 23:41:35.084504 progress 65 % (74 MB)
111 23:41:35.423994 progress 70 % (80 MB)
112 23:41:35.775699 progress 75 % (86 MB)
113 23:41:36.122886 progress 80 % (92 MB)
114 23:41:36.472108 progress 85 % (98 MB)
115 23:41:36.833378 progress 90 % (103 MB)
116 23:41:37.164722 progress 95 % (109 MB)
117 23:41:37.529189 progress 100 % (115 MB)
118 23:41:37.534587 115 MB downloaded in 6.50 s (17.74 MB/s)
119 23:41:37.534887 end: 1.4.1 http-download (duration 00:00:07) [common]
121 23:41:37.535287 end: 1.4 download-retry (duration 00:00:07) [common]
122 23:41:37.535408 start: 1.5 download-retry (timeout 00:09:51) [common]
123 23:41:37.535526 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 23:41:37.535709 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:41:37.535807 saving as /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/modules/modules.tar
126 23:41:37.535896 total size: 8603924 (8 MB)
127 23:41:37.535988 Using unxz to decompress xz
128 23:41:37.540336 progress 0 % (0 MB)
129 23:41:37.559944 progress 5 % (0 MB)
130 23:41:37.584021 progress 10 % (0 MB)
131 23:41:37.609320 progress 15 % (1 MB)
132 23:41:37.633908 progress 20 % (1 MB)
133 23:41:37.659400 progress 25 % (2 MB)
134 23:41:37.683878 progress 30 % (2 MB)
135 23:41:37.707150 progress 35 % (2 MB)
136 23:41:37.732972 progress 40 % (3 MB)
137 23:41:37.757324 progress 45 % (3 MB)
138 23:41:37.781111 progress 50 % (4 MB)
139 23:41:37.805653 progress 55 % (4 MB)
140 23:41:37.829756 progress 60 % (4 MB)
141 23:41:37.853965 progress 65 % (5 MB)
142 23:41:37.881190 progress 70 % (5 MB)
143 23:41:37.907146 progress 75 % (6 MB)
144 23:41:37.933705 progress 80 % (6 MB)
145 23:41:37.958484 progress 85 % (7 MB)
146 23:41:37.983035 progress 90 % (7 MB)
147 23:41:38.013134 progress 95 % (7 MB)
148 23:41:38.042224 progress 100 % (8 MB)
149 23:41:38.047824 8 MB downloaded in 0.51 s (16.03 MB/s)
150 23:41:38.048109 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:41:38.048377 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:41:38.048474 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 23:41:38.048569 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 23:41:41.546827 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/14172914/extract-nfsrootfs-98qg8u54
156 23:41:41.547036 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 23:41:41.547139 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 23:41:41.547316 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o
159 23:41:41.547445 makedir: /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin
160 23:41:41.547546 makedir: /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/tests
161 23:41:41.547644 makedir: /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/results
162 23:41:41.547745 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-add-keys
163 23:41:41.547886 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-add-sources
164 23:41:41.548015 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-background-process-start
165 23:41:41.548142 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-background-process-stop
166 23:41:41.548270 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-common-functions
167 23:41:41.548395 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-echo-ipv4
168 23:41:41.548521 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-install-packages
169 23:41:41.548647 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-installed-packages
170 23:41:41.548771 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-os-build
171 23:41:41.548896 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-probe-channel
172 23:41:41.549021 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-probe-ip
173 23:41:41.549145 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-target-ip
174 23:41:41.549267 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-target-mac
175 23:41:41.549394 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-target-storage
176 23:41:41.549518 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-test-case
177 23:41:41.549644 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-test-event
178 23:41:41.549767 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-test-feedback
179 23:41:41.549890 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-test-raise
180 23:41:41.550013 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-test-reference
181 23:41:41.550136 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-test-runner
182 23:41:41.550259 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-test-set
183 23:41:41.550384 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-test-shell
184 23:41:41.550512 Updating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-add-keys (debian)
185 23:41:41.550663 Updating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-add-sources (debian)
186 23:41:41.550804 Updating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-install-packages (debian)
187 23:41:41.550944 Updating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-installed-packages (debian)
188 23:41:41.551081 Updating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/bin/lava-os-build (debian)
189 23:41:41.551200 Creating /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/environment
190 23:41:41.551295 LAVA metadata
191 23:41:41.551362 - LAVA_JOB_ID=14172914
192 23:41:41.551425 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:41:41.551541 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 23:41:41.551611 skipped lava-vland-overlay
195 23:41:41.551686 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:41:41.551766 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 23:41:41.551828 skipped lava-multinode-overlay
198 23:41:41.551900 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:41:41.551978 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 23:41:41.552053 Loading test definitions
201 23:41:41.552141 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 23:41:41.552212 Using /lava-14172914 at stage 0
203 23:41:41.552501 uuid=14172914_1.6.2.3.1 testdef=None
204 23:41:41.552590 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:41:41.552677 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 23:41:41.553136 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:41:41.553364 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 23:41:41.553942 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:41:41.554175 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 23:41:41.554735 runner path: /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/0/tests/0_timesync-off test_uuid 14172914_1.6.2.3.1
213 23:41:41.554896 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:41:41.555122 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 23:41:41.555195 Using /lava-14172914 at stage 0
217 23:41:41.555294 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:41:41.555381 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/0/tests/1_kselftest-tpm2'
219 23:41:44.598174 Running '/usr/bin/git checkout kernelci.org
220 23:41:44.747330 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 23:41:44.748386 uuid=14172914_1.6.2.3.5 testdef=None
222 23:41:44.748597 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 23:41:44.748970 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 23:41:44.750116 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:41:44.750472 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 23:41:44.751995 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:41:44.752351 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 23:41:44.753852 runner path: /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/0/tests/1_kselftest-tpm2 test_uuid 14172914_1.6.2.3.5
232 23:41:44.753982 BOARD='mt8192-asurada-spherion-r0'
233 23:41:44.754080 BRANCH='cip'
234 23:41:44.754173 SKIPFILE='/dev/null'
235 23:41:44.754266 SKIP_INSTALL='True'
236 23:41:44.754357 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:41:44.754455 TST_CASENAME=''
238 23:41:44.754546 TST_CMDFILES='tpm2'
239 23:41:44.754746 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:41:44.755072 Creating lava-test-runner.conf files
242 23:41:44.755169 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/14172914/lava-overlay-17tww79o/lava-14172914/0 for stage 0
243 23:41:44.755304 - 0_timesync-off
244 23:41:44.755409 - 1_kselftest-tpm2
245 23:41:44.755548 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 23:41:44.755678 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 23:41:52.247596 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 23:41:52.247765 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 23:41:52.247861 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:41:52.247960 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 23:41:52.248048 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 23:41:52.412186 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:41:52.412581 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 23:41:52.412699 extracting modules file /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172914/extract-nfsrootfs-98qg8u54
255 23:41:52.627642 extracting modules file /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/14172914/extract-overlay-ramdisk-s1pgmxw5/ramdisk
256 23:41:52.849706 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:41:52.849906 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 23:41:52.850031 [common] Applying overlay to NFS
259 23:41:52.850137 [common] Applying overlay /var/lib/lava/dispatcher/tmp/14172914/compress-overlay-m4qv19gq/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/14172914/extract-nfsrootfs-98qg8u54
260 23:41:53.760693 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:41:53.760871 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 23:41:53.760964 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:41:53.761055 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 23:41:53.761140 Building ramdisk /var/lib/lava/dispatcher/tmp/14172914/extract-overlay-ramdisk-s1pgmxw5/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/14172914/extract-overlay-ramdisk-s1pgmxw5/ramdisk
265 23:41:54.110653 >> 130337 blocks
266 23:41:56.113511 rename /var/lib/lava/dispatcher/tmp/14172914/extract-overlay-ramdisk-s1pgmxw5/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/ramdisk/ramdisk.cpio.gz
267 23:41:56.113951 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:41:56.114086 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 23:41:56.114189 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 23:41:56.114293 Calling: ['lzma', '--keep', '/var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/kernel/Image']
271 23:42:09.053543 Returned 0 in 12 seconds
272 23:42:09.154148 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/kernel/image.itb
273 23:42:09.525307 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:42:09.525682 output: Created: Wed Jun 5 00:42:09 2024
275 23:42:09.525760 output: Image 0 (kernel-1)
276 23:42:09.525835 output: Description:
277 23:42:09.525899 output: Created: Wed Jun 5 00:42:09 2024
278 23:42:09.525963 output: Type: Kernel Image
279 23:42:09.526024 output: Compression: lzma compressed
280 23:42:09.526087 output: Data Size: 13061430 Bytes = 12755.30 KiB = 12.46 MiB
281 23:42:09.526163 output: Architecture: AArch64
282 23:42:09.526223 output: OS: Linux
283 23:42:09.526278 output: Load Address: 0x00000000
284 23:42:09.526334 output: Entry Point: 0x00000000
285 23:42:09.526409 output: Hash algo: crc32
286 23:42:09.526464 output: Hash value: ecfb5096
287 23:42:09.526518 output: Image 1 (fdt-1)
288 23:42:09.526574 output: Description: mt8192-asurada-spherion-r0
289 23:42:09.526650 output: Created: Wed Jun 5 00:42:09 2024
290 23:42:09.526711 output: Type: Flat Device Tree
291 23:42:09.526767 output: Compression: uncompressed
292 23:42:09.526821 output: Data Size: 47258 Bytes = 46.15 KiB = 0.05 MiB
293 23:42:09.526894 output: Architecture: AArch64
294 23:42:09.526951 output: Hash algo: crc32
295 23:42:09.527004 output: Hash value: 0f8e4d2e
296 23:42:09.527058 output: Image 2 (ramdisk-1)
297 23:42:09.527123 output: Description: unavailable
298 23:42:09.527209 output: Created: Wed Jun 5 00:42:09 2024
299 23:42:09.527292 output: Type: RAMDisk Image
300 23:42:09.527383 output: Compression: Unknown Compression
301 23:42:09.527467 output: Data Size: 18730110 Bytes = 18291.12 KiB = 17.86 MiB
302 23:42:09.527550 output: Architecture: AArch64
303 23:42:09.527647 output: OS: Linux
304 23:42:09.527705 output: Load Address: unavailable
305 23:42:09.527759 output: Entry Point: unavailable
306 23:42:09.527812 output: Hash algo: crc32
307 23:42:09.527872 output: Hash value: e3a99f22
308 23:42:09.527935 output: Default Configuration: 'conf-1'
309 23:42:09.527989 output: Configuration 0 (conf-1)
310 23:42:09.528042 output: Description: mt8192-asurada-spherion-r0
311 23:42:09.528095 output: Kernel: kernel-1
312 23:42:09.528167 output: Init Ramdisk: ramdisk-1
313 23:42:09.528223 output: FDT: fdt-1
314 23:42:09.528276 output: Loadables: kernel-1
315 23:42:09.528329 output:
316 23:42:09.528551 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 23:42:09.528662 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 23:42:09.528775 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 23:42:09.528871 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 23:42:09.528965 No LXC device requested
321 23:42:09.529046 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:42:09.529136 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 23:42:09.529256 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:42:09.529378 Checking files for TFTP limit of 4294967296 bytes.
325 23:42:09.529913 end: 1 tftp-deploy (duration 00:00:41) [common]
326 23:42:09.530030 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:42:09.530121 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:42:09.530263 substitutions:
329 23:42:09.530333 - {DTB}: 14172914/tftp-deploy-758tthvv/dtb/mt8192-asurada-spherion-r0.dtb
330 23:42:09.530397 - {INITRD}: 14172914/tftp-deploy-758tthvv/ramdisk/ramdisk.cpio.gz
331 23:42:09.530477 - {KERNEL}: 14172914/tftp-deploy-758tthvv/kernel/Image
332 23:42:09.530537 - {LAVA_MAC}: None
333 23:42:09.530594 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/14172914/extract-nfsrootfs-98qg8u54
334 23:42:09.530650 - {NFS_SERVER_IP}: 192.168.201.1
335 23:42:09.530724 - {PRESEED_CONFIG}: None
336 23:42:09.530781 - {PRESEED_LOCAL}: None
337 23:42:09.530835 - {RAMDISK}: 14172914/tftp-deploy-758tthvv/ramdisk/ramdisk.cpio.gz
338 23:42:09.530890 - {ROOT_PART}: None
339 23:42:09.530964 - {ROOT}: None
340 23:42:09.531020 - {SERVER_IP}: 192.168.201.1
341 23:42:09.531073 - {TEE}: None
342 23:42:09.531127 Parsed boot commands:
343 23:42:09.531196 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:42:09.531383 Parsed boot commands: tftpboot 192.168.201.1 14172914/tftp-deploy-758tthvv/kernel/image.itb 14172914/tftp-deploy-758tthvv/kernel/cmdline
345 23:42:09.531487 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:42:09.531599 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:42:09.531727 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:42:09.531847 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:42:09.531955 Not connected, no need to disconnect.
350 23:42:09.532069 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:42:09.532159 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:42:09.532246 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
353 23:42:09.536083 Setting prompt string to ['lava-test: # ']
354 23:42:09.536494 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:42:09.536651 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:42:09.536756 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:42:09.536846 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:42:09.537052 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=reboot']
359 23:42:14.671229 >> Command sent successfully.
360 23:42:14.673718 Returned 0 in 5 seconds
361 23:42:14.774108 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:42:14.774430 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:42:14.774527 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:42:14.774621 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:42:14.774688 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:42:14.774755 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:42:14.775174 [Enter `^Ec?' for help]
369 23:42:14.954409
370 23:42:14.954560
371 23:42:14.954636 F0: 102B 0000
372 23:42:14.954703
373 23:42:14.954765 F3: 1001 0000 [0200]
374 23:42:14.954825
375 23:42:14.957555 F3: 1001 0000
376 23:42:14.957675
377 23:42:14.957741 F7: 102D 0000
378 23:42:14.957804
379 23:42:14.957863 F1: 0000 0000
380 23:42:14.960823
381 23:42:14.960906 V0: 0000 0000 [0001]
382 23:42:14.960974
383 23:42:14.961035 00: 0007 8000
384 23:42:14.963982
385 23:42:14.964065 01: 0000 0000
386 23:42:14.964133
387 23:42:14.964194 BP: 0C00 0209 [0000]
388 23:42:14.964253
389 23:42:14.967423 G0: 1182 0000
390 23:42:14.967506
391 23:42:14.967603 EC: 0000 0021 [4000]
392 23:42:14.967712
393 23:42:14.971231 S7: 0000 0000 [0000]
394 23:42:14.971315
395 23:42:14.971381 CC: 0000 0000 [0001]
396 23:42:14.974267
397 23:42:14.974353 T0: 0000 0040 [010F]
398 23:42:14.974421
399 23:42:14.974484 Jump to BL
400 23:42:14.974544
401 23:42:15.000794
402 23:42:15.000903
403 23:42:15.008124 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
404 23:42:15.011865 ARM64: Exception handlers installed.
405 23:42:15.015149 ARM64: Testing exception
406 23:42:15.018637 ARM64: Done test exception
407 23:42:15.025614 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
408 23:42:15.035227 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
409 23:42:15.042187 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
410 23:42:15.052476 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
411 23:42:15.058957 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
412 23:42:15.065792 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
413 23:42:15.077545 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
414 23:42:15.083973 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
415 23:42:15.103815 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
416 23:42:15.106682 WDT: Last reset was cold boot
417 23:42:15.110051 SPI1(PAD0) initialized at 2873684 Hz
418 23:42:15.113242 SPI5(PAD0) initialized at 992727 Hz
419 23:42:15.116836 VBOOT: Loading verstage.
420 23:42:15.123330 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
421 23:42:15.126732 FMAP: Found "FLASH" version 1.1 at 0x20000.
422 23:42:15.129884 FMAP: base = 0x0 size = 0x800000 #areas = 25
423 23:42:15.133517 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
424 23:42:15.140915 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
425 23:42:15.147388 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
426 23:42:15.158433 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
427 23:42:15.158512
428 23:42:15.158577
429 23:42:15.168820 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
430 23:42:15.171925 ARM64: Exception handlers installed.
431 23:42:15.175268 ARM64: Testing exception
432 23:42:15.175377 ARM64: Done test exception
433 23:42:15.181911 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
434 23:42:15.185481 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
435 23:42:15.199353 Probing TPM: . done!
436 23:42:15.199465 TPM ready after 0 ms
437 23:42:15.206714 Connected to device vid:did:rid of 1ae0:0028:00
438 23:42:15.213656 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
439 23:42:15.261554 Initialized TPM device CR50 revision 0
440 23:42:15.277010 tlcl_send_startup: Startup return code is 0
441 23:42:15.277124 TPM: setup succeeded
442 23:42:15.287787 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
443 23:42:15.296660 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
444 23:42:15.306006 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
445 23:42:15.314841 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
446 23:42:15.318233 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
447 23:42:15.321813 in-header: 03 07 00 00 08 00 00 00
448 23:42:15.324765 in-data: aa e4 47 04 13 02 00 00
449 23:42:15.328229 Chrome EC: UHEPI supported
450 23:42:15.334734 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
451 23:42:15.338565 in-header: 03 95 00 00 08 00 00 00
452 23:42:15.342066 in-data: 18 20 20 08 00 00 00 00
453 23:42:15.342166 Phase 1
454 23:42:15.345464 FMAP: area GBB found @ 3f5000 (12032 bytes)
455 23:42:15.353097 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
456 23:42:15.356543 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
457 23:42:15.360418 Recovery requested (1009000e)
458 23:42:15.369676 TPM: Extending digest for VBOOT: boot mode into PCR 0
459 23:42:15.375355 tlcl_extend: response is 0
460 23:42:15.384461 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
461 23:42:15.390334 tlcl_extend: response is 0
462 23:42:15.396954 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
463 23:42:15.417732 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
464 23:42:15.424728 BS: bootblock times (exec / console): total (unknown) / 148 ms
465 23:42:15.424808
466 23:42:15.424878
467 23:42:15.435555 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
468 23:42:15.435640 ARM64: Exception handlers installed.
469 23:42:15.439273 ARM64: Testing exception
470 23:42:15.442053 ARM64: Done test exception
471 23:42:15.462475 pmic_efuse_setting: Set efuses in 11 msecs
472 23:42:15.465702 pmwrap_interface_init: Select PMIF_VLD_RDY
473 23:42:15.472496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
474 23:42:15.475859 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
475 23:42:15.482864 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
476 23:42:15.485738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
477 23:42:15.492413 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
478 23:42:15.496075 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
479 23:42:15.499108 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
480 23:42:15.505815 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
481 23:42:15.509377 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
482 23:42:15.516055 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
483 23:42:15.519035 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
484 23:42:15.522566 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
485 23:42:15.529176 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
486 23:42:15.535877 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
487 23:42:15.539605 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
488 23:42:15.546447 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
489 23:42:15.550788 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
490 23:42:15.557742 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
491 23:42:15.565182 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
492 23:42:15.568699 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
493 23:42:15.575506 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
494 23:42:15.579153 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
495 23:42:15.586593 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
496 23:42:15.590071 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
497 23:42:15.597310 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
498 23:42:15.601055 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
499 23:42:15.608351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
500 23:42:15.612374 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
501 23:42:15.615789 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
502 23:42:15.623332 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
503 23:42:15.627432 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
504 23:42:15.630680 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
505 23:42:15.638006 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
506 23:42:15.641919 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
507 23:42:15.645404 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
508 23:42:15.652741 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
509 23:42:15.656365 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
510 23:42:15.660041 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
511 23:42:15.667468 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
512 23:42:15.671115 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
513 23:42:15.674709 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
514 23:42:15.678425 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
515 23:42:15.682315 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
516 23:42:15.689591 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
517 23:42:15.693528 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
518 23:42:15.696864 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
519 23:42:15.700700 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
520 23:42:15.704669 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
521 23:42:15.707927 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
522 23:42:15.711814 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
523 23:42:15.719345 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
524 23:42:15.726124 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
525 23:42:15.733322 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
526 23:42:15.737125 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
527 23:42:15.748028 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
528 23:42:15.755296 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
529 23:42:15.759027 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
530 23:42:15.762418 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
531 23:42:15.769838 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:42:15.777573 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x26
533 23:42:15.780888 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
534 23:42:15.784310 [RTC]rtc_osc_init,62: osc32con val = 0xde70
535 23:42:15.790975 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
536 23:42:15.799910 [RTC]rtc_get_frequency_meter,154: input=15, output=764
537 23:42:15.809535 [RTC]rtc_get_frequency_meter,154: input=23, output=949
538 23:42:15.819159 [RTC]rtc_get_frequency_meter,154: input=19, output=857
539 23:42:15.828638 [RTC]rtc_get_frequency_meter,154: input=17, output=810
540 23:42:15.838194 [RTC]rtc_get_frequency_meter,154: input=16, output=787
541 23:42:15.847752 [RTC]rtc_get_frequency_meter,154: input=16, output=787
542 23:42:15.858248 [RTC]rtc_get_frequency_meter,154: input=17, output=809
543 23:42:15.860994 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
544 23:42:15.868192 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
545 23:42:15.872108 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
546 23:42:15.875794 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
547 23:42:15.879111 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
548 23:42:15.882848 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
549 23:42:15.886470 ADC[4]: Raw value=670432 ID=5
550 23:42:15.890125 ADC[3]: Raw value=212917 ID=1
551 23:42:15.890204 RAM Code: 0x51
552 23:42:15.893846 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
553 23:42:15.901100 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
554 23:42:15.908287 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
555 23:42:15.912289 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
556 23:42:15.915220 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
557 23:42:15.919319 in-header: 03 07 00 00 08 00 00 00
558 23:42:15.923024 in-data: aa e4 47 04 13 02 00 00
559 23:42:15.926716 Chrome EC: UHEPI supported
560 23:42:15.933244 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
561 23:42:15.937003 in-header: 03 95 00 00 08 00 00 00
562 23:42:15.940616 in-data: 18 20 20 08 00 00 00 00
563 23:42:15.944411 MRC: failed to locate region type 0.
564 23:42:15.948146 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
565 23:42:15.951762 DRAM-K: Running full calibration
566 23:42:15.959518 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
567 23:42:15.959610 header.status = 0x0
568 23:42:15.963224 header.version = 0x6 (expected: 0x6)
569 23:42:15.967119 header.size = 0xd00 (expected: 0xd00)
570 23:42:15.967198 header.flags = 0x0
571 23:42:15.974365 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
572 23:42:15.992760 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
573 23:42:16.000039 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
574 23:42:16.000126 dram_init: ddr_geometry: 0
575 23:42:16.003533 [EMI] MDL number = 0
576 23:42:16.007412 [EMI] Get MDL freq = 0
577 23:42:16.007488 dram_init: ddr_type: 0
578 23:42:16.010957 is_discrete_lpddr4: 1
579 23:42:16.014854 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
580 23:42:16.014932
581 23:42:16.014997
582 23:42:16.015065 [Bian_co] ETT version 0.0.0.1
583 23:42:16.022150 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
584 23:42:16.022236
585 23:42:16.026315 dramc_set_vcore_voltage set vcore to 650000
586 23:42:16.026392 Read voltage for 800, 4
587 23:42:16.026463 Vio18 = 0
588 23:42:16.029821 Vcore = 650000
589 23:42:16.029923 Vdram = 0
590 23:42:16.029992 Vddq = 0
591 23:42:16.033534 Vmddr = 0
592 23:42:16.033604 dram_init: config_dvfs: 1
593 23:42:16.041051 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
594 23:42:16.044534 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
595 23:42:16.048180 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
596 23:42:16.052101 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
597 23:42:16.055592 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
598 23:42:16.059358 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
599 23:42:16.062892 MEM_TYPE=3, freq_sel=18
600 23:42:16.067221 sv_algorithm_assistance_LP4_1600
601 23:42:16.071093 ============ PULL DRAM RESETB DOWN ============
602 23:42:16.074427 ========== PULL DRAM RESETB DOWN end =========
603 23:42:16.078151 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
604 23:42:16.081562 ===================================
605 23:42:16.085138 LPDDR4 DRAM CONFIGURATION
606 23:42:16.088781 ===================================
607 23:42:16.088858 EX_ROW_EN[0] = 0x0
608 23:42:16.092530 EX_ROW_EN[1] = 0x0
609 23:42:16.092624 LP4Y_EN = 0x0
610 23:42:16.096433 WORK_FSP = 0x0
611 23:42:16.096511 WL = 0x2
612 23:42:16.096575 RL = 0x2
613 23:42:16.100091 BL = 0x2
614 23:42:16.100163 RPST = 0x0
615 23:42:16.103608 RD_PRE = 0x0
616 23:42:16.103683 WR_PRE = 0x1
617 23:42:16.107521 WR_PST = 0x0
618 23:42:16.107595 DBI_WR = 0x0
619 23:42:16.110921 DBI_RD = 0x0
620 23:42:16.111000 OTF = 0x1
621 23:42:16.114801 ===================================
622 23:42:16.118445 ===================================
623 23:42:16.118524 ANA top config
624 23:42:16.122150 ===================================
625 23:42:16.125615 DLL_ASYNC_EN = 0
626 23:42:16.129700 ALL_SLAVE_EN = 1
627 23:42:16.129778 NEW_RANK_MODE = 1
628 23:42:16.133454 DLL_IDLE_MODE = 1
629 23:42:16.136718 LP45_APHY_COMB_EN = 1
630 23:42:16.136791 TX_ODT_DIS = 1
631 23:42:16.140187 NEW_8X_MODE = 1
632 23:42:16.143462 ===================================
633 23:42:16.146681 ===================================
634 23:42:16.150054 data_rate = 1600
635 23:42:16.153421 CKR = 1
636 23:42:16.156603 DQ_P2S_RATIO = 8
637 23:42:16.160262 ===================================
638 23:42:16.163633 CA_P2S_RATIO = 8
639 23:42:16.163706 DQ_CA_OPEN = 0
640 23:42:16.167253 DQ_SEMI_OPEN = 0
641 23:42:16.171062 CA_SEMI_OPEN = 0
642 23:42:16.174412 CA_FULL_RATE = 0
643 23:42:16.174496 DQ_CKDIV4_EN = 1
644 23:42:16.178102 CA_CKDIV4_EN = 1
645 23:42:16.181977 CA_PREDIV_EN = 0
646 23:42:16.184867 PH8_DLY = 0
647 23:42:16.188352 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
648 23:42:16.188426 DQ_AAMCK_DIV = 4
649 23:42:16.191566 CA_AAMCK_DIV = 4
650 23:42:16.194894 CA_ADMCK_DIV = 4
651 23:42:16.199390 DQ_TRACK_CA_EN = 0
652 23:42:16.202500 CA_PICK = 800
653 23:42:16.202611 CA_MCKIO = 800
654 23:42:16.205796 MCKIO_SEMI = 0
655 23:42:16.208844 PLL_FREQ = 3068
656 23:42:16.212086 DQ_UI_PI_RATIO = 32
657 23:42:16.215350 CA_UI_PI_RATIO = 0
658 23:42:16.219334 ===================================
659 23:42:16.222826 ===================================
660 23:42:16.222910 memory_type:LPDDR4
661 23:42:16.226044 GP_NUM : 10
662 23:42:16.229304 SRAM_EN : 1
663 23:42:16.229379 MD32_EN : 0
664 23:42:16.233276 ===================================
665 23:42:16.236730 [ANA_INIT] >>>>>>>>>>>>>>
666 23:42:16.240719 <<<<<< [CONFIGURE PHASE]: ANA_TX
667 23:42:16.240798 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
668 23:42:16.244256 ===================================
669 23:42:16.247904 data_rate = 1600,PCW = 0X7600
670 23:42:16.251380 ===================================
671 23:42:16.254995 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
672 23:42:16.261844 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
673 23:42:16.265254 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:42:16.272054 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
675 23:42:16.275262 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
676 23:42:16.279207 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:42:16.279291 [ANA_INIT] flow start
678 23:42:16.281825 [ANA_INIT] PLL >>>>>>>>
679 23:42:16.285422 [ANA_INIT] PLL <<<<<<<<
680 23:42:16.285498 [ANA_INIT] MIDPI >>>>>>>>
681 23:42:16.288542 [ANA_INIT] MIDPI <<<<<<<<
682 23:42:16.291807 [ANA_INIT] DLL >>>>>>>>
683 23:42:16.291898 [ANA_INIT] flow end
684 23:42:16.298843 ============ LP4 DIFF to SE enter ============
685 23:42:16.302061 ============ LP4 DIFF to SE exit ============
686 23:42:16.302137 [ANA_INIT] <<<<<<<<<<<<<
687 23:42:16.305085 [Flow] Enable top DCM control >>>>>
688 23:42:16.308781 [Flow] Enable top DCM control <<<<<
689 23:42:16.311845 Enable DLL master slave shuffle
690 23:42:16.318477 ==============================================================
691 23:42:16.321856 Gating Mode config
692 23:42:16.325234 ==============================================================
693 23:42:16.328321 Config description:
694 23:42:16.339131 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
695 23:42:16.345586 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
696 23:42:16.348493 SELPH_MODE 0: By rank 1: By Phase
697 23:42:16.355102 ==============================================================
698 23:42:16.358473 GAT_TRACK_EN = 1
699 23:42:16.361788 RX_GATING_MODE = 2
700 23:42:16.361869 RX_GATING_TRACK_MODE = 2
701 23:42:16.364888 SELPH_MODE = 1
702 23:42:16.368499 PICG_EARLY_EN = 1
703 23:42:16.371763 VALID_LAT_VALUE = 1
704 23:42:16.378382 ==============================================================
705 23:42:16.381730 Enter into Gating configuration >>>>
706 23:42:16.385462 Exit from Gating configuration <<<<
707 23:42:16.388332 Enter into DVFS_PRE_config >>>>>
708 23:42:16.398312 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
709 23:42:16.401739 Exit from DVFS_PRE_config <<<<<
710 23:42:16.405078 Enter into PICG configuration >>>>
711 23:42:16.408334 Exit from PICG configuration <<<<
712 23:42:16.411707 [RX_INPUT] configuration >>>>>
713 23:42:16.415248 [RX_INPUT] configuration <<<<<
714 23:42:16.418383 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
715 23:42:16.424817 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
716 23:42:16.432044 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
717 23:42:16.434998 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
718 23:42:16.441771 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
719 23:42:16.448372 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
720 23:42:16.451584 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
721 23:42:16.458389 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
722 23:42:16.461702 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
723 23:42:16.464860 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
724 23:42:16.468377 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
725 23:42:16.474838 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
726 23:42:16.478242 ===================================
727 23:42:16.478326 LPDDR4 DRAM CONFIGURATION
728 23:42:16.482038 ===================================
729 23:42:16.485100 EX_ROW_EN[0] = 0x0
730 23:42:16.488254 EX_ROW_EN[1] = 0x0
731 23:42:16.488341 LP4Y_EN = 0x0
732 23:42:16.491883 WORK_FSP = 0x0
733 23:42:16.491969 WL = 0x2
734 23:42:16.495121 RL = 0x2
735 23:42:16.495208 BL = 0x2
736 23:42:16.498612 RPST = 0x0
737 23:42:16.498696 RD_PRE = 0x0
738 23:42:16.501572 WR_PRE = 0x1
739 23:42:16.501656 WR_PST = 0x0
740 23:42:16.505269 DBI_WR = 0x0
741 23:42:16.505373 DBI_RD = 0x0
742 23:42:16.508329 OTF = 0x1
743 23:42:16.511539 ===================================
744 23:42:16.515450 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
745 23:42:16.518138 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
746 23:42:16.525010 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
747 23:42:16.528306 ===================================
748 23:42:16.528390 LPDDR4 DRAM CONFIGURATION
749 23:42:16.531640 ===================================
750 23:42:16.534818 EX_ROW_EN[0] = 0x10
751 23:42:16.534903 EX_ROW_EN[1] = 0x0
752 23:42:16.538356 LP4Y_EN = 0x0
753 23:42:16.538440 WORK_FSP = 0x0
754 23:42:16.542214 WL = 0x2
755 23:42:16.542298 RL = 0x2
756 23:42:16.544933 BL = 0x2
757 23:42:16.545017 RPST = 0x0
758 23:42:16.548457 RD_PRE = 0x0
759 23:42:16.551747 WR_PRE = 0x1
760 23:42:16.551831 WR_PST = 0x0
761 23:42:16.555184 DBI_WR = 0x0
762 23:42:16.555268 DBI_RD = 0x0
763 23:42:16.558736 OTF = 0x1
764 23:42:16.561643 ===================================
765 23:42:16.565135 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
766 23:42:16.570370 nWR fixed to 40
767 23:42:16.573656 [ModeRegInit_LP4] CH0 RK0
768 23:42:16.573748 [ModeRegInit_LP4] CH0 RK1
769 23:42:16.576916 [ModeRegInit_LP4] CH1 RK0
770 23:42:16.580379 [ModeRegInit_LP4] CH1 RK1
771 23:42:16.580463 match AC timing 12
772 23:42:16.586978 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
773 23:42:16.590507 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
774 23:42:16.593614 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
775 23:42:16.600189 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
776 23:42:16.603655 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
777 23:42:16.603759 [EMI DOE] emi_dcm 0
778 23:42:16.610269 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
779 23:42:16.610350 ==
780 23:42:16.613739 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:42:16.616923 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 23:42:16.617000 ==
783 23:42:16.623609 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
784 23:42:16.630158 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
785 23:42:16.638132 [CA 0] Center 37 (7~68) winsize 62
786 23:42:16.640966 [CA 1] Center 37 (7~68) winsize 62
787 23:42:16.644309 [CA 2] Center 35 (5~66) winsize 62
788 23:42:16.647585 [CA 3] Center 35 (5~66) winsize 62
789 23:42:16.650811 [CA 4] Center 34 (3~65) winsize 63
790 23:42:16.654099 [CA 5] Center 33 (3~64) winsize 62
791 23:42:16.654171
792 23:42:16.657513 [CmdBusTrainingLP45] Vref(ca) range 1: 34
793 23:42:16.657583
794 23:42:16.660743 [CATrainingPosCal] consider 1 rank data
795 23:42:16.664181 u2DelayCellTimex100 = 270/100 ps
796 23:42:16.667651 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
797 23:42:16.674327 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
798 23:42:16.677455 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
799 23:42:16.680886 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
800 23:42:16.684263 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
801 23:42:16.687505 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
802 23:42:16.687599
803 23:42:16.690944 CA PerBit enable=1, Macro0, CA PI delay=33
804 23:42:16.691044
805 23:42:16.694286 [CBTSetCACLKResult] CA Dly = 33
806 23:42:16.694358 CS Dly: 5 (0~36)
807 23:42:16.694419 ==
808 23:42:16.697637 Dram Type= 6, Freq= 0, CH_0, rank 1
809 23:42:16.704310 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
810 23:42:16.704397 ==
811 23:42:16.707612 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
812 23:42:16.714072 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
813 23:42:16.723467 [CA 0] Center 37 (7~68) winsize 62
814 23:42:16.727160 [CA 1] Center 37 (6~68) winsize 63
815 23:42:16.730324 [CA 2] Center 35 (4~66) winsize 63
816 23:42:16.733813 [CA 3] Center 35 (4~66) winsize 63
817 23:42:16.736967 [CA 4] Center 34 (3~65) winsize 63
818 23:42:16.740263 [CA 5] Center 34 (3~65) winsize 63
819 23:42:16.740335
820 23:42:16.743425 [CmdBusTrainingLP45] Vref(ca) range 1: 34
821 23:42:16.743523
822 23:42:16.747028 [CATrainingPosCal] consider 2 rank data
823 23:42:16.750458 u2DelayCellTimex100 = 270/100 ps
824 23:42:16.754048 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
825 23:42:16.757177 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
826 23:42:16.763862 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
827 23:42:16.767109 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
828 23:42:16.770323 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
829 23:42:16.773679 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
830 23:42:16.773787
831 23:42:16.777463 CA PerBit enable=1, Macro0, CA PI delay=33
832 23:42:16.777541
833 23:42:16.780202 [CBTSetCACLKResult] CA Dly = 33
834 23:42:16.780303 CS Dly: 5 (0~37)
835 23:42:16.780392
836 23:42:16.783905 ----->DramcWriteLeveling(PI) begin...
837 23:42:16.786866 ==
838 23:42:16.790327 Dram Type= 6, Freq= 0, CH_0, rank 0
839 23:42:16.793598 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
840 23:42:16.793670 ==
841 23:42:16.796816 Write leveling (Byte 0): 31 => 31
842 23:42:16.800234 Write leveling (Byte 1): 31 => 31
843 23:42:16.803802 DramcWriteLeveling(PI) end<-----
844 23:42:16.803873
845 23:42:16.803934 ==
846 23:42:16.807526 Dram Type= 6, Freq= 0, CH_0, rank 0
847 23:42:16.811308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
848 23:42:16.811391 ==
849 23:42:16.811457 [Gating] SW mode calibration
850 23:42:16.819422 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
851 23:42:16.826207 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
852 23:42:16.829140 0 6 0 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 1)
853 23:42:16.832651 0 6 4 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
854 23:42:16.839327 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 23:42:16.842802 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 23:42:16.845990 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 23:42:16.852640 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:42:16.856243 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:42:16.859536 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:42:16.866256 0 7 0 | B1->B0 | 2929 2b2b | 0 0 | (0 0) (0 0)
861 23:42:16.869501 0 7 4 | B1->B0 | 3a3a 4040 | 0 0 | (1 1) (0 0)
862 23:42:16.873063 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 23:42:16.879425 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 23:42:16.882603 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 23:42:16.886379 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 23:42:16.889494 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 23:42:16.896323 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
868 23:42:16.899773 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
869 23:42:16.902818 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 23:42:16.909415 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 23:42:16.912857 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 23:42:16.916187 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 23:42:16.922503 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 23:42:16.926221 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 23:42:16.929455 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 23:42:16.936006 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 23:42:16.939143 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 23:42:16.942403 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 23:42:16.949364 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 23:42:16.952574 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 23:42:16.955629 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 23:42:16.962291 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
883 23:42:16.965917 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
884 23:42:16.969096 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
885 23:42:16.976123 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
886 23:42:16.976211 Total UI for P1: 0, mck2ui 16
887 23:42:16.982469 best dqsien dly found for B0: ( 0, 9, 30)
888 23:42:16.982554 Total UI for P1: 0, mck2ui 16
889 23:42:16.989092 best dqsien dly found for B1: ( 0, 9, 30)
890 23:42:16.992209 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
891 23:42:16.995437 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
892 23:42:16.995522
893 23:42:16.998699 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
894 23:42:17.001979 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
895 23:42:17.005681 [Gating] SW calibration Done
896 23:42:17.005765 ==
897 23:42:17.009077 Dram Type= 6, Freq= 0, CH_0, rank 0
898 23:42:17.011967 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
899 23:42:17.012052 ==
900 23:42:17.015795 RX Vref Scan: 0
901 23:42:17.015880
902 23:42:17.015946 RX Vref 0 -> 0, step: 1
903 23:42:17.016008
904 23:42:17.018649 RX Delay -130 -> 252, step: 16
905 23:42:17.025511 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
906 23:42:17.028943 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
907 23:42:17.031997 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
908 23:42:17.035515 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
909 23:42:17.038837 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
910 23:42:17.042051 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
911 23:42:17.049054 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
912 23:42:17.052289 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
913 23:42:17.055338 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
914 23:42:17.059081 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
915 23:42:17.062039 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
916 23:42:17.068837 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
917 23:42:17.072326 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
918 23:42:17.075649 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
919 23:42:17.078731 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
920 23:42:17.085548 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
921 23:42:17.085633 ==
922 23:42:17.088583 Dram Type= 6, Freq= 0, CH_0, rank 0
923 23:42:17.092351 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
924 23:42:17.092436 ==
925 23:42:17.092502 DQS Delay:
926 23:42:17.095429 DQS0 = 0, DQS1 = 0
927 23:42:17.095512 DQM Delay:
928 23:42:17.099250 DQM0 = 83, DQM1 = 74
929 23:42:17.099333 DQ Delay:
930 23:42:17.102090 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
931 23:42:17.105646 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =101
932 23:42:17.108633 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
933 23:42:17.112120 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
934 23:42:17.112203
935 23:42:17.112270
936 23:42:17.112332 ==
937 23:42:17.115351 Dram Type= 6, Freq= 0, CH_0, rank 0
938 23:42:17.118865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
939 23:42:17.118950 ==
940 23:42:17.119017
941 23:42:17.119079
942 23:42:17.122122 TX Vref Scan disable
943 23:42:17.125454 == TX Byte 0 ==
944 23:42:17.128573 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
945 23:42:17.132475 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
946 23:42:17.135253 == TX Byte 1 ==
947 23:42:17.138917 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
948 23:42:17.141842 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
949 23:42:17.141926 ==
950 23:42:17.145245 Dram Type= 6, Freq= 0, CH_0, rank 0
951 23:42:17.151871 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
952 23:42:17.151955 ==
953 23:42:17.163391 TX Vref=22, minBit 4, minWin=27, winSum=449
954 23:42:17.166684 TX Vref=24, minBit 3, minWin=27, winSum=446
955 23:42:17.170092 TX Vref=26, minBit 3, minWin=27, winSum=453
956 23:42:17.173657 TX Vref=28, minBit 0, minWin=28, winSum=456
957 23:42:17.176746 TX Vref=30, minBit 0, minWin=28, winSum=459
958 23:42:17.180329 TX Vref=32, minBit 0, minWin=28, winSum=457
959 23:42:17.186810 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
960 23:42:17.186893
961 23:42:17.190219 Final TX Range 1 Vref 30
962 23:42:17.190297
963 23:42:17.190360 ==
964 23:42:17.193565 Dram Type= 6, Freq= 0, CH_0, rank 0
965 23:42:17.197283 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
966 23:42:17.197401 ==
967 23:42:17.197467
968 23:42:17.197529
969 23:42:17.200933 TX Vref Scan disable
970 23:42:17.204051 == TX Byte 0 ==
971 23:42:17.207409 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
972 23:42:17.210900 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
973 23:42:17.214330 == TX Byte 1 ==
974 23:42:17.217504 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
975 23:42:17.220787 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
976 23:42:17.220895
977 23:42:17.224292 [DATLAT]
978 23:42:17.224406 Freq=800, CH0 RK0
979 23:42:17.224502
980 23:42:17.227507 DATLAT Default: 0xa
981 23:42:17.227610 0, 0xFFFF, sum = 0
982 23:42:17.230914 1, 0xFFFF, sum = 0
983 23:42:17.230988 2, 0xFFFF, sum = 0
984 23:42:17.234191 3, 0xFFFF, sum = 0
985 23:42:17.234291 4, 0xFFFF, sum = 0
986 23:42:17.237483 5, 0xFFFF, sum = 0
987 23:42:17.237556 6, 0xFFFF, sum = 0
988 23:42:17.240879 7, 0xFFFF, sum = 0
989 23:42:17.240985 8, 0x0, sum = 1
990 23:42:17.244258 9, 0x0, sum = 2
991 23:42:17.244329 10, 0x0, sum = 3
992 23:42:17.247554 11, 0x0, sum = 4
993 23:42:17.247652 best_step = 9
994 23:42:17.247748
995 23:42:17.247835 ==
996 23:42:17.251156 Dram Type= 6, Freq= 0, CH_0, rank 0
997 23:42:17.254121 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
998 23:42:17.254224 ==
999 23:42:17.257494 RX Vref Scan: 1
1000 23:42:17.257565
1001 23:42:17.260610 Set Vref Range= 32 -> 127
1002 23:42:17.260709
1003 23:42:17.260799 RX Vref 32 -> 127, step: 1
1004 23:42:17.260892
1005 23:42:17.264073 RX Delay -111 -> 252, step: 8
1006 23:42:17.264175
1007 23:42:17.267863 Set Vref, RX VrefLevel [Byte0]: 32
1008 23:42:17.270588 [Byte1]: 32
1009 23:42:17.274543
1010 23:42:17.274621 Set Vref, RX VrefLevel [Byte0]: 33
1011 23:42:17.277277 [Byte1]: 33
1012 23:42:17.281965
1013 23:42:17.282045 Set Vref, RX VrefLevel [Byte0]: 34
1014 23:42:17.285132 [Byte1]: 34
1015 23:42:17.289692
1016 23:42:17.289768 Set Vref, RX VrefLevel [Byte0]: 35
1017 23:42:17.292937 [Byte1]: 35
1018 23:42:17.297180
1019 23:42:17.297251 Set Vref, RX VrefLevel [Byte0]: 36
1020 23:42:17.300293 [Byte1]: 36
1021 23:42:17.304653
1022 23:42:17.304725 Set Vref, RX VrefLevel [Byte0]: 37
1023 23:42:17.308115 [Byte1]: 37
1024 23:42:17.312374
1025 23:42:17.312457 Set Vref, RX VrefLevel [Byte0]: 38
1026 23:42:17.315681 [Byte1]: 38
1027 23:42:17.319859
1028 23:42:17.319961 Set Vref, RX VrefLevel [Byte0]: 39
1029 23:42:17.323373 [Byte1]: 39
1030 23:42:17.327773
1031 23:42:17.327875 Set Vref, RX VrefLevel [Byte0]: 40
1032 23:42:17.330856 [Byte1]: 40
1033 23:42:17.335291
1034 23:42:17.335364 Set Vref, RX VrefLevel [Byte0]: 41
1035 23:42:17.338721 [Byte1]: 41
1036 23:42:17.343060
1037 23:42:17.343130 Set Vref, RX VrefLevel [Byte0]: 42
1038 23:42:17.346419 [Byte1]: 42
1039 23:42:17.350522
1040 23:42:17.350591 Set Vref, RX VrefLevel [Byte0]: 43
1041 23:42:17.354224 [Byte1]: 43
1042 23:42:17.358275
1043 23:42:17.358345 Set Vref, RX VrefLevel [Byte0]: 44
1044 23:42:17.361576 [Byte1]: 44
1045 23:42:17.365999
1046 23:42:17.366080 Set Vref, RX VrefLevel [Byte0]: 45
1047 23:42:17.369162 [Byte1]: 45
1048 23:42:17.373649
1049 23:42:17.373723 Set Vref, RX VrefLevel [Byte0]: 46
1050 23:42:17.377050 [Byte1]: 46
1051 23:42:17.381042
1052 23:42:17.381141 Set Vref, RX VrefLevel [Byte0]: 47
1053 23:42:17.384471 [Byte1]: 47
1054 23:42:17.389221
1055 23:42:17.389353 Set Vref, RX VrefLevel [Byte0]: 48
1056 23:42:17.392028 [Byte1]: 48
1057 23:42:17.396473
1058 23:42:17.396580 Set Vref, RX VrefLevel [Byte0]: 49
1059 23:42:17.399912 [Byte1]: 49
1060 23:42:17.404418
1061 23:42:17.404491 Set Vref, RX VrefLevel [Byte0]: 50
1062 23:42:17.407774 [Byte1]: 50
1063 23:42:17.411916
1064 23:42:17.411990 Set Vref, RX VrefLevel [Byte0]: 51
1065 23:42:17.418173 [Byte1]: 51
1066 23:42:17.418263
1067 23:42:17.421531 Set Vref, RX VrefLevel [Byte0]: 52
1068 23:42:17.424935 [Byte1]: 52
1069 23:42:17.425006
1070 23:42:17.428107 Set Vref, RX VrefLevel [Byte0]: 53
1071 23:42:17.431610 [Byte1]: 53
1072 23:42:17.434877
1073 23:42:17.434947 Set Vref, RX VrefLevel [Byte0]: 54
1074 23:42:17.438295 [Byte1]: 54
1075 23:42:17.442669
1076 23:42:17.442738 Set Vref, RX VrefLevel [Byte0]: 55
1077 23:42:17.445693 [Byte1]: 55
1078 23:42:17.449906
1079 23:42:17.449980 Set Vref, RX VrefLevel [Byte0]: 56
1080 23:42:17.453381 [Byte1]: 56
1081 23:42:17.457841
1082 23:42:17.457931 Set Vref, RX VrefLevel [Byte0]: 57
1083 23:42:17.461045 [Byte1]: 57
1084 23:42:17.465320
1085 23:42:17.465419 Set Vref, RX VrefLevel [Byte0]: 58
1086 23:42:17.468882 [Byte1]: 58
1087 23:42:17.473366
1088 23:42:17.473444 Set Vref, RX VrefLevel [Byte0]: 59
1089 23:42:17.476769 [Byte1]: 59
1090 23:42:17.481244
1091 23:42:17.481377 Set Vref, RX VrefLevel [Byte0]: 60
1092 23:42:17.484501 [Byte1]: 60
1093 23:42:17.488407
1094 23:42:17.488490 Set Vref, RX VrefLevel [Byte0]: 61
1095 23:42:17.492016 [Byte1]: 61
1096 23:42:17.496391
1097 23:42:17.496474 Set Vref, RX VrefLevel [Byte0]: 62
1098 23:42:17.499460 [Byte1]: 62
1099 23:42:17.503870
1100 23:42:17.503956 Set Vref, RX VrefLevel [Byte0]: 63
1101 23:42:17.507298 [Byte1]: 63
1102 23:42:17.511349
1103 23:42:17.511431 Set Vref, RX VrefLevel [Byte0]: 64
1104 23:42:17.514554 [Byte1]: 64
1105 23:42:17.518795
1106 23:42:17.518877 Set Vref, RX VrefLevel [Byte0]: 65
1107 23:42:17.522311 [Byte1]: 65
1108 23:42:17.526467
1109 23:42:17.526548 Set Vref, RX VrefLevel [Byte0]: 66
1110 23:42:17.529847 [Byte1]: 66
1111 23:42:17.534058
1112 23:42:17.534140 Set Vref, RX VrefLevel [Byte0]: 67
1113 23:42:17.537431 [Byte1]: 67
1114 23:42:17.541743
1115 23:42:17.541825 Set Vref, RX VrefLevel [Byte0]: 68
1116 23:42:17.544909 [Byte1]: 68
1117 23:42:17.549344
1118 23:42:17.549438 Set Vref, RX VrefLevel [Byte0]: 69
1119 23:42:17.553198 [Byte1]: 69
1120 23:42:17.556944
1121 23:42:17.557039 Set Vref, RX VrefLevel [Byte0]: 70
1122 23:42:17.560382 [Byte1]: 70
1123 23:42:17.564830
1124 23:42:17.564931 Set Vref, RX VrefLevel [Byte0]: 71
1125 23:42:17.568189 [Byte1]: 71
1126 23:42:17.572751
1127 23:42:17.572850 Set Vref, RX VrefLevel [Byte0]: 72
1128 23:42:17.575436 [Byte1]: 72
1129 23:42:17.579931
1130 23:42:17.580033 Set Vref, RX VrefLevel [Byte0]: 73
1131 23:42:17.583282 [Byte1]: 73
1132 23:42:17.587798
1133 23:42:17.587882 Set Vref, RX VrefLevel [Byte0]: 74
1134 23:42:17.591532 [Byte1]: 74
1135 23:42:17.595306
1136 23:42:17.595386 Final RX Vref Byte 0 = 52 to rank0
1137 23:42:17.598421 Final RX Vref Byte 1 = 57 to rank0
1138 23:42:17.601786 Final RX Vref Byte 0 = 52 to rank1
1139 23:42:17.605120 Final RX Vref Byte 1 = 57 to rank1==
1140 23:42:17.608596 Dram Type= 6, Freq= 0, CH_0, rank 0
1141 23:42:17.615244 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1142 23:42:17.615340 ==
1143 23:42:17.615428 DQS Delay:
1144 23:42:17.615520 DQS0 = 0, DQS1 = 0
1145 23:42:17.618423 DQM Delay:
1146 23:42:17.618521 DQM0 = 84, DQM1 = 73
1147 23:42:17.622047 DQ Delay:
1148 23:42:17.625216 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1149 23:42:17.625341 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1150 23:42:17.628692 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1151 23:42:17.635547 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1152 23:42:17.635647
1153 23:42:17.635735
1154 23:42:17.641929 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1155 23:42:17.644889 CH0 RK0: MR19=606, MR18=3C3C
1156 23:42:17.651676 CH0_RK0: MR19=0x606, MR18=0x3C3C, DQSOSC=394, MR23=63, INC=95, DEC=63
1157 23:42:17.651780
1158 23:42:17.655277 ----->DramcWriteLeveling(PI) begin...
1159 23:42:17.655372 ==
1160 23:42:17.658653 Dram Type= 6, Freq= 0, CH_0, rank 1
1161 23:42:17.661651 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1162 23:42:17.661750 ==
1163 23:42:17.664855 Write leveling (Byte 0): 30 => 30
1164 23:42:17.668284 Write leveling (Byte 1): 28 => 28
1165 23:42:17.671498 DramcWriteLeveling(PI) end<-----
1166 23:42:17.671579
1167 23:42:17.671643 ==
1168 23:42:17.674947 Dram Type= 6, Freq= 0, CH_0, rank 1
1169 23:42:17.678176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1170 23:42:17.678268 ==
1171 23:42:17.681562 [Gating] SW mode calibration
1172 23:42:17.688336 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1173 23:42:17.695007 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1174 23:42:17.698268 0 6 0 | B1->B0 | 3030 2f2f | 1 1 | (1 0) (1 0)
1175 23:42:17.701643 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (1 1) (0 0)
1176 23:42:17.708329 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:42:17.711832 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:42:17.714921 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 23:42:17.721634 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 23:42:17.725045 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 23:42:17.728619 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 23:42:17.735047 0 7 0 | B1->B0 | 3030 2e2e | 0 0 | (0 0) (0 0)
1183 23:42:17.738328 0 7 4 | B1->B0 | 4444 4343 | 0 0 | (1 1) (0 0)
1184 23:42:17.741484 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 23:42:17.748345 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 23:42:17.751645 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 23:42:17.755117 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 23:42:17.761506 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 23:42:17.764847 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 23:42:17.768232 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 23:42:17.771783 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 23:42:17.778491 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 23:42:17.781664 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 23:42:17.785106 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 23:42:17.791991 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 23:42:17.794960 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 23:42:17.798317 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 23:42:17.805030 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 23:42:17.808307 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 23:42:17.811788 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 23:42:17.818222 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 23:42:17.821646 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 23:42:17.825212 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:42:17.831625 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:42:17.835310 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:42:17.838787 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1207 23:42:17.845405 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1208 23:42:17.848759 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 23:42:17.852209 Total UI for P1: 0, mck2ui 16
1210 23:42:17.855215 best dqsien dly found for B0: ( 0, 10, 2)
1211 23:42:17.858382 Total UI for P1: 0, mck2ui 16
1212 23:42:17.861757 best dqsien dly found for B1: ( 0, 10, 4)
1213 23:42:17.865382 best DQS0 dly(MCK, UI, PI) = (0, 10, 2)
1214 23:42:17.868595 best DQS1 dly(MCK, UI, PI) = (0, 10, 4)
1215 23:42:17.868700
1216 23:42:17.871831 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 2)
1217 23:42:17.875462 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 4)
1218 23:42:17.878688 [Gating] SW calibration Done
1219 23:42:17.878768 ==
1220 23:42:17.923007 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 23:42:17.923399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1222 23:42:17.923481 ==
1223 23:42:17.923545 RX Vref Scan: 0
1224 23:42:17.923605
1225 23:42:17.923663 RX Vref 0 -> 0, step: 1
1226 23:42:17.923719
1227 23:42:17.923958 RX Delay -130 -> 252, step: 16
1228 23:42:17.924018 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1229 23:42:17.924074 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1230 23:42:17.924139 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1231 23:42:17.924206 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1232 23:42:17.924262 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1233 23:42:17.924641 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1234 23:42:17.925196 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1235 23:42:17.942106 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1236 23:42:17.942187 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1237 23:42:17.942435 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1238 23:42:17.942500 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1239 23:42:17.945325 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1240 23:42:17.945405 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1241 23:42:17.948699 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1242 23:42:17.951951 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1243 23:42:17.958841 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1244 23:42:17.958922 ==
1245 23:42:17.962079 Dram Type= 6, Freq= 0, CH_0, rank 1
1246 23:42:17.965350 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1247 23:42:17.965444 ==
1248 23:42:17.965509 DQS Delay:
1249 23:42:17.968697 DQS0 = 0, DQS1 = 0
1250 23:42:17.968777 DQM Delay:
1251 23:42:17.972058 DQM0 = 82, DQM1 = 73
1252 23:42:17.972139 DQ Delay:
1253 23:42:17.975510 DQ0 =77, DQ1 =85, DQ2 =85, DQ3 =77
1254 23:42:17.978934 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
1255 23:42:17.982036 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
1256 23:42:17.985565 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1257 23:42:17.985659
1258 23:42:17.985723
1259 23:42:17.985783 ==
1260 23:42:17.988726 Dram Type= 6, Freq= 0, CH_0, rank 1
1261 23:42:17.992164 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1262 23:42:17.992246 ==
1263 23:42:17.992310
1264 23:42:17.992368
1265 23:42:17.995554 TX Vref Scan disable
1266 23:42:17.998749 == TX Byte 0 ==
1267 23:42:18.001857 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1268 23:42:18.005219 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1269 23:42:18.008766 == TX Byte 1 ==
1270 23:42:18.012049 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1271 23:42:18.015176 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1272 23:42:18.015257 ==
1273 23:42:18.018671 Dram Type= 6, Freq= 0, CH_0, rank 1
1274 23:42:18.022184 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1275 23:42:18.025216 ==
1276 23:42:18.036919 TX Vref=22, minBit 0, minWin=27, winSum=447
1277 23:42:18.040092 TX Vref=24, minBit 0, minWin=28, winSum=453
1278 23:42:18.043677 TX Vref=26, minBit 2, minWin=28, winSum=456
1279 23:42:18.046882 TX Vref=28, minBit 2, minWin=28, winSum=460
1280 23:42:18.050640 TX Vref=30, minBit 2, minWin=28, winSum=459
1281 23:42:18.054662 TX Vref=32, minBit 0, minWin=28, winSum=455
1282 23:42:18.062059 [TxChooseVref] Worse bit 2, Min win 28, Win sum 460, Final Vref 28
1283 23:42:18.062141
1284 23:42:18.062205 Final TX Range 1 Vref 28
1285 23:42:18.062265
1286 23:42:18.065599 ==
1287 23:42:18.065680 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 23:42:18.072182 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1289 23:42:18.072263 ==
1290 23:42:18.072326
1291 23:42:18.072386
1292 23:42:18.072442 TX Vref Scan disable
1293 23:42:18.077039 == TX Byte 0 ==
1294 23:42:18.080645 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1295 23:42:18.084035 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1296 23:42:18.087282 == TX Byte 1 ==
1297 23:42:18.090604 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1298 23:42:18.093913 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1299 23:42:18.093994
1300 23:42:18.097397 [DATLAT]
1301 23:42:18.097479 Freq=800, CH0 RK1
1302 23:42:18.097543
1303 23:42:18.100757 DATLAT Default: 0x9
1304 23:42:18.100838 0, 0xFFFF, sum = 0
1305 23:42:18.104078 1, 0xFFFF, sum = 0
1306 23:42:18.104180 2, 0xFFFF, sum = 0
1307 23:42:18.107648 3, 0xFFFF, sum = 0
1308 23:42:18.107730 4, 0xFFFF, sum = 0
1309 23:42:18.110630 5, 0xFFFF, sum = 0
1310 23:42:18.110712 6, 0xFFFF, sum = 0
1311 23:42:18.113960 7, 0xFFFF, sum = 0
1312 23:42:18.114042 8, 0x0, sum = 1
1313 23:42:18.117231 9, 0x0, sum = 2
1314 23:42:18.117338 10, 0x0, sum = 3
1315 23:42:18.120692 11, 0x0, sum = 4
1316 23:42:18.120775 best_step = 9
1317 23:42:18.120840
1318 23:42:18.120901 ==
1319 23:42:18.124147 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 23:42:18.127516 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1321 23:42:18.127600 ==
1322 23:42:18.130654 RX Vref Scan: 0
1323 23:42:18.130736
1324 23:42:18.133947 RX Vref 0 -> 0, step: 1
1325 23:42:18.134029
1326 23:42:18.134094 RX Delay -111 -> 252, step: 8
1327 23:42:18.141603 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1328 23:42:18.144876 iDelay=209, Bit 1, Center 88 (-31 ~ 208) 240
1329 23:42:18.148309 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1330 23:42:18.151569 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1331 23:42:18.154774 iDelay=209, Bit 4, Center 88 (-31 ~ 208) 240
1332 23:42:18.161499 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1333 23:42:18.164779 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
1334 23:42:18.168293 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1335 23:42:18.171646 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1336 23:42:18.174836 iDelay=209, Bit 9, Center 60 (-55 ~ 176) 232
1337 23:42:18.181479 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1338 23:42:18.184959 iDelay=209, Bit 11, Center 64 (-47 ~ 176) 224
1339 23:42:18.188139 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1340 23:42:18.191809 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1341 23:42:18.194902 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
1342 23:42:18.201621 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1343 23:42:18.201704 ==
1344 23:42:18.205013 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 23:42:18.208238 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1346 23:42:18.208321 ==
1347 23:42:18.208387 DQS Delay:
1348 23:42:18.212018 DQS0 = 0, DQS1 = 0
1349 23:42:18.212100 DQM Delay:
1350 23:42:18.214850 DQM0 = 85, DQM1 = 73
1351 23:42:18.214933 DQ Delay:
1352 23:42:18.218214 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =80
1353 23:42:18.221817 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1354 23:42:18.225220 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =64
1355 23:42:18.228328 DQ12 =80, DQ13 =76, DQ14 =84, DQ15 =84
1356 23:42:18.228410
1357 23:42:18.228474
1358 23:42:18.234985 [DQSOSCAuto] RK1, (LSB)MR18= 0x4444, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 392 ps
1359 23:42:18.238229 CH0 RK1: MR19=606, MR18=4444
1360 23:42:18.244662 CH0_RK1: MR19=0x606, MR18=0x4444, DQSOSC=392, MR23=63, INC=96, DEC=64
1361 23:42:18.248228 [RxdqsGatingPostProcess] freq 800
1362 23:42:18.255126 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1363 23:42:18.258039 Pre-setting of DQS Precalculation
1364 23:42:18.261296 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1365 23:42:18.261393 ==
1366 23:42:18.264712 Dram Type= 6, Freq= 0, CH_1, rank 0
1367 23:42:18.268329 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1368 23:42:18.268412 ==
1369 23:42:18.274742 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1370 23:42:18.281771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1371 23:42:18.289121 [CA 0] Center 37 (6~68) winsize 63
1372 23:42:18.292709 [CA 1] Center 37 (6~68) winsize 63
1373 23:42:18.296175 [CA 2] Center 34 (4~65) winsize 62
1374 23:42:18.299355 [CA 3] Center 34 (4~65) winsize 62
1375 23:42:18.302998 [CA 4] Center 33 (3~64) winsize 62
1376 23:42:18.305836 [CA 5] Center 33 (3~64) winsize 62
1377 23:42:18.305918
1378 23:42:18.309609 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1379 23:42:18.309691
1380 23:42:18.312722 [CATrainingPosCal] consider 1 rank data
1381 23:42:18.316227 u2DelayCellTimex100 = 270/100 ps
1382 23:42:18.319316 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1383 23:42:18.322743 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1384 23:42:18.329439 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1385 23:42:18.332706 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1386 23:42:18.336087 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1387 23:42:18.339495 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1388 23:42:18.339578
1389 23:42:18.342704 CA PerBit enable=1, Macro0, CA PI delay=33
1390 23:42:18.342786
1391 23:42:18.345920 [CBTSetCACLKResult] CA Dly = 33
1392 23:42:18.346002 CS Dly: 5 (0~36)
1393 23:42:18.349258 ==
1394 23:42:18.349348 Dram Type= 6, Freq= 0, CH_1, rank 1
1395 23:42:18.355791 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1396 23:42:18.355874 ==
1397 23:42:18.359522 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1398 23:42:18.366024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1399 23:42:18.375070 [CA 0] Center 36 (6~67) winsize 62
1400 23:42:18.378494 [CA 1] Center 37 (6~68) winsize 63
1401 23:42:18.381971 [CA 2] Center 34 (4~65) winsize 62
1402 23:42:18.385190 [CA 3] Center 34 (4~65) winsize 62
1403 23:42:18.388457 [CA 4] Center 33 (3~64) winsize 62
1404 23:42:18.391556 [CA 5] Center 33 (3~64) winsize 62
1405 23:42:18.391638
1406 23:42:18.395071 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1407 23:42:18.395153
1408 23:42:18.398445 [CATrainingPosCal] consider 2 rank data
1409 23:42:18.401913 u2DelayCellTimex100 = 270/100 ps
1410 23:42:18.405074 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1411 23:42:18.408451 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1412 23:42:18.415327 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1413 23:42:18.418651 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1414 23:42:18.421697 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1415 23:42:18.425151 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1416 23:42:18.425233
1417 23:42:18.428506 CA PerBit enable=1, Macro0, CA PI delay=33
1418 23:42:18.428588
1419 23:42:18.431708 [CBTSetCACLKResult] CA Dly = 33
1420 23:42:18.431790 CS Dly: 5 (0~37)
1421 23:42:18.431855
1422 23:42:18.435172 ----->DramcWriteLeveling(PI) begin...
1423 23:42:18.438536 ==
1424 23:42:18.438618 Dram Type= 6, Freq= 0, CH_1, rank 0
1425 23:42:18.445285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1426 23:42:18.445408 ==
1427 23:42:18.448408 Write leveling (Byte 0): 25 => 25
1428 23:42:18.451746 Write leveling (Byte 1): 27 => 27
1429 23:42:18.455045 DramcWriteLeveling(PI) end<-----
1430 23:42:18.455127
1431 23:42:18.455192 ==
1432 23:42:18.458448 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 23:42:18.461546 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1434 23:42:18.461627 ==
1435 23:42:18.465075 [Gating] SW mode calibration
1436 23:42:18.471739 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1437 23:42:18.475078 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1438 23:42:18.481708 0 6 0 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
1439 23:42:18.484788 0 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1440 23:42:18.488206 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 23:42:18.494988 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 23:42:18.498200 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 23:42:18.501595 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 23:42:18.508065 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 23:42:18.511723 0 6 28 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
1446 23:42:18.514589 0 7 0 | B1->B0 | 2d2d 3c3c | 0 0 | (0 0) (0 0)
1447 23:42:18.521627 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1448 23:42:18.524905 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1449 23:42:18.528093 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1450 23:42:18.534922 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1451 23:42:18.538352 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1452 23:42:18.541522 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1453 23:42:18.548143 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1454 23:42:18.551766 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1455 23:42:18.554985 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1456 23:42:18.561675 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1457 23:42:18.565176 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1458 23:42:18.568286 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1459 23:42:18.574797 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1460 23:42:18.578274 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1461 23:42:18.581601 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1462 23:42:18.584870 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1463 23:42:18.591817 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1464 23:42:18.594899 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1465 23:42:18.598104 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1466 23:42:18.604732 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1467 23:42:18.608147 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1468 23:42:18.611533 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1469 23:42:18.618378 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1470 23:42:18.621658 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1471 23:42:18.624892 Total UI for P1: 0, mck2ui 16
1472 23:42:18.628118 best dqsien dly found for B0: ( 0, 9, 28)
1473 23:42:18.631537 Total UI for P1: 0, mck2ui 16
1474 23:42:18.634735 best dqsien dly found for B1: ( 0, 9, 30)
1475 23:42:18.638217 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1476 23:42:18.641478 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1477 23:42:18.641561
1478 23:42:18.644871 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1479 23:42:18.648170 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1480 23:42:18.651617 [Gating] SW calibration Done
1481 23:42:18.651700 ==
1482 23:42:18.654665 Dram Type= 6, Freq= 0, CH_1, rank 0
1483 23:42:18.658083 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1484 23:42:18.661663 ==
1485 23:42:18.661746 RX Vref Scan: 0
1486 23:42:18.661811
1487 23:42:18.665248 RX Vref 0 -> 0, step: 1
1488 23:42:18.665379
1489 23:42:18.668215 RX Delay -130 -> 252, step: 16
1490 23:42:18.671598 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1491 23:42:18.675329 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1492 23:42:18.678367 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1493 23:42:18.681513 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1494 23:42:18.688264 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1495 23:42:18.691356 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1496 23:42:18.694775 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1497 23:42:18.698421 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1498 23:42:18.701257 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1499 23:42:18.708166 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1500 23:42:18.711552 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1501 23:42:18.714891 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1502 23:42:18.718633 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1503 23:42:18.722337 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1504 23:42:18.726173 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1505 23:42:18.729680 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1506 23:42:18.729762 ==
1507 23:42:18.733337 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 23:42:18.736937 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1509 23:42:18.740809 ==
1510 23:42:18.740890 DQS Delay:
1511 23:42:18.740954 DQS0 = 0, DQS1 = 0
1512 23:42:18.744431 DQM Delay:
1513 23:42:18.744512 DQM0 = 81, DQM1 = 71
1514 23:42:18.744576 DQ Delay:
1515 23:42:18.747745 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1516 23:42:18.751029 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1517 23:42:18.754576 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1518 23:42:18.757953 DQ12 =77, DQ13 =85, DQ14 =77, DQ15 =77
1519 23:42:18.758034
1520 23:42:18.758098
1521 23:42:18.758157 ==
1522 23:42:18.761144 Dram Type= 6, Freq= 0, CH_1, rank 0
1523 23:42:18.767831 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1524 23:42:18.767913 ==
1525 23:42:18.767977
1526 23:42:18.768036
1527 23:42:18.768093 TX Vref Scan disable
1528 23:42:18.771748 == TX Byte 0 ==
1529 23:42:18.774908 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1530 23:42:18.781227 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1531 23:42:18.781365 == TX Byte 1 ==
1532 23:42:18.784385 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1533 23:42:18.791146 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1534 23:42:18.791228 ==
1535 23:42:18.794949 Dram Type= 6, Freq= 0, CH_1, rank 0
1536 23:42:18.797811 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1537 23:42:18.797893 ==
1538 23:42:18.810261 TX Vref=22, minBit 3, minWin=27, winSum=446
1539 23:42:18.813645 TX Vref=24, minBit 3, minWin=27, winSum=448
1540 23:42:18.817013 TX Vref=26, minBit 8, minWin=27, winSum=447
1541 23:42:18.820722 TX Vref=28, minBit 0, minWin=28, winSum=459
1542 23:42:18.823860 TX Vref=30, minBit 9, minWin=27, winSum=459
1543 23:42:18.827247 TX Vref=32, minBit 0, minWin=28, winSum=457
1544 23:42:18.833623 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 28
1545 23:42:18.833705
1546 23:42:18.836955 Final TX Range 1 Vref 28
1547 23:42:18.837036
1548 23:42:18.837100 ==
1549 23:42:18.840212 Dram Type= 6, Freq= 0, CH_1, rank 0
1550 23:42:18.843970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1551 23:42:18.844052 ==
1552 23:42:18.844116
1553 23:42:18.846862
1554 23:42:18.846942 TX Vref Scan disable
1555 23:42:18.850277 == TX Byte 0 ==
1556 23:42:18.853881 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1557 23:42:18.860005 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1558 23:42:18.860087 == TX Byte 1 ==
1559 23:42:18.863730 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1560 23:42:18.870053 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1561 23:42:18.870135
1562 23:42:18.870198 [DATLAT]
1563 23:42:18.870257 Freq=800, CH1 RK0
1564 23:42:18.870314
1565 23:42:18.873564 DATLAT Default: 0xa
1566 23:42:18.873645 0, 0xFFFF, sum = 0
1567 23:42:18.876967 1, 0xFFFF, sum = 0
1568 23:42:18.877050 2, 0xFFFF, sum = 0
1569 23:42:18.880246 3, 0xFFFF, sum = 0
1570 23:42:18.883617 4, 0xFFFF, sum = 0
1571 23:42:18.883699 5, 0xFFFF, sum = 0
1572 23:42:18.886623 6, 0xFFFF, sum = 0
1573 23:42:18.886731 7, 0xFFFF, sum = 0
1574 23:42:18.890494 8, 0x0, sum = 1
1575 23:42:18.890576 9, 0x0, sum = 2
1576 23:42:18.890642 10, 0x0, sum = 3
1577 23:42:18.893470 11, 0x0, sum = 4
1578 23:42:18.893552 best_step = 9
1579 23:42:18.893616
1580 23:42:18.893675 ==
1581 23:42:18.896872 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 23:42:18.903402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1583 23:42:18.903484 ==
1584 23:42:18.903548 RX Vref Scan: 1
1585 23:42:18.903608
1586 23:42:18.906938 Set Vref Range= 32 -> 127
1587 23:42:18.907018
1588 23:42:18.910210 RX Vref 32 -> 127, step: 1
1589 23:42:18.910292
1590 23:42:18.913523 RX Delay -111 -> 252, step: 8
1591 23:42:18.913604
1592 23:42:18.916635 Set Vref, RX VrefLevel [Byte0]: 32
1593 23:42:18.920540 [Byte1]: 32
1594 23:42:18.920621
1595 23:42:18.923159 Set Vref, RX VrefLevel [Byte0]: 33
1596 23:42:18.926812 [Byte1]: 33
1597 23:42:18.926894
1598 23:42:18.929952 Set Vref, RX VrefLevel [Byte0]: 34
1599 23:42:18.933352 [Byte1]: 34
1600 23:42:18.936794
1601 23:42:18.936874 Set Vref, RX VrefLevel [Byte0]: 35
1602 23:42:18.939809 [Byte1]: 35
1603 23:42:18.944291
1604 23:42:18.944372 Set Vref, RX VrefLevel [Byte0]: 36
1605 23:42:18.947577 [Byte1]: 36
1606 23:42:18.951847
1607 23:42:18.951928 Set Vref, RX VrefLevel [Byte0]: 37
1608 23:42:18.955387 [Byte1]: 37
1609 23:42:18.959518
1610 23:42:18.959599 Set Vref, RX VrefLevel [Byte0]: 38
1611 23:42:18.962889 [Byte1]: 38
1612 23:42:18.967347
1613 23:42:18.967428 Set Vref, RX VrefLevel [Byte0]: 39
1614 23:42:18.970661 [Byte1]: 39
1615 23:42:18.974730
1616 23:42:18.974811 Set Vref, RX VrefLevel [Byte0]: 40
1617 23:42:18.978366 [Byte1]: 40
1618 23:42:18.982577
1619 23:42:18.982658 Set Vref, RX VrefLevel [Byte0]: 41
1620 23:42:18.985625 [Byte1]: 41
1621 23:42:18.990085
1622 23:42:18.990165 Set Vref, RX VrefLevel [Byte0]: 42
1623 23:42:18.993270 [Byte1]: 42
1624 23:42:18.997815
1625 23:42:18.997896 Set Vref, RX VrefLevel [Byte0]: 43
1626 23:42:19.001342 [Byte1]: 43
1627 23:42:19.005642
1628 23:42:19.005723 Set Vref, RX VrefLevel [Byte0]: 44
1629 23:42:19.008799 [Byte1]: 44
1630 23:42:19.013233
1631 23:42:19.013337 Set Vref, RX VrefLevel [Byte0]: 45
1632 23:42:19.016363 [Byte1]: 45
1633 23:42:19.020853
1634 23:42:19.020934 Set Vref, RX VrefLevel [Byte0]: 46
1635 23:42:19.023855 [Byte1]: 46
1636 23:42:19.028412
1637 23:42:19.028492 Set Vref, RX VrefLevel [Byte0]: 47
1638 23:42:19.031597 [Byte1]: 47
1639 23:42:19.035906
1640 23:42:19.035987 Set Vref, RX VrefLevel [Byte0]: 48
1641 23:42:19.039281 [Byte1]: 48
1642 23:42:19.043652
1643 23:42:19.043733 Set Vref, RX VrefLevel [Byte0]: 49
1644 23:42:19.046900 [Byte1]: 49
1645 23:42:19.051212
1646 23:42:19.051293 Set Vref, RX VrefLevel [Byte0]: 50
1647 23:42:19.054666 [Byte1]: 50
1648 23:42:19.059000
1649 23:42:19.059081 Set Vref, RX VrefLevel [Byte0]: 51
1650 23:42:19.062182 [Byte1]: 51
1651 23:42:19.066443
1652 23:42:19.066524 Set Vref, RX VrefLevel [Byte0]: 52
1653 23:42:19.070020 [Byte1]: 52
1654 23:42:19.074329
1655 23:42:19.074410 Set Vref, RX VrefLevel [Byte0]: 53
1656 23:42:19.077787 [Byte1]: 53
1657 23:42:19.082053
1658 23:42:19.082133 Set Vref, RX VrefLevel [Byte0]: 54
1659 23:42:19.085240 [Byte1]: 54
1660 23:42:19.089553
1661 23:42:19.089634 Set Vref, RX VrefLevel [Byte0]: 55
1662 23:42:19.092825 [Byte1]: 55
1663 23:42:19.097499
1664 23:42:19.097581 Set Vref, RX VrefLevel [Byte0]: 56
1665 23:42:19.100442 [Byte1]: 56
1666 23:42:19.105192
1667 23:42:19.105274 Set Vref, RX VrefLevel [Byte0]: 57
1668 23:42:19.108038 [Byte1]: 57
1669 23:42:19.112382
1670 23:42:19.112463 Set Vref, RX VrefLevel [Byte0]: 58
1671 23:42:19.115635 [Byte1]: 58
1672 23:42:19.120472
1673 23:42:19.120553 Set Vref, RX VrefLevel [Byte0]: 59
1674 23:42:19.123374 [Byte1]: 59
1675 23:42:19.127724
1676 23:42:19.127805 Set Vref, RX VrefLevel [Byte0]: 60
1677 23:42:19.131176 [Byte1]: 60
1678 23:42:19.135349
1679 23:42:19.135430 Set Vref, RX VrefLevel [Byte0]: 61
1680 23:42:19.138793 [Byte1]: 61
1681 23:42:19.142937
1682 23:42:19.143018 Set Vref, RX VrefLevel [Byte0]: 62
1683 23:42:19.146507 [Byte1]: 62
1684 23:42:19.150526
1685 23:42:19.150608 Set Vref, RX VrefLevel [Byte0]: 63
1686 23:42:19.153810 [Byte1]: 63
1687 23:42:19.158148
1688 23:42:19.158229 Set Vref, RX VrefLevel [Byte0]: 64
1689 23:42:19.161642 [Byte1]: 64
1690 23:42:19.165817
1691 23:42:19.165898 Set Vref, RX VrefLevel [Byte0]: 65
1692 23:42:19.169377 [Byte1]: 65
1693 23:42:19.173738
1694 23:42:19.173820 Set Vref, RX VrefLevel [Byte0]: 66
1695 23:42:19.177020 [Byte1]: 66
1696 23:42:19.181245
1697 23:42:19.181363 Set Vref, RX VrefLevel [Byte0]: 67
1698 23:42:19.184598 [Byte1]: 67
1699 23:42:19.188961
1700 23:42:19.189042 Set Vref, RX VrefLevel [Byte0]: 68
1701 23:42:19.192028 [Byte1]: 68
1702 23:42:19.196476
1703 23:42:19.196557 Set Vref, RX VrefLevel [Byte0]: 69
1704 23:42:19.199795 [Byte1]: 69
1705 23:42:19.204051
1706 23:42:19.204131 Set Vref, RX VrefLevel [Byte0]: 70
1707 23:42:19.207629 [Byte1]: 70
1708 23:42:19.212035
1709 23:42:19.212116 Set Vref, RX VrefLevel [Byte0]: 71
1710 23:42:19.215008 [Byte1]: 71
1711 23:42:19.219369
1712 23:42:19.219450 Set Vref, RX VrefLevel [Byte0]: 72
1713 23:42:19.222620 [Byte1]: 72
1714 23:42:19.227184
1715 23:42:19.227265 Set Vref, RX VrefLevel [Byte0]: 73
1716 23:42:19.230556 [Byte1]: 73
1717 23:42:19.235164
1718 23:42:19.235245 Set Vref, RX VrefLevel [Byte0]: 74
1719 23:42:19.238431 [Byte1]: 74
1720 23:42:19.242241
1721 23:42:19.242321 Set Vref, RX VrefLevel [Byte0]: 75
1722 23:42:19.245648 [Byte1]: 75
1723 23:42:19.250144
1724 23:42:19.250225 Set Vref, RX VrefLevel [Byte0]: 76
1725 23:42:19.253328 [Byte1]: 76
1726 23:42:19.257826
1727 23:42:19.257907 Set Vref, RX VrefLevel [Byte0]: 77
1728 23:42:19.260976 [Byte1]: 77
1729 23:42:19.265695
1730 23:42:19.265775 Set Vref, RX VrefLevel [Byte0]: 78
1731 23:42:19.268678 [Byte1]: 78
1732 23:42:19.272989
1733 23:42:19.273070 Set Vref, RX VrefLevel [Byte0]: 79
1734 23:42:19.276293 [Byte1]: 79
1735 23:42:19.280551
1736 23:42:19.280631 Final RX Vref Byte 0 = 57 to rank0
1737 23:42:19.284026 Final RX Vref Byte 1 = 54 to rank0
1738 23:42:19.287179 Final RX Vref Byte 0 = 57 to rank1
1739 23:42:19.290536 Final RX Vref Byte 1 = 54 to rank1==
1740 23:42:19.294593 Dram Type= 6, Freq= 0, CH_1, rank 0
1741 23:42:19.298635 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1742 23:42:19.298717 ==
1743 23:42:19.301720 DQS Delay:
1744 23:42:19.301802 DQS0 = 0, DQS1 = 0
1745 23:42:19.301866 DQM Delay:
1746 23:42:19.305065 DQM0 = 81, DQM1 = 74
1747 23:42:19.305146 DQ Delay:
1748 23:42:19.308281 DQ0 =88, DQ1 =72, DQ2 =72, DQ3 =76
1749 23:42:19.311550 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =80
1750 23:42:19.315302 DQ8 =56, DQ9 =64, DQ10 =76, DQ11 =64
1751 23:42:19.318375 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1752 23:42:19.318456
1753 23:42:19.318520
1754 23:42:19.328501 [DQSOSCAuto] RK0, (LSB)MR18= 0x5454, (MSB)MR19= 0x606, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
1755 23:42:19.331436 CH1 RK0: MR19=606, MR18=5454
1756 23:42:19.334807 CH1_RK0: MR19=0x606, MR18=0x5454, DQSOSC=388, MR23=63, INC=98, DEC=65
1757 23:42:19.334889
1758 23:42:19.338160 ----->DramcWriteLeveling(PI) begin...
1759 23:42:19.341669 ==
1760 23:42:19.344742 Dram Type= 6, Freq= 0, CH_1, rank 1
1761 23:42:19.348431 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1762 23:42:19.348513 ==
1763 23:42:19.351549 Write leveling (Byte 0): 25 => 25
1764 23:42:19.354915 Write leveling (Byte 1): 25 => 25
1765 23:42:19.358330 DramcWriteLeveling(PI) end<-----
1766 23:42:19.358411
1767 23:42:19.358476 ==
1768 23:42:19.361406 Dram Type= 6, Freq= 0, CH_1, rank 1
1769 23:42:19.364805 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1770 23:42:19.364894 ==
1771 23:42:19.367955 [Gating] SW mode calibration
1772 23:42:19.374876 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1773 23:42:19.378265 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1774 23:42:19.384735 0 6 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
1775 23:42:19.387892 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1776 23:42:19.391497 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1777 23:42:19.398048 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1778 23:42:19.401237 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1779 23:42:19.405028 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1780 23:42:19.411258 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1781 23:42:19.414638 0 6 28 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
1782 23:42:19.417983 0 7 0 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
1783 23:42:19.424735 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1784 23:42:19.428124 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1785 23:42:19.431514 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1786 23:42:19.438167 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1787 23:42:19.441409 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1788 23:42:19.444532 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1789 23:42:19.451272 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1790 23:42:19.454590 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1791 23:42:19.458090 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1792 23:42:19.464726 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1793 23:42:19.468414 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1794 23:42:19.471342 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1795 23:42:19.474607 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1796 23:42:19.481230 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1797 23:42:19.484523 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1798 23:42:19.487899 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1799 23:42:19.494635 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1800 23:42:19.498204 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1801 23:42:19.501239 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1802 23:42:19.507839 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1803 23:42:19.511423 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1804 23:42:19.514630 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1805 23:42:19.521105 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1806 23:42:19.524859 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1807 23:42:19.527670 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1808 23:42:19.531340 Total UI for P1: 0, mck2ui 16
1809 23:42:19.534290 best dqsien dly found for B0: ( 0, 9, 28)
1810 23:42:19.537995 Total UI for P1: 0, mck2ui 16
1811 23:42:19.541232 best dqsien dly found for B1: ( 0, 10, 0)
1812 23:42:19.544763 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1813 23:42:19.548004 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1814 23:42:19.548100
1815 23:42:19.554950 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1816 23:42:19.557701 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1817 23:42:19.557783 [Gating] SW calibration Done
1818 23:42:19.561494 ==
1819 23:42:19.564316 Dram Type= 6, Freq= 0, CH_1, rank 1
1820 23:42:19.568054 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1821 23:42:19.568136 ==
1822 23:42:19.568200 RX Vref Scan: 0
1823 23:42:19.568260
1824 23:42:19.571158 RX Vref 0 -> 0, step: 1
1825 23:42:19.571240
1826 23:42:19.574368 RX Delay -130 -> 252, step: 16
1827 23:42:19.577594 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1828 23:42:19.581178 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1829 23:42:19.587888 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1830 23:42:19.591224 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1831 23:42:19.594455 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1832 23:42:19.597856 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1833 23:42:19.601368 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1834 23:42:19.604418 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1835 23:42:19.610942 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1836 23:42:19.614461 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1837 23:42:19.617692 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1838 23:42:19.621107 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1839 23:42:19.627821 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1840 23:42:19.631171 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1841 23:42:19.634266 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1842 23:42:19.637701 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1843 23:42:19.637783 ==
1844 23:42:19.641128 Dram Type= 6, Freq= 0, CH_1, rank 1
1845 23:42:19.644428 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1846 23:42:19.647631 ==
1847 23:42:19.647711 DQS Delay:
1848 23:42:19.647776 DQS0 = 0, DQS1 = 0
1849 23:42:19.651031 DQM Delay:
1850 23:42:19.651112 DQM0 = 82, DQM1 = 72
1851 23:42:19.654339 DQ Delay:
1852 23:42:19.654420 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1853 23:42:19.657961 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1854 23:42:19.661054 DQ8 =53, DQ9 =53, DQ10 =69, DQ11 =61
1855 23:42:19.664741 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1856 23:42:19.664821
1857 23:42:19.664885
1858 23:42:19.667687 ==
1859 23:42:19.671195 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 23:42:19.674425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1861 23:42:19.674532 ==
1862 23:42:19.674623
1863 23:42:19.674710
1864 23:42:19.677628 TX Vref Scan disable
1865 23:42:19.677709 == TX Byte 0 ==
1866 23:42:19.681189 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1867 23:42:19.687548 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1868 23:42:19.687630 == TX Byte 1 ==
1869 23:42:19.694919 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1870 23:42:19.697972 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1871 23:42:19.698053 ==
1872 23:42:19.700850 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 23:42:19.704285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1874 23:42:19.704368 ==
1875 23:42:19.717742 TX Vref=22, minBit 0, minWin=28, winSum=451
1876 23:42:19.721076 TX Vref=24, minBit 8, minWin=27, winSum=450
1877 23:42:19.723991 TX Vref=26, minBit 8, minWin=27, winSum=452
1878 23:42:19.727422 TX Vref=28, minBit 8, minWin=27, winSum=455
1879 23:42:19.730894 TX Vref=30, minBit 0, minWin=28, winSum=459
1880 23:42:19.734364 TX Vref=32, minBit 9, minWin=27, winSum=453
1881 23:42:19.740901 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1882 23:42:19.740985
1883 23:42:19.744037 Final TX Range 1 Vref 30
1884 23:42:19.744120
1885 23:42:19.744184 ==
1886 23:42:19.747589 Dram Type= 6, Freq= 0, CH_1, rank 1
1887 23:42:19.750738 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1888 23:42:19.750821 ==
1889 23:42:19.750886
1890 23:42:19.753876
1891 23:42:19.753957 TX Vref Scan disable
1892 23:42:19.757592 == TX Byte 0 ==
1893 23:42:19.761016 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1894 23:42:19.764166 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1895 23:42:19.767249 == TX Byte 1 ==
1896 23:42:19.770694 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1897 23:42:19.774136 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1898 23:42:19.777656
1899 23:42:19.777738 [DATLAT]
1900 23:42:19.777804 Freq=800, CH1 RK1
1901 23:42:19.777864
1902 23:42:19.780963 DATLAT Default: 0x9
1903 23:42:19.781045 0, 0xFFFF, sum = 0
1904 23:42:19.784462 1, 0xFFFF, sum = 0
1905 23:42:19.784545 2, 0xFFFF, sum = 0
1906 23:42:19.787583 3, 0xFFFF, sum = 0
1907 23:42:19.787667 4, 0xFFFF, sum = 0
1908 23:42:19.790707 5, 0xFFFF, sum = 0
1909 23:42:19.790791 6, 0xFFFF, sum = 0
1910 23:42:19.794373 7, 0xFFFF, sum = 0
1911 23:42:19.794456 8, 0x0, sum = 1
1912 23:42:19.797346 9, 0x0, sum = 2
1913 23:42:19.797429 10, 0x0, sum = 3
1914 23:42:19.800750 11, 0x0, sum = 4
1915 23:42:19.800832 best_step = 9
1916 23:42:19.800897
1917 23:42:19.800957 ==
1918 23:42:19.803952 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 23:42:19.810824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1920 23:42:19.810907 ==
1921 23:42:19.810972 RX Vref Scan: 0
1922 23:42:19.811031
1923 23:42:19.813987 RX Vref 0 -> 0, step: 1
1924 23:42:19.814069
1925 23:42:19.817544 RX Delay -111 -> 252, step: 8
1926 23:42:19.821168 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1927 23:42:19.824156 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
1928 23:42:19.827502 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1929 23:42:19.834356 iDelay=217, Bit 3, Center 76 (-39 ~ 192) 232
1930 23:42:19.837541 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1931 23:42:19.840684 iDelay=217, Bit 5, Center 96 (-23 ~ 216) 240
1932 23:42:19.844082 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1933 23:42:19.847577 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
1934 23:42:19.854127 iDelay=217, Bit 8, Center 60 (-55 ~ 176) 232
1935 23:42:19.857646 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1936 23:42:19.860943 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1937 23:42:19.864313 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1938 23:42:19.867404 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1939 23:42:19.874646 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1940 23:42:19.877671 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1941 23:42:19.880862 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1942 23:42:19.880944 ==
1943 23:42:19.884385 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 23:42:19.887489 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1945 23:42:19.887644 ==
1946 23:42:19.890978 DQS Delay:
1947 23:42:19.891060 DQS0 = 0, DQS1 = 0
1948 23:42:19.894169 DQM Delay:
1949 23:42:19.894251 DQM0 = 84, DQM1 = 74
1950 23:42:19.894316 DQ Delay:
1951 23:42:19.897679 DQ0 =84, DQ1 =80, DQ2 =76, DQ3 =76
1952 23:42:19.900899 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
1953 23:42:19.904289 DQ8 =60, DQ9 =60, DQ10 =76, DQ11 =68
1954 23:42:19.907855 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =80
1955 23:42:19.907937
1956 23:42:19.908002
1957 23:42:19.918113 [DQSOSCAuto] RK1, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1958 23:42:19.920910 CH1 RK1: MR19=606, MR18=3838
1959 23:42:19.924624 CH1_RK1: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1960 23:42:19.927812 [RxdqsGatingPostProcess] freq 800
1961 23:42:19.934207 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1962 23:42:19.937555 Pre-setting of DQS Precalculation
1963 23:42:19.941205 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1964 23:42:19.950870 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1965 23:42:19.957969 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1966 23:42:19.958054
1967 23:42:19.958147
1968 23:42:19.960942 [Calibration Summary] 1600 Mbps
1969 23:42:19.961024 CH 0, Rank 0
1970 23:42:19.964218 SW Impedance : PASS
1971 23:42:19.964299 DUTY Scan : NO K
1972 23:42:19.967520 ZQ Calibration : PASS
1973 23:42:19.970858 Jitter Meter : NO K
1974 23:42:19.970940 CBT Training : PASS
1975 23:42:19.974303 Write leveling : PASS
1976 23:42:19.977590 RX DQS gating : PASS
1977 23:42:19.977672 RX DQ/DQS(RDDQC) : PASS
1978 23:42:19.981142 TX DQ/DQS : PASS
1979 23:42:19.981225 RX DATLAT : PASS
1980 23:42:19.984356 RX DQ/DQS(Engine): PASS
1981 23:42:19.987590 TX OE : NO K
1982 23:42:19.987736 All Pass.
1983 23:42:19.987806
1984 23:42:19.987867 CH 0, Rank 1
1985 23:42:19.991183 SW Impedance : PASS
1986 23:42:19.994575 DUTY Scan : NO K
1987 23:42:19.994657 ZQ Calibration : PASS
1988 23:42:19.997670 Jitter Meter : NO K
1989 23:42:20.001065 CBT Training : PASS
1990 23:42:20.001147 Write leveling : PASS
1991 23:42:20.004250 RX DQS gating : PASS
1992 23:42:20.007624 RX DQ/DQS(RDDQC) : PASS
1993 23:42:20.007706 TX DQ/DQS : PASS
1994 23:42:20.011023 RX DATLAT : PASS
1995 23:42:20.014664 RX DQ/DQS(Engine): PASS
1996 23:42:20.014746 TX OE : NO K
1997 23:42:20.014811 All Pass.
1998 23:42:20.017709
1999 23:42:20.017790 CH 1, Rank 0
2000 23:42:20.021132 SW Impedance : PASS
2001 23:42:20.021214 DUTY Scan : NO K
2002 23:42:20.024434 ZQ Calibration : PASS
2003 23:42:20.024516 Jitter Meter : NO K
2004 23:42:20.027850 CBT Training : PASS
2005 23:42:20.031133 Write leveling : PASS
2006 23:42:20.031215 RX DQS gating : PASS
2007 23:42:20.034458 RX DQ/DQS(RDDQC) : PASS
2008 23:42:20.037631 TX DQ/DQS : PASS
2009 23:42:20.037713 RX DATLAT : PASS
2010 23:42:20.041056 RX DQ/DQS(Engine): PASS
2011 23:42:20.044119 TX OE : NO K
2012 23:42:20.044201 All Pass.
2013 23:42:20.044266
2014 23:42:20.044325 CH 1, Rank 1
2015 23:42:20.047760 SW Impedance : PASS
2016 23:42:20.050978 DUTY Scan : NO K
2017 23:42:20.051060 ZQ Calibration : PASS
2018 23:42:20.054256 Jitter Meter : NO K
2019 23:42:20.057223 CBT Training : PASS
2020 23:42:20.057310 Write leveling : PASS
2021 23:42:20.061024 RX DQS gating : PASS
2022 23:42:20.064519 RX DQ/DQS(RDDQC) : PASS
2023 23:42:20.064602 TX DQ/DQS : PASS
2024 23:42:20.067622 RX DATLAT : PASS
2025 23:42:20.071342 RX DQ/DQS(Engine): PASS
2026 23:42:20.071424 TX OE : NO K
2027 23:42:20.071489 All Pass.
2028 23:42:20.074248
2029 23:42:20.074329 DramC Write-DBI off
2030 23:42:20.077486 PER_BANK_REFRESH: Hybrid Mode
2031 23:42:20.077568 TX_TRACKING: ON
2032 23:42:20.080944 [GetDramInforAfterCalByMRR] Vendor 6.
2033 23:42:20.083978 [GetDramInforAfterCalByMRR] Revision 606.
2034 23:42:20.090577 [GetDramInforAfterCalByMRR] Revision 2 0.
2035 23:42:20.090659 MR0 0x3939
2036 23:42:20.090724 MR8 0x1111
2037 23:42:20.094163 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
2038 23:42:20.094245
2039 23:42:20.097153 MR0 0x3939
2040 23:42:20.097235 MR8 0x1111
2041 23:42:20.100703 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
2042 23:42:20.100785
2043 23:42:20.110687 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2044 23:42:20.113818 [FAST_K] Save calibration result to emmc
2045 23:42:20.117665 [FAST_K] Save calibration result to emmc
2046 23:42:20.120448 dram_init: config_dvfs: 1
2047 23:42:20.123804 dramc_set_vcore_voltage set vcore to 662500
2048 23:42:20.127087 Read voltage for 1200, 2
2049 23:42:20.127169 Vio18 = 0
2050 23:42:20.127233 Vcore = 662500
2051 23:42:20.130782 Vdram = 0
2052 23:42:20.130863 Vddq = 0
2053 23:42:20.130928 Vmddr = 0
2054 23:42:20.137064 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2055 23:42:20.140468 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2056 23:42:20.143753 MEM_TYPE=3, freq_sel=15
2057 23:42:20.146940 sv_algorithm_assistance_LP4_1600
2058 23:42:20.150410 ============ PULL DRAM RESETB DOWN ============
2059 23:42:20.154173 ========== PULL DRAM RESETB DOWN end =========
2060 23:42:20.160422 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2061 23:42:20.163810 ===================================
2062 23:42:20.163892 LPDDR4 DRAM CONFIGURATION
2063 23:42:20.167261 ===================================
2064 23:42:20.170284 EX_ROW_EN[0] = 0x0
2065 23:42:20.173639 EX_ROW_EN[1] = 0x0
2066 23:42:20.173721 LP4Y_EN = 0x0
2067 23:42:20.176815 WORK_FSP = 0x0
2068 23:42:20.176897 WL = 0x4
2069 23:42:20.180441 RL = 0x4
2070 23:42:20.180523 BL = 0x2
2071 23:42:20.183629 RPST = 0x0
2072 23:42:20.183711 RD_PRE = 0x0
2073 23:42:20.186676 WR_PRE = 0x1
2074 23:42:20.186760 WR_PST = 0x0
2075 23:42:20.189994 DBI_WR = 0x0
2076 23:42:20.190075 DBI_RD = 0x0
2077 23:42:20.193446 OTF = 0x1
2078 23:42:20.196655 ===================================
2079 23:42:20.199942 ===================================
2080 23:42:20.200023 ANA top config
2081 23:42:20.203307 ===================================
2082 23:42:20.206797 DLL_ASYNC_EN = 0
2083 23:42:20.210190 ALL_SLAVE_EN = 0
2084 23:42:20.213338 NEW_RANK_MODE = 1
2085 23:42:20.213421 DLL_IDLE_MODE = 1
2086 23:42:20.216824 LP45_APHY_COMB_EN = 1
2087 23:42:20.219688 TX_ODT_DIS = 1
2088 23:42:20.223218 NEW_8X_MODE = 1
2089 23:42:20.227003 ===================================
2090 23:42:20.229704 ===================================
2091 23:42:20.233117 data_rate = 2400
2092 23:42:20.233198 CKR = 1
2093 23:42:20.236455 DQ_P2S_RATIO = 8
2094 23:42:20.240091 ===================================
2095 23:42:20.243317 CA_P2S_RATIO = 8
2096 23:42:20.246621 DQ_CA_OPEN = 0
2097 23:42:20.249747 DQ_SEMI_OPEN = 0
2098 23:42:20.253163 CA_SEMI_OPEN = 0
2099 23:42:20.253245 CA_FULL_RATE = 0
2100 23:42:20.256986 DQ_CKDIV4_EN = 0
2101 23:42:20.259949 CA_CKDIV4_EN = 0
2102 23:42:20.263098 CA_PREDIV_EN = 0
2103 23:42:20.266221 PH8_DLY = 17
2104 23:42:20.269702 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2105 23:42:20.269784 DQ_AAMCK_DIV = 4
2106 23:42:20.273117 CA_AAMCK_DIV = 4
2107 23:42:20.276443 CA_ADMCK_DIV = 4
2108 23:42:20.279648 DQ_TRACK_CA_EN = 0
2109 23:42:20.282843 CA_PICK = 1200
2110 23:42:20.286204 CA_MCKIO = 1200
2111 23:42:20.286286 MCKIO_SEMI = 0
2112 23:42:20.289462 PLL_FREQ = 2366
2113 23:42:20.293070 DQ_UI_PI_RATIO = 32
2114 23:42:20.296534 CA_UI_PI_RATIO = 0
2115 23:42:20.299656 ===================================
2116 23:42:20.303138 ===================================
2117 23:42:20.306167 memory_type:LPDDR4
2118 23:42:20.306249 GP_NUM : 10
2119 23:42:20.309415 SRAM_EN : 1
2120 23:42:20.312668 MD32_EN : 0
2121 23:42:20.316224 ===================================
2122 23:42:20.316306 [ANA_INIT] >>>>>>>>>>>>>>
2123 23:42:20.319703 <<<<<< [CONFIGURE PHASE]: ANA_TX
2124 23:42:20.322913 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2125 23:42:20.325970 ===================================
2126 23:42:20.329671 data_rate = 2400,PCW = 0X5b00
2127 23:42:20.332655 ===================================
2128 23:42:20.335947 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2129 23:42:20.342772 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2130 23:42:20.346453 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2131 23:42:20.352785 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2132 23:42:20.356243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2133 23:42:20.359803 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2134 23:42:20.359886 [ANA_INIT] flow start
2135 23:42:20.363044 [ANA_INIT] PLL >>>>>>>>
2136 23:42:20.366243 [ANA_INIT] PLL <<<<<<<<
2137 23:42:20.366323 [ANA_INIT] MIDPI >>>>>>>>
2138 23:42:20.369703 [ANA_INIT] MIDPI <<<<<<<<
2139 23:42:20.373037 [ANA_INIT] DLL >>>>>>>>
2140 23:42:20.376140 [ANA_INIT] DLL <<<<<<<<
2141 23:42:20.376221 [ANA_INIT] flow end
2142 23:42:20.379439 ============ LP4 DIFF to SE enter ============
2143 23:42:20.386323 ============ LP4 DIFF to SE exit ============
2144 23:42:20.386408 [ANA_INIT] <<<<<<<<<<<<<
2145 23:42:20.389250 [Flow] Enable top DCM control >>>>>
2146 23:42:20.392821 [Flow] Enable top DCM control <<<<<
2147 23:42:20.396114 Enable DLL master slave shuffle
2148 23:42:20.402855 ==============================================================
2149 23:42:20.402940 Gating Mode config
2150 23:42:20.409451 ==============================================================
2151 23:42:20.412880 Config description:
2152 23:42:20.419503 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2153 23:42:20.426218 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2154 23:42:20.432765 SELPH_MODE 0: By rank 1: By Phase
2155 23:42:20.439349 ==============================================================
2156 23:42:20.439434 GAT_TRACK_EN = 1
2157 23:42:20.443080 RX_GATING_MODE = 2
2158 23:42:20.445984 RX_GATING_TRACK_MODE = 2
2159 23:42:20.449346 SELPH_MODE = 1
2160 23:42:20.453199 PICG_EARLY_EN = 1
2161 23:42:20.455957 VALID_LAT_VALUE = 1
2162 23:42:20.462909 ==============================================================
2163 23:42:20.466026 Enter into Gating configuration >>>>
2164 23:42:20.469339 Exit from Gating configuration <<<<
2165 23:42:20.473008 Enter into DVFS_PRE_config >>>>>
2166 23:42:20.483066 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2167 23:42:20.486225 Exit from DVFS_PRE_config <<<<<
2168 23:42:20.489671 Enter into PICG configuration >>>>
2169 23:42:20.492725 Exit from PICG configuration <<<<
2170 23:42:20.496455 [RX_INPUT] configuration >>>>>
2171 23:42:20.496540 [RX_INPUT] configuration <<<<<
2172 23:42:20.502698 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2173 23:42:20.509705 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2174 23:42:20.512695 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2175 23:42:20.519408 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2176 23:42:20.526327 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2177 23:42:20.533043 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2178 23:42:20.536330 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2179 23:42:20.539461 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2180 23:42:20.546288 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2181 23:42:20.549510 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2182 23:42:20.552927 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2183 23:42:20.556199 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2184 23:42:20.559382 ===================================
2185 23:42:20.562967 LPDDR4 DRAM CONFIGURATION
2186 23:42:20.566367 ===================================
2187 23:42:20.569713 EX_ROW_EN[0] = 0x0
2188 23:42:20.569797 EX_ROW_EN[1] = 0x0
2189 23:42:20.573011 LP4Y_EN = 0x0
2190 23:42:20.573116 WORK_FSP = 0x0
2191 23:42:20.576498 WL = 0x4
2192 23:42:20.576584 RL = 0x4
2193 23:42:20.579491 BL = 0x2
2194 23:42:20.579576 RPST = 0x0
2195 23:42:20.582716 RD_PRE = 0x0
2196 23:42:20.582801 WR_PRE = 0x1
2197 23:42:20.586114 WR_PST = 0x0
2198 23:42:20.586198 DBI_WR = 0x0
2199 23:42:20.589693 DBI_RD = 0x0
2200 23:42:20.593123 OTF = 0x1
2201 23:42:20.596165 ===================================
2202 23:42:20.599358 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2203 23:42:20.603089 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2204 23:42:20.606131 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2205 23:42:20.609623 ===================================
2206 23:42:20.612871 LPDDR4 DRAM CONFIGURATION
2207 23:42:20.616079 ===================================
2208 23:42:20.619403 EX_ROW_EN[0] = 0x10
2209 23:42:20.619488 EX_ROW_EN[1] = 0x0
2210 23:42:20.622646 LP4Y_EN = 0x0
2211 23:42:20.622730 WORK_FSP = 0x0
2212 23:42:20.625891 WL = 0x4
2213 23:42:20.625976 RL = 0x4
2214 23:42:20.629697 BL = 0x2
2215 23:42:20.629781 RPST = 0x0
2216 23:42:20.633010 RD_PRE = 0x0
2217 23:42:20.633094 WR_PRE = 0x1
2218 23:42:20.636116 WR_PST = 0x0
2219 23:42:20.636225 DBI_WR = 0x0
2220 23:42:20.639521 DBI_RD = 0x0
2221 23:42:20.639606 OTF = 0x1
2222 23:42:20.642857 ===================================
2223 23:42:20.649298 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2224 23:42:20.649383 ==
2225 23:42:20.652617 Dram Type= 6, Freq= 0, CH_0, rank 0
2226 23:42:20.659493 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2227 23:42:20.659574 ==
2228 23:42:20.659639 [Duty_Offset_Calibration]
2229 23:42:20.662636 B0:0 B1:2 CA:1
2230 23:42:20.662715
2231 23:42:20.666249 [DutyScan_Calibration_Flow] k_type=0
2232 23:42:20.674613
2233 23:42:20.674713 ==CLK 0==
2234 23:42:20.677957 Final CLK duty delay cell = 0
2235 23:42:20.681227 [0] MAX Duty = 5093%(X100), DQS PI = 12
2236 23:42:20.684638 [0] MIN Duty = 4938%(X100), DQS PI = 52
2237 23:42:20.684714 [0] AVG Duty = 5015%(X100)
2238 23:42:20.687950
2239 23:42:20.691532 CH0 CLK Duty spec in!! Max-Min= 155%
2240 23:42:20.694815 [DutyScan_Calibration_Flow] ====Done====
2241 23:42:20.694890
2242 23:42:20.697984 [DutyScan_Calibration_Flow] k_type=1
2243 23:42:20.713957
2244 23:42:20.714035 ==DQS 0 ==
2245 23:42:20.717494 Final DQS duty delay cell = 0
2246 23:42:20.720755 [0] MAX Duty = 5124%(X100), DQS PI = 50
2247 23:42:20.724239 [0] MIN Duty = 5031%(X100), DQS PI = 6
2248 23:42:20.724315 [0] AVG Duty = 5077%(X100)
2249 23:42:20.727578
2250 23:42:20.727650 ==DQS 1 ==
2251 23:42:20.730940 Final DQS duty delay cell = 0
2252 23:42:20.734078 [0] MAX Duty = 5031%(X100), DQS PI = 52
2253 23:42:20.737275 [0] MIN Duty = 4906%(X100), DQS PI = 16
2254 23:42:20.737390 [0] AVG Duty = 4968%(X100)
2255 23:42:20.740731
2256 23:42:20.744036 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2257 23:42:20.744112
2258 23:42:20.747495 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2259 23:42:20.750779 [DutyScan_Calibration_Flow] ====Done====
2260 23:42:20.750851
2261 23:42:20.754280 [DutyScan_Calibration_Flow] k_type=3
2262 23:42:20.771346
2263 23:42:20.771432 ==DQM 0 ==
2264 23:42:20.774655 Final DQM duty delay cell = 0
2265 23:42:20.777626 [0] MAX Duty = 5156%(X100), DQS PI = 22
2266 23:42:20.780950 [0] MIN Duty = 4969%(X100), DQS PI = 42
2267 23:42:20.784374 [0] AVG Duty = 5062%(X100)
2268 23:42:20.784452
2269 23:42:20.784515 ==DQM 1 ==
2270 23:42:20.787945 Final DQM duty delay cell = 4
2271 23:42:20.790959 [4] MAX Duty = 5187%(X100), DQS PI = 54
2272 23:42:20.794619 [4] MIN Duty = 5000%(X100), DQS PI = 16
2273 23:42:20.797737 [4] AVG Duty = 5093%(X100)
2274 23:42:20.797813
2275 23:42:20.800859 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2276 23:42:20.800930
2277 23:42:20.804190 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2278 23:42:20.807362 [DutyScan_Calibration_Flow] ====Done====
2279 23:42:20.807433
2280 23:42:20.810645 [DutyScan_Calibration_Flow] k_type=2
2281 23:42:20.826279
2282 23:42:20.826406 ==DQ 0 ==
2283 23:42:20.829907 Final DQ duty delay cell = -4
2284 23:42:20.832780 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2285 23:42:20.836046 [-4] MIN Duty = 4813%(X100), DQS PI = 44
2286 23:42:20.839658 [-4] AVG Duty = 4937%(X100)
2287 23:42:20.839760
2288 23:42:20.839850 ==DQ 1 ==
2289 23:42:20.842946 Final DQ duty delay cell = -4
2290 23:42:20.846154 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2291 23:42:20.849484 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2292 23:42:20.852683 [-4] AVG Duty = 4984%(X100)
2293 23:42:20.852773
2294 23:42:20.856169 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2295 23:42:20.856269
2296 23:42:20.859121 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2297 23:42:20.862832 [DutyScan_Calibration_Flow] ====Done====
2298 23:42:20.862940 ==
2299 23:42:20.865975 Dram Type= 6, Freq= 0, CH_1, rank 0
2300 23:42:20.869189 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2301 23:42:20.869298 ==
2302 23:42:20.872841 [Duty_Offset_Calibration]
2303 23:42:20.872947 B0:0 B1:5 CA:-5
2304 23:42:20.873038
2305 23:42:20.876120 [DutyScan_Calibration_Flow] k_type=0
2306 23:42:20.886689
2307 23:42:20.886793 ==CLK 0==
2308 23:42:20.890367 Final CLK duty delay cell = 0
2309 23:42:20.893138 [0] MAX Duty = 5094%(X100), DQS PI = 24
2310 23:42:20.896709 [0] MIN Duty = 4907%(X100), DQS PI = 42
2311 23:42:20.896794 [0] AVG Duty = 5000%(X100)
2312 23:42:20.900151
2313 23:42:20.903256 CH1 CLK Duty spec in!! Max-Min= 187%
2314 23:42:20.906895 [DutyScan_Calibration_Flow] ====Done====
2315 23:42:20.906996
2316 23:42:20.909913 [DutyScan_Calibration_Flow] k_type=1
2317 23:42:20.925167
2318 23:42:20.925251 ==DQS 0 ==
2319 23:42:20.928388 Final DQS duty delay cell = 0
2320 23:42:20.931937 [0] MAX Duty = 5125%(X100), DQS PI = 16
2321 23:42:20.935164 [0] MIN Duty = 4875%(X100), DQS PI = 40
2322 23:42:20.938480 [0] AVG Duty = 5000%(X100)
2323 23:42:20.938582
2324 23:42:20.938673 ==DQS 1 ==
2325 23:42:20.941740 Final DQS duty delay cell = -4
2326 23:42:20.945215 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2327 23:42:20.948868 [-4] MIN Duty = 4907%(X100), DQS PI = 56
2328 23:42:20.952052 [-4] AVG Duty = 4953%(X100)
2329 23:42:20.952153
2330 23:42:20.955140 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2331 23:42:20.955212
2332 23:42:20.958708 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2333 23:42:20.961890 [DutyScan_Calibration_Flow] ====Done====
2334 23:42:20.961965
2335 23:42:20.965185 [DutyScan_Calibration_Flow] k_type=3
2336 23:42:20.980508
2337 23:42:20.980616 ==DQM 0 ==
2338 23:42:20.983757 Final DQM duty delay cell = -4
2339 23:42:20.986907 [-4] MAX Duty = 5094%(X100), DQS PI = 30
2340 23:42:20.990504 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2341 23:42:20.993623 [-4] AVG Duty = 4969%(X100)
2342 23:42:20.993699
2343 23:42:20.993762 ==DQM 1 ==
2344 23:42:20.996951 Final DQM duty delay cell = -4
2345 23:42:21.000484 [-4] MAX Duty = 5094%(X100), DQS PI = 22
2346 23:42:21.003810 [-4] MIN Duty = 4906%(X100), DQS PI = 42
2347 23:42:21.007043 [-4] AVG Duty = 5000%(X100)
2348 23:42:21.007139
2349 23:42:21.010623 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2350 23:42:21.010696
2351 23:42:21.013837 CH1 DQM 1 Duty spec in!! Max-Min= 188%
2352 23:42:21.016870 [DutyScan_Calibration_Flow] ====Done====
2353 23:42:21.016967
2354 23:42:21.020427 [DutyScan_Calibration_Flow] k_type=2
2355 23:42:21.037882
2356 23:42:21.037959 ==DQ 0 ==
2357 23:42:21.041220 Final DQ duty delay cell = 0
2358 23:42:21.044458 [0] MAX Duty = 5062%(X100), DQS PI = 0
2359 23:42:21.047773 [0] MIN Duty = 4938%(X100), DQS PI = 44
2360 23:42:21.047871 [0] AVG Duty = 5000%(X100)
2361 23:42:21.047961
2362 23:42:21.051303 ==DQ 1 ==
2363 23:42:21.054556 Final DQ duty delay cell = 0
2364 23:42:21.057575 [0] MAX Duty = 5031%(X100), DQS PI = 8
2365 23:42:21.060948 [0] MIN Duty = 4907%(X100), DQS PI = 0
2366 23:42:21.061018 [0] AVG Duty = 4969%(X100)
2367 23:42:21.061082
2368 23:42:21.064240 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2369 23:42:21.064314
2370 23:42:21.067823 CH1 DQ 1 Duty spec in!! Max-Min= 124%
2371 23:42:21.074262 [DutyScan_Calibration_Flow] ====Done====
2372 23:42:21.077554 nWR fixed to 30
2373 23:42:21.077658 [ModeRegInit_LP4] CH0 RK0
2374 23:42:21.080741 [ModeRegInit_LP4] CH0 RK1
2375 23:42:21.084081 [ModeRegInit_LP4] CH1 RK0
2376 23:42:21.084180 [ModeRegInit_LP4] CH1 RK1
2377 23:42:21.087544 match AC timing 6
2378 23:42:21.090933 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2379 23:42:21.094357 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2380 23:42:21.100683 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2381 23:42:21.104267 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2382 23:42:21.110715 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2383 23:42:21.110794 ==
2384 23:42:21.113945 Dram Type= 6, Freq= 0, CH_0, rank 0
2385 23:42:21.117531 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2386 23:42:21.117603 ==
2387 23:42:21.124147 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2388 23:42:21.127518 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2389 23:42:21.137304 [CA 0] Center 39 (9~70) winsize 62
2390 23:42:21.140668 [CA 1] Center 39 (8~70) winsize 63
2391 23:42:21.143795 [CA 2] Center 36 (5~67) winsize 63
2392 23:42:21.147284 [CA 3] Center 35 (4~66) winsize 63
2393 23:42:21.150410 [CA 4] Center 34 (3~65) winsize 63
2394 23:42:21.153995 [CA 5] Center 33 (3~64) winsize 62
2395 23:42:21.154061
2396 23:42:21.157046 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2397 23:42:21.157113
2398 23:42:21.160599 [CATrainingPosCal] consider 1 rank data
2399 23:42:21.163697 u2DelayCellTimex100 = 270/100 ps
2400 23:42:21.167235 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2401 23:42:21.174067 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2402 23:42:21.176963 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2403 23:42:21.180255 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2404 23:42:21.183998 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2405 23:42:21.187432 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2406 23:42:21.187533
2407 23:42:21.190575 CA PerBit enable=1, Macro0, CA PI delay=33
2408 23:42:21.190648
2409 23:42:21.193713 [CBTSetCACLKResult] CA Dly = 33
2410 23:42:21.193798 CS Dly: 7 (0~38)
2411 23:42:21.196928 ==
2412 23:42:21.196999 Dram Type= 6, Freq= 0, CH_0, rank 1
2413 23:42:21.203715 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2414 23:42:21.203800 ==
2415 23:42:21.207464 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2416 23:42:21.213608 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2417 23:42:21.222968 [CA 0] Center 39 (9~70) winsize 62
2418 23:42:21.225998 [CA 1] Center 39 (8~70) winsize 63
2419 23:42:21.229579 [CA 2] Center 36 (5~67) winsize 63
2420 23:42:21.232551 [CA 3] Center 35 (4~66) winsize 63
2421 23:42:21.236403 [CA 4] Center 33 (3~64) winsize 62
2422 23:42:21.239164 [CA 5] Center 33 (3~64) winsize 62
2423 23:42:21.239264
2424 23:42:21.242612 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2425 23:42:21.242707
2426 23:42:21.245899 [CATrainingPosCal] consider 2 rank data
2427 23:42:21.249579 u2DelayCellTimex100 = 270/100 ps
2428 23:42:21.252723 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2429 23:42:21.256007 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2430 23:42:21.262749 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2431 23:42:21.265867 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2432 23:42:21.269359 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2433 23:42:21.272545 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2434 23:42:21.272648
2435 23:42:21.276047 CA PerBit enable=1, Macro0, CA PI delay=33
2436 23:42:21.276148
2437 23:42:21.279345 [CBTSetCACLKResult] CA Dly = 33
2438 23:42:21.279427 CS Dly: 7 (0~39)
2439 23:42:21.282542
2440 23:42:21.285795 ----->DramcWriteLeveling(PI) begin...
2441 23:42:21.285878 ==
2442 23:42:21.289221 Dram Type= 6, Freq= 0, CH_0, rank 0
2443 23:42:21.292425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2444 23:42:21.292507 ==
2445 23:42:21.296042 Write leveling (Byte 0): 27 => 27
2446 23:42:21.298967 Write leveling (Byte 1): 27 => 27
2447 23:42:21.302690 DramcWriteLeveling(PI) end<-----
2448 23:42:21.302771
2449 23:42:21.302835 ==
2450 23:42:21.305962 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 23:42:21.309072 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2452 23:42:21.309154 ==
2453 23:42:21.312496 [Gating] SW mode calibration
2454 23:42:21.319029 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2455 23:42:21.325736 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2456 23:42:21.328959 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2457 23:42:21.332473 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2458 23:42:21.338896 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2459 23:42:21.342257 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2460 23:42:21.345656 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2461 23:42:21.349224 0 11 20 | B1->B0 | 2d2d 2c2c | 0 0 | (0 1) (0 1)
2462 23:42:21.355827 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2463 23:42:21.358916 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2464 23:42:21.362877 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2465 23:42:21.369093 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2466 23:42:21.372267 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2467 23:42:21.375480 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2468 23:42:21.382399 0 12 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2469 23:42:21.385723 0 12 20 | B1->B0 | 3535 3b3b | 1 0 | (1 1) (0 0)
2470 23:42:21.388918 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2471 23:42:21.395442 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2472 23:42:21.399051 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2473 23:42:21.402481 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2474 23:42:21.409145 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2475 23:42:21.412232 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2476 23:42:21.415607 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2477 23:42:21.422473 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2478 23:42:21.425607 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2479 23:42:21.428900 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2480 23:42:21.435527 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2481 23:42:21.438870 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2482 23:42:21.442017 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2483 23:42:21.448683 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2484 23:42:21.452173 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2485 23:42:21.455324 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2486 23:42:21.462135 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2487 23:42:21.465538 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2488 23:42:21.468869 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2489 23:42:21.472218 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2490 23:42:21.478743 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2491 23:42:21.482023 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2492 23:42:21.485511 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2493 23:42:21.492346 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2494 23:42:21.495425 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2495 23:42:21.498620 Total UI for P1: 0, mck2ui 16
2496 23:42:21.502143 best dqsien dly found for B0: ( 0, 15, 20)
2497 23:42:21.505233 Total UI for P1: 0, mck2ui 16
2498 23:42:21.508839 best dqsien dly found for B1: ( 0, 15, 20)
2499 23:42:21.511980 best DQS0 dly(MCK, UI, PI) = (0, 15, 20)
2500 23:42:21.515271 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2501 23:42:21.515356
2502 23:42:21.518590 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 20)
2503 23:42:21.522082 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2504 23:42:21.525492 [Gating] SW calibration Done
2505 23:42:21.525577 ==
2506 23:42:21.528912 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 23:42:21.535418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2508 23:42:21.535504 ==
2509 23:42:21.535590 RX Vref Scan: 0
2510 23:42:21.535671
2511 23:42:21.539185 RX Vref 0 -> 0, step: 1
2512 23:42:21.539269
2513 23:42:21.541965 RX Delay -40 -> 252, step: 8
2514 23:42:21.545566 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2515 23:42:21.548835 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2516 23:42:21.552096 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2517 23:42:21.555400 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
2518 23:42:21.561947 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2519 23:42:21.565137 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2520 23:42:21.568847 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2521 23:42:21.572035 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2522 23:42:21.575416 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2523 23:42:21.582244 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2524 23:42:21.585274 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2525 23:42:21.588901 iDelay=200, Bit 11, Center 103 (40 ~ 167) 128
2526 23:42:21.591941 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2527 23:42:21.595266 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2528 23:42:21.602382 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2529 23:42:21.605031 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2530 23:42:21.605102 ==
2531 23:42:21.608345 Dram Type= 6, Freq= 0, CH_0, rank 0
2532 23:42:21.611850 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2533 23:42:21.611921 ==
2534 23:42:21.615195 DQS Delay:
2535 23:42:21.615264 DQS0 = 0, DQS1 = 0
2536 23:42:21.615323 DQM Delay:
2537 23:42:21.618610 DQM0 = 115, DQM1 = 106
2538 23:42:21.618675 DQ Delay:
2539 23:42:21.621870 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =111
2540 23:42:21.625563 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2541 23:42:21.628505 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =103
2542 23:42:21.635039 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2543 23:42:21.635121
2544 23:42:21.635184
2545 23:42:21.635243 ==
2546 23:42:21.638624 Dram Type= 6, Freq= 0, CH_0, rank 0
2547 23:42:21.641880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2548 23:42:21.641961 ==
2549 23:42:21.642025
2550 23:42:21.642083
2551 23:42:21.645683 TX Vref Scan disable
2552 23:42:21.645763 == TX Byte 0 ==
2553 23:42:21.651811 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2554 23:42:21.655193 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2555 23:42:21.655273 == TX Byte 1 ==
2556 23:42:21.661688 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2557 23:42:21.665013 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2558 23:42:21.665087 ==
2559 23:42:21.668715 Dram Type= 6, Freq= 0, CH_0, rank 0
2560 23:42:21.671589 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2561 23:42:21.671692 ==
2562 23:42:21.684016 TX Vref=22, minBit 5, minWin=25, winSum=411
2563 23:42:21.687543 TX Vref=24, minBit 4, minWin=25, winSum=420
2564 23:42:21.690577 TX Vref=26, minBit 8, minWin=25, winSum=427
2565 23:42:21.694101 TX Vref=28, minBit 9, minWin=26, winSum=429
2566 23:42:21.697684 TX Vref=30, minBit 9, minWin=26, winSum=437
2567 23:42:21.704074 TX Vref=32, minBit 10, minWin=26, winSum=437
2568 23:42:21.707315 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 30
2569 23:42:21.707396
2570 23:42:21.710654 Final TX Range 1 Vref 30
2571 23:42:21.710734
2572 23:42:21.710797 ==
2573 23:42:21.714039 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 23:42:21.717407 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2575 23:42:21.717488 ==
2576 23:42:21.720569
2577 23:42:21.720649
2578 23:42:21.720713 TX Vref Scan disable
2579 23:42:21.724052 == TX Byte 0 ==
2580 23:42:21.727348 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2581 23:42:21.730526 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2582 23:42:21.733963 == TX Byte 1 ==
2583 23:42:21.737238 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2584 23:42:21.740996 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2585 23:42:21.741071
2586 23:42:21.743818 [DATLAT]
2587 23:42:21.743919 Freq=1200, CH0 RK0
2588 23:42:21.744008
2589 23:42:21.747223 DATLAT Default: 0xd
2590 23:42:21.747291 0, 0xFFFF, sum = 0
2591 23:42:21.750892 1, 0xFFFF, sum = 0
2592 23:42:21.750963 2, 0xFFFF, sum = 0
2593 23:42:21.754240 3, 0xFFFF, sum = 0
2594 23:42:21.754311 4, 0xFFFF, sum = 0
2595 23:42:21.757158 5, 0xFFFF, sum = 0
2596 23:42:21.757254 6, 0xFFFF, sum = 0
2597 23:42:21.760651 7, 0xFFFF, sum = 0
2598 23:42:21.763798 8, 0xFFFF, sum = 0
2599 23:42:21.763868 9, 0xFFFF, sum = 0
2600 23:42:21.767387 10, 0xFFFF, sum = 0
2601 23:42:21.767468 11, 0x0, sum = 1
2602 23:42:21.770834 12, 0x0, sum = 2
2603 23:42:21.770916 13, 0x0, sum = 3
2604 23:42:21.770981 14, 0x0, sum = 4
2605 23:42:21.774047 best_step = 12
2606 23:42:21.774127
2607 23:42:21.774190 ==
2608 23:42:21.777454 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 23:42:21.781036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2610 23:42:21.781142 ==
2611 23:42:21.784330 RX Vref Scan: 1
2612 23:42:21.784435
2613 23:42:21.784527 Set Vref Range= 32 -> 127
2614 23:42:21.784589
2615 23:42:21.787562 RX Vref 32 -> 127, step: 1
2616 23:42:21.787657
2617 23:42:21.790680 RX Delay -21 -> 252, step: 4
2618 23:42:21.790765
2619 23:42:21.794006 Set Vref, RX VrefLevel [Byte0]: 32
2620 23:42:21.797584 [Byte1]: 32
2621 23:42:21.797654
2622 23:42:21.800737 Set Vref, RX VrefLevel [Byte0]: 33
2623 23:42:21.803868 [Byte1]: 33
2624 23:42:21.808437
2625 23:42:21.808507 Set Vref, RX VrefLevel [Byte0]: 34
2626 23:42:21.811816 [Byte1]: 34
2627 23:42:21.816353
2628 23:42:21.816425 Set Vref, RX VrefLevel [Byte0]: 35
2629 23:42:21.819541 [Byte1]: 35
2630 23:42:21.824148
2631 23:42:21.824228 Set Vref, RX VrefLevel [Byte0]: 36
2632 23:42:21.827819 [Byte1]: 36
2633 23:42:21.832217
2634 23:42:21.832298 Set Vref, RX VrefLevel [Byte0]: 37
2635 23:42:21.835729 [Byte1]: 37
2636 23:42:21.840361
2637 23:42:21.840442 Set Vref, RX VrefLevel [Byte0]: 38
2638 23:42:21.843415 [Byte1]: 38
2639 23:42:21.848323
2640 23:42:21.848403 Set Vref, RX VrefLevel [Byte0]: 39
2641 23:42:21.851535 [Byte1]: 39
2642 23:42:21.855909
2643 23:42:21.855989 Set Vref, RX VrefLevel [Byte0]: 40
2644 23:42:21.859468 [Byte1]: 40
2645 23:42:21.864036
2646 23:42:21.864116 Set Vref, RX VrefLevel [Byte0]: 41
2647 23:42:21.867050 [Byte1]: 41
2648 23:42:21.871801
2649 23:42:21.871881 Set Vref, RX VrefLevel [Byte0]: 42
2650 23:42:21.875382 [Byte1]: 42
2651 23:42:21.879643
2652 23:42:21.879723 Set Vref, RX VrefLevel [Byte0]: 43
2653 23:42:21.883209 [Byte1]: 43
2654 23:42:21.887975
2655 23:42:21.888055 Set Vref, RX VrefLevel [Byte0]: 44
2656 23:42:21.891241 [Byte1]: 44
2657 23:42:21.896014
2658 23:42:21.896094 Set Vref, RX VrefLevel [Byte0]: 45
2659 23:42:21.899006 [Byte1]: 45
2660 23:42:21.903519
2661 23:42:21.903599 Set Vref, RX VrefLevel [Byte0]: 46
2662 23:42:21.906952 [Byte1]: 46
2663 23:42:21.911485
2664 23:42:21.911565 Set Vref, RX VrefLevel [Byte0]: 47
2665 23:42:21.914854 [Byte1]: 47
2666 23:42:21.919341
2667 23:42:21.919424 Set Vref, RX VrefLevel [Byte0]: 48
2668 23:42:21.922823 [Byte1]: 48
2669 23:42:21.927202
2670 23:42:21.927282 Set Vref, RX VrefLevel [Byte0]: 49
2671 23:42:21.930650 [Byte1]: 49
2672 23:42:21.935562
2673 23:42:21.935669 Set Vref, RX VrefLevel [Byte0]: 50
2674 23:42:21.938480 [Byte1]: 50
2675 23:42:21.943235
2676 23:42:21.943337 Set Vref, RX VrefLevel [Byte0]: 51
2677 23:42:21.946560 [Byte1]: 51
2678 23:42:21.951068
2679 23:42:21.951174 Set Vref, RX VrefLevel [Byte0]: 52
2680 23:42:21.954285 [Byte1]: 52
2681 23:42:21.958879
2682 23:42:21.958949 Set Vref, RX VrefLevel [Byte0]: 53
2683 23:42:21.962524 [Byte1]: 53
2684 23:42:21.966971
2685 23:42:21.967041 Set Vref, RX VrefLevel [Byte0]: 54
2686 23:42:21.970386 [Byte1]: 54
2687 23:42:21.974809
2688 23:42:21.974886 Set Vref, RX VrefLevel [Byte0]: 55
2689 23:42:21.978322 [Byte1]: 55
2690 23:42:21.982901
2691 23:42:21.983006 Set Vref, RX VrefLevel [Byte0]: 56
2692 23:42:21.986072 [Byte1]: 56
2693 23:42:21.990815
2694 23:42:21.990897 Set Vref, RX VrefLevel [Byte0]: 57
2695 23:42:21.994343 [Byte1]: 57
2696 23:42:21.998749
2697 23:42:21.998860 Set Vref, RX VrefLevel [Byte0]: 58
2698 23:42:22.002126 [Byte1]: 58
2699 23:42:22.006488
2700 23:42:22.006559 Set Vref, RX VrefLevel [Byte0]: 59
2701 23:42:22.009979 [Byte1]: 59
2702 23:42:22.014394
2703 23:42:22.014473 Set Vref, RX VrefLevel [Byte0]: 60
2704 23:42:22.017738 [Byte1]: 60
2705 23:42:22.022397
2706 23:42:22.022506 Set Vref, RX VrefLevel [Byte0]: 61
2707 23:42:22.026151 [Byte1]: 61
2708 23:42:22.030474
2709 23:42:22.030554 Set Vref, RX VrefLevel [Byte0]: 62
2710 23:42:22.033450 [Byte1]: 62
2711 23:42:22.038198
2712 23:42:22.038272 Set Vref, RX VrefLevel [Byte0]: 63
2713 23:42:22.041696 [Byte1]: 63
2714 23:42:22.046425
2715 23:42:22.046496 Set Vref, RX VrefLevel [Byte0]: 64
2716 23:42:22.049537 [Byte1]: 64
2717 23:42:22.054094
2718 23:42:22.054191 Set Vref, RX VrefLevel [Byte0]: 65
2719 23:42:22.057192 [Byte1]: 65
2720 23:42:22.062220
2721 23:42:22.062304 Set Vref, RX VrefLevel [Byte0]: 66
2722 23:42:22.065393 [Byte1]: 66
2723 23:42:22.069818
2724 23:42:22.069894 Set Vref, RX VrefLevel [Byte0]: 67
2725 23:42:22.074013 [Byte1]: 67
2726 23:42:22.078155
2727 23:42:22.078256 Final RX Vref Byte 0 = 46 to rank0
2728 23:42:22.081196 Final RX Vref Byte 1 = 52 to rank0
2729 23:42:22.084565 Final RX Vref Byte 0 = 46 to rank1
2730 23:42:22.087880 Final RX Vref Byte 1 = 52 to rank1==
2731 23:42:22.091397 Dram Type= 6, Freq= 0, CH_0, rank 0
2732 23:42:22.097740 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2733 23:42:22.097818 ==
2734 23:42:22.097882 DQS Delay:
2735 23:42:22.097940 DQS0 = 0, DQS1 = 0
2736 23:42:22.101173 DQM Delay:
2737 23:42:22.101297 DQM0 = 114, DQM1 = 106
2738 23:42:22.104285 DQ Delay:
2739 23:42:22.107729 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2740 23:42:22.110894 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
2741 23:42:22.114552 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =98
2742 23:42:22.118150 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =118
2743 23:42:22.118235
2744 23:42:22.118296
2745 23:42:22.124554 [DQSOSCAuto] RK0, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
2746 23:42:22.127644 CH0 RK0: MR19=404, MR18=C0C
2747 23:42:22.134173 CH0_RK0: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
2748 23:42:22.134249
2749 23:42:22.137604 ----->DramcWriteLeveling(PI) begin...
2750 23:42:22.137691 ==
2751 23:42:22.141026 Dram Type= 6, Freq= 0, CH_0, rank 1
2752 23:42:22.144392 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2753 23:42:22.144500 ==
2754 23:42:22.147706 Write leveling (Byte 0): 28 => 28
2755 23:42:22.150948 Write leveling (Byte 1): 24 => 24
2756 23:42:22.154308 DramcWriteLeveling(PI) end<-----
2757 23:42:22.154390
2758 23:42:22.154455 ==
2759 23:42:22.157479 Dram Type= 6, Freq= 0, CH_0, rank 1
2760 23:42:22.164281 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2761 23:42:22.164396 ==
2762 23:42:22.164493 [Gating] SW mode calibration
2763 23:42:22.174206 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2764 23:42:22.177564 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2765 23:42:22.180962 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2766 23:42:22.188069 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2767 23:42:22.190820 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2768 23:42:22.194972 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2769 23:42:22.200879 0 11 16 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2770 23:42:22.204181 0 11 20 | B1->B0 | 2e2e 2626 | 0 0 | (0 1) (0 1)
2771 23:42:22.207473 0 11 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2772 23:42:22.214225 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2773 23:42:22.217579 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2774 23:42:22.220821 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2775 23:42:22.227511 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2776 23:42:22.231085 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2777 23:42:22.234154 0 12 16 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
2778 23:42:22.240634 0 12 20 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
2779 23:42:22.244013 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2780 23:42:22.247559 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2781 23:42:22.254177 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2782 23:42:22.257729 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2783 23:42:22.260984 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2784 23:42:22.264247 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2785 23:42:22.271035 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2786 23:42:22.274087 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2787 23:42:22.277897 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2788 23:42:22.284225 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2789 23:42:22.287389 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2790 23:42:22.290742 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2791 23:42:22.297711 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2792 23:42:22.300759 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2793 23:42:22.304007 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2794 23:42:22.310671 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2795 23:42:22.313910 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2796 23:42:22.317409 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2797 23:42:22.324259 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2798 23:42:22.327682 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2799 23:42:22.330945 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2800 23:42:22.337936 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2801 23:42:22.341098 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2802 23:42:22.344687 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2803 23:42:22.351006 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2804 23:42:22.351088 Total UI for P1: 0, mck2ui 16
2805 23:42:22.354069 best dqsien dly found for B0: ( 0, 15, 18)
2806 23:42:22.357467 Total UI for P1: 0, mck2ui 16
2807 23:42:22.361101 best dqsien dly found for B1: ( 0, 15, 18)
2808 23:42:22.364230 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2809 23:42:22.370918 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
2810 23:42:22.371000
2811 23:42:22.374290 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2812 23:42:22.377510 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
2813 23:42:22.380851 [Gating] SW calibration Done
2814 23:42:22.380933 ==
2815 23:42:22.384256 Dram Type= 6, Freq= 0, CH_0, rank 1
2816 23:42:22.387399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2817 23:42:22.387482 ==
2818 23:42:22.390828 RX Vref Scan: 0
2819 23:42:22.390910
2820 23:42:22.390975 RX Vref 0 -> 0, step: 1
2821 23:42:22.391035
2822 23:42:22.394552 RX Delay -40 -> 252, step: 8
2823 23:42:22.397308 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2824 23:42:22.400863 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2825 23:42:22.407324 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2826 23:42:22.410713 iDelay=200, Bit 3, Center 107 (40 ~ 175) 136
2827 23:42:22.414194 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2828 23:42:22.417565 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2829 23:42:22.420701 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2830 23:42:22.427506 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2831 23:42:22.430706 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2832 23:42:22.434456 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2833 23:42:22.437491 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2834 23:42:22.440714 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2835 23:42:22.447509 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2836 23:42:22.450989 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2837 23:42:22.454094 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2838 23:42:22.457523 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2839 23:42:22.457605 ==
2840 23:42:22.460919 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 23:42:22.467538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2842 23:42:22.467621 ==
2843 23:42:22.467687 DQS Delay:
2844 23:42:22.467747 DQS0 = 0, DQS1 = 0
2845 23:42:22.471072 DQM Delay:
2846 23:42:22.471154 DQM0 = 113, DQM1 = 106
2847 23:42:22.474142 DQ Delay:
2848 23:42:22.477459 DQ0 =107, DQ1 =115, DQ2 =111, DQ3 =107
2849 23:42:22.480902 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2850 23:42:22.484177 DQ8 =91, DQ9 =91, DQ10 =107, DQ11 =99
2851 23:42:22.487865 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2852 23:42:22.487947
2853 23:42:22.488012
2854 23:42:22.488072 ==
2855 23:42:22.491354 Dram Type= 6, Freq= 0, CH_0, rank 1
2856 23:42:22.494236 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2857 23:42:22.494319 ==
2858 23:42:22.494383
2859 23:42:22.494445
2860 23:42:22.497715 TX Vref Scan disable
2861 23:42:22.501084 == TX Byte 0 ==
2862 23:42:22.504281 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2863 23:42:22.507433 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2864 23:42:22.510801 == TX Byte 1 ==
2865 23:42:22.514421 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2866 23:42:22.517714 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2867 23:42:22.517796 ==
2868 23:42:22.520907 Dram Type= 6, Freq= 0, CH_0, rank 1
2869 23:42:22.527476 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2870 23:42:22.527556 ==
2871 23:42:22.537860 TX Vref=22, minBit 8, minWin=25, winSum=420
2872 23:42:22.541486 TX Vref=24, minBit 8, minWin=25, winSum=426
2873 23:42:22.544814 TX Vref=26, minBit 8, minWin=25, winSum=429
2874 23:42:22.548119 TX Vref=28, minBit 8, minWin=26, winSum=429
2875 23:42:22.551130 TX Vref=30, minBit 8, minWin=26, winSum=431
2876 23:42:22.558005 TX Vref=32, minBit 10, minWin=25, winSum=433
2877 23:42:22.561161 [TxChooseVref] Worse bit 8, Min win 26, Win sum 431, Final Vref 30
2878 23:42:22.561259
2879 23:42:22.564478 Final TX Range 1 Vref 30
2880 23:42:22.564577
2881 23:42:22.564637 ==
2882 23:42:22.568092 Dram Type= 6, Freq= 0, CH_0, rank 1
2883 23:42:22.571142 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2884 23:42:22.571215 ==
2885 23:42:22.574604
2886 23:42:22.574673
2887 23:42:22.574732 TX Vref Scan disable
2888 23:42:22.577751 == TX Byte 0 ==
2889 23:42:22.581102 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2890 23:42:22.584335 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2891 23:42:22.587849 == TX Byte 1 ==
2892 23:42:22.591159 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
2893 23:42:22.594277 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
2894 23:42:22.598124
2895 23:42:22.598206 [DATLAT]
2896 23:42:22.598270 Freq=1200, CH0 RK1
2897 23:42:22.598330
2898 23:42:22.601153 DATLAT Default: 0xc
2899 23:42:22.601277 0, 0xFFFF, sum = 0
2900 23:42:22.604422 1, 0xFFFF, sum = 0
2901 23:42:22.604505 2, 0xFFFF, sum = 0
2902 23:42:22.607928 3, 0xFFFF, sum = 0
2903 23:42:22.608012 4, 0xFFFF, sum = 0
2904 23:42:22.611201 5, 0xFFFF, sum = 0
2905 23:42:22.611284 6, 0xFFFF, sum = 0
2906 23:42:22.614637 7, 0xFFFF, sum = 0
2907 23:42:22.618079 8, 0xFFFF, sum = 0
2908 23:42:22.618163 9, 0xFFFF, sum = 0
2909 23:42:22.621400 10, 0xFFFF, sum = 0
2910 23:42:22.621483 11, 0x0, sum = 1
2911 23:42:22.621560 12, 0x0, sum = 2
2912 23:42:22.624650 13, 0x0, sum = 3
2913 23:42:22.624736 14, 0x0, sum = 4
2914 23:42:22.628076 best_step = 12
2915 23:42:22.628157
2916 23:42:22.628221 ==
2917 23:42:22.631719 Dram Type= 6, Freq= 0, CH_0, rank 1
2918 23:42:22.634512 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2919 23:42:22.634594 ==
2920 23:42:22.638182 RX Vref Scan: 0
2921 23:42:22.638264
2922 23:42:22.638328 RX Vref 0 -> 0, step: 1
2923 23:42:22.638389
2924 23:42:22.641257 RX Delay -21 -> 252, step: 4
2925 23:42:22.648257 iDelay=195, Bit 0, Center 110 (43 ~ 178) 136
2926 23:42:22.651437 iDelay=195, Bit 1, Center 118 (47 ~ 190) 144
2927 23:42:22.654924 iDelay=195, Bit 2, Center 112 (43 ~ 182) 140
2928 23:42:22.658296 iDelay=195, Bit 3, Center 110 (43 ~ 178) 136
2929 23:42:22.661862 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
2930 23:42:22.668215 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
2931 23:42:22.671539 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
2932 23:42:22.674652 iDelay=195, Bit 7, Center 124 (55 ~ 194) 140
2933 23:42:22.678256 iDelay=195, Bit 8, Center 94 (31 ~ 158) 128
2934 23:42:22.681397 iDelay=195, Bit 9, Center 90 (27 ~ 154) 128
2935 23:42:22.688422 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
2936 23:42:22.691525 iDelay=195, Bit 11, Center 98 (39 ~ 158) 120
2937 23:42:22.694896 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
2938 23:42:22.698022 iDelay=195, Bit 13, Center 114 (51 ~ 178) 128
2939 23:42:22.701660 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
2940 23:42:22.708188 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
2941 23:42:22.708270 ==
2942 23:42:22.711598 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 23:42:22.715020 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2944 23:42:22.715104 ==
2945 23:42:22.715168 DQS Delay:
2946 23:42:22.718151 DQS0 = 0, DQS1 = 0
2947 23:42:22.718233 DQM Delay:
2948 23:42:22.721678 DQM0 = 114, DQM1 = 106
2949 23:42:22.721759 DQ Delay:
2950 23:42:22.724810 DQ0 =110, DQ1 =118, DQ2 =112, DQ3 =110
2951 23:42:22.728304 DQ4 =116, DQ5 =106, DQ6 =122, DQ7 =124
2952 23:42:22.731544 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =98
2953 23:42:22.735165 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =114
2954 23:42:22.735237
2955 23:42:22.735298
2956 23:42:22.745070 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2957 23:42:22.745168 CH0 RK1: MR19=404, MR18=E0E
2958 23:42:22.751527 CH0_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
2959 23:42:22.755046 [RxdqsGatingPostProcess] freq 1200
2960 23:42:22.761418 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2961 23:42:22.765172 Pre-setting of DQS Precalculation
2962 23:42:22.768271 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2963 23:42:22.768343 ==
2964 23:42:22.771927 Dram Type= 6, Freq= 0, CH_1, rank 0
2965 23:42:22.778536 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2966 23:42:22.778609 ==
2967 23:42:22.781723 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2968 23:42:22.788183 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2969 23:42:22.796899 [CA 0] Center 37 (7~68) winsize 62
2970 23:42:22.800258 [CA 1] Center 37 (7~68) winsize 62
2971 23:42:22.803233 [CA 2] Center 34 (4~65) winsize 62
2972 23:42:22.807156 [CA 3] Center 33 (3~64) winsize 62
2973 23:42:22.810006 [CA 4] Center 32 (2~63) winsize 62
2974 23:42:22.813240 [CA 5] Center 32 (2~63) winsize 62
2975 23:42:22.813364
2976 23:42:22.816630 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2977 23:42:22.816729
2978 23:42:22.820347 [CATrainingPosCal] consider 1 rank data
2979 23:42:22.823149 u2DelayCellTimex100 = 270/100 ps
2980 23:42:22.826699 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2981 23:42:22.829824 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2982 23:42:22.836688 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2983 23:42:22.840082 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2984 23:42:22.843305 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2985 23:42:22.847045 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2986 23:42:22.847114
2987 23:42:22.849992 CA PerBit enable=1, Macro0, CA PI delay=32
2988 23:42:22.850086
2989 23:42:22.853334 [CBTSetCACLKResult] CA Dly = 32
2990 23:42:22.853406 CS Dly: 6 (0~37)
2991 23:42:22.853467 ==
2992 23:42:22.856756 Dram Type= 6, Freq= 0, CH_1, rank 1
2993 23:42:22.863398 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2994 23:42:22.863474 ==
2995 23:42:22.867494 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2996 23:42:22.873422 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2997 23:42:22.881873 [CA 0] Center 37 (6~68) winsize 63
2998 23:42:22.885223 [CA 1] Center 37 (6~68) winsize 63
2999 23:42:22.888415 [CA 2] Center 33 (3~64) winsize 62
3000 23:42:22.891713 [CA 3] Center 33 (3~64) winsize 62
3001 23:42:22.895236 [CA 4] Center 32 (2~63) winsize 62
3002 23:42:22.898609 [CA 5] Center 32 (1~63) winsize 63
3003 23:42:22.898683
3004 23:42:22.901871 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3005 23:42:22.901940
3006 23:42:22.905119 [CATrainingPosCal] consider 2 rank data
3007 23:42:22.908526 u2DelayCellTimex100 = 270/100 ps
3008 23:42:22.911761 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
3009 23:42:22.915305 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
3010 23:42:22.921931 CA2 delay=34 (4~64),Diff = 2 PI (9 cell)
3011 23:42:22.925336 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
3012 23:42:22.928684 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
3013 23:42:22.932157 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3014 23:42:22.932229
3015 23:42:22.935247 CA PerBit enable=1, Macro0, CA PI delay=32
3016 23:42:22.935319
3017 23:42:22.938477 [CBTSetCACLKResult] CA Dly = 32
3018 23:42:22.938573 CS Dly: 6 (0~38)
3019 23:42:22.938664
3020 23:42:22.942037 ----->DramcWriteLeveling(PI) begin...
3021 23:42:22.945019 ==
3022 23:42:22.945091 Dram Type= 6, Freq= 0, CH_1, rank 0
3023 23:42:22.951769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3024 23:42:22.951844 ==
3025 23:42:22.954997 Write leveling (Byte 0): 21 => 21
3026 23:42:22.958561 Write leveling (Byte 1): 21 => 21
3027 23:42:22.961769 DramcWriteLeveling(PI) end<-----
3028 23:42:22.961841
3029 23:42:22.961904 ==
3030 23:42:22.965047 Dram Type= 6, Freq= 0, CH_1, rank 0
3031 23:42:22.968436 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3032 23:42:22.968512 ==
3033 23:42:22.971823 [Gating] SW mode calibration
3034 23:42:22.978749 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3035 23:42:22.981898 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3036 23:42:22.988289 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3037 23:42:22.991739 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3038 23:42:22.995314 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3039 23:42:23.001695 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3040 23:42:23.004864 0 11 16 | B1->B0 | 2f2f 2828 | 1 1 | (1 0) (0 1)
3041 23:42:23.008244 0 11 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3042 23:42:23.014912 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3043 23:42:23.018327 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3044 23:42:23.021773 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3045 23:42:23.028534 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3046 23:42:23.031985 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3047 23:42:23.035014 0 12 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
3048 23:42:23.041728 0 12 16 | B1->B0 | 3837 4444 | 1 0 | (0 0) (0 0)
3049 23:42:23.045011 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3050 23:42:23.048460 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3051 23:42:23.055247 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3052 23:42:23.058565 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3053 23:42:23.061748 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3054 23:42:23.068196 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3055 23:42:23.071563 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3056 23:42:23.074936 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3057 23:42:23.078449 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3058 23:42:23.085018 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3059 23:42:23.088656 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3060 23:42:23.091910 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3061 23:42:23.098577 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3062 23:42:23.101977 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3063 23:42:23.104995 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3064 23:42:23.111852 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3065 23:42:23.115219 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3066 23:42:23.118491 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3067 23:42:23.125028 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3068 23:42:23.128504 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3069 23:42:23.131803 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3070 23:42:23.138341 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3071 23:42:23.141865 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3072 23:42:23.144917 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3073 23:42:23.151648 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3074 23:42:23.151730 Total UI for P1: 0, mck2ui 16
3075 23:42:23.158312 best dqsien dly found for B0: ( 0, 15, 16)
3076 23:42:23.161578 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3077 23:42:23.165133 Total UI for P1: 0, mck2ui 16
3078 23:42:23.168329 best dqsien dly found for B1: ( 0, 15, 18)
3079 23:42:23.171850 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3080 23:42:23.175132 best DQS1 dly(MCK, UI, PI) = (0, 15, 18)
3081 23:42:23.175214
3082 23:42:23.178644 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3083 23:42:23.181525 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 18)
3084 23:42:23.185201 [Gating] SW calibration Done
3085 23:42:23.185348 ==
3086 23:42:23.188309 Dram Type= 6, Freq= 0, CH_1, rank 0
3087 23:42:23.191980 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3088 23:42:23.192063 ==
3089 23:42:23.195059 RX Vref Scan: 0
3090 23:42:23.195142
3091 23:42:23.198405 RX Vref 0 -> 0, step: 1
3092 23:42:23.198487
3093 23:42:23.198552 RX Delay -40 -> 252, step: 8
3094 23:42:23.205402 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3095 23:42:23.208381 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3096 23:42:23.211744 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3097 23:42:23.215335 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3098 23:42:23.218439 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3099 23:42:23.225005 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3100 23:42:23.228502 iDelay=208, Bit 6, Center 119 (40 ~ 199) 160
3101 23:42:23.231592 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3102 23:42:23.235158 iDelay=208, Bit 8, Center 91 (24 ~ 159) 136
3103 23:42:23.238567 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3104 23:42:23.244896 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3105 23:42:23.248597 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3106 23:42:23.251756 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3107 23:42:23.254969 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3108 23:42:23.258429 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3109 23:42:23.265042 iDelay=208, Bit 15, Center 115 (40 ~ 191) 152
3110 23:42:23.265124 ==
3111 23:42:23.268569 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 23:42:23.271606 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3113 23:42:23.271709 ==
3114 23:42:23.271778 DQS Delay:
3115 23:42:23.275093 DQS0 = 0, DQS1 = 0
3116 23:42:23.275176 DQM Delay:
3117 23:42:23.278317 DQM0 = 115, DQM1 = 107
3118 23:42:23.278417 DQ Delay:
3119 23:42:23.281859 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3120 23:42:23.284915 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3121 23:42:23.288737 DQ8 =91, DQ9 =95, DQ10 =111, DQ11 =99
3122 23:42:23.291716 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3123 23:42:23.291848
3124 23:42:23.291930
3125 23:42:23.292004 ==
3126 23:42:23.295305 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 23:42:23.301824 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3128 23:42:23.301948 ==
3129 23:42:23.302044
3130 23:42:23.302134
3131 23:42:23.302219 TX Vref Scan disable
3132 23:42:23.305333 == TX Byte 0 ==
3133 23:42:23.308816 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3134 23:42:23.315331 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3135 23:42:23.315539 == TX Byte 1 ==
3136 23:42:23.318659 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3137 23:42:23.325483 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3138 23:42:23.325728 ==
3139 23:42:23.328928 Dram Type= 6, Freq= 0, CH_1, rank 0
3140 23:42:23.332393 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3141 23:42:23.332824 ==
3142 23:42:23.343259 TX Vref=22, minBit 5, minWin=25, winSum=414
3143 23:42:23.346577 TX Vref=24, minBit 11, minWin=25, winSum=423
3144 23:42:23.350206 TX Vref=26, minBit 0, minWin=26, winSum=427
3145 23:42:23.353103 TX Vref=28, minBit 0, minWin=26, winSum=428
3146 23:42:23.356586 TX Vref=30, minBit 11, minWin=26, winSum=433
3147 23:42:23.363322 TX Vref=32, minBit 3, minWin=26, winSum=430
3148 23:42:23.366362 [TxChooseVref] Worse bit 11, Min win 26, Win sum 433, Final Vref 30
3149 23:42:23.366793
3150 23:42:23.369777 Final TX Range 1 Vref 30
3151 23:42:23.370202
3152 23:42:23.370536 ==
3153 23:42:23.373151 Dram Type= 6, Freq= 0, CH_1, rank 0
3154 23:42:23.376386 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3155 23:42:23.379613 ==
3156 23:42:23.380037
3157 23:42:23.380370
3158 23:42:23.380755 TX Vref Scan disable
3159 23:42:23.383068 == TX Byte 0 ==
3160 23:42:23.386803 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3161 23:42:23.389821 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3162 23:42:23.393084 == TX Byte 1 ==
3163 23:42:23.396386 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3164 23:42:23.399605 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3165 23:42:23.403140
3166 23:42:23.403557 [DATLAT]
3167 23:42:23.403886 Freq=1200, CH1 RK0
3168 23:42:23.404199
3169 23:42:23.406468 DATLAT Default: 0xd
3170 23:42:23.406947 0, 0xFFFF, sum = 0
3171 23:42:23.409957 1, 0xFFFF, sum = 0
3172 23:42:23.410383 2, 0xFFFF, sum = 0
3173 23:42:23.413427 3, 0xFFFF, sum = 0
3174 23:42:23.413854 4, 0xFFFF, sum = 0
3175 23:42:23.416563 5, 0xFFFF, sum = 0
3176 23:42:23.420485 6, 0xFFFF, sum = 0
3177 23:42:23.421009 7, 0xFFFF, sum = 0
3178 23:42:23.423120 8, 0xFFFF, sum = 0
3179 23:42:23.423588 9, 0xFFFF, sum = 0
3180 23:42:23.426770 10, 0xFFFF, sum = 0
3181 23:42:23.427342 11, 0x0, sum = 1
3182 23:42:23.430008 12, 0x0, sum = 2
3183 23:42:23.430478 13, 0x0, sum = 3
3184 23:42:23.430851 14, 0x0, sum = 4
3185 23:42:23.433235 best_step = 12
3186 23:42:23.433733
3187 23:42:23.434099 ==
3188 23:42:23.437143 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 23:42:23.440117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3190 23:42:23.440692 ==
3191 23:42:23.443444 RX Vref Scan: 1
3192 23:42:23.444010
3193 23:42:23.446853 Set Vref Range= 32 -> 127
3194 23:42:23.447448
3195 23:42:23.447815 RX Vref 32 -> 127, step: 1
3196 23:42:23.448152
3197 23:42:23.449840 RX Delay -21 -> 252, step: 4
3198 23:42:23.450302
3199 23:42:23.453433 Set Vref, RX VrefLevel [Byte0]: 32
3200 23:42:23.456603 [Byte1]: 32
3201 23:42:23.460215
3202 23:42:23.460780 Set Vref, RX VrefLevel [Byte0]: 33
3203 23:42:23.463305 [Byte1]: 33
3204 23:42:23.468153
3205 23:42:23.468721 Set Vref, RX VrefLevel [Byte0]: 34
3206 23:42:23.471020 [Byte1]: 34
3207 23:42:23.476273
3208 23:42:23.476839 Set Vref, RX VrefLevel [Byte0]: 35
3209 23:42:23.479132 [Byte1]: 35
3210 23:42:23.483574
3211 23:42:23.484034 Set Vref, RX VrefLevel [Byte0]: 36
3212 23:42:23.487634 [Byte1]: 36
3213 23:42:23.491921
3214 23:42:23.492386 Set Vref, RX VrefLevel [Byte0]: 37
3215 23:42:23.495031 [Byte1]: 37
3216 23:42:23.499408
3217 23:42:23.499878 Set Vref, RX VrefLevel [Byte0]: 38
3218 23:42:23.503075 [Byte1]: 38
3219 23:42:23.507766
3220 23:42:23.508326 Set Vref, RX VrefLevel [Byte0]: 39
3221 23:42:23.510979 [Byte1]: 39
3222 23:42:23.515573
3223 23:42:23.516134 Set Vref, RX VrefLevel [Byte0]: 40
3224 23:42:23.519005 [Byte1]: 40
3225 23:42:23.523521
3226 23:42:23.524082 Set Vref, RX VrefLevel [Byte0]: 41
3227 23:42:23.526744 [Byte1]: 41
3228 23:42:23.532246
3229 23:42:23.532804 Set Vref, RX VrefLevel [Byte0]: 42
3230 23:42:23.534664 [Byte1]: 42
3231 23:42:23.539165
3232 23:42:23.539725 Set Vref, RX VrefLevel [Byte0]: 43
3233 23:42:23.542885 [Byte1]: 43
3234 23:42:23.547201
3235 23:42:23.547755 Set Vref, RX VrefLevel [Byte0]: 44
3236 23:42:23.550594 [Byte1]: 44
3237 23:42:23.554972
3238 23:42:23.558405 Set Vref, RX VrefLevel [Byte0]: 45
3239 23:42:23.558963 [Byte1]: 45
3240 23:42:23.563087
3241 23:42:23.563812 Set Vref, RX VrefLevel [Byte0]: 46
3242 23:42:23.566609 [Byte1]: 46
3243 23:42:23.570878
3244 23:42:23.571344 Set Vref, RX VrefLevel [Byte0]: 47
3245 23:42:23.574260 [Byte1]: 47
3246 23:42:23.578849
3247 23:42:23.579312 Set Vref, RX VrefLevel [Byte0]: 48
3248 23:42:23.581880 [Byte1]: 48
3249 23:42:23.586642
3250 23:42:23.587291 Set Vref, RX VrefLevel [Byte0]: 49
3251 23:42:23.590232 [Byte1]: 49
3252 23:42:23.594581
3253 23:42:23.595044 Set Vref, RX VrefLevel [Byte0]: 50
3254 23:42:23.597818 [Byte1]: 50
3255 23:42:23.602678
3256 23:42:23.603248 Set Vref, RX VrefLevel [Byte0]: 51
3257 23:42:23.605949 [Byte1]: 51
3258 23:42:23.610469
3259 23:42:23.611037 Set Vref, RX VrefLevel [Byte0]: 52
3260 23:42:23.613927 [Byte1]: 52
3261 23:42:23.618372
3262 23:42:23.618939 Set Vref, RX VrefLevel [Byte0]: 53
3263 23:42:23.621612 [Byte1]: 53
3264 23:42:23.626546
3265 23:42:23.627110 Set Vref, RX VrefLevel [Byte0]: 54
3266 23:42:23.629851 [Byte1]: 54
3267 23:42:23.634376
3268 23:42:23.634955 Set Vref, RX VrefLevel [Byte0]: 55
3269 23:42:23.637917 [Byte1]: 55
3270 23:42:23.642594
3271 23:42:23.643264 Set Vref, RX VrefLevel [Byte0]: 56
3272 23:42:23.645647 [Byte1]: 56
3273 23:42:23.650589
3274 23:42:23.651162 Set Vref, RX VrefLevel [Byte0]: 57
3275 23:42:23.653195 [Byte1]: 57
3276 23:42:23.658404
3277 23:42:23.658968 Set Vref, RX VrefLevel [Byte0]: 58
3278 23:42:23.661534 [Byte1]: 58
3279 23:42:23.666139
3280 23:42:23.666703 Set Vref, RX VrefLevel [Byte0]: 59
3281 23:42:23.669397 [Byte1]: 59
3282 23:42:23.673784
3283 23:42:23.674249 Set Vref, RX VrefLevel [Byte0]: 60
3284 23:42:23.677469 [Byte1]: 60
3285 23:42:23.681475
3286 23:42:23.682075 Set Vref, RX VrefLevel [Byte0]: 61
3287 23:42:23.684766 [Byte1]: 61
3288 23:42:23.689669
3289 23:42:23.690129 Set Vref, RX VrefLevel [Byte0]: 62
3290 23:42:23.693126 [Byte1]: 62
3291 23:42:23.697435
3292 23:42:23.697896 Set Vref, RX VrefLevel [Byte0]: 63
3293 23:42:23.700769 [Byte1]: 63
3294 23:42:23.705563
3295 23:42:23.706128 Set Vref, RX VrefLevel [Byte0]: 64
3296 23:42:23.708870 [Byte1]: 64
3297 23:42:23.713735
3298 23:42:23.714304 Set Vref, RX VrefLevel [Byte0]: 65
3299 23:42:23.716946 [Byte1]: 65
3300 23:42:23.721428
3301 23:42:23.721991 Set Vref, RX VrefLevel [Byte0]: 66
3302 23:42:23.724765 [Byte1]: 66
3303 23:42:23.729466
3304 23:42:23.730038 Set Vref, RX VrefLevel [Byte0]: 67
3305 23:42:23.732780 [Byte1]: 67
3306 23:42:23.737406
3307 23:42:23.737962 Final RX Vref Byte 0 = 52 to rank0
3308 23:42:23.740196 Final RX Vref Byte 1 = 49 to rank0
3309 23:42:23.743913 Final RX Vref Byte 0 = 52 to rank1
3310 23:42:23.747521 Final RX Vref Byte 1 = 49 to rank1==
3311 23:42:23.750552 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 23:42:23.757730 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3313 23:42:23.758295 ==
3314 23:42:23.758668 DQS Delay:
3315 23:42:23.759013 DQS0 = 0, DQS1 = 0
3316 23:42:23.760276 DQM Delay:
3317 23:42:23.760741 DQM0 = 115, DQM1 = 106
3318 23:42:23.764074 DQ Delay:
3319 23:42:23.767270 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3320 23:42:23.770616 DQ4 =114, DQ5 =126, DQ6 =122, DQ7 =114
3321 23:42:23.773948 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3322 23:42:23.777206 DQ12 =114, DQ13 =116, DQ14 =116, DQ15 =116
3323 23:42:23.777831
3324 23:42:23.778204
3325 23:42:23.783973 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b1b, (MSB)MR19= 0x404, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
3326 23:42:23.787011 CH1 RK0: MR19=404, MR18=1B1B
3327 23:42:23.794079 CH1_RK0: MR19=0x404, MR18=0x1B1B, DQSOSC=399, MR23=63, INC=41, DEC=27
3328 23:42:23.794649
3329 23:42:23.797778 ----->DramcWriteLeveling(PI) begin...
3330 23:42:23.798244 ==
3331 23:42:23.800562 Dram Type= 6, Freq= 0, CH_1, rank 1
3332 23:42:23.803990 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3333 23:42:23.804570 ==
3334 23:42:23.807208 Write leveling (Byte 0): 20 => 20
3335 23:42:23.810749 Write leveling (Byte 1): 21 => 21
3336 23:42:23.814231 DramcWriteLeveling(PI) end<-----
3337 23:42:23.814798
3338 23:42:23.815167 ==
3339 23:42:23.817362 Dram Type= 6, Freq= 0, CH_1, rank 1
3340 23:42:23.820682 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3341 23:42:23.824429 ==
3342 23:42:23.825002 [Gating] SW mode calibration
3343 23:42:23.833916 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3344 23:42:23.837399 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3345 23:42:23.840656 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3346 23:42:23.847394 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3347 23:42:23.850523 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3348 23:42:23.853803 0 11 12 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (0 0)
3349 23:42:23.860843 0 11 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
3350 23:42:23.864128 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3351 23:42:23.867218 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3352 23:42:23.874366 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3353 23:42:23.877430 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3354 23:42:23.880433 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3355 23:42:23.887236 0 12 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
3356 23:42:23.890555 0 12 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
3357 23:42:23.893870 0 12 16 | B1->B0 | 3737 4545 | 1 0 | (0 0) (0 0)
3358 23:42:23.900572 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3359 23:42:23.903838 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3360 23:42:23.906990 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3361 23:42:23.913633 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3362 23:42:23.916943 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3363 23:42:23.920164 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3364 23:42:23.923884 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3365 23:42:23.930312 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3366 23:42:23.933616 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3367 23:42:23.937352 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3368 23:42:23.943845 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3369 23:42:23.947039 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3370 23:42:23.950386 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3371 23:42:23.957065 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3372 23:42:23.960768 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3373 23:42:23.963906 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3374 23:42:23.970279 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3375 23:42:23.973795 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3376 23:42:23.977190 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3377 23:42:23.983911 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3378 23:42:23.987107 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3379 23:42:23.990884 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3380 23:42:23.997366 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3381 23:42:24.000718 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3382 23:42:24.003909 Total UI for P1: 0, mck2ui 16
3383 23:42:24.007164 best dqsien dly found for B0: ( 0, 15, 12)
3384 23:42:24.011082 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3385 23:42:24.014254 Total UI for P1: 0, mck2ui 16
3386 23:42:24.017465 best dqsien dly found for B1: ( 0, 15, 14)
3387 23:42:24.020435 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3388 23:42:24.023955 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3389 23:42:24.024532
3390 23:42:24.027344 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3391 23:42:24.033773 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3392 23:42:24.034367 [Gating] SW calibration Done
3393 23:42:24.034740 ==
3394 23:42:24.037189 Dram Type= 6, Freq= 0, CH_1, rank 1
3395 23:42:24.044146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3396 23:42:24.044705 ==
3397 23:42:24.045068 RX Vref Scan: 0
3398 23:42:24.045447
3399 23:42:24.047354 RX Vref 0 -> 0, step: 1
3400 23:42:24.047909
3401 23:42:24.050602 RX Delay -40 -> 252, step: 8
3402 23:42:24.054236 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3403 23:42:24.057338 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3404 23:42:24.060661 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3405 23:42:24.067209 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3406 23:42:24.070590 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3407 23:42:24.074158 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3408 23:42:24.077400 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3409 23:42:24.080437 iDelay=200, Bit 7, Center 111 (32 ~ 191) 160
3410 23:42:24.083921 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3411 23:42:24.090280 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3412 23:42:24.093608 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3413 23:42:24.097268 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3414 23:42:24.100598 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3415 23:42:24.103992 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3416 23:42:24.110623 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3417 23:42:24.114265 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3418 23:42:24.114825 ==
3419 23:42:24.117222 Dram Type= 6, Freq= 0, CH_1, rank 1
3420 23:42:24.121048 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3421 23:42:24.121674 ==
3422 23:42:24.123675 DQS Delay:
3423 23:42:24.124233 DQS0 = 0, DQS1 = 0
3424 23:42:24.124604 DQM Delay:
3425 23:42:24.127496 DQM0 = 115, DQM1 = 105
3426 23:42:24.128053 DQ Delay:
3427 23:42:24.130325 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3428 23:42:24.133934 DQ4 =115, DQ5 =123, DQ6 =123, DQ7 =111
3429 23:42:24.137582 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =99
3430 23:42:24.144522 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3431 23:42:24.145101
3432 23:42:24.145526
3433 23:42:24.145867 ==
3434 23:42:24.147092 Dram Type= 6, Freq= 0, CH_1, rank 1
3435 23:42:24.150512 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3436 23:42:24.151096 ==
3437 23:42:24.151469
3438 23:42:24.151806
3439 23:42:24.153620 TX Vref Scan disable
3440 23:42:24.154191 == TX Byte 0 ==
3441 23:42:24.160820 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3442 23:42:24.163826 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3443 23:42:24.164389 == TX Byte 1 ==
3444 23:42:24.170157 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3445 23:42:24.174071 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3446 23:42:24.174631 ==
3447 23:42:24.177051 Dram Type= 6, Freq= 0, CH_1, rank 1
3448 23:42:24.180200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3449 23:42:24.180761 ==
3450 23:42:24.192642 TX Vref=22, minBit 8, minWin=25, winSum=423
3451 23:42:24.196059 TX Vref=24, minBit 9, minWin=25, winSum=425
3452 23:42:24.199519 TX Vref=26, minBit 9, minWin=25, winSum=426
3453 23:42:24.202661 TX Vref=28, minBit 8, minWin=26, winSum=432
3454 23:42:24.205933 TX Vref=30, minBit 8, minWin=26, winSum=434
3455 23:42:24.212758 TX Vref=32, minBit 9, minWin=26, winSum=433
3456 23:42:24.216374 [TxChooseVref] Worse bit 8, Min win 26, Win sum 434, Final Vref 30
3457 23:42:24.216945
3458 23:42:24.219473 Final TX Range 1 Vref 30
3459 23:42:24.219937
3460 23:42:24.220300 ==
3461 23:42:24.223132 Dram Type= 6, Freq= 0, CH_1, rank 1
3462 23:42:24.226139 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3463 23:42:24.226603 ==
3464 23:42:24.229864
3465 23:42:24.230422
3466 23:42:24.230785 TX Vref Scan disable
3467 23:42:24.232957 == TX Byte 0 ==
3468 23:42:24.236112 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3469 23:42:24.239407 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3470 23:42:24.243283 == TX Byte 1 ==
3471 23:42:24.246024 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3472 23:42:24.249461 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3473 23:42:24.253208
3474 23:42:24.253854 [DATLAT]
3475 23:42:24.254221 Freq=1200, CH1 RK1
3476 23:42:24.254558
3477 23:42:24.255659 DATLAT Default: 0xc
3478 23:42:24.256040 0, 0xFFFF, sum = 0
3479 23:42:24.259080 1, 0xFFFF, sum = 0
3480 23:42:24.259677 2, 0xFFFF, sum = 0
3481 23:42:24.262492 3, 0xFFFF, sum = 0
3482 23:42:24.262953 4, 0xFFFF, sum = 0
3483 23:42:24.266078 5, 0xFFFF, sum = 0
3484 23:42:24.269065 6, 0xFFFF, sum = 0
3485 23:42:24.269690 7, 0xFFFF, sum = 0
3486 23:42:24.272567 8, 0xFFFF, sum = 0
3487 23:42:24.273146 9, 0xFFFF, sum = 0
3488 23:42:24.275699 10, 0xFFFF, sum = 0
3489 23:42:24.276311 11, 0x0, sum = 1
3490 23:42:24.278895 12, 0x0, sum = 2
3491 23:42:24.279360 13, 0x0, sum = 3
3492 23:42:24.282129 14, 0x0, sum = 4
3493 23:42:24.282597 best_step = 12
3494 23:42:24.282960
3495 23:42:24.283293 ==
3496 23:42:24.285609 Dram Type= 6, Freq= 0, CH_1, rank 1
3497 23:42:24.288910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3498 23:42:24.289451 ==
3499 23:42:24.292629 RX Vref Scan: 0
3500 23:42:24.293220
3501 23:42:24.295809 RX Vref 0 -> 0, step: 1
3502 23:42:24.296284
3503 23:42:24.296653 RX Delay -29 -> 252, step: 4
3504 23:42:24.303221 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3505 23:42:24.306716 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3506 23:42:24.309764 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3507 23:42:24.313154 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3508 23:42:24.316780 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3509 23:42:24.323310 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3510 23:42:24.326497 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3511 23:42:24.330269 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3512 23:42:24.333040 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3513 23:42:24.336718 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3514 23:42:24.342756 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3515 23:42:24.346256 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3516 23:42:24.349681 iDelay=199, Bit 12, Center 112 (43 ~ 182) 140
3517 23:42:24.352957 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3518 23:42:24.356554 iDelay=199, Bit 14, Center 112 (43 ~ 182) 140
3519 23:42:24.363141 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3520 23:42:24.363707 ==
3521 23:42:24.365991 Dram Type= 6, Freq= 0, CH_1, rank 1
3522 23:42:24.369944 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3523 23:42:24.370507 ==
3524 23:42:24.370875 DQS Delay:
3525 23:42:24.372780 DQS0 = 0, DQS1 = 0
3526 23:42:24.373236 DQM Delay:
3527 23:42:24.375985 DQM0 = 114, DQM1 = 103
3528 23:42:24.376544 DQ Delay:
3529 23:42:24.379586 DQ0 =116, DQ1 =110, DQ2 =108, DQ3 =112
3530 23:42:24.382454 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3531 23:42:24.386001 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3532 23:42:24.389447 DQ12 =112, DQ13 =112, DQ14 =112, DQ15 =112
3533 23:42:24.389911
3534 23:42:24.390271
3535 23:42:24.399431 [DQSOSCAuto] RK1, (LSB)MR18= 0xe0e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
3536 23:42:24.402691 CH1 RK1: MR19=404, MR18=E0E
3537 23:42:24.405733 CH1_RK1: MR19=0x404, MR18=0xE0E, DQSOSC=404, MR23=63, INC=40, DEC=26
3538 23:42:24.409390 [RxdqsGatingPostProcess] freq 1200
3539 23:42:24.416224 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3540 23:42:24.419584 Pre-setting of DQS Precalculation
3541 23:42:24.422866 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3542 23:42:24.432452 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3543 23:42:24.439328 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3544 23:42:24.439897
3545 23:42:24.440259
3546 23:42:24.442459 [Calibration Summary] 2400 Mbps
3547 23:42:24.442920 CH 0, Rank 0
3548 23:42:24.445696 SW Impedance : PASS
3549 23:42:24.446154 DUTY Scan : NO K
3550 23:42:24.449435 ZQ Calibration : PASS
3551 23:42:24.452520 Jitter Meter : NO K
3552 23:42:24.452976 CBT Training : PASS
3553 23:42:24.456302 Write leveling : PASS
3554 23:42:24.458870 RX DQS gating : PASS
3555 23:42:24.459328 RX DQ/DQS(RDDQC) : PASS
3556 23:42:24.462330 TX DQ/DQS : PASS
3557 23:42:24.465734 RX DATLAT : PASS
3558 23:42:24.466190 RX DQ/DQS(Engine): PASS
3559 23:42:24.468861 TX OE : NO K
3560 23:42:24.469385 All Pass.
3561 23:42:24.469725
3562 23:42:24.472383 CH 0, Rank 1
3563 23:42:24.472796 SW Impedance : PASS
3564 23:42:24.475598 DUTY Scan : NO K
3565 23:42:24.478805 ZQ Calibration : PASS
3566 23:42:24.479218 Jitter Meter : NO K
3567 23:42:24.482422 CBT Training : PASS
3568 23:42:24.482841 Write leveling : PASS
3569 23:42:24.485437 RX DQS gating : PASS
3570 23:42:24.488713 RX DQ/DQS(RDDQC) : PASS
3571 23:42:24.489127 TX DQ/DQS : PASS
3572 23:42:24.492119 RX DATLAT : PASS
3573 23:42:24.495335 RX DQ/DQS(Engine): PASS
3574 23:42:24.495796 TX OE : NO K
3575 23:42:24.498824 All Pass.
3576 23:42:24.499241
3577 23:42:24.499571 CH 1, Rank 0
3578 23:42:24.502271 SW Impedance : PASS
3579 23:42:24.502688 DUTY Scan : NO K
3580 23:42:24.505932 ZQ Calibration : PASS
3581 23:42:24.509077 Jitter Meter : NO K
3582 23:42:24.509632 CBT Training : PASS
3583 23:42:24.512721 Write leveling : PASS
3584 23:42:24.515821 RX DQS gating : PASS
3585 23:42:24.516417 RX DQ/DQS(RDDQC) : PASS
3586 23:42:24.518856 TX DQ/DQS : PASS
3587 23:42:24.522087 RX DATLAT : PASS
3588 23:42:24.522553 RX DQ/DQS(Engine): PASS
3589 23:42:24.525825 TX OE : NO K
3590 23:42:24.526395 All Pass.
3591 23:42:24.526762
3592 23:42:24.528921 CH 1, Rank 1
3593 23:42:24.529406 SW Impedance : PASS
3594 23:42:24.532046 DUTY Scan : NO K
3595 23:42:24.532506 ZQ Calibration : PASS
3596 23:42:24.535283 Jitter Meter : NO K
3597 23:42:24.538977 CBT Training : PASS
3598 23:42:24.539399 Write leveling : PASS
3599 23:42:24.541854 RX DQS gating : PASS
3600 23:42:24.545382 RX DQ/DQS(RDDQC) : PASS
3601 23:42:24.545800 TX DQ/DQS : PASS
3602 23:42:24.548502 RX DATLAT : PASS
3603 23:42:24.552218 RX DQ/DQS(Engine): PASS
3604 23:42:24.552637 TX OE : NO K
3605 23:42:24.555650 All Pass.
3606 23:42:24.556069
3607 23:42:24.556399 DramC Write-DBI off
3608 23:42:24.558400 PER_BANK_REFRESH: Hybrid Mode
3609 23:42:24.561799 TX_TRACKING: ON
3610 23:42:24.568412 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3611 23:42:24.572120 [FAST_K] Save calibration result to emmc
3612 23:42:24.575227 dramc_set_vcore_voltage set vcore to 650000
3613 23:42:24.578083 Read voltage for 600, 5
3614 23:42:24.578823 Vio18 = 0
3615 23:42:24.581686 Vcore = 650000
3616 23:42:24.582352 Vdram = 0
3617 23:42:24.582975 Vddq = 0
3618 23:42:24.585192 Vmddr = 0
3619 23:42:24.588122 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3620 23:42:24.594962 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3621 23:42:24.595420 MEM_TYPE=3, freq_sel=19
3622 23:42:24.598239 sv_algorithm_assistance_LP4_1600
3623 23:42:24.604583 ============ PULL DRAM RESETB DOWN ============
3624 23:42:24.608222 ========== PULL DRAM RESETB DOWN end =========
3625 23:42:24.611047 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3626 23:42:24.614116 ===================================
3627 23:42:24.617573 LPDDR4 DRAM CONFIGURATION
3628 23:42:24.621053 ===================================
3629 23:42:24.624242 EX_ROW_EN[0] = 0x0
3630 23:42:24.624449 EX_ROW_EN[1] = 0x0
3631 23:42:24.627734 LP4Y_EN = 0x0
3632 23:42:24.627910 WORK_FSP = 0x0
3633 23:42:24.630752 WL = 0x2
3634 23:42:24.630913 RL = 0x2
3635 23:42:24.633927 BL = 0x2
3636 23:42:24.634099 RPST = 0x0
3637 23:42:24.637447 RD_PRE = 0x0
3638 23:42:24.637581 WR_PRE = 0x1
3639 23:42:24.640808 WR_PST = 0x0
3640 23:42:24.640971 DBI_WR = 0x0
3641 23:42:24.644012 DBI_RD = 0x0
3642 23:42:24.644142 OTF = 0x1
3643 23:42:24.647365 ===================================
3644 23:42:24.651380 ===================================
3645 23:42:24.654285 ANA top config
3646 23:42:24.657593 ===================================
3647 23:42:24.660782 DLL_ASYNC_EN = 0
3648 23:42:24.661489 ALL_SLAVE_EN = 1
3649 23:42:24.664228 NEW_RANK_MODE = 1
3650 23:42:24.667346 DLL_IDLE_MODE = 1
3651 23:42:24.670631 LP45_APHY_COMB_EN = 1
3652 23:42:24.673988 TX_ODT_DIS = 1
3653 23:42:24.674214 NEW_8X_MODE = 1
3654 23:42:24.677176 ===================================
3655 23:42:24.680559 ===================================
3656 23:42:24.683537 data_rate = 1200
3657 23:42:24.687155 CKR = 1
3658 23:42:24.690281 DQ_P2S_RATIO = 8
3659 23:42:24.693596 ===================================
3660 23:42:24.696872 CA_P2S_RATIO = 8
3661 23:42:24.700348 DQ_CA_OPEN = 0
3662 23:42:24.700576 DQ_SEMI_OPEN = 0
3663 23:42:24.703521 CA_SEMI_OPEN = 0
3664 23:42:24.707083 CA_FULL_RATE = 0
3665 23:42:24.710449 DQ_CKDIV4_EN = 1
3666 23:42:24.713755 CA_CKDIV4_EN = 1
3667 23:42:24.716752 CA_PREDIV_EN = 0
3668 23:42:24.716978 PH8_DLY = 0
3669 23:42:24.720076 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3670 23:42:24.723382 DQ_AAMCK_DIV = 4
3671 23:42:24.726542 CA_AAMCK_DIV = 4
3672 23:42:24.729867 CA_ADMCK_DIV = 4
3673 23:42:24.733273 DQ_TRACK_CA_EN = 0
3674 23:42:24.733520 CA_PICK = 600
3675 23:42:24.736906 CA_MCKIO = 600
3676 23:42:24.739832 MCKIO_SEMI = 0
3677 23:42:24.743031 PLL_FREQ = 2288
3678 23:42:24.746428 DQ_UI_PI_RATIO = 32
3679 23:42:24.749845 CA_UI_PI_RATIO = 0
3680 23:42:24.753273 ===================================
3681 23:42:24.756361 ===================================
3682 23:42:24.760064 memory_type:LPDDR4
3683 23:42:24.760291 GP_NUM : 10
3684 23:42:24.763272 SRAM_EN : 1
3685 23:42:24.763496 MD32_EN : 0
3686 23:42:24.766334 ===================================
3687 23:42:24.769630 [ANA_INIT] >>>>>>>>>>>>>>
3688 23:42:24.772906 <<<<<< [CONFIGURE PHASE]: ANA_TX
3689 23:42:24.776643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3690 23:42:24.779675 ===================================
3691 23:42:24.783048 data_rate = 1200,PCW = 0X5800
3692 23:42:24.786445 ===================================
3693 23:42:24.789773 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3694 23:42:24.793096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3695 23:42:24.799401 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3696 23:42:24.806345 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3697 23:42:24.809486 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3698 23:42:24.813264 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3699 23:42:24.813884 [ANA_INIT] flow start
3700 23:42:24.816550 [ANA_INIT] PLL >>>>>>>>
3701 23:42:24.820156 [ANA_INIT] PLL <<<<<<<<
3702 23:42:24.820728 [ANA_INIT] MIDPI >>>>>>>>
3703 23:42:24.823077 [ANA_INIT] MIDPI <<<<<<<<
3704 23:42:24.826131 [ANA_INIT] DLL >>>>>>>>
3705 23:42:24.826597 [ANA_INIT] flow end
3706 23:42:24.832979 ============ LP4 DIFF to SE enter ============
3707 23:42:24.836598 ============ LP4 DIFF to SE exit ============
3708 23:42:24.839939 [ANA_INIT] <<<<<<<<<<<<<
3709 23:42:24.840507 [Flow] Enable top DCM control >>>>>
3710 23:42:24.843159 [Flow] Enable top DCM control <<<<<
3711 23:42:24.846263 Enable DLL master slave shuffle
3712 23:42:24.852929 ==============================================================
3713 23:42:24.856242 Gating Mode config
3714 23:42:24.859624 ==============================================================
3715 23:42:24.862906 Config description:
3716 23:42:24.872918 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3717 23:42:24.879518 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3718 23:42:24.882880 SELPH_MODE 0: By rank 1: By Phase
3719 23:42:24.889231 ==============================================================
3720 23:42:24.892477 GAT_TRACK_EN = 1
3721 23:42:24.895799 RX_GATING_MODE = 2
3722 23:42:24.899310 RX_GATING_TRACK_MODE = 2
3723 23:42:24.899778 SELPH_MODE = 1
3724 23:42:24.902630 PICG_EARLY_EN = 1
3725 23:42:24.905976 VALID_LAT_VALUE = 1
3726 23:42:24.912522 ==============================================================
3727 23:42:24.916109 Enter into Gating configuration >>>>
3728 23:42:24.919166 Exit from Gating configuration <<<<
3729 23:42:24.922837 Enter into DVFS_PRE_config >>>>>
3730 23:42:24.932330 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3731 23:42:24.935692 Exit from DVFS_PRE_config <<<<<
3732 23:42:24.939401 Enter into PICG configuration >>>>
3733 23:42:24.942641 Exit from PICG configuration <<<<
3734 23:42:24.945980 [RX_INPUT] configuration >>>>>
3735 23:42:24.949208 [RX_INPUT] configuration <<<<<
3736 23:42:24.952614 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3737 23:42:24.958970 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3738 23:42:24.965742 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3739 23:42:24.972130 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3740 23:42:24.978828 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3741 23:42:24.982400 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3742 23:42:24.988925 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3743 23:42:24.992058 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3744 23:42:24.995298 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3745 23:42:24.998673 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3746 23:42:25.005437 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3747 23:42:25.008815 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3748 23:42:25.012410 ===================================
3749 23:42:25.015729 LPDDR4 DRAM CONFIGURATION
3750 23:42:25.018774 ===================================
3751 23:42:25.019239 EX_ROW_EN[0] = 0x0
3752 23:42:25.022276 EX_ROW_EN[1] = 0x0
3753 23:42:25.022844 LP4Y_EN = 0x0
3754 23:42:25.025410 WORK_FSP = 0x0
3755 23:42:25.026044 WL = 0x2
3756 23:42:25.028615 RL = 0x2
3757 23:42:25.029178 BL = 0x2
3758 23:42:25.032425 RPST = 0x0
3759 23:42:25.032996 RD_PRE = 0x0
3760 23:42:25.035325 WR_PRE = 0x1
3761 23:42:25.035847 WR_PST = 0x0
3762 23:42:25.039116 DBI_WR = 0x0
3763 23:42:25.039686 DBI_RD = 0x0
3764 23:42:25.041802 OTF = 0x1
3765 23:42:25.045581 ===================================
3766 23:42:25.048711 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3767 23:42:25.052322 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3768 23:42:25.058593 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3769 23:42:25.061896 ===================================
3770 23:42:25.064968 LPDDR4 DRAM CONFIGURATION
3771 23:42:25.068307 ===================================
3772 23:42:25.068883 EX_ROW_EN[0] = 0x10
3773 23:42:25.071330 EX_ROW_EN[1] = 0x0
3774 23:42:25.071792 LP4Y_EN = 0x0
3775 23:42:25.074674 WORK_FSP = 0x0
3776 23:42:25.075133 WL = 0x2
3777 23:42:25.078489 RL = 0x2
3778 23:42:25.079077 BL = 0x2
3779 23:42:25.081219 RPST = 0x0
3780 23:42:25.081815 RD_PRE = 0x0
3781 23:42:25.084474 WR_PRE = 0x1
3782 23:42:25.084932 WR_PST = 0x0
3783 23:42:25.087889 DBI_WR = 0x0
3784 23:42:25.088353 DBI_RD = 0x0
3785 23:42:25.091140 OTF = 0x1
3786 23:42:25.094732 ===================================
3787 23:42:25.101265 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3788 23:42:25.104499 nWR fixed to 30
3789 23:42:25.107841 [ModeRegInit_LP4] CH0 RK0
3790 23:42:25.108302 [ModeRegInit_LP4] CH0 RK1
3791 23:42:25.111460 [ModeRegInit_LP4] CH1 RK0
3792 23:42:25.114999 [ModeRegInit_LP4] CH1 RK1
3793 23:42:25.115571 match AC timing 16
3794 23:42:25.121522 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3795 23:42:25.124969 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3796 23:42:25.128113 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3797 23:42:25.134975 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3798 23:42:25.137872 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3799 23:42:25.138335 ==
3800 23:42:25.141219 Dram Type= 6, Freq= 0, CH_0, rank 0
3801 23:42:25.144680 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3802 23:42:25.145248 ==
3803 23:42:25.150971 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3804 23:42:25.157823 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3805 23:42:25.161451 [CA 0] Center 35 (5~66) winsize 62
3806 23:42:25.164387 [CA 1] Center 35 (5~66) winsize 62
3807 23:42:25.167878 [CA 2] Center 34 (4~65) winsize 62
3808 23:42:25.171326 [CA 3] Center 34 (3~65) winsize 63
3809 23:42:25.174679 [CA 4] Center 33 (3~64) winsize 62
3810 23:42:25.177347 [CA 5] Center 33 (3~64) winsize 62
3811 23:42:25.177810
3812 23:42:25.181402 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3813 23:42:25.181967
3814 23:42:25.184191 [CATrainingPosCal] consider 1 rank data
3815 23:42:25.187223 u2DelayCellTimex100 = 270/100 ps
3816 23:42:25.190836 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3817 23:42:25.194271 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3818 23:42:25.197335 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3819 23:42:25.200690 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3820 23:42:25.204190 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3821 23:42:25.210795 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3822 23:42:25.211399
3823 23:42:25.214009 CA PerBit enable=1, Macro0, CA PI delay=33
3824 23:42:25.214571
3825 23:42:25.217466 [CBTSetCACLKResult] CA Dly = 33
3826 23:42:25.218021 CS Dly: 4 (0~35)
3827 23:42:25.218388 ==
3828 23:42:25.220317 Dram Type= 6, Freq= 0, CH_0, rank 1
3829 23:42:25.223896 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3830 23:42:25.227312 ==
3831 23:42:25.230566 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3832 23:42:25.237145 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3833 23:42:25.240775 [CA 0] Center 35 (5~66) winsize 62
3834 23:42:25.244095 [CA 1] Center 35 (5~66) winsize 62
3835 23:42:25.246923 [CA 2] Center 34 (4~65) winsize 62
3836 23:42:25.250408 [CA 3] Center 34 (4~65) winsize 62
3837 23:42:25.253733 [CA 4] Center 33 (3~64) winsize 62
3838 23:42:25.257086 [CA 5] Center 33 (3~64) winsize 62
3839 23:42:25.257595
3840 23:42:25.260264 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3841 23:42:25.260721
3842 23:42:25.263764 [CATrainingPosCal] consider 2 rank data
3843 23:42:25.267371 u2DelayCellTimex100 = 270/100 ps
3844 23:42:25.270243 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3845 23:42:25.273937 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3846 23:42:25.277253 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3847 23:42:25.283659 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3848 23:42:25.287272 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3849 23:42:25.290180 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3850 23:42:25.290686
3851 23:42:25.293329 CA PerBit enable=1, Macro0, CA PI delay=33
3852 23:42:25.293793
3853 23:42:25.296649 [CBTSetCACLKResult] CA Dly = 33
3854 23:42:25.297106 CS Dly: 5 (0~37)
3855 23:42:25.297581
3856 23:42:25.300163 ----->DramcWriteLeveling(PI) begin...
3857 23:42:25.300629 ==
3858 23:42:25.303487 Dram Type= 6, Freq= 0, CH_0, rank 0
3859 23:42:25.310000 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3860 23:42:25.310548 ==
3861 23:42:25.313767 Write leveling (Byte 0): 31 => 31
3862 23:42:25.316927 Write leveling (Byte 1): 30 => 30
3863 23:42:25.317546 DramcWriteLeveling(PI) end<-----
3864 23:42:25.320090
3865 23:42:25.320646 ==
3866 23:42:25.323418 Dram Type= 6, Freq= 0, CH_0, rank 0
3867 23:42:25.326835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3868 23:42:25.327400 ==
3869 23:42:25.330075 [Gating] SW mode calibration
3870 23:42:25.336796 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3871 23:42:25.339665 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3872 23:42:25.346658 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3873 23:42:25.349840 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3874 23:42:25.353349 0 5 8 | B1->B0 | 3030 3030 | 0 0 | (1 1) (1 1)
3875 23:42:25.359982 0 5 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
3876 23:42:25.363478 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3877 23:42:25.366636 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3878 23:42:25.373474 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3879 23:42:25.376752 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3880 23:42:25.379657 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3881 23:42:25.386513 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3882 23:42:25.389336 0 6 8 | B1->B0 | 2d2d 3838 | 0 0 | (0 0) (0 0)
3883 23:42:25.392653 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3884 23:42:25.399526 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3885 23:42:25.402756 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3886 23:42:25.406491 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3887 23:42:25.413066 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3888 23:42:25.416048 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3889 23:42:25.419199 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3890 23:42:25.425904 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3891 23:42:25.429333 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3892 23:42:25.432571 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3893 23:42:25.439643 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3894 23:42:25.442651 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3895 23:42:25.445883 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3896 23:42:25.452452 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3897 23:42:25.456062 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3898 23:42:25.459522 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3899 23:42:25.465977 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3900 23:42:25.469399 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3901 23:42:25.472307 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3902 23:42:25.478972 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3903 23:42:25.482315 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3904 23:42:25.485684 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3905 23:42:25.489001 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3906 23:42:25.495755 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3907 23:42:25.499006 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3908 23:42:25.502323 Total UI for P1: 0, mck2ui 16
3909 23:42:25.505591 best dqsien dly found for B0: ( 0, 9, 8)
3910 23:42:25.508710 Total UI for P1: 0, mck2ui 16
3911 23:42:25.512163 best dqsien dly found for B1: ( 0, 9, 8)
3912 23:42:25.516289 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3913 23:42:25.519360 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
3914 23:42:25.519921
3915 23:42:25.521888 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3916 23:42:25.525784 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
3917 23:42:25.529035 [Gating] SW calibration Done
3918 23:42:25.529661 ==
3919 23:42:25.532172 Dram Type= 6, Freq= 0, CH_0, rank 0
3920 23:42:25.538729 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3921 23:42:25.539301 ==
3922 23:42:25.539668 RX Vref Scan: 0
3923 23:42:25.540010
3924 23:42:25.542035 RX Vref 0 -> 0, step: 1
3925 23:42:25.542495
3926 23:42:25.545138 RX Delay -230 -> 252, step: 16
3927 23:42:25.548891 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3928 23:42:25.552455 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3929 23:42:25.555284 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3930 23:42:25.561645 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3931 23:42:25.565212 iDelay=218, Bit 4, Center 41 (-134 ~ 217) 352
3932 23:42:25.568279 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3933 23:42:25.571727 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3934 23:42:25.578143 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
3935 23:42:25.581658 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3936 23:42:25.584811 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3937 23:42:25.588158 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3938 23:42:25.594951 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3939 23:42:25.598064 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3940 23:42:25.602068 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3941 23:42:25.604437 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3942 23:42:25.611099 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3943 23:42:25.611573 ==
3944 23:42:25.614592 Dram Type= 6, Freq= 0, CH_0, rank 0
3945 23:42:25.617827 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3946 23:42:25.618294 ==
3947 23:42:25.618663 DQS Delay:
3948 23:42:25.620996 DQS0 = 0, DQS1 = 0
3949 23:42:25.621572 DQM Delay:
3950 23:42:25.624373 DQM0 = 38, DQM1 = 33
3951 23:42:25.624833 DQ Delay:
3952 23:42:25.627630 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3953 23:42:25.631251 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =57
3954 23:42:25.634497 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3955 23:42:25.637547 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3956 23:42:25.638123
3957 23:42:25.638476
3958 23:42:25.638787 ==
3959 23:42:25.641118 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 23:42:25.644255 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3961 23:42:25.644676 ==
3962 23:42:25.645005
3963 23:42:25.647584
3964 23:42:25.648014 TX Vref Scan disable
3965 23:42:25.650771 == TX Byte 0 ==
3966 23:42:25.653935 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3967 23:42:25.657950 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3968 23:42:25.660697 == TX Byte 1 ==
3969 23:42:25.664569 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3970 23:42:25.667342 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3971 23:42:25.667765 ==
3972 23:42:25.670483 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 23:42:25.677451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3974 23:42:25.677878 ==
3975 23:42:25.678210
3976 23:42:25.678552
3977 23:42:25.680528 TX Vref Scan disable
3978 23:42:25.680946 == TX Byte 0 ==
3979 23:42:25.687388 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
3980 23:42:25.690715 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
3981 23:42:25.691283 == TX Byte 1 ==
3982 23:42:25.696997 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3983 23:42:25.700291 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3984 23:42:25.700759
3985 23:42:25.701101 [DATLAT]
3986 23:42:25.703621 Freq=600, CH0 RK0
3987 23:42:25.704103
3988 23:42:25.704441 DATLAT Default: 0x9
3989 23:42:25.707258 0, 0xFFFF, sum = 0
3990 23:42:25.707678 1, 0xFFFF, sum = 0
3991 23:42:25.710233 2, 0xFFFF, sum = 0
3992 23:42:25.710693 3, 0xFFFF, sum = 0
3993 23:42:25.713554 4, 0xFFFF, sum = 0
3994 23:42:25.714025 5, 0xFFFF, sum = 0
3995 23:42:25.717056 6, 0xFFFF, sum = 0
3996 23:42:25.717582 7, 0x0, sum = 1
3997 23:42:25.720399 8, 0x0, sum = 2
3998 23:42:25.720986 9, 0x0, sum = 3
3999 23:42:25.723885 10, 0x0, sum = 4
4000 23:42:25.724326 best_step = 8
4001 23:42:25.724654
4002 23:42:25.724956 ==
4003 23:42:25.726946 Dram Type= 6, Freq= 0, CH_0, rank 0
4004 23:42:25.733580 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4005 23:42:25.734218 ==
4006 23:42:25.734729 RX Vref Scan: 1
4007 23:42:25.735212
4008 23:42:25.736667 RX Vref 0 -> 0, step: 1
4009 23:42:25.737162
4010 23:42:25.740250 RX Delay -195 -> 252, step: 8
4011 23:42:25.740792
4012 23:42:25.743530 Set Vref, RX VrefLevel [Byte0]: 46
4013 23:42:25.746815 [Byte1]: 52
4014 23:42:25.747232
4015 23:42:25.749992 Final RX Vref Byte 0 = 46 to rank0
4016 23:42:25.753739 Final RX Vref Byte 1 = 52 to rank0
4017 23:42:25.756890 Final RX Vref Byte 0 = 46 to rank1
4018 23:42:25.760103 Final RX Vref Byte 1 = 52 to rank1==
4019 23:42:25.763630 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 23:42:25.766706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4021 23:42:25.767217 ==
4022 23:42:25.769877 DQS Delay:
4023 23:42:25.770294 DQS0 = 0, DQS1 = 0
4024 23:42:25.770623 DQM Delay:
4025 23:42:25.773657 DQM0 = 39, DQM1 = 30
4026 23:42:25.774069 DQ Delay:
4027 23:42:25.776650 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
4028 23:42:25.780425 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4029 23:42:25.783065 DQ8 =20, DQ9 =12, DQ10 =32, DQ11 =20
4030 23:42:25.786453 DQ12 =40, DQ13 =36, DQ14 =40, DQ15 =40
4031 23:42:25.786893
4032 23:42:25.787281
4033 23:42:25.796652 [DQSOSCAuto] RK0, (LSB)MR18= 0x5656, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4034 23:42:25.799968 CH0 RK0: MR19=808, MR18=5656
4035 23:42:25.802984 CH0_RK0: MR19=0x808, MR18=0x5656, DQSOSC=393, MR23=63, INC=169, DEC=113
4036 23:42:25.803405
4037 23:42:25.806573 ----->DramcWriteLeveling(PI) begin...
4038 23:42:25.810001 ==
4039 23:42:25.813641 Dram Type= 6, Freq= 0, CH_0, rank 1
4040 23:42:25.816376 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4041 23:42:25.816796 ==
4042 23:42:25.819689 Write leveling (Byte 0): 29 => 29
4043 23:42:25.823280 Write leveling (Byte 1): 29 => 29
4044 23:42:25.826769 DramcWriteLeveling(PI) end<-----
4045 23:42:25.827346
4046 23:42:25.827714 ==
4047 23:42:25.829752 Dram Type= 6, Freq= 0, CH_0, rank 1
4048 23:42:25.833268 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4049 23:42:25.833925 ==
4050 23:42:25.836713 [Gating] SW mode calibration
4051 23:42:25.843600 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4052 23:42:25.849821 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4053 23:42:25.853239 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4054 23:42:25.856229 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4055 23:42:25.863037 0 5 8 | B1->B0 | 3131 2f2f | 1 1 | (1 1) (1 1)
4056 23:42:25.866171 0 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4057 23:42:25.869551 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4058 23:42:25.876138 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4059 23:42:25.879335 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4060 23:42:25.882766 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 23:42:25.889802 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 23:42:25.892748 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 23:42:25.895956 0 6 8 | B1->B0 | 2b2b 3131 | 0 1 | (0 0) (0 0)
4064 23:42:25.902471 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 23:42:25.905775 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4066 23:42:25.909372 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4067 23:42:25.915878 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 23:42:25.918770 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 23:42:25.922205 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 23:42:25.929152 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 23:42:25.932477 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4072 23:42:25.935819 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 23:42:25.939420 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 23:42:25.945560 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 23:42:25.948815 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 23:42:25.952112 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 23:42:25.959012 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 23:42:25.962257 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 23:42:25.965535 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 23:42:25.972462 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 23:42:25.975624 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 23:42:25.978743 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 23:42:25.985127 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 23:42:25.989017 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 23:42:25.991818 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 23:42:25.998339 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 23:42:26.001858 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4088 23:42:26.005155 Total UI for P1: 0, mck2ui 16
4089 23:42:26.008203 best dqsien dly found for B0: ( 0, 9, 6)
4090 23:42:26.011438 Total UI for P1: 0, mck2ui 16
4091 23:42:26.015441 best dqsien dly found for B1: ( 0, 9, 6)
4092 23:42:26.018252 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4093 23:42:26.021633 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4094 23:42:26.022120
4095 23:42:26.025047 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4096 23:42:26.028197 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4097 23:42:26.031383 [Gating] SW calibration Done
4098 23:42:26.031845 ==
4099 23:42:26.035077 Dram Type= 6, Freq= 0, CH_0, rank 1
4100 23:42:26.038125 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4101 23:42:26.041576 ==
4102 23:42:26.042036 RX Vref Scan: 0
4103 23:42:26.042406
4104 23:42:26.044714 RX Vref 0 -> 0, step: 1
4105 23:42:26.045272
4106 23:42:26.047935 RX Delay -230 -> 252, step: 16
4107 23:42:26.051537 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4108 23:42:26.054670 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4109 23:42:26.057761 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4110 23:42:26.064765 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4111 23:42:26.068096 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4112 23:42:26.071331 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4113 23:42:26.074738 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4114 23:42:26.077957 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4115 23:42:26.084442 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4116 23:42:26.087987 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4117 23:42:26.090972 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4118 23:42:26.094211 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4119 23:42:26.100826 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4120 23:42:26.104286 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4121 23:42:26.107580 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4122 23:42:26.110846 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4123 23:42:26.114072 ==
4124 23:42:26.114533 Dram Type= 6, Freq= 0, CH_0, rank 1
4125 23:42:26.120857 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4126 23:42:26.121466 ==
4127 23:42:26.121843 DQS Delay:
4128 23:42:26.124083 DQS0 = 0, DQS1 = 0
4129 23:42:26.124565 DQM Delay:
4130 23:42:26.127424 DQM0 = 41, DQM1 = 33
4131 23:42:26.127902 DQ Delay:
4132 23:42:26.130681 DQ0 =33, DQ1 =49, DQ2 =33, DQ3 =33
4133 23:42:26.133979 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4134 23:42:26.137515 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4135 23:42:26.140632 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4136 23:42:26.141151
4137 23:42:26.141658
4138 23:42:26.142112 ==
4139 23:42:26.144056 Dram Type= 6, Freq= 0, CH_0, rank 1
4140 23:42:26.147183 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4141 23:42:26.147655 ==
4142 23:42:26.148026
4143 23:42:26.148370
4144 23:42:26.150632 TX Vref Scan disable
4145 23:42:26.154025 == TX Byte 0 ==
4146 23:42:26.157259 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4147 23:42:26.160549 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4148 23:42:26.164303 == TX Byte 1 ==
4149 23:42:26.167314 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4150 23:42:26.170797 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4151 23:42:26.171263 ==
4152 23:42:26.173816 Dram Type= 6, Freq= 0, CH_0, rank 1
4153 23:42:26.177203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4154 23:42:26.180470 ==
4155 23:42:26.180935
4156 23:42:26.181371
4157 23:42:26.181734 TX Vref Scan disable
4158 23:42:26.184617 == TX Byte 0 ==
4159 23:42:26.187813 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4160 23:42:26.194420 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4161 23:42:26.194909 == TX Byte 1 ==
4162 23:42:26.197512 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4163 23:42:26.204432 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4164 23:42:26.204897
4165 23:42:26.205259 [DATLAT]
4166 23:42:26.205649 Freq=600, CH0 RK1
4167 23:42:26.205997
4168 23:42:26.207769 DATLAT Default: 0x8
4169 23:42:26.208224 0, 0xFFFF, sum = 0
4170 23:42:26.210999 1, 0xFFFF, sum = 0
4171 23:42:26.214193 2, 0xFFFF, sum = 0
4172 23:42:26.214658 3, 0xFFFF, sum = 0
4173 23:42:26.217724 4, 0xFFFF, sum = 0
4174 23:42:26.218145 5, 0xFFFF, sum = 0
4175 23:42:26.220744 6, 0xFFFF, sum = 0
4176 23:42:26.221164 7, 0x0, sum = 1
4177 23:42:26.221551 8, 0x0, sum = 2
4178 23:42:26.224030 9, 0x0, sum = 3
4179 23:42:26.224450 10, 0x0, sum = 4
4180 23:42:26.227387 best_step = 8
4181 23:42:26.227800
4182 23:42:26.228126 ==
4183 23:42:26.231136 Dram Type= 6, Freq= 0, CH_0, rank 1
4184 23:42:26.233924 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4185 23:42:26.234343 ==
4186 23:42:26.237706 RX Vref Scan: 0
4187 23:42:26.238221
4188 23:42:26.238550 RX Vref 0 -> 0, step: 1
4189 23:42:26.238854
4190 23:42:26.240631 RX Delay -195 -> 252, step: 8
4191 23:42:26.248357 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4192 23:42:26.251266 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4193 23:42:26.254586 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4194 23:42:26.257744 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4195 23:42:26.264773 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4196 23:42:26.267799 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4197 23:42:26.271101 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4198 23:42:26.274631 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4199 23:42:26.280898 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4200 23:42:26.284785 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4201 23:42:26.287868 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4202 23:42:26.290856 iDelay=205, Bit 11, Center 20 (-131 ~ 172) 304
4203 23:42:26.297717 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4204 23:42:26.300894 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4205 23:42:26.304439 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4206 23:42:26.307610 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4207 23:42:26.308325 ==
4208 23:42:26.310742 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 23:42:26.317477 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4210 23:42:26.317902 ==
4211 23:42:26.318245 DQS Delay:
4212 23:42:26.320450 DQS0 = 0, DQS1 = 0
4213 23:42:26.320874 DQM Delay:
4214 23:42:26.321207 DQM0 = 40, DQM1 = 32
4215 23:42:26.324217 DQ Delay:
4216 23:42:26.327364 DQ0 =36, DQ1 =40, DQ2 =40, DQ3 =36
4217 23:42:26.330616 DQ4 =44, DQ5 =32, DQ6 =44, DQ7 =48
4218 23:42:26.334205 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =20
4219 23:42:26.337492 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =44
4220 23:42:26.337966
4221 23:42:26.338364
4222 23:42:26.344150 [DQSOSCAuto] RK1, (LSB)MR18= 0x7272, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4223 23:42:26.347164 CH0 RK1: MR19=808, MR18=7272
4224 23:42:26.353828 CH0_RK1: MR19=0x808, MR18=0x7272, DQSOSC=388, MR23=63, INC=174, DEC=116
4225 23:42:26.357260 [RxdqsGatingPostProcess] freq 600
4226 23:42:26.360489 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4227 23:42:26.363690 Pre-setting of DQS Precalculation
4228 23:42:26.370540 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4229 23:42:26.371021 ==
4230 23:42:26.373674 Dram Type= 6, Freq= 0, CH_1, rank 0
4231 23:42:26.377021 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4232 23:42:26.377472 ==
4233 23:42:26.383527 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4234 23:42:26.390281 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4235 23:42:26.393391 [CA 0] Center 35 (5~66) winsize 62
4236 23:42:26.396963 [CA 1] Center 35 (4~66) winsize 63
4237 23:42:26.400162 [CA 2] Center 33 (3~64) winsize 62
4238 23:42:26.403549 [CA 3] Center 33 (3~64) winsize 62
4239 23:42:26.406895 [CA 4] Center 33 (2~64) winsize 63
4240 23:42:26.409938 [CA 5] Center 33 (2~64) winsize 63
4241 23:42:26.410445
4242 23:42:26.413224 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4243 23:42:26.413690
4244 23:42:26.416742 [CATrainingPosCal] consider 1 rank data
4245 23:42:26.420263 u2DelayCellTimex100 = 270/100 ps
4246 23:42:26.423559 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4247 23:42:26.426841 CA1 delay=35 (4~66),Diff = 2 PI (19 cell)
4248 23:42:26.429973 CA2 delay=33 (3~64),Diff = 0 PI (0 cell)
4249 23:42:26.433138 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4250 23:42:26.436784 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
4251 23:42:26.439922 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4252 23:42:26.440551
4253 23:42:26.446659 CA PerBit enable=1, Macro0, CA PI delay=33
4254 23:42:26.447239
4255 23:42:26.447615 [CBTSetCACLKResult] CA Dly = 33
4256 23:42:26.449738 CS Dly: 4 (0~35)
4257 23:42:26.450205 ==
4258 23:42:26.453157 Dram Type= 6, Freq= 0, CH_1, rank 1
4259 23:42:26.456447 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4260 23:42:26.457014 ==
4261 23:42:26.463010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4262 23:42:26.469571 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4263 23:42:26.472843 [CA 0] Center 35 (5~66) winsize 62
4264 23:42:26.476365 [CA 1] Center 34 (4~65) winsize 62
4265 23:42:26.479255 [CA 2] Center 33 (3~64) winsize 62
4266 23:42:26.482358 [CA 3] Center 33 (3~64) winsize 62
4267 23:42:26.486231 [CA 4] Center 32 (2~63) winsize 62
4268 23:42:26.489215 [CA 5] Center 32 (2~63) winsize 62
4269 23:42:26.489720
4270 23:42:26.492344 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4271 23:42:26.492809
4272 23:42:26.495834 [CATrainingPosCal] consider 2 rank data
4273 23:42:26.499154 u2DelayCellTimex100 = 270/100 ps
4274 23:42:26.502352 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4275 23:42:26.505674 CA1 delay=34 (4~65),Diff = 2 PI (19 cell)
4276 23:42:26.509391 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4277 23:42:26.512516 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4278 23:42:26.519176 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4279 23:42:26.522663 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4280 23:42:26.523211
4281 23:42:26.525656 CA PerBit enable=1, Macro0, CA PI delay=32
4282 23:42:26.526121
4283 23:42:26.529172 [CBTSetCACLKResult] CA Dly = 32
4284 23:42:26.529791 CS Dly: 4 (0~36)
4285 23:42:26.530160
4286 23:42:26.532545 ----->DramcWriteLeveling(PI) begin...
4287 23:42:26.533196 ==
4288 23:42:26.535944 Dram Type= 6, Freq= 0, CH_1, rank 0
4289 23:42:26.542530 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4290 23:42:26.543120 ==
4291 23:42:26.545631 Write leveling (Byte 0): 28 => 28
4292 23:42:26.546189 Write leveling (Byte 1): 28 => 28
4293 23:42:26.548906 DramcWriteLeveling(PI) end<-----
4294 23:42:26.549403
4295 23:42:26.552334 ==
4296 23:42:26.552897 Dram Type= 6, Freq= 0, CH_1, rank 0
4297 23:42:26.558708 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4298 23:42:26.559291 ==
4299 23:42:26.562275 [Gating] SW mode calibration
4300 23:42:26.568834 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4301 23:42:26.572487 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4302 23:42:26.579023 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4303 23:42:26.581946 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
4304 23:42:26.585457 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
4305 23:42:26.591978 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4306 23:42:26.595517 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4307 23:42:26.599285 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4308 23:42:26.605401 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4309 23:42:26.608766 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4310 23:42:26.612208 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4311 23:42:26.615426 0 6 4 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)
4312 23:42:26.622536 0 6 8 | B1->B0 | 3838 4545 | 0 0 | (0 0) (1 1)
4313 23:42:26.625479 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4314 23:42:26.628667 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4315 23:42:26.635307 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4316 23:42:26.639073 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4317 23:42:26.642193 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4318 23:42:26.648439 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4319 23:42:26.651909 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4320 23:42:26.655319 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4321 23:42:26.662095 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4322 23:42:26.665412 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4323 23:42:26.668366 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4324 23:42:26.675596 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4325 23:42:26.678408 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4326 23:42:26.681687 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4327 23:42:26.688213 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4328 23:42:26.691856 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4329 23:42:26.695075 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4330 23:42:26.701673 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4331 23:42:26.704922 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4332 23:42:26.708420 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4333 23:42:26.714941 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4334 23:42:26.718618 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4335 23:42:26.721451 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4336 23:42:26.727983 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4337 23:42:26.728516 Total UI for P1: 0, mck2ui 16
4338 23:42:26.734978 best dqsien dly found for B0: ( 0, 9, 6)
4339 23:42:26.737914 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4340 23:42:26.741409 Total UI for P1: 0, mck2ui 16
4341 23:42:26.744721 best dqsien dly found for B1: ( 0, 9, 8)
4342 23:42:26.747974 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4343 23:42:26.751629 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4344 23:42:26.752095
4345 23:42:26.754587 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4346 23:42:26.757655 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4347 23:42:26.761160 [Gating] SW calibration Done
4348 23:42:26.761693 ==
4349 23:42:26.764984 Dram Type= 6, Freq= 0, CH_1, rank 0
4350 23:42:26.767905 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4351 23:42:26.768375 ==
4352 23:42:26.770991 RX Vref Scan: 0
4353 23:42:26.771557
4354 23:42:26.774613 RX Vref 0 -> 0, step: 1
4355 23:42:26.775229
4356 23:42:26.777779 RX Delay -230 -> 252, step: 16
4357 23:42:26.781186 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4358 23:42:26.784341 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4359 23:42:26.787582 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4360 23:42:26.790938 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4361 23:42:26.797557 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4362 23:42:26.800749 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4363 23:42:26.803838 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4364 23:42:26.807021 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4365 23:42:26.813737 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4366 23:42:26.816953 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4367 23:42:26.820622 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4368 23:42:26.823769 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4369 23:42:26.830359 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4370 23:42:26.833680 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4371 23:42:26.837124 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4372 23:42:26.840483 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4373 23:42:26.841038 ==
4374 23:42:26.843637 Dram Type= 6, Freq= 0, CH_1, rank 0
4375 23:42:26.850466 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4376 23:42:26.850881 ==
4377 23:42:26.851331 DQS Delay:
4378 23:42:26.853663 DQS0 = 0, DQS1 = 0
4379 23:42:26.854158 DQM Delay:
4380 23:42:26.854605 DQM0 = 39, DQM1 = 32
4381 23:42:26.856953 DQ Delay:
4382 23:42:26.860843 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4383 23:42:26.863704 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4384 23:42:26.867209 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4385 23:42:26.870226 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4386 23:42:26.870646
4387 23:42:26.870976
4388 23:42:26.871282 ==
4389 23:42:26.873782 Dram Type= 6, Freq= 0, CH_1, rank 0
4390 23:42:26.876942 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4391 23:42:26.877400 ==
4392 23:42:26.877739
4393 23:42:26.878049
4394 23:42:26.880545 TX Vref Scan disable
4395 23:42:26.883868 == TX Byte 0 ==
4396 23:42:26.886849 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4397 23:42:26.890250 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4398 23:42:26.893359 == TX Byte 1 ==
4399 23:42:26.897130 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4400 23:42:26.900233 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4401 23:42:26.900840 ==
4402 23:42:26.904131 Dram Type= 6, Freq= 0, CH_1, rank 0
4403 23:42:26.906753 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4404 23:42:26.907181 ==
4405 23:42:26.910272
4406 23:42:26.910680
4407 23:42:26.911002 TX Vref Scan disable
4408 23:42:26.913664 == TX Byte 0 ==
4409 23:42:26.917157 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4410 23:42:26.923642 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4411 23:42:26.924140 == TX Byte 1 ==
4412 23:42:26.927549 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4413 23:42:26.933856 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4414 23:42:26.934362
4415 23:42:26.934688 [DATLAT]
4416 23:42:26.934988 Freq=600, CH1 RK0
4417 23:42:26.935281
4418 23:42:26.936992 DATLAT Default: 0x9
4419 23:42:26.937434 0, 0xFFFF, sum = 0
4420 23:42:26.940148 1, 0xFFFF, sum = 0
4421 23:42:26.943843 2, 0xFFFF, sum = 0
4422 23:42:26.944260 3, 0xFFFF, sum = 0
4423 23:42:26.947115 4, 0xFFFF, sum = 0
4424 23:42:26.947638 5, 0xFFFF, sum = 0
4425 23:42:26.950211 6, 0xFFFF, sum = 0
4426 23:42:26.950730 7, 0x0, sum = 1
4427 23:42:26.951064 8, 0x0, sum = 2
4428 23:42:26.953842 9, 0x0, sum = 3
4429 23:42:26.954359 10, 0x0, sum = 4
4430 23:42:26.956887 best_step = 8
4431 23:42:26.957473
4432 23:42:26.957804 ==
4433 23:42:26.960336 Dram Type= 6, Freq= 0, CH_1, rank 0
4434 23:42:26.963790 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4435 23:42:26.964306 ==
4436 23:42:26.966978 RX Vref Scan: 1
4437 23:42:26.967491
4438 23:42:26.967828 RX Vref 0 -> 0, step: 1
4439 23:42:26.968134
4440 23:42:26.970173 RX Delay -195 -> 252, step: 8
4441 23:42:26.970595
4442 23:42:26.973401 Set Vref, RX VrefLevel [Byte0]: 52
4443 23:42:26.976693 [Byte1]: 49
4444 23:42:26.980834
4445 23:42:26.981355 Final RX Vref Byte 0 = 52 to rank0
4446 23:42:26.984173 Final RX Vref Byte 1 = 49 to rank0
4447 23:42:26.987267 Final RX Vref Byte 0 = 52 to rank1
4448 23:42:26.991007 Final RX Vref Byte 1 = 49 to rank1==
4449 23:42:26.993983 Dram Type= 6, Freq= 0, CH_1, rank 0
4450 23:42:27.000739 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4451 23:42:27.001213 ==
4452 23:42:27.001630 DQS Delay:
4453 23:42:27.003930 DQS0 = 0, DQS1 = 0
4454 23:42:27.004398 DQM Delay:
4455 23:42:27.004776 DQM0 = 37, DQM1 = 31
4456 23:42:27.007279 DQ Delay:
4457 23:42:27.010279 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4458 23:42:27.013812 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4459 23:42:27.017196 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =24
4460 23:42:27.020168 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4461 23:42:27.020627
4462 23:42:27.020984
4463 23:42:27.026978 [DQSOSCAuto] RK0, (LSB)MR18= 0x7474, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 388 ps
4464 23:42:27.030185 CH1 RK0: MR19=808, MR18=7474
4465 23:42:27.036790 CH1_RK0: MR19=0x808, MR18=0x7474, DQSOSC=388, MR23=63, INC=174, DEC=116
4466 23:42:27.037366
4467 23:42:27.040042 ----->DramcWriteLeveling(PI) begin...
4468 23:42:27.040506 ==
4469 23:42:27.043503 Dram Type= 6, Freq= 0, CH_1, rank 1
4470 23:42:27.046783 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4471 23:42:27.047318 ==
4472 23:42:27.049985 Write leveling (Byte 0): 27 => 27
4473 23:42:27.053245 Write leveling (Byte 1): 27 => 27
4474 23:42:27.056756 DramcWriteLeveling(PI) end<-----
4475 23:42:27.057213
4476 23:42:27.057605 ==
4477 23:42:27.060069 Dram Type= 6, Freq= 0, CH_1, rank 1
4478 23:42:27.063549 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4479 23:42:27.066655 ==
4480 23:42:27.067220 [Gating] SW mode calibration
4481 23:42:27.073677 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4482 23:42:27.080127 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4483 23:42:27.083294 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4484 23:42:27.089796 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
4485 23:42:27.092884 0 5 8 | B1->B0 | 2f2f 2727 | 0 0 | (0 0) (1 1)
4486 23:42:27.096239 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 23:42:27.102821 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 23:42:27.106206 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 23:42:27.109260 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 23:42:27.116370 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 23:42:27.119643 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 23:42:27.122967 0 6 4 | B1->B0 | 2424 3030 | 0 0 | (0 0) (1 1)
4493 23:42:27.129340 0 6 8 | B1->B0 | 2f2f 4040 | 1 0 | (0 0) (0 0)
4494 23:42:27.132908 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 23:42:27.136518 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 23:42:27.142391 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 23:42:27.145766 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 23:42:27.149100 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 23:42:27.156221 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 23:42:27.159080 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4501 23:42:27.162486 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4502 23:42:27.169064 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 23:42:27.172496 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 23:42:27.175794 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 23:42:27.182227 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 23:42:27.185852 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 23:42:27.189064 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 23:42:27.196212 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 23:42:27.199229 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 23:42:27.202051 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 23:42:27.209008 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 23:42:27.212260 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 23:42:27.215624 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 23:42:27.222225 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 23:42:27.225230 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 23:42:27.229023 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4517 23:42:27.232311 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 23:42:27.235815 Total UI for P1: 0, mck2ui 16
4519 23:42:27.238536 best dqsien dly found for B0: ( 0, 9, 4)
4520 23:42:27.241969 Total UI for P1: 0, mck2ui 16
4521 23:42:27.245589 best dqsien dly found for B1: ( 0, 9, 6)
4522 23:42:27.248978 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4523 23:42:27.252027 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4524 23:42:27.255924
4525 23:42:27.258302 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4526 23:42:27.262061 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4527 23:42:27.265394 [Gating] SW calibration Done
4528 23:42:27.265958 ==
4529 23:42:27.268593 Dram Type= 6, Freq= 0, CH_1, rank 1
4530 23:42:27.271910 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4531 23:42:27.272471 ==
4532 23:42:27.272837 RX Vref Scan: 0
4533 23:42:27.275101
4534 23:42:27.275656 RX Vref 0 -> 0, step: 1
4535 23:42:27.276020
4536 23:42:27.278653 RX Delay -230 -> 252, step: 16
4537 23:42:27.281864 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4538 23:42:27.288331 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4539 23:42:27.291577 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4540 23:42:27.295588 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4541 23:42:27.298089 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4542 23:42:27.301848 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4543 23:42:27.308016 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4544 23:42:27.311662 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4545 23:42:27.314877 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4546 23:42:27.318085 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4547 23:42:27.325080 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4548 23:42:27.328307 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4549 23:42:27.331427 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4550 23:42:27.335017 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4551 23:42:27.341248 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4552 23:42:27.344835 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4553 23:42:27.345454 ==
4554 23:42:27.347862 Dram Type= 6, Freq= 0, CH_1, rank 1
4555 23:42:27.351420 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4556 23:42:27.351998 ==
4557 23:42:27.354602 DQS Delay:
4558 23:42:27.355175 DQS0 = 0, DQS1 = 0
4559 23:42:27.355547 DQM Delay:
4560 23:42:27.357955 DQM0 = 42, DQM1 = 35
4561 23:42:27.358526 DQ Delay:
4562 23:42:27.360807 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4563 23:42:27.364315 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4564 23:42:27.367734 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4565 23:42:27.370989 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4566 23:42:27.371569
4567 23:42:27.371942
4568 23:42:27.372287 ==
4569 23:42:27.374733 Dram Type= 6, Freq= 0, CH_1, rank 1
4570 23:42:27.380754 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4571 23:42:27.381342 ==
4572 23:42:27.381716
4573 23:42:27.382061
4574 23:42:27.382388 TX Vref Scan disable
4575 23:42:27.384611 == TX Byte 0 ==
4576 23:42:27.388045 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4577 23:42:27.394403 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4578 23:42:27.394948 == TX Byte 1 ==
4579 23:42:27.397843 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4580 23:42:27.404391 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4581 23:42:27.404889 ==
4582 23:42:27.408068 Dram Type= 6, Freq= 0, CH_1, rank 1
4583 23:42:27.411207 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4584 23:42:27.411733 ==
4585 23:42:27.412224
4586 23:42:27.412673
4587 23:42:27.414507 TX Vref Scan disable
4588 23:42:27.417979 == TX Byte 0 ==
4589 23:42:27.421123 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4590 23:42:27.424187 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4591 23:42:27.427722 == TX Byte 1 ==
4592 23:42:27.430941 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4593 23:42:27.434108 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4594 23:42:27.434593
4595 23:42:27.435079 [DATLAT]
4596 23:42:27.437497 Freq=600, CH1 RK1
4597 23:42:27.437984
4598 23:42:27.438472 DATLAT Default: 0x8
4599 23:42:27.440812 0, 0xFFFF, sum = 0
4600 23:42:27.444432 1, 0xFFFF, sum = 0
4601 23:42:27.444994 2, 0xFFFF, sum = 0
4602 23:42:27.447883 3, 0xFFFF, sum = 0
4603 23:42:27.448371 4, 0xFFFF, sum = 0
4604 23:42:27.450741 5, 0xFFFF, sum = 0
4605 23:42:27.451230 6, 0xFFFF, sum = 0
4606 23:42:27.454274 7, 0x0, sum = 1
4607 23:42:27.454840 8, 0x0, sum = 2
4608 23:42:27.455340 9, 0x0, sum = 3
4609 23:42:27.457334 10, 0x0, sum = 4
4610 23:42:27.457827 best_step = 8
4611 23:42:27.458306
4612 23:42:27.458759 ==
4613 23:42:27.460912 Dram Type= 6, Freq= 0, CH_1, rank 1
4614 23:42:27.467257 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4615 23:42:27.467829 ==
4616 23:42:27.468323 RX Vref Scan: 0
4617 23:42:27.468779
4618 23:42:27.471033 RX Vref 0 -> 0, step: 1
4619 23:42:27.471516
4620 23:42:27.473851 RX Delay -195 -> 252, step: 8
4621 23:42:27.477341 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4622 23:42:27.484126 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4623 23:42:27.487336 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4624 23:42:27.490433 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4625 23:42:27.493823 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4626 23:42:27.500610 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4627 23:42:27.503897 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4628 23:42:27.507024 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4629 23:42:27.510293 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4630 23:42:27.513717 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4631 23:42:27.520334 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4632 23:42:27.523776 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4633 23:42:27.527010 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4634 23:42:27.530490 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4635 23:42:27.537149 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4636 23:42:27.540357 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4637 23:42:27.540951 ==
4638 23:42:27.543477 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 23:42:27.546840 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4640 23:42:27.547410 ==
4641 23:42:27.549982 DQS Delay:
4642 23:42:27.550464 DQS0 = 0, DQS1 = 0
4643 23:42:27.553892 DQM Delay:
4644 23:42:27.554458 DQM0 = 37, DQM1 = 29
4645 23:42:27.554945 DQ Delay:
4646 23:42:27.557098 DQ0 =40, DQ1 =32, DQ2 =32, DQ3 =32
4647 23:42:27.560310 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4648 23:42:27.563584 DQ8 =12, DQ9 =20, DQ10 =32, DQ11 =20
4649 23:42:27.566790 DQ12 =36, DQ13 =40, DQ14 =36, DQ15 =40
4650 23:42:27.567353
4651 23:42:27.567842
4652 23:42:27.576952 [DQSOSCAuto] RK1, (LSB)MR18= 0x6161, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4653 23:42:27.580290 CH1 RK1: MR19=808, MR18=6161
4654 23:42:27.586900 CH1_RK1: MR19=0x808, MR18=0x6161, DQSOSC=391, MR23=63, INC=171, DEC=114
4655 23:42:27.587513 [RxdqsGatingPostProcess] freq 600
4656 23:42:27.593455 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4657 23:42:27.596972 Pre-setting of DQS Precalculation
4658 23:42:27.600126 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4659 23:42:27.609870 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4660 23:42:27.616667 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4661 23:42:27.617159
4662 23:42:27.617578
4663 23:42:27.619558 [Calibration Summary] 1200 Mbps
4664 23:42:27.620024 CH 0, Rank 0
4665 23:42:27.623084 SW Impedance : PASS
4666 23:42:27.623551 DUTY Scan : NO K
4667 23:42:27.626402 ZQ Calibration : PASS
4668 23:42:27.629487 Jitter Meter : NO K
4669 23:42:27.629955 CBT Training : PASS
4670 23:42:27.632891 Write leveling : PASS
4671 23:42:27.636648 RX DQS gating : PASS
4672 23:42:27.637179 RX DQ/DQS(RDDQC) : PASS
4673 23:42:27.639770 TX DQ/DQS : PASS
4674 23:42:27.642868 RX DATLAT : PASS
4675 23:42:27.643335 RX DQ/DQS(Engine): PASS
4676 23:42:27.646263 TX OE : NO K
4677 23:42:27.646731 All Pass.
4678 23:42:27.647102
4679 23:42:27.649539 CH 0, Rank 1
4680 23:42:27.650003 SW Impedance : PASS
4681 23:42:27.653075 DUTY Scan : NO K
4682 23:42:27.656329 ZQ Calibration : PASS
4683 23:42:27.656862 Jitter Meter : NO K
4684 23:42:27.659460 CBT Training : PASS
4685 23:42:27.662802 Write leveling : PASS
4686 23:42:27.663274 RX DQS gating : PASS
4687 23:42:27.665934 RX DQ/DQS(RDDQC) : PASS
4688 23:42:27.666493 TX DQ/DQS : PASS
4689 23:42:27.669827 RX DATLAT : PASS
4690 23:42:27.672850 RX DQ/DQS(Engine): PASS
4691 23:42:27.673451 TX OE : NO K
4692 23:42:27.675884 All Pass.
4693 23:42:27.676352
4694 23:42:27.676730 CH 1, Rank 0
4695 23:42:27.679317 SW Impedance : PASS
4696 23:42:27.679871 DUTY Scan : NO K
4697 23:42:27.682629 ZQ Calibration : PASS
4698 23:42:27.685878 Jitter Meter : NO K
4699 23:42:27.686387 CBT Training : PASS
4700 23:42:27.689319 Write leveling : PASS
4701 23:42:27.692804 RX DQS gating : PASS
4702 23:42:27.693266 RX DQ/DQS(RDDQC) : PASS
4703 23:42:27.696245 TX DQ/DQS : PASS
4704 23:42:27.699804 RX DATLAT : PASS
4705 23:42:27.700264 RX DQ/DQS(Engine): PASS
4706 23:42:27.702688 TX OE : NO K
4707 23:42:27.703149 All Pass.
4708 23:42:27.703706
4709 23:42:27.705884 CH 1, Rank 1
4710 23:42:27.706498 SW Impedance : PASS
4711 23:42:27.709410 DUTY Scan : NO K
4712 23:42:27.712616 ZQ Calibration : PASS
4713 23:42:27.713074 Jitter Meter : NO K
4714 23:42:27.716048 CBT Training : PASS
4715 23:42:27.719207 Write leveling : PASS
4716 23:42:27.719738 RX DQS gating : PASS
4717 23:42:27.722501 RX DQ/DQS(RDDQC) : PASS
4718 23:42:27.722958 TX DQ/DQS : PASS
4719 23:42:27.725840 RX DATLAT : PASS
4720 23:42:27.729275 RX DQ/DQS(Engine): PASS
4721 23:42:27.729776 TX OE : NO K
4722 23:42:27.732582 All Pass.
4723 23:42:27.733114
4724 23:42:27.733602 DramC Write-DBI off
4725 23:42:27.735793 PER_BANK_REFRESH: Hybrid Mode
4726 23:42:27.739122 TX_TRACKING: ON
4727 23:42:27.745938 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4728 23:42:27.749258 [FAST_K] Save calibration result to emmc
4729 23:42:27.752581 dramc_set_vcore_voltage set vcore to 662500
4730 23:42:27.755784 Read voltage for 933, 3
4731 23:42:27.756239 Vio18 = 0
4732 23:42:27.758839 Vcore = 662500
4733 23:42:27.759297 Vdram = 0
4734 23:42:27.759661 Vddq = 0
4735 23:42:27.762515 Vmddr = 0
4736 23:42:27.765418 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4737 23:42:27.772057 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4738 23:42:27.772596 MEM_TYPE=3, freq_sel=17
4739 23:42:27.775414 sv_algorithm_assistance_LP4_1600
4740 23:42:27.782364 ============ PULL DRAM RESETB DOWN ============
4741 23:42:27.785244 ========== PULL DRAM RESETB DOWN end =========
4742 23:42:27.788876 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4743 23:42:27.792229 ===================================
4744 23:42:27.795544 LPDDR4 DRAM CONFIGURATION
4745 23:42:27.798392 ===================================
4746 23:42:27.802467 EX_ROW_EN[0] = 0x0
4747 23:42:27.802925 EX_ROW_EN[1] = 0x0
4748 23:42:27.804988 LP4Y_EN = 0x0
4749 23:42:27.805605 WORK_FSP = 0x0
4750 23:42:27.808364 WL = 0x3
4751 23:42:27.808824 RL = 0x3
4752 23:42:27.811755 BL = 0x2
4753 23:42:27.812215 RPST = 0x0
4754 23:42:27.815267 RD_PRE = 0x0
4755 23:42:27.815726 WR_PRE = 0x1
4756 23:42:27.818385 WR_PST = 0x0
4757 23:42:27.818842 DBI_WR = 0x0
4758 23:42:27.821487 DBI_RD = 0x0
4759 23:42:27.821946 OTF = 0x1
4760 23:42:27.825141 ===================================
4761 23:42:27.828427 ===================================
4762 23:42:27.832078 ANA top config
4763 23:42:27.835215 ===================================
4764 23:42:27.838702 DLL_ASYNC_EN = 0
4765 23:42:27.839267 ALL_SLAVE_EN = 1
4766 23:42:27.841578 NEW_RANK_MODE = 1
4767 23:42:27.845575 DLL_IDLE_MODE = 1
4768 23:42:27.848464 LP45_APHY_COMB_EN = 1
4769 23:42:27.849081 TX_ODT_DIS = 1
4770 23:42:27.851803 NEW_8X_MODE = 1
4771 23:42:27.854739 ===================================
4772 23:42:27.857969 ===================================
4773 23:42:27.861380 data_rate = 1866
4774 23:42:27.865028 CKR = 1
4775 23:42:27.868211 DQ_P2S_RATIO = 8
4776 23:42:27.871411 ===================================
4777 23:42:27.874625 CA_P2S_RATIO = 8
4778 23:42:27.877808 DQ_CA_OPEN = 0
4779 23:42:27.878272 DQ_SEMI_OPEN = 0
4780 23:42:27.881595 CA_SEMI_OPEN = 0
4781 23:42:27.884467 CA_FULL_RATE = 0
4782 23:42:27.888095 DQ_CKDIV4_EN = 1
4783 23:42:27.891451 CA_CKDIV4_EN = 1
4784 23:42:27.894361 CA_PREDIV_EN = 0
4785 23:42:27.894826 PH8_DLY = 0
4786 23:42:27.897502 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4787 23:42:27.900735 DQ_AAMCK_DIV = 4
4788 23:42:27.904377 CA_AAMCK_DIV = 4
4789 23:42:27.907648 CA_ADMCK_DIV = 4
4790 23:42:27.910618 DQ_TRACK_CA_EN = 0
4791 23:42:27.911242 CA_PICK = 933
4792 23:42:27.913999 CA_MCKIO = 933
4793 23:42:27.917246 MCKIO_SEMI = 0
4794 23:42:27.920810 PLL_FREQ = 3732
4795 23:42:27.924356 DQ_UI_PI_RATIO = 32
4796 23:42:27.927243 CA_UI_PI_RATIO = 0
4797 23:42:27.930765 ===================================
4798 23:42:27.934148 ===================================
4799 23:42:27.937619 memory_type:LPDDR4
4800 23:42:27.938245 GP_NUM : 10
4801 23:42:27.940538 SRAM_EN : 1
4802 23:42:27.940995 MD32_EN : 0
4803 23:42:27.944093 ===================================
4804 23:42:27.947464 [ANA_INIT] >>>>>>>>>>>>>>
4805 23:42:27.950627 <<<<<< [CONFIGURE PHASE]: ANA_TX
4806 23:42:27.953931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4807 23:42:27.957081 ===================================
4808 23:42:27.960695 data_rate = 1866,PCW = 0X8f00
4809 23:42:27.964086 ===================================
4810 23:42:27.967391 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4811 23:42:27.970285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4812 23:42:27.977039 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4813 23:42:27.980254 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4814 23:42:27.987184 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4815 23:42:27.990375 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4816 23:42:27.990799 [ANA_INIT] flow start
4817 23:42:27.994155 [ANA_INIT] PLL >>>>>>>>
4818 23:42:27.997170 [ANA_INIT] PLL <<<<<<<<
4819 23:42:27.997829 [ANA_INIT] MIDPI >>>>>>>>
4820 23:42:28.000104 [ANA_INIT] MIDPI <<<<<<<<
4821 23:42:28.003482 [ANA_INIT] DLL >>>>>>>>
4822 23:42:28.003961 [ANA_INIT] flow end
4823 23:42:28.007066 ============ LP4 DIFF to SE enter ============
4824 23:42:28.013361 ============ LP4 DIFF to SE exit ============
4825 23:42:28.013794 [ANA_INIT] <<<<<<<<<<<<<
4826 23:42:28.016892 [Flow] Enable top DCM control >>>>>
4827 23:42:28.020055 [Flow] Enable top DCM control <<<<<
4828 23:42:28.023042 Enable DLL master slave shuffle
4829 23:42:28.030105 ==============================================================
4830 23:42:28.033276 Gating Mode config
4831 23:42:28.036853 ==============================================================
4832 23:42:28.039851 Config description:
4833 23:42:28.050120 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4834 23:42:28.056441 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4835 23:42:28.060117 SELPH_MODE 0: By rank 1: By Phase
4836 23:42:28.066681 ==============================================================
4837 23:42:28.070182 GAT_TRACK_EN = 1
4838 23:42:28.073413 RX_GATING_MODE = 2
4839 23:42:28.073914 RX_GATING_TRACK_MODE = 2
4840 23:42:28.076716 SELPH_MODE = 1
4841 23:42:28.080172 PICG_EARLY_EN = 1
4842 23:42:28.083155 VALID_LAT_VALUE = 1
4843 23:42:28.090055 ==============================================================
4844 23:42:28.093360 Enter into Gating configuration >>>>
4845 23:42:28.096561 Exit from Gating configuration <<<<
4846 23:42:28.099625 Enter into DVFS_PRE_config >>>>>
4847 23:42:28.109719 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4848 23:42:28.113116 Exit from DVFS_PRE_config <<<<<
4849 23:42:28.116400 Enter into PICG configuration >>>>
4850 23:42:28.119778 Exit from PICG configuration <<<<
4851 23:42:28.123231 [RX_INPUT] configuration >>>>>
4852 23:42:28.126234 [RX_INPUT] configuration <<<<<
4853 23:42:28.129573 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4854 23:42:28.136941 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4855 23:42:28.143011 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4856 23:42:28.149979 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4857 23:42:28.152894 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4858 23:42:28.159382 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4859 23:42:28.166088 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4860 23:42:28.169335 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4861 23:42:28.172514 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4862 23:42:28.175784 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4863 23:42:28.182301 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4864 23:42:28.185487 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4865 23:42:28.188799 ===================================
4866 23:42:28.192257 LPDDR4 DRAM CONFIGURATION
4867 23:42:28.195815 ===================================
4868 23:42:28.196232 EX_ROW_EN[0] = 0x0
4869 23:42:28.199323 EX_ROW_EN[1] = 0x0
4870 23:42:28.199744 LP4Y_EN = 0x0
4871 23:42:28.202422 WORK_FSP = 0x0
4872 23:42:28.202968 WL = 0x3
4873 23:42:28.205796 RL = 0x3
4874 23:42:28.206251 BL = 0x2
4875 23:42:28.208962 RPST = 0x0
4876 23:42:28.209415 RD_PRE = 0x0
4877 23:42:28.212453 WR_PRE = 0x1
4878 23:42:28.212876 WR_PST = 0x0
4879 23:42:28.215550 DBI_WR = 0x0
4880 23:42:28.215975 DBI_RD = 0x0
4881 23:42:28.218994 OTF = 0x1
4882 23:42:28.222331 ===================================
4883 23:42:28.225624 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4884 23:42:28.229241 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4885 23:42:28.236047 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4886 23:42:28.239539 ===================================
4887 23:42:28.239966 LPDDR4 DRAM CONFIGURATION
4888 23:42:28.242475 ===================================
4889 23:42:28.245906 EX_ROW_EN[0] = 0x10
4890 23:42:28.249536 EX_ROW_EN[1] = 0x0
4891 23:42:28.250047 LP4Y_EN = 0x0
4892 23:42:28.252333 WORK_FSP = 0x0
4893 23:42:28.252862 WL = 0x3
4894 23:42:28.255395 RL = 0x3
4895 23:42:28.255832 BL = 0x2
4896 23:42:28.258680 RPST = 0x0
4897 23:42:28.259118 RD_PRE = 0x0
4898 23:42:28.262359 WR_PRE = 0x1
4899 23:42:28.262838 WR_PST = 0x0
4900 23:42:28.265676 DBI_WR = 0x0
4901 23:42:28.266111 DBI_RD = 0x0
4902 23:42:28.268973 OTF = 0x1
4903 23:42:28.272289 ===================================
4904 23:42:28.278815 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4905 23:42:28.281988 nWR fixed to 30
4906 23:42:28.285521 [ModeRegInit_LP4] CH0 RK0
4907 23:42:28.286179 [ModeRegInit_LP4] CH0 RK1
4908 23:42:28.288424 [ModeRegInit_LP4] CH1 RK0
4909 23:42:28.292139 [ModeRegInit_LP4] CH1 RK1
4910 23:42:28.292726 match AC timing 8
4911 23:42:28.298529 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4912 23:42:28.301778 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4913 23:42:28.305105 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4914 23:42:28.311733 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4915 23:42:28.314748 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4916 23:42:28.315218 ==
4917 23:42:28.318105 Dram Type= 6, Freq= 0, CH_0, rank 0
4918 23:42:28.321440 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4919 23:42:28.321911 ==
4920 23:42:28.327994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4921 23:42:28.334871 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4922 23:42:28.338575 [CA 0] Center 38 (8~69) winsize 62
4923 23:42:28.341502 [CA 1] Center 38 (8~69) winsize 62
4924 23:42:28.345107 [CA 2] Center 36 (6~67) winsize 62
4925 23:42:28.348392 [CA 3] Center 36 (5~67) winsize 63
4926 23:42:28.351352 [CA 4] Center 34 (4~65) winsize 62
4927 23:42:28.354936 [CA 5] Center 34 (4~65) winsize 62
4928 23:42:28.355498
4929 23:42:28.358348 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4930 23:42:28.358912
4931 23:42:28.361347 [CATrainingPosCal] consider 1 rank data
4932 23:42:28.365405 u2DelayCellTimex100 = 270/100 ps
4933 23:42:28.368159 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4934 23:42:28.371384 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4935 23:42:28.374413 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4936 23:42:28.377634 CA3 delay=36 (5~67),Diff = 2 PI (12 cell)
4937 23:42:28.381047 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4938 23:42:28.388214 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4939 23:42:28.388698
4940 23:42:28.391396 CA PerBit enable=1, Macro0, CA PI delay=34
4941 23:42:28.391982
4942 23:42:28.394377 [CBTSetCACLKResult] CA Dly = 34
4943 23:42:28.394865 CS Dly: 7 (0~38)
4944 23:42:28.395346 ==
4945 23:42:28.397767 Dram Type= 6, Freq= 0, CH_0, rank 1
4946 23:42:28.401203 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4947 23:42:28.404150 ==
4948 23:42:28.407218 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4949 23:42:28.413897 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4950 23:42:28.417444 [CA 0] Center 38 (8~69) winsize 62
4951 23:42:28.420757 [CA 1] Center 38 (7~69) winsize 63
4952 23:42:28.424466 [CA 2] Center 36 (6~66) winsize 61
4953 23:42:28.427564 [CA 3] Center 35 (5~66) winsize 62
4954 23:42:28.430805 [CA 4] Center 34 (4~64) winsize 61
4955 23:42:28.433885 [CA 5] Center 34 (4~65) winsize 62
4956 23:42:28.434371
4957 23:42:28.437235 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4958 23:42:28.437763
4959 23:42:28.440618 [CATrainingPosCal] consider 2 rank data
4960 23:42:28.443952 u2DelayCellTimex100 = 270/100 ps
4961 23:42:28.447069 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4962 23:42:28.450760 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4963 23:42:28.457055 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
4964 23:42:28.460290 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
4965 23:42:28.463745 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
4966 23:42:28.467087 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4967 23:42:28.467650
4968 23:42:28.470955 CA PerBit enable=1, Macro0, CA PI delay=34
4969 23:42:28.471436
4970 23:42:28.473677 [CBTSetCACLKResult] CA Dly = 34
4971 23:42:28.474245 CS Dly: 7 (0~39)
4972 23:42:28.474735
4973 23:42:28.476900 ----->DramcWriteLeveling(PI) begin...
4974 23:42:28.480074 ==
4975 23:42:28.483336 Dram Type= 6, Freq= 0, CH_0, rank 0
4976 23:42:28.486626 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4977 23:42:28.487111 ==
4978 23:42:28.490526 Write leveling (Byte 0): 31 => 31
4979 23:42:28.493097 Write leveling (Byte 1): 29 => 29
4980 23:42:28.497440 DramcWriteLeveling(PI) end<-----
4981 23:42:28.497996
4982 23:42:28.498486 ==
4983 23:42:28.499966 Dram Type= 6, Freq= 0, CH_0, rank 0
4984 23:42:28.503582 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4985 23:42:28.504055 ==
4986 23:42:28.506268 [Gating] SW mode calibration
4987 23:42:28.513081 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4988 23:42:28.519466 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4989 23:42:28.523613 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4990 23:42:28.526635 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4991 23:42:28.533057 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4992 23:42:28.536245 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4993 23:42:28.539494 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4994 23:42:28.545948 0 10 20 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 1)
4995 23:42:28.549198 0 10 24 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (1 0)
4996 23:42:28.552642 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4997 23:42:28.559265 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4998 23:42:28.562497 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4999 23:42:28.565943 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5000 23:42:28.573068 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5001 23:42:28.576481 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5002 23:42:28.579636 0 11 20 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5003 23:42:28.586042 0 11 24 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5004 23:42:28.589457 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5005 23:42:28.592916 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5006 23:42:28.599593 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5007 23:42:28.602668 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5008 23:42:28.605758 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5009 23:42:28.612224 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5010 23:42:28.615710 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5011 23:42:28.618738 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5012 23:42:28.625436 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5013 23:42:28.629116 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5014 23:42:28.632193 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5015 23:42:28.638983 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5016 23:42:28.641842 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5017 23:42:28.645085 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5018 23:42:28.652289 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5019 23:42:28.655466 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5020 23:42:28.659007 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5021 23:42:28.665975 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5022 23:42:28.668821 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5023 23:42:28.671718 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5024 23:42:28.678352 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5025 23:42:28.681766 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5026 23:42:28.685654 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5027 23:42:28.688560 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5028 23:42:28.691891 Total UI for P1: 0, mck2ui 16
5029 23:42:28.695437 best dqsien dly found for B0: ( 0, 14, 20)
5030 23:42:28.698346 Total UI for P1: 0, mck2ui 16
5031 23:42:28.701721 best dqsien dly found for B1: ( 0, 14, 20)
5032 23:42:28.708031 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5033 23:42:28.711612 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5034 23:42:28.712177
5035 23:42:28.714622 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5036 23:42:28.718219 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5037 23:42:28.721386 [Gating] SW calibration Done
5038 23:42:28.721992 ==
5039 23:42:28.724568 Dram Type= 6, Freq= 0, CH_0, rank 0
5040 23:42:28.728078 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5041 23:42:28.728653 ==
5042 23:42:28.731307 RX Vref Scan: 0
5043 23:42:28.731881
5044 23:42:28.732261 RX Vref 0 -> 0, step: 1
5045 23:42:28.732611
5046 23:42:28.734507 RX Delay -80 -> 252, step: 8
5047 23:42:28.737653 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5048 23:42:28.744376 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5049 23:42:28.747668 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5050 23:42:28.751057 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5051 23:42:28.754580 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5052 23:42:28.757906 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5053 23:42:28.761205 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5054 23:42:28.767730 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5055 23:42:28.770793 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5056 23:42:28.774203 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5057 23:42:28.777443 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5058 23:42:28.780650 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5059 23:42:28.787232 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5060 23:42:28.790738 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5061 23:42:28.794246 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5062 23:42:28.797223 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5063 23:42:28.797825 ==
5064 23:42:28.800734 Dram Type= 6, Freq= 0, CH_0, rank 0
5065 23:42:28.804046 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5066 23:42:28.807081 ==
5067 23:42:28.807551 DQS Delay:
5068 23:42:28.807943 DQS0 = 0, DQS1 = 0
5069 23:42:28.810447 DQM Delay:
5070 23:42:28.810911 DQM0 = 95, DQM1 = 87
5071 23:42:28.813766 DQ Delay:
5072 23:42:28.817038 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5073 23:42:28.820545 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5074 23:42:28.823852 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =79
5075 23:42:28.827104 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =91
5076 23:42:28.827679
5077 23:42:28.828053
5078 23:42:28.828394 ==
5079 23:42:28.830090 Dram Type= 6, Freq= 0, CH_0, rank 0
5080 23:42:28.833397 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5081 23:42:28.833866 ==
5082 23:42:28.834236
5083 23:42:28.834583
5084 23:42:28.836631 TX Vref Scan disable
5085 23:42:28.837096 == TX Byte 0 ==
5086 23:42:28.843647 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5087 23:42:28.847051 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5088 23:42:28.847522 == TX Byte 1 ==
5089 23:42:28.853886 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5090 23:42:28.857040 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5091 23:42:28.857669 ==
5092 23:42:28.860488 Dram Type= 6, Freq= 0, CH_0, rank 0
5093 23:42:28.863318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5094 23:42:28.863793 ==
5095 23:42:28.864161
5096 23:42:28.867073
5097 23:42:28.867636 TX Vref Scan disable
5098 23:42:28.870098 == TX Byte 0 ==
5099 23:42:28.873382 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5100 23:42:28.877052 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5101 23:42:28.879852 == TX Byte 1 ==
5102 23:42:28.883452 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5103 23:42:28.889897 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5104 23:42:28.890370
5105 23:42:28.890736 [DATLAT]
5106 23:42:28.891074 Freq=933, CH0 RK0
5107 23:42:28.891403
5108 23:42:28.893259 DATLAT Default: 0xd
5109 23:42:28.893865 0, 0xFFFF, sum = 0
5110 23:42:28.896654 1, 0xFFFF, sum = 0
5111 23:42:28.897220 2, 0xFFFF, sum = 0
5112 23:42:28.899950 3, 0xFFFF, sum = 0
5113 23:42:28.902698 4, 0xFFFF, sum = 0
5114 23:42:28.903173 5, 0xFFFF, sum = 0
5115 23:42:28.906250 6, 0xFFFF, sum = 0
5116 23:42:28.906889 7, 0xFFFF, sum = 0
5117 23:42:28.909474 8, 0xFFFF, sum = 0
5118 23:42:28.909998 9, 0xFFFF, sum = 0
5119 23:42:28.912807 10, 0x0, sum = 1
5120 23:42:28.913278 11, 0x0, sum = 2
5121 23:42:28.916014 12, 0x0, sum = 3
5122 23:42:28.916500 13, 0x0, sum = 4
5123 23:42:28.916873 best_step = 11
5124 23:42:28.919341
5125 23:42:28.919804 ==
5126 23:42:28.922669 Dram Type= 6, Freq= 0, CH_0, rank 0
5127 23:42:28.926308 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5128 23:42:28.926783 ==
5129 23:42:28.927152 RX Vref Scan: 1
5130 23:42:28.927493
5131 23:42:28.929236 RX Vref 0 -> 0, step: 1
5132 23:42:28.929749
5133 23:42:28.932693 RX Delay -69 -> 252, step: 4
5134 23:42:28.933159
5135 23:42:28.936052 Set Vref, RX VrefLevel [Byte0]: 46
5136 23:42:28.939609 [Byte1]: 52
5137 23:42:28.940183
5138 23:42:28.942878 Final RX Vref Byte 0 = 46 to rank0
5139 23:42:28.945970 Final RX Vref Byte 1 = 52 to rank0
5140 23:42:28.949539 Final RX Vref Byte 0 = 46 to rank1
5141 23:42:28.952775 Final RX Vref Byte 1 = 52 to rank1==
5142 23:42:28.956095 Dram Type= 6, Freq= 0, CH_0, rank 0
5143 23:42:28.959418 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5144 23:42:28.962386 ==
5145 23:42:28.962854 DQS Delay:
5146 23:42:28.963224 DQS0 = 0, DQS1 = 0
5147 23:42:28.965859 DQM Delay:
5148 23:42:28.966325 DQM0 = 97, DQM1 = 88
5149 23:42:28.969126 DQ Delay:
5150 23:42:28.972578 DQ0 =92, DQ1 =98, DQ2 =96, DQ3 =94
5151 23:42:28.976379 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5152 23:42:28.979259 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =80
5153 23:42:28.982391 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =98
5154 23:42:28.982963
5155 23:42:28.983338
5156 23:42:28.989184 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
5157 23:42:28.992224 CH0 RK0: MR19=505, MR18=2323
5158 23:42:28.998887 CH0_RK0: MR19=0x505, MR18=0x2323, DQSOSC=410, MR23=63, INC=64, DEC=42
5159 23:42:28.999454
5160 23:42:29.002058 ----->DramcWriteLeveling(PI) begin...
5161 23:42:29.002532 ==
5162 23:42:29.005236 Dram Type= 6, Freq= 0, CH_0, rank 1
5163 23:42:29.008617 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5164 23:42:29.009091 ==
5165 23:42:29.011822 Write leveling (Byte 0): 30 => 30
5166 23:42:29.015292 Write leveling (Byte 1): 26 => 26
5167 23:42:29.018388 DramcWriteLeveling(PI) end<-----
5168 23:42:29.018858
5169 23:42:29.019225 ==
5170 23:42:29.021779 Dram Type= 6, Freq= 0, CH_0, rank 1
5171 23:42:29.025088 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5172 23:42:29.025619 ==
5173 23:42:29.028321 [Gating] SW mode calibration
5174 23:42:29.035377 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5175 23:42:29.041812 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5176 23:42:29.045395 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 23:42:29.052343 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 23:42:29.055105 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 23:42:29.058366 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 23:42:29.064646 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5181 23:42:29.068402 0 10 20 | B1->B0 | 3232 2f2f | 1 0 | (1 0) (0 0)
5182 23:42:29.071673 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
5183 23:42:29.078205 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 23:42:29.081498 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 23:42:29.084963 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 23:42:29.091533 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 23:42:29.094927 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 23:42:29.098134 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 23:42:29.104993 0 11 20 | B1->B0 | 2e2e 3535 | 0 0 | (0 0) (1 1)
5190 23:42:29.107929 0 11 24 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
5191 23:42:29.110869 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 23:42:29.117706 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 23:42:29.121514 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 23:42:29.124220 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 23:42:29.130875 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 23:42:29.134610 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 23:42:29.137933 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 23:42:29.144468 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 23:42:29.147600 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 23:42:29.150895 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 23:42:29.157872 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 23:42:29.161370 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 23:42:29.164054 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 23:42:29.167853 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 23:42:29.174005 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 23:42:29.177752 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 23:42:29.181128 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 23:42:29.188031 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 23:42:29.190865 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 23:42:29.193851 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 23:42:29.201076 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 23:42:29.204216 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 23:42:29.207007 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5214 23:42:29.213845 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5215 23:42:29.217182 Total UI for P1: 0, mck2ui 16
5216 23:42:29.220526 best dqsien dly found for B0: ( 0, 14, 20)
5217 23:42:29.223919 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 23:42:29.227116 Total UI for P1: 0, mck2ui 16
5219 23:42:29.230470 best dqsien dly found for B1: ( 0, 14, 22)
5220 23:42:29.233379 best DQS0 dly(MCK, UI, PI) = (0, 14, 20)
5221 23:42:29.236989 best DQS1 dly(MCK, UI, PI) = (0, 14, 22)
5222 23:42:29.237613
5223 23:42:29.240671 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 20)
5224 23:42:29.246973 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 22)
5225 23:42:29.247589 [Gating] SW calibration Done
5226 23:42:29.247963 ==
5227 23:42:29.249872 Dram Type= 6, Freq= 0, CH_0, rank 1
5228 23:42:29.256631 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5229 23:42:29.257199 ==
5230 23:42:29.257615 RX Vref Scan: 0
5231 23:42:29.257962
5232 23:42:29.260116 RX Vref 0 -> 0, step: 1
5233 23:42:29.260694
5234 23:42:29.263255 RX Delay -80 -> 252, step: 8
5235 23:42:29.266260 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5236 23:42:29.269932 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5237 23:42:29.272980 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5238 23:42:29.279884 iDelay=200, Bit 3, Center 91 (0 ~ 183) 184
5239 23:42:29.282814 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5240 23:42:29.286366 iDelay=200, Bit 5, Center 95 (0 ~ 191) 192
5241 23:42:29.289409 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5242 23:42:29.292950 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5243 23:42:29.296137 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5244 23:42:29.302694 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5245 23:42:29.306090 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5246 23:42:29.309134 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5247 23:42:29.312420 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5248 23:42:29.315814 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5249 23:42:29.319441 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5250 23:42:29.325904 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5251 23:42:29.326467 ==
5252 23:42:29.329202 Dram Type= 6, Freq= 0, CH_0, rank 1
5253 23:42:29.332653 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5254 23:42:29.333223 ==
5255 23:42:29.333634 DQS Delay:
5256 23:42:29.335868 DQS0 = 0, DQS1 = 0
5257 23:42:29.336434 DQM Delay:
5258 23:42:29.339192 DQM0 = 98, DQM1 = 89
5259 23:42:29.339763 DQ Delay:
5260 23:42:29.342019 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5261 23:42:29.345525 DQ4 =103, DQ5 =95, DQ6 =103, DQ7 =103
5262 23:42:29.349137 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5263 23:42:29.352153 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5264 23:42:29.352629
5265 23:42:29.353335
5266 23:42:29.353909 ==
5267 23:42:29.355395 Dram Type= 6, Freq= 0, CH_0, rank 1
5268 23:42:29.359117 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5269 23:42:29.362047 ==
5270 23:42:29.362517
5271 23:42:29.362885
5272 23:42:29.363224 TX Vref Scan disable
5273 23:42:29.365494 == TX Byte 0 ==
5274 23:42:29.368905 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5275 23:42:29.372283 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5276 23:42:29.375469 == TX Byte 1 ==
5277 23:42:29.379200 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5278 23:42:29.382180 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5279 23:42:29.385458 ==
5280 23:42:29.388695 Dram Type= 6, Freq= 0, CH_0, rank 1
5281 23:42:29.392018 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5282 23:42:29.392488 ==
5283 23:42:29.392858
5284 23:42:29.393199
5285 23:42:29.395739 TX Vref Scan disable
5286 23:42:29.396204 == TX Byte 0 ==
5287 23:42:29.401951 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5288 23:42:29.405117 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5289 23:42:29.405608 == TX Byte 1 ==
5290 23:42:29.411710 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5291 23:42:29.414948 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5292 23:42:29.415418
5293 23:42:29.415790 [DATLAT]
5294 23:42:29.418294 Freq=933, CH0 RK1
5295 23:42:29.418761
5296 23:42:29.419129 DATLAT Default: 0xb
5297 23:42:29.421555 0, 0xFFFF, sum = 0
5298 23:42:29.422034 1, 0xFFFF, sum = 0
5299 23:42:29.424963 2, 0xFFFF, sum = 0
5300 23:42:29.425431 3, 0xFFFF, sum = 0
5301 23:42:29.428423 4, 0xFFFF, sum = 0
5302 23:42:29.428963 5, 0xFFFF, sum = 0
5303 23:42:29.431676 6, 0xFFFF, sum = 0
5304 23:42:29.434798 7, 0xFFFF, sum = 0
5305 23:42:29.435228 8, 0xFFFF, sum = 0
5306 23:42:29.437993 9, 0xFFFF, sum = 0
5307 23:42:29.438429 10, 0x0, sum = 1
5308 23:42:29.441424 11, 0x0, sum = 2
5309 23:42:29.441851 12, 0x0, sum = 3
5310 23:42:29.442189 13, 0x0, sum = 4
5311 23:42:29.444621 best_step = 11
5312 23:42:29.445043
5313 23:42:29.445418 ==
5314 23:42:29.448110 Dram Type= 6, Freq= 0, CH_0, rank 1
5315 23:42:29.451262 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5316 23:42:29.451690 ==
5317 23:42:29.454515 RX Vref Scan: 0
5318 23:42:29.454944
5319 23:42:29.455282 RX Vref 0 -> 0, step: 1
5320 23:42:29.457882
5321 23:42:29.458430 RX Delay -61 -> 252, step: 4
5322 23:42:29.465431 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5323 23:42:29.468861 iDelay=199, Bit 1, Center 100 (7 ~ 194) 188
5324 23:42:29.471982 iDelay=199, Bit 2, Center 96 (7 ~ 186) 180
5325 23:42:29.475399 iDelay=199, Bit 3, Center 92 (3 ~ 182) 180
5326 23:42:29.478902 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5327 23:42:29.481952 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5328 23:42:29.489395 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5329 23:42:29.492442 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5330 23:42:29.495782 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5331 23:42:29.498904 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5332 23:42:29.501992 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5333 23:42:29.508610 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5334 23:42:29.511994 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5335 23:42:29.515140 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5336 23:42:29.519009 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5337 23:42:29.521921 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5338 23:42:29.522393 ==
5339 23:42:29.525694 Dram Type= 6, Freq= 0, CH_0, rank 1
5340 23:42:29.532197 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5341 23:42:29.532731 ==
5342 23:42:29.533229 DQS Delay:
5343 23:42:29.535682 DQS0 = 0, DQS1 = 0
5344 23:42:29.536209 DQM Delay:
5345 23:42:29.536545 DQM0 = 97, DQM1 = 86
5346 23:42:29.538478 DQ Delay:
5347 23:42:29.542013 DQ0 =94, DQ1 =100, DQ2 =96, DQ3 =92
5348 23:42:29.545443 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =106
5349 23:42:29.548723 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5350 23:42:29.551783 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5351 23:42:29.552313
5352 23:42:29.552648
5353 23:42:29.558354 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
5354 23:42:29.561783 CH0 RK1: MR19=505, MR18=2E2E
5355 23:42:29.568425 CH0_RK1: MR19=0x505, MR18=0x2E2E, DQSOSC=407, MR23=63, INC=65, DEC=43
5356 23:42:29.571524 [RxdqsGatingPostProcess] freq 933
5357 23:42:29.578483 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5358 23:42:29.579019 Pre-setting of DQS Precalculation
5359 23:42:29.584956 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5360 23:42:29.585412 ==
5361 23:42:29.587910 Dram Type= 6, Freq= 0, CH_1, rank 0
5362 23:42:29.591247 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5363 23:42:29.591671 ==
5364 23:42:29.597836 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5365 23:42:29.604519 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5366 23:42:29.607710 [CA 0] Center 37 (7~68) winsize 62
5367 23:42:29.611174 [CA 1] Center 37 (6~68) winsize 63
5368 23:42:29.614538 [CA 2] Center 35 (5~65) winsize 61
5369 23:42:29.617920 [CA 3] Center 34 (4~65) winsize 62
5370 23:42:29.621207 [CA 4] Center 33 (2~64) winsize 63
5371 23:42:29.624671 [CA 5] Center 33 (3~64) winsize 62
5372 23:42:29.625192
5373 23:42:29.627509 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5374 23:42:29.627920
5375 23:42:29.631130 [CATrainingPosCal] consider 1 rank data
5376 23:42:29.634559 u2DelayCellTimex100 = 270/100 ps
5377 23:42:29.637735 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5378 23:42:29.641081 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5379 23:42:29.644512 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5380 23:42:29.647593 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5381 23:42:29.650969 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5382 23:42:29.657934 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5383 23:42:29.658497
5384 23:42:29.661020 CA PerBit enable=1, Macro0, CA PI delay=33
5385 23:42:29.661623
5386 23:42:29.664341 [CBTSetCACLKResult] CA Dly = 33
5387 23:42:29.664896 CS Dly: 5 (0~36)
5388 23:42:29.665263 ==
5389 23:42:29.667615 Dram Type= 6, Freq= 0, CH_1, rank 1
5390 23:42:29.670723 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5391 23:42:29.674385 ==
5392 23:42:29.677206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5393 23:42:29.684579 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5394 23:42:29.687273 [CA 0] Center 37 (7~68) winsize 62
5395 23:42:29.690928 [CA 1] Center 37 (6~68) winsize 63
5396 23:42:29.694108 [CA 2] Center 34 (4~65) winsize 62
5397 23:42:29.697352 [CA 3] Center 34 (4~65) winsize 62
5398 23:42:29.700755 [CA 4] Center 33 (2~64) winsize 63
5399 23:42:29.703716 [CA 5] Center 33 (3~64) winsize 62
5400 23:42:29.704172
5401 23:42:29.707467 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5402 23:42:29.708045
5403 23:42:29.710573 [CATrainingPosCal] consider 2 rank data
5404 23:42:29.714059 u2DelayCellTimex100 = 270/100 ps
5405 23:42:29.717417 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5406 23:42:29.720355 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5407 23:42:29.723737 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5408 23:42:29.727243 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5409 23:42:29.733754 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5410 23:42:29.737510 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5411 23:42:29.737925
5412 23:42:29.740542 CA PerBit enable=1, Macro0, CA PI delay=33
5413 23:42:29.740960
5414 23:42:29.743830 [CBTSetCACLKResult] CA Dly = 33
5415 23:42:29.744345 CS Dly: 5 (0~37)
5416 23:42:29.744674
5417 23:42:29.747405 ----->DramcWriteLeveling(PI) begin...
5418 23:42:29.747934 ==
5419 23:42:29.750852 Dram Type= 6, Freq= 0, CH_1, rank 0
5420 23:42:29.757402 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5421 23:42:29.757918 ==
5422 23:42:29.760966 Write leveling (Byte 0): 24 => 24
5423 23:42:29.764018 Write leveling (Byte 1): 24 => 24
5424 23:42:29.764565 DramcWriteLeveling(PI) end<-----
5425 23:42:29.767223
5426 23:42:29.767738 ==
5427 23:42:29.770564 Dram Type= 6, Freq= 0, CH_1, rank 0
5428 23:42:29.773234 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5429 23:42:29.773723 ==
5430 23:42:29.776729 [Gating] SW mode calibration
5431 23:42:29.783535 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5432 23:42:29.786916 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5433 23:42:29.794264 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5434 23:42:29.796595 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5435 23:42:29.799993 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5436 23:42:29.806512 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5437 23:42:29.809481 0 10 16 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 1)
5438 23:42:29.812999 0 10 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
5439 23:42:29.819472 0 10 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5440 23:42:29.822703 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5441 23:42:29.826269 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5442 23:42:29.832981 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5443 23:42:29.836339 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5444 23:42:29.839656 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5445 23:42:29.845866 0 11 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
5446 23:42:29.849587 0 11 20 | B1->B0 | 3232 4343 | 0 0 | (0 0) (0 0)
5447 23:42:29.852509 0 11 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5448 23:42:29.859068 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5449 23:42:29.862419 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5450 23:42:29.865802 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5451 23:42:29.872541 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5452 23:42:29.875834 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5453 23:42:29.879415 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5454 23:42:29.885981 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5455 23:42:29.888727 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 23:42:29.892465 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 23:42:29.898965 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 23:42:29.902356 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 23:42:29.905510 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5460 23:42:29.912653 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5461 23:42:29.915205 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5462 23:42:29.918661 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5463 23:42:29.925627 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5464 23:42:29.929087 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5465 23:42:29.932191 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5466 23:42:29.938930 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5467 23:42:29.941907 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5468 23:42:29.945585 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5469 23:42:29.951924 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5470 23:42:29.954919 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5471 23:42:29.958336 Total UI for P1: 0, mck2ui 16
5472 23:42:29.961595 best dqsien dly found for B0: ( 0, 14, 16)
5473 23:42:29.965077 Total UI for P1: 0, mck2ui 16
5474 23:42:29.967970 best dqsien dly found for B1: ( 0, 14, 16)
5475 23:42:29.971472 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5476 23:42:29.974645 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5477 23:42:29.975062
5478 23:42:29.978095 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5479 23:42:29.981489 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5480 23:42:29.984685 [Gating] SW calibration Done
5481 23:42:29.985099 ==
5482 23:42:29.987809 Dram Type= 6, Freq= 0, CH_1, rank 0
5483 23:42:29.995029 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5484 23:42:29.995555 ==
5485 23:42:29.995917 RX Vref Scan: 0
5486 23:42:29.996231
5487 23:42:29.998031 RX Vref 0 -> 0, step: 1
5488 23:42:29.998452
5489 23:42:30.001508 RX Delay -80 -> 252, step: 8
5490 23:42:30.004683 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5491 23:42:30.008182 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5492 23:42:30.011016 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5493 23:42:30.014664 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5494 23:42:30.021371 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5495 23:42:30.024446 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5496 23:42:30.028085 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5497 23:42:30.031150 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5498 23:42:30.034795 iDelay=208, Bit 8, Center 75 (-16 ~ 167) 184
5499 23:42:30.038197 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5500 23:42:30.044553 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5501 23:42:30.047650 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5502 23:42:30.051588 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5503 23:42:30.054087 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5504 23:42:30.057538 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5505 23:42:30.064432 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5506 23:42:30.065014 ==
5507 23:42:30.067475 Dram Type= 6, Freq= 0, CH_1, rank 0
5508 23:42:30.070884 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5509 23:42:30.071451 ==
5510 23:42:30.071819 DQS Delay:
5511 23:42:30.074244 DQS0 = 0, DQS1 = 0
5512 23:42:30.074706 DQM Delay:
5513 23:42:30.077569 DQM0 = 96, DQM1 = 89
5514 23:42:30.078129 DQ Delay:
5515 23:42:30.080963 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =91
5516 23:42:30.084415 DQ4 =91, DQ5 =107, DQ6 =107, DQ7 =91
5517 23:42:30.087714 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =79
5518 23:42:30.090895 DQ12 =99, DQ13 =103, DQ14 =91, DQ15 =99
5519 23:42:30.091459
5520 23:42:30.091824
5521 23:42:30.092164 ==
5522 23:42:30.093859 Dram Type= 6, Freq= 0, CH_1, rank 0
5523 23:42:30.097509 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5524 23:42:30.101084 ==
5525 23:42:30.101688
5526 23:42:30.102053
5527 23:42:30.102390 TX Vref Scan disable
5528 23:42:30.104171 == TX Byte 0 ==
5529 23:42:30.107063 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5530 23:42:30.111287 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5531 23:42:30.113769 == TX Byte 1 ==
5532 23:42:30.117206 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5533 23:42:30.120676 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5534 23:42:30.123666 ==
5535 23:42:30.127258 Dram Type= 6, Freq= 0, CH_1, rank 0
5536 23:42:30.130774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5537 23:42:30.131320 ==
5538 23:42:30.131661
5539 23:42:30.131965
5540 23:42:30.133784 TX Vref Scan disable
5541 23:42:30.134201 == TX Byte 0 ==
5542 23:42:30.140338 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5543 23:42:30.143615 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5544 23:42:30.144180 == TX Byte 1 ==
5545 23:42:30.150667 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5546 23:42:30.153546 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5547 23:42:30.154106
5548 23:42:30.154474 [DATLAT]
5549 23:42:30.156954 Freq=933, CH1 RK0
5550 23:42:30.157558
5551 23:42:30.157922 DATLAT Default: 0xd
5552 23:42:30.160514 0, 0xFFFF, sum = 0
5553 23:42:30.161085 1, 0xFFFF, sum = 0
5554 23:42:30.163548 2, 0xFFFF, sum = 0
5555 23:42:30.164014 3, 0xFFFF, sum = 0
5556 23:42:30.166801 4, 0xFFFF, sum = 0
5557 23:42:30.170005 5, 0xFFFF, sum = 0
5558 23:42:30.170566 6, 0xFFFF, sum = 0
5559 23:42:30.173116 7, 0xFFFF, sum = 0
5560 23:42:30.173649 8, 0xFFFF, sum = 0
5561 23:42:30.176697 9, 0xFFFF, sum = 0
5562 23:42:30.177252 10, 0x0, sum = 1
5563 23:42:30.180031 11, 0x0, sum = 2
5564 23:42:30.180607 12, 0x0, sum = 3
5565 23:42:30.180977 13, 0x0, sum = 4
5566 23:42:30.183117 best_step = 11
5567 23:42:30.183576
5568 23:42:30.183940 ==
5569 23:42:30.186343 Dram Type= 6, Freq= 0, CH_1, rank 0
5570 23:42:30.190285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5571 23:42:30.190857 ==
5572 23:42:30.193175 RX Vref Scan: 1
5573 23:42:30.193685
5574 23:42:30.196720 RX Vref 0 -> 0, step: 1
5575 23:42:30.197282
5576 23:42:30.197690 RX Delay -61 -> 252, step: 4
5577 23:42:30.198038
5578 23:42:30.200076 Set Vref, RX VrefLevel [Byte0]: 52
5579 23:42:30.202863 [Byte1]: 49
5580 23:42:30.207957
5581 23:42:30.208534 Final RX Vref Byte 0 = 52 to rank0
5582 23:42:30.211219 Final RX Vref Byte 1 = 49 to rank0
5583 23:42:30.214168 Final RX Vref Byte 0 = 52 to rank1
5584 23:42:30.217516 Final RX Vref Byte 1 = 49 to rank1==
5585 23:42:30.221250 Dram Type= 6, Freq= 0, CH_1, rank 0
5586 23:42:30.227940 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5587 23:42:30.228494 ==
5588 23:42:30.228861 DQS Delay:
5589 23:42:30.229203 DQS0 = 0, DQS1 = 0
5590 23:42:30.231789 DQM Delay:
5591 23:42:30.232266 DQM0 = 95, DQM1 = 90
5592 23:42:30.234310 DQ Delay:
5593 23:42:30.237909 DQ0 =100, DQ1 =90, DQ2 =88, DQ3 =92
5594 23:42:30.241059 DQ4 =94, DQ5 =106, DQ6 =102, DQ7 =94
5595 23:42:30.244306 DQ8 =74, DQ9 =78, DQ10 =90, DQ11 =82
5596 23:42:30.247690 DQ12 =96, DQ13 =102, DQ14 =98, DQ15 =100
5597 23:42:30.248243
5598 23:42:30.248680
5599 23:42:30.254223 [DQSOSCAuto] RK0, (LSB)MR18= 0x3636, (MSB)MR19= 0x505, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
5600 23:42:30.257645 CH1 RK0: MR19=505, MR18=3636
5601 23:42:30.264633 CH1_RK0: MR19=0x505, MR18=0x3636, DQSOSC=404, MR23=63, INC=66, DEC=44
5602 23:42:30.265187
5603 23:42:30.267816 ----->DramcWriteLeveling(PI) begin...
5604 23:42:30.268378 ==
5605 23:42:30.271229 Dram Type= 6, Freq= 0, CH_1, rank 1
5606 23:42:30.274157 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5607 23:42:30.274715 ==
5608 23:42:30.277794 Write leveling (Byte 0): 26 => 26
5609 23:42:30.281090 Write leveling (Byte 1): 26 => 26
5610 23:42:30.284394 DramcWriteLeveling(PI) end<-----
5611 23:42:30.284947
5612 23:42:30.285363 ==
5613 23:42:30.287597 Dram Type= 6, Freq= 0, CH_1, rank 1
5614 23:42:30.290751 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5615 23:42:30.291213 ==
5616 23:42:30.293900 [Gating] SW mode calibration
5617 23:42:30.300378 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5618 23:42:30.307123 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5619 23:42:30.310748 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 23:42:30.317105 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 23:42:30.320581 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 23:42:30.323915 0 10 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5623 23:42:30.330065 0 10 16 | B1->B0 | 3434 2c2c | 0 1 | (0 0) (1 0)
5624 23:42:30.333606 0 10 20 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5625 23:42:30.336691 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 23:42:30.343808 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 23:42:30.346897 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 23:42:30.350311 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 23:42:30.356751 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 23:42:30.360320 0 11 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5631 23:42:30.363562 0 11 16 | B1->B0 | 2525 3737 | 0 0 | (0 0) (0 0)
5632 23:42:30.370132 0 11 20 | B1->B0 | 3c3c 4646 | 0 0 | (1 1) (0 0)
5633 23:42:30.373930 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 23:42:30.376810 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 23:42:30.383562 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 23:42:30.386330 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 23:42:30.389822 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 23:42:30.396499 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 23:42:30.399642 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5640 23:42:30.402854 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5641 23:42:30.409532 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 23:42:30.413098 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 23:42:30.415924 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 23:42:30.422654 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 23:42:30.426121 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 23:42:30.429658 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 23:42:30.435991 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 23:42:30.439536 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 23:42:30.442777 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 23:42:30.449414 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 23:42:30.452888 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 23:42:30.456012 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 23:42:30.462658 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 23:42:30.465922 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 23:42:30.468882 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5656 23:42:30.476127 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 23:42:30.476715 Total UI for P1: 0, mck2ui 16
5658 23:42:30.479042 best dqsien dly found for B0: ( 0, 14, 16)
5659 23:42:30.482226 Total UI for P1: 0, mck2ui 16
5660 23:42:30.485838 best dqsien dly found for B1: ( 0, 14, 16)
5661 23:42:30.492438 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5662 23:42:30.495575 best DQS1 dly(MCK, UI, PI) = (0, 14, 16)
5663 23:42:30.496144
5664 23:42:30.499087 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5665 23:42:30.501948 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 16)
5666 23:42:30.505463 [Gating] SW calibration Done
5667 23:42:30.506050 ==
5668 23:42:30.508621 Dram Type= 6, Freq= 0, CH_1, rank 1
5669 23:42:30.512176 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5670 23:42:30.512645 ==
5671 23:42:30.515459 RX Vref Scan: 0
5672 23:42:30.515923
5673 23:42:30.516293 RX Vref 0 -> 0, step: 1
5674 23:42:30.516639
5675 23:42:30.518696 RX Delay -80 -> 252, step: 8
5676 23:42:30.521942 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5677 23:42:30.528714 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5678 23:42:30.531813 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5679 23:42:30.535582 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5680 23:42:30.538407 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5681 23:42:30.541843 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5682 23:42:30.545286 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5683 23:42:30.551655 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5684 23:42:30.555354 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5685 23:42:30.558101 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5686 23:42:30.561529 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5687 23:42:30.564872 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5688 23:42:30.571671 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5689 23:42:30.575172 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5690 23:42:30.578235 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5691 23:42:30.581843 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5692 23:42:30.582551 ==
5693 23:42:30.585187 Dram Type= 6, Freq= 0, CH_1, rank 1
5694 23:42:30.588080 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5695 23:42:30.588576 ==
5696 23:42:30.591480 DQS Delay:
5697 23:42:30.591973 DQS0 = 0, DQS1 = 0
5698 23:42:30.594587 DQM Delay:
5699 23:42:30.595008 DQM0 = 98, DQM1 = 89
5700 23:42:30.595340 DQ Delay:
5701 23:42:30.598025 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =99
5702 23:42:30.601278 DQ4 =99, DQ5 =107, DQ6 =107, DQ7 =95
5703 23:42:30.604453 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5704 23:42:30.607691 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5705 23:42:30.608113
5706 23:42:30.608443
5707 23:42:30.611228 ==
5708 23:42:30.614698 Dram Type= 6, Freq= 0, CH_1, rank 1
5709 23:42:30.617904 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5710 23:42:30.618330 ==
5711 23:42:30.618664
5712 23:42:30.619165
5713 23:42:30.620875 TX Vref Scan disable
5714 23:42:30.621324 == TX Byte 0 ==
5715 23:42:30.627659 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5716 23:42:30.631138 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5717 23:42:30.631668 == TX Byte 1 ==
5718 23:42:30.637573 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5719 23:42:30.640879 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5720 23:42:30.641453 ==
5721 23:42:30.644111 Dram Type= 6, Freq= 0, CH_1, rank 1
5722 23:42:30.647693 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5723 23:42:30.648220 ==
5724 23:42:30.648558
5725 23:42:30.648868
5726 23:42:30.651060 TX Vref Scan disable
5727 23:42:30.654338 == TX Byte 0 ==
5728 23:42:30.657211 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5729 23:42:30.660998 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5730 23:42:30.664026 == TX Byte 1 ==
5731 23:42:30.667134 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5732 23:42:30.670924 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5733 23:42:30.671447
5734 23:42:30.674197 [DATLAT]
5735 23:42:30.674714 Freq=933, CH1 RK1
5736 23:42:30.675052
5737 23:42:30.677523 DATLAT Default: 0xb
5738 23:42:30.678043 0, 0xFFFF, sum = 0
5739 23:42:30.680537 1, 0xFFFF, sum = 0
5740 23:42:30.680969 2, 0xFFFF, sum = 0
5741 23:42:30.683985 3, 0xFFFF, sum = 0
5742 23:42:30.684414 4, 0xFFFF, sum = 0
5743 23:42:30.687397 5, 0xFFFF, sum = 0
5744 23:42:30.687928 6, 0xFFFF, sum = 0
5745 23:42:30.690218 7, 0xFFFF, sum = 0
5746 23:42:30.690647 8, 0xFFFF, sum = 0
5747 23:42:30.693609 9, 0xFFFF, sum = 0
5748 23:42:30.694038 10, 0x0, sum = 1
5749 23:42:30.697435 11, 0x0, sum = 2
5750 23:42:30.697953 12, 0x0, sum = 3
5751 23:42:30.700457 13, 0x0, sum = 4
5752 23:42:30.700881 best_step = 11
5753 23:42:30.701212
5754 23:42:30.701577 ==
5755 23:42:30.703414 Dram Type= 6, Freq= 0, CH_1, rank 1
5756 23:42:30.710185 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5757 23:42:30.710690 ==
5758 23:42:30.711044 RX Vref Scan: 0
5759 23:42:30.711352
5760 23:42:30.713813 RX Vref 0 -> 0, step: 1
5761 23:42:30.714382
5762 23:42:30.716975 RX Delay -69 -> 252, step: 4
5763 23:42:30.720213 iDelay=203, Bit 0, Center 98 (11 ~ 186) 176
5764 23:42:30.726728 iDelay=203, Bit 1, Center 92 (3 ~ 182) 180
5765 23:42:30.730323 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5766 23:42:30.733412 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5767 23:42:30.736593 iDelay=203, Bit 4, Center 98 (7 ~ 190) 184
5768 23:42:30.740297 iDelay=203, Bit 5, Center 110 (19 ~ 202) 184
5769 23:42:30.743300 iDelay=203, Bit 6, Center 106 (15 ~ 198) 184
5770 23:42:30.746833 iDelay=203, Bit 7, Center 96 (7 ~ 186) 180
5771 23:42:30.753579 iDelay=203, Bit 8, Center 76 (-13 ~ 166) 180
5772 23:42:30.756842 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5773 23:42:30.760170 iDelay=203, Bit 10, Center 90 (-1 ~ 182) 184
5774 23:42:30.763098 iDelay=203, Bit 11, Center 82 (-9 ~ 174) 184
5775 23:42:30.769800 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5776 23:42:30.773325 iDelay=203, Bit 13, Center 98 (11 ~ 186) 176
5777 23:42:30.776494 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5778 23:42:30.779898 iDelay=203, Bit 15, Center 98 (11 ~ 186) 176
5779 23:42:30.780363 ==
5780 23:42:30.783235 Dram Type= 6, Freq= 0, CH_1, rank 1
5781 23:42:30.786424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5782 23:42:30.789510 ==
5783 23:42:30.789974 DQS Delay:
5784 23:42:30.790343 DQS0 = 0, DQS1 = 0
5785 23:42:30.792966 DQM Delay:
5786 23:42:30.793464 DQM0 = 98, DQM1 = 90
5787 23:42:30.796541 DQ Delay:
5788 23:42:30.797100 DQ0 =98, DQ1 =92, DQ2 =90, DQ3 =94
5789 23:42:30.799668 DQ4 =98, DQ5 =110, DQ6 =106, DQ7 =96
5790 23:42:30.803360 DQ8 =76, DQ9 =78, DQ10 =90, DQ11 =82
5791 23:42:30.806118 DQ12 =100, DQ13 =98, DQ14 =98, DQ15 =98
5792 23:42:30.809875
5793 23:42:30.810485
5794 23:42:30.816108 [DQSOSCAuto] RK1, (LSB)MR18= 0x2929, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5795 23:42:30.819241 CH1 RK1: MR19=505, MR18=2929
5796 23:42:30.825837 CH1_RK1: MR19=0x505, MR18=0x2929, DQSOSC=408, MR23=63, INC=65, DEC=43
5797 23:42:30.829447 [RxdqsGatingPostProcess] freq 933
5798 23:42:30.832628 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5799 23:42:30.835774 Pre-setting of DQS Precalculation
5800 23:42:30.842317 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5801 23:42:30.849208 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5802 23:42:30.855957 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5803 23:42:30.856522
5804 23:42:30.856891
5805 23:42:30.859326 [Calibration Summary] 1866 Mbps
5806 23:42:30.859888 CH 0, Rank 0
5807 23:42:30.862139 SW Impedance : PASS
5808 23:42:30.865837 DUTY Scan : NO K
5809 23:42:30.866400 ZQ Calibration : PASS
5810 23:42:30.868789 Jitter Meter : NO K
5811 23:42:30.872502 CBT Training : PASS
5812 23:42:30.873062 Write leveling : PASS
5813 23:42:30.875486 RX DQS gating : PASS
5814 23:42:30.879058 RX DQ/DQS(RDDQC) : PASS
5815 23:42:30.879619 TX DQ/DQS : PASS
5816 23:42:30.882080 RX DATLAT : PASS
5817 23:42:30.885260 RX DQ/DQS(Engine): PASS
5818 23:42:30.885766 TX OE : NO K
5819 23:42:30.889154 All Pass.
5820 23:42:30.889756
5821 23:42:30.890127 CH 0, Rank 1
5822 23:42:30.891703 SW Impedance : PASS
5823 23:42:30.892173 DUTY Scan : NO K
5824 23:42:30.895167 ZQ Calibration : PASS
5825 23:42:30.898373 Jitter Meter : NO K
5826 23:42:30.898840 CBT Training : PASS
5827 23:42:30.901776 Write leveling : PASS
5828 23:42:30.904940 RX DQS gating : PASS
5829 23:42:30.905438 RX DQ/DQS(RDDQC) : PASS
5830 23:42:30.908331 TX DQ/DQS : PASS
5831 23:42:30.911504 RX DATLAT : PASS
5832 23:42:30.911928 RX DQ/DQS(Engine): PASS
5833 23:42:30.914893 TX OE : NO K
5834 23:42:30.915319 All Pass.
5835 23:42:30.915729
5836 23:42:30.918345 CH 1, Rank 0
5837 23:42:30.918769 SW Impedance : PASS
5838 23:42:30.921394 DUTY Scan : NO K
5839 23:42:30.921837 ZQ Calibration : PASS
5840 23:42:30.924964 Jitter Meter : NO K
5841 23:42:30.928181 CBT Training : PASS
5842 23:42:30.928606 Write leveling : PASS
5843 23:42:30.931400 RX DQS gating : PASS
5844 23:42:30.935128 RX DQ/DQS(RDDQC) : PASS
5845 23:42:30.935666 TX DQ/DQS : PASS
5846 23:42:30.938207 RX DATLAT : PASS
5847 23:42:30.941562 RX DQ/DQS(Engine): PASS
5848 23:42:30.942281 TX OE : NO K
5849 23:42:30.944925 All Pass.
5850 23:42:30.945486
5851 23:42:30.945829 CH 1, Rank 1
5852 23:42:30.947894 SW Impedance : PASS
5853 23:42:30.948320 DUTY Scan : NO K
5854 23:42:30.951483 ZQ Calibration : PASS
5855 23:42:30.954804 Jitter Meter : NO K
5856 23:42:30.955339 CBT Training : PASS
5857 23:42:30.958294 Write leveling : PASS
5858 23:42:30.961286 RX DQS gating : PASS
5859 23:42:30.961865 RX DQ/DQS(RDDQC) : PASS
5860 23:42:30.964442 TX DQ/DQS : PASS
5861 23:42:30.967986 RX DATLAT : PASS
5862 23:42:30.968546 RX DQ/DQS(Engine): PASS
5863 23:42:30.971289 TX OE : NO K
5864 23:42:30.971853 All Pass.
5865 23:42:30.972221
5866 23:42:30.974244 DramC Write-DBI off
5867 23:42:30.977732 PER_BANK_REFRESH: Hybrid Mode
5868 23:42:30.978196 TX_TRACKING: ON
5869 23:42:30.987717 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5870 23:42:30.991335 [FAST_K] Save calibration result to emmc
5871 23:42:30.994128 dramc_set_vcore_voltage set vcore to 650000
5872 23:42:30.998030 Read voltage for 400, 6
5873 23:42:30.998587 Vio18 = 0
5874 23:42:30.998958 Vcore = 650000
5875 23:42:31.000962 Vdram = 0
5876 23:42:31.001554 Vddq = 0
5877 23:42:31.001926 Vmddr = 0
5878 23:42:31.007324 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5879 23:42:31.010641 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5880 23:42:31.013946 MEM_TYPE=3, freq_sel=20
5881 23:42:31.017611 sv_algorithm_assistance_LP4_800
5882 23:42:31.020505 ============ PULL DRAM RESETB DOWN ============
5883 23:42:31.024037 ========== PULL DRAM RESETB DOWN end =========
5884 23:42:31.030429 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5885 23:42:31.034087 ===================================
5886 23:42:31.034654 LPDDR4 DRAM CONFIGURATION
5887 23:42:31.037190 ===================================
5888 23:42:31.040636 EX_ROW_EN[0] = 0x0
5889 23:42:31.043575 EX_ROW_EN[1] = 0x0
5890 23:42:31.044040 LP4Y_EN = 0x0
5891 23:42:31.047151 WORK_FSP = 0x0
5892 23:42:31.047711 WL = 0x2
5893 23:42:31.050151 RL = 0x2
5894 23:42:31.050669 BL = 0x2
5895 23:42:31.053860 RPST = 0x0
5896 23:42:31.054423 RD_PRE = 0x0
5897 23:42:31.057056 WR_PRE = 0x1
5898 23:42:31.057661 WR_PST = 0x0
5899 23:42:31.059975 DBI_WR = 0x0
5900 23:42:31.060453 DBI_RD = 0x0
5901 23:42:31.063878 OTF = 0x1
5902 23:42:31.066642 ===================================
5903 23:42:31.070081 ===================================
5904 23:42:31.070639 ANA top config
5905 23:42:31.073243 ===================================
5906 23:42:31.076756 DLL_ASYNC_EN = 0
5907 23:42:31.080443 ALL_SLAVE_EN = 1
5908 23:42:31.083216 NEW_RANK_MODE = 1
5909 23:42:31.083683 DLL_IDLE_MODE = 1
5910 23:42:31.087036 LP45_APHY_COMB_EN = 1
5911 23:42:31.090120 TX_ODT_DIS = 1
5912 23:42:31.093528 NEW_8X_MODE = 1
5913 23:42:31.096865 ===================================
5914 23:42:31.100576 ===================================
5915 23:42:31.103389 data_rate = 800
5916 23:42:31.106771 CKR = 1
5917 23:42:31.107237 DQ_P2S_RATIO = 4
5918 23:42:31.109764 ===================================
5919 23:42:31.113159 CA_P2S_RATIO = 4
5920 23:42:31.116347 DQ_CA_OPEN = 0
5921 23:42:31.120150 DQ_SEMI_OPEN = 1
5922 23:42:31.123154 CA_SEMI_OPEN = 1
5923 23:42:31.126455 CA_FULL_RATE = 0
5924 23:42:31.126918 DQ_CKDIV4_EN = 0
5925 23:42:31.129841 CA_CKDIV4_EN = 1
5926 23:42:31.133456 CA_PREDIV_EN = 0
5927 23:42:31.136476 PH8_DLY = 0
5928 23:42:31.139666 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5929 23:42:31.140225 DQ_AAMCK_DIV = 0
5930 23:42:31.143043 CA_AAMCK_DIV = 0
5931 23:42:31.146504 CA_ADMCK_DIV = 4
5932 23:42:31.149677 DQ_TRACK_CA_EN = 0
5933 23:42:31.153411 CA_PICK = 800
5934 23:42:31.156214 CA_MCKIO = 400
5935 23:42:31.159376 MCKIO_SEMI = 400
5936 23:42:31.163110 PLL_FREQ = 3016
5937 23:42:31.163669 DQ_UI_PI_RATIO = 32
5938 23:42:31.166215 CA_UI_PI_RATIO = 32
5939 23:42:31.169461 ===================================
5940 23:42:31.172859 ===================================
5941 23:42:31.176300 memory_type:LPDDR4
5942 23:42:31.179457 GP_NUM : 10
5943 23:42:31.179919 SRAM_EN : 1
5944 23:42:31.182650 MD32_EN : 0
5945 23:42:31.185833 ===================================
5946 23:42:31.189133 [ANA_INIT] >>>>>>>>>>>>>>
5947 23:42:31.189643 <<<<<< [CONFIGURE PHASE]: ANA_TX
5948 23:42:31.195916 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5949 23:42:31.199186 ===================================
5950 23:42:31.199749 data_rate = 800,PCW = 0X7400
5951 23:42:31.202344 ===================================
5952 23:42:31.206067 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5953 23:42:31.212053 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5954 23:42:31.222282 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5955 23:42:31.229082 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5956 23:42:31.232344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5957 23:42:31.235651 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5958 23:42:31.239088 [ANA_INIT] flow start
5959 23:42:31.239647 [ANA_INIT] PLL >>>>>>>>
5960 23:42:31.241886 [ANA_INIT] PLL <<<<<<<<
5961 23:42:31.245742 [ANA_INIT] MIDPI >>>>>>>>
5962 23:42:31.246301 [ANA_INIT] MIDPI <<<<<<<<
5963 23:42:31.248665 [ANA_INIT] DLL >>>>>>>>
5964 23:42:31.252032 [ANA_INIT] flow end
5965 23:42:31.255700 ============ LP4 DIFF to SE enter ============
5966 23:42:31.258880 ============ LP4 DIFF to SE exit ============
5967 23:42:31.261798 [ANA_INIT] <<<<<<<<<<<<<
5968 23:42:31.265341 [Flow] Enable top DCM control >>>>>
5969 23:42:31.268410 [Flow] Enable top DCM control <<<<<
5970 23:42:31.271940 Enable DLL master slave shuffle
5971 23:42:31.275272 ==============================================================
5972 23:42:31.278735 Gating Mode config
5973 23:42:31.285057 ==============================================================
5974 23:42:31.285658 Config description:
5975 23:42:31.294775 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5976 23:42:31.301778 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5977 23:42:31.307939 SELPH_MODE 0: By rank 1: By Phase
5978 23:42:31.311547 ==============================================================
5979 23:42:31.314983 GAT_TRACK_EN = 0
5980 23:42:31.318169 RX_GATING_MODE = 2
5981 23:42:31.321609 RX_GATING_TRACK_MODE = 2
5982 23:42:31.324433 SELPH_MODE = 1
5983 23:42:31.327923 PICG_EARLY_EN = 1
5984 23:42:31.331516 VALID_LAT_VALUE = 1
5985 23:42:31.335064 ==============================================================
5986 23:42:31.338139 Enter into Gating configuration >>>>
5987 23:42:31.340918 Exit from Gating configuration <<<<
5988 23:42:31.344698 Enter into DVFS_PRE_config >>>>>
5989 23:42:31.358242 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5990 23:42:31.361360 Exit from DVFS_PRE_config <<<<<
5991 23:42:31.364574 Enter into PICG configuration >>>>
5992 23:42:31.367545 Exit from PICG configuration <<<<
5993 23:42:31.368011 [RX_INPUT] configuration >>>>>
5994 23:42:31.371234 [RX_INPUT] configuration <<<<<
5995 23:42:31.377404 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5996 23:42:31.381182 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5997 23:42:31.387344 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5998 23:42:31.393915 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5999 23:42:31.401031 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6000 23:42:31.407186 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6001 23:42:31.410500 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6002 23:42:31.413495 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6003 23:42:31.420568 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6004 23:42:31.423535 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6005 23:42:31.426731 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6006 23:42:31.433673 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6007 23:42:31.434236 ===================================
6008 23:42:31.436963 LPDDR4 DRAM CONFIGURATION
6009 23:42:31.440139 ===================================
6010 23:42:31.443136 EX_ROW_EN[0] = 0x0
6011 23:42:31.443617 EX_ROW_EN[1] = 0x0
6012 23:42:31.446871 LP4Y_EN = 0x0
6013 23:42:31.447456 WORK_FSP = 0x0
6014 23:42:31.450005 WL = 0x2
6015 23:42:31.450467 RL = 0x2
6016 23:42:31.453191 BL = 0x2
6017 23:42:31.456247 RPST = 0x0
6018 23:42:31.456654 RD_PRE = 0x0
6019 23:42:31.459873 WR_PRE = 0x1
6020 23:42:31.460336 WR_PST = 0x0
6021 23:42:31.463028 DBI_WR = 0x0
6022 23:42:31.463488 DBI_RD = 0x0
6023 23:42:31.466607 OTF = 0x1
6024 23:42:31.469668 ===================================
6025 23:42:31.473182 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6026 23:42:31.476343 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6027 23:42:31.480147 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6028 23:42:31.483440 ===================================
6029 23:42:31.486291 LPDDR4 DRAM CONFIGURATION
6030 23:42:31.489786 ===================================
6031 23:42:31.493453 EX_ROW_EN[0] = 0x10
6032 23:42:31.494004 EX_ROW_EN[1] = 0x0
6033 23:42:31.496379 LP4Y_EN = 0x0
6034 23:42:31.497043 WORK_FSP = 0x0
6035 23:42:31.499802 WL = 0x2
6036 23:42:31.500361 RL = 0x2
6037 23:42:31.503138 BL = 0x2
6038 23:42:31.503702 RPST = 0x0
6039 23:42:31.506273 RD_PRE = 0x0
6040 23:42:31.509781 WR_PRE = 0x1
6041 23:42:31.510240 WR_PST = 0x0
6042 23:42:31.512730 DBI_WR = 0x0
6043 23:42:31.513192 DBI_RD = 0x0
6044 23:42:31.516420 OTF = 0x1
6045 23:42:31.519121 ===================================
6046 23:42:31.522537 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6047 23:42:31.528379 nWR fixed to 30
6048 23:42:31.531699 [ModeRegInit_LP4] CH0 RK0
6049 23:42:31.532254 [ModeRegInit_LP4] CH0 RK1
6050 23:42:31.535185 [ModeRegInit_LP4] CH1 RK0
6051 23:42:31.537909 [ModeRegInit_LP4] CH1 RK1
6052 23:42:31.538461 match AC timing 18
6053 23:42:31.544519 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
6054 23:42:31.547773 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6055 23:42:31.551760 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6056 23:42:31.558232 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6057 23:42:31.561622 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6058 23:42:31.562184 ==
6059 23:42:31.564666 Dram Type= 6, Freq= 0, CH_0, rank 0
6060 23:42:31.568022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6061 23:42:31.568587 ==
6062 23:42:31.574636 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6063 23:42:31.581254 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
6064 23:42:31.584878 [CA 0] Center 36 (8~64) winsize 57
6065 23:42:31.587928 [CA 1] Center 36 (8~64) winsize 57
6066 23:42:31.591280 [CA 2] Center 36 (8~64) winsize 57
6067 23:42:31.594562 [CA 3] Center 36 (8~64) winsize 57
6068 23:42:31.595028 [CA 4] Center 36 (8~64) winsize 57
6069 23:42:31.597633 [CA 5] Center 36 (8~64) winsize 57
6070 23:42:31.598094
6071 23:42:31.604429 [CmdBusTrainingLP45] Vref(ca) range 1: 39
6072 23:42:31.604984
6073 23:42:31.607759 [CATrainingPosCal] consider 1 rank data
6074 23:42:31.611304 u2DelayCellTimex100 = 270/100 ps
6075 23:42:31.614180 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6076 23:42:31.618082 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6077 23:42:31.621429 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6078 23:42:31.624380 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6079 23:42:31.627943 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6080 23:42:31.631107 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6081 23:42:31.631571
6082 23:42:31.634092 CA PerBit enable=1, Macro0, CA PI delay=36
6083 23:42:31.634561
6084 23:42:31.637344 [CBTSetCACLKResult] CA Dly = 36
6085 23:42:31.641633 CS Dly: 1 (0~32)
6086 23:42:31.642190 ==
6087 23:42:31.644391 Dram Type= 6, Freq= 0, CH_0, rank 1
6088 23:42:31.647620 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6089 23:42:31.648183 ==
6090 23:42:31.654016 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6091 23:42:31.660744 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6092 23:42:31.661331 [CA 0] Center 36 (8~64) winsize 57
6093 23:42:31.664361 [CA 1] Center 36 (8~64) winsize 57
6094 23:42:31.667809 [CA 2] Center 36 (8~64) winsize 57
6095 23:42:31.670620 [CA 3] Center 36 (8~64) winsize 57
6096 23:42:31.673856 [CA 4] Center 36 (8~64) winsize 57
6097 23:42:31.677730 [CA 5] Center 36 (8~64) winsize 57
6098 23:42:31.678293
6099 23:42:31.681326 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6100 23:42:31.681895
6101 23:42:31.684045 [CATrainingPosCal] consider 2 rank data
6102 23:42:31.687521 u2DelayCellTimex100 = 270/100 ps
6103 23:42:31.691184 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6104 23:42:31.694253 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6105 23:42:31.700805 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6106 23:42:31.703917 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6107 23:42:31.707388 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6108 23:42:31.710939 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6109 23:42:31.711504
6110 23:42:31.714097 CA PerBit enable=1, Macro0, CA PI delay=36
6111 23:42:31.714622
6112 23:42:31.717364 [CBTSetCACLKResult] CA Dly = 36
6113 23:42:31.717877 CS Dly: 1 (0~32)
6114 23:42:31.718244
6115 23:42:31.720690 ----->DramcWriteLeveling(PI) begin...
6116 23:42:31.724527 ==
6117 23:42:31.727173 Dram Type= 6, Freq= 0, CH_0, rank 0
6118 23:42:31.730688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6119 23:42:31.731169 ==
6120 23:42:31.734450 Write leveling (Byte 0): 32 => 0
6121 23:42:31.736947 Write leveling (Byte 1): 32 => 0
6122 23:42:31.740138 DramcWriteLeveling(PI) end<-----
6123 23:42:31.740722
6124 23:42:31.741240 ==
6125 23:42:31.743657 Dram Type= 6, Freq= 0, CH_0, rank 0
6126 23:42:31.747095 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6127 23:42:31.747661 ==
6128 23:42:31.750442 [Gating] SW mode calibration
6129 23:42:31.756754 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6130 23:42:31.760114 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6131 23:42:31.766942 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6132 23:42:31.769955 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6133 23:42:31.773379 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6134 23:42:31.780207 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6135 23:42:31.783209 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6136 23:42:31.786949 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6137 23:42:31.793177 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6138 23:42:31.796455 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6139 23:42:31.799934 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6140 23:42:31.803222 Total UI for P1: 0, mck2ui 16
6141 23:42:31.806557 best dqsien dly found for B0: ( 0, 10, 16)
6142 23:42:31.809472 Total UI for P1: 0, mck2ui 16
6143 23:42:31.813036 best dqsien dly found for B1: ( 0, 10, 24)
6144 23:42:31.816590 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6145 23:42:31.823179 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6146 23:42:31.823668
6147 23:42:31.826036 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6148 23:42:31.829640 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6149 23:42:31.833027 [Gating] SW calibration Done
6150 23:42:31.833495 ==
6151 23:42:31.836511 Dram Type= 6, Freq= 0, CH_0, rank 0
6152 23:42:31.839958 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6153 23:42:31.840481 ==
6154 23:42:31.843328 RX Vref Scan: 0
6155 23:42:31.843842
6156 23:42:31.844173 RX Vref 0 -> 0, step: 1
6157 23:42:31.844486
6158 23:42:31.846088 RX Delay -410 -> 252, step: 16
6159 23:42:31.853129 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6160 23:42:31.856162 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6161 23:42:31.859410 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6162 23:42:31.862718 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6163 23:42:31.869833 iDelay=230, Bit 4, Center -35 (-298 ~ 229) 528
6164 23:42:31.872811 iDelay=230, Bit 5, Center -51 (-298 ~ 197) 496
6165 23:42:31.876079 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6166 23:42:31.879344 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6167 23:42:31.886227 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6168 23:42:31.889554 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6169 23:42:31.892530 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6170 23:42:31.895933 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6171 23:42:31.902567 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6172 23:42:31.905466 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6173 23:42:31.909033 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6174 23:42:31.912289 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6175 23:42:31.915342 ==
6176 23:42:31.918589 Dram Type= 6, Freq= 0, CH_0, rank 0
6177 23:42:31.922231 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6178 23:42:31.922761 ==
6179 23:42:31.923095 DQS Delay:
6180 23:42:31.925622 DQS0 = 51, DQS1 = 59
6181 23:42:31.926042 DQM Delay:
6182 23:42:31.928726 DQM0 = 12, DQM1 = 13
6183 23:42:31.929143 DQ Delay:
6184 23:42:31.931844 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6185 23:42:31.935221 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6186 23:42:31.938292 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6187 23:42:31.941780 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6188 23:42:31.942298
6189 23:42:31.942627
6190 23:42:31.942933 ==
6191 23:42:31.945346 Dram Type= 6, Freq= 0, CH_0, rank 0
6192 23:42:31.948216 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6193 23:42:31.948682 ==
6194 23:42:31.949018
6195 23:42:31.949365
6196 23:42:31.951970 TX Vref Scan disable
6197 23:42:31.952493 == TX Byte 0 ==
6198 23:42:31.958597 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6199 23:42:31.961929 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6200 23:42:31.962445 == TX Byte 1 ==
6201 23:42:31.968606 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6202 23:42:31.972022 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6203 23:42:31.972543 ==
6204 23:42:31.975038 Dram Type= 6, Freq= 0, CH_0, rank 0
6205 23:42:31.978467 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6206 23:42:31.978988 ==
6207 23:42:31.979322
6208 23:42:31.981504
6209 23:42:31.981923 TX Vref Scan disable
6210 23:42:31.984711 == TX Byte 0 ==
6211 23:42:31.988582 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6212 23:42:31.991750 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6213 23:42:31.995190 == TX Byte 1 ==
6214 23:42:31.998351 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6215 23:42:32.001470 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6216 23:42:32.001890
6217 23:42:32.002221 [DATLAT]
6218 23:42:32.004946 Freq=400, CH0 RK0
6219 23:42:32.005503
6220 23:42:32.007874 DATLAT Default: 0xf
6221 23:42:32.008338 0, 0xFFFF, sum = 0
6222 23:42:32.011711 1, 0xFFFF, sum = 0
6223 23:42:32.012240 2, 0xFFFF, sum = 0
6224 23:42:32.014594 3, 0xFFFF, sum = 0
6225 23:42:32.015039 4, 0xFFFF, sum = 0
6226 23:42:32.018001 5, 0xFFFF, sum = 0
6227 23:42:32.018422 6, 0xFFFF, sum = 0
6228 23:42:32.021429 7, 0xFFFF, sum = 0
6229 23:42:32.021956 8, 0xFFFF, sum = 0
6230 23:42:32.024786 9, 0xFFFF, sum = 0
6231 23:42:32.025405 10, 0xFFFF, sum = 0
6232 23:42:32.027746 11, 0xFFFF, sum = 0
6233 23:42:32.028213 12, 0x0, sum = 1
6234 23:42:32.031138 13, 0x0, sum = 2
6235 23:42:32.031605 14, 0x0, sum = 3
6236 23:42:32.034279 15, 0x0, sum = 4
6237 23:42:32.034743 best_step = 13
6238 23:42:32.035141
6239 23:42:32.035477 ==
6240 23:42:32.038139 Dram Type= 6, Freq= 0, CH_0, rank 0
6241 23:42:32.044318 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6242 23:42:32.044880 ==
6243 23:42:32.045472 RX Vref Scan: 1
6244 23:42:32.045846
6245 23:42:32.047768 RX Vref 0 -> 0, step: 1
6246 23:42:32.048322
6247 23:42:32.051188 RX Delay -359 -> 252, step: 8
6248 23:42:32.051816
6249 23:42:32.054086 Set Vref, RX VrefLevel [Byte0]: 46
6250 23:42:32.057411 [Byte1]: 52
6251 23:42:32.057870
6252 23:42:32.060692 Final RX Vref Byte 0 = 46 to rank0
6253 23:42:32.064174 Final RX Vref Byte 1 = 52 to rank0
6254 23:42:32.067836 Final RX Vref Byte 0 = 46 to rank1
6255 23:42:32.070713 Final RX Vref Byte 1 = 52 to rank1==
6256 23:42:32.074202 Dram Type= 6, Freq= 0, CH_0, rank 0
6257 23:42:32.077835 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6258 23:42:32.080901 ==
6259 23:42:32.081500 DQS Delay:
6260 23:42:32.081875 DQS0 = 52, DQS1 = 64
6261 23:42:32.084371 DQM Delay:
6262 23:42:32.084834 DQM0 = 8, DQM1 = 14
6263 23:42:32.087430 DQ Delay:
6264 23:42:32.088009 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6265 23:42:32.090672 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6266 23:42:32.094297 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =4
6267 23:42:32.097366 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6268 23:42:32.097932
6269 23:42:32.098296
6270 23:42:32.107309 [DQSOSCAuto] RK0, (LSB)MR18= 0xa7a7, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6271 23:42:32.110382 CH0 RK0: MR19=C0C, MR18=A7A7
6272 23:42:32.117228 CH0_RK0: MR19=0xC0C, MR18=0xA7A7, DQSOSC=389, MR23=63, INC=390, DEC=260
6273 23:42:32.117839 ==
6274 23:42:32.120552 Dram Type= 6, Freq= 0, CH_0, rank 1
6275 23:42:32.123895 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6276 23:42:32.124460 ==
6277 23:42:32.127324 [Gating] SW mode calibration
6278 23:42:32.133557 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6279 23:42:32.137157 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6280 23:42:32.143579 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6281 23:42:32.147003 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6282 23:42:32.150721 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 23:42:32.156966 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6284 23:42:32.160408 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 23:42:32.163568 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 23:42:32.170209 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 23:42:32.173036 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6288 23:42:32.176873 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 23:42:32.180169 Total UI for P1: 0, mck2ui 16
6290 23:42:32.183526 best dqsien dly found for B0: ( 0, 10, 16)
6291 23:42:32.186462 Total UI for P1: 0, mck2ui 16
6292 23:42:32.189883 best dqsien dly found for B1: ( 0, 10, 16)
6293 23:42:32.193365 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6294 23:42:32.199822 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6295 23:42:32.200394
6296 23:42:32.203143 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6297 23:42:32.206718 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6298 23:42:32.209574 [Gating] SW calibration Done
6299 23:42:32.210037 ==
6300 23:42:32.212759 Dram Type= 6, Freq= 0, CH_0, rank 1
6301 23:42:32.216170 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6302 23:42:32.216636 ==
6303 23:42:32.219500 RX Vref Scan: 0
6304 23:42:32.219964
6305 23:42:32.220326 RX Vref 0 -> 0, step: 1
6306 23:42:32.220663
6307 23:42:32.223127 RX Delay -410 -> 252, step: 16
6308 23:42:32.226571 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6309 23:42:32.232871 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6310 23:42:32.236400 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6311 23:42:32.239759 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6312 23:42:32.246227 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6313 23:42:32.249590 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6314 23:42:32.252902 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6315 23:42:32.256319 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6316 23:42:32.259477 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6317 23:42:32.265727 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6318 23:42:32.269542 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6319 23:42:32.272364 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6320 23:42:32.279179 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6321 23:42:32.282581 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6322 23:42:32.285546 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6323 23:42:32.288983 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6324 23:42:32.292674 ==
6325 23:42:32.293233 Dram Type= 6, Freq= 0, CH_0, rank 1
6326 23:42:32.299177 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6327 23:42:32.299743 ==
6328 23:42:32.300114 DQS Delay:
6329 23:42:32.302362 DQS0 = 43, DQS1 = 59
6330 23:42:32.302929 DQM Delay:
6331 23:42:32.305268 DQM0 = 7, DQM1 = 14
6332 23:42:32.305755 DQ Delay:
6333 23:42:32.308804 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6334 23:42:32.312275 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6335 23:42:32.315376 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6336 23:42:32.318982 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6337 23:42:32.319591
6338 23:42:32.319961
6339 23:42:32.320300 ==
6340 23:42:32.321972 Dram Type= 6, Freq= 0, CH_0, rank 1
6341 23:42:32.325544 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6342 23:42:32.326289 ==
6343 23:42:32.326713
6344 23:42:32.327055
6345 23:42:32.328603 TX Vref Scan disable
6346 23:42:32.329059 == TX Byte 0 ==
6347 23:42:32.331925 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6348 23:42:32.338411 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6349 23:42:32.338954 == TX Byte 1 ==
6350 23:42:32.341642 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6351 23:42:32.348859 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6352 23:42:32.349470 ==
6353 23:42:32.352003 Dram Type= 6, Freq= 0, CH_0, rank 1
6354 23:42:32.355451 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6355 23:42:32.356018 ==
6356 23:42:32.356387
6357 23:42:32.356724
6358 23:42:32.358932 TX Vref Scan disable
6359 23:42:32.359494 == TX Byte 0 ==
6360 23:42:32.364985 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6361 23:42:32.368311 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6362 23:42:32.368773 == TX Byte 1 ==
6363 23:42:32.374824 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6364 23:42:32.378194 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6365 23:42:32.378655
6366 23:42:32.379013 [DATLAT]
6367 23:42:32.381711 Freq=400, CH0 RK1
6368 23:42:32.382174
6369 23:42:32.382535 DATLAT Default: 0xd
6370 23:42:32.384899 0, 0xFFFF, sum = 0
6371 23:42:32.385403 1, 0xFFFF, sum = 0
6372 23:42:32.388392 2, 0xFFFF, sum = 0
6373 23:42:32.388953 3, 0xFFFF, sum = 0
6374 23:42:32.391977 4, 0xFFFF, sum = 0
6375 23:42:32.392617 5, 0xFFFF, sum = 0
6376 23:42:32.395049 6, 0xFFFF, sum = 0
6377 23:42:32.395614 7, 0xFFFF, sum = 0
6378 23:42:32.398080 8, 0xFFFF, sum = 0
6379 23:42:32.398640 9, 0xFFFF, sum = 0
6380 23:42:32.401459 10, 0xFFFF, sum = 0
6381 23:42:32.404756 11, 0xFFFF, sum = 0
6382 23:42:32.405354 12, 0x0, sum = 1
6383 23:42:32.405737 13, 0x0, sum = 2
6384 23:42:32.408284 14, 0x0, sum = 3
6385 23:42:32.409056 15, 0x0, sum = 4
6386 23:42:32.411702 best_step = 13
6387 23:42:32.412257
6388 23:42:32.412622 ==
6389 23:42:32.414456 Dram Type= 6, Freq= 0, CH_0, rank 1
6390 23:42:32.417916 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6391 23:42:32.418426 ==
6392 23:42:32.421130 RX Vref Scan: 0
6393 23:42:32.421620
6394 23:42:32.421987 RX Vref 0 -> 0, step: 1
6395 23:42:32.422325
6396 23:42:32.424361 RX Delay -359 -> 252, step: 8
6397 23:42:32.432813 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6398 23:42:32.436249 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6399 23:42:32.439473 iDelay=217, Bit 2, Center -40 (-287 ~ 208) 496
6400 23:42:32.443054 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6401 23:42:32.449852 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6402 23:42:32.453093 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6403 23:42:32.456212 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6404 23:42:32.459597 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6405 23:42:32.466459 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6406 23:42:32.469418 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6407 23:42:32.472849 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6408 23:42:32.479447 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6409 23:42:32.482735 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6410 23:42:32.486241 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6411 23:42:32.489445 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6412 23:42:32.496081 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6413 23:42:32.496640 ==
6414 23:42:32.499458 Dram Type= 6, Freq= 0, CH_0, rank 1
6415 23:42:32.502787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6416 23:42:32.503345 ==
6417 23:42:32.503712 DQS Delay:
6418 23:42:32.505517 DQS0 = 52, DQS1 = 60
6419 23:42:32.505979 DQM Delay:
6420 23:42:32.509057 DQM0 = 11, DQM1 = 11
6421 23:42:32.509645 DQ Delay:
6422 23:42:32.512370 DQ0 =4, DQ1 =16, DQ2 =12, DQ3 =8
6423 23:42:32.515786 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6424 23:42:32.519018 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6425 23:42:32.522490 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6426 23:42:32.523085
6427 23:42:32.523458
6428 23:42:32.528742 [DQSOSCAuto] RK1, (LSB)MR18= 0xbebe, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 386 ps
6429 23:42:32.532271 CH0 RK1: MR19=C0C, MR18=BEBE
6430 23:42:32.539038 CH0_RK1: MR19=0xC0C, MR18=0xBEBE, DQSOSC=386, MR23=63, INC=396, DEC=264
6431 23:42:32.541926 [RxdqsGatingPostProcess] freq 400
6432 23:42:32.549205 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6433 23:42:32.552365 Pre-setting of DQS Precalculation
6434 23:42:32.555800 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6435 23:42:32.556361 ==
6436 23:42:32.558646 Dram Type= 6, Freq= 0, CH_1, rank 0
6437 23:42:32.562205 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6438 23:42:32.562769 ==
6439 23:42:32.568738 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6440 23:42:32.575488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6441 23:42:32.578925 [CA 0] Center 36 (8~64) winsize 57
6442 23:42:32.581940 [CA 1] Center 36 (8~64) winsize 57
6443 23:42:32.585707 [CA 2] Center 36 (8~64) winsize 57
6444 23:42:32.589000 [CA 3] Center 36 (8~64) winsize 57
6445 23:42:32.591619 [CA 4] Center 36 (8~64) winsize 57
6446 23:42:32.592082 [CA 5] Center 36 (8~64) winsize 57
6447 23:42:32.595745
6448 23:42:32.598539 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6449 23:42:32.599094
6450 23:42:32.602216 [CATrainingPosCal] consider 1 rank data
6451 23:42:32.605649 u2DelayCellTimex100 = 270/100 ps
6452 23:42:32.608213 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6453 23:42:32.611837 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6454 23:42:32.615139 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6455 23:42:32.618253 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6456 23:42:32.621977 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6457 23:42:32.625263 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6458 23:42:32.625864
6459 23:42:32.628376 CA PerBit enable=1, Macro0, CA PI delay=36
6460 23:42:32.629013
6461 23:42:32.631874 [CBTSetCACLKResult] CA Dly = 36
6462 23:42:32.634658 CS Dly: 1 (0~32)
6463 23:42:32.635119 ==
6464 23:42:32.638027 Dram Type= 6, Freq= 0, CH_1, rank 1
6465 23:42:32.641758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6466 23:42:32.642222 ==
6467 23:42:32.648363 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6468 23:42:32.654993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6469 23:42:32.658066 [CA 0] Center 36 (8~64) winsize 57
6470 23:42:32.661703 [CA 1] Center 36 (8~64) winsize 57
6471 23:42:32.662261 [CA 2] Center 36 (8~64) winsize 57
6472 23:42:32.664746 [CA 3] Center 36 (8~64) winsize 57
6473 23:42:32.668269 [CA 4] Center 36 (8~64) winsize 57
6474 23:42:32.671382 [CA 5] Center 36 (8~64) winsize 57
6475 23:42:32.671946
6476 23:42:32.674919 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6477 23:42:32.675487
6478 23:42:32.681581 [CATrainingPosCal] consider 2 rank data
6479 23:42:32.682147 u2DelayCellTimex100 = 270/100 ps
6480 23:42:32.688019 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6481 23:42:32.690987 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6482 23:42:32.694324 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6483 23:42:32.698092 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6484 23:42:32.701096 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6485 23:42:32.705013 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6486 23:42:32.705607
6487 23:42:32.707822 CA PerBit enable=1, Macro0, CA PI delay=36
6488 23:42:32.708287
6489 23:42:32.711208 [CBTSetCACLKResult] CA Dly = 36
6490 23:42:32.714763 CS Dly: 1 (0~32)
6491 23:42:32.715261
6492 23:42:32.717990 ----->DramcWriteLeveling(PI) begin...
6493 23:42:32.718464 ==
6494 23:42:32.721396 Dram Type= 6, Freq= 0, CH_1, rank 0
6495 23:42:32.724644 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6496 23:42:32.725213 ==
6497 23:42:32.728059 Write leveling (Byte 0): 32 => 0
6498 23:42:32.731103 Write leveling (Byte 1): 32 => 0
6499 23:42:32.734328 DramcWriteLeveling(PI) end<-----
6500 23:42:32.734823
6501 23:42:32.735193 ==
6502 23:42:32.737708 Dram Type= 6, Freq= 0, CH_1, rank 0
6503 23:42:32.741683 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6504 23:42:32.742249 ==
6505 23:42:32.744310 [Gating] SW mode calibration
6506 23:42:32.750977 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6507 23:42:32.757600 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6508 23:42:32.761009 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6509 23:42:32.764387 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6510 23:42:32.771567 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6511 23:42:32.774138 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
6512 23:42:32.777476 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 23:42:32.784335 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6514 23:42:32.787398 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6515 23:42:32.790819 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6516 23:42:32.797723 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6517 23:42:32.798294 Total UI for P1: 0, mck2ui 16
6518 23:42:32.800761 best dqsien dly found for B0: ( 0, 10, 16)
6519 23:42:32.804176 Total UI for P1: 0, mck2ui 16
6520 23:42:32.807428 best dqsien dly found for B1: ( 0, 10, 16)
6521 23:42:32.814248 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6522 23:42:32.817187 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6523 23:42:32.817690
6524 23:42:32.820586 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6525 23:42:32.824537 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6526 23:42:32.827884 [Gating] SW calibration Done
6527 23:42:32.828443 ==
6528 23:42:32.830732 Dram Type= 6, Freq= 0, CH_1, rank 0
6529 23:42:32.834209 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6530 23:42:32.834953 ==
6531 23:42:32.837266 RX Vref Scan: 0
6532 23:42:32.837766
6533 23:42:32.838131 RX Vref 0 -> 0, step: 1
6534 23:42:32.838474
6535 23:42:32.840703 RX Delay -410 -> 252, step: 16
6536 23:42:32.847239 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6537 23:42:32.850501 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6538 23:42:32.853848 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6539 23:42:32.856943 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6540 23:42:32.863636 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6541 23:42:32.867183 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6542 23:42:32.870009 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6543 23:42:32.873464 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6544 23:42:32.880149 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6545 23:42:32.883239 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6546 23:42:32.886886 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6547 23:42:32.889934 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6548 23:42:32.896323 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6549 23:42:32.900135 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6550 23:42:32.903331 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6551 23:42:32.909941 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6552 23:42:32.910537 ==
6553 23:42:32.912976 Dram Type= 6, Freq= 0, CH_1, rank 0
6554 23:42:32.916057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6555 23:42:32.916696 ==
6556 23:42:32.917274 DQS Delay:
6557 23:42:32.919313 DQS0 = 43, DQS1 = 59
6558 23:42:32.919824 DQM Delay:
6559 23:42:32.922910 DQM0 = 6, DQM1 = 15
6560 23:42:32.923330 DQ Delay:
6561 23:42:32.925842 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6562 23:42:32.929588 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6563 23:42:32.932627 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6564 23:42:32.936647 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6565 23:42:32.937166
6566 23:42:32.937553
6567 23:42:32.937867 ==
6568 23:42:32.939697 Dram Type= 6, Freq= 0, CH_1, rank 0
6569 23:42:32.942345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6570 23:42:32.942795 ==
6571 23:42:32.943155
6572 23:42:32.943460
6573 23:42:32.945935 TX Vref Scan disable
6574 23:42:32.946357 == TX Byte 0 ==
6575 23:42:32.952372 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6576 23:42:32.955786 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6577 23:42:32.958768 == TX Byte 1 ==
6578 23:42:32.962292 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6579 23:42:32.965545 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6580 23:42:32.965967 ==
6581 23:42:32.969031 Dram Type= 6, Freq= 0, CH_1, rank 0
6582 23:42:32.972050 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6583 23:42:32.972482 ==
6584 23:42:32.976044
6585 23:42:32.976660
6586 23:42:32.976997 TX Vref Scan disable
6587 23:42:32.978952 == TX Byte 0 ==
6588 23:42:32.982355 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6589 23:42:32.985656 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6590 23:42:32.988979 == TX Byte 1 ==
6591 23:42:32.992135 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6592 23:42:32.995646 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6593 23:42:32.996070
6594 23:42:32.998875 [DATLAT]
6595 23:42:32.999423 Freq=400, CH1 RK0
6596 23:42:32.999939
6597 23:42:33.002335 DATLAT Default: 0xf
6598 23:42:33.002851 0, 0xFFFF, sum = 0
6599 23:42:33.005666 1, 0xFFFF, sum = 0
6600 23:42:33.006191 2, 0xFFFF, sum = 0
6601 23:42:33.009003 3, 0xFFFF, sum = 0
6602 23:42:33.009650 4, 0xFFFF, sum = 0
6603 23:42:33.012172 5, 0xFFFF, sum = 0
6604 23:42:33.012703 6, 0xFFFF, sum = 0
6605 23:42:33.015361 7, 0xFFFF, sum = 0
6606 23:42:33.015845 8, 0xFFFF, sum = 0
6607 23:42:33.018836 9, 0xFFFF, sum = 0
6608 23:42:33.019362 10, 0xFFFF, sum = 0
6609 23:42:33.021860 11, 0xFFFF, sum = 0
6610 23:42:33.022288 12, 0x0, sum = 1
6611 23:42:33.025193 13, 0x0, sum = 2
6612 23:42:33.025646 14, 0x0, sum = 3
6613 23:42:33.028633 15, 0x0, sum = 4
6614 23:42:33.029055 best_step = 13
6615 23:42:33.029409
6616 23:42:33.029771 ==
6617 23:42:33.032053 Dram Type= 6, Freq= 0, CH_1, rank 0
6618 23:42:33.038542 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6619 23:42:33.038964 ==
6620 23:42:33.039297 RX Vref Scan: 1
6621 23:42:33.039603
6622 23:42:33.042161 RX Vref 0 -> 0, step: 1
6623 23:42:33.042680
6624 23:42:33.045316 RX Delay -359 -> 252, step: 8
6625 23:42:33.045847
6626 23:42:33.048519 Set Vref, RX VrefLevel [Byte0]: 52
6627 23:42:33.051840 [Byte1]: 49
6628 23:42:33.055203
6629 23:42:33.055776 Final RX Vref Byte 0 = 52 to rank0
6630 23:42:33.058290 Final RX Vref Byte 1 = 49 to rank0
6631 23:42:33.061666 Final RX Vref Byte 0 = 52 to rank1
6632 23:42:33.065215 Final RX Vref Byte 1 = 49 to rank1==
6633 23:42:33.068274 Dram Type= 6, Freq= 0, CH_1, rank 0
6634 23:42:33.075051 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6635 23:42:33.075603 ==
6636 23:42:33.076077 DQS Delay:
6637 23:42:33.078163 DQS0 = 48, DQS1 = 64
6638 23:42:33.078582 DQM Delay:
6639 23:42:33.078908 DQM0 = 8, DQM1 = 15
6640 23:42:33.081690 DQ Delay:
6641 23:42:33.085046 DQ0 =12, DQ1 =0, DQ2 =0, DQ3 =4
6642 23:42:33.085622 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6643 23:42:33.088208 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6644 23:42:33.091333 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6645 23:42:33.091754
6646 23:42:33.092082
6647 23:42:33.101219 [DQSOSCAuto] RK0, (LSB)MR18= 0xcece, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 384 ps
6648 23:42:33.104625 CH1 RK0: MR19=C0C, MR18=CECE
6649 23:42:33.111348 CH1_RK0: MR19=0xC0C, MR18=0xCECE, DQSOSC=384, MR23=63, INC=400, DEC=267
6650 23:42:33.111776 ==
6651 23:42:33.114553 Dram Type= 6, Freq= 0, CH_1, rank 1
6652 23:42:33.118036 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6653 23:42:33.118458 ==
6654 23:42:33.121285 [Gating] SW mode calibration
6655 23:42:33.128018 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6656 23:42:33.131248 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6657 23:42:33.137879 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6658 23:42:33.141184 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6659 23:42:33.144405 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 23:42:33.151302 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6661 23:42:33.154584 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 23:42:33.157886 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 23:42:33.164662 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 23:42:33.167576 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6665 23:42:33.170909 Total UI for P1: 0, mck2ui 16
6666 23:42:33.174386 best dqsien dly found for B0: ( 0, 10, 8)
6667 23:42:33.177843 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6668 23:42:33.181047 Total UI for P1: 0, mck2ui 16
6669 23:42:33.184205 best dqsien dly found for B1: ( 0, 10, 16)
6670 23:42:33.187899 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6671 23:42:33.190896 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6672 23:42:33.194004
6673 23:42:33.197501 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6674 23:42:33.200435 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6675 23:42:33.203996 [Gating] SW calibration Done
6676 23:42:33.204558 ==
6677 23:42:33.206971 Dram Type= 6, Freq= 0, CH_1, rank 1
6678 23:42:33.210513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6679 23:42:33.211043 ==
6680 23:42:33.213978 RX Vref Scan: 0
6681 23:42:33.214433
6682 23:42:33.214833 RX Vref 0 -> 0, step: 1
6683 23:42:33.215180
6684 23:42:33.217078 RX Delay -410 -> 252, step: 16
6685 23:42:33.220613 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6686 23:42:33.227207 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6687 23:42:33.230116 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6688 23:42:33.233874 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6689 23:42:33.236813 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6690 23:42:33.243857 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6691 23:42:33.247022 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6692 23:42:33.250511 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6693 23:42:33.253643 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6694 23:42:33.260481 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6695 23:42:33.263556 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6696 23:42:33.267270 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6697 23:42:33.273338 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6698 23:42:33.277042 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6699 23:42:33.280098 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6700 23:42:33.283771 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6701 23:42:33.284351 ==
6702 23:42:33.286680 Dram Type= 6, Freq= 0, CH_1, rank 1
6703 23:42:33.293685 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6704 23:42:33.294247 ==
6705 23:42:33.294611 DQS Delay:
6706 23:42:33.296740 DQS0 = 35, DQS1 = 59
6707 23:42:33.297192 DQM Delay:
6708 23:42:33.297648 DQM0 = 3, DQM1 = 18
6709 23:42:33.300334 DQ Delay:
6710 23:42:33.303501 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6711 23:42:33.304068 DQ4 =0, DQ5 =16, DQ6 =8, DQ7 =0
6712 23:42:33.306520 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6713 23:42:33.309833 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =24
6714 23:42:33.310374
6715 23:42:33.313443
6716 23:42:33.313914 ==
6717 23:42:33.316707 Dram Type= 6, Freq= 0, CH_1, rank 1
6718 23:42:33.319844 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6719 23:42:33.320319 ==
6720 23:42:33.320797
6721 23:42:33.321242
6722 23:42:33.323497 TX Vref Scan disable
6723 23:42:33.324076 == TX Byte 0 ==
6724 23:42:33.326299 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6725 23:42:33.332907 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6726 23:42:33.333412 == TX Byte 1 ==
6727 23:42:33.336623 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6728 23:42:33.343622 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6729 23:42:33.344201 ==
6730 23:42:33.346616 Dram Type= 6, Freq= 0, CH_1, rank 1
6731 23:42:33.349912 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6732 23:42:33.350392 ==
6733 23:42:33.350874
6734 23:42:33.351325
6735 23:42:33.353121 TX Vref Scan disable
6736 23:42:33.353644 == TX Byte 0 ==
6737 23:42:33.356774 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6738 23:42:33.363434 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6739 23:42:33.364012 == TX Byte 1 ==
6740 23:42:33.366659 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6741 23:42:33.373062 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6742 23:42:33.373683
6743 23:42:33.374174 [DATLAT]
6744 23:42:33.374623 Freq=400, CH1 RK1
6745 23:42:33.375060
6746 23:42:33.376343 DATLAT Default: 0xd
6747 23:42:33.376816 0, 0xFFFF, sum = 0
6748 23:42:33.380247 1, 0xFFFF, sum = 0
6749 23:42:33.383393 2, 0xFFFF, sum = 0
6750 23:42:33.383975 3, 0xFFFF, sum = 0
6751 23:42:33.386662 4, 0xFFFF, sum = 0
6752 23:42:33.387243 5, 0xFFFF, sum = 0
6753 23:42:33.389792 6, 0xFFFF, sum = 0
6754 23:42:33.390373 7, 0xFFFF, sum = 0
6755 23:42:33.392754 8, 0xFFFF, sum = 0
6756 23:42:33.393232 9, 0xFFFF, sum = 0
6757 23:42:33.396340 10, 0xFFFF, sum = 0
6758 23:42:33.396928 11, 0xFFFF, sum = 0
6759 23:42:33.399268 12, 0x0, sum = 1
6760 23:42:33.399750 13, 0x0, sum = 2
6761 23:42:33.402868 14, 0x0, sum = 3
6762 23:42:33.403452 15, 0x0, sum = 4
6763 23:42:33.406087 best_step = 13
6764 23:42:33.406713
6765 23:42:33.407184 ==
6766 23:42:33.409361 Dram Type= 6, Freq= 0, CH_1, rank 1
6767 23:42:33.413057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6768 23:42:33.413589 ==
6769 23:42:33.414097 RX Vref Scan: 0
6770 23:42:33.415961
6771 23:42:33.416583 RX Vref 0 -> 0, step: 1
6772 23:42:33.416989
6773 23:42:33.419440 RX Delay -359 -> 252, step: 8
6774 23:42:33.426855 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6775 23:42:33.430188 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6776 23:42:33.433628 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6777 23:42:33.440338 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
6778 23:42:33.443650 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6779 23:42:33.446746 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6780 23:42:33.450000 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6781 23:42:33.453241 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6782 23:42:33.460110 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6783 23:42:33.463541 iDelay=217, Bit 9, Center -60 (-311 ~ 192) 504
6784 23:42:33.466861 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6785 23:42:33.473248 iDelay=217, Bit 11, Center -56 (-303 ~ 192) 496
6786 23:42:33.476982 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6787 23:42:33.479676 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6788 23:42:33.483486 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6789 23:42:33.489969 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6790 23:42:33.490517 ==
6791 23:42:33.492901 Dram Type= 6, Freq= 0, CH_1, rank 1
6792 23:42:33.496285 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6793 23:42:33.496746 ==
6794 23:42:33.497110 DQS Delay:
6795 23:42:33.499883 DQS0 = 48, DQS1 = 64
6796 23:42:33.500438 DQM Delay:
6797 23:42:33.503591 DQM0 = 9, DQM1 = 15
6798 23:42:33.504153 DQ Delay:
6799 23:42:33.506204 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6800 23:42:33.510016 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6801 23:42:33.512886 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6802 23:42:33.516365 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6803 23:42:33.517018
6804 23:42:33.517446
6805 23:42:33.523315 [DQSOSCAuto] RK1, (LSB)MR18= 0xa4a4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6806 23:42:33.526186 CH1 RK1: MR19=C0C, MR18=A4A4
6807 23:42:33.533036 CH1_RK1: MR19=0xC0C, MR18=0xA4A4, DQSOSC=389, MR23=63, INC=390, DEC=260
6808 23:42:33.536447 [RxdqsGatingPostProcess] freq 400
6809 23:42:33.542954 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6810 23:42:33.543510 Pre-setting of DQS Precalculation
6811 23:42:33.549653 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6812 23:42:33.556238 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6813 23:42:33.563393 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6814 23:42:33.563955
6815 23:42:33.564318
6816 23:42:33.565875 [Calibration Summary] 800 Mbps
6817 23:42:33.569278 CH 0, Rank 0
6818 23:42:33.569775 SW Impedance : PASS
6819 23:42:33.572665 DUTY Scan : NO K
6820 23:42:33.576295 ZQ Calibration : PASS
6821 23:42:33.576853 Jitter Meter : NO K
6822 23:42:33.579553 CBT Training : PASS
6823 23:42:33.582959 Write leveling : PASS
6824 23:42:33.583517 RX DQS gating : PASS
6825 23:42:33.586197 RX DQ/DQS(RDDQC) : PASS
6826 23:42:33.586762 TX DQ/DQS : PASS
6827 23:42:33.589639 RX DATLAT : PASS
6828 23:42:33.592842 RX DQ/DQS(Engine): PASS
6829 23:42:33.593427 TX OE : NO K
6830 23:42:33.596043 All Pass.
6831 23:42:33.596601
6832 23:42:33.596964 CH 0, Rank 1
6833 23:42:33.599407 SW Impedance : PASS
6834 23:42:33.599968 DUTY Scan : NO K
6835 23:42:33.602711 ZQ Calibration : PASS
6836 23:42:33.605885 Jitter Meter : NO K
6837 23:42:33.606447 CBT Training : PASS
6838 23:42:33.609063 Write leveling : NO K
6839 23:42:33.612192 RX DQS gating : PASS
6840 23:42:33.612651 RX DQ/DQS(RDDQC) : PASS
6841 23:42:33.615783 TX DQ/DQS : PASS
6842 23:42:33.618868 RX DATLAT : PASS
6843 23:42:33.619331 RX DQ/DQS(Engine): PASS
6844 23:42:33.622126 TX OE : NO K
6845 23:42:33.622591 All Pass.
6846 23:42:33.622960
6847 23:42:33.625781 CH 1, Rank 0
6848 23:42:33.626341 SW Impedance : PASS
6849 23:42:33.629384 DUTY Scan : NO K
6850 23:42:33.632355 ZQ Calibration : PASS
6851 23:42:33.632943 Jitter Meter : NO K
6852 23:42:33.635395 CBT Training : PASS
6853 23:42:33.638636 Write leveling : PASS
6854 23:42:33.639290 RX DQS gating : PASS
6855 23:42:33.642245 RX DQ/DQS(RDDQC) : PASS
6856 23:42:33.645632 TX DQ/DQS : PASS
6857 23:42:33.646216 RX DATLAT : PASS
6858 23:42:33.648866 RX DQ/DQS(Engine): PASS
6859 23:42:33.649371 TX OE : NO K
6860 23:42:33.652008 All Pass.
6861 23:42:33.652468
6862 23:42:33.652829 CH 1, Rank 1
6863 23:42:33.655765 SW Impedance : PASS
6864 23:42:33.656323 DUTY Scan : NO K
6865 23:42:33.658568 ZQ Calibration : PASS
6866 23:42:33.662513 Jitter Meter : NO K
6867 23:42:33.663070 CBT Training : PASS
6868 23:42:33.665226 Write leveling : NO K
6869 23:42:33.668528 RX DQS gating : PASS
6870 23:42:33.668990 RX DQ/DQS(RDDQC) : PASS
6871 23:42:33.672079 TX DQ/DQS : PASS
6872 23:42:33.675777 RX DATLAT : PASS
6873 23:42:33.676340 RX DQ/DQS(Engine): PASS
6874 23:42:33.679016 TX OE : NO K
6875 23:42:33.679577 All Pass.
6876 23:42:33.679941
6877 23:42:33.681997 DramC Write-DBI off
6878 23:42:33.685267 PER_BANK_REFRESH: Hybrid Mode
6879 23:42:33.685764 TX_TRACKING: ON
6880 23:42:33.695341 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6881 23:42:33.698774 [FAST_K] Save calibration result to emmc
6882 23:42:33.702063 dramc_set_vcore_voltage set vcore to 725000
6883 23:42:33.705039 Read voltage for 1600, 0
6884 23:42:33.705604 Vio18 = 0
6885 23:42:33.706078 Vcore = 725000
6886 23:42:33.708350 Vdram = 0
6887 23:42:33.708838 Vddq = 0
6888 23:42:33.709202 Vmddr = 0
6889 23:42:33.714655 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6890 23:42:33.718083 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6891 23:42:33.721527 MEM_TYPE=3, freq_sel=13
6892 23:42:33.725101 sv_algorithm_assistance_LP4_3733
6893 23:42:33.728223 ============ PULL DRAM RESETB DOWN ============
6894 23:42:33.734848 ========== PULL DRAM RESETB DOWN end =========
6895 23:42:33.738042 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6896 23:42:33.741283 ===================================
6897 23:42:33.744755 LPDDR4 DRAM CONFIGURATION
6898 23:42:33.748061 ===================================
6899 23:42:33.748612 EX_ROW_EN[0] = 0x0
6900 23:42:33.751385 EX_ROW_EN[1] = 0x0
6901 23:42:33.751845 LP4Y_EN = 0x0
6902 23:42:33.754776 WORK_FSP = 0x1
6903 23:42:33.755342 WL = 0x5
6904 23:42:33.757870 RL = 0x5
6905 23:42:33.758416 BL = 0x2
6906 23:42:33.760931 RPST = 0x0
6907 23:42:33.761434 RD_PRE = 0x0
6908 23:42:33.764477 WR_PRE = 0x1
6909 23:42:33.767758 WR_PST = 0x1
6910 23:42:33.768337 DBI_WR = 0x0
6911 23:42:33.771187 DBI_RD = 0x0
6912 23:42:33.771724 OTF = 0x1
6913 23:42:33.774480 ===================================
6914 23:42:33.777442 ===================================
6915 23:42:33.780903 ANA top config
6916 23:42:33.781506 ===================================
6917 23:42:33.784557 DLL_ASYNC_EN = 0
6918 23:42:33.787724 ALL_SLAVE_EN = 0
6919 23:42:33.790899 NEW_RANK_MODE = 1
6920 23:42:33.794148 DLL_IDLE_MODE = 1
6921 23:42:33.794621 LP45_APHY_COMB_EN = 1
6922 23:42:33.797458 TX_ODT_DIS = 0
6923 23:42:33.800703 NEW_8X_MODE = 1
6924 23:42:33.804486 ===================================
6925 23:42:33.807583 ===================================
6926 23:42:33.810556 data_rate = 3200
6927 23:42:33.813962 CKR = 1
6928 23:42:33.816955 DQ_P2S_RATIO = 8
6929 23:42:33.820913 ===================================
6930 23:42:33.821642 CA_P2S_RATIO = 8
6931 23:42:33.824004 DQ_CA_OPEN = 0
6932 23:42:33.827304 DQ_SEMI_OPEN = 0
6933 23:42:33.830683 CA_SEMI_OPEN = 0
6934 23:42:33.833780 CA_FULL_RATE = 0
6935 23:42:33.834256 DQ_CKDIV4_EN = 0
6936 23:42:33.837125 CA_CKDIV4_EN = 0
6937 23:42:33.840695 CA_PREDIV_EN = 0
6938 23:42:33.844327 PH8_DLY = 12
6939 23:42:33.847305 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6940 23:42:33.850343 DQ_AAMCK_DIV = 4
6941 23:42:33.854195 CA_AAMCK_DIV = 4
6942 23:42:33.854769 CA_ADMCK_DIV = 4
6943 23:42:33.856958 DQ_TRACK_CA_EN = 0
6944 23:42:33.860525 CA_PICK = 1600
6945 23:42:33.863707 CA_MCKIO = 1600
6946 23:42:33.867231 MCKIO_SEMI = 0
6947 23:42:33.870733 PLL_FREQ = 3068
6948 23:42:33.874007 DQ_UI_PI_RATIO = 32
6949 23:42:33.874482 CA_UI_PI_RATIO = 0
6950 23:42:33.877483 ===================================
6951 23:42:33.880550 ===================================
6952 23:42:33.883529 memory_type:LPDDR4
6953 23:42:33.887527 GP_NUM : 10
6954 23:42:33.888105 SRAM_EN : 1
6955 23:42:33.890072 MD32_EN : 0
6956 23:42:33.894037 ===================================
6957 23:42:33.896980 [ANA_INIT] >>>>>>>>>>>>>>
6958 23:42:33.900001 <<<<<< [CONFIGURE PHASE]: ANA_TX
6959 23:42:33.903513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6960 23:42:33.906694 ===================================
6961 23:42:33.907167 data_rate = 3200,PCW = 0X7600
6962 23:42:33.910578 ===================================
6963 23:42:33.913273 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6964 23:42:33.920122 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6965 23:42:33.926791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6966 23:42:33.930235 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6967 23:42:33.933325 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6968 23:42:33.936452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6969 23:42:33.939707 [ANA_INIT] flow start
6970 23:42:33.942978 [ANA_INIT] PLL >>>>>>>>
6971 23:42:33.943438 [ANA_INIT] PLL <<<<<<<<
6972 23:42:33.946281 [ANA_INIT] MIDPI >>>>>>>>
6973 23:42:33.949771 [ANA_INIT] MIDPI <<<<<<<<
6974 23:42:33.950268 [ANA_INIT] DLL >>>>>>>>
6975 23:42:33.952988 [ANA_INIT] DLL <<<<<<<<
6976 23:42:33.956732 [ANA_INIT] flow end
6977 23:42:33.959929 ============ LP4 DIFF to SE enter ============
6978 23:42:33.963279 ============ LP4 DIFF to SE exit ============
6979 23:42:33.966288 [ANA_INIT] <<<<<<<<<<<<<
6980 23:42:33.969746 [Flow] Enable top DCM control >>>>>
6981 23:42:33.972912 [Flow] Enable top DCM control <<<<<
6982 23:42:33.976747 Enable DLL master slave shuffle
6983 23:42:33.979665 ==============================================================
6984 23:42:33.983810 Gating Mode config
6985 23:42:33.989927 ==============================================================
6986 23:42:33.990492 Config description:
6987 23:42:33.999738 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6988 23:42:34.006253 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6989 23:42:34.009539 SELPH_MODE 0: By rank 1: By Phase
6990 23:42:34.016060 ==============================================================
6991 23:42:34.019481 GAT_TRACK_EN = 1
6992 23:42:34.022424 RX_GATING_MODE = 2
6993 23:42:34.025753 RX_GATING_TRACK_MODE = 2
6994 23:42:34.029644 SELPH_MODE = 1
6995 23:42:34.032736 PICG_EARLY_EN = 1
6996 23:42:34.035985 VALID_LAT_VALUE = 1
6997 23:42:34.039356 ==============================================================
6998 23:42:34.042796 Enter into Gating configuration >>>>
6999 23:42:34.046161 Exit from Gating configuration <<<<
7000 23:42:34.048998 Enter into DVFS_PRE_config >>>>>
7001 23:42:34.062432 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7002 23:42:34.062999 Exit from DVFS_PRE_config <<<<<
7003 23:42:34.065850 Enter into PICG configuration >>>>
7004 23:42:34.069357 Exit from PICG configuration <<<<
7005 23:42:34.072350 [RX_INPUT] configuration >>>>>
7006 23:42:34.075874 [RX_INPUT] configuration <<<<<
7007 23:42:34.082403 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7008 23:42:34.085963 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7009 23:42:34.092486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7010 23:42:34.099327 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7011 23:42:34.105457 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7012 23:42:34.112259 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7013 23:42:34.115672 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7014 23:42:34.118632 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7015 23:42:34.122229 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7016 23:42:34.128841 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7017 23:42:34.132147 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7018 23:42:34.135484 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7019 23:42:34.138857 ===================================
7020 23:42:34.141664 LPDDR4 DRAM CONFIGURATION
7021 23:42:34.145351 ===================================
7022 23:42:34.148571 EX_ROW_EN[0] = 0x0
7023 23:42:34.149134 EX_ROW_EN[1] = 0x0
7024 23:42:34.151923 LP4Y_EN = 0x0
7025 23:42:34.152484 WORK_FSP = 0x1
7026 23:42:34.155073 WL = 0x5
7027 23:42:34.155639 RL = 0x5
7028 23:42:34.158586 BL = 0x2
7029 23:42:34.159149 RPST = 0x0
7030 23:42:34.161714 RD_PRE = 0x0
7031 23:42:34.162178 WR_PRE = 0x1
7032 23:42:34.165525 WR_PST = 0x1
7033 23:42:34.166080 DBI_WR = 0x0
7034 23:42:34.168731 DBI_RD = 0x0
7035 23:42:34.169328 OTF = 0x1
7036 23:42:34.171586 ===================================
7037 23:42:34.178406 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7038 23:42:34.181499 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7039 23:42:34.184878 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7040 23:42:34.187942 ===================================
7041 23:42:34.191860 LPDDR4 DRAM CONFIGURATION
7042 23:42:34.194660 ===================================
7043 23:42:34.198689 EX_ROW_EN[0] = 0x10
7044 23:42:34.199156 EX_ROW_EN[1] = 0x0
7045 23:42:34.201228 LP4Y_EN = 0x0
7046 23:42:34.201847 WORK_FSP = 0x1
7047 23:42:34.204537 WL = 0x5
7048 23:42:34.205030 RL = 0x5
7049 23:42:34.208438 BL = 0x2
7050 23:42:34.208989 RPST = 0x0
7051 23:42:34.211164 RD_PRE = 0x0
7052 23:42:34.211628 WR_PRE = 0x1
7053 23:42:34.214903 WR_PST = 0x1
7054 23:42:34.215466 DBI_WR = 0x0
7055 23:42:34.217989 DBI_RD = 0x0
7056 23:42:34.218522 OTF = 0x1
7057 23:42:34.221142 ===================================
7058 23:42:34.227816 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7059 23:42:34.228409 ==
7060 23:42:34.231371 Dram Type= 6, Freq= 0, CH_0, rank 0
7061 23:42:34.237721 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7062 23:42:34.238404 ==
7063 23:42:34.238964 [Duty_Offset_Calibration]
7064 23:42:34.241069 B0:0 B1:2 CA:1
7065 23:42:34.241627
7066 23:42:34.244134 [DutyScan_Calibration_Flow] k_type=0
7067 23:42:34.253603
7068 23:42:34.254059 ==CLK 0==
7069 23:42:34.256737 Final CLK duty delay cell = 0
7070 23:42:34.260382 [0] MAX Duty = 5187%(X100), DQS PI = 24
7071 23:42:34.263825 [0] MIN Duty = 4938%(X100), DQS PI = 52
7072 23:42:34.266809 [0] AVG Duty = 5062%(X100)
7073 23:42:34.267303
7074 23:42:34.270323 CH0 CLK Duty spec in!! Max-Min= 249%
7075 23:42:34.273336 [DutyScan_Calibration_Flow] ====Done====
7076 23:42:34.273760
7077 23:42:34.276683 [DutyScan_Calibration_Flow] k_type=1
7078 23:42:34.293565
7079 23:42:34.294105 ==DQS 0 ==
7080 23:42:34.296805 Final DQS duty delay cell = 0
7081 23:42:34.300253 [0] MAX Duty = 5124%(X100), DQS PI = 34
7082 23:42:34.303540 [0] MIN Duty = 5000%(X100), DQS PI = 8
7083 23:42:34.306920 [0] AVG Duty = 5062%(X100)
7084 23:42:34.307402
7085 23:42:34.307879 ==DQS 1 ==
7086 23:42:34.310032 Final DQS duty delay cell = 0
7087 23:42:34.313500 [0] MAX Duty = 5031%(X100), DQS PI = 6
7088 23:42:34.316731 [0] MIN Duty = 4876%(X100), DQS PI = 18
7089 23:42:34.317191 [0] AVG Duty = 4953%(X100)
7090 23:42:34.320283
7091 23:42:34.323433 CH0 DQS 0 Duty spec in!! Max-Min= 124%
7092 23:42:34.323893
7093 23:42:34.326826 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7094 23:42:34.329999 [DutyScan_Calibration_Flow] ====Done====
7095 23:42:34.330456
7096 23:42:34.333363 [DutyScan_Calibration_Flow] k_type=3
7097 23:42:34.350873
7098 23:42:34.351401 ==DQM 0 ==
7099 23:42:34.354011 Final DQM duty delay cell = 0
7100 23:42:34.357254 [0] MAX Duty = 5187%(X100), DQS PI = 24
7101 23:42:34.360611 [0] MIN Duty = 4907%(X100), DQS PI = 42
7102 23:42:34.364175 [0] AVG Duty = 5047%(X100)
7103 23:42:34.364659
7104 23:42:34.365023 ==DQM 1 ==
7105 23:42:34.367318 Final DQM duty delay cell = 0
7106 23:42:34.370522 [0] MAX Duty = 5031%(X100), DQS PI = 50
7107 23:42:34.373748 [0] MIN Duty = 4782%(X100), DQS PI = 16
7108 23:42:34.377275 [0] AVG Duty = 4906%(X100)
7109 23:42:34.377863
7110 23:42:34.380732 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7111 23:42:34.381256
7112 23:42:34.383942 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7113 23:42:34.387662 [DutyScan_Calibration_Flow] ====Done====
7114 23:42:34.388224
7115 23:42:34.390563 [DutyScan_Calibration_Flow] k_type=2
7116 23:42:34.407090
7117 23:42:34.407618 ==DQ 0 ==
7118 23:42:34.410421 Final DQ duty delay cell = 0
7119 23:42:34.413342 [0] MAX Duty = 5218%(X100), DQS PI = 18
7120 23:42:34.416932 [0] MIN Duty = 4938%(X100), DQS PI = 56
7121 23:42:34.417431 [0] AVG Duty = 5078%(X100)
7122 23:42:34.420359
7123 23:42:34.420899 ==DQ 1 ==
7124 23:42:34.423546 Final DQ duty delay cell = -4
7125 23:42:34.426920 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7126 23:42:34.430044 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7127 23:42:34.433691 [-4] AVG Duty = 4953%(X100)
7128 23:42:34.434249
7129 23:42:34.437006 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7130 23:42:34.437807
7131 23:42:34.440715 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7132 23:42:34.443402 [DutyScan_Calibration_Flow] ====Done====
7133 23:42:34.443863 ==
7134 23:42:34.447063 Dram Type= 6, Freq= 0, CH_1, rank 0
7135 23:42:34.450228 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7136 23:42:34.450694 ==
7137 23:42:34.453643 [Duty_Offset_Calibration]
7138 23:42:34.454226 B0:0 B1:5 CA:-5
7139 23:42:34.454607
7140 23:42:34.456772 [DutyScan_Calibration_Flow] k_type=0
7141 23:42:34.467586
7142 23:42:34.468111 ==CLK 0==
7143 23:42:34.471248 Final CLK duty delay cell = 0
7144 23:42:34.474152 [0] MAX Duty = 5156%(X100), DQS PI = 20
7145 23:42:34.477718 [0] MIN Duty = 4906%(X100), DQS PI = 50
7146 23:42:34.480820 [0] AVG Duty = 5031%(X100)
7147 23:42:34.481278
7148 23:42:34.484446 CH1 CLK Duty spec in!! Max-Min= 250%
7149 23:42:34.487587 [DutyScan_Calibration_Flow] ====Done====
7150 23:42:34.488053
7151 23:42:34.490578 [DutyScan_Calibration_Flow] k_type=1
7152 23:42:34.507191
7153 23:42:34.507753 ==DQS 0 ==
7154 23:42:34.509860 Final DQS duty delay cell = 0
7155 23:42:34.513235 [0] MAX Duty = 5187%(X100), DQS PI = 22
7156 23:42:34.516661 [0] MIN Duty = 4907%(X100), DQS PI = 42
7157 23:42:34.519799 [0] AVG Duty = 5047%(X100)
7158 23:42:34.520264
7159 23:42:34.520647 ==DQS 1 ==
7160 23:42:34.523139 Final DQS duty delay cell = -4
7161 23:42:34.526402 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7162 23:42:34.529969 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7163 23:42:34.533187 [-4] AVG Duty = 4922%(X100)
7164 23:42:34.533777
7165 23:42:34.536848 CH1 DQS 0 Duty spec in!! Max-Min= 280%
7166 23:42:34.537545
7167 23:42:34.539883 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7168 23:42:34.543007 [DutyScan_Calibration_Flow] ====Done====
7169 23:42:34.543466
7170 23:42:34.546281 [DutyScan_Calibration_Flow] k_type=3
7171 23:42:34.562096
7172 23:42:34.562550 ==DQM 0 ==
7173 23:42:34.565646 Final DQM duty delay cell = -4
7174 23:42:34.569162 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7175 23:42:34.572734 [-4] MIN Duty = 4782%(X100), DQS PI = 46
7176 23:42:34.575460 [-4] AVG Duty = 4922%(X100)
7177 23:42:34.575941
7178 23:42:34.576311 ==DQM 1 ==
7179 23:42:34.578859 Final DQM duty delay cell = -4
7180 23:42:34.582334 [-4] MAX Duty = 5062%(X100), DQS PI = 0
7181 23:42:34.585417 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7182 23:42:34.588762 [-4] AVG Duty = 4984%(X100)
7183 23:42:34.589226
7184 23:42:34.592141 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7185 23:42:34.592669
7186 23:42:34.595603 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7187 23:42:34.598867 [DutyScan_Calibration_Flow] ====Done====
7188 23:42:34.599331
7189 23:42:34.601811 [DutyScan_Calibration_Flow] k_type=2
7190 23:42:34.619773
7191 23:42:34.620321 ==DQ 0 ==
7192 23:42:34.623315 Final DQ duty delay cell = 0
7193 23:42:34.626409 [0] MAX Duty = 5093%(X100), DQS PI = 18
7194 23:42:34.630180 [0] MIN Duty = 4969%(X100), DQS PI = 46
7195 23:42:34.630642 [0] AVG Duty = 5031%(X100)
7196 23:42:34.633148
7197 23:42:34.633651 ==DQ 1 ==
7198 23:42:34.636626 Final DQ duty delay cell = 0
7199 23:42:34.639621 [0] MAX Duty = 5062%(X100), DQS PI = 6
7200 23:42:34.642955 [0] MIN Duty = 4876%(X100), DQS PI = 24
7201 23:42:34.643413 [0] AVG Duty = 4969%(X100)
7202 23:42:34.643775
7203 23:42:34.649462 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7204 23:42:34.649988
7205 23:42:34.652774 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7206 23:42:34.655966 [DutyScan_Calibration_Flow] ====Done====
7207 23:42:34.659233 nWR fixed to 30
7208 23:42:34.659697 [ModeRegInit_LP4] CH0 RK0
7209 23:42:34.662599 [ModeRegInit_LP4] CH0 RK1
7210 23:42:34.666025 [ModeRegInit_LP4] CH1 RK0
7211 23:42:34.669415 [ModeRegInit_LP4] CH1 RK1
7212 23:42:34.669875 match AC timing 4
7213 23:42:34.676185 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7214 23:42:34.679242 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7215 23:42:34.682635 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7216 23:42:34.689101 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7217 23:42:34.692992 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7218 23:42:34.693577 [MiockJmeterHQA]
7219 23:42:34.693948
7220 23:42:34.696017 [DramcMiockJmeter] u1RxGatingPI = 0
7221 23:42:34.699282 0 : 4366, 4138
7222 23:42:34.699825 4 : 4253, 4026
7223 23:42:34.702179 8 : 4363, 4138
7224 23:42:34.702644 12 : 4252, 4027
7225 23:42:34.703012 16 : 4255, 4029
7226 23:42:34.705551 20 : 4252, 4027
7227 23:42:34.706085 24 : 4361, 4137
7228 23:42:34.709454 28 : 4253, 4027
7229 23:42:34.709982 32 : 4253, 4029
7230 23:42:34.712256 36 : 4250, 4027
7231 23:42:34.712716 40 : 4363, 4137
7232 23:42:34.715321 44 : 4361, 4137
7233 23:42:34.715793 48 : 4252, 4027
7234 23:42:34.716160 52 : 4250, 4026
7235 23:42:34.718701 56 : 4250, 4027
7236 23:42:34.719168 60 : 4250, 4027
7237 23:42:34.722178 64 : 4253, 4029
7238 23:42:34.722645 68 : 4361, 4138
7239 23:42:34.725904 72 : 4250, 4026
7240 23:42:34.726458 76 : 4250, 4027
7241 23:42:34.729113 80 : 4249, 4027
7242 23:42:34.729855 84 : 4253, 4029
7243 23:42:34.730254 88 : 4250, 4027
7244 23:42:34.732062 92 : 4360, 4137
7245 23:42:34.732525 96 : 4361, 4137
7246 23:42:34.735322 100 : 4250, 1699
7247 23:42:34.735910 104 : 4361, 0
7248 23:42:34.738652 108 : 4252, 0
7249 23:42:34.739342 112 : 4252, 0
7250 23:42:34.739757 116 : 4253, 0
7251 23:42:34.741847 120 : 4360, 0
7252 23:42:34.742315 124 : 4250, 0
7253 23:42:34.745592 128 : 4250, 0
7254 23:42:34.746059 132 : 4249, 0
7255 23:42:34.746426 136 : 4250, 0
7256 23:42:34.748461 140 : 4363, 0
7257 23:42:34.748973 144 : 4250, 0
7258 23:42:34.751648 148 : 4250, 0
7259 23:42:34.752112 152 : 4253, 0
7260 23:42:34.752481 156 : 4360, 0
7261 23:42:34.755499 160 : 4360, 0
7262 23:42:34.756096 164 : 4250, 0
7263 23:42:34.756470 168 : 4250, 0
7264 23:42:34.759150 172 : 4360, 0
7265 23:42:34.759720 176 : 4250, 0
7266 23:42:34.761680 180 : 4250, 0
7267 23:42:34.762145 184 : 4251, 0
7268 23:42:34.762515 188 : 4361, 0
7269 23:42:34.765237 192 : 4360, 0
7270 23:42:34.765751 196 : 4250, 0
7271 23:42:34.768378 200 : 4250, 0
7272 23:42:34.768847 204 : 4253, 0
7273 23:42:34.769220 208 : 4250, 0
7274 23:42:34.772287 212 : 4250, 0
7275 23:42:34.772787 216 : 4363, 0
7276 23:42:34.775633 220 : 4251, 763
7277 23:42:34.776128 224 : 4250, 4016
7278 23:42:34.776506 228 : 4360, 4138
7279 23:42:34.778771 232 : 4250, 4027
7280 23:42:34.779260 236 : 4250, 4026
7281 23:42:34.782103 240 : 4363, 4140
7282 23:42:34.782586 244 : 4250, 4027
7283 23:42:34.785344 248 : 4252, 4030
7284 23:42:34.785847 252 : 4250, 4026
7285 23:42:34.788844 256 : 4253, 4029
7286 23:42:34.789477 260 : 4250, 4027
7287 23:42:34.792028 264 : 4251, 4027
7288 23:42:34.792682 268 : 4361, 4137
7289 23:42:34.795280 272 : 4250, 4026
7290 23:42:34.795856 276 : 4250, 4027
7291 23:42:34.798351 280 : 4361, 4138
7292 23:42:34.798821 284 : 4249, 4027
7293 23:42:34.802109 288 : 4250, 4026
7294 23:42:34.802581 292 : 4363, 4140
7295 23:42:34.802953 296 : 4250, 4027
7296 23:42:34.805354 300 : 4249, 4027
7297 23:42:34.805942 304 : 4250, 4026
7298 23:42:34.808269 308 : 4253, 4029
7299 23:42:34.808736 312 : 4250, 4027
7300 23:42:34.811450 316 : 4250, 4027
7301 23:42:34.811921 320 : 4360, 4137
7302 23:42:34.814797 324 : 4250, 4026
7303 23:42:34.815268 328 : 4250, 4027
7304 23:42:34.818111 332 : 4360, 4138
7305 23:42:34.818579 336 : 4250, 3754
7306 23:42:34.821711 340 : 4250, 1887
7307 23:42:34.822182
7308 23:42:34.822549 MIOCK jitter meter ch=0
7309 23:42:34.822887
7310 23:42:34.824821 1T = (340-100) = 240 dly cells
7311 23:42:34.831488 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7312 23:42:34.831952 ==
7313 23:42:34.834712 Dram Type= 6, Freq= 0, CH_0, rank 0
7314 23:42:34.838002 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7315 23:42:34.838467 ==
7316 23:42:34.844444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7317 23:42:34.848392 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7318 23:42:34.851163 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7319 23:42:34.857749 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7320 23:42:34.867416 [CA 0] Center 42 (12~73) winsize 62
7321 23:42:34.870256 [CA 1] Center 42 (12~73) winsize 62
7322 23:42:34.874137 [CA 2] Center 39 (9~69) winsize 61
7323 23:42:34.876841 [CA 3] Center 38 (9~68) winsize 60
7324 23:42:34.880387 [CA 4] Center 37 (7~67) winsize 61
7325 23:42:34.883973 [CA 5] Center 36 (6~66) winsize 61
7326 23:42:34.884536
7327 23:42:34.887505 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7328 23:42:34.888071
7329 23:42:34.890464 [CATrainingPosCal] consider 1 rank data
7330 23:42:34.893663 u2DelayCellTimex100 = 271/100 ps
7331 23:42:34.900174 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7332 23:42:34.903267 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7333 23:42:34.906867 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7334 23:42:34.910063 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7335 23:42:34.913688 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7336 23:42:34.916667 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7337 23:42:34.917233
7338 23:42:34.919693 CA PerBit enable=1, Macro0, CA PI delay=36
7339 23:42:34.920242
7340 23:42:34.923557 [CBTSetCACLKResult] CA Dly = 36
7341 23:42:34.926532 CS Dly: 10 (0~41)
7342 23:42:34.929991 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7343 23:42:34.933218 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7344 23:42:34.933831 ==
7345 23:42:34.936795 Dram Type= 6, Freq= 0, CH_0, rank 1
7346 23:42:34.942871 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7347 23:42:34.943357 ==
7348 23:42:34.946604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7349 23:42:34.949830 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7350 23:42:34.956473 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7351 23:42:34.963133 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7352 23:42:34.969439 [CA 0] Center 42 (12~73) winsize 62
7353 23:42:34.972754 [CA 1] Center 41 (11~72) winsize 62
7354 23:42:34.976318 [CA 2] Center 38 (9~68) winsize 60
7355 23:42:34.979369 [CA 3] Center 37 (7~67) winsize 61
7356 23:42:34.982945 [CA 4] Center 35 (5~65) winsize 61
7357 23:42:34.986170 [CA 5] Center 35 (5~66) winsize 62
7358 23:42:34.986731
7359 23:42:34.989582 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7360 23:42:34.990043
7361 23:42:34.992743 [CATrainingPosCal] consider 2 rank data
7362 23:42:34.996168 u2DelayCellTimex100 = 271/100 ps
7363 23:42:35.002440 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7364 23:42:35.006176 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
7365 23:42:35.009063 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7366 23:42:35.012173 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7367 23:42:35.015453 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7368 23:42:35.018744 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7369 23:42:35.018878
7370 23:42:35.022304 CA PerBit enable=1, Macro0, CA PI delay=36
7371 23:42:35.022421
7372 23:42:35.025483 [CBTSetCACLKResult] CA Dly = 36
7373 23:42:35.029075 CS Dly: 11 (0~43)
7374 23:42:35.032174 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7375 23:42:35.035631 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7376 23:42:35.035725
7377 23:42:35.038794 ----->DramcWriteLeveling(PI) begin...
7378 23:42:35.038880 ==
7379 23:42:35.041882 Dram Type= 6, Freq= 0, CH_0, rank 0
7380 23:42:35.048679 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7381 23:42:35.048760 ==
7382 23:42:35.052122 Write leveling (Byte 0): 30 => 30
7383 23:42:35.052204 Write leveling (Byte 1): 27 => 27
7384 23:42:35.055454 DramcWriteLeveling(PI) end<-----
7385 23:42:35.055534
7386 23:42:35.058504 ==
7387 23:42:35.061796 Dram Type= 6, Freq= 0, CH_0, rank 0
7388 23:42:35.065498 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7389 23:42:35.065579 ==
7390 23:42:35.068343 [Gating] SW mode calibration
7391 23:42:35.075095 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7392 23:42:35.078479 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7393 23:42:35.085190 0 12 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7394 23:42:35.088532 0 12 4 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
7395 23:42:35.091559 0 12 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7396 23:42:35.098593 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7397 23:42:35.101896 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7398 23:42:35.105529 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7399 23:42:35.112061 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7400 23:42:35.115092 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7401 23:42:35.118799 0 13 0 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
7402 23:42:35.125280 0 13 4 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (1 0)
7403 23:42:35.128297 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7404 23:42:35.131754 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7405 23:42:35.138233 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7406 23:42:35.141760 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7407 23:42:35.144918 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7408 23:42:35.151837 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7409 23:42:35.155138 0 14 0 | B1->B0 | 2424 3d3d | 0 0 | (0 0) (0 0)
7410 23:42:35.158123 0 14 4 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
7411 23:42:35.165036 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7412 23:42:35.168450 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7413 23:42:35.172078 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7414 23:42:35.175042 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7415 23:42:35.181761 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7416 23:42:35.185124 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7417 23:42:35.188770 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7418 23:42:35.195310 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7419 23:42:35.198549 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7420 23:42:35.201407 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7421 23:42:35.208540 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7422 23:42:35.212470 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7423 23:42:35.215270 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7424 23:42:35.221884 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7425 23:42:35.224764 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7426 23:42:35.228091 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7427 23:42:35.234822 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7428 23:42:35.238756 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7429 23:42:35.241260 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7430 23:42:35.248010 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7431 23:42:35.251237 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7432 23:42:35.254520 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7433 23:42:35.261336 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7434 23:42:35.264662 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7435 23:42:35.267666 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7436 23:42:35.271349 Total UI for P1: 0, mck2ui 16
7437 23:42:35.274401 best dqsien dly found for B0: ( 1, 1, 0)
7438 23:42:35.277792 Total UI for P1: 0, mck2ui 16
7439 23:42:35.280862 best dqsien dly found for B1: ( 1, 1, 0)
7440 23:42:35.284305 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7441 23:42:35.287528 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
7442 23:42:35.287985
7443 23:42:35.291107 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7444 23:42:35.297777 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
7445 23:42:35.298311 [Gating] SW calibration Done
7446 23:42:35.298676 ==
7447 23:42:35.301437 Dram Type= 6, Freq= 0, CH_0, rank 0
7448 23:42:35.307569 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7449 23:42:35.307988 ==
7450 23:42:35.308315 RX Vref Scan: 0
7451 23:42:35.308619
7452 23:42:35.311300 RX Vref 0 -> 0, step: 1
7453 23:42:35.311819
7454 23:42:35.314365 RX Delay 0 -> 252, step: 8
7455 23:42:35.317800 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7456 23:42:35.320969 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7457 23:42:35.324661 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7458 23:42:35.327527 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7459 23:42:35.334262 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7460 23:42:35.337592 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7461 23:42:35.340851 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7462 23:42:35.344080 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7463 23:42:35.347409 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7464 23:42:35.353798 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7465 23:42:35.357151 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7466 23:42:35.360711 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7467 23:42:35.363744 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7468 23:42:35.370737 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7469 23:42:35.373780 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7470 23:42:35.377005 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7471 23:42:35.377452 ==
7472 23:42:35.380350 Dram Type= 6, Freq= 0, CH_0, rank 0
7473 23:42:35.383643 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7474 23:42:35.384062 ==
7475 23:42:35.387040 DQS Delay:
7476 23:42:35.387454 DQS0 = 0, DQS1 = 0
7477 23:42:35.390590 DQM Delay:
7478 23:42:35.391134 DQM0 = 129, DQM1 = 124
7479 23:42:35.393863 DQ Delay:
7480 23:42:35.396883 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7481 23:42:35.400443 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7482 23:42:35.403581 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7483 23:42:35.406982 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7484 23:42:35.407402
7485 23:42:35.407728
7486 23:42:35.408028 ==
7487 23:42:35.410463 Dram Type= 6, Freq= 0, CH_0, rank 0
7488 23:42:35.413781 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7489 23:42:35.414215 ==
7490 23:42:35.414740
7491 23:42:35.415177
7492 23:42:35.416510 TX Vref Scan disable
7493 23:42:35.419964 == TX Byte 0 ==
7494 23:42:35.423793 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7495 23:42:35.426774 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7496 23:42:35.429985 == TX Byte 1 ==
7497 23:42:35.433634 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7498 23:42:35.436614 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7499 23:42:35.437031 ==
7500 23:42:35.440272 Dram Type= 6, Freq= 0, CH_0, rank 0
7501 23:42:35.446566 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7502 23:42:35.446982 ==
7503 23:42:35.458063
7504 23:42:35.461392 TX Vref early break, caculate TX vref
7505 23:42:35.464852 TX Vref=16, minBit 8, minWin=22, winSum=373
7506 23:42:35.468115 TX Vref=18, minBit 7, minWin=23, winSum=384
7507 23:42:35.471522 TX Vref=20, minBit 8, minWin=23, winSum=390
7508 23:42:35.474749 TX Vref=22, minBit 9, minWin=23, winSum=401
7509 23:42:35.478706 TX Vref=24, minBit 8, minWin=24, winSum=406
7510 23:42:35.484835 TX Vref=26, minBit 2, minWin=25, winSum=411
7511 23:42:35.488414 TX Vref=28, minBit 8, minWin=25, winSum=420
7512 23:42:35.491473 TX Vref=30, minBit 0, minWin=25, winSum=409
7513 23:42:35.494708 TX Vref=32, minBit 1, minWin=24, winSum=400
7514 23:42:35.498004 TX Vref=34, minBit 8, minWin=23, winSum=395
7515 23:42:35.504843 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 28
7516 23:42:35.505259
7517 23:42:35.507974 Final TX Range 0 Vref 28
7518 23:42:35.508388
7519 23:42:35.508716 ==
7520 23:42:35.511702 Dram Type= 6, Freq= 0, CH_0, rank 0
7521 23:42:35.514859 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7522 23:42:35.515278 ==
7523 23:42:35.515607
7524 23:42:35.515909
7525 23:42:35.517617 TX Vref Scan disable
7526 23:42:35.524508 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7527 23:42:35.524955 == TX Byte 0 ==
7528 23:42:35.528190 u2DelayCellOfst[0]=14 cells (4 PI)
7529 23:42:35.530946 u2DelayCellOfst[1]=21 cells (6 PI)
7530 23:42:35.534416 u2DelayCellOfst[2]=14 cells (4 PI)
7531 23:42:35.537763 u2DelayCellOfst[3]=14 cells (4 PI)
7532 23:42:35.541324 u2DelayCellOfst[4]=7 cells (2 PI)
7533 23:42:35.544345 u2DelayCellOfst[5]=0 cells (0 PI)
7534 23:42:35.547624 u2DelayCellOfst[6]=18 cells (5 PI)
7535 23:42:35.550851 u2DelayCellOfst[7]=18 cells (5 PI)
7536 23:42:35.554309 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7537 23:42:35.557656 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7538 23:42:35.561268 == TX Byte 1 ==
7539 23:42:35.561805 u2DelayCellOfst[8]=3 cells (1 PI)
7540 23:42:35.564546 u2DelayCellOfst[9]=0 cells (0 PI)
7541 23:42:35.568332 u2DelayCellOfst[10]=10 cells (3 PI)
7542 23:42:35.571040 u2DelayCellOfst[11]=7 cells (2 PI)
7543 23:42:35.573972 u2DelayCellOfst[12]=14 cells (4 PI)
7544 23:42:35.577376 u2DelayCellOfst[13]=18 cells (5 PI)
7545 23:42:35.580782 u2DelayCellOfst[14]=21 cells (6 PI)
7546 23:42:35.584146 u2DelayCellOfst[15]=14 cells (4 PI)
7547 23:42:35.587426 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7548 23:42:35.594091 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7549 23:42:35.594507 DramC Write-DBI on
7550 23:42:35.594839 ==
7551 23:42:35.597445 Dram Type= 6, Freq= 0, CH_0, rank 0
7552 23:42:35.603946 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7553 23:42:35.604369 ==
7554 23:42:35.604699
7555 23:42:35.605002
7556 23:42:35.605328 TX Vref Scan disable
7557 23:42:35.607532 == TX Byte 0 ==
7558 23:42:35.610955 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7559 23:42:35.614444 == TX Byte 1 ==
7560 23:42:35.617558 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7561 23:42:35.621067 DramC Write-DBI off
7562 23:42:35.621585
7563 23:42:35.621924 [DATLAT]
7564 23:42:35.622234 Freq=1600, CH0 RK0
7565 23:42:35.622533
7566 23:42:35.624240 DATLAT Default: 0xf
7567 23:42:35.624655 0, 0xFFFF, sum = 0
7568 23:42:35.627638 1, 0xFFFF, sum = 0
7569 23:42:35.628060 2, 0xFFFF, sum = 0
7570 23:42:35.631013 3, 0xFFFF, sum = 0
7571 23:42:35.633895 4, 0xFFFF, sum = 0
7572 23:42:35.634414 5, 0xFFFF, sum = 0
7573 23:42:35.637416 6, 0xFFFF, sum = 0
7574 23:42:35.637853 7, 0xFFFF, sum = 0
7575 23:42:35.640717 8, 0xFFFF, sum = 0
7576 23:42:35.641135 9, 0xFFFF, sum = 0
7577 23:42:35.644144 10, 0xFFFF, sum = 0
7578 23:42:35.644591 11, 0xFFFF, sum = 0
7579 23:42:35.647658 12, 0xFFF, sum = 0
7580 23:42:35.648080 13, 0x0, sum = 1
7581 23:42:35.650941 14, 0x0, sum = 2
7582 23:42:35.651362 15, 0x0, sum = 3
7583 23:42:35.653892 16, 0x0, sum = 4
7584 23:42:35.654318 best_step = 14
7585 23:42:35.654644
7586 23:42:35.654949 ==
7587 23:42:35.657203 Dram Type= 6, Freq= 0, CH_0, rank 0
7588 23:42:35.660692 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7589 23:42:35.663920 ==
7590 23:42:35.664331 RX Vref Scan: 1
7591 23:42:35.664660
7592 23:42:35.667402 Set Vref Range= 24 -> 127
7593 23:42:35.667817
7594 23:42:35.668145 RX Vref 24 -> 127, step: 1
7595 23:42:35.670426
7596 23:42:35.670839 RX Delay 11 -> 252, step: 4
7597 23:42:35.671224
7598 23:42:35.673706 Set Vref, RX VrefLevel [Byte0]: 24
7599 23:42:35.677230 [Byte1]: 24
7600 23:42:35.680872
7601 23:42:35.681404 Set Vref, RX VrefLevel [Byte0]: 25
7602 23:42:35.684313 [Byte1]: 25
7603 23:42:35.688371
7604 23:42:35.688789 Set Vref, RX VrefLevel [Byte0]: 26
7605 23:42:35.691714 [Byte1]: 26
7606 23:42:35.696216
7607 23:42:35.696634 Set Vref, RX VrefLevel [Byte0]: 27
7608 23:42:35.699425 [Byte1]: 27
7609 23:42:35.703795
7610 23:42:35.704209 Set Vref, RX VrefLevel [Byte0]: 28
7611 23:42:35.706976 [Byte1]: 28
7612 23:42:35.711551
7613 23:42:35.711970 Set Vref, RX VrefLevel [Byte0]: 29
7614 23:42:35.714689 [Byte1]: 29
7615 23:42:35.718799
7616 23:42:35.719352 Set Vref, RX VrefLevel [Byte0]: 30
7617 23:42:35.722197 [Byte1]: 30
7618 23:42:35.726439
7619 23:42:35.726858 Set Vref, RX VrefLevel [Byte0]: 31
7620 23:42:35.729918 [Byte1]: 31
7621 23:42:35.733843
7622 23:42:35.734261 Set Vref, RX VrefLevel [Byte0]: 32
7623 23:42:35.737458 [Byte1]: 32
7624 23:42:35.741769
7625 23:42:35.742184 Set Vref, RX VrefLevel [Byte0]: 33
7626 23:42:35.744799 [Byte1]: 33
7627 23:42:35.749546
7628 23:42:35.749967 Set Vref, RX VrefLevel [Byte0]: 34
7629 23:42:35.752514 [Byte1]: 34
7630 23:42:35.756920
7631 23:42:35.757397 Set Vref, RX VrefLevel [Byte0]: 35
7632 23:42:35.760207 [Byte1]: 35
7633 23:42:35.764612
7634 23:42:35.765031 Set Vref, RX VrefLevel [Byte0]: 36
7635 23:42:35.767702 [Byte1]: 36
7636 23:42:35.772111
7637 23:42:35.772528 Set Vref, RX VrefLevel [Byte0]: 37
7638 23:42:35.775619 [Byte1]: 37
7639 23:42:35.780083
7640 23:42:35.780501 Set Vref, RX VrefLevel [Byte0]: 38
7641 23:42:35.783288 [Byte1]: 38
7642 23:42:35.787239
7643 23:42:35.787662 Set Vref, RX VrefLevel [Byte0]: 39
7644 23:42:35.790766 [Byte1]: 39
7645 23:42:35.795031
7646 23:42:35.795449 Set Vref, RX VrefLevel [Byte0]: 40
7647 23:42:35.798525 [Byte1]: 40
7648 23:42:35.802560
7649 23:42:35.802977 Set Vref, RX VrefLevel [Byte0]: 41
7650 23:42:35.806095 [Byte1]: 41
7651 23:42:35.810391
7652 23:42:35.810807 Set Vref, RX VrefLevel [Byte0]: 42
7653 23:42:35.813404 [Byte1]: 42
7654 23:42:35.818072
7655 23:42:35.818487 Set Vref, RX VrefLevel [Byte0]: 43
7656 23:42:35.821469 [Byte1]: 43
7657 23:42:35.825514
7658 23:42:35.825941 Set Vref, RX VrefLevel [Byte0]: 44
7659 23:42:35.828691 [Byte1]: 44
7660 23:42:35.833339
7661 23:42:35.833867 Set Vref, RX VrefLevel [Byte0]: 45
7662 23:42:35.836885 [Byte1]: 45
7663 23:42:35.840543
7664 23:42:35.840969 Set Vref, RX VrefLevel [Byte0]: 46
7665 23:42:35.844049 [Byte1]: 46
7666 23:42:35.848303
7667 23:42:35.848723 Set Vref, RX VrefLevel [Byte0]: 47
7668 23:42:35.851688 [Byte1]: 47
7669 23:42:35.855811
7670 23:42:35.856231 Set Vref, RX VrefLevel [Byte0]: 48
7671 23:42:35.859580 [Byte1]: 48
7672 23:42:35.863707
7673 23:42:35.864128 Set Vref, RX VrefLevel [Byte0]: 49
7674 23:42:35.866937 [Byte1]: 49
7675 23:42:35.871267
7676 23:42:35.871688 Set Vref, RX VrefLevel [Byte0]: 50
7677 23:42:35.874374 [Byte1]: 50
7678 23:42:35.878674
7679 23:42:35.879095 Set Vref, RX VrefLevel [Byte0]: 51
7680 23:42:35.881976 [Byte1]: 51
7681 23:42:35.886681
7682 23:42:35.887101 Set Vref, RX VrefLevel [Byte0]: 52
7683 23:42:35.889806 [Byte1]: 52
7684 23:42:35.893861
7685 23:42:35.894281 Set Vref, RX VrefLevel [Byte0]: 53
7686 23:42:35.897409 [Byte1]: 53
7687 23:42:35.901662
7688 23:42:35.902110 Set Vref, RX VrefLevel [Byte0]: 54
7689 23:42:35.905218 [Byte1]: 54
7690 23:42:35.909155
7691 23:42:35.909644 Set Vref, RX VrefLevel [Byte0]: 55
7692 23:42:35.912358 [Byte1]: 55
7693 23:42:35.916801
7694 23:42:35.917228 Set Vref, RX VrefLevel [Byte0]: 56
7695 23:42:35.920036 [Byte1]: 56
7696 23:42:35.924513
7697 23:42:35.924935 Set Vref, RX VrefLevel [Byte0]: 57
7698 23:42:35.927768 [Byte1]: 57
7699 23:42:35.932476
7700 23:42:35.932896 Set Vref, RX VrefLevel [Byte0]: 58
7701 23:42:35.935129 [Byte1]: 58
7702 23:42:35.939818
7703 23:42:35.940242 Set Vref, RX VrefLevel [Byte0]: 59
7704 23:42:35.942967 [Byte1]: 59
7705 23:42:35.947387
7706 23:42:35.947809 Set Vref, RX VrefLevel [Byte0]: 60
7707 23:42:35.950405 [Byte1]: 60
7708 23:42:35.954829
7709 23:42:35.955249 Set Vref, RX VrefLevel [Byte0]: 61
7710 23:42:35.958239 [Byte1]: 61
7711 23:42:35.962492
7712 23:42:35.962913 Set Vref, RX VrefLevel [Byte0]: 62
7713 23:42:35.965820 [Byte1]: 62
7714 23:42:35.970004
7715 23:42:35.970425 Set Vref, RX VrefLevel [Byte0]: 63
7716 23:42:35.973586 [Byte1]: 63
7717 23:42:35.978047
7718 23:42:35.978467 Set Vref, RX VrefLevel [Byte0]: 64
7719 23:42:35.980934 [Byte1]: 64
7720 23:42:35.985259
7721 23:42:35.985723 Set Vref, RX VrefLevel [Byte0]: 65
7722 23:42:35.988827 [Byte1]: 65
7723 23:42:35.993136
7724 23:42:35.993605 Set Vref, RX VrefLevel [Byte0]: 66
7725 23:42:35.996226 [Byte1]: 66
7726 23:42:36.000571
7727 23:42:36.000994 Set Vref, RX VrefLevel [Byte0]: 67
7728 23:42:36.004209 [Byte1]: 67
7729 23:42:36.008232
7730 23:42:36.008651 Set Vref, RX VrefLevel [Byte0]: 68
7731 23:42:36.011708 [Byte1]: 68
7732 23:42:36.015707
7733 23:42:36.016223 Set Vref, RX VrefLevel [Byte0]: 69
7734 23:42:36.018987 [Byte1]: 69
7735 23:42:36.023392
7736 23:42:36.023913 Set Vref, RX VrefLevel [Byte0]: 70
7737 23:42:36.026535 [Byte1]: 70
7738 23:42:36.031021
7739 23:42:36.031444 Set Vref, RX VrefLevel [Byte0]: 71
7740 23:42:36.034391 [Byte1]: 71
7741 23:42:36.038731
7742 23:42:36.039152 Set Vref, RX VrefLevel [Byte0]: 72
7743 23:42:36.041902 [Byte1]: 72
7744 23:42:36.046364
7745 23:42:36.046787 Set Vref, RX VrefLevel [Byte0]: 73
7746 23:42:36.049359 [Byte1]: 73
7747 23:42:36.053826
7748 23:42:36.054251 Final RX Vref Byte 0 = 54 to rank0
7749 23:42:36.057205 Final RX Vref Byte 1 = 56 to rank0
7750 23:42:36.060493 Final RX Vref Byte 0 = 54 to rank1
7751 23:42:36.063727 Final RX Vref Byte 1 = 56 to rank1==
7752 23:42:36.067044 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 23:42:36.073465 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7754 23:42:36.073892 ==
7755 23:42:36.074227 DQS Delay:
7756 23:42:36.076999 DQS0 = 0, DQS1 = 0
7757 23:42:36.077455 DQM Delay:
7758 23:42:36.077795 DQM0 = 127, DQM1 = 121
7759 23:42:36.080433 DQ Delay:
7760 23:42:36.083721 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =122
7761 23:42:36.087545 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7762 23:42:36.090207 DQ8 =112, DQ9 =104, DQ10 =120, DQ11 =112
7763 23:42:36.093896 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7764 23:42:36.094321
7765 23:42:36.094656
7766 23:42:36.094960
7767 23:42:36.096719 [DramC_TX_OE_Calibration] TA2
7768 23:42:36.100116 Original DQ_B0 (3 6) =30, OEN = 27
7769 23:42:36.103829 Original DQ_B1 (3 6) =30, OEN = 27
7770 23:42:36.106746 24, 0x0, End_B0=24 End_B1=24
7771 23:42:36.107174 25, 0x0, End_B0=25 End_B1=25
7772 23:42:36.110241 26, 0x0, End_B0=26 End_B1=26
7773 23:42:36.113432 27, 0x0, End_B0=27 End_B1=27
7774 23:42:36.116876 28, 0x0, End_B0=28 End_B1=28
7775 23:42:36.119967 29, 0x0, End_B0=29 End_B1=29
7776 23:42:36.120398 30, 0x0, End_B0=30 End_B1=30
7777 23:42:36.123656 31, 0x4141, End_B0=30 End_B1=30
7778 23:42:36.126961 Byte0 end_step=30 best_step=27
7779 23:42:36.129993 Byte1 end_step=30 best_step=27
7780 23:42:36.133422 Byte0 TX OE(2T, 0.5T) = (3, 3)
7781 23:42:36.136826 Byte1 TX OE(2T, 0.5T) = (3, 3)
7782 23:42:36.137247
7783 23:42:36.137615
7784 23:42:36.143842 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7785 23:42:36.146709 CH0 RK0: MR19=303, MR18=1F1F
7786 23:42:36.153261 CH0_RK0: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
7787 23:42:36.153717
7788 23:42:36.156612 ----->DramcWriteLeveling(PI) begin...
7789 23:42:36.157041 ==
7790 23:42:36.160413 Dram Type= 6, Freq= 0, CH_0, rank 1
7791 23:42:36.163542 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7792 23:42:36.163972 ==
7793 23:42:36.166734 Write leveling (Byte 0): 30 => 30
7794 23:42:36.169905 Write leveling (Byte 1): 27 => 27
7795 23:42:36.173285 DramcWriteLeveling(PI) end<-----
7796 23:42:36.173736
7797 23:42:36.174070 ==
7798 23:42:36.176657 Dram Type= 6, Freq= 0, CH_0, rank 1
7799 23:42:36.179771 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7800 23:42:36.180195 ==
7801 23:42:36.183288 [Gating] SW mode calibration
7802 23:42:36.190088 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7803 23:42:36.196384 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7804 23:42:36.199616 0 12 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (1 1)
7805 23:42:36.206298 0 12 4 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7806 23:42:36.209809 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7807 23:42:36.213035 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7808 23:42:36.219627 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7809 23:42:36.222807 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7810 23:42:36.226096 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7811 23:42:36.229491 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7812 23:42:36.236111 0 13 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
7813 23:42:36.239605 0 13 4 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)
7814 23:42:36.242852 0 13 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7815 23:42:36.249269 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7816 23:42:36.252935 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7817 23:42:36.256007 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7818 23:42:36.262498 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7819 23:42:36.265783 0 13 28 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
7820 23:42:36.269390 0 14 0 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
7821 23:42:36.276002 0 14 4 | B1->B0 | 3433 4646 | 1 0 | (0 0) (0 0)
7822 23:42:36.279183 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7823 23:42:36.282365 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7824 23:42:36.289194 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7825 23:42:36.292474 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7826 23:42:36.296136 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7827 23:42:36.302471 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7828 23:42:36.305519 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7829 23:42:36.309010 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7830 23:42:36.315620 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7831 23:42:36.319099 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7832 23:42:36.322102 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7833 23:42:36.328672 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7834 23:42:36.331975 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7835 23:42:36.335626 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7836 23:42:36.342315 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7837 23:42:36.345139 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7838 23:42:36.348685 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7839 23:42:36.355376 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7840 23:42:36.358953 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7841 23:42:36.361833 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7842 23:42:36.368408 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7843 23:42:36.371972 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7844 23:42:36.375037 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7845 23:42:36.381625 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7846 23:42:36.382048 Total UI for P1: 0, mck2ui 16
7847 23:42:36.388422 best dqsien dly found for B0: ( 1, 0, 28)
7848 23:42:36.391924 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7849 23:42:36.395263 Total UI for P1: 0, mck2ui 16
7850 23:42:36.398210 best dqsien dly found for B1: ( 1, 1, 2)
7851 23:42:36.401653 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7852 23:42:36.404820 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7853 23:42:36.405246
7854 23:42:36.408219 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7855 23:42:36.411625 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7856 23:42:36.415076 [Gating] SW calibration Done
7857 23:42:36.415501 ==
7858 23:42:36.418369 Dram Type= 6, Freq= 0, CH_0, rank 1
7859 23:42:36.421600 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7860 23:42:36.422027 ==
7861 23:42:36.425117 RX Vref Scan: 0
7862 23:42:36.425634
7863 23:42:36.428248 RX Vref 0 -> 0, step: 1
7864 23:42:36.428673
7865 23:42:36.429007 RX Delay 0 -> 252, step: 8
7866 23:42:36.435015 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7867 23:42:36.438124 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7868 23:42:36.441679 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7869 23:42:36.444743 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7870 23:42:36.447989 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7871 23:42:36.454763 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7872 23:42:36.458059 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7873 23:42:36.461371 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7874 23:42:36.464670 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7875 23:42:36.467700 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7876 23:42:36.474743 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7877 23:42:36.477924 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7878 23:42:36.480952 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7879 23:42:36.484510 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7880 23:42:36.487739 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7881 23:42:36.494453 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7882 23:42:36.494920 ==
7883 23:42:36.498011 Dram Type= 6, Freq= 0, CH_0, rank 1
7884 23:42:36.501257 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7885 23:42:36.501708 ==
7886 23:42:36.502038 DQS Delay:
7887 23:42:36.504275 DQS0 = 0, DQS1 = 0
7888 23:42:36.504690 DQM Delay:
7889 23:42:36.507820 DQM0 = 131, DQM1 = 124
7890 23:42:36.508342 DQ Delay:
7891 23:42:36.511131 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7892 23:42:36.514404 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =143
7893 23:42:36.517560 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7894 23:42:36.524367 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7895 23:42:36.525023
7896 23:42:36.525566
7897 23:42:36.526010 ==
7898 23:42:36.527407 Dram Type= 6, Freq= 0, CH_0, rank 1
7899 23:42:36.530795 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7900 23:42:36.531283 ==
7901 23:42:36.531756
7902 23:42:36.532202
7903 23:42:36.534124 TX Vref Scan disable
7904 23:42:36.534598 == TX Byte 0 ==
7905 23:42:36.540828 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7906 23:42:36.543970 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7907 23:42:36.544485 == TX Byte 1 ==
7908 23:42:36.550688 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7909 23:42:36.553773 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7910 23:42:36.554239 ==
7911 23:42:36.557712 Dram Type= 6, Freq= 0, CH_0, rank 1
7912 23:42:36.560448 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7913 23:42:36.560921 ==
7914 23:42:36.574506
7915 23:42:36.577755 TX Vref early break, caculate TX vref
7916 23:42:36.580863 TX Vref=16, minBit 1, minWin=22, winSum=370
7917 23:42:36.584352 TX Vref=18, minBit 1, minWin=23, winSum=382
7918 23:42:36.587494 TX Vref=20, minBit 1, minWin=23, winSum=389
7919 23:42:36.590705 TX Vref=22, minBit 1, minWin=24, winSum=396
7920 23:42:36.594231 TX Vref=24, minBit 1, minWin=24, winSum=403
7921 23:42:36.600634 TX Vref=26, minBit 0, minWin=25, winSum=410
7922 23:42:36.604386 TX Vref=28, minBit 1, minWin=25, winSum=418
7923 23:42:36.607784 TX Vref=30, minBit 8, minWin=24, winSum=410
7924 23:42:36.610987 TX Vref=32, minBit 1, minWin=24, winSum=403
7925 23:42:36.614123 TX Vref=34, minBit 8, minWin=23, winSum=393
7926 23:42:36.620742 [TxChooseVref] Worse bit 1, Min win 25, Win sum 418, Final Vref 28
7927 23:42:36.621170
7928 23:42:36.623902 Final TX Range 0 Vref 28
7929 23:42:36.624324
7930 23:42:36.624657 ==
7931 23:42:36.627551 Dram Type= 6, Freq= 0, CH_0, rank 1
7932 23:42:36.630674 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7933 23:42:36.631102 ==
7934 23:42:36.631439
7935 23:42:36.631747
7936 23:42:36.633904 TX Vref Scan disable
7937 23:42:36.640897 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7938 23:42:36.641371 == TX Byte 0 ==
7939 23:42:36.643943 u2DelayCellOfst[0]=10 cells (3 PI)
7940 23:42:36.647060 u2DelayCellOfst[1]=14 cells (4 PI)
7941 23:42:36.650453 u2DelayCellOfst[2]=7 cells (2 PI)
7942 23:42:36.653750 u2DelayCellOfst[3]=10 cells (3 PI)
7943 23:42:36.657160 u2DelayCellOfst[4]=7 cells (2 PI)
7944 23:42:36.660171 u2DelayCellOfst[5]=0 cells (0 PI)
7945 23:42:36.664078 u2DelayCellOfst[6]=14 cells (4 PI)
7946 23:42:36.667059 u2DelayCellOfst[7]=14 cells (4 PI)
7947 23:42:36.670289 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7948 23:42:36.673773 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7949 23:42:36.676990 == TX Byte 1 ==
7950 23:42:36.677525 u2DelayCellOfst[8]=3 cells (1 PI)
7951 23:42:36.680272 u2DelayCellOfst[9]=0 cells (0 PI)
7952 23:42:36.683909 u2DelayCellOfst[10]=14 cells (4 PI)
7953 23:42:36.686860 u2DelayCellOfst[11]=7 cells (2 PI)
7954 23:42:36.690012 u2DelayCellOfst[12]=18 cells (5 PI)
7955 23:42:36.693650 u2DelayCellOfst[13]=18 cells (5 PI)
7956 23:42:36.696993 u2DelayCellOfst[14]=21 cells (6 PI)
7957 23:42:36.700160 u2DelayCellOfst[15]=18 cells (5 PI)
7958 23:42:36.703675 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7959 23:42:36.710323 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7960 23:42:36.710752 DramC Write-DBI on
7961 23:42:36.711176 ==
7962 23:42:36.713641 Dram Type= 6, Freq= 0, CH_0, rank 1
7963 23:42:36.716985 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7964 23:42:36.719960 ==
7965 23:42:36.720404
7966 23:42:36.720739
7967 23:42:36.721041 TX Vref Scan disable
7968 23:42:36.723773 == TX Byte 0 ==
7969 23:42:36.727098 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7970 23:42:36.730437 == TX Byte 1 ==
7971 23:42:36.733618 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7972 23:42:36.737116 DramC Write-DBI off
7973 23:42:36.737617
7974 23:42:36.738011 [DATLAT]
7975 23:42:36.738349 Freq=1600, CH0 RK1
7976 23:42:36.738649
7977 23:42:36.740314 DATLAT Default: 0xe
7978 23:42:36.740744 0, 0xFFFF, sum = 0
7979 23:42:36.743671 1, 0xFFFF, sum = 0
7980 23:42:36.746677 2, 0xFFFF, sum = 0
7981 23:42:36.747108 3, 0xFFFF, sum = 0
7982 23:42:36.750530 4, 0xFFFF, sum = 0
7983 23:42:36.750966 5, 0xFFFF, sum = 0
7984 23:42:36.753439 6, 0xFFFF, sum = 0
7985 23:42:36.753875 7, 0xFFFF, sum = 0
7986 23:42:36.757007 8, 0xFFFF, sum = 0
7987 23:42:36.757608 9, 0xFFFF, sum = 0
7988 23:42:36.760225 10, 0xFFFF, sum = 0
7989 23:42:36.760659 11, 0xFFFF, sum = 0
7990 23:42:36.763338 12, 0xCFFF, sum = 0
7991 23:42:36.763976 13, 0x0, sum = 1
7992 23:42:36.766607 14, 0x0, sum = 2
7993 23:42:36.767039 15, 0x0, sum = 3
7994 23:42:36.770465 16, 0x0, sum = 4
7995 23:42:36.770997 best_step = 14
7996 23:42:36.771432
7997 23:42:36.771845 ==
7998 23:42:36.773479 Dram Type= 6, Freq= 0, CH_0, rank 1
7999 23:42:36.776515 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8000 23:42:36.779882 ==
8001 23:42:36.780310 RX Vref Scan: 0
8002 23:42:36.780788
8003 23:42:36.783209 RX Vref 0 -> 0, step: 1
8004 23:42:36.783635
8005 23:42:36.786552 RX Delay 11 -> 252, step: 4
8006 23:42:36.789894 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
8007 23:42:36.793181 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8008 23:42:36.796348 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
8009 23:42:36.802780 iDelay=195, Bit 3, Center 122 (67 ~ 178) 112
8010 23:42:36.806440 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8011 23:42:36.809426 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8012 23:42:36.812851 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8013 23:42:36.816095 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
8014 23:42:36.822799 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
8015 23:42:36.826547 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8016 23:42:36.829358 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8017 23:42:36.832837 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
8018 23:42:36.839428 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
8019 23:42:36.842714 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8020 23:42:36.846453 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8021 23:42:36.849105 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8022 23:42:36.849633 ==
8023 23:42:36.852874 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 23:42:36.859704 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8025 23:42:36.860239 ==
8026 23:42:36.860681 DQS Delay:
8027 23:42:36.861086 DQS0 = 0, DQS1 = 0
8028 23:42:36.862205 DQM Delay:
8029 23:42:36.862631 DQM0 = 128, DQM1 = 121
8030 23:42:36.865873 DQ Delay:
8031 23:42:36.868838 DQ0 =124, DQ1 =130, DQ2 =126, DQ3 =122
8032 23:42:36.872423 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =138
8033 23:42:36.875774 DQ8 =110, DQ9 =108, DQ10 =122, DQ11 =112
8034 23:42:36.879040 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =132
8035 23:42:36.879469
8036 23:42:36.879895
8037 23:42:36.880297
8038 23:42:36.882357 [DramC_TX_OE_Calibration] TA2
8039 23:42:36.885582 Original DQ_B0 (3 6) =30, OEN = 27
8040 23:42:36.888639 Original DQ_B1 (3 6) =30, OEN = 27
8041 23:42:36.892424 24, 0x0, End_B0=24 End_B1=24
8042 23:42:36.893021 25, 0x0, End_B0=25 End_B1=25
8043 23:42:36.895324 26, 0x0, End_B0=26 End_B1=26
8044 23:42:36.898988 27, 0x0, End_B0=27 End_B1=27
8045 23:42:36.902313 28, 0x0, End_B0=28 End_B1=28
8046 23:42:36.905163 29, 0x0, End_B0=29 End_B1=29
8047 23:42:36.905730 30, 0x0, End_B0=30 End_B1=30
8048 23:42:36.908566 31, 0x4141, End_B0=30 End_B1=30
8049 23:42:36.911974 Byte0 end_step=30 best_step=27
8050 23:42:36.915252 Byte1 end_step=30 best_step=27
8051 23:42:36.918621 Byte0 TX OE(2T, 0.5T) = (3, 3)
8052 23:42:36.921732 Byte1 TX OE(2T, 0.5T) = (3, 3)
8053 23:42:36.922167
8054 23:42:36.922585
8055 23:42:36.928268 [DQSOSCAuto] RK1, (LSB)MR18= 0x2424, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8056 23:42:36.931651 CH0 RK1: MR19=303, MR18=2424
8057 23:42:36.938566 CH0_RK1: MR19=0x303, MR18=0x2424, DQSOSC=391, MR23=63, INC=24, DEC=16
8058 23:42:36.941696 [RxdqsGatingPostProcess] freq 1600
8059 23:42:36.944982 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8060 23:42:36.948639 Pre-setting of DQS Precalculation
8061 23:42:36.955374 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8062 23:42:36.955970 ==
8063 23:42:36.958395 Dram Type= 6, Freq= 0, CH_1, rank 0
8064 23:42:36.961497 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8065 23:42:36.961926 ==
8066 23:42:36.968021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8067 23:42:36.971347 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8068 23:42:36.974781 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8069 23:42:36.981588 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8070 23:42:36.989841 [CA 0] Center 41 (11~71) winsize 61
8071 23:42:36.992940 [CA 1] Center 40 (10~71) winsize 62
8072 23:42:36.996107 [CA 2] Center 36 (6~66) winsize 61
8073 23:42:36.999766 [CA 3] Center 35 (6~65) winsize 60
8074 23:42:37.002856 [CA 4] Center 33 (4~63) winsize 60
8075 23:42:37.006347 [CA 5] Center 33 (4~63) winsize 60
8076 23:42:37.006765
8077 23:42:37.009461 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8078 23:42:37.009879
8079 23:42:37.013015 [CATrainingPosCal] consider 1 rank data
8080 23:42:37.016146 u2DelayCellTimex100 = 271/100 ps
8081 23:42:37.022843 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8082 23:42:37.025913 CA1 delay=40 (10~71),Diff = 7 PI (25 cell)
8083 23:42:37.029620 CA2 delay=36 (6~66),Diff = 3 PI (10 cell)
8084 23:42:37.032684 CA3 delay=35 (6~65),Diff = 2 PI (7 cell)
8085 23:42:37.036024 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
8086 23:42:37.039572 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8087 23:42:37.039990
8088 23:42:37.042816 CA PerBit enable=1, Macro0, CA PI delay=33
8089 23:42:37.043236
8090 23:42:37.046105 [CBTSetCACLKResult] CA Dly = 33
8091 23:42:37.049547 CS Dly: 9 (0~40)
8092 23:42:37.052729 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8093 23:42:37.056129 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8094 23:42:37.056541 ==
8095 23:42:37.059460 Dram Type= 6, Freq= 0, CH_1, rank 1
8096 23:42:37.062893 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8097 23:42:37.066373 ==
8098 23:42:37.069220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8099 23:42:37.072607 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8100 23:42:37.079219 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8101 23:42:37.082911 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8102 23:42:37.092303 [CA 0] Center 41 (11~71) winsize 61
8103 23:42:37.095764 [CA 1] Center 41 (11~71) winsize 61
8104 23:42:37.098705 [CA 2] Center 36 (7~66) winsize 60
8105 23:42:37.102063 [CA 3] Center 36 (7~65) winsize 59
8106 23:42:37.105368 [CA 4] Center 34 (5~64) winsize 60
8107 23:42:37.108822 [CA 5] Center 34 (4~64) winsize 61
8108 23:42:37.109236
8109 23:42:37.112115 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8110 23:42:37.112527
8111 23:42:37.115539 [CATrainingPosCal] consider 2 rank data
8112 23:42:37.118979 u2DelayCellTimex100 = 271/100 ps
8113 23:42:37.122113 CA0 delay=41 (11~71),Diff = 8 PI (28 cell)
8114 23:42:37.129040 CA1 delay=41 (11~71),Diff = 8 PI (28 cell)
8115 23:42:37.132007 CA2 delay=36 (7~66),Diff = 3 PI (10 cell)
8116 23:42:37.135402 CA3 delay=36 (7~65),Diff = 3 PI (10 cell)
8117 23:42:37.138802 CA4 delay=34 (5~63),Diff = 1 PI (3 cell)
8118 23:42:37.142136 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
8119 23:42:37.142582
8120 23:42:37.145481 CA PerBit enable=1, Macro0, CA PI delay=33
8121 23:42:37.145922
8122 23:42:37.148886 [CBTSetCACLKResult] CA Dly = 33
8123 23:42:37.151951 CS Dly: 9 (0~40)
8124 23:42:37.155392 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8125 23:42:37.158659 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8126 23:42:37.159075
8127 23:42:37.162085 ----->DramcWriteLeveling(PI) begin...
8128 23:42:37.162550 ==
8129 23:42:37.165244 Dram Type= 6, Freq= 0, CH_1, rank 0
8130 23:42:37.172130 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8131 23:42:37.172580 ==
8132 23:42:37.175009 Write leveling (Byte 0): 22 => 22
8133 23:42:37.175386 Write leveling (Byte 1): 22 => 22
8134 23:42:37.178789 DramcWriteLeveling(PI) end<-----
8135 23:42:37.179237
8136 23:42:37.179563 ==
8137 23:42:37.181568 Dram Type= 6, Freq= 0, CH_1, rank 0
8138 23:42:37.188383 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8139 23:42:37.188862 ==
8140 23:42:37.191650 [Gating] SW mode calibration
8141 23:42:37.198459 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8142 23:42:37.201591 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8143 23:42:37.208578 0 12 0 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
8144 23:42:37.211461 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8145 23:42:37.215055 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8146 23:42:37.221434 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8147 23:42:37.224667 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8148 23:42:37.227937 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8149 23:42:37.234676 0 12 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
8150 23:42:37.238009 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8151 23:42:37.241383 0 13 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
8152 23:42:37.247655 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8153 23:42:37.251296 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8154 23:42:37.254576 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8155 23:42:37.261208 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8156 23:42:37.264426 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8157 23:42:37.267608 0 13 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8158 23:42:37.274495 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8159 23:42:37.277801 0 14 0 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
8160 23:42:37.281125 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8161 23:42:37.287586 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8162 23:42:37.291269 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8163 23:42:37.294114 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8164 23:42:37.297551 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8165 23:42:37.304245 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8166 23:42:37.308080 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8167 23:42:37.314093 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8168 23:42:37.317104 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8169 23:42:37.320854 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8170 23:42:37.323991 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8171 23:42:37.330788 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8172 23:42:37.334244 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8173 23:42:37.337488 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8174 23:42:37.344460 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8175 23:42:37.347965 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8176 23:42:37.351117 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8177 23:42:37.357527 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8178 23:42:37.361043 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8179 23:42:37.364721 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8180 23:42:37.371307 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8181 23:42:37.374459 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8182 23:42:37.377797 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8183 23:42:37.384272 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8184 23:42:37.384734 Total UI for P1: 0, mck2ui 16
8185 23:42:37.390861 best dqsien dly found for B0: ( 1, 0, 26)
8186 23:42:37.394310 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8187 23:42:37.397442 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8188 23:42:37.400984 Total UI for P1: 0, mck2ui 16
8189 23:42:37.404412 best dqsien dly found for B1: ( 1, 1, 2)
8190 23:42:37.407264 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8191 23:42:37.410466 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8192 23:42:37.410882
8193 23:42:37.413722 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8194 23:42:37.420700 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8195 23:42:37.421114 [Gating] SW calibration Done
8196 23:42:37.421547 ==
8197 23:42:37.424048 Dram Type= 6, Freq= 0, CH_1, rank 0
8198 23:42:37.430733 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8199 23:42:37.431174 ==
8200 23:42:37.431503 RX Vref Scan: 0
8201 23:42:37.431831
8202 23:42:37.434007 RX Vref 0 -> 0, step: 1
8203 23:42:37.434444
8204 23:42:37.437815 RX Delay 0 -> 252, step: 8
8205 23:42:37.440768 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8206 23:42:37.443674 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8207 23:42:37.447372 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8208 23:42:37.453930 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8209 23:42:37.456835 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8210 23:42:37.460112 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8211 23:42:37.463242 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
8212 23:42:37.467040 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8213 23:42:37.473523 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8214 23:42:37.476651 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8215 23:42:37.480533 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8216 23:42:37.483474 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8217 23:42:37.486950 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8218 23:42:37.493662 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8219 23:42:37.496638 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8220 23:42:37.499948 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8221 23:42:37.500505 ==
8222 23:42:37.503150 Dram Type= 6, Freq= 0, CH_1, rank 0
8223 23:42:37.506346 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8224 23:42:37.509594 ==
8225 23:42:37.510006 DQS Delay:
8226 23:42:37.510364 DQS0 = 0, DQS1 = 0
8227 23:42:37.513245 DQM Delay:
8228 23:42:37.513695 DQM0 = 129, DQM1 = 125
8229 23:42:37.516395 DQ Delay:
8230 23:42:37.519608 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8231 23:42:37.522856 DQ4 =131, DQ5 =139, DQ6 =135, DQ7 =127
8232 23:42:37.526020 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8233 23:42:37.529490 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8234 23:42:37.529994
8235 23:42:37.530331
8236 23:42:37.530636 ==
8237 23:42:37.532516 Dram Type= 6, Freq= 0, CH_1, rank 0
8238 23:42:37.535947 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8239 23:42:37.536366 ==
8240 23:42:37.539456
8241 23:42:37.540001
8242 23:42:37.540347 TX Vref Scan disable
8243 23:42:37.543058 == TX Byte 0 ==
8244 23:42:37.545971 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8245 23:42:37.549250 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8246 23:42:37.552887 == TX Byte 1 ==
8247 23:42:37.555984 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8248 23:42:37.559531 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8249 23:42:37.559951 ==
8250 23:42:37.562728 Dram Type= 6, Freq= 0, CH_1, rank 0
8251 23:42:37.569661 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8252 23:42:37.570083 ==
8253 23:42:37.581899
8254 23:42:37.585083 TX Vref early break, caculate TX vref
8255 23:42:37.588441 TX Vref=16, minBit 3, minWin=21, winSum=370
8256 23:42:37.591634 TX Vref=18, minBit 3, minWin=22, winSum=373
8257 23:42:37.594829 TX Vref=20, minBit 0, minWin=23, winSum=385
8258 23:42:37.598218 TX Vref=22, minBit 3, minWin=23, winSum=392
8259 23:42:37.601398 TX Vref=24, minBit 3, minWin=23, winSum=403
8260 23:42:37.608222 TX Vref=26, minBit 1, minWin=24, winSum=406
8261 23:42:37.611503 TX Vref=28, minBit 3, minWin=24, winSum=407
8262 23:42:37.614786 TX Vref=30, minBit 1, minWin=24, winSum=405
8263 23:42:37.618052 TX Vref=32, minBit 1, minWin=23, winSum=391
8264 23:42:37.621789 TX Vref=34, minBit 3, minWin=22, winSum=387
8265 23:42:37.624589 TX Vref=36, minBit 0, minWin=22, winSum=376
8266 23:42:37.631718 [TxChooseVref] Worse bit 3, Min win 24, Win sum 407, Final Vref 28
8267 23:42:37.632251
8268 23:42:37.634834 Final TX Range 0 Vref 28
8269 23:42:37.635317
8270 23:42:37.635691 ==
8271 23:42:37.637990 Dram Type= 6, Freq= 0, CH_1, rank 0
8272 23:42:37.641433 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8273 23:42:37.641897 ==
8274 23:42:37.642260
8275 23:42:37.642615
8276 23:42:37.644695 TX Vref Scan disable
8277 23:42:37.651244 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8278 23:42:37.651749 == TX Byte 0 ==
8279 23:42:37.654427 u2DelayCellOfst[0]=14 cells (4 PI)
8280 23:42:37.657782 u2DelayCellOfst[1]=10 cells (3 PI)
8281 23:42:37.661632 u2DelayCellOfst[2]=0 cells (0 PI)
8282 23:42:37.664365 u2DelayCellOfst[3]=7 cells (2 PI)
8283 23:42:37.668045 u2DelayCellOfst[4]=7 cells (2 PI)
8284 23:42:37.671094 u2DelayCellOfst[5]=14 cells (4 PI)
8285 23:42:37.674369 u2DelayCellOfst[6]=14 cells (4 PI)
8286 23:42:37.678137 u2DelayCellOfst[7]=3 cells (1 PI)
8287 23:42:37.681237 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8288 23:42:37.684590 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8289 23:42:37.687950 == TX Byte 1 ==
8290 23:42:37.691272 u2DelayCellOfst[8]=0 cells (0 PI)
8291 23:42:37.691834 u2DelayCellOfst[9]=7 cells (2 PI)
8292 23:42:37.694249 u2DelayCellOfst[10]=10 cells (3 PI)
8293 23:42:37.697910 u2DelayCellOfst[11]=3 cells (1 PI)
8294 23:42:37.700817 u2DelayCellOfst[12]=18 cells (5 PI)
8295 23:42:37.704310 u2DelayCellOfst[13]=21 cells (6 PI)
8296 23:42:37.707467 u2DelayCellOfst[14]=21 cells (6 PI)
8297 23:42:37.711263 u2DelayCellOfst[15]=21 cells (6 PI)
8298 23:42:37.714247 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8299 23:42:37.720874 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8300 23:42:37.721377 DramC Write-DBI on
8301 23:42:37.721793 ==
8302 23:42:37.724010 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 23:42:37.730448 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8304 23:42:37.730966 ==
8305 23:42:37.731334
8306 23:42:37.731692
8307 23:42:37.732031 TX Vref Scan disable
8308 23:42:37.734350 == TX Byte 0 ==
8309 23:42:37.737696 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8310 23:42:37.741055 == TX Byte 1 ==
8311 23:42:37.744506 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8312 23:42:37.747507 DramC Write-DBI off
8313 23:42:37.747998
8314 23:42:37.748364 [DATLAT]
8315 23:42:37.748730 Freq=1600, CH1 RK0
8316 23:42:37.749102
8317 23:42:37.751209 DATLAT Default: 0xf
8318 23:42:37.751669 0, 0xFFFF, sum = 0
8319 23:42:37.754202 1, 0xFFFF, sum = 0
8320 23:42:37.757320 2, 0xFFFF, sum = 0
8321 23:42:37.757826 3, 0xFFFF, sum = 0
8322 23:42:37.760543 4, 0xFFFF, sum = 0
8323 23:42:37.761019 5, 0xFFFF, sum = 0
8324 23:42:37.764389 6, 0xFFFF, sum = 0
8325 23:42:37.764866 7, 0xFFFF, sum = 0
8326 23:42:37.767294 8, 0xFFFF, sum = 0
8327 23:42:37.767736 9, 0xFFFF, sum = 0
8328 23:42:37.770755 10, 0xFFFF, sum = 0
8329 23:42:37.771180 11, 0xFFFF, sum = 0
8330 23:42:37.773933 12, 0xF7F, sum = 0
8331 23:42:37.774358 13, 0x0, sum = 1
8332 23:42:37.777751 14, 0x0, sum = 2
8333 23:42:37.778177 15, 0x0, sum = 3
8334 23:42:37.780798 16, 0x0, sum = 4
8335 23:42:37.781223 best_step = 14
8336 23:42:37.781605
8337 23:42:37.781915 ==
8338 23:42:37.784473 Dram Type= 6, Freq= 0, CH_1, rank 0
8339 23:42:37.787259 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8340 23:42:37.790467 ==
8341 23:42:37.790900 RX Vref Scan: 1
8342 23:42:37.791237
8343 23:42:37.793784 Set Vref Range= 24 -> 127
8344 23:42:37.794482
8345 23:42:37.797344 RX Vref 24 -> 127, step: 1
8346 23:42:37.797904
8347 23:42:37.798334 RX Delay 3 -> 252, step: 4
8348 23:42:37.798657
8349 23:42:37.800416 Set Vref, RX VrefLevel [Byte0]: 24
8350 23:42:37.803762 [Byte1]: 24
8351 23:42:37.807867
8352 23:42:37.808566 Set Vref, RX VrefLevel [Byte0]: 25
8353 23:42:37.811413 [Byte1]: 25
8354 23:42:37.815478
8355 23:42:37.816161 Set Vref, RX VrefLevel [Byte0]: 26
8356 23:42:37.818439 [Byte1]: 26
8357 23:42:37.823136
8358 23:42:37.823661 Set Vref, RX VrefLevel [Byte0]: 27
8359 23:42:37.826333 [Byte1]: 27
8360 23:42:37.830663
8361 23:42:37.831168 Set Vref, RX VrefLevel [Byte0]: 28
8362 23:42:37.833670 [Byte1]: 28
8363 23:42:37.838165
8364 23:42:37.838715 Set Vref, RX VrefLevel [Byte0]: 29
8365 23:42:37.841564 [Byte1]: 29
8366 23:42:37.845858
8367 23:42:37.846324 Set Vref, RX VrefLevel [Byte0]: 30
8368 23:42:37.848958 [Byte1]: 30
8369 23:42:37.853619
8370 23:42:37.854107 Set Vref, RX VrefLevel [Byte0]: 31
8371 23:42:37.856721 [Byte1]: 31
8372 23:42:37.861111
8373 23:42:37.861863 Set Vref, RX VrefLevel [Byte0]: 32
8374 23:42:37.864634 [Byte1]: 32
8375 23:42:37.869078
8376 23:42:37.869732 Set Vref, RX VrefLevel [Byte0]: 33
8377 23:42:37.871965 [Byte1]: 33
8378 23:42:37.876597
8379 23:42:37.877011 Set Vref, RX VrefLevel [Byte0]: 34
8380 23:42:37.879990 [Byte1]: 34
8381 23:42:37.884258
8382 23:42:37.884837 Set Vref, RX VrefLevel [Byte0]: 35
8383 23:42:37.887523 [Byte1]: 35
8384 23:42:37.891952
8385 23:42:37.892521 Set Vref, RX VrefLevel [Byte0]: 36
8386 23:42:37.895598 [Byte1]: 36
8387 23:42:37.899651
8388 23:42:37.900222 Set Vref, RX VrefLevel [Byte0]: 37
8389 23:42:37.902746 [Byte1]: 37
8390 23:42:37.907343
8391 23:42:37.907797 Set Vref, RX VrefLevel [Byte0]: 38
8392 23:42:37.910776 [Byte1]: 38
8393 23:42:37.915135
8394 23:42:37.915704 Set Vref, RX VrefLevel [Byte0]: 39
8395 23:42:37.918212 [Byte1]: 39
8396 23:42:37.922590
8397 23:42:37.923153 Set Vref, RX VrefLevel [Byte0]: 40
8398 23:42:37.925945 [Byte1]: 40
8399 23:42:37.929949
8400 23:42:37.930404 Set Vref, RX VrefLevel [Byte0]: 41
8401 23:42:37.933424 [Byte1]: 41
8402 23:42:37.937843
8403 23:42:37.938403 Set Vref, RX VrefLevel [Byte0]: 42
8404 23:42:37.940976 [Byte1]: 42
8405 23:42:37.945710
8406 23:42:37.946267 Set Vref, RX VrefLevel [Byte0]: 43
8407 23:42:37.949042 [Byte1]: 43
8408 23:42:37.953110
8409 23:42:37.953709 Set Vref, RX VrefLevel [Byte0]: 44
8410 23:42:37.956303 [Byte1]: 44
8411 23:42:37.960603
8412 23:42:37.961060 Set Vref, RX VrefLevel [Byte0]: 45
8413 23:42:37.964747 [Byte1]: 45
8414 23:42:37.968502
8415 23:42:37.969059 Set Vref, RX VrefLevel [Byte0]: 46
8416 23:42:37.971531 [Byte1]: 46
8417 23:42:37.976052
8418 23:42:37.976608 Set Vref, RX VrefLevel [Byte0]: 47
8419 23:42:37.979620 [Byte1]: 47
8420 23:42:37.983861
8421 23:42:37.984426 Set Vref, RX VrefLevel [Byte0]: 48
8422 23:42:37.987188 [Byte1]: 48
8423 23:42:37.991664
8424 23:42:37.992224 Set Vref, RX VrefLevel [Byte0]: 49
8425 23:42:37.994892 [Byte1]: 49
8426 23:42:37.999338
8427 23:42:37.999909 Set Vref, RX VrefLevel [Byte0]: 50
8428 23:42:38.002895 [Byte1]: 50
8429 23:42:38.007080
8430 23:42:38.007625 Set Vref, RX VrefLevel [Byte0]: 51
8431 23:42:38.010141 [Byte1]: 51
8432 23:42:38.014167
8433 23:42:38.014653 Set Vref, RX VrefLevel [Byte0]: 52
8434 23:42:38.017741 [Byte1]: 52
8435 23:42:38.021742
8436 23:42:38.022215 Set Vref, RX VrefLevel [Byte0]: 53
8437 23:42:38.025251 [Byte1]: 53
8438 23:42:38.029565
8439 23:42:38.030026 Set Vref, RX VrefLevel [Byte0]: 54
8440 23:42:38.032611 [Byte1]: 54
8441 23:42:38.037102
8442 23:42:38.037694 Set Vref, RX VrefLevel [Byte0]: 55
8443 23:42:38.040633 [Byte1]: 55
8444 23:42:38.045261
8445 23:42:38.045865 Set Vref, RX VrefLevel [Byte0]: 56
8446 23:42:38.048429 [Byte1]: 56
8447 23:42:38.052812
8448 23:42:38.053277 Set Vref, RX VrefLevel [Byte0]: 57
8449 23:42:38.055934 [Byte1]: 57
8450 23:42:38.060265
8451 23:42:38.060797 Set Vref, RX VrefLevel [Byte0]: 58
8452 23:42:38.063630 [Byte1]: 58
8453 23:42:38.067924
8454 23:42:38.068497 Set Vref, RX VrefLevel [Byte0]: 59
8455 23:42:38.071241 [Byte1]: 59
8456 23:42:38.076143
8457 23:42:38.076727 Set Vref, RX VrefLevel [Byte0]: 60
8458 23:42:38.079177 [Byte1]: 60
8459 23:42:38.083312
8460 23:42:38.083889 Set Vref, RX VrefLevel [Byte0]: 61
8461 23:42:38.086366 [Byte1]: 61
8462 23:42:38.090673
8463 23:42:38.091244 Set Vref, RX VrefLevel [Byte0]: 62
8464 23:42:38.093893 [Byte1]: 62
8465 23:42:38.099092
8466 23:42:38.099733 Set Vref, RX VrefLevel [Byte0]: 63
8467 23:42:38.101902 [Byte1]: 63
8468 23:42:38.106088
8469 23:42:38.106568 Set Vref, RX VrefLevel [Byte0]: 64
8470 23:42:38.109512 [Byte1]: 64
8471 23:42:38.113971
8472 23:42:38.114553 Set Vref, RX VrefLevel [Byte0]: 65
8473 23:42:38.117168 [Byte1]: 65
8474 23:42:38.121454
8475 23:42:38.122054 Set Vref, RX VrefLevel [Byte0]: 66
8476 23:42:38.125167 [Byte1]: 66
8477 23:42:38.129214
8478 23:42:38.129736 Set Vref, RX VrefLevel [Byte0]: 67
8479 23:42:38.132346 [Byte1]: 67
8480 23:42:38.137262
8481 23:42:38.137864 Set Vref, RX VrefLevel [Byte0]: 68
8482 23:42:38.140082 [Byte1]: 68
8483 23:42:38.144538
8484 23:42:38.145118 Set Vref, RX VrefLevel [Byte0]: 69
8485 23:42:38.147628 [Byte1]: 69
8486 23:42:38.152251
8487 23:42:38.152837 Set Vref, RX VrefLevel [Byte0]: 70
8488 23:42:38.155171 [Byte1]: 70
8489 23:42:38.159698
8490 23:42:38.160241 Set Vref, RX VrefLevel [Byte0]: 71
8491 23:42:38.163189 [Byte1]: 71
8492 23:42:38.167498
8493 23:42:38.168119 Set Vref, RX VrefLevel [Byte0]: 72
8494 23:42:38.170705 [Byte1]: 72
8495 23:42:38.175172
8496 23:42:38.175646 Set Vref, RX VrefLevel [Byte0]: 73
8497 23:42:38.178442 [Byte1]: 73
8498 23:42:38.182835
8499 23:42:38.183331 Set Vref, RX VrefLevel [Byte0]: 74
8500 23:42:38.185968 [Byte1]: 74
8501 23:42:38.190307
8502 23:42:38.190782 Final RX Vref Byte 0 = 62 to rank0
8503 23:42:38.193466 Final RX Vref Byte 1 = 56 to rank0
8504 23:42:38.196771 Final RX Vref Byte 0 = 62 to rank1
8505 23:42:38.200423 Final RX Vref Byte 1 = 56 to rank1==
8506 23:42:38.203380 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 23:42:38.209962 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8508 23:42:38.210509 ==
8509 23:42:38.210985 DQS Delay:
8510 23:42:38.213527 DQS0 = 0, DQS1 = 0
8511 23:42:38.214117 DQM Delay:
8512 23:42:38.214606 DQM0 = 128, DQM1 = 123
8513 23:42:38.216785 DQ Delay:
8514 23:42:38.220047 DQ0 =130, DQ1 =122, DQ2 =118, DQ3 =126
8515 23:42:38.223670 DQ4 =128, DQ5 =140, DQ6 =136, DQ7 =124
8516 23:42:38.226979 DQ8 =106, DQ9 =112, DQ10 =126, DQ11 =110
8517 23:42:38.230023 DQ12 =132, DQ13 =134, DQ14 =134, DQ15 =132
8518 23:42:38.230500
8519 23:42:38.231074
8520 23:42:38.231521
8521 23:42:38.233366 [DramC_TX_OE_Calibration] TA2
8522 23:42:38.236585 Original DQ_B0 (3 6) =30, OEN = 27
8523 23:42:38.240263 Original DQ_B1 (3 6) =30, OEN = 27
8524 23:42:38.243217 24, 0x0, End_B0=24 End_B1=24
8525 23:42:38.243707 25, 0x0, End_B0=25 End_B1=25
8526 23:42:38.246798 26, 0x0, End_B0=26 End_B1=26
8527 23:42:38.249886 27, 0x0, End_B0=27 End_B1=27
8528 23:42:38.252986 28, 0x0, End_B0=28 End_B1=28
8529 23:42:38.256345 29, 0x0, End_B0=29 End_B1=29
8530 23:42:38.256987 30, 0x0, End_B0=30 End_B1=30
8531 23:42:38.259689 31, 0x4141, End_B0=30 End_B1=30
8532 23:42:38.263281 Byte0 end_step=30 best_step=27
8533 23:42:38.266709 Byte1 end_step=30 best_step=27
8534 23:42:38.269599 Byte0 TX OE(2T, 0.5T) = (3, 3)
8535 23:42:38.272904 Byte1 TX OE(2T, 0.5T) = (3, 3)
8536 23:42:38.273400
8537 23:42:38.273775
8538 23:42:38.279737 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
8539 23:42:38.282801 CH1 RK0: MR19=303, MR18=2525
8540 23:42:38.289424 CH1_RK0: MR19=0x303, MR18=0x2525, DQSOSC=391, MR23=63, INC=24, DEC=16
8541 23:42:38.289979
8542 23:42:38.292747 ----->DramcWriteLeveling(PI) begin...
8543 23:42:38.293219 ==
8544 23:42:38.296217 Dram Type= 6, Freq= 0, CH_1, rank 1
8545 23:42:38.299528 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8546 23:42:38.300071 ==
8547 23:42:38.302839 Write leveling (Byte 0): 21 => 21
8548 23:42:38.305916 Write leveling (Byte 1): 19 => 19
8549 23:42:38.309527 DramcWriteLeveling(PI) end<-----
8550 23:42:38.310005
8551 23:42:38.310476 ==
8552 23:42:38.312570 Dram Type= 6, Freq= 0, CH_1, rank 1
8553 23:42:38.316306 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8554 23:42:38.316891 ==
8555 23:42:38.319599 [Gating] SW mode calibration
8556 23:42:38.326255 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8557 23:42:38.332852 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8558 23:42:38.336170 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8559 23:42:38.342907 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8560 23:42:38.346098 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8561 23:42:38.349768 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8562 23:42:38.355730 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8563 23:42:38.359597 0 12 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8564 23:42:38.362456 0 12 24 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8565 23:42:38.369623 0 12 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (1 0)
8566 23:42:38.372668 0 13 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8567 23:42:38.375865 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8568 23:42:38.382501 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8569 23:42:38.385717 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8570 23:42:38.389200 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8571 23:42:38.395716 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8572 23:42:38.399022 0 13 24 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
8573 23:42:38.402194 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8574 23:42:38.405765 0 14 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8575 23:42:38.411958 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8576 23:42:38.415407 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8577 23:42:38.418901 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8578 23:42:38.425103 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8579 23:42:38.428456 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8580 23:42:38.431920 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8581 23:42:38.438716 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8582 23:42:38.441963 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8583 23:42:38.445159 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8584 23:42:38.451611 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8585 23:42:38.455280 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8586 23:42:38.458298 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8587 23:42:38.464979 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8588 23:42:38.468375 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8589 23:42:38.471994 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8590 23:42:38.478865 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8591 23:42:38.481804 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8592 23:42:38.484920 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8593 23:42:38.492014 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8594 23:42:38.494995 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8595 23:42:38.498270 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8596 23:42:38.505459 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8597 23:42:38.508153 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8598 23:42:38.511873 Total UI for P1: 0, mck2ui 16
8599 23:42:38.514806 best dqsien dly found for B0: ( 1, 0, 24)
8600 23:42:38.518256 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8601 23:42:38.521168 Total UI for P1: 0, mck2ui 16
8602 23:42:38.524545 best dqsien dly found for B1: ( 1, 0, 28)
8603 23:42:38.527875 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8604 23:42:38.531137 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8605 23:42:38.531597
8606 23:42:38.538031 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8607 23:42:38.541319 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8608 23:42:38.541792 [Gating] SW calibration Done
8609 23:42:38.544791 ==
8610 23:42:38.548184 Dram Type= 6, Freq= 0, CH_1, rank 1
8611 23:42:38.551549 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8612 23:42:38.552107 ==
8613 23:42:38.552553 RX Vref Scan: 0
8614 23:42:38.552917
8615 23:42:38.554461 RX Vref 0 -> 0, step: 1
8616 23:42:38.554920
8617 23:42:38.557749 RX Delay 0 -> 252, step: 8
8618 23:42:38.561012 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8619 23:42:38.564658 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8620 23:42:38.567923 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8621 23:42:38.574545 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8622 23:42:38.577675 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8623 23:42:38.580916 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8624 23:42:38.584376 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8625 23:42:38.587766 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8626 23:42:38.594460 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8627 23:42:38.597634 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8628 23:42:38.600772 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8629 23:42:38.604594 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8630 23:42:38.611024 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8631 23:42:38.614089 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8632 23:42:38.617737 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8633 23:42:38.620627 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8634 23:42:38.621096 ==
8635 23:42:38.624080 Dram Type= 6, Freq= 0, CH_1, rank 1
8636 23:42:38.630384 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8637 23:42:38.630944 ==
8638 23:42:38.631321 DQS Delay:
8639 23:42:38.631662 DQS0 = 0, DQS1 = 0
8640 23:42:38.634157 DQM Delay:
8641 23:42:38.634724 DQM0 = 130, DQM1 = 124
8642 23:42:38.637189 DQ Delay:
8643 23:42:38.640913 DQ0 =131, DQ1 =123, DQ2 =119, DQ3 =131
8644 23:42:38.643790 DQ4 =127, DQ5 =143, DQ6 =139, DQ7 =127
8645 23:42:38.647736 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8646 23:42:38.650595 DQ12 =135, DQ13 =139, DQ14 =131, DQ15 =131
8647 23:42:38.651183
8648 23:42:38.651557
8649 23:42:38.651896 ==
8650 23:42:38.653976 Dram Type= 6, Freq= 0, CH_1, rank 1
8651 23:42:38.657205 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8652 23:42:38.660758 ==
8653 23:42:38.661236
8654 23:42:38.661665
8655 23:42:38.662008 TX Vref Scan disable
8656 23:42:38.663480 == TX Byte 0 ==
8657 23:42:38.667016 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8658 23:42:38.670056 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8659 23:42:38.673460 == TX Byte 1 ==
8660 23:42:38.676997 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8661 23:42:38.680174 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8662 23:42:38.680642 ==
8663 23:42:38.684053 Dram Type= 6, Freq= 0, CH_1, rank 1
8664 23:42:38.689991 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8665 23:42:38.690458 ==
8666 23:42:38.702746
8667 23:42:38.706126 TX Vref early break, caculate TX vref
8668 23:42:38.709251 TX Vref=16, minBit 1, minWin=22, winSum=381
8669 23:42:38.712544 TX Vref=18, minBit 1, minWin=23, winSum=390
8670 23:42:38.716262 TX Vref=20, minBit 2, minWin=23, winSum=398
8671 23:42:38.719269 TX Vref=22, minBit 2, minWin=23, winSum=404
8672 23:42:38.722667 TX Vref=24, minBit 0, minWin=24, winSum=416
8673 23:42:38.729366 TX Vref=26, minBit 6, minWin=25, winSum=424
8674 23:42:38.732788 TX Vref=28, minBit 0, minWin=26, winSum=424
8675 23:42:38.736044 TX Vref=30, minBit 0, minWin=25, winSum=418
8676 23:42:38.739206 TX Vref=32, minBit 0, minWin=25, winSum=413
8677 23:42:38.742466 TX Vref=34, minBit 0, minWin=24, winSum=405
8678 23:42:38.745921 TX Vref=36, minBit 0, minWin=23, winSum=395
8679 23:42:38.752790 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8680 23:42:38.753264
8681 23:42:38.756018 Final TX Range 0 Vref 28
8682 23:42:38.756457
8683 23:42:38.756794 ==
8684 23:42:38.759681 Dram Type= 6, Freq= 0, CH_1, rank 1
8685 23:42:38.762652 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8686 23:42:38.763078 ==
8687 23:42:38.763412
8688 23:42:38.765948
8689 23:42:38.766372 TX Vref Scan disable
8690 23:42:38.772592 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8691 23:42:38.773181 == TX Byte 0 ==
8692 23:42:38.776053 u2DelayCellOfst[0]=18 cells (5 PI)
8693 23:42:38.779543 u2DelayCellOfst[1]=10 cells (3 PI)
8694 23:42:38.782273 u2DelayCellOfst[2]=0 cells (0 PI)
8695 23:42:38.785826 u2DelayCellOfst[3]=7 cells (2 PI)
8696 23:42:38.789168 u2DelayCellOfst[4]=7 cells (2 PI)
8697 23:42:38.792552 u2DelayCellOfst[5]=14 cells (4 PI)
8698 23:42:38.795732 u2DelayCellOfst[6]=14 cells (4 PI)
8699 23:42:38.799198 u2DelayCellOfst[7]=7 cells (2 PI)
8700 23:42:38.802705 Update DQ dly =973 (3 ,6, 13) DQ OEN =(3 ,3)
8701 23:42:38.805624 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8702 23:42:38.809061 == TX Byte 1 ==
8703 23:42:38.812137 u2DelayCellOfst[8]=0 cells (0 PI)
8704 23:42:38.815287 u2DelayCellOfst[9]=7 cells (2 PI)
8705 23:42:38.815760 u2DelayCellOfst[10]=7 cells (2 PI)
8706 23:42:38.818861 u2DelayCellOfst[11]=7 cells (2 PI)
8707 23:42:38.822091 u2DelayCellOfst[12]=14 cells (4 PI)
8708 23:42:38.825476 u2DelayCellOfst[13]=18 cells (5 PI)
8709 23:42:38.828438 u2DelayCellOfst[14]=18 cells (5 PI)
8710 23:42:38.831874 u2DelayCellOfst[15]=14 cells (4 PI)
8711 23:42:38.838450 Update DQ dly =971 (3 ,6, 11) DQ OEN =(3 ,3)
8712 23:42:38.841793 Update DQM dly =973 (3 ,6, 13) DQM OEN =(3 ,3)
8713 23:42:38.842263 DramC Write-DBI on
8714 23:42:38.842634 ==
8715 23:42:38.845822 Dram Type= 6, Freq= 0, CH_1, rank 1
8716 23:42:38.852141 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8717 23:42:38.852718 ==
8718 23:42:38.853094
8719 23:42:38.853520
8720 23:42:38.853856 TX Vref Scan disable
8721 23:42:38.855943 == TX Byte 0 ==
8722 23:42:38.859349 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8723 23:42:38.863024 == TX Byte 1 ==
8724 23:42:38.865696 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8725 23:42:38.869239 DramC Write-DBI off
8726 23:42:38.869748
8727 23:42:38.870120 [DATLAT]
8728 23:42:38.870465 Freq=1600, CH1 RK1
8729 23:42:38.870799
8730 23:42:38.872196 DATLAT Default: 0xe
8731 23:42:38.872661 0, 0xFFFF, sum = 0
8732 23:42:38.875684 1, 0xFFFF, sum = 0
8733 23:42:38.878918 2, 0xFFFF, sum = 0
8734 23:42:38.879395 3, 0xFFFF, sum = 0
8735 23:42:38.882386 4, 0xFFFF, sum = 0
8736 23:42:38.882860 5, 0xFFFF, sum = 0
8737 23:42:38.885614 6, 0xFFFF, sum = 0
8738 23:42:38.886089 7, 0xFFFF, sum = 0
8739 23:42:38.889241 8, 0xFFFF, sum = 0
8740 23:42:38.889876 9, 0xFFFF, sum = 0
8741 23:42:38.892306 10, 0xFFFF, sum = 0
8742 23:42:38.892783 11, 0xFFFF, sum = 0
8743 23:42:38.895782 12, 0xFFF, sum = 0
8744 23:42:38.896373 13, 0x0, sum = 1
8745 23:42:38.898862 14, 0x0, sum = 2
8746 23:42:38.899351 15, 0x0, sum = 3
8747 23:42:38.902292 16, 0x0, sum = 4
8748 23:42:38.902770 best_step = 14
8749 23:42:38.903143
8750 23:42:38.903486 ==
8751 23:42:38.905631 Dram Type= 6, Freq= 0, CH_1, rank 1
8752 23:42:38.908872 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8753 23:42:38.912204 ==
8754 23:42:38.912672 RX Vref Scan: 0
8755 23:42:38.913042
8756 23:42:38.915972 RX Vref 0 -> 0, step: 1
8757 23:42:38.916441
8758 23:42:38.916814 RX Delay 3 -> 252, step: 4
8759 23:42:38.922966 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8760 23:42:38.926065 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8761 23:42:38.929409 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8762 23:42:38.932694 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8763 23:42:38.936249 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8764 23:42:38.942575 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8765 23:42:38.946250 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8766 23:42:38.949244 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8767 23:42:38.952968 iDelay=195, Bit 8, Center 104 (47 ~ 162) 116
8768 23:42:38.956051 iDelay=195, Bit 9, Center 108 (55 ~ 162) 108
8769 23:42:38.962428 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8770 23:42:38.965907 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8771 23:42:38.969108 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8772 23:42:38.972760 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8773 23:42:38.979212 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8774 23:42:38.982520 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8775 23:42:38.982987 ==
8776 23:42:38.985864 Dram Type= 6, Freq= 0, CH_1, rank 1
8777 23:42:38.989122 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8778 23:42:38.989629 ==
8779 23:42:38.990004 DQS Delay:
8780 23:42:38.992259 DQS0 = 0, DQS1 = 0
8781 23:42:38.992686 DQM Delay:
8782 23:42:38.995908 DQM0 = 127, DQM1 = 122
8783 23:42:38.996488 DQ Delay:
8784 23:42:38.998897 DQ0 =128, DQ1 =124, DQ2 =118, DQ3 =126
8785 23:42:39.002132 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8786 23:42:39.005757 DQ8 =104, DQ9 =108, DQ10 =124, DQ11 =114
8787 23:42:39.012156 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8788 23:42:39.012582
8789 23:42:39.012916
8790 23:42:39.013224
8791 23:42:39.015544 [DramC_TX_OE_Calibration] TA2
8792 23:42:39.015966 Original DQ_B0 (3 6) =30, OEN = 27
8793 23:42:39.018725 Original DQ_B1 (3 6) =30, OEN = 27
8794 23:42:39.022031 24, 0x0, End_B0=24 End_B1=24
8795 23:42:39.025217 25, 0x0, End_B0=25 End_B1=25
8796 23:42:39.028914 26, 0x0, End_B0=26 End_B1=26
8797 23:42:39.032275 27, 0x0, End_B0=27 End_B1=27
8798 23:42:39.033037 28, 0x0, End_B0=28 End_B1=28
8799 23:42:39.035596 29, 0x0, End_B0=29 End_B1=29
8800 23:42:39.038839 30, 0x0, End_B0=30 End_B1=30
8801 23:42:39.041754 31, 0x4141, End_B0=30 End_B1=30
8802 23:42:39.045275 Byte0 end_step=30 best_step=27
8803 23:42:39.045801 Byte1 end_step=30 best_step=27
8804 23:42:39.048439 Byte0 TX OE(2T, 0.5T) = (3, 3)
8805 23:42:39.051825 Byte1 TX OE(2T, 0.5T) = (3, 3)
8806 23:42:39.052405
8807 23:42:39.052910
8808 23:42:39.061668 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
8809 23:42:39.062114 CH1 RK1: MR19=303, MR18=1F1F
8810 23:42:39.068265 CH1_RK1: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
8811 23:42:39.071617 [RxdqsGatingPostProcess] freq 1600
8812 23:42:39.078463 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8813 23:42:39.081497 Pre-setting of DQS Precalculation
8814 23:42:39.085165 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8815 23:42:39.095310 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8816 23:42:39.101431 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8817 23:42:39.101863
8818 23:42:39.102200
8819 23:42:39.104955 [Calibration Summary] 3200 Mbps
8820 23:42:39.105426 CH 0, Rank 0
8821 23:42:39.108251 SW Impedance : PASS
8822 23:42:39.108686 DUTY Scan : NO K
8823 23:42:39.111833 ZQ Calibration : PASS
8824 23:42:39.114574 Jitter Meter : NO K
8825 23:42:39.115052 CBT Training : PASS
8826 23:42:39.117830 Write leveling : PASS
8827 23:42:39.121545 RX DQS gating : PASS
8828 23:42:39.121975 RX DQ/DQS(RDDQC) : PASS
8829 23:42:39.124545 TX DQ/DQS : PASS
8830 23:42:39.128179 RX DATLAT : PASS
8831 23:42:39.128628 RX DQ/DQS(Engine): PASS
8832 23:42:39.131350 TX OE : PASS
8833 23:42:39.131916 All Pass.
8834 23:42:39.132365
8835 23:42:39.134595 CH 0, Rank 1
8836 23:42:39.135107 SW Impedance : PASS
8837 23:42:39.137977 DUTY Scan : NO K
8838 23:42:39.141183 ZQ Calibration : PASS
8839 23:42:39.141759 Jitter Meter : NO K
8840 23:42:39.144397 CBT Training : PASS
8841 23:42:39.144822 Write leveling : PASS
8842 23:42:39.147718 RX DQS gating : PASS
8843 23:42:39.150833 RX DQ/DQS(RDDQC) : PASS
8844 23:42:39.151360 TX DQ/DQS : PASS
8845 23:42:39.154466 RX DATLAT : PASS
8846 23:42:39.158119 RX DQ/DQS(Engine): PASS
8847 23:42:39.158704 TX OE : PASS
8848 23:42:39.160829 All Pass.
8849 23:42:39.161452
8850 23:42:39.161854 CH 1, Rank 0
8851 23:42:39.164135 SW Impedance : PASS
8852 23:42:39.164798 DUTY Scan : NO K
8853 23:42:39.167490 ZQ Calibration : PASS
8854 23:42:39.170762 Jitter Meter : NO K
8855 23:42:39.171394 CBT Training : PASS
8856 23:42:39.173944 Write leveling : PASS
8857 23:42:39.177749 RX DQS gating : PASS
8858 23:42:39.178307 RX DQ/DQS(RDDQC) : PASS
8859 23:42:39.180883 TX DQ/DQS : PASS
8860 23:42:39.183933 RX DATLAT : PASS
8861 23:42:39.184356 RX DQ/DQS(Engine): PASS
8862 23:42:39.187267 TX OE : PASS
8863 23:42:39.187696 All Pass.
8864 23:42:39.188032
8865 23:42:39.190948 CH 1, Rank 1
8866 23:42:39.191401 SW Impedance : PASS
8867 23:42:39.194071 DUTY Scan : NO K
8868 23:42:39.197555 ZQ Calibration : PASS
8869 23:42:39.198043 Jitter Meter : NO K
8870 23:42:39.200537 CBT Training : PASS
8871 23:42:39.204036 Write leveling : PASS
8872 23:42:39.204593 RX DQS gating : PASS
8873 23:42:39.207363 RX DQ/DQS(RDDQC) : PASS
8874 23:42:39.207931 TX DQ/DQS : PASS
8875 23:42:39.210609 RX DATLAT : PASS
8876 23:42:39.213996 RX DQ/DQS(Engine): PASS
8877 23:42:39.214420 TX OE : PASS
8878 23:42:39.217262 All Pass.
8879 23:42:39.217811
8880 23:42:39.218170 DramC Write-DBI on
8881 23:42:39.220687 PER_BANK_REFRESH: Hybrid Mode
8882 23:42:39.224077 TX_TRACKING: ON
8883 23:42:39.230686 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8884 23:42:39.240393 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8885 23:42:39.246984 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8886 23:42:39.250475 [FAST_K] Save calibration result to emmc
8887 23:42:39.253800 sync common calibartion params.
8888 23:42:39.254226 sync cbt_mode0:0, 1:0
8889 23:42:39.256982 dram_init: ddr_geometry: 0
8890 23:42:39.260373 dram_init: ddr_geometry: 0
8891 23:42:39.263664 dram_init: ddr_geometry: 0
8892 23:42:39.264133 0:dram_rank_size:80000000
8893 23:42:39.266856 1:dram_rank_size:80000000
8894 23:42:39.273245 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8895 23:42:39.273810 DFS_SHUFFLE_HW_MODE: ON
8896 23:42:39.280107 dramc_set_vcore_voltage set vcore to 725000
8897 23:42:39.280657 Read voltage for 1600, 0
8898 23:42:39.281064 Vio18 = 0
8899 23:42:39.283757 Vcore = 725000
8900 23:42:39.284335 Vdram = 0
8901 23:42:39.284777 Vddq = 0
8902 23:42:39.286794 Vmddr = 0
8903 23:42:39.287260 switch to 3200 Mbps bootup
8904 23:42:39.290324 [DramcRunTimeConfig]
8905 23:42:39.290842 PHYPLL
8906 23:42:39.293080 DPM_CONTROL_AFTERK: ON
8907 23:42:39.293677 PER_BANK_REFRESH: ON
8908 23:42:39.296776 REFRESH_OVERHEAD_REDUCTION: ON
8909 23:42:39.299902 CMD_PICG_NEW_MODE: OFF
8910 23:42:39.300535 XRTWTW_NEW_MODE: ON
8911 23:42:39.302899 XRTRTR_NEW_MODE: ON
8912 23:42:39.303364 TX_TRACKING: ON
8913 23:42:39.306393 RDSEL_TRACKING: OFF
8914 23:42:39.309820 DQS Precalculation for DVFS: ON
8915 23:42:39.310453 RX_TRACKING: OFF
8916 23:42:39.312840 HW_GATING DBG: ON
8917 23:42:39.313449 ZQCS_ENABLE_LP4: ON
8918 23:42:39.316211 RX_PICG_NEW_MODE: ON
8919 23:42:39.316713 TX_PICG_NEW_MODE: ON
8920 23:42:39.320150 ENABLE_RX_DCM_DPHY: ON
8921 23:42:39.322899 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8922 23:42:39.326823 DUMMY_READ_FOR_TRACKING: OFF
8923 23:42:39.329733 !!! SPM_CONTROL_AFTERK: OFF
8924 23:42:39.330261 !!! SPM could not control APHY
8925 23:42:39.333058 IMPEDANCE_TRACKING: ON
8926 23:42:39.333598 TEMP_SENSOR: ON
8927 23:42:39.336282 HW_SAVE_FOR_SR: OFF
8928 23:42:39.339716 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8929 23:42:39.342492 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8930 23:42:39.345733 Read ODT Tracking: ON
8931 23:42:39.346193 Refresh Rate DeBounce: ON
8932 23:42:39.348961 DFS_NO_QUEUE_FLUSH: ON
8933 23:42:39.352327 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8934 23:42:39.356099 ENABLE_DFS_RUNTIME_MRW: OFF
8935 23:42:39.356551 DDR_RESERVE_NEW_MODE: ON
8936 23:42:39.359296 MR_CBT_SWITCH_FREQ: ON
8937 23:42:39.362352 =========================
8938 23:42:39.380486 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8939 23:42:39.383611 dram_init: ddr_geometry: 0
8940 23:42:39.401677 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8941 23:42:39.405832 dram_init: dram init end (result: 0)
8942 23:42:39.411853 DRAM-K: Full calibration passed in 23447 msecs
8943 23:42:39.415028 MRC: failed to locate region type 0.
8944 23:42:39.415490 DRAM rank0 size:0x80000000,
8945 23:42:39.418318 DRAM rank1 size=0x80000000
8946 23:42:39.428175 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8947 23:42:39.435076 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8948 23:42:39.441750 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8949 23:42:39.448425 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8950 23:42:39.451887 DRAM rank0 size:0x80000000,
8951 23:42:39.454623 DRAM rank1 size=0x80000000
8952 23:42:39.455235 CBMEM:
8953 23:42:39.458213 IMD: root @ 0xfffff000 254 entries.
8954 23:42:39.461587 IMD: root @ 0xffffec00 62 entries.
8955 23:42:39.464799 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8956 23:42:39.467918 WARNING: RO_VPD is uninitialized or empty.
8957 23:42:39.474800 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8958 23:42:39.481465 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8959 23:42:39.493988 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8960 23:42:39.506025 BS: romstage times (exec / console): total (unknown) / 22979 ms
8961 23:42:39.506583
8962 23:42:39.506952
8963 23:42:39.515618 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8964 23:42:39.518605 ARM64: Exception handlers installed.
8965 23:42:39.522133 ARM64: Testing exception
8966 23:42:39.525286 ARM64: Done test exception
8967 23:42:39.525792 Enumerating buses...
8968 23:42:39.528746 Show all devs... Before device enumeration.
8969 23:42:39.531874 Root Device: enabled 1
8970 23:42:39.535485 CPU_CLUSTER: 0: enabled 1
8971 23:42:39.536052 CPU: 00: enabled 1
8972 23:42:39.538287 Compare with tree...
8973 23:42:39.538754 Root Device: enabled 1
8974 23:42:39.541916 CPU_CLUSTER: 0: enabled 1
8975 23:42:39.545366 CPU: 00: enabled 1
8976 23:42:39.545918 Root Device scanning...
8977 23:42:39.548434 scan_static_bus for Root Device
8978 23:42:39.551848 CPU_CLUSTER: 0 enabled
8979 23:42:39.555312 scan_static_bus for Root Device done
8980 23:42:39.558341 scan_bus: bus Root Device finished in 8 msecs
8981 23:42:39.558911 done
8982 23:42:39.565187 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8983 23:42:39.568116 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8984 23:42:39.574841 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8985 23:42:39.578284 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8986 23:42:39.581503 Allocating resources...
8987 23:42:39.585137 Reading resources...
8988 23:42:39.588366 Root Device read_resources bus 0 link: 0
8989 23:42:39.588834 DRAM rank0 size:0x80000000,
8990 23:42:39.591827 DRAM rank1 size=0x80000000
8991 23:42:39.594970 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8992 23:42:39.598167 CPU: 00 missing read_resources
8993 23:42:39.601371 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8994 23:42:39.608007 Root Device read_resources bus 0 link: 0 done
8995 23:42:39.608541 Done reading resources.
8996 23:42:39.614735 Show resources in subtree (Root Device)...After reading.
8997 23:42:39.618061 Root Device child on link 0 CPU_CLUSTER: 0
8998 23:42:39.621444 CPU_CLUSTER: 0 child on link 0 CPU: 00
8999 23:42:39.631407 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9000 23:42:39.631922 CPU: 00
9001 23:42:39.635037 Root Device assign_resources, bus 0 link: 0
9002 23:42:39.638231 CPU_CLUSTER: 0 missing set_resources
9003 23:42:39.644450 Root Device assign_resources, bus 0 link: 0 done
9004 23:42:39.644921 Done setting resources.
9005 23:42:39.651758 Show resources in subtree (Root Device)...After assigning values.
9006 23:42:39.654525 Root Device child on link 0 CPU_CLUSTER: 0
9007 23:42:39.658229 CPU_CLUSTER: 0 child on link 0 CPU: 00
9008 23:42:39.667521 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
9009 23:42:39.668171 CPU: 00
9010 23:42:39.671079 Done allocating resources.
9011 23:42:39.674211 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9012 23:42:39.678007 Enabling resources...
9013 23:42:39.678473 done.
9014 23:42:39.684670 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9015 23:42:39.685228 Initializing devices...
9016 23:42:39.687297 Root Device init
9017 23:42:39.687765 init hardware done!
9018 23:42:39.691228 0x00000018: ctrlr->caps
9019 23:42:39.694389 52.000 MHz: ctrlr->f_max
9020 23:42:39.694868 0.400 MHz: ctrlr->f_min
9021 23:42:39.697840 0x40ff8080: ctrlr->voltages
9022 23:42:39.700808 sclk: 390625
9023 23:42:39.701398 Bus Width = 1
9024 23:42:39.701777 sclk: 390625
9025 23:42:39.704348 Bus Width = 1
9026 23:42:39.704902 Early init status = 3
9027 23:42:39.710498 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9028 23:42:39.714382 in-header: 03 fc 00 00 01 00 00 00
9029 23:42:39.714848 in-data: 00
9030 23:42:39.720775 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9031 23:42:39.724033 in-header: 03 fd 00 00 00 00 00 00
9032 23:42:39.727565 in-data:
9033 23:42:39.730927 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9034 23:42:39.734161 in-header: 03 fc 00 00 01 00 00 00
9035 23:42:39.737564 in-data: 00
9036 23:42:39.740837 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9037 23:42:39.745526 in-header: 03 fd 00 00 00 00 00 00
9038 23:42:39.749194 in-data:
9039 23:42:39.752295 [SSUSB] Setting up USB HOST controller...
9040 23:42:39.755515 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9041 23:42:39.758655 [SSUSB] phy power-on done.
9042 23:42:39.761994 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9043 23:42:39.768406 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9044 23:42:39.771718 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9045 23:42:39.778521 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9046 23:42:39.784869 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9047 23:42:39.791748 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9048 23:42:39.798338 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9049 23:42:39.804479 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9050 23:42:39.808436 SPM: binary array size = 0x9dc
9051 23:42:39.811340 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9052 23:42:39.818386 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9053 23:42:39.824546 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9054 23:42:39.831219 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9055 23:42:39.834385 configure_display: Starting display init
9056 23:42:39.868697 anx7625_power_on_init: Init interface.
9057 23:42:39.871793 anx7625_disable_pd_protocol: Disabled PD feature.
9058 23:42:39.875269 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9059 23:42:39.903024 anx7625_start_dp_work: Secure OCM version=00
9060 23:42:39.906446 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9061 23:42:39.921368 sp_tx_get_edid_block: EDID Block = 1
9062 23:42:40.023561 Extracted contents:
9063 23:42:40.026712 header: 00 ff ff ff ff ff ff 00
9064 23:42:40.029918 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9065 23:42:40.033335 version: 01 04
9066 23:42:40.036646 basic params: 95 1f 11 78 0a
9067 23:42:40.039967 chroma info: 76 90 94 55 54 90 27 21 50 54
9068 23:42:40.043393 established: 00 00 00
9069 23:42:40.050023 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9070 23:42:40.053647 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9071 23:42:40.060081 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9072 23:42:40.066571 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9073 23:42:40.073198 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9074 23:42:40.076592 extensions: 00
9075 23:42:40.077014 checksum: fb
9076 23:42:40.077403
9077 23:42:40.079701 Manufacturer: IVO Model 57d Serial Number 0
9078 23:42:40.082869 Made week 0 of 2020
9079 23:42:40.086201 EDID version: 1.4
9080 23:42:40.086628 Digital display
9081 23:42:40.089598 6 bits per primary color channel
9082 23:42:40.090077 DisplayPort interface
9083 23:42:40.092867 Maximum image size: 31 cm x 17 cm
9084 23:42:40.096184 Gamma: 220%
9085 23:42:40.096455 Check DPMS levels
9086 23:42:40.099501 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9087 23:42:40.106259 First detailed timing is preferred timing
9088 23:42:40.106488 Established timings supported:
9089 23:42:40.109228 Standard timings supported:
9090 23:42:40.112605 Detailed timings
9091 23:42:40.115819 Hex of detail: 383680a07038204018303c0035ae10000019
9092 23:42:40.122597 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9093 23:42:40.125877 0780 0798 07c8 0820 hborder 0
9094 23:42:40.129266 0438 043b 0447 0458 vborder 0
9095 23:42:40.132452 -hsync -vsync
9096 23:42:40.132534 Did detailed timing
9097 23:42:40.138995 Hex of detail: 000000000000000000000000000000000000
9098 23:42:40.142331 Manufacturer-specified data, tag 0
9099 23:42:40.145641 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9100 23:42:40.148976 ASCII string: InfoVision
9101 23:42:40.152372 Hex of detail: 000000fe00523134304e574635205248200a
9102 23:42:40.155548 ASCII string: R140NWF5 RH
9103 23:42:40.155631 Checksum
9104 23:42:40.158694 Checksum: 0xfb (valid)
9105 23:42:40.162077 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9106 23:42:40.165238 DSI data_rate: 832800000 bps
9107 23:42:40.171914 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9108 23:42:40.175414 anx7625_parse_edid: pixelclock(138800).
9109 23:42:40.178591 hactive(1920), hsync(48), hfp(24), hbp(88)
9110 23:42:40.182525 vactive(1080), vsync(12), vfp(3), vbp(17)
9111 23:42:40.185240 anx7625_dsi_config: config dsi.
9112 23:42:40.191944 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9113 23:42:40.205168 anx7625_dsi_config: success to config DSI
9114 23:42:40.208607 anx7625_dp_start: MIPI phy setup OK.
9115 23:42:40.211978 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9116 23:42:40.215311 mtk_ddp_mode_set invalid vrefresh 60
9117 23:42:40.218608 main_disp_path_setup
9118 23:42:40.218690 ovl_layer_smi_id_en
9119 23:42:40.222237 ovl_layer_smi_id_en
9120 23:42:40.222346 ccorr_config
9121 23:42:40.222440 aal_config
9122 23:42:40.225113 gamma_config
9123 23:42:40.225221 postmask_config
9124 23:42:40.228787 dither_config
9125 23:42:40.232116 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9126 23:42:40.238882 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9127 23:42:40.241976 Root Device init finished in 551 msecs
9128 23:42:40.245146 CPU_CLUSTER: 0 init
9129 23:42:40.251870 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9130 23:42:40.255075 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9131 23:42:40.258178 APU_MBOX 0x190000b0 = 0x10001
9132 23:42:40.261765 APU_MBOX 0x190001b0 = 0x10001
9133 23:42:40.264769 APU_MBOX 0x190005b0 = 0x10001
9134 23:42:40.268255 APU_MBOX 0x190006b0 = 0x10001
9135 23:42:40.274934 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9136 23:42:40.284108 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9137 23:42:40.296527 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9138 23:42:40.303506 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9139 23:42:40.315159 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9140 23:42:40.324167 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9141 23:42:40.327267 CPU_CLUSTER: 0 init finished in 81 msecs
9142 23:42:40.330583 Devices initialized
9143 23:42:40.333973 Show all devs... After init.
9144 23:42:40.334056 Root Device: enabled 1
9145 23:42:40.337374 CPU_CLUSTER: 0: enabled 1
9146 23:42:40.340513 CPU: 00: enabled 1
9147 23:42:40.343969 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9148 23:42:40.347380 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9149 23:42:40.350552 ELOG: NV offset 0x57f000 size 0x1000
9150 23:42:40.357441 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9151 23:42:40.363581 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9152 23:42:40.366889 ELOG: Event(17) added with size 13 at 2024-06-04 23:42:41 UTC
9153 23:42:40.370432 out: cmd=0x121: 03 db 21 01 00 00 00 00
9154 23:42:40.374902 in-header: 03 df 00 00 2c 00 00 00
9155 23:42:40.388103 in-data: 84 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9156 23:42:40.394854 ELOG: Event(A1) added with size 10 at 2024-06-04 23:42:41 UTC
9157 23:42:40.401782 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9158 23:42:40.408020 ELOG: Event(A0) added with size 9 at 2024-06-04 23:42:41 UTC
9159 23:42:40.411561 elog_add_boot_reason: Logged dev mode boot
9160 23:42:40.414603 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9161 23:42:40.417929 Finalize devices...
9162 23:42:40.418011 Devices finalized
9163 23:42:40.424597 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9164 23:42:40.427845 Writing coreboot table at 0xffe64000
9165 23:42:40.431407 0. 000000000010a000-0000000000113fff: RAMSTAGE
9166 23:42:40.434703 1. 0000000040000000-00000000400fffff: RAM
9167 23:42:40.437879 2. 0000000040100000-000000004032afff: RAMSTAGE
9168 23:42:40.444443 3. 000000004032b000-00000000545fffff: RAM
9169 23:42:40.447942 4. 0000000054600000-000000005465ffff: BL31
9170 23:42:40.451556 5. 0000000054660000-00000000ffe63fff: RAM
9171 23:42:40.457605 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9172 23:42:40.461197 7. 0000000100000000-000000013fffffff: RAM
9173 23:42:40.461280 Passing 5 GPIOs to payload:
9174 23:42:40.468195 NAME | PORT | POLARITY | VALUE
9175 23:42:40.471087 EC in RW | 0x000000aa | low | undefined
9176 23:42:40.477526 EC interrupt | 0x00000005 | low | undefined
9177 23:42:40.481174 TPM interrupt | 0x000000ab | high | undefined
9178 23:42:40.484451 SD card detect | 0x00000011 | high | undefined
9179 23:42:40.490758 speaker enable | 0x00000093 | high | undefined
9180 23:42:40.494298 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9181 23:42:40.497454 in-header: 03 f4 00 00 02 00 00 00
9182 23:42:40.497527 in-data: 07 00
9183 23:42:40.500620 ADC[4]: Raw value=668222 ID=5
9184 23:42:40.504032 ADC[3]: Raw value=212549 ID=1
9185 23:42:40.507137 RAM Code: 0x51
9186 23:42:40.507246 ADC[6]: Raw value=74410 ID=0
9187 23:42:40.510472 ADC[5]: Raw value=211444 ID=1
9188 23:42:40.514014 SKU Code: 0x1
9189 23:42:40.517176 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 1d1d
9190 23:42:40.520730 coreboot table: 964 bytes.
9191 23:42:40.524112 IMD ROOT 0. 0xfffff000 0x00001000
9192 23:42:40.527022 IMD SMALL 1. 0xffffe000 0x00001000
9193 23:42:40.530286 RO MCACHE 2. 0xffffc000 0x00001104
9194 23:42:40.533793 CONSOLE 3. 0xfff7c000 0x00080000
9195 23:42:40.537211 FMAP 4. 0xfff7b000 0x00000452
9196 23:42:40.540414 TIME STAMP 5. 0xfff7a000 0x00000910
9197 23:42:40.543929 VBOOT WORK 6. 0xfff66000 0x00014000
9198 23:42:40.547401 RAMOOPS 7. 0xffe66000 0x00100000
9199 23:42:40.550270 COREBOOT 8. 0xffe64000 0x00002000
9200 23:42:40.550341 IMD small region:
9201 23:42:40.553494 IMD ROOT 0. 0xffffec00 0x00000400
9202 23:42:40.556910 VPD 1. 0xffffeb80 0x0000006c
9203 23:42:40.563369 MMC STATUS 2. 0xffffeb60 0x00000004
9204 23:42:40.566602 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9205 23:42:40.570119 Probing TPM: done!
9206 23:42:40.573659 Connected to device vid:did:rid of 1ae0:0028:00
9207 23:42:40.583821 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9208 23:42:40.586780 Initialized TPM device CR50 revision 0
9209 23:42:40.590344 Checking cr50 for pending updates
9210 23:42:40.594326 Reading cr50 TPM mode
9211 23:42:40.602823 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9212 23:42:40.609426 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9213 23:42:40.649379 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9214 23:42:40.652750 Checking segment from ROM address 0x40100000
9215 23:42:40.656009 Checking segment from ROM address 0x4010001c
9216 23:42:40.662910 Loading segment from ROM address 0x40100000
9217 23:42:40.663000 code (compression=0)
9218 23:42:40.672739 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9219 23:42:40.679435 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9220 23:42:40.679545 it's not compressed!
9221 23:42:40.685751 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9222 23:42:40.692237 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9223 23:42:40.709926 Loading segment from ROM address 0x4010001c
9224 23:42:40.710039 Entry Point 0x80000000
9225 23:42:40.713160 Loaded segments
9226 23:42:40.716341 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9227 23:42:40.723164 Jumping to boot code at 0x80000000(0xffe64000)
9228 23:42:40.729737 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9229 23:42:40.736438 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9230 23:42:40.744367 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9231 23:42:40.747443 Checking segment from ROM address 0x40100000
9232 23:42:40.750888 Checking segment from ROM address 0x4010001c
9233 23:42:40.758253 Loading segment from ROM address 0x40100000
9234 23:42:40.758347 code (compression=1)
9235 23:42:40.764452 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9236 23:42:40.774212 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9237 23:42:40.774325 using LZMA
9238 23:42:40.782829 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9239 23:42:40.789533 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9240 23:42:40.792996 Loading segment from ROM address 0x4010001c
9241 23:42:40.793107 Entry Point 0x54601000
9242 23:42:40.795951 Loaded segments
9243 23:42:40.799282 NOTICE: MT8192 bl31_setup
9244 23:42:40.806439 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9245 23:42:40.809487 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9246 23:42:40.812975 WARNING: region 0:
9247 23:42:40.816298 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9248 23:42:40.816398 WARNING: region 1:
9249 23:42:40.822798 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9250 23:42:40.826023 WARNING: region 2:
9251 23:42:40.829503 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9252 23:42:40.832652 WARNING: region 3:
9253 23:42:40.836118 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9254 23:42:40.839326 WARNING: region 4:
9255 23:42:40.845982 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9256 23:42:40.846059 WARNING: region 5:
9257 23:42:40.849688 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9258 23:42:40.852767 WARNING: region 6:
9259 23:42:40.856114 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9260 23:42:40.859569 WARNING: region 7:
9261 23:42:40.862878 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9262 23:42:40.869352 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9263 23:42:40.872696 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9264 23:42:40.875944 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9265 23:42:40.882676 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9266 23:42:40.886025 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9267 23:42:40.889797 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9268 23:42:40.895946 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9269 23:42:40.899436 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9270 23:42:40.906105 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9271 23:42:40.909476 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9272 23:42:40.912769 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9273 23:42:40.919236 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9274 23:42:40.922909 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9275 23:42:40.925829 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9276 23:42:40.932632 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9277 23:42:40.935881 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9278 23:42:40.942698 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9279 23:42:40.945980 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9280 23:42:40.949274 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9281 23:42:40.956160 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9282 23:42:40.959338 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9283 23:42:40.962797 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9284 23:42:40.969672 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9285 23:42:40.972974 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9286 23:42:40.979578 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9287 23:42:40.982863 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9288 23:42:40.986445 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9289 23:42:40.993011 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9290 23:42:40.996839 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9291 23:42:41.003006 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9292 23:42:41.006849 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9293 23:42:41.009893 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9294 23:42:41.016654 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9295 23:42:41.019488 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9296 23:42:41.023170 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9297 23:42:41.026953 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9298 23:42:41.033081 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9299 23:42:41.036410 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9300 23:42:41.039883 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9301 23:42:41.043250 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9302 23:42:41.049869 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9303 23:42:41.053252 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9304 23:42:41.056197 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9305 23:42:41.059374 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9306 23:42:41.066228 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9307 23:42:41.069474 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9308 23:42:41.072748 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9309 23:42:41.076065 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9310 23:42:41.082868 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9311 23:42:41.085863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9312 23:42:41.092675 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9313 23:42:41.096149 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9314 23:42:41.099532 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9315 23:42:41.106053 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9316 23:42:41.109328 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9317 23:42:41.115939 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9318 23:42:41.119153 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9319 23:42:41.125678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9320 23:42:41.129195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9321 23:42:41.135699 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9322 23:42:41.138993 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9323 23:42:41.142546 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9324 23:42:41.149137 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9325 23:42:41.152457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9326 23:42:41.159133 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9327 23:42:41.162405 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9328 23:42:41.168916 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9329 23:42:41.172188 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9330 23:42:41.178887 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9331 23:42:41.182164 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9332 23:42:41.185399 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9333 23:42:41.191826 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9334 23:42:41.195115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9335 23:42:41.202091 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9336 23:42:41.205400 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9337 23:42:41.211848 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9338 23:42:41.215187 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9339 23:42:41.218543 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9340 23:42:41.225329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9341 23:42:41.228424 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9342 23:42:41.235294 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9343 23:42:41.238699 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9344 23:42:41.245074 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9345 23:42:41.248280 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9346 23:42:41.254986 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9347 23:42:41.258614 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9348 23:42:41.262010 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9349 23:42:41.268701 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9350 23:42:41.272039 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9351 23:42:41.278510 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9352 23:42:41.281773 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9353 23:42:41.285245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9354 23:42:41.291954 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9355 23:42:41.295503 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9356 23:42:41.301845 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9357 23:42:41.305333 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9358 23:42:41.311963 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9359 23:42:41.315223 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9360 23:42:41.318569 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9361 23:42:41.321891 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9362 23:42:41.328470 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9363 23:42:41.331836 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9364 23:42:41.335083 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9365 23:42:41.342212 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9366 23:42:41.345409 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9367 23:42:41.352454 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9368 23:42:41.355721 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9369 23:42:41.358791 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9370 23:42:41.365375 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9371 23:42:41.368831 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9372 23:42:41.375587 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9373 23:42:41.378648 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9374 23:42:41.382132 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9375 23:42:41.388775 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9376 23:42:41.392266 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9377 23:42:41.395344 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9378 23:42:41.402458 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9379 23:42:41.405454 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9380 23:42:41.408893 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9381 23:42:41.415822 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9382 23:42:41.418809 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9383 23:42:41.421996 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9384 23:42:41.425760 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9385 23:42:41.432153 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9386 23:42:41.435511 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9387 23:42:41.438709 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9388 23:42:41.445377 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9389 23:42:41.448676 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9390 23:42:41.455353 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9391 23:42:41.458800 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9392 23:42:41.462058 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9393 23:42:41.469058 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9394 23:42:41.471967 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9395 23:42:41.475441 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9396 23:42:41.482170 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9397 23:42:41.485376 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9398 23:42:41.491965 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9399 23:42:41.495516 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9400 23:42:41.498704 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9401 23:42:41.505443 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9402 23:42:41.508389 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9403 23:42:41.515432 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9404 23:42:41.518842 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9405 23:42:41.521913 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9406 23:42:41.529088 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9407 23:42:41.532023 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9408 23:42:41.538881 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9409 23:42:41.541983 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9410 23:42:41.545326 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9411 23:42:41.551983 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9412 23:42:41.555263 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9413 23:42:41.558633 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9414 23:42:41.565569 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9415 23:42:41.568902 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9416 23:42:41.575476 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9417 23:42:41.578457 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9418 23:42:41.582148 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9419 23:42:41.588990 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9420 23:42:41.591808 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9421 23:42:41.598258 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9422 23:42:41.601828 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9423 23:42:41.604944 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9424 23:42:41.612035 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9425 23:42:41.615022 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9426 23:42:41.621597 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9427 23:42:41.624710 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9428 23:42:41.628168 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9429 23:42:41.634614 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9430 23:42:41.638076 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9431 23:42:41.645035 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9432 23:42:41.647950 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9433 23:42:41.651104 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9434 23:42:41.657720 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9435 23:42:41.660976 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9436 23:42:41.667837 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9437 23:42:41.671142 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9438 23:42:41.674608 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9439 23:42:41.680636 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9440 23:42:41.683945 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9441 23:42:41.690625 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9442 23:42:41.693799 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9443 23:42:41.697153 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9444 23:42:41.703592 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9445 23:42:41.706748 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9446 23:42:41.713551 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9447 23:42:41.716726 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9448 23:42:41.719984 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9449 23:42:41.726758 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9450 23:42:41.730297 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9451 23:42:41.736983 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9452 23:42:41.739816 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9453 23:42:41.743159 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9454 23:42:41.750008 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9455 23:42:41.753056 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9456 23:42:41.760285 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9457 23:42:41.762957 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9458 23:42:41.769602 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9459 23:42:41.772982 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9460 23:42:41.776118 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9461 23:42:41.783614 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9462 23:42:41.786102 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9463 23:42:41.793176 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9464 23:42:41.796345 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9465 23:42:41.802707 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9466 23:42:41.806058 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9467 23:42:41.809578 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9468 23:42:41.815962 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9469 23:42:41.819370 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9470 23:42:41.826103 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9471 23:42:41.829269 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9472 23:42:41.835991 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9473 23:42:41.839278 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9474 23:42:41.842667 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9475 23:42:41.849000 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9476 23:42:41.852541 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9477 23:42:41.858989 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9478 23:42:41.862450 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9479 23:42:41.865556 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9480 23:42:41.872879 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9481 23:42:41.875598 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9482 23:42:41.882464 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9483 23:42:41.885886 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9484 23:42:41.892045 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9485 23:42:41.895803 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9486 23:42:41.899156 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9487 23:42:41.905402 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9488 23:42:41.908839 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9489 23:42:41.915515 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9490 23:42:41.919228 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9491 23:42:41.921937 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9492 23:42:41.928639 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9493 23:42:41.931927 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9494 23:42:41.935112 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9495 23:42:41.938620 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9496 23:42:41.945197 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9497 23:42:41.948562 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9498 23:42:41.951923 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9499 23:42:41.958110 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9500 23:42:41.961766 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9501 23:42:41.965032 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9502 23:42:41.971655 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9503 23:42:41.974855 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9504 23:42:41.981400 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9505 23:42:41.984565 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9506 23:42:41.987823 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9507 23:42:41.994734 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9508 23:42:41.997794 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9509 23:42:42.004506 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9510 23:42:42.007665 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9511 23:42:42.011352 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9512 23:42:42.018055 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9513 23:42:42.021417 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9514 23:42:42.024461 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9515 23:42:42.031134 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9516 23:42:42.034349 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9517 23:42:42.040718 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9518 23:42:42.044065 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9519 23:42:42.047387 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9520 23:42:42.054067 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9521 23:42:42.056998 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9522 23:42:42.060213 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9523 23:42:42.066952 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9524 23:42:42.070073 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9525 23:42:42.073603 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9526 23:42:42.080214 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9527 23:42:42.083491 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9528 23:42:42.090152 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9529 23:42:42.093412 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9530 23:42:42.096715 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9531 23:42:42.100000 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9532 23:42:42.106640 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9533 23:42:42.110154 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9534 23:42:42.113256 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9535 23:42:42.116930 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9536 23:42:42.123389 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9537 23:42:42.126810 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9538 23:42:42.130403 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9539 23:42:42.133433 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9540 23:42:42.140032 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9541 23:42:42.143588 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9542 23:42:42.146891 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9543 23:42:42.153210 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9544 23:42:42.156102 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9545 23:42:42.159539 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9546 23:42:42.166055 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9547 23:42:42.169643 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9548 23:42:42.176189 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9549 23:42:42.179372 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9550 23:42:42.185920 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9551 23:42:42.189415 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9552 23:42:42.192870 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9553 23:42:42.199029 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9554 23:42:42.202246 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9555 23:42:42.209503 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9556 23:42:42.212054 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9557 23:42:42.218764 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9558 23:42:42.222428 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9559 23:42:42.225629 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9560 23:42:42.232003 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9561 23:42:42.235200 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9562 23:42:42.242070 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9563 23:42:42.245267 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9564 23:42:42.248984 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9565 23:42:42.255193 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9566 23:42:42.259016 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9567 23:42:42.265322 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9568 23:42:42.268923 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9569 23:42:42.271664 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9570 23:42:42.278283 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9571 23:42:42.281744 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9572 23:42:42.288299 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9573 23:42:42.291849 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9574 23:42:42.298286 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9575 23:42:42.301826 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9576 23:42:42.305546 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9577 23:42:42.311874 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9578 23:42:42.315409 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9579 23:42:42.321989 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9580 23:42:42.325062 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9581 23:42:42.328679 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9582 23:42:42.334789 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9583 23:42:42.338295 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9584 23:42:42.345284 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9585 23:42:42.348239 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9586 23:42:42.351516 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9587 23:42:42.358286 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9588 23:42:42.361517 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9589 23:42:42.368286 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9590 23:42:42.371769 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9591 23:42:42.374736 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9592 23:42:42.381374 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9593 23:42:42.384785 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9594 23:42:42.391804 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9595 23:42:42.394963 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9596 23:42:42.401376 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9597 23:42:42.404595 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9598 23:42:42.407891 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9599 23:42:42.414700 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9600 23:42:42.417744 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9601 23:42:42.424360 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9602 23:42:42.427724 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9603 23:42:42.431160 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9604 23:42:42.437809 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9605 23:42:42.441005 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9606 23:42:42.447542 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9607 23:42:42.450986 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9608 23:42:42.454429 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9609 23:42:42.461049 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9610 23:42:42.464088 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9611 23:42:42.470542 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9612 23:42:42.473738 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9613 23:42:42.480351 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9614 23:42:42.483611 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9615 23:42:42.486909 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9616 23:42:42.493922 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9617 23:42:42.497050 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9618 23:42:42.503853 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9619 23:42:42.506865 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9620 23:42:42.513496 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9621 23:42:42.516950 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9622 23:42:42.523223 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9623 23:42:42.526771 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9624 23:42:42.530164 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9625 23:42:42.536516 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9626 23:42:42.539870 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9627 23:42:42.546359 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9628 23:42:42.549272 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9629 23:42:42.556208 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9630 23:42:42.559483 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9631 23:42:42.565804 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9632 23:42:42.569422 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9633 23:42:42.572554 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9634 23:42:42.579145 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9635 23:42:42.582822 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9636 23:42:42.589134 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9637 23:42:42.592349 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9638 23:42:42.599304 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9639 23:42:42.602290 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9640 23:42:42.608852 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9641 23:42:42.612154 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9642 23:42:42.615573 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9643 23:42:42.621977 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9644 23:42:42.625622 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9645 23:42:42.632124 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9646 23:42:42.635523 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9647 23:42:42.642216 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9648 23:42:42.645214 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9649 23:42:42.648960 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9650 23:42:42.655284 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9651 23:42:42.658365 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9652 23:42:42.665247 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9653 23:42:42.668949 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9654 23:42:42.675291 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9655 23:42:42.678413 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9656 23:42:42.684937 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9657 23:42:42.688492 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9658 23:42:42.694726 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9659 23:42:42.698438 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9660 23:42:42.701222 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9661 23:42:42.708428 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9662 23:42:42.711557 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9663 23:42:42.718629 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9664 23:42:42.721561 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9665 23:42:42.724755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9666 23:42:42.731211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9667 23:42:42.734502 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9668 23:42:42.740953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9669 23:42:42.744388 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9670 23:42:42.750916 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9671 23:42:42.754275 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9672 23:42:42.760989 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9673 23:42:42.764510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9674 23:42:42.771023 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9675 23:42:42.774503 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9676 23:42:42.781193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9677 23:42:42.784271 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9678 23:42:42.790959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9679 23:42:42.793918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9680 23:42:42.800853 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9681 23:42:42.803912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9682 23:42:42.810198 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9683 23:42:42.813505 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9684 23:42:42.820729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9685 23:42:42.823508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9686 23:42:42.830260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9687 23:42:42.833966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9688 23:42:42.840147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9689 23:42:42.843239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9690 23:42:42.849930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9691 23:42:42.853366 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9692 23:42:42.859929 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9693 23:42:42.863142 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9694 23:42:42.869860 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9695 23:42:42.872904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9696 23:42:42.879534 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9697 23:42:42.880081 INFO: [APUAPC] vio 0
9698 23:42:42.886478 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9699 23:42:42.889827 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9700 23:42:42.893426 INFO: [APUAPC] D0_APC_0: 0x400510
9701 23:42:42.896377 INFO: [APUAPC] D0_APC_1: 0x0
9702 23:42:42.900332 INFO: [APUAPC] D0_APC_2: 0x1540
9703 23:42:42.903071 INFO: [APUAPC] D0_APC_3: 0x0
9704 23:42:42.906265 INFO: [APUAPC] D1_APC_0: 0xffffffff
9705 23:42:42.909656 INFO: [APUAPC] D1_APC_1: 0xffffffff
9706 23:42:42.913205 INFO: [APUAPC] D1_APC_2: 0x3fffff
9707 23:42:42.916210 INFO: [APUAPC] D1_APC_3: 0x0
9708 23:42:42.919610 INFO: [APUAPC] D2_APC_0: 0xffffffff
9709 23:42:42.922899 INFO: [APUAPC] D2_APC_1: 0xffffffff
9710 23:42:42.925662 INFO: [APUAPC] D2_APC_2: 0x3fffff
9711 23:42:42.929068 INFO: [APUAPC] D2_APC_3: 0x0
9712 23:42:42.932436 INFO: [APUAPC] D3_APC_0: 0xffffffff
9713 23:42:42.936008 INFO: [APUAPC] D3_APC_1: 0xffffffff
9714 23:42:42.939770 INFO: [APUAPC] D3_APC_2: 0x3fffff
9715 23:42:42.942813 INFO: [APUAPC] D3_APC_3: 0x0
9716 23:42:42.945741 INFO: [APUAPC] D4_APC_0: 0xffffffff
9717 23:42:42.949355 INFO: [APUAPC] D4_APC_1: 0xffffffff
9718 23:42:42.952579 INFO: [APUAPC] D4_APC_2: 0x3fffff
9719 23:42:42.952781 INFO: [APUAPC] D4_APC_3: 0x0
9720 23:42:42.956003 INFO: [APUAPC] D5_APC_0: 0xffffffff
9721 23:42:42.962621 INFO: [APUAPC] D5_APC_1: 0xffffffff
9722 23:42:42.965850 INFO: [APUAPC] D5_APC_2: 0x3fffff
9723 23:42:42.966017 INFO: [APUAPC] D5_APC_3: 0x0
9724 23:42:42.968950 INFO: [APUAPC] D6_APC_0: 0xffffffff
9725 23:42:42.972688 INFO: [APUAPC] D6_APC_1: 0xffffffff
9726 23:42:42.975524 INFO: [APUAPC] D6_APC_2: 0x3fffff
9727 23:42:42.979124 INFO: [APUAPC] D6_APC_3: 0x0
9728 23:42:42.982655 INFO: [APUAPC] D7_APC_0: 0xffffffff
9729 23:42:42.985667 INFO: [APUAPC] D7_APC_1: 0xffffffff
9730 23:42:42.988979 INFO: [APUAPC] D7_APC_2: 0x3fffff
9731 23:42:42.992842 INFO: [APUAPC] D7_APC_3: 0x0
9732 23:42:42.996348 INFO: [APUAPC] D8_APC_0: 0xffffffff
9733 23:42:42.999062 INFO: [APUAPC] D8_APC_1: 0xffffffff
9734 23:42:43.002499 INFO: [APUAPC] D8_APC_2: 0x3fffff
9735 23:42:43.005831 INFO: [APUAPC] D8_APC_3: 0x0
9736 23:42:43.009028 INFO: [APUAPC] D9_APC_0: 0xffffffff
9737 23:42:43.012557 INFO: [APUAPC] D9_APC_1: 0xffffffff
9738 23:42:43.015522 INFO: [APUAPC] D9_APC_2: 0x3fffff
9739 23:42:43.018881 INFO: [APUAPC] D9_APC_3: 0x0
9740 23:42:43.022452 INFO: [APUAPC] D10_APC_0: 0xffffffff
9741 23:42:43.025532 INFO: [APUAPC] D10_APC_1: 0xffffffff
9742 23:42:43.028846 INFO: [APUAPC] D10_APC_2: 0x3fffff
9743 23:42:43.032256 INFO: [APUAPC] D10_APC_3: 0x0
9744 23:42:43.035638 INFO: [APUAPC] D11_APC_0: 0xffffffff
9745 23:42:43.038809 INFO: [APUAPC] D11_APC_1: 0xffffffff
9746 23:42:43.042125 INFO: [APUAPC] D11_APC_2: 0x3fffff
9747 23:42:43.045850 INFO: [APUAPC] D11_APC_3: 0x0
9748 23:42:43.048866 INFO: [APUAPC] D12_APC_0: 0xffffffff
9749 23:42:43.052296 INFO: [APUAPC] D12_APC_1: 0xffffffff
9750 23:42:43.055452 INFO: [APUAPC] D12_APC_2: 0x3fffff
9751 23:42:43.059032 INFO: [APUAPC] D12_APC_3: 0x0
9752 23:42:43.062201 INFO: [APUAPC] D13_APC_0: 0xffffffff
9753 23:42:43.065805 INFO: [APUAPC] D13_APC_1: 0xffffffff
9754 23:42:43.068817 INFO: [APUAPC] D13_APC_2: 0x3fffff
9755 23:42:43.071853 INFO: [APUAPC] D13_APC_3: 0x0
9756 23:42:43.075376 INFO: [APUAPC] D14_APC_0: 0xffffffff
9757 23:42:43.078653 INFO: [APUAPC] D14_APC_1: 0xffffffff
9758 23:42:43.081988 INFO: [APUAPC] D14_APC_2: 0x3fffff
9759 23:42:43.085563 INFO: [APUAPC] D14_APC_3: 0x0
9760 23:42:43.088709 INFO: [APUAPC] D15_APC_0: 0xffffffff
9761 23:42:43.091670 INFO: [APUAPC] D15_APC_1: 0xffffffff
9762 23:42:43.095142 INFO: [APUAPC] D15_APC_2: 0x3fffff
9763 23:42:43.098761 INFO: [APUAPC] D15_APC_3: 0x0
9764 23:42:43.101836 INFO: [APUAPC] APC_CON: 0x4
9765 23:42:43.104890 INFO: [NOCDAPC] D0_APC_0: 0x0
9766 23:42:43.108466 INFO: [NOCDAPC] D0_APC_1: 0x0
9767 23:42:43.111714 INFO: [NOCDAPC] D1_APC_0: 0x0
9768 23:42:43.115077 INFO: [NOCDAPC] D1_APC_1: 0xfff
9769 23:42:43.118679 INFO: [NOCDAPC] D2_APC_0: 0x0
9770 23:42:43.121769 INFO: [NOCDAPC] D2_APC_1: 0xfff
9771 23:42:43.122236 INFO: [NOCDAPC] D3_APC_0: 0x0
9772 23:42:43.124976 INFO: [NOCDAPC] D3_APC_1: 0xfff
9773 23:42:43.128414 INFO: [NOCDAPC] D4_APC_0: 0x0
9774 23:42:43.131577 INFO: [NOCDAPC] D4_APC_1: 0xfff
9775 23:42:43.134821 INFO: [NOCDAPC] D5_APC_0: 0x0
9776 23:42:43.138345 INFO: [NOCDAPC] D5_APC_1: 0xfff
9777 23:42:43.141493 INFO: [NOCDAPC] D6_APC_0: 0x0
9778 23:42:43.144710 INFO: [NOCDAPC] D6_APC_1: 0xfff
9779 23:42:43.147698 INFO: [NOCDAPC] D7_APC_0: 0x0
9780 23:42:43.151114 INFO: [NOCDAPC] D7_APC_1: 0xfff
9781 23:42:43.154722 INFO: [NOCDAPC] D8_APC_0: 0x0
9782 23:42:43.158035 INFO: [NOCDAPC] D8_APC_1: 0xfff
9783 23:42:43.158615 INFO: [NOCDAPC] D9_APC_0: 0x0
9784 23:42:43.161370 INFO: [NOCDAPC] D9_APC_1: 0xfff
9785 23:42:43.164462 INFO: [NOCDAPC] D10_APC_0: 0x0
9786 23:42:43.167758 INFO: [NOCDAPC] D10_APC_1: 0xfff
9787 23:42:43.171152 INFO: [NOCDAPC] D11_APC_0: 0x0
9788 23:42:43.174858 INFO: [NOCDAPC] D11_APC_1: 0xfff
9789 23:42:43.177970 INFO: [NOCDAPC] D12_APC_0: 0x0
9790 23:42:43.181074 INFO: [NOCDAPC] D12_APC_1: 0xfff
9791 23:42:43.184514 INFO: [NOCDAPC] D13_APC_0: 0x0
9792 23:42:43.187758 INFO: [NOCDAPC] D13_APC_1: 0xfff
9793 23:42:43.191385 INFO: [NOCDAPC] D14_APC_0: 0x0
9794 23:42:43.194442 INFO: [NOCDAPC] D14_APC_1: 0xfff
9795 23:42:43.197507 INFO: [NOCDAPC] D15_APC_0: 0x0
9796 23:42:43.201327 INFO: [NOCDAPC] D15_APC_1: 0xfff
9797 23:42:43.201754 INFO: [NOCDAPC] APC_CON: 0x4
9798 23:42:43.204249 INFO: [APUAPC] set_apusys_apc done
9799 23:42:43.207851 INFO: [DEVAPC] devapc_init done
9800 23:42:43.214834 INFO: GICv3 without legacy support detected.
9801 23:42:43.217770 INFO: ARM GICv3 driver initialized in EL3
9802 23:42:43.221673 INFO: Maximum SPI INTID supported: 639
9803 23:42:43.224193 INFO: BL31: Initializing runtime services
9804 23:42:43.230970 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9805 23:42:43.234420 INFO: SPM: enable CPC mode
9806 23:42:43.237585 INFO: mcdi ready for mcusys-off-idle and system suspend
9807 23:42:43.244181 INFO: BL31: Preparing for EL3 exit to normal world
9808 23:42:43.247204 INFO: Entry point address = 0x80000000
9809 23:42:43.247779 INFO: SPSR = 0x8
9810 23:42:43.254485
9811 23:42:43.254905
9812 23:42:43.255382
9813 23:42:43.257925 Starting depthcharge on Spherion...
9814 23:42:43.258431
9815 23:42:43.258911 Wipe memory regions:
9816 23:42:43.259361
9817 23:42:43.262240 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9818 23:42:43.262757 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9819 23:42:43.263180 Setting prompt string to ['asurada:']
9820 23:42:43.263585 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9821 23:42:43.264252 [0x00000040000000, 0x00000054600000)
9822 23:42:43.383237
9823 23:42:43.383784 [0x00000054660000, 0x00000080000000)
9824 23:42:43.644016
9825 23:42:43.644332 [0x000000821a7280, 0x000000ffe64000)
9826 23:42:44.388832
9827 23:42:44.389429 [0x00000100000000, 0x00000140000000)
9828 23:42:44.770245
9829 23:42:44.773466 Initializing XHCI USB controller at 0x11200000.
9830 23:42:45.811091
9831 23:42:45.814194 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9832 23:42:45.814755
9833 23:42:45.815124
9834 23:42:45.815932 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9836 23:42:45.917441 asurada: tftpboot 192.168.201.1 14172914/tftp-deploy-758tthvv/kernel/image.itb 14172914/tftp-deploy-758tthvv/kernel/cmdline
9837 23:42:45.918091 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9838 23:42:45.918553 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9839 23:42:45.922770 tftpboot 192.168.201.1 14172914/tftp-deploy-758tthvv/kernel/image.itp-deploy-758tthvv/kernel/cmdline
9840 23:42:45.923306
9841 23:42:45.923681 Waiting for link
9842 23:42:46.083444
9843 23:42:46.084005 R8152: Initializing
9844 23:42:46.084374
9845 23:42:46.086588 Version 9 (ocp_data = 6010)
9846 23:42:46.087060
9847 23:42:46.089753 R8152: Done initializing
9848 23:42:46.090223
9849 23:42:46.090594 Adding net device
9850 23:42:48.028994
9851 23:42:48.029612 done.
9852 23:42:48.029989
9853 23:42:48.030334 MAC: 00:e0:4c:68:03:bd
9854 23:42:48.030666
9855 23:42:48.032098 Sending DHCP discover... done.
9856 23:42:48.032563
9857 23:42:48.035023 Waiting for reply... done.
9858 23:42:48.035130
9859 23:42:48.038299 Sending DHCP request... done.
9860 23:42:48.038380
9861 23:42:48.050831 Waiting for reply... done.
9862 23:42:48.050998
9863 23:42:48.051070 My ip is 192.168.201.16
9864 23:42:48.051136
9865 23:42:48.054276 The DHCP server ip is 192.168.201.1
9866 23:42:48.054447
9867 23:42:48.060642 TFTP server IP predefined by user: 192.168.201.1
9868 23:42:48.060820
9869 23:42:48.067230 Bootfile predefined by user: 14172914/tftp-deploy-758tthvv/kernel/image.itb
9870 23:42:48.067417
9871 23:42:48.070500 Sending tftp read request... done.
9872 23:42:48.070669
9873 23:42:48.074465 Waiting for the transfer...
9874 23:42:48.074679
9875 23:42:48.476414 00000000 ################################################################
9876 23:42:48.476563
9877 23:42:48.762121 00080000 ################################################################
9878 23:42:48.762272
9879 23:42:49.056672 00100000 ################################################################
9880 23:42:49.056839
9881 23:42:49.352446 00180000 ################################################################
9882 23:42:49.352584
9883 23:42:49.651803 00200000 ################################################################
9884 23:42:49.651979
9885 23:42:49.949183 00280000 ################################################################
9886 23:42:49.949335
9887 23:42:50.246489 00300000 ################################################################
9888 23:42:50.246634
9889 23:42:50.541758 00380000 ################################################################
9890 23:42:50.541896
9891 23:42:50.838088 00400000 ################################################################
9892 23:42:50.838258
9893 23:42:51.120950 00480000 ################################################################
9894 23:42:51.121131
9895 23:42:51.388023 00500000 ################################################################
9896 23:42:51.388174
9897 23:42:51.651244 00580000 ################################################################
9898 23:42:51.651381
9899 23:42:51.931214 00600000 ################################################################
9900 23:42:51.931356
9901 23:42:52.221030 00680000 ################################################################
9902 23:42:52.221183
9903 23:42:52.484234 00700000 ################################################################
9904 23:42:52.484382
9905 23:42:52.756181 00780000 ################################################################
9906 23:42:52.756320
9907 23:42:53.024794 00800000 ################################################################
9908 23:42:53.024932
9909 23:42:53.321599 00880000 ################################################################
9910 23:42:53.321741
9911 23:42:53.589230 00900000 ################################################################
9912 23:42:53.589392
9913 23:42:53.886426 00980000 ################################################################
9914 23:42:53.886620
9915 23:42:54.182880 00a00000 ################################################################
9916 23:42:54.183021
9917 23:42:54.478420 00a80000 ################################################################
9918 23:42:54.478556
9919 23:42:54.740372 00b00000 ################################################################
9920 23:42:54.740510
9921 23:42:54.997255 00b80000 ################################################################
9922 23:42:54.997401
9923 23:42:55.278612 00c00000 ################################################################
9924 23:42:55.278759
9925 23:42:55.578631 00c80000 ################################################################
9926 23:42:55.578773
9927 23:42:55.868199 00d00000 ################################################################
9928 23:42:55.868336
9929 23:42:56.169036 00d80000 ################################################################
9930 23:42:56.169219
9931 23:42:56.466479 00e00000 ################################################################
9932 23:42:56.466626
9933 23:42:56.768089 00e80000 ################################################################
9934 23:42:56.768231
9935 23:42:57.040115 00f00000 ################################################################
9936 23:42:57.040271
9937 23:42:57.334654 00f80000 ################################################################
9938 23:42:57.334795
9939 23:42:57.624096 01000000 ################################################################
9940 23:42:57.624257
9941 23:42:57.921246 01080000 ################################################################
9942 23:42:57.921419
9943 23:42:58.212567 01100000 ################################################################
9944 23:42:58.212716
9945 23:42:58.513816 01180000 ################################################################
9946 23:42:58.513955
9947 23:42:58.813633 01200000 ################################################################
9948 23:42:58.813773
9949 23:42:59.114093 01280000 ################################################################
9950 23:42:59.114231
9951 23:42:59.409294 01300000 ################################################################
9952 23:42:59.409450
9953 23:42:59.707366 01380000 ################################################################
9954 23:42:59.707534
9955 23:42:59.990504 01400000 ################################################################
9956 23:42:59.990668
9957 23:43:00.273557 01480000 ################################################################
9958 23:43:00.273697
9959 23:43:00.552517 01500000 ################################################################
9960 23:43:00.552667
9961 23:43:00.835699 01580000 ################################################################
9962 23:43:00.835867
9963 23:43:01.133904 01600000 ################################################################
9964 23:43:01.134049
9965 23:43:01.435309 01680000 ################################################################
9966 23:43:01.435446
9967 23:43:01.724293 01700000 ################################################################
9968 23:43:01.724436
9969 23:43:01.999247 01780000 ################################################################
9970 23:43:01.999386
9971 23:43:02.296050 01800000 ################################################################
9972 23:43:02.296189
9973 23:43:02.591128 01880000 ################################################################
9974 23:43:02.591266
9975 23:43:02.885297 01900000 ################################################################
9976 23:43:02.885446
9977 23:43:03.180820 01980000 ################################################################
9978 23:43:03.180962
9979 23:43:03.482396 01a00000 ################################################################
9980 23:43:03.482536
9981 23:43:03.785829 01a80000 ################################################################
9982 23:43:03.785969
9983 23:43:04.084204 01b00000 ################################################################
9984 23:43:04.084352
9985 23:43:04.383256 01b80000 ################################################################
9986 23:43:04.383401
9987 23:43:04.683697 01c00000 ################################################################
9988 23:43:04.683849
9989 23:43:04.983171 01c80000 ################################################################
9990 23:43:04.983312
9991 23:43:05.277954 01d00000 ################################################################
9992 23:43:05.278099
9993 23:43:05.570404 01d80000 ################################################################
9994 23:43:05.570555
9995 23:43:05.782765 01e00000 ############################################### done.
9996 23:43:05.782896
9997 23:43:05.785964 The bootfile was 31840834 bytes long.
9998 23:43:05.786055
9999 23:43:05.789054 Sending tftp read request... done.
10000 23:43:05.789150
10001 23:43:05.789226 Waiting for the transfer...
10002 23:43:05.789306
10003 23:43:05.792626 00000000 # done.
10004 23:43:05.792723
10005 23:43:05.799012 Command line loaded dynamically from TFTP file: 14172914/tftp-deploy-758tthvv/kernel/cmdline
10006 23:43:05.799207
10007 23:43:05.822622 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172914/extract-nfsrootfs-98qg8u54,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10008 23:43:05.823217
10009 23:43:05.823593 Loading FIT.
10010 23:43:05.823944
10011 23:43:05.825807 Image ramdisk-1 has 18730110 bytes.
10012 23:43:05.826280
10013 23:43:05.829254 Image fdt-1 has 47258 bytes.
10014 23:43:05.829754
10015 23:43:05.832341 Image kernel-1 has 13061430 bytes.
10016 23:43:05.832829
10017 23:43:05.842574 Compat preference: google,spherion-rev7-sku1 google,spherion-rev7 google,spherion-sku1 google,spherion
10018 23:43:05.843172
10019 23:43:05.859126 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion (match) mediatek,mt8192
10020 23:43:05.859755
10021 23:43:05.865471 Choosing best match conf-1 for compat google,spherion.
10022 23:43:05.866050
10023 23:43:05.873036 Connected to device vid:did:rid of 1ae0:0028:00
10024 23:43:05.879924
10025 23:43:05.883226 tpm_get_response: command 0x17b, return code 0x0
10026 23:43:05.883728
10027 23:43:05.886463 ec_init: CrosEC protocol v3 supported (256, 248)
10028 23:43:05.890560
10029 23:43:05.893937 tpm_cleanup: add release locality here.
10030 23:43:05.894534
10031 23:43:05.895035 Shutting down all USB controllers.
10032 23:43:05.897146
10033 23:43:05.897665 Removing current net device
10034 23:43:05.898149
10035 23:43:05.904093 Exiting depthcharge with code 4 at timestamp: 50899138
10036 23:43:05.904681
10037 23:43:05.906963 LZMA decompressing kernel-1 to 0x821a6718
10038 23:43:05.907447
10039 23:43:05.910674 LZMA decompressing kernel-1 to 0x40000000
10040 23:43:07.519086
10041 23:43:07.519667 jumping to kernel
10042 23:43:07.521572 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10043 23:43:07.522181 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10044 23:43:07.522651 Setting prompt string to ['Linux version [0-9]']
10045 23:43:07.523122 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10046 23:43:07.523591 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10047 23:43:07.569884
10048 23:43:07.572934 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10049 23:43:07.576692 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10050 23:43:07.577375 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10051 23:43:07.577868 Setting prompt string to []
10052 23:43:07.578545 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10053 23:43:07.579047 Using line separator: #'\n'#
10054 23:43:07.579467 No login prompt set.
10055 23:43:07.579935 Parsing kernel messages
10056 23:43:07.580353 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10057 23:43:07.581057 [login-action] Waiting for messages, (timeout 00:04:02)
10058 23:43:07.581631 Waiting using forced prompt support (timeout 00:02:01)
10059 23:43:07.595802 [ 0.000000] Linux version 6.1.92-cip22 (KernelCI@build-j217067-arm64-gcc-10-defconfig-arm64-chromebook-s48tj) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024
10060 23:43:07.599124 [ 0.000000] random: crng init done
10061 23:43:07.605910 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10062 23:43:07.609029 [ 0.000000] efi: UEFI not found.
10063 23:43:07.615771 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10064 23:43:07.622394 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10065 23:43:07.632212 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10066 23:43:07.642026 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10067 23:43:07.648535 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10068 23:43:07.655399 [ 0.000000] printk: bootconsole [mtk8250] enabled
10069 23:43:07.661844 [ 0.000000] NUMA: No NUMA configuration found
10070 23:43:07.668419 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10071 23:43:07.672291 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d5a00-0x13f7d7fff]
10072 23:43:07.674868 [ 0.000000] Zone ranges:
10073 23:43:07.682388 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10074 23:43:07.685120 [ 0.000000] DMA32 empty
10075 23:43:07.691543 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10076 23:43:07.694713 [ 0.000000] Movable zone start for each node
10077 23:43:07.698085 [ 0.000000] Early memory node ranges
10078 23:43:07.704883 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10079 23:43:07.711540 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10080 23:43:07.718488 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10081 23:43:07.724572 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10082 23:43:07.730914 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10083 23:43:07.737675 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10084 23:43:07.768189 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10085 23:43:07.774892 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10086 23:43:07.781675 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10087 23:43:07.785108 [ 0.000000] psci: probing for conduit method from DT.
10088 23:43:07.791652 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10089 23:43:07.794749 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10090 23:43:07.801462 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10091 23:43:07.804947 [ 0.000000] psci: SMC Calling Convention v1.2
10092 23:43:07.811604 [ 0.000000] percpu: Embedded 21 pages/cpu s48296 r8192 d29528 u86016
10093 23:43:07.814790 [ 0.000000] Detected VIPT I-cache on CPU0
10094 23:43:07.821437 [ 0.000000] CPU features: detected: GIC system register CPU interface
10095 23:43:07.827896 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10096 23:43:07.834333 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10097 23:43:07.840851 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10098 23:43:07.850564 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10099 23:43:07.857508 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10100 23:43:07.860419 [ 0.000000] alternatives: applying boot alternatives
10101 23:43:07.867385 [ 0.000000] Fallback order for Node 0: 0
10102 23:43:07.874254 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10103 23:43:07.877087 [ 0.000000] Policy zone: Normal
10104 23:43:07.900471 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/14172914/extract-nfsrootfs-98qg8u54,tcp,hard,v3 ip=dhcp tftpserverip=192.168.201.1
10105 23:43:07.910189 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10106 23:43:07.920424 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10107 23:43:07.930046 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10108 23:43:07.936522 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10109 23:43:07.940044 <6>[ 0.000000] software IO TLB: area num 8.
10110 23:43:07.995355 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10111 23:43:08.076196 <6>[ 0.000000] Memory: 3831484K/4191232K available (18112K kernel code, 4120K rwdata, 22504K rodata, 8512K init, 616K bss, 326980K reserved, 32768K cma-reserved)
10112 23:43:08.082265 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10113 23:43:08.088966 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10114 23:43:08.092445 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10115 23:43:08.099429 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10116 23:43:08.105887 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10117 23:43:08.108904 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10118 23:43:08.118901 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10119 23:43:08.125654 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10120 23:43:08.132253 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10121 23:43:08.138604 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10122 23:43:08.142054 <6>[ 0.000000] GICv3: 608 SPIs implemented
10123 23:43:08.145217 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10124 23:43:08.151927 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10125 23:43:08.155148 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10126 23:43:08.161517 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10127 23:43:08.175082 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10128 23:43:08.187964 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10129 23:43:08.194266 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10130 23:43:08.202606 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10131 23:43:08.216074 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10132 23:43:08.222432 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10133 23:43:08.229429 <6>[ 0.009231] Console: colour dummy device 80x25
10134 23:43:08.238846 <6>[ 0.013957] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10135 23:43:08.245380 <6>[ 0.024442] pid_max: default: 32768 minimum: 301
10136 23:43:08.249021 <6>[ 0.029314] LSM: Security Framework initializing
10137 23:43:08.255572 <6>[ 0.034225] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10138 23:43:08.265339 <6>[ 0.041880] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10139 23:43:08.272264 <6>[ 0.051122] cblist_init_generic: Setting adjustable number of callback queues.
10140 23:43:08.278684 <6>[ 0.058567] cblist_init_generic: Setting shift to 3 and lim to 1.
10141 23:43:08.288505 <6>[ 0.064906] cblist_init_generic: Setting adjustable number of callback queues.
10142 23:43:08.291738 <6>[ 0.072334] cblist_init_generic: Setting shift to 3 and lim to 1.
10143 23:43:08.298789 <6>[ 0.078735] rcu: Hierarchical SRCU implementation.
10144 23:43:08.305158 <6>[ 0.083750] rcu: Max phase no-delay instances is 1000.
10145 23:43:08.311967 <6>[ 0.090785] EFI services will not be available.
10146 23:43:08.314922 <6>[ 0.095743] smp: Bringing up secondary CPUs ...
10147 23:43:08.322887 <6>[ 0.100790] Detected VIPT I-cache on CPU1
10148 23:43:08.329598 <6>[ 0.100860] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10149 23:43:08.336157 <6>[ 0.100891] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10150 23:43:08.339145 <6>[ 0.101220] Detected VIPT I-cache on CPU2
10151 23:43:08.349559 <6>[ 0.101272] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10152 23:43:08.356162 <6>[ 0.101288] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10153 23:43:08.359449 <6>[ 0.101544] Detected VIPT I-cache on CPU3
10154 23:43:08.365987 <6>[ 0.101590] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10155 23:43:08.372685 <6>[ 0.101603] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10156 23:43:08.375846 <6>[ 0.101906] CPU features: detected: Spectre-v4
10157 23:43:08.382371 <6>[ 0.101912] CPU features: detected: Spectre-BHB
10158 23:43:08.385617 <6>[ 0.101917] Detected PIPT I-cache on CPU4
10159 23:43:08.392054 <6>[ 0.101977] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10160 23:43:08.398873 <6>[ 0.101993] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10161 23:43:08.405738 <6>[ 0.102286] Detected PIPT I-cache on CPU5
10162 23:43:08.412106 <6>[ 0.102348] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10163 23:43:08.418440 <6>[ 0.102364] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10164 23:43:08.421874 <6>[ 0.102641] Detected PIPT I-cache on CPU6
10165 23:43:08.428464 <6>[ 0.102702] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10166 23:43:08.435295 <6>[ 0.102718] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10167 23:43:08.441564 <6>[ 0.103011] Detected PIPT I-cache on CPU7
10168 23:43:08.448213 <6>[ 0.103070] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10169 23:43:08.455105 <6>[ 0.103086] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10170 23:43:08.458356 <6>[ 0.103133] smp: Brought up 1 node, 8 CPUs
10171 23:43:08.465031 <6>[ 0.244532] SMP: Total of 8 processors activated.
10172 23:43:08.468423 <6>[ 0.249453] CPU features: detected: 32-bit EL0 Support
10173 23:43:08.478218 <6>[ 0.254816] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10174 23:43:08.484911 <6>[ 0.263617] CPU features: detected: Common not Private translations
10175 23:43:08.491745 <6>[ 0.270133] CPU features: detected: CRC32 instructions
10176 23:43:08.497828 <6>[ 0.275517] CPU features: detected: RCpc load-acquire (LDAPR)
10177 23:43:08.501358 <6>[ 0.281478] CPU features: detected: LSE atomic instructions
10178 23:43:08.507669 <6>[ 0.287259] CPU features: detected: Privileged Access Never
10179 23:43:08.514181 <6>[ 0.293075] CPU features: detected: RAS Extension Support
10180 23:43:08.520901 <6>[ 0.298718] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10181 23:43:08.524086 <6>[ 0.305938] CPU: All CPU(s) started at EL2
10182 23:43:08.530939 <6>[ 0.310255] alternatives: applying system-wide alternatives
10183 23:43:08.539860 <6>[ 0.320251] devtmpfs: initialized
10184 23:43:08.555017 <6>[ 0.328436] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10185 23:43:08.561449 <6>[ 0.338396] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10186 23:43:08.568318 <6>[ 0.346430] pinctrl core: initialized pinctrl subsystem
10187 23:43:08.571340 <6>[ 0.353104] DMI not present or invalid.
10188 23:43:08.578107 <6>[ 0.357505] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10189 23:43:08.587874 <6>[ 0.364339] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10190 23:43:08.595192 <6>[ 0.371789] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10191 23:43:08.604361 <6>[ 0.379884] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10192 23:43:08.607947 <6>[ 0.388040] audit: initializing netlink subsys (disabled)
10193 23:43:08.617944 <5>[ 0.393735] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10194 23:43:08.624148 <6>[ 0.394445] thermal_sys: Registered thermal governor 'step_wise'
10195 23:43:08.630906 <6>[ 0.401701] thermal_sys: Registered thermal governor 'power_allocator'
10196 23:43:08.634102 <6>[ 0.407959] cpuidle: using governor menu
10197 23:43:08.640605 <6>[ 0.418917] NET: Registered PF_QIPCRTR protocol family
10198 23:43:08.647168 <6>[ 0.424402] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10199 23:43:08.650533 <6>[ 0.431508] ASID allocator initialised with 32768 entries
10200 23:43:08.657674 <6>[ 0.438071] Serial: AMBA PL011 UART driver
10201 23:43:08.666602 <4>[ 0.446919] Trying to register duplicate clock ID: 134
10202 23:43:08.724651 <6>[ 0.508372] KASLR enabled
10203 23:43:08.738866 <6>[ 0.516058] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10204 23:43:08.745538 <6>[ 0.523073] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10205 23:43:08.752187 <6>[ 0.529562] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10206 23:43:08.758790 <6>[ 0.536564] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10207 23:43:08.765268 <6>[ 0.543054] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10208 23:43:08.771800 <6>[ 0.550055] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10209 23:43:08.778430 <6>[ 0.556545] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10210 23:43:08.784991 <6>[ 0.563547] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10211 23:43:08.788417 <6>[ 0.571059] ACPI: Interpreter disabled.
10212 23:43:08.797043 <6>[ 0.577479] iommu: Default domain type: Translated
10213 23:43:08.803526 <6>[ 0.582588] iommu: DMA domain TLB invalidation policy: strict mode
10214 23:43:08.807206 <5>[ 0.589221] SCSI subsystem initialized
10215 23:43:08.813761 <6>[ 0.593381] usbcore: registered new interface driver usbfs
10216 23:43:08.820523 <6>[ 0.599111] usbcore: registered new interface driver hub
10217 23:43:08.823535 <6>[ 0.604659] usbcore: registered new device driver usb
10218 23:43:08.830374 <6>[ 0.610751] pps_core: LinuxPPS API ver. 1 registered
10219 23:43:08.840131 <6>[ 0.615943] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10220 23:43:08.843627 <6>[ 0.625287] PTP clock support registered
10221 23:43:08.846892 <6>[ 0.629529] EDAC MC: Ver: 3.0.0
10222 23:43:08.854498 <6>[ 0.634683] FPGA manager framework
10223 23:43:08.861050 <6>[ 0.638369] Advanced Linux Sound Architecture Driver Initialized.
10224 23:43:08.864252 <6>[ 0.645138] vgaarb: loaded
10225 23:43:08.870783 <6>[ 0.648301] clocksource: Switched to clocksource arch_sys_counter
10226 23:43:08.874173 <5>[ 0.654744] VFS: Disk quotas dquot_6.6.0
10227 23:43:08.880739 <6>[ 0.658931] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10228 23:43:08.884025 <6>[ 0.666118] pnp: PnP ACPI: disabled
10229 23:43:08.892316 <6>[ 0.672795] NET: Registered PF_INET protocol family
10230 23:43:08.899183 <6>[ 0.678189] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10231 23:43:08.911616 <6>[ 0.688219] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10232 23:43:08.921508 <6>[ 0.697011] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10233 23:43:08.927839 <6>[ 0.704977] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10234 23:43:08.934593 <6>[ 0.713376] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10235 23:43:08.945080 <6>[ 0.722026] TCP: Hash tables configured (established 32768 bind 32768)
10236 23:43:08.951664 <6>[ 0.728887] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10237 23:43:08.958268 <6>[ 0.735908] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10238 23:43:08.964669 <6>[ 0.743431] NET: Registered PF_UNIX/PF_LOCAL protocol family
10239 23:43:08.971442 <6>[ 0.749505] RPC: Registered named UNIX socket transport module.
10240 23:43:08.975078 <6>[ 0.755654] RPC: Registered udp transport module.
10241 23:43:08.981130 <6>[ 0.760587] RPC: Registered tcp transport module.
10242 23:43:08.987851 <6>[ 0.765519] RPC: Registered tcp NFSv4.1 backchannel transport module.
10243 23:43:08.991755 <6>[ 0.772184] PCI: CLS 0 bytes, default 64
10244 23:43:08.994714 <6>[ 0.776606] Unpacking initramfs...
10245 23:43:09.004568 <6>[ 0.780334] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10246 23:43:09.010830 <6>[ 0.789006] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10247 23:43:09.017974 <6>[ 0.797823] kvm [1]: IPA Size Limit: 40 bits
10248 23:43:09.020868 <6>[ 0.802355] kvm [1]: GICv3: no GICV resource entry
10249 23:43:09.027526 <6>[ 0.807374] kvm [1]: disabling GICv2 emulation
10250 23:43:09.034211 <6>[ 0.812058] kvm [1]: GIC system register CPU interface enabled
10251 23:43:09.037432 <6>[ 0.818221] kvm [1]: vgic interrupt IRQ18
10252 23:43:09.043619 <6>[ 0.822585] kvm [1]: VHE mode initialized successfully
10253 23:43:09.046991 <5>[ 0.828973] Initialise system trusted keyrings
10254 23:43:09.053760 <6>[ 0.833788] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10255 23:43:09.063739 <6>[ 0.843960] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10256 23:43:09.070216 <5>[ 0.850339] NFS: Registering the id_resolver key type
10257 23:43:09.073732 <5>[ 0.855635] Key type id_resolver registered
10258 23:43:09.080287 <5>[ 0.860051] Key type id_legacy registered
10259 23:43:09.086774 <6>[ 0.864342] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10260 23:43:09.093193 <6>[ 0.871261] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10261 23:43:09.099585 <6>[ 0.878972] 9p: Installing v9fs 9p2000 file system support
10262 23:43:09.136586 <5>[ 0.916811] Key type asymmetric registered
10263 23:43:09.139975 <5>[ 0.921143] Asymmetric key parser 'x509' registered
10264 23:43:09.149586 <6>[ 0.926284] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10265 23:43:09.153028 <6>[ 0.933894] io scheduler mq-deadline registered
10266 23:43:09.156310 <6>[ 0.938655] io scheduler kyber registered
10267 23:43:09.175754 <6>[ 0.955775] EINJ: ACPI disabled.
10268 23:43:09.208873 <4>[ 0.981890] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10269 23:43:09.218150 <4>[ 0.992511] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10270 23:43:09.233486 <6>[ 1.013612] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10271 23:43:09.241360 <6>[ 1.021698] printk: console [ttyS0] disabled
10272 23:43:09.269700 <6>[ 1.046328] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10273 23:43:09.276274 <6>[ 1.055809] printk: console [ttyS0] enabled
10274 23:43:09.279410 <6>[ 1.055809] printk: console [ttyS0] enabled
10275 23:43:09.285838 <6>[ 1.064706] printk: bootconsole [mtk8250] disabled
10276 23:43:09.289450 <6>[ 1.064706] printk: bootconsole [mtk8250] disabled
10277 23:43:09.295722 <6>[ 1.075818] SuperH (H)SCI(F) driver initialized
10278 23:43:09.298965 <6>[ 1.081092] msm_serial: driver initialized
10279 23:43:09.313521 <6>[ 1.090101] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10280 23:43:09.322957 <6>[ 1.098659] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10281 23:43:09.329856 <6>[ 1.107201] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10282 23:43:09.339617 <6>[ 1.115829] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10283 23:43:09.349695 <6>[ 1.124536] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10284 23:43:09.356326 <6>[ 1.133251] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10285 23:43:09.365932 <6>[ 1.141793] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10286 23:43:09.373177 <6>[ 1.150602] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10287 23:43:09.382411 <6>[ 1.159145] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10288 23:43:09.394614 <6>[ 1.174841] loop: module loaded
10289 23:43:09.401599 <6>[ 1.180760] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10290 23:43:09.424364 <4>[ 1.204203] mtk-pmic-keys: Failed to locate of_node [id: -1]
10291 23:43:09.430976 <6>[ 1.211302] megasas: 07.719.03.00-rc1
10292 23:43:09.440843 <6>[ 1.221194] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10293 23:43:09.447249 <6>[ 1.227705] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10294 23:43:09.464248 <6>[ 1.244273] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10295 23:43:09.520034 <6>[ 1.293642] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10296 23:43:09.782409 <6>[ 1.562689] Freeing initrd memory: 18288K
10297 23:43:09.794100 <6>[ 1.574433] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10298 23:43:09.805225 <6>[ 1.585488] tun: Universal TUN/TAP device driver, 1.6
10299 23:43:09.808642 <6>[ 1.591548] thunder_xcv, ver 1.0
10300 23:43:09.811873 <6>[ 1.595053] thunder_bgx, ver 1.0
10301 23:43:09.815300 <6>[ 1.598548] nicpf, ver 1.0
10302 23:43:09.825266 <6>[ 1.602574] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10303 23:43:09.828771 <6>[ 1.610050] hns3: Copyright (c) 2017 Huawei Corporation.
10304 23:43:09.835396 <6>[ 1.615637] hclge is initializing
10305 23:43:09.838503 <6>[ 1.619217] e1000: Intel(R) PRO/1000 Network Driver
10306 23:43:09.845181 <6>[ 1.624345] e1000: Copyright (c) 1999-2006 Intel Corporation.
10307 23:43:09.851663 <6>[ 1.630359] e1000e: Intel(R) PRO/1000 Network Driver
10308 23:43:09.854817 <6>[ 1.635574] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10309 23:43:09.861703 <6>[ 1.641759] igb: Intel(R) Gigabit Ethernet Network Driver
10310 23:43:09.868070 <6>[ 1.647409] igb: Copyright (c) 2007-2014 Intel Corporation.
10311 23:43:09.874858 <6>[ 1.653258] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10312 23:43:09.881670 <6>[ 1.659776] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10313 23:43:09.884763 <6>[ 1.666235] sky2: driver version 1.30
10314 23:43:09.891949 <6>[ 1.671164] usbcore: registered new device driver r8152-cfgselector
10315 23:43:09.898172 <6>[ 1.677698] usbcore: registered new interface driver r8152
10316 23:43:09.904821 <6>[ 1.683512] VFIO - User Level meta-driver version: 0.3
10317 23:43:09.911801 <6>[ 1.691707] usbcore: registered new interface driver usb-storage
10318 23:43:09.917992 <6>[ 1.698151] usbcore: registered new device driver onboard-usb-hub
10319 23:43:09.926810 <6>[ 1.707315] mt6397-rtc mt6359-rtc: registered as rtc0
10320 23:43:09.936855 <6>[ 1.712776] mt6397-rtc mt6359-rtc: setting system clock to 2024-06-04T23:43:11 UTC (1717544591)
10321 23:43:09.939979 <6>[ 1.722343] i2c_dev: i2c /dev entries driver
10322 23:43:09.957269 <6>[ 1.734130] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10323 23:43:09.964002 <4>[ 1.742856] cpu cpu0: supply cpu not found, using dummy regulator
10324 23:43:09.970501 <4>[ 1.749292] cpu cpu1: supply cpu not found, using dummy regulator
10325 23:43:09.977156 <4>[ 1.755694] cpu cpu2: supply cpu not found, using dummy regulator
10326 23:43:09.983612 <4>[ 1.762089] cpu cpu3: supply cpu not found, using dummy regulator
10327 23:43:09.990276 <4>[ 1.768481] cpu cpu4: supply cpu not found, using dummy regulator
10328 23:43:09.996970 <4>[ 1.774880] cpu cpu5: supply cpu not found, using dummy regulator
10329 23:43:10.003793 <4>[ 1.781288] cpu cpu6: supply cpu not found, using dummy regulator
10330 23:43:10.010181 <4>[ 1.787681] cpu cpu7: supply cpu not found, using dummy regulator
10331 23:43:10.028017 <6>[ 1.808299] cpu cpu0: EM: created perf domain
10332 23:43:10.031037 <6>[ 1.813212] cpu cpu4: EM: created perf domain
10333 23:43:10.038257 <6>[ 1.818787] sdhci: Secure Digital Host Controller Interface driver
10334 23:43:10.044987 <6>[ 1.825219] sdhci: Copyright(c) Pierre Ossman
10335 23:43:10.051775 <6>[ 1.830131] Synopsys Designware Multimedia Card Interface Driver
10336 23:43:10.058246 <6>[ 1.836732] sdhci-pltfm: SDHCI platform and OF driver helper
10337 23:43:10.061327 <6>[ 1.836816] mmc0: CQHCI version 5.10
10338 23:43:10.068340 <6>[ 1.846817] ledtrig-cpu: registered to indicate activity on CPUs
10339 23:43:10.074858 <6>[ 1.853897] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10340 23:43:10.081645 <6>[ 1.860933] usbcore: registered new interface driver usbhid
10341 23:43:10.084544 <6>[ 1.866754] usbhid: USB HID core driver
10342 23:43:10.091539 <6>[ 1.870948] spi_master spi0: will run message pump with realtime priority
10343 23:43:10.135053 <6>[ 1.908659] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10344 23:43:10.154373 <6>[ 1.924839] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10345 23:43:10.157800 <3>[ 1.931238] mtk-msdc 11f60000.mmc: phase error: [map:0]
10346 23:43:10.164628 <3>[ 1.943744] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10347 23:43:10.171631 <3>[ 1.949666] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10348 23:43:10.174701 <3>[ 1.956021] mmc0: error -5 whilst initialising MMC card
10349 23:43:10.181112 <6>[ 1.956141] cros-ec-spi spi0.0: Chrome EC device registered
10350 23:43:10.202773 <6>[ 1.979763] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10351 23:43:10.209761 <6>[ 1.990024] NET: Registered PF_PACKET protocol family
10352 23:43:10.213202 <6>[ 1.995410] 9pnet: Installing 9P2000 support
10353 23:43:10.219768 <5>[ 1.999969] Key type dns_resolver registered
10354 23:43:10.223063 <6>[ 2.004945] registered taskstats version 1
10355 23:43:10.229586 <5>[ 2.009320] Loading compiled-in X.509 certificates
10356 23:43:10.256708 <4>[ 2.030443] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10357 23:43:10.266604 <4>[ 2.041184] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10358 23:43:10.284670 <6>[ 2.064989] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10359 23:43:10.291376 <6>[ 2.071952] xhci-mtk 11200000.usb: xHCI Host Controller
10360 23:43:10.297967 <6>[ 2.077452] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10361 23:43:10.304803 <3>[ 2.080387] mtk-msdc 11f60000.mmc: phase error: [map:0]
10362 23:43:10.314790 <6>[ 2.085290] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10363 23:43:10.321368 <3>[ 2.090578] mtk-msdc 11f60000.mmc: Failed to get DLY1 delay!
10364 23:43:10.328018 <6>[ 2.099991] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10365 23:43:10.331319 <3>[ 2.105868] mtk-msdc 11f60000.mmc: Failed to tuning DS pin delay!
10366 23:43:10.337937 <6>[ 2.111924] xhci-mtk 11200000.usb: xHCI Host Controller
10367 23:43:10.344368 <3>[ 2.118207] mmc0: error -5 whilst initialising MMC card
10368 23:43:10.350937 <6>[ 2.123677] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10369 23:43:10.357827 <6>[ 2.136799] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10370 23:43:10.364356 <6>[ 2.144521] hub 1-0:1.0: USB hub found
10371 23:43:10.367487 <6>[ 2.148537] hub 1-0:1.0: 1 port detected
10372 23:43:10.374246 <6>[ 2.152812] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10373 23:43:10.380957 <6>[ 2.161342] hub 2-0:1.0: USB hub found
10374 23:43:10.384068 <6>[ 2.165345] hub 2-0:1.0: 1 port detected
10375 23:43:10.391762 <6>[ 2.172177] mtk-msdc 11f70000.mmc: Got CD GPIO
10376 23:43:10.407862 <6>[ 2.185271] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10377 23:43:10.414950 <6>[ 2.193296] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10378 23:43:10.424701 <4>[ 2.201184] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10379 23:43:10.434634 <6>[ 2.210710] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10380 23:43:10.441403 <6>[ 2.218787] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10381 23:43:10.447850 <6>[ 2.226893] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10382 23:43:10.457789 <6>[ 2.234821] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10383 23:43:10.464560 <6>[ 2.240173] mtk-msdc 11f60000.mmc: Final PAD_DS_TUNE: 0x16c14
10384 23:43:10.471465 <6>[ 2.242699] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10385 23:43:10.481134 <6>[ 2.256485] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10386 23:43:10.484268 <6>[ 2.256653] mmc0: Command Queue Engine enabled
10387 23:43:10.494175 <6>[ 2.267001] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10388 23:43:10.501185 <6>[ 2.270356] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10389 23:43:10.507402 <6>[ 2.278709] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10390 23:43:10.517488 <6>[ 2.278713] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10391 23:43:10.524453 <6>[ 2.278715] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10392 23:43:10.530829 <6>[ 2.286138] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10393 23:43:10.537263 <6>[ 2.293663] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10394 23:43:10.547483 <6>[ 2.293667] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10395 23:43:10.553605 <6>[ 2.293670] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10396 23:43:10.560531 <6>[ 2.306034] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10397 23:43:10.570390 <6>[ 2.310352] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10398 23:43:10.576998 <6>[ 2.310356] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10399 23:43:10.583340 <6>[ 2.316464] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10400 23:43:10.590160 <6>[ 2.323470] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10401 23:43:10.600251 <6>[ 2.323473] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10402 23:43:10.606691 <6>[ 2.323476] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10403 23:43:10.613384 <6>[ 2.332382] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10404 23:43:10.620229 <6>[ 2.340157] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10405 23:43:10.626640 <6>[ 2.346651] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10406 23:43:10.636307 <6>[ 2.354398] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10407 23:43:10.643049 <6>[ 2.354402] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10408 23:43:10.649789 <6>[ 2.355428] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10409 23:43:10.656773 <6>[ 2.437512] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10410 23:43:10.664214 <6>[ 2.444638] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10411 23:43:10.674255 <6>[ 2.451498] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10412 23:43:10.680877 <6>[ 2.458424] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10413 23:43:10.687534 <6>[ 2.465259] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10414 23:43:10.697225 <6>[ 2.474389] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10415 23:43:10.707197 <6>[ 2.483516] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10416 23:43:10.717499 <6>[ 2.492810] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10417 23:43:10.727075 <6>[ 2.502280] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10418 23:43:10.737250 <6>[ 2.511746] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10419 23:43:10.743785 <6>[ 2.520865] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10420 23:43:10.753447 <6>[ 2.530333] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10421 23:43:10.763446 <6>[ 2.539452] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10422 23:43:10.773559 <6>[ 2.548745] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10423 23:43:10.779925 <6>[ 2.552634] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10424 23:43:10.789730 <6>[ 2.558905] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10425 23:43:10.799641 <6>[ 2.560651] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10426 23:43:10.806409 <6>[ 2.585447] Trying to probe devices needed for running init ...
10427 23:43:10.809768 <6>[ 2.591931] hub 2-1:1.0: USB hub found
10428 23:43:10.815985 <6>[ 2.596403] hub 2-1:1.0: 3 ports detected
10429 23:43:10.823457 <6>[ 2.603844] hub 2-1:1.0: USB hub found
10430 23:43:10.826755 <6>[ 2.608204] hub 2-1:1.0: 3 ports detected
10431 23:43:10.934958 <6>[ 2.712498] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10432 23:43:11.090762 <6>[ 2.870961] hub 1-1:1.0: USB hub found
10433 23:43:11.093851 <6>[ 2.875497] hub 1-1:1.0: 4 ports detected
10434 23:43:11.103154 <6>[ 2.883729] hub 1-1:1.0: USB hub found
10435 23:43:11.106423 <6>[ 2.888089] hub 1-1:1.0: 4 ports detected
10436 23:43:11.167686 <6>[ 2.944883] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10437 23:43:11.275793 <6>[ 3.052971] r8152-cfgselector 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10438 23:43:11.313605 <4>[ 3.090425] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10439 23:43:11.323017 <4>[ 3.099507] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10440 23:43:11.370012 <6>[ 3.150609] r8152 2-1.3:1.0 eth0: v1.12.13
10441 23:43:11.427246 <6>[ 3.204570] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10442 23:43:11.559846 <6>[ 3.340471] hub 1-1.4:1.0: USB hub found
10443 23:43:11.563384 <6>[ 3.345130] hub 1-1.4:1.0: 2 ports detected
10444 23:43:11.572920 <6>[ 3.353263] hub 1-1.4:1.0: USB hub found
10445 23:43:11.576067 <6>[ 3.357938] hub 1-1.4:1.0: 2 ports detected
10446 23:43:11.871051 <6>[ 3.648463] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10447 23:43:12.058973 <6>[ 3.836613] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10448 23:43:13.072314 <6>[ 4.852996] r8152 2-1.3:1.0 eth0: carrier on
10449 23:43:15.931621 <5>[ 4.880413] Sending DHCP requests .., OK
10450 23:43:15.938035 <6>[ 7.716756] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.16
10451 23:43:15.941513 <6>[ 7.725038] IP-Config: Complete:
10452 23:43:15.954543 <6>[ 7.728535] device=eth0, hwaddr=00:e0:4c:68:03:bd, ipaddr=192.168.201.16, mask=255.255.255.0, gw=192.168.201.1
10453 23:43:15.961170 <6>[ 7.739244] host=mt8192-asurada-spherion-r0-cbg-4, domain=lava-rack, nis-domain=(none)
10454 23:43:15.967849 <6>[ 7.747862] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath=
10455 23:43:15.974467 <6>[ 7.747871] nameserver0=192.168.201.1
10456 23:43:15.977869 <6>[ 7.760029] clk: Disabling unused clocks
10457 23:43:15.981040 <6>[ 7.765516] ALSA device list:
10458 23:43:15.987439 <6>[ 7.768796] No soundcards found.
10459 23:43:15.995383 <6>[ 7.776462] Freeing unused kernel memory: 8512K
10460 23:43:15.998601 <6>[ 7.781367] Run /init as init process
10461 23:43:16.007805 Loading, please wait...
10462 23:43:16.036593 Starting systemd-udevd version 252.22-1~deb12u1
10463 23:43:16.246228 <6>[ 8.024131] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10464 23:43:16.260760 <6>[ 8.038491] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10465 23:43:16.267467 <6>[ 8.046250] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10466 23:43:16.277410 <6>[ 8.055258] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10467 23:43:16.288463 <6>[ 8.069580] remoteproc remoteproc0: scp is available
10468 23:43:16.295244 <6>[ 8.076221] remoteproc remoteproc0: powering up scp
10469 23:43:16.304847 <6>[ 8.081386] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10470 23:43:16.311842 <3>[ 8.084754] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10471 23:43:16.318040 <6>[ 8.089875] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10472 23:43:16.325000 <3>[ 8.098042] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10473 23:43:16.331253 <4>[ 8.106760] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10474 23:43:16.341120 <3>[ 8.111668] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10475 23:43:16.347826 <3>[ 8.115523] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10476 23:43:16.354437 <6>[ 8.116242] mc: Linux media interface: v0.10
10477 23:43:16.361123 <4>[ 8.120906] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10478 23:43:16.371097 <3>[ 8.127178] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10479 23:43:16.377571 <6>[ 8.136988] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10480 23:43:16.384418 <3>[ 8.139706] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10481 23:43:16.394263 <3>[ 8.139713] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10482 23:43:16.401001 <3>[ 8.139717] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10483 23:43:16.411016 <3>[ 8.139758] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10484 23:43:16.417546 <3>[ 8.139802] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10485 23:43:16.427701 <3>[ 8.139805] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10486 23:43:16.434040 <3>[ 8.139807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10487 23:43:16.444332 <3>[ 8.139877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10488 23:43:16.450719 <3>[ 8.139884] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10489 23:43:16.460665 <3>[ 8.139888] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10490 23:43:16.467291 <3>[ 8.139896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10491 23:43:16.474615 <3>[ 8.139902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10492 23:43:16.484190 <3>[ 8.139924] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10493 23:43:16.490809 <6>[ 8.181707] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10494 23:43:16.500623 <6>[ 8.196330] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10495 23:43:16.506960 <6>[ 8.197003] pci_bus 0000:00: root bus resource [bus 00-ff]
10496 23:43:16.513664 <6>[ 8.205617] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10497 23:43:16.520587 <6>[ 8.213020] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10498 23:43:16.531103 <6>[ 8.229088] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10499 23:43:16.537929 <6>[ 8.229191] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10500 23:43:16.547723 <6>[ 8.229339] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10501 23:43:16.554613 <6>[ 8.229390] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10502 23:43:16.561124 <6>[ 8.229403] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10503 23:43:16.567549 <6>[ 8.229466] pci 0000:00:00.0: supports D1 D2
10504 23:43:16.574158 <6>[ 8.229467] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10505 23:43:16.580828 <6>[ 8.230327] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10506 23:43:16.587160 <6>[ 8.230411] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10507 23:43:16.593878 <6>[ 8.230436] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10508 23:43:16.603755 <6>[ 8.230452] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10509 23:43:16.610159 <6>[ 8.230466] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10510 23:43:16.613770 <6>[ 8.230573] pci 0000:01:00.0: supports D1 D2
10511 23:43:16.620530 <6>[ 8.230574] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10512 23:43:16.626612 <6>[ 8.240330] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10513 23:43:16.636802 <4>[ 8.242037] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10514 23:43:16.640022 <4>[ 8.242037] Fallback method does not support PEC.
10515 23:43:16.646756 <6>[ 8.245292] remoteproc remoteproc0: remote processor scp is now up
10516 23:43:16.656714 <6>[ 8.253377] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10517 23:43:16.663496 <3>[ 8.257441] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10518 23:43:16.673204 <6>[ 8.260720] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10519 23:43:16.680120 <6>[ 8.278798] videodev: Linux video capture interface: v2.00
10520 23:43:16.686361 <6>[ 8.286469] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10521 23:43:16.696561 <6>[ 8.286479] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10522 23:43:16.702861 <6>[ 8.302747] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10523 23:43:16.713007 <6>[ 8.308377] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10524 23:43:16.719776 <6>[ 8.308390] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10525 23:43:16.722910 <6>[ 8.308940] Bluetooth: Core ver 2.22
10526 23:43:16.729755 <6>[ 8.309041] NET: Registered PF_BLUETOOTH protocol family
10527 23:43:16.736353 <6>[ 8.309044] Bluetooth: HCI device and connection manager initialized
10528 23:43:16.742679 <6>[ 8.309078] Bluetooth: HCI socket layer initialized
10529 23:43:16.746053 <6>[ 8.309085] Bluetooth: L2CAP socket layer initialized
10530 23:43:16.752199 <6>[ 8.309124] Bluetooth: SCO socket layer initialized
10531 23:43:16.758849 <6>[ 8.318118] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10532 23:43:16.765423 <6>[ 8.323939] pci 0000:00:00.0: PCI bridge to [bus 01]
10533 23:43:16.772582 <6>[ 8.323944] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10534 23:43:16.782296 <3>[ 8.336070] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10535 23:43:16.789076 <6>[ 8.340300] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10536 23:43:16.795272 <6>[ 8.369314] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10537 23:43:16.801871 <6>[ 8.374223] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10538 23:43:16.808753 <6>[ 8.374299] usbcore: registered new interface driver btusb
10539 23:43:16.818767 <4>[ 8.375388] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10540 23:43:16.825157 <3>[ 8.375397] Bluetooth: hci0: Failed to load firmware file (-2)
10541 23:43:16.828539 <3>[ 8.375400] Bluetooth: hci0: Failed to set up firmware (-2)
10542 23:43:16.841426 <4>[ 8.375403] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10543 23:43:16.851357 <6>[ 8.382465] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10544 23:43:16.857969 <6>[ 8.389077] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10545 23:43:16.864692 <6>[ 8.389574] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10546 23:43:16.871490 <6>[ 8.396166] usbcore: registered new interface driver uvcvideo
10547 23:43:16.877761 <5>[ 8.430618] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10548 23:43:16.903467 <5>[ 8.681797] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10549 23:43:16.909903 <5>[ 8.688824] cfg80211: Loaded X.509 cert 'wens: 61c038651aabdcf94bd0ac7ff06c7248db18c600'
10550 23:43:16.919896 <4>[ 8.697234] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10551 23:43:16.923051 <6>[ 8.706109] cfg80211: failed to load regulatory.db
10552 23:43:16.963907 <6>[ 8.742168] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10553 23:43:16.970267 <6>[ 8.749675] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10554 23:43:16.994911 <6>[ 8.776363] mt7921e 0000:01:00.0: ASIC revision: 79610010
10555 23:43:17.097461 <6>[ 8.875897] mt7921e 0000:01:00.0: HW/SW Version: 0x8a108a10, Build Time: 20240219110958a
10556 23:43:17.100690 <6>[ 8.875897]
10557 23:43:17.104109 Begin: Loading essential drivers ... done.
10558 23:43:17.107701 Begin: Running /scripts/init-premount ... done.
10559 23:43:17.113853 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10560 23:43:17.123906 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10561 23:43:17.127415 Device /sys/class/net/eth0 found
10562 23:43:17.127498 done.
10563 23:43:17.133830 Begin: Waiting up to 180 secs for any network device to become available ... done.
10564 23:43:17.171010 IP-Config: eth0 hardware address 00:e0:4c:68:03:bd mtu 1500 DHCP
10565 23:43:17.177426 IP-Config: eth0 complete (dhcp from 192.168.201.1):
10566 23:43:17.184345 address: 192.168.201.16 broadcast: 192.168.201.255 netmask: 255.255.255.0
10567 23:43:17.190642 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10568 23:43:17.197334 host : mt8192-asurada-spherion-r0-cbg-4
10569 23:43:17.204062 domain : lava-rack
10570 23:43:17.206965 rootserver: 192.168.201.1 rootpath:
10571 23:43:17.207056 filename :
10572 23:43:17.270707 done.
10573 23:43:17.277672 Begin: Running /scripts/nfs-bottom ... done.
10574 23:43:17.293176 Begin: Running /scripts/init-bottom ... done.
10575 23:43:17.368363 <6>[ 9.146912] mt7921e 0000:01:00.0: WM Firmware Version: ____010000, Build Time: 20240219111038
10576 23:43:18.604476 <6>[ 10.386500] NET: Registered PF_INET6 protocol family
10577 23:43:18.612317 <6>[ 10.393996] Segment Routing with IPv6
10578 23:43:18.615353 <6>[ 10.398015] In-situ OAM (IOAM) with IPv6
10579 23:43:18.780996 <30>[ 10.536359] systemd[1]: systemd 252.22-1~deb12u1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10580 23:43:18.787364 <30>[ 10.569452] systemd[1]: Detected architecture arm64.
10581 23:43:18.795103
10582 23:43:18.798476 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10583 23:43:18.798559
10584 23:43:18.827549 <30>[ 10.609689] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10585 23:43:19.817211 <30>[ 11.595947] systemd[1]: Queued start job for default target graphical.target.
10586 23:43:19.866813 <30>[ 11.645621] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10587 23:43:19.873610 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10588 23:43:19.895747 <30>[ 11.674551] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10589 23:43:19.905698 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10590 23:43:19.923591 <30>[ 11.702420] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10591 23:43:19.933478 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10592 23:43:19.951365 <30>[ 11.730058] systemd[1]: Created slice user.slice - User and Session Slice.
10593 23:43:19.957833 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10594 23:43:19.982015 <30>[ 11.757448] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10595 23:43:19.991881 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10596 23:43:20.009577 <30>[ 11.784863] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10597 23:43:20.015853 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10598 23:43:20.044187 <30>[ 11.813238] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10599 23:43:20.054723 <30>[ 11.833139] systemd[1]: Expecting device dev-ttyS0.device - /dev/ttyS0...
10600 23:43:20.060881 Expecting device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0...
10601 23:43:20.078302 <30>[ 11.856968] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10602 23:43:20.084823 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10603 23:43:20.106245 <30>[ 11.885080] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10604 23:43:20.116107 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10605 23:43:20.130890 <30>[ 11.913093] systemd[1]: Reached target paths.target - Path Units.
10606 23:43:20.141120 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10607 23:43:20.157966 <30>[ 11.936637] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10608 23:43:20.164263 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10609 23:43:20.178669 <30>[ 11.960573] systemd[1]: Reached target slices.target - Slice Units.
10610 23:43:20.188645 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10611 23:43:20.202918 <30>[ 11.985066] systemd[1]: Reached target swap.target - Swaps.
10612 23:43:20.209558 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10613 23:43:20.230190 <30>[ 12.009063] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10614 23:43:20.240153 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10615 23:43:20.258288 <30>[ 12.037062] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10616 23:43:20.267992 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10617 23:43:20.288580 <30>[ 12.067486] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10618 23:43:20.298532 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10619 23:43:20.315669 <30>[ 12.094555] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10620 23:43:20.325591 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10621 23:43:20.346676 <30>[ 12.125410] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10622 23:43:20.353073 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10623 23:43:20.375333 <30>[ 12.154038] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10624 23:43:20.385077 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10625 23:43:20.404354 <30>[ 12.183168] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10626 23:43:20.414101 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10627 23:43:20.430183 <30>[ 12.209066] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10628 23:43:20.440130 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10629 23:43:20.494192 <30>[ 12.272852] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10630 23:43:20.500615 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10631 23:43:20.522875 <30>[ 12.301628] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10632 23:43:20.529350 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10633 23:43:20.554706 <30>[ 12.333544] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10634 23:43:20.561282 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10635 23:43:20.588921 <30>[ 12.361188] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10636 23:43:20.634521 <30>[ 12.413158] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10637 23:43:20.643955 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10638 23:43:20.667182 <30>[ 12.445985] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10639 23:43:20.673689 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10640 23:43:20.726085 <30>[ 12.505041] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10641 23:43:20.733027 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10642 23:43:20.760775 <30>[ 12.539541] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10643 23:43:20.773927 Starting [0;1;39mmodprobe@drm.service[0m - Load Kerne<6>[ 12.551739] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10644 23:43:20.777172 l Module drm...
10645 23:43:20.826313 <30>[ 12.605087] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10646 23:43:20.835911 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10647 23:43:20.859149 <30>[ 12.637959] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10648 23:43:20.865446 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10649 23:43:20.890100 <30>[ 12.668980] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10650 23:43:20.896672 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10651 23:43:20.904735 <6>[ 12.686951] fuse: init (API version 7.37)
10652 23:43:20.922383 <30>[ 12.701287] systemd[1]: Starting systemd-journald.service - Journal Service...
10653 23:43:20.929049 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10654 23:43:20.978685 <30>[ 12.757541] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10655 23:43:20.985132 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10656 23:43:21.015625 <30>[ 12.791333] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10657 23:43:21.022359 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10658 23:43:21.054693 <3>[ 12.833350] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10659 23:43:21.083115 <30>[ 12.861485] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10660 23:43:21.093251 <3>[ 12.866897] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10661 23:43:21.099783 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10662 23:43:21.123716 <30>[ 12.902052] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10663 23:43:21.133758 <3>[ 12.909029] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10664 23:43:21.140090 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10665 23:43:21.164699 <3>[ 12.943407] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10666 23:43:21.171210 <30>[ 12.945025] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10667 23:43:21.181082 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10668 23:43:21.194237 <3>[ 12.973285] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10669 23:43:21.204613 <30>[ 12.983559] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10670 23:43:21.211270 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10671 23:43:21.224665 <3>[ 13.003709] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10672 23:43:21.234751 <30>[ 13.013764] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10673 23:43:21.241646 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10674 23:43:21.255025 <3>[ 13.034192] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10675 23:43:21.265312 <30>[ 13.044429] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10676 23:43:21.276595 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10677 23:43:21.286168 <3>[ 13.063407] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10678 23:43:21.296183 <30>[ 13.075097] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10679 23:43:21.306091 <30>[ 13.083181] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10680 23:43:21.313042 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - Load Kernel Module configfs.
10681 23:43:21.330692 <30>[ 13.109315] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10682 23:43:21.353930 <30>[ 13.132965] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10683 23:43:21.364139 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10684 23:43:21.382418 <30>[ 13.161363] systemd[1]: Started systemd-journald.service - Journal Service.
10685 23:43:21.389235 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10686 23:43:21.409847 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10687 23:43:21.428541 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10688 23:43:21.448806 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
10689 23:43:21.469632 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
10690 23:43:21.488573 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10691 23:43:21.507303 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
10692 23:43:21.531558 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount R<4>[ 13.311387] power_supply_show_property: 2 callbacks suppressed
10693 23:43:21.541626 <3>[ 13.311399] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10694 23:43:21.555122 <4>[ 13.327313] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10695 23:43:21.565326 <3>[ 13.341117] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10696 23:43:21.571641 <3>[ 13.342945] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10697 23:43:21.574846 oot and Kernel File Systems.
10698 23:43:21.599973 [[0;32m OK [<3>[ 13.375765] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10699 23:43:21.606334 0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10700 23:43:21.623722 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10701 23:43:21.633234 <3>[ 13.410918] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10702 23:43:21.662947 <3>[ 13.441989] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10703 23:43:21.674154 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10704 23:43:21.695926 Mounting [0;1;39msys-kernel-config…e<3>[ 13.474345] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10705 23:43:21.699372 rnel Configuration File System...
10706 23:43:21.730587 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage..<3>[ 13.509236] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10707 23:43:21.730726 .
10708 23:43:21.754629 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10709 23:43:21.764684 <3>[ 13.542067] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10710 23:43:21.778676 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10711 23:43:21.795268 <3>[ 13.574421] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10712 23:43:21.812469 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10713 23:43:21.826467 <3>[ 13.605392] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10714 23:43:21.843075 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10715 23:43:21.866781 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10716 23:43:21.876668 <46>[ 13.654364] systemd-journald[308]: Received client request to flush runtime journal.
10717 23:43:21.887545 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
10718 23:43:21.910673 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
10719 23:43:21.936168 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
10720 23:43:22.010688 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
10721 23:43:23.266628 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
10722 23:43:23.306212 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
10723 23:43:23.326144 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
10724 23:43:23.345644 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
10725 23:43:23.398033 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
10726 23:43:23.420802 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
10727 23:43:23.641732 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
10728 23:43:23.709016 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
10729 23:43:23.785966 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
10730 23:43:24.013128 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
10731 23:43:24.083877 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
10732 23:43:24.102937 <6>[ 15.885168] mt7921e 0000:01:00.0 wlp1s0: renamed from wlan0
10733 23:43:24.112385 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
10734 23:43:24.238614 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
10735 23:43:24.257498 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
10736 23:43:24.277585 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
10737 23:43:24.314241 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
10738 23:43:24.338128 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
10739 23:43:24.390632 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
10740 23:43:24.414843 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
10741 23:43:24.437865 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
10742 23:43:24.458071 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
10743 23:43:24.510712 <46>[ 16.293360] systemd-journald[308]: Time jumped backwards, rotating.
10744 23:43:24.520636 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
10745 23:43:24.544004 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
10746 23:43:24.597335 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
10747 23:43:25.318193 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
10748 23:43:25.645604 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
10749 23:43:25.665730 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
10750 23:43:26.015172 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
10751 23:43:26.036535 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
10752 23:43:26.053235 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
10753 23:43:26.069128 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
10754 23:43:26.087163 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
10755 23:43:26.105159 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
10756 23:43:26.121618 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
10757 23:43:26.158479 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
10758 23:43:26.200080 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
10759 23:43:26.300598 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
10760 23:43:26.334371 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
10761 23:43:26.354188 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
10762 23:43:26.464320 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
10763 23:43:26.503273 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
10764 23:43:26.521006 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
10765 23:43:26.541728 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
10766 23:43:26.562017 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
10767 23:43:26.591121 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
10768 23:43:26.617751 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
10769 23:43:26.637190 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
10770 23:43:26.653431 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
10771 23:43:26.703161 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
10772 23:43:26.747739 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
10773 23:43:26.851812
10774 23:43:26.854867 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
10775 23:43:26.854965
10776 23:43:26.858207 debian-bookworm-arm64 login: root (automatic login)
10777 23:43:26.858289
10778 23:43:27.126424 Linux debian-bookworm-arm64 6.1.92-cip22 #1 SMP PREEMPT Tue Jun 4 23:28:43 UTC 2024 aarch64
10779 23:43:27.126566
10780 23:43:27.133087 The programs included with the Debian GNU/Linux system are free software;
10781 23:43:27.139687 the exact distribution terms for each program are described in the
10782 23:43:27.143120 individual files in /usr/share/doc/*/copyright.
10783 23:43:27.143207
10784 23:43:27.149574 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10785 23:43:27.152860 permitted by applicable law.
10786 23:43:28.109494 Matched prompt #10: / #
10788 23:43:28.110796 Setting prompt string to ['/ #']
10789 23:43:28.111204 end: 2.2.5.1 login-action (duration 00:00:21) [common]
10791 23:43:28.112109 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10792 23:43:28.112519 start: 2.2.6 expect-shell-connection (timeout 00:03:41) [common]
10793 23:43:28.112850 Setting prompt string to ['/ #']
10794 23:43:28.113136 Forcing a shell prompt, looking for ['/ #']
10796 23:43:28.163905 / #
10797 23:43:28.164305 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10798 23:43:28.164635 Waiting using forced prompt support (timeout 00:02:30)
10799 23:43:28.170124
10800 23:43:28.170825 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10801 23:43:28.171172 start: 2.2.7 export-device-env (timeout 00:03:41) [common]
10803 23:43:28.272126 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172914/extract-nfsrootfs-98qg8u54'
10804 23:43:28.278394 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/14172914/extract-nfsrootfs-98qg8u54'
10806 23:43:28.379829 / # export NFS_SERVER_IP='192.168.201.1'
10807 23:43:28.384724 export NFS_SERVER_IP='192.168.201.1'
10808 23:43:28.385101 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10809 23:43:28.385248 end: 2.2 depthcharge-retry (duration 00:01:19) [common]
10810 23:43:28.385423 end: 2 depthcharge-action (duration 00:01:19) [common]
10811 23:43:28.385589 start: 3 lava-test-retry (timeout 00:08:00) [common]
10812 23:43:28.385733 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
10813 23:43:28.385850 Using namespace: common
10815 23:43:28.486275 / # #
10816 23:43:28.486506 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10817 23:43:28.491377 #
10818 23:43:28.491646 Using /lava-14172914
10820 23:43:28.592022 / # export SHELL=/bin/bash
10821 23:43:28.597187 export SHELL=/bin/bash
10823 23:43:28.697711 / # . /lava-14172914/environment
10824 23:43:28.702712 . /lava-14172914/environment
10826 23:43:28.808863 / # /lava-14172914/bin/lava-test-runner /lava-14172914/0
10827 23:43:28.809076 Test shell timeout: 10s (minimum of the action and connection timeout)
10828 23:43:28.813820 /lava-14172914/bin/lava-test-runner /lava-14172914/0
10829 23:43:29.053862 + export TESTRUN_ID=0_timesync-off
10830 23:43:29.056913 + TESTRUN_ID=0_timesync-off
10831 23:43:29.060296 + cd /lava-14172914/0/tests/0_timesync-off
10832 23:43:29.063590 ++ cat uuid
10833 23:43:29.066921 + UUID=14172914_1.6.2.3.1
10834 23:43:29.067041 + set +x
10835 23:43:29.073571 <LAVA_SIGNAL_STARTRUN 0_timesync-off 14172914_1.6.2.3.1>
10836 23:43:29.073854 Received signal: <STARTRUN> 0_timesync-off 14172914_1.6.2.3.1
10837 23:43:29.073955 Starting test lava.0_timesync-off (14172914_1.6.2.3.1)
10838 23:43:29.074087 Skipping test definition patterns.
10839 23:43:29.076766 + systemctl stop systemd-timesyncd
10840 23:43:29.137201 + set +x
10841 23:43:29.140409 <LAVA_SIGNAL_ENDRUN 0_timesync-off 14172914_1.6.2.3.1>
10842 23:43:29.140694 Received signal: <ENDRUN> 0_timesync-off 14172914_1.6.2.3.1
10843 23:43:29.140782 Ending use of test pattern.
10844 23:43:29.140848 Ending test lava.0_timesync-off (14172914_1.6.2.3.1), duration 0.07
10846 23:43:29.204157 + export TESTRUN_ID=1_kselftest-tpm2
10847 23:43:29.207549 + TESTRUN_ID=1_kselftest-tpm2
10848 23:43:29.214122 + cd /lava-14172914/0/tests/1_kselftest-tpm2
10849 23:43:29.214211 ++ cat uuid
10850 23:43:29.217228 + UUID=14172914_1.6.2.3.5
10851 23:43:29.217355 + set +x
10852 23:43:29.220637 Received signal: <STARTRUN> 1_kselftest-tpm2 14172914_1.6.2.3.5
10853 23:43:29.220735 Starting test lava.1_kselftest-tpm2 (14172914_1.6.2.3.5)
10854 23:43:29.220905 Skipping test definition patterns.
10855 23:43:29.224051 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 14172914_1.6.2.3.5>
10856 23:43:29.224137 + cd ./automated/linux/kselftest/
10857 23:43:29.250344 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10858 23:43:29.281572 INFO: install_deps skipped
10859 23:43:29.772024 --2024-06-04 23:43:29-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.92-cip22/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
10860 23:43:29.782040 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
10861 23:43:29.913941 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
10862 23:43:30.044090 HTTP request sent, awaiting response... 200 OK
10863 23:43:30.047309 Length: 1642752 (1.6M) [application/octet-stream]
10864 23:43:30.050614 Saving to: 'kselftest_armhf.tar.gz'
10865 23:43:30.050862
10866 23:43:30.051058
10867 23:43:30.303669 kselftest_armhf.tar 0%[ ] 0 --.-KB/s
10868 23:43:30.561717 kselftest_armhf.tar 2%[ ] 44.98K 173KB/s
10869 23:43:30.895773 kselftest_armhf.tar 13%[=> ] 217.50K 420KB/s
10870 23:43:31.073360 kselftest_armhf.tar 50%[=========> ] 808.57K 950KB/s
10871 23:43:31.079873 kselftest_armhf.tar 100%[===================>] 1.57M 1.52MB/s in 1.0s
10872 23:43:31.079969
10873 23:43:31.224620 2024-06-04 23:43:31 (1.52 MB/s) - 'kselftest_armhf.tar.gz' saved [1642752/1642752]
10874 23:43:31.224770
10875 23:43:35.043139 skiplist:
10876 23:43:35.046594 ========================================
10877 23:43:35.049720 ========================================
10878 23:43:35.093741 tpm2:test_smoke.sh
10879 23:43:35.096965 tpm2:test_space.sh
10880 23:43:35.112903 ============== Tests to run ===============
10881 23:43:35.112989 tpm2:test_smoke.sh
10882 23:43:35.116197 tpm2:test_space.sh
10883 23:43:35.119637 ===========End Tests to run ===============
10884 23:43:35.119722 shardfile-tpm2 pass
10885 23:43:35.220984 <12>[ 27.004932] kselftest: Running tests in tpm2
10886 23:43:35.228248 TAP version 13
10887 23:43:35.241580 1..2
10888 23:43:35.265974 # selftests: tpm2: test_smoke.sh
10889 23:43:36.999299 # test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite) ... ERROR
10890 23:43:37.005880 # test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp) ... ERROR
10891 23:43:37.012420 # Exception ignored in: <function Client.__del__ at 0xffff9938ccc0>
10892 23:43:37.015766 # Traceback (most recent call last):
10893 23:43:37.025874 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10894 23:43:37.025958 # if self.tpm:
10895 23:43:37.028802 # ^^^^^^^^
10896 23:43:37.032295 # AttributeError: 'Client' object has no attribute 'tpm'
10897 23:43:37.039186 # test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth) ... ERROR
10898 23:43:37.045572 # Exception ignored in: <function Client.__del__ at 0xffff9938ccc0>
10899 23:43:37.048913 # Traceback (most recent call last):
10900 23:43:37.058670 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10901 23:43:37.058754 # if self.tpm:
10902 23:43:37.062128 # ^^^^^^^^
10903 23:43:37.065264 # AttributeError: 'Client' object has no attribute 'tpm'
10904 23:43:37.075382 # test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy) ... ERROR
10905 23:43:37.078677 # Exception ignored in: <function Client.__del__ at 0xffff9938ccc0>
10906 23:43:37.081886 # Traceback (most recent call last):
10907 23:43:37.091678 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10908 23:43:37.095242 # if self.tpm:
10909 23:43:37.095325 # ^^^^^^^^
10910 23:43:37.101705 # AttributeError: 'Client' object has no attribute 'tpm'
10911 23:43:37.108331 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth) ... ERROR
10912 23:43:37.114909 # Exception ignored in: <function Client.__del__ at 0xffff9938ccc0>
10913 23:43:37.118290 # Traceback (most recent call last):
10914 23:43:37.128416 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10915 23:43:37.131388 # if self.tpm:
10916 23:43:37.131471 # ^^^^^^^^
10917 23:43:37.138024 # AttributeError: 'Client' object has no attribute 'tpm'
10918 23:43:37.144740 # test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds) ... ERROR
10919 23:43:37.148160 # Exception ignored in: <function Client.__del__ at 0xffff9938ccc0>
10920 23:43:37.151728 # Traceback (most recent call last):
10921 23:43:37.161571 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10922 23:43:37.165300 # if self.tpm:
10923 23:43:37.165385 # ^^^^^^^^
10924 23:43:37.171427 # AttributeError: 'Client' object has no attribute 'tpm'
10925 23:43:37.178031 # test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd) ... ERROR
10926 23:43:37.184588 # Exception ignored in: <function Client.__del__ at 0xffff9938ccc0>
10927 23:43:37.188072 # Traceback (most recent call last):
10928 23:43:37.198044 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10929 23:43:37.198128 # if self.tpm:
10930 23:43:37.201095 # ^^^^^^^^
10931 23:43:37.204373 # AttributeError: 'Client' object has no attribute 'tpm'
10932 23:43:37.214290 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth) ... ERROR
10933 23:43:37.220999 # Exception ignored in: <function Client.__del__ at 0xffff9938ccc0>
10934 23:43:37.224269 # Traceback (most recent call last):
10935 23:43:37.231118 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10936 23:43:37.234389 # if self.tpm:
10937 23:43:37.237768 # ^^^^^^^^
10938 23:43:37.240999 # AttributeError: 'Client' object has no attribute 'tpm'
10939 23:43:37.250918 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy) ... ERROR
10940 23:43:37.254464 # Exception ignored in: <function Client.__del__ at 0xffff9938ccc0>
10941 23:43:37.257601 # Traceback (most recent call last):
10942 23:43:37.268266 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
10943 23:43:37.272414 # if self.tpm:
10944 23:43:37.272495 # ^^^^^^^^
10945 23:43:37.275843 # AttributeError: 'Client' object has no attribute 'tpm'
10946 23:43:37.275925 #
10947 23:43:37.282443 # ======================================================================
10948 23:43:37.292492 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest.test_read_partial_overwrite)
10949 23:43:37.299437 # ----------------------------------------------------------------------
10950 23:43:37.302960 # Traceback (most recent call last):
10951 23:43:37.312392 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
10952 23:43:37.315583 # self.root_key = self.client.create_root_key()
10953 23:43:37.318894 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
10954 23:43:37.332030 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
10955 23:43:37.335470 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
10956 23:43:37.341858 # ^^^^^^^^^^^^^^^^^^
10957 23:43:37.351787 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
10958 23:43:37.355286 # raise ProtocolError(cc, rc)
10959 23:43:37.358563 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
10960 23:43:37.361734 #
10961 23:43:37.365151 # ======================================================================
10962 23:43:37.375100 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest.test_read_partial_resp)
10963 23:43:37.378455 # ----------------------------------------------------------------------
10964 23:43:37.381626 # Traceback (most recent call last):
10965 23:43:37.394955 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10966 23:43:37.395039 # self.client = tpm2.Client()
10967 23:43:37.398259 # ^^^^^^^^^^^^^
10968 23:43:37.407924 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10969 23:43:37.414754 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10970 23:43:37.417951 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
10971 23:43:37.424414 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10972 23:43:37.424498 #
10973 23:43:37.431549 # ======================================================================
10974 23:43:37.437801 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest.test_seal_with_auth)
10975 23:43:37.444889 # ----------------------------------------------------------------------
10976 23:43:37.447558 # Traceback (most recent call last):
10977 23:43:37.457611 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10978 23:43:37.461020 # self.client = tpm2.Client()
10979 23:43:37.464410 # ^^^^^^^^^^^^^
10980 23:43:37.474224 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10981 23:43:37.477570 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10982 23:43:37.484428 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
10983 23:43:37.487774 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10984 23:43:37.487863 #
10985 23:43:37.493938 # ======================================================================
10986 23:43:37.501313 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest.test_seal_with_policy)
10987 23:43:37.507715 # ----------------------------------------------------------------------
10988 23:43:37.510723 # Traceback (most recent call last):
10989 23:43:37.520740 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
10990 23:43:37.523945 # self.client = tpm2.Client()
10991 23:43:37.527277 # ^^^^^^^^^^^^^
10992 23:43:37.537252 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
10993 23:43:37.540792 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
10994 23:43:37.547193 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
10995 23:43:37.553796 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
10996 23:43:37.553882 #
10997 23:43:37.560231 # ======================================================================
10998 23:43:37.567303 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest.test_seal_with_too_long_auth)
10999 23:43:37.573646 # ----------------------------------------------------------------------
11000 23:43:37.577015 # Traceback (most recent call last):
11001 23:43:37.586964 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11002 23:43:37.590487 # self.client = tpm2.Client()
11003 23:43:37.593720 # ^^^^^^^^^^^^^
11004 23:43:37.601835 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11005 23:43:37.608091 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11006 23:43:37.611545 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11007 23:43:37.618467 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11008 23:43:37.618552 #
11009 23:43:37.623538 # ======================================================================
11010 23:43:37.630313 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest.test_send_two_cmds)
11011 23:43:37.637211 # ----------------------------------------------------------------------
11012 23:43:37.640707 # Traceback (most recent call last):
11013 23:43:37.651026 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11014 23:43:37.654585 # self.client = tpm2.Client()
11015 23:43:37.658478 # ^^^^^^^^^^^^^
11016 23:43:37.666052 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11017 23:43:37.672974 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11018 23:43:37.676428 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11019 23:43:37.679681 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11020 23:43:37.682969 #
11021 23:43:37.689613 # ======================================================================
11022 23:43:37.692843 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest.test_too_short_cmd)
11023 23:43:37.699395 # ----------------------------------------------------------------------
11024 23:43:37.702701 # Traceback (most recent call last):
11025 23:43:37.712580 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11026 23:43:37.715801 # self.client = tpm2.Client()
11027 23:43:37.719152 # ^^^^^^^^^^^^^
11028 23:43:37.729038 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11029 23:43:37.735563 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11030 23:43:37.739130 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11031 23:43:37.745500 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11032 23:43:37.745584 #
11033 23:43:37.752267 # ======================================================================
11034 23:43:37.758851 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest.test_unseal_with_wrong_auth)
11035 23:43:37.765482 # ----------------------------------------------------------------------
11036 23:43:37.768751 # Traceback (most recent call last):
11037 23:43:37.779140 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11038 23:43:37.781895 # self.client = tpm2.Client()
11039 23:43:37.785263 # ^^^^^^^^^^^^^
11040 23:43:37.795487 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11041 23:43:37.798588 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11042 23:43:37.805267 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11043 23:43:37.808576 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11044 23:43:37.812397 #
11045 23:43:37.815249 # ======================================================================
11046 23:43:37.824979 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest.test_unseal_with_wrong_policy)
11047 23:43:37.831614 # ----------------------------------------------------------------------
11048 23:43:37.834751 # Traceback (most recent call last):
11049 23:43:37.844731 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11050 23:43:37.848097 # self.client = tpm2.Client()
11051 23:43:37.851588 # ^^^^^^^^^^^^^
11052 23:43:37.861210 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11053 23:43:37.864544 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11054 23:43:37.871359 # ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
11055 23:43:37.874725 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11056 23:43:37.874810 #
11057 23:43:37.881254 # ----------------------------------------------------------------------
11058 23:43:37.884628 # Ran 9 tests in 0.048s
11059 23:43:37.884714 #
11060 23:43:37.887748 # FAILED (errors=9)
11061 23:43:37.891219 # test_async (tpm2_tests.AsyncTest.test_async) ... ok
11062 23:43:37.897697 # test_flush_invalid_context (tpm2_tests.AsyncTest.test_flush_invalid_context) ... ok
11063 23:43:37.897782 #
11064 23:43:37.904439 # ----------------------------------------------------------------------
11065 23:43:37.907595 # Ran 2 tests in 0.035s
11066 23:43:37.907718 #
11067 23:43:37.907803 # OK
11068 23:43:37.910876 ok 1 selftests: tpm2: test_smoke.sh
11069 23:43:37.914298 # selftests: tpm2: test_space.sh
11070 23:43:37.920651 # test_flush_context (tpm2_tests.SpaceTest.test_flush_context) ... ERROR
11071 23:43:37.927562 # test_get_handles (tpm2_tests.SpaceTest.test_get_handles) ... ERROR
11072 23:43:37.934062 # test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc) ... ERROR
11073 23:43:37.940966 # test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces) ... ERROR
11074 23:43:37.941048 #
11075 23:43:37.947381 # ======================================================================
11076 23:43:37.954345 # ERROR: test_flush_context (tpm2_tests.SpaceTest.test_flush_context)
11077 23:43:37.960464 # ----------------------------------------------------------------------
11078 23:43:37.963795 # Traceback (most recent call last):
11079 23:43:37.973895 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11080 23:43:37.977087 # root1 = space1.create_root_key()
11081 23:43:37.980517 # ^^^^^^^^^^^^^^^^^^^^^^^^
11082 23:43:37.990187 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11083 23:43:37.997070 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11084 23:43:38.000128 # ^^^^^^^^^^^^^^^^^^
11085 23:43:38.010465 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11086 23:43:38.013637 # raise ProtocolError(cc, rc)
11087 23:43:38.020712 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11088 23:43:38.020796 #
11089 23:43:38.026795 # ======================================================================
11090 23:43:38.033379 # ERROR: test_get_handles (tpm2_tests.SpaceTest.test_get_handles)
11091 23:43:38.039885 # ----------------------------------------------------------------------
11092 23:43:38.043448 # Traceback (most recent call last):
11093 23:43:38.053224 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11094 23:43:38.056594 # space1.create_root_key()
11095 23:43:38.066338 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11096 23:43:38.073039 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11097 23:43:38.076286 # ^^^^^^^^^^^^^^^^^^
11098 23:43:38.086163 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11099 23:43:38.089407 # raise ProtocolError(cc, rc)
11100 23:43:38.096107 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11101 23:43:38.096193 #
11102 23:43:38.102495 # ======================================================================
11103 23:43:38.109108 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest.test_invalid_cc)
11104 23:43:38.115994 # ----------------------------------------------------------------------
11105 23:43:38.119043 # Traceback (most recent call last):
11106 23:43:38.129130 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11107 23:43:38.132108 # root1 = space1.create_root_key()
11108 23:43:38.135439 # ^^^^^^^^^^^^^^^^^^^^^^^^
11109 23:43:38.145486 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11110 23:43:38.152239 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11111 23:43:38.155596 # ^^^^^^^^^^^^^^^^^^
11112 23:43:38.165765 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11113 23:43:38.168811 # raise ProtocolError(cc, rc)
11114 23:43:38.175603 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11115 23:43:38.175691 #
11116 23:43:38.182200 # ======================================================================
11117 23:43:38.188427 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest.test_make_two_spaces)
11118 23:43:38.195462 # ----------------------------------------------------------------------
11119 23:43:38.198371 # Traceback (most recent call last):
11120 23:43:38.211578 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11121 23:43:38.215133 # root1 = space1.create_root_key()
11122 23:43:38.218587 # ^^^^^^^^^^^^^^^^^^^^^^^^
11123 23:43:38.228285 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11124 23:43:38.234935 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11125 23:43:38.238005 # ^^^^^^^^^^^^^^^^^^
11126 23:43:38.247933 # File "/lava-14172914/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11127 23:43:38.251349 # raise ProtocolError(cc, rc)
11128 23:43:38.257794 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11129 23:43:38.257922 #
11130 23:43:38.264636 # ----------------------------------------------------------------------
11131 23:43:38.264743 # Ran 4 tests in 0.091s
11132 23:43:38.264842 #
11133 23:43:38.267868 # FAILED (errors=4)
11134 23:43:38.271315 not ok 2 selftests: tpm2: test_space.sh # exit=1
11135 23:43:38.552687 tpm2_test_smoke_sh pass
11136 23:43:38.555847 tpm2_test_space_sh fail
11137 23:43:38.621471 + ../../utils/send-to-lava.sh ./output/result.txt
11138 23:43:38.678296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11139 23:43:38.678669 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11141 23:43:38.717633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11142 23:43:38.717936 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11144 23:43:38.760574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11145 23:43:38.760894 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11147 23:43:38.763867 + set +x
11148 23:43:38.767085 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 14172914_1.6.2.3.5>
11149 23:43:38.767341 Received signal: <ENDRUN> 1_kselftest-tpm2 14172914_1.6.2.3.5
11150 23:43:38.767422 Ending use of test pattern.
11151 23:43:38.767497 Ending test lava.1_kselftest-tpm2 (14172914_1.6.2.3.5), duration 9.55
11153 23:43:38.770399 <LAVA_TEST_RUNNER EXIT>
11154 23:43:38.770656 ok: lava_test_shell seems to have completed
11155 23:43:38.770817 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11156 23:43:38.770950 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11157 23:43:38.771050 end: 3 lava-test-retry (duration 00:00:10) [common]
11158 23:43:38.771150 start: 4 finalize (timeout 00:07:50) [common]
11159 23:43:38.771255 start: 4.1 power-off (timeout 00:00:30) [common]
11160 23:43:38.771538 Calling: ['pduclient', '--daemon=localhost', '--hostname=mt8192-asurada-spherion-r0-cbg-4', '--port=1', '--command=off']
11161 23:43:38.847082 >> Command sent successfully.
11162 23:43:38.849633 Returned 0 in 0 seconds
11163 23:43:38.950031 end: 4.1 power-off (duration 00:00:00) [common]
11165 23:43:38.950386 start: 4.2 read-feedback (timeout 00:07:50) [common]
11166 23:43:38.950647 Listened to connection for namespace 'common' for up to 1s
11167 23:43:39.951623 Finalising connection for namespace 'common'
11168 23:43:39.951807 Disconnecting from shell: Finalise
11169 23:43:39.951905 / #
11170 23:43:40.052259 end: 4.2 read-feedback (duration 00:00:01) [common]
11171 23:43:40.052445 end: 4 finalize (duration 00:00:01) [common]
11172 23:43:40.052591 Cleaning after the job
11173 23:43:40.052735 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/ramdisk
11174 23:43:40.055089 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/kernel
11175 23:43:40.065908 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/dtb
11176 23:43:40.066122 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/nfsrootfs
11177 23:43:40.130183 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/14172914/tftp-deploy-758tthvv/modules
11178 23:43:40.136138 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/14172914
11179 23:43:40.700620 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/14172914
11180 23:43:40.700802 Job finished correctly